LSI Package Board needs…
Mutual Communication
Design Consistency
Shorten Development Time
Enabled by

LPB New Standard format
LPB

LPB
LPB

Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 20132013/12/15

Page1

Agenda & Speakers
Introduction
Yoshinori Fukuba TOSHIBALPB Standard Format
Yuji Nakagawa

FujitsuEDA - example of design tool
Kazunari Koga

Zuken

EDA – example of modeling/simulations
Toru Watanabe

ANSYS

Summary : BenefitsYoshinori Fukuba TOSHIBA

LPB
LPB

Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 20132013/12/15

Page2

Introduction of Fukuba• Yoshinori Fukuba– Chief specialist, Design Technology Development dept., Mixed Signal IC
Dev., TOSHIBA corporation Semiconductor & Storage
Today– Chairman JEITA EDA-TC/LSI Package Board(LPB) interoperable design
process WG(LPB-WG)– Chairman IEEE Standard Association, Computer Society, Design
Automation, Project : P2401 LPB-WG

EMC– Secretary IEC SC47A Integrated circuit

LPB
LPB

Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 20132013/12/15

Page3

About LPB-WG
Semiconductor board
Electronic Design Automation TechnicalCommittee

LPB(LSI Package board) interoperable
design process working grouphttp://www.jeita-edatc.com/wg_lpb/home/lpb-en.html•Members• LPB-WG + ex-LPB-WG
Toshiba, Fujitsu semiconductor, Renesas Electronics
Canon, Sony, Panasonic, Denso, Nokia
Fujitsu VLSI, Sony LSI, NEC System Technologies
Toppan NEC Circuit solutions
Zuken, Cadence Japan, Mentor Graphic Japan, StayShift(nimbic)
Fujitsu Advanced Technologies, Gem Design Technologies.
ANSYS, ANSYS Apache, ATE service(Sigrity)
Else,

LPB
LPB

Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 20132013/12/15

Page4

Issues• Product development flow & EMC issues

Product
planning

Circuit
DesignLayoutSI/PI/EMC
Check

Manufactur Compliance-ing/Field Test
EMC
NG

Current

Time consuming, re-design at all=>development cost,
missing business widow

LPB
LPB

Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 20132013/12/15

Page5

Target to improve• How to improve…

Product
planning

Circuit
DesignLayoutSI/PI/EMC
Check

Manufactur Compliance-ing/Field Test

Improve - put check point from early stage,
ＥＭＣ
Ｃｈｅｃｋ
Ｓｉｍ

ＥＭＣ
Ｃｈｅｃｋ
Ｓｉｍ

ＥＭＣ
Ｃｈｅｃｋ
Ｓｉｍ

ＥＭＣ
Ｃｈｅｃｋ
Ｓｉｍ

EMC issues
Free

Reduce iterations=>Time to market

LPB
LPB

Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 20132013/12/15

Page6

Challenge of EMC simulation in design• To estimate simulation time which is allowed in each
design steps
Product
planning

Circuit
DesignLayoutSI/PI/EMC
Check

Manufactur Compliance-ing/Field Test

Allowable Simulation time
0.5
h

1
h

3
h

3
days

1~3
week

Allowable simulation times aredifferent in the development stage.

LPB
LPB

Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 20132013/12/15

Page7

What is the simulation time?
• definition

Simulation time =Parameter collection + setup + calculation
Meeting, e-mail, negotiations

hand mesh, method, hard

Typical TAT
1day

2weeksLPB
LPB

30 hours

time
Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 20132013/12/15

Page8

However…
• Actually …

Product
planning

Circuit
DesignLayoutSI/PI/EMC
Check

Manufactur Compliance-ing/Field Test

Allowable Simulation time
0.5
h

1
h

3
h

3
days

1~3
weeks

EMC simulation cannot be doneat early stage.

LPB
LPB

Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 20132013/12/15

Page9Challenge to reduce the time. But…
Parameter collection

setup calculation

Meeting, e-mail, negotiations

hand mesh, method, hard
X10~ X100
EDA / computer /1day
Academic challenge

2weeksLPB
LPB

supplied by OR tech
Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 20132013/12/15

Page10Still…
• Not enough …

Product
planning

Circuit
DesignLayoutSI/PI/EMC
Check

Manufactur Compliance-ing/Field Test

Allowable Simulation time
0.5
h

1
h

3
h

3
days

1~3
weeks

Still …EMC simulation cannot bedone at early stage.

LPB
LPB

Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 20132013/12/15

Page11

What LPB is trying to achieved?
Parameter collection

setup calculation
1day

2weeks
2weeks

EDA / computer /Academic challenge

Common formats

List of information, exchange format,
common terms & definitions

2d

Extremely shorten
total simulation time

Community / e- commerce

LPB
LPB

time
Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 20132013/12/15

Page12

Reach to the target!
• Finally!

Product
planning

Circuit
DesignLayoutSI/PI/EMC
Check

Manufactur Compliance-ing/Field Test

EMC optimization time
0.5
h

1
h

EMC verification
3
h

3
days

1~3
weeks

EMC simulation can be done
from early stage.

LPB
LPB

Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 20132013/12/15

Page13

Design and Simulation• LPB Standard forma is also effective to shorten design process.

Product
planning

Circuit
DesignLayoutSI/PI/EMC
Check

ＥＭＣ
Ｃｈｅｃｋ
Ｓｉｍ

ＥＭＣ
Ｃｈｅｃｋ
Ｓｉｍ

ＥＭＣ
Ｃｈｅｃｋ
Ｓｉｍ

ＥＭＣ
Ｃｈｅｃｋ
Ｓｉｍ

LPB
LPB

Manufactur Compliance-ing/Field Test

Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 2013

ＥＭＣ finalcheck2013/12/15

Page14

Design and Simulation• LPB Standard forma is also intended to shorten design process.

Product Circ Layplanning uit out

ＥＭＣ
Ｃｈｅｃｋ
Ｓｉｍ

ＥＭＣ
Ｃｈｅｃｋ
Ｓｉｍ

ＥＭＣ
Ｃｈｅｃｋ
Ｓｉｍ

SI/PI/EMC Manufactur
-ing
Check

ＥＭＣ
Ｃｈｅｃｋ
Ｓｉｍ

Compliance/Field Test

ＥＭＣ final
check

Quality + Time to market

LPB
LPB

Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 20132013/12/15

Page15LPB Standard format
JEITA LPB-WG produce LPB Standard
format.
Conceptual design

Design environment to beconstructed by 6 formats,
1.Project Manage (M-Format)
2.Netlist (N-Format)
3.Component (C-Format)
4.Design Rule (R-Format)
5.Geometry (G-Format)
6.Glossary

N-Format

N-Format

N-Format

N-FormatComponent

Optimization
Timing
LVS

C-Format
LSI

PKG

Board

Design Rule
R-Format

Detailed
designDesignfeedback

Project
ManageM-Format

G-FormatSI

Geometry

EMI

PI

Post design analysis

LPB
LPB

Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 20132013/12/15

Page16

Exchange information in supply chain

LPB standard format reveal what the information necessary.
The required information must be shared and are provided in the supply
chain.

LPB
LPB

Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 20132013/12/15

Page17

LPB Community
http://www.lpb-forum.com/

LPB
LPB

Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 20132013/12/15

Page18

International Standardization Plan Standardization Plan
Introduction: DAC2013 2013/6/3-6/5

Submit Project Approval Request(PAR) to IEEE Standard
Association @ 2013 Oct.

Approved project: P2401 LPB-WG
Target IEEE standard/IEC dual logo :2015 June

LPB
LPB

Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 20132013/12/15

Page19EDA venders adoption• More then 10 venders already start to develop LPB
interface.

LPB
LPB

Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 20132013/12/15

Page20LPB Standard Format& Usage example

LPB
LPB

Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 20132013/12/15

Page21LPB Standard Format
Design environment to beconstructed by 6 formats
Conceptual design
N-Format

N-Format

N-Format

N-Format

1. Project Manage (M-Format)

Component

Optimization
Timing
LVS

C-Format

2. Netlist (N-Format)

LSI

PKG

Board

Design Rule

3. Component (C-Format)

Detailed
design4. Design Rule (R-Format)

Project
ManageR-Format

Designfeedback

M-Format

G-Format

5. Geometry (G-Format)

SI

Geometry

6. Glossary

PI

EMI

Post design analysis

LPB
LPB

Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 20132013/12/15

Page22

LPB Standard Format Abstract
FormatAbstract

Benefit

Project
Management(M-Format)

Manage the LPB files of the LSI, package and board.
- Manage the history , revision and update of
the files- JEITA original format using XML

Easy to Manage Design history
Easy to understand Design Status
Understanding The Latest Condition
for Verification

Netlist(N-Format)

Connection of the parts- Netlist between LSI, Package and Board.
- Verilog HDL format

Easy to Check Connection Between LSIPKG-Board
Enable to Simulate on Board Level

Component(C-Format)

Information of the parts that includes- Pin assignment- Design constraint- Design Status- JEITA original format using XML

Easy to Verify for Optimization of LPB
Clarification of Constraint Condition

Design Rule
(R-Format)

Rules of the components that includes- Design rule
- Assembly rule
- Characteristics of the material- JEITA original format using XML

Clarification of Design Rule in Advance
Clarification of Verification Condition
Easy to Set up for Verification

Geometry(G-Format)

Geometry of the Package and Board- XFL format

Efficient Use of Design Property
Use as Reference Design
Easy to convert Data

LPB
LPB

Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 20132013/12/15

Page23

LPB Standard Format Abstract
Project Manage (M-Format)
Abstract

Manage the LPB files of the LSI, package and board.
- Manage the history , revision and update of
the files- JEITA original format using XML

Example<include MFORMAT="MFMT_FKB48.xml" /><include MFORMAT="MFMT_SOC_PKG.xml" /><class comment="DDR MEMORY" ><CFORMAT
file_name="CFMT_DDR.xml" /><RFORMAT
file_name="RFMT_DDR.xml" /><NFORMAT
file_name="NFMT_DDR.v" /><OtherFile file_name="DDRPowerModel.sp" /></class>LPB
LPB

Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 20132013/12/15

Page24

LPB Standard Format Abstract
Netlist (N-Format)
Abstract

Connection of the parts- Netlist between LSI, Package and Board.
- Verilog HDL format

Examplemodule JEITA_SAMPLE ( );wire [23:0] FKBDO ;wire [23:0] FKBDI ;wire VDD33 ; /* PG_NET */wire DGND ; /* PG_NET */FKB48 FKB48 ( .AIN(FKBDO),.AOUT(FKBDI) ) ;SOC_PKG SOC ( .FKBDO(FKBDO), .FKBDI(FKBDI) ) ;endmodule

LPB
LPB

Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 20132013/12/15

Page25LPB Standard Format Abstract
Component (C-Format)
Abstract

Information of the parts that includes- Pin assignment- Design constraint- Design Status- JEITA original format using XML

Example<module name="SOC_PKG" type="PKG" shape_id="PKG_BODY“ ><socket name="SOC_PKG" ><port id="A5"x="-8500"y="12500"
angle="0" name="FKBDO[5]" /><port id="A6"
x="-7500"y="12500"
angle="0" name="FKBDO[2]" /><constraint><impedance group_name=“FKB_DIN" type="single" min="40" typ="50" max="60"/><delaygroup_name="FKB_DIN“ min="100" typ="150" max="200" /></constraint></socket></module>

LPB
LPB

Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 20132013/12/15

Page26

LPB Standard Format Abstract
Design Rule (R-Format)
Abstract

Rules of the components- Design rule
- Assembly rule
- Characteristics of the material- JEITA original format using XML

Example<material_def><conductor material="COPPER" volume_resistivity="1.68e-8" /><dielectric material="FR-4"
permittivity="4.5" tan_delta="0.035" /></material_def><layer_def><layer name="TOP_COND" type="conductor" thickness="0.030“
conductor_material="COPPER" /><layer name="DIELECTRIC12" type="dielectric" thickness="0.100“
dielectric_material="FR-4" /></layer_def><spacing_def><layer name="TOP_COND"><line_to_line space="0.050" /></layer></spacing_def>

LPB
LPB

Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 20132013/12/15

Page27

LPB Standard Format Abstract
Geometry (G-Format)
Abstract

ExampleLPB
LPB

Geometry of the Package and Board- XFL format

shape 1 4 53.2 26.8 90 N
via 1 4 V020C060C085 54.55 20 0 N
via 2 3 B010C050C075C23 41 24.25 0 N
shape 1 11 35.5 29 0 N
via 1 2 B010C030C12 35.5 29 0 N
path 2 0.1 {41 24.25
41.000000 24.750000}

Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 20132013/12/15

Page28

LPB Files Delivery
Die models
IBIS/SPICE
CPM/LPM

PackagemodelsS-paraSPICE
IBIS

C-Format

C-Format

Die Size
Pad location
Spice Modelcorrespondence

Package size
Terminal location
Spice/IBIS/S-para model
correspondence

C-Format
N-Format
Connectivity

Die mountrotation
Flip

C-Format
Packagemount rotation

M-Format
Revision number ofEach N/C/R/G files

LPB
LPB

C-FormatoutlineTerminal location
Simulation model
correspondence

Simulation
model
S-paraSPICE
etc

DesignG-Format
G-Format
PKG routing
PWB Routing/Plane /Bond wire /Plane

Auto set-up
simulation project

Passivecomponents/connectors

R-Format
R-FormatLine/Space
Wire Bonding rules
Via pitch/size/hole
Layer Stuck up
Material parameter

Analysis

Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 20132013/12/15

Page29

LPB sample files for test bench
Analog Signal(SMA x6)

FKB48

DDR3-1600Mbps

SOC PKG
SSTL15
GPIO

DDR

SOC
DIE
SSTL15

DDR

Xtal

TOP

PCIe x4

Passive

Gen.2

Power IC

Component

DetailsSOC

New Design

DDR

generic parts

FKB48

generic parts

Power IC

generic parts

Xtal

generic parts

Passive

generic parts

Edge Finger(Based on LPB Standard Format Ver.2.1)

Golden Sample are provided as a test bench for implementation.

LPB
LPB

Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 20132013/12/15

Page30Reference flow using LPB standard format
LSI Vendor(Package Design) LSI

Electric Products
Maker

Requirement(2) LSI
Outline SPEC.

PKG C2PKG N2(4) PKG Pin
Assignment

PKG C3(6) PKG
Pre Layout

PKG R6(3) Floor Plan

TOP C3
TOP N3(5) Board
Pre Layout

ICs C
ICs N

ICs
DDR, Power IC,
etc.

TOP R

PWB Substrate

TOP N3(7) Pre Layout
Check

TOP C7Discrete C
Discrete N

TOP C5TOP G5

Passive,
Socket,Connector

TOP N7(8) PKG
Final Layout(9) Board
Final Layout

PKG C8PKG G8LPB
LPB

Substrate/
Component
Vendors(1) Block
Diagram

PKG C5PKG C4PKG C6PKG G6

Board Artwork(10) Final
Layout Check

TOP C9TOP G9To understand the functionof the LPB standard format.

Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 20132013/12/15

Page31

Growth of LPB files in design steps
C-Format
HeaderheaderHeaderGlobalunit

Defines the unit

shape

Defines the shape

pad stackPort ID, Coordinate,Defines
the pad stack
Port Name

ModulesocketDefines the input/output ports of the module

port

Defines the port shape, name and locaion

port group

Defines the groupof thegroups
ports
Swappable
Ports/Port

power domain group

Defines the power domain of the signals

swappable port/group

Defines the swappable ports/port groups

frequency

Specifies the operating (clock) frequency for the port

constraint

Component

LPB files will grow every
time you go through theprocess of the design.

Impedance,
Delay,
Skew
Definesthe constraints
for the upper hierarchy

specification

Defines the specification of the module

reference

Defines the connection procedure between ports in socket
section and ports in referenced file.

placement

Defines the placement of the module

Placement Information of the parts

LPB
LPB

［Example］<placement ref_module="SOC" inst="SOC" x="400"y="-6500" /><placement ref_module="DDR" inst="DDR0" x="37000" y="-3200" />Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 20132013/12/15

Page32

<Example> The growth of C-format
<port
<port
<port
<port
<port
<port
<port

<port
<port
<port
<port
<port
<port
<port

id="A3"id="A4"id="A5"id="A6"
id="A7"id="A8"id="A9"id="A3"id="A4"id="A5"id="A6"
id="A7"id="A8"id="A9"x="-10500"
x="-9500"x="-8500"x="-7500"x="-6500"x="-5500"x="-4500"x="-10500"
x="-9500"x="-8500"x="-7500"x="-6500"x="-5500"x="-4500"y="12500"y="12500"y="12500"y="12500"y="12500"y="12500"y="12500"y="12500"y="12500"y="12500"y="12500"y="12500"y="12500"y="12500"

angle="0" />angle="0" />angle="0" />angle="0" />angle="0" />angle="0" />angle="0" />id="A3"id="A4"id="A5"id="A6"
id="A7"id="A8"id="A9"x="-10500"
x="-9500"x="-8500"x="-7500"x="-6500"x="-5500"x="-4500"y="12500"y="12500"y="12500"y="12500"y="12500"y="12500"y="12500"

PKG-C2

Add Name of the port
by Board designer

angle="0" />angle="0" />angle="0" name="FKBDO[3]"angle="0" name="FKBDO[0]"angle="0" />angle="0" />angle="0" name="XTAL1"

普通はここで喧嘩になる。
Dispute?
<port
<port
<port
<port
<port
<port
<port

Coordinate of port
only

direction="out"direction="out"direction="inout" type="signal" />Change the assignment
by Package designer

angle="0" />angle="0" />angle="0" name="FKBDO[5]"angle="0" name="FKBDO[2]"angle="0" />angle="0" name="VDD_PLL"
angle="0" name="XTAL1"

PKG-C3

type="signal" />type="signal" />direction="out"direction="out"

PKG-C4

type="signal" />type="signal" />direction="inout" type="power" />direction="inout" type="signal" />LPB files grow and share the information each other.

LPB
LPB

Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 20132013/12/15

Page33

<Example> The growth of C-format
PKG-C3<!-- Swappable Group --><!-- Swappable Port -->No info. about port swap

PKG-C4<!-- Swappable Group --><swappable_group><ref_portgroup name="FKB_DIN_BYTE0" /><ref_portgroup name="FKB_DIN_BYTE1" /><ref_portgroup name="FKB_DIN_BYTE2" /></swappable_group><!-- Swappable Port --><swappable_port><ref_port name="FKBDO[0]" /><ref_port name="FKBDO[1]" /><ref_port name="FKBDO[2]" /><ref_port name="FKBDO[3]" /><ref_port name="FKBDO[4]" /><ref_port name="FKBDO[5]" /><ref_port name="FKBDO[6]" /><ref_port name="FKBDO[7]" /></swappable_port>

Her is additional
preparation

Add swappable info.
Give the constraint frompackage designer to board
designer

Based on the constraint,
board designer canchange the design

Share the information about constraint and flexibility=> change of design proposal is possible

LPB
LPB

Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 20132013/12/15

Page34Reference Flow
Demonstration

LPB
LPB

Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 20132013/12/15

Page35Reference flow using LPB standard format
LSI Vendor(Package Design) LSI

Electric Products
Maker

Requirement(2) LSI
Outline SPEC.

PKG C2PKG N2(4) PKG Pin
Assignment

PKG C3(6) PKG
Pre Layout

PKG R6(3) Floor Plan

TOP C3
TOP N3(5) Board
Pre Layout

ICs C
ICs N

ICs
DDR, Power IC,
etc.

TOP R

PWB Substrate

TOP N3(7) Pre Layout
Check

TOP C7Discrete C
Discrete N

TOP C5TOP G5

Passive,
Socket,Connector

TOP N7(8) PKG
Final Layout(9) Board
Final Layout

PKG C8PKG G8LPB
LPB

Substrate/
Component
Vendors(1) Block
Diagram

PKG C5PKG C4PKG C6PKG G6

Board Artwork(10) Final
Layout Check

TOP C9TOP G9Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 20132013/12/15

Page36

(5) Board Pre Layout
LPB
formatFloorplan Result.
Tentative pin assignment is done.

Optimize Placement

LPB
formatCritical Path Routing

LPB
LPB

Add the change of floorplan andpin assignment.

Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 20132013/12/15

Page37

(5) Board Pre Layout
Change placement info.

<placement y="-8223.2" x="30206.5" mount="TOP" angle="270" z="200" inst="DDR0" ref_module="DDR"/><placement y="15911.7" x="36947.6" mount="TOP" angle="270" z="200" inst="DDR1" ref_module="DDR"/>TOP C3<placement y="-6500" x="400" mount="TOP" angle="0" z="200" inst="SOC" ref_module="SOC_PKG"/><placement y="22417.2" x="-8150.9" mount="TOP" z="20" inst="GRM1_C1" ref_module="GRM1"/><placement y="23603.4" x="-4479.3" mount="TOP" z="20" inst="GRM1_C2" ref_module="GRM1"/><placement y="-3223.2" x="37206.5" mount="TOP" angle=“90" z="200" inst="DDR0" ref_module="DDR"/><placement y="10911.7" x="30947.6" mount="TOP" angle=“90" z="200" inst="DDR1" ref_module="DDR"/> TOP C5<placement y="-6500" x="400" mount="TOP" angle=“45" z="200" inst="SOC" ref_module="SOC_PKG"/><placement y="22417.2" x="-8150.9" mount=“BOTTOM" z="20" inst="GRM1_C1" ref_module="GRM1"/><placement y="23603.4" x="-4479.3" mount=" BOTTOM " z="20" inst="GRM1_C2" ref_module="GRM1"/>

LPB
LPB

Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 20132013/12/15

Page38(5) Board Pre Layout
Swap pin<port id="R24" type="signal" y="-1500" x="10500" name="DDRDQ[0]" direction="inout"/><port id="R25" type="signal" y="-1500" x="11500" name="DDRDQ[1]" direction="inout"/><port id="R26" type="signal" y="-1500" x="12500" name="DDRDQ[2]" direction="inout"/><port id="P24" type="signal" y=“ -500" x="10500" name="DDRDQ[3]" direction="inout"/><port id="P25" type="signal" y=“ -500" x="11500" name="DDRDQ[4]" direction="inout"/><port id="P26" type="signal" y=“ -500" x="12500" name="DDRDQ[5]" direction="inout"/>

PKG C4<port id="R24" type="signal" y="-1500" x="10500" name="DDRDQ[7]" direction="inout"/><port id="R25" type="signal" y="-1500" x="11500" name="DDRDQ[0]" direction="inout"/><port id="R26" type="signal" y="-1500" x="12500" name="DDRDQ[2]" direction="inout"/><port id=“P24” type=“signal” y=“ -500" x="10500" name="DDRDQ[6]" direction="inout"/><port id=“P25” type=“signal” y=“ -500" x="11500" name="DDRDQ[3]" direction="inout"/><port id=“P26” type=“signal” y=“ -500" x="12500" name="DDRDQ[4]" direction="inout"/>

LPB
LPB

Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 2013

PKG C5

2013/12/15

Page39Simulation Setup
Input for Simulation：
Layout Tools :Zuken Design Force CadenceAPD etc…


Board, Package GeometryTraces, Vias, Pads



Planes, Polygons



etc…

G-Format
Package
Designed by APD

BoardDesigned by Design Force

Extraction Tools :ANSYS etc…
LPB
LPB

ANSYS SIwave, ANSYS HFSS

Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 20132013/12/15

Page40Simulation Setup
Input for Simulation：
Layout Tools :Zuken Design Force CadenceAPD etc…


Passive ComponentsCapacitor(C, ESL, ESR)

C, L, R

Inductor (L)C-Format

Constraints
Skew, Frequency, etc…

Resistor (R)Extraction Tools :ANSYS etc…
LPB
LPB

ANSYS SIwave, ANSYS HFSS

Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 20132013/12/15

Page41

(7) Pre Layout Check
LSI Vendor(Package Design) LSI

Electric Products
Maker

Requirement(2) LSI
Outline SPEC.

PKG C2PKG N2(4) PKG Pin
Assignment

PKG C3(6) PKG
Pre Layout

PKG R6(3) Floor Plan

TOP C3
TOP N3(5) Board
Pre Layout

ICs C
ICs N

ICs
DDR, Power IC,
etc.

TOP R

PWB Substrate

TOP N3(7) Pre Layout
Check

TOP C7Discrete C
Discrete N

TOP C5TOP G5

Passive,
Socket,Connector

TOP N7(8) PKG
Final Layout(9) Board
Final Layout

PKG C8PKG G8LPB
LPB

Substrate/
Component
Vendors(1) Block
Diagram

PKG C5PKG C4PKG C6PKG G6

Board Artwork(10) Final
Layout Check

TOP C9TOP G9Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 20132013/12/15

Page42

(7) Pre Layout Check
Works :
(7) Pre Layout Check【Signal Integrity Simulation of Critical Nets】• Timing Verification of DDRIII 1.3GBps Write Cycle Is Damping Resistors required?
 What is the best ODT setting?

 Estimate the worst skew of DQ

LPB
LPB

Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 20132013/12/15

Page43

(7) Pre Layout Check
Geometry :【Board】【Package】

G-Format

G-Format• Designed by Cadence APD• All nets are completely routed• DQs are NOT isometric• Designed by Zuken Design Force• Only 1.5V Power, Ground, DQS and DQ• DQS and DQs are isometric

ANSYS SIwave
Merged and stacked in Extraction Tool

LPB
LPB

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Page44

(7) Pre Layout Check
Overview of Simulation :【Controller IC】• IC : IBIS Model• Input 666MHz Cycle PRBS to DQ0-7【DDRIII】• IC：IBIS Model• ODT：Test for 30, 40, 60 and 120Ω
DQS, DQ signals in Package and Board Layout / ANSYS SIwave (Extraction Tool)

LPB
LPB

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Page45

(7) Pre Layout Check
Simulation Result :Eye Diagram (ODT：30Ω (FAIL))
DQSTransient Waveform of DQS and DQ0～7

DQ0

Eye Diagram (ODT：60Ω (Best Case))
DQS
DQ0【Worst Skew (Case of ODT=60Ω)】• 42.8ps (DQ5-DQ6)
Eye Diagram and Transient Waveform / ANSYS DesignerSI (Circuit Simulator)

LPB
LPB

Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 20132013/12/15

Page46

(9) Board Final Layout
Import the result of pre layout check• Skew• Decap

LPB
formatRe design to satisfy
the constraints.
• Change pin
assignment• Change decap
Route other signal
Design power/ground

LPB
LPB

Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 20132013/12/15

Page47

(10) Final Layout Check
LSI Vendor(Package Design) LSI

Electric Products
Maker

Requirement(2) LSI
Outline SPEC.

PKG C2PKG N2(4) PKG Pin
Assignment

PKG C3(6) PKG
Pre Layout

PKG R6(3) Floor Plan

TOP C3
TOP N3(5) Board
Pre Layout

ICs C
ICs N

ICs
DDR, Power IC,
etc.

TOP R

PWB Substrate

TOP N3(7) Pre Layout
Check

TOP C7Discrete C
Discrete N

TOP C5TOP G5

Passive,
Socket,Connector

TOP N7(8) PKG
Final Layout(9) Board
Final Layout

PKG C8PKG G8LPB
LPB

Substrate/
Component
Vendors(1) Block
Diagram

PKG C5PKG C4PKG C6PKG G6

Board Artwork(10) Final
Layout Check

TOP C9TOP G9Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 20132013/12/15

Page48

(10) Final Layout Check
Works :
(10) Final Layout Check【Power Integrity Simulation of PDN】
• Input Impedance Analysis of Controller IC and Bypass
Caps Optimization
 Chip-Package-System Total Impedance Bypass Caps Optimization【EMI (Far/Near Field) Simulation】• Far/Near Field analysis induced by Power Noise CISPR 22 Test (Far Field)

LPB
LPB

 Checks Near Field
Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 20132013/12/15

Page49(10) Final Layout Check
Overview of Simulation :Transient Waveform of 1.5V Power (V vs. T)【Controller IC】• IC：CPM (Chip Power Model / Apache RedHawk)• Place Port between 1.5V Power and Ground【Regulator】• DC 1.5V Power Supply【Bypass Capacitors】• 16 Caps for 1.5V Power
Package and Board Layout / ANSYS SIwave (Extraction Tool)

LPB
LPB

Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 20132013/12/15

Page50(10) Final Layout Check
Overview of Simulation :【Bypass Capacitors (Placement)】• 16 Caps are placed between 1.5V Power and Groundnearby Controller and DDRIII

Bypass Caps Placement (Bottom Layer) / ANSYS SIwave (Extraction Tool)

LPB
LPB

Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 20132013/12/15

Page51

(10) Final Layout Check
Simulation Result :Package and Board (G9, C9)Chip, Package and Board (G9, C9 + CPM)
Chip, Package and Board after Optimization (G9, C10 + CPM)

Input Impedance of 1.5V Power on Controller IC / ANSYS SIwave (Extraction Tool)

LPB
LPB

Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 20132013/12/15

Page52

(10) Final Layout Check
Simulation Result :NOT Required!

C-Format
Re-written to optimized list

Board Artwork
Bypass Caps Placement (Bottom Layer) / ANSYS SIwave (Extraction Tool)

LPB
LPB

Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 20132013/12/15

Page53

(10) Final Layout Check

Max. E at 3m

Simulation Result :H-field 1mm above (100MHz)

H-field 1mm above (420MHz)CISPR 22 - Class A
CISPR 22 - Class B

Far Field and Near Field / ANSYS SIwave (Extraction Tool)

LPB
LPB

Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 20132013/12/15

Page54

(10) Final Layout Check
Works :
(10) Final Layout Check【Power Integrity Simulation of PDN】
• Input Impedance Analysis of Controller IC and Bypass
Caps Optimization
 Chip-Package-System Total Impedance ⇒ OK

 Bypass Caps Optimization ⇒ Optimized【EMI (Far/Near Field) Simulation】• Far/Near Field analysis induced by Power Noise CISPR 22 Test (Far Field) ⇒ OK

LPB
LPB

 Checks Near Field ⇒ OK
Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 20132013/12/15

Page55LPB Standard Format
Summary

LPB
LPB

Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 20132013/12/15

Page56

Benefit of LPB format• Quick & Accurate design/simulation set up
 Enable EMC check from development early stage
 No more e-mail/phone call/meetings
 Avoid human error; eliminate hand edit, version
control• Feedback can be done from any parties,
and instantly.
 For optimization/cost down/quality up feed back

• Easy implementation• Human readable, open format XML/Verilog-HDL• XML parser available.
• Simple / light geometry format (G-format:XFL)

LPB
LPB

Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 20132013/12/15

Page57

Join us!
Visit & Support• Poster exhibition in B1 floor small hall
• Visit website “LPB format” ”LPB forum”• Please support International Standard IEEESA P2401

Link Together by LPB standard format

LPB
LPB

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Page58