SPI-NAND

GD5F1GQ5xExxH

GD5F1GQ5xExxH
DATASHEET
1G-bit 2K+64BPageSize with E Version

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Contents

1

FEATURE........................................................................................................................................................... 42

GENERAL DESCRIPTION ............................................................................................................................... 5
2.1

VALID PART NUMBERS ........................................................................................................................................ 6

2.2

CONNECTION DIAGRAM ..................................................................................................................................... 7

2.3

PIN DESCRIPTION ................................................................................................................................................ 8

2.4

BLOCK DIAGRAM ................................................................................................................................................ 83

ARRAY ORGANIZATION ................................................................................................................................. 9

4

MEMORY MAPPING ....................................................................................................................................... 105

DEVICE OPERATION ..................................................................................................................................... 11
5.1

SPI MODES.......................................................................................................................................................... 11

5.2

HOLD MODE ....................................................................................................................................................... 12

5.3

WRITE PROTECTION............................................................................................................................................... 12

5.4

POWER OFF TIMING .............................................................................................................................................. 13

6

COMMANDS DESCRIPTION ......................................................................................................................... 147

WRITE OPERATIONS .................................................................................................................................... 16

8

9

7.1

WRITE ENABLE (WREN) (06H) .............................................................................................................................. 16

7.2

WRITE DISABLE (WRDI) (04H) ............................................................................................................................... 16

READ OPERATIONS ...................................................................................................................................... 17
8.1

PAGE READ .......................................................................................................................................................... 17

8.2

PAGE READ TO CACHE (13H)................................................................................................................................... 18

8.3

READ FROM CACHE (03H OR 0BH) .......................................................................................................................... 19

8.4

READ FROM CACHE X2 (3BH) ................................................................................................................................. 20

8.5

READ FROM CACHE X4 (6BH) ................................................................................................................................. 21

8.6

READ FROM CACHE QUAD I/O DTR (EEH) ............................................................................................................... 22

8.7

READ ID (9FH)..................................................................................................................................................... 23

8.8

READ UID ........................................................................................................................................................... 24

8.9

READ PARAMETER PAGE ......................................................................................................................................... 25

PROGRAM OPERATIONS ............................................................................................................................. 30
9.1

PAGE PROGRAM.................................................................................................................................................... 30

9.2

PROGRAM LOAD (PL) (02H) ................................................................................................................................... 31

9.3

PROGRAM LOAD X4 (PL X4) (32H) .......................................................................................................................... 32

9.4

PROGRAM EXECUTE (PE) (10H) .............................................................................................................................. 33

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9.5

INTERNAL DATA MOVE ........................................................................................................................................... 34

9.6

PROGRAM LOAD RANDOM DATA (84H) .................................................................................................................... 34

9.7

PROGRAM LOAD RANDOM DATA X4 (C4H/34H) ........................................................................................................ 35

10 ERASE OPERATIONS ................................................................................................................................... 36
10.1
11

BLOCK ERASE (D8H) ............................................................................................................................................. 36

RESET OPERATIONS .................................................................................................................................... 37
11.1

SOFT RESET (FFH) ................................................................................................................................................ 37

11.2

ENABLE POWER ON RESET (66H) AND POWER ON RESET (99H) .................................................................................... 38

12 FEATURE OPERATIONS ............................................................................................................................... 39
12.1

GET FEATURES (0FH) AND SET FEATURES (1FH) ......................................................................................................... 39

12.2

STATUS REGISTER AND DRIVER REGISTER.................................................................................................................... 43

12.3

OTP REGION ........................................................................................................................................................ 44

12.4

ASSISTANT BAD BLOCK MANAGEMENT ...................................................................................................................... 45

12.5

BLOCK PROTECTION ............................................................................................................................................... 46

12.6

POWER LOCK DOWN PROTECTION ............................................................................................................................ 47

12.7

INTERNAL ECC...................................................................................................................................................... 48

13 POWER ON TIMING ....................................................................................................................................... 50
14 ABSOLUTE MAXIMUM RATINGS ................................................................................................................ 51
15 CAPACITANCE MEASUREMENT CONDITIONS ........................................................................................ 52
16 DC CHARACTERISTIC .................................................................................................................................. 53
17 AC CHARACTERISTICS ................................................................................................................................ 54
18 PERFORMANCE AND TIMING ..................................................................................................................... 55
19 ORDERING INFORMATION .......................................................................................................................... 57
20 PACKAGE INFORMATION ............................................................................................................................ 58
21 REVISION HISTORY ...................................................................................................................................... 60

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1 FEATURE◆ 1Gb SLC NAND Flash◆

Advanced security Features- 8K-Byte OTP Region◆ Page Size

- 2048 bytes + 64bytes◆ Program/Erase/Read Speed- Page Program time: 400us typical◆Standard, Dual, Quad SPI,DTR- Block Erase time: 3ms typical- Standard SPI: SCLK, CS#, SI, SO, WP#, HOLD#- Page read time: 60us maximum- Dual SPI: SCLK, CS#, SIO0, SIO1, WP#, HOLD#- Quad SPI: SCLK, CS#, SIO0, SIO1, SIO2, SIO3

◆ Low Power Consumption- DTR(Double Transfer Rate) Read : SCLK, CS#, SIO0,- 30mA maximum active current

SIO1, SIO2, SIO3◆

- 50uA maximum standby current

High Speed Clock Frequency◆- 3.3V: 133MHz for fast read with 30pF load

Enhanced access performance- 2Kbyte cache for fast random read- 1.8V: 104MHz for fast read with 30pF load
- 3.3V: Quad I/O Data transfer up to 532 Mbits/s◆ Advanced Feature for NAND

- 1.8V: Quad I/O Data transfer up to 416 Mbits/s- Factory good block0◆ Software/Hardware Write Protection◆ Reliability- Write protect all/portion of memory via software- P/E cycles with ECC: 100K

- Register protection with WP# Pin- Data retention: 10 Years- Power Lock Down Protection◆ Internal ECC◆ Single Power Supply Voltage- 4bits /528byte- Full voltage range for 1.8V: 1.7V ~ 2.0V
- Full voltage range for 3.3V: 2.7V ~ 3.6V

Note: (1). ECC is on default, which can be disable by user.

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2 GENERAL DESCRIPTION
SPI (Serial Peripheral Interface) NAND Flash provides an ultra-cost effective while high density non-volatile memorystorage solution for embedded systems, based on an industry-standard NAND Flash memory core. It is an attractive
alternative to SPI-NOR and standard parallel NAND Flash, with advanced features, Total pin count is 8, including VCC and
GND• Density is 1Gb• Superior write performance and cost per bit over SPI-NOR• Significant low cost than parallel NAND
This low-pin-count NAND Flash memory follows the industry-standard serial peripheral interface, and always remains thesame pin out from one density to another. The command sets resemble common SPI-NOR command sets, modified tohandle NAND specific functions and added new features. GigaDevice SPI NAND is an easy-to-integrate NAND Flashmemory, with specified designed features to ease host management:• User-selectable internal ECC. ECC parity is generated internally during a page program operation. When a pageis read to the cache register, the ECC parity is detected and corrects the errors when necessary. The 64-bytes sparearea is available even when internal ECC enabled. The device outputs corrected data and returns an ECC error status.
• Internal data move or copy back with internal ECC. The device can be easily refreshed and manage garbage
collection task, without need of shift in and out of data.
• Power on Read with internal ECC. The device will automatically read first page of fist block to cache after poweron, then host can directly read data from cache for easy boot. Also the data is promised correct by internal ECC when
ECC enabled.
It is programmed and read in page-based operations, and erased in block-based operations. Data is transferred to or fromthe NAND Flash memory array, page by page, to a data register and a cache register. The cache register is closest to I/O
control circuits and acts as a data buffer for the I/O data; the data register is closest to the memory array and acts as adata buffer for the NAND Flash memory array operation. The cache register functions as the buffer memory to enable pageand random data READ/WRITE and copy back operations. These devices also use a SPI status register that reports thestatus of device operation.

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2.1 VALID PART NUMBERS
Please contact GigaDevice regional sales for the latest product selection and available form factors

Product Number

Density

GD5F1GQ5REYIH

1.7V to 2.0V

GD5F1GQ5REWIH
GD5F1GQ5UEYIH

2.7V to 3.6V

GD5F1GQ5UEWIH
GD5F1GQ5REYFH*
GD5F1GQ5REWFH*
GD5F1GQ5UEYFH*
GD5F1GQ5UEWFH*
GD5F1GQ5REYJH
GD5F1GQ5REWJH
GD5F1GQ5UEYJH
GD5F1GQ5UEWJH

Voltage

1.7V to 2.0V
1Gbit
2.7V to 3.6V

1.7V to 2.0V

2.7V to 3.6V

Package Type

Temperature

WSON8(8*6mm)-40℃ to 85℃

WSON8(6*5mm)-40℃ to 85℃

WSON8(8*6mm)-40℃ to 85℃

WSON8(6*5mm)-40℃ to 85℃

WSON8(8*6mm)-40℃ to 85℃

WSON8(6*5mm)-40℃ to 85℃

WSON8(8*6mm)-40℃ to 85℃

WSON8(6*5mm)-40℃ to 85℃

WSON8(8*6mm)-40℃ to 105℃

WSON8(6*5mm)-40℃ to 105℃

WSON8(8*6mm)-40℃ to 105℃

WSON8(6*5mm)-40℃ to 105℃

Note: (1) Industrial+: F grade has implemented additional test flows to ensure higher product quality than I grade.

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2.2 CONNECTION DIAGRAM
Figure 2-1. Connect Diagram

CS#

1

8

VCC

SO/
SIO1

2

7

HOLD#/
SIO3

WP#/
SIO2

3

6

SCLK

VSS

4

5

SI/
SIO0

Top View

8–LEAD WSON

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2.3 PIN DESCRIPTION
Pin Name

I/O

Description

CS#

I

Chip Select input, active low

SO/SIO1

I/O

Serial Data Output / Serial Data Input Output 1

WP#/SIO2

I/O

Write Protect, active low / Serial Data Input Output 2

VSS

GroundGroundSI/SIO0

I/O

Serial Data Input / Serial Data Input Output 0

SCLK

I

Serial Clock input

HOLD#/SIO3

I/O

Hold Input/Serial Data Input Output 3

VCC

SupplyPower Supply
Not Connect, Not internal connection; can be driven or floated.

NC

2.4 BLOCK DIAGRAM
Figure 2-2. Block Diagram
SCLK

SI/SIO0

SO/SIO1CS#

HOLD#/
SIO3

WP#/
SIO2

Serial NAND controller

Vcc
Vss

Cache
memoryStatus register

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NAND
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3 ARRAY ORGANIZATION
Table 3. Array Organization
Each device has

Each block has

Each page has

128M+4M

128K+4K

2K+64

bytes

1024 x 64

64

-

pages

1024

-

-

blocks

1Gb

Figure 3.Array Organization

Cache Register

2048

64

Data Register

2048

64

IO

1 page= (2K + 64)bytes

1 block = (2K + 64)bytes x 64 pages= (128K + 4K)bytes
Per device:
1G: 1024 Blocks

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1 device:
For 1G: = (128K +4K)bytes x 1024 blocks= 1Gb

1 block

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4 MEMORY MAPPINGFor 1G
BlocksRA<15:6>

0

1

Pages
RA<5:0>

0

1

Bytes
CA<11:0>

0

1

2

1023

63

2

2111

Note:
1.

CA: Column Address. The 12-bit address is capable of addressing from 0 to 4095 bytes; however, only bytes 0
through 2111 are valid. Bytes 2112 through 4095 of each page are “out of bounds,” do not exist in the device,
and cannot be addressed.

2.

RA: Row Address. RA<5:0>selects a page inside a block, and RA<15:6>selects a block.

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5 DEVICE OPERATION
5.1 SPI Modes
SPI NAND supports two SPI modes:• CPOL = 0, CPHA = 0 (Mode 0)• CPOL = 1, CPHA = 1 (Mode 3)
Input data is latched on the rising edge of SCLK and data shifts out on the falling edge of SCLK for both modes. All timing
diagrams shown in this data sheet are mode 0. See Figure 5-1 for more details.
Figure 5-1. SPI Modes Sequence Diagram

CPOL CPHA00 SCLK

1

1

SCLK

SI

MSB

LSB

SO
MSB

CS#

LSB

Note: While CS# is HIGH, keep SCLK at VCC or GND (determined by mode 0 or mode 3). Do not toggle SCLK until CS#
is driven LOW.
We recommend that the user pull CS# to high when user don’t use SPI flash, otherwise the flash is always in the read state,
which is damage for flash.
When CS# is high and SCLK at VCC or GND state, the device is in idle state.
Standard SPISPI NAND Flash features a standard serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select (CS#),
Serial Data Input (SI) and Serial Data Output (SO).
Dual SPISPI NAND Flash supports Dual SPI operation when using the x2 and dual IO commands. These commands allow data to
be transferred to or from the device at two times the rate of the standard SPI. When using the Dual SPI command the SI
and SO pins become bidirectional I/O pins: SIO0 and SIO1.
Quad SPISPI NAND Flash supports Quad SPI operation when using the x4 and Quad IO commands. These commands allow data
to be transferred to or from the device at four times the rate of the standard SPI. When using the Quad SPI command the
SI and SO pins become bidirectional I/O pins: SIO0 and SIO1, and WP# and HOLD# pins become SIO2 and SIO3.

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DTR Quad SPI
The device supports DTR Quad SPI operation when using the “DTR Quad I/O Fast Read” command.
These command allow data to be transferred to or from the device at eight times the rate of the standard SPI, and data
output will be latched on both rising and falling edges of the serial clock. When using the DTR Quad SPI command the SI
and SO pins become bidirectional I/O pins: IO0 and IO1, and WP# and HOLD# pins become IO2 and IO3.

5.2 HOLD Mode
The HOLD# function is only available when QE=0, If QE=1, The HOLD# functions is disabled, the pin acts asdedicated data I/O pin.
The HOLD# signal goes low to stop any serial communications with the device, but doesn’t stop the operation of write
status register, programming, or erasing in progress.
The operation of HOLD, need CS# keep low, and starts on falling edge of the HOLD# signal, with SCLK signal being
low (if SCLK is not being low, HOLD operation will not start until SCLK being low). The HOLD condition ends on rising edgeof HOLD# signal with SCLK being low (If SCLK is not being low, HOLD operation will not end until SCLK being low).
The SO is high impedance, both SI and SCLK don’t care during the HOLD operation, if CS# drives high during HOLD
operation, it will reset the internal logic of the device. To re-start communication with chip, the HOLD# must be at high andthen CS# must be at low.
Figure 5-2. Hold Condition

CS#
SCLK
HOLD#
HOLD

HOLD

5.3 Write Protection
SPI NAND provides Hardware Protection Mode besides the Software Mode. Write Protect (WP#) prevents the block
lock bits (BP0, BP1, BP2 and INV, CMP) from being over written. If the BRWD bit is set to 1 and WP# is LOW, the blockprotect bits cannot be altered.
To enable the Write Protection, the Quad Enable bit (QE) of feature (B0[0]) must be set to 0.

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5.4 Power Off Timing
Please do not turn off the power before Write/Erase operation is complete. Avoid using the device when the battery is
low. Power shortage and/or power failure before Write/Erase operation is complete will cause loss of data and/or damage
to data.

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6 COMMANDS DESCRIPTION
Table 6. Commands Set
Command Name

Byte1

Byte2

Byte3

Byte4

Write Enable

06H

Write Disable

04H

Get Features

0FH

A7-A0

D7-D0

Wrap(8)Set Feature

1FH

A7-A0

D7-D0

Page Read (to cache)

13H

A23-A16

A15-A8A7-A0

Read From Cache

03H/0BH

A15-A8A7-A0(2)

Dummy(1)

D7-D0

A15-A8

A7-A0(2)Dummy(1)

D7-D0

6BH

A15-A8

A7-A0(2)Dummy(1)

D7-D0

EEH

A31-A24

A23-A16

A15-A8

A7-A0(2)Read ID(4)

9FH

Dummy

MID

DID

Read parameter page

13H

00H

00H

04H

Read UID

13H

00H

00H

Program Load

02H

A15-A8Program Load x4

32H

Program Execute

Read From Cache x 2
Read From Cache x 4
Read From Cache Quad I/O
DTR

3BH

Byte5

06H

A7-A0

(3)

D7-D0

Next byte

A15-A8

A7-A0

(3)

D7-D0

Next byte

10H

A23-A16

A15-A8A7-A0

Program Load Random Data

84H(6)

A15-A8

A7-A0(3)

D7-D0

Next byte

Program Load Random Data x4

C4H/34H

A15-A8

A7-A0

(3)

D7-D0

Next byte

Block Erase(128K)

D8H

A23-A16

A15-A8

A7-A0

Reset(5)

FFH

Enable Power on Reset

66h

Power on Reset(7)99h

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Byte6

Dummy
x8(1)

Byte 7

D7-D0

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Note:
1. The dummy has 8 clock.
03H/0BH/3BH/6BH has 1 byte dummy.
EEH has 8 bytes dummy.
2. The A15-A0 (03H/0BH/3BH/6BH) has 16 clock, include 4 clock dummy.
The A31-A0 (EEH) has 4 clock, include 2.5 clock dummy.
3. The A15-A0 has 16 clock, include 4 clock dummy.
4. MID is Manufacture ID (C8h for GigaDevice), DID is Device ID.
5. Reset command:• Reset will reset PAGE READ/PROGRAM/ERASE operation.
• Reset will reset status register bits P_FAIL/E_FAIL/WEL/OIP/ECCS/ECCSE.
6. Those commands are only available in Internal Data Move operation.
7. Power on reset:
Retrieve status register and data in cache to power on status.
8. The output would be updated by real-time, until CS# is driven high.

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7 WRITE OPERATIONS
7.1 Write Enable (WREN) (06H)
The Write Enable (WREN) command is for setting the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL) bit
must be set prior to following operations that change the contents of the memory array:• Page program• OTP program/OTP protection• Block erase
The WEL bit can be cleared after a reset command.
Figure 7-1. Write Enable Sequence Diagram
CS#
SCLK

0

1

2

3

4

5

6

7

CommandSI

06H
High-ZSO

7.2 Write Disable (WRDI) (04H)
The Write Disable command is for resetting the Write Enable Latch (WEL) bit. The WEL bit is reset by following
condition:• Page program• OTP program/OTP protection• Block erase
Figure 7-2. Write Disable Sequence Diagram
CS#
SCLK
SI

SO

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0

1

2

3

4

5

Command04H
High-Z

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8 READ OPERATIONS
8.1 Page Read
The PAGE READ (13H) command transfers the data from the NAND Flash array to the cache register. The commandsequence is as follows:• 13H (PAGE READ to cache)• 0FH (GET FEATURES command to read the status)• 03H or 0BH (Read from cache)/3BH (Read from cache x2)/6BH (Read from cache x4)/EEH(Read from cache DTR
x4)
The PAGE READ command requires a 24-bit address. After the block/page addresses are registered, the device starts
the transfer from the main array to the cache register, and is busy for tRD time. During this time, the GET FEATURE(0FH) command can be issued to monitor the status. Followed the page read operation, the RANDOM DATA READ
(03H/0BH/3BH/6BH/EEH) command must be issued in order to read out the data from cache. When CS# is pulled highthis operation will be terminated. Refer waveforms to view the entire READ operation.
Note: The command 6BH (Read from cache x4)/EEH (Read from cache DTR x4) is only available with the QE enable.

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8.2 Page Read to Cache (13H)
The command page read to cache is read the data from flash array to cache register.
Figure 8-1. Page Read to cache Sequence Diagram
CS#
1

0

SCLK

2

3

4

5

6

8

7

9 10

24-bit address

CommandSI

28 29 30 31

23 22 21

13H

0

1

2

3

High-Z

SO
CS#

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15

SLK
tCS

SI

0FH

SO

High-ZCS#

7
MSB

16 17 18 19 20 21 22 23 24

SCLK
SI

Data byte
SO

7

6

5

4

3

2

1

0

7

MSB

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1 byte address

Get Feature18

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6

5

4

3

2

1

0

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8.3 Read From Cache (03H or 0BH)
The command sequence is shown below.
Figure 8-2. Read From Cache Sequence Diagram

CS#
0

SCLK

1

SI

2

3

4 5

6

9 10 11 12 13 1487Command

Dummy<3:0>

03H or 0BH

00

A11- A03 2

0 0 11 10

22 23

1

0

High-ZSOCS#
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

SCLK
SI

Dummy byte
7SO

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6

5

4

3

2

1

0

7 6
MSB

Data byte 0
5 4 3 2 1

19

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0

Data byte 1
7 6 5
MSB

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8.4 Read From Cache x2 (3BH)
The command sequence is shown below.
Figure 8-3. Read From Cache x2 Sequence Diagram

CS#
0

SCLK

1

2

3

4

5

6

7

Dummy<3:0>

Command

SI/SIO0

9 10 11 12 13 14

8

3BH

0

0 0

22 23

A11-A03

0 11 102

High-Z

SO/SIO1
CS#

24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Dummy byte
SI/SIO0

7

SO/SIO1

6

5

4

3

2

1

0

6

4

2

Data byte 0 Data byte 1
7 5 3 1 7 5 3 1 7

5

3

6

4

2

6

4

MSB

MSB

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0

1

0

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8.5 Read From Cache x4 (6BH)
The Quad Enable bit (QE) of feature (B0[0]) must be set to enable the read from cache x4 command. The commandsequence is shown below.
Figure 8-4. Read From Cache x4 Sequence Diagram
CS#

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14

22 23

SCLK
Command

SI(SIO0)0

SO(SIO1)

High-Z

WP#(SIO2)

High-Z

HOLD#(SIO3)

High-ZCS#

A11- A0

Dummy<3:0>

6BH

0 0

3

0 11 1024 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

SCLK

Dummy byte
6

5

4

3

2

1

0 4

0

4

0

4

0

4

0

4

SO(SIO1)

5

1

5

1

5

1

5

1

5

WP#(SIO2)

6

2

6

2

6

2

6

2

6

HOLD#(SIO3)7 3 7 3 7 3 7 3 7
Byte0 Byte1 Byte2 Byte3

SI(SIO0)

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8.6 Read From Cache Quad I/O DTR (EEH)
The DTR Quad IO command enables Double Transfer Rate throughput on quad I/O of Serial Flash in read mode. A Quad
Enable (QE) bit of status Register must be set to “1” before sending the DTR Quad IO command. The address (interleaveon 4 I/O pins) is latched on both rising and falling edge of SCLK, and data (interleave on 4 I/O pins) shift out on both risingand falling edge of SCLK. The 8-bit address can be latched-in at one clock, and 8-bit data can be read out at one clock,which means four bits at rising edge of clock, the other four bits at falling edge of clock.
The first address Byte can be at any location. The address is automatically increased to the next higher address after each
Byte data is shifted out, so the whole page can be read out at a single DTR Quad IO command. The address counter rolls
over to 0 when the highest address has been reached.
Figure 8-5. Read From Cache Quad I/O DTR Sequence Diagram
CS#
SCLK

0

1

2

3

4

5

6

8

9 10 11Dummy<19:0>

CommandSI(IO0)

7

EEH

19 20

Dummy

0 0 0 0 0 8 4 0

4 0 4 0SO(IO1)0 0 0 0 0 9 5 1

5 1 5 1

IO2

0 0 0 0 0 10 6 2

6 2 6 2

IO3

0 0 0 0 0 11 7 3

A11- A0

Note:
Please contact GigaDevice when there is a need to use the EEh command for DTR.

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8.7 Read ID (9FH)
The READ ID command is used to identify the NAND Flash device.
• With address 00H, the READ ID command outputs the Manufacturer ID and the device ID. See Table 8-1 for details.
Figure 8-6. Read ID Sequence Diagram
CS#

0

SCLK

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15

7

6Command

SI

Dummy

9FH

5

4

3

2

1

High-ZSOCS#

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

SCLK
SI

7

SO

Manufacturer ID
6 5 4 3 2 1

MSB

Device ID

0

7

6

5

4

3

2

MSB

Table 8-1. READ ID Table
Part NoMID

DID1

GD5F1GQ5UExxH

C8H

31H

GD5F1GQ5RExxH

C8H

21H

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00

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8.8 Read UID
The Read Unique ID function is used to retrieve the 16 byte unique ID (UID) for the device. The unique ID when combinedwith the device manufacturer shall be unique.
The UID data may be stored within the Flash array. To allow the host to determine if the UID is without bit errors, the UID
is returned with its complement. If the XOR of the UID and its bit-wise complement is all ones, then the UID is valid. To
accommodate robust retrieval of the UID in the case of bit errors, sixteen copies of the UID and the corresponding
complement are stored by the target. For example, reading bytes 32-63 returns to the host another copy of the UID and its
complement.
Bytes

Value

0-15

UID

16-31

UID complement (bit-wise)

Sequence is as follows:
1.

Use Set Feature command to set B0 register, to enable OTP_EN.

2.

Use Get Feature command to get data from B0 register and check if the OTP_EN is enable.

3.

Use page read to cache (13h) command with address 24’h000006h, read data from array to cache.

4.

Use 0FH (GET FEATURES command) read the status.

5.

User can use Read from cache command (03H/0BH), read 16 bytes UID from cache.
Figure 8-7. Read UID to cache and Get Feature command Sequence Diagram one
CS#
0

SCLK

1

2

SI

3

4

5

6

8

7

9 10

28 29 30 31

Command24-bit address

13H

000006H

High-Z

SO

CS#
0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15

7

6

SLK

tCS

0FH

SO

High-ZCS#

MSB

16 17 18 19 20 21 22 23 24

SCLK

SI
Data byte

SO

7

6

5

4

3

2

1

0

7

MSB

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1 byte address

Get FeatureSI

24

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5

4

3

2

1

0

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GD5F1GQ5xExxH

8.9 Read Parameter Page
The Read Parameter Page function retrieves the data structure that describes the chip’s organization, features, timing andother behavioral parameters. This data structure enables the host processor to automatically recognize the SPI-NAND
Flash configuration of a device. A minimum of three copies of the parameter page are stored in the device. The Read from
Cache command can be used to change the location of data output.
Sequence is as follows:
1.

Use Set Feature command to set B0 register, to enable OTP_EN.

2.

Use Get Feature command to get data from B0 register and check if the OTP_EN is enable.

3.

Use Page Read to Cache (13h) command with address 24’h000004. Load parameter page from array tocache.

4.

Use 0FH (GET FEATURES command) read the status

5.

User can use Read from cache command (03H/0BH), read parameter page from cache.

Figure 8-8. Read parameter page to cache and Get Feature command Sequence Diagram
CS#

0

SCLK

1

2

SI

3

4

5

6

7

8

9 10

28 29 30 31

Command24-bit address

13H

000004H

High-Z

SO

CS#
0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15

7

6

SLK
0FH

MSB

High-ZSOCS#

16 17 18 19 20 21 22 23 24

SCLK
SI

Data byte
SO

7

6

5

4

3

2

1

0

7

MSB

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1 byte address

Get Feature

tCS

SI

25

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4

3

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0

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GD5F1GQ5xExxH

Parameter page table as follow (1G)
Byte

O/M

Description

3.3V/1.8V

0-3

M

Parameter page signature

4FH

Byte 0: 4FH, “O”

4EH

Byte 1: 4EH, “N”

46H

Byte 2: 46H, “F”

49H

Byte 3: 49H, “I”
4-5
6-7

8-9

M
M

M

Revision number

00H

0-15 Reserved (0)00HFeatures supported

00H

0-15 Reserved (0)00H

Reserved (0)

00H
00H

10-31

Reserved (0)

00H
…
00H

Manufacturer Information block
32-43

M

Device manufacturer (12 ASCII characters)“GIGADEVICE

”

47H
49H
47H
41H
44H
45H
56H
49H
43H
45H
20H
20H

44-63

M

Device model (20 ASCII characters)

47H

Device Model

ORGANIZATIONVCC RANGE

44H“GD5F1GQ5U”

X4

2.7v ~ 3.6v

35H

“GD5F1GQ5R”

X4

1.7v ~ 2.0v

46H
31H/
47H
51H
35H
55H/52H
20H
20H
20H
20H
20H
20H

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GD5F1GQ5xExxH
20H
20H
20H
20H
20H

64

M

JEDEC manufacturer ID“C8”

C8H

65-66

O

Date code

00H
00H

67-79

Reserved

00H
00H
00H

Memory organization block
80-83

M

Number of data bytes per page

00H
08H
00H
00H

84-85

M

Number of spare bytes per page

40H
00H

86-89

M

Number of data bytes per partial page

00H
02H
00H
00H

90-91

M

Number of spare bytes per partial page

10H
00H

92-95

M

Number of pages per block

40H
00H
00H
00H

96-99

M

Number of blocks per logical unit (LUN)

00H
04H
00H
00H

100

M

Number of logical units (LUNs)

01H

101

M

Reserved

00H

102

M

Number of bits per cell01H

103-104

M

Bad blocks maximum

14H
00H

105-106

M

Block endurance

01H
05H

107

M

Guaranteed valid blocks at beginning of target

01H

108-109M

Block endurance for guaranteed valid blocks

00H
00H

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110

M

Number of programs per page

04H

111

M

Partial programming attributes

00H

5-7 Reserved
4 1 = partial page layout is partial page data followed by partial page spare
1-3 Reserved
0 1 = partial page programming has constraints
112

M

Number of bits ECC correctability

00H

113

M

Number of interleaved address bits

00H

4-7 Reserved (0)0-3 Number of interleaved address bits
114

O

Interleaved operation attributes

00H

4-7 Reserved (0)3 Address restrictions for program cache
2 1 = program cache supported
1 1 = no block address restrictions
0 Overlapped / concurrent interleaving support
115-127

Reserved

00H
…
00H

Electrical parameters block128

M

I/O capacitance

08H

129-130

M

IO clock support

00H
00H

131-132

O

Reserved (0)

00H
00H

133-134

M

tPROG Maximum page program time (us)

58H
02H

135-136

M

tBERS Maximum block erase time (us)

10H
27H

137-138

M

tR Maximum page read time (us)

3CH
00H

139-140

M

Reserved

00H
00H

141-163

Reserved

00H

Vendor block164-165M

166-253
254-255

M

Vendor specific Revision number

00H

Vendor specific00H

Integrity CRC

Set on test

Redundant parameter pages
256-511

M

Value of bytes 0-255

512-767

M

Value of bytes 0-255

768+

O

Additional redundant parameter pages

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GD5F1GQ5xExxH

Notes:
1.

“O” Stands for Optional, “M” for Mandatory

2.

The Integrity CRC (Cycling Redundancy Check) field is used to verify that the contents of the parameters page were transferredcorrectly to the host. Please refer to ONFI 1.0 specifications for details. The CRC shall be calculated using the following 16-bit
generator polynomial: G(X) = X16 + X15 +X2 + 1，This polynomial in hex may be represented as 8005h.

3．The CRC value shall be initialized with a value of 4F4Eh before the calculation begins. There is no XOR applied to the final CRC value
after it is calculated. There is no reversal of the data bytes or the CRC calculated value.

Device Model

ORGANIZATIONVCC RANGE

CRC value“GD5F1GQ5UxxH”

X4

2.7v ~ 3.6v

F6H/B5H“GD5F1GQ5RxxH”

X4

1.7v ~ 2.0v

2EH/78H

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GD5F1GQ5xExxH

9 PROGRAM OPERATIONS
9.1 Page Program
The PAGE PROGRAM operation sequence programs 1 byte to whole page bytes of data within a page. The page program
sequence is as follows:• 02H (PROGRAM LOAD)/32H (PROGRAM LOAD x4)• 06H (WRITE ENABLE)• 10H (PROGRAM EXECUTE)• 0FH (GET FEATURE command to read the status)
Firstly, a PROGRAM LOAD (02H/32H) command is issued. PROGRAM LOAD consists of an 8-bit Op code, followed by 4
dummy bits and a 12-bit column address, then the data bytes to be programmed. The Program address should be insequential order in a block. The data bytes are loaded into a cache register that is whole page long. If more than one page
data are loaded, then those additional bytes are ignored by the cache register. The command sequence ends when CS#
goes from LOW to HIGH. Figure 9-1 shows the PROGRAM LOAD operation. Secondly, prior to performing the PROGRAMEXECUTE operation, a WRITE ENABLE (06H) command must be issued. As with any command that changes the memory
contents, the WRITE ENABLE must be executed in order to set the WEL bit. If this command is not issued, then the restof the program sequence is ignored.
Note:
1.

The contents of Cache Register doesn’t reset when Program Random Load (84h) command and RESET (FFh)command.

2.

When Program Execute (10h) command was issued just after Program Load (02h) command, the 0xFF is output tothe address that data was not loaded by Program Load (02h) command.

3.

When Program Execute (10h) command was issued just after Program Load Random Data (84h) command, thecontents of Cache Register is output to the NAND.

4.

The Program address should be in sequential order in a block.

5.

Program Load x4 is only available with the QE enable.

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9.2 Program Load (PL) (02H)
The command sequence is shown below.
Figure 9-1. Program Load Sequence Diagram

CS#
0

SCLK

1

2

3

4

5

6

Dummy<3:0>

CommandSI

9 10 11 12 13 14

8

7

0

02H

A11- A00 0 11 10

0

22 23

0

1

2

3

CS#
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

SCLK
SI

7 6
MSB

5

4

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3

Data byte N

Data byte 1

Data byte 0

2

1

0 7

6

5

4

3

2

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9.3 Program Load x4 (PL x4) (32H)
The Program Load x4 command (32H) is similar to the Program Load command (02H) but with the capability to input thedata bytes by four pins: SIO0, SIO1, SIO2, and SIO3. The command sequence is shown below. The Quad Enable bit (QE)of feature (B0[0]) must be set to enable the program load x4 command.
Figure 9-2. Program Load x4 Sequence Diagram
CS#

0

SCLK

1

2

3

4

5

6

7

Command8

9 10 1121 22 23 24 25 26 27 28 29 30 31

Byte 0 Byte1
A11 - A01 0 4 0 4 0 4

0

4

0

SO(SIO1)

5

1

5

1

5

1

5

1

WP#(SIO2)

6

2

6

2

6

2

6

2

HOLD#(SIO3)

7

3

7

3

7

3

7

3

SI(SIO0)

Dummy<3:0>
0 0 0 0 11

32H

CS#

SCLK

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

Byte10Byte11

Byte
N

Byte
N+1

SI(SIO0)

4

SO(SIO1)

5 1

5 1

5 1

5 1

5 1

5 1

5 1

5 1

5 1

5 1

5 1

5 1

WP#(SIO2)

6 2

6 2

6 2

6 2

6 2

6 2

6 2

6 2

6 2

6 2

6 2

6 2

HOLD#(SIO3) 7 3

7 3

7 3

7 3

7 3

7 3

7 3

7 3

7 3

7 3

7 3

7 3

0

4

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0

4

0

4

0

4

0

4

0

4

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0

4

0

4

0

4

0

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0

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GD5F1GQ5xExxH

9.4 Program Execute (PE) (10H)
After the data is loaded, a PROGRAM EXECUTE (10H) command must be issued to initiate the transfer of data from thecache register to the main array. PROGRAM EXECUTE consists of an 8-bit Op code, followed by a 24-bit address. Afterthe page/block address is registered, the memory device starts the transfer from the cache register to the main array, andis busy for tPROG time. This operation shown in Figure 9-3. During this busy time, the status register can be polled tomonitor the status of the operation (refer to Status Register). When the operation completes successfully, the next seriesof data can be loaded with the PROGRAM LOAD command. The command sequence is shown below.
Figure 9-3. Program Execute Sequence Diagram
CS#

0

SCLK

1

2

3

4

5

6

7

8

9 10

CommandSI

28 29 30 31

24-bit address

10H

3

23 22 212

1

0

High-Z

SO
CS#
0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15

SCLK
tCS

0FH

SO

High-ZCS#

Status register address

get feature

SI

7

6

5

4

3

2

1

MSB

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

SCLK
SI

SO

Status register data out

Status register data out

6

7

7
MSB

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0

5

4

3

2

1

0

6

MSB

33

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3

2

1

0

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6

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9.5 Internal Data MoveThe INTERNAL DATA MOVE command sequence programs or replaces data in a page with existing data. The
INTERNAL DATA MOVE command sequence is as follows:• 13H (PAGE READ to cache)• Optional 84H/C4H/34H(PROGRAM LOAD RANDOM DATA)• 06H (WRITE ENABLE)• 10H (PROGRAM EXECUTE)• 0FH (GET FEATURE command to read the status)
Prior to performing an internal data move operation, the target page content must be read out into the cache register by
issuing a PAGE READ (13H) command. The PROGRAM LOAD RANDOM DATA (84H/C4H) command can be issued, if
user wants to update bytes of data in the page. New data is loaded in the 12-bit column address. If the random data is
not sequential, another PROGRAM LOAD RANDOM DATA (84H/C4H) command must be issued with the new column
address. After the data is loaded, the WRITE ENABLE command must be issued, and then PROGRAMEXECUTE (10H)command can be issued to start the programming operation.

9.6 Program Load Random Data (84H)
This command consists of an 8-bit Op code, followed by 4 dummy bits, and a 12-bit column address. New data is loadedin the column address provided with the 12 bits. If the random data is not sequential, then another PROGRAM LOADRANDOM DATA (84H) command must be issued with a new column address, see Figure 9-4 for details. This command is
only available during internal data move sequence.
Figure 9-4. Program Load Random Data Sequence Diagram

CS#
0

SCLK

1

2

3

4

5

CommandSI

6

9 10 11 12 13 14

8

7

A11 - A0

Dummy<3:0>
0 11 10

0 0

0

84H

22 23

0

1

2

3

CS#
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

SCLK
SI

5

4 3

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Data byte N

Data byte 1

Data byte 0

7 6
MSB

2

1

0 7 6

5

4

3

2

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9.7 Program Load Random Data x4 (C4H/34H)
The Program Load Random Data x4 command (C4H/34H) is similar to the Program Load Random Data command (84H)
but with the capability to input the data bytes by four pins: SIO0, SIO1, SIO2, and SIO3. The command sequence is shown
below. The Quad Enable bit (QE) of feature (B0[0]) must be set to enable for the program load random data x4 command.
See Figure 9-5 for details. Those two commands are only available during internal data move sequence.
Figure 9-5. Program Load Random Data x4 Sequence Diagram
CS#

0

SCLK

1

2

3

4

5

6

7

Command
SI(SIO0)

9 10 11 128

22 23 24 25 26 27 28 29 30 31

Dummy<3:0>

C4H/34H0

Byte 0 Byte 1
A11 - A01 0 4 0 4 0 4
0 0 1100

40

SO(SIO1)

5

1

5

1

5

1

5

1

WP#(SIO2)

6

2

6

2

6

2

6

2

HOLD#(SIO3)

7

3

7

3

7

3

7

3

CS#

SCLK

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Byte10Byte11

SI(SIO0)

4

SO(SIO1)

5 1

5 1

5 1

WP#(SIO2)

6 2

6 2

HOLD#(SIO3) 7 3

7 3

0

4

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0

4

0

4

0

4

Byte N

0

4

0

4

5 1

5 1

5

1

5 1

5 1

5 1

5 1

5 1

5 1

6 2

6 2

6 2

6

2

6 2

6 2

6 2

6 2

6 2

6 2

7 3

7 3

7 3

7 3

7 3

7 3

7 3

7 3

7 3

7 3

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0

4

0

4

0

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ERASE OPERATIONS

10.1 Block Erase (D8H)
The BLOCK ERASE (D8H) command is used to erase at the block level. The BLOCK ERASE command (D8H) operates
on one block at a time. The command sequence for the BLOCK ERASE operation is as follows:• 06H (WRITE ENBALE command)• D8H (BLOCK ERASE command)• 0FH (GET FEATURES command to read the status register)Prior to performing the BLOCK ERASE operation, a WRITE ENABLE (06H) command must be issued. As with any
command that changes the memory contents, the WRITE ENABLE command must be executed in order to set the WEL
bit. If the WRITE ENABLE command is not issued, then the rest of the erase sequence is ignored. A WRITE ENABLE
command must be followed by a BLOCK ERASE (D8H) command. This command requires a 24-bit address. After therow address is registered, the control logic automatically controls timing and erase-verify operations. The device is busy
for tBERS time during the BLOCK ERASE operation. The GET FEATURES (0FH) command can be used to monitor the
status of the operation.
Figure 10. Block Erase Sequence Diagram
CS#

0

SCLK

1

2

3

4

5

6

7

8

9 10

CommandSI

28 29 30 31

24-bit address

D8H

3

23 22 212

1

0

High-Z

SO
CS#

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15

SLK

tCS

0FH

SO

High-ZCS#

Status register address

get feature

SI

7

6

5

4

3

2

1

MSB

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

SCLK
SI
SO

Status register data out

Status register data out

6

7

7
MSB

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0

5

4

3

2

1

0

6

MSB

36

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4

3

2

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0

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RESET OPERATIONS

11.1 Soft Reset (FFH)
The RESET (FFH) command stops all operations and the status. For example, in case of a program or erase or read
operation, the reset command can make the device enter the idle state.
Figure 11-1. Reset Sequence Diagram
CS#

0

SCLK

1

2

3

4

5

6

7

Command

SI

FFH
High-Z

SO
CS#

0

1

2

3

4

5

6

8

7

9 10 11 12 13 14 15

SLK
SI

1

2

3

4

5

6

7

0FH

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

SCLK
SI

Status register data out
SO

7
MSB

6

5

4

3

2

1

0

Status register data out
7

6

5

4

3

2

1

0

7

MSB

Note: The Register bit value after soft reset refers to Table 12-2.Register bit Descriptions.

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0

MSB

High-ZSO
CS#

Status register address

get feature

tCS

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11.2 Enable Power on Reset (66H) and Power on Reset (99H)
If the Power on Reset command is accepted, any on-going internal operation will be terminated and the device will return
to its default power-on state and lose all the current feature settings.
The “Enable Reset (66H)” and the “Reset (99H)” commands can be issued in SPI mode. The “Reset (99H)” commandsequence as follow: CS# goes low -> Sending Enable Reset command ->CS# goes high ->CS# goes low.->Sending Resetcommand ->CS# goes high. Once the Reset command is accepted by the device, the device will take approximately tVSL
to reset. During this period, no command will be accepted.
Figure 11-2. Reset Sequence Diagram

CS#
SCLK

0

SI
SO

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1

2

3

4

5

6

7

0

1

2

3

4

5

CommandCommand

66H

99H

High-Z

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12 FEATURE OPERATIONS
12.1 Get Features (0FH) and Set Features (1FH)
The GET FEATURES (0FH) and SET FEATURES (1FH) commands are used to monitor the device status and alter thedevice behavior. These commands use a 1-byte feature address to determine which feature is to be read or modified.
Feature such as OTP can be enabled or disabled by setting specific feature bits (shown in the below table).The status
register is mostly read, except WEL, which is a writable bit with the WRITE ENABLE (06H) command.
When a feature is set, it remains active until the device is power cycled or the feature is written to. Unless otherwise
specified in the following table, once the device is set, it remains set, even if a RESET (FFH) command is issued.
Table 12-1. Features Settings
Register

Addr.

Protection A0H

7

6

5

4

3

2

1

0

BRWD

Reserved

BP2

BP1

BP0

INV

CMP

Reserved

Feature

B0H

OTP_PRT

OTP_EN

Reserved

ECC_EN

BPL

Reserved

Reserved

QE

StatusC0H

Reserved

Reserved

ECCS1

ECCS0

P_FAIL

E_FAIL

WEL

OIP

FeatureD0H

Reserved

DS_IO[1]DS_IO[0]Reserved

Reserved

Reserved

Reserved

Reserved

StatusF0H

Reserved

Reserved

ECCSE1ECCSE0BPS

Reserved

Reserved

Reserved

Note: If BRWD is enabled and WP# is LOW, then the block lock register cannot be changed.
If QE is enabled, the quad IO operations can be executed.
All the reserved bits must be held low when the feature is set.
These registers A0H/B0H/D0H are write/read type, and Registers C0H/F0H are read only.
The OTP_PRT is non-volatile, others bits are volatile.
The Register Bit default value after power-up refers to Table 12-2. Register Bit Descriptions.

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Table 12-2. Status Register Bit Descriptions
Bit

Bit Name

After Power up

After Resetor Power oncommandReset(66H-99H)(FFH)

Description

Block
BRWD

register

Which is used combined with WP#, If BRWD is high0

No Change

write disableBP2

enabled and WP# is LOW, then the Protection registercannot be changed

1

BP1

Block

1

BP0

Protection

1

INV

bits

0

CMP

No Changeused combination, refer to chapter Block Protection

No Changeused combination, refer to chapter OTP Region

0

OTP_PRT

OTP Region

OTP_EN

bits

00
Before OTP Set
The device offers data corruption protection by offering
optional internal ECC. READs and PROGRAMs with

ECC_ENECC Enable
Latchinternal ECC can be enabled or disabled by setting feature
1

No Change

bit ECC_EN. ECC is enabled by default when device
powered on, so the default READ and PROGRAM
commands operate with internal ECC in the “active” state
when ECC enable.
BPL is for Power Lock Down Protection. Once the BPL bit

Block
BPL

Protection
Locksets as 1, the rest of the protection bits BP[0,2] , INV ,0

No Change

default BPL is 0 after power-on-reset and this bit default isregister

QE

The Quad
Enable bit

CMP , BRWD can’t be changed until next power cycle. By
Power Lock Down Protection disable.
This bit indicates that whether the quad IO operations can0

No Change

be executed.
If QE is set to 1, the quad IO operations can be executed.
ECCS provides ECC status as the following table.
ECCS and ECCSE are set to 00b either following a

ECCS1

0

ECCS0

0

ECCSE1ECC Status

ECCSE0Page 0 StatusRESET, or at the beginning of the READ. They are thenupdated after the device completes a valid READ
operation.

0

ECCS and ECCSE are invalid if internal ECC is disabled0(via a SET FEATURES command to reset ECC_EN to 0).
After power-on RESET, ECC status is set to reflect thecontents of block 0, page 0.

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This bit indicates that a program failure has occurred(P_FAIL set to 1). It will also be set if the user attempts to

P_FAIL

Program Fail0

program an invalid address or a protected region,0

including the OTP area. This bit is cleared during the
PROGRAM EXECUTE command sequence or a RESET
command (P_FAIL = 0).
This bit indicates that an erase failure has occurred(E_FAIL set to 1). It will also be set if the user attempts to

E_FAIL

Erase Fail00erase a locked region. This bit is cleared (E_FAIL = 0) at
the start of the BLOCK ERASE command sequence or the
RESET command.
This bit indicates the current status of the write enable
latch (WEL) and must be set (WEL = 1), prior to issuing a

WEL

Write Enable
Latch

0

PROGRAM EXECUTE or BLOCK ERASE command. It is0

set by issuing the WRITE ENABLE command. WEL canalso be disabled (WEL = 0), by issuing the WRITEDISABLE command.
This bit is set (OIP = 1 ) when a PROGRAM EXECUTE,

OIP

Operation In
Progress

0

PAGE READ, BLOCK ERASE, or RESET command is0

executing, indicating the device is busy. When the bit is 0,
the interface is in the ready state.

DS_IO[1]DS_IO[0]DrivenStrengthregister

00

No Change

Block
BPS

Protection

Block protection status
1

No Change

Statushttp://www.elm-tech.com

IO driver strength setting. Default is 00b.

BPS is 1, selected block is protected
BPS is 0, selected block is unprotected.

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Figure 12-1. Get Features Sequence Diagram

CS#
SCLK

0

1

2

3

4

5

SI

CommandSO

High-Z

67

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

1 byte address
6

7

0FH

4

5

3

2

1

0

Data byte

MSB
7

6

5

4

3

2

1

0

MSB

Figure 12-2. Set Features Sequence Diagram

CS#
SCLK

0

1

SI

2

3

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5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

Data byte

1 byte address

Command

1FH
SO

4

7 6
MSB

4

5

3

High-Z

42

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2

1

0

7

MSB

6

5

4

3

2

1

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12.2 Status Register and Driver Register
The NAND Flash device has an 8-bit status register that software can read during the device operation for operation state
query. The status register can be read by issuing the GET FEATURES (0FH)command, followed by the feature address
C0h (see FEATURE OPERATION). The Output Driver Register can be set and read by issuing the SET FEATURE (0FH)
and GET FEATURE command followed by the feature address D0h (see FEATURE OPERATION).
Table 12-3. ECC Error Bits Descriptions
Description

ECCS1

ECCS0

ECCSE1ECCSE000xx

No bit errors were detected during the previous read algorithm

0

1

0

0

Bit errors(=1) were detected and corrected

0

1

0

1

Bit errors (=2) were detected and corrected.

0

1

1

0

Bit errors (=3) were detected and corrected.

0

1

1

1

Bit errors (=4) were detected and corrected.

1

1

x

x

Reserved

1

0

x

x

Bit errors greater than ECC capability(4 bits) and not corrected

Table 12-4. Driver Register Bits Descriptions
DS_IO[1]DS_IO[0]Driver Strength

0

0

100%

0

1

75%

1

0

50%

1

1

25%

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12.3 OTP Region
The serial device offers a protected, One-Time Programmable NAND Flash memory area. 4 full pages are available on thedevice. Customers can use the OTP area any way they want, like programming serial numbers, or other data, for permanentstorage. When delivered from factory, feature bit OTP_PRT is 0. To access the OTP feature, the user must set feature bits
OTP_EN/OTP_PRT by SET FEATURES command. When the OTP is ready for access, pages 00h–03H can be
programmed in sequential order by PROGRAM LOAD (02H) and PROGRAM EXECUTE (10H) commands ( when not yet
protected), and read out by PAGE READ (13H) command and output data by READ from CACHE(03H/0BH/3BH/6BH).
When ECC is enabled, data written in the OTP area is ECC protected.
Table 12-5.OTP States
OTP_PRT

OTP_EN

State

x

0

Normal Operation

0

1

Access OTP region, read and program data

11

1. When the device power on state OTP_PRT is 0, user can set feature bit OTP_PRT and
OTP_EN to 1, then issue PROGRAM EXECUTE (10H) to lock OTP, and after that OTP_PRT
will permanently remain 1.
2. When the device power on state OTP_PRT is 1, user can only read the OTP region data

Note: The OTP space cannot be erased and after it has been protected, it cannot be programmed again, please use thisfunction carefully.
Access to OTP data
• Issue the SET FEATURES command (1FH)• Set feature bit OTP_EN• Issue the PAGE PROGRAM (only when OTP_PRT is 0) or PAGE READ commandProtect OTP region
Only when the following steps are completed, the OTP_PRT will be set and users can get this feature out with 0FH
command.
• Issue the SET FEATURES command (1FH)• Set feature bit OTP_EN and OTP_PRT• 06H (WRITE ENABLE)• Issue the PROGRAM EXECUTE (10H) command.

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12.4 Assistant Bad Block Management
As a NAND Flash, the device may have blocks that are invalid when shipped from the factory, and a minimum number ofvalid blocks (NVB) of the total available blocks are specified. An invalid block is one that contains at least one page thathas more bad bits than can be corrected by the minimum required ECC. Additional bad blocks may develop with use.
However, the total number of available blocks will not fall below NVB during the endurance life of the product.
Although NAND Flash memory devices may contain bad blocks, they can be used reliably in systems that provide badblock management and error-correction algorithms, which ensure data integrity. Internal circuitry isolates each block fromother blocks, so the presence of a bad block does not affect the operation of the rest of the NAND Flash array.
NAND Flash devices are shipped from the factory erased. The factory identifies invalid blocks before shipping by
programming the Bad Block Mark (00h) to the first spare area location in each bad block. This method is compliant with
ONFI Factory Defect Mapping requirements. See the following table for the bad-block mark.
System software should initially check the first spare area location for non-FFH data on the first page of each block prior toperforming any program or erase operations on the NAND Flash device. A bad-block table can then be created, enabling
system software to map around these areas. Factory testing is performed under worst-case conditions. Because invalid
blocks may be marginal, it may not be possible to recover the bad-block marking if the block is erased.
To simplify the system requirement and guard the data integration, GigaDevice SPI NAND provides assistant Management
options as below.
Table 12-6. Bad Block Mark information
Description

Requirement

Minimum number of valid blocks (NVB)

1004

Total available blocks per die

1024First spare area location

Byte 2048

Bad-block mark00h(use non FFH to check)

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12.5 Block Protection
The block lock feature provides the ability to protect the entire device, or ranges of blocks, from the PROGRAM and ERASE
operations. After power-up, the device is in the “locked” state, i.e., feature bits BP0, BP1and BP2 are set to 1, INV, CMP
and BRWD are set to 0. To unlock all the blocks, or a range of blocks, the SET FEATURES command must be issued toalter the state of protection feature bits. When BRWD is set and WP# is LOW, none of the writable protection feature bits
can be set. Also, when a PROGRAM/ERASE command is issued to a locked block, status bit OIP remains 0. When an
ERASE command is issued to a locked block, the erase failure, status bit E_FAIL set to 1. When a PROGRAM commandis issued to a locked block, program failure, status bit P_FAIL set to 1.
To enable the Write Protection (WP#), the Quad Enable bit (QE) of feature (B0[0]) must be set to 0.
Table 12-7. Block Lock Register Block Protect Bits
CMP

INV

BP2

BP1

BP0

Protect Row Address

Protect Rows

x

x

0

0

0

None

None—all unlocked

0

0

0

0

1

FC00h～FFFFH

Upper 1/64 locked

0

0

0

1

0

F800h～FFFFH

Upper 1/32 locked

0

0

0

1

1

F000h～FFFFH

Upper 1/16 locked

0

0

1

0

0

E000h～FFFFH

Upper 1/8 locked

0

0

1

0

1

C000h～FFFFH

Upper 1/4 locked

0

0

1

1

0

8000h～FFFFH

Upper 1/2 locked

x

x

1

1

1

0000h～FFFFH

All locked (default)

0

1

0

0

1

0000h～03FFH

Lower 1/64 locked

0

1

0

1

0

0000h～07FFH

Lower 1/32 locked

0

1

0

1

1

0000h～0FFFH

Lower 1/16 locked

0

1

1

0

0

0000h～1FFFH

Lower 1/8 locked

0

1

1

0

1

0000h～3FFFH

Lower 1/4 locked

0

1

1

1

0

0000h～7FFFH

Lower 1/2 locked

1

0

0

0

1

0000h～FBFFH

Lower 63/64 locked

1

0

0

1

0

0000h～F7FFH

Lower31/32 locked

1

0

0

1

1

0000h～EFFFH

Lower 15/16 locked

1

0

1

0

0

0000h～DFFFH

Lower7/8 locked

1

0

1

0

1

0000h～BFFFH

Lower3/4 locked

1

0

1

1

0

0000h～003FH

Block0

1

1

0

0

1

0400h～FFFFH

Upper 63/64 locked

1

1

0

1

0

0800h～FFFFH

Upper31/32 locked

1

1

0

1

1

1000h～FFFFH

Upper 15/16 locked

1

1

1

0

0

2000h～FFFFH

Upper7/8 locked

1

1

1

0

1

4000h～FFFFH

Upper3/4 locked

1

1

1

1

0

0000h～003FH

Block0

When WP# is not LOW, user can issue bellows commands to alter the protection states as want.
• Issue SET FEATURES register write (1FH)• Issue the feature bit address (A0h) and the feature bits combination as the table

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12.6 Power Lock Down Protection
The Power lock down protection prevent the block protection state from software modifications. After it is enabled, thisprotection cannot be disabled by a software command. Also, BP[0,2] , INV , CMP and BRWD bits are protected from further
software change. Only another power cycle can disable the Power Lock Down Protection.
When the Hardware Protection is disabled during quad or x4 mode, Power Lock Down Protection can be used to preventa block protection state change.
To enable the Power Lock Down Protection, perform the following command sequence:• Issue the SET FEATURES command (with address B0H) to set the feature bit BPL to 1:

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12.7 Internal ECC
The device offers data corruption protection by offering optional internal ECC. READs and PROGRAMs with internal ECC
can be enabled or disabled by setting feature bit ECC_EN. ECC is enabled by default when device powered on, so thedefault READ and PROGRAM commands operate with internal ECC in the “active” state when ECC enable.
To enable/disable ECC, perform the following command sequence:• Issue the SET FEATURES command (1FH) to set the feature bit ECC_EN:
1.

To enable ECC, Set ECC_EN to 1.

2.

To disable ECC, Clear ECC_EN to 0.

During a PROGRAM operation, the device calculates an ECC code on the 2k page in the cache register, before the pageis written to the NAND Flash array.
During a READ operation, the page data is read from the array to the cache register, where the ECC code is calculated
and compared with the ECC code value read from the array. If error bits are detected, the error is corrected in the cacheregister. Only corrected data is output on the I/O bus. The ECC status bit indicates whether or not the error correction was
successful. The ECC Protection table below shows the ECC protection scheme used throughout a page.
The ECC protection format as follow:• User meta data I is not protected by internal ECC and User meta data II is protected by internal ECC.
Any data wrote to the ECC parity data area are ignored when ECC enabled.
Table 12-8. The Distribution of ECC Segment and Spare Area in a Page
Main Area(2KB)

Spare Area(64B)

User data

User meta data(I+II)

Main0

Main1

Main2

Main3

Spare0

Spare1

Spare2

Spare3(512B)(512B)(512B)(512B)(4B+12B)(4B+12B)(4B+12B)(4B+12B)

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Table 12-9. ECC Protection and Spare Area
Max Byte Address

Min Byte Address

ECC Protected

Area

Description

1FFH

000H

Yes

Main 0User data 0

3FFH

200H

Yes

Main 1

User data 1

5FFH

400H

Yes

Main 2User data 2

7FFH

600H

Yes

Main 3User data 3

803H

800H

No

Spare 0User meta 0 data I(1)

80FH

804H

Yes

Spare 0User meta 0 data II

813H

810H

No

Spare 1

User meta 1 data I

81FH

814H

Yes

Spare 1

User meta 1 data II

823H

820H

No

Spare 2User meta 2 data I

82FH

824H

Yes

Spare 2User meta 2 data II

833H

830H

No

Spare 3User meta 3 data I

83FH

834H

Yes

Spare 3User meta 3 data II

Note
1.

800H is reserved for initial bad block mark, and please check the initial bad block mark with internal ECC off.

2.

When Internal ECC is disabled, we recommend the user to provide external ECC protection.

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POWER ON TIMING
Figure 13. Power on Timing Sequence

Vcc(max)

Chip Selection is not allowed
Vcc(min)tVSL

Device is fully
accessible

VWI

Time

Table 13. Power-On Timing and Write Inhibit Threshold for 1.8V/3.3V
SymboltVSL
VWIParameterMin

VCC(min) To CS# Low
Write Inhibit Voltage

http://www.elm-tech.com

Max

1

ms

1.8V

1.4

3.3V

2.5

50

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Unit

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ABSOLUTE MAXIMUM RATINGS
Parameter

Value

Unit

-40 to 85

Ambient Operating Temperature℃-40 to 105

Storage Temperature-65 to 150℃

Applied Input / Output Voltage-0.6 to VCC+0.4

V

VCC(3.3V)-0.6 to 4.0

V

VCC(1.8V)-0.6 to 2.5

V

Figure 14. Input Test Waveform and Measurement Level
Maximum Negative Overshoot Waveform
20ns

Maximum Positive Overshoot Waveform

20ns

20ns

Vss
Vcc + 2.0V

Vss-2.0V
Vcc

20ns

20ns

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CAPACITANCE MEASUREMENT CONDITIONS

SymbolParameter

Min

Typ

Max

Unit

Conditions

CIN

Input Capacitance6

pF

VIN=0V

COUT

Output Capacitance8pF

VOUT=0V

CL

Load Capacitance30

Input Rise And Fall time

pF
5

ns

Input Pulse Voltage

0.1VCC to 0.8VCC

V

Input Timing Reference Voltage

0.2VCC to 0.7VCC

V

Output Timing Reference Voltage

0.5VCCV

Figure 15. Input Test Waveform and Measurement Level

0.8VCC

Input timing reference level

0.1VCC

0.7VCC
0.2VCC

Output timing reference level

AC Measurement Level

Note: Input pulse rise and fall time are<5ns

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DC CHARACTERISTIC(T= -40℃~85℃/ -40℃~105℃, VCC=1.7~2.0V/2.7~3.6V)
SymbolParameter

Test Condition

Min.

Typ

Max.

Unit.

ILI

Input Leakage Current

±10

μA

ILO

Output Leakage Current

±10

μA

ICC1

Standby Current

50

μA

30

mA

30

mA

30

mA

30

mA

CS#=VCC,
VIN=VCC or VSS
CLK=0.1VCC / 0.9VCC
at 133MHz,

ICC2

Operating Current (Read)

Q=Open(*1*2,*4 I/O)
CLK=0.1VCC / 0.9VCC
at 104MHz,
Q=Open(*1,*2,*4 I/O)

ICC3
ICC4

Operating Current(Program)
Operating Current(Erase)VIL

Input Low Voltage-0.5

0.2VCCV

VIH

Input High Voltage

0.8VCC

VCC+0.4

V

VOL

Output Low Voltage

IOL =1.6mA

0.4

V

VOH

Output High Voltage

IOH =-100μA

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AC CHARACTERISTICS(T= -40℃~85℃/ -40℃~105℃, VCC=1.7~2.0V/2.7~3.6V, CL=30pf)
SymbolFC1
FC_DDR

1.8V

Parameter

Min.

3.3V
Max.

Min.

Max.

Unit.

Serial Clock Frequency

104

133

MHz

Serial Clock Frequency For: DDR

50

70

MHz

tCH

Serial Clock High Time

4

3.375

ns

tCL

Serial Clock Low Time

4

3.375

ns

tCLCH

Serial Clock Rise Time (Slew Rate)

0.2

0.2

V/ns

tCHCL

Serial Clock Fall Time (Slew Rate)

0.2

0.2

V/ns

tCHSH

CS# Active Hold Time

5

5

ns

tSHCH

CS# Not Active Setup Time

5

5

ns

tSLCH

CS# Active Setup Time

6

5

ns

tCHSL

CS# Not Active Hold Time

5

5

ns

CS# High Time

20

20

ns

tSHSL/tCS
tSHQZ

Output Disable Time

20

tCLQX

Output Hold Time

2

2

ns

tDVCH

Data In Setup Time

2

2

ns

tCHDX

Data In Hold Time

2

2

ns

tHLCH

Hold# Low Setup Time (relative to Clock)

5

5

ns

tHHCH

Hold# High Setup Time (relative to Clock)

5

5

ns

tCHHL

Hold# High Hold Time (relative to Clock)

5

5

ns

tCHHH

Hold# Low Hold Time (relative to Clock)

5

5

ns

tHLQZ

Hold# Low To High-Z Output

15

15

ns

tHHQX

Hold# High To Low-Z Output

15

15

ns

tCLQV

Clock Low To Output Valid

9.5

7

ns

tWHSL

WP# Setup Time Before CS# Low

20

20

ns

tSHWL

WP# Hold Time After CS# High

100

100

ns

Note:
Please contact GigaDevice when there is a need to use the EEh command for DTR.

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PERFORMANCE AND TIMING
SymbolParameter

Min.

Typ.

Max.

Unit.

tRST

CS# High To Next Command After Reset(FFh)

500

us

tRD

Read From Array25

ustRD_ECC

Read From Array with ECC

45

60

us

tPROG

Page Programming Time

300

600

us

tPROG_ECC

Page Programming Time with ECC

400

600

us

tBERS

Block Erase Time

3

10

ms

Figure 18-1. Serial Input Timing
tSHSL

CS#

tCHSL
SCLK

tSLCH

tDVCH

tCHSH

tSHCH
tCHCL

tCLCH

tCHDX

LSB

SI

MSB

SO

High-Z

Figure 18-2. Output Timing

CS#

tCH

SCLK
tCLQV
tCLQX

tCLQV

tCL

tCLQX

SO

LSB

SI
Least significant address bit (LIB) in

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55

Rev.1.1

tSHQZ

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GD5F1GQ5xExxH

Figure 18-3. Hold Timing
CS#
tCHHL

SCLK

tHLCH
tCHHH

tHLQZ

SO

HOLD#

SI do not care during HOLD operation.

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56

Rev.1.1

tHHCH

tHHQX

SPI-NAND

19

GD5F1GQ5xExxH

ORDERING INFORMATIONGD XX XX XX X X X X X X
Packing TypeT or No mark: Tube
R: Tape & Reel
Y: Tray

GD Prefix

Green Code
G: Pb Free & Halogen Free Green
Package + Full Spare Size
H: Pb Free & Halogen Free Green
Package + Half Spare Size
Temperature Range
I : Industrial(-40℃ to +85℃)
F : Industrial+(1)(-40℃ to +85℃)
J : Industrial(-40℃ to +105℃)
Package Type
Y: WSON8 8*6mm
W: WSON8 6*5mm

Generation
E: E Version

Voltage
U:3.3V(2.7~3.6V)
R:1.8V(1.7~2.0V)

Serial
Q5 Serial
Density
1G: 1Gb
Product Family
5F: SPI NAND Flash
Note: (1) Industrial+: F grade has implemented additional test flows to ensure higher product quality than I grade.

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Rev.1.1

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20

GD5F1GQ5xExxH

PACKAGE INFORMATION
Figure 20-1. WSON8 (8*6mm)

c

D

E

A1

Top View

L

A
Side View

b

E2

e

D2
Bottom View
Dimensions
Symbol

A

A1

c

b

D

D2

E

E2

Min

0.70

0.00

0.180

0.35

7.90

3.30

5.90

4.20

Nom

0.75

0.02

0.203

0.40

8.00

3.40

6.00

4.30

Max

0.80

0.05

0.250

0.45

8.10

3.50

6.05

4.40

0.55

Min

0.028

0

0.007

0.014

0.311

0.130

0.232

0.165

0.018

Nom

0.030

0.001

0.008

0.016

0.315

0.134

0.236

0.169

Max

0.032

0.002

0.010

0.018

0.319

0.138

0.238

0.173

Unit
mm

Inch

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Rev.1.1

e

L
0.45

1.27

0.05

0.50

0.020
0.022

SPI-NAND

GD5F1GQ5xExxH

Figure 20-2. WSON8 (6*5mm)

c

D

E

A1

Top View

A

L

Side View

b
E2

e

D2
Bottom View
Dimensions
Symbol

A

A1

c

b

D

D2

E

E2

Min

0.70

0.00

0.180

0.35

5.90

3.30

4.90

3.90

Nom

0.75

0.02

0.203

0.40

6.00

3.40

5.00

4.00

Max

0.80

0.05

0.250

0.45

6.10

3.50

5.10

4.10

0.75

Min

0.028

0

0.007

0.014

0.232

0.130

0.193

0.154

0.020

Nom

0.030

0.001

0.008

0.016

0.236

0.134

0.197

0.157

Max

0.032

0.002

0.010

0.018

0.240

0.138

0.201

0.161

Unit
mm

Inch

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Rev.1.1

e

L
0.50

1.27

0.05

0.60

0.024
0.030

SPI-NAND

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21 REVISION HISTORY
Version No
1.0
1.1

Description

Page

Initial Release2020-05-08

Release Industrial 105° and Industrial+ 85° productUpdate 105° test condition

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Date

6
53/54

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Rev.1.1

2020-06-11