Paralleling Power MOSFETs
for Switching Applications
AND90108/D
Introduction

In high current applications, a beneficial characteristic of power
MOSFETs is the ability to parallel devices to increase current
conduction and power switching capacity. Numerous authors havetreated this topic in the open technical literature [1−7] as well as
manufacturer's application notes [8] and data books [11]. The reader isguided to these references for very fine in−depth treatment in addition
to this application note.
The fundamental consideration when designing a system to employ
parallel MOSFETs is to maintain balance among the device junction
temperatures and to keep all within the maximum rating of the device
as given in the manufacturer's data sheet, e.g., [9]. As is well−known,safe and reliable operation of the MOSFET is a function of its thermal
state, which in turn is determined by the coupled interaction of device
losses and the thermal management system while operating according
the usage profile of the application. Total losses consist of conduction
and switching losses, which are driven primarily by the magnitude ofthe drain current and switching frequency. However, many factors
contribute to how well such losses are shared by the paralleled
MOSFETs, both statically and dynamically [1, 5, 7].
Equal sharing of current and losses among devices is important in allof the modes in which MOSFETs may operate, including:• Fully on" during static conditions• Switching transients (turn−on and turn−off) and pulsed conditions• Linear mode" (more precisely, “saturation mode”) operationwww.onsemi.com

APPLICATION NOTEThis application note provides guidance on how safely to operate
power MOSFETs in parallel in switching applications. For moregeneral guidance, refer to [7, 8, & 11].
Key Take−Aways for Paralleing MOSFETs• Successful paralleling of MOSFETs is achievable and is routinely

done without extraordinary or costly measures by careful layout andcircuit design.
• Thermal mismatch will exacerbate parameter mismatch issues andis best addressed by using a common heatsink for all paralleled
MOSFETs comprising the switch.
• Control stray circuit elements, especially inductance, by balanced
and compact circuit layout.
• Switch as fast as possible while watching for EMI issues (ringing)and keeping common source inductance for all MOSFETs asbalanced and minimal as possible to keep dynamic current sharing
as even as possible.
• Use a dedicated, distributed gate resistor for each MOSFET, closely
coupled to the device terminal, to provide damping (decoupling) of
any gate oscillations that may arise in the low impedance loops
between the Cgd of devices.

© Semiconductor Components Industries, LLC, 2021

May, 2021 − Rev. 0

1

Figure 1. Example Half−Bridge Test PCB
with 4 Paralleled D2PAK−7L
Silicon−Carbide MOSFETs per Switch
Publication Order Number:AND90108/D

AND90108/D• Avoid the costly practice of matching parameters

minimize the differences in both case and junction
temperature. Before a worst case example of these concepts
can be examined, some knowledge of the range of thevariation of RDS(on) within production devices must be
obtained.
Invariably (from any manufacturer) there will be at leasta slight mismatch in paralleled MOSFET's RDS(on), even at
the same current and case temperature, due to process andmanufacturing variation, leading to individual drain current
imbalance. The worst case situation is obviously theparalleling of devices with the widest possible variation in
RDS(on). A representative example of variation in RDS(on)taken from final test data on more than 1500 samples ofa given part number is shown in Figures 2 and 3.

(binning) and rely on good circuit board layout andnominal device selection to give some margin inallowable switching and conduction losses.
• Avoid extra gate circuitry such as external capacitanceand Zener diodes for protection as these tend to slow
down switching and induce oscillations, leading to higher
switching losses and greater imbalance from MOSFET to
MOSFET.
• When evaluating avalanche operation, e.g. during highcurrent, high speed switching, keep avalanche current ator below what can be handled by a single MOSFET sinceavalanche current sharing during very short transients isdifficult to ensure, likely resulting in the die with lowest
BVAV taking most or all of the avalanche energy.
Static Current Sharing Design Considerations

Although increasing junction temperature raises the on
resistance and the conduction losses of the power MOSFET,
definite benefits are attributable to the positive temperature
coefficient of RDS(on). If a portion of the chip begins to hog
current, the localized temperature will increase, causing
a corresponding increase in the RDS(on) of that portion of thechip, and current will shift away to the cooler, less active,
portions of the die. This trait accounts for the tendency of thedevice to share current over the entire surface of the die’s
active region. Because current crowding and hot−spotting
are eliminated under normal operating conditions, there isno need to de−rate power MOSFETs to guard against
secondary breakdown. The argument supporting current
sharing within a device, due to the positive temperature
coefficient of RDS(on), is easily extended to the case ofparalleled devices. As within a single device with some
imbalance in RDS(on) over the die’s active area, an imbalanceor mismatch of RDS(on) between devices will cause an initial
current loading imbalance between devices. The resulting
rise in junction temperature and on−resistance of the device
with the lowest RDS(on) will decrease that device’s draincurrent and will establish a more equal distribution of thetotal load current in all paralleled devices.
While this tendency is definitely observable andbeneficial, its influence on the degree of current sharing isoften overstated. In the power MOSFET, the current sharing
mechanism is not triggered simply by high junction
temperature, but by the difference in TJ between the low andhigh RDS(on) devices. Due to the generally small thermal
coefficient of RDS(on), a substantial difference in junction
temperature would need to develop to drive a reasonablelevel of current sharing.
Since the ultimate concern is for optimum reliability, theemphasis should not be placed on obtaining large deltas in
TJ to force a greater degree of current sharing; rather, theeffort should be focused on decreasing TJ of the hottest
device. This is accomplished by close thermal coupling of
the paralleled devices, provided that the total heat sinking
capability is not compromised by doing so. This will tend to

Figure 2. Representative Variation Trend

Figure 3. Representative Variation Distribution

Table 1 shows the min, max, median, and delta from thisdataset, as well as the data sheet entries for the same part[10]. As is frequently the case, data sheet values for min andmax are significantly wider than what is found withinwww.onsemi.com
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AND90108/D
normal process variation, and the user may be prudent tomake use of the data sheet information for added margin in
his design. From this information, one will have to design fora worst case RDS(on) mismatch in the range of 15 to 25%.

more evenly over time. This simulation was run for a targetof 300 A per device, which is the max ID value from the data
sheet [9].
In the prior exercise, we looked at on resistance variationin isolation. Now we examine the case where thermal
impedance from case to ambient is included.

Table 1. REPRESENTATIVE VARIATION LIMITS OFRDS(ON)
Final Test

Data Sheet

Max

1.183

1.4

Typ (Median)

1.100

1.1

RDS(on), mW

Min

1.036

Tj

10

0.3

Percent Variation

13.4%

27.3%

Tcase

R12

TJNOM

TC
Vds_nom

N
TJNOM

TJNOM

TJMIN

I_Low
Tj

TJMIN
TJMAX

0.147

U7

V1

n/a

Delta (max−min)

P

I_Nom

5

TJMAX

U3
5

Tcase

P

TJMIN

I1

TC

R14
1m Pulse(0 900 0 5m 5m 4)

Vds_low
R3

R2

R1

1G

1G

1G

N

TC
I_HighTj{temp}
Tcase1RDS(on) is dependent on the junction temperature, TJ. The
strength of this dependency varies by technology. For
example, from 25°C to TJ(max), low and medium voltage
trench silicon MOSFETs may vary by a factor of 1.75, whilehigh voltage super junction MOSFETs may vary by a factorof 2.2, and silicon−carbide MOSFETs may only vary bya factor of 1.2. ID is determined by the application operating
point and TJ is a result of the power dissipation and thermal
impedance, thus strongly dependent upon RDS(on). The
quality of heat sinking and thermal coupling between
devices also affects ID and TJ. These interdependent
relationships make an analytical attempt to determine thedegree of current sharing between several devices witha given RDS(on) mismatch a challenging task. Appendix A of
Reference [11] provides an excellent guide to such ananalysis, and Reference [9] provides a similar guide for an
iterative solution. However, instead of these venerable
classical methods, given the wide availability of circuit
simulation software, a simple process to evaluate current
mismatch due to RDS(on) variability is shown here.
Figure 4 shows a simple simulation schematic of threedevices in parallel that can be used to evaluate the impact oftemperature rise and RDS(on) variation on the evolution ofdrain current sharing among three MOSFETs with max,
typical, and min (assumed from final test data) RDS(on)values. The circuit is idealized in that all parallel paths haveexactly the same gate voltage and no other parasitic circuit
elements that would govern current balance. We haveassumed here that the case temperature is held constant at
105°C. The fixed and equal case temperature boundary
conditions illustrate solely the effect of on resistancevariation across manufacturing variability and junction
temperature. The model includes internal thermal network
for the package (RθJC ~ 0.89 C/W). One can see by
examining Figure 6 that the imbalance in current isapproximately 23% of the nominal 300 A (~70 A), anda thermal imbalance also exists, with a maximum variationof 8°C, as seen in Figure 5. Yet, there is no increasing
thermal imbalance. It is also obvious that the on resistancedifference is not sufficient to force the currents to balance

U5
5

Tcase

P

TJMAX
TC

R13

Vds_high
N

Figure 4. Idealized On Resistance Variation Circuit

Figure 5. Idealized On Resistance Temperature
Imbalance

Figure 6. Idealized On Resistance Current Imbalancewww.onsemi.com
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We now add a difference in gate voltage to see the further
impact on imbalances in current and junction temperature.
For example, we reduce the gate voltage on the typical andmaximum RDS(on) parts by 10% to 9 V while maintaining
VGS = 10 V on the low RDS(on) part / high Rθ part, with theintention to force even more current through this device.
Figures 9 and 10 present the results for this case forRDS(on), junction temperature, and ID variation. As expected
the reduced VGS on two parts forces a larger current
imbalance, higher junction temperature, worse current
sharing.

Let us assume as an example a very good cooling systemthat provides only an additional 0.2 K/W thermal resistancenominally, case to ambient, but has some variation due toassembly or other issues such that one device has 50%
higher thermal resistance. For simulation brevity, let us
assume a 120 ms thermal time constant for a simple 1st orderthermal network (Rθ = 200 m, Cθ = 600 m, nominal). To
keep the operating conditions approximately the same as thefirst simulation, we will assume ambient temperature is
85°C.
Figure 7 shows the case where the lowest RDS(on) device
happens to be mounted on the cooling system with theincreased Rθ, thus the device which carries the highest
current is also receiving the worst cooling. We see
a significantly higher junction temperature on this device,
and we see a greater spread in temperature.

Figure 9. R, RDS(on) & VGS Variation: RDS(on) and TJ
ResultFigure 7. R and RDS(on) Variation: RDS(on) and TJ
ResultFigure 7 shows that the spread in RDS(on) and junction
temperatures has increased to about 0.4 mW (about 24% of
nominal) and 30°C, up from 8°C. However, even with thelarger delta between devices, we do not see an increasing
thermal imbalance developing.

Figure 10. R and RDS(on) Variation: Current
Imbalance

Table 2 shows a summary of the steady state variation forthese three cases just studied, representing the static
imbalance condition.

Figure 8. R and RDS(on) Variation: Current Imbalancewww.onsemi.com
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Table 2. SUMMARY OF STEADY STATE RESULTS ACROSS ALL VARIATIONS – STATIC IMBALANCE CASE
R +50%RDS(on)VariedVGS −10%

None

Max

Typ

Min

Max

Typ

Min

Max

Typ

Min

ID

300

263

303

334

263

305

337

246

300

363

RDS(ON), mΩ

1.71

1.97

1.71

1.56

1.81

1.56

1.44

2.12

1.74

1.47

TJ, C

138

135

139

143

138

146

167

138

150

181

PD, W

154

137

157

173

126

146

158

128

157

185

Value

As was done for static imbalance cases, we will use circuit
simulation of three parts in parallel to illustrate the dynamic
imbalances that can occur during switching. As readers will
be aware, there are numerous contributors to specificswitching waveform behavior. Obvious ones are the gate
resistor, gate driver IC properties, device properties (andtheir intrinsic variability), stray parasitic circuit elements
associated with PCB and DC link filters and bus work, local
capacitor banks' specific part details, gate and drain
protection circuitry such as Zener diodes, etc. Additionally,
for test data, even the errors associated with high quality test
instrumentation can contribute significantly to uncertainty
in results. Therefore, with respect to evaluating dynamic
current sharing and associated safe operation of the
MOSFETs in parallel, it is not practical to include all suchcontributing elements in this analysis.

While reviewing Table 2, recall that each new variation
added after the RDS(on) was additional to the RDS(on)varation, and was applied to the same of the three parts inparallel, namely the one with minimum RDS(on), thus
carrying maximum current.
Dynamic Current Sharing Design Considerations

The dynamic current sharing case refers to the normal
switching of the MOSFETs, such as that found in a PWM
motor control or dc−dc converter application. This is themost commonly encountered dynamic situation affecting
normal design choices for paralleling MOSFETs. Some
comments will be made later regarding avalanche and shortcircuit conditions.
Power MOSFETs will share current reasonably well withsimple and efficient gate−drive circuitry. The issues ofgreatest concern to those interested in dynamic current
sharing of paralleled MOSFETs are:• Device parameters that influence dynamic current
sharing.
• Variation of pertinent device parameters from lot to lot.
• The effects of switching speed on dynamic current
sharing.
• The requirements and effects of circuit layout.
• The possibility of self−induced oscillations.

Variation of Pertinent Device Parameters
To begin, let us examine a representative set of final test
data that shows variation in VGS(th). Transconductance,
VGS(th), and RDS(on) are closely coupled parameters, so
examining VGS(th) is a simple parameter to look at. Figures
11 and 12 show the variation and the distribution of ~7500
samples of a particular large die, 80 V trench MOSFET.

Device Parameters That Influence Dynamic Current
Sharing
The device parameters that influence the degree ofdynamic current sharing are the inter−relatedtransconductance, gate−source threshold voltage VGS(th),input capacitance, and on−resistance RDS(on). However, thedevice characteristic that may be most useful to predict how
well paralleled MOSFETs will current share duringswitching is the transconductance curve, i.e., therelationship between the drain current and the gate−source
voltage. To obtain optimum current distribution duringturn−on and turn−off, the ideal situation is to have allgate-source voltages rising (or falling) simultaneously on
devices with identical transconductance curves. This
idealization would ensure that as the devices switch throughthe active region, all would share current evenly.

Figure 11. Variation of VGS(th)www.onsemi.com
5AND90108/D
With these models, we can examine switching waveforms
during turn−on and turn−off to see how well current isshared, using an idealized circuit initially with no parasitic
elements external to the package (that is, no additional drain
or common source inductance, identical gate voltage). Fora nominal 200 A drain current, Figures 15 and 16 illustrate
the dynamic behavior of this well−matched set of parts
switching in parallel.

Figure 12. Distribution of VGS(th) Across ~7500
Samples

As a representative part from the same technology, we can
expect the distribution of our 80 V MOSFET [9] to exhibit
similar variation. So, using an adjustable circuit model forour part, we can set up a simulation with three parts thatexhibit VGS(th) values that are only about ±20 mV different
from the nominal 3 V at 250 mA. The resulting transfer
characteristic and transconductance curves (at TJ = 25°C)
are shown in Figures 13 and 14. As seen, the curves are very
closely aligned. For example, at VGS = 5.25 V and VDS = 5
V, the drain current values are 224 A, 231 A, and 238 A, formax, typ, and min VGS(th) parts, respectively. Likewise,transconductances at the same gate and drain voltages are
477 S, 483 S, and 489 S, for max, typ, and min VGS(th) parts.
This current level of about 200 A was chosen because later
we will examine dynamic current balance while switching
this level of drain current in the three paralleled parts.

Figure 14. Transconductance of Well−Matched Parts

As seen in Figures 15 and 16, the device with the highest
threshold voltage, “max”, is the first to begin turning off andthe last to begin turning on, thereby conducting less current.
As “max” current reduces during turn off, the remaining two
devices are still “on” and experience an increase in theircurrent. As can be seen by close inspection of Figure 15, the“min” part accepts the larger amount of this increase because
it remains at a higher conductance, for the given gate
voltage. The reverse of this process is evident in Figure 16.
By examining the minor differences in the current
waveforms in Figures 15 and 16, one would expect very
minor differences in accumulated energy during theswitching events, and consequently minimal difference injunction temperature. In fact, not shown here but confirmed
in simulation, EOFF was different by only 40 mJ out of 485 mJ(typical), while EON was different by only 75 mJ out of 835
mJ (typical), per die, at this 200 A nominal switching event.
Likewise, with the case temperature fixed at 105°C, at theend of both switching events, typical temperature rise was< 1°C and the delta from min to max was only < 0.1°C.

Figure 13. Transfer Characteristic Well−MatchedParts

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external power circuitry is still very much idealized, in that
there is no drain inductance or common source inductance.
As will be seen, some common source inductance hasa beneficial effect for current balancing.

Figure 15. Turn−Off at 200A – Well−Matched Parts

Figure 17. Transfer Characteristic Poorly−Matched
Parts

Figure 16. Turn−On at 200A – Well−Matched Parts

Seeing the relatively good current sharing ofwell−matched parts, we now look what happens in the worst
case for the spread represented in Figure 11. We now set the
MOSFET models in simulation to exhibit 25°C, 250 mA
min, typical, and max VGS(th) of 2.75 V, 3.4 V, and 3.8 V,
respectively, and repeat the simulation. These results areshown in Figures 17 to 20.
Referring to Figures 19 and 20, we can see that theswitching currents are quite unbalanced, differing by~300 A from the max to min, while the typical device
remains at 200 A. Since this is a relatively brief transient of~400 ns, there is not a significant impact on temperature of
the devices, but there will develop an unbalance of averageswitching loss over time, which will produce a temperatureoffset eventually, depending on the system thermal
impedance. The reader is reminded that, while thetransconductance variation is large here and is realisticallypossible for parts taken from various production lots, theFigure 18. Transconductance of Poorly−Matched
Parts

Table 3 provides a summary comparison of switchingenergy and effect on total switching losses and junction
temperature rise dTJ for these initial cases with idealized
external circuits free of parasitic inductance. We can see thatfor the same high performance heatsink described above forthe static imbalance, here the well−matched parts yield
differences in total switching energy (ESW) of about 120 μJ,
which at 10 kHz switching in a MOSFET inverter would
correspond to less than 1°C variation in junction
temperature. The rather large current difference shown for

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the poorly matched parts would yield about 2000 mJ
difference, and about 11°C junction temperature variance.

With respect to this idealized situation of the external
circuit having no significant parasitic inductances, we cansee that even large differences in mismatchedtransconductance that yields a large current mismatch
during the switching transients, the net effect on total losses,
while measurable, have a relatively minimal impact onthermal imbalance.

Table 3. SUMMARY RESULTS LONG TERM
Well−Matched Parts
Variable
Eon, μJ

Poorly−Matched
Parts

Min

Typ

Max

Min

Typ

Max

850

810

770

1840

900

490

Eoff, μJ

511

491

471

896

339

156

Esw, μJ

1360

1301

1241

2736

1239

646

fsw, kHz

10

10

10

10

10

10

PSW, Avg W

6.8

6.5

6.2

13.7

6.2

3.23

δTj, °C

7.4

7.1

6.8

14.9

6.8

3.5

The Requirements and Effects of Circuit Layout
Even with identically matched devices, dynamic current
sharing between MOSFETs will be poor if an asymmetricalcircuit layout is used. Obviously, if the gate drives aredifferent, unequal rates of gate−source voltage rise and fall
can cause unsynchronized switching and even device failurein extreme cases. As the switching speeds of these devices
are increased, the designer’s perception as to what may
constitute an important parasitic circuit element mustchange. When approaching the maximum switching speedsof power MOSFETs, even small variations in lead length
may influence their paralleled switching performance.
Unequal source wiring inductances are especially
deleterious.
It is good design practice to minimize these inductances
to keep EMI and VDS overshoot issues under control.
However, the presence particularly of common source
inductance (inductance in the high current path of the source
connection that is common with the gate loop) can bebeneficial for current sharing, but must be balanced withoverall system performance and as similar as possible for allparalleled MOSFETs.
A modest 6 nH total split evenly between drain and source
legs yeilds a significant improvement in the dynamic current
imbalance, as seen in Figures 20 and 21. During turn off
from 200 A nominal for each part, we now have less than
100 A difference from min to max. We begin to see
overshoot voltage as expected in the drain circuit, but noavalanche is yet encountered.
Note in Figures 21 and 22, the red current trace is ID(max)and the blue current is ID(min), while the blue VGS trace is
VGS(max) and the green VGS trace is VGS(min).
Table 4 shows a summary for these conditions of adding
stray inductance for the case of poorly−matched parts. As
seen in this table, losses increase compared to the ideal
external circuit with poorly−matched parts, shown in
Table 3. However, losses and temperature rise are morebalanced in steady state. In this simulation, δTJ difference isonly ~7°C.

Figure 19. Turn−Off at 200A – Poorly−Matched Parts

Figure 20. Turn−On at 200A – Poorly−Matched Parts

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MOSFETs in parallel with a total of 2 W gate resistance, as
illustrated in Figure 23 (a). An underdamped RLC circuit isthen formed by the three MOSFETs’ CGD, CGS, parasitic
LD, and parasitic LS, with minimal damping resistance. An
equivalent distributed gate resistance network is shown in
Figure 23 (b), with each MOSFET having an associated 6 W
gate resistor. These two configurations will give equivalentswitching speed, but the distributed network will provide
more damping during the switching events.

Figure 21. Simulation Output with Stray Inductance,
Poorly−Matched Parts – Turn Off Event
(a)

(b)

Figure 23. (a) Single Gate Resistor(b) Distributed Gate Resistors

Continuing with our previous condition where the min,typical, and max VGS(th) samples are selected and paralleled
together, we can compare the relative gate and drain circuit
stability in simulation. The results are presented for the same
200 A drain current switching event as previously.
Figures 24 and 25 show the gate voltage waveforms foreach MOSFET with and without the distributed gate
resistors. In these figures, the dotted traces are without the
distributed gate resistor but with equivalent single driving
node gate resistance of 2 W, and the solid lines are with
distributed 6 W gate resistors.
Initial gate oscillations for this high speed switching caseare difficult to avoid, due to the midpoint dV/dt and Miller
capacitance. However, the following numerous cycles ofoscillations in gate voltage can be damped with the
distributed resistance as the RLC circuit responds to theinitial switching impulse and reverse recovery transient of
the opposite switch body diode.
Because the combined distributed gate resistances areequivalent in value to a single lumped gate resistor, theswitching time constant remains the same, and the losses are

Figure 22. Simulation Output with Stray Inductance,
Poorly−Matched Parts – Turn Off Event
Table 4. SUMMARY RESULTS – STRAY INDUCTANCEINCLUDED WITH POORLY−MATCHED PARTS
Variable

Min

Typ

Max

Eon, mJ

1459

864

630

Eoff, mJ

1773

1448

1258

Esw, mJ

3232

2312

1888

fsw, kHz

10

10

10

PSW, Avg W

16.2

11.6

9.4

δTj , °C

17.6

12.6

10.3

The Requirements and Effects of Circuit Layout
Coupled oscillations in the gate and drain circuits may
become objectionable or dangerous to the power MOSFETs
if the gates are driven from a single common gate node. For
example, assume one wishes to drive each of three

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not impacted significantly, but as can be seen especially in
Figure 24, the gate oscillations are under much better
control. As an example, Figure 26 shows the energy lost
during the turn−off event.

With respect to gate resistor selection, it is also worth
noting that for most high current applications (e.g., motor
drives) where paralleling is commonly used, switchingfrequency is relatively low (in the range of 5−15 kHz). Here,conduction losses are so dominant that increasing gate
resistance to reduce gate oscillations does not havea significant impact on total losses, since switching losses
remain relatively low.
For the final determination of what level of current
sharing is necessary for successful application, designers
will need to explore the techniques described here and to
consider how best to optimize circuit layout, switching
speed, device margin, and thermal management. This
involves making sure that the worst case operating
conditions can be handled in steady state and in harshtransient conditions, not solely the instantaneous losses andpeak currents reached. Using the techniques described here
will help the designers arrive at a successful solution.
A Few Words on Short Circuit Withstand Time andAvalanche

Figure 24. Gate Voltages for Turn Off with andwithout Distributed Gate Resistors.

With the increased application power MOSFETs to highpower systems such as Belt Starter Generator for 48 V
vehicle electrification and electric vehicle tractions drives,
increased attention is being paid to short circuit withstandtime (SCWT). With these applications the state of the art isbeing advanced and fundamental tradeoffs are being
examined. Especially with respect to very low RDS(on)silicon MOSFETs (≤0.5 mW) and very high speed
silicon−carbide MOSFETs, the very features that make themattractive for these applications make for difficulty inhandling short circuit conditions and also increase thelikelihood of experiencing avalanche.
To minimize switching and conduction losses, packages
with extremely low stray inductance and small, efficient
footprints are being developed. These lead to the ability,with tightly coupled DC link capacitor banks, to develop
thousands of amps of short circuit (SC) current within 1 to
2 microseconds. This is often less time than is necessary todetect an overcurrent condition and apply safe turn−offmeasures! Then, even with the low inductance package andboard design, di/dt is so high during turn off that avalanche
is likely to occur.
Two recommendations are clear: include an optimized
amount of common source inductance to provide negativegate voltage feedback during high di/dt events in order tolimit current, and consider alternatives to “desaturation
detection” techniques for overcurrent and SC fault
detection. Otherwise, with very low resistance, fastswitches, there may be instances when it is impossible torecover from a short circuit event.

Figure 25. Gate Voltages for Turn On with andwithout Distributed Gate Resistors

Figure 26. Turn−Off Energy with and without
Distributed Gate Resistors

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References[6] Andre Lenz, et al, “Hard Paralleling SiC MOSFET
Based Power Modules,” Bodo’s Power Systems,
September 2020, pp. 26−28.
[7] Steven A. Morris, “High Temperature Linear
Operation of Paralleled Power MOSFETs,” HITEN
Conference, September, 2007, St. Catherine’s College,
Oxford.
[8] Kim Gauen, “Paralleling Power MOSFETs in
Switching Applications,” Application Note AN−918,
Motorola Semiconductor Products, Inc., 1988.
[9] Data Sheet FDBL86361−F085, MOSFET –PowerTrench N−Channel 80V, 300A, 1.4 mOhm,
ON Semiconductor, December 2019.
[10] J.B. Forsythe, “Paralleling of Power MOSFETs forHigher Power Output,” IEEE IAS Conference Record,
October 1981.
[11] Motorola Power MOSFET Transistor Data, DL135,
Rev 2, Motorola, Inc., 1988 (Chapter 7).

[1] Toni Lopez and Reinhold Elferich, “Current Sharing of
Parlleled Power MOSFETs at PWM Operation,” 37th
IEEE PESC, 2006.
[2] Hongfang Wang and Fred Wang, “Power MOSFETs
Paralleling Operation for High Power High Density
Converters,” Conference Record of the 2006 IEEE
Forty First Industry Applications Conference, 2006.
[3] Yincan Mao, et al, “Balancing of Peak Currents
between Paralleled SiC MOSFETs by Source
Impedances,” 2017 IEEE Applied Power Electronics
Conference and Exposition, 2017.
[4] Krishna Mainali, et al, “Current Sharing andOvervoltage Issues of Paralleled SiC MOSFET
Modules,” 2019 IEEE Energy Conversion Congress
and Exposition, 2019.
[5] Rajagopalan Jaganathan, et al, “Discrete 1200V SiC
MOSFETs – SMD Package Benefits and Impacts ofMultiple Device and Circuit Parameters Mismatch inHigh Power Parallel Applications,” PCIM Europe,
Nuremberg, Germany, 5−7 June, 2018.

www.onsemi.com
11

AND90108/D
APPENDIX A
L12{LbusHalf}
IL
G2

U3

Ig_HS

U5

Tcase

G3

S2

S3
VGStyp

VGSminTJFDBL36361_die_5P_wSimTemp
Tj

TJ

Tcase
U6

Tcase

D1

D2

D3

S1

S2

S3

0
V1

VDSmin

L13

L14

5n

5n

VGSmax

L11

S1
FDBL36361_die_5P_wSimTemp
Tj
TJ{Lload}G1

FDBL36361_die_5P_wSimTemp
Tj

R3
1m

VDStypVDSmaxL155n

TC_NomTC_MinTC_MaxE_QminTJNOM

Let VDC = 50V
R13
100u

E_QmaxE_Qtyp

I(D)

TJTYP

I(D)

I(D)

TJMIN
R4

Let Lload = 3.315u

R5

200m

Let Ron = 5

C1

ID min

R6

300m

600m

Let ton =40 usec

C2
400m

200m

C3

TJMIN

600m

TJMAX

{temp}

R2

R8

R9

1G

1G

1G

17.5

S

R11

integ(abs((V(D)−V(S)))*abs(I(D)))

D3

L5

175p

D
S

S3

integ(abs((V(D)−V(S)))*abs(I(D)))

D2

L3
R7

ID maxD
S2

integ(abs((V(D)−V(S)))*abs(I(D)))

D1

TJMAX

ID typ

D
S

S1

+

C5
15n IC=50

L6

175p

R14

17.5

175p

17.5

Tcase1

R12
1

50
V3
FDBL36361_die_5P_wSimTemp
Tj
{Ron}

{Lgate}U7

Ig_LS

FDBL36361_die_5P_wSimTemp
Tj

TJMIN

U4

Tcase

FDBL36361_die_5P_wSimTemp
Tj

TJNOM

U8

Tcase

TJMAX

Tcase

L36
G1

TC_MinG2

TC_NomG3

TC_Max

L8
R17

L9

R16

50p

5

50p

L7
R15

5

50p

5

Vgs_LS_Drive
VgsLo2
S1

S2
S3{Lgate}

L43

R32
100u

L4

L2

L10

5n

5n

5n

{LbusHalf}
L1

Figure 27. Appendix A

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