FEBRUARY
17, 18, 19, 20, 21

CONFERENCE THEME:

60 YEARS OF(EM)POWERING THE FUTURE

SAN FRANCISCOMARRIOTT MARQUIS HOTELNEW THIS YEAR:

60TH ANNIVERSARYDISTINGUISHED EVENING PANEL

Graduate Student Research in Progress, Batteries Not Included

5 4 – 2 0 13

60GHz CMOS LNA Design, High-Bandwidth Memory Interfaces, Energy Harvesting & Processing,
FinFET Circuits, Data-Converter-Design Simulation, On-Chip Voltage & Timing Diagnostics, Robust SoC Design,
Wireless Transceiver System Design, Voltage-Reference Design, Data & Power Implant Telemetry

5-DAY 10 TUTORIALS on
PROGRAM
2 EVENING EVENTS on

OFSO

A SHORT-COURSE on RF Blocks for Wireless Tx/Rx

Frequency Generation & Clock Distribution,
Mixed-Signal/RF Design in Future CMOSTHURSDAY ALL-DAY

ADVANCE PROGRAM
4 FORUMS on Emerging Technology for Wireline, Scientific Imaging,

2013
IEEE
INTERNATIONAL
SOLID-STATECIRCUITSCONFERENCESUNDAY ALL-DAY

19

2 FORUMS on Advanced RF Transceiver Design, VLSI Power-Management Techniques

60 YEARSTE INNO
STA
VA
DLI

ON
TI

IEEE SOLID-STATE CIRCUITS SOCIETY

2013_MiniAP_Cover_AP 11/8/12 10:41 AM Page 1

2013_MiniAP_Cover_AP 11/8/12 10:41 AM Page 2

ISSCC VISION STATEMENTThe International Solid-State Circuits Conference is the foremost global forum forpresentation of advances in solid-state circuits and systems-on-a-chip. The Conference offersa unique opportunity for engineers working at the cutting edge of IC design and application
to maintain technical currency, and to network with leading experts.

CONFERENCE TECHNICAL HIGHLIGHTSOn Sunday, February 17th, the day before the official opening of the Conference, ISSCC 2013
offers:• A choice of up to 4 of a total of 10 Tutorials• A choice of 1 of 2 Advanced-Circuit-Design Forums
The 90-minute tutorials offer background information and a review of the basics in specificcircuit-design topics. In the all-day Advanced-Circuit-Design Forums, leading experts present
state-of-the-art design strategies in a workshop-like format. The Forums are targeted at designers experienced in the technical field.
On Sunday evening, there are two events: A Special-Topic Session entitled, “Batteries Not
Included - How Little is Enough for Real Energy Autonomy?” will be offered starting at
8:00pm. In addition, the Student Research Preview, featuring short presentations followed
by a poster session from selected graduate-student researchers from around the world will
begin at 7:30 pm. Introductory remarks at the Preview will be provided by Nicky Lu, a
distinguished innovator, entrepreneur, chief executive, researcher, and design architect.
On Monday, February 18th, ISSCC 2013 offers four plenary papers on the theme: “60 Yearsof (Em)Powering the Future”. On Monday at 12:15 pm, there will be a Women’s Networking
Event, a luncheon. On Monday afternoon, there will be five parallel technical sessions,followed by a Social Hour open to all ISSCC attendees. The Social Hour, held in conjunction
with the Book Display, will also include a Demonstration Session (DS1), featuring posters
and live demonstrations for selected papers from industry and academia. Monday evening
will feature 6 distinguished researchers in a 60th Anniversary Panel entitled “Antiques fromthe Innovations Attic”.
On Tuesday, February 19th, there are five parallel technical sessions, both morning andafternoon. A Social Hour open to all ISSCC attendees will follow. The Social Hour, held inconjunction with the Book Display, will include the second Demonstration Session (DS2),
featuring posters and live demonstrations for selected papers from industry and academia.
Tuesday evening sessions include two evening panels on “You’re Hired - The Top 25 Interview Questions for Circuit Designers”, and “SoCs Empowering 2020 Killer Applications”,
as well as one Special-Topic Session on “High-Speed Communications on 4 Wheels - What’sin Your Next Car?”.
On Wednesday, February 20th, there will be five parallel technical sessions, both morningand afternoon.
On Thursday, February 21st, ISSCC offers a choice of five events:• A Short Course on “RF Blocks for Wireless Transceivers”• Four Advanced-Circuit-Design Forums on
wireline communications; scientific imaging;frequency generation and distribution;and mixed-signal/RF design/modeling in evolving CMOS.
Registration for educational events will be filled on a first-come, first-served basis. Use of
the ISSCC Web-Registration Site (http://www.isscc.org) is strongly encouraged. Registrants
will be provided with immediate confirmation on registration for the Conference, Tutorials,
Advanced-Circuit-Design Forums, and the Short Course.

Need Additional Information?
Go to: www.isscc.org
2

2013_Mini_AP_AP 11/8/12 9:57 AM Page 3

TABLE OF CONTENTS
Tutorials .........................................................................................4-7
F1
F2
ES1
ES2

1
2
3
4
5
6

FORUMS
Advanced RF Transceiver Design Techniques ......................................................8
VLSI Power-Management Techniques: Principles and Applications .....................9EVENING SESSIONS
Student Research Preview .................................................................................10“Batteries Not Included.” – How Little is Enoughfor Real Energy Autonomy? ........................................................................11
PAPER SESSIONSPlenary Session............................................................................................12-13
Ultra-High-Speed Transceivers and Equalizers...................................................14
Processors.........................................................................................................15
Harvesting and Wireless Power .........................................................................16
RF Techniques....................................................................................................17
Emerging Medical and Sensor Technologies......................................................18

Demonstration Session 1..............................................................................................19
EP1

EVENING SESSIONS
Antiques from the Innovations Attic....................................................................20

7
8
9
10
11
12
13
14
15
16

PAPER SESSIONS
Optical Transceivers and Silicon Photonics........................................................21
Millimeter-Wave Techniques ..............................................................................22
Mobile Application Processors and Media Accelerators.....................................23
Analog Techniques .............................................................................................24
Emerging Memory and Wireless Technology .....................................................25
Nonvolatile Memory Solutions...........................................................................26
High-Performance Wireless ...............................................................................27
Digital PLLs and Building Blocks .......................................................................38
Data Converter Techniques ................................................................................29
Biomedical Circuits & Systems ..........................................................................30

Demonstration Session 2..............................................................................................31
Conference Timetable .............................................................................................32-33

EP3

EVENING SESSIONS
High-Speed Communications on 4 Wheels:
What’s in your Next Car? ..............................................................................34
You’re Hired - The Top 25 Interview Questions
for Circuit Designers .....................................................................................35
Empowering the Killer SoC Applications of 2020 ...............................................35

17
18
19
20
21
22
23
24
25
26
27

PAPER SESSIONS
High-Performance DRAM Interfaces..................................................................36
Advanced Embedded SRAM ..............................................................................37
Wireless Transceivers for Smart Devices ...........................................................38
Frequency Generation ........................................................................................39
Power Converters ..............................................................................................40
Sensors & Displays............................................................................................41
Short Reach Links, XCVR Techniques, & PLLs ..................................................42
Energy-Aware Digital Design..............................................................................43
Energy-Efficient Wireless ...................................................................................44
High-Speed Data Converters..............................................................................45
Image Sensors...................................................................................................46

ES3
EP2

SHORT COURSERF Blocks for Wireless Transceivers.............................................................47-48
F3
F4
F5
F6

FORUMS
Emerging Technologies for Wireline Communication.........................................49
Scientific Imaging ..............................................................................................50
Frequency Generation and Clock Distribution ....................................................51
Mixed-Signal/RF Design and Modeling in Next-Generation CMOS.....................52

Committees..............................................................................................................53-57
Conference Information...........................................................................................58-61
Conference Space Layout .............................................................................................623

2013_Mini_AP_AP 11/8/12 9:57 AM Page 4

Sunday February 17th

TUTORIALS

T1: Basics of 60GHz LNA and PA Design in CMOS
This tutorial will focus on 60GHz CMOS front-end building blocks (low-noise amplifiers andpower amplifiers). System specifications will be derived from high-data-rate wireless communication links, and the design of these blocks will be explained step-by-step. Fundamental
metrics for noise, linearity, and impedance matching will be addressed. As mm-wave operating frequencies are relatively close to the cutoff frequency of the active devices, little design
freedom is left. This inevitably limits the complexity of mm-wave circuits. Further, layout issues of these circuits are discussed, as at mm-wave frequencies the sensitivity to layout parasitics is higher compared to radio front-end circuits in the low-GHz frequency region. Thisrequires very careful electromagnetic modeling, as several interconnects need to be modeled
as on-chip integrated transmission lines.

Instructor: Piet Wambacq
Piet Wambacq received the M.Sc. and the Ph.D. degree in Electrical Engineering from the Catholic
University of Leuven, Belgium, in 1986 and 1996, respectively. Since 1996, he has been with imec,
Belgium, where he is a Principle Scientist in analog, RF and mm-wave IC design using advanced
CMOS technologies. Currently his focus is on mm-wave transceiver design. He is also Professor at
the Vrije Universiteit Brussel. He has published two books and more than 200 peer-reviewed journaland conference papers.

T2: High-Bandwidth Memory Interface Design
Memory bandwidth has been increased significantly. There are many technical issues toenhance the memory interface such as TSV interface, high-speed serial interface including
equalization, ODT, pre-emphasis, wide I/O interface including crosstalk, skew cancellation,and clock generation and distribution. This tutorial provides overviews of recent advancesin memory interface design both in architecture and circuit levels. Subtopics will include
signal integrity and testing. The future trends for further bandwidth enhancement will becovered as well.

Instructor: Chulwoo Kim
Chulwoo Kim received the B.S. and M.S. degrees in electronics engineering from the Korea University in 1994 and 1996, respectively, and the Ph.D. degree in electrical and computer engineeringfrom the University of Illinois at Urbana-Champaign in 2001. In May 2001, he joined IBM Microelectronics Division, Austin, TX, where he was involved in Cell processor design. Since September
2002, he has been with the Department of Electrical Engineering, Korea University, where he is currently a Professor. In 2008-2009, he was a Visiting Scholar at the University of California, Los Angeles. His current research interests are in the areas of wireline transceiver, memory, power
management and data converters. He is currently on the editorial board of the IEEE Transactions
on VLSI Systems.

T3: Energy Harvesters and Energy Processing Circuits
The area of energy harvesting has seen significant interest in academic circles over the past
decade. With the recent introduction of commercial ICs geared for energy harvesting applications by multiple semiconductor companies, this area is poised to take the next step tocommercial adoption. However, challenges remain in the widespread adoption of energy harvesting solutions primarily owing to the limitations in average power output. A sound understanding of the energy flow within the harvesting system (from energy extraction to energy
delivery) is crucial in overcoming these challenges.
In this tutorial, we will talk about the basics of commonly used energy harvesters and how
their characteristics differ from conventional energy sources. Specialized circuits used to optimize energy extraction from different harvesters will be reviewed. The second part of thetutorial will talk about energy processing circuits like chargers, DC-DC converters and protection circuits for energy storage elements. Theoretical considerations in designing thesecircuits will be discussed and examples of practical implementations from commercial ICs
will be presented.

Instructor: Yogesh Ramadass
Yogesh Ramadass received his B.Tech. degree from the Indian Institute of Technology, Kharagpur
in 2004 and the S.M. and Ph.D. degrees in Electrical Engineering from MIT in 2006 and 2009. He
is currently working as a lead design engineer at Texas Instruments where he is focused on architecting and designing power converters and mixed-signal circuits for energy harvesting, wireline42013_Mini_AP_AP 11/8/12 9:57 AM Page 5

Sunday February 17th

TUTORIALS

and wireless charging applications. Dr. Ramadass was awarded the President of India Gold Medalin 2004. He was a co-recipient of the Jack Kilby best student paper award at ISSCC 2009 and theBeatrice Winner award for editorial excellence at ISSCC 2007. He serves on the Technical Program
Committee for ISSCC and ISLPED. He served as the chair of the ‘Analog, MEMS, Mixed Signal andImaging Electronics’ committee at ISLPED 2012.

T4: Circuit Design using FinFETs
After HKMG, FinFETs are a powerful yet disruptive technology to enable continuous scaling
following Moore’s law. The disruptive nature arises from both the 3D structure and the quantization on width choice. FinFETs require new design skills to trade-off among PPA (powerperformance-area) and to conduct circuit-process co-optimization. Salient advantages of
FinFETs include: increased driving capability per footprint area, better control on short-channel
effect, subthreshold slope, and less requirement on channel doping. Thus, threshold voltage
can be reduced, which enables a reduction in supply voltage and thus power consumption or
increase of performance speed.
The tutorial will focus on critical issues of FinFET design: It starts with a crisp comparison ofplanar vs. 3D FinFET devices and the associated SPICE modeling. Next, logic design is presented, including effects on standard cells, I/O circuitry, and ESD. Then, the subjects of SRAM
and analog/mixed-signal design are treated in detail. Digital chip-level design that requires
methodology enhancement and new CAD tool features are carefully discussed. The tutorial
will enable CMOS designers to systematically comprehend circuit design using FinFETs.

Instructor: Bing Sheu
Bing Sheu obtained a BSEE from National Taiwan University, and Ph.D. degree from UC Berkeley.
He taught at USC during 1985 – 1998, and was promoted to Full Professor in 1997. He moved toindustry in 1999 and joined TSMC in 2006 as Director at R&D Design and Technology Platform. He
was the original Creator of the BSIM (Berkeley Short-channel IGFET Model). He served as Editorin-Chief of IEEE Transactions on VLSI Systems (1997 & 98), Founding Editor-in-Chief of IEEE Transactions on Multimedia (1998 & 99), and President of IEEE Circuits and Systems Society (2000). He
is an IEEE Fellow, a recipient of IEEE Guillemin-Cauer Award in 1997, and IEEE CAS Society Meritorious Service Award in 2004. He currently serves on the Program Committees of ISSCC and VLSI
Circuits Symposium.

T5: Simulation Techniques for Data Converter Design
ADC and DAC designers spend much time running long simulations that verify functionality
and performance of their designs. Some converter designs contain many nominally identicalcells (e.g. flash ADCs and current steering DACs). In some others the ratio of the samplingand signal frequencies is very high (oversampling ADCs). This tutorial, targeted at non-experts, will showcase some simulation techniques that are used in ADC/DAC designs. A brief
overview of various architectures and examples involving behavioural and SPICE-like simulators will be given.

Instructor: Shanthi Pavan
Shanthi Pavan obtained the B.Tech. degree in Electronics and Communication Engineering from theIndian Institute of Technology, Madras in 1995 and the D.Sc. from Columbia University, New Yorkin 1999. He is now a Professor of Electrical Engineering at the Indian Institute of Technology,
Madras. His research interests are in the areas of high-speed analog circuit design and signal processing.
Dr. Pavan is the recipient of the IEEE Circuits and Systems Society Darlington Best Paper Award(2009), the Swarnajayanthi Fellowship (2010, from the Government of India), the Young Faculty
Recognition Award from IIT Madras (2009, for excellence in teaching), the Technomentor Award
from the India Semiconductor Association (2010) and the Young Engineer Award from the Indian
National Academy of Engineering (2006). He is the Deputy Editor-in-Chief of the IEEE Transactions
on Circuits and Systems: Part I - Regular Papers, and serves on the Data Converter Committee of
the ISSCC.

5

2013_Mini_AP_AP 11/8/12 9:57 AM Page 6

Sunday February 17th

TUTORIALS

T6: On-Chip Voltage and Timing Diagnostic Circuits
This tutorial introduces a set of practical and powerful techniques and circuits to observe andcharacterize on-die circuitry. Measuring voltage and timing information on the chip itself alleviates the bandwidth and noise limitations associated with bringing signals off-chip to bemeasured. Specific applications of these techniques include measurement and characterization of power supply noise, power delivery impedance, clock skew, phase interpolator linearity,
I/O eye margins, waveform capture, RX voltage noise and hysteresis, and RX clock-data jitter.
Because the measurements are fully integrated, the rest of the system can be automatically
adapted based on these metrics in a stand-alone manner. Best of all, many of these techniquesleverage existing circuitry and are highly digital.

Instructor: Frank O’Mahony
Frank O’Mahony leads the I/O Circuit Technology group within Advanced Design at Intel in Hillsboro,
Oregon. He develops the first wireline I/O circuits for each new CMOS process technology. From2003 until 2011 he was a member of the Signaling Research group in Intel’s Circuit Research Lab.
His research interests at Intel include high-speed and low-power data links, clock generation anddistribution, and on-die measurement techniques. Frank received the B.S., M.S., and Ph.D. degrees
in electrical engineering from Stanford University, Stanford, CA, in 1997, 2000, and 2004, respectively. He received the 2003 Jack Kilby Award for Outstanding Student Paper at ISSCC for his workon standing-wave oscillators. Frank is a member of the ISSCC Wireline Subcommittee and an Associate Editor for TCAS-I.

T7: SoC Design Methodology for Improved Robustness
A holistic approach to power and performance attainment for semi-custom SoC designs isrequired to properly optimize future generation devices. We will cover novel techniques which
tie SoC development together from micro-architecture to design signoff using examples fromproduction SoCs. We discuss SoC clocking structures, local vs. distributed dividers, realworld implementation of clock-gating and data-driven clock power reduction. This is tied todesign signoff, specifically, margin and signoff corner requirements including use of statistical
STA. We will discuss how to select process corners and the type of outlier circuits whichmust be comprehended. Other novel areas of SoC optimization are considered including repeater insertion and repeater circuits for low power, auto-extraction and use of regularity inplace and route, and SRAM power optimization.

Instructor: Anthony M. Hill
Anthony Hill is a Distinguished Member of Technical Staff for Texas Instruments, Dallas, TX. He
leads the technology, physical implementation, and signoff team for TI’s Multi-Core Systems Business Unit. He has been involved in the execution of 6 generations of complex SOCs and cores from180nm to 28nm focused on communications infrastructure and high-performance embedded computing centered around TI’s C6X DSP family. He joined TI in 1996 after taking his BSEE from Oklahoma State University in 1992, and MSEE and PhD from the University of Illinois Urbana-Champaign
in 1993 and 1996. He is currently serving on the ISSCC High-Performance Digital subcommittee.

T8: Wireless Transceiver System Design for Modern
Communication Standards
Defining the architecture and deriving specifications for modern wireless communication
radio transceivers is a cross-domain task that requires understanding of digital communications, signal processing, radio architectures, analog/RF circuit design, discrete PCB systemdesign, IC process and real-world product experience. This tutorial introduces the basic terminology used, such as NF, IIP2, IIP3, and provides an overview of the architecture selection
and specification derivation procedure using state-of-the-art examples such as 3G/LTE cellular,
802.11ad and others. Starting from regulatory and communication standard document requirements such as sensitivity, blocking, spectral mask, EVM, etc., and taking into accountdifferent transceiver topologies, detailed transceiver specifications such as gain NF, IIP2, IIP3,
cross-modulation, phase noise, filtering profile, I/Q mismatch, ADC resolution are derived
and mapped onto circuit blocks. This is done by using both analytical calculations and simulation results, while the various transceiver performance degradation mechanisms are explained.

Instructor: Iason Vassiliou
Iason Vassiliou received his Diploma in Electrical Engineering from the National Technical Universityof Athens in 1991 and his M.Sc. and Ph.D. in Electrical Engineering from the University of California

6

2013_Mini_AP_AP 11/8/12 9:57 AM Page 7

Sunday February 17th

TUTORIALS

at Berkeley in 1995 and 1999, respectively. Currently he is an Associate Technical Director at Broadcom, Greece. His main responsibility is radio system design and has worked on transceivers for
WLAN, 60GHz, digital TV and LTE. Mr. Vassiliou holds 10 issued US patents and has authored several conference and journal papers, contributed 2 book chapters on wireless transceivers and analog CAD and has taught as a guest lecturer at professional seminars.

T9: Design of Voltage References
Voltage references are indispensable components in IC design. Their applications range from
simple biasing to providing adequate accuracy for ADCs, DACs, VFCs, and other building
blocks. In this tutorial, bandgap reference (BGR) fundamentals and the design of CMOS BGRs
will be covered. Topics include classic BGRs, op-amp based and non-op-amp based BGRs;
BGRs with and without output buffers; stability issues arose from negative and positive feedback; loop-gain function and power-supply rejection; startup issues, trimming and design ofresistor strings. Advanced topics include curvature compensation, sub-1V references, micropower references, and alternatives to bandgap references such as fully CMOS references andresistor-less references.

Instructor: Wing-Hung Ki
Wing-Hung Ki received his B.Sc. from UCSD (1984), M.Sc. from Caltech (1985), and Ph.D. from
UCLA (1995), all in electrical engineering. From 1992 to 1995, he worked for Micro Linear, San
Jose, on the design of power converter controllers. He joined the Hong Kong University of Scienceand Technology (HKUST) in 1995, and is currently a professor of the Department of Electronic andComputer Engineering. His research interests are IC techniques for power management circuits,
power transponders for RFID and energy harvesting applications, and fundamental research inswitching converters and charge pumps.

T10: Data and Power Telemetry for Implants
Power and data telemetry are mandatory components for all implantable systems. Especiallymultichannel recorders and stimulators require both large power and high data rates.
Nonetheless, in many systems the telemetry is just implemented with a holistic approach,but not analyzed in large detail. Based on the fact that most implantable devices dissipate
the largest amount of power in the telemetry subsystem, a careful design or even active adaptability of the link are thought necessary in order to provide high energy-efficiency as well as
to meet with regulatory compliance. Still today, most systems use RF data telemetry andsuffer from large power consumption. Power delivery is mostly done without feedback control, or batteries are employed. On the emerging side, power efficient data transfer using UWB
or non-RF telemetry, such as optical or ultrasonic approaches have shown to be excellent alternatives. Feedback controlled power telemetry or energy harvesting systems have shownhigh efficiency. This tutorial will give an overview and design guidelines for high-efficiency
data and power telemetry for implantable systems. It first reviews the common RF based approaches, and secondly highlights new approaches such as energy harvesting and non-RF
communication.

Instructor: Maurits Ortmanns
Maurits Ortmanns received the Dipl.-Ing. in Electrical Engineering from Saarland University, Germany and the Dr.-Ing. from IMTEK, University of Freiburg, Germany in 1999, and 2004, respectively.
From 2004-2005 he was with sciworx GmbH, Hannover, Germany as a project leader in mixedsignal electronics. From 2006-2007 he was Assistant Professor for Integrated Interface Circuits at
the University of Freiburg, Germany, and since 2008 he is full Professor and Director of the Instituteof Microelectronics at the University of Ulm, Ulm, Germany. His research interests include mixedsignal integrated circuit design, self-correcting and reconfigurable analog circuits, with special emphasis on data converters and biomedical applications. He served as program committee memberof ESSCIRC, DATE, ECCTD, ICECS, as Associate Editor of IEEE TCAS I, and is currently a programcommittee member of ISSCC. He holds several patents, is coauthor of the book “Continuous-Time
Sigma-Delta A/D Conversion”, and published more than 120 IEEE journal and conference papers.

7

2013_Mini_AP_AP 11/8/12 9:57 AM Page 8

Sunday February 17th, 8:00 AM

FORUM

F1: Advanced RF Transceiver Design Techniques
Organizer:
Co-Organizer:

Albert Jerng, Mediatek, Hsinchu, Taiwan
Yorgos Palaskas, Intel, Hillsboro, OR

Committee:

Eric Klumperink, University of Twente, Enschede, Netherlands
Didier Belot, STMicroelectronics, Crolles, France
Songcheol Hong, KAIST, Daejeon, Korea
Brian Floyd, North Carolina State University, Raleigh, NC

Radio-frequency performance is limited by fundamental constraints in dynamic range, as
CMOS scaling continues to push supply voltages lower. The receiver needs to reject large
in-band and out-of-band blockers while detecting small desired signals. The transmitter
needs to maintain high efficiency and low distortion, while processing signals with wider
bandwidths and higher peak-to-average ratios to support high data rates. Recent developments in RF transceiver design utilize techniques that cancel noise and distortion in receiverand transmitter signal paths. Digital circuits and calibration are increasingly being used toaid radio performance and allow area reduction. This Forum will present advanced circuitdesign techniques that demonstrate the current state-of-the-art. System specifications will
be discussed to provide context for the required circuit enhancements. The first three talks
will focus on noise and distortion cancellation techniques used in receivers. The next three
talks will focus on transmitter design including both digital and analog linearization techniques. Finally, the last talk will introduce in-device co-existence issues and solutions for wireless systems that require multiple radios operating concurrently. This Forum is aimed atcircuit designers and engineers active in radio-transceiver and wireless-system design.

Agenda
Time
08:00

Topic
Breakfast

08:20

Introduction
Albert Jerng, Mediatek, Hsinchu,Taiwan

08:30

Flexible and Linear RX Architectures
Tajinder Manku, Consultant, Waterloo, Canada

09:20

Noise- and Distortion Cancellation for RX Front-Ends
Asad Abidi, University of California, Los Angeles, CA

10:10

Break

10:30

Interference Cancellation Using Frequency Translated Filtering
Ahmad Mirzaei, Broadcom, Irvine, CA

11:20

Transmitter Linearization Using Digital Pre-DistortionPeter Asbeck, University of California, San Diego, CA

12:15

Lunch

13:30

Digital Transmitters for Wireless Applications
Chih-Ming Hung, MStar, Hsinchu, Taiwan

14:20

PA Linearization and Efficiency Enhancement
Patrick Reynaert, KU Leuven, Leuven, Belgium

15:10

Break

15:40

In-Device Multi-Standard Co-Existence
Leif Willhelmsson, Ericsson, Lund, Sweden

16:30

Closing Remarks8

2013_Mini_AP_AP 11/8/12 9:57 AM Page 9

Sunday February 17th, 8:00 AM

FORUM

F2: VLSI Power-Management Techniques: Principles and Applications
Organizer/Chair:
Co-Chair:Leland Chang, IBM, Yorktown Heights, NY
Shannon Morton, NVIDIA, Bristol, United Kingdom

Committee:

Ken Chang, Xilinx, San Jose, CA
Leland Chang, IBM, Yorktown Heights, NY
Jin-Man Han, Samsung, Hwasung, Korea
Piero Malcovati, University of Pavia, Pavia, Italy
Shannon Morton, NVIDIA, Bristol, United Kingdom
Vladimir Stojanovic, MIT, Cambridge, MA

Across the spectrum of microelectronics applications, power management is critical to enabling of power-efficient products. This Forum will provide practicing circuit designers witha summary of power-management techniques, including perspectives from a wide range of
product applications, and an outlook for the future in the context of coming challenges. The
first four speakers in this Forum will present the general principles in development today, including power-gating and state-retention modes, PLL/DLL techniques for dynamic frequency
scaling, integrated voltage regulators for dynamic voltage scaling, and low-power signaling.
In the second half, four speakers representing different industry perspectives, including microprocessors, consumer electronics, microcontrollers and mobile, and DRAM, will utilize
practical case studies to detail current usage of power-management techniques and speculate
on future trends.

Agenda
Time
08:00

Topic
Breakfast

08:20

Introduction
Leland Chang, IBM, Yorktown Heights, NY

08:30

Advanced Power-Gating and State-Retention Approaches to Leakage-Power
ReductionDavid Flynn, ARM, Cambridge, United Kingdom

09:20

Clocking Techniques for Dynamic Frequency Scaling
Jaeha Kim, Seoul National University, Seoul, Korea

10:10

Break

10:35

Dynamic Voltage Scaling Using On-Chip Voltage Regulation
Gu-Yeon Wei, Harvard University, Cambridge, MA

11:25

Power Management in High-Performance I/O
Jared Zerbe, Rambus, Sunnyvale, CA

12:15

Lunch

13:20

Fine-Grain Power Management in Microprocessors
Vivek De, Intel, Hillsboro, OR

14:10

A Key to Power Management for Digital Consumer Applications
Yukihiro Urakawa, Toshiba, Kawasaki, Japan

15:00

Break

15:20

Embedded Power-Management Solutions for Ultra-Low-Power SoCs:
Implementation Examples of Radio-Connected Microcontrollers andMobile-Application Microprocessors
Frédéric Hasbani, ST Microelectronics, Crolles, France

16:10

Power-Management Techniques in DRAM Design
Sangho Shin, Samsung, Hwasung, Korea

17:00

Closing remarks9

2013_Mini_AP_AP 11/8/12 9:57 AM Page 10

EVENING SESSIONS

Sunday February 17th, 7:30 PM

ES1: STUDENT RESEARCH PREVIEW (SRP)The Student Research Preview (SRP) will highlight selected student research projects
in progress. The SRP consists of 23 one-minute presentations followed by a Poster
Session, by graduate students from around the world, which have been selected on thebasis of a short submission concerning their on-going research. Selection is based on
the technical quality and innovation of the work. This year, the SRP will be presented inthree sessions: Data Converters and Analog Circuit Techniques; Circuits and Systems
for Bio-medical Applications; Memory, Digital, MEMS, and PLL IPs.
The Student Research Preview will begin with a brief talk by the distinguished circuitdesigner and entrepreneur, Dr. Nicky Lu, Etron Technologies. His talk on “Research with
Innovation is Power for Promising Career Growth” is scheduled for Sunday, February
17th, starting at 7:30pm, and is open to all ISSCC registrants.

Chair:
Co-Chair:
Co-Chair:

Jan Van der Spiegel University of Pennsylvania, USA
SeongHwan Cho
KAIST, Korea
Eugenio Cantatore
Eindhoven University of Technology,
The Netherlands
Secretary:
Tsung-Hsien Lin
National Taiwan University, Taiwan
Advisor:Kenneth C. Smith
University of Toronto, Canada
Media/Publications: Laura Fujino
University of Toronto, Canada
A/V:John Trnka
Rochester, MN

COMMITTEE MEMBERS
Bryan Ackland
Bharadwaj Amrutur
Andrea Baschirotto
Bevan Baas
Jean-Baptiste Begueret
William Bowhill
Eugenio Cantatore
Brian Lum Shue Chan
SeongHwan Cho
Denis Daly
Andreas Demosthenous
Vasantha Erraguntla
Vincent Gaudet
Makoto Ikeda
Takayuki Kawahara
Jaeha Kim
Tsung-Hsien Lin
Shen-Iuan Liu
Dejan Markovic’
Akira Matsuzawa
Shahriar Mirabbasi
Sameer Sonkusale
Jan Van der Spiegel
Marian Verhelst
Zhihua Wang
Jeff Weldon

Stevens Institute of Technology, USA
India Institute of Science, India
University of Milan-Bicocca, Italy
University of California, Davis, USA
IMS Labs, FranceIntel, USA
Eindhoven University of Technology, The Netherlands
Texas Instruments, USA
KAIST, Korea
Cambridge Analog Technologies, USA
University College London, UK
Intel, India
University of Waterloo, Canada
University of Tokyo, Japan
Hitachi, Japan
Seoul National University, Korea
National Taiwan University, Taiwan
National Taiwan University, Taiwan
University of California, Los Angeles, USA
Tokyo Institute of Technology, Japan
University of British Columbia, Canada
Tufts University, USA
University of Pennsylvania, USA
Kath. University of Leuven, Belgium
Tsinghua University, P.R. China
Carnegie Mellon University, USA

10

2013_Mini_AP_AP 11/8/12 9:57 AM Page 11

EVENING SESSIONS

Sunday February 17th, 8:00 PM

ES2:“Batteries Not Included.” – How Little is Enoughfor Real Energy Autonomy?

Organizer:

Minkyu Je, Institute of Microelectronics, A*STAR, Singapore
Axel Thomsen, Silicon Laboratories, Austin, TX

Chair:

Axel Thomsen, Silicon Laboratories, Austin, TX
Minkyu Je, Institute of Microelectronics, A*STAR, Singapore

Much has been said about energy scavenging and much has also been said about low power
circuitry**. It’s a bit analogous to Woody Allen’s movie Annie Hall *. But the goal of energy
autonomy depends on both sides of the equation. The aim of this evening session is to present
the theoretical and practical issues from both sides, add in some system-level techniques,
and then follow up with debate on the issues relating to getting realistic energy autonomy.
How much do you have to generate? How much are you allowed to consume? Can anyone
agree?
(* For younger and/or more naive readers, the numerical value of 3 times a week wasconsidered either “hardly ever” or “constantly” depending on one’s point of view.)** A wide gap exists between the amount of energy that the current technology can harvest,
and the energy needed to operate state-of-the-art low-power circuits
Time

Topic

8:00

Energy Harvesting: Fundamental Limits and Real-World Implementation
Sywert Brongersma, Holst Centre/imec, Eindhoven, Netherlands

8:30

An Energy-Centric Design Approach to Achieve Nanowatt Microsystems
Dennis Sylvester, University of Michigan, Ann Arbor, MI

9:00

Ultra-Low-Power Analog Design: Towards True Energy Autonomy
Jerald Yoo, Masdar Institute of Science and Technology,
Abu Dhabi, UAE

9:30

Duty Cycling of Analog and Mixed-Signal Circuits: A Straightforward Solution
for Significant Power Consumption Reduction?
Christian Enz, CSEM and EPFL, Neuchâtel, Switzerland

11

2013_Mini_AP_AP 11/8/12 9:57 AM Page 12

SESSION 1

Monday February 18th, 8:30 AM
Plenary Session — Invited Papers

Chair: Anantha Chandrakasan, Massachusetts Institute of Technology, Cambridge, MA
ISSCC Conference Chair
Associate Chair:
Bram Nauta, University of Twente, Enschede, The Netherlands
ISSCC Program Committee Chair

FORMAL OPENING OF THE CONFERENCE
1.1“Architecting the Future through Heterogeneous Computing”

8:30AM
8:45AM

Lisa Su, Senior Vice President and General Manager,
Global Business Units, AMD, Austin, TX, USA
Heterogeneous computing is changing the way system designers, software developers, andend users, are creating and experiencing the future of technology. The most-compelling
emerging algorithms are parallel in nature rather than serial CPU-centric. Virtually every computing device – whether smartphone, tablet, or PC – is transitioning to a new world: withsmaller, lighter, and cooler form factors; with more media and less text; with higher DPI
screens and high-definition video; and with a transformation from traditional user interfaces
to more-natural ones, involving touch and gesture recognition.
This metamorphosis opens up tremendous opportunity for computing to impact today’s
norms,.where most parallel code still runs on CPUsthat are optimizedfor scalar workloads.
Such mismatches are highly inefficient and wastes a tremendous amount of power. Similarly,
video and multimedia content is best handled by parallel processing, and GPUs are much
more efficient at running those workloads. In general, the key to efficient affordable optimized
computing is running the right workload on the right processor at the right time. This talkaddresses the industry’s efforts to accelerate the adoption of heterogeneous computing, andexpands upon the benefits that the end users can expect from these advances in our every
day lives.

1.2“Smart Life Solutions” from Home to City

9:20AM

Yoshiyuki Miyabe, Managing Director and CTO,
Panasonic, Osaka, Japan
It has been predicted that the global demand for electricity will be twice the current level by2035. In this event, even efficient use of resources can ensure only a limited energy supply.
This energy bottleneck is one of the serious social issues in our future. Meanwhile, otherinter-related developments proceed: electronic products are becoming increasingly sophisticated; users are aging; and, as a result, the demand for user-friendly interfaces is growing.
To resolve these social issues, we are working to provide “Smart Life Solutions”, which support both the eco-solution concept of intelligent energy saving, and the smart-solution conceptof providing products and services optimized for individual lifestyles, by means of informationand communication technology.
In the history of consumer electronics, evolving component technology has driven functional
evolution: Television is a good example of this. We entered this arena in 1952, with a 17-inch
black-and-white TV that contained 22 vacuum tubes. Subsequently, advances in components(transistors, ICs, microprocessors, and system LSIs), directly enabled the progress of TV
sets to color, satellite, analog high definition, digital high definition, 3D, and Smart. The latest
3D and Smart TVs include system LSIs in 40-nm CMOS that contain 700 million transistors
operating at 1 GHz. It is not an exaggeration to say that all growth in digital products has
been driven by the progress in semiconductor technology.
In this talk, I will introduce examples of “Smart Life Solutions”: Smart Homes to provide safe
and comfortable living environments while saving energy; Smart Surveillance to provide safe
and intelligent retail environments; Smart Mobility to provide more convenient transportation- automobiles with lower environmental impact; and Smart Cities to provide lifestyle values
through comprehensive town planning .

12

2013_Mini_AP_AP 11/8/12 9:57 AM Page 13

SESSION 1

Monday February 18th, 9:55 AM

To achieve these solutions, key developments include advanced sensing technology, communications technology (which has drastically reduced costs), and power-device technology(which contributes to energy saving). These developments are all supported by innovative
semiconductor technology.
This talk will also introduce initiatives for applying semiconductor technology to new fields,with examples from our research and development activities such as artificial photosynthesis.
As well, it will describe expectations for the evolution of semiconductor technology.

ISSCC, SSCS, IEEE AWARD PRESENTATIONS

9:55AM

BREAK

10:25AM

1.3

Continuing to Shrink: Next-Generation Lithography Progress and Prospects

10:40AM

Martin van den Brink, Executive Vice President and Chief
Product & Technology Officer, ASML, Veldhoven, The Netherlands
Optical lithography has been the key manufacturing technology for integrated-circuit production, enabling a million-fold reduction in average transistor length over 50 years. The development of projection scanners, step and repeat tools, and now, step and scan systems at
higher numerical apertures and shorter wavelengths have led to today’s main lithographic
production tool: the 193nm immersion scanner. With 20nm half-pitch fabrication, at half theeffective resolution limit, it is necessary to use multiple patterning, either through pattern
splitting and multiple exposures, or through a self-aligned spacer process. This leads to one
of two consequences: on the one hand, to a significant increase in the number of mask levels,
process cost, and manufacturing complexity; and, on the other hand, to significant layout restrictions which require closer collaboration between semiconductor design and manufacturing for optimal imaging results and high yield. Even so, for lithography systems to achievethese small resolutions, there are other requirements: a sharp increase in process overlay
to achieve nanometer-specific positioning of the projected image on the silicon wafer); andCritical Dimension Uniformity (CDU) ( to specify the nanometer consistency of the projected
image). Computational lithography and high-speed diffraction-based metrology are needed
to meet these challenges. To relax the complexity of the double-patterning process and layout
restrictions, EUV lithography has been developed to support 1x-nm logic and memory fabrication, and has been demonstrated to meet imaging and overlay requirements. The major
challenge remaining is productivity!

1.4

The Evolution of Technology

11:15AM

Carver Mead, Professor Emeritus, Caltech, Pasadena, CA, USA
Faraday’s Law of induction gave us generators, motors, telegraph, telephone, etc. The vacuum
tube gave us long-distance telephone, radio, hi-fi audio, television, and early computers. Microcircuits have given us personal computers, cell phones, the Internet, and GPS positioning.
Now, What?

PRESENTATION TO PLENARY SPEAKERS

11:50AMCONCLUSION

11:55AM

13

2013_Mini_AP_AP 11/8/12 9:57 AM Page 14

SESSION 2

Monday February 18th, 1:30 PM

Ultra-High-Speed Transceivers and Equalizers
Session Chair: Ken Chang, Xilinx, San Jose, CA
Associate Chair: Hisakatsu Yamaguchi, Fujitsu Laboratories, Kawasaki, Japan

2.1

A 32Gb/s Wireline Receiver with a Low-Frequency
Equalizer, CTLE and 2-Tap DFE in 28nm CMOS

1:30 PMS. Parikh1, T. Kao1, Y. Hidaka1, J. Jiang1, A. Toda1, S. Mcleod1, W. Walker1, Y. Koyanagi2,
T. Shibuya2, J. Yamada3
1
Fujitsu Laboratories of America, Sunnyvale, CA; 2Fujitsu Laboratories, Kawasaki, Japan
3
Fujitsu, Kawasaki, Japan

2.2

A 66Gb/s 46mW 3-Tap Decision-Feedback Equalizer
in 65nm CMOS

2:00 PM

Y. Lu, E. Alon, University of California, Berkeley, CA

2.3

A Sub-2W 39.8-to-44.6Gb/s Transmitter and Receiver
Chipset with SFI-5.2 Interface in 40nm CMOS

2:30 PM

B. Raghavan, D. Cui, U. Singh, H. Maarefi, D. Pi, A. Vasani, Z. Huang, A. Momtaz, J. Cao
Broadcom, Irvine, CA

Break
2.4

A 195mW / 55mW Dual-Path Receiver AFE for Multistandard
8.5-to-11.5 Gb/s Serial Links in 40nm CMOS

3:00 PM
3:15 PMB. Zhang, A. Nazemi, A. Garg, N. Kocaman, M. R. Ahmadi, M. Khanpour,
H. Zhang, J. Cao, A. Momtaz
Broadcom, Irvine, CA

2.5

32Gb/s Data-Interpolator Receiver with 2-Tap DFE
in 28nm CMOS

3:45 PM

Y. Doi1, T. Shibasaki1, T. Danjo1, W. Chaivipas1, T. Hashida1, H. Miyaoka2, M. Hoshino3,
Y. Koyanagi1, T. Yamamoto4, S. Tsukamoto1, H. Tamura1
1
Fujitsu Laboratories, Kawasaki, Japan; 2Fujitsu Semiconductor, Yokohama, Japan
3
Fujitsu Microelectronics Solutions, Yokohama, Japan
4
Fujitsu Laboratories of America, Sunnyvale, CA

2.6

A 32-to-48Gb/s Serializing Transmitter Using Multiphase
Sampling in 65nm CMOS

4:15 PMA. A. Hafez, M-S. Chen, C-K. Yang, University of California, Los Angeles, CA

2.7

32Gb/s 28nm CMOS Time-Interleaved Transmitter
Compatible with NRZ Receiver with DFE

4:45 PMY. Ogata1, Y. Hidaka2, Y. Koyanagi1, S. Akiya3, Y. Terao3, K. Suzuki1, K. Kashiwa4,
M. Suzuki4, H. Tamura1
1
Fujitsu Laboratories, Kawasaki, Japan; 2Fujitsu Laboratories of America, Sunnyvale, CA
3
Fujitsu, Kawasaki, Japan; 4Fujitsu Microelectronics Solutions, Akiruno, Japan2.8

A 0.94mW/Gb/s 22Gb/s 2-Tap Partial-Response DFE
Receiver in 40nm LP CMOS

5:00 PMK. Jung1, A. Amirkhany2, K. Kaviani2
1
University of California, Berkeley, CA
2Rambus, Sunnyvale, CA

Conclusion

14

5:15 PM2013_Mini_AP_AP 11/8/12 9:57 AM Page 15

SESSION 3

Monday February 18th, 1:30 PM
Processors

Session Chair: Se-Hyun Yang, Samsung, Yongin, Korea
Associate Chair: Eric Fluhr, IBM, Round Rock, TX

3.1

5.5GHz System z Microprocessor and Multichip Module
1:30 PMJ. Warnock1, Y. H. Chan2, H. Harrer3, D. Rude2, R. Puri4, S. Carey2, G. Salem5, G. Mayer3,
Y-H. Chan2, M. Mayo2, A. Jatkowski2, G. Strevig6, L. Sigal4, A. Datta7, A. Gattiker8,
A. Bansal4, D. Malone2, T. Strach3, H. Wen6, P-K. Mak2, C-L. Shum2, D. Plass2, C. Webb2
1
IBM Systems and Technology Group, Yorktown Heights, NY
2
IBM Systems and Technology Group, Poughkeepsie, NY
DS1
3
IBM Systems and Technology Group, Boeblingen, Germany
4
IBM Research, Yorktown Heights, NY; 5IBM Systems and Technology Group, Williston, VT
6
IBM Systems and Technology Group, Austin, TX
7IBM Systems and Technology Group, Bangalore, India; 8IBM Research, Austin, TX

3.2

A 3.6GHz 16-Core SPARC SoC Processor in 28nm
2:00 PM
J. Hart, S. Butler, H. Cho, Y. Ge, G. Gruber, D. Huang, C. Hwang, D. Jian, T. Johnson,
L. Kwong, R. Masleid, U. Nawathe, A. Ramachandran, Y. Sheng, J. Shin, S. Turullois,
Z. Qin, K. Yen, Oracle, Santa Clara, CA

3.3

A 3.40ms/GF(p521) and 2.77ms/GF(2521) DF-ECC Processor
with Side-Channel Attack Resistance

2:30 PMJ-W. Lee, S-C. Chung, H-C. Chang, C-Y. Lee,
National Chiao Tung University, Hsinchu, Taiwan

Break
3.4

Jaguar: A Next-Generation Low-Power x86-64 Core

3:00 PM
3:15 PMT. Singh, J. Bell, S. Southard, AMD, Austin, TX

3.5

Godson-3B1500: A 32nm 1.35GHz 40W 172.8GFLOPS
8-Core Processor

3:45 PMW. Hu1,2, Y. Zhang1,2, L. Yang2, B. Fan2, Y. Chen1,2, S. Zhong2, H. Wang2, Z. Qi1,2, P. Wang1,2,
X. Gao2, X. Yang2, B. Xiao1,2, H. Wang2, Z. Yang1,2, L. Yang1,2, S. Chen1,2
1
Chinese Academy of Sciences, Beijing, China; 2Loongson Technology, Beijing, China

3.6

A 65nm 39GOPS/W 24-Core Processor with 11Tb/s/W
Packet-Controlled Circuit-Switched Double-Layer
Network-on-Chip and Heterogeneous Execution Array

4:15 PMP. Ou, J. Zhang, H. Quan, Y. Li, M. He, Z. Yu, X. Yu, S. Cui, J. Feng, S. Zhu, J. Lin,M. Jing, X. Zeng, Z. Yu, Fudan University, Shanghai, China

3.7

Bandwidth and Power Management of Glueless 8-Socket
SPARC T5 System

4:30 PM

V. Krishnaswamy1, D. Huang2, S. Turullols1, J. Shin1
Oracle, Santa Clara, CA; 2Oracle, San Diego, CA

1

3.8

A 10th Generation 16-Core SPARC64 Processor for
Mission-Critical UNIX Server

4:45 PMR. Kan1, T. Tanaka1, G. Sugizaki1, R. Nishiyama1, S. Sakabayashi1, Y. Koyanagi2,
R. Iwatsuki1, K. Hayasaka1, T. Uemura3, G. Ito1, Y. Ozeki1, H. Adachi1, K. Furuya1,
T. Motokurumada1
1
Fujitsu, Kawasaki, Japan; 2Fujitsu Laboratories, Kawasaki, Japan
3
Fujitsu Semiconductor, Yokohama, Japan

Conclusion15

5:15 PM2013_Mini_AP_AP 11/8/12 9:57 AM Page 16

SESSION 4

Monday February 18th, 1:30 PM
Harvesting and Wireless Power

Session Chair: Jae-Youl Lee, Samsung, Yongin, Korea
Associate Chair: Saska Lindfors, Texas Instruments, Helsinki, Finland

4.1

A Resonant Regulating Rectifier (3R) Operating at
6.78 MHz for A 6W Wireless Charger with 86% Efficiency

1:30 PM

J-H. Choi1, S-K. Yeo2, C-B. Park1, S. Park2, J-S. Lee2, G-H. Cho1
KAIST, Daejeon, Korea; 2Samsung Electronics, Suwon, Korea

1

4.2

A 13.56MHz Fully Integrated 1X/2X Active Rectifier with
Compensated Bias Current for Inductively Powered Devices

2:00 PM

Y. Lu, X. Li, W-H. Ki, C-Y. Tsui, C. P. Yue,HKUST, Hong Kong, China

4.3

A 400nW Single-Inductor Dual-Input-Tri-Output DC-DC
Buck-Boost Converter with Maximum Power Point
Tracking for Indoor Photovoltaic Energy Harvesting

2:15 PMK. Chew, Z. Sun, H. Tang, L. Siek,
Nanyang Technological University, Singapore, Singapore

4.4

An Adaptive Load-Line Tuning IC for Photovoltaic
Module Integrated Mobile Device with 470µs TransientTime, Over 99% Steady-State Accuracy and 94% Power
Conversion Efficiency

2:30 PM

W-C. Liu, Y-H. Wang, T-H. Kuo,
National Cheng Kung University, Tainan, Taiwan

Break
4.5

A 3.4mW Photovoltaic Energy-Harvesting Charger
with Integrated Maximum Power Point Tracking andBattery Management

3:00 PM
3:15 PMT-H. Tsai, K. Chen,
National Chung Cheng University, Chia-Yi, Taiwan

4.6

A Self-Biased 5-to-60V Input Voltage and 25-to-1600µW
Integrated DC-DC Buck Converter with Fully Analog
MPPT Algorithm Reaching up to 88% End-to-End Efficiency

3:45 PMS. Stanzione1, C. van Liempd1, R. van Schaijk1, Y. Naito2, R. F. Yazicioglu3, C. van Hoof1,4
1
imec - Holst Centre, Eindhoven, The Netherlands; 2Panasonic, Osaka, Japan3
imec, Leuven, Belgium; 4KU Leuven, Leuven, Belgium

4.7

A 1µW-to-1mW Energy-Aware Interface IC for
Piezoelectric Harvesting with 40nA Quiescent Current
and Zero-Bias Active Rectifiers

4:15 PMC. van Liempd1, S. Stanzione1, Y. Allasasmeh1, C. van Hoof2,3
1
imec - Holst Centre, Eindhoven, The Netherlands
2
imec, Heverlee, Belgium; 3KU Leuven, Leuven, Belgium

4.8

A Single-Inductor 0.35µm CMOS Energy-Investing
Piezoelectric Harvester

4:45 PM

D. Kwon, G. A. Rincon-MoraGeorgia Institute of Technology, Atlanta, GA

Conclusion
16

5:15 PM2013_Mini_AP_AP 11/8/12 9:57 AM Page 17

Monday February 18th, 1:30 PM

SESSION 5

RF Techniques
Session Chair: Mike Keaveney, Analog Devices, Limerick, Ireland
Associate Chair: Joseph Golat, Motorola, Schaumburg, IL

5.1

SAW-Less Analog Front-End Receivers for TDD and FDD

1:30 PMI. Fabiano1, M. Sosio1, A. Liscidini1,2, R. Castello1
1
University of Pavia, Pavia, Italy2*Now at the University of Toronto, Toronto, ON, Canada

5.2

Simultaneous Spatial and Frequency-Domain Filtering
at the Antenna Inputs Achieving up to +10dBm
Out-of-Band/Beam P1dB

2:00 PMA. Ghaffari, E. E. Klumperink, F. van Vliet, B. Nauta
University of Twente, Enschede, The Netherlands

5.3

A Phase-Noise and Spur Filtering Technique Using
Reciprocal-Mixing Cancellation

2:30 PM

M. Mikhemar, D. Murphy, A. Mirzaei, H. Darabi
Broadcom, Irvine, CA

Break
5.4

A 30.3dBm 1.9GHz-Bandwidth 2×4-Array Stacked
5.3GHz CMOS Power Amplifier

3:00 PM
3:15 PMM. Fathi, D. K. Su, B. A. Wooley
Stanford University, Stanford, CA

5.5

A 1.8GHz Linear CMOS Power Amplifier with
Supply-Path Switching Scheme for WCDMA/LTE
Applications

3:45 PM

K. Onizuka, S. Saigusa, S. Otaka
Toshiba, Kawasaki, Japan

5.6

A New TX Leakage-Suppression Technique for an
RFID Receiver Using a Dead-Zone Amplifier

4:15 PM

S-S. Lee1, J. Lee2, I-Y. Lee1, S-G. Lee1, J. Ko2
1
KAIST, Daejeon, Korea
2
PHYCHIPS, Daejeon, Korea

5.7

A 200mW 100MHz-to-4GHz 11th-Order Complex
Analog Memory Polynomial Predistorter for
Wireless Infrastructure RF Amplifiers

4:45 PMF. Roger
Scintera, Sunnyvale, CA

Conclusion

17

5:15 PM2013_Mini_AP_AP 11/8/12 9:57 AM Page 18

SESSION 6

Monday February 18th, 1:30 PM

Emerging Medical and Sensor Technologies
Session Chair: David Ruffieux, CSEM, Neuchatel, Switzerland
Associate Chair: Yogesh Ramadass, Texas Instruments, Dallas, TX

6.1

An 87mA·min Iontophoresis Controller IC with Dual-Mode
Impedance Sensor for Patch-Type Transdermal Drug
Delivery System

DS1

K. Song, U. Ha, J. Lee, K. Bong, H-J. Yoo
KAIST, Daejeon, Korea

6.2

1:30 PM

A 1.83µJ/Classification Nonlinear Support-VectorMachine-Based Patient-Specific Seizure Classification SoC

2:00 PM

M. Altaf, J. Tillak, Y. Kifle, J. Yoo
Masdar Institute of Science and Technology, Abu Dhabi, United Arab Emirates

6.3

Through-Silicon-Via-Based Double-Side Integrated
Microsystem for Neural Sensing Applications

2:30 PM

C-W. Chang1, P-T. Huang1, L-C. Chou1, S-L. Wu1, S-W. Lee1, C-T. Chuang1, K-N. Chen1,
J-C. Chiou1,2, W. Hwang1,3, Y-C. Lee3, C-H. Wu3, K-H. Chen3, C-T. Chiu3, H-M. Tong3
1
National Chiao Tung University, Hsinchu, Taiwan
2
China Medical University, Taichung, Taiwan
3Advanced Semiconductor Engineering Group, Kaohsiung, Taiwan

Break
6.4 1µm-Thickness 64-Channel Surface Electromyogram
Measurement Sheet with 2V Organic Transistors for
Prosthetic Hand Control

3:00 PM
3:15 PM

H. Fuketa1,2, K. Yoshioka1,2, Y. Shinozuka1,2, K. Ishida1,2, T. Yokota1,2, N. Matsuhisa1,2,
Y. Inoue1,2, M. Sekino1,2, T. Sekitani1,2, M. Takamiya1,2, T. Someya1,2, T. Sakurai1,2
1
University of Tokyo, Tokyo, Japan; 2JST/ERATO, Tokyo, Japan

6.5

A 4b ADC Manufactured in a Fully-Printed Organic
Complementary Technology Including Resistors

3:45 PM

S. Abdinia1, M. Benwadih2, R. Coppard2, S. Jacob2, G. Maiellaro3, G. Palmisano3, M. Rizzo4,
A. Scuderi4, F. Tramontana4, A. van Roermund1, E. Cantatore1
1
Eindhoven University of Technology, Eindhoven, The Netherlands
2
CEA-LITEN, Grenoble, France; 3University of Catania, Catania, Italy
4
STMicroelectronics, Catania, Italy

6.6

An Organic VCO-Based ADC for Quasi-Static Signals
Achieving 1LSB INL at 6b Resolution

4:00 PMD. Raiteri1, P. van Lieshout2, A. van Roermund1, E. Cantatore1
1
Eindhoven University of Technology, Eindhoven, The Netherlands
2
Polymer Vision, Eindhoven, The Netherlands

6.7

A 1024×8 700ps Time-Gated SPAD Line Sensor for Laser
Raman Spectroscopy and LIBS in Space and Rover-Based
Planetary Exploration

4:15 PMY. Maruyama1, J. Blacksberg2, E. Charbon1
1
Delft University of Technology, Delft, The Netherlands
2
Jet Propulsion Laboratory, Pasadena, CA

6.8

Experimental Demonstration of a Fully Digital Capacitive
4:45 PM
Sensor Interface Built Entirely Using Carbon-Nanotube FETs
M. Shulaker1, J. van Rethy2, G. Hills1, H-Y. Chen1, G. Gielen2, H-S. Wong1, S. Mitra1
1
Stanford University, Stanford, CA; 2KU Leuven, Heverlee, Belgium

DS1

Conclusion
18

5:15 PM2013_Mini_AP_AP 11/8/12 9:57 AM Page 19

DEMONSTRATION SESSION 1 (DS1)*MONDAY, FEBRUARY 18TH 4:00-7:00 PM
This year, the Demonstration Sessions of techniques presented in selected regular papers,
both Academic and Industrial, will take place on two evenings: Monday, February 18 andTuesday, February 19, from 4 pm until 7 pm in the Golden Gate Hall. These demonstrations
will feature real-life applications made possible by new ICs presented at ISSCC 2013, as notedby the symbol, DS1 in the Advance Program. Scheduling details will be provided atwww.isscc.org shortly before the Conference. Meanwhile, a list of the selected papers is asfollows:

Monday, February 18th
3.1

5.5GHz System z Microprocessor and Multichip Module

1:30 PM

6.1

An 87mA·min Iontophoresis Controller IC with Dual-Mode
Impedance Sensor for Patch-Type Transdermal Drug
Delivery System

1:30 PM

6.8

4:45 PM
Experimental Demonstration of a Fully Digital Capacitive
Sensor Interface Built Entirely Using Carbon-Nanotube FETs

Tuesday, February 19th
7.6

A 1.23pJ/b 2.5Gb/s Monolithically Integrated Optical
Carrier-Injection Ring Modulator and All-Digital Driver
Circuit in Commercial 45nm SO

11:15 AM

8.7

A Low-Cost Miniature 120GHz SiP FMCW/CW Radar
Sensor with Software Linearization

11:15 AM9.3

A 0.48V 0.57nJ/Pixel Video-Recording SoC in 65nm CMOS

9:30 AM

9.5

A 249Mpixel/s HEVC Video-Decoder Chip for Quad
Full HD Applications

10:15 AM

9.6

Reconfigurable Processor for Energy-Scalable
Computational Photography

10:45 AM9.8

A 646GOPS/W Multi-Classifier Many-Core Processor
With Cortex-Like Architecture for Super-Resolution
Recognition

11:45 AM10.5 A 4Ω 2.3W Class-D Audio Amplifier with Embedded
DC-DC Boost Converter, Current-Sensing ADC
and DSP for Adaptive Speaker Protection

10:15 AM11.3 A Versatile Timing Microsystem Based on Wafer-Level
Packaged XTAL/BAW Resonators with Sub-µW RTC
Mode and Programmable HF Clocks

9:30 AM11.5 A 0.15mm-Thick Non-Contact Connector for MIPI Using
Vertical Directional Coupler

10:45 AM11.6 1.2Gb/s 3.9pJ/b Mono-Phase Pulse-Modulation
Inductive-Coupling Transceiver for mm-Range
Board-to-Board Communication

11:15 AM

*DS1 may include additional demonstrations of work reported
at the Student Research Preview.

19

2013_Mini_AP_AP 11/12/12 5:51 PM Page 20

EVENING SESSIONS

Monday February 18th, 8:00 PM

EP1:

Antiques from the Innovations Attic

Organizer:

Trudy Stetzler, Texas Instruments, Stafford,TX

Moderators:

Anantha Chandrakasan, Massachusetts Institute of Technology,
Cambridge, MA
Bram Nauta, University of Twente, Enschede, The Netherlands

When you clean up your attic you may find things that you have totally forgotten about: oldtoys you used to play with, old books with lost stories. And then you think back to thosepast days and view them in the context of today’s busy life. This panel does a similar thing;
we have asked 6 experts from academia and industry to dig into their memories and findlost treasures in circuit design. This panel features surprises from the past sixty years (ormore) and the panelists explain why the concept is significant today and should be pulledfrom the innovation attic.

Panelists:
Robert Brodersen, University of California, Berkeley, CA
Rinaldo Castello, University of Pavia, Pavia, Italy
Yoshiaki Daimon Hagihara, Sojo University, Kumamoto, Japan
Thomas Lee, Microsystems Technology Office, DARPA, Arlington, VA
Nicky Lu, Etron Technology, Hsinchu, Taiwan
Eric Vittoz, Independent Consultant, Cernier, Switzerland

20

2013_Mini_AP_AP 11/8/12 9:57 AM Page 21

Tuesday February 19th, 8:30 AM

SESSION 7

Optical Transceivers and Silicon Photonics
Session Chair: Ichiro Fujimori, Broadcom, Irvine, CA
Associate Chair: Masafumi Nogawa, NTT Microsystem Integration Laboratories,
Atsugi, Japan

7.1

A Quad 25Gb/s 270mW TIA in 0.13µm BiCMOS with
<0.15dB Crosstalk Penalty

8:30 AM

G. Kalogerakis, T. Moran, T. Nguyen, G. Denoyer, Finisar, Sunnyvale, CA

7.2

A 4× 25-to-28Gb/s 4.9mW/Gb/s -9.7dBm High-Sensitivity
Optical Receiver Based on 65nm CMOS for Board-to-Board
Interconnects

9:00 AM

T. Takemoto1, H. Yamashita1, T. Yazaki2, N. Chujo2, Y. Lee1, Y. Matsuoka1
1
Hitachi, Tokyo, Japan; 2Hitachi, Kanagawa, Japan

7.3

100Gb/s Ethernet Chipsets in 65nm CMOS Technology
9:30 AM
J-Y. Jiang1, P-C. Chiang1, H-W. Hung1, C-L. Lin1, T. Yoon2, J. Lee1
1
National Taiwan University, Taipei, Taiwan; 2Basas Microelectronics, Beijing, China
Break

7.4

10:00 AMA Blind Baud-Rate ADC-Based CDR

10:15 AM

C. Ting1, J. Liang1, A. Sheikholeslami1, M. Kibune2, H. Tamura2
1
University of Toronto, Toronto, Canada; 2Fujitsu Laboratories, Kawasaki, Japan

7.5

A Ring-Resonator-Based Silicon Photonics Transceiverwith Bias-Based Wavelength Stabilization and AdaptivePower-Sensitivity Receiver

10:45 AM

C. Li1, R. Bai2, A. Shafik1, E. Zhian Tabasy1, G. Tang1, C. Ma2, C-H. Chen3, Z. Peng3,
M. Fiorentino3, P. Chiang2,4, S. Palermo11Texas A&M University, College Station, TX; 2Oregon State University, Corvallis, OR
3
Hewlett Packard, Palo Alto, CA; 4Fudan University, Shanghai, China

7.6

A 1.23pJ/b 2.5Gb/s Monolithically Integrated Optical
Carrier-Injection Ring Modulator and All-Digital Driver
Circuit in Commercial 45nm SOI
1

1

2

1

DS1

B. R. Moss , C. Sun , M. Georgas , J. Shainline , J. S. Orcutt , J. C. Leu , M. Wade2,
Y-H. Chen1, K. Nammari2, X. Wang1, H. Li1, R. Ram1, M. A. Popovic2, V. Stojanovic1
1
Massachusetts Institute of Technology, Cambridge, MA
2University of Colorado, Boulder, CO

7.7

1

11:15 AM

1

A 20Gb/s NRZ/PAM-4 1V Transmitter in 40nm CMOS
Driving a Si-Photonic Modulator in 0.13µm CMOS

11:30 AM

X. Wu1, B. Dama2, P. Gothoskar2, P. Metz2, K. Shastri2, S. Sunder2, J. van der Spiegel1,
Y. Wang2, M. Webster2, W. Wilson2
1
University of Pennsylvania, Philadelphia, PA; 2Cisco Systems, Allentown, PA

7.8

Optical Receivers Using DFE-IIR Equalization

11:45 AMJ. Proesel, A. Rylyakov, C. Schow, IBM Research, Yorktown Heights, NY

7.9

A 10Gb/s 6Vpp Differential Modulator Driver in 0.18µm
SiGe-BiCMOS

12:00 PMY. Zhao1, L. Vera1, J. R. Long1, D. L. Harame2
1
Delft University of Technology, Delft, The Netherlands; 2IBM, Essex Junction, VT

Conclusion
21

12:15 PM2013_Mini_AP_AP 11/8/12 9:57 AM Page 22

SESSION 8

Tuesday February 19th, 8:30 AM
Millimeter-Wave Techniques

Session Chair: Ullrich Pfeiffer, University of Wuppertal, Wuppertal, Germany
Associate Chair: Gabriel Rebeiz, University of California, San Diego, La Jolla, CA

8.1

A 210GHz Fully Integrated Differential Transceiver with
Fundamental-Frequency VCO in 32nm SOI CMOS

8:30 AM

Z. Wang1, P-Y. Chiang1, P. Nazari1, C-C. Wang2, Z. Chen3, P. Heydari1
University of California, Irvine, CA
2Peregrine Semiconductor, San Diego, CA
3
Beijing Institute of Technology, Beijing, China

1

8.2

A 260GHz Broadband Source with 1.1mW ContinuousWave Radiated Power and EIRP of 15.7dBm in 65nm CMOS

9:00 AM

R. Han, E. Afshari, Cornell University, Ithaca, NY

8.3

A 260GHz Amplifier with 9.2dB Gain and -3.9dBm
Saturated Power in 65nm CMOS

9:30 AM

O. Momeni, University of California, Davis, CA

8.4

A 0.7W Fully Integrated 42GHz Power Amplifier with
10% PAE in 0.13µm SiGe BiCMOS

9:45 AM

W. Tai1, L. Carley1, D. S. Ricketts2
1
Carnegie Mellon University, Pittsburgh, PA
2
North Carolina State University, Raleigh, NC

Break
8.5

A 93-to-113GHz BiCMOS 9-Element Imaging Array
Receiver Utilizing Spatial-Overlapping Pixels with
Wideband Phase and Amplitude Control

10:00 AM
10:15 AM

F. Caster II, L. Gilreath, S. Pan, Z. Wang, F. Capolino, P. Heydari
University of California, Irvine, CA

8.6

A 94GHz 3D-Image Radar Engine with 4TX/4RX
Beamforming Scan Technique in 65nm CMOS

10:45 AM

P-N. Chen, P-J. Peng, C. Kao, Y-L. Chen, J. Lee
National Taiwan University, Taipei, Taiwan

8.7

A Low-Cost Miniature 120GHz SiP FMCW/CW Radar
Sensor with Software Linearization

11:15 AM

Y. Sun1, M. Marinkovic1, G. Fischer1, W. Winkler2, W. Debski2, S. Beer3, T. Zwick3,
M. G. Girma4, J. Hasch4, C. J. Scheytt51
IHP, Frankfurt Oder, Germany
DS1
2
Silicon Radar, Frankfurt Oder, Germany
3
Karlsruhe Institute of Technology, Karlsruhe, Germany
4
Robert Bosch, Stuttgart, Germany
5
University of Paderborn, Paderborn, Germany

8.8

A 10mW 37.8GHz Current-Redistribution BiCMOS VCO
with an Average FOMT of -193.5dBc/Hz

11:45 AM

Q. Wu1, T. Quach2, A. Mattamana2, S. Elabd1, S. R. Dooley2, J. J. McCue1,
P. L. Orlando2G. L. Creech2, W. Khalil1
1
Ohio State University, Columbus, OH
2
Air Force Research Laboratory, Wright-Patterson AFB, Dayton, OH

Conclusion
22

12:15 PM2013_Mini_AP_AP 11/8/12 9:57 AM Page 23

SESSION 9

Tuesday February 19th, 8:30 AM

Mobile Application Processors and Media Accelerators
Session Chair: Michael Polley, Texas Instruments, Dallas, TX
Associate Chair: Yongha Park, Samsung, Yongin, Korea

9.1

28nm High-κ Metal-Gate Heterogeneous Quad-Core
CPUs for High-Performance and Energy-Efficient
Mobile Application Processor

8:30 AM

Y. Shin1, K. Shin1, P. Kenkare2, R. Kashyap2, H-J. Lee1, D. Seo1, B. Millar2, Y. Kwon1,
R. Iyengar2, M-S. Kim1, A. Chowdhury2, S-I. Bae1, I. Hon1, W. Jeong2, A. Lindner2, U. Cho1,
K. Hawkins2, J. Son1, S. Hwang1
1
Samsung Electronics, Yongin, Korea; 2Samsung Electronics, Austin, TX

9.2

A 28nm High-κ Metal-Gate Single-Chip Communications
Processor with 1.5GHz Dual-Core Application
Processor and LTE/HSPA+-Capable Baseband Processor

9:00 AM

M. Fujigaya1, N. Sakamoto1, T. Koike1, T. Irita1, K. Wakahara1, T. Matsuyama1,
K. Hasegawa1, T. Saito1, A. Fukuda1, K. Teranishi1, K. Fukuoka2, N. Maeda2, K. Nii2,
T. Kataoka1, T. Hattori1
1
Renesas Mobile, Tokyo, Japan; 2Renesas Electronics, Tokyo, Japan9.3

A 0.48V 0.57nJ/Pixel Video-Recording SoC in 65nm CMOS

9:30 AM

T-J. Lin1, C-A. Chien1, P-Y. Chang1, C-W. Chen2, P-H. Wang3, T-Y. Shyu1,
C-Y. Chou2,S-C. Luo2, J-I. Guo3, T-F. Chen3, G. Chuang2, Y-H. Chu2, L-C. Cheng2,
H-M. Su4, C. Jou5, M. Ieong5, C-W. Wu2, J-S. Wang1
1
National Chung Cheng University, Chiayi, Taiwan
DS1
2
Industrial Technology Research Institute, Hsinchu, Taiwan
3
National Chiao Tung University, Hsinchu, Taiwan
4
Andes Technology, Hsinchu, Taiwan; 5TSMC, Hsinchu, Taiwan

9.4

72.5GFLOPS 240Mpixel/s 1080p 60fps Multi-Format
Video Codec Application Processor Enabled withGPGPU for Fused Multimedia Application

9:45 AM

Y. Park, C. Yu, K. Lee, H. Kim, Y. Park, C. Kim, Y. Choi, J. Oh, C. Oh, G. Moon, S. Kim,
H. Jang, J-A. Lee, C. Kim, S. Park
Samsung Electronics, Yongin, Korea
Break
10:00 AM

9.5

A 249Mpixel/s HEVC Video-Decoder Chip for Quad
Full HD Applications

10:15 AM

Reconfigurable Processor for Energy-Scalable
Computational Photography

10:45 AM

DS1
C-T. Huang1, M. Tikekar1, C. Juvekar1, V. Sze2, A. Chandrakasan11Massachusetts Institute of Technology, Cambridge, MA; 2Texas Instruments, Dallas, TX

9.6

R. Rithe1, P. Raina1, N. Ickes1, S. V. Tenneti2, A. P. Chandrakasan1
Massachusetts Institute of Technology, Cambridge, MA
2
California Institute of Technology, Pasadena, CA

1

9.7

DS1

A 470mV 2.7mW Feature Extraction-Accelerator for
Micro-Autonomous Vehicle Navigation in 28nm CMOS

11:15 AM

D. Jeon, Y. Kim, I. Lee, Z. Zhang, D. Blaauw, D. Sylvester
University of Michigan, Ann Arbor, MI

9.8

A 646GOPS/W Multi-Classifier Many-Core Processor
With Cortex-Like Architecture for Super-Resolution
Recognition
J. Park, I. Hong, G. Kim, Y. Kim, K. Lee, S. Park, K. Bong, H-J. Yoo
KAIST, Daejeon, Korea

Conclusion
23

11:45 AMDS1
12:15 PM2013_Mini_AP_AP 11/8/12 9:57 AM Page 24

SESSION 10

Tuesday February 19th, 8:30 AM
Analog Techniques

Session Chair: Jafar Savoj, Xilinx, San Jose, CA
Associate Chair: Chris Mangelsdorf, Analog Devices, Tokyo, Japan10.1 A 0.1-to-1.2GHz Tunable 6th-Order N-Path Channel-SelectFilter with 0.6dB Passband Ripple and +7dBm Blocker
Tolerance

8:30 AM

M. Darvishi, R. van der Zee, B. Nauta, University of Twente, Enschede, The Netherlands

10.2 A 2mW 800MS/s 7th-Order Discrete-Time IIR Filter
with 400kHz-to-30MHz BW and 100dB Stop-Band
Rejection in 65nm CMOS

9:00 AM

M. Tohidian, I. Madadi, R. B. Staszewski
Delft University of Technology, Delft, The Netherlands

10.3 A Multi-Path Chopper-Stabilized Capacitively Coupled
Operational Amplifier with 20V-Input-Common-Mode
Range and 3µV Offset

9:30 AM

Q. Fan, J. Huijsing, K. A. A. Makinwa, Delft University of Technology, Delft, The Netherlands

10.4 A 0.06mm2 14nV/√Hz Chopper Instrumentation Amplifier
with Automatic Differential-Pair Matching

9:45 AM

I. Akita1, M. Ishida1,2
1
Toyohashi University of Technology, Toyohashi, Japan
2
Electronics-Inspired Interdisciplinary Research Institute (EIIRIS), Toyohashi, Japan

Break
10.5 A 4Ω 2.3W Class-D Audio Amplifier with Embedded
DC-DC Boost Converter, Current-Sensing ADC
and DSP for Adaptive Speaker Protection
M. Berkhout, L. Dooper, B. Krabbenborg, J. Somberg
NXP Semiconductors, Nijmegen, The Netherlands

10:00 AM
10:15 AMDS1

10.6 A 62mW Stereo Class-G Headphone Driver with 108dB
Dynamic Range and 600µA/Channel Quiescent Current

10:45 AM

J. Chen1, S. Arunachalam1, T. L. Brooks1, I. Mehr1, F. Cheung1, H. Venkatram2
1
Broadcom, Irvine, CA; 2Oregon State University, Corvallis, OR

10.7 A 120nW 18.5kHz RC Oscillator with Comparator
Offset Cancellation for ±0.25% Temperature Stability

11:00 AM

A. Paidimarri1, D. Griffith2, A. Wang3, A. P. Chandrakasan1, G. Burra2
1
Massachusetts Institute of Technology, Cambridge, MA
2Texas Instruments, Dallas, TX; 3MediaTek, Austin, TX

10.8 A 63,000 Q-Factor Relaxation Oscillator with
Switched-Capacitor Integrated Error Feedback

11:15 AM

Y. Cao1,2, P. Leroux1, W. De Cock2, M. Steyaert1
1
KU Leuven, Heverlee, Belgium; 2SCK-CEN, Mol, Belgium

10.9 A 0.45V 423nW 3.2MHz Multiplying DLL with LeakageBased Oscillator for Ultra-Low-Power Sensor Platforms

11:45 AM

D-W. Jee1, D. Sylvester2, D. Blaauw2, J-Y. Sim1
Pohang University of Science and Technology, Pohang, Korea
2
University of Michigan, Ann Arbor, MI

1

Conclusion
24

12:15 PM2013_Mini_AP_AP 11/8/12 9:57 AM Page 25

Tuesday February 19th, 8:30 AM

SESSION 11

Emerging Memory and Wireless Technology
Session Chair: Fu-Lung Hsueh, TSMC, Hsinchu, Taiwan
Associate Chair: Shinichiro Mutoh, NTT, Atsugi, Japan11.1 A 3.4pJ FeRAM-Enabled D Flip-Flop in 0.13µm CMOS
for Nonvolatile Processing in Digital Systems

8:30 AM

M. Qazi1, A. Amerasekera2, A. P. Chandrakasan11Massachusetts Institute of Technology, Cambridge, MA; 2Texas Instruments, Dallas, TX

11.2 Nonvolatile Logic-in-Memory Array Processor in
90nm MTJ/MOS Achieving 75% Leakage Reduction
Using Cycle-Based Power Gating

9:00 AM

M. Natsui1, D. Suzuki1, N. Sakimura2, R. Nebashi2, Y. Tsuji2, A. Morioka2, T. Sugibayashi2,
S. Miura2, H. Honjo2, K. Kinoshita1, S. Ikeda1, T. Endoh1, H. Ohno1, T. Hanyu1
1
Tohoku University, Sendai, Japan; 2NEC, Tsukuba, Japan

11.3 A Versatile Timing Microsystem Based on Wafer-Level
Packaged XTAL/BAW Resonators with Sub-µW RTC
Mode and Programmable HF Clocks
1

1

1

1

2

9:30 AM

DS1

2

D. Ruffieux , N. Scolari , F. Giroud , T. C. Le , S. Dalla Piazza , F. Staub , K. Zoschke3,
C. A. Manier3, H. Oppermann3, J. Dekker4, T. Suni4, G. Allegato5
1
CSEM, Neuchatel, Switzerland; 2Micro Crystal, Grenchen, Switzerland
3
Fraunhofer IZM, Berlin, Germany; 4VTT, Espoo, Finland
5
STMicroelectronics, Agrate Brianza, Italy

Break

10:00 AM11.4 Microwave Amplification with Nanomechanical Resonators

10:15 AMF. Massel1, T. T. Heikkilä1, J-M. Pirkkalainen1, S-U. Cho1, H. Saloniemi2,
P. J. Hakonen1, M. A. Sillanpää1
1
Aalto University, Espoo, Finland; 2VTT, Espoo, Finland

11.5 A 0.15mm-Thick Non-Contact Connector for MIPI Using
10:45 AM
Vertical Directional Coupler
DS1
W. Mizuhara, T. Shidei, A. Kosuge, T. Takeya, N. Miura, M. Taguchi, H. Ishikuro, T. Kuroda
Keio University, Yokohama, Japan

11.6 1.2Gb/s 3.9pJ/b Mono-Phase Pulse-Modulation
Inductive-Coupling Transceiver for mm-Range
Board-to-Board Communication
H. Cho1, U. Ha1, T. Roh1, D. Kim2, J. Lee2, Y. Oh2, H-J. Yoo1
KAIST, Daejeon, Korea; 2Samsung Electronics, Suwon, Korea

11:15 AMDS1

1

11.7 Retrodirective Transponder Array with Universal
On-Sheet Reference for Wireless Mobile Sensor
Networks Without Battery or Oscillator

11:45 AM

H. Fukuda, T. Terada, T. Kuroda, Keio University, Yokohama, Japan11.8 A Scalable 2.9mW 1Mb/s eTextiles Body Area
Network Transceiver with Remotely Powered
Sensors and Bi-Directional Data Communication

12:00 PMN. V. Desai1, J. Yoo2, A. P. Chandrakasan11Massachusetts Institute of Technology, Cambridge, MA
2
Masdar Institute of Science and Technology, Abu Dhabi, United Arab Emirates

Conclusion25

12:15 PM2013_Mini_AP_AP 11/8/12 9:57 AM Page 26

SESSION 12

Tuesday February 19th, 1:30 PM
Nonvolatile Memory Solutions

Session Chair: Jin-Man Han, Samsung Electronics, Hwasung, Korea
Associate Chair: Daniele Vimercati, Micron Technology, Agrate Brianza, Italy

12.1 A 130.7mm2 2-Layer 32Gb ReRAM Memory Devicein 24nm Technology

1:30 PM

T-Y. Liu1, T. Yan1, R. Scheuerlein1, Y. Chen1, J. Lee1, G. Balakrishnan1, G. Yee1, H. Zhang1, A. Yap1, J. Ouyang1,
T. Sasaki2, S. Addepalli1, A. Al-Shamma1, C-Y. Chen1, M. Gupta1, G. Hilton1, S. Joshi1, A. Kathuria1, V. Lai1,
D. Masiwal1, M. Matsumoto1, A. Nigam1, A. Pai1, J. Pakhale1, C. Siau1, X. Wu1, R. Yin1, L. Peng1, J. Kang1, S. Huynh1,
H. Wang1, N. Nagel3, Y. Tanaka3, M. Higashitani1, T. Minvielle1, C. Gorla1, T. Tsukamoto4, T. Yamaguchi4, M. Okajima4,
T. Okamura4, S. Takase2, T. Hara2, H. Inoue4, L. Fasoli1, M. Mofidi1, R. Shrivastava1, K. Quader1
1
Sandisk, Milpitas, CA; 2Toshiba, Yokohama, Japan; 3Sandisk, Yokkaichi, Japan; 4Toshiba, Yokkaichi, Japan12.2 40nm Embedded SG-MONOS Flash Macros for
Automotive with 160MHz Random Access for Codeand Endurance Over 10M Cycles for Data

2:00 PMT. Kono1, T. Ito1, T. Tsuruda1, T. Nishiyama1, T. Nagasawa1, T. Ogawa1, Y. Kawashima2, H. Hidaka1, T. Yamauchi1
1
Renesas Electronics, Itami, Japan; 2Renesas Electronics, Hitachinaka, Japan12.3 A 6nW Inductive-Coupling Wake-Up Transceiver for
Reducing Standby Power of Non-Contact Memory
Card by 500×

2:30 PMN. Miura, M. Saito, M. Taguchi, T. Kuroda, Keio University, Yokohama, Japan12.4 Time-Differential Sense Amplifier for Sub-80mV Bitline
Voltage Embedded STT-MRAM in 40nm CMOS

2:45 PMM. Jefremow1,2, T. Kern1, W. Allers1, C. Peters1, J. Otterstedt1, O. Bahlous1, K. Hofmann1, R. Allinger1, S. Kassenetter1,
D. Schmitt-Landsiedel2
1
Infineon Technologies, Neubiberg, Germany; 2Technical University Munich, Munich, Germany

Break12.5 A 128Gb 3b/cell NAND Flash Design Using 20nm
Planar-Cell Technology

3:00 PM
3:15 PMG. Naso1, L. Botticchio1, M. Castelli1, C. Cerafogli1, M. Cichocki1, P. Conenna1, A. D’Alessandro1, L. De Santis1,
D. Di Cicco1, W. Di Francesco1, M. Gallese1, G. Gallo2, M. Incarnati1, C. Lattaro1, A. Macerola1, G. Marotta1,
V. Moschiano1, D. Orlandi1, F. Paolini1, S. Perugini1, L. Pilolli1, P. Pistilli2, G. Rizzo2, F. Rori1, M. Rossini1, G. Santin1,
E. Sirizotti1, A. Smaniotto2, U. Siciliani2, M. Tiburzi1, R. Meyer3, A. Goda3, B. Filipiak3, T. Vali1, M. Helm4, R. Ghodsi41
Micron, Avezzano, Italy; 2Micron, Padua, Italy; 3Micron, Boise, ID; 4Micron, San Jose, CA

12.6 Filament Scaling Forming Technique and Level-VerifyWrite Scheme with Endurance Over 107 Cycles in ReRAM

3:45 PM

A. Kawahara1, K. Kawai1, Y. Ikeda1, Y. Katoh1, R. Azuma1, Y. Yoshimoto1, K. Tanabe2, Z. Wei1, T. Ninomiya1,
K. Katayama1, R. Yasuhara1, S. Muraoka1, A. Himeno1, N. Yoshikawa1, H. Murase1, K. Shimakawa1, T. Takagi1,
T. Mikawa1, K. Aono1
1
Panasonic, Kyoto, Japan, 2Panasonic, Nagaokakyo, Japan12.7 A 45nm 6b/cell Charge-Trapping Flash Memory Using
LDPC-Based ECC and Drift-Immune Soft-Sensing Engine

4:15 PM

K-C. Ho1,2, P-C. Fang1, H-P. Li1, C-Y. M. Wang1, H-C. Chang2
1
Macronix, Hsinchu, Taiwan; 2National Chiao Tung University, Hsinchu, Taiwan

12.8 Cycling Endurance Optimization Scheme for 1Mb
STT-MRAM in 40nm Technology

4:30 PM

H-C. Yu, K-C. Lin, K-F. Lin, C-Y. Huang, Y-D. Chih, T-C. Ong, J. Chang, S. Natarajan, L. Tran
TSMC, Hsinchu, Taiwan

12.9 Unified Solid-State-Storage Architecture with NAND Flash
4:45 PM
Memory and ReRAM that Tolerates 32× Higher BER for
DS2
Big-Data Applications
S. Tanakamaru1,2, M. Doi1, K. Takeuchi1, 1Chuo University, Tokyo, Japan; 2University of Tokyo, Tokyo, Japan

Conclusion26

5:15 PM2013_Mini_AP_AP 11/8/12 9:57 AM Page 27

SESSION 13

Tuesday February 19th, 1:30 PM
High-Performance WirelessSession Chair: Brian Floyd, North Carolina State University, Raleigh, NC
Associate Chair: Kenichi Okada, Tokyo Institute of Technology, Tokyo, Japan13.1 A Fully Integrated 60GHz CMOS Transceiver Chipset
Based on WiGig/IEEE802.11ad with Built-In Self
Calibration for Mobile Applications

1:30 PMDS2

T. Tsukizawa, N. Shirakata, T. Morita, K. Tanaka, J. Sato, Y. Morishita, M. Kanemaru,
R. Kitamura, T. Shima, T. Nakatani, K. Miyanaga, T. Urushihara, H. Yoshikawa,
T. Sakamoto, H. Motozuka, Y. Shirakawa, N. Yosoku, A. Yamamoto, R. Shiozaki, N. Saito
Panasonic, Yokohama, Japan13.2 A Digitally Modulated mm-Wave Cartesian Beamforming
Transmitter with Quadrature Spatial Combining

2:00 PMJ. Chen1, L. Ye1, D. Titz2, F. Gianesello3, R. Pilard3, A. Cathelin3, F. Ferrero2,
C. Luxey2, A. M. Niknejad1
1
University of California, Berkeley, CA; 2University of Nice, Nice, France
3
STMicroelectronics, Crolles, France

13.3 A 50mW-TX 65mW-RX 60GHz 4-Element Phased-Array
Transceiver with Integrated Antennas in 65nm CMOS

2:30 PML. Kong, D. Seo, E. Alon, University of California, Berkeley, CA

13.4 A Low-Power Radio Chipset in 40nm LP CMOS with
2:45 PM
Beamforming for 60GHz High-Data-Rate Wireless Communication
V. Vidojkovic1, V. Szortyka1,2, K. Khalaf1,2, G. Mangraviti1,2, S. Brebels1, W. van Thillo1,
K. Vaesen1, B. Parvais1, V. Issakov1, M. Libois1, M. Matsuo3, J. Long4, C. Soens1,
P. Wambacq1,2
1
imec, Leuven, Belgium; 2Vrije Universiteit, Brussels, Belgium
3Panasonic, Yokohama, Japan; 4Delft University of Technology, Delft, The Netherlands

Break13.5 A Mixed-Signal 32-Coefficient RX-FFE 100-Coefficient
DFE for an 8Gb/s 60GHz Receiver in 65nm LP CMOS

3:00 PM
3:15 PM

C. Thakkar1,2, N. Narevsky1, C. D. Hull2, E. Alon1
1
University of California, Berkeley, CA; 2Intel, Hillsboro, OR

13.6 A 2-to-16GHz 204mW 3mm-Resolution Stepped-Frequency
Radar for Breast-Cancer Diagnostic Imaging in 65nm CMOS

3:45 PM

M. Caruso, M. Bassi, A. Bevilacqua, A. Neviani, University of Padova, Padova, Italy

13.7 A Scalable Direct-Sampling Broadband Radar Receiver
Supporting Simultaneous Digital Multibeam Array in 65nm
CMOS

4:15 PM

C-M. Lai, J-M. Wu, P-C. Huang, T-S. Chu, National Tsing Hua University, Hsinchu, Taiwan

13.8 A Digital Single-Wire Multiswitch (DSWM) ChannelStacking IC in 45nm CMOS for Satellite Outdoor Units

4:45 PMW. Gao1, B. Huff1, K. Hess1, D. Coulibaly2, C. Pala1, J. Cao1, J. Bhatia1, M. Waltari1,
L. Levin1, C. Cathelin2, T. Nouvet2, N. Nidhi1, R. Kodkani1, R. Maeda1, D. Costa1,
J. McFee1, R. Moazzam1, H. Vincent2, P. Durieux2
1
NXP Semiconductors, San Diego, CA; 2NXP Semiconductors, Caen, France

Conclusion27

5:15 PM2013_Mini_AP_AP 11/8/12 9:57 AM Page 28

SESSION 14

Tuesday February 19th, 1:30 PM
Digital PLLs and Building Blocks

Session Chair: Anthony Hill, Texas Instruments, Dallas, TX
Associate Chair: Atsuki Inoue, Fujitsu, Kawasaki, Japan14.1 A 0.022mm2 970µW Dual-Loop Injection-Locked PLL
with -243dB FOM Using Synthesizable All-Digital PVT
Calibration Circuits

1:30 PMW. Deng, A. Musa, T. Siriburanon, M. Miyahara, K. Okada, A. Matsuzawa
Tokyo Institute of Technology, Tokyo, Japan14.2 A 0.032mm2 3.1mW Synthesized Pixel Clock Generator
with 30psrms Integrated Jitter and 10-to-630MHz DCO
Tuning Range

2:00 PMW. Kim1, J. Park2, J. Kim2, T. Kim2, H. Park2, D. Jeong1
1Seoul National University, Seoul, Korea; 2Samsung Electronics, Yongin, Korea

14.3 An All-Digital PLL Using Random Modulation for SSC
Generation in 65nm CMOS

2:30 PM

N. Da Dalt, P. Pridnig, W. Grollitsch, Infineon Technologies, Villach, Austria

14.4 A 0.026mm2 5.3mW 32-to-2000MHz Digital Fractional-N
Phase Locked-Loop Using a Phase-Interpolating
Phase-to-Digital Converter

2:45 PM

T-K. Jang, X. Nan, F. Liu, J. Shin, H. Ryu, J. Kim, T. Kim, J. Park, H. Park
Samsung Electronics, Yongin, Korea

Break
14.5 A 2.5GHz 2.2mW/25µW On/Off-State Power
2psrms-Long-Term-Jitter Digital Clock Multiplierwith 3-Reference-Cycles Power-On Time

3:00 PM
3:15 PMT. Anand, M. Talegaonkar, A. Elshazly, B. Young, P. Hanumolu
Oregon State University, Corvallis, OR

14.6 3D Clock Distribution Using Vertically/HorizontallyCoupled Resonators

3:45 PM

Y. Take, N. Miura, H. Ishikuro, T. Kuroda, Keio University, Yokohama, Japan14.7 All-Digital Hybrid Temperature Sensor Network for
Dense Thermal Monitoring

4:00 PMS. Paek, W. Shin, J. Lee, H-E. Kim, J-S. Park, L-S. Kim, KAIST, Daejeon, Korea

14.8 A 95fJ/b Current-Mode Transceiver for 10mm
On-Chip Interconnect

4:15 PM

S-K. Lee1,2, S-H. Lee1, D. Sylvester3, D. Blaauw3, J-Y. Sim1
Pohang University of Science and Technology, Pohang, Korea
2
Samsung Electronics, Hwasung, Korea
3
University of Michigan, Ann Arbor, MI

1

14.9 Razor-Lite: A Side-Channel Error-Detection Register
for Timing-Margin Recovery in 45nm SOI CMOS

4:45 PMS. Kim, I. Kwon, D. Fick, M. Kim, Y-P. Chen, D. Sylvester
University of Michigan, Ann Arbor, MI

Conclusion28

5:15 PM2013_Mini_AP_AP 11/8/12 9:57 AM Page 29

SESSION 15

Tuesday February 19th, 1:30 PM
Data Converter Techniques

Session Chair: Michael Perrott, Masdar Institute of Science and Technology,
Abu Dhabi, United Arab Emirates
Associate Chair: Geert van der Plas, imec, Leuven-Heverlee, Belgium

15.1 A 28fJ/conv-step CT ΔΣ Modulator with 78dB DR
and 18MHz BW in 28nm CMOS Using a Highly Digital
Multibit Quantizer

1:30 PM

Y-S. Shu, J-Y. Tsai, P. Chen, T-Y. Lo, P-C. Chiu
MediaTek, Hsinchu, Taiwan

15.2 A 2.2/2.7fJ/conversion-step 10/12b 40kS/s SAR ADC
with Data-Driven Noise Reduction

2:00 PMP. Harpe, E. Cantatore, A. van Roermund
Eindhoven University of Technology, Eindhoven, The Netherlands

15.3 A 71dB-SNDR 50MS/s 4.2mW CMOS SAR ADC by
SNR Enhancement Techniques Utilizing Noise

2:30 PMT. Morie, T. Miki, K. Matsukawa, Y. Bando, T. Okumoto, K. Obata, S. Sakiyama, S. Dosho
Panasonic, Moriguchi, JapanBreak
15.4 A 1V 14b Self-Timed Zero-Crossing-Based
Incremental ΔΣ ADC

3:00 PM
3:15 PM

C. Chen, Z. Tan, M. A. Pertijs
Delft University of Technology, Delft, The Netherlands

15.5 A 6.3µW 20b Incremental Zoom-ADC with 6ppm
INL and 1µV Offset

3:45 PMY. Chae1, K. Souri2, K. A. A. Makinwa2
1
Yonsei University, Seoul, Korea
2
Delft University of Technology, Delft, The Netherlands

15.6 A 20b Clockless DAC with Sub-ppm-Linearity
7.5nV/√Hz-Noise and 0.05ppm/°C-Stability

4:15 PMR. C. McLachlan1, A. Gillespie1, M. C. Coln2, D. Chisholm1, D. T. Lee1
1
Analog Devices, Edinburgh, United Kingdom
2
Analog Devices, Wilmington, MA

15.7 A 2.4-to-5.2fJ/conversion-step 10b 0.5-to-4MS/s SAR ADC
with Charge-Average Switching DAC in 90nm CMOS

4:45 PMC-Y. Liou, C-C. Hsieh
National Tsing Hua University, Hsinchu, Taiwan

15.8 Adaptive Cancellation of Gain and Nonlinearity
Errors in Pipelined ADCs

5:00 PMY. Miyahara1, M. Sano1, K. Koyama1, T. Suzuki1, K. Hamashita1, B-S. Song2
1
Asahi Kasei Microdevices, Atsugi, Japan
2
University of California, San Diego, La Jolla, CA

Conclusion29

5:15 PM2013_Mini_AP_AP 11/8/12 9:57 AM Page 30

SESSION 16

Tuesday February 19th, 1:30 PM
Biomedical Circuits & Systems

Session Chair: Refet Firat Yazicioglu, imec, Leuven, Belgium
Associate Chair: TaeChan Kim, Samsung Semiconductor, Yongin, Korea

16.1 A Fully Integrated 8-Channel Closed-Loop NeuralProsthetic SoC for Real-Time Epileptic Seizure Control

1:30 PM

W-M. Chen1, H. Chiueh1, T-J. Chen1, C-L. Ho1, C. Jeng1, S-T. Chang1, M-D. Ker1, C-Y. Lin1,
Y-C. Huang1, C-W. Chou1, T-Y. Fan1, M-S. Cheng1, S-F. Liang2, T-C. Chien2, S-Y. Wu2,
Y-L. Wang2, F-Z. Shaw2, Y-H. Huang2, C-H. Yang1, J-C. Chiou1, C-W. Chang1, L-C. Chou1,
C-Y. Wu1
1
DS2
National Chiao Tung University, Hsinchu, Taiwan
2
National Cheng Kung University, Tainan, Taiwan

16.2 An Implantable 455-Active-Electrode 52-Channel
CMOS Neural Probe

2:00 PM

C. Mora Lopez1, A. Andrei1, S. Mitra1, M. Welkenhuysen1, W. Eberle1, C. Bartic2, R. Puers2,
R. F. Yazicioglu1, G. Gielen2
1imec, Heverlee, Belgium; 2KU Leuven, Heverlee, Belgium

16.3 A 0.45V 100-Channel Neural-Recording IC with
Sub-µW/Channel Consumption in 0.18µm CMOS

2:30 PMD. Han1,2, Y. Zheng1, R. Rajkumar3, G. Dawe3, M. Je2,3
1
Nanyang Technological University, Singapore, Singapore
2
Institute of Microelectronics, Singapore, Singapore
3
National University of Singapore, Singapore, Singapore

16.4 24-Channel Dual-Band Wireless Neural Recorder with
Activity-Dependent Power Consumption

2:45 PMS. Mitra1, J. Putzeys1, F. Battaglia2, C. M. Lopez1, M. Welkenhuysen1, C. Pennartz2,
C. van Hoof1, R. F. Yazicioglu11imec, Leuven, Belgium; 2University of Amsterdam, Amsterdam, The Netherlands

Break16.5 A 37.6mm 1024-Channel High-Compliance-Voltage
SoC for Epiretinal Prostheses
2

3:00 PM
3:15 PMK. Chen, Y-K. Lo, W. Liu, University of California, Los Angeles, CA

16.6 A Fully Intraocular 0.0169mm2/pixel 512-Channel
Self-Calibrating Epiretinal Prosthesis in 65nm CMOS

3:45 PMM. Monge1, M. Raj1, M. Honarvar-Nazari1, H-C. Chang1, Y. Zhao1, J. Weiland2,3,
M. Humayun2,3, Y-C. Tai1, A. Emami-Neyestanak1
1
California Institute of Technology, Pasadena, CA; 2Doheny Eye Institute, Los Angeles, CA
3
University of Southern California, Los Angeles, CA

16.7 A Near-Field-Communication (NFC) Enabled Wireless
4:15 PM
Fluorimeter for Fully Implantable Biosensing Applications DS2
A. D. Dehennis1, M. Mailand2, D. Grice2, S. Getzlaff2, A. E. Colvin1
1

Senseonics, Germantown, MD; 2Zentrum Mikroelektronik Dresden, Dresden, Germany

16.8 An Integrated Magnetic Spectrometer for Multiplexed
Biosensing

4:45 PM

C. Sideris, A. Hajimiri, California Institute of Technology, Pasadena, CA

16.9 A 20µW Intra-Cardiac Signal-Processing IC with 82dB
Bio-Impedance Measurement Dynamic Range and Analog
Feature Extraction for Ventricular Fibrillation Detection

5:00 PMS. Kim1, L. Yan1, S. Mitra1, M. Osawa2, Y. Harada2, K. Tamiya2, C. van Hoof1,3, R. Yazicioglu1
imec, Leuven, Belgium; 2Olympus, Tokyo, Japan; 3KU Leuven, Leuven, Belgium

1

Conclusion30

5:15 PM2013_Mini_AP_AP 11/8/12 9:57 AM Page 31

DEMONSTRATION SESSION 2 (DS2)* TUESDAY, FEBRUARY 19TH 4:00-7:00 PM
This year, the Demonstration Sessions of techniques presented in selected regular papers,
both Academic and Industrial, will take place on two evenings: Monday, February 18 andTuesday, February 19, from 4 pm until 7 pm in the Golden Gate Hall. These demonstrations
will feature real-life applications made possible by new ICs presented at ISSCC 2013, as notedby the symbol, DS2 in the Advance Program. Scheduling details will be provided atwww.isscc.org shortly before the Conference. Meanwhile, a list of the selected papers is asfollows:

Tuesday, February 19th
12.9 Unified Solid-State-Storage Architecture with NAND Flash
Memory and ReRAM that Tolerates 32× Higher BER for
Big-Data Applications

4:45 PM13.1 A Fully Integrated 60GHz CMOS Transceiver Chipset
Based on WiGig/IEEE802.11ad with Built-In Self
Calibration for Mobile Applications

1:30 PM

16.1 A Fully Integrated 8-Channel Closed-Loop NeuralProsthetic SoC for Real-Time Epileptic Seizure Control

1:30 PM

16.7 A Near-Field-Communication (NFC) Enabled WirelessFluorimeter for Fully Implantable Biosensing Applications

4:15 PM

Wednesday, February 20th
17.1 A 6.4Gb/s Near-Ground Single-Ended Transceiver for
Dual-Rank DIMM Memory Interface Systems

8:30 AM23.4 A 5.5Gb/s 5mm Contactless Interface Containing
a 50Mb/s Bidirectional Sub-Channel Employing
Common-Mode OOK Signaling

3:15 PM24.6 Reliable and Energy-Efficient 1MHz 0.4V Dynamically
Reconfigurable SoC for ExG Applications in 40nm LP CMOS

3:45 PM

24.7 An 8MHz 75µA/MHz Zero-Leakage Non-Volatile
Logic-Based Cortex-M0 MCU SoC Exhibiting 100%
Digital State Retention at VDD=0V with <400ns Wakeup
and Sleep Transitions

4:15 PM24.8 A 100GB/s Wide I/O with 4096b TSVs Through an
Active Silicon Interposer with In-Place Waveform Capturing

4:45 PM

25.4 A 1.9nJ/b 2.4GHz Multistandard

2:45 PM(Bluetooth Low Energy/Zigbee/IEEE802.15.6)
Transceiver for Personal/Body-Area Networks

25.7 A 5.5mW IEEE-802.15.6 Wireless Body-Area-Network

3:45 PM

Standard Transceiver for Multichannel
Electro-Acupuncture Application

26.1 A 10.3GS/s 6b Flash ADC for 10G Ethernet Applications

1:30 PM27.7 3D Camera Based on Linear-Mode Gain-Modulated
Avalanche Photodiodes

4:15 PM*DS2 may include additional demonstrations of work reported
at the Student Research Preview.

31

2013_Mini_AP_AP 11/8/12 9:56 AM Page 32

TIMETABLE OF ISSCC 2013 SESSIONS

32

33

2013_Mini_AP_AP 11/8/12 9:57 AM Page 34

EVENING SESSIONS

Tuesday February 19th, 8:00 PM

ES3: High-Speed Communications on 4 Wheels:
What’s in your Next Car?
Organizer:

Nicola Da Dalt, Infineon Technologies, Villach, Austria

Chair:

Ajith Amerasekera, Texas Instruments, Dallas, TX

Communications inside vehicles is experiencing a growing demand due to applications like
infotainment, driver assistance, safety systems and diagnostics, requiring data-rates beyond what is offered by current solutions.
Considering that cabling is the third highest cost factor and the third heaviest component in
the car, there is a clear need to go beyond the current low data-rate solutions and converge
to a high data-rate backbone network. Solutions, both electrical and optical, are being proposed by car-makers and silicon manufacturers. The evening session will give an overview
on the status and outlook on an emerging market that is already shipping 650 million communication ports per year.

Time

Topic

8:00

The Car: Transformation from Mechanical to Electronic Device
Kirsten Matheus and Stefan Sturm, BMW, Munich, Germany

8:25

Wireless Communications In and Around the Car: Status and Outlook
Norikazu Jack Endo, Toyota Info Techn. Center, Tokyo, Japan

8:50

From CAN to BroadR-Reach: the Development of Wireline Technologies
for Automotive Communications
Mehmet Tazebay, Broadcom, Irvine, CA

9:15

Gigabit Ethernet on Reduced Twisted Pair: Leveraging IEEE 802.3 Ethernet
Technologies for Next-Generation Vehicle Communications
Steven B. Carlson, High Speed Design, Portland, OR

9:40

Optical Fiber: The Backbone of Automotive Communication,
Now and Into the Future
Evan Marchman, Microchip Technology, Austin, TX

34

2013_Mini_AP_AP 11/8/12 9:57 AM Page 35

EVENING SESSIONS

Tuesday February 19th, 8:00 PM

EP2: You’re Hired - The Top 25 Interview Questions
for Circuit Designers
Organizer:
Co-Organizer:

Michael P. Flynn, University of Michigan, Ann Arbor, MIJohn Khoury, Silicon Labs, Austin, TX

Moderators:

Michael P. Flynn, University of Michigan, Ann Arbor, MIJohn Khoury, Silicon Labs, Austin, TX

Circuit designers have to survive one or many technical interviews before being hired for their
dream job. Many students and practicing engineers feel confident that they have a strong andintuitive understanding of circuits. However, even the best circuit designers can be stumpedby exotic circuits or through a misunderstanding of fundamental concepts. This panel of industry and academic circuit designers will entertain and challenge the audience and eachother with questions that often arise during job interviews. The audience can judge which interview questions are fair game in the pursuit of the highly coveted mixed-signal integrated
circuit job.

Panelists:
Eric Swanson, Cirrus Logic, Austin, TX
Sanroku Tsukamoto, Fujitsu Laboratories, Kawasaki, Japan
Marcel Pelgrom, Consultant, Helmond, The Netherlands
Beomsup Kim, Qualcomm, Santa Clara, CA
Ali Hajimiri, California Institute of Technology, Pasadena, CA
Behzad Razavi, University of California, Los Angeles, CA

EP3:

Empowering the Killer SoC Applications of 2020

Organizers:

Shekhar Borkar, Intel, Hillsboro, OR
Uming Ko, MediaTek, Austin, TX
Ali Keshavarzi, Cypress, San Jose, CA

Moderators:

Ali Keshavarzi, Cypress, San Jose, CA
Eugenio Cantatore, Eindhoven University, Eindhoven,
The Netherlands

A distinguished panel from global industry and academia will debate the nature of systems
driving the killer applications of 2020. Can we forecast the future killer applications? We have
had the computing revolution, then communications, and now the sensor era. Are sensors
driving the next killer applications? Are there any other revolutions in sight? What circuits
and system innovations can ISSCC bring forward for the next killer applications? What technology elements, device structures and memory architectures are required? Should we continue with silicon technology and find breakthroughs through system architecture, algorithms,
SoC integration and packaging? Or should we prepare for “beyond silicon” technologies? Are
any beyond-silicon technologies realistic for the future?

Panelists:
Atsushi Murase, NTT, Tokyo, Japan
Babak Parviz, Google, Mountain View, CA
J. Augusto de Oliveira, Cypress, San Jose, CA
Simon Segars, ARM, Cambridge, United Kingdom
Raj Yavatkar, Intel, Hillsboro, OR
Jong-Shik Yoon, Samsung, Suwon, South Korea

35

2013_Mini_AP_AP 11/8/12 9:57 AM Page 36

SESSION 17

Wednesday February 20th, 8:30 AM

High-Performance DRAM Interfaces
Session Chair: Yasuhiro Takai, Elpida Memory, Sagamihara, Japan
Associate Chair: James Sung, Etron Technology, Hsinchu, Taiwan

17.1 A 6.4Gb/s Near-Ground Single-Ended Transceiver for
Dual-Rank DIMM Memory Interface Systems

8:30 AM

K. Kaviani1, M. Bucher2, B. Su2, B. Daly2, B. Stonecypher2, W. Dettloff2, T. Stone2,
K. Prabhu3, P. Kumar Venkatesan3, F. Heaton2, R. Kollipara1, Y. Lu1, C. J. Madden1,
J. Eble2, L. Luo2, N. Nguyen1
1
DS2
Rambus, Sunnyvale, CA
2
Rambus, Chapel Hill, NC
3
Rambus, Bangalore, India

17.2 A 27% Reduction in Transceiver Power for Single-Ended
Point-to-Point DRAM Interface with the Termination
Resistance of 4×Z0 at both TX and RX

9:00 AM

S-M. Lee1, J-H. Kim1, J. Kim2, Y. Kim2, H. Lee2, J-Y. Sim1, H-J. Park1
1
Pohang University of Science and Technology, Pohang, Korea
2
Hynix Semiconductor, Icheon, Korea

17.3 A 5.7mW/Gb/s 24-to-240Ω 1.6Gb/s Thin-Oxide DDR
Transmitter with 1.9-to-7.6V/ns Clock-Feathering
Slew-Rate Control in 22nm CMOS

9:30 AM

M. A. Kossel, C. Menolfi, T. Toifl, P. A. Francese, M. Brändli, P. Buchmann, L. Kull,
T. Meyer Andersen, T. Morf
IBM, Rüschlikon, Switzerland

17.4 An Adaptive-Bandwidth PLL for Avoiding NoiseInterference and DFE-Less Fast Precharge
Sampling for over 10Gb/s/pin Graphics DRAM Interface

9:45 AM

J. Song1, H-W. Lee2, S-B. Lim1, S. Hwang1, Y. Kim2, Y-J. Choi2, B-T. Chung2, C. Kim1
Korea University, Seoul, Korea
2
Hynix Semiconductor, Icheon, Korea

1

Break

36

10:00 AM

2013_Mini_AP_AP 11/8/12 9:57 AM Page 37

SESSION 18

Wednesday February 20th, 10:15 AM
Advanced Embedded SRAM

Session Chair: Michael Clinton, Texas Instruments, Dallas, TX
Associate Chair: Atsushi Kawasumi, Toshiba, Kawasaki, Japan

18.1 A 20nm 112Mb SRAM in High-κ Metal-Gate with Assist
Circuitry for Low-Leakage and Low-VMIN Applications

10:15 AM

J. Chang, Y-H. Chen, H. Cheng, W-M. Chan, H-J. Liao, Q. Li, S. Chang, S. Natarajan,
R. Lee, P-W. Wang, S-S. Lin, C-C. Wu, K-L. Cheng, M. Cao, G. Chang
TSMC, Hsinchu, Taiwan

18.2 An SRAM Using Output Prediction to Reduce
BL-Switching Activity and Statistically-Gated SA
for up to 1.9× Reduction in Energy/Access

10:45 AM

M. E. Sinangil1, A. P. Chandrakasan2
1
Nvidia, Bedford, MA
2
Massachusetts Institute of Technology, Cambridge, MA

18.3 A 27% Active and 85% Standby Power Reduction in
Dual-Power-Supply SRAM Using BL Power Calculator
and Digitally Controllable Retention Circuit

11:15 AM

F. Tachibana, O. Hirabayashi, Y. Takeyama, M. Shizuno, A. Kawasumi, K. Kushida,
A. Suzuki, Y. Niki, S. Sasaki, T. Yabe, Y. Unekawa
Toshiba, Kawasaki, Japan

18.4 A 64Mb SRAM in 22nm SOI Technology Featuring
Fine-Granularity Power Gating and Low-Energy
Power-Supply Partition Techniques for 37% Leakage
Reduction

11:45 AM

H. Pilo1, C. A. Adams2, R. M. Houle1, S. M. Lamphier1, M. M. Lee1, F. M. Pavlik1,
S. N. Sambatur3, A. Seferagic1, R. Wu1, M. I. Younus4
1
IBM, Essex Junction, VT
2
IBM, Rochester, MN
3
IBM, Bangalore, India
4
IBM, Hopewell Junction, NY

18.5 7GHz L1 Cache SRAMs for the 32nm
zEnterpriseTM EC12 Processor

12:00 PMJ. D. Davis1, P. A. Bunce1, D. M. Henderson1, Y. H. Chan1, U. Srinivasan1, D. Rodko1,
P. Patel1, T. J. Knips1, T. Werner2
1
IBM, Poughkeepsie, NY
2
IBM, Boeblingen, Germany

Conclusion37

12:15 PM2013_Mini_AP_AP 11/8/12 9:57 AM Page 38

SESSION 19

Wednesday February 20th, 8:30 AM

Wireless Transceivers for Smart Devices
Session Chair: Sven Mattisson, Ericsson, Lund, Sweden
Associate Chair: Koji Takinami, Panasonic, Yokohama, Japan19.1 A Fully Integrated 2×2 b/g and 1×2 a-Band MIMOWLAN SoC in 45nm CMOS for Multi-Radio IC

8:30 AM

R. Kumar1, T. Krishnaswamy1, G. Rajendran1, D. Sahu1, A. Sivadas1, M. Nandigam1,
S. Ganeshan1, S. Datla1, A. Kudari1, H. Bhasin1, M. Agrawal1, S. Narayan1, Y. Dharwekar1,
R. Garg1, V. Edayath1, T. Suseela1, V. Jayaram1, S. Ram1, V. Murugan1, A. Kumar1,
S. Mukherjee1, N. Dixit1, E. Nussbaum2, J. Dror2, N. Ginzburg2, A. EvenChen2, A. Maruani2,
S. Sankaran3
1
Texas Instruments, Bangalore, India; 2Texas Instruments, Ra’anana, Israel
3
Texas Instruments, Dallas, TX

19.2 A Digitally Modulated 2.4GHz WLAN Transmitter with
Integrated Phase Path and Dynamic Load Modulationin 65nm CMOS

9:00 AM

L. Ye1, J. Chen1, L. Kong1, P. Cathelin2, E. Alon1, A. Niknejad1
University of California, Berkeley, CA; 2ST-Ericsson, Grenoble, France

1

19.3 A 24.7dBm All-Digital RF Transmitter for Multimode
Broadband Applications in 40nm CMOS

9:30 AM

C. Lu1, H. Wang1, C. Peng2, A. Goel3, S. Son1, P. Liang2, A. Niknejad4, H. Hwang2, G. Chien1
MediaTek, San Jose, CA; 2MediaTek, Hsinchu, Taiwan
3
University of Southern California, Los Angeles, CA; 4University of California, Berkeley, CA

1

Break
19.4 A Universal GNSS (GPS/Galileo/Glonass/Beidou) SoC
with a 0.25mm2 Radio in 40nm CMOS

10:00 AM
10:15 AM

C. Tan1, F. Song1, T. Choke1, M. Kong1, D-C. Song1, C-H. Yong1, W. Shu1, Z. You2, Y-H. Lin2,
O. Shanaa1
1MediaTek, Singapore, Singapore; 2MediaTek, Hsinchu, Taiwan

19.5 A Receiver for LTE Rel-11 and Beyond Supporting
Non-Contiguous Carrier Aggregation

10:45 AM

L. Sundström, M. Anderson, R. Strandberg, S. Ek, J. Svensson, F. Mu, T. Olsson, I. ud Din,
L. Wilhelmsson, D. Eckerbert, S. Mattisson
Ericsson, Lund, Sweden

19.6 A Multiband 40nm CMOS LTE SAW-Less Modulator
with -60dBc C-IM3

11:15 AM

M. Ingels1, Y. Furuta2, X. Zhang1, S. Cha3, J. Craninckx1
1
imec, Leuven, Belgium; 2Renesas Electronics, Itami, Japan3
Renesas Electronics, Takasaki, Japan19.7 An LTE Transmitter Using a Class-A/B Power Mixer

11:30 AM
P. Rossi1, N. Codega2, D. Gerna1, A. Liscidini2,3, D. Ottini1, Y. He4, A. Pirola1, E. Sacchi1,
G. Uehara5, C. Yang5,6, R. Castello2
1
Marvell, Pavia, Italy; 2University of Pavia, Pavia, Italy
3*Now at the University of Toronto, Toronto, ON, Canada; 4Marvell, Aliso Viejo, CA
5Marvell, Austin, TX; 6*Now at Silicon Laboratories, Austin, TX

19.8 A 0.27mm2 13.5dBm 2.4GHz All-Digital Polar Transmitter
Using 34%-Efficiency Class-D DPA in 40nm CMOS

11:45 AM

J-W. Lai1, C-H. Wang1, K. Kao1, A. Lin1, Y-H. Cho1, L. Cho1, M-H. Hung1, X-Y. Shih1,
C-M. Lin1, S-H. Yan1, Y-H. Chung1, P. Liang1, G-K. Dehng1, H-S. Li1, G. Chien2,
R. B. Staszewski3
1
MediaTek, Hsinchu, Taiwan; 2MediaTek, San Jose, CA
3Delft University of Technology, Delft, The Netherlands

Conclusion
38

12:00 PM2013_Mini_AP_AP 11/8/12 9:57 AM Page 39

Wednesday February 20th, 8:30 AM

SESSION 20

Frequency Generation
Session Chair: Marc Tiebout, Infineon Technologies, Villach, Austria
Associate Chair: Jing-Hong Conan Zhan, MediaTek, HsinChu, Taiwan

20.1 A 2.5-to-3.3GHz CMOS Class-D VCO

8:30 AM

L. Fanori, P. Andreani
Lund University, Lund, Sweden

20.2 Third-Harmonic Injection Technique Applied to a
5.87-to-7.56GHz 65nm CMOS Class-F Oscillator
with 192dBc/Hz FOM

9:00 AM

M. Babaie1,2, R. B. Staszewski1
1
Delft University of Technology, Delft, The Netherlands
2
Aktieve Rangschikkings Monolitische Microgolf Onderdelen B.V., Delft, The Netherlands

20.3 A 33.6-to-46.2GHz 32nm CMOS VCO with 177.5dBc/Hz
Minimum Noise FOM Using Inductor Splitting for
Tuning Extension

9:30 AM

E. Mammei1, E. Monaco2, A. Mazzanti1, F. Svelto1
University of Pavia, Pavia, Italy
2
STMicroelectronics, Pavia, Italy

1

Break
20.4 A 56.4-to-63.4GHz Spurious-Free All-Digital
Fractional-N PLL in 65nm CMOS

10:00 AM
10:15 AM

W. Wu1, X. Bai1,2, R. B. Staszewski1, J. R. Long1
1
Delft University of Technology, Delft, The Netherlands
2
University of Science and Technology of China, Hefei, China

20.5 A 57.9-to-68.3GHz 24.6mW Frequency Synthesizer
with In-Phase Injection-Coupled QVCO in 65nm CMOS

10:45 AM

X. Yi, C. Boon, H. Liu, J. Lin, J. Ong, W. Lim
Nanyang Technological University, Singapore, Singapore

20.6 A 2.4psrms-jitter Digital PLL with Multi-Output
Bang-Bang Phase Detector andPhase-Interpolator-Based Fractional-N Divider

11:15 AM

R. Nonis, W. Grollitsch, T. Santa, D. Cherniak, N. Da Dalt
Infineon Technologies, Villach, Austria

20.7 A 50-to-930MHz Quadrature-Output Fractional-N
Frequency Synthesizer with 770-to-1860MHz
Single-Inductor LC-VCO and Without Noise Folding
Effect for Multistandard DTV Tuners

11:45 AM

Z. Tang1, X. Wan1,2, M. Wang1,2, J. Liu1
1
Fudan University, Shanghai, China
2
Ratio Microelectronics, Shanghai, China

Conclusion

39

12:15 PM2013_Mini_AP_AP 11/8/12 9:57 AM Page 40

SESSION 21

Wednesday February 20th, 8:30 AM
Power Converters

Session Chair: Wing-Hung Ki, HKUST, Hong Kong, Hong Kong
Associate Chair: Marco Berkhout, NXP Semiconductors, Nijmegen, The Netherlands

21.1 An 82.4% Efficiency Package-Bondwire-Based
Four-Phase Fully Integrated Buck Converter with
Flying Capacitor for Area Reduction

8:30 AM

C. Huang, P. K. T. Mok, HKUST, Hong Kong, China

21.2 An AC-Coupled Hybrid Envelope Modulator for
HSUPA Transmitters with 80% Modulator Efficiency

9:00 AM

P. Riehl1, P. Fowers2, H-P. Hong3, M. Ashburn1
MediaTek, Woburn, MA
2MediaTek, West Malling, United Kingdom
3MediaTek, Hsinchu, Taiwan

1

21.3 A CMOS Dual-Switching Power-Supply Modulator with
8% Efficiency Improvement for 20MHz LTE Envelope
Tracking RF Power Amplifiers

9:30 AM

M. Hassan1, P. M. Asbeck1, L. E. Larson2
University of California, San Diego, La Jolla, CA
2
Brown University, Providence, RI

1

Break

10:00 AM

21.4 90.6% Efficient 11MHz 22W LED Driver Using GaN
FETs and Burst-Mode Controller with 0.96 Power Factor

10:15 AM

S. Bandyopadhyay1, B. Neidorff2, D. Freeman3, A. P. Chandrakasan1
Massachusetts Institute of Technology, Cambridge, MA
2Texas Instruments, Manchester, NH
3
Texas Instruments, Dallas, TX

1

21.5 A Fully Integrated Successive-Approximation
Switched-Capacitor DC-DC Converter with 31mV
Output Voltage Resolution

10:45 AM

S. Bang, A. Wang, B. Giridhar, D. Blaauw, D. Sylvester
University of Michigan, Ann Arbor, MI

21.6 A Sub-ns Response Fully Integrated Battery-Connected
Switched-Capacitor Voltage Regulator Delivering
0.19W/mm2 at 73% Efficiency

11:15 AM

H-P. Le, J. Crossley, S. R. Sanders, E. Alon
University of California, Berkeley, CA

21.7 A 93% Efficiency Reconfigurable Switched-Capacitor
DC-DC Converter Using On-Chip Ferroelectric Capacitors

11:45 AM

D. El-Damak, S. Bandyopadhyay, A. Chandrakasan
Massachusetts Institute of Technology, Cambridge, MA

21.8 A Soft Self-Commutating Method Using MinimumControl Circuitry for Multiple-String LED Drivers

12:00 PMJ. Kim, J. Lee, S. Park
Dankook University, Yongin, Korea

Conclusion40

12:15 PM2013_Mini_AP_AP 11/8/12 9:57 AM Page 41

SESSION 22

Wednesday February 20th, 8:30 AM
Sensors & Displays

Session Chair: Aaron Partridge, SiTime, Sunnyvale, CA
Associate Chair: Young-Sun Na, LG Electronics, Seoul, Korea

22.1 A Fully Differential Charge-Balanced Accelerometer forElectronic Stability Control

8:30 AM

V. P. Petkov1, G. K. Balachandran1, J. Beintner2
Robert Bosch, Palo Alto, CA; 2Robert Bosch, Reutlingen, Germany

1

22.2 A 0.25mm2 AC-Biased MEMS Microphone Interface
with 58dBA SNR

9:00 AMS. Ersoy1, R. H. van Veldhoven1, F. Sebastiano1, K. Reimann1, K. A. A. Makinwa2
1
NXP Semiconductors, Eindhoven, The Netherlands
2
Delft University of Technology, Delft, The Netherlands

22.3 A 0.5V <4µW CMOS Photoplethysmographic
Heart-Rate Sensor IC Based on a Non-Uniform
Quantizer

9:15 AM

M. Alhawari1,2, N. Albelooshi1, M. H. Perrott1
1
Masdar Institute of Science and Technology, Abu Dhabi, United Arab Emirates
2*Now at Khalifa University, Abu Dhabi, United Arab Emirates

22.4 A Micropower Battery Current Sensor with ±0.03% (3σ)
Inaccuracy from -40 to +85°C

9:30 AMS. Heidary Shalmany1, D. Draxelmayr2, K. A. A. Makinwa1
1
Delft University of Technology, Delft, The Netherlands
2
Infineon Technologies, Villach, Austria

Break
22.5 A 55dB SNR with 240Hz Frame Scan Rate Mutual
Capacitor 30×24 Touch-Screen Panel Read-Out IC
Using Code-Division Multiple Sensing Technique

10:00 AM
10:15 AM

H. Shin1, S. Ko1, H. Jang1, I. Yun2, K. Lee1
1
KAIST, Daejeon, Korea; 2Zinitix, Daejeon, Korea

22.6 A Highly Noise-Immune Touch Controller Using
Filtered-Delta-Integration and a Charge-Interpolation
Technique for 10.1-inch Capacitive Touch-Screen Panels

10:45 AM

J-H. Yang1, S-H. Park1, J-M. Choi2, H-S. Kim1, C-B. Park1, S-T. Ryu1, G-H. Cho1
1
KAIST, Daejeon, Korea; 2Siliconworks, Daejeon, Korea

22.7 A 5.6mV Inter-Channel DVO 10b Column-Driver IC with
Mismatch-Free Switched-Capacitor Interpolation for
Mobile Active-Matrix LCDs

11:15 AM

H-S. Kim, J-H. Yang, S-H. Park, S-T. Ryu, G-H. Cho, KAIST, Daejeon, Korea

22.8 A [10°C ; 70°C] 640×480 17µm Pixel Pitch TEC-Less IR
Bolometer Imager with Below 50mK and Below 4V
Power Supply

11:30 AM

B. Dupont, A. Dupret, S. Becker, A. Hamelin, F. Guellec, P. Imperinetti, W. Rabaud
CEA-LETI-MINATEC, Grenoble, France

22.9 3D Volumetric Ultrasound Imaging with a 32×32 CMUT
Array Integrated with Front-End ICs Using Flip-Chip
Bonding Technology

11:45 AM

A. Bhuyan1, J. Choe1, B. Lee1, I. Wygant2, A. Nikoozadeh1, O. Oralkan3, B. T. Khuri-Yakub1
1
Stanford University, Stanford, CA; 2Texas Instruments, Santa Clara, CA
3
North Carolina State University, Raleigh, NC

Conclusion
41

12:15 PM2013_Mini_AP_AP 11/8/12 9:57 AM Page 42

SESSION 23

Wednesday February 20th, 1:30 PM

Short Reach Links, XCVR Techniques, & PLLs
Session Chair: Gerrit den Besten, NXP Semiconductors, Eindhoven, The Netherlands
Associate Chair: Koichi Yamaguchi, Renesas Electronics, Kawasaki, Japan

23.1 A 0.1pJ/b 5-to-10Gb/s Charge-Recycling Stacked
Low-Power I/O for On-Chip Signaling in 45nm CMOS SOI

1:30 PM

Y. Liu1, P-H. Hsieh2, S. Kim1, J-S. Seo1, R. Montoye1, L. Chang1, J. Tierno3, D. Friedman1
1
IBM T. J. Watson, Yorktown Heights, NY; 2National Tsing Hua University, Hsinchu, Taiwan
3Apple, Cupertino, CA

23.2 A Scalable 0.128-to-1Tb/s 0.8-to-2.6pJ/b 64-Lane Parallel
I/O in 32nm CMOS

2:00 PMM. Mansuri1, J. E. Jaussi1, J. T. Kennedy1, T-C. Hsueh1, S. Shekhar1, G. Balamurugan1,
F. O’Mahony1, C. Roberts1, R. Mooney2, B. Casper1
1Intel, Hillsboro, OR; 2Intel, Mapleton, UT

23.3 A 0.54pJ/b 20Gb/s Ground-Referenced Single-Ended
Short-Haul Serial Link in 28nm CMOS for Advanced
Packaging Applications

2:30 PMJ. W. Poulton1, W. J. Dally2, X. Chen2, J. G. Eyles1, T. H. Greer III1, S. G. Tell1, C. T. Gray1
Nvidia, Durham, NC; 2Nvidia, Santa Clara, CA

Break
23.4 A 5.5Gb/s 5mm Contactless Interface Containing
a 50Mb/s Bidirectional Sub-Channel Employing
Common-Mode OOK Signaling

3:00 PM
3:15 PMDS2

K. Hijioka, M. Matsudaira, K. Yamaguchi, M. Mizuno,
Renesas Electronics, Kawasaki, Japan

23.5 An 8Gb/s 1.5mW/Gb/s 8-Tap 6b NRZ/PAM-4
Tomlinson-Harashima Precoding Transmitter for
Future Memory-Link Applications in 22nm CMOS

3:45 PMM. A. Kossel, T. Toifl, P. A. Francese, M. Brändli, C. Menolfi, P. Buchmann, L. Kull,
T. Meyer Andersen, T. Morf
IBM, Rüschlikon, Switzerland

23.6 An 8Gb/s 0.65mW/Gb/s Forwarded-Clock ReceiverUsing an ILO with Dual Feedback Loop and Quadrature
Injection Scheme

4:15 PM

J-H. Seol1, Y-J. Kim1, S-H. Chung1, K-S. Ha2, S-J. Bae2, J-B. Lee2, J. Choi2, L-S. Kim1
1
KAIST, Daejeon, Korea; 2Samsung Electronics, Hwasung, Korea

23.7 A 3.1mW Phase-Tunable Quadrature-Generation
Method for CEI 28G Short-Reach CDR in 28nm CMOS

4:30 PMK. Bhardwaj1, S. Narayan2, S. Shumarayev3, T. Lee1
1
Stanford University, Stanford, CA; 2Inphi, Santa Clara, CA; 3Altera, San Jose, CA

23.8 A Divider-Less Sub-Harmonically Injection-Locked PLL
with Self-Adjusted Injection Timing

4:45 PM

I-T. Lee1, Y-J. Chen2, S-I. Liu1, C-P. Jou2, F-L. Hsueh2, H-H. Hsieh2
National Taiwan University, Taipei, Taiwan; 2TSMC, Hsinchu, Taiwan

1

23.9 A Wideband Fractional-N Ring PLL with Fractional-SpurSuppression Using Spectrally Shaped Segmentation

5:00 PM

T-K. Kao1, C-F. Liang1, H-H. Chiu1, M. Ashburn2
1
MediaTek, Hsinchu, Taiwan; 2MediaTek, Woburn, MA

Conclusion42

5:15 PM2013_Mini_AP_AP 11/8/12 9:57 AM Page 43

SESSION 24

Wednesday February 20th, 1:30 PM
Energy-Aware Digital Design

Session Chair: Wim Dehaene, KU Leuven, Leuven, Belgium
Associate Chair: Masaya Sumita, Panasonic, Nagaokakyo, Japan

24.1 A 10.4pJ/b (32, 8) LDPC Decoder with Time-Domain
Analog and Digital Mixed-Signal Processing

1:30 PMD. Miyashita1, R. Yamaki2, K. Hashiyoshi3, H. Kobayashi1, S. Kousai1, Y. Oowaki1,
Y. Unekawa1
1
Toshiba, Kawasaki, Japan,2Toshiba, Yokohama, Japan3
Toshiba Microelectoronics, Kawasaki, Japan

24.2 A 1.15Gb/s Fully Parallel Nonbinary LDPC Decoder with
Fine-Grained Dynamic Clock Gating

2:00 PMY. Park, Y. Tao, Z. Zhang, University of Michigan, Ann Arbor, MI

24.3 Ultra-Wide Body-Bias Range LDPC Decoder in 28nm
UTBB FDSOI Technology

2:30 PM

P. Flatresse1, B. Giraud2, J-P. Noel1, B. Pelloux-Prayer1, F. Giner1, D-K. Arora3, F. Arnaud1,
N. Planes1, J. Le Coz1, O. Thomas2, S. Engels1, G. Cesana1, R. Wilson1, P. Urard1
1
STMicroelectronics, Crolles, France, 2CEA-LETI-MINATEC, Grenoble, France
3
STMicroelectronics, Greater Noida, India

24.4 Self-Super-Cutoff Power Gating with State Retention on
a 0.3V 0.29fJ/Cycle/Gate 32b RISC Core in 0.13µm CMOS

2:45 PM

J-S. Chen, C. Yeh, J-S. Wang, National Chung Cheng University, Chaiyi, Taiwan

Break3:00 PM

24.5 A Low-Power 1GHz Razor FIR Accelerator with
Time-Borrow Tracking Pipeline and Approximate
Error Correction in 65nm CMOS

3:15 PMP. N. Whatmough, S. Das, D. M. Bull, ARM, Cambridge, United Kingdom

24.6 Reliable and Energy-Efficient 1MHz 0.4V Dynamically
Reconfigurable SoC for ExG Applications in 40nm LP CMOS

3:45 PM

M. Konijnenburg1, Y. Cho2, M. Ashouei1, T. Gemmeke1, C. Kim2, J. Hulzink1, J. Stuyt1,
M. Jung2, J. Huisken1, S. Ryu2, J. Kim2, H. de Groot1
1
imec - Holst Centre, Eindhoven, The Netherlands
DS2
2
Samsung Advanced Institute of Technology, Seoul, Korea

24.7 An 8MHz 75µA/MHz Zero-Leakage Non-Volatile
Logic-Based Cortex-M0 MCU SoC Exhibiting 100%
Digital State Retention at VDD=0V with <400ns Wakeup
and Sleep Transitions

4:15 PMDS2

S. C. Bartling, S. Khanna, M. P. Clinton, S. R. Summerfelt, J. A. Rodriguez, H. P. McAdams
Texas Instruments, Dallas, TX

24.8 A 100GB/s Wide I/O with 4096b TSVs Through an
Active Silicon Interposer with In-Place Waveform Capturing

4:45 PMS. Takaya1, M. Nagata1, A. Sakai2, T. Kariya2, S. Uchiyama2, H. Kobayashi2, H. Ikeda2
1
Kobe University, Kobe, Japan2
DS2
Association of Super-Advanced Electronics Technologies, Tokyo, Japan

24.9 Intermittent Resonant Clocking Enabling Power Reduction
at any Clock Frequency for 0.37V 980kHz Near-Threshold
Logic Circuits

5:00 PM

H. Fuketa1, M. Nomura2, M. Takamiya1, T. Sakurai1
1
University of Tokyo, Tokyo, Japan
2
Semiconductor Technology Academic Research Center, Yokohama, Japan

Conclusion
43

5:15 PM2013_Mini_AP_AP 11/8/12 9:57 AM Page 44

Wednesday February 20th, 1:30 PM

SESSION 25

Energy-Efficient WirelessSession Chair: Shouhei Kousai, Toshiba, Kawasaki, Japan
Associate Chair: Gangadhar Burra, Texas Instruments, Plano, TX

25.1 A 45nm CMOS Near-Field Communication Radio with

1:30 PM

0.15A/m RX Sensitivity and 4mA Current Consumption
in Card Emulation Mode
Y. Darwhekar1, E. Braginskiy2, K. Levy2, A. Agrawal1, V. Singh1, R. Issac2, O. Blonskey2, O. Adler2,
Y. Benkuzari2, M. Ben-Shachar2, S. Manian1, A. Sivadas1, S. Mukherjee1, G. Burra3, N. Tal2,
Y. Shlivinski2, G. Bitton2
1
Texas Instruments, Bangalore, India; 2Texas Instruments, Ra’anana, Israel
3
Texas Instruments, Dallas, TX

25.2 An Ultra-Low-Power 9.8GHz Crystal-Less UWB Transceiver

2:00 PMwith Digital Baseband Integrated in 0.18µm BiCMOS
1

2

2

2

2

J. K. Brown , K-K. Huang , E. Ansari , R. R. Rogel , Y. Lee , D. D. Wentzloff
Cavium, Marlborough, MA; 2University of Michigan, Ann Arbor, MI2

1

25.3 A Self-Duty-Cycled and Synchronized UWB Receiver SoC

2:30 PM

Consuming 375pJ/b for -76.5dBm Sensitivity at 2Mb/s
B. Vigraham, P. Kinget, Columbia University, New York, NY

25.4 A 1.9nJ/b 2.4GHz Multistandard

2:45 PM(Bluetooth Low Energy/Zigbee/IEEE802.15.6)
Transceiver for Personal/Body-Area Networks
Y-H. Liu1, X. Huang1, M. Vidojkovic1, A. Ba1, P. Harpe2, G. Dolmans1, H. de Groot1
imec - Holst Centre, Eindhoven, The Netherlands
2
Eindhoven University of Technology, Eindhoven, The Netherlands

DS2

1

Break
25.5 A 1.7mW 0.22mm 2.4GHz ZigBee RX Exploiting a Current2

3:00 PM
3:15 PM

Reuse Blixer + Hybrid Filter Topology in 65nm CMOS
Z. Lin1, P-I. Mak1, R. Martins1,2
1
University of Macau, Macao, China; 2Instituto Superior Tecnico, Lisbon, Portugal

25.6 A 110pJ/b Multichannel FSK/GMSK/QPSK/π/4-DQPSK

3:30 PM

Transmitter with Phase-Interpolated Dual-Injection
DLL-Based Synthesizer Employing Hybrid FIR
S-J. Cheng1, Y. Gao1, W-D. Toh1, Y. Zheng2, M. Je1,3, C-H. Heng3
Institute of Microelectronics, Singapore, Singapore
2
Nanyang Technological University, Singapore, Singapore
3
National University of Singapore, Singapore, Singapore

125.7 A 5.5mW IEEE-802.15.6 Wireless Body-Area-Network
Standard Transceiver for Multichannel
Electro-Acupuncture Application
H. Lee, K. Lee, S. Hong, K. Song, T. Roh, J. Bae, H-J. Yoo, KAIST, Daejeon, Korea

25.8 Wideband UHF ISM-Band Transceiver Supporting

3:45 PMDS2
4:15 PM

Multichannel Reception and DSSS Modulation
J. van Sinderen1, G. W. de Jong1, F. Leong1, X. He1, M. Apostolidou1, H. Kundur Subramaniyan1,
R. Rutten1, J. Niehof1, J. Verlinden1, H. Wang1, A. Hoogstraate1, K. Kwok1, R. Verlinden1,
R. Hoogendoorn1, D. Jeurissen2, A. Salfelner2, E. Bergler2, J. M. Velandia Torres2, C. J. Haji-Michael2,
T. Unterweger2, E. Tarvainen2, M. Posch2, R. Schmidt2, M. Stattmann2, J. Tyminski2, P. Jean3,
S. Darfeuille3, O. Aymard3, A. le Grontec3, C. Boucey3, C. Kelma3, G. Monnerie3
1
NXP Semiconductors, Eindhoven, The Netherlands; 2NXP Semiconductors, Gratkorn, Austria
3
NXP Semiconductors, Caen, France

25.9 A 1.6mW 300mV-Supply 2.4GHz Receiver with -94dBm

4:45 PM

Sensitivity for Energy-Harvesting Applications
F. Zhang1, K. Wang1, J. Koo1, Y. Miyahara2, B. Otis1
1
University of Washington, Seattle, WA; 2Panasonic, Yokohama, Japan

25.10 A Super-Regenerative Radio on Plastic Based on

5:15 PMThin-Film Transistors and Antennas on Large Flexible
Sheets for Distributed Communication Links
L. Huang, W. Rieutort-Louis, Y. Hu, J. Sanz-Robinson, S. Wagner, J. C. Sturm, N. Verma
Princeton University, Princeton, NJ

Conclusion44

5:30 PM2013_Mini_AP_AP 11/8/12 9:57 AM Page 45

SESSION 26

Wednesday February 20th, 1:30 PM
High-Speed Data Converters

Session Chair: Boris Murmann, Stanford University, Stanford, CA
Associate Chair: Tetsuya Iizuka, University of Tokyo, Tokyo, Japan

26.1 A 10.3GS/s 6b Flash ADC for 10G Ethernet Applications
S. Verma, A. Kasapi, L-M. Lee, D. Liu, D. Loizos, S-H. Paik, A. Varzaghani,
S. Zogopoulos, S. Sidiropoulos
Broadcom, Santa Clara, CA

1:30 PM

DS2

26.2 An 11b 3.6GS/s Time-Interleaved SAR ADC in 65nm CMOS

2:00 PME. Janssen1, K. Doris1, A. Zanikopoulos1, A. Murroni1, G. van der Weide1, Y. Lin1,
L. Alvado2, F. Darthenay2, Y. Fregeais2
1
NXP Semiconductors, Eindhoven, The Netherlands
2
NXP Semiconductors, Caen, France

26.3 A 14b 2.5GS/s 8-Way-Interleaved Pipelined ADC with
Background Calibration and Digital Dynamic Linearity
Correction

2:30 PMB. Setterberg1, K. Poulton1, S. Ray1, D. J. Huber1, V. Abramzon1, G. Steinbach1,
J. P. Keane1, B. Wuppermann1, M. Clayson1, M. Martin2, R. Pasha2, E. Peeters3,
A. Jacobs3, F. Demarsin3, A. Al-Adnani3, P. Brandt3
1
Agilent Technologies, Santa Clara, CA
2Agilent Technologies, Colorado Springs, CO
3
Agilent Technologies, Rotselaar, Belgium

Break26.4 A 3.1mW 8b 1.2GS/s Single-Channel Asynchronous
SAR ADC with Alternate Comparators for Enhanced
Speed in 32nm Digital SOI CMOS

3:00 PM
3:15 PML. Kull1,2, T. Toifl1, M. Schmatz1, P. A. Francese1, C. Menolfi1, M. Braendli1,
M. Kossel1, T. Morf1, T. Meyer Andersen1, Y. Leblebici2
1
IBM Research, Rüschlikon, Switzerland
2
EPFL, Lausanne, Switzerland

26.5 An 8.6 ENOB 900MS/s Time-Interleaved 2b/cycle
SAR ADC with a 1b/cycle Reconfiguration for
Resolution Enhancement

3:45 PM

H-K. Hong1, H-W. Kang1, B. Sung1, C-H. Lee2, M. Choi2, H-J. Park2, S-T. Ryu1
1
KAIST, Daejeon, Korea
2
Samsung Electronics, Yongin, Korea

26.6 A 14b 80MS/s SAR ADC with 73.6dB SNDR in 65nm CMOS

4:15 PMR. Kapusta1, J. Shen1, S. Decker1, H. Li2, E. Ibaragi2
1
Analog Devices, Wilmington, MA
2Analog Devices, Tokyo, Japan

26.7 A 12b 1.6GS/s 40mW DAC in 40nm CMOS with >70dB
SFDR over Entire Nyquist Bandwidth

4:45 PM

W-T. Lin, T-H. Kuo
National Cheng Kung University, Tainan, Taiwan

Conclusion45

5:15 PM2013_Mini_AP_AP 11/8/12 9:57 AM Page 46

SESSION 27

Wednesday February 20th, 1:30 PM
Image Sensors

Session Chair: Robert Johansson, OmniVision Technologies, Oslo, Norway
Associate Chair: Shoji Kawahito, Shizuoka University, Hamamatsu, Japan

27.1 A 3.4µW CMOS Image Sensor with Embedded
Feature-Extraction Algorithm for Motion-Triggered
Object-of-Interest Imaging

1:30 PMJ. Choi, S. Park, J. Cho, E. Yoon, University of Michigan, Ann Arbor, MI

27.2 A 467nW CMOS Visual Motion Sensor with Temporal
Averaging and Pixel Aggregation

2:00 PM

G. Kim, M. Barangi, Z. Foo, N. Pinckney, S. Bang, D. Blaauw, D. Sylvester
University of Michigan, Ann Arbor, MI

27.3 A Rolling-Shutter Distortion-Free 3D Stacked Image
Sensor with -160dB Parasitic Light Sensitivity
In-Pixel Storage Node2:30 PMJ. Aoki, Y. Takemoto, K. Kobayashi, N. Sakaguchi, M. Tsukimura, N. Takazawa,H. Kato, T. Kondo, H. Saito, Y. Gomi, Y. Tadaki
Olympus, Hachioji, Japan

27.4 A 1/4-inch 8Mpixel Back-Illuminated Stacked CMOS
Image Sensor

2:45 PMS. Sukegawa1, T. Umebayashi1, T. Nakajima1, H. Kawanobe1, K. Koseki2, I. Hirota1,
T. Haruta1, M. Kasai1, K. Fukumoto1, T. Wakano1, K. Inoue3, H. Takahashi1,
T. Nagano1, Y. Nitta1, T. Hirayama1, N. Fukushima1
1Sony, Atsugi, Japan; 2Sony LSI Design, Atsugi, Japan
3
Sony Semiconductor, Kumamoto, JapanBreak
27.5 An 8×16-pixel 92kSPAD Time-Resolved Sensor with
On-Pixel 64ps 12b TDC and 100MS/s Real-Time
Energy Histogramming in 0.13µm CIS Technology
for PET/MRI Applications

3:00 PM
3:15 PML. H. Braga1, L. Gasparini1, L. Grant2, R. K. Henderson3, N. Massari1, M. Perenzoni1,
D. Stoppa1, R. Walker3
1
Fondazione Bruno Kessler, Trento, Italy
2
STMicroelectronics, Edinburgh, United Kingdom
3
University of Edinburgh, Edinburgh, United Kingdom

27.6 A 0.18µm CMOS SoC for a 100m-Range 10fps
200×96-Pixel Time-of-Flight Depth Sensor

3:45 PMC. Niclass, M. Soga, H. Matsubara, M. Ogawa, M. Kagami
Toyota Central R&D Labs, Nagakute, Japan

27.7 3D Camera Based on Linear-Mode Gain-Modulated
Avalanche Photodiodes

DS2

4:15 PMO. Shcherbakova1,2, L. Pancheri1, G-F. Dalla Betta1, N. Massari2, D. Stoppa2
1
University of Trento, Trento, Italy. 2Fondazione Bruno Kessler, Trento, Italy

27.8 A 3D Vision 2.1Mpixel Image Sensor for Single-Lens
Camera Systems

4:45 PM

S. Koyama, K. Onozawa, K. Tanaka, Y. Kato, Panasonic, Nagaokakyo, Japan

27.9 A 187.5µVrms-Read-Noise 51mW 1.4Mpixel CMOS Image
Sensor with PMOSCAP Column CDS and 10b
Self-Differential Offset-Cancelled Pipeline SAR-ADC

5:00 PM

J. Deguchi1, F. Tachibana1, M. Morimoto1, M. Chiba1, T. Miyaba2, H. Tanaka1,
K. Takenaka2, S. Funayama1, K. Amano1, K. Sugiura1, R. Okamoto1, S. Kousai1
1
Toshiba, Kawasaki, Japan; 2Toshiba Microelectronics, Kawasaki, Japan

Conclusion
46

5:15 PM2013_Mini_AP_AP 11/8/12 9:57 AM Page 47

SHORT COURSE

Thursday February 21st, 8:00 AM

RF Blocks for Wireless Transceivers
Organizer:

Willy Sansen, K.U. Leuven, Leuven, Belgium

Instructors:

Hooman Darabi, Broadcom, Irvine, CAJohn Long, Delft University of Technbologies, The Netherlands
Ali Hajimiri, Caltech, CA
Ali Niknejad, UC Berkeley, CA

IC’s for Communications
Hooman Darabi, Broadcom, Irvine, CA
In this presentation we offer architectural considerations of both receivers and transmittersfor advanced mobile and wireless applications. An overview of RF standards, along with system level analysis of various architectures, is presented. The key radio requirements are derived and translated to circuit specifications, followed by a detailed discussion of different
schemes and their pros and cons. General system level concerns for integrated transceivers,
particularly in CMOS, such as linearity, frequency planning, blockers and spurious mixing are
introduced and appropriate architecture level solutions are presented and discussed in detail.
Speaker Biography: Hooman Darabi received the BS and MS degrees both in Electrical Engineering from Sharif University of Technology, Tehran in 1994, and 1996 respectively. He
received the Ph.D. degree in electrical engineering from the University of California, Los Angeles, in 1999. He is currently a Senior Technical Director , and a Fellow, with Broadcom Corporation, Irvine, CA, within the RF group in the Mobile and Wireless Business Unit. He is also
an adjunct professor with the UCI EECS department. His interests include analog and RF IC
design for wireless communications. Hooman holds over 200 issued or pending patents with
Broadcom, and has published over 50 peer reviewed or conference papers. He is an IEEE distinguished lecturer.

Design of Building Blocks for the RF Transceiver Front-End
John Long, Delft University of Technologies, Delft, The Netherlands
The design of an RF front-end from specification to transistor-level circuit is outlined in thislecture. Circuits include: low-noise amplifiers (LNAs), up- and down-conversion mixers, voltage-controlled and digitally controlled oscillators (VCOs and DCOs), LO and power amplifierbuffers. Integration of these sub-blocks into I/Q up- and down-converters using submicron
CMOS technology (e.g., 65nm) is assumed. Packaging effects, supply isolation, and circuit
layout for optimum RF performance and reliability are also considered.
Speaker Biography: John R. Long received the B.Sc.-E.E. from the University of Calgary in
1984, and the M. Eng. and Ph.D. degrees in Electronics Engineering from Carleton University
in 1992 and 1996, respectively, all with distinction. He was employed for 10 years by BellNorthern Research Ltd., Ottawa, Canada designing GaAs ASICs for Gb/s fibre-optic transmission systems. Professor Long is currently chair of the Electronics Research Laboratory at theDelft University of Technology in the Netherlands. His current research interests include: lowpower transceiver circuitry for highly-integrated radio applications, and electronics designfor high-speed data communications systems

47

2013_Mini_AP_AP 11/8/12 9:57 AM Page 48

SHORT COURSE

Thursday February 21st, 8:00 AM

High-Frequency CMOS Power Generation andPhased-Array Transmitters
Ali Hajimiri, Caltech, CA
Over the last decade, silicon integrated circuits have come a long way in power generation
despite their diminishing voltage-handling capability. This is primarily due to innovations incircuit topologies and architectures. In this lecture, we will discuss some of the underlying
principles enabling power generation at high frequencies in silicon, such as parallelism, stacking, active -EM integration, periodic structures, and self healing. These concepts will bedemonstrated and explored in phased-array transmitters and high-frequency power amplifierswith an emphasis on innovative architectures for beam control, signal generation, and efficientradiation through several practical and illustrative examples.
Speaker Biography: Ali Hajimiri received his Ph.D. degrees in Electrical Engineering from
Stanford University. He is Thomas G. Myers Professor of Electrical Engineering and directorof the Microelectronics Laboratory at the California Institute of Technology. Prior to joining
Caltech he worked for Philips Semiconductors, Sun Microsystems, and Lucent Technologies(Bell Labs). He holds more than 50 patents and was selected to the TR35 top innovator’s list.
He has graduated more than twenty Ph.D. students, many of whom hold top leadership positions in academia and industry. He and his students have won several best paper and otherawards. He co-founded Axiom Microdevices Inc. that produced and shipped the first commercially viable fully-integrated CMOS PA for cellular handsets.

mm-Wave Phased-Array Receivers
Ali Niknejad, UC Berkeley, Berkeley, CA
Abstract: A phased-array receiver offers many advantages, such as a lower effective noise
factor, beam steering, beam nulling, and better immunity to interference and multi-path due
to spatial gain. However, the design of a phased-array at mm-wave frequencies presents a
unique set of challenges related to the phase shifters. Basic architectures for the phasedarray will be compared (RF, LO, IF) in terms of noise, linearity and power consumption. Circuit
realizations of active and passive phase shifters will be presented, followed by some design
examples from CMOS and SiGe prototypes.
Speaker Biography: Ali M. Niknejad is a professor in the EECS department at UC Berkeley
and co-director of the Berkeley Wireless Research Center and the BSIM Research Group. His
research interests lie within the area of wireless and broadband communications and biomedical imaging (RF, mm-wave, and sub-THz), including the implementation of integrated
communication systems in silicon using CMOS, SiGe, and BiCMOS processes. The focus
areas of his research include analog, RF, mixed-signal, mm-wave circuits, device physics andcompact modeling, and numerical techniques in electromagnetics.

48

2013_Mini_AP_AP 11/8/12 9:57 AM Page 49

FORUM
F3: Emerging Technologies for Wireline Communication
Organizer:
Chair:

Elad Alon, Unversity of California, Berkeley, Berkeley, CA
Azita Emami, California Institute of Technology, Pasadena, CA

Committee:

Gerritt den Besten, NXP Semiconductors, City, The Netherlands
Ichiro Fujimori, Broadcom, Irvine, CA
Tadahiro Kuroda, Keio University, Yokohama, Japan
Masafumi Nogawa, NTT, Atsugi, Japan
Hisakatsu Yamaguchi, Fujitsu, Kawasaki, Japan

Future systems will be shaped by advanced interconnects enabled by emerging wireline communications technologies. Thus, the objective of this Forum is to present an overview of theopportunities, challenges, and solutions associated with emerging optical as well as electricalcommunication technologies. The Forum begins with a talk describing design considerations
for integrated Power Over Ethernet. The next three presentations focus on emerging opticallink technologies, beginning with a talk describing the key enablers for next-generation opticalaccess systems. The next talk highlights the design and impact on future networks of coherent-optical transceivers, followed by a presentation describing the integration of silicon-photonic devices into state-of-the-art CMOS technologies with minimal process changes. The
next two talks focus on advanced electrical links, including an exploration of power-efficient
equalization, as well as examination of multiple modulation formats (NRZ and PAM4) for new
100Gb/s backplane standards. The final two talks of the Forum highlight the bandwidth-density opportunities offered by 2.5/3D integration technologies, describing how wireline circuit
techniques enable substantial performance improvements in both inductivecoupling, as well
as TSV-based through- and across-chip interfaces.

Agenda
Time
08:00

Topic
Breakfast

08:20

Introduction
Azita Emami, California Institute of Technology, Pasadena, CA

08:30

Integrated Power Over Ethernet ICs – Challenges and Solutions
Stefan Van Roeyen, Broadcom, Eke, Belgium

09:20

Recent Progress in Next-Generation Optical-Access Systems andOptical-Transceiver Technologies
Junichi Nakagawa, Mitsubishi Electric, Amagasaki, Japan

10:10

Break

10:35

Coherent Optical Transceivers: Design and Impact on Future Optical
Networks
Oscar Agazzi, ClariPhy Communications, Irvine, CA

11:25

Monolithic Electronic-Photonic Integration for Chip-to-Chip Interconnect
Jason Orcutt, Massachusetts Institute of Technology,
Cambridge, MA
Lunch

12:15
13:20

Power-Reduction Techniques and Tradeoffs for Advanced Equalization
Chih-Kong Ken Yang, University of California, Los Angeles, CA

14:10

Signaling at 100Gb/s: Evolution of the 100Gb Backplane Standard
Vasudevan Parthasarathy, Broadcom, Irvine, CA

15:00

Break

15:20

ThruChip Interface for 3D ICs
Noriyuki Miura, Keio University, Yokohama, Japan

16:10

Compact Low-Power 2.5D and 3D I/O Technologies
Yong Liu, IBM, Yorktown Heights, NY

17:00

Closing Remarks (Chair)49

2013_Mini_AP_AP 11/8/12 9:57 AM Page 50

Thursday February 21st, 8:00 AM
F4: Scientific Imaging
Organizer/Chair:

Makoto Ikeda, University of Tokyo, Tokyo, Japan

Committee:

Ehsan Afshari, Cornell University, Ithaca, NY
Yusuke Oike, Sony, Atsugi, JapanDavid Ruffieux, CSEM, Neuchatel, Switzerland
Johannes Solhusvik, Omnivision, Oslo, Norway
Albert Theuwissen, Harvest Imaging, Bree, Belgium,
Delft University of Technology, Delft, The Netherlands

Imaging techniques open new vistas for various scientific fields: These include observationof: ultra-high-speed events, very dark signals under a couple of photons, signals with afrequency range outside that of visible light (such as X-ray, Infrared, and THz). The objectiveof this Forum is to present applications and circuit details of system and sensor device
techniques which underpin or realize these scientific imaging techniques. This will start withan overview of scientific imaging over a broad wavelength range, followed by a discussionof associated CMOS-based sensor devices and circuits for multi-spectral imaging. The next
two talks will cover ultra-high-speed imaging up to 20Mfps, and ultra-high-sensitivity imaging
by SPAD. There follow two talks covering IR-imaging and readout circuittry, one uncooled ,and the other under ultra-low temperature conditions for astronomy. The final three talks will
highlight THz imaging, including an overview, system aspects, and CMOS realization.

Agenda
Time
08:00

Topic
Breakfast

08:30

Introduction
Makoto Ikeda, University of Tokyo, Tokyo, Japan

08:35

Overview of Scientific Imaging in the Frequency Range from X-Rays
to Terahertz
Valérie Nguyen, CEA Leti MINATEC, Grenoble, France

09:20

Multispectral Imaging: When CMOS Does the Trick!
Matteo Perenzoni, Fondazione Bruno Kessler, Torento, Italy

10:05

Break

10:30

Ultra-High-Speed Imaging
Shigetoshi Sugawa, Tohoku University, Sendai, Japan

11:15

Single-Photon Imaging with SPADs
Robert Henderson, University of Edinburgh, Edinburgh,
United Kingdom

12:00

Lunch

13:00

State-of-the-Art in Uncooled IR Sensors and Readout Circuitry
Patrick Robert, ULIS, Veurey-Voroize, France

13:45

High-Sensitivity Astronomical-Imaging Arrays with Cryogenic Electronics
for Terahertz Waves
Hiroshi Matsuo, National Observatory of Japan, Tokyo, Japan

14:30

Break

14:50

THz Imaging: What You See and What You Don’t!
Peter H. Siegel, Caltech/JPL, Pasedena, CA

15:35

Advanced Microwave Imaging Based on Modern Semiconductor
Technologies
Sherif-Sayed Ahmed, Rohde & Schwarz, Munich, Germany

16:20

THz CMOS Image Sensors Using Schottky Barrier Diodes for Lensless
Portable Applications
Kenneth O, University of Texas at Dallas, Dallas, TX

17:05

Closing Remarks (Chair)50

2013_Mini_AP_AP 11/8/12 9:57 AM Page 51

FORUM
F5: Frequency Generation and Clock Distribution
Organizer:

Antonio Liscidini, University of Toronto, Toronto, Canada

Committee:

SeongHwan Cho, KAIST, Daejeon, Korea
Tony Chan Carusone, University of Toronto, Toronto, Canada
Tanay Karnik, Intel, Hillsboro, OR
Mike Keaveney, Analog Devices, Limerick, Ireland
Brian Otis, University of Washington, Seattle, WA
Aaron Partridge, SiTime, Sunnyvale, CA
Christoph Sandner, Infineon Technologies, Villach, Austria

This Forum explores the primary challenges in the generation and distribution of frequencyreference signals in modern integrated circuits (analog and digital). Based on a bottom-up
approach, the Forum begins with an overview of the building blocks used for frequency generation and distribution. It continues by discussing particular challenges presented by thedesign of frequency synthesizers and their interaction with the rest of the system. The first
three talks provide insights into the design of frequency generators: harmonic oscillators,
ring oscillators, and MEMS topologies. The fourth presentation deals with various single- anddual-modulus divider topologies necessary for wireless or wireline applications. Then, frequency synthesizers for millimeter-wave wireless communications and PLLs for wireline applications are presented. The last two talks give an overview of the main challenges in clock
distribution for both microprocessors and RF analog transceivers. The Forum concludes witha brief panel discussion, providing an opportunity for participants to give feedback and ask
questions.
Agenda
Topic
Time
08:00
Breakfast
08:20

Introduction
Antonio Liscidini, University of Toronto, Toronto, Canada

08:30

Integrated Harmonic Voltage-Controlled Oscillators
Pietro Andreani, University of Lund, Lund, Sweden

09:20

Fully-Integrated Frequency References in CMOS
Fabio Sebastiano, NXP, Eindhoven, The Netherlands

10:10

Break

10:35

High-Frequency Piezoelectric MEMS Oscillators
Gianluca Piazza, Carnegie Mellon University, Pittsburgh, PA

11:25

High-Performance Frequency Dividers
Behzad Razavi, University of California, Los Angeles, CA

12:15

Lunch

13:20

Insights into Frequency Synthesizers for millimeter-Wave WirelessCommunications
Enrico Temporiti, ST Microelectronics, Pavia, Italy

14:10

Design and Implementation of Low-Power and Small-Size PLLs for SoC
Applications including Wirelines
Jaejin Park, Samsung, Giheung, South Korea

15:00

Break

15:20

Microprocessor Clocking Architectures
Kurd Nasser, Intel, Hillsboro, OR

16:10

LO Distribution Techniques to Prevent LO Pulling and RX Sensitivity
Degradation in Highly-Integrated Wireless Transceivers
Jinho Park, Marvell Semiconductors, Santa Clara, CA

17:00

Panel Discussion

17:20

Closing Remarks (Chair)51

2013_Mini_AP_AP 11/8/12 9:57 AM Page 52

Thursday February 21st, 8:00 AM
F6: Mixed-Signal/RF Design and Modeling in Next-Generation CMOS
Organizer/Chair:

Boris Murmann, Stanford University, Stanford, CA

Committee:

Jafar Savoj, Xilinx, San Jose, CA
Piet Wambacq, imec, Heverlee, Belgium
Jieh-Tsorng Wu, National Chiao-Tung University, Hsinchu, Taiwan

Technology awareness and modeling is important in all areas of mixed-signal and RF design.
This Forum intends to provide, for next-generation CMOS, a holistic overview and discussion
spanning a variety of important aspects of device modeling, reliability, and simulation. It begins with an analog/RF-centric comparison between FinFET and ultra-thin-body SOI technology. The next two talks then venture into bias stress and Electrostatic Discharge Protection(ESD), which are two issues of ever-increasing importance for future scaling. The fourth presentation discusses the latest developments surrounding the popular BSIM transistor model,
and explains how this new model can be efficiently coupled to the analog/RF design process.
Motivated by their increasing significance in integrated RF transceivers, the next talk outlines
a future roadmap for passive components in scaled technologies. Then, we expand upon modeling challenges that arise when components are stacked in three dimensions. Finally, thisseries of modeling talks is rounded up by two comprehensive presentations that summarize
key challenges from the foundry and EDA-tool-vendor perspectives.

Agenda
Time
08:00

Topic
Breakfast

08:20

Introduction
Boris Murmann, Stanford University, Stanford, CA

08:30

FinFET versus UTBB SOI for RF/Analog Applications
Tsu-Jae King Liu, University of California, Berkeley, CA

09:20

Reliability Modeling for nm-Scale Components
Praveen Raghavan, imec, Heverlee, Belgium

10:10

Break

10:35

ESD-Protection Design in Nanometer CMOS
Ming-Dou Ker, National Chiao-Tung University, Hsinchu, Taiwan

11:25

The BSIM6 MOSFET Compact Model and Its Use for Analog and RF Design
Christian Enz, CSEM, Neuchâtel, Switzerland

12:15

Lunch

13:20

Development of Passives in Advanced CMOS: A Key Enabler for RF
Applications up to mm-Wave
Frédéric Gianesello, STMicroelectronics, Crolles, France

14:10

3D Stacking, the Best of Both Worlds: Modeling Issues in an Optimized
Heterogeneous (Analog/Digital) Stacked Design
Liam Madden, Xilinx, San Jose, CA

15:00

Break

15:20

Foundry Perspectives on Analog/RF Challenges in Next-Generation CMOS
Sally Liu, TSMC, Hsinchu, Taiwan

16:10

Next-Generation Analog/RF EDA Tools
Li-Da Huang, Synopsys, Austin, TX

17:00

Closing Remarks (Chair)52

2013_Mini_AP_AP 11/8/12 9:57 AM Page 53

COMMITTEESEXECUTIVE COMMITTEECONFERENCE CHAIR
Anantha Chandrakasan, Massachusetts Institute of Technology, Cambridge, MA
SECRETARY, FORUMS AND DATA TEAM
Siva Narendra, Tyfone, Portland, OR
DIRECTOR OF FINANCE AND BOOK DISPLAY COORDINATOR
Bryant Griffin, Penfield, NY
PROGRAM CHAIR
Bram Nauta, University of Twente, Enschede, The Netherlands
PROGRAM VICE CHAIR
Trudy Stetzler, Texas Instruments, Stafford, TX
STUDENT RESEARCH CHAIR AND UNIVERSITY RECEPTIONS
Jan van der Spiegel, University of Pennsylvania, Philadelphia, PA
DEMONSTRATION SESSION CHAIR
Bill Bowhill, Intel, Hudson, MA
DEMONSTRATION SESSION CO-CHAIR
Chris van Hoof, imec, Leuven, Belgium
ITPC FAR EAST REGIONAL CHAIR
Makoto Ikeda, University of Tokyo, Tokyo, JapanITPC FAR EAST REGIONAL VICE CHAIR
Kazutami Arimoto, Renesas Electronics, Itami, JapanITPC FAR EAST REGIONAL SECRETARY
Jae-Youl Lee, Samsung, Yongin, Korea
ITPC EUROPEAN REGIONAL CHAIR
Aarno Pärssinen, Renesas Mobile, Helsinki, Finland
ITPC EUROPEAN REGIONAL VICE CHAIR
Eugenio Cantatore, Eindhoven University of Technology,
Eindhoven, The Netherlands
ITPC EUROPEAN REGIONAL SECRETARY
Alison Burdett, Toumaz Technology, Abingdon, United Kingdom
TUTORIALS CHAIR
Ali Sheikholeslami, University of Toronto, Toronto, Canada
ADCOM REPRESENTATIVE
Bryan Ackland, Stevens Institute of Technology, Old Bridge, NJ
DIRECTOR OF PUBLICATIONS AND PRESENTATIONS
Laura Fujino, University of Toronto, Toronto, Canada
DIRECTOR OF AUDIOVISUAL SERVICES
John Trnka, Rochester, MN
PRESS LIAISON AND AWARDS & RECOGNITION COMMITTEE (ARC) CHAIR
Kenneth C. Smith, University of Toronto, Toronto, Canada
PRESS COORDINATOR
Alice Wang, MediaTek USA, Austin, TX
DIRECTOR OF OPERATIONSMelissa Widerkehr, Widerkehr and Associates, Montgomery Village, MD
TECHNICAL EDITORS
Jason H. Anderson, University of Toronto, Toronto, Canada
Vincent Gaudet, University of Waterloo, Waterloo, Canada
Glenn Gulak (Editor-at-Large), University of Toronto, Toronto, Canada
James W. Haslett, University of Calgary, Calgary, Canada
Shahriar Mirabbasi, (Editor-at-Large) University of British Columbia, Vancouver, Canada
Kostas Pagiamtzis, Semtech, Gennum Products Group, Burlington, Canada
Kenneth C. Smith (Editor-at-Large), University of Toronto, Toronto, Canada
MULTI-MEDIA COORDINATORS
Dave Halupka, Kapik Integration, Toronto, Canada
Aleksey Tyshchenko, Intel, Toronto, Canada

53

2013_Mini_AP_AP 11/8/12 9:57 AM Page 54

COMMITTEESINTERNATIONAL TECHNICAL PROGRAM COMMITTEEPROGRAM CHAIR:
Bram Nauta, University of Twente, Enschede, The Netherlands
PROGRAM VICE CHAIR:
Trudy Stetzler, Texas Instruments, Stafford, TX

ANALOG SUBCOMMITTEE
Chair: Bill Redman-White, Southampton University, Southampton, United Kingdom
Marco Berkhout, NXP Semiconductors, Nijmegen, The Netherlands
Tony Chan Carusone, University of Toronto, Toronto, Canada
Baher Haroun, Texas Instruments, Dallas, TX
Minkyu Je, Institute of Microelectronics, A*STAR, Singapore,
Jerry (Xicheng) Jiang, Broadcom, Irvine, CA
Wing Hung Ki, HKUST, Hong Kong, China
Kimmo Koli, ST-Ericsson, Turku, Finland
Jae-Youl Lee, Samsung, Yongin, Korea
Tsung-Hsien Lin, National Taiwan University, Taipei, Taiwan
Saska Lindfors, Texas Instruments, Helsinki, Finland
Piero Malcovati, University of Pavia, Pavia, Italy
Chris Mangelsdorf, Analog Devices K.K, Tokyo, Japan
Christoph Sandner, Infineon Technologies Austria, Villach, Austria
Jafar Savoj, Xilinx, San Jose, CA
Michiel Steyaert, KULeuven, Hevrelee, Belgium
Axel Thomsen, Silicon Laboratories, Austin, TX
Ed (Adrianus JM) van Tuijl, University of Twente, Enschede, The Netherlands

DATA CONVERTERS SUBCOMMITTEE
Chair: Boris Murmann, Stanford University, Stanford, CA
Brian Brandt, Maxim Integrated Products, North Chelmsford, MA
Lucien Breems, NXP Semiconductors, Eindhoven, The Netherlands
Marco Corsi, Texas Instruments, Dallas, TX
Michael Flynn, University of Michigan, Ann Arbor, MI
Tetsuya Iizuka, University of Tokyo, Tokyo, Japan
John Khoury, Silicon Laboratories, Austin, TX
Hae-Seung Lee, Massachusetts Institute of Technology, Cambridge, MA
Takahiro Miki, Renesas Electronics, Hyogo, Japan
Gerhard Mitterregger, Intel Mobile Communications Austria, St. Magdalen, Austria
Un-Ku Moon, Oregon State University, Corvallis, OR
Jan Mulder, Broadcom, Bunnik, The Netherlands
Katsu Nakamura, Analog Devices, Wilmington, MA
Ken Nishimura, Agilent, Santa Clara, CA
Shanthi Pavan, Indian Institute Of Technology, Chennai, India
Michael Perrott, Masdar Institute of Science and Technology, Abu Dhabi,
United Arab Emirates
Geert Van der Plas, imec, Leuven, Belgium
Jieh-Tsorng Wu, National Chiao-Tung University, Hsin-Chu, Taiwan

ENERGY-EFFICIENT DIGITAL SUBCOMMITTEE
Chair: Stephen Kosonocky, Advanced Micro Devices, Fort Collins, COKazutami Arimoto, Okayama Prefectural University, Okayama, Japan
Wim Dehaene, KU Leuven, Leuven, Belgium
Vasantha Erraguntla, Intel Technology India, Bangalore, India
Shannon Morton, Nvidia, Bristol, United Kingdom
Byeong-Gyu Nam, Chungnam National University, Daejeon, Korea
Yongha Park, Samsung, Yongin, Korea
Michael Polley, Texas Instruments, Dallas, TX
Bing Sheu, TSMC, Hsinchu, Taiwan
Masaya Sumita, Panasonic, Moriguchi, Japan
Kees van Berkel, ST-Ericsson, Eindhoven, The Netherlands
Victor Zyuban, IBM T.J. Watson Research Center, Yorktown Heights, NY

HIGH-PERFORMANCE DIGITAL SUBCOMMITTEE
Chair: Stefan Rusu, Intel, Santa Clara, CA
Lew Chua-Eoan, Qualcomm, San Diego, CA
Tim Fischer, AMD, Fort Collins, CO
Eric Fluhr, IBM, Austin, TX
Hiroo Hayashi, Toshiba Corporation, Kawasaki, Japan
Anthony Hill, Texas Instruments, Dallas, TX
Atsuki Inoue, Fujitsu, Kawasaki, Japan
Tanay Karnik, Intel, Hillsboro, OR
Tobias Noll, RWTH Aachen University, Aachen, Germany
Luke (Jinuk) Shin, Oracle, Santa Clara, CA
Vladimir Stojanovic, Massachusetts Institute of Technology, Cambridge, MA
Se-Hyun Yang, Samsung, Yongin, Korea

54

2013_Mini_AP_AP 11/8/12 9:57 AM Page 55

COMMITTEESIMAGERS, MEMS, MEDICAL AND DISPLAYS SUBCOMMITTEE
Chair: Roland Thewes, TU Berlin, Berlin, Germany
Ralf Brederlow, Texas Instruments, Freising, Germany
Maysam Ghovanloo, Georgia Institute of Technology, Atlanta, GA
Makoto Ikeda, University of Tokyo, Tokyo, Japan
Robert Johansson, OmniVision, Oslo, Norway
Sam Kavusi, Bosch Research and Technology Center, Palo Alto, CA
Shoji Kawahito, Shizuoka University, Hamamatsu, Japan
Tae-Chan Kim, Samsung, Yongin, Kprea
Hideaki Kurata, Hitachi, Tokyo, Japan
Wentai Liu, UCLA, Los Angeles, CA
Young-Sun Na, LG Electronics, Seoul, Korea
Yoshiharu Nakajima, Japan Display, Kanagawa, Japan
Yusuke Oike, Sony, Kanagawa, Japan
Maurits Ortmanns, University of Ulm, Ulm, Germany
Aaron Partridge, SiTime, Sunnyvale, CA
Michiel Pertijs, TU Delft, Delft, The Netherlands
David Stoppa, Fondazione Bruno Kessler, Trento, Italy
Refet Firat Yazicioglu, IMEC, Leuven, Belgium

MEMORY SUBCOMMITTEE
Chair: Kevin Zhang, Intel, Hillsboro, OR
Colin Bill, Global Foundries, Sunnyvale, CA
Jonathan Chang, TSMC, Hsinchu, Taiwan
Leland Chang, IBM T. J. Watson Research Center Yorktown Heights, NY
Sungdae Choi, SK hynix, Icheon-si, Korea
Michael Clinton, Texas Instruments, Dallas, TX
Jin-Man Han, Samsung Electronics, Hwasung, Korea
Satoru Hanzawa, Hitachi, Tokyo, Japan
Uksong Kang, Samsung Electronics, Hwasung-si, Korea
Atsushi Kawasumi, Toshiba, Kawasaki, Japan
Chulwoo Kim, Korea University, Seoul, Korea
James Sung, Etron Technology, Hsinchu, Taiwan
Yasuhiro Takai, Elpida Memory, Kanagawa, Japan
Daniele Vimercati, Micron Technology, Agrate, Italy
Tadaaki Yamauchi, Renesas Electronics, Itami, JapanRF SUBCOMMITTEE
Chair: Andreia Cathelin, STMicroelectronics, Crolles, France
Ehsan Afshari, Cornell University, Ithaca, NY
Hooman Darabi, Broadcom, Irvine, CA
Brian Floyd, North Carolina State University, Raleigh, NC
Joseph Golat, Motorola, Algonquin, IL
Songcheol Hong, KAIST, Daejeon, Korea
Mike Keaveney, Analog Devices, Limerick, Ireland
Antonio Liscidini, University of Toronto, Toronto, Canada
Brian Otis, University of Washington, Seattle, WA
Ullrich Pfeiffer, University of Wuppertal, Wuppertal, Germany
Gabriel Rebeiz, UCSD, La Jolla, CA
Jussi Ryynanen, Aalto University, Espoo, Finland
Carlo Samori, Politecnico di Milano, Milano, Italy
Marc Tiebout, Infineon Technologies Austria, Villach, Austria
Piet Wambacq, imec, Heverlee, Belgium
Taizo Yamawaki, Renesas Mobile, Takasaki, Japan
Masoud Zargari, Qualcomm-Atheros, Irvine, CA
Jing-Hong Zhan, MediaTek, HsinChu, Taiwan

TECHNICAL DIRECTIONS SUBCOMMITTEE
Chair: Hoi-Jun Yoo, KAIST, Daejeon, Korea
Shekhar Borkar, Intel, Hillsboro, OR
Alison Burdett, Toumaz Technology, Abingdon, United Kingdom
Eugenio Cantatore, Eindhoven University of Technology, Eindhoven, The Netherlands
Eric Colinet, CEA-LETI, Grenoble, France
Paul Heremans, imec, Leuven, Belgium
Fu-Lung Hsueh, TSMC, Hsinchu, Taiwan
Ali Keshavarzi, Cypress, San Jose, CA
Uming Ko, MediaTek, Austin, TX
Tadahiro Kuroda, Keio University, Yokohama, Japan
Shinichiro Mutoh, NTT, Atsugi, Japan
Masaitsu Nakajima, Panasonic, Osaka, Japan
Chris Nicol, Wave Semiconductor, Sunnyvale, CA
Pirooz Pavarandeh, Maxim Integrated Products, San Jose, CA
Yogesh K. Ramadass, Texas Instruments, Dallas, TX
David Ruffieux, CSEM, Neuchated, Switzerland

55

2013_Mini_AP_AP 11/8/12 9:57 AM Page 56

COMMITTEESWIRELESS SUBCOMMITTEE
Chair: David Su, Qualcomm Atheros, San Jose, CA
Didier Belot, STMicroelectronics, Crolles, France
Gangadhar Burra, Texas Instruments, Dallas, TX
Jan Crols, AnSem, Heverlee, Belgium
Hossein Hashemi, University of Southern California, Los Angeles, CA
Myung-Woon Hwang, FCI, Sungnam, Korea
Albert Jerng, Mediatek, Hsinchu, Taiwan
Eric Klumperink, University of Twente, Enschede, The Netherlands
Shouhei Kousai, Toshiba, Kawasaki, Japan
Sven Mattisson, Ericsson, Lund, Sweden
Alyosha Molnar, Cornell University, Ithaca, NY
Kenichi Okada, Tokyo Institute of Technology, Tokyo, Japan
Yorgos Palaskas, Intel, Hillsboro, OR
Aarno Pärssinen, Renesas Mobile, Helsinki, Finland
Woogeun Rhee, Tsinghua University, Beijing, China
Koji Takinami, Panasonic, Yokohama, JapanJan Van Sinderen, NXP, Eindhoven, The Netherlands
Iason Vassiliou, Broadcom, Alimos, Greece

WIRELINE SUBCOMMITTEE
Chair: Daniel Friedman, IBM Thomas J. Watson Research Center, Yorktown Heights, NY
Elad Alon University of California, Berkeley, Berkeley,CAAjith Amerasekera, Texas Instruments, Dallas, TX
Ken Chang, Xilinx, San Jose, CA
SeongHwan Cho, KAIST, Daejon, Korea
Nicola Da Dalt, Infineon, Villach, Austria
Gerrit den Besten, NXP Semiconductors, Eindhoven, The Netherlands
Azita Emami-Neyestanak, California Institute of Technology, Pasadena, CA
Ichiro Fujimori, Broadcom Corporation, Irvine, CA
Chewnpu Jou, TSMC, Hsinchu, Taiwan
Jack Kenney, Analog Devices, Somerset, NJ
Masafumi Nogawa, NTT Microsystem Integration Laboratories, Atsugi, Japan
Frank O’Mahony, Intel, Hillsboro, OR
Ali Sheikholeslami, University of Toronto, Toronto, Canada
Koichi Yamaguchi, Renesas Electronics, Kawasaki, Japan
Hisakatsu Yamaguchi, Fujitsu Laboratories, Kawasaki, Japan

EUROPEAN REGIONAL COMMITTEEITPC EUROPEAN REGIONAL CHAIR
Aarno Pärssinen, Renesas Mobile, Helsinki, Finland
ITPC EUROPEAN REGIONAL VICE CHAIR
Eugenio Cantatore, Eindhoven University of Technology, Eindhoven, The Netherlands
ITPC EUROPEAN REGIONAL SECRETARY
Alison Burdett, Toumaz Technology, Abingdon, United Kingdom
Didier Belot, STMicroelectronics, Crolles, France
Marco Berkhout, NXP Semiconductors, Nijmegen, The Netherlands
Ralf Brederlow, Texas Instruments, Freising, Germany
Lucien Breems, NXP Semiconductors, Eindhoven, The Netherlands
Andreia Cathelin, STMicroelectronics, Crolles, France
Eric Colinet, CEA-LETI, Grenoble, France
Jan Crols, AnSem, Heverlee, Belgium
Nicola Da Dalt, Infineon, Villach, Austria
Wim Dehaene, KU Leuven, Leuven, Belgium
Gerrit den Besten, NXP Semiconductors, Eindhoven, The Netherlands
Paul Heremans, imec, Leuven, Belgium
Robert Johansson, OmniVision, Oslo, Norway
Mike Keaveney, Analog Devices, Limerick, Ireland
Eric Klumperink, University of Twente, Enschede, The Netherlands
Kimmo Koli, ST-Ericsson, Turku, Finland
Saska Lindfors, Texas Instruments, Helsinki, Finland
Antonio Liscidini, University of Toronto, Toronto, Canada
Piero Malcovati, University of Pavia, Pavia, Italy
Sven Mattisson, Ericsson, Lund, Sweden
Gerhard Mitterregger, Intel Mobile Communications Austria, St. Magdalen, Austria
Shannon Morton, Nvidia, Bristol, United Kingdom
Jan Mulder, Broadcom, Bunnik, The Netherlands
Tobias Noll, RWTH Aachen University, Aachen, Germany
Maurits Ortmanns, University of Ulm, Ulm, Germany
Michael Perrott Masdar Institute of Science and Technology,
Abu Dhabi, United Arab Emirates
Michiel Pertijs, TU Delft, Delft, The Netherlands
Ullrich Pfeiffer, University of Wuppertal, Wuppertal, Germany
Bill Redman-White, Southampton University, Southampton, United Kingdom
David Ruffieux, CSEM, Neuchated, Switzerland

56

2013_Mini_AP_AP 11/8/12 9:57 AM Page 57

COMMITTEES
European Members (continued):Jussi Ryynanen, Aalto University, Espoo, Finland
Carlo Samori, Politecnico di Milano, Milano, Italy
Christoph Sandner, Infineon Technologies Austria, Villach, Austria
Michiel Steyaert, KU Leuven, Hevrelee, Belgium
David Stoppa, Fondazione Bruno Kessler, Trento, Italy
Roland Thewes, TU Berlin, Berlin, Germany
Marc Tiebout, Infineon Technologies, Villach, Austria
Kees van Berkel, ST-Ericsson, Eindhoven, The Netherlands
Geert Van der Plas, imec, Leuven, Belgium
Jan Van Sinderen, NXP, Eindhoven, The Netherlands
Ed van Tuijl, University of Twente, Enschede, The Netherlands
Iason Vassiliou, Broadcom, Alimos, Greece
Daniele Vimercati, Micron Technology, Agrate, Italy
Piet Wambacq, imec, Heverlee, Belgium
Refet Firat Yazicioglu, imec, Leuven, Belgium

FAR EAST REGIONAL COMMITTEEITPC FAR EAST REGIONAL CHAIR
Makoto Ikeda, University of Tokyo, Tokyo, JapanITPC FAR EAST REGIONAL VICE-CHAIR
Kazutami Arimoto, Okayama Prefectural University, Soja, JapanITPC FAR EAST REGIONAL SECRETARY
Jae-Youl Lee, Samsung, Yongin, Korea
Jonathan Chang, TSMC, Hsinchu, Taiwan
SeongHwan Cho, KAIST, Daejon, Korea
Sungdae Choi, SK hynix, Icheon-si, Korea
Vasantha Erraguntla, Intel Technology India, Bangalore, India
Jin-Man Han, Samsung Electronics, Hwasung, Korea
Satoru Hanzawa, Hitachi, Tokyo, Japan
Hiroo Hayashi, Toshiba, Kawasaki, Japan
Fu-Lung Hsueh, TSMC, Hsinchu, Taiwan
Myung-Woon Hwang, FCI, Sungnam, Korea
Tetsuya Iizuka, University of Tokyo, Tokyo, Japan
Atsuki Inoue, Fujitsu, Kawasaki, Japan
Minkyu Je, Institute of Microelectronics, A*STAR, Singapore
Albert Jerng, Mediatek, Hsinchu, Taiwan
Chewnpu Jou, TSMC, Hsinchu, Taiwan
Uksong Kang, Samsung Electronics, Hwasung, Korea
Shoji Kawahito, Shizuoka University, Hamamatsu, Japan
Atsushi Kawasumi, Toshiba, Kawasaki, Japan
Wing Hung Ki, HKUST, Hong Kong, China
Chulwoo Kim, Korea University, Seoul, Korea
Tae-Chan Kim, Samsung, Yongin, Korea
Shouhei Kousai, Toshiba, Kawasaki, Japan
Hideaki Kurata, Hitachi, Tokyo, Japan
Tadahiro Kuroda, Keio University, Yokohama, Japan
Tsung-Hsien Lin, National Taiwan University, Taipei, Taiwan
Chris Mangelsdorf, Analog Devices K.K, Tokyo, Japan
Takahiro Miki, Renesas Electronics, Itami, Japan
Shinichiro Mutoh, NTT, Atsugi, Japan
Young-Sun Na, LG Electronics, Seoul, Korea
Masaitsu Nakajima, Panasonic, Osaka, Japan
Yoshiharu Nakajima, Japan Display, Kanagawa, Japan
Byeong-Gyu Nam, Chungnam National University, Daejeon, Korea
Masafumi Nogawa, NTT Microsystem, Atsugi, Japan
Yusuke Oike, Sony, Atsugi, Japan
Kenichi Okada, Tokyo Institute of Technology, Tokyo, Japan
Yongha Park, Samsung, Yongin, Korea
Shanthi Pavan, Indian Institute of Technology Madras, Chennai, India
Woogeun Rhee, Tsinghua University, Beijing, China
Bing Sheu, TSMC, Hsinchu, Taiwan
Masaya Sumita, Panasonic Corporation, Moriguchi, Japan
James Sung, Etron Technology, Hsinchu, Taiwan
Yasuhiro Takai, Elpida Memory, Sagamihara, Japan
Koji Takinami, Panasonic, Yokohama, Japan
Jieh-Tsorng Wu, National Chiao-Tung University, Hsinchu, Taiwan
Koichi Yamaguchi, Renesas Electronics, Kawasaki, Japan
Hisakatsu Yamaguchi, Fujitsu Laboratories, Kawasaki, Japan
Tadaaki Yamauchi, Renesas Electronics, Itami, Japan
Taizo Yamawaki, Renesas Mobile, Takasaki-shi, Japan
Se-Hyun Yang, Samsung, Yongin-Si, Korea
Hoi-Jun Yoo, KAIST, Daejeon, Korea
Jing-Hong Zhan, MediaTek, Hsinchu, Taiwan

57

2013_Mini_AP_AP 11/8/12 9:57 AM Page 58

CONFERENCE INFORMATIONHOW TO REGISTER FOR ISSCC
Online: This is the fastest, most convenient way to register and will give you immediate email
confirmation of your events. To register online (which requires a credit card), go to the ISSCC
website at www.isscc.org and select the link to the registration website.
FAX, mail or email: Use the “2013 IEEE ISSCC Registration Form” which can be downloaded
from the registration website. All payments must be made in U.S. Dollars, by credit card orcheck. Checks must be made payable to “ISSCC 2013”. It will take several days before you
receive email confirmation when you register using the form. Registration forms received
without full payment will not be processed until payment is received at YesEvents. Please
read the descriptions and instructions on the back of the form carefully.
On site: The On-site Registration and Advance Registration Pickup Desks at ISSCC 2013 will
be located in the Yerba Buena Ballroom Foyer at the San Francisco Marriott Marquis. All participants, except as noted below, should register or pick up their registration materials atthese desks as soon as possible. Pre-registered Presenting Authors and pre-registeredmembers of the ISSCC Program and Executive Committees must go to the Nob Hill Room,Ballroom level, to collect their conference materials.
REGISTRATION DESK HOURS:
Saturday, February 16
4:00 pm to 7:00 pm
Sunday, February 17
6:30 am to 8:30 pm
Monday, February 18
6:30 am to 3:00 pm
Tuesday, February 19
8:00 am to 3:00 pm
Wednesday, February 20
8:00 am to 3:00 pm
Thursday, February 21
7:00 am to 2:00 pm
Students must present their Student ID at the Registration Desk to receive the student rates.
Those registering at the IEEE Member rate must provide their IEEE Membership number.
Deadlines: The deadline for registering at the Early Registration rates is 11:59 pm PacificTime Friday January 11, 2013. After January 11th, and on or before 11:59 pm Pacific Time
Monday January 28, 2013, registrations will be processed at the Late Registration rates.
After January 28th, you must register on site at the On-site rates. You are urged to register
early to obtain the lowest rates and ensure your participation in all aspects of ISSCC 2013.
Cancellations/Adjustments/Substitutions: Prior to 11:59 pm Pacific Time Monday January
28, 2013, conference registration can be cancelled. Fees paid will be refunded (less a processing fee of $75). Registration category or credit card used can also be changed (for a processing fee of $35). Send an email to the registration contractor at ISSCCinfo@yesevents.com
to cancel or make other adjustments. No refunds will be made after 11:59 pm Pacific Time
January 28, 2013. Paid registrants who do not attend the conference will be sent all relevant
conference materials. Transfer of registration to someone else is allowed with WRITTEN permission from the original registrant.
IEEE Membership Saves on ISSCC Registration
Take advantage of reduced ISSCC registration fees by using your IEEE membership number.
If you’re an IEEE member and have forgotten your member number, simply phone IEEE at
1(800) 678-4333 and ask. IEEE membership staff will take about two minutes to look up
your number for you. If you come to register on site without your membership card, you canphone IEEE then, too. Or you can request a membership number look-up by email. Use theonline form at: www.ieee.org/about/help/member_support.html. If you’re not an IEEE member,consider joining before you register to save on your fees. Join online at www.ieee.org/join at
any time and you’ll receive your member number by email. If you join IEEE at the conference,
you can also select a free Society membership. This offer is not available to existing IEEE
members.
SSCS Membership – a Valuable Professional Resource for your Career Growth
Membership in the Solid-State Circuit Society offers you the chance to explore solutions
within a global community of colleagues in our field. Membership extends to you the opportunity to grow and share your knowledge, hone your expertise, expand or specialize your network of colleagues, advance your career, and give back to the profession and your local
community.

58

2013_Mini_AP_AP 11/8/12 9:57 AM Page 59

CONFERENCE INFORMATION
We invite you to join or renew today to participate in exclusive educational events, access toleading research and best practice literature, and start your own career legacy by mentoring
students and young professionals entering our field. It all starts with becoming a member of
the Solid-State Circuit Society where you can:-Connect with your Peers – valuable networking opportunities through our world-class conferences, publication offerings, social media extensions, and interactive educational opportunities.
-Keep up with the latest trends and cutting-edge developments in our industry – through ourelectronic newsletters, member magazine “Solid-State Circuits Magazine”, and our award
winning “Journal of Solid-State Circuits”.
-Valuable career and educational tools - saving you both time and money with 24/7 accessto our website and member-only professional development and educational material; Distinguished Lecturer Tours, Tutorials, and webinars by subject matter experts.
-Exclusive access to SSCS Conference Digests for ISSCC, CICC, A-SSCC, ESSCIRC, and Symposium on VLSI Circuits.
-Publications and EBooks – discounted access to vast online document libraries of journals,
standards, and conference papers offer you one-third of the world’s technical research to
keep your knowledge current. New in 2012-13, two new virtual journals – the RFIC-VJ andthe soon to be available, ESS-CDC.
SSCS Membership Saves Even More on ISSCC Registration
This year, SSCS members will receive an exclusive benefit of a $40 discount on the registration
fee for ISSCC in addition to the IEEE discount. Also, the SSCS will again reward our memberswith a $10 Starbucks gift card when they attend the Conference as an SSCS member in goodstanding.
Join or renew your membership with IEEE’s Solid-State Circuit Society today at sscs.ieee.org– you will not want to miss out on the opportunity and benefits your membership will provide
now and throughout your career.

ITEMS INCLUDED IN REGISTRATION
Technical Sessions: Registration includes admission to all technical and evening sessions
starting Sunday evening and continuing throughout Monday, Tuesday and Wednesday.
ISSCC does not offer partial conference registrations.
Technical Book Display: Several technical publishers will have collections of professional
books and textbooks for sale during the Conference. The Book Display will be open on Monday
from Noon to 7:00 pm; on Tuesday from 10:00 am to 7:00 pm; and on Wednesday from 10:00
am to 3:00 pm.
Demonstration Sessions: Hardware demonstrations will support selected papers during theSocial Hours on Monday and Tuesday.
Author Interviews: Author Interviews will be held Monday, Tuesday and Wednesday
evenings. Authors from each day’s papers will be available to discuss their work.
Social Hour: Social Hour refreshments will be available starting at 5:15 pm on Monday andTuesday in both the Book Display and Author Interview areas.
University Events: Several universities are planning social events during the Conference.
Check the University Events display at the conference for the list of universities, locations
and times of these events.
ISSCC travel mug: A convenient travel mug will be given to all Conference registrants.
Publications: Conference registration includes:-The Digest of Technical Papers in hard copy, on a DVD, and by download. Hard copy/DVD
are available on site during registration hours beginning on Sunday at 10:00 am.
-Download of all paper visuals: The Conference DVD has been replaced by a download of
the Digest and presentation visuals. Instructions and an ID/password will be provided.

OPTIONAL EVENTS
Educational Events: Many educational events are available at ISSCC 2013 for an additional
fee. There are ten 90-minute Tutorials and two all-day Forums on Sunday. There are four additional all-day Forums on Thursday as well as an all-day Short Course. All events include acourse handout in color. The all-day events also include breakfast, lunch and break refreshments. See the schedule for details of the topics and times.

59

2013_Mini_AP_AP 11/8/12 9:57 AM Page 60

CONFERENCE INFORMATION
Women’s Networking Event: ISSCC will be offering a networking event for women in solidstate circuits on Monday at 12:15 pm. This luncheon is an opportunity to hear from an accomplished speaker, get to know other women in the profession and discuss a range of topics
including leadership, work-life balance, and professional development. This event is open to
women only at a discounted fee.

OPTIONAL PUBLICATIONSISSCC 2013 Publications: The following ISSCC 2013 publications can be purchased in advance or on site:
Additional copies of the Digest of Technical Papers in book or DVD format.
2013 Tutorials DVD: All of the 90 minute Tutorials (mailed in May).
2013 Short Course DVD: “RF Blocks for Wireless Transceivers” (mailed in May).
Short Course and Tutorial DVDs contain audio and written English transcripts synchronizedwith the presentation visuals. In addition, the Short Course DVD contains a pdf file of the presentations suitable for printing, and pdf files of key reference material.
Earlier ISSCC Publications: Selected publications from earlier conferences can be purchased.
There are several ways to purchase this material:-Items listed on the registration form can be purchased with registration and picked up at
the conference or mailed to you when available.
-Visit the ISSCC Publications Desk. This desk is located in the registration area and has thesame hours as conference registration. With payment by cash, check or credit card, you canpick up (or order for future delivery) materials at this desk. Tutorial and Short Course DVDsfrom prior conferences are available. See the order form for titles and prices.
-Visit the ISSCC website at www.isscc.org and click on the link “SHOP ISSCC” where you
can order online or download an order form to mail, email or fax. For a small shipping fee,
this material will be sent to you immediately (or when available) and you will not have to wait
until you attend the conference to get it.

HOW TO MAKE HOTEL RESERVATIONSTO ALL ATTENDEES WHO NEED A HOTEL ROOM: We are offering this year a $100 Marriott
rebate coupon! If you register for ISSCC 2013 and spend at least three nights at the San
Francisco Marriott Marquis, a credit of $100 will be applied to your hotel bill. Enjoy theconvenience of staying at the Conference hotel AND save money too! See the hotel reservations website for details.
Online: ISSCC participants are urged to make their hotel reservations at the San Francisco
Marriott Marquis online. Go to the conference website and click on the Hotel Reservation link.
Conference room rates are $229 for a single/double, $249 for a triple and $269 for a quad(per night plus tax). In addition, ISSCC attendees booked in the ISSCC group receive in-room
Internet access for free. All online reservations require the use of a credit card. Online reservations are confirmed immediately. You should print the page containing your confirmation
number and reservation details and bring it with you when you travel to ISSCC.
Telephone: Call 877-622-3056 (US) or 415-896-1600 and ask for “Reservations.” When making your reservation, identify the group as ISSCC 2013 to get the group rate.
Hotel Deadline: Reservations must be received at the San Francisco Marriott Marquis nolater than January 28, 2013 to obtain the special ISSCC rates. A limited number of rooms areavailable at these rates. Once this limit is reached or after January 28th, the group rates
may no longer be available and reservations will be filled at the best available rate.
Changes: Before the hotel deadline, your reservation can be changed by calling the telephone
numbers above. After the deadline, call the Marriott Marquis at 415-896-1600 (ask for “Reservations”). Have your hotel confirmation number ready.

IEEE NON-DISCRIMINATION POLICYIEEE is committed to the principle that all persons shall have equal access to programs, facilities, services, and employment without regard to personal characteristics not related toability, performance, or qualifications as determined by IEEE policy and/or applicable laws.

EVENT PHOTOGRAPHY
Attendance at, or participation in, this conference constitutes consent to the use and distribution by IEEE of the attendee’s image or voice for informational, publicity, promotional
and/or reporting purposes in print or electronic communications media. Video recording byparticipants and other attendees during any portion of the conference is not allowed without special prior written permission of IEEE.

60

2013_Mini_AP_AP 11/8/12 9:57 AM Page 61

CONFERENCE INFORMATIONREFERENCE INFORMATIONTAKING PICTURES, VIDEOS OR AUDIO RECORDINGS DURINGANY OF THE SESSIONS IS NOT PERMITTED
Conference Website:www.isscc.org

ISSCC Email:

ISSCC@ieee.org

Registration questions:

ISSCCinfo@yesevents.com

Hotel Information:

San Francisco Marriott Marquis
Phone: 415-896-1600
55 Fourth Street
San Francisco, CA 94103

Press Information:

Kenneth C. Smith
Phone: 416-418-3034
University of Toronto
Email: lcfujino@aol.com

Registration:

YesEvents
Phone: 410-559-2200 or 800-937-8728
P.O. Box 32862
Baltimore, MD 21282
Fax: 410-559-2217
Email: issccinfo@yesevents.com

Hotel Transportation: Visit the ISSCC website “Attendees” page for helpful travel links andto download a document with directions and pictures of how to get from the San Francisco
Airport (SFO) to the Marriott Marquis. You can get a map and driving directions from thehotel website at www.marriott.com/hotels/travel/sfodt-san-francisco-marriott-marquis/
Next ISSCC Dates and Location: ISSCC 2014 will be held on February 9-13, 2014 at the
San Francisco Marriott Marquis Hotel.

61

2013_Mini_AP_AP 11/8/12 9:57 AM Page 62

CONFERENCE SPACE LAYOUT

GOLDEN GATE BALLROOM

C

B

A

YERBA BUENA BALLROOMSALON 15

SALON 1SALON 14SALON 2

SALON 13

SALON 3

SALON 12SALON 4

SALON 11

SALON 562

SALON 7

NOB HILL ANOB HILL CNOB HILL B

SALON 8SALON 9NOB HILL DSALON 10SALON 6

2013_MiniAP_Cover_AP 11/8/12 10:41 AM Page 63

2013_MiniAP_Cover_AP 11/8/12 10:41 AM Page 64

445 Hoes Lane
P.O. Box 1331
Piscataway, NJ 08855-1331
USA

ISSCC.org

sscs.ieee.org

ISSCC 2013 ADVANCE PROGRAM