Uniform Sector
Standard and Quad Serial FlashGD55B01GEDATASHEET

http://www.elm-tech.com

1

Rev.1.3

GD55B01GE

Uniform Sector
Standard and Quad Serial FlashGD55B01GE

Contents
1

FEATURES .........................................................................................................................................................42

GENERAL DESCRIPTIONS..............................................................................................................................5

3

MEMORY ORGANIZATION...............................................................................................................................94

DEVICE OPERATIONS....................................................................................................................................10
4.1

SPI MODE ............................................................................................................................................................ 10

4.2

QPI MODE............................................................................................................................................................ 10

4.3

RESET FUNCTION .................................................................................................................................................. 10

5

DATA PROTECTION........................................................................................................................................12

6

REGISTERS......................................................................................................................................................14

7

8

6.1

STATUS REGISTER ................................................................................................................................................... 14

6.2

EXTENDED ADDRESS REGISTER .................................................................................................................................. 16

INTERNAL CONFIGURATION REGISTER ...................................................................................................17
7.1

NONVOLATILE CONFIGURATION REGISTER ................................................................................................................... 17

7.2

VOLATILE CONFIGURATION REGISTER ......................................................................................................................... 18

7.3

SUPPORTED CLOCK FREQUENCIES .............................................................................................................................. 21

7.4

DATA SEQUENCE WRAPS BY DENSITY ......................................................................................................................... 21

COMMAND DESCRIPTIONS..........................................................................................................................22
8.1

ENABLE 4-BYTE MODE (B7H) .................................................................................................................................. 27

8.2

DISABLE 4-BYTE MODE (E9H).................................................................................................................................. 27

8.3

WRITE ENABLE (WREN) (06H)................................................................................................................................ 28

8.4

WRITE DISABLE (WRDI) (04H) ................................................................................................................................ 28

8.5

WRITE ENABLE FOR VOLATILE STATUS REGISTER (50H) ................................................................................................. 29

8.6

WRITE STATUS REGISTER (WRSR) (01H/31H) ........................................................................................................... 29

8.7

WRITE EXTENDED ADDRESS REGISTER (C5H)............................................................................................................... 30

8.8

WRITE NONVOLATILE/VOLATILE CONFIGURATION REGISTER (B1H/81H) ......................................................................... 31

8.9

READ STATUS REGISTER (05H/35H) ......................................................................................................................... 31

8.10

READ NONVOLATILE/VOLATILE CONFIGURATION REGISTER (B5H/85H)........................................................................... 32

8.11

READ EXTENDED ADDRESS REGISTER (C8H) ................................................................................................................ 33

8.12

READ DATA BYTES (03H/13H) ................................................................................................................................ 33

8.13

READ DATA BYTES AT HIGHER SPEED (0BH/0CH)........................................................................................................ 34

8.14

QUAD OUTPUT FAST READ (6BH/6CH)..................................................................................................................... 35

8.15

QUAD I/O FAST READ (EBH/ECH) ........................................................................................................................... 35

8.16

QUAD I/O DTR READ (EDH/EEH) ........................................................................................................................... 37

8.17

PAGE PROGRAM (PP) (02H/12H)............................................................................................................................ 38

8.18

QUAD PAGE PROGRAM (32H/34H).......................................................................................................................... 39

http://www.elm-tech.com

2

Rev.1.3

Uniform Sector
Standard and Quad Serial FlashGD55B01GE

8.19

EXTEND QUAD PAGE PROGRAM (C2H/3EH) .............................................................................................................. 40

8.20

SECTOR ERASE (SE) (20H/21H)............................................................................................................................... 41

8.21

32KB BLOCK ERASE (BE32) (52H/5CH)................................................................................................................... 42

8.22

64KB BLOCK ERASE (BE64) (D8H/DCH) .................................................................................................................. 43

8.23

CHIP ERASE (CE) (60H/C7H) .................................................................................................................................. 43

8.24

ENABLE QPI (38H) ................................................................................................................................................ 44

8.25

DISABLE QPI (FFH) ................................................................................................................................................ 44

8.26

DEEP POWER-DOWN (DP) (B9H)............................................................................................................................. 45

8.27

RELEASE FROM DEEP POWER-DOWN (ABH) ............................................................................................................... 45

8.28

READ UNIQUE ID (4BH).......................................................................................................................................... 46

8.29

READ IDENTIFICATION (RDID) (9FH/9EH) ................................................................................................................. 47

8.30

PROGRAM/ERASE SUSPEND (PES) (75H) ................................................................................................................... 48

8.31

PROGRAM/ERASE RESUME (PER) (7AH) ................................................................................................................... 48

8.32

ERASE SECURITY REGISTERS (44H) ............................................................................................................................ 49

8.33

PROGRAM SECURITY REGISTERS (42H)....................................................................................................................... 50

8.34

READ SECURITY REGISTERS (48H) ............................................................................................................................. 51

8.35

INDIVIDUAL BLOCK/SECTOR LOCK (36H)/UNLOCK (39H)/READ (3DH)........................................................................... 52

8.36

GLOBAL BLOCK/SECTOR LOCK (7EH) OR UNLOCK (98H)............................................................................................... 53

8.37

ENABLE RESET (66H) AND RESET (99H)..................................................................................................................... 54

8.38

READ SERIAL FLASH DISCOVERABLE PARAMETER (5AH)................................................................................................. 55

9ELECTRICAL CHARACTERISTICS ..............................................................................................................57
9.1

POWER-ON TIMING ................................................................................................................................................ 57

9.2

INITIAL DELIVERY STATE ........................................................................................................................................... 57

9.3

ABSOLUTE MAXIMUM RATINGS ................................................................................................................................ 57

9.4

CAPACITANCE MEASUREMENT CONDITIONS................................................................................................................. 58

9.5

DC CHARACTERISTICS .............................................................................................................................................. 59

9.6

AC CHARACTERISTICS .............................................................................................................................................. 62

10
10.1
11

ORDERING INFORMATION........................................................................................................................70
VALID PART NUMBERS ............................................................................................................................................ 71
PACKAGE INFORMATION .........................................................................................................................73

11.1

PACKAGE SOP16 300MIL ...................................................................................................................................... 73

11.2

PACKAGE WSON8 (8X6MM)................................................................................................................................... 73

11.3

PACKAGE TFBGA-24BALL (5X5 BALL ARRAY)............................................................................................................. 75

12

REVISION HISTORY....................................................................................................................................76

http://www.elm-tech.com

3

Rev.1.3

Uniform Sector
Standard and Quad Serial FlashGD55B01GE

1 FEATURES◆ 1G-bit Serial Flash◆ Fast Program/Erase Speed- 128M-Byte- Page Program time: 0.15ms typical- 256 Bytes per programmable page

- Sector Erase time: 30ms typical- Block Erase time: 0.15/0.22s typical◆ Standard, Quad SPI, DTR,QPI- Chip Erase time: 150s typical- Standard SPI: SCLK, CS#, SI, SO, WP#, RESET#- Quad SPI: SCLK, CS#, IO0, IO1, IO2, IO3, RESET#◆ Flexible Architecture- QPI: SCLK, CS#, IO0, IO1, IO2, IO3, RESET#- Sector of 4K-Byte- SPI DTR (Double Transfer Rate) Read

- Block of 32/64K-Byte- 3 or 4-Byte Address Mode

- Erase/Program Suspend/Resume◆ High Speed Clock Frequency◆ Low Power Consumption- 133MHz for fast read

- 32μA typical stand-by current- Quad I/O Data transfer up to 532Mbits/s- 4μA typical power-down current- QPI Mode Data transfer up to 532Mbits/s- DTR Quad I/O Data transfer up to 720Mbits/s◆ Advanced Security Features- 128-bit Unique ID◆ Allows XIP (eXecute in Place) Operation- 4K-Byte Security Registers With OTP Lock

- High speed Read reduce overall XiP instruction fetch time
- Continuous Read with Wrap further reduce data latency tofill up SoC cache◆ Single Power Supply Voltage- Full voltage range: 2.7~3.6V◆ Software/Hardware Write Protection◆ Endurance and Data Retention- Write protect all/portion of memory via software- Minimum 100,000 Program/Erase Cycles- Enable/Disable protection with WP# Pin- 20-year data retention typical- Individual Block Protection◆ Package Information- SOP16 300mil- WSON8 (8x6mm)- TFBGA-24ball (5x5 Ball Array)

http://www.elm-tech.com

4

Rev.1.3

Uniform Sector
Standard and Quad Serial Flash2

GD55B01GE

GENERAL DESCRIPTIONSThe GD55B01GE (1G-bit) Serial flash supports the standard Serial Peripheral Interface (SPI), and supports the Quad
SPI and DTR mode: Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO), I/O2 (WP#), I/O3, and RESET#. The
Quad I/O & Quad output data is transferred with speed of 532Mbits/s, and the DTR Quad I/O data is transferred withspeed of 720Mbits/s.

CONNECTION DIAGRAM AND PIN DESCRIPTION
Figure 1 Connection Diagram for SOP16 package

IO3

1

16

SCLK

VCC

2

15

SI
(IO0)

RESET#

3

14

NC

NC

4

13

DNU

NC

5

12

NC

DNU

6

11

DNU

CS#

7

10

VSS

SO
(IO1)

8

9

WP#
(IO2)

Top View

16-LEAD SOP
Table 1 Pin Description for SOP16 package
Pin No.

Pin Name

I/O

Description

1

IO3

I/O

Data Input Output 3

2

VCC

3

RESET#

6/11/13

DNU

7

CS#

I

Chip Select Input

8

SO (IO1)

I/O

Data Output (Data Input Output 1)

9

WP# (IO2)

I/O

Write Protect Input (Data Input Output 2)

10

VSS

15

SI (IO0)

I/O

Data Input (Data Input Output 0)

16

SCLK

I

Serial Clock Input

Power Supply
I

Reset Input
Do Not Use (It may connect to internal signal inside)

GroundNote:
1. CS# must be driven high if chip is not selected. Please don’t leave CS# floating any time after power is on.
2. The DNU pin must be floating. It may connect to internal signal inside.
3. The NC pin is not connected to any internal signal. It is OK to connect it to the system ground (GND) or leave it floating.
4. The RESET# pin is a dedicated hardware reset pin regardless of device settings or operation states. If the hardware reset

http://www.elm-tech.com

5

Rev.1.3

Uniform Sector
Standard and Quad Serial FlashGD55B01GE

function is not used, this pin must be connected to VCC in the system.
5. If WP# is unused, it must be driven high by the host, or an external pull-up resistor must be placed on the PCB in order
to avoid allowing WP# input to float.
Figure 2 Connection Diagram for WSON8 package

CS#

1

SO
(IO1)

2

WP#
(IO2)

3

6 SCLKVSS

4

5Top View

8

VCC

7

IO3

SI
(IO0)

8–LEAD WSON
Table 2 Pin Description for WSON8 package
Pin No.

Pin Name

I/O

Description

1

CS#

I

Chip Select Input

2

SO (IO1)

I/O

Data Output (Data Input Output 1)

3

WP# (IO2)

I/O

Write Protect Input (Data Input Output 2)

4

VSS

5

SI (IO0)

I/O

Data Input (Data Input Output 0)

6

SCLK

I

Serial Clock Input

7

IO3

I/O

Data Input Output 3

8

VCC

GroundPower Supply

Note:
1.

CS# must be driven high if chip is not selected. Please don’t leave CS# floating any time after power is on.

2.

If WP# is unused, it must be driven high by the host, or an external pull-up resistor must be placed on the PCB in order
to avoid allowing WP# input to float.

http://www.elm-tech.com

6

Rev.1.3

Uniform Sector
Standard and Quad Serial FlashGD55B01GE

Figure 3 Connection Diagram for TFBGA24 5x5 ball array package

Top View
A2

A3

A4

A5

NC

NC

RESET#

DNU

B1

B2

B3

B4

B5

NC

SCLK

VSS

VCC

NC

C1

C2

C3

C4

C5

CS#

D2

VSS

(5)

D1
(5)

VCC

E1
NC

DNU

WP#
(IO2)

DNU

D3

D4

D5

IO3

NC

E4

E5

SO(IO1) SI(IO0)

E2

E3

NC

NC

(5)

VCC

VSS(5)

24-BALL TFBGA (5x5 ball array)
Table 3 Ball Description for TFBGA24 5x5 ball array package
Pin No.

Pin Name

I/O

Description

A4

RESET#

I

Reset Input

A5/C3/C5

DNU

B2

SCLK

B3/C1/E5

VSS

Ground

B4/D1/E4

VCC

Power Supply

C2

CS#

I

Chip Select Input

C4

WP# (IO2)

I/O

Write Protect Input (Data Input Output 2)

D2

SO (IO1)

I/O

Data Output (Data Input Output 1)

D3

SI (IO0)

I/O

Data Input (Data Input Output 0)

D4

IO3

I/O

Data Input Output 3

Do Not Use (It may connect to internal signal inside)
I

Serial Clock Input

Note:
1. CS# must be driven high if chip is not selected. Please don’t leave CS# floating any time after power is on.
2. The DNU ball must be floating. It may connect to internal signal inside.
3. The NC ball is not connected to any internal signal. It is OK to connect it to the system ground (GND) or leave it floating.
4. The RESET# pin is a dedicated hardware reset pin regardless of device settings or operation states. If the hardware resetfunction is not used, this pin must be connected to VCC in the system.
5. If WP# is unused, it must be driven high by the host, or an external pull-up resistor must be placed on the PCB in order
to avoid allowing WP# input to float.
6. The device can work with only one group of VCC/VSS connected. Ball B4 must be connected to VCC and Ball B3 must
be connected to VSS. The other two groups of VCC/VSS balls (Ball C1/D1/E4/E5) are optional. If Ball C1/D1/E4/E5 are notused, they must be left floating.

http://www.elm-tech.com

7

Rev.1.3

Uniform Sector
Standard and Quad Serial FlashGD55B01GE

BLOCK DIAGRAM

Write Control
Logic

StatusRegister
IO3

SCLK
CS#

SPI
Command &Control Logic

High Voltage
Generators
Page Address
Latch/Counter

SI(IO0)

http://www.elm-tech.com

Flash
MemoryColumn Decode And
256-Byte Page Buffer

SO(IO1)RESET#

Write Protect Logic
and Row Decode

WP#(IO2)

Byte Address
Latch/Counter

8

Rev.1.3

Uniform Sector
Standard and Quad Serial Flash3

GD55B01GE

MEMORY ORGANIZATIONGD55B01GE
Each device has

Each block has

Each sector has

Each page has

128M

64/32K

4K

256

Bytes

512K

256/128

16

-

pages

32K

16/8

-

-

sectors

2K/4K

-

-

-

blocksUNIFORM BLOCK SECTOR ARCHITECTURE
GD55B01GE 64K Bytes Block Sector Architecture
Block
2047

2046

……

……

2

1

0

http://www.elm-tech.com

SectorAddress range

32767

7FFF000H

7FFFFFFH

……

……

……

32752

7FF0000H

7FF0FFFH

32751

7FEF000H

7FEFFFFH

……

……

……

32736

7FE0000H

7FE0FFFH

……

……

……

……

……

……

……

……

……

……

……

……

……

……

……

……

……

……

47

02F000H

02FFFFH

……

……

……

32

020000H

020FFFH

31

01F000H

01FFFFH

……

……

……

16

010000H

010FFFH

1500F000H

00FFFFH

……

……

……

0

000000H

000FFFH

9

Rev.1.3

Uniform Sector
Standard and Quad Serial FlashGD55B01GE

4 DEVICE OPERATIONS
4.1

SPI ModeStandard SPI
The GD55B01GE features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select (CS#), Serial
Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported. Input data is latched on the risingedge of SCLK and data shifts out on the falling edge of SCLK.
Quad SPIThe GD55B01GE supports Quad SPI operation when using the “Quad Output Fast Read”, “Quad I/O Fast Read”, “QuadPage Program” (6BH/6CH, EBH/ECH, 32H/34H, C2H/3EH) commands. These commands allow data to be transferred
to or from the device at four times the rate of the standard SPI. When using the Quad SPI command the SI and SO pins
become bidirectional I/O pins: IO0 and IO1.
DTR Quad SPI
The GD55B01GE supports DTR Quad SPI operation when using the “DTR Quad I/O Fast Read” (EDH/EEH) command.
These commands allow data to be transferred to or from the device at eight times the rate of the standard SPI, and data
output will be latched on both rising and falling edges of the serial clock. When using the DTR Quad SPI command the
SI and SO pins become bidirectional I/O pins: IO0 and IO1.

4.2

QPI Mode

The GD55B01GE supports Quad Peripheral Interface (QPI) operations only when the device is switched fromStandard/Quad SPI mode to QPI mode using the “Enable the QPI (38H)” command. The QPI mode utilizes all four IO pins
to input the command code. Standard/Quad SPI mode and QPI mode are exclusive. Only one mode can be active at any
given times. “Enable the QPI (38H)” and “Disable the QPI (FFH)” commands are used to switch between these two modes.
Upon power-up and after software reset using “Enable Reset (66H) and Reset (99H)” command, the default state of thedevice is Standard/Quad SPI mode.

4.3

RESET Function

The RESET# pin allows the device to be reset by the control.
The RESET# pin goes low for a minimum period of tRLRH will reset the flash. After reset cycle, the flash is at the following
states:- Standby mode
- All the volatile bits will return to the default status as power on.

http://www.elm-tech.com

10

Rev.1.3

Uniform Sector
Standard and Quad Serial Flash
Figure 4 RESET ConditionCS#

RESET#RESET

http://www.elm-tech.com

11

Rev.1.3

GD55B01GE

Uniform Sector
Standard and Quad Serial Flash5

GD55B01GEDATA PROTECTION

The GD55B01GE provide the following data protection methods:◆

Write Enable (WREN) command: The WREN command is set the Write Enable Latch bit (WEL). The WEL bit will
return to reset by the following situation:- Power-Up/ Software reset (66H+99H)- Write Disable (WRDI)- Write Status Register (WRSR)- Write Extended Address Register (WEAR)- Write Nonvolatile Configuration Register (WNVCR)- Write Volatile Configuration Register (WVCR)- Page Program (PP)- Sector Erase (SE) / Block Erase (BE) / Chip Erase (CE)- Erase Security Registers / Program Security Registers◆

Software Protection Mode:-The Block Protect (BP4, BP3, BP2, BP1, and BP0) bits define the section of the memory array that can be readbut cannot be changed.
- Individual Block Protection bit provides the protection selection of each individual block.

◆Hardware Protection Mode: WP# goes low to protect the BP0~BP4 bits and SRP0 bit.

◆

Deep Power-Down Mode: In Deep Power-Down Mode, all commands are ignored except the Release from DeepPower-Down Mode command and reset command (66H+99H).
Table 4. GD55B01GE Block Protected area size
Status Register Content

Memory Content

BP4

BP3

BP2

BP1

BP0

BlocksAddresses

Density

Portion

X

0

0

0

0

NONE

NONE

NONE

NONE

0

0

0

0

1

2047

07FF0000h-07FFFFFFh

64KB

Upper 1/2048

0

0

0

1

0

2046 to 2047

07FE0000h-07FFFFFFh

128KB

Upper 1/1024

0

0

0

1

1

2044 to 2047

07FC0000h-07FFFFFFh

256KB

Upper 1/512

0

0

1

0

0

2040 to 2047

07F80000h-07FFFFFFh

512KB

Upper 1/256

0

0

1

0

1

2032 to 2047

07F00000h-07FFFFFFh

1MB

Upper 1/128

0

0

1

1

0

2016 to 2047

07E00000h-07FFFFFFh

2MB

Upper 1/64

0

0

1

1

1

1984 to 2047

07C00000h-07FFFFFFh

4MB

Upper 1/32

0

1

0

0

0

1920 to 2047

07800000h-07FFFFFFh

8MB

Upper 1/16

0

1

0

0

1

1792 to 2047

07000000h-07FFFFFFh

16MB

Upper 1/8

0

1

0

1

0

1536 to 2047

06000000h-07FFFFFFh

32MB

Upper 1/4

0

1

0

1

1

1024 to 2047

04000000h-07FFFFFFh

64MB

Upper 1/2

1

0

0

0

1

0

00000000h-0000FFFFh

64KB

Lower 1/2048

1

0

0

1

0

0 to 100000000h-0001FFFFh

128KB

Lower 1/1024

1

0

0

1

1

0 to 300000000h-0003FFFFh

256KB

Lower 1/512

1

0

1

0

0

0 to 700000000h-0007FFFFh

512KB

Lower 1/256

1

0

1

0

1

0 to 1500000000h-000FFFFFh

1MB

Lower 1/128

http://www.elm-tech.com

12

Rev.1.3

Uniform Sector
Standard and Quad Serial FlashGD55B01GE

1

0

1

1

0

0 to 3100000000h-001FFFFFh

2MB

Lower 1/64

1

0

1

1

1

0 to 6300000000h-003FFFFFh

4MB

Lower 1/32

1

1

0

0

0

0 to 127

00000000h-007FFFFFh

8MB

Lower 1/16

1

1

0

0

1

0 to 255

00000000h-00FFFFFFh

16MB

Lower 1/8

1

1

0

1

0

0 to 511

00000000h-01FFFFFFh

32MB

Lower 1/4

1

1

0

1

1

0 to 1023

00000000h-03FFFFFFh

64MB

Lower 1/2

X

1

1

X

X

ALL

00000000h-07FFFFFFh

128MB

ALL

Table 5. GD55B01GE Individual Block Protection (WPS=0)
Block

SectorAddress range

Individual Block Lock Operation

32767

07FF F000h

07FF FFFFh

2048 Blocks

……

……

……

Block Lock: 36H+Address

32752

07FF 0000h

07FF 0FFFh

Block Unlock: 39H+Address

2046

32736~32751

07FE 0000h

07FE FFFFh

Read Block Lock: 3DH+Address

……

……

……

……

Global Block Lock: 7EH

……

……

……

……

Global Block Unlock: 98H

……

……

……

……

1

16~31

0001 0000h

0001 FFFFh

150000 F000h

0000 FFFFh

……

……

……

0

0000 0000h

0000 0FFFh

2047

0

Notes:
1. Protection configuration: This bit is used to select which Write Protect scheme should be used.
2. Individual Block Protection bits are volatile lock bits. Each volatile bit corresponds to and provides volatile protection for
an individual memory sector, which is locked temporarily (protection is cleared when the device is reset or powered down).
3. The first and last sectors will have volatile protections at the 4KB sector level. Each 4KB sector in these sectors can be
individually locked by volatile lock bits setting.

http://www.elm-tech.com

13

Rev.1.3

Uniform Sector
Standard and Quad Serial Flash6

REGISTERS

6.1

Status Register

GD55B01GE

Table 6. Status Register-SR No.1
No.

Bit Name

Description

Note

S7

SRP0

Status Register Protection Bit

Non-volatile writable

S6

BP4

Block Protect Bit

Non-volatile writable

S5

BP3

Block Protect Bit

Non-volatile writable

S4

BP2

Block Protect Bit

Non-volatile writable

S3

BP1

Block Protect Bit

Non-volatile writable

S2

BP0

Block Protect Bit

Non-volatile writable

S1

WEL

Write Enable Latch

Volatile, read only

S0

WIP

Erase/Write In Progress

Volatile, read only

Table 7. Status Register-SR No.2
No.

Bit Name

Description

Note

S15

SUS1

Erase Suspend Bit

Volatile, read only

S14

SRP1

Status Register Protection Bit

Non-volatile writable

S13

EE

Erase Error Bit

Volatile, read only

S12

PE

Program Error

Volatile, read only

S11

LB

Security Register Lock Bit

Non-volatile writable (OTP)

S10

SUS2

Program Suspend Bit

Volatile, read only

S9

Reserved

Reserved

Reserved

S8

ADS

Current Address Mode

Volatile, read only

The status and control bits of the Status Register are as follows:
WIP bit
The Write in Progress (WIP) bit indicates whether the memory is busy in program/erase/write status register or configuration
register progress. When WIP bit sets to 1, means the device is busy in program/erase/write status register or configuration
register progress, when WIP bit sets 0, means the device is not in program/erase/write status register or configuration
register progress.
WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal Write
Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write, Program or Erase command isaccepted.
BP4, BP3, BP2, BP1, BP0 bits
The Block Protect (BP4, BP3, BP2, BP1, and BP0) bits are non-volatile. They define the size of the area to be software
protected against Program and Erase commands. These bits are written with the Write Status Register (WRSR) command.

http://www.elm-tech.com

14

Rev.1.3

Uniform Sector
Standard and Quad Serial FlashGD55B01GE

When the Block Protect (BP4, BP3, BP2, BP1, and BP0) bits are set to 1, the relevant memory area becomes protectedagainst Page Program (PP), Sector Erase (SE) and Block Erase (BE) commands. The Block Protect (BP4, BP3, BP2, BP1,
and BP0) bits can be written provided that the Hardware Protected mode has not been set. The Chip Erase (CE) commandis executed only if none sector or block is protected.
SRP0, SRP1 bits
The Status Register Protect (SRP1 and SRP0) bits are non-volatile Read/Write bits in the status register. The SRP bits
control the method of write protection: software protection, hardware protection, power supply lock-down or one time
programmable protection.
SRP1

SRP0

#WP

Status Register

0

0

X

Software Protected

0

1

0

Hardware Protected

0

1

1

Hardware Unprotected

1

0

X

1

1

X

Power Supply LockDown(1)(2)

One Time Program(2)Description
The Status Register can be written to after a Write Enablecommand, WEL=1.(Default)
WP#=0, the Status Register locked and cannot be written to.
WP#=1, the Status Register is unlocked and can be written toafter a Write Enable command, WEL=1.
Status Register is protected and cannot be written to again until
the next Power-Down, Power-Up cycle.
Status Register is permanently protected and cannot be written
to.

NOTE:
1. When SRP1, SRP0= (1, 0), a Power-Down, Power-Up cycle will change SRP1, SRP0 to (0, 0) state.
2. This feature is available on special order. Please contact GigaDevice for details.
ADS bit
The Address Status (ADS) bit is a read only bit that indicates the current address mode the device is operating in. The
device is in 3-Byte address mode when ADS=0 (default), and in 4-Byte address mode when ADS=1.
SUS1, SUS2 bits
The SUS1 and SUS2 bits are read only bits in the status register (S15 and S10) that are set to 1 after executing an
Program/Erase Suspend (75H) command (The Erase Suspend will set the SUS1 bit to 1, and the Program Suspend will set
the SUS2 bit to 1). The SUS1 and SUS2 bits are cleared to 0 by Erase/Program Resume (7AH) command, software reset(66H+99H) command as well as a power-down, power-up cycle.
LB bit
The LB bit is non-volatile One Time Program (OTP) bit in Status Register (S11) that provide the write protect control andstatus to the Security Registers. The default state of LB bit is 0, the security registers are unlocked. The LB bit can be set
to 1 using the Write Register instruction. The LB bit is One Time Programmable, once they are set to 1, the Security Registers
will become read-only permanently.
PE bit
The Program Error (PE) bit is a read only bit that indicates a program failure. It will also be set when the user attempts tohttp://www.elm-tech.com

15

Rev.1.3

Uniform Sector
Standard and Quad Serial FlashGD55B01GE

program a protected array sector or access the locked OTP space. PE is cleared to "0" after program operation resumes
EE bit
The Erase Error (EE) bit is a read only bit that indicates an erase failure. It will also be set when the user attempts to erase
a protected array sector or access the locked OTP space. EE is cleared to "0" after erase operation resumes

6.2

Extended Address Register
Table 8 Extended Address Register

No.

Name

Description

Note

EA7

Reserved

Reserved

Reserved

EA6

Reserved

Reserved

Reserved

EA5

Reserved

Reserved

Reserved

EA4

Reserved

Reserved

Reserved

EA3

Reserved

Reserved

Reserved

EA2

A26

Address bit

Volatile writable

EA1

A25

Address bit

Volatile writable

EA0

A24

Address bit

Volatile writable

The extended address register is only used when the address mode is 3-Byte mode, as to set the higher address. The
default value of the address bit is “0”.
For the read operation, the whole array can be continually read out with one command. Data output starts from the selected
128Mb, and it can cross the boundary. When the last Byte of the segment is reached, the next Byte (in a continuous reading)is the first Byte of the next segment. However, the EAR (Extended Address Register) value does not change. The random
access reading can only be operated in the selected segment.
The Chip erase command will erase the whole chip and is not limited by EAR selected segment. However, the sector erase,
block erase, program operation are limited in selected segment and will not cross the boundary.
A26, A25, A24 bits
The Extended Address Bits are used only when the device is operating in the 3-Byte Address Mode (ADS=0), which isvolatile writable by C5H command.
If Configuration Register Byte <5> set to FEH, or an “Enter 4-Byte Address Mode (B7H)” instruction is issued, the device
will require 4-Byte address input for all address related instructions, and the Extended Address Bit setting will be ignored.
A26, A25, A24

Die#

Address000

00000 0000h-00FF FFFFh001

00100 0000h-01FF FFFFh010

00200 0000h-02FF FFFFh

011

00300 0000h-03FF FFFFh

100

1

0400 0000h-04FF FFFFh

101

1

0500 0000h-05FF FFFFh

110

10600 0000h-06FF FFFFh

111

1

0700 0000h-07FF FFFFh

http://www.elm-tech.com

16

Rev.1.3

Uniform Sector
Standard and Quad Serial FlashGD55B01GE

7 INTERNAL CONFIGURATION REGISTER
The memory configuration is set by an internal configuration register that is not directly accessible to users. The user canchange the default configuration at power up by using the WRITE NONVOLATILE CONFIGURATION REGISTER.
Information from the nonvolatile configuration register overwrites the internal configuration register during power on or after
a reset.
The user can change the configuration during device operation using the WRITE VOLATILE CONFIGURATION REGISTER
command. Information from the volatile configuration registers overwrite the internal configuration register immediately after
the WRITE command completes.

Nonvolatile to volatile register
download after power-on or RESET

Nonvolatile configuration register

Volatile configuration register

Volatile to internal register download after Write
Volatile Configuration Register Command

Nonvolatile to internal register download after
power-on or RESETInternal configuration register

Device behavior

7.1

Nonvolatile Configuration Register

Nonvolatile Configuration Register bits set the device configuration after power-up or reset. All bits are erased (FFh) unlessstated otherwise. This register is read from and written to using the READ NONVOLATILE CONFIGURATION REGISTER
and the WRITE NONVOLATILE CONFIGURATION REGISTER commands, respectively. The commands use the mainarray address scheme, but only the LSB is used to access different register settings, thereby providing up to 256 Bytes ofregisters (See the table below for the details). A WRITE command to a reserved address will set the device to the default
status of the corresponding Byte.
Table 9 Nonvolatile Configuration Register
Addr

<1>

Settings

Dummy cycle
configuration(6-7)

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

Description

0

0

0

0

0

0

1

1

3 Dummy

0

0

0

0

0

1

0

0

4 Dummy

…

…

…

…

…

…

…

…

Others<3>

On die termination

http://www.elm-tech.com

05~1E: 5~30 Dummy(Default=06h)
Reserved

1

1

1

1

x

x

x

x

ODT Disabled (Default)

1

1

1

0

x

x

x

x

300-Ohm ODT

1

1

0

1

x

x

x

x

150-Ohm ODT

17

Rev.1.3

Uniform Sector
Standard and Quad Serial Flash
1

1

0

0

x

x

x

x

100-Ohm ODT

x

x

x

x

1

1

1

1

50 Ohm (Default)

Driver strength

x

x

x

x

1

1

1

0

35 Ohmconfiguration

x

x

x

x

1

1

0

1

25 Ohm

x

x

x

x

1

1

0

0

18 Ohm

x

x

x

x

1

x

x

x

DLP Disabled (Default)

x

x

x

x

0

x

x

x

DLP Enabled

Protection

x

x

x

x

x

1

x

x

BP Protection (Default)

configuration

x

x

x

x

x

0

x

x

WPS Protection(8)

1

1

1

1

1

1

1

1

3-Byte Address (Default)

1

1

1

1

1

1

1

0

4-Byte Address

DLP enable
<4>

<5>

<6>

<7>

GD55B01GE

Beyond 128Mb
addr configuration

Continuous Readconfiguration(9)Wrapconfiguration(9)OthersReserved

1

1

1

1

1

1

1

1

XIP Disabled (Default)

1

1

1

1

1

1

1

0

XIP Enabled

OthersReserved

1

1

1

1

1

1

1

1

Wrap Disabled (Default)

1

1

1

1

1

1

1

0

64-Byte Wrap

1

1

1

1

1

1

0

1

32-Byte Wrap

1

1

1

1

1

1

0

0

16-Byte Wrap

OthersReserved

Notes:
1. The number of cycles must be set to accord with the clock frequency, which varies by the type of FAST READ command(See Supported Clock Frequencies table). Insufficient dummy clock cycles for the operating frequency causes the memory
to read incorrect data.
2. 03H/13H: SPI 0 dummy; QPI N/A
3. 05H/35H/9EH/9FH: SPI&QPI 0 dummy.
4. 3DH: SPI 0 dummy; QPI 8 dummy.
5. 4BH/5AH/B5H/85H: SPI&QPI 8 dummy.
6. 0BH/0CH/6BH/6CH/48H: SPI 8 dummy; QPI dummy follow CONFIGURATION REGISTER<1> (initiation = 6 dummy)
7. EBH/ECH/EDH/EEH: SPI&QPI dummy follow CONFIGURATION REGISTER<1> (initiation = 6 dummy)
8. When WPS protection is enabled, the entire memory array is being protected after Power-up or Reset.
9. Only Quad I/O (EBH and ECH) and DTR Quad I/O fast read (EDH and EEH) support wrap read and XIP operation.

7.2

Volatile Configuration Register

Volatile Configuration Register bits temporarily set the device configuration after power-up or reset. All bits are erased (FFh)unless stated otherwise. This register is read from and written to using the READ VOLATILE CONFIGURATION REGISTER
and the WRITE VOLATILE CONFIGURATION REGISTER commands, respectively. The commands use the main array
address scheme; however, only the LSB is used to access different register settings to provide up to 256 Bytes of registers(See the table below for the details). A WRITE command to a reserved address will set the device to the default status of
the corresponding Byte.

http://www.elm-tech.com

18

Rev.1.3

Uniform Sector
Standard and Quad Serial FlashGD55B01GE

Table 10 Volatile Configuration Register
Addr

<1>

Settings

Dummy cycle
configuration(6-7)

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

Description

0

0

0

0

0

0

1

1

3 Dummy

0

0

0

0

0

1

0

0

4 Dummy

…

…

…

…

…

…

…

…

Others
1

1

x

x

x

x

ODT Disabled (Default)

1

1

1

0

x

x

x

x

300-Ohm ODT

1

1

0

1

x

x

x

x

150-Ohm ODT

1

1

0

0

x

x

x

x

100-Ohm ODT

x

x

x

x

1

1

1

1

50 Ohm (Default)

Driver strength

x

x

x

x

1

1

1

0

35 Ohmconfiguration

x

x

x

x

1

1

0

1

25 Ohm

x

x

x

x

1

1

0

0

18 Ohm

x

x

x

x

1

x

x

x

DLP Disabled (Default)

x

x

x

x

0

x

x

x

DLP Enabled

Protection

x

x

x

x

x

1

x

x

BP Protection (Default)

configuration

x

x

x

x

x

0

x

x

WPS Protection(8)

1

1

1

1

1

1

1

1

3-Byte Address (Default)

1

1

1

1

1

1

1

0

4-Byte Address

DLP enable

<6>

<7>

Reserved
1

<3>

<5>

(Default=06h)

1
On die termination<4>

05~1E: 5~30 Dummy

Beyond 128Mb
addr configuration

Continuous Readconfiguration(9)Wrapconfiguration(9)OthersReserved

1

1

1

1

1

1

1

1

XIP Disabled (Default)

1

1

1

1

1

1

1

0

XIP Enabled

OthersReserved

1

1

1

1

1

1

1

1

Wrap Disabled (Default)

1

1

1

1

1

1

1

0

64-Byte Wrap

1

1

1

1

1

1

0

1

32-Byte Wrap

1

1

1

1

1

1

0

0

16-Byte Wrap

OthersReserved

Notes:
1. The number of cycles must be set to accord with the clock frequency, which varies by the type of FAST READ command(See Supported Clock Frequencies table). Insufficient dummy clock cycles for the operating frequency causes the memory
to read incorrect data.
2. 03H/13H: SPI 0 dummy; QPI N/A
3. 05H/35H/9EH/9FH: SPI&QPI 0 dummy.
4. 3DH: SPI 0 dummy; QPI 8 dummy.
5. 4BH/5AH/B5H/85H: SPI&QPI 8 dummy.
6. 0BH/0CH/6BH/6CH/48H: SPI 8 dummy; QPI dummy follow CONFIGURATION REGISTER<1> (initiation = 6 dummy)
7. EBH/ECH/EDH/EEH: SPI&QPI dummy follow CONFIGURATION REGISTER<1> (initiation = 6 dummy)
8. When WPS protection is enabled, the entire memory array is being protected after Power-up or Reset.

http://www.elm-tech.com

19

Rev.1.3

Uniform Sector
Standard and Quad Serial FlashGD55B01GE

9. Only Quad I/O (EBH and ECH) and DTR Quad I/O fast read (EDH and EEH) support wrap read and XIP operation.
DLP bit
The DLP bit is Data Learning Pattern Enable bit, which is writable by B1/81H command. For Quad output, Quad I/O andQuad I/O DTR Fast Read commands, a pre-defined “Data Learning Pattern” can be used by the flash memory controller todetermine the flash data output timing on 4 I/O pins. When DLP=0, from the third dummy clock, the flash will output“00110100” Data Learning Pattern sequence on each of the I/O or 4 I/O pins until data output. If the dummy clock is notenough for the output of the whole Data Learning Pattern, the last several bit of the Data Learning Pattern would be cut-off.
During this period, controller can fine tune the data latching timing for each I/O pins to achieve optimum system performance.
DLP=1 will disable the Data Learning Pattern output.
Figure 5. Data Learning Pattern Sequence Diagram (STR, Dummy Clock ≥ 10)
CS#

SCLK
Address

Dummy

Data

Data Learning Pattern

IO[3:0] Command

Address

0

0 F F 0 F 0

0

0

0 D D

7

6

0

7

6

5

4

3

2

1

Data

D D

Note: 12 dummy cycle example
Figure 6. Data Learning Pattern Sequence Diagram (STR, Dummy Clock < 10)
CS#

SCLK
Address

Dummy

Data

Data Learning
Pattern

IO[3:0] Command

Address

0

0 F F 0 F D D

7

6

5

4

3

Data

D D

2

Note: 8 dummy cycle example
Figure 7. Data Learning Pattern Sequence Diagram (DTR, Dummy Clock ≥ 6)
CS#

SCLK
Address

Dummy

Data

Data Learning Pattern

IO[3:0] Command

Address

0

0 F F 0 F 0

0

0

0 D

7

6

0

7

6

5

Note: 7 dummy cycle example

http://www.elm-tech.com

20

Rev.1.3

4

3

2

1

Data

D

Uniform Sector
Standard and Quad Serial FlashGD55B01GE

Figure 8. Data Learning Pattern Sequence Diagram (DTR, Dummy Clock < 6)
CS#

SCLK
Address

Dummy

Data

Data Learning
Pattern

IO[3:0] Command

Address

0

0 F F 0 F D D

7

6

5

4

3

Data

D D

2

Note: 5 dummy cycle example

7.3

Supported Clock Frequencies
Table 11 Clock Frequencies

Number of Dummy
Clock Cycle

Quad Output Fast Read
(6BH/6CH) (Only QPIQuad I/O Fast Read

DTR Quad I/O Fast Read

(EBH/ECH)(EDH/EEH)

Mode) (1)

4

40

40

40

6

84

84

66

8

104

104

84

10 and above

133

133

90

Note:
1.

Quad Output Fast Read (6BH/6CH): SPI Mode 8 dummy.

2.

Values are guaranteed by characterization and not 100% tested in production

3.

Dummy clock cycle listed above is recommended. Please contact GigaDevice for clock frequency of dummy clock
cycle configuration out of the table above.

7.4

Data Sequence Wraps by Density
Table 12 Sequence of Bytes during Wrap

Starting Address

16-Byte Wrap

32-Byte Wrap

64-Byte Wrap00-1-2- . . . -15-0-1- . .

0-1-2- . . . -31-0-1- . .

0-1-2- . . . -63-0-1- . .

1

1-2- . . . -15-0-1-2- . .

1-2- . . . -31-0-1-2- . .

1-2- . . . -63-0-1-2- . .

….

….
15-16-17- . . . -63-0-1- . .

….

….

15

15-0-1-2-3- . . . -15-0-1- . .

15-16-17- . . . -31-0-1- . .

….

….

….

31

-

31-0-1-2-3- . . . -31-0-1- . .

31-32-33- . . . -63-0-1- . .

…

….

….

….

63

-

-

63-0-1- . . . -63-0-1- . .

http://www.elm-tech.com

21

Rev.1.3

Uniform Sector
Standard and Quad Serial Flash8

GD55B01GE

COMMAND DESCRIPTIONSAll commands, addresses and data are shifted in and out of the device, beginning with the most significant bit on the firstrising edge of SCLK after CS# is driven low. Then, the one-Byte command code must be shifted in to the device, with mostsignificant bit first on SI, and each bit is latched on the rising edges of SCLK.
Every command sequence starts with a one-Byte command code. Depending on the command, this might be followed byaddress Bytes, or by data Bytes, or by both or none. CS# must be driven high after the last bit of the command sequence
has been completed. For the command of Read, Fast Read, Read Status Register or Release from Deep Power-Down,
and Read Device ID, the shifted-in command sequence is followed by a data-out sequence. All read instruction can becompleted after any bit of the data-out sequence is being shifted out, and then CS# must be driven high to return todeselected status.
For the command of Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Write Enable, Write
Disable or Deep Power-Down command, CS# must be driven high exactly at a Byte boundary, otherwise the command isrejected, and is not executed. That is CS# must be driven high when the number of clock pulses after CS# being driven low
is an exact multiple of eight. For Page Program, if at any time the input Byte is not a full Byte, nothing will happen and WEL
will not be reset.
Table 13 Commands (Standard/DTR Quad SPI)
Standard SPI
Command name

Code

Command-

Dummy Clock

Address-Data

CyclesAddress

Data

Bytes

Bytes

Software Reset Operations
Enable Reset

66h

1-0-0

0

0

0

Reset

99h

1-0-0

0

0

0

9Eh/9Fh1-0-(1)0

0

1 to ∞

5Ah

1-1-(1)8

3

1 to ∞

4Bh

1-1-(1)8

3(4)1 to ∞

03h1-1-(1)03(4)1 to ∞

0Bh

1-1-(1)8

3(4)1 to ∞

Quad Output Fast Read6Bh1-1-(4)83(4)1 to ∞

Quad I/O Fast ReadEBh

1-4-(4)63(4)1 to ∞

Quad I/O DTR Fast ReadEDh

1-4d-(4d)63(4)

1 to ∞

Read ID Operations
Read Identification
Read Serial Flash
Discoverable Parameter
Read Unique ID
Read Memory Operations
Read Data Bytes
Read Data Bytes at Higher
Speed

Read Memory Operations with 4-Byte Address
4-Byte Read Data Bytes
4-Byte Read Data Bytes atHigher Speed

http://www.elm-tech.com

13h1-1-(1)0

4

1 to ∞

0Ch

1-1-(1)8

4

1 to ∞

22

Rev.1.3

Uniform Sector
Standard and Quad Serial Flash
4-Byte Quad Output Fast

GD55B01GE

6Ch

1-1-(4)8

4

1 to ∞

ECh1-4-(4)6

4

1 to ∞

EEh

1-4d-(4d)64

1 to ∞

Write Enable

06h

1-0-0

0

0

0

Write Disable

04h

1-0-0

0

0

0

50h

1-0-0

0

0

0

Read Status Register-105h1-0-(1)0

0

1 to ∞

Read Status Register-235h1-0-(1)0

0

1 to ∞

B5h

1-1-(1)

8

3(4)

1

85h

1-1-(1)

8

3(4)

1

C8h

1-0-(1)0

0

1 to ∞

Write Status Register-1

01h

1-0-1

0

0

1

Write Status Register-2

31h

1-0-1

0

0

1

B1h

1-1-1

0

3(4)

1

81h

1-1-1

0

3(4)

1

C5h

1-0-1

0

0

1

Page Program

02h

1-1-1

0

3(4)

1 to 256

Quad Page Program

32h

1-1-4

0

3(4)

1 to 256

C2h

1-4-4

0

3(4)

1 to 256

12h

1-1-1

0

4

1 to 256

34h

1-1-4

0

4

1 to 256

3Eh

1-4-4

0

4

1 to 256

Sector Erase

20h

1-1-0

0

3(4)

0

32KB Block Erase

52h

1-1-0

0

3(4)

0

64KB Block Erase

D8h

1-1-0

0

3(4)

0

Read
4-Byte Quad I/O Fast Read
4-Byte Quad I/O DTR
Fast Read
Write Operations

Write Enable for Volatile
Status Register
Read Register Operations

Read Nonvolatile
Configuration Register
Read Volatile
Configuration Register
Read Extended Address
RegisterWrite Register Operations

Write Nonvolatile
Configuration Register
Write Volatile Configuration
RegisterWrite Extended Address
Register
Program Operations

Extended Quad Page
Program

Program Operations with 4-Byte Address
4-Byte Page Program
4-Byte Quad Page
Program
4-Byte Extended Quad
Page Program
Erase Operations

http://www.elm-tech.com

23

Rev.1.3

Uniform Sector
Standard and Quad Serial Flash
Chip Erase

C7h/60h

GD55B01GE

1-0-0

0

0

0

Erase Operations with 4-Byte Address
4-Byte Sector Erase

21h

1-1-0

0

4

0

4-Byte 32KB Block Erase

5Ch

1-1-0

0

4

0

4-Byte 64KB Block Erase

DCh

1-1-0

0

4

0

Program/Erase Suspend

75h

1-0-0

0

0

0

Program/Erase Resume

7Ah

1-0-0

0

0

0

48h

1-1-(1)8

3(4)1 to ∞

42h

1-1-1

0

3(4)

1 to 256

44h

1-1-0

0

3(4)

0

38h

1-0-0

0

0

0

B7h

1-0-0

0

0

0

E9h

1-0-0

0

0

0

B9h

1-0-0

0

0

0

ABh

1-0-0

0

0

0

36h

1-1-0

0

3(4)

0

39h

1-1-0

0

3(4)

0

3Dh

1-1-(1)

0

3(4)

1

Global Block/Sector Lock

7Eh

1-0-0

0

0

0

Global Block/Sector Unlock

98h

1-0-0

0

0

0

Suspend/Resume Operations

One-Time Programmable (OTP) Operations
Read Security Registers
Program Security
Registers
Erase Security Registers
QPI Mode Operation
Enable QPI

4-Byte Address Mode Operations
Enable 4-Byte Address
Mode
Disable 4-Byte Address
Mode
Deep Power-Down Operations
Deep Power-Down
Release From DeepPower-Down

Advanced Sector Protection Operations
Individual Block/Sector
Lock
Individual Block/Sector
UnlockRead Individual
Block/Sector Lock

Table 14 Commands (QPI)
Command name

Code

Command-

Dummy Clock

Address

Data

Address-Data

Cycles

Bytes

Bytes

Software Reset Operations
Enable Reset

66h

4-0-0

0

0

0

Reset

99h

4-0-0

0

0

0

9Eh/9Fh4-0-(4)0

0

1 to ∞

Read ID Operations
Read Identification

http://www.elm-tech.com

24

Rev.1.3

Uniform Sector
Standard and Quad Serial Flash
Read Serial Flash Discoverable

GD55B01GE

5Ah

4-4-(4)8

3

1 to ∞

4Bh

4-4-(4)83(4)1 to ∞

Read Data Bytes at Higher Speed

0Bh4-4-(4)63(4)1 to ∞

Quad Output Fast Read6Bh4-4-(4)63(4)1 to ∞

Quad I/O Fast Read

EBh4-4-(4)63(4)1 to ∞

Quad I/O DTR Fast ReadEDh

4-4d-(4d)63(4)

1 to ∞

0Ch4-4-(4)6

4

1 to ∞

4-Byte Quad Output Fast Read6Ch4-4-(4)6

4

1 to ∞

4-Byte Quad I/O Fast ReadECh4-4-(4)6

4

1 to ∞

4-Byte Quad I/O DTR Fast ReadEEh

4-4d-(4d)64

1 to ∞

Write Enable

06h

4-0-0

0

0

0

Write Disable

04h

4-0-0

0

0

0

Write Enable for Volatile Status

50h

4-0-0

0

0

0

Parameter
Read Unique ID
Read Memory Operations

Read Memory Operations with 4-Byte Address
4-Byte Read Data Bytes at Higher
Speed

Write Operations

Register
Read Register Operations
Read Status Register-105h4-0-(4)0

0

1 to ∞

Read Status Register-235h4-0-(4)0

0

1 to ∞

B5h4-4-(4)

8

3(4)

1

85h

4-4-(4)

8

3(4)

1

C8h

4-0-(4)0

0

1 to ∞

FFh

4-0-0

0

0

0

Write Status Register-1

01h

4-0-4

0

0

1

Write Status Register-2

31h

4-0-4

0

0

1

B1h

4-4-4

0

3(4)

1

81h

4-4-4

0

3(4)

1

C5h

4-0-4

0

0

1

Page Program

02h

4-4-4

0

3(4)

1 to 256

Quad Page Program

32h

4-4-4

0

3(4)

1 to 256

Extended Quad Page Program

C2h

4-4-4

0

3(4)

1 to 256

Read Nonvolatile Configuration
Register
Read Volatile Configuration
Register
Read Extended Address Register
QPI Mode Operation
Disable QPIWrite Register Operations

Write Nonvolatile Configuration
RegisterWrite Volatile Configuration
RegisterWrite Extended Address Register
Program Operations

Program Operations with 4-Byte Address

http://www.elm-tech.com

25

Rev.1.3

Uniform Sector
Standard and Quad Serial FlashGD55B01GE

4-Byte Page Program

12h

4-4-4

0

4

1 to 256

4-Byte Quad Page Program

34h

4-4-4

0

4

1 to 256

3Eh

4-4-4

0

4

1 to 256

Sector Erase

20h

4-4-0

0

3(4)

0

32KB Block Erase

52h

4-4-0

0

3(4)

0

64KB Block Erase

D8h

4-4-0

0

3(4)

0

C7h/60h

4-0-0

0

0

0

4-Byte Extended Quad Page
ProgramErase Operations

Chip Erase

Erase Operations with 4-Byte Address
4-Byte Sector Erase

21h

4-4-0

0

4

0

4-Byte 32KB Block Erase

5Ch

4-4-0

0

4

0

4-Byte 64KB Block Erase

DCh

4-4-0

0

4

0

Program/Erase Suspend

75h

4-0-0

0

0

0

Program/Erase Resume

7Ah

4-0-0

0

0

0

Suspend/Resume Operations

One-Time Programmable (OTP) Operations
Read Security Registers

48h4-4-(4)63(4)1 to ∞

Program Security Registers

42h

4-4-4

0

3(4)

1 to 256

Erase Security Registers

44h

4-4-0

0

3(4)

0

Enable 4-Byte Address Mode

B7h

4-0-0

0

0

0

Disable 4-Byte Address Mode

E9h

4-0-0

0

0

0

Deep Power-Down

B9h

4-0-0

0

0

0

Release From Deep Power-Down

ABh

4-0-0

0

0

0

4-ByteAddress Mode Operations

Deep Power-Down Operations

Advanced Sector Protection Operations
Individual Block/Sector Lock

36h

4-4-0

0

3(4)

0

Individual Block/Sector Unlock

39h

4-4-0

0

3(4)

0

Read Individual Block/Sector Lock3Dh4-4-(4)

8

3(4)

1

Global Block/Sector Lock

7Eh

4-0-0

0

0

0

Global Block/Sector Unlock

98h

4-0-0

0

0

0

Table of ID Definitions
GD55B01GE

Operation Code

M7-M0

ID23-ID16

ID15-ID8

ID7-ID0

9EH/9FH

C8

47

1B

FF

http://www.elm-tech.com

26

Rev.1.3

Uniform Sector
Standard and Quad Serial Flash
8.1

GD55B01GE

Enable 4-Byte Mode (B7H)

The Enable 4-Byte Mode command enables accessing the address length of 32-bit for the memory area of the higher
density (larger than 128Mb). After sending the Enable 4-Byte Mode command, the ADS bit (S8) will be set to 1 to indicate
the 4-Byte address mode has been enabled. Once the 4-Byte address mode is enabled, the address length becomes 32bit.
Figure 9 Enable 4-Byte Mode Sequence Diagram (SPI)
CS#
0

1

2

3

4

5

6

7

SCLK
CommandSI

B7H

Figure 10 Enable 4-Byte Mode Sequence Diagram (QPI)

CS#

0

1

SCLK

CommandIO[3:0]8.2

B7H

Disable 4-Byte Mode (E9H)

The Disable 4-Byte Mode command is executed to exit the 4-Byte address mode and enter the 3-Byte address mode. Aftersending the Disable 4-Byte Mode command, the ADS bit (S8) will be clear to be 0 to indicate the 4-Byte address mode has
been disabled, and then the address length will return to 24-bit.
Figure 11 Disable 4-Byte Mode Sequence Diagram (SPI)
CS#
0

1

2

3

4

5

6

7

SCLK
CommandSI

E9H

Figure 12 Disable 4-Byte Mode Sequence Diagram (QPI)

CS#

0

1

SCLK

CommandIO[3:0]

http://www.elm-tech.com

E9H

27

Rev.1.3

Uniform Sector
Standard and Quad Serial Flash
8.3

GD55B01GE

Write Enable (WREN) (06H)

The Write Enable (WREN) command is for setting the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL) bit must
be set prior to every Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE), Write Status Register(WRSR), Write Extended Address Register (WEAR), Write Nonvolatile/Volatile configure register and Erase/Program
Security Registers command. The Write Enable (WREN) command sequence: CS# goes low  sending the Write Enablecommand  CS# goes high.
Figure 13 Write Enable Sequence Diagram (SPI)
CS#
0

1

2

3

4

5

6

7

SCLK
CommandSI

06H

Figure 14 Write Enable Sequence Diagram (QPI)

CS#

0

1

SCLK

CommandIO[3:0]8.4

06H

Write Disable (WRDI) (04H)

The Write Disable command is for resetting the Write Enable Latch (WEL) bit. The Write Disable command sequence: CS#
goes low Sending the Write Disable command CS# goes high. The WEL bit is reset by following condition: Power-up
and upon completion of the Write Status Register, Write Extended Address Register (WEAR), Write Nonvolatile/Volatileconfigure register, Page Program, Sector Erase, Block Erase, Chip Erase, Erase/Program Security Registers and Resetcommands.
Figure 15 Write Disable Sequence Diagram (SPI)
CS#

0

1

2

3

4

5

6

7

SCLK
CommandSI

04H

Figure 16 Write Disable Sequence Diagram (QPI)

CS#

0

1

SCLK

CommandIO[3:0]

http://www.elm-tech.com

04H
28

Rev.1.3

Uniform Sector
Standard and Quad Serial Flash
8.5

GD55B01GE

Write Enable for Volatile Status Register (50H)

The non-volatile Status Register bits can also be written to as volatile bits. This gives more flexibility to change the system
configuration and memory protection schemes quickly without waiting for the typical non-volatile bit write cycles or affecting
the endurance of the Status Register non-volatile bits. The Write Enable for Volatile Status Register command must be
issued prior to a Write Status Register command, and any other commands cannot be inserted between them. Otherwise,
Write Enable for Volatile Status Register will be cleared. The Write Enable for Volatile Status Register command will not set
the Write Enable Latch bit, it is only valid for the Write Status Register command to change the volatile Status Register bit
values.
Figure 17 Write Enable for Volatile Status Register Sequence Diagram (SPI)

CS#

0

1

2

3

4

5

6

7

SCLK

CommandSI

50H

High-ZSO

Figure 18 Write Enable for Volatile Status Register Sequence Diagram (QPI)

CS#

0

1

SCLK

CommandIO[3:0]

8.6

50H

Write Status Register (WRSR) (01H/31H)

The Write Status Register (WRSR) command allows new values to be written to the Status Register. Before it can be
accepted, a Write Enable (WREN) command must previously have been executed. After the Write Enable (WREN)
command has been decoded and executed, the device sets the Write Enable Latch (WEL).
CS# must be driven high after the eighth of the data Byte has been latched in. Otherwise, the Write Status Register (WRSR)
command is not executed. As soon as CS# is driven high, the self-timed Write Status Register cycle (whose duration is tW)
is initiated. While the Write Status Register cycle is in progress, the Status Register may still be read to check the value ofthe Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, andis 0 when it is completed. When the cycle is completed, the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) command allows the user to change the values of the Block Protect (BP4, BP3, BP2,
BP1, and BP0) bits, to define the size of the area that is to be treated as read-only. The Write Status Register (WRSR)
command also allows the user to set or reset the Status Register Protect (SRP0) bit in accordance with the Write Protect(WP#) signal. The Status Register Protect (SRP1 and SRP0) bits and Write Protect (WP#) signal allow the device to be putin the Hardware Protected Mode. The Write Status Register (WRSR) command is not executed once the Hardware
Protected Mode is entered.

http://www.elm-tech.com

29

Rev.1.3

Uniform Sector
Standard and Quad Serial FlashGD55B01GE

Figure 19 Write Status Register Sequence Diagram (SPI)

CS#
1

0

2

3

4

5

6

8

7

9 10 11 12 13 14 15

SCLK
Status Register-1/2

CommandSI
SO

6

01H/31H

7

High-Z

MSB

5

4

3

2

1

0

Figure 20 Write Status Register Sequence Diagram (QPI)

CS#

0

1

2

3

SCLK

Command

SR-1/2

01H/31H

SR in

IO[3:0]

8.7

Write Extended Address Register (C5H)

The Extended Address Register is a volatile register that stores the 4th Byte address (A31-A24) when the device is operatingin the 3-Byte Address Mode (ADS=0). To write the Extended Address Register bits, a Write Enable (06h) instruction must
previously have been executed for the device to accept the Write Extended Address Register instruction (Status Register
bit WEL must equal 1). Once write enabled, the instruction is entered by driving CS# low, sending the instruction code
“C5H”, and then writing the Extended Address Register data Byte.
Upon power up or the execution of a Software/Hardware Reset, the Extended Address Register bit values will be cleared
to 0.
The Extended Address Bit is only effective when the device is in the 3-Byte Address Mode. When the device operates in
the 4-Byte Address Mode (ADS=1), any command with address input of A31-A24 will replace the Extended Address
Register values. It is recommended to check and update the Extended Address Register if necessary when the device isswitched from 4-Byte to 3-Byte Address Mode.
Figure 21 Write Extended Address Register Sequence Diagram (SPI)
CS#
0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15

C5H

7

Extended Addr.
Register In
6 5 4 3 2 1

High-ZMSB

SCLKCommandSI
SO

http://www.elm-tech.com

30

Rev.1.30Uniform Sector
Standard and Quad Serial FlashGD55B01GE

Figure 22 Write Extended Address Register Sequence Diagram (QPI)

CS#

0

1

2

3

SCLK

Command

EAR inC5H

EAR7~0IO[3:0]8.8

Write Nonvolatile/Volatile Configuration Register (B1H/81H)

The Write Nonvolatile/Volatile Configuration Register command allows new values to be written to the Nonvolatile/Volatile
Configuration Register. Before it can be accepted, a Write Enable (WREN) command must previously have been executed.
After the Write Enable (WREN) command has been decoded and executed, the device sets the Write Enable Latch (WEL).
CS# must be driven high after the data Byte has been latched in. If not, the Write Configuration Register command is not
executed. As soon as CS# is driven high, the self-timed Write Configuration Register cycle (whose duration is tW for B1H)
is initiated. The Write In Progress (WIP) bit is 1 during the self-timed Write Configuration Register cycle, and is 0 when it iscompleted. When the cycle is completed, the Write Enable Latch (WEL) is reset.
Figure 23 Write Nonvolatile/Volatile Configuration Register Sequence Diagram (SPI)
CS#
0

1

2

3

4

5

6

7

8

28 29 30 31 32 33 34 35 36 37 38 39

9

SCLK

Command24-bit address
23 22 21
3 2 1

B1H/81HSI

0 7

Configuration register in
6 5 4 3 2 1 0

MSB

MSB

Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.
Figure 24 Write Nonvolatile/Volatile Configuration Register Sequence Diagram (QPI)

CS#

0

1

2

4

3

5

6

7

8

9

SCLK

IO[3:0]CommandAddress

CR in

B1H/81H

Addr. Addr. Addr. Addr. Addr. Addr.

CR7~0

Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.

8.9

Read Status Register (05H/35H)

The Read Status Register command is for reading the Status Register. The Status Register may be read at any time, evenwhile a Program, Erase or Write Status Register cycle is in progress. When one of these cycles is in progress, it isrecommended to check the Write in Progress (WIP) bit before sending a new command to the device. It is also possible toread the Status Register continuously. For command code “05H”/“35H”, the SO will output Status Register bits
S7~S0/S15~S8.

http://www.elm-tech.com

31

Rev.1.3

Uniform Sector
Standard and Quad Serial FlashGD55B01GE

Figure 25 Read Status Register Sequence Diagram (SPI)

CS#
0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

SCLKCommandSI

05H/35H
High-ZSO

SR-1/2 out
5 4 3 2

6

7

1

MSB

5

6

7

0

SR-1/2 out
4 3 2 1

0

7

MSB

Figure 26 Read Status Register Sequence Diagram (QPI)

CS#
0

1

2

3

4

5

SCLK

Command

SR outSR out05H/35H

SR-1/2

SR-1/2

IO[3:0]SR-1/28.10 Read Nonvolatile/Volatile Configuration Register (B5H/85H)
The Read Nonvolatile/Volatile Configuration Register command is for reading the Nonvolatile/Volatile Configuration
Registers. It is followed by a 3-Byte address (A23-A0) or a 4-Byte address (A31-A0) and a dummy Byte, and each bit islatched-in on the rising edge of SCLK. Then the Configuration Register, at that address, is shifted out on SO, and each bit
is shifted out, at a Max frequency fC, on the falling edge of SCLK. Read Nonvolatile/Volatile Configuration Register command,
while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress.
Figure 27 Read Configuration Registers Sequence Diagram (SPI)

CS#

0

1

2

3

4

5

6

7

8

9 10

28 29 30 31

SCLKCommand24-bit address

B5H/85HSI

3

23 22 212

1

0

High-ZSOCS#

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Dummy Byte
SI
SO

7

6

5

4

3

2

1

0

7 6
MSB

5

CR out4 3 2

1

0

Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.

http://www.elm-tech.com

32

Rev.1.3

Uniform Sector
Standard and Quad Serial FlashGD55B01GE

Figure 28 Read Configuration Registers Sequence (QPI)

CS#

0

4

3

2

1

6

5

7

15

8

17

16

SCLK

IO[3:0]dummy

CommandAddress

B5H/85H

Addr. Addr. Addr. Addr. Addr. Addr.

CR outCR7~0

Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.

8.11 Read Extended Address Register (C8H)
The Read Extended Address Register instruction is entered by driving CS# low and shifting the instruction code “C8H” into
the SI pin on the rising edge of SCLK. The Extended Address Register bits are then shifted out on the SO pin at the fallingedge of SCLK with most significant bit (MSB) first.
When the device is in the 4-Byte Address Mode, the value of the address bits is ignored.
Figure 29 Read Extended Address Register Sequence Diagram (SPI)

CS#
0

1

2

3

4

5

6

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

7

6

7

SCLK
CommandSI

C8H
High-ZSO

5

EAR out
4 3 2

1

MSB

7

0

6

5

EAR out
4 3 2

1

0

7

MSB

Figure 30 Read Extended Address Register Sequence Diagram (QPI)

CS#
0

1

2

3

4

5

6

SCLK

IO[3:0]Command

EAR out

EAR out

C8H

EAR7~0EAR7~0EAR7~08.12 Read Data Bytes (03H/13H)
The Read Data Bytes (READ) command is followed by a 3-Byte address (A23-A0) or a 4-Byte address (A31-A0), and each
bit is latched-in on the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, and each bit isshifted out, at a Max frequency fR, on the falling edge of SCLK. The first Byte addressed can be at any location. The address
is automatically incremented to the next higher address after each Byte of data is shifted out. The whole memory can,therefore, be read with a single Read Data Bytes (READ) command. Any Read Data Bytes (READ) command, while an
Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress.

http://www.elm-tech.com

33

Rev.1.3

Uniform Sector
Standard and Quad Serial FlashGD55B01GE

Figure 31 Read Data Bytes Sequence Diagram
CS#
0

1

2

3

4

5

6

8

7

28 29 30 31 32 33 34 35 36 37 38 39

9 10

SCLK

24-bit address

CommandSI

23 22 21

03H

2

1

0

MSB

High-Z

SO

3

MSB

7

6

Data Out1
5 4 3 2 1

Data Out20

Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.

8.13 Read Data Bytes at Higher Speed (0BH/0CH)
The Read Data Bytes at Higher Speed (Fast Read) command is for quickly reading data out. It is followed by a 3-Byte
address (A23-A0) or a 4-Byte address (A31-A0) and dummy clocks, and each bit is latched-in on the rising edge of SCLK.
Then the memory content, at that address, is shifted out on SO, and each bit is shifted out, at a Max frequency f C, on thefalling edge of SCLK. The first Byte addressed can be at any location. The address is automatically incremented to the next
higher address after each Byte of data is shifted out.
Figure 32 Read Data Bytes at Higher Speed Sequence Diagram (SPI)

CS#

0

SCLK

1

2

3

4

5

6

7

8

CommandSI

9 10

28 29 30 31

24-bit address

0BH

3

23 22 212

1

0

High-ZSOCS#

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Dummy Byte

SI

7

6

5

4

3

2

1

0

7
MSB

SO

Data Out1
6 5 4 3 2

1

Data Out2
0 7 6 5MSB

Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.
Figure 33 Read Data Bytes at Higher Speed Sequence Diagram (QPI)

CS#

0

1

2

3

4

6

5

7

13

8

14

15

SCLK

IO[3:0]dummy

CommandAddress

0BH

Addr. Addr. Addr. Addr. Addr. Addr.

Byte 1

Byte 2

Data out

Data out

Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.

http://www.elm-tech.com

34

Rev.1.3

Uniform Sector
Standard and Quad Serial FlashGD55B01GE

8.14 Quad Output Fast Read (6BH/6CH)
The Quad Output Fast Read command is followed by 3-Byte address (A23-A0) or a 4-Byte address (A31-A0) and dummy
clocks, and each bit is latched in on the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cyclefrom IO3, IO2, IO1 and IO0. The first Byte addressed can be at any location. The address is automatically incremented to
the next higher address after each Byte of data is shifted out.
Figure 34 Quad Output Fast Read Sequence Diagram (SPI)
CS#
0

1

2

3

4

5

6

8

7

9 10

28 29 30 31

SCLK

24-bit address

Command23 22 21

6BH

IO0

1

2

3

0

High-Z

IO1

High-Z

IO2

High-Z

IO3
CS#

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

SCLK
Dummy Clocks

IO0

4

0

4

0

4

0

4

0

4

IO1

5

1

5

1

5

1

5

1

5

IO2

6

2

6

2

6

2

6

2

6

IO3

7 3 7 3 7 3 7 3 7
Byte1 Byte2 Byte3 Byte4

Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.
Figure 35 Quad Output Fast Read Sequence Diagram (QPI)

CS#

0

1

2

3

4

6

5

7

13

8

14

15

SCLK

IO[3:0]dummy

CommandAddress

6BH

Addr. Addr. Addr. Addr. Addr. Addr.

Byte 1

Byte 2

Data out

Data out

Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.

8.15 Quad I/O Fast Read (EBH/ECH)
The Quad I/O Fast Read command is similar to the Quad Output Fast Read command but with the capability to input the 3Byte address (A23-0) or a 4-Byte address (A31-A0) and a “Continuous Read Mode” Byte and dummy clocks. 4-bit per clock
is transferred by IO0, IO1, IO2, IO3, and each bit is latched in on the rising edge of SCLK, then the memory contents are
shifted out 4-bit per clock cycle from IO0, IO1, IO2, IO3. The first Byte addressed can be at any location. The address is
automatically incremented to the next higher address after each Byte of data is shifted out.

http://www.elm-tech.com

35

Rev.1.3

Uniform Sector
Standard and Quad Serial FlashGD55B01GE

Quad I/O Fast Read with “Continuous Read Mode”
The Quad I/O Fast Read command can further reduce command overhead through setting the “Continuous Read Mode”
bits (M7-0) after the input 3-Byte address (A23-A0) or 4-Byte address (A31-A0). If the “Continuous Read Mode” bits (M5-4)= (1, 0), then the next Quad I/O Fast Read command (after CS# is raised and then lowered) does not require the EBH/ECH
command code. If the “Continuous Read Mode” bits (M5-4) do not equal to (1, 0), the next command requires the commandcode, thus returning to normal operation. The only way to quit the Quad I/O Continuous Read Mode” is to set the “Continuous
Read Mode” bits (M5-4) not equal to (1, 0).
Figure 36 Quad I/O Fast Read Sequence Diagram (SPI, M5-4≠ (1, 0))
CS#

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15

19 20 21 22 23

SCLK
Dummy

Command
EBH

4

0

4

0

4

0

4

0

4

0

4

0

4

IO1

5

1

5

1

5

1

5

1

5

1

5

1

5

IO2

6

2

6

2

6

2

6

2

6

2

6

2

6

IO3

7

3

7

3

7

3

7

3

7

3

7

3

7

IO0

A23-16 A15-8 A7-0 M7-0

Byte1 Byte2

Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.
Figure 37 Quad I/O Fast Read Sequence Diagram (QPI, M5-4≠ (1, 0))

CS#

0

1

7

2

8

10

9

15

14

13

SCLK

IO[3:0]CommandAddress

EBH

Addr.

dummy
M7-4 M3-0

Byte 1

Byte 2

Data out

Data out

Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.
Figure 38 Quad I/O Fast Read Sequence Diagram (QPI, M5-4= (1, 0))

CS#

5

0

6

7

8

11

12

13

SCLK

dummy

Address
IO[3:0]Addr.

M7-4 M3-0

Byte 1

Byte 2

Data out

Data out

Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.

Quad I/O Fast Read with “16/32/64-Byte Wrap Around”
The Quad I/O Fast Read command can be used to access a specific portion within a page by issuing Wrap configuration
register Byte prior to EBH/ECH. The data being accessed can be limited to either a 16/32/64-Byte section of a 256-Byte
page. The output data starts at the initial address specified in the command, once it reaches the ending boundary of the

http://www.elm-tech.com

36

Rev.1.3

Uniform Sector
Standard and Quad Serial FlashGD55B01GE

16/32/64-Byte section, the output will wrap around the beginning boundary automatically until CS# is pulled high to terminate
the command.
The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cacheafterwards within a fixed length (16/32/64-Byte) of data without issuing multiple read commands.

8.16 Quad I/O DTR Read (EDH/EEH)
The Quad I/O DTR Read instruction enables Double Transfer Rate throughput on quad I/O of Serial Flash in read mode.
The address (interleave on 4 I/O pins) is latched on both rising and falling edge of SCLK, and data (interleave on 4 I/O pins)
shift out on both rising and falling edge of SCLK. The 8-bit address can be latched-in at one clock, and 8-bit data can beread out at one clock, which means four bits at rising edge of clock, the other four bits at falling edge of clock. The first
address Byte can be at any location. The address is automatically increased to the next higher address after each Byte datais shifted out, so the whole memory can be read out at a single Quad I/O DTR Read command. The address counter rolls
over to 0 when the highest address has been reached.
While Program/Erase/Write Status Register cycle is in progress, Quad I/O DTR Read command is rejected without any
impact on the Program/Erase/Write Status Register current cycle.
Figure 39. DTR Quad I/O Fast Read Sequence Diagram (SPI, M5-4 ≠ (1, 0))
CS#
0

1

2

3

4

5

6

7

8

16 17 18

9 10 11

SCLK
Command

IO0

Dummy

EDH

4 0 4 0 4 0 4 0

4 0 4 0

IO1

5 1 5 1 5 1 5 1

5 1 5 1IO2

6 2 6 2 6 2 6 2

6 2 6 2IO3

7 3 7 3 7 3 7 3

7 3 7 3

M7-0

Byt e1 Byte2

A23-0

Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.
Figure 40. DTR Quad I/O Fast Read Sequence Diagram (QPI, M5-4 ≠ (1, 0))

CS#
0

1

2

3

4

5

6

7

10

11

12

SCLK
CommandIO[3:0]

EDH

dummy

Address
A23- A19- A15- A11- A7- A3- M7- M3A20 A16 A12 A8 A4 A0 M4 M0

Byte 1 Byte 2

Byte nD7- D3- D7- D3D4 D0 D4 D0

Data out

Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.

Quad I/O DTR Read with “Continuous Read Mode”
The Quad I/O DTR Read command can further reduce command overhead through setting the “Continuous Read Mode”
bits (M7-0) after the input address. If the “Continuous Read Mode” bits (M5-4) = (1, 0), then the next Quad I/O DTR Read
command (after CS# is raised and then lowered) does not require the EDH/EEH command code. If the “Continuous Read

http://www.elm-tech.com

37

Rev.1.3

Uniform Sector
Standard and Quad Serial FlashGD55B01GE

Mode” bits (M5-4) do not equal to (1, 0), the next command requires the first EDH/EEH command code, thus returning tonormal operation. The only way to quit the Quad I/O DTR Continuous Read Mode” is to set the “Continuous Read Mode”
bits (M5-4) not equal to (1, 0).
Figure 41. DTR Quad I/O Fast Read Sequence Diagram (M5-4 = (1, 0))
CS#
0

1

2

3

4

5

8

9

10

SCLK
dummy

Address
IO[3:0]A23- A19- A15- A11- A7- A3- M7- M3A20 A16 A12 A8 A4 A0 M4 M0

Byte 1 Byte 2

Byte nD7- D3- D7- D3D4 D0 D4 D0

Data out

Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.

Quad I/O DTR Fast Read with “16/32/64-Byte Wrap Around”
The Quad I/O DTR Fast Read command can be used to access a specific portion within a page by issuing Wrap
configuration register Byte prior to EDH/EEH. The data being accessed can be limited to either a 16/32/64-Byte section of
a 256-Byte page. The output data starts at the initial address specified in the command, once it reaches the ending boundaryof the 16/32/64-Byte section, the output will wrap around the beginning boundary automatically until CS# is pulled high toterminate the command.
The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cacheafterwards within a fixed length (16/32/64-Byte) of data without issuing multiple read commands.

8.17 Page Program (PP) (02H/12H)
The Page Program (PP) command is for programming the memory. A Write Enable (WREN) command must previously
have been executed to set the Write Enable Latch (WEL) bit before sending the Page Program command.
The Page Program (PP) command is entered by driving CS# Low, followed by the command code, three or four address
Bytes and at least one data Byte on SI. If the 8 least significant address bits (A7-A0) are not all zero, all transmitted datathat goes beyond the end of the current page are programmed from the start address of the same page (from the address
whose 8 least significant bits (A7-A0) are all zero). CS# must be driven low for the entire duration of the sequence. The
Page Program command sequence: CS# goes low  sending Page Program command  3-Byte address or 4-Byte
address on SI  at least 1 Byte data on SI  CS# goes high. If more than 256 Bytes are sent to the device, previously
latched data are discarded and the last 256 data Bytes are guaranteed to be programmed correctly within the same page.
If less than 256 data Bytes are sent to device, they are correctly programmed at the requested addresses without having
any effects on the other Bytes of the same page. CS# must be driven high after the eighth bit of the last data Byte has beenlatched in; otherwise the Page Program (PP) command is not executed.
As soon as CS# is driven high, the self-timed Page Program cycle (whose duration is tPP) is initiated. While the Page
Program cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The
Write in Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At some unspecified
time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
A Page Program (PP) command applied to a page which is protected by the Block Protect (BP4, BP3, BP2, BP1, and BP0)
is not executed.

http://www.elm-tech.com

38

Rev.1.3

Uniform Sector
Standard and Quad Serial FlashGD55B01GE

Figure 42 Page Program Sequence Diagram (SPI)

CS#
0

1

2

3

4

5

6

7

8

9 10

28 29 30 31 32 33 34 35 36 37 38 39

SCLKCommand24-bit address

1

6

5

4

3

2

1

2076

2078

2079

0 7

2077

2

2075

3

23 22 21

2074

02H

SI

Data Byte 1

1

0

0

MSB

40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

2073

CS#

2072

MSB

7

6

SCLK
Data Byte 2
7

SI

6

5

4

3

2

Data Byte 3

1

0 7

6

5

4

3

2

Data Byte 256

1

MSB

MSB

0

5

4

3

2

MSB

Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.
Figure 43 Page Program Sequence Diagram (QPI)

CS#
0

1

2

7

8

9

10

11

517

518

519

SCLK

IO[3:0]CommandAddress

Byte 1

Byte 202H

Addr.

Data in

Data in

Byte
256
Data in

Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.

8.18 Quad Page Program (32H/34H)
The Quad Page Program command is for programming the memory using four pins: IO0, IO1, IO2, and IO3. A Write Enable(WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit before sending the Page
Program command. The quad Page Program command is entered by driving CS# Low, followed by the command code
(32H/34H), three or four address Bytes and at least one data Byte on IO pins.
If more than 256 Bytes are sent to the device, previously latched data are discarded and the last 256 data Bytes areguaranteed to be programmed correctly within the same page. If less than 256 data Bytes are sent to device, they arecorrectly programmed at the requested addresses without having any effects on the other Bytes of the same page. CS#
must be driven high after the eighth bit of the last data Byte has been latched in; otherwise the Quad Page Program (PP)command is not executed.
As soon as CS# is driven high, the self-timed Quad Page Program cycle (whose duration is tPP) is initiated. While the Quad
Page Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit.
The Write in Progress (WIP) bit is 1 during the self-timed Quad Page Program cycle, and is 0 when it is completed. At someunspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
A Quad Page Program command applied to a page which is protected by the Block Protect (BP4, BP3, BP2, BP1, and BP0)
is not executed.

http://www.elm-tech.com

39

Rev.1.3

Uniform Sector
Standard and Quad Serial FlashGD55B01GE

Figure 44 Quad Page Program Sequence Diagram (SPI)

CS#

0

1

2

3

4

5

6

7

8

9 10

28 29 30 31 32 33 34 35 36 37 38 39

SCLKCommand24-bit address3

Byte1 Byte2
0 4

0

4

0

4

0

4

0

IO1

5

1

5

1

5

1

5

1

IO2

6

2

6

2 6

2 6

2

IO3

7

3

7

3 7

3 7

3

539

1

537

2

538

32H

IO0

23 22 21

542

543

541

40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

540

CS#

536

MSB

SCLK

IO0

4

IO1

5 1

5 1

5 1

IO2

6 2

6 2

IO3

7 3

7 3

0

4

0

4

0 4

0

4

Byte11Byte12

Byte2534

Byte256

0

4 0

4

5 1

5 1

5 1

5 1

5 1

5 1

5 1

5 1

5 1

6 2

6 2

6 2

6 2

6 2

6 2

6 2

6 2

6 2

6 2

7 3

7 3

7 3

7 3

7 3

7 3

7 3

7 3

7 3

7 3

0

4

0

0

4

0 4

0 4

0

Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.
Figure 45 Quad Page Program Sequence Diagram (QPI)

CS#

0

1

7

2

8

9

10

11

517

518

519

SCLK

IO[3:0]CommandAddress

Byte 1

Byte 232H

Addr.

Data out

Data out

Byte
256
Data out

Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.

8.19 Extend Quad Page Program (C2H/3EH)
The Extend Quad Page Program command is for programming the memory using four pins: IO0, IO1, IO2, and IO3. A Write
Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit before sending thePage Program command. The extend quad Page Program command is entered by driving CS# Low, followed by thecommand code (C2H/3EH), three or four address Bytes and at least one data Byte on IO pins.
If more than 256 Bytes are sent to the device, previously latched data are discarded and the last 256 data Bytes areguaranteed to be programmed correctly within the same page. If less than 256 data Bytes are sent to device, they are

http://www.elm-tech.com

40

Rev.1.3

Uniform Sector
Standard and Quad Serial FlashGD55B01GE

correctly programmed at the requested addresses without having any effects on the other Bytes of the same page. CS#
must be driven high after the eighth bit of the last data Byte has been latched in; otherwise the Extend Quad Page Program(EPP) command is not executed.
As soon as CS# is driven high, the self-timed Extend Quad Page Program cycle (whose duration is tPP) is initiated. While
the Extend Quad Page Program cycle is in progress, the Status Register may be read to check the value of the Write In
Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Extend Quad Page Program cycle, and is 0
when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
An Extend Quad Page Program command applied to a page which is protected by the Block Protect (BP4, BP3, BP2, BP1,
and BP0) is not executed.
Figure 46 Extend Quad Page Program Sequence Diagram (SPI)
CS#
0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

SCLK

Address

Command

20 16 12 8

4

0

4

0

4

0

4

0

4

0

4

0

4

IO1

21 17 13 9

5

1

5

1

5

1

5

1

5

1

5

1

5

IO2

22 18 14 10 6

2

6

2

6

2

6

2

6

2

6

2

6

IO3

23 19 15 11 7

3

7

3

7

3 7

3

7

3

7

3

7

C2H

IO0

A23-16 A15-8 A7-0 Byte1 Byte2 Byte3 Byte4 Byte5

Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.
Figure 47 Extend Quad Page Program Sequence Diagram (QPI)

CS#

0

1

7

2

8

9

10

11

517

518

519

SCLK

IO[3:0]CommandAddress

Byte 1

Byte 2

C2H

Addr.

Data out

Data out

Byte
256
Data out

Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.

8.20 Sector Erase (SE) (20H/21H)
The Sector Erase (SE) command is erased the all data of the chosen sector. A Write Enable (WREN) command must
previously have been executed to set the Write Enable Latch (WEL) bit. The Sector Erase (SE) command is entered bydriving CS# low, followed by the command code, and 3- Byte address or 4-Byte address on SI. Any address inside thesector is a valid address for the Sector Erase (SE) command. CS# must be driven low for the entire duration of the sequence.
The Sector Erase command sequence: CS# goes low  sending Sector Erase command  3-Byte address or 4-Byte
address on SI  CS# goes high. CS# must be driven high after the eighth bit of the last address Byte has been latched in;otherwise the Sector Erase (SE) command is not executed. As soon as CS# is driven high, the self-timed Sector Erase
cycle (whose duration is tSE) is initiated. While the Sector Erase cycle is in progress, the Status Register may be read tocheck the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Sector Erase

http://www.elm-tech.com

41

Rev.1.3

Uniform Sector
Standard and Quad Serial FlashGD55B01GE

cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL)
bit is reset. A Sector Erase (SE) command applied to a sector which is protected by the Block Protect (BP4, BP3, BP2, BP1,
and BP0) bits is not executed.
Figure 48 Sector Erase Sequence Diagram (SPI)

CS#
0

1

2

3

4

5

6

7

8

9

29 30 31

SCLK

Command

24 Bits Address

20H

SI

2

23 22
MSB

1

0

Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.
Figure 49 Sector Erase Sequence Diagram (QPI)

CS#

0

4

3

2

1

7

6

5

SCLK

CommandAddress

20H

Addr. Addr. Addr. Addr. Addr. Addr.

IO[3:0]Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.

8.21 32KB Block Erase (BE32) (52H/5CH)
The 32KB Block Erase command is erased the all data of the chosen block. A Write Enable (WREN) command must
previously have been executed to set the Write Enable Latch (WEL) bit. The 32KB Block Erase (BE) command is enteredby driving CS# low, followed by the command code, and 3-Byte address or 4-Byte address on SI. Any address inside theblock is a valid address for the 32KB Block Erase command. CS# must be driven low for the entire duration of the sequence.
The 32KB Block Erase command sequence: CS# goes low  sending 32KB Block Erase command  3-Byte address or
4-Byte address on SI  CS# goes high. CS# must be driven high after the eighth bit of the last address Byte has beenlatched in; otherwise the 32KB Block Erase command is not executed. As soon as CS# is driven high, the self-timed Block
Erase cycle (whose duration is tBE1) is initiated. While the Block Erase cycle is in progress, the Status Register may be readto check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Block Erase
cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL)
bit is reset. A 32KB Block Erase command applied to a block which is protected by the Block Protect (BP4, BP3, BP2, BP1,
and BP0) bits is not executed.
Figure 50 32KB Block Erase Sequence Diagram (SPI)
CS#
0

1

2

3

4

5

6

8

7

9

29 30 31SCLK
24 Bits Address

Command

SI

52H

23 22
MSB

2

1

0

Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.

http://www.elm-tech.com

42

Rev.1.3

Uniform Sector
Standard and Quad Serial FlashGD55B01GE

Figure 51 32KB Block Erase Sequence Diagram (QPI)

CS#

0

4

3

2

1

7

6

5

SCLK

CommandAddress

52H

Addr. Addr. Addr. Addr. Addr. Addr.

IO[3:0]Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.

8.22 64KB Block Erase (BE64) (D8H/DCH)
The 64KB Block Erase command is erased the all data of the chosen block. A Write Enable (WREN) command must
previously have been executed to set the Write Enable Latch (WEL) bit. The 64KB Block Erase command is entered bydriving CS# low, followed by the command code, and 3-Byte address or 4-Byte address on SI. Any address inside the block
is a valid address for the 64KB Block Erase command. CS# must be driven low for the entire duration of the sequence.
The 64KB Block Erase command sequence: CS# goes low  sending 64KB Block Erase command  3-Byte address or
4-Byte address on SI  CS# goes high. CS# must be driven high after the eighth bit of the last address Byte has beenlatched in; otherwise the 64KB Block Erase command is not executed. As soon as CS# is driven high, the self-timed Block
Erase cycle (whose duration is tBE2) is initiated. While the Block Erase cycle is in progress, the Status Register may be readto check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Block Erase
cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL)
bit is reset. A 64KB Block Erase command applied to a block which is protected by the Block Protect (BP4, BP3, BP2, BP1,
and BP0) bits is not executed.
Figure 52 64KB Block Erase Sequence Diagram (SPI)
CS#
0

1

2

3

4

5

6

7

8

9

29 30 31SCLK
24 Bits Address

Command

SI

23 22
MSB

D8H

2

0

1

Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.
Figure 53 64KB Block Erase Sequence Diagram (QPI)

CS#

0

1

3

2

4

5

6

7

SCLK

IO[3:0]CommandAddress

D8H

Addr. Addr. Addr. Addr. Addr. Addr.

Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.

8.23 Chip Erase (CE) (60H/C7H)
The Chip Erase (CE) command is erased the all data of the chip. A Write Enable (WREN) command must previously havebeen executed to set the Write Enable Latch (WEL) bit. The Chip Erase (CE) command is entered by driving CS# Low,
followed by the command code on Serial Data Input (SI). CS# must be driven Low for the entire duration of the sequence.

http://www.elm-tech.com

43

Rev.1.3

Uniform Sector
Standard and Quad Serial FlashGD55B01GE

The Chip Erase command sequence: CS# goes low  sending Chip Erase command  CS# goes high. CS# must be
driven high after the eighth bit of the command code has been latched in; otherwise the Chip Erase command is not executed.
As soon as CS# is driven high, the self-timed Chip Erase cycle (whose duration is tCE) is initiated. While the Chip Erase
cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write inProgress (WIP) bit is 1 during the self-timed Chip Erase cycle, and is 0 when it is completed. At some unspecified time
before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Chip Erase (CE) command is executed if theBlock Protect (BP2, BP1, and BP0) bits are 0 The Chip Erase (CE) command is ignored if one or more sectors are protected.
Figure 54 Chip Erase Sequence Diagram (SPI)

CS#
0

1

2

3

4

5

6

7

SCLK
Command

60H/C7H

SI

Figure 55 Chip Erase Sequence Diagram (QPI)

CS#
0

1

SCLK

CommandIO[3:0]60H/C7H

8.24 Enable QPI (38H)
The device support both Standard/Quad SPI and QPI mode. The “Enable QPI (38H)” command can switch the device from
SPI mode to QPI mode. In order to switch the device to QPI mode, “Enable QPI (38H)” command must be issued. Whenthe device is switched from SPI mode to QPI mode, the existing Write Enable Latch and Program/Erase Suspend status,
and the Wrap Length setting will remain unchanged.
Figure 56 Enable QPI mode command Sequence Diagram

CS#

0

1

2

3

4

5

6

7

SCLK
CommandSI

38H

8.25 Disable QPI (FFH)
To exit the QPI mode and return to Standard/Quad SPI mode, the “Disable QPI (FFH)” command must be issued. Whenthe device is switched from QPI mode to SPI mode, the existing Write Enable Latch and Program/Erase Suspend status,
and the Wrap Length setting will remain unchanged.

http://www.elm-tech.com

44

Rev.1.3

Uniform Sector
Standard and Quad Serial Flash
Figure 57

GD55B01GE

Disable QPI mode command Sequence Diagram

CS#

0

1

SCLK

CommandIO[3:0]FFH

8.26 Deep Power-Down (DP) (B9H)
Executing the Deep Power-Down (DP) command is the only way to put the device in the lowest consumption mode (theDeep Power-Down Mode). It can also be used as an extra software protection mechanism, while the device is not in activeuse, since in this mode, the device ignores all Write, Program and Erase commands. Driving CS# high deselects the device,
and puts the device in the Standby Mode (if there is no internal cycle currently in progress). But this mode is not the DeepPower-Down Mode. The Deep Power-Down Mode can only be entered by executing the Deep Power-Down (DP) command.
Once the device has entered the Deep Power-Down Mode, all commands are ignored except the Release from DeepPower-Down (ABH) or Enable Reset (66H) and Reset (99H) commands. These commands can release the device fromthis mode. The Release from Deep Power-Down command releases the device from deep power down mode.
The Deep Power-Down Mode automatically stops at Power-Down, and the device is in the Standby Mode after Power-Up.
The Deep Power-Down command sequence: CS# goes low  sending Deep Power-Down command  CS# goes high.
CS# must be driven high after the eighth bit of the command code has been latched in; otherwise the Deep Power-Down(DP) command is not executed. As soon as CS# is driven high, it requires a delay of tDP before the supply current is reduced
to ICC2 and the Deep Power-Down Mode is entered. Any Deep Power-Down (DP) command, while an Erase, Program or
Write cycle is in progress, is rejected without having any effects on the cycle that is in progress.
Figure 58 Deep Power-Down Sequence Diagram (SPI)

CS#

0

1

2

3

4

5

6

tDP

7

SCLK

CommandDeep Power-down mode

B9H

SI

Figure 59 Deep Power-Down Sequence Diagram (QPI)

CS#

0

1

tDP

SCLK
Deep Power-down mode

CommandIO[3:0]B9H

8.27 Release from Deep Power-Down (ABH)
To release the device from the Power-Down state, the command is issued by driving the CS# pin low, shifting the
instruction code “ABH” and driving CS# high. Release from Power-Down will take the time duration of tRES1 (See AC
Characteristics) before the device will resume normal operation and other command are accepted. The CS# pin must

http://www.elm-tech.com

45

Rev.1.3

Uniform Sector
Standard and Quad Serial FlashGD55B01GE

remain high during the tRES1 time duration.
When used to release the device from the Power-Down state, the command is the same as previously described, After
this time duration the device will resume normal operation and other command will be accepted. If the Release from PowerDown command is issued while an Erase, Program or Write cycle is in process (when WIP equal 1) the command isignored and will not have any effects on the current cycle.
Figure 60

Release Power-Down Sequence Diagram (SPI)

CS#

0

1

2

3

4

5

6

t RES17

SCLK

Command
ABH

SI

Deep Power-down modeStand-by mode

Figure 61 Release Power-Down Sequence Diagram (QPI)

CS#

0

1

tRES1

SCLK
Deep Power-down mode

CommandIO[3:0]Stand-by mode

ABH

8.28 Read Unique ID (4BH)
The Read Unique ID command accesses a factory-set read-only 128bit number that is unique to each device. The Unique
ID can be used in conjunction with user software methods to help prevent copying or cloning of a system.
The Read Unique ID command sequence: CS# goes low  sending Read Unique ID command  3-Byte (000000H) or 4Byte (00000000H) Address 1 Byte Dummy 128bit Unique ID Out CS# goes high.
Figure 62 Read Unique ID Sequence Diagram (SPI)

CS#
0

1

2

3

4

5

6

7

8

9 10

28 29 30 31

SCLKCommandSI

24-bit address

4BH

23 22 21

3

2

1

0

High-ZSOCS#

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

SCLK
Dummy Byte
SI

7

6

5

4

3

2

1

0

Data Out1
Data Out2
7 6 5 4 3 2 1 0 7 6 5
MSB
MSB
Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.
SO

http://www.elm-tech.com

46

Rev.1.3

Uniform Sector
Standard and Quad Serial FlashGD55B01GE

Figure 63 Read Unique ID Sequence Diagram (QPI)

CS#

0

4

3

2

1

7

6

5

17

16

15

8

SCLK

Command
4BH

IO[3:0]Address(000000H)
Addr. Addr. Addr. Addr. Addr. Addr.

dummy

Byte 1

Byte 2

UID out

UID out

Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.

8.29 Read Identification (RDID) (9FH/9EH)
The Read Identification (RDID) command allows the 8-bit manufacturer identification to be read, followed by three Bytes ofdevice identification. The device identification indicates the memory type in the first Byte, and the memory capacity of thedevice in the second Byte. The Read Identification (RDID) command while an Erase or Program cycle is in progress, is notdecoded, and has no effect on the cycle that is in progress. The Read Identification (RDID) command should not be issued
while the device is in Deep Power-Down Mode.
The device is first selected by driving CS# low. Then, the 8-bit command code for the command is shifted in. This is followedby the 32-bit device identification, stored in the memory. Each bit is shifted out on the falling edge of Serial Clock. The Read
Identification (RDID) command is terminated by driving CS# high at any time during data output. When CS# is driven high,the device is in the Standby Mode. Once in the Standby Mode, the device waits to be selected, so that it can receive, decodeand execute commands.
Figure 64 Read Identification ID Sequence Diagram (SPI)
CS#
0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

SCLK

9FH/9EH

SI

7 6
MSB

SO

CS#

Manufacturer ID
5 4 3 2 1

0

7

Memory Type ID23-16
6 5 4 3 2 1 0

MSB

24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

SCLK
SI
SO

7

Capacity ID15-8
6 5 4 3 2 1

MSB

Manufacturer ID

Device ID7-0
7

0

6

5

4

3

2

1

7

0

6

5

4

3

2

1

0

MSB

MSB

Figure 65 Read Identification ID Sequence Diagram (QPI)

CS#

0

1

2

3

5

4

6

7

8

9

10

11

SCLK

IO[3:0]9FH/9EH

http://www.elm-tech.com(MID & DID) LOOP

(MID & DID) LOOP

Command

MID7~0

DID23~1647

Rev.1.3

DID15~8

DID7~0

MID7~0DID

Uniform Sector
Standard and Quad Serial FlashGD55B01GE

8.30 Program/Erase Suspend (PES) (75H)
The Program/Erase Suspend command “75H”, allows the system to interrupt a page program or sector/block erase
operation and then read data from any other sector or block. The Write Register command (01H, B1H) and Erase/Program
Security Registers command (44H, 42H) and Erase commands (20H/21H, 52H/5CH, D8H/DCH, C7H, 60H) and Page
Program command (02H/12H, 32H/34H, C2H/3EH) are not allowed during Program suspend. The Write Register command(01H, B1H) and Erase Security Registers command (44H) and Erase commands (20H/21H, 52H/5CH, D8H/DCH, C7H,
60H) are not allowed during Erase suspend. Program/Erase Suspend is valid only during the page program or sector/blockerase operation. A maximum of time of “tsus” (See AC Characteristics) is required to suspend the program/erase operation.
The Program/Erase Suspend command will be accepted by the device only if the SUS2/SUS1 bit in the Status Register
equal to 0 and WIP bit equal to 1 while a Page Program or a Sector or Block Erase operation is on-going. If the SUS2/SUS1
bit equal to 1 or WIP bit equal to 0, the Suspend command will be ignored by the device. The WIP bit will be cleared from 1
to 0 within “tsus” and the SUS2/SUS1 bit will be set from 0 to 1 immediately after Program/Erase Suspend. A power-off
during the suspend period will reset the device and release the suspend state.
Figure 66 Program/Erase Suspend Sequence Diagram (SPI)
CS#

0

1

2

3

4

5

6

7

tSUS

SCLK

CommandSI

75H
High-ZSO

Accept read command

Figure 67 Program/Erase Suspend Sequence Diagram (QPI)

CS#

0

1

tSUS

SCLK
Accept read command

CommandIO[3:0]75H

8.31 Program/Erase Resume (PER) (7AH)
The Program/Erase Resume command must be written to resume the program or sector/block erase operation after a
Program/Erase Suspend command. The Program/Erase Resume command will be accepted by the device only if the
SUS2/SUS1 bit equal to 1 and the WIP bit equal to 0. After issued the SUS2/SUS1 bit in the status register will be cleared
from 1 to 0 immediately, the WIP bit will be set from 0 to 1 within 200ns and the Sector or Block will complete the erase
operation or the page will complete the program operation. The Program/Erase Resume command will be ignored unless a
Program/Erase Suspend is active.

http://www.elm-tech.com

48

Rev.1.3

Uniform Sector
Standard and Quad Serial FlashGD55B01GE

Figure 68 Program/Erase Resume Sequence Diagram
CS#
0

1

2

3

4

5

6

7

SCLK
CommandSI

7AH
Resume Erase/Program

Figure 69 Program/Erase Resume Sequence Diagram (QPI)

CS#

0

1

SCLK

Resume Program/Erase

CommandIO[3:0]

7AH

8.32 Erase Security Registers (44H)
The GD55B01GE provides 4K-Byte Security Registers which can be erased and programmed individually. These registers
may be used by the system manufacturers to store security and other important information separately from the main
memory array.
The Erase Security Registers command is similar to Sector/Block Erase command. A Write Enable (WREN) command must
previously have been executed to set the Write Enable Latch (WEL) bit.
The Erase Security Registers command sequence: CS# goes low  sending Erase Security Registers command  CS#
goes high. CS# must be driven high after the eighth bit of the last address Byte has been latched in; otherwise the Erase
Security Registers command is not executed. As soon as CS# is driven high, the self-timed Erase Security Registers cycle(whose duration is tSE) is initiated. While the Erase Security Registers cycle is in progress, the Status Register may be readto check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Erase Security
Registers cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable
Latch (WEL) bit is reset. The Security Registers Lock Bit in the Status Register can be used to OTP protect the security
registers. Once the bit is set to 1, the Security Registers will be permanently locked; the Erase Security Registers command
will be ignored.
Address
Security RegisterA23-1600HA15-120000

A11-0
Don’t care

Figure 70 Erase Security Registers command Sequence Diagram (SPI)
CS#
0

1

2

3

4

5

6

7

8

9

29 30 31SCLK
24 Bits Address

Command

SI

44H

23 22
MSB

2

1

0

Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.

http://www.elm-tech.com

49

Rev.1.3

Uniform Sector
Standard and Quad Serial FlashGD55B01GE

Figure 71 Erase Security Registers command Sequence Diagram (QPI)

CS#

0

4

3

2

1

7

6

5

SCLK

CommandAddress

44H

Addr. Addr. Addr. Addr. Addr. Addr.

IO[3:0]Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.

8.33 Program Security Registers (42H)
The Program Security Registers command is similar to the Page Program command. The security register contains 16
pages content. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL)
bit before sending the Program Security Registers command. The Program Security Registers command is entered bydriving CS# Low, followed by the command code (42H), three address Bytes and at least one data Byte on SI. As soon asCS# is driven high, the self-timed Program Security Registers cycle (whose duration is tPP) is initiated. While the Program
Security Registers cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP)
bit. The Write in Progress (WIP) bit is 1 during the self-timed Program Security Registers cycle, and is 0 when it is completed.
At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
If the Security Registers Lock Bit is set to 1, the Security Registers will be permanently locked. Program Security Registers
command will be ignored.
Address
Security RegisterA23-1600HA15-120000

A11-8Page Address

A7-0
Byte Address

Figure 72 Program Security Registers command Sequence Diagram (SPI)

CS#
0

1

2

3

4

5

6

7

8

9 10

28 29 30 31 32 33 34 35 36 37 38 39

SCLKCommand24-bit address
1

6

5

4

3

2

1

2076

2078

2079

0 7

2077

2

2075

3

23 22 21

2074

1

0

MSB

40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

2072

MSB
CS#

2073

42H

SI

Data Byte 1

SCLK
Data Byte 2
SI

7

6

5

4

MSB

3

2

Data Byte 3

1

0 7

6

5

4

3

2

MSB

Data Byte 256

1

0

7

6

5

4

3

2

MSB

Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.

http://www.elm-tech.com

50

Rev.1.30Uniform Sector
Standard and Quad Serial FlashGD55B01GE

Figure 73 Program Security Registers command Sequence Diagram (QPI)

CS#
0

7

2

1

11

10

9

8

517

519

518

SCLK
CommandAddress

Byte 1

Byte 242H

Addr.

Data in

Data inIO[3:0]

Byte
256
Data in

Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.

8.34 Read Security Registers (48H)
The Read Security Registers command is similar to Fast Read command. The command is followed by a 3-Byte or 4-Byte
address (A23-A0 or A31-A0) and a dummy Byte, and each bit is latched-in on the rising edge of SCLK. Then the memory
content, at that address, is shifted out on SO, and each bit is shifted out, at a Max frequency f C, on the falling edge of SCLK.
The first Byte addressed can be at any location. The address is automatically incremented to the next higher address after
each Byte of data is shifted out. Once the A11-A0 address reaches the last Byte of the register (Byte FFFH), it will reset to
000H, the command is completed by driving CS# high.
Address
Security RegisterA23-1600HA15-120000

A11-8Page Address

A7-0
Byte Address

Figure 74 Read Security Registers command Sequence Diagram (SPI)

CS#
0

1

2

3

4

5

6

7

8

9 10

28 29 30 31

SCLKCommand24-bit address

48H

SI

3

23 22 212

1

0

High-ZSOCS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK

Dummy Byte

7 6

SI

5

4

3

2 1

0
Data Out1
5 4 3 2

7 6
MSB

SO

1

0

Data Out2
7 6 5
MSB

Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.
Figure 75 Read Security Registers command Sequence Diagram (QPI)

CS#
0

1

2

3

4

5

6

7

8

23

24

25

SCLK

IO[3:0]dummy

CommandAddress

48H

Addr. Addr. Addr. Addr. Addr. Addr.

Byte 1

Byte 2

Data out

Data out

Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.

http://www.elm-tech.com

51

Rev.1.3

Uniform Sector
Standard and Quad Serial FlashGD55B01GE

8.35 Individual Block/Sector Lock (36H)/Unlock (39H)/Read (3DH)
The individual block/sector lock provides an alternative way to protect the memory array from adverse Erase/Program. In
order to use the Individual Block/Sector Locks, the WPS bit in Configuration Register bit 2 at address 04h must be set to 0.
If WPS=1, the write protection will be determined by the combination of BP (4:0) bits in the Status Register.
The individual Block/Sector Lock command (36H) sequence: CS# goes low SI: Sending individual Block/Sector Lockcommand SI: Sending 3-Byte or 4-Byte individual Block/Sector Lock Address  CS# goes high.
The individual Block/Sector Unlock command (39H) sequence: CS# goes low SI: Sending individual Block/Sector Unlock
command SI: Sending 3-Byte or 4-Byte individual Block/Sector Lock Address  CS# goes high.
The Read individual Block/Sector lock command (3DH) sequence: CS# goes low  SI: Sending Read individual
Block/Sector Lock command SI: Sending 3-Byte or 4-Byte individual Block/Sector Lock Address  SO: The Block/Sector
Lock Bit will out CS# goes high. If the least significant bit (LSB) is1, the corresponding block/sector is locked, if the LSB
is 0, the corresponding block/sector is unlocked, Erase/Program operation can be performed.
Figure 76 Individual Block/Sector Lock command Sequence Diagram (SPI)
CS#
0

1

2

3

4

5

6

7

8

9

29 30 31SCLK

24 Bits Address

Command

SI

23 22
MSB

36H

2

0

1

Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.
Figure 77 Individual Block/Sector Lock command Sequence Diagram (QPI)

CS#

0

4

3

2

1

7

6

5

SCLK

CommandAddress

36H

Addr. Addr. Addr. Addr. Addr. Addr.

IO[3:0]Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.
Figure 78 Individual Block/Sector Unlock command Sequence Diagram (SPI)
CS#
0

1

2

3

4

5

6

7

8

9

29 30 31SCLK

24 Bits Address

Command

SI

39H

23 22
MSB

2

1

0

Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.

http://www.elm-tech.com

52

Rev.1.3

Uniform Sector
Standard and Quad Serial FlashGD55B01GE

Figure 79 Individual Block/Sector Unlock command Sequence Diagram (QPI)

CS#

0

4

3

2

1

6

5

7

SCLK

CommandAddress

39H

Addr. Addr. Addr. Addr. Addr. Addr.

IO[3:0]Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.
Figure 80 Read Individual Block/Sector lock command Sequence Diagram (SPI)CS#
0 1 2 3 4

5 6 7 8 929 30 31 32 33 34 35 36 37 38 39

SCLKCommand

SI

3DH

23 22

2

1 0
Lock value out
X X X X X X X 0

High-Z

SO

MSB

MSB

Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.
Figure 81 Read Individual Block/Sector lock command Sequence Diagram (QPI)

CS#

0

2

1

4

3

7

6

5

15

8

16

17

SCLK

IO[3:0]dummy

CommandAddress

3DH

Addr. Addr. Addr. Addr. Addr. Addr.

Data out
Lock Value

Note: The device default is in 24-bit address mode. For 4-Byte mode, the address length becomes 32-bit.

8.36 Global Block/Sector Lock (7EH) or Unlock (98H)
All Block/Sector Lock bits can be set to 1 by the Global Block/Sector Lock command, or can set to 0 by the Global
Block/Sector Unlock command.
The Global Block/Sector Lock command (7EH) sequence: CS# goes low SI: Sending Global Block/Sector Lockcommand CS# goes high.
The Global Block/Sector Unlock command (98H) sequence: CS# goes low SI: Sending Global Block/Sector Unlock
command CS# goes high.
Figure 82 Global Block/Sector Lock Sequence Diagram (SPI)

CS#

0

1

2

3

4

5

SCLK

CommandSI
SO

http://www.elm-tech.com

7EH
High-Z
53

Rev.1.3

6

7

Uniform Sector
Standard and Quad Serial FlashGD55B01GE

Figure 83 Global Block/Sector Lock Sequence Diagram (QPI)

CS#

0

1

SCLK

CommandIO[3:0]

7EH

Figure 84 Global Block/Sector Unlock Sequence Diagram (SPI)
CS#

0

1

2

3

4

5

6

7

SCLK

CommandSI

98H
High-ZSO

Figure 85 Global Block/Sector Unlock Sequence Diagram (QPI)

CS#

0

1

SCLK

CommandIO[3:0]98H

8.37 Enable Reset (66H) and Reset (99H)
If the Reset command is accepted, any on-going internal operation (except in Continuous Read Mode) will be terminatedand the device will return to its default power-on state and lose all the current volatile settings, such as Volatile Status
Register bits, Write Enable Latch status (WEL), Program/Erase Suspend status, Read Parameter setting (P7-P0), DeepPower Down Mode, Continuous Read Mode bit setting (M7-M0).
When Flash is in QPI Mode or Continuous Read Mode (XIP), 66H&99H cannot reset Flash to power-on state. Therefore, it
is recommended to send the following sequence to reset Flash in these modes:
1.

8CLK with IO<3:0>= all “H” or all “L”: ensure Flash quit XIP mode

2.

QPI format 66H/99H: ensure Flash in QPI mode can be reset

3.

SPI format 66H/99H: ensure Flash in SPI mode can be reset

The “Enable Reset (66H)” and the “Reset (99H)” commands can be issued in either SPI or QPI mode. The “Reset (99H)”
command sequence as follow: CS# goes low  Sending Enable Reset command  CS# goes high  CS# goes low 
Sending Reset command  CS# goes high. Once the Reset command is accepted by the device, the device will takeapproximately tRST / tRST_E to reset. During this period, no command will be accepted. Data corruption may happen if
there is an on-going or suspended internal Erase or Program operation when Reset command sequence is accepted by thedevice. It is recommended to check the WIP bit and the SUS2/SUS1 bits in Status Register before issuing the Resetcommand sequence.

http://www.elm-tech.com

54

Rev.1.3

Uniform Sector
Standard and Quad Serial FlashGD55B01GE

Figure 86 Enable Reset and Reset command Sequence Diagram (SPI)

CS#

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

SCLK

CommandCommand

66H

99H

SI

High-ZSO

Figure 87 Enable Reset and Reset command Sequence Diagram (QPI)
CS#

0

0

1

1

SCLK

CommandCommand

66H

99H

IO[3:0]8.38 Read Serial Flash Discoverable Parameter (5AH)
The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional andfeature capabilities of serial flash devices in a standard set of internal parameter tables. These parameter tables can beinterrogated by host system software to enable adjustments needed to accommodate divergent features from multiple
vendors. The concept is similar to the one found in the Introduction of JEDEC Standard, JESD68 on CFI. SFDP is a standard
of JEDEC Standard No.216B.
Figure 88 Read Serial Flash Discoverable Parameter command Sequence Diagram (SPI)

CS#
0

1

2

3

4

5

6

7

8

9 10

28 29 30 31

SCLKCommand24-bit address

5AH

SI

3

23 22 212

1

0

High-ZSOCS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK

Dummy Byte
SI
SO

http://www.elm-tech.com

7

6

5

4

3

2

1

0
7 6
MSB

55

Rev.1.3

Data Out1
5 4 3 2

10Data Out2
7 6 5
MSB

Uniform Sector
Standard and Quad Serial FlashGD55B01GE

Figure 89 Read Serial Flash Discoverable Parameter command Sequence Diagram (QPI)

CS#

0

1

2

3

4

6

5

7

15

8

16

17

SCLK

IO[3:0]dummy

CommandAddress

5AH

Addr. Addr. Addr. Addr. Addr. Addr.

Byte 1

Byte 2

SFDP out

SFDP

Table 15 Signature and Parameter Identification Data Values (Please contact GigaDevice for details)

http://www.elm-tech.com

56

Rev.1.3

Uniform Sector
Standard and Quad Serial Flash
9

GD55B01GE

ELECTRICAL CHARACTERISTICS

9.1 Power-On Timing
Figure 90 Power-on Timing
Vcc(max)
Chip Selection is not allowed

Vcc(min)
Device is fully
accessible

tVSL

VWI

Time

Table 16 Power-Up Timing and Write Inhibit Threshold
SymbolParameter

Min.

tVSL

VCC (min.) to device operation

1.8

VWI

Write Inhibit Voltage

1.5

Max.

Unit
ms
V

2.5

9.2 Initial Delivery StateThe device is delivered with the memory array erased: all bits are set to 1 (each Byte contains FFH). The Status Registercontains 00H (all Status Register bits are 0).

9.3

Absolute Maximum Ratings
Parameter

Value

Unit

Ambient Operating Temperature (TA)

-40 to 85℃-40 to 105-40 to 125
Storage Temperature-65 to 150℃

Transient Input/Output Voltage (note: overshoot)-2.0 to VCC+2.0

V

Applied Input/Output Voltage-0.6 to VCC+0.4

V-0.6 to 4.2

V

VCC

http://www.elm-tech.com

57

Rev.1.3

Uniform Sector
Standard and Quad Serial FlashGD55B01GE

Figure 91. Input Test Waveform and Measurement Level
Maximum Negative Overshoot Waveform
20ns

Maximum Positive Overshoot Waveform

20ns

20ns

Vss
Vcc + 2.0V

Vss-2.0V
Vcc

20ns

20ns

20ns

9.4 Capacitance Measurement Conditions
SymbolCIN/COUT

Parameter

Min

Typ.

Input/Output Capacitance(IO pins: IO[3:0])

Max

Unit

20

pF

Conditions
VIN=0V
VOUT=0V

CIN

Input Capacitance (except IO pins)

16

pF

VIN=0V

COUT

Output Capacitance (except IO pins)

16

pF

VOUT=0V

CL

Load Capacitance

30

pF

Input Rise And Fall time

5ns

Input Pulse Voltage

0.1VCC to 0.8VCC

V

Input Timing Reference Voltage

0.3VCC to 0.7VCC

V

Output Timing Reference Voltage

0.5VCCV

Figure 92. Absolute Maximum Ratings Diagram

0.8VCC

Input timing reference level

0.1VCC

0.7VCC
0.3VCC

Output timing reference level
AC Measurement Level

Note: Input pulse rise and fall time are<5ns

http://www.elm-tech.com

58

Rev.1.3

0.5VCCUniform Sector
Standard and Quad Serial FlashGD55B01GE

9.5 DC Characteristics(TA = -40℃~85℃, VCC=2.7~3.6V)
SymbolParameter

Test Condition

Min.

Typ.

Max.

Unit.

ILI

Input Leakage Current

±4

μA

ILO

Output Leakage Current

±4

μA

ICC1

Standby Current

32

120

μA

ICC2

Deep Power-Down Current

4

50

μA

30

50

mA

38

60

mA

CS#=VCC,
VIN=VCC or VSS
CS#=VCC,
VIN=VCC or VSS
CLK=0.1VCC / 0.9VCC
at 133MHz,

ICC3Operating Current (Read)

Q=Open(x4 I/O)
CLK=0.1VCC / 0.9VCC
at 90MHz DTR,
Q=Open(x4 I/O)

ICC4Operating Current (PP)

CS#=VCC

18

30

mA

ICC5

Operating Current (WRSR)

CS#=VCC

30

50

mA

ICC6

Operating Current (SE)

CS#=VCC

18

30

mA

ICC7

Operating Current (BE)

CS#=VCC

18

30

mA

ICC8

Operating Current (CE)

CS#=VCC

30

50

mA

VIL

Input Low Voltage-0.5

0.3VCCV

VIH

Input High Voltage

0.7VCC

VCC+0.4

V

VOL

Output Low Voltage

IOL = 100μA

0.2

V

VOH

Output High Voltage

IOH = -100μA

VCC-0.2

Note:
1. Typical value at TA = 25℃, VCC = 3.3V.
2. Value guaranteed by design and/or characterization, not 100% tested in production.

http://www.elm-tech.com

59

Rev.1.3

VUniform Sector
Standard and Quad Serial FlashGD55B01GE(TA = -40℃~105℃, VCC=2.7~3.6V)
SymbolParameter

Test Condition

Min.

Typ.

Max.

Unit.

ILI

Input Leakage Current

±4

μA

ILO

Output Leakage Current

±4

μA

ICC1

Standby Current

32

200

μA

ICC2

Deep Power-Down Current

4

100

μA

30

55

mA

38

70

mA

CS#=VCC,
VIN=VCC or VSS
CS#=VCC,
VIN=VCC or VSS
CLK=0.1VCC / 0.9VCC
at 133MHz,

ICC3Operating Current (Read)

Q=Open(x4 I/O)
CLK=0.1VCC / 0.9VCC
at 90MHz DTR,
Q=Open(x4 I/O)

ICC4Operating Current (PP)

CS#=VCC

18

35

mA

ICC5

Operating Current (WRSR)

CS#=VCC

30

60

mA

ICC6

Operating Current (SE)

CS#=VCC

18

35

mA

ICC7

Operating Current (BE)

CS#=VCC

18

35

mA

ICC8

Operating Current (CE)

CS#=VCC

30

60

mA

VIL

Input Low Voltage-0.5

0.3VCCV

VIH

Input High Voltage

0.7VCC

VCC+0.4

V

VOL

Output Low Voltage

IOL = 100μA

0.2

V

VOH

Output High Voltage

IOH = -100μA

VCC-0.2

Note:
1. Typical value at TA = 25℃, VCC = 3.3V.
2. Value guaranteed by design and/or characterization, not 100% tested in production.

http://www.elm-tech.com

60

Rev.1.3

VUniform Sector
Standard and Quad Serial FlashGD55B01GE(TA = -40℃~125℃, VCC=2.7~3.6V)
SymbolParameter

Test Condition

Min.

Typ.

Max.

Unit.

ILI

Input Leakage Current

±6

μA

ILO

Output Leakage Current

±6

μA

ICC1

Standby Current

32

400

μA

ICC2

Deep Power-Down Current

4

200

μA

30

60

mA

35

75

mA

CS#=VCC,
VIN=VCC or VSS
CS#=VCC,
VIN=VCC or VSS
CLK=0.1VCC / 0.9VCC
at 133MHz,

ICC3Operating Current (Read)

Q=Open(x4 I/O)
CLK=0.1VCC / 0.9VCC
at 84MHz DTR,
Q=Open(x4 I/O)

ICC4Operating Current (PP)

CS#=VCC

18

40

mA

ICC5

Operating Current (WRSR)

CS#=VCC

30

70

mA

ICC6

Operating Current (SE)

CS#=VCC

18

40

mA

ICC7

Operating Current (BE)

CS#=VCC

18

40

mA

ICC8

Operating Current (CE)

CS#=VCC

30

70

mA

VIL

Input Low Voltage-0.5

0.3VCCV

VIH

Input High Voltage

0.7VCC

VCC+0.4

V

VOL

Output Low Voltage

IOL = 100μA

0.2

V

VOH

Output High Voltage

IOH = -100μA

VCC-0.2

Note:
1. Typical value at TA = 25℃, VCC = 3.3V.
2. Value guaranteed by design and/or characterization, not 100% tested in production.

http://www.elm-tech.com

61

Rev.1.3

VUniform Sector
Standard and Quad Serial Flash
9.6

GD55B01GE

AC Characteristics(TA = -40℃~85℃, VCC=2.7~3.6V)
SymbolfC1
fC2

Parameter

Min.

Serial Clock Frequency for all instructions except
03H, 13H, EEH, EDH
Serial Clock Frequency for DTR Quad I/O Fast Read
(EEH, EDH) instructions

fR

Serial Clock Frequency For: Read (03H, 13H)

tCLH

Serial Clock High Time

tCLL

Serial Clock Low Time(fSCLK≤50MHz)tCHCL

Serial Clock Rise/Fall Time (Slew Rate)

Max.

Unit.

133

MHz

90

MHz

60

MHz

45%

ns

(1/fcmax)
45%

ns(1/fcmax)

Serial Clock Rise/Fall Time (Slew Rate)
tCLCH

Typ.

(fSCLK>50MHz)

0.3

V/ns

0.6

V/ns

tSLCH

CS# Active Setup Time

4

ns

tCHSH

CS# Active Hold Time

4

ns

tCLSH

CS# Active Hold Time (DTR)

4

ns

tSHCH

CS# Not Active Setup Time

5

ns

tCHSL

CS# Not Active Hold Time

5ns

CS# High Time (Read)20

ns

CS# High Time (Write)

40

ns

tSHSL
tSHQZ
tCLQX
tCHQX
tDVCH
tDVCH
tDVCL
tCHDX
tCHDX
tCLDX

Output Disable Time8ns

Output Hold Time

1.8

ns

Data In Setup Time (STR)

2

ns

Data In Setup Time (DTR)

1ns

Data In Hold Time (STR)

2

ns

Data In Hold Time (DTR)

1ns

Clock Low To Output Valid (VCC=2.7~3.0V,
loading=30pF)
Clock Low To Output Valid (VCC=2.7~3.0V,
tCLQV

loading=10pF)

tCHQV

Clock Low To Output Valid (VCC=3.0~3.6V,
loading=30pF, CR<3> = xxxx xx00b)
Clock Low To Output Valid (VCC=3.0~3.6V,
loading=10pF,CR<3> = xxxx xx00b)

8

ns

7

ns

7

ns

6

ns

tWHSL

Write Protect Setup Time Before CS# Low

20

ns

tSHWL

Write Protect Hold Time After CS# High

100

ns

http://www.elm-tech.com

62

Rev.1.3

Uniform Sector
Standard and Quad Serial Flash
tDP
tRES1

CS# High To Deep Power-Down Mode
CS# High To Standby Mode Without Electronic
Signature ReadtSUS

CS# High To Next Command After SuspendtRS

Latency Between Resume And Next SuspendtRST

GD55B01GE
3

μs

30

μs

20

μs

100

μs

CS# High To Next Command After Reset (From Read

40

μs

25

ms

5

30

ms

or From Program)CS# High To Next Command After Reset (From ErasetRST_Eor From Write Status/Non-volatile Configuration
Register)tW

Write Status/Non-Volatile Configuration Register
Cycle TimetBP1

Byte Program Time (First Byte)

30

50

μs

tBP2

Additional Byte Program Time (After First Byte)

2.5

12

μs

tPP

Page Programming Time

0.15

1.0

ms

tSE

Sector Erase Time

30

400

ms

tBE1

Block Erase Time (32K Bytes)

0.15

1.5

s

tBE2

Block Erase Time (64K Bytes)

0.22

2

s

tCE

Chip Erase Time (GD55B01GE)

150

300

s

Note:
1. Typical value at TA = 25℃.
2. Value guaranteed by design and/or characterization, not 100% tested in production.
3. Time of CS# High To Next Command After Reset from 01H/B1H command would be tW + tRST

http://www.elm-tech.com

63

Rev.1.3

Uniform Sector
Standard and Quad Serial FlashGD55B01GE(TA = -40℃~105℃, VCC=2.7~3.6V)
SymbolfC1
fC2

Parameter

Min.

Serial Clock Frequency for all instructions except
03H, 13H, EEH, EDH
Serial Clock Frequency for DTR Quad I/O Fast Read
(EEH, EDH) instructions

fR

Serial Clock Frequency For: Read (03H, 13H)

tCLH

Serial Clock High Time

tCLL

Serial Clock Low Time(fSCLK≤50MHz)tCHCL

Serial Clock Rise/Fall Time (Slew Rate)

Max.

Unit.

133

MHz

90

MHz

60

MHz

45%

ns

(1/fcmax)
45%

ns(1/fcmax)

Serial Clock Rise/Fall Time (Slew Rate)
tCLCH

Typ.

(fSCLK>50MHz)

0.3

V/ns

0.6

V/ns

tSLCH

CS# Active Setup Time

4

ns

tCHSH

CS# Active Hold Time

4

ns

tCLSH

CS# Active Hold Time (DTR)

4

ns

tSHCH

CS# Not Active Setup Time

5

ns

tCHSL

CS# Not Active Hold Time

5ns

CS# High Time (Read)20

ns

CS# High Time (Write)

40

ns

tSHSL
tSHQZ
tCLQX
tCHQX
tDVCH
tDVCH
tDVCL
tCHDX
tCHDX
tCLDX

Output Disable Time8ns

Output Hold Time

1.8

ns

Data In Setup Time (STR)

2

ns

Data In Setup Time (DTR)

1ns

Data In Hold Time (STR)

2

ns

Data In Hold Time (DTR)

1ns

Clock Low To Output Valid (VCC=2.7~3.0V,
loading=30pF)
Clock Low To Output Valid (VCC=2.7~3.0V,
tCLQV

loading=10pF)

tCHQV

Clock Low To Output Valid (VCC=3.0~3.6V,
loading=30pF, CR<3> = xxxx xx00b)
Clock Low To Output Valid (VCC=3.0~3.6V,
loading=10pF,CR<3> = xxxx xx00b)

8

ns

7

ns

7

ns

6

ns

tWHSL

Write Protect Setup Time Before CS# Low

20

ns

tSHWL

Write Protect Hold Time After CS# High

100

ns

tDP

CS# High To Deep Power-Down Mode

http://www.elm-tech.com

3

64

Rev.1.3μsUniform Sector
Standard and Quad Serial FlashtRES1

CS# High To Standby Mode Without Electronic
Signature ReadtSUS

CS# High To Next Command After SuspendtRS

Latency Between Resume And Next SuspendtRST

GD55B01GE
30

μs

20

μs

100

μs

CS# High To Next Command After Reset (From Read

40

μs

25

ms

5

40

ms

or From Program)CS# High To Next Command After Reset (From ErasetRST_Eor From Write Status/Non-volatile Configuration
Register)tW

Write Status/Non-Volatile Configuration Register
Cycle TimetBP1

Byte Program Time (First Byte)

30

140

μs

tBP2

Additional Byte Program Time (After First Byte)

2.5

25

μs

tPP

Page Programming Time

0.15

2.0

ms

tSE

Sector Erase Time

30

600

ms

tBE1

Block Erase Time (32K Bytes)

0.15

1.6

s

tBE2

Block Erase Time (64K Bytes)

0.22

3

s

tCE

Chip Erase Time (GD55B01GE)

150

450

s

Note:
1. Typical value at TA = 25℃.
2. Value guaranteed by design and/or characterization, not 100% tested in production.
3. Time of CS# High To Next Command After Reset from 01H/B1H command would be tW + tRST

http://www.elm-tech.com

65

Rev.1.3

Uniform Sector
Standard and Quad Serial FlashGD55B01GE(TA = -40℃~125℃, VCC=2.7~3.6V)
SymbolfC1
fC2

Parameter

Min.

Serial Clock Frequency for all instructions except
03H, 13H, EEH, EDH
Serial Clock Frequency for DTR Quad I/O Fast Read
(EEH, EDH) instructions

fR

Serial Clock Frequency For: Read (03H, 13H)

tCLH

Serial Clock High Time

tCLL

Serial Clock Low Time(fSCLK≤50MHz)tCHCL

Serial Clock Rise/Fall Time (Slew Rate)

Max.

Unit.

133

MHz

84

MHz

60

MHz

45%

ns

(1/fcmax)
45%

ns(1/fcmax)

Serial Clock Rise/Fall Time (Slew Rate)
tCLCH

Typ.

(fSCLK>50MHz)

0.3

V/ns

0.6

V/ns

tSLCH

CS# Active Setup Time

4

ns

tCHSH

CS# Active Hold Time

4

ns

tCLSH

CS# Active Hold Time (DTR)

4

ns

tSHCH

CS# Not Active Setup Time

5

ns

tCHSL

CS# Not Active Hold Time

5ns

CS# High Time (Read)20

ns

CS# High Time (Write)

40

ns

tSHSL
tSHQZ
tCLQX
tCHQX
tDVCH
tDVCH
tDVCL
tCHDX
tCHDX
tCLDX

Output Disable Time8ns

Output Hold Time

1.8

ns

Data In Setup Time (STR)

2

ns

Data In Setup Time (DTR)

1ns

Data In Hold Time (STR)

2

ns

Data In Hold Time (DTR)

1ns

Clock Low To Output Valid (VCC=2.7~3.0V,
loading=30pF)
Clock Low To Output Valid (VCC=2.7~3.0V,
tCLQV

loading=10pF)

tCHQV

Clock Low To Output Valid (VCC=3.0~3.6V,
loading=30pF, CR<3> = xxxx xx00b)
Clock Low To Output Valid (VCC=3.0~3.6V,
loading=10pF,CR<3> = xxxx xx00b)

8

ns

7

ns

7

ns

6

ns

tWHSL

Write Protect Setup Time Before CS# Low

20

ns

tSHWL

Write Protect Hold Time After CS# High

100

ns

tDP

CS# High To Deep Power-Down Mode

http://www.elm-tech.com

3

66

Rev.1.3μsUniform Sector
Standard and Quad Serial FlashtRES1

CS# High To Standby Mode Without Electronic
Signature ReadtSUS

CS# High To Next Command After SuspendtRS

Latency Between Resume And Next SuspendtRST

GD55B01GE
30

μs

20

μs

100

μs

CS# High To Next Command After Reset (From Read

40

μs

25

ms

5

40

ms

or From Program)CS# High To Next Command After Reset (From ErasetRST_Eor From Write Status/Non-volatile Configuration
Register)tW

Write Status/Non-Volatile Configuration Register
Cycle TimetBP1

Byte Program Time (First Byte)

30

140

μs

tBP2

Additional Byte Program Time (After First Byte)

2.5

25

μs

tPP

Page Programming Time

0.15

2.0

ms

tSE

Sector Erase Time

30

800

ms

tBE1

Block Erase Time (32K Bytes)

0.15

1.6

s

tBE2

Block Erase Time (64K Bytes)

0.22

3

s

tCE

Chip Erase Time (GD55B01GE)

150

500

s

Note:
1. Typical value at TA = 25℃.
2. Value guaranteed by design and/or characterization, not 100% tested in production.
3. Time of CS# High To Next Command After Reset from 01H/B1H command would be tW + tRST

Figure 93. Serial Input Timing

tSHSL

CS#
tCHSL

SCLK

tSLCH

tDVCH

MSB

SO

High-Z

tSHCH
tCHCL

tCLCH

tCHDX

SI

http://www.elm-tech.com

tCHSH

LSB

67

Rev.1.3

Uniform Sector
Standard and Quad Serial FlashGD55B01GE

Figure 94. Output Timing

CS#

tCLH

SCLK
tCLQV

tCLQV

tCLQX

tSHQZ

tCLL

tCLQX

SO

LSB

SI
Least significant address bit (LIB) in

Figure 95. Serial Input Timing (DTR)

tSHSL
CS#

tSLCH

tCHSL

tCLSH

tSHCH

SCLK

tDVCL
tDVCH

tCLDX

IO

tCHCL

tCLCH

MSB

LSB

tCHDX
Figure 96. Serial Output Timing (DTR)

CS#
tCLH

tCLQV

SCLK

IO

tCLL

tCHQV

tCLQX

tSHQZ
LSB

MSB
tCHQX

Figure 97. Resume to Suspend Timing DiagramCS#

http://www.elm-tech.com

ResumeCommandtRS

68

Rev.1.3

SuspendCommandUniform Sector
Standard and Quad Serial FlashGD55B01GE

Figure 98. WP# Timing

CS#
tWHSL

tSHWL

WP#

SCLK
IO
Input

Write Status Register allowed

Write Status Register NOT allowed

Figure 99. RESET Timing

tRB

CS#

RESET#
tRLRH

tRHSL

Table 17. Reset Timing
SymbolParameter

Min.

Typ.

Max.

Unit.

tRLRH

Reset Pulse Width

1

μs

tRHSL

Reset Hold time before next Operation

50

ns

tRB

Reset Recovery Time (From Read or Program)40μs

Reset Recovery Time (From Erase)

25

ms

Note:
1. Time of Reset Recovery Time from 01H/B1H command would be tW + tRB
2. The device need tRB (max) at most to get ready for all commands after RESET# low.

http://www.elm-tech.com

69

Rev.1.3

Uniform Sector
Standard and Quad Serial FlashGD55B01GE

10 ORDERING INFORMATIONGD XX XX XX X X X X X
Packing
T or no mark: Tube
Y: Tray
R: Tape and Reel
Green Code
G: Pb Free + Halogen Free Green Package
S: Pb Free + Halogen Free Green Package + SRP1 Function
R: Pb Free + Halogen Free Green Package + RESET# Pin
K: Pb Free + Halogen Free Green Package + RESET# Pin +SRP1 Function
Temperature Range
I: Industrial (-40℃ to +85℃)
J: Industrial+ (-40℃ to +105℃)
E: Industrial+ (-40℃ to +125℃)
F: Industrial+ (-40℃ to +85℃)**
3: Automotive (-40℃ to +85℃)*
2: Automotive (-40℃ to +105℃)*
A: Automotive (-40℃ to +125℃)*
Package Type
F: SOP16 300mil
Y: WSON8 (8x6mm)
B: TFBGA-24ball (5x5 Ball Array)
Generation
E: E Version
Density
01G: 1G bit
Series
B: 3V, 4KB Uniform Sector, default x4I/O
Product Family
55: SPI NOR Flash*Please contact GigaDevice sales for automotive products.
**F grade has implemented additional test flows to ensure higher product quality than I grade.

http://www.elm-tech.com

70

Rev.1.3

Uniform Sector
Standard and Quad Serial FlashGD55B01GE

10.1 Valid Part Numbers
Please contact GigaDevice regional sales for the latest product selection and available form factors.
Temperature Range I: Industrial (-40℃ to +85℃)

Product Number

Clock

GD55B01GEFIRGD55B01GEFIKGD55B01GEYIGGD55B01GEYIS
GD55B01GEBIR

133MHz133MHz133MHz133MHz133MHzGD55B01GEBIK

133MHzDensity

Package Type

1Gbit

SOP16 300mil

1Gbit

WSON8 (8x6mm)

1Gbit

TFBGA-24ball (5x5 Ball Array)

Packing
Options
T/Y/R
T/Y/R
Y/R
Y/R
Y/R
Y/R

Temperature Range J: Industrial+ (-40℃ to +105℃)

Product Number

Clock

GD55B01GEFJRGD55B01GEFJKGD55B01GEYJG
GD55B01GEYJSGD55B01GEBJR

133MHz133MHz133MHz133MHz133MHzGD55B01GEBJK133MHzDensity

Package Type

1Gbit

SOP16 300mil

1Gbit

WSON8 (8x6mm)

1Gbit

TFBGA-24ball (5x5 Ball Array)

Packing
Options
T/Y/R
T/Y/R
Y/R
Y/R
Y/R
Y/R

Temperature Range E: Industrial+ (-40℃ to +125℃)

Product Number

Clock

GD55B01GEFERGD55B01GEFEKGD55B01GEYEG
GD55B01GEYESGD55B01GEBER

133MHz133MHz133MHz133MHz133MHzGD55B01GEBEK

133MHzhttp://www.elm-tech.com

Density

Package Type

1Gbit

SOP16 300mil

1Gbit

WSON8 (8x6mm)

1Gbit

TFBGA-24ball (5x5 Ball Array)

71

Rev.1.3

Packing
Options
T/Y/R
T/Y/R
Y/R
Y/R
Y/R
Y/R

Uniform Sector
Standard and Quad Serial FlashGD55B01GE

Temperature Range F: Industrial+ (-40℃ to +85℃)

Product Number

Clock

GD55B01GEFFRGD55B01GEFFKGD55B01GEYFG
GD55B01GEYFS
GD55B01GEBFR

133MHz133MHz133MHz133MHz133MHzGD55B01GEBFK

133MHzhttp://www.elm-tech.com

Density

Package Type

1Gbit

SOP16 300mil

1Gbit

WSON8 (8x6mm)

1Gbit

TFBGA-24ball (5x5 Ball Array)

72

Rev.1.3

Packing
Options
T/Y/R
T/Y/R
Y/R
Y/R
Y/R
Y/R

Uniform Sector
Standard and Quad Serial FlashGD55B01GE

11 PACKAGE INFORMATION
11.1 Package SOP16 300MIL
D
16

9

E1

E

h
1

“A”

L

h

8

L1

θ

b
0.1 C
SEATING PLANEbBase Metal

c

A2 A

Detail “A”

A1e

Dimensions
Symbol

A

A1

A2

b

c

D

E

E1

Min

-

0.10

2.05

0.31

0.10

10.20

10.10

7.40

Nom

-

0.20

-

0.41

0.25

10.30

10.30

7.50

Max

2.65

0.30

2.55

0.51

0.33

10.40

10.50

7.60

Unit
mm

Note:
1. Both the package length and width do not include the mold flash.

http://www.elm-tech.com

73

Rev.1.3

e

L

L1

0.40
1.27

1.27

1.40

h

θ

0.25

0

-

-

0.75

8

Uniform Sector
Standard and Quad Serial FlashGD55B01GE

11.2 Package WSON8 (8x6mm)c

D
PIN 1#

E

A1
A
Side View

Top View

D2

4

5

E2

e
b

1

8

L

Bottom View
Dimensions
Symbol

A

A1

c

b

D

D2

E

E2

Min

0.70

0.00

0.180

0.35

7.90

3.30

5.90

4.20

Nom

0.75

0.02

0.203

0.40

8.00

3.40

6.00

4.30

Max

0.80

0.05

0.250

0.45

8.10

3.50

6.10

4.40

Unit
mm

e

L
0.45

1.27

0.50
0.55

Note:
1. Both the package length and width do not include the mold flash.
2. The exposed metal pad area on the bottom of the package is floating.
3. Coplanarity ≤0.08mm. Package edge tolerance≤0.10mm.
4. The lead shape may be of little difference according to different package lead frames. These leadshapes are compatible with each other.

http://www.elm-tech.com

74

Rev.1.3

Uniform Sector
Standard and Quad Serial FlashGD55B01GE

11.3 Package TFBGA-24BALL (5x5 ball array)

1

2

3

4

5

5

4

3

2

1

A

A

B

B

b

C

D

C

D1

D

D

e

E

E
e

E

E1

A2

A

A1

Dimensions
Symbol

A

A1

A2

b

E

Min

-

0.25

0.75

0.35

5.90

Nom

-

0.30

0.80

0.40

6.00

Max

1.20

0.35

0.85

0.45

6.10

Unit
mm

E1

75

Rev.1.3

D1

e

4.00

1.00

7.90
4.00

Note: Both the package length and width do not include the mold flash.

http://www.elm-tech.com

D

8.00
8.10

Uniform Sector
Standard and Quad Serial FlashGD55B01GE

12 REVISION HISTORY
Version No
1.0

1.1

Description
Initial Release

Page

Date

All

2020-9-28

Modify VIL from 0.2VCC to 0.3VCC

P60, 61, 62

Modify tCHSH/tCLSH from 3ns to 4ns

P63, 65, 67

Modify tSHCH from 3ns to 5ns

P63, 65, 67

Modify tRST_E from 12ms to 25ms

P64, 66, 68

Update Description of RESET#

2020-12-15

P5-P7

Modify Quad Output Fast Read(6BH,6CH) Max Frequency from
1.2

1.3

166Mhz to 133Mhz

P4, P59-67

Modify Supported Clock Frequencies

P21

Update ILI / ILO of 125℃ from ±4μA to ±6μA

P61

Add Note of WP# Pin

P6-7

Modify Typo of DLP

P20-21

Modify Description of AC parameter tCLCH/tCHCL

P62, P64, P66

Update Ordering Information

P70-P72

Add Coplanarity of SOP16

P73

http://www.elm-tech.com

76

Rev.1.3

2021-5-10

2022-1-10

Uniform Sector
Standard and Quad Serial FlashGD55B01GE

Important NoticeThis document is the property of GigaDevice Semiconductor (Beijing) Inc. and its subsidiaries (the "Company"). This
document, including any product of the Company described in this document (the “Product”), is owned by the Company
according to the laws of the People’s Republic of China and other applicable laws. The Company reserves all rights undersuch laws and no Intellectual Property Rights are transferred (either wholly or partially) or licensed (either expressly or
impliedly). The names and brands of third party referred thereto (if any) are the property of their respective owner andreferred to for identification purposes only.
The Company does not assume any warranty or condition, express or implied, with regard to this document or any
Product, including, but not limited to, the implied warranties of merchantability, fitness for any particular purpose, noninfringement, or any warranty arising out of the application or use of any Product described in this document. Any information
provided in this document is provided only for reference purposes. It is the responsibility of the user of this document toproperly design, program, and test the functionality and safety of any application and any product produced. Except forcustomized products which has been expressly identified in the applicable agreement, the Products are designed,
developed, and/or manufactured for ordinary business, industrial, personal, and/or household applications only. The
Products are not designed or intended for use in, and no warranty is made respect to, any applications designed or intended
for the operation of weaponry, nuclear equipment, atomic energy control instruments, combustion control instruments,
airplane or spaceship instruments, traffic signal instruments, life-support devices or systems, other medical devices orsystems (including resuscitation equipment and surgical implants etc.), pollution control or hazardous substancesmanagement, or other uses where failure to perform can reasonably be expected to result in personal injury, death, property
or environmental damage ("Unintended Uses"). Customers shall take any and all actions to ensure using and selling the
Products in accordance with the applicable laws and regulations. The Company is not liable, in whole or in part, andcustomers shall and hereby do release the Company as well as it’s suppliers and/or distributors from any claim, damage,or other liability arising from or related to all Unintended Uses of the Products. Customers shall indemnify and hold theCompany as well as it’s suppliers and/or distributors harmless from and against all claims, costs, damages, and otherliabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of the Products.
Customers shall discard the device according to the local environmental law.
Information in this document is provided solely in connection with the Products. The Company reserves theright to make changes, corrections, modifications or improvements to this document and the Products andservices described herein at any time, without notice. And the company shall have no responsibility whatsoever
for conflicts or incompatibilities arising from future changes to them.

http://www.elm-tech.com

77

Rev.1.3