Recess Etching Process for AlGaN/GaN-HFET Devices Using In-Situ Monitoring
T. Nishimiya, H. Ogiya, M. Hiramoto, S. Motoyama and P. Wood
Research and Development Department, Samco Inc.,
36 Waraya-cho, Takeda, Fushimi-ku, Kyoto 612-8443, Japan075-621-7841, motoyama@samco.co.jp
Keywords: AlGaN, GaN, Power Devices, ICP, Etching
Abstract
SAMCO has developed a dry etching process for
AlGaN/GaN-HFET power devices with precise control of theetching film depth. AlGaN/GaN-HFET devices are “normallyon” and require a circuit to turn off the device. To avoid theturning-off of devices, “normally off” devices are preferred forpower device applications. One method of making
AlGaN/GaN-HFET devices “normally off” is to eliminate the2D electron gas channel under the gate electrode. This can beachieved by recess etching (for example, etching a 25 nm
AlGaN layer with less than 5 nm of the AlGaN film remaining).
Precise control of the remaining AlGaN layer thickness is themost crucial factor because the remaining AlGaN layer depthdetermines Vg-Id characteristics of AlGaN/GaN-HEFT devices(when Vd is constant).
Remaining AlGaN layer thickness was controlled by theetching time while carrying out very slow etching. However,
the recess etching requires thickness control on the order of 1
nm and this timed etching method does not allow that. Since
the AlGaN etch rate can change due to byproducts in thereaction chamber, the timed etching approach is clearly noteffective. This paper introduces SAMCO’s development of anew, precise method for control of the remaining AlGaN layer
thickness during recess etching. SAMCO’s new method
employs an interferometric film thickness measurement
system and in-situ monitoring of the remaining AlGaN
thickness.

INTRODUCTION
Next generation power devices using Gallium Nitride(GaN) and Silicon Carbide (SiC) have excellent power
consumption and miniaturization characteristics, andresearch efforts have been aimed at introducing the devices
into market. The key processes for realizing power devices
are: (1) for GaN power devices, gate etching to convert theAlGaN/GaN-HFET devices into normally-off operation,and passivation layer formation to suppress current collapse,and (2) for SiC power devices, trench formation etching, viahole formation etching, and gate insulation film formation.
SAMCO has developed PECVD and ICP-RIE systems toachieve the requirements of the key processes mentioned

above. In this report, highly precise recess etching
technology for GaN power devices is described.
Table I, summarizes the important semiconductormaterial characteristics [1] of Si, GaAs, GaN and 4H-SiC(for which power device commercialization has alreadystarted), β-Ga2O3 (which has recently come into thespotlight), and diamond (which is still in the research stage
but shows promise). The most important characteristics forpower device applications are wide band-gap, highbreakdown voltage, and high thermal conductivity. Also,
high electron mobility, high hole mobility, high saturation
velocity, and low dielectric constant are important for highspeed
responsecharacteristics.
Diamondshows
extraordinary
performancebuthasfundamental
disadvantages, such as the difficulties of growing large
single crystal substrates and in P-N doping control. β-Ga2O3
has a wide band gap, high breakdown voltage, and n-typecontrol is possible by doping with Sn. Hetero-junctions withother oxide semiconductors and MOS-FET fabrication isalso possible using β-Ga2O3. However, it has thedisadvantage of having an extremely low thermal
conductivity.
4H-SiC is a power device material whose power device
commercialization has already started. High quality
epitaxial growth is possible because 4H-SiC substrates areavailable in the market, and Schottky Barrier Diodes(SBDs) and Double-diffused Metal–Oxide–Semiconductor
Field Effect Transistors (DMOS-FETs) have been alreadycommercialized. Furthermore, there have been research anddevelopment activities on MOS-FETs with vertical device
structure, Insulated Gate Bipolar Transistor (IGBT), andJunction FET (SIT = Static Induction Transistor). GaN is
anticipated to show better performance than 4H-SiC. GaN
substrates are grown using a Na flux method but are noteasy to obtain. Therefore epitaxial growth is achieved using
buffer layers on sapphire or Si substrates to mitigate thedifference in lattice constants. GaN on sapphire has been
applied to AlGaN/GaN-HFET (Hetero-structure FET) andGaN-MOSFET devices with planar structure. Both powerdevice and high-speed device applications are possible.

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GaN-based devices are also promising substitutes for
AlGaAs/GaAs-HFET devices.
AlGaN/GaN-HFET devices are fabricated with undoped
GaN and undoped AlGaN epitaxially grown on Si orsapphire substrates. Source, Drain, and Gate electrodes areformed on the layers. The ratio of Al in the AlGaN layer is~0.25 and AlGaN thickness is approximately 25 nm.
Through the Piezo effect, highly concentrated 2DEG (2Dimensional Electron Gas) is formed at the AlGaN/GaN
interface, resulting in the device becoming “Normally ON”.
However “Normally OFF” is more preferable for powerdevices. In order to form “Normally OFF” devices and todecrease the ON resistivity, three methods are used: (1)make the device a MOS-FET, (2) use a p-GaN GIT (GateInjection Transistor), or (3) use a recess structure bythinning the AlGaN layer to less than 5 nm. These methods
will all eliminate 2DEG at the gate electrode. Gate
formation is the most important technology in thefabrication process of AlGaN/GaN-HFET devices from theviewpoint of Gate voltage (Vg) – Drain current (Id)characteristics (Drain voltage (Vd) = constant).
EXPERIMENTAL DETAILSIn this research, etching of AlGaN and GaN, anddeposition of SiO2 were carried out on SAMCO
RIE-200iPC and PD-220LC systems, respectively. Thesesystems are displayed in Images 1 and 2 below.
Research on “Normally Off” devices was carried out withthree types of gate structures as follows;
1) MOS-FET2) GIT (Gate Injection Transistor)
3) Recess etchingFor the MOS-FET gate structure, AlGaN was etched to theGaN layer, the SiO2 gate oxide was deposited, and thedevice characteristics were studied. For the GIT, highselectivity etching of GaN/AlGaN was carried out. For therecess etching, highly precise etching of AlGaN was carried390

out to control its thickness using in-situ monitoring.

Image 1 – RIE-200iPC

Image 2 – PD-220LC

RESULTS AND DISCUSSION
1) AlGaN/GaN MOS-FET. Figure 1 illustrates theMOS-FET structure. The AlGaN layer at the gate wasetched down to the GaN interface using an ICP-RIE process.
In order to obtain smooth surfaces that would suppress
plasma damage, slow etching was carried out at the rate ofabout 1 nm/min. Surface smoothness (RMS) was essentiallyconstant before (0.4 nm) and after (0.41 nm) the etching [2].
A 100 nm thick gate oxide was formed using a plasma
enhanced CVD process and a SiH4-N2O process gas
mixture. Following deposition of the gate oxide it wasannealed in a N2 environment at 1000°C. Highly
concentrated 2DEG is generated at the AlGaN/GaNinterface. Since the Source and Drain are formed on theAlGaN layer. As a result, Drain voltage-current
characteristics showed saturation, and control with Gatevoltage was possible. Additionally, channel mobility wasapprox. 150 cm2/V・s, and an excellent interface condition
between Gate oxide and GaN of 1011/cm2·eV was obtained[3]. Mobility was about 10% HFET mobility. From these

CS MANTECH Conference, May 19th - 22nd, 2014, Denver, Colorado, USAresults, it can be concluded that plasma damage wassuppressed.

The results of interferometry monitoring are shown in Fig.
7 (time vs. reflection intensity of 364 nm light).

Gate

Gate SiO2
AlGaN

2DEGGp-GaN

DAlGaNnon-doped GaN

2DEGGaN

Sapphire Substrate2) GIT AlGaN/GaN-HFET. Fig. 2 illustrates the GIT
AlGaN/GaN-HFET structure [4], [5]. The GaN layer,
AlGaN layer, and p-GaN layers were epitaxially grown on
Si or sapphire substrates. By growing p-GaN at the Gate, adepletion layer is formed and 2DEG can be eliminated.
Etching with high AlGaN/GaN selectivity so that theICP-RIE etch rate decreases significantly at the AlGaNlayer is required to achieve this structure. Fig. 3 illustrates
the selectivity of GaN/AlGaN (Blue) and GaN etching rate(Green) when the sample was etched using Cl2/Ar/O2 withO2 flow as a parameter. With 2 SCCM of O2 flow, a GaN
etch rate of 70 nm/min and GaN/AlGaN selectivity of 55
was achieved. Through further process development, anoptimal GaN/AlGaN selectivity of 100 was obtained (redsymbol). Additionally, highly selective etching is requiredto obtain excellent uniformity over the wafer.
3) Recessed Gate AlGaN/GaN-HFET. In Fig. 4, an
AlGaN/GaN-HFET device with recess gate structure isshown. Here the device with a “Normally OFF”
characteristic is the target, and suppressing plasma damage
as well as controlling the residual AlGaN thickness to under
5 nm at the Gate is required to achieve low ON-resistance(decrease resistivity between Source – Gate and Drain –Gate). Furthermore, uniform etching across the wafer isrequired so that the device characteristic distribution suchas the Gate voltage/Drain current (with constant Drainvoltage) stays within the acceptable range.
As shown in Fig. 5, Super slow etching of 0.8nm/min（0.013nm/sec） was achieved by decreasing Bias RF power.
With super slow etching, batch to batch distribution of etch
depth by time control was minimized and the precision ofetch depth control was improved. Furthermore, an excellent
profile without micro trenches, pits, or pillars was achieved,
as shown in Fig. 6. Cross wafer uniformity was ±2.5% for 6inch wafers.
At the time of recess etching, an interferometry type End
Point Detector (EPD) was used to monitor the etch depth.

Figure 2. Gate Injection Transistor (GIT) AlGaN/GaN-HFET structure

120""

120"
GaN"Rate"
SAMCO"Process"100""

Etch*Rate**[nm/min]*Figure 1. MOS-FET structure

D100"

Cl2/Ar/O2"Process"
80""

80"

60""

60"

40""

40"

20""

20"

0""

0"

Selec%vity**[GaN/AlGaN]*SS

O2*Gas*Flow**[sccm]*

Figure 3. GaN/AlGaN highly selective etchingGate
S5nm

DAlGaN
2DEGGaN
Figure 4. Recess gate structure for AlGaN/GaN-HFET

It is well known that interface information can bedetected using the refractive index difference of GaN andAlGaN layers. Furthermore, by optimizing a relevantformula, Fig. 8 was obtained to show the etch time to reachthe GaN layer and residual layer thickness (with initialAlGaN layer thickness of 25 nm). On the other hand, theetched sample was observed using AFM and it was foundthat the etch depth was 20 nm, and this coincided well withthe result of Fig. 8.

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Figure 5. RF bias power and AlGaN etching rate

Figure 7. Intensity of reflected 364 nm light vs. time

Photo ResistAlGaNGaN

Figure 6．Cross sectional SEM of gate recess using super slow etching

As shown above, SAMCO’s recess etching process withthe combination of super slow etching and interferometry
type EPD enables highly precise etching with a precision
range of ±1nm. Furthermore, this method can be applied tothe highly selective etching at the interface of GIT
AlGaN/GaN-HFET (etching p-GaN layer and stopping at
AlGaN layer) as described in subsection 2) above.
CONCLUSIONSSAMCO has successfully developed ICP-RIE etching
technology with low plasma damage, and surface
smoothness to achieve “Normally OFF” GaN-based powerdevices. Etch-stop technology to precisely control the etch
depth of AlGaN using an interferometry EPD, in particular,
is crucial to achieving the recess structure. This technology
can be applied to other processes involving the etching oflayers with different refractive indices. Additionally, though
not described in this report, SAMCO has been developing
PECVD technology to suppress current collapse. Systemand process development are now under way for otherpower device materials such as 4H-SiC, taking the 4H-SiCmarket potential into consideration.
ACKNOWLEDGEMENT
The authors wish to thank Associate Professor J. P. Ao,and former Professor Y. Ohno of the University ofTokushima for allowing us to use their systems and for theirvaluable advice on power device fabrication and testing.

392

Figure 8.

AlGaN thickness as a function of time (based on calculation)

REFERENCES[1] T. Shinoe: SiC Power Devices, Toshiba Review Vol. 59 No. 2 (2004).
[2] K. Matsuura, D. Kikuta, J.-P. Ao, H. Ogiya, M. Hiramoto, H. Kawa,and Y. Ohno: Jpn. J. Appl. Phys. 46 (2007) 2320.
[3] J-P. Ao, K. Nakatani, Y. Sogawa, Y.H. Kim, T. Miyashita, S. Motoyama
and Y. Ohno: GaN MOSFET with Gate SiO2
Deposited by Silane-Based PECVD, The 37th International Symposium on
Compound Semiconductors, 31st May - 4th June, 2010, Kagawa, Japan.
[4] Y.Uemoto,et al:Gate Injection Transistor(GIT) A normally-off
AlGaN/GaN power transistor using conductivity modulation. IEEE Trans.
Electron Devices 54, No.12, P3393 (2007).
[5] Panasonic Technical Journal Vol. 55 No. 2 July 2009

ACRONYMS
MOS-FET: Metal Oxide Semiconductor-Field EffectTransistor
HFET: Hetero-structure Field Effect Transistor
GIT: Gate Injection Transistor
2DEG: 2-Dimensional Electron Gas
ICP-RIE: Inductively Couple Plasma Reactive Ion Etching
PECVD: Plasma Enhanced Chemical Vapor Deposition
AFM: Atomic Force Microscopy

CS MANTECH Conference, May 19th - 22nd, 2014, Denver, Colorado, USA