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219(2004.11.5)

219-7

VLSI

Low-Power VLSI Processor Based on Real-Time Optimal Control◦Ahmad Shaheer ,◦Ahmad Shaheer , Michitaka Kameyama

Graduate School of Information Sciences, Tohoku University

Keywords : Adaptive threshold voltage control, Body-bias control, Optimal control, Power minimization,
Leakage current reduction.

Contact : 6-6-05, Aobayama, Aoba-ku, Sendai 980-8579
Kameyama Laboratory, Graduate School of Information Sciences, Tohoku University
Ahmad Shaheer, Tel.: (022)217-7155, Fax.: (022)263-9167, E-mail: shaheer@kameyama.ecei.tohoku.ac.jp

1.

Introduction

In the recent deep-submicron era, fluctuation exists in transistor parameters in a dynamic manner.
Complexity of power supply line in VLSI processors
is increased because of larger number of transistors
in a single chip. Consequently, on-chip supply voltage fluctuation becomes remarkable due to IR-drop
and fluctuation caused by inductances as shown in
Eqs. (1) and (2) and Fig.1. Let VDD be a real supply voltage superposed by fluctuation, and let Vd
be a desired supply voltage.

VDD = Vd + ∆V

(1)

didt

(2)

∆V = IR + L

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by-time in VLSI processors. Because of this fluc-tuation, power consumption and circuit delay will

vary, hence affecting the circuit performance. For
an example, ±0.2V supply voltage fluctuation may
cause almost 15% of delay and even cause the circuit to function incorrectly. There is performance

limitation due to a fixed control, where a transis-tor threshold voltage VT H is fixed during real-time

operations. By using a variable threshold voltage,leakage power consumption is greatly reduced withmaintaining the circuit speed.

Large voltage drop due to metal resistance exists
when large current flows through power supply line.
This deviation might vary space-by-space and time-–1–Fig. 1

Supply voltage fluctuation

The leakage power and frequency in a chip can

be controlled to some extent using body bias toful in changing VT H and for subthreshold leakage

modulate the threshold voltage of a transistor1 ) .

current minimization. To retain the correct opera-

There are two ways in controlling VT H . They aretion due to fluctuation, real-time adaptive thresh-

reverse body bias (RBB)2 ) and forward body bias

old voltage control (ATVC) is introduced to mini-(FBB)3 ) .

RBB has been used to reduce leakage

mize power consumption under a time constraint.

current consumption effectively by increasing theIn this case, internal states of a module should bebody-bias voltage of a pMOS transistor to be larger

easily detected, that is, observability is important

than a supply voltage. For an nMOS transistor,

as well as controllability as shown in Fig.3.

the body-bias voltage is reduced to be lower thanBCD3E

ground. These changes cause VT H increased during012345

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standby mode. FBB is used during active mode to67879:;<7=;> 67879?979@7A;<decrease VT H and improving circuit performance
although it increases leakage power consumption.
Both of these techniques, RBB and FBB are popFig. 3

ularly used to control VT H and to realize a variable threshold-voltage scheme in CMOS transis-2.1

tors. Figure 2 shows an example how body-bias

Basic adaptive control architecture

Adaptive Threshold Voltage Control (ATVC) Scheme

voltage has effects on a threshold voltage underSince supply voltage VDD fluctuation varies higher

RBB and FBB.

and lower than a desired supply voltage Vd , so RBB+* %) ('&" #%,--.-/$#" !
         Fig. 2Effect of body-bias on a threshold voltage

and FBB can be effectively used to control a transistor threshold voltage, adaptively. From the Eqs.
(3) and (4), power consumption is small if VDD islow, while the delay becomes large. VT H has tobe decreased to retain the speed. When VDD ishigh, the higher VT H reduces the leakage current
under the same delay condition and thus minimize
the power consumption. Basically, by raising VT H
when a supply voltage fluctuates above Vd , it minimizes the power consumption. Besides that, bylowering VT H when a supply voltage fluctuates be-2.

Adaptive Threshold Voltage

low Vd , it improves circuit performance.

Generally, the bulk voltage of the conventional
CMOS logic circuit is connected to VDD for thecase of a pMOS transistor and to the ground for theRPower, P =(pt CVDD 2 + idp dtVDD )fclk +Ileak VDD 10−VT H /Scase of an nMOS transistor. It is well known thatthe pMOS and the nMOS body-bias control is use-–2–Delay, td =(k ∗ C ∗ VDD )(VDD − VT H )α(3)(4)

From the above equation, the leakage current(Ileak )varies from 1.6V to 2.0V. Under this condition, 5

is inversely proportional to VT H as written in Eq.

levels of reference voltages are considered. If more(5).

voltage references and wider range of VDD fluctuaIleak αexp(−VT H )(5)tion are considered, power reduction ratio will become larger.

ATVC allows each bulk of CMOS transistors toAn optimal VT H for each case of VDD fluctua-

have optimum VT H in order to reduce the effectsof fluctuation. Figure 4 shows a module whose
VT H value can be controlled by a control circuit.
The ATVC scheme selects an appropriate bodybias voltage with respect to the changes in VDD .
The same VDD used in the module, is also used fora control circuit. VDD is compared with several
reference voltages in a control circuit. If the fluctuated VDD is higher than a desired supply voltage,
control circuit selects higher VT H . While the fluctuated VDD is lower than a desired supply voltage,tion is chosen if it satisfies a time constraint, T andpower minimization. Each of this optimal VT H isthen selected adaptively based on the range of supply voltage fluctuation during real-time operations.
Supply voltage 1.8V is chosen as a desired supply
voltage Vd and it acts like a starting point. At thatvoltage, there is no deviation and it is the normal
condition. The substrate bias voltage VSB is zeroand VT H is set to VT H3 . The delay time td when
supply voltage is Vd and threshold voltage is VT H3 ,becomes the time constraint T. Incorrect value of acontrol circuit selects lower VT H .

      time constraint causes inaccurate value of optimal
VT H .

We assumed VT H for a pMOS transistor is samewith VT H for an nMOS transistor. Figure 5 shows

Fig. 4ATVC architecture

an example of an inverter using ATVC scheme based

In this paper, the control frequency is assumed
to be higher than the supply voltage fluctuation
frequency. This assumption is important because

on an optimal control algorithm. In real-time, optimal VT H is obtained by the following algorithm
where VT H1 > VT H2 > VT H3 > VT H4 >VT H5 .

this allows sufficient time for the appropriate bodybias voltage to be selected and for the bulk CMOS
to adapt to the new threshold voltage before theVT H =VT H1 ; If (VT H1 ,VT H2 ,VT H3 ,VT H4 and VT H5 )satisfy td =g(VDD ,VT H )<=T
VT H =VT H2 ; If (VT H2 ,VT H3 ,VT H4 and VT H5 )control circuit updates a new voltage fluctuation.

satisfy td =g(VDD ,VT H )<=T

2.2

VT H =VT H3 ; If (VT H3 ,VT H4 and VT H5 )Optimal Control Algorithm

satisfy td =g(VDD ,VT H )<=T
It is important to find a simple control algorithm
in designing a simple control circuit. Let VDD fluctuation be 1.8V±10% or 1.8V±0.2V. Therefore it–3–VT H =VT H4 ; If (VT H4 and VT H5 )satisfy td =g(VDD ,VT H )<=TOtherwise VT H =VT H5

4.

        ! '()*%!()*"#$%& +!,+-%&&.#        
Fig. 5Simulation

For an example, an inverter is chosen as the targeted module. Using 0.18µm CMOS standard design rule, ATVC is verified on HSPICE simulation.
Power consumption and delay time dependency on
VDD and VT H are simulated and their relationshipis analyzed. VT H that is selected is an optimal
one as it meets a time constraint and is used for aATVC based on an optimal control

range of VDD as shown in Eq. (6). Value x and y3.

are the minimum and maximum supply voltage, re-Optimal Control Circuit

spectively for an optimal VT H . In this case a time
A control circuit is designed to be as simple asconstraint T is fixed at 29.2ps as shown in Fig.7.

possible but there are still area and power con-VT Hi (i = 1, 2, 3, 4, 5) ⇒ xi <= VDD <= yisumption overhead caused by a control circuit. To`\~{}|z`^  vx 
rwvy_\_^sqtru]\]^    ¡¢£¤¥¦¤§¨[\[\ [b [c [d [e ] ][aa a a fgghijakljmlnop aovercome area and power consumption overhead,targeted module should contain many transistors
such as 100 NAND gates. A control circuit consists of a voltage comparator and a voltage selector.
Figure 6 shows the schematic diagram of ATVC
scheme. VDD fluctuation is compared in a voltage
comparator and the output becomes the input ofa voltage selector. A voltage selector is introduced
to select an appropriate body-bias voltage. Output
from a voltage comparator enable transistors in a
voltage selector and the selected voltage becomes(6)

Fig. 7

5.

Delay time dependency on VDD and VT H

Evaluation

pMOS and nMOS body-bias voltage. Each body-

Table 1 shows delay time, power and leakage cur-bias voltage represents different values of threshold

rent when VDD fluctuation occurs but VT H re-voltage.

mains unchanged. It means that at this time no/??

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threshold voltage control is applied. Table 2 shows
delay time, power and leakage current after ATVC
scheme is applied. We can see that when VDD
fluctuates above a desired voltage which is 1.8V,
power is reduced at average of 2% and leakage current is reduced at average of 35%. However, when
VDD fluctuates below a desired voltage, decreas-Fig. 6

Schematic diagram of the ATVC scheme

ing VT H is necessary to maintain the circuit performance under delay time consideration although–4–

it increases power consumption especially leakage

Referencespower.

1) James W. Tschanz, James T. Kao, Siva G.
Narenda, Raj Nair, Dimitri A. Antoniadis, Anantha P. Chandrakasan and Vivek De, ”Adaptive
Body Bias for Reducing Impacts of Die-to-Die andWithin-Die Parameter Variations on Microprocessor Frequency and Leakage,” IEEE J. Solid-State
Circuits, vol. 37, pp.1396-1402, (Nov. 2002).

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Table 1 Delay time, power and leakage current
without ATVC scheme')'*(( ')'*+, H0I)4JK* -)./01* 73045460);*:L FM 2/ 81109:<=> >=?@ <A=B C=<CD >=EAF
B=A >=@? <A=> <=ADD B=DAF
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B=G >=D@ <A=> <=CGG @G=E9
B=? >=D< <A=B D=??@ ?=BG8
Table 2 Delay time, power and leakage current
with ATVC scheme

6.

Conclusion

Real-time adaptive threshold voltage control scheme
using body-bias control is effective in changing VT H
to minimize leakage power as well as to improve
circuit performance under a time constraint. Further study should be done to implement a complete
control circuit in real-time. In addition, real-time
optimal control scheme can be employed to compensate variation in threshold voltage by controlling the frequency or supply voltage subject to atime constraint for minimizing power consumptionof MOS transistors.

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