APPLICATION NOTE
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Low Side SmartFETs
AND8202/D
Introduction

Process Technology

The ever increasing density and complexity of automotive
and industrial control electronics requires integration ofcomponents, wherever possible, so as to conserve space,
reduce cost, and improve reliability. Further, thecomponents in an automotive environment can be often
exposed to harsh operating conditions in the form of highvoltage and/or high−power transients, cable short circuits,
inductive overshoots, electrostatic discharges etc. These
factors necessitate self−protection features to be integrated
into power FETs used for switching automotive loads.
Advancements in power MOSFET processing technology
afford an economical marriage of protection features (suchas current limitation) and standard MOSFET powertransistor switches. This document describes thetechnological and operational details of onsemi Low Side
SmartFETs. For any application specific details, it isrecommended to refer to High Side SmartFETs with Analog
current sense − AND9733.

The power stage in low side devices is realized using astandard vertical DMOS transistor process flow. The control
and protection circuitry is monolithically integrated with thepower FET. A vertical DMOS allows for greatertransconductance, higher breakdowns, improved power
densities and consequently better heat dissipation whencompared to lateral power FETs. Figure 1(a) and 1(b) below
illustrate the advantage in terms of Si area available forpower distribution at the drain terminal in a vertical process.
The planar gate stack structure, although offering a higher
specific RDS(ON) (conduction losses for a given Si area) thanits trench counterpart, does ensure greater energy handlingcapability, superior thermal response. Further, there is areduced likelihood of current crowding, ease of
manufacturability and higher reliability associated withplanar gate FETs. Considering these trade−offs for the rangeof RDS(ON) targeted in the low side Smart−FET family(Refer Table 1), a planar gate with a vertical DMOS
constitutes the optimal choice for the power element.

SourceGate
gate oxide
p+

n+

n+

p−tub

n+

p+

n+

p−tub

channeln epi

Substrate (n+)Drain(a) Vertical DMOS Structure and Carrier Flow
Drain

SourceGate

Gategate oxidegate oxide
n+

n+

n+

p−tub

channeln substrate(b) Lateral DMOS Structure and Carrier Flow

Figure 1. DMOS Structure and Carrier Flow
© Semiconductor Components Industries, LLC, 2011

April, 2022 − Rev. 4

1

Publication Order Number:
AND8202/D

AND8202/D
D

Overvoltage
Protection
G

ESD
Protection

Temperature

Current
Limit

Current
Sense

S

Figure 2. Generic Block Architecture of Low Side SmartFETs
General Topology

Figure 2 depicts the generic block level schematic ofonsemi low side SmartFETs.
All devices employ ESD protection clamps at the gate
input and over−voltage protection clamps between drain andgate to limit the voltage transients observed by the powertransistor as well as to enable an active clamping mechanism(described later), while switching inductive loads. The
ratings for these protection clamps are described in the
Absolute Maximum Rating section of the respective productdatasheet. In addition to over−voltage protection, otherprotection schemes include Over−Temperature shutdown(TSD), Differential Thermal Shutdown (DTSD) and current
limitation (ILIM) protections. The TSD protection limits the
maximum junction temperature observed by the die by

shutting down the device in case of a high temperature
operation; DTSD protects the device from stressful thermal
gradients and the ILIM protection limits the output current toa pre−defined level in case of a short circuit or an overload
condition. It should be noted that the availability ofprotection features may vary across devices in the portfolioand some devices may not be equipped with one or more of
the protections discussed. Refer to product datasheets foravailable protection schemes and their specifications. All
Smart−FETs can drive any type of resistive, inductive loadand capacitive loads such as solenoids, heater coils, andfilament bulbs limited only by the conduction and thermal
capability of the device. Table 1 below lists the low−sidefamily of devices and associated protection scheme.

Table 1. LOW SIDE PRODUCT FAMILY AND FEATURES
DevicePackage

TSD

DTSD

ILIM

Clamp Voltage (V) Typ

NCV8411

DPAK

X

X

X

46

NCV8413

DPAK/ SOT−223

X

X

X

46

NCV8412

SOT−223

X

X

X

46

NCV8412D

SO8

X

X

X

46

NCV8415

DPAK/ SOT−223

X

X

X

46

NCV8401A

DPAK/SOT−223

X

−

X

46

NCV8401B*

DPAK

X

−

X

46

NCV8403A

DPAK/SOT−223

X

−

X

46

NCV8403B*

DPAK

X

−

X

46

NCV8402A

SOT−223

X

−

X

46

NCV8402AD

SO8

X

−

X

46

NCV8405A

DPAK/SOT−223

X

−

X

46

NCV8405B*

DPAK

X

−

X

46

NCV8406A

DPAK/SOT−223

X

−

X

65

NCV8406B*

SOT−223

X

−

X

65

NCV8406D**

SO8

X

−

X

65

NCV8408

DPAK

X

−

X

46

NCV8440A

SOT−223

−

−

−

55

*Multiple assembly locations / **Product in development

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AND8202/D
Normal Operation

Fault Types

Under normal operation, the low-side product family
operates the same as any standard power MOSFET device.
Many of the data sheet parameters and data sheet curves are
identical to those found on standard MOSFET data sheets.
Since numerous application notes cover standard power
MOSFET operations topics including gate drive control,gate charge, switching characteristics, thermal
management, etc., this paper focuses only on load switching
and fault condition operation as well as the modes of normal
operation affected by fault protection circuitry.

Typical faults as observed in a low side application
include short circuit to supply and/or ground, open load,over−voltage, over−temperature and dynamic over−power
events.
Perhaps the most common and worrisome fault is a shortcircuit. This type of fault can take several forms, as detailed
below:

SupplyGround+VbattON+Vbatt+Vgate+Vgate+Vbatt+VbattOFF

Figure 3. Short Circuit Modes

device power dissipation, but can also result from extreme
ambient conditions or a thermal path anomaly such as asolder void between the device heatsink and circuit board.
Finally, a dynamic over−power event can inflict severe
thermal transients, or “shocks” to the die. Such stresses, if
applied repetitively, affect the reliability and lifetime
performance of the device. An example of such use−case is
the activation of a capacitive load (such as a bulb), requiringhigh inrush currents, through the life of the device. The
control circuitry of the low-side products can detect andcontrol device operation during many of these failure modesby operating in a safe mode so the device can return tonormal function once the fault is remedied. These control
features are biased off the input pin and a study of theprotection features necessitates a thorough understanding of
the gate input operation as explained in later sections.

Such short conditions are further exacerbated since often
the short circuits are intermittent and thus can take many
forms during even very brief periods. For example, in thecase of a short to ground with the MOSFET off, one
normally would not worry about the FET since current isdiverted through the short. However, if the short isintermittent and the load is inductive, the interruption of thecurrent flow results in a fly-back voltage appearing at thedrain node of the FET. The peak current in the load
inductance could be higher than normal operation due to theduration of the short and when the resistance of the short isless than the operating resistance of the MOSFET. Thus thedevice may absorb more energy than expected, andnumerous intermittent short events occurring in quick
succession could result in elevated peak junction
temperature, leading to potential device destruction.
A short circuit to supply with the FET on often results inan overload condition as there is little to no load impedance
to limit the current through the device. An over−voltage
condition may exist because of electro−static discharges atthe device pins, supply line transients and/or an inductive
discharge event. An open load does not overstress the device
in most cases and consequently protection circuit is not
required. Overtemperature failure typically results fromanother failure such as short circuit which vastly increases

Gate Input Operation

The gate input pin on the low-side family of products
behaves very much like the gate pin of a standard MOSFET.
The voltage at the gate input pin is linearly related to the gateof the power MOSFET output transistor and as such, themagnitude of this voltage determines the operation mode of
the output stage. At voltages below the device threshold, thedevice remains off and blocks the load supply voltage. As

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AND8202/D
A simplified input circuit is shown in Figure 4. Under
normal operation, the voltage supply at the input must be
capable of driving the output stage as well as the reference
circuit for over−temperature and current limit protection. In
a fault mode, the activation of protection circuit can cause
the current at this pin to be orders of magnitude higher thanthat in normal mode as explained below.

the gate voltage increases above threshold, the device
channel becomes progressively enhanced, putting the
MOSFET into the on state. As in case of standard MOSFET
devices, exceeding the rated voltage on the gate pin can
result in rupture of the gate oxide, thereby damaging thedevice. While the input pin of a low side SmartFET can be
driven by a standard MOSFET driver, the source and sinkcapabilities of the driver should be carefully considered
accounting for the drive requirements of the control
circuitry.

D

Rg1

G

Rg2
Tlim and Ilim
Pulldown NMOSTransistor

Tlim Ref. andControl Circuit

S

Figure 4. Simplified Input Circuit

protection (as explained in later sections) as well. While thecircuit is slightly different, the principle of gate current
variation stays the same, and the gate drive supply must be
capable of sourcing the required current in the protectionmode.
In some devices, a current monitoring mechanism at the
input terminal can provide the feedback on the operation
mode. Given that the input current in thermal shutdown issignificantly higher than that in nominal operation,
externally sensing the gate current can let the customer know
if a thermal shutdown has been enforced or not. Such amechanism is particularly beneficial in devices such as
NCV8408 in which the output stage is latched off afterthermal shutdown, or in the new generation (NCV841X)
low side devices that have distinctly specified gate current
ranges for normal and fault mode operations (Refer
datasheets). In devices with auto−retry, the gate current willcontinuously be changing as the output stage is toggled on
and off. The sensing mechanism at the gate input will
therefore be challenged and the accuracy of the externalsensors/comparators must be considered while attempting
to measure and diagnose the RMS input current.

When the device is in a current limit operation mode,
a feedback loop to the current limit pulldown transistor will
drive the gate of the power FET to near threshold voltage,
thereby regulating the device in linear mode. Thus in thismode, the gate input supply must be able to source a current
equal to (Vin – Vgate) / Rg1 plus additional bias current,
where Vgate is near threshold voltage. During thermal
shutdown, the Tlim pulldown transistor pulls the gate voltage
down to ground potential, thereby shutting off the output
stage. Thus, the gate input supply must source current equal
to approximately Vin/Rg1 plus some additional bias current.
In addition, Rg1 (and Rg2) are negative temperature
coefficient devices, thus temperature shutdown operation
mode is the worst case condition for determining minimum
gate drive current source and sink requirements. This
minimum source current must be available during an
overtemperature fault. If not, the pulldown transistor may
not keep the power FET off, possibly allowing the junction
temperature of the power FET to reach the destructive level.
The following table lists nominal room temperature valuesof Rg1, Rg2, and typical gate input current for normal andTlim fault conditions at elevated temperature by device.
It should be noted that the new generation NCV841X
devices incorporate differential thermal shutdown
Table 2. TYPICAL GATE INPUT PARAMETERS
DeviceRg1 (kW)Rg2 (kW)

Ig @ 5V (mA), TJ = 25 5C

Ig @ 5V (mA), TJ > Tlim

NCV8411

9.9

5.0

50

633

NCV8413

13.5

9.0

50

500

NCV8412

10

90

52

630

NCV8412D

10

90

52

630

NCV8415

30

20

50

240

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AND8202/D
Table 2. TYPICAL GATE INPUT PARAMETERS (continued)
DeviceRg1 (kW)Rg2 (kW)

Ig @ 5V (mA), TJ = 25 5C

Ig @ 5V (mA), TJ > Tlim

NCV8401A​

9.9

5.0

50

600

NCV8401B*

9.9

5.0

50

600

NCV8403A

13.5

9.0

50

450

NCV8403B*

13.5

9.0

50

450

NCV8402A

60

40

50

150

NCV8402AD

60

40

50

150

NCV8405A

30

20

50

220

NCV8405B*

30

20

50

220

NCV8406A

1.0

0.5

30

5900

NCV8406B*

1.0

0.5

30

5900

NCV8406D**

1.0

0.5

30

5900

NCV8408

14.4

11

25

440

Figure 3) causes the drain current to increase. Very seldom,
an overload condition may also exist because of an anomaly
in the load including its degradation over lifetime. In either
case, the current in the output MOSFET can increase to
detrimental levels if not limited internally by the device.
Figure 5 shows a simplified current limit blockarchitecture used in low-side devices. The current limit
function utilizes a load current sensing technique in whicha part of the power FET is sectioned off as Sense FET. The
vertical DMOS FET is comprised of individual “FET
fingers” in parallel. The source metal can be patterned in away such that it allows for separate source contacts− one forthe power FET and other over the Sense FET. The sense
FET, with its gate and drain still connected to power FET,
conducts a current proportional to that in the power FET
with a ratio governed by the ratio of the active areas of two
FETs. The source connection of the Sense transistor is
known as the mirror connection and the ratio of current
through the larger device to the current through the Sense
device is known as the current mirror ratio and is symbolized
by the letter n. This means a sense current equal to only 1/nof the load current flows through the current mirror
MOSFET. The lower power dissipation in the sense pathallows for the integration of a sense resistor in the control
circuit. More detailed information regarding SENSEFET
technology is found in onsemi application note
AND8093/D.

The resistances, Rg1 and Rg2, in addition to affecting
minimum input source current requirements, also affectswitching speed and EMI/RFI requirements for the gate
drive design. The gate of the power MOSFET essentially isa capacitive load to the gate drive supply, so any resistancein series with the gate input will slow down the rising andfalling switching transitions of load current and voltage.
Many discrete MOSFET circuit designs add 1.0 kW or moreof external series gate resistance in order to slow thenormally nanosecond rise and fall times, especially inapplications with strict EMI/RFI limitations. Since all
low side SmartFETs have integrated series gate resistance,
addition of external series gate resistance may not benecessary.
Lastly, the gate input pin of a MOSFET device may besubjected to ESD during the assembly, test, installation, andservice of the circuit board. All low side devices incorporateback to back ESD diodes (Figure 4) at the gate input pin.
These diodes, coupled with the internal series gate
resistance, provide the required ESD capability. For
specifications on zener breakdowns and ESD performance,
refer to product datasheets.
Current Limit Protection

The current limit protection is invoked in case the draincurrent exceeds a set threshold. In most cases, a short circuit
across the load (short to supply when the FET is ON per

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AND8202/D
+VB

Load
D
1:n

VIN

Rg1

Rg2

S

Current Limit
Block

RS

Figure 5. Simplified Current Limit Circuit

power MOSFET) whose input threshold is controlled by thevoltage across RSense. The new NCV841X devices utilize an
active op−amp based circuit to control the gate of the power
MOSFET. The new architecture offers a stable current limit
threshold across temperature as explained below.
As the power MOSFET heats up during the current limit
operation, the adjacent control circuit also observes a rapid
increase in temperature. The sense resistor and the thresholdof the pull-down FET exhibit a strong dependence on
temperature which causes a wide variation in the limited
current in case of a persistent overload or short circuit
condition. The threshold of the pull−down FET usually
reduces with increase in temperature which is reflected in
the sharp negative slope of the regulated current with timein the oscilloscope waveform per Figure 6a). The newarchitecture eliminates this dependence on the thresholdvoltage to regulate the output MOSFET by replacing thepull−down FET with a more efficient circuit. The resulting
current limit is more stable and predictable acrosstemperature as shown in Figure 6b).

The voltage developed across RSense is fed to the current
limit control block which then controls the gate of the output
stage. As the load current increases, the sense current
increases proportionally and so does the voltage developed
across RSense. When the voltage across RSense exceeds aninternal pre−set threshold (in accordance with the desired
current limit trip threshold), the voltage at the gate of thepower FET is reduced such that it operates in a linear, or
regulation mode. This feedback loop ensures that thechannel is not fully enhanced but sufficient to maintain theload current at the setpoint value while the current limit
circuit is active. Not only is the device conducting highcurrent, but it is conducting this current at high drain tosource voltage. In the case of a near perfect short across theload, nearly all of the load supply voltage is across the drain
to source of the power MOSFET. Thus, in the current limit
operation mode, the device dissipates significant power. A
sustained operation in current limit is therefore notrecommended as it may affect the device performance overlifetime.
In the older generation devices, the current limit blockprimarily constituted a pull−down FET (at the gate of thewww.onsemi.com
6

AND8202/Da) Typical Current Limit profile in NCV8401 at room temperatureb) Typical Current Limit profile in NCV8411 at room temperature

Figure 6. Typical Current Limit Profile

variation of typical measured current limit in NCV8401
across Gate−Source voltage. With the improved circuit in
NCV841X devices, the dependence on gate voltage is also
weakened, especially at higher gate voltages where thecurrent limit is pulled back close to its value at VGS = 5V.
The typical measured current limit on NCV8411 is plottedin Figure 7b).

The current limit value not only varies with temperature,
as discussed above, but also with applied gate voltage. A
higher gate voltage requires more current in the current limit
block so as to discharge or pull this potential down which inturn requires a higher voltage developed across the sense
resistor. Since this voltage is directly related to sense or load
current, a higher gate voltage essentially implies an increasein the current limit trip threshold. Figure 7a) shows thewww.onsemi.com
7

AND8202/Da) Measured current limit across gate−source voltage in NCV8401b) Measured current limit across gate−source voltage in NCV8411

Figure 7. Measured Current Limit across Gate−Source Voltage

reduce susceptibility to injected currents and Rg2 is added as
an additional structure to eliminate device latchup.

The series resistance Rg2 limits how fast the current limit
circuit reacts to load current exceeding the current limit
setpoint. Discharging the power MOSFET capacitancethrough Rg2 limits the current in the current limit block. This
results in limiting the dv/dt observed at the power MOSFET
drain as the drain voltage transitions from low on-statemagnitude to a higher magnitude in linear operation. This isimportant because a high magnitude dv/dt, especiallycoupled with higher supply voltages, may result in latchup
of one or more NMOS control transistors. Latchup can occur
when enough current is injected into the NMOS structure sothat a normally shunted parasitic P−N junction is forward
biased. The injected current comes from the capacitanceformed by the depletion region between the drain and P-tub
source region, from the relation i = CdV/dt. In the low-side
device process, each NMOS transistor layout is optimized toOver−temperature Shutdown Protection

An over−temperature condition can be absolute− in which
the junction temperature on the die exceeds a pre−set
threshold; or can be differential− in which there is a rapid
gradient in junction temperature due to a transienthigh-power dissipation through the device. While the older
generation devices offer protection only in case of an
absolute over−temperature event, the new NCV841X family
is equipped with both absolute as well as dynamicover−temperature protection schemes.
Figure 8 diagrams a simplified overtemperature detection
and shutdown circuit.

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AND8202/D
+VB

Load
D

Rg1

VIN
VREF

Rg2

TSD/DTSD
Control

TSD
TSD/DTSD
Sensors &Hysteresis
HYSTS

Figure 8. Simplified Over−temperature Shutdown Circuit

In case of a sudden “thermal shock” to the die, the difference
between the two sensed temperatures is monitored andcompared to a preset threshold. Figure 9 is a pictorial
representation of the sensors termed as “hot” and “cold” inaccordance with their anticipated relative temperatures incase of power dissipation through the device. Intuitively, thesensor at the periphery of the FET active area will observea lower temperature than that at the center as the heat wave
propagates through the die. Shutting off the output stage incase of large temperature gradients prevents the die fromgetting “worn−out” over the lifetime as explained below.

An internal reference voltage generated off the input
supply biases the on−chip temperature sensitive elements.
These sensors are generally realized close to the center of thepower FET active area on the die which is expected toobserve maximum temperature in case of power dissipation
through the device. If a temperature exceeding the TSD
threshold is sensed, then the TSD protection circuit pulls
down the gate voltage of the power FET thereby shutting off
the output stage. A hysteresis circuit allows the output stage
to turn back on after the junction temperature on the diecools down to a defined setpoint.
In case of differential thermal protection, another sensing
element, at the periphery of the FET active area, is utilized.

FET
Hot Thermal Sensor

Cold Thermal Sensor

Control

Figure 9. Sensing Elements in Differential Thermal Shutdownwith a hysteresis as in case of absolute TSD. If the short ispersistent, the temperatures measured by both the sensors
increase with each “retry” and after some cycles, an absolute
thermal shutdown threshold will be attained which will thenoverride and protect the device thereafter. In the absence ofa differential thermal shutdown mechanism, the output stage
will not be turned off until the junction temperature reaches~ 175°C (typical TSD threshold in most devices). Thisimplies an initial gradient of more than 200°C considering

Consider the idealized set of waveforms in Figure 10
depicting a short circuit to supply. The ambient temperaturein this case is −40°C. When the current exceeds the ILIM
threshold, the output stage is regulated and power
dissipation through the FET increases. As the die heats up,
the gradient between the hot and cold sensors increases andeventually the output stage is turned off when the difference
between the two sensors reaches ~ 60°C (typical DTSD
threshold in most low side devices). The FET is turned onwww.onsemi.com
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AND8202/D
an ambient temp of −40°C at the beginning. Such hightemperature gradients inflict a huge amount of stress on thedie and reduce its lifetime and reliability, especially whensuch stresses are applied repetitively.

t

VIN
ILIM

t

IOUT

Absolute Temperature Shutdown

TJ

Hysteresis

TTSD

t

DTJ ~ 60 ° C
Figure 10. Idealized Wave−set depicting DTSD Protection (not drawn to scale)

short circuit performance per the table below. The
NCV841X family of devices, equipped with Differential
Thermal Shutdown, offer a superior RSC performance thanthe older generation of devices.

The repetitive short circuit (RSC) performance of theseproducts is quantified in terms of the number of cycles
withstood without a failure per the AEC−Q100−012
standard. The standard also grades the devices based on their
Table 3. RSC Grades per the Number of Cycles Appliedin accordance with AEC−Q100−012

Oscilloscope captures below depict the absolute anddifferential thermal shutdowns associated with the current
limit pulse trains in case of a short circuit applied to

NCV8401 and NCV8411 respectively. As can be noticed
that the output stage turns off in NCV8411 earlier in time
because of the DTSD control as compared to the absolute

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AND8202/D
TSD control in NCV8401. Both the waveforms were
measured at an ambient temperature of 25°C with VGS = 5 V
and VBAT = 12 V. It should also be noted that while thewaveforms hold a comparative significance in time, theabsolute response times will depend on the thermal
management in the application and may differ from one
application to another.

a) TSD Thermal Cycling in NCV8401b) DTSD Thermal Cycling in NCV8411

Figure 11. Thermal Cycling

While the majority of low side SmartFETs from onsemi
are designed with hysteretic auto−restart capability in anover−temperature scenario, certain devices such as
NCV8408 are designed to latch off the power MOSFET withthermal shutdown and allow a restart only after the input pin
is toggled. It is recommended to refer to individual productdatasheets for device specific retry strategy.
Since the reference voltage for the temperature sensing
elements is affected by the magnitude of the gate input
supply voltage, especially at lower gate voltages, theovertemperature setpoint decreases as the gate input voltage
increases up to approximately 5.0 V. As depicted in
Figure 12, the overtemperature threshold can reach highvalues of more than 200°C at gate voltages less than 4 V. Thisimplies that driving the device with low gate voltages, forinstance with a 3.3 V input, may expose the die to hightemperatures that can potentially damage the device. It is,therefore, not recommended to employ low gate drive
voltages. In addition, while using external protection
resistors at the input pin, the drop across this resistor mustbe accounted for as this drop would reduce the available
voltage at the input pin to bias the TSD block. In general,
onsemi recommends using a standard 5V supply at the gate
input with sufficient current capability for both normal andfault mode gate drive. This also ensures performanceadherence to specification since datasheet parameters are
generally specified at 5 V (or 10 V) gate voltage. As theapplied gate voltage increases above 5.0 V, the temperature
shutdown limit marginally increases with increasing gate
voltage. This is illustrated in Figure 12. The slight increasein the temperature shutdown limit for gate voltage above 5.0
V is due to the increased gate drive required by the NMOS
pulldown transistor as the NMOS drain voltage increases.

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AND8202/D
Tlim Setpoint vs. Gate Voltage

JUNCTION TEMPERATURE (5C)

220
210
200
190
180
170
160
150
3

4

5

6

7
Vgs (V)

8

9

10

11

Figure 12. Typical Temperature Limit Shutdown as a Function of Gate Voltage
Over−voltage Protection

measurements were performed with a 7 W load resistor atroom temperature. As can be seen in the waveforms, thedevice passes a load dump level of 75 V (typically sustained
over 100’s of milliseconds) while gets damaged at a load
dump level of 80 V with the output stage latching on andcurrent being limited by the load impedance. The input
command to the device was off in both scenarios implyingthat the protection features were not available during load
dump stress. While the clamp is engaged in both cases, thepower dissipation in the regulation mode at the higher load
dump level is sufficient to increase the die temperature
beyond it’s max capability which causes the device to fail.
It can also be observed that the clamp breakdown is“stretched” as the applied voltage increases. This is because
the breakdown characteristics of protection diodes exhibit aresistive component and do not mimic that of ideal zeners.
A higher load dump level essentially forces a higher current
through the clamps thereby yielding a slightly higher clamp
breakdown. The instantaneous power dissipation throughthe device can simply be calculated as (Vpk(transeint)(t) −VClamp(t)/R)L*VClamp(t) where RL includes both theexternal resistance and any resistance internal to the load
dump supply. If the cumulative power dissipation, at any
point while the clamps are engaged, causes the dietemperature to exceed maximum device capability, then thegate will lose control of the output stage resulting inpermanent damage to the device. It can thus be inferred thatthe thermal management in the application is also crucial tosurviving such over−voltage events. It should be noted thatthe damage to the device in this case was obvious in the
waveforms. In many cases, however, the damage is notnoticeable and over−voltage stress manifests itself as anon−conformance to the guaranteed electrical parametricspecification. The device performance is therefore assessedby checking key performance parameters such as RDS(ON),leakage, threshold etc. before and after the stress is applied.
In general, the higher the clamp voltage, the greater the load
resistance and the larger the device active area, the greater
the peak transient drain voltage that the device can survive.

Automotive environment is susceptible to high voltage
transients often inflicted in the form of ESD (Electro−Static
discharge) overstresses, alternator load dumps, as well asparasitic supply line transients modelled in ISO 7637−2.
Further, an inductive load discharge can also expose thedevice to high voltage levels. onsemi low side SmartFETs
have integrated over−voltage protection structures designed
to handle these stresses. Figure 13 highlights thesestructures. The ESD diodes from gate−source limit thetransients observed across the gate−stack structure andthereby protect the gate oxide from getting damaged. In casean application is expected to frequently observe highvoltages at the input drive, it is recommended to place
protection resistors at the input pin of the SmartFET to limit
the current through these ESD diodes. Further, inapplications employing a sense resistor at the source
terminal, caution must be exercised to ensure that thegate−source differential voltage does not exceed thebreakdown of these protection diodes. The absolute
maximum rating section of the respective product datasheets
must be referred to for specifications on these ESD
structures.
The alternator load−dumps and supply line transients
seldom present a high voltage at the output terminal. The
over−voltage protection clamps between drain and gate
protect the device in such case. If the voltage at the drainincreases over and above the clamp breakdown, and the
input command to the device is turned off, the protection
diodes are activated and regulate the device with the active
clamping mechanism (as described in Inductive Switching
section). If the input is turned on, the load impedance limits
the current through the device and at high supply levels,
current limitation can be triggered. In either case, if theover−voltage event is expected to last over an extended
duration, then the thermal capability of the device must be
considered while selecting the device for an application.
For instance, the waveforms in Figure 13 depict thestimulated load dump capability of NCV8406. The

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AND8202/Da) Pass: VGS = 0 V, Va + Vs = 75 V (Device clamps at 67.6 V)b) Fail: VGS = 0 V, Va + Vs = 75 V (Device clamps at 68.4 V)

Figure 13. Stimulated Load Dump Capability in NCV8406
Load Switching

and turn off times with intentionally reduced internal
resistors− Refer Figure 14 a) and 14 b) for typical measured
turn on and turn off response in NCV8406 at room
temperature with no external gate resistor. Switching times
also relate to the efficiency of a SmartFET in the form ofswitching energy losses. In a high−speed application,
switching losses can contribute to a significant proportion of
overall losses and may even override conduction state
losses. It should also be noted that switching times in thedatasheet are specified against a set of conditions such as theload resistor, external input resistor, gate voltage etc. While
selecting a device for an application, it is recommended toensure that any difference in conditions with regards to theResistive Switching
onsemi low side SmartFETs can be used to switch avariety of resistive loads including, but not limited to, LEDs,
squibs, heating elements etc. The internal resistors
connected to the gate terminal limit the output slew rate
thereby improving the EMI performance of the device inaddition to serving the protection features. Most automotive
loads require switching frequency in the range of a few
hundreds of Hz. The turn on and turn off times of a device
must be referred to while making the selection for theapplication. For certain applications that require fastswitching, devices such as NCV8406 offer faster turn off

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13

AND8202/D
application conditions is accounted for. For example, ahigher gate voltage forces a faster turn on time; an external
gate resistor, on the other hand, will slow down the switchingtimes. In addition to switching times, the datasheets also

specify slew rates during turn on and turn off. These allow
the user to calculate the turn on times specific to a battery
voltage.

a) Turn−on response in NCV8406b) Turn−off response in NCV8406

Figure 14.

accompanied by high voltage transients (dependent on therate of output current decay and the value of inductance).
The low side devices are equipped with an internal clamp tolimit the output voltage excursions in case of an inductive
flyback event.
Figure 15 and Figure 16 depict the schematic
representation and a typical oscilloscope wave capture incase of inductive load switching.

Inductive Switching
A wide majority of automotive loads, including solenoids,
relays, motors, actuators etc., are inductive in nature ranging
from a few mH’s all the way to 100’s of mH’s. Automotive
cables and harness, to a certain extent, present an inductive
impedance (to the order of a few mH’s), making it imperative
for the SmartFETs to be able to drive inductive loads. Unlike
resistive loads, the voltage and current polarity in inductive
loads is opposite to each other and load switching is often

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AND8202/D

Figure 15. Inductive Switching Circuit Diagram

Figure 16. Inductive Switching Oscilloscope Capture on NCV8406D with L = 10 mH

output FET. This prevents the body diode of the output FETfrom avalanching each time when an inductive discharge
happens. Repetitive avalanche breakdowns of the body
diode can present a reliability concern over the lifetime ofthe device. Similar to the charge time, the discharge time
(ignoring the line resistance) can be expressed as below:

As the device turns on, the inductive load is charged to a
current defined by the power supply voltage, conduction
losses across the device and the duty cycle of the input PWM
drive. Most inductive loads have a resistive component aswell which limits the peak load. Ignoring the line resistance,
the time required to charge the inductance to a pre−definedcurrent level can be expressed with the equation below:

t OFF +

I pk Lt ON +V BATT * V DS(ON)I pk L
V CLAMP * V BATTIt should be noted that the switching times are entirely
dependent on the external conditions because of theunderlying assumption that the value of inductance, or peakcurrent is not too low to infringe with the response times ofthe device and the integrated clamp. In other words, thespeed and response of the clamp to the inductive stimulus isvery fast and the resulting switching times are entirely
dependent on the external factors such as the peak current or
the value of the inductance itself.
In addition to voltage limitation, the drain to gate clamps
engage an active clamping mechanism by developing a
voltage at the gate of the output FET. When the clamps areactive, the current through these clamps bias the internal

While switching inductive loads, the most critical aspectis the driver’s ability to handle the inductive flyback energy
at switch−off. As the input command to the driver observesa high ³ low transition, the current flow in the inductor isinterrupted and it develops a voltage at the output terminal
to oppose the change in current flow. As the current starts todecay, the output voltage increases. In the absence of aninternal voltage limiting mechanism, the output voltage canreach detrimentally high levels. To preclude such a scenario,
onsemi low side SmartFETs have integrated drain−gateclamps as shown in Figure 15. The breakdown voltage ofthese clamps is set lower than the process breakdown of thewww.onsemi.com
15

AND8202/D
capability is specified. The value of inductance, battery
voltage, external gate resistor, if any, and ambient
temperature affect the energy capability specification. In
addition, any resistance in line, tends to increase theavailable voltage across the inductor for discharge andthereby presents a smaller “effective inductance”. The
datasheet curves provide extensive information on thevariation in SCIS energy with these factors. The condition
set and energy requirements must be considered while
selecting a device for an application.
Since most applications drive the load continuously in a
PWM fashion, it becomes intuitive to consider the repetitive
clamp (RCL) performance of the device as well. The RCL
performance is specified in terms of max current (or energy)
that can be switched with a known inductor over one million
cycles such that the temperature at the beginning of eachcycle is equal to the ambient temperature. In other words,
successive cycles do not inflict a cumulative temperature
increase.
Lastly, many applications use external clamps todischarge the inductive load as shown in Figure 17. For
instance, many solenoid actuators maintain a relatively
constant pressure by virtue of an RMS current established by
the PWM rate of the input drive. In order to prevent a fast
output current discharge (attributed to a high clamp voltage),the SmartFET is shunted with a parallel diode that reduces
the available voltage across the inductor to a diode drop(~0.7 V), thereby maintaining a near constant current
because of the slow discharge. While employing suchcomponents in tandem with the device, their breakdown andparasitic effects must be considered so as to avoid any
interference during the normal operation of the device.

gate resistors, and the voltage at the gate node becomes
greater than the threshold voltage of the FET. The output
stage is, thus, regulated in a linear mode and the inductive
current is discharged across the entire FET active area. As
the current decays, the gate voltage slightly reduces but isstill maintained over and above the threshold until thecurrent entirely discharges to zero. At this point, the output
voltage and gate voltage also drop to zero and the output
stage is turned off. Such a mechanism is called Self Clamped
Inductive Switching (SCIS) capability. Without theseclamps, the inductive current is discharged across the body
diode which limits the energy handling capability of thedevice. The energy capability is defined by the maximum
current that can be discharged across the device
corresponding to a given inductor. As the device operates
with a high voltage across drain−source, the temperature in
an SCIS event can increase rapidly as the power is dissipatedduring inductive discharge. An important consideration hereis the absence of over−temperature protection feature during
the flyback. Since an inductive discharge only happens
when the input observes a high ³ low transition, the TSD
sensors and the protection circuit (Refer Over−temperature
shutdown), that are biased off the input supply rail, remain
inactive. This implies that the temperature can reachdestructive levels at high discharge currents, which then puts
a ceiling on the maximum allowed current, or
correspondingly a maximum allowed SCIS energy. Theenergy capability is a quantitative metric widely used toqualify the performance of a SmartFET. In simplistic terms,
energy can be specified as E = 0.5 × L × I2.
However, as with any other parameter, due emphasis must
be placed on the set of conditions against which the energy

+VB

Load

External
Freewheeler

D
I3

G−D
Zener Clamp
Rg1

Rg2

VIN
S

Figure 17. Application Example with External Diode for Inductive Flyback

types of bulb loads and their characteristics in great detail.
To summarize, each bulb is characterized in terms of rated
wattage at a given voltage and the inrush required at turn on.
The nominal filament resistance can be calculated as:

Bulb Switching
While external lamps such as headlamp or turn signal
indicator utilize high side drivers, most internal lamps suchas the cabin lamp, or instrument cluster lamps are driven inlow side configuration. Bulbs, or incandescent lamps areprimarily capacitive in nature with a resistive element as
well. The application note AND9733 describes different

R Nom +

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V 2NomP Nom

AND8202/D
Where PNOM is the rated wattage and VNOM is the
specified voltage. The nominal load current can also be
calculated similarly. While a nominal current signifies theload requirement in steady state operation, all bulbs also

require an inrush current at turn on in order to heat thefilament. Figure 18 shows the inrush profile of a 4*R10W
when it is switched on by NCV8411 at an ambient
temperature of −40°C.

Figure 18. Inrush Profile of 4*R10W when Switched On at −405C

ambient temperature of the bulb and that of the driver, thevoltage available to power on the bulb, any parasitic line
resistance etc. impact the inrush profile. For example, a low
ambient temperature will ensue a long inrush phase whereas
a low parasitic resistance will imply that most of the supply
is available for the activation of bulb load. Since thesefactors vary from one application to another, it becomes very
challenging to select the driver for an application, especiallyin the absence of empirical relationships between practicalbulb turn on profiles and their controlling factors.
To circumvent the challenge presented above, anidealized circuit as depicted below is utilized to characterize
the inrush profile of a bulb:

It should be noted that as the bulb turns on, the filament iscold and consequently its resistance is very small whichcauses the current to increase. As the filament heats up, theresistance increases and load gradually reduces until itreaches a steady value. This dynamic nature of the filament
resistance emulates that of a capacitor which also presents
a low impedance at turn on followed by a gradual reductionof the load. The time interval during which the output
current reduces to 50% of its peak value is generally termed
as the inrush time and most automotive manufacturers placea maximum allowance on the inrush timing. As with anyother load activation, the set of external conditions
determine the inrush profile and the ability of a driver topower on a load in the required inrush time. In this case, thewww.onsemi.com
17

AND8202/D+20V to 24V

LM358
Reference
VoltageHigh Power
Regulated
FET(s)−+
1kW

Stable Supply
Generated
10kW

Current probe
Bulb under
test

LM358
NCV84XX

10kW

−
+

10kW
10kW

Figure 19. Idealized Circuit to measure the Inrush Profile of a Bulb against a known Driver

characteristics also influence the inrush profile and timing
to a great extent. Since an inrush event observes higher than
nominal current levels, the internal current limitation of theSmartFET can be triggered during the inrush phase. If thecurrent is regulated for an extended time then thermal
shutdown may be triggered thereby forcing the output stage
to shut off and subsequently retry with the thermal
hysteresis. The retry strategy, although designed to protect
the device, will impact the inrush timing for a given bulb
load. The waveform below depicts an 8*R10W being
switched on with NCV8411. The ambient temperature forthe bulb is −40°C and that for the device is 25°C.

This circuit configuration ensures that the supply
available to activate the bulb is held constant at a knownreference voltage level. Further, a low line resistanceconstituted with short power cables provides a near ideal
condition for activating the bulb. The inrush times measured
with this setup are compared with the customer
requirements and then used to make device
recommendations corresponding to a bulb load. While thisis a standard setup, onsemi can test the required bulbs underapplication conditions based on specific customer requests.
The description above is focused on the set of external
conditions dominating the inrush profile without muchemphasis on driver constraints. In reality, the driver

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AND8202/D

Figure 20. Inrush Profile with Retry Strategy

Accounting for all these factors, the device
recommendations are made while ensuring that the inrush
time is within the allowed limit as well as the device is notoverstressed in the application.
The last consideration with regards to a bulb load drive
capability is the steady state conduction loss through thedriver. As stated before, once the filaments heats up, its
resistance gradually increases and reaches a steady value of
RNOM. The driver, in addition to satisfying the inrush
requirements, should also be capable of handling the power
dissipation in steady state. As with any load, a calculation of
the maximum anticipated junction temperature must be
made using the expected power dissipation in steady state.
Since most bulb loads are operated in PWM mode with anominal resistive load, the average power over the pulse
train should be considered while doing these calculations.

As can be seen in the waveform, the current is regulated
at the current limit for a while after which the differential
thermal shutdown intervenes and shuts off the device. The
inrush time in case of retry strategy being invoked is definedas the time interval between turn on and the beginning of thelast retry as highlighted by the cursors in the waveform. In
NCV840X devices with no differential thermal shutdown,
the device is shut off only because of absolute thermal
shutdown which implies a longer time in regulation ascompared to the retries in waveform above. Although anabsolute TSD helps deliver more power to the load, it
overstresses the device at each load activation because of theassociated high temperature transient. On the other hand, thetemperature sensitivity of the current limit is significantly
higher in NCV840X family of devices and the current ineach retry observes a steeper slope (resulting in lower power
delivered per retry) as compared to the waveform above.

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AND8202/D
Summary of Failure Modes

A summary table of potential device failure modes andmitigation strategies is shown below.
Table 4. POTENTIAL DEVICE FAILURE MODES AND MITIGATION STRATEGIES
Potential Failure Mode

Mitigation

Insufficient gate drive during fault condition− Increase current source/sink capability of gate drive circuit− Increase gate drive voltage

Excessive dV/dt at drain− Increase series gate resistance− Filter or snubber circuits to eliminate fast edge transients− Reduce supply voltage

Excessive die temperature during SCIS operation− Reduce load inductance− Reduce circuit parasitic inductance− Use lower clamp voltage device− Use device with proper energy rating− Decrease device duty cycle or frequency or both
− Use parallel devices

Excessive die temperature during load dump or other transient
event− Increase load resistance− Improve transient thermal response via better thermal pathway
or larger silicon active area
− Use parallel devices

Summary

operation modes as described in this application note.
Moreover, while designing an application, it is important toconsider the mitigation mechanisms described above to
avoid over−stressing the SmartFET.

The low-side device family offers an efficient monolithic
solution to integrating protection features with verticalpower MOSFET technology. The operation and applicationof these devices is the same as standard MOSFETs,
assuming the gate drive circuit design allows for fault

SENSEFET is a registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
onsemi,, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
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Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or deathassociated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal
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