Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ASNT5001A-PQC
DC-32Gbps/17GHz Signal Phase Shifter with Linearized OBBroadband (DC-32Gbps / 17GHz) tunable data/clock phase shifter

Delay adjustment range of 265ps

Exhibits low jitter and limited temperature variation over industrial temperature range



1GHz of bandwidth for the phase adjustment tuning port

Fully differential CML input interface

Fully differential CML output interface with 600mV single-ended swingLinearized data output for minimized undershoot/overshoot.

Single +3.3V or -3.3V power supplyPower consumption: 1.17W

Fabricated in SiGe for high performance, yield, and reliabilityStandard MLF/QFN 24-pin package

ASNT5001A

Rev. 1.1.2

1January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

DESCRIPTION

50
ip50
outp

TunablePhase Shiftin50outn50

50

50

icntp icntn
Fig. 1. Functional Block Diagram

ASNT5001A-PQC is a data / clock variable delay line fabricated in a SiGe technology. The IC shown inFig. 1 provides an adjustable delay of its differential output signal outp/outn in relation to its broadband
input signal ip/in. The delay adjustment range is temperature-stabilized. The delay is controlled through awide-band differential tuning port icntp/icntn.
The part’s I/Os support the CML logic interface with on chip 50Ohm termination to vcc and may be useddifferentially, AC/DC coupled, single-ended, or in any combination (see also POWER SUPPLYCONFIGURATION). In the DC-coupling mode, the input signal’s common mode voltage should comply
with the specifications shown in ELECTRICAL CHARACTERISTICS. In the AC-coupling mode, theinput termination provides the required common mode voltage automatically. The differential DC
signaling mode is recommended for optimal performance.
The output buffer is linearized for reduction of undershoot and overshoot on the output waveforms. Dueto an extremely low jitter, the part is suitable for use in high-speed measurement / test equipment.

Delay Control PortThe delay is controlled through a wide-band differential tuning port icntp/icntn. The delay control
diagram is shown in Fig. 2.

Rev. 1.1.2

2January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

Delay Adjustment in 5001 (in the socket, new setup)
150

Delay shift, ps

100
50
0-0.6

-0.5

-0.4

-0.3

-0.2

-0.1

00.1

0.2

0.3

0.4

0.5

0.6

-50-100-150
Vcntn-Vcntp

Fig. 2. Delay Control Diagram

POWER SUPPLY CONFIGURATION
The part can operate with either a negative supply (vcc = 0.0V=ground and vee = -3.3V), or a positivesupply (vcc = +3.3V and vee = 0.0V=ground). In case of a positive supply, all I/Os need AC termination
when connected to any devices with 50Ohm termination to ground. Different PCB layouts will be neededfor each different power supply combination.

All the characteristics detailed below assume vcc = 0.0V and vee = -3.3V.

Rev. 1.1.23January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ABSOLUTE MAXIMUM RATINGS
Caution: exceeding the absolute maximum ratings shown in Table 1 may cause damage to this productand/or lead to reduced reliability. Functional performance is specified over the recommended operating
conditions for power supply and temperature only. AC and DC device characteristics at or beyond theabsolute maximum ratings are not assumed or implied. All min and max voltage limits are referenced toground (assumed vcc).
Table 1. Absolute Maximum Ratings

Parameter
Supply Voltage (vee)Power Consumption
RF Input Voltage Swing (SE)
Case Temperature
Storage Temperature
Operational Humidity
Storage Humidity

Min-401010Max-3.6
1.3
1.0+90+1009898

Units
VW
VºC
ºC%%

TERMINAL FUNCTIONSTERMINAL
Name
No.
Typeipinicntp
icntn
outp
outn
Name
vcc
vee

Rev. 1.1.2

DESCRIPTION

High-Speed I/Os
Differential high-speed signal inputs with internal SE 50Ohm
termination to vcc
Differential low-speed control inputs with internal SE 50Ohmtermination to vcc
Differential high-speed signal outputs with internal SE 50Ohm
termination to vcc. Require external SE 50Ohm termination to vcc
Supply And Termination Voltages
Description
Pin Number
Positive power supply (+3.3V or 0)
1, 3, 5, 7, 9, 11, 13, 14, 15, 16, 17, 19, 21,23
Negative power supply (0V or -3.3V)
6, 12, 18, 24
20
2224
10
8

CML
input
CML
input
CML
output4January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ELECTRICAL CHARACTERISTICSPARAMETERveevcc
Ivee
Power consumption
Junction temperature
Data Rate
Frequency
Swing
CM Voltage Level
Data Rate
Frequency
Logic “1” level
Logic “0” level
Rise/Fall times
Output Jitter
Duty cycle
Adjustment range
Absolute delay stability
Bandwidth
SE voltage level
SE voltage level
Differential swing
CM Level

MIN

TYP MAX UNIT
COMMENTS
General Parameters
-3.1
-3.3
-3.5
V
±6%
0.0
V
External ground
355mA
1.17W
-2550
125°C
HS Input Data/Clock (ip/in)
DC32Gbps
DC17GHzFor clock signals
0.05
1.0V
Differential or SE, p-p
vcc-0.8
vcc
VMust match for both inputs
HS Output Data/Clock (outp/outn)
DC
32Gbps
DC17
GHz
For clock signals
Vvcc
vcc-0.6
VWith external 50Ohm DC termination1418
ps
20%-80%1
ps
Peak-to-peak
455055%
For clock signal
Output-to-Input Delay
For the full range of icntp/icntn
265
pscontrol signals
-28
28
ps
0-125°C
Tuning port (icntp/icntn)
DC1000MHz
vcc-600
vccmV
Half control range when the opposite
pin is at vcc
vcc-1200
vccmV
Full control range when the opposite
pin is at vcc-0.6V01200mV
Peak-peak, full control range
vcc-(Diff. swing)/4VIn differential mode

PACKAGE INFORMATIONThe chip die is housed in a standard 24-pin QFN package shown in Fig. 3. It is recommended that thecenter heat slug located on the back side of the package is soldered to the vee plain, which is ground forthe positive supply or power for the negative supply. It will help dissipate heat generated by the chipduring operation.

Rev. 1.1.25January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

The part’s identification label is ASNT5001A-PQC. The first 9 characters of the name before the dashidentify the bare die including general circuit family, fabrication technology, specific circuit type, and partversion while the 3 characters after the dash represent the package’s manufacturer, type, and pin out
count.
This device complies with the Restriction of Hazardous Substances (RoHS) per 2011/65/EU for all tensubstances.

Fig. 3. QFN 24-Pin Package Drawing (All Dimensions in mm)

Rev. 1.1.2

6January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

REVISION HISTORY
Revision
1.1.2
1.0.2
1.0.1

Rev. 1.1.2

Date01-2020
07-2019
03-2017

Changes
Updated Package Information
Updated Letterhead
Initial release

7January 2020