Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ASNT5175-PQC
DC-17Gbps/14GHz Signal Phase Shifter

Broadband (DC-17Gbps/DC-14GHz) tunable data/clock phase shifter

Delay adjustment range of 255ps

Exhibits low jitter and limited temperature variation over industrial temperature range



1GHz of bandwidth for the phase adjustment tuning port

Fully differential CML input interfaces

Fully differential CML output interface with 400mV single-ended swingSingle +3.3V or -3.3V power supplyPower consumption: 610mW

Fabricated in SiGe for high performance, yield, and reliability

Standard MLF/QFN 24-pin package

Rev. 6.5.2

1January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

DESCRIPTION

50
ip

50
outp

TunablePhase Shiftin50

outn
50

5050

icntp icntn
Fig. 1. Functional Block Diagram

ASNT5175-PQC is a data / clock variable delay line fabricated in SiGe technology. The IC shown in
Fig. 1 provides an adjustable delay of its differential output signal outp/outn in relation to its broadband
input signal ip/in. The delay is controlled through a wide-band differential tuning port icntp/icntn.
The part’s I/O’s support the CML logic interface with on chip 50Ohm termination to vcc and may be useddifferentially, AC/DC coupled, single-ended, or in any combination (see also POWER SUPPLYCONFIGURATION). In the DC-coupling mode, the input signal’s common mode voltage should comply
with the specifications shown in ELECTRICAL CHARACTERISTICS. In the AC-coupling mode, theinput termination provides the required common mode voltage automatically. The differential DC
signaling mode is recommended for optimal performance.
Due to an extremely low jitter, the part is suitable for use in high-speed measurement / test equipment.

Delay Control PortThe delay is controlled through a wide-band differential tuning port icntp/icntn. The delay control
diagram is shown in Fig. 2.

Rev. 6.5.2

2January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Delay Adjustment in ASNT5175 (new setup)

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

180160140120100

Relative Delay, ps806040200-0.6-0.5-0.4-0.3

-0.2

-0.1

-20 0

0.1

0.2

0.3

0.4

0.5

0.6

-40
-60
-80
-100
-120
Vcntp-Vcntn

Fig. 2. Delay Control Diagram

Rev. 6.5.2

3January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

POWER SUPPLY CONFIGURATION
The part can operate with either a negative supply (vcc = 0.0V = ground and vee = −3.3V), or a positivesupply (vcc = +3.3V and vee = 0.0V = ground). In case of a positive supply, all I/Os need AC termination
when connected to any devices with 50Ohm termination to ground. Different PCB layouts will be neededfor each different power supply combination.

All the characteristics detailed below assume vcc = 0.0V and vee = -3.3V.

ABSOLUTE MAXIMUM RATINGS
Caution: Exceeding the absolute maximum ratings shown in Table 1 may cause damage to this productand/or lead to reduced reliability. Functional performance is specified over the recommended operating
conditions for power supply and temperature only. AC and DC device characteristics at or beyond theabsolute maximum ratings are not assumed or implied. All min and max voltage limits are referenced toground.
Table 1. Absolute Maximum Ratings

Parameter
Supply Voltage (vee)Power Consumption
RF Input Voltage Swing (SE)
Case Temperature
Storage Temperature
Operational Humidity
Storage Humidity

Min-401010Max-3.60.67
1.0+90+1009898UnitsVW
VºCºC%%TERMINAL FUNCTIONSTERMINAL
NameNo.
Typeipinicntp
icntn
outpoutnNamevcc
veeRev. 6.5.2

DESCRIPTION

High-Speed I/Os
20
CML Differential high-speed signal inputs with internal SE 50Ohm
input termination to vcc
222
CML Differential low-speed control inputs with internal SE 50Ohm
input termination to vcc
4
10
CML Differential high-speed signal outputs with internal SE 50Ohm
output termination to vcc. Require external SE 50Ohm termination to vcc
8Supply and Termination Voltages
Description
Pin Number
Positive power supply (+3.3V or 0)
1, 3, 5, 7, 9, 11, 13, 14, 15, 16, 17, 19, 21, 23
Negative power supply (0V or -3.3V)
6, 12, 18, 24

4January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ELECTRICAL CHARACTERISTICSPARAMETER
veevccIvee
Power consumption
Junction temperature
Data Rate
Frequency
Swing
CM Voltage Level
Data Rate
Frequency
Logic “1” level
Logic “0” level
Rise/Fall times
Output Jitter
Duty cycle
Adjustment range
Adjustment range
Absolute delay stability
Bandwidth
SE voltage level
SE voltage level
Differential swing
CM LevelRev. 6.5.2

MINTYPMAX UNITCOMMENTS
General Parameters
-3.1
-3.3
-3.5
V
±6%
0.0
V
External ground
185mA
610mW
-40
25125°C
HS Input Data/Clock (ip/in)
DC17Gbps
DC14GHzFor clock signals
0.05
1.0V
Differential or SE, p-p
vcc-0.8
vcc
VMust match for both inputs
HS Output Data/Clock (outp/outn)
DC17Gbps
DC14GHzFor clock signals
Vvcc
vcc-0.4
VWith external 50Ohm DC termination
1519ps20%-80%1
ps
Peak-to-peak
455055%For clock signal
Output-to-Input Delay270
ps
At 1GHzFor the full range of255
ps
At 13GHz icntp/icntn control signals
-32
32
ps
0-125°C
Phase Shift Control port (icntp/icntn)
DC
1000
MHz
vcc-600
vcc
mV
Half control range when the opposite
pin is at vcc
vcc-1200
vccmV
Full control range when the opposite
pin is at vcc-0.6V
01200mV
Peak-peak, full control range
vcc-(Diff. swing)/4V
In differential mode

5January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

PACKAGE INFORMATIONThe chip die is housed in a standard 24-pin QFN package shown in Fig. 3. It is recommended that thecenter heat slug located on the back side of the package is soldered to the vee plain, which is ground forthe positive supply or power for the negative supply. It will help dissipate heat generated by the chipduring operation.
The part’s identification label is ASNT5175-PQC. The first 8 characters of the name before the dashidentify the bare die including general circuit family, fabrication technology, specific circuit type, and partversion while the 3 characters after the dash represent the package’s manufacturer, type, and pin outcount.
This device complies with the Restriction of Hazardous Substances (RoHS) per 2011/65/EU for all ten
substances.

ASNT5175
Fig. 3. QFN 24-Pin Package Drawing (all dimensions in mm)

Rev. 6.5.2

6January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

REVISION HISTORY
Revision
6.5.2
6.4.2
6.4.1
6.3.1

6.2.1
6.1.1
6.0.1

5.0
4.0
3.0
2.0
1.0

Rev. 6.5.2

DateChanges
01-2020 Updated Package Information
07-2019 Updated Letterhead
06-2013 Corrected title
Corrected maximum speed value
05-2013 Corrected adjustment range
Corrected power consumption
Corrected control diagram
Revised power supply configuration
Corrected electrical characteristics table03-2013 Corrected terminal functions
Corrected phase shift values
03-2013 Added delay control diagram
02-2013 Revised package pin out drawing
Revised functional block diagram
Added power supply configuration
Added absolute maximum ratings
Revised terminal functions
Revised electrical characteristics
Added package information and mechanical drawing
Format correction
10-2011 Revised electrical characteristics section
Revised packaging information section
02-2008 Revised electrical characteristics section
06-2007 Revised electrical characteristics section
04-2007 Revised terminal functions section
01-2007 First release

7

January 2020