Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ASNT5173-PQC
DC-17Gbps/13GHz Signal Phase Shifter with Amplitude Control


Broadband (DC-17Gbps/13GHz) tunable data/clock phase shifter

Delay adjustment range of 135ps

Exhibits low jitter and limited temperature variation over industrial temperature range



100MHz of bandwidth for the phase adjustment tuning ports

Fully differential CML input interfaces

Fully differential CML output interface with adjustable SE amplitude from 0 to 0.8V



1GHz of bandwidth for the amplitude adjustment tuning ports

Single +3.3V or -3.3V power supplyPower consumption: 495mW

Fabricated in SiGe for high performance, yield, and reliabilityStandard MLF/QFN 24-pin package

Rev. 6.3.2

1January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

DESCRIPTION

tnp

icntp
50
ip

50

10050
outp

TunablePhase Shiftin50100

outn
50

icntn

50
tnn

Fig. 1. Functional Block Diagram

ASNT5173-PQC is a data / clock variable delay line fabricated in SiGe technology. The IC shown in
Fig. 1 provides an adjustable delay of its differential output signal outp/outn in relation to its broadband
input signal ip/in. The delay is controlled through a wide-band differential tuning port icntp/icntn.
The part’s I/O’s support the CML logic interface with on chip 50Ohm termination to vcc and may be useddifferentially, AC/DC coupled, single-ended, or in any combination (see also POWER SUPPLYCONFIGURATION). In the DC-coupling mode, the input signal’s common mode voltage should comply
with the specifications shown in ELECTRICAL CHARACTERISTICS. In the AC-coupling mode, theinput termination provides the required common mode voltage automatically. The differential DC
signaling mode is recommended for optimal performance.
The output amplitude is controlled through a wide-band differential tuning port tnp/tnn. Due to an
extremely low jitter, the part is suitable for use in high-speed measurement / test equipment.

Delay Control PortThe delay is controlled through a wide-band differential tuning port icntp/icntn. The delay control
diagram is shown in Fig. 2.

Rev. 6.3.2

2January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Delay Adjustment in ASNT5173 (new setup)

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

9080
70
60
50
Relative Delay, ps

40
30
20
100-0.6

-0.5

-0.4

-0.3

-0.2

-0.1

-10 0

0.1

0.2

0.3

0.4

0.5

0.6

-20-30-40-50-60Vcntp-Vcntn

Fig. 2. Delay Control Diagram

Amplitude Control PortThe output amplitude is controlled through a wide-band differential tuning port tnp/tnn. The amplitude
Amplitude Adjustment in ASNT5173 (new setup)
control diagram is shown in Fig. 3.
500
450
400
Output Amplitude, mV

350
300
250
200
150
100
50
0
-0.5

-0.4

-0.3

-0.2

-0.1

00.1

0.2

0.3

0.4

0.5

Vtnp-Vtnn

Fig. 3. Amplitude Control
Average Diagram

Rev. 6.3.2

3January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

POWER SUPPLY CONFIGURATION
The part can operate with either a negative supply (vcc = 0.0V = ground and vee = −3.3V), or a positivesupply (vcc = +3.3V and vee = 0.0V = ground). In case of a positive supply, all I/Os need AC termination
when connected to any devices with 50Ohm termination to ground. Different PCB layouts will be neededfor each different power supply combination.

All the characteristics detailed below assume vcc = 0.0V and vee = -3.3V.

ABSOLUTE MAXIMUM RATINGS
Caution: Exceeding the absolute maximum ratings shown in Table 1 may cause damage to this productand/or lead to reduced reliability. Functional performance is specified over the recommended operating
conditions for power supply and temperature only. AC and DC device characteristics at or beyond theabsolute maximum ratings are not assumed or implied. All min and max voltage limits are referenced toground.
Table 1. Absolute Maximum Ratings

Parameter
Supply Voltage (vee)Power Consumption
RF Input Voltage Swing (SE)
Case Temperature
Storage TemperatureOperational Humidity
Storage Humidity

Min-401010Max-3.60.55
1.0+90+10098
98

Units
VW
VºC
ºC%%

TERMINAL FUNCTIONSTERMINAL
Name
No.
Typeipinicntp
icntn
tnp
tnn
outp
outn
Name
vcc
vee
Rev. 6.3.2

DESCRIPTION

High-Speed I/Os
Differential high-speed signal inputs with internal SE 50Ohm
termination to vcc
Differential low-speed control inputs with internal SE 100Ohm
termination to vcc
CML Differential low-speed control inputs with internal SE 50Ohm
input termination to vcc
CML Differential high-speed signal outputs with internal SE 50Ohm
output termination to vcc. Require external SE 50Ohm termination to vcc
Supply and Termination Voltages
Description
Pin Number
Positive power supply (+3.3V or 0)
1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23
Negative power supply (0V or -3.3V)
6, 12, 18, 24
20
22
24
16
14
108

CML
input
Input

4January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.comELECTRICAL CHARACTERISTICSPARAMETERveevcc
Ivee
Power consumption
Junction temperature
Data Rate
Frequency
Swing
CM Voltage Level
Data Rate
Frequency
Logic “1” level
Highest logic “0” level
Lowest logic “0” level
Rise/Fall times
Output Jitter
Duty cycle
Adjustment range
Absolute delay stability
Bandwidth
SE voltage level
SE voltage level
Differential swing
CM Level
Bandwidth
SE voltage level
SE voltage level
Differential swing
CM LevelRev. 6.3.2

MINTYPMAX UNITCOMMENTS
General Parameters
-3.1
-3.3
-3.5
V±6%0.0
V
External ground
150mA495mW-40
25125°C
HS Input Data/Clock (ip/in)
DC17Gbps
DC13GHzFor clock signals
0.05
1.0VDifferential or SE, p-p
vcc-0.8
vcc
VMust match for both inputs
HS Output Data/Clock (outp/outn)
DC17Gbps
DC13GHzFor clock signals
Vvcc
V
With external 50Ohm DC termination andvcc
full range of tnp/tnn control signal
vcc-0.55
vcc-0.43
V15
19
ps20%-80%1
ps
Peak-to-peak
455055%
For clock signal
Output-to-Input Delay
140
ps
At 1GHzFor the full range oficntp/icntn control signals
135ps
At 13GHz-1515ps
0-125°C
Phase Shift Control port (icntp/icntn)
DC
100
MHz
vcc-600
vcc
mV
Half control range when the opposite pin
is at vcc
vcc-1200
vcc
mV
Full control range when the opposite pin
is at vcc-0.6V
01200
mV
Peak-peak, full control range
vcc-(Diff. swing)/4V
In differential mode
Output Amplitude port (tnp/tnn)
DC1000MHz
vcc-500
vcc
mV
Half control range when the opposite pin
is at vcc
vcc-1000
vcc
mV
Full control range when the opposite pin
is at vcc-0.5V
01000mV
Peak-peak, full control range
vcc-(Diff. swing)/4VIn differential mode
5January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

PACKAGE INFORMATIONThe chip die is housed in a standard 24-pin QFN package shown in Fig. 4. It is recommended that thecenter heat slug located on the back side of the package is soldered to the vee plain, which is ground forthe positive supply or power for the negative supply. It will help dissipate heat generated by the chipduring operation.
The part’s identification label is ASNT5173-PQC. The first 8 characters of the name before the dashidentify the bare die including general circuit family, fabrication technology, specific circuit type, and partversion while the 3 characters after the dash represent the package’s manufacturer, type, and pin out
count.
This device complies with the Restriction of Hazardous Substances (RoHS) per 2011/65/EU for all ten
substances.

ASNT5173
Fig. 4. QFN 24-Pin Package Drawing (all dimensions in mm)

Rev. 6.3.2

6January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

REVISION HISTORY
Revision
6.3.2
6.2.2
6.2.1

6.1.1

6.0.1

5.0
4.0
3.0
2.0
1.0

Rev. 6.3.2

Date
Changes
01-2020 Updated Package Information
07-2019 Updated Letterhead
06-2013 Corrected title
Corrected control diagrams
Corrected electrical characteristics table03-2013 Corrected package pin out drawing
Revised functional block diagram
Revised description
Corrected amplitude control diagram
Corrected terminal functions
Corrected electrical characteristics
02-2013 Corrected title
Revised package pin out drawing
Revised functional block diagram
Revised description
Added delay control diagram
Added amplitude control diagram
Added power supply configuration
Added absolute maximum ratings
Revised terminal functions
Revised electrical characteristics
Added package information and mechanical drawing
Format correction
08-2009 Revised electrical characteristics section
02-2008 Revised electrical characteristics section
06-2007 Revised electrical characteristics section
04-2007 Revised terminal functions section
01-2007 First release

7

January 2020