Novel DC to Single-phase AC Isolated Current Source
Inverter with Power Decoupling Capability for
Micro-Invrter system
Hiroki Watanabe and Jun-ichi Itoh
Department of Electrical，Electronics and Information Engineering
Nagaoka University of Technology
Nagaoka, Niigata, Japanhwatanabe@stn.nagaokaut.ac.jp，itoh@vos.nagaokaut.ac.jp

Abstract— This paper discusses a circuit configuration for asingle-phase current source inverter that features power
decoupling capability. This converter consists of a resonant
type isolated DC/DC converter, power decoupling circuit, anda current source inverter (CSI). The proposed converter can beachieved the low input voltage ripple without a largesmoothing inductor or electrolytic capacitor. In this paper, thefundamental operation of the proposed circuit is confirmed bysimulation and experiment. From the simulation results, thefundamental operation is conformed. In addition, the Pulse
Density Modulation (PDM) is applied on the active buffer andinverter control. As a result, the each switching devices are
switched at zero current period. Thus, the zero current
switching is achieved. Moreover, the maximum efficiency is
93.5% when the output power is 280 W. From theexperimental results, the input voltage ripple fluctuation is
reduced by 1.2% by proposed control. In addition, the Total
Harmonic Distortion (THD) of the inverter output current is
2.9%.
Keywords- micro inverter, single-phasecompensation, zero current switching

I.

power

pulsation

INTRODUCTION

In recent years, the photovoltaics system (PV) is active
researched for energy saving. In order to supply the power
to single-phase grid, the Power conditioning system (PCS)
is used. The PCS is categorized into two types: centralized
inverter, micro-inverter [1-2]. The first type is uses overkilo-Watts capacity inverter to connect multiple numbers of
PV modules in a series connection. However, this system
has any problem. Especially, when the some solar panels arecovered by clouds, the total generating power is severely
reduced.

978-1-4673-7151-3/15/$31.00 ©2015 IEEE

On the other hand, the micro-inverter has become thetrend for future PV system. Comparing to centralized type,the micro-inverter has a lot of advantages. The PV systemwith the micro-inverter system can improve the systemefficiency. This is because the micro-inverter optimize thegenerative power using the maximum power point tracing(MPPT) to each PV modules. In addition, this system hasenhanced flexibility and modularity. Finally, the microinverter can save the installation area. In this system, thepower conversion part is integrated on the PV modules.
In order to construct the PV system with micro-inverter,
the low cost, long life-time, and miniaturization are requiredfor power converter. However, owing to the instantaneous
power fluctuation with a twice frequency of the grid, thelarge electrolytic capacitor is needed on DC link part As aresults, periodic maintenance is needed for the conventional
micro-inverter Besides, the volume of the electrolytic
capacitor dominates the total volume of the micro-inverter
In order to remove the large electrolytic capacitor, thepower decoupling methods between DC side and AC side
known as DC link active filters have been studied [3-8].
These topologies can technically reduce the capacitancevalue of the DC link capacitor. However, extra circuit isrequired in order to control the charge and discharge of thesmall capacitor.
In order to solve above mentioned problems, the authors
have proposed the DC to single-phase AC grid connection
system with the active buffer circuit based on the boost
chopper [9-10]. The active buffer circuit has a function bothboost up and single-phase power pulsation without theadditional component. However, the boost-up inductor andinterconnected inductor is required. These magnetic

Iin
C1
Vin

S1

D1 D3

LS

L1

C3

S3

S5

S7
Iac

C2

S2

D2 D4

Isolated DC/DC
converter

S4

S6

DC active filter

VSI

C4

L2

L3

C5

vac

S8

Fig.1 Single-phase AC grid connection system with conventional active power decoupling method.

components decrease the efficiency and increase the circuit
volume.
This paper proposes a novel power decoupling methodthat uses the active buffer circuit with a Current source
inverter (CSI). The active buffer circuit is simple
configuration. Moreover, a CSI is not required the reverse
blocking diode due to the freewheeling operation of theactive buffer circuit. In addition, the isolated resonance
DC/DC converter is connected as front end converter of theactive buffer circuit. In the proposed circuit, the magnetic
components are a transformer and a filter inductor only.
Thus, the volume of the main circuit become small
compared to the conventional circuit. In addition, when theeach converter is operated on the high switching frequency,
the inductance of the transformer and the filter inductor canbe reduced. However, when the switching frequency is
increase, the switching loss of the active buffer and CSI
become large. In order to solve this problem, the Pulse
density modulation (PDM) is introduced in order to achieve
to the Zero current switching (ZCS) to all switching device.
This paper is organized as follows: first, the configurationof the conventional and proposed circuit is shown. Nest, theprinciple of the power decoupling control is described. In
addition, the control block diagram for proposed circuit isexplained. In order to evaluate the fundamental operation,
the operation of the proposed circuit is demonstrated bysimulation and experiment. From the simulation result, thevoltage ripple at twice the grid frequency on the input
voltage is compensated by small capacitor. In addition, theall switching device is switched at zero current. Thus, theZCS is achieved by proposed control. Finally, the active
power decoupling and grid connected operation is
confirmed by experiment.
II.

CIRCUIT CONFIGURATION

Fig.1 shows a single-phase AC grid connection systemwith a conventional active power decoupling method [11].
The conventional circuit consist of a resonant type isolated

DC/DC converter, DC active filter, and Voltage source
inverter (VSI) [6]. The DC active filter compensates thepower ripple by the filter capacitor C4. The advantages ofthis circuit are long-lifetime and size reduction of the micro
inverter. This is because a small ceramic capacitor can beused instead of an electrolytic capacitor. However, in orderto achieve the power pulsatile compensation by a DC active
filter, the filter inductor L1 is needed. Owing to the L1, thevolume of the circuit becomes large. In addition, this circuit
uses a PWM inverter with the hard switching in which theswitching loss of the S3 to S8 increased. Moreover, the large
interconnected inductor L2 is required. These reasons, thisconventional circuit become low efficiency, and large
circuit volume. Especially, in order to achieve the active
power decoupling, the additional magnetic component isrequire generally. However, this is the cause of decreasing
efficiency.
Fig.2 shows the proposed circuit configuration. The
proposed circuit consists of a resonant type isolated DC/DC
converter, active buffer circuit and the CSI [12]. A resonant
type isolated DC/DC converter applies the ZCS control
technique to reduce the switching loss, and then the highfrequency transformer increases the input voltage Vin. The
active buffer circuit compensates the single-phase power
pulsation. Finally, the PV is connected to the single-phasegrid using the CSI.
In the proposed circuit, a capacitor for the power
decoupling can be applied the small capacitor C3 instead ofan electrolytic capacitor by the active buffer circuit. In
addition, the proposed circuit does not need the boost-up
inductor and interconnected inductor. Moreover, theswitching device in the inverter does not required reverse
blocking diode even the CSI is used. This is because thereverse current passes the S5 to D4 in the active buffer
circuit at the reverse flow period. Thus, the proposed circuit
can be small size and long-lifetime. In order to reduce theinductance of L1, the active buffer circuit and CSI isoperated on the high switching frequency.

Iin
C1

idc

S1
D1

Vin

LS

S3

S6

D3

S5

L1
C3

C2

S8

iac

C4

S7

S2

vac

S9

D4
D2

S4

Fig.2 Proposed circuit configuration.

III.

vac

vc

Vin

In order to reduce the switching loss on the active buffer
circuit and the CSI due to the high switching frequency
operation, the PDM is applied to the proposed control. The
switching devices from S3 to S9 in the secondary side will beswitched at the zero cross point of the secondary resonancecurrent idc by PDM. In other words, the all switches of the
proposed circuit achieved to the ZCS. Owing to thesereasons, the proposed circuit achieves the high efficiency
and miniaturization comparing to the conventional circuit inFig.1.

vave
Vacp
t

0

0

Iin

ic

iac

0

0

0

pbuf

pout

0

Iacp
t

PRINCIPLE OF THE POWER DECOUPLING
COMPANSATION

Pin

Fig.3 shows the principle of the power decoupling
operation between the DC and AC sides. When both the gridvoltage and the inverter output current waveforms are
sinusoidal, the instantaneous output power pout is expressedasCharge
t

0

0

t

t

0

V I
pout  acp acp (1 cos2t )2Discharge
Active buffer
Single-phasecircuitgrid
Fig.3 Compensation principle of the single-phase power pulsation.
Input side (PV)

Vacp I acp(1  cos 2t )(1)2where, Vacp is the peak grid voltage, Iacp is the peak inverter
output current, andis the angular frequency of theoutput voltage. From (1), the power ripple, that contains
twice the frequency of the power grid, appears at the DC
side. In order to absorb the power ripple, the instantaneous
power pbuf of an active buffer should be controlled bypout 

1pin  Vacp I acp  VIN I IN
2
where, Vin is the input voltage, Vin is the input current.
IV.

1pbuf  Vacp I acp cos2t2(2)where, the polarity of the pbuf is define as possible when theactive buffer discharges. Note that the mean power of theactive buffer is zero because the active buffer does not
generate the power. Due to the power decoupling, the input
power is match the output power.

(3)

CONTROL STRATEGY OF THE PROPOSED CIRCUIT

A. Operation mode for active buffer and CSI
Fig.4 shows the operation mode of the proposed circuit
when the grid voltage is the positive. Note that, the current
pathway does not occur from the grid to the buffer capacitor
C3 on the active buffer circuit. This is because the capacitor
voltage of the C3 is controlled to higher than the peak gridvoltage. The proposed circuit is controlled in four modes
based on the switching pattern in Fig. 4. In the mode 1, the

S6

S5

idc

S8

Vin_buf

vac
S7

S6

S5

idc

Vin_buf

vac

S9

S7

(S5:OFF, S6:ON, S7:OFF, S8:OFF, S9:ON)

Mode2
S6

S5

S9

(S5:OFF, S6:OFF, S7:OFF, S8:OFF, S9:ON)

Mode1

idc

S8

S8
vac

Vin_buf
S7

S6

S5

idc

S8

Vin_buf

vac

S9

S7

S9

(S5:OFF, S6:ON, S7:OFF, S8:OFF, S9:ON)(S5:ON, S6:OFF, S7:OFF, S8:OFF, S9:ON)

Mode3

Mode4
Fig.4 Operation mode of the active buffer and inverter.

input power Pin is directly supplied to the single-phase grid.
The buffer power pbuf is controlled by mode 2 and mode 3.
In the mode 2, the buffer capacitor C3 is charged. On theother hand, the buffer capacitor C3 is discharged to thesingle-phase grid. As a results, the buffer capacitor voltage
vc is fluctuated at the twice frequency of the single-phasegrid. Finally, the mode 4 is the freewheeling mode.
Owing to the mode 4, the reverse blocking diode on the
CSI is not required. According to mode 1 to mode 4, theboosting up the secondary input voltage Vdc, the active
power decoupling operation and the grid connection are
performed. Owing to the active power decoupling, the largesmoothing inductor on the DC side is not required.
B. Control block diagram for proposed circuit, dc  0
d tempo
d mode2  , dc  00 d tempo , d c  0d mode3   0, dc  0



(4)

(6)

where, vc is instantaneous voltage of buffer capacitor C3. In
addition, ic is decided by the dmode2 ， dmode3 ， and Idc.
Relationship between the duty reference and the ic isexpressed as

ic  (d mode2  d mode3) I dc

(7)

According to (6) and (7)，the dc is expressed as

Vacp I acp
2vc I dccos2t  *

Vdccos2t 
vc(8)

where, the Vdc* has to be satisfied following condition

VIN 
*

*

VIN
sin(t )  d mode3
VINp

Vacp I acp
cos(2t )
2vc

dc 

Fig 5 shows the control block diagram for the proposed
circuit. The duty reference dmode1, dmode2 and dmode3 areexpressed as

d mode1  2

ic 

Vacp
2

(9)

this is because the all duty commands should be positive
value.
(5)

where, Vdc* is the reference value of the active buffer
voltage. dc is the duty reference for the charge and dischargeof the buffer capacitor C3. On the other hand, buffer
capacitor current ic is expressed as

Owing to the each duty reference, the gate signal for S5 to S9
is generated by PDM based on Pulse width modulation(PWM).
C. PDM based on pulse width modulation
Fig.6 shows the operation principle of the PDM basedon PWM [13]. In the proposed control strategy, in order toadopt ZCS with PDM, a D flip flop (D-FF) and a zerocrossing detection signal from idc are used. First, the original
switching signals are generated by PWM. The gate signals

vac

PLL

vc
idc
Commands

Cab
VCmin
Vin*

×

Vacp



pin

2Vdc*
Vacp |sin(t)|Vdc*
vc cos(2t)

+ +
vc
d
Vacp / 2 PI

dc

Limit
0 to 1+*vc
p
VCmin  in sin(2t )  1
+
Cab
2

+

PI

-1
dPI

Limit
0 to 1

Sgn{sin(t)}

ssgn

+

s1

+

s2

+

s3

dmode1
dmode2++dmode3
1
0 Carrier++Original
switchingsignals
5

S5

Pulse Density
Moduration
(PDM)

Peak

Pulse
transform

Detectionof sensors

S6
S7
S8
S9

Fig.5 Control block diagram for proposed circuit.

S5 to S9 are synchronized with the zero-crossing signal of
the primary transformer current idc by D-FF. In the
proposed control, the zero-crossing signal is generated by
the gate signals for half bridge converter on the isolated
resonance DC/DC converter. When the half bridge
converter is achieve the ZCS, the each switching device on
the half bridge converter is switched at the zero current
point of the primary transformer current. Thus, when therising and falling edge of the gate signal is used, the zerocrossing signal of the primary transformer current isgenerated.

Switchingsignalcal.

Original
switchingsignals
D-FF
5
D Q
E
CLK

5

Gate signals for
S5 to S9

idc

Edge
detection
Zero cross signalof primary transformer current

Each MOSFET
current

CLK

Note that, the secondary current idc has a ripple
frequency component at the twice resonance frequency,
and the bottom point of the ripple current and the zerocross point of primary transformer current is nearly same.
Thus, when the switches S5 to S9 is switched at zero crosspoint of the primary side transformer current, the active
buffer circuit and the CSI can be achieve the ZCS.
Fig.7 shows the modulation method for the half bridge
converter on the isolated resonance DC/DC converter andthe synchronies rectifier circuit. The switching frequencyof the half bridge converter and the synchronies rectifier
circuit is designed in concert with the resonance frequency.
In addition, the duty reference is 50%. In the proposed
circuit, the synchronies rectifier circuit has to switch at thezero cross point of primary transformer current. This isbecause the parasitic diode cannot use the current pass ofthe secondary transformer current. When the synchronies
rectifier circuit is switched except at zero cross current, alarge surge voltage occur.
In order to solve this problem, the carrier phase shift
control is applied on the modulation part for thesynchronies rectifier circuit. Fig.8 shows the carrier phaseshift control for the synchronies rectifier circuit. When thephase of carrier is changed, the gate signal for S3 to S4 isshifted. Owing to the carrier phase shift control, theswitching timing of the synchronies rectifier circuit isadjusted at the zero cross point of the primary transformer
current.

Fig.6 Operation principle of the PDM.

PWM Modulation forthe half bridge converter

Duty
Reference
+

0

-

S1
S2

Carrier1+
Carrier2

S3
S4

PWM Modulation for thesynchronies rectifier circuit
Fig.7 Modulation method of the half bridge converter and synchronies
rectifier circuit.
Carrier1

Carrier2

Duty
Reference(Duty:50%)

Gate signal forS1 and S2
Gate signal forS3 and S4

Fig.8 Carrier phase shift for synchronies rectifier circuit.

Table.1 Simulation conditions.

94

Vin

50 V

Input current

Iin

Switchingfrequency

fsw_primary

6A
170 kHz

Trans turn ratio
Buffer capacitor
Filter capacitor
Filter inductor
Grid voltage
Grid frequency
Output power

fsw_secondaly
N1 : N2
Cbuf
Cfilter
Lfilterv_gridf_gridPout

92

80 kHz1 : 6 turn
50 mF
3.3 mF
2 mH (%Z =0.4%)
200 Vrms
50 Hz
300 W

Efficiency [%]Input voltageh93.5%

90
88
86
84
82
80
78

50

Input voltage vin[V]

100 150 200 250
Output power [W]300

Fig.10 Efficiency characteristics of the proposed circuit by simulation.
Input current iin

25[A]
Capacitor voltage vc

20

[V]

15
Loss [W]Grid voltage vac[V]
Inverter output current iac

10
5

[A]
10 ms/div(a) Input and output waveforms.
Drain-source voltage of S5 [V]0Output power :282 W

proposed circuit. In the simulation, the PDM is applied to theactive buffer circuit and CSI control.

Drain-source current of S5 [A][A]

Drain-source voltage of S8 [V][V]

Drain-source current of S8 [A][A]
1 ms/div(b) Switching waveforms.
Fig.9 Simulation results.

V.

Conduction loss ofhalf bridge converter

Fig.11 Loss analysis results.

[V]

Switching at the zero current point

Transformer
copper loss
Transformer
iron loss
Conduction lossof active buffer
and inverter
Conduction lossof rectifierFig. 9 (a) shows the input and output waveforms of the
proposed circuit with PDM. According to Fig. 9 (a), it isconfirmed that the buffer capacitor voltage is fluctuated by
active buffer circuit, and the input voltage ripple is underthan 11% by controlling the buffer power pbuf. Thus, theoperation of the power pulsatile compensation is achieved.
In addition, the output power factor is almost unity at the
rated power. However, the output current THD is 6.8%.
This is because the gate signal by the PDM based on the
PWM has the quantizing error. In order solve this problem.
The PDM based on the -conversion is applied in the
future work. The -conversion can reduce the quantizing
error. Thus, the THD of the inverter output current is
improved.

SIMULATION AND EXPERIMENT

A. Simulation results
Table 1 shows the simulation parameter. Fig. 9 shows thesimulation results and about the fundamental operation of theFig. 9 (b) shows the switching period of the active buffer
circuit and inverter by simulation results. According to Fig.9(b), S5 and S9 are switched at the zero current by proposed
method. Thus, the active buffer circuit and inverter areachieved the ZCS. Moreover, the resonant type isolated
DC/DC converter is achieved the ZCS by the resonancecapacitor C1,C2 and leakage inductance Ls. Owing to theZCS, the switching loss of the all switching devices can be
reduced.

180
160

L2

140
C5

Fig. 10 shows the efficiency characteristics of the
proposed circuit in simulation. Note that, the device
According to Fig. 10, the maximum efficiency is 93.5%
when the output power is 280 W.

Volume [cm3]

120
100
80
60

L3
L1
C4
Trans
former

L1
C4
C3

C1-C3

C1,C2

Trans
former40

Fig. 11 shows the converter loss analysis for the
proposed circuit by simulation. According to Fig. 11, themain factor of the converter loss is the conduction loss ofeach power converter. When the ZCS is applied on the all
switching device, the main loss is the transformer loss andconduction loss only. In order to improve the efficiency ofthe proposed circuit, the MOSFET with low drain-source
on-state resistance should be selected. In addition, theefficiency at the low output power decays. This is because
the influence of the iron loss on the transformer.

20
0

S1-S9，D1-D4
Proposedcircuit(fsw:30kHz)

Conventional
Circuit(fsw:30kHz)

Fig.12 Volume comparison between the VSI with a DC active filter
and a proposed circuit.
Table.2 Experimental condition
Input voltage

Vin

Input current

Iin
fsw_primary

70 V

6A
190 kHz
fsw_secondaly
48 kHzTrans turn ratio N1 : N2
1 : 6 turn
Buffer capacitor
Cbuf
50 mF
Cfilter
Filter capacitor
3.3 mF
Lfilter
Filter inductor
2 mH (%Z =0.3%)
v_gridGrid voltage
200 Vrms
Grid frequency
f_grid50 Hz
Resonance
23.4mH
Lres
inductor
Resonance
2.9pF
Cres
capacitor
Switchingfrequency

Fig. 12 shows the volume comparison between the VSI
with a DC active filter in Fig.1 and the proposed circuit.
According to the Fig. 12, the volume of the proposed circuit
is reduced by 58% in comparison with VSI with a DC active
filter. This is because the proposed circuit does not need theinterconnected connected inductor L2 and the boost-up
inductor L1. In the proposed circuit, the volume of thetransformer and output filter inductor L1 are large. In orderto reduce the volume of these components, the switchingfrequency of primary and secondary side is increase.
Proposed circuit can achieve the ZCS to the all switching
devices. Thus, the switching loss is not increased.
B. Experimental results
In order to demonstrate the validity of the proposed
circuit without the DC/DC converter, a 300 W classprototype circuit is tested. In this experiment, the PDM is
not applied. The proposed circuit is connected to the singlephase grid.

S1-S8，D1-D4

Input voltage Vin(50V/div)0

Input current Iin(5A/div)0
Grid voltage Vout(500V/div)

Table 2 shows the experimental parameter. Fig. 13
shows the experimental results with active power
decoupling control. According to Fig. 13 (a), the input
voltage and current are constant. The input voltage ripple isbelow than 1.2% by controlling the buffer power pbuf. As aresult, a single-phase power pulsatile compensation isachieved by the proposed control. In addition, the inverter
output current is sinusoidal waveform. The THD of theinverter output current is 2.9%.
Fig. 13 (b) shows the buffer capacitor voltage
waveforms. According to Fig. 13 (b), the buffer capacitor

00
Output current of inverter iac(2A/div)(a) Input and output waveforms.

5[ms/div]

voltage is fluctuated by the twice frequency of the singlephase grid by the proposed control.

5[ms/div]
Input voltage Vin(50V/div)

VI.

CONCLUSION

This paper proposed a power decoupling method thatuses the active buffer circuit with a CSI. The active buffer
circuit and CSI is simple configuration. The single-phasepower ripple is compensated the small capacitor by theactive buffer. In addition, the magnetic component is thetransformer and filter inductor only. Moreover, the all
switching devise is switched at the zero current. Thus,
switching loss is dramatically reduced. In order to evaluate
the fundamental operation, the operation of the proposed
circuit is demonstrated by simulation and experiment. Fromthe simulation results, the input voltage ripple is under than
11% by controlling the buffer power pbuf. Thus, theoperation of the power pulsatile compensation is achieved.
In addition, the all switching devise is achieved the ZCS by
PDM. And the maximum efficiency is 93.5% when the
output power is 280 W. From the experimental results, theinput voltage and current are constant. The input voltage
ripple is below than 1.2% by controlling the buffer powerpbuf. As a result, a single-phase power pulsatilecompensation is achieved by the proposed control. In
addition, the inverter output current is sinusoidal waveform.
The THD of the inverter output current is 2.9%.
In the future work, the PDM is applied to the proposed
control. In addition, the ZCS operation is considered byexperiment. Finally, the efficiency characteristics of the
proposed circuit will be estimated
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0

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