Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ASNT5071-PQC
DC-17Gbps/10GHz Phase Shifter

Broadband (DC-17Gbps/DC-10GHz) tunable data/clock phase shifter

Delay adjustment range of 320ps

Exhibits low jitter and limited temperature variation over industrial temperature range



100MHz of bandwidth for the phase adjustment tuning ports

Fully differential CML input interfaces

Fully differential CML output interface with 600mV single-ended swingSingle +3.3V or -3.3V power supplyPower consumption: 1.44W

Fabricated in SiGe for high performance, yield, and reliability

Standard MLF/QFN 24-pin package

Rev. 5.2.2

1January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

DESCRIPTION

50
ip

50
outp

TunablePhase Shiftin50

outn
50

100

100

icntp

icntn

Fig. 1. Functional Block Diagram

ASNT5071-PQC is a data / clock variable delay line fabricated in SiGe technology. The IC shown inFig. 1 provides an adjustable delay of its differential output signal outp/outn in relation to its broadband
input signal ip/in. The delay adjustment range is temperature-stabilized. The delay is controlled through awide-band differential tuning port icntp/icntn.
The part’s I/O’s support the CML logic interface with on chip 50Ohm termination to vcc and may be useddifferentially, AC/DC coupled, single-ended, or in any combination (see also POWER SUPPLYCONFIGURATION). In the DC-coupling mode, the input signal’s common mode voltage should comply
with the specifications shown in ELECTRICAL CHARACTERISTICS. In the AC-coupling mode, theinput termination provides the required common mode voltage automatically. The differential DC
signaling mode is recommended for optimal performance.
Due to an extremely low jitter, the part is suitable for use in high-speed measurement / test equipment.

Delay Control PortThe delay is controlled through a wide-band differential tuning port icntp/icntn. The simulated delay
control diagram is shown in Fig. 2.

Rev. 5.2.2

2January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

Delay Adjustment in ASNT5071 (new setup)
160

120

Relative Delay, ps80

400-0.6

-0.5

-0.4

-0.3

-0.2

-0.1

0

0.1

0.2

0.3

0.4

0.5

0.6

-40

-80

-120

-160
Vcntp-Vcntn

Fig. 2. Delay Control Diagram

Rev. 5.2.2

3

January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

POWER SUPPLY CONFIGURATION
The part can operate with either a negative supply (vcc = 0.0V = ground and vee = −3.3V), or a positivesupply (vcc = +3.3V and vee = 0.0V = ground). In case of a positive supply, all I/Os need AC termination
when connected to any devices with 50Ohm termination to ground. Different PCB layouts will be neededfor each different power supply combination.

All the characteristics detailed below assume vcc = 0.0V and vee = -3.3V.

ABSOLUTE MAXIMUM RATINGS
Caution: Exceeding the absolute maximum ratings may cause damage to this product and/or lead toreduced reliability. Functional performance is specified over the recommended operating conditions forpower supply and temperature only. AC and DC device characteristics at or beyond the absolute
maximum ratings are not assumed or implied. All min and max voltage limits are referenced to ground.
Table 1. Absolute Maximum Ratings

Parameter
Supply Voltage (vee)Power Consumption
RF Input Voltage Swing (SE)
Case Temperature
Storage Temperature
Operational Humidity
Storage Humidity

Min-401010Max
-3.6
1.58
1.0+90+1009898UnitsVW
VºCºC%%TERMINAL FUNCTIONSTERMINAL
NameNo.
TypeDESCRIPTION

Namevcc

High-Speed I/Os
20
CML Differential high-speed data/clock inputs with internal SE 50Ohm
input termination to vcc
22
2
CML Differential low-speed control inputs with internal SE 100Ohm
input termination to vcc
410
CML Differential high-speed data/clock outputs with internal SE 50Ohm
output termination to vcc. Require external SE 50Ohm termination to vcc
8Supply and Termination Voltages
Description
Pin NumberPositive power supply (+3.3V or 0)
1, 3, 5, 7, 9, 11, 13, 14, 15, 16, 17, 19, 21, 23

vee

Negative power supply (0V or -3.3V)

ipin
icntp
icntn
outp
outn

Rev. 5.2.2

6, 12, 18, 24

4January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ELECTRICAL CHARACTERISTICSPARAMETER
vee
vcc
Ivee
Power consumption
Junction temperature
Data Rate
Frequency
Swing
CM Voltage Level
Data Rate
Frequency
Logic “1” levelLogic “0” level
Rise/Fall times
Output Jitter
Duty cycle
Adjustment range
Absolute delay stability
Bandwidth
SE voltage level
SE voltage level
Differential swing
CM LevelRev. 5.2.2

MIN

TYP MAX UNIT
COMMENTS
General Parameters
-3.1
-3.3
-3.5
V
±6%
0.0
V
External ground
435mA
1435mW-4025125°C
HS Input Data/Clock (ip/in)
DC17Gbps
DC10GHzFor clock signals
0.05
1.0
V
Differential or SE, p-p
vcc-0.8
vcc
VMust match for both inputs
HS Output Data/Clock (outp/outn)
DC17Gbps
DC10GHzFor clock signals
Vvcc
vcc-0.6
V
With external 50Ohm DC termination
151719ps
20%-80%3ps
Peak-to-peak
455055%For clock signal
Output-to-Input Delay
For the full range of icntp/icntn
320ps
control signals-44
ps0-125°C
Phase Shift Control port (icntp/icntn)
DC
100
MHz
vcc-600
vccmV
Half control range when the opposite
pin is at vcc
vcc-1200
vcc
mV
Full control range when the opposite
pin is at vcc-0.6V
01200
mV
Peak-peak, full control range
vcc-(Diff. swing)/4VIn differential mode

5January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

PACKAGE INFORMATIONThe chip die is housed in a standard 24-pin QFN package shown in Fig. 3. It is recommended that thecenter heat slug located on the back side of the package is soldered to the vee plain, which is ground forthe positive supply or power for the negative supply. It will help dissipate heat generated by the chipduring operation.
The part’s identification label is ASNT5071-PQC. The first 8 characters of the name before the dashidentify the bare die including general circuit family, fabrication technology, specific circuit type, and partversion while the 3 characters after the dash represent the package’s manufacturer, type, and pin out
count.
This device complies with the Restriction of Hazardous Substances (RoHS) per 2011/65/EU for all tensubstances.

ASNT5071
Fig. 3. QFN 24-Pin Package Drawing (All Dimensions in mm)

Rev. 5.2.2

6January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505
Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

REVISION HISTORY
Revision
5.2.2
5.1.2
5.1.1

Date
01-2020
07-2019
06-2013

5.0.1

03-20134.010-2008

3.0
2.0
1.0

06-2007
04-2007
01-2007

Rev. 5.2.2

Changes
Updated Package Information
Updated Letterhead
Revised description
Corrected adjustment range
Corrected delay control diagram
Corrected electrical characteristics table
Corrected title
Revised package pin out drawing
Revised functional block diagram
Revised description
Added delay graph
Added power supply configuration
Added absolute maximum ratings
Revised terminal functions
Revised electrical characteristics
Revised package information
Added mechanical drawing
Format correction
Revised electrical characteristics section
Added packaging information section
Revised electrical characteristics section
Revised terminal functions section
First release7

January 2020