APPLICATION NOTE
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NCD(V)57000/57001Gate
Driver Design Note
AND9949/D
Introduction

The input logic signal block diagram shows in Figure 1.

The NCD(V)5700x is a high−current single channel gate
driver with internal galvanic isolation, designed for highsystem efficiency and reliability in high power applications.
Its features include complementary inputs (IN+ and IN−),
open drain fault (FLT) and ready (RDY) outputs, reset or
clear fault function (RST), active miller clamp (CLAMP),
de−saturation protection (DESAT), soft turn−off atde−saturation condition, separate source (OUTH) and sink
(OUTL) driving outputs (for NCD(V)57000 only), accurate
under voltage lock−out (UVLO), low propagation delay
90 ns (Max.) and small pulse distortion 25 ns (Max.), higher
common mode transient immunity (CMTI) withstand
100kV/us (Min.) at VCM = 1500 V condition, input signal
range covering both 5 V and 3.3 V, output differential
biasvoltage (VDD2 − VEE2) up to 25 V (Max.), with VDD2
rated to 25 V (Max.) and VEE2 rated to negative 10 V (Max).
The NCD(V)5700x provides 5 kVrms galvanic isolationand 1.2 kV working voltage capabilities at least withguaranteed 8 mm creepage distance between input andoutput. The wide−body SOIC−16 package fulfills
reinforced safety insulation requirement.
This application note describes some parameters,functions, and design tips of NCD(V)5700x in systemapplication.

VDD1

50k

0.7 x VDD1IN+

0.7 x VDD1

IN−
50k

0.3 x VDD1

0.3 x VDD1

GND1

Figure 1. Input Logic Signal Block Diagram

In order to have good signal quality and noise immunity,
an input filter RC network could be placed between
microcontroller and gate driver inputs (IN+, IN−,RST). The
RC value will depend on input frequency range, duty cycle,
and time delay according to system requirement. The
application circuit for this RC filter shows in Figure 2. This
RC filter needs to place the gate driver pin lead as near as
possible. The common mode transient noise can beinterfering from high voltage output circuit to the low
voltage input side. The input digital control inputs shouldhave low impedance signal source to prevent the glitch or
unexpected switching. The standard CMOS or push−pulldrive circuit is preferred, the open−drain configuration was
avoided.
R

Input (IN) and Output (OUT) Signal

PWM

The relation between complementary input logic signals
and output is shown in Table 1.

57000

GND

57001

IN+

IN−

OUTH

OUTL

OUT

Low

Low

Hi−Z

Low

Low

Low

High

Hi−Z

Low

Low

High

Low

High

Hi−Z

High

High

High

Hi−Z

Low

Low

Low

X

High

X

X

High

X

Low

X

X

NOTES:C

uC

Table 1. INPUT AND OUTPUT SIGNAL LOGIC

InputsGate Driver
GND1

Figure 2. RC Filter Network for Input Signals

Based on the Table 1, the function of inverting input (IN−)
can be used for input signal enable/disable when the PWM
signal is applied to non−inverting input (IN+). The example
circuit of signal enable/disable is shown in Figure 3.
This configuration is to control the output signal only, notreset function for any protections (UVLO and
De−saturation) and output follows the non−inverting signal.

X: Floating, Internal pull−down 50 kW resistor lets IN+ go to
GND1, and internal pull−up 50 kW resistor lets IN− go to VDD1.
Hi−Z: High impedance state.

© Semiconductor Components Industries, LLC, 2019

August, 2021 − Rev. 1

1

Publication Order Number:
AND9949/D

AND9949/D
PWM Input

SignalEnable Control

applications will use higher value of gate resistanceand hence, the currents will be lower than those depicted inthese curves. The power demand can be estimated for
positive and negative bias supply.

IN+

IN−

Gate Driver

Enable

4.7

Disable

VDD1

GND
5.0V / 3.3V

Figure 3. Signal Enable Control by
Inverting Input (IN−)

+

−

2.2uF

0.1uF

Gate Driver

GND1

Input Bias Supply (VDD1)

Figure 4. De−coupling Capacitors for Input
Supply Bias (VDD1)

The series resistor and de−coupling capacitor have to beplaced between VDD1 and GND1. The capacitor needs tobe as close as possible to the gate driver pin leads to filter out
any high frequency noise and sustain input bias voltage. In
general, low ESL and ESR chip capacitors (MLCC) of value
0.1 mF and 2.2 mF are placed as shown in Figure 4.
The typical input bias operation supply currents for 5.0 V
and 3.3 V conditions are shown in Figure 5 and power
demand can be estimated when 5.0 V or 3.3 V supplied.
Output Positive and Negative Bias Supply(VDD2 and VEE2)The NCD5700x series has high source and sink current
capability. This requires extra layout precautions especiallywhen external gate resistance value is small. High peakcurrent transient will be present due to internal power
MOSFETs turning−on. The de−coupling capacitors thathave to be placed between VDD2, VEE2 and GND2 need to
be as close as possible to the driver pin leads to prevent bias
voltage over and under shoot due to the parasitic inductancefrom PCB trace and package. The major current demandcomes from external load capacitance, and hence the peakcurrent depends on external gate resistance. In generalapplication, the 10 mF capacitor per each of positive(VDD2) and negative (VEE2) bias are required when thegate resistance value is large than 10 W. When the gate
resistance is small than 10 W, the 20 mF capacitor issuggested. Of course, low ESL and ESR chip capacitors(MLCC) are preferred. The example circuit is shown in
Figure 6. The typical output bias operation supply currents
function of input frequency, ambient temperature, and load
capacitance are shown in Figure 7, Figure 8 and Figure 9
accordingly.
Note that these curves represent the extreme switchingcondition with external age resistance only at 1 W. Most

Figure 5. Input Supply Current (IDD1) v.s. Input
Frequency
VDD2

Gate Driver

CVDD2+ VDD2

CVEE2

+

−

GND2

− VEE2

VEE2

Figure 6. De−coupling Capacitors for Output
Supply Bias (VDD2 and VEE2)

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2

AND9949/DPower Consumption (PD) and Junction
Temperature (TJ)

It is important to review the power dissipation of gate
driver when the external gate resistance and supply bias
value fixed. The design has to make sure that the device
maximum junction temperature is not exceeded while thedevice operates within desired temperature range. The
power dissipation equation of gate driver can be descripted
as below.
P D*total + P D*input ) P D*output(eq. 1)

Where:PD−total is total device power dissipation (W)PD−input is input bias (VDD1) power dissipation (W)PD−output is output bias (VDD2, VEE2) power
dissipation (W)Figure 7. Output Supply Current (IDD2 and IEE2)
v.s. Input Frequency

For calculation of the input bias power dissipation(PD−input ), the input supply current values provided in
Figure 5 or the maximum bias current in datasheet can beused. The equation is
P D*input + VDD1

IDD1(eq. 2)The block diagram in Figure 10 shows the output bias
power delivery path. For calculation of the output bias
power dissipation (PD−output), two factors must be
considered. First is the essential operation power demand forthe internal logic circuit and junction capacitancecharging/discharge loss of source/sink power MOSFETs.
This can be measured by no−load condition which shown in
Figure 11 with specific VDD2 and VEE2 voltage bias
condition. Second is power dissipation of the output bias is
dividing between the equivalent on−resistance of internalsource/sink power MOSFETs and external gate resistancewhen output drives the load condition.

Figure 8. Output Supply Current (IDD2 and IEE2)
v.s. Load Capacitance

Gate Driver
VDD2+
Rsource

−

CJ

VDD2

Rg

Logic
CircuitOUT

Cg
R sink

CJ
+

−

VEE2

GND2

VEE2
GND2

Figure 10. Power Delivery Path for Output Bias

Figure 9. Output Supply Current (IDD2 and IEE2)
v.s. Ambient Temperature

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AND9949/D(TA ) when maximum junction temperature, TJ(MAX) , is
150°C. Figure 12 shows this power de−rating curve when
the junction to ambient thermal resistance, ofNCD(V)5700x series based on specific PCB layout, layer,and surface area.

Figure 11. Output Supply Current (IDD2, IEE2) at
No−load v.s. Input Frequency

The equation of PD−output isP D*output + ǒP D*outputǓ

no*load) ǒP D*outputǓ

load(eq. 3)Figure 12. Power Dissipation de−rating Curve ofNCD(V) 5700x Series

Where:
ǒPD*outputǓ
ǒPD*outputǓ

Fi
Qg
RsourceRsink
Rg

no*load

load

+

1
2

+ (VDD2
Fi

Qg

IDD2) no*load ) (VEE2(VDD2 ) VEE2)ǒIEE2) no*load

R source

R source ) R g)

R sinkUnder Voltage Lockout (UVLO) and READY (RDY)Ǔ

To ensure the correct voltage in driving operation,
the input (VDD1) and output (VDD2) bias supply ismonitored by under voltage non−latch protection. WhenUVLO protection is tripped, the output signal logic will be
low immediately with less prorogation delay. The power
good (READY) signal on RDY pin indicates this UVLOs
event only and may has 8 ms (Typ.) delay time. The RDY pin
output interface is an internal open drain with pull−up 50 kW
resistor to VDD1. The block diagram of Figure 13 shows
the UVLO and RDY function. The detail timing chart isshown in datasheet already. Figures 14 and Figure 15 showthat the RDY is related to under voltage lockout protection
only.

R sink ) R g= Input Frequency= Gate Charge= Internal Source MOSFET On Resistance ^ 1W
= Internal Sink MOSFET On Resistance ^ 1W
= External Gate Resistance

The junction temperature can be estimated by
T J + P D*total

R th(JA) ) T A(eq. 4)

Where:
Rth(JA) = Junction to Ambient Thermal ResistanceTA= Ambient Temperatur
Tth(JA) = 150°C/W at 100 mm2, 1 oz Copper, 1
Surface Layer
Tth(JA) = 84°C/W at 650 mm2, 1 oz Copper, 1 Surface
Layer and 2 Internal Power Plane Layers

Gate Driver

VDD1

UVLO1
Enable3.05V (Max.)

UVLO2Enable13.5V (Typ.)Disable2.40V (Min.)Disable12.5V (Typ.)

Logic
Circuit

Logic
Circuit

VDD2

50k
+

VDD1

−

VDD2

RDY

GND1

tRDxF
8us
(Typ.)+−

GND2

Figure 13. UVLOs and RDY Functional Block
Diagram of NCD(V) 5700x Series(Eq. 4) can also be used to compute the maximum
allowable power dissipation (PD ) with ambient temperature

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4

AND9949/D
De−Saturation Protection with Soft−Turn−Off and detailtiming chart is shown in the datasheet.

Figure 14. RDY Waveform When UVLO2 Triggered
for NCD(V) 5700x Series
Figure 16. Typical Saturation Current of Internal
Sink MOSFET (Qsink)

Figure 15. FAULT Waveform When DESAT
Protection Triggered for NCD(V) 5700x Series
De−Saturation (DESAT) Protection andSoft−Turn−Off (STO)

Figure 17. Typical Saturation Current of Internal
Soft−Turn−Off MOSFET (QSTO)In order to prevent the power semiconductor device from
dissipating too much power of over current or short circuit
event, the De−saturation protection function is an effective
and low cost method to implement into gate driver. By using
power device forward characteristic property, it can bedetected when the high device current results in higher
saturation voltage or transition into active region in bipolar
device or saturation region in unipolar device. In turning off
during over current condition, high di/dt occurs if the gate
voltage is turned off rapidly as in normal switching
operation. In conjunction with the parasitic loop inductancein the power path, this produces higher turn−off dV/dt thatcan lead to overvoltage stress and potentially damage
the switch. The Soft−Turn−Off (STO) feature can reduce
the stress on the power device when DESAT protection
tripped. The extra MOSFET (STO) with lower sink current
capability in gate driver will be active in place of the normal
turn−off transistor with high sink current capability.
The gate discharge current is reduced and the gate voltage isturned−off slowly, in lower turning−off di/dt and dV/dt.
The STO function does not impact the switching loss innormal operation. The typical saturation current for sink
MOSFET and Soft−Turn−Off MOSFET are shown in
Figure 16 (sink MOSFET, QSink) and Figure 17(Soft−Turn−Off MOSFET, QSTO). Therefore, Figure 15
shows load capacitor voltage falling down slowly when
STO is active. Figure 18 is a block diagram of

VDD2
DESAT
ChargetLEB
450ns(Typ.)tFILTER
320ns(Typ.)+−

0.5mA(Typ.)DESAT

9V(Typ.)DESAT
Discharge

Logic
Circuit

GND2

STO
Gate Driver

OUT / LVEE2

Figure 18. De−Saturation Protection Diagram for
NCD(V) 5700x Series

The DESAT protection circuit still needs to avoid false
triggering for short transient time of power device
turning−on to allow the Collector/Drain voltage falling
below the DESAT threshold. This transient time duration isnamed ”DESAT Blanking Time (tBlank )”. The blanking time
is controlled by the internal constant charge current source(IDESAT−CHG ), the DESAT threshold voltage (VDESAT−THR ),and the external blanking capacitor (CB ). The blanking
capacitor discharged by DESAT discharge MOSFET when
the input signals is active to let output low and thenthe blanking time is reset for next turning−on cycle.
The typical application circuit is shown in Figure 19.

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5AND9949/D
The blanking time equation is shown in (Eq. 5) which
includes leading edge blanking and the blanking timefunction of blanking capacitance is plotted in Figure 20.
C B ǒV DESAT*THR * V D*OFFSETǓ
t Blank +) t LEBI DESAT*CHG

Where:VDESAT−THR
VD−OFFSETIDESAT−CHG
tLEB

The DESAT protection may have false trigger or
unexpected current trip out of calculation value due to cause
by some parasitic elements in this sensing loop. Figure 21
shows the junction capacitor of de−saturation block diode(CJ−DESAT ) and parasitic inductor (Lk ) in power loop whichneeds to consider in the circuit when DESAT protection
applied.

(eq. 5)= 9 V (Typ.)= 0.7 V (Typ.)

VDD2= 0.5 mA (Typ.)CJ−DESATIDESAT−CHR= 450 ns (Typ.)

RDESATDESATDDESAT

In steady state, the voltage at DESAT to GND2 is sum of
the voltage across resistor (RDESAT ), forward voltage ofdiode (DDESAT ), and saturation voltage of power device(VCE−SAT ). The tripped threshold of saturation voltage forpower device (VCE−SAT−THR ) can be arranged as
V CE*SAT*THR + V DESAT*THR * ǒI DESAT*CHG

CB
DESAT
Discharge
SwitchGate Driver

Figure 21. Consider Parasitic Elements in
De−Saturation Protection Circuit

VDD2

+

−

0.5mA
(Typ.)The mechanism of negative voltage on DESAT is caused
primarily by the discharge of CJ−DESAT. The principal of thisnegative voltage is shown in Figure 22. In QS switchoff−state, the voltage of DDESAT junction capacitance(CJ−DESAT ) is near to BUS voltage, because the DESAT
discharge switch is turned on to let DDESAT withstandthe BUS voltage. The junction capacitance has a stored
energy ECJ−DESAT = 1/2 CJ−DESAT VBUS 2. When QS isturned−on, CJ−DESAT is discharged and its energy istransferred to the blanking capacitor CB , resulting in
negative voltage across CB . If the junction capacitance hashigher value than the blanking capacitor, the negative
voltage of blanking capacitor will be higher due to moreenergy coming from the junction capacitance. This negative
voltage will be recovered quickly by IDESAT−CHG current
source until goes to positive voltage and follows
the saturation voltage of IGBT. It may add extra time delay
for De−saturation trip function that causes the higher shortcircuit peak current of IGBT, if not accounted for by
adjusting the blanking capacitor value. Figure 23 shows
the simulation result of DESAT voltage with reference to
GND2. The NCD(V)5700x series DESAT pin has been
designed to withstand up to −9 V negative voltage without
damaging the IC.

RDESAT DDESAT

DESAT

9V
(Typ.)Lk
GND2

R DESATǓ * V F*DESAT(eq. 6)DESAT
Charge

Lk
QS

QS
CB

DESAT
Discharge

GND2

Gate Driver

Figure 19. Typical De−Saturation Protection
Application Circuit

Figure 20. Blanking Time (tBlank ) as a Function of
Blanking Capacitance (CB) for NCD(V) 5700x Series

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6

AND9949/D
VCJ(0) = VBUS
+
− C

VDD2

J−DESATIDESAT−CHR

RDESATDESATDDESAT−
CB VCB(0)
Vge
+
DESAT
Discharge
SwitchLk
QS

Vce
dVce/dt

0V

Lk

GND2

Gate Driver

Figure 25. DESAT Waveform (Simulated) withProtection Diode during Qs Turn−on

Figure 22. When the Qs Turning−on and DESAT
Discharge Switch Turned−off

Table 2. DE−SATURATION PROTECTION BLOCKDIODE (D−DESAT)Part Number

VRRM(V)IF(AV) (A)TRR (ns)

PackgeNHP160SF

600

1

50

SOD123−FL

ES1JAF

600

135

SMA−FL

US2KA

800

1.5

75

SMA

US2MA

1000

1.5

75

SMA

Table 3. PROTECTION DIODE (Dp )Figure 23. DESAT Waveform (Simulated) during
Qs Turn−on

If an external negative voltage protection is desired,a protection diode Dp can be paralleled with blanking
capacitor. This diode can limit the negative voltage andthe time delay can be improved. Figures 24 and Figure 25
are shown the circuit and simulation result with protection
diode. Based on this analysis, the De−Saturation block diode(DDESAT ) should have a low junction capacitance value
and fast reverse recovery performance. The protection
diode (Dp ) should have a low forward voltage and low
leakage current. Suggested diodes for DDESAT and Dp are
listed in Table 2 and Table 3.

− CJ−DESAT +
DESAT

CB
DESAT
Discharge
Switch

DP

Lk
QS

Vce

Vge
0V

IF(AV) (A)IR (mA)

PackgeNHP120SF

200

1

10

SOD123−FL

MBR1H100SF

100

1

250

SOD123−FL

NRVBSS13HE

60

1

300

SOD323−HE

The leakage current at VR < 20 V, Ta = 125°C or 150°C

When the protection diode is placed, the impact of extra
junction capacitance and leakage current on blanking timeneeds to be considered. The power path parasitic inductancewill produce high frequency voltage (VLk ) based onthe −dIc /dt coming at the condition of reverse recovery
current of power rectifier or IGBT turning−off. This highfrequency noise could inject into gate driver via the
De−Saturation pin and GND2. The De−Saturation resistor(RDESAT ) can suppress this to let this noise current goes topower loop, not into sensing loop if the resistance value large
enough. In general, around 1 kW and 2.2 W for RDESAT aresuggested. It also can have two De−Saturation block diodes
to reduce the total junction capacitance if the higher dVCE /dt
or dVds/dt are created by using fast switching speed powerdevices. Certainly, the tripped threshold voltage will bechanged if the resultant forward voltage on
the De−Saturation block diodes and De−Saturation resistor
is higher. The suggestion application circuit is shown in
Figure 26.

RDESAT
DDESAT

VRRM(V)

NOTE:

VDD2
IDESAT−CHR

Part Number

dVce/dt

Lk

GND2

Gate Driver

Figure 24. With the Protection Diode (Dp ) between
DESAT and GND2

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7AND9949/D
base resistor value helps achieve higher drive current, it stillneeds to be high enough to limit the base current in
Desaturation condition. In this trade off, the Soft−Turn−Off
may not be able to suppress the overvoltage spike
sufficiently during the short circuit condition. Figure 29
shows the current path in normal operationand Soft−Turn−Off when DESAT active.

VDD2
Enhace the Noise
Immunity

IDESAT−CHR

RDESAT = 1k

Reduce the Junction
Capacitance

DESAT

−

DDESAT
Solve the Negative
Voltage on DESAT

CB

DESAT
Discharge
SwitchQS

Lk VLk+IC

DP−

Enhace the Noise
Immunity

Lk VLk+

RDESAT = 2.2

VDD2

QSource

Gate Driver

GND2

QH

CVDD2

Gate Driver
Normal Operation

Figure 26. Suggested Application Circuit for
Improved De−Saturation Protection

RB

Rg

QS

OUT / L

QSTO

DESAT
Active

The ideal diagram of DESAT voltage waveformand blanking time design concept is shown in Figure 27.
The sum of blanking and filter time has to be less than the
short circuit capability duration time of power device thatprevent to stress the reliability life time, and blanking timeshould be more than power device’s collector/drain voltage
falling down duration in normal operation to prevent any
false triggered.

QSink
CVEE2

QL

VEE2

Figure 28. Typical Application Circuit of External
BJT Buffer
IB in DESAT Active
IC in DESAT Active

IC in Normal Operation

VDD2

QSource

Gate Driver

STO Logic Singal

QH

CVDD2

t

OUT/HLogic Singal

External BJT
BufferNormal Operation

RB

Rg

QS

OUT / L

QSTO

DESAT
Activet

VCE(t)

QSink
CVEE2

VBUS

QL

VEE2

De-saturation

VCE(SAT)VDESAT(t)Figure 29. Sinking Current Path for Normal
Operation and DESAT ActivettBlanktFILTERIn order to reduce the base current, an extra RC network
can produce a voltage between the base resistor and OUT/L
node. This extra voltage node can reduce the base current in
DESAT condition and prevent the PNP BJT (QL) from goingto hard saturation and allowing it to turn−on slowly.
The schematic of extra RC network is shown in Figure 30.
The approximate equation of voltage and current can be
written as below.

VDESAT-THR

VD-OFFSETt
VCE Falling Time < Blankt

andtBlank+ tFILTER < SC Time

Figure 27. De−Saturation Waveform (VDESAT )Diagram and Blanking Time Design Concept*t

V x(t) [ V CEXConsidering the Soft−Turn−Off (STO) with External
BJT Buffer

The external BJT buffer for boosting the drive current isused widely to drive higher current power semiconductor
devices with large gate charges. In order to have higher
driving current from buffer, the DC gain of BJT needs to behigh. In addition, high base current is provided for the buffer
by use of lower value base resistor (RB). A typicalapplication circuit is shown in Figure 28 which includes
the internal power switch and the STO switch. While lower

I B(t) [(0) @ e ǒR EX)RSTOǓ@CEX @R STOR STO ) R EX

V Cies(0) * V BE * V x(t) * (* VEE2)
R g(b ) 1) ) R B ) R STOWhile
REX << RB and RSTO
RSTO = Internal STO MOSFET On Resistance≅ 200W
Vcies(0) ≈ Vx(t) ≈ VDD2

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8(eq. 7)(eq. 8)

AND9949/D
Considering the BJT operates in Active Mode Region
Gate Driver

VDD2

QH

CVDD2
I(t)

IB(t)

+

REX

VX(t)

CEX
VCEX(0)RB

Rg

OUT / L

DESAT
Active

QSTO
CVEE2

−

V

IEX(t)+

Cies(0)

−

QL

VEE2

Figure 30. Typical Application Circuit of External
BJT Buffer

Figure 32. Output and Load Voltage Waveforms
without RC Network when DESAT Active

The REX is derived considering the current stress ofsource/sink MOSFET in gate driver IC. It needs to be
a compromise between current stress and Vx (t). Usually,
the REX value should be less RB or equal to RB . The CEX
value is derived considering the power dissipation of REX
and still needs to have enough time constant that lets Vx (t)decay slowly. If CEX is higher, the Soft−Turn−Off (STO) will
be achieved more easily. In general, the REX will be fixedthen let CEX be adjustable to make IGBT soft turning−off inshort circuit condition.
The example circuit with extra RC network (REX and CEX )with external BJT buffer is shown in Figure 31.
The comparison waveforms are shown in Figure 32(without the RC network) and Figure 33 (with RC network).
These RC waveforms demonstrate of the RC network has
the effect of producing a Soft−Turn−Off waveform at
the IGBT gate in DESAT condition. The RC network should
be designed so that there is no impact on the driving innormal operation. Figure 34 and Figure 35 show that withthe chosen value of REX and CEX , the RC network doesn’t
affect the turning−on rise time, Figure 36 and Figure 37
show the same outcome for turning−off fall time.

Figure 33. Output and Load Voltage Waveforms
with RC Network when DESAT Active

VDD2

QH

CVDD2

NSS60601

Gate Driver

RB

Rg

22

1

OUT / L

CVEE2

2

REX

2.2nF

CEX

QL

NSS60600

10nF

Figure 34. Output and Load Voltage Waveforms
without RC Network at Turning−On

CL

VEE2

Figure 31. Typical Application Circuit of External
BJT Buffer

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9AND9949/D
Figure 38 shows a typical schematic of an isolation
converter output with Zener Split Voltage Regulator.

+

DREC
ZD

CVDD
-

COUT

+
RB

CVEE
-

Figure 38. Typical Circuit of Zener Split Voltage
Regulator

Figure 35. Output and Load Voltage Waveformwith RC Network at Turning−On

The positive bias supplies the VDD2 and negative bias
supplies the VEE2 of gate driver. The VDD2 voltage isclamped by Zener breakdown voltage of Zener diodeand VEE2 voltage will be remaining from total DC output
voltage. According to this, the Zener diode has tobreakdown to sustain the positive voltage of VDD2 upon allof loading current range, otherwise the positive and negative
voltage cannot be sustained as expectation and swing up anddown that results UVLO tripped in risk. The equivalentcircuit is shown in Figure 39.
The positive and negative bias supply current (IDD2and IEE2 ) of NCD(V)5700x series has already shown in
Figure 7 and Figure 8 with difference input signal frequency
and load capacitance. It can be converted to equivalent load
resistance for positive and negative bias RL(VDD2) , RL(VEE2) .
In order to make sure the Zener diode breakdown, the bias
resistance will be equal as below equation.

Figure 36. Output and Load Voltage Waveform without
RC Network at Turning−Off+

VDD2 = VZD
VDC

+

+
ZD CVDDIDD2

RL(VDD2)IEE2RL(VEE2)

-

COUT

+

VEE2

+
RB

CVEE

-

-

Figure 39. The Equivalent Circuit of Zener Split
Voltage Regulator
Figure 37. Output and Load Voltage Waveformwith RC Network at Turning−Off

RB t

R L(VDD2) @ R L(VEE2) @ ǒV ZD * V DCǓ(eq. 9)V DC @ R L(VDD2) * V ZD @ ǒR L(VDD2) ) R L(VEE2)Ǔ

While
RL(VDD2) = equalvent load resistance of VDD2RL(VEE2) = equalvent load resistance of VEE2
VDC = VDD2 + VEE2

Zener Split Voltage Regulator for Bias Supply

The Zener Split Voltage Regulator is widely used inapplications as a cost effective solution for biasing the gate
drivers because it reduces the winding in transformer
and reduce components. It can generate positive andnegative bias voltage from unipolar voltage for driver bias
requirements (which include negative bias VEE2).

P ZD u V DD2

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10

V EE2
RB

(eq. 10)

AND9949/D
P RB uǒV EE2Ǔ2
RB

Gate DriverPart Number

VZD(V)PD (W)IZM (mA)

Packge

1SMA5929B

15.0

1.5

100

SMA

1SMB5929B

15.0

3

100

SMB

1N5352B

15.0

5

315

Axial−Lead

1SMB5930B

16.0

1.5
3

94
93

5

295

Axial−Lead

1SMA5932B

20.0

1.5

75

SMA

1SMB5932B

20.0

3

75

SMB

1N5357B

20.0

5

237

Axial−Lead

1SMA5933B

22.0

1.5

68

SMA

1SMB5933B

22.0

3

68

SMB

1N5358B

22.0

5

216

Axial−LeadCies

Rg(on)OUT H

Lk(DR)

Lk(PKG)

Logic
CircuitQS

GND2

Lk(PKG)

Icircuiting

Rg(off)Cies

Vge > VDD2 +
−

OUT L

QSink

Le(PKG)
CVEE2
Lk(PKG)
VEE2

Figure 40. The Circuiting Current Path in Positive
di/dt−
VLe(PKG)+

di/dt

Gate Driver

Lk(PKG)

Lk(DR)VDD2

QSourceResonant

CVDD2
Lk(PKG)

SMB

16.0

Resonant

CVDD2
Lk(PKG)

SMA

1N5353B

NOTE:

Lk(DR)VDD2

Table 4. ZENER DIODE (ZD)

16.0

Lk(PKG)
QSource

Zener voltage (VZD ) of Zener diode needs to consider
the tolerance shift with temperature. The maximum DC
Zener current (IZM ) should be concerned when bias
resistance RB determined. The power dissipation limited of
Zener Diode and RB must be considered. The device
tolerance should be considered to sustain the VDD2 > VZD
enough. The power rating of Zener Diode and bias resistancecan be knew and the recommendation of Zener Diode shownin Table 4.

1SMA5930B+
VLe(PKG)−

di/dt(eq. 11)

Cies

Rg(on)OUT H

Lk(DR)

Lk(PKG)

Logic
CircuitQS

GND2

Lk(PKG)

Rg(off)
OUT L

QSink

Vge > VEE2 −+Icircuiting

Cies
Le(PKG)

CVEE2
Lk(PKG)
VEE2

Figure 41. The Circuiting Current Path in Negativedi/dt

The Zener breakdown is typical value and defined atroom temperature.

DC(VDD2) can susitan that the Vge equals VDD2 in SC condition toprevent the higher peak SC current occured.
Gate Driver

NRVBSS16HE (SBD, 60V / 1A, SOD−323)
DC(VDD2)

Lk(PKG)

Connected to gate terminal by low impedance trace

VDD2

Clamping Diode in Gate Driving Circuit

QSource

The parasitic inductance in power loop and driving loop
is not easy to avoid due to layout placement and device
package. The higher di/dt will be occurred no matter indriving loop by higher peak driving current or in power loop
by power device current. This higher di/dt will produce
higher dv/dt by parasitic inductance (Lk) and this fasttransient voltage could be higher positive bias (VDD2 ) or
lower than negative bias (VEE2 ) that results in the highfrequency circuiting current into gate driver. The highfrequency circuiting current path shows in Figure 40 if
positive di/dt comes and Figure 41 if negative di/dt comes.
The suggestion of clamping diode was added as shown in
Figure 42. The high frequency circuiting current can passthrough to bias capacitor directly, not go to gate driver.
Besides, the positive clamping diode (DC(VDD2) ) can sustainthat gate voltage of IGBT equals bias voltage to preventthe gate voltage rise−up and results in higher peak shortcircuit current in short circuit condition.

CVDD2

Icircuiting at (di/dt)
Rg(on)

Lk(PKG)OUT H

Lk(DR)

Lk(PKG)

Logic
CircuitQS

GND2

Lk(PKG)

Rg(off)

Cies

OUT L

Icircuiting at (−di/dt)

QSink

Le(PKG)

CVEE2
Lk(PKG)
VEE2

Connected to gate terminal by low impedance trace

DC(VEE2)

NRVBSS16HE (SBD, 60V / 1A, SOD−323)

Figure 42. The Circuiting Current Path in Negative
di/dt
Layout and Placement Consideration

In order to has good noise immunity and stable operation,
the layout and placement have to consider in application
when using gate driver. The driving current path of

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11

AND9949/D
turning−on and turning−off are shown in Figure 43. It shows
the major driving loop from gate driver to power device.
The driving loop should as small as possible and lower
impedance to reduce stray inductance of the loop. This highdriving current path is via the bias capacitors and internal
MOSFET to IGBT gate only. The bias capacitor needs to beplaced as near VDD2 and VEE2 of gate driver pin lead.
The return path has a low impedance trace or plane toconnect emitter of IGBT.
Considering a good quality De−Saturation sensing, highdV/dt and dI/dt cross talk noise prevention is importantly inhigh power application. The De−saturation sensing loop
and driving loop should be spilt which can to avoid the crosstalk noise into. Figure 44 shows the schematic that is
separated the signal bias capacitor CVDD2(S) , CVEE2(S)and driving bias capacitor CVDD2(P) , CVEE2(P) by groundresistor RGND . This individual sensing trace from IGBT
collector to emitter can have a good noise immunity for
De−saturation protection. The suggestion of signal
capacitors value CVDD2(S) and CVEE2(S) are 1.0 mF at least,
driving capacitor value CVDD2(P) and CVEE2(P) are 10 mF atleast, and ground resistor value RGND is 4.7W above.
The recommendation layout and placement concepts areshown in Figure 45 (without BJT buffer) and Figure 46(with BJT buffer).

VDD2

QSource
CVDD2Turing−on Loop
Rg(on)

OUT H

Logic
CircuitIcharging

QS

Rg(off)

Cies

GND2

OUT L

QSink
CVEE2

Idischarging
Turing−off Loop

VEE2

Figure 43. Driving Current Path for Turning−on
and Turning−off
RDESAT

DDESAT

DESAT

CBlank
VDD2

As short and wide as possible,
no through hole conntact(< 0.5cm from cap to VDD2 pin)

QSource
CVDD2(S)CVDD2(P)Rg(on)

OUT H

RGND

Logic
Circuit

GND2

QS
P(GND)

S(GND)

Rg(off)

Cies

OUT L

QSink
CVEE2(S)VEE2

RDESATCVEE2(P)As short and wide as possible,
no through hole conntact(< 0.5cm from cap to VEE2 pin)

Figure 44. Schematic of Signal and Driving Loop
Split

Figure 45. Layout and Placement Concept (without BJT Buffer)www.onsemi.com
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AND9949/D

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