Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ASNT5106-PQC
DC-28Gbps/18GHz Signal Phase Shifter
Broadband tunable data/clock phase shifter

Manual control of power consumption / operational speed

1GHz of bandwidth for the phase adjustment tuning port

Automatic temperature and process corner delay compensation with manual override

Duty cycle distortion compensation with adjustable gain

Manual internal peaking control



Fully differential CML input interface

Fully differential CML output interface

Single +3.3V or -3.3V power supply

Fabricated in SiGe for high performance, yield, and reliability

Standard MLF/QFN 24-pin package

Rev. 1.3.2efcrl

1716 15 14 13
12vcc

vcc

18

vcc

vee

fbcrl

vcc

21

10inn

22

ASNT5106 9outp
vcc

vcc

23

8outn

vee

24

7

vcc

1

2

3

1

4

5

6icrl

vcc

vcc

11

icntn

20

nc

inp

icntp

19

vcc

vcc

vee

January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

DESCRIPTION
efcrl

fbcrl

5050

inpoutp

TunablePhase Shiftinn50

outn
505050

icntp

icntnFig. 1. Functional Block Diagram

ASNT5106-PQC is a data/clock variable delay line with an advanced control system fabricated in SiGetechnology. The IC shown in Fig. 1 provides an adjustable delay of its differential output signal
outp/outn in relation to its broadband input signal inp/inn. The delay is controlled through a wide-banddifferential tuning port icntp/icntn. The chip incorporates an automatic common-mode offset cancellation
circuit that operates with either clock signals or data signals with balanced patterns. In case of nonbalanced data patterns, the circuit should be disabled through a control port fbcrl. The single-ended
control port efcrl can be used to manipulate internal peaking in the delay block in order to adjust thepart’s frequency response and thus improve output eye diagrams for various data rates and operatingconditions.
The part’s I/Os support the CML logic interface with on chip 50Ohm termination to vcc and may be useddifferentially, AC/DC coupled, single-ended, or in any combination (see also POWER SUPPLYCONFIGURATION). In the DC-coupling mode, the input signal’s common mode voltage should comply
with the specifications shown in ELECTRICAL CHARACTERISTICS. In the AC-coupling mode, theinput termination provides the required common mode voltage automatically. The differential DC
signaling mode is recommended for optimal performance.
The part’s power consumption can be adjusted between its minimum (default) and maximum values usinga single-ended analog control port icrl. It should be noted that higher power leads to higher operational
speed of the part.
Due to an extremely low jitter, the part is suitable for use in high-speed measurement / test equipment.

Delay Control PortThe delay is controlled through a wide-band differential tuning port icntp/icntn. This part's delay control
system was designed to minimize output jitter and increase the control function linearity. To achieve thegoals, the control system is split so that each delay stage has its own control buffer. Only three stages
Rev. 1.3.2

2January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

operate in interpolation mode at any delay position, and all the other stages are fully switched either to theshort path or to the long path.
The measured diagram of ASNT5106
phase delayDelayversusvs.thedifference
between
icntp and icntn for nominal
Phase
Control
Voltageconditions is shown in Fig. 2.
150

100

Phase Delay, ps

500-50-100-150-0.5-0.4-0.3-0.2-0.1

00.1

0.2

0.3

0.4

0.5

icntp-icntn, VFig. 2. Delay Control Diagram

Feedback Gain Control PortThis part has two duty cycle correction feedback loops. In case of feedback malfunction, currents inside
feedback amplifiers can be manually adjusted or completely shut down through a single-ended tuning port
fbcrl. The simulated dependence of feedback reference current on the control voltage is shown in Fig. 3.
Higher feedback amplifier currents result in higher feedback gain and lower stability. If the port is left notconnected, it defaults to an internal level of vcc-0.66V, the feedback current is half its maximum value
and the phase shifter is in normal operating mode.

Fig. 3 Simulated Internal Feedback Current vs. Control Voltage

Rev. 1.3.2

3January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
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Internal Peaking Control Port
Depending on the data rate and operational conditions, the output eye diagram may get distorted becauseof jitter caused by parasitic internal peaking. Internal peaking can be adjusted by varying currents ofinternal emitter followers through a single-ended port efcrl. The simulated dependence of reference
current of internal emitter followers on the control voltage is shown in Fig. 4. If this port is left notconnected, it defaults to an internal level of vcc-0.66V and emitter follower currents are half of theirmaximum values and the circuit is in normal operating mode.

Fig. 4. Simulated Internal EF Reference Current vs. Control Voltage

POWER SUPPLY CONFIGURATION
The part can operate with either a negative supply (vcc = 0.0V=ground), or a positive supply (vee =0.0V=ground). In case of the positive supply, all I/Os need AC termination when connected to any devices
with 50Ohm termination to ground. Different PCB layouts will be needed for each different power supply
combination.
The part’s power consumption can be adjusted between its minimum and maximum values using a singleended analog control port icrl. Higher voltages at the control input correspond to higher power
consumption. With the non-connected control port, the part defaults to minimum power consumption. Itshould be noted that higher power consumption leads to higher operational speed of the part as detailed inELECTRICAL CHARACTERISTICS.

All the characteristics detailed below assume vcc = 0.0V.

Rev. 1.3.2

4January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
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ABSOLUTE MAXIMUM RATINGS
Caution: Exceeding the absolute maximum ratings shown in Table 1 may cause damage to this productand/or lead to reduced reliability. Functional performance is specified over the recommended operating
conditions for power supply and temperature only. AC and DC device characteristics at or beyond theabsolute maximum ratings are not assumed or implied. All min and max voltage limits are referenced toground (assumed vcc).
Table 1. Absolute Maximum Ratings

Parameter
Supply Voltage (vee)Power Consumption
RF Input Voltage Swing (SE)
Case Temperature
Storage Temperature
Operational Humidity
Storage Humidity

Min-401010Max-3.6
1.7
1.0+90+1009898

UnitsVWVºCºC%%TERMINAL FUNCTIONSTERMINAL
Name
No.
Typeinpinn
icntp
icntn
icrl
fbcrl
efcrl
outpoutn
Namevccveenc

Rev. 1.3.2

DESCRIPTION

High-Speed I/Os
20
CML Differential high-speed signal inputs with internal SE 50Ohm
input termination to vcc
222
input Differential control input with internal SE 50Ohm terminations to4
input vcc
6
input SE DC analog control input with internal 11.5KOhm termination
to vee14input SE DC control input terminated to internal resistive divider
16input between vee and vcc
10
CML Differential high-speed signal outputs with internal SE 50Ohm
output termination to vcc. Require external SE 50Ohm termination to vcc
8
Supply And Termination Voltages
Description
Pin Number
Positive power supply. (+3.3V or 0)
1, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23
Negative power supply. (0V or -3.3V)
12, 18, 24
Not connected
35January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.comELECTRICAL CHARACTERISTICSPARAMETERveevcc
Ivee
Power consumption
Junction temperature
Data Rate
Frequency
Swing
CM Voltage Level
Data Rate
Frequency
Logic “1” level
Logic “0” level
Rise/Fall times
Output Jitter
Duty cycle
Phase shift
Phase shift stability
Absolute delay stability
Bandwidth
Control voltage range
Control voltage range
Control voltage range
Control voltage range

Rev. 1.3.2

MIN

TYP MAX UNIT
COMMENTS
General Parameters
-3.1
-3.3
-3.5
V
±6%
0.0V
External ground327440mA
Adjustable
1080
1450mW
Adjustable-2550125°C
HS Input Data/Clock (inp/inn)
DC
28
Gbps
DC16GHzAt minimum power consumption
DC18GHzAt maximum power consumption
0.05
1.0
V
Differential or SE, p-p
vcc-0.8
vcc
VMust match for both inputs
HS Output Data/Clock (outp/outn)
DC
28GbpsDC
16
GHz
At minimum power consumption
DC18
GHz
At maximum power consumption
Vvcc
vcc-0.44
V
With external 50Ohm DC termination.
1113
ps
20%-80%3.5
ps
For PRBS input, peak-to-peak
455055%For clock signal
Output-to-Input Delay
For the full range of phadj control0290
pssignal-1010
ps
0-125°C junction temperature-2525
ps0-125°C junction temperature
Tuning port (icntp/icntn)
DC1000MHz
vcc-1000
vcc
mV
Default voltage is vcc
Tuning port (icrl)
mV
Default voltage is veevee
vcc
Tuning port (fbcrl)
vcc-1300
vcc
mV
Default voltage is vcc-0.66V
Tuning port (efcrl)
vcc-1300
vcc
mV
Default voltage is vcc-0.66V

6January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

PACKAGE INFORMATIONThe chip die is housed in a custom 24-pin CQFP package shown in Fig. 5. It is recommended that thecenter heat slug located on the back side of the package is soldered to the vee plain that is ground for thepositive supply or power for the negative supply.

Fig. 5. QFN 24-Pin Package Drawing (All Dimensions in mm)

The part’s identification label is ASNT5106-PQC. The first 8 characters of the name before the dashidentify the bare die including general circuit family, fabrication technology, specific circuit type, and partversion while the 3 characters after the dash represent the package’s manufacturer, type, and pin outcount.
This device complies with the Restriction of Hazardous Substances (RoHS) per 2011/65/EU for all ten
substances.

Rev. 1.3.2

7January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

REVISION HISTORY
Revision
1.3.2
1.2.2
1.2.1
1.1.1
1.0.1

Rev. 1.3.2

Date01-2020
07-2019
01-2018
09-2017
09-2017

Changes
Updated Package Information
Updated Letterhead
Added measured delay control diagram
Package information correction
Initial release

8January 2020