Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ASNT5105A-KMC
DC-50Gbps/32GHz Signal Phase Shifter

Manual frequency response adjustment for jitter minimization



Limited temperature variation over industrial temperature range



1GHz of bandwidth for the phase adjustment tuning port

Fully differential CML input interface

Fully differential CML output interface with 450mV single-ended swingSingle +3.3V or -3.3V power supplyPower consumption: 1.25WFabricated in SiGe for high performance, yield, and reliability

Custom CQFP 24-pin packageveeOn-chip automatic common mode offset compensation circuitry

vcc

fbcrlDelay adjustment range up to 110ps

vcc

efcrlBroadband (DC-50Gbps / 32GHz) tunable data / clock phase shifter

vcc



vee

vcc

vcc

inpoutp

ASNT5105A

vcc

vcc

innoutn

vcc

vcc

Rev. 1.3.2

1vcc

icntn

vcc

icntp

vcc

vee

vee

January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

DESCRIPTION
efcrl

fbcrl

5050

inpoutp

TunablePhase Shiftinn50

outn
50

50

50

icntp

icntn

Fig. 1. Functional Block Diagram

ASNT5105A-KMC is a data/clock variable delay line fabricated in SiGe technology. The IC shown inFig. 1 provides an adjustable delay of its differential output signal outp/outn in relation to its broadband
input signal inp/inn. The delay is controlled through a wide-band differential tuning port icntp/icntn. The
chip incorporates an automatic common-mode offset cancellation circuit that operates with either clock
signals or data signals with balanced patterns. In case of non-balanced data patterns, the circuit should bedisabled through control port fbcrl. The single-ended control port efcrl can be used to manipulate internal
peaking in the delay block in order to adjust the part’s frequency response and thus improve output eye
diagrams for various data rates and operating conditions.
The part’s I/Os support the CML logic interface with on chip 50Ohm termination to vcc and may be useddifferentially, AC/DC coupled, single-ended, or in any combination (see also POWER SUPPLYCONFIGURATION). In the DC-coupling mode, the input signal’s common mode voltage should comply
with the specifications shown in ELECTRICAL CHARACTERISTICS. In the AC-coupling mode, theinput termination provides the required common mode voltage automatically. The differential DC
signaling mode is recommended for optimal performance.

Feedback Control PortThis part has two internal duty cycle correction feedback loops. In case of non-balanced data pattern witha different average numbers of logic “0”s and logic “1”s, the feedbacks may be set to lower gain or
disabled completely. This is achieved by adjustment of currents inside feedback amplifiers through singleended tuning port fbcrl. Higher control voltages result in higher amplifier currents and higher total
feedback gain. If the port is left not connected, it defaults to vcc that corresponds to the maximum
feedback gain.
For normal operation with either a balanced data or clock signal, fbcrl should be left not connected orconnected to vcc. For normal operation with a non-balanced code, fbcrl should be connected to vee.
Rev. 1.3.2

2January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

Internal Peaking Control Port
Depending on the data rate and operational conditions, excessive peaking in the internal delay stages maylead to output signal degradation that results, for example, in additional jitter. At the same time,insufficient peaking may lead to the part’s speed degradation. Internal peaking can be adjusted by varying
currents of internal emitter followers through a single-ended port efcrl. Higher control voltages result inhigher emitter follower currents, and higher internal peaking. If this port is left not connected, it defaults
to an internal level of vcc-0.75V that corresponds to a medium level of peaking.
Generally, lower control voltages result in lower jitter and lower speed. Thus, higher input data rates
require higher efcrl voltage levels as shown in Table 1 for sinusoidal input signal.
Table 1. Recommended efcrl Settings for Sinusoidal Input Signal

F input, GHz Min voltage, V Max voltage, V<24vcc-0.72
vcc
24-26
vcc-0.72
vcc
26-28
vcc-0.6
vcc
28-29
vcc-0.6
vcc>29vcc-0.4
vcc

Delay Control PortThe delay is controlled through a wide-band differential tuning port icntp/icntn. The measured delay
ASNT5105 Delay vs. Phase Control Voltage
control diagram is shown in Fig. 2.
7060
5040Phase Delay, ps30
20100-10-20-30-40
-50
-0.5

-0.4

-0.3

-0.2

-0.1

00.1

0.20.30.4

0.5

icntp-icntn, V

Fig. 2. Measured Delay Control Diagram

Rev. 1.3.2

3January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

POWER SUPPLY CONFIGURATION
The part can operate with either a negative supply (vcc = 0.0V=ground and vee = -3.3V), or a positivesupply (vcc = +3.3V and vee = 0.0V=ground). In case of the positive supply, all I/Os need ACtermination when connected to any devices with 50Ohm termination to ground. Different PCB layouts
will be needed for each different power supply combination.

All the characteristics detailed below assume vcc = 0.0V and vee = -3.3V.

ABSOLUTE MAXIMUM RATINGS
Caution: Exceeding the absolute maximum ratings shown in Table 2 may cause damage to this productand/or lead to reduced reliability. Functional performance is specified over the recommended operating
conditions for power supply and temperature only. AC and DC device characteristics at or beyond theabsolute maximum ratings are not assumed or implied. All min and max voltage limits are referenced toground (assumed vcc).
Table 2. Absolute Maximum Ratings

Parameter
Supply Voltage (vee)Power Consumption
RF Input Voltage Swing (SE)
Case Temperature
Storage Temperature
Operational Humidity
Storage Humidity

Min-401010Max
-3.6
1.4
1.0
+90+100
98
98

Units
VW
VºC
ºC
%%

TERMINAL FUNCTIONSTERMINAL
Name
No.
Type
inp
inn
icntp
icntn
outp
outn
fbcrl
efcrl

Namevccvee
Rev. 1.3.2

DESCRIPTION

High-Speed I/Os
Differential high-speed signal inputs with internal SE 50Ohm
termination to vcc
Differential low-speed control inputs with internal SE 50Ohm
termination to vcc
CML Differential high-speed signal outputs with internal SE 50Ohm
output termination to vcc. Require external SE 50Ohm termination to vcc
Digital Controls
15
Input SE DC control input terminated to vcc. (In most cases should beleft not connected or connected to vcc)
17
Input SE DC control input terminated to internal resistive divider
between vee and vcc
Supply And Termination Voltages
Description
Pin NumberPositive power supply (+3.3V or 0)2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24
Negative power supply (0V or -3.3V)
1, 7, 13, 19
21
2335119CML
input
Input

4January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ELECTRICAL CHARACTERISTICSPARAMETER
veevccIvee
Power consumption
Junction temperature
Data Rate
Frequency
Swing
CM Voltage Level
Data Rate
Frequency
Logic “1” level
Logic “0” level
Rise/Fall times
Output Jitter
Duty cycle
Logic “1” level
Logic “0” level
Phase shift
Phase shift stability
Absolute delay stability
Bandwidth
SE voltage level
SE voltage level
Differential swing
CM Level
Control voltage range
Control voltage range
Rev. 1.3.2

MIN

TYP MAX UNIT
COMMENTS
General Parameters
-3.1
-3.3
-3.5
V
±6%
0.0
V
External ground
380mA
efcrl at max
270mA
efcrl at min
1.25
W
efcrl at max
890mW
efcrl at min
-25
50
125°C
HS Input Data/Clock (inp/inn)
DC50Gbps
DC32GHzFor clock signals
0.051.0V
Differential or SE, p-p
vcc-0.8
vcc
VMust match for both inputs
HS Output Data/Clock (outp/outn)
DC50
Gbps
DC32
GHz
For clock signals
Vvcc
vcc-0.45
V
With external 50Ohm DC termination911
ps
20%-80%1.5
ps
Peak-to-peak
45
50
55%
For clock signal
DC Offset Cancellation Control (fbcrl)
Vvcc
Vvee
Output-to-Input Delay
0110
ps
For the full range of icntp/icntn signals-1212
ps0-125°C-1414
ps
0-125°C
Tuning port (icntp/icntn)
DC1000MHzvcc-500vcc
mV
Half control range when the opposite
pin is at vcc
vcc-1000
vcc
mV
Full control range when the opposite
pin is at vcc-0.6V01000
mV
Peak-peak. Full control range
vcc-(Diff. swing)/4V
In differential mode
Tuning port (fbcrl)
mV
Default voltage is vcc
veevcc
Tuning port (efcrl)
vcc-1500
vcc
mV
Default voltage is vcc-0.75V
5January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

PACKAGE INFORMATIONThe chip die is housed in a custom 24-pin CQFP package shown in Fig. 3. The package provides a center
heat slug located on its back side to be used for heat dissipation. ADSANTEC recommends for thissection to be soldered to the vcc plain, which is ground for a negative supply, or power for a positive
supply.

Fig. 3. CQFP 24-Pin Package Drawing (All Dimensions in mm)

Rev. 1.3.2

6January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

The part’s identification label is ASNT5105A-KMC. The first 9 characters of the name before the dashidentify the bare die including general circuit family, fabrication technology, specific circuit type, and partversion while the 3 characters after the dash represent the package’s manufacturer, type, and pin outcount.
This device complies with the Restriction of Hazardous Substances (RoHS) per 2011/65/EU for all ten
substances.

REVISION HISTORY
Revision
1.3.2
1.2.2
1.2.1
1.1.1

Date
01-2020
07-2019
08-2018
09-2015

1.0.106-2015

Rev. 1.3.2

Changes
Updated Package Information
Updated Letterhead
Added efcrl settings (Table 1)
Revised operating frequency range
Revised title
Revised description
Revised electrical characteristics section
First release

7

January 2020