電気学会論文誌●（●●●●●●●部門誌）
IEEJ Transactions on ●●●●●●●●●●●●●●●
Vol.●● No.● pp.●-●●
DOI: ●.●●/ieejeiss.●●.●

Paper

Fundamental Operation of Modular Marx Topology forHigh Boost Ratio DC-DC Converter
Asmarashid Bin Ponniran＊a) Student-member, Koji Orikawa＊ Member, Jun-ichi Itoh＊ Member(Manuscript received Jan. 00, 20XX, revised May 00, 20XX)

The paper proposes a high boost ratio of modular Marx topology DC-DC boost converter (MTBC). In the proposed converter,
the parallel-connection is applied at the input side in order to reduce the conduction loss and the copper loss. Meanwhile themulti-stage connection is applied at the output side in order to reduce the voltage rating of switching components at the output
side. Therefore, with the proposed circuit configuration, high efficiency of the high boost ratio DC-DC converter is achieved.
Besides, 3-stage MTBC with boost ratio of 8.33 between the input voltage to the output voltage is designed and constructed.
Moreover, the achieved maximum efficiency of the designed 3-stage MTBC is 94.5%. Meanwhile, from the loss analysis, itshows that the iron loss and the conduction loss are dominant.
Keywords: high boost ratio DC-DC converter, Marx topology converter, input inductor design, stage capacitor design.

1.

topology that able to achieve a high boost ratio in DC-DC
converter. Basically the purpose of Marx generator is to generate ahigh-voltage pulse from a low-voltage DC source (12, 13). However,the conventional Marx generator has high conduction losses andcopper losses due to large input current. As a result, the efficiencyof the conventional Marx generator is low. Therefore the main
application of the Marx generator is limited for low power
applications. On the other hand, the Marx topology DC-DC
converters with resonant condition operation are proposed in orderto achieve the ZCS condition (14-16). However, due to the resonantcondition, the input inductor current should be in discontinuous
current mode (DCM) and consequently the input inductor is bulky.
Furthermore the conduction loss is also increased.
This paper proposes a new high boost ratio of a Marx topology
DC-DC converter. In the proposed circuit, the parallel-connectionof conventional 2-level boost DC-DC converters are applied at the
input side in order to reduce the conduction loss and the copper
loss. In addition, the multi-stage connections are applied at theoutput side in order to reduce the voltage rating of stage capacitorsand switches. Meanwhile, voltage stress of the lower switches sidein the input side is same to that of components at the output side.
Therefore, lower voltage semiconductors which have low
on-resistance can be used for the switches in the proposed circuit.
Meanwhile, high voltage rating diodes at the input side are
required. However, high voltage rating of SiC diodes which have
low forward voltage and low reverse recovery time can be used
nowadays. As a result, a high-efficiency boost converter can beachieved.
This paper is organized as follows. First, the principle of then-stage Marx topology DC-DC converter is described. Then, theinput inductors and stage capacitors designs on each stage areestablished. The relationship between the voltage stress on stage

Introduction

DC-DC converter with high boost ratio is required for low DC
voltage energy sources such as for electric vehicle (EV) system,fuel-cells system and photovoltaic (PV) systems. These systems
usually need low-voltage and high-current power converters inorder to supply DC power to a DC bus or a load.
In a conventional DC-DC boost converter, a high boost ratio
can be achieved by connecting those converters in cascade
connection (1). However, this topology cannot achieve highefficiency due to a number of required cascade connected DC-DC
converters. Especially, high conduction losses occur at input side
due to large input current. Besides, generally DC-DC converters
using high frequency transformers are also used in order to obtaina high boost ratio (1-5). However, those converters usually sufferfrom the bulkiness and large losses due to the bulky transformer.
In addition, leakage current causes false operation of the DC-DC
converter due to the parasitic capacitance and high voltage
difference between the transformer windings. On the other hand, ahigh boost ratio is achieved with switched capacitor DC-DC
converters (6-8). However, the output voltage stress on the output
capacitor is very high due to high output voltage and it requires
many capacitors connected in series. Meanwhile, with diodeclamped converters, the low on-resistance of switching devices isdifficult to be achieved due to high voltage stress at the output side
(9-11). Especially if a high boost ratio is considered, those circuit
configuration is not practical.
Besides, a Marx generator topology is one of the attractivea) Correspondence to: Jun-ichi Itoh. E-mail:itoh@vos.nagaokaut.ac.jp＊
Nagaoka University of Technology
1603-1 Kamitomioka-machi, Nagaoka, Niigata 940-2188, Japan© 200● The Institute of Electrical Engineers of Japan.

1

High Boost Ratio Marx Topology Converter (Asmarashid Bin Ponniran et al.)IL(m)capacitors and the number of stages is evaluated. Finally, power
loss of the proposed converter is theoretically analyzed. Then,
distribution of the power loss is clarified by comparing calculated
results and measurement results based on 3-stage Marx topology
DC-DC boost converter.

2.

Stage-m

L(m)

D(m)

S(m)a

C(m)

ILout
S(m)b

Lout

S(m)c

VDS-max= VC(m)-max

Converter Principle and Circuit Configuration
IL3

Fig. 1 shows a circuit configuration of the n-stage Marx
topology boost converter (MTBC). Basically, each stage of the
MTBC consists of a conventional 2-level boost DC-DC converter,a capacitor and two additional switches. The converter is designed
based on a principle of the Marx pulse generator whereby ahigh-output voltage is generated from a low-voltage DC source (12).
This principle is realized by charging several capacitors in parallel
and then suddenly connecting those capacitors in series. Therefore,
by arranging these combinations of capacitors in the proposed
converter, a high output voltage is generated. It is noted that 10 to
20 stages might be required in order to reduce input currents stress,
switching devices voltage rating and stage capacitor voltages
stress in the actual application.
In order to analyze the MTBC operation and its characteristic, a3-stage MTBC is introduced as a specific example in this section.
In principle, the relationship between the input voltage Vin and theoutput voltage Vout is expressed as follows:Stage-3

L3

D3

S3a

C3

S3c
IL2

C2

1

n

VDS-max= VC2-max

Stage-1

IL1
L1

D1
C1

S1a

S1b
S1c

........................................................................... (2)

Vout

S2b
S2c

where  is the boost ratio. Meanwhile the duty ratio D in terms ofboost ratio can be expressed as follows:

1

Cout

D2

S2a

Vin

VDS-max= VC3-max

Stage-2

L2

Vout  Vin ........................................................................... (1)

D

S3b

VDS-max= VC1-max

Fig. 1. n-stage MTBC circuit configuration.

However, high voltage SiC diodes which have low forward
voltage and low reverse recovery time can be used nowadays.

where D is the duty ratio for the switches S1a, S1b, S2a, S2b, S3a andS3b and n is the number of stage. Thus the output voltage Vout interms of the duty ratio D, the number of stage n and the input
voltage Vin can be rewrite as follows:

3. Passive components design and selection
In this section, the inductor current of each stage in the MTBC
is designed to be operated in continuous current mode (CCM) inorder to minimize the peak input current. Thus the minimum
inductor current of each stage should be greater than zero in orderto ensure a CCM condition is achieved. Then the minimum
inductance of the input inductor of each stage Lin(m) for CCM
operation is expressed as follows: D 
Vout  nVin .......................................................... (3)1 D Figs. 2 and 3 show the switching pattern and operation mode of
the 3-stage MTBC, respectively. The switching pattern withdead-time Td and additional time-delayed Ta is considered for
reducing of surge voltage of the switch. The 3-stage MTBC needs
four operation modes.
Table 1 shows the conditions of the stage capacitors. The stage
capacitors C1, C2 and C3 are charging when those capacitors areconnected in parallel as shown in Fig. 3. Then, those stage
capacitors are connected in series during discharging condition asshown in Fig. 3. Thus, the output voltage is boost-up by theadvantage of a series connection of the stage capacitors. Therefore,a high boost ratio is achieved.
The voltage stresses on the switching devices S 1a, S1b, S1c, S2a,
S2b, S2c, S3a, S3b and S3c are determined by each of the maximum
stage capacitor voltages VC1, VC2 and VC3. Each stage capacitor
voltage is lower than the output voltage. Therefore, lower voltage
stress semiconductors which have low on-resistance can be used.
Meanwhile, the voltage stresses on the diodes D1, D2 and D3 areequal to the VC1, 2VC2, and 3VC3, respectively. Thus the top diodevoltage stress is equal to total stage capacitor voltage stresses.

n Vin  D................................................................. (4)2 Pout f sw
2

Lin m  where m is the n-th of stage, n is the number stage, Pout is theoutput power and fsw is the switching frequency. Meanwhile theinductor current ripple on each stage ILin(m) can be expressed asfollows:

I Lin m  

Vin D............................................................... (5)f sw Lin m 

The capacitance of the stage capacitor is expressed as follows:C m  

I L m ave 1  D 
VC m  f sw



Pin 1  D .............................. (6)nVin VC m  f sw

where C(m) is the capacitance of the stage capacitor and VC(m) is
the stage capacitor voltage ripple.

2

IEEJ Trans. ●●, Vol.●●, No.●, ●●●High Boost Ratio Marx Topology Converter (Asmarashid Bin Ponniran et al.)Principally, the maximum stage capacitor voltage VC(m)-max andthe average inductor current on each stage IL(m)_ave are expressed asfollow:

Vout............................................. (7)
n

S1b
S2b
S3b

Pin
.................................................................... (8)
nVin

S1c
S2c
S3c

VC m max  VDS max  Vin 

I L m ave where VDS-max is the maximum drain-source voltage of a MOSFET,
Pin is the input power.
According to the circuit arrangement as shown in Fig. 3, themaximum stage capacitor voltage is equal to the maximum ofdrain-source voltage of MOSFETs as shown by (7). Furthermore,
the maximum stage capacitor voltage and average stage current
are inversely proportional to the number of stage as shown by (7)and (8). Thus the maximum stage capacitor voltage and average
stage current will be reduced according to the increasing thenumber of stage n.

4.







OFF

ON

OFF

ON

OFF

S3a

C3

L2

D2

S2a

C2

L1

S3b

III II
Td+Ta

L3

D3

S3a

C3

L2

D2

S2a

C2

S3b

Vout
Cout

L1

D1

S1a

C1

S1b
S1c

Mode IS1a, S2a and S3a – ON
S1b, S2b and S3b – ON

Mode II
Dead-time Td condition
S1a, S2a and S3a – ON
L3

D3

S3a

C3

L2

D2

S2a

C2

L1

I in
V D
 in
..................................... (12)nf sw Lout

Vout
Cout

S2c

Vin

Lout

S3b

S3a

D3
C3

S2b

Vout

C1

S2a

D2
C2

S2b

Cout

Vout

S2c
L1

D1

S1a

Lout

S3b
S3c

L2

S2c

I
V D
I S1a _ max  I Lin _ max  in  in..................................... (11)nf sw Lout

Lout

S2b

S3c

Vin

Tona
Tsw

S3c

S1b

2

where ILin_max and ILin_min are the maximum and minimum input
inductor currents, respectively at each stage and the currents equal
to the maximum and minimum currents of the MOSFET S1a
IS1a_max and IS1a_min, respectively. The maximum and minimum
currents IS1a_max and IS1a_min are expressed as follow:

D

S1c

L3

................... (10)

II III
Td+Ta

Switching pattern.

Lout

S2b

C1

I



D1

Vin S
1a



I S1a _ min  I Lin _ min 

IV

D3

S2c

iS1a eff   iS 2a eff   iS 3a eff  ..................................................... (9) I Lin _ max  2 I Lin _ min I Lin _ max  I Lin _ min D iS 1a eff   
3


2

I

I
I
D

I
D
Lin
_
max
Lin
_
min
Lin
_
min
Lin
_
min



ON

S3c

4.1
Conduction loss for MOSFETs S1a, S2a and S3a
Principally, the effective currents of iS1a(eff), iS2a(eff) and iS3a(eff) aresame because the input side of the MTBC are synchronized. The
effective current is expressed as follows:

1

Tsw

Fig. 2.
L3

In this section, the effective and average currents for the
MOSFETs and diode are derived mathematically for loss analysis
calculation. Then, the conduction power losses of the MOSFET
and diode in the 3-stage MTBC are analyzed theoretically.

2

ON

ON

III II I II III
Td+Ta
Td+Ta
Td = dead-time
Ta = additional time-delayed

Loss Analysis Based on Theoretical Equation

2

Ton-a

S1a
S2a
S3a

S1b

Vin

S1a

Cout

D1
C1

S1b

S1c

S1c

Mode III
Additional time-delay Ta
condition
S1a, S2a and S3a – ON
S1c, S2c and S3c – ON

Mode IV
S1c, S2c and S3c – ON

Fig. 3.
Table 1.

Operation mode of the 3-stage MTBC.
Stage capacitor operation on 3-stage MTBC.

where Iin is the average input current. Thus the summation of
conduction losses for S1a, S2a and S3a are expressed as follows:Mode

S1a S2a S3aS1b S2b S3bS1c S2c S3c

C1, C2 & C3

Pcond _ Sma  iSmaeff  Ron  n .................................................. (13)

(I)

ON

ON

OFF

Discharging
in series

(II)

ON

OFF

OFF

unchanged

(III)

ON

OFF

ON

unchanged

(IV)

OFF

OFF

ON

Charging
in parallel2

4.2
Conduction loss for MOSFETs S1b, S2b and S3b
The effective currents of iS1b(eff), iS2b(eff) and iS3b(eff) are same. It
equals to the output inductor current ILout when these switches areon-state. The effective current of these switches is expressed asfollow:

iS1beff   iS 2beff   iS 3beff  ..................................................... (14)3IEEJ Trans. ●●, Vol.●●, No.●, ●●●High Boost Ratio Marx Topology Converter (Asmarashid Bin Ponniran et al.)





1


 2






2
2
3
I

2
I
I

I
1

D
 S 2 c _ max
S 2 c _ max S 2 c _ min
S 2 c _ min2
3D  1
  I S 2 c _ max  I S 2 c _ min I S 2 c _ min



 
 (23)
D 1

 
2 
I S 2 c eff     
1 D 
22I
 2 I S 2 c _ max I S 2 c _ min  I S 2 c _ min    S 2 c _ max

2


 

D  1



 

2
I
I

I

S 2 c _ min
S 2 c _ max
S 2 c _ min2  I S 2 c _ min 

D

1




2
2 1  D    I 2 I S 2 c _ max I S 2 c _ min  I S 2 c _ min    S 2 c _ max


 

D  12

 


1

 I Lout _ max  I Lout _ min 2 D
 2



 .......... (15)3i S 1b eff   2
  2 I Lout _ min I Lout _ max  I Lout _ min D  ILout _ min D 
2













where ILout_max and ILout_min are the maximum and maximum output
inductor currents, respectively and the currents are equal to the
maximum and minimum currents of the MOSFET S1b IS1b_max andIS1b_min, respectively. The maximum and minimum currents IS1b_max
and IS1b_min are expressed as follow















nDVin
................................. (16)
I S1b _ max  I Lout _ max  I out 
2 f sw Lout

where IS2c_max and IS2c_min are the maximum and minimum currentsof the MOSFET S2c, respectively. The maximum and minimum
currents IS2c_max and IS2c_min are expressed as follow:

nDVin................................. (17)
I S1b _ min  I Lout _ max  I out 
2 f sw Lout
where Iout is the average output current. Thus the summation of
conduction losses for S1b, S2b and S3b are expressed as follow:

I S 2c _ max 

I in
V D
nVin D I out  in......................... (24)n
2 f sw Lin 2 f sw Lout

Pcond _ Smb  iSmbeff  Ron  n ................................................ (18)

I S 2c _ min 

I in
V D
nVin D I out  in......................... (25)n
2 f sw Lin 2 f sw Lout2

4.3
Conduction loss for MOSFET S1c, S2c and S3c
Principally, the MOSFETs S1c, S2c and S3c are operated during
charging condition of the stage capacitors. Furthermore, thecurrents iS1c(eff), iS2c(eff) and iS3c(eff) are not same one another due tocircuit configuration at the output side as shown in Mode IV ofFig. 3.

Thus the conduction loss for S2c is expressed as follows:

Pcond _ S 2c   iS 2c eff  Ron ........................................................ (26)2

Meanwhile, the effective current for iS3c(eff) is expressed as follows:

The effective current for iS1c(eff) is expressed as follows:

1


 2






2
2
3
 I S 3c _ max  2 I S 3c _ max I S 3c _ min  I S 3c _ min 1  D

2




3
D

1


  I S 3c _ max  I S 3c _ min I S 3c _ min



 

D 1

 
2 
i S 3c eff     
1

D
2
2

I
 2 I S 3c _ max I S 3c _ min  I S 3c _ min    S 3c _ max

2

 

D  1 
2 I S 3c _ min I S 3c _ max  I S 3c _ min

2


I



S 3c _ min
D 1

 

2
2 1  D    I

2
I
I

I
S
3
c
_
max
S
3
c
_
max
S
3
c
_
min
S
3
c
_
min

 


 

D  12

 


1


 2






2
2
3
I

2
I
I

I
1

D
 S 1c _ max
S 1c _ max S 1c _ min
S 1c _ min2
3D  1
  I S 1c _ max  I S 1c _ min I S 1c _ min



 
 . (19)
D 1

 
2 
i S 1c eff     
1 D 
22I
 2 I S 1c _ max I S 1c _ min  I S 1c _ min    S 1c _ max

2

 

D  1 
2 I S 1c _ min I S 1c _ max  I S 1c _ min2  I S 1c _ min 

D 1

 




1

D
2
2




I S 1c _ max  2 I S 1c _ max I S 1c _ min  I S 1c _ min 

 

2

 



D

1

 










































(27)







where IS3c_max and IS3c_min are the maximum and minimum currentsof the MOSFET S3c, respectively. The maximum and minimum
currents IS3c_max and IS3c_min are expressed as follow:

where IS1c_max and IS1c_min are the maximum and minimum currentof the MOSFET S1c, respectively. The maximum and minimum
currents IS1c_max and IS1c_min are expressed as follow:

2I
V D
nVin DI S1c _ max  in  I out  in......................... (20)nf sw Lin 2 f sw Lout

I S1c _ min 



2I in
V D
nVin D I out  in......................... (21)nf sw Lin 2 f sw Lout

I S 3c _ max  I Lout 

nVin D................................................. (28)
2 f sw Lout

I S 3c _ min  I Lout 

nVin D................................................. (29)
2 f sw Lout

where ILout is the average output inductor current. Therefore theconduction loss for S3c is expressed as follows:

Thus the conduction loss for S1c is expressed as follows:

Pcond _ S 3c   iS 3c eff  Ron ........................................................ (30)2

Pcond _ S1c   iS1c eff  Ron ......................................................... (22)2Then, the effective current for iS2c(eff) is expressed as follows:

4

IEEJ Trans. ●●, Vol.●●, No.●, ●●●High Boost Ratio Marx Topology Converter (Asmarashid Bin Ponniran et al.)

4.4
Conduction loss for diodes D1, D2 and D3
Theaverage diode currents iD1(ave), iD2(ave) and iD3(ave) are same. The
average diode current is expressed as follow:

4.7
Total conduction and switching losses for all
switches and diodes
The total conduction and switchinglosses for all switches and diodes in 3-stage MTBC is expressed asfollows:

i D1ave  i D 2ave  i D3ave ..................................................... (31)

Pcond SW _ total   Pcond _ total   PSW _ total  I Lin _ max  I Lin _ min 1  D 2 .................. (32)2D  1i D1ave    I Lin _ max  I Lin _ min 1  D  1  D I Lin _ min D  1

 Pcond _ S 1a  S 2 a  S 3a   Pcond _ S 1b  S 2b  S 3b   Pcond _ S 1c 
 Pcond _ S 2 c   Pcond _ S 3c   Pcond _  D1 D 2 D 3

 PSW _ S 1a  S 2 a  S 3a   PSW _ S 1b  S 2b  S 3b   PSW _ S 1c 
 PSW _ S 2 c   PSW _ S 3c 

The maximum and minimum diode currents ID1_max and ID2_min are
expressed as follow:

I D1 _ max  I Lin _ max 

I in
V D
..................................... (33) inn
f sw Lout

I D 2 _ min  I Lin _ min 

I in
V D
 in
...................................... (34)n
f sw Lout

5. Experimental results
Table 2 shows the specifications of the experimental prototype
circuit. The inductance of the input inductor on each stage isdesigned by using (5).
Fig. 4 shows the experimental results of the input inductor
current ripples on stage-1 (IL1), stage-2 (IL2) and stage-3 (IL3),
which are 1.9 A, 1.8 A and 1.8 A respectively at the output powerof 1 kW. However the designed input inductor current ripple oneach stage is 1.5 A and the design principle is according to (5).
The different between experimental results and designed value isdue to the voltage drop on the winding resistance of the inductors.
The stage average inductor current is divided by three due to threeparallel-connections at the input side. Therefore, if many stages
are considered, the input current will be divided by the factor of
the stage number and consequently the input current stress, theconduction loss and the copper loss will be reduced.
Fig. 5 shows the experimental results of the capacitor voltages
on each stage VC1, VC2 and VC3 of the 3-stage MTBC. The results
show that each stage capacitor voltage is 190 V. On the other hand,
it is experimentally confirmed that the output voltage is 400 V
when the input voltage is 48 V. Meanwhile if the number of stage
is increased the voltage stress on stage capacitors and the
maximum voltage stress on switching devices will be reduced aswell. Thus according to the (9), the voltage stress on stage
capacitor voltages and the maximum voltage stress on switching
devices are inversely proportional to the number of stage.
Fig. 6 shows the efficiency characteristic of the prototype
circuit. The input and output voltages are fixed at 48 V and 400 V,
respectively. The maximum efficiency is 94.5% at the output
power of 500 W. In addition, the efficiency is decreased when the
output power is increased at 1 kW due to the increasing of the
conduction loss and the copper loss. On the other hand, during low
output power, the power loss is dominated by the iron loss. As aresult, the efficiency is low during low output power.
Fig. 7 shows the distribution of the power losses based ontheoretical calculation. The power losses are distributed into nineparts, i.e., diode conduction loss, MOSFET conduction loss at
input and output sides, MOSFET switching loss at input andoutput sides, inductor copper loss, ESR loss, no load loss
(discharging power losses for drain-source parasitic capacitancesof MOSFETs) and others. The total power loss of 100% is basedon the measured total power loss by experiment when the output
power is 1 kW. From the loss analysis, it shows that the converter
loss is dominated by the ‘Others’ loss whereby it includes the ironloss, wiring loss and so on. It is estimated that the iron loss isdominant in the ‘Others’ loss.

Therefore the summation of conduction losses for D1, D2 and D3
are expressed as follows:

Pcond _ Dm  iDmaveVF  n ..................................................... (35)
4.5
Copper and iron losses
In the constructed 3-stage
MTBC, the copper loss is contributed by the three input inductors
and one output inductor. The copper resistances of each inductor
are measured for copper loss estimation. The expression for thecopper loss is expressed as follows:n

Pcopper   iLmeff  Rcopper _ m  iLouteff  Rcopper _ out ................. (36)
m1

2

2

where iLm(eff) is the effective stage input inductor currents, iLout(eff) is
the effective output inductor current, Rcopper_m is the inductor
winding resistance of the stage input inductor and Rcopper_out is theinductor winding resistance of the output inductor.
Meanwhile, iron loss is not analyzed by the theoretical equationin this paper. Instead, based on the power loss measurement andtheoretical calculation of other power losses, the different between
both power losses is considered as the iron loss.
4.6
Switching loss for MOSFETs and diodes
Allswitching device voltages have same minimum and maximum
voltages of the stage capacitor. The minimum and maximum
voltages can be expressed as follow:

VC m  _ max 

nVin  Vout 1 1  D Pout............................. (37)n
2 nf sw Cm Vin

VC m  _ min 

nVin  Vout 1 1  D Pout.............................. (38)n
2 nf sw Cm Vin.............. (40)

The generalization of each switching loss for S1a, S2a and S3a isexpressed as follows: VC m  _ min I Sma_ max
 VC m  _ max I Sma_ min
PSW _ Sma  
f swt r   
f swt f 66 on 
 off............................................................................................ (39)On the other hand, the switching losses for Smb and Smc aredefined by the same equation of (39).
5

IEEJ Trans. ●●, Vol.●●, No.●, ●●●High Boost Ratio Marx Topology Converter (Asmarashid Bin Ponniran et al.)Table 2.

Experiment specification.

Specification

Stage Capacitor Voltage VC1 (V)Value

Input voltage Vin/Output voltage Vout
Output power Pout
Switching frequency fsw
Input inductor L1=L2=L3
Output inductance Lout
Stage capacitor C1=C2=C3/Output capacitor CoutPower MOSFET (SiHG25N40D)
SiC Schottky Barrier Diode (SCS220KGC)

48/400 V
1000 W
50 kHz
500 mH
800 mH
44/50 mF
400 V/25 A
1200 V/20 A

VC2 = 190 V

0,(VC1)
Stage Capacitor Voltage VC2 (V)VC2 = 190 V

0,(VC1)
Stage Capacitor Voltage VC2 (V)VC2 = 190 V

0,(VC1)
Ouput Voltage Vout (V)Vout = 400 V
Inductor Current IL1 (A)IL1  1.9 A

0,(VC1)

Inductor Current IL2 (A)IL1  1.8 A

Fig. 5. Experimental waveforms of the stage-1, stage-2 andstage-3 capacitor voltages, and the output voltage.

Inductor Current IL3 (A)IL2  1.8 A

0,(IL1)0,(IL2)

Fig. 4.

Efficiency h (%)

IL1, IL2, IL3 (5 A/div)

10 (ms/div)

Experimental waveforms of the stage-1, stage-2 andstage-3 inductor currents.

Based on circuit configuration, the proposed 3-stage MTBC has
input and output inductors. Thus, the iron loss is considereddominant especially at the output inductor side due to the highvoltage stress at the output. The second major losses are the
MOSFET conduction loss and copper loss. From the experimental
results, the input current ripple is increased when the output power
is increased and this condition leads the iron loss increasing
according the increasing the output power. Besides, according to(17), the iron loss is influenced by the voltage stress on the inductor
and the applied switching frequency. Thus principally, the ironloss is reduced when the voltage stress and the applied switchingfrequency are reduced. These options will be further analyzed in a
future research work for iron loss reduction.

94

92

Boost ratio = 8.33
Switching frequency = 50 kHz
Number of stage = 3
Input voltage = 48 V
Output voltage = 400 V

90
88
86

200

400

600

800

1000

Output power Pout (W)Fig. 6.

100

Conclusion

Power loss Ploss (%)

6.

10 (ms/div)96

T = 20 ms

0,(IL3)

VC1, VC2, VC3, Vout (250 V/div)

This paper proposes a high boost ratio modular Marx topology
DC-DC boost converter whereby the parallel-connection ofseveral capacitors at the input side and then the multistage
connection of capacitors at the output side are applied. In thepresent paper, the authors have discussed (i) the fundamental
circuit operation confirmation of the 3-stage MTBC, (ii) the
design principle of the input inductors and stage capacitors, and(iii) the mathematical expression for loss calculation and analysis.
The principals of designing the inductance of the input inductor
and the capacitance of the stage capacitors according to thenumber of stage were explained. As a result, the inductance of the
input inductor and stage capacitor voltages stress on each stage isreduced by the increasing the number of stage. The input inductor
current ripple on each stage is designed and it confirmed by theexperimental results. Moreover, mathematical expressions of the
conduction and switching losses are derived and were confirmedby the simulation results. The maximum efficiency of the
prototype converter was 94.5% at the output power of 500 W.
From the loss analysis, it is confirmed that the efficiency is
increased by optimizing inductor design.

Efficiency of the 3-stage MTBC.

fsw = 50 kHz
Vin = 48 V
Vout = 400 V
100% = 70 W

Others (iron, etc.)
No load loss
ESR loss (Cm & Cout)
Pcopper (Lm & Lout)

50

Psw (MOSFET-output)
Psw (MOSFET-input)
Pcond (MOSFET-output)
Pcond (MOSFET-input)
Pcond (Diode)0500

800 1000

Output power Pout (W)Fig. 7.

*Note:
Pcond = conduction loss

Psw = switching loss
Pcopper = copper loss

Loss distribution of the 3-stage MTBC.

In a future, new switching patterns will be introduced for theconverter efficiency improvement.

6

IEEJ Trans. ●●, Vol.●●, No.●, ●●●High Boost Ratio Marx Topology Converter (Asmarashid Bin Ponniran et al.)References

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IEEJ Trans. ●●, Vol.●●, No.●, ●●●