Design Optimization of a Five-level Active NPC Inverter
Yugo Kashihara, and Jun-ichi Itoh,
Nagaoka University of Technology
1603-1 Kamitomioka-cho
Nagaoka City Niigata,Japan
Tel.: +81 / (258) – 47.9533.
Fax: +81 / (258) – 47.9533.
E-Mail: itoh@vos.nagaokaut.ac.jp
URL: http://itohserver01.nagaokaut.ac.jp/itohlab/index.html

Keywords
Multilevel converter, Design, Photovoltaic.

Abstract
This paper discusses the optimization designing method for a 5-level ANPC inverter. The point of themathematical expression is to observe the losses of a converter based on the study of the device
condition. Selection of the capacitor is also discussed accordingly based on the design method. The
performance of the 5-level ANPC inverter is compared with a conventional 2-level inverter. The
validity of the proposed calculation method for the power loss is confirmed with the experimental
results. The 5-level ANPC inverter can achieve higher efficiency than the 2-level inverter.

I. Introduction
Applications of the multilevel converters are actively researched recently [1-3]. Comparing themultilevel converters to the conventional 2-level converters, multilevel converters show better
advantages, for example a multilevel converter can reduce the voltage stress of a switching device to1/(n-1) of the DC input voltage and also reduce the harmonic component of the output voltage. As aresult, multilevel converters can use switching devices, which are high speed switching and low
voltage rating. Multilevel converters are possible to obtain higher efficiency than the conventional
converters.
In general, the multilevel converters are applied to the medium voltage application such as thepower converter for large power motor drive and also for the power transmission line. Recently, lowvoltage applications also have been studied to use multilevel converter such as the uninterrupted
power supply (UPS) and the power converter for photo voltaic cell (PV) [3].
There are two conventional multilevel topologies; the neutral point clamped (NPC) type and theflying capacitor (FC) type [1]. The NPC type outputs the voltage level from the neutral point voltage
which is clamped by using diodes. However the number of switching devices increases in proportional
to the voltage level. The FC type outputs the voltage level from the DC link voltage based on the
flying capacitor voltage. However, FC type needs more capacitors as the voltage level increases.
The active neutral point clamped (ANPC) which is one of the multilevel topology has been proposed
in Ref [2]. The ANPC type is a new topology that combines the NPC and FC type into one converter.
Compared to the conventional NPC and FC type converters, the ANPC uses lesser switching devices.
Therefore, the ANPC type is low in term of cost and further achieves higher efficiency than theconventional NPC and FC type.
Selection criteria of switching devices for multi-level converter are necessary to determine theconverter obtains high efficiency in low voltage applications. Loss analysis by using simulator is a
simple method to study the losses among the multilevel converter topologies under a same device
specification. However the loss estimation by simulation is not useful to consider the optimization ofdesign because hundreds of simulations are required under different conditions.
This paper establishes an optimization designing method for a 5-level ANPC inverter. The point of
the mathematical expression is to observe the losses of a converter based on the study of the device

condition. Selection of the capacitor is also discussed accordingly based on the design method. In thispaper, the 5-level ANPC inverter is designed to apply in a PV system. The performance of the 5-level
ANPC inverter is then compared with the conventional 2-level inverter. The validity of the proposed
calculation results for the power loss is confirmed with the experimental results. The 5-level ANPC
inverter is shown able to achieve higher efficiency than the 2-level inverter.

II. A Five-Level Converter Topology
A. ANPC circuit
Figure 1 shows the single leg diagram of a five-level ANPC inverter, which is constructed by eightswitches and three capacitors. The ANPC converter has two advantages; first, the ANPC inverter isable to obtain high efficiency because of the low switching loss. There are two switching frequencies
in an ANPC converter. In the conventional multi-level converter topology, the switching frequency of
all the switching devices is same to the carrier frequency, on the other hand, in an ANPC, theswitching frequency of the Cell2 switching device in Fig.1 is same to the output frequency (50Hz) andonly Cell1 switching devices use the carrier frequency. As a result, the switching loss is greatly
reduced. It should be noted that the voltage rating of the switching devices in Cell2 are required toequal to half of the DC link voltage. The second advantage is the ANPC converter can control the
flying capacitor voltage C1 and therefore a voltage balance circuit is not necessary and results the sizeof the circuit is compact and small.
Table I shows the switching pattern of the five-level ANPC converter and the flying capacitor
voltage. The five-level ANPC inverter outputs five kind of voltage levels which are –1/2Edc, –1/4Edc, 0,+1/4Edc, and +1/4Edc. These five kind of voltage levels are given by summing the flying capacitor
voltage and the DC smoothing capacitor voltage. There are eight switching pattern in the five-level
ANPC inverter. When the switching pattern is +1/4Edc or -1/4Edc, the flying capacitor is in charge
mode or discharge mode.

TABLE I
Switching pattern and flying capacitor voltage.

Fig.1. Single phase 5-level ANPC inverter circuit topology.

B. Control strategy
Figure 2 shows the gate signal waveform of the five-level ANPC inverter. The gate signals of Cell1
switches are generated by phase shift carrier-based PWM strategy. These gate signals are generated bycomparing to the output voltage command with two carriers which the phase is reversed to each other.
The duty ratio command Dref for Cell1 is given by;Dref  2a sin  1 0      .............................. (1),Dref  2a sin   1     2  ........................... (2),where a is the modulation index and  is the reference phase angle.

When the polarity of the output voltage command is positive, the gate signals of S 5 and S7 areturned on. When the polarity of voltage command is negative, the gate signals of S 6 and S8 are turned
on. This control method can balance the flying capacitor voltage automatically, by choosing thedischarge and charge modes according to the cycle of carrier frequency.

Fig.2. Gate signals.

III. Mathematical Expression of Power Loss
This chapter explains the power loss expression of the five-level ANPC inverter. The ANPC
inverter is assumed to operate in an ideal condition. The power loss of the ANPC inverter is calculated
under two ideal conditions, that is no load ripple current and no voltage ripple in capacitors. Then, thepower loss of the ANPC inverter is given by
PLoss  PCell1  PCell 2  PFC  C DCSC ......................... (3),where PLoss is the total loss (W), PCell1 is the Cell1 loss (W), PCell2 is the Cell2 loss (W), PFC is theflying capacitor loss (W) and PDCSC is the DC smoothing capacitor loss (W). Furthermore, the power
loss consists of the switching loss and the conduction loss, which are generated at turn on and off,from the forward voltage drop of a switching device, respectively.

A. Power loss of Cell1
1) Conduction loss
The conduction loss is separated into two, namely the switch side loss and FWD side loss. We
assume that the positive current flows into the switch side and the negative current flows into the
FWD side. In addition, if the switching device of the ANPC converter is MOSFET, both the positive
current and negative current flow into the switch side due to low on-resistance. The average value ofthe conduction loss is calculated from the on-voltage and the switch current and the duty ratio
command Dref which can be given by
PSwitch 

1  
vonisw1dx ..................................... (4),2 v on  ron I  v 0 ................................................... (5),





1

isw1  I m sin     1  Dref  ............................ (6),2where von is the on-voltage, ron is the on-resistance (), I is the current flows through the switch (A),v0 is the drop voltage (V) when I equals to approximately 0 A, Im is the peak phase current, a is themodulation index,  is the power factor.
The on-voltage von in the equation (4) and the equation (5) is expressed for the IGBT. The on-voltage

occurs in the switching device from on-resistance and p-n junction, which is expressed in the equation(5). On the other hand, if the switching device of the ANPC converter is MOSFET, v0=0 in theequation (5).
The conventional loss Pon_sw1 in the switch side are expressed in the equation (7) from the equation(4), (5), (6).
v

1
1
1
2
1
POn _ sw1  I m  0  v 0 cos  
I m ron sin 2 
I m ron 
I m aron cos   av 0 cos   (7)
2

2
8

4

3

4



On the other hand, the conventional loss Pon_FWD1 in the switch side are given by
v

1
1
1
1
2
1
POn _ FWD1  I m  0  v 0 cos  
I m ron sin 2 
I m ron 
I m ron 
I m aron cos   av 0 cos   (8).
8
4
4
3
4
 2 22) Switching loss
We assume that the switching loss of the switches in Cell1 is proportional to the applied voltage andcurrent. Therefore, the switching loss of the Cell1 depends on the current flows through the switches
and the number of switching. The Cell1 switching loss Psw1 is given by
Psw1 



1 Edc I meon  eoff f c ............................. (9),4 Edcd I md

where Edc is the input voltage (V), eon is the turn-on energy (J) per switching at datasheet, eoff is theturn-off energy (J) per switching at datasheet, Edcd is the voltage (V) at the measurement condition ofswitching loss at datasheet, Imd is the current (A) at the measurement condition of switching loss atdatasheet and fc is the carrier frequency (Hz). The recovery loss PRec1 in Cell1 is given by
PRe c 1 Edc I m
err f c .................................... (10),4 Edcd I md

where err is the recovery energy (J) per switching from the datasheet.

B. Power Loss of Cell2
1) Conduction loss
The conduction loss in Cell2 is obtained by the same formula that is used to calculate theconduction loss in Cell1. However, the current flows into the Cell2 switches are different from theCell1 because of the following two conditions: S5 and S7 are turn-on when the output voltage
command is positive and S6 and S8 are turn-on when the output voltage command is negative. isw2A isthe switch current flows to S5 and S7 and isw2B is the switch current flows to S5 and S7, which are given
by

1

i  I m sin     1  Dref  0     i sw2 A   sw1
(11),
2

0






2


0     0
i sw2 B  
(12).
1

i sw1  I m sin     2 1  Dref      2 












Therefore, the conduction loss Pon_sw2A is calculated by substituting equation (11) into equation (4).
Pon_sw2A is given by
POn _ sw2 A 

1  1
2
1 2
1
1
1

aron  cos 2  cos    I m  av0   cos   sin    cos  
2   6
3
2
2
2
2


(13).

The conduction loss of the FWD side of S5 and S7 are given by
POn _ FWD 2 A 

4
1   
 I m a 8I m ron sin   3v0 sin   3v0 cos  12  
2



(14).

Likewise, the conduction loss for the switch side of the S 6 and S8 is given by (15) and the
conduction loss for the FWD side of the S6 and S8 is given by (16)
Pon _ sw2 B 


1 
 1
1
1


2 
 I m v0 cos   1 I m r    sin 2   I m av0  cos   sin    cos  
2 
2
2
4
2
2
2




2
1 
1
 I m ar  cos 2  cos   
3
2 
6

(15),

Pon _ FWD 2 B 

1  2  1
1
2
1 

1
2
 I m r   sin 2   I mv0  I mv0 cos   I mav0 sin    cos    I m ar  cos 2  cos   
2 
2
4
2
6
3
2 




(16),

2) Switching loss
The switching loss in the Cell2 is depending on the output frequency (50Hz). As a result, theswitching loss in the Cell2 is lower than the switching loss in the Cell1, which is nearly equal to zeroand therefore the switching loss can be disregarded.

IV. Parameter Design of The Capacitor
A. Flying capacitor
1) Design of the capacitor
The capacitance of the flying capacitor C1 is calculated by the capacitor current, the ripple voltage
and the time integration of the charge period or discharge period. The flying capacitor voltage isrepeating to charge and discharge in one carrier cycle. Thus, the time integration of the charge period
and the discharge period is equivalent. Therefore, the capacitance of C1 is given by
C FC 

I mT E dc........................................... (17),8VFC Vm

Where VC1 is the ripple voltage of the flying capacitor, VDC is the DC link voltage, Vm is the
maximum value of output voltage, and T is the reciprocal of carrier frequency.

2) Calculation method of the flying capacitor loss
The conduction loss PFC occurs in the flying capacitor is based on the equivalent series resistance(ESR) [12]. The conduction loss PFC is given by2
PFC  I rms _ FC R FC ............................................ (18),where Irms_FC is the rms value of the flying capacitor current (A) and RFC is the ESR value of theflying capacitor (). The ripple current of the capacitors are limited as a permitted value in terms of
the lifetime of the capacitor. Thus, Irms_FC is an important factor for selecting the capacitor. The rms
value of the ripple current at switching frequency is a non-linear value. Therefore, the calculation as
for a general solution is difficult and the complexity is impractical. The current of the flying capacitor
is a function for the output power factor and modulation index. These values are also non-dimensional.
The rms value of the flying capacitor value is given by equation (19) using the flying capacitor current
coefficient Kfc. The flying capacitor current coefficient Kfc is calculated from the normalized
simulation.
I rms _ FC  K cf I m ............................................... (19)Figure 4 shows the conversion of the flying capacitor current coefficient Kfc. Kfc is defined by theoutput phase factor and modulation index. The maximum value of KCF is 0.65 when the modulationindex in figure 5 is 0.5 to 0.6. The ESR Rfc of the flying capacitor is given byRFC 

tan  1
2fC FC F fn .......................................... (20),where tan is the tangent of loss angle. Tan in the equation (20) is the normalized value at 120Hz.
Thus, Irms_FC and RFC at the switching frequency are calculated by using the frequency correction
coefficient Ffn.

B. DC smoothing capacitor
1) Design of the capacitor
The DC smoothing capacitors are connected to the DC link voltage in parallel because of the ANPC
inverter uses DC neutral point voltage. The capacitance of DC smoothing capacitor C2 and C3 are
calculated by the voltage ripple and the DC smoothing capacitor current based on DC neutral point
voltage fluctuation. The capacitance of DC smoothing capacitor C2 and C3 is given by
C2 

Vm


I m  3   ............................... (21)2VcnVDC 
3

where Vcn is the maximum voltage ripple of C2.

2) Calculation loss of the DC smoothing capacitor
The calculation for the DC smoothing capacitor loss is obtained by the same formula that is used to
calculate the flying capacitor loss. The DC smoothing capacitor loss is given by
2
PDCSC  I rms _ CDSC RDCSC .................................... (22),I rms _ CDSC  K cdc I m ............................................ (23),
RDCSC tan 
1
2fC DCSC F fn ..................................... (24),where Irms_CDSC is the rms value of the ripple current flows through the DC smoothing capacitor (A)and RCDC is the ESR of the DC smoothing capacitor () and KCDC is the DC capacitor current
coefficient Kcdc.
Figure 5 shows the current coefficient of the DC smoothing capacitor. Kcdc is calculated by thenormalized simulation. Figure 5 indicates that the maximum value of Kcdc becomes 0.46 at a=0.6. In
addition, the main component of the DC smoothing capacitor is the switching frequency component
and the triple component of output frequency. When the power factor is 1, the rms value Irms_CDSC of
the ripple current flows through the DC smoothing capacitor can be expressed by equation (23). In
addition, the rms value Irms_CDSC3rd of the triple component of output frequency is given by
I rms _ CDSC3rd 

1
2 2

aI m ...................................... (25)

Fig.3. Current coefficient of flying capacitor. Fig.4. Current coefficient of DC smoothing capacitor.

C. The volume of the capacitor
This chapter explains the calculation of the capacitor volume. There are two capacitors which are theflying capacitor and DC smoothing capacitor in the ANPC inverter. Thus, the capacitors volume iscalculated based on the film capacitors and electrolytic capacitors that are available in the marketed [5].

1) The film capacitor
The volume of the film capacitor is proportional to the energy is stored in the capacitor. The volume
VCE of the film capacitor is given by
VCF   VCF1

1
C F U O2 ......................................... (26),2where -1VCF is the proportionality factor between the energy and the volume, CF is the capacity of
the film capacitor and UO is the applied volume of the film capacitor.

2) The electrolytic capacitor
The volume of the electrolytic capacitor is proportional to the rms value of the ripple current of theelectrolytic capacitor. The volume VCE of the electrolytic capacitor is given by
VCE   V1 I C , RMS ............................................. (27),where -1VCE is the proportionality factor between the rms value of the ripple current and the volume,
and IC,RMS is the rms value of the ripple current of the electrolytic capacitor.
CE

D. The selection method of the capacitor
The capacitor has to satisfy these factors, which are the capacity, the rated voltage and the allowedripple current.
Figure 5 shows the design flowchart for the capacitor. In figure 8, Irip is the designed ripple current,
Vol is the determined capacitor volume, Irip_data is the ripple current of the datasheet, Vol_data is thecapacitor volume of the datasheet, and Cn is the capacity of the datasheet. The capacitor can beselected by the design produce flowchart. The specifications first need to decide are following; thevoltage ripple Vn of the capacitor, the input voltage Vin, the output voltage Vout and maximum output

current Ipeak. Firstly, the switching frequency is determined by the design specifications. Secondly, thecapacity Cn and the ripple current Irip is calculated based on the specifications. The capacity Cn is
calculated by equation (17) and equation (21). The rated voltage is two-thirds of the applied voltage ofthe capacitor in the datasheet. The ripple current Irip is calculated by equation (19) and equation (23).
The capacitor which satisfies the designed parameter showed be.

Fig.5.Design produce flowchart.

E. The design method of the inductor
The application of the 5-level ANPC inverter in this paper is proposed to apply in a PV system [6].
This chapter explains the design method of the utility interaction inductor. This utility interaction
inductor is for suppression of the output ripple current. The utility interaction inductor LANPC is givenby
L ANPC 

Vdc  3Vm V1 3 m  T ................... (28),2I
E dc 2 where I is the ripple current. The volume of the inductor is calculated by the Area Product. The
volume of the inductor is given by3

 2W  4
 ...................................... (29),
VL  KV  K u Bm J w 

where KV is the constant value which is determined by figure of the core, Ku is the window utilization
factor, Jw is the current density, Bm is the flux density.

F. The design method of heatsink
The performance of the heatsink is discussed based on the Cooling System Performance Index(CSPI) [5]. The CSPI is an expressed value of the thermal resistance at per unit volume. The larger thevolume of the CSPI, the large is the cooling capacity per unit volume will be. The CSPI is given by
CSPI 

1................................................ (30),RthV0where Rth is the thermal resistance of the heatsink, Vo is the volume of the heatsink. In addition, Rth isgiven byRth  f  a  

T j  TaPl Rth  f  s  ................................ (31),where Tj is the junction temperature of the switching device, Ta is the ambient temperature, Pl isevolution loss.

V. Experimental Verification
Figure 8 shows the operation waveforms for the five-level ANPC inverter. The input voltage is 283 V,
the output voltage is 141 V, 50 Hz, the output power is 1 kW (rating), the flying capacitor voltage
command is set to 70V and the carrier frequency is 10 kHz. The parameters of the devices arefollowing (S1-S4:IRFP4668pBF (IR), S5-S6:IXFB170N30P (IXYS), C1:LGU2W101MELA(Nichicon), and C2-3:FXA2G472 (Hitachi)) referring to datasheets in [7-10]. The output current
shows a perfect sinusoidal waveform without distortion. In addition, the flying capacitor voltage

agrees with the voltage command, which is approximately 70 V. Furthermore, a five-step waveform isshown at the output voltage of the ANPC inverter.
Figure 9 shows the efficiency of the five-level ANPC inverter. The maximum efficiency is 98.9% at a0.45 kW load. The Five-level ANPC inverter can obtain efficiency of over 98% in wide loadconditions.
Figure 10 shows the loss of the five-level ANPC inverter from on the theoretical calculation andexperimental results. The maximum error of the theoretical value and experimental value is 1.9W at
0.45 kW load. The loss estimation results are well agreed with that of the experimental results.
Figure 11 shows the switching loss analysis of the five-level ANPC inverter based on the theoretical
calculation. In the five-level ANPC inverter, the major loss is dominant by the conduction loss. In
order to achieve high efficiency, the switching devices which are featuring the low on-resistance or
low on-voltage are selected. In the devices selection, focus should be on the conduction loss, because
the switching loss in the Cell2 is very low. Note that there is trade off relationship between theswitching speed and on-resistance in the power device. That is, the switching device in the Cell 2
should be designed with a low on-resistance even though the switching speed becomes slow.

Fig.6 Experimental waveform.

Fig.7 Efficiency of a five- level ANPC inverter.

Fig.8 Loss analysis comparison between theoreticaland experimental.

Fig.9. Loss analysis.

VI. The Design Optimization of the 5-Level ANPC Inverter for a PV system
This chapter discusses the design optimization of the 5-level ANPC inverter for a PV system. First,
The PV inverter is designed by using the parameter design method of the 5-level ANPC inverter.
Secondary, The performance of the 5-level ANPC inverter is compared with the conventional 2-level
inverter.
Table II shows the specification of the PV converter. The input voltage is 350 V, the output voltage is
200 V, the rated power is 4 kW, the ripple voltage of the flying capacitor is 3%, the ripple voltage of
the DC smoothing capacitor is 5%. The CSPI of the heatsink is 10.
Table III shows the selected devices for the 5-level ANPC inverter and 2-level inverter. Table IVshows the selected device parameters for the 5-level ANPC inverter and 2-level inverter. The
switching device is determined by the rating voltage and allowable current. The applied voltages of theswitching device of the 5-level ANPC inverter and 2-level inverter are difference. In the 5-level ANPC
inverter, the applied voltage of the Cell1 switching devices is quarter of the input voltage. The applied
voltage of the Cell2 switching devices is half of the input voltage.Thus, the switching device for the 5level ANPC inverter is the MOSFET. On the other hand, the applied voltage of the 2-level inverter issame to the input voltage. The switching device for the 2-level inverter is the IGBT.
The capacitor values of the 5-level ANPC inverter are designed by the ripple voltage value from thetable II. The flying capacitor and DC smoothing capacitor use the electrolytic capacitor because ofdesigned capacitor value is high. Three capacitors are connected in parallel because the ripple current
is relatively high.
Figure 10 shows the efficiency of the 5-level ANPC inverter and 2-level inverter. The efficiency of
the 5-level ANPC inverter is 99.3% at rated load. On the other hand, the efficiency of the 2-level
inverter is 97.9 %. The efficiency of the 5-level ANPC inverter is 1.3 % higher than the efficiency ofthe 2-level inverter.
Figure 11 shows the loss analysis of the 5-level ANPC inverter and 2-level inverter. In the 5-level
ANPC inverter, major loss is dominant by the capacitor loss. On the other hand, major loss of the 2level inverter is dominant by the conduction loss.
Figure12 shows the volume of the 5-level ANPC inverter and 2-level inverter. In the 5-level ANPC
inverter, the volume value is 0.36 dm3. The major volume of the 5-level ANPC inverter is dominant by
the capacitor volume of the flying capacitor and DC smoothing capacitor. On the other hand, thevolume value of the 2-level inverter is 0.35 dm3. The major volume of the 2-level inverter is dominantby the inductor. The volume of the 2-level inverter is lower 0.01dm3 than the volume of the 5-level
ANPC inverter. However, the inductor volume of the 5-level ANPC inverter is 0.11dm3. On the other
Table II Specification of the converter.

Table III Selected devices.

Table IV Designed device parameters.

Fig.10 efficiency of the 5-level ANPC inverterand 2-level inverter.

Fig.11 Loss analysis of the converters s.

hand, the inductor volume of the 2-level inverter is 0.21dm3. The 5-level ANPC inverter can reducethe inductor volume by 50%.
Figure 13 shows the relationship between the efficiency and power density at switching frequency
from 1 kHz to 100 kHz. When the switching frequency is 9 kHz, the 5-level ANPC inverter achieves
the maximum power density 5.1 kW/dm3 and the efficiency is 98.3%. On the other hand, when theswitching frequency is 1 kHz, the 2-level inverter achieves the maximum power density 32.3 kW/dm3
and the efficiency point of 98.3%. The 5-level ANPC inverter is proved to achieve a higher efficiency
than the 2-level inverter.

VII. Conclusion
This paper established an optimization designing method for a five-level ANPC inverter. The fivelevel ANPC inverter loss is analyzed by the mathematical expressions and experimental results. The
error rate between the theoretical value and experimental value is 2 % at the rated load. In addition, theperformance of the 5-level ANPC inverter is compared with the conventional 2-level inverter under anapplication for PV system. When the switching frequency is 9 kHz, the 5-level ANPC inverter
achieves the maximum power density 5.1 kW/dm3 and efficiency is 98.3%. The 5-level ANPC inverter
is shown perform better than the 2-level inverter in term of efficiency and power density.
In the future study, the performance of the 5-level ANPC inverter will be compared with other typesof conventional multilevel converters.

References[1] F. Z. Peng : “A Generalized Multilevel Inverter Topology with Self Voltage Balancing”, IEEE
Transactions on industry applications, Vol.37, No.2, pp. 2024-2031 (2001)[2] Barbosa, P.; Steimer, P.; etc: “Active Neutral-point-Clamped Multilevel Converter”, PowerElectronics Specialists Conference, 2005. PESC '05. IEEE 36th16-16 June 2005 Page(s):2296 –2301[3] Lin Ma, Tamas Kerekes, etc :“The high efficiency Transformer-less PV Inverter Topologies
Derived From NPC Topology”, EPE2009 – Barcelona[4]Yugo Kashihara, Jun-ichi Itoh:“Parameter design of a Five-level Inverter for PV systems”, ICPEECCE Asia 2011[5] J. W. Kolar, J Biela and J. Miniböck：「Exploring the Pareto Front of Multi –Objective

Single-Phase PFC Rectifier Design Optimization -99.2% Efficiency vs. 7kW/dm3 PowerDensity」，IPEMC 2009-China，(2009)[6] Wm. T. Mclyman: “Transformer and inductor design handbook”, Marcel Dekker Inc. (2004)[7] Data sheet: IRFP4668pBF (IR) http://www.irf.com/productinfo/datasheets/data/irfp4668pbf.pdf[8] Data sheet: IXFB170N30P (IXYS) http://ixdev. ixys.com/DataSheet//DS100000(IXFB170N30P).pdf[9] Data sheet: LGU2W101MELA (Nichicon)http://www.nichicon.co.jp/products/pdf/gu.pdf[10] Data sheet: FXA2G472 (Hitachi) http://www. hitachiaic.com/products/condenser/almi/neji.html

Fig.12 Analysis of the converter volume

Fig.13 Relations between the Efficiency
and power density.