Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ASNT5107-KMC
DC-32Gbps/26GHz Signal Phase Shifter

Automatic temperature and process corner delay compensation with manual override

Duty cycle distortion compensation with adjustable gain

Manual internal peaking control



Fully differential CML input interface

Fully differential CML output interface

Single +3.3V or -3.3V power supply



Fabricated in SiGe for high performance, yield, and reliability

Custom CQFP 24-pin package

vee

1GHz of bandwidth for the phase adjustment tuning port

vcc

fbcrlManual control of power consumption / operational speedvcc

efcrlBroadband tunable data/clock phase shifter

vcc

vee

vcc

vcc

inp

outp

ASNT5107
X

vcc
inn
vcc

vcc
outn
vcc

Rev. 1.0.2

1vcc

icntn

vcc

icntp

vcc

vee

icrl

January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

DESCRIPTION
efcrl

fbcrl5050inp

outp

TunablePhase Shiftinn50

outn
505050

icntp

icntn

Fig. 1. Functional Block Diagram

ASNT5107-KMC is a data/clock variable delay line with an advanced control system fabricated in SiGetechnology. The IC shown in Fig. 1 provides an adjustable delay of its differential output signal
outp/outn in relation to its broadband input signal inp/inn. The delay is controlled through a wide-banddifferential tuning port icntp/icntn. The chip incorporates an automatic common-mode offset cancellation
circuit that operates with either clock signals or data signals with balanced patterns. In case of nonbalanced data patterns, the circuit should be disabled through the control port fbcrl. The single-ended
control port efcrl can be used to manipulate internal peaking in the delay block in order to adjust thepart’s frequency response and thus improve output eye diagrams for various data rates and operating
conditions.
The part’s I/Os support the CML logic interface with on chip 50Ohm termination to vcc and may be useddifferentially, AC/DC coupled, single-ended, or in any combination (see also POWER SUPPLYCONFIGURATION). In the DC-coupling mode, the input signal’s common mode voltage should comply
with the specifications shown in ELECTRICAL CHARACTERISTICS. In the AC-coupling mode, theinput termination provides the required common mode voltage automatically. The differential DC
signaling mode is recommended for optimal performance.
The part’s power consumption can be adjusted between its minimum (default), and maximum values
using a single-ended analog control port icrl. It should be noted that higher power leads to higher
operational speed of the part.
Due to an extremely low jitter, the part is suitable for use in high-speed measurement / test equipment.

Delay Control PortThe delay is controlled through a wide-band differential tuning port icntp/icntn. This part's delay control
system was designed to minimize output jitter and increase the control function linearity. To achieve thegoals, the control system is split so that each delay stage has its own control buffer. Only three stages
Rev. 1.0.2

2January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

operate in interpolation mode at any delay position, and all the other stages are fully switched either to theshort path or to the long path.

Feedback Gain Control PortThis part has two duty cycle correction feedback loops. In case of feedback malfunction, currents inside
feedback amplifiers can be manually adjusted or completely shut down through a single-ended tuning port
fbcrl. The simulated dependence of feedback reference current on the control voltage is shown in Fig. 2.

Fig. 2 Simulated Internal Feedback Current vs. Control Voltage

Higher feedback amplifier currents result in higher feedback gain and lower stability. If the port is left notconnected, it defaults to an internal level of vcc-0.66V, the feedback current is half its maximum value
and the phase shifter is in normal operating mode.

Internal Peaking Control Port
Depending on the data rate and operational conditions, the part’s output eye diagram may get distorted
because of jitter caused by parasitic internal peaking. Internal peaking can be adjusted by varying currentsof internal emitter followers through a single-ended port efcrl. The simulated dependence of reference
current of internal emitter followers on the control voltage is shown in Fig. 3. If this port is left notconnected, it defaults to an internal level of vcc-0.66V and, emitter follower currents are half of theirmaximum values and the circuit is in normal operating mode.

Rev. 1.0.2

3January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

Fig. 3. Simulated Internal EF Reference Current vs. Control Voltage

POWER SUPPLY CONFIGURATION
The part can operate with either a negative supply (vcc = 0.0V=ground), or a positive supply (vee =0.0V=ground). In case of a positive supply, all I/Os need AC termination when connected to any devices
with 50Ohm termination to ground. Different PCB layouts will be needed for each different power supply
combination.
The part’s power consumption can be adjusted between its minimum and maximum values using a singleended analog control port icrl. Higher voltages at the control input correspond to higher power
consumption. With the non-connected control port, the part defaults to minimum power consumption. Itshould be noted that higher power consumption leads to higher operational speed of the part as detailed in
ELECTRICAL CHARACTERISTICS.

All the characteristics detailed below assume vcc = 0.0V.

Rev. 1.0.2

4January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ABSOLUTE MAXIMUM RATINGS
Caution: Exceeding the absolute maximum ratings shown in Table 1 may cause damage to this productand/or lead to reduced reliability. Functional performance is specified over the recommended operating
conditions for power supply and temperature only. AC and DC device characteristics at or beyond theabsolute maximum ratings are not assumed or implied. All min and max voltage limits are referenced toground (assumed vcc).
Table 1. Absolute Maximum Ratings.

Parameter
Supply Voltage (vee)Power supply current
RF Input Voltage Swing (SE)Case Temperature
Storage Temperature
Operational Humidity
Storage Humidity

Min-401010Max-3.6400
1.0+90+100
98
98

Units
VmA
VºCºC%%TERMINAL FUNCTIONSTERMINAL
Name
No.
Typeinp
inn
icntp
icntn
icrl
fbcrl
efcrl
outp
outn
Name
vcc
vee

Rev. 1.0.2

DESCRIPTION

High-Speed I/Os
21
CML Differential high-speed signal inputs with internal SE 50Ohm
input termination to vcc
23
3
input Differential control input with internal SE 50Ohm terminations to5
input vcc
7
input SE DC analog control input with internal 11.5KOhm termination
to vee15
input SE DC control input terminated to internal resistive divider
17
input between vee and vcc
11
CML Differential high-speed signal outputs with internal SE 50Ohm
output termination to vcc. Require external SE 50Ohm termination to vcc
9Supply And Termination Voltages
Description
Pin Number
Positive power supply (+3.3V or 0)2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24
Negative power supply (0V or -3.3V)
1, 13, 19

5January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ELECTRICAL CHARACTERISTICSPARAMETERveevcc
Ivee
Power consumption
Junction temperature
Data Rate
Frequency
Swing
CM Voltage Level
Data Rate
Frequency
Logic “1” level
Logic “0” level
Rise/Fall times
Output Jitter
Duty cycle
Phase shift
Phase shift stability
Absolute delay stability
Bandwidth
Control voltage range
Control voltage range
Control voltage range
Control voltage range

Rev. 1.0.2

MIN

TYP MAX UNIT
COMMENTS
General Parameters-3.1-3.3-3.5V±6%0.0V
External ground
190350mA
Adjustable
630
1150mW
Adjustable
-2550
125°C
HS Input Data/Clock (inp/inn)
DC32Gbps
DC20GHzAt minimum power consumption
DC26
GHz
At maximum power consumption
0.05
1.0
V
Differential or SE, p-p
vcc-0.8
vcc
VMust match for both inputs
HS Output Data/Clock (outp/outn)
DC32Gbps
DC20
GHz
At minimum power consumption
DC26
GHz
At maximum power consumption
Vvcc
vcc-0.44
V
With external 50Ohm DC termination.
911ps
20%-80%1.7ps
For PRBS input, peak-to-peak
455055%For clock signal
Output-to-Input Delay
For the full range of phadj control
0110
pssignal-66ps0-125°C junction temperature-1515ps
0-125°C junction temperature
Tuning port (icntp/icntn)
DC1000MHz
vcc-1000
vcc
mV
Default voltage is vcc
Tuning port (icrl)
mV
Default voltage is veevee
vcc
Tuning port (fbcrl)
vcc-1300
vcc
mV
Default voltage is vcc-0.66V
Tuning port (efcrl)
vcc-1300
vcc
mV
Default voltage is vcc-0.66V

6January 2020Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

PACKAGE INFORMATIONThe chip die is housed in a custom 24-pin CQFP package shown in Fig. 4. The package provides a center
heat slug located on its back side to be used for heat dissipation. ADSANTEC recommends for thissection to be soldered to the vcc plain, which is ground for a negative supply, or power for a positivesupply.

Fig. 4. CQFP 24-Pin Package Drawing (All Dimensions in mm)

The part’s identification label is ASNT5107-KMC. The first 8 characters of the name before the dashidentify the bare die including general circuit family, fabrication technology, specific circuit type, and partversion while the 3 characters after the dash represent the package’s manufacturer, type, and pin outcount.
This device complies with the Restriction of Hazardous Substances (RoHS) per 2011/65/EU for all ten
substances.
Rev. 1.0.2

7January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

REVISION HISTORY
Revision
1.0.2
0.0.2
0.0.1

Rev. 1.0.2

Date01-2020
09-2019
09-2019

Changes
Corrected current and power consumption
Updated Letterhead
Preliminary release

8January 2020