Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ASNT5079-KMC
DC-20Gbps/14GHz Signal Phase Shifter with Linearized OB

1GHz of bandwidth for the phase adjustment tuning ports

Ideal for high speed proof-of-concept prototyping

Fully differential CML input interfaces

Fully differential CML output interface with 600mV single-ended swingLinearized data output for minimized undershoot/overshootSingle +3.3V or -3.3V power supplyPower consumption: 1.6W

Fabricated in SiGe for high performance, yield, and reliability

Custom CQFP 24-pin package
veeExhibits low jitter and limited temperature variation over industrial temperature range

vcc



vcc

Delay adjustment range up to 280ps

vcc

vcc

Broadband (DC-20Gbps/DC-14GHz) tunable data/clock phase shifter

vcc

vee

vcc

vcc

ipoutpASNT5079

vcc

vcc

inoutnvcc

vcc

Rev. 5.3.2

1vcc

icntn

vcc

icntp

vcc

veeveeJanuary 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

DESCRIPTION

50
ip50
outp

TunablePhase Shiftin50

outn
50

5050

icntp icntn
Fig. 1. Functional Block Diagram

ASNT5079-KMC is a data / clock variable delay line fabricated in SiGe technology. The IC shown inFig. 1 provides an adjustable delay of its differential output signal outp/outn in relation to its broadband
input signal ip/in. The delay adjustment range is temperature-stabilized. The delay is controlled through awide-band differential tuning port icntp/icntn.
The part’s I/O’s support the CML logic interface with on chip 50Ohm termination to vcc and may be useddifferentially, AC/DC coupled, single-ended, or in any combination (see also POWER SUPPLYCONFIGURATION). In the DC-coupling mode, the input signal’s common mode voltage should comply
with the specifications shown in ELECTRICAL CHARACTERISTICS. In the AC-coupling mode, theinput termination provides the required common mode voltage automatically. The differential DC
signaling mode is recommended for optimal performance.
The output buffer is linearized for reduction of undershoot and overshoot on the output waveforms. Dueto an extremely low jitter, the part is suitable for use in high-speed measurement / test equipment.

Delay Control PortThe delay is controlled through a wide-band differential tuning port icntp/icntn. The delay control
diagram is shown in Fig. 2.

Rev. 5.3.2

2January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Delay Adjustment in ASNT5079 (new setup)

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

16014012010080

Relative Delay, ps

60
40
200-0.6-0.5-0.4-0.3-0.2-0.1-20 00.1

0.2

0.3

0.4

0.5

0.6

-40-60-80-100-120-140-160
Vcntp-Vcntn

Fig. 2. Delay Control Diagram

Rev. 5.3.2

3January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

POWER SUPPLY CONFIGURATION
The part can operate with either a negative supply (vcc = 0.0V = ground and vee = −3.3V), or a positivesupply (vcc = +3.3V and vee = 0.0V = ground). In case of a positive supply, all I/Os need AC termination
when connected to any devices with 50Ohm termination to ground. Different PCB layouts will be neededfor each different power supply combination.

All the characteristics detailed below assume vcc = 0.0V and vee = -3.3V.

ABSOLUTE MAXIMUM RATINGS
Caution: Exceeding the absolute maximum ratings may cause damage to this product and/or lead to
reduced reliability. Functional performance is specified over the recommended operating conditions forpower supply and temperature only. AC and DC device characteristics at or beyond the absolutemaximum ratings are not assumed or implied. All min and max voltage limits are referenced to ground.
Table 1. Absolute Maximum Ratings

Parameter
Supply Voltage (vee)Power Consumption
RF Input Voltage Swing (SE)
Case Temperature
Storage Temperature
Operational Humidity
Storage Humidity

Min-401010Max-3.6
1.8
1.0
+90
+100
98
98Units
VW
VºC
ºC%%

TERMINAL FUNCTIONSTERMINAL
NameNo.
TypeDESCRIPTION

Namevcc

High-Speed I/Os
21
CML Differential high-speed signal inputs with internal SE 50Ohm
input termination to vcc
23
3
CML Differential high-speed control inputs with internal SE 50Ohm
input termination to vcc
511
CML Differential high-speed signal outputs with internal SE 50Ohm
output termination to vcc. Require external SE 50Ohm termination to vcc
9Supply and Termination Voltages
Description
Pin Number
Positive power supply (+3.3V or 0)2, 4, 6, 8, 10, 12, 14, 15, 16, 17, 18, 20, 22, 24

vee

Negative power supply (0V or -3.3V)

ipin
icntp
icntn
outp
outn

Rev. 5.3.2

1, 7, 13, 194

January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

ELECTRICAL CHARACTERISTICSPARAMETER
veevccIvee
Power consumption
Junction temperature
Data Rate
Frequency
Swing
CM Voltage Level
Data Rate
Frequency
Logic “1” level
Logic “0” level
Rise/Fall times
Output Jitter
Duty cycle
Adjustment range
Absolute delay stabilityBandwidth
SE voltage level
SE voltage levelDifferential swing
CM LevelMIN

TYP

MAX UNITCOMMENTS
General Parameters-3.1-3.3-3.5
V±6%
0.0V
External ground
485
mA
1600mW-4025125°C
HS Input Data/Clock (ip/in)
DC20Gbps
DC14GHzFor clock signals
0.05
1.0V
Differential or SE, p-p
vcc-0.8vcc
VMust match for both inputs
HS Output Data/Clock (outp/outn)
DC20Gbps
DC14GHzFor clock signals
Vvcc
vcc-0.6 vcc-0.3 vcc
V
With external 50Ohm DC termination
610ps
20%-80%1ps
Peak-to-peak
455055%For clock signal
Output-to-Input Delay290
ps
At 1GHzFor the full range of280
ps
At 13GHz icntp/icntn control signals-33
ps
0-125°C
Phase Shift Control port (icntp/icntn)
DC
1000
MHz
vcc-600
vccmV
Half control range when the opposite pin
is at vcc
vcc-1200
vcc
mV
Full control range when the opposite pin
is at vcc-0.6V
01200
mV
Peak-peak, full control range
vcc-(Diff. swing)/4V
In differential mode

PACKAGE INFORMATIONThe chip die is housed in a custom 24-pin CQFP package shown in Fig. 3. Even though the package
provides a center heat slug located on the back side of the package to be used for heat dissipation,
ADSANTEC does NOT recommend for this section to be soldered to the board. If the customer wishes
to solder it, it should be connected to the vcc plain, which is ground for a negative supply or power for apositive supply.
Rev. 5.3.2

5January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

Fig. 3. CQFP 24-Pin Package Drawing (All Dimensions in mm)

The part’s identification label is ASNT5079-KMC. The first 8 characters of the name before the dashidentify the bare die including general circuit family, fabrication technology, specific circuit type, and partversion while the 3 characters after the dash represent the package’s manufacturer, type, and pin outcount.
This device complies with the Restriction of Hazardous Substances (RoHS) per 2011/65/EU for all ten
substances.
Rev. 5.3.2

6January 2020

Advanced Science And Novel Technology Company, Inc.
2790 Skypark Drive Suite 112, Torrance, CA 90505

Offices: 310-530-9400 / Fax: 310-530-9402
www.adsantec.com

REVISION HISTORY
Revision
5.3.2
5.2.2
5.2.1

Date
01-2020
07-2019
06-2013

5.1.1
5.0.1

02-201302-2013

4.0

10-2008

3.0
2.0
1.0

06-2007
04-2007
01-2007

Rev. 5.3.2

Changes
Updated Package Information
Updated Letterhead
Corrected title
Corrected electrical characteristics table
Added delay control diagram
Added package pin out drawing
Revised functional block diagram
Added power supply configuration
Added absolute maximum ratings
Revised terminal functions
Revised electrical characteristics
Revised package information
Added mechanical drawing
Format correction
Revised electrical characteristics section
Added packaging information section
Revised electrical characteristics section
Revised terminal functions section
First release

7

January 2020