PCI-DAS6023 and
PCI-DAS6025
Analog and Digital I/O
User's Guide

Document Revision 4A, May, 2009
© Copyright 2009, Measurement Computing Corporation

Trademark and Copyright Information
Measurement Computing Corporation, InstaCal, Universal Library, and the Measurement Computing logo areeither trademarks or registered trademarks of Measurement Computing Corporation. Refer to the Copyrights &Trademarks section on mccdaq.com/legal for more information about Measurement Computing trademarks.
Other product and company names mentioned herein are trademarks or trade names of their respective
companies.
© 2009 Measurement Computing Corporation. All rights reserved. No part of this publication may be
reproduced, stored in a retrieval system, or transmitted, in any form by any means, electronic, mechanical, by
photocopying, recording, or otherwise without the prior written permission of Measurement Computing
Corporation.
NoticeMeasurement Computing Corporation does not authorize any Measurement Computing Corporation product for
use in life support systems and/or devices without prior written consent from Measurement Computing
Corporation. Life support devices/systems are devices or systems that, a) are intended for surgical implantation
into the body, or b) support or sustain life and whose failure to perform can be reasonably expected to result ininjury. Measurement Computing Corporation products are not designed with the components required, and are
not subject to the testing required to ensure a level of reliability suitable for the treatment and diagnosis ofpeople.

HM PCI-DAS6023_25.doc

3

4

Table of Contents
Preface

About this User's Guide .......................................................................................................................7
What you will learn from this user's guide ......................................................................................................... 7
Conventions in this user's guide ......................................................................................................................... 7
Where to find more information ......................................................................................................................... 7
Chapter 1

Introducing the PCI-DAS6023 and PCI-DAS6025 ...............................................................................8
Overview: PCI-DAS6023 and PCI-DAS6025 features ...................................................................................... 8
Software features ................................................................................................................................................ 8
Chapter 2

Installing the PCI-DAS6023 or PCI-DAS6025......................................................................................9
What comes with your PCI-DAS6023 or PCI-DAS6025 shipment ................................................................... 9
Hardware .......................................................................................................................................................................... 9
Additional documentation ................................................................................................................................................. 9
Optional components ........................................................................................................................................................ 9

Unpacking the board ......................................................................................................................................... 10
Installing the software ...................................................................................................................................... 10
Installing the hardware ..................................................................................................................................... 10
Configuring the hardware ................................................................................................................................. 11
Differential input mode ....................................................................................................................................................11Single-ended input mode .................................................................................................................................................11
Non-referenced single-ended input mode ........................................................................................................................11
DAQ-Sync configuration .................................................................................................................................................12

Connecting the board for I/O operations .......................................................................................................... 12
Connectors, cables – main I/O connector.........................................................................................................................12
Pin out – main I/O connector ...........................................................................................................................................13
Cabling.............................................................................................................................................................................15
DAQ-Sync connector and pinout .....................................................................................................................................16
Field wiring and signal termination accessories...............................................................................................................16

Chapter 3

Functional Details ...............................................................................................................................18
Basic architecture ............................................................................................................................................. 18
Auxiliary input and output interface ................................................................................................................................18
DAQ-Sync signals ...........................................................................................................................................................19

DAQ signal timing............................................................................................................................................ 21
SCANCLK signal ............................................................................................................................................................21
A/D START TRIGGER signal ........................................................................................................................................21
A/D STOP TRIGGER signal ...........................................................................................................................................22
STARTSCAN signal........................................................................................................................................................23
SSH signal .......................................................................................................................................................................23
A/D CONVERT signal ....................................................................................................................................................24
A/D PACER GATE signal...............................................................................................................................................24
A/D EXTERNAL TIME BASE signal ............................................................................................................................24
A/D STOP signal .............................................................................................................................................................25

Waveform generation timing connections ........................................................................................................ 25
D/A START TRIGGER signal ........................................................................................................................................25
D/A CONVERT signal ....................................................................................................................................................26
D/A EXTERNAL TIME BASE signal ............................................................................................................................26

General-purpose counter signal timing ............................................................................................................. 27
CTR1 CLK signal ............................................................................................................................................................27
CTR1 GATE signal .........................................................................................................................................................27
CTR1 OUT signal ............................................................................................................................................................28

5

PCI-DAS6023 and PCI-DAS6025 User's Guide

CTR2 CLK signal ............................................................................................................................................................28
CTR2 GATE signal .........................................................................................................................................................28
CTR2 OUT signal ............................................................................................................................................................29
Chapter 4

Calibrating the Board..........................................................................................................................30
Introduction ...................................................................................................................................................... 30
Calibration theory ............................................................................................................................................. 30
Chapter 5

Specifications ......................................................................................................................................31
Analog inputs.................................................................................................................................................... 31
Accuracy ..........................................................................................................................................................................31
System throughput ...........................................................................................................................................................32
Settling time .....................................................................................................................................................................32
Parametrics ......................................................................................................................................................................33
Noise performance ...........................................................................................................................................................33

Analog outputs (PCI-DAS6025 only)............................................................................................................... 34
Analog output pacing and triggering ................................................................................................................................35
Analog input/output calibration .......................................................................................................................................35

Digital input/output........................................................................................................................................... 35
Discrete ............................................................................................................................................................................35
82C55 (PCI-DAS6025 only)............................................................................................................................................36

Interrupts........................................................................................................................................................... 36
Counters............................................................................................................................................................ 37
Configurable AUXIN<5:0>, AUXOUT<2:0> external trigger/clocks ............................................................. 38
DAQ-Sync inter-board triggers/clocks ............................................................................................................. 39
Power consumption .......................................................................................................................................... 39
Environmental .................................................................................................................................................. 39
Mechanical ....................................................................................................................................................... 39
DAQ-Sync connector and pin out..................................................................................................................... 40
Main connector and pin out .............................................................................................................................. 40
Declaration of Conformity ..................................................................................................................43

6

Preface

About this User's Guide
What you will learn from this user's guideThis user's guide explains how to install, configure, and use the PCI-DAS6023 and PCI-DAS6025 boards sothat you get the most out of their analog, digital, and timing features.
This user's guide also refers you to related documents available on our web site, and to technical support
resources.

Conventions in this user's guide
For more information on …
Text presented in a box signifies additional information and helpful hints related to the subject matter you arereading.
Caution! Shaded caution statements present information to help you avoid injuring yourself and others,
damaging your hardware, or losing your data.
< : >Angle brackets that enclose numbers separated by a colon signify a range of numbers, such as those assigned
to registers, bit settings, etc.

bold text

Bold text is used for the names of objects on the screen, such as buttons, text boxes, and check boxes. For
example:1. Insert the disk or CD and click the OK button.

italic text

Italic text is used for the names of manuals and help topic titles, and to emphasize a word or phrase. For
example:The InstaCal installation procedure is explained in the Quick Start Guide.
Never touch the exposed pins or circuit connections on the board.

Where to find more information
For additional information relevant to the operation of your hardware, refer to the Documents subdirectory
where you installed the MCC DAQ software (C:\Program Files\Measurement Computing\DAQ by default), or
search for your device on our website at www.mccdaq.com.
If you need to program at the register level in your application, refer to the STC Register Map for the PCIDAS6000 Series. This document is available at www.mccdaq.com/registermaps/RegMapSTC6000.pdf.

7Chapter 1

Introducing the PCI-DAS6023 and PCI-DAS6025
Overview: PCI-DAS6023 and PCI-DAS6025 features
This manual explains how to install and use the PCI-DAS6023 and PCI-DAS6025 boards. These boards can beused in a wide variety of measurement applications, including data logging, field testing and process control.
The PCI-DAS6025 provides 16 channels of 12-bit analog input, dual 12-bit analog outputs with a 10 kS/s perchannel update rate, 32 digital I/O lines and two 16-bit counter timers.
The PCI-DAS6023 provides 16 channels of 12-bit analog input, 8 digital I/O lines and two 16-bit counter
timers.
The analog inputs on each board can be configured as either eight differential or 16 single-ended channels. The
input ranges are bipolar, in four ranges of ±10 V, ±5 V, ±500 mV, and ±50 mV. The ranges are softwareselectable.
Each board provides nine user-configurable trigger/clock/gate pins that are available at a 100-pin I/O connector.
Six of the pins are configurable as inputs and three pins are configurable as outputs.
Up to five PCI-DAS6000 series boards can be interconnected for I/O synchronization. Five trigger/strobes and asynchronizing clock are available on a 14-pin header connector. Interrupts can be generated by up to seven
ADC sources and four DAC sources.
Both boards are equipped with an 82C54 counter chip that contains three 16-bit counters. Clock, gate, andoutput signals from two of the counters are available on the board’s 100-pin I/O connector. The third counter isused internally.

Software features
For information on the features of InstaCal and the other software included with your PCI-DAS6023 and PCIDAS6025, refer to the Quick Start Guide that shipped with your device. The Quick Start Guide is also available
in PDF at www.mccdaq.com/PDFmanuals/DAQ-Software-Quick-Start.pdf.
Check www.mccdaq.com/download.htm for the latest software version.

8

Chapter 2

Installing the PCI-DAS6023 or PCI-DAS6025
This section contains instructions on installing and configuring your PCI-DAS6023 or PCI-DAS6025 board,and includes description of compatible cables and accessory equipment.

What comes with your PCI-DAS6023 or PCI-DAS6025 shipment
As you unpack your board shipment, verify that the following components are included.

Hardware
The following items should be included with your shipment:


PCI-DAS6023 or PCI-DAS6025 board

PCI-DAS6025

PCI-DAS6023

Additional documentation
In addition to this hardware user's guide, you should also receive the Quick Start Guide (available in PDF at
www.mccdaq.com/PDFmanuals/DAQ-Software-Quick-Start.pdf). This booklet supplies a brief description of
the software you received with your PCI-DAS6023 and PCI-DAS6025 and information regarding installation ofthat software. Please read this booklet completely before installing any software or hardware.

Optional components
If you ordered any of the following products with your PCI-DAS6023 or PCI-DAS6025 board, they should be
included with your shipment.


CablesC100HD50-x

C100MMS-x

9

CDS-14-x

PCI-DAS6023 and PCI-DAS6025 User's GuideInstalling the PCI-DAS6023 or PCI-DAS6025

Signal conditioning accessories
MCC provides signal termination products for use with the PCI-DAS6023 and PCI-DAS6025. Refer to the"Field wiring and signal termination accessories" section on page 16 for a complete list of compatible
accessory products.

Unpacking the board
As with any electronic device, you should take care while handling to avoid damage from static
electricity. Before removing the PCI-DAS6023 and PCI-DAS6025 from its packaging, ground yourself using awrist strap or by simply touching the computer chassis or other grounded object to eliminate any stored static
charge.
If any components are missing or damaged, notify Measurement Computing Corporation immediately byphone, fax, or e-mail:

Phone: 508-946-5100 and follow the instructions for reaching Tech Support.
Fax: 508-946-9500 to the attention of Tech Support
Email: techsupport@mccdaq.com

Installing the software
Refer to the Quick Start Guide for instructions on installing the software on the Measurement Computing Data
Acquisition Software CD. This booklet is available in PDF at www.mccdaq.com/PDFmanuals/DAQ-SoftwareQuick-Start.pdf.

Installing the hardware
PCI-DAS6023 and PCI-DAS6025 boards are completely plug-and-play. There are no switches or jumpers to set
on these boards. Configuration is controlled by your system's BIOS. To install your board, follow the steps
below:
Install the MCC DAQ software before you install your board
The driver needed to run your board is installed with the MCC DAQ software. Therefore, you need to install the
MCC DAQ software before you install your board. Refer to the Quick Start Guide for instructions on installingthe software.
1.

Turn your computer off, open it up, and insert your board into an available PCI slot.

2.

Close your computer and turn it on.
If you are using an operating system with support for plug-and-play (such as Windows 2000 or Windows
XP), a dialog box pops up as the system loads indicating that new hardware has been detected. If theinformation file for this board is not already loaded onto your PC, you will be prompted for the disk
containing this file. The MCC DAQ software contains this file. If required, insert the Measurement
Computing Data Acquisition Software CD and click OK.

3.

To test your installation and configure your board, run the InstaCal utility installed in the previous section.
Refer to the Quick Start Guide that came with your board for information on how to initially set up andload InstaCal.

Allow your computer to warm up for at least 15 minutes before acquiring data with these boards. The highspeed components used on these boards generate heat and it takes this amount of time for a board to reachsteady state if it has been powered off for a significant amount of time.

10

PCI-DAS6023 and PCI-DAS6025 User's Guide

Installing the PCI-DAS6023 or PCI-DAS6025

Configuring the hardware
All of the hardware configuration options on the PCI-DAS6025/6023 are software controlled. You may selectsome of the configuration options using InstaCal, such as the analog input configuration (16 single-ended oreight differential channels), the edge used for triggering when using an external pacer and the source for the two
independent counters. Once selected, any program that uses the Universal Library will use these selections toinitialize the hardware according to these selections.
Following is an overview of the available hardware configuration options for the PCI-DAS6023 and PCIDAS6025 boards. For general information regarding signal connection and configuration, refer to the Guide to
Signal Connections. This document is available on our web site at www.mccdaq.com/signals/signals.pdf.

Differential input mode
When all channels are configured for differential input mode, eight analog input channels are available. In thismode, the input signal is measured with respect to the low input. The input signal is delivered through threewires:
The wire carrying the signal to be measured connects to CH# IN HI.
The wire carrying the reference signal connects to CH# IN LO.
The third wire is connected to LLGND.

Differential input mode is the preferred configuration for applications in noisy environments or when the signal
source is referenced to a potential other than PC ground.

Single-ended input mode
When all channels are configured for single-ended input mode, 16 analog input channels are available. In thismode, the input signal is referenced to the board’s signal ground (LLGND). The input signal is delivered
through two wires:

The wire carrying the signal to be measured connects to CH# IN HI.
The second wire is connected to LLGND.

Non-referenced single-ended input modeThis mode is a compromise between differential and single-ended modes. It offers some of the advantages ofeach mode. Using non-referenced single-ended mode, you can still get noise rejection but not the limitation in
the number of channels resulting from a fully differential configuration. The possible downside is that theexternal reference input must be the same for every channel. It is equivalent to configuring the inputs fordifferential mode and then tying all of the low inputs together and using that node as the reference input.
When configured for non-referenced single-ended input mode, 16 analog input channels are available. In thismode, each input signal is not referenced to the board’s ground, but to a common reference signal (AISENSE).
The input signal is delivered through three wires:

The wire carrying the signal to be measured connects to CH# IN HI.
The wire carrying the reference signal connects to AISENSE.
The third wire is connected to LLGND.

This mode is useful when the application calls for differential input mode but the limitation on channel countprevents it.

11

PCI-DAS6023 and PCI-DAS6025 User's Guide

Installing the PCI-DAS6023 or PCI-DAS6025

DAQ-Sync configuration
You can interconnect multiple boards in the PCI-DAS6000 series to synchronize data acquisition or data output.
To do this, order and install a CDS-14-x cable at the DAQ-Sync connectors (P2) between the boards to besynchronized. Each system can have one master and up to four slaves.
The "x" in the CDS-14-x part number specifies the number of connectors available on the cable, and therefore,
the number of boards you can interconnect. Using a CDS-14-2, you can connect two PCI-DAS6000 seriesboards together for I/O synchronization. Using a CDS-14-3, you can synchronize three boards, and so on. You
can connect up to five PCI-DAS6000 series boards. A CDS-14-3 cable is shown in Figure 3.
By default, all DAQ-Sync connectors are configured as inputs (slave mode). In order to be useful, use software
to configure one board as the master and to define the signal sources of the slave boards. Refer to "DAQ-Sync
signals" on page 19 for more information.
Detailed information regarding software configuration of these functions is available in the STC Register Map
for the PCI-DAS 6000 Series. This document is available from our web site atwww.mccdaq.com/registermaps/RegMapSTC6000.pdf.

Connecting the board for I/O operations
Connectors, cables – main I/O connector
The table below lists the board connectors, applicable cables, and compatible accessory products for the PCIDAS6023 and PCI-DAS6025.
Board connectors, cables, and accessory equipment
Connector typeCompatible cables
Compatible accessory productswith the C100HD50-x cableCompatible accessory productswith the C100MMS-x cable

Shielded, SCSI 100-pin D-type
C100HD50-x unshielded round cable. x = 3 or 6 feet. (Figure 1)
C100MMS-x shielded round cable. x = 1, 2, or 3 meters. (Figure 2)
 ISO-RACK16/P
 ISO-DA02/P (PCI-DAS6025 only) BNC-16SE
 BNC-16DI
 CIO-MINI50
 CIO-TERM100
 SCB-50
 SSR-RACK24 (PCI-DAS6025 only - DADP-5037 adapter required) CIO-ERB24 (PCI-DAS6025 only - DADP-5037 adapter required) CIO-ERB08 (PCI-DAS6025 only - DADP-5037 adapter required)
SCB-100

Information on signal connections
General information regarding signal connection and configuration is available in the Guide to Signal
Connections. This document is available on our web site at
http://www.measurementcomputing.com/signals/signals.pdf.

12

PCI-DAS6023 and PCI-DAS6025 User's Guide

Installing the PCI-DAS6023 or PCI-DAS6025

Pin out – main I/O connector
8-channel differential mode pin out
Signal Name Pin
GND 100
CTR2 OUT99
CTR2 GATE98
CTR2 CLK97
GND
96
CTR1 OUT
95
CTR1 GATE
94
CTR1 CLK
93
DIO7
92
DIO6
91
DIO5
90
DIO4
89
DIO3
88
DIO2
87
DIO1
86
DIO0
85
n/c
84
n/c
83
n/c
82
n/c
81
n/c
80
n/c
79
n/c
78
n/c
77
n/c
76
n/c
75
FIRSTPORTC Bit 7 *74
FIRSTPORTC Bit 6 *73
FIRSTPORTC Bit 5 *72
FIRSTPORTC Bit 4 *71
FIRSTPORTC Bit 3 *70
FIRSTPORTC Bit 2 *69
FIRSTPORTC Bit 1 *68
FIRSTPORTC Bit 0 *67
FIRSTPORTB Bit 7 *66
FIRSTPORTB Bit 6 *65
FIRSTPORTB Bit 5 *64
FIRSTPORTB Bit 4 *63
FIRSTPORTB Bit 3 *62
FIRSTPORTB Bit 2 *61
FIRSTPORTB Bit 1 *60
FIRSTPORTB Bit 0 *59
FIRSTPORTA Bit 7 *58
FIRSTPORTA Bit 6 *57
FIRSTPORTA Bit 5 *56
FIRSTPORTA Bit 4 *55
FIRSTPORTA Bit 3 *54
FIRSTPORTA Bit 2 *53
FIRSTPORTA Bit 1 *52
FIRSTPORTA Bit 0 *51
PCI slot ↓

Pin
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

* Not connected on the PCI-DAS6023

13

Signal NameGND
AUXIN5 / A/D PACER GATEAUXIN4 / D/A START TRIGGER
AUXIN3 / D/A UPDATEAUXIN2 / A/D STOP TRIGGER
AUXIN1 / A/D START TRIGGER
n/c
AUXIN0 / A/D CONVERTAUXOUT2 / SCANCLKAUXOUT1 / A/D PACER OUT
AUXOUT0 / D/A PACER OUT
PC +5 VD/A OUT1*
D/A GND*
D/A OUT 0*
AISENSE
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
LLGND
CH7 IN LO
CH7 IN HI
CH6 IN LO
CH6 IN HI
CH5 IN LO
CH5 IN HI
CH4 IN LO
CH4 IN HI
CH3 IN LO
CH3 IN HI
CH2 IN LO
CH2 IN HI
CH1 IN LO
CH1 IN HI
CH0 IN LO
CH0 IN HI
LLGND

PCI-DAS6023 and PCI-DAS6025 User's Guide

Installing the PCI-DAS6023 or PCI-DAS6025

16-channel single-ended mode pin out
Signal NameGND
CTR2 OUT
CTR2 GATECTR2 CLK
GND
CTR1 OUT
CTR1 GATE
CTR1 CLK
DIO7
DIO6
DIO5
DIO4
DIO3
DIO2
DIO1
DIO0
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
FIRSTPORTC Bit 7 *FIRSTPORTC Bit 6 *FIRSTPORTC Bit 5 *FIRSTPORTC Bit 4 *FIRSTPORTC Bit 3 *FIRSTPORTC Bit 2 *FIRSTPORTC Bit 1 *FIRSTPORTC Bit 0 *FIRSTPORTB Bit 7 *FIRSTPORTB Bit 6 *FIRSTPORTB Bit 5 *FIRSTPORTB Bit 4 *FIRSTPORTB Bit 3 *FIRSTPORTB Bit 2 *FIRSTPORTB Bit 1 *FIRSTPORTB Bit 0 *FIRSTPORTA Bit 7 *FIRSTPORTA Bit 6 *FIRSTPORTA Bit 5 *FIRSTPORTA Bit 4 *FIRSTPORTA Bit 3 *FIRSTPORTA Bit 2 *FIRSTPORTA Bit 1 *FIRSTPORTA Bit 0 *PCI slot ↓

Pin
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

Pin
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

* Not connected on the PCI-DAS6023

14

Signal NameGND
AUXIN5 / A/D PACER GATEAUXIN4 / D/A START TRIGGER
AUXIN3 / D/A UPDATEAUXIN2 / A/D STOP TRIGGER
AUXIN1 / A/D START TRIGGER
n/c
AUXIN0 / A/D CONVERTAUXOUT2 / SCANCLKAUXOUT1 / A/D PACER OUT
AUXOUT0 / D/A PACER OUT
PC +5 VD/A OUT1*
D/A GND*
D/A OUT 0*
AISENSE
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
LLGND
CH15 IN
CH7 IN
CH14 IN
CH6 IN
CH13 IN
CH5 IN
CH12 IN
CH4 IN
CH11 IN
CH3 IN
CH10 IN
CH2 IN
CH9 IN
CH1 IN
CH8 IN
CH0 INLLGND

PCI-DAS6023 and PCI-DAS6025 User's Guide

Installing the PCI-DAS6023 or PCI-DAS6025

Cabling
Pins 1-50 are on the long sideof the “D” connector.

50

Strain relief isstamped “Pins 1-50”.

49

50

1

2

100

Key

The red stripe
identifies pin # 1
99 100

1

51

Key

Pins 51-100 are on
the short side of
the “D” connector.

Strain relief is
Stamped “Pins 51-100”.

51 52

The red stripe
identifies pin # 51

Figure 1. C100HD50-x cable connections
50

100

50

100

1

51

1

51

Figure 2. C100MMS-x cable

Details on these cables are available on our web site at www.mccdaq.com/products/accessories.aspx.

15

PCI-DAS6023 and PCI-DAS6025 User's Guide

Installing the PCI-DAS6023 or PCI-DAS6025

DAQ-Sync connector and pinout
DAQ-sync connector & cable types
Connector typeCompatible cables

14-pin right-angle 100mil box header
MCC p/n: CDS-14-x, 14 pin ribbon cable for board-to board DAQ-sync connection;x = number of boards (from 2 to 5 boards can be connected). See Figure 3.
DAQ-sync connector pinout (view from top)

Signal NameDS A/D START TRIGGER
DS A/D STOP TRIGGER
DS A/D CONVERTDS D/A UPDATEDS D/A START TRIGGER
RESERVEDSYNC CLK

Pin
1
3
5
7
9
11
13

■
■
■
■
■
■
■

■
■
■
■
■
■
■

Pin
2
4
6
8
10
12
14

Signal Name
GND
GND
GND
GND
GND
GND
GND

2
1

The red stripe
identifies pin # 1

2

14

1

13

2

14

1

13
14
13

14-pin Ribbon Cable

Figure 3. CDS-14-3 cable

Field wiring and signal termination accessories
The following Measurement Computing accessory boards can be used with the PCI-DAS6023 and PCIDAS6025:
Screw terminal boards and BNC adapters

Use with the C100HD50-x cable:






BNC-16SE – Brings analog signals to standard BNC connectors. Designed for boards operating in singleended mode.
BNC-16DI – Brings analog signals to standard BNC connectors. Designed for boards operating indifferential mode.
CIO-MINI50 – 50-pin screw terminal board. Two boards are required.
CIO-TERM100 – 100-pin screw terminal board (daisy-chained 50-pin IDC connectors).
SCB-50 – signal connection box, 50 conductor, shielded.

Use with the C100MMS-x cable:


SCB-100 – signal connection box, 100 conductor, shielded.

Details on these products are available on our web site at www.mccdaq.com/products/screw_terminal_bnc.aspx.

16

PCI-DAS6023 and PCI-DAS6025 User's Guide

Installing the PCI-DAS6023 or PCI-DAS6025

ISO-5B module racks

Use with the C100HD50-x cable:

ISO-RACK16/P – 16-channel isolation module mounting rack.
ISO-DA02/P (PCI-DAS6025 only) – Two-channel, 5B module rack.

Details on these products are available on our web site at www.mccdaq.com/products/signal_conditioning.aspx.
Relay racks (requires the DADP-5037 adapter board):

The following products have 37-pin connectors. Use the DADP-5037 adapter board for connections to the
C100HD50-x cable's 50-pin connectors.
SSR-RACK24 – 24-channel solid state I/O module rack.
CIO-ERB24 – 24 Form C, 6A relays.
CIO-ERB08 – Eight Form C, 6A relays.

Details on these products are available on our web site at www.mccdaq.com/products/signal_conditioning.aspx.
Details on the DADP-5037 adapter board are available on our web site atwww.mccdaq.com/products/accessories.aspx.

17

Chapter 3

Functional Details
Basic architecture
Figure 4 shows a simplified block diagram of the PCI-DAS6023 and PCI-DAS6025. The PCI-DAS6025
provides all of the functional elements shown in the diagram. The PCI-DAS6023 does not provide D/A outputs,
and has eight bits of TTL digital I/O rather than the 32 digital inputs/outputs provided by the PCI-DAS6025.
The two boards are identical in all other respects.
The STC (System Timing and Control) is the logical center for all DAQ, DIO, and DAC (if applicable)
operations. It communicates over two major busses, a local bus and a memory bus.
The local bus carries digital I/O data and software commands from the PCI Bus Master. Two Direct Memory
Access (DMA) channels provide data transfers to the PC.
Primarily, the memory bus carries A/D and D/A (PCI-DAS6025 only) related data and commands. There arethree buffer memories provided on the memory bus:The Queue Buffer is an 8K configuration memory. It can be used for storing programmed channel
numbers, gains, and offsets.
The ADC Buffer is an 8K FIFO (First In, First Out) for temporary storage of scanned and converted analog
inputs.
The DAC 16K Buffer can be used for storing data to be output as analog waveforms. (This function only
applies to the PCI-DAS6025.)

Auxiliary input and output interface
The board’s 100-pin I/O connector provides six software-selectable inputs and three software-selectable
outputs. The signals are user-configurable clocks, triggers and gates.
Refer to "DAQ signal timing" on page 21 for additional information and timing requirements for the signals.
The "Auxiliary I/O signals" table on page 19 defines the possible and default signals that can be used on thenine pins.
D/A signals
The D/A signals are applicable to the PCI-DAS6025 only.

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PCI-DAS6023 and PCI-DAS6025 User's Guide

Functional Details

Auxiliary I/O signals
I/O type

Signal name

Function

AUXIN<5:0> sources(software selectable)

A/D CONVERT
A/D EXT. TIMEBASE IN
A/D START TRIGGER
A/D STOP TRIGGER
A/D PACER GATE
D/A START TRIGGER
D/A UPDATE
D/A EXT. TIMEBASE IN
STARTSCAN
SSH

External ADC convert strobe (default)
External ADC pacer time base
ADC Start Trigger (default)
ADC Stop Trigger (default)
External ADC gate (default)
DAC trigger/gate (default) (PCI-DAS6025 only)
DAC update strobe (default) (PCI-DAS6025 only)
External DAC pacer time base (PCI-DAS6025 only)
A pulse indicating start of conversion
Active signal that terminates at the start of the lastconversion in a scan.
Indicates end of an acquisition sequence
ADC convert pulse (default)
Delayed version of ADC convert (default)
CTR1 clock source
D/A update pulse (default) (PCI-DAS6025 only)
CTR2 clock source
ADC Start Trigger Out
ADC Stop Trigger Out
DAC Start Trigger Out
A/D CONVERT
A/D START TRIGGER
A/D STOP TRIGGER
D/A UPDATE (PCI-DAS6025 only)
D/A START TRIGGER (PCI-DAS6025 only)
A/D PACER GATE
D/A UPDATE (PCI-DAS6025 only)
A/D CONVERTSCANCLKAUXOUT<2:0> sources(software selectable)

Default selections
summary

A/D STOP
A/D CONVERTSCANCLKCTR1 CLK
D/A UPDATECTR2 CLK
A/D START TRIGGER
A/D STOP TRIGGER
D/A START TRIGGER
AUXIN0
AUXIN1
AUXIN2
AUXIN3
AUXIN4
AUXIN5
AUXOUT0
AUXOUT1
AUXOUT2

DAQ-Sync signals
The DAQ-Sync hardware provides the capability of triggering or clocking up to four slave boards from a masterboard to synchronize data input and / or output.
The PCI-DAS6023 and PCI-DAS6025 boards provide the capability of inter-board synchronization with otherboards in the PCI-DAS6000 family. There are five trigger/strobes and a synchronizing clock provided on a 14pin header connector. The available signals are:







DS A/D START TRIGGER
DS A/D STOP TRIGGER
DS A/D CONVERTDS D/A UPDATE (PCI-DAS6025 only)
DS D/A START TRIGGER (PCI-DAS6025 only)
SYNC CLK

Except for the SYNC CLK signal, the DAQ-Sync timing and control signals are a subset of the AUXIO signals
available at the 100-pin I/O connector. These versions of the signals are used for board-to-board
synchronization and have the same timing specifications as their I/O connector counterparts. Refer to the "DAQ
signal timing" section on page 21 for explanations of signals and timing.

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PCI-DAS6023 and PCI-DAS6025 User's Guide

Functional Details

Use the SYNC CLCK signal to determine the master/slave configuration of a DAQ-Sync-enabled system. Eachsystem can have one master and up to three slaves. SYNC CLK is the 40 MHz time base used to derive allboard timing and control. The master provides this clock to the slave boards so that all boards in the DAQ-syncenabled system are timed from the same clock.
Holding
Register

Analog In
16 CH S-E or
8 CH DIFF.

Mux
&
Gain

12

12-Bit
ADC

D

Queue
Buffer
(8K)

Q

EOC

ADC
Buffer(8K)

DAC
Buffer(16K)

DAC0

12 BITS(PCI-DAS6025 Only

MEMORY BUS

DAC1

12 BITS

40 MHz

100-Pin I/O CONNECTOR

STC
A/D CONVERT
A/D START TRIGGER

SYSTEM

A/D PACER GATETIMINGA/D PACER OUTSCANCLK&

D/A START TRIGGERCONTROL

D/A UPDATE
D/A PACER OUT

DIO(7:0)

DIO
8 BITS

EXT CTR1 CLK
CTR1 CLK
CTR1 GATEUSER
COUNTER1

CTR1 OUT
CTR2 GATEUSER
COUNTER2

CTR2 OUT

82C54

LOCAL BUS

Control

Boot
EEPROM
FIRSTPORTA (7:0)

FIRSTPORTAFIRSTPORTB (7:0)

82C55

Control

FIRSTPORTCH (7:0)

FIRSTPORTCH

FIRSTPORTCL (7:0)

FIRSTPORTCL

PCI BUS (5V, 32-BIT, 33 MHZ)

24 Bits DIO
PCI-DAS6025 Only

Figure 4. Block diagram – PCI-DAS6025 and PCI-DAS6023

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PCI-DAS6023 and PCI-DAS6025 User's Guide

Functional Details

DAQ signal timing
The primary DAQ timing signals are:








SCANCLKSSH
A/D START TRIGGER
A/D STOP TRIGGER
STARTSCAN
A/D CONVERT
A/D PACER GATESCANCLK signal
SCANCLK is an output signal that may be used for switching external multiplexers. It is a 400 ns-wide pulsethat follows the CONVERT signal after a 50 ns delay. This is adequate time for the analog input signal to beacquired so that the next signal may be switched in. The polarity of the SCANCLK signal is programmable. The
default output pin for the SCANCLK signal is AUXOUT2, but any of the AUXOUT pins may be programmed
as a SCANCLK output.

Figure 5. SCANCLK Signal Timing

A/D START TRIGGER signal
The A/D START TRIGGER signal is used for conventional triggering, that is, when you only need to acquire
data after a trigger event. Figure 6 shows the A/D START TRIGGER signal timing for a conventionallytriggered acquisition.

Figure 6. Data Acquisition Example for Conventional Triggering

The A/D START TRIGGER source is programmable and may be set to any of the AUXIN inputs or to the
DAQ-Sync ―DS A/D START TRIGGER‖ input. The polarity of this signal is also programmable to trigger
acquisitions on either the positive or negative edge.
The A/D START TRIGGER signal is also available as an output and can be programmed to appear at any of the
AUXOUT outputs.

21

PCI-DAS6023 and PCI-DAS6025 User's Guide

Functional Details

See Figure 7 and Figure 8 for A/D START TRIGGER input and output timing requirements.

tw = 37.5 ns
minimum

Figure 7. A/D START TRIGGER input signal timing

Figure 8. A/D START TRIGGER output signal timing

The A/D START TRIGGER signal is also used to initiate pre-triggered DAQ operations, that is, when you needto acquire data just previous to a trigger event. In most pre-triggered applications, the A/D START TRIGGER
signal is generated by a software trigger. Descriptions of the use of A/D START TRIGGER and A/D STOPTRIGGER in pre-triggered DAQ applications follow.

A/D STOP TRIGGER signal
Pre-triggered data acquisition continually acquires data into a circular buffer until a specified number ofsamples after the trigger event. Figure 9 illustrates a typical pre-triggered DAQ sequence.

Figure 9. Pre-triggered data acquisition example

The A/D STOP TRIGGER signal signifies when the circular buffer should stop and when the specified numberof post trigger samples should be acquired. It is available as an output and an input. By default, it is available at
AUXIN2 as an input but may be programmed for access at any of the AUXIN pins or at the DAQ-Sync ―DS
A/D STOP TRIGGER‖ input. It may be programmed for access at any of the AUXOUT pins as an output.
When using the A/D STOP TRIGGER signal as an input, the polarity may be configured for either rising or
falling edge. The selected edge of the A/D STOP TRIGGER signal initiates the post-triggered phase of a pretriggered acquisition sequence.
As an output, the A/D STOP TRIGGER signal indicates the event separating the pre-trigger data from the posttrigger data. The output is an active high pulse with a pulse width of 50 ns. Figure 10 and Figure 11 show the
input and output timing requirements for the A/D STOP TRIGGER signal.
22

PCI-DAS6023 and PCI-DAS6025 User's Guide

Functional Details

tw = 37.5 ns
minimum

Figure 10. A/D STOP TRIGGER input signal timing

Figure 11. A/D STOP TRIGGER output signal timing

STARTSCAN signal
The STARTSCAN output signal indicates when a scan of channels has been initiated. It may be programmed to
be available at any of the AUXOUT pins. The STARTSCAN output signal is a 50 ns wide pulse the leadingedge of which indicates the start of a channel scan.

Figure 12. STARTSCAN start of scan timing

SSH signal
The SSH signal can be used as a control signal for external sample/hold circuits. The SSH signal isprogrammable polarity pulse that is asserted throughout a channel scan. The state of this signal changes after thestart of the last conversion in the scan. The SSH signal may be routed via software selection to any of the
AUXOUT pins. Figure 13 shows the timing for the SSH signal.

Figure 13. SSH signal timing

23

PCI-DAS6023 and PCI-DAS6025 User's Guide

Functional Details

A/D CONVERT signal
The A/D CONVERT signal indicates the start of an A/D conversion. It is available through software selection
as an input to any of the AUXIN pins (defaulting to AUXIN0) or the DAQ-Sync "DS A/D CONVERT" input
and as an output to any of the AUXOUT pins.
When used as an input, the polarity is software selectable. The A/D CONVERT signal starts an acquisition on
the selected edge. The convert pulses must be separated by a minimum of 5 s to remain within the 200 kS/s
conversion rate specification.
Refer back to Figure 6 and Figure 9 for the relationship of A/D CONVERT to the DAQ sequence. Figure 14
and Figure 15 show the input and output pulse width requirements for the A/D CONVERT signal.

tw = 37.5 ns minimum
Figure 14. A/D CONVERT signal input timing requirement

Figure 15. A/D CONVERT signal output timing requirement

The A/D CONVERT signal is generated by the on-board pacer circuit unless the external clock option is in use.
This signal may be gated by external hardware (A/D PACER GATE) or internally via software.

A/D PACER GATE signal
The A/D PACER GATE signal is used to disable scans temporarily. This signal may be programmed for input
at any of the AUXIN pins.
If the A/D PACER GATE signal is active, no scans can occur. If the A/D PACER GATE signal becomes active
during a scan in progress, the current scan is completed and scans are then held off until the gate is de-asserted.

A/D EXTERNAL TIME BASE signal
The A/D EXTERNAL TIME BASE signal can serve as the source for the on-board pacer circuit rather thanusing the 40 MHz internal time base. Any AUXIN pin can be set programmatically as the source for this signal.
The polarity is programmable.
The maximum frequency for the A/D EXTERNAL TIME BASE signal is 20 MHz. The minimum pulse widthis 23 ns high or low. There is no minimum frequency specification.
Figure 16 shows the timing specifications for the A/D EXTERNAL TIME BASE signal.

24

PCI-DAS6023 and PCI-DAS6025 User's Guide

Functional Details

Figure 16. A/D EXTERNAL TIME BASE signal timing

A/D STOP signal
The A/D STOP signal indicates a completed acquisition sequence. You can program this signal to be available
at any of the AUXOUT pins. The A/D STOP output signal is a 50 ns wide pulse whose leading edge indicates a
DAQ done condition.

Figure 17. A/D STOP signal timing

Waveform generation timing connections
There are three signals that control the timing for the analog output functions on the PCI-DAS6025. These are
D/A START TRIGGER, D/A UPDATE, and D/A EXTERNAL TIME BASE signals.

D/A START TRIGGER signal
The D/A START TRIGGER signal is used to hold off output scans until after a trigger event. The DAQ-Sync―DS D/ASTART TRIGGER‖ input or any AUXIN pin can be programmed to serve as the D/A START
TRIGGER signal. It is also available as an output on any AUXOUT pin.
When used as an input, the D/A START TRIGGER signal may be software selected as either a positive or
negative edge trigger. The selected edge of the D/A START TRIGGER signal causes the DACs to start
generating the output waveform.
The D/A START TRIGGER signal can be used as an output to monitor the trigger that initiates waveformgeneration. The output is an active-high pulse having a width of 50 ns.
Figure 18 and Figure 19 show the input and output timing requirements for the D/A START TRIGGER signal.

tw = 37.5 ns
minimum

Figure 18. D/A START TRIGGER input signal timing

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PCI-DAS6023 and PCI-DAS6025 User's Guide

Functional Details

Figure 19. D/A START TRIGGER output signal timing

D/A CONVERT signal
The D/A CONVERT signal causes a single output update on the D/A converters. The DAQ-Sync ―DSD/AUPDATE‖ input or any AUXIN pin can programmed to accept the D/A CONVERT signal. It is also available
as an output on any AUXOUT pin.
The D/A CONVERT input signal polarity is software selectable. DAC outputs will update within 100ns of theselected edge. The D/A CONVERT pulses should be no less than 100 s apart.
When used as an output, the D/A CONVERT signal may be used to monitor the pacing of the output updates.
The output has a pulse width of 225 ns with selectable polarity.
Figure 20 and Figure 21 show the input and output timing requirements for

tw = 37.5 ns
minimum

Figure 20. D/A CONVERT input signal timing

Figure 21. D/A CONVERT output signal timing

D/A EXTERNAL TIME BASE signal
The D/A EXTERNAL TIME BASE signal can serve as the source for the on-board DAC pacer circuit rather
than using the internal time base. Any AUXIN pin can be set programmatically as the source for this signal. The
polarity is programmable.
The maximum frequency for the D/A EXTERNAL TIME BASE signal is 20 MHz. The minimum pulse widthis 23 ns high or low. There is no minimum frequency specification.
Figure 22 shows the timing requirements for the D/A EXTERNAL TIME BASE signal.

26

PCI-DAS6023 and PCI-DAS6025 User's Guide

Functional Details

Figure 22. D/A EXTERNAL TIME BASE signal timing

General-purpose counter signal timing
The general-purpose counter signals are:







CTR1 CLK
CTR1 GATE
CTR1 OUT
CTR2 CLK
CTR2 GATECTR2 OUT

CTR1 CLK signal
The CTR1 CLK signal can serve as the clock source for independent user counter 1. It can be selected throughsoftware at the CTR1 CLK pin rather than using the on-board 10 MHz or 100 kHz sources. It is also polarity
programmable. The maximum input frequency is 10 MHz. There is no minimum frequency specified. Figure 23
shows the timing requirements for the CTR1 CLK signal.

Figure 23. CTR1 CLK signal timing

CTR1 GATE signal
You can use the CTR1 GATE signal for starting and stopping the counter, saving counter contents, etc. It ispolarity programmable and is available at the CTR1 GATE pin. See Figure 24 for the minimum timing
specification.

Figure 24. CTR1 GATE signal timing

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PCI-DAS6023 and PCI-DAS6025 User's Guide

Functional Details

CTR1 OUT signal
This signal is present on the CTR1 OUT pin. The CTR1 OUT signal is the output of one of the two user’s
counters in an industry-standard 82C54 chip. For detailed information on counter operations, refer to the 82C54
data sheet. This data sheet is available on our web site at www.mccdaq.com/PDFmanuals/82C54.pdf
Figure 25 shows the timing of the CTR1 OUT signal for counter mode 0 and mode 2.

Figure 25. CTR1 OUT signal timing

CTR2 CLK signal
The CTR2 CLK signal can serve as the clock source for independent user counter 2. It can be selected throughsoftware at the CTR2 CLK pin rather than using the on-board 10 MHz or 100 kHz sources. It is also polarity
programmable. The maximum input frequency is 10 MHz. There is no minimum frequency specified. Figure 26
shows the timing requirements for the CTR2 CLK signal.

Figure 26. CTR2 CLK Signal Timing

CTR2 GATE signal
You can use the CTR2 GATE signal for starting and stopping the counter, saving counter contents, etc. It ispolarity programmable and is available at the CTR2 GATE pin. Figure 27 shows the timing requirements for
the CTR2 GATE signal.

Figure 27. CTR2 GATE Signal Timing

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PCI-DAS6023 and PCI-DAS6025 User's Guide

Functional Details

CTR2 OUT signal
This signal is present on the CTR2 OUT pin. The CTR2 OUT signal is the output of one of the two user’s
counters in an industry-standard 82C54 chip. For detailed information on counter operations, refer to the 82C54
data sheet. This data sheet is available at www.mccdaq.com/PDFmanuals/82C54.pdf.
Figure 28 shows the timing of the CTR1 OUT signal for mode 0 and for mode 2.

Figure 28. CTR2 OUT signal timing

29

Chapter 4

Calibrating the Board
Introduction
We recommend that you calibrate the board using the InstaCal utility after the board has fully warmed up. The
recommended warm-up time is 15 minutes. For best results, calibrate the board immediately before making
critical measurements. The high resolution analog components on the board are somewhat sensitive totemperature. Pre-measurement calibration insures that your board is operating at optimum calibration values.

Calibration theory
Analog inputs are calibrated for offset and gain. Offset calibration for the analog inputs is performed directly on
the input amplifier, with coarse and fine trim DACs acting on the amplifier.
For input gain calibration, a precision calibration reference is used in conjunction with coarse and fine trim
DACs acting on the ADC. See Figure 29.
Analog In
Gain
Calibration
Reference

ADC

MUX

Gain Adjust
OffsetAdjustTrim DAC
CoarseTrim DAC
Fine
Trim DAC
CoarseTrim DAC
Fine

Figure 29. Analog input calibration

A similar method is used to calibrate the analog output components (PCI-DAS6025 only). A trim DAC is used
to adjust the gain of the DAC. A separate DAC is used to adjust offset on the final output amplifier. The
calibration circuits are duplicated for both analog outputs. See Figure 30.
Analog Out

DAC
Ref

Trim DAC

Gain
AdjustTrim DAC

OffsetAdjustFigure 30. Analog output calibration

30

Chapter 5

Specifications
Typical for 25 °C unless otherwise specified.
Specifications in italic text are guaranteed by design.

Analog inputs
Table 1. Analog input specifications
A/D converter type
Resolution
Number of channels
Input ranges
A/D pacing(SW programmable)

Burst mode
A/D gate sources
A/D gating modes
A/D trigger sources
A/D triggering modes
ADC pacer out
RAM buffer size
Data transfer
DMA modes
Configuration memory
Streaming-to-disk rate

Successive approximation type, min 200 kS/s conversion rate.
12 bits, 1-in-4096
16 single ended / 8 differential. Software selectable±10 V, ±5 V, ±500 mV, ±50 mV. Software selectable
Internal counter – ASIC. Software selectable time base: Internal 40 MHz, 50 ppm stability
External source via AUXIN<5:0>. Software selectable.
External convert strobe: A/D CONVERT
Software paced
Software selectable option, burst rate = 5 µS.
External digital: A/D GATE
External digital: Programmable, active high or active low, level or edge
External digital: A/D START TRIGGER
A/D STOP TRIGGER
External digital: Software-configurable for rising or falling edge.
Pre-/Post-trigger: Unlimited number of pre-trigger samples, 16 Meg post-trigger samples.
Available at user connector: A/D PACER OUT
8 k samples
DMA
Programmed I/ODemand or non-demand using scatter gather.
Up to 8 k elements. Programmable channel, gain, and offset
200 kS/s, system dependent

Accuracy
200 kS/s sampling rate, single channel operation and a 15-minute warm-up. Accuracies listed are formeasurements made following an internal calibration. They are valid for operational temperatures within ±1 °C
of internal calibration temperature, and ±10 °C of factory calibration temperature. Calculations for Absolute
Accuracy are based on the average of 100 measurements performed at the max input voltage for a given range,measured after one year. Calibrator test source high side tied to channel 0 high, and low side tied to channel 0
low. Low-level ground is tied to channel 0 low at the user connector.
Table 2. Absolute accuracy specifications
Range

Absolute Accuracy

±10 V
±5 V
±500 mV±50 mV±2.0 LSB±2.0 LSB±3.0 LSB±4.0 LSB

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PCI-DAS6023 and PCI-DAS6025 User's Guide

Specifications

Table 3. Absolute accuracy components - all values are (±)
Range

% of
Reading

Offset(mV)

Averaged Noise +Quantization (mV)1

Temp Drift(%/ C)

Absolute Accuracy
at FS (mV)

±10 V
±5 V
±500 mV±50 mV

0.05580.05630.10460.1340

2.930
1.460
0.150
0.024

1.262
0.605
0.057
0.007

0.00100.00100.00100.0010

9.77
4.88
0.73
0.098

1

Averaged measurements assume dithering and averaging of 100 single-channel readings.
Table 4. Differential non-linearity specifications

All ranges±0.5 LSB typ±1.0 LSB max

System throughput
Table 5. System throughput specifications
Condition

Calibration Coefficients

ADC Rate (max)

1. 1. Single channel, single input range.
2. 2. Multiple channel, single input range
3. 3. Single channel, multiple input
ranges.

Per specified range
Per specified range
Default to value for cbAInScan() range

200 kS/s
200 kS/s
200 kS/s

Note 1:For conditions 1-2 above, specified accuracy is maintained at rated throughput. Condition 3
applies a calibration coefficient which corresponds to the range value selected in cbAInScan().
This coefficient remains unchanged throughout the scan. Increased settling times may occur
during gain-switching operations.

Settling time
Settling time is defined here as the time required for a channel to settle to within a specified accuracy inresponse to a full-scale (FS) step. Two channels are scanned at a specified rate. A –FS DC signal is presented tochannel 1; a +FS DC signal is presented to channel 0.
Table 6. Settling time specifications
Condition

Same range to same range

Any range to any range

Range

±10 V
±5 V
±500 mV±50 mV-

Accuracy±0.012%(±0.5 LSB)

±0.024%(±1.0 LSB)

±0.098%(±4.0 LSB)

5 µS typ5 µS typ5 µS typ5 µS typ25 µS typ5 µS max
5 µS max
5 µS max
5 µS max
20 µS typ5 µS max
5 µS max
5 µS max
5 µS max
15 µS typ32

PCI-DAS6023 and PCI-DAS6025 User's Guide

Specifications

Parametrics
Table 7. Parametrics specifications
Maximum working voltage(signal + common-mode)
CMRR @ 60 Hz

Small signal bandwidth, all ranges
Large signal bandwidth, all ranges
Input coupling
Input impedance
Input bias current
Input offset current
Absolute maximum input voltage
Crosstalk

Input must remain within ±11 V of ground±10 V:
85 dB
±5 V:
85 dB
±500 mV:
90 dB±50 mV:
90 dB
500 kHz225 kHzDC
100 GOhm in normal operation.
Min 10 MOhm in powered off or overload condition.
±200 pA±100 pA–40 V to +55 V, power on or off. Protected inputs: CH<15:0> IN
 AISENSE
Adjacent channels: -60 dB
All other channels: -80 dB

Noise performance
Table 8 summarizes the noise performance for the PCI-DAS6025, PCI-DAS6023. Noise distribution isdetermined by gathering 50 K samples with inputs tied to ground at the user connector. Samples are gathered at
the maximum specified single-channel sampling rate. Specification applies to both single-ended and differential
modes of operation.
Table 8. Analog input noise performance (not including quantization)
Range

Typical Counts
Dithered

LSBrmsDithered

Typical Counts
Undithered

LSBrms
Undithered

±10 V
±5 V
±500 mV±50 mV

4
4
4
7

0.6
0.6
0.6
0.8

2
2
3
4

0.1
0.1
0.1
0.7

33

PCI-DAS6023 and PCI-DAS6025 User's Guide

Specifications

Analog outputs (PCI-DAS6025 only)
Table 9. Analog output specifications (PCI-DAS6025)
D/A converter type
Resolution
Number of channels
Voltage range
Monotonicity
DNL
Slew rate
Settling time
Noise
Glitch energy
Current drive
Output short-circuit duration
Output coupling
Output impedancePower up and reset

Double-buffered, multiplying
12-bits, 1-in-4096
2 voltage output±10 V
12-bits, guaranteed monotonic±1.0 LSB max
10 V/µs min
20 V step to 0.012% (0.5 LSB): 10 µs max
200 µVrms, DC to 1 MHz BW±24 mV @ 2 µs duration measured at mid-scale transition.
±5 mA
Indefinite @25 mA
DC
0.1 ohms max
DACs cleared to 0 volts ±200 mV max
Table 10. Absolute accuracy specifications

Range

Absolute Accuracy±10 V±1.7 LSB
Table 11. Absolute accuracy components

Range% of Reading

Offset(mV)

Temp Drift(%/DegC)

Absolute Accuracy at FS (mV)

±10 V

±0.0219±5.93±0.0005±8.127

Each PCI-DAS6025 is tested at the factory to assure the board’s overall error does not exceed ±1.7 LSB.
Table 12. Relative accuracy specifications
Range

Relative Accuracy±10 V±0.3 LSB, typical±0.5 LSB, max

Relative accuracy is defined as the measured deviation from a straight line drawn between measured endpointsof the transfer function.

34

PCI-DAS6023 and PCI-DAS6025 User's Guide

Specifications

Analog output pacing and triggering
Table 13. Analog output pacing and triggering specifications
DAC pacing(software programmable)

Internal counter – ASIC. Selectable time base: Internal 40 MHz, 50 ppm stability.
 External source via AUXIN<5:0>, SW selectable.
External convert strobe: D/A UPDATE
Software paced
External digital: D/A START TRIGGER
Software gatedExternal digital: Programmable, active high or active low, level or edge
External digital: D/A START TRIGGER
Software triggered
External digital: Software-configurable for rising or falling edge.
Available at user connector: D/A PACER OUT
16 K samples
DMA
Programmed I/OUpdate DACs individually or simultaneously, software selectable.
Demand or non-demand using scatter gather.
10 kS/s max per channel, 2 channels simultaneous

DAC gate source(software programmable)
DAC gating modes
DAC trigger sources
DAC triggering modes
DAC pacer out
RAM buffer size
Data transfer

DMA modes
Waveform generation throughput

Analog input/output calibration
Table 14. Analog I/O calibration specifications
Recommended warm-up time
Calibration
Onboard calibration reference

Calibration interval

15 minutes
Auto-calibration, calibration factors for each range stored on board in non-volatileRAM.
DC Level: 10.000 V ± 5 mV. Actual measured values stored in EEPROM.
Tempco: 5 ppm/°C max, 2 ppm/°C typicalLong-term stability: 15 ppm, T = 1000 hrs, non-cumulative
1 yearDigital input/output
Discrete
Table 15. Discrete DIO specifications
Digital type
Number of I/O
Configuration
Input high voltage
Input low voltage
Output high voltage(IOH = -32 mA)
Output low voltage (IOL = 32 mA)
Data transfer
Power-up / reset state

Discrete, 5V/TTL compatible
8
8 bits, independently programmable for input or output. All pins pulled up to +5 V
via 47 K resistors (default). Positions available for pull-down to ground (factory
configured option).
2.0 V min, 7.0 V absolute max
0.8 V max, –0.5 V absolute min
3.80 V min, 4.20 V typ
0.55 V max, 0.22 V typ
Programmed I/O
Input mode (high impedance)

35

PCI-DAS6023 and PCI-DAS6025 User's Guide

Specifications

82C55 (PCI-DAS6025 only)
Table 16. 82C55 specifications (PCI-DAS6025)
Digital type
Number of I/O
Configuration

Pull up/pull-down configuration
Input high voltage
Input low voltage
Output high voltage (IOH = -2.5 mA)
Output low voltage (IOL = 2.5 mA)
Power-up / reset state

82C55
24 (FIRSTPORTA 0 through FIRSTPORTC 7)
2 banks of 8 and 2 banks of 4 or
3 banks of 8 or
2 banks of 8 with handshake
All pins pulled up to +5 V via 47 K resistors (default). Positions available forpull-down to ground (factory configured option).
2.0 V min, 5.5 V absolute max
0.8 V max, –0.5 V absolute min
3.0 V min
0.4 V max
Input mode (high impedance)

Interrupts
Table 17. Interrupt specifications
Interrupts
Interrupt enable
ADC Interrupt sources(software programmable)

DAC Interrupt sources(software programmable)

PCI INTA# - mapped to IRQn via PCI BIOS at boot-time
Programmable through PLX9080
DAQ_ACTIVE:
Interrupt is generated when a DAQ sequence is active.
DAQ_STOP:Interrupt is generated when A/D Stop Trigger In is
detected.
DAQ_DONE:Interrupt is generated when a DAQ sequence completes.
DAQ_FIFO_1/4_FULL:
Interrupt is generated when ADC FIFO is ¼ full.
DAQ_SINGLE:
Interrupt is generated after each conversion completes.
DAQ_EOSCAN:
Interrupt is generated after the last channel is converted in
multi-channel scans.
DAQ_EOSEQ:
Interrupt is generated after each interval delay duringmulti-channel scans.
DAC_ACTIVE:
Interrupt is generated when DAC waveform circuitry is
active.
DAC_DONE:Interrupt is generated when a DAC sequence completes.
DAC_FIFO_1/4_EMPTY: Interrupt is generated DAC FIFO is ¼ empty.
DAC_HIGH_CHANNEL: Interrupt is generated when the DAC high channel output
is updated.

36

PCI-DAS6023 and PCI-DAS6025 User's Guide

Specifications

Counters
Table 18. Counter specifications
User counter type
Number of channels
Resolution
Compatibility
CTRn base clock source (software selectable)
Internal 10 MHz clock source stability
Counter n gate
Counter n output
Clock input frequency
High pulse width (clock input)
Low pulse width (clock input)
Gate width highGate width low
Input low voltage
Input high voltage
Output low voltage
Output high voltage

82C54
216-bits
5 V/TTL
Internal 10 MHz, Internal 100 KHz or external connector (CTRn CLK)50 ppmAvailable at connector (CTRn GATE).
Available at connector (CTRn OUT).
10 MHz max
15 ns min
25 ns min
25 ns min
25 ns min
0.8 V max
2.0 V min
0.4 V max
3.0 V min37

PCI-DAS6023 and PCI-DAS6025 User's Guide

Specifications

Configurable AUXIN<5:0>, AUXOUT<2:0> external trigger/clocks
The PCI-DAS6023 and PCI-DAS6025 provide nine user-configurable trigger/clock pins available at the
100-pin I/O connector. Of these, six are configurable as inputs while three are configurable as outputs.
Table 19. Configurable AUXIN, AUXOUT, and external trigger/clocks
AUXIN<5:0> sources(software selectable)

AUXOUT<2:0> sources(software selectable)

Default selections:Compatibility
Edge-sensitive polarity
Level-sensitive polarity
Minimum input pulse width

A/D CONVERT:
A/D TIMEBASE IN:
A/D START TRIGGER:
A/D STOP TRIGGER:
A/D PACER GATE:
D/A START TRIGGER
D/A UPDATE:
D/A TIMEBASE IN:
STARTSCAN:
SSH:

External ADC convert strobe
External ADC pacer time base
ADC Start Trigger
ADC Stop Trigger
External ADC gate
DAC trigger/gate
DAC update strobe
External DAC pacer time base
A pulse indicating start of conversion
Active signal that terminates at the start of thelast conversion in a scan.
Indicates end of scan
ADC convert pulse
Delayed version of ADC convert
CTR1 clock source
D/A update pulse
CTR2 clock source
ADC Start Trigger Out
ADC Stop Trigger Out
DAC Start Trigger Out
A/D CONVERT
A/D START TRIGGER
A/D STOP TRIGGER
D/A UPDATE
D/A START TRIGGER
A/D PACER GATE
D/A UPDATE
A/D CONVERTSCANCLK

A/D STOP:
A/D CONVERT:SCANCLK:CTR1 CLK:
D/A UPDATE:CTR2 CLK:
A/D START TRIGGER:
A/D STOP TRIGGER:
D/A START TRIGGER:
AUXIN0:
AUXIN1:
AUXIN2:
AUXIN3:
AUXIN4:
AUXIN5:
AUXOUT0:
AUXOUT1:
AUXOUT2:
5V/TTL
Rising/falling, software selectable
Active high/active low, software selectable
37.5 ns38

PCI-DAS6023 and PCI-DAS6025 User's Guide

Specifications

DAQ-Sync inter-board triggers/clocks
The DAQ-Sync bus provides inter-board triggering and synchronization capability. Five trigger/strobe I/O pins
and one clock I/O pin are provided on a 14-pin header. The DAQ-Sync signals use dedicated pins. Only the
direction may be set.
Table 20. DAQ-Sync inter-board triggers/clock specifications
DAQ-Sync signals:

DS A/D START TRIGGER
DS A/D STOP TRIGGER
DS A/D CONVERTDS D/A UPDATEDS D/A START TRIGGERSYNC CLKPower consumption
Table 21. Power consumption specifications+5 V+5 V available at I/O connector

PCI-DAS6025, PCI-DAS6023: 0.9 A typical, 1.1 A max. Does not include
power consumed through the I/O connector.
1 A max, protected with a resettable fuse

Environmental
Table 22. Environmental specifications
Operating temperature range
Storage temperature range
Humidity

0 to 55 °C-20 to 70 °C
0 to 90% non-condensing

Mechanical
Table 23. Mechanical specifications
Card dimensions

PCI half card: 174.6 mm (L) x 106.9 mm (W) x 11.65 mm (H)39

PCI-DAS6023 and PCI-DAS6025 User's Guide

Specifications

DAQ-Sync connector and pin out
Table 24. DAQ-Sync connector specifications
Connector typeCompatible cables

14-pin right-angle 100 mil box header
MCC p/n: CDS-14-x, 14-pin ribbon cable.
x = number of boards
Table 25. DAQ-Sync connector pin out

Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14

Signal NameDS A/D START TRIGGER
GND
DS A/D STOP TRIGGER
GND
DS A/D CONVERTGND
DS D/A UPDATEGND
DS D/A START TRIGGER
GND
RESERVEDGND
SYNC CLK
GND

Main connector and pin out
Table 26. Main connector specifications
Connector typeCompatible cables
Compatible accessory products(with C100HD50-x cable)

Compatible accessory products(with C100MMS-x cable)

Shielded SCSI 100 D-Type
C100HD50-x, unshielded ribbon cable. x = 3 or 6 feet
C100MMS-x, shielded round cable. x = 1, 2 or 3 meters
ISO-RACK16/P
ISO-DA02/P (PCI-DAS6025 only)
BNC-16SE
BNC-16DI
CIO-MINI50
CIO-TERM100
SCB-50SSR-RACK24 (PCI-DAS6025 only, with DADP-5037)
CIO-ERB24 (PCI-DAS6025 only, with DADP-5037)
CIO-ERB08 (PCI-DAS6025 only, with DADP-5037)
SCB-100

40

PCI-DAS6023 and PCI-DAS6025 User's Guide

Specifications

Table 27. 8-channel differential mode pin out
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50

Signal Name
LLGND
CH0 IN HI
CH0 IN LO
CH1 IN HI
CH1 IN LO
CH2 IN HI
CH2 IN LO
CH3 IN HI
CH3 IN LO
CH4 IN HI
CH4 IN LO
CH5 IN HI
CH5 IN LO
CH6 IN HI
CH6 IN LO
CH7 IN HI
CH7 IN LO
LLGND
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
AISENSED/A OUT 0*
D/A GND*
D/A OUT1*
PC +5 V
AUXOUT0 / D/A PACER OUT
AUXOUT1 / A/D PACER OUT
AUXOUT2 / SCANCLKAUXIN0 / A/D CONVERTn/c
AUXIN1 / A/D START TRIGGER
AUXIN2 / A/D STOP TRIGGER
AUXIN3 / D/A UPDATEAUXIN4 / D/A START TRIGGER
AUXIN5 / A/D PACER GATE
GND

Pin
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100

* = N/C on PCI-DAS6023

41

Signal Name
FIRSTPORTA Bit 0 *FIRSTPORTA Bit 1 *FIRSTPORTA Bit 2 *FIRSTPORTA Bit 3 *FIRSTPORTA Bit 4 *FIRSTPORTA Bit 5 *FIRSTPORTA Bit 6 *FIRSTPORTA Bit 7 *FIRSTPORTB Bit 0 *FIRSTPORTB Bit 1 *FIRSTPORTB Bit 2 *FIRSTPORTB Bit 3 *FIRSTPORTB Bit 4 *FIRSTPORTB Bit 5 *FIRSTPORTB Bit 6 *FIRSTPORTB Bit 7 *FIRSTPORTC Bit 0 *FIRSTPORTC Bit 1 *FIRSTPORTC Bit 2 *FIRSTPORTC Bit 3 *FIRSTPORTC Bit 4 *FIRSTPORTC Bit 5 *FIRSTPORTC Bit 6 *FIRSTPORTC Bit 7 *
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
DIO0
DIO1
DIO2
DIO3
DIO4
DIO5
DIO6
DIO7
CTR1 CLK
CTR1 GATE
CTR1 OUTGND
CTR2 CLK
CTR2 GATECTR2 OUT
GND

PCI-DAS6023 and PCI-DAS6025 User's Guide

Specifications

Table 28. 16-channel single-ended mode pin out
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50

Signal Name
LLGND
CH0 IN
CH8 IN
CH1 IN
CH9 INCH2 IN
CH10 IN
CH3 IN
CH11 IN
CH4 IN
CH12 IN
CH5 IN
CH13 IN
CH6 IN
CH14 IN
CH7 IN
CH15 IN
LLGND
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
AISENSED/A OUT 0*
D/A GND*
D/A OUT1*
PC +5 V
AUXOUT0 / D/A PACER OUT
AUXOUT1 / A/D PACER OUT
AUXOUT2 / SCANCLKAUXIN0 / A/D CONVERTn/c
AUXIN1 / A/D START TRIGGER
AUXIN2 / A/D STOP TRIGGER
AUXIN3 / D/A UPDATEAUXIN4 / D/A START TRIGGER
AUXIN5 / A/D PACER GATE
GND

Pin
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100

* = N/C on PCI-DAS6023

42

Signal Name
FIRSTPORTA Bit 0 *FIRSTPORTA Bit 1 *FIRSTPORTA Bit 2 *FIRSTPORTA Bit 3 *FIRSTPORTA Bit 4 *FIRSTPORTA Bit 5 *FIRSTPORTA Bit 6 *FIRSTPORTA Bit 7 *FIRSTPORTB Bit 0 *FIRSTPORTB Bit 1 *FIRSTPORTB Bit 2 *FIRSTPORTB Bit 3 *FIRSTPORTB Bit 4 *FIRSTPORTB Bit 5 *FIRSTPORTB Bit 6 *FIRSTPORTB Bit 7 *FIRSTPORTC Bit 0 *FIRSTPORTC Bit 1 *FIRSTPORTC Bit 2 *FIRSTPORTC Bit 3 *FIRSTPORTC Bit 4 *FIRSTPORTC Bit 5 *FIRSTPORTC Bit 6 *FIRSTPORTC Bit 7 *
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
DIO0
DIO1
DIO2
DIO3
DIO4
DIO5
DIO6
DIO7
CTR1 CLK
CTR1 GATE
CTR1 OUTGND
CTR2 CLK
CTR2 GATECTR2 OUT
GND

Declaration of Conformity
Manufacturer:
Address:

Category:

Measurement Computing Corporation
10 Commerce Way
Suite 1008
Norton, MA 02766
USAElectrical equipment for measurement, control and laboratory use.

Measurement Computing Corporation declares under sole responsibility that the product

PCI-DAS6023 and PCI-DAS6025
to which this declaration relates is in conformity with the relevant provisions of the following standards or otherdocuments:
EC EMC Directive 2004/108/EC: General Requirements, EN 61326-1:2006 (IEC 61326-1:2005).
Emissions:EN 55011 (2007) / CISPR 11(2003): Radiated emissions: Group 1, Class A
EN 55011 (2007) / CISPR 11(2003): Conducted emissions: Group 1, Class A

Immunity: EN 61326-1:2006, Table 3.







IEC 61000-4-2 (2001): Electrostatic Discharge immunity.
IEC 61000-4-3 (2002): Radiated Electromagnetic Field immunity.
IEC 61000-4-4 (2004): Electric Fast Transient Burst Immunity.
IEC 61000-4-5 (2001): Surge Immunity.
IEC 61000-4-6 (2003): Radio Frequency Common Mode Immunity.
IEC 61000-4-11 (2004): Voltage Interrupts.

To maintain compliance to the standards of this declaration, the following conditions must be met.






The host computer, peripheral equipment, power sources, and expansion hardware must be CE
compliant.
All I/O cables must be shielded, with the shields connected to ground.
I/O cables must be less than 3 meters (9.75 feet) in length.
The host computer must be properly grounded.
Equipment must be operated in a controlled electromagnetic environment as defined by Standards EN
61326-1:2006, or IEC 61326-1:2005.

Declaration of Conformity based on tests conducted by Chomerics Test Services, Woburn, MA 01801, USA in
May, 2004. Test records are outlined in Chomerics Test Report #EMI3889.04. Further testing was conducted by
Chomerics Test Services, Woburn, MA. 01801, USA in January, 2009. Test records are outlined in Chomerics
Test report #EMI5243.09.
We hereby declare that the equipment specified conforms to the above Directives and Standards.

Carl Haapaoja, Director of Quality Assurance

Measurement Computing Corporation
10 Commerce Way
Suite 1008
Norton, Massachusetts 02766(508) 946-5100
Fax: (508) 946-9500
E-mail: info@mccdaq.com
www.mccdaq.com