PCI-DAS1002

Specifications

Document Revision 1.4, February, 2010
© Copyright 2010, Measurement Computing CorporationSpecifications
Typical for 25 °C unless otherwise specified.
Specifications in italic text are guaranteed by design.

Analog input
Table 1. Analog input specifications
Parameter
A/D converter typeResolution
Number of channels
Input ranges
A/D pacing(software programmable)

A/D trigger sources
A/D triggering modes
A/D pre-trigger mode
Burst mode
Data transfer
A/D conversion time
Analog front end settling time
Calibrated throughput
Calibration
A/D full-scale gain drift
A/D zero drift
Common mode range
CMRR @ 60 Hz
Input leakage current
Input impedance
Absolute maximum input
voltageWarm-up time

Specification
ADS7800 or equivalent
12 bits
16 single-ended / 8 differential, software selectable±10 V, ±5 V, ±2.5 V, ±1.25 V, 0 to 10 V, 0 to 5V, 0 to 2.5 V, 0 to 1.25 V software
programmable
Internal counter - 82C54.
External source (A/D External Pacer)
software programmable for rising or falling edge
Software polled
External edge trigger (A/D EXTERNAL TRIGGER)
Rising edge trigger
Unlimited pre- and post-trigger samples. Total number of samples must be greater than512.
Software selectable option, burst rate = 150 kHz
From 1024 sample FIFO via REPINSW
Programmed I/O
3 µs max
6 µs for a full scale step to 1 LSB
200 kHz
Auto-calibration, calibration factors for each range stored on board in nonvolatile RAM±0.25 LSB/°C max±0.25 LSB/°C max±10 V min-70 dB min±20 nA max
10 MOhms min±35 volts
15 minutes

1Specifications

PCI-DAS1002

Accuracy
Accuracies are listed for a 200 kHz sampling rate, 100 sample average, single channel operation, a 15 minutewarm-up, and operational temperatures within ±2 C of internal calibration temperature. The calibrator test
source high side is tied to Channel 0 In and the low side is tied to AGND.
Table 2. Absolute accuracy specifications (analog input)
Range±10.00 V±5.000 V±2.500 V±1.250 V
0 to 10.00 V
0 to 5.000 V
0 to 2.500 V
0 to 1.250 V

Absolute Accuracy±2.5 LSB max±2.5 LSB max±2.5 LSB max±2.5 LSB max±2.5 LSB max±2.5 LSB max±2.5 LSB max±2.5 LSB max

Each PCI-DAS1002 is tested at the factory to assure the board’s overall error does not exceed accuracy limits
described in Table 2 above.
Table 3. Calibrated accuracy components (in LSB)
Range
All ranges

Gain Error±1.0 max

Offset Error±1.0 max

DLE±0.75 max

ILE
±0.5 max

As shown in Table 3, total board error is a combination of gain, offset, differential linearity and integral
linearity error. The theoretical worst-case error of the board may be calculated by summing these componenterrors. Worst case errors are realized only in the unlikely event that each of the component errors are at theirmaximum level, and causing error in the same direction.

Crosstalk
Crosstalk is defined here as the influence of one channel upon another when scanning two channels at themaximum rate. A full scale 100 Hz triangle wave is input on channel 1; Channel 0 is tied to analog ground at
the 100-pin user connector. The table below summarizes the influence of channel 1 on channel 0 with theeffects of noise removed. The residue on channel zero is described in LSB’s.
Table 4. Crosstalk specifications
Condition
All ranges

Crosstalk
2 LSB pk-pk

Per channel Rate
100 kHzADC Rate
200 kHz

Noise performance
Table 5 below summarizes the noise performance for the PCI-DAS1002. Noise distribution is determined bygathering 50 K samples at 200 kHz with inputs tied to ground at the user connector.
Table 5. Board noise performanceRange
0 to 1.250 V
All other ranges% within ±2 LSB
100%100%% within ±1 LSB
99%100%* RMS noise is defined as the peak-to-peak bin spread divided by 6.6.

2LSBs
43LSBrms*0.610.45

Specifications

PCI-DAS1002

Analog output
Table 6. Analog output specifications
D/A converter typeResolution
Number of channels
Configuration
Output range
D/A pacing
Data transfer
Monotonicity
Overall analog output drift
Settling timeSlew rate
Current drive
Output short-circuit duration
Output coupling
Output impedance
Miscellaneous

AD7847AR or equivalent
12 bits2
Voltage output, single-ended±10 V, ±5 V, 0 to 10 V, or 0 to 5 V. Software selectable. Each channel independently
programmable.
Software
Programmed I/O
Guaranteed monotonic over temperature±0.03 LSB/°C max
4 µs to 0.01% of 10 V step
7 V/µs min±5 mA minIndefinite @25 mA
DC0.1 Ohm, max
Double buffered output latches
Output voltage on power up and reset: ±200 mV

Absolute accuracy
Table 7. Absolute accuracy specifications (analog output)
All ranges±3 LSB

Calibrated accuracy components
Table 8. Calibrated accuracy specifications (analog output)
Gain error
Offset error
Integral linearity error
Differential linearity error±1.0 LSB max±0.5LSB max±1.0 LSB max±1.0 LSB max

Each PCI-DAS1002 is tested at the factory to assure absolute accuracy.
Total analog output error is a combination of gain, offset, integral linearity and differential linearity error. The
theoretical worst-case error of the board may be calculated by summing these component errors. Worst caseerror is realized only in the unlikely event that each of the component errors are at their maximum level, andcausing error in the same direction. Although an examination of the chart and a summation of the maximum
theoretical errors shows that the board could theoretically exhibit a ±3.5 LSB error, our testing assures this error
is never realized in a board that we ship.

3

Specifications

PCI-DAS1002

Counters
Table 9. Counter specifications
Parameter
Counter type
Configuration
82C54A:Counter 0 - ADC residual
sample counter
Counter 1 - ADC pacer lower
dividerCounter 2 - ADC pacer upperdivider

82C54B:Counter 0 - pretrigger mode

Counter 0 - user counter 4(when in non-pretrigger mode)

Counter 1 - user counter 5Counter 2 - user counter 6

Clock input frequency
High pulse width (clock input)
Low pulse width (clock input)
Gate width highGate width low
Input low voltage
Input high voltage
Output low voltage
Output high voltage
Crystal oscillator frequency
Frequency accuracy

Specification
82C54
Two 82C54 devices. 3 down counters per 82C54, 16 bits each
Source:
ADC Clock
Gate:
Internal programmable source
Output:End-of-Acquisition interrupt
Source:10 MHz oscillator
Gate:
Tied to counter 2 gate, programmable source
Output:Chained to counter 2 clock
Source:Counter 1 output
Gate:
Tied to counter 1 gate, programmable source
Output:
ADC pacer clock (if software selected). Available atuser connector.
Source:
ADC clock
Gate:
External trigger
Output:End-of-Acquisition interrupt
Source:User input at 100-pin connector (CTR4 CLK)or internal 10 MHz (software selectable)
Gate:
User input at 100-pin connector (CTR4 GATE)
Output:Available at 100-pin connector (CTR4 OUT)
Source:User input at 100-pin connector (CTR5 CLK)
Gate:
User input at 100-pin connector (CTR5 GATE)
Output:Available at 100-pin connector (CTR5 OUT)
Source:User input at 100-pin connector (CTR6 CLK)Gate:
User input at 100-pin connector (CTR6 GATE)
Output:Available at 100-pin connector (CTR6 OUT)
10 MHz max
30 ns min
50 ns min
50 ns min
50 ns min
0.8 V max
2.0 V min
0.4 V max
3.0 V min
10 MHz50 ppm

4Specifications

PCI-DAS1002

Digital input/output
Table 10. DIO specifications
Digital type
Number of I/O
Configuration

Input high voltage
Input low voltage
Output high voltage (IOH = -2.5 mA)
Output low voltage (IOL = 2.5 mA)
Power-up / reset state

82C55
24 (FIRSTPORTA Bit 0 through FIRSTPORTC Bit 7)
2 banks of 8 and 2 banks of 4 or
3 banks of 8 or
2 banks of 8 with handshake
2.0 V min, 5.5 V absolute max
0.8 V max, –0.5 V absolute min
3.0 V min
0.4 V max
Input mode (high impedance)

Interrupts
Table 11. Interrupt specifications
Interrupts

PCI INTA# – mapped to IRQn via PCI BIOS at boot-time

Interrupt enable
Interrupt sources

Programmable. Default = disabled.
Residual sample counter
A/D End-of-channel-scan
A/D FIFO-not-empty
A/D FIFO-half-full
A/D Pacer

Miscellaneous
Table 12. Micellaneous specifications+5 Volts+12 Volts-12 Volts

Available at I\O connector (PC +5V)
Available at I\O connector (PC +12V)
Available at I\O connector (PC –12V)

Power consumption
Table 13. Power consumption specifications+5 V

0.8 A typical, 1.0 A max

Environmental
Table 14. Environmental specifications
Operating temperature range
Storage temperature range
Humidity

0 to 70 °C-40 to 100 °C
0 to 95% non-condensing

Mechanical
Table 15. Mechanical specifications
Card dimensions

PCI half card: 174.63 mm (L) x 106.86 mm (H) x 14.48 mm (D)5Specifications

PCI-DAS1002

Connector and pin out
Table 16. Main connector specifications
Connector typeCompatible cableCompatible accessory products(with C100FF-x cable)

100-pin high-density Robinson Nugent
C100FF-x, unshielded ribbon cable. x = length in feet
ISO-RACK16/P
ISO-DA02/P
CIO-ERB24 (DADP-5037 adaptor required)
CIO-SERB24/FD (DADP-5037 adaptor required)
SSR-RACK24 (DADP-5037 adaptor required)BNC-16SE
BNC-16DI
CIO-MINI50 (2 required)
CIO-TERM100 (1 required)
SCB-50 (1 required)8-channel differential mode pin out
Pin

Signal Name

Pin

Signal Name

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LLGND
CH0 HI
CH0 LOCH1 HI
CH1 LOCH2 HI
CH2 LOCH3 HI
CH3 LOCH4 HI
CH4 LOCH5 HI
CH5 LOCH6 HI
CH6 LOCH7 HI
CH7 LO
LLGND
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
D/A GND 0D/A OUT 0D/A GND 1
D/A OUT 1CTR4 CLK
CTR4 GATECTR4 OUT
A/D EXTERNAL PACER
N/C
N/C
A/D EXTERNAL TRIGGER IN
N/CN/CPC +5V
N/C
GND

51525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100

FIRSTPORTA Bit 0
FIRSTPORTA Bit 1
FIRSTPORTA Bit 2
FIRSTPORTA Bit 3
FIRSTPORTA Bit 4
FIRSTPORTA Bit 5
FIRSTPORTA Bit 6
FIRSTPORTA Bit 7
FIRSTPORTB Bit 0
FIRSTPORTB Bit 1
FIRSTPORTB Bit 2FIRSTPORTB Bit 3
FIRSTPORTB Bit 4
FIRSTPORTB Bit 5
FIRSTPORTB Bit 6
FIRSTPORTB Bit 7
FIRSTPORTC Bit 0
FIRSTPORTC Bit 1
FIRSTPORTC Bit 2
FIRSTPORTC Bit 3
FIRSTPORTC Bit 4
FIRSTPORTC Bit 5
FIRSTPORTC Bit 6FIRSTPORTC Bit 7
N/C
N/C
N/C
N/C
N/C
CTR6 CLKCTR6 GATECTR6 OUT
N/C
N/C
CTR5 CLK
CTR5 GATE
CTR5 OUT
N/C
GND
+12V
GND
-12V
N/C
N/C
A/D INTERNAL PACER OUTPUT
N/C
N/C
N/C
N/C
GND

6Specifications

PCI-DAS1002

16-channel single-ended mode pin out
PinSignal Name

PinSignal Name

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LLGND
CH0 HI
CH8 HICH1 HI
CH9 HICH2 HI
CH10 HI
CH3 HI
CH11 HI
CH4 HI
CH12 HICH5 HI
CH13 HICH6 HI
CH14 HI
CH7 HI
CH15 HI
LLGND
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
D/A GND 0D/A OUT 0D/A GND 1D/A OUT 1
CTR4 CLK
CTR4 GATECTR4 OUT
A/D EXTERNAL PACER
N/CN/CA/D EXTERNAL TRIGGER IN
N/CN/CPC +5V
N/CGND51525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100

FIRSTPORTA Bit 0
FIRSTPORTA Bit 1
FIRSTPORTA Bit 2
FIRSTPORTA Bit 3
FIRSTPORTA Bit 4
FIRSTPORTA Bit 5
FIRSTPORTA Bit 6
FIRSTPORTA Bit 7
FIRSTPORTB Bit 0
FIRSTPORTB Bit 1
FIRSTPORTB Bit 2FIRSTPORTB Bit 3
FIRSTPORTB Bit 4
FIRSTPORTB Bit 5
FIRSTPORTB Bit 6
FIRSTPORTB Bit 7
FIRSTPORTC Bit 0
FIRSTPORTC Bit 1
FIRSTPORTC Bit 2
FIRSTPORTC Bit 3
FIRSTPORTC Bit 4
FIRSTPORTC Bit 5
FIRSTPORTC Bit 6
FIRSTPORTC Bit 7
N/C
N/C
N/C
N/C
N/C
CTR6 CLKCTR6 GATECTR6 OUT
N/C
N/C
CTR5 CLK
CTR5 GATE
CTR5 OUT
N/C
GND
+12V
GND
-12V
N/C
N/C
A/D INTERNAL PACER OUTPUT
N/C
N/C
N/C
N/C
GND

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Norton, Massachusetts 02766(508) 946-5100
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PCI-DAS1002-spec.doc