GR740
Next Generation
Microprocessor
Flight Models
TEC-ED & TEC-SW Final Presentation Day
June 2021

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Abstract• The GR740 microprocessor has been developed within ESA's NGMP
(Next Generation MicroProcessor) initiative in TRP, GSTP and EOP
programmes, accompanied also by several activities to consolidate
the SW ecosystem.
• The Phase 3 contract dedicated to the production of GR740 Flight
Models has now been completed. Screening / qualification tests per
MIL-PRF-38535L / MIL-STD-883K and delta-evaluation per ESCC2269000 have been passed successfully.
• QML-V & QML-Q equivalent flight parts can now be ordered, and firstusers have already designed GR740 into their equipment.
• QML-V and QML-Q qualified parts will be offered once the certification
is granted by the DLA.

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Agenda• About Cobham Gaisler• Start at the finish line
• Where are we now?

• We have made it• GR740 qualification results• And now what?
• RoadMap• Back to the beginning• When, why, what, where?
• Hurdles along the way• Package development• Over Pad Metallisation• Wire bonding• Selection of columns• Design changes

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A world leader in embedded computer
systems for harsh environments

Experts in fault-tolerant computing

We provide a full ecosystem to support
hardware and software design for:• Standard components• Semi-custom FPGA
• Full custom ASIC

Based on SPARC and RISC-V architectures

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4

Established 2001,
20-year anniversary!
•

Acquired by Aeroflex in 2008•

Acquired by Cobham in 2014•

Acquired by Advent in 2020

Main office located in Gothenburg,
Sweden48 staff + 10 consultants + 6 students

In-house facilities

PUBLIC•ASIC and FPGA design•

Software•

Component lab
5LEON Processors Populating
the Solar System
Components and IP cores in transit,
in orbit or on the surface

PUBLIC69 out of 10 instruments

in Solar Orbiter use
the LEON3FT
Launched February 2020

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7

Components
High-reliability• Radiation hardened • Space qualified • Fault-tolerant
NOEL Processor Family•

GR7xv, NOEL-V, 16-Core, in development

Interconnect•

GR718B, Vendor class S

LEON Processor Family

PUBLIC•GR765, LEON5FT, in development•

GR740, LEON4FT, quad-core, 250 MHz, QML-V approval exp. Q2 2021•

GR740 PBGA, LEON4FT, quad-core, 250 MHz, prototypes Q2 2021•

GR716A, LEON3FT, single-core, 50 MHz, ESCC 9000 screening exp. Q2 2021•

GR716B, LEON3FT, single core 100 MHz, in development•

GR712RC, LEON3FT, dual-core, 100 MHz, Vendor class S•

UT700, LEON3FT, single-core, 166 MHz, QML-Q, QML-V•

UT699E, LEON3FT, single-core, 100 MHz, QML-Q, QML-V•

UT699, LEON3FT, single-core, 66 MHz, QML-Q, QML-V

8

Start at the finish line
TEC-ED & TEC-SW Final
Presentation Day
Why start at the finish line?
Because the finish line for this project is today
So let us talk about:

PUBLIC•

20 years of LEON processors•

Where we are now with the GR740•

How we got here

9The finish line, is it?
LEON Technology – over 20 years of space success•••Five generation LEON SPARC V8 processors
Space proven technology
Industry Standard Tools & Eco-System
2000

2005

2010

LEON3 IP core
7-stage pipeline
AMBA 2.0 bus
LEON2 IP core
5-stage pipeline
AMBA bus
LEON1 IP core
SPARC V8 32-bit
5-stage pipeline

PUBLIC2015

2020

GR740 partQuad-core LEON4FTGR712RC partDual-core LEON3FTGR716A partSingle-core LEON3FT
microcontroller

LEON4 IP core
Wider data pathL2 cache
UT699 partSingle-core LEON3FTUT700/UT699E partSingle-core LEON3FTLEON5 IP core
Superscalar 8-stage
pipeline

10Where are we now

Part no.

Processor
core

GR740
SMD:
596221204

QuadCore
LEON4FT

GR740
SMD:
596221204

QuadCore
LEON4FT

GR740P
BGA

QuadCore
LEON4FT

Clock
freq.
(MHz)
250

250

250

Perf.
(DMIPS)>1700 *

>1700 *

>1700 *

TID
krad
(Si)

SEL LET(MeVcm^2/mg)

300

Package

Temp.
range

< 2W at
40 C*

625-Pin
Ceramic Land
Grid Array> 125< 2W at
40 C*> 125< 2W at
40 C*

> 125

300

300

Power
cons.

Qualification status

Availability-40C /
+125C(junction)• QML-Q/V qualification tests
completed in 2020
• QML-Q/V approval expectedin Q2 2021

• Components
available

625-Pin
Ceramic
Column Grid
Array

-40C /
+125C(junction)• QML-Q/V qualification tests
completed in 2020
• QML-Q/V approval expectedin Q2 2021

• Components
available

625, PBGA-40C /
+105C(case)

ESCC-Q-60-13C class 2
evaluation ongoing• Prototypes in
Q2 2021• Flight Models in
Q4 2021Development
board

GR-CPCI-GR740
GR-VPX-GR740

Complete software toolchain and debuggers are available

QML-V equivalent and QML-Q equivalent parts
are currently available!
* For more information:
https://www.gaisler.com/doc/gr740/GR740-VALT-0010.pdf

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How did we get here
• Technical officer Roland Weigand• STMicroelectronics (France)• Rennes• Grenoble• Crolles• Micross Components, Crewe (UK)• Pender Electronic Design (Switzerland)

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Back to the beginning
NGMP proposal 2008

Final GR740 Product

PDR proposal 2010

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13

When
ESA’s next generation Microprocessor (NGMP) development time-line:

2009

2014

2016

2018

2020

Start of the

Implementation ofEngineering models of

Flight Silicon

All QML-V related

development under a

NGMP into a space chip

the GR740 were

manufactured andqualification tests

TRP contract with ESA

technology

evaluated.

validated (including

successfully completed.

(VHDL design and(C65SPACE).

verification bysimulation on FPGA).

radiation).

2021
2021-Q1 -> All complementary tests(Delta ESCC) successfully completed.

2021-Q1 -> QML-V / QML-Q
equivalent flight parts made available.

Expected 2021-Q2 -> Constructional
analysis on CLGA & CCGA package by
ESA.
Expected 2021-Q2 -> QML-V andQML-Q certification by the DLA.

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14

Why

•

To develop a microprocessor (NGMP) with higher
performance than earlier European space-microprocessors(i.e. to have a European option to the RAD750 and a
successor with higher performance than the AT697)•

Each generation of processors enable new spacecraft
capabilities (JPL RADECS 2018)

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Success
GR740 - the successor of UT700• GR740 can replace UT700 when more
powerful processing is demanded• GR740 can operate in single core mode,
almost doubling performance vs UT700• GR740 offers three additional cores formore processing, providing a 7x
performance increase over UT700• GR740 is software compatible with UT700• GR740 requires same real estate as UT700

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Success
Part Number

GR716A

GR716B*

UT699

UT699E

UT700

GR712RC

GR740

Processor

LEON3FT
Single Core
32-bit SPARC V8

LEON3FT
Single Core
32-bit SPARC V8

LEON3FT
Single Core
32-bit SPARC V8

LEON3FT
Single Core
32-bit SPARC V8

LEON3FT
Single Core
32-bit SPARC V8

LEON3FT
Dual Core
32-bit SPARC V8

LEON4FT
Quad Core
32-bit SPARC V8

Foundry

UMC
(180)

UMC
(180)

TSMC
(250nm)

TSMC(130nm)

TSMC(130nm)TowerJazz(180nm)ST(65nm)

Operating Voltage(core/IO)

1.8V/3.3V

1.8V/3.3V

2.5V/3.3V

1.2V/3.3V

1.2V/3.3V

1.8V/3.3V

1.2V/2.5&3.3V

Clock Frequency

50 MHz

100 MHz

66 MHz

100 MHz

166 MHz

100 MHz250 MHzDMIPS/Core, total

98

196

92

140

230

140, 280

425, 1700

Cache L1 I/D (KiB)

192 KiB TCM

192 KiB TCM

8/8

16/16

16/16

16/16

16/16

Cache L2 / L3
(KiB)

No

No

No

No

No

No

2048KB

MMU

No

No

Yes

Yes

Yes

Yes

Yes

*Products under development, Values can be changed without notice

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Are we there yet?
The sky is the limit!

Next Generation Processing for space applications (JPL RADECS 2018)
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What?
Value proposition

•
•
•
•

High performance, wide range of interfaces
SPARC V8 compliant, Radiation-hard and Fault Tolerant
LEON Technology – re-use of Development and Software ecosystem
Excellent performance/watt ratio••

Very low power, < 3 W (core typical)
Performance 1700 DMIPS

Applications•••

High-performance general-purpose processing
Symmetric and asymmetric multiprocessing

Shared resources can be monitored to support mixedcriticality applications

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What?
’

65nm CMOS Technology
ST C65SPACE Library
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PLLs

Quad Core

Memory20

What?
Features•

Fault-Tolerant Quadprocessor SPARC V8 integer
unit with 7-stage pipeline,
8 register windows,
4x4 KiB instruction and 4x4
KiB data caches.

•

Double-precision IEEE-754
FPU (1 FPU/Core)•

2 MiB Level-2 cache•64-bit PC100 SDRAM
memory interface with
Reed-Solomon EDAC•

8/16-bit PROM/IO interface
with EDAC•

CPU and I/O memory
management units•

Multi-processor interrupt
controller with support forasymmetric and symmetricmultiprocessing•

PUBLICSpaceWire TDP controller
and support for timesynchronisation
21

Interfaces• SpaceWire router with 8 SpaceWire links (200 MHz)• 2x 10/100/1000 Mbit Ethernet interfaces• 2x UART, SPI, Timers and watchdog,
16+22 pin GPIO

• 2x MIL-STD-1553B interface• PCI Initiator/Target interface• 2x CAN 2.0 controller interface• JTAG
21

GR740 Software Ecosystem
Operating Systems
OS

Real Time

SMP

AMP

MMU

Toolchain

LicenseBCC bare-metal

Y

N

*

N

GCC/LLVM

BSD

RTEMS-5 **

Y

Y

Y

N

GCC/LLVM

BSD/GPL

Linux 4.9

N

Y

*

Y

GCC

GPL

VxWorks 7

Y

Y

Y

Y&N

GCC/LLVM

COM*) single-core and/SMP support, no dedicated AMP mode

Zephyr RTOS 2.5

Y

N

*

N

GCC

APACHE**) ESA RTEMS SMP qualification package released 2021/2022

Hypervisor and memory protection support via Partners•

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Para-virtualization or processes interface for mixed criticality,
protection using MMU•

WindRiver VxWorks 7 Real-Time Processes (RTP) w/wo Time
Partition Scheduler•

FENTISS Xtratum Next Generation (XNG)•

SysGo PikeOS

Software ecosystem support from Cobham Gaisler•

Software Life-cycle webpage•

Software Overview webpage•

Updated continuously as part of LEON device support and LEON5

Upcoming releases Q2 and Q3: Linux 5.10 LTS and Zephyr 2.6 LTS

22

GR740 Software Ecosystem
Toolchain support•••

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GCC-7 and GCC-10 (GPL)LLVM Clang-8 (MIT)C/C++11 or later depending
on environment

Boot loaders••

MKPROM2 (GPL)GRBOOT (COM)GRMON-3 hardware debugger••

Assembly and C/C++ via GDBJTAG and Ethernet debug-link•

ECSS quality development flow,
Criticallity B•

GR740/LEON4 drivers, AMP and
SMP system support•

Flight Computer Initialisation
Sequence (SAVOIR-GS-002)•

Instruction trace, AHB bus traces,
I/O register inspection, etc.

•

Unit/validation test-suite•

Optional STANDBY SpW/PUS
remote terminal

Simulator(GR740 specific support)•

TSIM3 multi-core simulator•

Wind River Simics simulator(partner)

23

Application example:
GR740 - IPAC Computer for the Platino mission

IPAC is an innovative avionic based on an integrated
and modular approach, which essentially consolidates
all the DHS units typically present in EO missions(e.g. OBC, PDH, GNSS, RTs) in a unique box.
One example of this approach is related to On Board
Processors: in fact in previous platform architectures(e.g. Sentinel-1C/D) there were on-board as many as 8 CPUs
(2 x SMU, 2 x GNSS, 2 x Star Trackers, 2 x DSHA), whereas
in IPAC all the processing for these functions is consolidated
on the two LEON4 GR740 quadcore processors, with thepossibility to host also payload processing if required.

PUBLIC

Source: Presented by Alessandro Marini at ADCSS 2018,Noordwijk, The Netherlands
24Application example:
GR740 – Roman Space Telescope (WFIRST) Processor Board

Quad-Core LEON4 GR740 (MUSTANG + size

WFIRST Processor Board features:

module form factor) - board size 6U-220• GR740 Quad-Core LEON4 SPARC V8, 250MHz• FPGA

RTG4• SUROM

64KB

1x delivered to the JPL Coronagraph Team tobe used in the instrument for a tech demo on
WFIRST Observatory• SDRAM

256MB(+128MB FEC)

• DDR2

4GB(+2GB FEC)

2x more deliveries planned for JPL• MRAM

2X16MB

3x Engineering Board assembled tested••• Oscillator QT194(50MHz)+QT2020
MUSTANG Team is planning on lifting the• Peripherals:

Quad–Core LEON4 design/layout and• SpaceWire: 20 (8 GR740, 12 RTG4)

create an upgraded version of MUSTANG• 1553B: 1 (1 GR740)

Processor Card

• RS422: 16 TX and 16RX
• UART: 3 (2 GR740, 1 RTG4)• Debug-ports: GR740 SPW debug-port and RTG4 JTAG

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Source: Presented by Art Azarbarzin at the IEEE Space Computing Conference, Pasadena, CA, July 30 to August 1, 201925

Application example: GR740 – CORA-RDHC activity
Compact Reconfigurable Avionics– Reconfigurable Data Handling Core Module
ESA•

Technical Officer: Jørgen Ilstad, TEC-EDD –> EOP-PPE

Cobham Gaisler AB, Sweden (prime)•

Responsible for the development of hardware, VHDL
design, boot software and drivers

Thales Alenia Space France•

Responsible for middleware software design

Thales Alenia Space España S.A., Spain•

Responsible for FPGA reconfiguration code

Airbus Defence & Space, France•

Contribution to the systems analysis and trade-off,requirements and system architecture

Development of an Elegant Bread Board• A compact reconfigurable data-handling coremodule• High performance microprocessor and highcapacity reconfigurable FPGAs• Clear path to space qualification• Accompanied by I/O interface modules
Development of board support package• FPGA communication and reconfiguration• Communication interfaces towards externalsensors and actuators
Development of SW platform and Boot SW
Installation of hardware at ESTEC’s avioniclaboratory
GR740 Quad-Core LEON4 SPARC V8
Processor• Controller and high-performance processing

External service providers•

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Responsible for breadboard development

26

Application example: GR740 – GOMX-5 cubesat

APPs Team• Cobham Gaisler AB, Göteborg, Sweden•

ńKzAkademii Nauk, Warsaw, Polandj• GMV Innovating Solutions Sp, Warsaw,
Poland• Space Technology Research Laboratory,
UFSC, Florianópolis, Brazil
ESA

APPs team
GMV

Applications• APPs management• Communications routing (S/C CAN to/from
local APPs SpW)
• Board and application control (GPIO I/F to
APPs boards)• Memory error detection and correction

GomSpace

Cobham Gaisler(project coordinator)

Objective• Demonstrate multiple processing
technologies developed within
ESA activities and acquire flight
heritage from related components

CBK

UFSC

• Processing and memory resource for off-board
experiments via SpW• Mono-frequency receiver for GNSS SDR
experiments (with GMV)
• BRAVE board reconfiguration (with UFSC)• Power distribution from S/C to APPs boards (passive)

System

GR740

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GR716

GNSS

BRAVE

Source: Presented by27

Application example: GR740 – Single Board Computer
The SBC provides an extensive set of memories and redundant interfaces to support
the needs of current and future OBC and Data Handling platforms.
Features•Interfaces•

Redundant MIL-STD-1553B•

2 x SpaceWire•

HSSL (SpFi)•

2 x UART•

Gigabit Ethernet

•

•

x

’

•

PPS (Pulse Per Second) input for synchronization•

JTAG debug interface•

Dual star, eight SpaceWire interfaces from the GR740 SpaceWire router•

Multi drop bus, redundant CAN from GR740•

Full mesh, 3.125 Gbit/s HSSL (SpFI) from RTG4 **•Multi drop bus, I2C from RTG4•

Alarms and other utility signals

Form factor•

6U (233.5 mm x 160 mm), 5 HP, Mass 1.2 kg (estimate)*Product under development,
options can be changed without notice

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Hurdles along the way

No development is free of technical challenges:

PUBLIC•Technology platform was not available•

Package development•

Over Pad metallization•

Wire bonding•

Selection of column type for CCGA package•

Design changes

29

Package development
625 pins Package:• CLGA• CCGA••

PUBLICImages courtesy of ST Microelectronics

Flip-Chip was not available
to projectThis led to development offunctional prototypes and, inthe end, additional design
improvements for the final
product30

Over Pad Metallisation (OPM)••

Al wedge bonding was not possible for the C65SPACE•

Wire bonding validation after die aging on corner caselibrary due to pad size compatibility and the complexity of(500h 150C / 500h 85C/85%RH) was performed with

the GR740. Au wire had to be used instead.

metallisation integrity check after aging

Because of the Al pad – Au wire metal interface, an OPM•

Constructional analysis

layer was implemented

Au

Silicon rev.0
Al
Images courtesy of ST Microelectronics

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Wire Bonding• C65SPACE library imposed the used of Au ball bonding

Before Test

• Device complexity imposed the use of thin bond wires,
20µm in diameter• 4 decks were necessary to accommodate all bond wires.
Package validation included:• Vibration, TM 2007 Condition A

After Test

• Mechanical Shocks, TM 2002 Condition B• Constant acceleration, TM 2001 Condition D• PIND test, TM 2020 Condition A.
• Electrical test & X-ray before and after each test.
X-ray based 3D reconstruction of the GR740 bonds.

Images courtesy of ST Microelectronics.

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Selection of column for the CCGA package••

The GR740 package is compatible with various columns types:•

Sn/Pb IBM type (Micross Crewe UK)•

Sn/Pb copper wrapped (e.g. Serma, SixSigma)

The QML qualification has been run with Micross IBM typecolumns•

Micross Crewe UK is currently QML-Q/V/Y certified by the DLA•

A board level reliability study of the IBM columns has been
completed by ST & Micross.
••

FIT FOR PURPOSE

A comparison study between Micross and Serma type columns
has been carried out by ESA/Thales I.

PUBLICImages courtesy of ST Microelectronics

33

Design Changes•

Corrections of issues with functional impact•••

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Level-2 cache fault-tolerance

Improvements of functional impact•

Extensions of logging•

Time synchronization

Die & Package revision 1
Description

Reference

Level

HBM

JS-001-2017

2000 V

CDM

JS-002-2014

500 V

Improvements without functional impact•

Correction of ring oscillator•

Removal of unused RAM bits•

Pipelining to reduce backend effort•

LVDS driver ESD sensitivity at low voltage (HBM)•

On-chip temperature sensor fixed

All GR740-CP/MP/MSxx components
have die revision 1

34

We have made it• Qualification testing has been successfully completed• Screening / qualification tests per MIL-PRF-38535L / MIL-STD-883K• Delta-evaluation per ESCC-2269000• The qualification data package to the DLA includes:• Draft SMD 5962-21204• Results of qualification tests• Reliability data
• Technology support data

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GR740 qualification results

GR740 qualification performed following QML-V flow
• QML-V Screening (MIL-PRF-38535)• Group A (Electrical tests)• Group B (Mechanical and Environmental tests)• Group C (Life test)• Group D (Package related tests)• CLGA• CCGA (IBM type columns)• Group E (Radiation tests)

PUBLICALL TESTS SUCCESSFULLY COMPLETED!

36

GR740 qualification results

Solder column pull test for
CCGA performed in Group D

Extensive Life test data has been collected by ST fortest vehicles manufactured with same library to
calculate the failure rate of the GR740 silicon.

Image of solderability test
courtesy of ST Microelectronics and Micross Crewe UK

PUBLICALL TESTS SUCCESSFULLY COMPLETED!

37

GR740 qualification results

Images of solder column pull test
courtesy of ST Microelectronics and Micross Crewe UK

Resistance to soldering heat (subgroup D9)
performed under both conditions I and J

PUBLICALL TESTS SUCCESSFULLY COMPLETED!

38

GR740 qualification results• TID tolerance of 300 krad(Si)• Overall SEE rate below 1x10-5 events/device/day (GEO)• SEL > 125 MeV.cm2/mg (T>85ºC & max supply)

PUBLICALL TESTS SUCCESSFULLY COMPLETED!

39

GR740 qualification results

From D3

ALL TESTS SUCCESSFULLY COMPLETED!

From D4

ALL TESTS SUCCESSFULLY COMPLETED!

Expected in Q2 2021

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Lessons Learnt•

In every development obtaining requirements and feedback fromusers is difficult but very valuable••

It is important to release prototypes early for:•

Functional validation•

Radiation characterisation•

Allow customers to test and design-in the device

Hardware/Software Co-engineering is critical to make sound design
decisions. The GR740 has benefited from backward compatibility withearlier generation LEONs and a large software ecosystem fordevelopment available at an early stage
Leaning tower of Pisa in 2013 (Wikipedia)
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What’s next

Next Generation
LEON processor

PUBLIC42

What’s next
Q1

2021
Q2
Q3

RISC-VNOEL

In production

Q4

Q1

2022
Q2
Q3

LEON

32-bit SPARC V8

GR712RC
LEON3FT, Dual Core
100 MHz
UT700
LEON3FT, Single Core
166 MHzUT699E
LEON3FT, Single Core
100 MHz
UT699
LEON3FT, Single Core
66 MHzRouterGR718B
18-port SpaceWire router

2023
Q2
Q3

Q4

GR7xV
NOEL-V, 16-Core 64-bit

Q1

2024
Q2
Q3

Q4

Q1

GR7xV
NOEL-V, 16-Core, 64-bit

2025
Q2
Q3

Q4

GR7xV
NOEL-V, 16-Core, 64-bit

GR765ES, Protoflight
LEON5FT, Multi-Core
On customer demand

GR765
LEON5FT, Octa-Core

SpW

Q1

GR7xV
SELENE and NOEL-V, 16-Core, 64-bit
De-RISC platform
NOEL-VGR765ESLEON5FT, Multi-Core

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Q4

GR765
LEON5FT, Octa-Core

GR765
LEON5FT, Octa-Core

GR740
LEON4FT, QuadCore, 250 MHz
GR740 PBGALEON4FT, QuadCore, 250 MHz

GR716A
LEON3FT, Single-Core,
50 MHzGR716B
LEON3FT, Single-Core, 100 MHz

GR716B
LEON3FT, Single-Core, 100 MHz

Project phases

Product availability
FPGA Prototype

Dates are subject to change without notice.
Roadmap updated quarterly.

Prototype

Flight model

Lot Val

QML

Concept

Definition

Prototype

FlightQualification
Lot Validation

43

What’s next
GR765•

The GR765 development builds on the successful GR740 quad-core LEON4FT
component and maintains backward compatibility with it.

•

The GR765 includes a octa-core LEON5FT, support for DDR3 SDRAM, high-speed
serial link controllers and several other extensions.
x•

GR765ES is planned to be available on development boards mid-2022•

The GR765 SoC implementation starts in parallel with the manufacturing of
GR765ES, GR765-XX (prototype) components are planned to be available Q2 2023.

•

x

x

GR765ESThe GR765 development puts emphasis on computational performance, power
efficiency, and support for mixed criticality application.

•

The GR765 is being defined and implemented with focus on the space industry.
Feedback can still be addressed, and your input is most welcome.

•

7

x

’

www.Gaisler.com/GR765
PUBLICxx

44

PUBLIC

45