ClockMatrix Time-to-Digital
Converter (TDC)

AN-1010
Application Note

Contents
Introduction ............................................................................................................................................................................................................2
Time-to-Digital Converter (TDC) ............................................................................................................................................................................3
Input TDC ..............................................................................................................................................................................................................3
Measuring Asynchronous Clocks .................................................................................................................................................................7
Finer Measurement Resolution ....................................................................................................................................................................7
Fine Measurement Example................................................................................................................................................................8
Accuracy vs Precision ................................................................................................................................................................................11
Settling Time...............................................................................................................................................................................................11
Output TDC .........................................................................................................................................................................................................11
Average Phase Measurement ....................................................................................................................................................................15
Continuous Phase Measurement ...............................................................................................................................................................15
Automatic Output Alignment .......................................................................................................................................................................16
Revision History...................................................................................................................................................................................................17

List of Figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.

Input TDC Conceptual Diagram ..........................................................................................................................................................3
Input TDC Input Selection using Timing Commander .........................................................................................................................5
Input TDC Reference Selection ...........................................................................................................................................................5
Input TDC Sampling ............................................................................................................................................................................6
Enabling High Precision Mode ............................................................................................................................................................7
Output TDC Conceptual Diagram (Single Instance; Up to Four Supported) .....................................................................................11
Output TDC using Timing Commander .............................................................................................................................................12
Output TDC Alignment Mask .............................................................................................................................................................17© 2021 Renesas Electronics Corporation

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List of Tables
Table 1. Clock Input Selection for Input TDCs Register ....................................................................................................................................4
Table 2. Sample Clock Selection for Input TDCs Register ................................................................................................................................5
Table 3. Phase Offset between Two Clocks Register .......................................................................................................................................6
Table 4. PLL Mode Selection Register ..............................................................................................................................................................6
Table 5. DPLL Loop Filter Status Register ........................................................................................................................................................8
Table 6. Accuracy Difference between XTAL and XO_DPLL for Various Phase Offsets ................................................................................11
Table 7. Output TDC Source and Target Registers.........................................................................................................................................12
Table 8. Output TDC Phase Measurement Register .......................................................................................................................................13
Table 9. Output TDC Valid Register ................................................................................................................................................................13
Table 10. Sample Clock Selection for Output TDCs Register ...........................................................................................................................13
Table 11. Output TDC Enable Bit Register ........................................................................................................................................................13
Table 12. Output TDC State Register................................................................................................................................................................14
Table 13. Output TDC Trigger Register .............................................................................................................................................................14
Table 14. Output TDC Status Register ..............................................................................................................................................................14
Table 15. Output TDC Samples Register ..........................................................................................................................................................15
Table 16. Output TDC Type Selection Register ................................................................................................................................................15
Table 17. Output TDC Mode Register ...............................................................................................................................................................16
Table 18. Output TDC Target Offset Register ...................................................................................................................................................16
Table 19. Output TDC Alignment Mask Register ..............................................................................................................................................16

Introduction
ClockMatrix provides many tools to manage timing references. It has several different modes to align the output clocks, to control the skew, tomeasure clocks, select clock sources, and have independent timing paths for IEEE 1588 / Precision Time Protocol (PTP) and Synchronous
Ethernet (SyncE) based clocks.
A typical large telecom system consists of Line Cards (LCs), Routing/Switching Processors (RSPs), Timing Cards (TC), Fan Trays, back/midplanes, and/or switching matrixes. Some of these functions can be combined in the same cards (e.g., RSP can have TC functionality as well).
If such a system needs to participate in network timing distribution then it is expected that they support SyncE and IEEE1588 standards. It isalso expected that these systems contribute very little constant Time Error (cTE) noise to the network clock.
This document addresses the usage of ClockMatrix’s Time-to-Digital Converters (TDCs) for precise clock phase measurement using
ClockMatrix. It shows the necessary registers to access the TDCs and also the equivalent GUI windows to access using Timing Commander.

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Time-to-Digital Converter (TDC)
A TDC circuit is used to recognize events and provide a digital representation of the time they occurred. TDCs are used in applications where
measurement events happen either infrequently (e.g., the time of arrival for each incoming pulse) or where measurement events happen in
relationship to another event (e.g., the relative offset between an input clock and feedback clock in a DPLL).
ClockMatrix provides access to its DPLL’s Phase-Frequency Detector (PFD), or input TDC, for continuous phase measurements between two
reference clocks (CLKn). It also provides a dedicated TDC measurement unit, or output TDC, for either single or continuous phasemeasurements.

Input TDC
Any of the DPLL channels’ PFD can be used to measure the phase offset between two input clocks of the same frequency. The PFD has adefault resolution of 50ps and a range of ±0.86s. Any frequency from 0.5Hz to 200MHz is supported.
Figure 1.

Input TDC Conceptual Diagram..

CLK0..CLK15fb..

fb_clk_select
ref_clk_selectrefint_fb_clk

PFD

36

Decimator

43

Loop filter[42:7]

tdc_clk

36

48

Phase status

Filter status

ext_fb_en
Figure 1 shows the concept of the setup. The reference and feedback clock are selected from inputs CLK0 to CLK15 by programming the
DPLL_PHASE_MEASUREMENT_CFG register (for information about which CLKn inputs are available, see the respective datasheet). The
registers are shown in Table 1, while the equivalent GUI windows are displayed in Figure 2.

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Table 1.

Clock Input Selection for Input TDCs Register© 2021 Renesas Electronics Corporation

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ClockMatrix Time-to-Digital Converter (TDC)
Figure 2.

Input TDC Input Selection using Timing Commander

The PFD measures the phase offset between the two clocks for every clock cycle, with a nominal resolution of 50ps (determined from tdc_clk).
The phase resolution is 1/32 of the period of the tdc_clk.
By default, the tdc_clk is 625MHz and therefore the phase resolution is 1.6ns/32 = 50ps. The accuracy of the measurement is determined by
the selected source. The tdc_clk source can come from the XTAL I/O (default) or XO_DPLL as shown in Table 2. It can be accessed by the
GUI as shown in Figure 3.
Table 2.

Sample Clock Selection for Input TDCs Register

Figure 3.

Input TDC Reference Selection

Using an nCXO (i.e., via XO_DPLL or overdriving OSCI) will provide for more accuracy in the measurement compared to an uncompensated
XO or XTAL. A compensated nCXO assisted to be nominal 0PPM will be even more accurate.
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The signed 36-bit phase output (see Table 3) from the phase detector can then be (optionally) low-pass filtered by a decimator, which will also
add 7 bits of additional granularity (for more information, see “Finer Measurement Resolution”). As displayed in Figure 1, the signed 36-bit
phase values from the phase detector/decimator can be read through the phase_status register, which refreshes every 100 microseconds.
When used for phase measurement mode, the range is from (-2^34) to (2^34 -1) ITDC_UI. If PHASE_STATUS is saturated, it is recommended
to swap the two clocks being measured.
Note: For input clocks < 10kHz, the phase values will update on every input clock cycle (+0~100 microseconds). In the GUI, the phase status
can be read from Step 3 in Figure 2.
Table 3.

Phase Offset between Two Clocks Register

The phase offset value is a signed value. A +’ve sign means that the feedback clock leads the reference clock; a –‘ve sign means that the
feedback clock lags the reference clock.
Figure 4.

Input TDC Sampling

TDC phase offset value n[resolution is +/-50ps ((1/625MHz)/32)]

TDC phase offset
value mInput A
Input B

Measurementn

n+1 n+2 n+3m

m+1 m+2 m+3

As shown in Figure 4, the phase offset of “every” input clock cycle is measured, regardless of its frequency. However, the phase offset registercontaining this measurement is only refreshed every 100 microseconds. If faster phase offset measurement readings are required, this is
supported via direct hardware Control/Status Register access. For more information, contact Renesas technical support.
You must select phase measurement mode as the DPLL’s mode of operation (see Table 4). When using the DPLL channel’s PFD formeasurement, the channel becomes unavailable for normal PLL operation but it can be used as a synthesizer. Using the GUI, the PLL mode
selection is shown in Step 2 of Figure 2. Also shown in Figure 2, the Channel can also be used in Write Frequency Mode (FCW) when in Phase
Measurement Mode. However, FCW can only be used in low precision mode (Phase Status), and not high precision mode (Phase Status andFilter Status). In high precision mode, the channel can only be used as a synthesizer. High precision mode is explained in Finer Measurement
Resolution.
Table 4.

PLL Mode Selection Register© 2021 Renesas Electronics Corporation

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Measuring Asynchronous Clocks
The PFD can measure the phase offset of two asynchronous clocks of the same frequency. However, because the two clocks will drift awayfrom each other over time, the PFD will eventually saturate at ±0.86s of phase offset. For example, if there is 1PPM of frequency offset between
the two measurement clocks (the frequency of the clocks is not important), the clock edges between the two clocks will drift away at
approximately 1 microsec/sec. Thus, assuming the two edges were exactly aligned at the start of the measurement and the frequency offset isstatic (i.e., remains at 1PPM), this means after (1,000,000 * 0.86s) = 860,000s (~10 days), the PFD will saturate.
To avoid this, the offset value can be reset by toggling the PLL_MODE. However, this means that the input TDC will also restart its phasemeasurement from the following edge after returning to phase measurement mode.

Finer Measurement Resolution
The decimator can be used to average the phase detector values and thereby get a better resolution than 50ps. As shown in Figure 1, thedecimator provides a 43-bit phase output to the DPLL loop filter but only the upper 36 bits are visible through the phase_status registers. Thus,
the filter_status (see Table 5) has 7 bits more lsb resolution than the phase_status, or a resolution of 0.39ps. The filtered/averaged phase value
can be read through the filter_status registers, which again refreshes every 100 microseconds. The filter_status can be enabled using the High
Precision Mode (0xCD24 bit 7) in the GUI as shown in Figure 5. Once filter_status is enabled, the Channel can no longer be used in Write
Frequency Mode while in Phase Measurement Mode. At this point, only Synthesizer Mode can be used with Phase Measurement Mode. Also
notice from Figure 5 that the TDC Frequency (tdc_clk) and the TDC Multiplier are changed when High Precision Mode is enabled. This is criticalin getting an improved resolution from filter_status. When only phase_status is used, the TDC Frequency is 625MHz. When filter_status is used,
the TDC Frequency must not be an integer multiple of the input clock frequencies being measured.
Figure 5.

Enabling High Precision Mode

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Table 5.

DPLL Loop Filter Status Register

In order to get a more precise decimated phase value from the filter_status, the loop filter must be set up such that it is transparent from thedecimated phase input to the filter status output. In addition, the decimator needs to be set up as a low pass filter to average the toggling lsb of
the phase word from the phase detector. For ClockMatrix, the bandwidth multiplier of the decimator and the bandwidth of the loop filter are preset when in phase measurement mode, such that the loop filter is transparent from the decimated phase input.
For the averaging of the phase values from the phase detector (i.e., to get better than 50ps resolution), it is also critical that the TDC Frequency(tdc_clk) is not synchronous (common multiple) to the input clocks. This setup is shown in the Fine Measurement Example. The TDC Frequency
can be modified by using the following equation.
𝑛𝑛𝑡𝑡𝑡𝑡𝑡𝑡_𝑐𝑐𝑐𝑐𝑐𝑐 = 𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓 �𝑤𝑤 + �
𝑑𝑑fref = The reference frequency (XTAL or TCXO/OCXO)
w = Integer portion of the divider (0xCD24 bits 6:0)
n = Numerator fractional portion of the divider (0xCD20:0xCD21)
d = Denominator fractional portion of the divider (0xCD22:0xCD23)
Fine Measurement Example
For measuring the phase between two 8kHz signals, the tdc_clk must be changed to a different frequency from 625MHz that is not an integer
multiple of 8kHz. When the tdc_clk frequency is divided by an integer number to get the closest to 8kHz, there must be a frequency difference
that is large enough to make the averaging work. The frequency offset by itself should not be an integer division of the 8kHz input frequency.
Example 1:
 Xtal frequency = 50MHz
 Input clock frequency of two inputs = 8kHz
 Tdc_clk nominal divide to 8kHz = 625MHz / 8kHz = 78125
 Desired sample frequency offset = 123Hz
 New Tdc_clk frequency = 78125 * (8000 – 123) = 615.390625MHz

Phase_status resolution = 1/32 * 1/615390625 = 50.781ps• Filter_status resolution = 50.781ps/128 = 0.39672464ps
Tdc_clk : xtal ratio = 615.390625MHz / 50MHz = 12 + 20094/65280
0xCD24 = 0x8C
0xCD20 = 0x7E
0xCD21 = 0x4E
0xCD22 = 0x00
0xCD23 = 0xFF
•

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


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Example 2:
 OCXO frequency = 10MHz
 Input clock frequency of two inputs = 8kHz
 Tdc_clk nominal divide to 8kHz = 625MHz / 8kHz = 78125
 Desired sample frequency offset = 123Hz
 New Tdc_clk frequency = 78125 * (8000 – 123) = 615.390625MHz

Phase_status resolution = 1/32 * 1/615390625 = 50.781ps
Filter_status resolution = 50.781ps/128 = 0.39672464ps
Tdc_clk : xtal ratio = 615.390625MHz / 10MHz = 61 + 35259/65408
0xCD24 = 0xBD
0xCD20 = 0xBB
0xCD21 = 0x89
0xCD22 = 0x80
0xCD23 = 0xFF
•
•

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





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Example 3:
 XTAL frequency = 49.152MHz
 Input clock frequency of two inputs = 25MHz
 Tdc_clk nominal divide to 25MHz = 625MHz / 25MHz = 25
 Desired sample frequency offset = 31776.16148Hz
 New Tdc_clk frequency = 25 * (25000000 – 31776.16148) = 624.205595963MHz

Phase_status resolution = 1/32 * 1/624205595.963 = 50.063633ps• Filter_status resolution = 50.063633ps /128 = 0.39112213ps
Tdc_clk : xtal ratio = 624.205595963MHz / 49.152MHz = 12 + 4297/6143
0xCD24 = 0x8C
0xCD20 = 0xC9
0xCD21 = 0x10
0xCD22 = 0xFF
0xCD23 = 0x17
•

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



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Accuracy vs Precision
The Input TDC Reference Selection (XTAL or XO_DPLL) affects the accuracy, whereas the TDC Multiplier affects the precision.
For small phase offsets using phase measurement such as 1ns or 1ps, XTAL or XO_DPLL do not make a difference in accuracy. For large
phase offsets such as 1µs or 1ms, XTAL or XO_DPLL makes a difference in accuracy (see Table 6).
Table 6.

Accuracy Difference between XTAL and XO_DPLL for Various Phase Offsets

The Input TDC “Enable high precision mode” affects the precision, not accuracy. Our TDC has a precision of 50ps, however, since we aredecimating/averaging/filtering, we can get much better precision down to 1ps and generally improved quantization error. By ensuring thetdc_clk is not an integer multiple of the input reference clocks, then averaging will improve the quantization error. In general, we want the
precision to be much better than the accuracy so we are not dominated by quantization error.

Settling Time
The decimator value of the Input TDC is calculated dynamically by the firmware. It will differ depending on the input frequency and the phaseoffset between the two inputs. For the initial measurement, it could take up to 15 seconds before the phase measurement has settled.
Subsequent measurements should converge much quicker (few seconds). However, the accuracy of the measurement itself could be affectedby noise such as the stability of the inputs (cycle to cycle jitter and wander), XO (frequency drift), or even the TDC itself. The noise from the
TDC itself is a maximum of 90ps.

Output TDC
An output TDC can perform a single measurement of the phase offset between two output channels or between an output channel and a GPIO
input. It can also be used to automatically align the outputs of two channels (see Automatic Output Alignment). The PFD has a default resolutionof 50ps. Up to four independent, parallel measurements are supported using the output TDC.
Figure 6.

Output TDC Conceptual Diagram (Single Instance; Up to Four Supported)..

DPLL0..7,
GPIO1,2,6,7

src0

..

TDC
unit0

dest_idx_selectsrc_idx_select[47:0]

48

Phase0

dest0

tdc_clk

Figure 6 shows the concept of the setup. The reference clocks to the output TDC are selected from channels DPLL0 to DPLL7. In addition,
GPIO1, GPIO2, GPIO6, or GPIO7 can be selected as one of the input reference clocks (for more information, see the relevant datasheet on
which DPLLn outputs and GPIOn inputs are available). The source and target references can be selected based on Table 7, and is also shownin Step 4 of Figure 7.

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ClockMatrix Time-to-Digital Converter (TDC)
Table 7.

Output TDC Source and Target Registers

Figure 7.

Output TDC using Timing Commander© 2021 Renesas Electronics Corporation

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ClockMatrix Time-to-Digital Converter (TDC)
The output TDC measures the phase offset between the two clocks with a nominal resolution of 50ps (determined from tdc_clk). The phasevalues from each of the four TDC measurement units can be read through four different phase measurement registers (see Table 8 and Step 11of Figure 7).
Table 8.

Output TDC Phase Measurement Register

To determine if the value in the PHASE[47:0] register is valid (i.e., after a measurement has completed), a VALID bit should be checked before
reading.
Table 9.

Output TDC Valid Register

The output TDC uses tdc_clk to sample the input clocks. This clock can come from the XTAL I/O or XO_DPLL (see Table 10 and Step 3 ofFigure 7).
Table 10.

Sample Clock Selection for Output TDCs Register

Similar to the input TDC, the phase resolution is 1/32 of the period of the tdc_clk. By default, the tdc_clk is 625MHz and therefore the phaseresolution is 1.6ns/32 = 50ps (note: the input TDCs and output TDC have their own tdc_clk). The accuracy of the measurement is determinedby the selected source (XTAL or XO). Using an nCXO (i.e., via XO_DPLL or overdriving OSCI) will provide for more accuracy in themeasurement compared to an uncompensated XO or XTAL.
The output TDC is disabled by default to save power when not in use (see Table 11 and Step 2 of Figure 7).
Table 11.

Output TDC Enable Bit Register

Once enabled, the state of the output TDC will reflect when it is ready for measurement.

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Table 12.

Output TDC State Register

Once the output TDC instance’s configuration is set, it must be manually triggered (“Go”) to start (see Table 13 and Step 10 of Figure 7). There
must be a minimum 1 second delay between the configuration being set and the trigger. The trigger must be the last register written for aparticular TDC.
Table 13.

Output TDC Trigger Register

The status of the TDC measurement can be monitored to see if the current measurement is valid (i.e., complete).
Table 14.

Output TDC Status Register© 2021 Renesas Electronics Corporation

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Average Phase Measurement
As previously mentioned, the output TDC was designed for a single measurement. To improve the precision of the measurement result, a
number of samples can be taken (i.e., averaged) instead of relying on a single measurement. By default, 4096 samples are taken and averaged.
To take a single measurement, set SAMPLES[15:0] = 1 (see Table 15 and Step 8 of Figure 7).
Table 15.

Output TDC Samples Register

Each sample is taken every 100 microseconds, with the final averaged result being placed in the PHASE[47:0] register (i.e., after(SAMPLES[15:0] * 100 microseconds)). To determine if the measurement sample has completed, the VALID bit should be checked.

Continuous Phase Measurement
The TDC can be configured to continuously take phase measurements, which will just repeat the single phase measurement settings (seeTable 16 and Step 6 of Figure 7).
Table 16.

Output TDC Type Selection RegisterIn the case of continuous measurement when doing average phase measurements, averaging will still be performed only on the measurement
values taken within the programmed sample window. Thus, the phase measurement register will reflect the [averaged] value of the previous
sample window when the VALID bit is set.

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Automatic Output Alignment
In addition to phase measurements, the output TDC provides a means to auto-align the outputs of two or more DPLL channels. This is forchannels that are frequency synchronized or syntonized to the source DPLL channel, either by locking to the internal feedback clock orsyntonized via the Combo Bus (see Table 17 and Step 5 of Figure 7). When alignment mode is selected, the target reference in Step 4 becomes
unused.
Table 17.

Output TDC Mode Register

The target phase offset for alignment is set via a configuration register, supporting a range of ±1.28ns in 10ps granularity. The resolution of thealignment will be determined by the configuration of the TDC measurement unit, but will be ≤ ±50ps (see Table 18 and Step 9 of Figure 7).
Table 18.

Output TDC Target Offset Register

More than one DPLL channel can be aligned to the source DPLL. This is set via a destination DPLL configuration register (see Table 19 and
Figure 8).
Table 19.

Output TDC Alignment Mask Register© 2021 Renesas Electronics Corporation

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Figure 8.

Output TDC Alignment Mask

For questions related to device configurations, please contact Renesas technical support.

Revision History
Revision Date
November 9, 2021
July 13, 2021
September 2, 2020

Description of Change Updated the second paragraph after Figure 3
 Completed other minor changes
 Added a new section, Settling Time
 Updated Time-to-Digital Converter (TDC), Finer Measurement Resolution, and Fine Measurement
Example Added a new section, Accuracy vs Precision

August 28, 2018

Initial release.

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