REVISIONSLTR

DESCRIPTIONDATE (YR-MO-DA)APPROVED

15-01-26

Thomas M. HessA

Correct IAM,100% and IAM,RAM values in Table I. - PHN

BCorrect Vendor part number in section 6.3. phn

15-08-25

Thomas M. Hess

Update boilerplate paragraphs to current VID description requirements.
- PHN

22-03-28

Muhammad A. Akbar

C

CURRENT DESIGN ACTIVITY CAGE CODE 16236
HAS CHANGED NAMES TO:
DLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
Prepared in accordance with ASME Y14.24

Vendor Item Drawing

Revision Status of Sheets
REV

C

C

C

C

C

C

C

C

SHEET

23

24

25

26

27

28

29

30

REV

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

SHEET

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20 21

22

PMIC N/A
Original date of drawing
YY MM DD

DEFENSE SUPPLY CENTER, COLUMBUS

PREPARED BY
Phu H. Nguyen

TITLE

CHECKED BY
Phu H. Nguyen
APPROVED BY

14-12-22

COLUMBUS, OHIO 43218-3990
MICROCIRCUIT, DIGITAL, MIXED SIGNALMICROCONTROLLERS, MONOLITHIC SILICON

Thomas M. HessSIZE

CAGE CODEDWG NO.

C

PAGE

16236

A

REV

V62/14644

1 OF 30AMSC N/A
DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.

5962-V028-22

1. SCOPE
1.1 Scope. This drawing documents the general requirements of a high performance mixed signal microcontrollers microcircuit, with
an operating temperature range of -55ºC to +85ºC.
1.2 Vendor Item Drawing Administrative Control Number. The manufacturer’s PIN is the item of identification. The vendor item
drawing establishes an administrative control number for identifying the item on the engineering documentation:
V62/14644-

Drawing
number01

X

E

Device type(see 1.2.1)

Case outline(see 1.2.2)

Lead finish(see 1.2.3)

1.2.1 Device type(s).
Device type

Generic

Circuit function

01

MSP430FR5739-EP

Mixed signal microcontrollers

1.2.2 Case outline(s). The case outlines are as specified herein.
Outline letter

Number of pins

X

40

JEDEC PUB 95

Package style

JEDEC MO-220

Plastic quad Flatpack no-lead

1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer:
Finish designator

Material

A
B
C
D
E
F
Z

DLA LAND AND MARITIMECOLUMBUS, OHIO

Hot solder dip
Tin-lead plate
Gold plate
PalladiumGold flash palladium
Tin-lead alloy
Other

SIZE
A

CAGE CODE
16236
REV

C

DWG NO.
V62/14644
PAGE 2

1.3 Absolute maximum ratings.

1/

Voltage applied at VCC to VSS ................................................................................................ -0.3 V to 4.1 V
Voltage applied to any pin (excluding VCORE) .................................................................... -0.3 V to VCC + 0.3 V 2/
Maximum diode current at any device pin ............................................................................ ±2 mA
Maximum junction temperature, TJ ....................................................................................... 95°C
Storage temperature range, Tstg ........................................................................................... -55°C to 125°C
3/ 4/ 5/
1.4 Recommended operating conditions.

6/

Supply voltage during program execution and FRAM programming (AVCC = DVCC) ......... 2.0 V to 3.6 V
7/
Supply voltage (AVSS = DVSS), VSS ................................................................................... 0 V TYP
Operating free air temperature, TJ ........................................................................................ -55°C to 85°C
Typical required capacitor at VCORE, CVCORE ..................................................................... 470 nF
8/Minimum capacitor ratio of VCC to VCORE , CVCC/CVCORE .................................................. 10 pF
Processor frequency (maximum MCLK frequency), fSYSTEM 9/:
No FRAME wait states, 10/ 2V ≤ VCC ≤ 3.6 V .............................................................. 0 MHz to 8.0 MHz
With FRAME wait state, 10/:NACCESS = {2},NPERCHING = {1}, 2V ≤ VCC ≤ 3.6 V .................................................................... 0 MHz to 24.0 MHz
2. APPLICABLE DOCUMENTSJEDEC – SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC)JEP95
JESD J-STD020––

Registered and Standard Outlines for Semiconductor Devices.
Standard for moisture/reflow sensitivity classification for nonhermetric solid state surface mountdevices.

(Copies of these documents are available online at https://www.jedec.org ).

___________
1/

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stressratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended
operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device
reliability.
2/ All voltages referenced to VSS. VCORE is for internal device use only. No external DC loading or voltage should be applied.
3/ Data retention on FRAM memory cannot be ensured when exceeding the specified maximum storage temperature, Tstg.
4/ For soldering during board manufacturing, it is required to follow the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
5/ Programming of devices with user application code should only be performed after reflow or hand soldering. Factory programmed
information, such as calibration values, are designed to withstand the temperatures reached in the current JEDEC J-STD-020
specification.
6/ Typical values are specified at VCC = 3.3 V and TA = 25°C (unless otherwise noted).
7/ It is recommended to power AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC
can be tolerated during power up and operation.
8/ A capacitor tolerance of ±20% or better is required.
9/ Modules may have a different maximum input clock specification. See the specification of the respective module in the
manufacturer data sheet.
10/ When using manual wait state control, see the MSP430FR57xx Family User's Guide (SLAU272) from manufacturer data sheet forrecommended settings for common system frequencies.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
16236
REV

C

DWG NO.
V62/14644
PAGE 3

3. REQUIREMENTS
3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as
follows:
A.
B.
C.

Manufacturer’s name, CAGE code, or logo
Pin 1 identifier
ESDS identification (optional)

3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable)
above.
3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics areas specified in 1.3, 1.4, and table I herein.
3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein.
3.5 Diagrams.
3.5.1

Case outline. The case outline shall be as shown in 1.2.2 and figure 1.

3.5.2

Terminal connections. The terminal connections shall be as shown in figure 2.

3.5.3

Functional block diagram. The functional block diagram shall be as shown in figure 3.

3.5.4

Typical Active mode supply currents, No Wait states. The typical Active mode supply currents, No Wait states shall be as
shown in figure 4.

3.5.5

Typical Low-Level Output Current vs Low-Level Output Voltage, VCC = 2.0 V. The typical Low-Level Output Current vs LowLevel Output Voltage, VCC = 2.0 V shall be as shown in figure 5.

3.5.6

Typical Low-Level Output Current vs Low-Level Output Voltage, VCC = 3.0 V. The typical Low-Level Output Current vs LowLevel Output Voltage, VCC = 3.0 V shall be as shown in figure 6.

3.5.7

Typical High-Level Output Current vs High-Level Output Voltage, VCC = 2.0 V. The Typical High-Level Output Current vs
High-Level Output Voltage, VCC = 2.0 V shall be as shown in figure 7.

3.5.8

Typical High-Level Output Current vs High-Level Output Voltage, VCC = 3.0 V. The Typical High-Level Output Current vs
High-Level Output Voltage, VCC = 3.0 V shall be as shown in figure 8.

3.5.9

SPI Master mode, CKPH = 0. The SPI Master mode, CKPH = 0 shall be as shown in figure 9.

3.5.10

SPI Master mode, CKPH = 1. The SPI Master mode, CKPH = 0 shall be as shown in figure 10.

3.5.11SPI Slave mode, CKPH = 0. The SPI Slave mode, CKPH = 0 shall be as shown in figure 11.

3.5.12SPI Slave mode, CKPH = 1. The SPI Slave mode, CKPH = 0 shall be as shown in figure 12.

3.5.13I2C Mode timing. The I2C mode timing shall be as shown in figure 13.

3.5.14

Typical temperature sensor voltage. The typical temperature sensor voltage shall be as shown in figure 14.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
16236
REV

C

DWG NO.
V62/14644
PAGE 4TABLE I. Electrical performance characteristics. 1/
Test

Execution

VCC

Frequency (fMCLK = fSMCLK)

Memory

1 MHz

4 MHz

8 MHz

16 MHzTyp Max
Typ Max Typ Max Typ
Active Mode Supply Current Into VCC Excluding External Current 2/ 3/ 4/ 5/
IAM, FRAM_UNI
7/
IAM,0%

8/

IAM,50%
8/ 9/
IAM,66%
8/ 9/
IAM,75%
8/ 9/
IAM,100%
8/ 9/
IAM, RAM 9/
10/

Typ

24 MHz

Max

Max

FRAM
0% cache hit
ratio
FRAM
50% cache hit
ratio
FRAM
66% cache hit
ratio
FRAM
75% cache hit
ratio
FRAM
100% cache hit
ratio
RAM

3V

0.42

3V

0.31

0.73

1.3

1.75

2.1

2.5

3V

0.27

0.58

1.0

1.55

1.9

2.2

3V

0.25

0.5

0.82

1.3

1.6

1.8

3V

0.2

0.44

0.3

0.56

0.42

0.81

0.73

1.17

0.88

1.32

1.0

1.53

3V

0.2

0.41

0.35

0.56

0.55

0.77

1.0

1.27

1.20

1.47

1.45

1.8

Symbol

VCC

1.7

2.2

2.9

2.3

-55 °C
Typ

1.9

Typ

0.27

1.2

1.53

20 MHz

3V

0.75

1.0

Max

Unit

FRAM

Test

0.58

5/

3.0

2.8

25 °C
Max

Typ

2.2
3.7

mA

3.45

4.3

85 °C

Unit

Max

Typ

Max

Low-Power Mode Supply Currents (Into VCC) Excluding External Current 11/ 3/ 4/
Low power mode 0
12/ 13/Low power mode 0
13/ 14/
Low power mode 0
13/ 15/
Low power mode 2
16/ 17/
Low power mode 3, crystal mode
17/ 18/Low power mode 3, VLO mode
17/ 19/Low power mode 4 17/ 20/
Low power mode 3.5 21/
Low power mode 4.5 22/

ILPM0, 1MHz
ILPM0, 8MHz
ILPM0, 24MHz
ILMP2
ILMP3, XT1LF

2 V, 3 V
2 V, 3 V
2 V, 3 V
2 V, 3 V
2 V, 3 V

166
170
274
56
3.4

175
177
285
61
6.4

244
340
80
15

225
225
340
110
48

360
455
210
150

µA

ILPM3,VLO

2 V, 3 V

3.3

6.3

15

48

150

ILPM4
ILPM3.5
ILPM4.5

2 V, 3 V
2 V, 3 V
2 V, 3 V

2.9
1.3
0.3

5.9
1.5
0.32

15
2.2
0.66

48
2.8
0.57

150
5.0
2.55

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
16236
REV

C

DWG NO.
V62/14644
PAGE 5TABLE I. Electrical performance characteristics - Continued. 1/
Test

SymbolTest conditions

VCC

Limits11/

Min

Schmitt-Trigger Inputs – General Purpose I/O(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.1, PJ.0 to PJ.5, ������𝐑𝐑𝐑𝐑𝐑𝐑/NMI)
Positive going input threshold

VIT+

voltage

Negative going input threshold

VIT-

voltage
Input voltage hysteresis (VIT+ - VIT-)

Vhys

Pull up or pull down resistor

RPull

Input capacitanceCI
24/t(int)

0.7

1.7

3V

1.45

2.12

2V

0.41

1.101

3V

0.72

1.68

2V

0.24

0.855

3V

0.27
19

51

kΩ
pF

23/

External trigger pulse
duration to set interrupt flag

25/

V

1.02
35
5

Leakage Current – General Purpose I/O(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.1, PJ.0 to PJ.5, ������𝐑𝐑𝐑𝐑𝐑𝐑/NMI)
High-impedance leakage current

Max

2V

For pullup: VIN = VSS
For pulldown: VIN = VCC

Inputs – Ports P1 and P2 (P1.0 to P1.7, P2.0 to P2.7)
External interrupt timing

Typ

Unit

26/

2 V, 3V20

ns

2 V, 3 V

-65

65

nA

2V

VCC – 0.25

VCC

V

VCC – 0.60

VCC

VCC – 0.25

VCC

VCC – 0.60

VCC

VSS

VSS + 0.25

VSS

VSS + 0.60

VSS

VSS + 0.25

VSS

VSS + 0.60

Outputs – General Purpose I/O(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.1, PJ.0 to PJ.5)
High level output voltage

Low level output voltage

VOH

VOL

I(OHmax) = –1 mA

27/

I(OHmax) = –3 mA

28/

I(OHmax) = –2 mA

27/

I(OHmax) = –6 mA

28/

I(OLmax) = 1 mA

27/

I(OLmax) = 3 mA

28/

I(OLmax) = 2 mA

27/

I(OLmax) = 6 mA

28/

3V
2V
3V

Output Frequency – General Purpose I/O(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.1, PJ.0 to PJ.5)
Port output frequency (with load)
Clock output frequency

fPx,yfPort_CLKPx.y29/ 30/

2V

16

3V

24

ACLK, SMCLK, or MCLK at
configured output port,

2V

16

C MHz L = 20 pF, no DC
loading
30/

3V

24

CAGE CODE
16236

DWG NO.
V62/14644

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
A

REV

C

PAGE 6MHzTABLE I. Electrical performance characteristics - Continued. 1/
Test

SymbolTest conditions

VCC

11/
Crystal Oscillator, XT1, Low-Frequency (LF) Mode

Additional current consumption
XT1 LF mode from lowest drive
setting

XT1 oscillator crystal frequency,
LF modeXT1 oscillator logic-level squarewave input frequency, LF mode

Oscillation allowance for LF
crystals

37/

Integrated effective load
capacitance, LF mode 38/ 39/

Typ60ƒOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVE = {2},TA = 25°C, CL,eff = 9 pF

3V

90

3V

140

fXT1,LF0ƒOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVE = {3},TA = 25°C, CL,eff = 12 pF
XTS = 0, XT1BYPASS = 0

fXT1,LF,SW

XTS = 0, XT1BYPASS = 1 32/ 33/

210

OALF

XTS = 0,XT1BYPASS = 0, XT1DRIVE = {0},ƒXT1,LF = 32768 Hz, CL,eff = 6 pF

300

fFault,LF

XTS = 0,XT1BYPASS = 0, XT1DRIVE = {3},ƒXT1,LF = 32768 Hz, CL,eff = 12 pF
XTS = 0, Measured at ACLK,ƒXT1,LF = 32768 Hz
XTS = 036/

ΔIVCC.LF

tSTART,LF

CL,eff

Unit
Max

31/
3V

Duty cycle, LF mode

Startup time, LF modeMinƒOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVE = {1},CL,eff = 9 pF, TA = 25°C,

34/

Oscillator fault frequency, LF
mode
35/

LimitsƒOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVE = {0},TA = 25°C, CL,eff = 6 pFƒOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVE = {3},TA = 25°C, CL,eff = 12 pF
XTS = 0

nA

32768
10

3V

32.768

Hz
50

kΩ

30

70

%

10

10000

Hz

1000

DLA LAND AND MARITIMECOLUMBUS, OHIO

1

CAGE CODE
16236
REV

ms

1000

See footnote at end of table.

SIZE
A

kHz

C

DWG NO.
V62/14644
PAGE 7

pF

TABLE I. Electrical performance characteristics - Continued. 1/
Test

SymbolTest conditions

VCC

11/
Crystal Oscillator, XT1, Low-Frequency (LF) ModeMin

XT1 oscillator crystal frequency,
HF mode 0
XT1 oscillator crystal frequency,
HF mode 1
XT1 oscillator crystal frequency,
HF mode 2
XT1 oscillator crystal frequency,
HF mode 3
XT1 oscillator logic-level squarewave input frequency, HF mode

Oscillation allowance for HF
crystals
40/

Startup time, HF mode 37/

IVCC,HF

fXT1,HF0

3VƒOSC = 8 MHz,XTS = 1, XOSCOFF = 0,
XT1BYPASS = 0, XT1DRIVE = {1},TA = 25°C, CL,eff = 16 pF
ƒOSC = 16 MHz,XTS = 1, XOSCOFF = 0,
XT1BYPASS = 0, XT1DRIVE = {2},TA = 25°C, CL,eff = 16 pF
ƒOSC = 24 MHz,XTS = 1, XOSCOFF = 0,
XT1BYPASS = 0, XT1DRIVE = {3},TA = 25°C, CL,eff = 16 pF
XTS = 1,XT1BYPASS = 0, XT1DRIVE = {0} 33/

fXT1,HF1

XTS = 1,XT1BYPASS = 0, XT1DRIVE = {1}33/

fXT1,HF2

XTS = 1,XT1BYPASS = 0, XT1DRIVE = {2}33/

fXT1,HF3

XTS = 1,XT1BYPASS = 0, XT1DRIVE = {3}33/

fXT1,HF,SW

XTS = 1,XT1BYPASS = 1
32/ 33/
XTS = 1,XT1BYPASS = 0, XT1DRIVE = {0},ƒXT1,HF = 4 MHz, CL,eff = 16 pF

OAHF

tSTART,HF

Typ

Unit
Max

31/

ƒOSC = 4 MHz,XTS = 1, XOSCOFF = 0,
XT1BYPASS = 0, XT1DRIVE = {0},TA = 25°C, CL,eff = 16 pF
XT1 oscillator crystal current HF
mode

Limits

175

µA

300

350

550

4

6

6

10

10

16

16

24

1

24
450

XTS = 1,XT1BYPASS = 0, XT1DRIVE = {1},ƒXT1,HF = 8 MHz, CL,eff = 16 pF

320

XTS = 1,XT1BYPASS = 0, XT1DRIVE = {2},ƒXT1,HF = 16 MHz, CL,eff = 16 pF
XTS = 1,XT1BYPASS = 0, XT1DRIVE = {3},ƒXT1,HF = 24 MHz, CL,eff = 16 pF
ƒOSC = 4 MHz, XTS = 1,
XT1BYPASS = 0, XT1DRIVE = {0},TA = 25°C, CL,eff = 16 pF

200

3V

8

2

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIOCAGE CODE
16236
REV

Ω

200

ƒOSC = 4 MHz, XTS = 1,
XT1BYPASS = 0, XT1DRIVE = {0},TA = 25°C, CL,eff = 16 pF

SIZE
A

MHz

C

DWG NO.
V62/14644
PAGE 8ms

TABLE I. Electrical performance characteristics - Continued. 1/
Test

SymbolTest conditions

VCC

11/
Crystal Oscillator, XT1, Low-Frequency (LF) Mode - Continued
Integrated effective load capacitance41/
42/
Duty cycle, HF mode

CL,effMin

XTS = 1Max

140Oscillator fault frequency, HF mode
fFault,HF
35/
Internal Very-Low-Power Low-Frequency Oscillator (VLO)

50

145

fVLO

Measured at ACLKVLO frequency temperature drift

dfVLO/dT

Measured at ACLK43/

VLO frequency supply voltage drift

dfVLO/dVCC

Measured at ACLK

44/

fVLO,DC

Measured at ACLK

fDCO,LO

Measured at ACLK,DCORSEL = 0

Duty cycle

Typ

Unit

31/

XTS = 1, Measured at
ACLK,
ƒXT1,HF2 = 24 MHz
XTS = 1 36/

VLO frequency

Limits2 V to 3.6 V

4.3

8.3

pF
60

%

900

kHz

13.3

kHz

0.5

%/°C

4
35

%/V

50

65

%

2 V to 3.6 V,-40°C to 85°C

5.37

±5%

MHz

Measured at ACLK,DCORSEL = 1

2 V to 3.6 V,-40°C to 85°C

16.2

±5%

Measured at ACLK,DCORSEL = 0

2 V to 3.6 V,-40°C to 85°C

6.67

±5%

Measured at ACLK,DCORSEL = 1

2 V to 3.6 V,-40°C to 85°C

20

±5%

Measured at ACLK,DCORSEL = 0

2 V to 3.6 V,-40°C to 85°C

8±5%

Measured at ACLK,DCORSEL = 1

2 V to 3.6 V,-40°C to 85°C

23.8

±5%

Measured at ACLK,
divide by 1,
No external divide,
All DCO setting

2 V to 3.6 V,-40°C to 85°C

50

65

DCO frequencies
DCO frequency low, trimmed

DCO frequency mid, trimmed

DCO frequency high, trimmed

Duty cycle

fDCO,MD

fDCO,HIfDCO,DC35

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
16236
REV

C

DWG NO.
V62/14644
PAGE 9%TABLE I. Electrical performance characteristics - Continued. 1/
Test

SymbolTest conditions

VCC

11/

Limits
Min

Typ

Unit
Max

MODOSC
Current consumption

IMODOSC

Enabled

2 V to 3.6 V

44

MODOSC frequency

fMODOSC

Duty cycle

fMODOSC,DC

Measured at ACLK,
divide by 1

Core voltage, active mode

VCORE(AM)2 V ≤ DVCC ≤ 3.6 V

1.5Core voltage, low-current mode

VCORE(LPM)

2 V ≤ DVCC ≤ 3.6 V

1.5

µA

2 V to 3.6 V

4.2

5.0

5.7

MHz

2 V to 3.6 V

35

50

65

%

PMM, Core Voltage
V

PMM, SVS, BOR
SVSH current consumption, active mode

ISVSH,AMVCC = 3.6 V

5

SVSH current consumption, low power modes

ISVSH,LPM

VCC = 3.6 V

0.8

SVSH on voltage level, falling supply voltage

VSVSH-SVSH off voltage level, rising supply voltage

VSVSH+

1.81

1.88

1.95

1.85

1.93

2

SVSH propagation delay, active modetPD,SVSH, AM

dVCC/dt = 10 mV/μs

10

SVSH propagation delay, low power modes

tPD,SVSH, LPM

dVCC/dt = 1 mV/μs

30

SVSL current consumption

µA

ISVSL

V
µs

0.3

µA
V

SVSL on voltage level

VSVSL–

1.42

SVSL off voltage level

VSVSL+

1.47

Wake-Up from Low Power Modes
Wake-up time from LPM0 to active mode
45/

tWAKE-UP

Wake-up time from LPM1, LPM2 to active
mode
45/

tWAKE-UP

Wake-up time from LPM3 or LPM4 to active
mode
45/

tWAKE-UP

Wake-up time from LPM3.5 or LPM4.5 toactive mod����� to active mode 46/
Wake-up time from RST
Wake-up time from BOR or power-up to
active mode�����/NMI terminal
Pulse duration required at RST
to accept a reset event
47/

2 V, 3 V,-40°C to 85°C

LPM0

0.58

1.1

12

25

78

165

2 V, 3 V,
0°C to 85°C

310

575

2 V, 3 V,-40°C to 85°C

310

1100

2 V, 3 V,-40°C to 85°C

230

LPM12

LPM34

tWAKE-UP
LPMx.5tWAKE-UP

VCC stable

RESET

tWAKE-UP BOR

dVCC/dt = 2400 V/s

1.6

tRESET

4

SIZE
ACAGE CODE
16236
REV

C

ms
ns

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIOµs

DWG NO.
V62/14644
PAGE 10

TABLE I. Electrical performance characteristics - Continued. 1/
Test

SymbolTest conditions

VCC

11/

Limits
Min

Typ

Unit
Max

Timer_A
Timer_A input clock
frequency

fTA

Internal: SMCLK, ACLK, External:
TACLK
Duty cycle = 50% ± 10%

Timer_A capture timingtTA,cap

All capture inputs, Minimum pulse
duration required for capture

Timer_B input clock
frequency

fTA

Internal: SMCLK, ACLK, External:
TBCLK
Duty cycle = 50% ± 10%

Timer_B capture timingtTA,cap

All capture inputs, Minimum pulse
duration required for capture

2 V, 3 V

24

20

MHz

ns

Timer_B
2 V, 3 V

24

20

MHz

ns

eUSCI (UART Mode) Recommended Operating Conditions
eUSCI input clock
frequency

feUSCIBITCLK clock frequency(equals baud rate in
MBaud)fBITCLKInternal: SMCLK, ACLK, External: UCLK
Duty cycle = 50% ± 10%

fSYSTEM

MHz

5

eUSCI (UART Mode)UCGLITx = 0
UART receive deglitch
tt
UCGLITx = 1
time 48/UCGLITx = 2
UCGLITx = 3
eUSCI (SPI Master Mode) Recommended Operating Conditions
eUSCI input clock
frequency

feUSCI

2 V, 3 V

Internal: SMCLK, ACLK
Duty cycle = 50% ± 10%

5
20
35
50

15
45
80
110

20
60
120
180

ns

fSYSTEMMHz

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
16236
REV

C

DWG NO.
V62/14644
PAGE 11TABLE I. Electrical performance characteristics - Continued. 1/
Test

SymbolTest conditions

VCC

Limits11/
eUSCI (SPI Master Mode)

Min

Max

49/

STE lead time, STE active totSTE,LEAD

clock
STE lag time, Last clock totSTE,LAG

STE inactive
STE access time, STE activetSTE,ACC

to SIMO data out
STE disable time, STE inactivetSTE,DIS

to SIMO high impedance

UCSTEM = 0, UCMODEx = 01 or 10

1

UCxCLKUCSTEM = 1, UCMODEx = 01 or 10

2 V, 3 V

1cyclesUCSTEM = 0, UCMODEx = 01 or 10

1

UCSTEM = 1, UCMODEx = 01 or 10

1

UCSTEM = 0, UCMODEx = 01 or 10

55

UCSTEM = 1, UCMODEx = 01 or 10

35

UCSTEM = 0, UCMODEx = 01 or 10

40

UCSTEM = 1, UCMODEx = 01 or 10

SOMI input data setup time

tSU,MISOMI input data hold time

tHD,MISIMO output data valid timetVALID,MO50/
SIMO output data hold time

tHD,MO

ns

30
2V

35

3V

35

2V

0

3V

0

UCLK edge to SIMO valid,2V30

CL = 20 pF

3V30

CL = 20 pF

2V

0

3V

0

2V

7

3V

7

51/
eUSCI (SPI Slave Mode)

Typ

Unit

52/

STE lead time, STE active totSTE,LEAD

clock
STE lag time, Last clock to STE

tSTE,LAG

inactive
STE access time, STE active totSTE,ACC

SOMI data out
STE disable time, STE inactivetSTE,DIS

to SOMI high impedance
SIMO input data setup time

tSU,SISIMO input data hold time

tHD,SISOMI output data valid time (tVALID,SO

SOMI output data hold time

tHD,SO

2V

0

3V

0

ns

2V

65

3V

40

2V

40

3V

35

2V

2

3V

2

2V

5

3V

5

UCLK edge to SOMI valid,2V30

CL = 20 pF

3V

CL = 20 pF

2V

4

3V

4

30

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
16236
REV

C

DWG NO.
V62/14644
PAGE 12TABLE I. Electrical performance characteristics - Continued. 1/
Test

SymbolTest conditions

VCC

11/
eUSCI (I2C Mode)

Limits
Min

Typ

Unit
Max

see FIGURE 13.

eUSCI input clock frequency

feUSCISCL clock frequency

fSCL

Hold time (repeated) START

tHD,STA

Setup time for a repeated STARTtSU,STAInternal: SMCLK, ACLK,
External: UCLK
Duty cycle = 50% ± 10%
2 V, 3 V

0

fSCL = 100 kHz

4.0

fSCL > 100 kHz

0.6

fSCL = 100 kHz

4.7

fSCL > 100 kHz

0.6

Data hold time

tHD,DAT0

Data setup time

tSU,DAT

250

Setup time for STOP

tSU,STO

Pulse duration of spikes

tSP

suppressed by input filter

Clock low timeouttTIMEOUT

fSYSTEM

MHz

400

kHz
µs

ns

fSCL = 100 kHz

4.0

µs

fSCL > 100 kHz

0.6

UCGLITx = 0

50

600

UCGLITx = 1

25

300

UCGLITx = 2

12.5

150

UCGLITx = 3

6.25

ns

75

UCCLTOx = 1

27

UCCLTOx = 2

30

UCCLTOx = 3

33

ms

10-Bit ADC, Power Supply and Input Range Conditions
Analog supply voltage

AVCC

AVCC and DVCC are connected
together,
AVSS and DVSS are connected together,
V(AVSS) = V(DVSS) = 0 V

2.0

3.6

Analog input voltage range

V(Ax)All ADC10 pins

0

AVCC

Operating supply current into
AVCC terminal, reference current

IADC10_A

fADC10CLK = 5 MHz, ADC10ON = 1,
REFON = 0, SHT0 = 0, SHT1 = 0,

2V

90

150

ADC10DIV = 0

3V

100

170

not included
Input capacitanceCI

Only one terminal Ax can be selected
at one time from the pad to the
ADC10_A capacitor array including
wiring and pad

Input MUX ON resistance

RI

AVCC ≥ 2 V, 0 V ≤ VAx ≤ AVCC

636

DLA LAND AND MARITIMECOLUMBUS, OHIOCAGE CODE
16236
REV

C

µA

pF

See footnote at end of table.

SIZE
A

V

DWG NO.
V62/14644
PAGE 13kΩ

TABLE I. Electrical performance characteristics - Continued. 1/
Test

SymbolTest conditions

VCC

11/

Limits
Min

Unit

Typ

Max

10-Bit ADC, Timing Parameters
fADC10CLKInternal ADC10 oscillator(MODOSC)

Conversion time

fADC100SCtCONVERT

Turn on settling time of
the ADCtADC10ON

Sampling time

tSampleFor specified performance of ADC10 linearity
parameters
ADC10DIV = 0,
fADC10CLK = fADC10OSC
REFON = 0, Internal oscillator,
12 ADC10CLK cycles, 10-bit mode,fADC10OSC = 4.5 MHz to 5.5 MHz
External fADC10CLK from ACLK, MCLK, or
SMCLK,
ADC10SSEL ≠ 0
The error in a conversion started after tADC10ON
is less than ±0.5 LSB,
Reference and input signal already settled
RS = 1000 Ω, RI = 36000 Ω, CI = 3.5 pF,

2 V to 3.6 V

0.45

5

5.5

2 V to 3.6 V

4.2

4.5

5.7

2 V to 3.6 V

2.18

2V

1.5

Approximately eight Tau (Ƭ) are required to get
an error of less than ±0.5 LSB

3V

2.0

2 V to 3.6 V

-1.4
-1.3

1.3

-1.2

1.2

2 V to 3.6 V

MHz

2.67

µs

100

ns

55/

µs

10-Bit ADC, Linearity Parameters
Integral linearity error

EI

1.4 V ≤ (VeREF+ – VREF–/VeREF–)min ≤ 1.6 V

Differential linearity error

ED(VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–)2 V to 3.6 V

Offset error

EO(VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–)2 V to 3.6 V

Gain error, externalreference(VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–)2 V to 3.6 V

EG

1.6 V < (VeREF+ – VREF–/VeREF–)min ≤ VAVCC

Gain error, internalreference
Total unadjusted error,
external reference

ET(VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–)2 V to 3.6 V

Total unadjusted error,
internal reference 56/

1.4

±2.5
-1.4

mV
1.4

DLA LAND AND MARITIMECOLUMBUS, OHIOCAGE CODE
16236
REV

C

LSB

±4

%

±2.3

LSB

±4

%

See footnote at end of table.

SIZE
A

LSB

DWG NO.
V62/14644
PAGE 14TABLE I. Electrical performance characteristics - Continued. 1/
Test

SymbolTest conditions

VCC

11/
REF, External Reference

Min

Static input current

Capacitance at VREF+ or
VREF- terminal
61/
REF, Built-In Reference
Positive built-in reference

Max

VeREF+

VeREF+ > VeREF– 58/

1.4

AVCC

VeREF-

VeREF+ > VeREF– 59/

0

1.2

1.4

AVCC

(VeREF+ –VeREF+ > VeREF– 60/
VREF–/VeREF–)
1.4 V ≤ VeREF+ ≤ VAVCC,
VeREF– = 0 V,
IVeREF+,
fADC10CLK = 5 MHz,
IVeREF–
ADC10SHTx = 1h,
Conversion rate 200 ksps
1.4 V ≤ VeREF+ ≤ VAVCC,
VeREF– = 0 V,
fADC10CLK = 5 MHz,ADC10SHTx = 1h,
Conversion rate 200 ksps
CVREF+,
CVREF-

VREF+

voltage output
AVCC minimum voltage,

AVCC(min)Positive built-in reference active

2 V, 3 V

REFVSEL = {2} for 2.5 V, REFON = 1

3V

µF

2.5

2.61

REFVSEL = {1} for 2 V, REFON = 1

1.91

2.0

2.09

1.5

1.57

REFVSEL = {0} for 1.5 V, REFON = 1

1.43

REFVSEL = {0} for 1.5 V

2.0

REFVSEL = {1} for 2 V

2.2

V

2.7

fADC10CLK = 5 MHz
REFON = 1, REFBURST = 0

Temperature coefficient of builtin reference

TREF+

63/

µA

2.39

REFVSEL = {2} for 2.5 V

tSETTLE

±6

10

IREF+

PSRR_DCV±1

Operating supply current into
AVCC terminal 62/

Settling time of reference
voltage

Typ

Unit

57/

Positive external reference
voltage input
Negative external reference
voltage input
Differential external reference
voltage input

Power supply rejection ratio(DC)

Limits3V

33µA

REFVSEL = (0, 1, 2}, REFON = 1

±35

ppm/
°C

AVCC = AVCC (min) - AVCC(max),
TA = 25°C, REFON = 1,
REFVSEL = (0} for 1.5 V

1600

µV/V

AVCC = AVCC (min) - AVCC(max),
TA = 25°C, REFON = 1,
REFVSEL = (1} for 2 V

1900

AVCC = AVCC (min) - AVCC(max),
TA = 25°C, REFON = 1,
REFVSEL = (2} for 2.5 V

3600

AVCC = AVCC (min) - AVCC(max),
REFVSEL = (0, 1, 2},
REFON = 0 → 1

30

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
16236
REV

C

DWG NO.
V62/14644
PAGE 15µs

TABLE I. Electrical performance characteristics - Continued. 1/
Test

SymbolTest conditions

VCC

11/

Limits
Min

Typ

Unit
Max

REF, Temperature Sensor and Built-In VMID
64/

Sample time required ifchannel 10 is selected

65/

AVCC divider at channel 11

VSENSOR

ADC10ON = 1, INCH = 0Ah,
TA = 0°C

2 V, 3 V

790

TCSENSOR

ADC10ON = 1, INCH = 0Ah

2 V, 3 V

2.55

tSENSORsampl

ADC10ON = 1, INCH = 0Ah,

2V

30

Error of conversion result ≤ 1 LSB

3V30

ADC10ON = 1, INCH = 0Bh,

2V

0.96

1.0

1.04

3V

1.43

1.5

1.57

2 V, 3 V

1000

e)

VMID

VMID is ~0.5 × VAVCC
Sample time required ifchannel 11 is selected

66/

tVMID(sample)

ADC10ON = 1, INCH = 0Bh,
Error of conversion result ≤ 1 LSB

mV/°C
µs
V
ns

Comparator_D

Propagation delay,
AVCC = 2 V to 3.6 V

tpd

Overdrive = 10 mV,
VIN- = (VIN+ – 400 mV) to(VIN+ + 10 mV)
Overdrive = 100 mV,
VIN- = (VIN+ – 400 mV) to(VIN+ + 100 mV)
Overdrive = 250 mV,
VIN- = (VIN+ – 400 mV) to(VIN+ + 250 mV)
CDF = 1, CDFDLY = 00
CDF = 1, CDFDLY = 01
CDF = 1, CDFDLY = 10
CDF = 1, CDFDLY = 11
AVCC = 2 V to 3.6 V
AVCC = 2 V to 3.6 V

49

100

202

ns

1.1
1.8
3.31
6.5
26
AVCC 1µs

8050Filter timer added to the
propagation delay of thecomparator

tfilter

0.28
0.49
0.85
1.59
-26
0

0.5
0.9
1.6
3.0

Input offset
Common mode input range

VoffsetVic

Comparator only
Reference buffer and RladderComparator enable time

Icomp(AVCC)
Iref(AVCC)

CDON = 1, AVCC = 2 V to 3.6 V
CDREFLx = 01, AVCC = 2 V to 3.6 V

28
20

tenable,comp

1.1

2.3

Resistor ladder enable time

tenable,rladder

CDON = 0 to CDON = 1,
AVCC = 2 V to 3.6 V
CDON = 0 to CDON = 1,
AVCC = 2 V to 3.6 V

1.1

2.3

Reference voltage for a tap

VCB_REF

µA
µA

VIN x
VIN x
VIN x
(n +0.49) (n + 1) (n + 1.51)
/ 32
/ 32
/ 32

VIN = voltage input to the R-ladder,n = 0 to 31

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
16236
REV

C

mV
V

DWG NO.
V62/14644
PAGE 16µs

V

TABLE I. Electrical performance characteristics - Continued. 1/
Test

SymbolTest conditions

VCC

11/

Limits
Min

Typ

Unit
Max

FRAM
Write supply voltage
Word or byte write time
Read access time
67/
Precharge time
67/
Cycle time, read or write operation
67/
Read and write endurance
Data retention duration

DVCC(WRITE)tWRITEtACCESStPRECHARGEtCYCLEtRetention

2.0

3.6
120
60
60

V
ns

120
1015
100
40
10

TJ = 25°C
TJ = 70°C
TJ = 85°C

cyclesyears

JTAG and Spy-Bi-Wire Interface
Spy-Bi-Wire input frequency
Spy-Bi-Wire low clock pulse duration
Spy-Bi-Wire enable time (TEST high toacceptance of first clock edge)
Spy-Bi-Wire return to normal operationtime
TCK input frequency, 4-wire JTAGfSBWtSBW,LowtSBW, En

Internal pulldown resistance on TEST

Rinternal

2 V, 3 V
2 V, 3 V
2 V, 3 V

tSBW,Rst
fTCK

2V
3V
2 V, 3 V

0
0.025

20
15
1

18

37

0
0
19

5
10
51.5

35

MHz
µs

MHz
MHz
kΩ

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
16236
REV

C

DWG NO.
V62/14644
PAGE 17

TABLE I. Electrical performance characteristics - Continued.
1/

2/
3/
4/
5/
6/

7/
8/

9/

10/

11/
12/
13/
14/
15/
16/
17/
18/
19/

Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the
specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may notnecessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or
design.
Over recommended operating free-air temperature (unless otherwise noted).
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal andexternal load capacitance are chosen to closely match the required 9 pF.
Characterized with program executing typical data processing.
At MCLK frequencies above 8 MHz, the FRAM requires wait states. When wait states are required, the effective MCLK frequency,
fMCLK,eff, decreases. The effective MCLK frequency is also dependent on the cache hit ratio. SMCLK is not affected by the numberof wait states or the cache hit ratio. The following equation can be used to compute fMCLK,eff:
fMCLK,eff,MHz = fMCLK,MHz x 1 / [# of wait states x ((1 - cache hit ratio percent/100)) + 1].
Program and data reside entirely in FRAM. No wait states enabled. DCORSEL = 0, DCOFSELx = 3 (fDCO = 8 MHz).
MCLK = SMCLK.
Program resides in FRAM. Data resides in SRAM. Average current dissipation varies with cache hit-to-miss ratio as specified.
Cache hit ratio represents number cache accesses divided by the total number of FRAM accesses. For example, a 25% ratio
implies one of every four accesses is from cache, the remaining are FRAM accesses.
For 1, 4, and 8 MHz, DCORSEL = 0, DCOFSELx = 3 (fDCO = 8 MHz). MCLK = SMCLK. No wait states enabled.
For 16 MHz, DCORSEL = 1, DCOFSELx = 0 (fDCO = 16 MHz).MCLK = SMCLK. One wait state enabled.
For 20 MHz, DCORSEL = 1, DCOFSELx = 2 (fDCO = 20 MHz).MCLK = SMCLK. Three wait states enabled.
For 24 MHz, DCORSEL = 1, DCOFSELx = 3 (fDCO = 24 MHz).MCLK = SMCLK. Three wait states enabled.
See FIGURE 4 for typical curves. Each characteristic equation shown in the graph is computed using the least squares method forbest linear fit using the typical data shown in manufacturer data.
fACLK = 32786 Hz, fMCLK = fSMCLK at specified frequency. No peripherals active.
XTS = CPUOFF = SCG0 = SCG1 = OSCOFF= SMCLKOFF = 0.
All execution is from RAM.
For 1, 4, and 8 MHz, DCORSEL = 0, DCOFSELx = 3 (fDCO = 8 MHz). MCLK = SMCLK.
For 16 MHz, DCORSEL = 1, DCOFSELx = 0 (fDCO = 16 MHz). MCLK = SMCLK.
For 20 MHz, DCORSEL = 1, DCOFSELx = 2 (fDCO = 20 MHz). MCLK = SMCLK.
For 24 MHz, DCORSEL = 1, DCOFSELx = 3 (fDCO = 24 MHz). MCLK = SMCLKOver recommended ranges of supply voltage and operating at -40°C ≤ TJ ≤ 80°C (unless otherwise noted).
Current for watchdog timer clocked by SMCLK included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0), fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = 1 MHz. DCORSEL = 0,
DCOFSELx = 3 (fDCO = 8 MHz).
Current for brownout, high-side supervisor (SVSH) and low-side supervisor (SVSL) included.
Current for watchdog timer clocked by SMCLK included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0), fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = 8 MHz. DCORSEL = 0,
DCOFSELx = 3 (fDCO = 8 MHz).
Current for watchdog timer clocked by SMCLK included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0), fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = 24 MHz. DCORSEL = 1,
DCOFSELx = 3 (fDCO = 24 MHz).
Current for watchdog timer (clocked by ACLK) and RTC (clocked by XT1 LF mode) included. ACLK = low-frequency crystal
operation (XTS = 0, XT1DRIVEx = 0). CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 (LPM2), fACLK = 32768 Hz, fMCLK = 0 MHz,fSMCLK = fDCO = 0 MHz, DCORSEL = 0, DCOFSELx = 3, DCO bias generator enabled.
Current for brownout, high-side supervisor (SVSH) included. Low-side supervisor disabled (SVSL).
Current for watchdog timer (clocked by ACLK) and RTC (clocked by XT1 LF mode) included. ACLK = low-frequency crystal
operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz.
Current for watchdog timer (clocked by ACLK) included. ACLK = VLO.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = fVLO, fMCLK = fSMCLK = fDCO = 0 MHz

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
16236
REV

C

DWG NO.
V62/14644
PAGE 18

TABLE I. Electrical performance characteristics - Continued.
20/
21/
22/
23/
24/
25/
26/
27/
28/
29/
30/
31/

32/
33/
34/

35/
36/
37/
38/
39/
40/
41/
42/
43/
44/
45/

CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 (LPM4), fDCO = fACLK = fMCLK = fSMCLK = 0 MHz.
Internal regulator disabled. No data retention. RTC active clocked by XT1 LF mode.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1, PMMREGOFF = 1 (LPM3.5), fDCO = fACLK = fMCLK = fSMCLK = 0 MHz
Internal regulator disabled. No data retention.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1, PMMREGOFF = 1 (LPM4.5), fDCO = fACLK = fMCLK = fSMCLK = 0 MHz
Some devices may contain additional ports with interrupts. See the block diagram and terminal function descriptions.
An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger
signals shorter than t(int).
The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor isdisabled.
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage
drop specified.
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±100 mA to hold the maximum voltage
drop specified.
A resistive divider with 2 × 1.6 kΩ between VCC and VSS is used as load. The output is connected to the center tap of the divider.
CL = 20 pF is connected from the output to VSS.
The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
To improve EMI on the XT1 oscillator, the following guidelines should be observed.
•
Keep the trace between the device and the crystal as short as possible.
•
Design a good ground plane around the oscillator pins.
•
Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
•
Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
•
Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.
•
If conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins.
When XT1BYPASS is set, XT1 circuits are automatically powered down. Input signal is a digital square wave with parametrics
defined in the Schmitt-trigger Inputs section of the manufacturer data sheet.
Maximum frequency of operation of the entire device cannot be exceeded.
Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the
XT1DRIVE settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following
guidelines, but should be evaluated based on the actual crystal selected for the application:•
For XT1DRIVE = {0}, CL,eff ≤ 6 pF.
•
For XT1DRIVE = {1}, 6 pF ≤ CL,eff ≤ 9 pF.
•
For XT1DRIVE = {2}, 6 pF ≤ CL,eff ≤ 10 pF.
•
For XT1DRIVE = {3}, 6 pF ≤ CL,eff ≤ 12 pF
Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies in between might set the flag.
Measured with logic-level input frequency but also applies to operation with crystals.
Includes startup counter of 4096 clock cycles.
Requires external capacitors at both terminals.
Values are specified by crystal manufacturers. Include parasitic bond and package capacitance (approximately 2 pF per pin).
Recommended values supported are 6 pF, 9 pF, and 12 pF. Maximum shunt capacitance of 1.6 pF.
Oscillation allowance is based on a safety factor of 5 for recommended crystals.
Includes parasitic bond and package capacitance (approximately 2 pF per pin). Because the PCB adds additional capacitance, it isrecommended to verify the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitanceshould always match the specification of the used crystal.
Requires external capacitors at both terminals. Values are specified by crystal manufacturers. Recommended values supported
are 14 pF, 16 pF, and 18 pF. Maximum shunt capacitance of 7 pF.
Calculated using the box method: (MAX(-40 to 85°C) – MIN(-40 to 85°C)) / MIN(-40 to 85°C) / (85°C – (–40°C))
Calculated using the box method: (MAX(2.0 to 3.6 V) – MIN(2.0 to 3.6 V)) / MIN(2.0 to 3.6 V) / (3.6 V – 2 V)
The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) until thefirst instruction of the user program is executed.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
16236
REV

C

DWG NO.
V62/14644
PAGE 19

TABLE I. Electrical performance characteristics - Continued.
46/
47/
48/
49/
50/
51/
52/
53/
54/
55/
56/
57/
58/
59/
60/
61/
62/
63/
64/
65/
66/
67/
68/
69/

����� signal until the first instruction of the user program is executed.
The wake-up time is measured from the rising edge of the RST
Meeting or exceeding this time makes sures a reset event occurs. Pulses shorter than this minimum time may or may not cause a
reset event to occur.
Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses
are correctly recognized, their duration should exceed the maximum specification of the deglitch time.
fUCxCLK = 1/2tLO/HI with tLO/HI = max(tVALID,MO(eUSCI) + tSU,SI(Slave), tSU,MI(eUSCI) + tVALID,SO(Slave)). For the slave's parameters tSU,SI(Slave) andtVALID,SO(Slave) see the SPI parameters of the attached slave.
Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing
diagramsin FIGURE 9 and FIGURE 10.
Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that thedata on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagramsin FIGURE 9 and FIGURE 10.
fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(eUSCI), tSU,MI(Master) + tVALID,SO(eUSCI)). For the master's parameters tSU,MI(Master)and tVALID,MO(Master) see the SPI parameters of the attached slave.
Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing
diagrams in FIGURE 11 and FIGURE 12.
Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in
FIGURE 11 and FIGURE 12.
12 × ADC10DIV × 1/fADC10CLK
Error is dominated by the internal reference.
The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance, Ci,
is also the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow
the recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy.
The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with
reduced accuracy requirements.
The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
Two decoupling capacitors, 10 μF and 100 nF, should be connected to VREF to decouple the dynamic current required for an
external reference source if it is used for the ADC10_B.
The internal reference current is supplied by terminal AVCC. Consumption is independent of the ADC10ON control bit, unless aconversion is active. The REFON bit enables to settle the built-in reference before starting an A/D conversion.
The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB.
The temperature sensor offset can vary significantly. A single-point calibration is recommended to minimize the offset error of thebuilt-in temperature sensor.
The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on).
The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.
When using manual wait state control, see manufacturer data for recommended settings for common system frequencies.
Tools accessing the Spy-Bi-Wire interface must wait for the tSBW,En time after pulling the TEST/SBWTCK pin high before applying
the first SBWTCK clock edge.
fTCK may be restricted to meet the timing requirements of the module selected.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
16236
REV

C

DWG NO.
V62/14644
PAGE 20

Case X

Dimensions
SymbolMillimeters
Min

Max

A

0.08

1.00

A1

0.00

A2
b

SymbolMillimeters
Min

Max

D/E

5.85

6.15

0.05

e

0.50 BSC

0.20 NOM

S

0.18

0.30

0.50

0.30

NOTES:
1. All linear dimensions are in millimeters.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the board for thermal and mechanical performance.
4. See the additional figure in the manufacturer data sheet for details regarding the exposed thermal pad features anddimensions.
5. Package complies to JEDEC MO-220 variation VJJD-2..
FIGURE 1. Case outline.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
16236
REV

C

DWG NO.
V62/14644
PAGE 21Case outline X
Terminal
Terminal symbol
Terminal
numbernumber1
P1.0/TA0.1/DMAE0/RTCCLK/A0*/CD0/VeREF40
2
P1.1/TA0.2/TA1CLK/CDOUT/A1*/CD1/VeREF+
39
3
P1.2/TA1.1/TA0CLK/CDOUT/A2*/CD238
4
P3.0/A12*/CD1237
5P3.1/A13*/CD1336
6
P3.2/A14*/CD1435
7P3.3/A15*/CD1534
8
P1.3/TA1.2/UCB0STE/A3*/CD3
33
9
P1.4/TB0.1/UCA0STE/A4*/CD4
32
10
P1.5/TB0.2/UCA0CLK/A5*/CD5
31
11
PJ.0/TDO/TB0OUTH/SMCLK/CD630
12PJ.1/TDI/TCLK/TB1OUTH/MCLK/CD7
29
13
PJ.2/TMS/TB2OUTH/ACLK/CD828
14
PJ.3/TCK/CD927
15
P4.0/TB2.0
26
16
P4.1
25
17
P2.5/TB0.0/UCA1TXD/UCA1SIMO
24
18
P2.6/TB1.0/UCA1RXD/UCA1SOMI
23
19
TEST/SBWTCK
22
�����
20
21
RST/NMI/SBWTDIONOTES:*
Not available on MSP430FR5739-EP
Exposed thermal pad connection to VSS recommended.

Terminal symbol
AVCC
AVSS
PJ.5/XOUT
PJ.4/XIN
AVSS
P2.4/TA1.0/UCA1CLK/A7*/CD11
P2.3/TA0.0/UCA1STE/A6*/CD10
P2.7
DVCC
DVSS
VCORE
P1.7/TB1.2/UCB0SOMI/UCB0SCL/TA1.0
P1.6/TB1.1/UCB0SIMO/UCB0SDA/TA0.0
P3.7/TB2.2
P3.6/TB2.1/TB1CLK
P3.5/TB1.2/CDOUT
P3.4/TB1.1/TB2CLK/SMCLK
P2.2/TB2.2/UCB0CLK/TB1.0
P2.1/TB2.1/UCA0RXD/UCA0SOMI/TB0.0
P2.0/TB2.0/UCA0TXD/UCA0SIMO/TB0CLK/ACLKFIGURE 2. Terminal connections.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
16236
REV

C

DWG NO.
V62/14644
PAGE 22

FIGURE 3. Functional block diagram.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
16236
REV

C

DWG NO.
V62/14644
PAGE 23

FIGURE 4. Typical Active mode supply currents, No Wait states.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
16236
REV

C

DWG NO.
V62/14644
PAGE 24

FIGURE 5. Typical Low-Level Output Current vs Low-Level Output Voltage, VCC = 2.0 V.

FIGURE 6. Typical Low-Level Output Current vs Low-Level Output Voltage VCC = 3.0 V.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
16236
REV

C

DWG NO.
V62/14644
PAGE 25

FIGURE 7. Typical High-Level Output Current vs High-Level Output Voltage, VCC = 2.0 V.

FIGURE 8. Typical High-Level Output Current vs High-Level Output Voltage, VCC = 3.0 V.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
16236
REV

C

DWG NO.
V62/14644
PAGE 26

FIGURE 9. SPI Master mode, CKPH = 0.

FIGURE 10. SPI Master mode, CKPH = 1.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
16236
REV

C

DWG NO.
V62/14644
PAGE 27

FIGURE 11. SPI Slave mode, CKPH = 0.

FIGURE 12. SPI Slave mode, CKPH = 1.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
16236
REV

C

DWG NO.
V62/14644
PAGE 28

FIGURE 13. I2C mode timing.

FIGURE 14. Typical temperature sensor voltage.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
16236
REV

C

DWG NO.
V62/14644
PAGE 29

4. VERIFICATION
4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as
indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices,classification, packaging, and labeling of moisture sensitive devices, as applicable.
5. PREPARATION FOR DELIVERY
5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial
practices for electrostatic discharge sensitive devices.
6. NOTES
6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum.
6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book.
The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided.
6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee
of present or continued availability as a source of supply for the item. DLA Land and Maritime maintains an online database of all
current sources of supply at https://landandmaritimeapps.dla.mil/programs/smcr/.

1/

Vendor item drawing
administrative control
number 1/

Devicemanufacturer
CAGE code

Vendor part number

V62/14644-01XE

01295

M430FR5739SRHATEP

The vendor item drawing establishes an administrative control number for
identifying the item on the engineering documentation.
CAGE code

Source of supply

01295

DLA LAND AND MARITIMECOLUMBUS, OHIO

Texas Instruments, Inc.
Semiconductor Group
8505 Forest Lane
P.O. Box 660199
Dallas, TX 75243

SIZE
A

CAGE CODE
16236
REV

C

DWG NO.
V62/14644
PAGE 30