REVISIONSLTR

DESCRIPTIONDATE (YR-MO-DA)APPROVEDA

Update boilerplate to current MIL-PRF-38535 requirements. - PHN

18-05-22

Thomas M. HessB

Update boilerplate paragraphs to current VID description requirements.
- PHN

23-10-18

Muhammad A. Akbar

Prepared in accordance with ASME Y14.24

Vendor Item Drawing

Revision Status of Sheets
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PMIC N/A
Original date of drawing
YY MM DD

DLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990

PREPARED BY
Phu H. Nguyen

TITLE

CHECKED BY
Phu H. Nguyen
APPROVED BY

12-12-10

https://www.dla.mil/landandmaritime
MICROCIRCUIT, DIGITAL, MIXED SIGNALMICROCONTROLLER, MONOLITHIC SILICON

Thomas M. HessSIZE

CAGE CODE

A

REV B

16236

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PAGE

V62/12623

1 OF 21

AMSC N/A
DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.

5962-V169-23

1. SCOPE
1.1 Scope. This drawing documents the general requirements of a high performance mixed signal microcontroller microcircuit, with
an operating temperature range of -40ºC to +85ºC.
1.2 Vendor Item Drawing Administrative Control Number. The manufacturer’s PIN is the item of identification. The vendor item
drawing establishes an administrative control number for identifying the item on the engineering documentation:
V62/12623-

Drawing
number01

X

E

Device type(see 1.2.1)

Case outline(see 1.2.2)

Lead finish(see 1.2.3)

1.2.1 Device type(s).
Device type

Generic

Circuit function

01

MSP430G2302-EP

Mixed signal microcontroller

1.2.2 Case outline(s). The case outlines are as specified herein.
Outline letter

Number of pins

JEDEC PUB 95

Package style

X

14

JEDEC MO-153

Plastic small outline

1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer:
Finish designator

Material

A
B
C
D
E
F
Z

DLA LAND AND MARITIMECOLUMBUS, OHIO

Hot solder dip
Tin-lead plate
Gold plate
PalladiumGold flash palladium
Tin-lead alloy
Other

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PAGE 2

1.3 Absolute maximum ratings.

1/

Voltage applied at VCC to VSS ............................................................................................... -0.3 V to 4.1 V
Voltage applied to any pin .................................................................................................... -0.3 V to VCC +0.3 V 2/
Diode current at any device terminal .................................................................................... ±2 mA
Storage temperature: 3/
Unprogrammed device .................................................................................................. -55°C to 150°C
Programmed device ...................................................................................................... -55°C to 150°C
1.4 Thermal characteristics.
Thermal information
Case outline X

Units

Junction to ambient thermal resistance, θJA 4/
Junction to case (top) thermal resistance, θJCtop 5/

98.7
26.8

°C/W
°C/W

Junction to board thermal resistance, θJB 6/
Junction to top characterization parameter, ΨJT 7/
Junction to board characterization parameter, ΨJB 8/

41.2
1.1
40.5

°C/W
°C/W

Junction to case (bottom) thermal resistance, θJCbot

N/A

9/

°C/W
°C/W

________________
1/

2/
3/
4/
5/
6/
7/
8/
9/

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stressratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended
operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device
reliability.
All voltage values referenced to VSS. The JTAG fuse blow voltage, VFB is allowed to exceed the absolute maximum rating. The
voltage is applied to the TEST pin when blowing the JTAG fuse..
Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak
reflow temperatures not higher than classified on the device label on the shipping boxes or reels.
The junction to ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-kboard, as specified in JESD51-7, in an environment described in JESD51-2a.
The junction to case (top) thermal resistance is obtanied by simulating a cold plate test on the package top. No specified JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction to board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the
PCB temperature, as described in JESD51-8.
The junction to top characterization parameter, ΨJT, estimates the junction teperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction to board characterization parameter, ΨJB, estimates the junction teperature of a device in a real system and is
extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction to case (bottom) thermal resistance is obtanied by simulating a cold plate test on the exposed (power) pad. No
specified JEDEC- standard test exists, but a close description can be found in the ANSI SEMI standard G30-88

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PAGE 3

1.5 Recommended operating conditions.
Supply voltage, (VCC):
During program execution ............................................................................................. 1.8 V to 3.6 V
During flash program/erase ........................................................................................... 2.2 V to 3.6 V
Supply voltage, (VSS) ............................................................................................................ 0 V
Operating free air temperature, (TA) ..................................................................................... -40°C to 85°C
Processor frequency (Maximum MCLK frequency) 10/ 11/
VCC = 1.8 V, Duty cycle = 50% ±10% ............................................................................ dc to 6 MHz
VCC = 2.7 V, Duty cycle = 50% ±10% ............................................................................ dc to 12 MHz
VCC = 3.3 V, Duty cycle = 50% ±10% ............................................................................ dc to 16 MHz
2. APPLICABLE DOCUMENTSJEDEC – SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC)JEP95
JESD51-2
JESD51-7
JESD51-8
J-STD-020

–
–
–
–
–

Registered and Standard Outlines for Semiconductor Devices
Integrated Circuits Thermal Test Method Environment Conditions – Natural Convection (Still Air)High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
Integrated Circuits Thermal Test Method Environment Conditions – Junction-to-board
Joint IPC/JEDEC standard for moisture/reflow sensitivity classification for nonhermetic solid state surface
mount devices.

(Copies of these documents are available online at https://www.jedec.org.)AMERICAN NATIONAL STANDARDS INSTITUTE (ANSI) STANDARD
ANSI SEMI STANDARD G30-88– Test Method for Junction-to-Case Thermal Resistance Measurements for Ceramic
Packages(Copies of these documents are available online at https://www.ansi.org.)
3. REQUIREMENTS
3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as
follows:
A.
B.
C.

Manufacturer’s name, CAGE code, or logo
Pin 1 identifier
ESDS identification (optional)

3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable)
above.
3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics areas specified in 1.3, 1.4, 1.5 and table I herein.
3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein.

______________
10/
11/

The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of thespecified maximum frequency.
Modules might have different maximum input clock specification. See the specification from the manufacturer data sheet.

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3.5 Diagrams.
3.5.1

Case outline. The case outline shall be as shown in 1.2.2 and figure 1.

3.5.2

Terminal connections. The terminal connections shall be as shown in figure 2.

3.5.3

Terminal function. The terminal function shall be as shown in figure 3.

3.5.4

Functional block diagram. The functional block diagram shall be as shown in figure 4.

3.5.5

Safe operating area. The safe operating area shall be as shown in figure 5.

3.5.6

POR/Brownout Reset (BOR) vs Supply voltage. The POR/Brownout Reset (BOR) vs Supply voltage shall be as shown infigure 6.

3.5.7

VCC(drop) level with a Square voltage drop to generate a POR/Brownout signal. The VCC(drop) level with a Square voltage drop
to generate a POR/Brownout signal shall be as shown in figure 7.

3.5.8

VCC(drop) level with a Triangle voltage drop to generate a POR/Brownout signal. The VCC(drop) level with a Triangle voltage
drop to generate a POR/Brownout signal shall be as shown in figure 8.

3.5.9

DCO wake-up time from LPM3/4 vs DCO frequency. The DCO wake-up time from LPM3/4 vs DCO frequency waveforms
shall be as shown in figure 9.

3.5.10

USI low level output voltage vs output current. The USI low level output voltage vs output current shall be as shown infigure 10.

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PAGE 5TABLE I. Electrical performance characteristics. 1/
Test

SymbolConditions

TA

2/ 3/ 4/
Active mode supply current into VCC excluding external current.
fDCO = fMCLK = fSMCLK = 1 MHz,fACLK = 32768 Hz,
IAM, 1MHz
Active mode (AM)Program executes in flash,

VCC

Lim itsMin

2.2 V

current (1 MHz)BCSCTL1 = CALBC1_1MHz,
DCOCTL = CALDCO_1MHz,CPUOFF = 0, SCG0 = 0
SCG1 = 0, OSCOOFF = 0
Low power mode Supply current (into VCC) Excluding external current
fMCLK = 0 MHz,fSMCLK = fCDO = 1 MHz,Low power mode 0
ILPM0, 1MHz fACLK = 32,768 Hz,(LPM0) current
BCSCTL1 = CALBC1_1MHz,
DCOCTL = CALDCO_1MHz,CPUOFF = 1, SCG0 = 0,
5/
SCG1 = 0, OSCOFF = 0
fMCLK = fSMCLK = 0 MHz,fCDO = 1 MHz,Low power mode 2
ILPM2
fACLK = 32,768 Hz,(LPM2) current
BCSCTL1 = CALBC1_1MHz,
DCOCTL = CALDCO_1MHz,CPUOFF = 1, SCG0 = 0,
6/
SCG1 = 1, OSCOFF = 0
fDCO = fMCLK = fSMCLK = 0 MHz,Low power mode 3
ILPM3, LFXT1 fACLK = 32768 Hz,(LPM3) current
6/
CPUOFF = 1, SCG0 = 1,
SCG1 = 1, OSCOFF = 0
fDCO = fMCLK = fSMCLK = 0 MHz,Low power mode 3
ILPM3, VLO fACLK = from internal LF oscillator (VLO),CPUOFF = 1, SCG0 = 1,
(LPM3) current 6/
SCG1 = 1, OSCOFF = 0
fDCO = fMCLK = fSMCLK = 0 MHz,Low power mode 4
ILPM4
fACLK = 0 Hz,(LPM4) current
CPUOFF = 1, SCG0 = 1,
7/
SCG1 = 1, OSCOFF = 1

Unit
Max

220 TYP

3V

400

µA

25°C

2.2 V

55 TYP

µA

25°C

2.2 V

22 TYP

µA

25°C

2.2 V

1.0

µA

25°C

2.2 V

0.7

µA

25°C

2.2 V

0.5

µA

1.5

µA

85°C

See footnote at end of table.

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TABLE I. Electrical performance characteristics - Continued. 1/
Test

SymbolSchmitt Trigger inputs (Port Px)

8/

Positive going input thresholdvoltage

VIT+

Negative going input threshold

VIT-

VCC

Conditions
2/ 3/ 4/3V

Lim its

Unit

Min

Max

0.45 VCC

0.75 VCC

V

1.35

2.25

V

0.25 VCC

0.55 VCC

V

3V

0.75

1.65

V

3V

0.3

1.0

V

For pullup: VIN = VSS
For pulldown: VIN = VCC
VIN = VSS or VCC

3V

20

50

kΩ

Ilkg(Px.y)

9/

3V

VOH

I(OHmax) = -6 mA 11/

3V

VCC - 0.3

V

VOL

I(OLmax) = 6 mA 11/

3V

VSS + 0.3

V

fPx.y

Px.y, CL = 20 pF, RL = 1 kΩ 12/ 13/3V

12 TYPMHz

Clock output frequency
fPort°CLK
Pin Oscillator frequency – Ports Px

Px.y, CL = 20 pF 13/

3V

16 TYPMHzPort output oscillation frequency

P1.y, CL = 10 pF, RL = 100 kΩ 14/ 15/

3V

1400 TYPkHz

900 TYP

kHz

1800 TYP

kHz

1000 TYPkHz

700 TYP

kHz

voltage
Input voltage hysteresis (VIT+ VIT-)

Vhys

Pullup/pulldown resistor

RPull

Input capacitance
Leakage current (Port Px)
High impedance leakage current
Outputs (Port Px)
High level output voltage

CI

Low level output voltage
Output frequency (Port Px)
Port output frequency (with load)

foP1.x

5 TYP

10/

±50

P1.y, CL = 20 pF, RL = 100 kΩ 14/ 15/
Port output oscillation frequency

foP2.xP2.0 to P2.5, CL = 10 pF, RL = 100 kΩ
14/ 15/
P2.0 to P2.5, CL = 20 pF, RL = 100 kΩ
14/ 15/
P2.6 and P2.7, CL = 20 pF, RL = 100 kΩ
14/ 15/

3V

pF

3V

nA

Port output oscillation frequency

foP2.6/7

POR/Brownout Reset (BOR)
See figure 10

16/
VCC(start)dVCC/dt ≤ 3 V/s

See figure 10 through figure 12

V(B_IT-)

dVCC/dt ≤ 3 V/s

1.40

TYP

V

See figure 10

Vhys(B_IT-)

dVCC/dt ≤ 3 V/s

140

TYP

mV

See figure 10td(BOR)�����/NMI
Pulse length needed at RST
pin to accept reset internallyt(reset)0.7 x V(B_IT-) TYP

2000
2.2 V

2

DLA LAND AND MARITIMECOLUMBUS, OHIOCAGE CODE
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µs
µs

See footnote at end of table.

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TABLE I. Electrical performance characteristics - Continued. 1/
Test

Symbol

VCC

Lim its

Unit

Min

Max

RSELx < 14

1.8

3.6

V

RSELx = 14

2.2

3.6

V

RSELx = 15

3.0

3.6

V

2/ 3/ 4/

Schmitt Trigger input
Supply voltage

VCC

Conditions

DCO frequency (0, 0)

fDCO(0,0)

RSELx = 0, DCOx = 0, MDDx = 0

3V

0.06

0.14

MHz

DCO frequency (0, 3)

fDCO(0,3)

RSELx = 0, DCOx = 3, MDDx = 0

3V

0.07

0.17

MHz

DCO frequency (1, 3)

fDCO(1,3)

RSELx = 1, DCOx = 3, MDDx = 03V0.15 TYPMHz

DCO frequency (2, 3)

fDCO(2,3)

RSELx = 2, DCOx = 3, MDDx = 03V0.21 TYPMHz

DCO frequency (3, 3)

fDCO(3,3)

RSELx = 3, DCOx = 3, MDDx = 03V0.30 TYPMHz

DCO frequency (4, 3)

fDCO(4,3)

RSELx = 4, DCOx = 3, MDDx = 03V0.41 TYPMHz

DCO frequency (5, 3)

fDCO(5,3)

RSELx = 5, DCOx = 3, MDDx = 03V0.58 TYPMHz

DCO frequency (6, 3)

fDCO(6,3)

RSELx = 6, DCOx = 3, MDDx = 0

3V

0.54

1.06

MHz

DCO frequency (7, 3)

fDCO(7,3)

RSELx = 7, DCOx = 3, MDDx = 0

3V

0.80

1.50

MHz

DCO frequency (8, 3)

fDCO(8,3)

RSELx = 8, DCOx = 3, MDDx = 0

3V

1.6 TYPMHz

DCO frequency (9, 3)

fDCO(9,3)

RSELx = 9, DCOx = 3, MDDx = 0

3V

2.3 TYPMHz

DCO frequency (10, 3)

fDCO(10,3)

RSELx = 10, DCOx = 3, MDDx = 0

3V

3.4 TYPMHz

DCO frequency (11, 3)

fDCO(11,3)

RSELx = 11, DCOx = 3, MDDx = 0

3V

4.25 TYPMHz

DCO frequency (12, 3)

fDCO(12,3)

RSELx = 12, DCOx = 3, MDDx = 0

3V

4.3

7.30

MHz

DCO frequency (13, 3)

fDCO(13,3)

RSELx = 13, DCOx = 3, MDDx = 0

3V

6.00

9.60

MHz

DCO frequency (14, 3)

fDCO(14,3)

RSELx = 14, DCOx = 3, MDDx = 0

3V

8.6

13.9

MHz

DCO frequency (15, 3)

fDCO(15,3)

RSELx = 15, DCOx = 3, MDDx = 0

3V

12.0

18.5

MHz

DCO frequency (15, 7)

fDCO(15,7)

RSELx = 15, DCOx = 7, MDDx = 0

3V

16.0

26.0

MHz

Frequency step between range
RSEL and RSEL + 1
Frequency step between tap
DCO and DCO + 1
Duty cycle

SRESL

SRSEL = fDCO(RSEL+1,DCO)/fDCO(RSEL,DCO)

3V

1.35 TYP

ratio

SDCO

SDCO = fDCO(RSEL,DCO+1)/fDCO(RSEL,DCO)

3V

1.08 TYP

ratio

Measured at SMCLK output

3V

50 TYP%See footnote at end of table.

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PAGE 8TABLE I. Electrical performance characteristics - Continued. 1/
Test

Conditions

VCC

TA

2/ 3/ 4/

Calibrated DCO frequencies – Tolerance
BCSCTL1 = CALBC1_1MHz,
1 MHz tolerance over
DCOCTL = CALDCO_1MHz,
temperature 17/
calibrated at 30°C and 3 V
BCSCTL1 = CALBC1_1MHz,
1 MHz tolerance over VCC
DCOCTL = CALDCO_1MHz,
calibrated at 30°C and 3 V
BCSCTL1 = CALBC1_1MHz,
1 MHz tolerance overall
DCOCTL = CALDCO_1MHz,
calibrated at 30°C and 3 V
BCSCTL1 = CALBC1_8MHz,
8 MHz tolerance over
DCOCTL = CALDCO_8MHz,
temperature 17/
calibrated at 30°C and 3 V
BCSCTL1 = CALBC1_8MHz,
8 MHz tolerance over VCC
DCOCTL = CALDCO_8MHz,
calibrated at 30°C and 3 V
BCSCTL1 = CALBC1_8MHz,
8 MHz tolerance overall
DCOCTL = CALDCO_8MHz,
calibrated at 30°C and 3 V
BCSCTL1 = CALBC1_12MHz,
12 MHz tolerance over
DCOCTL = CALDCO_12MHz,
temperature 17/
calibrated at 30°C and 3 V
BCSCTL1 = CALBC1_12MHz,
12 MHz tolerance over VCC
DCOCTL = CALDCO_12MHz,
calibrated at 30°C and 3 V
BCSCTL1 = CALBC1_12MHz,
12 MHz tolerance overall
DCOCTL = CALDCO_12MHz,
calibrated at 30°C and 3 V
BCSCTL1 = CALBC1_16MHz,
16 MHz tolerance over
DCOCTL = CALDCO_16MHz,
temperature 17/
calibrated at 30°C and 3 V
BCSCTL1 = CALBC1_16MHz,
16 MHz tolerance over VCC
DCOCTL = CALDCO_16MHz,
calibrated at 30°C and 3 V
BCSCTL1 = CALBC1_16MHz,
16 MHz tolerance overall
DCOCTL = CALDCO_16MHz,
calibrated at 30°C and 3 V

Lim its

Unit

Min

Max

0°C to 85°C

3V

-3

3

%

30°C

1.8 V to 3.6 V

-3

3

%

-40°C to 85°C

1.8 V to 3.6 V

-6

6

%

0°C to 85°C

3V

-3

3

%

30°C

2.2 V to 3.6 V

-3

3

%

-40°C to 85°C

2.2 V to 3.6 V

-6

6

%

0°C to 85°C

3V

-3

3

%

30°C

2.7 V to 3.6 V

-3

3

%

-40°C to 85°C

2.7 V to 3.6 V

-6

6

%

0°C to 85°C

3.3 V

-3

3

%

30°C

3.3 V to 3.6 V

-3

3

%

-40°C to 85°C

3.3 V to 3.6 V

-6

6

%

See footnote at end of table.

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PAGE 9TABLE I. Electrical performance characteristics - Continued. 1/
Test

SymbolWake up from Lower Power Models (LPM3/4)
DCO clock wake up time from LPM3/4
tDCO,LPM3/4
18/
CPU wake up time from LPM3/4 19/
tCPU,LPM3/4

VCC

Conditions
2/ 3/ 4/BCSCTL1 = CALBC1_1MHz,
DCOCTL = CALDCO_1MHz,

3V

Crystal oscillator, XT1, low frequency mode
20/
LFXT1 oscillator crystal frequency,
fLFXT1,LF
XTS = 0, LFXT1Sx = 0 or 1
LF mode 0, 1
LFXT1 oscillator logic level square
fLFXT1,LF,logic XTS = 0, XCAPx = 0, LFXT1Sx = 3
wave input frequency, LF mode
Oscillation allowance for LF crystals
OALF
XTS = 0, LFXT1Sx = 0,
fLFXT1,LF = 32768 Hz, CL,eff = 6 pF
XTS = 0, LFXT1Sx = 0,
fLFXT1,LF = 32768 Hz, CL,eff = 12 pF
Integrated effective load capacitance,
CL,eff
XTS = 0, XCAPx = 0
LF mode 21/

Lim its

Unit
Max

Min

1.5 TYPµs

1 / fMCLK +tClock,LPM3/4 TYP
1.8 V to
3.6 V

32768

TYP

Hz

1.8 V to
3.6 V

10000

50000

Hz

500 TYPkΩ

200 TYP

kΩ

1 TYP

pF

XTS = 0, XCAPx = 1

5.5 TYPpF

XTS = 0, XCAPx = 2

8.5 TYPpF

XTS = 0, XCAPx = 3

11 TYPpF

Duty cycle, LF mode

XTS = 0, Measured at P2.0/ACLK,fLFXT1,LF = 32768 Hz
Oscillator fault frequency, LF mode
fFault,LF
XTS = 0, XCAPx = 0, LFXT1Sx = 3
22/23/Internal Very Low power Low frequency Oscillator (VLO)
VLO frequency
fVLO-40°C ≤ TA ≤ 85°C
VLO frequency temperature drift 30/
dfVLO/dT-40°C ≤ TA ≤ 85°C

2.2 V

30

70

%

2.2 V

10

10000

Hz

3V

4

20

kHz

3V

0.5 TYPVLO frequency supply voltage drift

1.8 V to
3.6 V

4 TYP

%/°C
%/V

f SYSTEM

MHz

dfVLO/dVCC

TA = 25°C

Timer_A
Timer_A input clock frequency

fTA

Timer_A capture timing
USI, Universal Serial Interface
USI clock frequency

fTA,cap

Serial clock frequency, slave modeLow level output voltage on SDA andSCL

SMCLK,
Duty cycle = 50% ±10%TA0, TA1

3V

f(SCLK)

External: SCLK,
Duty cycle = 50% ±10%
SPI slve mode

3V

VOL,I2C

USI module in I2C mode,

3V

fUSI

I(OLmax) = 1.5 mA

20

VSS

ns
f SYSTEM

MHz

6

MHz

VSS +
0.4

V

See footnote at end of table.

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PAGE 10

TABLE I. Electrical performance characteristics - Continued. 1/
Test

SymbolFlash memory
Program and erase supply voltage

VCC

Conditions
2/ 3/ 4/VCC(PGM/ERASE)

Lim its

Unit

Min

Max

2.2

3.6

V

257

476

kHz

5

mA

Flash timing generator frequency

fFTG

Supply current from VCC during program

IPGM

2.2 V/3.6 V

Supply current from VCC during erase

IERASE

2.2 V/3.6 V

7mA

Cumulative program timetCPT

2.2 V/3.6 V

10ms

tCMErase

2.2 V/3.6 V

24/

Cumulative mass erase time
Program/erase endurance

20

ms

104

cycles100

years

Data retention durationtRetention

Word or byte program timetWord

TJ = 25°C
25/Block program time for first byte or word

tBlock, 0

25/

25 TYPtFTG

Block program time for each additional byte or
word
Block program end sequence wait time

tBlock, 1-63

25/

18 TYP

tFTG

tBlock, End

25/

6 TYP

tFTG

Mass erase time

tMass Erase25/

10593 TYP

tFTG

Segment erase time

tSeg Erase25/

4819 TYP

tFTG

RAM
RAM retention supply voltage 26/

V(RAMh)CPU halted

1.6

V

30 TYPtFTG

JTAG and Spy-Bi-Wire Interface
Spy-Bi-Wire input frequency

fSBW

2.2 V

0

20

MHz

Spy-Bi-Wire low clock pulse lengthtSBW,Low

2.2 V

0.025

15

µs

Spy-Bi-Wire enable time
(Test high to acceptance of first clock edge
27/)
Spy-Bi-Wire return to normal operation time

tSBW,En

2.2 V

1

µs

tSBW,Ret

2.2 V

15

100

µs

TCK input frequency 28/
Internal pulldown resistance on TESTfTCK
RInternal

2.2 V
2.2 V

0
25

5
90

MHz
kΩ

JTAG fuse 29/
Supply voltage during fuse blow condition

VCC(FB)

2.5

TA = 25°C

6V

Voltage level on TEST for fuse blow

VFB

7

V

Supply current into TEST during fuse blow

IFB

100

mA

Time to blow fuse

tFB

1

ms

See footnote at end of table.

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PAGE 11TABLE I. Electrical performance characteristics - Continued. 1/
1/

2/
3/
4/
5/
6/
7/
8/
9/
10/
11/
12/
13/
14/
15/
16/
17/
18/
19/
20/

21/
22/
23/
24/
25/
26/
27/
28/
29/
30/

Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the
specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may
not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization
and/or design.
Over recommended operating free air temperature range (unless otherwise noted).
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal andexternal load capacitance is chosen closely match the required 9 pF.
Current for brownout and WDT clocked by SMCLK included.
Current for brownout and WDT clocked by ACLK included.
Current for brownout included.
An external signal sets interrupt flag every time the minimum interrupt pulse width t(int) is met. It may be set even with trigger
signals shorter than t(int).
The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor isdisabled.
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage
drop specified.
A resistive divider with 2 x 0.5 kΩ resistors between VCC and VSS is used as load. The output is connected to the center tap of thedivider.
The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
A resistive divider with two 100 kΩ resistors between VCC and VSS is used as load. The output is connected to the center tap of
the divider.
The output voltage oscillator with a typical amplitude of 700 mV at the specified toggle frequency.
The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level
V(B_IT-) + Vhys(B_IT-) is ≤ 1.8 V.
This is the frequency change from the measured frequency at 30°C over temperature.
The DCO clock wake up time is measured from the edge of an external wake up signal (for example, port interrupt) to the firstclock edge observable externally on a clock pin (MCLK or SMCLK).
Parameter applicable only if DCOCLK is used for MCLK.
To improve EMI on the XT1 oscillator, the following guide lines should be observed.
a)
Keep the trace between the device and the crystal as short as possible.
b)
Design a good ground plane around the oscillator pins.
c)
Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
d)
Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
e)
Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
f)
If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
g)
Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in otherdocumentation. This signal is no longer required for the serial programming adapter.
Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Since the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For acorrect set up, the effective load capacitance should always match the specification of the used crystal.
Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies in between might set the flag.
Measured with logic level input frequency but also applies to operation with crystals.
The cumulative program time must not be exceeded when writing to a 64 byte flash block. This parameter applies to all
programming methods: individual word/byte write and block write modes.
These values are hardwired into the Flash controller’state machine (tFTG = 1/fFTG).
This parameter defines the minimum supply voltage VCC when the data in RAM remains unchanged. No program execution
should happen during this supply voltage condition.
Tools accessing the Spy-Bi-Wire interface need to wait for the maximum tSBW,En time after pulling the TEST/SBWCLK pin highbefore applying the first SBWCLK clock edge.
fTCK may be restricted to meet the timing requirements of the module selected.
Once the fuse is blown, no further access to the JATG/Test, Spy-Bi-Wire, and emulation feature is possible, and JTAG is switched
to bypass mode.
Ensured by design on specified temperature.

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PAGE 12Case Xbe

140.10(.004)

M

8

c
0°-8°

E E1

1

GAGE
PLANE

7

0.25(.010)

L

DETAIL A
D
SEE
DETAIL A
A1

A

SEATING
PLANE

SymbolAA1bcD

0.10(.004)

Dimen sions
Millim eters
Symbol
Min
Max
1.20
0.05
0.15
0.19
0.30
0.15 NOM
4.90
5.10

E
E1
e
L

Millim eters
Min
Max
4.30
6.20
0.65
0.50

4.50
6.60
BSC
0.70

NOTES:
1. All linear dimensions are in millimeters (inches).
2. This drawing is subject to change without notice.
3. Body length does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006
0.15 each side.
4. Body width does not include interlead flash. Interlead flash shall not exceed 0.25 each side.
5. Fall within JEDEC MO-153
FIGURE 1. Case outline.

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PAGE 13Case Outline X
Terminal
numberTerminal symbol

Terminal
numberTerminal symbol

1
2
3
4
5
6
7

DVCC
P1.0/TA0CLK/ACLK/A0
P1.1/TA0.0/A1
P1.2/TA0.1/A2
P1.3/ADC10CLK/A3/VREF-/VEREFP1.4/TA0.2/SMCLK/A4/VREF+/VEREF+/TCK
P1.5/TA0.0/SCLK/A5/TMS

8
9
10
11
12
13
14

P1.6/TA0.1/SDO/SCL/A6/TDI/TCLK
P1.7/SDI/SDA/A7/TDO/TDI�����/NMI/SBWTDIORSTTEST/SBWTCKXOUT/P2.7
XIN/P2.6/TA0.1
DVSS

NOTES:
1. The pulldown resistors of port pins P2.0, P2.1, P2.2, P2.3, P2.4, and P2.5 should be enabled by setting
P2REN.x = 1..

FIGURE 2. Terminal connections.

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PAGE 14Case outline X
Termi nal
Name
NumberP1.0/
2
TA0CLK/
ACLK
A0
P1.1/
3
TA0.0/
A1
P1.2/
4
TA0.1/A2
P1.3/
5
ADC10CLK/
A3/
VREF-/VEREFP1.4/
6
TA0.2/SMCLK/A4/
VREF+/VEREF+/
TCK
P1.5/
7
TA0.0/
A5/
SCLK/
TMS
P1.6/
8
TA0.1/
A6/
SDO/
SCL/
TDI/TCLK
P1.7/
9
A7/
SDI/
SDA/
TDO/TDI 2/
XIN/
13
P2.6/
TA0.1
XOUT/
12
P2.7

I/O
I/O

I/O
I/O
I/O

I/O

I/O

I/O

I/O

I/O

I/O

Description
General purpose digital I/O pin
Timer0_A, clock signal TACLK input
ACLK signal output
ADC10 analog input A0 1/
General purpose digital I/O pin
Timer0_A, capture:CCI0A input, compare: Out0 output
ADC10 analog input A1 1/
General purpose digital I/O pin
Timer0_A, capture:CCI1A input, compare: Out1 output
ADC10 analog input A2 1/
General purpose digital I/O pin
ADC10, conversion clock output 1/
ADC10 analog input A3
1/
ADC10 negative reference voltage
1/
General purpose digital I/O pin
Timer0_A, capture:CCI2A input, compare: Out2 output
SMCLK signal output
ADC10 analog input A41/
ADC10 positive reference voltage 1/
JTAG test clock, input terminal for device programming and test
General purpose digital I/O pin
Timer0_A, compare: Out0 output
ADC10 analog input A5
USI: clock input in I2C mode; clock input/output in SPI mode
JTAG test data input or test clock input during programming and test
General purpose digital I/O pin
Timer0_A, capture: CCI1A input, compare Out1 output
ADC10 analog input A6
USI: Data output in SPI mode
USI: I2C clock in I2C mode
JTAG test data input or test clock input during programming and test
General purpose digital I/O pin
ADC10 analog input A7 1/
USI: Data output in SPI mode
USI: Data i2c in I2C mode
JTAG test data output terminal or test data input during programming and test
Input terminal of crystal oscillator 3/
General purpose digital I/O pin
Timer0_A, compare: Out1 output
Output terminal of crystal oscillator 3/
General purpose digital I/O pin

See footnote at end of table
FIGURE 3. Terminal function.

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PAGE 15

Case outline x (continued)
Termi nal
Name
Number
�����
10
RST/
NMI/
SBWTDIOTEST/11
SBWTCK
DVCC
AVCC
DVSS
AVSS
NC
QFN Pad

1
NA
14
NA
-

I/O
I

I

NA
NA
NA
NA
NA
NA

Description
Reset
Nonmaskable interrupt input
Spy-Bi-Wire test data input/output during programming and test
Select test mode for JTAG pins on Port 1. The device protection fuse isconnected to TEST.
Spy-Bi-Wire test clock input during programming and test.
Supply voltage
Supply voltage
Ground reference
Ground reference
Not connected
QFN package pad connection to VSS recommended.

NOTES:
1. Available only on device type 02.
2. TDO or TDI is selected via JTAG instruction.
3. If XOUT/P2.7 is used as an input, excess current flows until P2SEL.7 is cleared. This is due to the oscillator output driverconnection to this pad after reset.

FIGURE 3. Terminal function - Continued.

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PAGE 16

Device type 01

DVCC
XIN

P2.x

P1.x

DVSS

XOUT
UP TO 8

8

FLASH

RAM

8 kB

256 B

4 kB

256 B

2 kB

256 B

1 kB

128 B

PORT P1

PORT P2ACLK
CLOCK
SYSTEM
SMCLK

8 I/O

UP TO 8 I/O

INTERRUPTINTERRUPTCAPABILITYCAPABILITY

PULL-UP/DOWN

PULL-UP/DOWNRESISTORSRESISTORSTIMER0_A3

USI

3 CC

UNIVERSAL

MCLK

16 MHzMABCPU

INCL 16REGISTERSMDBEMULATION
2BP

WATCHDOGWDT+JTAGINTERFACEBROWNOUTPROTECTION

15-BITREGISTERSSERIAL
INTERFACE
SPI,I2C

SPY-BI WIRE

RST/NMINOTE:
1. Port P2: two pins are available on the 14 pin package option. Eight pins are available on the 20 pin package option.
FIGURE 4. Functional block diagram.

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PAGE 17

LEGEND:SYSTEM FREQUENCY-MHz

16 MHz

SUPPLY VOLTAGE RANGE,DURING FLASH MEMORYPROGRAMMING

12 MHz

SUPPLY VOLTAGE RANGE,DURING PROGRAM EXECUTION

6 MHz

1.8 V

2.2 V

2.7 V

3.3 V

3.6 V

SUPPLY VOLTAGE-V

NOTE:
1. Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC of 2.2 V.
FIGURE 5. Safe operating area.

VCC
Vhys(B_IT-)

V(B_IT-)
VCC(START)

10td(BOR)

FIGURE 6. POR/Brownout Reset (BOR) vs Supply voltage.

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PAGE 18

V
2

t

CC

PW

3V
V

CC

=3 V

TYPICAL CONDITIONS

-V

1.5

V CC(drop)

1V

CC(drop)

.5

0
.001

1

1000
1 ns

tpw -PULSE WIDTH-

1 nss
tpw -PULSE WIDTH-s

FIGURE 7. VCC(drop) level with a Square voltage drop to generate a POR/Brownout signal.

V
2

t

CC

PW

3V
V

CC

=3 V

TYPICAL CONDITIONSV CC(drop)

-V

1.5

1
V

CC(drop)

.5

t
f

=t
r

0
.001

1
tpw -PULSE WIDTH-

1000

t
f

t
r

s
s

tpw -PULSE WIDTH-

FIGURE 8. VCC(drop) level with a Triangle voltage drop to generate a POR/Brownout signal.

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PAGE 19

DCO WAKE TIME-us

10.00

RSELx=0...11

1.00

.10
.10

RSELx=12...15

1.00

10.00

DCO FREQUENCY-MHz

FIGURE 9. DCO wake-up time from LPM3/4 vs DCO frequency.

5.0

5.0
VCC =3 V

TA =25° C

4.0

3.0
TA =85° C
2.0

1.0

0.0
0.0

0.2

0.4

0.6

0.8

TA =25° C

4.0

I OL -LOW-LEVEL OUTPUT VOLTAGE-mA

I OL -LOW-LEVEL OUTPUT VOLTAGE-mA

VCC =2.2 V

3.0

TA =85° C

2.0

1.0

0.0
0.0

1.0

0.2

0.4

0.6

0.8

V -LOW-LEVEL OUTPUT VOLTAGE-V
OL

V -LOW-LEVEL OUTPUT VOLTAGE-V
OL

FIGURE 10. USI low level output voltage vs output current.

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PAGE 20

1.0

4. VERIFICATION
4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as
indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices,classification, packaging, and labeling of moisture sensitive devices, as applicable.
5. PREPARATION FOR DELIVERY
5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial
practices for electrostatic discharge sensitive devices.
6. NOTES
6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum.
6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book.
The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided.
6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee
of present or continued availability as a source of supply for the item. DLA Land and Maritime maintains an online database of all
current sources of supply at https://landandmaritimeapps.dla.mil/programs/smcr/.

Vendor item drawing
administrative control
number 1/

Devicemanufacturer

V62/12623-01XE

01295

1/

Top sidemarking

Transport
media

Vendor part number

Tape and real

MSP430G2302IPW1REPTube

MSP430G2302IPW1EP

CAGE code
G2302EP

The vendor item drawing establishes an administrative control number for identifying the item on
the engineering documentation.
CAGE code

Source of supply

01295

DLA LAND AND MARITIMECOLUMBUS, OHIO

Texas Instruments, Inc.
Semiconductor Group
8505 Forest Lane
P.O. Box 660199
Dallas, TX 75243

SIZE
A

CAGE CODE
16236
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PAGE 21