Low Noise, 90 MHz
Variable Gain Amplifier
AD603

Data Sheet

The decibel gain is linear in dB, accurately calibrated, and stable
over temperature and supply. The gain is controlled at a highimpedance (50 MΩ), low bias (200 nA) differential input; thescaling is 25 mV/dB, requiring a gain control voltage of only
1 V to span the central 40 dB of the gain range. An overrange
and underrange of 1 dB is provided whatever the selected range.
The gain control response time is less than 1 μs for a 40 dB change.

FEATURES
Linear-in-dB gain control
Pin-programmable gain ranges−11 dB to +31 dB with 90 MHz bandwidth
9 dB to 51 dB with 9 MHz bandwidth
Any intermediate range, for example −1 dB to +41 dB
with 30 MHz bandwidth
Bandwidth independent of variable gain
1.3 nV/√Hz input noise spectral density±0.5 dB typical gain accuracy

The differential gain control interface allows the use of either
differential or single-ended positive or negative control voltages.
Several of these amplifiers may be cascaded and their gain
control gains offset to optimize the system SNR.
The AD603 can drive a load impedance as low as 100 Ω withlow distortion. For a 500 Ω load in shunt with 5 pF, the total
harmonic distortion for a ±1 V sinusoidal output at 10 MHz is
typically −60 dBc. The peak specified output is ±2.5 V minimum
into a 500 Ω load.

APPLICATIONSRF/IF AGC amplifiersVideo gain controls
A/D range extensions
Signal measurements

The AD603 uses a patented proprietary circuit topology—the
X-AMP®. The X-AMP comprises a variable attenuator of 0 dB
to −42.14 dB followed by a fixed-gain amplifier. Because of theattenuator, the amplifier never has to cope with large inputs andcan use negative feedback to define its (fixed) gain and dynamic
performance. The attenuator has an input resistance of 100 Ω,
laser trimmed to ±3%, and comprises a 7-stage R-2R laddernetwork, resulting in an attenuation between tap points of
6.021 dB. A proprietary interpolation technique provides acontinuous gain control function that is linear in dB.

GENERAL DESCRIPTION
The AD603 is a low noise, voltage-controlled amplifier for use
in RF and IF AGC systems. It provides accurate, pin-selectable
gains of −11 dB to +31 dB with a bandwidth of 90 MHz or +9 dB to
51+ dB with a bandwidth of 9 MHz. Any intermediate gain
range may be arranged using one external resistor. The input
referred noise spectral density is only 1.3 nV/√Hz, and power
consumption is 125 mW at the recommended ±5 V supplies.

The AD603 is specified for operation from −40°C to +85°C.

FUNCTIONAL BLOCK DIAGRAMSCALINGREFERENCEPRECISION PASSIVEINPUT ATTENUATORFIXED-GAIN
AMPLIFIER

GPOS

VOUT

VG

GNEG

6.44kΩ*

AD603

GAINCONTROLINTERFACE

FDBK
694Ω*

0dB
VINP

–6.02dB
R

2R–12.04dB –18.06dB –24.08dB
R

2R

R

2R

R

2R

–30.1dB
R

2R–36.12dB –42.14dB
R

2R

R

R

20Ω*

00539-001

COMM
R-2R LADDER NETWORK*NOMINAL VALUES.

Figure 1.

Rev. K
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or otherrights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113©1993–2012 Analog Devices, Inc. All rights reserved.

AD603

Data SheetTABLE OF CONTENTS
Features .............................................................................................. 1

The Gain Control Interface ....................................................... 13

Applications ....................................................................................... 1
General Description ......................................................................... 1

Programming the Fixed-Gain Amplifier Using Pin
Strapping...................................................................................... 13

Functional Block Diagram .............................................................. 1

Using the AD603 in Cascade ........................................................ 15

Revision History ............................................................................... 2

Sequential Mode (Optimal SNR) ............................................. 15

Specifications..................................................................................... 3

Parallel Mode (Simplest Gain Control Interface) .................. 16

Absolute Maximum Ratings............................................................ 4

Low Gain Ripple Mode (Minimum Gain Error) ................... 17

ESD Caution .................................................................................. 4

Applications Information .............................................................. 18

Pin Configurations and Function Descriptions ........................... 5

A Low Noise AGC Amplifier .................................................... 18

Typical Performance Characteristics ............................................. 6

Caution ........................................................................................ 19

Test Circuits ..................................................................................... 11

Evaluation Board ............................................................................ 20

Theory of Operation ...................................................................... 12

Outline Dimensions ....................................................................... 22

Noise Performance ..................................................................... 12

Ordering Guide .......................................................................... 23

REVISION HISTORY
4/12—Rev. J to Rev. K
Changes to Table 1 ............................................................................ 3
Added Figure 10 and Figure 11; Renumbered Sequentially ....... 7
Added Test Circuits Section .......................................................... 11
Moved Figure 29 and Figure 30 .................................................... 11
12/11—Rev. I to Rev. J
Changes to Figure 1 ......................................................................... 1
Changes to Evaluation Board Section .......................................... 19
Changes to Figure 48 Through Figure 50 .................................... 19
Changes to Figure 51 Through Figure 54 .................................... 20
Added Figure 57.............................................................................. 22
5/07—Rev. G to Rev. H
Changes to Layout .......................................................................... 14
Changes to Layout .......................................................................... 15
Changes to Layout .......................................................................... 16
Inserted Evaluation Board Section, and Figure 48 to
Figure 51 .......................................................................................... 19
Inserted Figure 52 and Table 4 ...................................................... 20
Changes to Ordering Guide .......................................................... 21

3/05—Rev. F to Rev. G
Updated Format .................................................................. Universal
Change to Features ............................................................................1
Changes to General Description .....................................................1
Change to Figure 1 ............................................................................1
Changes to Specifications .................................................................3
New Figure 4 and Renumbering Subsequent Figures ..................6
Change to Figure 10 ..........................................................................7
Change to Figure 23 ..........................................................................9
Change to Figure 29 ....................................................................... 12
Updated Outline Dimensions ....................................................... 20
4/04—Rev. E to Rev. F
Changes to Specifications .................................................................2
Changes to Ordering Guide .............................................................3
8/03—Rev. D to Rev E
Updated Format .................................................................. Universal
Changes to Specifications .................................................................2
Changes to TPCs 2, 3, 4 ....................................................................4
Changes to Sequential Mode (Optimal S/N Ratio) section .........9
Change to Figure 8 ......................................................................... 10
Updated Outline Dimensions ....................................................... 14

Rev. K | Page 2 of 24

Data Sheet

AD603

SPECIFICATIONS@ TA = 25°C, VS = ±5 V, –500 mV ≤ VG ≤ +500 mV, GNEG = 0 V, –10 dB to +30 dB gain range, RL = 500 Ω, and CL = 5 pF, unlessotherwise noted.
Table 1.
Parameter
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Noise Spectral Density 1
Noise Figure
1 dB Compression Point
Peak Input Voltage
OUTPUT CHARACTERISTICS−3 dB Bandwidth
Slew Rate
Peak Output 2
Output Impedance
Output Short-Circuit Current
Group Delay Change vs. Gain
Group Delay Change vs. Frequency
Differential Gain
Differential Phase
Total Harmonic Distortion
Third-Order Intercept
ACCURACY
Gain Accuracy, f = 100 kHz; Gain (dB) = (40 VG + 10) dB
TMIN to TMAX
Gain, f = 10.7 MHz
Output Offset Voltage 3
TMIN to TMAX
Output Offset Variation vs. VG
TMIN to TMAXGAIN CONTROL INTERFACE
Gain Scaling Factor
TMIN to TMAX
GNEG, GPOS Voltage Range 4
Input Bias Current
Input Offset Current
Differential Input Resistance
Response Rate
POWER SUPPLYSpecified Operating Range
Quiescent Current
TMIN to TMAX

Conditions

Min

Typ

Max

Unit

Pin 3 to Pin 4

97

100
2
1.3
8.8
−11
±1.4

103

Ω
pF
nV/√HzdB
dBm
V

Input short-circuitedf = 10 MHz, gain = maximum, RS = 10 Ω
f = 10 MHz, gain = maximum, RS = 10 Ω
VOUT = 100 mV rms
RL ≥ 500 Ω
RL ≥ 500 Ωf ≤ 10 MHz±2.5

f = 3 MHz; full gain range
VG = 0 V; f = 1 MHz to 10 MHz
f = 10 MHz, VOUT = 1 V rms
f = 40 MHz, gain = maximum, RS = 50 Ω−500 mV ≤ VG ≤ +500 mV
VG = -0.5 V
VG = 0.0 V
VG = 0.5 V
VG = 0 V

90
275
±3.0
2
50
±2
±2
0.2
0.2
−60
15

−1
−1.5
−10.3
+9.5
+29.3

±0.5

39.4
38
38.7
−1.2
50

40

−9.0
+10.5
+30.3

−500 mV ≤ VG ≤ +500 mV
100 kHz10.7 MHzPin 1 to Pin 2
Full 40 dB gain change

39.3
100
10
50
80

±4.75
12.5

1

±2

MHz
V/µs
V
Ω
mA
ns
ns
%
Degree
dBc
dBm
+1
+1.5
−8.0
+11.5
+31.3
20
30
20
30

dB
dB
dB
dB
dB
mV
mV
mV
mV

40.6
42
39.9
+2.0
250

dB/V
dB/V
dB/V
V
nA
nA
MΩ
dB/µs

±6.3
17
20

V
mA
mA

Typical open or short-circuited input; noise is lower when system is set to maximum gain and input is short-circuited. This figure includes the effects of both voltage
and current noise sources.
Using resistive loads of 500 Ω or greater or with the addition of a 1 kΩ pull-down resistor when driving lower loads.
3
The dc gain of the main amplifier in the AD603 is ×35.7; therefore, an input offset of 100 µV becomes a 3.57 mV output offset.
4
GNEG and GPOS, gain control, and voltage range are guaranteed to be within the range of −VS + 4.2 V to +VS − 3.4 V over the full temperature range of −40°C to +85°C.
2

Rev. K | Page 3 of 24

AD603

Data Sheet

ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Supply Voltage ±VS
Internal Voltage VINP (Pin 3)
GPOS, GNEG (Pin 1 and Pin2)
Internal Power Dissipation
Operating Temperature Range
AD603A
AD603S
Storage Temperature Range
Lead Temperature (Soldering, 60 sec)

Rating±7.5 V±2 V Continuous±VS for 10 ms±VS
400 mW

Table 3. Thermal Characteristics
Package Type
8-Lead SOIC
8-Lead CERDIPESD CAUTION−40°C to +85°C−55°C to +125°C−65°C to +150°C
300°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stressrating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affectdevice reliability.

Rev. K | Page 4 of 24

θJA
155
140

θJC
33
15

Unit
°C/W
°C/W

Data Sheet

AD603

AD603

8

VPOS

GPOS 17

VOUT

GNEG 2

6 VNEGVINP 3
TOP VIEWCOMM 4 (Not to Scale) 5 FDBKVINP 300539-002

GPOS 1
GNEG 2

COMM 4

Figure 2. 8-Lead SOIC Pin Configuration

Mnemonic
GPOS
GNEG
VINP
COMM
FDBK
VNEG
VOUT
VPOS

8

VPOS

7

VOUT

TOP VIEW
6 VNEG(Not to Scale)
5 FDBK

Figure 3. 8-Lead CERDIP Pin Configuration

Table 4. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8

AD603

00539-003

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

Description
Gain Control Input High (Positive Voltage Increases Gain).
Gain Control Input Low (Negative Voltage Increases Gain).
Amplifier Input.
Amplifier Ground.
Connection to Feedback Network.
Negative Supply Input.
Amplifier Output.
Positive Supply Input.

Rev. K | Page 5 of 24

AD603

Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS@ TA = 25°C, VS = ±5 V, –500 mV ≤ VG ≤ +500 mV, GNEG = 0 V, –10 dB to +30 dB gain range, RL = 500 Ω, and CL = 5 pF, unlessotherwise noted.
225

3

180

2

135

1
0

GAIN (dB)20

GAIN (dB)90
GAIN

10.7MHz10
100kHz

0

–0.4

–0.2

0
VG (V)

0.2

0.4

0.6

45

–1

0
PHASE

–2

–45

–3

–90

–4

–135

–5

–180
–225

–6
100k

00539-004

–10
–0.6

PHASE (Degrees)

30

4Figure 4. Gain vs. VG at 100 kHz and 10.7 MHz

1M

10M
FREQUENCY (Hz)00539-007

40

100M

Figure 7. Frequency and Phase Response vs. Gain
(Gain = 10 dB, PIN = −30 dBm)

2.5

4

225

2.0

3

180

2

135

45MHz

1.5
90

0
10.7MHz0.5
0455kHzPHASE (Degrees)

GAIN

70MHz

GAIN (dB)

GAIN ERROR (dB)

1
1.0

45

–1

0
PHASE

–2

–45

–3

–90

–4

–135

–5

–180

70MHz
–1.0

–0.3

–0.2

–0.1
0
0.1
0.2
GAIN VOLTAGE (V)

0.3

0.4

0.5

4

225

3

180

2

135

–3

–90

–4

–135

–5

–180
–225
1M

10M
FREQUENCY (Hz)100M

GROUP DELAY (ns)–45

PHASE (Degrees)

0
PHASE

–2

–6
100k

100M

7.4

7.2

7.0

6.8

6.6

00539-006

GAIN (dB)

45

–1

10M
FREQUENCY (Hz)

7.6

90
GAIN

0

1M

Figure 8. Frequency and Phase Response vs. Gain
(Gain = 30 dB, PIN = −30 dBm)

Figure 5. Gain Error vs. Gain Control Voltage at 455 kHz,10.7 MHz, 45 MHz, 70 MHz

1

–225

–6
100k

6.4
–0.6

–0.4

–0.2
0
0.2
GAIN CONTROL VOLTAGE (V)

0.4

Figure 9. Group Delay vs. Gain Control Voltage

Figure 6. Frequency and Phase Response vs. Gain
(Gain = −10 dB, PIN = −30 dBm)

Rev. K | Page 6 of 24

0.600539-009–0.400539-005

–1.5
–0.5

00539-008–0.5

Data Sheet
553 PIECE SAMPLE SIZEVOS AT 10dB GAIN
VOS VS VGAIN

50

10dB/DIV

40

30

20

0

2

4

6

8

10

12

14

16

18

20

OFFSET VOLTAGE (mV)

Figure 13. Third-Order Intermodulation Distortion at 10.7 MHz(10× Probe Used to HP3585A Spectrum Analyzer, Gain = 0 dB, PIN = 0 dBm)

Figure 10. Histogram of VOS at 10 dB Gain and VOS vs. VGAIN–1.0

553 PIECE SAMPLE SIZE

–1.2
–1.4

40

NEGATIVE OUTPUT VOLTAGE (V)PERCENTAGE OF SAMPLES (%)

5000539-012

1000539-057

PERCENTAGE OF SAMPLES (%)

60

AD603

GPOS
GNEG

30

20

10

–1.6
–1.8
–2.0
–2.2
–2.4
–2.6
–2.8
–3.0

85

90

95

100

105

110

–3.4

00539-058

0115

PIN GPOS AND PIN GNEG BIAS CURRENT (nA)

0

50

100

200
500
1000
LOAD RESISTANCE (Ω)

00539-013

–3.2
2000

Figure 14. Typical Output Voltage Swing vs. Load Resistance(Negative Output Swing Limits First)

Figure 11. Histogram of GPOS and GNEG Bias Current

102

INPUT IMPEDANCE (Ω)

10dB/DIV
100

98

96

00539-011

100k

Figure 12. Third-Order Intermodulation Distortion at 455 kHz(10× Probe Used to HP3585A Spectrum Analyzer, Gain = 0 dB, PIN = 0 dBm)

Rev. K | Page 7 of 24

1M

10M
FREQUENCY (Hz)

100M

Figure 15. Input Impedance vs. Frequency (Gain = −10 dB)

00539-014

94

AD603

Data Sheet
4.5V

102

INPUT IMPEDANCE (Ω)

INPUT GND
1V/DIV

100

98

500mV

96
OUTPUT GND
500mV/DIV

1M

10M
FREQUENCY (Hz)100M

–500mV
–49ns

451ns

Figure 19. Input Stage Overload Recovery Time
(Input Is 500 ns Period, 50% Duty-Cycle Square Wave,
Output Is Captured Using Tektronix 11402 Digitizing Oscilloscope)

Figure 16. Input Impedance vs. Frequency (Gain = 10 dB)

102

3V

100
INPUT GND
100MV/DIV98
1V
OUTPUT GND
1V/DIV

96

1M

10M
FREQUENCY (Hz)

100M

Figure 17. Input Impedance vs. Frequency (Gain = 30 dB)

–2V
–49ns

50ns

451ns

00539-019

100k

00539-016

94

Figure 20. Output Stage Overload Recovery Time
(Input Is 500 ns Period, 50% Duty-Cycle Square Wave,
Output Is Captured Using Tektronix 11402 Digitizing Oscilloscope)
3.5V

1V

INPUT
500mV/DIV

100
90

GND

500mV
OUTPUT
500mV/DIV
GND

1V

200ns

–1.5V
–44ns

50ns

456ns

Figure 18. Gain Control Channel Response Time
Figure 21. Transient Response, G = 0 dB
(Input Is 500 ns Period, 50% Duty-Cycle Square Wave,
Output Is Captured Using Tektronix 11402 Digitizing Oscilloscope)

Rev. K | Page 8 of 24

00539-020

100%00539-017

INPUT IMPEDANCE (Ω)

50ns

00539-018

100k

00539-015

94

Data Sheet

AD603
21

3.5V

TA = 25°C
RS = 50ΩTEST SETUP FIGURE 23

10MHz

19
17

NOISE FIGURE (dB)

INPUT GND
100mV/DIV

500mV
OUTPUT GND
500mV/DIV

15

20MHz

13
11
9

50ns

456ns

5
30

00539-021

–1.5V
–44ns

Figure 22. Transient Response, G = 20 dB(Input Is 500 ns Period, 50% Duty-Cycle Square Wave,
Output Is Captured Using Tektronix 11402 Digitizing Oscilloscope)

31

32

33

34

35
36
GAIN (dB)

37

38

39

40

00539-025

7

Figure 25. Noise Figure in 0 dB/40 dB Mode0

TA = 25°C
TEST SETUP FIGURE 23

0–5

INPUT LEVEL (dBm)–10

PSRR (dB)

–20
–30
–40
–50

–10

–15

–60

1M

10M
FREQUENCY (Hz)

100M

Figure 23. PSRR vs. Frequency(Worst Case Is Negative Supply PSRR, Shown Here)

–25
10

30
50
INPUT FREQUENCY (MHz)Figure 26. 1 dB Compression Point, −10 dB/+30 dB Mode, Gain = 30 dB
20

23
21

TA = 25°C
RS = 50VTEST SETUP FIGURE 23

70MHz

70

00539-026

100k

00539-022–20

TA = 25°C
TEST SETUP FIGURE 23

18
30MHz

OUTPUT LEVEL (dBm)

17
50MHz
15
13
30MHz
11

10MHz

9

16
40MHz
14

12
70MHz
10

5
20

21

22

23

24

25
26
GAIN (dB)

27

28

29

30

0
–20

–10
INPUT LEVEL (dBm)

000539-027

700539-024

NOISE FIGURE (dB)19

Figure 27. Third-Order Intercept −10 dB/+30 dB Mode, Gain = 10 dB

Figure 24. Noise Figure in −10 dB/+30 dB ModeRev. K | Page 9 of 24

AD603

Data Sheet

20

18

16
40MHz
14

12
70MHz
10

8
–40

–30
INPUT LEVEL (dBm)–2000539-028

OUTPUT LEVEL (dBm)

30MHz

TA = 25°C
RS = 50Ω
RIN = 50Ω
RL = 100Ω
TEST SETUP FIGURE 23

Figure 28. Third-Order Intercept −10 dB/+30 dB Mode, Gain = 30 dB

Rev. K | Page 10 of 24

Data Sheet

AD603

TEST CIRCUITS
0.1µF

+5V
HP3326A
DUALCHANNELSYNTHESIZER

8
3
5

AD603

100Ω

10×
PROBE

7

2
4

1

HP3585A
SPECTRUM
ANALYZER

511Ω

6

0.1µF
00539-010

–5V
DATEL
DVC 8500

Figure 29. Third-Order Intermodulation Distortion Test Setup

0.1µF

+5V
HP3326A
DUALCHANNELSYNTHESIZER

8
3

50Ω

5

AD603

100Ω

7
2

4

HP3585A
SPECTRUM
ANALYZER

1

6

–5V

DATEL
DVC 850000539-023

0.1µF

Figure 30. Test Setup Used for: Noise Figure, Third-Order Intercept, and1 dB Compression Point Measurements

Rev. K | Page 11 of 24

AD603

Data Sheet

THEORY OF OPERATIONThe AD603 comprises a fixed-gain amplifier, preceded by abroadband passive attenuator of 0 dB to 42.14 dB, having a gain
control scaling factor of 40 dB per volt. The fixed gain is lasertrimmed in two ranges, to either 31.07 dB (×35.8) or 50 dB(×358), or it may be set to any range in between using one
external resistor between Pin 5 and Pin 7. Somewhat higher
gain can be obtained by connecting the resistor from Pin 5 tocommon, but the increase in output offset voltage limits the
maximum gain to about 60 dB. For any given range, thebandwidth is independent of the voltage-controlled gain. Thissystem provides an underrange and overrange of 1.07 dB in allcases; for example, the overall gain is −11.07 dB to +31.07 dB in
the maximum bandwidth mode (Pin 5 and Pin 7 strapped).
This X-AMP structure has many advantages over former
methods of gain control based on nonlinear elements. Most
importantly, the fixed-gain amplifier can use negative feedback
to increase its accuracy. Because large inputs are first attenuated,
the amplifier input is always small. For example, to deliver a±1 V output in the −1 dB/+41 dB mode (that is, using a fixed
amplifier gain of 41.07 dB), its input is only 8.84 mV; therefore,
the distortion can be very low. Equally important, the smallsignal gain and phase response, and thus the pulse response, areessentially independent of gain.
Figure 31 is a simplified schematic. The input attenuator is a
7-section R-2R ladder network, using untrimmed resistors of
nominally R = 62.5 Ω, which results in a characteristic resistance of
125 Ω ± 20%. A shunt resistor is included at the input and laser
trimmed to establish a more exact input resistance of 100 Ω ± 3%,
which ensures accurate operation (gain and HP corner frequency)
when used in conjunction with external resistors or capacitors.
The nominal maximum signal at input VINP is 1 V rms(±1.4 V peak) when using the recommended ±5 V supplies,
although operation to ±2 V peak is permissible with someincrease in HF distortion and feedthrough. Pin 4 (COMM)
must be connected directly to the input ground; significant
impedance in this connection reduces the gain accuracy.
The signal applied at the input of the ladder network is attenuatedby 6.02 dB by each section; therefore, the attenuation to each of
the taps is progressively 0 dB, 6.02 dB, 12.04 dB, 18.06 dB,
24.08 dB, 30.1 dB, 36.12 dB, and 42.14 dB. A unique circuit
technique is employed to interpolate between these tap points,
indicated by the slider in Figure 31, thus providing continuous
attenuation from 0 dB to 42.14 dB. It helps in understanding theAD603 to think in terms of a mechanical means for moving thisslider from left to right; in fact, its position is controlled by thevoltage between Pin 1 and Pin 2. The details of the gain control
interface are in the The Gain Control Interface section.

The gain is at all times very exactly determined, and a linear-indB relationship is automatically guaranteed by the exponential
nature of the attenuation in the ladder network (the X-AMP
principle). In practice, the gain deviates slightly from the ideallaw, by about ±0.2 dB peak (see, for example, Figure 5).

NOISE PERFORMANCE
An important advantage of the X-AMP is its superior noise
performance. The nominal resistance seen at inner tap points is41.7 Ω (one third of 125 Ω), which exhibits a Johnson noise
spectral density (NSD) of 0.83 nV/√Hz (that is, √4kTR) at 27°C,
which is a large fraction of the total input noise. The first stageof the amplifier contributes a further 1 nV/√Hz, for a total input
noise of 1.3 nV/√Hz. It is apparent that it is essential to use alow resistance in the ladder network to achieve the very low
specified noise level. The source impedance of the signal
forms a voltage divider with the 100 Ω input resistance of theAD603. In some applications, the resulting attenuation may
be unacceptable, requiring the use of an external buffer or
preamplifier to match a high impedance source to the low
impedance AD603.
The noise at maximum gain (that is, at the 0 dB tap) depends onwhether the input is short-circuited or open-circuited. Whenshort-circuited, the minimum NSD of slightly over 1 nV/√Hz isachieved. When open-circuited, the resistance of 100 Ω looking
into the first tap generates 1.29 nV/√Hz, so the noise increases
to 1.63 nV/√Hz. (This last calculation would be important if theAD603 were preceded by, for example, a 900 Ω resistor to allow
operation from inputs up to 10 V rms.) As the selected tap
moves away from the input, the dependence of the noise on
source impedance quickly diminishes.
Apart from the small variations just discussed, the signal-tonoise (SNR) at the output is essentially independent of theattenuator setting. For example, on the −11 dB/+31 dB range,
the fixed gain of ×35.8 raises the output NSD to 46.5 nV/√Hz.
Therefore, for the maximum undistorted output of 1 V rms anda 1 MHz bandwidth, the output SNR would be 86.6 dB, that is,
20 log(1 V/46.5 µV).

Rev. K | Page 12 of 24

Data Sheet

AD603
VPOS 8SCALINGREFERENCE

VNEG 6PRECISION PASSIVEINPUT ATTENUATORFIXED-GAIN
AMPLIFIER

GPOS 1

7

VOUT

5

FDBK

VG
GNEG 26.44kΩ*

AD603

GAINCONTROLINTERFACE

694Ω*
0dB
VINP 3–6.02dB
R

2R–12.04dB –18.06dB –24.08dB
R

2R

R

2R

R

2R

–30.1dB
R

2R–36.12dB –42.14dB
R

2R

R

20Ω*

R

COMM 400539-029

R-2R LADDER NETWORK*NOMINAL VALUES.

Figure 31. Simplified Block Diagram

THE GAIN CONTROL INTERFACE
The attenuation is controlled through a differential, highimpedance (50 MΩ) input, with a scaling factor that is lasertrimmed to 40 dB per volt, that is, 25 mV/dB. An internal band
gap reference ensures stability of the scaling with respect tosupply and temperature variations.
When the differential input voltage VG = 0 V, the attenuatorslider is centered, providing an attenuation of 21.07 dB. For the
maximum bandwidth range, this results in an overall gain of
10 dB (= −21.07 dB + 31.07 dB). When the control input is−500 mV, the gain is lowered by +20 dB (= 0.500 V × 40 dB/V)
to −10 dB; when set to +500 mV, the gain is increased by+20 dB to +30 dB. When this interface is overdriven in either
direction, the gain approaches either −11.07 dB (= − 42.14 dB ++31.07 dB) or 31.07 dB (= 0 + 31.07 dB), respectively. The only
constraint on the gain control voltage is that it be kept within
the common-mode range (−1.2 V to +2.0 V assuming +5 V
supplies) of the gain control interface.
The basic gain of the AD603 can therefore be calculated by
Gain (dB) = 40 VG +10(1)

where VG is in volts. When Pin 5 and Pin 7 are strapped (see theProgramming the Fixed-Gain Amplifier Using Pin Strapping
section), the gain becomes

For example, if the gain is to be controlled by a DAC providing
a positive-only, ground-referenced output, the gain control low(GNEG) pin should be biased to a fixed offset of 500 mV to set
the gain to −10 dB when gain control high (GPOS) is at zero,and to 30 dB when at 1.00 V.
It is a simple matter to include a voltage divider to achieve otherscaling factors. When using an 8-bit DAC having an FS output
of 2.55 V (10 mV/bit), a divider ratio of 2 (generating 5 mV/bit)
results in a gain-setting resolution of 0.2 dB/bit. The use of suchoffsets is valuable when two AD603s are cascaded, whenvarious options exist for optimizing the signal-to-noise profile,
as is shown in the Sequential Mode (Optimal SNR) section,

PROGRAMMING THE FIXED-GAIN AMPLIFIERUSING PIN STRAPPING
Access to the feedback network is provided at Pin 5 (FDBK).
The user may program the gain of the output amplifier of theAD603 using this pin, as shown in Figure 32, Figure 33, andFigure 34. There are three modes: in the default mode, FDBK
is unconnected, providing the range +9 dB/+51 dB; when VOUT
and FDBK are shorted, the gain is lowered to −11 dB/+31 dB;
and, when an external resistor is placed between VOUT and
FDBK, any intermediate gain can be achieved, for example,−1 dB/+41 dB. Figure 35 shows the nominal maximum gain vs.
external resistor for this mode.

Gain (dB) = 40 VG + 20 for 0 to +40 dB
VC1

and

1

GPOS

VPOS 8

VPOS

AD603
VC2

(2)

The high impedance gain control input ensures minimalloading when driving many amplifiers in multiple channel
or cascaded applications. The differential capability provides
flexibility in choosing the appropriate signal levels andpolarities for various control schemes.

Rev. K | Page 13 of 24

VIN

2

GNEG

VOUT 73

VINP

VNEG 64COMM

FDBK 5VOUT
VNEG

Figure 32. −10 dB to +30 dB; 90 MHz Bandwidth00539-030

Gain (dB) = 40 VG + 30 for +10 to +50 dB

AD603

Data Sheet
VC1

1

GPOS

VC2

2

GNEG

VOUT 73

VINP

VNEG 64COMM

FDBK 5VPOS 8

Optionally, when a resistor is placed from FDBK to COMM,
higher gains can be achieved. This fourth mode is of limited
value because of the low bandwidth and the elevated output
offsets; it is thus not included in Figure 32, Figure 33, orFigure 34.

VPOS

AD603

VIN

VOUT

VNEG
2.15kΩ

The gain of this amplifier in the first two modes is set by theratio of on-chip laser-trimmed resistors. While the ratio of these
resistors is very accurate, the absolute value of these resistors
can vary by as much as ±20%. Therefore, when an external
resistor is connected in parallel with the nominal 6.44 kΩ ± 20%
internal resistor, the overall gain accuracy is somewhat poorer.
The worst-case error occurs at about 2 kΩ (see Figure 36).

00539-031

5.6pF

Figure 33. 0 dB to 40 dB; 30 MHz Bandwidth
VC1

1

GPOS

VPOS 8

VPOS

AD603
VC2

2

GNEG

VOUT 73

VINP

VNEG 64COMM

FDBK 5

VOUT

1.2
VNEG

0.8
0.6

GAIN ERROR (dB)

18pF

Figure 34. 10 dB to 50 dB; 9 MHz to Set Gain
52
50

–1:VdB (OUT)

48

0.4
0.2
0
–0.2
–0.4

46

–0.6

–1.0
10

–2:VdB (OUT)
40

VdB (OUT) – VdB (OREF )
100

1k

10k
REXT (Ω)

38

100k

1M

00539-034–0.8

VdB (OUT)

42

Figure 36. Worst-Case Gain Error, Assuming Internal Resistors Have a
Maximum Tolerance of −20% (Top Curve) or = 20% (Bottom Curve)

36
34
32
100

1k

10k
REXT (Ω)

100k

1M00539-033

GAIN (dB)

44

30
10

–1:VdB (OUT) – (–1):VdB (OREF )1.000539-032

VIN

Figure 35. Gain vs. REXT, Showing Worst-Case Limits Assuming Internal
Resistors Have a Maximum Tolerance of 20%

While the gain bandwidth product of the fixed-gain amplifier isabout 4 GHz, the actual bandwidth is not exactly related to the
maximum gain. This is because there is a slight enhancing of
the ac response magnitude on the maximum bandwidth range,
due to higher order poles in the open-loop gain function; thismild peaking is not present on the higher gain ranges. Figure 32,
Figure 33, and Figure 34 show how an optional capacitor may
be added to extend the frequency response in high gain modes.

Rev. K | Page 14 of 24

Data Sheet

AD603

USING THE AD603 IN CASCADE
Figure 37 shows the SNR over a gain range of −22 dB to +62 dB,
assuming an output of 1 V rms and a 1 MHz bandwidth. Figure 38,
Figure 39, and Figure 40 show the general connections toaccomplish this. Here, both the positive gain control inputs(GPOS) are driven in parallel by a positive-only, ground-referenced
source with a range of 0 V to 2 V, while the negative gain
control inputs (GNEG) are biased by stable voltages to provide
the needed gain offsets. These voltages may be provided byresistive dividers operating from a common voltage reference.

Two or more AD603s can be connected in series to achieve
higher gain. Invariably, ac coupling must be used to prevent thedc offset voltage at the output of each amplifier from overloading
the following amplifier at maximum gain. The required highpass coupling network is usually just a capacitor, chosen to set
the desired corner frequency in conjunction with the welldefined 100 Ω input resistance of the following amplifier.
For two AD603s, the total gain control range becomes 84 dB(2 × 42.14 dB); the overall −3 dB bandwidth of cascaded stages
is somewhat reduced. Depending on the pin strapping, the gain
and bandwidth for two cascaded amplifiers can range from−22 dB to +62 dB (with a bandwidth of about 70 MHz) to+22 dB to +102 dB (with a bandwidth of about 6 MHz).

90
85
80
75

SNR (dB)

There are several ways of connecting the gain control inputs
in cascaded operation. The choice depends on whether it isimportant to achieve the highest possible instantaneous signalto-noise ratio (ISNR), or, alternatively, to minimize the ripple
in the gain error. The following examples feature the AD603
programmed for maximum bandwidth; the explanations apply
to other gain/bandwidth combinations with appropriatechanges to the arrangements for setting the maximum gain.

70
65
60

50
–0.2

SEQUENTIAL MODE (OPTIMAL SNR)

A1

GNEG
VG1

–51.07dB

31.07dB–8.93dB–42.14dB
GPOS
VG2

VO1 = 0.473V

VC = 0V

GNEG

31.07dBOUTPUT–20dB

VO2 = 1.526V

00539-036–42.14dB

1.0
VC (V)

A2–40.00dB

GPOS

0.6

Figure 38. AD603 Gain Control Input Calculations for Sequential Control Operation VC = 0 V–11.07dB

0dB
GPOS

GNEG
VG1

31.07dB

31.07dB–42.14dB
GPOS
VG2

VO1 = 0.473V

VC = 1.0V

GNEG

31.07dBOUTPUT
20dB

VO2 = 1.526V

00539-037

0dB

INPUT
0dB

Figure 39. AD603 Gain Control Calculations for Sequential Control Operation VC = 1.0 V

0dB
GPOS

GNEG
VG1

VC = 2.0V–28.93dB

31.07dB

VO1 = 0.473V

31.07dB–2.14dB
GPOS

GNEG
VG2

31.07dBOUTPUT
60dB

VO2 = 1.526V

Figure 40. AD603 Gain Control Input Calculations for Sequential Operation VC = 2.0 V

Rev. K | Page 15 of 24

00539-038

0dB

INPUT
0dB

1.4

1.8

2.2

Figure 37. SNR vs. Control Voltage, Sequential Control (1 MHz Bandwidth)

In the sequential mode of operation, the ISNR is maintained at
its highest level for as much of the gain control range as possible.

INPUT
0dB

0.2

00539-035

55

AD603

Data Sheet

Gain (dB) = 40 VG + GO

(3)

Figure 43 is a plot of the SNR of the cascaded amplifiers vs. thecontrol voltage. Figure 44 is a plot of the gain error of thecascaded stages vs. the control voltages.
70
60

20
10
0
A2

0.2

0.6

1.0
VC (V)

1.4

1.8

2.0

00539-040

–30
–0.2

Figure 42. Plot of Separate and Overall Gains in Sequential Control
90+31.07dB

80+31.07dB+28.96dB

70

A2*–11.07dB*

60

SNR (dB)

A1–8.93dB–11.07dB
1.526
0.5
0

1.0
20

1.50
40

2.0
60

VC (V)
62.14*GAIN OFFSET OF 1.07dB, OR 26.75mV.

00539-039

0.473
0
–20

A1

30

–20

In the explanatory notes that follow, it is assumed thatthe maximum bandwidth connections are used, for which
GO is −20 dB.

GAIN(dB) –22.14

40

–10

where:VG is the applied control voltage.
GO is determined by the gain range chosen.

+10dB

COMBINED

50

OVERALL GAIN (dB)

The gains are offset (Figure 41) such that the gain of A2 isincreased only after the gain of A1 has reached its maximum
value. Note that for a differential input of –600 mV or less, thegain of a single amplifier (A1 or A2) is at its minimum value of−11.07 dB; for a differential input of 600 mV or more, the gain
is at its maximum value of 31.07 dB. Control inputs beyond
these limits do not affect the gain and can be tolerated without
damage or foldover in the response. This is an important aspectof the gain control response of the AD603. (See the Specifications
section for more details on the allowable voltage range.) The
gain is now

50
40
30
20

When VG = 2.0 V, the gain of A1 is pinned at 31.07 dB and thatof A2 is near its maximum value of 28.93 dB, resulting in an
overall gain of 60 dB (see Figure 40). This mode of operation isfurther clarified in Figure 42, which is a plot of the separate
gains of A1 and A2 and the overall gain vs. the control voltage.

0.2

0.6

1.0
VC (V)

1.4

1.8

2.0

Figure 43. SNR for Cascaded Stages—Sequential Control
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–0.2

0

0.2

0.4

0.6

0.8

1.0 1.2
VC (V)

1.4

1.6

1.8

2.0

2.2

Figure 44. Gain Error for Cascaded Stages–Sequential Control

PARALLEL MODE (SIMPLEST GAIN CONTROLINTERFACE)
In this mode, the gain control of voltage is applied to both
inputs in parallel: the GPOS pins of both A1 and A2 are

Rev. K | Page 16 of 24

00539-042

When VG = 1.00 V, VG1 = 1.00 V − 0.473 V = 0.526 V, which sets
the gain of A1 to nearly its maximum value of +31.07 dB, while
VG2 = 1.00 V − 1.526 V = 0.526 V, which sets the gain of A2 tonearly its minimum value of −11.07 dB. Close analysis showsthat the degree to which neither AD603 is completely pushed toits maximum nor minimum gain exactly cancels in the overall
gain, which is now 20 dB (see Figure 39).

10
–0.2

GAIN ERROR (dB)

With reference to Figure 38, Figure 39, and Figure 40, note that
VG1 refers to the differential gain control input to A1, and VG2refers to the differential gain control input to A2. When VG is
0 V, VG1 = −473 mV and thus the gain of A1 is −8.93 dB (recall
that the gain of each individual amplifier in the maximum
bandwidth mode is –10 dB for VG = −500 mV and 10 dB for VG= 0 V); meanwhile, VG2 = −1.908 V so the gain of A2 is pinned
at −11.07 dB. The overall gain is therefore –20 dB (see Figure 38).

00539-041

Figure 41. Explanation of Offset Calibration for Sequential Control

Data Sheet

AD603
LOW GAIN RIPPLE MODE (MINIMUM GAIN ERROR)

connected to the control voltage and the GNEW inputs are
grounded. The gain scaling is then doubled to 80 dB/V,
requiring only a 1.00 V change for an 80 dB change of gain
Gain = (dB) = 80 VG + GO

(4)

where, as before, GO depends on the range selected; for example,
in the maximum bandwidth mode, GO is 20 dB. Alternatively,
the GNEG pins may be connected to an offset voltage of
0.500 V, in which case GO is −20 dB.
The amplitude of the gain ripple in this case is also doubled, as
shown in Figure 45, while the ISNR at the output of A2 now
decreases linearly as the gain increases, as shown in Figure 46.

As can be seen in Figure 44 and Figure 45, the error in the gain
is periodic, that is, it shows a small ripple. (Note that there isalso a variation in the output offset voltage, which is due to thegain interpolation, but this is not exact in amplitude.) By
offsetting the gains of A1 and A2 by half the period of the ripple,
that is, by 3 dB, the residual gain errors of the two amplifiers
can be made to cancel. Figure 47 shows much lower gain ripple
when configured in this manner. Figure 48 plots the ISNR as afunction of gain; it is very similar to that in the parallel mode.
3.0
2.5

2.0

2.0
1.5

GAIN ERROR (dB)

1.5

0.5
0

0.5
0
–0.5
–1.0
–1.5

–0.5

–2.0

–1.0

–3.0
–0.1

0

0.2

0.4

0.6

0.8

1.0 1.2
VC (V)

1.4

1.6

1.8

2.0

2.2

00539-043

–2.0
–0.2

85

80

80

75

ISNR (dB)

85

75
70

60

55

55

50
–0.2
0.8

1.0

1.2

0.5 0.6
VC (V)

0.7

0.8

0.9

1.0

1.1

0

0.2

0.4

0.6

0.8

1.0

1.2

VC (V)

00539-044

0.6
VC (V)

0.4

65
60

0.4

0.3

70

65

0.2

0.2

Figure 47. Gain Error for Cascaded Stages—Low Ripple Mode

Figure 45. Gain Error for Cascaded Stages—Parallel Control

0

0.1

90

90

50
–0.2

0

00539-045

–2.5

–1.5

ISNR (dB)

1.0

Figure 48. ISNR vs. Control Voltage—Low Ripple Mode

Figure 46. ISNR for Cascaded Stages—Parallel Control

Rev. K | Page 17 of 24

00539-046

GAIN ERROR (dB)

1.0

AD603

Data SheetAPPLICATIONS INFORMATIONA LOW NOISE AGC AMPLIFIER

The circuit operates as follows:

Figure 49 shows the ease with which the AD603 can beconnected as an AGC amplifier. The circuit illustrates many ofthe points previously discussed: it uses few parts, has linear-indB gain, operates from a single supply, uses two cascaded amplifiersin sequential gain mode for maximum SNR, and an external
resistor programs each gain of the amplifier. It also uses a
simple temperature-compensated detector.

 A1 and A2 are cascaded.
 Capacitor C1 and the 100 Ω of resistance at the input of A1
form a time constant of 10 μs.
 C2 blocks the small dc offset voltage at the output of A1(which might otherwise saturate A2 at its maximum gain)
and introduces a high-pass corner at about 16 kHz,eliminating low frequency noise.

The circuit operates from a single 10 V supply. Resistors R1, R2,
R3, and R4 bias the common pins of A1 and A2 at 5 V. The
common pin is a low impedance point and must have a low
impedance path to ground, provided here by the 100 μF tantalum
capacitors and the 0.1 μF ceramic capacitors.

A half-wave detector is used, based on Q1 and R8. The current
into capacitor, CAV, is the difference between the collector
current of Q2 (biased to be 300 μA at 300 K, 27°C) and thecollector current of Q1, which increases with the amplitudeof the output signal.

The cascaded amplifiers operate in sequential gain. Here, theoffset voltage between Pin 2 (GNEG) of A1 and A2 is 1.05 V(42.14 dB × 25 mV/dB), provided by a voltage divider consisting ofResistors R5, R6, and R7. Using standard values, the offset is notexact, but it is not critical for this application.

The automatic gain control voltage, VAGC, is the time integralof this error current. For VAGC (and thus the gain) to remain
insensitive to short-term amplitude fluctuations in the output
signal, the rectified current in Q1 must, on average, exactly
balance the current in Q2. If the output of A2 is too small todo this, VAGC increases, causing the gain to increase until Q1
conducts sufficiently.

The gain of both A1 and A2 is programmed by Resistors R13
and R14, respectively, to be about 42 dB; therefore, the maximum
gain of the circuit is twice that, or 84 dB. The gain control range
can be shifted up by as much as 20 dB by appropriate choices of
R13 and R14.

Consider the case where R8 is zero and the output voltage VOUT
is a square wave at, for example, 455 kHz, which is well above
the corner frequency of the control loop.
10V

C7
0.1µF

10V

C1
0.1µF
J1

R1
2.49kΩ
+

C4
0.1µF

5

8

7

A2
AD603

10V
1

C 52
100µF

+

C6
0.1µF

Q1
2N3904
R8
806Ω

5

R11
3.83kΩ
5V
R1 2
4.99kΩ

C9
0.1µF
J2

7
2

C10
0.1µF

4

R3
2.49kΩ

R2
2.49kΩ

CAV
0.1µF

6

3

2

4

R1 4
2.49kΩ

C11
0.1µF

1

R4
2.49kΩ
AGC LINE

1V OFFSET FOR
SEQUENTIAL GAIN

R55.49kΩ
5.5V

R6
1.05kΩ

R7
3.48kΩ
6.5V

10V00539-047

C 32
100µF

C2
0.1µF

6

A1
AD603

10V

10V

R1 0
1.24kΩ

Q2
2N3906

VAGC

C8
0.1µF

R1 3
2.49kΩ

8
3

R T1
100Ω

R9
1.54kΩ

THIS CAPACITOR SETS
AGC TIME CONSTANT

1 RT PR OVI D ES A 5 0Ω IN PU T I MPED A N C E.
2 C 3 A N D C 5 A R E TA NTA LU M.

Figure 49. A Low Noise AGC Amplifier

Rev. K | Page 18 of 24

Data Sheet

AD603

During the time VOUT is negative with respect to the basevoltage of Q1, Q1 conducts; when VOUT is positive, it is cut off.
Because the average collector current of Q1 is forced to be
300 µA, and the square wave has a duty cycle of 1:1, Q1’s
collector current when conducting must be 600 µA. With R8
omitted, the peak amplitude of VOUT is forced to be just the VBE
of Q1 at 600 µA, typically about 700 mV, or 2 VBE peak-to-peak.
This voltage, the amplitude at which the output stabilizes, has astrong negative temperature coefficient (TC), typically −1.7 mV/°C.
Although this may not be troublesome in some applications, thecorrect value of R8 renders the output stable with temperature.
To understand this, note that the current in Q2 is made to be
proportional to absolute temperature (PTAT). For the moment,
continue to assume that the signal is a square wave.
When Q1 is conducting, VOUT is now the sum of VBE and a
voltage that is PTAT and that can be chosen to have an equal
but opposite TC to that of the VBE. This is actually nothing morethan an application of the band gap voltage reference principle.
When R8 is chosen such that the sum of the voltage across it
and the VBE of Q1 is close to the band gap voltage of about 1.2 V,
VOUT is stable over a wide range of temperatures, provided, ofcourse, that Q1 and Q2 share the same thermal environment.
Because the average emitter current is 600 µA during each halfcycle of the square wave, a resistor of 833 Ω adds a PTAT
voltage of 500 mV at 300 K, increasing by 1.66 mV/°C. In
practice, the optimum value depends on the type of transistor
used and, to a lesser extent, on the waveform for which thetemperature stability is to be optimized; for the inexpensive
2N3904/2N3906 pair and sine wave signals, the recommended
value is 806 Ω.

This resistor also serves to lower the peak current in Q1 whenmore typical signals (usually sinusoidal) are involved, and the
1.8 kHz LP filter it forms with CAV helps to minimize distortiondue to ripple in VAGC. Note that the output amplitude under sine
wave conditions is higher than for a square wave because theaverage value of the current for an ideal rectifier is 0.637 times
as large, causing the output amplitude to be 1.88 (= 1.2/0.637) V,or 1.33 V rms. In practice, the somewhat nonideal rectifier
results in the sine-wave output being regulated to about
1.4 V rms, or 3.6 V p-p.
The bandwidth of the circuit exceeds 40 MHz. At 10.7 MHz, theAGC threshold is 100 µV (−67 dBm) and its maximum gain is
83 dB (20 log 1.4 V/100 µV). The circuit holds its output at
1.4 V rms for inputs as low as −67 dBm to +15 dBm (82 dB),
where the input signal exceeds the maximum input rating of theAD603. For a 30 dBm input at 10.7 MHz, the second harmonicis 34 dB down from the fundamental, and the third harmonic is
35 dB down from the fundamental.

CAUTION
Careful component selection, circuit layout, power supply
decoupling, and shielding are needed to minimize the susceptibilityof the AD603 to interference from signals such as those fromradio and TV stations. In bench evaluation, it is recommended
to place all of the components into a shielded box and use
feedthrough decoupling networks for the supply voltage. Circuit
layout and construction are also critical because stray capacitancesand lead inductances can form resonant circuits and are apotential source of circuit peaking, oscillation, or both.

Rev. K | Page 19 of 24

AD603

Data SheetEVALUATION BOARD
The output is also ac-coupled and includes a 453 Ω series resistor.
Set the AD603 gain by connecting a voltage source between the
GNEG and GPOS test loops. The two slide switches SGPOS and
SGNEG provide three connections for GPOS and the GNEG.
Either pin can be ground referenced, or biased with a user selectedvoltage established by R1 and R5 to R7. A signal generator canbe connected to the GPOS or GNEG test loops, or the GNEG canbe driven to either polarity within the common-mode limits of−1.2 V to +2.0 V; to invert the gain slope, simply reverse thepolarity of the voltage source connected to GPOS and GNEG.
For bias current measurements, the third switch option
disconnects the bias voltage source and permits connection of a
microammeter between the GPOS and GNEG pins to ground.

00539-049

The evaluation board of the AD603 enables simple bench-top
experimenting to be performed with easy control of theAD603. Built-in flexibility allows convenient configuration toaccommodate most operating configurations. Figure 50 is aphotograph of the AD603 evaluation board.

Figure 50. AD603 Evaluation Board

Any dual-polarity power supply capable of providing 20 mA is
all that is required, in addition to whatever test equipment theuser wishes to perform the intended tests.

The AD603 includes built-in gain resistors selectable at the
FDBK pin. The board is shipped with the gain at minimum,with a 0 Ω resistor installed in R3. For maximum gain, simply
remove R3. Because of the architecture of the AD603, thebandwidth decreases by 10, but the gain range remains at 40 dB.
Intermediate gain values may be selected by installing a resistor
between the VOUT and FDBK pins.
Figure 52, Figure 53, and Figure 56 show the component andcircuit side copper patterns and silkscreen.

Referring to the schematic in Figure 51, the input to the VGA issingle-ended, ac-coupled, and terminated in 50 Ω to accommodate
most commonly available signal generators.
G1

VPOS GND VNEG
C7
C8
10µF
10µF
25V
25V

G3

G4

G5

G6

+

+

VPOS
VPOS

VNEG
VPOS

GPOS

GPOSS
R7

G2

C1
0.1µF

SGPOS

00539-051

C2
0.1µF

R1

VO

VNEG
VPOS
GNEGS
R6

AD603

GNEG

C4
SGNEG 0.1µF

1

C5
0.1µF

VNEG

3
4

VIN
W2

R2
100Ω

R4
453Ω

VOUT

8
GPOS VPOS

2
R5

C6
0.1µF

GNEG VOUT
VINP

VNEG

COMM FDBK

W1
7
6
5
C9

R3
0Ω

VNEG
C3
0.1µF

VPOS
R8
SCOM
00539-050

R9
VNEG

Figure 51. Schematic of the AD603 Evaluation Board

Rev. K | Page 20 of 24

Figure 52. Component Side CopperAD603Figure 53. Secondary Side Copper

00539-054

00539-052

Data Sheet

00539-055

00539-053

Figure 55. Inner Layer Power Plane

Figure 56. Component Side Silk Screen

Figure 54. Inner Layer Ground Plane

Rev. K | Page 21 of 24

AD603

Data SheetOUTLINE DIMENSIONS
0.005 (0.13)
MIN

0.055 (1.40)
MAX

8

5

0.310 (7.87)
0.220 (5.59)
1

40.100 (2.54) BSC
0.320 (8.13)
0.290 (7.37)

0.405 (10.29) MAX
0.060 (1.52)
0.015 (0.38)

0.200 (5.08)
MAX

0.150 (3.81)
MIN

0.200 (5.08)
0.125 (3.18)
0.023 (0.58)
0.014 (0.36)

0.070 (1.78)
0.030 (0.76)

SEATING
PLANE

15°
0°

0.015 (0.38)
0.008 (0.20)

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FORREFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 57. 8-Lead Ceramic Dual In-Line Package [CERDIP](Q-8)
Dimensions shown in inches and (millimeters)
5.00 (0.1968)
4.80 (0.1890)

156.20 (0.2441)
5.80 (0.2284)

41.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
COPLANARITY
0.10
SEATING
PLANE

1.75 (0.0688)
1.35 (0.0532)

0.51 (0.0201)
0.31 (0.0122)

0.50 (0.0196)
0.25 (0.0099)

45°

8°
0°
0.25 (0.0098)
0.17 (0.0067)

1.27 (0.0500)
0.40 (0.0157)

COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FORREFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 58. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)

Rev. K | Page 22 of 24

012407-A

8

4.00 (0.1574)
3.80 (0.1497)

Data Sheet

AD603
0.07

12-07-2011-A

0.088

TOP VIEW(CIRCUIT SIDE)

Figure 59. 9-Pad Bare Die [CHIP](C-9-1)
Dimensions Shown in Inches

ORDERING GUIDE
Model 1, 2
AD603ARAD603AR-REEL
AD603AR-REEL7
AD603ARZ
AD603ARZ-REEL
AD603ARZ-REEL7
AD603AQ
AD603SQ/883B
AD603-EVALZ
AD603ACHIPS
1
2

Temperature Range−40°C to +85°C−40°C to +85°C−40°C to +85°C−40°C to +85°C−40°C to +85°C−40°C to +85°C−40°C to +85°C−55°C to +125°C

Package Description
8-Lead SOIC_N
8-Lead SOIC_N, 13" Tape and Reel
8-Lead SOIC_N, 7" Tape and Reel
8-Lead SOIC_N
8-Lead SOIC_N, 13" Tape and Reel
8-Lead SOIC_N, 7" Tape and Reel
8-Lead CERDIP
8-Lead CERDIP
Evaluation BoardDIE

Z = RoHS Compliant Part.
For AD603SQ/883B, refer to AD603 Military data sheet. Also available as 5962-9457203MPA.

Rev. K | Page 23 of 24

Package Option
R-8
R-8
R-8
R-8
R-8
R-8
Q-8
Q-8
C-9-1

AD603

Data SheetNOTES©1993–2012 Analog Devices, Inc. All rights reserved. Trademarks andregistered trademarks are the property of their respective owners.
D00539-0-4/12(K)Rev. K | Page 24 of 24