IS25LP040E
IS25LP020E
IS25LP010E
IS25LP512E
IS25LP025E

IS25WP040E
IS25WP020E
IS25WP010E
IS25WP512E
IS25WP025E

4M/2M/1M/512K/256Kb
SERIAL FLASH MEMORY WITH 104MHZ MULTI I/O SPI &QPI INTERFACEDATA SHEETIS25LP040E/020E/010E/512E/025E
IS25WP040E/020E/010E/512E/025E

4M/2M/1M/512K/256Kb
SERIAL FLASH MEMORY WITH 104MHZ MULTI I/O SPI & QPI INTERFACEFEATURES• Industry Standard Serial Interface- IS25LP040E: 4Mbit/512Kbyte- IS25WP040E: 4Mbit/512Kbyte- IS25LP020E: 2Mbit/256Kbyte- IS25WP020E: 2Mbit/256Kbyte- IS25LP010E: 1Mbit/128Kbyte- IS25WP010E: 1Mbit/128Kbyte- IS25LP512E: 512Kbit/64Kbyte- IS25WP512E: 512Kbit/64Kbyte- IS25LP025E: 256Kbit/32Kbyte- IS25WP025E: 256Kbit/32Kbyte- 256 bytes per Programmable Page
- Supports standard SPI, Multi-I/O SPI, and
QPI- Supports Serial Flash Discoverable
Parameters (SFDP)• High Performance Serial Flash (SPI)- 50MHz Normal and 104Mhz Fast Read
- 416 MHz equivalent QPI- Supports SPI Modes 0 and 3- More than 100,000 Erase/Program Cycles- More than 20-year Data Retention• Flexible & Efficient Memory Architecture- Chip Erase with Uniform Sector/Block
Erase (4/32/64 Kbyte)- Program 1 to 256 Bytes per Page
- Program/Erase Suspend & Resume- Soft RESET & In-Band RESET• Low Power with Wide Temp. Ranges- Single Voltage Supply:
IS25LP: 2.30V to 3.60V
IS25WP: 1.70V to 1.95V- 6 mA Active Read Current- 17 µA Standby Current- 3 µA Deep Power Down
- Temp Grades:
Extended: -40°C to +105°C
Auto Grade (A3): -40°C to +125°C• Advanced Security Protection- Software and Hardware Write Protection- Power Supply Lock Protect- 4x256-Byte Dedicated Security Area
with OTP User-lockable Bits
- 128 bit Unique ID for Each Device(Call Factory)• Industry Standard Pin-out & Packages(1)- B = 8-pin SOIC 208mil (Call Factory)- N = 8-pin SOIC 150mil- D = 8-pin TSSOP (Call Factory)- V = 8-pin VVSOP 150mil (Call Factory)- K = 8-contact WSON 6x5mm (Call Factory)- Y = 8-contact USON 2x3mm- KGD (Call Factory)
Note:
1. Call Factory for other package• Efficient Read and Program modes- XIP Read Operation; Dual I/O & Quad IO
Read with AX mode
- Continuous Read & Wrap Burst Read
(8/16/32/64-Byte)- Program Operation during Erase
Suspend Mode

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GENERAL DESCRIPTION
The IS25LP/WP040E/020E/010E/512E/025E and Serial Flash memory offers a versatile storage solution with highflexibility and performance in a simplified pin count package. ISSI’s “Industry Standard Serial Interface” Flash isfor systems that require limited space, a low pin count, and low power consumption. The device is accessed
through a 4-wire SPI Interface consisting of a Serial Data Input (SI), Serial Data Output (SO), Serial Clock (SCK),
and Chip Enable (CE#) pins, which can also be configured to serve as multi-I/O (see pin descriptions).
The device supports Dual and Quad I/O as well as standard, Dual Output, and Quad Output SPI. Clock frequenciesof up to 104MHz allow for equivalent clock rates of up to 416MHz (104MHz x 4) which equates to 52Mbytes/s ofdata throughput. These transfer rates can outperform 16-bit Parallel Flash memories allowing for efficient memory
access to support XIP (execute in place) operation.
The memory array is organized into programmable pages of 256-bytes. This family supports page program mode
where 1 to 256 bytes of data are programmed in a single command. QPI (Quad Peripheral Interface) supports 2cycle instruction further reducing instruction times. Pages can be erased in groups of 4Kbyte sectors, 32Kbyte
blocks, 64Kbyte blocks, and/or the entire chip. The uniform sector and block architecture allows for a high degreeof flexibility so that the device can be utilized for a broad variety of applications requiring solid data retention.

GLOSSARYStandard SPI
In this operation, a 4-wire SPI Interface is utilized, consisting of Serial Data Input (SI), Serial Data Output (SO),Serial Clock (SCK), and Chip Enable (CE#) pins. Instructions are sent via the SI pin to encode instructions,addresses, or input data to the device on the rising edge of SCK. The SO pin is used to read data or to check thestatus of the device. This device supports SPI bus operation modes (0, 0) and (1, 1).
Multi I/O SPIMulti-I/O operation utilizes an enhanced SPI protocol to allow the device to function with Dual Output, Dual Input
and Output, Quad Output, and Quad Input and Output capability. Executing these instructions through SPI mode
will achieve double or quadruple the transfer bandwidth for READ and PROGRAM operations.
QPI
The device supports Quad Peripheral Interface (QPI) operations only when the device is switched fromStandard/Dual/Quad SPI mode to QPI mode using the enter QPI (35h) instruction. The typical SPI protocol requiresthat the byte-long instruction code being shifted into the device only via SI pin in eight serial clocks. The QPI modeutilizes all four I/O pins to input the instruction code thus requiring only two serial clocks. This can significantly
reduce the SPI instruction overhead and improve system performance. Only QPI mode or SPI/Dual/Quad modecan be active at any given time. Enter QPI (35h) and Exit QPI (F5h) instructions are used to switch between these
two modes, regardless of the non-volatible Quad Enable (QE) bit status in the Status Register. Power Reset orSoftware Reset will return the device into the standard SPI mode. SI and SO pins become bidirectional I/O0 and
I/O1, and WP# and HOLD# pins become I/O2 and I/O3 respectively during QPI mode.

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TABLE OF CONTENTSFEATURES ............................................................................................................................................................ 2
GENERAL DESCRIPTION .................................................................................................................................... 3
TABLE OF CONTENTS ......................................................................................................................................... 4
1.

PIN CONFIGURATION ................................................................................................................................... 62.

PIN DESCRIPTIONS ...................................................................................................................................... 7

3.

BLOCK DIAGRAM .......................................................................................................................................... 84.

SPI MODES DESCRIPTION .......................................................................................................................... 95.

SYSTEM CONFIGURATION ........................................................................................................................ 11
5.1 BLOCK/SECTOR ADDRESSES ............................................................................................................ 11
5.2 Serial Flash Discoverable Parameters ................................................................................................... 13

6.

REGISTERS ................................................................................................................................................. 18
6.1 STATUS REGISTER .............................................................................................................................. 18
6.2 FUNCTION REGISTER .......................................................................................................................... 22

7.

PROTECTION MODE................................................................................................................................... 23
7.1 HARDWARE WRITE PROTECTION...................................................................................................... 23
7.2 SOFTWARE WRITE PROTECTION ...................................................................................................... 23

8.

DEVICE OPERATION .................................................................................................................................. 24
8.1 NORMAL READ OPERATION (NORD, 03h) ......................................................................................... 27
8.2 FAST READ OPERATION (FRD, 0Bh) .................................................................................................. 29
8.3 HOLD OPERATION ................................................................................................................................ 31
8.4 FAST READ DUAL I/O OPERATION (FRDIO, BBh) ............................................................................. 31
8.5 FAST READ DUAL OUTPUT OPERATION (FRDO, 3Bh) ..................................................................... 34
8.6 FAST READ QUAD OUTPUT OPERATION (FRQO, 6Bh).................................................................... 35
8.7 FAST READ QUAD I/O OPERATION (FRQIO, EBh) ............................................................................ 37
8.8 PAGE PROGRAM OPERATION (PP, 02h) ............................................................................................ 41
8.9 QUAD INPUT PAGE PROGRAM OPERATION (PPQ, 32h/38h) .......................................................... 43
8.10 ERASE OPERATION ........................................................................................................................... 44
8.11 SECTOR ERASE OPERATION (SER, D7h/20h) ................................................................................. 45
8.12 BLOCK ERASE OPERATION (BER32K:52h or 52h/D8h, BER64K:D8h) ........................................... 46
8.13 CHIP ERASE OPERATION (CER, C7h/60h) ....................................................................................... 48
8.14 WRITE ENABLE OPERATION (WREN, 06h) ...................................................................................... 49
8.15 WRITE DISABLE OPERATION (WRDI, 04h) ....................................................................................... 50
8.16 READ STATUS REGISTER OPERATION (RDSR, 05h) ..................................................................... 51
8.17 WRITE STATUS REGISTER OPERATION (WRSR, 01h) ................................................................... 52
8.18 READ FUNCTION REGISTER OPERATION (RDFR, 48h) ................................................................. 53
8.19 WRITE FUNCTION REGISTER OPERATION (WRFR, 42h)............................................................... 54
8.20 ENTER QUAD PERIPHERAL INTERFACE (QPI) MODE OPERATION (QPIEN, 35h; QPIDI, F5h) .. 55
8.21 PROGRAM/ERASE SUSPEND & RESUME ........................................................................................ 56
8.22 ENTER DEEP POWER DOWN (DP, B9h) ........................................................................................... 58

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8.23 RELEASE DEEP POWER DOWN (RDPD, ABh) ................................................................................. 59
8.24 SET WRAPPED BURST READ (STWBR, C0h) .................................................................................. 60
8.25 READ PRODUCT IDENTIFICATION (RDID, ABh) .............................................................................. 62
8.26 READ PRODUCT IDENTIFICATION BY JEDEC ID OPERATION (RDJDID, 9Fh; RDJDIDQ, AFh) .. 64
8.27 READ DEVICE MANUFACTURER AND DEVICE ID OPERATION (RDMDID, 90h) .......................... 65
8.31 READ UNIQUE ID NUMBER (RDUID, 4Bh) ........................................................................................ 66
8.32 READ SFDP OPERATION (RDSFDP, 5Ah) ........................................................................................ 67
8.33 NO OPERATION (NOP, 00h) ............................................................................................................... 67
8.34 SOFTWARE RESET (RESET-ENABLE (RSTEN, 66h) AND RESET (RST, 99h)) ............................. 68
8.35 SECURITY INFORMATION ROW ........................................................................................................ 69
8.36 INFORMATION ROW ERASE OPERATION (IRER, 64h) ................................................................... 70
8.37 INFORMATION ROW PROGRAM OPERATION (IRP, 62h) ............................................................... 71
8.38 INFORMATION ROW READ OPERATION (IRRD, 68h) ..................................................................... 72
8.39 SECTOR LOCK/UNLOCK FUNCTIONS .............................................................................................. 73
8.40 IN BAND RESET Operation ................................................................................................................. 75
9.

ELECTRICAL CHARACTERISTICS............................................................................................................. 77
9.1 ABSOLUTE MAXIMUM RATINGS (1) ..................................................................................................... 77
9.2 OPERATING RANGE ............................................................................................................................. 77
9.3 DC CHARACTERISTICS ........................................................................................................................ 78
9.4 AC MEASUREMENT CONDITIONS ...................................................................................................... 79
9.5 PIN CAPACITANCE ............................................................................................................................... 79
9.6 AC CHARACTERISTICS ........................................................................................................................ 80
9.7 SERIAL INPUT/OUTPUT TIMING .......................................................................................................... 81
9.8 POWER-UP AND POWER-DOWN ........................................................................................................ 84
9.9 PROGRAM/ERASE PERFORMANCE (1) ............................................................................................... 85
9.10 RELIABILITY CHARACTERISTICS ..................................................................................................... 85

10.

PACKAGE TYPE INFORMATION ........................................................................................................... 86
10.1 8-Pin JEDEC 208mil Broad Small Outline Integrated Circuit (SOIC) Package (B) .............................. 86
10.2 8-Pin JEDEC 150mil Broad Small Outline Integrated Circuit (SOIC) Package (N) .............................. 87
10.3 8-Pin 150mil VVSOP Package (V)........................................................................................................ 88
10.4 8-Contact Ultra-Thin Small Outline No-Lead (USON) Package 2x3mm (Y) ........................................ 89
10.5 8-Pin TSSOP Package (D) ................................................................................................................... 90
10.6 8-Contact Ultra-Thin Small Outline No-Lead (WSON) Package 6x5mm (K)........................................ 91

11.

ORDERING INFORMATION - Valid Part Numbers................................................................................. 92

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1. PIN CONFIGURATION

CE#

SO (IO1)

1

2

8

Vcc

7

HOLD# (IO3)

WP# (IO2)

3

6

SCK

GND

4

5

SI (IO0)8-pin SOIC 208mil (Package: B)
8-pin SOIC 150mil (Package: N)
8-pin TSSOP (Package: D)
8-pin VVSOP 150mil (Package: V)

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CE#

1

8 Vcc

SO (IO1)

2

7

WP# (IO2)

3

6 SCK

GND

4

5 SI (IO0)

8-pin USON 2x3mm (Package: Y)
8-pin WSON 6x5mm (Package: K)

6

HOLD# (IO3)

IS25LP040E/020E/010E/512E/025E
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2. PIN DESCRIPTIONSSYMBOLTYPE

DESCRIPTION
Chip Enable: The Chip Enable (CE#) pin enables and disables the devices
operation. When CE# is high the device is deselected and output pins are in a highimpedance state. When deselected the devices non-critical internal circuitry power
down to allow minimal levels of power consumption while in a standby state.

CE#

INPUT

When CE# is pulled low the device will be selected and brought out of standby mode.
The device is considered active and instructions can be written to, data read, andwritten to the device. After power-up, CE# must transition from high to low before a
new instruction will be accepted.
Keeping CE# in a high state deselects the device and switches it into its low powerstate. Data will not be accepted when CE# is high.
Serial Data Input, Serial Output, and IOs (SI, SO, IO0, and IO1):

SI (IO0),SO (IO1)INPUT/OUTPUT

This device supports standard SPI, Dual SPI, and Quad SPI operation. Standard SPI
instructions use the unidirectional SI (Serial Input) pin to write instructions,addresses, or data to the device on the rising edge of the Serial Clock (SCK).
Standard SPI also uses the unidirectional SO (Serial Output) to read data or statusfrom the device on the falling edge of the serial clock (SCK).
In Dual and Quad SPI mode, SI and SO become bidirectional IO pins to write
instructions, addresses or data to the device on the rising edge of the Serial Clock(SCK) and read data or status from the device on the falling edge of SCK. Quad SPI
instructions use the WP# and HOLD# pins as IO2 and IO3 respectively.

WP# (IO2)INPUT/OUTPUT

Write Protect/Serial Data IO (IO2): The WP# pin protects the Status Register frombeing written in conjunction with the SRWD bit. When the SRWD is set to “1” and the
WP# is pulled low, the Status Register bits (SRWD, QE, BP3, BP2, BP1, BP0) are
write-protected and vice-versa for WP# high. When the SRWD is set to “0”, the Status
Register is not write-protected regardless of WP# state.
When the QE bit is set to “1”, the WP# pin (Write Protect) function is not available
since this pin is used for IO2.
Hold/Serial Data IO (IO3): Pauses serial communication by the master device
without resetting the serial sequence. When the QE bit of Status Register is set to“1”, HOLD# pin is not available since it becomes IO3.

HOLD# (IO3)

INPUT/OUTPUT

The HOLD# pin allows the device to be paused while it is selected. The HOLD# pin
is active low. When HOLD# is in a low state, and CE# is low, the SO pin will be athigh impedance.
Device operation can resume when HOLD# pin is brought to a high state. When the
QE bit of Status Register is set for Quad I/O, the HOLD# pin function is not available
and becomes IO3 for Multi-I/O SPI mode.

SCK

INPUT

Serial Data Clock: Synchronized Clock for input and output timing operations.

Vcc

POWER

Power: Device Core Power Supply

GND

GROUND

Ground: Connect to ground when referenced to Vcc

NC

UnusedNC: Pins labeled “NC” stand for “No Connect”. Not internally connected.

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3. BLOCK DIAGRAM

Control Logic

High Voltage Generator

StatusRegisterI/O Buffers andData Latches

256 Bytes
Page Buffer

SCK

WP#
(IO2)
SI
(IO0)

SO
(IO1)

Serial Peripheral Interface

CE#

X-Decoder

HOLD#
(IO3)

Y-Decoder

Memory Array

Address Latch &Counter

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4. SPI MODES DESCRIPTION
Multiple IS25LP/WP040E/020E/010E/512E/025E devices can be connected on the SPI serial bus and controlled
by a SPI Master, i.e. microcontroller, as shown in Figure 4.1. The devices support either of two SPI modes:
Mode 0 (0, 0)
Mode 3 (1, 1)
The difference between these two modes is the clock polarity. When the SPI master is in stand-by mode, the serial
clock remains at “0” (SCK = 0) for Mode 0 and the clock remains at “1” (SCK = 1) for Mode 3. Please refer to Figure
4.2 and Figure 4.3 for SPI and QPI mode. In both modes, the input data is latched on the rising edge of Serial Clock(SCK), and the output data is available from the falling edge of SCK.
Figure 4.1 Connection Diagram among SPI Master and SPI Slaves (Memory Devices)

SDO
SPI interface with(0,0) or (1,1)

SDI
SCK
SCK SOSISCK SOSISCK SOSI

SPI Master(i.e. Microcontroller)

CS3

CS2

SPI
MemoryDevice

CS1
CE#

SPI
MemoryDeviceCE#

WP# HOLD#

SPI
MemoryDeviceCE#

WP# HOLD#

WP# HOLD#

Notes:
1. The Write Protect (WP#) and Hold (HOLD#) signals should be driven high or low as necessary.
2. SI and SO pins become bidirectional IO0 and IO1, and WP# and HOLD# pins become IO2 and IO3 respectively during
Multi-IO mode.

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Figure 4.2 SPI Mode Support
CPOL CPHA

Shift in(Mode 0)

0

0

SCK

(Mode 3)

1

1

SCK

SI

MSB INSO

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Shift out

LSB INLSB OUTMSB OUT10

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5. SYSTEM CONFIGURATION
The memory array of IS25LP/WP512E/025E is divided into uniform 4Kbyte sectors or uniform 32Kbyte blocks (ablock consists of eight adjacent sectors). The memory array of IS25LP/WP040E/020E/010E is divided into uniform
4Kbyte sectors or uniform 32/64Kbyte blocks (a block consists of eight/sixteen adjacent sectors respectively).
Note: Optional 1Mb device (Option C) is also divided into uniform 4Kbyte sectors or uniform 32Kbyte blocks.

Table 5.1 illustrates the memory map of the device. The Status Register controls how the memory is protected.
5.1 BLOCK/SECTOR ADDRESSES
Table 5.1 Block/Sector Addresses of IS25LP/WP0512E/025E
MemoryDensity

256Kb

Block No.
(32Kbyte)

Block 0512Kb
Block 1

Sector 0

Sector Size
(Kbyte)4000000h - 000FFFh

Sector 1

4001000h - 001FFFh

:

:

:

Sector 7

4007000h - 007FFFh

Sector 8

4008000h - 008FFFh

Sector 9

4009000h - 009FFFh

:

:

:

Sector 15

400F000h - 00FFFFh

Sector No.

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Address Range

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Table 5.2 Block/Sector Addresses of IS25LP/WP040E/020E/010E
Memory Density

Block No.
(64Kbyte)

Block No.
(32Kbyte)
Block 0Block 0Block 1
1Mb(1)
Block 2Block 1
Block 3
2Mb
Block 4Block 2Block 5Block 6Block 3Block 7
4Mb
Block 8Block 4Block 9Block 10Block 5Block 11Block 12Block 6Block 13Block 14Block 7Block 15

Sector No.

Sector Size
(Kbyte)Address Range

Sector 0

4000000h - 000FFFh

:

:

:

:

:

:

Sector 15

400F000h - 00FFFFh

Sector 16

4010000h - 010FFFh

:

:

:

:

:

:

Sector 31

4

01F000h - 01FFFFh

Sector 32

4020000h - 020FFFh

:

:

:

:

:

:

Sector 47

402F000h - 02FFFFh

Sector 48

4030000h - 030FFFh

:

:

:

:

:

:

Sector 63

403F000h - 03FFFFh

Sector 64

4040000h - 040FFFh

:

:

:

:

:

:

Sector 79

404F000h - 04FFFFh

Sector 80

4050000h - 050FFFh

:

:

:

:

:

:

Sector 95

405F000h - 05FFFFh

Sector 96

4060000h - 060FFFh

:

:

:

:

:

:

Sector 111

406F000h - 06FFFFh

Sector 112

4070000h - 070FFFh

:

:

:

:

:

:

Sector 127

407F000h - 07FFFFh

Note: Optional 1Mb device (Option C) is divided into uniform 4Kbyte sectors or uniform 32Kbyte blocks like

512Kb. Then both D8h and 52h commands are for 32KB Block Erase operation .

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5.2 SERIAL FLASH DISCOVERABLE PARAMETERS
The Serial Flash Discoverable Parameters (SFDP) standard defines the structure of the SFDP database within thememory device. SFDP is the standard of JEDEC JESD216.
The JEDEC-defined header with Parameter ID FF00h and related Basic Parameter Table is mandatory. Additionalparameter headers and tables are optional.
Table 5.2 Signature and Parameter Identification Data Values

Description
SFDP Signature

SFDP Revision
Number of Parameter Headers (NPH)
UnusedParameter ID LSBParameter Minor Revision
Parameter Major Revision
Parameter Table Length (in DWPRDs)
Basic Flash Parameter Table Pointer (PTP)
Parameter ID MSB

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Minor
Major

Address(Byte)
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh

Address
(Bit)
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24

13

Data
53h
46h
44h
50h
06h
01h
00h
FFh
00h
06h
01h
10h
30h
00h
00h
FFh

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Table 5.3 JEDEC Basic Flash Parameter Table

Address(Byte)

Description
Minimum Sector Erase Sizes
Write Granularity
Volatile Status Register Block Protect bits
Write Enable Instruction Select for writing to Volatile Status
RegisterUnused4KB Erase Instruction
Supports (1-1-2) Fast Read
Address Bytes
Supports Double Transfer Rate (DTR) Clocking
Supports (1-2-2) Fast Read
Supports (1-4-4) Fast Read
Supports (1-1-4) Fast Read
UnusedReserved
Flash memory Density (bits)

Flash memory Density (bits)

Flash memory Density (bits)
1-4-4 Fast Read Wait Cycle Count
1-4-4 Fast Read Mode bit Cycle Count
1-4-4 Fast Read Instruction
1-1-4 Fast Read Wait Cycle Count
1-1-4 Fast Read Mode bit Cycle Count
1-1-4 Fast Read Instruction
1-1-2 Fast Read Wait Cycle Count
1-1-2 Fast Read Mode bit Cycle Count
1-1-2 Fast Read Instruction
1-2-2 Fast Read Wait Cycle Count
1-2-2 Fast Read Mode bit Cycle Count
1-2-2 Fast Read Instruction

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4Mb
2Mb
1Mb
512Kb
256Kb

30h

Address
(Bit)
1:0
2
3

Data
01b
1b
1b

4

0b

33h

7:5
15:8
16
18:17
19
20
21
22
23
31:24

111b
20h
1b
00b
0b
1b
1b
1b
1b
FFh

34h
35h
36h
36h
36h
36h
36h
37h

7:0
15:8
23:16
23:16
23:16
23:16
23:16
31:24

FFh
FFh
3Fh
1Fh
0Fh
07h
03h
00h

4:0
7:5
15:8
20:16
23:21
31:24

00100b010b
EBh01000b
000b
6Bh

4:0
7:5
15:8
20:16
23:21
31:24

01000b000b
3Bh00000b
100b
BBh

31h

32h

38h
39h
3Ah
3Bh
3Ch
3Dh
3Eh
3Fh

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Table 5.3 JEDEC Basic Flash Parameter Table (Continued)

Address(Byte)

Description
Supports (2-2-2) Fast Read
Reserved
Supports (4-4-4) Fast Read
Reserved
Reserved

40h

43:41hAddress
(Bit)

Data

0
3:1
4
7:5
31:8

0b
111b
1b
111b
FFFFFFh

15:0
20:16
23:21
31:24

FFFFh
00000b
000b
FFh
FFFFh
00100b010b
EBhReserved
2-2-2 Fast Read Wait Cycle Count
2-2-2 Fast Read Mode bit Cycle Count
2-2-2 Fast Read Instruction

45:44hReserved
4-4-4 Fast Read Wait Cycle Count4-4-4 Fast Read Mode bit Cycle Count4-4-4 Fast Read Instruction

49:48h

4Bh

15:0
20:16
23:21
31:24

Erase Type 1 Size (4KB)
Erase Type 1 Instruction
Erase Type 2 Size (32KB)

4Ch
4Dh
4Eh

7:0
15:8
23:16

0Ch
20h
0Fh

Erase Type 2 Instruction

4Fh

31:24

52h(1)

50h

7:0

51h

15:8

52h
53h

23:16
31:24

10h(2)FFh
D8h(3)
00h
FFh

57:54h

3:0
8:4
10:9
15:11
17:16
22:18
24:23
22:18
24:23
29:25
31:30

0010b
00100b01b00100b01b00000b00b01100b(4)01b(4)
00000b00bErase Type 3 Size (64KB)
Erase Type 3 Instruction

46h
47h

4Ah

256Kb/512Kb/

1Mb 2Mb/4Mb
256Kb/512Kb
1Mb/2Mb/4Mb

Erase Type 4 Size (256KB)
Erase Type 4 Instruction
Multiplier from typical erase time to maximum erase time
Sector Type 1 ERASE time (typ)Sector Type 2 ERASE time (typ)256Kb/512Kb
Sector Type 3 ERASE time (typ)1Mb/2Mb/4Mb
Sector Type 4 ERASE time (typ)00hNotes:
1. D8h can also be used for 32KB block erase in 256Kb/512Kb and optional 1Mb (Option C) device.
2. 00h in optional 1Mb (Option C) device. 3. FFh in optional 1Mb (Option C) device
4. [22:18] = 00000b and [24:23] = 00b in optional 1Mb (Option C) device
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4. Table 5.3 JEDEC Basic Flash Parameter Table (Continued)
Address(Byte)

Description
Multiplier from typical time to maximum time for page or byte
PROGRAM
Page size

58hPage Program Typical time
Byte Program Typical time, first byte

5Ah:59h

Byte Program Typical time, additional byte

Chip Erase, Typical time

Units

4Mb
2Mb
1Mb
512Kb
256Kb
4Mb/2Mb/1Mb
512Kb/256Kb

Suspend in-progress program max latency

3:0

0001b

7:4

1000b

12:8
13
17:14
18
22:19
23

31

00111b
1b
0111b
0b
0000b
0b
00101b00010b00001b01111b01000b
01b
00b
1b

3:0
7:4
8
12:9
17:13

1100b
1110b
1b
0110b
01100b

19:18

10b

23:20
28:24
30:29
31

0110b
01100b
10b
0b

5Bh
30:29

5Ch

5Eh:5Dh

Erase Resume to Suspend Interval
Suspend in-progress erase max latency

Data

28:24

Reserved
Prohibited Operations During Program Suspend
Prohibited Operations During Erase Suspend
Reserved
Program Resume to Suspend Interval

Address(Bit)

5Fh

Suspend /Resume supported
Program Resume Instruction
Program Suspend Instruction
Resume Instruction
Suspend Instruction

60h
61h
62h
63h

7:0
15:8
23:16
31:24

7Ah
75h
7Ah
75h

Reserved
Status Register Polling Device Busy

64h

1:0
7:2

11b
111101b

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Table 5.3 JEDEC Basic Flash Parameter Table (Continued)

Address(Byte)

Description
Exit Deep Power-down to next operation delay

3V
1.8V

Exit Deep Power-down to next operation delay Units
Exit Deep Power-down Instruction
Enter Deep Power-down Instruction
Deep Power-down Supported
4-4-4 mode disable sequences (QPIDI)
4-4-4 mode enable sequences (QPIEN)
0-4-4 Mode Supported
0-4-4 Mode Exit Method
0-4-4 Mode Entry Method:
Quad Enable Requirements (QER)
Hold or RESET Disable
Reserved
Volatile or Non-Volatile Register and Write Enable (WREN)
Instruction for Status Register 1
Reserved
Soft Reset and Rescue Sequence Support
Exit 4-Byte Addressing
Enter 4-Byte Addressing

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Address
(Bit)

14:13
22:15
30:23
31

00010b00100b
01b
ABh
B9h
0b

3:0
8:4
9
15:10
19:16
22:20
23
31:24

1010b
00100b1b110000b
1100b
010b
0b
FFh

6:0

1101000b

7
13:8

1b
110000b110000000
0b10000000b

12:8
67h:65h69h:68h

6Ah
6Bh
6Ch

6Eh:6Dh
6Fh

Data

23:14
31:24

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IS25WP040E/020E/010E/512E/025E
6. REGISTERS
The device has four sets of Registers: Status and Function Register.
6.1 STATUS REGISTER
Status Register Format and Status Register Bit Definitions are described in Table 6.1 & Table 6.2.
Table 6.1 Status Register Format

Default

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SRWD

QE

BP3

BP2

BP1

BP0

WEL

WIP

0

0

0

0

0

0

0

0

Table 6.2 Status Register Bit Definition
Bit

Name

Bit 0

WIP

Bit 1

WEL

Bit 2

BP0

Bit 3

BP1

Bit 4

BP2

Bit 5

BP3

Bit 6

QE

Bit 7

SRWD

Definition
Write In Progress Bit:"0" indicates the device is ready(default)"1" indicates a write cycle is in progress and the device is busy
Write Enable Latch:"0" indicates the device is not write enabled (default)"1" indicates the device is write enabled
Block Protection Bit:"0" indicates the specific blocks are not write-protected (default)"1" indicates the specific blocks are write-protected
Quad Enable bit:“0” indicates the Quad output function disable (default)“1” indicates the Quad output function enable
Status Register Write Disable: (See Table 7.1 for details)"0" indicates the Status Register is not write-protected (default)"1" indicates the Status Register is write-protected

Read/Write

Type

R

Volatile

R/W 1

Volatile

R/W

Non-Volatile

R/W

Non-Volatile

R/W

Non-Volatile

Note1: WEL bit can be written by WREN and WRDI commands, but cannot by WRSR command.

The BP0, BP1, BP2, BP3, QE, and SRWD are non-volatile memory cells that can be written by a Write Status
Register (WRSR) instruction. The default value of the BP0, BP1, BP2, BP3, QE, and SRWD bits were set to “0” atfactory. The Status Register can be read by the Read Status Register (RDSR).
The function of Status Register bits are described as follows:
WIP bit: Write In Progress (WIP) is read-only, and can be used to detect the progress or completion of a Program,
Erase, or Write/Set Non-Volatile/OTP Register operation. WIP is set to “1” (busy state) when the device is executing
the operation. When an operation has completed, WIP is cleared to “0” (ready state) whether the operation is
successful or not and the device is ready for further instructions.
WEL bit: Write Enable Latch (WEL) indicates the status of the internal write enable latch. When WEL is “0”, theinternal write enable latch is disabled and the write operations described in Table 6.3 are inhibited. When WEL is“1”, the Write operations are allowed. WEL bit is set by a Write Enable (WREN) instruction. Each Write Non-Volatile
Register, Program and Erase instruction must be preceded by a WREN instruction. The volatile register relatedcommands such as the Set Volatile Read Register and the Set Volatile Extended Read Register don’t require toset WEL to “1". WEL can be reset by a Write Disable (WRDI) instruction. It will automatically reset after thecompletion of any Write operation.

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Table 6.3 Instructions requiring WREN instruction ahead
Instructions must be preceded by the WREN instruction
Name

Hex Code

Operation

PP

02h

Serial Input Page Program

PPQ

32h/38h

Quad Input Page Program

SER

D7h/20h

Sector Erase 4KB

BER32 (32KB)

52h

Block Erase 32KB

BER64 (64KB)

D8h

Block Erase 64KB

BER32 (32KB)

52h/D8h(2)Block Erase 32KB

BER64 (64KB)

NA

Block Erase 64KB

IS25LP/WP040E/020E/010E(2)IS25LP/WP512E/025E

CER

C7h/60h

Chip Erase

WRSR

01h

Write Non-Volatile Status Register Status Register (1)

WRFR

42h

Write Function Register

IRER

64h

Erase Information Row

IRP

62h

Program Information Row

Note:
1. Optional 1Mb device (Option C) supports only 32KB Block Erase operation with D8h/ 52h command.

BP3, BP2, BP1, BP0 bits: The Block Protection (BP3, BP2, BP1 and BP0) bits are used to define the portion of
the memory area to be protected. Refer to Table 6.4 for the Block Write Protection (BP) bit settings. When a defined
combination of BP3, BP2, BP1 and BP0 bits are set, the corresponding memory area is protected. Any program orerase operation to that area will be inhibited.
SRWD bit: The Status Register Write Disable (SRWD) bit operates in conjunction with the Write Protection (WP#)
signal to provide a Hardware Protection Mode. When the SRWD is set to “0”, the Status Register is not writeprotected. When the SRWD is set to “1” and the WP# is pulled low (V IL), the bits of Status Register (SRWD, QE,
BP3, BP2, BP1, BP0) become read-only, and a WRSR instruction will be ignored. If the SRWD is set to “1” andWP# is pulled high (VIH), the Status Register can be changed by a WRSR instruction.
QE bit: The Quad Enable (QE) allows quad operation. When the QE bit is set to “0”, the pin WP# and HOLD# areenabled. When the QE bit is set to “1”, the IO2 and IO3 pins are enabled.
WARNING: The QE bit must be set to 0 if WP# or HOLD# pin is tied directly to the power supply.

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Table 6.4 Block (64Kbyte) assignment by Block Write Protect (BP) Bits
Status Register Bits

BP Table, Protected Memory Area
4Mb

2Mb

512Kb and
256Kb
0 (None)

BP3

BP2

BP1

BP0

1Mb

0

0

0

0

0 (None)0 (None)0 (None)

0

0

0

1

1(1 block : 7th)

1(1 block : 3rd)

1(1 block : 1st)

0

0

1

0

2(2 blocks : 6th – 7th)

2(2 blocks : 2nd – 3rd)

0

0

1

1

3(4 blocks : 4th – 7th)

3(3 blocks : 1st – 3rd)

0

1

0

0

4(6 blocks : 2nd – 7th)

0

1

0

1

5(7 blocks : 1st – 7th)2~8(2 blocks: All Blocks)

4~8(4 blocks: All Blocks)

0

1

1

0

0

1

1

1

1

0

0

0

1

0

0

1

9(1 block : 0th)9(1 block : 0th)

1

0

1

0

10(2 blocks : 0th – 1st)10(2 blocks : 0th – 1st)

1

0

1

1

11(4 blocks : 0th – 3rd)

11(3 blocks : 0th – 2nd)

1

1

0

0

12(6 blocks : 0th – 5th)

1

1

0

1

13(7 blocks : 0th– 6th)

1

1

1

0

1

1

1

1

14~15
(8 blocks : All Blocks)

6~8(8 blocks: All Blocks)

1~15(All Blocks)
9(1 block : 0th)10~15
(2 blocks : All Blocks)

12~15(4 blocks : All Blocks)

Table 6.5 Optional Block (64Kbyte) assignment by Block Write Protect (BP) Bits (1)Status Register Bits

Protected Memory Area

BP3

BP2

BP1

BP0

4Mb

0

0

0

0

None

None

None

0

0

0

1

1 block : 7

1 block : 3

1 block : 1

0

0

1

0

2 blocks : 6 - 7

2 blocks : 2 - 3

All Blocks

0

0

1

1

4 blocks : 4 - 7

3 blocks : 1 - 3

0

1

0

0

6 blocks : 2 - 7

0

1

0

1

7 blocks : 1 - 7

0

1

1

0

0

1

1

1

1

0

0

0

1

0

0

1

1

0

1

0

7 blocks 0 - 6

1

0

1

1

6 blocks 0 - 5

1

1

0

0

4 blocks 0 - 3

3 blocks : 0 - 2

1

1

0

1

2 blocks : 0 - 1

2 blocks : 0 - 1

1

1

1

0

1 block : 0

1 block : 0

1 block : 0

1

1

1

1

None

None

None

All Blocks

2Mb

All Blocks

1Mb

2 blocks : 0 - 1

512Kb and
256Kb
None

All Blocks

None

Note:
1. Call factory for optional BP Table.

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IS25LP040E/020E/010E/512E/025E
IS25WP040E/020E/010E/512E/025E
Table 6.6 Optional Block (32Kbyte) assignment by Block Write Protect (BP) Bits for 1Mb Option C
Status Register Bits

BP Table, Protected Memory Area

BP3

BP2

BP1

BP0

1Mb

0

0

0

0

0 (None)

0

0

0

1

1(1 block : 3rd)

0

0

1

0

2(2 blocks : 2nd – 3rd)

0

0

1

1

0

1

0

0

0

1

0

1

0

1

1

0

0

1

1

1

1

0

0

0

1

0

0

1

1

0

1

0

1

0

1

1

1

1

0

0

1

1

0

1

1

1

1

0

1

1

1

1

3~15
(4 blocks: All Blocks)

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IS25WP040E/020E/010E/512E/025E
6.2 FUNCTION REGISTER
Function Register Format and Bit definition are described in Table 6.5 and Table 6.6.
Table 6.7 Function Register Format
Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

IRL3

IRL2

IRL1

IRL0

ESUS

PSUS

Reserved

Reserved

0

0

0

0

0

0

0

0

Default

Table 6.8 Function Register Bit Definition
Bit

Name

Definition

Bit 0

Reserved

Reserved

Bit 1

Reserved

Bit 2

PSUS

Bit 3

ESUS

Bit 4

IR Lock 0

Bit 5

IR Lock 1

Bit 6

IR Lock 2

Bit 7

IR Lock 3

Reserved
Program suspend bit:“0” indicates program is not suspend“1” indicates program is suspend
Erase suspend bit:"0" indicates Erase is not suspend"1" indicates Erase is suspend
Lock the Information Row 0:“0” indicates the Information Row can be programmed“1” indicates the Information Row cannot be programmed
Lock the Information Row 1:“0” indicates the Information Row can be programmed“1” indicates the Information Row cannot be programmed
Lock the Information Row 2:“0” indicates the Information Row can be programmed“1” indicates the Information Row cannot be programmed
Lock the Information Row 3:“0” indicates the Information Row can be programmed“1” indicates the Information Row cannot be programmed

Read/WriteR

Reserved

R

Reserved

R

VolatileR

Volatile

R/W

OTP

R/W

OTP

R/W

OTP

R/W

OTP

Type

Note: Once OTP bits of Function Register are written to “1”, it cannot be modified to “0” any more.

PSUS bit: The Program Suspend Status bit indicates when a Program operation has been suspended. The PSUS
changes to “1” after a suspend command is issued during the program operation. Once the suspended Program
resumes, the PSUS bit is reset to “0”.
ESUS bit: The Erase Suspend Status bit indicates when an Erase operation has been suspended. The ESUS bit
is “1” after a suspend command is issued during an Erase operation. Once the suspended Erase resumes, theESUS bit is reset to “0”.
IR Lock bit 0 ~ 3: The default is “0” so that the Information Row can be programmed. If the bit set to “1”, theInformation Row can’t be programmed. Once it set to “1”, it cannot be changed back to “0” since IR Lock bits are
OTP.

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IS25WP040E/020E/010E/512E/025E
7. PROTECTION MODE
The device supports hardware and software write-protection mechanisms.
7.1 HARDWARE WRITE PROTECTION
The Write Protection (WP#) pin provides a hardware write protection method for BP3, BP2, BP1, BP0, SRWD, and
QE in the Status Register. Refer to the section 6.1 STATUS REGISTER.
Write inhibit voltage (VWI) is specified in the section 9.8 POWER-UP AND POWER-DOWN. All write sequence willbe ignored when Vcc drops to VWI.
Table 7.1 Hardware Write Protection on Status Register
SRWD

WP#

Status Register0

Low

Writable

1

Low

Protected

0High

Writable

1

High

WritableNote: Before the execution of any program, erase or write Status Register instruction, the Write Enable Latch (WEL)
bit must be enabled by executing a Write Enable (WREN) instruction. If the WEL bit is not enabled, the program,erase or write register instruction will be ignored.

7.2 SOFTWARE WRITE PROTECTION
The device also provides a software write protection feature. The Block Protection (BP3, BP2, BP1, BP0) bits allow
part or the whole memory area to be write-protected.

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8. DEVICE OPERATION
The device utilizes an 8-bit instruction register. Refer to Table 8.1. Instruction Set for details on instructions andinstruction codes. All instructions, addresses, and data are shifted in with the most significant bit (MSB) first on
Serial Data Input (SI) or Serial Data IOs (IO0, IO1, IO2, IO3 ). The input data on SI or IOs is latched on the risingedge of Serial Clock (SCK) after Chip Enable (CE#) is driven low (V IL). Every instruction sequence starts with a
one-byte instruction code and is followed by address bytes, data bytes, or both address bytes and data bytes,
depending on the type of instruction. CE# must be driven high (V IH) after the last bit of the instruction sequence has
been shifted in to end the operation.
Table 8.1 Instruction Set(1)Instruction
Name

Operation

Mode

Byte0

Byte1

Byte2

Byte3

Byte4

NORD

Normal Read
Mode

SPI

03h

A
<23:16>A<15:8>

A<7:0>

Data out

SPI

0Bh

A
<23:16>A<15:8>

A
<7:0>

Dummy

Data out

FRD

Fast Read
Mode

QPI

0Bh

A
<23:16>
A<23:16>Dual

A<15:8>
A<15:8>
Dual

A
<7:0>
A
<7:0>
Dual

Dummy

Dummy

Dummy
(AXh(2))

Dual
Data outA<23:16>A<15:8>

A
<7:0>

Dummy

Dummy

A
<23:16>
A<23:16>
Quad
A<23:16>A<15:8>
A<15:8>
Quad
A<15:8>

A
<7:0>
A
<7:0>
Quad
A
<7:0>

Dummy

Quad
Data out

Dummy(AXh(2))

Dummy

FRDIO

Fast Read
Dual I/O

SPI

BBh

FRDO

Fast Read
Dual Output

SPI

3Bh

FRQO

Fast Read
Quad Output

SPI

6Bh

FRQIO

Fast Read
Quad I/O

SPI
QPI

EBh

PP

Input Page
Program

SPI
QPI

02h

PPQ

Quad Input
Page Program

SPI

32h
38h

A
<23:16>A<15:8>

A
<7:0>

SER

Sector Erase

SPI
QPI

D7h
20h

A
<23:16>A<15:8>

A
<7:0>

BER32
(32KB)

Block Erase
32KbyteSPI
QPI

52h(1)

A<23:16>A<15:8>

A
<7:0>

BER64
(64KB)

Block Erase
64KbyteSPI
QPI

D8h(1)

A<23:16>A<15:8>

A
<7:0>

CER

Chip Erase

SPI
QPI

C7h
60h

WREN

Write Enable

SPI
QPI

06h

WRDI

Write Disable

SPI
QPI

04h

RDSR

Read Status
Register

SPI
QPI

05h

SR

WRSR

Write Status
Register

SPI
QPI

01h

WSR
Data

Byte5

Byte6

Byte7

Dummy

Data out

Dual
Data out

Dummy
PD(256byte)
Quad PD(256byte)

Note: 1. In 256Kb/512Kb, both 52h and D8h command are for 32KB ERASE only.

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Quad
Data out

Byte8

IS25LP040E/020E/010E/512E/025E
IS25WP040E/020E/010E/512E/025E
Instruction
Name

Operation

Mode

Byte0

Byte1

RDFR

Read Function
Register

SPI
QPI

48h

Data
out

WRFR

Write Function
Register

SPI
QPI

42h

WFR
Data

QPIEN

Enter
QPI mode

SPI

35h

QPIDI

Exit
QPI mode

QPI

F5h

PERSUS

Suspend during
program/erase

SPI
QPI

75h
B0h

PERRSM

Resumeprogram/erase

SPI
QPI

7Ah
30h

DP

Deep Power
Down

SPI
QPI

B9h

RDPD

ReleasePower Down

SPI
QPI

ABh

RDID

Read ID

SPI
QPI

ABh

Read JEDECID Command

SPI

RDJDID

RDMDIDRDUID

RDSFDP

Read
Manufacturer& Device ID

Read
Unique ID

Byte2

Byte3

Byte4

Dummy

Dummy

Dummy

ID7-ID0

9Fh

MF7MF0

ID15ID8

ID7-ID0

QPI

AFh

MF7MF0

ID15ID8

ID7-ID0

SPI
QPI

A<23:16>= 00h

A<15:8>= 00h

00h

MF7-MF0ID7-ID090h

01h

ID7-ID0

MF7MF0

SPI

4Bh

A(3)
<23:16>A(3)<15:8>

A(3)
<7:0>

Dummy

Data out

QPI

4Bh

A(3)
<23:16>A(3)<15:8>

A(3)
<7:0>

Dummy

Dummy

SPI

5Ah

A
<7:0>
A
<7:0>
Quad

Data out

5Ah

A<15:8>
A<15:8>
Quad

Dummy

QPI

A
<23:16>
A<23:16>
Quad

Dummy

Dummy

SFDP ReadNOPNo Operation

SPI
QPI

00h

RSTEN

SoftwareReset
Enable

SPI
QPI

66h

RST

Software Reset

SPI
QPI

99h

SPI
QPI

64h

A
<23:16>A<15:8>

A
<7:0>

SPI
QPI

62h

A
<23:16>A<15:8>

A<7:0>

A<23:16>
A<23:16>
Quad
STWBR
Data

A
<15:8>
A<15:8>
Quad

A
<7:0>
A
<7:0>
Quad

IRER

IRP

IRRD

STWBR

Erase
Information
Row
ProgramInformation
Row
Read
Information
Row

SPI

68h

QPI

68h

Set Wrapped
Burst Read

SPI
QPI

C0h

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Byte5

Byte6

Byte7

Dummy

Data out

Dummy

Dummy

Dummy

Quad
Data outPD(256byte)
Dummy

Data out

Dummy

Dummy

25

Byte8

Quad
Data outIS25LP040E/020E/010E/512E/025E
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Notes:
1. The number of dummy cycles for read operation is fixed like below.

Command

InstructionAddress-Data

Dummy
CyclesFast Read (SPI mode)

0Bh

1-1-1

8

Fast Read (QPI mode)

0Bh

4-4-4

6

Fast Read Dual Output

3Bh

1-1-2

8

Fast Read Dual IO SPI

BBh

1-2-2

4

Fast Read Quad Output

6Bh

1-1-4

8

Fast Read Quad IO (SPI mode)

EBh

1-4-4

6

Fast Read Quad IO (QPI mode)

EBh

4-4-4

6

Operation

Comment
RDUID, IRRD instructions have same
dummy cycles with Fast Read operation.

2. AXh has to be counted as a part of dummy cycles. X means “don’t care”.
3. A<23:9> are “don’t care” and A<8:4> are always “0”.

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8.1 NORMAL READ OPERATION (NORD, 03h)
The NORMAL READ (NORD) instruction is used to read memory contents at a maximum frequency of 50MHz.
The NORD instruction code is transmitted via the SI line, followed by three address bytes (A23 - A0) of the firstmemory location to be read. A total of 24 address bits are shifted in, but only AVMSB (Valid Most Significant Bit) - A0
are decoded. The remaining bits (A23 – AVMSB+1) are ignored. The first byte addressed can be at any memory
location. Upon completion, any data on the SI will be ignored. Refer to Table 8.2 for the related Address Key.
The first byte data (D7 - D0) is shifted out on the SO line, MSB first. A single byte of data, or up to the whole memory
array, can be read out in one NORMAL READ instruction. The address is automatically incremented by one after
each byte of data is shifted out. The read operation can be terminated at any time by driving CE# high (VIH) after
the data comes out. When the highest address of the device is reached, the address counter will roll over to the000000h address, allowing the entire memory to be read in one continuous READ instruction.
If the NORMAL READ instruction is issued while an Erase, Program or Write operation is in process (WIP=1) the
instruction is ignored and will not have any effects on the current operation .
Table 8.2 Address Key
Address
AVMSB–A0

4Mb
A18-A0 (A23A19=X)

2Mb
A17-A0 (A23A18=X)

1Mb
A16-A0 (A23A17=X)

512Kb
A15-A0 (A23A16=X)

256Kb
A14-A0 (A23A15=X)

Note: X=Don’t Care

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Figure 8.1 Normal Read Sequence
CE #Mode 3 0

1

2

3

4

5

7

6

8

9

10

...

28

29

30

31

SCK
Mode 03-byte AddressSI

Instruction = 03h

23

22

21

...

3

2

1

0

41

42

43

44

45

46

47

...

High Impedance

SO

CE #
32

33

34

35

36

37

39

38

40

SCK

SI

Data Out 1
SO
tV

7

6

5

4

3

Data Out 2
2

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0

7

6

5

4

3

2

0

1

28

...

IS25LP040E/020E/010E/512E/025E
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8.2 FAST READ OPERATION (FRD, 0Bh)
The FAST READ (FRD) instruction is used to read memory data at up to a 104MHz clock.
The FAST READ instruction code is followed by three address bytes (A23 - A0) transmitted via the SI line, witheach bit latched-in during the rising edge of SCK. Then the first data byte from the address is shifted out on the SO
line after 6 dummy cycles, with each bit shifted out at a maximum frequency f CT, during the falling edge of SCK.
The first byte addressed can be at any memory location. The address is automatically incremented by one after
each byte of data is shifted out. When the highest address is reached, the address counter will roll over to the000000h address, allowing the entire memory to be read with a single FAST READ instruction. The FAST READ
instruction is terminated by driving CE# high (VIH).
If the FAST READ instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the instruction
is ignored without affecting the current cycle.
Figure 8.2 Fast Read Sequence
CE #Mode 3 0

1

2

3

4

5

6

8

7

9

10

...

28

29

30

31

SCK
Mode 03-byte AddressSI

Instruction = 0Bh

23

22

21

...

3

2

1

0

41

42

43

44

45

46

47

...

High Impedance

SO

CE #
32

33

34

35

36

37

38

39

40

SCK

SI

Dummy Cycles

Data Out

tV
SO

7

6

5

4

3

2

0

1

...

Note: Dummy cycles depends on Read Parameter setting. Detailed information in Table 6.11 Read Dummy Cycles.

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FAST READ OPERATION IN QPI MODE (FRD, 0Bh)
The FAST READ (FRD) instruction is used also in QPI mode to read memory data at up to a 104MHz clock.
The FAST READ instruction code (2 clocks) is followed by three address bytes (A23-A0 — 6 clocks), transmitted
via the IO3, IO2, IO1 and IO0 lines, with each bit latched-in during the rising edge of SCK. Then the first data byte
addressed is shifted out on the IO3, IO2, IO1 and IO0 lines after 6 dummy cycles, with each bit shifted out at a
maximum frequency fCT, during the falling edge of SCK.
The first byte addressed can be at any memory location. The address is automatically incremented by one after
each byte of data is shifted out. When the highest address is reached, the address counter will roll over to the000000h address, allowing the entire memory to be read with a single FAST READ instruction. The FAST READ
instruction in QPI mode is terminated by driving CE# high (VIH).
If the FAST READ instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the instruction
is ignored without affecting the current cycle.
The Fast Read sequence in QPI mode is also applied to the commands in the following table 8.3.
Table 8.3 Address Key
Instruction Name
FRQIO
RDUID
IRRD

Operation
Fast Read Quad I/O
Read Unique ID
Read Information Row

Hex Code
EBh
4Bh
68h

Figure 8.3 Fast Read Sequence In QPI Mode
CE#

Mode 3 0

1

2

3

4

5

6

7

8

9

...

13

14

15

16

17

...

SCK
Mode 0tV
IO[3:0]0Bh
Instruction

23:20 19:16 15:12 11:8
3-byte Address

7:4

3:0

7:4
6 Dummy Cycles

3:0

Data 1

7:4

3:0

...

Data 2

Note: Number of dummy cycles depends on Read Parameter setting. Detailed information in Table 6.11 Read Dummy
Cycles.

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8.3 HOLD OPERATIONHOLD# is used in conjunction with CE# to select the device. When the device is selected and a serial sequence isunderway, HOLD# can be used to pause the serial communication with the master device without resetting theserial sequence. To pause, HOLD# is brought low while the SCK signal is low. To resume serial communication,
HOLD# is brought high while the SCK signal is low (SCK may still toggle during HOLD). Inputs to SI will be ignored
while SO is in the high impedance state, during HOLD.
Note: HOLD# is not supported with QE=1.

Timing graph can be referenced in AC Parameters Figure 9.4.
8.4 FAST READ DUAL I/O OPERATION (FRDIO, BBh)
The FRDIO allows the address bits to be input two bits at a time. This may allow for code to be executed directlyfrom the SPI in some applications.
The FRDIO instruction code is followed by three address bytes (A23 – A0) transmitted via the IO1 and IO0 lines,
with each pair of bits latched-in during the rising edge of SCK. The address MSB is input on IO1, the next bit on
IO0, and this shift pattern continues to alternate between the two lines. Depending on the usage of AX read
operation mode, a mode byte may be located after address input.
The first data byte addressed is shifted out on the IO1 and IO0 lines after 4 dummy cycles, with each pair of bits
shifted out at a maximum frequency f CT, during the falling edge of SCK. The MSB is output on IO1, while
simultaneously the second bit is output on IO0. Figure 8.4 illustrates the timing sequence.
The first byte addressed can be at any memory location. The address is automatically incremented by one after
each byte of data is shifted out. When the highest address is reached, the address counter will roll over to the000000h address, allowing the entire memory to be read with a single FRDIO instruction. FRDIO instruction is
terminated by driving CE# high (VIH).
The device supports the AX read operation by applying mode bits during dummy period. Mode bits consist of 8bits, such as M7 to M0. Four cycles after address input are reserved for Mode bits in FRDIO execution. M7 to M4
are important for enabling this mode. M3 to M0 become don’t care for future use. When M[7:4]=1010(Ah), it enables
the AX read operation and subsequent FRDIO execution skips command code. It saves cycles as described in
Figure 8.5. When the code is different from AXh (where X is don’t care), the device exits the AX read operation.
After finishing the read operation, device becomes ready to receive a new command. SPI or QPI mode configuration
retains the prior setting. Mode bit must be applied during dummy cycles. The dummy cycles are 4 cycles, data
output will start right after mode bit is applied.
If the FRDIO instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the instruction is
ignored and will not affect the current cycle.

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Figure 8.4 Fast Read Dual I/O Sequence (with command decode cycles)
CE #Mode 3 0

1

2

3

4

5

7

6

8

9

10

...

18

19

20

21

SCK
Mode 04 Dummy Cycles

3-byte Address
IO0

Instruction = BBh

22

20

18

...

2

0

6

4

23

21

19

...

3

1

7

5

High Impedance

IO1

Mode Bits
CE #

22

23

24

25

26

27

29

28

30

31

32

33

34

35

36

37

...

SCK

tV
IO0

2

0

6

4

2

0

6

Data Out 1

IO1

3

1

7

5

3

4

2

0

6

Data Out 2

1

7

5

3

4

2

0

6

4

...

1

7

5

...

Data Out 3
1

7

5

3

Mode Bits

Notes:
1. If the mode bits=AXh (where X is don’t care), it can execute the AX read mode (without command). When the mode
bits are different from AXh, the device exits the AX read operation.
2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.11 Read Dummy Cycles.
3. Sufficient dummy cycles are required to avoid I/O contention. If the number of dummy cycles and AX bit cycles are
same, then X should be Hi-Z.

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Figure 8.5 Fast Read Dual I/O AX Read Sequence (without command decode cycles)
CE #Mode 3 0

1

2

3

...

11

12

13

14

15

16

17

18

19

20

...

21

SCK
Mode 04 Dummy Cycles

3-byte AddresstV

Data Out 2

Data Out 1

IO0

22

20

18

...

2

0

6

4

2

0

6

4

2

0

6

4

...

IO1

23

21

19

...

3

1

7

5

3

1

7

5

3

1

7

5

...

Mode Bits

Notes:
1. If the mode bits=AXh (where X is don’t care), it will keep executing the AX read mode (without command). When themode bits are different from AXh, the device exits the AX read operation.

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8.5 FAST READ DUAL OUTPUT OPERATION (FRDO, 3Bh)
The FRDO instruction is used to read memory data on two output pins each at up to a 104MHz clock.
The FRDO instruction code is followed by three address bytes (A23 – A0) transmitted via the IO0 line, and each bit
latched-in during the rising edge of SCK. Then the first data byte addressed is shifted out on the IO1 and IO0 lines
after 8 dummy cycles, with each pair of bits shifted out at a maximum frequency fCT, during the falling edge of SCK.
The first bit (MSB) is output on IO1. Simultaneously, the second bit is output on IO0.
The first byte addressed can be at any memory location. The address is automatically incremented by one after
each byte of data is shifted out. W hen the highest address is reached, the address counter will roll over to the000000h address, allowing the entire memory to be read with a single FRDO instruction. The FRDO instruction is
terminated by driving CE# high (VIH).
If the FRDO instruction is issued while an Erase, Program or Write cycle is in process (BUSY=1) the instruction is
ignored and will not have any effects on the current cycle.
Figure 8.6 Fast Read Dual Output Sequence
CE #Mode 3 0

1

2

3

4

5

7

6

8

9

10

...

28

29

30

31

SCK
Mode 03-byte Address
IO0

Instruction = 3Bh

23

22

21

...

3

2

1

0

41

42

43

44

45

46

47

...

High Impedance

IO1

CE #

32

33

34

35

36

37

38

39

40

SCK

tV
IO0

6

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0

6

Data Out 1

8 Dummy Cycles
IO1

4

7

5

3

4

2

0

...

1

...

Data Out 2
1

7

5

3

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8.6 FAST READ QUAD OUTPUT OPERATION (FRQO, 6Bh)
The FRQO instruction is used to read memory data on four output pins each at up to a 104 MHz clock.
The FRQO instruction code is followed by three address bytes (A23 – A0), transmitted via the IO0 line, and each
bit latched-in during the rising edge of SCK. Then the first data byte addressed is shifted out on the IO3, IO2,
IO1 and IO0 lines after 8 dummy cycles, with each group of four bits shifted out at a maximum frequency fCT,
during the falling edge of SCK. The first bit (MSB) is output on IO3, while simultaneously the second bit is output
on IO2, the third bit is output on IO1, etc.
The first byte addressed can be at any memory location. The address is automatically incremented after eachbyte of data is shifted out. When the highest address is reached, the address counter will roll over to the 000000h
address, allowing the entire memory to be read with a single FRQO instruction. FRQO instruction is termin atedby driving CE# high (VIH).
If a FRQO instruction is issued while an Erase, Program or Write cycle is in process (BUSY=1) the instruction is
ignored and will not have any effects on the current cycle.

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Figure 8.7 Fast Read Quad Output Sequence
CE #Mode 3 0

1

2

3

4

5

7

6

8

9

10

...

28

29

30

31

SCK

Mode 03-byte Address
IO0

Instruction = 6Bh

23

22

21

...

3

2

1

0

41

42

43

44

45

46

47

...

High Impedance

IO1

High Impedance

IO2

High Impedance

IO3

CE #

32

33

34

35

36

37

38

39

40

SCK

tV
IO0

4
8 Dummy Cycles

0

4

0

4

0

4

0

...

Data Out 1 Data Out 2 Data Out 3 Data Out 4

IO1

5

1

5

1

5

1

5

1

...

IO2

6

2

6

2

6

2

6

2

...

IO3

7

3

7

3

7

3

7

3

...

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8.7 FAST READ QUAD I/O OPERATION (FRQIO, EBh)The FRQIO instruction allows the address bits to be input four bits at a time. This may allow for code to be executed
directly from the SPI in some applications.
The FRQIO instruction code is followed by three address bytes (A23 – A0), transmitted via the IO3, IO2, IO1 andIO0 lines, and each group of four bits latched-in during the rising edge of SCK. The address of MSB inputs on IO3,
the next bit on IO2, the next bit on IO1, the next bit on IO0, and continue to shift in alternating on the four. Dependingon the usage of AX read operation mode, a mode byte may be located after address input.
The first data byte addressed is shifted out on the IO3, IO2, IO1 and IO0 lines after 6 dummy cycles, with eachgroup of four bits shifted out at a maximum frequency f CT, during the falling edge of SCK. The first bit (MSB) is
output on IO3, while simultaneously the second bit is output on IO2, the third bit is output on IO1, etc. Figure 8.8
illustrates the timing sequence.
The first byte addressed can be at any memory location. The address is automatically incremented after each byteof data is shifted out. When the highest address is reached, the address counter will roll over to the 000000h
address, allowing the entire memory to be read with a single FRQIO instruction. FRQIO instruction is terminatedby driving CE# high (VIH).
The device supports the AX read operation by applying mode bits during dummy period. Mode bits consist of 8bits, such as M7 to M0. Two cycles after address input are reserved for Mode bits in FRQIO execution. M7 to M4
are important for enabling this mode. M3 to M0 become don’t care for future use. When M[7:4]=1010(Ah), it enables
the AX read operation and subsequent FRQIO execution skips command code. It saves cycles as described in
Figure 8.9. When the code is different from AXh (where X is don’t care), the device exits the AX read operation.
After finishing the read operation, device becomes ready to receive a new command. SPI or QPI mode configuration
retains the prior setting.
If the FRQIO instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the instruction is
ignored and will not have any effects on the current cycle.

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Figure 8.8 Fast Read Quad I/O Sequence (with command decode cycles)
CE #Mode 3 0

1

2

3

4

5

7

6

8

9

10

11

12

13

14

15

SCK
Mode 03-byte Address
IO0

20

16

12

8

4

0

4

0

21

17

13

9

5

1

5

1

IO2

22

18

14

10

6

2

6

2

IO3

23

19

15

11

7

3

7

3

Instruction = EBhHigh Impedance

IO1

Mode Bits
CE #

16

17

18

19

20

21

23

22

24

25

26

27

28

29

30

31

...

SCK

6 Dummy Cycles

tV Data Out 1 Data Out 2 Data Out 3 Data Out 4 Data Out 5 Data Out 6

IO0

4

0

4

0

4

0

4

0

4

0

4

0

...

IO1

5

1

5

1

5

1

5

1

5

1

5

1

...

6

2

6

2

6

2

6

2

6

2

6

2

...

7

3

7

3

7

3

7

3

7

3

7

3

...

IO2

IO3

Note:
1. If the mode bits=AXh (where X is don’t care), it can execute the AX read mode (without command). When the mode
bits are different from AXh, the device exits the AX read operation.

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Figure 8.9 Fast Read Quad I/O AX Read Sequence (without command decode cycles)
CE #Mode 3 0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

...

SCK
Mode 06 Dummy Cycles

3-byte AddresstV

Data Out 1 Data Out 2

IO0

20

16

12

8

4

0

4

0

4

0

4

0

...

IO1

21

17

13

9

5

1

5

1

5

1

5

1

...

IO2

22

18

14

10

6

2

6

2

6

2

6

2

...

IO3

23

19

15

11

7

3

7

3

7

3

7

3

...

Mode Bits

Note:
1. If the mode bits=AXh (where X is don’t care), it will keep executing the AX read mode (without command). When themode bits are different from AXh, the device exits the AX read operation.

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FAST READ QUAD I/O OPERATION IN QPI MODE (FRQIO, EBh)The FRQIO instruction is also used in QPI mode to read memory data at up to a 104MHz clock.
The FRQIO instruction in QPI mode utilizes all four IO lines to input the instruction code so that only two clocks are
required, while the FRQIO instruction in SPI mode requires that the byte-long instruction code is shifted into thedevice only via IO0 line in eight clocks. As a result, 6 command cycles will be reduced by the FRQIO instruction in
QPI mode.
The first data byte addressed is shifted out on the IO3, IO2, IO1 and IO0 lines after 6 dummy cycles, with eachgroup of four bits shifted out at a maximum frequency f CT, during the falling edge of SCK.
The device supports the AX read operation by applying mode bits during dummy period. Mode bits consist of 8bits, such as M7 to M0. Two cycles after address input are reserved for Mode bits in FRQIO execution. M7 to M4
are important for enabling this mode. M3 to M0 become don’t care for future use. When M[7:4]=1010(Ah), it enables
the AX read operation and subsequent FRQIO execution skips command code. When the code is different fromAXh (where X is don’t care), the device exits the AX read operation.
After finishing the read operation, device becomes ready to receive a new command. SPI or QPI mode configuration
retains the prior setting.
If the FRQIO instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the instruction is
ignored and will not have any effects on the current cycle.
Figure 8.10 Fast Read Quad I/O Sequence in QPI Mode
CE#
Mode 3 0

1

2

3

4

5

6

7

8

9

...

13

14

15

16

17

...

SCK
Mode 0Mode Bits

IO[3:0]EBh
Instruction

23:20 19:16 15:12 11:8
3-byte Address

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7:4

3:0

7:4

3:0

6 Dummy Cycles

tV
7:4

3:0

Data 1

7:4

3:0

Data 240...

IS25LP040E/020E/010E/512E/025E
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8.8 PAGE PROGRAM OPERATION (PP, 02h)
The Page Program (PP) instruction allows up to 256 bytes data to be programmed into memory in a single
operation. The destination of the memory to be programmed must be outside the protected memory area set by
the Block Protection (BP3, BP2, BP1, BP0) bits. A PP instruction which attempts to program into a page that iswrite-protected will be ignored. Before the execution of PP instruction, the Write Enable Latch (WEL) must be
enabled through a Write Enable (WREN) instruction.
The PP instruction code, three address bytes and program data (1 to 256 bytes) are input via the Sl line. Program
operation will start immediately after the CE# is brought high, otherwise the PP instruction will not be executed.
The internal control logic automatically handles the programming voltages and timing. The progress or completionof the program operation can be determined by reading the WIP bit in Status Register via a RDSR instruction. If
the WIP bit is “1”, the program operation is still in progress. If WIP bit is “0”, the program operation has completed.
If more than 256 bytes data are sent to a device, the address counter rolls over within the same page, the previously
latched data are discarded, and the last 256 bytes are kept to be programmed into the page. The starting byte canbe anywhere within the page. When the end of the page is reached, the address will wrap around to the beginningof the same page. If the data to be programmed are less than a full page, the data of all other bytes on the same
page will remain unchanged.
Note: A program operation can alter “1”s into “0”s. The same byte location or page may be programmed more thanonce, to incrementally change “1”s to “0”s. An erase operation is required to change “0”s to “1”s.

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Figure 8.11 Page Program Sequence in SPI Mode

1

...

7

8

9

...

31

32

33

...

39

...

...

2079

Mode 3 0

2072

CE #

SCK
Mode 0SI

3-byte Address
Instruction = 02h

23

22

...

Data In 1

Data In 256

0

7

6

...

0

...

7

...

0

High ImpedanceSO

Figure 8.12 Page Program Sequence in QPI Mode
CE#
Mode 3 0

1

5

6

7

8

9

10

11

12

13

14

15

...

23:20 19:16 15:12 11:8

7:4

3:0

7:4

3:0

7:4

3:0

7:4

3:0

7:4

3:0

...

2

3

4

SCK
Mode 0IO[3:0]02h

3-byte Address

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Data In 2

Data In 3

Data In 4

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8.9 QUAD INPUT PAGE PROGRAM OPERATION (PPQ, 32h/38h)
The Quad Input Page Program instruction allows up to 256 bytes data to be programmed into memory in a single
operation with four pins (IO0, IO1, IO2 and IO3). The destination of the memory to be programmed must be outside
the protected memory area set by the Block Protection (BP3, BP2, BP1, BP0) bits. A Quad Input Page Program
instruction which attempts to program into a page that is write-protected will be ignored. Before the execution of
Quad Input Page Program instruction, the QE bit in the Status Register must be set to “1” and the Write Enable
Latch (WEL) must be enabled through a Write Enable (WREN) instruction.
The Quad Input Page Program instruction code, three address bytes and program data (1 to 256 bytes) are input
via the four pins (IO0, IO1, IO2 and IO3). Program operation will start immediately after the CE# is brought high,otherwise the Quad Input Page Program instruction will not be executed. The internal control logic automaticallyhandles the programming voltages and timing. The progress or completion of the program operation can be
determined by reading the WIP bit in Status Register via a RDSR instruction. If the WIP bit is “1”, the program
operation is still in progress. If WIP bit is “0”, the program operation has completed.
If more than 256 bytes data are sent to a device, the address counter rolls over within the same page, the previously
latched data are discarded, and the last 256 bytes data are kept to be programmed into the page. The starting byte
can be anywhere within the page. When the end of the page is reached, the address will wrap around to thebeginning of the same page. If the data to be programmed are less than a full page, the data of all other bytes on
the same page will remain unchanged.
Note: A program operation can alter “1”s into “0”s. The same byte location or page may be programmed more thanonce, to incrementally change “1”s to “0”s. An erase operation is required to change “0”s to “1”s.

Figure 8.13 Quad Input Page Program Sequence
CE #Mode 3 0

1

2

3

4

5

6

7

8

9

...

31

32

33

34

35

...

SCK
Mode 03-byte Address

Data In 1

Data In 2

4

0

4

0

...

5

1

5

1

...

IO2

6

2

6

2

...

IO3

7

3

7

3

...

IO0

IO1

Instruction = 32h/38hHigh ImpedanceIntegrated Silicon Solution, Inc.- www.issi.com
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22

...

0

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8.10 ERASE OPERATIONThe Erase command sets all bits in the addressed sector or block to “1”s.
The memory array of the 512Kb/256Kb (IS25LP/WP512E/025E) is organized into uniform 4Kbyte sectors or
32Kbyte uniform blocks (a block consists of eight adjacent sectors).
The memory array of the 4Mb/2Mb/1Mb (IS25LP/WP040E/020E/010E) is organized into uniform 4Kbyte sectors or
32/64Kbyte uniform blocks (a block consists of eight/sixteen adjacent sectors respectively).
In order to erase the device, there are three erase instructions available: Sector Erase (SER), Block Erase (BER)
and Chip Erase (CER). A sector erase operation allows any individual sector to be erased without affecting thedata in other sectors. A block erase operation erases any individual block. A chip erase operation erases the wholememory array of a device. A sector erase, block erase or chip erase operation can be executed prior to any
programming operation.

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8.11 SECTOR ERASE OPERATION (SER, D7h/20h)
A Sector Erase (SER) instruction erases a 4 Kbyte sector before the execution of a SER instruction, the Write
Enable Latch (WEL) must be set via a Write Enable (WREN) instruction. The WEL bit is automatically reset after
the completion of Sector Erase operation.
A SER instruction is entered, after CE# is pulled low to select the device and stays low during the entire instruction
sequence The SER instruction code, and three address bytes are input via SI. Erase operation will start immediately
after CE# is pulled high. The internal control logic automatically handles the erase voltage and timing.
The progress or completion of the erase operation can be determined by reading the WIP bit in the Status Register
using a RDSR instruction.
If the WIP bit is “1”, the erase operation is still in progress. If the WIP bit is “0”, the erase operation has been
completed.
Figure 8.14 Sector Erase Sequence In SPI Mode
CE #Mode 3 0

1

2

3

4

5

6

7

8

9

10

...

28

29

30

31

1

0

SCK
Mode 03-byte Address
SI

SO

Instruction = D7h/20h

23

22

21

...

4

5

6

7

7:4

3:0

3

2

High Impedance

Figure 8.15 Sector Erase Sequence In QPI Mode
CE#
Mode 3 0

1

2

3

SCK
Mode 0IO[3:0]3-byte Address
D7h/20h

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8.12 BLOCK ERASE OPERATION (BER32K:52h or 52h/D8h, BER64K:D8h)
A Block Erase (BER) instruction erases a 32/64Kbyte block. Before the execution of a BER instruction, the Write
Enable Latch (WEL) must be set via a Write Enable (WREN) instruction. The WEL is reset automatically after thecompletion of a block erase operation.
In 256Kb/512Kb (IS25LP/WP512E/025E), there is a 32KB block only, both 52h and D8h are for BER32K command.
But in 4Mb/2Mb/1Mb (IS25LP/WP040E/020E/010E), there are 32KB block and 64KB block, so 52h is for BER32K
command, and D8h is for BER64K command.
The BER instruction code and three address bytes are input via SI. Erase operation will start immediately after theCE# is pulled high, otherwise the BER instruction will not be executed. The internal control logic automaticallyhandles the erase voltage and timing.
Figure 8.16 Block Erase (64KB) Sequence In SPI Mode
CE #Mode 3 0

1

2

3

4

5

6

7

8

9

10

...

28

29

30

31

2

1

0

SCK
Mode 03-byte Address
SI

SO

Instruction = D8h

23

22

21

...

4

5

6

7

7:4

3:0

3

High Impedance

Figure 8.17 Block Erase (64KB) Sequence In QPI Mode
CE#
Mode 3 0

1

2

3

SCK
Mode 0IO[3:0]3-byte Address
D8h

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Figure 8.18 Block Erase (32KB) Sequence In SPI Mode
CE #Mode 3 0

1

2

3

4

5

6

7

8

9

10

...

28

29

30

31

2

1

0

SCK
Mode 03-byte Address
SI

SO

Instruction = 52h

23

22

21

...

4

5

6

7

7:4

3:0

3

High Impedance

Figure 8.19 Block Erase (32KB) Sequence In QPI Mode
CE#

Mode 3 0

1

2

3

SCK
Mode 0IO[3:0]3-byte Address
52h

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8.13 CHIP ERASE OPERATION (CER, C7h/60h)
A Chip Erase (CER) instruction erases the entire memory array. Before the execution of CER instruction, the Write
Enable Latch (WEL) must be set via a Write Enable (WREN) instruction. The WEL is automatically reset after
completion of a chip erase operation.
The CER instruction code is input via the SI. Erase operation will start immediately after CE# is pulled high,otherwise the CER instruction will not be executed. The internal control logic automatically handles the erase
voltage and timing.

Figure 8.20 Chip Erase Sequence In SPI Mode
CE#

Mode 3

0

1

2

3

4

5

6

7

SCK
Mode 0SI

Instruction = C7h/60h

SOHigh Impedance

Figure 8.21 Chip Erase Sequence In QPI Mode
CE#
Mode 3 01

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8.14 WRITE ENABLE OPERATION (WREN, 06h)
The Write Enable (WREN) instruction is used to set the Write Enable Latch (WEL) bit. The WEL bit is reset to thewrite-protected state after power-up. The WEL bit must be write enabled before any write operation, including
Sector Erase, Block Erase, Chip Erase, Page Program, Program Information Row, Write Non-Volatile Status
Register, and Write Function Register operations except for Write Volatile Status Register.
The WEL bit will be reset to the write-protected state automatically upon completion of a write operation. The
WREN instruction is required before any above operation is executed.

Figure 8.22 Write Enable Sequence In SPI Mode
CE#

Mode 3

0

1

2

3

4

5

6

7

SCK
Mode 0Instruction = 06h

SI

High ImpedanceSO

Figure 8.23 Write Enable Sequence In QPI Mode
CE#
Mode 3 01

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8.15 WRITE DISABLE OPERATION (WRDI, 04h)
The Write Disable (WRDI) instruction resets the WEL bit and disables all write instructions. The WRDI instruction
is not required after the execution of a write instruction, since the WEL bit is automatically reset.
Figure 8.24 Write Disable Sequence In SPI Mode
CE#

Mode 3

0

1

2

3

4

5

6

7

SCK
Mode 0Instruction = 04h

SI

High ImpedanceSO

Figure 8.25 Write Disable Sequence In QPI Mode
CE#
Mode 3 01

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8.16 READ STATUS REGISTER OPERATION (RDSR, 05h)
The Read Status Register (RDSR) instruction provides access to the Status Register. During the execution of aprogram, erase or write Status Register operation, RDSR instruction can be used to check the progress orcompletion of an operation by reading the WIP bit of Status Register.
Figure 8.26 Read Status Register Sequence In SPI Mode
CE #Mode 3 0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

SCK
Mode 0SI

Instruction = 05htVSO

Data Out
7

6

5

4

3

2

1

Figure 8.27 Read Status Register Sequence In QPI Mode
CE#

Mode 3 0

1

2

3

SCK
Mode 0tV
IO[3:0]

05h

7:4

3:0

Data Out

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8.17 WRITE STATUS REGISTER OPERATION (WRSR, 01h)
The Write Status Register (WRSR) instruction allows the user to enable or disable the block protection and Status
Register write protection features by writing “0”s or “1”s into the volatile/non-volatile BP3, BP2, BP1, BP0, and
SRWD bits. Also WRSR instruction allows the user to disable or enable quad operation by writing “0” or “1” into thevolatile/non-volatile QE bit.
To write Status Register bits, a standard Write Enable (06h) instruction must previously have been executed forthe device to accept Write Status Register (01h) instruction (Status Register bit WEL must equal 1).
Figure 8.28 Write Status Register Sequence In SPI Mode
CE #Mode 3 0

1

2

3

4

5

7

6

8

9

10

11

12

13

14

15

2

1

0

SCK
Mode 0

Data InSI

SO

Instruction = 01h

7

6

2

3

7:4

3:0

5

4

3

High Impedence

Figure 8.29 Write Status Register Sequence In QPI Mode
CE#
Mode 3 01

SCKMode 0IO[3:0]01h

Data In

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8.18 READ FUNCTION REGISTER OPERATION (RDFR, 48h)
The Read Function Register (RDFR) instruction provides access to the Function Register.
Figure 8.30 Read Function Register Sequence In SPI Mode
CE #Mode 3 0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

SCK
Mode 0SI

Instruction = 48htVSO

Data Out
7

6

5

4

3

2

1

Figure 8.31 Read Function Register Sequence In QPI Mode
CE#

Mode 3 0

1

2

3

SCK
Mode 0tV
IO[3:0]

48h

7:4

3:0

Data Out

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8.19 WRITE FUNCTION REGISTER OPERATION (WRFR, 42h)
Information Row Lock bits (IRL3~IRL0) can be set to “1” individually by WRFR instruction in order to lock
Information Row. Since IRL bits are OTP, once it is set to “1”, it cannot set back to “0” again.
Before the execution of a WRFR instruction, the Write Enable Latch (WEL) must be set via a Write Enable (WREN)
instruction. The WEL is reset automatically after the completion of a write function register operation.

Figure 8.32 Write Function Register Sequence In SPI Mode
CE #Mode 3 0

1

2

3

4

5

7

6

8

9

10

11

12

13

14

15

2

1

0

SCK
Mode 0

Data InSI

SO

Instruction = 42h

7

6

5

4

3

High Impedence

Figure 8.33 Write Function Register QPI Sequence In QPI Mode
CE#
Mode 3 0

1

2

3

7:4

3:0

SCK
Mode 0IO[3:0]42h

Data In

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8.20 ENTER QUAD PERIPHERAL INTERFACE (QPI) MODE OPERATION (QPIEN, 35h; QPIDI, F5h)
The Enter Quad Peripheral Interface (QPIEN) instruction, 35h, enables the Flash device for QPI bus operation.
Upon completion of the instruction, all instructions thereafter will be 4-bit multiplexed input/output until a power
cycle or an Exit Quad Peripheral Interface instruction is sent to device.
The Exit Quad Peripheral Interface (QPIDI) instruction, F5h, resets the device to 1-bit SPI protocol operation. To
execute an Exit Quad Peripheral Interface operation, the host drives CE# low, sends the QPIDI instruction, thendrives CE# high. The device just accepts QPI (2 clocks) command cycles.
Figure 8.34 Enter Quad Peripheral Interface (QPI) Mode Sequence
CE#

Mode 3

0

1

2

3

4

5

6

7

SCK
Mode 0Instruction = 35h

SIHigh ImpedanceSO

Figure 8.35 Exit Quad Peripheral Interface (QPI) Mode Sequence
CE#
Mode 3 01

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8.21 PROGRAM/ERASE SUSPEND & RESUME
The device allows the interruption of Sector Erase, Block Erase, or Page Program operations to conduct otheroperations. 75h/B0h command for suspend and 7Ah/30h for resume will be used. (SPI/QPI all acceptable) Function
Register bit2 (PSUS) and bit3 (ESUS) are used to check whether or not the device is in suspend mode.
Suspend to read ready timing (tSUS): 100µs (TYP)
Resume to another suspend timing (tRS): 80µs (TYP)

SUSPEND DURING SECTOR-ERASE OR BLOCK-ERASE (PERSUS 75h/B0h)
The Suspend command allows the interruption of Sector Erase and Block Erase operations. But Suspend command
will be ignored during Chip Erase operation. After the Suspend command, other commands include array read
operation can be accepted.
But Write Status Register command (01h) and Erase instructions are not allowed during Erase Suspend. Also,array read for being erased sector/block is not allowed.
To execute Erase Suspend operation, the host drives CE# low, sends the Suspend command cycle (75h/B0h),then drives CE# high. The Function Register indicates that the Erase has been suspended by setting the ESUS bitfrom “0” to “1”, but the device will not accept another command until it is ready. To determine when the device will
accept a new command, poll the WIP bit or wait the specified time t SUS. When ESUS bit is set to “1”, the Write
Enable Latch (WEL) bit clears to “0”.
SUSPEND DURING PAGE PROGRAMMING (PERSUS 75h/B0h)
The Suspend command also allows the interruption of all array Program operations. After the Suspend command,
other commands include array read operation can be accepted can be accepted.
But Write Status Register instruction (01h) and Program instructions are not allowed during Program Suspend.
Also, array read for being programmed page is not allowed.
To execute the Program Suspend operation, the host drives CE# low, sends the Suspend command cycle(75h/B0h), then drives CE# high. The Function Register indicates that the programming has been suspended by
setting the PSUS bit from “0” to “1”, but the device will not accept another command until it is ready. To determine
when the device will accept a new command, poll the WIP bit or wait the specified time t SUS. When PSUS bit is set
to “1”, the Write Enable Latch (WEL) bit clears to “0”.

PROGRAM/ERASE RESUME (PERRSM 7Ah/30h)
The Program/Erase Resume restarts the Program or Erase command that was suspended, and clears the suspend
status bit in the Function Register (ESUS or PSUS bits) to “0”. To execute the Program/Erase Resume operation,
the host drives CE# low, sends the Program/Erase Resume command cycle (7Ah/30h), then drives CE# high. A
cycle is two nibbles long, most significant nibble first. To issue another Erase Suspend operation after Erase
Resume operation, Erase Resume to another Erase Suspend delay (tRS) is required, but it could require longer
Erase time to complete Erase operation.
To determine if the internal, self-timed Write operation completed, poll the WIP bit.

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Table 8.4 Instructions accepted during Suspend
Instruction Allowed

Operation
SuspendedName

Hex Code

Program or Erase

NORD

03h

Read Data Bytes from Memory at Normal Read Mode

Program or Erase

FRD

0Bh

Read Data Bytes from Memory at Fast Read Mode

Program or Erase

FRDIO

BBh

Fast Read Dual I/O

Program or Erase

FRDO

3Bh

Fast Read Dual Output

Program or Erase

FRQIO

EBh

Fast Read Quad I/O

Program or Erase

FRQO

6Bh

Fast Read Quad Output

Program or Erase

WREN

06h

Write Enable

Program or Erase

WRDI

04h

Write Disable

Program or Erase

WRSR

01h

Write Volatile Status Register

Erase

PP (1)

02h

Serial Input Page ProgramErase

PPQ (1)32h/38h

Quad Input Page Program

Program or Erase

RDSR

05h

Read Status Register

Program or Erase

RDFR

48h

Read Function Register

Program or Erase

PERRSM

7Ah/30hErase

PERRSM

75h/B0h

Program or Erase

RDID

ABh

Program/Erase Resume
Program/Erase Suspend (to suspend program operation inanother block during Erase suspend)
Read Manufacturer and Product ID

Program or Erase

RDJDID

9Fh

Read JEDEC ID

Program or Erase

RDJDIDQ

AFh

Read JEDEC ID in QPI mode

Program or Erase

RDMDID

90h

Read Manufacturer and Device ID

Program or Erase

RDUID

4Bh

Read Unique ID Number

Program or Erase

RDSFDP

5Ah

SFDP Read

Program or Erase

NOP

00h

No Operation

Program or Erase

RSTEN

66h

Software reset enable

Program or Erase

RST

99h

Reset (Only along with 66h)

Program or Erase

IRRD

68h

Read Information Row

Erase

SECUNLOCK26h

Sector Unlock

Erase

SECLOCK

24h

Sector Lock

Program or Erase

QPIEN

35h

Enter QPI mode

Program or Erase

QPIDI

F5h

Exit QPI mode

Program or Erase

STWBR

C0h

Set Wrapped Burst Read

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8.22 ENTER DEEP POWER DOWN (DP, B9h)
The Deep Power-down (DP) instruction is for setting the device on the minimizing the power consumption (enter
into Power-down mode). During this mode, standby current is reduced from Isb1 to Isb2. While in the Power-down
mode, the device is not active and all Write/Program/Erase instructions are ignored. The instruction is initiated bydriving the CE# pin low and shifting the instruction code into the device. The CE# pin must be driven high after the
instruction has been latched, or Power-down mode will not engage. Once CE# pin driven high, the Power-down
mode will be entered within the time duration of tDP. While in the Power-down mode only the Release from Powerdown/RDID instruction, which restores the device to normal operation, will be recognized. All other instructions are
ignored, including the Read Status Register instruction which is always available during normal operation. Ignoring
all but one instruction makes the Power Down state a useful condition for securing maximum write protection. It isavailable in both SPI and QPI mode.
Figure 8.36 Enter Deep Power Down Mode Sequence In SPI MOde

tDP

CE #

Mode 3 0

1

2

3

4

5

6

7

SCK
Mode 0SI

SO

Instruction = B9h

High Impedance

Figure 8.37 Enter Deep Power Down Mode Sequence In QPI Mode

tDP

CE#
Mode 3 01

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8.23 RELEASE DEEP POWER DOWN (RDPD, ABh)
The Release Deep Power-down/Read Device ID instruction is a multi-purpose command. To release the device
from the Power-down mode, the instruction is issued by driving the CE# pin low, shifting the instruction code “ABh”
and driving CE# high.
Releasing the device from Power-down mode will take the time duration of tRES1 before normal operation is restored
and other instructions are accepted. The CE# pin must remain high during the tRES1 time duration. If the Release
Deep Power-down/RDID instruction is issued while an Erase, Program or Write cycle is in progress (WIP=1) the
instruction is ignored and will not have any effects on the current cycle.
Figure 8.38 Release Deep Power Down Mode Sequence In SPI Mode

tRES1

CE #

Mode 3 0

1

2

3

4

5

6

7

SCK
Mode 0SI

SO

Instruction = ABh

High Impedance

Figure 8.39 Release Deep Power Down Mode Sequence In QPI Mode

tRES1

CE#
Mode 3 01

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8.24 SET WRAPPED BURST READ (STWBR, C0h)

The device is capable of wrapped burst read operation in both SPI and QPI mode.
Wrapped burst read and the size of burst length are set by using C0h instruction like below:
C0h command is followed by 1 byte data, and wrapped burst and burst length are set like below table:
Data

Wrap Around

Burst Length

10h

Yes

8-byte11h

Yes

16-byte12hYes

32-byte13hYes

64-byte

0Xh

No

X

By default, address increases by one up through the entire array (Linear Burst). By setting the burst length, thedata being accessed can be limited to the length of burst boundary within a 256 byte page, with random initialaddress. The first output will be the data at the initial address which is specified in the instruction. Following data
will come out from the next address within the burst boundary. Once the address reaches the end of boundary, it
will automatically move to the first address of the boundary. CE# high will terminate read operation.
For example, if burst length of 8 and initial address being applied is 0h, following byte output will be from address
00h and continue to 01h,..,07h, 00h, 01h… until CE# terminates the operation. If burst length of 8 and initial address
being applied is FEh(254d), following byte output will be from address FEh and continue to FFh, F8h, F9h, FAh,
FBh, FCh, FDh, and repeat from FEh until CE# terminates the operation.
To exit the wrapped burst mode, it is required to issue another “C0h” command with data = 1Xh. Otherwise,
wrapped burst read mode will be maintained until either power down or reset operation.
To change burst length, it is required to issue another “C0h” command with 1 byte data.
Figure 8.40 Set Wrapped Burst Read Sequence In SPI Mode

CE #Mode 3 0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

2

1

0

SCK
Mode 0SI

SO

Data In
Instruction = C0h

7

6

5

4

3

High Impedence

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Figure 8.41 Set Wrapped Burst Read Sequence In QPI Mode
CE#
Mode 3 0

1

2

3

7:4

3:0

SCK
Mode 0IO[3:0]C0h

Data In

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8.25 READ PRODUCT IDENTIFICATION (RDID, ABh)
The Release from Power-down/Read Device ID instruction is a multi-purpose instruction. It can support both SPI
and QPI modes. The Read Product Identification (RDID) instruction is for reading out the old style of 8-bit Electronic
Signature, whose values are shown as table of Product Identification.
The RDID instruction code is followed by three dummy bytes, each bit being latched-in on SI during the rising SCK
edge. Then the Device ID is shifted out on SO with the MSB first, each bit been shifted out during the falling edgeof SCK. The RDID instruction is ended by driving CE# high. The Device ID (ID7-ID0) outputs repeatedly if additional
clock cycles are continuously sent to SCK while CE# is at low.
Table 8.5 Product Identification
Manufacturer ID(MF7-MF0)

ISSI Serial Flash

9Dh

Instruction

ABh

90h

Part Number

Device ID (ID7-ID0)

9Fh
Memory Type + Capacity(ID15-ID0)

IS25LP040E

12h

4013h

IS25LP020E

11h

4012h

IS25LP010E

10h

4011h

IS25LP512E

05h

4010h

IS25LP025E

02h

4009h

IS25WP040E

12h

7013h

IS25WP020E

11h

7012h

IS25WP010E

10h

7011h

IS25WP512E

05h

7010h

IS25WP025E

02h

7009h

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Figure 8.42 RDID (Read Product Identification) Sequence In SPI Mode
CE #Mode 3 0

1

...

7

8

9

...

31

32

33

...

39

SCK

Mode 0SI

Instruction = ABh

3 Dummy Bytes

Data OuttV

Device ID(ID7-ID0)SO

Figure 8.43 RDID (Read Product Identification) Sequence In QPI Mode
CE#
Mode 3 0

1

2

3

4

5

6

7

8

9

SCK
Mode 0tV
IO[3:0]ABh

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8.26 READ PRODUCT IDENTIFICATION BY JEDEC ID OPERATION (RDJDID, 9Fh; RDJDIDQ, AFh)
The JEDEC ID READ instruction allows the user to read the manufacturer and product ID of devices. Refer to Table
8.5 Product Identification for Manufacturer ID and Device ID. After the JEDEC ID READ command (9Fh in SPI
mode, AFh in QPI mode) is input, the Manufacturer ID is shifted out MSB first followed by the 2-byte electronic ID(ID15-ID0) that indicates Memory Type and Capacity, one bit at a time. Each bit is shifted out during the fallingedge of SCK. If CE# stays low after the last bit of the 2-byte electronic ID, the Manufacturer ID and 2-byte electronic
ID will loop until CE# is pulled high.
Figure 8.44 RDJDID (Read JEDEC ID In SPI Mode) Sequence
CE #Mode 3 0

1

...

7

8

9

15

...

16

17

...

23

24

25

...

SCK
Mode 0SI

Instruction = 9FhtVManufacturer ID(MF7-MF0)SO

Capacity(ID7-ID0)

Memory Type
(ID15-ID8)

Figure 8.45 RDJDID and RDJDIDQ DJDIDQ (Read JEDEC ID In QPI Mode) Sequence
CE#

Mode 3 0

1

2

3

4

5

6

7

SCK

Mode 0IO[3:0]tV
9Fh/AFh

7:4

3:0

MF7-MF0

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3:0

ID15-ID8

7:4

3:0

ID7-ID064

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8.27 READ DEVICE MANUFACTURER AND DEVICE ID OPERATION (RDMDID, 90h)
The Read Device Manufacturer and Device ID (RDMDID) instruction allows the user to read the Manufacturer andproduct ID of devices. Refer to Table 8.5 Product Identification for Manufacturer ID and Device ID. The RDMDID
instruction code is followed by two dummy bytes and one byte address (A7~A0), each bit being latched-in on SI
during the rising edge of SCK. If one byte address is initially set as A0 = 0, then the Manufacturer ID is shifted out
on SO with the MSB first followed by the Device ID (ID7- ID0). Each bit is shifted out during the falling edge of SCK.
If one byte address is initially set as A0 = 1, then Device ID will be read first followed by the Manufacturer ID. The
Manufacturer and Device ID can be read continuously alternating between the two until CE# is driven high.
Figure 8.46 RDMDID (Read Product Identification) Sequence In SPI Mode
CE #Mode 3 0

1

...

7

8

9

...

31

32

33

...

39

40

41

...

47

SCK

Mode 0SI

Instruction = 90h

3-byte AddresstV

Device ID(ID7-ID0)

Manufacturer ID(MF7-MF0)SO

Notes:
1. ADDRESS A0 = 0, will output the 1-byte Manufacturer ID (MF7-MF0) → 1-byte Device ID (ID7-ID0)
ADDRESS A0 = 1, will output the 1-byte Device ID (ID7-ID0) → 1-byte Manufacturer ID (MF7-MF0)
2. The Manufacturer and Device ID can be read continuously and will alternate from one to the other until CE# pin ispulled high.

Figure 8.47 RDMDID (Read Product Identification) Sequence In QPI Mode
CE#
Mode 3 0

1

2

3

4

5

6

7

8

9

10

11

SCK
Mode 0tV

IO[3:0]90h

23:20 19:16 15:12 11:8

Instruction

3-byte Address

7:4

3:0

7:4

3:0

7:4

3:0

Manufacturer Device ID
ID (MF7-MF0) (ID7-ID0)

Notes:
1. ADDRESS A0 = 0, will output the 1-byte Manufacturer ID (MF7-MF0) → 1-byte Device ID (ID7-ID0)
ADDRESS A0 = 1, will output the 1-byte Device ID (ID7-ID0) → 1-byte Manufacturer ID (MF7-MF0)
2. The Manufacturer and Device ID can be read continuously and will alternate from one to the other until CE# pin ispulled high.

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8.31 READ UNIQUE ID NUMBER (RDUID, 4Bh)
The Read Unique ID Number (RDUID) instruction accesses a factory-set read-only 16-byte number that is uniqueto the device. The ID number can be used in conjunction with user software methods to help prevent copying or
cloning of a system. The RDUID instruction is instated by driving the CE# pin low and shifting the instruction code(4Bh) followed by 3 address bytes and dummy cycles (configurable, default is 8 clocks). After which, the 16-byte
ID is shifted out on the falling edge of SCK as shown below. As a result, the sequence of RDUID instruction is sameas FAST READ. RDUID QPI sequence is also same as FAST READ QPI except for the instruction code. Refer tothe FAST READ QPI operation.
Note: 16 bytes of data will repeat as long as CE# is low and SCK is toggling.

Figure 8.48 RDUID Sequence In SPI Mode
CE #Mode 3 0

1

...

7

8

9

...

31

32

33

...

39

40

41

...

47

SCK
Mode 0SI

Instruction = 4Bh

3 Byte Address

Dummy Cycles
tV

SO

Data Out

A[23:10]A[9:4]

A[3:0]XX

00000

0h Byte address

XX

00000

1h Byte address

XX

00000

2h Byte address

XX

00000

…

Table 8.6 Unique ID Addressing

XX

00000

Fh Byte address

Note: XX means “don’t care”.

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8.32 READ SFDP OPERATION (RDSFDP, 5Ah)
The Serial Flash Discoverable Parameters (SFDP) standard provides a consistent method of describing thefunctions and features of serial Flash devices in a standard set of internal parameter tables. These parameters canbe interrogated by host system software to enable adjustments needed to accommodate divergent features frommultiple vendors. For more details please refer to the JEDEC Standard JESD216 (Serial Flash Discoverable
Parameters).
The sequence of issuing RDSFDP instruction in SPI mode is:CE# goes low → Send RDSFDP instruction (5Ah) → Send 3 address bytes on SI pin → 8 dummy cycles on SI pin→ Read SFDP code on SO → End RDSFDP operation by driving CE# high at any time during data out. Refer to
ISSI’s Application note for SFDP table. The data at the addresses that are not specified in SFDP table are
undefined.
RDSFDP Sequence in QPI mode, has 8 dummy cycles before SFDP code, too.
Figure 8.49 RDSFDP (Read SFDP) Sequence In SPI Mode
CE #Mode 3 0

1

...

7

8

9

...

31

32

33

...

39

40

41

...

47

...

SCK
Mode 0SI

Instruction = 5Ah

3 Byte Address

8 Dummy Cycles
tV

SO

Data Out8.33 NO OPERATION (NOP, 00h)
The No Operation command solely cancels a Reset Enable command and has no impact on any other commands.
It is available in both SPI and QPI modes. To execute a NOP, the host drives CE# low, sends the NOP command
cycle (00H), then drives CE# high.

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8.34 SOFTWARE RESET (RESET-ENABLE (RSTEN, 66h) AND RESET (RST, 99h)
The Reset operation is used as a system (software) reset that puts the device in normal operating mode. This
operation consists of two commands: Reset-Enable (RSTEN) and Reset (RST). The Reset operation requires theReset-Enable command followed by the Reset command. Any command other than the Reset command after the
Reset-Enable command will disable the Reset-Enable.
Execute the CE# pin low → sends the Reset-Enable command (66h), and drives CE# high. Next, the host drives
CE# low again, sends the Reset command (99h), and drives CE# high.
The Software Reset during an active Program or Erase operation aborts the operation, which can result in
corrupting or losing the data of the targeted address range. Depending on the prior operation, the reset timing mayvary. Recovery from a Write operation requires more latency time than recovery from other operations.
Note: The non-volatile Status Register and Function Register remain unaffected by Software RESET.

Figure 8.50 Software Reset Enable and Software Reset Sequence In SPI Mode (RSTEN, 66h + RST, 99h)
CE#
Mode 3 0

1

2

3

4

5

6

7

8

9

10

11

12

13

SCK
Mode 0SI

Instruction = 66h

Instruction = 99h

High ImpedanceSO

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Figure 8.51 Software Reset Enable and Software Reset Sequence In QPI Mode (RSTEN, 66h + RST, 99h)
CE#
Mode 3 0

1

0

1

SCK
Mode 0IO[3:0]99h

66h8.35 SECURITY INFORMATION ROW
The security Information Row is comprised of an additional 4 x 256 bytes of programmable information. The security
bits can be reprogrammed by the user. Any program security instruction issued while an erase, program or write
cycle is in progress is rejected without having any effect on the cycle that is in progress.
Table 8.7 Information Row Valid Address Range
Address Assignment
IRL0 (Information Row Lock0)
IRL1
IRL2
IRL3

A[23:16]
00h
00h
00h
00h

A[15:8]
00h
10h
20h
30h

A[7:0]
Byte address
Byte address
Byte address
Byte address

Bit 7~4 of the Function Register is used to permanently lock the programmable memory array.
When Function Register bit IRLx = “0”, the 256 bytes of the programmable memory array can be programmed.
When Function Register bit IRLx = “1”, the 256 bytes of the programmable memory array function as read only.

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8.36 INFORMATION ROW ERASE OPERATION (IRER, 64h)
Information Row Erase (IRER) instruction erases the data in the Information Row x (x: 0~3) array. Prior to theoperation, the Write Enable Latch (WEL) must be set via a Write Enable (WREN) instruction. The WEL bit isautomatically reset after the completion of the operation.
The sequence of IRER operation: Pull CE# low to select the device → Send IRER instruction code → Send threeaddress bytes → Pull CE# high. CE# should remain low during the entire instruction sequence. Once CE# is pulled
high, Erase operation will begin immediately. The internal control logic automatically handles the erase voltage andtiming.
Figure 8.52 IRER (Information Row Erase) Sequence
CE #Mode 3 0

1

2

3

4

5

6

7

8

9

10

...

28

29

30

31

1

0

SCK
Mode 03-byte Address
SI

SO

Instruction = 64h

23

22

21

...

3

2

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8.37 INFORMATION ROW PROGRAM OPERATION (IRP, 62h)
The Information Row Program (IRP) instruction allows up to 256 bytes data to be programmed into the memory ina single operation. Before the execution of IRP instruction, the Write Enable Latch (WEL) must be enabled througha Write Enable (WREN) instruction.
The IRP instruction code, three address bytes and program data (1 to 256 bytes) should be sequentially input.
Three address bytes has to be input as specified in the Table 8.7 Information Row Valid Address Range. Program
operation will start once the CE# goes high, otherwise the IRP instruction will not be executed. The internal control
logic automatically handles the programming voltages and timing. The progress or completion of the program
operation can be determined by reading the WIP bit in Status Register via a RDSR instruction. If the WIP bit is “1”,the program operation is still in progress. If WIP bit is “0”, the program operation has completed.
If more than 256 bytes data are sent to a device, the address counter rolls over within the same page. The
previously latched data are discarded and the last 256 bytes data are kept to be programmed into the page. The
starting byte can be anywhere within the page. When the end of the page is reached, the address will wrap aroundto the beginning of the same page. If the data to be programmed are less than a full page, the data of all otherbytes on the same page will remain unchanged.
Note: A program operation can alter “1”s into “0”s, but an erase operation is required to change “0”s back to “1”s. A
byte cannot be reprogrammed without first erasing the corresponding Information Row array which is one of
IR0~3.

Figure 8.53 IRP (Information Row Program) Sequence

1

...

7

8

9

...

31

32

33

...

39

...

...

2079

Mode 3 0

2072

CE #

SCK

Mode 0SISO

3-byte Address
Instruction = 62h

23

22

...

Data In 1
0

7

6

...

Data In 256
0

...

7

...

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8.38 INFORMATION ROW READ OPERATION (IRRD, 68h)
The IRRD instruction is used to read memory data at up to a 104MHz clock.
The IRRD instruction code is followed by three address bytes (A23 - A0), transmitted via the SI line, and each bit
latched-in during the rising edge of SCK. Then the first data byte addressed is shifted out on the SO line after 8
dummy cycles in SPI mode ( 6 dummy cycles in QPI mode), with each bit shifted out at a maximum frequency f CT,
during the falling edge of SCK.
The address is automatically incremented by one after each byte of data is shifted out. Once the address reaches
the last address of each 256 byte Information Row, the next address will not be valid and the data of the address
will be garbage data. It is recommended to repeat four times IRRD operation that reads 256 byte with a valid starting
address of each Information Row in order to read all data in the 4 x 256 byte Information Row array. The IRRD
instruction is terminated by driving CE# high (VIH).
If an IRRD instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the instruction is
ignored and will not have any effects on the current cycle.

Figure 8.54 IRRD (Information Row Read) Sequence
CE #Mode 3

0

1

...

7

8

9

...

31

32

33

...

39

40

41

...

47

SCK

Mode 0SI

Instruction = 68h

3 Byte Address

Dummy Cycles
tV

SO

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8.39 SECTOR LOCK/UNLOCK FUNCTIONSSECTOR UNLOCK OPERATION (SECUNLOCK, 26h)
The Sector Unlock command allows the user to select a specific sector to allow program and erase operations.
This instruction is effective when the blocks are designated as write-protected through the BP0, BP1, BP2, andBP3 bits in the Status Register. Only one sector can be enabled at any time. To enable a different sector, apreviously enabled sector must be disabled by executing a Sector Lock command. The instruction code is followed
by a 24-bit address specifying the target sector, but A0 through A11 are not decoded. The remaining sectors within
the same block remain as read-only.
Figure 8.55 Sector Unlock Sequence In SPI Mode
CE #Mode 3 0

1

2

3

4

5

6

7

8

9

10

...

28

29

30

31

1

0

SCK
Mode 03-byte Address

SI

SO

Instruction = 26h

23

22

21

...

4

5

6

7

7:4

3:0

3

2

High Impedance

Figure 8.56 Sector Unlock QPI Sequence In QPI Mode
CE#
Mode 3 0

1

2

3

SCK
Mode 0Instruction
IO[3:0]26h

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SECTOR LOCK OPERATION (SECLOCK, 24h)
The Sector Lock command relocks a sector that was previously unlocked by the Sector Unlock command. The
instruction code does not require an address to be specified, as only one sector can be enabled at a time. The
remaining sectors within the same block remain in read-only mode.
Figure 8.57 Sector Lock Sequence In SPI Mode
CE#

Mode 3

0

1

2

3

4

5

6

7

SCK

Mode 0Instruction = 24h

SIHigh ImpedanceSO

Figure 8.58 Sector Lock QPI Sequence In QPI Mode
CE#
Mode 3 01

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8.40 IN BAND RESET OPERATION
The device offers an additional feature of In-Band RESET function, which uses existing SPI signals to initiate a
hardware reset, which is different from existing software reset/hardware reset (dedicated RESET# pin);-

Existing software reset commands often depend on the Flash being in a particular mode before they are effective. This
makes software based reset sequences depend on slave device and mode.
Dedicated RESET# pin requires additional pin over traditional 8-pins of SPI Flash device. Also it requires 1 more signal forreset operation.

In Band-RESET operation requires 2-signal pins; CE# and IO0.
•
•
•
•
•
•

CE# is driven active low to select the SPI slave (note1)
Clock (SCK) remains stable in either a high or low state ….(note 2)
SI (DQ0) is driven low by the bus master, simultaneously with CE# going active low……(note 3)
CE# is driven inactive … (note 4)
Repeat the above 4 steps, each time alternating the state of SI (IO0).
After the fourth CE# pulse, the slave triggers its internal reset……..(note 5)

Note 1
Note 2
Note 3Note 4Note 5This powers up the SPI slave
This prevents any confusion with a command, as no command bits are transferred (clocked)
No SPI bus slave drives SI (IO0) during CE# low before a transition of clock. Slave streaming output active is
not allowed until after the first edge of clock.
The slave captures the state of SI on the rising edge of CE#
SI (IO0) is low on the first CE#, high on the second, low on the third,
high on the fourth … (This provides a 5th, unlike random noise)

NOTE:
This reset sequence is not intended to be used at normal power on, but to be used only when the device is not
responding to the system. This reset sequence will be operational from any state that the device may be in. During thereset process, the device will ignore any chip select (command). Once the sequence is completed the device will
respond to normal operation e.g: provide a SFDP response.

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Figure 8.59 Timing for In-Band RESET Operation

Mode 3
SCK

Mode 0

tCSL

tCSH

tSU

tHD

CE#

tHD

tSU

SI (IO0)
SI = LOW

SI = LOW

SI = HIGH

SI = HIGH

High-ZSO(IO1)

100 msInternal ResetParameter

Symbol

Min

Max

Units

CE# Low Pulse
CE# High Pulse
Setup Time
Hold Time

tCSL
tCSH
tSU
tHD

500
500
5
5

-----

ns
ns
ns
ns

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9. ELECTRICAL CHARACTERISTICS
9.1 ABSOLUTE MAXIMUM RATINGS (1)Storage Temperature-65°C to +150°C

Surface Mount Lead Soldering TemperatureStandard Package

240°C 3 Seconds

Lead-free Package

260°C 3 Seconds

Input Voltage with Respect to Ground on All Pins

-0.5V to VCC + 0.5V

All Output Voltage with Respect to Ground
VCC-0.5V to VCC + 0.5V
IS25LP-0.5V to +6.0V

IS25WP-0.5V to +2.5V

Notes:
1. Applied conditions greater than those listed in “Absolute Maximum Ratings” may cause permanent damage to thedevice. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. ANSI/ESDA/JEDEC JS-001

9.2 OPERATING RANGE
Ambient Operating Temperature
VCC Power Supply

Extended Grade E-40°C to 105°C

Automotive Grade A3-40°C to 125°C

IS25LP

2.3V (VMIN) – 3.6V (VMAX); 3.0V (Typ)IS25WP

1.70V (VMIN) –1.95V (VMAX); 1.8V (Typ)Integrated Silicon Solution, Inc.- www.issi.com
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9.3 DC CHARACTERISTICS(Under operating range)
Symbo
l

Max

NORD at 50MHz

68

FRD Single at 104MHz

7

9

FRD Dual at 104MHz

8

10

10

12

Condition

VCC Active Read current(3)ICC1

Typ(2)

ParameterMin

FRD Quad at 104MHz

85°C
ICC2

VCC Program Current

20

105°C

CE# = VCC

15

20

125°C

20

85°C
ICC3

VCC WRSR Current

VCC Erase Current(SER/BER4K/BER64K)

ICC4

ICC5

VCC Erase Current (CE)VCC Standby Current
CMOS

ISB1

IS25LP

IS25WP

15

20

85°C

20
15

CE# = VCC,
VIN = GND or VCC

20

85°C

20
15

CE# = VCC,
VIN = GND or VCC

20

85°C

35(4)
40(4)

17

125°C

45

85°C

15(4)

105°C

CE# = VCC,
VIN = GND or VCC

20

125°C
105°C

18(4)

6

125°C

20

85°C

15 (4)

105°C

20

ILI

Input Leakage Current

VIN = 0V to VCC

1

ILO

Output Leakage Current

VIN = 0V to VCC

1

VIL

(1)

Input Low Voltage-0.5

0.3VCC

VIH(1)

Input High Voltage

0.7VCC

VCC + 0.3

Output Low Voltage

VOH

Output High Voltage

VMIN < VCC < VMAX

Integrated Silicon Solution, Inc.- www.issi.com
Rev. A6
08/10/2022

IOL = 100 µA
IOH = -100 µA

µA

18(4)

3

125°C

VOL

mA

20

125°C
105°C

CE# = VCC

20

125°C
105°C

CE# = VCC

Deep power
down current

ISB2

20

105°C

CE# = VCC

Units

0.2
VCC - 0.2

78

V

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Notes:
1. Maximum DC voltage on input or I/O pins is VCC + 0.5V. During voltage transitions, input or I/O pins may overshoot
VCC by + 2.0V for a period of time not to exceed 20ns. Minimum DC voltage on input or I/O pins is-0.5V. During voltage transitions, input or I/O pins may undershoot GND by -2.0V for a period of time not to exceed
20ns.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC= VCC (Typ), TA=25°C.
3. Outputs are unconnected during reading data so that output switching current is not included.
4. These parameters are characterized and are not 100% tested.

9.4 AC MEASUREMENT CONDITIONS
Max

Units

CL

SymbolLoad CapacitanceParameter

Min

30

pF

TR,TF

Input Rise and Fall Times

5

ns

VIN

Input Pulse Voltages

0.2VCC to 0.8VCC

V

VREFI

Input Timing Reference Voltages

0.3VCC to 0.7VCC

V

VREFO

Output Timing Reference Voltages

0.5VCCV

Figure 9.1 Output test load & AC measurement I/O Waveform

0.8VCC

VCC/2

AC
Measurement
Level

IS25LP

IS25WP

Input
1.8k
0.2VCCOUTPUT PIN

1.2k

10/30pf

9.5 PIN CAPACITANCE(TA = 25°C, VCC=3V for IS25LP, VCC=1.8V for IS25WP, 1MHz)
SymbolCIN
CIN/OUT

Parameter

Test Condition

Input Capacitance(CE#, SCK)
Input/Output
Capacitance(other pins)

Max

Min

Max

VIN = 0V

-

6

-

6

pF

VIN/OUT = 0V

-

8

-

10

pF

Note:
1. These parameters are characterized and are not 100% tested.

Integrated Silicon Solution, Inc.- www.issi.com
Rev. A6
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Units

Min

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9.6 AC CHARACTERISTICS(Under operating range, refer to section 9.4 for AC measurement conditions)SymbolParameter

Min

fCT
fC
tRI
tFI
tCKH
tCKL
tCEH
tCS
tCH
tCHSL
tSHCH

Clock Frequency for fast read mode
Clock Frequency for read mode
Input Rise Time
Input Fall TimeSCK High TimeSCK Low TimeCE# High Time
CE# Setup TimeCE# Hold Time
CE# Not Active Hold Time
CE# Not Active Setup Time

0
0

tDS
tDH
tV
tOH
tDIS (1)tWHSL(3)tSHWL(3)
tHLCH
tCHHH
tHHCH
tCHHL
tLZ(1)

Data In Setup Time
Data in Hold Time
Output Valid
Output Hold Time
Output Disable Time
Write Protect Setup Time
Write Protect Hold Time
HOLD Active Setup Time relative to SCKHOLD Active Hold Time relative to SCKHOLD Not Active Setup Time relative to SCKHOLD Not Active Hold Time relative to SCKHOLD to Output Low Z

tHZ

(1)

Chip Erase Time(5)

256Kb
512Kb
1Mb
2Mb
4Mb

tPP

Page Program Time

tres1(1)Release deep power downtDP(1)tWtSUS(1)tRS(1)tSRST(1)Deep power down
Write Status Register time
Suspend to read readyResume to next suspend
Software Reset cover time

Max

Units

104
50
8
8

MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns

4

HOLD to Output High Z
Sector Erase Time (4Kbyte)
Block Erase Time (32Kbyte)
Block Erase time (64Kbyte)(4)tEC

Typ(2)

4
7
5
5
5
5
2
2
8
2
8
20
100
5
5
5
5

70
130
200
130

12
12
300
500
1000
500

0.25
0.4
0.75
1.5
0.45

1.0
1.5
2.0
3.0
1.2

IS25LP
IS25WP
2
80

3
5
3
10
100
100

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
ms
ms

s

ms
µs
µs
ms
µs
µs
µs

Notes:
1. These parameters are characterized and not 100% tested.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V CC
= VCC (Typ), TA=25°C.
3. Only applicable as a constraint for a WRITE STATUS REGISTER command when SRWD is set at 1
4. 64Kbyte Block Erase time is not applicable to 256Kb (IS25LP/WP025E) and 512Kb (IS25LP/WP512E).
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9.7 SERIAL INPUT/OUTPUT TIMING

Figure 9.2 SERIAL INPUT TIMING (STR Mode)

tCEH
CE#

tCHSL

tCS

tCH

tSHCH

SCK
tDS

tDH

MSB INSI or IOLSB IN

Figure 9.3 SERIAL INPUT TIMING (DTR Mode)

tCEH
CE#

tCHSL

tCH

tCS

tSHCH
SCK
tDS
tDH

SI or IO

MSB

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LSB

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Figure 9.4 OUTPUT TIMING (STR Mode)

CE#

tCKH

SCK
tV

tOH

tCKL

MSB OUT

SO or IOtDISLSB OUT

Figure 9.5 OUTPUT TIMING (DTR Mode)
CE#

tCKH

SCK
tV

SO or IO

tOH

MSB

Integrated Silicon Solution, Inc.- www.issi.com
Rev. A6
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tCKL

tDIS
LSB

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Figure 9.6 HOLD TIMING

CE#
tHLCH
tCHHL

tHHCH

SCK
tCHHH
tHZ

tLZ

SO

SI

HOLD#

Figure 9.7 WRITE PROTECT SETUP AND HOLD TIMIMNG DURING WRITE STATUS REGISTER (SRWD=1)
WP#

tWHSL
tSHWL

CE #

Mode 3 0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

2

1

0

SCK
Mode 0SI

SO

Data In
Instruction = 01h

7

6

5

4

3

High Impedence

Note: WP# must be kept high until the embedded operation finish.

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9.8 POWER-UP AND POWER-DOWN
At Power-up and Power-down, the device must be NOT SELECTED until Vcc reaches at the right level. (Adding asimple pull-up resistor on CE# is recommended.)
Figure 9.8 POWER UP TIMING
VCC
VCC ( max)

Chip Selection Not Allowed

VCC(min)tVCE= Vcc min. to CE# Low

Device is fully
accessible

VWI

Time

SymbolParametertVCE(1)

Vcc(min) to CE# Low

VWI(1)

Write Inhibit Voltage

Min.

Max

Unit

300

us

IS25LP

2.1

IS25WP

1.4

V

Note: These parameters are characterized and not 100% tested.

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9.9 PROGRAM/ERASE PERFORMANCE (1)Parameter

Typ

Max

Unit

Sector Erase Time (4KB)

70

300

ms

Block Erase Time (32KB)

130

500

ms

Block Erase Time (64KB) (2)

200

1000

ms

256Kb

130

500

ms

512Kb

0.25

1.0

1Mb

0.4

1.5

2Mb

0.75

2.0

4Mb

1.5

3.0

Page Programming Time

0.45

1.2

ms

Byte Program

8

40

µs

Chip Erase Time

s

Note:
1. These parameters are characterized and not 100% tested.
2. 64Kbyte Block Erase time is not applicable to 256Kb (IS25LP/WP025E) and 512Kb (IS25LP/WP512E).

9.10 RELIABILITY CHARACTERISTICS
Parameter

Min

Max

Unit

Test Method

Endurance

100,000-

CyclesJEDEC Standard A117

Data Retention

20

-

Years

JEDEC Standard A117

Latch-Up

-100

+100

mA

JEDEC Standard 78

Note: These parameters are characterized and not 100% tested.

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10. PACKAGE TYPE INFORMATION
10.1 8-PIN JEDEC 208MIL BROAD SMALL OUTLINE INTEGRATED CIRCUIT (SOIC) PACKAGE (B)Integrated Silicon Solution, Inc.- www.issi.com
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10.2 8-PIN JEDEC 150MIL BROAD SMALL OUTLINE INTEGRATED CIRCUIT (SOIC) PACKAGE (N)

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10.3 8-PIN 150MIL VVSOP PACKAGE (V)Integrated Silicon Solution, Inc.- www.issi.com
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10.4 8-CONTACT ULTRA-THIN SMALL OUTLINE NO-LEAD (USON) PACKAGE 2X3MM (Y)Note: Please click here to refer to Application Note (AN25D011, Thin USON/WSON/XSON package handlingprecautions) for assembly guidelines.

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IS25WP040E/020E/010E/512E/025E
10.5 8-PIN TSSOP PACKAGE (D)

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10.6 8-CONTACT ULTRA-THIN SMALL OUTLINE NO-LEAD (WSON) PACKAGE 6X5MM (K)Note: Please click here to refer to Application Note (AN25D011, Thin USON/WSON/XSON package handlingprecautions) for assembly guidelines.

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11. ORDERING INFORMATION - Valid Part Numbers
IS25LP 040 E -

J

B

L

E
TEMPERATURE RANGE
E = Extended (-40°C to +105°C)
A3 = Automotive Grade (-40°C to +125°C)

PACKAGING CONTENT
L = RoHS compliant

PACKAGE TypeB = 8-pin SOIC 208mil
N = 8-pin SOIC 150mil
D = 8-pin TSSOP (Call Factory)
V = 8-pin VVSOP 150mil (Call Factory)
Y = 8-contact USON 2x3mm
K = 8-contact WSON 6x5mm (Call Factory)
W = KGD (Call Factory)

OptionJ = Standard
B = Optional BP Table (Call Factory)
C = Optional 1Mb with 32KB Erase only (D8h/52h)
Die Revision
E = Revision E

Density
040 = 4 Mbit
020 = 2 Mbit
010 = 1 Mbit
512 = 512Kbit
025 = 256Kbit

BASE PART NUMBER
IS = Integrated Silicon Solution Inc.
25LP = FLASH, 2.30V ~ 3.60V, QPI
25WP = FLASH, 1.70V ~ 1.95V, QPI

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Density,
VoltageFrequency
(MHz)

4Mb,
3V

2Mb,
3V

1Mb,
3V

512Kb,
3V
256Kb,
3V

4Mb,
1.8V

2Mb,
1.8V

104

Order Part Number(1, 2)

Package

IS25LP040E-JBLE

8-pin SOIC 208mil (Call Factory)

IS25LP040E-JNLE

8-pin SOIC 150mil

IS25LP040E-JKLE

8-contact WSON 6x5mm (Call Factory)

IS25LP040E-JYLE

8-contact USON 2x3mm

IS25LP040E-JBLA38-pin SOIC 208mil (Call Factory)

IS25LP040E-JNLA38-pin SOIC 150mil

IS25LP040E-JKLA3

8-contact WSON 6x5mm (Call Factory)

IS25LP040E-JYLA3

8-contact USON 2x3mm

IS25LP020E-JNLE

8-pin SOIC 150mil

IS25LP020E-JYLE

8-contact USON 2x3mm

IS25LP020E-JNLA38-pin SOIC 150mil

IS25LP020E-JYLA3

8-contact USON 2x3mm

IS25LP010E-JBLE

8-pin SOIC 208mil (Call Factory)

IS25LP010E-JNLE

8-pin SOIC 150mil

IS25LP010E-JYLE

8-contact USON 2x3mm

IS25LP010E-JNLA38-pin SOIC 150mil (Call Factory)

IS25LP010E-JYLA3

8-contact USON 2x3mm(Call Factory)

IS25LP512E-JNLE

8-pin SOIC 150mil (Call Factory)

IS25LP025E -JNLE

8-pin SOIC 150mil (Call Factory)

IS25WP040E-JNLE

8-pin SOIC 150mil

IS25WP040E-JKLE

8-contact WSON 6x5mm (Call Factory)

IS25WP040E-JYLE

8-contact USON 2x3mm

IS25WP040E-JBLE

8-pin SOIC 208mil

IS25WP040E-JNLA38-pin SOIC 150mil

IS25WP040E-JYLA3

8-contact USON 2x3mm

IS25WP020E-JBLE

8-pin SOIC 208mil (Call Factory)

IS25WP020E-JNLE

8-pin SOIC 150mil

IS25WP020E-JYLE

8-contact USON 2x3mm

Notes:
1. A3 meets AEC-Q100 requirements with PPAP, E1= Extended+ non-Auto qualified
Temp Grades: E= -40 to 105°C, A3= -40 to 125°C
2. Call Factory

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