LUPO DAQ Master Module
Rev. 1.1

2010 Aug. 30

11 General

1 General
1.1

Function

1.2

Output register

As a output register, NIM outputs ch0–1 can ﬁre pulse and level signals. The width ofNIM pulse is variable, and it can be changed 20ns–1.3ms with 20 ns step.

1.3Interrupt register

As a interrupt register, this module can generete the interrupt signal to VME/CAMAC.
The delay time between trigger signal and interrupt generation is variable, and it can bechanged 20ns–1.3ms with 20ns step. By the clear command, this interrupt signal iscleared.

1.4Trigger generator

This module can generate the trigger signal according to registerd trigger logic. TheVETO signal which corresponds to DAQ (computer) busy is also generated. The trigger
is inhibited by VETO within inside of LUPO.

1.5Connector12

1 General

Input 0 : 0
Input 1 : 2
Input 2 : 4Input 3 : 6

1 : Module access
3 : Interrupt
5 : Trigger
7 : Accepted

Input 0ch
Input 1ch
Input 2ch
Input 3ch

LVDS input
0–15ch

Output 0ch
Output 1ch
Output 0ch
Output 1ch

232 Interface

2 Interface
2.1

Register Map

Command list.(Tab.2.1)。

2.1.1

Pulse Width

Set the pulse width of the output register. 1 point corresponds to 20ns, and default
vaule is 10 = 200ns. The maximum value is 65536  1.3 ms.

2.1.2

Interrupt Delay

Set the delay time from trigger generation timing to interrupt generation timing. 1
point corresponds to 20ns, and default vaule is 10 = 200ns. The maximum value is 65536
 1.3 ms.

2.1.3

Level Output

Output NIM Level signal. 1=on, 0=oﬀ.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Ch.0
Ch.1
Ch.2
Ch.3

2.1.4

Pulse Output

F(17)A(0) / Base+%10 D16W Output NIM pulse with given width.

3

42 Interface

Table 2.1: Register map
CAMAC (R/W)
F(0)A(0)F(0)A(2)F(0)A(4)F(16)A(0)F(17)A(0)F(1)A(0)F(1)A(2)F(2)A(0)F(2)A(2)F(2)A(4)F(2)A(8)F(3)A(0)F(4)A(0) F(20)A(0)F(4)A(1) F(20)A(1)F(5)A(0) F(21)A(0)F(5)A(1) F(21)A(1)F(5)A(2) F(21)A(2)F(5)A(3) F(21)A(3)F(6)A(0) F(22)A(0)F(6)A(1) F(22)A(1)F(6)A(2) F(22)A(2)F(6)A(3) F(22)A(3)F(6)A(4) F(22)A(4)F(6)A(5) F(22)A(5)F(7)A(0)F(9)A(0)F(9)A(1)F(9)A(2)F(9)A(3)F(24)A(0)F(26)A(0)VME
Base + %00
Base + %04
Base + %08
Base + %00
Base + %10
Base + %10
Base + %14
Base + %20
Base + %24
Base + %28
Base + %2c
Base + %30
Base + %40
Base + %42Base + %50
Base + %52
Base + %54
Base + %56
Base + %60
Base + %62
Base + %64
Base + %66
Base + %68
Base + %6a
Base + %70
Base + %90
Base + %92
Base + %94
Base + %96
Base + %80
Base + %A0Register
Clock 1MHz
Clock 10KHz
Clock 1KHz
Level Output
Pulse Output
Ungated trigger
Gated trigger
Scaler 0ch
Scaler 1ch
Scaler 2ch
Scaler 3ch
Trigger Source
Pulse Width
Interrupt Delay
Output 0ch Conﬁg
Output 1ch Conﬁg
Output 2ch Conﬁg
Output 3ch Conﬁg
AND/OR Register 0
AND/OR Register 1
AND/OR Register 2AND/OR Register 3
Trigger Conﬁguration
Trigger Activation
Version
Clear intterupt & busy
Clear all scaler
Clear trigger scaler
Clear allDisable Interrupt
Enable Interrupt

4

Data
D32
D32
D32
D16
D16
D32
D32
D32
D32
D32
D32
D16
D16
D16
D16
D16
D16
D16
D16
D16
D16
D16
D16
D16
D16
D16
D16
D16
D16
D16
D16

VME R/W
read
read
read
write
write
read
read
read
read
read
read
read
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
readreadreadread
read
write
write52 Interface

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Ch.0
Ch.1
Ch.2
Ch.3

2.1.5

Trigger source

F(3)A(0) / Base+%30 D16R

This register returns the hit pattern of AND/OR Logic and Input channels. The hit
pattern is latched by the trigger timing. This register can be used as the coincidence/input
register. By accessing the Clear intterupt or Clear all register, this register is cleared.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AND/OR logic 0
AND/OR logic 1
AND/OR logic 2AND/OR logic 3
Input Ch.0
Input Ch.1
Input Ch.2
Input Ch.3

2.1.6

Output Configuration 0–3

F(5)A(0–3) F(21)A(0–3) / Base+%50–56 D16RWConﬁgure NIM output channels. You can select the output channel as Ungated (Generated) Trigger, Gated (Accepted) Trigger, VETO, and output register. Usually, you should
on only 1 bit, if multiple bits are on, output will be OR of these. As a output register
case, Output Conﬁg. 0 will be Output Reg. 0, Output Conﬁg 1 will be Output Reg. 1 になります。The default values are: Ch.0 = “0001”、Ch.1 = “0001”、Ch.2 = “0010”、Ch.3= “0100”(Ch.0 and 1 are as the Output Reg. Ch.2 is Ungated Trigger, Ch.3 is GatedTrigger.)562 Interface

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Output
Ungated Trigger
Gated Trigger
Veto
Clock 1KHz
Clock 10KHz
Clock 10MHzThrough

2.1.7

AND/OR Logic 0–3

F(6)A(0–3) F(22)A(0–3) / Base+%60–66 D16RW

Register AND/OR logic to deﬁne the trigger. By setting these AND/OR logic to Trigger
Register, the conﬁguration of the trigger generation is determined. 4th bit corresponds
to AND(=1) / OR(=0). For example, “10011” means that register logical AND or Ch0and Ch1. “01001” case, it is logical OR of Ch0 and Ch3. The default values are: lo0 =“00001”、lo1 = “00010”、lo2 = “00100”、lo3 = “01000”.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Ch.0
Ch.1
Ch.2
Ch.3
AND/OR

2.1.8

Trigger Register

F(6)A(4) F(22)A(4) / Base+%68 D16RW

Select AND/OR logic as the trigger source. This case, trigger will be OR of selectedbits. The default value is ”0001”.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AND/OR Logic 0
AND/OR Logic 1
AND/OR Logic 2
AND/OR Logic 3

6

72 Interface

2.1.9

Trigger Activation

F(6)A(5) F(22)A(5) / Base+%6a D16RW

The validation of tirgger and VETO. (1=On, 0=Oﬀ) ’01’(=1) is used to check thetrigger. ’11’(=3) is DAQ start case. ’00’(=0) or ’10’(=2) cases, ungated trigger isn’tgenerated. The default value is ’01’(=1).
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Trigger
VETO

2.1.10

Clear Register

Clear interrupt register. VME case, this register is read access.

2.1.11Disable Interrupt

Disable VME/CAMAC interrupt. VME case, this register is write access.

2.1.12

Enable Interrupt

Enable VME/CAMAC interrupt. VME case, this register is write access. VME/CAMAC
割り込みを許可します。

2.1.13

VersionReteruns version code of this module. Followind is CAMAC DAQ Master Rev 1.0:
15

1413
12
CAMAC/VME
111109Module ID
987765Rev X.X
14321Rev X.X
0093 Appendix

3 Appendix
3.1

Version Information

1.1 Interrupt function is ﬁxed. The trigger source register in available. Clocks andthrough signals are available on the output conﬁguration.
1.0 First version

9