LUPO Multi TimeStamp Module (Ver. 2.0)
Hidetada Baba
September 26, 2012

11 General

1 General
1.1

Function

This module is a CAMAC/VME LUPO module which including the function of MultiChannel Time stamper, interrupt register, output register.

1.2Time stamp

Time-stamp values are obtained with a 48 bits depth and a 10 ns resolution according
to the trigger inputs (LVDS IN0–15). It can be stored up to 4095 time-stamps into FIFO
memory. A 10 ns separation is required to detect subsequent triggers. Input signals haveto more than 20 ns width. Both clock sources of internal and external are available.
In case of external clock, 100 MHz clock is generated by DLL (Delay Lock Loop) circuitfrom 25 MHz external clock of NIM IN3. The clear input (NIM IN2) reset the time-stampvalue. By using this clear signal, the synchronization for multiple LUPOs are achieved.

1.3

Output register

As a output register, NIM OUT0 can ﬁre pulse and level signals. The width of NIM
pulse is variable, and it can be changed 20ns–1.3ms with 20 ns step.

1.4Interrupt register

As a interrupt register, this module can generate the interrupt signal to VME/CAMAC.
The delay time between trigger signal and interrupt generation is variable, and it can bechanged 20ns–1.3ms with 20ns step. By the clear command, this interrupt signal iscleared.

1

21 General

1.5

Indicator

1.5.1

Ex Clock OK

When the external clock is correct, this LED lights up. However even if the external
clock is not 25 MHz, sometimes this LED becomes ON. And also, after the correct operation, even if cable is removed, sometimes this LED still lights up. When the externalclock mode, please check the Ex Clock through output by oscilloscope. If this signal is 25
MHz, the external clock synchronization is correct.

1.5.2

FIFO Full

There is FIFO memory, and it can store 4095 time-stamps. When FIFO becomes full,
this LED will light up.

1.5.3

Int/Ext clock mode

With the external clock mode, this LED lights up. Internal clock mode case, this LED
is oﬀ. The default setting is the external clock mode.

1.6

Connector

1.6.1

NIM input ch0 : Interrupt

CAMAC/VME interrupt signal is generated by this interrupt input. Interrupt is generated by this input signal OR when exceed 1024 time-stamps in the FIFO.

1.6.2

NIM input ch1 : Veto

When veto is on, triggers are inhibited.

1.6.3

NIM input ch2 : Time ResetWith this input, time stamp values are cleared to be 0. This input is for the module
synchronization. More than 20 ns width logic pulse is required.

1.6.4

NIM input ch3 : Ext Clock

Input external clock. Duty ratio 50:50, 25 MHz NIM logic pulse is needed.
2

31 General

1.6.5

NIM output ch0 : Output 0An output for NIM level and pulse.

1.6.6

NIM output ch1 : Full

When FIFO buﬀer is full, NIM level signal is generated.

1.6.7

NIM output ch2 : Int clock throughAn output of internal 25 MHz clock which is based on internal 50 MHz clock. Thissignal is used for synchronizing other modules.

1.6.8

NIM output ch3 : Ext clock throughAn output signal of external 25 MHz clock which is the through out of the external
25 MHz clock input. This signal is used for checking the external clock quality andsynchronizing other modules. This through out is not a real direct output of the externalclock. The external clock is put into the DLL circuit once, and this signal come from oneof the DLL outputs. Thus, if the 25 MHz external clock has large noise, this through out
will be not stable signal.

3

4

1.7

1 General

Front panel

Ex Clock OK : 0
Veto : 2
FIFO Full : 4
Or 0–7 : 6

1 : Module access
3 : Int/Ext clock mode
5 : Interrupt
7 : Or 8–15

Interrupt
Veto
Time Reset
Ext Clock

NIM output Register
Buﬀer full
Int clock throughExt clock through4

52 Interface2 Interface
2.1

Register map

Command list.
CAMAC (R/W)
F(0)A(0)F(1)A(0)F(1)A(2)F(2)A(0)F(2)A(2)F(2)A(4)F(2)A(6)F(16)A(0)F(17)A(0)F(4)A(0) F(20)A(0)F(4)A(1) F(20)A(1)F(4)A(2) F(20)A(2)F(6)A(0) F(22)A(0)F(6)A(1) F(22)A(1)F(7)A(0)F(9)A(0)F(9)A(1)F(9)A(2)F(9)A(3)F(9)A(4)F(24)A(0)F(26)A(0)

2.1.1

VME
Base + %00
Base + %10
Base + %14
Base + %20
Base + %24
Base + %28
Base + %2c
Base + %00
Base + %10
Base + %40
Base + %42
Base + %44
Base + %60
Base + %62
Base + %70
Base + %90
Base + %92
Base + %94
Base + %96
Base + %98
Base + %80
Base + %A0

Register
Data ReadFIFO Counter
FIFO Full Count
Data on the ﬂy
Clock 10MHz
Clock 10KHz
Clock 1KHz
Level Output
Pulse Output
Pulse Width
Interrupt Delay
Interrupt Source
Clock Source
Software Veto
Module version
Clear Interrupt & Interrupt
Reset Time Stamp
Clear FIFO
Clear All
Clear ClockDisable Interrupt
Enable Interrupt

DataD32
D32
D32
D32
D32
D32
D32
D16
D16
D16
D16
D16
D16
D16
D16
D16
D16
D16
D16
D16
D16
D16

VME R/W
read
read
read
read
read
read
read
write
write
read/write
read/write
read/write
read/write
read/write
read
read
read
read
read
read
write
write

Data Read

F(0)A(0) / Base+%00 D32R Read data from FIFO. 32 bit in VME, 16 bit in CAMAC. In5

62 Interface

VME case, ﬁrst readout returns lower 32 bit value. Second readout returns upper 16 bitvalue and channel number.
First readout
3130

2928272625242322Time Stamp
876Time Stamp

2120191817161514131211109543210313029282726252422212019876Time Stamp5431817Channel
211514131211109

Second readout

2.1.2

23

160

FIFO Counter

F(1)A(0) / Base+%10 D32R

Return the number of 32 bit data in FIFO. The maximum value is 8190.

2.1.3

FIFO Full countF(1)A(2) / Base+%14 D32R

When FIFO becomes full, this counter is incremented. The counter value is cleared byaccessing “Clear FIFO” or “Clear All”.

2.1.4

Data on the fly

F(2)A(0) / Base+%20 D32R

Return the current time stamp counter (higher 24 bits).

2.1.5

Level Output

F(16)A(0) / Base+%00 D16W

Output level signals from NIM Output connectors (1=on, 0=oﬀ).
151413121110

98

76

654

32

10ch0

72 Interface

2.1.6

Pulse Output

F(17)A(0) / Base+%10 D16W

Output pulse signals from NIM Output connectors (1=on, 0=oﬀ). With this pulse
signal, level output will be canceled.
15142.1.7

131211109876543210ch0

Pulse WidthF(4/20)A(0) / Base+%40 D16RW Set the width of the pulse output signal. 1 point corresponds

to 20 ns. The default value is 10 = 200 ns. The maximum value is 65536  1.3 ms.

2.1.8

Interrupt Delay

F(4/20)A(1) / Base+%42 D16RW

Set the delay time during interrupt input arrival time and actual interrupt generation.
1 point corresponds to 20 ns. The default value is 0 = 0 ns. The maximum value is 65536
 1.3 ms.

2.1.9Interrupt SourceF(4/20)A(2) / Base+%44 D16W

Choose the interrupt source (1=on, 0=oﬀ). 0x03 corresponds to “FIFO Threshold” or“External Input”. The default value is 0x03 = “FIFO Threshold”.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFO Threshold
External Input

2.1.10

Clock SourceF(6/22)A(0) / Base+%60 D16RW

Choose the time stamp clock source. Default is the external clock.
0 : Internal Clock
1 : External NIM Input 0782 Interface

2.1.11

Software Veto

F(6/22)A(1) / Base+%62 D16RW

By writing ’1’ into this register, veto will be on. To clear software veto, write ’0’. The
default is ’0’.

2.1.12

Clear Interrupt

F(9)A(0) / Base+%90 D16R

Clear interrupt signal. In case of VME, this function is invoked by read action.

2.1.13

Reset Time stamp

F(9)A(1) / Base+%92 D16R

Reset the time stamp counter to 0. FIFO memory is also cleared. In case of VME, thisfunction is invoked by read action.

2.1.14

Clear FIFO

F(9)A(2) / Base+%94 D16R

Clear FIFO memory. The time stamp counter is not reset. In case of VME, this function
is invoked by read action.

2.1.15Clear All

F(9)A(3) / Base+%96 D16R

Clear FIFO, interrupt signal, clock scalers. In case of VME, this function is invoked byread action.

2.1.16

Clear Clock

F(9)A(4) / Base+%98 D16R

Clear clock scalers. In case of VME, this function is invoked by read action.

2.1.17

Disable Interrupt

F(24)A(0) / Base+%80 D16W

Disable VME/CAMAC interrupt. In case of VME, this function is invoked by write
action. Any write value is acceptable.

892 Interface

2.1.18

Enable Interrupt

F(26)A(0) / Base+%A0 D16W

Enable VME/CAMAC interrupt. In case of VME, this function is invoked by write
action. Any write value is acceptable.

2.1.19

VersionF(7)A(0) / Base+%70 D16R

Return the version code of this module. The following is VME Multi Time Stamp Ver
2.0 case.
15

14
13
12CAMAC/VME
211109Module ID
787965Ver X.X
24321Ver X.X
00113 Appendix

3 Appendix
3.1Version Information

2.0 16ch version, uniﬁed FIFO readout.
1.0 Initial version, 4ch, individual FIFO readout.

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