Proceedings of International Forum for Green Asia 2019
5th International Exchange and Innovation Conference on Engineering & Sciences (IEICES 2019)

GA20 / P32
Impact of Border Trap on mobility of Ge p-MOSFET with Al2O3/GeOx/Ge gate stacks
1

Wei-Chen Wen1, Keisuke Yamamoto1, Dong Wang1, Hiroshi Nakashima2
Interdisciplinary Graduate School of Engineering Sciences, Kyushu University
2
Global Innovation Center, Kyushu University
Email: 3ES17010E@s.kyushu-u.ac.jp

Abstract: Interface traps (ITs) and border traps (BTs) in Al2O3/GeOx/p-Ge gate stacks were characterized using deeplevel transient spectroscopy (DLTS). Through evaluating the gate stacks with several thicknesses of GeOx, the BTs inAl2O3, at Al2O3/GeOx interface, in GeOx were detected. The highest density of BT was found at Al2O3/GeOx interface.
Metal-oxide-semiconductor field-effect transistors (MOSFETs) with Al2O3/GeOx/p-Ge gate stacks were evaluated and theimpact of border trap on mobility are also discussed.
Keywords: border trap, DLTS, Ge MOSFET
1. INTRODUCTION
Ge is one of the candidate materials for the future
MOSFETs due to its high carrier mobility. For highmobility Ge MOSFET, stacked gate dielectric with thin
Ge oxide interlayer, such as SiO2/GeO2 and Al2O3/GeOx,
has been studied actively [1,2]. On the other hand, in thecase of Ge MOS, not only interface traps ITs but BTs
located in gate dielectric are also problematic because it
degrade MOS characteristics and mobility. For deep
understanding and performance improvement of Ge
MOS device, both the value and the position of BT instacked gate dielectric should be clarified. However, indepth study about BT in Ge stacked gate dielectric islimited [3]. Recently, we succeeded in separating the BT
signal and IT signal using DLTS in SiO2/GeO2/Ge gate
stacks grown by thermal and plasma oxidation [4]. In thisstudy, we evaluated the density of IT (Dit) and density ofBT (Nbt) in Al2O3/GeOx/p-Ge gate stacks grown by post
plasma oxidation (PPO). Additionally, we fabricated pMOSFETs with Al2O3/GeOx/p-Ge gate stacks anddiscussed the impact of BT on the devices.

active area, sacrificial GeO2 was formed by thermaloxidation at 450°C for 30 min in O2 ambient and removedby rinse in a dilute HF solution. Next, an Al2O3/GeOx/Gegate stacked was fabricated by ALD and ECR method.
After the 400°C PDA, the Al/TiN gate electrode wasdeposited and patterned. The BF2 ion implantation wascarried out with an acceleration energy of 30 keV and adose of 1015 cm-2. The Al/Pt source/drain contact wasformed by lift-off method, followed by CA (for gate) andactivation annealing (for source/drain) at 300°C for
10min in N2 ambient. Subsequently, the InGa backcontact was formed. P-MOSFET fabrication process andthe device structure are shown in Figs. 1 (a) and (b),respectively. The implanted acceptor density of 4.3×1015
cm-3 was confirmed by Hall Effect measurement, andboth Dit and Nbt were characterized using DLTS [4].
2nd-Al2O3/1st-Al2O3/GeOx

Substrate cleaning
SiO2 deposition (350 nm)
SiO2
Active area definition
Sacrificial oxidation & etching
AlAl2O3/GeOx/Ge gate stack formation
Post deposition annealing (400°C, 30 min)TiN deposition
Pt
Post metallization annealing (350°C, 20 min)Al deposition
Gate electrode patterning
p+BF2 Ion implantation (30 keV)
S/D Al/Pt contact formation
Activation & contact annealing (300°C, 10 min)Back contact formation

2. EXPERIMENTAL
The fabrication process of MOS capacitors is as follows.
P-type (100) Ge substrate with doping concentration of
2.3×1016 cm-3 was used. After chemical cleaning by
acetone and HF solution, the first layer of Al2O3 wasdeposited at 300°C by atomic layer deposition (ALD)with trimethyl aluminum for 3, 9, 14 and 20 cycles,
followed by PPO by electron cyclotron resonance (ECR).
Then, the second layer of Al2O3 was deposited at 300°Cby ALD for 25 cycles to suppress the current leakage. A400°C post-deposition annealing (PDA) for 30 min wasperformed, TiN gate electrode was deposited bysputtering, followed by 350°C post-metallization
annealing (PMA) for 20 min. After Al deposition,
electrodes are patterned. Next, 300°C contact annealing(CA) for 10 min was carried out, and InGa back contact
was formed. All the annealing in this study wasperformed in N2 ambient.
Ge p-MOSFETs are fabricated on n-type (100) Ge
substrate with doping concentration of 9.3×1015 cm-3.
After wafer cleaning, a SiO2 field oxide for isolation wassputtered by ECR, and the active-area lithography wasthen carried out to define the active areas. To eliminate
the damages resulting from sputtering and etching of theAlTiNSiO2AlPtp+InGa

n-Ge

Fig. 1. Fabrication process and device structure of Ge pMOSFETs with Al2O3/GeOx gate stacks.
3. RESULTS AND DISCUSSION
3.1 Electrical properties of Ge MOS capacitors
3-cycle (0.87 nm-GeOx)
9-cycle (0.42 nm-GeOx)
14-cycle (0.06 nm-GeOx)
20-cycle (0.16 nm-GeOx)

1.4C (µF/cm2)

1.2
1.0
0.8
0.6
0.4
0.2

@1 MHz0.0-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0

Voltage (V)Fig. 2. C-V characteristics of Al/TiN/Al2O3/GeOx/p-Ge
MOS capacitors with different cycle number of 1st-Al2O3.
The measurement was performed at RT and at afrequency of 1 MHz.

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Table 1. Thickness information of Al/TiN/Al2O3/GeOx/p-Ge MOS capacitors with different cycle number of 1st-Al2O3.
1st-Al2O3
cycle

1st-Al2O3
thickness (nm)2nd-Al2O3
thickness (nm)

1st + 2nd
Al2O3 EOT (nm)MOS EOT (nm)3-cycle9-cycle14-cycle
20-cycle

1.02
1.65
2.14
2.73

3.2
3.2
3.2
3.2

1.94
2.23
2.46
2.73

2.54
2.52
2.5
2.84

All samples showed typical C-V characteristics, as shownin Fig. 2. With increasing cycle number of the first layerof Al2O3, the flat band voltage (VFB) shifts to the positive
direction, and a bit stretch-out can be seen. The stretchout in C-V may result from the thinner GeOx. The
thickness information including equivalent oxide
thickness (EOT) for each oxide layer is shown in theTable 1.

Dit (eV-1cm-2)

0.60
0.29
0.04
0.11Nbt (cm-3)0.87
0.420.06
0.163cycle (0.87 nm-GeOx)
9cycle (0.42 nm-GeOx)
14cycle (0.06 nm-GeOx)
20cycle (0.16 nm-GeOx)

1019

1018

1017

3-cycle (0.87 nm-GeOx)
9-cycle (0.42 nm-GeOx)
14-cycle (0.06 nm-GeOx)
20-cycle (0.16 nm-GeOx)

1013

GeOx
GeOx EOT (nm)(MOS EOT-Al2O3 EOT) thickness (nm)

80

100

120

140

Temperature (K)160

Fig. 4. Temperature dependence of Nbt for
Al/TiN/Al2O3/GeOx/p-Ge MOS capacitors with different
cycle number of 1st-Al2O3.

1012

1011

10Figure 4 shows the Nbt for all samples. Here, wemeasured BT which affect capture/emission of hole invalence band of Ge. With decreasing thickness of GeOx,
Nbt firstly increases and then decreases. The measured
depth of BT is approximately 0.4 nm when the tunnelingbarrier height is the band offset of GeO2 and Ge [4]. The
locations of detected Nbt are demonstrated in Fig. 5. In
the case of the thickest GeOx (3 cycle-1st-Al2O3), BT inGeOx is measured, as shown in Fig. 5(a). The value iscomparable with our previous work about 1.8 nm-thick
PPO GeO2 [4]. In the case of 9 cycle-1st-Al2O3corresponding 0.42 nm-thick GeOx, BT located at theinterface of Al2O3 and GeOx is observed (Fig. 5(b)), andthe value is the highest in this study. If the 1st-Al2O3 isthicker (14-20 cycle) corresponding thinner GeOx, themeasured BTs are located in the Al2O3 layer and Nbt issmaller than those of in GeOx and Al2O3/GeOx interface.
Therefore, BT at Al2O3/GeOx interface is the mostserious for hole capture/emission in this stacked gate
dielectric.

10-0.3-0.2-0.1

ET-Ei (eV)0.0forFig.
3.
EnergydistributionofDit
Al/TiN/Al2O3/GeOx/p-Ge MOS capacitors with different
cycle number of 1st-Al2O3.
Figure 3 shows the energy distribution of Dit. In theregion close to mid-gap, the thicker GeOx contributes tothe lower Dit. This is reasonable and commonly accepted[1], and the tendency also well agrees with the C-V
characteristics. However, in the region close to valenceband, the thicker GeOx shows higher Dit. The reason isunclear yet. One possibility is that the mechanism issimilar to the effect of defect termination by Al atom after
post-metallization annealing (Al-PMA), so the ITs closeto valence b and are passivated [5].

(a)

(b)

3 cycleAl2O3GeOx

p-Ge~0.4 nm~3.6 eV(c)

9 cycle

GeOx

Al2O3

14-20 cycle

p-Ge

Al2O3~3.6 eV>0.16 nm

GeOx

p-Ge

~0.4 nm0.87 nm0.42 nm~3.6 eV<0.16 nmFig. 5. Detected BT signals in band diagram of Al/TiN/Al2O3/GeOx/p-Ge MOS capacitors with 1st-Al2O3 deposition for(a) 3 cycle, (b) 9 cycle and (c) 14-22 cycle.
3.2 Device performance of Ge p-MOSFETs
Figure 6 shows drain current (ID) versus drain voltage(VD) characteristics of pMOSFETs with theAl2O3/GeOx/Ge gate stack. Here, the channel length (L)and width (W) are 120 and 390 m, respectively. ThepMOSFET with higher cycle number of Al2O3 first layer

showed the higher current drivability. Figure 7 showssource current (IS) versus gate voltage (VG)
characteristics with VD=-10mV. The threshold voltage(VTH) was obtain from the x-axis interception of IS/gm1/2
versus VG plot, where is transconductance. With
increasing cycle number of the first layer of Al2O3, the- 54 -

Al2O3 are in between. In the low-field region,
degradation of mobility is generally considered as aneffect of surface roughness due to the channel carrier
gathering near the surface under high electric field.
However, the wafer condition and the fabrication processof these devices are the same, and we believed there
should be no discrepancy in the roughness. Instead ofsurface roughness, here we considered the effect ofbolder trap as the main factor of mobility degradation inhigh-field region.

VTH shifts to the positive direction, which coincide with
VFB shift found in C-V characteristics of MOS capacitors.
The effective mobility (µ) was calculated using IS-VG datawith VD=-10 mV and a formula of µ=gm/[(W/L)COXVD],
where COX is an inversion channel capacitanceexperimentally obtained from the gate-channel
capacitance.
3-cycleVTH= -0.42V-1.09-cycle
VTH= -0.30V20-cycle
VTH= 0.39V

-1.6V

-0.8
VG-VTH= -1.6V

-1.6V

-0.4

-1.2V

-1.2V

-0.2-0.8V

-0.8V

-0.4V

-0.4V

-0.6

0.0

Effective Mobility (cm2/Vs)

Drain Current ID (mA)

-1.2

-1.2V

-0.8V

-2

-10 -2-0.4V-10 -2

Drain Voltage VD (V)-10Source Current IS (A/µm)

Fig. 6. ID-VD characteristics of Ge p-MOSFET withdifferent cycle number of 1st-Al2O3. All the devices have
Al2O3/GeOx/Ge gate stacks. The L and W were 120 and390 m, respectively.

10-100.0

0.5

1.0Gate Voltge VG (V)Fig. 7. IS-VG characteristics of Ge p-MOSFET withdifferent cycle number of 1st-Al2O3.
Figure 8 shows the effective mobility as a function ofinversion carrier density. The highest peak mobility wasobtained from the MOSFET with 20-cycle-1st-Al2O3
even in the high-field region. A delay of signal rising canbe seen in this device, which may result from theCoulomb scattering of ITs. MOSFET with 9-cycle-1stAl2O3 showed the lowest mobility among all devices, andthe mobility value of the MOSFET with 3-cycle-1st(a) ΦS=ΨB(b) ΦS=ΨB+0.23 eV

150
1003-cycle
9-cycle20-cycle

5000246810121416Figure 9 shows band diagrams of MOSFETs at different
bias conditions. When the surface potential (ΦS) equals
to difference of Fermi level (EF) and intrinsic Fermi level(Ei) (ΨB), corresponding to weak inversion, the ITs near
mid gap are filled, thus showing negative charge, asshown in Fig. 9 (a). When ΦS equals to ΨB + 0.23 eV,corresponding to the crossing point in Fig. 3, the ITcharge become neutral and some carrier may be captured
by BTs, as shown in Fig. 9 (b). When ΦS is over ΨB + 0.5
band gap (Eg), corresponding to the high-field region (Fig.
9 (c)), even the donor-like ITs near valence band arefilled with holes, the IT charge shows positive. Besides,
a lot of holes are captured by the BTs in oxide layers.
Since the capture cross section of BTs is very small, thecapture may last for whole measurement. As a result, thehigh-field region, more carriers (holes) were captured by
the BT in the oxide layer, thus degrading the mobility.
According to the result of Nbt, the net effect of BT wasless severe for the device with 20-cycle-1st-Al2O3, so themobility reach a higher level than other conditions.

3-cycle9-cycle20-cycle-2.0 -1.5 -1.0 -0.5

200

Fig. 8. Effective hole mobility in Ge p-NOSFET withdifferent cycle number of 1st-Al2O3.

VTH

10-9

W/L=120/390µm
VD=-10mV

Inversion Carrier Density (1012 cm-2)

W/L=120/390µm
VD=-10mV

10-8250(c) ΦS>ΨB+0.5Eg

ECEFEiECEFEVEi

Acceptor-like IT
Donor-like ITHoleEVECEFEiEV- 55 -Fig. 9. Band diagrams of Ge pMOSFET showing the occupancyof IT and BT when (a) ΦS=ΨB, (b)ΦS=ΨB+0.23 eV and (c)ΦS>ΨB+0.5Eg (corresponding tohigh field region). IT charges arenegative at condition (a), neutral atcondition (b) and negative atcondition (c).

4. CONCLUSION
We evaluated Dit and Nbt of Al2O3/GeOx/p-Ge gate stacks
with different GeOx thickness by using DLTS. Bychanging GeOx thickness, we can separately evaluate Nbt
in GeOx, Nbt at Al2O3/GeOx interface, and Nbt in Al2O3.
The Dit near to mid-gap is lower in the thicker GeOx. By
contrast, the Dit near to the valence band is lower in thethinner GeOx. BTs are mainly located at the interface ofAl2O3 and GeOx. Surface roughness may not be the only
factor of mobility degradation in high-field region. The
BTs in oxide layers play an important role as well.
Therefore, good quality oxide layers and adequately highband offset of oxide layers are important for highperformance MOSFETs.

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