AN90005

Understanding Power GaN FET data sheet parameters
Rev. 2.0 — 8 June 2020

application note

Document information
Information

Content

Keywords

GaN FET, parameters, data sheet

Abstract

This appplication note explains the content of Nexperia Power GaN FET data sheets.
Nomenclature, pinning and key parameters are detailed.

AN90005

Nexperia

Understanding Power GaN FET data sheet parameters

1. Introduction
This application note examines in detail the data sheet for the GAN063-650WSA GaN FET device
from Nexperia. Visit the product information page on Nexperia.com to download the latest versionof the full data sheet.

2. Nomenclature
The device name (type number) is shown at the top of the data sheet. The name contains some
important information about the device. In the below example for GAN063-650WSA, the maximum
on-state resistance and the limiting drain-source voltage are specified, together with letter codesindicating the package, the mounting base electrical connection and the technology generation.
Nexperia
GaN FET

RDSon (max.)

Drain-source voltage (max.)
650 V

63 mΩ

{
{

{

GAN063-650WSA
W = package code TO247
S = TAB connected to Source
A = Nexperia technology generation 1

Fig. 1.

GaN FET Nomenclature

3. Pinning information
Table 1. Pinning information
Pin
Symbol Description

Simplified outline

1

G

gate

2

S

source

3

D

drain

mb

S

mounting base; connected tosourceGraphic symbol

mb

D

G

1

2

3

TO-247 (SOT429)

S
aaa-028116

The Nexperia GAN063-650WSA is packaged in a TO247 (SOT429) package with a source tab.
The traditional TO-247 provides excellent heat transfer, and therefore excellent power-handlingcapability.

mounting baseconnected to source

aaa-029292

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Understanding Power GaN FET data sheet parameters
Note: the pin functions are different from a standard MOSFET: pin 1 is the gate,pin 2 is the source and pin 3 is the drain.

G

gate
loop

D

S

G

ZL

power
loop

gate
loop

aaa-029293

Fig. 2.

S

D

ZL

power
loop
aaa-029294

Conventional pin assignment

Fig. 3.

Nexperia pin assignment

Using pin 2 as the source pin allows the circuit designer to keep the gate loop and the power loop
separate. This facilitates a very clean design and greatly reduces or eliminates cross coupling. The
PCB design can be optimised to take advantage of this feature.

4. Two-chip, integrated, normally-off power switch
The full graphic symbol of a GaN FET is shown in the pinning information section of the data sheet.
Note that the symbol includes two devices:D

G
S
aaa-028116••

Low-voltage Si MOSFET with a p-n body diodeHigh-voltage GaN FET without a p-n body diodeThe full graphic symbol shows that the device is a two chip integrated switch. Functionally theswitch is normally off. Internally the device is built with two chips. The high-voltage GaN HEMT or
FET is normally on, which is the type most naturally made with GaN, and is combined with a highperformance normally-off Si MOSFET specifically developed to complement the GaN HEMT. The
two chips are integrated with absolute minimum inductance between them.

Q2
il

Vi

D2

VIN
VD

Q1

D1

aaa-029295

Fig. 4.

Simplified GaN FET symbol

In circuit schematics where just the basic switching function is important, a simple N-channel FET
symbol is used to represent the complete, integrated switch (see Q1 circled in red above). Whenyou see the simple symbol, understand that it represents this two-chip integrated combination.

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Understanding Power GaN FET data sheet parameters

5. GaN FET limiting values
The limiting values table provides the range of operating conditions allowed for the GaN FET. The
conditions are defined in accordance with the Absolute Maximum Rating System (IEC 60134).
Operation outside of these conditions is not guaranteed, so it is recommended that these values
are never exceeded. Doing so risks immediate device failure or reduced lifetime of the GaN FET.
To calculate how the limiting values change with temperature de-rating curves are provided.
The limiting values table for the GAN063-650WSA is given as an example of a standard limiting
values table, in Table 2.
Table 2. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
SymbolParameter

Conditions

Min

Max

Unit

VDS

drain-source voltage-55 °C ≤ Tj ≤ 175 °C

-

650

V

VTDS

transient drain to source
voltagepulsed; tp = 1 µs; δfactor = 0.01

-

800

V

VGS

gate-source voltage

-20

20

V

Ptot

total power dissipation

Tmb = 25 °C; Fig. 8

-

143

W

ID

drain current

VGS = 10 V; Tmb = 25 °C

-

34.5

A

VGS = 10 V; Tmb = 100 °C

-

24.4

A

pulsed; tp ≤ 10 µs; Tmb = 25 °C

IDM

peak drain current

-

150

A

Tstg

storage temperature

-55

150

°C

Tj

junction temperature

-55

175

°C

Tsld(M)

peak soldering
temperature

-

260

°C

Source-drain diodeIS

source current

Tmb = 25 °C; VGS = 0 V

-

34.5

A

ISM

peak source current

pulsed; tp ≤ 10 µs; Tmb = 25 °C

-

150

A

5.1. Drain-source voltage, VDS

This 650 V rating is the maximum value that will give you the desired product life.
GaN FETs do not have an avalanche breakdown mechanism. The Nexperia GaN FET does not
typically show any significant leakage current until a VDS well beyond 800 V is reached. So there isan extra margin in VDS before excess leakage occurs. If the GaN FET is subjected to a sufficiently
high voltage, well beyond the specified maximum, then because there is no clamping mechanism
damage and failure will occur. Since GaN FETs do not have an avalanche breakdown mechanism
they are immune to cosmic radiation and so no further derating is required.
••

AN90005

application note

VDS is the maximum voltage the device is guaranteed to block between drain and source
terminals in the off-state. VDS is a DC rating
VDS is not limited by avalanche breakdown; the rating can be applied over the entire operating
range of -55 °C to 175 °C in contrast to the VDS for a Si MOSFET which must be de-rated below
25 °C

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Understanding Power GaN FET data sheet parameters5.2. Transient drain-source voltage, VTDSVTDS is the Maximum repetitive transient voltage the device is guaranteed to block between drain
and source in the off state. This transient rating, applies over the entire operating temperature
range.
P

t2

duty cycle δ =

t1
t2

t1

t

006aaa812

Fig. 5.

Duty Cycle Definition
800 V

+
DUT
3 MΩ

VG

VDS

tp

tp ≥ 1 µs

800 V

800 V

900 V
MOSFET0V
10 tp
pulse width ≥ 1 µs
duty ratio = 0.1

Fig. 6.

AN90005

application note

aaa-029296

Fig. 7.

0V
aaa-029297

VTDS waveform

VTDS test circuit

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Understanding Power GaN FET data sheet parameters5.3. Gate source voltage, VGS and total power dissipation, Ptot

VGS
Maximum voltage the device is guaranteed to block between the gate and source terminals. This isa DC rating, and applies over the entire operating temperature range.

Ptot
Ptot is the Total Power dissipation is the maximum for a device with a mounting base temperature of
25 °C.
03aa16

120
Pder
(%)
80

40

0

0

50

Pder =
Fig. 8.

100

Ptot
Ptot(25 °C)

150

Tmb (°C)

200

× 100 %

Normalised total power dissipation as a function of mounting base temperaturePower dissipation is calculated as that which would take the device to the maximum allowed
junction temperature while keeping the mounting base at 25 °C.

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Understanding Power GaN FET data sheet parameters

5.4. Continuous and pulsed currents, ID, IDM, IS and ISM,

The 25 °C current ratings are the same for both current directions (ID and IS).
D

ID

D

G

G
S

aaa-029304

SIS

aaa-029304

The maximum current at any Tmb is the current which increases Tj to the maximum allowed
temperature (175 °C).

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Understanding Power GaN FET data sheet parameters

6. GaN FET static characteristics
These are the device parameters that explain how the GaN FET behaves in it normal operating
conditions

6.1. Gate-source threshold voltage, VGS(th)Gate-source threshold voltage for the GaN FET device is the gate-source threshold voltage of the
Si MOSFET. This gate threshold is 3.9 V typically, with a negative temperature co-efficient.
D

ID

G
S

aaa-029304

ID = 1 mA; VGS = VGS(th)Fig. 9.

AN90005

application note

GaN FET gate-source threshold voltage

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Understanding Power GaN FET data sheet parameters6.2. Drain-source on-state resistance, RDSon

I
RSNS

ID

DUT

V
VDS

VGS

VDS

t

480 V
VDD

VGS

2.5 µs.01 % duty cycle

aaa-029305

Fig. 10. Test circuit for dynamic RDSont

aaa-029306

Fig. 11. Dynamic RDSon waveform

RDSon is the drain-to-source on-state resistance of the GaN FET. This has a dynamic value for
GaN FETs. When RDSon is measured immediately after turn-on, following period of blocking highvoltage, this value will be slightly higher than normal. This is due to temporary charge trapping in
the device structure. Nexperia have optimised the device so that charge trapping and dynamic
RDSon are minimised.
As can be seen in Fig. 12, RDSon is shown as a normalised function of junction temperature.

aaaa-027810

3
2.5
2
1.5
1
0.5
0

0

25

50

a=

75

100

125

RDSon

150 175
Tj(°C)

200

RDSon(25 °C)

Fig. 12. Normalised drain-source on-state resistance as a funtion of junction temperature.

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Understanding Power GaN FET data sheet parameters

7. GaN FET dynamic characteristics
These are the device parameters that explain how the GaN FET behaves in its normal operating
conditions

7.1. Gate charge QG(tot), QGS and QGD

Gate charge for GaN FET is defined in the same way as a normal MOSFET, because the cascodearrangement of a GaN FET means that the gate is in fact the gate of a LV MOSFET. Since the LV
MOSFET is a relatively small device it has a small gate charge suited to high speed switching.

7.2. Capacitances Ciss, Coss and Crss

Traditional small signal capacitance is shown in Fig. 13. The discontinuity (step change) in Fig. 13
is where GaN HEMT pinches off. Capacitance relates charge to voltage and energy to voltage. Fora linear capacitance, the following fundamental equations apply:

Q = CV

E=
104
C
(pF)

CV2
2

aaa-028058

103
Ciss
102
Coss
10
Crss
1

1

10

102

VDS (V)103

VGS = 0 V; f = 1 MHz
Fig. 13. Input, output and reverse transfer capacitance as a funtion of drain-source
voltage; typical values

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Understanding Power GaN FET data sheet parameters
The capacitances Co(er) and Co(tr) attempt to capture these relationships for a nonlinear
capacitance.

7.3. Effective output capacitance (energy related), Co(er)The GaN FET capacitance parameter Co(er) is the effective output capacitance (energy-related)dependent on the drain voltage
Note that 0 ≤ VDS ≤ 400 V shown above, means as the voltage rises from 0 V to 400 V.

aaa-029307

30

EOSS
(µJ)
25
20
15
10
5
0

1/2 · 190 pF · V DS2
0

100

200

300

400

500
600
VDS (V)

Fig. 14. EOSS as a function of VDS
At a specific VDS, a unique value of Coss satisfies the equation:e.g.

By integrating COSS with respect to VDS, the result will be QOSS. If we then integrate QOSS withrespect to VDS, we will then arrive at EOSS.
EOSS * switching frequency will give the switching power loss in Watts.

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Understanding Power GaN FET data sheet parameters7.4. Effective output capacitance (time related), Co(tr)The GaN FET capacitance parameter Co(tr) is the equivalent capacitance to give same charging
time, as VDS rises from 0 V to 400 V. This can also be described as a constant current being used
to charge the output capacitance, giving a time related effective value.

At a specific VDS, a unique value of Coss satisfies the equation:e.g.

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AN90005

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Understanding Power GaN FET data sheet parameters7.5. Output charge and stored energy, Qoss and Eoss
Rather than using the Co(tr) and Co(er) parameters, it is much easier to use the graphs shown belowthat are also available in the data sheet. The respective QOSS and EOSS values can be read directly
for the required VDS.
aaa-029173

160
QOSS
(nC)

aaa-028063

30
EOSS
(µJ)
25

120
20
80

15
10

40
5
0

0

100

200

300

400

500
600
VDS (V)

0700

Fig. 15. Typical QOSS

0

100

200

300

400

500
VDS (V)

600

Fig. 16. Typical COSS stored energy

7.6. GaN FET switching time characteristics

Nexperia GaN FETs generally require a ferrite bead in series with the gate. This serves to de-”Q”
the gate-source loop and improve the switching stability. The ferrite bead effectively provides
damping impedance at frequencies > 100 MHz. It also introduces a small propagation delay,
however it does not introduce any additional loss.
The GAN063-650WSA in TO247 package has an integral ferrite bead, and so an external beadis not required. Newer GaN FETs may not include the integral ferrite bead, and so one must
be included in the external gate drive. Always refer to the data sheet of specific devices fordetails.
VDS

VGS

D

90 %

10 %
tR
tD(on)G

tF
tD(off)

tON

tOFF

S

aaa-029330

Fig. 17. Switching time waveform
Fig. 18. Internal Ferrite bead

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Understanding Power GaN FET data sheet parameters7.7. Source-drain voltage, VSD

This device parameter source-drain voltage refers to the GaN FET device when it is acting as a two
terminal device when not enhanced with the gate VGS = 0 V.

D

aaa-028059

150
IS
(A)
125

Tj = 25°C

-

50°C
75°C
100°C

100

125°C
150°C

75

175°C

VSD

50

G

25
0

0

2

4

6

8
VSD (V)

VGS = 0 V

10S

VGS = 0 V
Fig. 19. Source-drain (diode forward) current as afunction of source-drain (diode forward)
voltage; typical values+

IS
Fig. 20. Source-drain (diode forward) voltage

VSD is the voltage developed whilst GaN FET conducts in reverse direction (e.g. acting as arectifier carrying freewheeling current) Here the voltage VSD comprises the forward voltage of the
Silicon MOSFET body diode and the voltage drop across the 2 DEG channel of the GaN HEMT.

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Understanding Power GaN FET data sheet parameters

8. Qr for GaN FET switches

I, V
dlS/dt

IS

trr

IRM
DUT

A

Qr

t

0.25 IRM

VRRM

VSD

+
aaa-029277

Fig. 21. Recovered charge test circuit and measurement waveforms
The Device Under Test (DUT) is carrying a freewheeling current. The switch in the high side of
the test circuit in Fig. 21 will then turn on and force a transition at the switching node from low
voltage to high voltage. This will cause the current in the DUT to change from freewheeling current
to some negative current up until the point that the DUT is blocking the full DC supply voltage. If
you integrate the negative current you will get the minority carrier stored change plus any output
capacitance charge.
For GaN FETs, the charge on the output capacitance QOSS is the dominant component of thereverse recovery charge Qr. Hence the reason that the datasheet for the Nexperia GaN FET
specifies the same value for both QOSS and Qr.
Some GaN device manufacturers will claim to have zero reverse recovery charge Qr because they
do not have a PN junction body diode. However, they will still have QOSS.

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Understanding Power GaN FET data sheet parameters

9. Switching-node snubber
To achieve maximum efficiency and stability when switching high currents, a switching node RC
snubber (R, Csn) is recommended. For IL < 14 A, a switching-node snubber is not required.

driverRG

RCDCL(place as close as
possible to drain pin)

Q2

140
120

VS

100

driver

RG

80

Vo

Q1
RSN

RCSN

CSN

60

aaa-029331

40

Fig. 23. DC-link snubber circuit

20
0

VBUS

DC busaaa-029603

Csn 180
(pF)
160

0

5

10

15

20

25

30
35
IL (A)

40

RG = 30 Ω; τ = RSN × CSN = 1 ns
Fig. 22. Snubber capacitance as function of Loadcurrent
Note: a DC-link snubber is recommended in all cases. Optimal is 20 nF in series with 4 Ω,most easily achieved with parallel combination 10 nF and 8 Ω. This snubber lowers the
Q factor of any resonance in the bus. That resonance will act as a load on the high gain
amplifier that is the GaN FET and can lead to instability.
For some GaN FETs, like the GAN063-650WSA, an RC snubber is recommended for theswitching node. This will increase switching loss, so this is only recommended at highpower levels where the losses are a very small percentage of the total power. Other GaN
FETs do not require a snubber on the switching node at any power level. Always refer tothe data sheet of specific devices for details.

10. Revision history
Table 3. Revision history
Revision
Date
numberDescription

2.0

2020-06-08

Section 5.1, Section 7.6 and Section 9 updated

1.1

2019-02-13

Initial version

1.0

2018-11-09

Preliminary version

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Understanding Power GaN FET data sheet parameters

11. Legal information
Definitions
Draft — The document is a draft version only. The content is still underinternal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any representations or
warranties as to the accuracy or completeness of information included hereinand shall have no liability for the consequences of use of such information.

Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, Nexperia does not give any
representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for theconsequences of use of such information. Nexperia takes no responsibility
for the content in this document if provided by an information source outsideof Nexperia.
In no event shall Nexperia be liable for any indirect, incidental, punitive,
special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removalor replacement of any products or rework charges) whether or not suchdamages are based on tort (including negligence), warranty, breach ofcontract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, Nexperia’s aggregate and cumulative liability towards customer
for the products described herein shall be limited in accordance with theTerms and conditions of commercial sale of Nexperia.
Right to make changes — Nexperia reserves the right to make changes
to information published in this document, including without limitation
specifications and product descriptions, at any time and without notice. This
document supersedes and replaces all information supplied prior to the
publication hereof.
Suitability for use — Nexperia products are not designed, authorized or
warranted to be suitable for use in life support, life-critical or safety-criticalsystems or equipment, nor in applications where failure or malfunctionof an Nexperia product can reasonably be expected to result in personal
injury, death or severe property or environmental damage. Nexperia and its
suppliers accept no liability for inclusion and/or use of Nexperia products insuch equipment or applications and therefore such inclusion and/or use is at
the customer’s own risk.
Applications — Applications that are described herein for any of theseproducts are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using Nexperia products, and Nexperia accepts no liability forany assistance with applications or customer product design. It is customer’ssole responsibility to determine whether the Nexperia product is suitableand fit for the customer’s applications and products planned, as well as
for the planned application and use of customer’s third party customer(s).
Customers should provide appropriate design and operating safeguards tominimize the risks associated with their applications and products.
Nexperia does not accept any liability related to any default, damage, costs
or problem which is based on any weakness or default in the customer’s
applications or products, or the application or use by customer’s third party
customer(s). Customer is responsible for doing all necessary testing for thecustomer’s applications and products using Nexperia products in order toavoid a default of the applications and the products or of the application or
use by customer’s third party customer(s). Nexperia does not accept any
liability in this respect.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a priorauthorization from competent authorities.
Translations — A non-English (translated) version of a document is forreference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.

Trademarks
Notice: All referenced brands, product names, service names andtrademarks are the property of their respective owners.

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Understanding Power GaN FET data sheet parameters

List of Tables
Table 1. Pinning information................................................ 2
Table 2. Limiting values....................................................... 4
Table 3. Revision history....................................................16

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Understanding Power GaN FET data sheet parameters

List of Figures
Fig. 1. GaN FET Nomenclature........................................... 2
Fig. 2. Conventional pin assignment....................................3
Fig. 3. Nexperia pin assignment.......................................... 3
Fig. 4. Simplified GaN FET symbol......................................3
Fig. 5. Duty Cycle Definition................................................ 5
Fig. 6. VTDS test circuit....................................................... 5
Fig. 7. VTDS waveform........................................................5
Fig. 8. Normalised total power dissipation as afunction of mounting base temperature............................... 6
Fig. 9. GaN FET gate-source threshold voltage.................. 8
Fig. 10. Test circuit for dynamic RDSon...............................9
Fig. 11. Dynamic RDSon waveform..................................... 9
Fig. 12. Normalised drain-source on-state resistanceas a funtion of junction temperature.................................... 9
Fig. 13. Input, output and reverse transfer capacitanceas a funtion of drain-source voltage; typical values........... 10
Fig. 14. EOSS as a function of VDS..................................11
Fig. 15. Typical QOSS....................................................... 13
Fig. 16. Typical COSS stored energy................................ 13
Fig. 17. Switching time waveform...................................... 13
Fig. 18. Internal Ferrite bead............................................. 13
Fig. 19. Source-drain (diode forward) current as afunction of source-drain (diode forward) voltage;
typical values......................................................................14
Fig. 20. Source-drain (diode forward) voltage....................14
Fig. 21. Recovered charge test circuit andmeasurement waveforms................................................... 15
Fig. 22. Snubber capacitance as function of Load current. 16
Fig. 23. DC-link snubber circuit..........................................16

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Understanding Power GaN FET data sheet parameters

Contents
1. Introduction................................................................... 2
2. Nomenclature................................................................ 2
3. Pinning information......................................................2
4. Two-chip, integrated, normally-off power switch....... 3
5. GaN FET limiting values.............................................. 4
5.1. Drain-source voltage, VDS........................................... 4
5.2. Transient drain-source voltage, VTDS...........................55.3. Gate source voltage, VGS and total power
dissipation, Ptot.....................................................................6
5.4. Continuous and pulsed currents, ID, IDM, IS and ISM,....7
6. GaN FET static characteristics....................................8
6.1. Gate-source threshold voltage, VGS(th).....................8
6.2. Drain-source on-state resistance, RDSon..................9
7. GaN FET dynamic characteristics.............................10
7.1. Gate charge QG(tot), QGS and QGD............................ 10
7.2. Capacitances Ciss, Coss and Crss............................... 10
7.3. Effective output capacitance (energy related), Co(er)..11
7.4. Effective output capacitance (time related), Co(tr).......127.5. Output charge and stored energy, Qoss and Eoss....... 13
7.6. GaN FET switching time characteristics................137.7. Source-drain voltage, VSD......................................... 14
8. Qr for GaN FET switches........................................... 15
9. Switching-node snubber............................................ 16
10. Revision history........................................................16
11. Legal information......................................................17© Nexperia B.V. 2020. All rights reserved

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Date of release: 8 June 2020

AN90005

application note

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Rev. 2.0 — 8 June 2020

© Nexperia B.V. 2020. All rights reserved

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