page.1

Preliminary

IGBT Gate Drive Unit
VLA593-11R

Sep.2021

page.2

Preliminary

IGBT Gate Drive Unit VLA593‐11R
Block Diagram
TIMER&RESET

GND

C1

DETECTCollectorclamp

G1

INTERFACE

E1

GATE SHUT DOWN

VCC1
UVL

Reg.

Targeted IGBT Modules
1700V series Prime PACK IGBT modules

LATCH

VEE1

DC－AC

Features>Directly mountable on the Prime PACK
>Built in the isolated DC‐DC converter for gate drive>Output peak current is +/‐20A(max)>Electrical isolation voltage is 4000Vrms
FoH(for 1 minute)
INH>Built in short circuit protection with soft shut down
>Built in collector clamp circuit>One way power supply system for drivers andinput signal (VD=15V)
VD

VCC2UVLVEE2TIMER&RESET

LATCH

DETECTCollectorclamp

FoL
INL

G2INTERFACEGATE SHUT DOWN

E2

page.3

Maximum ratings(unless otherwise noted, Ta=25C)

SymbolItem

Conditions

Ratings

Unit

VD

Supply voltage

DC‐1 ~ 16.5

V

VI
I_Fo

Input signal voltage
Fo output current

Applied between GND ‐ INH,INL
Sink and source current of Fo terminal

19+/‐10VmA

Output peak current

Pulse width 3us‐20A20A

VisoIsolation voltage between
primary and secondary

Sine wave voltage 60Hz, for 1min

4000

Vrms

Topr

Operating temperature

No condensation allowable‐40 ~ 85deg CTstg

Storage temperature

No condensation allowable‐40 ~ 90

deg CIdrive

Gate drive current

Gate average current (Per one circuit)

100mA

VDC_Link

Main circuit voltage

The voltage between P and N

1200

V

IOHP
IOLP

Electrical characteristics( unless otherwise noted, Ta=25 degC, VD=15V, f=3kHz)

Symbol

ItemConditions

VD

Supply voltagefSwitching frequency

Limits

UnitMin

TypMaxRecommended range

14.5

1515.5

V

Recommended range
It is limited by gate average current (max:100mA)‐‐

7kHzohm

RG

Gate resistance

Recommended range

0.5‐

‐

VI
I_Fo

Input signal voltage
Fo output current

Recommended range

4.5

‐

15.5

V

Recommended range

‐4‐

4mA

VI_H

Input signal high threshold

‐

1.5

1.8

2.1

V

VI_L
VOH

Input signal low threshold
Plus bias output voltage

‐

0.8

1.1

1.4

V

Input “H”(High active)

13.5

15.216.5VVOL

Minus bias output voltage

Input “L”

‐6‐8‐11V

tPLH“L‐H” propagation time

RG=1.5Ω, f=3kHz, C_load:0.33uF

‐

0.29

‐

ustPHL“H‐L” propagation time

RG=1.5Ω, f=3kHz, C_load:0.33uF

‐

0.15

‐

us

ttimerTimer

Between start and cancel of protection(Under input signal is off state)

1‐

2ms

UVLO+_VCC

Under voltage lock out

VCC voltage (Operation start)

‐

12.6‐

V

UVLO‐_VCC

Under voltage lock out

VCC voltage (Operation stop)

‐

11.7‐

V

Clamp zener voltage

Total zener voltage in collector clamp circuit
at Iz = 1mA , Tj=25 deg C

1270

1340

1410

VSC detect voltage

Collector voltage of IGBT

15‐‐VVz(*1)
VSC*1 : It depends on the condition of use, but actual clamp voltage of collector approximately rises by 300V from 200V to Vz.

Preliminary

page.4

Preliminary
Calculation for gate drive current (gate average current)This product has isolated DCDC converter built in for gate drive.
The maximum output average current is 100mA per one channel.
This current means maximum gate average current.
When you decide the switching frequency,
please check the gate average current by next formula.

Idrive = (Q1＋lQ2l ) X f
 It must be less than 100mA
Idrive : Gate average current
Q1 : Gate charge at +15V (Read from data sheet of IGBT)
Q2 : Gate charge at ‐7V (Read from data sheet of IGBT)
f: Switching frequency of IGBT

Gate charge characteristic of IGBT
VGE
15V

Gate charge
‐7VQ2

Q1

page.5

Circuit diagram
Pin N.o.
1234567891011121314151617181920CN1Pin name
VD
GND
VD
GND
VD
GND
VD
GND
FoH
GND
INH
GND
FoL
GND
INL
GND
NC
GND
NC
GND

Preliminary19
VD

VIN(5V)50

18254917CN11234567891011
121314151617181920

VD
GND
VD
GND
VD
GND
VD
GND
FoH

221C7

GND
INH
GND
FoL
GND
INL
GND
NC
GND
NC
GND

IC2

3546

223

D1C1RG1RG2

VCC1 D7

D8

D4203

DZ6DZ7
DZ8
DZ9E1C2‐1~2‐104821

VEE1R6C5(Ctrip)
HIC1C9447

IC1‐2D2342910k28

RG3RG4

VCC2 D9

D10C3‐1~3‐103M

R5
D11G126

FoH6FoL4531Collector
clamp circuit

D16E1

D5
D6G2

DZ10
DZ11E2

DZ12
DZ13
DZ14
DZ15
DZ16

C4‐1~4‐1030

VEE2C6(Ctrip)

CN1 : 3428‐5002LCPL

D1224

IC1‐110k

DZ3
DZ4
DZ5

D3G1

C1‐1~1‐10C8C1Collector
clamp circuit

D15127233R8

D14R7
D1332
G2Note1)Gate Resistor is not installed at the time of shipment.
Please solder the chosen resistor.
2) C5,6 is not installed at the time of shipment.
It isn’t be needed basically.
But if needed, please solder the chosen condenser.
50V, ceramic, ~ 47pF (rough guide)page.6Preliminary

Application example

IGBT Module

VLA59319VD
RC filter
~10us
VD
(15V)

5V

4.7k

4.7k
MCU

Input signal (5V‐‐‐‐‐15V )VIN(5V)

12345678910111213
1415161718
1920

CN1
VD
GND
VD
GND
VD
GND
VD
GND
FoH
GND
INH
GND
FoL
GND
INL
GND
NC
GND
NC
GND

50

18254917

D1RG1RG2VCC1 D7

D822
1C7IC23546223

C1‐1~1‐103Collector
clamp circuit

D15D3G1D420C8E1

C2‐1~2‐104821C1VEE1C5(Ctrip)

24

IC1‐1

HIC1C910k

447

IC1‐2

D22634
2910k

28

RG3

RG4

VCC2 D9D10

C3‐1~3‐10
FoH

6

FoL

4531
C4‐1~4‐1030

VEE2C6(Ctrip)

12723332Note) About the IC which drives gate signal on input side, it is not recommended to use the one whose output is open collector oropen drain type.

Collector
clamp circuitD16D5G2D6E2page.7

Definition of characteristics
Switching operation
5V
INH, INL

Preliminary

Operation of short circuit protection
INH, INL

50%

Tested by
RG=1.5Ω, C_load=0.33uF
f=3kHz, Duty=50%

VOHVo(22,29 pin of HIC)

Vo(22,29 pin of HIC)

0V‐5V
ttrip

0V

ttimer5V

VOL
FoH, FoL

50%

tPHL

tPLH

Operation flow on detecting short circuit
START

Operation of protection circuit

DETECTION OF
SHORT CIRCUITGATE SOFT SHUTDOWNTIMER STARTOUTPUT ALARMEND OF TIMER

1 ~ 2ms
NoYes
INPUT SIGNAL ISOFFYes
CLEAR ALARM
ENABLE OUTPUT

No(1) In case the gate voltage is “H” and the collector voltage is high, this drive unit will recognize the circuit as shortcircuit and reduce the gate voltage (soft shut down). Besides, put out error signal (”L”) which inform that protection
circuit is operating at the same time from Fo terminal (6,45 pin of CN1).
(2) The protection circuit reset and resort to ordinary condition if input signal is “OFF” when the premised 1~2msec
passed. ( “OFF” period needs 10us or more )(3) When the output rises, the masked time detect short circuit (ttrip) is set up so that on‐time of IGBT can besecured properly.
It is possible to adjust that time by connecting the capacitor (Ctrip) at the point of C5,6 for countermeasure ofmisdetection.

Latch & Timer reset system in short‐circuit protection circuit
Once the short‐circuit protection circuit starts, it shuts down the gate output and keeps alarm output, causing the latch
status. This status is canceled if the input signal is OFF when specific time elapses after the activation of the short‐circuit protection circuit. Then, gate output depending on input signals becomes possible. If the input signal is ON
when specific time elapses, the latch status is not canceled: it is canceled when the signal becomes OFF.
As mentioned above, on the latch & timer reset system, the latch status is resulted after activation of the protection
circuit and shutdown of the gate output. Therefore, during this period, gate output is not made no matter how much
input signals are received. For this reason, it is possible to safely stop the entire equipment by sending error signals to
the microcomputer during this period to stop all gate signals.

page.8

Note about collector clamp circuit (1)The following chart is the collector voltage wave form of IGBT at high current turn off.
This drive unit has collector clamp circuit built in.
As for this clamp circuit, there is effectiveness to control the surge voltage on collector at high current turn off,
but the surge voltage may go over the maximum rating of collector voltage depending on the condition of use.
Therefore please confirm it in the actual machine evaluation.
Finally each parameter must be the following relation. Please keep this condition.

Preliminary

VDC_Link < Vosc_peak < Vz < Voff_surge
200V ~ 300V (rough guide )It depends on the condition of use

Collector voltage wave form
at high current turn off

Voff_surge

Vz : Total zener voltage in collector clamp circuit

Vz

Vosc_peak

VDC_Link

Work of collector clamp circuit
Gate voltage
wave form

The next countermeasures are effective to suppress the rise and oscillationof the collector voltage.
P(1) Reducing the value of L1,L2 and L3(2) Increasing the value of C2(3) Increasing the resistance of off gate resistor(4) Limiting maximum collector current(5) Reducing the VDC_Link

L2L3

L1

C1
Main smoothing
capacitor
NC2

L1:Stray inductance in main smoothing
capacitor
L2:Stray inductance of main wiring
L3:Stray inductance of snubber circuit
C1:Main smoothing capacitor
C2:Snubber capacitor

Snubber capacitor

page.9

Note about collector clamp circuit (2)Preliminary

The total zener voltage in the collector clamp circuit has the tolerance and fluctuation by temperaturesuch as the following chart.
Please keep the main circuit so that the DC_Link voltage does not exceed this zener voltage.

Total zener voltage characteristic
1700

Max

1600
1500
Vz (V)

1400
1300

Typ1200

Min

1100

Iz=1mA

1000
900‐40 ‐20020 40 60 80 100 120 140
Tj (deg C)

Note about collector clamp circuit (3)When the collector clamp circuit operates repeatedly, it may be destroyed for heat.
Therefore please keep it to work non‐consecutively.

page.10

Preliminary

About mounting gate resister
There is not Gate Resistors at the initial state.
It is possible to install up to 2 resistors in mount area of gate resistor per one channel.
And there are some variations by combining resistor.
There are some examples in the following chart, please refer to it and set the gate resistor.
And please solder the chosen resistor.

Drivecircuit

SBD
D7,9

RG1

RG4

RG2

RG3

SBD
D8,10
G1,2

RG1,3

RG2,4: Gate resistor mount part (Initial is open)

Layout pattern connection on substrate

Example 1
SBD

Example 2
SBD

SBD

SBD

Drivecircuit

G1,2

Drivecircuit

G1,2

RG2
RG1,3

RG2,4

RG_on RG1,3
RG_off RG2,4

RGa

RG_on RGa
RG_off RGa

page.11

Outline & Size
Note1) There is not Gate Resistors at the initial state.
So please solder the chosen resistor.

Preliminary

page.12

Preliminary
Keep safety first in your circuit designs!
∙ISAHAYA Electronics Corporation puts the maximum effort into making semiconductor products better and more reliable, butthere is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire orproperty damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures
such as (1) placement of substitutive, auxiliary circuits, (2) use of non‐farmable material or (3) prevention against anymalfunction or mishap.

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