Overview of SINAP Timing System

Electronics GroupBeam Diagnostics & Control Division
SINAP

Outline••••••

v1 timing system structure
v1 hardware
v1 performancev1 in PLS-IIv2 timing system structurev2 hardware

束测控制部电子学组SINAP v1 timing system structure

束测控制部电子学组Hardware List
• SINAP v1 timing system:EVG
EVR
FANOUT
TTL VME Transition Board
Plastic fiber VME Transition Board
Multimode fiber O/E
Plastic fiber O/E

束测控制部电子学组EVG
VME 6U module; A16D32 addressing
Input: 1ch RF clock (0 – 10 dBm)
1ch AC line (3Vp-p typical)
Output: 1ch multi-mode fiber
1ch Sequence RAM trigger(TTL)

束测控制部电子学组EVR
VME 6U module; A16D32 addressing
Input: 1ch multi-mode fiber
1ch interlock input (TTL)
Output: 3ch TTL trigger/clock
3ch LVPECL trigger/clock
1ch CML RF recovery clock
2ch Multi-mode fiber trigger

束测控制部电子学组

FANOUTVME 6U module
Input : 1ch multimode fiber
Output: 12ch multimode fiber

束测控制部电子学组

TTL VME Transition Board
VME transition board
Output: 14ch TTL trigger

束测控制部电子学组Plastic Fiber VME Transition Board
VME transition board;
Output: 14ch optic trigger(Agilent HFBR-1528)

束测控制部电子学组Multi-mode Fiber O/E
Standalone module
Input: 1ch multi-mode fiber
1ch power supply (24V/1A)
Output: 1ch TTL (50ohm)

束测控制部电子学组

Plastic Fiber O/E
Standalone module
Input: 1ch multi-mode fiber
1ch power supply (24V/1A)
Output: 1ch TTL

束测控制部电子学组Performance Testing• Stability
coding-decoding error

束测控制部电子学组Performance Testing• Jitter
EVR TTL output< 6ps

束测控制部电子学组Performance Testing• Jitter
Multi-mode O/E output< 10ps束测控制部电子学组MRF Jitter Performance•

EVR TTL output > 18ps

束测控制部电子学组Performance Testing• Phase Shift
Phase shift with temperature changing (35ps/℃)

束测控制部电子学组v1 in PLS-IIin LINAC control roomin RF station (EVG)
束测控制部电子学组v1 in PLS-IIin Klystron & Modulatorin E-gun束测控制部电子学组V1 in PLS-IIin Storage Ringin Kicker station
束测控制部电子学组

SINAP v2 timing system structure

束测控制部电子学组

System Design• Synchronization
Broadcasting mode

束测控制部电子学组

System Design• Deterministic Data Transfer
Switching mode

束测控制部电子学组System Design• Frame Format
1 byte for trigger code
1 byte for data frame

The minimum interval of trigger is 8ns (2.5Gbps).
束测控制部电子学组System Design• Data Frame Format

4 bytes for address; 8 bytes for data; 1 byte for K28.3
The maximum data transfer rate is 76.9MB/s (2.5Gbps)

束测控制部电子学组Hardware list
• SINAP v2 timing system:
VME-EVO
VME-EVE
PLC-EVR
STD-OE

束测控制部电子学组VME-EVO
Configured to EVG, EVR and FANOUT by software
VME 6U module, A16D32 addressing
Input: 1 RF clock (0 – 10dBm)
1 interlock / AC-line (TTL)
1 fiber (SFP module)
Output: 8 fiber (SFP module)

束测控制部电子学组VME-EVO• Configure to EVG

束测控制部电子学组VME-EVO• Configure to FANOUT

束测控制部电子学组VME-EVO• Configure to EVR

束测控制部电子学组VME-EVE
Configured to EVR
VME 6U module, A16D32 addressing
Input: 1 interlock (TTL)
1 fiber (SFP module)
Output: 8 outputs (TTL)
1 RF recovery clock

束测控制部电子学组VME-EVE

束测控制部电子学组VME-EVE•

RF recovery clock

0x003ff -> event clock
0x03c1f -> 2x event clock
0x18c63 -> 4x event clock…
束测控制部电子学组VME-EVE• RF delay(0,0,0xfffff,0xfffff) -> (0,0x1,0xffffe,0xfffff)
1/20 event clock delay(Synchronized with RF clock)

束测控制部电子学组PLC-EVR
Yokogawa FAM3 series, 1-slot module
Input/Output register mode
external 5V/3A DC power supply is required
Input: 1 fiber (SFP module)
Output: 4 outputs (TTL)

束测控制部电子学组STD-OE
19 inches 1U standard chassis
110/220V 50-60Hz AC power supply
Input: 4 fiber (SFP module)
Output: 4 outputs (TTL)

束测控制部电子学组