CSNS Timing System
G. LeiFeb. 2009

Contents of this talk

• Breif introduction to CSNS
• Requirement investigation• Strategy: based on event timing concept• Progress• Challenges

CSNS Timing System Feb.2009

Page 2CSNS Timing System Feb.2009

Page 3

Layout design based on the geology detection last year

CSNS Timing System Feb.2009

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Accelerator beam power front

CSNS Timing System Feb.2009

Jie WeiPage 5

Beam Travel
Length
FE9m
DTL
38.13mLRBT 170.5m
RSC238.8m
RTBT 123m

CSNS Timing System Feb.2009

Page 6CSNS baseline layout !"#$Jie Wei

RCS 1.6 GeV
25 Hz, 63 µA

H- IS, 50 keV
Ip = 20 mA

Room for higher
energy linac

RFQ, 3 MeV
324 MHz
DTL, 80 MeV
Iave=75 µA

Future proton
applications

Collimation &cleaning

Future medicalapplications

To future second target,
muon target, fast neutron

Target station &neutron instruments
CSNS Timing System Feb.2009

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Requirement investigation
HRFQ
DTL-RF
Inj. Bumpers
RCS RF! ! 8 sets

RCS PS!!

Ext.Kickers
Choppers
CSNS Timing System Feb.2009! ! 10 sets!!
Page 8CSNS timing task (1)• Scheduled timing– H- source– magnet power supply,– injection bumpers and extraction kickers– beam diagnostics– Linac and RCS RF– Target and detectors

CSNS Timing System Feb.2009

Page 9CSNS timing task (2)• Synchronized timing– Triggers to LEBT /MEBT chopping should be
synchronized with RCS RF phase– Triggers to extraction kickers should be
synchronized with RCS beam

CSNS Timing System Feb.2009

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CSNS timing task (3)• Synchronizing clock– 1MHz clock for magnet power supply• RF reference distribution– to linac LLRF and BI• Timestamp and some operating relatedparameters distributed through dedicated event
timing links

CSNS Timing System Feb.2009

Page 11Requirement for triggers
sysdevice

PSnum

delay

pulse

Max.

risingjitter

ChwidthFreqtime(RMS)

delayadjust

scope

step

DTL-Q

76

76

10us

25Hz

<10ns

<100ns

<40us

100ns

RCS-B

1

1

10us

25Hz

<10ns

<100ns

<40us

100ns

RCS-Q

7

10us

25Hz

<10ns

<100ns

<40us

100ns

RCS-C

72

10us

25Hz

<10ns

<100ns

<40us

100ns

RCS RF

LLRF

14

14

1us

25Hz

<10ns

<100ns

<40us

100ns

Inj. Ext.

bumper

2

2

1us

50Hz

5ns

1ns

1ms

5ns

kicker

10101us

50Hz

5ns

1ns

1ms

5ns

chopper

9950us

25Hz

1us

1us

<40us

100ns

sys start

995us

25Hz

<10ns

<100ns

<40us

100ns

RF GATE

9

9200us ~ 800us

25Hz

<10ns

<100ns

<40us

100ns

mod gate

99500us ~

25Hz

<10ns

<100ns

<40us

100ns

Targetlinac LLRF

1ms
H- source

H2 PS

3

3300us

25Hz

<10ns

<100ns

<40us

100ns

Arc PS3

3800us

25Hz

<10ns

<100ns

<40us

100ns

Ext. PS

3

3500us

25Hz

<10ns

<100ns

<40us

100ns

333

333

25Hz

<10ns

<100ns<40us100nsBI

CSNS Timing System Feb.2009

Page 12Strategy: adopting event timing concept

CSNS Timing System Feb.2009

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MRF Event Timing Concept

Event timing systemJukka•

Functionality based on the APS timing system•

Redesigned for SLS ! Series 100•

Improved performance for Diamond ! Series 200•

Timing signals needed for synchronisation of subsystems are applied to
Event Generator (EVG) or generated by EVG•

Timing information is converted to 8-bit event codes and disbtributed to
Event Receivers (EVR) as optical signals•

Event clock rate determines timing resolution:– Minimum clock rate 50 MHz, 20 ns resolution– Maximum clock rate 125 MHz, 8 ns resolution•

8-bit distributed bus running in parallel and independent of timing events
allows distribution of eight signals updated with the event clock rate

CSNS Timing System Feb.2009

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CSNS Timing System Feb.2009

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EVR%&'(EVR

CSNS Timing System Feb.2009PageStrategy: adopting event timing concept•

Event Generator (EVG), Event Receiver (EVR)•Multi-mode optical fiber between EVG and Fanout/EVR•

8 bit event codes and 8 clock•

Timestamp and data buffer•Heartbeat monitor•Interlock input to disable some outputs•

Fine grained adjustable output pulses and clock frequencies.

CSNS Timing System Feb.2009

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Framework

MasterOscillator
324MHzSplitter

EVG
FanoutE/O
EVR

FanoutNeutron
troppers

EVR
RTBT

DTL

LLRF
CSNS Timing System Feb.2009

ModPS

MG
PS

1MHz

EVR

25Hz

Front End

O/E

25Hz

EVR

324MHz

O/E

O/E
LRBT

EVR

O/E
EVR
RCS inj

O/E
EVR
RCS ext

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Progress

Design the CSNS timing system using EVG/EVR
Using experience of BEPCII timing system, but requirements
different• Decide the event clock– 324MHz/4 = 81MHz• Calculate the parameters for Fractional-N synthesizer– Work out several equations and inequalities

CSNS Timing System Feb.2009

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Fractional Synthesiser•

A Micrel (http://www.micrel.com) SY87739L Protocol Transparent
Fractional-N Synthesiser with a reference clock of 24 MHz is used in
EVG. By correctly setting the parameters in this circuit, we can get
proper frequency for CSNS timing system.

CSNS Timing System Feb.2009

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Calculate parameters of Fractional-N synthesizer
fVCO (min) = 540MHz, fVCO (max) = 729MHzCSNS Timing System Feb.2009

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Calculate parameters of Fractional-N synthesizer• fref=24MHz, event clock=81MHz• 24 * (P - Qp-1/(Qp-1 + Qp)) / PostDivSel=81,540 < 24 * (P - Qp-1/(Qp-1 + Qp)) < 729,
• P=24, QP-1=3, QP=5, PostDivSel=7, N=M=14• 0000 qp qpm1 divsel 000 PostDivSel NdivSel MdivSel0000 00101 00011 0111 000 00111 101 101= 0x028d c1ed

CSNS Timing System Feb.2009

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Progress (cont.)• Very preliminary design• Prototype 1– Got official approval– Hardware ordered but not reached us– Several experiments done using BEPCII spare parts

CSNS Timing System Feb.2009

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324MHz measured from EVR230, done by Guanglei Xu

CSNS Timing System Feb.2009

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50Hz (324MHz/4/1620000) generated from event clock in EVG, done byGuanglei Xu

CSNS Timing System Feb.2009

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Interlock design – using UNIV-TTL-IN

CSNS Timing System Feb.2009

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Challenges• Interlock realization• Synchronized timing• Timestamp distribution by timing system to control
systemCSNS Timing System Feb.2009

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Thank you all for yourattention
Referenece (documents, discussions)1.

China Spallation Neutron Source, Jei Wei, etc.

2.

Front End, Ouyang Huafu, 2007/5/1

3.

Linac LLRF, LI Jian,etc.

4.

Injection and Extraction, Tang Jingyu, Chi Yunong, Shen Li, etc.

5.

CSNS Beam Diagnostics, Xu Taoguang

6.

Discussions with Wang Sheng, Zhang Jing, etc.

7.

EPICS Collaboration Meeting, ANL, Argonne, Jukka Pietarinen,
Micro-Research Finland Oy.

CSNS Timing System Feb.2009

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