Data SheetADXL345
3-Axis, ±2 g/±4 g/±8 g/±16 g Digital Accelerometer► Gaming and pointing devices

FEATURES► Industrial instrumentation► Ultralow power: as low as 23 µA in measurement mode and► Personal navigation devices

0.1 µA in standby mode at VS = 2.5 V (typical)► Power consumption scales automatically with bandwidth► Hard disk drive (HDD) protection► User-selectable resolution

GENERAL DESCRIPTION► Fixed 10-bit resolution

The ADXL345 is a small, thin, ultralow power, 3-axis accelerometerwith high resolution (13-bit) measurement at up to ±16 g. Digital
output data is formatted as 16-bit twos complement and is accessible through either a SPI (3- or 4-wire) or I2C digital interface.

► Full resolution, where resolution increases with g range, up to

13-bit resolution at ±16 g (maintaining 4 mg/LSB scale factor
in all g ranges)► Embedded memory management system with FIFO technology
minimizes host processor load
► Single tap/double tap detection► Activity/inactivity monitoring► Free-fall detection► Supply voltage range: 2.0 V to 3.6 V► I/O voltage range: 1.7 V to VS► SPI (3- and 4-wire) and I2C digital interfaces► Flexible interrupt modes mappable to either interrupt pin► Measurement ranges selectable via serial command► Bandwidth selectable via serial command► Wide temperature range (−40°C to +85°C)► 10,000 g shock survival► Pb free/RoHS compliant► Small and thin: 3 mm × 5 mm × 1 mm LGA package

The ADXL345 is well suited for mobile device applications. It measures the static acceleration of gravity in tilt-sensing applications, aswell as dynamic acceleration resulting from motion or shock. Its
high resolution (3.9 mg/LSB) enables measurement of inclination
changes less than 1.0°.
Several special sensing functions are provided. Activity and inactivity sensing detect the presence or lack of motion by comparing
the acceleration on any axis with user-set thresholds. Tap sensing
detects single and double taps in any direction. Free-fall sensing
detects if the device is falling. These functions can be mapped
individually to either of two interrupt output pins. An integrated
memory management system with a 32-level first in, first out (FIFO)
buffer can be used to store data to minimize host processor activity
and lower overall system power consumption.
Low power modes enable intelligent motion-based power management with threshold sensing and active acceleration measurement
at extremely low power dissipation.

APPLICATIONSThe ADXL345 is supplied in a small, thin, 3 mm × 5 mm × 1 mm,
14-lead, plastic package.

► Handsets► Medical instrumentation

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

Rev. G
DOCUMENT FEEDBACKTECHNICAL SUPPORTInformation furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject tochange without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks andregistered trademarks are the property of their respective owners.

Data SheetADXL345TABLE OF CONTENTS
Features................................................................ 1
Applications........................................................... 1
General Description...............................................1
Functional Block Diagram......................................1
Specifications........................................................ 3
Absolute Maximum Ratings...................................5
Thermal Resistance........................................... 5
Recommended Soldering Profile........................5
ESD Caution.......................................................5
Pin Configuration and Function Descriptions........ 6
Typical Performance Characteristics..................... 7
Theory of Operation.............................................12
Power Sequencing........................................... 12Power Savings................................................. 13
Serial Communications........................................14
SPI....................................................................14
I2C.................................................................... 17
Interrupts............................................................. 19
DATA_READY..................................................20
SINGLE_TAP................................................... 20
DOUBLE_TAP..................................................20
Activity.............................................................. 20
Inactivity........................................................... 20
FREE_FALL..................................................... 20
Watermark........................................................20
Overrun............................................................ 20
FIFO.................................................................... 21

Bypass Mode....................................................21
FIFO Mode....................................................... 21
Stream Mode....................................................21
Trigger Mode.................................................... 21
Retrieving Data from FIFO............................... 21
Self-Test...............................................................22
Register Map....................................................... 23
Register Definitions.......................................... 24
Applications Information...................................... 29
Power Supply Decoupling................................ 29
Mechanical Considerations for Mounting......... 29
Tap Detection................................................... 29
Threshold......................................................... 30
Link Mode.........................................................30
Sleep Mode vs. Low Power Mode....................30
Offset Calibration..............................................30
Using Self-Test................................................. 31
Asynchronous Data Readings..........................32
Data Formatting of Upper Data Rates..............32
Noise Performance...........................................33
Operation at Voltages Other Than 2.5 V.......... 34
Offset Performance at Lowest Data Rates.......34
Axes of Acceleration Sensitivity....................... 35
Layout and Design Recommendations............ 35
Outline Dimensions............................................. 36
Ordering Guide.................................................36
Evaluation Boards............................................ 36

REVISION HISTORY
5/2022—Rev. F to Rev. G
Deleted Package Information Section..............................................................................................................5
Added Recommended Soldering Profile Section.............................................................................................5
Moved Figure 2 and Table 4............................................................................................................................ 5
Moved Table 13..............................................................................................................................................19
Change to Using Self-Test Section................................................................................................................ 31
Added Asynchronous Data Readings Section............................................................................................... 32

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Data SheetADXL345

SPECIFICATIONSTA = 25°C, VS = 2.5 V, VDD I/O = 1.8 V, acceleration = 0 g, CS = 10 µF tantalum, CI/O = 0.1 µF, output data rate (ODR) = 800 Hz, unlessotherwise noted. All minimum and maximum specifications are guaranteed. Typical specifications are not guaranteed.
Table 1.
Parameter

Test Conditions

SENSOR INPUT

Each axis

Min

Typ1

Max

Unit

Measurement Range

User selectable±2, ±4, ±8, ±16gNonlinearity

Percentage of full scale

±0.5

%

±0.1

Degrees±1%

Inter-Axis Alignment Error
Cross-Axis Sensitivity2
OUTPUT RESOLUTION

Each axis

All g Ranges

10-bit resolution

10

Bits

±2 g Range

Full resolution

10

Bits

±4 g Range

Full resolution

11

Bits

±8 g Range

Full resolution

12

Bits

±16 g Range

Full resolution

13

Bits

SENSITIVITY
Sensitivity at XOUT, YOUT, ZOUT

Each axis
All g-ranges, full resolution

230

256

282

LSB/g

±2 g, 10-bit resolution

230

256

282

LSB/g

±4 g, 10-bit resolution

115

128

141

LSB/g

±8 g, 10-bit resolution

57

64

71

LSB/g

±16 g, 10-bit resolution

29

32

35

LSB/g

Sensitivity Deviation from Ideal

All g-ranges

Scale Factor at XOUT, YOUT, ZOUTAll g-ranges, full resolution

3.5

±1.0
3.9

4.3

mg/LSB±2 g, 10-bit resolution

3.5

3.9

4.3

mg/LSB±4 g, 10-bit resolution

7.1

7.8

8.7

mg/LSB±8 g, 10-bit resolution

14.1

15.6

17.5

mg/LSB±16 g, 10-bit resolution

28.6

31.2

34.5

mg/LSB

Sensitivity Change Due to Temperature
0 g OFFSET

%

±0.01

%/°C

Each axis

0 g Output for XOUT, YOUT

−150

0

+150

mg

0 g Output for ZOUT

−250

0

+250

mg

0 g Output Deviation from Ideal, XOUT, YOUT

±35

mg

0 g Output Deviation from Ideal, ZOUT

±40

mg

0 g Offset vs. Temperature for X-, Y-Axes

±0.4

mg/°C

0 g Offset vs. Temperature for Z-Axis

±1.2

mg/°C

0.75

LSB rms

1.1

LSB rmsNOISE
X-, Y-Axes
ODR = 100 Hz for ±2 g, 10-bit resolution or
all g-ranges, full resolution
Z-AxisODR = 100 Hz for ±2 g, 10-bit resolution or
all g-ranges, full resolution
OUTPUT DATA RATE AND BANDWIDTH
Output Data Rate (ODR)3, 4, 5User selectable
0.1

3200

Hz

0.20

2.10

g

SELF-TEST6
Output Change in X-Axis
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Data SheetADXL345

SPECIFICATIONS
Table 1.
Parameter

Test Conditions

Min

Typ1

Max

Unit

Output Change in Y-Axis

−2.10

−0.20

g

Output Change in Z-Axis

0.30

3.40

g

POWER SUPPLY
Operating Voltage Range (VS)

2.0

2.5

3.6

V

Interface Voltage Range (VDD I/O)

1.7

1.8

VS

V

Supply Current

ODR ≥ 100 Hz

140

µA

ODR < 10 Hz

30

µA

0.1

µA

ODR = 3200 Hz

1.4

ms

Standby Mode Leakage Current
Turn-On and Wake-Up Time7
TEMPERATURE
Operating Temperature Range

−40

+85

°C

WEIGHT
Device Weight
1

30

mg

The typical specifications shown are for at least 68% of the population of parts and are based on the worst case of mean ±1 σ, except for 0 g output and sensitivity, which
represents the target value. For 0 g offset and sensitivity, the deviation from the ideal describes the worst case of mean ±1 σ.

2

Cross-axis sensitivity is defined as coupling between any two axes.

3

Bandwidth is the −3 dB frequency and is half the output data rate, bandwidth = ODR/2.

4

The output format for the 3200 Hz and 1600 Hz ODRs is different than the output format for the remaining ODRs. This difference is described in the Data Formatting ofUpper Data Rates section.

5

Output data rates below 6.25 Hz exhibit additional offset shift with increased temperature, depending on selected output data rate. Refer to the Offset Performance at
Lowest Data Rates section for details.

6

Self-test change is defined as the output (g) when the SELF_TEST bit = 1 (in the DATA_FORMAT register, Address 0x31) minus the output (g) when the SELF_TEST bit= 0. Due to device filtering, the output reaches its final value after 4 × τ when enabling or disabling self-test, where τ = 1/(data rate). The part must be in normal power
operation (LOW_POWER bit = 0 in the BW_RATE register, Address 0x2C) for self-test to operate correctly.

7

Turn-on and wake-up times are determined by the user-defined bandwidth. At a 100 Hz data rate, the turn-on and wake-up times are each approximately 11.1 ms. For otherdata rates, the turn-on and wake-up times are each approximately τ + 1.1 in milliseconds, where τ = 1/(data rate).

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Data SheetADXL345

ABSOLUTE MAXIMUM RATINGSRECOMMENDED SOLDERING PROFILE

Table 2.
Parameter

RatingFigure 2 and Table 4 provide details about the recommended
soldering profile.

Acceleration
Any Axis, Unpowered

10,000 g

Any Axis, Powered

10,000 g

VS−0.3 V to +3.9 V

VDD I/O−0.3 V to +3.9 V

Digital Pins

−0.3 V to VDD I/O + 0.3 V or 3.9 V,
whichever is less

All Other Pins
Output Short-Circuit Duration (Any Pin
to Ground)Temperature Range−0.3 V to +3.9 V
Indefinite
Figure 2. Recommended Soldering Profile

Powered−40°C to +105°C

Storage−40°C to +105°C

Table 4. Recommended Soldering Profile1, 2Condition

Stresses at or above those listed under Absolute Maximum Ratings
may cause permanent damage to the product. This is a stressrating only; functional operation of the product at these or any otherconditions above those indicated in the operational section of thisspecification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.

Profile Feature

Sn63/Pb37

Average Ramp Rate from Liquid Temperature(TL) to Peak Temperature (TP)3°C/sec max- 3°C/sec maxiimum
mum

Preheat

THERMAL RESISTANCE
Table 3. Package Characteristics
Package Type

θJA

θJC

Device Weight

14-Terminal LGA

150°C/W

85°C/W

30 mg

Pb-Free

Minimum Temperature (TSMIN)

100°C

150°C

Maximum Temperature (TSMAX)

150°C

200°C

Time from TSMIN to TSMAX (tS)

60 sec to 120 60 sec to 180
sec
sec

TSMAX to TL Ramp-Up Rate

3°C/sec max- 3°C/sec maxiimum
mum

Liquid Temperature (TL)

183°C

Time Maintained Above TL (tL)

60 sec to 150 60 sec to 150
sec
sec

Peak Temperature (TP)240 + 0/−5°C 260 + 0/−5°C

Time of Actual TP − 5°C (tP)

10 sec to 30
sec

Ramp-Down Rate

6°C/sec max- 6°C/sec maxiimum
mumTime 25°C to Peak Temperature

6 minutes
maximum

217°C

20 sec to 40
sec

8 minutes
maximum

1

Based on JEDEC Standard J-STD-020D.1.

2

For best results, the soldering profile should be in accordance with the recommendations of the manufacturer of the solder paste used.

ESD CAUTION
ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although
this product features patented or proprietary protection circuitry,damage may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to avoid
performance degradation or loss of functionality.

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Data SheetADXL345

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 3. Pin Configuration (Top View)
Table 5. Pin Function Descriptions
Pin No.

Mnemonic

Description

1

VDD I/O

Digital Interface Supply Voltage.

2

GND

This pin must be connected to ground.

3

RESERVED

Reserved. This pin must be connected to VS or left open.

4

GND

This pin must be connected to ground.

5

GND

This pin must be connected to ground.

6VS

Supply Voltage.

7

CS

Chip Select.

8

INT1

Interrupt 1 Output.

9

INT2

Interrupt 2 Output.

10

NC

Not Internally Connected.

11

RESERVED

Reserved. This pin must be connected to ground or left open.

12

SDO/ALT ADDRESS

Serial Data Output (SPI 4-Wire)/Alternate I2C Address Select (I2C).

13

SDA/SDI/SDIO

Serial Data (I2C)/Serial Data Input (SPI 4-Wire)/Serial Data Input and Output (SPI 3-Wire).

14

SCL/SCLK

Serial Communications Clock. SCL is the clock for I2C, and SCLK is the clock for SPI.

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Data SheetADXL345

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 4. X-Axis Zero g Offset at 25°C, VS = 2.5 V

Figure 7. X-Axis Zero g Offset at 25°C, VS = 3.3 V

Figure 5. Y-Axis Zero g Offset at 25°C, VS = 2.5 V

Figure 8. Y-Axis Zero g Offset at 25°C, VS = 3.3 V

Figure 6. Z-Axis Zero g Offset at 25°C, VS = 2.5 V

Figure 9. Z-Axis Zero g Offset at 25°C, VS = 3.3 V

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Data SheetADXL345

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 10. X-Axis Zero g Offset Temperature Coefficient, VS = 2.5 V

Figure 11. Y-Axis Zero g Offset Temperature Coefficient, VS = 2.5 V

Figure 13. X-Axis Zero g Offset vs. Temperature—45 Parts Soldered to PCB,
VS = 2.5 V

Figure 14. Y-Axis Zero g Offset vs. Temperature—45 Parts Soldered to PCB,
VS = 2.5 V

Figure 12. Z-Axis Zero g Offset Temperature Coefficient, VS = 2.5 V
Figure 15. Z-Axis One g Offset vs. Temperature—45 Parts Soldered to PCB,
VS = 2.5 V

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Data SheetADXL345

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 16. X-Axis Sensitivity at 25°C, VS = 2.5 V, Full Resolution

Figure 19. X-Axis Sensitivity Temperature Coefficient, VS = 2.5 V

Figure 17. Y-Axis Sensitivity at 25°C, VS = 2.5 V, Full Resolution

Figure 20. Y-Axis Sensitivity Temperature Coefficient, VS = 2.5 V

Figure 18. Z-Axis Sensitivity at 25°C, VS = 2.5 V, Full Resolution

Figure 21. Z-Axis Sensitivity Temperature Coefficient, VS = 2.5 V

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Data SheetADXL345

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 22. X-Axis Sensitivity vs. Temperature—Eight Parts Soldered to PCB,
VS = 2.5 V, Full Resolution

Figure 25. X-Axis Sensitivity vs. Temperature—Eight Parts Soldered to PCB,
VS = 3.3 V, Full Resolution

Figure 23. Y-Axis Sensitivity vs. Temperature—Eight Parts Soldered to PCB,
VS = 2.5 V, Full Resolution

Figure 26. Y-Axis Sensitivity vs. Temperature—Eight Parts Soldered to PCB,
VS = 3.3 V, Full Resolution

Figure 24. Z-Axis Sensitivity vs. Temperature—Eight Parts Soldered to PCB,
VS = 2.5 V, Full Resolution

Figure 27. Z-Axis Sensitivity vs. Temperature—Eight Parts Soldered to PCB,
VS = 3.3 V, Full Resolution

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Data SheetADXL345

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 28. X-Axis Self-Test Response at 25°C, VS = 2.5 V

Figure 31. Current Consumption at 25°C, 100 Hz Output Data Rate, VS = 2.5 V

Figure 29. Y-Axis Self-Test Response at 25°C, VS = 2.5 V

Figure 32. Current Consumption vs. Output Data Rate at 25°C—10 Parts, VS =2.5 V

Figure 30. Z-Axis Self-Test Response at 25°C, VS = 2.5 V

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Figure 33. Supply Current vs. Supply Voltage, VS at 25°C

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Data SheetADXL345

THEORY OF OPERATIONThe ADXL345 is a complete 3-axis acceleration measurement
system with a selectable measurement range of ±2 g, ±4 g, ±8 g, or±16 g. It measures both dynamic acceleration resulting from motion
or shock and static acceleration, such as gravity, that allows thedevice to be used as a tilt sensor.
The sensor is a polysilicon surface-micromachined structure built
on top of a silicon wafer. Polysilicon springs suspend the structure
over the surface of the wafer and provide a resistance against
forces due to applied acceleration.
Deflection of the structure is measured using differential capacitorsthat consist of independent fixed plates and plates attached to themoving mass. Acceleration deflects the proof mass and unbalances
the differential capacitor, resulting in a sensor output whose amplitude is proportional to acceleration. Phase-sensitive demodulation
is used to determine the magnitude and polarity of the acceleration.
POWER SEQUENCING
Power can be applied to VS or VDD I/O in any sequence without
damaging the ADXL345. All possible power-on modes are summar-

ized in Table 6. The interface voltage level is set with the interface
supply voltage, VDD I/O, which must be present to ensure that the
ADXL345 does not create a conflict on the communication bus.
For single-supply operation, VDD I/O can be the same as the main
supply, VS. In a dual-supply application, however, VDD I/O can differ
from VS to accommodate the desired interface voltage, as longas VS is greater than or equal to VDD I/O. When power cycling isrequired, VS and VDD I/O must be completely discharged (to GND)
before powering the device back on.
After VS is applied, the device enters standby mode, where power
consumption is minimized and the device waits for VDD I/O to be
applied and for the command to enter measurement mode to bereceived. (This command can be initiated by setting the measure bit(Bit D3) in the POWER_CTL register (Address 0x2D).) In addition,
while the device is in standby mode, any register can be written toor read from to configure the part. It is recommended to configure
the device in standby mode and then to enable measurement
mode. Clearing the measure bit returns the device to the standby
mode.

Table 6. Power Sequencing
ConditionVS

VDD I/O

Description

Power Off

Off

Off

Bus Disabled

On

Off

Bus Enabled

Off

On

Standby or Measurement

On

On

The device is completely off, but there is a potential for a communication bus conflict.
The device is on in standby mode, but communication is unavailable and creates a conflict on the communication bus.
The duration of this state should be minimized during power-up to prevent a conflict.
No functions are available, but the device does not create a conflict on the communication bus.
At power-up, the device is in standby mode, awaiting a command to enter measurement mode, and all sensor functions
are off. After the device is instructed to enter measurement mode, all sensor functions are available.

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Data SheetADXL345

THEORY OF OPERATIONPOWER SAVINGS

Table 8. Typical Current Consumption vs. Data Rate, Low Power Mode (TA =25°C, VS = 2.5 V, VDD I/O = 1.8 V)

Power Modes

Output Data Rate(Hz)

Bandwidth (Hz)Rate CodeIDD (µA)

400

200

1100

90

200

100

1011

60

100

50

1010

50

50

25

1001

45

25

12.5

1000

40

12.5

6.25

0111

34

The ADXL345 automatically modulates its power consumption in
proportion to its output data rate, as outlined in Table 7. If additional power savings is desired, a lower power mode is available.
In this mode, the internal sampling rate is reduced, allowing for
power savings in the 12.5 Hz to 400 Hz data rate range at theexpense of slightly greater noise. To enter low power mode, set
the LOW_POWER bit (Bit 4) in the BW_RATE register (Address
0x2C). Table 8 shows the current consumption in low power modefor cases where there is an advantage to using low power mode.
Use of low power mode for a data rate not shown in Table 8 does
not provide any advantage over the same data rate in normal power
mode. Therefore, it is recommended that only data rates shownin Table 8 be used in low power mode. The current consumption
values shown in Table 7 and Table 8 are for a VS of 2.5 V.
Table 7. Typical Current Consumption vs. Data Rate (TA = 25°C, VS = 2.5 V,
VDD I/O = 1.8 V)

Auto Sleep Mode
Additional power can be saved if the ADXL345 automaticallyswitches to sleep mode during periods of inactivity. To enable thisfeature, set the THRESH_INACT register (Address 0x25) and the
TIME_INACT register (Address 0x26) each to a value that signifies
inactivity (the appropriate value depends on the application), andthen set the AUTO_SLEEP bit (Bit D4) and the link bit (Bit D5) inthe POWER_CTL register (Address 0x2D). Current consumption at
the sub-12.5 Hz data rates that are used in this mode is typically 23µA for a VS of 2.5 V.

Output Data Rate(Hz)

Bandwidth (Hz)Rate CodeIDD (µA)

3200

1600

1111

140

1600

800

1110

90

Standby Mode

800

400

1101

140

400

200

1100

140

200

100

1011

140

100

50

1010

140

50

25

1001

90

25

12.5

1000

60

For even lower power operation, standby mode can be used. In
standby mode, current consumption is reduced to 0.1 µA (typical).
In this mode, no measurements are made. Enter standby modeby clearing the measure bit (Bit D3) in the POWER_CTL register(Address 0x2D). Placing the device into standby mode preserves
the contents of FIFO.

12.5

6.25

0111

50

6.25

3.13

0110

45

3.13

1.56

0101

40

1.56

0.78

0100

34

0.78

0.39

0011

23

0.39

0.20

0010

23

0.20

0.10

0001

23

0.10

0.05

0000

23

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Data SheetADXL345SERIAL COMMUNICATIONS
I2C and SPI digital communications are available. In both cases, theADXL345 operates as a slave. I2C mode is enabled if the CS pin is
tied high to VDD I/O. The CS pin should always be tied high to VDD
I/O or be driven by an external controller because there is no default
mode if the CS pin is left unconnected. Therefore, not taking theseprecautions may result in an inability to communicate with the part.
In SPI mode, the CS pin is controlled by the bus master. In both SPI
and I2C modes of operation, data transmitted from the ADXL345 to
the master device should be ignored during writes to the ADXL345.
SPI
For SPI, either 3- or 4-wire configuration is possible, as shownin the connection diagrams in Figure 34 and Figure 35. Clearing
the SPI bit (Bit D6) in the DATA_FORMAT register (Address 0x31)
selects 4-wire mode, whereas setting the SPI bit selects 3-wire
mode. The maximum SPI clock speed is 5 MHz with 100 pF
maximum loading, and the timing scheme follows clock polarity(CPOL) = 1 and clock phase (CPHA) = 1. If power is applied
to the ADXL345 before the clock polarity and phase of the hostprocessor are configured, the CS pin should be brought high beforechanging the clock polarity and phase. When using 3-wire SPI, it
is recommended that the SDO pin be either pulled up to VDD I/O orpulled down to GND via a 10 kΩ resistor.

Figure 34. 3-Wire SPI Connection Diagram

Figure 35. 4-Wire SPI Connection Diagram

CS is the serial port enable line and is controlled by the SPI master.
This line must go low at the start of a transmission and high at theend of a transmission, as shown in Figure 37. SCLK is the serial
port clock and is supplied by the SPI master. SCLK should idle highduring a period of no transmission. SDI and SDO are the serial data
input and output, respectively. Data is updated on the falling edgeof SCLK and should be sampled on the rising edge of SCLK.

(MB in Figure 37 to Figure 39), must be set. After the register
addressing and the first byte of data, each subsequent set of clock
pulses (eight clock pulses) causes the ADXL345 to point to the next
register for a read or write. This shifting continues until the clock
pulses cease and CS is deasserted. To perform reads or writes on
different, nonsequential registers, CS must be deasserted between
transmissions and the new register must be addressed separately.
The timing diagram for 3-wire SPI reads or writes is shown in Figure 39. The 4-wire equivalents for SPI writes and reads are shownin Figure 37 and Figure 38, respectively. For correct operation of
the part, the logic thresholds and timing parameters in Table 9 andTable 10 must be met at all times.
Use of the 3200 Hz and 1600 Hz output data rates is only recommended with SPI communication rates greater than or equal to
2 MHz. The 800 Hz output data rate is recommended only forcommunication speeds greater than or equal to 400 kHz, andthe remaining data rates scale proportionally. For example, theminimum recommended communication speed for a 200 Hz output
data rate is 100 kHz. Operation at an output data rate above therecommended maximum may result in undesirable effects on theacceleration data, including missing samples or additional noise.
Preventing Bus Traffic Errors
The ADXL345 CS pin is used both for initiating SPI transactions,and for enabling I2C mode. When the ADXL345 is used on a SPI
bus with multiple devices, its CS pin is held high while the mastercommunicates with the other devices. There may be conditions
where a SPI command transmitted to another device looks like avalid I2C command. In this case, the ADXL345 would interpret thisas an attempt to communicate in I2C mode, and could interfere withother bus traffic. Unless bus traffic can be adequately controlled toassure such a condition never occurs, it is recommended to add alogic gate in front of the SDI pin as shown in Figure 36. This OR
gate will hold the SDA line high when CS is high to prevent SPI bus
traffic at the ADXL345 from appearing as an I2C start command.

Figure 36. Recommended SPI Connection Diagram when Using Multiple SPI
Devices on a Single Bus

To read or write multiple bytes in a single transmission, the multiple-byte bit, located after the R/W bit in the first byte transfer

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Data SheetADXL345SERIAL COMMUNICATIONS

Figure 37. SPI 4-Wire Write

Figure 38. SPI 4-Wire Read

Figure 39. SPI 3-Wire Read/Write
Table 9. SPI Digital Input/Output
Limit1
Parameter

Test Conditions

Min

Digital Input
Low Level Input Voltage (VIL)High Level Input Voltage (VIH)

Max

Unit

0.3 × VDD I/O

V

0.7 × VDD I/OV

Low Level Input Current (IIL)

VIN = VDD I/OHigh Level Input Current (IIH)

VIN = 0 V

Digital Output
Low Level Output Voltage (VOL)IOL = 10 mA

High Level Output Voltage (VOH)

IOH = −4 mA

0.8 × VDD I/OV

Low Level Output Current (IOL)

VOL = VOL, max

10mA

High Level Output Current (IOH)

VOH = VOH, min−4mA

fIN = 1 MHz, VIN = 2.5 V

8pF

Pin Capacitance
1

0.1
−0.1

µA
µA

0.2 × VDD I/OVLimits based on characterization results, not production tested.

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Data SheetADXL345SERIAL COMMUNICATIONS
Table 10. SPI Timing (TA = 25°C, VS = 2.5 V, VDD I/O = 1.8 V)1Limit2, 3
Parameter

Min

fSCLK

Max

Unit

Description

5

MHz

SPI clock frequency

tSCLK

200

ns

1/(SPI clock frequency) mark-space ratio for the SCLK input is 40/60 to 60/40

tDELAY5ns

CS falling edge to SCLK falling edgetQUIET

5

ns

SCLK rising edge to CS rising edgens

CS rising edge to SDO disabled

tDIS

10

tCS,DIS150

ns

CS deassertion between SPI communications

tS

0.3 × tSCLK

ns

SCLK low pulse width (space)tM

0.3 × tSCLK

ns

SCLK high pulse width (mark)tSETUP

5ns

SDI valid before SCLK rising edge

tHOLD

5

tSDO

40

ns

SDI valid after SCLK rising edge

ns

SCLK falling edge to SDO/SDIO output transition

t R4

20

ns

SDO/SDIO output high to output low transition

tF4

20

ns

SDO/SDIO output low to output high transition

1

The CS, SCLK, SDI, and SDO pins are not internally pulled up or down; they must be driven for proper operation.

2

Limits based on characterization results, characterized with fSCLK = 5 MHz and bus load capacitance of 100 pF; not production tested.

3

The timing values are measured corresponding to the input thresholds (VIL and VIH) given in Table 9.

4

Output rise and fall times measured with capacitive load of 150 pF.

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Rev. G | 16 of 36

Data SheetADXL345SERIAL COMMUNICATIONS
I2CWith CS tied high to VDD I/O, the ADXL345 is in I2C mode, requiring
a simple 2-wire connection, as shown in Figure 40. The ADXL345
conforms to the UM10204 I2C-Bus Specification and User Manual,
Rev. 03—19 June 2007, available from NXP Semiconductors. It
supports standard (100 kHz) and fast (400 kHz) data transfer
modes if the bus parameters given in Table 11 and Table 12
are met. Single- or multiple-byte reads/writes are supported, as
shown in Figure 41. With the ALT ADDRESS pin high, the 7-bit
I2C address for the device is 0x1D, followed by the R/W bit. Thistranslates to 0x3A for a write and 0x3B for a read. An alternate
I2C address of 0x53 (followed by the R/W bit) can be chosen bygrounding the SDO/ALT ADDRESS pin (Pin 12). This translates to
0xA6 for a write and 0xA7 for a read.
There are no internal pull-up or pull-down resistors for any unused
pins; therefore, there is no known state or default state for the CS
or ALT ADDRESS pin if left floating or unconnected. It is requiredthat the CS pin be connected to VDD I/O and that the ALT ADDRESS
pin be connected to either VDD I/O or GND when using I2C.

change in the I2C communication speed. For example, using I2C
at 100 kHz would limit the maximum ODR to 200 Hz. Operation at
an output data rate above the recommended maximum may resultin undesirable effect on the acceleration data, including missing
samples or additional noise.

Figure 40. I2C Connection Diagram (Address 0x53)

If other devices are connected to the same I2C bus, the nominal operating voltage level of these other devices cannot exceed VDD I/O
by more than 0.3 V. External pull-up resistors, RP, are necessary forproper I2C operation. Refer to the UM10204 I2C-Bus Specificationand User Manual, Rev. 03—19 June 2007, when selecting pull-up
resistor values to ensure proper operation.

Due to communication speed limitations, the maximum output data
rate when using 400 kHz I2C is 800 Hz and scales linearly with a
Table 11. I2C Digital Input/Output
Limit1
Parameter

Test Conditions

Min

Digital Input
Low Level Input Voltage (VIL)

0.3 × VDD I/OHigh Level Input Voltage (VIH)
VIN = VDD I/OHigh Level Input Current (IIH)

VIN = 0 V

Low Level Output Current (IOL)
Pin Capacitance1

0.7 × VDD I/O

Low Level Input Current (IIL)
Digital Output
Low Level Output Voltage (VOL)

Max

Unit
V
V

0.1
−0.1

µA
µA

VDD I/O < 2 V, IOL = 3 mA

0.2 × VDD I/OV

VDD I/O ≥ 2 V, IOL = 3 mA

400

mV

8

pF

VOL = VOL, max
fIN = 1 MHz, VIN = 2.5 V

3mA

Limits based on characterization results; not production tested.

Figure 41. I2C Device Addressing
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Data SheetADXL345SERIAL COMMUNICATIONS
Table 12. I2C Timing (TA = 25°C, VS = 2.5 V, VDD I/O = 1.8 V)
Limit1, 2
Parameter

Min

fSCL

Max

Unit

Description

400

kHz

SCL clock frequency

t1

2.5

µs

SCL cycle time

t2

0.6

µs

tHIGH, SCL high time

t3

1.3

µs

tLOW, SCL low time

t4

0.6

µs

tHD, STA, start/repeated start condition hold timenstSU, DAT, data setup timeµs

tHD, DAT, data hold time

t5

100

t63, 4, 5, 6

0

t7

0.6

µs

tSU, STA, setup time for repeated start

t8

0.6

µs

tSU, STO, stop condition setup time

t9

1.3

µs

tBUF, bus-free time between a stop condition and a start condition

nstR, rise time of both SCL and SDA when receiving

nstR, rise time of both SCL and SDA when receiving or transmittingnstF, fall time of SDA when receiving

t10

0.9

300
0

t11

300
250

ns

tF, fall time of both SCL and SDA when transmitting

Cb

400

pF

Capacitive load for each bus line

1

Limits based on characterization results, with fSCL = 400 kHz and a 3 mA sink current; not production tested.

2

All values referred to the VIH and the VIL levels given in Table 11.

3

t6 is the data hold time that is measured from the falling edge of SCL. It applies to data in transmission and acknowledge.

4

A transmitting device must internally provide an output hold time of at least 300 ns for the SDA signal (with respect to VIH(min) of the SCL signal) to bridge the undefined
region of the falling edge of SCL.

5

The maximum t6 value must be met only if the device does not stretch the low period (t3) of the SCL signal.

6

The maximum value for t6 is a function of the clock low time (t3), the clock rise time (t10), and the minimum data setup time (t5(min)). This value is calculated as t6(max) = t3 −t10 − t5(min).

Figure 42. I2C Timing Diagram

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Rev. G | 18 of 36

Data SheetADXL345

INTERRUPTS
The ADXL345 provides two output pins for driving interrupts: INT1
and INT2. Both interrupt pins are push-pull, low impedance pinswith output specifications shown in Table 13. The default configuration of the interrupt pins is active high. This can be changed toactive low by setting the INT_INVERT bit in the DATA_FORMAT(Address 0x31) register. All functions can be used simultaneously,with the only limiting feature being that some functions may need toshare interrupt pins.
Interrupts are enabled by setting the appropriate bit in the INT_ENABLE register (Address 0x2E) and are mapped to either the INT1
pin or the INT2 pin based on the contents of the INT_MAP register(Address 0x2F). When initially configuring the interrupt pins, it isrecommended that the functions and interrupt mapping be done before enabling the interrupts. When changing the configuration of aninterrupt, it is recommended that the interrupt be disabled first, byclearing the bit corresponding to that function in the INT_ENABLE
register, and then the function be reconfigured before enabling theinterrupt again. Configuration of the functions while the interrupts
are disabled helps to prevent the accidental generation of aninterrupt before desired.
The interrupt functions are latched and cleared by either reading
the data registers (Address 0x32 to Address 0x37) until the interrupt
condition is no longer valid for the data-related interrupts or byreading the INT_SOURCE register (Address 0x30) for the remaining interrupts. This section describes the interrupts that can be set
in the INT_ENABLE register and monitored in the INT_SOURCE
register.

Table 13. Interrupt Pin Digital Output
Limit1
Parameter

Test Conditions

Min

Max

Unit

0.2 × VDD I/O

VDigital Output
Low Level Output Voltage (VOL)IOL = 300 µA

High Level Output Voltage (VOH)

IOH = −150 µA

0.8 × VDD I/OV

Low Level Output Current (IOL)

VOL = VOL, max

300

µA

High Level Output Current (IOH)

VOH = VOH, min

−150

µA

fIN = 1 MHz, VIN = 2.5 V

8pF

Rise Time (tR)2

CLOAD = 150 pF

210

ns

Fall Time (tF)3

CLOAD = 150 pF

150

ns

Pin Capacitance
Rise/Fall Time

1

Limits based on characterization results, not production tested.

2

Rise time is measured as the transition time from VOL, max to VOH, min of the interrupt pin.

3

Fall time is measured as the transition time from VOH, min to VOL, max of the interrupt pin.

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Rev. G | 19 of 36

Data SheetADXL345

INTERRUPTS

The DATA_READY bit is set when new data is available and iscleared when no new data is available.

perienced for more time than is specified in the TIME_INACT
register (Address 0x26) on all participating axes, as set by the
ACT_INACT_CTL register (Address 0x27). The maximum value for
TIME_INACT is 255 sec.

SINGLE_TAP

FREE_FALL

The SINGLE_TAP bit is set when a single acceleration event thatis greater than the value in the THRESH_TAP register (Address
0x1D) occurs for less time than is specified in the DUR register(Address 0x21).

The FREE_FALL bit is set when acceleration of less than the value
stored in the THRESH_FF register (Address 0x28) is experienced
for more time than is specified in the TIME_FF register (Address0x29) on all axes (logical AND). The FREE_FALL interrupt differsfrom the inactivity interrupt as follows: all axes always participate
and are logically AND’ed, the timer period is much smaller (1.28
sec maximum), and the mode of operation is always dc-coupled.

DATA_READYDOUBLE_TAPThe DOUBLE_TAP bit is set when two acceleration events thatare greater than the value in the THRESH_TAP register (Address
0x1D) occur for less time than is specified in the DUR register(Address 0x21), with the second tap starting after the time specified
by the latent register (Address 0x22) but within the time specified in
the window register (Address 0x23). See the Tap Detection section
for more details.
ACTIVITY
The activity bit is set when acceleration greater than the value
stored in the THRESH_ACT register (Address 0x24) is experienced
on any participating axis, set by the ACT_INACT_CTL register(Address 0x27).
INACTIVITY
The inactivity bit is set when acceleration of less than the value stored in the THRESH_INACT register (Address 0x25) is ex-analog.com

WATERMARK
The watermark bit is set when the number of samples in FIFO
equals the value stored in the samples bits (Register FIFO_CTL,
Address 0x38). The watermark bit is cleared automatically when
FIFO is read, and the content returns to a value below the value
stored in the samples bits.
OVERRUNThe overrun bit is set when new data replaces unread data. The
precise operation of the overrun function depends on the FIFO
mode. In bypass mode, the overrun bit is set when new datareplaces unread data in the DATAX, DATAY, and DATAZ registers(Address 0x32 to Address 0x37). In all other modes, the overrun bit
is set when FIFO is filled. The overrun bit is automatically cleared
when the contents of FIFO are read.

Rev. G | 20 of 36

Data SheetADXL345

FIFOThe ADXL345 contains technology for an embedded memory management system with 32-level FIFO that can be used to minimize
host processor burden. This buffer has four modes: bypass, FIFO,
stream, and trigger (see Table 37). Each mode is selected by thesettings of the FIFO_MODE bits (Bits[D7:D6]) in the FIFO_CTL
register (Address 0x38).
BYPASS MODE
In bypass mode, FIFO is not operational and, therefore, remains empty.
FIFO MODE
In FIFO mode, data from measurements of the x-, y-, and z-axes
are stored in FIFO. When the number of samples in FIFO equals
the level specified in the samples bits of the FIFO_CTL register(Address 0x38), the watermark interrupt is set. FIFO continues accumulating samples until it is full (32 samples from measurementsof the x-, y-, and z-axes) and then stops collecting data. After FIFO
stops collecting data, the device continues to operate; therefore,features such as tap detection can be used after FIFO is full. The
watermark interrupt continues to occur until the number of samples
in FIFO is less than the value stored in the samples bits of the
FIFO_CTL register.
STREAM MODE
In stream mode, data from measurements of the x-, y-, and z-axes
are stored in FIFO. When the number of samples in FIFO equals
the level specified in the samples bits of the FIFO_CTL register(Address 0x38), the watermark interrupt is set. FIFO continues
accumulating samples and holds the latest 32 samples from measurements of the x-, y-, and z-axes, discarding older data as new
data arrives. The watermark interrupt continues occurring until thenumber of samples in FIFO is less than the value stored in thesamples bits of the FIFO_CTL register.

RETRIEVING DATA FROM FIFOThe FIFO data is read through the DATAX, DATAY, and DATAZ
registers (Address 0x32 to Address 0x37). When the FIFO is in
FIFO, stream, or trigger mode, reads to the DATAX, DATAY, andDATAZ registers read data stored in the FIFO. Each time data isread from the FIFO, the oldest x-, y-, and z-axes data are placed
into the DATAX, DATAY, and DATAZ registers.
If a single-byte read operation is performed, the remaining bytes ofdata for the current FIFO sample are lost. Therefore, all axes ofinterest should be read in a burst (or multiple-byte) read operation.
To ensure that the FIFO has completely popped (that is, that new
data has completely moved into the DATAX, DATAY, and DATAZ
registers), there must be at least 5 µs between the end of reading
the data registers and the start of a new read of the FIFO or a readof the FIFO_STATUS register (Address 0x39). The end of reading
a data register is signified by the transition from Register 0x37 toRegister 0x38 or by the CS pin going high.
For SPI operation at 1.6 MHz or less, the register addressing
portion of the transmission is a sufficient delay to ensure that the
FIFO has completely popped. For SPI operation greater than 1.6
MHz, it is necessary to deassert the CS pin to ensure a total
delay of 5 µs; otherwise, the delay is not sufficient. The total delaynecessary for 5 MHz operation is at most 3.4 µs. This is not aconcern when using I2C mode because the communication rate is
low enough to ensure a sufficient delay between FIFO reads.

TRIGGER MODE
In trigger mode, FIFO accumulates samples, holding the latest 32
samples from measurements of the x-, y-, and z-axes. After a
trigger event occurs and an interrupt is sent to the INT1 or INT2
pin (determined by the trigger bit in the FIFO_CTL register), FIFO
keeps the last n samples (where n is the value specified by the
samples bits in the FIFO_CTL register) and then operates in FIFO
mode, collecting new samples only when FIFO is not full. A delay ofat least 5 µs should be present between the trigger event occurringand the start of reading data from the FIFO to allow the FIFO to
discard and retain the necessary samples. Additional trigger events
cannot be recognized until the trigger mode is reset. To reset thetrigger mode, set the device to bypass mode and then set thedevice back to trigger mode. Note that the FIFO data should beread first because placing the device into bypass mode clears
FIFO.

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Rev. G | 21 of 36

Data SheetADXL345

SELF-TESTThe ADXL345 incorporates a self-test feature that effectively tests
its mechanical and electronic systems simultaneously. When the
self-test function is enabled (via the SELF_TEST bit in the DATA_FORMAT register, Address 0x31), an electrostatic force is exerted on the mechanical sensor. This electrostatic force moves themechanical sensing element in the same manner as acceleration,and it is additive to the acceleration experienced by the device. Thisadded electrostatic force results in an output change in the x-, y-,and z-axes. Because the electrostatic force is proportional to VS2,
the output change varies with VS. This effect is shown in Figure
43. The scale factors shown in Table 14 can be used to adjust the
expected self-test output limits for different supply voltages, VS. The
self-test feature of the ADXL345 also exhibits a bimodal behavior.
However, the limits shown in Table 1 and Table 15 to Table 18
are valid for both potential self-test values due to bimodality. Useof the self-test feature at data rates less than 100 Hz or at 1600
Hz may yield values outside these limits. Therefore, the part must
be in normal power operation (LOW_POWER bit = 0 in BW_RATE
register, Address 0x2C) and be placed into a data rate of 100 Hz
through 800 Hz or 3200 Hz for the self-test function to operatecorrectly.

Table 14. Self-Test Output Scale Factors for Different Supply Voltages, VS
Supply Voltage, VS (V)X-Axis, Y-Axis

Z-Axis

2.00

0.64

0.8

2.50

1.00

1.00

3.30

1.77

1.47

3.60

2.11

1.69

Table 15. Self-Test Output in LSB for ±2 g, 10-Bit or Full Resolution (TA =25°C, VS = 2.5 V, VDD I/O = 1.8 V)
Axis

Min

Max

Unit

X

50

540

LSB

Y

−540

−50

LSB

Z

75

875

LSB

Table 16. Self-Test Output in LSB for ±4 g, 10-Bit Resolution (TA = 25°C, VS =2.5 V, VDD I/O = 1.8 V)
Axis

Min

Max

Unit

X

25

270

LSB

Y

−270

−25

LSB

Z

38

438

LSB

Table 17. Self-Test Output in LSB for ±8 g, 10-Bit Resolution (TA = 25°C, VS =2.5 V, VDD I/O = 1.8 V)
Axis

Min

Max

Unit

X

12

135

LSB

Y

−135

−12

LSB

Z

19

219

LSB

Table 18. Self-Test Output in LSB for ±16 g, 10-Bit Resolution (TA = 25°C, VS =2.5 V, VDD I/O = 1.8 V)
Figure 43. Self-Test Output Change Limits vs. Supply Voltage

analog.com

Axis

Min

Max

Unit

X

6

67

LSB

Y

−67

−6

LSB

Z

10

110

LSB

Rev. G | 22 of 36

Data SheetADXL345REGISTER MAP
Table 19.
Address
Hex

Dec

Name

Type

Reset Value

Description

0x00

0

DEVID

R

11100101

Device ID

0x01 to 0x1C

1 to 28

Reserved

0x1D

29

THRESH_TAP

R/W

00000000

Tap threshold

0x1E

30

OFSX

R/W

00000000

X-axis offset

0x1F

31

OFSY

R/W

00000000

Y-axis offset

0x20

32

OFSZ

R/W

00000000

Z-axis offset

0x21

33

DUR

R/W

00000000

Tap duration

0x22

34

LatentR/W

00000000

Tap latency

0x23

35

Window

R/W

00000000

Tap window

0x24

36

THRESH_ACT

R/W

00000000

Activity threshold

0x25

37

THRESH_INACT

R/W

00000000

Inactivity threshold

0x26

38

TIME_INACT

R/W

00000000

Inactivity time

0x27

39

ACT_INACT_CTL

R/W

00000000

Axis enable control for activity and inactivity detection

0x28

40

THRESH_FF

R/W

00000000

Free-fall threshold

0x29

41

TIME_FF

R/W

00000000

Free-fall time

0x2A

42

TAP_AXES

R/W

00000000

Axis control for single tap/double tap

0x2B

43

ACT_TAP_STATUS

R

00000000

Source of single tap/double tap

0x2C

44

BW_RATE

R/W

00001010

Data rate and power mode control

0x2D

45

POWER_CTL

R/W

00000000

Power-saving features control

0x2E

46

INT_ENABLE

R/W

00000000Interrupt enable control

0x2F

47

INT_MAP

R/W

00000000Interrupt mapping control

0x30

48

INT_SOURCE

R

00000010

Source of interrupts

0x31

49

DATA_FORMAT

R/W

00000000

Data format control

0x32

50

DATAX0R

00000000

X-Axis Data 0

0x33

51

DATAX1R

00000000

X-Axis Data 1

0x34

52

DATAY0R

00000000

Y-Axis Data 0

0x35

53

DATAY1R

00000000

Y-Axis Data 1

0x36

54

DATAZ0R

00000000

Z-Axis Data 0

0x37

55

DATAZ1R

00000000

Z-Axis Data 1

0x38

56

FIFO_CTL

R/W

00000000

FIFO control

0x39

57

FIFO_STATUS

R

00000000

FIFO statusanalog.com

Reserved; do not accessRev. G | 23 of 36

Data SheetADXL345REGISTER MAP
Register 0x24—THRESH_ACT (Read/Write)

REGISTER DEFINITIONSRegister 0x00—DEVID (Read Only)
Table 20. Register 0x00
D7

D6

D5

D4

D3

D2

D1

D0

1

1

1

0

0

1

0

1

The DEVID register holds a fixed device ID code of 0xE5 (345 octal).
Register 0x1D—THRESH_TAP (Read/Write)
The THRESH_TAP register is eight bits and holds the thresholdvalue for tap interrupts. The data format is unsigned, therefore,
the magnitude of the tap event is compared with the value
in THRESH_TAP for normal tap detection. The scale factor is62.5 mg/LSB (that is, 0xFF = 16 g). A value of 0 may result inundesirable behavior if single tap/double tap interrupts are enabled.
Register 0x1E, Register 0x1F, Register 0x20—
OFSX, OFSY, OFSZ (Read/Write)
The OFSX, OFSY, and OFSZ registers are each eight bits and offeruser-set offset adjustments in twos complement format with a scale
factor of 15.6 mg/LSB (that is, 0x7F = 2 g). The value stored in
the offset registers is automatically added to the acceleration data,
and the resulting value is stored in the output data registers. For
additional information regarding offset calibration and the use of theoffset registers, refer to the Offset Calibration section.
Register 0x21—DUR (Read/Write)

The THRESH_ACT register is eight bits and holds the thresholdvalue for detecting activity. The data format is unsigned, so themagnitude of the activity event is compared with the value in the
THRESH_ACT register. The scale factor is 62.5 mg/LSB. A valueof 0 may result in undesirable behavior if the activity interrupt isenabled.
Register 0x25—THRESH_INACT (Read/Write)
The THRESH_INACT register is eight bits and holds the thresholdvalue for detecting inactivity. The data format is unsigned, so themagnitude of the inactivity event is compared with the value in the
THRESH_INACT register. The scale factor is 62.5 mg/LSB. A valueof 0 may result in undesirable behavior if the inactivity interrupt isenabled.
Register 0x26—TIME_INACT (Read/Write)
The TIME_INACT register is eight bits and contains an unsigned
time value representing the amount of time that acceleration mustbe less than the value in the THRESH_INACT register for inactivity
to be declared. The scale factor is 1 sec/LSB. Unlike the otherinterrupt functions, which use unfiltered data (see the Thresholdsection), the inactivity function uses filtered output data. At least
one output sample must be generated for the inactivity interrupt tobe triggered. This results in the function appearing unresponsive
if the TIME_INACT register is set to a value less than the time
constant of the output data rate. A value of 0 results in an interrupt
when the output data is less than the value in the THRESH_INACT
register.

The DUR register is eight bits and contains an unsigned time value
representing the maximum time that an event must be above the
THRESH_TAP threshold to qualify as a tap event. The scale factor
is 625 µs/LSB. A value of 0 disables the single tap/ double tap
functions.

Register 0x27—ACT_INACT_CTL (Read/Write)

Register 0x22—Latent (Read/Write)

Table 22. Register 0x27—Bits[D3:D0]

The latent register is eight bits and contains an unsigned time value
representing the wait time from the detection of a tap event to thestart of the time window (defined by the window register) during
which a possible second tap event can be detected. The scale
factor is 1.25 ms/LSB. A value of 0 disables the double tap function.
Register 0x23—Window (Read/Write)
The window register is eight bits and contains an unsigned timevalue representing the amount of time after the expiration of thelatency time (determined by the latent register) during which a
second valid tap can begin. The scale factor is 1.25 ms/LSB. A
value of 0 disables the double tap function.

analog.com

Table 21. Register 0x27—Bits[D7:D4]
D7

D6

D5

D4

ACT ac/dc

ACT_X enable

ACT_Y enable

ACT_Z enable

D3

D2

D1

D0

INACT ac/dc

INACT_X enable

INACT_Y enable

INACT_Z enable

ACT AC/DC and INACT AC/DC Bits
A setting of 0 selects dc-coupled operation, and a setting of 1
enables ac-coupled operation. In dc-coupled operation, the current
acceleration magnitude is compared directly with THRESH_ACT
and THRESH_INACT to determine whether activity or inactivity isdetected.
In ac-coupled operation for activity detection, the acceleration value
at the start of activity detection is taken as a reference value. New
samples of acceleration are then compared to this reference value,

Rev. G | 24 of 36

Data SheetADXL345REGISTER MAP
and if the magnitude of the difference exceeds the THRESH_ACT
value, the device triggers an activity interrupt.
Similarly, in ac-coupled operation for inactivity detection, a reference value is used for comparison and is updated whenever
the device exceeds the inactivity threshold. After the reference
value is selected, the device compares the magnitude of the difference between the reference value and the current acceleration
with THRESH_INACT. If the difference is less than the value in
THRESH_INACT for the time in TIME_INACT, the device is considered inactive and the inactivity interrupt is triggered.
ACT_x Enable Bits and INACT_x Enable Bits
A setting of 1 enables x-, y-, or z-axis participation in detecting
activity or inactivity. A setting of 0 excludes the selected axis fromparticipation. If all axes are excluded, the function is disabled. For
activity detection, all participating axes are logically OR’ed, causing
the activity function to trigger when any of the participating axes
exceeds the threshold. For inactivity detection, all participating axes
are logically AND’ed, causing the inactivity function to trigger only if
all participating axes are below the threshold for the specified time.
Register 0x28—THRESH_FF (Read/Write)
The THRESH_FF register is eight bits and holds the thresholdvalue, in unsigned format, for free-fall detection. The accelerationon all axes is compared with the value in THRESH_FF to determine
if a free-fall event occurred. The scale factor is 62.5 mg/LSB. Notethat a value of 0 mg may result in undesirable behavior if thefree-fall interrupt is enabled. Values between 300 mg and 600 mg(0x05 to 0x09) are recommended.

A setting of 1 in the TAP_X enable, TAP_Y enable, or TAP_Z
enable bit enables x-, y-, or z-axis participation in tap detection.
A setting of 0 excludes the selected axis from participation in tap
detection.
Register 0x2B—ACT_TAP_STATUS (Read Only)
Table 24. Register 0x2B
D7

D6

D5

D4

D3

D2

D1

D0

0

ACT_X
sourceACT_YsourceACT_ZsourceAsleepTAP_XsourceTAP_YsourceTAP_ZsourceACT_x Source and TAP_x Source Bits
These bits indicate the first axis involved in a tap or activity event.
A setting of 1 corresponds to involvement in the event, and a
setting of 0 corresponds to no involvement. When new data isavailable, these bits are not cleared but are overwritten by the
new data. The ACT_TAP_STATUS register should be read before
clearing the interrupt. Disabling an axis from participation clears thecorresponding source bit when the next activity or single tap/double
tap event occurs.
Asleep Bit
A setting of 1 in the asleep bit indicates that the part is asleep,
and a setting of 0 indicates that the part is not asleep. This bit
toggles only if the device is configured for auto sleep. See the
AUTO_SLEEP Bit section for more information on autosleep mode.
Register 0x2C—BW_RATE (Read/Write)

Register 0x29—TIME_FF (Read/Write)

Table 25. Register 0x2C

The TIME_FF register is eight bits and stores an unsigned timevalue representing the minimum time that the value of all axes
must be less than THRESH_FF to generate a free-fall interrupt. The
scale factor is 5 ms/LSB. A value of 0 may result in undesirable
behavior if the free-fall interrupt is enabled. Values between 100 ms
and 350 ms (0x14 to 0x46) are recommended.
Register 0x2A—TAP_AXES (Read/Write)
Table 23.
D7

D6

D5

D4

D3

D2

D1

D0

0

0

0

0

Suppress

TAP_X
enableTAP_YenableTAP_ZenableSuppress Bit
Setting the suppress bit suppresses double tap detection if acceleration greater than the value in THRESH_TAP is present between
taps. See the Tap Detection section for more details.

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TAP_x Enable Bits

D7

D6

D5

D4

0

0

0

LOW_POWER

D3

D2

D1

D0

Rate

LOW_POWER Bit
A setting of 0 in the LOW_POWER bit selects normal operation,
and a setting of 1 selects reduced power operation, which has
somewhat higher noise (see the Power Modes section for details).
Rate Bits
These bits select the device bandwidth and output data rate (seeTable 7 and Table 8 for details). The default value is 0x0A, whichtranslates to a 100 Hz output data rate. An output data rate should
be selected that is appropriate for the communication protocol andfrequency selected. Selecting too high of an output data rate with alow communication speed results in samples being discarded.

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Data SheetADXL345REGISTER MAP
Sleep Bit

Register 0x2D—POWER_CTL (Read/Write)
Table 26. Register 0x2D
D7

D6

D5

D4

D3

D2

D1

D0

0

0

Link

AUTO_SLEEP

MeasureSleep

Wakeup

Link Bit
A setting of 1 in the link bit with both the activity and inactivity functions enabled delays the start of the activity function until inactivity
is detected. After activity is detected, inactivity detection begins,preventing the detection of activity. This bit serially links the activity
and inactivity functions. When this bit is set to 0, the inactivity
and activity functions are concurrent. Additional information can befound in the Link Mode section.
When clearing the link bit, it is recommended that the part beplaced into standby mode and then set back to measurement modewith a subsequent write. This is done to ensure that the device
is properly biased if sleep mode is manually disabled; otherwise,
the first few samples of data after the link bit is cleared may haveadditional noise, especially if the device was asleep when the bit
was cleared.
AUTO_SLEEP Bit
If the link bit is set, a setting of 1 in the AUTO_SLEEP bit enables
the auto-sleep functionality. In this mode, the ADXL345 auto-matically switches to sleep mode if the inactivity function is enabled
and inactivity is detected (that is, when acceleration is below the
THRESH_INACT value for at least the time indicated by TIME_INACT). If activity is also enabled, the ADXL345 automatically wakes
up from sleep after detecting activity and returns to operation at theoutput data rate set in the BW_RATE register. A setting of 0 in the
AUTO_SLEEP bit disables automatic switching to sleep mode. See
the Sleep Bit section for more information on sleep mode.
If the link bit is not set, the AUTO_SLEEP feature is disabled andsetting the AUTO_SLEEP bit does not have an impact on device
operation. Refer to the Link Bit section or the Link Mode section for
more information on utilization of the link feature.
When clearing the AUTO_SLEEP bit, it is recommended that thepart be placed into standby mode and then set back to measurement mode with a subsequent write. This is done to ensure thatthe device is properly biased if sleep mode is manually disabled;
otherwise, the first few samples of data after the AUTO_SLEEP bit
is cleared may have additional noise, especially if the device wasasleep when the bit was cleared.
Measure Bit
A setting of 0 in the measure bit places the part into standby
mode, and a setting of 1 places the part into measurement mode.
The ADXL345 powers up in standby mode with minimum power
consumption.
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A setting of 0 in the sleep bit puts the part into the normal modeof operation, and a setting of 1 places the part into sleep mode.
Sleep mode suppresses DATA_READY, stops transmission of data
to FIFO, and switches the sampling rate to one specified by the
wakeup bits. In sleep mode, only the activity function can be used.
When the DATA_READY interrupt is suppressed, the output dataregisters (Register 0x32 to Register 0x37) are still updated at the
sampling rate set by the wakeup bits (D1:D0).
When clearing the sleep bit, it is recommended that the part beplaced into standby mode and then set back to measurement modewith a subsequent write. This is done to ensure that the device isproperly biased if sleep mode is manually disabled; otherwise, thefirst few samples of data after the sleep bit is cleared may haveadditional noise, especially if the device was asleep when the bit
was cleared.
Wakeup Bits
These bits control the frequency of readings in sleep mode as
described in Table 27.
Table 27. Frequency of Readings in Sleep Mode
Setting
D1

D0

Frequency (Hz)

0

0

8

0

1

4

1

0

2

1

1

1

Register 0x2E—INT_ENABLE (Read/Write)
Table 28. Register 0x2E—Bits[D7:D0]
D7

D6

D5

D4

DATA_READYSINGLE_TAP

DOUBLE_TAP

Activity

Table 29. Register 0x2E—Bits[D3:D0]
D3

D2

D1

D0

Inactivity

FREE_FALL

Watermark

OverrunSetting bits in this register to a value of 1 enables their respectivefunctions to generate interrupts, whereas a value of 0 preventsthe functions from generating interrupts. The DATA_READY, watermark, and overrun bits enable only the interrupt output; thefunctions are always enabled. It is recommended that interrupts beconfigured before enabling their outputs.
Register 0x2F—INT_MAP (R/W)
Table 30. Register 0x2F—Bits[D7:D4]
D7

D6

D5

D4

DATA_READYSINGLE_TAP

DOUBLE_TAP

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Data SheetADXL345REGISTER MAP
FULL_RES Bit

Table 31. Register 0x2F—Bits[D3:D0]
D3

D2

D1

D0

Inactivity

FREE_FALL

Watermark

OverrunAny bits set to 0 in this register send their respective interrupts to
the INT1 pin, whereas bits set to 1 send their respective interrupts
to the INT2 pin. All selected interrupts for a given pin are OR’ed.

When this bit is set to a value of 1, the device is in full resolutionmode, where the output resolution increases with the g range set
by the range bits to maintain a 4 mg/LSB scale factor. When the
FULL_RES bit is set to 0, the device is in 10-bit mode, and therange bits determine the maximum g range and scale factor.
Justify Bit

Register 0x30—INT_SOURCE (Read Only)

A setting of 1 in the justify bit selects left-justified (MSB) mode, anda setting of 0 selects right-justified mode with sign extension.

Table 32. Register 0x30—Bits[D7:D4]
D7

D6

D5

D4

DATA_READYSINGLE_TAP

DOUBLE_TAP

Activity

Range Bits
These bits set the g range as described in Table 35.

Table 33. Register 0x30—Bits[D3:D0]
D3

D2

D1

D0

Inactivity

FREE_FALL

Watermark

OverrunTable 35. g Range Setting
Setting

Bits set to 1 in this register indicate that their respective functions
have triggered an event, whereas a value of 0 indicates thatthe corresponding event has not occurred. The DATA_READY,
watermark, and overrun bits are always set if the corresponding
events occur, regardless of the INT_ENABLE register settings, andare cleared by reading data from the DATAX, DATAY, and DATAZ
registers. The DATA_READY and watermark bits may require multiple reads, as indicated in the FIFO mode descriptions in the FIFO
section. Other bits, and the corresponding interrupts, are cleared byreading the INT_SOURCE register.
Register 0x31—DATA_FORMAT (Read/Write)
Table 34. Register 0x31
D7

D6

D5

D4

D3

D2

SELF_TESTSPIINT_INVERT0

FULL_RES Justify

D1

D0
Range

The DATA_FORMAT register controls the presentation of data to
Register 0x32 through Register 0x37. All data, except that for the±16 g range, must be clipped to avoid rollover.
SELF_TEST Bit
A setting of 1 in the SELF_TEST bit applies a self-test force to thesensor, causing a shift in the output data. A value of 0 disables theself-test force.
SPI BitD1

D0

g Range

0

0

±2 g

0

1

±4 g

1

0

±8 g

1

1

±16 g

Register 0x32 to Register 0x37—DATAX0,DATAX1, DATAY0, DATAY1, DATAZ0, DATAZ1(Read Only)
These six bytes (Register 0x32 to Register 0x37) are eight bits
each and hold the output data for each axis. Register 0x32 andRegister 0x33 hold the output data for the x-axis, Register 0x34 andRegister 0x35 hold the output data for the y-axis, and Register 0x36
and Register 0x37 hold the output data for the z-axis. The output
data is twos complement, with DATAx0 as the least significant byte
and DATAx1 as the most significant byte, where x represent X,
Y, or Z. The DATA_FORMAT register (Address 0x31) controls theformat of the data. It is recommended that a multiple-byte read of all
registers be performed to prevent a change in data between readsof sequential registers.
Register 0x38—FIFO_CTL (Read/Write)
Table 36. Register 0x38
D7

D6

FIFO_MODE

D5
Trigger

D4

D3

D2

D1

D0

SamplesA value of 1 in the SPI bit sets the device to 3-wire SPI mode, and avalue of 0 sets the device to 4-wire SPI mode.
INT_INVERT Bit
A value of 0 in the INT_INVERT bit sets the interrupts to active
high, and a value of 1 sets the interrupts to active low.

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Rev. G | 27 of 36

Data SheetADXL345REGISTER MAP
FIFO_MODE Bits

Entries Bits

These bits set the FIFO mode, as described in Table 37.

These bits report how many data values are stored in FIFO. Accessto collect the data from FIFO is provided through the DATAX,DATAY, and DATAZ registers. FIFO reads must be done in burst or
multiple-byte mode because each FIFO level is cleared after any
read (single- or multiple-byte) of FIFO. FIFO stores a maximum of
32 entries, which equates to a maximum of 33 entries available atany given time because an additional entry is available at the output
filter of the device.

Table 37. FIFO Modes
Setting
D7

D6

Mode

Function00

BypassFIFO is bypassed.

0

1

FIFO

FIFO collects up to 32 values and then stops collecting data, collecting new data only when FIFO is not
full.

1

0

StreamFIFO holds the last 32 data values. When FIFO is full,
the oldest data is overwritten with newer data.

1

1

Trigger

When triggered by the trigger bit, FIFO holds the last
data samples before the trigger event and then continues to collect data until full. New data is collected only
when FIFO is not full.

Trigger Bit
A value of 0 in the trigger bit links the trigger event of trigger mode
to INT1, and a value of 1 links the trigger event to INT2.
Samples Bits
The function of these bits depends on the FIFO mode selected (seeTable 38). Entering a value of 0 in the samples bits immediately
sets the watermark status bit in the INT_SOURCE register, regardless of which FIFO mode is selected. Undesirable operation may
occur if a value of 0 is used for the samples bits when trigger modeis used.
Table 38. Samples Bits Functions
FIFO Mode

Samples Bits Function

Bypass

None.

FIFO

Specifies how many FIFO entries are needed to trigger awatermark interrupt.

StreamSpecifies how many FIFO entries are needed to trigger awatermark interrupt.

Trigger

Specifies how many FIFO samples are retained in the FIFO
buffer before a trigger event.

Register 0x39—FIFO_STATUS (Read Only)
Table 39. Register 0x39
D7

D6

FIFO_TRIG

0

D5

D4

D3

D2

D1

D0

Entries

FIFO_TRIG Bit
A 1 in the FIFO_TRIG bit corresponds to a trigger event occurring,
and a 0 means that a FIFO trigger event has not occurred.

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Rev. G | 28 of 36

Data SheetADXL345APPLICATIONS INFORMATIONPOWER SUPPLY DECOUPLING
A 1 µF tantalum capacitor (CS) at VS and a 0.1 µF ceramic
capacitor (CI/O) at VDD I/O placed close to the ADXL345 supply pinsis recommended to adequately decouple the accelerometer fromnoise on the power supply. If additional decoupling is necessary,a resistor or ferrite bead, no larger than 100 Ω, in series with VS
may be helpful. Additionally, increasing the bypass capacitance on
VS to a 10 µF tantalum capacitor in parallel with a 0.1 µF ceramic
capacitor may also improve noise.
Care should be taken to ensure that the connection from the
ADXL345 ground to the power supply ground has low impedance
because noise transmitted through ground has an effect similar tonoise transmitted through VS. It is recommended that VS and VDD
I/O be separate supplies to minimize digital clocking noise on the VS
supply. If this is not possible, additional filtering of the supplies, as
previously mentioned, may be necessary.

Figure 44. Application Diagram

MECHANICAL CONSIDERATIONS FOR
MOUNTING
The ADXL345 should be mounted on the PCB in a location close
to a hard mounting point of the PCB to the case. Mounting the
ADXL345 at an unsupported PCB location, as shown in Figure 45,
may result in large, apparent measurement errors due to undampened PCB vibration. Locating the accelerometer near a hard mounting point ensures that any PCB vibration at the accelerometer isabove the accelerometer’s mechanical sensor resonant frequency
and, therefore, effectively invisible to the accelerometer. Multiple
mounting points, close to the sensor, and/or a thicker PCB also help
to reduce the effect of system resonance on the performance of thesensor.

Figure 45. Incorrectly Placed Accelerometers

TAP DETECTION
The tap interrupt function is capable of detecting either single or
double taps. The following parameters are shown in Figure 46 for avalid single and valid double tap event:analog.com► The tap detection threshold is defined by the THRESH_TAP

register (Address 0x1D).

► The maximum tap duration time is defined by the DUR register(Address 0x21).

► The tap latency time is defined by the latent register (Address0x22) and is the waiting period from the end of the first tap until
the start of the time window, when a second tap can be detected,
which is determined by the value in the window register (Address
0x23).
► The interval after the latency time (set by the latent register)is defined by the window register. Although a second tap must
begin after the latency time has expired, it need not finish before
the end of the time defined by the window register.

Figure 46. Tap Interrupt Function with Valid Single and Double Taps

If only the single tap function is in use, the single tap interrupt is
triggered when the acceleration goes below the threshold, as longas DUR has not been exceeded. If both single and double tap
functions are in use, the single tap interrupt is triggered when the
double tap event has been either validated or invalidated.
Several events can occur to invalidate the second tap of a double
tap event. First, if the suppress bit in the TAP_AXES register(Address 0x2A) is set, any acceleration spike above the threshold
during the latency time (set by the latent register) invalidates the
double tap detection, as shown in Figure 47.

Figure 47. Double Tap Event Invalid Due to High g Event When the Suppress
Bit Is Set

A double tap event can also be invalidated if acceleration above thethreshold is detected at the start of the time window for the secondtap (set by the window register). This results in an invalid double
tap at the start of this window, as shown in Figure 48. Additionally, a
double tap event can be invalidated if an acceleration exceeds thetime limit for taps (set by the DUR register), resulting in an invalid
Rev. G | 29 of 36

Data SheetADXL345APPLICATIONS INFORMATION
double tap at the end of the DUR time limit for the second tap
event, also shown in Figure 48.

accelerometer is examined. This may result in functions triggering
when acceleration data does not appear to meet the conditions set
by the user for the corresponding function.
LINK MODE
The function of the link bit is to reduce the number of activity
interrupts that the processor must service by setting the device tolook for activity only after inactivity. For proper operation of thisfeature, the processor must still respond to the activity and inactivity
interrupts by reading the INT_SOURCE register (Address 0x30)
and, therefore, clearing the interrupts. If an activity interrupt is notcleared, the part cannot go into autosleep mode. The asleep bit in
the ACT_TAP_STATUS register (Address 0x2B) indicates if the partis asleep.
SLEEP MODE VS. LOW POWER MODE

Figure 48. Tap Interrupt Function with Invalid Double Taps

Single taps, double taps, or both can be detected by setting
the respective bits in the INT_ENABLE register (Address 0x2E).
Control over participation of each of the three axes in single tap/
double tap detection is exerted by setting the appropriate bits in
the TAP_AXES register (Address 0x2A). For the double tap function
to operate, both the latent and window registers must be set to anonzero value.
Every mechanical system has somewhat different single tap/ double
tap responses based on the mechanical characteristics of thesystem. Therefore, some experimentation with values for the DUR,
latent, window, and THRESH_TAP registers is required. In general,a good starting point is to set the DUR register to a value greaterthan 0x10 (10 ms), the latent register to a value greater than
0x10 (20 ms), the window register to a value greater than 0x40
(80 ms), and the THRESH_TAP register to a value greater than
0x30 (3 g). Setting a very low value in the latent, window, or
THRESH_TAP register may result in an unpredictable response
due to the accelerometer picking up echoes of the tap inputs.
After a tap interrupt has been received, the first axis to exceed the
THRESH_TAP level is reported in the ACT_TAP_STATUS register(Address 0x2B). This register is never cleared but is overwrittenwith new data.
THRESHOLD
The lower output data rates are achieved by decimating a common
sampling frequency inside the device. The activity, free-fall, and single tap/double tap detection functions without improved tap enabled
are performed using undecimated data. Because the bandwidthof the output data varies with the data rate and is lower thanthe bandwidth of the undecimated data, the high frequency andhigh g data that is used to determine activity, free-fall, and single
tap/double tap events may not be present if the output of theanalog.com

In applications where a low data rate and low power consumption isdesired (at the expense of noise performance), it is recommended
that low power mode be used. The use of low power mode preserves the functionality of the DATA_READY interrupt and the FIFO
for postprocessing of the acceleration data. Sleep mode, while
offering a low data rate and power consumption, is not intended fordata acquisition.
However, when sleep mode is used in conjunction with the AUTO_SLEEP mode and the link mode, the part can automaticallyswitch to a low power, low sampling rate mode when inactivity
is detected. To prevent the generation of redundant inactivity interrupts, the inactivity interrupt is automatically disabled and activity isenabled. When the ADXL345 is in sleep mode, the host processor
can also be placed into sleep mode or low power mode to savesignificant system power. When activity is detected, the accelerometer automatically switches back to the original data rate of theapplication and provides an activity interrupt that can be used towake up the host processor. Similar to when inactivity occurs,
detection of activity events is disabled and inactivity is enabled.
OFFSET CALIBRATION
Accelerometers are mechanical structures containing elements thatare free to move. These moving parts can be very sensitive tomechanical stresses, much more so than solid-state electronics.
The 0 g bias or offset is an important accelerometer metric because it defines the baseline for measuring acceleration. Additional
stresses can be applied during assembly of a system containing
an accelerometer. These stresses can come from, but are notlimited to, component soldering, board stress during mounting, andapplication of any compounds on or over the component. If calibration is deemed necessary, it is recommended that calibration be
performed after system assembly to compensate for these effects.
A simple method of calibration is to measure the offset whileassuming that the sensitivity of the ADXL345 is as specified inTable 1. The offset can then be automatically accounted for by

Rev. G | 30 of 36

Data SheetADXL345APPLICATIONS INFORMATION
using the built-in offset registers. This results in the data acquired
from the DATA registers already compensating for any offset.
In a no-turn or single-point calibration scheme, the part is oriented
such that one axis, typically the z-axis, is in the 1 g field of gravity
and the remaining axes, typically the x- and y-axis, are in a 0
g field. The output is then measured by taking the average of aseries of samples. The number of samples averaged is a choice ofthe system designer, but a recommended starting point is 0.1 sec
worth of data for data rates of 100 Hz or greater. This corresponds
to 10 samples at the 100 Hz data rate. For data rates less than
100 Hz, it is recommended that at least 10 samples be averaged
together. These values are stored as X0g, Y0g, and Z+1g for the 0 g
measurements on the x- and y-axis and the 1 g measurement on
the z-axis, respectively.
The values measured for X0g and Y0g correspond to the x- andy-axis offset, and compensation is done by subtracting those values
from the output of the accelerometer to obtain the actual acceleration:
XACTUAL = XMEAS − X0g
YACTUAL = YMEAS − Y0g
Because the z-axis measurement was done in a +1 g field, a noturn or single-point calibration scheme assumes an ideal sensitivity,
SZ for the z-axis. This is subtracted from Z+1g to attain the z-axis
offset, which is then subtracted from future measured values toobtain the actual value:Z0g = Z+1g − SZZACTUAL = ZMEAS − Z0g
The ADXL345 can automatically compensate the output for offset
by using the offset registers (Register 0x1E, Register 0x1F, andRegister 0x20). These registers contain an 8-bit, twos complement
value that is automatically added to all measured acceleration values, and the result is then placed into the DATA registers. Because
the value placed in an offset register is additive, a negative value isplaced into the register to eliminate a positive offset and vice versa
for a negative offset. The register has a scale factor of 15.6 mg/LSB
and is independent of the selected g-range.
As an example, assume that the ADXL345 is placed into full-resolution mode with a sensitivity of typically 256 LSB/g. The part isoriented such that the z-axis is in the field of gravity and x-, y-, andz-axis outputs are measured as +10 LSB, −13 LSB, and +9 LSB,
respectively. Using the previous equations, X0g is +10 LSB, Y0g is−13 LSB, and Z0g is +9 LSB. Each LSB of output in full-resolution is
3.9 mg or one-quarter of an LSB of the offset register. Because theoffset register is additive, the 0 g values are negated and rounded
to the nearest LSB of the offset register:XOFFSET = −Round(10/4) = −3 LSB
YOFFSET = −Round(−13/4) = 3 LSBZOFFSET = −Round(9/4) = −2 LSB
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These values are programmed into the OFSX, OFSY, and OFXZ
registers, respectively, as 0xFD, 0x03 and 0xFE. As with all registers in the ADXL345, the offset registers do not retain the value
written into them when power is removed from the part. Power-cycling the ADXL345 returns the offset registers to their default valueof 0x00.
Because the no-turn or single-point calibration method assumes anideal sensitivity in the z-axis, any error in the sensitivity results inoffset error. For instance, if the actual sensitivity was 250 LSB/g inthe previous example, the offset would be 15 LSB, not 9 LSB. To
help minimize this error, an additional measurement point can beused with the z-axis in a 0 g field and the 0 g measurement can beused in the ZACTUAL equation.
USING SELF-TEST
The self-test change is defined as the difference between the acceleration output of an axis with self-test enabled and the acceleration
output of the same axis with self-test disabled (see Endnote 6 ofTable 1). This definition assumes that the sensor does not move
between these two measurements, because if the sensor moves, anon–self-test related shift corrupts the test.
Proper configuration of the ADXL345 is also necessary for an
accurate self-test measurement. The part should be set with adata rate of 100 Hz through 800 Hz, or 3200 Hz. This is doneby ensuring that a value of 0x0A through 0x0D, or 0x0F is written
into the rate bits (Bit D3 through Bit D0) in the BW_RATE register(Address 0x2C). The part also must be placed into normal power
operation by ensuring the LOW_POWER bit in the BW_RATE
register is cleared (LOW_POWER bit = 0) for accurate self-test
measurements. It is recommended that the part be set to full-resolution, 16 g mode to ensure that there is sufficient dynamic range
for the entire self-test shift. This is done by setting Bit D3 of the
DATA_FORMAT register (Address 0x31) and writing a value of
0x03 to the range bits (Bit D1 and Bit D0) of the DATA_FORMAT
register (Address 0x31). This results in a high dynamic range formeasurement and a 3.9 mg/LSB scale factor.
After the part is configured for accurate self-test measurement,
several samples of x-, y-, and z-axis acceleration data should
be retrieved from the sensor and averaged together. The numberof samples averaged is a choice of the system designer, but arecommended starting point is 0.1 sec worth of data for data ratesof 100 Hz or greater. This corresponds to 10 samples at the 100 Hz
data rate. For data rates less than 100 Hz, it is recommended thatat least 10 samples be averaged together. The averaged values
should be stored and labeled appropriately as the self-test disableddata, that is, XST_OFF, YST_OFF, and ZST_OFF.
Next, self-test should be enabled by setting Bit D7 (SELF_TEST)of the DATA_FORMAT register (Address 0x31). The output needssome time (about four samples) to settle after enabling self-test.
After allowing the output to settle, several samples of the x-, y-, andz-axis acceleration data should be taken again and averaged. It is
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Data SheetADXL345APPLICATIONS INFORMATION
average as was previously taken. These averaged values should
again be stored and labeled appropriately as the value with self-test
enabled, that is, XST_ON, YST_ON, and ZST_ON. Self-test can then bedisabled by clearing Bit D7 (SELF_TEST) of the DATA_FORMAT
register (Address 0x31).

ing tone at the frequency the self-test was toggled. Using an FFTlike this removes the dependency of the test on supply voltage andon self-test magnitude, which can vary within a rather wide range.

With the stored values for self-test enabled and disabled, theself-test change is as follows:

Asynchronous readings of acceleration data can lead to accessing the acceleration data registers while they are being updated.
To avoid this, it is recommended to either enable stream mode(see Table 37) or to synchronize the SPI/I2C transaction to the
DATA_READY interrupt functionality, so that the host processor
samples immediately after the DATA_READY interrupt goes high.

XST = XST_ON − XST_OFF
YST = YST_ON − YST_OFF
ZST = ZST_ON − ZST_OFF
Because the measured output for each axis is expressed in LSBs,
XST, YST, and ZST are also expressed in LSBs. These values canbe converted to g’s of acceleration by multiplying each value by
the 3.9 mg/LSB scale factor, if configured for full-resolution mode.
Additionally, Table 15 through Table 18 correspond to the self-test
range converted to LSBs and can be compared with the measured
self-test change when operating at a VS of 2.5 V. For other voltages, the minimum and maximum self-test output values should be
adjusted based on (multiplied by) the scale factors shown in Table
14. If the part was placed into ±2 g, 10-bit or full-resolution mode,the values listed in Table 15 should be used. Although the fixed
10-bit mode or a range other than 16 g can be used, a different
set of values, as indicated in Table 16 through Table 18, would
need to be used. Using a range below 8 g may result in insufficient
dynamic range and should be considered when selecting the range
of operation for measuring self-test.
If the self-test change is within the valid range, the test is considered successful. Generally, a part is considered to pass if theminimum magnitude of change is achieved. However, a part thatchanges by more than the maximum magnitude is not necessarily a
failure.
Another effective method for using the self-test to verify accelerometer functionality is to toggle the self test at a certain rate and thenperform an FFT on the output. The FFT should have a correspond-

ASYNCHRONOUS DATA READINGSDATA FORMATTING OF UPPER DATA RATESFormatting of output data at the 3200 Hz and 1600 Hz output data
rates changes depending on the mode of operation (full-resolution
or fixed 10-bit) and the selected output range.
When using the 3200 Hz or 1600 Hz output data rates in full-resolution or ±2 g, 10-bit operation, the LSB of the output data-wordis always 0. When data is right justified, this corresponds to Bit
D0 of the DATAx0 register, as shown in Figure 49. When data isleft justified and the part is operating in ±2 g, 10-bit mode, theLSB of the output data-word is Bit D6 of the DATAx0 register. In
full-resolution operation when data is left justified, the location of the
LSB changes according to the selected output range.
For a range of ±2 g, the LSB is Bit D6 of the DATAx0 register; for±4 g, Bit D5 of the DATAx0 register; for ±8 g, Bit D4 of the DATAx0
register; and for ±16 g, Bit D3 of the DATAx0 register. This is shownin Figure 50.
The use of 3200 Hz and 1600 Hz output data rates for fixed 10‑bit
operation in the ±4 g, ±8 g, and ±16 g output ranges provides
an LSB that is valid and that changes according to the applied
acceleration. Therefore, in these modes of operation, Bit D0 is notalways 0 when output data is right justified and Bit D6 is not always
0 when output data is left justified. Operation at any data rate of 800
Hz or lower also provides a valid LSB in all ranges and modes thatchanges according to the applied acceleration.

Figure 49. Data Formatting of Full-Resolution and ±2 g, 10-Bit Modes of Operation When Output Data Is Right Justified

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Data SheetADXL345APPLICATIONS INFORMATION

Figure 50. Data Formatting of Full-Resolution and ±2 g, 10-Bit Modes of Operation When Output Data Is Left Justified

NOISE PERFORMANCEThe specification of noise shown in Table 1 corresponds to the typical noise performance of the ADXL345 in normal power operation
with an output data rate of 100 Hz (LOW_POWER bit (D4) = 0, rate
bits (D3:D0) = 0xA in the BW_RATE register, Address 0x2C). For
normal power operation at data rates below 100 Hz, the noise of
the ADXL345 is equivalent to the noise at 100 Hz ODR in LSBs.
For data rates greater than 100 Hz, the noise increases roughly bya factor of √2 per doubling of the data rate. For example, at 400 Hz
ODR, the noise on the x- and y-axes is typically less than 1.5 LSB
rms, and the noise on the z-axis is typically less than 2.2 LSB rms.
For low power operation (LOW_POWER bit (D4) = 1 in the
BW_RATE register, Address 0x2C), the noise of the ADXL345 isconstant for all valid data rates shown in Table 8. This value istypically less than 1.8 LSB rms for the x- and y-axes and typicallyless than 2.6 LSB rms for the z-axis.

Figure 51. Noise vs. Output Data Rate for Normal and Low Power Modes,
Full-Resolution (256 LSB/g)

The trend of noise performance for both normal power and low
power modes of operation of the ADXL345 is shown in Figure 51.
Figure 52 shows the typical Allan deviation for the ADXL345. The
1/f corner of the device, as shown in this figure, is very low, allowing
absolute resolution of approximately 100 µg (assuming that there
is sufficient integration time). Figure 52 also shows that the noise
density is 290 µg/√Hz for the x-axis and y-axis and 430 µg/√Hz forthe z-axis.
Figure 53 shows the typical noise performance trend of the
ADXL345 over supply voltage. The performance is normalized tothe tested and specified supply voltage, VS = 2.5 V. In general,
noise decreases as supply voltage is increased. It should be noted,
as shown in Figure 51, that the noise on the z-axis is typicallyhigher than on the x-axis and y-axis; therefore, while they changeroughly the same in percentage over supply voltage, the magnitudeof change on the z-axis is greater than the magnitude of change on
the x-axis and y-axis.

Figure 52. Root Allan Deviation

Figure 53. Normalized Noise vs. Supply Voltage, VSanalog.com

Rev. G | 33 of 36

Data SheetADXL345APPLICATIONS INFORMATIONOPERATION AT VOLTAGES OTHER THAN 2.5 V
The ADXL345 is tested and specified at a supply voltage of
VS = 2.5 V; however, it can be powered with VS as high as 3.6
V or as low as 2.0 V. Some performance parameters change as
the supply voltage changes: offset, sensitivity, noise, self-test, andsupply current.
Due to slight changes in the electrostatic forces as supply voltage isvaried, the offset and sensitivity change slightly. When operating at
a supply voltage of VS = 3.3 V, the x- and y-axis offset is typically
25 mg higher than at Vs = 2.5 V operation. The z-axis is typically
20 mg lower when operating at a supply voltage of 3.3 V than when
operating at VS = 2.5 V. Sensitivity on the x- and y-axes typicallyshifts from a nominal 256 LSB/g (full-resolution or ±2 g, 10-bit
operation) at VS = 2.5 V operation to 265 LSB/g when operatingwith a supply voltage of 3.3 V. The z-axis sensitivity is unaffected bya change in supply voltage and is the same at VS = 3.3 V operation
as it is at VS = 2.5 V operation. Simple linear interpolation can beused to determine typical shifts in offset and sensitivity at othersupply voltages.

minimal offset shift across the operating temperature range. Due
to variability between parts, it is also recommended that calibration
over temperature be performed if any data rates below 6.25 Hz are
in use.

Figure 54. Typical X-Axis Output vs. Temperature at Lower Data Rates,
Normalized to 100 Hz Output Data Rate, VS = 2.5 V

Changes in noise performance, self-test response, and supply
current are discussed elsewhere throughout the data sheet. For
noise performance, the Noise Performance section should be reviewed. The Using Self-Test section discusses both the operationof self-test over voltage, a square relationship with supply voltage,
as well as the conversion of the self-test response in g’s to LSBs.
Finally, Figure 33 shows the impact of supply voltage on typicalcurrent consumption at a 100 Hz output data rate, with all other
output data rates following the same trend.
OFFSET PERFORMANCE AT LOWEST DATARATESFigure 55. Typical Y-Axis Output vs. Temperature at Lower Data Rates,
Normalized to 100 Hz Output Data Rate, VS = 2.5 V

The ADXL345 offers a large number of output data rates andbandwidths, designed for a large range of applications. However, atthe lowest data rates, described as those data rates below 6.25 Hz,
the offset performance over temperature can vary significantly fromthe remaining data rates. Figure 54, Figure 55, and Figure 56 show
the typical offset performance of the ADXL345 over temperature forthe data rates of 6.25 Hz and lower. All plots are normalized tothe offset at 100 Hz output data rate; therefore, a nonzero value
corresponds to additional offset shift due to temperature for thatdata rate.
When using the lowest data rates, it is recommended that theoperating temperature range of the device be limited to provide

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Figure 56. Typical Z-Axis Output vs. Temperature at Lower Data Rates,
Normalized to 100 Hz Output Data Rate, VS = 2.5 V

Rev. G | 34 of 36

Data SheetADXL345APPLICATIONS INFORMATIONAXES OF ACCELERATION SENSITIVITY

Figure 57. Axes of Acceleration Sensitivity (Corresponding Output Voltage Increases When Accelerated Along the Sensitive Axis)

Figure 58. Output Response vs. Orientation to Gravity

LAYOUT AND DESIGN RECOMMENDATIONS
Figure 59 shows the recommended printed wiring board land pattern.

Figure 59. Recommended Printed Wiring Board Land Pattern (Dimensions shown in millimeters)

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Data SheetADXL345OUTLINE DIMENSIONS

Figure 60. 14-Terminal Land Grid Array [LGA](CC-14-1)
Dimensions shown in millimeters
Updated: May 10, 2022

ORDERING GUIDE
Model1

Temperature Range

Package Description

Packing Quantity

Package
OptionADXL345BCCZ
ADXL345BCCZ-RL
ADXL345BCCZ-RL7-40°C to +85°C-40°C to +85°C-40°C to +85°C

14-Lead LGA (5mm x 3mm)
14-Lead LGA (5mm x 3mm)
14-Lead LGA (5mm x 3mm)

Tray
Reel, 5000
Reel, 1500

CC-14-1
CC-14-1
CC-14-1

1

Z = RoHS Compliant Part.

EVALUATION BOARDS
Model1

Description

EVAL-ADXL345Z
EVAL-ADXL345-DB
EVAL-ADXL345-M
EVAL-ADXL345-S

Evaluation Board
Evaluation Board
Analog Devices Inertial Sensor Evaluation System, Includes ADXL345 Satellite
ADXL345 Satellite, Standalone

1

Z = RoHS Compliant Part.

I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

©2009-2022 Analog Devices, Inc. All rights reserved. Trademarks andregistered trademarks are the property of their respective owners.
One Analog Way, Wilmington, MA 01887-2356, U.S.A.

Rev. G | 36 of 36