THC63LVDM83E_Rev.1.41_E

THC63LVDM83E
28bits LVTTL/CMOS to 4ch LVDS Serializer/Transmitter

General DescriptionFeatures

The THC63LVDM83E is a general purpose data
serializer based on LVDS technology with nooverhead for protocol or encoding.
The THC63LVDM83E converts 28bits ofCMOS/TTL data into 4ch LVDS data stream. The
transmitter can be programmed for rising edge orfalling edge clocks through a dedicated pin.

･49pin 0.65mm pitch VFBGA Package･Wide Input clock range: 8-160MHz･Maximum total throughput 4.48Gbit/s@160MHz･3.3/2.5/1.8/1.2V voltage logic input･LVDS swing is reducible by RS-pin to reduce EMI
and power consumption.
･PLL requires no external components.
･On chip jitter filtering.
･Spread Spectrum Clock input tolerant.
･Power down mode.
･Input clock triggering edge is selectable by R/F-pin.
･Operates from a Single 3.3V Supply and110mW(typ.) at 75MHz.

Block Diagram

RS
Normal/Small
Swing Level

Vref

7

7

28bit Parallel
Data Input

TB0-6

TC0-677
TD0-6

Clock Input(8 – 160MHz)

CLKIN

Multi-Level LVTTL/CMOS
Input Buffer

TA0-6

7:1Serializer

TA+

7:1
Serializer

TB+

7:1
Serializer

TC+

7:1
Serializer

TD+

PLL

TA-TB-

4ch Serial
Data Output(56 – 1120Mbps/ch)

TC-

TD-

TCLK+

Clock Output

TCLK-(8 - 160MHz)

R/F
/PDWN

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THC63LVDM83E_Rev.1.41_E

Ball OutTOP VIEW
1234567A

TA6TA5TA4TA3TA2TA1TA0B

TB4

TD3TD2

TD1TD0TA-TA+C

TB5TB0

GND

VCC

RS

TB-

TB+

D

TB6TB1GND

LVDS
VCC

LVDS
VCC

TC-TC+E

TC0TB2GNDPLL
VCC

R/F

TCLK- TCLK+F

TC1TB3

TD4TD5TD6TD-GTC2TC3TC4TC5TC6

CLKIN /PDWN

TD+Pin Description
Pin Name
TA+, TATB+, TBTC+, TCTD+, TDTCLK+, TCLKTA0 ~ TA6
TB0 ~ TB6
TC0 ~ TC6
TD0 ~ TD6
CLKIN

Pin #B7, B6
C7, C6
D7, D6
F7, F6
E7, E6
A7,A6,A5,A4,A3,A2,A1
C2,D2,E2,F2,B1,C1,D1
E1,F1,G1,G2,G3,G4,G5
B5,B4,B3,B2,F3,F4,F5
G6/PDWN

G7TypeLVDS
Output3.3V LVTTL
2.5/1.8/1.2V CMOS
Digital Input

E5RS

C5VCCC4GND
LVDS VCC
PLL VCC

C3,D3,E3
D4,D5
E4Copyright©2023 THine Electronics, Inc.

4ch Serial Data Output
Clock Output

3.3V LVTTL
Digital Input
R/F

Description

Analog Input

Power

228bit Parallel Data Input
Clock Input
Power Down Control
H: Normal operation
L: Power Down (All output are Hi-Z.)
Input Clock Triggering Edge Select
H: Rising edge
L: Falling edge
Input/output Level Select and 2.5/1.8/1.2V
Logic level Reference Voltage Input
RS-pin Input
Data/ClockVoltage Setting Input Voltage
VCC
3.3V
1.25V
2.5V
0.9V
1.8V
0.6V
1.2V
GND
3.3V

Input Buffer LVDS Output
Vref
VOD
VCC/2
1.25V
350mV
0.9V
0.6V
VCC/2200mVPower Supply Pin for LVTTL/CMOS input
and digital circuit.
Ground Pins for Common.
Power Supply Pins for LVDS Outputs.
Power Supply Pin for PLL circuit.

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THC63LVDM83E_Rev.1.41_E

Absolute Maximum Ratings
Parameter
Supply Voltage
LVTTL/CMOS and Analog Input Voltage
LVDS Transmitter Output Voltage
Output Current
Junction Temperature
Storage TemperatureReflow Peak Temperature
Reflow Peak Temperature Time
Maximum Power Dissipation @+25CMin-0.3-0.3-0.3-30-55-Max+4.0
VCC + 0.3
VCC + 0.330+125+125+260
101.2Units
VVVmA
C
C
Csec
W

Recommended Operating Conditions
Symbol
VCC
Ta
CLKIN

Parameter

Min
3.008

All Supply Voltage
Operating Ambient Temperature
Clock Frequency

Power Consumption
SymbolMax
3.6+70160

Units
V
C
MHz

VCC = 3.0~3.6V, Ta= 0~+70ºC

Parameter
LVDS Transmitter
Operating Current
Gray Scale Pattern 16(Fig.1)

ITCCW
LVDS Transmitter
Operating Current
Worst Case Pattern(Fig.2)
ITCCS

Typ3.325-Conditions
RL=100, CL=5pF, f=85MHz
RS=VCC, (RS=GND)
RL=100, CL=5pF, f=160MHz
RS=VCC, (RS=GND)
RL=100, CL=5pF, f=85MHz
RS=VCC, (RS=GND)
RL=100, CL=5pF, f=160MHz
RS=VCC, (RS=GND)

Typ*42(34)
58(50)
45(36)
63(55)Max

Units-mA-mA-

10

LVDS Transmitter
Power Down Current

67(56)
92(80)mA
mAµA*Typ values are at VCC=3.3V, Ta = +25ºC
CLKINfTA0,TB1,TC2

f/16

TA1,TB2,TC3

f/8

TA2,TB3,TC4

f/4

TA3,TB4,TC5f/2

TA4-TA6,TB0,TB5,TB6
TC0,TC1,TC6,TD0 – TD2

Steady State Low

TD3 – TD6

Steady State High

Figure 1. 16 Grayscale Pattern
CLKIN

f

Tx0 – Tx6

f/2

X=A,B,C,D

Figure 2. Worst Case Pattern
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THC63LVDM83E_Rev.1.41_E

LVTTL/CMOS DC Specifications
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
VIH

VIL
IINC

ParameterConditions
3.3V LVTTL
Vref =VCC/2
2.5/1.8/1.2V CMOS
Vref = RS Input Voltage
3.3V LVTTL
Vref =VCC/2
2.5/1.8/1.2V CMOS
Vref = RS Input Voltage
GND  VIN  VCC

High Level Input Voltage

Low Level Input Voltage
Input Current

Min

TypMax

2.0-

VCC

Vref
+0.1-

VCC

GND-

0.8

GND---

Vref
-0.1
10

VCC

VIH.max

Units
VV
A

*Typ values are at VCC=3.3V, Ta = +25ºC.
VCC

VIH.max

2.4V

VOH(*EIAJ)

2.0V

VIH.min

VCC/2

Vref

0.8V

VIL.max

0.4V

VOL(*EIAJ)GND

VCCVIL.min

VIH.max

2.3V

VOH(*EIAJ)

1.7V
1.35V
1.25V

VIH(*EIAJ)
VIH.min
Vref

1.15V

VIL.max

0.7V

VIL(*EIAJ)

0.2V
GND

VOL(*EIAJ)
VIL.min

VCC

VIH.max

1.2V

VOH(*EIAJ)

0.825V

VIH(*EIAJ)

1.07V
1.0V
0.9V

VIH(*EIAJ)
VIH.min
Vref

0.8V
0.68V
0.45V
GND

VIL.max
VIL(*EIAJ)
VOL(*EIAJ)
VIL.min

0.715V
0.7V
0.6V
0.5V
0.455V
0.325V
GND

VIH(*EIAJ)
VIH.min
Vref
VIL.max
VIL(*EIAJ)
VOL(*EIAJ)
VIL.min3.3V LVTTL
RS=VCC or GND

2.5V CMOS
RS=1.25V

1.8V CMOS
RS=0.9V

1.2V CMOS
RS=0.6V(*EIAJ ED-5001A Normal Range)(*EIAJ ED-5002A Normal Range)(*EIAJ ED-5003A Normal Range)(*EIAJ ED-5005A Normal Range)

Figure 3. LVTTL/CMOS Digital Input Compatibility

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THC63LVDM83E_Rev.1.41_E

LVDS DC Specifications
Over recommended operating supply and temperature ranges unless otherwise specified.
SymbolParameter

VOD

Differential Output Voltage∆VODIOSChange in VOD between
complementary output states
Common Mode Voltage
Change in VOC between
complementary output states
Output Short Circuit Current

IOZ

Output TRI-STATE Current

VOC∆VOCConditions
RS=VCC, 0.6 ~ 1.4V
RL=100Ω
RS=GND
RL=100ΩMin

TypMax

Units

250

350

450mV

120

200300mV

RL=100Ω--35mV

RL=100Ω

1.125

1.25

1.375

V

RL=100Ω--35mV

VOUT=GND, RL=100Ω
/PDWN=GND,
VOUT=GND to VCC---24mA--

10

A*Typ values are at VCC=3.3V, Ta = +25ºC.

Tn-Single

VOC

VOD

Tn+
VOD

Differential

TnVdiff=(Tn+)-(Tn-)

0V
VOD

n=0,1
n=A,B,C,D,CLK

Figure 4. LVDS DC Specifications

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THC63LVDM83E_Rev.1.41_E

LVTTL/CMOS AC Specifications
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
tTCIT
tTCP
tTCH
tTCL
tTCDtTStTH

Parameter
CLKIN Transition Time
CLKIN Period
CLKIN High Time
CLKIN Low Time
CLKIN to TCLK+/- Delay
Tx0-6 Setup time to CLKIN
Tx0-6 Hold time to CLKIN

Min
6.25
0.35T
0.35T
2.0
0.0

TypT0.5T
0.5T
3T-Max5.0125
0.65T
0.65T-Unitsnsnsnsnsnsnsns*Typ values are at VCC=3.3V, Ta = +25ºC

90%

90%10%10%

tTCIT

tTCIT

Figure 5. CLKIN Transmission TimetTCP
tTCH

tTCL

R/F = H

CLKIN*

Vref

Vref

Vref

R/F = LtTS
Tx0-6
X=A,B,C,D

Vref

tTH
Vref

Figure 6. LVTTL/CMOS Input Timings

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THC63LVDM83E_Rev.1.41_E

LVDS AC Specifications
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
tLVT
tTOP1
tTop0
tTop6
tTop5
tTop4
tTop3
tTop2

Parameter
LVDS Transition Time
Output Data Position0 (T=6.25ns ~ 20ns)
Output Data Position1 (T=6.25ns ~ 20ns)
Output Data Position2 (T=6.25ns ~ 20ns)
Output Data Position3 (T=6.25ns ~ 20ns)
Output Data Position4 (T=6.25ns ~ 20ns)
Output Data Position5 (T=6.25ns ~ 20ns)
Output Data Position6 (T=6.25ns ~ 20ns)

Min-0.15
T/7-0.15
2T/7-0.15
3T/7-0.15
4T/7-0.15
5T/7-0.15
6T/7-0.15

Typ0.6
0.0
T/7
2T/7
3T/7
4T/7
5T/7
6T/7

Max
1.5+0.15
T/7+0.15
2T/7+0.15
3T/7+0.15
4T/7+0.15
5T/7+0.15
6T/7+0.15

Unitsnsnsnsnsnsnsnsns*Typ values are at VCC=3.3V, Ta = +25ºC

Vdiff = (TA+) – (TA-)
TA+5pF

80%

90%

20%

10%

Vdiff

100Ω
TA-tLVTtLVT

Figure 7. LVDS Output Load and Transmission Time

TCLK0V

0V(Differential)

tTOP2 max
tTOP2 mintTOP3 max
tTOP3 mintTOP4 max
tTOP4 mintTOP5 maxtTOP5 mintTOP6 max
tTOP6 mintTOP0 max
tTOP0 mintTOP1 max
tTOP1 minTx+/(Single)

VOC

Tx1

Tx0

Tx6

Tx5

Tx4

Tx3

Tx2

Tx1

Tx0

Tx6

X=A,B,C,D
Previous Cycle

Next Cycle

Figure 8. LVDS Output Data Position

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THC63LVDM83E_Rev.1.41_E

Input to Output AC Specifications
Over recommended operating supply and temperature ranges unless otherwise specified.
SymboltTCDtTPLL

Parameter
CLKIN to TCLK+/- Delay
Phase Lock Loop Set

Min-Typ3T-Max
10.0Units
nsms*Typ values are at VCC=3.3V, Ta = +25ºC

R/F = H

Vref

CLKIN
R/F = LtTCD
TCLKVOC

TCLK+Figure 9. CLKIN to TCLK+/- Delay

VCC

3V
Min.0sec

CLKIN

2V

Min.0sec/PDWN

2VtTPLL
TCLK

Vdiff=0V

Figure 10. PLL Set Time

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THC63LVDM83E_Rev.1.41_E

Board Layout Example

TOP VIEW
1234

5

67A

TA6TA5TA4TA3TA2TA1TA0A

B

TB4TD3TD2TD1TD0TA-TA+B

C

TB5TB0GNDVCC

RS

TB-

TB+

C

DTB6TB1

GND

LVDS
VCC

LVDS
VCC

TC-TC+

D

E

TC0

TB2

GND

PLL
VCC

R/F

TCLK-

TCLK+

E

F

TC1TB3TD4TD5TD6TD-

TD+

F

G

TC2

TC3TC4TC5TC6

CLKIN

/PDWN

G1234567R0R1R2R3R4R5R6R7B0
B1G0G1G2G3G4G5G6G7TA6TA5TA4TA3TA2

TA1TA0

TB4TD3TD2

TD1

TD0

TA-

TA+

TB5TB0

GND

VCC

RS

TB-

TB+

TB6TB1

GND

LVDS
VCC

LVDS
VCC

TC-

TC+

TC0

TB2GND

PLL
VCC

R/F

TCLK-TCLK+TC1
TC2TB3TC3TD4TC4TD5TC5TD6TC6TDCLKIN

TD+/PWDN

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THC63LVDM83E_Rev.1.41_E

Note1) Cable Connection and Disconnection
Don’t connect and disconnect the LVDS cable, when the power is supplied to the system.

2) GND Connection
Connect the each GND of the PCB which THC63LVDM83E and LVDS-Rx on it.
reduction to place GND cable as close to LVDS cable as possible.

It is better for EMI3) Multi Drop Connection
Multi drop connection is not recommended.

TCLK+
THC63LVDM83E

LVDS-RxTCLKLVDS-Rx4) Asynchronous use
Asynchronous using such as following systems are not recommended.

CLKOUT
DATA
IC

TCLK+
THC63LVDM83E

CLKOUTDATA

TCLK-CLKOUT
LVDS-RxIC

TCLK+
THC63LVDM83E

TCLK-

CLKOUTDATAICLVDS-Rx

DATA

TCLK+
THC63LVDM83E

CLKOUTDATADATATCLKTCLK+

THC63LVDM83E

IC

TCLK-Package

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THC63LVDM83E_Rev.1.41_E

PIN A1 CORNERTOP VIEW
1234567ABCDEFG

5.0

BOTTOM VIEWPIN A1 CORNER

Φ0.3
7654321ABCDEFG3.90

SIDE VIEW

Unit : mm

0.3

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THC63LVDM83E_Rev.1.41_E

Notices and Requests
1.

The product specifications described in this material are subject to change without prior notice.

2.

The circuit diagrams described in this material are examples of the application which may not always apply to the customer’s
design. THine Electronics, Inc. (“THine”) is not responsible for possible errors and omissions in this material. Please noteeven if errors or omissions should be found in this material, THine may not be able to correct them immediately.

3.

This material contains THine’s copyright, know-how or other intellectual property rights. Copying, reverse-engineer ordisclosing to third parties the contents of this material without THine’s prior written permission is prohibited.

4.

THINE ACCEPTS NO LIABILITY FOR ANY DAMAGE OR LOSS IN CONNECTION WITH ANY DISPUTE
RELATING TO INTELLECTUAL PROPERTY RIGHTS BETWEEN THE USER AND ANY THIRD PARTY, ARISINGOUT OF THIS PRODUCT, EXCEPT FOR SUCH DAMAGE OR LOSS IN CONNECTION WITH DISPUTESSUCCESSFULLY PROVED BY THE USER THAT SUCH DISPUTES ARE DUE SOLELY TO THINE. NOTE,HOWEVER, EVEN IN THE AFOREMENTIONED CASE, THINE ACCEPTS NO LIABILITY FOR SUCH DAMAGE ORLOSS IF THE DISPUTE IS CAUSED BY THE USER’S INSTRUCTION.

5.

This product is not designed for applications that require extremely high-reliability/safety such as aerospace device, nuclearpower control device, or medical device related to critical care, excluding when this product is specified for automotive use by
THine and used it for that purpose. THine accepts no liability whatsoever for any damages, claims or losses arising out of theuses set forth above.

6.

Despite our utmost efforts to improve the quality and reliability of the product, faults will occur with a certain smallprobability, which is inevitable to a semi-conductor product. Therefore, you are encouraged to have sufficiently fail-safe
design principles such as redundant or error preventive design applied to the use of the product so as not to have our productcause any social or public damage.

7.

This product may be permanently damaged and suffer from performance degradation or loss of mechanical functionality if
subjected to electrostatic charge exceeding capacity of the ESD (Electrostatic Discharge) protection circuitry. Safety earth
ground must be provided to anything in contact with the product, including any operator, floor, tester and soldering iron.

8.

Please note that this product is not designed to be radiation-proof.

9.

Testing and other quality control techniques are used to this product to the extent THine deems necessary to support warranty
for performance of this product. Except where mandated by applicable law or deemed necessary by THine based on the user’s
request, testing of all functions and performance of the product is not necessarily performed.

10. This product must be stored according to storage method which is specified in this specifications. THine accepts no liability
whatsoever for any damage or loss caused to the user due to any storage not according to above-mentioned method.
11. Customers are asked, if required, to judge by themselves if this product falls under the category of strategic goods under theForeign Exchange and Foreign Trade Act in Japan and the Export Administration Regulations in the United States of America
on export or transit of this product. This product is prohibited for the purpose of developing military modernization, including
the development of weapons of mass destruction (WMD), and the purpose of violating human rights.
12. The product or peripheral parts may be damaged by a surge in voltage over the absolute maximum ratings or malfunction, ifpins of the product are shorted by such as foreign substance. The damages may cause a smoking and ignition. Therefore, youare encouraged to implement safety measures by adding protection devices, such as fuses. THine accepts no liability
whatsoever for any damage or loss caused to the user due to use under a condition exceeding the limiting values.
13. All patents or pending patent applications, trademarks, copyrights, layout-design exploitation rights or other intellectual
property rights concerned with this product belong to THine or licensor(s) of THine. No license or right is granted to the user
for any intellectual property right or other proprietary right now or in the future owned by THine or THine’s licensor. The user
must enter into a license agreement with THine or THine’s licensor to be granted of such license or right.

THine Electronics, Inc.
https://www.thine.co.jp

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