THC63LVD827_DesignGuide_Rev.1.20_E

THC63LVD827
System Diagram and PCB Design Guide

Copyright©2024 THine Electronics, Inc.

1THine Electronics, Inc.

SC E

THC63LVD827_DesignGuide_Rev.1.20_E

Contents
1. Mode Settings

P.3

2. Signal Flow for Each Setting

P.3

3. COMS/TTL DATA Timing Diagram

P.4

4. LVDS DATA Timing Diagram

P.6

5. LVDS DATA Mapping

P.8

6. Example of System Diagram
1) Single In–Single Out / 8bit COMS/TTL Input / IO VCC=1.8V
2) Single In –Dual Out / 8bit COMS/TTL Input / IO VCC = 1.8V
3) Single In –Dual Out / 6bit COMS/TTL Input / IO VCC = 3.3V

P.10
P.11
P.12

7. NOTE

P.13

8. Trace Example for BGA

P.14

9. PCB Design Guide Line for LVDS

P.15

Copyright©2024 THine Electronics, Inc.

2

THine Electronics, Inc.

SC E

THC63LVD827_DesignGuide_Rev.1.20_E

1. Mode Settings

Input / Output

OptionSingle In /Single Out

Output Disable (Hi-Z)
Output Enable
Output Disable (Hi-Z)
Output Enable/DDR off
Output Enable/DDR on

Single In /Dual OutMODE
Input Mode
H : Single
L : DualHHLLLDDRN
Double Data Rate
H : DDR Input off
L : DDR Input onH
L

O/E
Output Enable
H : Enable
L : Disable
LHLHH

2. Signal Flow for Each Setting

Single In / Single Out

CLK Frequencyf

DATA RatefTA1+/TB1+/TC1+/TD1+/TCLK1+/-

R[7:0]
G[7:0]
B[7:0]
HSYNC
VSYNC
DE
CLKIN

TA2+/TB2+/TC2+/TD2+/TCLK2+/-

CLK Frequencyf
DATA Ratef

Hi-ZSingle In / Dual Out
Double Data Rate off

CLK Frequencyf

DATA Ratef

R[7:0]
G[7:0]
B[7:0]HSYNC
VSYNCDE
CLKIN

Single In / Dual Out
Double Data Rate on
TA1+/TB1+/TC1+/TD1+/TCLK1+/-

CLK Frequency
f/2

TA2+/TB2+/TC2+/TD2+/TCLK2+/-

CLK Frequency
f/2

DATA Rate
f/2

CLK Frequency
f/2

DATA Rate
f/2

TCLK1+/-

Copyright©2024 THine Electronics, Inc.

DATA Ratef

R[7:0]
G[7:0]
B[7:0]
HSYNC
VSYNC
DE
CLKIN

TA1+/TB1+/TC1+/TD1+/TCLK1+/-

CLK Frequency
f/2

TA2+/TB2+/TC2+/TD2+/TCLK2+/-

CLK Frequency
f/2

TCLK1+/-

3

THine Electronics, Inc.

SC E

DATA Rate
f/2

DATA Rate
f/2

THC63LVD827_DesignGuide_Rev.1.20_E

3. COMS/TTL Data Timing Diagram
1) Single Edge Input Mode (MODE=H or MODE=L, DDR=H)
IOVCC
CLKIN
GND
RGB
HSYNC
VSYNC
DEIOVCC
GND

2) Double Edge Input Mode (MODE=L, DDR=L)
IOVCC
CLKIN
GND
RGB
HSYNC
VSYNC
DE

Copyright©2024 THine Electronics, Inc.

IOVCC
GND

4

THine Electronics, Inc.

SC E

THC63LVD827_DesignGuide_Rev.1.20_E

3) Data sorting example of TTL input versus LVDS output in Single-In Dual-Out mode with double edge Input
mode for 1920 x 1440 panel.

Single CMOS/TTL Input

THC63LVD827Dual LVDS Output#1CH1CH2#2#1919 #1920

TFT Panel(1920 x 1440)

MSB

LSB

Copyright©2024 THine Electronics, Inc.

R17R16R15R14R13R12R11R10G17G16G15G14G13G12G11G105B17B16B15B14B13B12B11B10

THine Electronics, Inc.

SC E

THC63LVD827_DesignGuide_Rev.1.20_E

4. LVDS Data Timing Diagram
1) Single In- Dual Out Mode (MODE=L)

Copyright©2024 THine Electronics, Inc.

6

THine Electronics, Inc.

SC E

THC63LVD827_DesignGuide_Rev.1.20_E

2) Single In- Single Out Mode (MODE=H)

Copyright©2024 THine Electronics, Inc.

7

THine Electronics, Inc.

SC E

THC63LVD827_DesignGuide_Rev.1.20_E

5. LVDS Data Mapping
1) for 8 bit mode (6B/8B=L)

Copyright©2024 THine Electronics, Inc.

8

THine Electronics, Inc.

SC E

THC63LVD827_DesignGuide_Rev.1.20_E

2) for 6 bit mode (6B/8B=H)

Copyright©2024 THine Electronics, Inc.

9

THine Electronics, Inc.

SC E

THC63LVD827_DesignGuide_Rev.1.20_E

6. Example of System Diagram
1) Single In–Single Out / 8bit 1.8V COMS/TTL Input
PCB Transmitter

PCB Receiver

1.8 VCC
F.BeadF.Bead
0.01uF
Decupling Cap
X2 for 2 VCC

Decupling Cap
X2 for 2 LVDS VCC

0.01uFVCC
GND

LVDS VCC
0.1uF

0.1uF
0.01uFIO VCC
0.1uF
0.01uF
/PDWN
MODE
DDRN

OPEN

Setting
Setting
IO
IOVCC
VCC
GND
GND
SettingR10ohm
IO VCCNC (default)
GND

Setting

Setting
IO VCCIO VCC
GND
GND

CLKIN
R10R11R12R13
R14R15
R16
R17G10
G11G12
G13
G14
G15
G16
G17
B10B11B12
B13
B14
B15
B16
B17HSYNC
VSYNC
DE

O/E
O/E
OutputEnableOutputEnableOutputDisable/ Hi-Z
OutputDisable/ Hi-ZRS R2NC
350mV Swing
0ohm(default)
200mVSwing

0.1uF

100ohm pair cableor
PCB trace

PRBS
NC
Reserved
6B/8B
O/E
RS
R/F
MAP

CLKIN
R0R1R2
R3
R4R5R6R7G0G1G2G3G4
G5G6G7
B0
B1B2B3B4B5B6B7
HSYNC
VSYNC
DE

PLL VCC

TA1TA1+100ohm

TB1TB1+100ohm

TC1TC1+100ohm

TCLK1TCLK1+100ohm

TD1TD1+100ohm

TA2TA2+

LVDS Receiver
CircuitTB2TB2+
TC2TC2+OPEN

TCLK2TCLK2+
TD2TD2+

COMS/TTL
1.8V
1.8V

R/F

RSLVDS=350mV
LVDS=200mV

GND

GND

R/F
Rising Edge
Rising Edge
Falling Edge
Falling Edge

Setting

MAP

Setting
IO VCCIO GNDVCCGND

MAP Mode 1Mapping
Mapping
Mode1 2Mapping
Mode
Mapping Mode 2

Note :
 O/E, RS, R/F, MAP : Please select IOVCC level or GND level, it depends on your operation.
 Connect each Board GND Please prepare the 100ohm pair cable or PCB pattern trace that is controlled with 100ohm for
LVDS signal.

Copyright©2024 THine Electronics, Inc.

10THine Electronics, Inc.

SC E

THC63LVD827_DesignGuide_Rev.1.20_E

2) Single In –Dual Out / 8bit 1.8V COMS/TTL Input
DDR(Double Edge input) function disable.
PCB Transmitter

PCB Receiver

1.8 VCC
F.BeadF.Bead
0.01uF
Decupling Cap
X2 for 2 VCC

Decupling Cap
X2 for 2 LVDS VCC

0.01uFVCC
GND

LVDS VCC
0.1uF

0.1uF
0.01uFIO VCC
0.1uF
0.01uF
/PDWN
DDRN
MODE

OPEN

Setting
Setting
IO
IOVCC
VCC
GND
GND
SettingR10ohm
IO VCCNC (default)
GND

Setting

Setting
IO VCCIO VCC
GND
GND

CLKIN
R10R11R12R13R14R15R16R17G10G11G12G13G14G15G16G17B10B11B12B13
B14B15B16
B17
HSYNC
VSYNC
DEO/E
O/E
OutputEnableOutputEnableOutputDisable/ Hi-Z
OutputDisable/ Hi-ZRS R2NC
350mV Swing
0ohm(default)
200mV
Swing

COMS/TTL
1.8V
1.8V

0.1uF

100ohm pair cableor
PCB trace

PRBS
NC
Reserved
6B/8B
O/E
RS
R/F
MAP

CLKIN
R0
R1
R2
R3R4
R5R6
R7
G0G1
G2G3G4G5G6G7
B0B1B2B3B4B5B6B7HSYNC
VSYNC
DE

PLL VCC

TA1TA1+100ohm

TB1TB1+100ohm

TC1TC1+100ohm

TCLK1TCLK1+100ohm

TD1TD1+100ohm

TA2TA2+100ohm

TB2TB2+100ohm

TC2TC2+100ohm

TCLK2TCLK2+100ohm

TD2TD2+100ohm

LVDS Receiver
CircuitRS
LVDS=350mV
LVDS=200mV

R/F

GND

GND

R/F
Rising Edge
Rising Edge
Falling Edge
Falling Edge

Setting

MAP

Setting
IO VCC
IOGND
VCC
GND

MAP Mode 1
Mapping
MappingMode
1 2Mapping
Mode
Mapping Mode 2

Note :
 O/E, RS, R/F, MAP : Please select IOVCC level or GND level, it depends on your operation.
 Connect each Board GND Please prepare the 100ohm pair cable or PCB pattern trace that is controlled with 100ohm for
LVDS signal.

Copyright©2024 THine Electronics, Inc.

11THine Electronics, Inc.

SC E

THC63LVD827_DesignGuide_Rev.1.20_E

3) Single In –Dual Out / 3.3V 6bit COMS/TTL Input
DDR(Double Edge input) function enable
PCB Transmitter
3.3 VCCPCB Receiver

1.8 VCC
F.BeadF.Bead
0.01uF

Decupling Cap
X2 for 2 VCC

Decupling Cap
X2 for 2 LVDS VCC

0.01uFVCC
GND

LVDS VCC
0.1uF

0.1uF
0.01uFIO VCC
0.1uF
0.01uF
/PDWN
DDRN
MODE

OPEN

PLL VCC
0.1uF

100ohm pair cableor
PCB trace

PRBS
NC
Reserved
6B/8B
O/E
RS
R/F
MAP

CLKIN
R2R3
R4R5
R6R7G2G3G4G5G6G7
B2B3B4B5B6B7VSYNC
HSYNC
DESettingSetting
IO VCCIO VCC
GND
GND

O/E

RS
R2350mV
Swing
NC
200mV
Swing
0ohm (default)

Setting
Setting
IO IO
VCC
VCC
GND
GND

R/F
R/F
RisingRisingEdge
Edge
Falling
FallingEdge
Edge

Setting
Setting
IO VCCIO VCCGNDMAP
MAP
Mapping
Mode 1
Mapping Mode 1
Mapping Mode 2

GND

R13R14R12R15R16R17G12G13G14G15G16G17B12B13B14
B15B16B17HSYNC
VSYNC
DER10R11G10G11B10B11O/E
Output Enable
Output Enable
Output Disable / Hi-Z
Output Disable / Hi-Z

Setting
R1
IO0ohmVCC
NCGND(default)

CLKIN

COMS/TTL
1.8V
1.8V

TA1TA1+

100ohmTB1TB1+100ohm

TC1TC1+100ohm

TCLK1TCLK1+
TD1TD1+100ohm
OPEN

LVDS Receiver
CircuitOPEN

TA2TA2+100ohm

TB2TB2+100ohm

TC2TC2+100ohm

TCLK2TCLK2+
TD2TD2+100ohm
OPENOPENRS
LVDS=350mV
LVDS=200mV

GND

GND

Mapping Mode 2

Note :
 O/E, RS, R/F, MAP : Please select IOVCC level or GND level, it depends on your operation.
 Connect each Board GND Please prepare the 100ohm pair cable or PCB pattern trace that is controlled with 100ohm for
LVDS signal.

Copyright©2024 THine Electronics, Inc.

12

THine Electronics, Inc.

SC E

THC63LVD827_DesignGuide_Rev.1.20_E

7. Note7.1) Cable Connection and Disconnection
Do not connect and disconnect the LVDS cable, when the power is supplied to the system.

7.2) GND Connection
Connect the each GND of the Board which THC63LVDM83E and Receiver on it.
It is better for EMI reduction to place GND cable as close to LVDS cable as possible.

7.3) Multi Drop Connection
Multi drop connection is not recommended.

TCLK+
THC63LVD827

Receiver IC
TCLKReceiver IC

7.3) Asynchronous use
Asynchronous uses such as following systems are not recommended. If it’s not avoidable, please contact tomspsupport@thine.co.jp(for FAE mailing list)

CLKOUTDATAICTCLK+
THC63LVD827!

CLKOUTDATA

TCLK-

THC63LVD827

DATA
IC

DATA
CLKOUT

Receiver IC

IC

DATA

TCLK+
THC63LVD827

TCLK-!

CLKOUT
DATA

Receiver IC

TCLK+
TCLK-

CLKOUT

CLKOUT

THC63LVD827

Copyright©2024 THine Electronics, Inc.

TCLK+

IC

TCLK-

13

THine Electronics, Inc.

SC E

THC63LVD827_DesignGuide_Rev.1.20_E

8. Trace Example for BGA

TOP VIEW

123456789A

TA1+

TB1+

TC1+

TCLK1+

TD1+

TA2+

TB2+

TC2+

TCLK2+

A

B

TA1-

TB1-

TC1-

TCLK1-

TD1-

TA2-

TB2-

TC2-

TCLK2-BC

PRBSNCReserved1

GND

LVDS
VCC

GND

PLL
VCC

TD2-

TD2+

C

D

R11R10LVDS
VCC

GND

/PWDN

O/E

DE

R13R12GND

MODE

MAP

DDRN

E

F

R15R14GND

6B/8B

RS

CLKIN

F

G

R17

R16VCC

GND

VCC

GND

IO
VCC

R/F

DE

G

H

G10G12G14G16

B10B12B14

B16

VSYNC

H

J

G11G13G15G17B11

B13B15

B17

HSYNC

J

123456789R0
R1
R2
R3
R4
R5
R6
R7

TA1+

TB1+

TC1+

TCLK1+

TD1+

TA2+

TB2+

TC2+

TCLK2+

TA1TA1TA1+

TB1-

TC1-TCLK1-

TD1-

TA2-

TB2-

TC2-

TCLK2-

PRBS
PRBS

NC
NC

LVDS
VCC

GND

PLL
VCC

TD2-

TD2+

LVDS
VCC

PLL
GND

PLL
GND
PLL
GND

/PDWN
/ PWDN

O/E
O/E

Reserved1
Reserved1 GND
LVDS
GND

R11R10R10LVDS
VCC
VCC

R13R12R

GND
GND

MODE
MODE

MAP
MAP

DDRN
DDRN

Reserv
6B/8B 2ed

RS
RS

CLKIN
CLKIN

R15R14GND
GND

RR17R16
R16VCC
VCC

GND

VCC

GND
GND

IOVCC
VCC

R/F
R/F

DE
DE

G10G10G12G14G16GB10B12B14B14B16

VSYNC
VSYNC

G11G11G13G15G17B11B13B15B17HSYNC

G0G1G2G3G4G5G6G7B0B1B2B3B4B5B6B7Copyright©2024 THine Electronics, Inc.

14

THine Electronics, Inc.

SC E

THC63LVD827_DesignGuide_Rev.1.20_E

9. PCB Design Guide Line
General Guideline
Use 4 layers PCB (minimum).

Locate by-pass capacitors adjacent close to the device pins to a maximum extent.

Make the loop minimum which is consist of Power line and GND line.

Use large GND plane.

Separate VDD power supply for each block via ferrite bead.

LVDS Trace
Interconnecting media between Transmitter and Receiver (i.e. PCB trace, connector and cable) should bewell balanced. (Keep all these differential impedance and the length of media as same as possible)

Minimize the distance between traces of a pair (S1) to maximize common mode rejection. See followingfigure.

Place adjacent LVDS trace pair at least twice (>2 x S1) as far away as possible.

Avoid 90 degree bends and sharp angles.

Minimize the number of VIA on LVDS traces.

Match impedance of PCB trace, connector, cable and termination to minimize reflections (emissions) for
cabled applications (typically 100ohm differential mode characteristic impedance).

Place terminal resistor close to the Receiver pins to a maximum extent.

To place common mode choke coil is desired for EMI reduction.

S1> 2 x S1

GND+Signal

Copyright©2024 THine Electronics, Inc.

-Signal15+Signal-SignalTHine Electronics, Inc.

SC E

THC63LVD827_DesignGuide_Rev.1.20_E

Notices and Requests
1. The product specifications described in this material are subject to change without prior notice.
2. The circuit diagrams described in this material are examples of the application which may notalways apply to the customer’s design. THine Electronics, Inc. (“THine”) is not responsible
for possible errors and omissions in this material. Please note even if errors or omissions
should be found in this material, THine may not be able to correct them immediately.
3. This material contains THine’s copyright, know-how or other intellectual property rights.

Copying, reverse-engineer or disclosing to third parties the contents of this material without
THine’s prior written permission is prohibited.
4. THINE ACCEPTS NO LIABILITY FOR ANY DAMAGE OR LOSS IN CONNECTIONWITH ANY DISPUTE RELATING TO INTELLECTUAL PROPERTY RIGHTSBETWEEN THE USER AND ANY THIRD PARTY, ARISING OUT OF THIS PRODUCT,EXCEPT FOR SUCH DAMAGE OR LOSS IN CONNECTION WITH DISPUTESSUCCESSFULLY PROVED BY THE USER THAT SUCH DISPUTES ARE DUE SOLELYTO THINE. NOTE, HOWEVER, EVEN IN THE AFOREMENTIONED CASE, THINEACCEPTS NO LIABILITY FOR SUCH DAMAGE OR LOSS IF THE DISPUTE ISCAUSED BY THE USER’S INSTRUCTION.
5. This product is not designed for applications that require extremely high-reliability/safety suchas aerospace device, nuclear power control device, or medical device related to critical care,excluding when this product is specified for automotive use by THine and used it for that
purpose. THine accepts no liability whatsoever for any damages, claims or losses arising outof the uses set forth above.
6. Despite our utmost efforts to improve the quality and reliability of the product, faults will

occur with a certain small probability, which is inevitable to a semi-conductor product.
Therefore, you are encouraged to have sufficiently fail-safe design principles such as
redundant or error preventive design applied to the use of the product so as not to have ourproduct cause any social or public damage.
7. This product may be permanently damaged and suffer from performance degradation or loss of

mechanical functionality if subjected to electrostatic charge exceeding capacity of the ESD(Electrostatic Discharge) protection circuitry. Safety earth ground must be provided toCopyright©2024 THine Electronics, Inc.

16THine Electronics, Inc.

SC E

THC63LVD827_DesignGuide_Rev.1.20_E

anything in contact with the product, including any operator, floor, tester and soldering iron.
8. Please note that this product is not designed to be radiation-proof.
9. Testing and other quality control techniques are used to this product to the extent THine deems

necessary to support warranty for performance of this product. Except where mandated byapplicable law or deemed necessary by THine based on the user’s request, testing of all
functions and performance of the product is not necessarily performed.
10. This product must be stored according to storage method which is specified in thisspecifications. THine accepts no liability whatsoever for any damage or loss caused to the user
due to any storage not according to above-mentioned method.
11. Customers are asked, if required, to judge by themselves if this product falls under thecategory of strategic goods under the Foreign Exchange and Foreign Trade Act in Japan andthe Export Administration Regulations in the United States of America on export or transit ofthis product. This product is prohibited for the purpose of developing military modernization,including the development of weapons of mass destruction (WMD), and the purpose of
violating human rights.
12. The product or peripheral parts may be damaged by a surge in voltage over the absolute
maximum ratings or malfunction, if pins of the product are shorted by such as foreign
substance. The damages may cause a smoking and ignition. Therefore, you are encouraged to
implement safety measures by adding protection devices, such as fuses. THine accepts noliability whatsoever for any damage or loss caused to the user due to use under a condition
exceeding the limiting values.
13. All patents or pending patent applications, trademarks, copyrights, layout-design exploitationrights or other intellectual property rights concerned with this product belong to THine orlicensor(s) of THine. No license or right is granted to the user for any intellectual property
right or other proprietary right now or in the future owned by THine or THine’s licensor. Theuser must enter into a license agreement with THine or THine’s licensor to be granted of suchlicense or right.

THine Electronics, Inc.
https:www.thine.co.jp

Copyright©2024 THine Electronics, Inc.

17

THine Electronics, Inc.

SC E