THCV213_THCV214_Design Guide_Rev.1.11_E

THCV213/THCV214 Application Note
System Diagram and PCB Design Guideline

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THCV213_THCV214_Design Guide_Rev.1.11_E

1) TTL DATA Timing Diagram
The following is THCV213 TTL data input timing example for SVGA(800 x 600).
HSYNC
DEDot CLK
Rx/Gx/Bx

#1

#2

#1

#2

#3

#4

#798 #799 #800

x=0～5
See note.1)#799 #800

TFT Panel(800 x 600)

Note.
1) RGB signal Assignments.
RedR5R4R3R2R1R0MSB

6bit LSBGreen
G5G4G3G2G1G0Blue
B5B4B3B2B1B02) Min. pulse widths for HSYNC/VSYNC/DE are 2pixels.

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THCV213_THCV214_Design Guide_Rev.1.11_E

2) Examples of System Diagram(i) Normal Mode
Example:
THCV213: Falling edge / without pre-emphasis.
THCV214: Falling edge / Normal Mode.

ferritebead

0.001uF
0.1uF

CLKIN

THCV213
LVDSVDDGND

LVDSGND

CLKIN

PLLVDD

D17D16
D15D14D13D12D11D10D9
D8
D7D6D5D4D3D2D1
D0

PLLGND

DE
HSYNC
VSYNC
CTRL

DE
SYNC0SYNC1SYNC2/PDWN/PDWN

0.001uF

0.001uF

0.1uF

0.1uF

0.001uF

0.001uF

0.1uF

4.7uF

100Ω twist
Pair Cable
orPCB Trace

TXOUT+TXOUT-

0.1uF

INIT

100Ω

LOCKN

LVDSGND

PRE1PRE0

NM

NM

0Ω0Ω

CLKOUTPLLGND

D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0

VDDO
GNDO
RXIN+RXIN+

LOCKN

EDGE
OE
MOD0MOD1RESERVED0/PDWN

GND

PLLVDD

EDGE
VDD

10uF

THCV214
LVDSVDD
VDD

0.001uF

CON

R5R4R3R2
R1R0G5G4G3G2G1G0
B5B4B3B2B1B0

VDD

CON

VDD

VDD

ferritebead

DE
SYNC0SYNC1SYNC20.001uF
0.1uF

CLKOUT
R5R4R3R2
R1R0
G5G4G3G2G1G0
B5B4B3B2B1B0
DE
HSYNC
VSYNC
CTRL

/PDWN

*1
GND

GND
PCB (Transmitter)

PCB (Receiver)Note:
DE signal must meet the following requirements:
1) Min. of DE=L duration is 50 Clocks
2) Max. of DE=H pulse width is 80us, Min.of DE=H pulse width is 2clocks*1: Connect each PCB GND

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THCV213_THCV214_Design Guide_Rev.1.11_E(ii) Shake Hand Mode
Example:
THCV213: Falling edge / Pre-emphasis (100%) mode.
THCV214: Falling edge / Shake Hand Mode.

ferritebead

VDD

THCV213
LVDSVDDGND

LVDSGND

CLKIN

CLKIN

PLLVDD

R5
R4
R3R2
R1R0
G5G4G3G2G1
G0
B5B4B3B2VDD B1B0

D17
D16D15D14D13D12D11D10D9D8D7D6D5D4D3D2
D1
D0

PLLGND

0.001uF
0.1uF

0.1uF

0.1uF

0.001uF

0.001uF

0.1uF

4.7uF

100Ω twist
Pair Cable
orPCB Trace

TXOUT+

0.1uF

100Ω

TXOUT-INIT

LVDSGND

PRE1
PRE0

CLKOUTPLLGND

D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5D4
D3
D2D1
D0

VDDO
GNDO
RXIN+RXIN+

LOCKN

0Ω0Ω

NM

NM

EDGE
OE
MOD0MOD1RESERVED0/PDWN

/PDWN

GND

PLLVDD

EDGE
VDD

10uF

THCV214
LVDSVDD
VDD

0.001uFDE
SYNC0SYNC1SYNC2/PDWN

0.001uF

CONDE

0.001uF

CON

VDD

VDD

ferritebeadDE
SYNC0SYNC1SYNC20.001uF
0.1uF

CLKOUT
R5R4R3R2R1R0G5G4G3G2G1G0
B5B4B3B2B1B0
DE=H
SYNC0=LSYNC1=LSYNC2=L/PDWN

*1
GND

GND
PCB (Transmitter)

PCB (Receiver)Note:
If there is no DE input, you must keep DE of THCV213 high and set SYNC2-0 low.

DE signal must meet the following requirements:
1) Min.of DE=H pulse width is 2clocks2) Min.of DE=L pulse width is 2clocks*1: Connect each PCB GND

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THCV213_THCV214_Design Guide_Rev.1.11_E

3) Timing Chart
Following timing chart is common for all link mode.
THCV213: Falling edge (EDGE=Low)
THCV214: Falling edge (EDGE=Low)
THCV213 Input

tPWLDEtPWHDE

CLKIN
INIT

Fix LowDE
D<17:0>

Don’t Care

Don’t Care
Don’t CareSYNC<2:0>

Don’t Care

THCV214 Output
CLKOUTLOCKN

Fix LowDE
D<17:0>

Fix Low

SYNC<2:0>

Fix Low
Keep value

Keep valueRequirements for DE pulse width
THCV214 ModetPWHDE

tPWLDE

Remarks

NormalMin. 2Clock
Max. 80usMin. 50Clock-Shake Hand

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THCV213_THCV214_Design Guide_Rev.1.11_E

4) THCV214 Receiver Eye Mask Diagram.
Differential voltage/timing (EYE) diagram
Eye diagram measurement is performed with an oscilloscope capable of recovering clock from the incoming data
stream. The clock recovery algorithm is set as specified in Table 1. Differential eye measurement is performed ateither the termination resistor located close to the receiver chip or the chip package pins. Waveforms equivalent to
100,000 UI's are captured for the eye mask test.
Refer to Figure 1 and Table2 for receiver eye mask specifications.

Table1 Clock Recovery Algorithm for Eye Mask Test
ItemValue

Clock Recovery Method
Nominal Data Rate
PLL's Loop Bandwidth
Damping Factor

Unit

2nd order PLL
Pixel clock *21
0.3
0.6bpsMHz-1UI = 1/(serial data rate)

FAYEBD

Y=0mVCX
X=0UI

X=1UIFigure 1 Receive EYE MaskTable 2 Receiver Mask Vertices TableABCDEFX[UI]

Y[mV]

0.2
0.35
0.65
0.8
0.65
0.35

0-50-5005050

Note1: UI=Unit Interval.

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THCV213_THCV214_Design Guide_Rev.1.11_E

5) PCB Design Guide Line for LVDS.





Use at least four-layer PCBs with signals, ground, power, and signals assigned for each layer. (Refer tofigure below.)
PCB traces for high-speed signals must be single-ended micro-strip lines or coupled micro-strip lines
whose differential characteristic impedance is 100Ω.
Minimize the distance between traces of a differential pair (S1) to maximize common mode rejection andcoupling effect which works to reduce EMI (Electro-Magnetic Interference).
Route differential signal traces symmetrically.
Avoid right-angle turns or minimize the number of vias on the high speed traces because they usually cause
impedance discontinuity in the transmission lines and degrade the signal integrity.
Mismatch among impedances of PCB traces, connectors, or cables also caused reflection, limiting thebandwidth of the high-speed channels.
Using common-mode filter on differential traces is desirable to reduce EMI. Pay attention on data-rate
driven noise. For example, if data-rate is 1.5Gbps, common mode choke coil of 1.5GHz common mode
impedance is desired to be high, while 1.5GHz differential impedance is low.

PCB Cross-sectional Viewfor Microstrip Lines> 3 x S1

GND

S1

> 3 x S1

GND

Layer1: Signals
Layer2: Ground
Layer3: Power
Layer3: Signals

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THCV213_THCV214_Design Guide_Rev.1.11_E6) Notices and requests

Please kindly read, understand and accept this “Notices and Requests” before using this product.
For the Material:
1. The product specifications described in this material are subject to change without prior notice.
2. The circuit diagrams described in this material are examples of the application which may not always apply todesign of respective customers. THine Electronics, Inc. (“THine”) is not responsible for possible errors andomissions in this material. Please note if the errors or omissions should be found in this material, THine may
not be able to correct them immediately.
3. This material contains THine’s copyright, know-how or other proprietary. Copying or disclosing of thecontents of this material to any third party without THine’s prior permission is strictly prohibited.
For the Product:
1. This product is solely designed for evaluation purpose, and other purposes including mass production anddistribution are not intended.
2. This product has been solely manufactured for electric design engineers but not for end-users.
3. This product is not radiation-tolerant product.
4. This product is presumed to be used for general electric device, not for applications which require extremely
high-reliability/safety (including medical device concerned with critical care, aerospace device, or nuclear
power control device). Also, when using this product for any device concerned with control and/or safety oftransportation mean, traffic signal device, or other various types of safety device, such use must be after
applying appropriate measures to the product.
5. This product has been designed with the utmost care to accomplish the purpose of evaluation of IC products
manufactured by THine Electronics, Inc., however, THine MAKES NO WARRANTIES OR
REPRESENTATIONS WITH REGARD TO ANY PERFORMANCE OR FUNCTION OF THISPRODUCT IN ANY CIRCUMSTANCE.
6. This product has been manufactured with the utmost care in quality control and product reliability, however,there may be faults or defects with a low but fixed probability, as inevitable phenomenon concerned withsemiconductor manufacturing processes. Therefore, Customers are encouraged to have sufficiently redundantor error-preventive design applied to the use of the product so as not to have THine’s product cause anysocial or public damage. Replacement of the product is only available in case of obvious defects of mountdevices at the point of unpacking the product. Neither replacement nor failure analysis of the product isavailable in any other case of defects with the product and/or the product’s components.
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THine will be exempted from any responsibility unless it directly relates to the production process orfunctions of the product.
9. Developing, designing and manufacturing of Customers’ own products, equipments or system by using of thisproduct is strictly prohibited in any way.

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