REVISIONSLTR

DESCRIPTIONDATE (YR-MO-DA)

Update device supplier CAGE code 01295 information and boilerplateparagraphs to the current MIL-PRF-38535 requirements. – TTM

A

APPROVED
Muhammad A. Akbar

24-07-29

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PMIC N/A

PREPARED BY

REV STATUS

Muhammad Akbar

STANDARD
MICROCIRCUITDRAWINGCHECKED BY
Muhammad Akbar
APPROVED BY

THIS DRAWING IS AVAILABLEFOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSEAMSC N/A

DLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
https://www.dla.mil/landandmaritime

Thomas HessDRAWING APPROVAL DATE
19-07-16
REVISION LEVELAMICROCIRCUIT, BiCMOS, RADIATION
HARDENED, HIGH PERFORMANCE WIDEBANDSYNTHESIZER WITH PHASESYNCHRONIZATION, OUTPUT FREQUENCY
40 MHz TO 15 GHz, MONOLITHIC SILICONSIZECAGE CODE

A

67268
SHEET

DSCC FORM 2233
APR 97
DISTRIBUTION STATEMENT A. Approved for public release. Distribution is unlimited.

5962-17236
1 OF 235962-E430-24

1. SCOPE
1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device class Q) andspace application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or
Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN.
1.2 PIN. The PIN is as shown in the following example:

5962

R

17236

Federalstock classdesignator\

RHA
designator(see 1.2.1)

01

V

X

C

Devicetype(see 1.2.2)

Deviceclass
designator(see 1.2.3)

Case
outline(see 1.2.4)

Leadfinish(see 1.2.5)/\/
Drawing number

1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and aremarked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.
1.2.2 Device type(s). The device type(s) identify the circuit function as follows:
Device type

Generic number

01

Circuit function

LMX2615-SP

High performance wideband synthesizer withphase synchronization output frequency
40MHz to 15 GHz.

1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level asfollows:
Device class

Device requirements documentation

Q or V

Certification and qualification to MIL-PRF-38535

1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows:
Outline letter
X

Descriptive designator
See figure 1

Terminals

Package style64

Ceramic quad flat pack (CQFP) with
exposed pad

1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V.

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97

SIZE

5962-17236

A
REVISION LEVEL

A

SHEET

2

1.3 Absolute maximum ratings. 1/ 2/Power supply voltage (VCC) ....................................................................................... 3.6 V maximum
Digital pin voltage Supply (VDIG) (FS0-FS7,SYNC, SysRefReq, RECAL_EN,CAL) ... VCC +0.3 V maximum
Differential AC voltage between OSCinP and OSCinN |VOSCin| ............................... 2.1 Vpp
Maximum junction temperature (TJ) .......................................................................... -55C to 150C
Storage temperature range ....................................................................................... -65C to +150C
Electrostatic discharge (ESD) rating:
Human body model (HBM) .................................................................................... 1000 V 3/
Charge device model (CDM) ................................................................................. 250 V 4/
Thermal resistance, junction-to-ambient (RJA) .......................................................... 22.7C/W
Thermal resistance, junction-to-case, top (RJCtop) .................................................... 7.3C/W
Thermal resistance, junction-to-case, bottom (RJCbottom) ........................................... 1.0C/W
Thermal resistance, junction-to-board(RJB) ............................................................. 7.6C/W
Junction-to-top characterization parameter, (ψ JT) .................................................... 2.2C/W
Junction-to-board characterization parameter (ψ JB) ................................................. 7.4C/W
1.4 Recommended operating conditions.
Power supply voltage (VCC) ....................................................................................... +3.20 V to +3.45 V 2/ 3/
Case operating temperature range (TC) ..................................................................... -55C to +125C_________
1/
2/
3/

4/

5/

Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the
maximum levels may degrade performance and affect reliability.
Unless otherwise specified, all voltages are measured with respect to VCC = 0 V.
JEDEC document JEP155 states that ± 500 V HBM allows safe manufacturing with a standard ESD control process.
Manufacturing with less than ± 500 V HBM is possible with the necessary precautions. Pins listed as ±1000 V may
actually have higher performance.
JEDEC document JEP157 states that ± 250 V CDM allows safe manufacturing with a standard ESD control process.
Manufacturing with less than ± 250 V CDM is possible with the necessary precautions. Pins listed as ±250 V may actually
have higher performance.
For more information about traditional and new thermal metrics, see Texas Instruments IC Package Thermal Metrics
application report, SPRA953

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97

SIZE

5962-17236

A
REVISION LEVEL

A

SHEET

3

1.5 Radiation features.
Maximum total dose available (high dose rate = 50 – 300 rad(Si)/s) ............................ 100 krad(Si) 1/
Maximum total dose available (low dose rate = 10 mrad(Si)/s) ..................................... 100 krad(Si) 1/
Single event phenomenon (SEP):No Single event latchup (SEL) occurs at effective LET (see 4.4.4.3) ........................  120 MeV/(mg/cm2) 2/_________
1/ The manufacturer supplying device type 01 has performed characterization testing in accordance with MIL-STD-883
method 1019, and the parts exhibited no low dose rate sensitivity at a dose level of 100 krad(Si). The radiation end points
limits for the noted parameters are guaranteed only for the conditions as specified in MIL-STD-883, method 1019,
condition A and condition D to a maximum total dose of 100 krad(Si).
2/ Heavy ion single event effects(SEE) test was performed at the 88” Cyclotron Facility at Lawrence Berkeley National
Laboratory (LBNL) located in Berkeley, California with an ion beam energy 10 MeV/nucleon exposed inside a vacuum
chamber. No single event latch-up (SEL) was observed when Gold (Au) ions beam exposed with a fluence 1x107 ions/cm2
at an angle 45° with bias voltage 3.45 V and operating temperature 125°C corresponding to an effective LET of 120
MeV·cm2/mg. For more information on SEP test results, customers are requested to contact the manufacturer.

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97

SIZE

5962-17236

A
REVISION LEVEL

A

SHEET

4

2. APPLICABLE DOCUMENTS
2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a partof this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in thesolicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATIONMIL-PRF-38535 -- Integrated Circuits, Manufacturing, General Specification for.
DEPARTMENT OF DEFENSE STANDARDSMIL-STD-883 MIL-STD-1835 -Test Method Standard Microcircuits.
Interface Standard Electronic Component Case Outlines.

DEPARTMENT OF DEFENSE HANDBOOKSMIL-HDBK-103 MIL-HDBK-780 -List of Standard Microcircuit Drawings.
Standard Microcircuit Drawings.

(Copies of these documents are available online at https://quicksearch.dla.mil.)
2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein.
Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract.
ASTM INTERNATIONAL (ASTM)
ASTM F1192−

Standard Guide for the Measurement of Single Event Phenomena (SEP) Induced by Heavy Ion
Irradiation of semiconductor Devices.

(Copies of these documents are available online at https://www.astm.org.)JEDEC Solid State Technology Association
JEDEC JS-001
JEDEC PUB 95
JEDEC JEP 155
JEDEC JEP 157
JEDEC JEP 163

−
–
−
−
−

Human Body Model Testing of Integrated Circuits
Registered and Standard Outlines for Semiconductor Devices
Recommended ESD Target Levels for HBM/MM Qualification
Recommended ESD-CDM Target Levels
Selection of burn-in/life test conditions and critical parameters for QML microcircuits(Copies of these documents are available online at https://www.jedec.org/.)(Non-Government standards and other publications are normally available from the organizations that prepare or distribute thedocuments. These documents also may be available in or through libraries or other informational services.)
2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the textof this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a
specific exemption has been obtained.

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97

SIZE

5962-17236

A
REVISION LEVEL

A

SHEET

5

3. REQUIREMENTS
3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with
MIL-PRF-38535 as specified herein, or as modified in the device manufacturer's Quality Management (QM) plan. The
modification in the QM plan shall not affect the form, fit, or function as described herein.
3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified
in MIL-PRF-38535 and herein for device classes Q and V.
3.2.1 Case outline. The case outline shall be in accordance with 1.2.4 herein and figure 1.
3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2.
3.2.3 Block diagram. The block diagram shall be as specified on figure 3.
3.2.4 Timing diagrams. The timing diagrams shall be as specified on figure 4.
3.2.5 Radiation exposure circuit. The radiation exposure circuit shall be maintained by the manufacturer under document
revision level control and shall be made available to the preparing and acquiring activity upon request.
3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, theelectrical performance characteristics and postirradiation parameter limits are as specified in table IA and shall apply over thefull ambient operating temperature range.
3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electricaltests for each subgroup are defined in table IA.
3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also bemarked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer
has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still bemarked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535.
3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in
MIL-PRF-38535.
3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535
listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). The certificate of compliancesubmitted to DLA Land and Maritime-VA prior to listing as an approved source of supply for this drawing shall affirm that the
manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein.
3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 shallbe provided with each lot of microcircuits delivered to this drawing.

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97

SIZE

5962-17236

A
REVISION LEVEL

A

SHEET

6

TABLE IA. Electrical performance characteristics.
Test

SymbolConditions 1/ 2/ 7/-55C  Tc  +125C 6/
3.2V  Vcc  +3.45V
unless otherwise specified

Group A Device
subgroups
type

Limits

Unit

Min

Max

3.2

3.45

POWER SUPPLYPower supply voltage

Supply current

VCC

Icc

OUTA_PD = 0, OUTB_PD = 1
OUTA_MUX = OUTB_MUX = 1
OUTA_PWR = 31, CPG=7
fOSC= fPD = 100 MHz, fVCO =fOUT = 14.5 GHz

1,2,3

01

1,2,3

01

V

390
mA

RSET=1

310
1,2,3

01

Power down =1

8

DIGITAL INTERFACE (Applies to SCLK, SDI, CSB, CAL, RECAL_EN, MUXout, SYNC, SysRefReq)
High level output voltage

VOH

MUX out pin,
Load current = -5mA

1,2,3

01

Low level output voltage

VOL

MUX out pin,
Load current = 5mA

1,2,3

01

high level input voltage

VIH

1,2,3

01

Low level input voltage

VIL

1,2,3

01

High level input current

IIH

1,2,3

01

Low level input current

IIL

1,2,3

1,2,3

V

Vcc-0.6

V

0.5
1.6

V
0.4

V

-100

+100

A

01

-100

+100

A

01

5

1000

MHz

5

200

0.4

2

0.8

2

1.6

2

0.125

250

5

200

INPUT SIGNAL PATH
Input signal path:
Reference input frequency
Reference input voltage

fOSCinOSC_2X = 0
OSC_2X = 1

VOSCinSingle-ended
AC coupledsine wave
input withcomplementa
ry side AC
coupled to
ground with50 Ω resistor

fOSCin ≥ 20
MHz

1,2,3

01

10 MHz ≤fOSCin< 20 MHz
5 MHz ≤
fOSCin <10
MHz

Vpp

PHASE DETECTOR AND CHARGE PUMP
Phase detector frequency

fPD

MASH_ORDER=0

1,2,3

01

MASH_ORDER>0

MHz

See footnotes at end of table.

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97

SIZE

5962-17236

A
REVISION LEVEL

A

SHEET

7

TABLE IA. Electrical performance characteristics - continued.
Test

SymbolConditions 1/ 2/ 7/-55C  Tc  +125C 6/
3.2V  Vcc  +3.45V
unless otherwise specified

Group A
subgroups

Devicetype

Limits

Min

Unit

Max

Digital interface WRITE specifications
SPI write speed

fSPIWrite

9,10,1101

tCE

9,10,11

01

50

dBc

Data to clock setup timetCS

9,10,11

01

50

ns

Data to clock hold timetCH

9,10,11

01

50

ns

9,10,11

01

200

ns

Clock to enable low time

see figure 4

2

MHz

Clock pulse width hightCWH

Clock pulse width low

tCWL

9,10,11

01

200

ns

Enable to clock setup time

tCES

9,10,11

01

100

ns

Enable pulse width hightEWH

9,10,11

01

100

ns

Digital interface READBACK specifications
SPI Readback speed

9,10,11fSPIREADBack

01

2

MHz

tCE

9,10,11

01

50

dBc

Clock to data wait timetCS

9,10,11

01

50

ns

Clock pulse width hightCWH

9,10,11

01

200

ns

Clock pulse width low

tCWL

9,10,11

01

200

ns

Enable to clock setup time

tCES

9,10,11

01

50

ns

Enable pulse width hightEWH

9,10,11

01

100

ns

Falling clock edge to data wait timetCD

9,10,11

01

200

ns

Clock to enable low time

see figure 4

See footnotes at end of table.

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97

SIZE

5962-17236

A
REVISION LEVEL

A

SHEET

8

TABLE IA. Electrical performance characteristics – continued
Test

SymbolConditions 1/ 2/ 7/-55°C ≤ Tc ≤ +125°C 6/
3.2V ≤ Vcc ≤ 3.45V
unless otherwise specified

Group A
sub-groups

Devicetype

Typical
value
5/

Unit

Phase detector and charge pump

Effective charge pump current.
(Sum of the up and down
currents)

ICPOUT

CPG = 43

CPG =16

CPG = 5

1

01

mA

9

CPG = 312

CPG = 715

100 kHz-105

VCO Characteristics

VCO1
fVCO = 8.1 GHz

VCO2fVCO = 9.3 GHz

VCO3fVCO = 10.4 GHz
VCO phase noise

1 MHz

-127
4

01

10 MHz-148

100 MHz-155

100 kHz

-103

1 MHz

-125
4

01

10 MHz-146

100 MHz-153

100 kHz

-103

1 MHz

-125
4

01

10 MHz-147

100 MHz-158

100 kHz

-101

PNVCO

dBc/Hz
VCO4
fVCO = 11.4 GHz

VCO5fVCO = 12.5 GHz

VCO6fVCO = 13.6 GHz

1 MHz

-124
4

01

10 MHz-146

100 MHz-158

100 kHz

-102

1 MHz

-126
4

01

10 MHz-147

100 MHz-156

100 kHz

-101

1 MHz

-124
4

01

10 MHz-146

100 MHz-160

See footnotes at end of table.

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97

SIZE

5962-17236

A
REVISION LEVEL

A

SHEET

9

TABLE IA. Electrical performance characteristics – continued
Test

SymbolConditions 1/ 2/ 7/-55°C ≤ Tc ≤ +125°C 6/
3.2V ≤ Vcc ≤ 3.45V
unless otherwise specified

Group A
sub-groups

Devicetype

Typical value
5/

Unit

VCO Characteristics
100 kHzVCO phase noise

VCO calibration
speed,VCO gainPNVCO

tVCOCAL

KVCO

VCO7
fVCO = 14.7 GHz

-101

1 MHz

-124
4

01

dBc/Hz10 MHz-146

100 MHz-157

VCO calibration speed, switch
across the entire frequency
band, fOSC = 100 MHz, fPD =100 MHz, fVCO = 7.9
GHz,VCO_SEL=7

9

01

650

8.1 GHz94

9.3 GHz106

10.4 GHz122

11.4 GHz

4

01

µs

148

12.5 GHz185

13.6 GHz202

14.7 GHz

233

MHz/V

OUTPUT Characteristics
Output power(single ended) 3/ 4/

Pout50-Ω resistor pullup
OUTx_PWR = 31

fOUT = 8 GHz

4

01

6

fOUT = 15 GHz

4

01

4

dBm

1/ Devices supplied to this drawing have been characterized through all levels M, D, P, L, and R of irradiation. However, thisdevice radiation end point limits for the noted parameters are guaranteed only for the conditions as specified in MIL-STD883, method 1019, condition A and condition D. Pre and Post irradiation values are identical unless otherwise specified inTable IA. When performing post irradiation electrical measurements for any RHA level, TA = +25C (see 1.5 herein).
2/ Unless otherwise specified, 3.2V< Vcc < 3.45V
3/ Single ended output power obtained after de-embedding microstrip trace losses and matching with a manual tuner. Unused
port terminated to 50 Ω load.
4/ Output power, spurs, and harmonics can vary based on board layout and components. For lower VCO frequencies, the N
divider minimum value can limit the phase-detector frequency.
5/ Typical values at TA=+25C. Some parameters are tested in functional mode and may not be independently tested in
production. This parameter is for informational purpose only.
6/ Tc = TJ - (RJCtop) ( IccTotal) (Vcc). Case temperature Tc may be above TA.
For more information about traditional and new thermal metrics, see Texas Instruments IC Package Thermal Metrics
application report, SPRA953.

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97

SIZE

5962-17236

A
REVISION LEVEL

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10

TABLE IB. SEP test limits. 1/ 2/ 3/

Devicetype

SEP

Temperature

No Single event latch-up(SEL occurs at
effective Linear energy transfer (LET)01

No SEL125C

LET  120 MeV/(mg/cm2)

1/ For single event phenomena (SEP) test conditions, see 4.4.4.3 herein.
2/ Technology characterization and model verification supplemented by in-line data
may be used in lieu of end of line testing. Test plan must be approved by the technicalreview board and qualifying activity.
3/ Heavy ion single event effects(SEE) test was performed at the 88” Cyclotron Facility at Lawrence
Berkeley National Laboratory (LBNL) located in Berkeley, California with an ion beam energy 10
MeV/nucleon exposed inside a vacuum chamber. No single event latch-up (SEL) was observed whenGold (Au) ions beam exposed with a fluence 1x107 ions/cm2 at an angle 45° with bias voltage 3.45 V
and operating temperature 125°C corresponding to an effective LET of 120 MeV·cm2/mg. For more
information on SEP test results, customers are requested to contact the manufacturer.

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97

SIZE

5962-17236

A
REVISION LEVEL

A

SHEET

11

Case outline X(Bottom view)Notes: Package is hermitically sealed with a metal lid. Ground pad to be electrically connected to the heat sink and seal ring. All
leads are gold plated and can be solder dipped
FIGURE 1. Case outline X.

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97

SIZE

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A
REVISION LEVEL

A

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12

FIGURE 1. Case outline X (top view).- continued.

Dimensions

InchesSymbolMillimeters

Min

Max

Min

Max

A

0.39690.4031

10.08

10.24

B

0.41930.4390

10.65

11.15

0.0909C

2.31

NOTES:
1.

Controlling dimensions are millimeter, inch dimensions are given for reference only.

FIGURE 1. Case outline X - continued.

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97

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REVISION LEVEL

A

SHEET

13

NO.
1

PIN
NAME
NC

I/O

TYPE

—

—

2

NC

—

—

3
4

FS0
FS1

I
I

—
—

5

CAL

I

—

6
7
8
9
10
11

GND
VbiasVCO
GND
SYNC
GND
VccDIG

—
—
—
I
—
—

—
—
—
—
—
—

12

OSCinP

I—

13

OSCinM

I

—

14

—

—

15
16
17
18
19

VregI
N
FS2
FS3
FS4
FS5
FS6

I
I
I
I
I

—
—
—
—
—

20

FS7

I

—

21

VccC
P

—

—

22

CPout

O

—

23
24
25
26
27
28
29

GND
GND
VccMASHSCK
SDI
GND
RFoutBM

—
—
—
I
I
—
O

GroundGround———Ground—30

RFoutBP

O

—

31

GND

—

GroundDESCRIPTION
No connection. Pin may be grounded, connected to the supply rail or left
unconnected.
No connection. Pin may be grounded, connected to the supply rail or left
unconnected.
Parallel pin control. This is the LSB.
Parallel pin control
Chip enable. In Pin Mode (not SPI Mode), rising edges presented to this pin
activate the VCO calibration.
GroundVCO bias. Requires connecting 10uF capacitor to ground. Place close to pin.
GroundPhase synchronization input pin.
GroundDigital supply. Recommend connecting 0.1uF capacitor to ground.
Complimentary Reference input clock pins. High input impedance. Requires
connecting series capacitor (0.1 uF recommended).
Complimentary pin to OSCinP.
Input reference path regulator decoupling. Requires connecting 1uF
capacitor to ground. Place close to pin.
Parallel pin control
Parallel pin control
Parallel pin control
Parallel pin control
Parallel pin control
Parallel pin control. This is the MSB. Controls output state in pin mode.
When this pin is low, only RFoutA is active, otherwise both outputs areactive.
Charge pump supply. Recommend connecting 0.1uF capacitor to ground.
Charge pump output. Recommend connecting C1 of loop filter close to
charge pump pin.
GroundGroundDigital supply. Recommend connecting 0.1uF and 10uF capacitor to ground.
SPI input clock. High impedance CMOS input. 1.8 – 3.3V logic.
SPI input data. High impedance CMOS input. 1.8 – 3.3V logic.
GroundComplementary pin for RFoutBP
Differential output B Pair. Requires connecting a 50-Ω resistor pull-up to Vcc
as close as possible to pin. Can be used as a synthesizer output or SYSREF
output.
GroundFIGURE 2. Terminal connections.

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97

SIZE

5962-17236

A
REVISION LEVEL

A

SHEET

14

PIN
I/O

TYPE

DESCRIPTIONMUXout

O

—

33

NC

—

—

34
35
36

VccBUF
GND
RFoutAM——O—
Ground—37

RFoutAP

O

—

38
39
40
41
42
43
44
45
46

GND
CSB
GND
VccVCO2
VbiasVCO2
SysRefReq
VrefVCO2
RECAL_EN
NC

—
I
—
—
—
I
—
I
—

Ground—Ground
—
—
—
—
—
—

47

NC

—

—

48

NC

—

—

49

NC

—

—

50

NC

—

—

51
52

GND
NC

—
—

Ground
—

53
54
55
56
57
58

VbiasVARAC
GND
Vtune
VrefVCOVccVCO
NC

—
—
I
—
—
—

—
Ground
—
—
—
—

59
60
61
62

VregVCO
GND
GND
NC

—
—
—
—

—
GroundGround
—

63

NC

—

—

Multiplexed output pin. Can output: lock detect, SPI readback anddiagnostics.
No connection. Pin may be grounded, connected to the supply rail or left
unconnected.
Output buffer supply. Requires connecting 0.1uF capacitor to ground.
GroundComplementary pin for RFoutAP
Differential output B Pair. Requires connecting a 50-Ω resistor pull-up to
Vcc as close as possible to pin.
GroundSPI chip select bar. High impedance CMOS input. 1.8 – 3.3V logic.
GroundVCO supply. Recommend connecting 0.1uF and 10uF capacitor to ground.
VCO bias. Requires connecting 1uF capacitor to ground.
SYSREF request input for JESD204B support.
VCO supply reference. Requires connecting 10uF capacitor to ground.
Enables the automatic recalibration feature.
No connection. Pin may be grounded, connected to the supply rail or left
unconnected.
No connection. Pin may be grounded, connected to the supply rail or left
unconnected.
No connection. Pin may be grounded, connected to the supply rail or left
unconnected.
No connection. Pin may be grounded, connected to the supply rail or left
unconnected.
No connection. Pin may be grounded, connected to the supply rail or left
unconnected.
GroundNo connection. Pin may be grounded, connected to the supply rail or left
unconnected.
VCO Varactor bias. Requires connecting 10uF capacitor to ground.
GroundVCO tuning voltage input.
VCO supply reference. Requires connecting 10uF capacitor to ground.
VCO supply. Recommend connecting 0.1uF and 10uF capacitor to ground.
No connection. Pin may be grounded, connected to the supply rail or left
unconnected.
VCO regulator node. Requires connecting 1uF capacitor to ground.
GroundGroundNo connection. Pin may be grounded, connected to the supply rail or left
unconnected.
No connection. Pin may be grounded, connected to the supply rail or left
unconnected.

64

NC

—

—

NO.

NAME

32

No connection. Pin may be grounded, connected to the supply rail or left unconnected.

Notes:
1/ NC = No connection. Pin may be grounded, connected to the supply rail or left unconnected.
2/ I = input, O = output, P = power, D = digital, A = analog, PU = pull up with an internal resistor, and
PD = pull down with internal resistor
FIGURE 2. Terminal connections.- continued.

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
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REVISION LEVEL

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FIGURE 3. Block diagram.

STANDARD
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Notes: There are several other considerations for writing on the SPI:

1. The R/W bit must be set to 0.
2. The data on SDI pin is clocked into a shift register on each rising edge on the SCK pin.
3. The CSB must be held low for data to be clocked. Device will ignore clock pulses if CSB is heldhigh.
4. The CSB transition from high to low must occur when SCK is low.
5. When SCK and SDI lines are shared between devices, TI recommends hold the CSB line high on
the device that is not to be clocked.

FIGURE 4. Serial data input timing diagram

Notes: There are several other considerations for SPI readback:1. The R/W bit must be set to 1.
2. The MUXout pin will always be low for the address portion of the transaction.
3. The data on MUXout becomes available momentarily after the falling edge of SCK and therefore
should be read back on the rising edge of SCK.
4. The data portion of the transition on the SDI line is always ignored.

FIGURE 4. Serial data readback timing diagram – continued.

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
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REVISION LEVEL

A

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4. VERIFICATION
4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with
MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan
shall not affect the form, fit, or function as described herein.
4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted
on all devices prior to qualification and technology conformance inspection.
4.2.1 Additional criteria for device classes Q and V.
a.

The burn-in test shall be performed in accordance with method 1015 of MIL-STD-883. Burn-in test duration, test
condition and test temperature, or approved alternatives shall be specified in the device manufacturer's QM plan inaccordance with MIL-PRF-38535 and JEDEC JEP163. The burn-in test circuit shall be maintained under document
revision level control of the device manufacturer's Technology Review Board (TRB) in accordance with MIL-PRF38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the
inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of
MIL-STD-883.

b.

Interim and final electrical test parameters shall be as specified in table IIA herein.

c.

Additional screening for device class V beyond the requirements of device class Q shall be as specified in
MIL-PRF-38535, appendix B.

d.

Unless otherwise specified in the QM plan, for devices class Q and V dynamic burn-in shall be performed with test
condition D, method 1015 of MIL-STD-883.

e.

For devices class V , interim and post burn-in final electrical test delta parameters shall be specified in delta burn-intable IIB herein.

4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be inaccordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for groups
A, B, C, D, and E inspections (see 4.4.1 through 4.4.4).
4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with
MIL-PRF-38535 including groups A, B, C, D, and E inspections, and as specified herein (see 4.4.1 through 4.4.4).
4.4.1 Group A inspection.
a.

Tests shall be as specified in table IIA herein.

b.

For device classes Q and V, subgroups 7 and 8 shall include verifying the functionality of the device.

c.

CIN , COUT , CON , COFF1 , and COFF2 shall be measured in accordance with MIL-STD-883, M3012 and only for the initialtest and after process or design changes which may affect capacitance. CIN shall be measured between thedesignated terminal and VSS at a frequency of 1 MHz. For CIN and COUT, test all pins on one device and then test four
additional devices on worst case pin for each I/O type.

4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table IIA herein.
4.4.2.1 Additional criteria for device classes Q and V. The steady-state life test duration, test condition and test temperature,
or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The
test circuit shall be maintained under document revision level control by the device manufacturer's TRB in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the
inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of
MIL-STD-883.
4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table IIA herein.

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
DSCC FORM 2234
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REVISION LEVEL

A

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18

TABLE IIA. Electrical test requirements.
Test requirements

Subgroups(in accordance with
MIL-PRF-38535, table III)
Deviceclass Q

Deviceclass VInterim electricalparameters (see 4.2)

1, 4, 7, 9

1, 4, 7, 9Final electricalparameters (see 4.2)

1, 2, 3, 4, 1/
5, 6, 7, 8, 9, 10,11

1, 2, 3, 1/ 2/
4, 5, 6, 7, 8, 9, 10,11

Group A test
requirements (see 4.4)

1, 2, 3, 4, 5, 6, 7, 8, 9,
10, 11

1, 2, 3, 4, 5, 6, 7, 8, 9,
10,11 1/ 2/Group C end-point electricalparameters (see 4.4)

1, 2, 3, 4, 5, 6, 7, 8, 9,
10, 11

1, 2, 3, 4, 5, 6, 7, 8, 9,
10, 11

Group D end-point electricalparameters (see 4.4)

1, 2, 3, 4, 5, 6, 7, 8, 9,
10, 11

1, 2, 3, 4, 5, 6, 7, 8, 9,
10, 11

Group E end-point electricalparameters (see 4.4)

1, 4, 7, 9

1, 4, 7, 9

1/ PDA applies to subgroup 1 (see 4.2). For device class V, PDA applies to subgroups 1 and 7 (see 4.2).
2/ The burn-in shall meet the requirements of 4.2.1a herein.
3/ On all class V lots, the device manufacturer shall maintain read-and-record data (as a minimum on disk) forburn-in electrical parameters (group A, subgroup 1), in accordance with MIL-PRF-38535. For pre-burn-in andinterim electrical parameters, the read-and-record requirements are for delta measurements only.
4/ Dynamic burn-in test shall be performed per TM 1015 with test condition D (see MIL-PRF-38535 and
JEDEC JEP163).
5/ Delta limits shall be required only on table IA, subgroup 1. The delta values shall be computed withreference to the previous interim electrical parameters. The delta limits are specified in table IIB.

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
DSCC FORM 2234
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REVISION LEVEL

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TABLE IIB. Burn-in and operating life test delta parameters (+25C).

#

PARAMETERTEST CONDITIONSOUTA_PD = 0, OUTB_PD = 1 OUTA_MUX =OUTB_MUX = 1 OUTA_PWR = 31, CPG = 7
fOSC = fPD = 100 MHz, fVCO = fOUT = 14.5
GHz

1

Icc

Supply current

2

Icc

Power down current

3

VOH

high-level output

MUXout pin, load = -5 mA

4VOLhigh-level output

MUXout pin, load = 5 mA

56

POWERDOWN = 1, CE-HI/R0[0]=1

SCK
ViH

high-level input

SDI

7

CSB

8

SCK

9

ViL

Low-level input

SDI

MIN

MAX

UNIT

-15

15

mA

-1
0.03
0.03
0.02
0.02
0.02
0.01
0.01
0.01

1

mA

0.025

V

0.025

V

0.015

V

0.015

V

0.015

V

0.01

V

0.01

V

0.01

V

10

CSB

11

SCK

-1

1

uA

SDI

-1

1

uA

13

CSB

-1

1

uA

11

SCK

-0.1

0.1

uA

SDI

-0.1

0.1

uA

CSB

-0.1

0.1

uA

50 ohm pull up, FVCO 8.1GHz, OUTx_PWR =31,CHAN DIV =4
50 ohm pull up, FVCO 9.3GHz, OUTx_PWR =31,CHAN DIV =4
50 ohm pull up, FVCO 10.4GHz, OUTx_PWR =31,CHAN DIV =4
50 ohm pull up, FVCO 11.4GHz, OUTx_PWR =31,CHAN DIV =4
50 ohm pull up, FVCO 12.5GHz, OUTx_PWR =31,CHAN DIV =4
50 ohm pull up, FVCO 13.6GHz, OUTx_PWR =31,CHAN DIV =4
50 ohm pull up, FVCO 14.7GHz, OUTx_PWR =31,CHAN DIV =4

0.25
0.25
0.25
0.25
0.25
0.25
0.25

0.25

dBm

0.25

dBm

0.25

dBm

0.25

dBm

0.25

dBm

0.25

dBm

0.25

dBm

12

12

IiH

IiL

high-level input

Low-level input

13
14

Pout

15

Pout

16

Pout

17

Pout

18

Pout

19

Pout

20

Pout

Single-ended output power
RFoutA
Single-ended output power
RFoutA
Single-ended output power
RFoutA
Single-ended output power
RFoutA
Single-ended output power
RFoutA
Single-ended output power
RFoutA
Single-ended output power
RFoutA

1/ The above parameter shall be recorded before and after the required burn-in and life tests to determine thedelta () burn-in electrical limit.

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
DSCC FORM 2234
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5962-17236

A
REVISION LEVEL

A

SHEET

20

4.4.4 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness assured(see 3.5 herein).
a.

End-point electrical parameters shall be as specified in table IIA herein.

b.

For device classes Q and V, the devices or test vehicle shall be subjected to radiation hardness assured tests as
specified in MIL-PRF-38535 for the RHA level being tested. All device classes must meet the post irradiation end-point
electrical parameter limits as defined in table IA at TA = +25C 5C, after exposure, to the subgroups specified in table
II herein.

4.4.4.1 Total dose irradiation testing. Total dose irradiation testing shall be performed in accordance with MIL-STD-883 method
1019, condition A and condition D, and as specified herein.
4.4.4.1.1 Accelerated aging test. Accelerated aging tests shall be performed on all devices requiring a RHA level greaterthan 5 krad(Si). The post-anneal end-point electrical parameter limits shall be as specified in table IA herein and shall be thepre-irradiation end-point electrical parameter limit at 25C 5C. Testing shall be performed at initial qualification and after any
design or process changes which may affect the RHA response of the device.
4.4.4.2 Neutron irradiation. When specified in the purchase order or contract, Neutron irradiation test shall be conducted byusing a neutron fluence of approximately 1 x 1014 neutrons/cm2.
4.4.4.3 Single event phenomena (SEP). When specified in the purchase order or contract, SEP testing shall be performed onclass V devices. SEP testing shall be performed on the Standard Evaluation Circuit (SEC) or alternate SEP test vehicle asapproved by the qualifying activity at initial qualification and after any design or process changes which may affect the upset or
latch-up characteristics. Test four devices with zero failures. ASTM F1192 or JESD57 may be used as a guideline when
performing SEP testing. The test conditions for SEP are as follows:a.

The ion beam angle of incidence shall be between normal to the die surface and 60 to the normal, inclusive(i.e. 0  angle  60). No shadowing of the ion beam due to fixturing or package related affects is allowed.

b.

The fluence shall be  100 errors or  107 ions/cm2.

c.

The flux shall be between 102 and 105 ions/cm2/s. The cross-section shall be verified to be flux independent bymeasuring the cross-section at two flux rates which differ by at least an order of magnitude.

d.

The particle range shall be  20 micron in silicon.

e.

The test temperature shall be the maximum rated operating temperature 25C ±10°C for the latch-up measurements.

f.

Bias conditions shall be defined by the manufacturer for the latch-up measurements.

g.

For SEP test limits, see table IB herein.

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5. PACKAGING
5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device classes
Q and V.
6. NOTES
6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications(original equipment), design applications, and logistics purposes.
6.1.1 General applications: The manufacturer is supplying this SMD device as a high-performance wideband phase lockloop(PLL) with integrated voltage controlled oscillator(VCO) and voltage regulators that can lead output frequency from 40 MHz
to 15 GHz without doubler, which eliminates ½ harmonic filters. The VCO on this device covers an entire octave, so thefrequency coverage complete down to 40 MHz. The high performance PLL with figure of merit of -236dBc/Hz and high phasedetector frequency can attain very low in-band noise and integrated jitter.
This device can be used in many applications/systems but general applications are for Space communications application likeSpace Radar system, phase array antenna and beam forming and high speed data converter clocking system.
6.1.2 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor
prepared specification or drawing.
6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record forthe individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal, or emailcommunication.
6.3 Record of users. Military and industrial users should inform DLA Land and Maritime when a system application requires
configuration control and which SMD's are applicable to that system. DLA Land and Maritime will maintain a record of users andthis list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronic
devices (FSC 5962) should contact DLA Land and Maritime-VA, telephone (614) 692-8108.
6.4 Comments. Comments on this drawing should be directed to DLA Land and Maritime-VA, Columbus, Ohio 43218-3990,
or telephone (614) 692-0591.
6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in
MIL-PRF-38535 and MIL-HDBK-1331.
6.6 Sources of supply.
6.6.1 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in
MIL-HDBK-103 and QML-38535. The vendors listed in MIL-HDBK-103 and QML-38535 have submitted a certificate ofcompliance (see 3.6 herein) to DLA Land and Maritime-VA and have agreed to this drawing.
6.7 Additional information. When applicable, a copy of the following additional data shall be maintained and available fromthe device manufacturer:
a. RHA test conditions of SEP.
b. Number of latchup (SEL).

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MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
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REVISION LEVEL

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STANDARD MICROCIRCUIT DRAWING BULLETIN
DATE: 24-07-29
Approved sources of supply for SMD 5962-17236 are listed below for immediate acquisition information only andshall be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will berevised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and acertificate of compliance has been submitted to and accepted by DLA Land and Maritime-VA. This information
bulletin is superseded by the next dated revision of MIL-HDBK-103 and QML-38535. DLA Land and Maritime
maintains an online database of all current sources of supply at https://landandmaritimeapps.dla.mil/programs/smcr/.

Standard
microcircuit drawing
PIN 1/

VendorCAGE
numberVendorsimilar
PIN 2/

5962R1723601VXC

01295

LMX2615WRQMLV

1/ The lead finish shown for each PIN representing
a hermetic package is the most readily available
from the manufacturer listed for that part. If thedesired lead finish is not listed contact the vendor
to determine its availability.
2/ Caution. Do not use this number for item
acquisition. Items acquired to this number may notsatisfy the performance requirements of this drawing.

Vendor CAGE
number01295

Vendor nameand address
Texas Instruments, Inc.
12500 TI Blvd
Dallas, TX 75243

The information contained herein is disseminated for convenience only and theGovernment assumes no liability whatsoever for any inaccuracies in theinformation bulletin.