THC63LVDF84C_Rev.1.21_E

THC63LVDF84C
24bit Color LVDS Receiver (Falling Edge Strobe Output)
General DescriptionFeatures

The THC63LVDF84C receiver supports wide
temperature range as -40 to +85C, and wide
frequency range as 8 to 112MHz.
The THC63LVDF84C converts the four LVDS data
streams back into 24bits of LVCMOS data withfalling edge clock. At a transmit clock frequency of112MHz, 24bits of RGB data and 4bits of timing andcontrol data (HSYNC, VSYNC, DE, etc.) aretransmitted at an effective rate of 3.1Gbps.

･1:7 LVDS to LVCMOS Deserializer･Operating Temperature Range : -40 to +85C･No Special Start-up Sequence Required･Spread Spectrum Clocking Tolerant up to 100kHz
Frequency Modulation and +/-2.5% Deviations･Pixel Clock Range: 8 to 112MHz･56pin TSSOP Package･Power Down Mode･Falling Edge Strobe Output･EU RoHS Compliant

Application･Medium and Small Size Panel･Security Camera･Multi Function Printer･Machine Vision (Frame Grabber Board)･Medical Equipment Monitor

Recommended LVDS Transmitter ICs･THC63LVDM83D･THC63LVDM87

LVDS to LVCMOS
1:7 Deserializer

Block Diagram

Figure 1. Block Diagram

Copyright©2023 THine Electronics, Inc.

1

THine Electronics, Inc.
SC: E

THC63LVDF84C_Rev.1.21_E

Pin Diagram

Figure 2. Pin Diagram

Pin Description
Pin Name
RA+, RARB+, RBRC+, RCRD+, RD-

Pin #10, 912, 1116, 15
20, 19Direction

Description
LVDS Data Inputs

Input
RCLK+,RCLK-18, 17

RA0 ~ RA6
RB0 ~ RB6
RC0 ~ RC6
RD0 ~ RD6
CLKOUT27, 29, 30, 32, 33, 35, 37
38, 39, 43, 45, 46, 47, 51
53, 54, 55, 1, 3, 5, 67, 34, 41, 42, 49, 50, 2
26

Output

/PDWN

25

Input

VCC31, 40, 48, 56

GND

4, 28, 36, 44, 52

LVDS VCC
LVDS GND
PLL VCC
PLL GND

138, 14, 21
2322, 24

Copyright©2023 THine Electronics, Inc.

Type

LVDS
LVDS Clock Inputs

Pixel Data Outputs
LVCMOS-Power

2

Pixel Clock Output
H : Normal Operation
L : Power Down (All outputs are pulled toground)Power Supply Pins for LVCMOS outputs
and digital circuitry
Ground Pins for LVCMOS outputs anddigital circuitry
Power Supply Pins for LVDS inputs
Ground Pins for LVDS inputs
Power Supply Pins for PLL circuitry
Ground Pins for PLL circuitry

THine Electronics, Inc.
SC: E

THC63LVDF84C_Rev.1.21_E

Absolute Maximum Ratings
Parameter
Supply Voltage (VCC, LVDS VCC, PLL VCC)
LVCMOS Input Voltage
LVCMOS Output Voltage
LVDS Input Pin
Junction Temperature
Storage Temperature
Reflow Peak Temperature
Reflow Peak Temperature Time
Maximum Power Dissipation @+25CMin
-0.3
-0.3
-0.3
-0.3
-55-Max+4.0
VCC + 0.3
VCC + 0.3
VCC + 0.3
+125+150+260
101.9

Unit
VVVV
C
C
CsecW

Max3.6+85112Unit
VCMHzRecommended Operating Conditions
Symbol
VCC33TaPCLKParameter
All Supply Voltage(VCC, LVDS VCC, PLL VCC)
Operating Ambient Temperature
RCLK and CLKOUT Clock Frequency

Min
3.0-40
8Typ+25-“Absolute Maximum Ratings” are those values beyond which the safety of the device can not be guaranteed. They
are not meant to imply that the device should be operated at these limits. The tables of “Electrical Characteristics
Table4, 5, 6, 7” specify conditions for device operation.
“Absolute Maximum Rating” value also includes behavior of overshooting and undershooting.

Copyright©2023 THine Electronics, Inc.

3

THine Electronics, Inc.
SC: E

THC63LVDF84C_Rev.1.21_E

Equivalent LVDS Input Schematic Diagram
OutputControl

LVDS VCC

LVDS VCC

CMP

LVDS VCC

LVDS +AMP
LVDS -Figure 3. LVDS Input Schematic Diagram

Output Control/PDWN
HH
HL

Copyright©2023 THine Electronics, Inc.

RCLK +/- Input
Valid Clock
Invalid ClockOpen or Hi-z
Don’t Care

LVCMOS Output
Active Clock & Data
Unfixed Clock & Data
All Low
All Low4

THine Electronics, Inc.
SC: E

THC63LVDF84C_Rev.1.21_E

Power Consumption
Over recommended operating supply and temperature range unless otherwise specifiedSymbol

Parameter

IRCCG

LVDS Receiver Operating Current
Gray Scale Pattern 16 (Fig.4)

IRCCW

IRCCS

LVDS Receiver Operating Current
Worst Case Pattern(Fig.5)
LVDS ReceiverPower Down Current

Conditions
CL=8pF, PCLK=65MHz,
VCC33=3.3V
CL=8pF, PCLK=112MHz,
VCC33=3.3V
CL=8pF, PCLK=65MHz,
VCC33=3.3V
CL=8pF, PCLK=112MHz,
VCC33=3.3V

Typ*Max

Unit

5570mA

90110mA

90110mA

130160mA/PDWN=L-500µA*Typ values are at the conditions of Ta = +25ºC

16 Grayscale PatternFigure 4. 16 Grayscale Pattern

Worst Case PatternFigure 5. Worst Case Pattern

Copyright©2023 THine Electronics, Inc.

5THine Electronics, Inc.
SC: E

THC63LVDF84C_Rev.1.21_E

Electrical Characteristics
LVDS Receiver DC Specifications
Over recommended operating supply and temperature range unless otherwise specified
SymbolVTH
VTLIIN

Parameter
Differential Input High
Threshold
Differential Input Low
ThresholdConditions

Typ*Max

Unit--100mV-100--mV--

30

A

RL=100Ω, VIC=+1.2V
VIN=+2.4 / 0VLVDS VCC=3.6V

Input Current

Min

LVCMOS DC Specifications
Over recommended operating supply and temperature range unless otherwise specifiedSymbol
VIH
VILParameter
High Level Input Voltage
Low Level Input Voltage

VOH

High Level Output Voltage

VOL

Low Level Output Voltage

IIN

Input Current

Conditions
IOH=-4mA (Data)
IOH=-8mA (Clock)
IOL=4mA (Data)
IOL=8mA (Clock)
GND  VIN  VCC

Min
2.0
GND

Typ-Max
VCC
0.8

Unit
VV

2.4--V--0.4V--

10

A

LVCMOS Output Load Limitation
The output load is limited so that the junction temperature does not exceed 125C.

Figure 6. LVCMOS Output Load Limitation

Copyright©2023 THine Electronics, Inc.

6THine Electronics, Inc.
SC: E

THC63LVDF84C_Rev.1.21_E

Switching Characteristics
Over recommended operating supply and temperature range unless otherwise specified
Symbol
tRCP
tRCH
tRCL
tRCD
tRS
tRH
tTLH
tTHL
tSK
tRIP1tRIP0tRIP6tRIP5tRIP4tRIP3tRIP2tRPLL

Parameter
RCLK and CLKOUT Transition Time
LVCMOS CLKOUT High Time
LVCMOS CLKOUT Low TimeRCLK IN to CLKOUT Delay
LVCMOS Data Setup to CLKOUT
LVCMOS Data Hold from CLKOUT
LVCMOS Low to High Transition Time
LVCMOS High to Low Transition Time
PCLK=65MHz
LVDS Receiver Skew Margin
PCLK=112MHz
LVDS Input Data Position0
LVDS Input Data Position1
LVDS Input Data Position2
LVDS Input Data Position3
LVDS Input Data Position4
LVDS Input Data Position5
LVDS Input Data Position6
Phase Lock Loop Set

Min
8.92
0.35×T - 0.3
0.45×T - 1.6
-0.55
-0.25
- tSK
T/7- tSK
2T/7- tSK
3T/7- tSK
4T/7- tSK
5T/7- tSK
6T/7- tSK-

Typ*T
T/2
T/2
(3/14+3)×T
0.7
0.7
0.0
T/7
2T/7
3T/7
4T/7
5T/7
6T/7-Max
125
1.0
1.0
0.55
0.25+ tSK
T/7+ tSK
2T/7+ tSK
3T/7+ tSK
4T/7+ tSK
5T/7+ tSK
6T/7+ tSK
10.0

Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms

*Typ values are at the conditions of VCC33=3.3V and Ta = +25ºC

Copyright©2023 THine Electronics, Inc.

7

THine Electronics, Inc.
SC: E

THC63LVDF84C_Rev.1.21_E

AC Timing Diagrams
LVDS Input

Figure 7. LVDS Input Data Position

LVCMOS Output

Figure 8. LVCMOS Output Load and Transition TimeFigure 9. LVCMOS Output Setup and Hold Time

Copyright©2023 THine Electronics, Inc.

8

THine Electronics, Inc.
SC: E

THC63LVDF84C_Rev.1.21_E

Input to Output Delay
Note:Vdiff=(RCLK+)-(RCLK-)

Vdiff = 0V

RCLK+tRCD

VCC/2

CLKOUT

Figure 10.Input Clock to Output Clock Delay Time

Phase Lock Loop Set Time

Figure 11. PLL Lock Loop Set Time

Copyright©2023 THine Electronics, Inc.

9

THine Electronics, Inc.
SC: E

THC63LVDF84C_Rev.1.21_E

Application note
Display Data Mapping Example
JEIDA format
Transmitter VESA format
Pin6bit(18bpp) 8bit(24bpp) 6bit(18bpp) 8bit(24bpp)
TA0
R0R0R2R2TA1
R1
R1
R3R3TA2
R2
R2R4R4TA3R3
R3R5R5TA4R4R4R6R6TA5R5R5R7
R7
TA6G0
G0
G2G2
TB0
G1
G1
G3G3
TB1
G2G2
G4G4
TB2
G3G3G5G5TB3
G4G4G6G6TB4G5G5G7G7TB5
B0B0B2B2TB6B1B1B3B3TC0
B2B2B4B4TC1
B3
B3
B5
B5
TC2
B4
B4B6
B6TC3
B5B5B7
B7TC4Hsync
Hsync
Hsync
Hsync
TC5Vsync
Vsync
Vsync
Vsync
TC6DEDEDEDE
TD0
R6R0
TD1
R7
R1
TD2
G6G0
TD3
G7
G1
TD4
B6
B0
TD5
B7
B1
TD6
N/A
N/A
Note : Use TA to TC channels and open TD channel for 6bit application.

Copyright©2023 THine Electronics, Inc.

10

Receiver
Pin
RA0
RA1
RA2
RA3
RA4
RA5
RA6
RB0
RB1
RB2
RB3
RB4
RB5
RB6
RC0
RC1
RC2
RC3
RC4
RC5
RC6RD0RD1
RD2
RD3
RD4RD5RD6THine Electronics, Inc.
SC: E

THC63LVDF84C_Rev.1.21_E

System Connection Example
VCC33

PCB(Transmitter)

PCB(Receiver)

VCC33Ferrite BeadFerrite BeadFerrite BeadFerrite Bead

THC63LVDM83D

THC63LVDF(R)84C
0.01uF

VCC

0.1uF 0.01uF

LVDS VCC

LVDS VCC
0.01uF

0.1uF

0.1uF

0.01uFGND

GND
LVDS GND

CLKIN
R2
R3
R4R5
R6R7
G2
G3G4G5G6G7B2B3B4B5B6B7
HSYNC
VSYNC
DE
R0R1G0G1B0B1CLKIN
TA0TA1TA2TA3TA4TA5TA6TB0TB1
TB2
TB3
TB4
TB5
TB6
TC0
TC1
TC2
TC3
TC4
TC5
TC6
TD0
TD1
TD2
TD3
TD4
TD5
TD60.1uF

VCC

LVDS GND

PLL VCCPLL VCC
0.01uF

0.1uF

0.1uF

0.01uF

PLL GNDPLL GND

TA-

RA100ohm

TA+

RA+

TB-

RB100ohm

TB+

RB+

TC-

RC100ohm

TC+

RC+

TCLK-

CLKOUT
RA0
RA1
RA2
RA3
RA4
RA5
RA6
RB0
RB1
RB2
RB3
RB4
RB5
RB6
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RD0
RD1
RD2
RD3
RD4
RD5
RD6

CLKOUT
R2
R3
R4
R5
R6
R7
G2
G3
G4G5
G6
G7
B2
B3B4B5B6B7
HSYNC
VSYNC
DER0R1
G0G1
B0
B1OPENRCLK100ohm

TCLK+
/PDWN

RCLK+

/PDWN

/PDWN
TD-

VCC33/PDWN

RD100ohm

TD+RD+

RS

100ohm pair Cable
orPCB trace

R/F

GND

GND

Figure 12. Connection Example with JEIDA Format

Copyright©2023 THine Electronics, Inc.

11

THine Electronics, Inc.
SC: E

THC63LVDF84C_Rev.1.21_E

Notes
1) Cable Connection and Disconnection
Do not connect and disconnect the LVDS cable, when the power is supplied to the system.

2) GND Connection
Connect each GND of the PCB which LVDS-Tx and THC63LVDF84C on it.
to place GND cable as close to LVDS cable as possible.

It is better for EMI reduction3) Multi Drop Connection
Multi drop connection is not recommended.

Figure 13. Multi Drop Connection4) Asynchronous use
Asynchronous using such as following systems is not recommended.

Figure 14. Asynchronous Use

Copyright©2023 THine Electronics, Inc.

12

THine Electronics, Inc.
SC: E

THC63LVDF84C_Rev.1.21_E

Package

Figure 15. Package Diagram

Copyright©2023 THine Electronics, Inc.

13

THine Electronics, Inc.
SC: E

THC63LVDF84C_Rev.1.21_EReference Land PatternFigure 16. Reference of Land Pattern
The recommendation mounting method of THine device is reflow soldering.
The reference pattern is using the calculation result on condition of reflow soldering.

Notes
This land pattern design is a calculated value based on JEITA ET-7501.
Please take into consideration in an actual substrate design about enough the ease of mounting, the intensity ofconnection, the density of mounting, and the solder paste used, etc… The optimal land pattern size changes
with these parameters. Please use the value shown by the land pattern as reference data.

Copyright©2023 THine Electronics, Inc.

14

THine Electronics, Inc.
SC: E

THC63LVDF84C_Rev.1.21_E

Notices and Requests
1.

The product specifications described in this material are subject to change without prior notice.

2.

The circuit diagrams described in this material are examples of the application which may not always apply to the customer’s
design. THine Electronics, Inc. (“THine”) is not responsible for possible errors and omissions in this material. Please noteeven if errors or omissions should be found in this material, THine may not be able to correct them immediately.

3.

This material contains THine’s copyright, know-how or other intellectual property rights. Copying, reverse-engineer ordisclosing to third parties the contents of this material without THine’s prior written permission is prohibited.

4.

THINE ACCEPTS NO LIABILITY FOR ANY DAMAGE OR LOSS IN CONNECTION WITH ANY DISPUTERELATING TO INTELLECTUAL PROPERTY RIGHTS BETWEEN THE USER AND ANY THIRD PARTY, ARISINGOUT OF THIS PRODUCT, EXCEPT FOR SUCH DAMAGE OR LOSS IN CONNECTION WITH DISPUTESSUCCESSFULLY PROVED BY THE USER THAT SUCH DISPUTES ARE DUE SOLELY TO THINE. NOTE,HOWEVER, EVEN IN THE AFOREMENTIONED CASE, THINE ACCEPTS NO LIABILITY FOR SUCH DAMAGE OR
LOSS IF THE DISPUTE IS CAUSED BY THE USER’S INSTRUCTION.

5.

This product is not designed for applications that require extremely high-reliability/safety such as aerospace device, nuclearpower control device, or medical device related to critical care, excluding when this product is specified for automotive use byTHine and used it for that purpose. THine accepts no liability whatsoever for any damages, claims or losses arising out of theuses set forth above.

6.

Despite our utmost efforts to improve the quality and reliability of the product, faults will occur with a certain small
probability, which is inevitable to a semi-conductor product. Therefore, you are encouraged to have sufficiently fail-safe
design principles such as redundant or error preventive design applied to the use of the product so as not to have our productcause any social or public damage.

7.

This product may be permanently damaged and suffer from performance degradation or loss of mechanical functionality ifsubjected to electrostatic charge exceeding capacity of the ESD (Electrostatic Discharge) protection circuitry. Safety earth
ground must be provided to anything in contact with the product, including any operator, floor, tester and soldering iron.

8.

Please note that this product is not designed to be radiation-proof.

9.

Testing and other quality control techniques are used to this product to the extent THine deems necessary to support warranty
for performance of this product. Except where mandated by applicable law or deemed necessary by THine based on the user’s
request, testing of all functions and performance of the product is not necessarily performed.

10. This product must be stored according to storage method which is specified in this specifications. THine accepts no liability
whatsoever for any damage or loss caused to the user due to any storage not according to above-mentioned method.
11. Customers are asked, if required, to judge by themselves if this product falls under the category of strategic goods under theForeign Exchange and Foreign Trade Act in Japan and the Export Administration Regulations in the United States of Americaon export or transit of this product. This product is prohibited for the purpose of developing military modernization, including
the development of weapons of mass destruction (WMD), and the purpose of violating human rights.
12. The product or peripheral parts may be damaged by a surge in voltage over the absolute maximum ratings or malfunction, if
pins of the product are shorted by such as foreign substance. The damages may cause a smoking and ignition. Therefore, youare encouraged to implement safety measures by adding protection devices, such as fuses. THine accepts no liability
whatsoever for any damage or loss caused to the user due to use under a condition exceeding the limiting values.
13. All patents or pending patent applications, trademarks, copyrights, layout-design exploitation rights or other intellectual
property rights concerned with this product belong to THine or licensor(s) of THine. No license or right is granted to the user
for any intellectual property right or other proprietary right now or in the future owned by THine or THine’s licensor. The user
must enter into a license agreement with THine or THine’s licensor to be granted of such license or right.

THine Electronics, Inc.
https://www.thine.co.jp

Copyright©2023 THine Electronics, Inc.

15

THine Electronics, Inc.
SC: E