Datasheet
ZSSC3241
Sensor Signal Conditioner IC for Resistive Sensors

Description

Features

The ZSSC3241 is a sensor signal conditioning IC(SSC) for highly accurate amplification, digitization,and sensor-specific correction of resistive sensor
signals. The ZSSC3241 provides best-in-classsensor-element adaptability, and it is suitable forbridge and half-bridge sensors, as well as external
voltage-source element and single-element sensors(e.g., Pt100 and external temperature sensor
diodes) powered by an on-chip current source.
Digital compensation of the sensor offset, sensitivity,
temperature drift, and non-linearity is accomplished
via a 26-bit math core running a correction algorithmwith calibration coefficients stored in a non-volatile,
reprogrammable memory. A second, separate
compensation for gain and offset, and digital-output
independent analog-output correction is supported
for optimum adaptability of dual-domain (analog anddigital) sensor solutions. The programmable,
integrated sensor front-end allows optimally applying
various sensors for a broad range of applications.

•

The ZSSC3241 provides measurement value
readouts and programming capabilities via an I2C,
SPI, or one-wire interface (OWI). Three different
operation modes allow optimal development ofdigital, digital-analog, and analog-output smart
sensor modules including wake-up on request,
continuous-on/fast-response, and automatic/cyclic
sensor measurement operations. Absolute andratiometric voltage, current-loop, or interrupt analog
outputs are supported by the ZSSC3241. The
analog output options and digital interface options(for calibration and/or a digital application interface)can be combined.

o

SPI up to 10MHzo

I2C (Standard, Fast, and High-Speed Mode)oOne-wire-interface (OWI), up to 100kBit/s•

Accommodates nearly all resistive bridge sensor
types (signal spans from 1mV/V up to 500mV/V)•

Supports different sensor element configurations:oResistive bridge or half-bridgeoResistive divider stringoVoltage source•

On-chip temperature sensor•

External temperature sensing supported, e.g.
sensor-bridge as temperature detector, external
diode, etc.

•

Support for Pt100•

Programmable 16-bit digital-to-analog-converter andoutput:o(0V to 1V) or (0V to 5V) absolute voltage outputo

VDD-ratiometric voltage outputo

4mA to 20mA current-loop output supported•

On-chip voltage regulators for sensor supply, and IC
operation•

Support for extra regulation by external transistor, forexample JFET•

Programmable 24-bit sensor-signal-conditioning(main) math core•

Programmable 16-bit signal-conditioning (support)
math core for dual-domain sensor-applications•

Reprogrammable, nonvolatile memory (NVM)•

Programmable measurement scheduler forcontinuous sensing applications, with optimizedbalance of:Basic Application Diagram
SensorElement

Digital communication and calibration interfaces

VDDoEnergy consumptiono

Output update rateoSelf-diagnostic coverage and system safety

VSS

ZSSC3241

Optional Digital Master(I2C, SPI, OWI)

Feb.2.24

OUTANA•

Programmable analog-output clipping•

On-chip diagnostics:o

Sensor connectionoBroken-chip-check / chipping-checko

Memory integrity

Page 1ZSSC3241

Datasheet

Physical Characteristics

Typical Applications•

Supply voltage, VDD: 2.7V to 5.5V;
with external transistor, for example
JFET: 5V to 48V•Calibrated, continuously operating sensors withdigital interface and/or analog output: (absolute or
ratiometric) voltage or current loop output•

Operating temperature: -40°C to 125°C••

Supported sensor elements: 0.5kΩ to 60kΩ

Enables smart, digital sensors for energy-efficientsolutions•

Pressure, flow, and level sensing•

Industrial applications; e.g. process/factory
automation•

Consumer / white goods, e.g. HVAC, weight scales•

Medical applications, e.g. blood pressure,continuous smart health monitors•

Available as die on wafers or 4  4 mm2 24-QFN
with wettable flanks, allowing visual inspection of
QFN reflow quality

Block Diagram
Sensor Supply: voltage / ratiometric

VDDB

VTP

SensorBias
Current

VTN

Internal
Temp.
Sensor

AGND / CM
Generator

IC Bias Current
Generator

Internal
Voltage
Regulators

Power Ctr.

Sensor Supply:
current mode

Ana

VDD
VSS

Dig

ZSSC3241
Input
Multiplexer

DAC
13-16Bit

INP
VSSB

A

MUXOUT

SensorElement

LDOctrl
external
Transistor
Regulation

VDDA int

MUXSENS-SUPTEXT

AOUT /
OWI1
RESQ

D
PGA

FB

12-24Bit
DAC-SSCOWIOWI2inINN
Digitial Control andMath Core
SensorConnection
Diagnostics

Chipping
Check

Power-ON
Reset

Clock
Generator
Oscillator

Analog
SystemControl
Unit

EOC

SPI
NVM
I2C

SCLK/SCLSS
MOSI/SDA
MISO

VDD(2.7-5.5V)

VDD(2.7 to 5.5V)

VSS

VDDB

INP
Rt1

PTC /
NTC

VSSB

VSS

INP

AOUT / OWI1

ZSSC3241

VSSB

4 INN

AOUT / OWI1

4 INN

MISO

SCLK / SCLMOSI / SDA

ZSSC3241

RESQ

Sensor HalfBridge

VDD

VDDB

CAOUT,EMC

VDD

Typical Application Examples

OWI

VOUT, absolute(0 to 1V / 0 to 5V)

OWI

SS

Sensor Bridge

Digital Interface:
I2C or SPI or OWI

Analog Sensor with Absolute Voltage Out

Digital Half-Bridge Sensor, e.g. PT100
VDD(2.7 to 5.5V)

Loop+(7 to 48V)

VDD

5 to 5.5V

VDDB

OWI

VSS
INP

ZSSC3241

VDDB

VSS

SS

OWI

MISO

SCLK / SCLINPMOSI / SDA

RESQ

Sensor Bridge

LDOctrl(2.5% to 97.5% of VDD)

AOUT /
OWI1

VSSB

4 INN

VDD

VOUT, ratiometric

VSSB

ZSSC3241

VDD(2.7 to 5.5V)

Digital Interface:
I2C or SPI or OWIFBAOUT / OWI1

4 INN

OWI2inSensor Bridge

Rsens

Sensor with Ratiometric Voltage Output and Digital
InterfaceFeb.2.24

Loop4 to 20mA

Analog Sensor with Current Loop Output, OWI, and External
JFET

Page 2ZSSC3241

DatasheetContents
1.

Pin Assignments ............................................................................................................................................ 62.

Pin Descriptions ............................................................................................................................................ 7

3.

Absolute Maximum Ratings.......................................................................................................................... 8

4.

Recommended Operating Conditions ......................................................................................................... 8

5.

Electrical Characteristics .............................................................................................................................. 9

6.

Device Description ...................................................................................................................................... 12
6.1

Signal Flow .......................................................................................................................................... 13

6.2

Analog (Sensor) Front-End .................................................................................................................. 14
6.2.1.

Programmable-Gain Amplifier (PGA) .................................................................................... 14

6.2.2.

Analog-to-Digital Converter (ADC) ........................................................................................ 17

6.2.3.

Internal Temperature Sensor ................................................................................................ 18

6.2.4.

Supported Supplies for Sensor Elements and Additional, External Temperature Sensing .. 18

6.3

On-Chip Diagnostics ............................................................................................................................ 25

6.4

Digital Interfaces .................................................................................................................................. 27

6.5

6.6

6.7

6.4.1.

SPI ......................................................................................................................................... 28

6.4.2.

I2C ......................................................................................................................................... 30

6.4.3.

One-Wire-Interface, OWI ...................................................................................................... 32

Measurement and Output Options ...................................................................................................... 36
6.5.1.

Single Measurements, Digital Raw Results, and SSC Results ............................................ 36

6.5.2.

Cyclic, Continuous, Repeated Measurements – Measurement Scheduler .......................... 38

6.5.3.

Analog Outputs: Digital-to-Analog Converter (DAC) ............................................................. 39

6.5.4.

Output Interrupt Signaling ..................................................................................................... 42

System Setup and Control ................................................................................................................... 46
6.6.1.

Digital Commands ................................................................................................................. 47

6.6.2.

Nonvolatile Memory (NVM) ................................................................................................... 50

6.6.3.

Digital Sensor-Signal-Conditioning Mathematics .................................................................. 62

External, Extra LDO (LDOctrl) for Applications for > 5.5V .................................................................. 66

7.

Calibration .................................................................................................................................................... 67

8.

Package Outline Drawings .......................................................................................................................... 67

9.

Marking Diagram .......................................................................................................................................... 67

10. Ordering Information ................................................................................................................................... 68
11. Glossary........................................................................................................................................................ 68
12. Revision History .......................................................................................................................................... 69

Feb.2.24

Page 3

ZSSC3241

Datasheet

FiguresFigure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.

Pin Assignments for 4  4 mm2 24-QFN Package – Top View .......................................................6
Pin (Pad) Assignments for Bare Die ...............................................................................................6
Main Operating Modes of the ZSSC3241 .....................................................................................12
IC-Architecture View for Sensor-Signal-Transfer Perspective ......................................................13
Analog Sensor Front-End Topology ..............................................................................................14
SPI Configuration CPHA=0 ...........................................................................................................28
SPI Configuration CPHA=1 ...........................................................................................................29
SPI Command Request ................................................................................................................29
SPI Read Data ..............................................................................................................................29
SPI Read Status ............................................................................................................................30
I2C Command Request ................................................................................................................30
I2C Read Data ..............................................................................................................................31
I2C Read Status ............................................................................................................................31
General Block Schematic of the OWI Interface ............................................................................32
OWI Timing Diagram.....................................................................................................................33
OWI Extra (Activation) Pulse for Concurrent OWI and Analog Output Configuration ..................33OWI Command Request ...............................................................................................................34
OWI Response by ZSSC3241 ......................................................................................................35
Example Configuration for the Measurement Scheduling and Cyclic Mode Operation ................38
Measurement Result Output Update in Cyclic Operation (with “Slow” Interface Polling) .............39
DAC and Analog Output Topology................................................................................................39
Current Loop Configuration ...........................................................................................................42
EOC-Behavior: Signalization of End-of-Conversion (INT_setup = 00BIN) .....................................43
EOC and Interrupt Thresholds without Hysteresis (eoc_hyst_on=0BIN)........................................44
EOC and Single-Interrupt Thresholds with Hysteresis (eoc_hyst_on=1BIN) .................................45
EOC and Dual-Interrupt Thresholds with Hysteresis (eoc_hyst_on=1BIN) ....................................46
Digital IC Section Architecture ......................................................................................................47
LDOctrl Application Topology .......................................................................................................66

TablesTable 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.

Pin Descriptions ..............................................................................................................................7
Absolute Maximum Ratings ............................................................................................................8
Recommended Operating Conditions .............................................................................................8
Electrical Characteristics .................................................................................................................9PGA Gain: Stage 1........................................................................................................................14
PGA Gain: Stage 2........................................................................................................................15
Absolute Offset Shift – Properties .................................................................................................15
Absolute Offset Shift – Differential Sensor Signal’s Offset Compensation ...................................16
PGA Input Span Ranges ...............................................................................................................16
Single Analog-to-Digital Conversion .............................................................................................17
ADC Offset Shift ............................................................................................................................18
Sensor Supply Options .................................................................................................................18
Supported Sensor Front-End Configuration Options ....................................................................18
Sensor Supply – Main Sensing .....................................................................................................21
Sensor Bias Currents – Sensor Sourcing in Current Mode ..........................................................22

Feb.2.24

Page 4ZSSC3241

Datasheet

Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.

Sensor Supply – IC External Temperature Sensing Configuration Examples..............................22
Diagnostic Signalization Options with ZSSC3241 ........................................................................26
Information Assignment for CHECK_DIAG Command: Output Register diagnosticreg [15:0] .....27
General Status Byte ......................................................................................................................28
Mode Status ..................................................................................................................................28
SPI Interface Parameter ...............................................................................................................30
I2C Interface Parameter ................................................................................................................31OWI Dimensioning Examples .......................................................................................................32OWI Interface Parameters ............................................................................................................33
Data Format of Raw ADC Readings .............................................................................................36
Data Format of Corrected, SSC Results (S and T) .......................................................................36
Typical Conversion Times for Complete SSC Sensor Measurements: SM, TM ..........................37
Typical Conversion Times and Noise Performance for Complete SSC Measurements ..............37
DAC Configurations ......................................................................................................................39
Direct Voltage Outputs ..................................................................................................................40
Recommended Operating Conditions for Voltage Output ............................................................41
ZSSC3241 Current-Loop-Specific Properties ...............................................................................41
Data Format of Interrupt Thresholds (TRSH1a, TRSH1b, TRSH2a and TRSH2b) ......................43
Command List ...............................................................................................................................47
Memory (NVM) Content Assignments ..........................................................................................51
Data Format of 24-bit SSC Coefficients ........................................................................................63
Data Format of Corrected, SSC Results (S and T) .......................................................................63
IC Supply, VDD Target Level Selection with External Voltage Regulation, External LDO .............66
External LDO Operating Conditions ..............................................................................................66

Feb.2.24

Page 5ZSSC3241

1.

Datasheet

Pin Assignments

n.c.

LDOctrl

n.c.

Text

n.c.

VDD

The ZSSC3241 is available as 8-inch wafers and in a 24-QFN package. Detailed information about die andwafers is available on request (see last page for contact information).

24

23

22

21

20

19

25

VDDB

1

18

VSS

INP

2

17

FB

VSSB

3

16

AOUT / OWI1

ZSSC3241
14

EOC

Renesas-Test

6

13

SS

7

8

9

10

11

12

MISO

5

SCLK / SCL

Renesas-Test

n.c.

OWI2inMOSI / SDA

15

Renesas-Test

4

RESQ

INN

: QFN-bottom plate, Exposed PAD.

Figure 1.

Pin Assignments for 4  4 mm2 24-QFN Package – Top View
IC CoreSeal Ring

LDOctrl

VDD

Text
VSS

VDDB
FB

INP

AOUT / OWI1VSSB

OWI2inINN

EOC

RenesasTest
RenesasTest

SS
MISO

RESQ
MOSI / SDA
RenesasTest

SCLK / SCL

Figure 2.

Feb.2.24

Pin (Pad) Assignments for Bare Die

Page 6ZSSC3241

2.

Datasheet

Pin Descriptions

Table 1.

Pin Descriptions

Pin Number

Name

1

VDDB

2
3
4
5
6
7
8

INP
VSSB
INN
Renesas-test
Renesas-test
RESQ
Renesas-test

9

MOSI / SDA

10
11

n.c.
SCLK / SCL

AnalogInput/Output
Analog Input
Analog Input
Analog Input––
Digital Input–
DigitalInput/Output–
Digital Input

12

MISO

Digital Output

13
14
15

SS
EOC
OWI2in16

AOUT / OWI1

Digital Input
Digital Output
Digital Input
Analog Output;
DigitalInput/Output

17

FB

Analog Output

18
19
20

VSS
VDD
n.c.

GroundSupply–21

TEXT

Analog Output

22

n.c.

–

23

LDOctrl

Analog Output

24

n.c.

–

25

Exposed PAD-

Feb.2.24

Type

Description
Positive sensor (bridge) supply or sensor-signal input.
Positive sensor (bridge) signal.
Sensor (bridge) ground or sensor-signal input.
Negative sensor (bridge) signal.
Renesas-internal use only. Connect to VSS or no connection; leave pin floating.
Renesas-internal use only. Connect to VSS or no connection; leave pin floating.
Digital IC reset (low active); internal pull-up.
Renesas-internal use only. Connect to VSS or no connection; leave pin floating.
Digital data input for SPI or bidirectional data I/O for I2C. Pull-up to VDD.
No connection. Leave pin floating.
Clock input for SPI or I2C interface. Referenced to applied VDD level.
Data output from ZSSC3241 to master for SPI interface. Referenced to applied
VDD level.
Slave select (interface enable) for SPI. Referenced to applied VDD level.
End-of-conversion and output interrupt signal.
Optional OWI interface input line for current-loop applications.
Analog smart-sensor output signal and/or OWI-interface input/output line.
Short-circuit protection, capping the short-circuit current at 10-12mA (maximum
output range of the internal driver).
Current-loop application feedback output (level below VSS!). No connection if notused.
Power supply ground.
Power supply.
No connection. Leave pin floating.
Current drive output for external temperature sensor and/or bridge in Current
Mode. A 150Ω serial resistor is built in the IC internally for pad-protection
purposes.
No connection. Leave pin floating.
Control output (reference signal) for (optional) external regulator / supply control
loop.
No connection. Leave pin floating.
QFN-bottom plate, i.e. Die-bottom/substrate. Connect to VSS, PAD to be used
for heat dissipation and additional EMC robustness.

Page 7

ZSSC3241

3.

Datasheet

Absolute Maximum Ratings

The absolute maximum ratings are stress ratings only. Stresses greater than those listed below can cause
permanent damage to the device. Functional operation of the ZSSC3241 at absolute maximum ratings is not
implied. Exposure to absolute maximum rating conditions might affect device reliability.
Table 2.

4.

Absolute Maximum Ratings

SymbolParameter

TJ
TS

VDD_max
VIF_max

Junction temperature
Storage temperature
ESD – Human Body Model
ESD – Charged Device Model
Latch-up
Maximum allowed for voltage supply
Voltage at digital interface pins

Conditions

VFB_max

Voltage at FB pin

Minimum

Maximum

Units

-100
-0.3
-0.3

135
150
4000
750
+100
6.5
5.5

°C
°C
V
V
mA
V
V

-2

2

V

-45

Referenced to VSS.
I2C pins: SDA, SCL
4mA to 20mA current loop
interface

Recommended Operating Conditions

Table 3.

Recommended Operating Conditions

SymbolParameter

Minimum

TypicalMaximum

Units

VDD
TA

Power supply voltage
Ambient temperature (depending on the part code)
External (parasitic) capacitance between VDD and VSS,
without external supply transistor regulation
External (parasitic) capacitance between VDD and VSS, with
(optional) external supply transistor regulation
Recommended, external capacitance between VDDB and
VSS for electro-magnetic immunity (EMI)
Recommended, external capacitance between AOUT versus
VSS, and versus VDD for EMI [a]Load current through external sensor element [b]External temperature diode and RTD input range, drop overexternal element referenced to TEXT pin
Absolute sensor signal input level, INN, INP pins
Minimum level at VDDB [b]Maximum level at VSSB [b]At maximum 85°C, up to VSSB=0.60V can be applied underratiometric sensor supply (with internal Rt’).
Maximum current load at AOUT pin for voltage outputs
Recommended VDD rise slew rate for power-on-reset (POR) [c]

2.7
-40

–
–

5.5
125

V
°C

0

100

–

80

100

120

0

6.8

8

nF

0

22

33

nF

0.02

0.5

4

mA

-0.2

–

1

V

0.5
0.9

–
–

1.2
–

V
V

-

–

0.55
(0.60)

V

1.5

–

18
–

mA
V/ms

CVDD

CVDDB,EMC
CAOUT,EMC
ISensor
VDioDrop
VSens_in
VDDBratio_min
VSSBratio_max
Imax_AOUT_V
SRVDD_PORnF[a]

For applications with OWI-interface or analog voltage-output.

[b]With ratiometric sensor supply configuration; e.g. a ratiometric bridge or bridge as temperature sensor with internal or external Rt.

[c]

Per design, there is no (theoretical) minimum VDD slew rate to trigger a clean POR. Nevertheless, a reasonable slew rate isrecommended.

Feb.2.24

Page 8ZSSC3241

5.

Datasheet

Electrical Characteristics

All parameter values are valid only under specified operating conditions. All voltages are referenced to V SS.
Table 4.

Electrical Characteristics

Note: See important notes at the end of this table.
SymbolIIC
IIDLE

Parameter
Current consumption,
active IC
Idle current consumption,
IC in Idle State
Average current draw

IAVE

VDD,LDOctrl

ISUP
ErrTBIASVTBIASVDDB(VDDAint)
PSRRLOWPSRRHIGH
rADC
fS,raw
VADCmid(AGND)ENOB [g]rDACtDACsettle

VDACout

BWDAC
SRout

IOUTmax

IDRloopFeb.2.24

Target level regulation
range to generate VDD
after external transistor,
for example JFET
Sensor bias
Relative sensor bias
current error [a]Drop over sensor bias
current source
Internally regulated
analog (bridge) sensor
front-end supply
Power supply rejection
ratio[b], only internal
regulator
Resolution
Single-conversion rate,
conversions per second
Differential ADC input
common mode [c]Conditions
IC Supply
Excluding connected sensor elements(with LDOctrl enabled)
Typical value at 30°C, maximum value at
85°C (125°C)
OWI and LDOctrl disabled
Mean current consumption for one
complete SSC measurement cycle persecond at 16-bit digital-only output
Using LDOctrl and external transistor;
programmable setup: VDD_ldoctrl_target(see section 6.7)
Sensor Supply
In the case of a Current Mode sensor
supply; setup in temp_source andsensor_sup (see section 6.2)
referenced VDDAint from internal analog
regulator
In the case of a ratiometric sensor
supply, setup in temp_source andsensor_sup
Attenuation of VDD fluctuations in therange of fVDD = 0Hz to 10MHz
fVDD > 10MHz
Analog-to-Digital Converter (ADC, A2D)
Single external sensor A2D conversion(without auto-zero measurement AZ);
resolution dependent

Minimum

TypicalMaximum

Units

–

2.3

2.80

mA

–

1.5

6
(22)

µA

–

–

3.5

µA

4.6

5.2

5.5

V

5
-3.5

80
-1

500
1.5

µA
%

–

200

230

mV

1.68

1.75

1.80

V

45

50

–

dB

20

–

–

dB

12
0.21
(ADC:
24-bit)
–

16
2.56
(ADC:
16-bit)
0.5

24
5.81
(ADC:
12-bit)
–

Bit
kHz

VDDB

18.1

–

Bit

14
65

16
150

Bit
µs

–

1

V

–

5

V

–
15
100

100
20
-

%VDD
kHz
mV/µs

12

18

mA

100

160

µA

With internal regulator supplying VDDB
pin, typical: VDDB/2 = 875mV (equals
PGA output common mode level)
Effective number of bits,
For gain < 78, shorted input,
15.8
3Noise basedrADC = 24-bit, no oversampling
Digital-to-Analog Converter (DAC) and Analog Output
Resolution
13
Analog voltage output
Time from 30% steady state until 99% of0
new DAC output (100% out) value issettling timereached; varies with level differences
Absolute output, Aout_setup = 010BIN
0.025(see section 6.5.3.2)
Addressable output
Absolute output, VDD > 5.01V,
0.025
voltage at AOUT pin
Aout_setup = 011BIN
Ratiometric output, Aout_setup = 001BIN
0.1
Output filter bandwidth
Without external components
12
Resistive load > 2kΩ,
Output slew rate
20
capacitive load < 20nF at Aout,
temperature = 25°C
This current level must be overdriven
Maximum output current
10
from an OWI-Master, if concurrent DACoutput and OWI communication is
configured.
Current loop driving
Aout_setup = 000BIN; depends onconnected bipolar transistor for current
current–
loop application

Page 9

ZSSC3241

Symbol
Gamp
Gerr
VCMin

fSSCout

ErrA,IC
Vioffsc

ΔADC,cDatasheet

Parameter
Gain
Gain error
Supported input common
mode

Output (Update) rate [d]ZSSC3241 accuracy
error
Correctable (in PGA),
absolute, differential input
offsetCorrectable (in ADC),
relative, differential input
offsetAbsolute sensor input

VINP, VINN
VTEXT

External temperature
diode or RTD input range

RSENSOR

External sensor (bridge)
resistance|VDIFFin|

Differential input signal
range

Ropen
RshortSensor connection loss;
i.e., open threshold
Sensor connection shortthreshold
Valid sensor input signal

Vs,valid

tSTA1
tSTA2
tWUP1

Start-up Time

Wake-up Time

tWUP2
fCLK

rTemp

Rt, Rt'Feb.2.24

Conditions

TypicalMaximum

Units

1.32
-2.5

–
0

540
2.5

V/V
%

0.70

0.85

1.00

V

0.09

1.22

2.50

kHz

–

1.22

–

kHz

1.33

1.43

1.58

kHz

–

–

0.01

% FSO

-15

0

15

mV

0

–

98

%

0.5

–

1.20

V

0.5

–

1.25

V

VDDB = 1.75V
For 4mA to 20mA current loop output
Referenced to sensor supply (VDDAint);
leading to full scale analog excitation
Diagnostics
INP vs. INN

0.5
1.6

–
–

60
60

kΩ
kΩ

2.6

50

700

mV

70

–

–

kΩ

INP vs. INN; TEXT vs. VDDB

–

–

400

Ω

0.44

–

1.31

V

–
–

–
–

2
2.5

ms
ms

–

2

10

µs

–

–

2

ms

5.9

6.0

6.1

MHz

12

35

–

Counts/K

1.34

–

40

kΩ

Percentage of sensor signal offset
versus maximum sensor signal
Input
Voltages at INP and INN pin; resulting
minimum/maximum differential voltages:-700mV < VINdiff < 700mVAt TEXT pin

Beyond Vs,valid, sensor connection checks(such as in-range, etc.) signalize
Diagnostic FAULTs
Power-Up
VDD ramp up to interface communication
VDD ramp up to analog operation
Sleep to Active State interface
communication
Sleep to Active State analog operation
Oscillator

Internal oscillator
frequency
Internal temperature
sensor resolution
Internal low TC [f]top/bottom resistance forexternal temperature

Minimum

Programmable-Gain Amplifier (PGA)
120 steps
Referenced to nominal gain, T = 25°C
VDDAint = 1.75V, valid for ratiometric andcurrent mode sensor supply
Sensor Signal Conditioning Performance
Cyclic operation
SSC-corrected (S, T) digital output rate,
ADC:16-bit (see section 6.5.1)
Complete SSC cycle (S, T) including
analog output update; ADC: 14-bit; DAC:
14-bitAccuracy error with an ideally linear
sensor (in temperature and measurand)
Programmable in 1mV steps; accuracy:±5% referenced to nominal setup

Temperature Sensor(s)Setup: rADC,Tsens,int = 13-bit
Programmable with internal_rt andextra_rt;applied if temp_source є {010; 110} (seesection 6.2.4)

Page 10ZSSC3241

SymbolDatasheet

Parameter

Conditions

Minimum

TypicalMaximum

Units

0.05
0.33
–
1000
10

1
–
–
3
10000
–

12
3.4
10
7
–
–

MHz
MHz
kBit/sms
Numeric
Years

Interface and Memory
fC,SPIfC,I2C
CDOWI
tPROG
nNVM
tRET,NVM

SPI clock frequency
I2C clock frequency
OWI data rate
NVM program time
NVM endurance
Data retention

Programming time per 16-bit word
Number of reprogramming cycles[a]Referenced to nominal value. Relative errors are typically < 1% for sensor bias current setups > 20µA.

[b]

PSRR = 20·log10(VDD/VDDB): will be improved when applying external filter elements at V DD and/or also using an external JFET
regulator.

[c]

This parameter must be taken into account if automatic common mode regulation in the PGA is switched off (pga_en_shift; seesection 6.2.1) and a non-symmetric sensor supply and input to the PGA ADC path have been configured.

[d]There are several setups and parameters that allow optimizing and maximizing the output update rate; e.g., ADC and DAC
resolutions, configurations for the measurement sequence, usage of the internal or an external temperature sensor.

[e]Vioffsc and ΔADC,c can be arbitrarily set up and combined. They work independently on each other.

[f]Typical residual temperature variation of voltage across Rt, Rt': 10ppm/K; maximum deviation: 150ppm/K at
40kΩ and >100°C, all other setups and conditions < 60ppm/K.

[g]

ENOB = log2( 2rADC / 3Noise ) with, for example rADC[Bit] = 24.

Feb.2.24

Page 11

ZSSC3241

6.

Datasheet

Device Description

The ZSSC3241 can be set up to for one of three main operating modes:
Sleep Mode

The Sleep Mode is recommended for smart sensors with purely digital output. The
ZSSC3241 automatically enters the idle state after command execution for minimum
current consumption, whereas the interface is still listening and accepts commands.
After receiving a valid command, the ZSSC3241 wakes up, executes the command,
provides the results at the digital interface, where the results must be read, and returns
to idle state after the data fetch. The results are only available once; repeated data fetch
is not supported. In Sleep Mode, sensor measurement results cannot be provided at theanalog output of ZSSC3241.

Command Mode

The Command Mode is most appropriate for evaluation, test, and calibration purposes.
In this mode, all commands are available, both digital and analog outputs are supported
and all functionality is available. Command Mode can be used for applications requiring
re-occurring (or even continuous) digital interaction, potential analog output, andminimum latency. Applications in Command Mode are only active on command request.

Cyclic Mode

In Cyclic Mode, autonomous, cyclically repeated sensor measurements are performed
and related digital and/or analog output updates are provided. Cyclic Mode isrecommended for analog output applications. The cyclic sequence for measurements,
diagnostics, and hence the output update rate is configurable.

The ZSSC3241 always enters the programmed default_mode after power-on (reset). One of the three operating
modes can be set up as the default. After the ZSSC3241 is powered and has entered its default mode, changing
to one of the other operating modes is possible via the mode change and start commands: START_CM,
START_CYC, START_SLEEP (see section 6.6.1 for details).
Power-On (VDD),
Reset

Initialization(load from configurations from NVM,
interfaces, default_mode, etc.)

10 BINdefault_mode

01 BIN

00 BIN
Sleep Mode(wake up on command, automatic
sleep after command execution, no
analog output)

START_SLEEPSTART_CM

Command Mode(activity on command, digital andanalog output supported, fastest
response, all commands)

START_CYC
START_CM

Cyclic Mode
(autonomous measurements, digital
and analog output supported, limitedcommands)

START_CYC
START_SLEEP

Figure 3.

Main Operating Modes of the ZSSC3241

The ZSSC3241 supports three different types of digital interfaces: I2C, SPI, and OWI. All interface types allow
application and control of each of the main operating modes.
Exception: The combination of Sleep Mode as the default mode (see the default_mode bit in the SSF1 register inTable 35) and the OWI interface is not supported. The OWI interface must be disabled (owi_off = 1, bit[13] in the
SSF1 register) for correct Sleep Mode operation.

Feb.2.24

Page 12ZSSC3241

Datasheet

When using commands to change the operating mode, e.g. START_CM or START_SLEEP, validation of the
new operating mode is recommended; e.g., by reading an NVM register or simply retrieving the status byte.
Note: The ZSSC3241 always requires two or more interface command interactions after an operating modechange prior to any additional changes in the mode.

6.1

Signal Flow

See the figures on page 2 for the ZSSC3241 block diagram and circuit diagrams for different input sensors. The
ZSSC3241 supports two sensor supplies: ratiometric voltage and current mode, i.e., sensor current bias. In theratiometric sensor-supply configuration, VDDB and the power supply for analog circuitry are provided by an onchip voltage regulator, which is optimized for power supply disturbance rejection (PSRR). To improve noise
suppression, the digital blocks are powered by a separate voltage regulator. A power supervision circuit monitors
all supply voltages and generates appropriate reset signals for initializing the digital blocks.
The System Control Unit controls the analog circuitry to perform the measurement types: external sensor,
external or internal temperature, and offset measurement. The multiplexer selects the signal input to theamplifier, which can be the external signals from the input pins INP, INN, TEXT, VDDB, and VSSB or the internal
temperature reference sensor signals. A full measurement request will trigger an automatic sequence of all
measurement types and all input signals. The basic sensor signal source configuration is set up in the SSF1
register (see Table 35) in the on-chip memory.
The programmable gain amplifier (PGA) consists of two stages with programmable gain values. The ZSSC3241
employs a programmable analog-to-digital converter (ADC) optimized for conversion speed and noise
suppression. The programmable resolution from 12 to 24 bits provides flexibility for adapting the conversion
characteristics. To improve power supply noise suppression, the ADC uses the external sensor supply voltage,e.g., VDDB for the ratiometric supply of a connected full-bridge sensor element, as its reference voltage leading
to a ratiometric measurement topology. The remaining IC-internal offset and the sensor element offset, i.e., theoverall system offset for the amplifier and ADC, can be canceled via an offset and auto-zero measurement,
respectively.

24Bitphysics real-world measurand

24Bit

SPI

main SSC-Mathcorrected result

VDDB

I2C

raw ADC result
16Bit

INP
VSSB
INN

Input
Multiplexer>>

SensorElement

16Bit
16Bit

A
D
PGA

24Bit

SSCMath24Bit

DAC
13-16Bit

DACSSC

AOUT

12-24Bit
DAC-SSC pre-distorted/corrected result

VDD
VSS

Figure 4.

IC-Architecture View for Sensor-Signal-Transfer Perspective

The main math core accomplishes the auto-zero, span, and 1st and 2nd order temperature compensation of themeasured external sensor signal. The correction coefficients are stored in the non-volatile memory. In addition to
the main sensor or temperature signal compensation (see sections 6.6.3.1 and 6.6.3.2), a separate signal
conditioning is integrated to correct DAC offset and gain (see section 6.6.3.3). It is programmable to provide
SSC-corrected digital and analog outputs concurrently.
The ZSSC3241 supports SPI, OWI, and I2C interface communication for controlling the ZSSC3241,
configuration, and measurement result output. Analog output signals can be provided, which are proportional to
the sensor signal that has been compensated for nonlinearity and temperature. The ZSSC3241 can also checkand signalize numerous sensor and self-check diagnostic values.

Feb.2.24

Page 13

ZSSC3241

6.2

Datasheet

Analog (Sensor) Front-End

The main blocks and functions of the analog sensor front-end of the ZSSC3241 are illustrated in Figure 5. As atypical first setup, the type and supply of the connected (external) sensor element should be determined andconfigured. The sensor_sup and temp_source bits in the SSF1 register (03HEX; see Table 35) of the NVM must
be set up according to the connected sensor configuration.
Important: If using the current mode sensor biasing via the “Sensor Bias Current” block, which is configured with
the Tbiasout bit field (see section 6.2.4), ensure that the selection for bias current combined with thedimensioning for the connected external sensor is within the input common mode constraints, VCMin (typical
0.85V) as defined in Table 4.
VDDAint

Sensor Supply: Voltage / Ratiometric

1.75V

MUXSENS-SUP

TEXT

VDDB

Internal
Temp.
SensorVTP

SensorBias
Current

VTN

Sensor Supply:
Current Mode

Input Multiplexer

A

INP

VSSB

D

PGA

INN
adc_bits

sensor_sup

Tbiasout

Figure 5.

6.2.1.

gain_polarity

Gain_stage1

ioffsc Gain_stage2

adc_en_shiftadc_offset

Analog Sensor Front-End Topology

Programmable-Gain Amplifier (PGA)The amplifier has a fully differential architecture and consists of two stages. The amplification of each stage andthe external sensor gain polarity are programmable via settings in the measurement configuration register:•For the main sensor element: SM_config1 and SM_config2 (NVM addresses 14HEX and 15HEX; see Table 35)•

For an optional external temperature sensor: extTemp_config1 and extTemp_config2 (NVM addresses 16HEX
and 17HEX; see Table 35).

The first 7 bits of the *_config1 registers are the programmable gain settings Gain_stage1 and Gain_stage2. The
options for the programmable gain settings are listed in Table 5 and Table 6. The resulting analog gain is thelinear product of the stage 1 and stage 2 selection: GainPGA = Gain1  Gain2. With the programmable
Gain_polarity bit in the *_config1 registers, the sign of the effective PGA gain can be swapped; e.g., to invert thesensor characteristic’s slope and invert signal processing of the differential signal between INP and INN.
Table 5.

PGA Gain: Stage 1
Gain_stage1[3:0]Feb.2.24

bit[3]

bit[2]

bit[1]

bit[0]

0
0

0
0

0
0

0
1

Gain1 [V/V]
1.2
2

Page 14

ZSSC3241

Datasheet

Gain_stage1[3:0]bit[3]

bit[2]

bit[1]

bit[0]

0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
1
1
1
1
0
0
0
0
1
1
1
1

1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1

Table 6.

Gain1 [V/V]
4
6
12
20
30
40
60
80
120
150
200
240
300
Not assigned

PGA Gain: Stage 2
Gain_stage2[2:0]bit[2]

bit[1]

bit[0]

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

Gain2 [V/V]
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8

In addition to the amplification of the sensor input signals, the PGA’s first stage can perform an absolute offset
shifting of the differential sensor signal. This shift operation can be programmed in 1mV steps with theconfiguration setup ioffsc bit field in the SM_config2 and extTemp_config2 registers. The effective voltage-shiftdepends on the selected Gain1, Gain_stage1. The VIOFFSC values (in Table 8) correspond to the higher Gain1
values, i.e. Gain1 > 100. The PGA-operation including shift effect for a differential input signal, VDIFFin can be
described as:∙

VADC,IN = Gain2 Gain1

Table 7.

∙ (VDIFFin+ VIOFFSC ) − Gain2∙V

Absolute Offset Shift – Properties

SymbolParameter

IOFFSC

Relative accuracy of the effectively applied Offset Shiftreferenced to the selected setup per ioffsc[4:0], IC-to-IC variation
1st order temperature coefficient for the change of the effective
Offset Shift voltage for negative-voltage shift effects, i.e.
ioffsc[4]=0
1st order temperature coefficient for the change of the effective
Offset Shift voltage for positive-voltage shift effects, i.e.
ioffsc[4]=1
Fluctuation of output offset signal (VIOFFSC) versus nominal value
at 25°C; 20·log10(VIOFFSC/VIOFFSC)

TCneg,IOFFSC

TCpos,IOFFSCSNRIOFFSC

Equation 1

IOFFSC

Minimum

TypicalMaximum

Units

0.89

0.98

1.07

-

-0.25

-0.21

0

PPT/K

0

0.21

0.25

PPT/K

–

74

–

dB

The shifting can be configured independently for the main sensor and the optional, external temperature sensor.
If the absolute offset shifting is enabled, then the ZSSC3241 current consumption increases by 100µA. The
advantage of absolute offset shifting is an increase of analog dynamic range in the ZSSC3241’s sensor frontend, which results in higher measurement result quality (less noise/fluctuations).

Feb.2.24

Page 15ZSSC3241

Datasheet

Absolute Offset Shift – Differential Sensor Signal’s Offset Compensation

Table 8.

ioffsc[4:0]bit[4]

bit[3]

bit[2]

bit[1]

bit[0]

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

Shift Effect, VIOFFSC
0mV, no shift
-1mV
-2mV
-3mV
-4mV
-5mV
-6mV
-7mV
-8mV
-9mV
-10mV
-11mV
-12mV
-13mV
-14mV
-15mV
0mV, no shift
1mV
2mV
3mV
4mV
5mV
6mV
7mV
8mV
9mV
10mV
11mV
12mV
13mV
14mV
15mV

The PGA can perform an automatic adjustment for the PGA input to ADC input common mode. This can be
enabled via the pga_en_shift bit in the *_config2 registers. The supportable input common mode range at thePGA, i.e. at the sensor front-end input, is constant per IC because it is derived from the internally regulated
voltage VDDAint.
Table 9.

PGA Input Span Ranges

Total Gain, GAMP Examples

Gain1

Gain2

Max. Input Span, Differential Signal Range [mV]

540
420
330
280
220
144
103
88
72
60
48
39
30
19.2
13.2

300
300
300
200
200
120
80
80
60
40
40
30
20
12
12

1.8
1.4
1.1
1.4
1.1
1.2
1.3
1.1
1.2
1.5
1.2
1.3
1.5
1.6
1.1

5.0
6.4
8.1
9.6
12.2
18.5
25.9
30.5
37.5
45
56
69
90
140
204

Feb.2.24

Page 16

ZSSC3241

Datasheet

Total Gain, GAMP Examples

Gain1

Gain2

Max. Input Span, Differential Signal Range [mV]

10.2
5.2
3.0
1.32 [a]

6
4
2
1.2

1.7
1.3
1.5
1.1

264
519
900
1400

[a]

There is a general PGA-input range constraint to support VINdiff of ±700mV at maximum, which is especially dominating for GAMP < 2.

6.2.2.

Analog-to-Digital Converter (ADC)

An analog-to-digital converter (ADC) is used to digitize the amplifier signal. To allow optimizing the trade-off
between conversion time and resolution, the resolution can be programmed from 12-bit to 24-bit (adc_bits bit
fields in the SM_config1, and extTemp_config1 registers; see section 6.6.2.1). The ADC processes differential
input signals around its input common mode level: VADCmid. Table 10 lists the ADC resolution, signal ranges,
conversion times for a single Analog-to-Digital conversion.
Table 10.

Single Analog-to-Digital Conversion

Bit[3]

Bit[2]

Bit[1]

Bit[0]ADC
Resolution[Bits]

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

12
13
14
15
16
17
18
19
20
21
22
23
24
Not assigned
Not assigned
Not assigned

adc_bits[3:0]

Ratiometric ADC
Input Range [a], [c],VADC,IN [V]Absolute ADC
Input Range [b],VADC,IN [V]

Conversion
Time, Typical[µs]

Conversion
Rate, Typical
[kHz]

±1.42
±1.43
±1.41
±1.42
±1.41
±1.42
±1.41
±1.42
±1.41
±1.42
±1.41
±1.42
±1.40
–
–
–

±1.07
±1.08
±1.06
±1.07
±1.06
±1.07
±1.06
±1.07
±1.06
±1.07
±1.06
±1.07
±1.06
–
–
–

172
202
245
304
390
507
680
913
1255
1725
2410
3345
4715
–
–
–

5.8
5.0
4.1
3.3
2.6
2.0
1.5
1.1
0.8
0.6
0.4
0.3
0.2
–
–
–

[a]

With the following settings: ratiometric reference, sel_ref* = 1, and no ADC-shift (adc_en_shift = 0) nor extra ADC-gain, i.e. GainADC=1[b]

With the following settings: absolute reference, sel_ref* = 0, and no ADC-shift (adc_en_shift = 0) nor extra ADC-gain, i.e. GainADC=1[c]

Ratiometric reference together with application setup S2 or T2 (see section 6.2.4) leads to reduced ADC input range due to ADC
reference voltage derivation from VDDB pin voltage. ADC reference voltage depends on the mean sensor-bridge resistance andapplied sensor bias current.

The ADC can perform an additional offset shift (independent of the PGA shifting with ioffsc) in order to adapt
input signals with offsets to the ADC input range. The shift feature is enabled by setting adc_en_shift = 1 (bit[8]in the SM_config2 or extTemp_config2 registers). As defined in Table 11, the respective analog offset shift canbe selected with bits [14:12], adc_offset in SM_config1 or extTemp_config1.
Note: Enabling the offset shift causes the ADC to perform an additional amplification of the ADC’s input signal byfactor 2. This must be considered for a correct analog sensor setup by means of the PGA’s gain, the absoluteoffset shift in the PGA, the ADC offset shift, and the potential ADC gain.
The overall analog amplification GainTOTAL = GainPGA · GainADC can be determined for the following potential use
cases using Equation 2 or Equation 3 depending on the ADC offset setting:If no ADC offset shift is selected, i.e., adc_en_shift = 0 and adc_offset = 000, then
GainTOTAL = GainPGA  1

Feb.2.24

Equation 2

Page 17

ZSSC3241

Datasheet

If ADC offset shift is selected, i.e., adc_en_shift = 1 (adc_offset is configurable), then
GainTOTAL = GainPGA  2

Table 11.

Equation 3

ADC Offset Shiftadc_offset[2:0]bit[2]

bit[1]

0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
ADC-offset shift disabled, adc_en_shift = 0

6.2.3.

Compensation of Percentage
Offset in Input Signal

bit[0]
0
1
0
1
0
1
0
1

ADC Input Signal
Range [VADC,IN]

0%
6.25%
12.50%
18.75%
25.00%
31.25%
37.50%
44.00%
0% (compensation, 2-gain off)

-0.5 to 0.5-0.44 to 0.56
-0.38 to 0.62
-0.31 to 0.69
-0.25 to 0.75
-0.19 to 0.81
-0.13 to 0.87
-0.06 to 0.94
-1 to +1

Internal Temperature Sensor

The ZSSC3241 provides an internal temperature sensor measurement to allow compensation for temperatureeffects. The temperature output signal is a differential voltage that is adapted by the amplifier (PGA) for the ADC
input, comparable to the external sensor’s signal. For ZSSC3241-internal temperature measurements, therespective settings are defined and programmed in the NVM by Renesas.
6.2.4.

Supported Supplies for Sensor Elements and Additional, External Temperature Sensing

There are two options to supply and bias the external sensor element, which can be selected by the sensor_sup
bit field in the SSF1 register (03HEX) in the NVM (see Table 35). The differential sensor signal (e.g., from asensor bridge) is fed into the ZSSC3241 at the INP pin for the positive and the INN pin for the negative signal
level.
Table 12.

Sensor Supply Options

sensor_sup[1:0]bit[1]

bit[0]

0
0

0
1

1

0

1

1

External Main Sensor Supply
Ratiometric voltage: VDDB to VSSB.
Bias current out of VDDB.
No supply, INN internally connected to AGND, absolute voltage-source measurement (e.g., thermopile
between INP and INN).
Not assigned.

There are multiple possible combinations of an external main sensing supply and the SSC-input signal
generation with different sensing elements and approaches for generating a temperature signal for temperaturedependency compensation, see Table 13. Table 14 illustrates the possible main-sensor connections, application
circuits, and ZSSC3241 configurations.
Note: The applications circuits S1 to S3 and T1 to T6 highlight the supply paths in blue and the input signal paths
in red for the main sensing element connection and supply in Table 14 and for the supporting, external
temperature sensing in Table 16.
Table 13.

Supported Sensor Front-End Configuration Options
Supported Sensor Elements

Temperature Sensing,
T (AZT)IC internal temperature sensor

Feb.2.24

Main Sensing,
S (AZS)
Sensor bridge,
ratiometric supply

Setup
temp_source sensor_sup
000BIN

00BIN

Comment
Effect of sel_ref1 according to Table 35;
Tbiasout; internal_rt, extra_rt, sel_ref2 content
without effect

Page 18

ZSSC3241

Datasheet

Supported Sensor Elements

Setup

Temperature Sensing,
T (AZT)

Main Sensing,
S (AZS)IC internal temperature sensor

Sensor bridge, currentbias supply

000BIN

01BIN

Effect of sel_ref1 and Tbiasout according toTable 35;
internal_rt, extra_rt, extTemp_config content
without effectIC internal temperature sensor

Absolute voltage source, 000BIN
for example, Thermopile

10BIN

Must be set to sel_ref1=0BIN
Tbiasout; internal_rt, extra_rt, extTemp_config
content without effect

101BIN

00BIN

Must be set to extra_rt=0BIN;
effect of internal_rt, sel_ref1, sel_ref2 according
to Table 35;
Tbiasout content without effect

001BIN

01BIN

Must be set to extra_rt=0BIN ;effect of internal_rt, sel_ref1, sel_ref2, Tbiasout
as described

Main sensor bridge as
Sensor bridge,
temperature sensor, ratiometric ratiometric supply
supply, with external Rt
between TEXT and VDDB pads,
no internal Rt, Rt’

110BIN

00BIN

Must be set to extra_rt=1BIN;
sel_ref1, sel_ref2 according to Table 35
Tbiasout; internal_rt content without effect

Main sensor bridge temperature Sensor bridge,
sensor, ratiometric supply, with ratiometric supply
external Rt between TEXT and
VDDB pads and internal bottom
Rt’, no internal top-Rt [b]110BIN

00BIN

Must be set to extra_rt=0BIN ;internal_rt, sel_ref1, sel_ref2 according to Table
35
Tbiasout content without effect

Main sensor bridge temperature Sensor bridge, currentsensor, current bias out of TEXT bias supply
pad, with external Rt between
TEXT and VDDB pads andinternal bottom Rt’, no internal
top-Rt010BIN

01BIN

Must be set to extra_rt=0BIN ;internal_rt, Tbiasout, sel_ref1, sel_ref2
according to Table 35
Note-1: If ratiometric reference is selected forthe main sensor, then the reference source isthe voltage between VDDB and VSSB (T2, S2
combination see tables below).

External diode or PTC between Sensor bridge,
TEXT and VSSB, current biased, ratiometric supply
internal bottom-Rt’ at VSSB (toground/VSS)

100BIN

00BIN

Must be set to extra_rt=0BIN , sel_ref2=0BIN ;internal_rt, sel_ref1, and Tbiasout in
extTemp_config register according to Table 35
Tbiasout content in BM_config register without
effectExternal diode or PTC between Sensor bridge,
TEXT and VSSB, current biased, ratiometric supply
without internal bottom-Rt’

100BIN

00BIN

Must be set to extra_rt=1BIN , sel_ref2=0BIN ;sel_ref1, and Tbiasout in extTemp_config
register according to Table 35
internal_rt, and Tbiasout content in BM_config
register without effect

External diode or PTC between Sensor bridge,
TEXT and VSSB, current biased, ratiometric supply
internal top-Rt at TEXT andbottom-Rt’ at VSSB (toground/VSS)

011BIN

00BIN

Must be set to extra_rt=0BIN
sel_ref1 as describedinternal_rt, sel_ref2, and Tbiasout in
extTemp_config register according to Table 35
Tbiasout content in BM_config register without
effectExternal diode or PTC between Absolute voltage source, 100BIN
TEXT and VSSB, current biased, for example, Thermopile
internal bottom-Rt’ at VSSB (toground/VSS)

10BIN

Must be set to extra_rt=0BIN, sel_ref1=0BIN,
sel_ref2=0BIN.
internal_rt, and Tbiasout in extTemp_config
register according to Table 35
Tbiasout content in BM_config register without
effectExternal diode or PTC between Absolute voltage source, 100BIN
TEXT and VSSB, current biased, for example, Thermopile
without internal Rt, and Rt’

10BIN

Must be set to extra_rt=1BIN, sel_ref1=0BIN,
sel_ref2=0BIN.
Tbiasout in extTemp_config register according toTable 35internal_rt, and Tbiasout content in
BM_config register without effect

Main sensor bridge as
Sensor bridge,
temperature sensor, ratiometric ratiometric supply
supply, with internal Rt and Rt’

temp_source sensor_sup[b]Main sensor bBridge
temperature sensor, current
biased, with internal top-Rt andbottom-Rt’

Feb.2.24

Sensor bridge, currentbias supply

Comment

Page 19

ZSSC3241

Datasheet

Supported Sensor Elements
Temperature Sensing,
T (AZT)

Main Sensing,
S (AZS)

Setup
temp_source sensor_sup

External diode or PTC between Absolute voltage source, 011BINTEXT and VSSB, current biased, for example, Thermopile
internal top-Rt at TEXT andbottom-Rt’ at VSSB (toground/VSS)

10BIN

Comment
Must be set to extra_rt=0BIN, sel_ref1=0BIN;
internal_rt, sel_ref2 and Tbiasout in
extTemp_config register according to Table 35[a]

Any non-listed front end configuration setup leads to the IC internal default with temp_source=000BIN and sensor_sup=00BIN,
i.e. usage of internal temperature sensor and the external sensor(-bridge), ratiometrically supplied, as main sensor.

[b]Take into consideration: max. level constraint for VSSB ratio_max (see Table 3) in the case of ratiometric (external temperature)supply.

Feb.2.24

Page 20ZSSC3241

Application

Sensor Supply – Main Sensing
Front-End Configuration, Sensor Application, and Connection Circuit[a]
TEXT
VDDB

Rt

MUXSENS-SUP

Table 14.

Datasheet

SensorBias
Current

Internal
Temp.
Sensor

Input
Multiplexer

S0

VTP
VTN

INP
VSSB

Setup and Remarks
General sensor front-end overview for
main and supporting temperature
sensor connection and setup

PGA

INN

Rt´

extr a_rt

Regulated Voltage,
VDDA

TEXT

SensorElement

VDDB

SensorBias
Current

Internal
Temp.
SensorRatiometric bridge-type sensor setup:• Sensor element supplied through an
ZSSC3241 internal, regulated
voltage• sensor_sup = 00BIN

S1
Vsup
INP
PGA

VSSB
INN

Regulated Voltage,
VDDA

TEXT

SensorElement

Isup
VDDB

SensorBias
Current

Internal
Temp.
Sensor

S2
INP
PGA

VSSB

Current Mode bridge-type sensor
setup:• Sensor element biased through an
ZSSC3241 internal current source
via VDDB pad• sensor_sup = 01BIN
Note: When combined with T2application and if ratiometric referenceis selected, the reference source is thevoltage between VDDB and VSSB for
the main sensor measurement.

INN
Regulated Voltage,
VDDA

TEXT
VDDB

S3

SensorBias
Current

Internal
Temp.
SensorAbsolute-voltage sensor setup:• Sensor element not supplied• sensor_sup = 10BIN
Note: Only up to a maximum of 50% of
the input dynamic range is useable inthis configuration

SensorElement

INP

Voltage
Source VSSB

INN

[a]

PGA
AGND

Figure legend:o Blue line: sensor supply
o Red line: sensor signal

For a ratiometric sensor supply, the VDDAint voltage from the ZSSC3241-internal regulator is used. As defined inTable 15, the alternative sensor bias current source generates a bias current that is programmable with the
Tbiasout in bit field in the *_config2 registers (see Table 35).

Feb.2.24

Page 21

ZSSC3241

Table 15.

Datasheet

Sensor Bias Currents – Sensor Sourcing in Current Mode
Tbiasout
bit[2]

bit[1]

bit[0]

Nominal Sensor
Bias Current [µA]

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

5
10
20
39
79
157
196
494

The ZSSC3241 supports internal and external temperature sensing for sensor-signal conditioning (SSC)
purposes, i.e. an extra, separate temperature measurement in order to compensate temperature effects in themeasurand signal from the main sensing element; e.g., a pressure sensor. The respective setup must be
configured via the temp_source bit field in the SSF1 register.
If the main sensing element itself with its inherent temperature sensitivity is used to generate the temperature
information for SSC correction, then the internal_rt and extra_rt bit fields in the SFF1 register must be
programmed. Table 16 provides an overview of the supported IC external temperature measurement main
options. The internal resistors Rt and Rt’ have been designed for flat, almost zero-sensitivity to temperature,such that the resulting temperature sensor measurements’ characteristic is mainly dominated only by the(typically spurious) temperature characteristic of the main sensor element itself. The use of the bottom
resistance Rt’, selectable by extra_rt=0BIN is recommended for most related applications in order to have abridge-resistance-related, symmetric temperature excitation, and not to introduce further differential signal offset
when using the bridge-sensor element as the temperature sensor.
In any configuration, the constraints for the minimum/ maximum absolute and differential input signal dynamics
must be considered.
Table 16.

Sensor Supply – IC External Temperature Sensing Configuration Examples

Application

Front-End Configuration, Temperature Sensor Application, and Connection Circuit[a]Regulated Voltage,
VDDA

TEXT

Isup
SensorElement

SensorBias
Current

VDDB

VTP
VTN

Internal
Temp.
Sensor

Rt
T1

Rsens
INP
PGA

VSSB
INN
Rt´

Feb.2.24

extr a_rt

Setup and Comments
Bridge as the temperature
sensor with the internal Rt
and Rt’ in Current Mode• Sensor element supplied
through the ZSSC3241internal bias, i.e., thecurrent source• temp_source = 001BIN• internal_rt = User selected• extra_rt = 0BIN
Note: Only combine this T1
application withsensor_sup = 01BIN (i.e.,
main sensing application S2
in Table 14)

Page 22

ZSSC3241

Application

Datasheet

Front-End Configuration, Temperature Sensor Application, and Connection Circuit[a]IsupSensorElement

Regulated Voltage,
VDDA

TEXT
SensorBias
Current

VDDB

Rt,external

VTP
VTN

Internal
Temp.
Sensor

Rt
T2

Rsens

INP
PGA

VSSB

INN
Rt´

extr a_rt

Isup

RPTC
(or Didoe)

TEXT
VDDB

SensorBias
Current

INP

AGND

Regulated Voltage,
VDDA
Internal
Temp.
SensorSensorElement

T3.1

PGA

VSSB
INN

Rt´

extr a_rt

Isup
Sensor Element

Regulated Voltage,
VDDA

TEXT
SensorBias
Current

RPTC(or Didoe)

VDDB

Rsens
INP

AGND

INN
Rt´

Feb.2.24

Internal
Temp.
Sensor

Rt

VSSB

T3.2

VTP
VTN

extr a_rt

PGA

Setup and Comments
Bridge as temperature
sensor with an external Rt in
Current Mode:• Sensor element supplied
through the ZSSC3241internal bias, i.e., thecurrent source• temp_source = 010BIN• internal_rt = value close toRt,external• extra_rt = 0BIN
Note: Only combine this T2
application withsensor_sup = 01BIN (i.e.,
main sensing application S2
in Table 14)
Separate diode / PTCresistor as temperature
sensor in Current Mode:• Sensor element supplied
through the ZSSC3241internal bias, i.e., thecurrent source• temp_source = 100BIN• internal_rt = any• extra_rt = User selected• sel_ref2 = 0BIN must be
selected
Note: Only combine withsensor_sup = 10BIN (i.e.,
main sensing application S3
in Table 14)
Note: The voltage at TEXT
must fulfill input conditions
and must be in the range of
0.5V to 1.25V
Separate diode / PTCresistor as temperature
sensor in Current Mode:• Sensor element supplied
through the ZSSC3241internal bias, i.e., thecurrent source• temp_source = 100BIN• internal_rt = any• extra_rt = User selected• sel_ref2 = 0BIN must be
selected
Note: Only combine withsensor_sup = 00BIN (i.e.,
main sensing application S1in Table 14)
Note: The voltage at TEXT
must fulfill input conditions
and must be in the range of
0.5V to 1.25V

Page 23

ZSSC3241

Application

Datasheet

Front-End Configuration, Temperature Sensor Application, and Connection Circuit[a]Regulated Voltage,
VDDA

TEXT

SensorElement

SensorBias
Current

VDDB

VTP
VTN

Internal
Temp.
Sensor

Rt

Rsens

T4

INP

Vsup
PGA

VSSB
INN

Rt´

SensorElement

extr a_rt

Regulated Voltage,
VDDA

TEXT
Rt,external

VTP
VTN

SensorBias
Current

VDDB

Internal
Temp.
Sensor

Rt
Rsens

INP

T5

PGA

VSSB

INN
Rt´

extr a_rt

Isup

Sensor Element

Regulated Voltage,
VDDA

TEXT
SensorBias
Current

RPTC(or Didoe)

VDDB

[b]

T6

Internal
Temp.
Sensor

Rt
Rsens

INP
PGA

VSSB
INN
Rt´

[a]

VTP
VTN

Setup and Comments
Temperature sensor withinternal Rt with ratiometricsupply• Sensor element supplied
through the ZSSC3241internal regulated voltage
VDDA, i.e., radiometricsupply• temp_source = 101BIN• internal_rt = User selected• extra_rt = 0BIN
Note: Only combine this T4
application withsensor_sup = 00BIN (i.e.,
main sensing application S1in Table 14)
Temperature Sensor withexternal Rt with ratiometricsupply• Sensor element supplied
through the ZSSC3241internal regulated voltage
VDDA; i.e., theradiometric supply• temp_source = 110BIN• internal_rt = no value or
any value close to theexternal Rt• extra_rt = User selected
Note: Only combine this T5
application withsensor_sup = 00BIN only (i.e.,
main sensing application S1in Table 14)
Separate diode/PTC-resistor
as temperature sensor withinternal Rt and Rt’ in Current
Mode:• Sensor element supplied
through the ZSSC3241
internal regulated voltage
VDDA; i.e., theradiometric supply• temp_source = 011BIN• internal_rt = any• extra_rt = 0BIN
• sel_ref2 = User selected
Note: Only combine withsensor_sup = 00BIN or withsensor_sup = 10BIN (i.e.,
main sensing applications
S1 or S3 in Table 14)

Figure legend:o Blue line: sensor supply
o Red line: sensor signal[b]

The ratiometric supply for the main (bridge) sensor is kept on (if sensor_sup=00BIN is configured) by the IC during temperature
measurements.
If T6 is configured together with a non-zero bottom Rt’, the joint bias currents: Isup through the temperature sensor element and thecurrent through the bridge sensor must be considered in order to determine the VSSB-level, and hence MIN/MAX of TEXT-VSSB
as temperature sensing input signal.

Feb.2.24

Page 24ZSSC3241

Datasheet

When using scenario T1, “Bridge as the temperature sensor with the internal Rt in Current Mode” in Table 16,
the setup for bias current (Isup) and internal Rt must fulfill the requirements given in Equation 4 and Equation 5:(0.5  Rsens + Rt)  Isup = 0.85V ±125mV

Equation 4

Where Rsens is the nominal resistance of the sensor element; i.e. the typical, effective resistancegenerating the differential sensor signal as input to the INP and INN pads.
Important: Take into consideration the maximum specifications for the PGA common mode input
level, VCmin (see Table 4).
(MAX[Rsens ] – MIN[Rsens])  Isup < 700mV

Equation 5

Important: Take into consideration the maximum specifications for the input signal, MAX[VDIFFin](see Table 4).
The best method for deriving the respective values for Rt and Isup is to choose an Rt value close to but greaterthan Rsens and to calculate Isup accordingly.
When using scenario T4, “Temperature sensor with internal Rt with ratiometric supply,” in Table 16 the setup forbias current (Isup) and internal Rt must fulfill Equation 6:
Important: Take into consideration the maximum specifications for the PGA common mode input
level, VCmin, which is automatically ensured if Rt and the extra Rt’ are selected.
(MAX[Rsens] – MIN[Rsens]) / (Rsens + 2  Rt)  VDDBtyp < 700mV

Equation 6

Important: Take into consideration the maximum specifications for the input signal, MAX[VDIFFin]
with VDDBtyp = 1.85V.
In most cases, a low Rt value will suffice for ratiometrically supplied configurations. The lower the applied Rt
value, the less the noise-level effect onto the temperature measurement signal.
Sensor-bridge elements, which already contain a top resistor for temperature sensing purposes, can use theinternal extra Rt’.

6.3

On-Chip Diagnostics

The ZSSC3241 offers analog and digital self-test and sensor-diagnostic features to ensure robust system
operation. If the part is programmed and operated with analog output (cont_ANAoutn = 0BIN in the SSF2 register;see Table 35), then diagnostic states are indicated by upper and lower levels at the AOUT pin; see Table 17.
With the SPI, I2C, and OWI digital interfaces, the default status byte contains fault-diagnostics information. Iffurther detailed diagnostic information is required, the CHECK_DIAG command B0HEX must be issued to retrieve
the detailed diagnostics’ results in the diagnosticreg output register. The content of diagnosticreg (see Table 18)
is updated each time new respective diagnostic information becomes available. This is also the case with thedefault ZSSC3241 initialization after power-on-reset (POR) or if specific commands are triggered in order toperform diagnostic checks or influence diagnosticreg:
RESET_DIAG, B1HEX

Resets the contents of diagnosticreg.

UPDATE_DIAG, B2HEX

Performs all enabled diagnostic checks (selected via the select_checks bit field[9:0] in register 21HEX in NVM; see Table 35) and default diagnostic checks
including checksum validation of the NVM; results in complete update ofdiagnosticreg.

Connection Checks

These are scheduled connection checks in the Cyclic Mode setup. All enabledchecks (as selected with select_checks) are performed, and diagnosticreg is
updated accordingly.

Feb.2.24

Page 25ZSSC3241

Datasheet

The analog signalization of diagnostic states at the AOUT pin for the different analog output options can be
enabled/disabled via the diagouten bit in the SSF2 register 04HEX in the NVM (see Table 35). In Cyclic Mode, theanalog signalization of a diagnostic state is present with the SSC Calculation and Output Update phase of thesame measurement slot; see section 6.5.2. In Command Mode (with enabled analog output at AOUT pin), thediagnostic state at AOUT will be present with completion of the next SSC-conversion command, i.e. AAHEX or
ACHEX to AFHEX; see Table 34).
Table 17.

Diagnostic Signalization Options with ZSSC3241

Detected Fault

Analog RatiometricAnalog Absolute Diagnostic
Diagnostic Level, AOUT [a]Level, AOUT [a]Upper

0.125 to 4.875 V [b]0.025 to 0.975 V [c]0 to 0.125 V [b]0 to 0.025 V [c]4.875 V to VDD [b]0.975 to 1.0 V [c]Upper

4.875 V to VDD [b]0.975 to 1.0 V [c]No Error / Fault

2.5% to 97.5%

Memory Error

Lower

Loss of INP
Connection, INP
Open [d]Loss of INN
Connection, INN
Open [d]INN or INP Signals
Out of Range [d]UpperBridge/Sensor
Short (INN=INP)

Upper

T_ext Pin Open [d]Lower

T_ext Pin Out ofRange [d]T_ext Pin Short to
INP

Lower
Lower

T_ext Pin Short to
INN

Lower

Die Crack /Chipping CheckUpper

SSC Calculation
Unit Saturation

Upper (extra)

4.875 V to VDD [b]0.975 to 1.0 V [c]4.875 V to VDD [b]0.975 to 1.0 V [c]0 to 0.125 V [b]0 to 0.025 V [c]0 to 0.125 V [b]0 to 0.025 V [c]0 to 0.125 V [b]0 to 0.025 V [c]0 to 0.125 V [b]0 to 0.025 V [c]4.875 V to VDD [b]0.975 to 1.0 V [c]4.875 V to VDD [b]0.975 to 1.0 V [c]OWI, SPI, I2C Status
Byte [7:0]01XX X000BIN
0XXX X1XXBIN

0XXX XX1XBIN

Comments
Status after “reset.”
Checksum failure ofNVM.

A detailed, digital
decoding of therespective connection
check fault can be
fetched using the B0HEXCHECK_DIAG
command, which returns
the diagnosticreg register
content.

0XXX XXX1BIN[a]Only signalized if diagouten = 1BIN.

[b]With VDD = 5V ±10%, for 0 to 5V absolute analog out.

[c]With any VDD, for 0 to 1V absolute analog out.

[d]

Do not enable if the IC is connected to an absolute voltage source sensor, for example, Thermopile (sensor_sup = 10BIN) withtypical internal resistances >60kΩ.

If multiple failures are detected leading to analog outputs that would be contradictory to each other, the highsignal is always provided. The effective absolute, analog diagnostic-output level is constant for lower and upper
diagnostic signal output. This absolute level may vary from IC to IC slightly. Hence, the effective lower and upper
level for the absolute AOUT signal in the event of a valid diagnostic and failure event, respectively, are notinfluenced by any diagnostic-related setup in NVM nor by calibration coefficients, etc., per the Aout_setup bit
field in register 04HEX in NVM (see Table 35). However, the threshold (i.e., the sensor-signal-valid maximum forthe upper and minimum for the lower diagnostic band) can be programmed and adjusted via proper calibrationand the diagouten bit in register 04HEX.

Feb.2.24

Page 26

ZSSC3241

Table 18.

Datasheet

Information Assignment for CHECK_DIAG Command: Output Register diagnosticreg [15:0]

Meaning
No Error / Fault
Fault information improved sincelast status information
Loss of sensor positive
connection, INP
Loss of sensor negative
connection, INN
Signal at INP pin out of range(leaking / short to VSS or VDDB)
Signal at INN pin out of range(leaking / short to VSS or VDDB)
Sensor short (INN = INP)TEXT pin open
Signal at TEXT pin out of range(leaking / short to VSS or VDDB)TEXT pin short to INN
SSC Calculation Unit saturation
Memory error, checksum-check
failureTEXT pin short to INP
Die crack / chipping check failure

Connection Check
Content

DAC
OutputYes

From SSC
–

Yes
Yes

15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

0

0

0

2
–1
0007HEX
0007HEX

0
0

0
0

0
0

0
0

0
0

0
0

0
0

0
0

0
0

0
1

1
0

0
0

0
0

0
0

0
0

0
0

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0007HEX2dacres – 1
0007HEX

0
0

0
0

0
0

0
0

0
0

0
0

0
1

1
0

0
0

0
0

0
0

0
0

0
0

0
0

0
0

0
0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

0

0007HEX2dacres – 1

0
0

0
0

0
1

0
0

1
0

0
0

0
0

0
0

0
0

0
0

0
0

0
0

0
0

0
0

0
0

0
0

2dacres – 1
dacresYes

2dacres

Yes
Yes
Yes
Yes
Yes
Yes
No
No
Yes
No

Bit-Number

2

–1
–1

2dacres – 1
dacresIf a bit reset, i.e. a change from 1BIN (FAULT) back to 0BIN (NO-FAULT), for any bit occurs, diagnosticreg[0] is set
in order to signal an improvement of fault states during the ZSSC3241 operation. This is especially relevant for
Cyclic Mode and Continuous Analog-Output Mode operation.
The select_checks bit field in NVM register 21HEX 1 can be programed to select which (analog) checks are
executed and/or signalized when the UPDATE_DIAG command is triggered or when a connection check is
performed during Cyclic Mode operation. Checks that are not selected do not result in diagnosticreg register
updates and are not signalized at the DAC and AOUT output.

6.4

Digital Interfaces

The ZSSC3241 supports three different digital interface protocols: SPI, I2C, and OWI. The implementation of theinterfaces is such that the available commands (section 6.6.1) and request codes for the ZSSC3241 are thesame regardless on the interface type used.
The selection of whether the ZSSC3241 operates with SPI, I2C, or OWI interface is determined in the start-up
phase after power-on. Initially all interface relevant parameters are loaded from address 02HEX in the NVM (slave
address, SPI configuration). If the first command after power-on is a valid and properly formatted I2C request
including the correct slave address, the interface is fixed as an I2C slave. If, instead, there is an active signal at
the SS pin as the first valid activity, then the IC is fixed as an SPI slave. Alternatively, a valid OWI start (within
the start-up window) will fix the interface as OWI. Once the interface is established and fixed, a change of theinterface can only be done by means of a power-on-reset; applying signals or protocol of the assumed-inactive
interfaces must not happen.
Note: When the active interface is I2C and an active SS-signal (for example, SS==0, when “active low” isconfigured with SS_polarity=0BIN) is applied, the IC can become unresponsive, which can be only resolved by an
IC-reset.
The status byte defined in Table 19 is common for all supported interface types, and it is part of the ZSSC3241’s
digital response to read requests.

1

Recommendation for current loop applications: To minimize the effect of varying current draw in current loop applications, do not perform
short-connection checks (sens_short_check, text_inn_short_check, text_inp_short_check).

Feb.2.24

Page 27

ZSSC3241

Datasheet

Table 19.

General Status Byte

Bit-Number

70Meaning

Table 20.

6

5Powered?

4

3

Busy?

Mode

2

1

0

MemoryError?

Connection
Check
Fault?

Math
Saturation

Mode Status
Status[4:3]

Mode

00
01
10
11

Command Mode
Cyclic Mode
Sleep Mode
Renesas reserved

Note: If the latest command request is a mode change (for example, START_CM) and the previous activity wasan SSC-measurement (for example, in Cyclic Mode) in which a Math Saturation occurred, then bit[0] of thestatus byte can still be 1BIN for the response to the mode change command.
6.4.1.

SPIThe SPI interface mode is available if the first interface activity after ZSSC3241 power-up is an active signal at
the SS pin. The polarity and phase of the SPI clock are programmable via the CKP_CKE setting in bits [11:10] inaddress 02HEX as described in Table 35. CKP_CKE is two bits: CPHA (bit 10), which selects which edge of
SCLK latches data, and CPOL (bit 11), which indicates whether SCLK is high or low when it is idle. The polarityof the SS signal and pin are programmable via the SS_polarity setting (bit 9).
The different combinations of polarity and phase are illustrated in Figure 6 and Figure 7. See Table 21 for thetiming parameters.
CPHA=0SCLK (CPOL=0)

SCLK (CPOL=1)

MOSI

MSB

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

LSB

MISO

MSB

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

LSB

/SS
SAMPLE

tssd

tssa
Figure 6.

Feb.2.24

SPI Configuration CPHA=0

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ZSSC3241

Datasheet

CPHA=1SCLK (CPOL=0)

SCLK (CPOL=1)

MOSI

MSB

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

LSB

MISO

MSB

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

LSB

/SS

SAMPLE

tssa

tssd

Figure 7.

SPI Configuration CPHA=1

In SPI Mode, each command except NOP is started as shown in Figure 8. After the execution of a command(busy = 0), the expected data can be read as illustrated in Figure 9 or if no data are returned by the command,
the next command can be sent. The status can be read at any time with the NOP command (see Figure 10).
Note: If SS and SCLK do not end after one complete read-response cycle, but continue for any reason, theZSSC3241 will start repeating; e.g. the measurement result data would repeat in the following sequence(comparable to the OWI response shown in Figure 18):
Status → SensorData [23:16] → SensorData [15:8] → SensorData [7:0] → TempData[23:16] → TempData[15:8]→ TempData[7:0] → SensorData [23:16] → SensorData [15:8] →...

Command Request
MOSI

Commandother thanNOP

CmdDat<15:8>

CmdDat<7:0>

MISO

Status

Data

Data

Note: A command request always consists of 3 bytes. If the command is shorter, thenit must be completed with 0 s. The data on MISO depend on the preceding command.

Figure 8.

SPI Command Request

Read Data(a) Example: after the completion of a Memory Read command
MOSI

Command
= NOP

00HEX

00HEX

MISO

Status

MemData<15:8>

MemData<7:0>(b) Example: after the completion of a Measure command (AAHEX)MOSICommand
= NOP

MISO

Status

00HEX

00HEX

00HEX

00HEX

00HEX

SensorData SensorData SensorData TempData TempData TempData<23:16><15:8><7:0><23:16><15:8><7:0>

Figure 9.

Feb.2.24

00HEX

SPI Read Data

Page 29ZSSC3241

Datasheet

Read Status
MOSI

Command
= NOP

MISO

StatusFigure 10. SPI Read Status
Table 21.

SPI Interface Parameter

Note: See important table notes at the end of the table.
SymbolfSCLK
DSPI
Vhigh,SPI
Vlow,SPI
SRSPI
tssa

tssd

tss
IMISO
[a]

Parameter

Conditions

Interface clock
Duty cycle
Input high level voltage
Input low level voltage

Minimum

TypicalMaximum

Units

0.05
40
-

1
50
VDD - 0.7

12
60
-

MHz
%
V

Referenced to external
supply voltage VDD(maximum 5.5V)

Input rising and falling edge slew rate
Delay time [a] between SS-activationedge and first edge of SLCK, MOSI or
MISO
Delay time [a] between SS-deactivationedge and last edge of SLCK, MOSI or
MISO
Delay between SS-deactivation edge oflast command and of SS-activation edge
for next command
Driving current of SPI output (peak)

-

0.7

-

V

0.26

–

1

V/ns

170

300

–

ns

1

50

–

ns

10

–

–

µs

–

40

180

mA

“Typical” is for
fSCLK ≤ 3.4MHz operation

Typical: For conditions with no clocks prior and after the command and data bytes, the maximum values for t ssa and tssd are not
relevant.

6.4.2.

I2C

I2C Mode is selected if the first interface activity after the ZSSC3241 power-up is an I2C command with valid
slave address. In I2C Mode, each command is started as shown in Figure 11. Only the number of bytes that areneeded for the command must be sent. An exception is the I2C High Speed Mode where 3 bytes must always
be sent as in SPI Mode. After the execution of a command (busy = 0), the expected data can be read as
illustrated in Figure 12 or if no data are returned by the command, the next command can be sent. The status
can be read at any time as described in Figure 13.
Command Request (IC Write)
From master to slave

S

START condition

From slave to master

P

STOP condition

A

AcknowledgeN

Not acknowledge

S SlaveAddr 0 A Command A P

write

S SlaveAddr 0 A Command A

CmdData<15:8>A

CmdData
<7:0>

A P

write

Figure 11. I2C Command Request

Feb.2.24

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Datasheet

Read Data (I2C Read)(a) Example: after the completion of a Memory Read command
S SlaveAddr 1 A

StatusA

MemData<15:8>A

MemData
N P
<7:0>

read

(b) Example: after the completion of a Measure command (AAHEX)S SlaveAddr 1 A

StatusA

SensorData
SensorData
SensorData
TempData
TempData
TempData
A
A
A
A
A
N P
<23:16><15:8><7:0><23:16><15:8><7:0>

read

Figure 12. I2C Read Data

Read Status (I2C Read)
S SlaveAddr 1 A

StatusN P

read

Figure 13. I2C Read Status
Table 22.
SymbolfSCL
DSPI
Vhigh,I2C
Vlow,I2C

I2C Interface Parameter
Parameter
Interface clock
Duty cycle
Input high level
voltage
Input low level
voltage
Capacitive load at
input pin, SDA

CSDA

IOL

Low level output
current

Conditions

Referenced to external supply
voltage VDD.

100pF: maximum for Standard andFast Mode; in HS ModefSCL,max = 3.4MHz
400pF: only in HS Mode;fSCL,max = 1.7MHz
VSDA=0.4V; Standard and Fast
Mode with 400kHz; 400pF load

Minimum

TypicalMaximum

Units

0.1
33

–
–

3.4
50

MHz
%

-

VDD - 0.7

-

V

-

0.7

-

V

–

100

400

pF

3

6

40

mA

Details for timing and protocol of the ZSSC3241-supported I2C communication in Standard Mode, Fast Mode,and High-Speed Mode are given in I2C-Bus Specification, Rev.6, UM10204.

Feb.2.24

Page 31ZSSC3241

6.4.3.

Datasheet

One-Wire-Interface, OWIThe ZSSC3241 employs a one-wire digital interface concept (OWI). It combines a simple and easy protocol
adaptation with a cost-saving pin sharing. The communication principle of the OWI interface is derived from theI2C protocol.
OWI-Slave

ZSSC3241OWI-Master
Dynamic Driving,switch-on only
during OWI-SlaveOutput phases

5µA

ROWI,PULLUPAOUTROWI,LINE
COWI,LINE

VSS

Figure 14. General Block Schematic of the OWI Interface

Both the analog output signal and the digital OWI interface use the same pin, AOUT. An advantage of the OWI isthat it enables “end of line” calibration – no additional pins are required to digitally calibrate a finished assembly.
Although the OWI is integrated mainly for calibration, it can also be used to read out the calibrated sensor signal
continuously or retrieve diagnostic detail information.
The OWI protocol is defined as follows:•

Idle State: During inactivity of the bus, the OWI line is pulled up to the supply voltage V DD by an external
resistor.

•

Start Condition: When the OWI line is in idle mode, a low pulse with a minimum width of t OWI,START ≥ 10μs andthen a return to high indicates a start condition. Every request must be initiated by a start condition sent by amaster. A master can generate a start condition only when the OWI line is in idle mode.

•

Valid Data: Data is transmitted in bytes (8 bits) starting with the most significant bit (MSB). Transmitted bits
are recognized after a start condition at every transition from low to high at the OWI line. The value of thetransmitted bit depends on the duty ratio between the high phase and high/low period (bit period, tOWI,BIT in
Figure 15). A duty ratio greater than 1/8 and less than 3/8 is detected as 0; a duty ratio greater than 5/8 andless than 7/8 is detected as 1. The bit period of consecutive bits must not increase to more than 1.5 times theprevious bit period or decrease to less than half of the previous bit period because a stop condition is detectedin this case.

The length of the OWI-line and the size of ROWI,PULL (if it is statically connected to AOUT), and consequently theresistive and capacitive load influence the maximum possible interface speed and minimum Bit period,
respectively. Further, it can be beneficial for harsh EMC conditions to intentionally add capacitance to the OWI1(AOUT) line in order to improve RF disturbance robustness. Table 23 shows some practical OWI-interface
dimensioning examples and the resulting maximum signal frequencies (minimum possible Bit periods). The
complete ZSSC3241’s OWI interface properties and timing capabilities are given in Table 24.
Table 23.

OWI Dimensioning Examples
ROWI,PULL(+ ROWI,LOAD)

1.8 kΩ

2.5 kΩ

3.3 kΩ

5.5 kΩ

10.0 kΩ

20µs
113µs
249µs
373µs
497µs
576µs

20µs
157µs
345µs
518µs
691µs
801µs

21µs
207µs
456µs
684µs
912µs
1057µs

35µs
345µs
760µs
1140µs1520µs1760µs

63µs
628µs
1381µs2070µs2762µs3205µs

COWI,LOAD [a]
1nF
10nF
22nF
33nF
44nF
51nF
[a]

Examples are shown with statically connected ROWI,PULL, and with minimum bit period: tOWI,BIT.

Feb.2.24

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Datasheet

OWI protocol timing and parameters are specified in Figure 15, Figure 16, and Table 24.

Start

1

0

0

tOWI,STARTtOWI,0tOWI,BIT

1

StoptOWI,STOP

tOWI,1Start

tOWI,IDLE

Figure 15. OWI Timing Diagram

Note: Configuration for SSF1 register 03HEX in NVM (see Table 35) to allow continuous OWI and concurrent
analog output: owi_off = 0, cont_ANAoutn = 0, owi_su_case = 1.

Start

1

0

tOWIextraH

tOWIextraL

tOWI,STARTtOWI,BIT

Figure 16. OWI Extra (Activation) Pulse for Concurrent OWI and Analog Output Configuration
Table 24.

OWI Interface Parameters

SymbolParameter

tSUlength

OWI start-up “listening”
windowtOWI,IDLE

Bus free time between
START and STOP
condition

tOWI,START

Hold time for START
condition

tOWI,BIT

Bit period, bit time

tOWI,0tOWI,1

Duty ratio bit ‘0’
Duty ratio bit ‘1’

tOWI,STOP

Hold time STOP conditiontOWI_BIT_DEV

Bit time deviationtOWIextraL

Length of extra pulse [a]Duration of HIGH after
Aout-to-OWI extra pulse

tOWIextraH
COWI,LOAD

Capacitive load at OWI
line

ROWI,PULL

Pull-up resistance –master [b]ROWI,LOAD

Resistive OWI line load

VOWI,inL
VOWI,inH

Voltage level LOW
Voltage level HIGH

Feb.2.24

Conditions
Programmable window length , see
owi_su_length, bit[2] in SSF1
register
For Cyclic and Command Modeoperation
Minimum in ZSSC3241 Sleep Modeoperation

Robust operation with:
tOWI,BIT ≥ 10  ROWI,PULL  COWI,LOAD

tOWI_BIT_L is the bit period of the lastvalid bit
Duration of most recent bit versus
previous bit durationOWI configuration to allow
continuous OWI and concurrent
analog output; see Figure 16.
Minimize COWI,LOAD if ratiometric
DAC-output, Aout_setup = 001BIN isconfigured for AOUT/OWI1
If ROWI,PULL values greater than
3.3kΩ were applied, the shortest
tOWI,BIT times cannot be achieved
anymore.
If ROWI,LOAD>35Ω, OWI-timing
parameter (tOWI,*) low-limits, i.e.
highest speeds are not guaranteed.

Minimum

TypicalMaximum

Units

–

–

50

ms

30

–

µs

20µs

0.5 ×
tOWI_BIT

–

µs

20

40

3000

µs

0.125
0.625

0.25
0.75

0.375
0.875

tOWI_BITtOWI_BIT

1.5

3

0.55

1.0

1.45

tOWI_BIT

43.5

–

49.5

µs

43.5

–

–

µs

0.05

2.2

66

nF

1.8

2.5

3.3

kΩ

0

0.01 xROWI,PULL

–

Ω

–
0.80

0.1
0.9

0.25
–

VDD
VDD

1
20

tOWI_BIT_L

Page 33

ZSSC3241

SymbolVOWI-S,LOW[a][b]

Datasheet

Parameter
Slave output level LOW

Conditions

Minimum

TypicalMaximum

Units

–

–

0.1

VDD

Open drain output at AOUT pin,max. allowed current draw 5mA,
otherwise: VOWI-S,LOW >0.1*VDD

To switch from analog output to “OWI listen” at AOUT pin.
For the selection of ROWI,PULL, the minimum current limit of the AOUT buffer and maximal VDD supply must take into account if
OWI and analog output voltage mode are set up to work concurrently; that is owi_off = 0, cont_ANAoutn = 0, and owi_su_case = 1.
If the current limitation condition (IOUTmax, see Table 4) is exceeded, it is recommended to use the Dynamic Driving Approach for
ROWI,PULL at the OWI-master, and only switch the ROWI,PULL to AOUT when the OWI-master starts communication. This setting is
specifically recommended for the phases when the OWI-master listens to the AOUT-line, and the OWI-slave (the ZSSC3241) has
to respond, respectively.

The effective OWI properties depend on the load conditions at the OWI1 pin. Additional to Table 23, somefurther applicable configurations are as follows:•

For maximum operation speed (50kHz) of OWI1, the capacitive load, C OWI,LOAD can be up to 1nF and the
maximum ROWI,PULL is 2.5kΩ.

•For high operation speed (10kHz) of OWI1, the capacitive load, C OWI,LOAD can be up to 4.7nF and ROWI,PULL
must be ≤ 3.3kΩ.

•For an equivalent frequency of 1kHz of OWI1, it should be ensured that C OWI,LOAD ≤ 22nF and ROWI,PULL ≤ 7kΩ,or for example that COWI,LOAD ≤ 66nF combined with ROWI,PULL ≤ 4.5kΩ.
Example 1: OWI Request, 1 Command Byte, 1 Data Word:

Optional

S 6 5 4 3 2 1 0 W 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 S

Slave Address [6:0]

Data Byte

Data Byte

Command Byte [7:0]

Data Byte

Data Word [15:0]

Example 2: OWI Request, 1 Command Byte, no Data:
S 6 5 4 3 2 1 0 W 7 6 5 4 3 2 1 0 S

Slave Address [6:0]

S Start condition

S StopRead/write bitW(write = 0)

condition
Data bit2(example: Bit 2)

Data Byte
5

Command Byte [7:0]
Sent by

Slave address(example: Bit 5)

MasterFigure 17. OWI Command Request

Feb.2.24

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Datasheet

Example: OWI Read Operation, Status Byte (+n) Data Bytes*:
Response data is sent in a loop, i.e. repeated until master generates stop condition

Optional
S 6 5 4 3 2 1 0 R 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 ... 7 6 5 4 3 2 1 0 S

Slave Address [6:0]

Status Byte [7:0]

Data Byte [7:0]...nth Data Byte

* n data bytes could be:
NVM read: 2 bytes,
Measure: 6 bytes,
Get_Raw: 3 bytes

Sent byMaster

S Start condition

Slave
S Stop condition

R

Read/write bit(read = 1)

5

Slave address(example: Bit 5)

Master2

Data bit(example: Bit 2)

Figure 18. OWI Response by ZSSC3241

The ZSSC3241 allows utilization of the OWI interface in different application configurations:•OWI Disable: The OWI interface can be deactivated by owi_off = 1 (bit[13] in SSF1 register 03HEX). For
example, this could be applied in cases when an analog-output smart sensor is configured and calibratedusing the OWI interface and the OWI will not be available after calibration and final setup/programming.

•OWI Only (no analog output): With the NVM configuration owi_off = 0 and cont_ANAoutn = 1, the AOUT will
not provide any analog outputs and is only used as the OWI pin. There is no startup window limitation(owi_su_length is ignored by the ZSSC3241). If the first (valid) digital interface activity is the Startup OWI(D2HEX) command, the ZSSC3241’s interface type will be fixed as OWI communication (SPI and I2C will bedisabled/ignored).

•OWI with Startup Window and Analog Output: The OWI startup window followed by subsequent activationof the analog output is possible with owi_off = 0, cont_ANAoutn = 0, and owi_su_case = 0. AOUT works as a(listening) OWI signal pin after power-up until the selected startup window (owi_su_length) has elapsed. If theStartup OWI (D2HEX) command is received within the startup window, AOUT persists as the OWI
communication pin until a power-on reset occurs. If the ZSSC3241 does not receive theStartup OWI command (D2HEX) during the startup window, the OWI interface will be disabled and AOUT starts
functioning as an analog output.

•

Continuous OWI and Analog Output: The configuration owi_off = 0, cont_ANAoutn = 0, andowi_su_case = 1 results in AOUT providing analog output levels as soon as they are available after power-up(in Cyclic Mode). Concurrently, the OWI listens to the AOUT 1 pin in order to check for valid OWI commands.
The OWI still needs to be enabled by means of the Startup OWI command. The physical protocol in thisconfiguration requires an extra pulse (see Figure 16) prior the Startup OWI command. After the release of theextra OWI initialization pulse, the analog output is switched off 2 and AOUT becomes the OWI I/O pin until the
OWI startup window (according to owi_su_length) has elapsed.
The OWI-master implements Dynamic Driving to avoid dynamic currents (due to DAC-output level changes)
causing unwanted pull-up signal generation (via ROWI,PULL). When Dynamic Driving Approach is not applied inthis configuration, set the constantly connected OWI-master pull-up resistances (ROWI,PULL) to ≥5.5kΩ toprevent erroneous OWI-start detections that can be triggered by changing DAC-output levels. Limit theinterface speed to slower values with the proper setting, such as longer bit period.

1

Dependent on Aout_setup, OWI2 is the alternative input pin, e.g., in the case of the current loop setup, i.e. the Aout_setup bit field = 000 inregister 04HEX.
The DAC switch-off time point is variable and depends on the activity status in the measurement cycle, measurement execution, etc. It canbe anytime between the extra-pulse and a received, completed Startup OWI command.

2

Feb.2.24

Page 35ZSSC3241

6.5

Datasheet

Measurement and Output Options

Sensor or diagnostic measurement results of the ZSSC3241 can be provided in both domains, digital andanalog. Any of the supported digital interfaces and output options can be used as the only active interaction
path, or it can be combined with any of the analog output configurations. For digital communication, only one
interface type can be active and supported (see section 6.4).
Digital communication via SPI and I2C are fully independent of the configuration and application of theZSSC3241’s analog outputs. For digital OWI communication combined with analog output, special application
circuits and constraints might have to be considered, as the OWI interface and the analog outputs use the same
pin, AOUT.
6.5.1.

Single Measurements, Digital Raw Results, and SSC Results

The IC generates digital raw values, which are processed by the ZSSC3241 internal main math core generating
the SSC-corrected (linearized, temperature-compensated) output signal. See section 6.6.3 for details about the
SSC math, etc. In addition to the SSC-corrected digital measurement results, the ZSSC3241 can provide raw
values without SSC correction for evaluation and/or calibration purposes. The respective results are provided at
the digital interface as a 24-bit wide data word. Raw values and SSC results are MSB-aligned. Raw values areformatted as two’s-complement, whereas SSC results are formatted as unsigned absolute value.
Table 25.
Bit-Number
Meaning,
Weighting

Table 26.
Bit-Number
Meaning,
Weighting

Data Format of Raw ADC Readings
23

22

21

20

…

2

1

0

0

-1

-2

-3

…

-21

2

-22

2

2-23

-2

2

2

2

Data Format of Corrected, SSC Results (S and T)
23

22

21

20

…

2

1

0

0

-1

-2

-3

…

-21

-22

2-23

2

2

2

2

2

2

The ZSSC3241 can process and digitize the following signals:•

SM: Direct sensor signal inputs; i.e., perform sensor measurements•

AZS: Auto-zero signals for the sensor channel•

TM: Direct temperature signal inputs, i.e. perform temperature measurements•

AZT: Auto-zero signals for the temperature channel

The internal sequence (in time) of A2D-conversions with both auto-zero measurements enabled is: first is AZS,
second is SM, third is AZT, and forth is TM. The utilization of auto-zero measurements allows further
optimization and reduction of the noise level for the sensor signal in combination with the inherent compensationof the residual offsets of the analog sensor front-end. If an auto-zero measurement is enabled, then the sensor
signal remains the input for the auto-zero measurement with the gain and ADC set up as for the original signal
measurement, but with swapped inputs and offset configurations of the PGA and ADC such that the following
holds for the resulting raw value:•Sensor raw value with auto-zero: S_raw = 0.5  (SM – AZS)•

Temperature raw value with auto-zero: T_raw = 0.5  (TM – AZT)The application benefits with enabled auto-zero measurements are•

ZSSC3241 front-end offset cancellation – residual signal degradation1 or drift for the application is eliminated•Improvement of the signal-to-noise ratio for the raw or SSC-corrected output signal

1

Worst-case IC-offset drift is < 2ppm/day at 125°C.

Feb.2.24

Page 36ZSSC3241

Datasheet

On the other hand, the default application benefit without auto-zero measurements is an approximately 50%
faster output update rate compared to an equivalent configuration with enabled auto-zero measurements.
Recommendations: For applications where a faster update rate is the priority, disable and not apply the autozero measurements. For applications where a better signal-to-noise level and maximum signal quality are thepriority, enable and apply the auto-zero measurements.
The NVM configuration and measurement-request commands can be used to select which measurements are
performed, processed, and provided at the digital interface. See Table 34 for command details.
Examples of options for a single measurement request and output:•

SSC-corrected sensor readings (requested by the Measure command AAHEX) generating an output of SSCcorrected, 24-bit sensor data followed by SSC-corrected, 24-bit temperature data.

•

Raw sensor measurement with or without auto-zero correction (requested by the Raw Sensor Measurecommand A2HEX) generating an output of raw 24-bit sensor data.

•

Raw temperature measurement with or without auto-zero correction (requested by the Raw Temperature
Measure command, A4HEX) generating an output of raw 24-bit temperature data.

The auto-zero measurements can be disabled/enabled via the AZMs_on and AZMt_on bits in NVM registers
04HEX (see Table 35).
Table 27 and Table 28 provide some exemplary, typical conversion times and noise performance values for the
ZSSC3241’s Front-End (PGA and ADC) in order provide some guidance for understanding effects and signalquality-related consequences while defining an application setup.
Table 27.

Typical Conversion Times for Complete SSC Sensor Measurements: SM, TM

ADC Resolution (Main) Sensor
12
14
14
16
16
18
24
[a]

ADC Resolution Temperature Sensor

Typical Measurement Duration [ms] [a]12 (external temperature sensor)
13 (internal temperature sensor)
14 (external temperature sensor)
14 (external temperature sensor)
16 (external temperature sensor)
18 (external temperature sensor)
24 (external temperature sensor)

0.40
0.49
0.55
0.69
0.82
1.42
9.49

The time from the end of the SSC-measurement command request AAHEX to signalization for the end-of-conversion at the EOC pin
with the ZSSC3241 in Command Mode; INT_setup bit field = 00BIN in register 02HEX (see Table 35); 25°C; VDD=5V; AZMs_on = 0BIN;
and AZMt_on = 0BIN.
The data is shown with ZSSC3241 default NVM configuration.

Table 28.

Typical Conversion Times and Noise Performance for Complete SSC Measurements

ADC Resolution:
External Sensor [Bits]
12
12
16
16
20
20
24
24

Reference Source for External
Sensor (sel_ref1)
Absolute, sel_ref1=0
Ratiometric, sel_ref1=1
Absolute, sel_ref1=0
Ratiometric, sel_ref1=1
Absolute, sel_ref1=0
Ratiometric, sel_ref1=1
Absolute, sel_ref1=0
Ratiometric, sel_ref1=1

Typical 3-sigma Noise for SSCCorrected (Digital) Output [b], S, T
5 LSB12Bit
7 LSB12Bit
26 LSB16Bit
51 LSB16Bit
182 LSB20Bit
270 LSB20Bit
1122 LSB24Bit
1354 LSB24Bit

Typical Measurement[a]Duration [c] [ms]
0.8
1.3
2.9
9.8

[a]

Measurements including AZS, SM, AZT, TM with internal temperature measurement.

[b]Reference noise values normalized to the respective external sensor’s ADC resolution, obtained with the following setup:10kΩ sensor bridge, 25°C, Gain=28, VDD=3.3V, ioffsc=00000 for sel_ref1=1, ioffsc=01111 for sel_ref1=0, adc_en_shift=0,
pga_en_shift=0, sensor_sup=00, cp_off=0.

[c]

The time from the end of the SSC-measurement command request AAHEX to signalization for the end-of-conversion at the EOC pin
with the ZSSC3241 in Command Mode; INT_setup bit field = 00BIN in register 02HEX (see Table 35).

Feb.2.24

Page 37ZSSC3241

Datasheet

Cyclic, Continuous, Repeated Measurements – Measurement Scheduler

6.5.2.

In addition to single measurement requests, such as AAHEX, or the Oversample-x Measure requests (ACHEX to
AFHEX; see Table 34), the ZSSC3241 can be configured for cyclic measurement sequences. The continuously
running measurement sequence consists of individual measurement slots in which all or a selectable subset ofmeasurements and checks can be scheduled and allocated including sensor measurement (S), auto-zeromeasurement for the sensor (AZS), temperature measurement (T), auto-zero measurement for temperature(AZT), and diagnostic checks (see section 6.3). If AZS is enabled (AZMs_on = 1BIN in register 04HEX;
see Table 35 for details for registers), the sensor measurement (S) and auto-zero measurement for the sensor(AZS) must be scheduled to always occur together for correct signal processing; i.e., these settings are required:slots_S = slots_AZS in register 1FHEX and startS_wfirstn = startAZS_wfirstn in register 1EHEX. If AZT is enabled(AZMt_on = 1BIN in register 04HEX), the temperature measurement (T) and auto-zero measurement for
temperature (AZT) must be scheduled to always occur together for correct signal processing; i.e., these settings
are required: slots_T = slots_AZT and startT_wfirstn = startAZT_wfirstn (see registers 1EHEX and 1FHEX). For
applications where obtaining the fastest possible update rate is the highest priority, disabling the auto-zeromeasurements is recommended, i.e., AZM*_on = 0BIN, for which slot scheduling is user programmable without
constraints.
The automatically, continuously running measurement sequence is executed in Cyclic Mode, which is either
entered as the default main operating mode after power-on or entered by means of the START_CYC command,
ABHEX.
Figure 19 shows an example of the measurement sequence configurability. During the pauses in the sequence,
the ZSSC3241 signals that it is not busy (i.e., the Busy? bit = 0BIN in the general status byte; see Table 19). The
available measurement results are updated at the end of each SSC calculation and output operation and are
kept valid at the digital interface or DAC output until the next SSC calculation and output operation.
The configuration of the measurement scheduler is done in the NVM registers 1E HEX to 20HEX.
Measurement example with the following requirements:▪

S every slot, start with first▪

No AZS (AZMs_on = 0BIN)▪

T every 7 slots, start with first▪

AZT every 7 slots, start with first▪

Sensor Connection Check every 10 slots, no start with first slot

Individual Measurement Slot Numbers

SSC Calculation & Out(Bridge) Sensor
Measurement

Pause: Cyc_Period

10

SSC Calculation & Out

Sensor Connection
Check(Bridge) Sensor
Measurement

9

Pause: Cyc_Period

SSC Calculation & Out(Bridge) Sensor
Measurement

Pause: Cyc_Period

SSC Calculation & Out

8

Temperature Sensor
Measurement

Auto-Zero Tempe-rature
Measurement(Bridge) Sensor
Measurement

Pause: Cyc_Period

7

SSC Calculation & Out(Bridge) Sensor
Measurement

Pause: Cyc_Period

6

SSC Calculation & Out(Bridge) Sensor
Measurement

Pause: Cyc_Period

5

SSC Calculation & Out(Bridge) Sensor
Measurement

Pause: Cyc_Period

4

SSC Calculation & Out(Bridge) Sensor
Measurement

Pause: Cyc_Period

3

SSC Calculation & Out(Bridge) Sensor
Measurement

Pause: Cyc_Period

2

SSC Calculation & Out(Bridge) Sensor
Measurement

Pause: Cyc_Period

SSC Calculation & Out

1

Temperature Sensor
Measurement

Auto-Zero Tempe-rature
Measurement(Bridge) Sensor
Measurement

Power-On, Cyclic
Measurements Start

0

...

Time

Figure 19. Example Configuration for the Measurement Scheduling and Cyclic Mode Operation

A slot denotes all measurements that are conducted and updated before the next SSC calculation. There can bepauses from one slot to the start of the next slot. The first slot has the slot number 0.
If the digital interface clock speed is too slow or contains long no-read pauses related to the SSC output update
rate in Cyclic Mode, intermediate results can be lost.
In Cyclic Mode, the present data word (measurement result) at the interface output is always the latest data .
See Figure 20 for relatively slow interface polling compared to the internal measurement data update rate in
Cyclic Mode.

Feb.2.24

Page 38ZSSC3241

Datasheettime

IC-internal operation

ADC/SSC: measuredata 1

measurement result
generation

ADC/SSC: measuredata 2

ADC/SSC: measuredata 3ADC/SSC: measuredata 4

result not read at interface,
Lost Information

Data availability at

result at digitalinterface: data1

Digital Interface
for result data polling

result at digitalinterface: data 2

result at digitalinterface: data3

time between 2 subsequent reads longer than time to get
next ADC/SSC result update  intermediate data lost

data read at interface

data read at interface

Figure 20. Measurement Result Output Update in Cyclic Operation (with “Slow” Interface Polling)

Note: When a mode change request (START_CM, START_SLEEP) is received relatively close to the IC internal
output register update in Cyclic Mode, the request is acknowledged and the latest measurement result generated
during the cyclic operation may not be present at the interface. It is recommended to read out the last measurement
result directly before the mode change.
6.5.3.

Analog Outputs: Digital-to-Analog Converter (DAC)

The integrated, programmable digital-to-analog converter (DAC) generates an IC-internal analog signal that canbe output at AOUT as an absolute voltage, VDD-ratiometric voltage, or control signal for an externally connectedcurrent loop circuit. The analog output must be configured by Aout_setup in the SSF2 register, 04HEX.
side-input by
DAC-Diagnostic, B3HEX

bit[0]

bit[15]DAC-SSC andClipping Unit

T or S

Digitial Control
and Math Core

DAC-Input Register

D
A

...

truncated

AOUT

SSC-Result Regist er

T or S
either / or

Aout_setup

13-16Bit

MUXOU T

ADC raw results

setup dependent

bit[23]

bit[8]

FB

bit[0]

Figure 21. DAC and Analog Output Topology

The ZSSC3241 provides only analog outputs for signals that are processed by the SSC calculation unit (seesection 6.6.3), that are post-processed by the DAC-SSC correction and Clipping unit, or that are directlytransferred (via the digital command, DAC Diagnostic, B3HEX; see Table 34) as input to the DAC; e.g., for test or
calibration purposes.
Note: OWI does not support the DAC Diagnostic feature, it is only applicable with the interfaces I2C and SPI.
The setup parameter dacouttype, bit[3] of the SSF2 register, 04HEX defines if either the SSC-corrected sensor
value, S, or the SSC-corrected temperature value, T, is provided at AOUT; see Figure 21.
Table 29.

DAC Configurations
dacresbit[1]

bit[0]

0
0
1
1

0
1
0
1

Feb.2.24

Applied DAC Resolution

Maximum DAC Output Voltage tDACsettle Settling Time [a]13-Bit14-Bit15-Bit16-Bit

150µs
160µs
180µs
200µs

Page 39ZSSC3241

Datasheetdacresbit[1][a]Applied DAC Resolution

bit[0]

Maximum DAC Output Voltage tDACsettle Settling Time [a]tDACsettle is the step-response time for the DAC and analog output stage (only); i.e., the time to reach 99% of the new analog output
level after a DAC input change. For analog-output smart-sensor step-response time, the time for generating a new SSC-result as
input to the DAC must also be considered.

For the suppression of spuriously emitted tones in the analog output signal, dithering within the DAC operation
can be enabled/disabled via the dither_off bit in the SSF2 register. If spurious tone emission is irrelevant in theapplication, dithering can be switched off in order to improve the analog output signal’s noise level.
For analog diagnostic level signalization, enabled by the diagouten bit = 1BIN in the SSF2 register (see Table 17),
the ZSSC3241 directly ties the analog output signal to 0% or 100% with the selected output stage, supported bydigital pre-scaling to reserve approximately 1.5%-wide signal bands for diagnostic outputs. Strong
recommendation: If the ZSSC3241 provides diagnostic levels, activate analog signalization of diagnostic levels
before sensor calibration.
6.5.3.1.

Programmable Clipping Limits for the Digital-to-Analog Converter

The DAC allows programming a lower and upper clipping limit (Low_Clip_Lim and Up_Clip_Lim bit fields
respectively; see Table 35) for the output signal. The main SSC-corrected output value (sensor signal S ortemperature signal T – selectable by dacouttype bit) is compared against the 16-bit value formed by{Up_Clip_Lim[15:0],00000000BIN} for the upper limit and against {Low_Clip_Lim[15:0],00000000BIN} for the lower
limit. If the calculated bridge value is higher than the upper limit or less than the lower limit, the analog output value
is clipped to this limit value, see Figure 21.
The high/low-clipping functions can be enabled by the clipping_on bit field in the NVM-register 24HEX.
The enabled clipping function is not applied (regardless on the setup in clipping_on) in the following cases:▪

if the DAC Diagnostic command B3HEX is used to force a certain DAC-output▪

if enabled diagnostic checks (diagouten=1BIN) detected a Diagnostic State, that is signalized at the AOUT
pin, see Table 17.

The clipping is performed in the same sub-block of the IC as the separate correction of the Digital-to-Analog
converter characteristic (DAC-SSC), see section 6.6.3.3. DAC-SSC can be applied to allow for post-main-SSC
correction of a gain and offset factor allowing the compensation of the typical DAC-characteristic. A digital output
signal that covers the complete dynamic range can be mapped to a lower DAC output dynamic range by the DACSSC function, for example, to reserve low and upper DAC output voltage bands for diagnostic state signalization.
6.5.3.2.

Voltage Outputs

The ZSSC3241 can provide one of three direct voltage outputs at the AOUT pin. The Aout_setup bit field in the
SSF2 register (bits [7:5]; see Table 35) is used to configure the ZSSC3241 and select the analog voltage output
stage as defined in Table 30. It is also possible to set up the analog voltage output for 0V to 10V systems using
additional external components.
Table 30.

Direct Voltage Outputs
Aout_setup

bit[2]

bit[1]

bit[0]

0
0
0
0
1

0
0
1
1
0

0
1
0
1
0

1

0

1

1

1

0

1

1

1

Feb.2.24

Voltage Output (Range/Type) [a]–0 to VDD, ratiometric
0 to 1V, absolute
0 to 5V, absolute–
0 to VDD, ratiometric
0 to 1V, absolute
0 to 5V, absolute

Comments
Current loop; see section 6.5.3.4
Typical 0 to 5V; with VDD > 5V, rail-to-rail output
Any (valid) VDD
Requires VDD > 5.01V
Not assigned
Typical 0 to 5V; with VDD > 5V, rail-to-rail output,
OWI2in enabled as OWI input pin
Any (valid) VDD, OWI2in enabled as OWI input
Requires VDD > 5.01V, OWI2in enabled as OWI
input

Page 40ZSSC3241

Datasheet

Aout_setup
bit[2][a]bit[1]

bit[0]

Voltage Output (Range/Type) [a]Comments

The voltage outputs listed are directly supported, requiring minimal (for ratiometric output) or no (for absolute voltage output)
additional external devices.

Table 31.

Recommended Operating Conditions for Voltage Output

SymbolParameter

Typical Value

Unit

RLout
CLout

External, resistive load at AOUT
External, capacitive load at AOUT

1
10

kΩ
nF

6.5.3.3.

Comments
For 1kHz to 5kHz output bandwidth, as RC lowpass filter configuration.

Accuracy and Calibration of the DAC-Output

The 16-bit-DAC of ZSSC3241 is optimized from design prospective for high stability. Low drift over operational
conditions can be achieved with minimal additional effort during the calibration phase, by compensating absolute
errors/mismatches with mathematical adaptation of sensor calibration coefficients.
The functional, analog main-components of the ZSSC3241’s DAC come with some residual level of IC-to-IC
variation for DAC-characteristic’s offset and gain. It is recommended to calibrate the DAC-characteristic andconsider the linearity IC-to-IC-variation of the DAC at the IC’s calibration, especially for applications with highrequirements for absolute accuracy of the output voltage. For analog output configurations, the SSC coefficientscan be derived such that the digital SSC-results and hence the DAC’s digital input (S or T) is pre-shaped in order
to compensate the residual DAC’s (non-)linearity variation.
To avoid taking analog measurement values during the smart sensors’ calibration procedure, the ZSSC3241
provides two high-precision DAC-calibration point measurement results in the NVM, DAC10RM5V and
DAC90RM5V in the NVM registers 22HEX and 23HEX, see Table 35. Using these two high-precision DAC
calibration points for the determination of the SSC-coefficients, the ZSSC3241 achieves a low residual, absolute
DAC-output error of less than ±0.15% over the device specified temperature range, and over the DAC output
swinging from 1% to 100% of the specified range. This approach can be also interpreted as mapping of thedigital SSC-outputs (S or T) to an IC-to-IC-varying best fit straight-line characteristic of the DAC. The residual
DAC-error is typically higher in the signal range 0% to 1%, as the ZSSC3241’s does not provide exactly 0V forzero-value digital DAC-inputs, S or T.
If more than two DAC-calibration points are considered, absolute accuracies below ±0.15% become possible,
down to the analog output (AOUT) line’s noise-and-distortion level.
6.5.3.4.

Current Loop Output

The analog current loop is a typical output signal configuration, especially for industrial sensors. Using only two
wires, the sensor is supplied with power and transmits its output signal to the processing unit. With
Aout_setup = 000BIN (bits [7:5] in the SSF2 register; see Table 35), the ZSSC3241 will generate a SSC-corrected
sensor-signal-proportional control signal at AOUT that allows generating a related loop current according theapplication in Figure 22.
Table 32.
SymbolZSSC3241 Current-Loop-Specific Properties
Parameter

Typical Value

Unit

R1

Control feedback resistor,
internal

120

kΩ

RSENS

External loop-sensing resistor

50Ω

β TLOOP

Current gain of external-loop
bipolar transistor, TLOOPTransfer bandwidth of internalcurrent loop op amp.

100

Numeric

20

kHz

BWL

Feb.2.24

Comments
Combined with external RSENS, defines the current-loop
gain: R1/RSENS
R1-process-variation in the range of ±20%
Using a low-TC resistor is recommended to minimize
spurious temperature influence

Page 41ZSSC3241

Datasheet

SymbolParameter

RSENSOR,MIN

Typical Value

External sensor element’s
minimum resistance

Unit

1.6

kΩ

ILoop,highLoop-response current forlogical-1; OWI over current-loop

20…24

mA

ILoop,low

Loop-response current forlogical-0; OWI over current-loop

7…11

mA

Comments
With a ratiometric supply and resistances that are too
low, the overall current consumption (ISensor + IIC) at VDD
could exceed the 4mA low-limit for typical current loops(see Table 3 for ISensor specifications, and see Table 4 for
IIC specifications)
Effective current modulation when ZSSC3241 is OWI
slave modulating the slave-to-master response via theloop current (controlled by AOUT/OWI1), including ICactive-current draw, IIC and (typ.) 1mA load through thesensor element, Re,Tloop~150

Strong recommendation: Use the Zener diode between FB and VDD to protect the V DD line from positive overvoltage conditions and protect the FB input from negative over-voltages. The 100nF capacitor performs a lowpass-filter function for short /fast changes in the total current consumption for the sensor element plus theZSSC3241 (ISENS + IIC), such that current consumption changes do not lead to short-term fluctuations of AOUT
and the loop current.
An equivalent effect of slight loop current fluctuations might be observable if a sensor-connection check issometimes executed between the normal sensor measurements. Here, the connected sensor element, e.g., aresistive bridge, will be unsupplied briefly in order to determine the electrical connection properties; whereas an
overall load change (sensor measurements → sensor-connection check → sensor-measurement) at VDD andhence in the current loop will be present. Therefore, diagnostic features should be carefully enabled andselected for current loop applications that have strong requirements for output signal quality under any
circumstances.

ISE NSOR + IIC < 4mA !

VDD (VDD~5V)

JFET

Loop+
7 to 48VLDO Control /Regulation
detectIloop

LDOctrl

13-16 bit

D

+

A

Tloop

AOUT

-

ISE NSOR + IIC

A

100n

IDAC

Vloop

VSS

R1

Rsens
ILoop
FB

Loop4..20mA

Figure 22. Current Loop Configuration

6.5.4.

Output Interrupt Signaling

The EOC pin can be programmed to operate either as a simple “measurement busy” and end-of-conversion
transducer or as a configurable interrupt transducer, which is configured using the INT_setup[1:0] bits in NVM
register 02HEX, bits[8:7]. Further, one or two 24-bit quantized thresholds without threshold-hysteresis(eoc_hyst_on=0BIN) can be programmed via TRSH1a and TRSH2a (Interrupt Level Setup registers 18HEX, 19HEX
and 1AHEX in NVM; see Table 35). Depending on the INT_setup selection, the EOC pin provides a logic 1 or logic
0 (also dependent on the respective interface setup; e.g., SPI with either logic 0 = V DD or logic 0 = VSS, etc.)
according to the SSC-corrected measurement result. The respective thresholds must be programmed leftaligned in the memory with the threshold’s MSB in the memory register’s MSB, etc. The LSBs of the 24-bit

Feb.2.24

Page 42ZSSC3241

Datasheetthreshold in memory are ignored depending on the number of bits of the ADC resolution as selected with
adc_bits (see Table 10).
The programmable pre-selection eoc_hyst_on=0BIN, enables the consideration of further hysteresis thresholds:
TRSH1b and TRSH2b which are programmed in the NVM-registers 27HEX, 28HEX and 29HEX. The corresponding
threshold consideration by the IC and the resulting EOC output behavior depend on the setup in INT_setup.
Figure 23 to Figure 26 illustrate the EOC behaviors and their respective selection setup based on eoc_hyst_on,
INT_setup, TRSH1a and TRSH2a.
With INT_setup = 00BIN, only the effective end-of-conversion is signalized. The EOC signal is a pulse of
approximately 5µs (see Figure 23). The next command will be executed only after this EOC signaling period.

configured ADCmeasurements: SM,
TM, AZS, AZT

SSC
Calculation

configured ADCmeasurements: SM,
TM, AZS, AZT

SSC
Calculation

configured ADCmeasurements: SM,
TM, AZS, AZT

SSC
Calculation

ZSSC3241 internal activity

SSC-Measurement Result

Time
EOC

5µs

1

0
Time
Note: timing relations are not to scale, they are qualitative illustrations only

Figure 23. EOC-Behavior: Signalization of End-of-Conversion (INT_setup = 00BIN)

The interrupt functionality is only available for digital values from the SSC-calculation unit. The interrupt featurecannot monitor raw values. The encoding and data format of the interrupt thresholds is the same as for SSCcorrected measurement results (see Table 33).
Table 33.

Data Format of Interrupt Thresholds (TRSH1a, TRSH1b, TRSH2a and TRSH2b)

Bit-Number

23

22

21

20

…

2

1

0

Meaning,
Weighting

20

2-1

2-2

2-3

…

2-21

2-22

2-23

Feb.2.24

Page 43ZSSC3241

Datasheet

Measurement
Result

INT_setup = 01BIN

Measurement
Resultmax.

INT_setup = 10BIN

max.

threshold 1athreshold 1a

0

0
Time

Time

EOC

EOC

1

1

0

0
Time

Time

INT_setup = 11BIN

Measurement
ResultCase A:
threshold1a > threshold2a

Measurement
Resultmax.

max.

threshold 1athreshold 2athreshold 2athreshold 1a0Case B:
threshold1a < threshold2a

0
Time

Time

EOC

EOC

1

1

0

0
Time

Time

Figure 24. EOC and Interrupt Thresholds without Hysteresis (eoc_hyst_on=0BIN)

Feb.2.24

Page 44ZSSC3241

Datasheet

Measurement
Result

INT_setup=01BIN

Measurement
Resultmax.

INT_setup=10BIN

max.

threshold 1a=threshold1bthreshold 1a=threshold1b

0

Time

0

EOC

EOC

1

1

0

Time

0

Measurement
ResultMeasurement
Resultmax.

max.

threshold 1a

Time

Time

hysteresis band

threshold 1bthreshold 1athreshold 1b

0

Time

hysteresis band

0

EOC

EOC

1

1

0

Time
Always ensure that threshold1b

0

Time

Time

threshold1a

Figure 25. EOC and Single-Interrupt Thresholds with Hysteresis (eoc_hyst_on=1BIN)

Feb.2.24

Page 45ZSSC3241

Datasheet

INT_setup=11BIN
Measurement
ResultCase A:
threshold1a > threshold2a

Measurement
Resultmax.

Case B:
threshold1a < threshold2amax.

threshold2athreshold2bthreshold1athreshold1bthreshold2athreshold1athreshold1bthreshold2b

0

Time

0

Time

EOC

EOC

1

1

0

Time
Always ensure that: threshold1b0threshold1aTimeand threshold2bthreshold2a

Figure 26. EOC and Dual-Interrupt Thresholds with Hysteresis (eoc_hyst_on=1BIN)

6.6

System Setup and Control

The digital blocks of the ZSSC3241 are organized functionally as shown in Figure 27. In addition to the central
blocks, which are the “Interfaces,” “Digital Main Core,” and “Memory (NVM)” blocks, there is also the Shadow
Registers block, which in most cases, is a direct copy of the NVM registers. The shadow registers are loaded
from NVM during the power-up sequence and allow acceleration of command processing and NVM-independentconfiguration adaptability; e.g., during adaptive sensor setup, evaluation, or smart sensor test. For the mainfunction of the ZSSC3241 to conduct a sensor measurement and ADC-conversion, the setups (for main Sensor
or Temperature) are loaded or activated from the corresponding Shadow Registers in order to set all IC-internal
configuration switches for sensor supply, PGA gain, offset compensation, reference voltage sources, etc. After asettling time for the analog signals and levels, the A2D conversion takes place. This course of activities is(re-)done for each individual measurement, i.e. once for SM, AZS, TM, AZT, with setups for SM and AZS
according the Shadow Registers for SM_config1 and SM_config2, and for TM, AZT from registers
extTemp_config1 and extTemp_config2. If the internal temperature sensor was selected as signal source for TM,
AZT, the setups are loaded from a Renesas-preprogrammed register different to extTemp_config1 and
extTemp_config2.

Feb.2.24

Page 46

ZSSC3241

Datasheet

Analog Front-End

Analog Output

▪
▪
▪
▪

▪ DAC
▪ AO UT driver stages▪ MUXout

Internal Temp. Sensor
PGA
ADC
inMUX

Shadow Registers

Register 02 HEXInterfaces

Select(De)activate

Digital Main Core

Overwrite
Shadow▪
▪
▪
▪

Register 03 HEX
...

Read

OWI

IC Control
Command Interpreter
SSC Math
DAC-SSC and Clipping

Digital Request,
Response

SPI
I2C

Load Shadow from NVM

Memory (NVM)
Read/Write NVM

Register 00 HEXRegister 01 HEX...

Dashed line indicates control line

Register 35 HEX...

Green line indicates data transfer line

Figure 27. Digital IC Section Architecture

6.6.1.

Digital Commands

The availability of commands depends on the active main operating mode: Command, Sleep, or Cyclic Mode.
Table 34.

Command List

Note: See important table notes as the end of this table.
Command Code
(Byte)

ReturnDescription

00HEX to 3F HEX
40HEX to 75HEX
followed by data
(0000HEX to
FFFFHEX)

16-bit data

90HEX

–

A2HEX

24-bit raw data

Memory Read address 00HEX to 3FHEX
Memory Write addresses 00HEX to 35HEX (NVM
register address is command minus 40HEX); if the
NVM is locked, write requests are not acknowledged or are ignored
Calculate NVM Checksum and write it to thememoryRaw Sensor Measurement [a] – Configuration isloaded in the controlling shadow registers fromthe SM_config1 and SM_config2 registers in
NVM
Note: auto-zero sensor measurement isperformed if set up in the AZMs_on bit in the
SSF2 registerFeb.2.24–

Available in
Available in
Available in
Sleep Mode Command Mode Cyclic Mode
Yes

Yes

No

Yes

Yes

No

Yes

Yes

No

Yes

Yes

No

Page 47ZSSC3241

Command Code
(Byte)

Datasheet

ReturnA4HEX

24-bit raw data

A8HEX

–

A9HEX

–

AAHEX

24-bit SSCcorrected
sensor data and24-bit SSCcorrected
temperature
data

ABHEX

–

ACHEX

ADHEX

AEHEX

24-bit SSCcorrected
sensor data and24-bit SSCcorrected
temperature
data

AFHEX

B0HEX

Feb.2.24

16-bitdiagnostic
result data

Description
Raw Temperature Measurement [a] –Configuration is loaded in the controlling shadow
registers from the extTemp_Config1/2 orT_config1/2 registers in NVM as well as the
SSF1/2 registers
Note: Auto-zero correction will be performed if
set up via the AZMt_on bit in the SSF2 register
Note: If a raw data measurement with an external
setup (different from the NVM content) will be
performed, then pre-load the measurement
configuration via the Overwrite SSF1/2 Register
and Overwrite T_config1/2 Shadow Registercommands.
Note: The internal or external temperature
measurement will be performed if set up via thetemp_source bit field in the SSF1 register
START_SLEEP – Exit Command Mode or Cyclic
Mode and transition to Sleep Mode
Note: The response to Start_Sleep is only thestatus byte
START_CM – Exit Sleep Mode or Cyclic Modeand transition to Command Mode
Measure – Trigger a full measurement (autozero-sensor, sensor, auto-zero-temperature,temperature) and perform SSC correction
Note: Auto-zero correction is performed with thiscommand if set up in the AZMs_on and AZMt_on
bits in the SSF2 register
START_CYC – Enter the Cyclic Mode:continuous measurement cycles, SSC
corrections, and automatic, continuous digital
and/or analog output updates
Oversample-2 Measure [b] – Mean value
generation; 2 full measurements (triggeredsimilar to AAHEX, not cyclic) are performed andthe resulting mean value is provided as output
Note: Auto-zero correction is performed with thiscommand if set up in the AZMs_on and AZMt_on
bits in the SSF2 register
Oversample-4 Measure [b] – Mean value
generation; 4 full measurements (triggeredsimilar to AAHEX, not cyclic) are performed andthe resulting mean value is provided as output
Note: Auto-zero correction is performed with thiscommand if set up in the AZMs_on and AZMt_on
bits in the SSF2 register
Oversample-8 Measure [b] – Mean value
generation; 8 full measurements (triggeredsimilar to AAHEX, not cyclic) are performed andthe resulting mean value is provided as output
Note: Auto-zero correction is performed with thiscommand if set up in the AZMs_on and AZMt_on
bits in the SSF2 register
Oversample-16 Measure [b] – Mean value
generation; 16 full measurements (triggeredsimilar to AAHEX, not cyclic) are performed andthe resulting mean value is provided as output
Note: Auto-zero correction is performed with thiscommand if set up in the AZMs_on and AZMt_on
bits in the SSF2 register
CHECK_DIAG – The ZSSC3241 responds withthe detailed fault-result status in the
diagnosticreg register

Available in
Available in
Available in
Sleep Mode Command Mode Cyclic Mode

Yes

Yes

No

No

Yes

Yes

Yes

No

Yes

Yes

Yes

No

Yes

Yes

No

Yes

Yes

No

Yes

Yes

No

Yes

Yes

No

Yes

Yes

No

Yes

Yes

No

Page 48

ZSSC3241

Datasheet

Command Code
(Byte)

Return

B1HEX

–

B2HEX

–

B3HEX followed bydata (0000HEX to
FFFFHEX)–

B4HEX followed by
00XXHEX

24-bit raw data

D1HEX followed by
XXXXHEX

–

D2HEX

–

D6HEX followed bydata (0000HEX to
FFFFHEX)–

D7HEX followed bydata (0000HEX to
FFFFHEX)–

D8HEX followed bydata (0000HEX to
FFFFHEX)–

D9HEX followed bydata (0000HEX to
FFFFHEX)–Feb.2.24

Description
RESET_DIAG – Resets the contents ofdiagnosticreg to 00HEX
Update_DIAG – Causes a complete diagnostics
check cycle including memory CRC calculation,etc., and results in a reset and update ofdiagnosticreg
Note: If a measurement cycle is running concurrently, the diagnostic update happens after
completion of the measurement cycle and SSC
calculations (and might delay the next cyclic
measurement cycle)
DAC Diagnostic – Set the DAC output registerwith the data in the command and enable/output
the respective analog signal through AOUT
(according to the AOUT_setup)
Note: The DAC output can be switched off by the
RESQ pin, POR, or a change in the main
operating mode
Note: DAC Diagnostic feature is only applicablewith the interfaces I2C and SPI.
Self-Diagnostic Measure – The ADC performs a
raw measurement with the setup from theSM_config registers, and the PGA input isdisconnected from the external sensor andinternally shorted (INN = INP = AGND). The
ZSSC3241-internal setup, which is configured
according to the ioffsc bit field in the SM_config2
register, is changed to XXHEX (transmitted withthe command). The respective pseudo-offset
signal becomes the input test signal to the PGAADC-path.
The original ioffsc and SM_config2 contents arerestored after the self-diagnostic measurement
completion.
Note: alternatively, also a changed setup (PGA,
ADC) could be used by applying Overwrite
commands prior to the self-diagnostic
measurement.
Set Post-Calibration Offset – Set recent SSCoutput to expected value XXXXHEX in commandby means of offset adjustment with coefficient
SENS_shift
Startup OWI – Initialization command to enter
OWI interface operation; only valid for OWI (seesection 6.4.3)
Overwrite SM_config1 shadow register –Content (originally from NVM register 14HEX) inthe digital shadow register for SM_config1 isdirectly overwritten with the command data [c]Overwrite SM_config2 shadow register –Content (originally from NVM register 15HEX) inthe digital shadow register for SM_config2 isdirectly overwritten with the command data [c]Overwrite T_config1 shadow register –Content (originally from NVM register 16HEX or
3CHEX) in the digital shadow register for thetemperature measurement is directly overwrittenwith the command data [c]Overwrite T_config2 shadow register –Content (originally from NVM register 17HEX or
3DHEX) in the digital shadow register for thetemperature measurement is directly overwrittenwith the command data [c]Available in
Available in
Available in
Sleep Mode Command Mode Cyclic Mode
Yes

Yes

No

Yes

Yes

No

No

Yes

No

No

Yes

No

Yes

Yes

No

Yes

Yes

Yes

No

Yes

No

No

Yes

No

No

Yes

No

No

Yes

No

Page 49ZSSC3241

Command Code
(Byte)

Datasheet

ReturnDAHEX followedby data (0000HEX
to FFFFHEX)-DBHEX followedby data (0000HEX
to FFFFHEX)

-

FXHEX

Status followed
by last 24-bit
data

Description

Available in
Available in
Available in
Sleep Mode Command Mode Cyclic Mode

Overwrite SSF1 shadow register – Content(originally from NVM register 03HEX) n the digital
shadow register for SSF1 is directly overwrittenwith the command data [c]Note: transferred bits[1:0] and bits[15:13] areignored; i.e., are not overwritten in the shadow
register
Overwrite SSF2 shadow register – Content(originally from NVM register 04HEX) the digital
shadow register for SSF2 is directly overwrittenwith the command data [c]NOP – Output of read results; only valid for SPI(see section 6.4.1)

No

Yes

No

No

Yes

No

Yes

Yes

Yes

[a]

These commands can be used to conduct a measurement without an SSC correction; e.g., during the smart sensor calibration
procedure. No digital correction is performed on the measurement result. The setup and configuration for the raw measurement is
the content in the shadow registers that can be pre-loaded (automatically loaded during power-on) from the NVM or by means of
the Overwrite commands, D6HEX to DBHEX.

[b]

Use Oversample measurements to obtain noise-minimized measurement results in Sleep or Command Mode. With higher
oversampling factors, the command execution time increases proportionally.

[c]Overwrite commands can be used to optimize evaluation and test routine execution time for analog front-end setup or to configure
self-diagnostic measurement setups without needing to change the ZSSC3241’s NVM content. The content and effects from
Overwrite commands are cleared and reset with the ZSSC3241 reset via the RESQ pin or POR.

6.6.2.

Nonvolatile Memory (NVM)

In the ZSSC3241, the memory is organized in 16-bit wide registers and can be programmed multiple times(approximately 10000). There are 54  16-bit registers available for customer use. Each register can be reprogrammed.
Basically, there are two NVM content sectors:•

Customer Use: Accessible via regular write operations: 40HEX to 75HEX. This sector contains the customer ID,
interface setup data, measurement setup information, calibration coefficients, analog output configuration, etc.

•

Renesas Use: Only accessible for write operations by Renesas. This sector (36HEX to 3FHEX) contains
specific trim information and is programmed during manufacturing test by Renesas, e.g. setups for the internal
temperature sensor are stored there.

The whole NVM can be locked by programming lock = 1BIN in the SSF1 register, NVM address 03HEX, bit[14]. Nochange of the NVM content is possible once the NVM lock has been activated.
Recommendations when using the NVM lock:•Write all required setups, configurations, and SSC coefficients to the NVM first.

•

Then write the SSF1 register content with the lock bit set.

•

Then trigger the generation and writing of the CRC via the Calculate NVM Checksum command, 90HEX.

The NVM lock will be effective after a ZSSC3241 reset with POR or RESQ.

Feb.2.24

Page 50ZSSC3241

Datasheet

6.6.2.1.

Memory Contents

Table 35.

Memory (NVM) Content Assignments

NVM Address

Word / Bit Range

Default Setting

00HEX

15:0

0000HEX

01HEX

15:0

0000HEX

6:0

000 0000BIN

Description

Notes / Explanations

Customer ID byte 0 (combines with memory word 01HEX to
Cust_ID0
form customer ID)[a]Customer ID byte 1 (combines with memory word 00HEX to
Cust_ID1
form customer ID).
Interface Configuration
I2C and OWI slave address; valid range: 00HEX to 7FHEX(default: 00HEX).
Slave_Addr
Note: address codes 04HEX to 07HEX are reserved for entering
the I2C High Speed Mode.
Interrupt configuration, EOC pin functionality(clipping_on = 00BIN):
00 = End-of-conversion signal
01 = 0 to 1 transition if threshold1a (TRSH1a) is exceeded
and 1 to 0 transition if threshold1a is underrun again
10 = 0 to 1 transition if threshold1a is underrun and 1 to 0
transition if threshold1a is exceeded again

8:7

00BIN

INT_setup

11 = EOC is determined by threshold settings (see section
6.5.4):• If (TRSH1a > TRSH2a) then EOC/INT (interrupt
level) = 0 if (TRSH1a > MEAS ≥ TRSH2a) where
MEAS is the conditioned measurement result.
Otherwise EOC/INT = 1.
• If (TRSH1a ≤ TRSH2a) then EOC = 1 if (TRSH1a≤ MEAS < TRSH2a). Otherwise EOC = 0.
Determines the polarity of the Slave Select pin (SS) for SPI
operation:

9

0BIN

SS_polarity

02HEX

0=

Slave Select is active low (SPI and ZSSC3241 areactive if SS==0)

1=

Slave Select is active high (SPI and ZSSC3241 areactive if SS==1)

Clock polarity and clock-edge select. CKP_CKE determines
polarity and phase of SPI interface clock with the following
modes:

11:10

14:12

15

03HEX

Feb.2.24

1:0

00BIN

CKP_CKE00 =SCLK is low in idle state; data latch with rising edge
and data output with falling edge

01 =SCLK is low in idle state; data latch with fallingedge and data output with rising edge

10 =SCLK is high in idle state; data latch with fallingedge and data output with rising edge

11 =SCLK is high in idle state; data latch with risingedge and data output with falling edge

Update period in cyclic operation:
000 = 0.0ms
100 = 5.0ms
001 = 0.1ms
101 = 10ms
010 = 1.0ms
110 = 50ms
000BINCYC_period
011 = 2.5ms
111 = 87.5ms
Note: A slower measurement rate, i.e., a higher CYC_period,
can improve the analog output signal quality due to lower
system bandwidth.
Type/shape of second-order curve correction for the sensor
signal:0BIN
SOT_curve
0 = Parabolic curve
1 = S-shaped curve
Smart Sensor Feature Configuration Register 1 (SSF1)
Defines the default operating mode that is automaticallyentered after power-on:
00BIN
default_mode
00 = Command Mode
10 = Sleep Mode
01 = Cyclic Mode
11 = Not assigned

Page 51

ZSSC3241

NVM Address

Datasheet

Word / Bit Range

Default Setting

Description

2

0BIN

owi_su_length

3

0BIN

owi_su_case

Notes / Explanations
Defines the length of the OWI startup window, during which
the OWI interface can be activated if analog output throughthe AOUT pin is also set up via cont_ANAoutn = 0BIN (seeregister 04HEX).
OWI_ListenTime:
0 = 50ms
1 = 3ms
Defines the activation level for the analog output at AOUT
with or without concurrent OWI1 I/O behavior (see section
6.4.3 for OWI application cases):0=

Regular, separate Startup Window for OWI first, thenswitch over to AOUT behavior

1=

Direct start with output of analog signal at AOUT

Selection of utilized temperature sensor source:

6:4000BIN

temp_source

000 =Integrated PTAT temperature sensor (no extra
setup required)001 =Bridge as temperature sensor with internal Rt in
Current Mode[b]010 =Current Mode through TEXT [b]: bridge as thetemperature sensor with external Rt at TEXT andinternal bottom-Rt’

011 =Current Mode operation for diode or PTC between
TEXT and VSSB [b] with internal Rt and Rt’

100 =Current Mode operation for diode or PTC between
TEXT and VSSB [b] with internal bottom-Rt’

101 =Ratiometric supply for the sensor (bridge) as thetemperature sensor with the internal Rt and Rt’ [b]110 =Ratiometric supply for sensor (bridge) as thetemperature sensor with the external Rt between
sensor (bridge) top and TEXT pin[b]111 =Not assigned

Front-end operation and supply setup for main measurandsensor measurements:

8:7

Feb.2.24

00BIN

00 =

Ratiometric supply at VDDB

01 =Current Mode out of VDDB from Tbias(see section 6.2)

10 =Absolute voltage (Thermopile)

11 =Not assigned

sensor_sup

11:9000BIN

internal_rt

12

0BIN

extra_rt

Note: if temp_source = 100 (temperature application T3.2) isalso set up, sensor_sup = 01 must be configured in order to
get ratiometric main sensor supply at VDDB.
Top resistance set up for “Bridge as temperature sensor”
configuration (see Table 16).
Selection of resistance value (internal Rt) for re-using thesensor (bridge) as the temperature sensor with internal Rt(temp_source = 001 or 101).
Selected Rt value is as follows:
000 = 1.34kΩ
100 = 15kΩ
001 = 4kΩ
101 = 20kΩ
010 = 8kΩ
110 = 30kΩ
011 = 10kΩ
111 = 40kΩ
Note: the same value is selected for the bottom Rt’, if
extra_rt = 1BIN is selected
Bottom resistance setup for the “Bridge as temperature
sensor” configuration.
Defines whether an internal bottom resistor Rt’ equivalent to
the internal_rt value selection is placed between VSSB andPGA negative input:
0 = Use internal Rt’
1 = Do not apply internal Rt’

Page 52

ZSSC3241

NVM Address

Datasheet

Word / Bit Range

Default Setting

Description

13

0BIN

owi_off

14

0BIN

lock

15

1:0

2

3

4

0BIN

Notes / Explanations
Setup bit to disable OWI interface:
0 = OWI is enabled and usable
1 = OWI is disabled and cannot be used
Note: This setting has no effect on SPI or I2C operation
Lock bit: no further NVM writing is possible if this bit is set.
0 = NVM write allowed
1 = NVM locked
Note: Once this bit is set to 1, the lock becomes effective
after the next IC reset.
Switch off the charge pump for the internal regulators:
0=

Charge pump on (recommended setting for better
PSRR, or when external VDD<4.3V)

1=

Charge pump off (less current consumption andlower distortion risks, e.g. coupling to VSS); thismight be needed to ensure the 4mA low-limit incurrent loop applications (default setting for preconfigured Current-Loop application products:
ZSSC3241DL*)

cp_off

Note: Switch off the charge pump only if VDD > 4.3V isensuredSmart Sensor Feature Configuration Register 2 (SSF2):
Setup of DAC output resolution:
00BIN
dacres00 =13-bit10 = 15-bit
01 =14-bit11 = 16-bit
Switch on/off the dithering function for the DAC:
1BIN
dither_off
0=
Dither is applied for DAC outputs
1=
Dither is switched off
Defines if the SSC-corrected sensor(bridge) signal S or thetemperature signal T is the output at the DAC:
0BIN
dacouttype
0 = Sensor signal S is output at the DAC
1 = Temperature signal T is output at DAC
Selects whether the ZSSC3241 provides analog output ingeneral:0BIN

cont_ANAoutn

0=

Analog (DAC) output is enabled

1=

No analog output (cyclic operation with digital
outputs is still possible)

Note: If cont_ANAoutn is set to 1, then Aout_setup is ignored;
there is no analog output in Sleep Mode in general
Definition of the basic AOUT pin behavior:
04HEX

001BIN
7:5

Aout_setup(000BIN)

8

Feb.2.24

0BIN

diagouten

000 =Current loop enabled, output through error
amplifier for current loop[c], OWI listens to both
the OWI2in and OWI1 pins concurrently(default setting for pre-configured Current-Loopapplication products: ZSSC3241DL*)

001 =External VDD-ratiometric, rail-to-rail out

010 =0V to 1.0V absolute output

011 =0V to 5V absolute output

100 =not assigned

101 =External VDD-ratiometric, rail-to-rail out (OWI2in
enabled)110 =0V to 1.0V absolute output (OWI2in enabled)

111 =0V to 5V absolute output (OWI2in enabled)

Note: if lower and upper band are reserved for signalizing
diagnostic states, proper output calibration and/or DAC
clipping is required together with diagouten=1BIN
Enable diagnostic level output mode
0 = No analog signalization
1 = Analog diagnostic signaling is enabled

Page 53

ZSSC3241

NVM Address

Datasheet

Word / Bit Range

Default Setting

Description

9

0BIN

disable_ldoctrl

11:10

10BIN

VDD_ldoctrl_target120BIN

AZMs_onNotes / Explanations
Switch off the internal output regulator circuit running the
LDOctrl pin if no external supply transistor (such as JFET) is
used; this reduces current consumption, etc.
0 = LDOctrl output is switched/kept on
1 = LDOctrl output switched off
Note: If enabled (= 0), then the charge-pump can be off (thecp_off bit = 1 in register 03HEX)
Set point for regulated VDD using external supply transistor
JFET or depletion MOSFET:
00 = VDD = 4.8V
01 = VDD = 5.0V
10 = VDD = 5.2V
11 = VDD = 5.4V
Enable/disable for auto-zero measurement for (bridge)
sensor measurement:0=

No auto-zero measurements for sensor signal

1=

Auto-zero measurement of sensor bridge isperformed and processed

Note: This setup is ignored for raw data measurements withsetup via the interface, i.e. command A2HEX
Enable/disable for auto-zero measurement for temperature
measurement:
13

0BIN

AZMt_on0=

No auto-zero measurements for temperature signal

1=

Auto-zero measurement for temperature signal
performed and processed

Selection for applied digital oversampling in Cyclic Modeoperation:

15:14

05HEX

15:0

06HEX

15:0

07HEX

15:0

08HEX

15:0

09HEX

15:0

0AHEX

15:0

0BHEX

15:0

Feb.2.24

00BIN

oversamp_cyc

00 =No oversampling

01 =Oversample-4: Results of 4 SSC cycles per lastmeas_scheduler sequence

10 =Oversample-8: Results of 8 SSC cycles per lastmeas_scheduler sequence

11 =Oversample-16: Results of 16 SSC cycles per lastmeas_scheduler sequence

Note: This setup is ignored for any measurement inCommand and Sleep Mode
Signal Conditioning Parameters
Bits [15:0] of the 24-bit-wide sensor offset correction
0000HEX
Offset_S[15:0] coefficient Offset_S. The MSBs including sign are
Offset_S[23:16], which is [15:8] in register 0FHEX.
Bits [15:0] of the 24-bit-wide value of the sensor gain
coefficient Gain_S. The MSBs including sign are
0000HEX
Gain_S[15:0]
Gain_S[23:16], which is [7:0] in register 0FHEX.
Bits [15:0] of the 24-bit-wide coefficient Tcg for thetemperature correction of the sensor gain. The MSBs
0000HEXTcg[15:0]
including sign are Tcg[23:16], which is bits [15:8] inregister 10HEX.
Bits [15:0] of the 24-bit-wide coefficient Tco for temperaturecorrection of the sensor offset. The MSBs with sign are
0000HEXTco[15:0]
Tco[23:16], which is bits [7:0] in register 10HEX.
Bits [15:0] of the 24-bit-wide 2nd order term SOT_tco applied
0000HEX
SOT_tco[15:0] to Tco. The MSBs of this term including sign are
SOT_tco[23:16], which is bits [15:8] in register 11HEX.
Bits [15:0] of the 24-bit-wide 2nd order term SOT_tcg applied
0000HEX
SOT_tcg[15:0] to Tcg. The MSBs of this term including sign are
SOT_tcg[23:16], which is bits[7:0] in register 11HEX.
Bits [15:0] of the 24-bit-wide 2nd order term SOT_sens
applied to the sensor readout. The MSBs of this term
0000HEXSOT_sens[15:0]
including sign are SOT_sens[23:16], which is bits[15:8] inregister 12HEX.

Page 54ZSSC3241

NVM Address

Datasheet

Word / Bit Range

0CHEX

15:0

0DHEX

15:0

0EHEX

15:0

7:0
0FHEX
15:8

7:0
10HEX
15:8

7:0
11HEX
15:8

7:0
12HEX
15:8

7:0
13HEX
15:8

Default Setting

Description

Notes / Explanations

Bits [15:0] of the 24-bit-wide temperature offset correction
0000HEX
Offset_T[15:0] coefficient Offset_T. The MSBs of this coefficient including
sign are Offset_T[23:16], which is bits[7:0] in register 12HEX.
Bits [15:0] of the 24-bit-wide absolute value of thetemperature gain coefficient Gain_T. The MSBs including
0000HEX
Gain_T[15:0]
sign are Gain_T[23:16], which is bits[15:8] in register 13HEX.
Bits [15:0] of the 24-bit-wide 2nd-order term SOT_T applied tothe temperature reading. The MSBs including sign are
0000HEXSOT_T[15:0]
SOT_T[23:16], which is bit[7:0] in register 13HEX.
Bits [23:16] including sign for the 24-bit-wide sensor gain
20HEX
Gain_S[23:16] correction coefficient Gain_S. The LSBs of this coefficient are
Gain_S[15:0] in register 06HEX.
Bits [23:16] including sign for the 24-bit-wide sensor offset
00HEX
Offset_S[23:16] correction coefficient Offset_S. The LSBs are Offset_S[15:0]
in register 05HEX.
Bits [23:16] including sign for the 24-bit-wide coefficient Tco
for temperature correction for the sensor offset. The LSBs are
00HEX
Tco[23:16]
Tco[15:0] in register 08HEX.
Bits [23:16] including sign for the 24-bit-wide coefficient Tcg
for the temperature correction of the sensor gain. The LSBs
00HEX
Tcg[23:16]
are Tcg[15:0] in register 07HEX.
Bits [23:16] including sign for the 24-bit-wide 2nd order term
00HEX
SOT_tcg[23:16] SOT_tcg applied to Tcg. The LSBs are SOT_tcg[15:0] inregister 0AHEX.
Bits [23:16] including sign for the 24-bit-wide 2nd order term
00HEX
SOT_tco[23:16] SOT_tco applied to Tco. The LSBs are SOT_tco[15:0] inregister 09HEX.
Bits [23:16] including sign for the 24-bit-wide temperature
00HEX
Offset_T[23:16] offset correction coefficient Offset_T. The LSBs are
Offset_T[15:0] in register 0CHEX.
Bits [23:16] including sign for the 24-bit-wide 2nd order term
00HEX
SOT_sens[23:16] SOT_sens applied to the sensor readout. The LSBs are
SOT_sens[15:0] in register 0BHEX.
Bits [23:16] including sign for the 24-bit-wide 2nd-order term
SOT_T applied to the temperature reading. The LSBs are
00HEX
SOT_T[23:16]
SOT_T[15:0] in register 0EHEX.
Bits [23:16] including sign for the 24-bit-wide absolute value
20HEX
Gain_T[23:16] of the temperature gain coefficient Gain_T. The LSBs are
Gain_T[15:0] in register 0DHEX.
Measurement Configuration Register 1 (SM_config1)
Gain setting for the 1st PGA stage with Gain_stage1[3:0]:

Parameters are valid for
GainPGA ≤ 192:
3:0

0111BIN

Gain_stage1

6:4

001BIN

Gain_stage2

7

0BIN

Gain_polarity

14HEX

Feb.2.24

Parameters are limited for
GainPGA > 192:

0000 = 1.2
0110 = 30 1011 = 150
0001 = 20111 = 40 1100 = 2000010 = 41000 = 60 1101 = 2400011 = 61001 = 80 1110 = 300
0100 = 121010 = 120 1111 = Not assigned
0101 = 20
Gain setting for the 2nd PGA stage with Gain_stage2[1:0]:
000 = 1.1
100 = 1.5001 = 1.2
101 = 1.6
010 = 1.3
110 = 1.7
011 = 1.4
111 = 1.8
Set up the polarity of the sensor bridge’s gain
(invert chopper 1):
0 = positive (no polarity change)
1 = negative (180° polarity change)

Page 55ZSSC3241

NVM Address

Datasheet

Word / Bit Range

Description

11:8

0100BIN

adc_bits

14:12

000BIN

adc_offset

15

1BIN

sel_ref1

4:0

15HEX

7:5

8

9

15:10

Feb.2.24

Default Setting

Notes / Explanations
Resolution, i.e. absolute number of bits for the ADC with
adc_bits[3:0]:0000 = 120111 = 190001 = 131000 = 200010 = 141001 = 210011 = 151010 = 220100 = 16 (default)
1011 = 230101 = 171100 = 240110 = 181101 to 1111 = Not assigned
Differential signal’s offset shift in the ADC including gain x2;
compensation of x% signal offset:
000 = 0%, no offset compensation 100 = 25.00% offset
001 = 6.25% offset
101 = 31.25% offset
010 = 12.50% offset
110 = 37.50% offset
011 = 18.75% offset
111 = 44.00% offset
Reference source for main sensor measurement:0=Absolute (internal) bandgap is the reference

1=

Ratiometric reference; recommended forratiometrically supplied sensors

Measurement Configuration Register 2 (SM_config2)
Absolute voltage input shift for input signals to the PG, e.g.
INP-INN
The input signal is shifted by the following voltages:
00000 =
0mV, no shift
00001 =
-1mV
00010 =
-2mV
00011 =
-3mV…
0 0000BIN
ioffsc01110 =
-14mV
01111 =
-15mV
10000 =
0mV, no shift
10001 =
+1mV
10010 =
+2mV…
11110 =
+14mV
11111 =
+15mV
Current Mode sensor bias selection; nominal sensor supply
current Isup(if sensor_sup = 01):
000 =
5µA
001 =
10µA
010 =
20µA
000BIN
Tbiasout
011 =
39µA
100 =
79µA
101 = 157µA
110 = 196µA
111 = 494µA
General disable/enable of the ADC feature to apply the extra
gain x2 and signal offset compensation adc_offset in register
14HEX:
0BIN
adc_en_shift
0 = Gain: 2 and signal offset compensation off
1 = Gain: 2 and signal offset compensation on
Automatic common mode adjust feature, which allows
automatically, optimally adapting the sensor-input common
mode to AGND at the PGA output.[d]1BIN
pga_en_shift
0 = Automatic common mode adjustment off
1 = Automatic common mode adjustment on
00 0000BIN–
Not assigned

Page 56

ZSSC3241

NVM Address

Datasheet

Word / Bit Range

Default Setting

Description

Notes / Explanations

External Temperature Measurement Configuration Register 1 (extTemp_config1)
Gain setting for the 1st PGA stage with Gain_stage1[3:0] forexternal temperature measurements:
Parameters are valid for GainPGA ≤ 192:
0000 = 1.2
0110 = 30
0001 = 20111 = 400010 = 41000 = 600011 = 61001 = 80
0100 = 121010 = 120
3:0
0000BIN
Gain_stage1
0101 = 20

6:4000BIN

Gain_stage2

7

0BIN

Gain_polarity

11:8

0100BIN

adc_bits

14:12

000BIN

adc_offset

15

0BIN

sel_ref2

16HEX

Feb.2.24

Parameters are limited for GainPGA > 192:
1011 = 150
1100 = 2001101 = 240
1110 = 300
1111 = Not assigned
Gain setting for the 2nd PGA stage with Gain_stage2[1:0] forexternal temperature measurements:
000 = 1.1
100 = 1.5001 = 1.2
101 = 1.6
010 = 1.3
110 = 1.7
011 = 1.4
111 = 1.8
Set up the polarity of the temperature sensor gain (invert
input) with:
0 = Positive (no polarity change)
1 = Negative (180° polarity change)
Resolution, i.e. absolute number of bits for the ADC forexternal temperature measurements with adc_bits[3:0]:0000 = 120111 = 190001 = 131000 = 200010 = 141001 = 210011 = 151010 = 220100 = 16 (default)
1011 = 230101 = 171100 = 240110 = 181101 to 1111 = Not assigned
Differential signal’s offset shift in ADC including gain x2 forexternal temperature measurements; compensation of x%
signal offset:
000 = 0%, no offset compensation
001 = 6.25% offset
010 = 12.50% offset
011 = 18.75% offset
100 = 25.00% offset
101 = 31.25% offset
110 = 37.50% offset
111 = 44.00% offset
Reference source for external temperature sensing andconversion:0=

Absolute (internal) bandgap is reference

1=

Ratiometric reference; recommended forratiometrically supplied sensors

Page 57

ZSSC3241

NVM Address

17HEX

18HEX

19HEX

1AHEX

1BHEX

1CHEX

1DHEX

Feb.2.24

Datasheet

Word / Bit Range

Default Setting

Description

Notes / Explanations

External Temperature Measurement Configuration Register 2 (extTemp_config2)
Absolute voltage input shift for input signals for external
temperature measurements to the PG, e.g. INP-INN
The input signal is shifted by the following voltages:
00000 = 0mV, no shift
00001 = -1mV
00010 = -2mV
00011 = -3mV…
4:0
0 0000BIN
ioffsc01110 = -14mV
01111 = -15mV
10000 = 0mV, no shift
10001 = +1mV
10010 = +2mV…
11110 = +14mV
11111 = +15mV
Current Mode sensor bias selection for external temperature
measurements; nominal sensor supply current(if temp_source є {001BIN, 010 BIN, 011 BIN, 100 BIN }):000 = 5µA
001 = 10µA
010 = 20µA
7:5000BIN
Tbiasout
011 = 39µA
100 = 79µA
101 = 157µA
110 = 196µA
111 = 494µA
General disenable/enable of the ADC feature for external
temperature measurements to apply the extra gain x2 andsignal offset compensation adc_offset in register 16HEX:
80BIN
adc_en_shift
0 = Gain: x2 and signal offset compensation off
1 = Gain: x2 and signal offset compensation on
Automatic common mode adjust feature, which allows
automatically, optimally adapting the sensor-input common
mode to AGND at the PGA output for external temperature
90BIN
pga_en_shiftmeasurements.[d]0 = Automatic common mode adjustment off
1 = Automatic common mode adjustment on
15:10
00 0000BIN–
Not assigned
Interrupt Level Setup and Post-Calibration (Digital) Offset Calibration
Bits [15:0] of the 24-bit-wide interrupt threshold1a, TRSH1a.
15:0
0000HEXTRSH1a[15:0] (The MSBs for this threshold are TRSH1a[23:16], which isbits [7:0] of register 1AHEX.)
Bits [15:0] of the 24-bit-wide interrupt threshold2a, TRSH2a.
15:0
0000HEXTRSH2a[15:0] (The MSBs for this threshold are TRSH2a[23:16], which isbits[15:8] of register 1AHEX.)
Bits [23:16] of the 24-bit-wide interrupt threshold1a, TRSH1a.
7:0
00HEX
TRSH1a[23:16] (The LSBs for this threshold are TRSH1a[15:0], which isbits[15:0] of register 18HEX.)
Bits [23:16] of the 24-bit-wide interrupt threshold2a, TRSH2a.
15:8
00HEX
TRSH2a[23:16] (The LSBs for this threshold are TRSH2a[15:0], which isbits[15:0] of register 19HEX.)
Bits [15:0] of the post-calibration sensor offset shift coefficient
15:0
0000HEXSENS_Shift[15:0] SENS_Shift.
(The MSBs of SENS_Shift are bits [15:8] of register 1DHEX.)
Bits [15:0] of the post-calibration temperature offset shiftcoefficient T_Shift.
15:00000HEXT_Shift[15:0](The MSBs of T_Shift are bits [7:0] of register 1DHEX.)
Bits [23:16] of the post-calibration temperature offset shift
7:0
00HEX
T_Shift[23:16] coefficient T_Shift. (The LSBs of T_Shift are in register
1CHEX.)

Page 58

ZSSC3241

NVM Address

1EHEX

Datasheet

Word / Bit Range

Default Setting

Description

Notes / Explanations

Bits [23:16] of the post-calibration sensor offset shift
15:8
00HEX
SENS_Shift[23:16] coefficient SENS_Shift. (The LSBs of SENS_Shift are in
register 1BHEX.)
Measurement Scheduler (Cyclic Operation Sequence)
Cyclic measurement operation is performed with / including
the sensor measurement:
0 = Sensor measurement is performed
00BIN
cycwsn1 = Sensor measurement is not performed
Note: Whether AZS is to be performed in the cyclic
measurement sequence is set up with AZMs_on (see register
04HEX)
Cyclic measurement operation is performed with thetemperature measurement:
0 = Temperature measurement is performed
10BIN
cycwtn
1 = Temperature measurement is not performed
Note: whether AZT is to be performed in the cyclic
measurement sequence is set up with AZMt_on (see register
04HEX)
20BIN
Not assigned
Cyclic measurement operation is performed with / including
the sensor-connection check:3
1BIN
cycwscn
0 = Sensor connection check is performed
1 = Sensor connection check is not performed
The bits [9:4] in the 1EHEX register define whether the cycle measurement sequence performs the respective
measurement type in the first slot or only after respective slots_X have been completed for the first time.
Note: The SSC and analog output will only become valid after the sensor, temperature, and related auto-zeromeasurements have already been conducted for the first time. The first output signals maybe invalid until this condition
is reached.
0 = Perform the sensor measurement in the first slot
40BIN
startS_wfirstn
1 = Do not perform the sensor measurement in the first slot

5

0BIN

startAZS_wfirstn

0=

Perform the auto-zero sensor measurement in thefirst slot

1=

Do not perform the auto-zero sensor measurementin the first slot

Note: The startAZS_wfirstn bit is ignored for the cyclic
operation if the AZMs_on = 0 = “off.”

6

0BIN

startT_wfirstn

1EHEX(continued)
7

0BIN

startAZT_wfirstn

8

0BIN

–

9

0BIN

startSC_wfirstn

0=

Perform the temperature measurement in the first
slot

1=

Do not perform the temperature measurement in thefirst slot

0=

Perform the auto-zero temperature measurement in
the first slot

1=

Do not perform the auto-zero temperature
measurement in the first slot

Note: The startAZT_wfirstn bit is ignored for the cyclic
operation if the AZMt_on = 0 = “off.”
Not assigned
Diagnostics: sensor connection checks:
0=

Perform sensor connection checks in the first slot

1=

Do not perform sensor connection checks in the first
slot

Defines the number of pause slots between two subsequent
temperature measurements:
0=
15:10

00 0000BIN

slots_TNo pause, measure temperature at eachslot

1DEC to 63DEC= Pause slots after the slot with thetemperature measurement
Note: Set slots_T = slots_AZT for correct Cyclic
Operation.

Feb.2.24

Page 59

ZSSC3241

NVM Address

Datasheet

Word / Bit Range

Default Setting

Description

Notes / Explanations
Defines the number of pause slots between two subsequentauto-zero temperature (AZT) measurements:0=

5:0

00 0000BIN

slots_AZT

No pause, measure AZT at each slot

1 to 63DEC = Number of pause slots after the slot with the
AZT measurement
Note: If AZMt_on = 0, no auto-zero temperature
measurement will be performed.
Defines the number of pause slots between two subsequent
sensor / bridge measurements:

1FHEX

9:6

0000BIN

slots_S0=

No pause, measure sensor at each slot

1DEC to 15DEC=

Number of pause slots after the slot withthe sensor measurement

Note: Set slots_S = slots_AZS for correct Cyclic
Operation.
Defines the number of pause slots between two subsequentauto-zero sensor (AZS) measurements:
13:10

20HEX

0000BIN

slots_AZS

15:14
5:0

00BIN
00 0000BIN

–
–

15:6

00 0000 0000BIN

slots_SC0=

No pause, measure AZS at each slot

1DEC to 15DEC=

Number of pause slots after the slot withsensor measurement

Note: If AZMs_on = 0, no auto-zero sensor measurement isperformed.
These bits must be 00BIN to ensure proper Cyclic Operation
Not assigned.
Defines the number of pause slots between two subsequent
sensor connection check runs:0=

No pause, always check sensor
connection

1DEC to 1023DEC= Number of pause-slots after slot with
Sensor-Connection check

21HEX

Feb.2.24

Selection of (Sensor) Connection Checks to be Conducted
The first 10 bits of register 21HEX are the select_checks[9:0] bit field:
Loss of sensor positive connection, INP [e]00BIN
inp_check
0 = Check is not performed; result is not signalized
1 = Check is performed; result is signalized
Loss of bridge/sensor negative connection, INN [e]10BIN
inn_check
0 = Check is not performed; result is not signalized
1 = Check is performed; result is signalized
Signal at pin INP out of range (leaking / short to VSS or
VDDB) [e]20BIN
inp_range_check
0 = Check is not performed; result is not signalized
1 = Check is performed; result is signalized
Signal at pin INN out of range (leaking / short to VSS or
VDDB) [e]30BIN
inn_range_check
0 = Check is not performed; result is not signalized
1 = Check is performed; result is signalized
Sensor short (INN = INP)
sens_short
4
0BIN
0 = Check is not performed; result is not signalized_check
1 = Check is performed; result is signalized
TEXT pin open [e]50BIN
text_open_check 0 = Check is not performed; result is not signalized
1 = Check is performed; result is signalized
Signal at pin TEXT out of range (leaking / short to VSS or
VDDB) [e]60BIN
text_range_check
0 = Check is not performed; result is not signalized
1 = Check is performed; result is signalized
TEXT pin short to INN
text_inn_short
7
0BIN
0 = Check is not performed; result is not signalized_check
1 = Check is performed; result is signalized

Page 60

ZSSC3241

NVM Address

Datasheet

Word / Bit Range
8

9
15:10

22HEX

15:0

23HEX

15:0

1:0

Default Setting

Description

eoc_hyst_on

Enable second EOC interrupt extra threshold set threshold1b
and threshold2b:
0=
usage of extra thresholds disabled
1=
usage of extra thresholds enabled
Enable bit for the additional DAC-SSC pre-distortion for DAC
output linearization (via Gain_DAC, Offset_DAC):
0=
usage of DAC-SSC correction disabled/bypassed
1=
usage of DAC-SSC correction enabled

24HEX
2

25HEX

0BIN

3

0BIN

dac_ssc_enable

15:4000HEX-

15:0

0000HEX

Low_Clip_Lim

26HEX

15:0

0000HEX

Up_Clip_Lim

27HEX

15:0

0000HEXTRSH1b[15:0]

28HEX

15:0

0000HEXTRSH2b[15:0]

7:0

00HEX

TRSH1b[23:16]

15:8

00HEX

TRSH2b[23:16]

15:0

0000HEX

Gain_DAC

29HEX

2AHEX

Feb.2.24

Notes / Explanations

TEXT pin short to INP
text_inp_short
0BIN
0 = Check is not performed; result is not signalized_check
1 = Check is performed; result is signalized
Broken-chip check / chipping check
0BIN
crack_check
0 = Check is not performed; result is not signalized
1 = Check is performed; result is signalized
00 0000BIN–
Not assigned
DAC (Output Calibration Data)
Encoded, 16bit-quantized measurement value of DAC-output
at VDD=5V with 10%-DAC-excitation, digital code (199AHEX).
Programmed at Renesas’ device test. The measured DACXXXXHEXDAC10RM5V
voltage [f] can be derived as: VDAC10,AOUT[V] :=DAC10RM5V[dec] / 296000 + 0.39
Encoded, 16bit-quantized measurement value of DAC-output
at VDD=5V with 90%-DAC-excitation, digital code (E666HEX).
Programmed at Renesas’ device test. The measured DACXXXXHEX
DAC90RM5V
voltage [f] can be derived as: VDAC90,AOUT[V] :=DAC90RM5V[dec] / 284000 + 4.45
Enhanced Output Features
DAC Clipping function, i.e. consideration of DAC clipping
limits (Up_Clip_Lim, Low_Clip_Lim) for the AOUT signal:
00 = DAC clipping disabled
01 = upper limit DAC clipping disabled,
00BIN
clipping_on
lower limit DAC clipping enabled
10 = upper limit DAC clipping enabled,
lower limit DAC clipping disabled
11 = upper and lower limit DAC clipping enabled

Not assigned
Lower DAC output clipping limit.
If the calculated value (T or S per selection in dacouttype) islower than this limit, the analog output value is clipped to thisvalue.
Note: if diagnostic checks are enabled (by means of
diagouten), clipping is not appliedUpper DAC output clipping limit.
If the calculated value (T or S per selection in dacouttype) ishigher than this limit, the analog output value is clipped to thisvalue.
Note: if diagnostic checks are enabled (by means of
diagouten), clipping is not applied
Bits [15:0] of the 24-bit-wide interrupt TRSH1b. (The MSBs
for this threshold are TRSH1b[23:16], which is bits [7:0] of
register 29HEX.)
Bits [15:0] of the 24-bit-wide interrupt TRSH2b. (The MSBs
for this threshold are TRSH2b[23:16], which is bits[15:8] ofregister 29HEX.)
Bits [23:16] of the 24-bit-wide interrupt TRSH1b. (The LSBs
for this threshold are TRSH1b[15:0], which is bits[15:0] of
register 27HEX.)
Bits [23:16] of the 24-bit-wide interrupt TRSH2b. (The LSBs
for this threshold are TRSH2b[15:0], which is bits[15:0] of
register 28HEX.)
Gain correction coefficient for DAC-SSC math, see section
6.6.3.3

Page 61

ZSSC3241

NVM Address

Datasheet

Word / Bit Range

2BHEX

15:0

2CHEX

15:0

…
34HEX

15:0

35HEX

15:0

Default Setting

Description

Notes / Explanations

Offset correction coefficient for DAC-SSC math, see section
0000HEX
Offset_DAC
6.6.3.3
Free Memory (Available for Customer Use)
Not assigned (e.g., can be used for Cust_IDx customer
0000HEX–
identification number)
Not assigned (e.g., can be used for Cust_IDx customer–
identification number)
Not assigned (e.g., can be used for Cust_IDx customer
0000HEX–
identification number)
Generated (checksum) for the entire memory through a linear
feedback shift register (LFSR); signature is checked on
Checksumpower-up to ensure memory content integrity[a]

For I3C operation, this should contain the Legacy Virtual Register (LVR) information: 1XHEX to Index 0. Fast-Mode is supported.

[b]

Use the extTemp_config1 and extTemp_config2 registers for temperature sensor related front-end configuration.

[c]

In Current Loop Operation Mode, it must be ensured that a sufficient external V DD-level > 4.8V is present (e.g., with external supply
transistor, such as JFET or depletion MOSFET, and extra LDO-control option).

[d]

If pga_en_shift is enabled, the ZSSC3241 current consumption increases by approximately 100µA. Usage is recommended for
optimizing the analog front-end setup.

[e]

Do not enable ( set to 0BIN) if the IC is connected to an absolute voltage source sensor, for example, Thermopile (sensor_sup = 10BIN).

[f]

The IC provides the originally measured DAC-output voltage VDAC*0,AOUT[V] with VDD=5V, Aout_setup=(001BIN or 101BIN) as reaction on
B3HEX command, see Table 34.

The NVM-consistence checksum is calculated (internally by the ZSSC3241 for the whole NVM) using thepolynomial: x16 + x15 + x2 + 1. The checksum verification is only realized directly after V DD power-on. If thechecksum is successfully verified, then the “Memory Error” status bit is set to 0 BIN.
6.6.3.

Digital Sensor-Signal-Conditioning Mathematics

The saturation check (signalized by SSC Calculation Unit Saturation, see Table 17) in the ZSSC3241 detects
saturation effects of the internal calculation steps, allowing the final correction output to be determined despite
the saturation. It is possible to get potentially useful signal conditioning results that have had an intermediate
saturation during the calculations. These cases are detectable; e.g., by observing the status bit[0] for eachmeasurement result. Details about the saturation limits and the valid ranges for values are provided in theequations in the following sections.
The calibration math description assumes a calculation with integer numbers. The description is numericallycorrect concerning values, dynamic range, and resolution.
6.6.3.1.

Main Sensor Signal Correction (Main SSC Math)The configuration parameter SOT_curve in NVM register 02HEX selects whether second-order equations
compensate for sensor nonlinearity with a parabolic or S-shaped curve. The parabolic compensation isrecommended for most sensor types.
The following equations describe the available SSC capabilities. The equation terms are as follows:
S

Corrected sensor reading output via I2C, OWI, or SPI; range [0HEX to FFFFFFHEX]

S_Raw

Raw sensor reading from ADC (after AZ correction, if selected); range [-7FFFFFHEX to
7FFFFFHEX]

Gain_S

Sensor gain term; range [-7FFFFFHEX to 7FFFFFHEX]

Offset_S

Sensor offset term; range [-7FFFFFHEX to 7FFFFFHEX]

Tcg

Temperature coefficient gain term; range [-7FFFFFHEX to 7FFFFFHEX]

Tco

Temperature coefficient offset term; range [-7FFFFFHEX to 7FFFFFHEX]

T_Raw

Raw temperature reading (after AZ correction); range [-7FFFFFHEX to 7FFFFFHEX]

SOT_tcg

Second-order term for Tcg non-linearity; range [-7FFFFFHEX to 7FFFFFHEX]

Feb.2.24

Page 62

ZSSC3241

Datasheet

SOT_tcoSecond-order term for Tco non-linearity; range [-7FFFFFHEX to 7FFFFFHEX]

SOT_sens

Second-order term for sensor non-linearity; range [-7FFFFFHEX to 7FFFFFHEX]SENS_shift

Post-calibration, post-assembly offset shift; range [-7FFFFFHEX to 7FFFFFHEX]



Absolute value  ulll

Bound/saturation number range from ll to ul, overflow/underflow is reported as saturation in thestatus byte

The correction formula for the differential signal reading is represented as a two-step process depending on the
SOT_curve setting.
Table 36.

Data Format of 24-bit SSC Coefficients

Bit-Number:

23
0 = positive
1 = negative

Meaning, Weighting

Table 37.

22

21

20

…

2

1

0

21

20

2-1

…

2-19

2-20

2-21

Data Format of Corrected, SSC Results (S and T)

Bit-Number:

23

22

21

20

…

2

1

0

Meaning, Weighting

20

2-1

2-2

2-3

…

2-21

2-22

2-23

Equations for the parabolic SOT_curve setting (SOT_curve = 0):
Simplified:
K1 = 223 +

T_Raw
223

∙ (4 ∙ SOT_tcg
∙T
2
23

∙

K2 = 4 Offset_S + S_raw +

ZSP =

S =

ZSP
223

∙

223

∙

∙( ∙

223

4 Gain_S

K1
223

T_Raw
223

4 SOT_sens∙Z∙ Tcg)∙( ∙ 2

4 SOT_tco

23Equation 7∙ Tco)

Equation 8(delimited to positive number range)

Equation 9

23

∙K +2
2

Raw + 423
SP + 2 ) + SENS_shift∙TRaw + 4Equation 10(delimited to positive number range)

Complete:

T_Raw

K1 = 223 +

23

[

[

2

SOT_tcg∙ [[[Gain_SZSP = [
221[

Feb.2.24

225 -1∙ [2 ∙ K ]
23

T_Raw
[

[

K1

Raw ]
-225

2

∙

2

-225

2 -1

∙T

21

K2 = 4 Offset_S + S_raw +225 -1

25

223

∙

-225

225 -1Equation 11∙+ 4 Tcg]

SOT_tco[[221-225 ]-225∙T

225 -1
Raw ]
25
-2

]-225

25

2 -1

225 -1225 -1225 -1Equation 12∙+ 4 Tco]
-2

25

]-225

]-225

]-225

225 -1225 -1]225 -1Equation 13

+ 223
]0

Page 63

ZSSC3241

𝑍𝑆𝑃
S = [[ 232

Datasheet

𝑆𝑂𝑇_𝑠𝑒𝑛𝑠221∙ [[225 −1225 −1∙𝑍 ]𝑆𝑃+ 223 ]

−225

Equation 14+ SENS_shift]

]

−225

224 -1225 −1−225

0Equations for the S-shaped SOT_curve setting (SOT_curve = 1):
Simplified:∙∙

4 Gain_S

ZSS =

223

∙( ∙

Z

4

S = SS
23
2

K1
223

∙K

SOT_sens(K1 and K2 according to Equation 7 and Equation 8)

2∙ |Z | + 2 ) + 2 + SENS_shift
23

SS

223

23

(delimited to positive number range)

Equation 15
Equation 16

Complete:
Gain_SZSS = [
221
[

ZSS

S=

23

[
[

2

225-1

K1

∙ [2 ∙ K ]2

23

SOT_sens∙ [[6.6.3.2.

-225

225 -1Equation 17]-225 ]-225

25

2 -1

∙ |Z |]
SS

21

2

225 -1

-2

25

25

2 -1

224 -1225 -1+ 223 ]

+ 223 + SENS_shift-225 ]-225

Equation 18]0

Main Temperature Signal Correction

Temperature is measured either internally by the ZSSC3241 or through an additional external element or bymeans of a combination of ZSSC3241-internal and external temperature sensing capabilities; see sections 6.2.3
and 6.2.4. Temperature correction contains both linear gain and offset terms as well as a second-order term tocorrect for any nonlinearities. For temperature, second-order compensation for nonlinearity is always parabolic.
The correction equation terms are as follows:
T

Corrected temperature sensor reading output via digital interface; range [0 HEX to FFFFFFHEX]

Gain_T

Gain coefficient for temperature; range [-7FFFFFHEX to 7FFFFFHEX]

T_Raw

Raw temperature reading after AZ correction; range [-7FFFFFHEX to 7FFFFFHEX]

Offset_T

Offset coefficient for temperature; range [-7FFFFFHEX to 7FFFFFHEX]

SOT_T

Second-order term for temperature source nonlinearity; range [-7FFFFFHEX to 7FFFFFHEX]

T_Shift

Shift for post-calibration/post-assembly offset compensation [-7FFFFFHEX to 7FFFFFHEX]

The correction formula is best represented as a two-step process as follows:
Simplified:∙ZT =4 Gain_TZ∙( ∙T = 23T
2

223∙ ( T_Raw + 4 ∙ Offset_T) + 2

23

4 SOT_T
223(delimited to positive number range)∙ Z + 2 ) + T_shift (delimited to positive number range)T

23

Equation 19
Equation 20

Complete:
Gain_TZT = [[
221

Feb.2.24∙ [T_Raw + 4 ∙225 -125
Offset_T ]2-225-1 ]-225

225 -123+2 ]Equation 21

0

Page 64ZSSC3241

𝑍𝑇
T = [[ 232∙

6.6.3.3.

Datasheet

𝑆𝑂𝑇_𝑇
[[ 21
2

25
𝑍𝑇 ] 2−225−1 +

∙

2 ]

−225

24

2 -1

225 −1225 −123

Equation 22+ T_shift]

]
−225

0

Separate Correction of the Digital-to-Analog Converter Characteristic (DAC-SSC)

In applications that require both digital and analog outputs, the separate DAC output signal compensation unit
can be applied. It temperature independently allows to compensate the ZSSC3241’s DAC offset and DAC gain
deviation (resulting from manufacturing process variation) from an ideal, linear characteristic.
Note: If only analog outputs need to be provided, the main SSC math can cover corrections for all sensor- andIC-characteristics including DAC offset and DAC gain without an extra DAC output signal compensation feature.
The DAC output signal compensation can be enabled by dac_ssc_enable. It is applied to main SSC corrected
output signals for main sensor: S or temperature: T (to which of those is determined by the dacouttype
selection). The processing width and coefficients of the DAC output signal compensation are 16Bit wide.
Gain_DAC is formatted as 16bit-integer, the Offset_DAC is formatted as 16bit 2’s-complement.
DAC output signal compensation contains both linear gain and offset terms as follows:
Gain_DAC:

Gain coefficient for DAC output correction; range [0HEX to FFFFHEX];

Offset_DAC:

Offset coefficient for DAC output correction; range [-7FF0HEX to 7FF0HEX];

DAC_in_orig: DAC Digital input from main SSC math (T or S); range [0HEX to FFFFFFHEX];
DAC_in:16 MSBs of digital input from main SSC math (T or S); range [0HEX to FFFFHEX];DAC_out:

Corrected digital word to lead to the final output of the DAC; range [0HEX to FFFFHEX];

Simplified:Equation 23

DAC_IN = DAC_in_orig ≫ 8bit

DAC_OUT = (GAIN_DAC
2

1

1

2

4

+ ) ∙ DAC_IN + 2∙OFFSET_DAC +(delimited to 16bit-MSB positive number range)

Equation 24

Complete:
Equation 25

DAC_IN = DAC_in_orig ≫ 8bit

GAIN_DAC + 215
DAC_OUT = [[∙ DAC_IN] + 2∙OFFSET_DAC + 214 ]216

216 −1Equation 26

0

The DAC output signal correction is not applied and the corresponding digital value is used for generating the
DAC output signal without correction in the following cases:•

the DAC Diagnostic command (B3HEX) is used to force the DAC output•

DAC outputs of the sensor-diagnostic are enabled (diagouten) and a valid diagnostic and failure event (forexample, Sensor connection check failure) is detected•

DAC clipping is enabled and the digital main sSC corrected signal (S or T) already reached a programmedclipping limit.

Feb.2.24

Page 65

ZSSC3241

6.7

Datasheet

External, Extra LDO (LDOctrl) for Applications for > 5.5V

The ZSSC3241 has integrated voltage regulators that generate separate analog and digital ZSSC3241-internal
voltages for any valid external supply voltage, VDD (2.7V to 5.5V). For proper ZSSC3241 function, the directly
applied supply voltage should not exceed the maximum VDD limit.
The ZSSC3241 also supports applications with higher application-inherent supply voltages greater than 5.5V.
The ZSSC3241 provides a voltage regulation signal at the LDOctrl pin and a programmable IC supply, i.e. V DDlevel regulation target level, VDD_ldoctrl_target in the SSF2 register. The use of an additional external regulatortransistor (by means of, for example JFET, depletion MOSFET, or comparable) further improves the powersupply rejection ratio (PSRR); i.e., it reduces effects from the external supply voltage onto the sensor
measurement results in addition to the ZSSC3241-internal regulator properties. If the external extra supply
regulation is not used or needed, the respective feature should be disabled by disable_ldoctrl = 1BIN.
Table 38.

IC Supply, VDD Target Level Selection with External Voltage Regulation, External LDO
VDD_ldoctrl_target
Bit[1]

Bit[0]

0
0
1
1

0
1
0
1

VDD Target Level

Notes

4.8V
5.0V
5.2V
5.4V

Recommended, typical settings.

Recommendation: Use the clamping diode at VDD (to FB for current-loop output configurations or to VSS in allother cases with external LDO as shown by gray dashed line in Figure 27) to ensure over-voltage protection at
the initial application power-on. The external transistor, depicted as JFET 1 can be a real JFET type, or, forexample, depletion MOSFET and comparable. It must be selected such that the drain-source voltage can be atleast VDDext – 5V.
ISEN SOR + IIC
IC-Internal
Regulators
VDDA

LDO Control /Regulation

VDDD

Application Supply
VDDext > 5.5V

LDOctrl

Digital Core

Analog Front-End- IC Control- Memory- SSC Math- Internal Temp.Sensor
- PGA
- ADC
- inMUX

AOUT

Analog Output

VSS

ZSSC3241

JFET

VDD

- DAC
- AOUT Driver Stages- MUXout

CVDD

FB

LDO control circuitry

Figure 28. LDOctrl Application Topology
Table 39.

1

External LDO Operating Conditions

SymbolParameter

Minimum

TypicalMaximum

Units

Cctrl
CVDD

Allowed parasitic capacitance at LDOctrl pin
Buffer/filter capacitance between VDD and VSS

–
80

150
100

500
120

pF
nF

Depending on the VDDext>5.5V application main supply, different external transistors can be applied, for example BSS169 (Infineon),
DN3545N8 (Microchip-Supertex), MMBF4392LT1G (Fairchild), etc.

Feb.2.24

Page 66

ZSSC3241

7.

Datasheet

Calibration

Calibration essentially involves collecting raw signal and temperature data from the sensor-ZSSC3241 systemfor different known sensor-element values (i.e., for a resistive bridge or an absolute voltage source) andtemperatures. This raw data can then be processed by the calibration master (assumed to be the user’s
computer), and the calculated calibration coefficients can then be written to on-chip memory.
Brief overview of the three mains steps involved in calibrating the ZSSC3241:
1. Assigning a unique identification to the ZSSC3241. This identification is written to shadow RAM andprogrammed in NVM. This unique identification can be stored in the two 16-bit registers dedicated to thecustomer ID. It can be used as an index into a database stored on the calibration PC. This database willcontain all the raw values of the connected sensor-element readings and temperature readings for that part,as well as the known sensor-element measurand conditions and temperature to which the sensor-element
was exposed.
2. Data collection. Data collection involves getting uncorrected (raw) data from the external sensor at different
known measurand values and temperatures. Then this data is stored on the calibration master using theunique identification of the device as the index to the database.
3. Coefficient calculation and storage in NVM. After enough data points have been collected to calculate all thedesired coefficients, the coefficients can be calculated by the calibration master. Then the coefficients can be
programmed to the memory.
4. Result. The sensor signal and the characteristic temperature effect on output will be linearized according to
the setup-dependent maximum output range.
It is essential to perform the calibration with a fixed programming setup during the data collection phase.
Strong recommendation: To prevent any accidental misprocessing, keep the sensor front-end NVM setup(registers SSF1, SSF2, SM_config1, SM_config2, extTemp_config1, extTemp_config2) stable during the entire
calibration process as well as in the subsequent operation.
Note: A ZSSC3241 calibration only fits the setup used during its calibration. Changes of functional parameters
after a successful calibration can decrease the precision and accuracy performance of the ZSSC3241 as well asof the entire application.

8.

Package Outline Drawings

The package outline drawings are appended at the end of this document and are accessible from the links
below. The package information is the most current data available.
•

Generally valid summary information:•

Specific package outline drawing:https://www.renesas.com/eu/en/document/psc/24-vfqfpn-packageoutline-drawing-40-x-40-x-085-mm-body-050mm-pitch-epad-250-x-250-mm-wettableflank?language=en&r=710

9.

https://www.renesas.com/eu/en/package/nlg24

Marking Diagram
3241D
YYWW
XXXXX

Feb.2.24

1. Line 1 is the truncated part number.
2. Line 2 – “YYWW” are the last two digits of the year andweek that the part was assembled.

3.

Line 3 – “XXXXX” denotes assembly lot number.

Page 67

ZSSC3241

Datasheet

10. Ordering Information
Orderable Part Number

Description and Package

ZSSC3241DI1B

MSL Rating

Carrier Type

Temperature

DICE on 304µm wafer no inking

Wafer Box

-40 to 125°C

ZSSC3241DI1C

Sawn DICE on frame, 304µm wafer, no inking

Wafer Box

-40 to 125°C

ZSSC3241DI5B

DICE on 304µm wafer with inking

Wafer Box

-40 to 125°C

ZSSC3241DI5C

Sawn DICE on frame, 304µm wafer, with inking

Wafer Box

-40 to 125°C

ZSSC3241DI3R

2

4  4 mm 24-QFN

MSL1

13 inch Reel

-40 to 125°C

ZSSC3241DI3W

4  4 mm 24-QFN

MSL1

7 inch Reel

-40 to 125°C

ZSSC3241DL1B

DICE on 304µm wafer no inking, pre-configured for
Current-Loop

Wafer Box

-40 to 125°C

ZSSC3241DL1C

Sawn DICE on frame, 304µm wafer, no inking, preconfigured for Current-Loop

Wafer Box

-40 to 125°C

ZSSC3241DL5B

DICE on 304µm wafer with inking, pre-configured for
Current-Loop

Wafer Box

-40 to 125°C

ZSSC3241DL5C

Sawn DICE on frame, 304µm wafer, with inking, preconfigured for Current-Loop

Wafer Box

-40 to 125°C

ZSSC3241DL3R

4  4 mm2 24-QFN, pre-configured for Current-LoopMSL1

13 inch Reel

-40 to 125°C

ZSSC3241DL3W

4  4 mm 24-QFN, pre-configured for Current-LoopMSL1

7 inch Reel

-40 to 125°C

ZSSC3241KIT

Modular ZSSC3241 SSC Evaluation Kit including three interconnecting boards, five ZSSC3241 24-VFPQFN
samples, and cable. Software is available for download on www.renesas.com/zssc3241KIT.

2

2

11. Glossary
Term
A2D
ACK
ADC
AGND
AZ
AZS
AZT
CLK
DAC
EMC
EMI
EOC
FSO
I2C
LFSR
LSB
MSB
MSL
NACK
NVM
Op amp
PGA
POR
PPT
PSRR
PTC
S
SM
SOT
SPI

Feb.2.24

Description
Analog-to-Digital
Acknowledge (interface’s protocol indicator for successful data/command transfer)
Analog-to-Digital Converter or Conversion
Analog-Ground, ZSSC3241-internal … VDDAint/2
Auto-Zero (unspecific)
Auto-Zero Measurement for (External) Sensor Path
Auto-Zero Measurement for (External or Internal) Temperature Path
Clock
Digital-to-Analog Converter or Conversion
Electromagnetic Compatibility
Electromagnetic Immision (Immunity), i.e. immunity on spuriously coupled high-frequency disturbances
End of Conversion
Full Scale Output (value in percent relative to the ADC maximum output code; resolution dependent)Inter-Integrated Circuit (I-Squared-C), asynchronous serial communication bus
Linear Feedback Shift Register
Least Significant Bit
Most Significant Bit
Moisture Sensitivity Level
Not Acknowledge (interface’s protocol indicator for unsuccessful data/command transfer)
Nonvolatile Memory
Operating Amplifier
Programmable Gain Amplifier
Power-On ResetParts-per-Thousand, 1PPT=1/1000
Power Supply (Disturbance) Rejection Ratio
Positive Temperature Coefficient (sensing element)
SSC-corrected Sensor Readout / Result
Sensor Measurement
Second Order Term
Serial Peripheral Interface, synchronous serial communication interface

Page 68

ZSSC3241

Datasheet

Term
SSF
T
TC

Description
Smart-Sensor Function (specific NVM registers)
SSC-corrected (extra) Temperature Readout / Result
Temperature Coefficient

12. Revision History
Revision Date

Description of Change

Feb.2.24• Correction of register assignment for parameters Low_Clip_Lim, Up_Clip_Lim• QFN Exposed PAD recommendation changed• AOUT short circuit information added in pin description• Additional note to DAC-Diagnostic

Jul.14.23

Threshold value correction of Vhigh,I2C; Vlow,I2C and Vhigh,SPI; Vlow,SPI

Mar.29.23

Initial releaseFeb.2.24

Page 69

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