VEML6040
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RGBW Color Sensor with I2C Interface
FEATURES• Package type: surface mount• Dimensions (L x W x H in mm): 2.0 x 1.25 x 1.0• Integrated modules: color sensor (RGBW) andsignal conditioning IC• FiltronTM technology provides a spectrum
matching real human eye responses• Supports low transmittance (dark) lens design• Fluorescent light flicker immunity• Provides 16-bit resolution for each channel(R, G, B, W)

DESCRIPTIONVEML6040 color sensor senses red, green, blue, and whitelight and incorporates photodiodes, amplifiers, and analog /digital circuits into a single chip using CMOS process. With
the color sensor applied, the brightness, and color
temperature of backlight can be adjusted base on ambient
light source that makes panel looks more comfortable forend user’s eyes. VEML6040’s adoption of FiltronTM
technology achieves the closest ambient light spectral
sensitivity to real human eye responses.
VEML6040 provides excellent temperature compensation
capability for keeping the output stable under changing
temperature. VEML6040’s function are easily operated
via the simple command format of I2C (SMBus compatible)
interface protocol. VEML6040’s operating voltage ranges
from 2.5 V to 3.6 V. VEML6040 is packaged in alead (Pb)-free 4 pin OPLGA package which offers thebest market-proven reliability.

• Selectable maximum detection range (360, 721, 1442,
2883, 5767, or 11 796) lux with highest sensitivity
0.0056 lux/step• Package: OPLGA• Temperature compensation: -40 °C to +85 °C• Low power consumption I2C (SMBus compatible)
interface• Floor life: 168 h, MSL 3, according to J-STD-020• Output type: I2C bus• Operation voltage: 2.5 V to 3.6 V• Material categorization: for definitions of complianceplease see www.vishay.com/doc?99912

APPLICATIONS• Handheld device• Notebook• Consumer device• Industrial and mechanical application

PRODUCT SUMMARYPART NUMBER
VEML6040

OPERATING
VOLTAGE RANGE(V)

I2C BUSVOLTAGE RANGE(V)PEAK SENSITIVITY(nm)

RANGE OF SPECTRALBANDWIDTH λ0.5
(nm)

OUTPUT CODE

2.5 to 3.6

1.7 to 3.6

650, 550, 450 (R, G, B)± 35, ± 35, ± 40 (R, G, B)

16 bit, I2C

Note(1) Adjustable through I2C interface

ORDERING INFORMATIONORDERING CODE

PACKAGING

VOLUME (1)REMARKSVEML6040A3OG

Tape and reel

MOQ: 2500 pcs

2.0 mm x 1.25 mm x 1.0 mm

Note
MOQ: minimum order quantity(1)

ABSOLUTE MAXIMUM RATINGS (Tamb = 25 °C, unless otherwise specified)
PARAMETERTEST CONDITIONSYMBOL

MIN.

MAX.

UNIT

Supply voltage

VDD

0

3.6

V

Operation temperature range

Tamb

-40

+85

°C

Storage temperature range

Tstg

-40

+85

°C

Rev. 1.2, 02-Mar-15

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RECOMMENDED OPERATING CONDITIONS (Tamb = 25 °C, unless otherwise specified)
PARAMETERTEST CONDITIONSYMBOL

MIN.

MAX.

UNIT

VDD

2.5

3.6

V

Operation temperature range

Tamb

-40

+85

°C

I2C bus operating frequencyf(I2CCLK)

10

400

kHz

Supply voltage

PIN DESCRIPTIONSPIN ASSIGNMENTSYMBOL

TYPE

1

GND

I

FUNCTION
Ground2

SDAT

I / O (open drain)

I2C data bus data input / output

3

SCLK

I

I2C digital bus clock input

4

VDD

I

Power supply input

BLOCK DIAGRAM
VDDControl
Logic

SDAT

State machine2
I C bus interface(slave)SCLK

GNDBASIC CHARACTERISTICS (Tamb = 25 °C, unless otherwise specified)
PARAMETERSYMBOL

MIN.

Supply voltage

TEST CONDITION

VDD

2.5

Supply current

IDD
Logic highI2C signal input

Logic low
Logic highLogic low

VDD = 3.3 V
VDD = 2.6 V

Peak sensitivity wavelength

0.8
1.4
0.6

VIL

V
V

λPR

650

nm

550

nm

λPB

450

nm

144

λPB = 467 nm

52

Minimum

G channel, IT = 1280 ms (1)(2)0.0056

Maximum

G channel, IT = 40 ms (1)(2)

11 796

G channel, IT = 80 ms (1)TambLight condition = dark, VDD = 3.6 V

V

λPG

λPG = 530 nm

Operating temperature range

UNIT
μA

1.5

180

Dark offset
Shutdown current

200

VIL
VIH

MAX.
3.6

λPR = 630 nm
Irradiance responsivity

Detectable intensity

VIH

TYP.

IDD

LSB/(μW/cm2)

lx

0

3

-40

+85
800

°C
nA

Notes
(1) Test condition: V
DD = 3.3 V, temperature: 25°C
(2) Light source: white LED
Rev. 1.2, 02-Mar-15

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I2C BUS TIMING CHARACTERISTICS (Tamb = 25 °C, unless otherwise specified)
PARAMETERSYMBOL

Clock frequency

STANDARD MODE
MIN.

MAX.
100

FAST MODE
MIN.

MAX.

10

400

UNIT

f(SMBCLK)10

Bus free time between start and stop conditiont(BUF)

4.7

1.3

μs

Hold time after (repeated) start condition;
after this period, the first clock is generatedt(HDSTA)

4.0

0.6

μs

Repeated start condition setup timet(SUSTA)

4.7

0.6

μs

Stop condition setup timet(SUSTO)

4.0

0.6

μs

Data hold timet(HDDAT)

200

90

ns

Data setup timet(SUDAT)

250

100

ns

I2C clock (SCK) low periodt(LOW)

4.7

1.3

μs

t(HIGH)

4.0t(TIMEOUT)

25

I2C clock (SCK) high period
Detect clock / data low timeout

kHz

0.6

μs

35

ms

Clock / data fall time

t(F)

300

300

ns

Clock / data rise time

t(R)

1000

300

ns

t(LOW)

t(R)

t(F)

VIH

I2CBusCLOCK(SCLK)VILt(HDSTA)P
Stop Conditiont(SUSTA)t(SUSTO)t(BUF)

I2CBusDATA(SDAT)t(HIGH)t(HDDAT)t(SUDAT)

VIH
VIL

S
Star Condition

S

P

Fig. 1 - I2C Bus Timing Diagram

Rev. 1.2, 02-Mar-15

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PARAMETER TIMING INFORMATIONACK byVEML6040

ACK byVEML6040

ACK byVEML6040

ACK byVEML6040

Fig. 2 - I2C Bus Timing for Sending Word Command Format

ACK byVEML6040

ACK byVEML6040

ACK byVEML6040

Fig. 3 - I2C Bus Timing for Receiving Word Command Format
Rev. 1.2, 02-Mar-15

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TYPICAL PERFORMANCE CHARACTERISTICS (Tamb = 25 °C, unless otherwise specified)
Axis Title
100

10000

80

W-CH

70

1000

60

1st line
2nd line

2nd line
Normalized Output (%)

90

R-CH

50

G-CH

40

100

30
B-CH

20
10
0
400

500

600

700

800

900

10
1000

λ - Wavelength (nm)
2nd line

Fig. 4 - Normalized Spectral Response

Fig. 5 - Normalized Output vs. View Angle

APPLICATION INFORMATION
Pin Connection with the Host
VEML6040 integrates R, G, B, and W sensor together with I2C interface. It is very easy for the baseband (CPU) to access
VEML6040 output data via I2C interface without extra software algorithms. The hardware schematic is shown in the following
diagram.
The 0.1 μF capacitor near the VDD pin is used for power supply noise rejection. The 2.2 kΩs are suitable for the pull-up resistorsof I2C.

VEML6040

Fig. 6 - Hardware Pin Connection Diagram

Rev. 1.2, 02-Mar-15

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Digital Interface
VEML6040 apply slave address 0x10 of 7 bit addressing protocol for I2C. VEML6040 contains an 8-bit command register
following each of slave address as shown in figure 7. All operations can be controlled by the command register. The simple
command structure helps users easily program the operation setting and latch the light data from VEML6040. Following I2C
command format is simple for read and write operations between VEML6040 and the host as shown in figure 7. The white
sections indicate host activity and the gray sections indicate VEML6040’s acknowledgement of the host access activity. Basedon write word protocol, 8-bit command codes can be written by the host under the same slave address. For data reading,
VEML6040 apply read word protocol.
Send Byte ɦ Write Command to VEML6040
1

7

1

1

8

1

8

1

8

1

1

S

Slave address

Wr

A

Command code

A

Data byte low

A

Data byte highA

P

Receive Byte ɦ Read Data from VEML6040
1

7

1

1

8

1

1

7

1

1

8

1

8

1

1

S

Slave address

Wr

A

Command code

A

S

Slave address

Rd

A

Data byte low

A

Data byte highAP

S = start condition
P = stop condition
A = acknowledge
Shaded area = VEML6040 acknowledge

Fig. 7 - Command Protocol Format

Slave Address and Function Description
VEML6040 uses 0x10 slave address for 7-bit I2C addressing protocol. VEML6040 has 16-bit resolution for each channel (R, G,
B, and W) that provides sensitivity up to 0.0056 lux/step for G, which is advantageous under a low transmittance lens design(dark lens).

TABLE 1 - SLAVE ADDRESS AND COMMAND CODE DESCRIPTIONSLAVE ADDRESS 0x10
COMMAND
CODE

BIT

REGISTER
NAME

R/W

00H_L

CONF

R/W

0

00H_H

Reserved

R/W

Reserved

01H to 07H

Reserved

R/W

Reserved

08H_L

R_DATA_L

R

R_Data (7 : 0)08H_H

R_DATA_M

R

R_Data (15 : 8)

09H_L

G_DATA_L

R

G_Data (7 : 0)09H_H

G_DATA_M

R

G_Data (15 : 8)0AH_L

B_DATA_L

R

B_Data (7 : 0)0AH_H

B_DATA_M

R

B_Data (15 : 8)0BH_L

W_DATA_L

R

W_Data (7 : 0)0BH_H

W_DATA_M

R

W_Data (15 : 8)7

6

5
IT (2 : 0)

4

3

2

1

0

0

TRIG

AF

SD

Note
• Slave address is 7-bit addressing protocol

Rev. 1.2, 02-Mar-15

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Command Register Format
VEML6040 provides an 8-bit command register for controlling. The description of each command format is shown in thefollowing tables. Color sensor is function compatible with ambient light sensor when apply color sensor at green channel.
Color Sensor Command

TABLE 2-1 - COMMAND CODE 00H BITS DESCRIPTIONSLAVE ADDRESS: 0x10; REGISTER NAME: CONF; COMMAND CODE: 00H / DATA BYTE LOW
X

IT

X

TRIG

AF

SD

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

0

IT2

IT1

IT0

0

TRIG

AF

SD

DESCRIPTION
IT

Integration time setting

TRIG

Proceed one detecting cycle at manual force mode

AF

Auto / manual force modeSD

Chip shutdown setting

TABLE 2-2 - COMMAND CODE 00H REGISTER SETTING
BITS SETTINGBIT 7

DESCRIPTION

BITS SETTING

Default = 0

BIT 3

Default = 0(0 : 0 : 0) = 40 ms

BIT 2
TRIG

0 = no trigger
1 = trigger one time detect cycle

BIT 1
AF

1 = force mode

BIT 0
SD

1 = disable color sensor(0 : 0 : 1) = 80 ms(0 : 1 : 0) = 160 ms

BIT 6, 5, 4
IT (2 : 0)

(0 : 1 : 1) = 320 ms(1 : 0 : 0) = 640 ms(1 : 0 : 1) = 1280 ms

DESCRIPTION

0 = auto mode0 = enable color sensor

TABLE 3-1 - RESERVE COMMAND CODE DESCRIPTIONRESERVEDCOMMAND CODE: 00H / DATA BYTE HIGH

Command

Bit

Reserved

7:0

Description
Default = 00H

TABLE 3-2 - RESERVE COMMAND CODE DESCRIPTIONRESERVEDCOMMAND CODE: 01H TO 07H

Command

Bit

Reserved

7:0

Description
Default = 00H

TABLE 4 - READ OUT COMMAND CODE DESCRIPTIONCOMMAND CODEREGISTER

BIT

DESCRIPTION

08H_L (08H data byte low)

R_DATA_L

7:0

00H to FFH, R channel LSB output data
00H to FFH, R channel MSB output data

08H_H (08H data byte high)

R_DATA_M

7:0

09H_L (09H data byte low)

G_DATA_L

7:0

00H to FFH, G channel LSB output data

09H_H (09H data byte high)

G_DATA_M

7:0

00H to FFH, G channel MSB output data

0AH_L (0AH data byte low)

B_DATA_L

7:0

00H to FFH, B channel LSB output data

0AH_H (0AH data byte high)

B_DATA_M

7:0

00H to FFH, B channel MSB output data

0BH_L (0BH data byte low)

W_DATA_L

7:0

00H to FFH, W channel LSB output data

0BH_H (0BH data byte high)

W_DATA_M

7:0

00H to FFH, W channel MSB output data

Rev. 1.2, 02-Mar-15

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Data Access
VEML6040 has 16-bit high resolution sensitivity for each channel of color sensor (R,G,B, and W). To represent the 16-bit data,it has to apply two bytes. One byte is for LSB and the other byte is for MSB. The host needs to follow the read word protocol
as shown in figure 7. The data format shows as below.

TABLE 5 - 16-BIT DATA FORMATVEML6040 16-BIT DATA FORMAT
Data bit

15

14

13

12

11

Command code

A

10

9

8

7

6

5

4

3

2

1

0

Data byte low
Data byte highNotes
SSlave address

Wr

A

S

Slave address

Rd

A

Data byte low

A

Data byte highAP

• Data byte low represents LSB and data byte high represents MSB.
• To read color data, for example, R channel the following should be written: 10H-08H-11H and then the 16 bit result is available. Commandcode for R, G, B, and W channel data is 08H, 09H, 0AH, and 0BH respectively.

The integration time settings result in the corresponding resolutions that are shown in table 6.

TABLE 6 - G CHANNEL RESOLUTION AND MAXIMUM DETECTION RANGEIT SETTINGG SENSITIVITY

IT (2 : 0)

INTEGRATION TIME

(0 : 0 : 0)40 ms

(0 : 0 : 1)

80 ms

0.09

(0 : 1 : 0)

160 ms0.045(0 : 1 : 1)

320 ms

0.02250.18(1 : 0 : 0)640 ms

0.01125(1 : 0 : 1)1280 ms

0.005625

G integration time = 40 ms

11 796 lux

Data Auto-Memorization
VEML6040 can memorize the last ambient light data before shutting down and keeps this data before waking up again. When
VEML6040 is in shutdown mode, the host can freely read this data directly via read command. When VEML6040 wakes up, thedata is refreshed by a newly acquired detection.

Rev. 1.2, 02-Mar-15

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PACKAGE INFORMATION in millimeters0.45 ± 0.05

X

X

1

4

0.70

1.25 ± 0.15

0~0.064

1

1.10

0~0.050.35 ± 0.05

2.00 ± 0.15

0.25

TOP VIEW

X

X

3

2
0.1

3

0~0.042

0.625± 0.15

0~0.020.55 ± 0.05

1.00± 0.15

1.0

SIDE VIEW

DIE

1± 0.100.45
0.56

30um ± 10 um

VEML6040 Pin-out assignment
1

GND

2

SDAT

3

SCLK

4

VDD

Unit: mm0.1

Fig. 8 - VEML6040 A3OG Package Dimensions

LAYOUT NOTICE AND REFERENCE CIRCUIT in millimeters

Fig. 9 - VEML6040 PCB Layout Footprint

Rev. 1.2, 02-Mar-15

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APPLICATION CIRCUIT BLOCK REFERENCEVEML6040

Fig. 10 - VEML6040 Application Circuit

RECOMMENDED STORAGE AND REBAKING CONDITIONSPARAMETERCONDITIONS

MIN.

MAX.

UNIT

5

50

°C

Relative humidity

60%

Open time

168hStorage temperature

Total time
Rebaking

From the date code on the aluminized envelope (unopened)

12

monthsTape and reel: 60 °C

22h

Tube: 60 °C

22h

RECOMMENDED INFRARED REFLOW
Soldering conditions which are based on J-STD-020 C

IR REFLOW PROFILE CONDITIONPARAMETER
Peak temperature
Preheat temperature range and timing

CONDITIONSTEMPERATURE

10 s

150 °C to 200 °C

60 s to 180 s

217 °C

60 s to 150 s

Timing within 5 °C to peak temperature
Timing maintained above temperature / time

10 s to 30 s

Timing from 25 °C to peak temperature

8 min (max.)

Ramp-up rate

3 °C/s (max.)

Ramp-down rate

6 °C/s (max.)

Rev. 1.2, 02-Mar-15

TIME

255 °C + 0 °C / - 5 °C (max.: 260 °C)

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Temperature (ºC)

Recommend Normal Solder Reflow is 235 °C to 255 °C

Fig. 11 - VEML6040 OPLGA Solder Reflow Profile Chart

RECOMMENDED IRON TIP SOLDERING CONDITION AND WARNING HANDLING
1. Solder the device with the following conditions:1.1. Soldering temperature: 400 °C (max.)
1.2. Soldering time: 3 s (max.)
2. If the temperature of the method portion rises in addition to the residual stress between the leads, the possibility that anopen or short circuit occurs due to the deformation or destruction of the resin increases.
3. The following methods: VPS and wave soldering, have not been suggested for the component assembly.
4. Cleaning method conditions:4.1. Solvent: methyl alcohol, ethyl alcohol, isopropyl alcohol
4.2. Solvent temperature < 45 °C (max.)
4.3. Time: 3 min (min.)Rev. 1.2, 02-Mar-15

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TAPE PACKAGING INFORMATION in millimeters

Fig. 12 - VEML6040 A3OG Package Carrier Tape

Fig. 13 - Taping Direction

Fig. 14 - Reel Dimensions

Rev. 1.2, 02-Mar-15

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ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVERELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
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Statements regarding the suitability of products for certain types of applications are based on Vishay’s knowledge of typicalrequirements that are often placed on Vishay products in generic applications. Such statements are not binding statements
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product with the properties described in the product specification is suitable for use in a particular application. Parametersprovided in datasheets and/or specifications may vary in different applications and performance may vary over time. All
operating parameters, including typical parameters, must be validated for each customer application by the customer’s
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Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as RoHS-Compliant fulfill thedefinitions and restrictions defined under Directive 2011/65/EU of The European Parliament and of the Councilof June 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment(EEE) - recast, unless otherwise specified as non-compliant.
Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that
all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU.
Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as Halogen-Free follow Halogen-Free
requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference
to the IEC 61249-2-21 definition. We confirm that all the products identified as being compliant to IEC 61249-2-21
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