PIC18F2455/2550/4455/4550
Data Sheet
28/40/44-Pin, High Performance,
Enhanced Flash, USB Microcontrollers
with nanoWatt Technology© 2007 Microchip Technology Inc.

DS39632D

Note the following details of the code protection feature on Microchip devices:•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in theintended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to ourknowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

•

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does notmean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such actsallow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device
applications and the like is provided only for your convenienceand may be superseded by updates. It is your responsibility toensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely atthe buyer’s risk, and the buyer agrees to defend, indemnify andhold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses areconveyed, implicitly or otherwise, under any Microchip
intellectual property rights.

Trademarks
The Microchip name and logo, the Microchip logo, Accuron,dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,PRO MATE, PowerSmart, rfPIC and SmartShunt areregistered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,SEEVAL, SmartSensor and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active
Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit,
PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,
PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB,
rfPICDEM, Select Mode, Smart Serial, SmartTel, Total
Endurance, UNI/O, WiperLock and ZENA are trademarks ofMicrochip Technology Incorporated in the U.S.A. and othercountries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of theirrespective companies.
© 2007, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler andTempe, Arizona, Gresham, Oregon and Mountain View, California. The
Company’s quality system processes and procedures are for its PIC®
MCUs and dsPIC DSCs, KEELOQ® code hopping devices, Serial
EEPROMs, microperipherals, nonvolatile memory and analog
products. In addition, Microchip’s quality system for the design andmanufacture of development systems is ISO 9001:2000 certified.

DS39632D-page ii© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
28/40/44-Pin, High-Performance, Enhanced Flash,
USB Microcontrollers with nanoWatt Technology
Universal Serial Bus Features:

Peripheral Highlights:• USB V2.0 Compliant• Low Speed (1.5 Mb/s) and Full Speed (12 Mb/s)• Supports Control, Interrupt, Isochronous and Bulk
Transfers• Supports up to 32 Endpoints (16 bidirectional)• 1-Kbyte Dual Access RAM for USB• On-Chip USB Transceiver with On-Chip Voltage
Regulator• Interface for Off-Chip USB Transceiver• Streaming Parallel Port (SPP) for USB streamingtransfers (40/44-pin devices only)• High-Current Sink/Source: 25 mA/25 mA• Three External Interrupts• Four Timer modules (Timer0 to Timer3)• Up to 2 Capture/Compare/PWM (CCP) modules:- Capture is 16-bit, max. resolution 5.2 ns (TCY/16)- Compare is 16-bit, max. resolution 83.3 ns (TCY)- PWM output: PWM resolution is 1 to 10-bit• Enhanced Capture/Compare/PWM (ECCP) module:- Multiple output modes- Selectable polarity- Programmable dead time
- Auto-shutdown and auto-restart• Enhanced USART module:- LIN bus support• Master Synchronous Serial Port (MSSP) module
supporting 3-wire SPI (all 4 modes) and I2C™
Master and Slave modes• 10-bit, up to 13-channel Analog-to-Digital Converter
module (A/D) with Programmable Acquisition Time• Dual Analog Comparators with Input Multiplexing

Power-Managed Modes:• Run: CPU on, peripherals on• Idle: CPU off, peripherals on• Sleep: CPU off, peripherals off• Idle mode currents down to 5.8 μA typical• Sleep mode currents down to 0.1 μA typical• Timer1 Oscillator: 1.1 μA typical, 32 kHz, 2V• Watchdog Timer: 2.1 μA typical• Two-Speed Oscillator Start-up

Special Microcontroller Features:

Flexible Oscillator Structure:• C Compiler Optimized Architecture with optional
Extended Instruction Set• 100,000 Erase/Write Cycle Enhanced Flash
Program Memory typical• 1,000,000 Erase/Write Cycle Data EEPROM
Memory typical• Flash/Data EEPROM Retention: > 40 years• Self-Programmable under Software Control• Priority Levels for Interrupts• 8 x 8 Single-Cycle Hardware Multiplier• Extended Watchdog Timer (WDT):- Programmable period from 41 ms to 131s
• Programmable Code Protection• Single-Supply 5V In-Circuit Serial
Programming™ (ICSP™) via two pins
• In-Circuit Debug (ICD) via two pins
• Optional dedicated ICD/ICSP port (44-pin devices only)• Wide Operating Voltage Range (2.0V to 5.5V)
EAUSART

Comparators• Four Crystal modes, including High Precision PLL
for USB• Two External Clock modes, up to 48 MHz• Internal Oscillator Block:- 8 user-selectable frequencies, from 31 kHz
to 8 MHz- User-tunable to compensate for frequency drift• Secondary Oscillator using Timer1 @ 32 kHz• Dual Oscillator options allow microcontroller andUSB module to run at different clock speeds• Fail-Safe Clock Monitor:- Allows for safe shutdown if any clock stops

Timers
8/16-Bit

PIC18F2455

24K

12288

2048

256

24

10

2/0

No

Y

Y

1

2

1/3

PIC18F2550

32K

16384

2048

256

24

10

2/0

No

Y

Y

1

2

1/3

PIC18F4455

24K

12288

2048

256

35

13

1/1

Yes

Y

Y

1

2

1/3

PIC18F4550

32K

16384

2048

256

35

13

1/1

Yes

Y

Y

1

2

1/3

Program Memory
DeviceMSSP

Data Memory

Flash # Single-Word SRAM EEPROM(bytes) Instructions (bytes) (bytes)© 2007 Microchip Technology Inc.

I/O

10-Bit CCP/ECCP
A/D (ch)(PWM)Preliminary

SPP

SPI

Master
I2C™

DS39632D-page 1

PIC18F2455/2550/4455/4550
Pin Diagrams

1
2
3
4
5
6
7
8
9
10
11
12
13
14

PIC18F2455
PIC18F2550

MCLR/VPP/RE3
RA0/AN0RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT/RCV
RA5/AN4/SS/HLVDIN/C2OUT
VSS
OSC1/CLKI
OSC2/CLKO/RA6
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2(1)/UOE
RC2/CCP1
VUSB

28
27
26
25
24
23
22
21
20
19
18
17
16
15

RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/AN11/KBI0
RB3/AN9/CCP2(1)/VPO
RB2/AN8/INT2/VMO
RB1/AN10/INT1/SCK/SCL
RB0/AN12/INT0/FLT0/SDI/SDA
VDD
VSS
RC7/RX/DT/SDO
RC6/TX/CK
RC5/D+/VP
RC4/D-/VM

PIC18F4455
PIC18F4550

28-Pin PDIP, SOIC

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/AN11/KBI0/CSSPP
RB3/AN9/CCP2(1)/VPO
RB2/AN8/INT2/VMO
RB1/AN10/INT1/SCK/SCL
RB0/AN12/INT0/FLT0/SDI/SDA
VDD
VSS
RD7/SPP7/P1D
RD6/SPP6/P1C
RD5/SPP5/P1B
RD4/SPP4
RC7/RX/DT/SDO
RC6/TX/CK
RC5/D+/VP
RC4/D-/VM
RD3/SPP3
RD2/SPP2

40-Pin PDIP

MCLR/VPP/RE3
RA0/AN0RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT/RCV
RA5/AN4/SS/HLVDIN/C2OUT
RE0/AN5/CK1SPP
RE1/AN6/CK2SPP
RE2/AN7/OESPP
VDD
VSS
OSC1/CLKI
OSC2/CLKO/RA6
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2(1)/UOE
RC2/CCP1/P1A
VUSB
RD0/SPP0RD1/SPP1

Note 1:

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

RB3 is the alternate pin for CCP2 multiplexing.

DS39632D-page 2

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
RC6/TX/CK
RC5/D+/VP
RC4/D-/VM
RD3/SPP3
RD2/SPP2
RD1/SPP1
RD0/SPP0VUSB
RC2/CCP1/P1A
RC1/T1OSI/CCP2(1)/UOE
NC/ICPORTS(2)Pin Diagrams (Continued)

44
43
42
41
40
39
38
37
36
35
34

44-Pin TQFP

PIC18F4455
PIC18F4550

33
32
31
30
29
28
27
26
25
24
23

12
13
14
15
16
17
18
19
20
21
22

1
2
3
4
5
6
7
8
9
10
11

NC/ICRST(2)/ICVPP(2)RC0/T1OSO/T13CKI
OSC2/CLKO/RA6
OSC1/CLKI
VSS
VDD
RE2/AN7/OESPP
RE1/AN6/CK2SPP
RE0/AN5/CK1SPP
RA5/AN4/SS/HLVDIN/C2OUT
RA4/T0CKI/C1OUT/RCV

RC6/TX/CK
RC5/D+/VP
RC4/D-/VM
RD3/SPP3
RD2/SPP2
RD1/SPP1
RD0/SPP0VUSB
RC2/CCP1/P1A
RC1/T1OSI/CCP2(1)/UOE
RC0/T1OSO/T13CKI

NC/ICCK(2)/ICPGC(2)NC/ICDT(2)/ICPGD(2)RB4/AN11/KBI0/CSSPP
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
MCLR/VPP/RE3
RA0/AN0RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+

RC7/RX/DT/SDO
RD4/SPP4
RD5/SPP5/P1B
RD6/SPP6/P1C
RD7/SPP7/P1D
VSS
VDD
RB0/AN12/INT0/FLT0/SDI/SDA
RB1/AN10/INT1/SCK/SCL
RB2/AN8/INT2/VMO
RB3/AN9/CCP2(1)/VPO

44
43
42
41
40
39
38
37
36
35
34

44-Pin QFNPIC18F4455
PIC18F4550

33
32
31
30
29
28
27
26
25
24
23

12
13
14
15
16
17
18
19
20
21
22

1
2
3
4
5
6
7
8
9
10
11

OSC2/CLKO/RA6
OSC1/CLKI
VSS
VSS
VDD
VDD
RE2/AN7/OESPP
RE1/AN6/CK2SPP
RE0/AN5/CK1SPP
RA5/AN4/SS/HLVDIN/C2OUT
RA4/T0CKI/C1OUT/RCV

RB3/AN9/CCP2(1)/VPONC
RB4/AN11/KBI0/CSSPP
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
MCLR/VPP/RE3
RA0/AN0RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+

RC7/RX/DT/SDO
RD4/SPP4
RD5/SPP5/P1B
RD6/SPP6/P1C
RD7/SPP7/P1D
VSS
VDD
VDD
RB0/AN12/INT0/FLT0/SDI/SDA
RB1/AN10/INT1/SCK/SCL
RB2/AN8/INT2/VMO

Note 1:2:RB3 is the alternate pin for CCP2 multiplexing.
Special ICPORTS features available in select circumstances. See Section 25.9 “Special ICPORT Features (Designated
Packages Only)” for more information.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 3

PIC18F2455/2550/4455/4550
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 7
2.0 Oscillator Configurations ............................................................................................................................................................ 23
3.0 Power-Managed Modes ............................................................................................................................................................. 35
4.0 Reset .......................................................................................................................................................................................... 43
5.0 Memory Organization ................................................................................................................................................................. 57
6.0 Flash Program Memory .............................................................................................................................................................. 79
7.0 Data EEPROM Memory ............................................................................................................................................................. 89
8.0 8 x 8 Hardware Multiplier............................................................................................................................................................ 95
9.0 Interrupts .................................................................................................................................................................................... 97
10.0 I/O Ports ................................................................................................................................................................................... 111
11.0 Timer0 Module ......................................................................................................................................................................... 125
12.0 Timer1 Module ......................................................................................................................................................................... 129
13.0 Timer2 Module ......................................................................................................................................................................... 135
14.0 Timer3 Module ......................................................................................................................................................................... 137
15.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................. 141
16.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................ 149
17.0 Universal Serial Bus (USB) ...................................................................................................................................................... 163
18.0 Streaming Parallel Port ............................................................................................................................................................ 187
19.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 193
20.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 237
21.0 10-Bit Analog-to-Digital Converter (A/D) Module ..................................................................................................................... 259
22.0 Comparator Module.................................................................................................................................................................. 269
23.0 Comparator Voltage Reference Module ................................................................................................................................... 275
24.0 High/Low-Voltage Detect (HLVD)............................................................................................................................................. 279
25.0 Special Features of the CPU .................................................................................................................................................... 285
26.0 Instruction Set Summary .......................................................................................................................................................... 307
27.0 Development Support............................................................................................................................................................... 357
28.0 Electrical Characteristics .......................................................................................................................................................... 361
29.0 DC and AC Characteristics Graphs and Tables ....................................................................................................................... 399
30.0 Packaging Information.............................................................................................................................................................. 401
Appendix A: Revision History............................................................................................................................................................. 409
Appendix B: Device Differences......................................................................................................................................................... 409
Appendix C: Conversion Considerations ........................................................................................................................................... 410
Appendix D: Migration From Baseline to Enhanced Devices............................................................................................................. 410
Appendix E: Migration From Mid-Range to Enhanced Devices ......................................................................................................... 411
Appendix F: Migration From High-End to Enhanced Devices............................................................................................................ 411
Index .................................................................................................................................................................................................. 413
The Microchip Web Site ..................................................................................................................................................................... 425
Customer Change Notification Service .............................................................................................................................................. 425
Customer Support .............................................................................................................................................................................. 425
Reader Response .............................................................................................................................................................................. 426
PIC18F2455/2550/4455/4550 Product Identification System ............................................................................................................ 427

DS39632D-page 4

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
TO OUR VALUED CUSTOMERSIt is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined andenhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We
welcome your feedback.

Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

ErrataAn errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revisionof silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:• Microchip’s Worldwide Web site; http://www.microchip.com• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you areusing.

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Register on our web site at www.microchip.com to receive the most current information on all of our products.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 5

PIC18F2455/2550/4455/4550
NOTES:DS39632D-page 6

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
1.0

DEVICE OVERVIEW

1.1.3

This document contains device-specific information for
the following devices:• PIC18F2455• PIC18LF2455• PIC18F2550• PIC18LF2550• PIC18F4455• PIC18LF4455• PIC18F4550• PIC18LF4550

This family of devices offers the advantages of all
PIC18 microcontrollers – namely, high computational
performance at an economical price – with the additionof high endurance, Enhanced Flash program memory. In
addition to these features, thePIC18F2455/2550/4455/4550 family introduces design
enhancements that make these microcontrollers a logical choice for many high-performance, power sensitive
applications.

1.1
1.1.1

New Core Features
nanoWatt TECHNOLOGYAll of the devices in the PIC18F2455/2550/4455/4550
family incorporate a range of features that can significantly reduce power consumption during operation.
Key items include:• Alternate Run Modes: By clocking the controller
from the Timer1 source or the internal oscillator
block, power consumption during code execution
can be reduced by as much as 90%.
• Multiple Idle Modes: The controller can also run
with its CPU core disabled but the peripherals still
active. In these states, power consumption can be
reduced even further, to as little as 4% of normal
operation requirements.
• On-the-Fly Mode Switching: The
power-managed modes are invoked by user code
during operation, allowing the user to incorporate
power-saving ideas into their application’s
software design.
• Low Consumption in Key Modules: The power
requirements for both Timer1 and the Watchdog
Timer are minimized. See Section 28.0
“Electrical Characteristics” for values.

1.1.2

MULTIPLE OSCILLATOR OPTIONSAND FEATURES

All of the devices in the PIC18F2455/2550/4455/4550
family offer twelve different oscillator options, allowing
users a wide range of choices in developing application
hardware. These include:• Four Crystal modes using crystals or ceramic
resonators.
• Four External Clock modes, offering the option ofusing two pins (oscillator input and a divide-by-4
clock output) or one pin (oscillator input, with thesecond pin reassigned as general I/O).
• An internal oscillator block which provides an
8 MHz clock (±2% accuracy) and an INTRC
source (approximately 31 kHz, stable overtemperature and VDD), as well as a range of
6 user-selectable clock frequencies, between
125 kHz to 4 MHz, for a total of 8 clock
frequencies. This option frees an oscillator pin foruse as an additional general purpose I/O.
• A Phase Lock Loop (PLL) frequency multiplier,available to both the High-Speed Crystal andExternal Oscillator modes, which allows a wide
range of clock speeds from 4 MHz to 48 MHz.
• Asynchronous dual clock operation, allowing theUSB module to run from a high-frequency
oscillator while the rest of the microcontroller isclocked from an internal low-power oscillator.
Besides its availability as a clock source, the internal
oscillator block provides a stable reference source thatgives the family additional features for robust
operation:• Fail-Safe Clock Monitor: This option constantly
monitors the main clock source against areference signal provided by the internal
oscillator. If a clock failure occurs, the controller isswitched to the internal oscillator block, allowing
for continued low-speed operation or a safe
application shutdown.
• Two-Speed Start-up: This option allows theinternal oscillator to serve as the clock sourcefrom Power-on Reset, or wake-up from Sleep
mode, until the primary clock source is available.

UNIVERSAL SERIAL BUS (USB)

Devices in the PIC18F2455/2550/4455/4550 family
incorporate a fully featured Universal Serial Bus
communications module that is compliant with the USB
Specification Revision 2.0. The module supports both
low-speed and full-speed communication for all supported data transfer types. It also incorporates its own
on-chip transceiver and 3.3V regulator and supports
the use of external transceivers and voltage regulators.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 7

PIC18F2455/2550/4455/4550
1.2

Other Special Features

1.3• Memory Endurance: The Enhanced Flash cells
for both program memory and data EEPROM are
rated to last for many thousands of erase/write
cycles – up to 100,000 for program memory and
1,000,000 for EEPROM. Data retention without
refresh is conservatively estimated to be greaterthan 40 years.
• Self-Programmability: These devices can write totheir own program memory spaces under internal
software control. By using a bootloader routine,
located in the protected Boot Block at the top of
program memory, it becomes possible to create anapplication that can update itself in the field.
• Extended Instruction Set: The
PIC18F2455/2550/4455/4550 family introduces
an optional extension to the PIC18 instruction set,
which adds 8 new instructions and an Indexed
Literal Offset Addressing mode. This extension,
enabled as a device configuration option, hasbeen specifically designed to optimize re-entrant
application code originally developed in high-level
languages such as C.
• Enhanced CCP Module: In PWM mode, thismodule provides 1, 2 or 4 modulated outputs forcontrolling half-bridge and full-bridge drivers.
Other features include auto-shutdown fordisabling PWM outputs on interrupt or other selectconditions and auto-restart to reactivate outputs
once the condition has cleared.
• Enhanced Addressable USART: This serial
communication module is capable of standard
RS-232 operation and provides support for the LIN
bus protocol. Other enhancements include
Automatic Baud Rate Detection and a 16-bit Baud
Rate Generator for improved resolution. When the
microcontroller is using the internal oscillator
block, the EUSART provides stable operation for
applications that talk to the outside world without
using an external crystal (or its accompanying
power requirement).
• 10-Bit A/D Converter: This module incorporates
programmable acquisition time, allowing for achannel to be selected and a conversion to be
initiated, without waiting for a sampling period andthus, reducing code overhead.
• Dedicated ICD/ICSP Port: These devices
introduce the use of debugger and programming
pins that are not multiplexed with other microcontroller features. Offered as an option in selectpackages, this feature allows users to develop I/O
intensive applications while retaining the ability toprogram and debug in the circuit.

DS39632D-page 8

Details on Individual Family
Members

Devices in the PIC18F2455/2550/4455/4550 family areavailable in 28-pin and 40/44-pin packages. Block
diagrams for the two groups are shown in Figure 1-1
and Figure 1-2.
The devices are differentiated from each other in six
ways:
1.

2.
3.

4.

5.

Flash program memory (24 Kbytes for
PIC18FX455
devices,
32 Kbytes
for
PIC18FX550).
A/D channels (10 for 28-pin devices, 13 for
40/44-pin devices).
I/O ports (3 bidirectional ports and 1 input only
port on 28-pin devices, 5 bidirectional ports on
40/44-pin devices).
CCP and Enhanced CCP implementation(28-pin devices have two standard CCP
modules, 40/44-pin devices have one standard
CCP module and one ECCP module).
Streaming Parallel Port (present only on
40/44-pin devices).

All other features for devices in this family are identical.
These are summarized in Table 1-1.
The pinouts for all devices are listed in Table 1-2 andTable 1-3.
Like all Microchip PIC18 devices, members of the
PIC18F2455/2550/4455/4550 family are available asboth standard and low-voltage devices. Standard
devices with Enhanced Flash memory, designated withan “F” in the part number (such as PIC18F2550),
accommodate an operating VDD range of 4.2V to 5.5V.
Low-voltage parts, designated by “LF” (such as
PIC18LF2550), function over an extended VDD rangeof 2.0V to 5.5V.

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
TABLE 1-1:

DEVICE FEATURES

Features

PIC18F2455

PIC18F2550

PIC18F4455

PIC18F4550

Operating Frequency

DC – 48 MHz

DC – 48 MHz

DC – 48 MHz

DC – 48 MHz

Program Memory (Bytes)

24576

32768

24576

32768

Program Memory (Instructions)

12288

16384

12288

16384

Data Memory (Bytes)

2048

2048

2048

2048

Data EEPROM Memory (Bytes)

256

256

256

256

Interrupt Sources

19

19

20

20

I/O Ports

Ports A, B, C, (E)Ports A, B, C, (E)Timers4

4

Ports A, B, C, D, E Ports A, B, C, D, E
4

4Capture/Compare/PWM Modules

2

2

1

1

Enhanced Capture/
Compare/PWM Modules

0

0

1

1

Serial Communications

MSSP,
Enhanced USARTMSSP,Enhanced USARTMSSP,Enhanced USARTMSSP,Enhanced USART

1

1

1

1

Universal Serial Bus (USB)
ModuleStreaming Parallel Port (SPP)

No

No

Yes

Yes

10-Bit Analog-to-Digital Module

10 Input Channels

10 Input Channels

13 Input Channels

13 Input Channels

Comparators

2

2

2

2

POR, BOR,RESET Instruction,
Stack Full,
Stack Underflow(PWRT, OST),MCLR (optional),
WDT

POR, BOR,RESET Instruction,
Stack Full,
Stack Underflow(PWRT, OST),MCLR (optional),
WDT

POR, BOR,RESET Instruction,
Stack Full,
Stack Underflow(PWRT, OST),MCLR (optional),
WDT

POR, BOR,RESET Instruction,
Stack Full,
Stack Underflow(PWRT, OST),MCLR (optional),
WDT

Programmable Low-Voltage
Detect

Yes

Yes

Yes

Yes

Programmable Brown-out Reset

Yes

Yes

Yes

Yes

75 Instructions;
83 with Extended
Instruction Set
enabled75 Instructions;
83 with Extended
Instruction Set
enabled75 Instructions;
83 with Extended
Instruction Set
enabled75 Instructions;
83 with Extended
Instruction Set
enabled28-pin PDIP
28-pin SOIC

28-pin PDIP
28-pin SOIC

40-pin PDIP
44-pin QFN
44-pin TQFP

40-pin PDIP
44-pin QFN
44-pin TQFPResets (and Delays)

Instruction Set

Packages© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 9

PIC18F2455/2550/4455/4550
FIGURE 1-1:

PIC18F2455/2550 (28-PIN) BLOCK DIAGRAM
Data Bus<8>Table Pointer<21>

PORTA
8

inc/dec logic

Data Memory(2 Kbytes)

PCLATU PCLATH

21

RA0/AN0RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT/RCV
RA5/AN4/SS/HLVDIN/C2OUT
OSC2/CLKO/RA6

Data Latch

8

Address Latch

20
PCU PCH PCL
Program Counter

12
Data Address<12>

31 Level Stack
4
BSR

Address Latch
Program Memory(24/32 Kbytes)

STKPTR

Data Latch

4
Access
Bank

12
FSR0
FSR1
FSR2

12

PORTB
RB0/AN12/INT0/FLT0/SDI/SDA
RB1/AN10/INT1/SCK/SCL
RB2/AN8/INT2/VMO
RB3/AN9/CCP2(3)/VPO
RB4/AN11/KBI0
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD

inc/dec
logic

8
Table Latch

Address
DecodeROM Latch

Instruction Bus <16>IR

8
Instruction
Decode &ControlState Machine
Control Signals
PRODH PRODL
3

OSC1

(2)

Internal
Oscillator
Block

OSC2(2)
T1OSI

INTRC
Oscillator

T1OSO

8 MHz
Oscillator
Single-Supply
Programming
In-Circuit
Debugger

MCLR(1)
VDD, VSSPower-up
Timer
Oscillator
Start-up Timer
Power-onReset

RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2(3)/UOE
RC2/CCP1
RC4/D-/VM
RC5/D+/VP
RC6/TX/CK
RC7/RX/DT/SDO

8

BITOP
8

W

8

8
8

8

ALU<8>

Watchdog
Timer

8

Brown-out
Reset
Fail-Safe
Clock Monitor

PORTE

Band Gap
Reference

USB Voltage
Regulator

VUSB

PORTC

8 x 8 Multiply

MCLR/VPP/RE3(1)

BOR
HLVD

Data
EEPROM

Timer0Timer1

Timer2Timer3Comparator

CCP1

CCP2

MSSP

EUSART

ADC
10-BitNote 1:2:
3:USB

RE3 is multiplexed with MCLR and is only available when the MCLR Resets are disabled.
OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer
to Section 2.0 “Oscillator Configurations” for additional information.
RB3 is the alternate pin for CCP2 multiplexing.

DS39632D-page 10

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
FIGURE 1-2:

PIC18F4455/4550 (40/44-PIN) BLOCK DIAGRAM
Data Bus<8>

PORTA

Table Pointer<21>

Data Memory(2 Kbytes)

PCLATU PCLATH

21

RA0/AN0RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT/RCV
RA5/AN4/SS/HLVDIN/C2OUT
OSC2/CLKO/RA6

Data Latch

8

8inc/dec logic

Address Latch

20
PCU PCH PCL
Program Counter

12
Data Address<12>
PORTB

31 Level Stack
4
BSR

Address Latch
Program Memory(24/32 Kbytes)

STKPTR

Data Latch

12
FSR0
FSR1
FSR2

RB0/AN12/INT0/FLT0/SDI/SDA
RB1/AN10/INT1/SCK/SCL
RB2/AN8/INT2/VMO
RB3/AN9/CCP2(4)/VPO
RB4/AN11/KBI0/CSSPP
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD

4AccessBank
12inc/dec
logic

8
Table Latch

PORTC

Address
DecodeROM Latch

Instruction Bus <16>

RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2(4)/UOE
RC2/CCP1/P1A
RC4/D-/VM
RC5/D+/VP
RC6/TX/CK
RC7/RX/DT/SDO

IR

8Instruction
Decode &ControlState Machine
Control Signals
PRODH PRODL
PORTD
3

VDD, VSS
Internal
Oscillator
Block

OSC1(2)
OSC2(2)

Power-up
Timer

T1OSO
ICPGC(3)Single-Supply
Programming

ICPGD(3)ICPORTS(3)In-Circuit
Debugger

MCLR(1)

RD0/SPP0:RD4/SPP4
RD5/SPP5/P1B
RD6/SPP6/P1C
RD7/SPP7/P1D

8

8

8

ALU<8>

Watchdog
Timer

8

Brown-out
Reset
Fail-Safe
Clock Monitor

ICRST(3)W

8Power-on
Reset

8 MHz
Oscillator

8

BITOP
8

Oscillator
Start-up Timer

INTRC
Oscillator

T1OSI

8 x 8 Multiply

PORTE
RE0/AN5/CK1SPP
RE1/AN6/CK2SPP
RE2/AN7/OESPPMCLR/VPP/RE3(1)Band Gap
Reference

USB Voltage
Regulator

VUSB

BOR
HLVD

Data
EEPROM

Timer0Timer1

Timer2Timer3Comparator

ECCP1

CCP2

MSSP

EUSART

ADC
10-BitNote 1:
2:
3:
4:

USB

RE3 is multiplexed with MCLR and is only available when the MCLR Resets are disabled.
OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer
to Section 2.0 “Oscillator Configurations” for additional information.
These pins are only available on 44-pin TQFP packages under certain conditions. Refer to Section 25.9 “Special ICPORT Features(Designated Packages Only)” for additional information.
RB3 is the alternate pin for CCP2 multiplexing.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 11

PIC18F2455/2550/4455/4550
TABLE 1-2:

PIC18F2455/2550 PINOUT I/O DESCRIPTIONS
Pin
NumberPin
Type

Buffer
Type

I

ST

P
I

ST

I
I

AnalogAnalog

O

—

CLKO

O

—

RA6

I/O

TTL

Pin Name
PDIP,
SOIC
MCLR/VPP/RE3
MCLR

1

VPP
RE3
OSC1/CLKI
OSC1
CLKI

9

OSC2/CLKO/RA6
OSC2

10

Description

Master Clear (input) or programming voltage (input).
Master Clear (Reset) input. This pin is an active-low
Reset to the device.
Programming voltage input.
Digital input.
Oscillator crystal or external clock input.
Oscillator crystal input or external clock source input.
External clock source input. Always associated with pinfunction OSC1. (See OSC2/CLKO pin.)
Oscillator crystal or clock output.
Oscillator crystal output. Connects to crystal or resonator in
Crystal Oscillator mode.
In select modes, OSC2 pin outputs CLKO which has 1/4 thefrequency of OSC1 and denotes the instruction cycle rate.
General purpose I/O pin.

Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
I= Input
O = Output
P= Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.

DS39632D-page 12

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
TABLE 1-2:

PIC18F2455/2550 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin
NumberPin Name
PDIP,
SOIC

Pin
Type

BufferType

Description

PORTA is a bidirectional I/O port.
RA0/AN0
RA0
AN02

RA1/AN1
RA1
AN1

3

RA2/AN2/VREF-/CVREF
RA2
AN2
VREFCVREF

4

RA3/AN3/VREF+
RA3
AN3
VREF+

5

RA4/T0CKI/C1OUT/RCV
RA4
T0CKI
C1OUT
RCV

6

RA5/AN4/SS/
HLVDIN/C2OUT
RA5
AN4
SS
HLVDIN
C2OUT

7

RA6

—

I/O
I

TTL
AnalogDigital I/O.
Analog input 0.

I/O
I

TTL
AnalogDigital I/O.
Analog input 1.

I/O
I
I
O

TTL
AnalogAnalogAnalogDigital I/O.
Analog input 2.
A/D reference voltage (low) input.
Analog comparator reference output.

I/O
I
I

TTL
AnalogAnalogDigital I/O.
Analog input 3.
A/D reference voltage (high) input.

I/O
I
O
I

ST
ST
—
TTL

Digital I/O.
Timer0 external clock input.
Comparator 1 output.
External USB transceiver RCV input.

I/O
I
I
I
O

TTL
Analog
TTL
Analog—Digital I/O.
Analog input 4.
SPI slave select input.
High/Low-Voltage Detect input.
Comparator 2 output.

——

See the OSC2/CLKO/RA6 pin.

Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
I= Input
O = Output
P= Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 13

PIC18F2455/2550/4455/4550
TABLE 1-2:

PIC18F2455/2550 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin
NumberPin Name
PDIP,
SOIC

Pin
Type

BufferType

Description

PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/AN12/INT0/FLT0/
SDI/SDA
RB0
AN12
INT0
FLT0
SDI
SDA

21

RB1/AN10/INT1/SCK/
SCL
RB1
AN10
INT1
SCK
SCL

22

RB2/AN8/INT2/VMO
RB2
AN8
INT2
VMO

23

RB3/AN9/CCP2/VPO
RB3
AN9
CCP2(1)VPO

24

RB4/AN11/KBI0
RB4
AN11
KBI0

25

RB5/KBI1/PGM
RB5
KBI1
PGM

26

RB6/KBI2/PGC
RB6
KBI2
PGC

27

RB7/KBI3/PGD
RB7
KBI3
PGD

28

I/O
I
I
I
I
I/O

TTL
AnalogST
ST
ST
ST

Digital I/O.
Analog input 12.
External interrupt 0.
PWM Fault input (CCP1 module).
SPI data in.
I2C™ data I/O.

I/O
I
I
I/O
I/O

TTL
AnalogST
ST
ST

Digital I/O.
Analog input 10.
External interrupt 1.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C mode.

I/O
I
I
O

TTL
AnalogST—

Digital I/O.
Analog input 8.
External interrupt 2.
External USB transceiver VMO output.

I/O
I
I/O
O

TTL
AnalogST—

Digital I/O.
Analog input 9.
Capture 2 input/Compare 2 output/PWM 2 output.
External USB transceiver VPO output.

I/O
I
I

TTL
AnalogTTL

Digital I/O.
Analog input 11.
Interrupt-on-change pin.

I/O
I
I/O

TTL
TTL
ST

Digital I/O.
Interrupt-on-change pin.
Low-Voltage ICSP™ Programming enable pin.

I/O
I
I/O

TTL
TTL
ST

Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming clock pin.

I/O
I
I/O

TTL
TTL
ST

Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.

Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
I= Input
O = Output
P= Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.

DS39632D-page 14

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
TABLE 1-2:

PIC18F2455/2550 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin
NumberPin Name
PDIP,
SOIC

Pin
Type

BufferType

Description

PORTC is a bidirectional I/O port.
RC0/T1OSO/T13CKI
RC0
T1OSO
T13CKI11

RC1/T1OSI/CCP2/UOE
RC1
T1OSI
CCP2(2)
UOE

12

RC2/CCP1
RC2
CCP1

13

RC4/D-/VM
RC4
DVM

15

RC5/D+/VP
RC5
D+
VP

16

RC6/TX/CK
RC6
TX
CK

17

RC7/RX/DT/SDO
RC7
RX
DT
SDO

18

I/O
O
I

ST
—
ST

Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.

I/O
I
I/O
—

ST
CMOS
ST
—

Digital I/O.
Timer1 oscillator input.
Capture 2 input/Compare 2 output/PWM 2 output.
External USB transceiver OE output.

I/O
I/O

ST
ST

Digital I/O.
Capture 1 input/Compare 1 output/PWM 1 output.

I
I/O
I

TTL
—
TTL

Digital input.
USB differential minus line (input/output).
External USB transceiver VM input.

I
I/O
O

TTL
—
TTL

Digital input.
USB differential plus line (input/output).
External USB transceiver VP input.

I/O
O
I/O

ST
—
ST

Digital I/O.
EUSART asynchronous transmit.
EUSART synchronous clock (see RX/DT).

I/O
I
I/O
O

ST
ST
ST
—

Digital I/O.
EUSART asynchronous receive.
EUSART synchronous data (see TX/CK).
SPI data out.

RE3

—

—

—

See MCLR/VPP/RE3 pin.

VUSB

14

O

—

Internal USB 3.3V voltage regulator.

VSS

8, 19

P

—

Ground reference for logic and I/O pins.

VDD

20

P

—

Positive supply for logic and I/O pins.

Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
I= Input
O = Output
P= Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 15

PIC18F2455/2550/4455/4550
TABLE 1-3:

PIC18F4455/4550 PINOUT I/O DESCRIPTIONSPin Number

Pin Name
PDIP
MCLR/VPP/RE3
MCLR

1Pin Buffer
Type
Type
QFN TQFP
18

18
I

ST

P
I

ST

I
I

AnalogAnalog

O

—

CLKO

O

—

RA6

I/O

TTL

VPP
RE3
OSC1/CLKI
OSC1
CLKI

13

OSC2/CLKO/RA6
OSC2

14

32

33

30

31

Description
Master Clear (input) or programming voltage (input).
Master Clear (Reset) input. This pin is an active-low
Reset to the device.
Programming voltage input.
Digital input.
Oscillator crystal or external clock input.
Oscillator crystal input or external clock source input.
External clock source input. Always associated withpin function OSC1. (See OSC2/CLKO pin.)
Oscillator crystal or clock output.
Oscillator crystal output. Connects to crystal orresonator in Crystal Oscillator mode.
In RC mode, OSC2 pin outputs CLKO which has 1/4
the frequency of OSC1 and denotes the instruction
cycle rate.
General purpose I/O pin.

Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I= InputO= OutputP= Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No
Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.

DS39632D-page 16

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
TABLE 1-3:

PIC18F4455/4550 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number

Pin Name
PDIP

Pin Buffer
QFN TQFP Type Type

Description
PORTA is a bidirectional I/O port.

RA0/AN0
RA0
AN02

RA1/AN1
RA1
AN1

3

RA2/AN2/VREF-/
CVREF
RA2
AN2
VREFCVREF

4

RA3/AN3/VREF+
RA3
AN3
VREF+

5

RA4/T0CKI/C1OUT/
RCV
RA4
T0CKI
C1OUT
RCV

6

RA5/AN4/SS/
HLVDIN/C2OUT
RA5
AN4
SS
HLVDIN
C2OUT

7

RA6

—

19

20

21

22

23

24

—

19
I/O
I

TTL
AnalogDigital I/O.
Analog input 0.

I/O
I

TTL
AnalogDigital I/O.
Analog input 1.

I/O
I
I
O

TTL
AnalogAnalogAnalogDigital I/O.
Analog input 2.
A/D reference voltage (low) input.
Analog comparator reference output.

I/O
I
I

TTL
AnalogAnalogDigital I/O.
Analog input 3.
A/D reference voltage (high) input.

I/O
I
O
I

ST
ST
—
TTL

Digital I/O.
Timer0 external clock input.
Comparator 1 output.
External USB transceiver RCV input.

I/O
I
I
I
O

TTL
Analog
TTL
Analog—Digital I/O.
Analog input 4.
SPI slave select input.
High/Low-Voltage Detect input.
Comparator 2 output.

——

See the OSC2/CLKO/RA6 pin.

20

21

22

23

24

—

Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I= InputO= OutputP= Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No
Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 17

PIC18F2455/2550/4455/4550
TABLE 1-3:

PIC18F4455/4550 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number

Pin Name
PDIP

Pin Buffer
Type
Type
QFN TQFP

Description
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.

RB0/AN12/INT0/
FLT0/SDI/SDA
RB0
AN12
INT0
FLT0
SDI
SDA

33

RB1/AN10/INT1/SCK/
SCL
RB1
AN10
INT1
SCK
SCL

34

RB2/AN8/INT2/VMO
RB2
AN8
INT2
VMO

35

RB3/AN9/CCP2/VPO
RB3
AN9
CCP2(1)VPO

36

RB4/AN11/KBI0/CSSPP
RB4
AN11
KBI0
CSSPP

37

RB5/KBI1/PGM
RB5
KBI1
PGM

38

RB6/KBI2/PGC
RB6
KBI2
PGC

39

RB7/KBI3/PGD
RB7
KBI3
PGD

40

9

10

11

12

14

15

16

17

8
I/O
I
I
I
I
I/O

TTL
AnalogST
ST
ST
ST

Digital I/O.
Analog input 12.
External interrupt 0.
Enhanced PWM Fault input (ECCP1 module).
SPI data in.
I2C™ data I/O.

I/O
I
I
I/O
I/O

TTL
AnalogST
ST
ST

Digital I/O.
Analog input 10.
External interrupt 1.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C mode.

I/O
I
I
O

TTL
AnalogST—

Digital I/O.
Analog input 8.
External interrupt 2.
External USB transceiver VMO output.

I/O
I
I/O
O

TTL
AnalogST—

Digital I/O.
Analog input 9.
Capture 2 input/Compare 2 output/PWM 2 output.
External USB transceiver VPO output.

I/O
I
I
O

TTL
AnalogTTL—

Digital I/O.
Analog input 11.
Interrupt-on-change pin.
SPP chip select control output.

I/O
I
I/O

TTL
TTL
ST

Digital I/O.
Interrupt-on-change pin.
Low-Voltage ICSP™ Programming enable pin.

I/O
I
I/O

TTL
TTL
ST

Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming clock pin.

I/O
I
I/O

TTL
TTL
ST

Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.

9

10

11

14

15

16

17

Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I= InputO= OutputP= Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No
Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.

DS39632D-page 18

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
TABLE 1-3:

PIC18F4455/4550 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
PDIP

Pin Buffer
Type
Type
QFN TQFPRC0/T1OSO/T13CKI
RC0
T1OSO
T13CKI

15

34

RC1/T1OSI/CCP2/
UOE
RC1
T1OSI
CCP2(2)
UOE

16

RC2/CCP1/P1A
RC2
CCP1
P1A

17

RC4/D-/VM
RC4
DVM

23

RC5/D+/VP
RC5
D+
VP

24

RC6/TX/CK
RC6
TX
CK

25

RC7/RX/DT/SDO
RC7
RX
DT
SDO

26

Pin Name

Description
PORTC is a bidirectional I/O port.

35

36

42

43

44

1

32
I/O
O
I

ST
—
ST

I/O
I
I/O
O

ST
CMOS
ST
—

Digital I/O.
Timer1 oscillator input.
Capture 2 input/Compare 2 output/PWM 2 output.
External USB transceiver OE output.

I/O
I/O
O

ST
ST
TTL

Digital I/O.
Capture 1 input/Compare 1 output/PWM 1 output.
Enhanced CCP1 PWM output, channel A.

I
I/O
I

TTL
—
TTL

Digital input.
USB differential minus line (input/output).
External USB transceiver VM input.

I
I/O
I

TTL
—
TTL

Digital input.
USB differential plus line (input/output).
External USB transceiver VP input.

I/O
O
I/O

ST
—
ST

Digital I/O.
EUSART asynchronous transmit.
EUSART synchronous clock (see RX/DT).

I/O
I
I/O
O

ST
ST
ST
—

Digital I/O.
EUSART asynchronous receive.
EUSART synchronous data (see TX/CK).
SPI data out.

Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.

35

36

42

43

44

1

Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I= InputO= OutputP= Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No
Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 19

PIC18F2455/2550/4455/4550
TABLE 1-3:

PIC18F4455/4550 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number

Pin Name
PDIP

Pin Buffer
Type
Type
QFN TQFP

Description
PORTD is a bidirectional I/O port or a Streaming
Parallel Port (SPP). These pins have TTL input buffers
when the SPP module is enabled.

RD0/SPP0
RD0
SPP0

19

RD1/SPP1
RD1
SPP1

20

RD2/SPP2
RD2
SPP2

21

RD3/SPP3
RD3
SPP3

22

RD4/SPP4
RD4
SPP4

27

RD5/SPP5/P1B
RD5
SPP5
P1B

28

RD6/SPP6/P1C
RD6
SPP6
P1C

29

RD7/SPP7/P1D
RD7
SPP7
P1D

30

38

39

40

41

2

3

4

5

38
I/O
I/O

ST
TTL

Digital I/O.
Streaming Parallel Port data.

I/O
I/O

ST
TTL

Digital I/O.
Streaming Parallel Port data.

I/O
I/O

ST
TTL

Digital I/O.
Streaming Parallel Port data.

I/O
I/O

ST
TTL

Digital I/O.
Streaming Parallel Port data.

I/O
I/O

ST
TTL

Digital I/O.
Streaming Parallel Port data.

I/O
I/O
O

ST
TTL
—

Digital I/O.
Streaming Parallel Port data.
Enhanced CCP1 PWM output, channel B.

I/O
I/O
O

ST
TTL
—

Digital I/O.
Streaming Parallel Port data.
Enhanced CCP1 PWM output, channel C.

I/O
I/O
O

ST
TTL
—

Digital I/O.
Streaming Parallel Port data.
Enhanced CCP1 PWM output, channel D.

39

40

41

2

3

4

5

Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I= InputO= OutputP= Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No
Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.

DS39632D-page 20

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
TABLE 1-3:

PIC18F4455/4550 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number

Pin Name
PDIP

Pin Buffer
Type
Type
QFN TQFP

Description
PORTE is a bidirectional I/O port.

RE0/AN5/CK1SPPRE0AN5CK1SPP

8

RE1/AN6/CK2SPPRE1AN6CK2SPP

9

RE2/AN7/OESPP
RE2
AN7
OESPP

10

25

26

27

25
I/O
I
O

ST
Analog—Digital I/O.
Analog input 5.
SPP clock 1 output.

I/O
I
O

ST
Analog—Digital I/O.
Analog input 6.
SPP clock 2 output.

I/O
I
O

ST
Analog—Digital I/O.
Analog input 7.
SPP output enable output.

26

27

—

—

—

—

See MCLR/VPP/RE3 pin.

VSS

12, 31 6, 30,
31

6, 29

P

—

Ground reference for logic and I/O pins.

VDD

11, 32 7, 8, 7, 28
28, 29P—

Positive supply for logic and I/O pins.

O—

Internal USB 3.3V voltage regulator output.

I/O
I/O

ST
ST

No Connect or dedicated ICD/ICSP™ port clock.
In-Circuit Debugger clock.
ICSP programming clock.

I/O
I/O

ST
ST

No Connect or dedicated ICD/ICSP port clock.
In-Circuit Debugger data.
ICSP programming data.

I
P

—
—

No Connect or dedicated ICD/ICSP port Reset.
Master Clear (Reset) input.
Programming voltage input.

RE3

—

VUSB

18

37

37

NC/ICCK/ICPGC(3)
ICCK
ICPGC

—

—

12

NC/ICDT/ICPGD(3)
ICDT
ICPGD

—

NC/ICRST/ICVPP(3)
ICRST
ICVPP

—

NC/ICPORTS(3)ICPORTS

—

—

34

P

—

No Connect or 28-pin device emulation.
Enable 28-pin device emulation when connected
to VSS.

NC

—

13

—

—

—

No Connect.

—

—

13

33

Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I= InputO= OutputP= Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No
Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 21

PIC18F2455/2550/4455/4550
NOTES:DS39632D-page 22

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
2.0

OSCILLATORCONFIGURATIONS

2.1

Overview

1.
2.
3.
4.

Devices in the PIC18F2455/2550/4455/4550 family
incorporate a different oscillator and microcontroller
clock system than previous PIC18F devices. The addition of the USB module, with its unique requirements
for a stable clock source, make it necessary to provide
a separate clock source that is compliant with both
USB low-speed and full-speed specifications.
To accommodate these requirements, PIC18F2455/
2550/4455/4550 devices include a new clock branch toprovide a 48 MHz clock for full-speed USB operation.
Since it is driven from the primary clock source, anadditional system of prescalers and postscalers has
been added to accommodate a wide range of oscillator
frequencies. An overview of the oscillator structure isshown in Figure 2-1.
Other oscillator features used in PIC18 enhanced
microcontrollers, such as the internal oscillator blockand clock switching, remain the same. They are
discussed later in this chapter.

2.1.1

OSCILLATOR CONTROLThe operation of the oscillator in PIC18F2455/2550/
4455/4550 devices is controlled through two Configuration registers and two control registers. Configuration
registers, CONFIG1L and CONFIG1H, select theoscillator mode and USB prescaler/postscaler options.
As Configuration bits, these are set when the device isprogrammed and left in that configuration until thedevice is reprogrammed.
The OSCCON register (Register 2-2) selects the Active
Clock mode; it is primarily used in controlling clock
switching in power-managed modes. Its use isdiscussed in Section 2.4.1 “Oscillator Control
Register”.
The OSCTUNE register (Register 2-1) is used to trim
the INTRC frequency source, as well as select the
low-frequency clock source that drives several special
features. Its use is described in Section 2.2.5.2“OSCTUNE Register”.

2.2

Oscillator Types

PIC18F2455/2550/4455/4550 devices can be operated
in twelve distinct oscillator modes. In contrast with previous PIC18 enhanced microcontrollers, four of thesemodes involve the use of two oscillator types at once.
Users can program the FOSC3:FOSC0 Configuration
bits to select one of these modes:© 2007 Microchip Technology Inc.

XT
XTPLL
HS
HSPLL

Crystal/Resonator
Crystal/Resonator with PLL enabled
High-Speed Crystal/Resonator
High-Speed Crystal/Resonatorwith PLL enabled
5. EC
External Clock with FOSC/4 output
6. ECIO
External Clock with I/O on RA6
7. ECPLL External Clock with PLL enabledand FOSC/4 output on RA6
8. ECPIO External Clock with PLL enabled,
I/O on RA6
9. INTHS Internal Oscillator used as
microcontroller clock source, HS
Oscillator used as USB clock source
10. INTXT Internal Oscillator used as
microcontroller clock source, XT
Oscillator used as USB clock source
11. INTIO Internal Oscillator used as
microcontroller clock source, EC
Oscillator used as USB clock source,
digital I/O on RA6
12. INTCKO Internal Oscillator used as
microcontroller clock source, EC
Oscillator used as USB clock source,
FOSC/4 output on RA6

2.2.1

OSCILLATOR MODES AND
USB OPERATION

Because of the unique requirements of the USB module,
a different approach to clock operation is necessary. In
previous PIC® devices, all core and peripheral clocks
were driven by a single oscillator source; the usual
sources were primary, secondary or the internal oscillator. With PIC18F2455/2550/4455/4550 devices, the primary oscillator becomes part of the USB module andcannot be associated to any other clock source. Thus,
the USB module must be clocked from the primary clock
source; however, the microcontroller core and otherperipherals can be separately clocked from the secondary or internal oscillators as before.
Because of the timing requirements imposed by USB,an internal clock of either 6 MHz or 48 MHz is required
while the USB module is enabled. Fortunately, themicrocontroller and other peripherals are not required
to run at this clock speed when using the primaryoscillator. There are numerous options to achieve theUSB module clock requirement and still provide flexibility for clocking the rest of the device from the primaryoscillator source. These are detailed in Section 2.3“Oscillator Settings for USB”.

Preliminary

DS39632D-page 23

PIC18F2455/2550/4455/4550
FIGURE 2-1:

PIC18F2455/2550/4455/4550 CLOCK DIAGRAM

PIC18F2455/2550/4455/4550

Primary Oscillator
OSC2
Sleep
OSC1

÷ 12

111

÷ 10

110

÷6

101

÷5

100

÷4

011

÷3

010

÷2

001

÷1

000

USB Clock Source

USBDIV(4 MHz Input Only)
MUX

PLL Prescaler

PLLDIV

96 MHz
PLL

0
1

÷2

FSEN
1

HSPLL, ECPLL,
XTPLL, ECPIO

USB
Peripheral

PLL Postscaler

CPUDIVXT, HS, EC, ECIO

Oscillator Postscaler

CPUDIV
÷4

11

÷3

10

÷2

01

÷1

00

÷6

11

÷4

10

÷3

01

÷2

00

÷4

0

CPU
1
0

Primary
Clock
FOSC3:FOSC0

T1OSIPeripherals

MUX

Secondary Oscillator
T1OSO

IDLEN

T1OSC
T1OSCEN
EnableOscillator
OSCCON<6:4>

INTRC
Source

4 MHz

8 MHz
(INTOSC)

31 kHz (INTRC)

INTOSC Postscaler

Internal
Oscillator
Block
8 MHz
Source2 MHz
1 MHz
500 kHz250 kHz

111
110

Clock
Control

101
100
011

MUX

8 MHz

OSCCON<6:4>

Internal Oscillator

FOSC3:FOSC0OSCCON<1:0>010

125 kHz001
1 31 kHz000
0Clock Source Option
for other Modules

OSCTUNE<7>
WDT, PWRT, FSCM
and Two-Speed Start-up

DS39632D-page 24

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
2.2.2

CRYSTAL OSCILLATOR/CERAMICRESONATORSIn HS, HSPLL, XT and XTPLL Oscillator modes, acrystal or ceramic resonator is connected to the OSC1
and OSC2 pins to establish oscillation. Figure 2-2
shows the pin connections.

TABLE 2-2:

Osc Type

Use of a series cut crystal may give a frequency out of the crystal manufacturer’s
specifications.

FIGURE 2-2:

C1(1)CRYSTAL/CERAMICRESONATOR OPERATION(XT, HS OR HSPLLCONFIGURATION)
OSC1

XTAL

RF(3)

OSC1

4.0 MHz

33 pF

33 pF

8.0 MHz16.0 MHz

27 pF
22 pF

27 pF
22 pF

22 pF

22 pF

15 pF

15 pF

20 MHzNote 1: Higher capacitance increases the stabilityof oscillator but also increases thestart-up time.
2: When operating below 3V VDD, or whenusing certain ceramic resonators at any
voltage, it may be necessary to use theHS mode or switch to a crystal oscillator.
3: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate
valuesofexternal
components.

Capacitor values are for design guidance only.

4: Rs may be required to avoid overdriving
crystals with low drive level specification.

These capacitors were tested with the resonators
listed below for basic start-up and operation. These
values are not optimized.
Different capacitor values may be required to produce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected
VDD and temperature range for the application.
See the notes following Table 2-2 for additional
information.

8.0 MHz

8 MHz
20 MHz

8 MHz

OSC2

XT

4.0 MHz

27 pF
27 pF

4 MHz

HS

Resonators Used:

27 pF
27 pF

See the notes following this table for additional
information.

CAPACITOR SELECTION FOR
CERAMIC RESONATORS

Freq

4 MHz
4 MHz

Different capacitor values may be required to produce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected
VDD and temperature range for the application.

Typical Capacitor Values Used:
Mode

XT
HS

Crystals Used:

Note 1: See Table 2-1 and Table 2-2 for initial values of
C1 and C2.
2: A series resistor (RS) may be required for AT
strip cut crystals.
3: RF varies with the oscillator mode chosen.

TABLE 2-1:

C2

These capacitors were tested with the crystals listed
below for basic start-up and operation. These values
are not optimized.

PIC18FXXXX

OSC2

Typical Capacitor Values
Tested:Capacitor values are for design guidance only.

Sleep

RS(2)
C2(1)

To
Internal
Logic

CrystalFreq

C1

The oscillator design requires the use of a parallel cut
crystal.
Note:

CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR

5: Always verify oscillator performance overthe VDD and temperature range that is
expected for the application.
An internal postscaler allows users to select a clock
frequency other than that of the crystal or resonator.
Frequency division is determined by the CPUDIV
Configuration bits. Users may select a clock frequencyof the oscillator frequency, or 1/2, 1/3 or 1/4 of thefrequency.
An external clock may also be used when the microcontroller is in HS Oscillator mode. In this case, theOSC2/CLKO pin is left open (Figure 2-3).

16.0 MHz© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 25

PIC18F2455/2550/4455/4550
FIGURE 2-3:

EXTERNAL CLOCK INPUTOPERATION (HS OSCCONFIGURATION)
OSC1Clock from
Ext. System

PIC18FXXXX
Open

2.2.3

OSC2

(HS Mode)

EXTERNAL CLOCK INPUTThe EC, ECIO, ECPLL and ECPIO Oscillator modes
require an external clock source to be connected to the
OSC1 pin. There is no oscillator start-up time required
after a Power-on Reset or after an exit from Sleepmode.
In the EC and ECPLL Oscillator modes, the oscillator
frequency divided by 4 is available on the OSC2 pin.
This signal may be used for test purposes or tosynchronize other logic. Figure 2-4 shows the pin
connections for the EC Oscillator mode.

FIGURE 2-4:

EXTERNAL CLOCKINPUT OPERATION(EC AND ECPLLCONFIGURATION)

Clock from
Ext. System

OSC1/CLKI

2.2.4

PLL FREQUENCY MULTIPLIER

PIC18F2455/2550/4255/4550 devices include a Phase
Locked Loop (PLL) circuit. This is provided specificallyfor USB applications with lower speed oscillators andcan also be used as a microcontroller clock source.
The PLL is enabled in HSPLL, XTPLL, ECPLL and
ECPIO Oscillator modes. It is designed to produce a
fixed 96 MHz reference clock from a fixed 4 MHz input.
The output can then be divided and used for both the
USB and the microcontroller core clock. Because the
PLL has a fixed frequency input and output, there areeight prescaling options to match the oscillator input
frequency to the PLL.
There is also a separate postscaler option for deriving
the microcontroller clock from the PLL. This allows theUSB peripheral and microcontroller to use the same
oscillator input and still operate at different clock
speeds. In contrast to the postscaler for XT, HS and EC
modes, the available options are 1/2, 1/3, 1/4 and 1/6of the PLL output.
The HSPLL, ECPLL and ECPIO modes make use of
the HS mode oscillator for frequencies up to 48 MHz.
The prescaler divides the oscillator input by up to 12 toproduce the 4 MHz drive for the PLL. The XTPLL mode
can only use an input frequency of 4 MHz which drives
the PLL directly.

FIGURE 2-6:

PIC18FXXXXFOSC/4

OSC2/CLKO

HS/EC/ECIO/XT Oscillator Enable
PLL Enable(from CONFIG1H Register)

The ECIO and ECPIO Oscillator modes function like theEC and ECPLL modes, except that the OSC2 pin
becomes an additional general purpose I/O pin. The I/O
pin becomes bit 6 of PORTA (RA6). Figure 2-5 shows
the pin connections for the ECIO Oscillator mode.

FIGURE 2-5:

PLL BLOCK DIAGRAM(HS MODE)

OSC2
Oscillator
and
OSC1
Prescaler

FIN
FOUT

EXTERNAL CLOCKINPUT OPERATION(ECIO AND ECPIOCONFIGURATION)

Loop
Filter

VCO
MUX

÷24
OSC1/CLKI

Clock from
Ext. System

Phase
Comparator

SYSCLK

PIC18FXXXX
RA6

I/O (OSC2)

The internal postscaler for reducing clock frequency in
XT and HS modes is also available in EC and ECIO
modes.

DS39632D-page 26

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
2.2.5

INTERNAL OSCILLATOR BLOCK

2.2.5.2

The PIC18F2455/2550/4455/4550 devices include aninternal oscillator block which generates two different
clock signals; either can be used as the microcontroller’s
clock source. If the USB peripheral is not used, theinternal oscillator may eliminate the need for external
oscillator circuits on the OSC1 and/or OSC2 pins.

OSCTUNE Register

The internal oscillator’s output has been calibrated at
the factory but can be adjusted in the user’s application. This is done by writing to the OSCTUNE register(Register 2-1). The tuning sensitivity is constantthroughout the tuning range.

The main output (INTOSC) is an 8 MHz clock source
which can be used to directly drive the device clock. It
also drives the INTOSC postscaler which can provide a
range of clock frequencies from 31 kHz to 4 MHz. The
INTOSC output is enabled when a clock frequency
from 125 kHz to 8 MHz is selected.

When the OSCTUNE register is modified, the INTOSC
and INTRC frequencies will begin shifting to the new
frequency. The INTRC clock will reach the new
frequency within 8 clock cycles (approximately,
8 * 32 μs = 256 μs). The INTOSC clock will stabilize
within 1 ms. Code execution continues during this shift.
There is no indication that the shift has occurred.

The other clock source is the internal RC oscillator(INTRC) which provides a nominal 31 kHz output.
INTRC is enabled if it is selected as the device clock
source; it is also enabled automatically when any of thefollowing are enabled:

The OSCTUNE register also contains the INTSRC bit.
The INTSRC bit allows users to select which internal
oscillator provides the clock source when the 31 kHz
frequency option is selected. This is covered in greater
detail in Section 2.4.1 “Oscillator Control Register”.

• Power-up Timer• Fail-Safe Clock Monitor• Watchdog Timer• Two-Speed Start-up

2.2.5.3

These features are discussed in greater detail in
Section 25.0 “Special Features of the CPU”.
The clock source frequency (INTOSC direct, INTRC
direct or INTOSC postscaler) is selected by configuring
the IRCF bits of the OSCCON register (page 32).

2.2.5.1

Internal Oscillator Modes

Internal Oscillator Output Frequency
and Drift

The internal oscillator block is calibrated at the factory
to produce an INTOSC output frequency of 8.0 MHz.
However, this frequency may drift as VDD or temperature changes, which can affect the controller operation
in a variety of ways.
The low-frequency INTRC oscillator operates independently of the INTOSC source. Any changes in INTOSC
across voltage and temperature are not necessarilyreflected by changes in INTRC and vice versa.

When the internal oscillator is used as the microcontroller clock source, one of the other oscillator
modes (External Clock or External Crystal/Resonator)
must be used as the USB clock source. The choice of
the USB clock source is determined by the particularinternal oscillator mode.
There are four distinct modes available:
1.
2.
3.

4.

INTHS mode: The USB clock is provided by theoscillator in HS mode.
INTXT mode: The USB clock is provided by theoscillator in XT mode.
INTCKO mode: The USB clock is provided by an
external clock input on OSC1/CLKI; the OSC2/
CLKO pin outputs FOSC/4.
INTIO mode: The USB clock is provided by an
external clock input on OSC1/CLKI; the OSC2/
CLKO pin functions as a digital I/O (RA6).

Of these four modes, only INTIO mode frees up an
additional pin (OSC2/CLKO/RA6) for port I/O use.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 27

PIC18F2455/2550/4455/4550
REGISTER 2-1:

OSCTUNE: OSCILLATOR TUNING REGISTER

R/W-0

U-0

U-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

INTSRC

—

—

TUN4

TUN3

TUN2

TUN1

TUN0

bit 7

bit 0

Legend:R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’-n = Value at POR‘1’ = Bit is set‘0’ = Bit is clearedx = Bit is unknown

bit 7

INTSRC: Internal Oscillator Low-Frequency Source Select bit
1 = 31.25 kHz device clock derived from 8 MHz INTOSC source (divide-by-256 enabled)
0 = 31 kHz device clock derived directly from INTRC internal oscillator

bit 6-5

Unimplemented: Read as ‘0’

bit 4-0

TUN4:TUN0: Frequency Tuning bits
01111 = Maximum frequency
•
•
•
•
00001
00000 = Center frequency. Oscillator module is running at the calibrated frequency.
11111
•
•
•
•
10000 = Minimum frequency

2.2.5.4

Compensating for INTOSC Drift

It is possible to adjust the INTOSC frequency bymodifying the value in the OSCTUNE register. This has
no effect on the INTRC clock source frequency.
Tuning the INTOSC source requires knowing when to
make the adjustment, in which direction it should bemade and in some cases, how large a change isneeded. When using the EUSART, for example, anadjustment may be required when it begins to generateframing errors or receives data with errors while in
Asynchronous mode. Framing errors indicate that thedevice clock frequency is too high; to adjust for this,decrement the value in OSCTUNE to reduce the clock
frequency. On the other hand, errors in data may suggest that the clock speed is too low; to compensate,increment OSCTUNE to increase the clock frequency.
It is also possible to verify device clock speed against
a reference clock. Two timers may be used: one timer
is clocked by the peripheral clock, while the other isclocked by a fixed reference source, such as theTimer1 oscillator. Both timers are cleared but the timer
clocked by the reference generates interrupts. WhenDS39632D-page 28

an interrupt occurs, the internally clocked timer is readand both timers are cleared. If the internally clocked
timer value is greater than expected, then the internal
oscillator block is running too fast. To adjust for this,decrement the OSCTUNE register.
Finally, a CCP module can use free-running Timer1 (orTimer3), clocked by the internal oscillator block and an
external event with a known period (i.e., AC power
frequency). The time of the first event is captured in the
CCPRxH:CCPRxL registers and is recorded for use
later. When the second event causes a capture, thetime of the first event is subtracted from the time of thesecond event. Since the period of the external event is
known, the time difference between events can becalculated.
If the measured time is much greater than the calculated time, the internal oscillator block is running too
fast; to compensate, decrement the OSCTUNE register.
If the measured time is much less than the calculated
time, the internal oscillator block is running too slow; tocompensate, increment the OSCTUNE register.

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
2.3

Oscillator Settings for USB

active and the controller clock source is one of the
primary oscillator modes (XT, HS or EC, with or without
the PLL).

When the PIC18F4550 is used for USB connectivity, it
must have either a 6 MHz or 48 MHz clock for USB
operation, depending on whether Low-Speed or
Full-Speed mode is being used. This may require someforethought in selecting an oscillator frequency andprogramming the device.

This restriction does not apply if the microcontroller
clock source is the secondary oscillator or internal
oscillator block.

2.3.2

The full range of possible oscillator configurations
compatible with USB operation is shown in Table 2-3.

2.3.1

The USB module, in either mode, can run asynchronously with respect to the microcontroller core andother peripherals. This means that applications can use
the primary oscillator for the USB clock while the microcontroller runs from a separate clock source at a lower
speed. If it is necessary to run the entire applicationfrom only one clock source, full-speed operation
provides a greater selection of microcontroller clock
frequencies.

LOW-SPEED OPERATIONThe USB clock for Low-Speed mode is derived fromthe primary oscillator chain and not directly from the
PLL. It is divided by 4 to produce the actual 6 MHz
clock. Because of this, the microcontroller can only use
a clock frequency of 24 MHz when the USB module is

TABLE 2-3:

RUNNING DIFFERENT USB AND
MICROCONTROLLER CLOCKSOSCILLATOR CONFIGURATION OPTIONS FOR USB OPERATION

Input Oscillator
Frequency

PLL Division(PLLDIV2:PLLDIV0)

Clock Mode
(FOSC3:FOSC0)MCU Clock Division(CPUDIV1:CPUDIV0)

Microcontroller
Clock Frequency

48 MHzN/A(1)EC, ECIO

None (00)48 MHz÷2 (01)

24 MHz÷3 (10)16 MHz÷4 (11)

12 MHzNone (00)48 MHz÷2 (01)

24 MHz÷3 (10)16 MHz÷4 (11)

12 MHz÷2 (00)48 MHz÷3 (01)

32 MHz÷4 (10)24 MHz÷6 (11)

16 MHzNone (00)40 MHz48 MHz÷12 (111)

EC, ECIOECPLL, ECPIO

40 MHz÷10 (110)

EC, ECIOECPLL, ECPIO

24 MHz÷6 (101)

HS, EC, ECIOHSPLL, ECPLL, ECPIO

Legend:Note 1:÷2 (01)

20 MHz÷3 (10)13.33 MHz÷4 (11)

10 MHz÷2 (00)48 MHz÷3 (01)

32 MHz÷4 (10)24 MHz÷6 (11)

16 MHzNone (00)24 MHz÷2 (01)

12 MHz÷3 (10)8 MHz

÷4 (11)6 MHz

÷2 (00)48 MHz÷3 (01)

32 MHz÷4 (10)24 MHz÷6 (11)

16 MHzAll clock frequencies, except 24 MHz, are exclusively associated with full-speed USB operation (USB clock of 48 MHz).
Bold is used to highlight clock selections that are compatible with low-speed USB operation (system clock of 24 MHz,USB clock of 6 MHz).
Only valid when the USBDIV Configuration bit is cleared.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 29

PIC18F2455/2550/4455/4550
TABLE 2-3:

OSCILLATOR CONFIGURATION OPTIONS FOR USB OPERATION (CONTINUED)

Input Oscillator
Frequency

PLL Division(PLLDIV2:PLLDIV0)

Clock Mode
(FOSC3:FOSC0)MCU Clock Division(CPUDIV1:CPUDIV0)

Microcontroller
Clock Frequency

20 MHz÷5 (100)

HS, EC, ECIO

None (00)

20 MHzHSPLL, ECPLL, ECPIO

16 MHz÷4 (011)HS, EC, ECIOHSPLL, ECPLL, ECPIO

12 MHz÷3 (010)

HS, EC, ECIOHSPLL, ECPLL, ECPIO

8 MHz

÷2 (001)

HS, EC, ECIOHSPLL, ECPLL, ECPIO

4 MHz

÷1 (000)

XT, HS, EC, ECIOHSPLL, ECPLL, XTPLL,ECPIOLegend:Note 1:÷2 (01)

10 MHz÷3 (10)6.67 MHz÷4 (11)5 MHz

÷2 (00)48 MHz÷3 (01)

32 MHz÷4 (10)24 MHz÷6 (11)

16 MHzNone (00)

16 MHz÷2 (01)8 MHz

÷3 (10)5.33 MHz÷4 (11)4 MHz

÷2 (00)48 MHz÷3 (01)

32 MHz÷4 (10)24 MHz÷6 (11)

16 MHzNone (00)

12 MHz÷2 (01)6 MHz

÷3 (10)4 MHz

÷4 (11)3 MHz

÷2 (00)48 MHz÷3 (01)

32 MHz÷4 (10)24 MHz÷6 (11)

16 MHzNone (00)8 MHz

÷2 (01)4 MHz

÷3 (10)2.67 MHz÷4 (11)2 MHz

÷2 (00)48 MHz÷3 (01)

32 MHz÷4 (10)24 MHz÷6 (11)

16 MHzNone (00)4 MHz

÷2 (01)2 MHz

÷3 (10)1.33 MHz÷4 (11)1 MHz

÷2 (00)48 MHz÷3 (01)

32 MHz÷4 (10)24 MHz÷6 (11)

16 MHzAll clock frequencies, except 24 MHz, are exclusively associated with full-speed USB operation (USB clock of 48 MHz).
Bold is used to highlight clock selections that are compatible with low-speed USB operation (system clock of 24 MHz,USB clock of 6 MHz).
Only valid when the USBDIV Configuration bit is cleared.

DS39632D-page 30

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
2.4

Clock Sources and Oscillator
Switching

Like previous PIC18 enhanced devices, thePIC18F2455/2550/4455/4550 family includes a featurethat allows the device clock source to be switched fromthe main oscillator to an alternate low-frequency clock
source. PIC18F2455/2550/4455/4550 devices offer
two alternate clock sources. When an alternate clock
source is enabled, the various power-managed
operating modes are available.
Essentially, there are three clock sources for thesedevices:• Primary oscillators• Secondary oscillators• Internal oscillator block
The primary oscillators include the External Crystal
and Resonator modes, the External Clock modes andthe internal oscillator block. The particular mode isdefined by the FOSC3:FOSC0 Configuration bits. The
details of these modes are covered earlier in thischapter.
The secondary oscillators are those external sources
not connected to the OSC1 or OSC2 pins. Thesesources may continue to operate even after thecontroller is placed in a power-managed mode.
PIC18F2455/2550/4455/4550 devices offer the Timer1
oscillator as a secondary oscillator. This oscillator, in all
power-managed modes, is often the time base forfunctions such as a Real-Time Clock. Most often, a32.768 kHz watch crystal is connected between the
RC0/T1OSO/T13CKI and RC1/T1OSI/UOE pins. Like
the XT and HS oscillator mode circuits, loading
capacitors are also connected from each pin to ground.
The Timer1 oscillator is discussed in greater detail in
Section 12.3 “Timer1 Oscillator”.
In addition to being a primary clock source, the internal
oscillator block is available as a power-managed
mode clock source. The INTRC source is also used as
the clock source for several special features, such as
the WDT and Fail-Safe Clock Monitor.

2.4.1

OSCILLATOR CONTROL REGISTERThe OSCCON register (Register 2-2) controls several
aspects of the device clock’s operation, both in fullpower operation and in power-managed modes.
The System Clock Select bits, SCS1:SCS0, select theclock source. The available clock sources are theprimary clock (defined by the FOSC3:FOSC0 Configuration bits), the secondary clock (Timer1 oscillator) andthe internal oscillator block. The clock source changes
immediately after one or more of the bits is written to,following a brief clock transition interval. The SCS bits
are cleared on all forms of Reset.

© 2007 Microchip Technology Inc.

The Internal Oscillator Frequency Select bits,
IRCF2:IRCF0, select the frequency output of the internal
oscillator block to drive the device clock. The choices are
the INTRC source, the INTOSC source (8 MHz) or oneof the frequencies derived from the INTOSC postscaler(31 kHz to 4 MHz). If the internal oscillator block is
supplying the device clock, changing the states of thesebits will have an immediate change on the internal oscillator’s output. On device Resets, the default output
frequency of the internal oscillator block is set at 1 MHz.
When an output frequency of 31 kHz is selected(IRCF2:IRCF0 = 000), users may choose which internal oscillator acts as the source. This is done with the
INTSRC bit in the OSCTUNE register (OSCTUNE<7>).
Setting this bit selects INTOSC as a 31.25 kHz clock
source by enabling the divide-by-256 output of the
INTOSC postscaler. Clearing INTSRC selects INTRC(nominally 31 kHz) as the clock source.
This option allows users to select the tunable and more
precise INTOSC as a clock source, while maintaining
power savings with a very low clock speed. Regardlessof the setting of INTSRC, INTRC always remains theclock source for features such as the Watchdog Timerand the Fail-Safe Clock Monitor.
The OSTS, IOFS and T1RUN bits indicate which clock
source is currently providing the device clock. The OSTS
bit indicates that the Oscillator Start-up Timer has timedout and the primary clock is providing the device clock inprimary clock modes. The IOFS bit indicates when theinternal oscillator block has stabilized and is providing
the device clock in RC Clock modes. The T1RUN bit(T1CON<6>) indicates when the Timer1 oscillator isproviding the device clock in secondary clock modes. In
power-managed modes, only one of these three bits will
be set at any time. If none of these bits are set, the
INTRC is providing the clock or the internal oscillator
block has just started and is not yet stable.
The IDLEN bit determines if the device goes into Sleep
mode, or one of the Idle modes, when the SLEEP
instruction is executed.
The use of the flag and control bits in the OSCCON
register is discussed in more detail in Section 3.0“Power-Managed Modes”.
Note 1: The Timer1 oscillator must be enabled to
select the secondary clock source. The
Timer1 oscillator is enabled by setting the
T1OSCEN bit in the Timer1 Control register (T1CON<3>). If the Timer1 oscillator is
not enabled, then any attempt to select asecondary clock source will be ignored.

Preliminary

2: It is recommended that the Timer1
oscillator be operating and stable prior toswitching to it as the clock source; otherwise, a very long delay may occur while
the Timer1 oscillator starts.

DS39632D-page 31

PIC18F2455/2550/4455/4550
2.4.2

OSCILLATOR TRANSITIONSPIC18F2455/2550/4455/4550 devices contain circuitry
to prevent clock “glitches” when switching between
clock sources. A short pause in the device clock occurs
during the clock switch. The length of this pause is the

REGISTER 2-2:

sum of two cycles of the old clock source and three tofour cycles of the new clock source. This formula
assumes that the new clock source is stable.
Clock transitions are discussed in greater detail in
Section 3.1.2 “Entering Power-Managed Modes”.

OSCCON: OSCILLATOR CONTROL REGISTER

R/W-0

R/W-1

R/W-0

R/W-0

R(1)

R-0

R/W-0

R/W-0

IDLEN

IRCF2

IRCF1

IRCF0

OSTS

IOFS

SCS1

SCS0

bit 7

bit 0

Legend:R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’-n = Value at POR‘1’ = Bit is set‘0’ = Bit is clearedx = Bit is unknown

bit 7

IDLEN: Idle Enable bit
1 = Device enters Idle mode on SLEEP instruction
0 = Device enters Sleep mode on SLEEP instruction

bit 6-4

IRCF2:IRCF0: Internal Oscillator Frequency Select bits
111 = 8 MHz (INTOSC drives clock directly)
110 = 4 MHz
101 = 2 MHz
100 = 1 MHz(3)011 = 500 kHz
010 = 250 kHz
001 = 125 kHz
000 = 31 kHz (from either INTOSC/256 or INTRC directly)(2)

bit 3

OSTS: Oscillator Start-up Time-out Status bit(1)1 = Oscillator Start-up Timer time-out has expired; primary oscillator is running
0 = Oscillator Start-up Timer time-out is running; primary oscillator is not readybit 2

IOFS: INTOSC Frequency Stable bit
1 = INTOSC frequency is stable
0 = INTOSC frequency is not stable

bit 1-0

SCS1:SCS0: System Clock Select bits
1x = Internal oscillator
01 = Timer1 oscillator
00 = Primary oscillator

Note 1:
2:
3:

Depends on the state of the IESO Configuration bit.
Source selected by the INTSRC bit (OSCTUNE<7>), see text.
Default output frequency of INTOSC on Reset.

DS39632D-page 32

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
2.5

Effects of Power-Managed Modeson the Various Clock Sources

When PRI_IDLE mode is selected, the designatedprimary oscillator continues to run without interruption.
For all other power-managed modes, the oscillator
using the OSC1 pin is disabled. Unless the USB
module is enabled, the OSC1 pin (and OSC2 pin if
used by the oscillator) will stop oscillating.
In secondary clock modes (SEC_RUN and
SEC_IDLE), the Timer1 oscillator is operating andproviding the device clock. The Timer1 oscillator may
also run in all power-managed modes if required toclock Timer1 or Timer3.
In internal oscillator modes (RC_RUN and RC_IDLE),
the internal oscillator block provides the device clock
source. The 31 kHz INTRC output can be used directly
to provide the clock and may be enabled to support
various special features regardless of thepower-managed mode (see Section 25.2 “Watchdog
Timer (WDT)”, Section 25.3 “Two-Speed Start-up”
and Section 25.4 “Fail-Safe Clock Monitor” for more
information on WDT, Fail-Safe Clock Monitor and
Two-Speed Start-up). The INTOSC output at 8 MHz
may be used directly to clock the device or may be
divided down by the postscaler. The INTOSC output isdisabled if the clock is provided directly from the INTRC
output.
Regardless of the Run or Idle mode selected, the USB
clock source will continue to operate. If the device isoperating from a crystal or resonator-based oscillator,that oscillator will continue to clock the USB module.
The core and all other modules will switch to the newclock source.
If the Sleep mode is selected, all clock sources are
stopped. Since all the transistor switching currents
have been stopped, Sleep mode achieves the lowest
current consumption of the device (only leakage
currents).
Sleep mode should never be invoked while the USB
module is operating and connected. The only exception
is when the device has been issued a “Suspend”

TABLE 2-4:

command over the USB. Once the module has suspended operation and shifted to a low-power state, themicrocontroller may be safely put into Sleep mode.
Enabling any on-chip feature that will operate during
Sleep will increase the current consumed during Sleep.
The INTRC is required to support WDT operation. The
Timer1 oscillator may be operating to support a
Real-Time Clock. Other features may be operating that
do not require a device clock source (i.e., MSSP slave,
PSP, INTn pins and others). Peripherals that may add
significant current consumption are listed in
Section 28.2 “DC Characteristics: Power-Down and
Supply Current”.

2.6

Power-up Delays

Power-up delays are controlled by two timers so that noexternal Reset circuitry is required for most applications.
The delays ensure that the device is kept in Reset until
the device power supply is stable under normal circumstances and the primary clock is operating and stable.
For additional information on power-up delays, see
Section 4.5 “Device Reset Timers”.
The first timer is the Power-up Timer (PWRT), which
provides a fixed delay on power-up (parameter 33,
Table 28-12). It is enabled by clearing (= 0) the
PWRTEN Configuration bit.
The second timer is the Oscillator Start-up Timer(OST), intended to keep the chip in Reset until the
crystal oscillator is stable (XT and HS modes). The
OST does this by counting 1024 oscillator cycles
before allowing the oscillator to clock the device.
When the HSPLL Oscillator mode is selected, thedevice is kept in Reset for an additional 2 ms following
the HS mode OST delay, so the PLL can lock to theincoming clock frequency.
There is a delay of interval, TCSD (parameter 38,
Table 28-12), following POR, while the controller
becomes ready to execute instructions. This delay runs
concurrently with any other delays. This may be theonly delay that occurs when any of the EC or internal
oscillator modes are used as the primary clock source.

OSC1 AND OSC2 PIN STATES IN SLEEP MODE

Oscillator Mode

OSC1 Pin

OSC2 Pin

INTCKO

Floating, pulled by external clock

At logic low (clock/4 output)

INTIO

Floating, pulled by external clock

Configured as PORTA, bit 6

ECIO, ECPIO

Floating, pulled by external clock

Configured as PORTA, bit 6

EC

Floating, pulled by external clock

At logic low (clock/4 output)

XT and HS

Feedback inverter disabled at quiescentvoltage level

Feedback inverter disabled at quiescentvoltage level

Note:

See Table 4-2 in Section 4.0 “Reset” for time-outs due to Sleep and MCLR Reset.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 33

PIC18F2455/2550/4455/4550
NOTES:DS39632D-page 34

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
3.0

POWER-MANAGED MODES

3.1.1

PIC18F2455/2550/4455/4550 devices offer a total ofseven operating modes for more efficient power
management. These modes provide a variety ofoptions for selective power conservation in applications
where resources may be limited (i.e., battery-powered
devices).

CLOCK SOURCESThe SCS1:SCS0 bits allow the selection of one of threeclock sources for power-managed modes. They are:
• The primary clock, as defined by the
FOSC3:FOSC0 Configuration bits
• The secondary clock (the Timer1 oscillator)• The internal oscillator block (for RC modes)

There are three categories of power-managed modes:

3.1.2• Run modes• Idle modes• Sleep mode
These categories define which portions of the device
are clocked and sometimes, what speed. The Run and
Idle modes may use any of the three available clock
sources (primary, secondary or internal oscillator
block); the Sleep mode does not use a clock source.
The power-managed modes include several
power-saving features offered on previous PIC®
devices. One is the clock switching feature, offered inother PIC18 devices, allowing the controller to use theTimer1 oscillator in place of the primary oscillator. Also
included is the Sleep mode, offered by all PIC devices,where all device clocks are stopped.

3.1

Selecting Power-Managed Modes

Selecting a power-managed mode requires two
decisions: if the CPU is to be clocked or not and theselection of a clock source. The IDLEN bit(OSCCON<7>) controls CPU clocking, while theSCS1:SCS0 bits (OSCCON<1:0>) select the clock
source. The individual modes, bit settings, clock sources
and affected modules are summarized in Table 3-1.

TABLE 3-1:

Switching from one power-managed mode to anotherbegins by loading the OSCCON register. The
SCS1:SCS0 bits select the clock source and determine
which Run or Idle mode is to be used. Changing thesebits causes an immediate switch to the new clock
source, assuming that it is running. The switch may
also be subject to clock transition delays. These are
discussed in Section 3.1.3 “Clock Transitions andStatus Indicators” and subsequent sections.
Entry to the power-managed Idle or Sleep modes istriggered by the execution of a SLEEP instruction. The
actual mode that results depends on the status of the
IDLEN bit.
Depending on the current mode and the mode being
switched to, a change to a power-managed mode does
not always require setting all of these bits. Manytransitions may be done by changing the oscillator
select bits, or changing the IDLEN bit, prior to issuing a
SLEEP instruction. If the IDLEN bit is alreadyconfigured correctly, it may only be necessary to
perform a SLEEP instruction to switch to the desired
mode.

POWER-MANAGED MODESOSCCON Bits

Mode

ENTERING POWER-MANAGED
MODES

Module Clocking
Available Clock and Oscillator Source

IDLEN(1)SCS1:SCS0

Sleep

0

N/A

Off

Off

PRI_RUN

N/A

00

ClockedClockedPrimary – all oscillator modes.
This is the normal full power execution mode.

SEC_RUN

N/A

01

ClockedClockedSecondary – Timer1 oscillator

RC_RUN

N/A

1x

ClockedClockedInternal oscillator block(2)

PRI_IDLE

1

00

Off

ClockedPrimary – all oscillator modes

SEC_IDLE

1

01

Off

ClockedSecondary – Timer1 oscillator

RC_IDLE

1

1x

Off

ClockedInternal oscillator block(2)Note 1:
2:

CPU

Peripherals
None – all clocks are disabled

IDLEN reflects its value when the SLEEP instruction is executed.
Includes INTOSC and INTOSC postscaler, as well as the INTRC source.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 35

PIC18F2455/2550/4455/4550
3.1.3

CLOCK TRANSITIONS ANDSTATUS INDICATORS

3.2

The length of the transition between clock sources is
the sum of two cycles of the old clock source and three
to four cycles of the new clock source. This formula
assumes that the new clock source is stable.
Three bits indicate the current clock source and its
status. They are:• OSTS (OSCCON<3>)• IOFS (OSCCON<2>)• T1RUN (T1CON<6>)
In general, only one of these bits will be set while in agiven power-managed mode. When the OSTS bit isset, the primary clock is providing the device clock.
When the IOFS bit is set, the INTOSC output is providing a stable 8 MHz clock source to a divider that
actually drives the device clock. When the T1RUN bit isset, the Timer1 oscillator is providing the clock. If noneof these bits are set, then either the INTRC clock
source is clocking the device, or the INTOSC source is
not yet stable.
If the internal oscillator block is configured as theprimary clock source by the FOSC3:FOSC0 Configuration bits, then both the OSTS and IOFS bits may
be set when in PRI_RUN or PRI_IDLE modes. This
indicates that the primary clock (INTOSC output) is
generating a stable 8 MHz output. Entering another RC
power-managed mode at the same frequency would
clear the OSTS bit.

In the Run modes, clocks to both the core andperipherals are active. The difference between thesemodes is the clock source.

3.2.1

3.1.4

MULTIPLE SLEEP COMMANDS

The power-managed mode that is invoked with the
SLEEP instruction is determined by the setting of the
IDLEN bit at the time the instruction is executed. If
another SLEEP instruction is executed, the device willenter the power-managed mode specified by IDLEN atthat time. If IDLEN has changed, the device will enter
the new power-managed mode specified by the new
setting.

DS39632D-page 36

PRI_RUN MODE

The PRI_RUN mode is the normal, full power execution
mode of the microcontroller. This is also the default
mode upon a device Reset unless Two-Speed Start-up
is enabled (see Section 25.3 “Two-Speed Start-up”
for details). In this mode, the OSTS bit is set. The IOFS
bit may be set if the internal oscillator block is theprimary clock source (see Section 2.4.1 “Oscillator
Control Register”).

3.2.2

SEC_RUN MODE

The SEC_RUN mode is the compatible mode to the“clock switching” feature offered in other PIC18
devices. In this mode, the CPU and peripherals areclocked from the Timer1 oscillator. This gives users theoption of lower power consumption while still using ahigh accuracy clock source.
SEC_RUN mode is entered by setting the SCS1:SCS0
bits to ‘01’. The device clock source is switched to theTimer1 oscillator (see Figure 3-1), the primaryoscillator is shut down, the T1RUN bit (T1CON<6>) is
set and the OSTS bit is cleared.
Note:

Note 1: Caution should be used when modifying asingle IRCF bit. If VDD is less than 3V, it ispossible to select a higher clock speed
than is supported by the low VDD.
Improper device operation may result if
the VDD/FOSC specifications are violated.
2: Executing a SLEEP instruction does notnecessarily place the device into Sleep
mode. It acts as the trigger to place thecontroller into either the Sleep mode, or
one of the Idle modes, depending on thesetting of the IDLEN bit.

Run Modes

The Timer1 oscillator should already berunning prior to entering SEC_RUN mode.
If the T1OSCEN bit is not set when the
SCS1:SCS0 bits are set to ‘01’, entry to
SEC_RUN mode will not occur. If theTimer1 oscillator is enabled but not yet
running, device clocks will be delayed until
the oscillator has started. In suchsituations, initial oscillator operation is far
from stable and unpredictable operation
may result.

On transitions from SEC_RUN mode to PRI_RUN, theperipherals and CPU continue to be clocked from theTimer1 oscillator while the primary clock is started.
When the primary clock becomes ready, a clock switch
back to the primary clock occurs (see Figure 3-2).
When the clock switch is complete, the T1RUN bit iscleared, the OSTS bit is set and the primary clock isproviding the clock. The IDLEN and SCS bits are notaffected by the wake-up; the Timer1 oscillator
continues to run.

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
FIGURE 3-1:

TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE
Q1 Q2 Q3 Q4 Q1

Q2
1

T1OSI

2

3

n-1

Q3

Q4

Q1

Q2

Q3

n

Clock Transition(1)

OSC1
CPU
Clock
Peripheral
Clock
Program
Counter
Note

1:

PC

PC + 2PC + 4Clock transition typically occurs within 2-4 TOSC.

FIGURE 3-2:

TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL)
Q1

Q2

Q3

Q4

Q1

Q2 Q3 Q4 Q1 Q2 Q3

T1OSI
OSC1
TOST(1)

TPLL(1)
1

PLL Clock
Output2

n-1 nClock(2)Transition
CPU Clock
Peripheral
Clock
Program
Counter
SCS1:SCS0 bits Changed
Note

3.2.3

PC + 2PC
OSTS bit Set

1:

TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.

2:

Clock transition typically occurs within 2-4 TOSC.

RC_RUN MODE

In RC_RUN mode, the CPU and peripherals areclocked from the internal oscillator block using the
INTOSC multiplexer; the primary clock is shut down.
When using the INTRC source, this mode provides thebest power conservation of all the Run modes while still
executing code. It works well for user applications
which are not highly timing sensitive or do not require
high-speed clocks at all times.

This mode is entered by setting SCS1 to ‘1’. Although
it is ignored, it is recommended that SCS0 also be
cleared; this is to maintain software compatibility with
future devices. When the clock source is switched to
the INTOSC multiplexer (see Figure 3-3), the primaryoscillator is shut down and the OSTS bit is cleared. The
IRCF bits may be modified at any time to immediatelychange the clock speed.
Note:

If the primary clock source is the internal oscillator
block (either INTRC or INTOSC), there are no distinguishable differences between the PRI_RUN and
RC_RUN modes during execution. However, a clock
switch delay will occur during entry to and exit from
RC_RUN mode. Therefore, if the primary clock sourceis the internal oscillator block, the use of RC_RUN
mode is not recommended.

© 2007 Microchip Technology Inc.

PC + 4

Preliminary

Caution should be used when modifying asingle IRCF bit. If VDD is less than 3V, it ispossible to select a higher clock speed
than is supported by the low VDD.
Improper device operation may result if
the VDD/FOSC specifications are violated.

DS39632D-page 37

PIC18F2455/2550/4455/4550
If the IRCF bits and the INTSRC bit are all clear, the
INTOSC output is not enabled and the IOFS bit willremain clear; there will be no indication of the current
clock source. The INTRC source is providing thedevice clocks.

On transitions from RC_RUN mode to PRI_RUN mode,the device continues to be clocked from the INTOSC
multiplexer while the primary clock is started. When the
primary clock becomes ready, a clock switch to theprimary clock occurs (see Figure 3-4). When the clock
switch is complete, the IOFS bit is cleared, the OSTS
bit is set and the primary clock is providing the device
clock. The IDLEN and SCS bits are not affected by theswitch. The INTRC source will continue to run if either
the WDT or the Fail-Safe Clock Monitor is enabled.

If the IRCF bits are changed from all clear (thus,
enabling the INTOSC output), or if INTSRC is set, the
IOFS bit becomes set after the INTOSC output
becomes stable. Clocks to the device continue while
the INTOSC source stabilizes after an interval of
TIOBST.
If the IRCF bits were previously at a non-zero value or
if INTSRC was set before setting SCS1 and the
INTOSC source was already stable, the IOFS bit willremain set.

FIGURE 3-3:

TRANSITION TIMING TO RC_RUN MODE
Q1 Q2 Q3 Q4 Q1

Q2
1

INTRC

2

3

n-1

Q3

Q4

Q1

Q2

Q3

n

Clock Transition(1)

OSC1
CPU
Clock
Peripheral
Clock
Program
Counter
Note

1:

PC

PC + 2PC + 4Clock transition typically occurs within 2-4 TOSC.

FIGURE 3-4:

TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE
Q1

Q2

Q3

Q4

Q2 Q3 Q4 Q1 Q2 Q3

Q1INTOSC
Multiplexer
OSC1
TOST(1)

TPLL(1)
1

PLL Clock
Output2

n-1 nClock(2)Transition
CPU Clock
Peripheral
Clock
Program
CounterPC

SCS1:SCS0 bits Changed
Note

PC + 2OSTS bit Set

1:

TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.

2:

Clock transition typically occurs within 2-4 TOSC.

DS39632D-page 38

PC + 4

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
3.3

Sleep Mode

3.4

The
power-managed
Sleep
mode
in
the
PIC18F2455/2550/4455/4550 devices is identical to
the legacy Sleep mode offered in all other PIC devices.
It is entered by clearing the IDLEN bit (the default state
on device Reset) and executing the SLEEP instruction.
This shuts down the selected oscillator (Figure 3-5). All
clock source status bits are cleared.

Idle Modes

The Idle modes allow the controller’s CPU to be
selectively shut down while the peripherals continue tooperate. Selecting a particular Idle mode allows users
to further manage power consumption.
If the IDLEN bit is set to ‘1’ when a SLEEP instruction is
executed, the peripherals will be clocked from the clock
source selected using the SCS1:SCS0 bits; however, theCPU will not be clocked. The clock source status bits are
not affected. Setting IDLEN and executing a SLEEP
instruction provides a quick method of switching from agiven Run mode to its corresponding Idle mode.

Entering the Sleep mode from any other mode does not
require a clock switch. This is because no clocks areneeded once the controller has entered Sleep. If the
WDT is selected, the INTRC source will continue tooperate. If the Timer1 oscillator is enabled, it will also
continue to run.

If the WDT is selected, the INTRC source will continue
to operate. If the Timer1 oscillator is enabled, it will also
continue to run.

When a wake event occurs in Sleep mode (by interrupt,
Reset or WDT time-out), the device will not be clocked
until the clock source selected by the SCS1:SCS0 bits
becomes ready (see Figure 3-6), or it will be clockedfrom the internal oscillator block if either the
Two-Speed Start-up or the Fail-Safe Clock Monitor are
enabled (see Section 25.0 “Special Features of theCPU”). In either case, the OSTS bit is set when the
primary clock is providing the device clocks. The
IDLEN and SCS bits are not affected by the wake-up.

Since the CPU is not executing instructions, the only
exits from any of the Idle modes are by interrupt, WDT
time-out or a Reset. When a wake event occurs, CPU
execution is delayed by an interval of TCSD
(parameter 38, Table 28-12) while it becomes ready to
execute code. When the CPU begins executing code,
it resumes with the same clock source for the current
Idle mode. For example, when waking from RC_IDLE
mode, the internal oscillator block will clock the CPU
and peripherals (in other words, RC_RUN mode). The
IDLEN and SCS bits are not affected by the wake-up.
While in any Idle mode or Sleep mode, a WDT time-out
will result in a WDT wake-up to the Run mode currently
specified by the SCS1:SCS0 bits.

FIGURE 3-5:

TRANSITION TIMING FOR ENTRY TO SLEEP MODE

Q1 Q2 Q3 Q4 Q1
OSC1
CPU
Clock
Peripheral
Clock
Sleep
Program
CounterPC

FIGURE 3-6:

PC + 2

TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL)
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1OSC1PLL Clock
OutputTOST(1)

TPLL(1)

CPU Clock
Peripheral
Clock
Program
CounterPC
Wake Event

PC + 2PC + 4

PC + 6

OSTS bit Set

Note1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 39

PIC18F2455/2550/4455/4550
3.4.1

PRI_IDLE MODE

3.4.2

This mode is unique among the three low-power Idle
modes in that it does not disable the primary device
clock. For timing sensitive applications, this allows forthe fastest resumption of device operation, with its
more accurate primary clock source, since the clock
source does not have to “warm up” or transition fromanother oscillator.
PRI_IDLE mode is entered from PRI_RUN mode bysetting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, set IDLEN
first, then clear the SCS bits and execute SLEEP.
Although the CPU is disabled, the peripherals continue
to be clocked from the primary clock source specified
by the FOSC3:FOSC0 Configuration bits. The OSTS
bit remains set (see Figure 3-7).

In SEC_IDLE mode, the CPU is disabled but the
peripherals continue to be clocked from the Timer1
oscillator. This mode is entered from SEC_RUN by setting the IDLEN bit and executing a SLEEP instruction. If
the device is in another Run mode, set IDLEN first, thenset SCS1:SCS0 to ‘01’ and execute SLEEP. When theclock source is switched to the Timer1 oscillator, theprimary oscillator is shut down, the OSTS bit is cleared
and the T1RUN bit is set.
When a wake event occurs, the peripherals continue tobe clocked from the Timer1 oscillator. After an intervalof TCSD following the wake event, the CPU begins executing code being clocked by the Timer1 oscillator. The
IDLEN and SCS bits are not affected by the wake-up;
the Timer1 oscillator continues to run (see Figure 3-8).

When a wake event occurs, the CPU is clocked from theprimary clock source. A delay of interval TCSD is
required between the wake event and when code
execution starts. This is required to allow the CPU tobecome ready to execute instructions. After the
wake-up, the OSTS bit remains set. The IDLEN and
SCS bits are not affected by the wake-up (seeFigure 3-8).

FIGURE 3-7:

SEC_IDLE MODENote:

The Timer1 oscillator should already berunning prior to entering SEC_IDLE mode.
If the T1OSCEN bit is not set when the
SLEEP instruction is executed, the SLEEP
instruction will be ignored and entry to
SEC_IDLE mode will not occur. If theTimer1 oscillator is enabled but not yet
running, peripheral clocks will be delayed
until the oscillator has started. In suchsituations, initial oscillator operation is far
from stable and unpredictable operation
may result.

TRANSITION TIMING FOR ENTRY TO IDLE MODE
Q1

Q4

Q3

Q2

Q1

OSC1
CPU Clock
Peripheral
Clock
Program
CounterPC

FIGURE 3-8:

PC + 2

TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE
Q1

Q2

Q3

Q4

OSC1
TCSD
CPU Clock
Peripheral
Clock
Program
CounterPC

Wake Event

DS39632D-page 40

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
3.4.3

RC_IDLE MODE

In RC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the internal oscillator
block using the INTOSC multiplexer. This mode allows
for controllable power conservation during Idle periods.
From RC_RUN, this mode is entered by setting the
IDLEN bit and executing a SLEEP instruction. If thedevice is in another Run mode, first set IDLEN, then set
the SCS1 bit and execute SLEEP. Although its value isignored, it is recommended that SCS0 also be cleared;
this is to maintain software compatibility with future
devices. The INTOSC multiplexer may be used to
select a higher clock frequency by modifying the IRCF
bits before executing the SLEEP instruction. When theclock source is switched to the INTOSC multiplexer, theprimary oscillator is shut down and the OSTS bit iscleared.
If the IRCF bits are set to any non-zero value, or the
INTSRC bit is set, the INTOSC output is enabled. The
IOFS bit becomes set after the INTOSC output
becomes stable, after an interval of TIOBST(parameter 39, Table 28-12). Clocks to the peripherals
continue while the INTOSC source stabilizes. If the
IRCF bits were previously at a non-zero value, or
INTSRC was set before the SLEEP instruction was
executed and the INTOSC source was already stable,
the IOFS bit will remain set. If the IRCF bits and
INTSRC are all clear, the INTOSC output will not beenabled, the IOFS bit will remain clear and there will be
no indication of the current clock source.
When a wake event occurs, the peripherals continue tobe clocked from the INTOSC multiplexer. After a delayof TCSD following the wake event, the CPU begins
executing code being clocked by the INTOSC multiplexer. The IDLEN and SCS bits are not affected by the
wake-up. The INTRC source will continue to run ifeither the WDT or the Fail-Safe Clock Monitor isenabled.

3.5

Exiting Idle and Sleep Modes

An exit from Sleep mode or any of the Idle modes istriggered by an interrupt, a Reset or a WDT time-out.
This section discusses the triggers that cause exits
from power-managed modes. The clocking subsystem
actions are discussed in each of the power-managed
modes (see Section 3.2 “Run Modes”, Section 3.3“Sleep Mode” and Section 3.4 “Idle Modes”).

3.5.1

EXIT BY INTERRUPT

Any of the available interrupt sources can cause thedevice to exit from an Idle mode, or the Sleep mode, toa Run mode. To enable this functionality, an interrupt
source must be enabled by setting its enable bit in oneof the INTCON or PIE registers. The exit sequence isinitiated when the corresponding interrupt flag bit is set.

© 2007 Microchip Technology Inc.

On all exits from Idle or Sleep modes by interrupt, code
execution branches to the interrupt vector if the
GIE/GIEH bit (INTCON<7>) is set. Otherwise, code
execution continues or resumes without branching(see Section 9.0 “Interrupts”).
A fixed delay of interval TCSD following the wake eventis required when leaving Sleep and Idle modes. Thisdelay is required for the CPU to prepare for execution.
Instruction execution resumes on the first clock cycle
following this delay.

3.5.2

EXIT BY WDT TIME-OUT

A WDT time-out will cause different actions dependingon which power-managed mode the device is in when
the time-out occurs.
If the device is not executing code (all Idle modes andSleep mode), the time-out will result in an exit from thepower-managed mode (see Section 3.2 “Run
Modes” and Section 3.3 “Sleep Mode”). If the device
is executing code (all Run modes), the time-out will
result in a WDT Reset (see Section 25.2 “Watchdog
Timer (WDT)”).
The WDT timer and postscaler are cleared by executing a SLEEP or CLRWDT instruction, the loss of acurrently selected clock source (if the Fail-Safe Clock
Monitor is enabled) and modifying the IRCF bits in the
OSCCON register if the internal oscillator block is thedevice clock source.

3.5.3

EXIT BY RESET

Normally, the device is held in Reset by the Oscillator
Start-up Timer (OST) until the primary clock becomes
ready. At that time, the OSTS bit is set and the device
begins executing code. If the internal oscillator block is
the new clock source, the IOFS bit is set instead.
The exit delay time from Reset to the start of code
execution depends on both the clock sources before
and after the wake-up and the type of oscillator if the
new clock source is the primary clock. Exit delays are
summarized in Table 3-2.
Code execution can begin before the primary clock
becomes ready. If either the Two-Speed Start-up (seeSection 25.3 “Two-Speed Start-up”) or Fail-Safe
Clock Monitor (see Section 25.4 “Fail-Safe Clock
Monitor”) is enabled, the device may begin execution
as soon as the Reset source has cleared. Execution isclocked by the INTOSC multiplexer driven by theinternal oscillator block. Execution is clocked by theinternal oscillator block until either the primary clock
becomes ready or a power-managed mode is entered
before the primary clock becomes ready; the primaryclock is then shut down.

Preliminary

DS39632D-page 41

PIC18F2455/2550/4455/4550
3.5.4

EXIT WITHOUT AN OSCILLATORSTART-UP DELAY

Certain exits from power-managed modes do notinvoke the OST at all. There are two cases:• PRI_IDLE mode, where the primary clock source
is not stopped; and• the primary clock source is not any of the XT or
HS modes.

TABLE 3-2:

In these instances, the primary clock source either
does not require an oscillator start-up delay, since it isalready running (PRI_IDLE), or normally does not
require an oscillator start-up delay (EC and any internal
oscillator modes). However, a fixed delay of interval
TCSD following the wake event is still required whenleaving Sleep and Idle modes to allow the CPU to
prepare for execution. Instruction execution resumeson the first clock cycle following this delay.

EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE
(BY CLOCK SOURCES)
Microcontroller Clock Source
Exit Delay

Before Wake-up

After Wake-up

Primary Device Clock(PRI_IDLE mode)

XTPLL, HSPLL

Clock Ready Status
Bit (OSCCON)

XT, HSEC

None

INTOSC(3)T1OSC or INTRC(1)INTOSC(3)None(Sleep mode)

3:
4:
5:

IOFS

XT, HSTOST(4)

XTPLL, HSPLLTOST + trc(4)EC

TCSD(2)INTOSC(3)TIOBST(5)XT, HSTOST(4)

XTPLL, HSPLLTOST + trc(4)EC

TCSD(2)

OSTS
IOFS
OSTS

INTOSC(3)None

XT, HSTOST(4)

XTPLL, HSPLLTOST + trc(4)

OSTS

EC

TCSD(2)
TIOBST(5)IOFS

INTOSC(3)Note 1:
2:

OSTS

IOFS

In this instance, refers specifically to the 31 kHz INTRC clock source.
TCSD (parameter 38, Table 28-12) is a required delay when waking from Sleep and all Idle modes and runs
concurrently with any other required delays (see Section 3.4 “Idle Modes”).
Includes both the INTOSC 8 MHz source and postscaler derived frequencies.
TOST is the Oscillator Start-up Timer period (parameter 32, Table 28-12). trc is the PLL lock time-out(parameter F12, Table 28-9); it is also designated as TPLL.
Execution continues during TIOBST (parameter 39, Table 28-12), the INTOSC stabilization period.

DS39632D-page 42

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
4.0

RESET

A simplified block diagram of the on-chip Reset circuit
is shown in Figure 4-1.

The PIC18F2455/2550/4455/4550 devices differentiate
between various kinds of Reset:
a)
b)
c)
d)
e)
f)
g)
h)

Power-on Reset (POR)
MCLR Reset during normal operation
MCLR Reset during power-managed modes
Watchdog Timer (WDT) Reset (duringexecution)
Programmable Brown-out Reset (BOR)
RESET Instruction
Stack Full Reset
Stack Underflow Reset

RCON Register

Device Reset events are tracked through the RCON
register (Register 4-1). The lower five bits of the register indicate that a specific Reset event has occurred. In
most cases, these bits can only be cleared by the eventand must be set by the application after the event. The
state of these flag bits, taken together, can be read toindicate the type of Reset that just occurred. This is
described in more detail in Section 4.6 “Reset Stateof Registers”.

This section discusses Resets generated by MCLR,
POR and BOR and covers the operation of the various
start-up timers. Stack Reset events are covered in
Section 5.1.2.4 “Stack Full and Underflow Resets”.
WDT Resets are covered in Section 25.2 “Watchdog
Timer (WDT)”.

FIGURE 4-1:

4.1

The RCON register also has control bits for settinginterrupt priority (IPEN) and software control of the
BOR (SBOREN). Interrupt priority is discussed in
Section 9.0 “Interrupts”. BOR is covered in
Section 4.4 “Brown-out Reset (BOR)”.

SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUITRESETInstruction
Stack Full/Underflow Reset

Stack
Pointer

External Reset
MCLR

MCLRE
( )_IDLE
Sleep
WDT
Time-out
VDD Rise
DetectPOR Pulse

VDD
Brown-out
Reset

S

BOREN
OST/PWRT
OST1024 Cycles

Chip_Reset

10-Bit Ripple Counter

R

OSC1
32 μs
INTRC(1)PWRT

Q

65.5 ms

11-Bit Ripple Counter

Enable PWRT
Enable OST(2)Note 1:
2:This is the INTRC source from the internal oscillator block and is separate from the RC oscillator of the CLKI pin.
See Table 4-2 for time-out situations.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 43

PIC18F2455/2550/4455/4550
REGISTER 4-1:

RCON: RESET CONTROL REGISTER

R/W-0

R/W-1(1)

U-0

R/W-1

R-1

R-1

R/W-0(2)

R/W-0

IPEN

SBOREN

—

RI

TO

PD

POR

BOR

bit 7

bit 0

Legend:R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’-n = Value at POR‘1’ = Bit is set‘0’ = Bit is clearedx = Bit is unknown

bit 7

IPEN: Interrupt Priority Enable bit
1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode)

bit 6

SBOREN: BOR Software Enable bit(1)If BOREN1:BOREN0 = 01:
1 = BOR is enabled
0 = BOR is disabled
If BOREN1:BOREN0 = 00, 10 or 11:
Bit is disabled and read as ‘0’.

bit 5

Unimplemented: Read as ‘0’

bit 4

RI: RESET Instruction Flag bit
1 = The RESET instruction was not executed (set by firmware only)
0 = The RESET instruction was executed causing a device Reset (must be set in software after a
Brown-out Reset occurs)

bit 3

TO: Watchdog Time-out Flag bit
1 = Set by power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred

bit 2

PD: Power-Down Detection Flag bit
1 = Set by power-up or by the CLRWDT instruction
0 = Set by execution of the SLEEP instruction

bit 1

POR: Power-on Reset Status bit(2)1 = A Power-on Reset has not occurred (set by firmware only)
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

bit 0

BOR: Brown-out Reset Status bit
1 = A Brown-out Reset has not occurred (set by firmware only)
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

Note 1:
2:

If SBOREN is enabled, its Reset state is ‘1’; otherwise, it is ‘0’.
The actual Reset value of POR is determined by the type of device Reset. See the notes following thisregister and Section 4.6 “Reset State of Registers” for additional information.

Note 1: It is recommended that the POR bit be set after a Power-on Reset has been detected so that subsequentPower-on Resets may be detected.
2: Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to‘1’ by software immediately after POR).

DS39632D-page 44

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
4.2

FIGURE 4-2:

Master Clear Reset (MCLR)

The MCLR pin provides a method for triggering an
external Reset of the device. A Reset is generated byholding the pin low. These devices have a noise filter inthe MCLR Reset path which detects and ignores small
pulses.

In PIC18F2455/2550/4455/4550 devices, the MCLR
input can be disabled with the MCLRE Configuration
bit. When MCLR is disabled, the pin becomes a digital
input. See Section 10.5 “PORTE, TRISE and LATE
Registers” for more information.

4.3

VDD

VDD

The MCLR pin is not driven low by any internal Resets,
including the WDT.

EXTERNAL POWER-ON
RESET CIRCUIT (FORSLOW VDD POWER-UP)

D

R
R1
MCLR
C

PIC18FXXXXNote 1:

External Power-on Reset circuit is required
only if the VDD power-up slope is too slow.
The diode D helps discharge the capacitor
quickly when VDD powers down.

2:

R < 40 kΩ is recommended to make sure thatthe voltage drop across R does not violate
the device’s electrical specification.

3:

R1 ≥ 1 kΩ will limit any current flowing into
MCLR from external capacitor C, in the eventof MCLR/VPP pin breakdown, due to Electrostatic Discharge (ESD) or Electrical
Overstress (EOS).

Power-on Reset (POR)

A Power-on Reset pulse is generated on-chip
whenever VDD rises above a certain threshold. This
allows the device to start in the initialized state when
VDD is adequate for operation.
To take advantage of the POR circuitry, tie the MCLR pin
through a resistor (1 kΩ to 10 kΩ) to VDD. This will
eliminate external RC components usually needed tocreate a Power-on Reset delay. A minimum rise rate for
VDD is specified (parameter D004, Section 28.1 “DC
Characteristics”). For a slow rise time, see Figure 4-2.
When the device starts normal operation (i.e., exits theReset condition), device operating parameters (voltage, frequency, temperature, etc.) must be met toensure operation. If these conditions are not met, thedevice must be held in Reset until the operating
conditions are met.
POR events are captured by the POR bit (RCON<1>).
The state of the bit is set to ‘0’ whenever a POR occurs;
it does not change for any other Reset event. POR is
not reset to ‘1’ by any hardware event. To capture
multiple events, the user manually resets the bit to ‘1’
in software following any POR.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 45

PIC18F2455/2550/4455/4550
4.4

Brown-out Reset (BOR)

PIC18F2455/2550/4455/4550 devices implement a
BOR circuit that provides the user with a number ofconfiguration and power-saving options. The BOR
is controlled by the BORV1:BORV0 and
BOREN1:BOREN0 Configuration bits. There are a totalof four BOR configurations which are summarized inTable 4-1.
The BOR threshold is set by the BORV1:BORV0 bits. If
BOR is enabled (any values of BOREN1:BOREN0
except ‘00’), any drop of VDD below VBOR (parameter
D005, Section 28.1 “DC Characteristics”) for
greater than TBOR (parameter 35, Table 28-12) will
reset the device. A Reset may or may not occur if VDD
falls below VBOR for less than TBOR. The chip willremain in Brown-out Reset until VDD rises above VBOR.
If the Power-up Timer is enabled, it will be invoked after
VDD rises above VBOR; it then will keep the chip in
Reset for an additional time delay, TPWRT(parameter 33, Table 28-12). If VDD drops below VBOR
while the Power-up Timer is running, the chip will goback into a Brown-out Reset and the Power-up Timer
will be initialized. Once VDD rises above VBOR, thePower-up Timer will execute the additional time delay.
BOR and the Power-on Timer (PWRT) are
independently configured. Enabling BOR Reset does
not automatically enable the PWRT.

4.4.1

SOFTWARE ENABLED BORWhen BOREN1:BOREN0 = 01, the BOR can be
enabled or disabled by the user in software. This isdone with the control bit, SBOREN (RCON<6>).
Setting SBOREN enables the BOR to function aspreviously described. Clearing SBOREN disables the
BOR entirely. The SBOREN bit operates only in thismode; otherwise, it is read as ‘0’.

TABLE 4-1:

Placing the BOR under software control gives the user
the additional flexibility of tailoring the application to its
environment without having to reprogram the device tochange BOR configuration. It also allows the user totailor device power consumption in software by eliminating the incremental current that the BOR consumes.
While the BOR current is typically very small, it may
have some impact in low-power applications.
Note:

4.4.2

Even when BOR is under software control,
the BOR Reset voltage level is still set by
the BORV1:BORV0 Configuration bits. It
cannot be changed in software.

DETECTING BORWhen BOR is enabled, the BOR bit always resets to ‘0’on any BOR or POR event. This makes it difficult todetermine if a BOR event has occurred just by reading
the state of BOR alone. A more reliable method is tosimultaneously check the state of both POR and BOR.
This assumes that the POR bit is reset to ‘1’ in software
immediately after any POR event. IF BOR is ‘0’ while
POR is ‘1’, it can be reliably assumed that a BOR event
has occurred.

4.4.3

DISABLING BOR IN SLEEP MODE

When BOREN1:BOREN0 = 10, the BOR remains
under hardware control and operates as previously
described. Whenever the device enters Sleep mode,
however, the BOR is automatically disabled. When thedevice returns to any other operating mode, BOR is
automatically re-enabled.
This mode allows for applications to recover frombrown-out situations, while actively executing code,when the device requires BOR protection the most. At
the same time, it saves additional power in Sleep modeby eliminating the small incremental BOR current.

BOR CONFIGURATIONSBOR Configuration
BOREN1

BOREN0Status of
SBOREN(RCON<6>)00Unavailable

BOR disabled; must be enabled by reprogramming the Configuration bits.

0

1

Available

BOR enabled in software; operation controlled by SBOREN.

1

0

Unavailable

BOR enabled in hardware in Run and Idle modes, disabled during Sleep
mode.

1

1

Unavailable

BOR enabled in hardware; must be disabled by reprogramming theConfiguration bits.

DS39632D-page 46

Preliminary

BOR Operation© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
4.5

4.5.3

Device Reset Timers

With the PLL enabled in its PLL mode, the time-out
sequence following a Power-on Reset is slightly different from other oscillator modes. A separate timer isused to provide a fixed time-out that is sufficient for the
PLL to lock to the main oscillator frequency. This PLL
lock time-out (TPLL) is typically 2 ms and follows theoscillator start-up time-out.

PIC18F2455/2550/4455/4550 devices incorporate
three separate on-chip timers that help regulate thePower-on Reset process. Their main function is toensure that the device clock is stable before code is
executed. These timers are:• Power-up Timer (PWRT)• Oscillator Start-up Timer (OST)• PLL Lock Time-out

4.5.1

4.5.4

TIME-OUT SEQUENCE

On power-up, the time-out sequence is as follows:

POWER-UP TIMER (PWRT)

1.

The Power-up Timer (PWRT) of the PIC18F2455/2550/
4455/4550 devices is an 11-bit counter which uses the
INTRC source as the clock input. This yields anapproximate time interval of 2048 x 32 μs = 65.6 ms.
While the PWRT is counting, the device is held in
Reset.

2.

After the POR condition has cleared, PWRT
time-out is invoked (if enabled).
Then, the OST is activated.

The total time-out will vary based on oscillator configuration and the status of the PWRT. Figure 4-3,
Figure 4-4, Figure 4-5, Figure 4-6 and Figure 4-7 all
depict time-out sequences on power-up, with thePower-up Timer enabled and the device operating in
HS Oscillator mode. Figures 4-3 through 4-6 also apply
to devices operating in XT mode. For devices in RC
mode and with the PWRT disabled, on the other hand,
there will be no time-out at all.

The power-up time delay depends on the INTRC clock
and will vary from chip to chip due to temperature andprocess variation. See DC parameter 33 (Table 28-12)
for details.
The PWRT is enabled by clearing the PWRTEN
Configuration bit.

4.5.2

PLL LOCK TIME-OUT

Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, all time-outs will expire. Bringing MCLR high will begin execution immediately(Figure 4-5). This is useful for testing purposes or tosynchronize more than one PIC18FXXXX device
operating in parallel.

OSCILLATOR START-UP
TIMER (OST)The Oscillator Start-up Timer (OST) provides a1024 oscillator cycle (from OSC1 input) delay after the
PWRT delay is over (parameter 33, Table 28-12). This
ensures that the crystal oscillator or resonator has
started and stabilized.
The OST time-out is invoked only for XT, HS andHSPLL modes and only on Power-on Reset or on exitfrom most power-managed modes.

TABLE 4-2:

TIME-OUT IN VARIOUS SITUATIONSPower-up(2) and Brown-out

Oscillator
Configuration

PWRTEN = 0

PWRTEN = 1

66 ms(1) + 1024 TOSC

HS, XT
HSPLL, XTPLL

66 ms

(1)

+ 1024 TOSC + 2 ms

1024 TOSC(2)1024 TOSC + 2 ms

66 ms(1)EC, ECIOECPLL, ECPIO

66 ms(1)+ 2 msExit fromPower-Managed Mode

—
(2)

2 ms

1024 TOSC(2)1024 TOSC + 2 ms(2)—(2)

2 ms(2)INTIO, INTCKO

66 ms(1)——INTHS, INTXT

66 ms(1) + 1024 TOSC

1024 TOSC

1024 TOSC

Note 1:
2:

66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay.
2 ms is the nominal time required for the PLL to lock.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 47

PIC18F2455/2550/4455/4550
FIGURE 4-3:

TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT)

VDD
MCLR
INTERNAL POR
TPWRTPWRT TIME-OUT

TOST

OST TIME-OUT

INTERNAL RESETTIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1

FIGURE 4-4:

VDD
MCLR
INTERNAL POR
TPWRTPWRT TIME-OUT

TOST

OST TIME-OUT

INTERNAL RESETTIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2

FIGURE 4-5:

VDD
MCLR
INTERNAL POR
TPWRTPWRT TIME-OUT

TOST

OST TIME-OUT

INTERNAL RESET

DS39632D-page 48

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
FIGURE 4-6:

SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT)
5V
VDD

1V

0V

MCLR
INTERNAL POR
TPWRTPWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESETFIGURE 4-7:

TIME-OUT SEQUENCE ON POR w/PLL ENABLED (MCLR TIED TO VDD)

VDD
MCLR
INTERNAL POR
TPWRTPWRT TIME-OUT

TOST
TPLL

OST TIME-OUT

PLL TIME-OUT
INTERNAL RESETNote:TOST = 1024 clock cycles.
TPLL ≈ 2 ms max. First three stages of the Power-up Timer.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 49

PIC18F2455/2550/4455/4550
4.6

Reset State of Registers

Most registers are unaffected by a Reset. Their statusis unknown on POR and unchanged by all other
Resets. The other registers are forced to a “Resetstate” depending on the type of Reset that occurred.

Table 4-4 describes the Reset states for all of theSpecial Function Registers. These are categorized byPower-on and Brown-out Resets, Master Clear and
WDT Resets and WDT wake-ups.

Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal operation. Status bits from the RCON register, RI, TO, PD,
POR and BOR, are set or cleared differently in different
Reset situations as indicated in Table 4-3. These bits
are used in software to determine the nature of theReset.

TABLE 4-3:

STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION
FOR RCON REGISTERRCON Register

STKPTR Register

Program
Counter

SBOREN

RI

TO

PD

0000h

1

1

1

1

0

0

0

0

RESET Instruction

0000h

u(2)

0

u

u

u

u

u

u

Brown-out

0000h

u(2)

1

1

1

u

0

u

u

MCLR during Power-Managed
Run modes

0000h

u(2)

u

1

u

u

u

u

u

MCLR during Power-Managed
Idle modes and Sleep mode

0000h

u(2)

u

1

0

u

u

u

u

WDT Time-out during Full Poweror Power-Managed Run modes

0000h

u(2)

u

0

u

u

u

u

u

MCLR during Full Power
Execution

0000h

u(2)

u

u

u

u

u

u

u

Stack Full Reset (STVREN = 1)

0000h

u(2)

u

u

u

u

u

1

u

Stack Underflow Reset(STVREN = 1)

0000h

u(2)

u

u

u

u

u

u

1

Stack Underflow Error (not an
actual Reset, STVREN = 0)

0000h

u(2)

u

u

u

u

u

u

1

WDT Time-out during
Power-Managed Idle or Sleepmodes

PC + 2

u(2)

u

0

0

u

u

u

u

Interrupt Exit fromPower-Managed modes

PC + 2(1)

u(2)

u

u

0

u

u

u

u

Condition
Power-on Reset

POR BOR STKFULSTKUNF

Legend: u = unchanged
Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with theinterrupt vector (008h or 0018h).
2: Reset state is ‘1’ for POR and unchanged for all other Resets when software BOR is enabled(BOREN1:BOREN0 Configuration bits = 01 and SBOREN = 1); otherwise, the Reset state is ‘0’.

DS39632D-page 50

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
TABLE 4-4:

INITIALIZATION CONDITIONS FOR ALL REGISTERS
Applicable Devices

Power-on Reset,
Brown-out Reset

MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets

TOSU

2455 2550 4455 4550---0 0000---0 0000---0 uuuu(1)TOSH

2455 2550 4455 4550

0000 0000

0000 0000

uuuu uuuu(1)TOSL

2455 2550 4455 4550

0000 0000

0000 0000

uuuu uuuu(1)STKPTR2455 2550 4455 4550

00-0 0000

uu-0 0000

uu-u uuuu(1)PCLATU2455 2550 4455 4550---0 0000---0 0000---u uuuu

PCLATH

2455 2550 4455 4550

0000 0000

0000 0000

uuuu uuuu

PCL2455 2550 4455 4550

0000 0000

0000 0000

PC + 2(3)

TBLPTRU

2455 2550 4455 4550--00 0000--00 0000--uu uuuu

TBLPTRH

2455 2550 4455 4550

0000 0000

0000 0000

uuuu uuuu

TBLPTRL

2455 2550 4455 4550

0000 0000

0000 0000

uuuu uuuu

TABLAT

2455 2550 4455 4550

0000 0000

0000 0000

uuuu uuuu

PRODH

2455 2550 4455 4550

xxxx xxxx

uuuu uuuu

uuuu uuuu

PRODL

2455 2550 4455 4550

xxxx xxxx

uuuu uuuu

uuuu uuuu

INTCON2455 2550 4455 4550

0000 000x

0000 000u

uuuu uuuu(2)INTCON22455 2550 4455 4550

1111 -1-11111 -1-1

uuuu -u-u(2)INTCON32455 2550 4455 4550

11-0 0-00

11-0 0-00

uu-u u-uu(2)INDF02455 2550 4455 4550

N/A

N/A

N/A

POSTINC02455 2550 4455 4550

N/A

N/A

N/A

POSTDEC02455 2550 4455 4550

N/A

N/A

N/A

PREINC02455 2550 4455 4550

N/A

N/A

N/A

RegisterWake-up via WDT
or Interrupt

PLUSW02455 2550 4455 4550

N/A

N/A

N/A

FSR0H

2455 2550 4455 4550---- 0000---- 0000---- uuuu

FSR0L

2455 2550 4455 4550

xxxx xxxx

uuuu uuuu

uuuu uuuu

WREG2455 2550 4455 4550

xxxx xxxx

uuuu uuuu

uuuu uuuu

INDF1

2455 2550 4455 4550

N/A

N/A

N/A

POSTINC12455 2550 4455 4550

N/A

N/A

N/A

POSTDEC12455 2550 4455 4550

N/A

N/A

N/A

PREINC12455 2550 4455 4550

N/A

N/A

N/A

PLUSW12455 2550 4455 4550

N/A

N/A

N/A

FSR1H

2455 2550 4455 4550---- 0000---- 0000---- uuuu

FSR1L

2455 2550 4455 4550

xxxx xxxx

uuuu uuuu

uuuu uuuu

BSR

2455 2550 4455 4550---- 0000---- 0000---- uuuu

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
4: See Table 4-3 for Reset value for specific condition.
5: PORTA<6>, LATA<6> and TRISA<6> are enabled depending on the oscillator mode selected. When notenabled as PORTA pins, they are disabled and read ‘0’.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 51

PIC18F2455/2550/4455/4550
TABLE 4-4:

INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Applicable Devices

Power-on Reset,
Brown-out Reset

MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets

Wake-up via WDT
or Interrupt

INDF2

2455 2550 4455 4550

N/A

N/A

N/A

POSTINC22455 2550 4455 4550

N/A

N/A

N/A

POSTDEC22455 2550 4455 4550

N/A

N/A

N/A

PREINC22455 2550 4455 4550

N/A

N/A

N/A

Register

PLUSW22455 2550 4455 4550

N/A

N/A

N/A

FSR2H

2455 2550 4455 4550---- 0000---- 0000---- uuuu

FSR2L

2455 2550 4455 4550

xxxx xxxx

uuuu uuuu

uuuu uuuu

STATUS2455 2550 4455 4550---x xxxx---u uuuu---u uuuu

TMR0H

2455 2550 4455 4550

0000 0000

0000 0000

uuuu uuuu

TMR0L

2455 2550 4455 4550

xxxx xxxx

uuuu uuuu

uuuu uuuu

T0CON

2455 2550 4455 4550

1111 1111

1111 1111

uuuu uuuu

OSCCON2455 2550 4455 4550

0100 q000

0100 00q0

uuuu uuqu

HLVDCON

2455 2550 4455 4550

0-00 0101

0-00 0101

u-uu uuuu

WDTCON2455 2550 4455 4550---- ---0---- ---0---- ---u

(4)

RCON

2455 2550 4455 4550

0q-1 11q0

0q-q qquu

uq-u qquu

TMR1H

2455 2550 4455 4550

xxxx xxxx

uuuu uuuu

uuuu uuuu

TMR1L

2455 2550 4455 4550

xxxx xxxx

uuuu uuuu

uuuu uuuu

T1CON

2455 2550 4455 4550

0000 0000

u0uu uuuu

uuuu uuuu

TMR22455 2550 4455 4550

0000 0000

0000 0000

uuuu uuuu

PR22455 2550 4455 4550

1111 1111

1111 1111

1111 1111

T2CON

2455 2550 4455 4550

-000 0000-000 0000-uuu uuuu

SSPBUF2455 2550 4455 4550

xxxx xxxx

uuuu uuuu

uuuu uuuu

SSPADD2455 2550 4455 4550

0000 0000

0000 0000

uuuu uuuu

SSPSTAT2455 2550 4455 4550

0000 0000

0000 0000

uuuu uuuu

SSPCON12455 2550 4455 4550

0000 0000

0000 0000

uuuu uuuu

SSPCON22455 2550 4455 4550

0000 0000

0000 0000

uuuu uuuu

ADRESH

2455 2550 4455 4550

xxxx xxxx

uuuu uuuu

uuuu uuuu

ADRESL2455 2550 4455 4550

xxxx xxxx

uuuu uuuu

uuuu uuuu

ADCON02455 2550 4455 4550--00 0000--00 0000--uu uuuu

ADCON12455 2550 4455 4550--00 0qqq--00 0qqq--uu uuuu

ADCON22455 2550 4455 4550

0-00 0000

0-00 0000

u-uu uuuu

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
4: See Table 4-3 for Reset value for specific condition.
5: PORTA<6>, LATA<6> and TRISA<6> are enabled depending on the oscillator mode selected. When notenabled as PORTA pins, they are disabled and read ‘0’.

DS39632D-page 52

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
TABLE 4-4:

INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Applicable Devices

Power-on Reset,
Brown-out Reset

MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets

Wake-up via WDT
or Interrupt

CCPR1H

2455 2550 4455 4550

xxxx xxxx

uuuu uuuu

uuuu uuuu

CCPR1L2455 2550 4455 4550

xxxx xxxx

uuuu uuuu

uuuu uuuu

CCP1CON

2455 2550 4455 4550--00 0000--00 0000--uu uuuu

2455 2550 4455 4550

0000 0000

0000 0000

uuuu uuuu

CCPR2H

2455 2550 4455 4550

xxxx xxxx

uuuu uuuu

uuuu uuuu

CCPR2L2455 2550 4455 4550

xxxx xxxx

uuuu uuuu

uuuu uuuu

CCP2CON

2455 2550 4455 4550

0000 0000

0000 0000

uuuu uuuu

BAUDCON

2455 2550 4455 4550

0100 0-00

0100 0-00

uuuu u-uu

ECCP1DEL

2455 2550 4455 4550

0000 0000

0000 0000

uuuu uuuu

ECCP1AS

2455 2550 4455 4550

0000 0000

0000 0000

uuuu uuuu

CVRCON2455 2550 4455 4550

0000 0000

0000 0000

uuuu uuuu

CMCON

2455 2550 4455 4550

0000 0111

0000 0111

uuuu uuuu

TMR3H

2455 2550 4455 4550

xxxx xxxx

uuuu uuuu

uuuu uuuu

TMR3L

2455 2550 4455 4550

xxxx xxxx

uuuu uuuu

uuuu uuuu

T3CON2455 2550 4455 4550

0000 0000

uuuu uuuu

uuuu uuuu

SPBRGH

2455 2550 4455 4550

0000 0000

0000 0000

uuuu uuuu

SPBRG

2455 2550 4455 4550

0000 0000

0000 0000

uuuu uuuu

RCREG

2455 2550 4455 4550

0000 0000

0000 0000

uuuu uuuu

TXREG

2455 2550 4455 4550

0000 0000

0000 0000

uuuu uuuu

TXSTA

2455 2550 4455 4550

0000 0010

0000 0010

uuuu uuuu

RCSTA

2455 2550 4455 4550

0000 000x

0000 000x

uuuu uuuu

EEADR

2455 2550 4455 4550

0000 0000

0000 0000

uuuu uuuu

EEDATA

2455 2550 4455 4550

0000 0000

0000 0000

uuuu uuuu

EECON22455 2550 4455 4550

0000 0000

0000 0000

0000 0000

EECON12455 2550 4455 4550

xx-0 x000

uu-0 u000

uu-0 u000

Register

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
4: See Table 4-3 for Reset value for specific condition.
5: PORTA<6>, LATA<6> and TRISA<6> are enabled depending on the oscillator mode selected. When notenabled as PORTA pins, they are disabled and read ‘0’.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 53

PIC18F2455/2550/4455/4550
TABLE 4-4:

INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Applicable Devices

Power-on Reset,
Brown-out Reset

MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets

Wake-up via WDT
or Interrupt

IPR2

2455 2550 4455 4550

1111 1111

1111 1111

uuuu uuuu

PIR22455 2550 4455 4550

0000 0000

0000 0000

uuuu uuuu(2)PIE22455 2550 4455 4550

0000 0000

0000 0000

uuuu uuuu

IPR12455 2550 4455 4550

1111 1111

1111 1111

uuuu uuuu

2455 2550 4455 4550

-111 1111-111 1111-uuu uuuu

2455 2550 4455 4550

0000 0000

0000 0000

uuuu uuuu(2)2455 2550 4455 4550

-000 0000-000 0000-uuu uuuu

2455 2550 4455 4550

0000 0000

0000 0000

uuuu uuuu

2455 2550 4455 4550

-000 0000-000 0000-uuu uuuu

OSCTUNE

2455 2550 4455 4550

0--0 0000

0--0 0000

u--u uuuu

TRISE

2455 2550 4455 4550---- -111---- -111---- -uuu

TRISD

2455 2550 4455 4550

1111 1111

1111 1111

uuuu uuuu

TRISC2455 2550 4455 4550

11-- -111

11-- -111

uu-- -uuu

TRISB

2455 2550 4455 4550

1111 1111

1111 1111

uuuu uuuu

TRISA

2455 2550 4455 4550

-111 1111(5)-111 1111(5)-uuu uuuu(5)LATE2455 2550 4455 4550---- -xxx---- -uuu---- -uuu

LATD

2455 2550 4455 4550

xxxx xxxx

uuuu uuuu

uuuu uuuu

LATC2455 2550 4455 4550

xx-- -xxx

uu-- -uuu

uu-- -uuu

LATB

2455 2550 4455 4550

xxxx xxxx

uuuu uuuu

uuuu uuuu

LATA(5)2455 2550 4455 4550

-xxx xxxx(5)-uuu uuuu(5)-uuu uuuu(5)PORTE

2455 2550 4455 4550

0--- x000

0--- x000

u--- uuuu

PORTD

2455 2550 4455 4550

xxxx xxxx

uuuu uuuu

uuuu uuuu

PORTC

2455 2550 4455 4550

xxxx -xxx

uuuu -uuu

uuuu -uuu

PORTB

2455 2550 4455 4550

xxxx xxxx

uuuu uuuu

uuuu uuuu

Register

PIR1
PIE1

(5)

(5)

PORTA

2455 2550 4455 4550

-x0x0000(5)-u0u0000(5)-uuu uuuu(5)Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
4: See Table 4-3 for Reset value for specific condition.
5: PORTA<6>, LATA<6> and TRISA<6> are enabled depending on the oscillator mode selected. When notenabled as PORTA pins, they are disabled and read ‘0’.

DS39632D-page 54

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
TABLE 4-4:

INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Applicable Devices

Power-on Reset,
Brown-out Reset

MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets

Wake-up via WDT
or Interrupt

UEP152455 2550 4455 4550---0 0000---0 0000---u uuuu

UEP142455 2550 4455 4550---0 0000---0 0000---u uuuu

UEP132455 2550 4455 4550---0 0000---0 0000---u uuuu

UEP122455 2550 4455 4550---0 0000---0 0000---u uuuu

UEP112455 2550 4455 4550---0 0000---0 0000---u uuuu

UEP102455 2550 4455 4550---0 0000---0 0000---u uuuu

UEP92455 2550 4455 4550---0 0000---0 0000---u uuuu

UEP82455 2550 4455 4550---0 0000---0 0000---u uuuu

UEP72455 2550 4455 4550---0 0000---0 0000---u uuuu

UEP62455 2550 4455 4550---0 0000---0 0000---u uuuu

UEP52455 2550 4455 4550---0 0000---0 0000---u uuuu

UEP42455 2550 4455 4550---0 0000---0 0000---u uuuu

UEP32455 2550 4455 4550---0 0000---0 0000---u uuuu

UEP22455 2550 4455 4550---0 0000---0 0000---u uuuu

UEP12455 2550 4455 4550---0 0000---0 0000---u uuuu

UEP02455 2550 4455 4550---0 0000---0 0000---u uuuu

UCFG

2455 2550 4455 4550

00-0 0000

00-0 0000

uu-u uuuu

UADDR

2455 2550 4455 4550

-000 0000-000 0000-uuu uuuu

UCON2455 2550 4455 4550

-0x0 000--0x0 000--uuu uuu-

USTAT

2455 2550 4455 4550

-xxx xxx--xxx xxx--uuu uuu-

UEIE2455 2550 4455 4550

0--0 0000

0--0 0000

u--u uuuu

UEIR2455 2550 4455 4550

0--0 0000

0--0 0000

u--u uuuu

UIE2455 2550 4455 4550

-000 0000-000 0000-uuu uuuu

UIR2455 2550 4455 4550

-000 0000-000 0000-uuu uuuu

UFRMH

2455 2550 4455 4550---- -xxx---- -xxx---- -uuu

UFRML

2455 2550 4455 4550

xxxx xxxx

xxxx xxxx

uuuu uuuu

SPPCON2455 2550 4455 4550---- --00---- --00---- --uu

SPPEPS2455 2550 4455 4550

00-0 0000

00-0 0000

uu-u uuuu

SPPCFG

2455 2550 4455 4550

0000 0000

0000 0000

uuuu uuuu

SPPDATA

2455 2550 4455 4550

0000 0000

0000 0000

uuuu uuuu

Register

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
4: See Table 4-3 for Reset value for specific condition.
5: PORTA<6>, LATA<6> and TRISA<6> are enabled depending on the oscillator mode selected. When notenabled as PORTA pins, they are disabled and read ‘0’.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 55

PIC18F2455/2550/4455/4550
NOTES:DS39632D-page 56

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
MEMORY ORGANIZATION

5.1

There are three types of memory in PIC18 enhanced
microcontroller devices:• Program Memory• Data RAM• Data EEPROM
As Harvard architecture devices, the data and program
memories use separate busses; this allows for concurrent access of the two memory spaces. The data
EEPROM, for practical purposes, can be regarded asa peripheral device, since it is addressed and accessed
through a set of control registers.
Additional detailed information on the operation of theFlash program memory is provided in Section 6.0“Flash Program Memory”. Data EEPROM isdiscussed separately in Section 7.0 “Data EEPROM
Memory”.

FIGURE 5-1:

Program Memory Organization

PIC18 microcontrollers implement a 21-bit program
counter which is capable of addressing a 2-Mbyte
program memory space. Accessing a location between
the upper boundary of the physically implemented
memory and the 2-Mbyte address will return all ‘0’s (aNOP instruction).
The PIC18F2455 and PIC18F4455 each have
24 Kbytes of Flash memory and can store up to 12,288
single-word instructions. The PIC18F2550 and
PIC18F4550 each have 32 Kbytes of Flash memoryand can store up to 16,384 single-word instructions.
PIC18 devices have two interrupt vectors. The Resetvector address is at 0000h and the interrupt vector
addresses are at 0008h and 0018h.
The program memory maps for PIC18FX455 andPIC18FX550 devices are shown in Figure 5-1.

PROGRAM MEMORY MAP AND STACK FOR PIC18F2455/2550/4455/4550 DEVICES
PIC18FX455

PIC18FX550

PC<20:0>
CALL, RCALL, RETURN,
RETFIE, RETLW, CALLW,ADDULNK, SUBULNK

PC<20:0>
CALL, RCALL, RETURN,
RETFIE, RETLW, CALLW,ADDULNK, SUBULNK

21

21

Stack Level 1

Stack Level 1

•
•
•

•
•
•

Stack Level 31

Stack Level 31

Reset Vector

0000h

Reset Vector

0000hHigh Priority Interrupt Vector 0008h

High Priority Interrupt Vector 0008h

Low Priority Interrupt Vector 0018h

Low Priority Interrupt Vector 0018h

On-Chip
Program Memory
5FFFh
6000h

User Memory Space

On-Chip
Program Memory

Read ‘0’

8000h

Read ‘0’

1FFFFFh
200000h© 2007 Microchip Technology Inc.

7FFFh

User Memory Space

5.0

1FFFFFh
200000hPreliminary

DS39632D-page 57

PIC18F2455/2550/4455/4550
5.1.1

PROGRAM COUNTER

The Program Counter (PC) specifies the address of the
instruction to fetch for execution. The PC is 21 bits wide
and is contained in three separate 8-bit registers. The
low byte, known as the PCL register, is both readable
and writable. The high byte, or PCH register, contains
the PC<15:8> bits; it is not directly readable or writable.
Updates to the PCH register are performed through the
PCLATH register. The upper byte is called PCU. This
register contains the PC<20:16> bits; it is also notdirectly readable or writable. Updates to the PCU
register are performed through the PCLATU register.
The contents of PCLATH and PCLATU are transferredto the program counter by any operation that writes
PCL. Similarly, the upper two bytes of the program
counter are transferred to PCLATH and PCLATU by anoperation that reads PCL. This is useful for computed
offsets to the PC (see Section 5.1.4.1 “Computed
GOTO”).
The PC addresses bytes in the program memory. To
prevent the PC from becoming misaligned with word
instructions, the Least Significant bit of PCL is fixed toa value of ‘0’. The PC increments by 2 to address
sequential instructions in the program memory.
The CALL, RCALL and GOTO program branch
instructions write to the program counter directly. For
these instructions, the contents of PCLATH and
PCLATU are not transferred to the program counter.

5.1.2

RETURN ADDRESS STACK

The return address stack allows any combination of up
to 31 program calls and interrupts to occur. The PC ispushed onto the stack when a CALL or RCALL instruction is executed or an interrupt is Acknowledged. The
PC value is pulled off the stack on a RETURN, RETLW ora RETFIE instruction. PCLATU and PCLATH are notaffected by any of the RETURN or CALL instructions.

FIGURE 5-2:

The stack operates as a 31-word by 21-bit RAM and a
5-bit Stack Pointer, STKPTR. The stack space is notpart of either program or data space. The Stack Pointeris readable and writable and the address on the top of
the stack is readable and writable through the
Top-of-Stack Special Function Registers. Data can also
be pushed to, or popped from the stack, using theseregisters.
A CALL type instruction causes a push onto the stack.
The Stack Pointer is first incremented and the location
pointed to by the Stack Pointer is written with thecontents of the PC (already pointing to the instruction
following the CALL). A RETURN type instruction causes
a pop from the stack. The contents of the location
pointed to by the STKPTR are transferred to the PC
and then the Stack Pointer is decremented.
The Stack Pointer is initialized to ‘00000’ after all
Resets. There is no RAM associated with the location
corresponding to a Stack Pointer value of ‘00000’; thisis only a Reset value. Status bits indicate if the stack isfull, has overflowed or has underflowed.

5.1.2.1

Top-of-Stack Access

Only the top of the return address stack (TOS) is
readable and writable. A set of three registers,
TOSU:TOSH:TOSL, hold the contents of the stack location pointed to by the STKPTR register (Figure 5-2). This
allows users to implement a software stack if necessary.
After a CALL, RCALL or interrupt, the software can readthe pushed value by reading the TOSU:TOSH:TOSL
registers. These values can be placed on a user-defined
software stack. At return time, the software can returnthese values to TOSU:TOSH:TOSL and do a return.
The user must disable the global interrupt enable bits
while accessing the stack to prevent inadvertent stackcorruption.

RETURN ADDRESS STACK AND ASSOCIATED REGISTERS
Return Address Stack<20:0>
11111
11110
11101

Top-of-Stack Registers
TOSU
00h

TOSH
1Ah

STKPTR<4:0>
00010

TOSL
34h
Top-of-Stack

DS39632D-page 58

Stack Pointer

001A34h
000D58hPreliminary

00011
00010
00001
00000

© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
5.1.2.2

Return Stack Pointer (STKPTR)

When the stack has been popped enough times tounload the stack, the next pop will return a value of zeroto the PC and sets the STKUNF bit, while the Stack
Pointer remains at zero. The STKUNF bit will remain
set until cleared by software or until a POR occurs.

The STKPTR register (Register 5-1) contains the Stack
Pointer value, the STKFUL (Stack Full) status bit andthe STKUNF (Stack Underflow) status bit. The value ofthe Stack Pointer can be 0 through 31. The Stack
Pointer increments before values are pushed onto thestack and decrements after values are popped off thestack. On Reset, the Stack Pointer value will be zero.
The user may read and write the Stack Pointer value.
This feature can be used by a Real-Time Operating
System (RTOS) for return stack maintenance.

Note:

After the PC is pushed onto the stack 31 times (without
popping any values off the stack), the STKFUL bit isset. The STKFUL bit is cleared by software or by a
POR.

5.1.2.3

PUSH and POP Instructions

Since the Top-of-Stack is readable and writable, theability to push values onto the stack and pull values off
the stack, without disturbing normal program execution, is a desirable feature. The PIC18 instruction set
includes two instructions, PUSH and POP, that permit
the TOS to be manipulated under software control.
TOSU, TOSH and TOSL can be modified to place dataor a return address on the stack.

The action that takes place when the stack becomesfull depends on the state of the STVREN (Stack
Overflow Reset Enable) Configuration bit. (Refer to
Section 25.1 “Configuration Bits” for a description of
the device Configuration bits.) If STVREN is set(default), the 31st push will push the (PC + 2) value
onto the stack, set the STKFUL bit and reset thedevice. The STKFUL bit will remain set and the Stack
Pointer will be set to zero.

The PUSH instruction places the current PC value onto
the stack. This increments the Stack Pointer and loads
the current PC value onto the stack.

If STVREN is cleared, the STKFUL bit will be set on the
31st push and the Stack Pointer will increment to 31.
Any additional pushes will not overwrite the 31st pushand the STKPTR will remain at 31.

REGISTER 5-1:

Returning a value of zero to the PC on anunderflow has the effect of vectoring the
program to the Reset vector, where thestack conditions can be verified andappropriate actions can be taken. This is
not the same as a Reset, as the contentsof the SFRs are not affected.

The POP instruction discards the current TOS by decrementing the Stack Pointer. The previous value pushed
onto the stack then becomes the TOS value.

STKPTR: STACK POINTER REGISTER

R/C-0

R/C-0

U-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

STKFUL(1)STKUNF(1)

—

SP4

SP3

SP2

SP1

SP0

bit 7

bit 0

Legend:C = Clearable bit

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’-n = Value at POR‘1’ = Bit is set‘0’ = Bit is cleared

bit 7

STKFUL: Stack Full Flag bit(1)1 = Stack became full or overflowed
0 = Stack has not become full or overflowed

bit 6

STKUNF: Stack Underflow Flag bit(1)1 = Stack underflow occurred
0 = Stack underflow did not occur

bit 5

Unimplemented: Read as ‘0’

bit 4-0

SP4:SP0: Stack Pointer Location bits

Note 1:x = Bit is unknown

Bit 7 and bit 6 are cleared by user software or by a POR.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 59

PIC18F2455/2550/4455/4550
5.1.2.4

Stack Full and Underflow Resets

5.1.4

Device Resets on stack overflow and stack underflow
conditions are enabled by setting the STVREN bit inConfiguration Register 4L. When STVREN is set, a fullor underflow condition will set the appropriate STKFULor STKUNF bit and then cause a device Reset. When
STVREN is cleared, a full or underflow condition will set
the appropriate STKFUL or STKUNF bit but not causea device Reset. The STKFUL or STKUNF bits arecleared by user software or a Power-on Reset.

5.1.3

FAST REGISTER STACK

A Fast Register Stack is provided for the STATUS,
WREG and BSR registers to provide a “fast return”
option for interrupts. Each stack is only one level deep
and is neither readable nor writable. It is loaded with thecurrent value of the corresponding register when theprocessor vectors for an interrupt. All interrupt sources
will push values into the stack registers. The values in
the registers are then loaded back into their associatedregisters if the RETFIE, FAST instruction is used toreturn from the interrupt.

LOOK-UP TABLES IN PROGRAMMEMORY

There may be programming situations that require thecreation of data structures, or look-up tables, inprogram memory. For PIC18 devices, look-up tables
can be implemented in two ways:• Computed GOTO
• Table Reads

5.1.4.1

Computed GOTO

A computed GOTO is accomplished by adding an offset
to the program counter. An example is shown in
Example 5-2.
A look-up table can be formed with an ADDWF PCL
instruction and a group of RETLW nn instructions. The
W register is loaded with an offset into the table before
executing a call to that table. The first instruction of thecalled routine is the ADDWF PCL instruction. The next
instruction executed will be one of the RETLW nn
instructions that returns the value ‘nn’ to the calling
function.

If both low and high priority interrupts are enabled, thestack registers cannot be used reliably to return fromlow priority interrupts. If a high priority interrupt occurs
while servicing a low priority interrupt, the stack registervalues stored by the low priority interrupt will beoverwritten. In these cases, users must save the key
registers in software during a low priority interrupt.

The offset value (in WREG) specifies the number ofbytes that the program counter should advance andshould be multiples of 2 (LSb = 0).

If interrupt priority is not used, all interrupts may use theFast Register Stack for returns from interrupt. If nointerrupts are used, the Fast Register Stack can beused to restore the STATUS, WREG and BSR registers
at the end of a subroutine call. To use the Fast Register
Stack for a subroutine call, a CALL label, FAST
instruction must be executed to save the STATUS,
WREG and BSR registers to the Fast Register Stack. A
RETURN, FAST instruction is then executed to restore
these registers from the Fast Register Stack.

EXAMPLE 5-2:

Example 5-1 shows a source code example that uses
the Fast Register Stack during a subroutine call andreturn.

EXAMPLE 5-1:
CALL

FAST REGISTER STACKCODE EXAMPLE

SUB1, FAST;STATUS, WREG, BSR;SAVED IN FAST REGISTER;STACK

•
•
SUB1

•
•
RETURN, FAST

DS39632D-page 60;RESTORE VALUES SAVED;IN FAST REGISTER STACK

In this method, only one data byte may be stored ineach instruction location and room on the return
address stack is required.

ORG
TABLE

5.1.4.2

MOVF
CALL
nn00h
ADDWF
RETLW
RETLW
RETLW
.
.
.

COMPUTED GOTO USINGAN OFFSET VALUEOFFSET, W
TABLE
PCL
nnh
nnh
nnh

Table Reads and Table Writes

A better method of storing data in program memory
allows two bytes of data to be stored in each instruction
location.
Look-up table data may be stored two bytes per
program word by using table reads and writes. The
Table Pointer (TBLPTR) register specifies the byte
address and the Table Latch (TABLAT) registercontains the data that is read from or written to program
memory. Data is transferred to or from program
memory one byte at a time.
Table read and table write operations are discussed
further in Section 6.1 “Table Reads and Table
Writes”.

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
5.2

PIC18 Instruction Cycle

5.2.1

CLOCKING SCHEME

5.2.2

An “Instruction Cycle” consists of four Q cycles: Q1
through Q4. The instruction fetch and execute are pipelined in such a manner that a fetch takes one instruction
cycle, while the decode and execute takes another
instruction cycle. However, due to the pipelining, each
instruction effectively executes in one cycle. If an
instruction causes the program counter to change (e.g.,
GOTO), then two cycles are required to complete theinstruction (Example 5-3).

The microcontroller clock input, whether from aninternal or external source, is internally divided by fourto generate four non-overlapping quadrature clocks(Q1, Q2, Q3 and Q4). Internally, the program counter isincremented on every Q1; the instruction is fetchedfrom the program memory and latched into the Instruction Register (IR) during Q4. The instruction is decodedand executed during the following Q1 through Q4. The
clocks and instruction execution flow are shown in
Figure 5-3.

FIGURE 5-3:

INSTRUCTION FLOW/PIPELINING

A fetch cycle begins with the Program Counter (PC)incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the Instruction Register (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3 and Q4 cycles. Data memory is read during Q2(operand read) and written during Q4 (destination
write).

CLOCK/INSTRUCTION CYCLE
Q1

Q2

Q3

Q4

Q2

Q1

Q3

Q4

Q2

Q1

Q3

Q4

OSC1
Q1
Q2

Internal
Phase
Clock

Q3
Q4
PC

PC

PC + 2PC + 4

OSC2/CLKO(RC mode)
Execute INST (PC – 2)Fetch INST (PC)

EXAMPLE 5-3:

Execute INST (PC)
Fetch INST (PC + 2)

INSTRUCTION PIPELINE FLOW

1. MOVLW 55h

TCY0

TCY1

Fetch 1

Execute 1

2. MOVWF PORTB
3. BRA

SUB_1

4. BSF

PORTA, BIT3 (Forced NOP)

Fetch 2

TCY2

TCY3

TCY4

TCY5

Execute 2
Fetch 3

Execute 3
Fetch 4

Flush (NOP)
Fetch SUB_1 Execute SUB_1

5. Instruction @ address SUB_1

Note:

Execute INST (PC + 2)
Fetch INST (PC + 4)

All instructions are single cycle, except for any program branches. These take two cycles since the fetch
instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 61

PIC18F2455/2550/4455/4550
5.2.3

INSTRUCTIONS IN PROGRAMMEMORYThe program memory is addressed in bytes. Instructions are stored as two bytes or four bytes in program
memory. The Least Significant Byte of an instruction
word is always stored in a program memory location
with an even address (LSb = 0). To maintain alignment
with instruction boundaries, the PC increments in stepsof 2 and the LSb will always read ‘0’ (see Section 5.1.1“Program Counter”).
Figure 5-4 shows an example of how instruction words
are stored in the program memory.

FIGURE 5-4:

The CALL and GOTO instructions have the absoluteprogram memory address embedded into the instruction. Since instructions are always stored on wordboundaries, the data contained in the instruction is aword address. The word address is written to PC<20:1>,
which accesses the desired byte address in program
memory. Instruction #2 in Figure 5-4 shows how the
instruction, GOTO 0006h, is encoded in the program
memory. Program branch instructions, which encode a
relative address offset, operate in the same manner. The
offset value stored in a branch instruction represents thenumber of single-word instructions that the PC will be
offset by. Section 26.0 “Instruction Set Summary”
provides further details of the instruction set.

INSTRUCTIONS IN PROGRAM MEMORYLSB = 1

LSB = 0

0Fh
EFh
F0h
C1h
F4h

55h
03h
00h
23h
56h

Program Memory
Byte Locations →5.2.4

Instruction 1:
Instruction 2:

MOVLW
GOTO

055h
0006h

Instruction 3:

MOVFF

123h, 456h

TWO-WORD INSTRUCTIONSThe standard PIC18 instruction set has four two-word
instructions: CALL, MOVFF, GOTO and LSFR. In allcases, the second word of the instructions always has‘1111’ as its four Most Significant bits; the other 12 bits
are literal data, usually a data memory address.
The use of ‘1111’ in the 4 MSbs of an instruction
specifies a special form of NOP. If the instruction is
executed in proper sequence, immediately after the
first word, the data in the second word is accessed and

EXAMPLE 5-4:

Word Address↓
000000h
000002h000004h000006h
000008h
00000Ah
00000Ch
00000Eh
000010h
000012h000014hused by the instruction sequence. If the first word isskipped for some reason and the second word is
executed by itself, a NOP is executed instead. This isnecessary for cases when the two-word instruction ispreceded by a conditional instruction that changes thePC. Example 5-4 shows how this works.
Note:

See Section 5.5 “Program Memory andthe Extended Instruction Set” for
information on two-word instruction in theextended instruction set.

TWO-WORD INSTRUCTIONSCASE 1:
Object Code

Source Code0110 0110 0000 0000

TSTFSZ

REG1

1100 0001 0010 0011

MOVFF

REG1, REG2 ; No, skip this word

1111 0100 0101 0110
0010 0100 0000 0000

; is RAM location 0?
; Execute this word as a NOP

ADDWF

REG3

; continue code

CASE 2:
Object Code

Source Code0110 0110 0000 0000

TSTFSZ

REG1

1100 0001 0010 0011

MOVFF

REG1, REG2 ; Yes, execute this word

1111 0100 0101 0110
0010 0100 0000 0000

DS39632D-page 62; is RAM location 0?
; 2nd word of instruction

ADDWF

REG3

; continue code

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
5.3
Note:

5.3.2

Data Memory Organization
The operation of some aspects of data
memory are changed when the PIC18
extended instruction set is enabled. See
Section 5.6 “Data Memory and theExtended Instruction Set” for more
information.

The data memory in PIC18 devices is implemented asstatic RAM. Each register in the data memory has a
12-bit address, allowing up to 4096 bytes of data
memory. The memory space is divided into as many as
16
banks
that
contain
256
bytes
each.
PIC18F2455/2550/4455/4550 devices implement eightcomplete banks, for a total of 2048 bytes. Figure 5-5
shows the data memory organization for the devices.
The data memory contains Special Function Registers(SFRs) and General Purpose Registers (GPRs). The
SFRs are used for control and status of the controller
and peripheral functions, while GPRs are used for data
storage and scratchpad operations in the user’s
application. Any read of an unimplemented location will
read as ‘0’s.
The instruction set and architecture allow operations
across all banks. The entire data memory may beaccessed by Direct, Indirect or Indexed Addressing
modes. Addressing modes are discussed later in thissubsection.
To ensure that commonly used registers (SFRs andselect GPRs) can be accessed in a single cycle, PIC18
devices implement an Access Bank. This is a 256-bytememory space that provides fast access to SFRs andthe lower portion of GPR Bank 0 without using the
BSR. Section 5.3.3 “Access Bank” provides adetailed description of the Access RAM.

5.3.1

USB RAM

Banks 4 through 7 of the data memory are actually
mapped to special dual port RAM. When the USB
module is disabled, the GPRs in these banks are used
like any other GPR in the data memory space.
When the USB module is enabled, the memory in thesebanks is allocated as buffer RAM for USB operation.
This area is shared between the microcontroller core
and the USB Serial Interface Engine (SIE) and is used
to transfer data directly between the two.
It is theoretically possible to use the areas of USB RAM
that are not allocated as USB buffers for normal
scratchpad memory or other variable storage. In practice, the dynamic nature of buffer allocation makes thisrisky at best. Additionally, Bank 4 is used for USB buffer
management when the module is enabled and should
not be used for any other purposes during that time.

BANK SELECT REGISTER (BSR)

Large areas of data memory require an efficientaddressing scheme to make rapid access to any
address possible. Ideally, this means that an entire
address does not need to be provided for each read or
write operation. For PIC18 devices, this is accomplished with a RAM banking scheme. This divides thememory space into 16 contiguous banks of 256 bytes.
Depending on the instruction, each location can beaddressed directly by its full 12-bit address, or an 8-bit
low-order address and a 4-bit Bank Pointer.
Most instructions in the PIC18 instruction set make useof the Bank Pointer, known as the Bank Select Register(BSR). This SFR holds the 4 Most Significant bits of alocation’s address; the instruction itself includes theeight Least Significant bits. Only the four lower bits of
the BSR are implemented (BSR3:BSR0). The upper
four bits are unused; they will always read ‘0’ and cannot be written to. The BSR can be loaded directly byusing the MOVLB instruction.
The value of the BSR indicates the bank in data
memory. The eight bits in the instruction show the location in the bank and can be thought of as an offset fromthe bank’s lower boundary. The relationship between
the BSR’s value and the bank division in data memory
is shown in Figure 5-6.
Since up to sixteen registers may share the same
low-order address, the user must always be careful toensure that the proper bank is selected before performing a data read or write. For example, writing whatshould be program data to an 8-bit address of F9h,
while the BSR is 0Fh, will end up resetting the program
counter.
While any bank can be selected, only those banks thatare actually implemented can be read or written to.
Writes to unimplemented banks are ignored, whilereads from unimplemented banks will return ‘0’s. Evenso, the STATUS register will still be affected as if theoperation was successful. The data memory map in
Figure 5-5 indicates which banks are implemented.
In the core PIC18 instruction set, only the MOVFF
instruction fully specifies the 12-bit address of thesource and target registers. This instruction ignores the
BSR completely when it executes. All other instructions
include only the low-order address as an operand andmust use either the BSR or the Access Bank to locate
their target registers.

Additional information on USB RAM and buffer
operation is provided in Section 17.0 “Universal
Serial Bus (USB)”.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 63

PIC18F2455/2550/4455/4550
FIGURE 5-5:

DATA MEMORY MAP FOR PIC18F2455/2550/4455/4550 DEVICES

BSR<3:0>= 000000h

Access RAM

FFh
00h

GPR

Bank 0= 0001= 0011= 0100= 0101= 0110= 0111

1FFh
200h

FFh
00h
Bank 2

Bank 3

Bank 4

Bank 5

GPR
FFh
00h

2FFh
300h
GPR

FFh
00h

Bank 6= 1111

Note 1:

The remaining 160 bytes are
Special Function Registers(from Bank 15).
When a = 1:
The BSR specifies the bankused by the instruction.

4FFh
500h
GPR(1)5FFh
600h
GPR(1)

FFh
00h

6FFh
700h

Bank 8

Access Bank
Access RAM Low

GPR(1)
7FFh
800h

00h

5Fh
Access RAM High 60h(SFRs)
FFh

UnusedRead as 00h

to= 1110The first 96 bytes are
general purpose RAM(from Bank 0).

GPR(1)

FFh
00h= 1000

The BSR is ignored and theAccess Bank is used.

3FFh
400h

FFh
00h

FFh
00h

Bank 7

000h
05Fh
060h
0FFh
100h

GPR

Bank 1= 0010

When a = 0:

Data Memory Map

Bank 14FFh
00h

UnusedFFh

SFR

Bank 15

EFFh
F00h
F5Fh
F60h
FFFh

These banks also serve as RAM buffer for USB operation. See Section 5.3.1 “USB RAM” for more
information.

DS39632D-page 64

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
FIGURE 5-6:

USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING)

0

Data Memory

BSR(1)

7

0

0

0

0

0

0

1

1

000h

00h
Bank 0

FFh
00h

100h
Bank 1

Bank Select(2)From Opcode(2)

7

1

1

1

1

1

1

0

1

1

FFh
00h

200h
Bank 2

FFh
00h

300h

Bank 3through
Bank 13

FFh
00h

E00h
Bank 14

FFh
00h

F00h
Bank 15
FFFh
Note 1:
2:

5.3.3

FFh

The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to
the registers of the Access Bank.
The MOVFF instruction embeds the entire 12-bit address in the instruction.

ACCESS BANK

While the use of the BSR, with an embedded 8-bit
address, allows users to address the entire range ofdata memory, it also means that the user must always
ensure that the correct bank is selected. Otherwise,data may be read from or written to the wrong location.
This can be disastrous if a GPR is the intended targetof an operation but an SFR is written to instead.
Verifying and/or changing the BSR for each read or
write to data memory can become very inefficient.
To streamline access for the most commonly used data
memory locations, the data memory is configured withan Access Bank, which allows users to access amapped block of memory without specifying a BSR.
The Access Bank consists of the first 96 bytes ofmemory (00h-5Fh) in Bank 0 and the last 160 bytes ofmemory (60h-FFh) in Block 15. The lower half is known
as the “Access RAM” and is composed of GPRs. The
upper half is where the device’s SFRs are mapped.
These two areas are mapped contiguously in the
Access Bank and can be addressed in a linear fashion
by an 8-bit address (Figure 5-5).
The Access Bank is used by core PIC18 instructions
that include the Access RAM bit (the ‘a’ parameter in
the instruction). When ‘a’ is equal to ‘1’, the instructionuses the BSR and the 8-bit address included in the
opcode for the data memory address. When ‘a’ is ‘0’,© 2007 Microchip Technology Inc.

however, the instruction is forced to use the AccessBank address map; the current value of the BSR is
ignored entirely.
Using this “forced” addressing allows the instruction tooperate on a data address in a single cycle without
updating the BSR first. For 8-bit addresses of 60h andabove, this means that users can evaluate and operate
on SFRs more efficiently. The Access RAM below 60h
is a good place for data values that the user might needto access rapidly, such as immediate computational
results or common program variables. Access RAM
also allows for faster and more code efficient context
saving and switching of variables.
The mapping of the Access Bank is slightly different
when the extended instruction set is enabled (XINST
Configuration bit = 1). This is discussed in more detailin Section 5.6.3 “Mapping the Access Bank in
Indexed Literal Offset Mode”.

5.3.4

GENERAL PURPOSEREGISTER FILE

PIC18 devices may have banked memory in the GPR
area. This is data RAM which is available for use by all
instructions. GPRs start at the bottom of Bank 0(address 000h) and grow upwards towards the bottomof the SFR area. GPRs are not initialized by aPower-on Reset and are unchanged on all other
Resets.

Preliminary

DS39632D-page 65

PIC18F2455/2550/4455/4550
5.3.5

SPECIAL FUNCTION REGISTERS

The Special Function Registers (SFRs) are registers
used by the CPU and peripheral modules for controllingthe desired operation of the device. These registers are
implemented as static RAM in the data memory space.
SFRs start at the top of data memory and extend downward to occupy the top segment of Bank 15, from F60h
to FFFh. A list of these registers is given in Table 5-1
and Table 5-2.

peripheral functions. The Reset and interrupt registers
are described in their respective chapters, while the
ALU’s STATUS register is described later in thissection. Registers related to the operation of aperipheral feature are described in the chapter for thatperipheral.
The SFRs are typically distributed among theperipherals whose functions they control. Unused SFR
locations are unimplemented and read as ‘0’s.

The SFRs can be classified into two sets: those
associated with the “core” device functionality (ALU,
Resets and interrupts) and those related to the

TABLE 5-1:
Address

SPECIAL FUNCTION REGISTER MAP FOR PIC18F2455/2550/4455/4550 DEVICES
Name

Address

Name
INDF2

(1)

Address

Name

Address

Name

Address

Name

FFFh

TOSU

FDFh

FBFh

CCPR1H

F9Fh

IPR1

F7Fh

UEP15

FFEh

TOSH

FDEh POSTINC2(1)FBEh

CCPR1L

F9Eh

PIR1

F7Eh

UEP14

FFDh

TOSL

FDDh POSTDEC2(1)FBDh

CCP1CON

F9Dh

PIE1

F7Dh

UEP13

FFCh

STKPTR

FDCh

PREINC2(1)FBCh

CCPR2H

F9Ch

—(2)

F7Ch

UEP12

FFBh

PCLATUFDBh

PLUSW2(1)FBBh

CCPR2LF9Bh

OSCTUNE

F7Bh

UEP11

FFAh

PCLATH

FDAh

FSR2H

FBAh

CCP2CON

F9Ah

—(2)

F7Ah

UEP10

FF9h

PCL

FD9h

FSR2L

FB9h

—(2)

F99h

—(2)

F79h

UEP9

FF8h

TBLPTRU

FD8h

STATUS

FB8h

BAUDCON

F98h

—(2)

F78h

UEP8

FF7h

TBLPTRH

FD7h

TMR0H

FB7h

ECCP1DEL

F97h

—(2)

F77h

UEP7

FF6h

TBLPTRL

FD6h

TMR0L

FB6h

ECCP1AS

F96h

TRISE(3)

F76h

UEP6

(3)

F75h

UEP5

F74h

UEP4

FF5h

TABLAT

FD5h

T0CON

FB5h

CVRCON

F95h

TRISD

FF4h

PRODH

FD4h

—(2)

FB4h

CMCON

F94h

TRISC

FF3h

PRODL

FD3h

OSCCON

FB3h

TMR3H

F93h

TRISB

F73h

UEP3

FF2h

INTCONFD2h

HLVDCON

FB2h

TMR3L

F92h

TRISA

F72h

UEP2

FF1h

INTCON2

FD1h

WDTCON

FB1h

T3CON

F91h

—(2)

F71h

UEP1

FF0h

INTCON3

FD0h

RCON

FB0h

SPBRGH

F90h

—(2)

F70h

UEP0

FEFh

INDF0(1)

FCFh

TMR1H

FAFh

SPBRG

F8Fh

—(2)

F6Fh

UCFG

FCEh

TMR1L

FAEh

RCREG

F8Eh

—(2)

F6Eh

UADDR

FEEh POSTINC0(1)
(1)

FCDh

T1CON

FADh

TXREG

FECh

PREINC0(1)

FCCh

TMR2

FACh

TXSTA

FEBh

PLUSW0(1)

FCBh

PR2

FABh

FEAh

FSR0H

FCAh

T2CON

FAAh

FE9h

FSR0L

FC9h

SSPBUF

FA9h

FE8h

WREG

FC8h

SSPADDFA8h

FE7h

INDF1(1)FC7h

SSPSTAT

FA7h

FC6h

SSPCON1

FEDh POSTDEC0

FE6h POSTINC1(1)FE5h POSTDEC1

(1)

(1)

FC5h

ADRESH

LATE

F6Dh

UCON

F8Ch

LATD(3)

F6Ch

USTAT

RCSTA

F8Bh

LATC

F6Bh

UEIE

—(2)

F8Ah

LATB

F6Ah

UEIR

EEADR

F89h

LATA

F69h

UIE

EEDATA

F88h

—(2)

F68h

UIR

EECON2(1)

F87h

—(2)

F67h

UFRMH

FA6h

EECON1

F86h

—(2)

F66h

UFRML

FA5h

—

(2)

F85h

—

(2)

F65h

SPPCON(3)

FA4h

—

(2)

F84h

PORTE

F64h

SPPEPS(3)F83h

PORTD(3)F63h

SPPCFG(3)FE4hPREINC1

FE3h

PLUSW1(1)FC3h

ADRESL

FA3h

—(2)

FE2h

FSR1H

FC2h

ADCON0

FA2h

IPR2

F82h

PORTC

F62h SPPDATA(3)

FE1h

FSR1L

FC1h

ADCON1

FA1h

PIR2

F81h

PORTB

F61h

—(2)

FE0h

BSR

FC0h

ADCON2

FA0h

PIE2

F80h

PORTA

F60h

—(2)

Note 1:
2:
3:

FC4h

SSPCON2

F8Dh(3)

Not a physical register.
Unimplemented registers are read as ‘0’.
These registers are implemented only on 40/44-pin devices.

DS39632D-page 66

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
TABLE 5-2:
File NameTOSUREGISTER FILE SUMMARY (PIC18F2455/2550/4455/4550)
Bit 7

Bit 6

Bit 5

—

—

—

TOSH

Top-of-Stack High Byte (TOS<15:8>)

TOSL

Top-of-Stack Low Byte (TOS<7:0>)

STKPTRSTKFULSTKUNF—PCLATU———PCLATH

Holding Register for PC<15:8>

PCL

PC Low Byte (PC<7:0>)

TBLPTRU
TBLPTRH——

bit 21(1)

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Top-of-Stack Upper Byte (TOS<20:16>)

SP4

SP3

SP2

SP1

SP0

Holding Register for PC<20:16>

Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)

Program Memory Table Pointer High Byte (TBLPTR<15:8>)

Value on
POR, BOR

Details
on page---0 0000

51, 580000 0000

51, 580000 0000

51, 5800-0 0000

51, 59---0 0000

51, 580000 0000

51, 580000 0000

51, 58--00 0000

51, 820000 0000

51, 82

TBLPTRL

Program Memory Table Pointer Low Byte (TBLPTR<7:0>)0000 0000

51, 82TABLAT

Program Memory Table Latch

0000 0000

51, 82

PRODH

Product Register High Byte

xxxx xxxx

51, 95

PRODL

Product Register Low Byte

xxxx xxxx

51, 95INTCON

GIE/GIEH

PEIE/GIEL

TMR0IEINT0IE

0000 000x

51, 99INTCON2RBPU

INTEDG0

INTEDG1

INTCON3

INT2IP

INT1IP—RBIE

TMR0IF

INT0IFRBIFINTEDG2—

TMR0IP—

RBIP

1111 -1-1

51, 100

INT2IEINT1IE—INT2IF

INT1IF

11-0 0-00

51, 101

INDF0

Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register)N/A51, 73POSTINC0

Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register)N/A51, 74

POSTDEC0Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register)N/A51, 74

PREINC0

Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register)N/A51, 74

PLUSW0Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) –value of FSR0 offset by W

N/A

51, 74

FSR0H---- 0000

51, 73

FSR0L

Indirect Data Memory Address Pointer 0 Low Byte

—

—

—

—

Indirect Data Memory Address Pointer 0 High Byte

xxxx xxxx

51, 73

WREG

Working Registerxxxx xxxx

51

INDF1

Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register)N/A51, 73POSTINC1

Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register)N/A51, 74

POSTDEC1

Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register)N/A51, 74

PREINC1

Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register)N/A51, 74

PLUSW1

Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) –value of FSR1 offset by W

N/A

51, 74

FSR1H

—

FSR1L

—

—

—

Indirect Data Memory Address Pointer 1 High Byte

Indirect Data Memory Address Pointer 1 Low Byte

BSR—---- 0000

52, 63Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register)N/A52, 73POSTINC2

Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register)N/A52, 74

POSTDEC2

Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register)N/A52, 74

PREINC2

Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register)N/A52, 74

PLUSW2

Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) –value of FSR2 offset by W

N/A

52, 74

—

FSR2L

—

—

—

—

—

Bank Select Register51, 7351, 73

INDF2

FSR2H

—

---- 0000
xxxx xxxx

Indirect Data Memory Address Pointer 2 High Byte

Indirect Data Memory Address Pointer 2 Low Byte

STATUS

—

—

TMR0H

Timer0 Register High Byte

TMR0L

Timer0 Register Low Byte

T0CON

TMR0ON

Legend:Note 1:
2:
3:
4:
5:
6:
7:

T08BIT

—

T0CS

N

T0SE

OV

PSA

Z

T0PS2

DC

T0PS1

C

T0PS0

---- 0000

52, 73xxxx xxxx

52, 73---x xxxx

52, 710000 0000

52, 127xxxx xxxx

52, 1271111 1111

52, 125

x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as ‘0’.
Bit 21 of the TBLPTRU allows access to the device Configuration bits.
The SBOREN bit is only available when BOREN<1:0> = 01; otherwise, the bit reads as ‘0’.
These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
RA6 is configured as a port pin based on various primary oscillator modes. When the port pin is disabled, all of the associated bits read ‘0’.
RE3 is only available as a port pin when the MCLRE Configuration bit is clear; otherwise, the bit reads as ‘0’.
RC5 and RC4 are only available as port pins when the USB module is disabled (UCON<3> = 0).
I2C Slave mode only.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 67

PIC18F2455/2550/4455/4550
TABLE 5-2:
File NameREGISTER FILE SUMMARY (PIC18F2455/2550/4455/4550) (CONTINUED)
Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on
POR, BOR

Details
on page

OSCCON

IDLEN

IRCF2

IRCF1

IRCF0

OSTS

IOFS

SCS1

SCS0

0100 q000

52, 32

HLVDCON

VDIRMAG—IRVST

HLVDENHLVDL3

HLVDL2

HLVDL1

HLVDL00-00 0101

52, 279

WDTCON

—

—

—

—

—

—

—

SWDTEN--- ---052, 298

—

RI

TO

PD

POR

BOR

RCON

IPEN

SBOREN(2)

TMR1HTimer1 Register High Byte

TMR1L

Timer1 Register Low Byte

T1CON

RD16

T1RUN

TMR2

Timer2 Register

PR2

Timer2 Period Register

T2CON

—

T2OUTPS3T1CKPS1T2OUTPS2

T1CKPS0

T2OUTPS1

T1OSCEN

T2OUTPS0T1SYNCTMR2ON

TMR1CS

TMR1ONT2CKPS1T2CKPS0SSPBUFMSSP Receive Buffer/Transmit Register

SSPADDMSSP Address Register in I2C™ Slave mode. MSSP Baud Rate Reload Register in I2C™ Master mode.

0q-1 11q0

52, 44xxxx xxxx

52, 133xxxx xxxx

52, 1330000 0000

52, 1290000 0000

52, 1361111 1111

52, 136-000 0000

52, 135xxxx xxxx

52, 194,202

0000 0000

52, 202

SSPSTAT

SMP

CKE

D/A

P

S

R/W

UA

BF

0000 0000

52, 194,203

SSPCON1

WCOL

SSPOV

SSPEN

CKP

SSPM3

SSPM2

SSPM1

SSPM0

0000 0000

52, 195,204

SSPCON2GCEN

ACKSTATACKDT/ADMSK5(7)ACKEN/ADMSK4(7)RCEN/
ADMSK3(7)PEN/
ADMSK2(7)RSEN/
ADMSK1(7)SEN0000 0000

52, 205

ADRESHA/D Result Register High Byte

xxxx xxxx

52, 268

ADRESLA/D Result Register Low Byte

xxxx xxxx

52, 268

ADCON0

—

—

CHS3

CHS2

CHS1

CHS0

GO/DONE

ADON--00 0000

52, 259

ADCON1

—

—

VCFG1

VCFG0

PCFG3

PCFG2

PCFG1

PCFG0

--00 0qqq

52, 260

ADFM

—

ACQT2

ACQT1

ACQT0

ADCS2

ADCS1

ADCS0

ADCON2
CCPR1H

Capture/Compare/PWM Register 1 High Byte

CCPR1L

Capture/Compare/PWM Register 1 Low Byte

CCP1CON

P1M1(3)

P1M0(3)

DC1B1

DC1B0

CCP1M3

CCP1M2

CCP1M1

CCP1M00-00 0000

52, 261xxxx xxxx

53, 142xxxx xxxx

53, 1420000 0000

53, 141,
149

CCPR2H

Capture/Compare/PWM Register 2 High Byte

xxxx xxxx

53, 142

CCPR2L

Capture/Compare/PWM Register 2 Low Byte

xxxx xxxx

53, 142

CCP2CON

—

—

DC2B1

DC2B0

CCP2M3

CCP2M2CCP2M1CCP2M0--00 0000

53, 141

BAUDCONABDOVF

RCIDL

RXDTP

TXCKP

BRG16

—

WUE

ABDEN

0100 0-00

53, 240

ECCP1DEL

PRSEN

PDC6(3)PDC5(3)

PDC4(3)

PDC3(3)

PDC2(3)

PDC1(3)

PDC0(3)0000 0000

53, 158

ECCP1AS

ECCPASE

ECCPAS2

ECCPAS1

ECCPAS0PSSAC1PSSAC0PSSBD1(3)PSSBD0(3)0000 0000

53, 159

CVRCON

CVREN

CVROE

CVRR

CVRSS

CVR3

CVR2

CVR1

CVR0

0000 0000

53, 275

C2OUT

C1OUT

C2INV

C1INV

CIS

CM2

CM1

CM0

0000 0111

53, 269

TMR3H

CMCON

Timer3 Register High Byte

xxxx xxxx

53, 139

TMR3L

Timer3 Register Low Byte

xxxx xxxx

53, 139

T3CON

RD16

SPBRGH

T3CCP2T3CKPS1T3CKPS0

T3CCP1T3SYNCTMR3CS

TMR3ONEUSART Baud Rate Generator Register High Byte

0000 0000

53, 1370000 0000

53, 24153, 241SPBRG

EUSART Baud Rate Generator Register Low Byte

0000 0000

RCREG

EUSART Receive Register

0000 0000

53, 250TXREG

EUSART Transmit Register

0000 0000

53, 247

TXSTA

CSRC

TX9

TXEN

SYNC

SENDB

BRGH

TRMT

TX9D

0000 0010

53, 238

RCSTA

SPEN

RX9

SREN

CREN

ADDEN

FERR

OERR

RX9D

0000 000x

53, 239

Legend:Note 1:
2:
3:
4:
5:
6:
7:

x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as ‘0’.
Bit 21 of the TBLPTRU allows access to the device Configuration bits.
The SBOREN bit is only available when BOREN<1:0> = 01; otherwise, the bit reads as ‘0’.
These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
RA6 is configured as a port pin based on various primary oscillator modes. When the port pin is disabled, all of the associated bits read ‘0’.
RE3 is only available as a port pin when the MCLRE Configuration bit is clear; otherwise, the bit reads as ‘0’.
RC5 and RC4 are only available as port pins when the USB module is disabled (UCON<3> = 0).
I2C Slave mode only.

DS39632D-page 68

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
TABLE 5-2:
File NameREGISTER FILE SUMMARY (PIC18F2455/2550/4455/4550) (CONTINUED)
Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on
POR, BOR

Details
on page

EEADR

EEPROM Address Register

0000 0000

53, 89

EEDATAEEPROM Data Register

0000 0000

53, 89EECON2

EEPROM Control Register 2 (not a physical register)

0000 0000

53, 80EECON1

EEPGD

CFGS

—

FREE

WRERR

WREN

WR

RD

xx-0 x000

53, 81IPR2OSCFIP

CMIP

USBIP

EEIP

BCLIP

HLVDIP

TMR3IP

CCP2IP

1111 1111

54, 107

PIR2

OSCFIF

CMIF

USBIF

EEIF

BCLIF

HLVDIF

TMR3IF

CCP2IF

0000 0000

54, 103

PIE2

OSCFIE

CMIE

USBIE

EEIE

BCLIE

HLVDIETMR3IECCP2IE

0000 0000

54, 105IPR1

SPPIP(3)

ADIP

RCIP

TXIP

SSPIP

CCP1IP

TMR2IP

TMR1IP

1111 1111

54, 106

PIR1

SPPIF(3)

ADIF

RCIF

TXIF

SSPIF

CCP1IF

TMR2IF

TMR1IF

0000 0000

54, 102PIE1

SPPIE(3)

ADIE

RCIE

TXIE

SSPIE

CCP1IETMR2IETMR1IE

0000 0000

54, 104

OSCTUNE

INTSRC

—

—

TUN4

TUN3

TUN2

TUN1

TUN0

0--0 0000

54, 28

TRISE(3)

—

—

—

—

—

TRISE2

TRISE1

TRISE0---- -111

54, 124

TRISD(3)

TRISD7

TRISD6

TRISD5

TRISD4

TRISD3

TRISD2

TRISD1

TRISD01111 1111

54, 122

TRISC

TRISC7

TRISC6———

TRISC2

TRISC1

TRISC011-- -111

54, 119TRISB

TRISB7TRISB6TRISB5TRISB4

TRISB3

TRISB2

TRISB1TRISB01111 1111

54, 116TRISA—TRISA6(4)TRISA5TRISA4TRISA3

TRISA2TRISA1TRISA0-111 1111

54, 113

LATE(3)

—

—

—

—

—

LATE2

LATE1

LATE0

---- -xxx

54, 124

LATD(3)

LATD7

LATD6

LATD5

LATD4

LATD3

LATD2

LATD1

LATD0

xxxx xxxx

54, 122

LATC

LATC7

LATC6

—

—

—

LATC2

LATC1

LATC0

xx-- -xxx

54, 119

LATB

LATB7

LATB6

LATB5

LATB4

LATB3

LATB2

LATB1

LATB0

xxxx xxxx

54, 116LATA—

LATA6(4)

LATA5

LATA4

LATA3

LATA2

LATA1

LATA0

-xxx xxxx

54, 113PORTE

RDPU(3)———

RE3(5)

RE2(3)

RE1(3)

RE0(3)

0--- x000

54, 123

PORTD(3)

RD7

RD6

RD5

RD4

RD3

RD2

RD1

RD0

xxxx xxxx

54, 122

PORTC

RC7

RC6

RC5(6)

RC4(6)

—

RC2

RC1

RC0

xxxx -xxx

54, 119

PORTB

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

xxxx xxxx

54, 116PORTA—

RA6(4)

RA5

RA4

RA3

RA2

RA1

RA0

-x0x 0000

54, 113

UEP15

—

—

—

EPHSHKEPCONDISEPOUTEN

EPINENEPSTALL---0 0000

55, 169

UEP14

—

—

—

EPHSHKEPCONDISEPOUTEN

EPINENEPSTALL---0 0000

55, 169

UEP13

—

—

—

EPHSHKEPCONDISEPOUTEN

EPINENEPSTALL---0 0000

55, 169

UEP12

—

—

—

EPHSHKEPCONDISEPOUTEN

EPINENEPSTALL---0 0000

55, 169

UEP11

—

—

—

EPHSHKEPCONDISEPOUTEN

EPINENEPSTALL---0 0000

55, 169

UEP10

—

—

—

EPHSHKEPCONDISEPOUTEN

EPINENEPSTALL---0 0000

55, 169

UEP9

—

—

—

EPHSHKEPCONDISEPOUTEN

EPINENEPSTALL---0 0000

55, 169

UEP8

—

—

—

EPHSHKEPCONDISEPOUTEN

EPINENEPSTALL---0 0000

55, 169

UEP7

—

—

—

EPHSHKEPCONDISEPOUTEN

EPINENEPSTALL---0 0000

55, 169

UEP6

—

—

—

EPHSHKEPCONDISEPOUTEN

EPINENEPSTALL---0 0000

55, 169

UEP5

—

—

—

EPHSHKEPCONDISEPOUTEN

EPINENEPSTALL---0 0000

55, 169

UEP4

—

—

—

EPHSHKEPCONDISEPOUTEN

EPINENEPSTALL---0 0000

55, 169

UEP3

—

—

—

EPHSHKEPCONDISEPOUTEN

EPINENEPSTALL---0 0000

55, 169

UEP2

—

—

—

EPHSHKEPCONDISEPOUTEN

EPINENEPSTALL---0 0000

55, 169

UEP1

—

—

—

EPHSHKEPCONDISEPOUTEN

EPINENEPSTALL---0 0000

55, 169

UEP0

—

—

—

EPHSHKEPCONDISEPOUTEN

EPINENEPSTALL---0 0000

55, 169

Legend:Note 1:
2:
3:
4:
5:
6:
7:

x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as ‘0’.
Bit 21 of the TBLPTRU allows access to the device Configuration bits.
The SBOREN bit is only available when BOREN<1:0> = 01; otherwise, the bit reads as ‘0’.
These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
RA6 is configured as a port pin based on various primary oscillator modes. When the port pin is disabled, all of the associated bits read ‘0’.
RE3 is only available as a port pin when the MCLRE Configuration bit is clear; otherwise, the bit reads as ‘0’.
RC5 and RC4 are only available as port pins when the USB module is disabled (UCON<3> = 0).
I2C Slave mode only.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 69

PIC18F2455/2550/4455/4550
TABLE 5-2:
File NameREGISTER FILE SUMMARY (PIC18F2455/2550/4455/4550) (CONTINUED)
Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on
POR, BOR

Details
on page

UCFG

UTEYE

UOEMON—UPUENUTRDIS

FSEN

PPB1

PPB0

00-0 0000

55, 166

UADDR

—

ADDR6

ADDR5

ADDR4

ADDR3

ADDR2

ADDR1

ADDR0

-000 0000

55, 170UCON—PPBRSTSE0

PKTDISUSBEN

RESUMESUSPND—-0x0 000-

55, 164

USTAT

—

ENDP3

ENDP2

ENDP1

ENDP0

DIR

PPBI

—

-xxx xxx-

55, 168

UEIE

BTSEE

—

—

BTOEE

DFN8EE

CRC16EE

CRC5EEPIDEE

0--0 0000

55, 182

UEIR

BTSEF

—

—

BTOEF

DFN8EF

CRC16EF

CRC5EF

PIDEF

0--0 0000

55, 181

UIE

—

SOFIE

STALLIE

IDLEIETRNIEACTVIEUERRIEURSTIE-000 0000

55, 180

UIR

—

SOFIF

STALLIFIDLEIFTRNIF

ACTVIF

UERRIFURSTIF-000 0000

55, 178

UFRMH

—

—

—

—

—

FRM10

FRM9

FRM8

---- -xxx

55, 170

UFRML

FRM7

FRM6

FRM5

FRM4

FRM3

FRM2

FRM1

FRM0

xxxx xxxx

55, 170

SPPCON(3)

—

—

—

—

—

—

SPPOWN

SPPEN---- --00

55, 187

SPPEPS(3)

RDSPP

WRSPP

—

SPPBUSY

ADDR3

ADDR2

ADDR1

ADDR0

00-0 0000

55, 191

SPPCFG(3)CLKCFG1

CLKCFG0CSEN

CLK1EN

WS3

WS2

WS1

WS0

0000 0000

55, 188

SPPDATA(3)

DATA7

DATA6

DATA5

DATA4

DATA3

DATA2

DATA1

DATA0

0000 0000

55, 192

Legend:Note 1:
2:
3:
4:
5:
6:
7:

x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as ‘0’.
Bit 21 of the TBLPTRU allows access to the device Configuration bits.
The SBOREN bit is only available when BOREN<1:0> = 01; otherwise, the bit reads as ‘0’.
These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
RA6 is configured as a port pin based on various primary oscillator modes. When the port pin is disabled, all of the associated bits read ‘0’.
RE3 is only available as a port pin when the MCLRE Configuration bit is clear; otherwise, the bit reads as ‘0’.
RC5 and RC4 are only available as port pins when the USB module is disabled (UCON<3> = 0).
I2C Slave mode only.

DS39632D-page 70

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
5.3.6

STATUS REGISTERThe STATUS register, shown in Register 5-2, contains
the arithmetic status of the ALU. As with any other SFR,
it can be the operand for any instruction.
If the STATUS register is the destination for an instruction that affects the Z, DC, C, OV or N bits, the resultsof the instruction are not written; instead, the STATUS
register is updated according to the instruction performed. Therefore, the result of an instruction with the
STATUS register as its destination may be different
than intended. As an example, CLRF STATUS will set
the Z bit and leave the remaining Status bits
unchanged (‘000u u1uu’).

REGISTER 5-2:

It is recommended that only BCF, BSF, SWAPF, MOVFF
and MOVWF instructions are used to alter the STATUS
register because these instructions do not affect the Z,
C, DC, OV or N bits in the STATUS register.
For other instructions that do not affect Status bits, see
the instruction set summaries in Table 26-2 andTable 26-3.
Note:

The C and DC bits operate as the Borrowand Digit Borrow bits, respectively, in
subtraction.

STATUS REGISTER

U-0

U-0

U-0

R/W-x

R/W-x

R/W-x

R/W-x

R/W-x

—

—

—

N

OV

Z

DC(1)

C(2)

bit 7

bit 0

Legend:R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’-n = Value at POR‘1’ = Bit is set‘0’ = Bit is clearedx = Bit is unknown

bit 7-5

Unimplemented: Read as ‘0’

bit 4

N: Negative bit
This bit is used for signed arithmetic (2’s complement). It indicates whether the result was negative(ALU MSB = 1).
1 = Result was negative
0 = Result was positive

bit 3

OV: Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the 7-bit magnitude
which causes the sign bit (bit 7 of the result) to change state.
1 = Overflow occurred for signed arithmetic (in this arithmetic operation)
0 = No overflow occurredbit 2

Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero

bit 1

DC: Digit Carry/Borrow bit(1)For ADDWF, ADDLW, SUBLW and SUBWF instructions:
1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result

bit 0

C: Carry/Borrow bit(2)For ADDWF, ADDLW, SUBLW and SUBWF instructions:
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred

Note 1:
2:

For Borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second
operand. For rotate (RRF, RLF) instructions, this bit is loaded with either bit 4 or bit 3 of the source register.
For Borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second
operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of thesource register.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 71

PIC18F2455/2550/4455/4550
5.4

Data Addressing Modes

Note:

The execution of some instructions in thecore PIC18 instruction set are changed
when the PIC18 extended instruction
set is enabled. See Section 5.6 “DataMemory and the Extended Instruction
Set” for more information.

While the program memory can be addressed in only
one way – through the program counter – informationin the data memory space can be addressed in several
ways. For most instructions, the addressing mode isfixed. Other instructions may use up to three modes,
depending on which operands are used and whether or
not the extended instruction set is enabled.
The addressing modes are:• Inherent• Literal• Direct• Indirect
An additional addressing mode, Indexed Literal Offset,
is available when the extended instruction set isenabled (XINST Configuration bit = 1). Its operation is
discussed in greater detail in Section 5.6.1 “Indexed
Addressing with Literal Offset”.

5.4.1

INHERENT AND LITERALADDRESSING

Many PIC18 control instructions do not need anyargument at all; they either perform an operation that
globally affects the device or they operate implicitly on
one register. This addressing mode is known as
Inherent Addressing. Examples include SLEEP, RESET
and DAW.
Other instructions work in a similar way but require an
additional explicit argument in the opcode. This is
known as Literal Addressing mode because theyrequire some literal value as an argument. Examples
include ADDLW and MOVLW, which respectively, add ormove a literal value to the W register. Other examples
include CALL and GOTO, which include a 20-bit
program memory address.

5.4.2

Purpose Register File”) or a location in the AccessBank (Section 5.3.3 “Access Bank”) as the data
source for the instruction.
The Access RAM bit ‘a’ determines how the address isinterpreted. When ‘a’ is ‘1’, the contents of the BSR(Section 5.3.2 “Bank Select Register (BSR)”) areused with the address to determine the complete 12-bit
address of the register. When ‘a’ is ‘0’, the address isinterpreted as being a register in the Access Bank.
Addressing that uses the Access RAM is sometimes
also known as Direct Forced Addressing mode.
A few instructions, such as MOVFF, include the entire
12-bit address (either source or destination) in theiropcodes. In these cases, the BSR is ignored entirely.
The destination of the operation’s results is determinedby the destination bit ‘d’. When ‘d’ is ‘1’, the results are
stored back in the source register, overwriting its original contents. When ‘d’ is ‘0’, the results are stored in
the W register. Instructions without the ‘d’ argument
have a destination that is implicit in the instruction; theirdestination is either the target register being operated
on or the W register.

5.4.3

Indirect Addressing allows the user to access a locationin data memory without giving a fixed address in the
instruction. This is done by using File Select Registers(FSRs) as pointers to the locations to be read or written
to. Since the FSRs are themselves located in RAM asSpecial Function Registers, they can also be directly
manipulated under program control. This makes FSRs
very useful in implementing data structures, such astables and arrays in data memory.
The registers for Indirect Addressing are also
implemented with Indirect File Operands (INDFs) that
permit automatic manipulation of the pointer value with
auto-incrementing, auto-decrementing or offsettingwith another value. This allows for efficient code, using
loops, such as the example of clearing an entire RAM
bank in Example 5-5.

EXAMPLE 5-5:

DIRECT ADDRESSING

Direct Addressing mode specifies all or part of thesource and/or destination address of the operation
within the opcode itself. The options are specified by
the arguments accompanying the instruction.
In the core PIC18 instruction set, bit-oriented andbyte-oriented instructions use some version of Direct
Addressing by default. All of these instructions include
some 8-bit literal address as their Least Significant
Byte. This address specifies either a register address in
one of the banks of data RAM (Section 5.3.4 “General

DS39632D-page 72

INDIRECT ADDRESSING

NEXT

LFSR
CLRF

BTFSS
BRA
CONTINUE

Preliminary

HOW TO CLEAR RAM(BANK 1) USING
INDIRECT ADDRESSING
FSR0, 100h ;POSTINC0; Clear INDF
; register then; inc pointer
FSR0H, 1; All done with
; Bank1?
NEXT; NO, clear next
; YES, continue© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
5.4.3.1

FSR Registers and the
INDF Operandmapped in the SFR space but are not physically implemented. Reading or writing to a particular INDF register
actually accesses its corresponding FSR register pair.
A read from INDF1, for example, reads the data at theaddress indicated by FSR1H:FSR1L. Instructions that
use the INDF registers as operands actually use thecontents of their corresponding FSR as a pointer to the
instruction’s target. The INDF operand is just a
convenient way of using the pointer.

At the core of Indirect Addressing are three sets ofregisters: FSR0, FSR1 and FSR2. Each represents apair of 8-bit registers: FSRnH and FSRnL. The four
upper bits of the FSRnH register are not used, so each
FSR pair holds a 12-bit value. This represents a valuethat can address the entire range of the data memory
in a linear fashion. The FSR register pairs, then, serveas pointers to data memory locations.

Because Indirect Addressing uses a full 12-bit address,
data RAM banking is not necessary. Thus, the current
contents of the BSR and the Access RAM bit have noeffect on determining the target address.

Indirect Addressing is accomplished with a set ofIndirect File Operands, INDF0 through INDF2. Thesecan be thought of as “virtual” registers; they are

FIGURE 5-7:

INDIRECT ADDRESSING
000h

Using an instruction with one of theindirect addressing registers as theoperand....

Bank 0ADDWF, INDF1, 1
100hBank 1200h
Bank 2...uses the 12-bit address stored in
the FSR pair associated with that
register....

300h

FSR1H:FSR1L
7

0x x x x 1 1 1 0

70

1 1 0 0 1 1 0 0

Bank 3through
Bank 13...to determine the data memory
location to be used in that operation.
E00h

In this case, the FSR1 pair contains
ECCh. This means the contents oflocation ECCh will be added to thatof the W register and stored back in
ECCh.

Bank 14F00h
Bank 15
FFFh

Data Memory© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 73

PIC18F2455/2550/4455/4550
5.4.3.2

FSR Registers and POSTINC,
POSTDEC, PREINC and PLUSW

In addition to the INDF operand, each FSR register pairalso has four additional indirect operands. Like INDF,
these are “virtual” registers that cannot be indirectly
read or written to. Accessing these registers actuallyaccesses the associated FSR register pair, but also
performs a specific action on it stored value. They are:
• POSTDEC: accesses the FSR value, thenautomatically decrements it by ‘1’ afterwards• POSTINC: accesses the FSR value, thenautomatically increments it by ‘1’ afterwards• PREINC: increments the FSR value by ‘1’, thenuses it in the operation• PLUSW: adds the signed value of the W register(range of -127 to 128) to that of the FSR and uses
the new value in the operation.
In this context, accessing an INDF register uses thevalue in the FSR registers without changing them. Similarly, accessing a PLUSW register gives the FSR value
offset by that in the W register; neither value is actuallychanged in the operation. Accessing the other virtual
registers changes the value of the FSR registers.
Operations on the FSRs with POSTDEC, POSTINC
and PREINC affect the entire register pair; that is,rollovers of the FSRnL register, from FFh to 00h, carryover to the FSRnH register. On the other hand, resultsof these operations do not change the value of any
flags in the STATUS register (e.g., Z, N, OV, etc.).

5.4.3.3

Operations by FSRs on FSRs

Indirect Addressing operations that target other FSRs
or virtual registers represent special cases. For example, using an FSR to point to one of the virtual registers
will not result in successful operations. As a specificcase, assume that FSR0H:FSR0L contains FE7h, theaddress of INDF1. Attempts to read the value of INDF1,
using INDF0 as an operand, will return 00h. Attempts
to write to INDF1, using INDF0 as the operand, will
result in a NOP.
On the other hand, using the virtual registers to write toan FSR pair may not occur as planned. In these cases,
the value will be written to the FSR pair but without any
incrementing or decrementing. Thus, writing to INDF2
or POSTDEC2 will write the same value to the
FSR2H:FSR2L.
Since the FSRs are physical registers mapped in the
SFR space, they can be manipulated through all direct
operations. Users should proceed cautiously whenworking on these registers, particularly if their codeuses Indirect Addressing.
Similarly, operations by Indirect Addressing are generally permitted on all other SFRs. Users should exercise
the appropriate caution that they do not inadvertently
change settings that might affect the operation of thedevice.

The PLUSW register can be used to implement a formof Indexed Addressing in the data memory space. By
manipulating the value in the W register, users canreach addresses that are fixed offsets from pointeraddresses. In some applications, this can be used to
implement some powerful program control structure,such as software stacks, inside of data memory.

DS39632D-page 74

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
5.5

Program Memory and theExtended Instruction Set

When using the extended instruction set, thisaddressing mode requires the following:

The operation of program memory is unaffected by theuse of the extended instruction set.
Enabling the extended instruction set adds eight
additional two-word commands to the existing
PIC18 instruction set: ADDFSR, ADDULNK, CALLW,
MOVSF, MOVSS, PUSHL, SUBFSR and SUBULNK. These
instructions are executed as described in
Section 5.2.4 “Two-Word Instructions”.

5.6

Data Memory and the Extended
Instruction Set

Enabling the PIC18 extended instruction set (XINST
Configuration bit = 1) significantly changes certain
aspects of data memory and its addressing.
Specifically, the use of the Access Bank for many of thecore PIC18 instructions is different. This is due to theintroduction of a new addressing mode for the data
memory space. This mode also alters the behavior ofIndirect Addressing using FSR2 and its associatedoperands.
What does not change is just as important. The size ofthe data memory space is unchanged, as well as its
linear addressing. The SFR map remains the same.
Core PIC18 instructions can still operate in both Direct
and Indirect Addressing mode; inherent and literal
instructions do not change at all. Indirect Addressing
with FSR0 and FSR1 also remains unchanged.

5.6.1

INDEXED ADDRESSING WITH
LITERAL OFFSET

Enabling the PIC18 extended instruction set changes
the behavior of Indirect Addressing using the FSR2
register pair and its associated file operands. Under theproper conditions, instructions that use the AccessBank – that is, most bit-oriented and byte-oriented
instructions – can invoke a form of Indexed Addressing
using an offset specified in the instruction. This special
addressing mode is known as Indexed Addressing with
Literal Offset or Indexed Literal Offset mode.

© 2007 Microchip Technology Inc.

• The use of the Access Bank is forced (‘a’ = 0);
and• The file address argument is less than or equal
to 5Fh.
Under these conditions, the file address of the instruction is not interpreted as the lower byte of an address(used with the BSR in Direct Addressing), or as an 8-bit
address in the Access Bank. Instead, the value isinterpreted as an offset value to an Address Pointerspecified by FSR2. The offset and the contents of
FSR2 are added to obtain the target address of theoperation.

5.6.2

INSTRUCTIONS AFFECTED BY
INDEXED LITERAL OFFSET MODE

Any of the core PIC18 instructions that can use Direct
Addressing are potentially affected by the Indexed
Literal Offset Addressing mode. This includes all
byte-oriented and bit-oriented instructions, or almost
one-half of the standard PIC18 instruction set. Instructions that only use Inherent or Literal Addressing
modes are unaffected.
Additionally, byte-oriented and bit-oriented instructions
are not affected if they use the Access Bank (Access
RAM bit is ‘1’) or include a file address of 60h or above.
Instructions meeting these criteria will continue to
execute as before. A comparison of the different
possible addressing modes when the extended
instruction set is enabled in shown in Figure 5-8.
Those who desire to use byte-oriented or bit-oriented
instructions in the Indexed Literal Offset mode shouldnote the changes to assembler syntax for this mode.
This is described in more detail in Section 26.2.1“Extended Instruction Syntax”.

Preliminary

DS39632D-page 75

PIC18F2455/2550/4455/4550
FIGURE 5-8:

COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND
BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED)

EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff)

When a = 0 and f ≥ 60h:
The instruction executes in
Direct Forced mode. ‘f’ is interpreted as a location in the
Access RAM between 060h
and 0FFh. This is the same as
the SFRs or locations F60h to
0FFh (Bank 15) of data
memory.

000h

Locations below 60h are notavailable in this addressing
mode.

F00h

060h
080h

Bank 0100h
00hBank 1through
Bank 1460h
Valid range
for ‘f’FFhAccess RAM

Bank 15
F60h
SFRs
FFFh
Data Memory

When a = 0 and f ≤ 5Fh:
The instruction executes inIndexed Literal Offset mode. ‘f’is interpreted as an offset to theaddress value in FSR2. The
two are added together toobtain the address of the target
register for the instruction. The
address can be anywhere in
the data memory space.
Note that in this mode, thecorrect syntax is now:
ADDWF [k], dwhere ‘k’ is the same as ‘f’.

000hBank 0080h
100h

001001da ffffffff
Bank 1through
Bank 14
FSR2H

FSR2L

F00h
Bank 15
F60h
SFRs
FFFh
Data Memory

When a = 1 (all values of f):
The instruction executes in
Direct mode (also known as
Direct Long mode). ‘f’ is interpreted as a location in one of
the 16 banks of the data
memory space. The bank isdesignated by the Bank SelectRegister (BSR). The address
can be in any implemented
bank in the data memory
space.

BSR
00000000000hBank 0080h
100h
Bank 1through
Bank 14001001da ffffffff

F00h
Bank 15
F60h
SFRs
FFFh
Data Memory

DS39632D-page 76

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
5.6.3

MAPPING THE ACCESS BANK IN
INDEXED LITERAL OFFSET MODE

The use of Indexed Literal Offset Addressing mode
effectively changes how the lower portion of Access
RAM (00h to 5Fh) is mapped. Rather than containing
just the contents of the bottom half of Bank 0, this mode
maps the contents from Bank 0 and a user-defined“window” that can be located anywhere in the data
memory space. The value of FSR2 establishes thelower boundary of the addresses mapped into thewindow, while the upper boundary is defined by FSR2
plus 95 (5Fh). Addresses in the Access RAM above
5Fh are mapped as previously described (seeSection 5.3.3 “Access Bank”). An example of AccessBank remapping in this addressing mode is shown in
Figure 5-9.

FIGURE 5-9:

Remapping of the Access Bank applies only to operations using the Indexed Literal Offset mode. Operations
that use the BSR (Access RAM bit is ‘1’) will continue
to use Direct Addressing as before. Any indirect orindexed operation that explicitly uses any of the indirect
file operands (including FSR2) will continue to operate
as standard Indirect Addressing. Any instruction thatuses the Access Bank, but includes a register addressof greater than 05Fh, will use Direct Addressing andthe normal Access Bank map.

5.6.4

BSR IN INDEXED LITERALOFFSET MODE

Although the Access Bank is remapped when theextended instruction set is enabled, the operation of the
BSR remains unchanged. Direct Addressing, using the
BSR to select the data memory bank, operates in thesame manner as previously described.

REMAPPING THE ACCESS BANK WITH INDEXED LITERALOFFSET ADDRESSING

Example Situation:

ADDWF f, d, a000h

FSR2H:FSR2L = 120h
Locations in the region
from the FSR2 Pointer(120h) to the pointer plus
05Fh (17Fh) are mapped
to the bottom of theAccess RAM (000h-05Fh).

Bank 0
100h
120h
17Fh

00h

Bank 1

Bank 1 “Window”

200h

5Fh
60h

Special Function Registers at F60h through FFFh
are mapped to 60h
through FFh as usual.
Bank 0 addresses below
5Fh are not available inthis mode. They can still
be addressed by using the
BSR.

Window

Bank 2through
Bank 14

SFRs

FFh

Access Bank
F00h
Bank 15
F60h
SFRs
FFFh

Data Memory© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 77

PIC18F2455/2550/4455/4550
NOTES:DS39632D-page 78

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
6.0

FLASH PROGRAM MEMORY

6.1

Table Reads and Table Writes

The Flash program memory is readable, writable anderasable, during normal operation over the entire VDD
range.

In order to read and write program memory, there are
two operations that allow the processor to move bytes
between the program memory space and the data RAM:A read from program memory is executed on one byte
at a time. A write to program memory is executed onblocks of 32 bytes at a time. Program memory iserased in blocks of 64 bytes at a time. A Bulk Erase
operation may not be issued from user code.

• Table Read (TBLRD)• Table Write (TBLWT)

Writing or erasing program memory will cease
instruction fetches until the operation is complete. The
program memory cannot be accessed during the writeor erase, therefore, code cannot execute. An internal
programming timer terminates program memory writes
and erases.
A value written to program memory does not need to bea valid instruction. Executing a program memory
location that forms an invalid instruction results in a
NOP.

The program memory space is 16 bits wide, while thedata RAM space is 8 bits wide. Table reads and table
writes move data between these two memory spaces
through an 8-bit register (TABLAT).
Table read operations retrieve data from program
memory and place it into the data RAM space.
Figure 6-1 shows the operation of a table read with
program memory and data RAM.
Table write operations store data from the data memory
space into holding registers in program memory. The
procedure to write the contents of the holding registers
into program memory is detailed in Section 6.5 “Writing
to Flash Program Memory”. Figure 6-2 shows theoperation of a table write with program memory and data
RAM.
Table operations work with byte entities. A table blockcontaining data, rather than program instructions, is not
required to be word-aligned. Therefore, a table block canstart and end at any byte address. If a table write is being
used to write executable code into program memory,
program instructions will need to be word-aligned.

FIGURE 6-1:

TABLE READ OPERATION
Instruction: TBLRD*

Program Memory

Table Pointer(1)TBLPTRU

TBLPTRH

Table Latch (8-bit)
TBLPTRLTABLAT

Program Memory(TBLPTR)

Note 1:

Table Pointer register points to a byte in program memory.

© 2007 Microchip Technology Inc.

Preliminary

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FIGURE 6-2:

TABLE WRITE OPERATION
Instruction: TBLWT*

Program Memory
Holding Registers
Table Pointer(1)TBLPTRU

TBLPTRH

Table Latch (8-bit)
TBLPTRLTABLAT

Program Memory(TBLPTR)

Note 1: Table Pointer actually points to one of 32 holding registers, the address of which is determined by
TBLPTRL<4:0>. The process for physically writing data to the program memory array is discussed in
Section 6.5 “Writing to Flash Program Memory”.

6.2

Control Registers

Several control registers are used in conjunction with
the TBLRD and TBLWT instructions. These include the:• EECON1 register• EECON2 register• TABLAT register• TBLPTR registers

6.2.1

The FREE bit, when set, will allow a program memory
erase operation. When FREE is set, the erase
operation is initiated on the next WR command. When
FREE is clear, only writes are enabled.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit isset in hardware when the WREN bit is set and cleared
when the internal programming timer expires and thewrite operation is complete.

EECON1 AND EECON2 REGISTERS

The EECON1 register (Register 6-1) is the control
register for memory accesses. The EECON2 register is
not a physical register; it is used exclusively in thememory write and erase sequences. Reading
EECON2 will read all ‘0’s.
The EEPGD control bit determines if the access will be
a program or data EEPROM memory access. When
clear, any subsequent operations will operate on thedata EEPROM memory. When set, any subsequent
operations will operate on the program memory.

Note:

The WR control bit initiates write operations. The bit
cannot be cleared, only set, in software; it is cleared in
hardware at the completion of the write operation.
Note:

The CFGS control bit determines if the access will beto the Configuration/Calibration registers or to program
memory/data EEPROM memory. When set,
subsequent operations will operate on Configuration
registers regardless of EEPGD (see Section 25.0
“Special Features of the CPU”). When clear, memory
selection access is determined by EEPGD.

DS39632D-page 80

During normal operation, the WRERR isread as ‘1’. This can indicate that a write
operation was prematurely terminated bya Reset or a write operation was
attempted improperly.

Preliminary

The EEIF interrupt flag bit (PIR2<4>) is set
when the write is complete. It must be
cleared in software.

© 2007 Microchip Technology Inc.

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REGISTER 6-1:

EECON1: DATA EEPROM CONTROL REGISTER 1

R/W-x

R/W-x

U-0

R/W-0

R/W-x

R/W-0

R/S-0

R/S-0

EEPGD

CFGS

—

FREE

WRERR(1)

WREN

WR

RD

bit 7

bit 0

Legend:S = Settable bit

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’-n = Value at POR‘1’ = Bit is set‘0’ = Bit is clearedx = Bit is unknown

bit 7

EEPGD: Flash Program or Data EEPROM Memory Select bit
1 = Access Flash program memory
0 = Access data EEPROM memory

bit 6

CFGS: Flash Program/Data EEPROM or Configuration Select bit
1 = Access Configuration registers
0 = Access Flash program or data EEPROM memory

bit 5

Unimplemented: Read as ‘0’

bit 4

FREE: Flash Row Erase Enable bit
1 = Erase the program memory row addressed by TBLPTR on the next WR command (cleared bycompletion of erase operation)
0 = Perform write-only

bit 3

WRERR: Flash Program/Data EEPROM Error Flag bit(1)1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal
operation or an improper write attempt)
0 = The write operation completed

bit 2

WREN: Flash Program/Data EEPROM Write Enable bit
1 = Allows write cycles to Flash program/data EEPROM
0 = Inhibits write cycles to Flash program/data EEPROM

bit 1

WR: Write Control bit
1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle(The operation is self-timed and the bit is cleared by hardware once write is complete.
The WR bit can only be set (not cleared) in software.)
0 = Write cycle to the EEPROM is complete

bit 0

RD: Read Control bit
1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can only
be set (not cleared) in software. RD bit cannot be set when EEPGD = 1 or CFGS = 1.)
0 = Does not initiate an EEPROM read

Note 1:

When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error
condition.

© 2007 Microchip Technology Inc.

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6.2.2

TABLE LATCH REGISTER (TABLAT)

6.2.4

The Table Latch (TABLAT) is an 8-bit register mapped
into the SFR space. The Table Latch register is used tohold 8-bit data during data transfers between program
memory and data RAM.

6.2.3

TBLPTR is used in reads, writes and erases of theFlash program memory.
When a TBLRD is executed, all 22 bits of the TBLPTR
determine which byte is read from program memory
into TABLAT.

TABLE POINTER REGISTER(TBLPTR)

When a TBLWT is executed, the five LSbs of the Table
Pointer register (TBLPTR<4:0>) determine which of the
32 program memory holding registers is written to.
When the timed write to program memory begins (via
the WR bit), the 16 MSbs of the TBLPTR(TBLPTR<21:6>) determine which program memory
block of 32 bytes is written to. For more detail, see
Section 6.5 “Writing to Flash Program Memory”.

The Table Pointer (TBLPTR) register addresses a byte
within the program memory. The TBLPTR is comprisedof three SFR registers: Table Pointer Upper Byte, Table
Pointer High Byte and Table Pointer Low Byte
(TBLPTRU:TBLPTRH:TBLPTRL). These three registers join to form a 22-bit wide pointer. The low-order
21 bits allow the device to address up to 2 Mbytes ofprogram memory space. The 22nd bit allows access tothe device ID, the user ID and the Configuration bits.

When an erase of program memory is executed, the
16 MSbs of the Table Pointer register (TBLPTR<21:6>)
point to the 64-byte block that will be erased. The Least
Significant bits (TBLPTR<5:0>) are ignored.

The Table Pointer, TBLPTR, is used by the TBLRD and
TBLWT instructions. These instructions can update the
TBLPTR in one of four ways based on the table operation. These operations are shown in Table 6-1. These
operations on the TBLPTR only affect the low-order
21 bits.

TABLE 6-1:

TABLE POINTER BOUNDARIES

Figure 6-3 describes the relevant boundaries of the
TBLPTR based on Flash program memory operations.

TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS

ExampleOperation on Table Pointer

TBLRD*
TBLWT*

TBLPTR is not modified

TBLRD*+
TBLWT*+

TBLPTR is incremented after the read/write

TBLRD*TBLWT*-TBLPTR is decremented after the read/write

TBLRD+*
TBLWT+*

TBLPTR is incremented before the read/write

FIGURE 6-3:
21

TABLE POINTER BOUNDARIES BASED ON OPERATION
TBLPTRU

16

15

TBLPTRH

8

7

TBLPTRL

0TABLE ERASETBLPTR<21:6>
TABLE WRITE – TBLPTR<21:5>
TABLE READ – TBLPTR<21:0>

DS39632D-page 82

Preliminary© 2007 Microchip Technology Inc.

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6.3

Reading the Flash Program
MemoryThe TBLRD instruction is used to retrieve data fromprogram memory and places it into data RAM. Table
reads from program memory are performed one byte ata time.

FIGURE 6-4:

TBLPTR points to a byte address in program space.
Executing TBLRD places the byte pointed to into
TABLAT. In addition, TBLPTR can be modified
automatically for the next table read operation.
The internal program memory is typically organized bywords. The Least Significant bit of the address selects
between the high and low bytes of the word. Figure 6-4
shows the interface between the internal program
memory and the TABLAT.

READS FROM FLASH PROGRAM MEMORY

Program Memory(Even Byte Address)(Odd Byte Address)

TBLPTR = xxxxx1

Instruction Register(IR)

EXAMPLE 6-1:

FETCH

TBLRD

TBLPTR = xxxxx0

TABLAT
Read Register

READING A FLASH PROGRAM MEMORY WORD

MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF

CODE_ADDR_UPPERTBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL; Load TBLPTR with the base; address of the word

READ_WORD
TBLRD*+MOVF
MOVWF
TBLRD*+MOVF
MOVF

TABLAT, W
WORD_EVENTABLAT, W
WORD_ODD© 2007 Microchip Technology Inc.

; read into TABLAT and increment; get data
; read into TABLAT and increment; get data

Preliminary

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6.4

Erasing Flash Program Memory

The minimum erase block is 32 words or 64 bytes. Only
through the use of an external programmer, or through
ICSP control, can larger blocks of program memory be
Bulk Erased. Word Erase in the Flash array is notsupported.
When initiating an erase sequence from the microcontroller itself, a block of 64 bytes of program memory
is erased. The Most Significant 16 bits of the
TBLPTR<21:6> point to the block being erased.
TBLPTR<5:0> are ignored.

6.4.1

The sequence of events for erasing a block of internal
program memory is:
1.
2.

The EECON1 register commands the erase operation.
The EEPGD bit must be set to point to the Flashprogram memory. The WREN bit must be set to enable
write operations. The FREE bit is set to select an erase
operation.

3.
4.
5.
6.

For protection, the write initiate sequence for EECON2
must be used.

7.

A long write is necessary for erasing the internal Flash.
Instruction execution is halted while in a long write
cycle. The long write will be terminated by the internal
programming timer.

EXAMPLE 6-2:

FLASH PROGRAM MEMORYERASE SEQUENCE

8.

Load Table Pointer register with address of row
being erased.
Set the EECON1 register for the erase operation:• set EEPGD bit to point to program memory;• clear the CFGS bit to access program memory;• set WREN bit to enable writes;• set FREE bit to enable the erase.
Disable interrupts.
Write 55h to EECON2.
Write 0AAh to EECON2.
Set the WR bit. This will begin the Row Erase
cycle.
The CPU will stall for duration of the erase(about 2 ms using internal timer).
Re-enable interrupts.

ERASING A FLASH PROGRAM MEMORY ROW
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF

CODE_ADDR_UPPERTBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL; load TBLPTR with the base; address of the memory block

BSF
BCF
BSF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF

EECON1, EEPGDEECON1, CFGSEECON1, WREN
EECON1, FREE
INTCON, GIE
55h
EECON20AAh
EECON2
EECON1, WR
INTCON, GIE; point to Flash program memory; access Flash program memory; enable write to memory; enable Row Erase operation; disable interrupts

ERASE_ROW

RequiredSequence

DS39632D-page 84; write 55h; write 0AAh
; start erase (CPU stall); re-enable interrupts

Preliminary© 2007 Microchip Technology Inc.

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6.5

Writing to Flash Program Memory

The minimum programming block is 16 words or
32 bytes. Word or byte programming is not supported.

The long write is necessary for programming theinternal Flash. Instruction execution is halted while in along write cycle. The long write will be terminated by
the internal programming timer.

Table writes are used internally to load the holding
registers needed to program the Flash memory. Thereare 32 holding registers used by the table writes for
programming.

The EEPROM on-chip timer controls the write time.
The write/erase voltages are generated by an on-chipcharge pump, rated to operate over the voltage rangeof the device.

Since the Table Latch (TABLAT) is only a single byte, theTBLWT instruction may need to be executed 32 times foreach programming operation. All of the table write operations will essentially be short writes because only theholding registers are written. At the end of updating the
32 holding registers, the EECON1 register must be
written to in order to start the programming operation
with a long write.

FIGURE 6-5:

Note:

The default value of the holding registers on
device Resets and after write operations isFFh. A write of FFh to a holding register
does not modify that byte. This means that
individual bytes of program memory may be
modified, provided that the change does not
attempt to change any bit from a ‘0’ to a ‘1’.
When modifying individual bytes, it is notnecessary to load all 32 holding registers
before executing a write operation.

TABLE WRITES TO FLASH PROGRAM MEMORYTABLAT
Write Register

8

8
TBLPTR = xxxxx0

8

TBLPTR = xxxxx1

Holding Register

TBLPTR = xxxxx2

Holding Register

8
TBLPTR = xxxx1F

Holding Register

Holding Register

Program Memory

6.5.1

FLASH PROGRAM MEMORY WRITESEQUENCE

The sequence of events for programming an internal
program memory location should be:
1.
2.
3.
4.
5.
6.
7.

Read 64 bytes into RAM.
Update data values in RAM as necessary.
Load Table Pointer register with address being
erased.
Execute the Row Erase procedure.
Load Table Pointer register with address of first
byte being written.
Write 32 bytes into the holding registers with
auto-increment.
Set the EECON1 register for the write operation:• set EEPGD bit to point to program memory;• clear the CFGS bit to access program memory;• set WREN to enable byte writes.

© 2007 Microchip Technology Inc.

8. Disable interrupts.
9. Write 55h to EECON2.
10. Write 0AAh to EECON2.
11. Set the WR bit. This will begin the write cycle.
12. The CPU will stall for duration of the write (about
2 ms using internal timer).
13. Re-enable interrupts.
14. Repeat steps 6 through 14 once more to write
64 bytes.
15. Verify the memory (table read).
This procedure will require about 8 ms to update one
row of 64 bytes of memory. An example of the required
code is given in Example 6-3.
Note:

Preliminary

Before setting the WR bit, the Table
Pointer address needs to be within theintended address range of the 32 bytes in
the holding register.

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EXAMPLE 6-3:

WRITING TO FLASH PROGRAM MEMORY
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF

D'64’
COUNTERBUFFER_ADDR_HIGH
FSR0H
BUFFER_ADDR_LOW
FSR0L
CODE_ADDR_UPPERTBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRLTBLRD*+MOVF
MOVWF
DECFSZBRA

TABLAT, W
POSTINC0
COUNTER
READ_BLOCK

MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF

DATA_ADDR_HIGH
FSR0H
DATA_ADDR_LOW
FSR0L
NEW_DATA_LOW
POSTINC0
NEW_DATA_HIGH
INDF0

MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BCF
BSF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
TBLRD*MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF

CODE_ADDR_UPPERTBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRLEECON1, EEPGDEECON1, CFGSEECON1, WREN
EECON1, FREE
INTCON, GIE
55h
EECON20AAh
EECON2
EECON1, WR
INTCON, GIE; number of bytes in erase block; point to buffer; Load TBLPTR with the base; address of the memory block

READ_BLOCK; read into TABLAT, and inc; get data
; store data
; done?
; repeat

MODIFY_WORD; point to buffer; update buffer word

ERASE_BLOCK

RequiredSequence

BUFFER_ADDR_HIGH
FSR0H
BUFFER_ADDR_LOW
FSR0L
D’2’
COUNTER1; load TBLPTR with the base; address of the memory block; point to Flash program memory; access Flash program memory; enable write to memory; enable Row Erase operation; disable interrupts; write 55h; write 0AAh
; start erase (CPU stall); re-enable interrupts; dummy read decrement; point to buffer

WRITE_BUFFER_BACK
MOVLW
MOVWF
WRITE_BYTE_TO_HREGS
MOVF
MOVWF
TBLWT+*DECFSZ
BRA

DS39632D-page 86

D’32’
COUNTER; number of bytes in holding register

POSTINC0, W
TABLAT; get low byte of buffer data
; present data to table latch; write data, perform a short write; to internal TBLWT holding register.
; loop until buffers are full

COUNTERWRITE_WORD_TO_HREGS

Preliminary© 2007 Microchip Technology Inc.

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EXAMPLE 6-3:

WRITING TO FLASH PROGRAM MEMORY (CONTINUED)

PROGRAM_MEMORY
BSF
BCF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
DECFSZ
BRA
BSF
BCF

RequiredSequence

6.5.2

EECON1, EEPGDEECON1, CFGSEECON1, WREN
INTCON, GIE
55h
EECON20AAh
EECON2
EECON1, WR
COUNTER1WRITE_BUFFER_BACKINTCON, GIE
EECON1, WREN

UNEXPECTED TERMINATION OF
WRITE OPERATION

If a write is terminated by an unplanned event, such as
loss of power or an unexpected Reset, the memory
location just programmed should be verified and reprogrammed if needed. If the write operation is interrupted
by a MCLR Reset or a WDT Time-out Reset during
normal operation, the user can check the WRERR bit
and rewrite the location(s) as needed.

TABLE 6-2:

; write 55h; write 0AAh
; start program (CPU stall); re-enable interrupts; disable write to memory

6.5.4

WRITE VERIFY

Depending on the application, good programming
practice may dictate that the value written to thememory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.

6.5.3; point to Flash program memory; access Flash program memory; enable write to memory; disable interrupts

PROTECTION AGAINST SPURIOUS
WRITESTo protect against spurious writes to Flash program
memory, the write initiate sequence must also be
followed. See Section 25.0 “Special Features of theCPU” for more detail.

6.6

Flash Program Operation During
Code Protection

See Section 25.5 “Program Verification and CodeProtection” for details on code protection of Flashprogram memory.

REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

TBLPTRU——

bit 21(1) Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)

Reset
Valueson page
51

TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)

51

TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>)

51

TABLAT

Program Memory Table Latch

INTCON

GIE/GIEH PEIE/GIEL TMR0IE

51

EECON2

EEPROM Control Register 2 (not a physical register)

EECON1

EEPGD

CFGS

—

FREE

INT0IERBIE

TMR0IF

INT0IF

RBIF

51

WRERR

WREN

WR

RD

53

53

IPR2

OSCFIP

CMIP

USBIP

EEIP

BCLIP

HLVDIP

TMR3IP

CCP2IP54

PIR2

OSCFIF

CMIF

USBIF

EEIF

BCLIF

HLVDIF

TMR3IF

CCP2IF54

PIE2

OSCFIE

CMIE

USBIE

EEIE

BCLIE

HLVDIETMR3IECCP2IE

54

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.
Note 1: Bit 21 of the TBLPTRU allows access to the device Configuration bits.

© 2007 Microchip Technology Inc.

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NOTES:DS39632D-page 88

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7.0

DATA EEPROM MEMORY

The data EEPROM is a nonvolatile memory array,separate from the data RAM and program memory, thatis used for long-term storage of program data. It is notdirectly mapped in either the register file or program
memory space, but is indirectly addressed through theSpecial Function Registers (SFRs). The EEPROM isreadable and writable during normal operation over theentire VDD range.
Four SFRs are used to read and write to the data
EEPROM as well as the program memory. They are:
• EECON1• EECON2• EEDATA• EEADR
The data EEPROM allows byte read and write. Wheninterfacing to the data memory block, EEDATA holds
the 8-bit data for read/write and the EEADR registerholds the address of the EEPROM location being
accessed.
The EEPROM data memory is rated for high erase/write
cycle endurance. A byte write automatically erases thelocation and writes the new data (erase-before-write).
The write time is controlled by an on-chip timer; it willvary with voltage and temperature as well as from chip
to chip. Please refer to parameter D122 (Table 28-1 in
Section 28.0 “Electrical Characteristics”) for exact
limits.

7.1

EECON1 and EECON2 Registers

Access to the data EEPROM is controlled by two
registers: EECON1 and EECON2. These are the sameregisters which control access to the program memory
and are used in a similar manner for the data
EEPROM.

Control bit, CFGS, determines if the access will be to
the Configuration registers or to program memory/data
EEPROM memory. When set, subsequent operations
access Configuration registers. When CFGS is clear,
the EEPGD bit selects either program Flash or data
EEPROM memory.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit isset in hardware when the WREN bit is set and cleared
when the internal programming timer expires and thewrite operation is complete.
Note:

During normal operation, the WRERR isread as ‘1’. This can indicate that a write
operation was prematurely terminated bya Reset or a write operation was
attempted improperly.

The WR control bit initiates write operations. The bit
cannot be cleared, only set, in software; it is cleared in
hardware at the completion of the write operation.
Note:

The EEIF interrupt flag bit (PIR2<4>) is set
when the write is complete. It must be
cleared in software.

Control bits, RD and WR, start read and erase/write
operations, respectively. These bits are set by firmware
and cleared by hardware at the completion of theoperation.
The RD bit cannot be set when accessing program
memory (EEPGD = 1). Program memory is read using
table read instructions. See Section 6.1 “Table Reads
and Table Writes” regarding table reads.
The EECON2 register is not a physical register. It is
used exclusively in the memory write and erase
sequences. Reading EECON2 will read all ‘0’s.

The EECON1 register (Register 7-1) is the control
register for data and program memory access. Control
bit, EEPGD, determines if the access will be to programor data EEPROM memory. When clear, operations willaccess the data EEPROM memory. When set, program
memory is accessed.

© 2007 Microchip Technology Inc.

Preliminary

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REGISTER 7-1:
R/W-x

EECON1: DATA EEPROM CONTROL REGISTER 1
R/W-x

EEPGD

CFGS

U-0
—

R/W-0
FREE

R/W-x
(1)

WRERR

R/W-0

R/S-0

R/S-0

WREN

WR

RD

bit 7

bit 0

Legend:S = Settable bit

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’-n = Value at POR‘1’ = Bit is set‘0’ = Bit is clearedx = Bit is unknown

bit 7

EEPGD: Flash Program or Data EEPROM Memory Select bit
1 = Access Flash program memory
0 = Access data EEPROM memory

bit 6

CFGS: Flash Program/Data EEPROM or Configuration Select bit
1 = Access Configuration registers
0 = Access Flash program or data EEPROM memory

bit 5

Unimplemented: Read as ‘0’

bit 4

FREE: Flash Row Erase Enable bit
1 = Erase the program memory row addressed by TBLPTR on the next WR command (cleared bycompletion of erase operation)
0 = Perform write-only

bit 3

WRERR: Flash Program/Data EEPROM Error Flag bit(1)1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal
operation or an improper write attempt)
0 = The write operation completed

bit 2

WREN: Flash Program/Data EEPROM Write Enable bit
1 = Allows write cycles to Flash program/data EEPROM
0 = Inhibits write cycles to Flash program/data EEPROM

bit 1

WR: Write Control bit
1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle(The operation is self-timed and the bit is cleared by hardware once write is complete.
The WR bit can only be set (not cleared) in software.)
0 = Write cycle to the EEPROM is complete

bit 0

RD: Read Control bit
1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can only
be set (not cleared) in software. RD bit cannot be set when EEPGD = 1 or CFGS = 1.)
0 = Does not initiate an EEPROM read

Note 1:

When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error
condition.

DS39632D-page 90

Preliminary© 2007 Microchip Technology Inc.

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7.2

Reading the Data EEPROM
MemoryTo read a data memory location, the user must write theaddress to the EEADR register, clear the EEPGD
control bit (EECON1<7>) and then set control bit, RD(EECON1<0>). The data is available on the very next
instruction cycle; therefore, the EEDATA register canbe read by the next instruction. EEDATA will hold thisvalue until another read operation or until it is written toby the user (during a write operation).
The basic process is shown in Example 7-1.

7.3

Writing to the Data EEPROM
MemoryTo write an EEPROM data location, the address mustfirst be written to the EEADR register and the data
written to the EEDATA register. The sequence inExample 7-2 must be followed to initiate the write cycle.
The write will not begin if this sequence is not exactly
followed (write 55h to EECON2, write 0AAh to
EECON2, then set WR bit) for each byte. It is strongly
recommended that interrupts be disabled during thiscode segment.

EXAMPLE 7-1:
MOVLW
MOVWF
BCF
BCF
BSF
MOVF

After a write sequence has been initiated, EECON1,
EEADR and EEDATA cannot be modified. The WR bit
will be inhibited from being set unless the WREN bit isset. The WREN bit must be set on a previous instruction. Both WR and WREN cannot be set with the same
instruction.
At the completion of the write cycle, the WR bit iscleared in hardware and the EEPROM Interrupt Flag bit(EEIF) is set. The user may either enable this interrupt,
or poll this bit. EEIF must be cleared by software.

7.4

Write Verify

Depending on the application, good programming
practice may dictate that the value written to thememory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.

DATA EEPROM READ
DATA_EE_ADDR
EEADR
EECON1, EEPGDEECON1, CFGSEECON1, RD
EEDATA, W

EXAMPLE 7-2:

RequiredSequence

Additionally, the WREN bit in EECON1 must be set toenable writes. This mechanism prevents accidental
writes to data EEPROM due to unexpected code execution (i.e., runaway programs). The WREN bit should
be kept clear at all times except when updating the
EEPROM. The WREN bit is not cleared by hardware.

;; Lower bits of Data Memory Address to read
; Point to DATA memory; Access EEPROM; EEPROM Read
; W = EEDATADATA EEPROM WRITE
MOVLW
MOVWF
MOVLW
MOVWF
BCF
BCF
BSF

DATA_EE_ADDR
EEADR
DATA_EE_DATA
EEDATAEECON1, EPGDEECON1, CFGSEECON1, WREN;
; Lower bits of Data Memory Address to write;; Data Memory Value to write; Point to DATA memory; Access EEPROM; Enable writes

BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF

INTCON, GIE
55h
EECON20AAh
EECON2
EECON1, WR
INTCON, GIE; Disable Interrupts;; Write 55h;; Write 0AAh
; Set WR bit to begin write; Enable Interrupts

BCF

EECON1, WREN

; User code execution; Disable writes on write complete (EEIF set)

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 91

PIC18F2455/2550/4455/4550
7.5

Operation During Code-Protect

7.7

Data EEPROM memory has its own code-protect bits in
Configuration Words. External read and write
operations are disabled if code protection is enabled.
The microcontroller itself can both read and write to theinternal data EEPROM regardless of the state of thecode-protect Configuration bit. Refer to Section 25.0
“Special Features of the CPU” for additional
information.

7.6

Protection Against Spurious Write

There are conditions when the device may not want towrite to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms havebeen implemented. On power-up, the WREN bit iscleared. In addition, writes to the EEPROM are blocked
during the Power-up Timer period (TPWRT,
parameter 33, Table 28-12).

Using the Data EEPROM

The data EEPROM is a high endurance, byte addressable array that has been optimized for the storage of
frequently changing information (e.g., program
variables or other data that are updated often).
Frequently changing values will typically be updated
more often than specification D124 or D124A. If this is
not the case, an array refresh must be performed. For
this reason, variables that change infrequently (such as
constants, IDs, calibration, etc.) should be stored inFlash program memory.
A simple data EEPROM refresh routine is shown in
Example 7-3.
Note:

If data EEPROM is only used to store
constants and/or data that changes rarely,
an array refresh is likely not required. See
specification D124 or D124A.

The write initiate sequence and the WREN bit together
help prevent an accidental write during brown-out,
power glitch or software malfunction.

EXAMPLE 7-3:

DATA EEPROM REFRESH ROUTINE
CLRF
BCF
BCF
BCF
BSF

EEADR
EECON1, CFGSEECON1, EEPGDINTCON, GIE
EECON1, WREN

BSF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BTFSC
BRA
INCFSZBRAEECON1, RD
55h
EECON20AAh
EECON2
EECON1, WR
EECON1, WR$-2
EEADR, F
LOOP

BCF
BSF

EECON1, WREN
INTCON, GIE

Loop

RequiredSequence

DS39632D-page 92; Start at address 0; Set for memory; Set for Data EEPROM; Disable interrupts; Enable writes; Loop to refresh array; Read current address;; Write 55h;; Write 0AAh
; Set WR bit to begin write; Wait for write to complete; Increment address; Not zero, do it again; Disable writes; Enable interrupts

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
TABLE 7-1:

REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset
Valueson page

INTCON

GIE/GIEH

PEIE/GIEL

TMR0IEINT0IERBIE

TMR0IF

INT0IF

RBIF

51

EEADR

EEPROM Address Register

53

EEDATAEEPROM Data Register

53

EECON2

EEPROM Control Register 2 (not a physical register)

53

EECON1

EEPGD

CFGS

—

FREE

WRERR

WREN

WR

RD

53

IPR2

OSCFIP

CMIP

USBIP

EEIP

BCLIP

HLVDIP

TMR3IP

CCP2IP54

PIR2

OSCFIF

CMIF

USBIF

EEIF

BCLIF

HLVDIF

TMR3IF

CCP2IF54

PIE2

OSCFIE

CMIE

USBIE

EEIE

BCLIE

HLVDIETMR3IECCP2IE

54

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 93

PIC18F2455/2550/4455/4550
NOTES:DS39632D-page 94

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
8.0

8 x 8 HARDWARE MULTIPLIER

8.1

Introduction

All PIC18 devices include an 8 x 8 hardware multiplieras part of the ALU. The multiplier performs an unsigned
operation and yields a 16-bit result that is stored in the
product register pair, PRODH:PRODL. The multiplier’s
operation does not affect any flags in the STATUS
register.

8 x 8 UNSIGNEDMULTIPLY ROUTINE

MOVF
MULWF

;
; ARG1 * ARG2 ->; PRODH:PRODL

ARG1, W
ARG2

EXAMPLE 8-2:

Making multiplication a hardware operation allows it tobe completed in a single instruction cycle. This has theadvantages of higher computational throughput andreduced code size for multiplication algorithms andallows the PIC18 devices to be used in many applications previously reserved for digital signal processors.
A comparison of various hardware and software
multiply operations, along with the savings in memory
and execution time, is shown in Table 8-1.

8.2

EXAMPLE 8-1:

8 x 8 SIGNED MULTIPLY
ROUTINE

MOVF
MULWF

ARG1, W
ARG2

BTFSC
SUBWF

ARG2, SB
PRODH, F

MOVF
BTFSC
SUBWF

ARG2, W
ARG1, SB
PRODH, F; ARG1 * ARG2 ->; PRODH:PRODL; Test Sign Bit; PRODH = PRODH;- ARG1; Test Sign Bit; PRODH = PRODH;- ARG2

Operation

Example 8-1 shows the instruction sequence for an
8 x 8 unsigned multiplication. Only one instruction isrequired when one of the arguments is already loadedin the WREG register.
Example 8-2 shows the sequence to do an 8 x 8 signed
multiplication. To account for the sign bits of thearguments, each argument’s Most Significant bit (MSb)is tested and the appropriate subtractions are done.

TABLE 8-1:

PERFORMANCE COMPARISON FOR VARIOUS MULTIPLY OPERATIONS

Routine8 x 8 unsigned
8 x 8 signed
16 x 16 unsigned
16 x 16 signed

Multiply Method
Without hardware multiply

Program
Memory(Words)Cycles(Max)@ 40 MHz@ 10 MHz@ 4 MHz1369

6.9 μs27.6 μs

69 μs

Time

Hardware multiply

1

1

100 ns

400 ns1 μs

Without hardware multiply

33

91

9.1 μs36.4 μs

91 μs

Hardware multiply

6

6

600 ns2.4 μs

6 μs

Without hardware multiply

21

242

24.2 μs

96.8 μs

242 μsHardware multiply

28

28

2.8 μs11.2 μs

28 μs

Without hardware multiply

52

254

25.4 μs102.6 μs

254 μsHardware multiply

3540

4.0 μs

16.0 μs

40 μs© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 95

PIC18F2455/2550/4455/4550
Example 8-3 shows the sequence to do a 16 x 16
unsigned multiplication. Equation 8-1 shows thealgorithm that is used. The 32-bit result is stored in four
registers (RES3:RES0).

EQUATION 8-1:

RES3:RES0==

EXAMPLE 8-3:

16 x 16 UNSIGNEDMULTIPLICATIONALGORITHM
ARG1H:ARG1L • ARG2H:ARG2L(ARG1H • ARG2H • 216) +(ARG1H • ARG2L • 28) +(ARG1L • ARG2H • 28) +(ARG1L • ARG2L)

EQUATION 8-2:

RES3:RES0 = ARG1H:ARG1L • ARG2H:ARG2L= (ARG1H • ARG2H • 216) +(ARG1H • ARG2L • 28) +(ARG1L • ARG2H • 28) +(ARG1L • ARG2L) +(-1 • ARG2H<7> • ARG1H:ARG1L • 216) +(-1 • ARG1H<7> • ARG2H:ARG2L • 216)

EXAMPLE 8-4:

16 x 16 UNSIGNEDMULTIPLY ROUTINE

MOVF
MULWF

ARG1L, W
ARG2L

MOVFF
MOVFF

PRODH, RES1PRODL, RES0

MOVF
MULWF

ARG1H, W
ARG2H

MOVFF
MOVFF

PRODH, RES3
PRODL, RES2

MOVF
MULWF

ARG1L, W
ARG2H

MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFCPRODL, W
RES1, FPRODH, W
RES2, F
WREG
RES3, F

MOVF
MULWF

ARG1H, W
ARG2L

MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFCPRODL, W
RES1, FPRODH, W
RES2, F
WREG
RES3, F

; ARG1L * ARG2L->; PRODH:PRODL;;

Example 8-4 shows the sequence to do a 16 x 16
signed multiply. Equation 8-2 shows the algorithm
used. The 32-bit result is stored in four registers(RES3:RES0). To account for the sign bits of thearguments, the MSb for each argument pair is tested
and the appropriate subtractions are done.

DS39632D-page 96

ARG1L, W
ARG2L

MOVFF
MOVFF

PRODH, RES1PRODL, RES0

MOVF
MULWF

ARG1H, W
ARG2H

MOVFF
MOVFF

PRODH, RES3
PRODL, RES2

MOVF
MULWF

ARG1L,W
ARG2H

MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFCPRODL, W
RES1, FPRODH, W
RES2, F
WREG
RES3, F

MOVF
MULWF

ARG1H, W
ARG2L

MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFCPRODL, W
RES1, FPRODH, W
RES2, F
WREG
RES3, F

BTFSS
BRA
MOVF
SUBWF
MOVF
SUBWFB

ARG2H, 7
SIGN_ARG1
ARG1L, W
RES2
ARG1H, W
RES3; ARG2H:ARG2L neg?
; no, check ARG1;;;

ARG1H, 7
CONT_CODE
ARG2L, W
RES2
ARG2H, W
RES3; ARG1H:ARG1L neg?
; no, done;;;

; ARG1L * ARG2L ->; PRODH:PRODL;;; ARG1H * ARG2H ->; PRODH:PRODL;;; ARG1L * ARG2H ->; PRODH:PRODL;; Add cross; products
;
;
;

;

;
;
; ARG1H * ARG2L->; PRODH:PRODL;; Add cross; products
;
;
;

MOVF
MULWF

;

;
; ARG1L * ARG2H->; PRODH:PRODL;; Add cross; products;;;

16 x 16 SIGNEDMULTIPLY ROUTINE;;; ARG1H * ARG2H->; PRODH:PRODL;;

16 x 16 SIGNEDMULTIPLICATIONALGORITHM;; ARG1H * ARG2L ->; PRODH:PRODL;; Add cross; products
;
;
;

;

;
SIGN_ARG1
BTFSS
BRA
MOVF
SUBWF
MOVF
SUBWFB;
CONT_CODE:

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
9.0

INTERRUPTS

The PIC18F2455/2550/4455/4550 devices havemultiple interrupt sources and an interrupt priority
feature that allows each interrupt source to be assigned
a high priority level or a low priority level. The highpriority interrupt vector is at 000008h and the low
priority interrupt vector is at 000018h. High priority
interrupt events will interrupt any low priority interruptsthat may be in progress.
There are ten registers which are used to control
interrupt operation. These registers are:
• RCON• INTCON• INTCON2• INTCON3• PIR1, PIR2
• PIE1, PIE2
• IPR1, IPR2When an interrupt is responded to, the global interrupt
enable bit is cleared to disable further interrupts. If theIPEN bit is cleared, this is the GIE bit. If interrupt priority
levels are used, this will be either the GIEH or GIEL bit.
High priority interrupt sources can interrupt a low
priority interrupt. Low priority interrupts are notprocessed while high priority interrupts are in progress.
The return address is pushed onto the stack and the
PC is loaded with the interrupt vector address(000008h or 000018h). Once in the Interrupt Service
Routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt
flag bits must be cleared in software before re-enabling
interrupts to avoid recursive interrupts.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine and sets the GIE bit (GIEH or GIEL
if priority levels are used) which re-enables interrupts.

It is recommended that the Microchip header files
supplied with MPLAB® IDE be used for the symbolic bit
names in these registers. This allows the assembler/
compiler to automatically take care of the placement ofthese bits within the specified register.

For external interrupt events, such as the INT pins or
the PORTB input change interrupt, the interrupt latency
will be three to four instruction cycles. The exact
latency is the same for one or two-cycle instructions.
Individual interrupt flag bits are set regardless of thestatus of their corresponding enable bit or the GIE bit.
Note:

Each interrupt source has three bits to control its
operation. The functions of these bits are:
• Flag bit to indicate that an interrupt event
occurred• Enable bit that allows program execution tobranch to the interrupt vector address when theflag bit is set• Priority bit to select high priority or low priority

9.1

The interrupt priority feature is enabled by setting theIPEN bit (RCON<7>). When interrupt priority isenabled, there are two bits which enable interrupts
globally. Setting the GIEH bit (INTCON<7>) enables all
interrupts that have the priority bit set (high priority).
Setting the GIEL bit (INTCON<6>) enables all
interrupts that have the priority bit cleared (low priority).
When the interrupt flag, enable bit and appropriate
global interrupt enable bit are set, the interrupt will
vector immediately to address 000008h or 000018h,
depending on the priority bit setting. Individual interrupts can be disabled through their corresponding
enable bits.
When the IPEN bit is cleared (default state), theinterrupt priority feature is disabled and interrupts arecompatible with PIC® mid-range devices. In
Compatibility mode, the interrupt priority bits for eachsource have no effect. INTCON<6> is the PEIE bit
which enables/disables all peripheral interrupt sources.
INTCON<7> is the GIE bit which enables/disables all
interrupt sources. All interrupts branch to address
000008h in Compatibility mode.

© 2007 Microchip Technology Inc.

Do not use the MOVFF instruction to modify
any of the interrupt control registers while
any interrupt is enabled. Doing so may
cause erratic microcontroller behavior.

USB Interrupts

Unlike other peripherals, the USB module is capable ofgenerating a wide range of interrupts for many types of
events. These include several types of normal communication and status events and several module level
error events.
To handle these events, the USB module is equippedwith its own interrupt logic. The logic functions in amanner similar to the microcontroller level interrupt funnel, with each interrupt source having separate flag andenable bits. All events are funneled to a single device
level interrupt, USBIF (PIR2<5>). Unlike the device
level interrupt logic, the individual USB interrupt events
cannot be individually assigned their own priority. Thisis determined at the device level interrupt funnel for all
USB events by the USBIP bit.
For additional details on USB interrupt logic, refer to
Section 17.5 “USB Interrupts”.

Preliminary

DS39632D-page 97

PIC18F2455/2550/4455/4550
FIGURE 9-1:

INTERRUPT LOGIC

TMR0IF
TMR0IETMR0IP
RBIF
RBIE
RBIP
INT0IF
INT0IEInterrupt to CPU
Vector to Location
0008h

INT1IF
INT1IEINT1IP
INT2IF
INT2IEINT2IP

Peripheral Interrupt Flag bit
Peripheral Interrupt Enable bit
Peripheral Interrupt Priority bit

GIE/GIEHTMR1IF
TMR1IETMR1IP
From USB
Interrupt Logic

Wake-up if in Sleep Mode

IPEN
IPEN

USBIF
USBIE
USBIP

PEIE/GIEL
IPEN
Additional Peripheral Interrupts

High Priority Interrupt Generation
Low Priority Interrupt Generation

Peripheral Interrupt Flag bit
Peripheral Interrupt Enable bit
Peripheral Interrupt Priority bit

TMR1IF
TMR1IETMR1IP
From USB
Interrupt Logic

RBIF
RBIE
RBIP

USBIF
USBIE
USBIP

Additional Peripheral Interrupts

DS39632D-page 98

Interrupt to CPU
Vector to Location
0018h

TMR0IF
TMR0IETMR0IP

PEIE/GIEL
GIE/GIEH

INT1IF
INT1IEINT1IP
INT2IF
INT2IEINT2IP

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
9.2

INTCON Registers

Note:

The INTCON registers are readable and writableregisters which contain various enable, priority and flag
bits.

REGISTER 9-1:

Interrupt flag bits are set when an interrupt
condition occurs regardless of the state ofits corresponding enable bit or the global
interrupt enable bit. User software should
ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt.
This feature allows for software polling.

INTCON: INTERRUPT CONTROL REGISTER

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-x

GIE/GIEH

PEIE/GIEL

TMR0IEINT0IERBIE

TMR0IF

INT0IF

RBIF(1)

bit 7

bit 0

Legend:R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’-n = Value at POR‘1’ = Bit is set‘0’ = Bit is clearedx = Bit is unknown

bit 7

GIE/GIEH: Global Interrupt Enable bit
When IPEN = 0:
1 = Enables all unmasked interrupts
0 = Disables all interrupts
When IPEN = 1:
1 = Enables all high priority interrupts
0 = Disables all high priority interrupts

bit 6

PEIE/GIEL: Peripheral Interrupt Enable bit
When IPEN = 0:
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
When IPEN = 1:
1 = Enables all low priority peripheral interrupts
0 = Disables all low priority peripheral interrupts

bit 5

TMR0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 overflow interrupt
0 = Disables the TMR0 overflow interrupt

bit 4

INT0IE: INT0 External Interrupt Enable bit
1 = Enables the INT0 external interrupt
0 = Disables the INT0 external interrupt

bit 3

RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt

bit 2

TMR0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow

bit 1

INT0IF: INT0 External Interrupt Flag bit
1 = The INT0 external interrupt occurred (must be cleared in software)
0 = The INT0 external interrupt did not occur

bit 0

RBIF: RB Port Change Interrupt Flag bit(1)1 = At least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state

Note 1:

A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition andallow the bit to be cleared.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 99

PIC18F2455/2550/4455/4550
REGISTER 9-2:

INTCON2: INTERRUPT CONTROL REGISTER 2

R/W-1

R/W-1

R/W-1

R/W-1

U-0

R/W-1

U-0

R/W-1

RBPU

INTEDG0

INTEDG1

INTEDG2—

TMR0IP

—

RBIP

bit 7

bit 0

Legend:R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’-n = Value at POR‘1’ = Bit is set‘0’ = Bit is cleared

bit 7

RBPU: PORTB Pull-up Enable bit
1 = All PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values

bit 6

INTEDG0: External Interrupt 0 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge

bit 5

INTEDG1: External Interrupt 1 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge

bit 4

INTEDG2: External Interrupt 2 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge

bit 3

Unimplemented: Read as ‘0’

bit 2

TMR0IP: TMR0 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority

bit 1

Unimplemented: Read as ‘0’

bit 0

RBIP: RB Port Change Interrupt Priority bit
1 = High priority
0 = Low priority

Note:

x = Bit is unknown

Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding
enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt. This feature allows for software polling.

DS39632D-page 100

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
REGISTER 9-3:

INTCON3: INTERRUPT CONTROL REGISTER 3

R/W-1

R/W-1

U-0

R/W-0

R/W-0

U-0

R/W-0

R/W-0

INT2IP

INT1IP—

INT2IEINT1IE—INT2IF

INT1IF

bit 7

bit 0

Legend:R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’-n = Value at POR‘1’ = Bit is set‘0’ = Bit is cleared

bit 7

INT2IP: INT2 External Interrupt Priority bit
1 = High priority
0 = Low priority

bit 6

INT1IP: INT1 External Interrupt Priority bit
1 = High priority
0 = Low priority

bit 5

Unimplemented: Read as ‘0’

bit 4

INT2IE: INT2 External Interrupt Enable bit
1 = Enables the INT2 external interrupt
0 = Disables the INT2 external interrupt

bit 3

INT1IE: INT1 External Interrupt Enable bit
1 = Enables the INT1 external interrupt
0 = Disables the INT1 external interrupt

bit 2

Unimplemented: Read as ‘0’

bit 1

INT2IF: INT2 External Interrupt Flag bit
1 = The INT2 external interrupt occurred (must be cleared in software)
0 = The INT2 external interrupt did not occur

bit 0

INT1IF: INT1 External Interrupt Flag bit
1 = The INT1 external interrupt occurred (must be cleared in software)
0 = The INT1 external interrupt did not occur

Note:

x = Bit is unknown

Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding
enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt. This feature allows for software polling.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 101

PIC18F2455/2550/4455/4550
9.3

PIR Registers

The PIR registers contain the individual flag bits for the
peripheral interrupts. Due to the number of peripheral
interrupt sources, there are two Peripheral Interrupt
Request (Flag) registers (PIR1 and PIR2).

REGISTER 9-4:

Note 1: Interrupt flag bits are set when an interrupt
condition occurs regardless of the state ofits corresponding enable bit or the Global
Interrupt Enable bit, GIE (INTCON<7>).
2: User software should ensure the appropriate interrupt flag bits are cleared prior toenabling an interrupt and after servicingthat interrupt.

PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1

R/W-0

R/W-0

R-0

R-0

R/W-0

R/W-0

R/W-0

R/W-0

SPPIF(1)

ADIF

RCIF

TXIF

SSPIF

CCP1IF

TMR2IF

TMR1IF

bit 7

bit 0

Legend:R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’-n = Value at POR‘1’ = Bit is set‘0’ = Bit is clearedx = Bit is unknown

bit 7

SPPIF: Streaming Parallel Port Read/Write Interrupt Flag bit(1)1 = A read or a write operation has taken place (must be cleared in software)
0 = No read or write has occurred

bit 6

ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed (must be cleared in software)
0 = The A/D conversion is not complete

bit 5

RCIF: EUSART Receive Interrupt Flag bit
1 = The EUSART receive buffer, RCREG, is full (cleared when RCREG is read)
0 = The EUSART receive buffer is empty

bit 4

TXIF: EUSART Transmit Interrupt Flag bit
1 = The EUSART transmit buffer, TXREG, is empty (cleared when TXREG is written)
0 = The EUSART transmit buffer is fullbit 3

SSPIF: Master Synchronous Serial Port Interrupt Flag bit
1 = The transmission/reception is complete (must be cleared in software)
0 = Waiting to transmit/receive

bit 2

CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode.

bit 1

TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred

bit 0

TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow

Note 1:This bit is reserved on 28-pin devices; always maintain this bit clear.

DS39632D-page 102

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
REGISTER 9-5:

PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

OSCFIF

CMIF

USBIF

EEIF

BCLIF

HLVDIF

TMR3IF

CCP2IF

bit 7

bit 0

Legend:R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’-n = Value at POR‘1’ = Bit is set‘0’ = Bit is clearedx = Bit is unknown

bit 7

OSCFIF: Oscillator Fail Interrupt Flag bit
1 = System oscillator failed, clock input has changed to INTOSC (must be cleared in software)
0 = System clock operating

bit 6

CMIF: Comparator Interrupt Flag bit
1 = Comparator input has changed (must be cleared in software)
0 = Comparator input has not changed

bit 5

USBIF: USB Interrupt Flag bit
1 = USB has requested an interrupt (must be cleared in software)
0 = No USB interrupt request

bit 4

EEIF: Data EEPROM/Flash Write Operation Interrupt Flag bit
1 = The write operation is complete (must be cleared in software)
0 = The write operation is not complete or has not been started

bit 3

BCLIF: Bus Collision Interrupt Flag bit
1 = A bus collision has occurred (must be cleared in software)
0 = No bus collision occurred

bit 2

HLVDIF: High/Low-Voltage Detect Interrupt Flag bit
1 = A high/low-voltage condition occurred (must be cleared in software)
0 = No high/low-voltage event has occurred

bit 1

TMR3IF: TMR3 Overflow Interrupt Flag bit
1 = TMR3 register overflowed (must be cleared in software)
0 = TMR3 register did not overflow

bit 0

CCP2IF: CCP2 Interrupt Flag bit
Capture mode:
1 = A TMR1 or TMR3 register capture occurred (must be cleared in software)
0 = No TMR1 or TMR3 register capture occurred
Compare mode:
1 = A TMR1 or TMR3 register compare match occurred (must be cleared in software)
0 = No TMR1 or TMR3 register compare match occurred
PWM mode:
Unused in this mode.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 103

PIC18F2455/2550/4455/4550
9.4

PIE Registers

The PIE registers contain the individual enable bits forthe peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt
Enable registers (PIE1 and PIE2). When IPEN = 0, thePEIE bit must be set to enable any of these peripheral
interrupts.

REGISTER 9-6:

PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

SPPIE(1)

ADIE

RCIE

TXIE

SSPIE

CCP1IETMR2IETMR1IE

bit 7

bit 0

Legend:R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’-n = Value at POR‘1’ = Bit is set‘0’ = Bit is cleared

bit 7

SPPIE: Streaming Parallel Port Read/Write Interrupt Enable bit(1)1 = Enables the SPP read/write interrupt
0 = Disables the SPP read/write interrupt

bit 6

ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D interrupt
0 = Disables the A/D interrupt

bit 5

RCIE: EUSART Receive Interrupt Enable bit
1 = Enables the EUSART receive interrupt
0 = Disables the EUSART receive interrupt

bit 4

TXIE: EUSART Transmit Interrupt Enable bit
1 = Enables the EUSART transmit interrupt
0 = Disables the EUSART transmit interrupt

bit 3

SSPIE: Master Synchronous Serial Port Interrupt Enable bit
1 = Enables the MSSP interrupt
0 = Disables the MSSP interrupt

bit 2

CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt

bit 1

TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt

bit 0

TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt

Note 1:x = Bit is unknown

This bit is reserved on 28-pin devices; always maintain this bit clear.

DS39632D-page 104

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
REGISTER 9-7:

PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

OSCFIE

CMIE

USBIE

EEIE

BCLIE

HLVDIETMR3IECCP2IE

bit 7

bit 0

Legend:R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’-n = Value at POR‘1’ = Bit is set‘0’ = Bit is cleared

bit 7

OSCFIE: Oscillator Fail Interrupt Enable bit
1 = Enabled
0 = Disabled

bit 6

CMIE: Comparator Interrupt Enable bit
1 = Enabled
0 = Disabled

bit 5

USBIE: USB Interrupt Enable bit
1 = Enabled
0 = Disabled

bit 4

EEIE: Data EEPROM/Flash Write Operation Interrupt Enable bit
1 = Enabled
0 = Disabled

bit 3

BCLIE: Bus Collision Interrupt Enable bit
1 = Enabled
0 = Disabledbit 2

HLVDIE: High/Low-Voltage Detect Interrupt Enable bit
1 = Enabled
0 = Disabled

bit 1

TMR3IE: TMR3 Overflow Interrupt Enable bit
1 = Enabled
0 = Disabled

bit 0

CCP2IE: CCP2 Interrupt Enable bit
1 = Enabled
0 = Disabled© 2007 Microchip Technology Inc.

Preliminary

x = Bit is unknown

DS39632D-page 105

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9.5

IPR Registers

The IPR registers contain the individual priority bits forthe peripheral interrupts. Due to the number of
peripheral interrupt sources, there are two Peripheral
Interrupt Priority registers (IPR1 and IPR2). Using thepriority bits requires that the Interrupt Priority Enable(IPEN) bit be set.

REGISTER 9-8:

IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1

R/W-1

R/W-1

R/W-1

R/W-1

R/W-1

R/W-1

R/W-1

R/W-1

SPPIP(1)

ADIP

RCIP

TXIP

SSPIP

CCP1IP

TMR2IP

TMR1IP

bit 7

bit 0

Legend:R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’-n = Value at POR‘1’ = Bit is set‘0’ = Bit is cleared

bit 7

SPPIP: Streaming Parallel Port Read/Write Interrupt Priority bit(1)1 = High priority
0 = Low priority

bit 6

ADIP: A/D Converter Interrupt Priority bit
1 = High priority
0 = Low priority

bit 5

RCIP: EUSART Receive Interrupt Priority bit
1 = High priority
0 = Low priority

bit 4

TXIP: EUSART Transmit Interrupt Priority bit

x = Bit is unknown

1 = High priority
0 = Low priority
bit 3

SSPIP: Master Synchronous Serial Port Interrupt Priority bit
1 = High priority
0 = Low priority

bit 2

CCP1IP: CCP1 Interrupt Priority bit
1 = High priority
0 = Low priority

bit 1

TMR2IP: TMR2 to PR2 Match Interrupt Priority bit
1 = High priority
0 = Low priority

bit 0

TMR1IP: TMR1 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority

Note 1:This bit is reserved on 28-pin devices; always maintain this bit clear.

DS39632D-page 106

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
REGISTER 9-9:

IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2

R/W-1

R/W-1

R/W-1

R/W-1

R/W-1

R/W-1

R/W-1

R/W-1

OSCFIP

CMIP

USBIP

EEIP

BCLIP

HLVDIP

TMR3IP

CCP2IP

bit 7

bit 0

Legend:R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’-n = Value at POR‘1’ = Bit is set‘0’ = Bit is cleared

bit 7

OSCFIP: Oscillator Fail Interrupt Priority bit
1 = High priority
0 = Low priority

bit 6

CMIP: Comparator Interrupt Priority bit
1 = High priority
0 = Low priority

bit 5

USBIP: USB Interrupt Priority bit
1 = High priority
0 = Low priority

bit 4

EEIP: Data EEPROM/Flash Write Operation Interrupt Priority bit
1 = High priority
0 = Low priority

bit 3

BCLIP: Bus Collision Interrupt Priority bit
1 = High priority
0 = Low priority

bit 2

HLVDIP: High/Low-Voltage Detect Interrupt Priority bit
1 = High priority
0 = Low priority

bit 1

TMR3IP: TMR3 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority

bit 0

CCP2IP: CCP2 Interrupt Priority bit
1 = High priority
0 = Low priority© 2007 Microchip Technology Inc.

Preliminary

x = Bit is unknown

DS39632D-page 107

PIC18F2455/2550/4455/4550
9.6

RCON Register

The RCON register contains flag bits which are used todetermine the cause of the last Reset or wake-up from
Idle or Sleep modes. RCON also contains the IPEN bit
which enables interrupt priorities.

REGISTER 9-10:

RCON: RESET CONTROL REGISTER

R/W-0

R/W-1(1)

U-0

R/W-1

R-1

R-1

R/W-0(2)

R/W-0

IPEN

SBOREN

—

RI

TO

PD

POR

BOR

bit 7

bit 0

Legend:R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’-n = Value at POR‘1’ = Bit is set‘0’ = Bit is clearedx = Bit is unknown

bit 7

IPEN: Interrupt Priority Enable bit
1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode)

bit 6

SBOREN: BOR Software Enable bit(1)For details of bit operation, see Register 4-1.

bit 5

Unimplemented: Read as ‘0’

bit 4

RI: RESET Instruction Flag bit
For details of bit operation, see Register 4-1.

bit 3

TO: Watchdog Time-out Flag bit
For details of bit operation, see Register 4-1.

bit 2

PD: Power-Down Detection Flag bit
For details of bit operation, see Register 4-1.

bit 1

POR: Power-on Reset Status bit(2)For details of bit operation, see Register 4-1.

bit 0

BOR: Brown-out Reset Status bit
For details of bit operation, see Register 4-1.

Note 1:
2:

If SBOREN is enabled, its Reset state is ‘1’; otherwise, it is ‘0’. See Register 4-1 for additional information.
The actual Reset value of POR is determined by the type of device Reset. See Register 4-1 for additional
information.

DS39632D-page 108

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
9.7

INTn Pin Interrupts

9.8

TMR0 Interrupt

External interrupts on the RB0/AN12/INT0/FLT0/SDI/
SDA, RB1/AN10/INT1/SCK/SCL and RB2/AN8/INT2/
VMO pins are edge-triggered. If the corresponding
INTEDGx bit in the INTCON2 register is set (= 1), theinterrupt is triggered by a rising edge; if the bit is clear,
the trigger is on the falling edge. When a valid edge
appears on the RBx/INTx pin, the corresponding flag
bit, INTxIF, is set. This interrupt can be disabled byclearing the corresponding enable bit, INTxIE. Flag bit,
INTxIF, must be cleared in software in the Interrupt
Service Routine before re-enabling the interrupt.

In 8-bit mode (which is the default), an overflow in the
TMR0 register (FFh → 00h) will set flag bit, TMR0IF. In
16-bit mode, an overflow in the TMR0H:TMR0L register pair (FFFFh → 0000h) will set TMR0IF. The interrupt
can be enabled/disabled by setting/clearing enable bit,
TMR0IE (INTCON<5>). Interrupt priority for Timer0 is
determined by the value contained in the interrupt
priority bit, TMR0IP (INTCON2<2>). See Section 11.0
“Timer0 Module” for further details on the Timer0
module.

All external interrupts (INT0, INT1 and INT2) can wakeup the processor from the power-managed modes if bit,
INTxIE, was set prior to going into the power-managed
modes. If the Global Interrupt Enable bit, GIE, is set, theprocessor will branch to the interrupt vector following
wake-up.

9.9

Interrupt priority for INT1 and INT2 is determined by thevalue contained in the interrupt priority bits, INT1IP(INTCON3<6>) and INT2IP (INTCON3<7>). There is
no priority bit associated with INT0. It is always a highpriority interrupt source.

EXAMPLE 9-1:

PORTB Interrupt-on-Change

An input change on PORTB<7:4> sets flag bit, RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit, RBIE (INTCON<3>).
Interrupt priority for PORTB interrupt-on-change isdetermined by the value contained in the interrupt
priority bit, RBIP (INTCON2<0>).

9.10

Context Saving During Interrupts

During interrupts, the return PC address is saved on
the stack. Additionally, the WREG, STATUS and BSR
registers are saved on the fast return stack. If a fast
return from interrupt is not used (see Section 5.3“Data Memory Organization”), the user may need tosave the WREG, STATUS and BSR registers on entry
to the Interrupt Service Routine. Depending on theuser’s application, other registers may also need to be
saved. Example 9-1 saves and restores the WREG,STATUS and BSR registers during an Interrupt Service
Routine.

SAVING STATUS, WREG AND BSR REGISTERS IN RAM

MOVWF
W_TEMPMOVFF
STATUS, STATUS_TEMP
MOVFF
BSR, BSR_TEMP;; USER ISR CODE;
MOVFF
BSR_TEMP, BSR
MOVF
W_TEMP, W
MOVFF
STATUS_TEMP, STATUS© 2007 Microchip Technology Inc.

; W_TEMP is in virtual bank
; STATUS_TEMP located anywhere; BSR_TMEP located anywhere; Restore BSR; Restore WREG
; Restore STATUS

Preliminary

DS39632D-page 109

PIC18F2455/2550/4455/4550
NOTES:DS39632D-page 110

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
10.0

I/O PORTS

Reading the PORTA register reads the status of thepins; writing to it will write to the port latch.

Depending on the device selected and features
enabled, there are up to five ports available. Some pinsof the I/O ports are multiplexed with an alternate
function from the peripheral features on the device. In
general, when a peripheral is enabled, that pin may not
be used as a general purpose I/O pin.
Each port has three registers for its operation. These
registers are:
• TRIS register (data direction register)• PORT register (reads the levels on the pins of thedevice)• LAT register (output latch)
The Data Latch register (LATA) is useful for readmodify-write operations on the value driven by the I/O
pins.
A simplified model of a generic I/O port, without theinterfaces to other peripherals, is shown in Figure 10-1.

FIGURE 10-1:

GENERIC I/O PORTOPERATION

RD LATData
Bus

RA4 is also multiplexed with the USB module; it serves
as a receiver input from an external USB transceiver.
For details on configuration of the USB module, see
Section 17.2 “USB Status and Control”.
Several PORTA pins are multiplexed with analog inputs,
the analog VREF+ and VREF- inputs and the comparator
voltage reference output. The operation of pins RA5
and RA3:RA0 as A/D converter inputs is selected byclearing/setting the control bits in the ADCON1 register(A/D Control Register 1).

Q
I/O pin(1)CK
Data Latch
D

WR TRISThe RA4 pin is multiplexed with the Timer0 module
clock input to become the RA4/T0CKI pin. The RA6 pin
is multiplexed with the main oscillator pin; it is enabled
as an oscillator or I/O pin by the selection of the main
oscillator in Configuration Register 1H (seeSection 25.1 “Configuration Bits” for details). When
not used as a port pin, RA6 and its associated TRIS
and LAT bits are read as ‘0’.

Note:
D

WR LATor PORT

The Data Latch register (LATA) is also memory
mapped. Read-modify-write operations on the LATA
register read and write the latched output value for
PORTA.

All other PORTA pins have TTL input levels and full
CMOS output drivers.
The TRISA register controls the direction of the RA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.

Q

CK
TRIS Latch

Input
Buffer

EXAMPLE 10-1:
CLRF

RD TRIS

Q

CLRF

D

ENEN
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW

RD PORT
Note 1:

10.1

On a Power-on Reset, RA5 and RA3:RA0
are configured as analog inputs and readas ‘0’. RA4 is configured as a digital input.

I/O pins have diode protection to VDD and VSS.

PORTA, TRISA and LATA Registers
MOVWF

PORTA is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISA. Setting a
TRISA bit (= 1) will make the corresponding PORTA pin
an input (i.e., put the corresponding output driver in ahigh-impedance mode). Clearing a TRISA bit (= 0) will
make the corresponding PORTA pin an output (i.e., put
the contents of the output latch on the selected pin).

© 2007 Microchip Technology Inc.

Preliminary

INITIALIZING PORTA

PORTA; Initialize PORTA by; clearing output; data latches
LATA; Alternate method; to clear output; data latches
0Fh; Configure A/D
ADCON1 ; for digital inputs
07h; Configure comparators
CMCON; for digital input
0CFh; Value used to; initialize data
; direction
TRISA; Set RA<3:0> as inputs; RA<5:4> as outputs

DS39632D-page 111

PIC18F2455/2550/4455/4550
TABLE 10-1:
Pin

PORTA I/O SUMMARY
Function

TRIS
Setting

I/O

RA0

0

OUT

DIG

LATA<0> data output; not affected by analog input.

1

IN

TTL

PORTA<0> data input; disabled when analog input enabled.

AN0

1

IN

ANA

A/D input channel 0 and Comparator C1- input. Default configuration
on POR; does not affect digital output.

RA1

0

OUT

DIG

LATA<1> data output; not affected by analog input.

1

IN

TTL

PORTA<1> data input; reads ‘0’ on POR.

AN1

1

IN

ANA

A/D input channel 1 and Comparator C2- input. Default configuration
on POR; does not affect digital output.

RA2

0

OUT

DIG

LATA<2> data output; not affected by analog input. Disabled when
CVREF output enabled.

1

IN

TTL

PORTA<2> data input. Disabled when analog functions enabled;
disabled when CVREF output enabled.

AN2

1

IN

ANA

A/D input channel 2 and Comparator C2+ input. Default configuration
on POR; not affected by analog output.

VREF-

1

IN

ANA

A/D and comparator voltage reference low input.

CVREF

x

OUT

ANA

Comparator voltage reference output. Enabling this feature disables
digital I/O.

RA3

0

OUT

DIG

LATA<3> data output; not affected by analog input.

RA0/AN0RA1/AN1

RA2/AN2/
VREF-/CVREF

RA3/AN3/
VREF+

1

IN

TTL

PORTA<3> data input; disabled when analog input enabled.

1

IN

ANA

A/D input channel 3 and Comparator C1+ input. Default configuration
on POR.

VREF+

1

IN

ANA

A/D and comparator voltage reference high input.

RA4

0

OUT

DIG

LATA<4> data output; not affected by analog input.

1

IN

ST

PORTA<4> data input; disabled when analog input enabled.

1

IN

ST

Timer0 clock input.

C1OUT

0

OUT

DIG

Comparator 1 output; takes priority over port data.

RCV

x

IN

TTL

External USB transceiver RCV input.

RA5

0

OUT

DIG

LATA<5> data output; not affected by analog input.

T0CKI

RA5/AN4/SS/
HLVDIN/C2OUTLegend:Description

AN3

RA4/T0CKI/C1OUT/RCV

OSC2/CLKO/
RA6

I/O Type

1

IN

TTL

PORTA<5> data input; disabled when analog input enabled.

AN4

1

IN

ANA

A/D input channel 4. Default configuration on POR.

SS

1

IN

TTL

Slave select input for SSP (MSSP module).

HLVDIN

1

IN

ANA

High/Low-Voltage Detect external trip point input.

C2OUT

0

OUT

DIG

Comparator 2 output; takes priority over port data.

OSC2

x

OUT

ANA

Main oscillator feedback output connection (all XT and HS modes).

CLKO

x

OUT

DIG

System cycle clock output (FOSC/4); available in EC, ECPLL and
INTCKO modes.

RA6

0

OUT

DIG

LATA<6> data output. Available only in ECIO, ECPIO and INTIO
modes; otherwise, reads as ‘0’.

1

IN

TTL

PORTA<6> data input. Available only in ECIO, ECPIO and INTIO
modes; otherwise, reads as ‘0’.

OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option)

DS39632D-page 112

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
TABLE 10-2:
Name

SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset
Valueson page

Bit 7

Bit 6

PORTA

—

RA6(1)

RA5

RA4

RA3

RA2

RA1

RA0

54

LATA

—

LATA6(1)

LATA5

LATA4

LATA3

LATA2

LATA1

LATA0

54

TRISA

—

TRISA6(1)TRISA5TRISA4TRISA3

TRISA2TRISA1TRISA054

ADCON1

—

—

VCFG1

VCFG0

PCFG3

PCFG2

PCFG1

PCFG0

52

CMCON

C2OUT

C1OUT

C2INV

C1INV

CIS

CM2

CM1

CM0

53

CVRCON

CVREN

CVROE

CVRR

CVRSS

CVR3

CVR2

CVR1

CVR0

53

UCON

—

PPBRSTSE0

PKTDIS

USBEN

—

55

RESUME SUSPND

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA.
Note 1: RA6 and its associated latch and data direction bits are enabled as I/O pins based on oscillator
configuration; otherwise, they are read as ‘0’.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 113

PIC18F2455/2550/4455/4550
10.2

PORTB, TRISB and LATB
Registers

PORTB is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISB. Setting a
TRISB bit (= 1) will make the corresponding PORTB
pin an input (i.e., put the corresponding output driver ina high-impedance mode). Clearing a TRISB bit (= 0)will make the corresponding PORTB pin an output (i.e.,
put the contents of the output latch on the selected pin).
The Data Latch register (LATB) is also memory
mapped. Read-modify-write operations on the LATB
register read and write the latched output value for
PORTB.
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This isperformed by clearing bit, RBPU (INTCON2<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on a Power-on Reset.
Note:

On a Power-on Reset, RB4:RB0 are
configured as analog inputs by default andread as ‘0’; RB7:RB5 are configured asdigital inputs.
By programming the Configuration bit,
PBADEN (CONFIG3H<1>), RB4:RB0 willalternatively be configured as digital inputs
on POR.

Four of the PORTB pins (RB7:RB4) have an interrupton-change feature. Only pins configured as inputs cancause this interrupt to occur. Any RB7:RB4 pin
configured as an output is excluded from the interrupton-change comparison. The pins are compared withthe old value latched on the last read of PORTB. The“mismatch” outputs of RB7:RB4 are ORed together togenerate the RB Port Change Interrupt with Flag bit,
RBIF (INTCON<0>).

The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-changefeature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
Pins, RB2 and RB3, are multiplexed with the USB
peripheral and serve as the differential signal outputs
for an external USB transceiver (TRIS configuration).
Refer to Section 17.2.2.2 “External Transceiver” foradditional information on configuring the USB module
for operation with an external transceiver.
RB4 is multiplexed with CSSPP, the chip selectfunction for the Streaming Parallel Port (SPP) – TRIS
setting. Details of its operation are discussed in
Section 18.0 “Streaming Parallel Port”.

EXAMPLE 10-2:
CLRF

CLRF

MOVLW
MOVWF

MOVLW

MOVWF

INITIALIZING PORTBPORTB; Initialize PORTB by; clearing output; data latches
LATB; Alternate method; to clear output; data latches
0Eh; Set RB<4:0> as
ADCON1 ; digital I/O pins
; (required if config bit; PBADEN is set)
0CFh
; Value used to; initialize data
; direction
TRISB; Set RB<3:0> as inputs; RB<5:4> as outputs; RB<7:6> as inputs

The interrupt-on-change can be used to wake thedevice from Sleep. The user, in the Interrupt Service
Routine, can clear the interrupt in the following manner:a)b)

Any read or write of PORTB (except with the
MOVFF (ANY), PORTB instruction). This willend the mismatch condition.
Clear flag bit, RBIF.

A mismatch condition will continue to set flag bit, RBIF.
Reading PORTB will end the mismatch condition andallow flag bit, RBIF, to be cleared.

DS39632D-page 114

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
TABLE 10-3:
Pin
RB0/AN12/
INT0/FLT0/
SDI/SDA

RB1/AN10/
INT1/SCK/SCLPORTB I/O SUMMARY
Function

TRIS
Setting

I/O

I/O Type

RB0

0

OUT

DIG

LATB<0> data output; not affected by analog input.

1

IN

TTL

PORTB<0> data input; weak pull-up when RBPU bit is cleared.
Disabled when analog input enabled.(1)

AN12

1

IN

ANA

A/D input channel 12.(1)

INT0

1

IN

ST

External interrupt 0 input.

FLT0

1

IN

ST

Enhanced PWM Fault input (ECCP1 module); enabled in software.

SDI

1

IN

ST

SPI data input (MSSP module).

SDA

1

OUT

DIG

I2C™ data output (MSSP module); takes priority over port data.

1

IN

0

OUT

DIG

LATB<1> data output; not affected by analog input.

1

IN

TTL

PORTB<1> data input; weak pull-up when RBPU bit is cleared.
Disabled when analog input enabled.(1)

AN10

1

IN

ANA

A/D input channel 10.(1)

INT1

1

IN

ST

External interrupt 1 input.

SCK

0

OUT

DIG

SPI clock output (MSSP module); takes priority over port data.

1

IN

ST

SPI clock input (MSSP module).

0

OUT

DIG

I2C clock output (MSSP module); takes priority over port data.

1

IN

I2C/SMB

0

OUT

DIG

LATB<2> data output; not affected by analog input.

1

IN

TTL

PORTB<2> data input; weak pull-up when RBPU bit is cleared.
Disabled when analog input enabled.(1)

AN8

1

IN

ANA

A/D input channel 8.(1)

RB1

SCL
RB2/AN8/
INT2/VMORB2

RB3/AN9/
CCP2/VPO

Legend:Note 1:2:
3:
4:

I2C clock input (MSSP module); input type depends on module setting.

INT2

1

IN

ST

External interrupt 2 input.

0

OUT

DIG

External USB transceiver VMO data output.

RB3

0

OUT

DIG

LATB<3> data output; not affected by analog input.

1

IN

TTL

PORTB<3> data input; weak pull-up when RBPU bit is cleared.
Disabled when analog input enabled.(1)

1

IN

ANA

A/D input channel 9.(1)

0

OUT

DIG

CCP2 Compare and PWM output.

1

IN

ST

CCP2 Capture input.

VPO

0

OUT

DIG

External USB transceiver VPO data output.

RB4

0

OUT

DIG

LATB<4> data output; not affected by analog input.

1

IN

TTL

PORTB<4> data input; weak pull-up when RBPU bit is cleared.
Disabled when analog input enabled.(1)

AN11

1

IN

ANA

A/D input channel 11.(1)Interrupt-on-pin change.

CCP2

RB5/KBI1/PGM

I2C/SMB I2C data input (MSSP module); input type depends on module setting.

VMO

AN9

RB4/AN11/
KBI0/CSSPP

Description

(2)

KBI0

1

IN

TTL

CSSPP(4)

0

OUT

DIG

SPP chip select control output.

RB5

0

OUT

DIG

LATB<5> data output.

1

IN

TTL

PORTB<5> data input; weak pull-up when RBPU bit is cleared.

KBI1

1

IN

TTL

Interrupt-on-pin change.

PGM

x

IN

ST

Single-Supply Programming mode entry (ICSP™). Enabled by LVP
Configuration bit; all other pin functions disabled.

OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
I2C/SMB = I2C/SMBus input buffer, TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or isoverridden for this option)
Configuration on POR is determined by PBADEN Configuration bit. Pins are configured as analog inputs when
PBADEN is set and digital inputs when PBADEN is cleared.
Alternate pin assignment for CCP2 when CCP2MX = 0. Default assignment is RC1.
All other pin functions are disabled when ICSP™ or ICD operation is enabled.
40/44-pin devices only.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 115

PIC18F2455/2550/4455/4550
TABLE 10-3:
Pin
RB6/KBI2/
PGC

RB7/KBI3/
PGD

Legend:Note 1:
2:
3:
4:

PORTB I/O SUMMARY (CONTINUED)
Function

TRIS
Setting

I/O

I/O Type

RB6

0

OUT

DIG

LATB<6> data output.

1

IN

TTL

PORTB<6> data input; weak pull-up when RBPU bit is cleared.

KBI2

1

IN

TTL

Interrupt-on-pin change.

PGC

x

IN

ST

Serial execution (ICSP™) clock input for ICSP and ICD operation.(3)

RB7

0

OUT

DIG

LATB<7> data output.

1

IN

TTL

PORTB<7> data input; weak pull-up when RBPU bit is cleared.

Description

KBI3

1

IN

TTL

Interrupt-on-pin change.

PGD

x

OUT

DIG

Serial execution data output for ICSP and ICD operation.(3)

x

IN

ST

Serial execution data input for ICSP and ICD operation.(3)OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
I2C/SMB = I2C/SMBus input buffer, TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or isoverridden for this option)
Configuration on POR is determined by PBADEN Configuration bit. Pins are configured as analog inputs when
PBADEN is set and digital inputs when PBADEN is cleared.
Alternate pin assignment for CCP2 when CCP2MX = 0. Default assignment is RC1.
All other pin functions are disabled when ICSP™ or ICD operation is enabled.
40/44-pin devices only.

TABLE 10-4:
Name

SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset
Valueson page
54

PORTB

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

LATB

LATB7

LATB6

LATB5

LATB4

LATB3

LATB2

LATB1

LATB0

54

TRISB

TRISB7TRISB6TRISB5TRISB4

TRISB3

TRISB2

TRISB1TRISB054

INTCON

GIE/GIEH PEIE/GIEL

TMR0IEINT0IERBIE

TMR0IF

INT0IF

RBIF

51

INTCON2RBPU

INTEDG0 INTEDG1 INTEDG2—TMR0IP

—

RBIP

51

INTCON3

INT2IP

INT1IP—

INT2IEINT1IE—INT2IF

INT1IF51

ADCON1

—

—

VCFG1

VCFG0

PCFG3

PCFG2

PCFG1

PCFG0

52

SPPCON(1)

—

—

—

—

—

—

SPPOWN

SPPEN

55

CSEN

CLK1EN

WS3

WS2

WS1

WS0

55

SE0

PKTDIS

USBEN

—

55

SPPCFG(1)UCON

CLKCFG1 CLKCFG0—PPBRST

RESUME SUSPND

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTB.
Note 1: These registers are unimplemented on 28-pin devices.

DS39632D-page 116

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
10.3

PORTC, TRISC and LATC
Registers

PORTC is a 7-bit wide, bidirectional port. The corresponding data direction register is TRISC. Setting a
TRISC bit (= 1) will make the corresponding PORTC
pin an input (i.e., put the corresponding output driver ina high-impedance mode). Clearing a TRISC bit (= 0)will make the corresponding PORTC pin an output (i.e.,
put the contents of the output latch on the selected pin).

When enabling peripheral functions on PORTC pinsother than RC4 and RC5, care should be taken in defining the TRIS bits. Some peripherals override the TRIS
bit to make a pin an output, while other peripherals
override the TRIS bit to make a pin an input. The user
should refer to the corresponding peripheral section forthe correct TRIS bit settings.
Note:

In PIC18F2455/2550/4455/4550 devices, the RC3 pin
is not implemented.
The Data Latch register (LATC) is also memory
mapped. Read-modify-write operations on the LATC
register read and write the latched output value for
PORTC.
PORTC is primarily multiplexed with serial communication modules, including the EUSART, MSSP moduleand the USB module (Table 10-5). Except for RC4 andRC5, PORTC uses Schmitt Trigger input buffers.
Pins RC4 and RC5 are multiplexed with the USB
module. Depending on the configuration of the module,
they can serve as the differential data lines for the onchip USB transceiver, or the data inputs from anexternal USB transceiver. Both RC4 and RC5 have
TTL input buffers instead of the Schmitt Trigger buffers
on the other pins.
Unlike other PORTC pins, RC4 and RC5 do not have
TRISC bits associated with them. As digital ports, they
can only function as digital inputs. When configured for
USB operation, the data direction is determined by theconfiguration and status of the USB module at a given
time. If an external transceiver is used, RC4 and RC5
always function as inputs from the transceiver. If the
on-chip transceiver is used, the data direction isdetermined by the operation being performed by themodule at that time.

On a Power-on Reset, these pins, except
RC4 and RC5, are configured as digital
inputs. To use pins RC4 and RC5 as digital inputs, the USB module must be disabled (UCON<3> = 0) and the on-chip
USB transceiver must be disabled(UCFG<3> = 1).

The contents of the TRISC register are affected byperipheral overrides. Reading TRISC always returns
the current contents, even though a peripheral device
may be overriding one or more of the pins.

EXAMPLE 10-3:
CLRF

PORTC

CLRF

LATC

MOVLW

07h

MOVWF

TRISC

INITIALIZING PORTC; Initialize PORTC by; clearing output; data latches; Alternate method; to clear output; data latches; Value used to; initialize data
; direction; RC<5:0> as outputs; RC<7:6> as inputs

When the external transceiver is enabled, RC2 also
serves as the output enable control to the transceiver.
Additional information on configuring USB options isprovided in Section 17.2.2.2 “External Transceiver”.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 117

PIC18F2455/2550/4455/4550
TABLE 10-5:

PORTC I/O SUMMARY

Pin

Function

TRIS
Setting

I/O

I/O Type

RC0/T1OSO/
T13CKI

RC0

0

OUT

DIG

LATC<0> data output.

1

IN

ST

PORTC<0> data input.

x

OUT

ANA

Timer1 oscillator output; enabled when Timer1 oscillator enabled.
Disables digital I/O.

T1OSO
T13CKI

1IN

ST

Timer1/Timer3 counter input.

RC1

0

OUT

DIG

LATC<1> data output.

1

IN

ST

PORTC<1> data input.

T1OSI

x

IN

ANA

Timer1 oscillator input; enabled when Timer1 oscillator enabled.
Disables digital I/O.

CCP2(1)

0

OUT

DIG

CCP2 Compare and PWM output; takes priority over port data.

RC1/T1OSI/
CCP2/UOE

RC2/CCP1/
P1A

RC4/D-/VM

1

IN

ST

CCP2 Capture input.

UOE

0

OUT

DIG

External USB transceiver OE output.

RC2

0

OUT

DIG

LATC<2> data output.

1

IN

ST

PORTC<2> data input.

CCP1

0

OUT

DIG

ECCP1 Compare and PWM output; takes priority over port data.

1

IN

ST

ECCP1 Capture input.

P1A(3)

0

OUT

DIG

ECCP1 Enhanced PWM output, channel A; takes priority over port
data. May be configured for tri-state during Enhanced PWM shutdown
events.

RC4

—(2)

IN

TTL

PORTC<4> data input; disabled when USB module or on-chiptransceiver are enabled.

D-

—(2)

OUT

XCVR

USB bus differential minus line output (internal transceiver).

(2)

IN

XCVR

USB bus differential minus line input (internal transceiver).

VM

—(2)

IN

TTL

External USB transceiver VM input.

RC5

—(2)

IN

TTL

PORTC<5> data input; disabled when USB module or on-chiptransceiver are enabled.

D+

—(2)

OUT

XCVR

USB bus differential plus line output (internal transceiver).

—(2)

IN

XCVR

USB bus differential plus line input (internal transceiver).

VP

—(2)

IN

TTL

External USB transceiver VP input.

RC6

0

OUT

DIG

LATC<6> data output.

1

IN

ST

PORTC<6> data input.

TX

0

OUT

DIG

Asynchronous serial transmit data output (EUSART module); takes
priority over port data. User must configure as output.

CK

0

OUT

DIG

Synchronous serial clock output (EUSART module); takes priority
over port data.

1

IN

ST

Synchronous serial clock input (EUSART module).

—
RC5/D+/VP

RC6/TX/CKLegend:Note 1:
2:
3:

Description

OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input, XCVR = USB transceiver, x = Don’t care (TRIS bit does not affect port direction or is overridden
for this option)
Default pin assignment. Alternate pin assignment is RB3 (when CCP2MX = 0).
RC4 and RC5 do not have corresponding TRISC bits. In Port mode, these pins are input only. USB data direction isdetermined by the USB configuration.
40/44-pin devices only.

DS39632D-page 118

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
TABLE 10-5:
Pin
RC7/RX/DT/
SDO

PORTC I/O SUMMARY (CONTINUED)
Function

TRIS
Setting

I/O

I/O Type

RC7

0

OUT

DIG

LATC<7> data output.

1

IN

ST

PORTC<7> data input.

RX

1

IN

ST

Asynchronous serial receive data input (EUSART module).

DT

1

OUT

DIG

Synchronous serial data output (EUSART module); takes priority over
SPI and port data.

1

IN

ST

Synchronous serial data input (EUSART module). User must
configure as an input.

0

OUT

DIG

SPI data output (MSSP module); takes priority over port data.

SDO
Legend:Note 1:
2:
3:

Description

OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input, XCVR = USB transceiver, x = Don’t care (TRIS bit does not affect port direction or is overridden
for this option)
Default pin assignment. Alternate pin assignment is RB3 (when CCP2MX = 0).
RC4 and RC5 do not have corresponding TRISC bits. In Port mode, these pins are input only. USB data direction isdetermined by the USB configuration.
40/44-pin devices only.

TABLE 10-6:

SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset
Valueson page

PORTC

RC7

RC6

RC5(1)

RC4(1)

—

RC2

RC1

RC0

54

LATC

LATC7

LATC6

—

—

—

LATC2

LATC1

LATC0

54

TRISC

TRISC7

TRISC6———

TRISC2

TRISC1

TRISC0

54

UCON

—

PPBRSTSE0

PKTDIS

USBEN

—

55

Name

RESUME SUSPND

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTC.
Note 1: RC5 and RC4 are only available as port pins when the USB module is disabled (UCON<3> = 0).

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 119

PIC18F2455/2550/4455/4550
10.4
Note:

PORTD, TRISD and LATD
Registers
PORTD is only available on 40/44-pin
devices.

PORTD is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISD. Setting a
TRISD bit (= 1) will make the corresponding PORTD
pin an input (i.e., put the corresponding output driver ina high-impedance mode). Clearing a TRISD bit (= 0)will make the corresponding PORTD pin an output (i.e.,
put the contents of the output latch on the selected pin).
The Data Latch register (LATD) is also memory
mapped. Read-modify-write operations on the LATD
register read and write the latched output value for
PORTD.
All pins on PORTD are implemented with Schmitt
Trigger input buffers. Each pin is individuallyconfigurable as an input or output.
Each of the PORTD pins has a weak internal pull-up. A
single control bit, RDPU (PORTE<7>), can turn on all
the pull-ups. This is performed by setting RDPU. The
weak pull-up is automatically turned off when the port
pin is configured as a digital output or as one of theother multiplexed peripherals. The pull-ups are
disabled on a Power-on Reset. The PORTE register isshown in Section 10.5 “PORTE, TRISE and LATE
Registers”.

PORTD can also be configured as an 8-bit wide
Streaming Parallel Port (SPP). In this mode, the input
buffers are TTL. For additional information on configuration and uses of the SPP, see Section 18.0
“Streaming Parallel Port”.
Note:

When the Enhanced PWM mode is usedwith either dual or quad outputs, the MSSP
functions of PORTD are automaticallydisabled.

EXAMPLE 10-4:
CLRF

PORTD

CLRF

LATD

MOVLW

0CFh

MOVWF

TRISD

INITIALIZING PORTD; Initialize PORTD by; clearing output; data latches; Alternate method; to clear output; data latches; Value used to; initialize data
; direction; Set RD<3:0> as inputs; RD<5:4> as outputs; RD<7:6> as inputs

Three of the PORTD pins are multiplexed with outputs,
P1B, P1C and P1D, of the Enhanced CCP module. The
operation of these additional PWM output pins iscovered in greater detail in Section 16.0 “Enhanced
Capture/Compare/PWM (ECCP) Module”.
Note:

On a Power-on Reset, these pins are
configured as digital inputs.

DS39632D-page 120

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
TABLE 10-7:
Pin
RD0/SPP0PORTD I/O SUMMARY
Function

TRIS
Setting

I/O

I/O Type

RD0

0

OUT

DIG

LATD<0> data output.

1

IN

ST

PORTD<0> data input.

1

OUT

DIG

SPP<0> output data; takes priority over port data.

1

IN

TTL

SPP<0> input data.

0

OUT

DIG

LATD<1> data output.

1

IN

ST

PORTD<1> data input.

1

OUT

DIG

SPP<1> output data; takes priority over port data.

1

IN

TTL

SPP<1> input data.

0

OUT

DIG

LATD<2> data output.

1

IN

ST

PORTD<2> data input.

1

OUT

DIG

SPP<2> output data; takes priority over port data.

1

IN

TTL

SPP<2> input data.

0

OUT

DIG

LATD<3> data output.

1

IN

ST

PORTD<3> data input.

1

OUT

DIG

SPP<3> output data; takes priority over port data.

1

IN

TTL

SPP<3> input data.

0

OUT

DIG

LATD<4> data output.

1

IN

ST

PORTD<4> data input.

1

OUT

DIG

SPP<4> output data; takes priority over port data.

1

IN

TTL

SPP<4> input data.

0

OUT

DIG

LATD<5> data output

1

IN

ST

PORTD<5> data input

1

OUT

DIG

SPP<5> output data; takes priority over port data.

1

IN

TTL

SPP<5> input data.

P1B

0

OUT

DIG

ECCP1 Enhanced PWM output, channel B; takes priority overport and SPP data.(1)

RD6

0

OUT

DIG

LATD<6> data output.

1

IN

ST

PORTD<6> data input.

1

OUT

DIG

SPP<6> output data; takes priority over port data.

SPP0
RD1/SPP1RD1
SPP1

RD2/SPP2RD2
SPP2

RD3/SPP3RD3
SPP3

RD4/SPP4RD4SPP4

RD5/SPP5/P1B

RD5
SPP5

RD6/SPP6/P1C

SPP6

RD7/SPP7/P1D

1

IN

TTL

SPP<6> input data.

P1C

0

OUT

DIG

ECCP1 Enhanced PWM output, channel C; takes priority overport and SPP data.(1)

RD7

0

OUT

DIG

LATD<7> data output.

1

IN

ST

PORTD<7> data input.

1

OUT

DIG

SPP<7> output data; takes priority over port data.

1

IN

TTL

SPP<7> input data.

0

OUT

DIG

ECCP1 Enhanced PWM output, channel D; takes priority overport and SPP data.(1)

SPP7
P1D
Legend:Note 1:

Description

OUT = Output, IN = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input
May be configured for tri-state during Enhanced PWM shutdown events.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 121

PIC18F2455/2550/4455/4550
TABLE 10-8:
Name
PORTD(3)

SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset
Valueson page

RD7

RD6

RD5

RD4

RD3

RD2

RD1

RD0

54

(3)

LATD

LATD7

LATD6

LATD5

LATD4

LATD3

LATD2

LATD1

LATD0

54

TRISD(3)

TRISD7

TRISD6

TRISD5

TRISD4

TRISD3

TRISD2

TRISD1

TRISD0

54

PORTE

(3)

RDPU

—

—

—

(1,2)

(3)

(3)

(3)

RE0

54

CCP1CON

P1M1(3)

P1M0(3)

DC1B1

DC1B0

CCP1M3

CCP1M2

CCP1M1

CCP1M053

SPPCON(3)

—

—

—

—

—

—

SPPOWN

SPPEN

55

RE3

RE2

RE1

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTD.
Note 1: Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0).
2: RE3 is the only PORTE bit implemented on both 28-pin and 40/44-pin devices. All other bits are
implemented only when PORTE is implemented (i.e., 40/44-pin devices).
3: These registers and/or bits are unimplemented on 28-pin devices.

DS39632D-page 122

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
10.5

PORTE, TRISE and LATE
Registers

Depending on the particular PIC18F2455/2550/4455/
4550 device selected, PORTE is implemented in two
different ways.
For 40/44-pin devices, PORTE is a 4-bit wide port.
Three pins (RE0/AN5/CK1SPP, RE1/AN6/CK2SPPand RE2/AN7/OESPP) are individually configurable as
inputs or outputs. These pins have Schmitt Trigger
input buffers. When selected as an analog input, thesepins will read as ‘0’s.
The corresponding data direction register is TRISE.
Setting a TRISE bit (= 1) will make the corresponding
PORTE pin an input (i.e., put the corresponding output
driver in a high-impedance mode). Clearing a TRISE bit(= 0) will make the corresponding PORTE pin an output(i.e., put the contents of the output latch on the selectedpin).
In addition to port data, the PORTE register(Register 10-1) also contains the RDPU control bit(PORTE<7>); this enables or disables the weakpull-ups on PORTD.
TRISE controls the direction of the RE pins, even when
they are being used as analog inputs. The user must
make sure to keep the pins configured as inputs whenusing them as analog inputs.
Note:

On a Power-on Reset, RE2:RE0 are
configured as analog inputs.

The Data Latch register (LATE) is also memory
mapped. Read-modify-write operations on the LATE
register read and write the latched output value for
PORTE.

REGISTER 10-1:

The fourth pin of PORTE (MCLR/VPP/RE3) is an input
only pin. Its operation is controlled by the MCLRE Configuration bit. When selected as a port pin (MCLRE = 0), it
functions as a digital input only pin; as such, it does nothave TRIS or LAT bits associated with its operation.
Otherwise, it functions as the device’s Master Clear input.
In either configuration, RE3 also functions as the
programming voltage input during programming.
Note:

On a Power-on Reset, RE3 is enabled asa digital input only if Master Clear
functionality is disabled.

EXAMPLE 10-5:
CLRF

CLRF

MOVLW
MOVWF
MOVLW

MOVLW
MOVWF
MOVWF

10.5.1INITIALIZING PORTEPORTE; Initialize PORTE by; clearing output; data latches
LATE; Alternate method; to clear output; data latches
0Ah; Configure A/D
ADCON1 ; for digital inputs
03h; Value used to; initialize data
; direction
07h; Turn off
CMCON; comparators
TRISC; Set RE<0> as inputs; RE<1> as outputs; RE<2> as inputs

PORTE IN 28-PIN DEVICES

For 28-pin devices, PORTE is only available when Master Clear functionality is disabled (MCLRE = 0). In thesecases, PORTE is a single bit, input only port comprisedof RE3 only. The pin operates as previously described.

PORTE REGISTER

R/W-0

U-0

U-0

U-0

R/W-x

R/W-0

R/W-0

R/W-0

(3)

—

—

—

(1,2)

(3)

(3)

RE0(3)

RDPU

RE3

RE2

RE1

bit 7

bit 0

Legend:R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’-n = Value at POR‘1’ = Bit is set‘0’ = Bit is cleared

bit 7

RDPU: PORTD Pull-up Enable bit
1 = PORTD pull-ups are enabled by individual port latch values
0 = All PORTD pull-ups are disabled

bit 6-4

Unimplemented: Read as ‘0’

bit 3-0

RE3:RE0: PORTE Data Input bits(1,2,3)Note 1:2:
3:

x = Bit is unknown

implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0); otherwise,
read as ‘0’.
RE3 is the only PORTE bit implemented on both 28-pin and 40/44-pin devices. All other bits are
implemented only when PORTE is implemented (i.e., 40/44-pin devices).
Unimplemented in 28-pin devices; read as ‘0’.

© 2007 Microchip Technology Inc.

Preliminary

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TABLE 10-9:
Pin

PORTE I/O SUMMARY
Function

TRIS
Setting

I/O

I/O Type

RE0

0

OUT

DIG

1

IN

ST

PORTE<0> data input; disabled when analog input enabled.

AN5

1

IN

ANA

A/D input channel 5; default configuration on POR.

CK1SPP

0

OUT

DIG

SPP clock 1 output (SPP enabled).

RE1

0

OUT

DIG

LATE<1> data output; not affected by analog input.

1

IN

ST

PORTE<1> data input; disabled when analog input enabled.

AN6

1

IN

ANA

A/D input channel 6; default configuration on POR.

CK2SPP

0

OUT

DIG

SPP clock 2 output (SPP enabled).

RE2

0

OUT

DIG

LATE<2> data output; not affected by analog input.

1

IN

ST

PORTE<2> data input; disabled when analog input enabled.

AN7

1

IN

ANA

A/D input channel 7; default configuration on POR.

OESPP

0

OUT

DIG

SPP enable output (SPP enabled).

MCLR

—(1)

IN

ST

External Master Clear input; enabled when MCLRE Configuration bit
is set.

VPP

— (1)

IN

ANA

High-voltage detection, used for ICSP™ mode entry detection.
Always available regardless of pin mode.

RE3

— (1)

IN

ST

PORTE<3> data input; enabled when MCLRE Configuration bit isclear.

RE0/AN5/CK1SPP

RE1/AN6/CK2SPP

RE2/AN7/OESPP

MCLR/VPP/
RE3

Legend:Note 1:

Description
LATE<0> data output; not affected by analog input.

OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input
RE3 does not have a corresponding TRISE<3> bit. This pin is always an input regardless of mode.

TABLE 10-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset
Valueson page

PORTE

RDPU(3)———

RE3(1,2)

RE2(3)

RE1(3)

RE0(3)

54

LATE(3)

—

—

—

—

—

LATE2

LATE1

LATE0

54

(3)

TRISE

—

—

—

—

—

TRISE2

TRISE1

TRISE054

ADCON1

—

—

VCFG1

VCFG0

PCFG3

PCFG2

PCFG1

PCFG0

52

CMCON

C2OUT

C1OUT

C2INV

C1INV

CIS

CM2

CM1

CM0

53

—

—

—

—

—

—

SPPOWN

SPPEN

55

CSEN

CLK1EN

WS3

WS2

WS1

WS0

55

Name

SPPCON(3)SPPCFG(3)CLKCFG1 CLKCFG0

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTE.
Note 1: Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0).
2: RE3 is the only PORTE bit implemented on both 28-pin and 40/44-pin devices. All other bits are
implemented only when PORTE is implemented (i.e., 40/44-pin devices).
3: These registers or bits are unimplemented on 28-pin devices.

DS39632D-page 124

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11.0

TIMER0 MODULEThe T0CON register (Register 11-1) controls all
aspects of the module’s operation, including theprescale selection. It is both readable and writable.

The Timer0 module incorporates the following features:• Software selectable operation as a timer orcounter in both 8-bit or 16-bit modes• Readable and writable registers• Dedicated 8-bit, software programmableprescaler• Selectable clock source (internal or external)• Edge select for external clock• Interrupt on overflow

REGISTER 11-1:

A simplified block diagram of the Timer0 module in 8-bit
mode is shown in Figure 11-1. Figure 11-2 shows a
simplified block diagram of the Timer0 module in 16-bit
mode.

T0CON: TIMER0 CONTROL REGISTER

R/W-1

R/W-1

R/W-1

R/W-1

R/W-1

R/W-1

R/W-1

R/W-1

TMR0ON

T08BIT

T0CS

T0SE

PSA

T0PS2

T0PS1

T0PS0

bit 7

bit 0

Legend:R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’-n = Value at POR‘1’ = Bit is set‘0’ = Bit is clearedx = Bit is unknown

bit 7

TMR0ON: Timer0 On/Off Control bit
1 = Enables Timer00 = Stops Timer0

bit 6

T08BIT: Timer0 8-Bit/16-Bit Control bit
1 = Timer0 is configured as an 8-bit timer/counter
0 = Timer0 is configured as a 16-bit timer/counterbit 5

T0CS: Timer0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (CLKO)

bit 4

T0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin

bit 3

PSA: Timer0 Prescaler Assignment bit
1 = TImer0 prescaler is NOT assigned. Timer0 clock input bypasses prescaler.
0 = Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output.

bit 2-0

T0PS2:T0PS0: Timer0 Prescaler Select bits
111 = 1:256 Prescale value
110 = 1:128 Prescale value
101 = 1:64 Prescale value
100 = 1:32 Prescale value
011 = 1:16 Prescale value
010 = 1:8 Prescale value
001 = 1:4 Prescale value
000 = 1:2 Prescale value© 2007 Microchip Technology Inc.

Preliminary

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11.1

Timer0 Operation

Timer0 can operate as either a timer or a counter; themode is selected by clearing the T0CS bit(T0CON<5>). In Timer mode, the module increments
on every clock by default unless a different prescaler
value is selected (see Section 11.3 “Prescaler”). If
the TMR0 register is written to, the increment isinhibited for the following two instruction cycles. The
user can work around this by writing an adjusted value
to the TMR0 register.
The Counter mode is selected by setting the T0CS bit(= 1). In Counter mode, Timer0 increments either on
every rising or falling edge of pin RA4/T0CKI. The
incrementing edge is determined by the Timer0 Source
Edge Select bit, T0SE (T0CON<4>); clearing this bit
selects the rising edge. Restrictions on the external
clock input are discussed below.
An external clock source can be used to drive Timer0;
however, it must meet certain requirements to ensurethat the external clock can be synchronized with the

FIGURE 11-1:

internal phase clock (TOSC). There is a delay between
synchronization and the onset of incrementing thetimer/counter.

11.2

Timer0 Reads and Writes in
16-Bit Mode

TMR0H is not the actual high byte of Timer0 in 16-bit
mode. It is actually a buffered version of the real highbyte of Timer0 which is not directly readable nor
writable (refer to Figure 11-2). TMR0H is updated withthe contents of the high byte of Timer0 during a read of
TMR0L. This provides the ability to read all 16 bits ofTimer0 without having to verify that the read of the highand low byte were valid, due to a rollover between
successive reads of the high and low byte.
Similarly, a write to the high byte of Timer0 must also
take place through the TMR0H Buffer register. The highbyte is updated with the contents of TMR0H when awrite occurs to TMR0L. This allows all 16 bits of Timer0
to be updated at once.

TIMER0 BLOCK DIAGRAM (8-BIT MODE)
FOSC/40
1
1
Programmable
Prescaler

T0CKI pin
T0SE
T0CS

0

Sync with
Internal
ClocksSet
TMR0IFon Overflow

TMR0L(2 TCY Delay)
83

T0PS2:T0PS0

8

PSA

Note:

Internal Data Bus

Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI maximum prescale.

FIGURE 11-2:

TIMER0 BLOCK DIAGRAM (16-BIT MODE)

FOSC/4

0
1
1

T0CKI pin
T0SE
T0CS

Programmable
Prescaler0

Sync with
Internal
ClocksTMR0High Byte

TMR0L

8

Set
TMR0IFon Overflow(2 TCY Delay)

3

Read TMR0L

T0PS2:T0PS0

Write TMR0L

PSA

8

8

TMR0H
8
8
Internal Data Bus
Note:

Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI maximum prescale.

DS39632D-page 126

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11.3

11.3.1

Prescaler

An 8-bit counter is available as a prescaler for the Timer0
module. The prescaler is not directly readable or writable;
its value is set by the PSA and T0PS2:T0PS0 bits
(T0CON<3:0>) which determine the prescaler
assignment and prescale ratio.
Clearing the PSA bit assigns the prescaler to theTimer0 module. When it is assigned, prescale values
from 1:2 through 1:256, in power-of-2 increments, areselectable.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF TMR0, MOVWF
TMR0, BSF TMR0,etc.) clear the prescaler count.
Note:

Writing to TMR0 when the prescaler isassigned to Timer0 will clear the prescaler
count but will not change the prescaler
assignment.

TABLE 11-1:
Name

SWITCHING PRESCALERASSIGNMENT

The prescaler assignment is fully under software
control and can be changed “on-the-fly” during program
execution.

11.4

Timer0 Interrupt

The TMR0 interrupt is generated when the TMR0
register overflows from FFh to 00h in 8-bit mode, orfrom FFFFh to 0000h in 16-bit mode. This overflow sets
the TMR0IF flag bit. The interrupt can be masked byclearing the TMR0IE bit (INTCON<5>). Before reenabling the interrupt, the TMR0IF bit must be clearedin software by the Interrupt Service Routine.
Since Timer0 is shut down in Sleep mode, the TMR0
interrupt cannot awaken the processor from Sleep.

REGISTERS ASSOCIATED WITH TIMER0
Bit 7

Bit 6

Bit 5

TMR0L

Timer0 Register Low Byte

TMR0H

Timer0 Register High Byte

INTCON

GIE/GIEH PEIE/GIEL TMR0IE

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset
Valueson page52
52

INT0IERBIE

TMR0IF

INT0IF

RBIF

51

INTCON2RBPU

INTEDG0 INTEDG1 INTEDG2—TMR0IP

—

RBIP

51

T0CON

TMR0ON

T08BIT

T0CS

T0SE

PSA

T0PS2

T0PS1

T0PS0

52

—

TRISA6(1)TRISA5TRISA4TRISA3

TRISA2TRISA1TRISA054

TRISA

Legend: — = unimplemented locations, read as ‘0’. Shaded cells are not used by Timer0.
Note 1: RA6 is configured as a port pin based on various primary oscillator modes. When the port pin is disabled,
all of the associated bits read ‘0’.

© 2007 Microchip Technology Inc.

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NOTES:DS39632D-page 128

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12.0

TIMER1 MODULEThe Timer1 timer/counter module incorporates thesefeatures:• Software selectable operation as a 16-bit timer orcounter• Readable and writable 8-bit registers (TMR1H
and TMR1L)• Selectable clock source (internal or external) with
device clock or Timer1 oscillator internal options• Interrupt on overflow• Module Reset on CCP Special Event Trigger• Device clock status flag (T1RUN)REGISTER 12-1:
R/W-0

The module incorporates its own low-power oscillator
to provide an additional clocking option. The Timer1
oscillator can also be used as a low-power clock source
for the microcontroller in power-managed operation.
Timer1 can also be used to provide Real-Time Clock(RTC) functionality to applications with only a minimal
addition of external components and code overhead.
Timer1 is controlled through the T1CON Control
register (Register 12-1). It also contains the Timer1
Oscillator Enable bit (T1OSCEN). Timer1 can be
enabled or disabled by setting or clearing control bit,
TMR1ON (T1CON<0>).

T1CON: TIMER1 CONTROL REGISTER
R-0

RD16

A simplified block diagram of the Timer1 module isshown in Figure 12-1. A block diagram of the module’s
operation in Read/Write mode is shown in Figure 12-2.

T1RUN

R/W-0
T1CKPS1

R/W-0
T1CKPS0

R/W-0
T1OSCEN

R/W-0

R/W-0

R/W-0

T1SYNC

TMR1CS

TMR1ON

bit 7

bit 0

Legend:R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’-n = Value at POR‘1’ = Bit is set‘0’ = Bit is clearedx = Bit is unknown

bit 7

RD16: 16-Bit Read/Write Mode Enable bit
1 = Enables register read/write of Timer1 in one 16-bit operation
0 = Enables register read/write of Timer1 in two 8-bit operations

bit 6

T1RUN: Timer1 System Clock Status bit
1 = Device clock is derived from Timer1 oscillator
0 = Device clock is derived from another source

bit 5-4

T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value

bit 3

T1OSCEN: Timer1 Oscillator Enable bit
1 = Timer1 oscillator is enabled
0 = Timer1 oscillator is shut off
The oscillator inverter and feedback resistor are turned off to eliminate power drain.

bit 2

T1SYNC: Timer1 External Clock Input Synchronization Select bit
When TMR1CS = 1:
1 = Do not synchronize external clock input
0 = Synchronize external clock input
When TMR1CS = 0:This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.

bit 1

TMR1CS: Timer1 Clock Source Select bit
1 = External clock from RC0/T1OSO/T13CKI pin (on the rising edge)
0 = Internal clock (FOSC/4)

bit 0

TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1© 2007 Microchip Technology Inc.

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12.1

Timer1 Operation

cycle (FOSC/4). When the bit is set, Timer1 increments
on every rising edge of the Timer1 external clock input
or the Timer1 oscillator, if enabled.

Timer1 can operate in one of these modes:• Timer• Synchronous Counter• Asynchronous Counter

When Timer1 is enabled, the RC1/T1OSI/UOE and
RC0/T1OSO/T13CKI pins become inputs. This means
the values of TRISC<1:0> are ignored and the pins areread as ‘0’.

The operating mode is determined by the clock selectbit, TMR1CS (T1CON<1>). When TMR1CS is cleared(= 0), Timer1 increments on every internal instruction

FIGURE 12-1:

TIMER1 BLOCK DIAGRAM
Timer1 Oscillator
On/OffT1OSO/T13CKI

1

1
FOSC/4
Internal
Clock

T1OSI

Synchronize

Prescaler
1, 2, 4, 80

Detect0
2

T1OSCEN(1)Sleep Input

Timer1
On/Off

TMR1CST1CKPS1:T1CKPS0T1SYNCTMR1ON

Clear TMR1
(CCP Special Event Trigger)

Set
TMR1IFon Overflow

TMR1
High Byte

TMR1L

Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.

FIGURE 12-2:

TIMER1 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)
Timer1 Oscillator
1

T1OSO/T13CKI

1
FOSC/4
Internal
Clock

T1OSI

Synchronize

Prescaler
1, 2, 4, 80

Detect0
2

T1OSCEN(1)Sleep Input

Timer1
On/Off

TMR1CST1CKPS1:T1CKPS0T1SYNCTMR1ON
Clear TMR1
(CCP Special Event Trigger)

TMR1
High Byte

TMR1L

8

Set
TMR1IFon Overflow

Read TMR1L
Write TMR1L
8

8

TMR1H
8
8
Internal Data Bus

Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.

DS39632D-page 130

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12.2

TABLE 12-1:

Timer1 16-Bit Read/Write Mode

Timer1 can be configured for 16-bit reads and writes(see Figure 12-2). When the RD16 control bit(T1CON<7>) is set, the address for TMR1H is mapped
to a buffer register for the high byte of Timer1. A readfrom TMR1L will load the contents of the high byte ofTimer1 into the Timer1 high byte buffer. This provides
the user with the ability to accurately read all 16 bits ofTimer1 without having to determine whether a read of
the high byte, followed by a read of the low byte, has
become invalid due to a rollover between reads.

Osc Type
LP

CAPACITOR SELECTION FOR
THE TIMER OSCILLATOR(2,3,4)Freq
32 kHz

C1
27 pF

C2
(1)

27 pF(1)Note 1: Microchip suggests these values as astarting point in validating the oscillator
circuit.
2: Higher capacitance increases the stabilityof the oscillator but also increases thestart-up time.

A write to the high byte of Timer1 must also take placethrough the TMR1H Buffer register. The Timer1 highbyte is updated with the contents of TMR1H when awrite occurs to TMR1L. This allows a user to write all
16 bits to both the high and low bytes of Timer1 at once.

3: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate
valuesofexternal
components.

The high byte of Timer1 is not directly readable orwritable in this mode. All reads and writes must takeplace through the Timer1 High Byte Buffer register.
Writes to TMR1H do not clear the Timer1 prescaler.
The prescaler is only cleared on writes to TMR1L.

4: Capacitor values are for design guidance
only.

12.3

Timer1 Oscillator

An on-chip crystal oscillator circuit is incorporated
between pins T1OSI (input) and T1OSO (amplifier
output). It is enabled by setting the Timer1 Oscillator
Enable bit, T1OSCEN (T1CON<3>). The oscillator is a
low-power circuit rated for 32 kHz crystals. It willcontinue to run during all power-managed modes. The
circuit for a typical LP oscillator is shown in Figure 12-3.
Table 12-1 shows the capacitor selection for the Timer1
oscillator.
The user must provide a software time delay to ensure
proper start-up of the Timer1 oscillator.

FIGURE 12-3:

EXTERNALCOMPONENTS FOR THE
TIMER1 LP OSCILLATOR

C1
33 pF

PIC18FXXXX

XTAL
32.768 kHz
T1OSO
C2
33 pF
See the Notes with Table 12-1 for additional
information about capacitor selection.

© 2007 Microchip Technology Inc.

USING TIMER1 AS A CLOCKSOURCEThe Timer1 oscillator is also available as a clock sourcein power-managed modes. By setting the clock selectbits, SCS1:SCS0 (OSCCON<1:0>), to ‘01’, the device
switches to SEC_RUN mode. Both the CPU andperipherals are clocked from the Timer1 oscillator. If the
IDLEN bit (OSCCON<7>) is cleared and a SLEEP
instruction is executed, the device enters SEC_IDLE
mode. Additional details are available in Section 3.0“Power-Managed Modes”.
Whenever the Timer1 oscillator is providing the clock
source, the Timer1 system clock status flag, T1RUN(T1CON<6>), is set. This can be used to determine thecontroller’s current clocking mode. It can also indicate
the clock source being currently used by the Fail-Safe
Clock Monitor. If the Clock Monitor is enabled and theTimer1 oscillator fails while providing the clock, polling
the T1RUN bit will indicate whether the clock is being
provided by the Timer1 oscillator or another source.

12.3.2

T1OSI

Note:

12.3.1

LOW-POWER TIMER1 OPTIONThe Timer1 oscillator can operate at two distinct levelsof power consumption based on device configuration.
When the LPT1OSC Configuration bit is set, the Timer1
oscillator operates in a low-power mode. When
LPT1OSC is not set, Timer1 operates at a higher power
level. Power consumption for a particular mode is relatively constant, regardless of the device’s operating
mode. The default Timer1 configuration is the higher
power mode.
As the low-power Timer1 mode tends to be moresensitive to interference, high noise environments may
cause some oscillator instability. The low-power optionis, therefore, best suited for low noise applications
where power conservation is an important design
consideration.

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12.3.3

TIMER1 OSCILLATOR LAYOUTCONSIDERATIONS

12.5

The Timer1 oscillator circuit draws very little power
during operation. Due to the low-power nature of theoscillator, it may also be sensitive to rapidly changing
signals in close proximity.
The oscillator circuit, shown in Figure 12-3, should belocated as close as possible to the microcontroller.
There should be no circuits passing within the oscillator
circuit boundaries other than VSS or VDD.
If a high-speed circuit must be located near the oscillator (such as the CCP1 pin in Output Compare or PWM
mode, or the primary oscillator using the OSC2 pin), a
grounded guard ring around the oscillator circuit, asshown in Figure 12-4, may be helpful when used on asingle-sided PCB or in addition to a ground plane.

FIGURE 12-4:

OSCILLATOR CIRCUIT
WITH GROUNDED
GUARD RING

If either of the CCP modules is configured in Compare
mode to generate a Special Event Trigger(CCP1M3:CCP1M0 or CCP2M3:CCP2M0 = 1011),
this signal will reset Timer1. The trigger from CCP2 will
also start an A/D conversion if the A/D module isenabled (see Section 15.3.4 “Special Event Trigger”
for more information).
The module must be configured as either a timer or asynchronous counter to take advantage of this feature.
When used this way, the CCPRH:CCPRL register paireffectively becomes a period register for Timer1.
If Timer1 is running in Asynchronous Counter mode,
this Reset operation may not work.
In the event that a write to Timer1 coincides with aSpecial Event Trigger, the write operation will takeprecedence.
Note:

VDD
VSS

12.6

OSC1
OSC2

The Special Event Triggers from the
CCP2 module will not set the TMR1IF
interrupt flag bit (PIR1<0>).

Using Timer1 as a Real-Time
Clock

Adding an external LP oscillator to Timer1 (such as theone described in Section 12.3 “Timer1 Oscillator”)
gives users the option to include RTC functionality totheir applications. This is accomplished with an
inexpensive watch crystal to provide an accurate timebase and several lines of application code to calculate
the time. When operating in Sleep mode and using abattery or supercapacitor as a power source, it cancompletely eliminate the need for a separate RTC
device and battery backup.

RC0
RC1

RC2
Note: Not drawn to scale.

12.4

Resetting Timer1 Using the CCP
Special Event Trigger

Timer1 Interrupt

The TMR1 register pair (TMR1H:TMR1L) incrementsfrom 0000h to FFFFh and rolls over to 0000h. The
Timer1 interrupt, if enabled, is generated on overflow
which is latched in interrupt flag bit, TMR1IF(PIR1<0>). This interrupt can be enabled or disabled
by setting or clearing the Timer1 Interrupt Enable bit,
TMR1IE (PIE1<0>).

The application code routine, RTCisr, shown in
Example 12-1, demonstrates a simple method toincrement a counter at one-second intervals using an
Interrupt Service Routine. Incrementing the TMR1
register pair to overflow triggers the interrupt and calls
the routine, which increments the seconds counter by
one. Additional counters for minutes and hours are
incremented as the previous counter overflows.
Since the register pair is 16 bits wide, counting up to
overflow the register directly from a 32.768 kHz clock
would take 2 seconds. To force the overflow at therequired one-second intervals, it is necessary to preload it. The simplest method is to set the MSb of
TMR1H with a BSF instruction. Note that the TMR1L
register is never preloaded or altered; doing so may
introduce cumulative error over many cycles.
For this method to be accurate, Timer1 must operate in
Asynchronous mode and the Timer1 overflow interrupt
must be enabled (PIE1<0> = 1) as shown in theroutine, RTCinit. The Timer1 oscillator must also beenabled and running at all times.

DS39632D-page 132

Preliminary© 2007 Microchip Technology Inc.

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EXAMPLE 12-1:

IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE

RTCinit
MOVLW
MOVWF
CLRF
MOVLW
MOVWF
CLRF
CLRF
MOVLW
MOVWF
BSF
RETURN

80h
TMR1H
TMR1L
b’00001111’
T1OSC
secs
mins
d’12’
hours
PIE1, TMR1IE; Preload TMR1 register pair
; for 1 second overflow

BSF
BCF
INCF
MOVLW
CPFSGT
RETURN
CLRF
INCF
MOVLW
CPFSGT
RETURN
CLRF
INCF
MOVLW
CPFSGT
RETURN
MOVLW
MOVWF
RETURN

TMR1H, 7
PIR1, TMR1IF
secs, F
d’59’
secs

; Preload for 1 sec overflow; Clear interrupt flag
; Increment seconds; 60 seconds elapsed?

; Configure for external clock,; Asynchronous operation, external oscillator; Initialize timekeeping registers;; Enable Timer1 interrupt

RTCisrTABLE 12-2:
Name; No, done
; Clear seconds; Increment minutes; 60 minutes elapsed?

secs
mins, Fd’59’
mins

; No, done
; clear minutes; Increment hours; 24 hours elapsed?

mins
hours, F
d’23’
hours

; No, done
; Reset hours to 1

d’01’
hours

; DoneREGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset
Valueson page

INTCON

GIE/GIEH PEIE/GIEL

TMR0IEINT0IERBIE

TMR0IF

INT0IF

RBIF

51

PIR1

SPPIF(1)

ADIF

RCIF

TXIF

SSPIF

CCP1IF

TMR2IF

TMR1IF

54

PIE1

(1)

SPPIE

ADIE

RCIE

TXIE

SSPIE

CCP1IETMR2IETMR1IE54

IPR1

SPPIP(1)

ADIP

RCIP

TXIP

SSPIP

CCP1IP

TMR2IP

TMR1IP

54

TMR1L

Timer1 Register Low Byte

52

TMR1H

TImer1 Register High Byte

52

T1CON

RD16

T1RUN

T1CKPS1 T1CKPS0 T1OSCEN T1SYNC

TMR1CS

TMR1ON

52

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.
Note 1: These bits are unimplemented on 28-pin devices; always maintain these bits clear.

© 2007 Microchip Technology Inc.

Preliminary

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NOTES:DS39632D-page 134

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
13.0

TIMER2 MODULE

13.1

The Timer2 module timer incorporates the following
features:• 8-bit timer and period registers (TMR2 and PR2,
respectively)• Readable and writable (both registers)• Software programmable prescaler (1:1, 1:4 and1:16)• Software programmable postscaler (1:1 through
1:16)• Interrupt on TMR2 to PR2 match• Optional use as the shift clock for the MSSP
moduleThe module is controlled through the T2CON register(Register 13-1) which enables or disables the timer andconfigures the prescaler and postscaler. Timer2 can be
shut off by clearing control bit, TMR2ON (T2CON<2>),
to minimize power consumption.
A simplified block diagram of the module is shown in
Figure 13-1.

Timer2 Operation

In normal operation, TMR2 is incremented from 00h oneach clock (FOSC/4). A 2-bit counter/prescaler on theclock input gives direct input, divide-by-4 and divide-by16 prescale options. These are selected by the prescaler
control bits, T2CKPS1:T2CKPS0 (T2CON<1:0>). The
value of TMR2 is compared to that of the period register,PR2, on each clock cycle. When the two values match,the comparator generates a match signal as the timer
output. This signal also resets the value of TMR2 to 00h
on the next cycle and drives the output counter/
postscaler (see Section 13.2 “Timer2 Interrupt”).
The TMR2 and PR2 registers are both directly readable
and writable. The TMR2 register is cleared on any
device Reset, while the PR2 register initializes at FFh.
Both the prescaler and postscaler counters are clearedon the following events:• a write to the TMR2 register• a write to the T2CON register• any device Reset (Power-on Reset, MCLR Reset,
Watchdog Timer Reset or Brown-out Reset)
TMR2 is not cleared when T2CON is written.

REGISTER 13-1:

T2CON: TIMER2 CONTROL REGISTER

U-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

—

T2OUTPS3

T2OUTPS2

T2OUTPS1

T2OUTPS0

TMR2ONT2CKPS1T2CKPS0

bit 7

bit 0

Legend:R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’-n = Value at POR‘1’ = Bit is set‘0’ = Bit is cleared

bit 7

Unimplemented: Read as ‘0’

bit 6-3

T2OUTPS3:T2OUTPS0: Timer2 Output Postscale Select bits
0000 = 1:1 Postscale
0001 = 1:2 Postscale•••
1111 = 1:16 Postscale

bit 2

TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off

bit 1-0

T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4
1x = Prescaler is 16© 2007 Microchip Technology Inc.

Preliminary

x = Bit is unknown

DS39632D-page 135

PIC18F2455/2550/4455/4550
13.2

Timer2 Interrupt

13.3

Timer2 also can generate an optional device interrupt.
The Timer2 output signal (TMR2 to PR2 match) provides the input for the 4-bit output counter/postscaler.
This counter generates the TMR2 match interrupt flag
which is latched in TMR2IF (PIR1<1>). The interrupt isenabled by setting the TMR2 Match Interrupt Enable
bit, TMR2IE (PIE1<1>).

TMR2 Output

The unscaled output of TMR2 is available primarily to
the CCP modules, where it is used as a time base for
operations in PWM mode.
Timer2 can be optionally used as the shift clock source
for the MSSP module operating in SPI mode.
Additional information is provided in Section 19.0
“Master Synchronous Serial Port (MSSP) Module”.

A range of 16 postscale options (from 1:1 through 1:16
inclusive) can be selected with the postscaler control
bits, T2OUTPS3:T2OUTPS0 (T2CON<6:3>).

FIGURE 13-1:

TIMER2 BLOCK DIAGRAM
4

1:1 to 1:16
Postscaler

T2OUTPS3:T2OUTPS0

Set TMR2IF

2

TMR2 Output(to PWM or MSSP)T2CKPS1:T2CKPS0
TMR2/PR2
Match

Reset

1:1, 1:4, 1:16
Prescaler

FOSC/4

TMR2

Comparator

8

PR2
8

8

Internal Data Bus

TABLE 13-1:
Name

REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Bit 5

Bit 4

INTCON GIE/GIEH PEIE/GIEL

TMR0IEPIR1

SPPIF(1)

ADIF

RCIF

PIE1

SPPIE(1)

ADIE

IPR1

SPPIP(1)

ADIP

TMR2

Timer2 Register

T2CON
PR2

Bit 7

—

Bit 6

Bit 1

Bit 0

Reset
Valueson page

Bit 3

Bit 2

INT0IERBIE

TMR0IF

INT0IF

RBIF

51

TXIF

SSPIF

CCP1IF

TMR2IF

TMR1IF

54

RCIE

TXIE

SSPIE

CCP1IETMR2IETMR1IE

54

RCIP

TXIP

SSPIP

CCP1IP

TMR2IP

TMR1IP

54

T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS052

52Timer2 Period Register

52

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.
Note 1: These bits are unimplemented on 28-pin devices; always maintain these bits clear.

DS39632D-page 136

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
14.0

TIMER3 MODULEThe Timer3 module timer/counter incorporates thesefeatures:• Software selectable operation as a 16-bit timer orcounter• Readable and writable 8-bit registers (TMR3H
and TMR3L)• Selectable clock source (internal or external) with
device clock or Timer1 oscillator internal options• Interrupt on overflow• Module Reset on CCP Special Event Trigger

REGISTER 14-1:

A simplified block diagram of the Timer3 module isshown in Figure 14-1. A block diagram of the module’s
operation in Read/Write mode is shown in Figure 14-2.
The Timer3 module is controlled through the T3CON
register (Register 14-1). It also selects the clock source
options for the CCP modules (see Section 15.1.1“CCP Modules and Timer Resources” for more
information).

T3CON: TIMER3 CONTROL REGISTER

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

RD16

T3CCP2T3CKPS1T3CKPS0

T3CCP1T3SYNCTMR3CS

TMR3ON

bit 7

bit 0

Legend:R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’-n = Value at POR‘1’ = Bit is set‘0’ = Bit is clearedx = Bit is unknown

bit 7

RD16: 16-Bit Read/Write Mode Enable bit
1 = Enables register read/write of Timer3 in one 16-bit operation
0 = Enables register read/write of Timer3 in two 8-bit operations

bit 6, 3

T3CCP2:T3CCP1: Timer3 and Timer1 to CCPx Enable bits
1x = Timer3 is the capture/compare clock source for both CCP modules
01 = Timer3 is the capture/compare clock source for CCP2;
Timer1 is the capture/compare clock source for CCP1
00 = Timer1 is the capture/compare clock source for both CCP modules

bit 5-4

T3CKPS1:T3CKPS0: Timer3 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value

bit 2

T3SYNC: Timer3 External Clock Input Synchronization Control bit(Not usable if the device clock comes from Timer1/Timer3.)
When TMR3CS = 1:
1 = Do not synchronize external clock input
0 = Synchronize external clock input
When TMR3CS = 0:This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0.

bit 1

TMR3CS: Timer3 Clock Source Select bit
1 = External clock input from Timer1 oscillator or T13CKI (on the rising edge after the first falling edge)
0 = Internal clock (FOSC/4)

bit 0

TMR3ON: Timer3 On bit
1 = Enables Timer3
0 = Stops Timer3© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 137

PIC18F2455/2550/4455/4550
14.1

Timer3 Operation

cycle (FOSC/4). When the bit is set, Timer3 increments
on every rising edge of the Timer1 external clock input
or the Timer1 oscillator, if enabled.

Timer3 can operate in one of three modes:• Timer• Synchronous Counter• Asynchronous CounterAs with Timer1, the RC1/T1OSI/UOE and RC0/
T1OSO/T13CKI pins become inputs when the Timer1
oscillator is enabled. This means the values of
TRISC<1:0> are ignored and the pins are read as ‘0’.

The operating mode is determined by the clock selectbit, TMR3CS (T3CON<1>). When TMR3CS is cleared(= 0), Timer3 increments on every internal instruction

FIGURE 14-1:

TIMER3 BLOCK DIAGRAM
Timer1 Oscillator

Timer1 Clock Input
1

T1OSO/T13CKI

1
FOSC/4
Internal
Clock

T1OSI

Synchronize

Prescaler
1, 2, 4, 80

Detect0
2

T1OSCEN(1)Sleep Input

Timer3
On/Off

TMR3CST3CKPS1:T3CKPS0T3SYNCTMR3ON

CCP1/CCP2 Special Event Trigger
CCP1/CCP2 Select from T3CON<6,3>

Clear TMR3Set
TMR3IFon Overflow

TMR3
High Byte

TMR3L

Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.

FIGURE 14-2:

TIMER3 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)
Timer1 Oscillator

Timer1 Clock Input
1

T1OSO/T13CKI

1
FOSC/4
Internal
Clock

T1OSI

Synchronize

Prescaler
1, 2, 4, 80

Detect0
2

T1OSCEN(1)Sleep Input

Timer3
On/Off

TMR3CST3CKPS1:T3CKPS0T3SYNCTMR3ON
CCP1/CCP2 Special Event Trigger
CCP1/CCP2 Select from T3CON<6,3>

Clear TMR3

TMR3
High Byte

TMR3L

8

Set
TMR3IFon Overflow

Read TMR1L
Write TMR1L
8

8

TMR3H
8
8
Internal Data Bus
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.

DS39632D-page 138

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PIC18F2455/2550/4455/4550
14.2

Timer3 16-Bit Read/Write Mode

14.4

Timer3 can be configured for 16-bit reads and writes(see Figure 14-2). When the RD16 control bit(T3CON<7>) is set, the address for TMR3H is mapped
to a buffer register for the high byte of Timer3. A readfrom TMR3L will load the contents of the high byte ofTimer3 into the Timer3 high byte buffer. This provides
the user with the ability to accurately read all 16 bits ofTimer1 without having to determine whether a read of
the high byte, followed by a read of the low byte, has
become invalid due to a rollover between reads.
A write to the high byte of Timer3 must also take placethrough the TMR3H Buffer register. The Timer3 highbyte is updated with the contents of TMR3H when awrite occurs to TMR3L. This allows a user to write all
16 bits to both the high and low bytes of Timer3 at once.
The high byte of Timer3 is not directly readable orwritable in this mode. All reads and writes must takeplace through the Timer3 High Byte Buffer register.

Timer3 Interrupt

The TMR3 register pair (TMR3H:TMR3L) incrementsfrom 0000h to FFFFh and overflows to 0000h. The
Timer3 interrupt, if enabled, is generated on overflow
and is latched in interrupt flag bit, TMR3IF (PIR2<1>).
This interrupt can be enabled or disabled by setting or
clearing the Timer3 Interrupt Enable bit, TMR3IE(PIE2<1>).

14.5

Resetting Timer3 Using the CCP
Special Event Trigger

If the CCP2 module is configured to generate aSpecial Event Trigger in Compare mode
(CCP2M3:CCP2M0 = 1011), this signal will reset
Timer3. It will also start an A/D conversion if the A/D
module is enabled (see Section 15.3.4 “Special
Event Trigger” for more information.).

Writes to TMR3H do not clear the Timer3 prescaler.
The prescaler is only cleared on writes to TMR3L.

The module must be configured as either a timer orsynchronous counter to take advantage of this feature.
When used this way, the CCPR2H:CCPR2L registerpair effectively becomes a period register for Timer3.

14.3

If Timer3 is running in Asynchronous Counter mode,
the Reset operation may not work.

Using the Timer1 Oscillator as theTimer3 Clock Source

The Timer1 internal oscillator may be used as the clock
source for Timer3. The Timer1 oscillator is enabled by
setting the T1OSCEN (T1CON<3>) bit. To use it as theTimer3 clock source, the TMR3CS bit must also be set.
As previously noted, this also configures Timer3 toincrement on every rising edge of the oscillator source.

In the event that a write to Timer3 coincides with aSpecial Event Trigger from a CCP module, the write willtake precedence.
Note:

The Special Event Triggers from the
CCP2 module will not set the TMR3IF
interrupt flag bit (PIR2<1>).

The Timer1 oscillator is described in Section 12.0
“Timer1 Module”.

TABLE 14-1:
Name

REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER

Bit 7

Bit 6

INTCON GIE/GIEH PEIE/GIEL

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset
Valueson page

TMR0IEINT0IERBIE

TMR0IF

INT0IF

RBIF

51

PIR2

OSCFIF

CMIF

USBIF

EEIF

BCLIF

HLVDIF

TMR3IF

CCP2IF54

PIE2

OSCFIE

CMIE

USBIE

EEIE

BCLIE

HLVDIETMR3IECCP2IE54

IPR2

OSCFIP

CMIP

USBIP

EEIP

BCLIP

HLVDIP

TMR3IP

CCP2IP

54

TMR3L

Timer3 Register Low Byte

53

TMR3H

Timer3 Register High Byte

53

T1CON

RD16

T1RUN

T1CKPS1 T1CKPS0 T1OSCEN T1SYNC

TMR1CS

TMR1ON

52

T3CON

RD16

T3CCP2T3CKPS1 T3CKPS0TMR3CS

TMR3ON53

T3CCP1T3SYNC

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 139

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NOTES:DS39632D-page 140

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
15.0

CAPTURE/COMPARE/PWM(CCP) MODULES

The Capture and Compare operations described in thischapter apply to all standard and Enhanced CCP
modules.

PIC18F2455/2550/4455/4550 devices all have two
CCP (Capture/Compare/PWM) modules. Each module
contains a 16-bit register, which can operate as a 16-bit
Capture register, a 16-bit Compare register or a PWM
Master/Slave Duty Cycle register.
In 28-pin devices, the two standard CCP modules (CCP1and CCP2) operate as described in this chapter. In
40/44-pin devices, CCP1 is implemented as an
Enhanced CCP module, with standard Capture andCompare modes and Enhanced PWM modes. The
ECCP implementation is discussed in Section 16.0
“Enhanced Capture/Compare/PWM (ECCP) Module”.

REGISTER 15-1:

Note: Throughout this section and Section 16.0
“Enhanced Capture/Compare/PWM (ECCP)
Module”, references to the register and bit
names for CCP modules are referred to generically by the use of ‘x’ or ‘y’ in place of thespecific module number. Thus, “CCPxCON”
might refer to the control register for CCP1,
CCP2 or ECCP1. “CCPxCON” is usedthroughout these sections to refer to themodule control register regardless of whether
the CCP module is a standard or Enhanced
implementation.

CCPxCON: STANDARD CCPx CONTROL REGISTER

U-0

U-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

—(1)

—(1)

DCxB1

DCxB0

CCPxM3

CCPxM2

CCPxM1

CCPxM0

bit 7

bit 0

Legend:R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’-n = Value at POR‘1’ = Bit is set‘0’ = Bit is clearedx = Bit is unknown

bit 7-6

Unimplemented: Read as ‘0’(1)bit 5-4

DCxB1:DCxB0: PWM Duty Cycle Bit 1 and Bit 0 for CCPx Module
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two LSbs (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight MSbs of the duty
cycle are found in CCPR1L.

bit 3-0

CCPxM3:CCPxM0: CCPx Module Mode Select bits
0000 = Capture/Compare/PWM disabled (resets CCPx module)
0001 = Reserved
0010 = Compare mode: toggle output on match (CCPxIF bit is set)
0011 = Reserved
0100 = Capture mode: every falling edge
0101 = Capture mode: every rising edge
0110 = Capture mode: every 4th rising edge
0111 = Capture mode: every 16th rising edge
1000 = Compare mode: initialize CCPx pin low; on compare match, force CCPx pin high
(CCPxIF bit is set)
1001 = Compare mode: initialize CCPx pin high; on compare match, force CCPx pin low(CCPxIF bit is set)
1010 = Compare mode: generate software interrupt on compare match (CCPxIF bit is set,
CCPx pin reflects I/O state)1011 = Compare mode: trigger special event, reset timer, start A/D conversion on CCP2 match(CCPxIF bit is set)
11xx = PWM mode

Note 1:

These bits are not implemented on 28-pin devices and are read as ‘0’.

© 2007 Microchip Technology Inc.

Preliminary

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15.1

CCP Module Configuration

Each Capture/Compare/PWM module is associatedwith a control register (generically, CCPxCON) and adata register (CCPRx). The data register, in turn, iscomprised of two 8-bit registers: CCPRxL (low byte)
and CCPRxH (high byte). All registers are bothreadable and writable.

15.1.115.1.2

CCP MODULES AND TIMERRESOURCESThe CCP modules utilize Timers 1, 2 or 3, dependingon the mode selected. Timer1 and Timer3 are available
to modules in Capture or Compare modes, while
Timer2 is available for modules in PWM mode.

TABLE 15-1:

Timer Resource

CaptureCompare
PWM

Timer1 or Timer3
Timer1 or Timer3
Timer2TABLE 15-2:

CCP2 PIN ASSIGNMENT

The pin assignment for CCP2 (Capture input, Compare
and PWM output) can change, based on device configuration. The CCP2MX Configuration bit determines
which pin CCP2 is multiplexed to. By default, it isassigned to RC1 (CCP2MX = 1). If the Configuration bit
is cleared, CCP2 is multiplexed with RB3.
Changing the pin assignment of CCP2 does not
automatically change any requirements for configuring
the port pin. Users must always verify that the appropriate TRIS register is configured correctly for CCP2
operation, regardless of where it is located.

CCP MODE – TIMERRESOURCE

CCP/ECCP Mode

The assignment of a particular timer to a module isdetermined by the Timer to CCP enable bits in the
T3CON register (Register 14-1). Both modules may be
active at any given time and may share the same timer
resource if they are configured to operate in the samemode (Capture/Compare or PWM) at the same time. Theinteractions between the two modules are summarized in
Figure 15-2. In Timer1 in Asynchronous Counter mode,the capture operation will not work.

INTERACTIONS BETWEEN CCP1 AND CCP2 FOR TIMER RESOURCES

CCP1 Mode CCP2 Mode

Interaction

CaptureCaptureEach module can use TMR1 or TMR3 as the time base. The time base can be different
for each CCP.

CaptureCompareCCP2 can be configured for the Special Event Trigger to reset TMR1 or TMR3
(depending upon which time base is used). Automatic A/D conversions on trigger event
can also be done. Operation of CCP1 could be affected if it is using the same timer as atime base.

CompareCaptureCCP1 be configured for the Special Event Trigger to reset TMR1 or TMR3 (depending
upon which time base is used). Operation of CCP2 could be affected if it is using thesame timer as a time base.

CompareCompareEither module can be configured for the Special Event Trigger to reset the time base.
Automatic A/D conversions on CCP2 trigger event can be done. Conflicts may occur if
both modules are using the same time base.

Capture

PWM(1)

None

Compare

PWM(1)None

PWM(1)

Capture

None

(1)

PWM

CompareNone

PWM(1)

PWM

Note 1:

Both PWMs will have the same frequency and update rate (TMR2 interrupt).

Includes standard and Enhanced PWM operation.

DS39632D-page 142

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
15.2

15.2.3

Capture Mode

When the Capture mode is changed, a false captureinterrupt may be generated. The user should keep the
CCPxIE interrupt enable bit clear to avoid false
interrupts. The interrupt flag bit, CCPxIF, should also be
cleared following any such change in operating mode.

In Capture mode, the CCPRxH:CCPRxL register paircaptures the 16-bit value of the TMR1 or TMR3
registers when an event occurs on the corresponding
CCPx pin. An event is defined as one of the following:• every falling edge
• every rising edge
• every 4th rising edge
• every 16th rising edge

15.2.4

Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore, the first capture may be froma non-zero prescaler. Example 15-1 shows therecommended method for switching between capture
prescalers. This example also clears the prescaler
counter and will not generate the “false” interrupt.

CCP PIN CONFIGURATIONIn Capture mode, the appropriate CCPx pin should be
configured as an input by setting the corresponding
TRIS direction bit.
Note:

If RB3/CCP2 or RC1/CCP2 is configured
as an output, a write to the port can cause
a capture condition.

15.2.2TIMER1/TIMER3 MODE SELECTION

EXAMPLE 15-1:

CLRF
MOVLW

The timers that are to be used with the capture feature(Timer1 and/or Timer3) must be running in Timer mode or
Synchronized Counter mode. In Asynchronous Countermode, the capture operation will not work. The timer to be
used with each CCP module is selected in the T3CON
register (see Section 15.1.1 “CCP Modules and Timer
Resources”).

FIGURE 15-1:

CCP PRESCALER

There are four prescaler settings in Capture mode.
They are specified as part of the operating mode
selected by the mode select bits (CCPxM3:CCPxM0).
Whenever the CCP module is turned off or Capturemode is disabled, the prescaler counter is cleared. Thismeans that any Reset will clear the prescaler counter.

The event is selected by the mode select bits,
CCPxM3:CCPxM0 (CCPxCON<3:0>). When a capture
is made, the interrupt request flag bit, CCPxIF, is set; itmust be cleared in software. If another capture occurs
before the value in register CCPRx is read, the oldcaptured value is overwritten by the new captured value.

15.2.1SOFTWARE INTERRUPT

MOVWFCHANGING BETWEENCAPTURE PRESCALERS(CCP2 SHOWN)

CCP2CON; Turn CCP module off
NEW_CAPT_PS ; Load WREG with the; new prescaler mode
; value and CCP ON
CCP2CON; Load CCP2CON with; this value

CAPTURE MODE OPERATION BLOCK DIAGRAM
TMR3H

TMR3L

Set CCP1IF
T3CCP2
CCP1 pin
Prescaler÷ 1, 4, 16

andEdge Detect

CCPR1H

T3CCP2
4

CCP1CON<3:0>
Q1:Q4
CCP2CON<3:0>

4

TMR3
EnableCCPR1L

TMR1
Enable
TMR1H

TMR1L

TMR3H

TMR3L

Set CCP2IF

4
T3CCP1T3CCP2

TMR3
EnableCCP2 pin
Prescaler÷ 1, 4, 16

andEdge Detect

CCPR2H

CCPR2L

TMR1
EnableT3CCP2T3CCP1© 2007 Microchip Technology Inc.

Preliminary

TMR1H

TMR1L

DS39632D-page 143

PIC18F2455/2550/4455/4550
15.3

15.3.2Compare Mode

TIMER1/TIMER3 MODE SELECTION

In Compare mode, the 16-bit CCPRx register value isconstantly compared against either the TMR1 or TMR3
register pair value. When a match occurs, the CCPx pin
can be:Timer1 and/or Timer3 must be running in Timer mode,or Synchronized Counter mode, if the CCP module isusing the compare feature. In Asynchronous Countermode, the compare operation may not work.

• driven high• driven low• toggled (high-to-low or low-to-high)• remain unchanged (that is, reflects the state of the
I/O latch)

15.3.3

When the Generate Software Interrupt mode is chosen(CCPxM3:CCPxM0 = 1010), the corresponding CCPx
pin is not affected. Only a CCP interrupt is generated,
if enabled, and the CCPxIE bit is set.

The action on the pin is based on the value of the mode
select bits (CCPxM3:CCPxM0). At the same time, theinterrupt flag bit, CCPxIF, is set.

15.3.1

CCP PIN CONFIGURATIONThe user must configure the CCPx pin as an output by
clearing the appropriate TRIS bit.
Note:

SOFTWARE INTERRUPT MODE

Clearing the CCP2CON register will force
the RB3 or RC1 compare output latch(depending on device configuration) to thedefault low level. This is not the PORTB or
PORTC I/O data latch.

15.3.4SPECIAL EVENT TRIGGER

Both CCP modules are equipped with a Special Event
Trigger. This is an internal hardware signal generated
in Compare mode to trigger actions by other modules.
The Special Event Trigger is enabled by selecting
the Compare Special Event Trigger mode
(CCPxM3:CCPxM0 = 1011).
For either CCP module, the Special Event Trigger resets
the Timer register pair for whichever timer resource iscurrently assigned as the module’s time base. This
allows the CCPRx registers to serve as a programmableperiod register for either timer.
The Special Event Trigger for CCP2 can also start an
A/D conversion. In order to do this, the A/D converter
must already be enabled.

FIGURE 15-2:

COMPARE MODE OPERATION BLOCK DIAGRAM

CCPR1H

Set CCP1IF

CCPR1LSpecial Event Trigger(Timer1/Timer3 Reset)
CCP1 pinComparator

OutputLogic

Compare
Match

S

Q

R
TRIS
Output Enable

4
CCP1CON<3:0>
0

TMR1H

TMR1L

0

1

TMR3H

TMR3L

1

Special Event Trigger(Timer1/Timer3 Reset, A/D Trigger)

T3CCP1T3CCP2
Set CCP2IF
Comparator

CCPR2H

CCP2 pinCompareMatch

OutputLogic
4

CCPR2L

S

Q

R
TRIS
Output Enable

CCP2CON<3:0>

DS39632D-page 144

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
TABLE 15-3:
Name
INTCONREGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3
Bit 7

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset
Valueson page

TMR0IEINT0IERBIE

TMR0IF

INT0IF

RBIF

51

Bit 6

GIE/GIEH PEIE/GIEL
(1)

RCON

IPEN

SBOREN

—

RI

TO

PD

POR

BOR

52

PIR1

SPPIF(2)

ADIF

RCIF

TXIF

SSPIF

CCP1IF

TMR2IF

TMR1IF54

PIE1

SPPIE(2)

ADIE

RCIE

TXIE

SSPIE

CCP1IETMR2IETMR1IE54

IPR1

SPPIP(2)

ADIP

RCIP

TXIP

SSPIP

CCP1IP

TMR2IP

TMR1IP54

PIR2

OSCFIF

CMIF

USBIF

EEIF

BCLIF

HLVDIF

TMR3IF

CCP2IF54

PIE2

OSCFIE

CMIE

USBIE

EEIE

BCLIE

HLVDIETMR3IECCP2IE54

IPR2

OSCFIP

CMIP

USBIP

EEIP

BCLIP

HLVDIP

TMR3IP

CCP2IP54

TRISBTRISB7TRISB6TRISB5TRISB4

TRISB3

TRISB2

TRISB1TRISB054

TRISC

TRISC7

TRISC6———

TRISC2

TRISC1

TRISC054

TMR1L

Timer1 Register Low Byte

TMR1H

Timer1 Register High Byte

T1CON

RD16

T1RUN

Timer3 Register High Byte

TMR3L

Timer3 Register Low Byte
RD16

T3CCP252

T1CKPS1 T1CKPS0 T1OSCEN T1SYNC

TMR3H
T3CON

52
TMR1CS TMR1ON

52
53
53

T3CKPS1 T3CKPS0T3CCP1T3SYNCTMR3CS TMR3ON

53

CCPR1L

Capture/Compare/PWM Register 1 Low Byte

53

CCPR1H

Capture/Compare/PWM Register 1 High Byte

53

CCP1CON

P1M1(2)

CCPR2L

Capture/Compare/PWM Register 2 Low Byte

CCPR2H

Capture/Compare/PWM Register 2 High Byte

CCP2CON—

P1M0(2)

—

DC1B1

DC2B1

DC1B0

DC2B0

CCP1M3

CCP1M2

CCP1M1

CCP1M053
53
53

CCP2M3

CCP2M2CCP2M1CCP2M053

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Capture/Compare, Timer1 or Timer3.
Note 1: The SBOREN bit is only available when BOREN<1:0> = 01; otherwise, the bit reads as ‘0’.
2: These bits are unimplemented on 28-pin devices; always maintain these bits clear.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 145

PIC18F2455/2550/4455/4550
15.4

15.4.1PWM Mode

In Pulse-Width Modulation (PWM) mode, the CCPx pin
produces up to a 10-bit resolution PWM output. Since
the CCP2 pin is multiplexed with a PORTB or PORTC
data latch, the appropriate TRIS bit must be cleared tomake the CCP2 pin an output.
Note:

Clearing the CCP2CON register will force
the RB3 or RC1 output latch (depending
on device configuration) to the default low
level. This is not the PORTB or PORTC
I/O data latch.

Figure 15-3 shows a simplified block diagram of the
CCP module in PWM mode.
For a step-by-step procedure on how to set up the CCP
module for PWM operation, see Section 15.4.4“Setup for PWM Operation”.

FIGURE 15-3:

SIMPLIFIED PWM BLOCKDIAGRAMThe PWM period is specified by writing to the PR2
register. The PWM period can be calculated using thefollowing formula:

EQUATION 15-1:
PWM Period = [(PR2) + 1] • 4 • TOSC •(TMR2 Prescale Value)
PWM frequency is defined as 1/[PWM period].
When TMR2 is equal to PR2, the following three eventsoccur on the next increment cycle:• TMR2 is cleared• The CCPx pin is set (exception: if PWM duty
cycle = 0%, the CCPx pin will not be set)
• The PWM duty cycle is latched from CCPRxL into
CCPRxH
Note:

CCPxCON<5:4>

Duty Cycle Registers
CCPRxL

15.4.2

CCPRxH (Slave)

R

Comparator

Q
CCPx
Output(Note 1)

TMR2

SComparator
Clear Timer,
CCPx pin andlatch D.C.

PR2

Corresponding
TRIS bit

The Timer2 postscalers (see Section 13.0
“Timer2 Module”) are not used in thedetermination of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than
the PWM output.

PWM DUTY CYCLE

The PWM duty cycle is specified by writing to the
CCPRxL register and to the CCPxCON<5:4> bits. Up
to 10-bit resolution is available. The CCPRxL contains
the eight MSbs and the CCPxCON<5:4> bits containthe two LSbs. This 10-bit value is represented by
CCPRxL:CCPxCON<5:4>. The following equation isused to calculate the PWM duty cycle in time:

EQUATION 15-2:

Note 1: The 8-bit TMR2 value is concatenated with the 2-bit
internal Q clock, or 2 bits of the prescaler, to create the
10-bit time base.

A PWM output (Figure 15-4) has a time base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period(1/period).

FIGURE 15-4:

PWM PERIODPWM Duty Cycle = (CCPRXL:CCPXCON<5:4>) •TOSC • (TMR2 Prescale Value)
CCPRxL and CCPxCON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPRxH until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPRxH is a read-only register.

PWM OUTPUT
PeriodDuty Cycle
TMR2 = PR2
TMR2 = Duty Cycle
TMR2 = PR2

DS39632D-page 146

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
The CCPRxH register and a 2-bit internal latch areused to double-buffer the PWM duty cycle. This
double-buffering is essential for glitchless PWM
operation.

EQUATION 15-3:
F OSC
log ⎛ ---------------⎞⎝ F PWM⎠
PWM Resolution (max) = -----------------------------bitslog ( 2 )When the CCPRxH and 2-bit latch match TMR2,
concatenated with an internal 2-bit Q clock or 2 bits of
the TMR2 prescaler, the CCPx pin is cleared.

Note:

The maximum PWM resolution (bits) for a given PWM
frequency is given by the equation:

TABLE 15-4:

If the PWM duty cycle value is longer than
the PWM period, the CCPx pin will not becleared.

EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz

PWM Frequency

2.44 kHz

9.77 kHz39.06 kHz156.25 kHz

312.50 kHz

416.67 kHz

Timer Prescaler (1, 4, 16)

16

4

1

1

1

1

PR2 Value

FFh

FFh

FFh

3Fh

1Fh

17h

Maximum Resolution (bits)

10

10

10

8

7

6.58

15.4.315.4.4PWM AUTO-SHUTDOWN(CCP1 ONLY)

The PWM auto-shutdown features of the Enhanced CCP
module are also available to CCP1 in 28-pin devices. The
operation of this feature is discussed in detail in
Section 16.4.7 “Enhanced PWM Auto-Shutdown”.

The following steps should be taken when configuring
the CCP module for PWM operation:
1.
2.

Auto-shutdown features are not available for CCP2.
3.
4.
5.

© 2007 Microchip Technology Inc.

SETUP FOR PWM OPERATION

Preliminary

Set the PWM period by writing to the PR2
register.
Set the PWM duty cycle by writing to the
CCPRxL register and CCPxCON<5:4> bits.
Make the CCPx pin an output by clearing theappropriate TRIS bit.
Set the TMR2 prescale value, then enable
Timer2 by writing to T2CON.
Configure the CCPx module for PWM operation.

DS39632D-page 147

PIC18F2455/2550/4455/4550
TABLE 15-5:
Name
INTCONREGISTERS ASSOCIATED WITH PWM AND TIMER2
Bit 7

Bit 6

GIE/GIEH PEIE/GIEL
(1)

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset
Valueson page

TMR0IEINT0IERBIE

TMR0IF

INT0IF

RBIF

51

RCON

IPEN

SBOREN

—

RI

TO

PD

POR

BOR

52

PIR1

SPPIF(2)

ADIF

RCIF

TXIF

SSPIF

CCP1IF

TMR2IF

TMR1IF

54

PIE1

SPPIE

(2)

ADIE

RCIE

TXIE

SSPIE

CCP1IETMR2IETMR1IE54

IPR1

SPPIP(2)

ADIP

RCIP

TXIP

SSPIP

CCP1IP

TMR2IP

TMR1IP54

TRISBTRISB7TRISB6TRISB5TRISB4

TRISB3

TRISB2

TRISB1TRISB054

TRISC

TRISC7

TRISC6———

TRISC2

TRISC1

TRISC054

TMR2Timer2 Register

52

PR2

Timer2 Period Register

52

T2CON

—

T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON

CCPR1L

Capture/Compare/PWM Register 1 Low Byte

CCPR1H

Capture/Compare/PWM Register 1 High Byte

CCP1CON

P1M1(2)

P1M0(2)

DC1B1

DC1B0

T2CKPS1 T2CKPS0

52
53
53

CCP1M3

CCP1M2

CCP1M1

CCP1M053

CCPR2L

Capture/Compare/PWM Register 2 Low Byte

53

CCPR2H

Capture/Compare/PWM Register 2 High Byte

53

DC2B0

CCP2M3

CCP2M2CCP2M053

ECCP1AS

ECCPASE ECCPAS2 ECCPAS1 ECCPAS0PSSAC1PSSAC0 PSSBD1(2) PSSBD0(2)53

ECCP1DEL

PRSEN

PDC3(2)PDC2(2)53

CCP2CON——
PDC6(2)

DC2B1
PDC5(2)

PDC4(2)CCP2M1
PDC1(2)

PDC0(2)

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PWM or Timer2.
Note 1: The SBOREN bit is only available when BOREN<1:0> = 01; otherwise, the bit reads as ‘0’.
2: These bits are unimplemented on 28-pin devices; always maintain these bits clear.

DS39632D-page 148

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
16.0

ENHANCEDCAPTURE/COMPARE/PWM(ECCP) MODULE

Note:

The ECCP module is implemented only in
40/44-pin devices.

In PIC18F4455/4550 devices, CCP1 is implemented
as a standard CCP module with Enhanced PWM
capabilities. These include the provision for 2 or 4
output channels, user-selectable polarity, dead-band
control and automatic shutdown and restart. The

REGISTER 16-1:

Enhanced features are discussed in detail in
Section 16.4 “Enhanced PWM Mode”. Capture,
Compare and single output PWM functions of the
ECCP module are the same as described for the
standard CCP module.
The control register for the Enhanced CCP module isshown in Register 16-1. It differs from the CCPxCON
registers in PIC18F2255/2550 devices in that the two
Most Significant bits are implemented to control PWM
functionality.

CCP1CON: ECCP CONTROL REGISTER (40/44-PIN DEVICES)

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

P1M1

P1M0

DC1B1

DC1B0

CCP1M3

CCP1M2

CCP1M1

CCP1M0

bit 7

bit 0

Legend:R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’-n = Value at POR‘1’ = Bit is set‘0’ = Bit is clearedx = Bit is unknown

bit 7-6

P1M1:P1M0: Enhanced PWM Output Configuration bits
If CCP1M3:CCP1M2 = 00, 01, 10:
xx = P1A assigned as Capture/Compare input/output; P1B, P1C, P1D assigned as port pins
If CCP1M3:CCP1M2 = 11:
00 = Single output: P1A modulated; P1B, P1C, P1D assigned as port pins
01 = Full-bridge output forward: P1D modulated; P1A active; P1B, P1C inactive
10 = Half-bridge output: P1A, P1B modulated with dead-band control; P1C, P1D assigned as port pins
11 = Full-bridge output reverse: P1B modulated; P1C active; P1A, P1D inactive

bit 5-4

DC1B1:DC1B0: PWM Duty Cycle Bit 1 and Bit 0
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two LSbs of the 10-bit PWM duty cycle. The eight MSbs of the duty cycle are foundin CCPR1L.

bit 3-0

CCP1M3:CCP1M0: Enhanced CCP Mode Select bits
0000 = Capture/Compare/PWM off (resets ECCP module)
0001 = Reserved
0010 = Compare mode, toggle output on match
0011 = Capture mode
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode, initialize CCP1 pin low, set output on compare match (set CCP1IF)
1001 = Compare mode, initialize CCP1 pin high, clear output on compare match (set CCP1IF)
1010 = Compare mode, generate software interrupt only, CCP1 pin reverts to I/O state
1011 = Compare mode, trigger special event (CCP1 resets TMR1 or TMR3, sets CCP1IF bit)1100 = PWM mode: P1A, P1C active-high; P1B, P1D active-high1101 = PWM mode: P1A, P1C active-high; P1B, P1D active-low
1110 = PWM mode: P1A, P1C active-low; P1B, P1D active-high1111 = PWM mode: P1A, P1C active-low; P1B, P1D active-low© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 149

PIC18F2455/2550/4455/4550
In addition to the expanded range of modes available
through the CCP1CON register, the ECCP module has
two additional registers associated with Enhanced
PWM operation and auto-shutdown features. They are:
• ECCP1DEL (Dead-Band Delay)• ECCP1AS (Auto-Shutdown Configuration)

16.1

ECCP Outputs and Configuration

The Enhanced CCP module may have up to four PWM
outputs, depending on the selected operating mode.
These outputs, designated P1A through P1D, aremultiplexed with I/O pins on PORTC and PORTD. The
outputs that are active depend on the CCP operating
mode selected. The pin assignments are summarizedin Table 16-1.
To configure the I/O pins as PWM outputs, the proper
PWM mode must be selected by setting theP1M1:P1M0 and CCP1M3:CCP1M0 bits. The
appropriate TRISC and TRISD direction bits for the port
pins must also be set as outputs.

16.1.1

ECCP MODULES AND TIMERRESOURCES

16.2

Capture and Compare Modes

Except for the operation of the Special Event Trigger
discussed below, the Capture and Compare modes of
the ECCP module are identical in operation to that of
CCP. These are discussed in detail in Section 15.2
“Capture Mode” and Section 15.3 “CompareMode”.

16.2.1

SPECIAL EVENT TRIGGER

The Special Event Trigger output of ECCP resets the
TMR1 or TMR3 register pair, depending on which timer
resource is currently selected. This allows the
CCPR1H:CCPR1L registers to effectively be a 16-bit
programmable period register for Timer1 or Timer3.

16.3

Standard PWM Mode

When configured in Single Output mode, the ECCP
module functions identically to the standard CCP
module in PWM mode as described in Section 15.4
“PWM Mode”. This is also sometimes referred to as“Compatible CCP” mode, as in Table 16-1.
Note:

Like the standard CCP modules, the ECCP module canutilize Timers 1, 2 or 3, depending on the mode
selected. Timer1 and Timer3 are available for modules
in Capture or Compare modes, while Timer2 isavailable for modules in PWM mode. Interactions
between the standard and Enhanced CCP modules are
identical to those described for standard CCP modules.
Additional details on timer resources are provided in
Section 15.1.1“CCP
Modulesand
Timer
Resources”.

TABLE 16-1:

When setting up single output PWM
operations, users are free to use either ofthe processes described in Section 15.4.4“Setup for PWM Operation” orSection 16.4.9 “Setup for PWM Operation”. The latter is more generic but will
work for either single or multi-output PWM.

PIN ASSIGNMENTS FOR VARIOUS ECCP1 MODES

ECCP Mode

CCP1CON
Configuration

Compatible CCP

00xx 11xx

CCP1

Dual PWM

10xx 11xx

Quad PWM

x1xx 11xx

RC2

RD5

RD6

RD7

RD5/SPP5

RD6/SPP6

RD7/SPP7

P1A

P1B

RD6/SPP6

RD7/SPP7

P1A

P1B

P1C

P1D

All PIC18F4455/4550 devices:

Legend: x = Don’t care. Shaded cells indicate pin assignments not used by ECCP in a given mode.

DS39632D-page 150

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
16.4

16.4.1

Enhanced PWM Mode

The Enhanced PWM mode provides additional PWM
output options for a broader range of control applications. The module is a backward compatible version of
the standard CCP module and offers up to four outputs,
designated P1A through P1D. Users are also able toselect the polarity of the signal (either active-high or
active-low). The module’s output mode and polarity are
configured by setting the P1M1:P1M0 and
CCP1M3:CCP1M0 bits of the CCP1CON register.
Figure 16-1 shows a simplified block diagram of PWM
operation. All control registers are double-buffered andare loaded at the beginning of a new PWM cycle (theperiod boundary when Timer2 resets) in order toprevent glitches on any of the outputs. The exception is
the PWM Dead-Band Delay register, ECCP1DEL,
which is loaded at either the duty cycle boundary or theboundary period (whichever comes first). Because of
the buffering, the module waits until the assigned timer
resets instead of starting immediately. This means that
Enhanced PWM waveforms do not exactly match thestandard PWM waveforms, but are instead offset by
one full instruction cycle (4 TOSC).

PWM PERIODThe PWM period is specified by writing to the PR2
register. The PWM period can be calculated using thefollowing equation:

EQUATION 16-1:
PWM Period = [(PR2) + 1] • 4 • TOSC •(TMR2 Prescale Value)
PWM frequency is defined as 1/ [PWM period]. When
TMR2 is equal to PR2, the following three events occur
on the next increment cycle:• TMR2 is cleared• The CCP1 pin is set (if PWM duty cycle = 0%, the
CCP1 pin will not be set)
• The PWM duty cycle is copied from CCPR1L into
CCPR1HNote:

As before, the user must manually configure theappropriate TRIS bits for output.

FIGURE 16-1:

The Timer2 postscaler (see Section 13.0
“Timer2 Module”) is not used in thedetermination of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than
the PWM output.

SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODULE
CCP1CON<5:4>

Duty Cycle Registers

CCP1M3:CCP1M0

P1M1:P1M0
4

2

CCPR1LCCP1/P1A

CCP1/P1A
TRISD<4>

CCPR1H (Slave)

P1B
R

Comparator

Q

OutputController

P1B
TRISD<5>

P1C
TMR2(Note 1)P1D

Comparator

PR2

P1C
TRISD<6>

S

Clear Timer,
set CCP1 pin andlatch D.C.

P1D
TRISD<7>

ECCP1DEL

Note: The 8-bit TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler, to create the 10-bit timebase.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 151

PIC18F2455/2550/4455/4550
16.4.2PWM DUTY CYCLEEQUATION 16-3:

The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available. The CCPR1L contains
the eight MSbs and the CCP1CON<5:4> contains thetwo LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The PWM duty cycle iscalculated by the following equation.

log FOSCFPWM
PWM Resolution (max) =log(2)(

Note:

If the PWM duty cycle value is longer than
the PWM period, the CCP1 pin will not becleared.

16.4.3PWM OUTPUT CONFIGURATIONSEQUATION 16-2:
PWM Duty Cycle = (CCPR1L:CCP1CON<5:4> •TOSC • (TMR2 Prescale Value)
CCPR1L and CCP1CON<5:4> can be written to at any
time, but the duty cycle value is not copied into
CCPR1H until a match between PR2 and TMR2 occurs(i.e., the period is complete). In PWM mode, CCPR1H
is a read-only register.
The CCPR1H register and a 2-bit internal latch areused to double-buffer the PWM duty cycle. This
double-buffering is essential for glitchless PWM operation. When the CCPR1H and 2-bit latch match TMR2,
concatenated with an internal 2-bit Q clock or two bitsof the TMR2 prescaler, the CCP1 pin is cleared. The
maximum PWM resolution (bits) for a given PWM
frequency is given by the following equation.

TABLE 16-2:) bitsThe P1M1:P1M0 bits in the CCP1CON register allow
one of four configurations:• Single Output• Half-Bridge Output• Full-Bridge Output, Forward mode
• Full-Bridge Output, Reverse mode
The Single Output mode is the standard PWM mode
discussed in Section 16.4 “Enhanced PWM Mode”.
The Half-Bridge and Full-Bridge Output modes arecovered in detail in the sections that follow.
The general relationship of the outputs in all
configurations is summarized in Figure 16-2 andFigure 16-3.

EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz

PWM Frequency

2.44 kHz

9.77 kHz39.06 kHz156.25 kHz

312.50 kHz

416.67 kHz

Timer Prescaler (1, 4, 16)

16

4

1

1

1

1

PR2 Value

FFh

FFh

FFh

3Fh

1Fh

17h

Maximum Resolution (bits)

10

10

10

8

7

6.58

DS39632D-page 152

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
FIGURE 16-2:

PWM OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE)
000

CCP1CON<7:6>

SIGNAL(Single Output)

P1A Modulated

PR2 + 1

Duty
Cycle
PeriodDelay(1)Delay(1)P1A Modulated
10(Half-Bridge)

P1B Modulated
P1A Active

01(Full-Bridge,
Forward)P1B Inactive
P1C Inactive
P1D Modulated
P1A Inactive

11(Full-Bridge,
Reverse)P1B Modulated
P1C Active
P1D Inactive

FIGURE 16-3:

PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE)
000

CCP1CON<7:6>

SIGNAL(Single Output)

P1A Modulated

PR2 + 1

Duty
Cycle
PeriodP1A Modulated
10(Half-Bridge)

Delay(1)Delay(1)P1B Modulated
P1A Active

01(Full-Bridge,
Forward)P1B Inactive
P1C Inactive
P1D Modulated
P1A Inactive

11(Full-Bridge,
Reverse)P1B Modulated
P1C Active
P1D Inactive

Relationships:• Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value)• Duty Cycle = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value)• Delay = 4 * TOSC * (ECCP1DEL<6:0>)
Note 1: Dead-band delay is programmed using the ECCP1DEL register (Section 16.4.6 “Programmable Dead-Band Delay”).

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 153

PIC18F2455/2550/4455/4550
16.4.4

HALF-BRIDGE MODE

FIGURE 16-4:

In the Half-Bridge Output mode, two pins are used as
outputs to drive push-pull loads. The PWM output signal is output on the P1A pin, while the complementary
PWM output signal is output on the P1B pin(Figure 16-4). This mode can be used for half-bridge
applications, as shown in Figure 16-5, or for full-bridge
applications where four power switches are being
modulated with two PWM signals.

HALF-BRIDGE PWM
OUTPUT

PeriodPeriodDuty Cycle
P1A(2)td
td

P1B(2)In Half-Bridge Output mode, the programmabledead-band delay can be used to prevent shoot-throughcurrent in half-bridge power devices. The value of bits
PDC6:PDC0 sets the number of instruction cycles
before the output is driven active. If the value is greaterthan the duty cycle, the corresponding output remains
inactive during the entire cycle. See Section 16.4.6“Programmable Dead-Band Delay” for more detailsof the dead-band delay operations.

(1)

(1)

(1)

td = Dead-Band Delay
Note 1: At this time, the TMR2 register is equal to thePR2 register.
2: Output signals are shown as active-high.

Since the P1A and P1B outputs are multiplexed with
the PORTC<2> and PORTD<5> data latches, theTRISC<2> and TRISD<5> bits must be cleared toconfigure P1A and P1B as outputs.

FIGURE 16-5:

EXAMPLES OF HALF-BRIDGE OUTPUT MODE APPLICATIONSV+Standard Half-Bridge Circuit (“Push-Pull”)
PIC18FX455/X550

FET
Driver

+
V
-

P1A

Load
FET
Driver

+
V
-

P1B

V-

Half-Bridge Output Driving a Full-Bridge Circuit
V+
PIC18FX455/X550
FET
DriverFET
Driver

P1A

FET
DriverLoad

FET
Driver

P1B

V-

DS39632D-page 154

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
16.4.5

FULL-BRIDGE MODE

In Full-Bridge Output mode, four pins are used as
outputs; however, only two outputs are active at a time.
In the Forward mode, pin P1A is continuously active
and pin P1D is modulated. In the Reverse mode, pin
P1C is continuously active and pin P1B is modulated.
These are illustrated in Figure 16-6.

FIGURE 16-6:

P1A, P1B, P1C and P1D outputs are multiplexed with
the PORTC<2>, PORTD<5>, PORTD<6> andPORTD<7> data latches. The TRISC<2>, TRISD<5>,
TRISD<6> and TRISD<7> bits must be cleared tomake the P1A, P1B, P1C and P1D pins outputs.

FULL-BRIDGE PWM OUTPUT

Forward Mode
PeriodP1A(2)
Duty Cycle
P1B(2)

P1C(2)

P1D(2)(1)(1)
Reverse Mode
PeriodDuty Cycle
P1A(2)
P1B(2)
P1C(2)

P1D(2)(1)(1)

Note 1: At this time, the TMR2 register is equal to the PR2 register.
Note 2: Output signal is shown as active-high.

© 2007 Microchip Technology Inc.

Preliminary

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PIC18F2455/2550/4455/4550
FIGURE 16-7:

EXAMPLE OF FULL-BRIDGE APPLICATIONV+

PIC18FX455/X550

FET
Driver

QC

QA

FET
Driver

P1A

Load

P1B
FET
Driver

P1C

FET
Driver

QD

QB

VP1D

16.4.5.1

Direction Change in Full-Bridge ModeIn the Full-Bridge Output mode, the P1M1 bit in the
CCP1CON register allows the user to control theforward/reverse direction. When the application firmware changes this direction control bit, the module willassume the new direction on the next PWM cycle.
Just before the end of the current PWM period, themodulated outputs (P1B and P1D) are placed in theirinactive state, while the unmodulated outputs (P1A andP1C) are switched to drive in the opposite direction.
This occurs in a time interval of (4 TOSC * (Timer2
Prescale Value) before the next PWM period begins.
The Timer2 prescaler will be either 1, 4 or 16,
depending on the value of the T2CKPS1:T2CKPS0 bits
(T2CON<1:0>). During the interval from the switch of
the unmodulated outputs to the beginning of the next
period, the modulated outputs (P1B and P1D) remain
inactive. This relationship is shown in Figure 16-8.
Note that in the Full-Bridge Output mode, the ECCP
module does not provide any dead-band delay. In general, since only one output is modulated at all times,
dead-band delay is not required. However, there is asituation where a dead-band delay might be required.
This situation occurs when both of the following
conditions are true:
1.
2.

Figure 16-9 shows an example where the PWM direction changes from forward to reverse at a near 100%
duty cycle. At time t1, the outputs, P1A and P1D,
become inactive, while output P1C becomes active. In
this example, since the turn-off time of the powerdevices is longer than the turn-on time, a shoot-throughcurrent may flow through power devices, QC and QD,(see Figure 16-7) for the duration of ‘t’. The same
phenomenon will occur to power devices, QA and QB,
for PWM direction change from reverse to forward.
If changing PWM direction at high duty cycle is required
for an application, one of the following requirements
must be met:
1.
2.

Reduce PWM for a PWM period beforechanging directions.
Use switch drivers that can drive the switches off
faster than they can drive them on.

Other options to prevent shoot-through current may
exist.

The direction of the PWM output changes when
the duty cycle of the output is at or near 100%.
The turn-off time of the power switch, including
the power device and driver circuit, is greaterthan the turn-on time.

DS39632D-page 156

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
FIGURE 16-8:

PWM DIRECTION CHANGE
Period(1)

SIGNAL

PeriodP1A (Active-High)P1B (Active-High)DC
P1C (Active-High)(Note 2)P1D (Active-High)DC

Note 1: The direction bit in the CCP1 Control register (CCP1CON<7>) is written any time during the PWM cycle.
2: When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle at intervalsof 4 TOSC, 16 TOSC or 64 TOSC, depending on the Timer2 prescaler value. The modulated P1B and P1D signals
are inactive at this time.

FIGURE 16-9:

PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE
Forward Periodt1

Reverse Period

P1A(1)
P1B(1)DC

P1C(1)
P1D(1)

DCtON(2)

External Switch C(1)tOFF(3)External Switch D(1)t = tOFF – tON(2, 3)

Potential
Shoot-Through Current(1)Note 1: All signals are shown as active-high.
2: tON is the turn-on delay of power switch QC and its driver.
3: tOFF is the turn-off delay of power switch QD and its driver.

© 2007 Microchip Technology Inc.

Preliminary

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PIC18F2455/2550/4455/4550
16.4.6Note:

PROGRAMMABLE DEAD-BAND
DELAY
Programmable dead-band delay is not
implemented in 28-pin devices withstandard CCP modules.

In half-bridge applications where all power switches are
modulated at the PWM frequency at all times, the powerswitches normally require more time to turn off than toturn on. If both the upper and lower power switches are
switched at the same time (one turned on and the otherturned off), both switches may be on for a short period oftime until one switch completely turns off. During thisbrief interval, a very high current (shoot-through current)
may flow through both power switches, shorting thebridge supply. To avoid this potentially destructive
shoot-through current from flowing during switching,turning on either of the power switches is normallydelayed to allow the other switch to completely turn off.
In the Half-Bridge Output mode, a digitally programmable dead-band delay is available to avoid
shoot-through current from destroying the bridge
power switches. The delay occurs at the signal transition from the non-active state to the active state. See
Figure 16-4 for illustration. Bits PDC6:PDC0 of the
ECCP1DEL register (Register 16-2) set the delay
period in terms of microcontroller instruction cycles(TCY or 4 TOSC). These bits are not available on 28-pin
devices, as the standard CCP module does not support
half-bridge operation.

16.4.7ENHANCED PWM AUTO-SHUTDOWN

When ECCP is programmed for any of the Enhanced
PWM modes, the active output pins may be configured
for auto-shutdown. Auto-shutdown immediately places
the Enhanced PWM output pins into a defined shutdown
state when a shutdown event occurs.

REGISTER 16-2:

A shutdown event can be caused by either of thecomparator modules, a low level on theRB0/AN12/INT0/FLT0/SDI/SDA pin, or any combinationof these three sources. The comparators may be used tomonitor a voltage input proportional to a current being
monitored in the bridge circuit. If the voltage exceeds athreshold, the comparator switches state and triggers ashutdown. Alternatively, a digital signal on the INT0 pin
can also trigger a shutdown. The auto-shutdown feature
can be disabled by not selecting any auto-shutdown
sources. The auto-shutdown sources to be used are
selected using the ECCPAS2:ECCPAS0 bits (bits<6:4>of the ECCP1AS register).
When a shutdown occurs, the output pins are
asynchronously placed in their shutdown states,
specified
bythe
PSSAC1:PSSAC0andPSSBD1:PSSBD0 bits (ECCP1AS3:ECCP1AS0). Eachpin pair (P1A/P1C and P1B/P1D) may be set to drive
high, drive low or be tri-stated (not driving). The
ECCPASE bit (ECCP1AS<7>) is also set to hold theEnhanced PWM outputs in their shutdown states.
The ECCPASE bit is set by hardware when a shutdown
event occurs. If automatic restarts are not enabled, the
ECCPASE bit is cleared by firmware when the cause of
the shutdown clears. If automatic restarts are enabled,
the ECCPASE bit is automatically cleared when thecause of the auto-shutdown has cleared.
If the ECCPASE bit is set when a PWM period begins,
the PWM outputs remain in their shutdown state for thatentire PWM period. When the ECCPASE bit is cleared,
the PWM outputs will return to normal operation at the
beginning of the next PWM period.
Note:

Writing to the ECCPASE bit is disabled
while a shutdown condition is active.

ECCP1DEL: PWM DEAD-BAND DELAY REGISTER

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

PRSEN

PDC6(1)

PDC5(1)

PDC4(1)

PDC3(1)

PDC2(1)

PDC1(1)

PDC0(1)

bit 7

bit 0

Legend:R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’-n = Value at POR‘1’ = Bit is set‘0’ = Bit is clearedx = Bit is unknown

bit 7

PRSEN: PWM Restart Enable bit
1 = Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown event goes away;
the PWM restarts automatically
0 = Upon auto-shutdown, ECCPASE must be cleared in software to restart the PWM)

bit 6-0

PDC6:PDC0: PWM Delay Count bits(1)Delay time, in number of FOSC/4 (4 * TOSC) cycles, between the scheduled and actual time for a PWM
signal to transition to active.

Note 1:

Reserved on 28-pin devices; maintain these bits clear.

DS39632D-page 158

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
REGISTER 16-3:
R/W-0

ECCP1AS: ENHANCED CAPTURE/COMPARE/PWM AUTO-SHUTDOWNCONTROL REGISTER
R/W-0

ECCPASE

ECCPAS2

R/W-0
ECCPAS1

R/W-0
ECCPAS0

R/W-0
PSSAC1

R/W-0

R/W-0

R/W-0
(1)

PSSAC0PSSBD1PSSBD0(1)

bit 7

bit 0

Legend:R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’-n = Value at POR‘1’ = Bit is set‘0’ = Bit is clearedx = Bit is unknown

bit 7

ECCPASE: ECCP Auto-Shutdown Event Status bit
1 = A shutdown event has occurred; ECCP outputs are in shutdown state
0 = ECCP outputs are operating

bit 6-4

ECCPAS2:ECCPAS0: ECCP Auto-Shutdown Source Select bits
111 = FLT0 or Comparator 1 or Comparator 2
110 = FLT0 or Comparator 2
101 = FLT0 or Comparator 1
100 = FLT0011 = Either Comparator 1 or 2
010 = Comparator 2 output
001 = Comparator 1 output
000 = Auto-shutdown is disabled

bit 3-2

PSSAC1:PSSAC0: Pins A and C Shutdown State Control bits
1x = Pins A and C tri-state (40/44-pin devices)
01 = Drive Pins A and C to ‘1’00 = Drive Pins A and C to ‘0’

bit 1-0

PSSBD1:PSSBD0: Pins B and D Shutdown State Control bits(1)1x = Pins B and D tri-state
01 = Drive Pins B and D to ‘1’00 = Drive Pins B and D to ‘0’Note 1:

Reserved on 28-pin devices; maintain these bits clear.

© 2007 Microchip Technology Inc.

Preliminary

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PIC18F2455/2550/4455/4550
16.4.7.1

Auto-Shutdown and Auto-Restart

16.4.8The auto-shutdown feature can be configured to allow
automatic restarts of the module following a shutdown
event. This is enabled by setting the PRSEN bit of the
ECCP1DEL register (ECCP1DEL<7>).
In Shutdown mode with PRSEN = 1 (Figure 16-10), the
ECCPASE bit will remain set for as long as the causeof the shutdown continues. When the shutdown condition clears, the ECCP1ASE bit is cleared. If PRSEN = 0(Figure 16-11), once a shutdown condition occurs, the
ECCPASE bit will remain set until it is cleared byfirmware. Once ECCPASE is cleared, the Enhanced
PWM will resume at the beginning of the next PWM
period.
Note:

Writing to the ECCPASE bit is disabled
while a shutdown condition is active.

Independent of the PRSEN bit setting, if theauto-shutdown source is one of the comparators, theshutdown condition is a level. The ECCPASE bit
cannot be cleared as long as the cause of the shutdown
persists.
The Auto-Shutdown mode can be forced by writing a ‘1’
to the ECCPASE bit.

FIGURE 16-10:

START-UP CONSIDERATIONSWhen the ECCP module is used in the PWM mode, theapplication hardware must use the proper external pull-up
and/or pull-down resistors on the PWM output pins. Whenthe microcontroller is released from Reset, all of the I/O
pins are in the high-impedance state. The external circuits
must keep the power switch devices in the OFF state until
the microcontroller drives the I/O pins with the proper
signal levels or activates the PWM output(s).
The CCP1M1:CCP1M0 bits (CCP1CON<1:0>) allow
the user to choose whether the PWM output signals areactive-high or active-low for each pair of PWM output
pins (P1A/P1C and P1B/P1D). The PWM output
polarities must be selected before the PWM pins are
configured as outputs. Changing the polarity configuration while the PWM pins are configured as outputs is
not recommended, since it may result in damage to theapplication circuits.
The P1A, P1B, P1C and P1D output latches may not bein the proper states when the PWM module is initialized.
Enabling the PWM pins for output at the same time as
the ECCP module may cause damage to the application circuit. The ECCP module must be enabled in theproper output mode and complete a full PWM cycle
before configuring the PWM pins as outputs. The completion of a full PWM cycle is indicated by the TMR2IF
bit being set as the second PWM period begins.

PWM AUTO-SHUTDOWN (PRSEN = 1, AUTO-RESTART ENABLED)PWM Period

PWM Period

PWM Period

Dead Time

Dead Time

Dead Time

Duty Cycle

Duty Cycle

PWM Activity
Duty Cycle
Shutdown Event

ECCPASE bit

FIGURE 16-11:

PWM AUTO-SHUTDOWN (PRSEN = 0, AUTO-RESTART DISABLED)PWM Period

PWM Period

PWM Period

Dead Time

Dead Time

Dead Time

Duty Cycle

Duty Cycle

PWM Activity
Duty Cycle
Shutdown Event

ECCPASE bit
ECCPASE
Cleared by Firmware

DS39632D-page 160

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
16.4.9SETUP FOR PWM OPERATION

16.4.10

The following steps should be taken when configuring
the ECCP module for PWM operation:
1.

Configure the PWM pins, P1A and P1B (andP1C and P1D, if used), as inputs by setting thecorresponding TRIS bits.
2. Set the PWM period by loading the PR2 register.
3. If Auto-Shutdown is required do the following:• Disable Auto-Shutdown (ECCPASE = 0)
• Configure source (FLT0, Comparator 1 orComparator 2)• Wait for non-shutdown condition
4. Configure the ECCP module for the desired
PWM mode and configuration by loading the
CCP1CON register with the appropriate values:• Select one of the available output
configurations and direction with theP1M1:P1M0 bits.
• Select the polarities of the PWM output
signals with the CCP1M3:CCP1M0 bits.
5. Set the PWM duty cycle by loading the CCPR1L
register and CCP1CON<5:4> bits.
6. For Half-Bridge Output mode, set thedead-band delay by loading ECCP1DEL<6:0>with the appropriate value.
7. If auto-shutdown operation is required, load the
ECCP1AS register:• Select the auto-shutdown sources using the
ECCPAS2:ECCPAS0 bits.
• Select the shutdown states of the PWM
output pins using the PSSAC1:PSSAC0 and
PSSBD1:PSSBD0 bits.
• Set the ECCPASE bit (ECCP1AS<7>).
• Configure the comparators using the CMCON
register.
• Configure the comparator inputs as analog
inputs.
8. If auto-restart operation is required, set the
PRSEN bit (ECCP1DEL<7>).
9. Configure and start TMR2:• Clear the TMR2 interrupt flag bit by clearing
the TMR2IF bit (PIR1<1>).
• Set the TMR2 prescale value by loading theT2CKPS bits (T2CON<1:0>).
• Enable Timer2 by setting the TMR2ON bit(T2CON<2>).
10. Enable PWM outputs after a new PWM cycle
has started:• Wait until TMRn overflows (TMRnIF bit is set).
• Enable the CCP1/P1A, P1B, P1C and/or P1D
pin outputs by clearing the respective TRIS
bits.
• Clear the ECCPASE bit (ECCP1AS<7>).

© 2007 Microchip Technology Inc.

OPERATION IN POWER-MANAGED
MODES

In Sleep mode, all clock sources are disabled. Timer2
will not increment and the state of the module will notchange. If the ECCP pin is driving a value, it will continue
to drive that value. When the device wakes up, it willcontinue from this state. If Two-Speed Start-ups areenabled, the initial start-up frequency from INTOSC andthe postscaler may not be stable immediately.
In PRI_IDLE mode, the primary clock will continue toclock the ECCP module without change. In all otherpower-managed modes, the selected power-managed
mode clock will clock Timer2. Other power-managed
mode clocks will most likely be different than the
primary clock frequency.

16.4.10.1

Operation with Fail-Safe
Clock Monitor

If the Fail-Safe Clock Monitor is enabled, a clock failure
will force the device into the power-managed RC_RUN
mode and the OSCFIF bit (PIR2<7>) will be set. The
ECCP will then be clocked from the internal oscillator
clock source, which may have a different clock
frequency than the primary clock.
See the previous section for additional details.

16.4.11

EFFECTS OF A RESETBoth Power-on Reset and subsequent Resets will force
all ports to Input mode and the CCP registers to their
Reset states.
This forces the Enhanced CCP module to reset to astate compatible with the standard CCP module.

Preliminary

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PIC18F2455/2550/4455/4550
TABLE 16-3:
Name
INTCONREGISTERS ASSOCIATED WITH ECCP MODULE AND TIMER1 TO TIMER3
Bit 7

Bit 6

GIE/GIEH

PEIE/GIEL
(1)

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset
Valueson page

TMR0IEINT0IERBIE

TMR0IF

INT0IF

RBIF

51
52

RCON

IPEN

SBOREN

—

RI

TO

PD

POR

BOR

IPR1

SPPIP(2)

ADIP

RCIP

TXIP

SSPIP

CCP1IP

TMR2IP

TMR1IP54

PIR1

SPPIF(2)

ADIF

RCIF

TXIF

SSPIF

CCP1IF

TMR2IF

TMR1IF54

PIE1

SPPIE(2)

ADIE

RCIE

TXIE

SSPIE

CCP1IETMR2IETMR1IE54

IPR2

OSCFIP

CMIP

USBIP

EEIP

BCLIP

HLVDIP

TMR3IP

CCP2IP54

PIR2

OSCFIF

CMIF

USBIF

EEIF

BCLIF

HLVDIF

TMR3IF

CCP2IF54

PIE2

OSCFIE

CMIE

USBIE

EEIE

BCLIE

HLVDIETMR3IECCP2IE54

TRISB

TRISB7TRISB6TRISB5TRISB4

TRISB3

TRISB2

TRISB1TRISB0

54
54

TRISC

TRISC7

TRISC6———

TRISC2

TRISC1

TRISC0

TRISD(2)TRISD7

TRISD6

TRISD5

TRISD4

TRISD3

TRISD2

TRISD1

TRISD0

TMR1L

Timer1 Register Low Byte

52

TMR1H

Timer1 Register High Byte

52

T1CON
TMR2
T2CON

RD16

T1RUN

T1CKPS1T1CKPS0

T1OSCEN

T1SYNC

TMR1CS

TMR1ON

Timer2 Module Register—

T2OUTPS3

54

52
52

T2OUTPS2

T2OUTPS1

T2OUTPS0

TMR2ONT2CKPS1T2CKPS052

PR2Timer2 Period Register

52

TMR3L

Timer3 Register Low Byte

53

TMR3H

Timer3 Register High Byte

53

T3CON

RD16

T3CCP2T3CKPS1T3CKPS0

CCPR1L

Capture/Compare/PWM Register 1 (LSB)

CCPR1H

Capture/Compare/PWM Register 1 (MSB)

CCP1CON

P1M1(2)

P1M0(2)

DC1B1

T3CCP1T3SYNCTMR3CS

TMR3ON

53
53

DC1B0

53
CCP1M3

CCP1M2

CCP1M1

CCP1M0

53

(2)

(2)

ECCP1AS

ECCPASE

ECCPAS2

ECCPAS1

ECCPAS0PSSAC1PSSAC0PSSBD1PSSBD053

ECCP1DEL

PRSEN

PDC6(2)PDC5(2)

PDC4(2)

PDC3(2)PDC2(2)

PDC1(2)

PDC0(2)

53

Legend:Note 1:
2:— = unimplemented, read as ‘0’. Shaded cells are not used during ECCP operation.
The SBOREN bit is only available when BOREN<1:0> = 01; otherwise, the bit reads as ‘0’.
These bits or registers are unimplemented in 28-pin devices; always maintain these bits clear.

DS39632D-page 162

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
17.0

UNIVERSAL SERIAL BUS(USB)

The SIE can be interfaced directly to the USB, utilizing
the internal transceiver, or it can be connected throughan external transceiver. An internal 3.3V regulator isalso available to power the internal transceiver in 5V
applications.

This section describes the details of the USB
peripheral. Because of the very specific nature of themodule, knowledge of USB is expected. Somehigh-level USB information is provided in
Section 17.10 “Overview of USB” only for application
design reference. Designers are encouraged to refer tothe official specification published by the USB Implementers Forum (USB-IF) for the latest information.
USB Specification Revision 2.0 is the most current
specification at the time of publication of this document.

17.1

Some special hardware features have been included to
improve performance. Dual port memory in thedevice’s data memory space (USB RAM) has been
supplied to share direct memory access between the
microcontroller core and the SIE. Buffer descriptors arealso provided, allowing users to freely program endpoint memory usage within the USB RAM space. A
Streaming Parallel Port has been provided to support
the uninterrupted transfer of large volumes of data,such as isochronous data, to external memory buffers.

Overview of the USB Peripheral

Figure 17-1 presents a general overview of the USB
peripheral and its features.

The PIC18FX455/X550 device family contains afull-speed and low-speed compatible USB Serial Interface Engine (SIE) that allows fast communication
between any USB host and the PIC® microcontroller.

FIGURE 17-1:

USB PERIPHERAL AND OPTIONSPIC18FX455/X550 Family

3.3V Regulator
VREGEN

Optional
External
Pull-ups(2)

P
FSEN
UPUEN
UTRDISPInternal Pull-ups(Full
Speed)

TransceiverFS

USB Clock from theOscillator Module(Low
Speed)USB Bus

D+
D-

UOE

UOE(1)VM(1)
VP(1)
RCV(1)
VMO(1)VPO(1)USB Control andConfiguration
USB
SIE

External
Transceiver
USB Bus

SPP7:SPP0CK1SPPCK2SPPCSSPP
OESPP

1 KbyteUSB RAM

Note 1:

External 3.3V
Supply(3)

VUSB

EN

This signal is only available if the internal transceiver is disabled (UTRDIS = 1).

2:

The internal pull-up resistors should be disabled (UPUEN = 0) if external pull-up resistors are used.

3:

Do not enable the internal regulator when using an external 3.3V supply.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 163

PIC18F2455/2550/4455/4550
17.2

USB Status and Control

In addition, the USB Control register contains a status
bit, SE0 (UCON<5>), which is used to indicate theoccurrence of a single-ended zero on the bus. When
the USB module is enabled, this bit should be monitored to determine whether the differential data lines
have come out of a single-ended zero condition. This
helps to differentiate the initial power-up state from the
USB Reset signal.

The operation of the USB module is configured andmanaged through three control registers. In addition, a
total of 22 registers are used to manage the actual USB
transactions. The registers are:• USB Control register (UCON)• USB Configuration register (UCFG)• USB Transfer Status register (USTAT)• USB Device Address register (UADDR)• Frame Number registers (UFRMH:UFRML)• Endpoint Enable registers 0 through 15 (UEPn)

17.2.1The overall operation of the USB module is controlled
by the USBEN bit (UCON<3>). Setting this bit activatesthe module and resets all of the PPBI bits in the Buffer
Descriptor Table to ‘0’. This bit also activates the
on-chip voltage regulator and connects internal pull-up
resistors, if they are enabled. Thus, this bit can be used
as a soft attach/detach to the USB. Although all status
and control bits are ignored when this bit is clear, themodule needs to be fully preconfigured prior to setting
this bit.

USB CONTROL REGISTER (UCON)The USB Control register (Register 17-1) contains bits
needed to control the module behavior during transfers.
The register contains bits that control the following:• Main USB Peripheral Enable• Ping-Pong Buffer Pointer Reset• Control of the Suspend mode
• Packet Transfer Disable

REGISTER 17-1:

UCON: USB CONTROL REGISTER

U-0

R/W-0

R-x

R/C-0

R/W-0

R/W-0

R/W-0

U-0

—

PPBRSTSE0

PKTDISUSBEN

RESUMESUSPND

—

bit 7

bit 0

Legend:C = Clearable bit

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’-n = Value at POR‘1’ = Bit is set‘0’ = Bit is clearedx = Bit is unknown

bit 7

Unimplemented: Read as ‘0’

bit 6

PPBRST: Ping-Pong Buffers Reset bit
1 = Reset all Ping-Pong Buffer Pointers to the Even Buffer Descriptor (BD) banks
0 = Ping-Pong Buffer Pointers not being reset

bit 5

SE0: Live Single-Ended Zero Flag bit
1 = Single-ended zero active on the USB bus
0 = No single-ended zero detected

bit 4

PKTDIS: Packet Transfer Disable bit
1 = SIE token and packet processing disabled, automatically set when a SETUP token is received
0 = SIE token and packet processing enabled

bit 3

USBEN: USB Module Enable bit
1 = USB module and supporting circuitry enabled (device attached)
0 = USB module and supporting circuitry disabled (device detached)

bit 2

RESUME: Resume Signaling Enable bit
1 = Resume signaling activated
0 = Resume signaling disabled

bit 1

SUSPND: Suspend USB bit
1 = USB module and supporting circuitry in Power Conserve mode, SIE clock inactive
0 = USB module and supporting circuitry in normal operation, SIE clock clocked at the configured rate

bit 0

Unimplemented: Read as ‘0’DS39632D-page 164

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
The PPBRST bit (UCON<6>) controls the Reset statuswhen Double-Buffering mode (ping-pong buffering) isused. When the PPBRST bit is set, all Ping-Pong
Buffer Pointers are set to the Even buffers. PPBRST
has to be cleared by firmware. This bit is ignored inbuffering modes not using ping-pong buffering.
The PKTDIS bit (UCON<4>) is a flag indicating that the
SIE has disabled packet transmission and reception.
This bit is set by the SIE when a SETUP token is
received to allow setup processing. This bit cannot be
set by the microcontroller, only cleared; clearing it
allows the SIE to continue transmission and/or
reception. Any pending events within the Buffer
Descriptor Table will still be available, indicated within
the USTAT register’s FIFO buffer.
The RESUME bit (UCON<2>) allows the peripheral toperform a remote wake-up by executing Resume
signaling. To generate a valid remote wake-up,
firmware must set RESUME for 10 ms and then clear
the bit. For more information on Resume signaling, see
Sections 7.1.7.5, 11.4.4 and 11.9 in the USB 2.0
specification.
The SUSPND bit (UCON<1>) places the module andsupporting circuitry (i.e., voltage regulator) in a
low-power mode. The input clock to the SIE is also
disabled. This bit should be set by the software in
response to an IDLEIF interrupt. It should be reset by
the microcontroller firmware after an ACTVIF interrupt
is observed. When this bit is active, the device remains
attached to the bus but the transceiver outputs remain
Idle. The voltage on the VUSB pin may vary dependingon the value of this bit. Setting this bit before a IDLEIF
request will result in unpredictable bus behavior.
Note:

17.2.2

While in Suspend mode, a typical bus
powered USB device is limited to 500 μA
of current. This is the complete current
drawn by the PIC device and its supporting circuitry. Care should be taken toassure minimum current draw when thedevice enters Suspend mode.

USB CONFIGURATION REGISTER(UCFG)

Prior to communicating over USB, the module’s
associated internal and/or external hardware must be
configured. Most of the configuration is performed with
the UCFG register (Register 17-2). The separate USB
voltage regulator (see Section 17.2.2.8 “Internal
Regulator”) is controlled through the Configuration
registers.
The UFCG register contains most of the bits that
control the system level behavior of the USB module.
These include:

The UCFG register also contains two bits which aid inmodule testing, debugging and USB certifications.
These bits control output enable state monitoring andeye pattern generation.
Note:

17.2.2.1

Internal Transceiver

The USB peripheral has a built-in, USB 2.0, full-speed
and low-speed compliant transceiver, internally connected to the SIE. This feature is useful for low-costsingle chip applications. The UTRDIS bit (UCFG<3>)
controls the transceiver; it is enabled by default(UTRDIS = 0). The FSEN bit (UCFG<2>) controls thetransceiver speed; setting the bit enables full-speed
operation.
The on-chip USB pull-up resistors are controlled by the
UPUEN bit (UCFG<4>). They can only be selected
when the on-chip transceiver is enabled.
The USB specification requires 3.3V operation forcommunications; however, the rest of the chip may berunning at a higher voltage. Thus, the transceiver is
supplied power from a separate source, VUSB.

17.2.2.2

External TransceiverThis module provides support for use with an off-chiptransceiver. The off-chip transceiver is intended for
applications where physical conditions dictate the location of the transceiver to be away from the SIE. For
example, applications that require isolation from theUSB could use an external transceiver through someisolation to the microcontroller’s SIE (Figure 17-2).
External transceiver operation is enabled by setting the
UTRDIS bit.

FIGURE 17-2:

PIC®
Microcontroller

TYPICAL EXTERNAL
TRANSCEIVER WITH
ISOLATIONVDD Isolated
from USB

3.3V Derived
from USB

VDD
VUSB
VM
VP
RCV
VMO
VPO
UOE

Note:

• Bus Speed (full speed versus low speed)• On-Chip Pull-up Resistor Enable• On-Chip Transceiver Enable• Ping-Pong Buffer Usage© 2007 Microchip Technology Inc.

The USB speed, transceiver and pull-up
should only be configured during the module setup phase. It is not recommended toswitch these settings while the module isenabled.

Preliminary

1.5 kΩ
Isolation

TransceiverD+
D-

The above setting shows a simplified schematicfor a full-speed configuration using an externaltransceiver with isolation.

DS39632D-page 165

PIC18F2455/2550/4455/4550
REGISTER 17-2:

UCFG: USB CONFIGURATION REGISTER

R/W-0

R/W-0

U-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

UTEYE

UOEMON(1)—UPUEN(2,3)

UTRDIS(2)FSEN(2)

PPB1

PPB0

bit 7

bit 0

Legend:R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’-n = Value at POR‘1’ = Bit is set‘0’ = Bit is clearedx = Bit is unknown

bit 7

UTEYE: USB Eye Pattern Test Enable bit
1 = Eye pattern test enabled
0 = Eye pattern test disabled

bit 6

UOEMON: USB OE Monitor Enable bit(1)1 = UOE signal active; it indicates intervals during which the D+/D- lines are driving
0 = UOE signal inactive

bit 5

Unimplemented: Read as ‘0’

bit 4

UPUEN: USB On-Chip Pull-up Enable bit(2,3)
1 = On-chip pull-up enabled (pull-up on D+ with FSEN = 1 or D- with FSEN = 0)
0 = On-chip pull-up disabled

bit 3

UTRDIS: On-Chip Transceiver Disable bit(2)1 = On-chip transceiver disabled; digital transceiver interface enabled
0 = On-chip transceiver active

bit 2

FSEN: Full-Speed Enable bit(2)1 = Full-speed device: controls transceiver edge rates; requires input clock at 48 MHz
0 = Low-speed device: controls transceiver edge rates; requires input clock at 6 MHz

bit 1-0

PPB1:PPB0: Ping-Pong Buffers Configuration bits
11 = Even/Odd ping-pong buffers enabled for Endpoints 1 to 15
10 = Even/Odd ping-pong buffers enabled for all endpoints
01 = Even/Odd ping-pong buffer enabled for OUT Endpoint 000 = Even/Odd ping-pong buffers disabled

Note 1:
2:
3:

If UTRDIS is set, the UOE signal will be active independent of the UOEMON bit setting.
The UPUEN, UTRDIS and FSEN bits should never be changed while the USB module is enabled. These
values must be preconfigured prior to enabling the module.
This bit is only valid when the on-chip transceiver is active (UTRDIS = 0); otherwise, it is ignored.

There are 6 signals from the module to communicate
with and control an external transceiver:• VM: Input from the single-ended D- line
• VP: Input from the single-ended D+ line
• RCV: Input from the differential receiver• VMO: Output to the differential line driver• VPO: Output to the differential line driver• UOE: Output enable

DS39632D-page 166

The VPO and VMO signals are outputs from the SIE tothe external transceiver. The RCV signal is the output
from the external transceiver to the SIE; it represents
the differential signals from the serial bus translated
into a single pulse train. The VM and VP signals areused to report conditions on the serial bus to the SIE
that can’t be captured with the RCV signal. The
combinations of states of these signals and theirinterpretation are listed in Table 17-1 and Table 17-2.

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
TABLE 17-1:

DIFFERENTIAL OUTPUTS TO
TRANSCEIVER

VPO

VMO

Bus State00Single-Ended Zero01

Differential ‘0’10

Differential ‘1’11

Illegal Condition

TABLE 17-2:

17.2.2.5

Ping-Pong Buffer Configuration

The usage of ping-pong buffers is configured using the
PPB1:PPB0 bits. Refer to Section 17.4.4 “Ping-Pong
Buffering” for a complete explanation of the ping-pongbuffers.

17.2.2.6

USB Output Enable Monitor

The USB OE monitor provides indication as to whether
the SIE is listening to the bus or actively driving the bus.
This is enabled by default when using an externaltransceiver or when UCFG<6> = 1.

SINGLE-ENDED INPUTSFROM TRANSCEIVER

The USB OE monitoring is useful for initial system
debugging, as well as scope triggering during eyepattern generation tests.

VP

VM

Bus State00Single-Ended Zero0

1

Low Speed

17.2.2.7

An automatic eye pattern test can be generated by themodule when the UCFG<7> bit is set. The eye pattern
output will be observable based on module settings,
meaning that the user is first responsible for configuring
the SIE clock settings, pull-up resistor and Transceivermode. In addition, the module has to be enabled.

10High Speed

1

1

Error

The UOE signal toggles the state of the external transceiver. This line is pulled low by the device to enable
the transmission of data from the SIE to an external
device.

17.2.2.3

Internal Pull-up Resistors

The PIC18FX455/X550 devices have built-in pull-up
resistors designed to meet the requirements forlow-speed and full-speed USB. The UPUEN bit(UCFG<4>) enables the internal pull-ups. Figure 17-1
shows the pull-ups and their control.

17.2.2.4

External Pull-up Resistors

External pull-up may also be used. The VUSB pin may be
used to pull up D+ or D-. The pull-up resistor must be
1.5 kΩ (±5%) as required by the USB specifications.
Figure 17-3 shows an example.

FIGURE 17-3:

EXTERNAL CIRCUITRY

PIC®
Microcontroller

Host
Controller/HUB

Once UTEYE is set, the module emulates a switch froma receive to transmit state and will start transmitting a
J-K-J-K bit sequence (K-J-K-J for full speed). The
sequence will be repeated indefinitely while the Eye
Pattern Test mode is enabled.
Note that this bit should never be set while the module
is connected to an actual USB system. This test mode
is intended for board verification to aid with USB certification tests. It is intended to show a system developer
the noise integrity of the USB signals which can beaffected by board traces, impedance mismatches andproximity to other system components. It does notproperly test the transition from a receive to a transmit
state. Although the eye pattern is not meant to replace
the more complex USB certification test, it should aid
during first order system debugging.

17.2.2.8

Internal Regulator

The PIC18FX455/X550 devices have a built-in 3.3V regulator to provide power to the internal transceiver andprovide a source for the internal/external pull-ups. An
external 220 nF (±20%) capacitor is required for stability.

VUSB

Note:
1.5 kΩ
D+
D-

Note:

Eye Pattern Test Enable

The above setting shows a typical connection
for a full-speed configuration using an on-chip
regulator and an external pull-up resistor.

The drive from VUSB is sufficient to only
drive an external pull-up in addition to theinternal transceiver.

The regulator is enabled by default and can be disabledthrough the VREGEN Configuration bit. When enabled,
the voltage is visible on pin VUSB. When the regulator
is disabled, a 3.3V source must be provided throughthe VUSB pin for the internal transceiver. If the internaltransceiver is disabled, VUSB is not used.
Note 1: Do not enable the internal regulator if anexternal regulator is connected to VUSB.
2: VDD must be greater than VUSB at all
times, even with the regulator disabled.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 167

PIC18F2455/2550/4455/4550
17.2.3

USB STATUS REGISTER (USTAT)

Clearing the transfer complete flag bit, TRNIF, causes
the SIE to advance the FIFO. If the next data in the
FIFO holding register is valid, the SIE will immediately
reassert the interrupt. If no additional data is present,
TRNIF will remain clear; USTAT data will no longer be
reliable.

The USB Status register reports the transaction status
within the SIE. When the SIE issues a USB transfer
complete interrupt, USTAT should be read to determine
the status of the transfer. USTAT contains the transfer
endpoint number, direction and Ping-Pong Buffer
Pointer value (if used).
Note:

Note:

The data in the USB Status register is valid
only when the TRNIF interrupt flag isasserted.

The USTAT register is actually a read window into afour-byte status FIFO, maintained by the SIE. It allows
the microcontroller to process one transfer while the
SIE processes additional endpoints (Figure 17-4).
When the SIE completes using a buffer for reading or
writing data, it updates the USTAT register. If anotherUSB transfer is performed before a transaction
complete interrupt is serviced, the SIE will store thestatus of the next transfer into the status FIFO.

If an endpoint request is received while the
USTAT FIFO is full, the SIE willautomatically issue a NAK back to thehost.

FIGURE 17-4:

USTAT FIFOUSTAT from SIE

Clearing TRNIF
Advances FIFO

4-byte FIFO
for USTAT

Data BusREGISTER 17-3:
U-0

USTAT: USB STATUS REGISTER
R-x

—

ENDP3

R-x
ENDP2

R-x
ENDP1

R-x
ENDP0

R-x

R-x

U-0

DIR

PPBI(1)

—

bit 7

bit 0

Legend:R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’-n = Value at POR‘1’ = Bit is set‘0’ = Bit is cleared

bit 7

Unimplemented: Read as ‘0’

bit 6-3

ENDP3:ENDP0: Encoded Number of Last Endpoint Activity bits
(represents the number of the BDT updated by the last USB transfer)
1111 = Endpoint 151110 = Endpoint 14....
0001 = Endpoint 10000 = Endpoint 0

bit 2

DIR: Last BD Direction Indicator bit
1 = The last transaction was an IN token
0 = The last transaction was an OUT or SETUP token

bit 1

PPBI: Ping-Pong BD Pointer Indicator bit(1)1 = The last transaction was to the Odd BD bank
0 = The last transaction was to the Even BD bank

bit 0

Unimplemented: Read as ‘0’Note 1:x = Bit is unknown

This bit is only valid for endpoints with available Even and Odd BD registers.

DS39632D-page 168

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
17.2.4

USB ENDPOINT CONTROL

Each of the 16 possible bidirectional endpoints has its
own independent control register, UEPn (where ‘n’ represents the endpoint number). Each register has an
identical complement of control bits. The prototype isshown in Register 17-4.
The EPHSHK bit (UEPn<4>) controls handshaking forthe endpoint; setting this bit enables USB handshaking.
Typically, this bit is always set except when usingisochronous endpoints.
The EPCONDIS bit (UEPn<3>) is used to enable ordisable USB control operations (SETUP) through theendpoint. Clearing this bit enables SETUP transactions. Note that the corresponding EPINEN and
EPOUTEN bits must be set to enable IN and OUT

REGISTER 17-4:transactions. For Endpoint 0, this bit should always becleared since the USB specifications identify
Endpoint 0 as the default control endpoint.
The EPOUTEN bit (UEPn<2>) is used to enable or disable USB OUT transactions from the host. Setting thisbit enables OUT transactions. Similarly, the EPINEN bit(UEPn<1>) enables or disables USB IN transactions
from the host.
The EPSTALL bit (UEPn<0>) is used to indicate a
STALL condition for the endpoint. If a STALL is issued
on a particular endpoint, the EPSTALL bit for that endpoint pair will be set by the SIE. This bit remains set
until it is cleared through firmware, or until the SIE isreset.

UEPn: USB ENDPOINT n CONTROL REGISTER (UEP0 THROUGH UEP15)

U-0

U-0

U-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

—

—

—

EPHSHKEPCONDISEPOUTEN

EPINENEPSTALL(1)

bit 7

bit 0

Legend:R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’-n = Value at POR‘1’ = Bit is set‘0’ = Bit is clearedx = Bit is unknown

bit 7-5

Unimplemented: Read as ‘0’

bit 4

EPHSHK: Endpoint Handshake Enable bit
1 = Endpoint handshake enabled
0 = Endpoint handshake disabled (typically used for isochronous endpoints)

bit 3

EPCONDIS: Bidirectional Endpoint Control bit
If EPOUTEN = 1 and EPINEN = 1:
1 = Disable Endpoint n from control transfers; only IN and OUT transfers allowed
0 = Enable Endpoint n for control (SETUP) transfers; IN and OUT transfers also allowed

bit 2

EPOUTEN: Endpoint Output Enable bit
1 = Endpoint n output enabled
0 = Endpoint n output disabled

bit 1

EPINEN: Endpoint Input Enable bit
1 = Endpoint n input enabled
0 = Endpoint n input disabled

bit 0

EPSTALL: Endpoint Stall Enable bit(1)1 = Endpoint n is stalled
0 = Endpoint n is not stalled

Note 1:

Valid only if Endpoint n is enabled; otherwise, the bit is ignored.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 169

PIC18F2455/2550/4455/4550
17.2.5

USB ADDRESS REGISTER(UADDR)

FIGURE 17-5:

The USB Address register contains the unique USB
address that the peripheral will decode when active.
UADDR is reset to 00h when a USB Reset is received,
indicated by URSTIF, or when a Reset is received fromthe microcontroller. The USB address must be writtenby the microcontroller during the USB setup phase(enumeration) as part of the Microchip USB firmware
support.

17.2.617.3

000hBanks 0
to 3

User Data

Buffer Descriptors,
USB Data or User Data

USB FRAME NUMBER REGISTERS(UFRMH:UFRML)The Frame Number registers contain the 11-bit frame
number. The low-order byte is contained in UFRML,
while the three high-order bits are contained in
UFRMH. The register pair is updated with the current
frame number whenever a SOF token is received. For
the microcontroller, these registers are read-only. The
Frame Number register is primarily used forisochronous transfers.

IMPLEMENTATION OF
USB RAM IN DATAMEMORY SPACE

Banks 4
to 7

3FFh
400h
4FFh
500h

USB Data or
User Data(USB RAM)

7FFh
800h

USB RAM

USB data moves between the microcontroller core andthe SIE through a memory space known as the USB
RAM. This is a special dual port memory that is
mapped into the normal data memory space in Banks 4through 7 (400h to 7FFh) for a total of 1 Kbyte(Figure 17-5).
Bank 4 (400h through 4FFh) is used specifically for
endpoint buffer control, while Banks 5 through 7 areavailable for USB data. Depending on the type of
buffering being used, all but 8 bytes of Bank 4 may also
be available for use as USB buffer space.
Although USB RAM is available to the microcontroller
as data memory, the sections that are being accessedby the SIE should not be accessed by the
microcontroller. A semaphore mechanism is used todetermine the access to a particular buffer at any given
time. This is discussed in Section 17.4.1.1 “Buffer
Ownership”.

DS39632D-page 170

Preliminary

Banks 8
to 14

Bank15

Unused

SFRs

F00h
F60h
FFFh

© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
17.4

Buffer Descriptors and the Buffer
Descriptor Table

The registers in Bank 4 are used specifically for endpoint buffer control in a structure known as the Buffer
Descriptor Table (BDT). This provides a flexible method
for users to construct and control endpoint buffers ofvarious lengths and configuration.

FIGURE 17-6:
Address

The BDT is composed of Buffer Descriptors (BD) which
are used to define and control the actual buffers in the
USB RAM space. Each BD, in turn, consists of four registers, where n represents one of the 64 possible BDs(range of 0 to 63):
• BDnSTAT: BD Status register• BDnCNT: BD Byte Count register• BDnADRL: BD Address Low register• BDnADRH: BD Address High register

BD0STAT401h

BD0CNT40h

402h

BD0ADRL00h

403h

BD0ADRH

05h

Size of Block
Starting
Address500h

USB Data

BufferNote:

Depending on the buffering configuration used
(Section 17.4.4 “Ping-Pong Buffering”), there are up
to 32, 33 or 64 sets of buffer descriptors. At a minimum,
the BDT must be at least 8 bytes long. This is because
the USB specification mandates that every device musthave Endpoint 0 with both input and output for initial
setup. Depending on the endpoint and buffering
configuration, the BDT can be as long as 256 bytes.
Although they can be thought of as Special Function
Registers, the Buffer Descriptor Status and Address
registers are not hardware mapped, as conventional
microcontroller SFRs in Bank 15 are. If the endpoint corresponding to a particular BD is not enabled, its registers
are not used. Instead of appearing as unimplemented
addresses, however, they appear as available RAM.
Only when an endpoint is enabled by setting the
UEPn<1> bit does the memory at those addresses
become functional as BD registers. As with any addressin the data memory space, the BD registers have an
indeterminate value on any device Reset.
An example of a BD for a 64-byte buffer, starting at
500h, is shown in Figure 17-6. A particular set of BD
registers is only valid if the corresponding endpoint has
been enabled using the UEPn register. All BD registers
are available in USB RAM. The BD for each endpointshould be set up prior to enabling the endpoint.

BD STATUS AND CONFIGURATION

Buffer descriptors not only define the size of an endpoint buffer, but also determine its configuration andcontrol. Most of the configuration is done with the BD
Status register, BDnSTAT. Each BD has its own uniqueand correspondingly numbered BDnSTAT register.

© 2007 Microchip Technology Inc.

Contents

53Fh

BDs always occur as a four-byte block in the sequence,
BDnSTAT:BDnCNT:BDnADRL:BDnADRH. The addressof BDnSTAT is always an offset of (4n – 1) (in hexadecimal) from 400h, with n being the buffer descriptor
number.

17.4.1

Registers
(xxh)

400h
BufferDescriptor

EXAMPLE OF A BUFFER
DESCRIPTOR

Memory regions not to scale.

Unlike other control registers, the bit configuration for
the BDnSTAT register is context sensitive. There are
two distinct configurations, depending on whether the
microcontroller or the USB module is modifying the BD
and buffer at a particular time. Only three bit definitions
are shared between the two.

17.4.1.1

Buffer Ownership

Because the buffers and their BDs are shared between
the CPU and the USB module, a simple semaphoremechanism is used to distinguish which is allowed to
update the BD and associated buffers in memory.
This is done by using the UOWN bit (BDnSTAT<7>) asa semaphore to distinguish which is allowed to update
the BD and associated buffers in memory. UOWN is the
only bit that is shared between the two configurationsof BDnSTAT.
When UOWN is clear, the BD entry is “owned” by the
microcontroller core. When the UOWN bit is set, the BD
entry and the buffer memory are “owned” by the USB
peripheral. The core should not modify the BD or its
corresponding data buffer during this time. Note thatthe microcontroller core can still read BDnSTAT while
the SIE owns the buffer and vice versa.
The buffer descriptors have a different meaning basedon the source of the register update. Prior to placing
ownership with the USB peripheral, the user can configure the basic operation of the peripheral through the
BDnSTAT bits. During this time, the byte count andbuffer location registers can also be set.
When UOWN is set, the user can no longer depend on
the values that were written to the BDs. From this point,
the SIE updates the BDs as necessary, overwriting theoriginal BD values. The BDnSTAT register is updated
by the SIE with the token PID and the transfer count,
BDnCNT, is updated.

Preliminary

DS39632D-page 171

PIC18F2455/2550/4455/4550
The BDnSTAT byte of the BDT should always be thelast byte updated when preparing to arm an endpoint.
The SIE will clear the UOWN bit when a transaction
has completed. The only exception to this is when KEN
is enabled and/or BSTALL is enabled.
No hardware mechanism exists to block access when
the UOWN bit is set. Thus, unexpected behavior canoccur if the microcontroller attempts to modify memory
when the SIE owns it. Similarly, reading such memory
may produce inaccurate data until the USB peripheral
returns ownership to the microcontroller.

17.4.1.2

BDnSTAT Register (CPU Mode)

When UOWN = 0, the microcontroller core owns the
BD. At this point, the other seven bits of the registertake on control functions.
The Keep Enable bit, KEN (BDnSTAT<5>), determines
if a BD stays enabled. If the bit is set, once the UOWN
bit is set, it will remain owned by the SIE independentof the endpoint activity. This prevents the USTAT FIFO
from being updated, as well as the transaction
complete interrupt from being set for the endpoint. Thisfeature should only be enabled when the Streaming
Parallel Port is selected as the data I/O channel insteadof USB RAM.
The Address Increment Disable bit, INCDIS(BDnSTAT<4>), controls the SIE’s automatic addressincrement function. Setting INCDIS disables theauto-increment of the buffer address by the SIE foreach byte transmitted or received. This feature should
only be enabled when using the Streaming Parallel
Port, where each data byte is processed to or from thesame memory location.

the SIE. When enabled, it checks the data packet’s parity against the value of DTS (BDnSTAT<6>). If a packet
arrives with an incorrect synchronization, the data will
essentially be ignored. It will not be written to the USB
RAM and the USB transfer complete interrupt flag will
not be set. The SIE will send an ACK token back to thehost to Acknowledge receipt, however. The effects of
the DTSEN bit on the SIE are summarized inTable 17-3.
The Buffer Stall bit, BSTALL (BDnSTAT<2>), provides
support for control transfers, usually one-time stalls on
Endpoint 0. It also provides support for the
SET_FEATURE/CLEAR_FEATURE commands specified in Chapter 9 of the USB specification; typically,
continuous STALLs to any endpoint other than thedefault control endpoint.
The BSTALL bit enables buffer stalls. Setting BSTALL
causes the SIE to return a STALL token to the host if a
received token would use the BD in that location. The
EPSTALL bit in the corresponding UEPn control register is set and a STALL interrupt is generated when a
STALL is issued to the host. The UOWN bit remains set
and the BDs are not changed unless a SETUP token is
received. In this case, the STALL condition is cleared
and the ownership of the BD is returned to themicrocontroller core.
The BD9:BD8 bits (BDnSTAT<1:0>) store the two mostsignificant digits of the SIE byte count; the lower 8 digits
are stored in the corresponding BDnCNT register. See
Section 17.4.2 “BD Byte Count” for more
information.

The Data Toggle Sync Enable bit, DTSEN(BDnSTAT<3>), controls data toggle parity checking.
Setting DTSEN enables data toggle synchronization by

TABLE 17-3:

EFFECT OF DTSEN BIT ON ODD/EVEN (DATA0/DATA1) PACKET RECEPTIONOUT Packet
from Host

BDnSTAT Settings

Device Response after Receiving Packet

DTSEN

DTS

Handshake

UOWN

TRNIF

BDnSTAT and USTAT Status

1

0

ACK

0

1

Updated

DATA0
DATA1

1

0

ACK

1

0

Not Updated

DATA0

1

1

ACK

0

1

Updated

DATA1

1

1

ACK

1

0

Not Updated

Either

0

x

ACK

0

1

UpdatedEither, with error

x

x

NAK

1

0

Not Updated

Legend: x = don’t care

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REGISTER 17-5:

BDnSTAT: BUFFER DESCRIPTOR n STATUS REGISTER (BD0STAT THROUGH
BD63STAT), CPU MODE (DATA IS WRITTEN TO THE SIDE)

R/W-x

R/W-x

R/W-x

R/W-x

R/W-x

R/W-x

R/W-x

R/W-x

UOWN(1)

DTS(2)KEN

INCDISDTSEN

BSTALL

BC9

BC8

bit 7

bit 0

Legend:R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’-n = Value at POR‘1’ = Bit is set‘0’ = Bit is clearedx = Bit is unknown

bit 7

UOWN: USB Own bit(1)0 = The microcontroller core owns the BD and its corresponding buffer

bit 6

DTS: Data Toggle Synchronization bit(2)
1 = Data 1 packet
0 = Data 0 packet

bit 5

KEN: BD Keep Enable bit
1 = USB will keep the BD indefinitely once UOWN is set (required for SPP endpoint configuration)
0 = USB will hand back the BD once a token has been processed

bit 4

INCDIS: Address Increment Disable bit
1 = Address increment disabled (required for SPP endpoint configuration)
0 = Address increment enabledbit 3

DTSEN: Data Toggle Synchronization Enable bit
1 = Data toggle synchronization is enabled; data packets with incorrect Sync value will be ignored
except for a SETUP transaction, which is accepted even if the data toggle bits do not match
0 = No data toggle synchronization is performed

bit 2

BSTALL: Buffer Stall Enable bit
1 = Buffer stall enabled; STALL handshake issued if a token is received that would use the BD in thegiven location (UOWN bit remains set, BD value is unchanged)
0 = Buffer stall disabled

bit 1-0

BC9:BC8: Byte Count 9 and 8 bits
The byte count bits represent the number of bytes that will be transmitted for an IN token or received
during an OUT token. Together with BC<7:0>, the valid byte counts are 0-1023.

Note 1:
2:This bit must be initialized by the user to the desired value prior to enabling the USB module.
This bit is ignored unless DTSEN = 1.

© 2007 Microchip Technology Inc.

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17.4.1.3

BDnSTAT Register (SIE Mode)

When the BD and its buffer are owned by the SIE, mostof the bits in BDnSTAT take on a different meaning. The
configuration is shown in Register 17-6. Once UOWN
is set, any data or control settings previously written
there by the user will be overwritten with data from theSIE.
The BDnSTAT register is updated by the SIE with thetoken Packet Identifier (PID) which is stored in
BDnSTAT<5:3>. The transfer count in the corresponding BDnCNT register is updated. Values that overflow
the 8-bit register carry over to the two most significant
digits of the count, stored in BDnSTAT<1:0>.

17.4.2BD BYTE COUNTThe byte count represents the total number of bytes
that will be transmitted during an IN transfer. After an IN
transfer, the SIE will return the number of bytes sent to
the host.
For an OUT transfer, the byte count represents the
maximum number of bytes that can be received andstored in USB RAM. After an OUT transfer, the SIE will
return the actual number of bytes received. If thenumber of bytes received exceeds the corresponding
byte count, the data packet will be rejected and a NAK
handshake will be generated. When this happens, thebyte count will not be updated.

REGISTER 17-6:

The 10-bit byte count is distributed over two registers.
The lower 8 bits of the count reside in the BDnCNT
register. The upper two bits reside in BDnSTAT<1:0>.
This represents a valid byte range of 0 to 1023.

17.4.3

BD ADDRESS VALIDATIONThe BD Address register pair contains the starting RAM
address location for the corresponding endpoint buffer.
For an endpoint starting location to be valid, it must fallin the range of the USB RAM, 400h to 7FFh. No
mechanism is available in hardware to validate the BD
address.
If the value of the BD address does not point to an
address in the USB RAM, or if it points to an address
within another endpoint’s buffer, data is likely to be lostor overwritten. Similarly, overlapping a receive buffer(OUT endpoint) with a BD location in use can yield
unexpected
results.
WhendevelopingUSBapplications, the user may want to consider the
inclusion of software-based address validation in their
code.

BDnSTAT: BUFFER DESCRIPTOR n STATUS REGISTER (BD0STAT THROUGH
BD63STAT), SIE MODE (DATA RETURNED BY THE SIDE TO THE
MICROCONTROLLER)

R/W-x

U-x

R/W-x

R/W-x

R/W-x

R/W-x

R/W-x

R/W-x

UOWN

—

PID3

PID2

PID1

PID0

BC9

BC8

bit 7

bit 0

Legend:R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’-n = Value at POR‘1’ = Bit is set‘0’ = Bit is clearedx = Bit is unknown

bit 7

UOWN: USB Own bit
1 = The SIE owns the BD and its corresponding buffer

bit 6

Reserved: Not written by the SIE

bit 5-2

PID3:PID0: Packet Identifier bits
The received token PID value of the last transfer (IN, OUT or SETUP transactions only).

bit 1-0

BC9:BC8: Byte Count 9 and 8 bits
These bits are updated by the SIE to reflect the actual number of bytes received on an OUT transfer
and the actual number of bytes transmitted on an IN transfer.

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17.4.4

PING-PONG BUFFERING

the completion of a transaction (UOWN cleared by theSIE), the pointer is toggled to the Odd BD. After thecompletion of the next transaction, the pointer istoggled back to the Even BD and so on.

An endpoint is defined to have a ping-pong buffer when
it has two sets of BD entries: one set for an Eventransfer and one set for an Odd transfer. This allows the
CPU to process one BD while the SIE is processing theother BD. Double-buffering BDs in this way allows for
maximum throughput to/from the USB.

The Even/Odd status of the last transaction is stored in
the PPBI bit of the USTAT register. The user can reset
all Ping-Pong Pointers to Even using the PPBRST bit.
Figure 17-7 shows the four different modes ofoperation and how USB RAM is filled with the BDs.

The USB module supports four modes of operation:• No ping-pong support• Ping-pong buffer support for OUT Endpoint 0 only
• Ping-pong buffer support for all endpoints• Ping-pong buffer support for all other Endpoints
except Endpoint 0

BDs have a fixed relationship to a particular endpoint,depending on the buffering configuration. The mappingof BDs to endpoints is detailed in Table 17-4. This
relationship also means that gaps may occur in the
BDT if endpoints are not enabled contiguously. This
theoretically means that the BDs for disabled endpoints
could be used as buffer space. In practice, users
should avoid using such spaces in the BDT unless amethod of validating BD addresses is implemented.

The ping-pong buffer settings are configured using the
PPB1:PPB0 bits in the UCFG register.
The USB module keeps track of the Ping-Pong Pointerindividually for each endpoint. All pointers are initiallyreset to the Even BD when the module is enabled. After

FIGURE 17-7:

BUFFER DESCRIPTOR TABLE MAPPING FOR BUFFERING MODES

PPB1:PPB0 = 00
No Ping-Pong
Buffers
400h

PPB1:PPB0 = 10
Ping-Pong Buffers
on all EPs

PPB1:PPB0 = 01
Ping-Pong Buffer
on EP0 OUT
400h

EP0 OUT
Descriptor

400h
EP0 OUT Even
Descriptor

EP0 OUT Even
Descriptor

EP0 IN
Descriptor

EP0 OUT Odd
Descriptor

EP0 OUT Odd
Descriptor

EP0 IN
Descriptor

EP0 IN Even
Descriptor

EP1 OUT Even
Descriptor

EP0 IN Odd
Descriptor

EP1 OUT Odd
Descriptor

EP1 OUT Even
Descriptor

EP1 IN Even
Descriptor

EP1 OUT Odd
Descriptor

EP1 IN Odd
Descriptor

EP1 OUT
Descriptor

EP0 IN
Descriptor

EP1 IN
Descriptor

EP1 OUT
Descriptor
EP1 IN
Descriptor

EP15 IN
Descriptor

47Fh

PPB1:PPB0 = 11
Ping-Pong Buffers
on all other EPs
except EP0

Availableas
Data RAMEP1 IN Odd
Descriptor

Availableas
Data RAM

4FFh

Maximum Memory
Used: 128 bytes
Maximum BDs:
32 (BD0 to BD31)

Note:

Maximum Memory
Used: 132 bytes
Maximum BDs:
33 (BD0 to BD32)

EP15 IN Odd
Descriptor

4F7h
Availableas
Data RAM

EP15 IN Odd
Descriptor
4FFh

EP0 OUT
Descriptor

EP1 IN Even
Descriptor

EP15 IN
Descriptor

483h

400h

4FFh

4FFh
Maximum Memory
Used: 256 bytes
Maximum BDs: 6
4 (BD0 to BD63)

Maximum Memory
Used: 248 bytes
Maximum BDs:
62 (BD0 to BD61)

Memory area not shown to scale.

© 2007 Microchip Technology Inc.

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TABLE 17-4:

ASSIGNMENT OF BUFFER DESCRIPTORS FOR THE DIFFERENTBUFFERING MODES
BDs Assigned to Endpoint

Mode 0(No Ping-Pong)

Endpoint

Out

Mode 1(Ping-Pong on EP0 OUT)

In

Out

Mode 3(Ping-Pong on all other EPs,
except EP0)

Mode 2(Ping-Pong on all EPs)

In

Out

In

Out

In

0

0

1

0 (E), 1 (O)2

0 (E), 1 (O)

2 (E), 3 (O)

0

1

1

2

3

3

4

4 (E), 5 (O)

6 (E), 7 (O)

2 (E), 3 (O)

4 (E), 5 (O)

2

4

5

5

6

8 (E), 9 (O)

10 (E), 11 (O)

6 (E), 7 (O)

8 (E), 9 (O)

3

6

7

7

8

12 (E), 13 (O)

14 (E), 15 (O)

10 (E), 11 (O) 12 (E), 13 (O)

4

8

9

9

10

16 (E), 17 (O)

18 (E), 19 (O)14 (E), 15 (O) 16 (E), 17 (O)

5

10

11

11

12

20 (E), 21 (O)

22 (E), 23 (O)

18 (E), 19 (O) 20 (E), 21 (O)

6

12

13

13

14

24 (E), 25 (O)26 (E), 27 (O)

22 (E), 23 (O) 24 (E), 25 (O)

7

14

15

15

16

28 (E), 29 (O)30 (E), 31 (O) 26 (E), 27 (O) 28 (E), 29 (O)

8

16

17

17

18

32 (E), 33 (O)34 (E), 35 (O)

30 (E), 31 (O) 32 (E), 33 (O)

9

18

19

19

20

36 (E), 37 (O)38 (E), 39 (O)34 (E), 35 (O) 36 (E), 37 (O)

10

20

21

21

22

40 (E), 41 (O)

42 (E), 43 (O)38 (E), 39 (O) 40 (E), 41 (O)

11

22

23

23

24

44 (E), 45 (O)

46 (E), 47 (O)

42 (E), 43 (O) 44 (E), 45 (O)

12

24

25

25

26

48 (E), 49 (O)

50 (E), 51 (O)

46 (E), 47 (O) 48 (E), 49 (O)

13

26

27

27

28

52 (E), 53 (O)54 (E), 55 (O)

50 (E), 51 (O) 52 (E), 53 (O)

14

28

29

29

30

56 (E), 57 (O)58 (E), 59 (O)54 (E), 55 (O) 56 (E), 57 (O)

15

30

31

31

32

60 (E), 61 (O)62 (E), 63 (O)58 (E), 59 (O) 60 (E), 61 (O)Legend:(E) = Even transaction buffer, (O) = Odd transaction buffer

TABLE 17-5:

SUMMARY OF USB BUFFER DESCRIPTOR TABLE REGISTERS

Name
BDnSTAT(1)

BDnCNT(1)

3:
4:

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

UOWN

DTS(4)

PID3(2)

PID2(2)

PID1(2)

PID0(2)BC9BC8

KEN(3)INCDIS(3)DTSEN(3)

BSTALL(3)Byte Count
Buffer Address Low(1)

Buffer Address HighBDnADRH

2:

Bit 6

(1)

BDnADRL
Note 1:

Bit 7

For buffer descriptor registers, n may have a value of 0 to 63. For the sake of brevity, all 64 registers areshown as one generic prototype. All registers have indeterminate Reset values (xxxx xxxx).
Bits 5 through 2 of the BDnSTAT register are used by the SIE to return PID3:PID0 values once the register
is turned over to the SIE (UOWN bit is set). Once the registers have been under SIE control, the values
written for KEN, INCDIS, DTSEN and BSTALL are no longer valid.
Prior to turning the buffer descriptor over to the SIE (UOWN bit is cleared), bits 5 through 2 of the
BDnSTAT register are used to configure the KEN, INCDIS, DTSEN and BSTALL settings.
This bit is ignored unless DTSEN = 1.

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17.5

USB Interrupts

Figure 17-8 shows the interrupt logic for the USB
module. There are two layers of interrupt registers in
the USB module. The top level consists of overall USB
status interrupts; these are enabled and flagged in the
UIE and UIR registers, respectively. The second levelconsists of USB error conditions, which are enabled
and flagged in the UEIR and UEIE registers. Aninterrupt condition in any of these triggers a USB Error
Interrupt Flag (UERRIF) in the top level.

The USB module can generate multiple interrupt conditions. To accommodate all of these interrupt sources,
the module is provided with its own interrupt logic
structure, similar to that of the microcontroller. USB
interrupts are enabled with one set of control registers
and trapped with a separate set of flag registers. All
sources are funneled into a single USB interrupt
request, USBIF (PIR2<5>), in the microcontroller’sinterrupt logic.

FIGURE 17-8:

Interrupts may be used to trap routine events in a USB
transaction. Figure 17-9 shows some common events
within a USB frame and their corresponding interrupts.

USB INTERRUPT LOGIC FUNNEL
Second Level USB Interrupts(USB Error Conditions)

Top Level USB Interrupts(USB Status Interrupts)

UEIR (Flag) and UEIE (Enable) Registers

UIR (Flag) and UIE (Enable) Registers
SOFIF
SOFIE

BTSEF
BTSEE

TRNIF
TRNIE

BTOEF
BTOEE

USBIF

IDLEIF
IDLEIEDFN8EF
DFN8EEUERRIF
UERRIE

CRC16EF
CRC16EE

STALLIFSTALLIE

CRC5EF
CRC5EEPIDEF
PIDEE

ACTVIFACTVIEURSTIFURSTIEFIGURE 17-9:

EXAMPLE OF A USB TRANSACTION AND INTERRUPT EVENTS
From Host

From Host

To Host

SETUPToken

Data

ACK

From Host

To HostFrom Host

IN Token

Data

ACK

From Host

From Host

To HostOUT Token

Empty Data

ACK

USB Reset
URSTIFSTART-OF-FRAME
SOFIF

Set TRNIF

Set TRNIF

Set TRNIF

Transaction
Transaction
Complete
RESET

SOF

SETUP

DATA

SOF

STATUS

Differential Data
Control Transfer(1)1 ms Frame
Note

1:

The control transfer shown here is only an example showing events that can occur for every transaction. Typical control transfers
will spread across multiple frames.

© 2007 Microchip Technology Inc.

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17.5.1

USB INTERRUPT STATUS
REGISTER (UIR)

Once an interrupt bit has been set by the SIE, it must
be cleared by software by writing a ‘0’. The flag bits
can also be set in software which can aid in firmware
debugging.

The USB Interrupt Status register (Register 17-7) contains the flag bits for each of the USB status interrupt
sources. Each of these sources has a corresponding
interrupt enable bit in the UIE register. All of the USB
status flags are ORed together to generate the USBIF
interrupt flag for the microcontroller’s interrupt funnel.

REGISTER 17-7:

UIR: USB INTERRUPT STATUS REGISTER

U-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R-0

R/W-0

—

SOFIF

STALLIFIDLEIF(1)TRNIF(2)ACTVIF(3)UERRIF(4)URSTIF

bit 7

bit 0

Legend:R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’-n = Value at POR‘1’ = Bit is set‘0’ = Bit is clearedx = Bit is unknown

bit 7

Unimplemented: Read as ‘0’

bit 6

SOFIF: START-OF-FRAME Token Interrupt bit
1 = A START-OF-FRAME token received by the SIE
0 = No START-OF-FRAME token received by the SIE

bit 5

STALLIF: A STALL Handshake Interrupt bit
1 = A STALL handshake was sent by the SIE
0 = A STALL handshake has not been sent

bit 4

IDLEIF: Idle Detect Interrupt bit(1)1 = Idle condition detected (constant Idle state of 3 ms or more)
0 = No Idle condition detected

bit 3

TRNIF: Transaction Complete Interrupt bit(2)1 = Processing of pending transaction is complete; read USTAT register for endpoint information
0 = Processing of pending transaction is not complete or no transaction is pending

bit 2

ACTVIF: Bus Activity Detect Interrupt bit(3)1 = Activity on the D+/D- lines was detected
0 = No activity detected on the D+/D- lines

bit 1

UERRIF: USB Error Condition Interrupt bit(4)1 = An unmasked error condition has occurred
0 = No unmasked error condition has occurred.

bit 0

URSTIF: USB Reset Interrupt bit
1 = Valid USB Reset occurred; 00h is loaded into UADDR register
0 = No USB Reset has occurred

Note 1:2:
3:
4:

Once an Idle state is detected, the user may want to place the USB module in Suspend mode.
Clearing this bit will cause the USTAT FIFO to advance (valid only for IN, OUT and SETUP tokens).
This bit is typically unmasked only following the detection of a UIDLE interrupt event.
Only error conditions enabled through the UEIE register will set this bit. This bit is a status bit only andcannot be set or cleared by the user.

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17.5.1.1

Bus Activity Detect Interrupt Bit(ACTVIF)The ACTVIF bit cannot be cleared immediately after
the USB module wakes up from Suspend or while theUSB module is suspended. A few clock cycles are
required to synchronize the internal hardware statemachine before the ACTVIF bit can be cleared byfirmware. Clearing the ACTVIF bit before the internal

EXAMPLE 17-1:

hardware is synchronized may not have an effect on
the value of ACTVIF. Additionally, if the USB module
uses the clock from the 96 MHz PLL source, then after
clearing the SUSPND bit, the USB module may not be
immediately operational while waiting for the 96 MHz
PLL to lock. The application code should clear the
ACTVIF flag as shown in Example 17-1.

CLEARING ACTVIF BIT (UIR<2>)

Assembly:
BCF
LOOP:
BTFSS
BRA
BCF
BRA
DONE:

UCON, SUSPNDUIR, ACTVIF
DONE
UIR, ACTVIFLOOPC:
UCONbits.SUSPND = 0;
while (UIRbits.ACTVIF) { UIRbits.ACTVIF = 0; }© 2007 Microchip Technology Inc.

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17.5.2USB INTERRUPT ENABLE
REGISTER (UIE)The USB Interrupt Enable register (Register 17-8)
contains the enable bits for the USB status interrupt
sources. Setting any of these bits will enable therespective interrupt source in the UIR register.

REGISTER 17-8:

The values in this register only affect the propagationof an interrupt condition to the microcontroller’s interrupt logic. The flag bits are still set by their interrupt
conditions, allowing them to be polled and serviced
without actually generating an interrupt.

UIE: USB INTERRUPT ENABLE REGISTER

U-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

—

SOFIE

STALLIE

IDLEIETRNIEACTVIEUERRIEURSTIE

bit 7

bit 0

Legend:R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’-n = Value at POR‘1’ = Bit is set‘0’ = Bit is cleared

bit 7

Unimplemented: Read as ‘0’

bit 6

SOFIE: START-OF-FRAME Token Interrupt Enable bit
1 = START-OF-FRAME token interrupt enabled
0 = START-OF-FRAME token interrupt disabled

bit 5

STALLIE: STALL Handshake Interrupt Enable bit
1 = STALL interrupt enabled
0 = STALL interrupt disabled

bit 4

IDLEIE: Idle Detect Interrupt Enable bit
1 = Idle detect interrupt enabled
0 = Idle detect interrupt disabled

bit 3

TRNIE: Transaction Complete Interrupt Enable bit
1 = Transaction interrupt enabled
0 = Transaction interrupt disabled

bit 2

ACTVIE: Bus Activity Detect Interrupt Enable bit
1 = Bus activity detect interrupt enabled
0 = Bus activity detect interrupt disabled

bit 1

UERRIE: USB Error Interrupt Enable bit
1 = USB error interrupt enabled
0 = USB error interrupt disabled

bit 0

URSTIE: USB Reset Interrupt Enable bit
1 = USB Reset interrupt enabled
0 = USB Reset interrupt disabled

DS39632D-page 180

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x = Bit is unknown© 2007 Microchip Technology Inc.

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17.5.3

USB ERROR INTERRUPT STATUS
REGISTER (UEIR)The USB Error Interrupt Status register (Register 17-9)
contains the flag bits for each of the error sources
within the USB peripheral. Each of these sources iscontrolled by a corresponding interrupt enable bit in
the UEIE register. All of the USB error flags are ORed
together to generate the USB Error Interrupt Flag
(UERRIF) at the top level of the interrupt logic.

REGISTER 17-9:

Each error bit is set as soon as the error condition isdetected. Thus, the interrupt will typically notcorrespond with the end of a token being processed.
Once an interrupt bit has been set by the SIE, it must
be cleared by software by writing a ‘0’.

UEIR: USB ERROR INTERRUPT STATUS REGISTER

R/C-0

U-0

U-0

R/C-0

R/C-0

R/C-0

R/C-0

R/C-0

BTSEF

—

—

BTOEF

DFN8EF

CRC16EF

CRC5EF

PIDEF

bit 7

bit 0

Legend:R = Readable bit

C = Clearable bit

U = Unimplemented bit, read as ‘0’-n = Value at POR‘1’ = Bit is set‘0’ = Bit is clearedx = Bit is unknown

bit 7

BTSEF: Bit Stuff Error Flag bit
1 = A bit stuff error has been detected
0 = No bit stuff error

bit 6-5

Unimplemented: Read as ‘0’

bit 4

BTOEF: Bus Turnaround Time-out Error Flag bit
1 = Bus turnaround time-out has occurred (more than 16 bit times of Idle from previous EOP elapsed)
0 = No bus turnaround time-out

bit 3

DFN8EF: Data Field Size Error Flag bit
1 = The data field was not an integral number of bytes
0 = The data field was an integral number of bytes

bit 2

CRC16EF: CRC16 Failure Flag bit
1 = The CRC16 failed
0 = The CRC16 passed

bit 1

CRC5EF: CRC5 Host Error Flag bit
1 = The token packet was rejected due to a CRC5 error
0 = The token packet was accepted

bit 0

PIDEF: PID Check Failure Flag bit
1 = PID check failed
0 = PID check passed© 2007 Microchip Technology Inc.

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17.5.4

USB ERROR INTERRUPT ENABLE
REGISTER (UEIE)As with the UIE register, the enable bits only affect the
propagation of an interrupt condition to the microcontroller’s interrupt logic. The flag bits are still set by
their interrupt conditions, allowing them to be polled
and serviced without actually generating an interrupt.

The
USB
Error
Interrupt
Enableregister(Register 17-10) contains the enable bits for each of
the USB error interrupt sources. Setting any of thesebits will enable the respective error interrupt source inthe UEIR register to propagate into the UERR bit at
the top level of the interrupt logic.

REGISTER 17-10: UEIE: USB ERROR INTERRUPT ENABLE REGISTER
R/W-0

U-0

U-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

BTSEE

—

—

BTOEE

DFN8EE

CRC16EE

CRC5EE

PIDEE

bit 7

bit 0

Legend:R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’-n = Value at POR‘1’ = Bit is set‘0’ = Bit is cleared

bit 7

BTSEE: Bit Stuff Error Interrupt Enable bit
1 = Bit stuff error interrupt enabled
0 = Bit stuff error interrupt disabled

bit 6-5

Unimplemented: Read as ‘0’

bit 4

BTOEE: Bus Turnaround Time-out Error Interrupt Enable bit
1 = Bus turnaround time-out error interrupt enabled
0 = Bus turnaround time-out error interrupt disabled

bit 3

DFN8EE: Data Field Size Error Interrupt Enable bit
1 = Data field size error interrupt enabled
0 = Data field size error interrupt disabled

bit 2

CRC16EE: CRC16 Failure Interrupt Enable bit
1 = CRC16 failure interrupt enabled
0 = CRC16 failure interrupt disabled

bit 1

CRC5EE: CRC5 Host Error Interrupt Enable bit
1 = CRC5 host error interrupt enabled
0 = CRC5 host error interrupt disabled

bit 0

PIDEE: PID Check Failure Interrupt Enable bit
1 = PID check failure interrupt enabled
0 = PID check failure interrupt disabled

DS39632D-page 182

Preliminary

x = Bit is unknown© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
17.6

FIGURE 17-12:

USB Power Modes

Many USB applications will likely have several different
sets of power requirements and configuration. The
most common power modes encountered are Bus
Power Only, Self-Power Only and Dual Power with
Self-Power Dominance. The most common cases arepresented here.

DUAL POWER EXAMPLE

100 kΩ Attach Sense
I/O pin
VBUS
~5V

VDD

100 kΩ

17.6.1In Bus Power Only mode, all power for the application
is drawn from the USB (Figure 17-10). This iseffectively the simplest power method for the device.

FIGURE 17-10:

VSELF
~5V

VBUS
~5V

VDD

VUSB

17.7

VSS

In Self-Power Only mode, the USB application provides
its own power, with very little power being pulled fromthe USB. Figure 17-11 shows an example. Note that an
attach indication is added to indicate when the USB
has been connected.

SELF-POWER ONLY

Attach Sense
VBUS
~5V
VSELF
~5V

Streaming Parallel PortThis methodology presents design possibilities where
the microcontroller acts as a data manager, allowing
the SPP to pass large blocks of data without the microcontroller actually processing it. An application
example might include a data acquisition system,
where data is streamed from an external FIFO throughUSB to the host computer. In this case, endpoint
control is managed by the microcontroller and raw data
movement is processed externally.

VDDThe SPP is enabled as a USB endpoint port throughthe associated endpoint buffer descriptor. The endpoint
must be enabled as follows:

VUSB

1.
2.

VSS

3.

I/O pin100 kΩ

100 kΩ

Users should keep in mind the limits fordevices drawing power from the USB.
According to USB Specification 2.0, thiscannot exceed 100 mA per low-powerdevice or 500 mA per high-power device.

The Streaming Parallel Port (SPP) is an alternate route
option for data besides USB RAM. Using the SPP, an
endpoint can be configured to send data to or receive
data directly from external hardware.

SELF-POWER ONLY

FIGURE 17-11:

VSS

BUS POWER ONLY
Note:

17.6.2VUSB

BUS POWER ONLY

Set BDnADRL:BDnADRH to point to FFFFh.
Set the KEN bit (BDnSTAT<5>) to let SIE keep
control of the buffer.
Set the INCDIS bit (BDnSTAT<4>) to disable
automatic address increment.

Refer to Section 18.0 “Streaming Parallel Port” formore information about the SPP.

17.6.3

DUAL POWER WITH SELF-POWERDOMINANCE

Some applications may require a dual power option.
This allows the application to use internal power primarily, but switch to power from the USB when no internal
power is available. Figure 17-12 shows a simple DualPower with Self-Power Dominance example, which
automatically switches between Self-Power Only and
USB Bus Power Only modes.

© 2007 Microchip Technology Inc.

Note 1: If an endpoint is configured to use the
SPP, the SPP module must also be
configured to use the USB module.
Otherwise, unexpected operation may
occur.

Preliminary

2: In addition, if an endpoint is configured touse the SPP, the data transfer type of that
endpoint must be isochronous only.

DS39632D-page 183

PIC18F2455/2550/4455/4550
17.8

Oscillator

17.9

The USB module has specific clock requirements. For
full-speed operation, the clock source must be 48 MHz.
Even so, the microcontroller core and other peripherals
are not required to run at that clock speed or even fromthe same clock source. Available clocking options aredescribed in detail in Section 2.3 “Oscillator Settings
for USB”.

TABLE 17-6:
Name

USB Firmware and Drivers

Microchip provides a number of application specificresources, such as USB firmware and driver support.
Refer to www.microchip.com for the latest firmware anddriver support.

REGISTERS ASSOCIATED WITH USB MODULE OPERATION(1)
Bit 7

Bit 6

Bit 5

Bit 4

INTCON

GIE/GIEH

PEIE/GIEL

TMR0IEIPR2OSCFIP

CMIP

USBIP

Bit 1

Bit 0

Details on
page

Bit 3

Bit 2

INT0IERBIE

TMR0IF

INT0IF

RBIF

51

EEIP

BCLIP

HLVDIP

TMR3IP

CCP2IP54

PIR2

OSCFIF

CMIF

USBIF

EEIF

BCLIF

HLVDIF

TMR3IF

CCP2IF54

PIE2

OSCFIE

CMIE

USBIE

EEIE

BCLIE

HLVDIETMR3IECCP2IE

54
55

UCON

—

PPBRSTSE0

PKTDISUSBEN

RESUMESUSPND

—

UCFG

UTEYE

UOEMON—UPUENUTRDIS

FSEN

PPB1

PPB0

55

USTAT

—

ENDP3

ENDP2

ENDP1

ENDP0

DIR

PPBI

—

55

UADDR

—

ADDR6

ADDR5

ADDR4

ADDR3

ADDR2

ADDR1

ADDR0

55

UFRML

FRM7

FRM6

FRM5

FRM4

FRM3

FRM2

FRM1

FRM0

55

UFRMH

—

—

—

—

—

FRM10

FRM9

FRM8

55

UIR

—

SOFIF

STALLIFIDLEIFTRNIF

ACTVIF

UERRIFURSTIF

55

UIE

—

SOFIE

STALLIE

IDLEIETRNIEACTVIEUERRIEURSTIE

55

UEIR

BTSEF

—

—

BTOEF

DFN8EF

CRC16EF

CRC5EF

PIDEF

55

UEIE

BTSEE

—

—

BTOEE

DFN8EE

CRC16EE

CRC5EE

PIDEE

55

UEP0

—

—

—

EPHSHKEPCONDIS EPOUTEN

EPINENEPSTALL

55

UEP1

—

—

—

EPHSHKEPCONDIS EPOUTEN

EPINENEPSTALL

55

UEP2

—

—

—

EPHSHKEPCONDIS EPOUTEN

EPINENEPSTALL

55

UEP3

—

—

—

EPHSHKEPCONDIS EPOUTEN

EPINENEPSTALL

55

UEP4

—

—

—

EPHSHKEPCONDIS EPOUTEN

EPINENEPSTALL

55

UEP5

—

—

—

EPHSHKEPCONDIS EPOUTEN

EPINENEPSTALL

55

UEP6

—

—

—

EPHSHKEPCONDIS EPOUTEN

EPINENEPSTALL

55

UEP7

—

—

—

EPHSHKEPCONDIS EPOUTEN

EPINENEPSTALL

55

UEP8

—

—

—

EPHSHKEPCONDIS EPOUTEN

EPINENEPSTALL

55

UEP9

—

—

—

EPHSHKEPCONDIS EPOUTEN

EPINENEPSTALL

55

UEP10

—

—

—

EPHSHKEPCONDIS EPOUTEN

EPINENEPSTALL

55

UEP11

—

—

—

EPHSHKEPCONDIS EPOUTEN

EPINENEPSTALL

55

UEP12

—

—

—

EPHSHKEPCONDIS EPOUTEN

EPINENEPSTALL

55

UEP13

—

—

—

EPHSHKEPCONDIS EPOUTEN

EPINENEPSTALL

55

UEP14

—

—

—

EPHSHKEPCONDIS EPOUTEN

EPINENEPSTALL

55

UEP15

—

—

—

EPHSHKEPCONDIS EPOUTEN

EPINENEPSTALL

55

Legend:Note 1:— = unimplemented, read as ‘0’. Shaded cells are not used by the USB module.
This table includes only those hardware mapped SFRs located in Bank 15 of the data memory space. The Buffer
Descriptor registers, which are mapped into Bank 4 and are not true SFRs, are listed separately in Table 17-5.

DS39632D-page 184

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
17.10 Overview of USB

17.10.3

This section presents some of the basic USB concepts
and useful information necessary to design a USB
device. Although much information is provided in thissection, there is a plethora of information provided
within the USB specifications and class specifications.
Thus, the reader is encouraged to refer to the USB
specifications for more information (www.usb.org). If
you are very familiar with the details of USB, then thissection serves as a basic, high-level refresher of USB.

There are four transfer types defined in the USB
specification.

17.10.1

LAYERED FRAMEWORK

USB device functionality is structured into a layered
framework graphically shown in Figure 17-13. Eachlevel is associated with a functional level within thedevice. The highest layer, other than the device, is theconfiguration. A device may have multiple configurations. For example, a particular device may havemultiple power requirements based on Self-Power Onlyor Bus Power Only modes.
For each configuration, there may be multiple
interfaces. Each interface could support a particularmode of that configuration.
Below the interface is the endpoint(s). Data is directly
moved at this level. There can be as many as
16 bidirectional endpoints. Endpoint 0 is always acontrol endpoint and by default, when the device is on
the bus, Endpoint 0 must be available to configure thedevice.

17.10.2

TRANSFERS• Isochronous: This type provides a transfer
method for large amounts of data (up to1023 bytes) with timely delivery ensured;
however, the data integrity is not ensured. This isgood for streaming applications where small data
loss is not critical, such as audio.
• Bulk: This type of transfer method allows for large
amounts of data to be transferred with ensured
data integrity; however, the delivery timeliness is
not ensured.
• Interrupt: This type of transfer provides for
ensured timely delivery for small blocks of data,plus data integrity is ensured.
• Control: This type provides for device setup
control.
While full-speed devices support all transfer types,
low-speed devices are limited to interrupt and control
transfers only.

17.10.4

POWER

Power is available from the Universal Serial Bus. The
USB specification defines the bus power requirements.
Devices may either be self-powered or bus powered.
Self-powered devices draw power from an externalsource, while bus powered devices use power supplied
from the bus.

FRAMES

Information communicated on the bus is grouped into
1 ms time slots, referred to as frames. Each frame cancontain many transactions to various devices andendpoints. Figure 17-9 shows an example of atransaction within a frame.

FIGURE 17-13:

USB LAYERS
DeviceTo other Configurations (if any)

Configuration
To other Interfaces (if any)

Interface

Interface

Endpoint

Endpoint© 2007 Microchip Technology Inc.

Endpoint

Endpoint

Preliminary

Endpoint

DS39632D-page 185

PIC18F2455/2550/4455/4550
The USB specification limits the power taken from thebus. Each device is ensured 100 mA at approximately
5V (one unit load). Additional power may be requested,
up to a maximum of 500 mA. Note that power above
one unit load is a request and the host or hub is not
obligated to provide the extra current. Thus, a device
capable of consuming more than one unit load must beable to maintain a low-power configuration of a one unitload or less, if necessary.
The USB specification also defines a Suspend mode.
In this situation, current must be limited to 500 μA,
averaged over 1 second. A device must enter a
Suspend state after 3 ms of inactivity (i.e., no SOF
tokens for 3 ms). A device entering Suspend modemust drop current consumption within 10 ms after
Suspend. Likewise, when signaling a wake-up, thedevice must signal a wake-up within 10 ms of drawing
current above the Suspend limit.

17.10.5

ENUMERATION

When the device is initially attached to the bus, the hostenters an enumeration process in an attempt to identify
the device. Essentially, the host interrogates the device,gathering information such as power consumption, data
rates and sizes, protocol and other descriptive
information; descriptors contain this information. A
typical enumeration process would be as follows:
1.

2.
3.
4.
5.

6.
7.
8.

USB Reset: Reset the device. Thus, the device
is not configured and does not have an address(address 0).
Get Device Descriptor: The host requests a
small portion of the device descriptor.
USB Reset: Reset the device again.
Set Address: The host assigns an address to thedevice.
Get Device Descriptor: The host retrieves thedevice descriptor, gathering info such as
manufacturer, type of device, maximum control
packet size.
Get configuration descriptors.
Get any other descriptors.
Set a configuration.

The exact enumeration process depends on the host.

17.10.6

DESCRIPTORSThere are eight different standard descriptor types ofwhich five are most important for this device.

17.10.6.1

Device Descriptor

The device descriptor provides general information,such as manufacturer, product number, serial number,the class of the device and the number of configurations.
There is only one device descriptor.

DS39632D-page 18617.10.6.2

Configuration Descriptor

The configuration descriptor provides information on
the power requirements of the device and how manydifferent interfaces are supported when in this configuration. There may be more than one configuration for adevice (i.e., low-power and high-power configurations).

17.10.6.3

Interface Descriptor

The interface descriptor details the number of endpoints used in this interface, as well as the class of theinterface. There may be more than one interface for a
configuration.

17.10.6.4

Endpoint Descriptor

The endpoint descriptor identifies the transfer type
(Section 17.10.3 “Transfers”) and direction, as well
as some other specifics for the endpoint. There may be
many endpoints in a device and endpoints may beshared in different configurations.

17.10.6.5

String Descriptor

Many of the previous descriptors reference one ormore string descriptors. String descriptors provide
human readable information about the layer(Section 17.10.1 “Layered Framework”) theydescribe. Often these strings show up in the host to
help the user identify the device. String descriptors are
generally optional to save memory and are encoded ina unicode format.

17.10.7

BUS SPEED

Each USB device must indicate its bus presence andspeed to the host. This is accomplished through a
1.5 kΩ resistor which is connected to the bus at thetime of the attachment event.
Depending on the speed of the device, the resistor
either pulls up the D+ or D- line to 3.3V. For alow-speed device, the pull-up resistor is connected to
the D- line. For a full-speed device, the pull-up resistor
is connected to the D+ line.

17.10.8

CLASS SPECIFICATIONS AND
DRIVERSUSB specifications include class specifications which
operating system vendors optionally support.
Examples of classes include Audio, Mass Storage,
Communications and Human Interface (HID). In mostcases, a driver is required at the host side to ‘talk’ to theUSB device. In custom applications, a driver may need
to be developed. Fortunately, drivers are available formost common host systems for the most common
classes of devices. Thus, these drivers can be reused.

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
18.0

STREAMING PARALLEL PORTNote:

In addition, the SPP can provide time multiplexed
addressing information along with the data by using thesecond strobe output. Thus, the USB endpoint number
can be written in conjunction with the data for that
endpoint.

The Streaming Parallel Port is only
available on 40/44-pin devices.

PIC18F4455/4550 USB devices provide a Streaming
Parallel Port as a high-speed interface for moving data
to and from an external system. This parallel port
operates as a master port, complete with chip selectand clock outputs to control the movement of data toslave devices. Data can be channelled either directly to
the USB SIE or to the microprocessor core. Figure 18-1
shows a block view of the SPP data path.

FIGURE 18-1:

18.1

The operation of the SPP is controlled by two registers:
SPPCON and SPPCFG. The SPPCON register(Register 18-1) controls the overall operation of theparallel port and determines if it operates under USB or
microcontroller control. The SPPCFG register(Register 18-2) controls timing configuration and pin
outputs.

SPP DATA PATH
PIC18F4455/4550

18.1.1

USB
SIE

CPU

ENABLING THE SPP

To enable the SPP, set the SPPEN bit (SPPCON<0>).
In addition, the TRIS bits for the corresponding SPP
pins must be properly configured. At a minimum:

CK1SPPCK2SPP
OESPP
CSSPP

SPP
Logic

SPP Configuration• Bits TRISD<7:0> must be set (= 1)• Bits TRISE<2:1> must be cleared (= 0)
If CK1SPP is to be used:

SPP<7:0>• Bit TRISE<0> must be cleared (= 0)
If CSPP is to be used:• Bit TRISB<4> must be cleared (= 0)REGISTER 18-1:

SPPCON: SPP CONTROL REGISTER

U-0

U-0

U-0

U-0

U-0

U-0

R/W-0

R/W-0

—

—

—

—

—

—

SPPOWN

SPPEN

bit 7

bit 0

Legend:R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’-n = Value at POR‘1’ = Bit is set‘0’ = Bit is cleared

bit 7-2

Unimplemented: Read as ‘0’

bit 1

SPPOWN: SPP Ownership bit
1 = USB peripheral controls the SPP
0 = Microcontroller directly controls the SPP

bit 0

SPPEN: SPP Enable bit
1 = SPP is enabled
0 = SPP is disabled© 2007 Microchip Technology Inc.

Preliminary

x = Bit is unknown

DS39632D-page 187

PIC18F2455/2550/4455/4550
REGISTER 18-2:

SPPCFG: SPP CONFIGURATION REGISTER

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

CLKCFG1

CLKCFG0CSEN

CLK1EN

WS3

WS2

WS1

WS0

bit 7

bit 0

Legend:R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’-n = Value at POR‘1’ = Bit is set‘0’ = Bit is clearedx = Bit is unknown

bit 7-6

CLKCFG1:CLKCFG0: SPP Clock Configuration bits
1x = CLK1 toggles on read or write of an Odd endpoint address;
CLK2 toggles on read or write of an Even endpoint address
01 = CLK1 toggles on write; CLK2 toggles on read00 = CLK1 toggles only on endpoint address write; CLK2 toggles on data read or write

bit 5

CSEN: SPP Chip Select Pin Enable bit
1 = RB4 pin is controlled by the SPP module and functions as SPP CS output
0 = RB4 functions as a digital I/O port

bit 4

CLK1EN: SPP CLK1 Pin Enable bit
1 = RE0 pin is controlled by the SPP module and functions as SPP CLK1 output
0 = RE0 functions as a digital I/O port

bit 3-0

WS3:WS0: SPP Wait States bits
1111 = 30 additional wait states
1110 = 28 additional wait states••••
0001 = 2 additional wait states0000 = 0 additional wait states

18.1.2

CLOCKING DATA

18.1.3The SPP has four control outputs:

The SPP is designed with the capability of adding waitstates to read and write operations. This allows accessto parallel devices that require extra time for access.

• Two separate clock outputs (CK1SPP andCK2SPP)• Output enable (OESPP)• Chip select (CSSPP)
Together, they allow for several different configurations
for controlling the flow of data to slave devices. When
all control outputs are used, the three main options are:
• CLK1 clocks endpoint address information while
CLK2 clocks data
• CLK1 clocks write operations while CLK2 clocks
reads• CLK1 clocks Odd address data while CLK2 clocks
Even address data
Additional control options are derived by disabling the
CK1SPP and CSSPP outputs. These are enabled or
disabled with the CLK1EN and CSEN bits, respectively,
located in Register 18-2.

DS39632D-page 188

WAIT STATES

Wait state clocking is based on the data source clock.
If the SPP is configured to operate as a USB endpoint,then wait states are based on the USB clock. Likewise,
if the SPP is configured to operate from the microcontroller, then wait states are based on the instruction
rate (FOSC/4).
The WS3:WS0 bits set the wait states used by the SPP,
with a range of no wait states to 30 wait states, in multiples of two. The wait states are added symmetrically to
all transactions, with one-half added following each of thetwo clock cycles normally required for the transaction.
Figure 18-3 and Figure 18-4 show signalling examples
with 4 wait states added to each transaction.

18.1.4

SPP PULL-UPS

The SPP data lines (SPP<7:0>) are equipped withinternal pull-ups for applications that may leave the port
in a high-impedance condition. The pull-ups areenabled using the control bit, RDPU (PORTE<7>).

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
FIGURE 18-2:

TIMING FOR MICROCONTROLLER WRITE ADDRESS, WRITE DATA AND
READ DATA (NO WAIT STATES)FOSC/4OESPP
CSSPP
CK1SPPCK2SPPADDR

SPP<7:0>

Write Address
MOVWF SPPEPSFIGURE 18-3:

DATA

DATA

Write Data
MOVWF SPPDATA

Read Data
MOVF SPPDATA, W

TIMING FOR USB WRITE ADDRESS AND DATA (4 WAIT STATES)USB Clock
OESPP
CSSPP
CK1SPPCK2SPP
Write Address

SPP<7:0>

2 Wait States

FIGURE 18-4:

Write Data

2 Wait States

2 Wait States

2 Wait States

TIMING FOR USB WRITE ADDRESS AND READ DATA (4 WAIT STATES)USB Clock
OESPP
CSSPP
CK1SPPCK2SPPSPP<7:0>

Write Address

2 Wait States© 2007 Microchip Technology Inc.

Read Data

2 Wait States

2 Wait States

Preliminary

2 Wait States

DS39632D-page 189

PIC18F2455/2550/4455/4550
18.2

18.3.1

Setup for USB Control

When the SPP is configured for USB operation, data
can be clocked directly to and from the USB peripheral
without intervention of the microcontroller; thus, noprocess time is required. Data is clocked into or out
from the SPP with endpoint (address) information first,
followed by one or more bytes of data, as shown in
Figure 18-5. This is ideal for applications that requireisochronous, large volume data movement.
The following steps are required to set up the SPP for
USB control:
1.
2.
3.
4.
5.
6.

Configure the SPP as desired, including waitstates and clocks.
Set the SPPOWN bit for USB ownership.
Set the buffer descriptor starting address(BDnADRL:BDnADRH) to FFFFh.
Set the KEN bit (BDnSTAT<5>) so the buffer
descriptor is kept indefinitely by the SIE.
Set the INCDIS bit (BDnSTAT<4>) to disable
automatic buffer address increment.
Set the SPPEN bit to enable the module.
Note:

18.3

If a USB endpoint is configured to use the
SPP, the data transfer type of that
endpoint must be isochronous only.

Setup for Microcontroller Control

The SPP can also act as a parallel port for the
microcontroller. In this mode, the SPPEPS register(Register 18-3) provides status and address write
control. Data is written to and read from the SPPDATA
register. When the SPP is owned by the
microcontroller, the SPP clock is driven by the
instruction clock (FOSC/4).

When owned by the microcontroller core, control cangenerate an interrupt to notify the application wheneach read and write operation is completed. Theinterrupt flag bit is SPPIF (PIR1<7>) and is enabled by
the SPPIE bit (PIE1<7>). Like all other microcontroller
level interrupts, it can be set to a low or high priority.
This is done with the SPPIP bit (IPR1<7>).

18.3.2

2.
3.

The following is an example write sequence:
1.

Write the 4-bit address to the SPPEPS register.
The SPP automatically starts writing theaddress. If address write is not used, then skip
to step 3.
Monitor the SPPBUSY bit to determine when theaddress has been sent. The duration depends
on the wait states.
Write the data to the SPPDATA register. The
SPP automatically starts writing the data.
Monitor the SPPBUSY bit to determine when thedata has been sent. The duration depends on
the wait states.
Go back to steps 1 or 3 to write a new address
or data.

2.

3.
4.

5.

Note:

Configure the SPP as desired, including waitstates and clocks.
Clear the SPPOWN bit.
Set SPPEN to enable the module.

FIGURE 18-5:

WRITING TO THE SPP

Once configured, writing to the SPP is performed bywriting to the SPPEPS and SPPDATA registers. If the
SPP is configured to clock out endpoint address information with the data, writing to the SPPEPS register
initiates the address write cycle. Otherwise, the write isstarted by writing the data to the SPPDATA register.
The SPPBUSY bit indicates the status of the address
and the data write cycles.

The following steps are required to set up the SPP for
microcontroller operation:
1.

SPP INTERRUPTS

The SPPBUSY bit should be polled tomake certain that successive writes to the
SPPEPS or SPPDATA registers do not
overrun the wait time due to the wait statesetting.

TRANSFER OF DATA BETWEEN USB SIE AND SPP
Write USB endpoint number to SPP
Write outbound USB data to SPP orread inbound USB data from SPP

Endpoint
AddressDS39632D-page 190

Byte 0

Byte 1

Byte 2Byte 3Preliminary

Byte n© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
18.3.3READING FROM THE SPP

3.

Reading from the SPP involves reading the SPPDATA
register. Reading the register the first time initiates theread operation. When the read is finished, indicated by
the SPPBUSY bit, the SPPDATA will be loaded with thecurrent data.

4.

The following is an example read sequence:
1.

2.

5.

Write the 4-bit address to the SPPEPS register.
The SPP automatically starts writing theaddress. If address write is not used then skip to
step 3.
Monitor the SPPBUSY bit to determine when theaddress has been sent. The duration depends
on the wait states.

REGISTER 18-3:

Read the data from the SPPDATA register; thedata from the previous read operation isreturned. The SPP automatically starts the readcycle for the next read.
Monitor the SPPBUSY bit to determine when thedata has been read. The duration depends on
the wait states.
Go back to step 3 to read the current byte fromthe SPP and start the next read cycle.

SPPEPS: SPP ENDPOINT ADDRESS AND STATUS REGISTER

R-0

R-0

U-0

R-0

R/W-0

R/W-0

R/W-0

R/W-0

RDSPP

WRSPP

—

SPPBUSY

ADDR3

ADDR2

ADDR1

ADDR0

bit 7

bit 0

Legend:R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’-n = Value at POR‘1’ = Bit is set‘0’ = Bit is clearedx = Bit is unknown

bit 7

RDSPP: SPP Read Status bit (Valid when SPPCON<SPPOWN> = 1, USB)
1 = The last transaction was a read from the SPP
0 = The last transaction was not a read from the SPP

bit 6

WRSPP: SPP Write Status bit (Valid when SPPCON<SPPOWN> = 1, USB)
1 = The last transaction was a write to the SPP
0 = The last transaction was not a write to the SPP

bit 5

Unimplemented: Read as ‘0’

bit 4

SPPBUSY: SPP Handshaking Override bit
1 = The SPP is busy
0 = The SPP is ready to accept another read or write request

bit 3-0

ADDR3:ADDR0: SPP Endpoint Address bits
1111 = Endpoint Address 15
•
•
•
•
0001
0000 = Endpoint Address 0© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 191

PIC18F2455/2550/4455/4550
TABLE 18-1:
Name
SPPCON(3)(3)

SPPCFGSPPEPS(3)(3)

REGISTERS ASSOCIATED WITH THE STREAMING PARALLEL PORT
Bit 7

Bit 6

—

—

CLKCFG1 CLKCFG0

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset
Valueson page

—

—

—

—

SPPOWN

SPPEN

55

CSEN

CLK1EN

WS3

WS2

WS1

WS0

55

ADDR2

ADDR1

ADDR0

55

RDSPP

WRSPP

—

SPPBUSYADDR3SPPDATA

DATA7

DATA6

DATA5

DATA4

DATA3

DATA2

DATA1

DATA0

55

PIR1

SPPIF(3)

ADIF

RCIF

TXIF

SSPIF

CCP1IF

TMR2IF

TMR1IF54

PIE1

SPPIE(3)

ADIE

RCIE

TXIE

SSPIE

CCP1IETMR2IETMR1IE54

IPR1

SPPIP(3)

ADIP

RCIP

TXIP

SSPIP

CCP1IP

TMR2IP

TMR1IP

54

—

—

—

RE3(1,2)

RE2(3)

RE1(3)

RE0(3)

54

PORTE

(3)

RDPU

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for the Streaming Parallel Port.
Note 1: Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0).
2: RE3 is the only PORTE bit implemented on both 28-pin and 40/44-pin devices. All other bits are
implemented only when PORTE is implemented (i.e., 40/44-pin devices).
3: These registers and/or bits are unimplemented on 28-pin devices.

DS39632D-page 192

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
19.0

19.1

MASTER SYNCHRONOUS
SERIAL PORT (MSSP)MODULE

19.3

SPI Mode

The SPI mode allows 8 bits of data to be synchronouslytransmitted and received simultaneously. All fourmodes of the SPI are supported. To accomplish
communication, typically three pins are used:

Master SSP (MSSP) Module
Overview

The Master Synchronous Serial Port (MSSP) module isa serial interface, useful for communicating with otherperipheral or microcontroller devices. These peripheraldevices may be serial EEPROMs, shift registers,
display drivers, A/D converters, etc. The MSSP module
can operate in one of two modes:• Serial Peripheral Interface (SPI)• Inter-Integrated Circuit (I2C™)- Full Master mode
- Slave mode (with general address call)• Serial Data Out (SDO) – RC7/RX/DT/SDO• Serial Data In (SDI) – RB0/AN12/INT0/FLT0/SDI/SDA• Serial Clock (SCK) – RB1/AN10/INT1/SCK/SCL
Additionally, a fourth pin may be used when in a Slave
mode of operation:• Slave Select (SS) – RA5/AN4/SS/HLVDIN/C2OUT
Figure 19-1 shows the block diagram of the MSSP
module when operating in SPI mode.

FIGURE 19-1:

MSSP BLOCK DIAGRAM(SPI MODE)

The I2C interface supports the following modes in
hardware:

Internal
Data Bus• Master mode
• Multi-Master mode
• Slave mode

19.2

Read

Write
SSPBUF reg

Control Registers

The MSSP module has three associated control registers. These include a status register (SSPSTAT) andtwo control registers (SSPCON1 and SSPCON2). The
use of these registers and their individual Configuration
bits differ significantly depending on whether the MSSP
module is operated in SPI or I2C mode.

SSPSR reg
SDI

bit0

Shift
Clock

SDO

Additional details are provided under the individual
sections.

SS Control
EnableSS

Edge
Select2
Clock SelectSSPM3:SSPM0
SMP:CKE
4
TMR2 Output
2
2
Edge
SelectPrescaler TOSC
4, 16, 64

(

SCK

)

Data to TX/RX in SSPSR
TRIS bit
Note:© 2007 Microchip Technology Inc.

Preliminary

Only those pin functions relevant to SPI
operation are shown here.

DS39632D-page 193

PIC18F2455/2550/4455/4550
19.3.1REGISTERSSSPSR is the shift register used for shifting data in orout. SSPBUF is the buffer register to which data bytes
are written to or read from.

The MSSP module has four registers for SPI mode
operation. These are:

In receive operations, SSPSR and SSPBUF together
create a double-buffered receiver. When SSPSR
receives a complete byte, it is transferred to SSPBUF
and the SSPIF interrupt is set.

• MSSP Control Register 1 (SSPCON1)• MSSP Status Register (SSPSTAT)• Serial Receive/Transmit Buffer Register(SSPBUF)• MSSP Shift Register (SSPSR) – Not directly
accessible

During transmission, the SSPBUF is not doublebuffered. A write to SSPBUF will write to both SSPBUF
and SSPSR.

SSPCON1 and SSPSTAT are the control and status
registers in SPI mode operation. The SSPCON1
register is readable and writable. The lower six bits of
the SSPSTAT are read-only. The upper two bits of the
SSPSTAT are read/write.

REGISTER 19-1:

SSPSTAT: MSSP STATUS REGISTER (SPI MODE)

R/W-0

R/W-0

R-0

R-0

R-0

R-0

R-0

R-0

SMP

(1)

D/A

P

S

R/W

UA

BF

CKE

bit 7

bit 0

Legend:R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’-n = Value at POR‘1’ = Bit is set‘0’ = Bit is clearedx = Bit is unknown

bit 7

SMP: Sample bit
SPI Master mode:
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode.

bit 6

CKE: SPI Clock Select bit(1)1 = Transmit occurs on transition from active to Idle clock state
0 = Transmit occurs on transition from Idle to active clock state

bit 5

D/A: Data/Address bit
Used in I2C mode only.

bit 4

P: Stop bit
Used in I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.

bit 3

S: Start bit
Used in I2C mode only.

bit 2

R/W: Read/Write Information bit
Used in I2C mode only.

bit 1

UA: Update Address bit
Used in I2C mode only.

bit 0

BF: Buffer Full Status bit (Receive mode only)
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty

Note 1:

Polarity of clock state is set by the CKP bit (SSPCON1<4>).

DS39632D-page 194

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
REGISTER 19-2:
R/W-0

SSPCON1: MSSP CONTROL REGISTER 1 (SPI MODE)
R/W-0

WCOL

SSPOV

(1)

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

SSPEN

CKP

SSPM3

SSPM2

SSPM1

SSPM0

bit 7

bit 0

Legend:R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’-n = Value at POR‘1’ = Bit is set‘0’ = Bit is clearedx = Bit is unknown

bit 7

WCOL: Write Collision Detect bit (Transmit mode only)
1 = The SSPBUF register is written while it is still transmitting the previous word
(must be cleared in software)
0 = No collision

bit 6

SSPOV: Receive Overflow Indicator bit(1)SPI Slave mode:
1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user must read the
SSPBUF, even if only transmitting data, to avoid setting overflow (must be cleared in software).
0 = No overflow

bit 5

SSPEN: Master Synchronous Serial Port Enable bit
1 = Enables serial port and configures SCK, SDO, SDI and SS as serial port pins(2)0 = Disables serial port and configures these pins as I/O port pins(2)bit 4

CKP: Clock Polarity Select bit
1 = Idle state for clock is a high level
0 = Idle state for clock is a low levelbit 3-0

SSPM3:SSPM0: Master Synchronous Serial Port Mode Select bits
0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin(3)0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled(3)0011 = SPI Master mode, clock = TMR2 output/2(3)0010 = SPI Master mode, clock = FOSC/64(3)0001 = SPI Master mode, clock = FOSC/16(3)0000 = SPI Master mode, clock = FOSC/4(3)Note 1:2:
3:In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated bywriting to the SSPBUF register.
When enabled, these pins must be properly configured as input or output.
Bit combinations not specifically listed here are either reserved or implemented in I2C™ mode only.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 195

PIC18F2455/2550/4455/4550
19.3.2OPERATION

When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits (SSPCON1<5:0> and SSPSTAT<7:6>).
These control bits allow the following to be specified:• Master mode (SCK is the clock output)• Slave mode (SCK is the clock input)• Clock Polarity (Idle state of SCK)
• Data Input Sample Phase (middle or end of data
output time)• Clock Edge (output data on rising/falling edge of
SCK)• Clock Rate (Master mode only)• Slave Select mode (Slave mode only)
The MSSP module consists of a transmit/receive shift
register (SSPSR) and a buffer register (SSPBUF). The
SSPSR shifts the data in and out of the device, MSb
first. The SSPBUF holds the data that was written to the
SSPSR until the received data is ready. Once the eightbits of data have been received, that byte is moved to
the SSPBUF register. Then, the Buffer Full detect bit,
BF (SSPSTAT<0>) and the interrupt flag bit, SSPIF, areset. This double-buffering of the received data
(SSPBUF) allows the next byte to start reception before

EXAMPLE 19-1:
LOOP

reading the data that was just received. Any write to the
SSPBUF register during transmission/reception of data
will be ignored and the Write Collision detect bit, WCOL(SSPCON1<7>), will be set. User software must clear
the WCOL bit so that it can be determined if the following write(s) to the SSPBUF register completed
successfully.
When the application software is expecting to receive
valid data, the SSPBUF should be read before the next
byte of data to transfer is written to the SSPBUF. The
Buffer Full bit, BF (SSPSTAT<0>), indicates when
SSPBUF has been loaded with the received data
(transmission is complete). When the SSPBUF is read,the BF bit is cleared. This data may be irrelevant if the
SPI is only a transmitter. Generally, the MSSP interrupt
is used to determine when the transmission/reception
has completed. If the interrupt method is not going to
be used, then software polling can be done to ensurethat a write collision does not occur. Example 19-1
shows the loading of the SSPBUF (SSPSR) for datatransmission.
The SSPSR is not directly readable or writable and can
only be accessed by addressing the SSPBUF register.
Additionally, the MSSP Status register (SSPSTAT)
indicates the various status conditions.

LOADING THE SSPBUF (SSPSR) REGISTER

BTFSS
BRA
MOVF

SSPSTAT, BF
LOOPSSPBUF, W;Has data been received (transmit complete)?
;No;WREG reg = contents of SSPBUF

MOVWF

RXDATA;Save in user RAM, if data is meaningful

MOVF
MOVWF

TXDATA, W
SSPBUF;W reg = contents of TXDATA;New data to xmit

DS39632D-page 196

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
19.3.3ENABLING SPI I/O

19.3.4

To enable the serial port, MSSP Enable bit, SSPEN(SSPCON1<5>), must be set. To reset or reconfigure
SPI mode, clear the SSPEN bit, reinitialize the SSPCON
registers and then set the SSPEN bit. This configures
the SDI, SDO, SCK and SS pins as serial port pins. For
the pins to behave as the serial port function, some musthave their data direction bits (in the TRIS register)
appropriately programmed as follows:• SDI is automatically controlled by the SPI module• SDO must have TRISC<7> bit cleared• SCK (Master mode) must have TRISB<1> bitcleared• SCK (Slave mode) must have TRISB<1> bit set• SS must have TRISA<5> bit set

TYPICAL CONNECTION

Figure 19-2 shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCK signal.
Data is shifted out of both shift registers on theirprogrammed clock edge and latched on the opposite
edge of the clock. Both processors should be programmed to the same Clock Polarity (CKP), then bothcontrollers would send and receive data at the sametime. Whether the data is meaningful (or dummy data)
depends on the application software. This leads tothree scenarios for data transmission:• Master sends data – Slave sends dummy data
• Master sends data – Slave sends data
• Master sends dummy data – Slave sends data

Any serial port function that is not desired may beoverridden by programming the corresponding data
direction (TRIS) register to the opposite value.

FIGURE 19-2:

SPI MASTER/SLAVE CONNECTION

SPI Master SSPM3:SSPM0 = 00xxb

SPI Slave SSPM3:SSPM0 = 010xb
SDO

SDI

Serial Input Buffer(SSPBUF)

SDI

Shift Register(SSPSR)
MSb

Serial Input Buffer(SSPBUF)

SDO

LSb

MSb
SCK

Serial Clock

PROCESSOR 1© 2007 Microchip Technology Inc.

Shift Register(SSPSR)LSb

SCK
PROCESSOR 2

Preliminary

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PIC18F2455/2550/4455/4550
19.3.5

MASTER MODE

The master can initiate the data transfer at any time
because it controls the SCK. The master determines
when the slave (Processor 2, Figure 19-2) is tobroadcast data by the software protocol.
In Master mode, the data is transmitted/received assoon as the SSPBUF register is written to. If the SPI isonly going to receive, the SDO output could be disabled (programmed as an input). The SSPSR register
will continue to shift in the signal present on the SDI pin
at the programmed clock rate. As each byte isreceived, it will be loaded into the SSPBUF register as
if a normal received byte (interrupts and status bits
appropriately set). This could be useful in receiverapplications as a “Line Activity Monitor” mode.

FIGURE 19-3:

The clock polarity is selected by appropriately
programming the CKP bit (SSPCON1<4>). This then,would give waveforms for SPI communication asshown in Figure 19-3, Figure 19-5 and Figure 19-6,
where the MSB is transmitted first. In Master mode, theSPI clock rate (bit rate) is user programmable to be oneof the following:• FOSC/4 (or TCY)
• FOSC/16 (or 4 • TCY)
• FOSC/64 (or 16 • TCY)
• Timer2 output/2
This allows a maximum data rate (at 48 MHz) of
2.00 Mbps.
Figure 19-3 shows the waveforms for Master mode.
When the CKE bit is set, the SDO data is valid before
there is a clock edge on SCK. The change of the input
sample is shown based on the state of the SMP bit. The
time when the SSPBUF is loaded with the received
data is shown.

SPI MODE WAVEFORM (MASTER MODE)

Write toSSPBUFSCK(CKP = 0
CKE = 0)SCK(CKP = 1
CKE = 0)

4 Clock
Modes

SCK(CKP = 0
CKE = 1)SCK(CKP = 1
CKE = 1)SDO
(CKE = 0)

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

SDO
(CKE = 1)

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

SDI
(SMP = 0)

bit 0

bit 7

Input
Sample(SMP = 0)
SDI(SMP = 1)

bit 0

bit 7

Input
Sample(SMP = 1)
SSPIF
Next Q4 Cycle
after Q2↓SSPSR toSSPBUFDS39632D-page 198

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
19.3.6SLAVE MODE

In Slave mode, the data is transmitted and received as
the external clock pulses appear on SCK. When thelast bit is latched, the SSPIF interrupt flag bit is set.
While in Slave mode, the external clock is supplied by
the external clock source on the SCK pin. This external
clock must meet the minimum high and low times as
specified in the electrical specifications.
While in Sleep mode, the slave can transmit/receive
data. When a byte is received, the device can be configured to wake-up from Sleep.

19.3.7SLAVE SELECTSYNCHRONIZATIONThe SS pin allows a Synchronous Slave mode. The
SPI must be in Slave mode with the SS pin control
enabled (SSPCON1<3:0> = 04h). When the SS pin is
low, transmission and reception are enabled and the
SDO pin is driven. When the SS pin goes high, theSDO pin is no longer driven, even if in the middle of a

FIGURE 19-4:transmitted byte and becomes a floating output. External pull-up/pull-down resistors may be desirable
depending on the application.
Note 1: When the SPI module is in Slave mode
pin
controlenabledwith
SS(SSPCON1<3:0> = 0100), the SPI module
will reset if the SS pin is set to VDD.
2: If the SPI is used in Slave mode with CKE
set, then the SS pin control must be
enabled.
When the SPI module resets, the bit counter is forced
to ‘0’. This can be done by either forcing the SS pin toa high level or clearing the SSPEN bit.
To emulate two-wire communication, the SDO pin canbe connected to the SDI pin. When the SPI needs tooperate as a receiver, the SDO pin can be configured
as an input. This disables transmissions from the SDO.
The SDI can always be left as an input (SDI function)
since it cannot create a bus conflict.

SLAVE SYNCHRONIZATION WAVEFORMSSSCK(CKP = 0
CKE = 0)SCK(CKP = 1
CKE = 0)

Write toSSPBUF

bit 7

SDO

SDI
(SMP = 0)

bit 6

bit 7

bit 0

bit 0
bit 7

bit 7

Input
Sample(SMP = 0)
SSPIFInterrupt
Flag
Next Q4 Cycle
after Q2↓SSPSR toSSPBUF© 2007 Microchip Technology Inc.

Preliminary

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PIC18F2455/2550/4455/4550
FIGURE 19-5:

SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)

SS
OptionalSCK(CKP = 0
CKE = 0)SCK(CKP = 1
CKE = 0)
Write toSSPBUF
SDO
SDI(SMP = 0)

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

bit 0

bit 7

Input
Sample(SMP = 0)
SSPIFInterrupt
Flag

Next Q4 Cycle
after Q2↓SSPSR toSSPBUF

FIGURE 19-6:

SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)

SS
Not Optional
SCK(CKP = 0
CKE = 1)SCK(CKP = 1
CKE = 1)
Write toSSPBUF
SDO

bit 7

SDI
(SMP = 0)

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

bit 0

Input
Sample(SMP = 0)
SSPIFInterrupt
Flag

Next Q4 Cycle
after Q2↓SSPSR toSSPBUFDS39632D-page 200

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
19.3.8OPERATION IN POWER-MANAGED
MODES

19.3.9In SPI Master mode, module clocks may be operating
at a different speed than when in full power mode; inthe case of the Sleep mode, all clocks are halted.
In most idle modes, a clock is provided to the peripherals. That clock should be from the primary clock
source, the secondary clock (Timer1 oscillator) or the
INTOSC source. See Section 2.4 “Clock Sources
and Oscillator Switching” for additional information.

EFFECTS OF A RESET

A Reset disables the MSSP module and terminates thecurrent transfer.

19.3.10

BUS MODE COMPATIBILITY

Table 19-1 shows the compatibility between thestandard SPI modes and the states of the CKP and
CKE control bits.

TABLE 19-1:

SPI BUS MODES
Control Bits StateIn most cases, the speed that the master clocks SPI
data is not important; however, this should be
evaluated for each system.

Standard SPI Mode
Terminology

CKP

CKE

If MSSP interrupts are enabled, they can wake the controller from Sleep mode or one of the Idle modes whenthe master completes sending data. If an exit from
Sleep or Idle mode is not desired, MSSP interrupts
should be disabled.

0, 0

0

1

0, 1

0

0

1, 0

1

1

1, 1

1

0

If the Sleep mode is selected, all module clocks arehalted and the transmission/reception will remain inthat state until the devices wakes. After the device
returns to Run mode, the module will resumetransmitting and receiving data.

There is also an SMP bit which controls when the data
is sampled.

In SPI Slave mode, the SPI Transmit/Receive Shiftregister operates asynchronously to the device. This
allows the device to be placed in any power-managed
mode and data to be shifted into the SPI Transmit/
Receive Shift register. When all eight bits have been
received, the MSSP interrupt flag bit will be set and if
enabled, will wake the device.

TABLE 19-2:
Name

REGISTERS ASSOCIATED WITH SPI OPERATION
Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset
Valueson page

INTCON

GIE/GIEH PEIE/GIEL TMR0IE

INT0IERBIE

TMR0IF

INT0IF

RBIF

51

PIR1

SPPIF(1)

ADIF

RCIF

TXIF

SSPIF

CCP1IF

TMR2IF

TMR1IF54

PIE1

SPPIE(1)

ADIE

RCIE

TXIE

SSPIE

CCP1IETMR2IETMR1IE54

IPR1

SPPIP(1)

ADIP

RCIP

TXIP

SSPIP

CCP1IP

TMR2IP

TMR1IP

54

TRISA

—

TRISA6(2)TRISA5TRISA4TRISA3

TRISA2TRISA1TRISA054

TRISB

TRISB7TRISB6TRISB5TRISB4

TRISB3

TRISB2

TRISB1TRISB054

TRISC

TRISC7

TRISC6———

TRISC2

TRISC1

TRISC054

SSPBUF

Synchronous Serial Port Receive Buffer/Transmit Register

52

SSPCON1

WCOL

SSPOV

SSPEN

CKP

SSPM3

SSPM2

SSPM1

SSPM0

52

SSPSTAT

SMP

CKE

D/A

P

S

R/W

UA

BF

52

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode.
Note 1: These bits are unimplemented in 28-pin devices; always maintain these bits clear.
2: RA6 is configured as a port pin based on various primary oscillator modes. When the port pin is disabled,
all of the associated bits read ‘0’.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 201

PIC18F2455/2550/4455/4550
19.4

I2C Mode

19.4.1The MSSP module in I 2C mode fully implements all
master and slave functions (including general callsupport) and provides interrupts on Start and Stop bitsin hardware to determine a free bus (multi-masterfunction). The MSSP module implements the standard
mode specifications, as well as 7-bit and 10-bit
addressing.
Two pins are used for data transfer:• Serial clock (SCL) – RB1/AN10/INT1/SCK/SCL• Serial data (SDA) – RB0/AN12/INT0/FLT0/SDI/SDA
The user must configure these pins as inputs by setting
the associated TRIS bits.

FIGURE 19-7:

MSSP BLOCK DIAGRAM(I2C™ MODE)

Write

Shift
Clock
MSb

LSb

Match Detect

SSPCON1, SSPCON2 and SSPSTAT are the control
and status registers in I2C mode operation. The
SSPCON1 and SSPCON2 registers are readable andwritable. The lower six bits of the SSPSTAT are read-only.
The upper two bits of the SSPSTAT are read/write.

In receive operations, SSPSR and SSPBUF together
create a double-buffered receiver. When SSPSR
receives a complete byte, it is transferred to SSPBUF
and the SSPIF interrupt is set.

SSPSR reg
SDA

• MSSP Control Register 1 (SSPCON1)• MSSP Control Register 2 (SSPCON2)• MSSP Status Register (SSPSTAT)• Serial Receive/Transmit Buffer Register(SSPBUF)• MSSP Shift Register (SSPSR) – Not directly
accessible• MSSP Address Register (SSPADD)

SSPADD register holds the slave device address when
the MSSP is configured in I2C Slave mode. When the
MSSP is configured in Master mode, the lower sevenbits of SSPADD act as the Baud Rate Generator reload
value.

SSPBUF reg

SCL

The MSSP module has six registers for I2C operation.
These are:SSPSR is the shift register used for shifting data in orout. SSPBUF is the buffer register to which data bytes
are written to or read from.

Internal
Data Bus
Read

REGISTERS

Addr Match

During transmission, the SSPBUF is not doublebuffered. A write to SSPBUF will write to both SSPBUF
and SSPSR.

Address Mask

SSPADD reg

Start andStop bit Detect

Note:

Set, ResetS, P bits(SSPSTAT reg)

Only port I/O names are used in this diagram forthe sake of brevity. Refer to the text for a full list ofmultiplexed functions.

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REGISTER 19-3:
R/W-0

SSPSTAT: MSSP STATUS REGISTER (I2C™ MODE)
R/W-0

SMP

CKE

R-0

R-0

R-0

D/A

(1)

(1)

P

S

R-0
R/W

(2,3)

R-0

R-0

UA

BF

bit 7

bit 0

Legend:R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’-n = Value at POR‘1’ = Bit is set‘0’ = Bit is clearedx = Bit is unknown

bit 7

SMP: Slew Rate Control bit
In Master or Slave mode:
1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz)
0 = Slew rate control enabled for High-Speed mode (400 kHz)

bit 6

CKE: SMBus Select bit
In Master or Slave mode:
1 = Enable SMBus specific inputs
0 = Disable SMBus specific inputs

bit 5

D/A: Data/Address bit
In Master mode:
Reserved.
In Slave mode:
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address

bit 4

P: Stop bit(1)1 = Indicates that a Stop bit has been detected last
0 = Stop bit was not detected lastbit 3

S: Start bit(1)1 = Indicates that a Start bit has been detected last
0 = Start bit was not detected last

bit 2

R/W: Read/Write Information bit(2,3)
In Slave mode:
1 = Read
0 = Write
In Master mode:
1 = Transmit is in progress
0 = Transmit is not in progress

bit 1

UA: Update Address bit (10-Bit Slave mode only)
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated

bit 0

BF: Buffer Full Status bit
In Transmit mode:
1 = SSPBUF is full
0 = SSPBUF is empty
In Receive mode:
1 = SSPBUF is full (does not include the ACK and Stop bits)
0 = SSPBUF is empty (does not include the ACK and Stop bits)

Note 1:
2:
3:This bit is cleared on Reset and when SSPEN is cleared.
This bit holds the R/W bit information following the last address match. This bit is only valid from theaddress match to the next Start bit, Stop bit or not ACK bit.
ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Active mode.

© 2007 Microchip Technology Inc.

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REGISTER 19-4:

SSPCON1: MSSP CONTROL REGISTER 1 (I2C™ MODE)

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

WCOL

SSPOV

SSPEN

CKP

SSPM3

SSPM2

SSPM1

SSPM0

bit 7

bit 0

Legend:R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’-n = Value at POR‘1’ = Bit is set‘0’ = Bit is clearedx = Bit is unknown

bit 7

WCOL: Write Collision Detect bit
In Master Transmit mode:
1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for atransmission to be started (must be cleared in software)
0 = No collision
In Slave Transmit mode:
1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared insoftware)
0 = No collision
In Receive mode (Master or Slave modes):This is a “don’t care” bit.

bit 6

SSPOV: Receive Overflow Indicator bit
In Receive mode:
1 = A byte is received while the SSPBUF register is still holding the previous byte (must be cleared insoftware)
0 = No overflow
In Transmit mode:This is a “don’t care” bit in Transmit mode.

bit 5

SSPEN: Master Synchronous Serial Port Enable bit
1 = Enables the serial port and configures the SDA and SCL pins as the serial port pins(1)0 = Disables serial port and configures these pins as I/O port pins(1)

bit 4

CKP: SCK Release Control bit
In Slave mode:
1 = Release clock
0 = Holds clock low (clock stretch), used to ensure data setup time
In Master mode:
Unused in this mode.

bit 3-0

SSPM3:SSPM0: Master Synchronous Serial Port Mode Select bits
1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled(2)1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled(2)1011 = I2C Firmware Controlled Master mode (slave Idle)(2)1000 = I2C Master mode, clock = FOSC/(4 * (SSPADD + 1))(2)0111 = I2C Slave mode, 10-bit address(2)0110 = I2C Slave mode, 7-bit address(2)Note 1:
2:

When enabled, the SDA and SCL pins must be properly configured as input or output.
Bit combinations not specifically listed here are either reserved or implemented in SPI mode only.

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REGISTER 19-5:

SSPCON2: MSSP CONTROL REGISTER 2 (I2C™ MASTER MODE)

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

GCEN

ACKSTATACKDT(1)

ACKEN(2)

RCEN(2)

PEN(2)

RSEN(2)

SEN(2)

bit 7

bit 0

Legend:R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’-n = Value at POR‘1’ = Bit is set‘0’ = Bit is clearedx = Bit is unknown

bit 7

GCEN: General Call Enable bit (Slave mode only)
Unused in Master mode.

bit 6

ACKSTAT: Acknowledge Status bit (Master Transmit mode only)
1 = Acknowledge was not received from slave
0 = Acknowledge was received from slave

bit 5

ACKDT: Acknowledge Data bit (Master Receive mode only)(1)
1 = Not Acknowledge
0 = Acknowledge

bit 4

ACKEN: Acknowledge Sequence Enable bit(2)1 = Initiate Acknowledge sequence on SDA and SCL pins and transmit ACKDT data bit. Automatically
cleared by hardware.
0 = Acknowledge sequence Idle

bit 3

RCEN: Receive Enable bit (Master Receive mode only)(2)
1 = Enables Receive mode for I2C
0 = Receive Idle

bit 2

PEN: Stop Condition Enable bit(2)1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Stop condition Idle

bit 1

RSEN: Repeated Start Condition Enable bit(2)1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Repeated Start condition Idle

bit 0

SEN: Start Condition Enable/Stretch Enable bit(2)1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Start condition Idle

Note 1:
2:

Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive.
If the I2C module is active, these bits may not be set (no spooling) and the SSPBUF may not be written (orwrites to the SSPBUF are disabled).

© 2007 Microchip Technology Inc.

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REGISTER 19-6:

SSPCON2: MSSP CONTROL REGISTER 2 (I2C™ SLAVE MODE)

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

GCEN

ACKSTATADMSK5ADMSK4ADMSK3ADMSK2ADMSK1

SEN(1)

bit 7

bit 0

Legend:R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’-n = Value at POR‘1’ = Bit is set‘0’ = Bit is clearedx = Bit is unknown

bit 7

GCEN: General Call Enable bit (Slave mode only)
1 = Enable interrupt when a general call address (0000h) is received in the SSPSR
0 = General call address disabled

bit 6

ACKSTAT: Acknowledge Status bit
Unused in Slave mode.

bit 5-2

ADMSK5:ADMSK2: Slave Address Mask Select bits
1 = Masking of corresponding bits of SSPADD enabled
0 = Masking of corresponding bits of SSPADD disabled

bit 1

ADMSK1: Slave Address Mask Select bit
In 7-Bit Address mode:
1 = Masking of SPADD<1> only enabled
0 = Masking of SPADD<1> only disabled
In 10-Bit Address mode:
1 = Masking of SSPADD<1:0> enabled
0 = Masking of SSPADD<1:0> disabled

bit 0

SEN: Stretch Enable bit(1)1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0 = Clock stretching is disabled

Note 1:

If the I2C module is active, this bit may not be set (no spooling) and the SSPBUF may not be written (orwrites to the SSPBUF are disabled).

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19.4.2OPERATION

19.4.3.1

The MSSP module functions are enabled by setting
MSSP Enable bit, SSPEN (SSPCON1<5>).
The SSPCON1 register allows control of the I2C
operation. Four mode selection bits (SSPCON1<3:0>)
allow one of the following I2C modes to be selected:• I2C Master mode, clock• I 2C Slave mode (7-bit address)• I 2C Slave mode (10-bit address)• I 2C Slave mode (7-bit address) with Start andStop bit interrupts enabled• I 2C Slave mode (10-bit address) with Start andStop bit interrupts enabled• I 2C Firmware Controlled Master mode, slave isIdle

19.4.3Once the MSSP module has been enabled, it waits fora Start condition to occur. Following the Start condition,
the 8 bits are shifted into the SSPSR register. All
incoming bits are sampled with the rising edge of theclock (SCL) line. The value of register SSPSR<7:1> iscompared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match and the BF
and SSPOV bits are clear, the following events occur:
1.
2.
3.
4.

Selection of any I 2C mode with the SSPEN bit set
forces the SCL and SDA pins to be open-drain,provided these pins are programmed as inputs bysetting the appropriate TRISC or TRISD bits. To ensure
proper operation of the module, pull-up resistors must
be provided externally to the SCL and SDA pins.

SLAVE MODE

In Slave mode, the SCL and SDA pins must be
configured as inputs (TRISC<4:3> set). The MSSP
module will override the input state with the output datawhen required (slave-transmitter).
The I 2C Slave mode hardware will always generate aninterrupt on an address match. Address masking willallow the hardware to generate an interrupt for morethan one address (up to 31 in 7-bit addressing and up
to 63 in 10-bit addressing). Through the mode selectbits, the user can also choose to interrupt on Start andStop bits.
When an address is matched, or the data transfer afteran address match is received, the hardware automatically will generate the Acknowledge (ACK) pulse
and load the SSPBUF register with the received value
currently in the SSPSR register.
Any combination of the following conditions will cause
the MSSP module not to give this ACK pulse:• The Buffer Full bit, BF (SSPSTAT<0>), was set
before the transfer was received.
• The overflow bit, SSPOV (SSPCON1<6>), wasset before the transfer was received.

Addressing

The SSPSR register value is loaded into the
SSPBUF register.
The Buffer Full bit, BF, is set.
An ACK pulse is generated.
The MSSP Interrupt Flag bit, SSPIF, is set (andinterrupt is generated, if enabled) on the fallingedge of the ninth SCL pulse.

In 10-Bit Address mode, two address bytes need to bereceived by the slave. The five Most Significant bits
(MSbs) of the first address byte specify if this is a 10-bit
address. Bit R/W (SSPSTAT<2>) must specify a write so
the slave device will receive the second address byte.
For a 10-bit address, the first byte would equal ‘11110
A9 A8 0’, where ‘A9’ and ‘A8’ are the two MSbs of theaddress. The sequence of events for 10-bit address is asfollows, with steps 7 through 9 for the slave-transmitter:
1.

2.

3.
4.
5.

6.
7.
8.
9.

Receive first (high) byte of address (bits SSPIF,BF and UA (SSPSTAT<1>) are set on address
match).
Update the SSPADD register with second (low)byte of address (clears bit UA and releases the
SCL line).
Read the SSPBUF register (clears bit BF) andclear flag bit SSPIF.
Receive second (low) byte of address (bits
SSPIF, BF and UA are set).
Update the SSPADD register with the first (high)byte of address. If match releases SCL line, thiswill clear bit UA.
Read the SSPBUF register (clears bit BF) andclear flag bit SSPIF.
Receive Repeated Start condition.
Receive first (high) byte of address (bits SSPIF
and BF are set).
Read the SSPBUF register (clears bit BF) andclear flag bit SSPIF.

In this case, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF is set. The BF bit iscleared by reading the SSPBUF register, while bit
SSPOV is cleared through software.
The SCL clock input must have a minimum high andlow for proper operation. The high and low times of the
I2C specification, as well as the requirement of the
MSSP module, are shown in timing parameter 100 andparameter 101.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 207

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19.4.3.2

Address Masking

Masking an address bit causes that bit to become a“don’t care”. When one address bit is masked, twoaddresses will be Acknowledged and cause aninterrupt. It is possible to mask more than one address
bit at a time, which makes it possible to Acknowledge
up to 31 addresses in 7-bit mode and up to 63
addresses in 10-bit mode (see Example 19-2).
The I2C Slave behaves the same way whether address
masking is used or not. However, when address
masking is used, the I2C slave can Acknowledge
multiple addresses and cause interrupts. When thisoccurs, it is necessary to determine which addresscaused the interrupt by checking SSPBUF.

In 10-Bit Address mode, bits ADMSK<5:2> mask thecorresponding address bits in the SSPADD register. In
addition, ADMSK1 simultaneously masks the two LSbsof the address (SSPADD<1:0>). For any ADMSK bitsthat are active (ADMSK<n> = 1), the corresponding
address bit is ignored (SSPADD<n> = x). Also notethat although in 10-Bit Addressing mode, the upper
address bits reuse part of the SSPADD register bits, theaddress mask bits do not interact with those bits. They
only affect the lower address bits.
Note 1: ADMSK1 masks the two Least Significant
bits of the address.

In 7-Bit Address mode, address mask bits
ADMSK<5:1> (SSPCON2<5:1>) mask the corresponding address bits in the SSPADD register. For any
ADMSK bits that are set (ADMSK<n> = 1), thecorresponding
addressbit
isignored(SSPADD<n> = x). For the module to issue an address
Acknowledge, it is sufficient to match only on
addresses that do not have an active address mask.

EXAMPLE 19-2:

2: The two Most Significant bits of theaddress are not affected by address
masking.

ADDRESS MASKING EXAMPLES

7-bit addressing:
SSPADD<7:1> = A0h (1010000) (SSPADD<0> is assumed to be ‘0’)ADMSK<5:1>= 00111Addresses Acknowledged : A0h, A2h, A4h, A6h, A8h, AAh, ACh, AEh10-bit addressing:
SSPADD<7:0> = A0h (10100000) (The two MSbs of the address are ignored in this example, since
they are not affected by masking)
ADMSK<5:1>= 00111Addresses Acknowledged: A0h, A1h, A2h, A3h, A4h, A5h, A6h, A7h, A8h, A9h, AAh, ABh, ACh, ADh,
AEh, AFh

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19.4.3.3

Reception

19.4.3.4

When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleared. The received address is loaded into
the SSPBUF register and the SDA line is held low(ACK).
When the address byte overflow condition exists, then
the no Acknowledge (ACK) pulse is given. An overflow
condition is defined as either bit BF (SSPSTAT<0>) isset, or bit SSPOV (SSPCON1<6>) is set.
An MSSP interrupt is generated for each data transfer
byte. The Interrupt Flag bit, SSPIF, must be cleared insoftware. The SSPSTAT register is used to determine
the status of the byte.
If SEN is enabled (SSPCON2<0> = 1), RB1/AN10/
INT1/SCK/SCL will be held low (clock stretch) following
each data transfer. The clock must be released by
setting bit, CKP (SSPCON1<4>). See Section 19.4.4“Clock Stretching” for more detail.

Transmission

When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address isloaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit and pin RB1/AN10/INT1/SCK/SCL is held low regardless of SEN (see Section 19.4.4“Clock Stretching” for more detail). By stretching theclock, the master will be unable to assert another clock
pulse until the slave is done preparing the transmit
data. The transmit data must be loaded into the
SSPBUF register which also loads the SSPSR register.
Then pin RB1/AN10/INT1/SCK/SCL should be enabled
by setting bit, CKP (SSPCON1<4>). The eight data bits
are shifted out on the falling edge of the SCL input. This
ensures that the SDA signal is valid during the SCL
high time (Figure 19-10).
The ACK pulse from the master-receiver is latched on
the rising edge of the ninth SCL input pulse. If the SDA
line is high (not ACK), then the data transfer iscomplete. In this case, when the ACK is latched by theslave, the slave logic is reset (resets SSPSTAT register) and the slave monitors for another occurrence of
the Start bit. If the SDA line was low (ACK), the nexttransmit data must be loaded into the SSPBUF register.
Again, pin RB1/AN10/INT1/SCK/SCL must be enabled
by setting bit CKP (SSPCON1<4>).
An MSSP interrupt is generated for each data transfer
byte. The SSPIF bit must be cleared in software andthe SSPSTAT register is used to determine the statusof the byte. The SSPIF bit is set on the falling edge ofthe ninth clock pulse.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 209

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Preliminary

CKP

2

A6

3

4

A4

5

A3

Receiving Address
A5

6

A2

(CKP does not reset to ‘0’ when SEN = 0)

SSPOV (SSPCON1<6>)

BF (SSPSTAT<0>)

SSPIF (PIR1<3>)

1

SCL

S

A7

7

A1

8

9

ACK

R/W = 0

1

D7

3

4

D4

5

D3

Receiving Data
D5

Cleared in software
SSPBUF is read

2

D6

6

D2

7

D1

8

D0

9

ACK

1

D7

2

D6

3

4

D4

5

D3

Receiving Data
D5

6

D2

7

D1

8

D0

Bus masterterminatestransferP

SSPOV is set
because SSPBUF isstill full. ACK is not sent.

9

ACK

FIGURE 19-8:

SDA

PIC18F2455/2550/4455/4550
I2C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS)© 2007 Microchip Technology Inc.

© 2007 Microchip Technology Inc.

Preliminary

Note

CKP

2

A6

3

A5

4

X

5

A3

6

X

1

3

4

D4

Cleared in software
SSPBUF is read

2

D5

5

D3

6

D2

7

D1

8

D0

In this example, an address equal to A7.A6.A5.X.A3.X.X will be Acknowledged and cause an interrupt.

9D6

x = Don’t care (i.e., address bit can be either a ‘1’ or a ‘0’).

8

D7

Receiving Data

2:

7

X

ACK

R/W = 01:

(CKP does not reset to ‘0’ when SEN = 0)

SSPOV (SSPCON1<6>)

BF (SSPSTAT<0>)

SSPIF (PIR1<3>)

1

SCL

S

A7

Receiving Address

9

ACK

1

D7

2

D6

3

D5

4

D4

5

D3

Receiving Data

6

D2

7

D1

8

D0

Bus masterterminatestransferP

SSPOV is set
because SSPBUF isstill full. ACK is not sent.

9

ACK

FIGURE 19-9:

SDA

PIC18F2455/2550/4455/4550

I2C™ SLAVE MODE TIMING WITH SEN = 0 AND ADMSK<5:1> = 01011(RECEPTION, 7-BIT ADDRESS)

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Preliminary

CKP

BF (SSPSTAT<0>)

SSPIF (PIR1<3>)

1

2

A6

Data insampled

SCL

S

A7

3

4

A4

5

A3

6

A2

Receiving Address

A5

7

A1

8

R/W = 19ACK

SCL held low
while CPU
responds to SSPIF

1

D7

3

D5

4

5

D3

CKP is set in software

SSPBUF is written in software

6

D2

Transmitting Data
D4

Cleared in software

2

D6

7

8

D0

9

From SSPIF ISR

D1

ACK

1

D7

4

D4

5

D3

Cleared in software

3

D5

6

D2

CKP is set in software

SSPBUF is written in software

2

D6

7

8

D0

9

ACK

From SSPIF ISR

D1Transmitting DataP

FIGURE 19-10:

SDA

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I2C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS)© 2007 Microchip Technology Inc.

© 2007 Microchip Technology Inc.

2

1

Preliminary

4

1

5

0

7

A8

UA is set indicating that
the SSPADD needs to be
updatedSSPBUF is written with
contents of SSPSR

6

A9

8

9

(CKP does not reset to ‘0’ when SEN = 0)

UA (SSPSTAT<1>)

SSPOV (SSPCON1<6>)

CKP

3

1

Cleared in software

BF (SSPSTAT<0>)

SSPIF (PIR1<3>)

1

SCL

S

1

ACK

R/W = 0
A7

2

4

5

A4 A3

6

8

9

A0 ACK

UA is set indicating that
SSPADD needs to be
updatedCleared by hardware
when SSPADD is updatedwith low byte of address

7

A2 A1

Cleared in software

3

A5

Dummy read of SSPBUF
to clear BF flag

1

A6

Receive Second Byte of Address

1

D7

4

5

6

Cleared in software

3

7

8

9
1

2

4

5

6

Cleared in software

3

D3 D2

Receive Data Byte
D1 D0 ACK D7 D6 D5 D4Cleared by hardware when
SSPADD is updated with highbyte of address

2

D3 D2

Receive Data Byte
D6 D5 D4

Clock is held low until
update of SSPADD has
taken place

7

8

D1 D0

9

P
Bus masterterminatestransfer

SSPOV is set
because SSPBUF isstill full. ACK is not sent.

ACK

FIGURE 19-11:

SDA

Receive First Byte of Address

Clock is held low until
update of SSPADD has
taken place

PIC18F2455/2550/4455/4550

I2C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS)

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Preliminary

Note

CKP

4

1

5

0

7

A8

UA is set indicating that
the SSPADD needs to be
updatedSSPBUF is written with
contents of SSPSR

6

A9

8

9

2

X

4

5

A3

6

A2

4

5

6

Cleared in software

3

7

8

9
1

2

4

5
6

Cleared in software

3

D3 D2

Receive Data Byte
D1 D0 ACK D7 D6 D5 D4Cleared by hardware when
SSPADD is updated with highbyte of address

2

D3 D2

Note that the Most Significant bits of the address are not affected by the bit masking.

1

D6 D5 D4

3:

9

D7

x = Don’t care (i.e., address bit can be either a ‘1’ or a ‘0’).

8

X

Receive Data Byte

In this example, an address equal to A9.A8.A7.A6.A5.X.A3.A2.X.X will be Acknowledged and cause an interrupt.

UA is set indicating that
SSPADD needs to be
updatedCleared by hardware
when SSPADD is updatedwith low byte of address

7

X

Cleared in software

3

A5

Dummy read of SSPBUF
to clear BF flag

1

A6

ACK

1:

A7

Receive Second Byte of Address

2:(CKP does not reset to ‘0’ when SEN = 0)

UA (SSPSTAT<1>)3

1

Cleared in software

2

1

SSPOV (SSPCON1<6>)

BF (SSPSTAT<0>)

SSPIF (PIR1<3>)

1

SCL

S

1

ACK

R/W = 0

Clock is held low until
update of SSPADD has
taken place

7

8

D1 D0

9

P
Bus masterterminatestransfer

SSPOV is set
because SSPBUF isstill full. ACK is not sent.

ACK

FIGURE 19-12:

SDA

Receive First Byte of Address

Clock is held low until
update of SSPADD has
taken place

PIC18F2455/2550/4455/4550
I2C™ SLAVE MODE TIMING WITH SEN = 0 AND ADMSK<5:1> = 01001(RECEPTION, 10-BIT ADDRESS)© 2007 Microchip Technology Inc.

© 2007 Microchip Technology Inc.

2

Preliminary

CKP (SSPCON1<4>)

UA (SSPSTAT<1>)

BF (SSPSTAT<0>)

SSPIF (PIR1<3>)

1

S

SCL

1

4

1

5

0

6

7

A9 A8

8

UA is set indicating that
the SSPADD needs to be
updatedSSPBUF is written with
contents of SSPSR

3

1

9

ACK

Receive First Byte of Address R/W = 0

1

1

3

4

5

Cleared in software2

7

UA is set indicating that
SSPADD needs to be
updated

8

A1 A0

Cleared by hardware when
SSPADD is updated with low
byte of address

6

A6 A5 A4 A3 A2Receive Second Byte of Address

Dummy read of SSPBUF
to clear BF flag

A7

9

ACK

2

3

1

4

1

Cleared in software

1

1

5

0

6
8

9

ACK

R/W = 1

1

2

4

5

6

Cleared in software

3

CKP is set in software

9P

Completion ofdata transmission
clears BF flag

8

ACK

Bus masterterminatestransfer

CKP is automatically cleared in hardware, holding SCL low

7

D7 D6 D5 D4 D3 D2 D1 D0Transmitting Data Byte

Clock is held low until
CKP is set to ‘1’

Write of SSPBUF
BF flag is clear
initiates transmit
at the end of thethird address sequence

7

A9 A8

Cleared by hardware when
SSPADD is updated with highbyte of address.

Dummy read of SSPBUF
to clear BF flag

Sr

1

Receive First Byte of Address

Clock is held low until
update of SSPADD has
taken place

FIGURE 19-13:

SDA

Clock is held low until
update of SSPADD has
taken place

PIC18F2455/2550/4455/4550

I2C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS)

DS39632D-page 215

PIC18F2455/2550/4455/4550
19.4.4

CLOCK STRETCHING

19.4.4.3

Both 7-Bit and 10-Bit Slave modes implement
automatic clock stretching during a transmit sequence.
The SEN bit (SSPCON2<0>) allows clock stretching to
be enabled during receives. Setting SEN will cause
the SCL pin to be held low at the end of each data
receive sequence.

19.4.4.1

Clock Stretching for 7-Bit Slave
Receive Mode (SEN = 1)

In 7-Bit Slave Receive mode, on the falling edge of theninth clock at the end of the ACK sequence if the BF
bit is set, the CKP bit in the SSPCON1 register is
automatically cleared, forcing the SCL output to beheld low. The CKP bit being cleared to ‘0’ will assert
the SCL line low. The CKP bit must be set in the user’s
ISR before reception is allowed to continue. By holding
the SCL line low, the user has time to service the ISR
and read the contents of the SSPBUF before themaster device can initiate another receive sequence.
This will prevent buffer overruns from occurring (seeFigure 19-15).
Note 1: If the user reads the contents of the
SSPBUF before the falling edge of theninth clock, thus clearing the BF bit, theCKP bit will not be cleared and clock
stretching will not occur.
2: The CKP bit can be set in software
regardless of the state of the BF bit. The
user should be careful to clear the BF bit
in the ISR before the next receive
sequence in order to prevent an overflow
condition.

19.4.4.2

Clock Stretching for 7-Bit Slave
Transmit Mode

7-Bit Slave Transmit mode implements clock stretching by clearing the CKP bit after the falling edge of theninth clock if the BF bit is clear. This occurs regardlessof the state of the SEN bit.
The user’s ISR must set the CKP bit before transmission is allowed to continue. By holding the SCL line
low, the user has time to service the ISR and load thecontents of the SSPBUF before the master device caninitiate another transmit sequence (see Figure 19-10).
Note 1: If the user loads the contents of SSPBUF,
setting the BF bit before the falling edge ofthe ninth clock, the CKP bit will not becleared and clock stretching will not occur.
2: The CKP bit can be set in software
regardless of the state of the BF bit.

19.4.4.4

Clock Stretching for 10-Bit Slave
Transmit Mode

In 10-Bit Slave Transmit mode, clock stretching iscontrolled during the first two address sequences by
the state of the UA bit, just as it is in 10-Bit Slave
Receive mode. The first two addresses are followed
by a third address sequence which contains the highorder bits of the 10-bit address and the R/W bit set to‘1’. After the third address sequence is performed, theUA bit is not set, the module is now configured inTransmit mode and clock stretching is controlled by
the BF flag as in 7-Bit Slave Transmit mode (seeFigure 19-13).

Clock Stretching for 10-Bit Slave
Receive Mode (SEN = 1)

In 10-Bit Slave Receive mode during the address
sequence, clock stretching automatically takes place
but CKP is not cleared. During this time, if the UA bit isset after the ninth clock, clock stretching is initiated.
The UA bit is set after receiving the upper byte of the
10-bit address and following the receive of the second
byte of the 10-bit address with the R/W bit cleared to‘0’. The release of the clock line occurs upon updating
SSPADD. Clock stretching will occur on each data
receive sequence as described in 7-bit mode.
Note:

If the user polls the UA bit and clears it by
updating the SSPADD register before thefalling edge of the ninth clock occurs and if
the user hasn’t cleared the BF bit by reading the SSPBUF register before that time,then the CKP bit will still NOT be asserted
low. Clock stretching on the basis of thestate of the BF bit only occurs during adata sequence, not an address sequence.

DS39632D-page 216

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
19.4.4.5

Clock Synchronization and
the CKP bit

When the CKP bit is cleared, the SCL output is forced
to ‘0’. However, clearing the CKP bit will not assert the
SCL output low until the SCL output is alreadysampled low. Therefore, the CKP bit will not assert the
SCL line until an external I2C master device has

FIGURE 19-14:

already asserted the SCL line. The SCL output willremain low until the CKP bit is set and all otherdevices on the I2C bus have deasserted SCL. This
ensures that a write to the CKP bit will not violate theminimum high time requirement for SCL (seeFigure 19-14).

CLOCK SYNCHRONIZATION TIMINGQ1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

SDA

DX

DX – 1SCL

CKP

Master device
asserts clock
Master device
deasserts clock

Write
SSPCON1© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 217

DS39632D-page 218

Preliminary

CKP

SSPOV (SSPCON1<6>)

BF (SSPSTAT<0>)

SSPIF (PIR1<3>)

1

SCL

S

A7

2

A6

3

4

A4

5

A3

6

A2

Receiving Address
A5

7

A1

8

9

ACK

R/W = 0

3

4

D4

5

D3

Receiving Data
D5

Cleared in software

2

D6

If BF is clearedprior to the fallingedge of the ninth clock,
CKP will not be resetto ‘0’ and no clock
stretching will occur

SSPBUF is read

1

D7

6

D2

7

D1

9

ACK

1

D7

2

D6

3

4

D4

5

D3

Receiving Data
D5

CKP
writtento ‘1’ insoftware
BF is set after fallingedge of the ninth clock,
CKP is reset to ‘0’ andclock stretching occurs

8

D0

Clock is held low until
CKP is set to ‘1’

6

D2

7

D1

8

D0

Bus masterterminatestransferP

SSPOV is set
because SSPBUF isstill full. ACK is not sent.

9

ACK

Clock is not held low
because ACK = 1

FIGURE 19-15:

SDA

Clock is not held low
because Buffer Full (BF) bit isclear prior to falling edgeof ninth clock

PIC18F2455/2550/4455/4550
I2C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS)© 2007 Microchip Technology Inc.

© 2007 Microchip Technology Inc.

2

1

Preliminary

UA (SSPSTAT<1>)

SSPOV (SSPCON1<6>)

CKP

3

1

4

1

5

0

6

7

A9 A8

8

UA is set indicating that
the SSPADD needs to be
updatedSSPBUF is written with
contents of SSPSR

Cleared in software

BF (SSPSTAT<0>)

SSPIF (PIR1<3>)

1

SCL

S

1

9

ACK

R/W = 0
A7

2

4

A4

5

A3

6

8

A0

Note: An update of the SSPADD
register before the fallingedge of the ninth clock will
have no effect on UA andUA will remain set.

UA is set indicating that
SSPADD needs to be
updatedCleared by hardware when
SSPADD is updated with low
byte of address after falling edgeof ninth clock

7

A2 A1

Cleared in software

3

A5

Dummy read of SSPBUF
to clear BF flag

1

A6

Receive Second Byte of Address

9

ACK

2

4

5

6

Cleared in software

3

D3 D2

7

9

Note: An update of the SSPADD register before
the falling edge of the ninth clock will haveno effect on UA and UA will remain set.

8

ACK

1

4

5

6

Cleared in software

3

D3 D2

CKP written to ‘1’
in software

2

D4

Receive Data Byte
D7 D6 D5

Clock is held low until
CKP is set to ‘1’

D1 D0

Cleared by hardware when
SSPADD is updated with highbyte of address after falling edgeof ninth clock

Dummy read of SSPBUF
to clear BF flag

1

D7 D6 D5 D4Receive Data Byte

Clock is held low until
update of SSPADD has
taken place

7

8

9

ACK

Bus masterterminatestransferP

SSPOV is set
because SSPBUF isstill full. ACK is not sent.

D1 D0

Clock is not held low
because ACK = 1

FIGURE 19-16:

SDA

Receive First Byte of Address

Clock is held low until
update of SSPADD has
taken place

PIC18F2455/2550/4455/4550

I2C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 10-BIT ADDRESS)

DS39632D-page 219

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19.4.5

GENERAL CALL ADDRESSSUPPORT

If the general call address matches, the SSPSR istransferred to the SSPBUF, the BF flag bit is set (eighthbit) and on the falling edge of the ninth bit (ACK bit), the
SSPIF interrupt flag bit is set.

The addressing procedure for the I2C bus is such thatthe first byte after the Start condition usually
determines which device will be the slave addressed by
the master. The exception is the general call address
which can address all devices. When this address isused, all devices should, in theory, respond with an
Acknowledge.

When the interrupt is serviced, the source for theinterrupt can be checked by reading the contents of the
SSPBUF. The value can be used to determine if theaddress was device specific or a general call address.
In 10-bit mode, the SSPADD is required to be updated
for the second half of the address to match and the UA
bit is set (SSPSTAT<1>). If the general call address is
sampled when the GCEN bit is set, while the slave isconfigured in 10-Bit Address mode, then the second
half of the address is not necessary, the UA bit will not
be set and the slave will begin receiving data after the
Acknowledge (Figure 19-17).

The general call address is one of eight addresses
reserved for specific purposes by the I2C protocol. It
consists of all ‘0’s with R/W = 0.
The general call address is recognized when the General Call Enable (GCEN) bit is enabled (SSPCON2<7>set). Following a Start bit detect, 8 bits are shifted into
the SSPSR and the address is compared against the
SSPADD. It is also compared to the general calladdress and fixed in hardware.

FIGURE 19-17:

SLAVE MODE GENERAL CALL ADDRESS SEQUENCE(7 OR 10-BIT ADDRESS MODE)
Address is compared to General Call Address
after ACK, set interrupt
R/W = 0ACK D7

General Call Address

SDA

Receiving Data

ACK

D6

D5

D4

D3

D2

D1

D0

2

3

4

5

6

7

8

SCL
S

1

2

3

4

5

6

7

8

9

1

9

SSPIF
BF (SSPSTAT<0>)Cleared in software
SSPBUF is read
SSPOV (SSPCON1<6>)‘0’

GCEN (SSPCON2<7>)‘1’

DS39632D-page 220

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
MASTER MODE

Note:

The MSSP module, when configured in
I2C Master mode, does not allow queueingof events. For instance, the user is notallowed to initiate a Start condition and
immediately write the SSPBUF register toinitiate transmission before the Start
condition is complete. In this case, the
SSPBUF will not be written to and the
WCOL bit will be set, indicating that a write
to the SSPBUF did not occur.

Master mode is enabled by setting and clearing theappropriate SSPM bits in SSPCON1 and by setting the
SSPEN bit. In Master mode, the SCL and SDA lines
are manipulated by the MSSP hardware if the TRIS bits
are set.
Master mode operation is supported by interrupt
generation on the detection of the Start and Stopconditions. The Stop (P) and Start (S) bits are cleared
from a Reset or when the MSSP module is disabled.
Control of the I 2C bus may be taken when the P bit isset or the bus is Idle, with both the S and P bits clear.

The following events will cause the MSSP Interrupt
Flag bit, SSPIF, to be set (and MSSP interrupt, if
enabled):In Firmware Controlled Master mode, user code
conducts all I 2C bus operations based on Start andStop bit conditions.

• Start condition• Stop condition• Data transfer byte transmitted/received• Acknowledge transmit• Repeated Start

Once Master mode is enabled, the user has six
options:
1.
2.
3.
4.
5.
6.

Assert a Start condition on SDA and SCL.
Assert a Repeated Start condition on SDA and
SCL.
Write to the SSPBUF register initiatingtransmission of data/address.
Configure the I2C port to receive data.
Generate an Acknowledge condition at the endof a received byte of data.
Generate a Stop condition on SDA and SCL.

FIGURE 19-18:

MSSP BLOCK DIAGRAM (I2C™ MASTER MODE)
Internal
Data Bus
Read

SSPM3:SSPM0
SSPADD<6:0>

Write
SSPBUF

Baud
Rate
Generator
Shift
Clock

SDA
SDA InSCL InBus Collision© 2007 Microchip Technology Inc.

LSb

Start bit, Stop bit,Acknowledge
Generate

Start bit Detect
Stop bit Detect
Write Collision Detect
Clock Arbitration
State Counter for
End of XMIT/RCVPreliminary

Clock Cntl

SCL

Receive Enable

SSPSR
MSb

Clock Arbitrate/WCOL Detect(hold off clock source)

19.4.6

Set/Reset S, P, WCOL (SSPSTAT, SSPCON1);
set SSPIF, BCLIF;
reset ACKSTAT, PEN (SSPCON2)

DS39632D-page 221

PIC18F2455/2550/4455/4550
19.4.6.1

I2C Master Mode Operation

A typical transmit sequence would go as follows:

The master device generates all of the serial clock
pulses and the Start and Stop conditions. A transfer isended with a Stop condition or with a Repeated Start
condition. Since the Repeated Start condition is also
the beginning of the next serial transfer, the I2C bus will
not be released.
In Master Transmitter mode, serial data is output
through SDA, while SCL outputs the serial clock. The
first byte transmitted contains the slave address of thereceiving device (seven bits) and the Read/Write (R/W)
bit. In this case, the R/W bit will be logic ‘0’. Serial datais transmitted eight bits at a time. After each byte istransmitted, an Acknowledge bit is received. Start andStop conditions are output to indicate the beginningand the end of a serial transfer.
In Master Receive mode, the first byte transmitted contains the slave address of the transmitting device(7 bits) and the R/W bit. In this case, the R/W bit will be
logic ‘1’ Thus, the first byte transmitted is a 7-bit slave
address followed by a ‘1’ to indicate the receive bit.
Serial data is received via SDA, while SCL outputs theserial clock. Serial data is received eight bits at a time.
After each byte is received, an Acknowledge bit istransmitted. Start and Stop conditions indicate thebeginning and end of transmission.
The Baud Rate Generator used for the SPI mode
operation is used to set the SCL clock frequency for
either 100 kHz, 400 kHz or 1 MHz I2C operation. See
Section 19.4.7 “Baud Rate” for more detail.

DS39632D-page 222

1.

The user generates a Start condition by setting
the Start Enable bit, SEN (SSPCON2<0>).
2. SSPIF is set. The MSSP module will wait therequired start time before any other operation
takes place.
3. The user loads the SSPBUF with the slave
address to transmit.
4. Address is shifted out the SDA pin until all eightbits are transmitted.
5. The MSSP module shifts in the ACK bit from theslave device and writes its value into the
SSPCON2 register (SSPCON2<6>).
6. The MSSP module generates an interrupt at theend of the ninth clock cycle by setting the SSPIF
bit.
7. The user loads the SSPBUF with eight bits ofdata.
8. Data is shifted out the SDA pin until all eight bits
are transmitted.
9. The MSSP module shifts in the ACK bit from theslave device and writes its value into the
SSPCON2 register (SSPCON2<6>).
10. The MSSP module generates an interrupt at theend of the ninth clock cycle by setting the SSPIF
bit.
11. The user generates a Stop condition by setting
the Stop Enable bit, PEN (SSPCON2<2>).
12. Interrupt is generated once the Stop condition iscomplete.

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
19.4.7BAUD RATE

2

In I C Master mode, the Baud Rate Generator (BRG)
reload value is placed in the lower seven bits of the
SSPADD register (Figure 19-19). When a write occurs
to SSPBUF, the Baud Rate Generator will automaticallybegin counting. The BRG counts down to ‘0’ and stops
until another reload has taken place. The BRG count isdecremented twice per instruction cycle (TCY) on theQ2 and Q4 clocks. In I2C Master mode, the BRG isreloaded automatically.

FIGURE 19-19:

SSPM3:SSPM0

ReloadSCL

Control
CLKO

Note 1:

Table 19-3 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPADD.

BAUD RATE GENERATOR BLOCK DIAGRAM
SSPM3:SSPM0

TABLE 19-3:

Once the given operation is complete (i.e., transmission of the last data bit is followed by ACK), the internal
clock will automatically stop counting and the SCL pin
will remain in its last state.

SSPADD<6:0>

ReloadBRG Down Counter

FOSC/4I2C™ CLOCK RATE W/BRG

FCY

FCY * 2BRG Value

FSCL(2 Rollovers of BRG)

10 MHz20 MHz18h

400 kHz(1)10 MHz20 MHz1Fh

312.5 kHz

10 MHz20 MHz63h

100 kHz

4 MHz

8 MHz

09h

400 kHz(1)

4 MHz

8 MHz

0Ch

308 kHz

4 MHz

8 MHz

27h

100 kHz

1 MHz

2 MHz

02h

333 kHz(1)

1 MHz

2 MHz

09h

100 kHz

1 MHz

2 MHz

00h

1 MHz(1)The I2C™ interface does not conform to the 400 kHz I2C specification (which applies to rates greater than
100 kHz) in all details, but may be used with care where higher rates are required by the application.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 223

PIC18F2455/2550/4455/4550
19.4.7.1

Clock Arbitration

Clock arbitration occurs when the master, during any
receive, transmit or Repeated Start/Stop condition,
deasserts the SCL pin (SCL allowed to float high).
When the SCL pin is allowed to float high, the Baud
Rate Generator (BRG) is suspended from counting
until the SCL pin is actually sampled high. When the

FIGURE 19-20:
SDA

SCL pin is sampled high, the Baud Rate Generator isreloaded with the contents of SSPADD<6:0> andbegins counting. This ensures that the SCL high time
will always be at least one BRG rollover count in theevent that the clock is held low by an external device(Figure 19-20).

BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATIONDXDX – 1
SCL deasserted but slave holds
SCL low (clock arbitration)

SCL allowed to transition highSCL
BRG decrements on
Q2 and Q4 cycles
BRG
Value

03h

02h

01h

00h (hold off)

03h

02h

SCL is sampled high, reload takes
place and BRG starts its count
BRG
ReloadDS39632D-page 224

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
19.4.8I2C MASTER MODE START
CONDITION TIMINGNote:

To initiate a Start condition, the user sets the Start
Enable bit, SEN (SSPCON2<0>). If the SDA and SCL
pins are sampled high, the Baud Rate Generator isreloaded with the contents of SSPADD<6:0> and starts
its count. If SCL and SDA are both sampled high whenthe Baud Rate Generator times out (TBRG), the SDA
pin is driven low. The action of the SDA being driven
low while SCL is high is the Start condition and causes
the S bit (SSPSTAT<3>) to be set. Following this, theBaud Rate Generator is reloaded with the contents of
SSPADD<6:0> and resumes its count. When the Baud
Rate Generator times out (TBRG), the SEN bit(SSPCON2<0>) will be automatically cleared byhardware, the Baud Rate Generator is suspended,leaving the SDA line held low and the Start condition iscomplete.

FIGURE 19-21:

19.4.8.1

If at the beginning of the Start condition,
the SDA and SCL pins are already sampled low, or if during the Start condition, the
SCL line is sampled low before the SDA
line is driven low, a bus collision occurs,
the Bus Collision Interrupt Flag, BCLIF, isset, the Start condition is aborted and theI2C module is reset into its Idle state.

WCOL Status Flag

If the user writes the SSPBUF when a Start sequenceis in progress, the WCOL bit is set and the contents ofthe buffer are unchanged (the write doesn’t occur).
Note:

Because queueing of events is notallowed, writing to the lower five bits ofSSPCON2 is disabled until the Start
condition is complete.

FIRST START BIT TIMING
Set S bit (SSPSTAT<3>)

Write to SEN bit occurs here
SDA = 1,SCL = 1TBRG

At completion of Start bit,
hardware clears SEN bit
and sets SSPIF bit
TBRG

Write to SSPBUF occurs here
1st bitSDA

2nd bit

TBRG

SCL

TBRG
S

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 225

PIC18F2455/2550/4455/4550
19.4.9I2C MASTER MODE REPEATEDSTART CONDITION TIMING

Note 1: If RSEN is programmed while any otherevent is in progress, it will not take effect.

A Repeated Start condition occurs when the RSEN bit(SSPCON2<1>) is programmed high and the I2C logic
module is in the Idle state. When the RSEN bit is set,
the SCL pin is asserted low. When the SCL pin is sampled low, the Baud Rate Generator is loaded with thecontents of SSPADD<5:0> and begins counting. The
SDA pin is released (brought high) for one Baud Rate
Generator count (TBRG). When the Baud Rate Generator times out, if SDA is sampled high, the SCL pin will
be deasserted (brought high). When SCL is sampled
high, the Baud Rate Generator is reloaded with thecontents of SSPADD<6:0> and begins counting. SDA
and SCL must be sampled high for one TBRG. Thisaction is then followed by assertion of the SDA pin(SDA = 0) for one TBRG while SCL is high. Following
this, the RSEN bit (SSPCON2<1>) will be automatically
cleared and the Baud Rate Generator will not be
reloaded, leaving the SDA pin held low. As soon as aStart condition is detected on the SDA and SCL pins,
the S bit (SSPSTAT<3>) will be set. The SSPIF bit will
not be set until the Baud Rate Generator has timed out.

2: A bus collision during the Repeated Start
condition occurs if:• SDA is sampled low when SCL goesfrom low-to-high.
• SCL goes low before SDA isasserted low. This may indicate that
another master is attempting totransmit a data ‘1’.
Immediately following the SSPIF bit getting set, the user
may write the SSPBUF with the 7-bit address in 7-bit
mode or the default first address in 10-bit mode. After the
first eight bits are transmitted and an ACK is received,
the user may then transmit an additional eight bits ofaddress (10-bit mode) or eight bits of data (7-bit mode).

19.4.9.1

If the user writes the SSPBUF when a Repeated Start
sequence is in progress, the WCOL bit is set and thecontents of the buffer are unchanged (the write doesn’t
occur).
Note:

FIGURE 19-22:

WCOL Status Flag

Because queueing of events is notallowed, writing of the lower five bits ofSSPCON2 is disabled until the RepeatedStart condition is complete.

REPEATED START CONDITION WAVEFORM

Set S (SSPSTAT<3>)
Write to SSPCON2
occurs here.
SDA = 1,
SCL (no change).

SDA = 1,SCL = 1TBRG

At completion of Start bit,
hardware clears RSEN bit
and sets SSPIF

TBRG

TBRG
1st bit

SDA

Write to SSPBUF occurs here

Falling edge of ninth clock,end of Xmit

TBRG

SCL
TBRG
Sr = Repeated Start

DS39632D-page 226

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
19.4.10I2C MASTER MODE
TRANSMISSION

Transmission of a data byte, a 7-bit address, or theother half of a 10-bit address is accomplished by simply
writing a value to the SSPBUF register. This action will
set the Buffer Full flag bit, BF and allow the Baud Rate
Generator to begin counting and start the nexttransmission. Each bit of address/data will be shiftedout onto the SDA pin after the falling edge of SCL isasserted (see data hold time specification
parameter 106). SCL is held low for one Baud Rate
Generator rollover count (TBRG). Data should be valid
before SCL is released high (see data setup time specification parameter 107). When the SCL pin is released
high, it is held that way for TBRG. The data on the SDA
pin must remain stable for that duration and some holdtime after the next falling edge of SCL. After the eighth
bit is shifted out (the falling edge of the eighth clock),the BF flag is cleared and the master releases SDA.
This allows the slave device being addressed torespond with an ACK bit during the ninth bit time if anaddress match occurred, or if data was received
properly. The status of ACK is written into the ACKDT
bit on the falling edge of the ninth clock. If the masterreceives an Acknowledge, the Acknowledge Status bit,
ACKSTAT, is cleared. If not, the bit is set. After the ninth
clock, the SSPIF bit is set and the master clock (BaudRate Generator) is suspended until the next data byte
is loaded into the SSPBUF, leaving SCL low and SDA
unchanged (Figure 19-23).
After the write to the SSPBUF, each bit of the address
will be shifted out on the falling edge of SCL until allseven address bits and the R/W bit are completed. On
the falling edge of the eighth clock, the master will
deassert the SDA pin, allowing the slave to respondwith an Acknowledge. On the falling edge of the ninth
clock, the master will sample the SDA pin to see if theaddress was recognized by a slave. The status of the
ACK bit is loaded into the ACKSTAT status bit(SSPCON2<6>). Following the falling edge of the ninth
clock transmission of the address, the SSPIF is set, theBF flag is cleared and the Baud Rate Generator isturned off until another write to the SSPBUF takes
place, holding SCL low and allowing SDA to float.

The user should verify that the WCOL is clear after
each write to SSPBUF to ensure the transfer is correct.
In all cases, WCOL must be cleared in software.

19.4.10.3

In Transmit mode, the ACKSTAT bit (SSPCON2<6>) is
cleared when the slave has sent an Acknowledge(ACK = 0) and is set when the slave does not Acknowledge (ACK = 1). A slave sends an Acknowledge when
it has recognized its address (including a general call),or when the slave has properly received its data.

19.4.11

BF Status Flag

In Transmit mode, the BF bit (SSPSTAT<0>) is set
when the CPU writes to SSPBUF and is cleared when
all eight bits are shifted out.

19.4.10.2

I2C MASTER MODE RECEPTION

Master mode reception is enabled by programming theReceive Enable bit, RCEN (SSPCON2<3>).
Note:

The MSSP module must be in an Idle state
before the RCEN bit is set or the RCEN bit
will be disregarded.

The Baud Rate Generator begins counting and on eachrollover, the state of the SCL pin changes (high-to-low/
low-to-high) and data is shifted into the SSPSR. Afterthe falling edge of the eighth clock, the receive enable
flag is automatically cleared, the contents of the
SSPSR are loaded into the SSPBUF, the BF flag bit isset, the SSPIF flag bit is set and the Baud Rate Generator is suspended from counting, holding SCL low. The
MSSP is now in Idle state awaiting the next command.
When the buffer is read by the CPU, the BF flag bit isautomatically cleared. The user can then send an
Acknowledge bit at the end of reception by setting the
Acknowledge Sequence Enable bit, ACKEN(SSPCON2<4>).

19.4.11.1

BF Status Flag

In receive operation, the BF bit is set when an address
or data byte is loaded into SSPBUF from SSPSR. It iscleared when the SSPBUF register is read.

19.4.11.2

SSPOV Status Flag

In receive operation, the SSPOV bit is set when eightbits are received into the SSPSR and the BF flag bit isalready set from a previous reception.

19.4.11.3
19.4.10.1

ACKSTAT Status Flag

WCOL Status Flag

If the user writes the SSPBUF when a receive isalready in progress (i.e., SSPSR is still shifting in a databyte), the WCOL bit is set and the contents of the buffer
are unchanged (the write doesn’t occur).

WCOL Status Flag

If the user writes the SSPBUF when a transmit isalready in progress (i.e., SSPSR is still shifting out adata byte), the WCOL bit is set and the contents of thebuffer are unchanged (the write doesn’t occur) after
2 TCY after the SSPBUF write. If SSPBUF is rewritten
within 2 TCY, the WCOL bit is set and SSPBUF is
updated. This may result in a corrupted transfer.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 227

DS39632D-page 228
S

Preliminary
R/W

PEN

SEN

BF (SSPSTAT<0>)

SSPIF

SCL

SDA

A6

A5

A4

A3

A2

A1

3

4

5

Cleared in software

2

6

7

8

9

After Start condition, SEN cleared by hardware

SSPBUF written

1

D7

1
SCL held low
while CPU
responds to SSPIFACK = 0R/W = 0SSPBUF written with 7-bit address and R/Wstart transmit

A7Transmit Address to Slave

3

D5

4

D4

5

D3

6

D2

7

D1

8

D0

SSPBUF is written in software

Cleared in software service routine
from MSSP interrupt

2

D6

Transmitting Data or Second Halfof 10-bit Address

From slave, clear ACKSTAT bit SSPCON2<6>P

Cleared in software

9

ACK

ACKSTAT in
SSPCON2 = 1

FIGURE 19-23:

SEN = 0

Write SSPCON2<0> SEN = 1,
Start condition begins

PIC18F2455/2550/4455/4550
I 2C™ MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)© 2007 Microchip Technology Inc.

© 2007 Microchip Technology Inc.

Preliminary

ACKEN

SSPOV

BF
(SSPSTAT<0>)

SDA = 0, SCL = 1
while CPU
responds to SSPIF

SSPIF

1

SCL

S

A7

SDA

2

4
5

Cleared in software

3

6

A6 A5 A4 A3 A2Transmit Address to Slave

7

A1

8

9

R/W = 1ACK

ACK from Slave

2

3

5

6

7

8

D0

9

ACK

2

3

4

5

6

7

Cleared in software

Set SSPIF interrupt
at end of Acknowledge
sequence

Data shifted in on falling edge of CLK

1

D7 D6 D5 D4 D3 D2 D1Cleared insoftwareSet SSPIF at endof receive

9

ACK is not sent

ACK

P

PEN bit = 1
written here

SSPOV is set because
SSPBUF is still full

8

D0

RCEN cleared
automatically

Set SSPIF interrupt
at end of Acknowledge sequence

Bus masterterminatestransfer

Set P bit
(SSPSTAT<4>)and SSPIF

Set ACKEN, start Acknowledge sequence,
SDA = ACKDT = 1

Receiving Data from Slave

RCEN = 1, startnext receive

ACK from master,
SDA = ACKDT = 0

Last bit is shifted into SSPSR andcontents are unloaded into SSPBUF

Cleared in software

Set SSPIF interrupt
at end of receive

4

Cleared in software

1

D7 D6 D5 D4 D3 D2 D1

Receiving Data from Slave

RCEN cleared
automatically

Master configured as a receiverby programming SSPCON2<3> (RCEN = 1)

FIGURE 19-24:

SEN = 0
Write to SSPBUF occurs here,
start XMIT

Write to SSPCON2<0> (SEN = 1),
begin Start Condition

Write to SSPCON2<4>to start Acknowledge sequence
SDA = ACKDT (SSPCON2<5>) = 0

PIC18F2455/2550/4455/4550

I 2C™ MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)

DS39632D-page 229

PIC18F2455/2550/4455/4550
19.4.12ACKNOWLEDGE SEQUENCE
TIMING

19.4.13

A Stop bit is asserted on the SDA pin at the end of areceive/transmit by setting the Stop Enable bit, PEN(SSPCON2<2>). At the end of a receive/transmit, the
SCL line is held low after the falling edge of the ninth
clock. When the PEN bit is set, the master will assert
the SDA line low. When the SDA line is sampled low,the Baud Rate Generator is reloaded and counts down
to ‘0’. When the Baud Rate Generator times out, theSCL pin will be brought high and one TBRG (Baud Rate
Generator rollover count) later, the SDA pin will bedeasserted. When the SDA pin is sampled high while
SCL is high, the P bit (SSPSTAT<4>) is set. A TBRG
later, the PEN bit is cleared and the SSPIF bit is set(Figure 19-26).

An Acknowledge sequence is enabled by setting the
Acknowledge Sequence Enable bit, ACKEN(SSPCON2<4>). When this bit is set, the SCL pin ispulled low and the contents of the Acknowledge data bit
are presented on the SDA pin. If the user wishes to generate an Acknowledge, then the ACKDT bit should becleared. If not, the user should set the ACKDT bit before
starting an Acknowledge sequence. The Baud Rate
Generator then counts for one rollover period (TBRG)
and the SCL pin is deasserted (pulled high). When the
SCL pin is sampled high (clock arbitration), the Baud
Rate Generator counts for TBRG. The SCL pin is thenpulled low. Following this, the ACKEN bit is automatically
cleared, the Baud Rate Generator is turned off and the
MSSP module then goes into an inactive state(Figure 19-25).

19.4.12.1

19.4.13.1

WCOL Status Flag

If the user writes the SSPBUF when a Stop sequenceis in progress, then the WCOL bit is set and thecontents of the buffer are unchanged (the write doesn’t
occur).

WCOL Status Flag

If the user writes the SSPBUF when an Acknowledge
sequence is in progress, then WCOL is set and thecontents of the buffer are unchanged (the write doesn’t
occur).

FIGURE 19-25:

STOP CONDITION TIMINGACKNOWLEDGE SEQUENCE WAVEFORM

Acknowledge sequence starts here,
write to SSPCON2
ACKEN = 1, ACKDT = 0
SDA

D0

SCL

8

ACKEN automatically cleared
TBRG

TBRG
ACK
9

SSPIF
Set SSPIF at theend of receive

Cleared insoftwareCleared insoftwareSet SSPIF at the endof Acknowledge sequence

Note: TBRG = one Baud Rate Generator period.

FIGURE 19-26:

STOP CONDITION RECEIVE OR TRANSMIT MODE
Write to SSPCON2,
set PENSCL = 1 for TBRG, followed by SDA = 1 for TBRG
after SDA sampled high. P bit (SSPSTAT<4>) is set.

Falling edge ofninth clock

PEN bit (SSPCON2<2>) is cleared byhardware and the SSPIF bit is set
TBRG

SCL

SDA

ACK
P
TBRG

TBRG

TBRG

SCL brought high after TBRG
SDA asserted low before rising edge of clock
to setup Stop condition

Note: TBRG = one Baud Rate Generator period.

DS39632D-page 230

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
19.4.14SLEEP OPERATION

19.4.172

While in Sleep mode, the I C module can receive
addresses or data and when an address match orcomplete byte transfer occurs, wake the processor
from Sleep (if the MSSP interrupt is enabled).

19.4.15

Multi-Master mode support is achieved by bus arbitration. When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
outputs a ‘1’ on SDA, by letting SDA float high andanother master asserts a ‘0’. When the SCL pin floats
high, data should be stable. If the expected data on
SDA is a ‘1’ and the data sampled on the SDA pin = 0,then a bus collision has taken place. The master will set
the Bus Collision Interrupt Flag, BCLIF and reset theI2C port to its Idle state (Figure 19-27).

EFFECTS OF A RESET

A Reset disables the MSSP module and terminates thecurrent transfer.

19.4.16

MULTI -MASTER COMMUNICATION,
BUS COLLISION AND BUS
ARBITRATIONMULTI-MASTER MODE

In Multi-Master mode, the interrupt generation on thedetection of the Start and Stop conditions allows thedetermination of when the bus is free. The Stop (P) andStart (S) bits are cleared from a Reset or when the
MSSP module is disabled. Control of the I 2C bus may
be taken when the P bit (SSPSTAT<4>) is set, or thebus is Idle, with both the S and P bits clear. When thebus is busy, enabling the MSSP interrupt will generate
the interrupt when the Stop condition occurs.

If a transmit was in progress when the bus collisionoccurred, the transmission is halted, the BF flag iscleared, the SDA and SCL lines are deasserted and the
SSPBUF can be written to. When the user services thebus collision Interrupt Service Routine and if the I2C
bus is free, the user can resume communication byasserting a Start condition.

In multi-master operation, the SDA line must be
monitored for arbitration to see if the signal level is the
expected output level. This check is performed in
hardware with the result placed in the BCLIF bit.

If a Start, Repeated Start, Stop or Acknowledge
condition was in progress when the bus collisionoccurred, the condition is aborted, the SDA and SCL
lines are deasserted and the respective control bits in
the SSPCON2 register are cleared. When the user services the bus collision Interrupt Service Routine and if
the I2C bus is free, the user can resume communication
by asserting a Start condition.

The states where arbitration can be lost are:• Address Transfer• Data Transfer• A Start Condition• A Repeated Start Condition• An Acknowledge Condition

The master will continue to monitor the SDA and SCL
pins. If a Stop condition occurs, the SSPIF bit will be set.
A write to the SSPBUF bit will start the transmission ofdata at the first data bit regardless of where thetransmitter left off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on thedetection of Start and Stop conditions allows the determination of when the bus is free. Control of the I2C bus canbe taken when the P bit is set in the SSPSTAT register,or the bus is Idle and the S and P bits are cleared.

FIGURE 19-27:

BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
Data changes
while SCL = 0

SDA line pulled low
by another source
SDA releasedby master

Sample SDA. While SCL is high,data doesn’t match what is driven
by the master.
Bus collision has occurred.

SDA

SCL

Set Bus CollisionInterrupt Flag (BCLIF)

BCLIF© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 231

PIC18F2455/2550/4455/4550
19.4.17.1

Bus Collision During a Start
Condition

During a Start condition, a bus collision occurs if:a)b)

SDA or SCL are sampled low at the beginning of
the Start condition (Figure 19-28).
SCL is sampled low before SDA is asserted low(Figure 19-29).

During a Start condition, both the SDA and the SCL
pins are monitored.

If the SDA pin is sampled low during this count, theBRG is reset and the SDA line is asserted early(Figure 19-30). If, however, a ‘1’ is sampled on the SDA
pin, the SDA pin is asserted low at the end of the BRG
count. The Baud Rate Generator is then reloaded andcounts down to ‘0’. If the SCL pin is sampled as ‘0’,during this time a bus collision does not occur. At theend of the BRG count, the SCL pin is asserted low.
Note:

If the SDA pin is already low, or the SCL pin is alreadylow, then all of the following occur:• the Start condition is aborted,• the BCLIF flag is set and• the MSSP module is reset to its inactive state(Figure 19-28).
The Start condition begins with the SDA and SCL pins
deasserted. When the SDA pin is sampled high, theBaud Rate Generator is loaded from SSPADD<6:0>
and counts down to ‘0’. If the SCL pin is sampled low
while SDA is high, a bus collision occurs because it isassumed that another master is attempting to drive adata ‘1’ during the Start condition.

FIGURE 19-28:

The reason that bus collision is not a factor
during a Start condition is that no two bus
masters can assert a Start condition at theexact same time. Therefore, one masterwill always assert SDA before the other.
This condition does not cause a bus
collision because the two masters must beallowed to arbitrate the first address
following the Start condition. If the addressis the same, arbitration must be allowed tocontinue into the data portion, RepeatedStart or Stop conditions.

BUS COLLISION DURING START CONDITION (SDA ONLY)SDA goes low before the SEN bit is set.
Set BCLIF,
S bit and SSPIF set because
SDA = 0, SCL = 1.

SDA

SCL
Set SEN, enable Start
condition if SDA = 1, SCL = 1

SEN cleared automatically because of bus collision.
MSSP module reset into Idle state.

SEN

BCLIF

SDA sampled low before
Start condition. Set BCLIF.
S bit and SSPIF set because
SDA = 0, SCL = 1.
SSPIF and BCLIF arecleared in software

S

SSPIF

SSPIF and BCLIF arecleared in software

DS39632D-page 232

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
FIGURE 19-29:

BUS COLLISION DURING START CONDITION (SCL = 0)
SDA = 0, SCL = 1
TBRG

TBRG

SDA

Set SEN, enable Start
sequence if SDA = 1, SCL = 1

SCL

SCL = 0 before SDA = 0,bus collision occurs. Set BCLIF.

SEN
SCL = 0 before BRG time-out,bus collision occurs. Set BCLIF.
BCLIFInterrupt clearedin software
S

‘0’

‘0’

SSPIF

‘0’

‘0’

FIGURE 19-30:

BRG RESET DUE TO SDA ARBITRATION DURING START CONDITIONSDA = 0, SCL = 1
Set S
Less than TBRG

SDA

Set SSPIFTBRG

SDA pulled low by other master.
Reset BRG and assert SDA.

SCLSSCL pulled low after BRG
time-out

SEN

BCLIF

Set SEN, enable Start
sequence if SDA = 1, SCL = 1

‘0’

S

SSPIF
SDA = 0, SCL = 1,
set SSPIF© 2007 Microchip Technology Inc.

Preliminary

Interrupts clearedin software

DS39632D-page 233

PIC18F2455/2550/4455/4550
19.4.17.2

Bus Collision During a RepeatedStart Condition

If SDA is low, a bus collision has occurred (i.e., anothermaster is attempting to transmit a data ‘0’, see
Figure 19-31). If SDA is sampled high, the BRG isreloaded and begins counting. If SDA goes from high-tolow before the BRG times out, no bus collision occurs
because no two masters can assert SDA at exactly thesame time.

During a Repeated Start condition, a bus collisionoccurs if:a)b)

A low level is sampled on SDA when SCL goesfrom low level to high level.
SCL goes low before SDA is asserted low,indicating that another master is attempting totransmit a data ‘1’.

If SCL goes from high-to-low before the BRG times out
and SDA has not already been asserted, a bus collisionoccurs. In this case, another master is attempting totransmit a data ‘1’ during the Repeated Start condition(see Figure 19-32).

When the user deasserts SDA and the pin is allowed tofloat high, the BRG is loaded with SSPADD<6:0> andcounts down to ‘0’. The SCL pin is then deasserted andwhen sampled high, the SDA pin is sampled.

FIGURE 19-31:

If, at the end of the BRG time-out, both SCL and SDA
are still high, the SDA pin is driven low and the BRG isreloaded and begins counting. At the end of the count,regardless of the status of the SCL pin, the SCL pin isdriven low and the Repeated Start condition iscomplete.

BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)

SDA

SCL
Sample SDA when SCL goes high.
If SDA = 0, set BCLIF and release SDA and SCL.
RSEN

BCLIF
Cleared in software
S

‘0’

SSPIF

‘0’

FIGURE 19-32:

BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
TBRG

TBRG

SDA
SCL

BCLIF

SCL goes low before SDA,
set BCLIF. Release SDA and SCL.
Interrupt clearedin software

RSEN
‘0’

S
SSPIF

DS39632D-page 234

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
19.4.17.3

Bus Collision During a Stop
Condition

The Stop condition begins with SDA asserted low.
When SDA is sampled low, the SCL pin is allowed tofloat. When the pin is sampled high (clock arbitration),the Baud Rate Generator is loaded with SSPADD<6:0>
and counts down to ‘0’. After the BRG times out, SDA
is sampled. If SDA is sampled low, a bus collision has
occurred. This is due to another master attempting todrive a data ‘0’ (Figure 19-33). If the SCL pin is
sampled low before SDA is allowed to float high, a bus
collision occurs. This is another case of another masterattempting to drive a data ‘0’ (Figure 19-34).

Bus collision occurs during a Stop condition if:a)b)After the SDA pin has been deasserted andallowed to float high, SDA is sampled low after
the BRG has timed out.
After the SCL pin is deasserted, SCL is sampled
low before SDA goes high.

FIGURE 19-33:

BUS COLLISION DURING A STOP CONDITION (CASE 1)
TBRG

TBRG

TBRG

SDA sampled
low after TBRG,
set BCLIFSDA
SDA asserted low
SCL
PEN
BCLIF
P

‘0’

SSPIF

‘0’

FIGURE 19-34:

BUS COLLISION DURING A STOP CONDITION (CASE 2)
TBRG

TBRG

TBRG

SDA
SCL goes low before SDA goes high,set BCLIF

Assert SDA
SCL
PEN
BCLIF
P

‘0’

SSPIF

‘0’

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 235

PIC18F2455/2550/4455/4550
TABLE 19-4:
Name

REGISTERS ASSOCIATED WITH I2C™ OPERATION
Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset
Valueson Page

INTCON

GIE/GIEH PEIE/GIEL

TMR0IEINT0IERBIE

TMR0IF

INT0IF

RBIF

51

PIR1

SPPIF(1)

ADIF

RCIF

TXIF

SSPIF

CCP1IF

TMR2IF

TMR1IF54

PIE1

SPPIE(1)

ADIE

RCIE

TXIE

SSPIE

CCP1IETMR2IETMR1IE

54

IPR1

(1)

SPPIP

ADIP

RCIP

TXIP

SSPIP

CCP1IP

TMR2IP

TMR1IP54

PIR2

OSCFIF

CMIF

USBIF

EEIF

BCLIF

HLVDIF

TMR3IF

CCP2IF54

PIE2

OSCFIE

CMIE

USBIE

EEIE

BCLIE

HLVDIETMR3IECCP2IE54

IPR2

OSCFIP

CMIP

USBIP

EEIP

BCLIP

HLVDIP

TMR3IP

CCP2IP

54——

TRISC2

TRISC1

TRISC054

TRISD4

TRISD3

TRISD2

TRISD1

TRISD054

TRISC

TRISC7

TRISC6—

TRISD(1)

TRISD7

TRISD6

TRISD5SSPBUFMSSP Receive Buffer/Transmit Register

52

SSPADDMSSP Address Register in I2C Slave mode.
MSSP Baud Rate Reload Register in I2C Master mode.

52

TMR2

Timer2 Register

52

PR2

Timer2 Period Register

52

SSPCON1

WCOL

SSPOV

SSPEN

CKP

SSPM3

SSPM2

SSPM1

SSPM0

52

SSPCON2GCEN

ACKSTAT

ACKDT

ACKEN

RCEN

PEN

RSEN

SEN

52

SSPSTAT

SMP

CKE

D/A

P

S

R/W

UA

BF

52

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in I2C™ mode.
Note 1: These registers or bits are not implemented in 28-pin devices.

DS39632D-page 236

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
20.0

ENHANCED UNIVERSALSYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (EUSART)The Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART) module is one of thetwo serial I/O modules. (Generically, the USART is also
known as a Serial Communications Interface or SCI.)The EUSART can be configured as a full-duplex
asynchronous system that can communicate with
peripheral devices, such as CRT terminals andpersonal computers. It can also be configured as a halfduplex synchronous system that can communicate
with peripheral devices, such as A/D or D/A integrated
circuits, serial EEPROMs, etc.
The Enhanced USART module implements additionalfeatures, including automatic baud rate detection andcalibration, automatic wake-up on Sync Break reception and 12-bit Break character transmit. These make itideally suited for use in Local Interconnect Network bus(LIN bus) systems.

The pins of the Enhanced USART are multiplexedwith PORTC. In order to configure RC6/TX/CK and
RC7/RX/DT/SDO as an EUSART:• bit SPEN (RCSTA<7>) must be set (= 1)• bit TRISC<7> must be set (= 1)• bit TRISC<6> must be set (= 1)Note:

The EUSART control will automaticallyreconfigure the pin from input to output asneeded.

The operation of the Enhanced USART module iscontrolled through three registers:• Transmit Status and Control (TXSTA)• Receive Status and Control (RCSTA)• Baud Rate Control (BAUDCON)
These are detailed on the following pages inRegister 20-1, Register 20-2 and Register 20-3,
respectively.

The EUSART can be configured in the following
modes:• Asynchronous (full-duplex) with:- Auto-wake-up on Break signal- Auto-baud calibration- 12-bit Break character transmission• Synchronous – Master (half-duplex) withselectable clock polarity• Synchronous – Slave (half-duplex) with selectableclock polarity© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 237

PIC18F2455/2550/4455/4550
REGISTER 20-1:

TXSTA: TRANSMIT STATUS AND CONTROL REGISTER

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R-1

R/W-0

CSRC

TX9

TXEN(1)

SYNC

SENDB

BRGH

TRMT

TX9D

bit 7

bit 0

Legend:R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’-n = Value at POR‘1’ = Bit is set‘0’ = Bit is clearedx = Bit is unknown

bit 7

CSRC: Clock Source Select bit
Asynchronous mode:
Don’t care.
Synchronous mode:
1 = Master mode (clock generated internally from BRG)
0 = Slave mode (clock from external source)

bit 6

TX9: 9-Bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission

bit 5

TXEN: Transmit Enable bit(1)1 = Transmit enabled
0 = Transmit disabled

bit 4

SYNC: EUSART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode

bit 3

SENDB: Send Break Character bit
Asynchronous mode:
1 = Send Sync Break on next transmission (cleared by hardware upon completion)
0 = Sync Break transmission completed
Synchronous mode:
Don’t care.

bit 2

BRGH: High Baud Rate Select bit
Asynchronous mode:
1 = High speed
0 = Low speed
Synchronous mode:
Unused in this mode.

bit 1

TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR fullbit 0

TX9D: 9th bit of Transmit Data
Can be address/data bit or a parity bit.

Note 1:

SREN/CREN overrides TXEN in Sync mode with the exception that SREN has no effect in Synchronous
Slave mode.

DS39632D-page 238

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
REGISTER 20-2:

RCSTA: RECEIVE STATUS AND CONTROL REGISTER

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R-0

R-0

R-x

SPEN

RX9

SREN

CREN

ADDEN

FERR

OERR

RX9D

bit 7

bit 0

Legend:R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’-n = Value at POR‘1’ = Bit is set‘0’ = Bit is clearedx = Bit is unknown

bit 7

SPEN: Serial Port Enable bit
1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins)
0 = Serial port disabled (held in Reset)

bit 6

RX9: 9-Bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception

bit 5

SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care.
Synchronous mode – Master:
1 = Enables single receive
0 = Disables single receive
This bit is cleared after reception is complete.
Synchronous mode – Slave:Don’t care.

bit 4

CREN: Continuous Receive Enable bit
Asynchronous mode:
1 = Enables receiver
0 = Disables receiver
Synchronous mode:
1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0 = Disables continuous receive

bit 3

ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1 = Enables address detection, enables interrupt and loads the receive buffer when RSR<8> is set
0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit
Asynchronous mode 9-bit (RX9 = 0):
Don’t care.

bit 2

FERR: Framing Error bit
1 = Framing error (can be updated by reading RCREG register and receiving next valid byte)
0 = No framing error

bit 1

OERR: Overrun Error bit
1 = Overrun error (can be cleared by clearing bit CREN)
0 = No overrun error

bit 0

RX9D: 9th bit of Received Data
This can be address/data bit or a parity bit and must be calculated by user firmware.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 239

PIC18F2455/2550/4455/4550
REGISTER 20-3:

BAUDCON: BAUD RATE CONTROL REGISTER

R/W-0

R-1

R/W-0

R/W-0

R/W-0

U-0

R/W-0

R/W-0

ABDOVF

RCIDL

RXDTP

TXCKP

BRG16

—

WUE

ABDEN

bit 7

bit 0

Legend:R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’-n = Value at POR‘1’ = Bit is set‘0’ = Bit is clearedx = Bit is unknown

bit 7

ABDOVF: Auto-Baud Acquisition Rollover Status bit
1 = A BRG rollover has occurred during Auto-Baud Rate Detect mode (must be cleared in software)
0 = No BRG rollover has occurred

bit 6

RCIDL: Receive Operation Idle Status bit
1 = Receive operation is Idle
0 = Receive operation is active

bit 5

RXDTP: Received Data Polarity Select bit
Asynchronous mode:
1 = RX data is inverted
0 = RX data received is not inverted
Synchronous modes:
1 = CK clocks are inverted
0 = CK clocks are not inverted

bit 4

TXCKP: Clock and Data Polarity Select bit
Asynchronous mode:
1 = TX data is inverted
0 = TX data is not inverted
Synchronous modes:
1 = CK clocks are inverted
0 = CK clocks are not inverted

bit 3

BRG16: 16-Bit Baud Rate Register Enable bit
1 = 16-bit Baud Rate Generator – SPBRGH and SPBRG
0 = 8-bit Baud Rate Generator – SPBRG only (Compatible mode), SPBRGH value ignored

bit 2

Unimplemented: Read as ‘0’

bit 1

WUE: Wake-up Enable bit
Asynchronous mode:
1 = EUSART will continue to sample the RX pin – interrupt generated on falling edge; bit cleared in
hardware on following rising edge
0 = RX pin not monitored or rising edge detected
Synchronous mode:
Unused in this mode.

bit 0

ABDEN: Auto-Baud Detect Enable bit
Asynchronous mode:
1 = Enable baud rate measurement on the next character. Requires reception of a Sync field (55h);
cleared in hardware upon completion.
0 = Baud rate measurement disabled or completed
Synchronous mode:
Unused in this mode.

DS39632D-page 240

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
20.1

Baud Rate Generator (BRG)

The BRG is a dedicated 8-bit, or 16-bit, generator that
supports both the Asynchronous and Synchronousmodes of the EUSART. By default, the BRG operates
in 8-bit mode. Setting the BRG16 bit (BAUDCON<3>)selects 16-bit mode.
The SPBRGH:SPBRG register pair controls the periodof a free-running timer. In Asynchronous mode, bits
BRGH (TXSTA<2>) and BRG16 (BAUDCON<3>) also
control the baud rate. In Synchronous mode, BRGH is
ignored. Table 20-1 shows the formula for computationof the baud rate for different EUSART modes which
only apply in Master mode (internally generated clock).
Given the desired baud rate and FOSC, the nearest
integer value for the SPBRGH:SPBRG registers can becalculated using the formulas in Table 20-1. From this,the error in baud rate can be determined. An example
calculation is shown in Example 20-1. Typical baudrates and error values for the various Asynchronousmodes are shown in Table 20-2. It may be advantageous

TABLE 20-1:

to use the high baud rate (BRGH = 1), or the 16-bit BRG
to reduce the baud rate error, or achieve a slow baudrate for a fast oscillator frequency.
Writing a new value to the SPBRGH:SPBRG registers
causes the BRG timer to be reset (or cleared). This
ensures the BRG does not wait for a timer overflow
before outputting the new baud rate.

20.1.1OPERATION IN POWER-MANAGED
MODES

The device clock is used to generate the desired baudrate. When one of the power-managed modes isentered, the new clock source may be operating at adifferent frequency. This may require an adjustment tothe value in the SPBRG register pair.

20.1.2

SAMPLING

The data on the RX pin is sampled three times by amajority detect circuit to determine if a high or a low
level is present at the RX pin.

BAUD RATE FORMULAS

Configuration Bits

BRG/EUSART Mode

Baud Rate Formula

8-bit/Asynchronous

FOSC/[64 (n + 1)]

SYNC

BRG16

BRGH

0

0

0

0

0

1

8-bit/Asynchronous

0

1

0

16-bit/Asynchronous

0

1

1

16-bit/Asynchronous

1

0

x

8-bit/Synchronous

1

1

x

16-bit/Synchronous

FOSC/[16 (n + 1)]

FOSC/[4 (n + 1)]

Legend: x = Don’t care, n = value of SPBRGH:SPBRG register pair

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 241

PIC18F2455/2550/4455/4550
EXAMPLE 20-1:

CALCULATING BAUD RATE ERROR

For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG:
Desired Baud Rate
= FOSC/(64 ([SPBRGH:SPBRG] + 1))
Solving for SPBRGH:SPBRG:
X= ((FOSC/Desired Baud Rate)/64) – 1= ((16000000/9600)/64) – 1= [25.042] = 25
Calculated Baud Rate = 16000000/(64 (25 + 1))= 9615Error= (Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate
= (9615 – 9600)/9600 = 0.16%

TABLE 20-2:

REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset Values
on page

TXSTA

CSRC

TX9

TXEN

SYNC

SENDB

BRGH

TRMT

TX9D

53

RCSTA

SPEN

RX9

SREN

CREN

ADDEN

FERR

OERR

RX9D

53

BAUDCON ABDOVF

RCIDL

RXDTP

TXCKP

BRG16

—

WUE

ABDEN

53

Name

SPBRGHEUSART Baud Rate Generator Register High Byte

53

SPBRG

EUSART Baud Rate Generator Register Low Byte

53

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the BRG.

DS39632D-page 242

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
TABLE 20-3:

BAUD RATES FOR ASYNCHRONOUS MODESSYNC = 0, BRGH = 0, BRG16 = 0

BAUD
RATE
(K)

FOSC = 40.000 MHz

FOSC = 20.000 MHz
ActualRate(K)

FOSC = 10.000 MHz
ActualRate(K)

FOSC = 8.000 MHz
ActualRate(K)

Actual
Rate
(K)

%
Error

0.3

—

—

—

—

—

—

—

—

—

—

—

—

1.2

—

—

—

1.221

1.73

255

1.202

0.16

129

1201

-0.16

103

2.4

2.441

1.73

255

2.404

0.16

129

2.404

0.16

64

2403

-0.16

51

9.6

9.615

0.16

64

9.766

1.73

31

9.766

1.73

15

9615

-0.16

12
—

SPBRG
value
(decimal)

%
Error

SPBRG
value
(decimal)

%
Error

SPBRG
value
(decimal)

%
Error

SPBRG
value
(decimal)

19.2

19.5311.73

31

19.5311.73

15

19.531

1.73

7

—

—

57.6

56.818-1.36

1062.5008.51

452.083

-9.58

2

—

—

—

115.2

125.000

8.51

4

104.167-9.58

2

78.125-32.181———

SYNC = 0, BRGH = 0, BRG16 = 0
BAUD
RATE
(K)

FOSC = 4.000 MHz

FOSC = 2.000 MHz
Actual
Rate
(K)

%
Error

207

300

-0.16

51

1201

-0.16

0.16

25

2403

Actual
Rate
(K)

%
Error

0.3

0.300

0.16

1.2

1.202

0.16

2.4

2.404

SPBRG
value
(decimal)

FOSC = 1.000 MHz
Actual
Rate
(K)

%
Error

103

300

-0.16

51

25

1201

-0.16

12

-0.16

12

—

—

—

SPBRG
value
(decimal)

SPBRG
value
(decimal)

9.6

8.929

-6.99

6

—

—

—

—

—

—

19.2

20.833

8.51

2

—

—

—

—

—

—

57.6

62.500

8.51

0

—

—

—

—

—

—

115.2

62.500-45.75

0

—

—

—

—

—

—

SYNC = 0, BRGH = 1, BRG16 = 0
BAUD
RATE
(K)

FOSC = 40.000 MHz

FOSC = 20.000 MHz(decimal)Actual
Rate
(K)

%
Error

—

—

—

—

—

—

—

—

—

9.6

9.766

1.73

19.2

19.231

0.16

Actual
Rate
(K)

%
Error

0.3

—

1.2

—

2.4

FOSC = 10.000 MHz(decimal)Actual
Rate
(K)

%
Error

—

—

—

—

—

—

—

—

—

255

9.615

0.16

129

19.231

0.16

SPBRG
value

FOSC = 8.000 MHz(decimal)Actual
Rate
(K)

%
Error

—

—

—

—

—

—

—

—

—

2.441

1.73

255

2403

-0.16

207

129

9.615

0.16

64

9615

-0.16

51

64

19.531

1.73

31

19230

-0.16

25

SPBRG
value

SPBRG
value

SPBRG
value
(decimal)—

57.6

58.1400.94

4256.818-1.36

2156.818

-1.36

10

55555

3.55

8

115.2

113.636-1.36

21

113.636-1.36

10125.000

8.51

4

—

—

—

SYNC = 0, BRGH = 1, BRG16 = 0
BAUD
RATE
(K)

FOSC = 4.000 MHz

FOSC = 2.000 MHz(decimal)Actual
Rate
(K)

%
Error

—
0.16

—
207

—
1201

0.16

103

Actual
Rate
(K)

%
Error

0.3
1.2

—
1.202

2.4

2.404

SPBRG
value

FOSC = 1.000 MHz(decimal)Actual
Rate
(K)

%
Error

—
-0.16

—
103

300
1201

-0.16
-0.16

207
51

2403

-0.16

51

2403

-0.16

25

SPBRG
value

SPBRG
value
(decimal)

9.6

9.615

0.16

25

9615

-0.16

12

—

—

—

19.2

19.231

0.16

12

—

—

—

—

—

—

57.6

62.500

8.51

3

—

—

—

—

—

—

115.2

125.000

8.51

1

—

—

—

—

—

—

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 243

PIC18F2455/2550/4455/4550
TABLE 20-3:

BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)SYNC = 0, BRGH = 0, BRG16 = 1

BAUD
RATE
(K)

FOSC = 40.000 MHz

FOSC = 20.000 MHz(decimal)Actual
Rate
(K)

%
Error

0.00
0.02

8332
2082

0.300
1.200

2.402

0.06

1040

Actual
Rate
(K)

%
Error

0.3
1.2

0.300
1.200

2.4

SPBRG
value

FOSC = 10.000 MHz(decimal)Actual
Rate
(K)

%
Error

0.02
-0.03

4165
1041

0.300
1.200

2.399

-0.03

520

SPBRG
value

FOSC = 8.000 MHz(decimal)Actual
Rate
(K)

%
Error

0.02
-0.03

2082
520

300
1201

-0.04
-0.16

1665
415

2.404

0.16

259

2403

-0.16

207

SPBRG
value

SPBRG
value
(decimal)

9.6

9.615

0.16

259

9.615

0.16

129

9.615

0.16

64

9615

-0.16

51

19.2

19.2310.16

12919.2310.16

6419.531

1.73

31

19230

-0.16

25

57.6

58.1400.94

4256.818-1.36

2156.818

-1.36

10

55555

3.55

8

115.2

113.636-1.36

21

113.636-1.36

10125.000

8.51

4

—

—

—

SYNC = 0, BRGH = 0, BRG16 = 1
BAUD
RATE
(K)

FOSC = 4.000 MHz(decimal)Actual
Rate
(K)

%
Error

832

300

-0.16

0.16

207

1201

0.16

103

2403

Actual
Rate
(K)

%
Error

0.300

0.04

1.2

1.202

2.4

2.404

0.3

FOSC = 2.000 MHz

SPBRG
value

FOSC = 1.000 MHz(decimal)Actual
Rate
(K)

%
Error

415

300

-0.16

-0.16

103

1201

-0.16

51

-0.16

51

2403

-0.16

25

SPBRG
value

SPBRG
value
(decimal)

207

9.6

9.615

0.16

25

9615

-0.16

12

—

—

—

19.2

19.231

0.16

12

—

—

—

—

—

—

57.6

62.500

8.51

3

—

—

—

—

—

—

115.2

125.000

8.51

1

—

—

—

—

—

—

SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1
BAUD
RATE
(K)

FOSC = 40.000 MHz

FOSC = 20.000 MHz
ActualRate(K)

Actual
Rate
(K)

%
Error

0.3

0.300

0.00

33332

0.300

1.2

1.200

0.00

8332

1.200

SPBRG
value
(decimal)

FOSC = 10.000 MHz

FOSC = 8.000 MHz(decimal)Actual
Rate
(K)

%
Error

0.00

16665

0.300

0.00

8332

300

-0.01

6665

0.02

4165

1.200

0.02

2082

1200

-0.04

1665

%
Error

SPBRG
value

SPBRG
value
(decimal)Actual
Rate
(K)

%
Error

SPBRG
value
(decimal)

2.4

2.400

0.02

4165

2.400

0.02

2082

2.402

0.06

1040

2400

-0.04

832

9.6

9.606

0.06

1040

9.596

-0.03

520

9.615

0.16

259

9615

-0.16

207

19.2

19.193-0.03

520

19.2310.16

259

19.231

0.16

129

19230

-0.16

103

57.6

57.8030.35

172

57.471-0.22

8658.140

0.94

42

57142

0.79

34

115.2

114.943-0.22

86116.2790.94

42113.636-1.3621117647-2.12

16

SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1
BAUD
RATE
(K)

FOSC = 4.000 MHz
Actual
Rate
(K)

%
Error

0.3

0.300

0.01

1.2

1.200

0.04

FOSC = 2.000 MHz(decimal)Actual
Rate
(K)

%
Error

3332

300

-0.04

832

1201

SPBRG
value

FOSC = 1.000 MHz(decimal)Actual
Rate
(K)

%
Error

1665

300

-0.04

832

-0.16

415

1201

-0.16

207

SPBRG
value

SPBRG
value
(decimal)

2.4

2.404

0.16

415

2403

-0.16

207

2403

-0.16

103

9.6

9.615

0.16

103

9615

-0.16

51

9615

-0.16

25

19.2

19.231

0.16

51

19230

-0.16

25

19230

-0.16

12

57.6

58.824

2.12

16

55555

3.55

8

—

—

—

115.2

111.111

-3.55

8

—

—

—

—

—

—

DS39632D-page 244

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
20.1.3

AUTO-BAUD RATE DETECTThe Enhanced USART module supports the automatic
detection and calibration of baud rate. This feature is
active only in Asynchronous mode and while the WUE
bit is clear.

Note 1: If the WUE bit is set with the ABDEN bit,
Auto-Baud Rate Detection will occur on
the byte following the Break character.
2: It is up to the user to determine that theincoming character baud rate is within therange of the selected BRG clock source.
Some combinations of oscillator frequency
and EUSART baud rates are not possible
due to bit error rates. Overall systemtiming and communication baud rates
must be taken into consideration whenusing the Auto-Baud Rate Detection
feature.

The automatic baud rate measurement sequence(Figure 20-1) begins whenever a Start bit is received
and the ABDEN bit is set. The calculation isself-averaging.
In the Auto-Baud Rate Detect (ABD) mode, the clock to
the BRG is reversed. Rather than the BRG clocking theincoming RX signal, the RX signal is timing the BRG. In
ABD mode, the internal Baud Rate Generator is used
as a counter to time the bit period of the incoming serial
byte stream.
Once the ABDEN bit is set, the state machine will clear
the BRG and look for a Start bit. The Auto-Baud Rate
Detect must receive a byte with the value 55h (ASCII“U”, which is also the LIN bus Sync character) in order tocalculate the proper bit rate. The measurement is takenover both a low and a high bit time in order to minimize
any effects caused by asymmetry of the incoming signal.
After a Start bit, the SPBRG begins counting up, using
the preselected clock source on the first rising edge of
RX. After eight bits on the RX pin, or the fifth rising edge,
an accumulated value totalling the proper BRG period isleft in the SPBRGH:SPBRG register pair. Once the 5thedge is seen (this should correspond to the Stop bit), the
ABDEN bit is automatically cleared.
If a rollover of the BRG occurs (an overflow from FFFFh
to 0000h), the event is trapped by the ABDOVF status
bit (BAUDCON<7>). It is set in hardware by BRG
rollovers and can be set or cleared by the user insoftware. ABD mode remains active after rollover
events and the ABDEN bit remains set (Figure 20-2).

TABLE 20-4:
BRG16

BRGH

BRG COUNTER
CLOCK RATESBRG Counter Clock00

FOSC/512

01

FOSC/128

1

0

FOSC/128

1

1

FOSC/32

Note:

During the ABD sequence, SPBRG andSPBRGH are both used as a 16-bit counter,
independent of the BRG16 setting.

20.1.3.1

ABD and EUSART Transmission

Since the BRG clock is reversed during ABD acquisition, the EUSART transmitter cannot be used during
ABD. This means that whenever the ABDEN bit is set,
TXREG cannot be written to. Users should also ensurethat ABDEN does not become set during a transmit
sequence. Failing to do this may result in unpredictable
EUSART operation.

While calibrating the baud rate period, the BRG
registers are clocked at 1/8th the preconfigured clock
rate. Note that the BRG clock will be configured by the
BRG16 and BRGH bits. Independent of the BRG16 bit
setting, both the SPBRG and SPBRGH will be used asa 16-bit counter. This allows the user to verify that no
carry occurred for 8-bit modes by checking for 00h in
the SPBRGH register. Refer to Table 20-4 for counterclock rates to the BRG.
While the ABD sequence takes place, the EUSART
state machine is held in Idle. The RCIF interrupt is set
once the fifth rising edge on RX is detected. The value
in the RCREG needs to be read to clear the RCIF
interrupt. The contents of RCREG should be discarded.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 245

PIC18F2455/2550/4455/4550
FIGURE 20-1:
BRG Value

AUTOMATIC BAUD RATE CALCULATIONXXXXhRX pin

0000h

001Ch

Start

Edge #1
bit 1
bit 0

Edge #2
bit 3
bit 2

Edge #3
bit 5
bit 4

Edge #4
bit 7
bit 6

Edge #5
Stop bit

BRG ClockAuto-Cleared

Set by User
ABDEN bit
RCIF bit(Interrupt)
Read
RCREG
SPBRG

XXXXh

1Ch

SPBRGH

XXXXh

00h

Note: The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE = 0.

FIGURE 20-2:

BRG OVERFLOW SEQUENCE

BRG Clock
ABDEN bit
RX pin

Start

bit 0

ABDOVF bit
FFFFh
BRG Value

DS39632D-page 246

XXXXh

0000h

0000h

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
20.2

EUSART Asynchronous Mode

The Asynchronous mode of operation is selected byclearing the SYNC bit (TXSTA<4>). In this mode, the
EUSART uses standard Non-Return-to-Zero (NRZ)
format (one Start bit, eight or nine data bits and one
Stop bit). The most common data format is 8 bits. An
on-chip dedicated 8-bit/16-bit Baud Rate Generator
can be used to derive standard baud rate frequencies
from the oscillator.
The EUSART transmits and receives the LSb first. The
EUSART’s transmitter and receiver are functionallyindependent but use the same data format and baudrate. The Baud Rate Generator produces a clock, either
x16 or x64 of the bit shift rate depending on the BRGH
and BRG16 bits (TXSTA<2> and BAUDCON<3>). Parity
is not supported by the hardware but can be
implemented in software and stored as the 9th data bit.

Once the TXREG register transfers the data to the TSR
register (occurs in one TCY), the TXREG register is empty
and the TXIF flag bit (PIR1<4>) is set. This interrupt canbe enabled or disabled by setting or clearing the interrupt
enable bit, TXIE (PIE1<4>). TXIF will be set regardless ofthe state of TXIE; it cannot be cleared in software. TXIF
is also not cleared immediately upon loading TXREG, but
becomes valid in the second instruction cycle following
the load instruction. Polling TXIF immediately following aload of TXREG will return invalid results.
While TXIF indicates the status of the TXREG register,
another bit, TRMT (TXSTA<1>), shows the status of
the TSR register. TRMT is a read-only bit which is set
when the TSR register is empty. No interrupt logic istied to this bit so the user has to poll this bit in order todetermine if the TSR register is empty.

The
TXCKP
(BAUDCON<4>)
and
RXDTP
(BAUDCON<5>) bits allow the TX and RX signals to be
inverted (polarity reversed). Devices that buffer signals
between TTL and RS-232 levels also invert the signal.
Setting the TXCKP and RXDTP bits allows for the use of
circuits that provide buffering without inverting the signal.

The TXCKP bit (BAUDCON<4>) allows the TX signal to
be inverted (polarity reversed). Devices that buffer
signals from TTL to RS-232 levels also invert the signal(when TTL = 1, RS-232 = negative). Inverting the polarity of the TX pin data by setting the TXCKP bit allows foruse of circuits that provide buffering without inverting thesignal.

When operating in Asynchronous mode, the EUSART
module consists of the following important elements:

Note 1: The TSR register is not mapped in data
memory so it is not available to the user.
2: Flag bit TXIF is set when enable bit TXEN
is set.

• Baud Rate Generator• Sampling Circuit• Asynchronous Transmitter• Asynchronous Receiver• Auto-Wake-up on Break signal• 12-Bit Break Character Transmit• Auto-Baud Rate Detection• Pin State Polarity

20.2.1

To set up an Asynchronous Transmission:
1.

2.
3.

EUSART ASYNCHRONOUS
TRANSMITTERThe EUSART transmitter block diagram is shown in
Figure 20-3. The heart of the transmitter is the Transmit(Serial) Shift Register (TSR). The Shift register obtains
its data from the Read/Write Transmit Buffer register,
TXREG. The TXREG register is loaded with data insoftware. The TSR register is not loaded until the Stop
bit has been transmitted from the previous load. As
soon as the Stop bit is transmitted, the TSR is loadedwith new data from the TXREG register (if available).

4.
5.
6.
7.
8.
9.

© 2007 Microchip Technology Inc.

Preliminary

Initialize the SPBRGH:SPBRG registers for theappropriate baud rate. Set or clear the BRGH
and BRG16 bits, as required, to achieve thedesired baud rate.
Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
If the signal from the TX pin is to be inverted, set
the TXCKP bit.
If interrupts are desired, set enable bit TXIE.
If 9-bit transmission is desired, set transmit bit
TX9. Can be used as address/data bit.
Enable the transmission by setting bit TXEN
which will also set bit TXIF.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Load data to the TXREG register (starts
transmission).
If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) areset.

DS39632D-page 247

PIC18F2455/2550/4455/4550
FIGURE 20-3:

EUSART TRANSMIT BLOCK DIAGRAM
Data BusTXIF

TXREG Register

TXIE

TXCKP

8
MSb

LSb
• • •

(8)

Pin Buffer
and Control

0

TSR Register

TX pinInterrupt
TXEN

Baud Rate CLK
TRMT

BRG16

SPBRGHSPBRG

TX9Baud Rate Generator

FIGURE 20-4:

SPEN

TX9D

ASYNCHRONOUS TRANSMISSION, TXCKP = 0 (TX NOT INVERTED)

Write to TXREGBRG Output(Shift Clock)

Word 1TX (pin)Start bit

FIGURE 20-5:

bit 1

bit 7/8

Stop bitWord 1

TXIF bit(Transmit BufferReg. Empty Flag)

TRMT bit(Transmit ShiftReg. Empty Flag)

bit 0

1 TCY

Word 1
Transmit Shift Reg

ASYNCHRONOUS TRANSMISSION (BACK TO BACK),TXCKP = 0 (TX NOT INVERTED)

Write to TXREG
Word 1

Word 2BRG Output(Shift Clock)
TX (pin)

TXIF bit(Interrupt Reg. Flag)

Start bit

bit 0

1 TCY

bit 1
Word 1

bit 7/8

Stop bit

Start bit

bit 0

Word 2

1 TCY
TRMT bit(Transmit ShiftReg. Empty Flag)

Word 1
Transmit Shift Reg.

Word 2
Transmit Shift Reg.

Note: This timing diagram shows two consecutive transmissions.

DS39632D-page 248

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
TABLE 20-5:
Name

REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset
Valueson page

INTCON

GIE/GIEH PEIE/GIEL

TMR0IEINT0IERBIE

TMR0IF

INT0IF

RBIF

51

PIR1

SPPIF(1)

ADIF

RCIF

TXIF

SSPIF

CCP1IF

TMR2IF

TMR1IF54

PIE1

SPPIE(1)

ADIE

RCIE

TXIE

SSPIE

CCP1IETMR2IETMR1IE

54

IPR1

(1)

SPPIP

ADIP

RCIP

TXIP

SSPIP

CCP1IP

TMR2IP

TMR1IP

54

RCSTA

SPEN

RX9

SREN

CREN

ADDEN

FERR

OERR

RX9D

53

TXREG

EUSART Transmit Register

53

TXSTA

CSRC

TX9

TXEN

SYNC

SENDB

BRGH

TRMT

TX9D

53

BAUDCONABDOVF

RCIDL

RXDTP

TXCKP

BRG16

—

WUE

ABDEN

53

SPBRGHEUSART Baud Rate Generator Register High Byte

53

SPBRG

EUSART Baud Rate Generator Register Low Byte

53

Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission.
Note 1: Reserved in 28-pin devices; always maintain these bits clear.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 249

PIC18F2455/2550/4455/4550
20.2.2EUSART ASYNCHRONOUS
RECEIVER

20.2.3

The receiver block diagram is shown in Figure 20-6.
The data is received on the RX pin and drives the data
recovery block. The data recovery block is actually ahigh-speed shifter operating at x16 times the baud rate,
whereas the main receive serial shifter operates at the
bit rate or at FOSC. This mode would typically be usedin RS-232 systems.
The RXDTP bit (BAUDCON<5>) allows the RX signal to
be inverted (polarity reversed). Devices that buffer
signals from RS-232 to TTL levels also perform an inversion of the signal (when RS-232 = positive, TTL = 0).
Inverting the polarity of the RX pin data by setting the
RXDTP bit allows for the use of circuits that provide
buffering without inverting the signal.
To set up an Asynchronous Reception:
1.

Initialize the SPBRGH:SPBRG registers for theappropriate baud rate. Set or clear the BRGH
and BRG16 bits, as required, to achieve thedesired baud rate.
2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
3. If the signal at the RX pin is to be inverted, set
the RXDTP bit.
4. If interrupts are desired, set enable bit RCIE.
5. If 9-bit reception is desired, set bit RX9.
6. Enable the reception by setting bit CREN.
7. Flag bit, RCIF, will be set when reception iscomplete and an interrupt will be generated if
enable bit, RCIE, was set.
8. Read the RCSTA register to get the 9th bit (ifenabled) and determine if any error occurred
during reception.
9. Read the 8-bit received data by reading the
RCREG register.
10. If any error occurred, clear the error by clearing
enable bit CREN.
11. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) areset.

DS39632D-page 250

SETTING UP 9-BIT MODE WITH
ADDRESS DETECTThis mode would typically be used in RS-485 systems.
To set up an Asynchronous Reception with Address
Detect Enable:
1.

Initialize the SPBRGH:SPBRG registers for theappropriate baud rate. Set or clear the BRGH
and BRG16 bits, as required, to achieve thedesired baud rate.
2. Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
3. If the signal at the RX pin is to be inverted, set
the RXDTP bit. If the signal from the TX pin is to
be inverted, set the TXCKP bit.
4. If interrupts are required, set the RCEN bit andselect the desired priority level with the RCIP bit.
5. Set the RX9 bit to enable 9-bit reception.
6. Set the ADDEN bit to enable address detect.
7. Enable reception by setting the CREN bit.
8. The RCIF bit will be set when reception iscomplete. The interrupt will be Acknowledged if
the RCIE and GIE bits are set.
9. Read the RCSTA register to determine if any
error occurred during reception, as well as readbit 9 of data (if applicable).
10. Read RCREG to determine if the device is being
addressed.
11. If any error occurred, clear the CREN bit.
12. If the device has been addressed, clear the
ADDEN bit to allow all received data into thereceive buffer and interrupt the CPU.

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
FIGURE 20-6:

EUSART RECEIVE BLOCK DIAGRAM
CREN

OERR

FERR

x64 Baud Rate CLK
BRG16

SPBRGH

÷ 64
or
÷ 16
or
÷4

SPBRG

Baud Rate Generator

RSR Register

MSb
Stop

(8)

• • •

7

1

LSb
Start

0

RX9
Pin Buffer
and Control

Data
RecoveryRX

RX9D

RCREG Register
FIFO

SPEN

RXDTP

8
Interrupt

Data Bus

RCIF
RCIE

FIGURE 20-7:

ASYNCHRONOUS RECEPTION, RXDTP = 0 (RX NOT INVERTED)
Start
bit

RX (pin)

bit 0

bit 7/8 Stop
bit

bit 1

Start
bit

bit 0

Rcv Shift Reg
Rcv Buffer Reg

Stop
bit

Start
bit

bit 7/8

Stop
bit

Word 2
RCREG

Word 1
RCREG

Read Rcv
Buffer Reg
RCREG

bit 7/8

RCIF(Interrupt Flag)OERR bit
CREN
Note:

This timing diagram shows three words appearing on the RX input. The RCREG (Receive Buffer) is read after the third wordcausing the OERR (Overrun) bit to be set.

TABLE 20-6:
Name

REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset
Valueson page

INTCON

GIE/GIEH PEIE/GIEL

TMR0IEINT0IERBIE

TMR0IF

INT0IF

RBIF

51

PIR1

SPPIF(1)

ADIF

RCIF

TXIF

SSPIF

CCP1IF

TMR2IF

TMR1IF54

PIE1

SPPIE(1)

ADIE

RCIE

TXIE

SSPIE

CCP1IETMR2IETMR1IE54

IPR1

SPPIP(1)

ADIP

RCIP

TXIP

SSPIP

CCP1IP

TMR2IP

TMR1IP

54

SPEN

RX9

SREN

CREN

ADDEN

FERR

OERR

RX9D

RCSTA
RCREG

EUSART Receive Register

53
53

TXSTA

CSRC

TX9

TXEN

SYNC

SENDB

BRGH

TRMT

TX9D

53

BAUDCONABDOVF

RCIDL

RXDTP

TXCKP

BRG16

—

WUE

ABDEN

53

SPBRGHEUSART Baud Rate Generator Register High Byte

53

SPBRG

EUSART Baud Rate Generator Register Low Byte

53

Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
Note 1: Reserved in 28-pin devices; always maintain these bits clear.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 251

PIC18F2455/2550/4455/4550
20.2.4

AUTO-WAKE-UP ON SYNC
BREAK CHARACTER

Character and cause data or framing errors. To work
properly, therefore, the initial character in the transmission must be all ‘0’s. This can be 00h (8 bytes) for
standard RS-232 devices or 000h (12 bits) for LIN bus.

During Sleep mode, all clocks to the EUSART aresuspended. Because of this, the Baud Rate Generator
is inactive and a proper byte reception cannot be performed. The auto-wake-up feature allows the controller
to wake-up due to activity on the RX/DT line while the
EUSART is operating in Asynchronous mode.

Oscillator start-up time must also be considered,especially in applications using oscillators with longer
start-up intervals (i.e., XT or HS mode). The Sync
Break (or Wake-up Signal) character must be of
sufficient length and be followed by a sufficient interval
to allow enough time for the selected oscillator to startand provide proper initialization of the EUSART.

The auto-wake-up feature is enabled by setting the
WUE bit (BAUDCON<1>). Once set, the typical receive
sequence on RX/DT is disabled and the EUSART
remains in an Idle state, monitoring for a wake-up event
independent of the CPU mode. A wake-up event
consists of a high-to-low transition on the RX/DT line.
(This coincides with the start of a Sync Break or a
Wake-up Signal character for the LIN protocol.)20.2.4.2

The timing of WUE and RCIF events may cause some
confusion when it comes to determining the validity ofreceived data. As noted, setting the WUE bit places the
EUSART in an Idle mode. The wake-up event causes a
receive interrupt by setting the RCIF bit. The WUE bit iscleared after this when a rising edge is seen on RX/DT.
The interrupt condition is then cleared by reading the
RCREG register. Ordinarily, the data in RCREG will bedummy data and should be discarded.

Following a wake-up event, the module generates an
RCIF interrupt. The interrupt is generated synchronously to the Q clocks in normal operating modes(Figure 20-8) and asynchronously, if the device is in
Sleep mode (Figure 20-9). The interrupt condition iscleared by reading the RCREG register.
The WUE bit is automatically cleared once a low-tohigh transition is observed on the RX line following thewake-up event. At this point, the EUSART module is in
Idle mode and returns to normal operation. This signals
to the user that the Sync Break event is over.

20.2.4.1

The fact that the WUE bit has been cleared (or is stillset) and the RCIF flag is set should not be used as anindicator of the integrity of the data in RCREG. Users
should consider implementing a parallel method in
firmware to verify received data integrity.
To assure that no actual data is lost, check the RCIDL
bit to verify that a receive operation is not in process. If
a receive operation is not occurring, the WUE bit may
then be set just prior to entering the Sleep mode.

Special Considerations Using
Auto-Wake-up

Since auto-wake-up functions by sensing rising edgetransitions on RX/DT, information with any statechanges before the Stop bit may signal a false End-of-

FIGURE 20-8:

Special Considerations Using
the WUE Bit

AUTO-WAKE-UP BIT (WUE) TIMINGS DURING NORMAL OPERATIONQ1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4OSC1
Bit set by user

Auto-Cleared

WUE bit(1)RX/DT Line
RCIF
Note 1:

Cleared due to user read of RCREG

The EUSART remains in Idle while the WUE bit is set.

FIGURE 20-9:

AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEPQ1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Q1

Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4OSC1
Bit set by user

Auto-Cleared

WUE bit(2)RX/DT Line

Note 1

RCIF
Sleep Ends

Sleep Command Executed
Note 1:
2:

Cleared due to user read of RCREG

If the wake-up event requires long oscillator warm-up time, the auto-clear of the WUE bit can occur before the oscillator is ready. Thissequence should not depend on the presence of Q clocks.
The EUSART remains in Idle while the WUE bit is set.

DS39632D-page 252

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
20.2.5

BREAK CHARACTER SEQUENCE

The EUSART module has the capability of sending thespecial Break character sequences that are required by
the LIN bus standard. The Break character transmit
consists of a Start bit, followed by twelve ‘0’ bits and a
Stop bit. The Frame Break character is sent whenever
the SENDB and TXEN bits (TXSTA<3> and
TXSTA<5>) are set while the Transmit Shift register isloaded with data. Note that the value of data written to
TXREG will be ignored and all ‘0’s will be transmitted.
The SENDB bit is automatically reset by hardware after
the corresponding Stop bit is sent. This allows the user
to preload the transmit FIFO with the next transmit byte
following the Break character (typically, the Sync
character in the LIN specification).
Note that the data value written to the TXREG for the
Break character is ignored. The write simply serves the
purpose of initiating the proper sequence.
The TRMT bit indicates when the transmit operation is
active or Idle, just as it does during normal transmission. See Figure 20-10 for the timing of the Breakcharacter sequence.

20.2.5.1

Break and Sync Transmit Sequence

The following sequence will send a message frame
header made up of a Break, followed by an Auto-Baud
Sync byte. This sequence is typical of a LIN bus
master.

FIGURE 20-10:
Write to TXREG

1.
2.
3.
4.
5.

Configure the EUSART for the desired mode.
Set the TXEN and SENDB bits to set up the
Break character.
Load the TXREG with a dummy character toinitiate transmission (the value is ignored).
Write ‘55h’ to TXREG to load the Sync character
into the transmit FIFO buffer.
After the Break has been sent, the SENDB bit isreset by hardware. The Sync character now
transmits in the preconfigured mode.

When the TXREG becomes empty, as indicated by the
TXIF, the next data byte can be written to TXREG.

20.2.6

RECEIVING A BREAK CHARACTERThe Enhanced USART module can receive a Breakcharacter in two ways.
The first method forces configuration of the baud rate
at a frequency of 9/13 the typical speed. This allows for
the Stop bit transition to be at the correct sampling
location (13 bits for Break versus Start bit and 8 databits for typical data).
The second method uses the auto-wake-up featuredescribed in Section 20.2.4 “Auto-Wake-up on Sync
Break Character”. By enabling this feature, the
EUSART will sample the next two transitions on RX/DT,
cause an RCIF interrupt and receive the next data byte
followed by another interrupt.
Note that following a Break character, the user will
typically want to enable the Auto-Baud Rate Detectfeature. For both methods, the user can set the ABD bit
once the TXIF interrupt is observed.

SEND BREAK CHARACTER SEQUENCE
Dummy Write

BRG Output(Shift Clock)
TX (pin)Start bit

bit 0

bit 1

bit 11

Stop bitBreak
TXIF bit(Transmit BufferReg. Empty Flag)
TRMT bit(Transmit ShiftReg. Empty Flag)SENDB sampled here

Auto-Cleared

SENDB(Transmit ShiftReg. Empty Flag)© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 253

PIC18F2455/2550/4455/4550
20.3

EUSART Synchronous
Master Mode

Once the TXREG register transfers the data to the TSR
register (occurs in one TCY), the TXREG is empty and
the TXIF flag bit (PIR1<4>) is set. The interrupt can be
enabled or disabled by setting or clearing the interrupt
enable bit, TXIE (PIE1<4>). TXIF is set regardless ofthe state of enable bit TXIE; it cannot be cleared insoftware. It will reset only when new data is loaded into
the TXREG register.

The Synchronous Master mode is entered by setting
the CSRC bit (TXSTA<7>). In this mode, the data istransmitted in a half-duplex manner (i.e., transmission
and reception do not occur at the same time). Whentransmitting data, the reception is inhibited and viceversa. Synchronous mode is entered by setting bit,
SYNC (TXSTA<4>). In addition, enable bit, SPEN(RCSTA<7>), is set in order to configure the TX and RX
pins to CK (clock) and DT (data) lines, respectively.

While flag bit, TXIF, indicates the status of the TXREG
register, another bit, TRMT (TXSTA<1>), shows thestatus of the TSR register. TRMT is a read-only bit which
is set when the TSR is empty. No interrupt logic is tied tothis bit so the user has to poll this bit in order to determine if the TSR register is empty. The TSR is not
mapped in data memory so it is not available to the user.

The Master mode indicates that the processor
transmits the master clock on the CK line.
Clock polarity (CK) is selected with the TXCKP bit(BAUDCON<4>). Setting TXCKP sets the Idle state on
CK as high, while clearing the bit sets the Idle state as
low. Data polarity (DT) is selected with the RXDTP bit(BAUDCON<5>). Setting RXDTP sets the Idle state on
DT as high, while clearing the bit sets the Idle state as
low. DT is sampled when CK returns to its idle state.
This option is provided to support Microwire devices
with this module.

20.3.1

To set up a Synchronous Master Transmission:
1.

2.
3.

EUSART SYNCHRONOUS MASTER
TRANSMISSION

4.
5.
6.
7.

The EUSART transmitter block diagram is shown in
Figure 20-3. The heart of the transmitter is the Transmit(Serial) Shift Register (TSR). The Shift register obtains
its data from the Read/Write Transmit Buffer register,
TXREG. The TXREG register is loaded with data insoftware. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loadedwith new data from the TXREG (if available).

FIGURE 20-11:

Initialize the SPBRGH:SPBRG registers for theappropriate baud rate. Set or clear the BRG16bit, as required, to achieve the desired baud rate.
Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
If the signal from the CK pin is to be inverted, set
the TXCKP bit. If the signal from the DT pin is to
be inverted, set the RXDTP bit.
If interrupts are desired, set enable bit TXIE.
If 9-bit transmission is desired, set bit TX9.
Enable the transmission by setting bit TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Start transmission by loading data to the TXREG
register.
If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.

8.
9.

SYNCHRONOUS TRANSMISSION

Q1 Q2 Q3Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4

RC7/RX/DT/
SDO pin

bit 0

bit 1

bit 2

Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

bit 7

bit 0

bit 1

bit 7

Word 2

Word 1
RC6/TX/CK pin(TXCKP = 0)
RC6/TX/CK pin(TXCKP = 1)
Write toTXREG Reg

Write Word 1

Write Word 2

TXIF bit(Interrupt Flag)
TRMT bit
TXEN bit ‘1’
Note:

‘1’

Sync Master mode, SPBRG = 0, continuous transmission of two 8-bit words.

DS39632D-page 254

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
FIGURE 20-12:

SYNCHRONOUS TRANSMISSION (THROUGH TXEN)

RC7/RX/DT/SDO pin

bit 0

bit 1

bit 2

bit 6

bit 7

RC6/TX/CK pin
Write toTXREG reg

TXIF bit

TRMT bit

TXEN bit

TABLE 20-7:
Name

REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset
Valueson page

INT0IERBIE

TMR0IF

INT0IF

RBIF

51

INTCON

GIE/GIEH PEIE/GIEL TMR0IE

PIR1SPPIF(1)

ADIF

RCIF

TXIF

SSPIF

CCP1IF

TMR2IF

TMR1IF54

PIE1

SPPIE(1)

ADIE

RCIE

TXIE

SSPIE

CCP1IETMR2IETMR1IE54

IPR1

SPPIP(1)

ADIP

RCIP

TXIP

SSPIP

CCP1IP

TMR2IP

TMR1IP

54

RCSTA

SPEN

RX9

SREN

CREN

ADDEN

FERR

OERR

RX9D

53

TXREG

EUSART Transmit Register

53

CSRC

TX9

TXEN

SYNC

SENDB

BRGH

TRMT

TX9D

53

BAUDCONABDOVF

RCIDL

RXDTP

TXCKP

BRG16

—

WUE

ABDEN

53

SPBRGHEUSART Baud Rate Generator Register High Byte

53

SPBRG

EUSART Baud Rate Generator Register Low Byte

53

TXSTA

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.
Note 1: Reserved in 28-pin devices; always maintain these bits clear.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 255

PIC18F2455/2550/4455/4550
20.3.2EUSART SYNCHRONOUS
MASTER RECEPTION

4.

If the signal from the CK pin is to be inverted, set
the TXCKP bit. If the signal from the DT pin is to
be inverted, set the RXDTP bit.
5. If interrupts are desired, set enable bit RCIE.
6. If 9-bit reception is desired, set bit RX9.
7. If a single reception is required, set bit SREN.
For continuous reception, set bit CREN.
8. Interrupt flag bit, RCIF, will be set when reception
is complete and an interrupt will be generated if
the enable bit, RCIE, was set.
9. Read the RCSTA register to get the 9th bit (ifenabled) and determine if any error occurred
during reception.
10. Read the 8-bit received data by reading the
RCREG register.
11. If any error occurred, clear the error by clearing
bit CREN.
12. If using interrupts, ensure that the GIE and PEIE bitsin the INTCON register (INTCON<7:6>) are set.

Once Synchronous mode is selected, reception isenabled by setting either the Single Receive Enable bit,
SREN (RCSTA<5>), or the Continuous Receive
Enable bit, CREN (RCSTA<4>). Data is sampled on theRX pin on the falling edge of the clock.
If enable bit SREN is set, only a single word is received.
If enable bit CREN is set, the reception is continuous
until CREN is cleared. If both bits are set, then CREN
takes precedence.
To set up a Synchronous Master Reception:
1.

2.
3.

Initialize the SPBRGH:SPBRG registers for theappropriate baud rate. Set or clear the BRG16bit, as required, to achieve the desired baud rate.
Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
Ensure bits CREN and SREN are clear.

FIGURE 20-13:

SYNCHRONOUS RECEPTION (MASTER MODE, SREN)

Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

RC7/RX/DT/SDO
pin

bit 0

bit 1

bit 2

bit 3

bit 4

bit 5

bit 6

bit 7

RC6/TX/CK pin(TXCKP = 0)
RC6/TX/CK pin(TXCKP = 1)
Write tobit SREN
SREN bit
CREN bit ‘0’‘0’

RCIF bit(Interrupt)
Read
RXREG
Note:

Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.

TABLE 20-8:
Name

REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset Values
on page

INTCON

GIE/GIEH PEIE/GIEL TMR0IE

INT0IERBIE

TMR0IF

INT0IF

RBIF

51

PIR1

SPPIF(1)

ADIF

RCIF

TXIF

SSPIF

CCP1IF

TMR2IF

TMR1IF54

PIE1

SPPIE(1)

ADIE

RCIE

TXIE

SSPIE

CCP1IETMR2IETMR1IE54

IPR1

SPPIP(1)

ADIP

RCIP

TXIP

SSPIP

CCP1IP

TMR2IP

TMR1IP

54

SPEN

RX9

SREN

CREN

ADDEN

FERR

OERR

RX9D

RCSTA
RCREG

EUSART Receive Register

53
53

CSRC

TX9

TXEN

SYNC

SENDB

BRGH

TRMT

TX9D

53

BAUDCON ABDOVF

RCIDL

RXDTP

TXCKP

BRG16

—

WUE

ABDEN

53

TXSTA
SPBRGHEUSART Baud Rate Generator Register High Byte

53

SPBRG

EUSART Baud Rate Generator Register Low Byte

53

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
Note 1: Reserved in 28-pin devices; always maintain these bits clear.

DS39632D-page 256

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
20.4

EUSART Synchronous
Slave Mode

To set up a Synchronous Slave Transmission:
1.

Synchronous Slave mode is entered by clearing bit,
CSRC (TXSTA<7>). This mode differs from theSynchronous Master mode in that the shift clock is supplied externally at the CK pin (instead of being suppliedinternally in Master mode). This allows the device totransfer or receive data while in any power-managed
mode.

2.
3.
4.

20.4.1

5.
6.

EUSART SYNCHRONOUS
SLAVE TRANSMISSION

The operation of the Synchronous Master and Slavemodes are identical, except in the case of the Sleepmode.
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
a)
b)
c)
d)

e)

7.
8.
9.

The first word will immediately transfer to the
TSR register and transmit.
The second word will remain in the TXREG
register.
Flag bit, TXIF, will not be set.
When the first word has been shifted out of TSR,
the TXREG register will transfer the second word
to the TSR and flag bit, TXIF, will now be set.
If enable bit TXIE is set, the interrupt will wake thechip from Sleep. If the global interrupt is enabled,
the program will branch to the interrupt vector.

TABLE 20-9:
Name
INTCON

Enable the synchronous slave serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
Clear bits CREN and SREN.
If interrupts are desired, set enable bit TXIE.
If the signal from the CK pin is to be inverted, set
the TXCKP bit. If the signal from the DT pin is to
be inverted, set the RXDTP bit.
If 9-bit transmission is desired, set bit TX9.
Enable the transmission by setting enable bit
TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Start transmission by loading data to the
TXREGx register.
If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.

REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Bit 7

Bit 6

Bit 5

GIE/GIEH PEIE/GIEL TMR0IE

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset
Valueson page

INT0IERBIE

TMR0IF

INT0IF

RBIF

51

PIR1

SPPIF

(1)

ADIF

RCIF

TXIF

SSPIF

CCP1IF

TMR2IF

TMR1IF54

PIE1

SPPIE(1)

ADIE

RCIE

TXIE

SSPIE

CCP1IETMR2IETMR1IE54

IPR1

SPPIP(1)

ADIP

RCIP

TXIP

SSPIP

CCP1IP

TMR2IP

TMR1IP

54

RCSTA

SPEN

RX9

SREN

CREN

ADDEN

FERR

OERR

RX9D

53

TXREG
TXSTA

EUSART Transmit Register

53

CSRC

TX9

TXEN

SYNC

SENDB

BRGH

TRMT

TX9D

53

RCIDL

RXDTP

TXCKP

BRG16

—

WUE

ABDEN

53

BAUDCONABDOVFSPBRGHEUSART Baud Rate Generator Register High Byte

53

SPBRG

EUSART Baud Rate Generator Register Low Byte

53

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.
Note 1: Reserved in 28-pin devices; always maintain these bits clear.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 257

PIC18F2455/2550/4455/4550
20.4.2EUSART SYNCHRONOUS SLAVERECEPTION

To set up a Synchronous Slave Reception:
1.

The operation of the Synchronous Master and Slavemodes is identical, except in the case of Sleep, or any
Idle mode and bit SREN, which is a “don’t care” in
Slave mode.
If receive is enabled by setting the CREN bit prior toentering Sleep or any Idle mode, then a word may bereceived while in this low-power mode. Once the word
is received, the RSR register will transfer the data to the
RCREG register. If the RCIE enable bit is set, theinterrupt generated will wake the chip from the lowpower mode. If the global interrupt is enabled, theprogram will branch to the interrupt vector.

Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
2. If interrupts are desired, set enable bit RCIE.
3. If the signal from the CK pin is to be inverted, set
the TXCKP bit. If the signal from the DT pin is to
be inverted, set the RXDTP bit.
4. If 9-bit reception is desired, set bit RX9.
5. To enable reception, set enable bit CREN.
6. Flag bit, RCIF, will be set when reception iscomplete. An interrupt will be generated if
enable bit, RCIE, was set.
7. Read the RCSTA register to get the 9th bit (ifenabled) and determine if any error occurred
during reception.
8. Read the 8-bit received data by reading the
RCREG register.
9. If any error occurred, clear the error by clearing
bit CREN.
10. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.

TABLE 20-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset
Valueson page

INTCON

GIE/GIEH PEIE/GIEL TMR0IE

INT0IERBIE

TMR0IF

INT0IF

RBIF

51

PIR1

SPPIF(1)

ADIF

RCIF

TXIF

SSPIF

CCP1IF

TMR2IF

TMR1IF54

PIE1

SPPIE(1)

ADIE

RCIE

TXIE

SSPIE

CCP1IETMR2IETMR1IE54

IPR1

SPPIP(1)

ADIP

RCIP

TXIP

SSPIP

CCP1IP

TMR2IP

TMR1IP

54

SPEN

RX9

SREN

CREN

ADDEN

FERR

OERR

RX9D

53

RCSTA
RCREG

EUSART Receive Register

53

TXSTA

CSRC

TX9

TXEN

SYNC

SENDB

BRGH

TRMT

TX9D

53

BAUDCONABDOVF

RCIDL

RXDTP

TXCKP

BRG16

—

WUE

ABDEN

53

SPBRGHEUSART Baud Rate Generator Register High Byte

53

SPBRG

EUSART Baud Rate Generator Register Low Byte

53

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.
Note 1: Reserved in 28-pin devices; always maintain these bits clear.

DS39632D-page 258

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
21.0

10-BIT ANALOG-TO-DIGITALCONVERTER (A/D) MODULE

The Analog-to-Digital (A/D) converter module has
10 inputs for the 28-pin devices and 13 for the
40/44-pin devices. This module allows conversion of ananalog input signal to a corresponding 10-bit digital
number.

The ADCON0 register, shown in Register 21-1,
controls the operation of the A/D module. The
ADCON1 register, shown in Register 21-2, configures
the functions of the port pins. The ADCON2 register,
shown in Register 21-3, configures the A/D clock
source, programmed acquisition time and justification.

The module has five registers:• A/D Result High Register (ADRESH)• A/D Result Low Register (ADRESL)• A/D Control Register 0 (ADCON0)• A/D Control Register 1 (ADCON1)• A/D Control Register 2 (ADCON2)

REGISTER 21-1:

ADCON0: A/D CONTROL REGISTER 0

U-0

U-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

—

—

CHS3

CHS2

CHS1

CHS0

GO/DONE

ADON

bit 7

bit 0

Legend:R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’-n = Value at POR‘1’ = Bit is set‘0’ = Bit is cleared

bit 7-6

Unimplemented: Read as ‘0’

bit 5-2

CHS3:CHS0: Analog Channel Select bits
0000 = Channel 0 (AN0)0001 = Channel 1 (AN1)0010 = Channel 2 (AN2)0011 = Channel 3 (AN3)0100 = Channel 4 (AN4)0101 = Channel 5 (AN5)(1,2)
0110 = Channel 6 (AN6)(1,2)
0111 = Channel 7 (AN7)(1,2)
1000 = Channel 8 (AN8)1001 = Channel 9 (AN9)1010 = Channel 10 (AN10)1011 = Channel 11 (AN11)
1100 = Channel 12 (AN12)1101 = Unimplemented(2)1110 = Unimplemented(2)1111 = Unimplemented(2)

bit 1

GO/DONE: A/D Conversion Status bit
When ADON = 1:
1 = A/D conversion in progress
0 = A/D Idle

bit 0

ADON: A/D On bit
1 = A/D converter module is enabled
0 = A/D converter module is disabled

Note 1:2:

x = Bit is unknown

These channels are not implemented on 28-pin devices.
Performing a conversion on unimplemented channels will return a floating input measurement.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 259

PIC18F2455/2550/4455/4550
REGISTER 21-2:

ADCON1: A/D CONTROL REGISTER 1

U-0

U-0

R/W-0

R/W-0

R/W-0(1)

R/W(1)

R/W(1)

R/W(1)

—

—

VCFG0

VCFG0

PCFG3

PCFG2

PCFG1

PCFG0

bit 7

bit 0

Legend:R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’-n = Value at POR‘1’ = Bit is set‘0’ = Bit is cleared

PCFG3:
PCFG0

AN6(2)

AN5(2)

AN4

AN3

AN2

AN1

AN0

PCFG3:PCFG0: A/D Port Configuration Control bits:
AN7(2)

bit 3-0

AN8

VCFG0: Voltage Reference Configuration bit (VREF+ source)
1 = VREF+ (AN3)0 = VDD

AN9

bit 4

AN10

VCFG0: Voltage Reference Configuration bit (VREF- source)
1 = VREF- (AN2)0 = VSS

AN11

Unimplemented: Read as ‘0’

bit 5

AN12

bit 7-60000(1)
0001
0010
0011
0100
0101
0110

A

A

A

A

A

A

A

A

A

A

A

A

A

A
A
D
D
D
D
D

A
A
A
D
D
D
D

A
A
A
A
D
D
D

A
A
A
A
A
D
D

A
A
A
A
A
A
D

A
A
A
A
A
A
A

A
A
A
A
A
A
A

A
A
A
A
A
A
A

A
A
A
A
A
A
A

A
A
A
A
A
A
A

A
A
A
A
A
A
A

A
A
A
A
A
A
A

A
A
A
A
A
A
A

D
D
D
D
D
D
D
D

D
D
D
D
D
D
D
D

D
D
D
D
D
D
D
D

D
D
D
D
D
D
D
D

D
D
D
D
D
D
D
D

D
D
D
D
D
D
D
D

A
D
D
D
D
D
D
D

A
A
D
D
D
D
D
D

A
A
A
D
D
D
D
D

A
A
A
A
D
D
D
D

A
A
A
A
A
D
D
D

A
A
A
A
A
A
D
D

A
A
A
A
A
A
A
D

0111(1)
1000
1001
1010
1011
1100
1101
1110
1111

A = Analog input

Note 1:2:

x = Bit is unknown

D = Digital I/O

The POR value of the PCFG bits depends on the value of the PBADEN Configuration bit. When
PBADEN = 1, PCFG<3:0> = 0000; when PBADEN = 0, PCFG<3:0> = 0111.
AN5 through AN7 are available only on 40/44-pin devices.

DS39632D-page 260

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
REGISTER 21-3:

ADCON2: A/D CONTROL REGISTER 2

R/W-0

U-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

ADFM

—

ACQT2

ACQT1

ACQT0

ADCS2

ADCS1

ADCS0

bit 7

bit 0

Legend:R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’-n = Value at POR‘1’ = Bit is set‘0’ = Bit is cleared

bit 7

ADFM: A/D Result Format Select bit
1 = Right justified
0 = Left justified

bit 6

Unimplemented: Read as ‘0’

bit 5-3

ACQT2:ACQT0: A/D Acquisition Time Select bits
111 = 20 TAD
110 = 16 TAD
101 = 12 TAD
100 = 8 TAD
011 = 6 TAD
010 = 4 TAD
001 = 2 TAD
000 = 0 TAD(1)bit 2-0

ADCS2:ADCS0: A/D Conversion Clock Select bits
111 = FRC (clock derived from A/D RC oscillator)(1)110 = FOSC/64
101 = FOSC/16
100 = FOSC/4
011 = FRC (clock derived from A/D RC oscillator)(1)010 = FOSC/32
001 = FOSC/8000 = FOSC/2

Note 1:x = Bit is unknown

If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is added before the A/Dclock starts. This allows the SLEEP instruction to be executed before starting a conversion.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 261

PIC18F2455/2550/4455/4550
The analog reference voltage is software selectable toeither the device’s positive and negative supply voltage(VDD and VSS) or the voltage level on theRA3/AN3/VREF+ and RA2/AN2/VREF-/CVREF pins.

A device Reset forces all registers to their Reset state.
This forces the A/D module to be turned off and any
conversion in progress is aborted.
Each port pin associated with the A/D converter can be
configured as an analog input or as a digital I/O. The
ADRESH and ADRESL registers contain the result of
the A/D conversion. When the A/D conversion is complete, the result is loaded into the ADRESH:ADRESL
register pair, the GO/DONE bit (ADCON0 register) is
cleared and A/D Interrupt Flag bit, ADIF, is set. The
block diagram of the A/D module is shown in
Figure 21-1.

The A/D converter has a unique feature of being able
to operate while the device is in Sleep mode. To
operate in Sleep, the A/D conversion clock must bederived from the A/D’s internal RC oscillator.
The output of the sample and hold is the input into theconverter, which generates the result via successive
approximation.

FIGURE 21-1:

A/D BLOCK DIAGRAM

CHS3:CHS0
1100
1011
1010
1001
1000

Reference
Voltage

VREF+

X0
X1
1X

VREF-

0X

AN8

AN6(1)0101

AN5(1)

0010
0001

VDD(2)

AN9

0110

0011

VCFG1:VCFG0

AN10

AN7(1)

0100(Input Voltage)

AN11

0111

VAIN
10-BitConverter
A/D

AN12

0000

AN4
AN3
AN2
AN1
AN0

VSS(2)

Note 1:
2:

Channels AN5 through AN7 are not available on 28-pin devices.
I/O pins have diode protection to VDD and VSS.

DS39632D-page 262

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
Wait for A/D conversion to complete, by either:• Polling for the GO/DONE bit to be clearedOR• Waiting for the A/D interrupt
Read A/D Result registers (ADRESH:ADRESL);
clear bit ADIF, if required.
For next conversion, go to step 1 or step 2, as
required. The A/D conversion time per bit isdefined as TAD. A minimum wait of 3 TAD isrequired before the next acquisition starts.

6.
7.

FIGURE 21-2:

The following steps should be followed to perform an
A/D conversion:

3FFh

1.

3FEh

FIGURE 21-3:

Digital Code Output

002h
001h

1023 LSB

1023.5 LSB

1022 LSB

1022.5 LSB

3 LSB

Analog Input Voltage

ANALOG INPUT MODEL
VDD

Sampling
SwitchVT = 0.6V
Rs

VAIN

2 LSB

000h
2.5 LSB

3.
4.

A/D TRANSFER FUNCTION

003h

0.5 LSB2.

Configure the A/D module:• Configure analog pins, voltage reference anddigital I/O (ADCON1)• Select A/D input channel (ADCON0)• Select A/D acquisition time (ADCON2)• Select A/D conversion clock (ADCON2)• Turn on A/D module (ADCON0)
Configure A/D interrupt (if desired):• Clear ADIF bit• Set ADIE bit• Set GIE bit
Wait the required acquisition time (if required).
Start conversion:• Set GO/DONE bit (ADCON0 register)

1 LSB

After the A/D module has been configured as desired,
the selected channel must be acquired before the conversion is started. The analog input channels musthave their corresponding TRIS bits selected as an
input. To determine acquisition time, see Section 21.1
“A/D Acquisition Requirements”. After this acquisition time has elapsed, the A/D conversion can bestarted. An acquisition time can be programmed tooccur between setting the GO/DONE bit and the actual
start of the conversion.

5.

1.5 LSB

The value in the ADRESH:ADRESL registers is not
modified for a Power-on Reset. The ADRESH:ADRESL
registers will contain unknown data after a Power-on
Reset.

ANx

RIC ≤ 1k

CPIN
5 pF

VT = 0.6V

SS

RSS

ILEAKAGE±100 nACHOLD = 25 pF

VSS

Legend: CPIN
= Input CapacitanceVT= Threshold Voltage
ILEAKAGE = Leakage Current at the pin due tovarious junctions= Interconnect ResistanceRIC= Sampling Switch
SS= Sample/hold Capacitance (from DAC)
CHOLD
RSS
= Sampling Switch Resistance© 2007 Microchip Technology Inc.

Preliminary

VDD

6V
5V
4V
3V
2V
1

2

3

4

Sampling Switch (kΩ)

DS39632D-page 263

PIC18F2455/2550/4455/4550
21.1

A/D Acquisition Requirements

For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 21-3. The
source impedance (RS) and the internal samplingswitch (RSS) impedance directly affect the timerequired to charge the capacitor CHOLD. The samplingswitch (RSS) impedance varies over the device voltage(VDD). The source impedance affects the offset voltage
at the analog input (due to pin leakage current). The
maximum recommended impedance for analog
sources is 2.5 kΩ. After the analog input channel isselected (changed), the channel must be sampled forat least the minimum acquisition time before starting a
conversion.
Note:

CHOLD
Rs
Conversion Error
VDD
Temperature

=
=
≤
=
=

25 pF
2.5 kΩ
1/2 LSb
5V → RSS = 2 kΩ85°C (system max.)

ACQUISITION TIME=

Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient=

TAMP + TC + TCOFF

EQUATION 21-2:
VHOLD
or
TC

Example 21-3 shows the calculation of the minimum
required acquisition time TACQ. This calculation isbased on the following application system
assumptions:

When the conversion is started, theholding capacitor is disconnected from the
input pin.

EQUATION 21-1:
TACQ

To calculate the minimum acquisition time,
Equation 21-1 may be used. This equation assumes
that 1/2 LSb error is used (1024 steps for the A/D). The
1/2 LSb error is the maximum error allowed for the A/D
to meet its specified resolution.

A/D MINIMUM CHARGING TIME=

(VREF – (VREF/2048)) • (1 – e(-TC/CHOLD(RIC + RSS + RS)))=-(CHOLD)(RIC + RSS + RS) ln(1/2048)

EQUATION 21-3:

CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME

TACQ

=

TAMP + TC + TCOFF

TAMP

=

0.2 μs

TCOFF=(Temp – 25°C)(0.02 μs/°C)(85°C – 25°C)(0.02 μs/°C)
1.2 μsTemperature coefficient is only required for temperatures > 25°C. Below 25°C, TCOFF = 0 ms.
TC=-(CHOLD)(RIC + RSS + RS) ln(1/2048) μs-(25 pF) (1 kΩ + 2 kΩ + 2.5 kΩ) ln(0.0004883) μs
1.05 μs

TACQ=

0.2 μs + 1.05 μs + 1.2 μs
2.45 μs

DS39632D-page 264

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
21.2

Selecting and Configuring
Acquisition Time

21.3

Selecting the A/D Conversion
Clock

The ADCON2 register allows the user to select anacquisition time that occurs each time the GO/DONE
bit is set. It also gives users the option to use an
automatically determined acquisition time.

The A/D conversion time per bit is defined as TAD. The
A/D conversion requires 11 TAD per 10-bit conversion.
The source of the A/D conversion clock is software
selectable. There are seven possible options for TAD:

Acquisition time may be set with the ACQT2:ACQT0
bits (ADCON2<5:3>) which provide a range of 2 to20 TAD. When the GO/DONE bit is set, the A/D module
continues to sample the input for the selected acquisition time, then automatically begins a conversion.
Since the acquisition time is programmed, there may
be no need to wait for an acquisition time between
selecting a channel and setting the GO/DONE bit.

• 2 TOSC• 4 TOSC• 8 TOSC• 16 TOSC• 32 TOSC• 64 TOSC• Internal RC Oscillator

Manualacquisitionisselected
when
ACQT2:ACQT0 = 000. When the GO/DONE bit is set,sampling is stopped and a conversion begins. The user
is responsible for ensuring the required acquisition time
has passed between selecting the desired input
channel and setting the GO/DONE bit. This option is
also the default Reset state of the ACQT2:ACQT0 bits
and is compatible with devices that do not offer
programmable acquisition times.

For correct A/D conversions, the A/D conversion clock(TAD) must be as short as possible but greater than theminimum TAD (see parameter 130 in Table 28-29 formore information).
Table 21-1 shows the resultant TAD times derived fromthe device operating frequencies and the A/D clock
source selected.

In either case, when the conversion is completed, theGO/DONE bit is cleared, the ADIF flag is set and theA/D begins sampling the currently selected channel
again. If an acquisition time is programmed, there isnothing to indicate if the acquisition time has ended orif the conversion has begun.

TABLE 21-1:

TAD vs. DEVICE OPERATING FREQUENCIESAD Clock Source (TAD)

Operation

ADCS2:ADCS0

PIC18FXXXXPIC18LFXXXX(4)2 TOSC000

2.86 MHz1.43 MHz

4 TOSC100

5.71 MHz

2.86 MHz

8 TOSC001

11.43 MHz5.72 MHz

16 TOSC

101

22.86 MHz11.43 MHz

32 TOSC010

45.71 MHz22.86 MHz64 TOSC110

48.0 MHz45.71 MHzx11

1.00 MHz(1)1.00 MHz(2)RC(3)
Note 1:
2:
3:
4:

Maximum Device Frequency

The RC source has a typical TAD time of 4 ms.
The RC source has a typical TAD time of 6 ms.
For device frequencies above 1 MHz, the device must be in Sleep for the entire conversion or the A/D
accuracy may be out of specification.
Low-power devices only.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 265

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21.4

Operation in Power-Managed
Modes

21.5

The selection of the automatic acquisition time and A/Dconversion clock is determined in part by the clock
source and frequency while in a power-managed
mode.
If the A/D is expected to operate while the device is ina power-managed mode, the ACQT2:ACQT0 and
ADCS2:ADCS0 bits in ADCON2 should be updated inaccordance with the clock source to be used in that
mode. After entering the mode, an A/D acquisition orconversion may be started. Once started, the device
should continue to be clocked by the same clock
source until the conversion has been completed.
If desired, the device may be placed into thecorresponding Idle mode during the conversion. If thedevice clock frequency is less than 1 MHz, the A/D RC
clock source should be selected.

The ADCON1, TRISA, TRISB and TRISE registers all
configure the A/D port pins. The port pins needed as
analog inputs must have their corresponding TRIS bits
set (input). If the TRIS bit is cleared (output), the digital
output level (VOH or VOL) will be converted.
The A/D operation is independent of the state of the
CHS3:CHS0 bits and the TRIS bits.
Note 1: When reading the PORT register, all pins
configured as analog input channels will
read as cleared (a low level). Pins configured as digital inputs will convert as
analog inputs. Analog levels on a digitallyconfigured input will be accurately
converted.

Operation in the Sleep mode requires the A/D FRC
clock to be selected. If bits ACQT2:ACQT0 are set to‘000’ and a conversion is started, the conversion will bedelayed one instruction cycle to allow execution of the
SLEEP instruction and entry to Sleep mode. The IDLEN
bit (OSCCON<7>) must have already been clearedprior to starting the conversion.

DS39632D-page 266

Configuring Analog Port Pins

Preliminary

2: Analog levels on any pin defined as adigital input may cause the digital input
buffer to consume current out of thedevice’s specification limits.
3: The PBADEN bit in Configuration
Register 3H configures PORTB pins toreset as analog or digital pins by controlling how the PCFG0 bits in ADCON1 arereset.

© 2007 Microchip Technology Inc.

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21.6

A/D Conversions

After the A/D conversion is completed or aborted, a
2 TAD wait is required before the next acquisition can bestarted. After this wait, acquisition on the selectedchannel is automatically started.

Figure 21-4 shows the operation of the A/D converter
after the GO/DONE bit has been set and the
ACQT2:ACQT0 bits are cleared. A conversion isstarted after the following instruction to allow entry into
Sleep mode before the conversion begins.

Note:

Figure 21-5 shows the operation of the A/D converter
after the GO/DONE bit has been set, theACQT2:ACQT0 bits are set to ‘010’ and selecting a
4 TAD acquisition time before the conversion starts.

21.7

Discharge

The discharge phase is used to initialize the value ofthe capacitor array. The array is discharged before
every sample. This feature helps to optimize theunity-gain amplifier as the circuit always needs tochargethecapacitor
array,
ratherthancharge/discharge based on previous measurement
values.

Clearing the GO/DONE bit during a conversion willabort the current conversion. The A/D Result registerpair will NOT be updated with the partially completed
A/D
conversion
sample.
This
means
the
ADRESH:ADRESL registers will continue to containthe value of the last completed conversion (or the lastvalue written to the ADRESH:ADRESL registers).

FIGURE 21-4:

The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.

A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0)

TCY - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 TAD1
b4
b1
b0
b6
b7
b2
b9
b8
b3
b5
Conversion starts

Discharge

Holding capacitor is disconnected from analog input (typically 100 ns)
Set GO/DONE bit
On the following cycle:
ADRESH:ADRESL is loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.

FIGURE 21-5:

A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD)TAD Cycles

TACQ Cycles
1

2

3

Automatic
Acquisition
Time

4

1

2

3

4

5

6

7

8

9

10

11

b9

b8

b7

b6

b5

b4

b3

b2

b1

b0

Conversion starts(Holding capacitor is disconnected)

Set GO/DONE bit(Holding capacitor continues
acquiring input)© 2007 Microchip Technology Inc.

TAD1

Discharge

On the following cycle:
ADRESH:ADRESL is loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.

Preliminary

DS39632D-page 267

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21.8

Use of the CCP2 Trigger

An A/D conversion can be started by the Special Event
Trigger of the CCP2 module. This requires that the
CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be programmed as ‘1011’ and that the A/D module is enabled(ADON bit is set). When the trigger occurs, theGO/DONE bit will be set, starting the A/D acquisitionand conversion and the Timer1 (or Timer3) counter will
be reset to zero. Timer1 (or Timer3) is reset to automatically repeat the A/D acquisition period with minimal
software overhead (moving ADRESH:ADRESL to the

TABLE 21-2:
Namedesired location). The appropriate analog input channel must be selected and the minimum acquisition
period is either timed by the user, or an appropriate
TACQ time selected before the Special Event Trigger
sets the GO/DONE bit (starts a conversion).
If the A/D module is not enabled (ADON is cleared), theSpecial Event Trigger will be ignored by the A/D
module but will still reset the Timer1 (or Timer3)
counter.

REGISTERS ASSOCIATED WITH A/D OPERATION
Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset
Valueson page

INTCON

GIE/GIEH PEIE/GIEL

TMR0IEINT0IERBIE

TMR0IF

INT0IF

RBIF

51

PIR1

SPPIF(4)

ADIF

RCIF

TXIF

SSPIF

CCP1IF

TMR2IF

TMR1IF54

PIE1

SPPIE(4)

ADIE

RCIE

TXIE

SSPIE

CCP1IETMR2IETMR1IE54

IPR1

SPPIP(4)

ADIP

RCIP

TXIP

SSPIP

CCP1IP

TMR2IP

TMR1IP54

PIR2

OSCFIF

CMIF

USBIF

EEIF

BCLIF

HLVDIF

TMR3IF

CCP2IF54

PIE2

OSCFIE

CMIE

USBIE

EEIE

BCLIE

HLVDIETMR3IECCP2IE54

IPR2

OSCFIP

CMIP

USBIP

EEIP

BCLIP

HLVDIP

TMR3IP

CCP2IP

54

ADRESHA/D Result Register High Byte

52

ADRESLA/D Result Register Low Byte

52

ADCON0

—

—

CHS3

CHS2

CHS1

CHS0

GO/DONEADON

52

ADCON1

—

—

VCFG1

VCFG0

PCFG3

PCFG2

PCFG1

PCFG0

52

ADCON2

ADFM

—

ACQT2

ACQT1

ACQT0

ADCS2

ADCS1

ADCS0

52

—

RA6(2)

RA5

RA4

RA3

RA2

RA1

RA0

54

TRISA

—

TRISA6(2)TRISA5TRISA4TRISA3

TRISA2TRISA1TRISA0

54

PORTB

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

54

TRISB

TRISB7TRISB6TRISB5TRISB4

TRISB3

TRISB2

TRISB1TRISB0

54

LATB

LATB7

LATB6

LATB5

LATB4

LATB3

LATB2

LATB1

LATB0

54

PORTE

RDPU(4)———

RE3(1,3)

RE2(4)

RE1(4)

RE0(4)

54

TRISE(4)

—

—

—

—

—

TRISE2

TRISE1

TRISE054

LATE(4)

—

—

—

—

—

LATE2

LATE1

LATE0

54

PORTA

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1: Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0).
2: RA6 and its associated latch and data direction bits are enabled as I/O pins based on oscillator
configuration; otherwise, they are read as ‘0’.
3: RE3 port bit is available only as an input pin when the MCLRE Configuration bit is ‘0’.
4: These registers and/or bits are not implemented on 28-pin devices.

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22.0

COMPARATOR MODULE

The analog comparator module contains two comparators that can be configured in a variety of ways. The
inputs can be selected from the analog inputs multiplexedwith pins RA0 through RA5, as well as the on-chip voltage reference (see Section 23.0 “Comparator Voltage
Reference Module”). The digital outputs (normal or
inverted) are available at the pin level and can also beread through the control register.

REGISTER 22-1:

The CMCON register (Register 22-1) selects thecomparator input and output configuration. Block
diagrams of the various comparator configurations areshown in Figure 22-1.

CMCON: COMPARATOR CONTROL REGISTER

R-0

R-0

R/W-0

R/W-0

R/W-0

R/W-1

R/W-1

R/W-1

C2OUT

C1OUT

C2INV

C1INV

CIS

CM2

CM1

CM0

bit 7

bit 0

Legend:R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’-n = Value at POR‘1’ = Bit is set‘0’ = Bit is clearedx = Bit is unknown

bit 7

C2OUT: Comparator 2 Output bit
When C2INV = 0:
1 = C2 VIN+ > C2 VIN0 = C2 VIN+ < C2 VINWhen C2INV = 1:
1 = C2 VIN+ < C2 VIN0 = C2 VIN+ > C2 VIN-

bit 6

C1OUT: Comparator 1 Output bit
When C1INV = 0:
1 = C1 VIN+ > C1 VIN0 = C1 VIN+ < C1 VINWhen C1INV = 1:
1 = C1 VIN+ < C1 VIN0 = C1 VIN+ > C1 VIN-

bit 5

C2INV: Comparator 2 Output Inversion bit
1 = C2 output inverted
0 = C2 output not inverted

bit 4

C1INV: Comparator 1 Output Inversion bit
1 = C1 output inverted
0 = C1 output not inverted

bit 3

CIS: Comparator Input Switch bit
When CM2:CM0 = 110:
1 = C1 VIN- connects to RA3/AN3/VREF+
C2 VIN- connects to RA2/AN2/VREF-/CVREF
0 = C1 VIN- connects to RA0/AN0
C2 VIN- connects to RA1/AN1

bit 2-0

CM2:CM0: Comparator Mode bits
Figure 22-1 shows the Comparator modes and the CM2:CM0 bit settings.

© 2007 Microchip Technology Inc.

Preliminary

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22.1

Comparator Configuration

There are eight modes of operation for the comparators, shown in Figure 22-1. Bits CM2:CM0 of the
CMCON register are used to select these modes. The
TRISA register controls the data direction of thecomparator pins for each mode. If the Comparator

FIGURE 22-1:

VIN-

RA3/AN3/ A
VREF+

VIN+

A

VIN-

RA2/AN2/ A
VREF-/CVREF

VIN+

C1

Off (Read as ‘0’)

C2

Off (Read as ‘0’)

Two Independent Comparators
CM2:CM0 = 010
A

VIN-

RA3/AN3/ A
VREF+

VIN+

A

VIN-

RA2/AN2/ A
VREF-/CVREF

VIN+

RA0/AN0

Comparator interrupts should be disabledduring a Comparator mode change.
Otherwise, a false interrupt may occur.

Comparators Off (POR Default Value)
CM2:CM0 = 111

A

RA1/AN1

Note:

COMPARATOR I/O OPERATING MODES

Comparators Reset
CM2:CM0 = 000
RA0/AN0mode is changed, the comparator output level may not
be valid for the specified mode change delay shown in
Section 28.0 “Electrical Characteristics”.

C1

RA0/AN0D

VIN-

RA3/AN3/
VREF+

D

VIN+

RA1/AN1

D

VIN-

DRA2/AN2/
VREF-/CVREF

VIN+

C1

Off (Read as ‘0’)

C2

Off (Read as ‘0’)

Two Independent Comparators with Outputs
CM2:CM0 = 011
RA0/AN0RA3/AN3/
VREF+

C1OUT

A

VIN-

A

VIN+

C1

C1OUT

C2

C2OUT

RA4/T0CKI/C1OUT*/RCV
RA1/AN1

C2

A

VIN-

RA2/AN2/ A
VREF-/CVREF

VIN+

RA1/AN1C2OUT

RA5/AN4/SS/HLVDIN/C2OUT*
Two Common Reference Comparators
CM2:CM0 = 100
A

VIN-

RA3/AN3/ A
VREF+

VIN+

A

VIN-

RA2/AN2/ D
VREF-/CVREF

VIN+

RA0/AN0RA1/AN1

C1

Two Common Reference Comparators with Outputs
CM2:CM0 = 101
RA0/AN0RA3/AN3/
VREF+

C1OUT

A

VIN-

A

VIN+

C1

C1OUT

C2

C2OUT

RA4/T0CKI/C1OUT*/
RCV
C2

C2OUT

RA1/AN1A

VIN-

RA2/AN2/
VREF-/CVREF

D

VIN+

RA5/AN4/SS/HLVDIN/C2OUT*
Four Inputs Multiplexed to Two Comparators
CM2:CM0 = 110

One Independent Comparator with Output
CM2:CM0 = 001
A

VIN-

RA3/AN3/ A
VREF+

VIN+

RA0/AN0

C1

C1OUT

RA4/T0CKI/C1OUT*/RCV
D

VIN-

RA2/AN2/ D
VREF-/CVREF

VIN+

RA1/AN1

RA0/AN0A

RA3/AN3/
VREF+

A

RA1/AN1AVINVIN+A
RA2/AN2/
VREF-/CVREF

C2

CIS = 0
CIS = 1

CIS = 0
CIS = 1

C1

C1OUT

C2

C2OUT

VINVIN+

Off (Read as ‘0’)
CVREF

From VREF Module

A = Analog Input, port reads zeros always
D = Digital Input
CIS (CMCON<3>) is the Comparator Input Switch* Setting the TRISA<5:4> bits will disable the comparator outputs by configuring the pins as inputs.

DS39632D-page 270

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22.2

22.3.2Comparator Operation

A single comparator is shown in Figure 22-2, along withthe relationship between the analog input levels andthe digital output. When the analog input at VIN+ is lessthan the analog input VIN-, the output of the comparator
is a digital low level. When the analog input at VIN+ isgreater than the analog input VIN-, the output of thecomparator is a digital high level. The shaded areas ofthe output of the comparator in Figure 22-2 represent
the uncertainty, due to input offsets and response time.

22.3

Comparator Reference

Depending on the comparator operating mode, either
an external or internal voltage reference may be used.
The analog signal present at VIN- is compared to thesignal at VIN+ and the digital output of the comparator
is adjusted accordingly (Figure 22-2).

FIGURE 22-2:

SINGLE COMPARATOR

VIN+

+

VIN-

–

The internal reference is only available in the mode
where four inputs are multiplexed to two comparators(CM2:CM0 = 110). In this mode, the internal voltage
reference is applied to the VIN+ pin of bothcomparators.

22.4

Comparator Response Time

Response time is the minimum time, after selecting a
new reference voltage or input source, before thecomparator output has a valid level. If the internal reference is changed, the maximum delay of the internal
voltage reference must be considered when using thecomparator outputs. Otherwise, the maximum delay ofthe comparators should be used (see Section 28.0
“Electrical Characteristics”).

Comparator Outputs

The comparator outputs are read through the CMCON
register. These bits are read-only. The comparator
outputs may also be directly output to the RA4 and RA5
I/O pins. When enabled, multiplexors in the output pathof the RA4 and RA5 pins will switch and the output ofeach pin will be the unsynchronized output of thecomparator. The uncertainty of each of thecomparators is related to the input offset voltage andthe response time given in the specifications.
Figure 22-3 shows the comparator output block
diagram.

VINVIN+

Output22.3.1

The comparator module also allows the selection of aninternally generated voltage reference from thecomparator voltage reference module. This module isdescribed in more detail in Section 23.0 “Comparator
Voltage Reference Module”.

22.5

OutputINTERNAL REFERENCE SIGNALThe TRISA bits will still function as an output enable/
disable for the RA4 and RA5 pins while in this mode.

EXTERNAL REFERENCE SIGNAL

When external voltage references are used, thecomparator module can be configured to have the comparators operate from the same or different reference
sources. However, threshold detector applications may
require the same reference. The reference signal must
be between VSS and VDD and can be applied to either
pin of the comparator(s).

© 2007 Microchip Technology Inc.

The polarity of the comparator outputs can be changed
using the C2INV and C1INV bits (CMCON<5:4>).
Note 1: When reading the PORT register, all pins
configured as analog inputs will read as a‘0’. Pins configured as digital inputs will
convert an analog input according to the
Schmitt Trigger input specification.

Preliminary

2: Analog levels on any pin defined as adigital input may cause the input buffer toconsume more current than is specified.

DS39632D-page 271

PIC18F2455/2550/4455/4550

Port pins+

COMPARATOR OUTPUT BLOCK DIAGRAM

MULTIPLEXFIGURE 22-3:

To RA4 orRA5 pin

D

Q

Bus
Data

D

Q

Set
CMIF
bit

EN

CL

CxINV
EN

Read CMCON

From
other
Comparator

Reset

22.6

Comparator Interrupts

22.7

The comparator interrupt flag is set whenever there isa change in the output value of either comparator.
Software will need to maintain information about thestatus of the output bits, as read from CMCON<7:6>, todetermine the actual change that occurred. The CMIF
bit (PIR2<6>) is the Comparator Interrupt Flag. The
CMIF bit must be reset by clearing it. Since it is also
possible to write a ‘1’ to this register, a simulated
interrupt may be initiated.
Both the CMIE bit (PIE2<6>) and the PEIE bit(INTCON<6>) must be set to enable the interrupt. In
addition, the GIE bit (INTCON<7>) must also be set. If
any of these bits are clear, the interrupt is not enabled,
though the CMIF bit will still be set if an interrupt
condition occurs.
Note:

If a change in the CMCON register(C1OUT or C2OUT) should occur when aread operation is being executed (start of
the Q2 cycle), then the CMIF (PIR2<6>)interrupt flag may not get set.

The user, in the Interrupt Service Routine, can clear theinterrupt in the following manner:a)b)Comparator Operation
During Sleep

When a comparator is active and the device is placedin Sleep mode, the comparator remains active and theinterrupt is functional if enabled. This interrupt will
wake-up the device from Sleep mode, when enabled.
Each operational comparator will consume additional
current, as shown in the comparator specifications. To
minimize power consumption while in Sleep mode, turnoff the comparators (CM2:CM0 = 111) before entering
Sleep. If the device wakes up from Sleep, the contentsof the CMCON register are not affected.

22.8

Effects of a Reset

A device Reset forces the CMCON register to its Resetstate, causing the comparator modules to be turned off(CM2:CM0 = 111). However, the input pins (RA0through RA3) are configured as analog inputs bydefault on device Reset. The I/O configuration for thesepins is determined by the setting of the PCFG3:PCFG0
bits (ADCON1<3:0>). Therefore, device current isminimized when analog inputs are present at Resettime.

Any read or write of CMCON will end themismatch condition.
Clear flag bit CMIF.

A mismatch condition will continue to set flag bit CMIF.
Reading CMCON will end the mismatch condition andallow flag bit CMIF to be cleared.

DS39632D-page 272

Preliminary© 2007 Microchip Technology Inc.

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22.9

Analog Input Connection
Considerations

range by more than 0.6V in either direction, one of thediodes is forward biased and a latch-up condition may
occur. A maximum source impedance of 10 kΩ isrecommended for the analog sources. Any external
component connected to an analog input pin, such asa capacitor or a Zener diode, should have very little
leakage current.

A simplified circuit for an analog input is shown in
Figure 22-4. Since the analog pins are connected to adigital output, they have reverse biased diodes to VDD
and VSS. The analog input, therefore, must be between
VSS and VDD. If the input voltage deviates from thisFIGURE 22-4:

COMPARATOR ANALOG INPUT MODEL
VDD
VT = 0.6V

RS < 10k

RIC
Comparator
Input

AIN
CPIN
5 pF

VA

VT = 0.6V

ILEAKAGE±500 nA

VSS
Legend:TABLE 22-1:

CPIN
=
VT
=
ILEAKAGE =
=
RIC
RS
=
VA
=

Input CapacitanceThreshold Voltage
Leakage Current at the pin due to various junctions
Interconnect ResistanceSource Impedance
Analog Voltage

REGISTERS ASSOCIATED WITH COMPARATOR MODULE

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset
Valueson page

CMCON

C2OUT

C1OUT

C2INV

C1INV

CIS

CM2

CM1

CM0

53

CVRCON

CVREN

CVROE

CVRR

CVRSS

CVR3

CVR2

CVR1

CVR0

53

INTCON

GIE/GIEH PEIE/GIEL

TMR0IEINT0IERBIE

TMR0IF

INT0IF

RBIF

51

PIR2

OSCFIF

CMIF

USBIF

EEIF

BCLIF

HLVDIF

TMR3IF

CCP2IF54

PIE2

OSCFIE

CMIE

USBIE

EEIE

BCLIE

HLVDIETMR3IECCP2IE54

IPR2

OSCFIP

CMIP

USBIP

EEIP

BCLIP

HLVDIP

TMR3IP

CCP2IP

54

PORTA

—

RA6(1)

RA5

RA4

RA3

RA2

RA1

RA0

54

LATA

—

LATA6(1)

LATA5

LATA4

LATA3

LATA2

LATA1

LATA0

54

TRISA

—

TRISA6(1)TRISA5TRISA4TRISA3

TRISA2TRISA1TRISA054

Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the comparator module.
Note 1: PORTA<6> and its direction and latch bits are individually configured as port pins based on various
oscillator modes. When disabled, these bits read as ‘0’.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 273

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NOTES:DS39632D-page 274

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
23.0

COMPARATOR VOLTAGE
REFERENCE MODULE

The comparator voltage reference is a 16-tap resistor
ladder network that provides a selectable reference
voltage. Although its primary purpose is to provide areference for the analog comparators, it may also be
used independently of them.
A block diagram of the module is shown in Figure 23-1.
The resistor ladder is segmented to provide two rangesof CVREF values and has a power-down function toconserve power when the reference is not being used.
The module’s supply reference can be provided fromeither device VDD/VSS or an external voltage reference.

23.1

Configuring the Comparator
Voltage Reference

The voltage reference module is controlled through the
CVRCON register (Register 23-1). The comparator
voltage reference provides two ranges of output
voltage, each with 16 distinct levels. The range to be

REGISTER 23-1:
R/W-0

If CVRR = 1:
CVREF = ((CVR3:CVR0)/24) x CVRSRC
If CVRR = 0:
CVREF = (CVRSRC/4) + (((CVR3:CVR0)/32) x
CVRSRC)The comparator reference supply voltage can comefrom either VDD and VSS, or the external VREF+ and
VREF- that are multiplexed with RA2 and RA3. The
voltage source is selected by the CVRSS bit(CVRCON<4>).
The settling time of the comparator voltage reference
must be considered when changing the CVREF
output (see Table 28-3 in Section 28.0 “Electrical
Characteristics”).

CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER
R/W-0
(1)

CVREN

used is selected by the CVRR bit (CVRCON<5>). The
primary difference between the ranges is the size of thesteps selected by the CVREF Selection bits
(CVR3:CVR0), with one range offering finer resolution.
The equations used to calculate the output of thecomparator voltage reference are as follows:

CVROE

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

CVRR

CVRSS

CVR3

CVR2

CVR1

CVR0

bit 7

bit 0

Legend:R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’-n = Value at POR‘1’ = Bit is set‘0’ = Bit is clearedx = Bit is unknown

bit 7

CVREN: Comparator Voltage Reference Enable bit
1 = CVREF circuit powered on
0 = CVREF circuit powered down

bit 6

CVROE: Comparator VREF Output Enable bit(1)1 = CVREF voltage level is also output on the RA2/AN2/VREF-/CVREF pin
0 = CVREF voltage is disconnected from the RA2/AN2/VREF-/CVREF pin

bit 5

CVRR: Comparator VREF Range Selection bit
1 = 0 to 0.667 CVRSRC, with CVRSRC/24 step size (low range)0 = 0.25 CVRSRC to 0.75 CVRSRC, with CVRSRC/32 step size (high range)

bit 4

CVRSS: Comparator VREF Source Selection bit
1 = Comparator reference source, CVRSRC = (VREF+) – (VREF-)
0 = Comparator reference source, CVRSRC = VDD – VSS

bit 3-0

CVR3:CVR0: Comparator VREF Value Selection bits (0 ≤ (CVR3:CVR0) ≤ 15)
When CVRR = 1:
CVREF = ((CVR3:CVR0)/24) • (CVRSRC)
When CVRR = 0:
CVREF = (CVRSRC/4) + ((CVR3:CVR0)/32) • (CVRSRC)

Note 1:CVROE overrides the TRISA<2> bit setting.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 275

PIC18F2455/2550/4455/4550
FIGURE 23-1:

COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
VREF+
VDD

CVRSS = 1

8R

CVRSS = 0

CVR3:CVR0

R

CVREN

R

16-to-1 MUX

R
R
16 Steps

CVREF

R
R
R

CVRR
VREF-

8R
CVRSS = 1

CVRSS = 023.2

Voltage Reference Accuracy/Error

The full range of voltage reference cannot be realized
due to the construction of the module. The transistors
on the top and bottom of the resistor ladder network(Figure 23-1) keep CVREF from approaching the reference source rails. The voltage reference is derived
from the reference source; therefore, the CVREF output
changes with fluctuations in that source. The tested
absolute accuracy of the voltage reference can befound in Section 28.0 “Electrical Characteristics”.

23.3

Operation During Sleep

When the device wakes up from Sleep through aninterrupt or a Watchdog Timer time-out, the contents of
the CVRCON register are not affected. To minimize
current consumption in Sleep mode, the voltage
reference should be disabled.

23.4

Effects of a Reset

A device Reset disables the voltage reference byclearing bit, CVREN (CVRCON<7>). This Reset also
disconnects the reference from the RA2 pin by clearing
bit, CVROE (CVRCON<6>) and selects the high-voltage
range by clearing bit, CVRR (CVRCON<5>). The CVRvalue select bits are also cleared.

23.5

Connection Considerations

The voltage reference module operates independentlyof the comparator module. The output of the reference
generator may be connected to the RA2 pin if the
TRISA<2> bit and the CVROE bit are both set.
Enabling the voltage reference output onto RA2 when
it is configured as a digital input will increase current
consumption. Connecting RA2 as a digital output withCVRSS enabled will also increase current
consumption.
The RA2 pin can be used as a simple D/A output withlimited drive capability. Due to the limited current drive
capability, a buffer must be used on the voltage
reference output for external connections to VREF.
Figure 23-2 shows an example buffering technique.

DS39632D-page 276

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
FIGURE 23-2:

COMPARATOR VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
PIC18FXXXX
CVREFModuleR(1)Voltage
Reference
OutputImpedance

Note 1:TABLE 23-1:

+
–

RA2

CVREF Output

R is dependent upon the voltage reference configuration bits, CVRCON<5> and CVRCON<3:0>.

REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE

Name

Bit 7

Bit 6

CVRCON

CVREN

CMCON

C2OUT

TRISA

—

Reset
Valueson page

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

CVROE

CVRR

CVRSS

CVR3

CVR2

CVR1

CVR0

53

C1OUT

C2INV

C1INV

CIS

CM2

CM1

CM0

53

TRISA6(1) TRISA5TRISA4TRISA3

TRISA2TRISA1TRISA054

Legend: Shaded cells are not used with the comparator voltage reference.
Note 1: PORTA<6> and its direction and latch bits are individually configured as port pins based on various
oscillator modes. When disabled, these bits read as ‘0’.

© 2007 Microchip Technology Inc.

Preliminary

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PIC18F2455/2550/4455/4550
NOTES:DS39632D-page 278

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
24.0

HIGH/LOW-VOLTAGE DETECT(HLVD)

PIC18F2455/2550/4455/4550 devices have a
High/Low-Voltage Detect module (HLVD). This is a programmable circuit that allows the user to specify both adevice voltage trip point and the direction of change
from that point. If the device experiences an excursion
past the trip point in that direction, an interrupt flag isset. If the interrupt is enabled, the program execution
will branch to the interrupt vector address and thesoftware can then respond to the interrupt.

REGISTER 24-1:
R/W-0

The block diagram for the HLVD module is shown in
Figure 24-1.

HLVDCON: HIGH/LOW-VOLTAGE DETECT CONTROL REGISTER
U-0

VDIRMAGThe High/Low-Voltage Detect Control register(Register 24-1) completely controls the operation of the
HLVD module. This allows the circuitry to be “turnedoff” by the user under software control which minimizes
the current consumption for the device.

—

R-0
IRVST

R/W-0

R/W-0

R/W-1

R/W-0

R/W-1

HLVDENHLVDL3(1)

HLVDL2(1)HLVDL1(1)HLVDL0(1)

bit 7

bit 0

Legend:R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’-n = Value at POR‘1’ = Bit is set‘0’ = Bit is clearedx = Bit is unknown

bit 7

VDIRMAG: Voltage Direction Magnitude Select bit
1 = Event occurs when voltage equals or exceeds trip point (HLVDL3:HLDVL0)
0 = Event occurs when voltage equals or falls below trip point (HLVDL3:HLVDL0)

bit 6

Unimplemented: Read as ‘0’

bit 5

IRVST: Internal Reference Voltage Stable Flag bit
1 = Indicates that the voltage detect logic will generate the interrupt flag at the specified voltage range
0 = Indicates that the voltage detect logic will not generate the interrupt flag at the specified voltage
range and the HLVD interrupt should not be enabledbit 4

HLVDEN: High/Low-Voltage Detect Power Enable bit
1 = HLVD enabled
0 = HLVD disabled

bit 3-0

HLVDL3:HLVDL0: Voltage Detection Limit bits(1)1111 = External analog input is used (input comes from the HLVDIN pin)
1110 = Maximum setting.
.
.
0000 = Minimum setting

Note 1:

See Table 28-6 in Section 28.0 “Electrical Characteristics” for specifications.

© 2007 Microchip Technology Inc.

Preliminary

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PIC18F2455/2550/4455/4550
The module is enabled by setting the HLVDEN bit.
Each time that the HLVD module is enabled, thecircuitry requires some time to stabilize. The IRVST bit
is a read-only bit and is used to indicate when the circuit
is stable. The module can only generate an interrupt
after the circuit is stable and IRVST is set.

event, depending on the configuration of the module.
When the supply voltage is equal to the trip point, thevoltage tapped off of the resistor array is equal to theinternal reference voltage generated by the voltage
reference module. The comparator then generates aninterrupt signal by setting the HLVDIF bit.

The VDIRMAG bit determines the overall operation of
the module. When VDIRMAG is cleared, the module
monitors for drops in VDD below a predetermined set
point. When the bit is set, the module monitors for rises
in VDD above the set point.

The trip point voltage is software programmable to any
one of 16 values. The trip point is selected byprogrammingthe
HLVDL3:HLVDL0
bits(HLVDCON<3:0>).

24.1

The HLVD module has an additional feature that allows
the user to supply the trip voltage to the module from anexternal source. This mode is enabled when bits,
HLVDL3:HLVDL0, are set to ‘1111’. In this state, thecomparator input is multiplexed from the external input
pin, HLVDIN. This gives users flexibility because it
allows them to configure the High/Low-Voltage Detect
interrupt to occur at any voltage in the valid operating
range.

Operation

When the HLVD module is enabled, a comparator uses
an internally generated reference voltage as the set
point. The set point is compared with the trip point,where each node in the resistor divider represents a
trip point voltage. The “trip point” voltage is the voltage
level at which the device detects a high or low-voltage

FIGURE 24-1:

HLVD MODULE BLOCK DIAGRAM (WITH EXTERNAL INPUT)

Externally Generated
Trip Point
VDD
VDD

HLVDL3:HLVDL0

HLVDCON
Register

HLVDEN

16-to-1 MUXHLVDINVDIRMAGSet
HLVDIFHLVDEN

BOREN

DS39632D-page 280

Internal Voltage
Reference
1.2V Typical

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
24.2

HLVD Setup

Depending on the application, the HLVD module does
not need to be operating constantly. To decrease thecurrent requirements, the HLVD circuitry may only
need to be enabled for short periods where the voltage
is checked. After doing the check, the HLVD module
may be disabled.

The following steps are needed to set up the HLVD
module:
1.
2.
3.
4.
5.

6.

Disable the module by clearing the HLVDEN bit(HLVDCON<4>).
Write the value to the HLVDL3:HLVDL0 bits that
selects the desired HLVD trip point.
Set the VDIRMAG bit to detect high voltage(VDIRMAG = 1) or low voltage (VDIRMAG = 0).
Enable the HLVD module by setting the
HLVDEN bit.
Clear the HLVD Interrupt Flag, HLVDIF(PIR2<2>), which may have been set from aprevious interrupt.
Enable the HLVD interrupt, if interrupts aredesired, by setting the HLVDIE and GIE/GIEH
bits (PIE2<2> and INTCON<7>). An interrupt
will not be generated until the IRVST bit is set.

24.3

24.4

The internal reference voltage of the HLVD module,
specified in electrical specification parameter D420 (seeTable 28-6 in Section 28.0 “Electrical Characteristics”), may be used by other internal circuitry, such as
the Programmable Brown-out Reset. If the HLVD orother circuits using the voltage reference are disabled tolower the device’s current consumption, the reference
voltage circuit will require time to become stable before
a low or high-voltage condition can be reliably detected.
This start-up time, TIRVST, is an interval that is independent of device clock speed. It is specified in electrical
specification parameter 36 (Table 28-12).

Current Consumption

The HLVD interrupt flag is not enabled until TIRVST has
expired and a stable reference voltage is reached. For
this reason, brief excursions beyond the set point may
not be detected during this interval. Refer toFigure 24-2 or Figure 24-3.

When the module is enabled, the HLVD comparator
and voltage divider are enabled and will consume static
current. The total current consumption, when enabled,is specified in electrical specification parameter D022
(Section 28.2 “DC Characteristics”).

FIGURE 24-2:

HLVD Start-up Time

LOW-VOLTAGE DETECT OPERATION (VDIRMAG = 0)

CASE 1:HLVDIF may not be set
VDD
VHLVD
HLVDIF

Enable HLVDTIRVST

IRVSTInternal Reference is stable

HLVDIF cleared in software

CASE 2:VDD
VHLVD
HLVDIF
Enable HLVDTIRVST

IRVSTInternal Reference is stable

HLVDIF cleared in software
HLVDIF cleared in software,
HLVDIF remains set since HLVD condition still exists© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 281

PIC18F2455/2550/4455/4550
FIGURE 24-3:

HIGH-VOLTAGE DETECT OPERATION (VDIRMAG = 1)

CASE 1:HLVDIF may not be set
VHLVD
VDD
HLVDIF

Enable HLVDTIRVSTIRVST

HLVDIF cleared in software
Internal Reference is stable
CASE 2:VHLVD
VDD

HLVDIF
Enable HLVDTIRVST

IRVSTInternal Reference is stable

HLVDIF cleared in software
HLVDIF cleared in software,
HLVDIF remains set since HLVD condition still exists

FIGURE 24-4:

Applications

In many applications, the ability to detect a drop below
or rise above a particular threshold is desirable. For
example, the HLVD module could be periodicallyenabled to detect Universal Serial Bus (USB) attach or
detach. This assumes the device is powered by a lower
voltage source than the USB when detached. An attachwould indicate a high-voltage detect from, for example,
3.3V to 5V (the voltage on USB) and vice versa for a
detach. This feature could save a design a few extra
components and an attach signal (input pin).
For general battery applications, Figure 24-4 shows apossible voltage curve. Over time, the device voltage
decreases. When the device voltage reaches voltage,
VA, the HLVD logic generates an interrupt at time, TA.
The interrupt could cause the execution of an ISR,
which would allow the application to perform “housekeeping tasks” and perform a controlled shutdown
before the device voltage exits the valid operating
range at TB. The HLVD, thus, would give the application a time window, represented by the difference
between TA and TB, to safely exit.

DS39632D-page 282

TYPICAL
HIGH/LOW-VOLTAGE
DETECT APPLICATION

VA
VB
Voltage

24.5

Preliminary

Time

TA

TB

Legend: VA = HLVD trip point
VB = Minimum valid device
operating voltage© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
24.6

Operation During Sleep

24.7

When enabled, the HLVD circuitry continues to operate
during Sleep. If the device voltage crosses the trip
point, the HLVDIF bit will be set and the device will
wake-up from Sleep. Device execution will continue
from the interrupt vector address if interrupts havebeen globally enabled.

TABLE 24-1:

Effects of a Reset

A device Reset forces all registers to their Reset state.
This forces the HLVD module to be turned off.

REGISTERS ASSOCIATED WITH HIGH/LOW-VOLTAGE DETECT MODULE

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset
Valueson page

HLVDCON

VDIRMAG—IRVST

HLVDENHLVDL3

HLVDL2

HLVDL1

HLVDL052

INTCON

GIE/GIEH PEIE/GIEL

TMR0IEINT0IERBIE

TMR0IF

INT0IF

RBIF

51

PIR2

OSCFIF

CMIF

USBIF

EEIF

BCLIF

HLVDIF

TMR3IF

CCP2IF54

PIE2

OSCFIE

CMIE

USBIE

EEIE

BCLIE

HLVDIETMR3IECCP2IE54

IPR2

OSCFIP

CMIP

USBIP

EEIP

BCLIP

HLVDIP

TMR3IP

CCP2IP

54

Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the HLVD module.

© 2007 Microchip Technology Inc.

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NOTES:DS39632D-page 284

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
25.0

SPECIAL FEATURES OF THE
CPU

PIC18F2455/2550/4455/4550 devices include several
features intended to maximize reliability and minimize
cost through elimination of external components.
These are:• Oscillator Selection• Resets:- Power-on Reset (POR)- Power-up Timer (PWRT)- Oscillator Start-up Timer (OST)- Brown-out Reset (BOR)• Interrupts• Watchdog Timer (WDT)• Fail-Safe Clock Monitor• Two-Speed Start-up• Code Protection• ID Locations• In-Circuit Serial Programming

In addition to their Power-up and Oscillator Start-up Timers provided for Resets, PIC18F2455/2550/4455/4550
devices have a Watchdog Timer, which is either
permanently enabled via the Configuration bits orsoftware controlled (if configured as disabled).
The inclusion of an internal RC oscillator also provides
the additional benefits of a Fail-Safe Clock Monitor(FSCM) and Two-Speed Start-up. FSCM provides forbackground monitoring of the peripheral clock andautomatic switchover in the event of its failure.
Two-Speed Start-up enables code to be executedalmost immediately on start-up, while the primary clock
source completes its start-up delays.
All of these features are enabled and configured by
setting the appropriate Configuration register bits.

The oscillator can be configured for the application
depending on frequency, power, accuracy and cost. Allof the options are discussed in detail in Section 2.0“Oscillator Configurations”.
A complete discussion of device Resets and interrupts
is available in previous sections of this data sheet.

© 2007 Microchip Technology Inc.

Preliminary

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PIC18F2455/2550/4455/4550
25.1

Configuration Bits

Programming the Configuration registers is done in amanner similar to programming the Flash memory. The
WR bit in the EECON1 register starts a self-timed write
to the Configuration register. In normal operation mode,a TBLWT instruction, with the TBLPTR pointing to the
Configuration register, sets up the address and thedata for the Configuration register write. Setting the WR
bit starts a long write to the Configuration register. The
Configuration registers are written a byte at a time. To
write or erase a configuration cell, a TBLWT instruction
can write a ‘1’ or a ‘0’ into the cell. For additional details
on Flash programming, refer to Section 6.5 “Writing
to Flash Program Memory”.

The Configuration bits can be programmed (read as‘0’) or left unprogrammed (read as ‘1’) to select various
device configurations. These bits are mapped startingat program memory location 300000h.
The user will note that address 300000h is beyond theuser program memory space. In fact, it belongs to theconfiguration memory space (300000h-3FFFFFh),which can only be accessed using table reads andtable writes.

TABLE 25-1:

CONFIGURATION BITS AND DEVICE IDs

File Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

USBDIV CPUDIV1 CPUDIV0 PLLDIV2

Bit 1

Bit 0

Default/
Unprogrammed
Value

PLLDIV1

PLLDIV0--00 0000

FOSC000-- 0101

300000h

CONFIG1L——

300001h

CONFIG1H

IESO

FCMEN

—

—

FOSC3

FOSC2

FOSC1

300002h

CONFIG2L——

VREGEN

BORV1

BORV0

BOREN1

BOREN0 PWRTEN

300003h

CONFIG2H———

300005h

CONFIG3H

MCLRE

—

—

—

—

300006h

CONFIG4L

DEBUG

XINST

ICPRT(3)

—

—

LVP

—

STVREN

100- -1-1

300008h

CONFIG5L

—

—

—

—

CP3(1)

CP2

CP1

CP0

---- 1111

300009h

CONFIG5H

CPD

CPB

—

—

—

—

—

—

11-- ----

30000AhCONFIG6L

—

—

—

—

WRT3(1)

WRT2

WRT1

WRT0

---- 1111

30000Bh

CONFIG6H

WRTD

WRTB

WRTC

—

—

—

—

—

111- ----

30000Ch

CONFIG7L

—

—

—

—

EBTR3(1)

EBTR2

EBTR1

EBTR0

---- 1111

30000Dh

CONFIG7H

WDTPS3 WDTPS2 WDTPS1 WDTPS0WDTEN

LPT1OSC PBADEN CCP2MX--01 1111---1 1111
1--- -011

—

EBTRB

—

—

—

—

—

—

-1-- ----

3FFFFEh DEVID1

DEV2

DEV1

DEV0

REV4

REV3

REV2

REV1

REV0

xxxx xxxx(2)3FFFFFh

DEVID2

DEV10

DEV9

DEV8

DEV7

DEV6

DEV5

DEV4

DEV3

0001 0010(2)Legend:Note 1:2:

x = unknown, u = unchanged, - = unimplemented. Shaded cells are unimplemented, read as ‘0’.
Unimplemented in PIC18FX455 devices; maintain this bit set.
See Register 25-13 and Register 25-14 for DEVID values. DEVID registers are read-only and cannot be programmed by
the user.
Available only on PIC18F4455/4550 devices in 44-pin TQFP packages. Always leave this bit clear in all other devices.

3:

DS39632D-page 286

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PIC18F2455/2550/4455/4550
REGISTER 25-1:

CONFIG1L: CONFIGURATION REGISTER 1 LOW (BYTE ADDRESS 300000h)

U-0

U-0

R/P-0

R/P-0

R/P-0

R/P-0

R/P-0

R/P-0

—

—

USBDIV

CPUDIV1

CPUDIV0PLLDIV2

PLLDIV1

PLLDIV0

bit 7

bit 0

Legend:R = Readable bit

P = Programmable bit-n = Value when device is unprogrammed

U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state

bit 7-6

Unimplemented: Read as ‘0’

bit 5

USBDIV: USB Clock Selection bit (used in Full-Speed USB mode only; UCFG:FSEN = 1)
1 = USB clock source comes from the 96 MHz PLL divided by 2
0 = USB clock source comes directly from the primary oscillator block with no postscale

bit 4-3

CPUDIV1:CPUDIV0: System Clock Postscaler Selection bits
For XT, HS, EC and ECIO Oscillator modes:
11 = Primary oscillator divided by 4 to derive system clock
10 = Primary oscillator divided by 3 to derive system clock
01 = Primary oscillator divided by 2 to derive system clock
00 = Primary oscillator used directly for system clock (no postscaler)
For XTPLL, HSPLL, ECPLL and ECPIO Oscillator modes:
11 = 96 MHz PLL divided by 6 to derive system clock
10 = 96 MHz PLL divided by 4 to derive system clock
01 = 96 MHz PLL divided by 3 to derive system clock
00 = 96 MHz PLL divided by 2 to derive system clock

bit 2-0

PLLDIV2:PLLDIV0: PLL Prescaler Selection bits
111 = Divide by 12 (48 MHz oscillator input)
110 = Divide by 10 (40 MHz oscillator input)
101 = Divide by 6 (24 MHz oscillator input)
100 = Divide by 5 (20 MHz oscillator input)
011 = Divide by 4 (16 MHz oscillator input)
010 = Divide by 3 (12 MHz oscillator input)
001 = Divide by 2 (8 MHz oscillator input)
000 = No prescale (4 MHz oscillator input drives PLL directly)© 2007 Microchip Technology Inc.

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PIC18F2455/2550/4455/4550
REGISTER 25-2:

CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h)

R/P-0

R/P-0

U-0

U-0

R/P-0

R/P-1

R/P-0

R/P-1

IESO

FCMEN

—

—

FOSC3(1)

FOSC2(1)

FOSC1(1)

FOSC0(1)

bit 7

bit 0

Legend:R = Readable bit

P = Programmable bit-n = Value when device is unprogrammed

U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state

bit 7

IESO: Internal/External Oscillator Switchover bit
1 = Oscillator Switchover mode enabled
0 = Oscillator Switchover mode disabledbit 6

FCMEN: Fail-Safe Clock Monitor Enable bit
1 = Fail-Safe Clock Monitor enabled
0 = Fail-Safe Clock Monitor disabled

bit 5-4

Unimplemented: Read as ‘0’

bit 3-0

FOSC3:FOSC0: Oscillator Selection bits(1)111x = HS oscillator, PLL enabled (HSPLL)
110x = HS oscillator (HS)1011 = Internal oscillator, HS oscillator used by USB (INTHS)
1010 = Internal oscillator, XT used by USB (INTXT)
1001 = Internal oscillator, CLKO function on RA6, EC used by USB (INTCKO)
1000 = Internal oscillator, port function on RA6, EC used by USB (INTIO)
0111 = EC oscillator, PLL enabled, CLKO function on RA6 (ECPLL)
0110 = EC oscillator, PLL enabled, port function on RA6 (ECPIO)
0101 = EC oscillator, CLKO function on RA6 (EC)0100 = EC oscillator, port function on RA6 (ECIO)
001x = XT oscillator, PLL enabled (XTPLL)
000x = XT oscillator (XT)

Note 1:

The microcontroller and USB module both use the selected oscillator as their clock source in XT, HS andEC modes. The USB module uses the indicated XT, HS or EC oscillator as its clock source whenever the
microcontroller uses the internal oscillator.

DS39632D-page 288

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PIC18F2455/2550/4455/4550
REGISTER 25-3:
U-0

CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h)
U-0

—

—

R/P-0

R/P-1

R/P-1

R/P-1

R/P-1

R/P-1

VREGENBORV1(1)

BORV0(1)

BOREN1(2)

BOREN0(2)PWRTEN(2)

bit 7

bit 0

Legend:R = Readable bit

P = Programmable bit-n = Value when device is unprogrammed

U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state

bit 7-6

Unimplemented: Read as ‘0’

bit 5

VREGEN: USB Internal Voltage Regulator Enable bit
1 = USB voltage regulator enabled
0 = USB voltage regulator disabled

bit 4-3

BORV1:BORV0: Brown-out Reset Voltage bits(1)11 = Minimum setting.
.
.
00 = Maximum setting

bit 2-1

BOREN1:BOREN0: Brown-out Reset Enable bits(2)11 = Brown-out Reset enabled in hardware only (SBOREN is disabled)
10 = Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled)
01 = Brown-out Reset enabled and controlled by software (SBOREN is enabled)
00 = Brown-out Reset disabled in hardware and software

bit 0

PWRTEN: Power-up Timer Enable bit(2)1 = PWRT disabled
0 = PWRT enabled

Note 1:
2:

See Section 28.0 “Electrical Characteristics” for the specifications.
The Power-up Timer is decoupled from Brown-out Reset, allowing these features to be independently
controlled.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 289

PIC18F2455/2550/4455/4550
REGISTER 25-4:

CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h)

U-0

U-0

U-0

R/P-1

R/P-1

R/P-1

R/P-1

R/P-1

—

—

—

WDTPS3WDTPS2WDTPS1WDTPS0

WDTEN

bit 7

bit 0

Legend:R = Readable bit

P = Programmable bit-n = Value when device is unprogrammed

U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state

bit 7-5

Unimplemented: Read as ‘0’

bit 4-1

WDTPS3:WDTPS0: Watchdog Timer Postscale Select bits
1111 = 1:32,768
1110 = 1:16,384
1101 = 1:8,192
1100 = 1:4,096
1011 = 1:2,048
1010 = 1:1,024
1001 = 1:512
1000 = 1:256
0111 = 1:128
0110 = 1:64
0101 = 1:32
0100 = 1:16
0011 = 1:80010 = 1:40001 = 1:20000 = 1:1

bit 0

WDTEN: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled (control is placed on the SWDTEN bit)

DS39632D-page 290

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PIC18F2455/2550/4455/4550
REGISTER 25-5:

CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h)

R/P-1

U-0

U-0

U-0

U-0

R/P-0

R/P-1

R/P-1

MCLRE

—

—

—

—

LPT1OSCPBADEN

CCP2MX

bit 7

bit 0

Legend:R = Readable bit

P = Programmable bit-n = Value when device is unprogrammed

U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state

bit 7

MCLRE: MCLR Pin Enable bit
1 = MCLR pin enabled, RE3 input pin disabled
0 = RE3 input pin enabled, MCLR pin disabled

bit 6-3

Unimplemented: Read as ‘0’

bit 2

LPT1OSC: Low-Power Timer1 Oscillator Enable bit
1 = Timer1 configured for low-power operation
0 = Timer1 configured for higher power operation

bit 1

PBADEN: PORTB A/D Enable bit(Affects ADCON1 Reset state. ADCON1 controls PORTB<4:0> pin configuration.)
1 = PORTB<4:0> pins are configured as analog input channels on Reset
0 = PORTB<4:0> pins are configured as digital I/O on Reset

bit 0

CCP2MX: CCP2 MUX bit
1 = CCP2 input/output is multiplexed with RC1
0 = CCP2 input/output is multiplexed with RB3© 2007 Microchip Technology Inc.

Preliminary

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PIC18F2455/2550/4455/4550
REGISTER 25-6:
R/P-1

CONFIG4L: CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS 300006h)
R/P-0
XINST

DEBUG

R/P-0
ICPRT

(1)

U-0

U-0

R/P-1

U-0

R/P-1

—

—

LVP

—

STVREN

bit 7

bit 0

Legend:R = Readable bit

P = Programmable bit-n = Value when device is unprogrammed

U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state

bit 7

DEBUG: Background Debugger Enable bit
1 = Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins
0 = Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug

bit 6

XINST: Extended Instruction Set Enable bit
1 = Instruction set extension and Indexed Addressing mode enabled
0 = Instruction set extension and Indexed Addressing mode disabled (Legacy mode)

bit 5

ICPRT: Dedicated In-Circuit Debug/Programming Port (ICPORT) Enable bit(1)1 = ICPORT enabled
0 = ICPORT disabled

bit 4-3

Unimplemented: Read as ‘0’

bit 2

LVP: Single-Supply ICSP™ Enable bit
1 = Single-Supply ICSP enabled
0 = Single-Supply ICSP disabled

bit 1

Unimplemented: Read as ‘0’

bit 0

STVREN: Stack Full/Underflow Reset Enable bit
1 = Stack full/underflow will cause Reset
0 = Stack full/underflow will not cause Reset

Note 1:

Available only on PIC18F4455/4550 devices in 44-pin TQFP packages. Always leave this bit clear in allother devices.

DS39632D-page 292

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PIC18F2455/2550/4455/4550
REGISTER 25-7:

CONFIG5L: CONFIGURATION REGISTER 5 LOW (BYTE ADDRESS 300008h)

U-0

U-0

U-0

U-0

R/C-1

R/C-1

R/C-1

R/C-1

—

—

—

—

CP3(1)

CP2

CP1

CP0

bit 7

bit 0

Legend:R = Readable bit

C = Clearable bit

U = Unimplemented bit, read as ‘0’-n = Value when device is unprogrammedu = Unchanged from programmed state

bit 7-4

Unimplemented: Read as ‘0’

bit 3

CP3: Code Protection bit(1)1 = Block 3 (006000-007FFFh) is not code-protected
0 = Block 3 (006000-007FFFh) is code-protected

bit 2

CP2: Code Protection bit
1 = Block 2 (004000-005FFFh) is not code-protected
0 = Block 2 (004000-005FFFh) is code-protected

bit 1

CP1: Code Protection bit
1 = Block 1 (002000-003FFFh) is not code-protected
0 = Block 1 (002000-003FFFh) is code-protected

bit 0

CP0: Code Protection bit
1 = Block 0 (000800-001FFFh) is not code-protected
0 = Block 0 (000800-001FFFh) is code-protected

Note 1:

Unimplemented in PIC18FX455 devices; maintain this bit set.

REGISTER 25-8:

CONFIG5H: CONFIGURATION REGISTER 5 HIGH (BYTE ADDRESS 300009h)

R/C-1

R/C-1

U-0

U-0

U-0

U-0

U-0

U-0

CPD

CPB

—

—

—

—

—

—

bit 7

bit 0

Legend:R = Readable bit

C = Clearable bit

U = Unimplemented bit, read as ‘0’-n = Value when device is unprogrammedu = Unchanged from programmed state

bit 7

CPD: Data EEPROM Code Protection bit
1 = Data EEPROM is not code-protected
0 = Data EEPROM is code-protected

bit 6

CPB: Boot Block Code Protection bit
1 = Boot block (000000-0007FFh) is not code-protected
0 = Boot block (000000-0007FFh) is code-protected

bit 5-0

Unimplemented: Read as ‘0’© 2007 Microchip Technology Inc.

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PIC18F2455/2550/4455/4550
REGISTER 25-9:

CONFIG6L: CONFIGURATION REGISTER 6 LOW (BYTE ADDRESS 30000Ah)

U-0

U-0

U-0

U-0

R/C-1

R/C-1

R/C-1

R/C-1

—

—

—

—

WRT3(1)

WRT2

WRT1

WRT0

bit 7

bit 0

Legend:R = Readable bit

C = Clearable bit

U = Unimplemented bit, read as ‘0’-n = Value when device is unprogrammedu = Unchanged from programmed state

bit 7-4

Unimplemented: Read as ‘0’

bit 3

WRT3: Write Protection bit(1)1 = Block 3 (006000-007FFFh) is not write-protected
0 = Block 3 (006000-007FFFh) is write-protected

bit 2

WRT2: Write Protection bit
1 = Block 2 (004000-005FFFh) is not write-protected
0 = Block 2 (004000-005FFFh) is write-protected

bit 1

WRT1: Write Protection bit
1 = Block 1 (002000-003FFFh) is not write-protected
0 = Block 1 (002000-003FFFh) is write-protected

bit 0

WRT0: Write Protection bit
1 = Block 0 (000800-001FFFh) or (001000-001FFFh) is not write-protected
0 = Block 0 (000800-001FFFh) or (001000-001FFFh) is write-protected

Note 1:

Unimplemented in PIC18FX455 devices; maintain this bit set.

REGISTER 25-10: CONFIG6H: CONFIGURATION REGISTER 6 HIGH (BYTE ADDRESS 30000Bh)
R/C-1

R/C-1

WRTD

WRTB

R-1
(1)

WRTC

U-0

U-0

U-0

U-0

U-0

—

—

—

—

—

bit 7

bit 0

Legend:R = Readable bit

C = Clearable bit

U = Unimplemented bit, read as ‘0’-n = Value when device is unprogrammedu = Unchanged from programmed state

bit 7

WRTD: Data EEPROM Write Protection bit
1 = Data EEPROM is not write-protected
0 = Data EEPROM is write-protected

bit 6

WRTB: Boot Block Write Protection bit
1 = Boot block (000000-0007FFh) is not write-protected
0 = Boot block (000000-0007FFh) is write-protected

bit 5

WRTC: Configuration Register Write Protection bit(1)1 = Configuration registers (300000-3000FFh) are not write-protected
0 = Configuration registers (300000-3000FFh) are write-protected

bit 4-0

Unimplemented: Read as ‘0’Note 1:This bit is read-only in normal execution mode; it can be written only in Program mode.

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PIC18F2455/2550/4455/4550
REGISTER 25-11: CONFIG7L: CONFIGURATION REGISTER 7 LOW (BYTE ADDRESS 30000Ch)
U-0

U-0

U-0

U-0

R/C-1

R/C-1

R/C-1

R/C-1

—

—

—

—

EBTR3(1)

EBTR2

EBTR1

EBTR0

bit 7

bit 0

Legend:R = Readable bit

C = Clearable bit

U = Unimplemented bit, read as ‘0’-n = Value when device is unprogrammedu = Unchanged from programmed state

bit 7-4

Unimplemented: Read as ‘0’

bit 3

EBTR3: Table Read Protection bit(1)1 = Block 3 (006000-007FFFh) not protected from table reads executed in other blocks
0 = Block 3 (006000-007FFFh) protected from table reads executed in other blocks

bit 2

EBTR2: Table Read Protection bit
1 = Block 2 (004000-005FFFh) not protected from table reads executed in other blocks
0 = Block 2 (004000-005FFFh) protected from table reads executed in other blocks

bit 1

EBTR1: Table Read Protection bit
1 = Block 1 (002000-003FFFh) is not protected from table reads executed in other blocks
0 = Block 1 (002000-003FFFh) is protected from table reads executed in other blocks

bit 0

EBTR0: Table Read Protection bit
1 = Block 0 (000800-001FFFh) is not protected from table reads executed in other blocks
0 = Block 0 (000800-001FFFh) is protected from table reads executed in other blocks

Note 1:

Unimplemented in PIC18FX455 devices; maintain this bit set.

REGISTER 25-12: CONFIG7H: CONFIGURATION REGISTER 7 HIGH (BYTE ADDRESS 30000Dh)
U-0

R/C-1

U-0

U-0

U-0

U-0

U-0

U-0

—

EBTRB

—

—

—

—

—

—

bit 7

bit 0

Legend:R = Readable bit

C = Clearable bit-n = Value when device is unprogrammed

U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state

bit 7

Unimplemented: Read as ‘0’

bit 6

EBTRB: Boot Block Table Read Protection bit
1 = Boot block (000000-0007FFh) is not protected from table reads executed in other blocks
0 = Boot block (000000-0007FFh) is protected from table reads executed in other blocks

bit 5-0

Unimplemented: Read as ‘0’© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 295

PIC18F2455/2550/4455/4550
REGISTER 25-13: DEVID1: DEVICE ID REGISTER 1 FOR PIC18F2455/2550/4455/4550 DEVICES
R

R

R

R

R

R

R

R

DEV2

DEV1

DEV0

REV4

REV3

REV2

REV1

REV0

bit 7

bit 0

Legend:R = Read-only bit

P = Programmable bit-n = Value when device is unprogrammed

U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state

bit 7-5

DEV2:DEV0: Device ID bits
011 = PIC18F2455
010 = PIC18F2550
001 = PIC18F4455
000 = PIC18F4550

bit 4-0

REV3:REV0: Revision ID bits
These bits are used to indicate the device revision.

REGISTER 25-14: DEVID2: DEVICE ID REGISTER 2 FOR PIC18F2455/2550/4455/4550 DEVICES
R

R

R

R

R

R

R

R

DEV10(1)DEV9(1)

DEV8(1)

DEV7(1)

DEV6(1)

DEV5(1)

DEV4(1)

DEV3(1)

bit 7

bit 0

Legend:R = Read-only bit

P = Programmable bit-n = Value when device is unprogrammed
bit 7-0

Note 1:U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state

DEV10:DEV3: Device ID bits(1)These bits are used with the DEV2:DEV0 bits in the Device ID Register 1 to identify the part number.
0001 0010 = PIC18F2455/2550/4455/4550 devices
These values for DEV10:DEV3 may be shared with other devices. The specific device is always identified
by using the entire DEV10:DEV0 bit sequence.

DS39632D-page 296

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PIC18F2455/2550/4455/4550
25.2

Watchdog Timer (WDT)For PIC18F2455/2550/4455/4550 devices, the WDT isdriven by the INTRC source. When the WDT isenabled, the clock source is also enabled. The nominal
WDT period is 4 ms and has the same stability as the
INTRC oscillator.
The 4 ms period of the WDT is multiplied by a 16-bit
postscaler. Any output of the WDT postscaler isselected by a multiplexer, controlled by bits in Configuration Register 2H. Available periods range from 4 ms
to 131.072 seconds (2.18 minutes). The WDT andpostscaler are cleared when any of the following eventsoccur: a SLEEP or CLRWDT instruction is executed, the
IRCF bits (OSCCON<6:4>) are changed or a clock
failure has occurred.
.

FIGURE 25-1:

Note 1: The CLRWDT and SLEEP instructions
clear the WDT and postscaler counts
when executed.
2: Changing the setting of the IRCF bits
(OSCCON<6:4>) clears the WDT andpostscaler counts.
3: When a CLRWDT instruction is executed,
the postscaler count will be cleared.

25.2.1

CONTROL REGISTER

Register 25-15 shows the WDTCON register. This is areadable and writable register which contains a control
bit that allows software to override the WDT enable
Configuration bit, but only if the Configuration bit has
disabled the WDT.

WDT BLOCK DIAGRAMSWDTEN
WDTEN

Enable WDT

INTRC Control

WDT Counter
INTRC Source

÷128

Wake-up fromPower-Managed
Modes

Change on IRCF bits
Programmable Postscaler
1:1 to 1:32,768

CLRWDTAll Device Resets
WDTPS<3:0>

Reset

WDT
Reset

WDT
4

SLEEP

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 297

PIC18F2455/2550/4455/4550
REGISTER 25-15: WDTCON: WATCHDOG TIMER CONTROL REGISTER
U-0

U-0

U-0

U-0

U-0

U-0

U-0

R/W-0

—

—

—

—

—

—

—

SWDTEN(1)

bit 7

bit 0

Legend:R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’-n = Value at POR‘1’ = Bit is set‘0’ = Bit is cleared

bit 7-1

Unimplemented: Read as ‘0’

bit 0

SWDTEN: Software Controlled Watchdog Timer Enable bit(1)1 = Watchdog Timer is on
0 = Watchdog Timer is off

Note 1:x = Bit is unknown

This bit has no effect if the Configuration bit, WDTEN, is enabled.

TABLE 25-2:

SUMMARY OF WATCHDOG TIMER REGISTERS
Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset
Valueson page

RCON

IPEN

SBOREN(1)

—

RI

TO

PD

POR

BOR

52

WDTCON

—

—

—

—

—

—

—

SWDTEN

52

Name

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Watchdog Timer.
Note 1: The SBOREN bit is only available when BOREN<1:0> = 01; otherwise, the bit reads as ‘0’.

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PIC18F2455/2550/4455/4550
25.3

Two-Speed Start-up

Reset. For wake-ups from Sleep, the INTOSC or
postscaler clock sources can be selected by setting
IRCF2:IRCF0 prior to entering Sleep mode.

The Two-Speed Start-up feature helps to minimize thelatency period, from oscillator start-up to code execution, by allowing the microcontroller to use the INTRC
oscillator as a clock source until the primary clock
source is available. It is enabled by setting the IESO
Configuration bit.

In all other power-managed modes, Two-Speed Start-up
is not used. The device will be clocked by the currently
selected clock source until the primary clock source
becomes available. The setting of the IESO bit isignored.

Two-Speed Start-up should be enabled only if the
primary oscillator mode is XT, HS, XTPLL or HSPLL(Crystal-based modes). Other sources do not requirean OST start-up delay; for these, Two-Speed Start-up
should be disabled.

25.3.1

While using the INTRC oscillator in Two-Speed Start-up,
the device still obeys the normal command sequences
for entering power-managed modes, including serial
SLEEP instructions (refer to Section 3.1.4 “Multiple
Sleep Commands”). In practice, this means that user
code can change the SCS1:SCS0 bit settings or issue
SLEEP instructions before the OST times out. This would
allow an application to briefly wake-up, perform routine“housekeeping” tasks and return to Sleep before thedevice starts to operate from the primary oscillator.

When enabled, Resets and wake-ups from Sleep modecause the device to configure itself to run from the internal oscillator block as the clock source, following thetime-out of the Power-up Timer after a Power-on Resetis enabled. This allows almost immediate code
execution while the primary oscillator starts and the
OST is running. Once the OST times out, the device
automatically switches to PRI_RUN mode.
Because the OSCCON register is cleared on Reset
events, the INTOSC (or postscaler) clock source is notinitially available after a Reset event; the INTRC clock
is used directly at its base frequency. To use a higher
clock speed on wake-up, the INTOSC or postscaler
clock sources can be selected to provide a higher clock
speed by setting bits, IRCF2:IRCF0, immediately after

FIGURE 25-2:

SPECIAL CONSIDERATIONS FOR
USING TWO-SPEED START-UP

User code can also check if the primary clock source iscurrently providing the device clocking by checking thestatus of the OSTS bit (OSCCON<3>). If the bit is set,
the primary oscillator is providing the clock. Otherwise,
the internal oscillator block is providing the clock during
wake-up from Reset or Sleep mode.

TIMING TRANSITION FOR TWO-SPEED START-UP (INTOSC TO HSPLL)
Q1

Q2

Q3

Q4

Q2 Q3 Q4 Q1 Q2 Q3

Q1INTOSC
Multiplexer
OSC1
TOST(1)

TPLL(1)
1

PLL Clock
Output

2

n-1 n

Clock
Transition
CPU Clock
Peripheral
Clock
Program
CounterPC

Wake from Interrupt Event
Note 1:

PC + 2PC + 4

PC + 6

OSTS bit Set

TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.

© 2007 Microchip Technology Inc.

Preliminary

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PIC18F2455/2550/4455/4550
25.4

Fail-Safe Clock Monitor

The Fail-Safe Clock Monitor (FSCM) allows the
microcontroller to continue operation in the event of an
external oscillator failure by automatically switching thedevice clock to the internal oscillator block. The FSCM
function is enabled by setting the FCMEN Configuration
bit.
When FSCM is enabled, the INTRC oscillator runs at
all times to monitor clocks to peripherals and provide abackup clock in the event of a clock failure. Clockmonitoring (shown in Figure 25-3) is accomplished bycreating a sample clock signal, which is the INTRC output divided by 64. This allows ample time between
FSCM sample clocks for a peripheral clock edge tooccur. The peripheral device clock and the sample
clock are presented as inputs to the Clock Monitor latch(CM). The CM is set on the falling edge of the device
clock source, but cleared on the rising edge of thesample clock.

FIGURE 25-3:

FSCM BLOCK DIAGRAM
Clock Monitor
Latch (CM)(edge-triggered)

Peripheral
Clock

INTRC
Source(32 μs)

÷ 64

S

Q

C

Q

To use a higher clock speed on wake-up, the INTOSC
or postscaler clock sources can be selected to provide
a higher clock speed by setting bits IRCF2:IRCF0
immediately after Reset. For wake-ups from Sleep, the
INTOSC or postscaler clock sources can be selectedby setting IRCF2:IRCF0 prior to entering Sleep mode.
The FSCM will detect failures of the primary or secondary clock sources only. If the internal oscillator block
fails, no failure would be detected, nor would any action
be possible.

25.4.1

Both the FSCM and the WDT are clocked by the
INTRC oscillator. Since the WDT operates with aseparate divider and counter, disabling the WDT has
no effect on the operation of the INTRC oscillator when
the FSCM is enabled.
As already noted, the clock source is switched to the
INTOSC clock when a clock failure is detected.
Depending on the frequency selected by the
IRCF2:IRCF0 bits, this may mean a substantial change
in the speed of code execution. If the WDT is enabledwith a small prescale value, a decrease in clock speed
allows a WDT time-out to occur and a subsequent
device Reset. For this reason, Fail-Safe Clock Monitor
events also reset the WDT and postscaler, allowing it tostart timing from when execution speed was changed
and decreasing the likelihood of an erroneous time-out.

25.4.2488 Hz(2.048 ms)
Clock
FailureDetected

Clock failure is tested for on the falling edge of thesample clock. If a sample clock falling edge occurs
while CM is still set, a clock failure has been detected(Figure 25-4). This causes the following:• the FSCM generates an oscillator fail interrupt by
setting bit, OSCFIF (PIR2<7>);• the device clock source is switched to the internal
oscillator block (OSCCON is not updated to show
the current clock source – this is the fail-safecondition); and• the WDT is reset.

FSCM AND THE WATCHDOG TIMEREXITING FAIL-SAFE OPERATION

The fail-safe condition is terminated by either a device
Reset or by entering a power-managed mode. On
Reset, the controller starts the primary clock source
specified in Configuration Register 1H (with any
start-up delays that are required for the oscillator mode,such as OST or PLL timer). The INTOSC multiplexer
provides the device clock until the primary clock source
becomes ready (similar to a Two-Speed Start-up). The
clock source is then switched to the primary clock(indicated by the OSTS bit in the OSCCON registerbecoming set). The Fail-Safe Clock Monitor thenresumes monitoring the peripheral clock.
The primary clock source may never become readyduring start-up. In this case, operation is clocked by the
INTOSC multiplexer. The OSCCON register will remain
in its Reset state until a power-managed mode isentered.

During switchover, the postscaler frequency from theinternal oscillator block may not be sufficiently stable fortiming sensitive applications. In these cases, it may bedesirable to select another clock configuration and enteran alternate power-managed mode. This can be done toattempt a partial recovery or execute a controlled shutdown. See Section 3.1.4 “Multiple Sleep Commands”
and Section 25.3.1 “Special Considerations for
Using Two-Speed Start-up” for more details.

DS39632D-page 300

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
FIGURE 25-4:

FSCM TIMING DIAGRAM

Sample Clock
Oscillator
FailureDeviceClock
OutputCM Output(Q)

FailureDetected
OSCFIFCM TestNote:

25.4.3

CM TestCM TestThe device clock is normally at a much higher frequency than the sample clock. The relative frequencies in thisexample have been chosen for clarity.

25.4.4

FSCM INTERRUPTS IN
POWER-MANAGED MODES

By entering a power-managed mode, the clock
multiplexer selects the clock source selected by the
OSCCON register. Fail-Safe Clock Monitoring of thepower-managed clock source resumes in the
power-managed mode.
If an oscillator failure occurs during power-managed
operation, the subsequent events depend on whether
or not the oscillator failure interrupt is enabled. If
enabled (OSCFIF = 1), code execution will be clocked
by the INTOSC multiplexer. An automatic transition
back to the failed clock source will not occur.
If the interrupt is disabled, subsequent interrupts while
in Idle mode will cause the CPU to begin executing
instructions while being clocked by the INTOSC
source.

POR OR WAKE-UP FROM SLEEPThe FSCM is designed to detect oscillator failure at any
point after the device has exited Power-on Reset(POR) or Low-Power Sleep mode. When the primarydevice clock is either EC or INTRC, monitoring canbegin immediately following these events.
For oscillator modes involving a crystal or resonator(HS, HSPLL or XT), the situation is somewhat different.
Since the oscillator may require a start-up time considerably longer than the FCSM sample clock time, afalse clock failure may be detected. To prevent this, theinternal oscillator block is automatically configured as
the device clock and functions until the primary clock is
stable (the OST and PLL timers have timed out). Thisis identical to Two-Speed Start-up mode. Once theprimary clock is stable, the INTRC returns to its role as
the FSCM source.
Note:

The same logic that prevents false oscillator failure interrupts on POR or wake from
Sleep will also prevent the detection of theoscillator’s failure to start at all following
these events. This can be avoided bymonitoring the OSTS bit and using atiming routine to determine if the oscillator
is taking too long to start. Even so, nooscillator failure interrupt will be flagged.

As noted in Section 25.3.1 “Special Considerations
for Using Two-Speed Start-up”, it is also possible toselect another clock configuration and enter an alternate
power-managed mode while waiting for the primaryclock to become stable. When the new power-managed
mode is selected, the primary clock is disabled.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 301

PIC18F2455/2550/4455/4550
25.5

Program Verification and
Code Protection

Each of the five blocks has three code protection bits
associated with them. They are:

The overall structure of the code protection on the
PIC18 Flash devices differs significantly from other
PIC® devices.

• Code-Protect bit (CPn)• Write-Protect bit (WRTn)• External Block Table Read bit (EBTRn)

The user program memory is divided into five blocks.
One of these is a boot block of 2 Kbytes. The remainderof the memory is divided into four blocks on binary
boundaries.

Figure 25-5 shows the program memory organizationfor 24 and 32-Kbyte devices and the specific code
protection bit associated with each block. The actual
locations of the bits are summarized in Table 25-3.

FIGURE 25-5:

CODE-PROTECTED PROGRAM MEMORY FOR PIC18F2455/2550/4455/4550
MEMORY SIZE/DEVICE

24 Kbytes(PIC18F2455/2555)

32 Kbytes(PIC18F2550/4550)

Address
Range

Boot Block

Boot Block

000000h
0007FFh

Block 0Block 0Block Code Protection
Controlled By:

CPB, WRTB, EBTRB

000800h
CP0, WRT0, EBTR0001FFFh
002000h
Block 1

Block 1

CP1, WRT1, EBTR1
003FFFh
004000h

Block 2Block 2CP2, WRT2, EBTR2
005FFFh
006000h

Unimplemented
Read ‘0’s

CP3, WRT3, EBTR3

Block 3
007FFFh
008000h

Unimplemented
Read ‘0’s

Unimplemented
Read ‘0’s(Unimplemented Memory Space)

1FFFFFhTABLE 25-3:

SUMMARY OF CODE PROTECTION REGISTERS

File Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

300008h

CONFIG5L

—

—

—

—

CP3(1)

CP2

CP1

CP0

300009h

CONFIG5H

CPD

CPB

—

—

—

—

—

—

WRT2

WRT1

WRT0

—

—

—

EBTR2

EBTR1

EBTR0

—

—

—

30000AhCONFIG6L

—

—

—

—

WRT3(1)30000Bh

CONFIG6H

WRTD

WRTB

WRTC

—

—

30000Ch

CONFIG7L

—

—

—

—

EBTR3

30000Dh

CONFIG7H

—

EBTRB

—

—

—

(1)

Legend: Shaded cells are unimplemented.
Note 1: Unimplemented in PIC18FX455 devices; maintain this bit set.

DS39632D-page 302

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
25.5.1PROGRAM MEMORYCODE PROTECTION

The program memory may be read to or written fromany location using the table read and table write
instructions. The device ID may be read with table
reads. The Configuration registers may be read andwritten with the table read and table write instructions.

A table read instruction that executes from a location
outside of that block is not allowed to read and will
result in reading ‘0’s. Figures 25-6 through 25-8
illustrate table write and table read protection.
Note:

In normal execution mode, the CPn bits have no direct
effect. CPn bits inhibit external reads and writes. A
block of user memory may be protected from table
writes if the WRTn Configuration bit is ‘0’. The EBTRn
bits control table reads. For a block of user memory
with the EBTRn bit set to ‘0’, a table read instructionthat executes from within that block is allowed to read.

FIGURE 25-6:

Code protection bits may only be written toa ‘0’ from a ‘1’ state. It is not possible towrite a ‘1’ to a bit in the ‘0’ state. Codeprotection bits are only set to ‘1’ by a full
Chip Erase or Block Erase function. The
full Chip Erase and Block Erase functions
can only be initiated via ICSP operation or
an external programmer.

TABLE WRITE (WRTn) DISALLOWEDRegister Values

Program Memory

Configuration Bit Settings
000000h
0007FFh
000800h

TBLPTR = 0008FFh
PC = 001FFEh

WRTB, EBTRB = 11

WRT0, EBTR0 = 01
TBLWT*

001FFFh
002000h
WRT1, EBTR1 = 11003FFFh
004000h

PC = 005FFEh

WRT2, EBTR2 = 11

TBLWT*
005FFFh
006000h

WRT3, EBTR3 = 11
007FFFhResults: All table writes disabled to Blockn whenever WRTn = 0.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 303

PIC18F2455/2550/4455/4550
FIGURE 25-7:

EXTERNAL BLOCK TABLE READ (EBTRn) DISALLOWEDRegister Values

Program Memory

Configuration Bit Settings
000000h
0007FFh
000800h

WRTB, EBTRB = 11

WRT0, EBTR0 = 10

TBLPTR = 0008FFh
001FFFh
002000h

WRT1, EBTR1 = 11
PC = 003FFEh

TBLRD*

003FFFh
004000h
WRT2, EBTR2 = 11005FFFh
006000h
WRT3, EBTR3 = 11
007FFFhResults: All table reads from external blocks to Blockn are disabled whenever EBTRn = 0.
TABLAT register returns a value of ‘0’.

FIGURE 25-8:

EXTERNAL BLOCK TABLE READ (EBTRn) ALLOWEDRegister Values

Program Memory

Configuration Bit Settings
000000h

WRTB, EBTRB = 110007FFh
000800h

TBLPTR = 0008FFh

WRT0, EBTR0 = 10
PC = 001FFEh

TBLRD*

001FFFh
002000h
WRT1, EBTR1 = 11003FFFh
004000h
WRT2, EBTR2 = 11005FFFh
006000h
WRT3, EBTR3 = 11
007FFFhResults: Table reads permitted within Blockn, even when EBTRBn = 0.
TABLAT register returns the value of the data at the location TBLPTR.

DS39632D-page 304

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
25.5.2DATA EEPROM
CODE PROTECTION

The entire data EEPROM is protected from external
reads and writes by two bits: CPD and WRTD. CPD
inhibits external reads and writes of data EEPROM.
WRTD inhibits internal and external writes to data
EEPROM. The CPU can continue to read and write
data EEPROM regardless of the protection bit settings.

25.5.3

CONFIGURATION REGISTERPROTECTION

The Configuration registers can be write-protected.
The WRTC bit controls protection of the Configuration
registers. In normal execution mode, the WRTC bit isreadable only. WRTC can only be written via ICSP
operation or an external programmer.

25.6

ID Locations

Eight memory locations (200000h-200007h) aredesignated as ID locations, where the user can store
checksum or other code identification numbers. These
locations are both readable and writable during normal
execution through the TBLRD and TBLWT instructions
or during program/verify. The ID locations can be readwhen the device is code-protected.

25.7

In-Circuit Serial Programming

PIC18F2455/2550/4455/4550 microcontrollers can beserially programmed while in the end application circuit.
This is simply done with two lines for clock and data
and three other lines for power, ground and theprogramming voltage. This allows customers to manufacture boards with unprogrammed devices and thenprogram the microcontroller just before shipping the
product. This also allows the most recent firmware or acustom firmware to be programmed.

To use the In-Circuit Debugger function of the microcontroller, the design must implement In-Circuit Serial
Programming connections to MCLR/VPP/RE3, VDD,
VSS, RB7 and RB6. This will interface to the In-Circuit
Debugger module available from Microchip or one of
the third party development tool companies.

25.9

Special ICPORT Features(Designated Packages Only)

Under specific circumstances, the No Connect (NC)pins of PIC18F4455/4550 devices in 44-pin TQFP
packages can provide additional functionality. Thesefeatures are controlled by device Configuration bits andare available only in this package type and pin count.

25.9.1

DEDICATED ICD/ICSP PORTThe 44-pin TQFP devices can use NC pins to provide
an alternate port for In-Circuit Debugging (ICD) andIn-Circuit Serial Programming (ICSP). These pins arecollectively known as the dedicated ICSP/ICD port,
since they are not shared with any other function of thedevice.
When implemented, the dedicated port activates three
NC pins to provide an alternate device Reset, data andclock ports. None of these ports overlap with standard
I/O pins, making the I/O pins available to the user’s
application.
The dedicated ICSP/ICD port is enabled by setting the
ICPRT Configuration bit. The port functions the same
way as the legacy ICSP/ICD port on RB6/RB7.
Table 25-5 identifies the functionally equivalent pins for
ICSP and ICD purposes.

TABLE 25-5:

EQUIVALENT PINS FORLEGACY AND DEDICATED
ICD/ICSP™ PORTS

Pin Name

25.8

In-Circuit Debugger

When the DEBUG Configuration bit is programmed toa ‘0’, the In-Circuit Debugger functionality is enabled.
This function allows simple debugging functions whenused with MPLAB® IDE. When the microcontroller has
this feature enabled, some resources are not available
for general use. Table 25-4 shows which resources are
required by the background debugger.

TABLE 25-4:

DEBUGGER RESOURCES

I/O pins:

RB6, RB7

Stack:

2 levels

Program Memory:

512 bytes

Data Memory:

10 bytes© 2007 Microchip Technology Inc.

Pin
Type

Pin Function

LegacyPort

DedicatedPort

MCLR/VPP/
RE3

NC/ICRST/
ICVPP

PDevice Reset andProgramming
EnableRB6/KBI2/
PGC

NC/ICCK/ICPGC

I

Serial Clock

RB7/KBI3/
PGD

NC/ICDT/
ICPGD

I/O

Serial Data

Legend:Preliminary

I = Input, O = Output, P = PowerDS39632D-page 305

PIC18F2455/2550/4455/4550
Even when the dedicated port is enabled, the ICSP and
ICD functions remain available through the legacy port.
When VIH is seen on the MCLR/VPP/RE3 pin, the stateof the ICRST/ICVPP pin is ignored.

Note 1: High-Voltage Programming is always
available, regardless of the state of the
LVP bit, by applying VIHH to the MCLR pin.
2: While in Low-Voltage ICSP Programming
mode, the RB5 pin can no longer be used
as a general purpose I/O pin and shouldbe held low during normal operation.

Note 1: The ICPRT Configuration bit can only be
programmed through the default ICSP
port.
2: The ICPRT Configuration bit must be
maintained clear for all 28-pin and 40-pin
devices; otherwise, unexpected operation
may occur.

25.9.2

3: When using Low-Voltage ICSP Programming (LVP) and the pull-ups on PORTB
are enabled, bit 5 in the TRISB registermust be cleared to disable the pull-up on
RB5 and ensure the proper operation of
the device.

28-PIN EMULATION

PIC18F4455/4550 devices in 44-pin TQFP packages
also have the ability to change their configuration under
external control for debugging purposes. This allows
the device to behave as if it were a PIC18F2455/2550
28-pin device.
This 28-pin Configuration mode is controlled through asingle pin, NC/ICPORTS. Connecting this pin to VSS
forces the device to function as a 28-pin device.
Features normally associated with the 40/44-pin
devices are disabled along with their corresponding
control registers and bits. This includes PORTD and
PORTE, the SPP and the Enhanced PWM functionalityof CCP1. On the other hand, connecting the pin to VDD
forces the device to function in its default configuration.
The configuration option is only available when background debugging and the dedicated ICD/ICSP port
are both enabled (DEBUG Configuration bit is clear
and ICPRT Configuration bit is set). When disabled,
NC/ICPORTS is a No Connect pin.

25.10 Single-Supply ICSP Programming
The LVP Configuration bit enables Single-Supply ICSP
Programming (formerly known as Low-Voltage ICSP
Programming or LVP). When Single-Supply Programming is enabled, the microcontroller can be
programmed without requiring high voltage being
applied to the MCLR/VPP/RE3 pin, but theRB5/KBI1/PGM pin is then dedicated to controlling
Program mode entry and is not available as a general
purpose I/O pin.

4: If the device Master Clear is disabled,verify that either of the following is done toensure proper entry into ICSP mode:a) disable Low-Voltage Programming(CONFIG4L<2> = 0); orb) make certain that RB5/KBI1/PGM
is held low during entry into ICSP.
If Single-Supply ICSP Programming mode will not be
used, the LVP bit can be cleared. RB5/KBI1/PGM thenbecomes available as the digital I/O pin, RB5. The LVP
bit may be set or cleared only when using standard
high-voltage programming (VIHH applied to the
MCLR/VPP/RE3 pin). Once LVP has been disabled,
only the standard high-voltage programming isavailable and must be used to program the device.
Memory that is not code-protected can be erased using
either a Block Erase, or erased row by row, then written
at any specified VDD. If code-protected memory is to beerased, a Block Erase is required. If a Block Erase is tobe performed when using Low-Voltage Programming,the device must be supplied with VDD of 4.5V to 5.5V.

While programming using Single-Supply Programming, VDD is applied to the MCLR/VPP/RE3 pin as innormal execution mode. To enter Programming mode,
VDD is applied to the PGM pin.

DS39632D-page 306

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
26.0

INSTRUCTION SET SUMMARY

PIC18F2455/2550/4455/4550 devices incorporate thestandard set of 75 PIC18 core instructions, as well as
an extended set of eight new instructions for the
optimization of code that is recursive or that utilizes asoftware stack. The extended set is discussed later inthis section.

26.1

Standard Instruction Set

The standard PIC18 instruction set adds many
enhancements to the previous PIC instruction sets,
while maintaining an easy migration from these PIC
instruction sets. Most instructions are a single program
memory word (16 bits) but there are four instructions
that require two program memory locations.
Each single-word instruction is a 16-bit word divided
into an opcode, which specifies the instruction type andone or more operands, which further specify theoperation of the instruction.
The instruction set is highly orthogonal and is grouped
into four basic categories:• Byte-oriented operations• Bit-oriented operations• Literal operations• Control operations
The PIC18 instruction set summary in Table 26-2 lists
byte-oriented, bit-oriented, literal and control
operations. Table 26-1 shows the opcode field
descriptions.
Most byte-oriented instructions have three operands:
1.
2.
3.

The file register (specified by ‘f’)
The destination of the result (specified by ‘d’)
The accessed memory (specified by ‘a’)

The file register designator ‘f’ specifies which fileregister is to be used by the instruction. The destination
designator ‘d’ specifies where the result of the operation is to be placed. If ‘d’ is zero, the result is placed in
the WREG register. If ‘d’ is one, the result is placed in
the file register specified in the instruction.

• A literal value to be loaded into a file register(specified by ‘k’)
• The desired FSR register to load the literal value
into (specified by ‘f’)
• No operand required(specified by ‘—’)The control instructions may use some of the following
operands:• A program memory address (specified by ‘n’)
• The mode of the CALL or RETURN instructions(specified by ‘s’)
• The mode of the table read and table write
instructions (specified by ‘m’)
• No operand required(specified by ‘—’)All instructions are a single word, except for four
double-word instructions. These instructions weremade double-word to contain the required informationin 32 bits. In the second word, the 4 MSbs are ‘1’s. If
this second word is executed as an instruction (byitself), it will execute as a NOP.
All single-word instructions are executed in a single
instruction cycle, unless a conditional test is true or the
program counter is changed as a result of the instruction. In these cases, the execution takes two instruction
cycles with the additional instruction cycle(s) executed
as a NOP.
The double-word instructions execute in two instruction
cycles.
One instruction cycle consists of four oscillator periods.
Thus, for an oscillator frequency of 4 MHz, the normal
instruction execution time is 1 μs. If a conditional test istrue, or the program counter is changed as a result of
an instruction, the instruction execution time is 2 μs.
Two-word branch instructions (if true) would take 3 μs.
Figure 26-1 shows the general formats that the instructions can have. All examples use the convention ‘nnh’
to represent a hexadecimal number.
The Instruction Set Summary, shown in Table 26-2,
lists the standard instructions recognized by theMicrochip MPASMTM Assembler.

All bit-oriented instructions have three operands:
1.
2.
3.

The literal instructions may use some of the following
operands:

The file register (specified by ‘f’)
The bit in the file register (specified by ‘b’)
The accessed memory (specified by ‘a’)Section 26.1.1 “Standard Instruction Set” provides
a description of each instruction.

The bit field designator ‘b’ selects the number of the bit
affected by the operation, while the file register
designator ‘f’ represents the number of the file in which
the bit is located.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 307

PIC18F2455/2550/4455/4550
TABLE 26-1:

OPCODE FIELD DESCRIPTIONS

Field

Descriptiona

RAM access bit
a = 0: RAM location in Access RAM (BSR register is ignored)
a = 1: RAM bank is specified by BSR registerbbb

Bit address within an 8-bit file register (0 to 7).

BSR

Bank Select Register. Used to select the current RAM bank.

C, DC, Z, OV, N

ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative.

dDestination select bit
d = 0: store result in WREG
d = 1: store result in file register f

dest

Destination: either the WREG register or the specified register file location.

f

8-bit register file address (00h to FFh) or 2-bit FSR designator (0h to 3h).

fs

12-bit register file address (000h to FFFh). This is the source address.

fd

12-bit register file address (000h to FFFh). This is the destination address.

GIE

Global Interrupt Enable bit.

k

Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value).

label

Label name.

mm

The mode of the TBLPTR register for the table read and table write instructions.
Only used with table read and table write instructions:*

No change to register (such as TBLPTR with table reads and writes)*+

Post-Increment register (such as TBLPTR with table reads and writes)*-

Post-Decrement register (such as TBLPTR with table reads and writes)
Pre-Increment register (such as TBLPTR with table reads and writes)+*n

The relative address (2’s complement number) for relative branch instructions or the direct address for
Call/Branch and Return instructions.

PC

Program Counter.

PCL

Program Counter Low Byte.

PCH

Program Counter High Byte.

PCLATH

Program Counter High Byte Latch.

PCLATU

Program Counter Upper Byte Latch.

PD

Power-Down bit.

PRODH

Product of Multiply High Byte.

PRODL

Product of Multiply Low Byte.

sFast Call/Return mode select bit
s = 0: do not update into/from shadow registers
s = 1: certain registers loaded into/from shadow registers (Fast mode)

TBLPTR

21-bit Table Pointer (points to a program memory location).

TABLAT

8-bit Table Latch.

TO

Time-out bit.

TOS

Top-of-Stack.

u

Unused or unchanged.

WDT

Watchdog Timer.

WREG

Working register (accumulator).

x

Don’t care (‘0’ or ‘1’). The assembler will generate code with x = 0. It is the recommended form of use forcompatibility with all Microchip software tools.

zs

7-bit offset value for indirect addressing of register files (source).
7-bit offset value for indirect addressing of register files (destination).

zd
{

}

Optional argument.

[text]

Indicates an indexed address.

(text)

The contents of text.

[expr]<n>Specifies bit n of the register indicated by the pointer expr.

→

Assigned to.

< >Register bit field.

∈

In the set of.

italics

User-defined term (font is Courier).

DS39632D-page 308

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
FIGURE 26-1:

GENERAL FORMAT FOR INSTRUCTIONS
Byte-oriented file register operations
15

10
OPCODE

9

8 7

d

a

Example Instruction
0
ADDWF MYREG, W, B

f (FILE #)d = 0 for result destination to be WREG registerd = 1 for result destination to be file register (f)a = 0 to force Access Banka = 1 for BSR to select bankf = 8-bit file register address
Byte to Byte move operations (2-word)
15

12 11

0

OPCODE
15

f (Source FILE #)12 11

MOVFF MYREG1, MYREG20f (Destination FILE #)1111

f = 12-bit file register address
Bit-oriented file register operations
15

12 11

9 8 7

0

OPCODE b (BIT #) af (FILE #)BSF MYREG, bit, B

b = 3-bit position of bit in file register (f)a = 0 to force Access Banka = 1 for BSR to select bankf = 8-bit file register address
Literal operations
15

8

7

0

OPCODEMOVLW 7Fhk (literal)k = 8-bit immediate value
Control operations
CALL, GOTO and Branch operations
15

8 7

0

OPCODE
15

GOTO Labeln<7:0> (literal)

12 11

0
n<19:8> (literal)1111

n = 20-bit immediate value
15

8 7
S

OPCODE
15

0
CALL MYFUNC

n<7:0> (literal)

12 11

0
n<19:8> (literal)1111
S = Fast bit
15

11 10
OPCODE

15

0

8 7
OPCODE© 2007 Microchip Technology Inc.

BRA MYFUNC

n<10:0> (literal)0n<7:0> (literal)

Preliminary

BC MYFUNC

DS39632D-page 309

PIC18F2455/2550/4455/4550
TABLE 26-2:

PIC18FXXXX INSTRUCTION SET

Mnemonic,
Operands

16-Bit Instruction Word
Description

CyclesMSb

LSb

StatusAffected

Notes

BYTE-ORIENTED OPERATIONSADDWFADDWFC
ANDWF
CLRF
COMF
CPFSEQCPFSGTCPFSLT
DECF
DECFSZDCFSNZ
INCF
INCFSZINFSNZ
IORWF
MOVF
MOVFF

f, d, af, d, af, d, af, af, d, a
f, a
f, a
f, a
f, d, af, d, af, d, af, d, af, d, af, d, af, d, af, d, afs, fd

MOVWF
MULWF
NEGF
RLCF
RLNCF
RRCF
RRNCF
SETF
SUBFWB

f, a
f, a
f, a
f, d, af, d, af, d, af, d, af, af, d, aSUBWF
SUBWFBf, d, af, d, aSWAPF
TSTFSZ
XORWF

f, d, af, af, d, aNote 1:

When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be thatvalue present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as an input and isdriven low by an external device, the data will be written back with a ‘0’.
If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if
assigned.
If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The
second cycle is executed as a NOP.
Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP
unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all
program memory locations have a valid instruction.

2:
3:
4:

DS39632D-page 310

Add WREG and f
Add WREG and Carry bit to f
AND WREG with f
Clear fComplement f
Compare f with WREG, skip =Compare f with WREG, skip >Compare f with WREG, skip <Decrement f
Decrement f, Skip if 0
Decrement f, Skip if Not 0
Increment f
Increment f, Skip if 0
Increment f, Skip if Not 0
Inclusive OR WREG with f
Move fMove fs (source) to 1st word
fd (destination) 2nd word
Move WREG to f
Multiply WREG with f
Negate f
Rotate Left f through Carry
Rotate Left f (No Carry)
Rotate Right f through Carry
Rotate Right f (No Carry)
Set f
Subtract f from WREG withborrow
Subtract WREG from f
Subtract WREG from f withborrow
Swap nibbles in f
Test f, skip if 0
Exclusive OR WREG with f

1
1
1
1
1
1 (2 or 3)
1 (2 or 3)
1 (2 or 3)
1
1 (2 or 3)
1 (2 or 3)
1
1 (2 or 3)
1 (2 or 3)
1
1
2

C, DC, Z, OV, N
C, DC, Z, OV, N
Z, N
Z
Z, N
None
None
None
C, DC, Z, OV, N
None
None
C, DC, Z, OV, N
None
None
Z, N
Z, N
None

1, 2
1, 2
1,2
2
1, 2
4
4
1, 2
1, 2, 3, 4
1, 2, 3, 4
1, 2
1, 2, 3, 4
4
1, 2
1, 2
1

1
1
1
1
1
1
1
1
1

0010
0010
0001
0110
0001
0110
0110
0110
0000
0010
0100
0010
0011
0100
0001
0101
1100
1111
0110
0000
0110
0011
0100
0011
0100
0110
0101

01da
00da
01da
101a
11da
001a
010a
000a
01da
11da
11da
10da
11da
10da
00da
00da
ffff
ffff
111a
001a
110a
01da
01da
00da
00da
100a
01da

ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff

ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff

1
1

0101
0101

11da
10da

ffff
ffff

ffff C, DC, Z, OV, N
ffff C, DC, Z, OV, N

1, 2

0011
1
1 (2 or 3) 0110
0001
1

10da
011a
10da

ffff
ffff
ffff

ffff None
ffff None
ffff Z, N

4
1, 2

Preliminary

None
None
C, DC, Z, OV, N
C, Z, N
Z, N
C, Z, N
Z, N
None
C, DC, Z, OV, N

1, 2
1, 2

1, 2

© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
TABLE 26-2:

PIC18FXXXX INSTRUCTION SET (CONTINUED)
16-Bit Instruction Word

Mnemonic,
Operands

Description

CyclesMSb

LSb

StatusAffected

Notes

BIT-ORIENTED OPERATIONS
BCF
BSF
BTFSC
BTFSS
BTG

f, b, af, b, af, b, af, b, af, d, aBit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
Bit Toggle f

1
1
1 (2 or 3)
1 (2 or 3)
1

1001
1000
1011
1010
0111

bbba
bbba
bbba
bbba
bbba

ffff
ffff
ffff
ffff
ffff

ffff
ffff
ffff
ffff
ffff

None
None
None
None
None

1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
2
1 (2)
2

0010
0110
0011
0111
0101
0001
0100
0nnn
0000
110s
kkkk
0000
0000
1111
kkkk
0000
xxxx
0000
0000
1nnn
0000
0000

nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
kkkk
kkkk
0000
0000
kkkk
kkkk
0000
xxxx
0000
0000
nnnn
1111
0001

nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
kkkk
kkkk
0100
0111
kkkk
kkkk
0000
xxxx
0110
0101
nnnn
1111
000s

None
None
None
None
None
None
None
None
None
None

1
1
1
1
2
1
2

1110
1110
1110
1110
1110
1110
1110
1101
1110
1110
1111
0000
0000
1110
1111
0000
1111
0000
0000
1101
0000
0000

2
2
1

0000
0000
0000

1100
0000
0000

kkkk
0001
0000

1, 2
1, 2
3, 4
3, 4
1, 2

CONTROL OPERATIONS
BC
BN
BNC
BNN
BNOV
BNZ
BOV
BRA
BZ
CALL

n
n
n
n
n
n
n
n
n
n, s

CLRWDT
DAW
GOTO

—
—
n

NOP
NOP
POP
PUSH
RCALL
RESET
RETFIE

—
—
—
—
n
s

Branch if Carry
Branch if Negative
Branch if Not Carry
Branch if Not Negative
Branch if Not Overflow
Branch if Not Zero
Branch if Overflow
Branch UnconditionallyBranch if Zero
Call subroutine 1st word
2nd word
Clear Watchdog Timer
Decimal Adjust WREG
Go to address 1st word
2nd word
No Operation
No Operation
Pop top of return stack (TOS)Push top of return stack (TOS)
Relative Call
Software device Reset
Return from interrupt enable

RETLW
RETURN
SLEEP

k
s
—

Return with literal in WREG
Return from Subroutine
Go into Standby mode

Note 1:

When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be thatvalue present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as an input and isdriven low by an external device, the data will be written back with a ‘0’.
If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if
assigned.
If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The
second cycle is executed as a NOP.
Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP
unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all
program memory locations have a valid instruction.

2:
3:
4:

© 2007 Microchip Technology Inc.

1
1
2

Preliminary

TO, PD
C
None

None
None
None
None
None
All
GIE/GIEH,
PEIE/GIEL
kkkk None001s None0011 TO, PD

4

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PIC18F2455/2550/4455/4550
TABLE 26-2:

PIC18FXXXX INSTRUCTION SET (CONTINUED)
16-Bit Instruction Word

Mnemonic,
Operands

Description

CyclesMSb

LSb

StatusAffected

Notes

LITERAL OPERATIONS
ADDLW
ANDLW
IORLW
LFSR

k
k
k
f, k

MOVLB
MOVLW
MULLW
RETLW
SUBLW
XORLW

k
k
k
k
k
k

Add literal and WREG
1
AND literal with WREG
1
Inclusive OR literal with WREG 1
Move literal (12-bit) 2nd word2
to FSR(f)1st wordMove literal to BSR<3:0>
1
Move literal to WREG
1
Multiply literal with WREG
1Return with literal in WREG
2
Subtract WREG from literal
1
Exclusive OR literal with WREG 1

0000
0000
0000
1110
1111
0000
0000
0000
0000
0000
0000

1111
1011
1001
1110
0000
0001
1110
1101
1100
1000
1010

kkkk
kkkk
kkkk
00ff
kkkk
0000
kkkk
kkkk
kkkk
kkkk
kkkk

kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk

C, DC, Z, OV, N
Z, N
Z, N
None

0000
0000
0000
0000
0000
0000
0000
0000

0000
0000
0000
0000
0000
0000
0000
0000

0000
0000
0000
0000
0000
0000
0000
0000

1000
1001
1010
1011
1100
1101
1110
1111

None
None
None
None
None
None
None
None

None
None
None
None
C, DC, Z, OV, N
Z, NDATA MEMORY ↔ PROGRAM MEMORY OPERATIONSTBLRD*
TBLRD*+
TBLRD*TBLRD+*
TBLWT*
TBLWT*+
TBLWT*TBLWT+*
Note 1:

2:
3:
4:

Table Read
2
Table Read with post-increment
Table Read with post-decrement
Table Read with pre-increment
Table Write
2
Table Write with post-increment
Table Write with post-decrement
Table Write with pre-increment

When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be thatvalue present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as an input and isdriven low by an external device, the data will be written back with a ‘0’.
If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if
assigned.
If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The
second cycle is executed as a NOP.
Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP
unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all
program memory locations have a valid instruction.

DS39632D-page 312

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
26.1.1

STANDARD INSTRUCTION SET

ADDLW

ADD Literal to W

ADDWF

Syntax:ADDLW

Syntax:ADDWF

Operands:

0 ≤ k ≤ 255

Operands:

Operation:(W) + k → W

Status Affected:

N, OV, C, DC, Z

0 ≤ f ≤ 255
d ∈ [0,1]a ∈ [0,1]

Operation:(W) + (f) → dest

Status Affected:

N, OV, C, DC, Z

Encoding:

0000

Description:

k

1111

kkkk

kkkk

The contents of W are added to the
8-bit literal ‘k’ and the result is placed inW.

Words:

1

Cycles:1

ADD W to f

Encoding:

0010

Q1

Q2

Q3

Q4

Read
literal ‘k’

Process
Data

Write to W

Example:

ADDLW

ffff

ffff

Add W to register ‘f’. If ‘d’ is ‘0’, theresult is stored in W. If ‘d’ is ‘1’, theresult is stored back in register ‘f’(default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented andBit-Oriented Instructions in Indexed
Literal Offset Mode” for details.

Words:

1

Cycles:1

15h

Before InstructionW= 10h
After Instruction
W =
25h

01da

Description:

Q Cycle Activity:
Decodef {,d {,a}}Q Cycle Activity:
Q1

Q2

Q3

Q4

DecodeReadregister ‘f’

Process
Data

Write todestination

ADDWF

REG, 0, 0

Example:Before Instruction

Note:

W
=
REG
=
After Instruction

17h
0C2h

W
REG

0D9h
0C2h

=
=

All PIC18 instructions may take an optional label argument, preceding the instruction mnemonic, for use insymbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s).

© 2007 Microchip Technology Inc.

Preliminary

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PIC18F2455/2550/4455/4550
ADDWFCADD W and Carry bit to f

ANDLW

AND Literal with W

Syntax:ADDWFC

Syntax:

ANDLW

Operands:

0 ≤ f ≤ 255
d ∈ [0,1]a ∈ [0,1]

f {,d {,a}}(W) + (f) + (C) → dest

Operation:
Status Affected:
Encoding:

0010

Description:

00da

ffff

ffff

Add W, the Carry flag and data memory
location ‘f’. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed in data memory location ‘f’.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented andBit-Oriented Instructions in Indexed
Literal Offset Mode” for details.

Words:

1

Cycles:1

Operands:

0 ≤ k ≤ 255

Operation:(W) .AND. k → W

Status Affected:

N, Z

Encoding:

N, OV, C, DC, Z

k

0000

1011

kkkk

kkkk

Description:

The contents of W are ANDed with the
8-bit literal ‘k’. The result is placed in W.

Words:

1

Cycles:1

Q Cycle Activity:
Q1

Q2

Q3

Q4

DecodeRead literal‘k’

Process
Data

Write to W

Example:ANDLW

Before Instruction
W=
After Instruction
W
=

05Fh

A3h
03h

Q Cycle Activity:
Q1

Q2

Q3

Q4

DecodeReadregister ‘f’

Process
Data

Write todestination

ADDWFC

REG, 0, 1

Example:Before Instruction
Carry bit =
REG
=
W
=
After Instruction
Carry bit =
REG
=
W
=

DS39632D-page 314

1
02h
4Dh
0
02h
50h

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
ANDWF

AND W with fBCBranch if Carry

Syntax:

ANDWF

Syntax:BC

Operands:

0 ≤ f ≤ 255
d ∈ [0,1]a ∈ [0,1]

f {,d {,a}}Operation:(W) .AND. (f) → dest

Status Affected:

N, Z

Encoding:

0001

Description:

ffff

ffff

The contents of W are ANDed withregister ‘f’. If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored backin register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented andBit-Oriented Instructions in Indexed
Literal Offset Mode” for details.

Words:

1

Cycles:1

Operands:-128 ≤ n ≤ 127

Operation:

if Carry bit is ‘1’(PC) + 2 + 2n → PC

Status Affected:

None

Encoding:
01da

Q2

Q3

Q4

DecodeReadregister ‘f’

Process
Data

Write todestination

ANDWF

REG, 0, 0

nnnn

nnnn

Words:

1

Cycles:1(2)Q Cycle Activity:
If Jump:
Q1

Q2

Q3

Q4

DecodeRead literal‘n’

Process
Data

Write to PC

No
operationNo
operationNo
operationNo
operation

Q1

Q2

Q3

Q4

DecodeRead literal‘n’

Process
Data

No
operation

Example:HERE

Before Instruction
PC
After Instruction
If CarryPC
If Carry
PC

17h
C2h
02h
C2h

© 2007 Microchip Technology Inc.

0010

If the Carry bit is ‘1’, then the program
will branch.
The 2’s complement number ‘2n’ isadded to the PC. Since the PC will haveincremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.

If No Jump:

Q1

Before Instruction
W
=
REG
=
After Instruction
W
=
REG
=

1110

Description:

Q Cycle Activity:

Example:nPreliminary

BC

5

=

address (HERE)

=
=
=
=

1;
address (HERE + 12)
0;address (HERE + 2)

DS39632D-page 315

PIC18F2455/2550/4455/4550
BCF

Bit Clear f

BNBranch if Negative

Syntax:BCF

Syntax:BN

Operands:

0 ≤ f ≤ 255
0≤b≤7a ∈ [0,1]

f, b {,a}Operation:

0 → f<b>

Status Affected:

None

Encoding:
Description:

bbba

ffff

ffff

Bit ‘b’ in register ‘f’ is cleared.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented andBit-Oriented Instructions in Indexed
Literal Offset Mode” for details.

Words:

1

Cycles:1

Operands:-128 ≤ n ≤ 127

Operation:

if Negative bit is ‘1’(PC) + 2 + 2n → PC

Status Affected:

None

Encoding:

1001

Q1

Q2

Q3

Q4

Read
register ‘f’

ProcessData

Writeregister ‘f’

Example:BCF

Before Instruction
FLAG_REG =After Instruction
FLAG_REG =FLAG_REG,

1110

nnnn

nnnn

If the Negative bit is ‘1’, then the
program will branch.
The 2’s complement number ‘2n’ isadded to the PC. Since the PC will haveincremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.

Words:

1

Cycles:1(2)Q Cycle Activity:
If Jump:
Q1

Q2

Q3

Q4

DecodeRead literal‘n’

Process
Data

Write to PC

No
operationNo
operationNo
operationNo
operation

If No Jump:

7, 0

Q1

Q2

Q3

Q4

DecodeRead literal‘n’

Process
Data

No
operation

C7h
47h

Example:HERE

Before Instruction
PC
After Instruction
If NegativePC
If NegativePC

DS39632D-page 316

0110

Description:

Q Cycle Activity:
DecodenPreliminary

BN

Jump

=

address (HERE)

=
=
=
=

1;
address (Jump)0;address (HERE + 2)

© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
BNC

Branch if Not Carry

BNN

Branch if Not Negative

Syntax:BNCnSyntax:BNN

Operands:-128 ≤ n ≤ 127

Operands:-128 ≤ n ≤ 127

Operation:

if Carry bit is ‘0’(PC) + 2 + 2n → PC

Operation:

if Negative bit is ‘0’(PC) + 2 + 2n → PC

Status Affected:

None

Status Affected:

None

Encoding:

1110

0011

nnnn

nnnn

Encoding:

n

1110

0111

nnnn

nnnn

Description:

If the Carry bit is ‘0’, then the program
will branch.
The 2’s complement number ‘2n’ isadded to the PC. Since the PC will haveincremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.

Description:

If the Negative bit is ‘0’, then the
program will branch.
The 2’s complement number ‘2n’ isadded to the PC. Since the PC will haveincremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.

Words:

1

Words:

1

Cycles:1(2)Cycles:1(2)Q Cycle Activity:
If Jump:

Q Cycle Activity:
If Jump:

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

DecodeRead literal‘n’

Process
Data

Write to PC

DecodeRead literal‘n’

Process
Data

Write to PC

No
operationNo
operationNo
operationNo
operationNo
operationNo
operationNo
operationNo
operation

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

DecodeRead literal‘n’

Process
Data

No
operation

DecodeRead literal‘n’

Process
Data

No
operation

If No Jump:

Example:If No Jump:

HERE

Before Instruction
PC
After Instruction
If CarryPC
If Carry
PC

BNC

Jump

=

address (HERE)

=
=
=
=

0;
address (Jump)1;
address (HERE + 2)

© 2007 Microchip Technology Inc.

Example:HERE

Before Instruction
PC
After Instruction
If NegativePC
If Negative
PC

Preliminary

BNN

Jump

=

address (HERE)

=
=
=
=

0;
address (Jump)1;
address (HERE + 2)

DS39632D-page 317

PIC18F2455/2550/4455/4550
BNOV

Branch if Not Overflow

BNZ

Branch if Not Zero

Syntax:BNOV

Syntax:BNZnnOperands:-128 ≤ n ≤ 127

Operands:-128 ≤ n ≤ 127

Operation:

if Overflow bit is ‘0’(PC) + 2 + 2n → PC

Operation:

if Zero bit is ‘0’(PC) + 2 + 2n → PC

Status Affected:

None

Status Affected:

None

Encoding:

1110

0101

nnnn

nnnn

Encoding:

1110

0001

nnnn

nnnn

Description:

If the Overflow bit is ‘0’, then the
program will branch.
The 2’s complement number ‘2n’ isadded to the PC. Since the PC will haveincremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.

Description:

If the Zero bit is ‘0’, then the program
will branch.
The 2’s complement number ‘2n’ isadded to the PC. Since the PC will haveincremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.

Words:

1

Words:

1

Cycles:1(2)Cycles:1(2)Q Cycle Activity:
If Jump:

Q Cycle Activity:
If Jump:

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

DecodeRead literal‘n’

Process
Data

Write to PC

DecodeRead literal‘n’

Process
Data

Write to PC

No
operationNo
operationNo
operationNo
operationNo
operationNo
operationNo
operationNo
operation

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

DecodeRead literal‘n’

Process
Data

No
operation

DecodeRead literal‘n’

Process
Data

No
operationHERE

BNOV Jump

If No Jump:

If No Jump:

Example:Before Instruction
PC
After Instruction
If Overflow
PC
If Overflow
PC

DS39632D-page 318=

address (HERE)

=
=
=
=

0;
address (Jump)1;
address (HERE + 2)

Example:HERE

Before Instruction
PC
After Instruction
If ZeroPC
If ZeroPC

Preliminary

BNZ

Jump

=

address (HERE)

=
=
=
=

0;
address (Jump)1;
address (HERE + 2)

© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
BRA

Unconditional Branch

BSF

Bit Set f

Syntax:BRAnSyntax:

BSF

Operands:-1024 ≤ n ≤ 1023

Operands:

Operation:(PC) + 2 + 2n → PC

Status Affected:

None

0 ≤ f ≤ 255
0≤b≤7a ∈ [0,1]

Operation:

1 → f<b>

Status Affected:

None

Encoding:

1101

Description:

0nnn

nnnn

nnnn

Add the 2’s complement number ‘2n’ to
the PC. Since the PC will haveincremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is a
two-cycle instruction.

Words:

1

Cycles:2

Encoding:

1000

Q1

Q2

Q3

Q4

Read literal‘n’

Process
Data

Write to PC

No
operationNo
operationNo
operationNo
operation

bbba

ffff

ffff

Description:

Bit ‘b’ in register ‘f’ is set.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented andBit-Oriented Instructions in Indexed
Literal Offset Mode” for details.

Words:

1

Cycles:1

Q Cycle Activity:
Decodef, b {,a}Q Cycle Activity:
Example:HERE

Before Instruction
PC
After Instruction
PC

BRA

Q1

Q2

Q3

Q4

DecodeReadregister ‘f’

ProcessData

Writeregister ‘f’

Jump

=

address (HERE)=

address (Jump)

Example:BSF

Before Instruction
FLAG_REG
After Instruction
FLAG_REG© 2007 Microchip Technology Inc.

Preliminary

FLAG_REG, 7, 1

=

0Ah

=

8Ah

DS39632D-page 319

PIC18F2455/2550/4455/4550
BTFSC

Bit Test File, Skip if Clear

BTFSS

Bit Test File, Skip if Set

Syntax:BTFSC f, b {,a}Syntax:BTFSS f, b {,a}Operands:

0 ≤ f ≤ 255
0≤b≤7a ∈ [0,1]

Operands:

0 ≤ f ≤ 255
0≤b<7
a ∈ [0,1]

Operation:

skip if (f<b>) = 0

Operation:

skip if (f<b>) = 1

Status Affected:

None

Status Affected:

None

Encoding:

1011

Description:

bbba

ffff

ffff

Encoding:

1010

If bit ‘b’ in register ‘f’ is ‘0’, then the next
instruction is skipped. If bit ‘b’ is ‘0’, then
the next instruction fetched during thecurrent instruction execution is discarded
and a NOP is executed instead, making
this a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected. If‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates inIndexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh).
See Section 26.2.3 “Byte-Oriented andBit-Oriented Instructions in Indexed
Literal Offset Mode” for details.

Description:

Words:

1

Words:

1

Cycles:1(2)Note: 3 cycles if skip and followed
by a 2-word instruction.

Cycles:

1(2)
Note:

Q Cycle Activity:

bbba

ffff

ffff

If bit ‘b’ in register ‘f’ is ‘1’, then the next
instruction is skipped. If bit ‘b’ is ‘1’, then
the next instruction fetched during thecurrent instruction execution is discarded
and a NOP is executed instead, making
this a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected. If‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh).
See Section 26.2.3 “Byte-Oriented andBit-Oriented Instructions in Indexed
Literal Offset Mode” for details.

3 cycles if skip and followed
by a 2-word instruction.

Q Cycle Activity:

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

DecodeReadregister ‘f’

Process
Data

No
operation

DecodeReadregister ‘f’

Process
Data

No
operation

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

No
operationNo
operationNo
operationNo
operationNo
operationNo
operationNo
operationNo
operation

If skip:

If skip:

If skip and followed by 2-word instruction:

If skip and followed by 2-word instruction:

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

No
operationNo
operationNo
operationNo
operationNo
operationNo
operationNo
operationNo
operationNo
operationNo
operationNo
operationNo
operationNo
operationNo
operationNo
operationNo
operation

Example:

HERE
FALSE
TRUE

Before Instruction
PC
After Instruction
If FLAG<1>PC
If FLAG<1>PC

DS39632D-page 320

BTFSC
:
:

FLAG, 1, 0=

address (HERE)

=
=
=
=

0;
address (TRUE)
1;
address (FALSE)

Example:

HERE
FALSE
TRUE

Before Instruction
PC
After Instruction
If FLAG<1>PC
If FLAG<1>PC

Preliminary

BTFSS
:
:

FLAG, 1, 0=

address (HERE)

=
=
=
=

0;
address (FALSE)
1;
address (TRUE)© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
BTG

Bit Toggle f

BOV

Branch if Overflow

Syntax:

BTG f, b {,a}Syntax:BOV

Operands:

0 ≤ f ≤ 255
0≤b<7
a ∈ [0,1]

Operands:-128 ≤ n ≤ 127

Operation:

if Overflow bit is ‘1’(PC) + 2 + 2n → PC

Status Affected:

None

Operation:(f<b>) → f<b>

Status Affected:

None

Encoding:

0111

Description:

Encoding:
bbba

ffff

ffff

Bit ‘b’ in data memory location ‘f’ isinverted.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented andBit-Oriented Instructions in Indexed
Literal Offset Mode” for details.

n

1110

0100

nnnn

nnnn

Description:

If the Overflow bit is ‘1’, then the
program will branch.
The 2’s complement number ‘2n’ isadded to the PC. Since the PC will haveincremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.

Words:

1

Cycles:1(2)Q Cycle Activity:
If Jump:Words:

1

Q1

Q2

Q3

Q4

Cycles:1

DecodeRead literal‘n’

Process
Data

Write to PC

No
operationNo
operationNo
operationNo
operation

Q Cycle Activity:
Q1

Q2

Q3

Q4

DecodeReadregister ‘f’

ProcessData

Writeregister ‘f’

Example:BTG

PORTC,

Q1

Q2

Q3

Q4

DecodeRead literal‘n’

Process
Data

No
operation

4, 0

Before Instruction:
PORTC =
0111 0101 [75h]After Instruction:
PORTC =
0110 0101 [65h]© 2007 Microchip Technology Inc.

If No Jump:

Example:HERE

Before Instruction
PC
After Instruction
If Overflow
PC
If Overflow
PC

Preliminary

BOV

Jump

=

address (HERE)

=
=
=
=

1;
address (Jump)0;address (HERE + 2)

DS39632D-page 321

PIC18F2455/2550/4455/4550
BZ

Branch if Zero

CALL

Subroutine Call

Syntax:BZnSyntax:CALL k {,s}Operands:-128 ≤ n ≤ 127

Operands:

Operation:

if Zero bit is ‘1’(PC) + 2 + 2n → PC

0 ≤ k ≤ 1048575
s ∈ [0,1]

Operation:

Status Affected:

None(PC) + 4 → TOS,
k → PC<20:1>,
if s = 1(W) → WS,
(STATUS) → STATUSS,(BSR) → BSRS

Status Affected:

None

Encoding:

1110

Description:

0000

nnnn

nnnn

If the Zero bit is ‘1’, then the program
will branch.
The 2’s complement number ‘2n’ isadded to the PC. Since the PC will haveincremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.

Words:

1

Cycles:1(2)Encoding:
1st word (k<7:0>)
2nd word(k<19:8>)

Q1

Q2

Q3

Q4

Read literal‘n’

Process
Data

Write to PC

No
operationNo
operationNo
operationNo
operation

Q2

Q3

Q4

If No Jump:
Q1
DecodeRead literal‘n’

Example:HERE

Before Instruction
PC
After Instruction
If ZeroPC
If ZeroPC

DS39632D-page 322

Process
Data
BZ

No
operation

address (HERE)

=
=
=
=

1;
address (Jump)0;address (HERE + 2)

k7kkk
kkkk

kkkk0
kkkk8

Subroutine call of entire 2-Mbyte
memory range. First, return address(PC + 4) is pushed onto the return
stack. If ‘s’ = 1, the W, STATUS andBSR
registers are also pushed into theirrespective shadow registers, WS,
STATUSS and BSRS. If ‘s’ = 0, no
update occurs (default). Then, the20-bit value ‘k’ is loaded into PC<20:1>.
CALL is a two-cycle instruction.

Words:

2

Cycles:2

Q Cycle Activity:
Q1

Q2

Q3

Q4

DecodeRead literal‘k’<7:0>,

Push PC to
stack

Read literal‘k’<19:8>,
Write to PC

No
operationNo
operationNo
operationNo
operation

HERE

CALL

Jump

=

110s
k19kkkDescription:

Q Cycle Activity:
If Jump:
Decode1110
1111

Example:Before Instruction
PC=
After Instruction
PC
=
TOS
=
WS
=
BSRS
=
STATUSS =Preliminary

THERE,1

address (HERE)
address (THERE)
address (HERE + 4)W
BSR
STATUS© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
CLRF

Clear fSyntax:

CLRF

Operands:

0 ≤ f ≤ 255a ∈ [0,1]

f {,a}

Operation:

000h → f,
1→ZStatus Affected:

Z

Encoding:

0110

Description:

101a

ffff

ffff

Clears the contents of the specified
register.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented andBit-Oriented Instructions in Indexed
Literal Offset Mode” for details.

Words:

1

Cycles:1

CLRWDT

Clear Watchdog Timer

Syntax:

CLRWDT

Operands:

None

Operation:

000h → WDT,
000h → WDT postscaler,
1 → TO,
1 → PD

Status Affected:

TO, PD

Encoding:

Q2

Q3

Q4

Read
register ‘f’

ProcessData

Writeregister ‘f’

CLRF

FLAG_REG,1

Example:Before Instruction
FLAG_REG
After Instruction
FLAG_REG

=

5Ah

=

00h

© 2007 Microchip Technology Inc.

0000

0100

Words:

1

Cycles:1

Q Cycle Activity:
Q1

Q2

Q3

Q4

DecodeNo
operation

Process
Data

No
operation

Example:

Q10000

CLRWDT instruction resets the
Watchdog Timer. It also resets thepostscaler of the WDT. Status bits, TO
and PD, are set.

Q Cycle Activity:
Decode0000

Description:

Preliminary

CLRWDT

Before Instruction
WDT Counter
After Instruction
WDT Counter
WDT Postscaler
TO
PD

=

?

=
=
=
=

00h
0
1
1

DS39632D-page 323

PIC18F2455/2550/4455/4550
COMF

Complement f

CPFSEQ

Compare f with W, Skip if f = W

Syntax:COMF

Syntax:CPFSEQ

Operands:

0 ≤ f ≤ 255a ∈ [0,1]

Operation:(f) – (W),skip if (f) = (W)(unsigned comparison)

Status Affected:

None

f {,d {,a}}Operands:

0 ≤ f ≤ 255
d ∈ [0,1]a ∈ [0,1]

Operation:(f) → dest

Status Affected:

N, Z

Encoding:

0001

11da

ffff

ffff

Description:

The contents of register ‘f’ arecomplemented. If ‘d’ is ‘0’, the result isstored in W. If ‘d’ is ‘1’, the result isstored back in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented andBit-Oriented Instructions in Indexed
Literal Offset Mode” for details.

Words:

1

Cycles:1

Q Cycle Activity:
Q1

Q2

Q3

Q4

DecodeReadregister ‘f’

Process
Data

Write todestination

COMF

REG, 0, 0

Example:Before Instruction
REG=
After Instruction
REG
=
W
=

Encoding:
Description:

0110

001a

ffff

ffff

Compares the contents of data memory
location ‘f’ to the contents of W byperforming an unsigned subtraction.
If ‘f’ = W, then the fetched instruction is
discarded and a NOP is executed
instead, making this a two-cycle
instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented andBit-Oriented Instructions in Indexed
Literal Offset Mode” for details.

Words:

1

Cycles:1(2)Note: 3 cycles if skip and followed
by a 2-word instruction.

Q Cycle Activity:
Q1
DecodeQ3
Process
Data

Q4
No
operation

Q1
Q2
Q3
No
No
No
operation
operation
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
No
No
No
operation
operation
operation
No
No
No
operation
operation
operation

Q4
No
operation

13h

Q2
Read
register ‘f’

If skip:
13h
ECh

Example:HERE
NEQUAL
EQUAL

Before Instruction
PC Address
W
REG
After Instruction
If REGPC
If REGPC

DS39632D-page 324

f {,a}

Preliminary

Q4
No
operationNo
operation

CPFSEQ REG, 0
:
:

=
=
=

HERE
?
?

=
=
≠
=

W;
Address (EQUAL)W;
Address (NEQUAL)© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
CPFSGT

Compare f with W, Skip if f > W

CPFSLT

Compare f with W, Skip if f < W

Syntax:CPFSGT

Syntax:CPFSLT

Operands:

0 ≤ f ≤ 255a ∈ [0,1]

Operands:

Operation:(f) – (W),skip if (f) > (W)(unsigned comparison)0 ≤ f ≤ 255a ∈ [0,1]

Operation:(f) – (W),skip if (f) < (W)(unsigned comparison)

Status Affected:

None

Status Affected:

None

Encoding:
Description:

Words:
Cycles:Q Cycle Activity:
Q1
Decode0110

f {,a}

010a

ffff

ffff

Compares the contents of data memory
location ‘f’ to the contents of the W byperforming an unsigned subtraction.
If the contents of ‘f’ are greater than thecontents of WREG, then the fetched
instruction is discarded and a NOP is
executed instead, making this atwo-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented andBit-Oriented Instructions in Indexed
Literal Offset Mode” for details.

Encoding:

Q2
Readregister ‘f’

Q3
Process
Data

Q4
No
operation

Q1
Q2
Q3
No
No
No
operation
operation
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
No
No
No
operation
operation
operation
No
No
No
operation
operation
operation

Q4
No
operation

Example:HERE
NGREATERGREATER

Before Instruction
PC
W
After Instruction
If REGPC
If REGPC

Address (HERE)
?

>
=
≤
=

W;
Address (GREATER)W;
Address (NGREATER)© 2007 Microchip Technology Inc.

ffff

ffff

Words:

1

Cycles:

1(2)
Note:

3 cycles if skip and followed
by a 2-word instruction.

Q Cycle Activity:
Q1

Q2

Q3

Q4

DecodeReadregister ‘f’

Process
Data

No
operation

If skip:
Q1

Q2

Q3

Q4

No
operationNo
operationNo
operationNo
operation

If skip and followed by 2-word instruction:
Q1

Q2

Q3

Q4

No
operationNo
operationNo
operationNo
operationNo
operationNo
operationNo
operationNo
operation

HERE
NLESS
LESS

CPFSLT REG, 1::

Example:Before Instruction
PC
W
After Instruction
If REGPC
If REGPC

CPFSGT REG, 0
:
:

=
=

000a

Compares the contents of data memory
location ‘f’ to the contents of W byperforming an unsigned subtraction.
If the contents of ‘f’ are less than thecontents of W, then the fetched
instruction is discarded and a NOP is
executed instead, making this atwo-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).

If skip:

Q4
No
operationNo
operation

0110

Description:11(2)Note: 3 cycles if skip and followed
by a 2-word instruction.

f {,a}

Preliminary==

Address (HERE)
?

<
=
≥
=

W;
Address (LESS)W;
Address (NLESS)

DS39632D-page 325

PIC18F2455/2550/4455/4550
DAW

Decimal Adjust W Register

DECF

Decrement f

Syntax:DAW

Syntax:DECF f {,d {,a}}Operands:

None

Operands:

Operation:

If [W<3:0> > 9] or [DC = 1] then(W<3:0>) + 6 → W<3:0>;
else(W<3:0>) → W<3:0>

0 ≤ f ≤ 255
d ∈ [0,1]a ∈ [0,1]

Operation:(f) – 1 → dest

Status Affected:

C, DC, N, OV, Z

If [W<7:4> + DC > 9] or [C = 1] then(W<7:4>) + 6 + DC → W<7:4>;
else(W<7:4>) + DC → W<7:4>
Status Affected:

Encoding:

0000

0000

0000

0000

DAW adjusts the eight-bit value in W,
resulting from the earlier addition of two
variables (each in packed BCD format)
and produces a correct packed BCD
result.

Words:

1

Cycles:1

Q Cycle Activity:
Q1

Q2

Q3

Q4

DecodeReadregister W

Process
Data

Write
W

Example 1:

Words:

1

Cycles:1

Q Cycle Activity:

DAW

Before Instruction
W
=
C
=
DC
=
After Instruction
W
=
C
=
DC
=

A5h
0
0

DS39632D-page 326

Q1

Q2

Q3

Q4

DecodeReadregister ‘f’

Process
Data

Write todestination

Example:DECF

Before Instruction
CNT
=
Z
=
After Instruction
CNT
=
Z
=

05h
1
0

Example 2:
Before Instruction
W
=
C
=
DC
=
After Instruction
W
=
C
=
DC
=

ffff

Decrement register ‘f’. If ‘d’ is ‘0’, theresult is stored in W. If ‘d’ is ‘1’, theresult is stored back in register ‘f’(default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented andBit-Oriented Instructions in Indexed
Literal Offset Mode” for details.

0111

Description:

ffff

Description:

C

Encoding:

01da

CNT,

1, 0

01h
0
00h
1

CEh
0
0
34h
1
0

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
DECFSZ

Decrement f, Skip if 0

DCFSNZ

Decrement f, Skip if Not 0

Syntax:DECFSZ f {,d {,a}}Syntax:DCFSNZ

Operands:

0 ≤ f ≤ 255
d ∈ [0,1]a ∈ [0,1]

Operands:

0 ≤ f ≤ 255
d ∈ [0,1]a ∈ [0,1]

Operation:(f) – 1 → dest,
skip if result = 0

Operation:(f) – 1 → dest,
skip if result ≠ 0

Status Affected:

None

Status Affected:

None

Encoding:

0010

11da

ffff

ffff

Description:

The contents of register ‘f’ aredecremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If the result is ‘0’, the next instruction,
which is already fetched, is discarded
and a NOP is executed instead, making
it a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented andBit-Oriented Instructions in Indexed
Literal Offset Mode” for details.

Words:

1

Cycles:1(2)Note: 3 cycles if skip and followed
by a 2-word instruction.

Encoding:

0100

Description:

11da

Q2

Q3

Q4

Read
register ‘f’

Process
Data

Write todestination

Words:

1

Cycles:

1(2)
Note:

3 cycles if skip and followed
by a 2-word instruction.

Q1

Q2

Q3

Q4

No
operationNo
operationNo
operationNo
operation

Q1

Q2

Q3

Q4

DecodeReadregister ‘f’

Process
Data

Write todestination

If skip:
If skip:

If skip and followed by 2-word instruction:

Q1

Q2

Q3

Q4

No
operationNo
operationNo
operationNo
operation

If skip and followed by 2-word instruction:

Q1

Q2

Q3

Q4

No
operationNo
operationNo
operationNo
operationNo
operationNo
operationNo
operationNo
operation

HERE

DECFSZ
GOTO

CNT, 1, 1
LOOP

Q1

Q2

Q3

Q4

No
operationNo
operationNo
operationNo
operationNo
operationNo
operationNo
operationNo
operation

Example:CONTINUE

HERE
ZERO
NZERO

Before Instruction
TEMP
After Instruction
TEMP
If TEMPPC
If TEMPPC

Address (HERE)
CNT – 10;
Address (CONTINUE)
0;
Address (HERE + 2)

© 2007 Microchip Technology Inc.

ffff

Q Cycle Activity:

Q1
DecodeBefore Instruction
PC=
After Instruction
CNT=
If CNT=PC =If CNT
≠
PC =

ffff

The contents of register ‘f’ aredecremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If the result is not ‘0’, the next
instruction, which is already fetched, isdiscarded and a NOP is executed
instead, making it a two-cycle
instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented andBit-Oriented Instructions in Indexed
Literal Offset Mode” for details.

Q Cycle Activity:

Example:f {,d {,a}}Preliminary

DCFSNZ::

TEMP, 1, 0

=

?

=
=
=
≠
=

TEMP – 1,0;
Address (ZERO)
0;
Address (NZERO)

DS39632D-page 327

PIC18F2455/2550/4455/4550
GOTO

Unconditional Branch

INCF

Increment f

Syntax:GOTO kSyntax:INCF

Operands:

0 ≤ k ≤ 1048575

Operands:

Operation:

k → PC<20:1>

Status Affected:

None

0 ≤ f ≤ 255
d ∈ [0,1]a ∈ [0,1]

Operation:(f) + 1 → dest

Status Affected:

C, DC, N, OV, Z

Encoding:
1st word (k<7:0>)
2nd word(k<19:8>)

1110
1111

1111
k19kkk

k7kkk
kkkk

kkkk0
kkkk8

Description:

GOTO allows an unconditional branch
anywhere within the entire
2-Mbyte memory range. The 20-bit
value ‘k’ is loaded into PC<20:1>. GOTO
is always a two-cycle instruction.

Words:

2

Cycles:2

Encoding:

0010

Q1

Q2

Q3

Q4

Read literal‘k’<7:0>,

No
operation

Read literal‘k’<19:8>,
Write to PC

No
operationNo
operationNo
operationNo
operation

Example:GOTO THERE

ffff

ffff

The contents of register ‘f’ areincremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented andBit-Oriented Instructions in Indexed
Literal Offset Mode” for details.

Words:

1

Cycles:1

Q Cycle Activity:

After Instruction
PC =Address (THERE)

Q1

Q2

Q3

Q4

DecodeReadregister ‘f’

Process
Data

Write todestination

INCF

CNT, 1, 0

Example:Before Instruction
CNT
=
Z
=
C
=
DC
=
After Instruction
CNT
=
Z
=
C
=
DC
=

DS39632D-page 328

10da

Description:

Q Cycle Activity:
Decodef {,d {,a}}Preliminary

FFh
0
?
?
00h
1
1
1

© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
INCFSZ

Increment f, Skip if 0

INFSNZ

Syntax:INCFSZ

Syntax:INFSNZ0 ≤ f ≤ 255
d ∈ [0,1]a ∈ [0,1]

f {,d {,a}}Increment f, Skip if Not 0
f {,d {,a}}Operands:

0 ≤ f ≤ 255
d ∈ [0,1]a ∈ [0,1]

Operands:

Operation:(f) + 1 → dest,
skip if result = 0

Operation:(f) + 1 → dest,
skip if result ≠ 0

Status Affected:

None

Status Affected:

None

Encoding:

0011

11da

ffff

ffff

Encoding:

0100

Description:

Description:

The contents of register ‘f’ areincremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’. (default)
If the result is ‘0’, the next instruction,
which is already fetched, is discarded
and a NOP is executed instead, making
it a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented andBit-Oriented Instructions in Indexed
Literal Offset Mode” for details.

Words:

1

Words:

1

Cycles:1(2)Note: 3 cycles if skip and followed
by a 2-word instruction.

Cycles:

1(2)
Note:

Q Cycle Activity:

10da

ffff

ffff

The contents of register ‘f’ areincremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If the result is not ‘0’, the next
instruction, which is already fetched, isdiscarded and a NOP is executed
instead, making it a two-cycle
instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented andBit-Oriented Instructions in Indexed
Literal Offset Mode” for details.

3 cycles if skip and followed
by a 2-word instruction.

Q Cycle Activity:

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

DecodeReadregister ‘f’

Process
Data

Write todestination

DecodeReadregister ‘f’

Process
Data

Write todestination

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

No
operationNo
operationNo
operationNo
operationNo
operationNo
operationNo
operationNo
operation

If skip:

If skip:

If skip and followed by 2-word instruction:

If skip and followed by 2-word instruction:

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

No
operationNo
operationNo
operationNo
operationNo
operationNo
operationNo
operationNo
operationNo
operationNo
operationNo
operationNo
operationNo
operationNo
operationNo
operationNo
operation

Example:

HERE
NZERO
ZERO

Before Instruction
PC=
After Instruction
CNT=
If CNT=PC=
If CNT≠PC=

INCFSZ::

CNT, 1, 0

Example:Before Instruction
PC=
After Instruction
REG=
If REG≠PC=
If REG=PC=

Address (HERE)
CNT + 10;
Address (ZERO)
0;
Address (NZERO)© 2007 Microchip Technology Inc.

HERE
ZERO
NZERO

Preliminary

INFSNZ

REG, 1, 0

Address (HERE)
REG + 10;
Address (NZERO)
0;
Address (ZERO)

DS39632D-page 329

PIC18F2455/2550/4455/4550
IORLW

Inclusive OR Literal with W

IORWF

Inclusive OR W with f

Syntax:IORLW kSyntax:IORWF

Operands:

0 ≤ k ≤ 255

Operands:

Operation:(W) .OR. k → W

Status Affected:

N, Z

0 ≤ f ≤ 255
d ∈ [0,1]a ∈ [0,1]

Operation:(W) .OR. (f) → dest

Status Affected:

N, Z

Encoding:

0000

1001

kkkk

kkkk

Description:

The contents of W are ORed with theeight-bit literal ‘k’. The result is placed inW.

Words:

1

Cycles:1

Encoding:

0001

Q1

Q2

Q3

Q4

Read
literal ‘k’

Process
Data

Write to W

IORLW

35h

Example:Before Instruction
W=
After Instruction
W
=

ffff

ffff

Inclusive OR W with register ‘f’. If ‘d’ is‘0’, the result is placed in W. If ‘d’ is ‘1’,
the result is placed back in register ‘f’(default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented andBit-Oriented Instructions in Indexed
Literal Offset Mode” for details.

Words:

1

Cycles:

1

9Ah
BFh

00da

Description:

Q Cycle Activity:
Decodef {,d {,a}}Q Cycle Activity:
Q1

Q2

Q3

Q4

DecodeReadregister ‘f’

Process
Data

Write todestination

IORWF

RESULT, 0, 1

Example:Before Instruction
RESULT =W=
After Instruction
RESULT =W=

DS39632D-page 330

Preliminary

13h
91h
13h
93h

© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
LFSR

Load FSR

MOVF

Move fSyntax:

LFSR f, k

Syntax:MOVF

Operands:0≤f≤2
0 ≤ k ≤ 4095

Operands:

Operation:

k → FSRf

0 ≤ f ≤ 255
d ∈ [0,1]a ∈ [0,1]

Status Affected:

None

Operation:f → dest

Status Affected:

N, Z

Encoding:

1110
1111

1110
0000

00ff
k7kkk

k11kkkkkkk

Description:

The 12-bit literal ‘k’ is loaded into theFile Select Register pointed to by ‘f’.

Words:

2

Cycles:2

Encoding:

0101

Q1

Q2

Q3

Q4

Read literal‘k’ MSB

ProcessData

Writeliteral ‘k’ MSB
to FSRfH

DecodeRead literal‘k’ LSB

Process
Data

Write literal ‘k’
to FSRfL

Example:After Instruction
FSR2H
FSR2L

03h
ABh

ffff

ffff

The contents of register ‘f’ are moved toa destination dependent upon thestatus of ‘d’. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
Location ‘f’ can be anywhere in the256-byte bank.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented andBit-Oriented Instructions in Indexed
Literal Offset Mode” for details.

Words:

1

Cycles:1

LFSR 2, 3ABh
=
=

00da

Description:

Q Cycle Activity:
Decodef {,d {,a}}Q Cycle Activity:
Q1

Q2

Q3

Q4

DecodeReadregister ‘f’

Process
Data

Write W

Example:MOVF

Before Instruction
REG
W
After Instruction
REG
W© 2007 Microchip Technology Inc.

Preliminary

REG, 0, 0

=
=

22h
FFh

=
=

22h
22h

DS39632D-page 331

PIC18F2455/2550/4455/4550
MOVFF

Move f to f

MOVLB

Move Literal to Low Nibble in BSR

Syntax:

MOVFF fs,fd

Syntax:MOVLW kOperands:

0 ≤ fs ≤ 4095
0 ≤ fd ≤ 4095

Operands:

0 ≤ k ≤ 255

Operation:k → BSR

Status Affected:

None

Operation:(fs) → fd

Status Affected:

None

Encoding:
1st word (source)
2nd word (destin.)

Encoding:

1100
1111

Description:

ffff
ffff

ffff
ffff

ffffs
ffffd

The contents of source register ‘fs’ are
moved to destination register ‘fd’.
Location of source ‘fs’ can be anywherein the 4096-byte data space (000h toFFFh) and location of destination ‘fd’
can also be anywhere from 000h to
FFFh.
Either source or destination can be W
(a useful special situation).
MOVFF is particularly useful fortransferring a data memory location to a
peripheral register (such as the transmit
buffer or an I/O port).
The MOVFF instruction cannot use the
PCL, TOSU, TOSH or TOSL as thedestination register.

Words:

2

Cycles:

2

0000

0001

kkkk

kkkk

Description:

The eight-bit literal ‘k’ is loaded into the
Bank Select Register (BSR). The valueof BSR<7:4> always remains ‘0’
regardless of the value of k7:k4.

Words:

1

Cycles:1

Q Cycle Activity:
Q1

Q2

Q3

Q4

DecodeReadliteral ‘k’

Process
Data

Write literal‘k’ to BSR

MOVLB

5

Example:Before Instruction
BSR Register =After Instruction
BSR Register =

02h
05h

Q Cycle Activity:
Q1

Q2

Q3

Q4

DecodeReadregister ‘f’(src)

Process
Data

No
operation

DecodeNo
operationNo
operation

Writeregister ‘f’(dest)

No dummy
read
Example:MOVFF

Before Instruction
REG1
REG2
After Instruction
REG1
REG2

DS39632D-page 332

REG1, REG2

=
=

33h
11h

=
=

33h
33h

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
MOVLW

Move Literal to W

MOVWF

Move W to f

Syntax:MOVLW kSyntax:

MOVWF

Operands:

0 ≤ k ≤ 255

Operands:

Operation:k→W

0 ≤ f ≤ 255a ∈ [0,1]

Status Affected:

None

Encoding:

0000

Description:

1110

kkkk

kkkk

The eight-bit literal ‘k’ is loaded into W.

Words:

1

Cycles:1

Operation:(W) → fStatus Affected:

None

Encoding:

0110

Q1

Q2

Q3

Q4

Read
literal ‘k’

Process
Data

Write to W

MOVLW

5Ah

Example:After Instruction
W
=

111a

ffff

ffff

Description:

Move data from W to register ‘f’.
Location ‘f’ can be anywhere in the256-byte bank.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented andBit-Oriented Instructions in Indexed
Literal Offset Mode” for details.

Words:

1

Cycles:1

Q Cycle Activity:
Decodef {,a}5Ah

Q Cycle Activity:
Q1

Q2

Q3

Q4

DecodeReadregister ‘f’

ProcessData

Writeregister ‘f’

Example:

MOVWF

Before Instruction
W
=
REG
=
After Instruction
W
=
REG
=

© 2007 Microchip Technology Inc.

Preliminary

REG, 0

4Fh
FFh
4Fh
4Fh

DS39632D-page 333

PIC18F2455/2550/4455/4550
MULLW

Multiply Literal with W

MULWF

Syntax:

MULLW

Syntax:

MULWF

Operands:

0 ≤ k ≤ 255

Operands:

Operation:(W) x k → PRODH:PRODL

0 ≤ f ≤ 255a ∈ [0,1]

Status Affected:

None

Operation:(W) x (f) → PRODH:PRODL

Status Affected:

None

Encoding:

0000

Description:

k

1101

kkkk

kkkk

An unsigned multiplication is carriedout between the contents of W and the
8-bit literal ‘k’. The 16-bit result is
placed in PRODH:PRODL register pair.
PRODH contains the high byte.
W is unchanged.
None of the Status flags are affected.
Note that neither Overflow nor Carry is
possible in this operation. A zero result
is possible but not detected.

Words:

1

Cycles:1

Multiply W with f

Encoding:

0000

Q1

Q2

Q3

Q4

Read
literal ‘k’

ProcessData

Writeregisters
PRODH:PRODL

Example:Before Instruction
W
PRODH
PRODL
After Instruction
W
PRODH
PRODL

MULLW
=
=
=

ffff

Words:

1

Cycles:1

Q Cycle Activity:
=
=
=

E2h
ADh
08h

Q1

Q2

Q3

Q4

DecodeReadregister ‘f’

ProcessData

Writeregisters
PRODH:PRODL

Example:Before Instruction
W
REG
PRODH
PRODL
After Instruction
W
REG
PRODH
PRODL

DS39632D-page 334

ffff

An unsigned multiplication is carriedout between the contents of W and theregister file location ‘f’. The 16-bit
result is stored in the PRODH:PRODL
register pair. PRODH contains thehigh byte. Both W and ‘f’ areunchanged.
None of the Status flags are affected.
Note that neither Overflow nor Carry is
possible in this operation. A zero
result is possible but not detected.
If ‘a’ is ‘0’, the Access Bank isselected. If ‘a’ is ‘1’, the BSR is used
to select the GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction
operates in Indexed Literal Offset
Addressing mode wheneverf ≤ 95 (5Fh). See Section 26.2.3“Byte-Oriented and Bit-Oriented
Instructions in Indexed Literal Offset
Mode” for details.

0C4h
E2h
?
?

001a

Description:

Q Cycle Activity:
Decodef {,a}

Preliminary

MULWF

REG, 1

=
=
=
=

C4h
B5h
?
?

=
=
=
=

C4h
B5h
8Ah
94h

© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
NEGF

Negate f

Syntax:

NEGF

Operands:

0 ≤ f ≤ 255a ∈ [0,1]

f {,a}

Operation:(f) + 1 → f

Status Affected:

N, OV, C, DC, Z

Encoding:

0110

Description:

1

Cycles:1

No Operation

Syntax:NOP

Operands:

None

Operation:

No operation

Status Affected:

None

Encoding:

110a

ffff

0000
1111

ffff

Location ‘f’ is negated using two’s
complement. The result is placed in thedata memory location ‘f’.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented andBit-Oriented Instructions in Indexed
Literal Offset Mode” for details.

Words:

NOP

0000
xxxx

Description:

No operation.

Words:

1

Cycles:

1

0000
xxxx

0000
xxxx

Q Cycle Activity:
Q1

Q2

Q3

Q4

DecodeNo
operationNo
operationNo
operation

Example:None.

Q Cycle Activity:
Q1

Q2

Q3

Q4

DecodeReadregister ‘f’

ProcessData

Writeregister ‘f’

Example:NEGF

Before Instruction
REG=
After Instruction
REG=

REG, 10011 1010 [3Ah]1100 0110 [C6h]© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 335

PIC18F2455/2550/4455/4550
POP

Pop Top of Return Stack

PUSH

Push Top of Return Stack

Syntax:POP

Syntax:

PUSH

Operands:

None

Operands:

None

Operation:(TOS) → bit bucket

Operation:(PC + 2) → TOS

Status Affected:

None

Status Affected:

None

Encoding:

0000

0000

0000

0110

Description:

The TOS value is pulled off the return
stack and is discarded. The TOS value
then becomes the previous value thatwas pushed onto the return stack.
This instruction is provided to enable
the user to properly manage the return
stack to incorporate a software stack.

Words:

1

Cycles:1

Encoding:

Q2

Q3

Q4

DecodeNo
operation

Pop TOSvalue

No
operation

POP
GOTO

NEW

Before Instruction
TOS
Stack (1 level down)

DS39632D-page 336

0000

0101

The PC + 2 is pushed onto the top of
the return stack. The previous TOS
value is pushed down on the stack.
This instruction allows implementing asoftware stack by modifying TOS andthen pushing it onto the return stack.

Words:

1

Cycles:1

Q Cycle Activity:

Q1

After Instruction
TOS
PC

0000

Description:

Q Cycle Activity:

Example:

0000

Q1

Q2

Q3

Q4

DecodePush PC + 2
onto return
stack

No
operationNo
operation

Example:====0031A2h014332h014332hNEW

Preliminary

PUSH

Before Instruction
TOS
PC

=
=

345Ah
0124h

After InstructionPC
TOS
Stack (1 level down)

=
=
=

0126h
0126h
345Ah

© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
RCALL

Relative Call

RESET

Reset

Syntax:

RCALL

Syntax:RESETnOperands:-1024 ≤ n ≤ 1023

Operands:

None

Operation:(PC) + 2 → TOS,
(PC) + 2 + 2n → PC

Operation:

Reset all registers and flags that are
affected by a MCLR Reset.

Status Affected:

None

Status Affected:

All

Encoding:

1101

Description:

1nnn

nnnn

nnnn

Subroutine call with a jump up to 1K
from the current location. First, return
address (PC + 2) is pushed onto thestack. Then, add the 2’s complement
number ‘2n’ to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is a
two-cycle instruction.

Words:

1

Cycles:2

Encoding:

0000

Q2

Q3

Q4

Read literal‘n’

Process
Data

Write to PC

No
operationNo
operationNo
operation

HERE

RCALL Jump

1111

Words:

1

Cycles:1

Q Cycle Activity:
Q1

Q2

Q3

Q4

Decode

Start
Reset

No
operationNo
operation

Example:Q1

1111

This instruction provides a way to
execute a MCLR Reset in software.

Q Cycle Activity:
Decode0000

Description:

After Instruction
Registers =Flags*=RESET
Reset Value
Reset Value

Push PC tostack
Nooperation
Example:Before Instruction
PC =Address (HERE)
After Instruction
PC =Address (Jump)
TOS =Address (HERE + 2)

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 337

PIC18F2455/2550/4455/4550
RETFIE

Return from Interrupt

RETLW

Return Literal to W

Syntax:RETFIE {s}Syntax:RETLW kOperands:s ∈ [0,1]

Operands:

0 ≤ k ≤ 255

Operation:(TOS) → PC,
1 → GIE/GIEH or PEIE/GIEL,
if s = 1(WS) → W,(STATUSS) → STATUS,(BSRS) → BSR,PCLATU, PCLATH are unchanged

Operation:

k → W,(TOS) → PC,
PCLATU, PCLATH are unchanged

Status Affected:

None

Status Affected:

Encoding:

0000

Description:

0000

0001

Words:

1

Cycles:2

Q Cycle Activity:

kkkk

kkkk

W is loaded with the eight-bit literal ‘k’.
The program counter is loaded from the
top of the stack (the return address).
The high address latch (PCLATH)
remains unchanged.

Words:

1

Cycles:

2000s

Return from interrupt. Stack is popped
and Top-of-Stack (TOS) is loaded into
the PC. Interrupts are enabled by
setting either the high or low priority
global interrupt enable bit. If ‘s’ = 1, thecontents of the shadow registers WS,
STATUSS and BSRS are loaded into
their corresponding registers, W,
STATUS and BSR. If ‘s’ = 0, no updateof these registers occurs (default).

1100

Description:

GIE/GIEH, PEIE/GIEL.

Encoding:

Q Cycle Activity:
Q1

Q2

Q3

Q4

DecodeReadliteral ‘k’

ProcessData

Pop PC fromstack, Write
to W

No
operationNo
operationNo
operationNo
operation

Example:

Q1

Q2

Q3

Q4

DecodeNo
operationNo
operation

Pop PC fromstack
Set GIEH or
GIEL

No
operation

0000

No
operation

Example:RETFIE

After Interrupt
PC
W
BSR
STATUS
GIE/GIEH, PEIE/GIEL

DS39632D-page 338

NooperationNo
operation

1
=
=
=
=
=

TOS
WS
BSRS
STATUSS
1

CALL TABLE ; W contains table; offset value; W now has; table value:
TABLE
ADDWF PCL ; W = offset
RETLW k0
; Begin table
RETLW k1;::
RETLW kn
; End of table
Before Instruction
W=
After Instruction
W=

Preliminary

07hvalue of kn© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
RETURN

Return from Subroutine

RLCF

Rotate Left f through Carry

Syntax:RETURN {s}Syntax:RLCF

Operands:s ∈ [0,1]

Operands:

Operation:(TOS) → PC,
if s = 1(WS) → W,(STATUSS) → STATUS,(BSRS) → BSR,PCLATU, PCLATH are unchanged

0 ≤ f ≤ 255
d ∈ [0,1]a ∈ [0,1]

Operation:(f<n>) → dest<n + 1>,(f<7>) → C,(C) → dest<0>

Status Affected:

C, N, Z

Status Affected:

None

Encoding:

0000

Encoding:
0000

0001

001s

Description:

Return from subroutine. The stack ispopped and the top of the stack (TOS)
is loaded into the program counter. If‘s’= 1, the contents of the shadow
registers WS, STATUSS and BSRS areloaded into their corresponding
registers, W, STATUS and BSR. If‘s’ = 0, no update of these registers
occurs (default).

Words:

1

Cycles:20011

Description:

Q Cycle Activity:
Q1

Q2

Q3

Q4

DecodeNo
operation

ProcessData

Pop PC
from stackNo
operationNo
operationNo
operationNo
operationf {,d {,a}}

01da

ffff

ffff

The contents of register ‘f’ are rotated
one bit to the left through the Carryflag. If ‘d’ is ‘0’, the result is placed in
W. If ‘d’ is ‘1’, the result is stored backin register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank isselected. If ‘a’ is ‘1’, the BSR is used to
select the GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction
operates in Indexed Literal Offset
Addressing mode wheneverf ≤ 95 (5Fh). See Section 26.2.3“Byte-Oriented and Bit-Oriented
Instructions in Indexed Literal Offset
Mode” for details.
register fCWords:

1

Cycles:1

Q Cycle Activity:
Example:

RETURN

After Instruction:
PC = TOS

Q1

Q2

Q3

Q4

DecodeReadregister ‘f’

Process
Data

Write todestination

Example:Before Instruction
REG
=
C
=
After Instruction
REG
=
W
=
C
=

© 2007 Microchip Technology Inc.

Preliminary

RLCF

REG, 0, 01110 0110
01110 0110
1100 1100
1

DS39632D-page 339

PIC18F2455/2550/4455/4550
RLNCF

Rotate Left f (No Carry)

RRCF

Rotate Right f through Carry

Syntax:RLNCF

Syntax:RRCF

Operands:

0 ≤ f ≤ 255
d ∈ [0,1]a ∈ [0,1]

Operands:

0 ≤ f ≤ 255
d ∈ [0,1]a ∈ [0,1]

Operation:(f<n>) → dest<n + 1>,(f<7>) → dest<0>

Operation:

Status Affected:

N, Z(f<n>) → dest<n – 1>,(f<0>) → C,(C) → dest<7>

Status Affected:

C, N, Z

Encoding:

0100

Description:f {,d {,a}}

01da

ffff

ffff

The contents of register ‘f’ are rotated
one bit to the left. If ‘d’ is ‘0’, the resultis placed in W. If ‘d’ is ‘1’, the result isstored back in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented andBit-Oriented Instructions in Indexed
Literal Offset Mode” for details.

Encoding:

0011

Description:

register f
Words:

1

Cycles:1

DecodeQ2
Readregister ‘f’

Example:Before Instruction
REG=
After Instruction
REG=

DS39632D-page 340

00da

RLNCF

Q3
Process
Data

Q4
Write todestination

Words:

1

Cycles:ffff

register f

1

Q Cycle Activity:
Q1

Q2

Q3

Q4

DecodeReadregister ‘f’

Process
Data

Write todestination

RRCF

REG, 0, 0

REG, 1, 01010 1011

ffff

The contents of register ‘f’ are rotated
one bit to the right through the Carryflag. If ‘d’ is ‘0’, the result is placed in W.
If ‘d’ is ‘1’, the result is placed back inregister ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented andBit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
C

Q Cycle Activity:Q1

f {,d {,a}}Example:Before Instruction
REG
=
C
=
After Instruction
REG
=
W
=
C
=

0101 0111

Preliminary

1110 0110
01110 0110
0111 0011
0© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
RRNCF

Rotate Right f (No Carry)

SETF

Set f

Syntax:RRNCF

Syntax:

SETF

Operands:

0 ≤ f ≤ 255
d ∈ [0,1]a ∈ [0,1]

Operands:

0 ≤ f ≤ 255a ∈ [0,1]

Operation:(f<n>) → dest<n – 1>,(f<0>) → dest<7>

Status Affected:

N, Z

Encoding:

0100

Description:f {,d {,a}}00daOperation:

FFh → fStatus Affected:

None

Encoding:
ffff

ffff

The contents of register ‘f’ are rotated
one bit to the right. If ‘d’ is ‘0’, the resultis placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank will beselected, overriding the BSR value. If ‘a’is ‘1’, then the bank will be selected as
per the BSR value (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented andBit-Oriented Instructions in Indexed
Literal Offset Mode” for details.

1

Cycles:1
Q3

Q4

DecodeReadregister ‘f’

Process
Data

Write todestination

RRNCF

REG, 1, 0

Example 1:

Before Instruction
REG=
After Instruction
REG=
Example 2:

ffff

1

Cycles:1

Q Cycle Activity:
Q1

Q2

Q3

Q4

DecodeReadregister ‘f’

ProcessData

Writeregister ‘f’

SETF

Before Instruction
REG
After Instruction
REG

REG,1

=

5Ah

=

FFh

1101 0111
1110 1011

RRNCF

Before Instruction
W
=
REG
=
After Instruction
W
=
REG
=

ffff

Words:Q Cycle Activity:
Q2

100a

The contents of the specified registerare set to FFh.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented andBit-Oriented Instructions in Indexed
Literal Offset Mode” for details.

Example:Q1

0110

Description:

register f
Words:

f {,a}

REG, 0, 0?
1101 0111
1110 1011
1101 0111© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 341

PIC18F2455/2550/4455/4550
SLEEP

Enter Sleep mode

SUBFWB

Subtract f from W with Borrow

Syntax:SLEEP

Syntax:SUBFWB

Operands:

None

Operands:

Operation:

00h → WDT,
0 → WDT postscaler,
1 → TO,
0 → PD0 ≤ f ≤ 255
d ∈ [0,1]a ∈ [0,1]

Operation:(W) – (f) – (C) → dest

Status Affected:

N, OV, C, DC, Z

Status Affected:

TO, PD

Encoding:

0000

Encoding:
0000

0000

0011

Description:

The Power-Down status bit (PD) is
cleared. The Time-out status bit (TO)is set. Watchdog Timer and its
postscaler are cleared.
The processor is put into Sleep modewith the oscillator stopped.

Words:

1

Cycles:

1

0101

Q1

Q2

Q3

Q4

No
operation

Process
Data

Go to
Sleep

Example:SLEEP

Before Instruction
TO =
?
?
PD =

DS39632D-page 342

ffff

ffff

Subtract register ‘f’ and Carry flag(borrow) from W (2’s complement
method). If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored inregister ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank isselected. If ‘a’ is ‘1’, the BSR is used
to select the GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction
operates in Indexed Literal Offset
Addressing mode wheneverf ≤ 95 (5Fh). See Section 26.2.3“Byte-Oriented and Bit-Oriented
Instructions in Indexed Literal Offset
Mode” for details.

Words:

1

Cycles:1

Q Cycle Activity:

After Instruction
1†
TO =
PD =
0
† If WDT causes wake-up, this bit is cleared.

01da

Description:

Q Cycle Activity:
Decodef {,d {,a}}

Q1

Q2

Q3

Q4

DecodeReadregister ‘f’

Process
Data

Write todestination

SUBFWB
REG, 1, 0
Example 1:
Before Instruction
REG
=
3
W
=
2
C
=
1
After Instruction
REG
=
FF
W
=
2
C
=
0
Z
=
0
N
=
1 ; result is negative
SUBFWB
REG, 0, 0
Example 2:
Before Instruction
REG
=
2
W
=
5
C
=
1
After Instruction
REG
=
2
W
=
3
C
=
1
Z
=
0
N
=
0 ; result is positive
SUBFWB
REG, 1, 0
Example 3:
Before Instruction
REG
=
1
W
=
2
C
=
0
After Instruction
REG
=
0
W
=
2
C
=
1
Z
=
1 ; result is zeroN=
0Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
SUBLW

Subtract W from Literal

SUBWF

Subtract W from f

Syntax:SUBLW kSyntax:SUBWF

Operands:

0 ≤ k ≤ 255

Operands:

Operation:k – (W) → W

Status Affected:

N, OV, C, DC, Z

0 ≤ f ≤ 255
d ∈ [0,1]a ∈ [0,1]

Operation:(f) – (W) → dest

Status Affected:

N, OV, C, DC, Z

Encoding:

0000

1000

kkkk

kkkk

Description

W is subtracted from the eight-bit
literal ‘k’. The result is placed in W.

Words:

1

Cycles:1

Encoding:

0101

Q1

Q2

Q3

Q4

Read
literal ‘k’

Process
Data

Write to W

Example 1:
Before Instruction
W=
C=
After Instruction
W
=
C
=
Z
=
N
=
Example 2:
Before Instruction
W=
C=
After Instruction
W
=
C
=
Z
=
N
=
Example 3:
Before Instruction
W=
C=
After Instruction
W
=
C
=
Z
=
N
=

SUBLW

SUBLW

1

Cycles:1; result is positive02h?

Q Cycle Activity:00h
1; result is zero
1
0
SUBLW

Q1

Q2

Q3

Q4

DecodeReadregister ‘f’

Process
Data

Write todestination

SUBWF

REG, 1, 0

Example 1:
Before Instruction
REG
=
W
=
C
=
After Instruction
REG
=
W
=
C
=
Z
=
N
=

02h

03h
?
FFh
0
0
1

ffff

Words:

02h

02h

ffff

Subtract W from register ‘f’ (2’scomplement method). If ‘d’ is ‘0’, theresult is stored in W. If ‘d’ is ‘1’, theresult is stored back in register ‘f’(default).
If ‘a’ is ‘0’, the Access Bank isselected. If ‘a’ is ‘1’, the BSR is used
to select the GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction
operates in Indexed Literal Offset
Addressing mode wheneverf ≤ 95 (5Fh). See Section 26.2.3“Byte-Oriented and Bit-Oriented
Instructions in Indexed Literal Offset
Mode” for details.

01h
?
01h
1
0
0

11da

Description:

Q Cycle Activity:
Decodef {,d {,a}}; (2’s complement); result is negative

Example 2:
Before Instruction
REG
=
W
=
C
=
After Instruction
REG
=
W
=
C
=
Z
=
N
=
Example 3:
Before Instruction
REG
=
W
=
C
=
After Instruction
REG
=
W
=
C
=
Z
=
N
=

© 2007 Microchip Technology Inc.

Preliminary

3
2
?
1
2
1
0
0

; result is positive

SUBWF

REG, 0, 0

2
2
?
2
0
1
1
0
SUBWF

; result is zero

REG, 1, 0

12?
FFh ;(2’s complement)
20; result is negative
0
1

DS39632D-page 343

PIC18F2455/2550/4455/4550
SUBWFB

Subtract W from f with Borrow

SWAPF

Swap fSyntax:SUBWFB

Syntax:SWAPF f {,d {,a}}Operands:

0 ≤ f ≤ 255
d ∈ [0,1]a ∈ [0,1]

Operands:

Operation:(f) – (W) – (C) → dest0 ≤ f ≤ 255
d ∈ [0,1]a ∈ [0,1]

Operation:

Status Affected:

N, OV, C, DC, Z(f<3:0>) → dest<7:4>,(f<7:4>) → dest<3:0>

Status Affected:

None

Encoding:

0101

Description:

1

Cycles:

1

ffff

Q2
Read
register ‘f’

Q3
Process
Data

SUBWFB

REG, 1, 0

Example 1:
Before Instruction
REG
=
W
=
C
=
After Instruction
REG
=
W
=
C
=
Z
=
N
=
Example 2:

ffff

Q4
Write todestination

19h
0Dh
1

(0001 1001)(0000 1101)

0Ch
0Dh
1
0
0

(0000 1011)(0000 1101)

Encoding:

0011

10da

ffff

ffff

Description:

The upper and lower nibbles of register‘f’ are exchanged. If ‘d’ is ‘0’, the resultis placed in W. If ‘d’ is ‘1’, the result is
placed in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented andBit-Oriented Instructions in Indexed
Literal Offset Mode” for details.

Words:

1

Cycles:1

Q Cycle Activity:
Q1

Q2

Q3

Q4

DecodeReadregister ‘f’

Process
Data

Write todestination

Example:SWAPF

Before Instruction
REG=
After Instruction
REG=

REG, 1, 053h
35h; result is positive

SUBWFB REG, 0, 0

Before Instruction
REG
=
W
=
C
=
After Instruction
REG
=
W
=
C
=
Z
=
N
=
Example 3:

1Bh
1Ah
0

(0001 1011)(0001 1010)

1Bh
00h
1
1
0

(0001 1011)

SUBWFB

Before Instruction
REG
=
W
=
C
=
After Instruction
REG
=
W
C
Z
N

10da

Subtract W and the Carry flag (borrow)from register ‘f’ (2’s complement
method). If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored backin register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented andBit-Oriented Instructions in Indexed
Literal Offset Mode” for details.

Words:Q Cycle Activity:
Q1
Decodef {,d {,a}}

=
=
=
=

DS39632D-page 344; result is zero
REG, 1, 0

03h
0Eh
1

(0000 0011)(0000 1101)

F5h(1111 0100); [2’s comp](0000 1101)

0Eh
0
0
1

; result is negative

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
TBLRD

Table Read

TBLRD

Table Read (Continued)

Syntax:TBLRD ( *; *+; *-; +*)Example 1:

TBLRD

Operands:

None

Operation:

if TBLRD *(Prog Mem (TBLPTR)) → TABLAT;TBLPTR – No Change;
if TBLRD *+(Prog Mem (TBLPTR)) → TABLAT;(TBLPTR) + 1 → TBLPTR;
if TBLRD *(Prog Mem (TBLPTR)) → TABLAT;(TBLPTR) – 1 → TBLPTR;
if TBLRD +*(TBLPTR) + 1 → TBLPTR;(Prog Mem (TBLPTR)) → TABLAT

Before Instruction
TABLAT
TBLPTRMEMORY (00A356h)
After Instruction
TABLAT
TBLPTR
Example 2:

0000

0000

0000

TBLRD

=
=
=

55h
00A356h
34h

=
=

34h
00A357h+* ;Before Instruction
TABLAT
TBLPTRMEMORY (01A357h)
MEMORY (01A358h)
After Instruction
TABLAT
TBLPTR

Status Affected: None
Encoding:

*+ ;

=
=
=
=

AAh
01A357h
12h
34h

=
=

34h
01A358h10nnnn=0 *=1 *+=2 *=3 +*Description:

This instruction is used to read the contentsof Program Memory (P.M.). To address the
program memory, a pointer called Table
Pointer (TBLPTR) is used.
The TBLPTR (a 21-bit pointer) points toeach byte in the program memory. TBLPTR
has a 2-Mbyte address range.
TBLPTR[0] = 0: Least Significant Byte
of Program Memory
Word
TBLPTR[0] = 1: Most Significant Byte
of Program Memory
Word
The TBLRD instruction can modify the valueof TBLPTR as follows:• no change• post-increment• post-decrement• pre-increment

Words:

1

Cycles:2

Q Cycle Activity:
Q1

Q2

Q3

Q4

DecodeNo
operationNo
operationNo
operationNo
operation

No operation(Read Program
Memory)No
operation

No operation(WriteTABLAT)© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 345

PIC18F2455/2550/4455/4550
TBLWT

Table Write

TBLWT

Table Write (Continued)

Syntax:TBLWT ( *; *+; *-; +*)Example 1:

TBLWTOperands:

None

Operation:

if TBLWT*(TABLAT) → Holding Register;
TBLPTR – No Change;
if TBLWT*+(TABLAT) → Holding Register;(TBLPTR) + 1 → TBLPTR;
if TBLWT*(TABLAT) → Holding Register;(TBLPTR) – 1 → TBLPTR;
if TBLWT+*(TBLPTR) + 1 → TBLPTR;(TABLAT) → Holding Register

Before Instruction
TABLAT=
55h
TBLPTR=
00A356h
HOLDING REGISTER(00A356h)=
FFh
After Instructions (table write completion)
TABLAT=
55h
TBLPTR=
00A357h
HOLDING REGISTER(00A356h)=
55h
Example 2:

Status Affected: None
Encoding:

0000

0000

0000

*+;

11nn
nn=0 *=1 *+=2 *=3 +*Description:

This instruction uses the 3 LSBs of TBLPTR
to determine which of the
8 holding registers the TABLAT is written to.
The holding registers are used toprogram the contents of Program
Memory (P.M.). (Refer to Section 6.0“Flash Program Memory” for additional
details on programming Flash memory.)
The TBLPTR (a 21-bit pointer) points toeach byte in the program memory. TBLPTR
has a 2-Mbyte address range. The LSb of
the TBLPTR selects which byte of the
program memory location to access.
TBLPTR[0] = 0: Least Significant
Byte of Program
Memory Word
TBLPTR[0] = 1: Most Significant
Byte of Program
Memory Word
The TBLWT instruction can modify thevalue of TBLPTR as follows:• no change• post-increment• post-decrement• pre-increment

Words:

1

Cycles:

2

TBLWT

+*;

Before Instruction
TABLAT=
34h
TBLPTR=
01389AhHOLDING REGISTER(01389Ah)=
FFh
HOLDING REGISTER(01389Bh)=
FFh
After Instruction (table write completion)
TABLAT=
34h
TBLPTR=
01389Bh
HOLDING REGISTER(01389Ah)=
FFh
HOLDING REGISTER(01389Bh)=
34h

Q Cycle Activity:
Q1
Decode

Q2

Q3

Q4

No
No
No
operation operation operation

No
No
No
No
operation operation operation operation(Read(Write to
TABLAT)
Holding
Register)

DS39632D-page 346

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
TSTFSZ

Test f, Skip if 0

Syntax:TSTFSZ f {,a}Operands:

0 ≤ f ≤ 255a ∈ [0,1]

Operation:

skip if f = 0

Status Affected:

None

Encoding:

0110

Description:

011a

ffff

ffff

If ‘f’ = 0, the next instruction fetchedduring the current instruction execution
is discarded and a NOP is executed,
making this a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented andBit-Oriented Instructions in Indexed
Literal Offset Mode” for details.

Words:

1

Cycles:1(2)Note: 3 cycles if skip and followed
by a 2-word instruction.

XORLW

Exclusive OR Literal with W

Syntax:XORLW kOperands:

0 ≤ k ≤ 255

Operation:(W) .XOR. k → W

Status Affected:

N, Z

Encoding:

0000

1010

kkkk

kkkk

Description:

The contents of W are XORed withthe 8-bit literal ‘k’. The result is placedin W.

Words:

1

Cycles:1

Q Cycle Activity:

Q1

Q2

Q3

Q4

DecodeReadliteral ‘k’

Process
Data

Write to W

Example:Before Instruction
W=
After Instruction
W
=

XORLW

0AFh

B5h
1Ah

Q Cycle Activity:
Q1

Q2

Q3

Q4

DecodeReadregister ‘f’

Process
Data

No
operation

If skip:
Q1

Q2

Q3

Q4

No
operationNo
operationNo
operationNo
operation

If skip and followed by 2-word instruction:
Q1

Q2

Q3

Q4

No
operationNo
operationNo
operationNo
operationNo
operationNo
operationNo
operationNo
operation

Example:

HERE
NZERO
ZERO

Before Instruction
PC
After Instruction
If CNTPC
If CNTPC

TSTFSZ::

CNT, 1=

Address (HERE)

=
=
≠
=

00h,
Address (ZERO)
00h,
Address (NZERO)© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 347

PIC18F2455/2550/4455/4550
XORWF

Exclusive OR W with f

Syntax:XORWF

Operands:

0 ≤ f ≤ 255
d ∈ [0,1]a ∈ [0,1]

Operation:(W) .XOR. (f) → dest

Status Affected:

N, Z

Encoding:

0001

f {,d {,a}}

10da

ffff

ffff

Description:

Exclusive OR the contents of W withregister ‘f’. If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored backin the register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented andBit-Oriented Instructions in Indexed
Literal Offset Mode” for details.

Words:

1

Cycles:1

Q Cycle Activity:
Q1

Q2

Q3

Q4

DecodeReadregister ‘f’

Process
Data

Write todestination

XORWF

REG, 1, 0

Example:Before Instruction
REG
=
W
=
After Instruction
REG
=
W
=

DS39632D-page 348

AFh
B5h
1Ah
B5h

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
26.2

Extended Instruction Set

A summary of the instructions in the extended instruction set is provided in Table 26-3. Detailed descriptions
are provided in Section 26.2.2 “Extended Instruction
Set”. The opcode field descriptions in Table 26-1
(page 308) apply to both the standard and extended
PIC18 instruction sets.

In addition to the standard 75 instructions of the PIC18
instruction set, PIC18F2455/2550/4455/4550 devices
also provide an optional extension to the core CPU
functionality. The added features include eight additional instructions that augment Indirect and Indexed
Addressing operations and the implementation ofIndexed Literal Offset Addressing mode for many of thestandard PIC18 instructions.

Note:

The instruction set extension and theIndexed Literal Offset Addressing mode
were designed for optimizing applications
written in C; the user may likely never use
these instructions directly in assembler.
The syntax for these commands is provided as a reference for users who may bereviewing code that has been generated
by a compiler.

26.2.1EXTENDED INSTRUCTION SYNTAXThe additional features of the extended instruction set
are disabled by default. To enable them, users must set
the XINST Configuration bit.
The instructions in the extended set can all beclassified as literal operations, which either manipulate
the File Select Registers, or use them for Indexed
Addressing. Two of the instructions, ADDFSR and
SUBFSR, each have an additional special instantiation
for using FSR2. These versions (ADDULNK and
SUBULNK) allow for automatic return after execution.

Most of the extended instructions use indexed
arguments, using one of the File Select Registers andsome offset to specify a source or destination register.
When an argument for an instruction serves as part ofIndexed Addressing, it is enclosed in square brackets(“[ ]”). This is done to indicate that the argument is used
as an index or offset. The MPASM™ Assembler will
flag an error if it determines that an index or offset value
is not bracketed.

The extended instructions are specifically implemented
to optimize re-entrant program code (that is, code thatis recursive or that uses a software stack) written in
high-level languages, particularly C. Among otherthings, they allow users working in high-level
languages to perform certain operations on data
structures more efficiently. These include:

When the extended instruction set is enabled, brackets
are also used to indicate index arguments in byteoriented and bit-oriented instructions. This is in addition
to other changes in their syntax. For more details, see
Section 26.2.3.1 “Extended Instruction Syntax withStandard PIC18 Commands”.

• Dynamic allocation and deallocation of software
stack space when entering and leaving
subroutines• Function Pointer invocation• Software Stack Pointer manipulation• Manipulation of variables located in a software
stack

TABLE 26-3:

Note:

In the past, square brackets have beenused to denote optional arguments in the
PIC18 and earlier instruction sets. In thistext and going forward, optional
arguments are denoted by braces (“{ }”).

EXTENSIONS TO THE PIC18 INSTRUCTION SET
16-Bit Instruction Word

Mnemonic,
Operands
ADDFSRADDULNK
CALLW
MOVSF

f, k
k

MOVSS

zs, zdPUSHLkSUBFSRSUBULNKf, k
kzs, fdDescription

CyclesMSb

Add literal to FSR
Add literal to FSR2 and return
Call subroutine using WREG
Move zs (source) to 1st word
fd (destination) 2nd word
Move zs (source) to 1st word
zd (destination) 2nd word
Store literal at FSR2,
decrement FSR2
Subtract literal from FSR
Subtract literal from FSR2 andreturn© 2007 Microchip Technology Inc.

1
2
2
2

LSb

StatusAffected

1000
1000
0000
1011
ffff
1011
xxxx
1010

ffkk
11kk
0001
0zzz
ffff
1zzz
xzzz
kkkk

kkkk
kkkk
0100
zzzz
ffff
zzzz
zzzz
kkkk

None
None
None
None

1

1110
1110
0000
1110
1111
1110
1111
1110

1
2

1110
1110

1001
1001

ffkk
11kk

kkkk
kkkk

None
None

2

Preliminary

None
None

DS39632D-page 349

PIC18F2455/2550/4455/4550
26.2.2EXTENDED INSTRUCTION SETADDFSR

Add Literal to FSR

ADDULNK

Syntax:ADDFSR f, k

Syntax:ADDULNK k

Operands:

0 ≤ k ≤ 63f ∈ [ 0, 1, 2 ]Operands:

0 ≤ k ≤ 63

Operation:

FSR(f) + k → FSR(f)Status Affected:

None

Encoding:

1110

Description:

The 6-bit literal ‘k’ is added to thecontents of the FSR specified by ‘f’.

Words:

1

Cycles:1

Add Literal to FSR2 and Return

FSR2 + k → FSR2,

Operation:(TOS) → PC
Status Affected:

1000

ffkk

kkkk

None

Encoding:

1110

Description:

The 6-bit literal ‘k’ is added to thecontents of FSR2. A RETURN is thenexecuted by loading the PC with the
TOS.
The instruction takes two cycles to
execute; a NOP is performed during
the second cycle.
This may be thought of as a special
case of the ADDFSR instruction,
where f = 3 (binary ‘11’); it operates
only on FSR2.

Words:

1

Cycles:2

Q Cycle Activity:
Q1

Q2

Q3

Q4

DecodeReadliteral ‘k’

Process
Data

Write to
FSR

Example:ADDFSR

Before Instruction
FSR2
=

03FFh

After Instruction
FSR2
=

0422h

2, 23h11kk

kkkk

Q Cycle Activity:
Q1

Q2

Q3

Q4

DecodeReadliteral ‘k’

Process
Data

Write to
FSR

No
OperationNo
OperationNo
OperationNo
Operation

Example:

Note:

1000

ADDULNK 23h

Before Instruction
FSR2
=
PC
=

03FFh
0100h

After Instruction
FSR2
=
PC
=

0422h
(TOS)

All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use insymbolic addressing. If a label is used, the instruction syntax then becomes: {label} instruction argument(s).

DS39632D-page 350

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
CALLW

Subroutine Call Using WREG

MOVSF

Move Indexed to f

Syntax:CALLW

Syntax:

MOVSF [zs], fd

Operands:

None

Operands:

Operation:(PC + 2) → TOS,(W) → PCL,
(PCLATH) → PCH,
(PCLATU) → PCU

0 ≤ zs ≤ 127
0 ≤ fd ≤ 4095

Operation:((FSR2) + zs) → fd

Status Affected:

None

Status Affected:

None

Encoding:

0000

0000

0001

0100

Description

First, the return address (PC + 2) ispushed onto the return stack. Next, thecontents of W are written to PCL; theexisting value is discarded. Then thecontents of PCLATH and PCLATU arelatched into PCH and PCU,
respectively. The second cycle is
executed as a NOP instruction while the
new next instruction is fetched.
Unlike CALL, there is no option to
update W, STATUS or BSR.

Words:

1

Cycles:2

Encoding:
1st word (source)
2nd word (destin.)

1110
1111

Q1

Q2

Q3

Q4

Read
WREG

Push PC to
stack

No
operation

Words:

2

Cycles:2No
operationNo
operationNo
operationNo
operation

Q Cycle Activity:

Before Instruction
PC=
PCLATH =PCLATU =W=
After Instruction
PC
=
TOS
=
PCLATH =PCLATU =
W
=

Q1

Q3

Read
source reg

DecodeNo
operation

Writeregister ‘f’(dest)

No
operation

No dummy
read

Example:

MOVSF

Before Instruction
FSR2
Contents
of 85hREG2After Instruction
FSR2
Contents
of 85hREG2Preliminary

Q4

Determine
Determinesource addr source addr

address (HERE)
10h
00h
06h

© 2007 Microchip Technology Inc.

Q2

Decode
CALLW

001006haddress (HERE + 2)
10h
00h
06h

zzzzs
ffffd

The contents of the source register are
moved to destination register ‘fd’. The
actual address of the source register isdetermined by adding the 7-bit literal
offset ‘zs’ in the first word to the value of
FSR2. The address of the destination
register is specified by the 12-bit literal‘fd’ in the second word. Both addresses
can be anywhere in the 4096-byte data
space (000h to FFFh).
The MOVSF instruction cannot use the
PCL, TOSU, TOSH or TOSL as thedestination register.
If the resultant source address points toan indirect addressing register, thevalue returned will be 00h.

Decode

HERE

0zzz
ffff

Description:

Q Cycle Activity:

Example:

1011
ffff

[05h], REG2

=

80h

=
=

33h
11h

=

80h

=
=

33h
33h

DS39632D-page 351

PIC18F2455/2550/4455/4550
MOVSS

Move Indexed to Indexed

PUSHLStore Literal at FSR2, Decrement FSR2

Syntax:MOVSS [zs], [zd]Syntax:PUSHL kOperands:

0 ≤ zs ≤ 127
0 ≤ zd ≤ 127

Operation:((FSR2) + zs) → ((FSR2) + zd)

Status Affected:

None

Encoding:
1st word (source)
2nd word (dest.)

1110
1111

Description

1011
xxxx

1zzz
xzzz

zzzzs
zzzzd

The contents of the source register are
moved to the destination register. The
addresses of the source and destination
registers are determined by adding the
7-bit literal offsets ‘zs’ or ‘zd’,
respectively, to the value of FSR2. Bothregisters can be located anywhere in
the 4096-byte data memory space(000h to FFFh).
The MOVSS instruction cannot use the
PCL, TOSU, TOSH or TOSL as thedestination register.
If the resultant source address points toan indirect addressing register, thevalue returned will be 00h. If theresultant destination address points toan indirect addressing register, theinstruction will execute as a NOP.

Words:

2

Cycles:2

Operands:

0 ≤ k ≤ 255

Operation:k → (FSR2),
FSR2 – 1→ FSR2

Status Affected:

None

Encoding:

1111

1010

kkkk

kkkk

Description:

The 8-bit literal ‘k’ is written to the data
memory address specified by FSR2. FSR2
is decremented by ‘1’ after the operation.
This instruction allows users to push values
onto a software stack.

Words:

1

Cycles:1

Q Cycle Activity:
Q1

Q2

Q3

Q4

DecodeRead ‘k’

Processdata

Write todestination

Example:

PUSHL

08h

Before Instruction
FSR2H:FSR2L
Memory (01ECh)

=
=

01ECh
00h

After Instruction
FSR2H:FSR2L
Memory (01ECh)

=
=

01EBh
08h

Q Cycle Activity:
Q1

Q2

Q3

Q4

DecodeDetermine
Determinesource addr source addr

Readsource reg

DecodeDetermine
dest addr

Determine
dest addr

Write
to dest reg

MOVSS[05h], [06h]Example:Before Instruction
FSR2
Contents
of 85hContents
of 86hAfter Instruction
FSR2
Contents
of 85hContents
of 86hDS39632D-page 352

=

80h

=

33h

=

11h

=

80h

=

33h

=

33h

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
SUBFSR

Subtract Literal from FSR

SUBULNK

Syntax:SUBFSR f, k

Syntax:SUBULNK k

Operands:

0 ≤ k ≤ 63

Operands:

0 ≤ k ≤ 63f ∈ [ 0, 1, 2 ]Operation:

Operation:

FSRf – k → FSRf

Status Affected:

None

Encoding:

1110

Description:

The 6-bit literal ‘k’ is subtracted fromthe contents of the FSR specified by‘f’.

Words:

1

Cycles:1

FSR2 – k → FSR2
(TOS) → PC

Status Affected: None
1001

ffkk

kkkk

Encoding:

1110

Q1

Q2

Q3

Q4

DecodeReadregister ‘f’

Process
Data

Write todestination

Before Instruction
FSR2=
After Instruction
FSR2=

SUBFSR 2, 23h

1001

11kk

kkkk

Description:

The 6-bit literal ‘k’ is subtracted from thecontents of the FSR2. A RETURN is thenexecuted by loading the PC with the TOS.
The instruction takes two cycles to
execute; a NOP is performed during thesecond cycle.
This may be thought of as a special case of
the SUBFSR instruction, where f = 3 (binary‘11’); it operates only on FSR2.

Words:

1

Cycles:2

Q Cycle Activity:

Example:Subtract Literal from FSR2 and Return

Q Cycle Activity:
Q1

Q2

Q3

Q4

03FFh

DecodeReadregister ‘f’

Process
Data

Write todestination

03DCh

No
OperationNo
OperationNo
OperationNo
Operation

Example:© 2007 Microchip Technology Inc.

Preliminary

SUBULNK 23h

Before Instruction
FSR2
=
PC
=

03FFh
0100h

After Instruction
FSR2
=
PC
=

03DCh
(TOS)

DS39632D-page 353

PIC18F2455/2550/4455/4550
26.2.3Note:

BYTE-ORIENTED AND
BIT-ORIENTED INSTRUCTIONS IN
INDEXED LITERAL OFFSET MODE
Enabling the PIC18 instruction set
extension may cause legacy applications
to behave erratically or fail entirely.

In addition to eight new commands in the extended set,
enabling the extended instruction set also enables
Indexed Literal Offset Addressing mode (Section 5.6.1“Indexed Addressing with Literal Offset”). This has
a significant impact on the way that many commands ofthe standard PIC18 instruction set are interpreted.
When the extended set is disabled, addresses embedded in opcodes are treated as literal memory locations:either as a location in the Access Bank (‘a’ = 0) or in a
GPR bank designated by the BSR (‘a’ = 1). When theextended instruction set is enabled and ‘a’ = 0,
however, a file register argument of 5Fh or less isinterpreted as an offset from the pointer value in FSR2
and not as a literal address. For practical purposes, thismeans that all instructions that use the Access RAM bit
as an argument – that is, all byte-oriented and bitoriented instructions, or almost half of the core PIC18
instructions – may behave differently when theextended instruction set is enabled.
When the content of FSR2 is 00h, the boundaries of theAccess RAM are essentially remapped to their originalvalues. This may be useful in creating backward
compatible code. If this technique is used, it may benecessary to save the value of FSR2 and restore it
when moving back and forth between C and assemblyroutines in order to preserve the Stack Pointer. Users
must also keep in mind the syntax requirements of theextended instruction set (see Section 26.2.3.1“Extended Instruction Syntax with Standard PIC18
Commands”).

26.2.3.1

Extended Instruction Syntax withStandard PIC18 Commands

When the extended instruction set is enabled, the fileregister argument, ‘f’, in the standard byte-oriented andbit-oriented commands is replaced with the literal offset
value, ‘k’. As already noted, this occurs only when ‘f’ isless than or equal to 5Fh. When an offset value is used,
it must be indicated by square brackets (“[ ]”). As withthe extended instructions, the use of brackets indicatesto the compiler that the value is to be interpreted as anindex or an offset. Omitting the brackets, or using avalue greater than 5Fh within brackets, will generate anerror in the MPASM Assembler.
If the index argument is properly bracketed for Indexed
Literal Offset Addressing mode, the Access RAM
argument is never specified; it will automatically be
assumed to be ‘0’. This is in contrast to standard
operation (extended instruction set disabled) when ‘a’is set on the basis of the target address. Declaring theAccess RAM bit in this mode will also generate an error
in the MPASM Assembler.
The destination argument, ‘d’, functions as before.
In the latest versions of the MPASM assembler,
language support for the extended instruction set must
be explicitly invoked. This is done with either thecommand line option, /y, or the PE directive in thesource listing.

26.2.4CONSIDERATIONS WHEN
ENABLING THE EXTENDED
INSTRUCTION SET

It is important to note that the extensions to the instruction set may not be beneficial to all users. In particular,
users who are not writing code that uses a software
stack may not benefit from using the extensions to the
instruction set.

Although the Indexed Literal Offset Addressing modecan be very useful for dynamic stack and pointermanipulation, it can also be very annoying if a simple
arithmetic operation is carried out on the wrong
register. Users who are accustomed to the PIC18
programming must keep in mind that, when theextended instruction set is enabled, register addressesof 5Fh or less are used for Indexed Literal Offset
Addressing.

Additionally, the Indexed Literal Offset Addressing
mode may create issues with legacy applications
written to the PIC18 assembler. This is because
instructions in the legacy code may attempt to address
registers in the Access Bank below 5Fh. Since theseaddresses are interpreted as literal offsets to FSR2
when the instruction set extension is enabled, theapplication may read or write to the wrong data
addresses.

Representative examples of typical byte-oriented andbit-oriented instructions in the Indexed Literal Offset
Addressing mode are provided on the following page toshow how execution is affected. The operandconditions shown in the examples are applicable to all
instructions of these types.

When porting an application to the PIC18F2455/2550/
4455/4550, it is very important to consider the type ofcode. A large, re-entrant application that is written in ‘C’
and would benefit from efficient compilation will do wellwhen using the instruction set extensions. Legacy
applications that heavily use the Access Bank will most
likely not benefit from using the extended instruction
set.

DS39632D-page 354

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
ADD W to Indexed(Indexed Literal Offset mode)

BSF

Bit Set Indexed(Indexed Literal Offset mode)

Syntax:ADDWF

Syntax:

BSF [k], b

Operands:

0 ≤ k ≤ 95
d ∈ [0,1]

Operands:

0 ≤ f ≤ 95
0≤b≤7

Operation:(W) + ((FSR2) + k) → dest

Operation:

1 → ((FSR2) + k)<b>

Status Affected:

N, OV, C, DC, Z

Status Affected:

None

ADDWF

Encoding:[k] {,d}0010

Description:

01d0

kkkk

kkkk

The contents of W are added to thecontents of the register indicated by
FSR2, offset by the value ‘k’.
If ‘d’ is ‘0’, the result is stored in W. If ‘d’is ‘1’, the result is stored back inregister ‘f’ (default).

Encoding:

1000

bbb0

kkkk

kkkk

Description:

Bit ‘b’ of the register indicated by FSR2,
offset by the value ‘k’, is set.

Words:

1

Cycles:1

Q Cycle Activity:

Words:

1

Q1

Q2

Q3

Q4

Cycles:1

DecodeReadregister ‘f’

Process
Data

Write todestination

Q Cycle Activity:
Q1

Q2

Q3

Q4

DecodeRead ‘k’

Process
Data

Write todestination

Example:ADDWF

Before Instruction
W
OFST
FSR2
Contentsof 0A2Ch
After Instruction
W
Contentsof 0A2Ch

Example:Before Instruction
FLAG_OFSTFSR2Contentsof 0A0Ah
After Instruction
Contentsof 0A0Ah[OFST] ,0
=
=
=

17h
2Ch
0A00h

=

20h

=

37h

=

20h

BSF

[FLAG_OFST], 7
=
=

0Ah
0A00h

=

55h

=

D5h

SETF

Set Indexed(Indexed Literal Offset mode)

Syntax:SETF [k]Operands:

0 ≤ k ≤ 95

Operation:

FFh → ((FSR2) + k)

Status Affected:

None

Encoding:

0110

1000

kkkk

kkkk

Description:

The contents of the register indicated by
FSR2, offset by ‘k’, are set to FFh.

Words:

1

Cycles:1

Q Cycle Activity:
Q1

Q2

Q3

Q4

DecodeRead ‘k’

ProcessData

Writeregister

Example:SETF

Before Instruction
OFST
FSR2
Contentsof 0A2Ch
After Instruction
Contentsof 0A2Ch© 2007 Microchip Technology Inc.

Preliminary[OFST]

=
=

2Ch
0A00h

=

00h

=

FFh

DS39632D-page 355

PIC18F2455/2550/4455/4550
26.2.5SPECIAL CONSIDERATIONS WITH
MICROCHIP MPLAB® IDE TOOLSThe latest versions of Microchip’s software tools havebeen designed to fully support the extended instruction
set of the PIC18F2455/2550/4455/4550 family of
devices. This includes the MPLAB C18 C compiler,
MPASM Assembly language and MPLAB Integrated
Development Environment (IDE).
When selecting a target device for softwaredevelopment, MPLAB IDE will automatically set default
Configuration bits for that device. The default setting for
the XINST Configuration bit is ‘0’, disabling theextended instruction set and Indexed Literal Offset
Addressing mode. For proper execution of applications
developed to take advantage of the extended
instruction set, XINST must be set during
programming.

DS39632D-page 356

To develop software for the extended instruction set,
the user must enable support for the instructions andthe Indexed Addressing mode in their language tool(s).
Depending on the environment being used, this may bedone in several ways:• A menu option, or dialog box within theenvironment, that allows the user to configure thelanguage tool and its settings for the project• A command line option• A directive in the source code
These options vary between different compilers,
assemblers and development environments. Users areencouraged to review the documentation accompanying their development systems for the appropriate
information.

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
27.0

DEVELOPMENT SUPPORT

27.1

The PIC® microcontrollers are supported with a fullrange of hardware and software development tools:• Integrated Development Environment- MPLAB® IDE Software• Assemblers/Compilers/Linkers- MPASMTM Assembler- MPLAB C18 and MPLAB C30 C Compilers- MPLINKTM Object Linker/
MPLIBTM Object Librarian- MPLAB ASM30 Assembler/Linker/Library• Simulators- MPLAB SIM Software Simulator• Emulators- MPLAB ICE 2000 In-Circuit Emulator- MPLAB ICE 4000 In-Circuit Emulator• In-Circuit Debugger- MPLAB ICD 2• Device Programmers- PICSTART® Plus Development Programmer- MPLAB PM3 Device Programmer• Low-Cost Demonstration and Development
Boards and Evaluation Kits

MPLAB Integrated Development
Environment Software

The MPLAB IDE software brings an ease of softwaredevelopment previously unseen in the 8/16-bit microcontroller market. The MPLAB IDE is a Windows®
operating system-based application that contains:• A single graphical interface to all debugging tools- Simulator- Programmer (sold separately)- Emulator (sold separately)- In-Circuit Debugger (sold separately)• A full-featured editor with color-coded context• A multiple project manager• Customizable data windows with direct edit ofcontents• High-level source code debugging• Visual device initializer for easy register
initialization• Mouse over variable inspection• Drag and drop variables from source to watch
windows• Extensive on-line help
• Integration of select third party tools, such as
HI-TECH Software C Compilers and IAR
C Compilers
The MPLAB IDE allows you to:• Edit your source files (either assembly or C)• One touch assemble (or compile) and download
to PIC MCU emulator and simulator tools(automatically updates all project information)• Debug using:- Source files (assembly or C)- Mixed assembly and C- Machine code
MPLAB IDE supports multiple debugging tools in asingle development paradigm, from the cost-effective
simulators, through low-cost in-circuit debuggers, tofull-featured emulators. This eliminates the learning
curve when upgrading to tools with increased flexibility
and power.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 357

PIC18F2455/2550/4455/4550
27.2

MPASM Assembler

27.5

The MPASM Assembler is a full-featured, universal
macro assembler for all PIC MCUs.
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbolreference, absolute LST files that contain source linesand generated machine code and COFF files fordebugging.
The MPASM Assembler features include:

MPLAB ASM30 Assembler produces relocatablemachine code from symbolic assembly language for
dsPIC30F devices. MPLAB C30 C Compiler uses theassembler to produce its object file. The assembler
generates relocatable object files that can then bearchived or linked with other relocatable object files andarchives to create an executable file. Notable featuresof the assembler include:• Support for the entire dsPIC30F instruction set• Support for fixed-point and floating-point data
• Command line interface• Rich directive set• Flexible macro language• MPLAB IDE compatibility• Integration into MPLAB IDE projects• User-defined macros to streamline
assembly code
• Conditional assembly for multi-purpose
source files• Directives that allow complete control over theassembly process

27.6
27.3

MPLAB C18 and MPLAB C30
C Compilers

The MPLAB C18 and MPLAB C30 Code Development
Systems are complete ANSI C compilers for
Microchip’s PIC18 family of microcontrollers anddsPIC30F family of digital signal controllers. These
compilers provide powerful integration capabilities,
superior code optimization and ease of use not foundwith other compilers.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.

27.4

MPLAB ASM30 Assembler, Linker
and Librarian

MPLINK Object Linker/
MPLIB Object Librarian

The MPLINK Object Linker combines relocatableobjects created by the MPASM Assembler and the
MPLAB C18 C Compiler. It can link relocatable objects
from precompiled libraries, using directives from alinker script.

MPLAB SIM Software Simulator

The MPLAB SIM Software Simulator allows codedevelopment in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instructionlevel. On any given instruction, the data areas can be
examined or modified and stimuli can be applied froma comprehensive stimulus controller. Registers can belogged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power ofthe simulator to record and track program execution,actions on I/O, as well as internal registers.
The MPLAB SIM Software Simulator fully supports
symbolic debugging using the MPLAB C18 and
MPLAB C30 C Compilers, and the MPASM and
MPLAB ASM30 Assemblers. The software simulator
offers the flexibility to develop and debug code outsideof the laboratory environment, making it an excellent,
economical software development tool.

The MPLIB Object Librarian manages the creation andmodification of library files of precompiled code. Whena routine from a library is called from a source file, only
the modules that contain that routine will be linked inwith the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:• Efficient linking of single libraries instead of manysmaller files• Enhanced code maintainability by grouping
related modules together• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction

DS39632D-page 358

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
27.7

MPLAB ICE 2000
High-Performance
In-Circuit Emulator

27.9

The MPLAB ICE 2000 In-Circuit Emulator is intended
to provide the product development engineer with acomplete microcontroller design tool set for PIC microcontrollers. Software control of the MPLAB ICE 2000
In-Circuit Emulator is advanced by the MPLAB Integrated Development Environment, which allows
editing, building, downloading and source debugging
from a single environment.
The MPLAB ICE 2000 is a full-featured emulator
system with enhanced trace, trigger and data monitoring features. Interchangeable processor modules allow
the system to be easily reconfigured for emulation ofdifferent processors. The architecture of the MPLAB
ICE 2000 In-Circuit Emulator allows expansion to
support new PIC microcontrollers.
The MPLAB ICE 2000 In-Circuit Emulator system has
been designed as a real-time emulation system withadvanced features that are typically found on more
expensive development tools. The PC platform andMicrosoft® Windows® 32-bit operating system werechosen to best make these features available in a
simple, unified application.

27.8

MPLAB ICE 4000
High-Performance
In-Circuit Emulator

The MPLAB ICE 4000 In-Circuit Emulator is intended toprovide the product development engineer with acomplete microcontroller design tool set for high-end
PIC MCUs and dsPIC DSCs. Software control of the
MPLAB ICE 4000 In-Circuit Emulator is provided by the
MPLAB Integrated Development Environment, whichallows editing, building, downloading and source
debugging from a single environment.

MPLAB ICD 2 In-Circuit Debugger

Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a
powerful, low-cost, run-time development tool,connecting to the host PC via an RS-232 or high-speed
USB interface. This tool is based on the Flash PIC
MCUs and can be used to develop for these and other
PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes
the in-circuit debugging capability built into the Flashdevices. This feature, along with Microchip’s In-Circuit
Serial ProgrammingTM (ICSPTM) protocol, offers costeffective, in-circuit Flash debugging from the graphicaluser interface of the MPLAB Integrated Development
Environment. This enables a designer to develop anddebug source code by setting breakpoints, single stepping and watching variables, and CPU status andperipheral registers. Running at full speed enables
testing hardware and applications in real time. MPLAB
ICD 2 also serves as a development programmer for
selected PIC devices.

27.10 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display(128 x 64) for menus and error messages and a modular, detachable socket assembly to support various
package types. The ICSP™ cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications andoptimized algorithms for quick programming of large
memory devices and incorporates an SD/MMC card forfile storage and secure data applications.

The MPLAB ICE 4000 is a premium emulator system,
providing the features of MPLAB ICE 2000, but withincreased emulation memory and high-speed performance for dsPIC30F and PIC18XXXX devices. Its
advanced emulator features include complex triggeringand timing, and up to 2 Mb of emulation memory.
The MPLAB ICE 4000 In-Circuit Emulator system has
been designed as a real-time emulation system withadvanced features that are typically found on more
expensive development tools. The PC platform andMicrosoft Windows 32-bit operating system werechosen to best make these features available in a
simple, unified application.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 359

PIC18F2455/2550/4455/4550
27.11 PICSTART Plus Development
Programmer

27.12 Demonstration, Development and
Evaluation Boards

The PICSTART Plus Development Programmer is aneasy-to-use, low-cost, prototype programmer. It
connects to the PC via a COM (RS-232) port. MPLAB
Integrated Development Environment software makesusing the programmer simple and efficient. The
PICSTART Plus Development Programmer supports
most PIC devices in DIP packages up to 40 pins.
Larger pin count devices, such as the PIC16C92X andPIC17C76X, may be supported with an adapter socket.
The PICSTART Plus Development Programmer is CE
compliant.

A wide variety of demonstration, development andevaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully functional systems. Most boards include prototyping areas foradding custom circuitry and provide application firmware
and source code for examination and modification.
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
The demonstration and development boards can beused in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits, Microchip
has a line of evaluation kits and demonstration software
for analog filter design, KEELOQ® security ICs, CAN,
IrDA®, PowerSmart® battery management, SEEVAL®
evaluation system, Sigma-Delta ADC, flow ratesensing, plus many more.
Check the Microchip web page (www.microchip.com)
and the latest “Product Selector Guide” (DS00148) forthe complete list of demonstration, development andevaluation kits.

DS39632D-page 360

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
28.0

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings(†)
Ambient temperature under bias.............................................................................................................. .-40°C to +85°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on any pin with respect to VSS (except VDD, MCLR and RA4) .......................................... -0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V
Voltage on MCLR with respect to VSS (Note 2) ......................................................................................... 0V to +13.25V
Total power dissipation (Note 1) ...............................................................................................................................1.0W
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin ..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................... ±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) .............................................................................................................. ±20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by all ports .......................................................................................................................200 mA
Maximum current sourced by all ports ..................................................................................................................200 mA
Note 1: Power dissipation is calculated as follows:
Pdis = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOL x IOL)
2: Voltage spikes below VSS at the MCLR/VPP/RE3 pin, inducing currents greater than 80 mA, may cause
latch-up. Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR/VPP/
RE3 pin, rather than pulling this pin directly to VSS.

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to thedevice. This is a stress rating only and functional operation of the device at those or any other conditions above thoseindicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions forextended periods may affect device reliability.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 361

PIC18F2455/2550/4455/4550
FIGURE 28-1:

PIC18F2455/2550/4455/4550 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)

6.0V
5.5V

Voltage

5.0V

PIC18FX455/X550

4.5V
4.2V

4.0V
3.5V
3.0V
2.5V
2.0V

48 MHzFrequency

FIGURE 28-2:

PIC18LF2455/2550/4455/4550 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
6.0V
5.5V
5.0V

PIC18LFX455/X550

4.5V
4.2V

Voltage

4.0V
3.5V
3.0V
2.5V
2.0V

4 MHz

16 MHz25 MHz48 MHzFrequency
Note: VDDAPPMIN is the minimum voltage of the PIC® device in the application.

DS39632D-page 362

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
28.1

DC Characteristics:

Supply Voltage
PIC18F2455/2550/4455/4550 (Industrial)
PIC18LF2455/2550/4455/4550 (Industrial)

PIC18LF2455/2550/4455/4550(Industrial)

Standard Operating Conditions (unless otherwise stated)
Operating temperature-40°C ≤ TA ≤ +85°C for industrial

PIC18F2455/2550/4455/4550(Industrial)

Standard Operating Conditions (unless otherwise stated)
Operating temperature-40°C ≤ TA ≤ +85°C for industrial

Param
No.

SymbolMin

Typ

Max Units

D001

VDD

2.0

—

5.5

V

EC, HS, XT and Internal Oscillator modes

3.0

—

5.5

V

HSPLL, XTPLL, ECPIO and ECPLL
Oscillator modes

Characteristic
Supply Voltage

D002

VDR

RAM Data Retention
Voltage(1)

1.5

—

—

V

D003

VPOR

VDD Start Voltage
to ensure internal Power-on
Reset signal

—

—

0.7

V

D004

SVDD

VDD Rise Rateto ensure internal Power-on
Reset signal

0.05

—

—

D005

VBOR

Brown-out Reset Voltage

Legend:Note 1:

Conditions

See Section 4.3 “Power-on Reset (POR)”
for details

V/ms See Section 4.3 “Power-on Reset (POR)”
for details

BORV1:BORV0 = 11

2.00

2.05

2.16

V

BORV1:BORV0 = 10

2.65

2.79

2.93

V

BORV1:BORV0 = 01

4.11

4.33

4.55

V

BORV1:BORV0 = 00

4.36

4.59

4.82

V

Shading of rows is to assist in readability of the table.
This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM data.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 363

PIC18F2455/2550/4455/4550
28.2

DC Characteristics:

Power-Down and Supply Current
PIC18F2455/2550/4455/4550 (Industrial)
PIC18LF2455/2550/4455/4550 (Industrial)

PIC18LF2455/2550/4455/4550(Industrial)

Standard Operating Conditions (unless otherwise stated)
Operating temperature-40°C ≤ TA ≤ +85°C for industrial

PIC18F2455/2550/4455/4550(Industrial)

Standard Operating Conditions (unless otherwise stated)
Operating temperature-40°C ≤ TA ≤ +85°C for industrial

Param
No.

Device

Typ

Max

Units

Conditions

Power-Down Current (IPD)(1)
PIC18LFX455/X550

PIC18LFX455/X550

All devices

Legend:Note 1:
2:

3:
4:

0.1

0.95

μA

-40°C

0.1

1.0

μA

+25°C

0.2

5

μA

+85°C

0.1

1.4

μA

-40°C

0.1

2

μA

+25°C

0.3

8

μA

+85°C

0.1

1.9

μA

-40°C

0.1

2.0

μA

+25°C

0.4

15

μA

+85°C

VDD = 2.0V
(Sleep mode)

VDD = 3.0V
(Sleep mode)

VDD = 5.0V
(Sleep mode)

TBD = To Be Determined. Shading of rows is to assist in readability of the table.
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured
with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features thatadd delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin
loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also havean impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD or VSS;MCLR = VDD; WDT enabled/disabled as specified.
Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended
temperature crystals are available at a much higher cost.
BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will beless than the sum of both specifications.

DS39632D-page 364

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
28.2

DC Characteristics:

Power-Down and Supply Current
PIC18F2455/2550/4455/4550 (Industrial)
PIC18LF2455/2550/4455/4550 (Industrial) (Continued)

PIC18LF2455/2550/4455/4550(Industrial)

Standard Operating Conditions (unless otherwise stated)
Operating temperature-40°C ≤ TA ≤ +85°C for industrial

PIC18F2455/2550/4455/4550(Industrial)

Standard Operating Conditions (unless otherwise stated)
Operating temperature-40°C ≤ TA ≤ +85°C for industrial

Param
No.

Device

Typ

Max

Units

Conditions

15

32

μA

-40°C

15

30

μA

+25°C

Supply Current (IDD)(2)
PIC18LFX455/X550

PIC18LFX455/X550

-40°C

35

60

μA

+25°C

57

μA

+85°C

μA

-40°C

90

160

μA

+25°C

80

152

μA

+85°C

PIC18LFX455/X550 0.33

1

mA

-40°C

0.33

1

mA

+25°C

0.33

1

mA

+85°C

0.6

1.3

mA

-40°C

0.6

1.2

mA

+25°C

0.6

1.1

mA

+85°C

1.1

2.3

mA

-40°C

1.1

2.2

mA

+25°C

1.0

2.1

mA

+85°C

0.8

2.1

mA

-40°C

0.8

2.0

mA

+25°C
+85°C

PIC18LFX455/X550

PIC18LFX455/X550

All devices

4:

+85°C

μA

168

All devices

3:

μA

30

PIC18LFX455/X550

2:

29
63

105

All devices

Legend:Note 1:

15
40

0.8

1.9

mA

1.3

3.0

mA

-40°C

1.3

3.0

mA

+25°C
+85°C

1.3

3.0

mA

2.5

5.3

mA

-40°C

2.5

5.0

mA

+25°C

2.5

4.8

mA

+85°C

VDD = 2.0V

VDD = 3.0V

FOSC = 31 kHz(RC_RUN mode,
INTRC source)

VDD = 5.0V

VDD = 2.0V

VDD = 3.0V

FOSC = 1 MHz(RC_RUN mode,
INTOSC source)

VDD = 5.0V

VDD = 2.0V

VDD = 3.0V

FOSC = 4 MHz(RC_RUN mode,
INTOSC source)

VDD = 5.0V

TBD = To Be Determined. Shading of rows is to assist in readability of the table.
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured
with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features thatadd delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin
loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also havean impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD or VSS;MCLR = VDD; WDT enabled/disabled as specified.
Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended
temperature crystals are available at a much higher cost.
BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will beless than the sum of both specifications.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 365

PIC18F2455/2550/4455/4550
28.2

DC Characteristics:

Power-Down and Supply Current
PIC18F2455/2550/4455/4550 (Industrial)
PIC18LF2455/2550/4455/4550 (Industrial) (Continued)

PIC18LF2455/2550/4455/4550(Industrial)

Standard Operating Conditions (unless otherwise stated)
Operating temperature-40°C ≤ TA ≤ +85°C for industrial

PIC18F2455/2550/4455/4550(Industrial)

Standard Operating Conditions (unless otherwise stated)
Operating temperature-40°C ≤ TA ≤ +85°C for industrial

Param
No.

Device

Typ

Max

Units

Conditions

Supply Current (IDD)(2)
PIC18LFX455/X550

PIC18LFX455/X550

All devices

PIC18LFX455/X550

PIC18LFX455/X550

4:

-40°C

μA

+25°C

3.6

11

μA

+85°C

4.5

11

μA

-40°C

4.8

11

μA

+25°C

5.8

15

μA

+85°C

9.2

16

μA

-40°C

9.8

16

μA

+25°C

11.4

36

μA

+85°C

165

350

μA

-40°C

175

350

μA

+25°C
+85°C

190

350

μA

250

500

μA

-40°C

270

500

μA

+25°C

500

μA

+85°C

1

mA

-40°C

0.52

1

mA

+25°C

0.55

1

mA

+85°C

340

500

μA

-40°C

All devices

3:

μA

290

PIC18LFX455/X550

2:

8
8

All devices 0.50

PIC18LFX455/X550

Legend:Note 1:

2.9
3.1

350

500

μA

+25°C

360

500

μA

+85°C

520

900

μA

-40°C

540

900

μA

+25°C

580

900

μA

+85°C

1.0

1.6

mA

-40°C

1.1

1.5

mA

+25°C

1.1

1.4

mA

+85°C

VDD = 2.0V

VDD = 3.0V

FOSC = 31 kHz(RC_IDLE mode,
INTRC source)

VDD = 5.0V

VDD = 2.0V

VDD = 3.0V

FOSC = 1 MHz(RC_IDLE mode,
INTOSC source)

VDD = 5.0V

VDD = 2.0V

VDD = 3.0V

FOSC = 4 MHz(RC_IDLE mode,
INTOSC source)

VDD = 5.0V

TBD = To Be Determined. Shading of rows is to assist in readability of the table.
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured
with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features thatadd delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin
loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also havean impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD or VSS;MCLR = VDD; WDT enabled/disabled as specified.
Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended
temperature crystals are available at a much higher cost.
BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will beless than the sum of both specifications.

DS39632D-page 366

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
28.2

DC Characteristics:

Power-Down and Supply Current
PIC18F2455/2550/4455/4550 (Industrial)
PIC18LF2455/2550/4455/4550 (Industrial) (Continued)

PIC18LF2455/2550/4455/4550(Industrial)

Standard Operating Conditions (unless otherwise stated)
Operating temperature-40°C ≤ TA ≤ +85°C for industrial

PIC18F2455/2550/4455/4550(Industrial)

Standard Operating Conditions (unless otherwise stated)
Operating temperature-40°C ≤ TA ≤ +85°C for industrial

Param
No.

Device

Typ

Max

Units

Conditions

250

500

μA

-40°C

250

500

μA

+25°C

250

500

μA

+85°C

550

650

μA

-40°C

480

650

μA

+25°C

460

650

μA

+85°C

1.2

1.6

mA

-40°C

1.1

1.5

mA

+25°C
+85°C

Supply Current (IDD)(2)
PIC18LFX455/X550

PIC18LFX455/X550

All devices

1.0

1.4

mA

PIC18LFX455/X550 0.74

2.0

mA

-40°C

0.74

2.0

mA

+25°C

0.74

2.0

mA

+85°C

1.3

3.0

mA

-40°C

1.3

3.0

mA

+25°C

1.3

3.0

mA

+85°C

2.7

6.0

mA

-40°C

2.6

6.0

mA

+25°C

2.5

6.0

mA

+85°C

15

35

mA

-40°C

16

35

mA

+25°C

16

35

mA

+85°C

21

40

mA

-40°C

21

40

mA

+25°C

21

40

mA

+85°C

20

40

mA

-40°C

20

40

mA

+25°C

20

40

mA

+85°C

25

50

mA

-40°C

25

50

mA

+25°C

25

50

mA

+85°C

PIC18LFX455/X550

All devices

All devices

All devices

All devices

All devices

Legend:Note 1:
2:

3:
4:

VDD = 2.0V

VDD = 3.0V

FOSC = 1 MHZ(PRI_RUN,
EC oscillator)

VDD = 5.0V

VDD = 2.0V

VDD = 3.0V

FOSC = 4 MHz(PRI_RUN,
EC oscillator)

VDD = 5.0V

VDD = 4.2V
FOSC = 40 MHZ(PRI_RUN,
EC oscillator)
VDD = 5.0V

VDD = 4.2V
FOSC = 48 MHZ(PRI_RUN,
EC oscillator)
VDD = 5.0V

TBD = To Be Determined. Shading of rows is to assist in readability of the table.
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured
with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features thatadd delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin
loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also havean impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD or VSS;MCLR = VDD; WDT enabled/disabled as specified.
Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended
temperature crystals are available at a much higher cost.
BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will beless than the sum of both specifications.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 367

PIC18F2455/2550/4455/4550
28.2

DC Characteristics:

Power-Down and Supply Current
PIC18F2455/2550/4455/4550 (Industrial)
PIC18LF2455/2550/4455/4550 (Industrial) (Continued)

PIC18LF2455/2550/4455/4550(Industrial)

Standard Operating Conditions (unless otherwise stated)
Operating temperature-40°C ≤ TA ≤ +85°C for industrial

PIC18F2455/2550/4455/4550(Industrial)

Standard Operating Conditions (unless otherwise stated)
Operating temperature-40°C ≤ TA ≤ +85°C for industrial

Param
No.

Device

Typ

Max

Units

Conditions

65

130

μA

-40°C

65

120

μA

+25°C

70

115

μA

+85°C

120

270

μA

-40°C

120

250

μA

+25°C

130

240

μA

+85°C

230

480

μA

-40°C

Supply Current (IDD)(2)
PIC18LFX455/X550

PIC18LFX455/X550

All devices

PIC18LFX455/X550

PIC18LFX455/X550

All devices

All devices

All devices

All devices

All devices

Legend:Note 1:
2:

3:
4:

240

450

μA

+25°C

250

430

μA

+85°C

255

475

μA

-40°C

260

450

μA

+25°C

270

430

μA

+85°C

420

900

μA

-40°C

430

850

μA

+25°C

450

810

μA

+85°C

0.9

1.5

mA

-40°C

0.9

1.4

mA

+25°C

0.9

1.3

mA

+85°C

6.0

16

mA

-40°C

6.2

16

mA

+25°C

6.6

16

mA

+85°C

8.1

18

mA

-40°C

8.3

18

mA

+25°C

9.0

18

mA

+85°C

8.0

18

mA

-40°C

8.1

18

mA

+25°C

8.2

18

mA

+85°C

9.8

21

mA

-40°C

10.0

21

mA

+25°C

10.5

21

mA

+85°C

VDD = 2.0V

VDD = 3.0V

FOSC = 1 MHz(PRI_IDLE mode,
EC oscillator)

VDD = 5.0V

VDD = 2.0V

VDD = 3.0V

FOSC = 4 MHz(PRI_IDLE mode,
EC oscillator)

VDD = 5.0V

VDD = 4.2V
FOSC = 40 MHz(PRI_IDLE mode,
EC oscillator)
VDD = 5.0V

VDD = 4.2V
FOSC = 48 MHz(PRI_IDLE mode,
EC oscillator)
VDD = 5.0V

TBD = To Be Determined. Shading of rows is to assist in readability of the table.
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured
with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features thatadd delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin
loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also havean impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD or VSS;MCLR = VDD; WDT enabled/disabled as specified.
Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended
temperature crystals are available at a much higher cost.
BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will beless than the sum of both specifications.

DS39632D-page 368

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
28.2

DC Characteristics:

Power-Down and Supply Current
PIC18F2455/2550/4455/4550 (Industrial)
PIC18LF2455/2550/4455/4550 (Industrial) (Continued)

PIC18LF2455/2550/4455/4550(Industrial)

Standard Operating Conditions (unless otherwise stated)
Operating temperature-40°C ≤ TA ≤ +85°C for industrial

PIC18F2455/2550/4455/4550(Industrial)

Standard Operating Conditions (unless otherwise stated)
Operating temperature-40°C ≤ TA ≤ +85°C for industrial

Param
No.

Device

Typ

Max

Units

Conditions

14

40

μA

-40°C

15

40

μA

+25°C

16

40

μA

+85°C

40

74

μA

-40°C

35

70

μA

+25°C

31

67

μA

+85°C

Supply Current (IDD)(2)
PIC18LFX455/X550

PIC18LFX455/X550

All devices

PIC18LFX455/X550

PIC18LFX455/X550

All devices

Legend:Note 1:
2:

3:
4:

99

150

μA

-40°C

81

150

μA

+25°C
+85°C

75

150

μA

2.5

12

μA

-40°C

3.7

12

μA

+25°C

4.5

12

μA

+85°C

5.0

15

μA

-40°C

5.4

15

μA

+25°C

6.3

15

μA

+85°C

8.5

25

μA

-40°C

9.0

25

μA

+25°C

10.5

36

μA

+85°C

VDD = 2.0V

VDD = 3.0V

FOSC = 32 kHz(3)(SEC_RUN mode,
Timer1 as clock)

VDD = 5.0V

VDD = 2.0V

VDD = 3.0V

FOSC = 32 kHz(3)(SEC_IDLE mode,
Timer1 as clock)

VDD = 5.0V

TBD = To Be Determined. Shading of rows is to assist in readability of the table.
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured
with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features thatadd delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin
loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also havean impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD or VSS;MCLR = VDD; WDT enabled/disabled as specified.
Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended
temperature crystals are available at a much higher cost.
BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will beless than the sum of both specifications.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 369

PIC18F2455/2550/4455/4550
28.2

DC Characteristics:

Power-Down and Supply Current
PIC18F2455/2550/4455/4550 (Industrial)
PIC18LF2455/2550/4455/4550 (Industrial) (Continued)

PIC18LF2455/2550/4455/4550(Industrial)

Standard Operating Conditions (unless otherwise stated)
Operating temperature-40°C ≤ TA ≤ +85°C for industrial

PIC18F2455/2550/4455/4550(Industrial)

Standard Operating Conditions (unless otherwise stated)
Operating temperature-40°C ≤ TA ≤ +85°C for industrial

Param
No.
D022
(ΔIWDT)

D022A(ΔIBOR)

DeviceWatchdog Timer

Brown-out Reset(4)High/Low-Voltage
Detect(4)Timer1 Oscillator

D025(ΔIOSCB)

A/D Converter

D026(ΔIAD)

2:

3:
4:

Max

Units

Conditions

Module Differential Currents (ΔIWDT, ΔIBOR, ΔILVD, ΔIOSCB, ΔIAD)

D022B(ΔILVD)

Legend:Note 1:

Typ

1.3

3.8

μA

-40°C

1.4

3.8

μA

+25°C

2.0

3.8

μA

+85°C

1.9

4.6

μA

-40°C

2.0

4.6

μA

+25°C

2.8

4.6

μA

+85°C

4.0

10

μA

-40°C

5.5

10

μA

+25°C

VDD = 2.0V

VDD = 3.0V

VDD = 5.0V

5.6

10

μA

+85°C

35

40

μA

-40°C to +85°C

40

45

μA

-40°C to +85°C

0

2

μA

-40°C to +85°C

22

38

μA

-40°C to +85°C

VDD = 2.0V

25

40

μA

-40°C to +85°C

VDD = 3.0V

29

45

μA

-40°C to +85°C

VDD = 5.0V

2.1

4.5

μA

-40°C

1.8

4.5

μA

+25°C

2.1

4.5

μA

+85°C

2.2

6.0

μA

-40°C

2.6

6.0

μA

+25°C

2.9

6.0

μA

+85°C

VDD = 3.0V
VDD = 5.0V

Sleep mode,
BOREN1:BOREN0 = 10

VDD = 2.0V

32 kHz on Timer1(3)VDD = 3.0V

32 kHz on Timer1(3)VDD = 5.0V

32 kHz on Timer1(3)

3.0

8.0

μA

-40°C

3.2

8.0

μA

+25°C

3.4

8.0

μA

+85°C

1.0

2.0

μA

-40°C to +85°C

VDD = 2.0V

1.0

2.0

μA

-40°C to +85°C

VDD = 3.0V

1.0

2.0

μA

-40°C to +85°C

VDD = 5.0V

A/D on, not converting

TBD = To Be Determined. Shading of rows is to assist in readability of the table.
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured
with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features thatadd delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin
loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also havean impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD or VSS;MCLR = VDD; WDT enabled/disabled as specified.
Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended
temperature crystals are available at a much higher cost.
BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will beless than the sum of both specifications.

DS39632D-page 370

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
28.2

DC Characteristics:

Power-Down and Supply Current
PIC18F2455/2550/4455/4550 (Industrial)
PIC18LF2455/2550/4455/4550 (Industrial) (Continued)

PIC18LF2455/2550/4455/4550(Industrial)

Standard Operating Conditions (unless otherwise stated)
Operating temperature-40°C ≤ TA ≤ +85°C for industrial

PIC18F2455/2550/4455/4550(Industrial)

Standard Operating Conditions (unless otherwise stated)
Operating temperature-40°C ≤ TA ≤ +85°C for industrial

Param
No.

Device

Typ

Max

Units

Conditions

USB and Related Module Differential Currents (ΔIUSBx, ΔIPLL, ΔIUREG)
ΔIUSBxΔIPLL
ΔIUREG
Legend:Note 1:
2:

3:
4:

USB Module8with On-Chip Transceiver TBD

TBD

mA

+25°C

VDD = 3.3V

TBD

mA

+25°C

VDD = 5.0V

96 MHz PLL 1.2(Oscillator Module) TBD

TBD

mA

+25°C

VDD = 3.3V

TBD

TBD

+25°C

VDD = 5.0V

TBD

μA

+25°C

VDD = 5.0V

USB Internal Voltage
Regulator

80

TBD = To Be Determined. Shading of rows is to assist in readability of the table.
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured
with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features thatadd delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin
loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also havean impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD or VSS;MCLR = VDD; WDT enabled/disabled as specified.
Standard low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended
temperature crystals are available at a much higher cost.
BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will beless than the sum of both specifications.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 371

PIC18F2455/2550/4455/4550
28.3

DC Characteristics: PIC18F2455/2550/4455/4550 (Industrial)
PIC18LF2455/2550/4455/4550 (Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial

DC CHARACTERISTICS
Param
SymbolNo.
VIL

Characteristic

Min

Max

Units

Conditions

VSS

0.15 VDDV

VDD < 4.5V

—

0.8

V

4.5V ≤ VDD ≤ 5.5V

VSS
VSS

0.2 VDD
0.3 VDDV
V

Input Low Voltage
I/O ports (except RC4/RC5 in
USB mode):

D030

with TTL buffer

D030A
D031

with Schmitt Trigger buffer
RC3 and RC4

D032

MCLR

VSS

0.2 VDDV

D032A

OSC1 and T1OSI

VSS

0.3 VDDV

XT, HS,HSPLL modes(1)

D033

OSC1

VSS

0.2 VDDV

EC mode(1)

VILU

D+/D- input

—

0.8

V

VDD = 4.35V,
USB suspended(5)VIH

Input High Voltage

0.25 VDD + 0.8V

VDDV

VDD < 4.5V

2.0

VDD

V

4.5V ≤ VDD ≤ 5.5V

0.8 VDD
0.7 VDD

VDD
VDD

V
V

MCLR

0.8 VDD

VDD

V

D042A

OSC1 and T1OSI

0.7 VDD

VDD

V

XT, HS,HSPLL modes(1)

D043

OSC1

0.8 VDD

VDD

V

EC mode(1)

2.4

—

V

VDD = 4.35V,
USB suspended(5)I/O ports

—

±1

μA

VSS ≤ VPIN ≤ VDD,
Pin at high-impedance

D061

MCLR

—

±5

μA

Vss ≤ VPIN ≤ VDD

D063

OSC1

—

±5

μA

Vss ≤ VPIN ≤ VDD

50

400

μA

VDD = 5V, VPIN = VSS

I/O ports (except RC4/RC5 in
USB mode):D040

with TTL buffer

D040A
D041

with Schmitt Trigger buffer
RC3 and RC4

D042

VIHU

D+/D- input

IIL

Input Leakage Current(2,3)

D060

D070
Note 1:
2:

3:
4:
5:

IPU

Weak Pull-up Current

IPURB

PORTB weak pull-up current

In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the
PIC® device be driven with an external clock while in RC mode.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
Negative current is defined as current sourced by the pin.
Parameter is characterized but not tested.
D+ parameters per USB Specification 2.0.

DS39632D-page 372

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
28.3

DC Characteristics: PIC18F2455/2550/4455/4550 (Industrial)
PIC18LF2455/2550/4455/4550 (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial

DC CHARACTERISTICS
Param
SymbolNo.
VOL

Characteristic

Min

Max

Units

Conditions

Output Low Voltage

D080

I/O ports (except RC4/RC5 in
USB mode)

—

0.6

V

IOL = 8.5 mA, VDD = 4.5V,-40°C to +85°C

D083

OSC2/CLKO(EC, ECIO modes)

—

0.6

V

IOL = 1.6 mA, VDD = 4.5V,-40°C to +85°C

VOLU

D+/D- out

—

0.3

VOH

Output High Voltage(3)VDD = 4.35V,
USB suspended(5)D090

I/O ports (except RC4/RC5 in
USB mode)

VDD – 0.7—

V

IOH = -3.0 mA, VDD = 4.5V,-40°C to +85°C

D092

OSC2/CLKO(EC, ECIO, ECPIO modes)

VDD – 0.7—

V

IOH = -1.3 mA, VDD = 4.5V,-40°C to +85°C

2.8

3.6

V

VDD = 4.35V,
USB suspended(5)D100(4) COSC2 OSC2 pin

—

15

pF

In XT and HS modes
when external clock isused to drive OSC1

D101

CIO

All I/O pins and OSC2
(in RC mode)

—

50

pF

To meet the AC Timing
Specifications

D102

CB

SCL, SDA

—

400

pF

I2C™ Specification

VOHU

D+/D- out
Capacitive Loading Specs
on Output Pins

Note 1:
2:

3:
4:
5:

In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the
PIC® device be driven with an external clock while in RC mode.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
Negative current is defined as current sourced by the pin.
Parameter is characterized but not tested.
D+ parameters per USB Specification 2.0.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 373

PIC18F2455/2550/4455/4550
TABLE 28-1:

MEMORY PROGRAMMING REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial

DC Characteristics
Param
No.

Sym

Characteristic

Min

Typ†

Max

Units

Conditions

Internal Program Memory
Programming Specifications(1)
D110

VPP

Voltage on MCLR/VPP/RE3 pin

9.00

—

13.25

V

D113

IDDP

Supply Current during
Programming

—

—

10

mA

D120

ED

Byte Endurance

100K

1M

—

E/W -40°C to +85°C

D121

VDRW

VDD for Read/Write

VMIN

—

5.5

V

(Note 3)

Data EEPROM Memory
Using EECON to read/write
VMIN = Minimum operating
voltage

D122

TDEW

Erase/Write Cycle Time

—

4

—

ms

D123

TRETD Characteristic Retention

40

—

—

Year Provided no otherspecifications are violated

D124

TREF

1M

10M

—

E/W -40°C to +85°C

D130

EP

Cell Endurance

10K

100K

—

E/W -40°C to +85°C

D131

VPR

VDD for Read

VMIN

—

5.5

V

VMIN = Minimum operating
voltage

D132

VIE

VDD for Block Erase

4.5

—

5.5

V

Using ICSP™ port

D132A VIW

VDD for Externally Timed Eraseor Write

4.5

—

5.5

V

Using ICSP port

D132B VPEW

VDD for Self-Timed Write

VMIN

—

5.5

V

VMIN = Minimum operating
voltage

D133

TIE

ICSP Block Erase Cycle Time

—

4

—

ms

VDD > 4.5V

D133A

TIW

ICSP Erase or Write Cycle Time(externally timed)

1

—

—

ms

VDD > 4.5V

Number of Total Erase/Write
Cycles before Refresh(2)Program Flash Memory

D133A TIW
D134

Self-Timed Write Cycle Time

TRETD Characteristic Retention

—

2

—

ms

40

100

—

Year Provided no otherspecifications are violated† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: These specifications are for programming the on-chip program memory through the use of table write
instructions.
2: Refer to Section 7.7 “Using the Data EEPROM” for a more detailed discussion on data EEPROM
endurance.
3: Required only if Single-Supply Programming is disabled.

DS39632D-page 374

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
TABLE 28-2:

COMPARATOR SPECIFICATIONS

Operating Conditions: 3.0V < VDD < 5.5V, -40°C < TA < +85°C (unless otherwise stated)
Param
No.

Sym

Characteristics

Min

Typ

Max

Units

D300

VIOFF

Input Offset Voltage

—

±5.0

±10

mV

D301

VICM

Input Common Mode Voltage*

0—

VDD – 1.5

V

Comments

D302

CMRR

Common Mode Rejection Ratio*

55

—

—

dB

300

TRESP

Response Time*(1)

—

150

400

ns

PIC18FXXXX

—

150

600

ns

PIC18LFXXXX,VDD = 2.0V

—

—

10

μs

300A
301
*
Note 1:

TMC2OV

Comparator Mode Change to
Output Valid*

These parameters are characterized but not tested.
Response time measured with one comparator input at (VDD – 1.5)/2, while the other input transitions
from VSS to VDD.

TABLE 28-3:

VOLTAGE REFERENCE SPECIFICATIONS

Operating Conditions: 3.0V < VDD < 5.5V, -40°C < TA < +85°C (unless otherwise stated)
Param
No.

Sym

Characteristics

Min

Typ

Max

Units

Comments

D310

VRES

Resolution

VDD/24—

VDD/32

LSb

D311

VRAA

Absolute Accuracy

—
—

1/4
—

1
1/2

LSb
LSb

D312

VRUR

Unit Resistor Value (R)*

—

2k

—

Ω

310

TSET

Settling Time*(1)

—

—

10

μs

*
Note 1:

These parameters are characterized but not tested.
Settling time measured while CVRR = 1 and CVR3:CVR0 transitions from ‘0000’ to ‘1111’.

© 2007 Microchip Technology Inc.

Preliminary

Low Range (CVRR = 1)
High Range (CVRR = 0)DS39632D-page 375

PIC18F2455/2550/4455/4550
TABLE 28-4:

USB MODULE SPECIFICATIONS

Operating Conditions: -40°C < TA < +85°C (unless otherwise stated).
Param
No.

Sym

Characteristic

Min

Typ

Max

Units

Comments

D313

VUSB

USB Voltage

3.0

—

3.6

V

Voltage on bus must be in thisrange for proper USB
operation

D314

IIL

Input Leakage on Pin

—

—

±1

μA

VSS ≤ VPAD ≤ VDD;
pin at high impedance

D315

VILUSB

Input Low Voltage for USB
Buffer

—

—

0.8

V

For VUSB range

D316

VIHUSB

Input High Voltage for USB
Buffer

2.0

—

—

V

For VUSB range

D317

VCRS

Crossover Voltage

1.3

2.0

V

Voltage range for pad_dp and
pad_dm crossover to occur

D318

VDIFS

Differential Input Sensitivity

—

—

0.2

V

The difference between D+
and D- must exceed this value
while VCM is met

D319

VCM

Differential Common Mode
Range

0.8

—

2.5

V

D320

ZOUT

Driver Output Impedance

28

—

44

Ω

D321

VOL

Voltage Output Low

0.0

—

0.3

V

1.5 kΩ load connected to 3.6V

D322

VOH

Voltage Output High

2.8

—

3.6

V

15 kΩ load connected to
groundTABLE 28-5:

USB INTERNAL VOLTAGE REGULATOR SPECIFICATIONS

Operating Conditions: -40°C < TA < +85°C (unless otherwise stated).
Param
No.

Sym

Characteristics

D323

VUSBANA Regulator Output Voltage*

D324

CUSB

*

External Filter Capacitor
Value*

Min

Typ

Max

Units

3.0

—

3.6

V

220

—

—

nF

Comments

Must hold sufficient charge
for peak load with minimal
voltage drop

These parameters are characterized but not tested. Parameter numbers not yet assigned for these
specifications.

DS39632D-page 376

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
FIGURE 28-3:

HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS

For VDIRMAG = 1:

VDD
VHLVD

(HLVDIF set by hardware)(HLVDIF can becleared in software)

VHLVD
For VDIRMAG = 0:

VDD

HLVDIFTABLE 28-6:

HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS

Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
Param
SymbolNo.
D420

Characteristic

Min

Typ

Max

Units

HLVD Voltage on VDD HLVDL<3:0> = 0000
Transition High-to-Low HLVDL<3:0> = 0001

2.06

2.17

2.28

V

2.12

2.23

2.34

V

HLVDL<3:0> = 0010

2.24

2.36

2.48

V

HLVDL<3:0> = 0011

2.32

2.44

2.56

V

HLVDL<3:0> = 0100

2.47

2.60

2.73

V

HLVDL<3:0> = 0101

2.65

2.79

2.93

V

HLVDL<3:0> = 0110

2.74

2.89

3.04

V

HLVDL<3:0> = 0111

2.96

3.12

3.28

V

HLVDL<3:0> = 1000

3.22

3.39

3.56

V

HLVDL<3:0> = 1001

3.37

3.55

3.73

V

HLVDL<3:0> = 1010

3.52

3.71

3.90

V

HLVDL<3:0> = 1011

3.70

3.90

4.10

V

HLVDL<3:0> = 1100

3.90

4.11

4.32

V

HLVDL<3:0> = 1101

4.11

4.33

4.55

V

HLVDL<3:0> = 1110

4.36

4.59

4.82

V

© 2007 Microchip Technology Inc.

Preliminary

Conditions

DS39632D-page 377

PIC18F2455/2550/4455/4550
28.4
28.4.1

AC (Timing) Characteristics
TIMING PARAMETER SYMBOLOGY

The timing parameter symbols have been createdusing one of the following formats:
1. TppS2ppS
2. TppS
T
F
Frequency
Lowercase letters (pp) and their meanings:
ppad
SPP address write
cc
CCP1
ck
CLKO
cs
CS
da
SPP data write
di
SDI
do
SDO
dt
Data inio
I/O port
Uppercase letters and their meanings:
S
F
Fall
H
High
I
Invalid (High-Impedance)L
Low
I2C onlyAA
output access
BUF
Bus free
TCC:ST (I2C specifications only)
CC
HD
Hold
ST
DAT
DATA input hold
STA
Start condition

DS39632D-page 378

3. TCC:ST
4. Ts(I2C specifications only)(I2C specifications only)

T

Time

mc
osc
rd
rw
sc
ss
t0
t1
wr

MCLR
OSC1
RD
RD or WR
SCK
SS
T0CKI
T13CKIWR

P
RVZ

PeriodRise
Valid
High-Impedance

High
Low

High
Low

SU

Setup

STO

Stop condition

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
28.4.2TIMING CONDITIONSNote:

The temperature and voltages specified in Table 28-7
apply to all timing specifications unless otherwise
noted. Figure 28-4 specifies the load conditions for thetiming specifications.

TABLE 28-7:

Because of space limitations, the genericterms “PIC18FXXXX” and “PIC18LFXXXX”
are used throughout this section to refer tothe PIC18F2455/2550/4455/4550 and
PIC18LF2455/2550/4455/4550 families ofdevices specifically and only those devices.

TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC

AC CHARACTERISTICSFIGURE 28-4:

Standard Operating Conditions (unless otherwise stated)
Operating temperature-40°C ≤ TA ≤ +85°C for industrial
Operating voltage VDD range as described in DC spec Section 28.1 andSection 28.3.
LF parts operate for industrial temperatures only.

LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 1

Load Condition 2

VDD/2

RL

CL

Pin
VSS

CL

Pin

RL = 464Ω
VSS© 2007 Microchip Technology Inc.

CL = 50 pF

for all pins except OSC2/CLKO
and including D and E outputs as ports

Preliminary

DS39632D-page 379

PIC18F2455/2550/4455/4550
28.4.3

TIMING DIAGRAMS AND SPECIFICATIONSFIGURE 28-5:

EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL)
Q4

Q1

Q2

Q3

Q4

Q1

OSC1
1

3

4

3

4

2

CLKO

TABLE 28-8:

EXTERNAL CLOCK TIMING REQUIREMENTS

Param.
No.

Symbol

1A

FOSC

1

TOSC

Characteristic

Min

Max

Units

External CLKI Frequency(1)Oscillator Frequency(1)

DC

48

MHz

EC, ECIO Oscillator mode

0.2

1

MHz

XT, XTPLL Oscillator mode

4

25

MHz

HS Oscillator mode

4

25

MHz

HSPLL Oscillator mode

External CLKI Period(1)Oscillator Period(1)Conditions

20.8

—

ns

EC, ECIO Oscillator mode

1000

5000

ns

XT Oscillator mode

40

250

ns

HS Oscillator mode

40

250

ns

HSPLL Oscillator mode

2

TCY

Instruction Cycle Time(1)

83.3

—

ns

TCY = 4/FOSC

3

TosL,
TosH

External Clock in (OSC1)High or Low Time

30

—

ns

XT Oscillator mode

10

—

ns

HS Oscillator mode

4

TosR,
TosF

External Clock in (OSC1)
Rise or Fall Time

—

20

ns

XT Oscillator mode

—

7.5

ns

HS Oscillator mode

Note 1:

Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations
except PLL. All specified values are based on characterization data for that particular oscillator type understandard operating conditions with the device executing code. Exceeding these specified limits may resultin an unstable oscillator operation and/or higher than expected current consumption. All devices are tested
to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock
input is used, the “max.” cycle time limit is “DC” (no clock) for all devices.

DS39632D-page 380

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
TABLE 28-9:

PLL CLOCK TIMING SPECIFICATIONS (VDD = 3.0V TO 5.5V)

Param
No.

Sym

F10
F11

FOSC Oscillator Frequency Range
FSYS On-Chip VCO System Frequency

F12

trc
ΔCLK

F13

Characteristic

Min

Typ†

Max

Units

4
—

—
96

48
—

MHz
MHz

PLL Start-up Time (Lock Time)

—

—

2

ms

CLKO Stability (Jitter)

-0.25

—

+0.25

%

Conditions† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.

TABLE 28-10: AC CHARACTERISTICS: INTERNAL RC ACCURACY
PIC18F2455/2550/4455/4550 (INDUSTRIAL)
PIC18LF2455/2550/4455/4550 (INDUSTRIAL)
PIC18LF2455/2550/4455/4550(Industrial)

Standard Operating Conditions (unless otherwise stated)
Operating temperature-40°C ≤ TA ≤ +85°C for industrial

PIC18F2455/2550/4455/4550(Industrial)

Standard Operating Conditions (unless otherwise stated)
Operating temperature-40°C ≤ TA ≤ +85°C for industrial

Param
No.

Device

Min

Typ

Max

Units

Conditions

INTOSC Accuracy @ Freq = 8 MHz, 4 MHz, 2 MHz, 1 MHz, 500 kHz, 250 kHz, 125 kHz(1)PIC18LF2455/2550/4455/4550

PIC18F2455/2550/4455/4550

+/-1

2

%

+25°C

VDD = 2.7-3.3V

-5

—

5

%

-10°C to +85°C

VDD = 2.7-3.3V

-10

+/-1

10

%

-40°C to +85°C

VDD = 2.7-3.3V

-2

+/-1

2

%

+25°C

VDD = 4.5-5.5V

-5

—

5

%

-10°C to +85°C

VDD = 4.5-5.5V

-10

+/-1

10

%

-40°C to +85°C

VDD = 4.5-5.5V

PIC18LF2455/2550/4455/4550 26.562—

35.938kHz-40°C to +85°C

VDD = 2.7-3.3V

PIC18F2455/2550/4455/4550 26.562—

35.938kHz-40°C to +85°C

VDD = 4.5-5.5V

INTRC Accuracy @ Freq = 31 kHz

Legend:Note 1:
2:
3:

-2

(2)

Shading of rows is to assist in readability of the table.
Frequency calibrated at 25°C. OSCTUNE register can be used to compensate for temperature drift.
INTRC frequency after calibration.
Change of INTRC frequency as VDD changes.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 381

PIC18F2455/2550/4455/4550
FIGURE 28-6:

CLKO AND I/O TIMING
Q1

Q4

Q2

Q3

OSC1
11

10
CLKO
13

19

14

12

18

16

I/O pin(Input)15

17
I/O pin(Output)

New Value

Old Value20, 21

Note:

Refer to Figure 28-4 for load conditions.

TABLE 28-11: CLKO AND I/O TIMING REQUIREMENTS
Param
No.

Symbol10

TosH2ckL OSC1 ↑ to CLKO ↓Characteristic

Min

Typ

Max

—

75

200

Units Conditions
ns(Note 1)

11

TosH2ckH OSC1 ↑ to CLKO ↑

—

75

200

ns

(Note 1)

12

TckR

CLKO Rise Time

—

35

100

ns

(Note 1)

13

TckF

CLKO Fall Time

—

35

100

ns

(Note 1)

14

TckL2ioV

CLKO ↓ to Port Out Valid——

0.5 TCY + 20

ns

(Note 1)

15

TioV2ckH Port In Valid before CLKO ↑16

TckH2ioI17
18

TosH2ioI

0.25 TCY + 25

—

—

ns

(Note 1)

0

—

—

ns

(Note 1)

TosH2ioV OSC1 ↑ (Q1 cycle) to Port Out Valid

—

50

150

ns

OSC1 ↑ (Q2 cycle) toPort Input Invalid(I/O in hold time)

PIC18FXXXX

100

—

—

ns

PIC18LFXXXX

200

—

—

ns

18A

Port In Hold after CLKO ↑19

TioV2osH Port Input Valid to OSC1 ↑ (I/O in setup time)

0

—

—

ns

20

TioR

Port Output Rise Time

20A
21

TioF

Port Output Fall Time

21A

PIC18FXXXX

—

10

25

ns

PIC18LFXXXX

—

—

60

ns

PIC18FXXXX

—

10

25

ns

PIC18LFXXXX

—

—

60

ns

22†

TINP

INT pin High or Low Time

TCY

—

—

ns

23†

TRBP

RB7:RB4 Change INT High or Low Time

TCY

—

—

ns

VDD = 2.0V

VDD = 2.0V
VDD = 2.0V

† These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in RC mode, where CLKO output is 4 x TOSC.

DS39632D-page 382

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
FIGURE 28-7:

RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND
POWER-UP TIMER TIMING

VDD
MCLR
30

Internal
POR
33

PWRT
Time-out

32

Oscillator
Time-out
Internal
Reset
Watchdog
Timer
Reset

31

34

34

I/O pins
Note:

Refer to Figure 28-4 for load conditions.

FIGURE 28-8:

BROWN-OUT RESET TIMING
BVDD

VDD

35
VBGAP = 1.2V
VIRVST
Enable Internal
Reference Voltage
Internal Reference
Voltage Stable

36

TABLE 28-12: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
Param.
Symbol
No.

Characteristic

Min

Typ

Max

Units

30

TmcL

MCLR Pulse Width (low)

2

—

—

μs

31

TWDT

Watchdog Timer Time-out Period(no postscaler)

—

4.00

TBD

ms

32

TOST

Oscillator Start-up Timer Period

1024 TOSC—

1024 TOSC

—

33

TPWRT

Power-up Timer Period

—

65.5

TBD

ms

34

TIOZ

I/O High-Impedance from MCLR
Low or Watchdog Timer Reset

—

2

—

μs

35

TBOR

Brown-out Reset Pulse Width

200

—

—

μs

36

TIRVST

Time for Internal Reference
Voltage to become Stable

—

20

50

μs

37

TLVD

Low-Voltage Detect Pulse Width

200

—

—

μs

38

TCSD

CPU Start-up Time

5

—

10

μs

39

TIOBST

Time for INTOSC to Stabilize

—

1

—

ms

Conditions

TOSC = OSC1 period

VDD ≤ BVDD (see D005)

VDD ≤ VLVD

Legend: TBD = To Be Determined© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 383

PIC18F2455/2550/4455/4550
FIGURE 28-9:

TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI

41

40

42
T1OSO/T13CKI

46

45

47

48

TMR0 or
TMR1
Note:

Refer to Figure 28-4 for load conditions.

TABLE 28-13: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param
Symbol
No.

Characteristic

40

Tt0H

T0CKI High Pulse Width

41

Tt0L

T0CKI Low Pulse Width

42

Tt0P

T0CKI Period

45

Tt1H

T13CKI High
Time

Min

Max

Units

0.5 TCY + 20—

nsWith prescaler

10

—

ns

No prescaler

0.5 TCY + 20—

ns

No prescalerWith prescaler

10

—

ns

No prescaler

TCY + 10—ns

With prescaler

Greater of:
20 ns or(TCY + 40)/N—

ns

Synchronous, no prescaler
PIC18FXXXX

Tt1L

T13CKI Low
Time

25

—

ns

30

—

ns

Synchronous, no prescaler
Synchronous,
with prescaler

50

—

ns

0.5 TCY + 5—

ns

N = prescalevalue(1, 2, 4,..., 256)

VDD = 2.0V
VDD = 2.0V

PIC18FXXXX

10

—

ns

PIC18LFXXXX

25

—

ns

PIC18FXXXX

30

—

ns

PIC18LFXXXX

50

—

ns

VDD = 2.0V

Greater of:
20 ns or(TCY + 40)/N—ns

N = prescalevalue (1, 2, 4, 8)

Tt1P

T13CKI Input
PeriodFt1

T13CKI Oscillator Input Frequency Range

SynchronousTcke2tmrI Delay from External T13CKI Clock Edge to Timer
Increment

DS39632D-page 384

ns

PIC18FXXXXAsynchronous
48

ns

—

PIC18LFXXXXAsynchronous
47

—

10

Asynchronous

PIC18LFXXXX
46

0.5 TCY + 20

Synchronous,
with prescaler

Conditions

Preliminary

60

—

ns

DC

50

kHz

2 TOSC

7 TOSC—VDD = 2.0V

© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
FIGURE 28-10:

CAPTURE/COMPARE/PWM TIMINGS (ALL CCP MODULES)
CCPx(Capture Mode)

50

51
52

CCPx
(Compare or PWM Mode)
54

53
Note:

Refer to Figure 28-4 for load conditions.

TABLE 28-14: CAPTURE/COMPARE/PWM REQUIREMENTS (ALL CCP MODULES)
Param
Symbol
No.
50

51

TccL

TccH

Characteristic

Min

Max

Units

CCPx Input Low No prescaler
Time
With
PIC18FXXXX
prescaler PIC18LFXXXX

0.5 TCY + 20

—

ns

10

—

ns

20

—

ns

CCPx Input
High Time

0.5 TCY + 20—

ns

No prescalerWith
prescaler

52

TccP

CCPx Input Period

53

TccR

CCPx Output Fall Time

54

TccF

CCPx Output Fall Time

© 2007 Microchip Technology Inc.

Conditions

VDD = 2.0V

PIC18FXXXX

10

—

ns

PIC18LFXXXX

20

—

ns

VDD = 2.0V

3 TCY + 40
N

—

ns

N = prescalevalue (1, 4 or 16)

—

25

ns

PIC18FXXXXPIC18LFXXXX

—

45

ns

PIC18FXXXX

—

25

ns

PIC18LFXXXX

—

45

ns

Preliminary

VDD = 2.0V
VDD = 2.0V

DS39632D-page 385

PIC18F2455/2550/4455/4550
FIGURE 28-11:

EXAMPLE SPI MASTER MODE TIMING (CKE = 0)

SS
70
SCK
(CKP = 0)
71

72
78

79

79

78

SCK
(CKP = 1)

80

bit 6 - - - - - -1

MSb

SDO

LSb

75, 76SDI

MSb Inbit 6 - - - -1

LSb In

74
73
Note:

Refer to Figure 28-4 for load conditions.

TABLE 28-15: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)
Param
No.

SymbolCharacteristic

Min

Max Units

70

TssL2scH,
TssL2scL

SS ↓ to SCK ↓ or SCK ↑ Input

TCY

—

ns

71

TscH

SCK Input High Time
(Slave mode)

Continuous

1.25 TCY + 30—

nsSingle Byte

40

—

ns

SCK Input Low Time
(Slave mode)

Continuous

1.25 TCY + 30—

nsSingle Byte

40

—

ns

100

—

ns

1.5 TCY + 40

—

ns

71A
72

TscL

72A
73

TdiV2scH,
TdiV2scL

Setup Time of SDI Data Input to SCK Edge

73A

Tb2b

Last Clock Edge of Byte 1 to the 1st Clock Edgeof Byte 274

TscH2diL,TscL2diL

Hold Time of SDI Data Input to SCK Edge

100

—

ns

75

TdoR

SDO Data Output Rise Time

PIC18FXXXX

—

25

ns

PIC18LFXXXX

—

45

ns

76

TdoF

SDO Data Output Fall Time

—

25

ns

78

TscR

SCK Output Rise Time
(Master mode)

PIC18FXXXX

—

25

ns

PIC18LFXXXX

—

45

ns

79

TscF

SCK Output Fall Time (Master mode)

—

25

ns

80

TscH2doV,
TscL2doV

SDO Data Output Valid after
SCK Edge

PIC18FXXXX

—

50

ns

PIC18LFXXXX

—

100

ns

Note 1:
2:

Conditions(Note 1)
(Note 1)

(Note 2)

VDD = 2.0V

VDD = 2.0V

VDD = 2.0V

Requires the use of Parameter 73A.
Only if Parameter 71A and 72A are used.

DS39632D-page 386

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
FIGURE 28-12:

EXAMPLE SPI MASTER MODE TIMING (CKE = 1)

SS
81
SCK
(CKP = 0)
71

72
79

73
SCK
(CKP = 1)
80
78

MSb

SDO

bit 6 - - - - - -1

LSb

bit 6 - - - -1

LSb In75, 76SDI

MSb In74

Note:Refer to Figure 28-4 for load conditions.

TABLE 28-16: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)
Param.
No.

SymbolCharacteristic

Min

Max Units

1.25 TCY + 30—

nsSingle Byte

40

—

ns

Continuous

1.25 TCY + 30—

nsSingle Byte

40

—

ns

Setup Time of SDI Data Input to SCK Edge

100

—

ns

1.5 TCY + 40—

ns

Hold Time of SDI Data Input to SCK Edge

100

—

ns

TdoR

SDO Data Output Rise Time

PIC18FXXXX

—

25

ns

PIC18LFXXXX

—

45

ns

76

TdoF

SDO Data Output Fall Time

—

25

ns

78

TscR

SCK Output Rise Time
(Master mode)

PIC18FXXXX

—

25

ns

PIC18LFXXXX

—

45

ns

71

TscH

SCK Input High Time
(Slave mode)TscL

SCK Input Low Time
(Slave mode)73

TdiV2scH,
TdiV2scL

73A

Tb2b

Last Clock Edge of Byte 1 to the 1st Clock Edgeof Byte 274

TscH2diL,TscL2diL

75

71A
72
72A

Continuous

79

TscF

SCK Output Fall Time (Master mode)

—

25

ns

80

TscH2doV,
TscL2doV

SDO Data Output Valid after
SCK Edge

—

50

ns

—

100

ns

81

TdoV2scH,
TdoV2scL

SDO Data Output Setup to SCK Edge

TCY

—

ns

Note 1:
2:

PIC18FXXXXPIC18LFXXXXConditions(Note 1)
(Note 1)

(Note 2)

VDD = 2.0V

VDD = 2.0V

VDD = 2.0V

Requires the use of Parameter 73A.
Only if Parameter 71A and 72A are used.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 387

PIC18F2455/2550/4455/4550
FIGURE 28-13:

EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)

SS
70
SCK
(CKP = 0)

83
71

72

78

79

79

78

SCK
(CKP = 1)

80
MSb

SDO

bit 6 - - - - - -1

LSb77

75, 76
MSb In

SDI

73
Note:

bit 6 - - - -1

LSb In74

Refer to Figure 28-4 for load conditions.

TABLE 28-17: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0)
Param
No.

Symbol70

TssL2scH, SS ↓ to SCK ↓ or SCK ↑ Input
TssL2scL

71

TscH

71A
72

TscL

72A

Characteristic

Min

Max Units Conditions

TCY

—

ns

SCK Input High Time
(Slave mode)

Continuous

1.25 TCY + 30—

nsSingle Byte

40

—

ns

SCK Input Low Time
(Slave mode)

Continuous

1.25 TCY + 30—

nsSingle Byte

40

—

ns

100

—

ns

73

TdiV2scH, Setup Time of SDI Data Input to SCK Edge
TdiV2scL

73A

Tb2b

—

ns

74

TscH2diL, Hold Time of SDI Data Input to SCK Edge
TscL2diL

100

—

ns

75

TdoR

PIC18FXXXX

—

25

ns

PIC18LFXXXX

—

45

ns

Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40

SDO Data Output Rise Time

76

TdoF

SDO Data Output Fall Time

—

25

ns

77

TssH2doZ SS ↑ to SDO Output High-Impedance

10

50

ns

78

TscR

PIC18FXXXX

—

25

ns

PIC18LFXXXX

—

45

ns

79

TscF

—

25

ns

80

TscH2doV, SDO Data Output Valid after SCK Edge PIC18FXXXXTscL2doV
PIC18LFXXXX

—

50

ns

—

100

ns

1.5 TCY + 40

—

ns

83
Note 1:2:SCK Output Rise Time (Master mode)
SCK Output Fall Time (Master mode)

TscH2ssH, SS ↑ after SCK edge
TscL2ssH(Note 1)
(Note 1)

(Note 2)

VDD = 2.0V

VDD = 2.0V

VDD = 2.0V

Requires the use of Parameter 73A.
Only if Parameter 71A and 72A are used.

DS39632D-page 388

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
FIGURE 28-14:

EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)
82

SS

SCK
(CKP = 0)

70
83
71

72

SCK
(CKP = 1)
80

MSb

SDO

bit 6 - - - - - -1

LSb75, 76SDI

MSb InNote:77
bit 6 - - - -1

LSb In74
Refer to Figure 28-4 for load conditions.

TABLE 28-18: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)
Param
No.

Symbol70

TssL2scH, SS ↓ to SCK ↓ or SCK ↑ Input
TssL2scL71

TscH

SCK Input High Time
(Slave mode)TscL

SCK Input Low Time
(Slave mode)

73A

Tb2b

Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40

74

TscH2diL, Hold Time of SDI Data Input to SCK Edge
TscL2diL75

TdoR

SDO Data Output Rise Time

76

TdoF

SDO Data Output Fall Time

71A
72
72A

Characteristic

Continuous

Min

Max Units Conditions

TCY

—

ns

1.25 TCY + 30—

nsSingle Byte

40

—

ns

Continuous

1.25 TCY + 30—

nsSingle Byte

40

PIC18FXXXXPIC18LFXXXX—ns(Note 1)—ns

(Note 2)

100

—

ns

—

25

ns

—

45

ns

—

25

ns

77

TssH2doZ SS ↑ to SDO Output High-Impedance

10

50

ns

78

TscR

SCK Output Rise Time
(Master mode)

PIC18FXXXX

—

25

ns

PIC18LFXXXX

—

45

ns

79

TscF

SCK Output Fall Time (Master mode)

—

25

ns

80

TscH2doV, SDO Data Output Valid after SCK
TscL2doV Edge

PIC18FXXXX

—

50

ns

PIC18LFXXXX

—

100

ns

SDO Data Output Valid after SS ↓Edge

PIC18FXXXX

—

50

ns

—

100

ns

1.5 TCY + 40

—

ns

82

TssL2doV83

TscH2ssH, SS ↑ after SCK Edge
TscL2ssH

Note 1:
2:

PIC18LFXXXX(Note 1)

VDD = 2.0V

VDD = 2.0V

VDD = 2.0V
VDD = 2.0V

Requires the use of Parameter 73A.
Only if Parameter 71A and 72A are used.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 389

PIC18F2455/2550/4455/4550
I2C™ BUS START/STOP BITS TIMINGFIGURE 28-15:

SCL

91

93

90

92

SDA

Stop
Condition

Start
Condition
Note:

Refer to Figure 28-4 for load conditions.

TABLE 28-19: I2C™ BUS START/STOP BITS REQUIREMENTS (SLAVE MODE)
Param.
Symbol
No.

Characteristic90

TSU:STA

Start Condition

91

THD:STA92

TSU:STO93

THD:STO Stop Condition

Max

Units

Conditions

4700

—

ns

Only relevant for RepeatedStart conditionns

After this period, the firstclock pulse is generated

Setup Time

400 kHz mode

600—

Start Condition

100 kHz mode

4000

—

Hold Time

400 kHz mode

600—

Stop Condition

100 kHz mode

4700

—

Setup Time
Hold Time

FIGURE 28-16:

100 kHz modeMin

400 kHz mode

600—

100 kHz mode

4000

—

400 kHz mode

600

—

ns
ns

I2C™ BUS DATA TIMING
103

102

100
101

SCL
90

106

107

91

92

SDA
In
110
109

109

SDA
Out
Note:

Refer to Figure 28-4 for load conditions.

DS39632D-page 390

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
TABLE 28-20: I2C™ BUS DATA REQUIREMENTS (SLAVE MODE)
Param.
Symbol
No.
100

THIGH

101

TLOW

102

TR

103

91
106
107
92
109

2:

Conditions

100 kHz mode

4.0

—

μs

PIC18FXXXX must operate
at a minimum of 1.5 MHz

400 kHz mode

0.6

—

μs

PIC18FXXXX must operate
at a minimum of 10 MHz

MSSP Module

1.5 TCY—

100 kHz mode

4.7

—

μs

PIC18FXXXX must operate
at a minimum of 1.5 MHz

400 kHz mode

1.3

—

μs

PIC18FXXXX must operate
at a minimum of 10 MHz

MSSP Module

1.5 TCY

—

—

1000

ns

20 + 0.1 CB

300

ns

SDA and SCL Rise 100 kHz modeTime
400 kHz mode
SDA and SCL FallTime

CB is specified to be from10 to 400 pF

300

ns

400 kHz mode

300

ns

CB is specified to be from10 to 400 pF

TSU:STA Start Condition
Setup Time

100 kHz mode

4.7

—

μs

400 kHz mode

0.6

—

μs

Only relevant for RepeatedStart condition

THD:STA Start Condition
Hold Time

100 kHz mode

4.0

—

μs

400 kHz mode

0.6

—

μs

THD:DAT Data Input HoldTime

100 kHz mode

0

—

ns

400 kHz mode

0

0.9

μs

TSU:DAT Data Input Setup
Time

100 kHz mode

250

—

ns

400 kHz mode

100

—

ns

TSU:STO Stop Condition
Setup Time

100 kHz mode

4.7

—

μs

400 kHz mode

0.6

—

μs

100 kHz mode

—

3500

ns

400 kHz mode

—

—

ns

CB

Note 1:Units

20 + 0.1 CB

TBUF

D102

Clock Low Time

Max

—

TAA

110

Clock High TimeMin

100 kHz mode

TF

90

Characteristic

Output Valid fromClock
Bus Free Time

100 kHz mode

4.7

—

μs

400 kHz mode

1.3

—

μs

—

400

pF

Bus Capacitive Loading

After this period, the firstclock pulse is generated(Note 2)

(Note 1)Time the bus must be free
before a new transmission
can start

As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region(min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
A Fast mode I2C™ bus device can be used in a Standard mode I2C bus system but the requirement,
TSU:DAT ≥ 250 ns, must then be met. This will automatically be the case if the device does not stretch the
LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must
output the next data bit to the SDA line, TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to theStandard mode I2C bus specification), before the SCL line is released.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 391

PIC18F2455/2550/4455/4550
MASTER SSP I2C™ BUS START/STOP BITS TIMING WAVEFORMS

FIGURE 28-17:

SCL

93

91
90

92

SDA

Stop
Condition

Start
Condition
Note:

Refer to Figure 28-4 for load conditions.

TABLE 28-21: MASTER SSP I2C™ BUS START/STOP BITS REQUIREMENTS
Param.
SymbolNo.
90

91

TSU:STA

Characteristic

93

Conditions

ns

Only relevant for
Repeated Start
conditionns

After this period, thefirst clock pulse isgenerated

2(TOSC)(BRG + 1)—

Setup Time

400 kHz mode2(TOSC)(BRG + 1)—

1 MHz mode(1)2(TOSC)(BRG + 1)—

100 kHz mode2(TOSC)(BRG + 1)—

400 kHz mode2(TOSC)(BRG + 1)—

1 MHz mode(1)2(TOSC)(BRG + 1)—

Stop Condition

100 kHz mode2(TOSC)(BRG + 1)—

Setup Time

400 kHz mode

THD:STO Stop Condition
Hold Time

Note 1:Units

100 kHz mode

Hold Time
92

Max

Start Condition

THD:STA Start Condition

TSU:STOMin

2(TOSC)(BRG + 1)—

1 MHz mode(1)2(TOSC)(BRG + 1)—

100 kHz mode2(TOSC)(BRG + 1)—

400 kHz mode2(TOSC)(BRG + 1)—

1 MHz mode(1)2(TOSC)(BRG + 1)

—

ns

ns

2C™ pins.

Maximum pin capacitance = 10 pF for all I

FIGURE 28-18:

MASTER SSP I2C™ BUS DATA TIMING
103

102

100
101

SCL

90

106

91

107

92

SDA
In
109

109

110

SDA
Out
Note:

DS39632D-page 392

Refer to Figure 28-4 for load conditions.

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
TABLE 28-22: MASTER SSP I2C™ BUS DATA REQUIREMENTS
Param.
Symbol
No.
100

101

102

103

90

91

THIGH

TLOW

TR

TF

TSU:STA

Characteristic

Min

Max

Units

Clock High Time 100 kHz mode2(TOSC)(BRG + 1)—

ms

400 kHz mode2(TOSC)(BRG + 1)—

ms

1 MHz mode(1)2(TOSC)(BRG + 1)—

ms

Clock Low Time 100 kHz mode2(TOSC)(BRG + 1)—

ms

400 kHz mode2(TOSC)(BRG + 1)

—

ms

(1)

1 MHz mode2(TOSC)(BRG + 1)—

ms

100 kHz mode

—

1000

ns

400 kHz mode

20 + 0.1 CB

300

ns

1 MHz mode(1)

—

300

ns

SDA and SCL
Rise Time

SDA and SCL
Fall Time

Start Condition
Setup Time

THD:STA Start Condition
Hold Time

100 kHz mode

—

300

ns

400 kHz mode

20 + 0.1 CB

300

ns

1 MHz mode(1)

—

100

ns

100 kHz mode2(TOSC)(BRG + 1)—

ms

400 kHz mode2(TOSC)(BRG + 1)—

ms

1 MHz mode(1)2(TOSC)(BRG + 1)—

ms

100 kHz mode2(TOSC)(BRG + 1)—

ms

400 kHz mode2(TOSC)(BRG + 1)—

ms

1 MHz mode(1)2(TOSC)(BRG + 1)

—

ms

0

—

ns

106

THD:DAT Data Input
Hold Time

100 kHz mode
400 kHz mode

0

0.9

ms

107

TSU:DAT

100 kHz mode

250

—

ns

92

TSU:STO Stop Condition
Setup Time

109

110

D102
Note 1:
2:

TAA

TBUF

CB

Data Input
Setup Time

Output Validfrom ClockBus Free Time

400 kHz mode

100

—

ns

100 kHz mode2(TOSC)(BRG + 1)—

ms

400 kHz mode2(TOSC)(BRG + 1)—

ms

1 MHz mode(1)2(TOSC)(BRG + 1)—

ms

100 kHz mode

—

3500

ns

400 kHz mode

—

1000

ns

(1)

1 MHz mode

—

—

ns

100 kHz mode

4.7

—

ms

400 kHz mode

1.3

—

ms

—

400

pF

Bus Capacitive Loading

Conditions

CB is specified to be from10 to 400 pF

CB is specified to be from10 to 400 pF

Only relevant for
Repeated Start
condition
After this period, the firstclock pulse is generated(Note 2)Time the bus must be free
before a new transmission
can start

2C™ pins.

Maximum pin capacitance = 10 pF for all I
A Fast mode I2C bus device can be used in a Standard mode I2C bus system but parameter #107 ≥ 250 ns
must then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bitto the SDA line, parameter #102 + parameter #107 = 1000 + 250 = 1250 ns (for 100 kHz mode), before the
SCL line is released.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 393

PIC18F2455/2550/4455/4550
FIGURE 28-19:

EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING

RC6/TX/CK
pin
121

121

RC7/RX/DT/SDO
pin
120
Note:

122

Refer to Figure 28-4 for load conditions.

TABLE 28-23: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Param
No.
120

SymbolCharacteristic

TckH2dtV SYNC XMIT (MASTER & SLAVE)
Clock High to Data Out Valid

PIC18FXXXX

Min

Max

Units

—

40

ns

PIC18LFXXXX

—

100

ns

121

Tckrf

Clock Out Rise Time and Fall Time
(Master mode)

PIC18FXXXX

—

20

ns

PIC18LFXXXX

—

50

ns

122

Tdtrf

Data Out Rise Time and Fall Time

PIC18FXXXX

—

20

ns

PIC18LFXXXX

—

50

ns

FIGURE 28-20:

Conditions

VDD = 2.0V
VDD = 2.0V
VDD = 2.0V

EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING

RC6/TX/CK
pin

125

RC7/RX/DT/SDO
pin
126
Note:

Refer to Figure 28-4 for load conditions.

TABLE 28-24: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS
Param.
No.
125
126

SymbolCharacteristic

TDTV2CKL SYNC RCV (MASTER & SLAVE)
Data Hold before CK ↓ (DT hold time)TCKL2DTL

DS39632D-page 394

Data Hold after CK ↓ (DT hold time)

Preliminary

Min

Max

Units

10

—

ns

15

—

ns

Conditions© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
FIGURE 28-21:

USB SIGNAL TIMINGUSB Data Differential Lines
90%
VCRS
10%
TLF, TFF

TLR, TFRTABLE 28-25: USB LOW-SPEED TIMING REQUIREMENTS
Param
No.

SymbolCharacteristic

Min

Typ

Max

Units

Conditions

TLR

Transition Rise Time

75

—

300

ns

CL = 200 to 600 pF

TLF

Transition Fall Time

75

—

300

ns

CL = 200 to 600 pF

TLRFM

Rise/Fall Time Matching

80

—

125

%

Min

Typ

Max

Units

4

—

20

ns

CL = 50 pF
CL = 50 pF

TABLE 28-26: USB FULL-SPEED REQUIREMENTS
Param
No.

SymbolCharacteristic

TFRTransition Rise Time

TFF

Transition Fall Time

4

—

20

ns

TFRFM

Rise/Fall Time Matching

90

—

111.1

%

© 2007 Microchip Technology Inc.

Preliminary

Conditions

DS39632D-page 395

PIC18F2455/2550/4455/4550
FIGURE 28-22:

STREAMING PARALLEL PORT TIMING (PIC18F4455/4550)

OESPP

CSSPP
ToeF2adR

SPP<7:0>

ToeF2daR

Write Address

ToeF2adV
Note:

Write Data

ToeR2adI

ToeF2daV

ToeR2adI

Refer to Figure 28-4 for load conditions.

TABLE 28-27: STREAMING PARALLEL PORT REQUIREMENTS (PIC18F4455/4550)
Param.
No.

SymbolCharacteristic

Min

Max

Units

ToeF2adR

OESPP Falling Edge to CSSPP Rising Edge,
Address Out

0

5

ns

ToeF2adVOESPP Falling Edge to Address Out Valid

0

5

ns

ToeR2adI

OESPP Rising Edge to Address Out Invalid

0

5

ns

ToeF2daROESPP Falling Edge to CSSPP Rising Edge,
Data Out0

5

ns

ToeF2daVOESPP Falling Edge to Address Out Valid

0

5

ns

ToeR2daIOESPP Rising Edge to Data Out Invalid

0

5

ns

DS39632D-page 396

Preliminary

Conditions© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
TABLE 28-28: A/D CONVERTER CHARACTERISTICS: PIC18F2455/2550/4455/4550 (INDUSTRIAL)
PIC18LF2455/2550/4455/4550 (INDUSTRIAL)
Param
Symbol
No.

Characteristic

Min

Typ

Max

Units

—

—

10

bit

Conditions
ΔVREF ≥ 3.0V

A01

NR

Resolution

A03

EIL

Integral Linearity Error

—

—

<±1

LSb ΔVREF ≥ 3.0V

A04

EDL

Differential Linearity Error

—

—

<±1

LSb ΔVREF ≥ 3.0V

A06

EOFF

Offset Error

—

—

<±1.5

LSb ΔVREF ≥ 3.0V

A07

EGN

Gain Error

—

—

<±1

LSb ΔVREF ≥ 3.0V

A10—

Monotonicity—

VSS ≤ VAIN ≤ VREF

A20

ΔVREF

Reference Voltage Range(VREFH – VREFL)

1.8
3

—
—

—
—

V
V

VDD < 3.0V
VDD ≥ 3.0V

A21

VREFH

Reference Voltage High

VSS

—

VREFH

V

A22

VREFL

Reference Voltage Low

VSS – 0.3V—

VDD – 3.0V

V

A25

VAIN

Analog Input Voltage

VREFL

—

VREFH

V

A30

ZAIN

Recommended Impedance of
Analog Voltage Source

—

—

2.5

kΩ

A50

IREF

VREF Input Current(2)

—
—

—
—

5
150

μA
μA

Note 1:
2:

Guaranteed(1)During VAIN acquisition.
During A/D conversion
cycle.

The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
VREFH current is from RA3/AN3/VREF+ pin or VDD, whichever is selected as the VREFH source.
VREFL current is from RA2/AN2/VREF-/CVREF pin or VSS, whichever is selected as the VREFL source.

FIGURE 28-23:

A/D CONVERSION TIMING

BSF ADCON0, GO(Note 2)

131

Q4
130
A/D CLK132

9

A/D DATA

8

7

...

...

2

1

0

OLD_DATAADRES

NEW_DATA
TCY(1)

ADIF
GO

DONE
SAMPLING STOPPEDSAMPLE

Note

1:

If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts.
This allows the SLEEP instruction to be executed.

2:This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 397

PIC18F2455/2550/4455/4550
TABLE 28-29: A/D CONVERSION REQUIREMENTS
Param
Symbol
No.
130

TAD

Characteristic
A/D Clock Period

Min

Max

Units

0.7

25.0(1)μs

TOSC based, VREF ≥ 3.0V

PIC18LFXXXX

1.4

25.0

(1)

μs

VDD = 2.0V,
TOSC based, VREF full range

PIC18FXXXX

TBD

1

μs

A/D RC mode

PIC18LFXXXX

TBD

3

μs

VDD = 2.0V,
A/D RC mode

PIC18FXXXX

131

TCNV

Conversion Time(not including acquisition time)(2)

11

12

TAD

132

TACQ

Acquisition Time(3)

1.4
TBD

—
—

μs
μs

135

TSWC

Switching Time from Convert → Sample—(Note 4)

137

TDIS

Discharge Time

0.2—

Legend:Note 1:
2:
3:
4:

Conditions-40°C to +85°C
0°C ≤ to ≤ +85°C

μs

TBD = To Be Determined
The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.
ADRES registers may be read on the following TCY cycle.
The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50Ω.
On the following cycle of the device clock.

DS39632D-page 398

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
29.0

DC AND AC
CHARACTERISTICS GRAPHSAND TABLES

Graphs and tables are not available at this time.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 399

PIC18F2455/2550/4455/4550
NOTES:DS39632D-page 400

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
30.0

PACKAGING INFORMATION

30.1

Package Marking Information
28-Lead PDIP (Skinny DIP)

Example
PIC18F2455-I/SP e3
0710017

XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXYYWWNNN

28-Lead SOIC

Example
PIC18F2550-E/SO e3
0710017

XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXYYWWNNN

40-Lead PDIP

Example
PIC18F4455-I/P e30710017

XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXYYWWNNN

Legend: XX...X
Y
YY
WW
NNN

e3

*

Note:

Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability codePb-free JEDEC designator for Matte Tin (Sn)This package is Pb-free. The Pb-free JEDEC designator ( e3 )can be found on the outer packaging for this package.

In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 401

PIC18F2455/2550/4455/4550
Package Marking Information (Continued)

44-Lead TQFP

ExampleXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXYYWWNNN

PIC18F4550-I/PT e3071001744-Lead QFNExampleXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXYYWWNNNDS39632D-page 402

PIC18F4550-I/ML e30710017

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
30.2

Package Details

The following sections give the technical details of the
packages.

28-Lead Skinny Plastic Dual In-Line (SP) – 300 mil Body [SPDIP]
Note:

For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

N
NOTE 1
E1

1

2

3
D
E
A2

A

L

c

b1

A1

b

e

eB

Units
Dimension Limits
Number of Pins

INCHES
MIN

N

NOM

MAX

28

Pitch

e

Top to Seating Plane

A–.100 BSC–.200

Molded Package Thickness

A2

.120

.135

.150

Base to Seating Plane

A1

.015

–

–

Shoulder to Shoulder Width

E

.290

.310

.335

Molded Package Width

E1

.240

.285

.295

Overall Length

D

1.345

1.365

1.400

Tip to Seating Plane

L

.110

.130

.150

Lead Thickness

c

.008

.010

.015

Upper Lead Width

b1

.040

.050

.070

Lower Lead Width

b

.014

.018

.022

Overall Row Spacing §

eB

–

–

.430
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-070B© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 403

PIC18F2455/2550/4455/4550
28-Lead Plastic Small Outline (SO) – Wide, 7.50 mm Body [SOIC]Note:

For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
N

E
E1
NOTE 1
1 2 3
b

e

h

α

h
c

φ

A2

A

L
A1

Units
Dimension Limits
Number of Pinsβ

L1

MILLMETERS
MIN

N

NOM

MAX

28

Pitch

e

Overall HeightA–

1.27 BSC–

Molded Package Thickness

A2

2.05

–

–

Standoff §

A1

0.10

–

0.30

Overall WidthE

Molded Package Width

E1

7.50 BSC

Overall LengthD

17.90 BSC

2.65

10.30 BSC

Chamfer (optional)

h

0.25

–

0.75

Foot Length

L

0.40

–

1.27

Footprint

L1

Foot Angle Top

φ

0°

–

8°

Lead Thickness

c

0.18

–

0.33

Lead Width

b

0.31

–

0.51

Mold Draft Angle Top

α

5°

–

15°

Mold Draft Angle Bottom

β

5°

–

1.40 REF

15°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-052B

DS39632D-page 404

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
40-Lead Plastic Dual In-Line (P) – 600 mil Body [PDIP]
Note:

For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

N
NOTE 1
E1

1 2 3
D

E
A2

A

L

c

b1

A1

b

e

eB

Units
Dimension Limits
Number of Pins

INCHES
MIN

N

NOM

MAX

40

Pitch

e

Top to Seating Plane

A–.100 BSC–.250

Molded Package Thickness

A2

.125

–

.195

Base to Seating Plane

A1

.015

–

–

Shoulder to Shoulder Width

E

.590

–

.625

Molded Package Width

E1

.485

–

.580

Overall Length

D

1.980

–

2.095

Tip to Seating Plane

L

.115

–

.200

Lead Thickness

c

.008

–

.015

Upper Lead Width

b1

.030

–

.070

Lower Lead Width

b

.014

–

.023

Overall Row Spacing §

eB

–

–

.700
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-016B© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 405

PIC18F2455/2550/4455/4550
44-Lead Plastic Thin Quad Flatpack (PT) – 10x10x1 mm Body, 2.00 mm Footprint [TQFP]
Note:

For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
D1

E
e

E1

N

b

NOTE 1

1 2 3

NOTE 2

α

A

c

φ

β

L

A1

Units
Dimension Limits
Number of Leads

A2

L1

MILLIMETERS
MIN

N

NOM

MAX

44

Lead PitcheOverall HeightA–

0.80 BSC–

Molded Package Thickness

A2

0.95

1.00

1.05

Standoff

A1

0.05

–

0.15

Foot Length

L

0.45

0.60

0.75

Footprint

L1

1.20

1.00 REF

Foot Angle

φOverall WidthE

12.00 BSC

Overall LengthD

12.00 BSC

Molded Package Width

E1

10.00 BSC

Molded Package Length

D1

10.00 BSC

0°

3.5°

7°

Lead Thickness

c

0.09

–

0.20

Lead Width

b

0.30

0.37

0.45

Mold Draft Angle Top

α

11°

12°

13°

Mold Draft Angle Bottom

β

11°

12°

13°

Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Chamfers at corners are optional; size may vary.
3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-076B

DS39632D-page 406

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
44-Lead Plastic Quad Flat, No Lead Package (ML) – 8x8 mm Body [QFN]
Note:

For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D

D2

EXPOSED
PAD

e
E
E2
b
2

2
1
N

1
N

NOTE 1TOP VIEWK

L
BOTTOM VIEW

A
A3

A1
Units
Dimension Limits
Number of Pins

MILLIMETERS
MIN

N

NOM

MAX

44

Pitch

e

Overall Height

A

0.80

0.65 BSC
0.90

1.00

Standoff

A1

0.00

0.02

0.05

Contact Thickness

A3

0.20 REF

Overall Width

E

Exposed Pad WidthE2

8.00 BSC

Overall Length

D

Exposed Pad Length

D2

6.30

6.45

6.80

Contact Width

b

0.25

0.30

0.38

Contact Length

L

0.30

0.40

0.50

Contact-to-Exposed Pad

K

0.20

–

–

6.30

6.45

6.80

8.00 BSC

Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated.
3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-103B© 2007 Microchip Technology Inc.

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PIC18F2455/2550/4455/4550
NOTES:DS39632D-page 408

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
APPENDIX A:REVISION HISTORY

Revision D (January 2007)
This revision includes updates to the packaging
diagrams.

Revision A (May 2004)
Original data sheet for PIC18F2455/2550/4455/4550
devices.

APPENDIX B:

Revision B (October 2004)
This revision includes updates to the Electrical Specifications in Section 28.0 “Electrical Characteristics”
and includes minor corrections to the data sheet text.

DEVICE
DIFFERENCES

The differences between the devices listed in this data
sheet are shown in Table B-1.

Revision C (February 2006)
This revision includes updates to Section 19.0 “Master
Synchronous Serial Port (MSSP) Module”,
Section 20.0 “Enhanced Universal Synchronous
Asynchronous Receiver Transmitter (EUSART)” andthe Electrical Specifications in Section 28.0 “Electrical
Characteristics” and includes minor corrections to thedata sheet text.

TABLE B-1:

DEVICE DIFFERENCES

Features

PIC18F2455

PIC18F2550

PIC18F4455

PIC18F4550

Program Memory (Bytes)

24576

32768

24576

32768

Program Memory (Instructions)

12288

16384

12288

16384

20

20

Interrupt Sources
I/O Ports

19

19

Ports A, B, C, (E)Ports A, B, C, (E)Ports A, B, C, D, E Ports A, B, C, D, E

Capture/Compare/PWM Modules

2

2

1

1

Enhanced Capture/Compare/
PWM Modules

0

0

1

1

Parallel Communications (SPP)

No

No

Yes

Yes

10-Bit Analog-to-Digital Module

10 input channels

10 input channels

13 input channels

13 input channels

28-pin PDIP
28-pin SOIC

28-pin PDIP
28-pin SOIC

40-pin PDIP
44-pin TQFP
44-pin QFN

40-pin PDIP
44-pin TQFP
44-pin QFNPackages© 2007 Microchip Technology Inc.

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PIC18F2455/2550/4455/4550
APPENDIX C:CONVERSIONCONSIDERATIONSAPPENDIX D:This appendix discusses the considerations forconverting from previous versions of a device to theones listed in this data sheet. Typically, these changes
are due to the differences in the process technology
used. An example of this type of conversion is from a
PIC16C74A to a PIC16C74B.
Not Applicable

DS39632D-page 410

MIGRATION FROMBASELINE TO
ENHANCED DEVICES

This section discusses how to migrate from a Baseline
device (i.e., PIC16C5X) to an Enhanced MCU device(i.e., PIC18FXXX).
The following are the list of modifications over the
PIC16C5X microcontroller family:
Not Currently Available

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
APPENDIX E:MIGRATION FROM
MID-RANGE TO
ENHANCED DEVICES

A detailed discussion of the differences between the
mid-range MCU devices (i.e., PIC16CXXX) and theenhanced devices (i.e., PIC18FXXX) is provided in
AN716, “Migrating Designs from PIC16C74A/74B to
PIC18C442”. The changes discussed, while device
specific, are generally applicable to all mid-range toenhanced device migrations.

APPENDIX F:MIGRATION FROMHIGH-END TOENHANCED DEVICES

A detailed discussion of the migration pathway anddifferences between the high-end MCU devices (i.e.,
PIC17CXXX) and the enhanced devices (i.e.,
PIC18FXXX) is provided in AN726, “PIC17CXXX to
PIC18CXXX Migration”. This Application Note isavailable as Literature Number DS00726.

This Application Note is available as Literature Number
DS00716.

© 2007 Microchip Technology Inc.

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NOTES:DS39632D-page 412

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PIC18F2455/2550/4455/4550
INDEX
A
A/D ................................................................................... 259
Acquisition Requirements ........................................ 264
ADCON0 Register .................................................... 259
ADCON1 Register .................................................... 259
ADCON2 Register .................................................... 259
ADRESH Register ............................................ 259, 262
ADRESL Register .................................................... 259
Analog Port Pins, Configuring .................................. 266
Associated Registers ............................................... 268
Configuring the Module ............................................ 263
Conversion Clock (TAD) ........................................... 265
Conversion Requirements ....................................... 398
Conversion Status (GO/DONE Bit) .......................... 262
Conversions ............................................................. 267
Converter Characteristics ........................................ 397
Converter Interrupt, Configuring .............................. 263
Discharge ................................................................. 267
Operation in Power-Managed Modes ...................... 266
Selecting and Configuring
Acquisition Time .............................................. 265
Special Event Trigger (CCP2) .................................. 268
Special Event Trigger (ECCP) ................................. 150
Use of the CCP2 Trigger .......................................... 268
Absolute Maximum Ratings ............................................. 361
AC (Timing) Characteristics ............................................. 378
Load Conditions for Device Timing
Specifications ................................................... 379
Parameter Symbology ............................................. 378
Temperature and Voltage Specifications ................. 379
Timing Conditions .................................................... 379
AC Characteristics
Internal RC Accuracy ............................................... 381
Access Bank
Mapping with Indexed Literal Offset Mode ................. 77
ACKSTAT ........................................................................ 227
ACKSTAT Status Flag ..................................................... 227
ADCON0 Register ............................................................ 259
GO/DONE Bit ........................................................... 262
ADCON1 Register ............................................................ 259
ADCON2 Register ............................................................ 259
ADDFSR .......................................................................... 350
ADDLW ............................................................................ 313
ADDULNK ........................................................................ 350
ADDWF ............................................................................ 313
ADDWFC ......................................................................... 314
ADRESH Register ............................................................ 259
ADRESL Register .................................................... 259, 262
Analog-to-Digital Converter. See A/D.
and BSR ............................................................................. 77
ANDLW ............................................................................ 314
ANDWF ............................................................................ 315
Assembler
MPASM Assembler .................................................. 358

B
Baud Rate Generator ....................................................... 223
BC .................................................................................... 315
BCF .................................................................................. 316
BF .................................................................................... 227
BF Status Flag ................................................................. 227© 2007 Microchip Technology Inc.

Block Diagrams
A/D ........................................................................... 262
Analog Input Model .................................................. 263
Baud Rate Generator .............................................. 223
Capture Mode Operation ......................................... 143
Comparator Analog Input Model .............................. 273
Comparator I/O Operating Modes ........................... 270
Comparator Output .................................................. 272
Comparator Voltage Reference ............................... 276
Comparator Voltage Reference Output
Buffer Example ................................................ 277
Compare Mode Operation ....................................... 144
Device Clock .............................................................. 24
Enhanced PWM ....................................................... 151
EUSART Receive .................................................... 251
EUSART Transmit ................................................... 248
External Power-on Reset Circuit(Slow VDD Power-up) ........................................ 45
Fail-Safe Clock Monitor ........................................... 300
Generic I/O Port ....................................................... 111
High/Low-Voltage Detect with External Input .......... 280
MSSP (I2C Master Mode) ........................................ 221
MSSP (I2C Mode) .................................................... 202
MSSP (SPI Mode) ................................................... 193
On-Chip Reset Circuit ................................................ 43
PIC18F2455/2550 ..................................................... 10
PIC18F4455/4550 ..................................................... 11
PLL (HS Mode) .......................................................... 26
PWM Operation (Simplified) .................................... 146
Reads from Flash Program Memory ......................... 83
Single Comparator ................................................... 271
SPP Data Path ........................................................ 187
Table Read Operation ............................................... 79
Table Write Operation ............................................... 80
Table Writes to Flash Program Memory .................... 85
Timer0 in 16-Bit Mode ............................................. 126
Timer0 in 8-Bit Mode ............................................... 126
Timer1 ..................................................................... 130
Timer1 (16-Bit Read/Write Mode) ............................ 130
Timer2 ..................................................................... 136
Timer3 ..................................................................... 138
Timer3 (16-Bit Read/Write Mode) ............................ 138
USB Interrupt Logic ................................................. 177
USB Peripheral and Options ................................... 163
Watchdog Timer ...................................................... 297
BN .................................................................................... 316
BNC ................................................................................. 317
BNN ................................................................................. 317
BNOV .............................................................................. 318
BNZ ................................................................................. 318
BOR. See Brown-out Reset.
BOV ................................................................................. 321
BRA ................................................................................. 319
Break Character (12-Bit) Transmit and Receive .............. 253
BRG. See Baud Rate Generator.
Brown-out Reset (BOR) ..................................................... 46
Detecting ................................................................... 46
Disabling in Sleep Mode ............................................ 46
Software Enabled ...................................................... 46
BSF .................................................................................. 319
BTFSC ............................................................................. 320
BTFSS ............................................................................. 320
BTG ................................................................................. 321
BZ .................................................................................... 322

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PIC18F2455/2550/4455/4550
C
C Compilers
MPLAB C18 ............................................................. 358
MPLAB C30 ............................................................. 358
CALL ................................................................................ 322
CALLW ............................................................................. 351
Capture (CCP Module) ..................................................... 143
CCP Pin Configuration ............................................. 143
CCPRxH:CCPRxL Registers ................................... 143
Prescaler .................................................................. 143
Software Interrupt .................................................... 143
Timer1/Timer3 Mode Selection ................................ 143
Capture (ECCP Module) .................................................. 150
Capture/Compare (CCP Module)
Associated Registers ............................................... 145
Capture/Compare/PWM (CCP) ........................................ 141
Capture Mode. See Capture.
CCP Mode and Timer Resources ............................ 142
CCP2 Pin Assignment ............................................. 142
CCPRxH Register .................................................... 142
CCPRxL Register ..................................................... 142
Compare Mode. See Compare.
Interaction of Two CCP Modules forTimer Resources .............................................. 142
Module Configuration ............................................... 142
Clock Sources .................................................................... 31
Effects of Power-Managed Modes ............................. 33
Selecting the 31 kHz Source ...................................... 31
Selection Using OSCCON Register ........................... 31
CLRF ................................................................................ 323
CLRWDT .......................................................................... 323
Code Examples
16 x 16 Signed Multiply Routine ................................ 96
16 x 16 Unsigned Multiply Routine ............................ 96
8 x 8 Signed Multiply Routine .................................... 95
8 x 8 Unsigned Multiply Routine ................................ 95
Changing Between Capture Prescalers ................... 143
Computed GOTO Using an Offset Value ................... 60
Data EEPROM Read ................................................. 91
Data EEPROM Refresh Routine ................................ 92
Data EEPROM Write ................................................. 91
Erasing a Flash Program Memory Row ..................... 84
Fast Register Stack .................................................... 60
How to Clear RAM (Bank 1) Using
Indirect Addressing ............................................ 72
Implementing a Real-Time Clock Using aTimer1 Interrupt Service .................................. 133
Initializing PORTA .................................................... 111
Initializing PORTB .................................................... 114
Initializing PORTC .................................................... 117
Initializing PORTD .................................................... 120
Initializing PORTE .................................................... 123
Loading the SSPBUF (SSPSR) Register ................. 196
Reading a Flash Program Memory Word .................. 83
Saving STATUS, WREG and BSR
Registers in RAM ............................................. 109
Writing to Flash Program Memory ....................... 86–87
Code Protection ............................................................... 285
COMF ............................................................................... 324
Comparator ...................................................................... 269
Analog Input Connection Considerations ................. 273
Associated Registers ............................................... 273
Configuration ............................................................ 270
Effects of a Reset ..................................................... 272
Interrupts .................................................................. 272

DS39632D-page 414

Operation ................................................................. 271
Operation During Sleep ........................................... 272
Outputs .................................................................... 271
Reference ................................................................ 271
External Signal ................................................ 271
Internal Signal .................................................. 271
Response Time ........................................................ 271
Comparator Specifications ............................................... 375
Comparator Voltage Reference ....................................... 275
Accuracy and Error .................................................. 276
Associated Registers ............................................... 277
Configuring .............................................................. 275
Connection Considerations ...................................... 276
Effects of a Reset .................................................... 276
Operation During Sleep ........................................... 276
Compare (CCP Module) .................................................. 144
CCP Pin Configuration ............................................. 144
CCPRx Register ...................................................... 144
Software Interrupt .................................................... 144
Special Event Trigger .............................. 139, 144, 268
Timer1/Timer3 Mode Selection ................................ 144
Compare (ECCP Module) ................................................ 150
Special Event Trigger .............................................. 150
Configuration Bits ............................................................ 286
Configuration Register Protection .................................... 305
Context Saving During Interrupts ..................................... 109
Conversion Considerations .............................................. 410
CPFSEQ .......................................................................... 324
CPFSGT .......................................................................... 325
CPFSLT ........................................................................... 325
Crystal Oscillator/Ceramic Resonator ................................ 25
Customer Change Notification Service ............................ 423
Customer Notification Service ......................................... 423
Customer Support ............................................................ 423

D
Data Addressing Modes .................................................... 72
Comparing Addressing Modes with the
Extended Instruction Set Enabled ..................... 76
Direct ......................................................................... 72
Indexed Literal Offset ................................................ 75
Indirect ....................................................................... 72
Inherent and Literal .................................................... 72
Data EEPROM
Code Protection ....................................................... 305
Data EEPROM Memory ..................................................... 89
Associated Registers ................................................. 93
EECON1 and EECON2 Registers ............................. 89
Operation During Code-Protect ................................. 92
Protection Against Spurious Write ............................. 92
Reading ..................................................................... 91
Using ......................................................................... 92
Write Verify ................................................................ 91
Writing ....................................................................... 91
Data Memory ..................................................................... 63
Access Bank .............................................................. 65
and the Extended Instruction Set .............................. 75
Bank Select Register (BSR) ...................................... 63
General Purpose Registers ....................................... 65
Map for PIC18F2455/2550/4455/4550 Devices ......... 64
Special Function Registers ........................................ 66
Map .................................................................... 66
USB RAM .................................................................. 63
DAW ................................................................................ 326
DC and AC Characteristics
Graphs and Tables .................................................. 399

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
DC Characteristics ........................................................... 372
Power-Down and Supply Current ............................ 364
Supply Voltage ......................................................... 363
DCFSNZ .......................................................................... 327
DECF ............................................................................... 326
DECFSZ ........................................................................... 327
Dedicated ICD/ICSP Port ................................................. 305
Development Support ...................................................... 357
Device Differences ........................................................... 409
Device Overview .................................................................. 7
Features (table) ............................................................ 9
New Core Features ...................................................... 7
Other Special Features ................................................ 8
Device Reset Timers .......................................................... 47
Oscillator Start-up Timer (OST) ................................. 47
PLL Lock Time-out ..................................................... 47
Power-up Timer (PWRT) ........................................... 47
Direct Addressing ............................................................... 73

Synchronous Slave Mode ........................................ 257
Associated Registers, Receive ........................ 258
Associated Registers, Transmit ....................... 257
Reception ........................................................ 258
Transmission ................................................... 257
Extended Instruction Set ................................................. 349
ADDFSR .................................................................. 350
ADDULNK ............................................................... 350
and Using MPLAB IDE Tools .................................. 356
CALLW .................................................................... 351
Considerations for Use ............................................ 354
MOVSF .................................................................... 351
MOVSS .................................................................... 352
PUSHL ..................................................................... 352
SUBFSR .................................................................. 353
SUBULNK ................................................................ 353
Syntax ...................................................................... 349
External Clock Input ........................................................... 26

E

F

Effect on Standard PIC Instructions ................................... 75
Effect on Standard PIC MCU Instructions ........................ 354
Electrical Characteristics .................................................. 361
Enhanced Capture/Compare/PWM (ECCP) .................... 149
Associated Registers ............................................... 162
Capture and Compare Modes .................................. 150
Capture Mode. See Capture (ECCP Module).
Outputs and Configuration ....................................... 150
Pin Configurations for ECCP1 ................................. 150
PWM Mode. See PWM (ECCP Module).
Standard PWM Mode ............................................... 150
Timer Resources ...................................................... 150
Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART). See EUSART.
Equations
A/D Acquisition Time ................................................ 264
A/D Minimum Charging Time ................................... 264
Calculating the Minimum Required
A/D Acquisition Time ....................................... 264
Errata ................................................................................... 5
EUSART
Asynchronous Mode ................................................ 247
12-Bit Break Transmit and Receive ................. 253
Associated Registers, Receive ........................ 251
Associated Registers, Transmit ....................... 249
Auto-Wake-up on Sync Break Character ......... 252
Receiver ........................................................... 250
Setting up 9-Bit Mode with
Address Detect ........................................ 250
Transmitter ....................................................... 247
Baud Rate Generator
Operation in Power-Managed Modes .............. 241
Baud Rate Generator (BRG) .................................... 241
Associated Registers ....................................... 242
Auto-Baud Rate Detect .................................... 245
Baud Rate Error, Calculating ........................... 242
Baud Rates, Asynchronous Modes ................. 243
High Baud Rate Select (BRGH Bit) ................. 241
Sampling .......................................................... 241
Synchronous Master Mode ...................................... 254
Associated Registers, Receive ........................ 256
Associated Registers, Transmit ....................... 255
Reception ......................................................... 256
Transmission ................................................... 254

Fail-Safe Clock Monitor ........................................... 285, 300
Exiting the Operation ............................................... 300
Interrupts in Power-Managed Modes ...................... 301
POR or Wake-up from Sleep ................................... 301
WDT During Oscillator Failure ................................. 300
Fast Register Stack ........................................................... 60
Firmware Instructions ...................................................... 307
Flash Program Memory ..................................................... 79
Associated Registers ................................................. 87
Control Registers ....................................................... 80
EECON1 and EECON2 ..................................... 80
TABLAT (Table Latch) Register ........................ 82
TBLPTR (Table Pointer) Register ...................... 82
Erase Sequence ........................................................ 84
Erasing ...................................................................... 84
Operation During Code-Protect ................................. 87
Protection Against Spurious Writes ........................... 87
Reading ..................................................................... 83
Table PointerBoundaries Based on Operation ....................... 82
Table Pointer Boundaries .......................................... 82
Table Reads and Table Writes .................................. 79
Unexpected Termination of Write .............................. 87
Write Sequence ......................................................... 85
Write Verify ................................................................ 87
Writing To .................................................................. 85
FSCM. See Fail-Safe Clock Monitor.

© 2007 Microchip Technology Inc.

G
GOTO .............................................................................. 328

H
Hardware Multiplier ............................................................ 95
Introduction ................................................................ 95
Operation ................................................................... 95
Performance Comparison .......................................... 95

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PIC18F2455/2550/4455/4550
High/Low-Voltage Detect ................................................. 279
Applications .............................................................. 282
Associated Registers ............................................... 283
Characteristics ......................................................... 377
Current Consumption ............................................... 281
Effects of a Reset ..................................................... 283
Operation ................................................................. 280
During Sleep .................................................... 283
Setup ........................................................................ 281
Start-up Time ........................................................... 281
Typical Application ................................................... 282
HLVD. See High/Low-Voltage Detect.

I
I/O Ports ........................................................................... 111
I2C Mode (MSSP)
Acknowledge Sequence Timing ............................... 230
Associated Registers ............................................... 236
Baud Rate Generator ............................................... 223
Bus CollisionDuring a Repeated Start Condition .................. 234
During a Stop Condition ................................... 235
Clock Arbitration ....................................................... 224
Clock Stretching ....................................................... 216
10-Bit Slave Receive Mode (SEN = 1) ............. 216
10-Bit Slave Transmit Mode ............................. 216
7-Bit Slave Receive Mode (SEN = 1) ............... 216
7-Bit Slave Transmit Mode ............................... 216
Clock Synchronization and the CKP Bit ................... 217
Effect of a Reset ...................................................... 231
General Call Address Support ................................. 220
I2C Clock Rate w/BRG ............................................. 223
Master Mode ............................................................ 221
Operation ......................................................... 222
Reception ......................................................... 227
Repeated Start Condition Timing ..................... 226
Start Condition Timing ..................................... 225
Transmission .................................................... 227
Transmit Sequence .......................................... 222
Multi-Master Communication, Bus Collision
and Arbitration .................................................. 231
Multi-Master Mode ................................................... 231
Operation ................................................................. 207
Read/Write Bit Information (R/W Bit) ............... 207, 209
Registers .................................................................. 202
Serial Clock (RB1/AN10/INT1/SCK/SCL) ................ 209
Slave Mode .............................................................. 207
Addressing ....................................................... 207
Addressing Masking ......................................... 208
Reception ......................................................... 209
Transmission .................................................... 209
Sleep Operation ....................................................... 231
Stop Condition Timing .............................................. 230
ID Locations ............................................................. 285, 305
Idle Modes .......................................................................... 39
INCF ................................................................................. 328
INCFSZ ............................................................................ 329
In-Circuit Debugger .......................................................... 305
In-Circuit Serial Programming (ICSP) ...................... 285, 305
Indexed Literal Offset Addressing
and Standard PIC18 Instructions ............................. 354
Indexed Literal Offset Mode ................................. 75, 77, 354
Indirect Addressing ............................................................ 73
INFSNZ ............................................................................ 329
Initialization Conditions for all Registers ...................... 51–55

DS39632D-page 416

Instruction Cycle ................................................................ 61
Clocking Scheme ....................................................... 61
Flow/Pipelining ........................................................... 61
Instruction Set .................................................................. 307
ADDLW .................................................................... 313
ADDWF .................................................................... 313
ADDWF (Indexed Literal Offset mode) .................... 355
ADDWFC ................................................................. 314
ANDLW .................................................................... 314
ANDWF .................................................................... 315
BC ............................................................................ 315
BCF ......................................................................... 316
BN ............................................................................ 316
BNC ......................................................................... 317
BNN ......................................................................... 317
BNOV ...................................................................... 318
BNZ ......................................................................... 318
BOV ......................................................................... 321
BRA ......................................................................... 319
BSF .......................................................................... 319
BSF (Indexed Literal Offset mode) .......................... 355
BTFSC ..................................................................... 320
BTFSS ..................................................................... 320
BTG ......................................................................... 321
BZ ............................................................................ 322
CALL ........................................................................ 322
CLRF ....................................................................... 323
CLRWDT ................................................................. 323
COMF ...................................................................... 324
CPFSEQ .................................................................. 324
CPFSGT .................................................................. 325
CPFSLT ................................................................... 325
DAW ........................................................................ 326
DCFSNZ .................................................................. 327
DECF ....................................................................... 326
DECFSZ .................................................................. 327
General Format ........................................................ 309
GOTO ...................................................................... 328
INCF ........................................................................ 328
INCFSZ .................................................................... 329
INFSNZ .................................................................... 329
IORLW ..................................................................... 330
IORWF ..................................................................... 330
LFSR ....................................................................... 331
MOVF ...................................................................... 331
MOVFF .................................................................... 332
MOVLB .................................................................... 332
MOVLW ................................................................... 333
MOVWF ................................................................... 333
MULLW .................................................................... 334
MULWF .................................................................... 334
NEGF ....................................................................... 335
NOP ......................................................................... 335
Opcode Field Descriptions ....................................... 308
POP ......................................................................... 336
PUSH ....................................................................... 336
RCALL ..................................................................... 337
RESET ..................................................................... 337
RETFIE .................................................................... 338
RETLW .................................................................... 338
RETURN .................................................................. 339
RLCF ....................................................................... 339
RLNCF ..................................................................... 340
RRCF ....................................................................... 340
RRNCF .................................................................... 341

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
SETF ........................................................................ 341
SETF (Indexed Literal Offset mode) ........................ 355
SLEEP ..................................................................... 342
Standard Instructions ............................................... 307
SUBFWB .................................................................. 342
SUBLW .................................................................... 343
SUBWF .................................................................... 343
SUBWFB .................................................................. 344
SWAPF .................................................................... 344
TBLRD ..................................................................... 345
TBLWT ..................................................................... 346
TSTFSZ ................................................................... 347
XORLW .................................................................... 347
XORWF .................................................................... 348
INTCON Register
RBIF Bit .................................................................... 114
INTCON Registers ............................................................. 99
Inter-Integrated Circuit. See I2C.
Internal Oscillator Block ..................................................... 27
Adjustment ................................................................. 27
INTHS, INTXT, INTCKO and INTIO Modes ............... 27
OSCTUNE Register ................................................... 27
Internal RC Oscillator
Use with WDT .......................................................... 297
Internet Address ............................................................... 423
Interrupt Sources ............................................................. 285
A/D Conversion Complete ....................................... 263
Capture Complete (CCP) ......................................... 143
Compare Complete (CCP) ....................................... 144
Interrupt-on-Change (RB7:RB4) .............................. 114
INTn Pin ................................................................... 109
PORTB, Interrupt-on-Change .................................. 109
TMR0 ....................................................................... 109
TMR0 Overflow ........................................................ 127
TMR1 Overflow ........................................................ 129
TMR2 to PR2 Match (PWM) ............................ 146, 151
TMR3 Overflow ................................................ 137, 139
Interrupts ............................................................................ 97
Logic (diagram) .......................................................... 98
USB ............................................................................ 97
Interrupts, Flag Bits
Interrupt-on-Change (RB7:RB4) Flag
(RBIF Bit) ......................................................... 114
INTOSC Frequency Drift .................................................... 27
INTOSC, INTRC. See Internal Oscillator Block.
IORLW ............................................................................. 330
IORWF ............................................................................. 330
IPR Registers ................................................................... 106

L
LFSR ................................................................................ 331
Low-Voltage ICSP Programming. See Single-Supply
ICSP Programming.

M
Master Clear Reset (MCLR) .............................................. 45
Master Synchronous Serial Port (MSSP). See MSSP.
Memory Organization ......................................................... 57
Data Memory ............................................................. 63
Program Memory ....................................................... 57
Memory Programming Requirements .............................. 374
Microchip Internet Web Site ............................................. 423
Migration from Baseline to Enhanced Devices ................ 410
Migration from High-End to Enhanced Devices ............... 411
Migration from Mid-Range to Enhanced Devices ............ 411© 2007 Microchip Technology Inc.

MOVF .............................................................................. 331
MOVFF ............................................................................ 332
MOVLB ............................................................................ 332
MOVLW ........................................................................... 333
MOVSF ............................................................................ 351
MOVSS ............................................................................ 352
MOVWF ........................................................................... 333
MPLAB ASM30 Assembler, Linker, Librarian .................. 358
MPLAB ICD 2 In-Circuit Debugger .................................. 359
MPLAB ICE 2000 High-Performance
Universal In-Circuit Emulator ................................... 359
MPLAB ICE 4000 High-Performance
Universal In-Circuit Emulator ................................... 359
MPLAB Integrated Development
Environment Software ............................................. 357
MPLAB PM3 Device Programmer ................................... 359
MPLINK Object Linker/MPLIB Object Librarian ............... 358
MSSP
ACK Pulse ....................................................... 207, 209
Control Registers (general) ..................................... 193
I2C Mode. See I2C Mode.
Module Overview ..................................................... 193
SPI Master/Slave Connection .................................. 197
SPI Mode. See SPI Mode.
SSPBUF .................................................................. 198
SSPSR .................................................................... 198
MULLW ............................................................................ 334
MULWF ............................................................................ 334

N
NEGF ............................................................................... 335
NOP ................................................................................. 335

O
Oscillator Configuration ..................................................... 23
EC .............................................................................. 23
ECIO .......................................................................... 23
ECPIO ....................................................................... 23
ECPLL ....................................................................... 23
HS .............................................................................. 23
HSPLL ....................................................................... 23
INTCKO ..................................................................... 23
Internal Oscillator Block ............................................. 27
INTHS ........................................................................ 23
INTIO ......................................................................... 23
INTXT ........................................................................ 23
Oscillator Modes and USB Operation ........................ 23
XT .............................................................................. 23
XTPLL ........................................................................ 23
Oscillator Selection .......................................................... 285
Oscillator Settings for USB ................................................ 29
Oscillator Start-up Timer (OST) ................................... 33, 47
Oscillator Switching ........................................................... 31
Oscillator Transitions ......................................................... 32
Oscillator, Timer1 ..................................................... 129, 139
Oscillator, Timer3 ............................................................. 137

P
Packaging Information ..................................................... 401
Details ...................................................................... 403
Marking .................................................................... 401
PICSTART Plus Development Programmer .................... 360
PIE Registers ................................................................... 104

Preliminary

DS39632D-page 417

PIC18F2455/2550/4455/4550
Pin Functions
MCLR/VPP/RE3 .................................................... 12, 16
NC/ICCK/ICPGC ........................................................ 21
NC/ICDT/ICPGD ........................................................ 21
NC/ICPORTS ............................................................. 21
NC/ICRST/ICVPP ....................................................... 21
OSC1/CLKI .......................................................... 12, 16
OSC2/CLKO/RA6 ................................................ 12, 16
RA0/AN0 .............................................................. 13, 17
RA1/AN1 .............................................................. 13, 17
RA2/AN2/VREF-/CVREF ........................................ 13, 17
RA3/AN3/VREF+ ................................................... 13, 17
RA4/T0CKI/C1OUT/RCV ..................................... 13, 17
RA5/AN4/SS/HLVDIN/C2OUT ............................. 13, 17
RB0/AN12/INT0/FLT0/SDI/SDA .......................... 14, 18
RB1/AN10/INT1/SCK/SCL ................................... 14, 18
RB2/AN8/INT2/VMO ............................................ 14, 18
RB3/AN9/CCP2/VPO ........................................... 14, 18
RB4/AN11/KBI0 ......................................................... 14
RB4/AN11/KBI0/CSSPP ............................................ 18
RB5/KBI1/PGM .................................................... 14, 18
RB6/KBI2/PGC .................................................... 14, 18
RB7/KBI3/PGD .................................................... 14, 18
RC0/T1OSO/T13CKI ........................................... 15, 19
RC1/T1OSI/CCP2/UOE ....................................... 15, 19
RC2/CCP1 ................................................................. 15
RC2/CCP1/P1A ......................................................... 19
RC4/D-/VM ........................................................... 15, 19
RC5/D+/VP .......................................................... 15, 19
RC6/TX/CK .......................................................... 15, 19
RC7/RX/DT/SDO ................................................. 15, 19
RD0/SPP0 .................................................................. 20
RD1/SPP1 .................................................................. 20
RD2/SPP2 .................................................................. 20
RD3/SPP3 .................................................................. 20
RD4/SPP4 .................................................................. 20
RD5/SPP5/P1B .......................................................... 20
RD6/SPP6/P1C .......................................................... 20
RD7/SPP7/P1D .......................................................... 20
RE0/AN5/CK1SPP ..................................................... 21
RE1/AN6/CK2SPP ..................................................... 21
RE2/AN7/OESPP ....................................................... 21
VDD ....................................................................... 15, 21
VSS ....................................................................... 15, 21
VUSB ..................................................................... 15, 21
Pinout I/O Descriptions
PIC18F2455/2550 ...................................................... 12
PIC18F4455/4550 ...................................................... 16
PIR Registers ................................................................... 102
PLL Frequency Multiplier ................................................... 26
HSPLL, XTPLL, ECPLL and ECPIO
Oscillator Modes ................................................ 26
PLL Lock Time-out ............................................................. 47
POP .................................................................................. 336
POR. See Power-on Reset.
PORTA
Associated Registers ............................................... 113
I/O Summary ............................................................ 112
LATA Register .......................................................... 111
PORTA Register ...................................................... 111
TRISA Register ........................................................ 111

DS39632D-page 418

PORTB
Associated Registers ............................................... 116
I/O Summary ............................................................ 115
LATB Register ......................................................... 114
PORTB Register ...................................................... 114
RB1/AN10/INT1/SCK/SCL Pin ................................ 209
RB7:RB4 Interrupt-on-Change Flag (RBIF Bit) ........ 114
TRISB Register ........................................................ 114
PORTC
Associated Registers ............................................... 119
I/O Summary ............................................................ 118
LATC Register ......................................................... 117
PORTC Register ...................................................... 117
TRISC Register ........................................................ 117
PORTD
Associated Registers ............................................... 122
I/O Summary ............................................................ 121
LATD Register ......................................................... 120
PORTD Register ...................................................... 120
TRISD Register ........................................................ 120
PORTE
Associated Registers ............................................... 124
I/O Summary ............................................................ 124
LATE Register ......................................................... 123
PORTE Register ...................................................... 123
TRISE Register ........................................................ 123
Postscaler, WDT
Assignment (PSA Bit) .............................................. 127
Rate Select (T0PS2:T0PS0 Bits) ............................. 127
Power-Managed Modes ..................................................... 35
and Multiple Sleep Commands .................................. 36
and PWM Operation ................................................ 161
Clock Sources ............................................................ 35
Clock Transitions and Status Indicators .................... 36
Entering ..................................................................... 35
Exiting Idle and Sleep Modes .................................... 41
by Interrupt ........................................................ 41
by Reset ............................................................ 41
by WDT Time-out .............................................. 41
Without an Oscillator Start-up Delay ................. 42
Idle ............................................................................. 39
Idle Modes
PRI_IDLE ........................................................... 40
RC_IDLE ........................................................... 41
SEC_IDLE ......................................................... 40
Run Modes ................................................................ 36
PRI_RUN ........................................................... 36
RC_RUN ............................................................ 37
SEC_RUN ......................................................... 36
Selecting .................................................................... 35
Sleep ......................................................................... 39
Summary (table) ........................................................ 35
Power-on Reset (POR) ...................................................... 45
Oscillator Start-up Timer (OST) ................................. 47
Power-up Timer (PWRT) ........................................... 47
Time-out Sequence ................................................... 47
Power-up Delays ............................................................... 33
Power-up Timer (PWRT) ............................................. 33, 47
Prescaler
Timer2 ..................................................................... 152
Prescaler, Timer0 ............................................................ 127
Assignment (PSA Bit) .............................................. 127
Rate Select (T0PS2:T0PS0 Bits) ............................. 127

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
Prescaler, Timer2 ............................................................. 147
PRI_IDLE Mode ................................................................. 40
PRI_RUN Mode ................................................................. 36
Program Counter ............................................................... 58
PCL, PCH and PCU Registers ................................... 58
PCLATH and PCLATU Registers .............................. 58
Program Memory
and the Extended Instruction Set ............................... 75
Code Protection ....................................................... 303
Instructions ................................................................. 62
Two-Word .......................................................... 62
Interrupt Vector .......................................................... 57
Look-up Tables .......................................................... 60
Map and Stack (diagram) ........................................... 57
Reset Vector .............................................................. 57
Program Verification and Code Protection ....................... 302
Associated Registers ............................................... 302
Programming, Device Instructions ................................... 307
Pulse-Width Modulation. See PWM (CCP Module)
and PWM (ECCP Module).
PUSH ............................................................................... 336
PUSH and POP Instructions .............................................. 59
PUSHL ............................................................................. 352
PWM (CCP Module)
Associated Registers ............................................... 148
Auto-Shutdown (CCP1 Only) ................................... 147
Duty Cycle ................................................................ 146
Example Frequencies/Resolutions .......................... 147
Period ....................................................................... 146
Setup for PWM Operation ........................................ 147
TMR2 to PR2 Match ................................................ 146
PWM (ECCP Module) ...................................................... 151
CCPR1H:CCPR1L Registers ................................... 151
Direction Change in Full-Bridge
Output Mode .................................................... 156
Duty Cycle ................................................................ 152
Effects of a Reset ..................................................... 161
Enhanced PWM Auto-Shutdown ............................. 158
Enhanced PWM Mode ............................................. 151
Example Frequencies/Resolutions .......................... 152
Full-Bridge Application Example .............................. 156
Full-Bridge Mode ...................................................... 155
Half-Bridge Mode ..................................................... 154
Half-Bridge Output Mode
Applications Example ...................................... 154
Operation in Power-Managed Modes ...................... 161
Operation with Fail-Safe Clock Monitor ................... 161
Output Configurations .............................................. 152
Output Relationships (Active-High) .......................... 153
Output Relationships (Active-Low) ........................... 153
Period ....................................................................... 151
Programmable Dead-Band Delay ............................ 158
Setup for PWM Operation ........................................ 161
Start-up Considerations ........................................... 160
TMR2 to PR2 Match ................................................ 151

Q
Q Clock .................................................................... 147, 152

R
RAM. See Data Memory.
RC_IDLE Mode .................................................................. 41
RC_RUN Mode .................................................................. 37
RCALL ............................................................................. 337
RCON Register
Bit Status During Initialization .................................... 50© 2007 Microchip Technology Inc.

Reader Response ............................................................ 424
Register File ....................................................................... 65
Register File Summary ................................................ 67–70
Registers
ADCON0 (A/D Control 0) ......................................... 259
ADCON1 (A/D Control 1) ......................................... 260
ADCON2 (A/D Control 2) ......................................... 261
BAUDCON (Baud Rate Control) .............................. 240
BDnSTAT (Buffer Descriptor n Status,
CPU Mode) ...................................................... 173
BDnSTAT (Buffer Descriptor n Status,
SIE Mode) ....................................................... 174
CCP1CON (ECCP Control) ..................................... 149
CCPxCON (Standard CCPx Control) ...................... 141
CMCON (Comparator Control) ................................ 269
CONFIG1H (Configuration 1 High) .......................... 288
CONFIG1L (Configuration 1 Low) ........................... 287
CONFIG2H (Configuration 2 High) .......................... 290
CONFIG2L (Configuration 2 Low) ........................... 289
CONFIG3H (Configuration 3 High) .......................... 291
CONFIG4L (Configuration 4 Low) ........................... 292
CONFIG5H (Configuration 5 High) .......................... 293
CONFIG5L (Configuration 5 Low) ........................... 293
CONFIG6H (Configuration 6 High) .......................... 294
CONFIG6L (Configuration 6 Low) ........................... 294
CONFIG7H (Configuration 7 High) .......................... 295
CONFIG7L (Configuration 7 Low) ........................... 295
CVRCON (Comparator Voltage
Reference Control) .......................................... 275
DEVID1 (Device ID 1) .............................................. 296
DEVID2 (Device ID 2) .............................................. 296
ECCP1AS (Enhanced Capture/Compare/PWM
Auto-Shutdown Control) .................................. 159
ECCP1DEL (PWM Dead-Band Delay) .................... 158
EECON1 (Data EEPROM Control 1) ................... 81, 90
HLVDCON (High/Low-Voltage
Detect Control) ................................................ 279
INTCON (Interrupt Control) ....................................... 99
INTCON2 (Interrupt Control 2) ................................ 100
INTCON3 (Interrupt Control 3) ................................ 101
IPR1 (Peripheral Interrupt Priority 1) ....................... 106
IPR2 (Peripheral Interrupt Priority 2) ....................... 107
OSCCON (Oscillator Control) .................................... 32
OSCTUNE (Oscillator Tuning) ................................... 28
PIE1 (Peripheral Interrupt Enable 1) ....................... 104
PIE2 (Peripheral Interrupt Enable 2) ....................... 105
PIR1 (Peripheral Interrupt Request(Flag) 1) ........................................................... 102
PIR2 (Peripheral Interrupt Request(Flag) 2) ........................................................... 103
PORTE .................................................................... 123
RCON (Reset Control) ....................................... 44, 108
RCSTA (Receive Status and Control) ..................... 239
SPPCFG (SPP Configuration) ................................. 188
SPPCON (SPP Control) .......................................... 187
SPPEPS (SPP Endpoint Address
and Status) ...................................................... 191
SSPCON1 (MSSP Control 1, I2C Mode) ................. 204
SSPCON1 (MSSP Control 1, SPI Mode) ................ 195
SSPCON2 (MSSP Control 2, I2C
Master Mode) .................................................. 205
SSPCON2 (MSSP Control 2, I2C
Slave Mode) .................................................... 206
SSPSTAT (MSSP Status, I2C Mode) ...................... 203
SSPSTAT (MSSP Status, SPI Mode) ...................... 194

Preliminary

DS39632D-page 419

PIC18F2455/2550/4455/4550
STATUS ..................................................................... 71
STKPTR (Stack Pointer) ............................................ 59
T0CON (Timer0 Control) .......................................... 125
T1CON (Timer1 Control) .......................................... 129
T2CON (Timer2 Control) .......................................... 135
T3CON (Timer3 Control) .......................................... 137
TXSTA (Transmit Status and Control) ..................... 238
UCFG (USB Configuration) ...................................... 166
UCON (USB Control) ............................................... 164
UEIE (USB Error Interrupt Enable) .......................... 182
UEIR (USB Error Interrupt Status) ........................... 181
UEPn (USB Endpoint n Control) .............................. 169
UIE (USB Interrupt Enable) ...................................... 180
UIR (USB Interrupt Status) ...................................... 178
USTAT (USB Status) ............................................... 168
WDTCON (Watchdog Timer Control) ....................... 298
RESET ............................................................................. 337
Reset State of Registers .................................................... 50
Resets ........................................................................ 43, 285
Brown-out Reset (BOR) ........................................... 285
Oscillator Start-up Timer (OST) ............................... 285
Power-on Reset (POR) ............................................ 285
Power-up Timer (PWRT) ......................................... 285
RETFIE ............................................................................ 338
RETLW ............................................................................. 338
RETURN .......................................................................... 339
Return Address Stack ........................................................ 58
and Associated Registers .......................................... 58
Return Stack Pointer (STKPTR) ........................................ 59
Revision History ............................................................... 409
RLCF ................................................................................ 339
RLNCF ............................................................................. 340
RRCF ............................................................................... 340
RRNCF ............................................................................. 341

S
SCK .................................................................................. 193
SDI ................................................................................... 193
SDO ................................................................................. 193
SEC_IDLE Mode ................................................................ 40
SEC_RUN Mode ................................................................ 36
Serial Clock, SCK ............................................................. 193
Serial Data In (SDI) .......................................................... 193
Serial Data Out (SDO) ..................................................... 193
Serial Peripheral Interface. See SPI Mode.
SETF ................................................................................ 341
Slave Select (SS) ............................................................. 193
SLEEP .............................................................................. 342
Sleep
OSC1 and OSC2 Pin States ...................................... 33
Sleep Mode ........................................................................ 39
Software Simulator (MPLAB SIM) .................................... 358
Special Event Trigger. See Compare (CCP Module).
Special Event Trigger. See Compare (ECCP Module).
Special Features of the CPU ............................................ 285
Special ICPORT Features ................................................ 305
SPI Mode (MSSP)
Associated Registers ............................................... 201
Bus Mode Compatibility ........................................... 201
Effects of a Reset ..................................................... 201
Enabling SPI I/O ...................................................... 197
Master Mode ............................................................ 198
Master/Slave Connection ......................................... 197
Operation ................................................................. 196
Operation in Power-Managed Modes ...................... 201
Serial Clock .............................................................. 193

DS39632D-page 420

Serial Data In ........................................................... 193
Serial Data Out ........................................................ 193
Slave Mode .............................................................. 199
Slave Select ............................................................. 193
Slave Select Synchronization .................................. 199
SPI Clock ................................................................. 198
Typical Connection .................................................. 197
SPP. See Streaming Parallel Port.
SS .................................................................................... 193
SSPOV ............................................................................ 227
SSPOV Status Flag ......................................................... 227
SSPSTAT Register
R/W Bit .................................................................... 209
SSPxSTAT Register
R/W Bit .................................................................... 207
Stack Full/Underflow Resets .............................................. 60
STATUS Register .............................................................. 71
Streaming Parallel Port .................................................... 187
Associated Registers ............................................... 192
Clocking Data .......................................................... 188
Configuration ........................................................... 187
Internal Pull-ups ....................................................... 188
Interrupts ................................................................. 190
Microcontroller Control Setup .................................. 190
Reading from (Microcontroller Mode) ...................... 191
Transfer of Data Between USB SIE
and SPP (diagram) .......................................... 190
USB Control Setup .................................................. 190
Wait States .............................................................. 188
Writing to (Microcontroller Mode) ............................. 190
SUBFSR .......................................................................... 353
SUBFWB ......................................................................... 342
SUBLW ............................................................................ 343
SUBULNK ........................................................................ 353
SUBWF ............................................................................ 343
SUBWFB ......................................................................... 344
SWAPF ............................................................................ 344

T
T0CON Register
PSA Bit .................................................................... 127
T0CS Bit .................................................................. 126
T0PS2:T0PS0 Bits ................................................... 127
T0SE Bit .................................................................. 126
Table Pointer Operations (table) ........................................ 82
Table Reads/Table Writes ................................................. 60
TBLRD ............................................................................. 345
TBLWT ............................................................................. 346
Time-out in Various Situations (table) ................................ 47
Timer0 .............................................................................. 125
16-Bit Mode Timer Reads and Writes ...................... 126
Associated Registers ............................................... 127
Clock Source Edge Select (T0SE Bit) ..................... 126
Clock Source Select (T0CS Bit) ............................... 126
Operation ................................................................. 126
Overflow Interrupt .................................................... 127
Prescaler ................................................................. 127
Switching Assignment ..................................... 127
Prescaler. See Prescaler, Timer0.
Timer1 .............................................................................. 129
16-Bit Read/Write Mode .......................................... 131
Associated Registers ............................................... 133
Interrupt ................................................................... 132
Operation ................................................................. 130

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
Oscillator .......................................................... 129, 131
Layout Considerations ..................................... 132
Low-Power Option ........................................... 131
Using Timer1 as a Clock Source ..................... 131
Overflow Interrupt .................................................... 129
Resetting, Using a Special Event
Trigger Output (CCP) ....................................... 132
Special Event Trigger (ECCP) ................................. 150
TMR1H Register ...................................................... 129
TMR1L Register ....................................................... 129
Use as a Real-Time Clock ....................................... 132
Timer2 .............................................................................. 135
Associated Registers ............................................... 136
Interrupt .................................................................... 136
Operation ................................................................. 135
Output ...................................................................... 136
PR2 Register .................................................... 146, 151
TMR2 to PR2 Match Interrupt .......................... 146, 151
Timer3 .............................................................................. 137
16-Bit Read/Write Mode ........................................... 139
Associated Registers ............................................... 139
Operation ................................................................. 138
Oscillator .......................................................... 137, 139
Overflow Interrupt ............................................ 137, 139
Special Event Trigger (CCP) .................................... 139
TMR3H Register ...................................................... 137
TMR3L Register ....................................................... 137
Timing Diagrams
A/D Conversion ........................................................ 397
Acknowledge Sequence .......................................... 230
Asynchronous Reception (TXCKP = 0,
TX Not Inverted) .............................................. 251
Asynchronous Transmission (TXCKP = 0,
TX Not Inverted) .............................................. 248
Asynchronous Transmission, Back to Back(TXCKP = 0, TX Not Inverted) ......................... 248
Automatic Baud Rate Calculation ............................ 246
Auto-Wake-up Bit (WUE) During
Normal Operation ............................................ 252
Auto-Wake-up Bit (WUE) During Sleep ................... 252
Baud Rate Generator with Clock Arbitration ............ 224
BRG Overflow Sequence ......................................... 246
BRG Reset Due to SDA Arbitration
During Start Condition ..................................... 233
Brown-out Reset (BOR) ........................................... 383
Bus Collision During a Repeated Start
Condition (Case 1) ........................................... 234
Bus Collision During a Repeated Start
Condition (Case 2) ........................................... 234
Bus Collision During a Start
Condition (SCL = 0) ......................................... 233
Bus Collision During a Start
Condition (SDA only) ....................................... 232
Bus Collision During a Stop
Condition (Case 1) ........................................... 235
Bus Collision During a Stop
Condition (Case 2) ........................................... 235
Bus Collision for Transmit andAcknowledge ................................................... 231
Capture/Compare/PWM(All CCP Modules) ........................................... 385
CLKO and I/O .......................................................... 382
Clock Synchronization ............................................. 217© 2007 Microchip Technology Inc.

Preliminary

Clock/Instruction Cycle .............................................. 61
EUSART Synchronous Receive(Master/Slave) ................................................. 394
EUSART Synchronous Transmission(Master/Slave) ................................................. 394
Example SPI Master Mode (CKE = 0) ..................... 386
Example SPI Master Mode (CKE = 1) ..................... 387
Example SPI Slave Mode (CKE = 0) ....................... 388
Example SPI Slave Mode (CKE = 1) ....................... 389
External Clock (All Modes Except PLL) ................... 380
Fail-Safe Clock Monitor ........................................... 301
First Start Bit Timing ................................................ 225
Full-Bridge PWM Output .......................................... 155
Half-Bridge PWM Output ......................................... 154
High/Low-Voltage Detect Characteristics ................ 377
High-Voltage Detect (VDIRMAG = 1) ...................... 282
I2C Bus Data ............................................................ 390
I2C Bus Start/Stop Bits ............................................ 390
I2C Master Mode (7 or 10-Bit Transmission) ........... 228
I2C Master Mode (7-Bit Reception) ......................... 229
I2C Slave Mode (10-Bit Reception, SEN = 0) .......... 213
I2C Slave Mode (10-Bit Reception,
SEN = 0, ADMSK 01001) ................................ 214
I2C Slave Mode (10-Bit Reception, SEN = 1) .......... 219
I2C Slave Mode (10-Bit Transmission) .................... 215
I2C Slave Mode (7-Bit Reception, SEN = 0) ............ 210
I2C Slave Mode (7-bit Reception, SEN = 0,
ADMSK = 01011) ............................................ 211
I2C Slave Mode (7-Bit Reception, SEN = 1) ............ 218
I2C Slave Mode (7-Bit Transmission) ...................... 212
I2C Slave Mode General Call Address
Sequence (7 or 10-Bit Address Mode) ............ 220
Low-Voltage Detect (VDIRMAG = 0) ....................... 281
Master SSP I2C Bus Data ....................................... 392
Master SSP I2C Bus Start/Stop Bits ........................ 392
PWM Auto-Shutdown (PRSEN = 0,
Auto-Restart Disabled) .................................... 160
PWM Auto-Shutdown (PRSEN = 1,
Auto-Restart Enabled) ..................................... 160
PWM Direction Change ........................................... 157
PWM Direction Change at Near
100% Duty Cycle ............................................. 157
PWM Output ............................................................ 146
Repeated Start Condition ........................................ 226
Reset, Watchdog Timer (WDT), Oscillator
Start-up Timer (OST) and Power-up
Timer (PWRT) ................................................. 383
Send Break Character Sequence ............................ 253
Slave Synchronization ............................................. 199
Slow Rise Time (MCLR Tied to VDD,
VDD Rise > TPWRT) ............................................ 49
SPI Mode (Master Mode) ........................................ 198
SPI Mode (Slave Mode with CKE = 0) ..................... 200
SPI Mode (Slave Mode with CKE = 1) ..................... 200
SPP Write Address and Data for USB(4 Wait States) ................................................. 189
SPP Write Address and Read Data for USB(4 Wait States) ................................................. 189
SPP Write Address, Write and Read Data
(No Wait States) .............................................. 189
Stop Condition Receive or Transmit Mode .............. 230
Streaming Parallel Port (PIC18F4455/4550) ........... 396
Synchronous Reception(Master Mode, SREN) ..................................... 256

DS39632D-page 421

PIC18F2455/2550/4455/4550
Synchronous Transmission ...................................... 254
Synchronous Transmission (Through TXEN) .......... 255
Time-out Sequence on POR w/PLL Enabled(MCLR Tied to VDD) ........................................... 49
Time-out Sequence on Power-up(MCLR Not Tied to VDD), Case 1 ....................... 48
Time-out Sequence on Power-up(MCLR Not Tied to VDD), Case 2 ....................... 48
Time-out Sequence on Power-up(MCLR Tied to VDD, VDD Rise TPWRT) .............. 48
Timer0 and Timer1 External Clock .......................... 384
Transition for Entry to Idle Mode ................................ 40
Transition for Entry to SEC_RUN Mode .................... 37
Transition for Entry to Sleep Mode ............................ 39
Transition for Two-Speed Start-up(INTOSC to HSPLL) ......................................... 299
Transition for Wake from Idle to Run Mode ............... 40
Transition for Wake from Sleep (HSPLL) ................... 39
Transition From RC_RUN Mode to
PRI_RUN Mode ................................................. 38
Transition from SEC_RUN Mode to
PRI_RUN Mode (HSPLL) .................................. 37
Transition to RC_RUN Mode ..................................... 38
USB Signal ............................................................... 395
Timing Diagrams and Specifications ................................ 380
Capture/Compare/PWM Requirements(All CCP Modules) ........................................... 385
CLKO and I/O Requirements ................................... 382
EUSART Synchronous Receive
Requirements ................................................... 394
EUSART Synchronous Transmission
Requirements ................................................... 394
Example SPI Mode Requirements(Master Mode, CKE = 0) .................................. 386
Example SPI Mode Requirements(Master Mode, CKE = 1) .................................. 387
Example SPI Mode Requirements(Slave Mode, CKE = 0) .................................... 388
Example SPI Mode Requirements(Slave Mode, CKE = 1) .................................... 389
External Clock Requirements .................................. 380
I2C Bus Data Requirements (Slave Mode) .............. 391
I2C Bus Start/Stop Bits Requirements ..................... 390
Master SSP I2C Bus Data Requirements ................ 393
Master SSP I2C Bus Start/Stop Bits
Requirements ................................................... 392
PLL Clock ................................................................. 381
Reset, Watchdog Timer, Oscillator Start-up
Timer, Power-up Timer and Brown-out
Reset Requirements ........................................ 383
Streaming Parallel Port Requirements(PIC18F4455/4550) ......................................... 396
Timer0 and Timer1 External Clock
Requirements ................................................... 384
USB Full-Speed Requirements ................................ 395
USB Low-Speed Requirements ............................... 395
Top-of-Stack Access .......................................................... 58
TQFP Packages and Special Features ............................ 305
TSTFSZ ............................................................................ 347
Two-Speed Start-up ................................................. 285, 299
Two-Word Instructions
Example Cases .......................................................... 62
TXSTA Register
BRGH Bit ................................................................. 241

DS39632D-page 422

U
Universal Serial Bus .......................................................... 63
Address Register (UADDR) ..................................... 170
and Streaming Parallel Port ..................................... 183
Associated Registers ............................................... 184
Buffer Descriptor Table ............................................ 171
Buffer Descriptors .................................................... 171
Address Validation ........................................... 174
Assignment in Different
Buffering Modes ...................................... 176
BDnSTAT Register (CPU Mode) ..................... 172
BDnSTAT Register (SIE Mode) ....................... 174
Byte Count ....................................................... 174
Example ........................................................... 171
Memory Map .................................................... 175
Ownership ....................................................... 171
Ping-Pong Buffering ........................................ 175
Register Summary ........................................... 176
Status and Configuration ................................. 171
Class Specifications and Drivers ............................. 186
Descriptors ............................................................... 186
Endpoint Control ...................................................... 169
Enumeration ............................................................ 186
External Pull-up Resistors ....................................... 167
External Transceiver ................................................ 165
Eye Pattern Test Enable .......................................... 167
Firmware and Drivers .............................................. 184
Frame Number Registers ........................................ 170
Frames .................................................................... 185
Internal Pull-up Resistors ......................................... 167
Internal Transceiver ................................................. 165
Internal Voltage Regulator ....................................... 167
Interrupts ................................................................. 177
and USB Transactions ..................................... 177
Layered Framework ................................................. 185
Oscillator Requirements .......................................... 184
Output Enable Monitor ............................................. 167
Overview .......................................................... 163, 185
Ping-Pong Buffer Configuration ............................... 167
Power ...................................................................... 185
Power Modes ........................................................... 183
Bus Power Only ............................................... 183
Dual Power with Self-Power
Dominance .............................................. 183
Self-Power Only ............................................... 183
RAM ......................................................................... 170
Memory Map .................................................... 170
Speed ...................................................................... 186
Status and Control ................................................... 164
Transfer Types ......................................................... 185
UFRMH:UFRML Registers ...................................... 170
USB. See Universal Serial Bus.

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
V
Voltage Reference Specifications .................................... 375

W
Watchdog Timer (WDT) ........................................... 285, 297
Associated Registers ............................................... 298
Control Register ....................................................... 297
During Oscillator Failure .......................................... 300
Programming Considerations .................................. 297
WCOL ...................................................... 225, 226, 227, 230
WCOL Status Flag ................................... 225, 226, 227, 230
WWW Address ................................................................. 423
WWW, On-Line Support ...................................................... 5X
XORLW ............................................................................ 347
XORWF ............................................................................ 348© 2007 Microchip Technology Inc.

Preliminary

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PIC18F2455/2550/4455/4550
NOTES:DS39632D-page 424

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
THE MICROCHIP WEB SITE

CUSTOMER SUPPORTMicrochip provides online support via our WWW site atwww.microchip.com. This web site is used as a means
to make files and information easily available tocustomers. Accessible by using your favorite Internet
browser, the web site contains the following
information:

Users of Microchip products can receive assistancethrough several channels:• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing• Business of Microchip – Product selector andordering guides, latest Microchip press releases,
listing of seminars and events, listings ofMicrochip sales offices, distributors and factory
representatives• Distributor or Representative• Local Sales Office• Field Application Engineer (FAE)• Technical Support• Development Systems Information Line
Customers
shouldcontact
their
distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the web site
at: http://support.microchip.com

CUSTOMER CHANGE NOTIFICATIONSERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there arechanges, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site atwww.microchip.com, click on Customer Change
Notification and follow the registration instructions.

© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 425

PIC18F2455/2550/4455/4550
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
To:

Technical Publications Manager

RE:

Reader Response

Total Pages Sent ________

From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________

FAX: (______) _________ - _________

Application (optional):
Would you like a reply?

YN

Device: PIC18F2455/2550/4455/4550

Literature Number: DS39632D

Questions:
1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

DS39632D-page 426

Preliminary© 2007 Microchip Technology Inc.

PIC18F2455/2550/4455/4550
PIC18F2455/2550/4455/4550 PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.

X

/XX

XXX

DeviceTemperature
Range

Package

Pattern

Examples:a)b)Device

PIC18F2455/2550(1), PIC18F4455/4550(1),PIC18F2455/2550T(2), PIC18F4455/4550T(2);VDD range 4.2V to 5.5V
PIC18LF2455/2550(1), PIC18LF4455/4550(1),PIC18LF2455/2550T(2), PIC18LF4455/4550T(2);VDD range 2.0V to 5.5V

Temperature Range

I
E

=
=

-40°C to +85°C (Industrial)-40°C to +125°C (Extended)

Package

PT
SO
SP
P
ML

=
=
=
=
=

TQFP (Thin Quad Flatpack)
SOIC
Skinny Plastic DIP
PDIP
QFN

Patternc)

PIC18LF4550-I/P 301 = Industrial temp., PDIP
package, Extended VDD limits, QTP pattern#301.
PIC18LF2455-I/SO = Industrial temp., SOIC
package, Extended VDD limits.
PIC18F4455-I/P = Industrial temp., PDIP
package, normal VDD limits.

Note 1:
2:

F = Standard Voltage Range
LF = Wide Voltage Range
T = in tape and reel TQFP
packages only.

QTP, SQTP, Code or Special Requirements(blank otherwise)© 2007 Microchip Technology Inc.

Preliminary

DS39632D-page 427

WORLDWIDE SALES AND SERVICEAMERICAS

ASIA/PACIFIC

ASIA/PACIFICEUROPE

Corporate Office2355 West Chandler Blvd.
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Technical Support:
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Web Address:www.microchip.com

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Taiwan - Kaohsiung
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Tel: 86-757-2839-5507
Fax: 86-757-2839-5571

Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102

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Italy - Milan
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Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
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Tel: 44-118-921-5869
Fax: 44-118-921-5820

China - Xian
Tel: 86-29-8833-7250
Fax: 86-29-8833-7256

12/08/06

DS39632D-page 428

Preliminary© 2007 Microchip Technology Inc.