LTC6820
isoSPI Isolated
Communications Interface
FEATURESDESCRIPTION

AEC-Q100 Qualified for Automotive Applications
nn 1Mbps Isolated SPI Data Communications
nn Simple Galvanic Isolation Using Standard
Transformers
nn Bidirectional Interface Over a Single Twisted Pairnn Supports Cable Lengths Up to 100 Meters
nn Very Low EMI Susceptibility and Emissions
nn Configurable for High Noise Immunity or Low Powernn Engineered for ISO26262 Compliant Systems
nn Requires No Software Changes in Most SPI Systems
nn Ultralow, 2µA Idle Current
nn Automatic Wake-Up Detection
nn Operating Temperature Range: –40°C to 125°C
nn 2.7V to 5.5V Power Supply
nn Interfaces to All Logic from 1.7V to 5.5V
nn Available in 16-Lead QFN and MSOP Packages

The LTC®6820 provides bidirectional SPI communications
between two isolated devices through a single twistedpair connection. Each LTC6820 encodes logic states into
signals that are transmitted across an isolation barrier toanother LTC6820. The receiving LTC6820 decodes thetransmission and drives the slave bus to the appropriate logic states. The isolation barrier can be bridged bya simple pulse transformer to achieve hundreds of voltsof isolation.

nn

APPLICATIONSThe LTC6820 drives differential signals using matchedsource and sink currents, eliminating the requirement
for a transformer center tap and reducing EMI. Precisionwindow comparators in the receiver detect the differential
signals. The drive currents and the comparator thresholds
are set by a simple external resistor divider, allowing thesystem to be optimized for required cable lengths anddesired signal-to-noise performance.
All registered trademarks and trademarks are the property of their respective owners. Protectedby U.S. patents, including 8908779.

Industrial Networking
Battery Monitoring Systems
nn Remote Sensors
nn
nn

TYPICAL APPLICATION
Microcontroller to SPI Slave Isolated Interface
1.2
LTC6820

SDO
SDI
SCK
CS

MSTR
MOSI IP
MISO
SCK
IM
CS

120Ω

100 METERSTWISTED PAIR

0.8
0.6
0.4
0.2

LTC6820
MSTR

SDI
SDO
SCK
CS

IP
MOSI
MISO
IM
SCK
CS

CAT-5 ASSUMED

1.0
DATA RATE (Mbps)

MASTERµC

REMOTESLAVE IC

Data Rate vs Cable Length

0
120Ω

1

10
CABLE LENGTH (METERS)

100
6820 TA01b

6820 TA01a

Rev C

Document Feedback

For more information www.analog.com

1

LTC6820
ABSOLUTE MAXIMUM RATINGS (Notes 1, 2, 3)
Input Supply Voltages (VDD and VDDS) to GND............6V
Pin Voltages
SCK, CS, EN................–0.3V to VDDS + 0.3V (6V Max)IBIAS, SLOW, IP, IM......–0.3V to VDD + 0.3V (6V Max)All Other Pin Voltages............................... –0.3V to 6V
Maximum Source/Sink Current
IP, IM..................................................................30mA
MOSI, MISO, SCK, CS.........................................20mA

Operating Temperature Range
LTC6820I..............................................–40°C to 85°C
LTC6820H........................................... –40°C to 125°C
Specified Temperature Range
LTC6820I..............................................–40°C to 85°C
LTC6820H........................................... –40°C to 125°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
MSOP................................................................ 300°C

PIN CONFIGURATION
GND

ICMP

IBIAS

EN

TOP VIEWTOP VIEW

16 15 14 13
MOSI 1EN 1
MOSI 2MISO 3SCK 4
CS 5
VDDS 6POL 7
PHA 8

12 SLOWMISO 211 MSTR

17

SCK 3

10 IP

CS 4
6

7

8

VDDS

POL

PHA

VDD

9
5

IM

16
15
14
13
12
11
10
9

IBIAS
ICMP
GND
SLOW
MSTR
IP
IM
VDD

MS PACKAGE
16-LEAD PLASTIC MSOPUD PACKAGE
16-LEAD (3mm × 3mm) PLASTIC QFNTJMAX = 150°C, θJA = 120°C/W

TJMAX = 150°C, θJA = 58.7°C/W
EXPOSED PAD (PIN 17) PCB CONNECTION TO GND IS OPTIONAL

ORDER INFORMATIONPARTMARKING* PACKAGE DESCRIPTIONMSLRATING

SPECIFIEDTEMPERATURE RANGE

TUBE (121PC)

TAPE AND REEL (2500PC)

LTC6820IUD#PBF

LTC6820IUD#TRPBF

LGFM

16-Lead (3mm × 3mm) Plastic QFN

1–40°C to 85°C

LTC6820HUD#PBF

LTC6820HUD#TRPBF

LGFM

16-Lead (3mm × 3mm) Plastic QFN

1–40°C to 125°C

MSL
RATING

SPECIFIEDTEMPERATURE RANGEAUTOMOTIVE PRODUCTS**PARTMARKING* PACKAGE DESCRIPTIONTUBE (37PC)

TAPE AND REEL (2500PC)

LTC6820IMS#PBF

LTC6820IMS#TRPBF

6820

16-Lead Plastic MSOP

1

–40°C to 85°C

LTC6820IMS#3ZZPBF

LTC6820IMS#3ZZTRPBF

6820

16-Lead Plastic MSOP

1

–40°C to 85°C

LTC6820HMS#PBF

LTC6820HMS#TRPBF

6820

16-Lead Plastic MSOP

1

–40°C to 125°C

LTC6820HMS#3ZZPBF

LTC6820HMS#3ZZTRPBF

6820

16-Lead Plastic MSOP

1

–40°C to 125°C

Contact the factory for parts specified with wider operating temperature ranges.*The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
**Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Thesemodels are designated with a #3ZZ suffix. Only the automotive grade products shown are available for use in automotive applications. Contact yourlocal Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports forthese models.

2

Rev C

For more information www.analog.com

LTC6820
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full specified

temperature range, otherwise specifications are at TA = 25°C. VDD = 2.7V to 5.5V, VDDS = 1.7V to 5.5V, RBIAS = 2k to 20k unlessotherwise specified. All voltages are with respect to GND.
SYMBOL PARAMETER
Power Supply
VDD
Operating Supply Voltage Range
VDDS
IO Supply Voltage Range (Level Shifting)
IDD
Supply Current, READY/ACTIVE States(Note 4)

Supply Current, IDLE State

CONDITIONS

Voltage on IBIAS Pin

IB
AIBIsolated Interface Bias Current (Note 6)
Isolated Interface Current Gain

READY/ACTIVE StateIDLE StateRBIAS = 2k to 20k
VA ≤ 1.6V

VA

Transmitter Pulse Amplitude

VA = |VIP – VIM|

VOH

Digital Voltage Output High (CS and SCK)VOL

Digital Voltage Output Low(MOSI, MISO, CS, SCK)

1.3

l

Biasing
VBIAS

Digital Voltage Input Low, EN Pinll

IO Supply Current (Note 5)

VIL(EN)

l

2.7
1.7
4

l

Affects CS, SCK, MOSI, MISO and EN Pins
RBIAS = 2kΩ (IB = 1mA)
1/tCLK = 0MHz
1/tCLK = 1MHzRBIAS = 20kΩ (IB = 0.1mA)
1/tCLK = 0MHz
1/tCLK = 1MHzMSTR = 0V
MSTR = VDD
SPI Inputs and EN Pin at 0V or VDDS,SPI Outputs Unloaded

IDDS

VICMP
Threshold-Setting Voltage on ICMP Pin
ILEAK(ICMP) Leakage Current on ICMP Pin
ILEAK(IP/IM) Leakage Current on IP and IM Pins
ATCMP
Receiver Comparator Threshold Voltage
Gain
VCM
Receiver Common Mode Bias
RIN
Receiver Input ResistanceIdle/Wake-Up (See Figure 13, 14, 15)
VWAKE
Differential Wake-Up Voltage(See Figure 13)
tDWELL
Dwell Time at VWAKE
tREADY
Start-Up Time After Wake DetectiontIDLE
Idle Time-Out Duration
Digital I/O
VIH(CFG) Digital Voltage Input High, Configuration
Pins (PHA, POL, MSTR, SLOW)VIL(CFG)
Digital Voltage Input Low, Configuration
Pins (PHA, POL, MSTR, SLOW)VIH(SPI)
Digital Voltage Input High, SPI Pins
(CS, SCK, MOSI, MISO)
VIL(SPI)
Digital Voltage Input Low, SPI Pins
(CS, SCK, MOSI, MISO)
VIH(EN)
Digital Voltage Input High, EN Pin

MIN

l
l

4.8
7
2
2.4
2
1

l

1.9

l

IB = 1mA
IB = 0.1mA
VDD < 3.3V
VDD ≥ 3.3V

TYP

l
l

18
18

2.0
0
VBIAS/RBIAS
20
20

l
l

UNITS

5.5
5.5
5.8

V
V
mA
mA
mA
mA
µA
µA
µA

2.9
6
3
1

2.1

V
V
mA
22
mA/mA
24
mA/mA
VDD – 1.7V
V
1.6
V
1.5
V
±1
µA
±2
µA
0.6
V/V

VTCMP = ATCMP • VICMP
VICMP = 0V to VDD
IDLE State, VIP = VIM = 0V to VDD
VCM = VDD/2 to VDD – 0.2V,
VICMP = 0.2V to 1.5V
IP/IM Not Driving
Single-Ended to IP or IM

l

0.4

l

(VDD – VICMP/3 – 167mV)
26
35
42

V
kΩ

tDWELL = 240ns

l

240

mV

VWAKE = 240mV

l

240

ns
µs
ms

l

0.2

MAX

l
l

0.5

l
l

4

VDD = 2.7V to 5.5V (POL, PHA, MSTR, SLOW)l

0.7 • VDD

VDD = 2.7V to 5.5V (POL, PHA, MSTR, SLOW)lVDDS = 2.7V to 5.5V
VDDS = 1.7V to 2.7V
VDDS = 2.7V to 5.5V
VDDS = 1.7V to 2.7V
VDDS = 2.7V to 5.5V
VDDS = 1.7V to 2.7V
VDDS = 2.7V to 5.5V
VDDS = 1.7V to 2.7V
VDDS = 3.3V, Sourcing 2mA
VDDS = 1.7V, Sourcing 1mA
VDDS = 3.3V, Sinking 3.3mA
VDDS = 1.7V, Sinking 1mA

l 0.7 • VDDS
l 0.8 • VDDS
l
l

5.7

8
7.5

V
0.3 • VDD

0.3 • VDDS
0.2 • VDDSl2l 0.85 • VDDSll

0.8
0.25 • VDDSl VDDS – 0.2
l VDDS – 0.25
l
l

0.2
0.2

V
V
V
V
V
V
V
V
V
V
V
V
V
Rev C

For more information www.analog.com

3

LTC6820
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full specified

junction temperature range, otherwise specifications are at TA = 25°C. VDD = 2.7V to 5.5V, VDDS = 1.7V to 5.5V, RBIAS = 2k to 20k
unless otherwise specified. All voltages are with respect to GND.
SYMBOL PARAMETERILEAK(DIG) Digital Pin Input Leakage Current
CI/O
Input/Output Pin Capacitance
Isolated Pulse Timing (See Figure 2)
t1/2PW(CS) Chip-Select Half-Pulse WidthtINV(CS)
Chip-Select Pulse Inversion DelaytDEL(CS)
Chip-Select Response Delayt½PW(D)
Data Half-Pulse WidthtINV(D)
Data Pulse Inversion DelaytDEL(D)
Data Response Delay
isoSPI™ Timing—Master (See Figure 3, 4)
tCLK
SCK Latching Edge to SCK Latching Edge
t1
t2
t3
t4
t5

MOSI Setup Time Before SCK Latching Edge
MOSI Hold Time After SCK Latching Edge
SCK Low
SCK High
CS Rising Edge to CS Falling Edget6

SCK Latching Edge to CS Rising Edge
(Note 7)t7

CS Falling Edge to SCK Latch Edge
(Note 7)t8
SCK Non-Latch Edge to MISO Validt9
SCK Latching Edge to Short ±1 Transmit
t10
CS Transition to Long ±1 Transmit
t11
CS Rising Edge to MISO Rising
isoSPI Timing—Slave (See Figure 3, 4)
t12
isoSPI Data Recognized to SCK
Latching Edge
t13
SCK Pulse Width

CONDITIONSPHA, POL, MSTR, SLOW = 0V to VDD
CS, SCK, MOSI, MISO, EN = 0V to VDDS
(Note 9)

l

TYP

120

150

40

140
50

l
l
l
l

(Note 8)(Note 7)75lSLOW = 0
SLOW = 1(Note 8)lllltCLK = t3 + t4 ≥ 0.5µs
tCLK = t3 + t4 ≥ 0.5µs
1MHz isoSPI Slave, tCLK > 1 µs
2MHz isoSPI Slave, 0.5µs < tCLK < 1µs
1MHz isoSPI Slave, tCLK > 1µs
2MHz isoSPI Slave, 0.5µs < tCLK < 1µs
ADI Stack Monitor isoSPI Slave
Other isoSPI Slave Devices Including 6820
(Note 8)

l
l
l
l
l
l
l
l
l

l

(Note 8)(Note 8)SCK Non-Latch Edge to isoSPI Data Transmit (Note 8)t15

CS Falling Edge to SCK Non-Latch Edget16

CS Falling Edge to isoSPI Data Transmit

t17

CS Rising Edge to SCK Latching Edge

PHA = 1t18
tRTN

CS Rising Edge to MOSI Rising Edge
Data Return Delay(Note 8)

PHA = 1l

SLOW = 0
SLOW = 1
SLOW = 0
SLOW = 1
SLOW = 0
SLOW = 1
SLOW = 0
SLOW = 1
SLOW = 0
SLOW = 1
SLOW = 0
SLOW = 1

l
l
l
l
l
l
l
l
l
l
l
l

110
0.9
90
0.9
115
0.9
90
0.9
200
1.8
90
0.9

145
1.1
115
1.1
145
1.1
120
1.1
265
2.2
120
1.1

l

SLOW = 0
SLOW = 1

l
l

MAX
±1

UNITS
µA

10

pF

180
200
190
60
70
120

ns
ns
ns
ns
ns
ns

55
50
55
55

µs
µs
ns
ns
ns
ns
µs
µs
µs
µs
µs
µs
ns
ns
ns
ns

185
1.4
150
1.4
190
1.4
160
1.4
345
2.8
160
1.4
35
625
4

ns
µs
ns
µs
ns
µs
ns
µs
ns
µs
ns
µs
ns
ns
µs

0.5
5
25
25
50
50
0.6
2.0
1
0.5
0.5
1

l

t14

4

MIN
l

485
3.3

Rev C

For more information www.analog.com

LTC6820
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into pins are positive, and all voltages are referenced
to GND unless otherwise specified.
Note 3: The LTC6820I is guaranteed to meet specified performancefrom –40°C to 85°C. The LTC6820H is guaranteed to meet specified
performance from –40°C to 125°C.
Note 4: Active supply current (IDD) is dependent on the amount of timethat the output drivers are active on IP and IM. During those times IDD will
increase by the 20 • IB drive current. For the maximum data rate 1MHz,
the drivers are active approximately 10% of the time if MSTR = 1, and 5%of the time if MSTR = 0. See Applications Information section for moredetailed information.
Note 5: The IO supply pin, VDDS, provides power for the SPI inputs andoutputs, including the EN pin. If the inputs are near 0V or VDDS (to avoid
static current in input buffers) and the outputs are not sourcing current,
then IDDS includes only leakage current.

Note 6: The LTC6820 is guaranteed to meet specifications with RBIAS
resistor values ranging from 2k to 20k, with 1% or better tolerance. Those
resistor values correspond to a typical IB that can range from 0.1mA(for 20k) to 1mA (for 2k).
Note 7: These timing specifications are dependent on the delay throughthe cable, and include allowances for 50ns of delay each direction. 50ns
corresponds to 10m of CAT-5 cable (which has a velocity of propagation of
66% the speed of light). Use of longer cables would require derating these
specs by the amount of additional delay.
Note 8: These specifications do not include rise or fall time. While falltime (typically 5ns due to the internal pull-down transistor) is not aconcern, rising-edge transition time tRISE is dependent on the pull-up
resistance and load capacitance. In particular, t12 and t14 require tRISE< 110ns (if SLOW = 0) for the slave’s setup and hold times. Therefore,
the recommended time constant is 50ns or less. For example, if thetotal capacitance on the data pin is 25pF (including self capacitance
CI/O of 10pF), the required pull-up resistor value is RPU ≤ 2kΩ. If theserequirements can’t be met, use SLOW = 1.
Note 9: Guaranteed by design. Not tested in production.

Rev C

For more information www.analog.com

5

LTC6820
TYPICAL PERFORMANCE CHARACTERISTICS VDD = VDDS, unless otherwise noted.

5.3

7
VDD = 5V, IB = 1mA

6

SUPPLY CURRENT (mA)

SUPPLY CURRENT (mA)

54

VDD = 5V, IB = 0.1mA

2
MSTR = 1
0

200

400
600
FREQUENCY (kHz)5.1
VDD = 3V

5.0

4.8
–50

1000

800

VDD = 5V

4.9

VDD = 3V, IB = 0.1mA

1

4.0

IB = 1mA

5.2

VDD = 3V, IB = 1mA

3

Input Voltage Threshold(Except EN Pin)
vs Supply Voltage (VDD or VDDS)

Supply Current (READY)vs Temperature
INPUT VOLTAGE THRESHOLD (V)Supply Current (READY/ACTIVE)
vs Clock Frequency

–25

50
0
75
25
TEMPERATURE (°C)

100

2.5

2.5
SUPPLY CURRENT (µA)

3.0

SUPPLY CURRENT (µA)

3.0

MASTER (MSTR = 1)

1.0

LOW

2.0
1.5
1.0

VIL

0.5

Supply Current (IDLE)vs Temperature

1.5

HIGH

1.5

2.0

2.5 3.0 3.5 4.0 4.5
SUPPLY VOLTAGE (V)

5.0

0.5

Output Resistance vs Supply
Voltage (VOH/VOL)100

VDD = 5V

2.0
SLAVE (MSTR = 0)

1.5
1.0

MASTER (MSTR = 1)

0.5

5.5

6820 G03

OUTPUT RESISTANCE (Ω)

Supply Current (IDLE)vs Supply Voltage

SLAVE (MSTR = 0)

VIH

2.5

0

125

ONLY
SPI PINS

3.0

6820 G02

6820 G01

2.0

3.5

80
OUTPUT
SOURCING 2mA CURRENT
60
40

20
OUTPUT SINKING 3.3mA CURRENT

0

2.5

3.0

3.5
4.0
4.5
SUPPLY VOLTAGE (V)5.00–50 –25

5.5

50
25
75
0
TEMPERATURE (°C)

1006820 G04

2.00

1.98
IB = 1mA
IB = 0.1mA
–25

50
25
0
75
TEMPERATURE (°C)

100

125

IBIAS Voltage vs Supply Voltage

VDD = 3V

2.005

2.000

1.995

1.990

0

0.2

0.6
0.8
0.4
IBIAS CURRENT (mA)

6820 G07

6

5.5

2.010

IBIAS PIN VOLTAGE (V)IBIAS PIN VOLTAGE (V)IBIAS PIN VOLTAGE (V)

2.02

3.5
2.5
4.5
SUPPLY VOLTAGE (V)6820 G19

IBIAS Voltage Load Regulation
2.010

VDD = 3V
3 PARTS

1.96
–50

125

6820 G05

IBIAS Voltage vs Temperature
2.04

0
1.5

1.0
6820 G08

IB = 0.1mA

2.005

IB = 1mA
2.000

1.995

1.990

2.5

3

3.5
4
4.5
SUPPLY VOLTAGE (V)55.56820 G09

Rev C

For more information www.analog.com

LTC6820
TYPICAL PERFORMANCE CHARACTERISTICS VDD = VDDS, unless otherwise noted.
Driver Current Gainvs IBIAS Current (IB)Driver Current Gain vs Amplitude
21.5

VDD = 5V
IB = 0.1mA

21
20
VDD = 3V
IB = 0.1mA

19

VDD = 3V
IB = 1mA

18
17

21.0

VDD = 5V

20.5
VDD = 3V

20.0
19.5
19.0

18.0

2.0

0.5
1.0
1.5
PULSE AMPLITUDE VA (V)

5

0.2

0

0.4

0.8
0.6
IBIAS CURRENT (mA)

VA = 1V

DRIVER COMMON MODE (V)

CURRENT GAIN (mA/mA)

21.5

20.5

IB = 0.1mA, VDD = 3V

20.0

IB = 1mA, VDD = 3V

19.5
19.0

75
50
25
TEMPERATURE (°C)

0100

IB = 0.1mA, VDD = 5V

4.53
IB = 0.1mA, VDD = 3V2
IB = 1mA, VDD = 3V
1

–25

50
0
75
25
TEMPERATURE (°C)

100

IB = 0.1mA, VDD = 5V
IB = 1mA, VDD = 5V

3.5
3.0

IB = 0.1mA, VDD = 3V

2.5
2.0

VDD = 3V
VDD = 5V
0

0.2

0.4

0.6 0.8 1.0 1.2
ICMP VOLTAGE (V)

1.4 1.6

IB = 1mA, VDD = 3V
0.5
1.5
1.0
PULSE AMPLITUDE (V)06820 G15

0.56

0.54
0.52 VICMP = 1V
VDD = 3V

VICMP = 1V
VDD = 5V

0.50
0.48

VICMP = 0.2V
VDD = 3V

VICMP = 0.2V
VDD = 5V

0.46
0.44

1.5

2.0

2.5 3.0 3.5 4.0 4.5 5.0
COMMON MODE VOLTAGE (V)5.5

6820 G17

6820 G16

2.0

Comparator Threshold Gainvs Temperature
COMPARATOR THRESHLD GAIN (V/V)

COMPARATOR THRESHLD GAIN (V/V)

0.48
0.46

1.0

125

0.56

3 PARTS

5.5

4.0

Comparator Threshold Gainvs Common Mode

0.50

5

6820 G14

6820 G13

0.52

4.5

5.0

IB = 1mA, VDD = 5V

0
–50

125

0.54

4

Driver Common Mode Voltage
vs Pulse Amplitude

4

Comparator Threshold Gain
vs ICMP Voltage
0.56

3.5

3

6820 G12

1.5

18.0–50 –25

COMPARATOR THRESHOLD GAIN (V/V)

19.0

SUPPLY VOLTAGE (V)

18.5

0.44

19.5

18.0
2.5

1.0

DRIVER COMMON MODE (V)VA = 1V

IB = 1mA, VDD = 5V

IB = 1mA

20.0

Driver Common Mode Voltage
vs Temperature

IB = 0.1mA, VDD = 5V

IB = 0.1mA

20.56820 G11

Driver Current Gainvs Temperature

21.0

21.0

18.5

6820 G10

22.0

VA = 1V

21.5

18.5

VA(MAX) = 1.3V
FOR VDD = 3V0

22.0

VA = 1V

CURRENT GAIN (mA/mA)

VDD = 5V
IB = 1mA

22

22.0

VA(MAX) = 1.6V
FOR VDD > 3.3V
CURRENT GAIN (mA/mA)

CURRENT GAIN AIB (mA/mA)

23

Driver Current Gainvs Supply Voltage

0.54

VDD = 3V
3 PARTS

0.52
0.50
0.48
0.46
0.44
–50

VICMP = 1V
VICMP = 0.2V
–25

50
25
0
75
TEMPERATURE (°C)

100

125

6820 G18

Rev C

For more information www.analog.com

7

LTC6820
TYPICAL PERFORMANCE CHARACTERISTICS VDD = VDDS, unless otherwise noted.

WAKE-UP PULSE AMPLITUDE, VWAKE (mV)

Wake-Up Pulse Amplitude
vs Dwell Time
300

Start-Up TimeVDD = 3VCS
5V/DIVGUARANTEED
WAKE-UP REGION

250

3.6µs

IBIAS
2V/DIV

200
150

IP-IM
1V/DIV
100

50

0

300
150
450
WAKE-UP DWELL TIME, tDWELL (ns)

VDDS = 5V
MSTR = 1
RBIAS = 2k6006820 G06

1µs/DIV

6820 G20

SPI Signal and isoSPI Pulses, MSTR = 1

SPI Signal and isoSPI Pulses, MSTR = 0

CS
5V/DIV

IP-IM
2V/DIVSCK
5V/DIVCS
5V/DIV

MOSI
5V/DIVSCK
5V/DIVMIS0
5V/DIV

MOSI
5V/DIV

IP-IM
2V/DIVMIS0
5V/DIVVDD = 5V
VDDS = 3.3V
PHA = 1
POL = 18

1.2µs/DIV

6820 G21

VDD = 5V
VDDS = 5V
PHA = 0
POL = 01.2µs/DIV

6820 G22

Rev C

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LTC6820
PIN FUNCTIONS (QFN/MSOP)MOSI (Pin 1/Pin 2): SPI Master Out/Slave In Data. If connected on the master side of a SPI interface (MSTR pinhigh), this pin receives the data signal output from themaster SPI controller. If connected on the slave side of theinterface (MSTR pin low), this pin drives the data signal
input to the slave SPI device. The output is open drain, so
an external pull-up resistor to VDDS is required.
MISO (Pin 2/Pin 3): SPI Master In/Slave Out Data. If connected on the master side of a SPI interface (MSTR pinhigh), this pin drives the data signal input to the master
SPI controller. If connected on the slave side of the interface (MSTR pin low), this pin receives the data signal output from the slave SPI device. The output is open drain,
so an external pull-up resistor to VDDS is required.
SCK (Pin 3/Pin 4): SPI Clock Input/Output. If connectedon the master side of the interface (MSTR pin high), thispin receives the clock signal from the master SPI controller. This input should not be pulled above VDDS. If connected on the slave side of the interface (MSTR pin low),
this pin outputs the clock signal to the slave device. The
output driver is push-pull; no external pull-up resistor
is needed.
CS (Pin 4/Pin 5): SPI Chip Select Input/Output. If connected on the master side of the interface (MSTR pinhigh), this pin receives the chip select signal from themaster SPI controller. This input should not be pulled
above VDDS. If connected on the slave side of the interface(MSTR pin low), this pin outputs the chip select signal
to the slave device. The output driver is push-pull; noexternal pull-up resistor is needed.
VDDS (Pin 5/Pin 6): SPI Input/Output Power Supply Input.
The output drivers for the SCK and CS pins use the VDDS
input as their positive power supply. The input thresholdvoltages of SCK, CS, MOSI, MISO and EN are determined
by VDDS. May be tied to VDD or to a supply above or below
VDD to level shift the SPI I/O. If separate from VDD, connect a bypass capacitor of at least 0.01μF directly between
VDDS and GND.
POL (Pin 6/Pin 7): SPI Clock Polarity Input. Tie to VDD or
GND. See Operation section for details.
PHA (Pin 7/Pin 8): SPI Clock Phase Input. Tie to VDD or
GND. See Operation section for details.

VDD (Pin 8/Pin 9): Device Power Supply Input. Connect
a bypass capacitor of at least 0.01μF directly between
VDD and GND.
IM (Pin 9/Pin 10): Isolated Interface Minus Input/Output.
IP (Pin 10/Pin 11): Isolated Interface Plus Input/Output.
MSTR (Pin 11/Pin 12): Serial Interface Master/Slave
Selector Input. Tie this pin to VDD if the device is on themaster side of the isolated interface. Tie this pin to GND
if the device is on the slave side of the isolated interface.
SLOW (Pin 12/Pin 13): Slow Interface Selection Input. For
clock frequencies at or below 200kHz, or if slave devices
cannot meet timing requirements, this pin should be tied
to VDD. For clock frequencies above 200kHz, this pinshould be tied to GND.
GND (Pin 13/Pin 14): Device Ground.
ICMP (Pin 14/Pin 15): Isolated Interface Comparator
Voltage Threshold Set. Tie this pin to the resistor divider
between IBIAS and GND to set the voltage threshold of theinterface receiver comparators. The comparator thresholds are set to 1/2 the voltage on the ICMP pin.
IBIAS (Pin 15/Pin 16): Isolated Interface Current Bias.
Tie IBIAS to GND through a resistor divider to set theinterface output current level. When the device is enabled,
this pin is approximately 2V. When transmitting pulses,
the sink current on each of the IP and IM pins is set to
20 times the current sourced from pin IBIAS to GND.
Limit the capacitance on the IBIAS pin to less than 50pF
to maintain the stability of the feedback circuit regulating
the IBIAS voltage.
EN (Pin 16/Pin 1): Device Enable Input. If high, thispin forces the LTC6820 to stay enabled, overriding theinternal IDLE mode function. If low, the LTC6820 will go
into IDLE mode after the CS pin has been high for 5.7ms(when MSTR pin is high) or after no signal on the IP/IM
pins for 5.7ms (when MSTR pin is low). The LTC6820 will
wake-up less than 8µs after CS falls (MSTR high) or after
a signal is detected on IP/IM (MSTR low).
Exposed Pad (Pin 17, QFN Package Only): Exposed pad
may be left open or connected to device GND.
Rev C

For more information www.analog.com

9

LTC6820

SLOW
POL
PHA

VDDS

VDDS
EN

RPU
(TO MOSI IF MSTR = 0)

MOSI(TO MISO IF MSTR = 1)

MISO
SCK
CS

IB

IBIAS

RB1

ICMP
LOGIC

MSTR

IDLE TIMEOUT 2V
WAKE DETECTREADYRBIAS = RB1 + RB2

VDD
VICMP
+ 167mV
3
OPEN
WHEN
IDLE

RB2

+
–
35k
35k

PULSE QUALIFICATION

0.1µF

EN
CS

Rx = +1+
THRESHOLD

Rx = –1

Tx = –1

0.5x–

Tx = +1
TIMING

VDD

VDDS-POWERED SPI PIN TRANSLATION

VDD

VDD-POWERED CONFIGURATION INPUTSBLOCK DIAGRAM

IP
IDRV

RM

IM
Tx • 20 • IB

GND

6820 BDOPERATION
The LTC6820 creates a bidirectional isolated serial portinterface (isoSPI) over a single twisted pair of wires,with increased safety and noise immunity over a nonisolated interface. Using transformers, the LTC6820
translates standard SPI signals (CS, SCK, MOSI andMISO) into pulses that can be sent back and forth on
twisted-pair cables.
A typical system uses two LTC6820 devices. The first ispaired with a microcontroller or other SPI master. Its IP
and IM transmitter/receiver pins are connected across an
isolation barrier to a second LTC6820 that reproduces the
SPI signals for use by one or more slave devices.
The transmitter is a current-regulated differential driver.
The voltage amplitude is determined by the drive current and the equivalent resistive load (cable characteristic
impedance and termination resistor, RM).

10

The receiver consists of a window comparator with adifferential voltage threshold, VTCMP. When VIP – VIM
is greater than +VTCMP, the comparator detects a logic+1. When VIP – VIM is less than –VTCMP, the comparator
detects a logic –1. A logic 0 (null) indicates VIP – VIM is
between the positive and negative thresholds.
The comparator outputs are sent to pulse timers (filters)that discriminate between short and long pulses.
Selecting Bias Resistors
The adjustable signal amplitude allows the system to trade
power consumption for communication robustness, andthe adjustable comparator threshold allows the system toaccount for signal losses.

Rev C

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LTC6820
OPERATIONISOLATION BARRIER
MSTR
MASTER
SDO
SDI
SCK
CS

IP

LTC6820IMMOSIMISO IBIAS
SCK
CS
ICMP

IP
RM

RM
TWISTED-PAIR CABLE
WITH CHARACTERISTIC IMPEDANCE RM

RB1

MSTR

IM
IBIAS
RB1
ICMP

RB2

SLAVE

LTC6820
MOSI
MISO
SCK
CS

SDI
SDO
SCK
CS

RB2

6820 F01

Figure 1. Typical System Using Two LTC6820 Devices

The transmitter drive current and comparator voltage
threshold are set by a resistor divider (RBIAS = RB1 + RB2)
between the IBIAS pin and GND, with the divided voltage
tied to the ICMP pin. When the LTC6820 is enabled (notIDLE), IBIAS is held at 2V, causing a current, IB, to flowout of the IBIAS pin. The IP and IM pin drive currents are
20 • IB. The comparator threshold is half the voltage on
the ICMP pin (VICMP).
As an example, if divider resistor RB1 is 1.21k and resistor
RB2 is 787Ω (so that RBIAS = 2k), then:
IB =2V
R B1 + R B2

= 1mA

The isoSPI transmitter can generate three voltage levels:+VA, 0V, and –VA. To eliminate the DC signal component
and enhance reliability, isoSPI pulses are defined as symmetric pulse pairs. A +1 pulse pair is defined as a +VA
pulse followed by a –VA pulse. A –1 pulse pair is –VA
followed by +VA.
The duration of each pulse is defined as t1/2PW. (The total
isoSPI pulse duration is 2 • t1/2PW). The LTC6820 allows
for two different t1/2PW values so that four types of pulses
can be transmitted, as listed in Table 1.
Table 1. isoSPI Pulse Types

IDRV = IIP = IIM = 20 • IB = 20mA
VICMP = 2V •isoSPI Pulse Detail

R B2
R B1 + R B2

= IB • R B2 = 788mVVTCMP = 0.5 • VICMP = 394mVIn this example, the pulse drive current IDRV will be 20mA,
and the receiver comparators will detect pulses with IP-IM
amplitudes greater than ±394mV.
If the isolation barrier uses 1:1 transformers connectedby a twisted pair and terminated with 100Ω resistors oneach end, then the transmitted differential signal amplitude (±) will be:R
V A = IDRV • M = 1V
2(This result ignores transformer and cable losses, which
will reduce the amplitude).

PULSE TYPELong +1
Long –1
Short +1
Short –1

FIRST LEVEL+VA (150ns)–VA (150ns)+VA (50ns)–VA (50ns)

SECOND LEVEL–VA (150ns)+VA (150ns)–VA (50ns)+VA (50ns)

ENDING LEVEL
0V
0V
0V
0V

Long pulses are used to transmit CS changes. Short pulses
transmit data (MOSI or MISO). An LTC6820 detects fourtypes of communication events from the SPI master: CS
falling, CS rising, SCK latching MOSI = 0, and SCK latching MOSI = 1. It converts each event into one of the four
pulse types, as shown in Table 2.
Table 2. Master Communication Events
SPI MASTER EVENTCS Rising
CS Falling
SCK Latching Edge, MOSI = 1
SCK Latching Edge, MOSI = 0

TRANSMITTED PULSELong +1
Long –1
Short +1
Short –1

Rev C

For more information www.analog.com

11

LTC6820
OPERATION
On the other side of the isolation barrier (i.e., the other endof the cable) another LTC6820 is configured to interface
with a SPI slave. It receives the transmitted pulses andreconstructs the SPI signals on its output port, as shownin Table 3. In addition, the slave device may transmit a
return data pulse to the master to set the state of MISO.
See isoSPI Interaction and Timing for additional details.
Table 3. Slave SPI Port Output
RECEIVED PULSE

SPI PORT ACTION

RETURN PULSELong +1

Drive CS High

None

Long –1

Drive CS Low

Short +1

1. Set MOSI = 1
2. Pulse SCK

Short –1

Setting Clock Phase and Polarity (PHA and POL)

(No Return Pulse
if MISO = 1)

A slave LTC6820 never transmits long (CS) pulses.
Furthermore, a slave will only transmit a short –1 pulse(when MISO = 0), never a +1 pulse. This allows for multiple slave devices on a single cable without risk of collisions (see Multidrop section).
isoSPI Pulse Specifications
Figure 2 details the timing specifications for the +1 and–1 isoSPI pulses. The same timing specifications apply toeither version of these symmetric pulses. In the Electrical+1 PULSE

A valid pulse must meet the minimum spec for t1/2PW andthe maximum spec for tINV. In other words, the half-pulse
width must be long enough to pass through the appropriate pulse timer, but short enough for the inversion to begin
within the valid window of time.
The response observed at MOSI, MISO or CS will occur
after delay tDEL from the pulse inversion.

Short –1 Pulse
if MISO = 0

1. Set MOSI = 0
2. Pulse SCK

Characteristics table, these specifications are further separated into CS (long) and Data (short) parameters.

SPI devices often use one clock edge to latch data andthe other edge to shift data. This avoids timing problems
associated with clock skew. There is no standard to specify whether the shift or latch occurs first. There is also no
requirement for data to be latched on a rising or falling
clock edge, although latching on the rising edge is mostcommon. The LTC6820 supports all four SPI operating
modes, as configured by the PHA and POL Pins.
Table 4. SPI Modes
MODE

POL

PHA

DESCRIPTION

0

0

0

SCK Idles Low, Latches on Rising (1st) Edge

1

0

1

SCK Idles Low, Latches on Falling (2nd) Edge

2

1

0

SCK Idles High, Latches on Falling (1st) Edge

3

1

1

SCK Idles High, Latches on Rising (2nd) Edge

VA
VTCMP
VIP – VIM
–VTCMP–VA

t1/2PW
t1/2PWtINV
tDEL

MOSI, MISO OR CS–1 PULSE

VA
VTCMP
VIP – VIM
–VTCMP

tINV
t1/2PW
t1/2PWtDEL–VA
MOSI, MISO OR CS

6820 F02

Figure 2. isoSPI Differential Pulse Detail

12

Rev C

For more information www.analog.com

LTC6820
OPERATION
If POL = 0, SCK idles low. Data is latched on the rising(first) clock edge if PHA = 0 and on the falling (second)
clock edge if PHA = 1.
If POL =1, SCK idles high. Data is latched on the falling(first) clock edge if PHA = 0 and on the rising (second)
clock edge if PHA = 1.
The two most common configurations are mode 0 (PHA =0 and POL = 0) and mode 3 (PHA = 1 and POL = 1)
because these modes latch data on a rising clock edge.
isoSPI Interaction and Timing
The timing diagrams in Figure 3 and Figure 4 show how
an isoSPI in master mode (connected to a SPI master)interacts with an isoSPI in slave mode (connected to a
SPI slave). Figure 3 details operation with PHA = 0 (andshows SCK signals for POL = 0 or 1). Figure 4 provides
the timing diagram for PHA = 1. Although not shown, it
is acceptable to use different SPI modes (PHA and POL
settings) on the master and slave devices.
A master SPI device initiates communication by lowering
CS. The LTC6820 converts this transition into a Long –1
pulse on its IP/IM pins. The pulse traverses the isolation
barrier (with an associated cable delay) and arrives at the
IP/IM pins of the slave LTC6820. Once validated, the Long
–1 pulse is converted back into a falling CS transition, thistime supplied to the slave SPI device. If slave PHA = 1,
SCK will also leave the idle state at this time.
Before the master SPI device supplies the first latchingclock edge (usually a rising edge, but see Table 4 forexceptions), the slave LTC6820 must transmit the initialslave data bit SN, which it determines by sampling thestate of MISO after a suitable delay.
If MISO = 0, the slave will transmit a Short –1 pulse to themaster. The master LTC6820 will receive and decode thepulse and set the master MISO = 0 (matching the slave).
However, if the slave MISO=1, the slave does not transmit
a pulse. The master will interpret this null response as a 1and set the master MISO = 1. This makes it possible toconnect multiple slave LTC6820’s to a single cable withno conflicting signals (see Multidrop section).
After the falling CS sequence, every latching clock edge
on the master converts the state of the MOSI pin into an

isoSPI data pulse (MN, MN–1, … M0) while simultaneously latching the slave’s data bit. As the slave LTC6820
receives each data bit it will set the slave MOSI pin to
the proper state and then generate an SCK pulse before
returning the slave’s MISO data (either as a Short –1
pulse, or as a null).
At the end of communication, the final data bit sent by
the slave (either as a pulse or null) will be ignored by
the master controller. (The slave LTC6820 must return adata bit since it cannot predict when communications willcease.) The master SPI device can then raise CS, which
is transmitted to the slave in the form of a Long +1 pulse.
The process ends with the slave LTC6820 transitioning
CS high, and returning SCK to the idle state if PHA = 1.
Rise TimeMOSI and MISO outputs have open-drain drivers. The risetime tRISE for the data output is determined by the pullup resistance and load capacitance. RPU must be smallenough to provide adequate setup and hold times.
Slow Mode
When configured for slave operation, the LTC6820 provides
two operating modes to ensure compatibility with a wide
range of SPI timing scenarios. These modes are referred
to as fast and slow mode, and are set using the SLOW pin.
When configured for master operation, the SLOW pin setting has no effect on the LTC6820 operation. In this case,
it is recommended to tie the SLOW pin to GND.
In fast mode (SLOW pin tied to GND), the LTC6820 can
operate at clock rates up to 1MHz (tCLK = 1µs). However,some SPI slave devices can’t respond quickly enough to
support this data rate. Fast mode requires a slave to operatewith setup and response times of 100ns, as well as 100ns
clock widths. In addition, allowances must be made for the
RC rise time of MOSI and MISO’s open-drain outputs. In
slow mode (SLOW pin tied to V+), the timing requirement
are relaxed at the expense of maximum data rate. As indicated in the Electrical Characteristics, the clock pulses andrequired setup and response times are increased to 0.9µs
minimum. Accordingly, the minimum tCLK (controlled by
the master) must be limited to 5µs. The SLOW pin setting
has no effect on the master LTC6820 (with MSTR = 1).

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Rev C

13

14

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MISO

MOSI

SCK (POL = 1)

SCK (POL = 0)

CS

ISO

ISO

MISO

MOSI

SCK (POL = 1)

SCK (POL = 0)

CS

0

SN

t9

SAMPLEtDEL(CS)
t16

500

CSB = 0

t10

t7

1000

t1

t2

MN

t4

tDEL(D)

2000

tRISE

tDEL(D)SAMPLE

SN-1

t3

MN-1

t12

2500
TIME (ns)

t13

t14

SAMPLE

SN-2

3000

SLAVE DOES NOTTRANSMIT +1

M0

Figure 3. Transceiver Timing Diagram (PHA = 0)

1500

tRTN

t8
tRISE

tCLK

3500

t6

4000

tDEL(CS)IGNORED

t10

t11

t18

4500

CSB = 1t56820 F03

5000

LTC6820

OPERATION

Rev C

For more information www.analog.com

MISO

MOSI

SCK (POL = 0)

SCK (POL = 1)

CS

ISO

ISO

MISO

MOSI

SCK (POL = 0)

SCK (POL = 1)

CS

0

SN

t9

SAMPLEtDEL(CS)
t16

500

t15

CSB = 0

t10

t7

1000

t1

t2

MN

t4

t8

2000

tRISE

tDEL(D)SAMPLE

SN-1

t3

MN-1

t12

TIME (ns)

2500

t13

t14

tDEL(D)SAMPLE

SN-2

3000

t6

3500

SLAVE DOES NOTTRANSMIT +1

MO

Figure 4. Transceiver Timing Diagram (PHA = 1)

1500

tRTN

tRISE

tCLK

4000

tDEL(CS)IGNORED

t10

t11

t18

4500

t17

CSB = 1t56820 F04

5000

LTC6820

OPERATION

Rev C

15

LTC6820
OPERATION
Figure 6 demonstrates slow mode, as compared to fastmode in Figure 5.
IP-IM
2V/DIVSCK
5V/DIV

VDD

VDD

+
–

VICMP
+ 167mV
3

OPEN WHEN IDLE

POS

IP

MOSI
5V/DIV

35k

MISO
5V/DIV

35k

RM

VDD = 5V
VDDS = 5V

200ns/DIV

6820 F05

IM

NEG

POS
NEG

Figure 5. Fast Mode (SLOW = 0)

20 • IBVIP – VIM

IP-IM
2V/DIVSCK
5V/DIV

6820 F07

Figure 7. Pulse Driver
25

VDD = 5V
VDDS = 5V

1µs/DIV

6820 F06

Figure 6. Slow Mode (SLOW = 1)

IP and IM Pulse Driver
The IP and IM pins transmit and receive the isoSPI pulses.
The transmitter uses a current-regulated driver (seeFigure 7) to establish the pulse amplitude, as determinedby the IBIAS pin current, IB, and the load resistance. The
sinking current source is regulated to 20x the bias current
IB. The sourcing current source operates in a currentstarved (resistive) manner to maintain the sourcing pin’s
voltage near VDD, as shown in Figure 8 and Figure 9. The
common mode voltage (while driving) is dependent on
bias current and output amplitude.
The output driver will regulate the common mode andpeak swing of IP and IM to the proper levels, allowing fora broad range of output amplitude with fairly flat gain, as
shown in Figure 10.

SOURCING OUTPUT

20
1V AMPLITUDE

15

SINKING OUTPUT

10

5
0

VDD = 3V
IB = 1mA
0

1
1.5
2
VIP OR VIM (V)

0.5

2.5

3
6820 F08

Figure 8. Drive Source/Sink vs Output Voltage
3.0
SOURCINGOUTPUT

2.5
OUTPUT VOLTAGE (V)MISO
5V/DIV

SOURCE/SINK CURRENT (mA)MOSI
5V/DIV

2.0

VCM

1.5
1.0

SINKINGOUTPUT

0.5
0

VDD = 3V
IB = 1mA
0

0.5

1
1.5
2
PULSE AMPLITUDE (V)2.5

36820 F09

Figure 9. Output Voltages and Common Mode vs Amplitude

16

Rev C

For more information www.analog.com

LTC6820
OPERATION
25

3.0

TRANSMIT SHORT +1

20

2.0

15

VOLTAGE (V)

CURRENT GAIN (mA/mA)

2.5

10

IM

RECEIVE SHORT –1

1.0
0.5

IP-IM

0
–0.5

5
0

IP

1.5

VDD = 3V
IS = 1mA
00.5

VDD = 3V
IB = 1mA

–1.0
1
1.5
2
PULSE AMPLITUDE (V)

2.5

–1.5

3

0

200

1000

800

600
400
TIME (ns)6820 F106820 F11

Figure 10. AIB Current Gain vs Amplitude

Figure 11. Transmitting and Receiving Data

This type of driver does not require a center-tapped transformer, but such a transformer may improve noise immunity, especially if it has a common mode choke. See theApplications Information section for additional details.

IDLE
IDLE
TIMEOUT(tIDLE)

Receiver Common Mode Bias

WAKE-UP SIGNAL(tREADY)
READYWhen not transmitting, the output driver maintains IP and
IM near VDD with a pair of 35k (RIN) resistors to a voltage of VDD – VICMP/3 – 167mV. This weak bias net-workholds the outputs near their desired operating point without significantly loading the cable, which allows a large
number of LTC6820’s to be paralleled without affecting
signal amplitude.
Figure 11 shows the differential and single-ended IP and
IM signals while transmitting and receiving data. The
driver forces the common mode voltage it needs whiletransmitting, then it returns to the bias level with a time
constant of RIN • CLOAD/2, where CLOAD is the sum of thecapacitance at the IP and IM pins.
When the LTC6820 is in low power IDLE mode, the bias
voltage is disconnected from the 35k resistors, resulting
in a 70k differential load.
State Diagram
During periods of no communication, a low current IDLE
(or shutdown) state is available to reduce power. In the
IDLE state the LTC6820 shuts down most of the circuitry.
A slave device uses a low current comparator to monitor
for activity, so it has larger IDLE current.

NO ACTIVITY
ON isoSPIPORTTRANSMIT/RECEIVE

ACTIVE

6820 F12

Figure 12. State Diagram

In the READY state all circuitry is enabled and ready totransmit or receive, but is not actively transmitting on IP
and IM.
Supply current increases when actively communicating,so this condition is referred to as the ACTIVE state.
Supply Current
Table 5 provides equations for estimating IDD in each state.
The results are for average supply current (as opposedto peak currents), and make the assumption that a slave
is returning an equal number of 0s and 1s (significant
because the slave doesn’t generate +1 data pulses, so theaverage driver current is smaller).

Rev C

For more information www.analog.com

17

LTC6820
OPERATION
Table 5. IDD Equations
STATE
IDLE

MSTR

ESTIMATED IDD

0 (slave)

2µA

1 (master)

1µA

READY

0 or 1

1.7mA + 3 • IB

ACTIVE0 (slave)⎛
100ns • 0.5 ⎟⎞2mA + ⎜⎜ 3 + 20 •⎟⎟ • IB
⎜
t CLK
⎝
⎠

1 (master)⎛
100ns ⎞⎟
2mA + ⎜⎜ 3 + 20 •⎟ • IB⎜t CLK ⎟⎠⎝

Figure 15 demonstrates a simple procedure for waking
a master (MSTR = 1) LTC6820 and its connected slave(MSTR = 0). A negative edge on CS causes the masterto drive IBIAS to 2V and, after a short delay, transmit along +1 pulse. (If CS remains low throughout tREADY, theLTC6820 would first generate a –1 pulse, then the +1
pulse when CS returns high). The long pulse serves as a
wake-up signal for the slave device, which responds by
driving its IBIAS pin to 2V and entering the READY state.
240mV

IDLE Mode and Wake-Up Detection
To conserve power, an LTC6820 in slave mode (MSTR = 0)
will enter an IDLE state after 5.7ms (tIDLE) of inactivity on
the IP/IM pins. In this condition IDD is reduced to lessthan 6µA and the SPI pins are idled (CS = 1, MOSI = 1
and SCK = POL).

A LTC6820 in master mode (MSTR = 1) doesn’t use thewake-up detection comparator. A falling edge on CS will
enable the isoSPI port within tREADY, and the LTC6820
will transmit a long (CS) pulse as it leaves the IDLE state.
(The polarity of the pulse matches the CS state at the endof tREADY).
The master LTC6820 will remain in the READY/ACTIVE
state as long as CS = 0. If CS transitions high and EN = 0
it will enter the IDLE state, but not until tIDLE expires.
This prevents the device from shutting down between
data packets.
In either master or slave mode the IDLE feature may bedisabled by driving EN high. This forces the device toremain “ready” at all times.

18

240ns DELAY(FILTER)|IPAC–IMAC| > 240mV
240ns

IM

SLAVE

IMAC

MASTERCS
WAKE-UP
IDLE TIMER

The LTC6820 will continue monitoring the IP and IM pinsusing a low power AC-coupled detector. It will wake up
when it sees a differential signal of 240mV or greaterthat persists for 240ns or longer. In practice, a long (CS)
isoSPI pulse is sufficient to wake the device up. Once thecomparator generates the wake-up signal it can take up
to 8µs (tREADY) for bias circuits to stabilize.
Figure 14 details the sequence of waking up a slave LTC6820(placing it in the READY state), using it to communicate,then allowing it to return to the low power IDLE state.

IPAC

IP

EN

tREADYREADY(IBIAS = 2V)

tIDLE6820 F13

Figure 13. Wake-Up Detection and IDLE Timer
REJECTSCOMMON MODE
NOISE
IP
IM
IP-IM
READY

tDWELLtIDLE

tREADYOK TO COMMUNICATE
6820 F14

Figure 14. Slave LTC6820 Wake-Up/Idle Timing

ALLOW >2 • tREADY TO WAKE
MASTER AND SLAVEMASTER CS
tIDLE

tREADYMASTER
IBIAS
IP-IM

tDWELLSLAVE
IBIAStREADYtIDLESLAVE CS
6820 F15

Figure 15. Master and Slave Wake-Up/Idle Sequence

Rev C

For more information www.analog.com

LTC6820
OPERATION
MultidropnMultiple slaves can be connected to a single master by connecting them in parallel (multidrop configuration)along one
cable. As shown in Figure 16, the cable should be terminatedonly at the beginning (master) and the end. In between, theadditional LTC6820’s and their associated slave devices will
be connected to “stubs” on the cable. These stubs should
be kept short, with as little capacitance as possible, to avoid
degrading the termination along the cable.
The multidrop scheme is only possible if the SPI slaves
have certain characteristics:

MASTER

LTC6820

SDO
SDI
SCK
CS

MSTR
MOSI IP
MISO
SCK
IM
CS

n

The SPI slaves must be addressable, because they will
all see the same CS signal (as decoded by each slave
LTC6820).
When not addressed, the slave SDO must remain high.

When a slave is not addressed, its LTC6820 will not transmit data pulses as long as MISO (the SPI device’s SDO)
remains high. This eliminates the possibility for collisions,as only the addressed slave device will ever be returning
data to the master.

LTC6820
IP

MSTR

MOSI
MISO
IM SCK
CS

RM

1

SDI
SDO
SCK
CS

1

1

LTC6820SLAVE 2

IP

MSTR

MOSI
MISO
IM SCK
CS

2

SDI
SDO
SCK
CS

2

2

LTC6820SLAVE 3IP
RM

SLAVE 1

MSTR

MOSI
MISO
IM SCK
CS
3

3

SDI
SDO
SCK
CS
3
6820 F16

Figure 16. Multidropping Multiple Slaves on a Single Cable

Rev C

For more information www.analog.com

19

LTC6820
APPLICATIONS INFORMATION
isoSPI Setup

For cables over 50 meters:

The LTC6820 allows each application to be optimized for
power consumption or for noise immunity. The power
and noise immunity of an isoSPI system is determinedby the programmed IB current. The IB current can range
from 0.1mA to 1mA. A low IB reduces the isoSPI power
consumption in the READY and ACTIVE states, while ahigh IB increases the amplitude of the differential signal
voltage VA across the matching termination resistor, RM.
IB is programmed by the sum of the RB1 and RB2 resistors connected between the IBIAS pin and GND. For mostapplications setting IB to 0.5mA is a good compromise
between power consumption and noise immunity. Using
this IB setting with a 1:1 transformer and RM = 120Ω, RB1should be set to 2.8k and RB2 set to 1.2k. In a typical CAT5
twisted pair these settings will allow for communication
up to 50m.
For applications that require cables longer than 50m it isrecommended to increase the amplitude VA by increasing
IB to 1mA. This compensates for the increased insertion
loss in the cable and maintains high noise immunity. So
when using cables over 50m and, again, using a transformer with a 1:1 turns ratio and RM = 120Ω, RB1 would
be 1.4k and RB2 would be 600Ω.
Other IB settings can be used to reduce power consumption or increase the noise immunity as required by theapplication. In these cases when setting VICMP and choosing RB1 and RB2 resistor values the following rules should
be used:For cables 50 meters or less:
IB = 0.5mA
VA = (20 • IB) • (RM/2)
VTCMP = 1/2 • VA
VICMP = 2 • VTCMP

IB = 1mA
VA = (20 • IB) • (RM/2)
VTCMP = 1/4 • VA
VICMP = 2 • VTCMP
RB2 = VICMP/IB⎛ 2V ⎞⎟ –R
R B1 = ⎜⎜
B2
⎟
I
⎝ B ⎠

The maximum data rate of an isoSPI link is determined by
the length of the cable used. For cables 10 meters or lessthe maximum 1MHz SPI clock frequency is possible. As
the length of the cable increases the maximum possible
SPI clock rate decreases. This is a result of the increased
propagation delays through the cable creating possible
timing violations.
Cable delay affects three timing specifications, tCLK, t6,
and t7. In the Electrical Characteristics table, each isderated by 100ns to allow for 50ns of cable delay. For
longer cables, the minimum timing parameters may be
calculated as shown below:
tCLK, t6, and t7 > 0.9µs + 2 • tCABLE
Pull-Up Resistance Considerations
The data output (MOSI if MSTR = 0, MISO if MSTR =1) requires a pull-up resistor, RPU. The rise time tRISE isdetermined by RPU and the capacitance on the pin. RPU
must be small enough to provide adequate setup and holdtimes. For a slave device, the time constant must be lessthan t12 and t14. In fast mode, 50ns is recommended.
RPU < 50ns/CLOAD
Larger pull-up resistances, up to 5k, can be used in slow
mode.

RB2 = VICMP/IB⎛ 2V ⎞⎟ –R
R B1 = ⎜⎜
B2
⎟
I
⎝ B ⎠

20

Rev C

For more information www.analog.com

LTC6820
APPLICATIONS INFORMATION
Table 6. Typical RB1 and RB2 Values
MAX CABLELENGTH

TURNS
RATIO

TERMINATIONRESISTANCE

IB

VA

VTCMP

VICMP

RB2

RB1

IDRV

READY
CURRENT

100m

1 :1

120Ω

1mA

1.2V

0.3V

0.6V

604Ω

1.4k

20mA

4.7mA

50m

1 :1

120Ω

0.5mA

0.6V

0.3V

0.6V

1.21k

2.8k

10mA

3.2mA

100m

1 :1

75Ω

1mA

0.75V

0.19V

0.38V

374Ω

1.62k

20mA

4.7mA

50m

1 :1

75Ω

0.5mA

0.375V

0.19V

0.38V

750Ω

3.24k

10mA

3.2mA

Transformer Selection Guide
As shown in Figure 1, a transformer or a pair of transformers are used to isolate the IP and IM signals between the
two LTC6820’s. The isoSPI signals have programmablepulse amplitudes up to 1.6V, and pulse widths of 50ns
and 150ns. To meet these requirements, choose a transformer having a magnetizing inductance ranging from
50µH to 350µH, and a 1:1 or 2:1 turns ratio. Minimizing
transformer insertion loss will reduce required transmit
power; generally an insertion loss of less than –1.5dB is
recommended.

For optimal common mode noise rejection, choose a center-tapped transformer or a transformer with an integrated
common mode choke. The center tap can be tied to a 27pF
or smaller capacitor (larger will restrict the driver’s ability to set the common mode voltage). If the transformer
has both a center tap and common mode choke on the
primary side, a larger capacitor may be used.
Table 7 shows a recommended list of transformers for use
with the LTC6820. 10/100BaseTX Ethernet transformers
are inexpensive and work very well in this application.
Ethernet transformers often include a common mode
choke, which will improve common mode rejection ascompared to other transformers.

Table 7. Recommended Transformers
MANUFACTURERPART NUMBER

ISOLATION VOLTAGE

TURNS RATIOCENTER TAP

CM CHOKE

PCA

EPF8119SE

1500VRMS

1:1

Yes

Yes

Halo

TG110-AE050N5LF

1500VRMS

1:1

Yes

Yes

Pulse

PE-68386NL

1500V DC

1:1

No

No

Murata78613/3C

1000VRMS

1:1

Yes

No

Murata78604/3C

1000VRMS

2:1

No

No

Pulse

HX1188NL

1500VRMS

1:1

Yes

Yes

EPCOS

B82804A0354A110

1500V DC

1:1

No

No

µC
SDO
SDI
SCK
CS

µC
SDO
SDI
SCK
CS

2:1 Transformers

LTC6820MSTR
MOSI IP
MISO
SCK
IM
CS

2:1

1:2

480Ω

IP
480Ω

Single-Transformer Isolation

LTC6820MSTR
MOSI IP
MISO
SCK
IM
CS

LTC6820MOSIMISOIM SCK
CS

SDO
SCK
CS

LTC6820

LTC6802

IP
120Ω

120Ω

LTC2452

MSTR

MSTR

MOSI
MISO
IM SCK
CS

SDI
SDO
SCK
CS
6820 F17

Figure 17. Alternative Isolation Barriers

For more information www.analog.com

Rev C

21

LTC6820
APPLICATIONS INFORMATION
Capacitive Isolation Barrier

use a transformer with a center tap and a common mode
choke as shown in Figure 19. The center tap of the transformer should be bypassed with a 27pF capacitor. The
center tap capacitor will help attenuate common mode
signals. Large center tap capacitors should be avoided asthey will prevent the isoSPI transmitters common mode
voltage from settling.

In some applications, where the environment is relatively
noise free and only galvanic isolation is required, capacitors can be used in place of transformers as the isolation
barrier. With capacitive coupling, the twisted pair cableis driven by a voltage and is subject to signal loss withcable length. This low cost isolated solution can be suitable for short distance interconnections (1 meter or less),such as between adjacent circuit boards or across a large
PCB. The capacitors will provide galvanic isolation, but nocommon mode rejection. This option uses the drivers ina different way, by using pull up resistors to maintain thecommon mode near VDD, only the sinking drive current
has any effect. Figure 18 shows an example application
circuit using a capacitive isolation barrier capable of driving 1 meter of cable.
MANUFACTURER PART NUMBER
Murata

GCM188R72A104KA64

CAPACITANCE

VOLTAGERATING

100nF

100V

To improve common mode current rejection a common
mode choke should also be placed in series with the IP
and IM lines of the LTC6820. The common mode choke
will both increase EMI immunity and reduce EMI emission.
When choosing a common mode choke, the differential
mode impedance should be 20Ω or less for signals 50MHz
and below. Generally common mode chokes similar to
those used in Ethernet applications are recommended.
Table 8. Recommended Common Mode Chokes
MANUFACTURER PART NUMBER
TDK

EMC

DIFFERENTIAL COMMON MODE
IMPEDANCE AT IMPEDANCE AT
50MHz
50MHz

ACT45B-220-2P

20Ω

5000Ω

When using the LTC6820, for the best electromagnetic
compatibility (EMC) performance it is recommended to
Capacitive IsolationµC

LTC6820

SDO
SDI
SCK
CS

MSTR
MOSI IPMISOSCK IMCS

LTC6820

LTC2640

MSTR

100nF
IP

MOSI
MISO

SDI

IM

SCK
CS

SCK
CS

100nF

6820 F18

Figure 18. Capacitive Isolation Barrier

LTC6820
IP
IM

27pF
120Ω

6820 F19

Figure 19. Connection of Transformer and Common Mode Choke

22

Rev C

For more information www.analog.com

LTC6820
APPLICATIONS INFORMATION
Layout of the isoSPI signal lines also plays a significant
role in maximizing the immunity of a circuit. The following
layout guidelines should be followed:
1. The transformer should be placed as close to the isoSPI cable connector as possible. The distance should
be kept less than 2cm. The LTC6820 should be placed
at least 1cm to 2cm away from the transformer to help
isolate the IC from the magnetic coupling fields.
2. On the top layer, no ground plane should be placed
under the magnetic, the isoSPI connector, or in
between the transformer and the connector.
3. The IP and IM traces should be isolated from surrounding circuits. No traces should cross the IP and
IM lines, unless separated by a ground plane within
the printed circuit board.
The isoSPI drive currents are programmable and allow fora tradeoff between power consumption and noise immunity. The noise immunity of the LTC6820 has been evaluated using a bulk current injection (BCI) test. The BCI test

injects current into the twisted-pair lines at set levels overa frequency range of 1MHz to 400MHz. With the minimum IB current, 0.1mA, the isoSPI serial link has beenshown to pass a 40mA BCI test with no bit errors. A 40mA
BCI test level is sufficient for most industrial applications.
Automotive applications tend to have a higher BCI requirement so the recommended IB is set to 1mA, the maximum
power level. The isoSPI system has been shown to pass a
200mA BCI test with no transmitted bit errors. The 200mA
test level is typical for automotive testing.
Software Layer
The isoSPI physical layer has high immunity to EMI andis not particularly susceptible to bit errors induced bynoise, but for best results in a high noise environment it
is recommended to implement a software layer that uses
an error detection code like a cyclic redundancy checkor check sum. Error detection codes will allow software
detection of any bit error and will notify the system to retry
the last erroneous serial communication.

1.5cm

1cm

IP

IM

CONNECTOR

6820 F20

Figure 20. Example Layout

Rev C

For more information www.analog.com

23

LTC6820
TYPICAL APPLICATIONS
Remote Sensor Monitor with Micropower Shutdown
LTC6820
IBIAS
ICMP
VDDS
GND
SLOW
VDD
MSTR
POL
MISO
PHA
MOSI
SCK
IP
CS
IM
EN
5V
100nF
2k

2.8k
1.21k

1.21k

2.8k

5V
100nF

120Ω

1

16

1

16

2

15

2

15

3

14

3

14

HX1188NL

LTC6820

IBIAS
ICMP
GND
SLOW
MSTR
IP
IM
PHA
POL
VDD

120Ω

HX1188NL

LT6656-3

+

100nF

EN
CS
SCK
MISO
MOSI

VDDS
3V
1µF

3.6V

+

IN+

VREF

VCC
MISO

LTC2452

TO SENSOR

–

SCK
CS

IN–

6820 TA02

IQ SHUTDOWN = 3.7µA

100 Meter Remote DAC Control
LTC6820
IBIAS
ICMP
VDDS
GND
SLOW
VDD
MSTR
POL
MISO
PHA
MOSI
SCK
IP
CS
IM
EN
3V
100nF
2k

1.4k
604Ω

604Ω

1.4k

5V
100nF

120Ω

1

16

1

16

2

15

2

15

3

14

3

14

HX1188NL

LTC6820

IBIAS
ICMP
GND
SLOW
MSTR
IP
IM
PHA
POL
VDD

120Ω

HX1188NL

LT6656-3

+

100nF

EN
CS
SCK
MISO
MOSI
2k
VDDS
3V
1µF

3.6V
VREF

VCC
SDI

VOUT

OUT

LTC2640

SCK
CS

GND

24

6820 TA03

Rev C

For more information www.analog.com

LTC6820
TYPICAL APPLICATIONSInterfacing to Addressable Stack of LTC6804-2 Multicell Battery Monitors
LTC6804-2
VREG
ISOMD
A3
A2
A1
IBIAS
A0
2

IPA

ICMP

IMA

VM

120Ω

806Ω
1.21k
2

LTC6804-2
VREG
ISOMD
A3
A2
A1
IBIAS
A0
1

IPA

ICMP

IMA

VM

806Ω
1.21k

LTC6820
IBIAS
ICMP
VDDS
GND
SLOW
VDD
MSTR
POL
MISO
PHA
MOSI
SCK
IP
CS
IM
EN

5V
100nF
2k

806Ω

1
1.21k

LTC6804-2
VREG
ISOMD
A3
A2
A1
IBIAS
A0

5V
100nF
0

IPA

ICMP

IMA

VM

120Ω

806Ω
1.21k

6820 TA05

0

Rev C

For more information www.analog.com

25

LTC6820
TYPICAL APPLICATIONS
Battery Monitoring System Using a Multidrop isoSPI Link
LTC6803-2
1.21k

GND3

806Ω

VDD3

LTC6820

IBIAS
ICMP
GND
SLOW
MSTR

EN
MOSI
MISO
SCK
CS

IP
IM
VDD

VDDS
POL
PHA

A3
A2
A1
A0

GND3
MOSI
MISO
SCK
CS

VSTACK3
GND3
100Ω

VREG

CZT3055

2k
120Ω

2k
VDD3
LTC6803-2

1.21k

GND2

806Ω

VDD2

LTC6820

IBIAS
ICMP
GND
SLOW
MSTR

GND2

EN
MOSI
MISO
SCK
CS

MOSI
MISO
SCK
CS

A3
A2
A1
A0

VSTACK2
GND2
100Ω

VREG

CZT3055

2k
IP
IM
VDD

5V
100nF
2k

26

LTC6820
EN
IBIAS
ICMP
VDDS
GND
SLOW
VDD
MSTR
POL
MISO
PHA
MOSI
SCK
IP
CS
IM

VDDS
POL
PHA

2k
VDD2
LTC6803-2

806Ω

1.21k

806Ω

1.21k

5V
100nF

GND1

VDD1

LTC6820

IBIAS
ICMP
GND
SLOW
MSTR

EN
MOSI
MISO
SCK
CS

IP
IM
VDD

VDDS
POL
PHA

GND1
MOSI
MISO
SCK
CS

A3
A2
A1
A0
VREG

VSTACK1
GND1100Ω

CZT3055

2k
120Ω

2k
VDD1

6820 TA04

Rev C

For more information www.analog.com

LTC6820
PACKAGE DESCRIPTIONUD Package
16-Lead Plastic QFN (3mm × 3mm)

(Reference LTC DWG # 05-08-1700 Rev A)

Exposed Pad Variation AA

0.70 ±0.05

3.50 ±0.05
1.65 ±0.05
2.10 ±0.05 (4 SIDES)

PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
3.00 ±0.10(4 SIDES)

BOTTOM VIEW—EXPOSED PAD
PIN 1 NOTCH R = 0.20 TYP
OR 0.25 × 45° CHAMFER

R = 0.115
TYP

0.75 ±0.05

15

PIN 1
TOP MARK(NOTE 6)16
0.40 ±0.10
11.65 ±0.10(4-SIDES)

20.200 REF

0.25 ±0.05(UD16 VAR A) QFN 1207 REV A

0.00 – 0.05
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WEED-4)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATIONON THE TOP AND BOTTOM OF PACKAGE

0.50 BSC

Rev C

For more information www.analog.com

27

LTC6820
PACKAGE DESCRIPTIONMS Package
16-Lead Plastic MSOP

(Reference LTC DWG # 05-08-1669 Rev A)
0.889 ±0.127(.035 ±.005)

5.10(.201)
MIN

3.20 – 3.45(.126 – .136)

4.039 ±0.102(.159 ±.004)(NOTE 3)0.50(.0197)BSC

0.305 ±0.038(.0120 ±.0015)
TYP

16151413121110 9

RECOMMENDED SOLDER PAD LAYOUT

0.254(.010)DETAIL “A”

3.00 ±0.102(.118 ±.004)(NOTE 4)4.90 ±0.152(.193 ±.006)

0° – 6° TYP

0.280 ±0.076(.011 ±.003)
REF

GAUGE PLANE

0.53 ±0.152(.021 ±.006)
DETAIL “A”

0.18(.007)SEATING
PLANE

1.10(.043)
MAX

1234567 8

0.17 – 0.27(.007 – .011)
TYP

0.86
(.034)
REF

0.1016 ±0.0508(.004 ±.002)

0.50
MSOP (MS16) 0213 REV A
NOTE:(.0197)
1. DIMENSIONS IN MILLIMETER/(INCH)
BSC
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

28

Rev C

For more information www.analog.com

LTC6820
REVISION HISTORY
REV

DATE

DESCRIPTION

A

06/13

Web hyperlinks added.

PAGE NUMBER

Note 8 added to Electrical Characteristics section.

5

B

01/17

Patent Information added.
Web Links updated.

1
All

C

05/19

Specifications for isoSPI Timing-Master modified to support operation up to 2Mbps

4

1 to 30

Rev C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license For
is granted
implication orotherwise under any patent or patent rights of Analog Devices.
more byinformationwww.analog.com

29

LTC6820
TYPICAL APPLICATIONInterfacing to Daisy-Chained Stack of LTC6804-1 Multicell Battery Monitors
LTC6804-1
IPB

VREG
ISOMD

IMB

IBIAS

IPA

ICMP

IMA

VM

806Ω
120Ω

1.21k
GND4
LTC6804-1
IPB

VREG
ISOMD

IMB

IBIAS

IPA

ICMP

IMA

VM

120Ω
806Ω
120Ω

5V
100nF
2k

LTC6820
EN
IBIAS
ICMP
VDDS
GND
SLOW
VDD
MSTR
POL
MISO
PHA
MOSI
SCK
IP
CS
IM

806Ω

1.21k
GND3

1.21k

LTC6804-1

5V
100nF

IPB

VREG
ISOMD

IMB

IBIAS

IPA

ICMP

IMA

VM

120Ω
806Ω
120Ω

120Ω

1.21k

6820 TA06

GND2

RELATED PARTS
PART NUMBER

DESCRIPTIONCOMMENTS

LTC6803-2/
LTC6803-4

Multicell Battery Stack Monitor with an Individually
Addressable SPI Interface

Functionality Equivalent to LTC6803-1/LTC6803-3, Allows for Parallel
Communication Battery Stack Topologies

LTC6803-1/
LTC6803-3

Multicell Battery Stack Monitor with Daisy-Chained
SPI Interface

Functionality Equivalent to LTC6803-2/LTC6803-4, Allows for Multiple
Devices to Be Daisy Chained

LTC6903

1kHz to 68MHz Programmable Silicon Oscillator withSPI Interface

Frequency Resolution of 0.01%. No External Components Required.
Operates on 2.7V to 5.5V

LTC6804-1/
LTC6804-2

Multicell Battery Stack Monitor with Built-In isoSPIInterface

Includes isoSPI Interfaces for Communication with Master LTC6820
and to other LTC6804 Devices

30

Rev C
05/19

www.analog.com
For more information www.analog.com

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