ATmega128RFA1
Features®

• High Performance, Low Power AVR 8-Bit Microcontroller• Advanced RISC Architecture- 135 Powerful Instructions – Most Single Clock Cycle Execution- 32x8 General Purpose Working Registers- Fully Static Operation- Up to 16 MIPS Throughput at 16 MHz and 1.8V
- On-Chip 2-cycle Multiplier• Non-volatile Program and Data Memories- 128K Bytes of In-System Self-Programmable Flash• Endurance: 2000 Write/Erase Cycles @ 85°C
- 4K Bytes EEPROM• Endurance: 2000 Write/Erase Cycles @ 85°C
- 16K Bytes Internal SRAM
• JTAG (IEEE std. 1149.1 compliant) Interface- Boundary-scan Capabilities According to the JTAG Standard- Extensive On-chip Debug Support- Programming of Flash EEPROM, Fuses and Lock Bits through the JTAG interface• Peripheral Features- Multiple Timer/Counter & PWM channels- Real Time Counter with Separate Oscillator- 10-bit, 330 ks/s A/D Converter; Analog Comparator; On-chip Temperature Sensor- Master/Slave SPI Serial Interface- Two Programmable Serial USART- Byte Oriented 2-wire Serial Interface• Advanced Interrupt Handler• Watchdog Timer with Separate On-Chip Oscillator• Power-on Reset and Low Current Brown-Out Detector• Advanced Power Save Modes• Fully integrated Low Power Transceiver for 2.4 GHz ISM Band
- Supported Data Rates: 250 kb/s and 500 kb/s, 1 Mb/s, 2 Mb/s
- -100 dBm RX Sensitivity; TX Output Power up to 3.5 dBm- Hardware Assisted MAC (Auto-Acknowledge, Auto-Retry)- 32 Bit IEEE 802.15.4 Symbol Counter- Baseband Signal Processing- SFR-Detection, Spreading; De-Spreading; Framing ; CRC-16 Computation- Antenna Diversity and TX/RX control- TX/RX 128 Byte Frame Buffer• Hardware Security (AES, True Random Generator)• Integrated Crystal Oscillators (32.768 kHz & 16 MHz)• I/O and Package- 38 Programmable I/O Lines- 64-pad QFN (RoHS/Fully Green)• Temperature Range: -40°C to 85°C Industrial• Supply voltage range 1.8V to 3.6V with integrated voltage regulators• Ultra Low Power consumption (1.8 to 3.6V) for Rx/Tx & AVR: <18.6 mA- CPU Active Mode (16MHz): 4.1 mA- 2.4GHz Transceiver: RX_ON 12.5 mA / TX 14.5 mA (maximum TX output power)- Deep Sleep Mode: <250nA @ 25°C
• Speed Grade: 0 – 16 MHz @ 1.8 – 3.6V

8-bit
Microcontroller
with Low Power
2.4GHzTransceiver for
ZigBee andIEEE 802.15.4
ATmega128RFA1PRELIMINARY

Applications®

• ZigBee / IEEE 802.15.4-2006/2003™ – Full And Reduced Function Device (FFD/RFD)• General Purpose 2.4GHz ISM Band Transceiver with Microcontroller• RF4CE, SP100, WirelessHART™, ISM Applications and IPv6 / 6LoWPAN

8266A-MCU Wireless-12/09

1
8266A-MCU Wireless-12/09

1 Pin Configurations[PE3:OC3A:AIN1][PE4:OC3B:INT4][PE5:OC3C:INT5][PE6:T3:INT6][PE7:ICP3:INT7:CLKO][DEVDD][DVSS][XTAL2][AVSS][XTAL1][EVDD][AVDD][AVSS:ASVSS][AREF][PF0:ADC0][PF1:ADC1]

Figure 1-1. Pinout ATmega128RFA1

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49[PF2:ADC2:DIG2] 1

48 [PE2:XCK0:AIN0][PF3:ADC3:DIG4] 2

47 [PE1:TXD0][PF4:ADC4:TCK] 3

46 [PE0:RXD0:PCINT8]

Index corner[PF5:ADC5:TMS] 4

45 [DVSS][PF6:ADC6:TDO] 5

44 [DEVDD][PF7:ADC7:TDI] 6

43 [PB7:OC0A:OC1C:PCINT7]

ATmega128RFA1[AVSS_RFP] 7

42 [PB6:OC1B:PCINT6][RFP] 841 [PB5:OC1A:PCINT5][RFN] 940 [PB4:OC2A:PCINT4][AVSS_RFN] 10

39 [PB3:MISO:PDO:PCINT3][TST] 1138 [PB2:MOSI:PDI:PCINT2][RSTN] 12

37 [PB1:SCK:PCINT1][RSTON] 13

36 [PB0:SSN:PCINT0][PG0:DIG3] 14

35 [DVSS]

Exposed paddle: [AVSS][PG1:DIG1] 15

34 [DEVDD][PG2:AMR] 16

33 [CLKI]

Note:[PD7:T0][PD6:T1][PD5:XCK1][PD4:ICP1][PD3:TXD1:INT3][PD2:RXD1:INT2][PD1:SDA:INT1][PD0:SCL:INT0][DVSS][DEVDD][DVDD][DVDD][DVSS:DSVSS][PG5:OC0B][PG4:TOSC1][PG3:TOSC2]

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
00

The large center pad underneath the QFN/MLF package is made of metal and internally connected
to AVSS. It should be soldered or glued to the board to ensure good mechanical stability. If thecenter pad is left unconnected, the package might loosen from the board

2 Disclaimer
Typical values contained in this datasheet are based on simulation and characterization
results of other AVR microcontrollers and radio transceivers manufactured in a similar
process technology. Minimum and Maximum values will be available after the device ischaracterized.

2

ATmega128RFA1
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ATmega128RFA1
3 Overview
The ATmega128RFA1 is a low-power CMOS 8 bit microcontroller based on the AVR
enhanced RISC architecture combined with a high data rate transceiver for the 2.4 GHz
ISM band. It is derived from the ATmega1281 microcontroller and the AT86RF231 radiotransceiver.
By executing powerful instructions in a single clock cycle, the device achieves
throughputs approaching 1 MIPS per MHz allowing the system designer to optimize
power consumption versus processing speed.
The radio transceiver provides high data rates from 250 kb/s up to 2 Mb/s, frame
handling, outstanding receiver sensitivity and high transmit output power enabling avery robust wireless communication.

3.1 Block Diagram
Figure 3-1 Block Diagram

The AVR core combines a rich instruction set with 32 general purpose working
registers. All 32 registers are directly connected to the Arithmetic Logic Unit (ALU). Two
independent registers can be accessed with one single instruction executed in one
clock cycle. The resulting architecture is very code efficient while achieving throughputs
up to ten times faster than conventional CISC microcontrollers. The system includes
internal voltage regulation and an advanced power management. Distinguished by thesmall leakage current it allows an extended operation time from battery.
The radio transceiver is a fully integrated ZigBee solution using a minimum number ofexternal components. It combines excellent RF performance with low cost, small sizeand low current consumption. The radio transceiver includes a crystal stabilized
fractional-N synthesizer, transmitter and receiver, and full Direct Sequence Spread

3
8266A-MCU Wireless-12/09

Spectrum Signal (DSSS) processing with spreading and despreading. The device isfully compatible with IEEE802.15.4-2006/2003 and ZigBee standards.
The ATmega128RFA1 provides the following features: 128 kbytes of In-System
Programmable (ISP) Flash with read-while-write capabilities, 4 kbytes EEPROM, 16
kbytes SRAM, up to 35 general purpose I/O lines, 32 general purpose working
registers, Real Time Counter (RTC), 6 flexible Timer/Counters with compare modes
and PWM, USART, a byte oriented 2-wire Serial Interface, a 8 channel, 10 bit analog todigital converter (ADC) with an optional differential input stage with programmable gain,
programmable Watchdog Timer with Internal Oscillator, a SPI serial port, IEEE std.
1149.1 compliant JTAG test interface, also used for accessing the On-chip Debug
system and programming and 6 software selectable power saving modes.
The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, andinterrupt system to continue functioning. The Power-down mode saves the register
contents but freezes the Oscillator, disabling all other chip functions until the next
interrupt or hardware reset. In Power-save mode, the asynchronous timer continues torun, allowing the user to maintain a timer base while the rest of the device is sleeping.
The ADC Noise Reduction mode stops the CPU and all I/O modules except
asynchronous timer and ADC, to minimize switching noise during ADC conversions. In
Standby mode, the RC oscillator is running while the rest of the device is sleeping. This
allows very fast start-up combined with low power consumption. In Extended Standby
mode, both the main RC oscillator and the asynchronous timer continue to run.
Typical supply current of the microcontroller with CPU clock set to 16MHz and the radiotransceiver for the most important states is shown in the Figure 3-2 below.
Figure 3-2 Radio transceiver and microcontroller (16MHz) supply current
20

18,6mA

I(DEVDD,EVDD) [mA]

1.8V
3.0V
3.6V

16,6mA

15

10

5

0

4,1mA

4,7mA

SLEEP

TRX_OFF

250nA
Deep Sleep

RX_LISTEN

TX_ACT

Radio Transceiver State

The transmit output power is set to maximum. If the radio transceiver is in SLEEP modethe current is dissipated by the AVR microcontroller only.
In Deep Sleep mode all major digital blocks with no data retention requirements are
disconnected from main supply providing a very small leakage current. Watchdog timer,
MAC symbol counter and 32.768kHz oscillator can be configured to continue to run.
The device is manufactured using Atmel’s high-density nonvolatile memory technology.
The On-chip ISP Flash allows the program memory to be reprogrammed in-system
4

ATmega128RFA1
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ATmega128RFA1
trough an SPI serial interface, by a conventional nonvolatile memory programmer, or byon on-chip boot program running on the AVR core. The boot program can use any
interface to download the application program in the application Flash memory.
Software in the boot Flash section will continue to run while the application Flashsection is updated, providing true Read-While-Write operation. By combining an 8 bit
RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel
ATmega128RFA1 is a powerful microcontroller that provides a highly flexible and costeffective solution to many embedded control applications.
The ATmega128RFA1 AVR is supported with a full suite of program and systemdevelopment tools including: C compiler, macro assemblers, program
debugger/simulators, in-circuit emulators, and evaluation kits.

3.2 Pin Descriptions
3.2.1 EVDD
External analog supply voltage;
3.2.2 DEVDD
External digital supply voltage;
3.2.3 AVDD
Regulated analog supply voltage (internally generated);
3.2.4 DVDD
Regulated digital supply voltage (internally generated);
3.2.5 DVSS
Digital ground;
3.2.6 AVSS
Analog ground;
3.2.7 Port B (PB7...PB0)
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for eachbit). The Port B output buffers have symmetrical drive characteristics with both high sinkand source capability. As inputs, Port B pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port B also provides functions of various special features of the ATmega128RFA1.
3.2.8 Port D (PD7...PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for eachbit). The Port D output buffers have symmetrical drive characteristics with both high sinkand source capability. As inputs, Port D pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port D also provides functions of various special features of the ATmega128RFA1.
3.2.9 Port E (PE7...PE0)
Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for eachbit). The Port E output buffers have symmetrical drive characteristics with both high sinkand source capability. As inputs, Port E pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port E also provides functions of various special features of the ATmega128RFA1.

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3.2.10 Port F (PF7...PF0)
Port F is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for eachbit). The Port F output buffers have symmetrical drive characteristics with both high sinkand source capability. As inputs, Port F pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port F pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port F also provides functions of various special features of the ATmega128RFA1.
3.2.11 Port G (PG5…PG0)
Port G is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for eachbit). The Port G output buffers have symmetrical drive characteristics with both highsink and source capability. However the driver strength of PG3 and PG4 is reduced
compared to the other port pins. The output voltage drop (VOH, VOL) is higher while theleakage current is smaller. As inputs, Port G pins that are externally pulled low willsource current if the pull-up resistors are activated. The Port G pins are tri-stated whena reset condition becomes active, even if the clock is not running.
Port G also provides functions of various special features of the ATmega128RFA1.
3.2.12 AVSS_RFP
AVSS_RFP is a dedicated ground pin for the bi-directional, differential RF I/O port.
3.2.13 AVSS_RFN
AVSS_RFN is a dedicated ground pin for the bi-directional, differential RF I/O port.
3.2.14 RFP
RFP is the positive terminal for the bi-directional, differential RF I/O port.
3.2.15 RFN
RFN is the negative terminal for the bi-directional, differential RF I/O port.
3.2.16 RSTN
Reset input. A low level on this pin for longer than the minimum pulse length will
generate a reset, even if the clock is not running. Shorter pulses are not guaranteed togenerate a reset.
3.2.17 RSTON
Reset output. A low level on this pin indicates a reset initiated by the internal reset
sources or the pin RSTN.
3.2.18 XTAL1
Input to the inverting 16MHz crystal oscillator amplifier. In general a crystal between
XTAL1 and XTAL2 provides the 16MHz reference clock of the radio transceiver.
3.2.19 XTAL2
Output of the inverting 16MHz crystal oscillator amplifier;3.2.20 AREF
Reference voltage output of the A/D Converter. In general this pin is left open.
3.2.21 TST
Programming and test mode enable pin;
3.2.22 CLKI
Input to the clock system. If selected, it provides the operating clock of the
microcontroller.

3.3 Compatibility to ATmega1281/2561
The basic AVR feature set of the ATmega128RFA1 is derived from theATmega1281/2561. Address locations and names of the implemented modules and6

ATmega128RFA1
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ATmega128RFA1
registers are unchanged as long as it fits the target application of a very small andpower efficient radio system. In addition, several new features were added.
Backward compatibility of the ATmega128RFA1 to the ATmega1281/2561 is provided
in most cases. However some incompatibilities between the microcontrollers exist.
3.3.1 Port A and Port C
Port A and Port C are not implemented. The associated registers are available but will
not provide any port control. Remaining ports are kept at their original address location
to not require changes of existing software packages.
3.3.2 External Memory Interface
The alternate pin function “External Memory interface” using Port A and Port C is not
implemented due to the missing ports.
The large internal data memory (SRAM) does not require an external memory and theassociated parallel interface. It keeps the system radiation (EMC) at a very small levelto provide very high sensitivity at the antenna input.
3.3.3 High Voltage Programming Mode
Alternate pin function BS2 (high voltage programming) of pin PA0 is mapped to adifferent pin. Entering the parallel programming mode is controlled by the TST pin.
3.3.4 AVR Oscillators and External Clock
The AVR microcontroller can utilize the high performance crystal oscillator of the
2.4GHz transceiver connected to the pins XTAL1 and XTAL2. An external clock can beapplied to the microcontroller using the clock input CLKI.
3.3.5 Analog Frontend
The ATmega128RFA1 has a new A/D converter. Software compatibility is basicallyassured. Nevertheless to benefit from the higher conversion speeds and the better
performance some changes are required.

4 Resources
A comprehensive set of development tools and application notes, and datasheets areavailable for download on http://www.atmel.com.

5 About Code Examples
This documentation contains simple code examples that briefly show how to use
various parts of the device. Be aware that not all C compiler vendors include bit
definitions in the header files and interrupt handling in C is compiler dependent. Pleaseconfirm with the C compiler documentation for more details.
These code examples assume that the part specific header file is included before
compilation. For I/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC","CBI", and "SBI" instructions must be replaced with instructions that allow access toextended I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and"CBR".

6 Data Retention
Reliability Qualification results show that the projected data retention failure rate for the
given ambient temperature is less than TBD PPM

7
8266A-MCU Wireless-12/09

• over 10 years at 85°C
• TBD years at 25°C.

8ATmega128RFA1
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ATmega128RFA1
7 AVR CPU Core
7.1 Introduction
This section discusses the AVR core architecture in general. The main function of the
CPU core is to ensure correct program execution. The CPU must therefore be able toaccess memories, perform calculation, control peripherals, and handle interrupts.

7.2 Architectural Overview
Figure 7-1.Block Diagram of the AVR Architecture
Data Bus 8-bit

Flash
Program
MemoryProgram
Counter

Statusand Control

32 x 8GeneralPurposeRegistrers

Control Lines

Direct Addressing

Instruction
Decoder

Indirect Addressing

Instruction
RegisterInterrupt
Unit
SPI
Unit
Watchdog
Timer

ALU

AnalogComparator

I/O Module1

Data
SRAM

I/O Module 2

I/O Module n
EEPROM

I/O Lines

In order to maximize performance and parallelism, the AVR uses a Harvardarchitecture – with separate memories and buses for program and data. Instructions in
the program memory are executed with a single level pipelining. While one instruction is
being executed, the next instruction is pre-fetched from the program memory. This
concept enables instructions to be executed in every clock cycle. The program memory
is In-System Reprogrammable Flash memory.
9
8266A-MCU Wireless-12/09

The fast-access Register File contains 32 x 8-bit general purpose working registers witha single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU)
operation. In a typical ALU operation, two operands are output from the Register File,the operation is executed, and the result is stored back in the Register File – in one
clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for
Data Space addressing – enabling efficient address calculations. One of these address
pointers can also be used as an address pointer for look up tables in Flash program
memory. These added function registers are the 16-bit X-, Y-, and Z-register, describedlater in this section.
The ALU supports arithmetic and logic operations between registers or between a
constant and a register. Single register operations can also be executed in the ALU.
After an arithmetic operation, the Status Register is updated to reflect information about
the result of the operation.
Program flow is provided by conditional and unconditional jump and call instructions,able to directly address the whole address space. Most AVR instructions have a single
16-bit word format. Every program memory address contains a 16- or 32-bit instruction.
Program Flash memory space is divided in two sections, the Boot Program section and
the Application Program section. Both sections have dedicated Lock bits for write andread/write protection. The SPM instruction that writes into the Application Flash memory
section must reside in the Boot Program section.
During interrupts and subroutine calls, the return address Program Counter (PC) is
stored on the Stack. The Stack is effectively allocated in the general data SRAM, andconsequently the Stack size is only limited by the total SRAM size and the usage of the
SRAM. All user programs must initialize the SP in the Reset routine (before subroutines
or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/Ospace. The data SRAM can easily be accessed through the five different addressing
modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional
Global Interrupt Enable bit in the Status Register. All interrupts have a separate
Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordancewith their Interrupt Vector position. The lower the Interrupt Vector address, the higher
the priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control
Registers, SPI, and other I/O functions. The I/O Memory can be accessed directly, or as
the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition,
the ATmega128RFA1 has Extended I/O space from 0x60 - 0x1FF in SRAM where only
the ST/STS/STD and LD/LDS/LDD instructions can be used.

7.3 ALU – Arithmetic Logic Unit
The high-performance AVR ALU operates in direct connection with all the 32 general
purpose working registers. Within a single clock cycle, arithmetic operations between
general purpose registers or between a register and an immediate are executed. The
ALU operations are divided into three main categories – arithmetic, logical, and bit
functions. Some implementations of the architecture also provide a powerful multipliersupporting both signed/unsigned multiplication and fractional format. See the“Instruction Set” section for a detailed description.

10

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ATmega128RFA1
7.4 Status Register
The Status Register contains information about the result of the most recently executedarithmetic instruction. This information can be used for altering program flow in order toperform conditional operations. Note that the Status Register is updated after all ALU
operations, as specified in the Instruction Set Reference. This will in many cases
remove the need for using the dedicated compare instructions, resulting in faster andmore compact code. The Status Register is not automatically stored when entering aninterrupt routine and restored when returning from an interrupt. This must be handled bysoftware.
7.4.1 SREG – Status Register
Bit

7

6

5

4

3

2

1

0

$3F ($5F)

I

T

H

S

V

N

Z

C

Read/Write
Initial Value

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

SREG

• Bit 7 – I - Global Interrupt Enable
The global interrupt enable bit must be set (one) for the interrupts to be enabled. The
individual interrupt enable control is then performed in separate control registers. If the
global interrupt enable bit is cleared (zero), none of the interrupts are enabledindependent of the individual interrupt enable settings. The I-bit is cleared by hardware
after an interrupt has occurred, and is set by the RETI instruction to enable subsequentinterrupts.
• Bit 6 – T - Bit Copy Storage
The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T bit as sourceand destination for the operated bit. A bit from a register in the register file can becopied into T by the BST instruction, and a bit in T can be copied into a bit in a registerin the register file by the BLD instruction.
• Bit 5 – H - Half Carry Flag
The half carry flag H indicates a half carry in some arithmetic operations. See theInstruction Set Description for detailed information.
• Bit 4 – S - Sign Bit
The S-bit is always an exclusive or between the negative flag N and the two's
complement overflow flag V. See the Instruction Set Description for detailed
information.
• Bit 3 – V - Two's Complement Overflow Flag
The two's complement overflow flag V supports two's complement arithmetics. See theInstruction Set Description for detailed information.
• Bit 2 – N - Negative Flag
The negative flag N indicates a negative result after the different arithmetic and logic
operations. See the Instruction Set Description for detailed information.
• Bit 1 – Z - Zero Flag
The zero flag Z indicates a zero result after the different arithmetic and logic operations.
See the Instruction Set Description for detailed information.
• Bit 0 – C - Carry Flag
The carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction
Set Description for detailed information. Note that the status register is not automatically11
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stored when entering an interrupt routine and restored when returning from an interrupt
routine. This must be handled by software.

7.5 General Purpose Register FileThe Register File is optimized for the AVR Enhanced RISC instruction set. In order toachieve the required performance and flexibility, the following input/output schemes aresupported by the Register File:• One 8-bit output operand and one 8-bit result input• Two 8-bit output operands and one 8-bit result input• Two 8-bit output operands and one 16-bit result input• One 16-bit output operand and one 16-bit result input
Figure 7-1 below shows the structure of the 32 general purpose working registers in theCPU.
Figure 7-1. AVR CPU General Purpose Working Registers

Most of the instructions operating on the Register File have direct access to all
registers, and most of them are single cycle instructions.
As shown in Figure 7-1 above on page 12, each register is also assigned a data
memory address, mapping them directly into the first 32 locations of the user Data
Space. Although not being physically implemented as SRAM locations, this memoryorganization provides great flexibility in access of the registers, as the X-, Y- and Zpointer registers can be set to index any register in the file.
7.5.1 The X-register, Y-register, and Z-register
The registers R26...R31 have some added functions to their general purpose usage.
These registers are 16-bit address pointers for indirect addressing of the data space.
The three indirect address registers X, Y, and Z are defined as described in Figure 7-2
on page 13.

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ATmega128RFA1
Figure 7-2. The X-, Y-, Z-registers

In the different addressing modes these address registers have functions as fixed
displacement, automatic increment, and automatic decrement (see the instruction set
reference for details).

7.6 Stack PointerThe Stack is mainly used for storing temporary data, for storing local variables and forstoring return addresses after interrupts and subroutine calls. The Stack PointerRegister always points to the top of the Stack. Note that the Stack is implemented as
growing from higher memory locations to lower memory locations. This implies that a
Stack PUSH command decreases the Stack Pointer.
The Stack Pointer points to the data SRAM Stack area where the Subroutine andInterrupt Stacks are located. This Stack space in the data SRAM must be defined by
the program before any subroutine calls are executed or interrupts are enabled. The
Stack Pointer must be set to point above 0x0200. The initial value of the stack pointer isthe last address of the internal SRAM.
The Stack Pointer is decremented by one when data is pushed onto the Stack with the
PUSH instruction, and it is decremented by two when the return address is pushed onto
the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one
when data is popped from the Stack with the POP instruction, and it is incremented by
two when data is popped from the Stack with return from subroutine RET or return frominterrupt RETI.
When the FLASH memory exceeds 128Kbyte one additional cycle is required. In thiscase the Stack Pointer is decremented by three when the return address is pushed onto
the Stack with subroutine call or interrupt and is incremented by three when data ispopped from the Stack with return from subroutine RET or return from interrupt RETI.
7.6.1 SPH – Stack Pointer High
Bit

7

6

5

4

3

2

1

0

$3E ($5E)

SP15

SP14

SP13

SP12

SP11

SP10

SP9

SP8

Read/Write
Initial Value

RW
0

RW
0

RW
1

RW
0

RW
0

RW
0

RW
0

RW
1

SPH

The AVR Stack Pointer is implemented as two 8-bit registers SPL and SPH in the I/Ospace. The number of bits actually used is implementation dependent. Note that thedata space in some implementations of the AVR architecture is so small that only SPL
is needed. In this case, the SPH Register will not be present.
• Bit 7:0 – SP15:8 - Stack Pointer High Byte
13
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7.6.2 SPL – Stack Pointer Low
Bit

7

6

5

4

3

2

1

0

$3D ($5D)

SP7

SP6

SP5

SP4

SP3

SP2

SP1

SP0

Read/Write
Initial Value

RW
1

RW
1

RW
1

RW
1

RW
1

RW
1

RW
1

RW
1

SPL

The AVR Stack Pointer is implemented as two 8-bit registers SPL and SPH in the I/Ospace. The number of bits actually used is implementation dependent. Note that thedata space in some implementations of the AVR architecture is so small that only SPL
is needed. In this case, the SPH Register will not be present.
• Bit 7:0 – SP7:0 - Stack Pointer Low Byte

7.6.3 RAMPZ – Extended Z-pointer Register for ELPM/SPM
Bit

7

6

5

4

3

2

$3B ($5B)

Res5

Res4

Res3

Res2

Res1

Res0

Read/Write
Initial Value

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

1

0

RAMPZ1 RAMPZ0
RW
0

RAMPZ

RW
0

For ELPM/SPM instructions, the Z-pointer is a concatenation of RAMPZ, ZH, and ZL.
Note that LPM is not affected by the RAMPZ setting.
• Bit 7:2 – Res5:0 - Reserved
For compatibility with future devices, be sure to write these bits to zero.
• Bit 1:0 – RAMPZ1:0 - Extended Z-Pointer Value
These two bits represent the MSB's of the Z-Pointer.
Table 7-2 RAMPZ Register Bits
Register Bits

Value

RAMPZ1:0

0

Description
Default value of Z-pointer MSB's.

For ELPM/SPM instructions, the Z-pointer is a concatenation of RAMPZ, ZH, and ZL,
as shown in Figure 7-3 below. Note that LPM is not affected by the RAMPZ setting.
Figure 7-3. The Z-pointer used by ELPM and SPM

The actual number of bits is implementation dependent. Unused bits in an
implementation will always read as zero. For compatibility with future devices, be sureto write these bits to zero.

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ATmega128RFA1
7.7 Instruction Execution Timing
Figure 7-4. The Parallel Instruction Fetches and Instruction Executions
T1

T2

T3

T4

clkCPU
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch

Figure 7-5 below shows the internal timing concept for the Register File. In a single
clock cycle an ALU operation using two register operands is executed, and the result isstored back to the destination register.
Figure 7-5. Single Cycle ALU operation
T1

T2

T3

T4

clkCPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back

7.8 Reset and Interrupt Handling
The AVR provides several different interrupt sources. These interrupts and the separate
Reset Vector each have a separate program vector in the program memory space. Allinterrupts are assigned individual enable bits which must be written logic one together
with the Global Interrupt Enable bit in the Status Register in order to enable theinterrupt. Depending on the Program Counter value, interrupts may be automaticallydisabled when Boot Lock bits BLB02 or BLB12 are programmed. This feature improves
software security. See the section "Memory Programming" on page 464 for details.
The lowest addresses in the program memory space are by default defined as theReset and Interrupt Vectors. The complete list of vectors is shown in "Interrupts" onpage 211. The list also determines the priority levels of the different interrupts. The
lower the address the higher is the priority level. RESET has the highest priority, andnext is INT0 – the External Interrupt Request 0. The Interrupt Vectors can be moved tothe start of the Boot Flash section by setting the IVSEL bit in the MCU Control Register(MCUCR). Refer to "Interrupts" on page 211 for more information. The Reset Vector
can also be moved to the start of the Boot Flash section by programming the
BOOTRST Fuse, see "Memory Programming" on page 464.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts
are disabled. The user software can write logic one to the I-bit to enable nested
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interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit
is automatically set when a Return from Interrupt instruction – RETI – is executed.
There are basically two types of interrupts. The first type is triggered by an event thatsets the Interrupt Flag. For these interrupts, the Program Counter is vectored to theactual Interrupt Vector in order to execute the interrupt handling routine, and hardware
clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a
logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while
the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set andremembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if
one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared,
the corresponding Interrupt Flag(s) will be set and remembered until the Global
Interrupt Enable bit is set, and will then be executed by order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present.
These interrupts do not necessarily have Interrupt Flags. If the interrupt condition
disappears before the interrupt is enabled, the interrupt will not be triggered.
When the AVR exits from an interrupt, it will always return to the main program andexecute one more instruction before any pending interrupt is served.
Note that the Status Register is not automatically stored when entering an interrupt
routine, nor restored when returning from an interrupt routine. This must be handled bysoftware.
When using the CLI instruction to disable interrupts, the interrupts will be immediately
disabled. No interrupt will be executed after the CLI instruction, even if it occurs
simultaneously with the CLI instruction. The following example shows how this can beused to avoid interrupts during the timed EEPROM write sequence.

Assembly Code Example
in r16, SREG ; store SREG value
cli ; disable interrupts during timed sequencesbi EECR, EEMPE ; start EEPROM write
sbi EECR, EEPE
out SREG, r16 ; restore SREG value (I-bit)
C Code Example
char cSREG;cSREG = SREG; /* store SREG value *//* disable interrupts during timed sequence */__disable_interrupt();
EECR |= (1<<EEMPE); /* start EEPROM write */EECR |= (1<<EEPE);
SREG = cSREG; /* restore SREG value (I-bit) */When using the SEI instruction to enable interrupts, the instruction following SEI will be
executed before any pending interrupts, as shown in this example.

Assembly Code Example
sei ; set Global Interrupt Enable
sleep; enter sleep, waiting for interrupt

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ATmega128RFA1Assembly Code Example; note: will enter sleep before any pending; interrupt(s)C Code Example__enable_interrupt(); /* set Global Interrupt Enable */__sleep(); /* enter sleep, waiting for interrupt *//* note: will enter sleep before any pending interrupt(s) */7.8.1 Interrupt Response TimeThe interrupt execution response for all the enabled AVR interrupts is five clock cycles
minimum. After five clock cycles the program vector address for the actual interrupt
handling routine is executed. During these five clock cycle period, the Program Counter
is pushed onto the Stack. The vector is normally a jump to the interrupt routine, and thisjump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle
instruction, this instruction is completed before the interrupt is served. If an interrupt
occurs when the MCU is in sleep mode, the interrupt execution response time isincreased by five clock cycles. This increase comes in addition to the start-up time fromthe selected sleep mode.
A return from an interrupt handling routine takes five clock cycles. During these fiveclock cycles, the Program Counter (three bytes) is popped back from the Stack, theStack Pointer is incremented by three, and the I-bit in SREG is set.

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8 AVR Memories
This section describes the different memories in the ATmega128RFA1. The AVR
architecture has two main memory spaces, the Data Memory and the Program Memory
space. In addition, the ATmega128RFA1 features an EEPROM Memory for data
storage. All three memory spaces are linear and regular.

8.1 In-System Reprogrammable Flash Program Memory
The ATmega128RFA1 contains 128K bytes On-chip In-System Reprogrammable Flashmemory for program storage, see Figure 8-6 below. Since all AVR instructions are 16 or
32 bits wide, the Flash is 16 bit wide. For software security, the Flash Program memory
space is divided into two sections, Boot Program section and Application Program
section.
The Flash memory has an endurance of at least 2000 write/erase cycles. The
ATmega128RFA1 Program Counter (PC) is 16 bits wide, thus addressing the required
program memory locations. The operation of Boot Program section and associatedBoot Lock bits for software protection are described in detail in "Boot Loader Support –Read-While-Write Self-Programming" on page 450. "Memory Programming" on page
464 contains a detailed description on Flash data serial downloading using the SPI pinsor the JTAG interface.
Constant tables can be allocated within the entire program memory address space (seethe LPM – Load Program Memory instruction description and ELPM – Extended Load
Program Memory instruction description).
Timing diagrams for instruction fetch and execution are presented in "Instruction
Execution Timing" on page 15.
Figure 8-6. Program Flash Memory Map
Program Memory
Application Flash Section$0000

Boot Flash Section

8.2 SRAM Data Memory
Figure 8-7 on page 19 shows how the ATmega128RFA1 SRAM Memory is organized.
The ATmega128RFA1 is a complex microcontroller with more peripheral units than canbe supported within the 64 location reserved in the Opcode for the IN and OUT
instructions. For the Extended I/O space from $060 – $1FF in SRAM, only the
ST/STS/STD and LD/LDS/LDD instructions can be used.
The first Data Memory locations address both the Register File, the I/O Memory,
Extended I/O Memory, and the internal data SRAM. The first 32 locations address theRegister file, the next 64 location the standard I/O Memory, then 416 locations ofExtended I/O memory and the following locations address the internal data SRAM.

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ATmega128RFA1
The five different addressing modes for the data memory cover: Direct, Indirect with
Displacement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment.
In the Register file, registers R26 to R31 feature the indirect addressing pointerregisters.
The direct addressing reaches the entire data space.
The Indirect with Displacement mode reaches 63 address locations from the baseaddress given by the Y- or Z-register.
When using register indirect addressing modes with automatic pre-decrement and postincrement, the address registers X, Y, and Z are decremented or incremented.
The 32 general purpose working registers, 64 I/O registers, and the internal data SRAM
in the ATmega128RFA1 are all accessible through all these addressing modes. The
Register File is described in "General Purpose Register File" on page 12.
Figure 8-7. Data Memory Map

Data Memory
32 Registers
64 I/O Registers
416 Ext I/O Reg.

$0000 - $001F$0020 - $005F$0060 - $01FF$0200

Internal SRAM
(16K x 8)
$41FF

$FFFF
8.2.1 Data Memory Access Times
This section describes the general access timing concepts for internal memory access.
Access to the internal data SRAM is performed in two clkCPU cycles as described in
Figure 8-8 on page 20.

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Figure 8-8. On-Chip Data SRAM Access Cycles
T1

T2

Compute Address

Address valid

T3

clkCPU
Address

Write

Data
WR

Read

Data
RD

Memory Access Instruction

Next Instruction

8.3 EEPROM Data Memory
The ATmega128RFA1 contains 4Kbyte of data EEPROM memory. It is organized as aseparate data space, in which single bytes can be read and written. The EEPROM hasan endurance of at least 2000 write/erase cycles. The access between the EEPROM
and the CPU is described in the following, specifying the EEPROM Address Registers,
the EEPROM Data Register, and the EEPROM Control Register.
For a detailed description of SPI, JTAG and Parallel data downloading to the EEPROM,
see "Serial Downloading" on page 477, "Programming via the JTAG Interface" on page481, and "Programming the EEPROM" on page 491 respectively.
8.3.1 EEPROM Read Write Access
The EEPROM Access Registers are accessible in the I/O space, see "EEPROM
Register Description" on page 23.
The write access time for the EEPROM is given in Table 8-3 below. A self-timing
function, however, lets the user software detect when the next byte can be written. If theuser code contains instructions that write the EEPROM, some precautions must be
taken. In heavily filtered power supplies, DVDD is likely to rise or fall slowly on powerup/down. This causes the device for some period of time to run at a voltage lower thanspecified as minimum for the clock frequency used. See "Preventing EEPROM
Corruption" on page 22 for details on how to avoid problems in these situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be
followed. See the description of the EEPROM Control Register for details on this,"EEPROM Register Description" on page 23.
When the EEPROM is read, the CPU is halted for four clock cycles before the next
instruction is executed. When the EEPROM is written, the CPU is halted for two clock
cycles before the next instruction is executed.
The calibrated Oscillator is used to time the EEPROM accesses. The following tablelists the typical programming time for EEPROM access from the CPU.
Table 8-3. EEPROM Programming Time
Symbol20

Typical Programming time

EEPROM write (from CPU)

4ms

EEPROM erase (from CPU)

8ms

ATmega128RFA1
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ATmega128RFA1
The following code examples show one assembly and one C function for writing to the
EEPROM. The examples assume that interrupts are controlled (e.g. by disabling
interrupts globally) so that no interrupts will occur during execution of these functions.
The examples also assume that no Flash Boot Loader is present in the software. If suchcode is present, the EEPROM write function must also wait for any ongoing SPM
command to finish.

Assembly Code Example
EEPROM_write:; Wait for completion of previous write
sbic EECR,EEPE
rjmp EEPROM_write; Set up address (r18:r17) in address registerout EEARH, r18
out EEARL, r17; Write data (r16) to Data Registerout EEDR,r16; Write logical one to EEMPE
sbi EECR,EEMPE; Start eeprom write by setting EEPE
sbi EECR,EEPE
ret
C Code Example
void EEPROM_write(unsigned int uiAddress, unsigned char ucData){/* Wait for completion of previous write */while(EECR & (1<<EEPE));/* Set up address and Data Registers */EEAR = uiAddress;
EEDR = ucData;/* Write logical one to EEMPE */EECR |= (1<<EEMPE);/* Start eeprom write by setting EEPE */EECR |= (1<<EEPE);}

The next code examples show assembly and C functions for reading the EEPROM. The
examples assume that interrupts are controlled so that no interrupts will occur duringexecution of these functions.

Assembly Code Example
EEPROM_read:; Wait for completion of previous write

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Assembly Code Example
sbic EECR,EEPE
rjcmp EEPROM_read; Set up address (r18:r17) in address registerout EEARH, r18
out EEARL, r17; Start eeprom read by writing EERE
sbi EECR,EERE; Read data from Data Registerin r16,EEDR
ret
C Code Example
unsigned char EEPROM_read(unsigned int uiAddress){/* Wait for completion of previous write */while(EECR & (1<<EEPE));/* Set up address register */EEAR = uiAddress;/* Start eeprom read by writing EERE */EECR |= (1<<EERE);/* Return data from Data Register */return EEDR;}

8.3.2 Preventing EEPROM Corruption
During periods of low DEVDD, the EEPROM data can be corrupted because the supply
voltage is too low for the CPU and the EEPROM to operate properly. These issues are
the same as for board level systems using EEPROM, and the same design solutions
should be applied.
An EEPROM data corruption can be caused by two situations when the voltage is toolow. First, a regular write sequence to the EEPROM requires a minimum voltage tooperate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the
supply voltage is too low.
EEPROM data corruption can easily be avoided by following thisrecommendation:

designKeep the AVR RESET active (low) during periods of insufficient power supply voltage.
This can be done by enabling the internal Brown-out Detector (BOD). If the detectionlevel of the internal BOD does not match the needed detection level, an external low
VCC reset Protection circuit can be used. If a reset occurs while a write operation is inprogress, the write operation will be completed provided that the power supply voltage
is sufficient.

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ATmega128RFA1
8.4 EEPROM Register Description
8.4.1 EEARH – EEPROM Address Register High Byte
Bit

7

6

5

4

$22 ($42)

Res3

Res2

Res1

Res0

Read/Write
Initial Value

R
0

R
0

R
0

R
0

3

2

EEAR11 EEAR10
RW
X

RW
X

1

0

EEAR9

EEAR8

RW
X

RW
X

EEARH

The EEPROM Address Registers EEARH and EEARL specify the EEPROM address inthe 4K bytes EEPROM space. The EEPROM data bytes are addressed linearly
between 0 and 4096. The initial value of EEAR is undefined. A proper value must be
written before the EEPROM may be accessed.
• Bit 7:4 – Res3:0 - Reserved• Bit 3:0 – EEAR11:8 - EEPROM Address

8.4.2 EEARL – EEPROM Address Register Low Byte
Bit

7

6

5

4

3

2

1

0

$21 ($41)

EEAR7

EEAR6

EEAR5

EEAR4

EEAR3

EEAR2

EEAR1

EEAR0

Read/Write
Initial Value

RW
X

RW
X

RW
X

RW
X

RW
X

RW
X

RW
X

RW
X

EEARL

The EEPROM Address Registers EEARH and EEARL specify the EEPROM address inthe 4K bytes EEPROM space. The EEPROM data bytes are addressed linearly
between 0 and 4096. The initial value of EEAR is undefined. A proper value must be
written before the EEPROM may be accessed.
• Bit 7:0 – EEAR7:0 - EEPROM Address

8.4.3 EEDR – EEPROM Data Register
Bit

7

6

5

$20 ($40)
Read/Write
Initial Value

4

3

2

1

0

EEDR7:0
RW
0

RW
0

RW
0

RW
0

RW
0

EEDR
RW
0

RW
0

RW
0

For the EEPROM write operation, the EEDR Register contains the data to be written to
the EEPROM in the address given by the EEAR Register. For the EEPROM read
operation, the EEDR contains the data read out from the EEPROM at the address given
by EEAR.
• Bit 7:0 – EEDR7:0 - EEPROM Data

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8.4.4 EECR – EEPROM Control Register
Bit

7

6

5

4

3

2

1

0

$1F ($3F)

Res1

Res0

EEPM1

EEPM0

EERIE

EEMPE

EEPE

EERE

Read/Write
Initial Value

R
0

R
0

RW
X

RW
X

RW
0

RW
0

RW
X

RW
0

EECR

• Bit 7:6 – Res1:0 - Reserved• Bit 5:4 – EEPM1:0 - EEPROM Programming Mode
The EEPROM Programming mode bit setting defines which programming action will be
triggered when writing EEPE. It is possible to program data in one atomic operation(erase the old value and program the new value) or to split the Erase and Write
operations in two different operations. The Programming times for the different modes
are shown in the following table. While EEPE is set, any write to EEPM1:0 will beignored. During reset, the EEPM1:0 bits will be reset to 0 unless the EEPROM is busy
programming.
Table 8-4 EEPM Register Bits
Register Bits

Value

Description

EEPM1:00x00

Erase and Write in one operation (Atomic
Operation)

0x01

Erase only

0x02

Write only

0x03

Reserved for future use• Bit 3 – EERIE - EEPROM Ready Interrupt Enable
Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set.
Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates aconstant interrupt when EEPE is cleared.
• Bit 2 – EEMPE - EEPROM Master Write Enable
The EEMPE bit determines whether setting EEPE to one causes the EEPROM to be
written. When EEMPE is set, setting EEPE within four clock cycles will write data to the
EEPROM at the selected address If EEMPE is zero, setting EEPE will have no effect.
When EEMPE has been written to one by software, hardware clears the bit to zero after
four clock cycles. See the description of the EEPE bit for an EEPROM write procedure.
• Bit 1 – EEPE - EEPROM Programming Enable
The EEPROM Write Enable Signal EEPE is the write strobe to the EEPROM. Whenaddress and data are correctly set up, the EEPE bit must be written to one to write thevalue into the EEPROM. The EEMPE bit must be written to one before a logical one iswritten to EEPE, otherwise no EEPROM write takes place. The following procedure
should be adopted when writing the EEPROM (the order of steps 3 and 4 is notessential):
1. Wait until EEPE becomes zero.
2. Wait until SPMEN in SPMCSR becomes zero.
3. Write new EEPROM address to EEAR (optional).
4. Write new EEPROM data to EEDR (optional).
5. Write a logical one to the EEMPE bit while writing a zero to EEPE in EECR.
6. Within four clock cycles after setting EEMPE, write a logical one to EEPE.

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ATmega128RFA1The EEPROM can not be programmed during a CPU write to the Flash memory. The
software must check that the Flash programming is completed before initiating a new
EEPROM write. Step 2 is only relevant if the software contains a Boot Loader allowing
the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2
can be omitted.
Caution: an interrupt between step 5 and step 6 will make the write cycle fail, since the
EEPROM Master Write Enable will time-out. If an interrupt routine accessing the
EEPROM is interrupting another EEPROM access, the EEAR or EEDR Register will be
modified, causing the interrupted EEPROM access to fail. It is recommended to have
the Global Interrupt Flag cleared during all steps to avoid these problems.
When the write access time has elapsed, the EEPE bit is cleared by hardware. The
user software can poll this bit and wait for a zero before writing the next byte. When
EEPE has been set, the CPU is halted for two cycles before the next instruction is
executed.
• Bit 0 – EERE - EEPROM Read Enable
The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When thecorrect address is set up in the EEAR Register, the EERE bit must be written to a logic
one to trigger the EEPROM read. The EEPROM read access takes one instruction andthe requested data is available immediately. When the EEPROM is read, the CPU ishalted for four cycles before the next instruction is executed. The user should poll the
EEPE bit before starting the read operation. If a write operation is in progress, it isneither possible to read the EEPROM nor to change the EEAR Register.

8.5 I/O Memory
The Input/Output (I/O) space definition of the ATmega128RFA1 is shown in "Register
Summary" on page 496.
All ATmega128RFA1 I/Os and peripherals are placed in the I/O space. All I/O locations
may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data
between the 32 general purpose working registers and the I/O space. I/O Registers
within the address range 0x00 – 0x1F are directly bit-accessible using the SBI and CBIinstructions. In these registers, the value of single bits can be checked by using the
SBIS and SBIC instructions. Refer to the AVR instruction set for more details. Whenusing the I/O specific commands IN and OUT, the I/O addresses 0x00 – 0x3F must be
used. When addressing I/O Registers as data space using LD and ST instructions,
0x20 must be added to these addresses. The ATmega128RFA1 is a complex
microcontroller with more peripheral units than can be supported within the 64 location
reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from
0x60 – 0x1FF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can beused.
For compatibility with future devices, reserved bits may not be modified. Reserved
registers and I/O memory addresses should never be written.
Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike
most other AVRs, the CBI and SBI instructions will only operate on the specified bit,and can therefore be used on registers containing such Status Flags. The CBI and SBI
instructions work with registers 0x00 to 0x1F only.
The control registers of I/O and peripherals are explained in later sections.

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8.6 General Purpose I/O Registers
The ATmega128RFA1 contains three General Purpose I/O Registers. These registers
can be used for storing any information, and they are particularly useful for storing
global variables and Status Flags. General Purpose I/O Registers within the address
range 0x00 – 0x1F are directly bit-accessible using the SBI, CBI, SBIS, and SBIC
instructions.
8.6.1 GPIOR0 – General Purpose IO Register 0
Bit

7

6

5

$1E ($3E)
Read/Write
Initial Value

4

3

2

1

0

GPIOR07:00
RW
0

RW
0

RW
0

RW
0

RW
0

GPIOR0
RW
0

RW
0

RW
0

The three General Purpose I/O Registers can be used for storing any information.
• Bit 7:0 – GPIOR07:00 - General Purpose I/O Register 0 Value

8.6.2 GPIOR1 – General Purpose IO Register 1
Bit

7

6

5

4

RW
0

RW
0

RW
0

RW
0

$2A ($4A)
Read/Write
Initial Value

3

2

1

0

RW
0

RW
0

RW
0

GPIOR17:10
RW
0

GPIOR1

The three General Purpose I/O Registers can be used for storing any information.
• Bit 7:0 – GPIOR17:10 - General Purpose I/O Register 1 Value

8.6.3 GPIOR2 – General Purpose I/O Register 2
Bit

7

6

5

$2B ($4B)
Read/Write
Initial Value

4

3

2

1

0

GPIOR27:20
RW
0

RW
0

RW
0

RW
0

RW
0

GPIOR2
RW
0

RW
0

RW
0

The three General Purpose I/O Registers can be used for storing any information.
• Bit 7:0 – GPIOR27:20 - General Purpose I/O Register 2 Value

8.7 Other Port Registers
The inherited control registers of missing ports located in the I/O space are kept in the
ATmega128RFA1. They can be used as general purpose I/O registers for storing any
information. Registers placed in the address range 0x00 – 0x1F are directly bitaccessible using the SBI, CBI, SBIS and SBIC instructions.

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ATmega128RFA1
8.7.1 PORTA – Port A Data Register
Bit

7

6

5

4

$02 ($22)
Read/Write
Initial Value

3

2

1

0

PORTA7:0
RW
0

RW
0

RW
0

RW
0

PORTA

RW
0

RW
0

RW
0

RW
0

The PORTA register can be used as a General Purpose I/O Register for storing any
information.
• Bit 7:0 – PORTA7:0 - Port A Data Register Value

8.7.2 DDRA – Port A Data Direction Register
Bit

7

6

5

4

3

2

1

0

$01 ($21)

DDA7

DDA6

DDA5

DDA4

DDA3

DDA2

DDA1

DDA0

Read/Write
Initial Value

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

DDRA

The DDRA register can be used as a General Purpose I/O Register for storing any
information.
• Bit 7:0 – DDA7:0 - Port A Data Direction Register Value

8.7.3 PINA – Port A Input Pins Address
Bit

7

6

5

4

$00 ($20)
Read/Write
Initial Value

3

2

1

0

PINA7:0
RW
0

RW
0

RW
0

RW
0

RW
0

PINA
RW
0

RW
0

RW
0

The PINA register is reserved for interal use and cannot be used as a General Purpose
I/O Register.
• Bit 7:0 – PINA7:0 - Port A Input Pins

8.7.4 PORTC – Port C Data Register
Bit

7

6

5

4

RW
0

RW
0

RW
0

RW
0

$08 ($28)
Read/Write
Initial Value

3

2

1

0

RW
0

RW
0

RW
0

PORTC7:0
RW
0

PORTC

The PORTC register can be used as a General Purpose I/O Register for storing any
information.
• Bit 7:0 – PORTC7:0 - Port C Data Register Value

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8.7.5 DDRC – Port C Data Direction Register
Bit

7

6

5

4

3

2

1

0

$07 ($27)

DDC7

DDC6

DDC5

DDC4

DDC3

DDC2

DDC1

DDC0

Read/Write
Initial Value

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

DDRC

The DDRC register can be used as a General Purpose I/O Register for storing any
information.
• Bit 7:0 – DDC7:0 - Port C Data Direction Register Value

8.7.6 PINC – Port C Input Pins Address
Bit

7

6

5

4

R
0

R
0

R
0

R
0

$06 ($26)
Read/Write
Initial Value

3

2

1

0

R
0

R
0

R
0

PINC7:0R
0

PINC

The PINC register is reserved for interal use and cannot be used as a General Purpose
I/O Register.
• Bit 7:0 – PINC7:0 - Port C Input Pins

28

ATmega128RFA1
8266A-MCU Wireless-12/09

ATmega128RFA1
9 Low-Power 2.4 GHz Transceiver
9.1 Features• High performance RF-CMOS 2.4 GHz radio transceiver targeted for IEEE
802.15.4™, ZigBee™, IPv6 / 6LoWPAN, RF4CE, SP100, WirelessHART™ andISM applications• Outstanding link budget (103.5 dB):o

Receiver sensitivity -100 dBmoProgrammable output power from -17 dBm up to +3.5 dBm• Ultra-low current consumption:o

TRX_OFF= 0.4 mAo

RX_ON

= 12.5 mAo

BUSY_TX= 14.5 mA (at max. transmit power of +3.5 dBm)

• Optimized for low BoM cost and ease of production:o

Few external components necessary (crystal, capacitors andantenna)o

Excellent ESD robustness• Easy to use interface:oRegisters and frame buffer access from softwareoDedicated radio transceiver interrupts• Radio transceiver features:o

128 byte FIFO (SRAM) for data bufferingoIntegrated RX/TX switchoFully integrated, fast settling PLL to support frequency hoppingoBattery monitoroFast wake-up time < 0.25 ms• Special IEEE 802.15.4 2006 hardware support:o

FCS computation and clear channel assessment (CCA)o

RSSI measurement, energy detection and link quality indication• MAC hardware accelerator:oAutomated acknowledgement, CSMA-CA and frame
retransmissionoAutomatic address filteringoAutomated FCS check• Extended Feature Set Hardware Support:o

AES 128 bit hardware acceleratoro

RX/TX indication (external RF front-end control)oRX antenna diversityoSupported PSDU data rates: 250 kb/s, 500 kb/s, 1 Mb/s and 2 Mb/soTrue random number generation for security applications• Compliant to IEEE 802.15.4-2006, IEEE 802.15.4-2003 and RF4CE• Compliant to EN 300 328/440, FCC-CFR-47 Part 15, ARIB STD-66, RSS-210

29
8266A-MCU Wireless-12/09

The ATmega128RFA1 features a low-power 2.4 GHz radio transceiver designed forindustrial and consumer ZigBee/IEEE 802.15.4, 6LoWPAN, RF4CE and high data rate
2.4 GHz ISM band applications. The radio transceiver is a true peripheral block of the
AVR microcontroller. All RF-critical components except the antenna, crystal and decoupling capacitors are integrated on-chip. Therefore, the ATmega128RFA1 isparticularly suitable for applications like:• 2.4 GHz IEEE 802.15.4 and ZigBee systems• 6LoWPAN and RF4CE systems• Wireless sensor networks• Industrial control, sensing and automation (SP100, WirelessHART)• Residential and commercial automation• Health care
• Consumer electronics• PC peripherals

9.2 General Circuit Description®

This radio transceiver is part of a system-on-chip solution with an AVR microcontroller.
It comprises a complex peripheral component containing the analog radio, digitalmodulation and demodulation including time and frequency synchronization and data
buffering. The number of external components for the transceiver operation isminimized such that only the antenna, the crystal and decoupling capacitors are
required. The bidirectional differential antenna pins (RFP, RFN) are used fortransmission and reception, thus no external antenna switch is needed.
The ATmega128RFA1 block diagram is shown in Figure 9-9 below.

ext. PA and Power
Control

DIG3/4

PA

XTAL2

XTAL1

Figure 9-9. Transceiver Block Diagram

XOSC

PLL

AVREG

TX Data

Configuration Registers

TX BBP

Data

DVREG
µC
Interface

RFP
FTN, BATMON

Frame
BufferInterrupts
Address
Control

RFN
LNA

AD
DIG1/2

PPF

BPF

RX
ADC

AGC

RSSI

RX BBP

AES

Control Logic

Antenna Diversity

Analog Domain

30

Limiter

Digital Domain

ATmega128RFA1
8266A-MCU Wireless-12/09

ATmega128RFA1
The received RF signal at pins RFN and RFP is differentially fed through the low-noise
amplifier (LNA) to the RF filter (PPF) to generate a complex signal, driving the
integrated channel filter (BPF). The limiting amplifier provides sufficient gain to drive thesucceeding analog-to-digital converter (RX ADC) and generates a digital RSSI signal.
The RX ADC output signal is sampled by the digital base band receiver (RX BBP).
The transmit modulation scheme is offset-QPSK (O-QPSK) with half-sine pulse shaping
and 32-length block coding (spreading) according to [1] on page 100 and [2] on page100. The modulation signal is generated in the digital transmitter (TX BBP) and applied
to the fractional-N frequency synthesis (PLL), to ensure the coherent phase modulation
required for demodulation of O-QPSK signals. The frequency-modulated signal is fed tothe power amplifier (PA).
A differential pin pair DIG3/DIG4 can be enabled to control an external RF front-end.
The two on-chip low-dropout voltage regulators (A|DVREG) provide the analog anddigital 1.8V supply.
An internal 128-byte RAM for RX and TX (Frame Buffer) buffers the data to betransmitted or received.
The configuration of the reading and writing of the Frame Buffer is controlled via themicrocontroller interface.
The transceiver further contains comprehensive hardware-MAC support (Extended
Operating Mode) and a security engine (AES) to improve the overall system power
efficiency and timing. The 128-bit AES engine can be accessed in parallel to all PHY
operational transactions and states using the microcontroller interface, except duringtransceiver power down state.
For applications not necessarily targeting IEEE 802.15.4 compliant networks, the radiotransceiver also supports alternative data rates up to 2 Mb/s.
For long-range applications or to improve the reliability of an RF connection the RF
performance can further be improved by using an external RF front-end or Antenna
Diversity. Both operation modes are supported by the radio transceiver with dedicatedcontrol pins without the interaction of the microcontroller.
Additional features of the Extended Feature Set, see section "Radio Transceiver
Extended Feature Set" on page 85, are provided to simplify the interaction between
radio transceiver and microcontroller.

9.3 Transceiver to Microcontroller Interface
This section describes the internal Interface between the transceiver module and themicrocontroller. Unlike all other AVR I/O modules, the transceiver module can operate
asynchronously to the controller. The transceiver requires an accurate 16MHz crystal
clock for operation, but the controller can run at any frequency within its operating limits.
9.3.1 Transceiver Configuration and Data Access9.3.1.1 Register Access
All transceiver registers are mapped into I/O space of the controller. Due to theasynchronous interface a register access can take up to three transceiver clock cycles.
Depending on the controller clock speed, program execution wait cycles are generated.
That means if the controller runs with about 16MHz or faster, at least three wait cycles
are generated, but if the controller runs with about 4MHz, no wait cycles are inserted. A

31
8266A-MCU Wireless-12/09

register access is only possible, if the transceiver clock is available. Therefore thetransceiver must be enabled (PRR1 Register) and not in SLEEP state.
9.3.1.2 Frame Buffer Access
The 128-byte Frame Buffer can hold the PHY service data unit (PSDU) data of one
IEEE 802.15.4 compliant RX or one TX frame of maximum length at a time. A detailed
description of the Frame Buffer can be found in section "Frame Buffer" on page 77. An
introduction to the IEEE 802.15.4 frame format can be found in section "Introduction –IEEE 802.15.4-2006 Frame Format" on page 61.
The Frame Buffer is located within the controller I/O address space above of thetransceiver register set. The first byte of the Frame Buffer can be accessed with thesymbolical address TRXFBST and the last byte can be accessed with the symbolicaladdress TRXFBEND. Random access to single frame bytes is possible with “TRXFBST+ byte index” or “TRXFBEND – byte index”. In contrast to the transceiver register
access, the Frame Buffer allows single cycle read/write operations for all controller
clock speeds.
The content of the Frame Buffer is only overwritten by a new received frame or a Frame
Buffer write access.
The Frame Buffer usage is different between received and transmitted frames.
Therefore it is not possible to retransmit a received frame without modifying the frame
buffer.
On received frames, the frame length byte is not stored in the Frame Buffer, but can beaccessed over the TST_FRAME_LENGTH register. During frame receive, the Link
Quality Indication (LQI) value (refer to "Link Quality Indication (LQI)" on page 72 ) isappended to the frame data in the Frame Buffer.
For frame transmission, the first byte of the Frame Buffer must contain the frame length
information followed by the frame data. The TST_FRAME_LENGTH register does notneed to be written in this case.
A detailed description of the Frame Buffer usage for receive and transmit frames can befound in Figure 9-31 on page 78.
Notes:
1. The Frame Buffer is shared between RX and TX; therefore, the frame data are overwritten by
new incoming frames. If the TX frame data are to be retransmitted, it must be ensured that noframe was received in the meanwhile.
2. To avoid overwriting during receive, Dynamic Frame Buffer Protection can be enabled. For
details about this feature refer to section "Dynamic Frame Buffer Protection" on page 91.
3. It is not possible to retransmit received frames without inserting the frame length information at
the beginning of the Frame Buffer. That requires a complete read out of the received frame
and rewriting the modified frame to the Frame Buffer.
4. For exceptions, e.g. receiving acknowledgement frames in Extended Operating Mode
(TX_ARET) refer to section "TX_ARET_ON – Transmit with Automatic Retry and CSMA-CA
Retry" on page 57.

9.3.1.3 Transceiver Pin Register TRXPRThe Transceiver Pin Register TRXPR is located in the Controller clock domain and isaccessible even if the transceiver is in sleep state. This register provides access to thepin functionality, known from the RF231 devices (two chip solution).
The register (TRXRST) can be used to reset the transceiver without resetting thecontroller. After the reset bit was set, it is cleared immediately.

32

ATmega128RFA1
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ATmega128RFA1
A second configuration bit (SLPTR) is used to control frame transmission or sleep andwakeup of the transceiver. This bit is not cleared automatically.
The function of the SLPTR bit relates to the current state of the transceiver module andis summarized in Table 9-1 below. The radio transceiver states are explained in detail in
section "Operating Modes" on page 35.
Table 9-1. SLPTR Multi-functional Configuration bit
Transceiver Status

Function

SLPTR Bit

Description

PLL_ONTX start“0”  “1”Starts frame transmission

TX_ARET_ON

TX start“0”  “1”Starts TX_ARET transaction

TRX_OFFSleep“0”  “1”Takes the radio transceiver into SLEEP state

SLEEP

Wakeup“1”  “0”Takes the radio transceiver back into TRX_OFF state;

In states PLL_ON and TX_ARET_ON, bit SLPTR is used to initiate a TX transaction.
Here bit SLPTR is sensitive on the transition from “0” to “1” only. The bit should becleared before the frame transmission is finished.
After initiating a state change by a “0” to “1” transition at bit SLPTR in radio transceiverstates TRX_OFF, RX_ON or RX_AACK_ON, the radio transceiver remains in the newstate as long as the bit is logical “1” and returns to the preceding state if the bit is set to“0”.
SLEEP state
The SLEEP state is used when radio transceiver functionality is not required, and thus
the receiver module can be powered down to reduce the overall power consumption.
When the radio transceiver is in TRX_OFF state the microcontroller forces thetransceiver to SLEEP by setting SLPTR = “1”. The transceiver awakes when the
microcontroller releases bit SLPTR.
9.3.2 Interrupt Logic
9.3.2.1 Overview
The transceiver module differentiates between eight interrupt events. Internally all
pending interrupt are stored in a separate bit of the interrupt status register(IRQ_STATUS). Each interrupt is enabled by setting the corresponding bit in theinterrupt mask register (IRQ_MASK). If an IRQ is enabled an interrupt service routine
must be defined to handle the IRQ. A pending IRQ is cleared automatically if anInterrupt service routine is called. It is also possible to handle IRQs manually by polling
the IRQ_STATUS register. If an IRQ occurred, the appropriate IRQ_STATUS register
bit is set. The IRQ can be cleared by writing ‘1’ to the register bit. It is recommended toclear the corresponding status bit before enabling an interrupt.
Interrupts are not cleared automatically when the event that caused them vanishes.
More information about interrupt handling by the controller can be found in section"Interrupts" on page 211.
The supported interrupts for the Basic Operating Mode are summarized in Table 9-2 onpage 34.

33
8266A-MCU Wireless-12/09

Table 9-2. Interrupt Description in Basic Operating Mode
IRQ Vector
Number/(1)
Priority

IRQ Name

Description

64

TRX24_AWAKE

Indicates radio transceiver reached TRX_OFF
state RESET, or SLEEP states"TRX_OFF – Clock State" on page 36

63

TRX24_TX_END

Indicates the completion of a frametransmission"Frame Transmit Procedure" on page 84

62

TRX24_XAH_AMI

Indicates address matching

61

TRX24_CCA_ED_DONE

Indicates the end of a CCA or ED
measurement

60

TRX24_RX_END

Indicates the completion of a frame reception"Frame Transmit Procedure" on page 84

59

TRX24_RX_START

Indicates the start of a PSDU reception. The
TRX_STATE changes to BUSY_RX, the PHR
is ready to be read from Frame Buffer"Frame Receive Procedure" on page 84

58

TRX24_PLL_UNLOCK

Indicates PLL unlock. If the radio transceiveris in BUSY_TX / BUSY_TX_ARET state, thePA is turned off immediately"Interrupt Handling" on page 83

57

TRX24_PLL_LOCK

Indicates PLL lock"Interrupt Handling" on page 83

Note:

Section"Frame Filtering" on page 54"Energy Detection (ED)" on page 68

1. The lowest IRQ Number has the highest priority.

During startup from SLEEP or RESET, the radio transceiver issues an TRX24_AWAKE
interrupt when it enters state TRX_OFF.
If the microcontroller initiates an energy-detect (ED) or clear-channel-assessment(CCA) measurement, the completion of the measurement is indicated by interrupt
TRX24_CCA_ED_DONE, refer to sections "Energy Detection (ED)" on page 68 and"Clear Channel Assessment (CCA)" on page 70 for details.
After RESET all interrupts are disabled. During radio transceiver initialization it isrecommended to enable AWAKE to be notified once the TRX_OFF state is entered.
Note that the TRX24_AWAKE interrupt can usually not be seen when the transceiver
enters TRX_OFF state after RESET, because register IRQ_MASK is reset to mask allinterrupts. In this case, state TRX_OFF is normally entered before the microcontroller
could modify the register.
The interrupt handling in Extended Operating Mode is described in section "Interrupt
Handling" on page 59.
9.3.3 Radio Transceiver Identification
The ATmega128RFA1 Transceiver module can be identified by four registers(PART_NUM, VERSION_NUM, MAN_ID_0, MAN_ID_1). One register contains aunique part number and one register the corresponding version number. Two additional
registers contain the JTAG manufacture ID. The transceiver identification registers areprovided for compatibility to the transceiver only device.
A unique device identification is also possible with the three AVR signature bytes. For
details about accessing this information refer to "Signature Bytes" on page 466.

34

ATmega128RFA1
8266A-MCU Wireless-12/09

ATmega128RFA1
9.4 Operating Modes
9.4.1 Basic Operating Mode
This section summarizes all states to provide the basic functionality of the 2.4GHz radiotransceiver, such as receiving and transmitting frames, the power up sequence andradio transceiver sleep. The Basic Operating Mode is designed for IEEE 802.15.4 andISM applications; the corresponding radio transceiver states are shown in Figure 9-12
below.
Figure 9-12. Basic Operating Mode State Diagram (for timing refer to Table 9-3 on page 42)
SLEEP(S le e p S ta te )=0

XOSC=OFFFO RCE_TRX_O FF

RESET

FF

X
_O

TR
X
_O

R

RX_O N

FF

8

N
_O
LL

N

P

5
_O
X

F ra m e
End

7

TR

B U SY_R X

TRXRST = 0

X O S C =O N

6

(R e c e iv e S ta te )13

(C lo c k S ta te )(a ll s ta te s e x c e p t S L E E P )SHR
D e te c te d=

TR X_O FF

12

TRXRST = 1

S
LP
TR

2

(fro m a ll s ta te s )

1

S
LP
TR

3

4

11

RX_ON

PLL_O N(R x L is te n S ta te )F ra m eEnd

P LL _O N

B U SY_TX(T ra n s m it S ta te )(P L L S ta te )10

9SLPTR = 1
or
TX_STARTFORCE_PLL_ON

14(a ll s ta te s e x c e p t S L E E P ,TR X _O FF)

L egend :B lu e : R e g is te r w rite to T R X _ S T A T E
Red:
C o n tro l s ig n a ls v ia R e g is te r T R X P R
G re e n : E v e n t
B a s ic O p e ra tin g M o d e S ta te s
X

Note:

S ta te tra n s itio n n u m b e r

1. State transition numbers correspond to Table 9-3 on page 42.

9.4.1.1 State Control
The radio transceiver states are controlled either by writing commands to bits
TRX_CMD of register TRX_STATE, or directly by the two control bits SLPTR andTRXRST of the TRXPR register. A successful state change can be verified by reading
the radio transceiver status from register TRX_STATUS.
If TRX_STATUS = 0x1F (STATE_TRANSITION_IN_PROGRESS) the radio transceiveris on a state transition. Do not try to initiate a further state change while the radiotransceiver is in STATE_TRANSITION_IN_PROGRESS.

35
8266A-MCU Wireless-12/09

Bit SLPTR is a multifunctional bit (refer to section "Transceiver Pin Register TRXPR" onpage 32 for more details). Dependent on the radio transceiver state, a “0” to “1”transition on SLPTR causes the following state transitions:• TRX_OFF SLEEP• PLL_ON BUSY_TX

Whereas resetting bit SLPTR to “0” causes the following state transitions:• SLEEP TRX_OFF

Bit TRXRST causes a reset of all radio transceiver registers and forces the radiotransceiver into TRX_OFF state.
For all states except SLEEP, the state change commands FORCE_TRX_OFF or
TRX_OFF lead to a transition into TRX_OFF state. If the radio transceiver is in active
receive or transmit states (BUSY_*), the command FORCE_TRX_OFF interrupts these
active processes, and forces an immediate transition to TRX_OFF. In contrast a
TRX_OFF command is stored until an active state (receiving or transmitting) has been
finished. After that the transition to TRX_OFF is performed.
For a fast transition from receive or active transmit states to PLL_ON state thecommand FORCE_PLL_ON is provided. In contrast to FORCE_TRX_OFF thiscommand does not disable the PLL and the analog voltage regulator AVREG. It is notavailable in states SLEEP, and RESET.
The completion of each requested state-change shall always be confirmed by reading
the bits TRX_STATUS of register TRX_STATUS.
9.4.1.2 Basic Operating Mode Description
9.4.1.2.1 SLEEP – Sleep StateIn radio transceiver SLEEP state, the entire radio transceiver is disabled. No circuitry is
operating. The radio transceiver’s current consumption is reduced to leakage current
only. This state can only be entered from state TRX_OFF, by setting the bit
SLPTR = “1”.
Setting SLPTR = “0” returns the radio transceiver to the TRX_OFF state. During radiotransceiver SLEEP the register contents remains valid while the content of the Frame
Buffer and the security engine (AES) are cleared.
TRXRST = “1” in SLEEP state returns the radio transceiver to TRX_OFF state andthereby sets all registers to their reset values.
9.4.1.2.2 TRX_OFF – Clock State
This state is reached immediately after Power On or Reset. In TRX_OFF the crystal
oscillator is running. The digital voltage regulator is enabled, thus the radio transceiver
registers, the Frame Buffer and security engine (AES) are accessible (see section"Frame Buffer" on page 77 and "Security Module (AES)" on page 92).
SLPTR and TRXRST in register TRXPR can be used for state control (see "State
Control" on page 35 for details). The analog front-end is disabled during TRX_OFF.
Entering the TRX_OFF state from radio transceiver SLEEP, or RESET state isindicated by the TRX24_AWAKE interrupt.

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ATmega128RFA1
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ATmega128RFA1
9.4.1.2.3 PLL_ON – PLL StateEntering the PLL_ON state from TRX_OFF state first enables the analog voltage
regulator (AVREG). After the voltage regulator has been settled the PLL frequency
synthesizer is enabled. When the PLL has been settled at the receive frequency to achannel defined by bits CHANNEL of register PHY_CC_CCA a successful PLL lock is
indicated by issuing a TRX24_PLL_LOCK interrupt.
If an RX_ON command is issued in PLL_ON state, the receiver is immediately enabled.
If the PLL has not been settled before the state change nevertheless takes place. Even
if the register bits TRX_STATUS of register TRX_STATUS indicates RX_ON, actual
frame reception can only start once the PLL has locked.
The PLL_ON state corresponds to the TX_ON state in IEEE 802.15.4.
9.4.1.2.4 RX_ON and BUSY_RX – RX Listen and Receive StateIn RX_ON state the receiver blocks and the PLL frequency synthesizer are enabled.
The receive mode is internally separated into the RX_ON and BUSY_RX states. Thereis no difference between these states with respect to the analog radio transceivercircuitry, which are always turned on. In both states the receiver and the PLL frequency
synthesizer are enabled.
During RX_ON state the receiver listens for incoming frames. After detecting a valid
synchronization header (SHR), the receiver automatically enters the BUSY_RX state.
The reception of a valid PHY header (PHR) generates an TRX24_RX_START interrupt
and receives and demodulates the PSDU data.
During PSDU reception the frame data are stored continuously in the Frame Buffer until
the last byte was received. The completion of the frame reception is indicated by an
TRX24_RX_END interrupt and the radio transceiver reenters the state RX_ON. At thesame time the bits RX_CRC_VALID of register PHY_RSSI are updated with the resultof the FCS check (see "Frame Check Sequence (FCS)" on page 66).
Received frames are passed to the frame filtering unit, refer to section "Frame Filtering"on page 54. If the content of the MAC addressing fields of a frame (refer toIEEE 802.15.4 section 7.2.1) matches to the expected addresses, which is further
dependent on the addressing mode, an address match interrupt (TRX24_XAH_AMI) isissued, refer to "Interrupt Logic" on page 33. The expected address values are to be
stored in the registers Short-Address, PAN-ID and IEEE-address. Frame filtering isavailable in Basic and Extended Operating Mode, refer to section "Frame Filtering" onpage 54.
Leaving state RX_ON is only possible by writing a state change command to bits
TRX_CMD of register TRX_STATE.
9.4.1.2.5 BUSY_TX – Transmit StateA transmission can only be initiated in state PLL_ON. There are two ways to start atransmission:• Setting Bit SLPTR of register TRXPR to ‘1’. The bit should be cleared before theframe has been transmitted. This mode is for legacy operation and should be
replaced by the TX_START command below.
• TX_START command to bits TRX_CMD of register TRX_STATE.
Either of these causes the radio transceiver into the BUSY_TX state.

37
8266A-MCU Wireless-12/09

During the transition to BUSY_TX state, the PLL frequency shifts to the transmit
frequency. The actual transmission of the first data chip of the SHR starts after 16 µs toallow PLL settling and PA ramp-up, see Figure 9-16 on page 40. After transmission of
the SHR, the Frame Buffer content is transmitted. In case the PHR indicates a frame
length of zero, the transmission is aborted.
After the frame transmission has completed, the radio transceiver automatically turns
off the power amplifier, generates a TRX24_TX_END interrupt and returns into PLL_ON
state.
9.4.1.2.6 RESET StateThe RESET state is used to set back the state machine and to reset all registers of theradio transceiver to their default values.
A reset forces the radio transceiver into the TRX_OFF state.
A reset is initiated by a ATmega128RFA1 main reset (see "Resetting the AVR" on page176) or a radio transceiver reset (see "Transceiver Pin Register TRXPR" on page 32).
During radio transceiver reset the TRXPR register is not cleared and therefore theapplication software has to set the SLPTR bit to “0”.
9.4.1.3 Interrupt Handling
All interrupts provided by the radio transceiver are supported in Basic Operating Mode(see Table 9-2 on page 34).
Required interrupts must be enabled by writing to register IRQ_MASK and the global
interrupt enable flag must be set. For a general explanation of the interrupt handlingrefer to "Reset and Interrupt Handling" on page 15 and "Interrupt Logic" on page 33.
For example, interrupts are provided to observe the status of the RX and TX operations.
On receive the TRX24_RX_START interrupt indicates the detection of a valid PHR, theTRX24_XAH_AMI interrupt an address match and the TRX24_RX_END interrupt thecompletion of the frame reception.
On transmit the TRX24_TX_END interrupt indicates the completion of the frametransmission.
Figure 9-13 on page 39 shows an example for a transmit/receive transaction between
two devices and the related interrupt events in Basic Operating Mode. Device 1
transmits a frame containing a MAC header (in this example of length 7), payload andvalid FCS. The frame is received by Device 2 which generates the interrupts during theprocessing of the incoming frame. The received frame is stored in the Frame Buffer.
If the received frame passes the address filter (refer to section "Frame Filtering" onpage 54) an address match TRX24_XAH_AMI interrupt is issued after the reception of
the MAC header (MHR).
In Basic Operating Mode the TRX24_RX_END interrupt is issued at the end of thereceived frame. In Extended Operating Mode (refer to "Extended Operating Mode" onpage 43) the interrupt is only issued if the received frame passes the address filter andthe FCS is valid. Further exceptions are explained in "Extended Operating Mode" onpage 43.
Processing delay tIRQ is a typical value (see chapter "Digital Interface Timing
Characteristics" on page 507).

38

ATmega128RFA1
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ATmega128RFA1
Figure 9-13. Timing of TRX24_RX_START, TRX24_XAH_AMI, TRX24_TX_END and TRX24_RX_END Interrupts in
Basic Operating Mode

TRX _STATE

0

128

160

P LL_O N

192

1 9 2 + (9 + m )*3 2

BU SY _TX

T im e [µ s ]PLL_O N

TX

SLPTR
IR Q

T R X 24_TX _E N D

TRX _STATE

4

1

1

7

m

2

P r e a m b le

SFD

PHR

MHR

MSDU

FC S

R X_O NB U S Y_R X

IR Q

T R X 24_R X _S TA R T

I n te r r u p t la te n c yt IR Qon AirF r a m e C o n te n t

Frame

N u m b e r o f O c te ts

RX

16 µs

(Device 2)

T y p . P ro c e s s in g D e la y(Device1)-1 6

RX_O NT R X 24_
R X_EN D

T R X 24_XA H _AM I

t IR Qt IR Q

9.4.1.4 Basic Operating Mode Timing
The following paragraphs depict state transitions and their timing properties. Timing
figures are explained in Table 9-3 on page 42 and section "Digital Interface Timing
Characteristics" on page 507.
9.4.1.4.1 Wake-up Procedure
The wake-up procedure from radio transceiver SLEEP state is shown in Figure 9-14
below. This figure implies, that the microcontroller is already running and hence, thedigital voltage regulator is enabled. If the microcontroller clock source is set toTransceiver Clock, the crystal oscillator is also running, which reduces the radiotransceiver wake-up time further. For information about the wake-up timing of the
microcontroller, depending on the different clock source options, refer to "System Clockand Clock Options" on page 147.
In order to calculate the total wake-up delay from microcontroller sleep mode (see"Power Management and Sleep Modes" on page 156), the microcontroller wake-up
time, including the voltage regulator ramp-up and the radio transceiver wake-up time
has to be added.
Figure 9-14. Wake-up Procedure from Transceiver SLEEP State
0

Block
Tim e

400

200

Time [µs]TRX24_AW AKE IRQSLPTR = 0

Event
State

100

TRX_OFFSLEEPXOSC startup

FTN

XOSC enabledt TR2

The radio transceiver SLEEP state is left by releasing bit SLPTR to “0”. This restarts the
XOSC if it is not already running. After tTR2 = 215 µs + 25 µs = 240 µs (see Table 9-3 onpage 42) the radio transceiver enters TRX_OFF state. If the XOSC is already running,
the radio transceiver enters TRX_OFF state after 25 µs.

39
8266A-MCU Wireless-12/09

During this wake-up procedure the calibration of the filter-tuning network (FTN) is
performed. Entering TRX_OFF state is signaled by the TRX24_AWAKE interrupt, if
enabled.
9.4.1.4.2 PLL_ON and RX_ON States
The transition from TRX_OFF to PLL_ON and RX_ON mode is shown in Figure 9-15
below.
Figure 9-15. Transition from TRX_OFF to PLL_ON and RX_ON State0

TRX24_PLL_LOCK IRQ

Event
State

PLL_ON

TRX_OFF

Block

AVREG

Command

PLL_ON

Time

Note:

Time [µs]

100

RX_ON
RX

PLL

RX_ON
tTR4

tTR8

1. If TRX_CMD = RX_ON in TRX_OFF state RX_ON state is entered immediately,even if the PLL has not settled.
2. If the AVR ADC module is enabled, the AVREG is already started and thus thestate transition time tTR4 is reduced.

Entering the commands PLL_ON or RX_ON in TRX_OFF state initiates a ramp-up
sequence of the internal 1.8V voltage regulator for the analog domain (AVREG), if
AVREG is not already enabled by the AVR ADC module. RX_ON state can be entered
any time from PLL_ON state regardless whether the PLL has already locked asindicated by the TRX24_PLL_LOCK interrupt.
9.4.1.4.3 BUSY_TX and RX_ON States
The transition from PLL_ON to BUSY_TX state and subsequent to RX_ON state isshown in Figure 9-16 below.
Figure 9-16. PLL_ON to BUSY_TX to RX_ON Timing
0

Event
State

x

x + 32Tim e [µ s]

SLPTR
PLL_O N

BUSY_TX

Block

PLL

Com m andor com m and

Tim e

16

PA
TX_STARTt TR 10

RX_O N
PA, TXPLLRX

R X_O Nt TR 11

Starting from PLL_ON state it is assumed that the PLL is already locked. A
transmission is initiated either by writing “1” to bit SLPTR or by command TX_START.
The PLL settles to the transmit frequency and the PA is enabled.
40

ATmega128RFA1
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ATmega128RFA1
tTR10 = 16 µs after initiating the transmission, the radio transceiver changes into
BUSY_TX state and the internally generated SHR is transmitted. After that the PSDU
data are transmitted from the Frame Buffer.
After completing the frame transmission, indicated by the TRX24_TX_END interrupt,
the PLL settles back to the receive frequency within tTR11 = 32 µs in state PLL_ON.
If during TX_BUSY the radio transmitter is programmed to change to a receive state it
automatically proceeds the state change to RX_ON state after finishing thetransmission.
9.4.1.4.4 Reset Procedure
The radio transceiver reset procedure is shown in Figure 9-17 below.
Figure 9-17. Reset Procedure0xx + 10T im e [µ s ]x + 40E vent[T R X 2 4 _ A W A K E IR Q ]S ta tev a rio u s

B lo c k

TR X_O FF

X O S C , D V R E G e n a b le dFTN

X O S C , D V R E G e n a b le d

TRXRST
T im eNote:> t1 13 x A V R c lo c k

tTR13

1. Timing parameter tTR13 = 37 µs refers to Table 9-3 on page 42; t11 refers to "Digital
Interface Timing Characteristics" on page 507.
2. If TRXRST is set during radio transceiver SLEEP state, the XOSC startup delay isextended by the XOSC startup time.

TRXRST = “1” resets all radio transceiver registers to their default values.
The radio transceiver reset is released automatically after 3 AVR clock cycles and thewake-up sequence without restarting XOSC and DVREG, nevertheless an FTN
calibration cycle is performed, refer to "Automatic Filter Tuning (FTN)" on page 83. Afterthat the TRX_OFF state is entered.
Figure 9-17 above illustrates the radio transceiver reset procedure if the radiotransceiver is in any state but not in SLEEP state.
If the radio transceiver was in SLEEP state, the SLPTR bit in the TRXPR register must
be cleared prior to clearing the TRXRST bit in order to enter the TRX_OFF state.
Otherwise the radio transceiver enters the SLEEP state immediately.
If the radio transceiver was in SLEEP state and the Transceiver Clock is not selected as
the microcontroller clock source, the XOSC is enabled before entering TRX_OFF state.
If register TRX_STATUS indicates STATE_TRANSITION_IN_PROGRESS duringsystem initialization until the radio transceiver reaches TRX_OFF, do not try to initiate afurther state change while the radio transceiver is in this state.
Note that before accessing the radio transceiver module the TRX24_AWAKE event
should be checked.

41
8266A-MCU Wireless-12/09

9.4.1.4.5 State Transition Timing Summary
The transition numbers correspond to Table 9-3 below. See measurement setup in"Basic Application Schematic" on page 493.
Table 9-3. Radio Transceiver State Transition Timing
No

Symbol

1

tTR2

SLEEP



TRX_OFF

240

2

tTR3

TRX_OFFSLEEP

35 · 1 / fCLKM

3

tTR4

TRX_OFF

PLL_ON

110

4

tTR5

PLL_ON

TRX_OFF

1

5

tTR6

TRX_OFF



RX_ON

110

6

tTR7

RX_ON



TRX_OFF

1

7

tTR8

PLL_ON



RX_ON

1

8

tTR9

RX_ON



PLL_ON

1

Transition time is also valid for TX_ARET_ON, RX_AACK_ON

Transition

Time [µs], (typ)Comments
Depends on crystal oscillator setup (CL = 10 pf)
TRX_OFF state indicated by TRX24_AWAKE interrupt
For fCLKM > 250 kHz
Depends on external capacitor at AVDD (1 µF nom)
Depends on external capacitor at AVDD (1 µF nom)

9

tTR10

PLL_ON

BUSY_TX

16

When setting bit SLPTR or TRX_CMD = TX_START, the firstsymbol transmission is delayed by 16 µs (PLL settling andPA ramp up).

10

tTR11

BUSY_TX

PLL_ON32

PLL settling time from TX_BUSY to PLL_ON state

11

tTR12

All modes



TRX_OFF

1

Using TRX_CMD = FORCE_TRX_OFF (see register
TRX_STATE),
Not valid for SLEEP state

12

tTR13

RESET



TRX_OFF37

Not valid for SLEEP state

13

tTR14

Variousstates

PLL_ON

1

Using TRX_CMD = FORCE_PLL_ON (see register
TRX_STATE),
Not valid for SLEEP, RESET and TRX_OFFThe state transition timing is calculated based on the timing of the individual blocks
shown in Table 9-8 on page 51. The worst case values include maximum operating
temperature, minimum supply voltage, and device parameter variations.
Table 9-8. Analog Block Initialization and Settling TimeNo

Symbol BlockTime [µs], (typ)Time [µs], (max) Comments
1000

Leaving SLEEP state, depends on crystal Q factor and load
capacitor

25

FTN tuning time, fixed

60

1000

Depends on external bypass capacitor at DVDD
(CB3 = 1 µF nom., 10 µF worst case), depends on VDEVDD

AVREG

60

1000

Depends on external bypass capacitor at AVDD
(CB1 = 1 µF nom., 10 µF worst case) , depends on VEVDDtTR19

PLL, initial

110

155

PLL settling time TRX_OFF  PLL_ON, including 60 µs
AVREG settling time

20

tTR20

PLL, settling

11

24

Settling time between channel switch

21

tTR21

PLL, CF cal

35

22

tTR22

PLL, DCU cal

6

PLL DCU calibration, refer to "Calibration Loops" onpage 83

23

tTR23

PLL, RX  TX

16

Maximum PLL settling time RX  TX

15

tTR15

XOSC

16

tTR16

FTN

17

tTR17

DVREG

18

tTR18

19

42

215

PLL center frequency calibration, refer to "Calibration
Loops" on page 83

ATmega128RFA1
8266A-MCU Wireless-12/09

ATmega128RFA1
No

Symbol BlockTime [µs], (typ)Time [µs], (max) Comments

24

tTR24

PLL, TX  RX

32

Maximum PLL settling time TX  RX

25

tTR25

RSSI, update

2

RSSI update period in receive states, refer to "Reading
RSSI" on page 68

26

tTR26

ED

140

ED measurement period, refer to "Measurement
Description" on page 69

27

tTR27

SHR, sync

28

tTR28

CCA

140

CCA measurement period, refer to "Configuration and
CCA Request" on page 71

29

tTR29

Random value

1

Random value update period, refer to "Random
Number Generator" on page 85

Typical SHR synchronization period,"Measurement Description" on page 69

96

refer

to

9.4.2 Extended Operating Mode
The Extended Operating Mode is a hardware MAC accelerator and goes beyond thebasic radio transceiver functionality provided by the Basic Operating Mode. It handles
time critical MAC tasks requested by the IEEE 802.15.4 standard or by hardware suchas automatic acknowledgement, automatic CSMA-CA and retransmission. This results
in a more efficient IEEE 802.15.4 software MAC implementation including reduced code
size and may allow operating at lower microcontroller clock rates.
The Extended Operating Mode is designed to support IEEE 802.15.4-2006 compliant
frames; the mode is backward compatible to IEEE 802.15.4-2003 and supports non
IEEE 802.15.4 compliant frames. This mode comprises the following procedures:
Automatic acknowledgement (RX_AACK) divides into the tasks:• Frame reception and automatic FCS check;• Configurable addressing fields check;• Interrupt indicating address match;• Interrupt indicating frame reception, if it passes address filtering and FCS check;• Automatic ACK frame transmission (if the received frame passed the address filter
and FCS check and if an ACK is required by the frame type and ACK request);• Support of slotted acknowledgment using SLPTR bit for frame start.
Automatic CSMA-CA and Retransmission (TX_ARET) divides into the tasks:• CSMA-CA including automatic CCA retry and random back-off;• Frame transmission and automatic FCS field generation;• Reception of ACK frame (if an ACK was requested);• Automatic frame retry if ACK was expected but not received;• Interrupt signaling with transaction status.
Automatic FCS check and generation (refer to "Frame Check Sequence (FCS)" onpage 66) is used by the RX_AACK and TX_ARET modes. In RX_AACK mode anautomatic FCS check is always performed for incoming frames.
An ACK received in TX_ARET mode within the time required by IEEE 802.15.4 isaccepted if the FCS is valid and if the sequence number of the ACK matches thesequence number of the previously transmitted frame. Dependent on the value of the43
8266A-MCU Wireless-12/09

frame pending subfield in the received acknowledgement frame the transaction status isset according to Table 9-16 on page 58.
The state diagram including the Extended Operating Mode states is shown in Figure 918 below. Yellow marked states represent the Basic Operating Mode; blue marked
states represent the Extended Operating Mode.
Figure 9-18. Extended Operating Mode State Diagram
SLEEP(S le e p S ta te )0

X O S C = O FF

TR

LP
S

T R X _O F F

12FO RCE_TRX_O FF

TRXRST = 1

S
LP

2

13

(C lo c k S ta te )(all m o d e s e xce p t S L E E P )(fro m a ll sta te s)

=

1

TR

=

3

TRXRST = 0

RESET

XO SC =O N

FF

_O
X

_O

R

F ra m e
End

TR
X

8

RX_ON
(R x L is te n S ta te )4FF

(R e c e iv e S ta te )_O

BUSY_RXSHR
D e te c te d

5
X
TR

6

N
_O
LL

N

P

7

RX_ON
PLL_O NSLPTR = 1
or
TX_START

PLL_ON11

BUSY_TX(P L L S ta te )10

(T ra n s m it S ta te )9

TX_ARET_ON

FORCE_PLL_ON
see notes
F rom / T o
T R X _O F FSLPTR = 1
or
TX_STARTSHR
D e tec te d

R X _A A C K _ O N

B U S Y _R X _A A C K

F ra m e
End

TX
_A
RE
T_
TR
ON
X_
OF
F

K_
ON
AC

PLL_ON

RX
_A
AC
K_
TR
ON
X_
OF
F

F rom / T o
T R X _O F F

RX
_A

PL
L_

ON

14

T ran s a c tio n
F in is h e d

TX_ARET_ON

B U S Y _T X _A R E T
F ra m eEnd

Legend:B lu e : R e g iste r W rite to T R X _ S T A T E
R ed :
C o n tro l sig n a ls via R e g iste r T R X P R
G re e n : E ve nt
B a sic O p e ra ting M o d e S ta te s
E xte n de d O p e ra tin g M o d e S ta te s

Note:

44

1. State transition numbers correspond to Table 9-3 on page 42.

ATmega128RFA1
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ATmega128RFA1
9.4.2.1 State Control
The Extended Operating Mode states RX_AACK and TX_ARET are controlled via thebits TRX_CMD of register TRX_STATE, which receives the state transition commands.
The states are entered from TRX_OFF or PLL_ON state as illustrated in Figure 9-18 on
page 44. The completion of each state change command shall always be confirmed byreading the TRX_STATUS register.
RX_AACK - Receive with Automatic ACK
A state transition to RX_AACK_ON from PLL_ON or TRX_OFF is initiated by writing thecommand RX_AACK_ON to the register bits TRX_CMD. The state change can be
confirmed by reading register TRX_STATUS, those changes to RX_AACK_ON or
BUSY_RX_AACK on success. BUSY_RX_AACK is returned if a frame is currently
being received.
The RX_AACK state is left by writing command TRX_OFF or PLL_ON to the register
bits TRX_CMD. If the radio transceiver is within a frame receive or acknowledgmentprocedure (BUSY_RX_AACK) the state change is executed after finish. Alternatively,
the commands FORCE_TRX_OFF or FORCE_PLL_ON can be used to cancel the
RX_AACK transaction and change into radio transceiver state TRX_OFF or PLL_ON
respectively.
TX_ARET - Transmit with Automatic Retry and CSMA-CA Retry
Similarly, a state transition to TX_ARET_ON from PLL_ON or TRX_OFF is initiated bywriting command TX_ARET_ON to register bits TRX_CMD. The radio transceiver is in
the TX_ARET_ON state after TRX_STATUS register changes to TX_ARET_ON. The
TX_ARET transaction is started with writing ‘1’ to the SLPTR bit of the TRXPR registeror writing the command TX_START to register bits TRX_CMD.
TX_ARET state is left by writing the command TRX_OFF or PLL_ON to the register bits
TRX_CMD. If the radio transceiver is within a CSMA-CA, a frame-transmit or an
acknowledgment procedure (BUSY_TX_ARET) the state change is executed after
finish. Alternatively, the command FORCE_TRX_OFF or FORCE_PLL_ON can beused to instantly terminate the TX_ARET transaction and change into radio transceiverstates TRX_OFF or PLL_ON, respectively.
Note that a state change request from TRX_OFF to RX_AACK_ON or TX_ARET_ON
internally passes the state PLL_ON to initiate the radio transceiver. Thus the readinessto receive or transmit data is delayed accordingly. It is recommended to use interrupt
TRX24_PLL_LOCK as an indicator.
9.4.2.2 Configuration
The use of the Extended Operating Mode is based on Basic Operating Modefunctionality. Only features beyond the basic radio transceiver functionality aredescribed in the following sections. For details on the Basic Operating Mode refer tosection "Basic Operating Mode" on page 35.
When using the RX_AACK or TX_ARET modes, the following registers needs to be
configured.
RX_AACK configuration steps:• Short address, PAN-ID and IEEE address (register SHORT_AADR_0,
SHORT_ADDR_1, PAN_ID_0, PAN_ID_1, IEEE_ADDR_0 … IEEE_ADDR_7)• Configure RX_AACK properties (register XAH_CTRL_0, CSMA_SEED_1)
oHandling of Frame Version Subfield
45

8266A-MCU Wireless-12/09

oHandling of Pending Data IndicatoroCharacterize as PAN coordinatoroHandling of Slotted Acknowledgement• Additional Frame Filtering Properties (register XAH_CTRL_1, CSMA_SEED_1)oPromiscuous ModeoEnable or disable automatic ACK generationoHandling of reserved frame types

The addresses for the address match algorithm are to be stored in the appropriate
address registers. Additional control of the RX_AACK mode is done with registers
XAH_CTRL_1 and CSMA_SEED_1.
As long as a short address has not been set, only broadcast frames and frames
matching the IEEE address can be received.
Configuration examples for different device operating modes and handling of various
frame types can be found in section "Description of RX_AACK Configuration Bits" onpage 49.
TX_ARET configuration steps:• Leave register bit TX_AUTO_CRC_ON = 1

register TRX_CTRL_1• Configure CSMA-CAo

MAX_FRAME_RETRIES

register XAH_CTRL_0

o

MAX_CSMA_RETRIES

register XAH_CTRL_0

o

CSMA_SEED

registersCSMA_SEED_0, CSMA_SEED_1

o

MAX_BE, MIN_BE

register CSMA_BE• Configure CCA (see section "Configuration and CCA Request" on page 71)
MAX_FRAME_RETRIES (register XAH_CTRL_0) defines the maximum number offrame retransmissions.
The register bits MAX_CSMA_RETRIES (register XAH_CTRL_0) configure the numberof CSMA-CA retries after a busy channel is detected.
The CSMA_SEED_0 and CSMA_SEED_1 registers define a random seed for the backoff-time random-number generator of the radio transceiver.
The MAX_BE and MIN_BE register bits (register CSMA_BE) set the maximum andminimum CSMA back-off exponent (according to [1] on page 100).
9.4.2.3 RX_AACK_ON – Receive with Automatic ACK
The general functionality of the RX_AACK procedure is shown in Figure 9-19 on page48.
The gray shaded area is the standard flow of a RX_AACK transaction forIEEE 802.15.4 compliant frames (refer to section "Configuration of IEEE Scenarios" onpage 50). All other procedures are exceptions for specific operating modes or frame
formats (refer to section "Configuration of non IEEE 802.15.4 Compliant Scenarios" onpage 52).
The frame filtering operation is described in detail in section "Frame Filtering" on page54.
In RX_AACK_ON state, the radio transceiver listens for incoming frames. After
detecting SHR and a valid PHR, the radio transceiver parses the frame content of the
MAC header (MHR) as described in section "PHY Header (PHR)" on page 61.
46

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ATmega128RFA1
Generally, at nodes, configured as a normal device or PAN coordinator, a frame is notindicated if the frame filter does not match and the FCS is invalid. Otherwise, theTRX_24_RX_END interrupt is issued after the completion of the frame reception. The
microcontroller can then read the frame. An exception applies if promiscuous mode isenabled (see section "Configuration of IEEE Scenarios" on page 50). In that case a
TRX_24_RX_END interrupt is issued even if the FCS fails.
If the content of the MAC addressing fields of the received frame (refer toIEEE 802.15.4 section 7.2.1) matches one of the configured addresses, dependent on
the addressing mode, an address match interrupt (TRX24_XAH_AMI) is issued (refer tosection "Frame Filtering" on page 54). The expected address values are to be stored inregisters Short-address, PAN-ID and IEEE-address. Frame filtering as described in
section "Frame Filtering" on page 54 is also valid for Basic Operating Mode.
During reception the radio transceiver parses bit[5] (ACK Request) of the frame control
field of the received data or the MAC command frame to check if an ACK reply is
expected. In that case and if the frame passes the third level of filtering (seeIEEE 802.15.4-2006, section 7.5.6.2), the radio transceiver automatically generates andtransmits an ACK frame. After the ACK transmission is finished, a TRX24_TX_END
interrupt is generated.
The content of the frame pending subfield of the ACK response is set by bit
AACK_SET_PD of register CSMA_SEED_1 when the ACK frame is sent in response toa data request MAC command frame, otherwise this subfield is set to “0”. The
sequence number is copied from the received frame.
Optionally, the start of the transmission of the acknowledgement frame can be
influenced by register bit AACK_ACK_TIME. Default value (according to standard
IEEE 802.15.4, page 54) is 12 symbol times after the reception of the last symbol of adata or MAC command frame.
If the bit AACK_DIS_ACK of register CSMA_SEED_1 is set, no acknowledgement
frame is sent even if an acknowledgment frame was requested. This is useful for
operating the MAC hardware accelerator in promiscuous mode (see section"Configuration of non IEEE 802.15.4 Compliant Scenarios" on page 52).
The status of the RX_AACK operation is indicated by the bits TRAC_STATUS ofregister TRAC_STATUS.
During the operations
BUSY_RX_AACK state.

described

above

the

radio

transceiver

remainsin

47
8266A-MCU Wireless-12/09

Figure 9-19. Flow Diagram of RX_AACKTRX_STATE = RX_AACK_ON

SHR detectedN

Y
TRX_STATE = BUSY_RX_AACKGenerate TRX24_RX_START
interrupt

Scanning MHR(see Note 1)

Y

Reserved Frames

N

Frame
Filtering
Note 1: Frame Filtering, Promiscuous Mode andReserved Frames:- A radio transceiver in Promiscuous
Mode, or configured to receive Reserved
Frames handles received frames passing
the third level of filtering- For details refer to the description ofPromiscuous Mode and Reserved
Frame Types

Promiscuous Mode

Frame reception

Generate TRX24_XAH_AMI
interrupt
AACK_PROM_MODE== 1

Frame receptionNYN

FCS validN(see Note 2)

Note 2: FCS check is omitted for Promiscous Mode

FCF[2:0]>3

Y
Generate TRX24_RX_END
interrupt

Y

NN

ACK requested

AACK_UPLD_RES_FT== 1(see Note 3)

Note 3: Additional conditions:- ACK requested &- ACK_DIS_ACK==0 &- frame_version<=AACK_FVN_MODEYYNFCS validN

Slotted Operation
== 0
Y
Y

N

AACK_ACK_TIME== 0

AACK_ACK_TIME== 0

Y
Wait 2 symbol
periods

Generate
TRX24_RX_END
interrupt

Y

Wait 6 symbol
periods

SLPTR bit=1

Generate
TRX24_RX_END
interrupt

N

Wait 12 symbol
periods

Wait 2 symbol
periods

N

Y
Transmit ACK
GenerateTRX24_TX_END
interrupt
TRX_STATE = RX_AACK_ON

48

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ATmega128RFA1
9.4.2.3.1 Description of RX_AACK Configuration Bits
Overview
The following table summarizes all register bits which affect the behavior of a
RX_AACK transaction. For address filtering it is further required to setup address
registers to match to the expected address.
Configuration and address bits are to be set in TRX_OFF or PLL_ON state prior toswitching to RX_AACK mode.
A graphical representation of various operating modes is illustrated in Figure 9-19 on
page 48.
Table 9-5. Overview of RX_AACK Configuration Bits
Register Name

Register Bits

SHORT_ADDR_0/1
PAN_ADDR_0/1
IEEE_ADDR_0…
IEEE_ADDR_7

Description
Set node addresses

RX_SAFE_MODE

7

Protect buffer after frame receive

AACK_PROM_MODE

1

Support promiscuous mode

AACK_ACK_TIME

2

Change auto acknowledge start time

AACK_UPLD_RES_FT

4

Enable reserved frame type reception, needed toreceive non-standard compliant frames

AACK_FLTR_RES_FT

5Filter reserved frame types like data frame type,needed for filtering of non-standard compliant
framesSLOTTED_OPERATION

0

If set, acknowledgment transmission has to be
triggered by register bit SLPTR

AACK_I_AM_COORD

3

If set, the device is a PAN coordinator

AACK_DIS_ACK

4

Disable generation of acknowledgment

AACK_SET_PD

5

Set frame pending subfield in Frame Control Field(FCF), refer to section "Overview" on page 66

AACK_FVN_MODE

7:6

Controls the ACK behavior, depending on FCF
frame version number

The usage of the RX_AACK configuration bits for various operating modes of a node is
explained in the following sections. Configuration bits not mentioned in the following two
sections should be set to their reset values.
All registers mentioned in Table 9-5 above are described in section "Register Summary"on page 60.
Note, that the general behavior of the Extended Feature Set settings:• OQPSK_DATA_RATE(PSDU data rate)• SFD_VALUE(alternative SFD value)• ANT_DIV(Antenna Diversity)• RX_PDT_LEVEL(blocking frame reception of lower power signals)

are completely independent from RX_AACK mode (see "Radio Transceiver Extended
Feature Set" on page 85). Each of these operating modes can be combined with the
RX_AACK mode.

49
8266A-MCU Wireless-12/09

9.4.2.3.2 Configuration of IEEE Scenarios
Normal Device
The Table 9-6 below shows a typical RX_AACK configuration of an IEEE 802.15.4
device operated as a normal device rather than a PAN coordinator or router.
Table 9-6. Configuration of IEEE 802.15.4 Devices
Register Name

Register Bits

SHORT_ADDR_0/1
PAN_ADDR_0/1
IEEE_ADDR_0…
IEEE_ADDR_7

Description
Set node addresses

RX_SAFE_MODE

7

0: disable frame protection
1: enable frame protection

SLOTTED_OPERATION0

0: if transceiver works in unslotted mode
1: if transceiver works in slotted mode

AACK_FVN_MODE

7:6

Controls the ACK behavior, depending on FCF
frame version number
0x00 : acknowledges only frames with version
number 0, i.e. according to IEEE 802.15.4-2003
frames0x01 : acknowledges only frames with version
number 0 or 1, i.e. frames according toIEEE 802.15.4-2006
0x10 : acknowledges only frames with version
number 0 or 1 or 2
0x11 : acknowledges all frames, independent of
the FCF frame version number

Notes:

1. If no short address has been configured before the device has been assigned oneby the PAN-coordinator, only frames directed to either the broadcast address or
the IEEE address are received.
2. In IEEE 802.15.4-2003 standard the frame version subfield did not yet exist but
was marked as reserved. According to this standard, reserved fields have to be set
to zero. On the other hand, IEEE 802.15.4-2003 standard requires ignoring
reserved bits upon reception. Thus, there is a contradiction in the standard which
can be interpreted in two ways:a) If a network should only allow access to nodes which
IEEE 802.15.4-2003, then AACK_FVN_MODE should be set to 0.

use

the

b) If a device should acknowledge all frames independent of its frame version,
AACK_FVN_MODE should be set to 3. However, this can result in conflicts withco-existing IEEE 802.15.4-2006 standard compliant networks.
The same holds for PAN coordinators as described below.

PAN-Coordinator
Table 9-7 on page 51 shows the RX_AACK configuration for a PAN coordinator.

50

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ATmega128RFA1
Table 9-7. Configuration of a PAN Coordinator
Register Name

Register Bits

SHORT_ADDR_0/1
PAN_ADDR_0/1
IEEE_ADDR_0…
IEEE_ADDR_7

Description
Set node addresses

RX_SAFE_MODE

7

0: disable frame protection
1: enable frame protection

SLOTTED_OPERATION0

0: if transceiver works in unslotted mode
1: if transceiver works in slotted mode

AACK_I_AM_COORD

3

1: device is PAN coordinator

AACK_SET_PD

5

0: frame pending subfield is not set in FCF
1: frame pending subfield is set in FCF

AACK_FVN_MODE

7:6

Controls the ACK behavior, depends on FCF
frame version number
0x00 : acknowledges only frames with version
number 0, i.e. according to IEEE 802.15.4-2003
frames0x01 : acknowledges only frames with version
number 0 or 1, i.e. frames according toIEEE 802.15.4-2006
0x10 : acknowledges only frames with version
number 0 or 1 or 2
0x11 : acknowledges all frames, independent of
the FCF frame version number

Promiscuous Mode
The promiscuous mode is described in IEEE 802.15.4-2006, section 7.5.6.5. This modeis further illustrated in Radio Transceiver Extended Feature Set on page 85. According
to IEEE 802.15.4-2006 when in promiscuous mode, the MAC sub layer shall passreceived frames with correct FCS to the next higher layer without further processing.
That implies that frames should never be acknowledged.
Only second level filter rules as defined by IEEE 802.15.4-2006, section 7.5.6.2, areapplied to the received frame.
Table 9-8 below shows the typical configuration of a device operating in promiscuous
mode.
Table 9-8. Configuration of Promiscuous Mode
Register Name

Register Bits

SHORT_ADDR_0/1
PAN_ADDR_0/1
IEEE_ADDR_0…
IEEE_ADDR_7

Description
Each address shall be set: 0x00

AACK_PROM_MODE

1

1: Enable promiscuous mode

AACK_DIS_ACK

4

1: Disable generation of acknowledgment

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Register Name

Register Bits

AACK_FVN_MODE

7:6

Description
Controls the ACK behavior, depends on FCF frame
version number
0x00 : acknowledges only frames with version
number 0, i.e. according to IEEE 802.15.4-2003
frames0x01 : acknowledges only frames with version
number 0 or 1, i.e. frames according toIEEE 802.15.4-2006
0x10 : acknowledges only frames with version
number 0 or 1 or 2
0x11 : acknowledges all frames, independent of the
FCF frame version number

Second level of filtering according to IEEE 802.15.4-2006, section 7.5.6.2, is applied toa received frame if the radio transceiver is in promiscuous mode. However, a
TRX24_RX_END interrupt is issued even if the FCS is invalid. Thus it is necessary toread bit RX_CRC_VALID of register PHY_RSSI after the TRX24_RX_END interrupt inorder to verify the reception of a frame with a valid FCS.
If a device, operating in promiscuous mode, receives a frame with a valid FCS which inaddition passed the third level filtering according to IEEE 802.15.4-2006, section
7.5.6.2, an acknowledgement frame would be transmitted. According to the definition of
the promiscuous mode a received frame shall not be acknowledged even if it isrequested. Thus bit AACK_DIS_ACK of register CSMA_SEED_1 has to be set to 1.
In all receive modes a TRX24_AMI interrupt is issued, when the received frame
matches the node’s address according to the filter rules described in section "Frame
Filtering" on page 54.
Alternatively, in RX_ON state of the Basic Operating Mode when a valid PHR is
detected a TRX24_RX_START interrupt is generated and the frame is received. The
end of the frame reception is signalized with a TRX24_RX_END interrupt. At the sametime the bit RX_CRC_VALID of register PHY_RSSI is updated with the result of the
FCS check (see "Overview" on page 66). The RX_CRC_VALID bit must be checked inorder to dismiss corrupted frames according to the definition of the promiscuous mode.
9.4.2.3.3 Configuration of non IEEE 802.15.4 Compliant Scenarios
SnifferTable 9-9 below shows a RX_AACK configuration to setup a sniffer device. Other
RX_AACK configuration bits should be set to their reset values (see Table 9-5 on page49). All frames received are indicated by a TRX24_RX_START and TRX24_RX_END
interrupt. Bit RX_CRC_VALID of register PHY_RSSI is updated after frame reception
with the result of the FCS check (see "Overview" on page 66). The RX_CRC_VALID bit
needs to be checked in order to dismiss corrupted frames.
Table 9-9. Configuration of a Sniffer Device
Register Name

Register Bits

Description

AACK_PROM_MODE

1

1: Enable promiscuous mode

AACK_DIS_ACK

4

1: Disable generation of acknowledgment

This operating mode is similar to the promiscuous mode.

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Reception of Reserved Frames
Frames with reserved frame types (see section Table 9-16 on page 63) can also be
handled in RX_AACK mode. This might be required when implementing proprietary,
non-standard compliant protocols. It is an extension of the address filtering in
RX_AACK mode. Received frames are either handled similar to data frames or may beallowed to completely bypass the address filter.
Table 9-10 below shows the required configuration for a node to receive reserved
frames and Figure 9-19 on page 48 shows the corresponding flow chart.
Table 9-10. RX_AACK Configuration to Receive Reserved Frame Types
Register Name

Register Bits

SHORT_ADDR_0/1
PAN_ADDR_0/1
IEEE_ADDR_0…
IEEE_ADDR_7

Description
Set node addresses

RX_SAFE_MODE

7

0: disable frame protection
1: enable frame protection

AACK_UPLD_RES_FT

4

1 : Enable reserved frame type reception

AACK_FLTR_RES_FT

5Filter reserved frame types like data frame type,see note below
0 : disable
1 : enable

SLOTTED_OPERATION0

0: if transceiver works in un-slotted mode
1: if transceiver works in slotted mode

AACK_I_AM_COORD

3

0: device is not PAN coordinator
1: device is PAN coordinator

AACK_DIS_ACK

4

0: Enable generation of acknowledgment
1: Disable generation of acknowledgment

AACK_FVN_MODE

7:6

Controls the ACK behavior, depends on FCF
frame version number
0x00 : acknowledges only frames with version
number 0, i.e. according to IEEE 802.15.4-2003
frames0x01 : acknowledges only frames with version
number 0 or 1, i.e. frames according toIEEE 802.15.4-2006
0x10 : acknowledges only frames with version
number 0 or 1 or 2
0x11 : acknowledges all frames, independent of
the FCF frame version number

There are two different options for handling reserved frame types.
1. AACK_UPLD_RES_FT = 1, AACK_FLT_RES_FT = 0:
Any non-corrupted frame with a reserved frame type is indicated by a
TRX24_RX_END interrupt. No further address filtering is applied on those frames.
A TRX24_AMI interrupt is never generated and the acknowledgment subfield isignored.
2. AACK_UPLD_RES_FT = 1, AACK_FLT_RES_FT = 1:

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If AACK_FLT_RES_FT = 1 any frame with a reserved frame type is filtered by theaddress filter similar to a data frame as described in the standard. Consequently, a
TRX24_AMI interrupt is generated upon address match. A TRX24_RX_END
interrupt is only generated if the address matched and the frame was notcorrupted. An acknowledgment is only send, when the ACK request subfield was
set in the received frame and a TRX24_RX_END interrupt occurred.
Note that It is not allowed to set AACK_FLTR_RES_FT = 1 and have register bit
AACK_FLTR_RES_FT set to 0.
Short Acknowledgment Frame (ACK) Start Timing
The bit AACK_ACK_TIME of register XAH_CTRL_1 defines the symbol time between
frame reception and transmission of an acknowledgment frame.
Table 9-11. Overview of RX_AACK Configuration Bits
Register Name

Register Bit

AACK_ACK_TIME

2

Description
0: Standard compliant acknowledgement timing of 12
symbol periods. In slotted acknowledgement operationmode, the acknowledgment frame transmission can betriggered 6 symbol periods after reception of the frame
earliest.
1: Reduced acknowledgment timing of 2 symbol periods(32 µs).

Note that this feature can be used in all scenarios, independent of other configurations.
However, shorter acknowledgment timing is especially useful when using High Data
Rate Modes to increase battery lifetime and to improve the overall data throughput; see"High Data Rate Modes" on page 86 for details.
9.4.2.4 Frame Filtering
Frame Filtering is an evaluation whether or not a received frame is dedicated for thisnode. To accept a received frame and to generate an address match interrupt(TRX24_AMI) a filtering procedure as described in IEEE 802.15.4-2006 chapter 7.5.6.2.
(Third level of filtering) is applied to the frame. The radio transceiver’s RX_AACK mode
accepts only frames that satisfy all of the following requirements (quote fromIEEE 802.15.4-2006, 7.5.6.2):
1. The Frame Type subfield shall not contain a reserved frame type.
2. The Frame Version subfield shall not contain a reserved value.
3. If a destination PAN identifier is included in the frame, it shall match macPANId or
shall be the broadcast PAN identifier (0xFFFF).
4. If a short destination address is included in the frame, it shall match either
macShortAddress or the broadcast address (0xFFFF). Otherwise, if an extended
destination address is included in the frame, it shall match aExtendedAddress.
5. If the frame type indicates that the frame is a beacon frame, the source PAN
identifier shall match macPANId unless macPANId is equal to 0xFFFF, in whichcase the beacon frame shall be accepted regardless of the source PAN identifier.
6. If only source addressing fields are included in a data or MAC command frame, theframe shall be accepted only if the device is the PAN coordinator and the source
PAN identifier matches macPANId.
The radio transceiver requires two additional rules:
1. The frame type indicates that the frame is not an ACK frame (refer toTable 9-6 onpage 50).

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2. At least one address field must be configured.
Address match, indicated by the TRX24_AMI interrupt is further controlled by thecontent of subfields of the frame control field of a received frame according to thefollowing rule:
If (Destination Addressing Mode = 0 OR 1) AND (Source Addressing Mode = 0) no
TRX24_AMI interrupt is generated, refer to Figure 9-26 on page 63. This effectively
causes all acknowledgement frames not to be announced which otherwise always pass
the filter regardless of whether they are intended for this device or not.
For backward compatibility to IEEE 802.15.4-2003 third level filter rule 2 (Frame
Version) can be disabled by the bits AACK_FVN_MODE of register CSMA_SEED_1.
Frame filtering is available in Extended and Basic Operating Mode (see section "BasicOperating Mode" on page 35); a frame passing the frame filtering generates an
TRX24_AMI interrupt, if enabled.
Note:

1. Filter rule 1 is affected by register bits AACK_FLTR_RES_FT and
AACK_UPLD_RES_FT(seeregister"XAH_CTRL_1–
Transceiver
Acknowledgment Frame Control Register 1" on page 119).
2. Filter rule 2 is affected by register bits AACK_FVN_MODE (see register"CSMA_SEED_1 – Transceiver Acknowledgment Frame Control Register 2" onpage 129).

9.4.2.4.1 RX_AACK Slotted Operation – Slotted Acknowledgement
The radio transceiver supports slotted acknowledgement operation according toIEEE 802.15.4-2006, section 5.5.4.1.
In RX_AACK mode with bit SLOTTED_OPERATION of register XAH_CTRL_0 set, thetransmission of an acknowledgement frame has to be controlled by the microcontroller.
If an ACK frame has to be transmitted the radio transceiver expects writing SLPTR=1 toactually start the transmission. This waiting state is signaled 6 symbol periods after the
reception of the last symbol of a data or MAC command frame by bits TRAC_STATUS
of register XAH_CTRL_0, which are set to SUCCESS_WAIT_FOR_ACK in that case. In
networks using slotted operation the start of the acknowledgment frame and thus theexact timing must be provided by the microcontroller.
A timing example of an RX_AACK transaction with bit SLOTTED_OPERATION ofregister XAH_CTRL_0 set is shown in the next figure. The acknowledgement frame isready to transmit 6 symbol times after the reception of the last symbol of a data or MAC
command frame. The transmission of the acknowledgement frame is initiated by the
microcontroller by writing SLPTR=1 and starts 16µs (tTR10) later. The interrupt latencytIRQ is specified in section "Digital Interface Timing Characteristics" on page 507.

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Figure 9-10. Example Timing of an RX_AACK Transaction for Slotted Operation

F ram e T ype

SFD

T R X_ ST AT E

7 04

D ata Fram e (Length = 10, A C K = 1)

1 026

A C K F ram e

R X _A A C K _O N

B U S Y _R X _AA C K

R X _A AC K_O N

RXR X/TX

TTX
X

IR Q

RX
T R X 24_T X _E N D

T R X 24_R X _E N D

t IR QT yp . Processing D elay

tim e [µ s]Frameon Air51 2

64

t IR Q
96 µ s(6 sym bols)

RX/TX

0

A C K transm ission initiated by m icrocontroller

S LP T R

w aiting period signaled by register bits T R A C _S T A T U S

S LP TRtT R 1 0

If bit AACK_ACK_TIME of register XAH_CTRL_1 is set, an acknowledgment frame canbe sent already 2 symbol times after the reception of the last symbol of a data or MAC
command frame.
9.4.2.4.2 RX_AACK Mode Timing
A timing example of an RX_AACK transaction is shown in the next figure. In thisexample a data frame of length 10 with an ACK request is received. The radiotransceiver changes to state BUSY_RX_AACK after SFD detection. The completion of
the frame reception is indicated by a TRX24_RX_END interrupt. Interrupts
TRX24_RX_START and TRX24_AMI are disabled in this example. The ACK frame isautomatically transmitted after a default wait period of 12 symbols (192 µs), bit
AACK_ACK_TIME = 0 (reset value). The interrupt latency tIRQ is specified in section"Digital Interface Timing Characteristics" on page 507.
Figure 9-11. Example Timing of an RX_AACK Transaction

F ram e T ype

512

SFD

T R X _S T A T E

D ata F ram e (Length = 10, A C K = 1)

1 088

B U S Y _R X _A A C K
RXR X _A A C K _O N
TX

IR Q

RX
TR X 24_ TX _E N D

TR X 24 _R X _E N D

t IR QT yp. P rocessing D elay

tim e [µ s]

A C K F ram e

R X _A A C K _O N

R X /T X

7 04

Frame
on Air

64

RX/TX

0

t IR Q
192 µ s
(12 sym bols)

If bit AACK_ACK_TIME of register XAH_CTRL_1 is set, an acknowledgment frame issent already 2 symbol times after the reception of the last symbol of a data or MAC
command frame.

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9.4.2.5 TX_ARET_ON – Transmit with Automatic Retry and CSMA-CA Retry
Figure 9-12. Flow Diagram of TX_ARET
TRX_STATE = TX_AR ET_O N

fra m e _ rctr = 0

N

S ta rt T X

YTR X _S TA TE = B U S Y _TX _A R E T
T R A C _ S T A T U S = IN V A L ID
(s e e N o te 1 )N

N o te 1 : If M A X _ C S M A _ R E T R IE S = 7 n o re try is
p e rfo rm e d

MAX_CSM A_RETRIES<7
Y
cs m a _ rctr = 0

R a n d o m B a c k -O ff
c sm a _ rc tr = c sm a _ rctr + 1
CCA
N
CCA
R e su lt

F a ilu rec sm a _ rctr >MAX_CSMA_RETRIESY

S u c ce ss
T ra n s m it F ra m e
fra m e _ rc tr = fra m e _ rctr + 1

A C K re q u e ste d

N

Y

N

R e c e iv e A C K
u n til tim e o u tY

A C K va lid

Y

N

N

fra m e _ rc tr >M A X _ F R A M E _ R E T R IE SY
TR A C _S TA TU S =N O _AC K

D a ta P e n d in g

NY
TRAC_STATU S =S U C C E S S _ D A T A _ P E N D IN G

TR A C _S TA TU S =SUCCESSTR AC _STATU S =C H A N N E L _ A C C E S S _ F A IL U R E

Is su e T R X 2 4 _ T X _ E N D in te rru p t

TRX_STATE = TX_AR ET_O N

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Overview
The implemented TX_ARET algorithm is shown in Figure 9-12 on page 57.
In TX_ARET mode, the radio transceiver first executes the CSMA-CA algorithm, as
defined by IEEE 802.15.4–2006, section 7.5.1.4, initiated by a transmit start event. If
the channel is IDLE a frame is transmitted from the Frame Buffer. If theacknowledgement frame is requested the radio transceiver additionally checks for an
ACK reply.
A TRX24_TX_END interrupt indicates the completion of the TX_ARET transmit
transaction.
Description
Configuration and address bits are to be set in TRX_OFF or PLL_ON state prior toswitching to TX_ARET mode. It is further recommended to transfer the PSDU data to
the Frame Buffer in advance. The transaction is started by either writing SLPTR=1 as
described in section "Transceiver Pin Register TRXPR" on page 32 or writing a
TX_START command to register TRX_STATE.
If the CSMA-CA detects a busy channel, it is retried as specified by bits
MAX_CSMA_RETRIES of register XAH_CTRL_0. In case that CSMA-CA does notdetect a clear channel after MAX_CSMA_RETRIES it aborts the TX_ARET transaction,issues a TRX24_TX_END interrupt and sets the value of the TRAC_STATUS register
bits to CHANNEL_ACCESS_FAILURE.
During transmission of a frame the radio transceiver parses bit 5 (ACK Request) of the
MAC header (MHR) frame control field of the PSDU data (PSDU octet #1) to betransmitted to check if an ACK reply is expected.
If an ACK is expected the radio transceiver automatically switches into receive mode to
wait for a valid ACK reply. After receiving an ACK frame the Frame Pending subfield ofthat frame is parsed and the status register bits TRAC_STATUS are updated
accordingly (see Table 9-16 below). This receive procedure does not overwrite theFrame Buffer content. Transmit data in the Frame Buffer is not changed during theentire TX_ARET transaction. Received frames other than the expected ACK frame are
discarded.
If no valid ACK is received or after timeout of 54 symbol periods (864 µs), the radiotransceiver retries the entire transaction (including CSMA-CA) until the maximum
number of retransmissions as set by the bits MAX_FRAME_RETRIES in register
XAH_CTRL_0 is exceeded.
After that, the microcontroller may read the value of the bits TRAC_STATUS of register
TRX_STATE to verify whether the transaction was successful or not. The register bits
are set according to the following cases:
Table 9-16. Interpretation of the TRAC_STATUS register bits
Value

58

Name

Description

0

SUCCESSThe transaction was responded by a valid
ACK, or, if no ACK is requested, after asuccessful frame transmission

1

SUCCESS_DATA_PENDING

Equivalent to SUCCESS; indicates pending
frame data according to the MHR frame
control field of the received ACK response

3

CHANNEL_ACCESS_FAILURE

Channel is still busy after
MAX_CSMA_RETRIES of CSMA-CA

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Value

Name

Description

5

NO_ACKNo acknowledgement frames were received
during all retry attempts

7

INVALIDEntering TX_ARET mode sets
TRAC_STATUS = 7

Note that if no ACK is expected (according to the content of the received frame in the
Frame Buffer), the radio transceiver issues a TRX24_TX_END interrupt directly after
the frame transmission has been completed. The value of the bits TRAC_STATUS ofregister TRX_STATE is set to SUCCESS.
A value of MAX_CSMA_RETRIES = 7 initiates an immediate TX_ARET transaction
without performing CSMA-CA. This is required to support slotted acknowledgement
operation. Further the value MAX_FRAME_RETRIES is ignored and the TX_ARET
transaction is performed only once.
A timing example of a TX_ARET transaction is shown in Figure 9-13 below .
Figure 9-13. Example Timing of a TX_ARET Transaction
128

FrameTypex

Data Frame (Length = 10, ACK=1)

TX_ARET_ON

RX/TX

ACK Frame

BUSY_TX_ARET

TX_ARET_ON
RX

TX

CSMA-CA

time [µs]

x+352

RX/TX

TRX_STATE

672

Frame
on Air

0

SLPTR
IRQ
Typ. Processing Delay

RX_ENDtCSM A-CA

16 µs

Note:

32 µs

tIRQ

1. tCSMA-CA defines the random CSMA-CA processing time.

Here an example data frame of length 10 with an ACK request is transmitted, see Table
9-13 on page 60. After the transmission the radio transceiver switches to receive modeand expects an acknowledgement response. During the whole transaction including
frame transmit, wait for ACK and ACK receive the radio transceiver status register
TRX_STATUS signals BUSY_TX_ARET.
A successful reception of the acknowledgment frame is indicated by the
TRX24_TX_END interrupt. The status register TRX_STATUS changes back to
TX_ARET_ON. The TX_ARET status register TRAC_STATUS changes as well to
TRAC_STATUS = SUCCESS or TRAC_STATUS = SUCCESS_DATA_PENDING if theframe pending subfield of the received ACK frame was set to 1.
9.4.2.6 Interrupt Handling
The interrupt handling in the Extended Operating Mode is similar to the Basic Operating
Mode (see section "Interrupt Handling" on page 38). The microcontroller enables
interrupts by setting the appropriate bit in register IRQ_MASK.
For RX_AACK and TX_ARET the following interrupts (Table 9-13 on page 60) inform
about the status of a frame reception and transmission:

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Table 9-13. Interrupt Handling in Extended Operating Mode
Mode

Interrupt

Description

RX_AACKTRX24_RX_START

Indicates a PHR reception

TRX24_AMI

Issued at address match

TRX24_RX_END

Signals completion of RX_AACK transaction if
successful- A received frame must pass the address filter;- The FCS is valid

TX_ARET

TRX24_TX_END

Signals completion of TX_ARET transaction

Both

TRX24_PLL_LOCKEntering RX_AACK_ON or TX_ARET_ON state from
TRX_OFF state, the TRX24_PLL_LOCK interrupt
signals that the transaction can be started

RX_AACKFor RX_AACK it is recommended to enable the TRX24_RX_END interrupt. This
interrupt is issued only if a frame passes the frame filtering (see section "Frame
Filtering" on page 54) and has a valid FCS. This is different to Basic Operating Mode(see section "Basic Operating Mode" on page 35). The use of the other interrupts is
optional.
On reception of a valid PHR a TRX24_RX_START interrupt is issued. The TRX24_AMI
interrupt indicates an address match (see filter rules in section "Frame Filtering" onpage 54). The completion of a frame reception with a valid FCS is indicated by the
TRX24_RX_END interrupt.
Thus it can happen that a TRX24_RX_START and/or a TRX24_AMI interrupt areissued, but no TRX24_RX_END interrupt.
The end of an acknowledgment transmission is confirmed by a TRX24_TX_END
interrupt.
TX_ARETIn TX_ARET interrupt TRX24_TX_END is only issued after completing the entire
TX_ARET transaction.
Acknowledgement frames do not issue a TRX24_RX_START, TRX24_AMI or a
TRX24_RX_END interrupt.
All other interrupts as described in section Table 9-2 on page 34 are also available in
Extended Operating Mode.
9.4.2.7 Register Summary
The following registers (Table 9-14 below) are to be configured to control the Extended
Operating Mode:
Table 9-14. Register Summary

60

Register Name

Description

TRX_STATUS

Radio transceiver status, CCA result

TRX_STATERadio transceiver state control, TX_ARET status

TRX_CTRL_1

TX_AUTO_CRC_ON

PHY_CC_CCA

CCA mode control, Table 9-21 on page 70

CCA_THRES

CCA threshold settings, see "Overview" on page 70

XAH_CTRL_1

RX_AACK control

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Register Name

Description

IEEE_ADDR7….
IEEE_ADDR0
PAN_ID1
PAN_ID0SHORT_ADDR1SHORT_ADDR0

Address filter configuration
Short address, PAN-ID and IEEE address

XAH_CTRL_0

TX_ARET control, retries value control

CSMA_SEED_0

CSMA-CA seed value

CSMA_SEED_1

CSMA-CA seed value, RX_AACK control

CSMA_BE

CSMA-CA back-off exponent control

9.5 Functional Description
9.5.1 Introduction – IEEE 802.15.4-2006 Frame Format
Figure 9-14 below provides an overview of the physical layer (PHY) frame structure as
defined by IEEE 802.15.4. Figure 9-15 on page 62 shows the frame structure of themedium access control (MAC) layer.
Figure 9-14. IEEE 802.15.4 Frame Format - PHY-Layer Frame Structure (PPDU)

9.5.1.1 PHY Protocol Layer Data Unit (PPDU)
9.5.1.1.1 Synchronization Header (SHR)
The SHR consists of a four-octet preamble field (all zero), followed by a single byte
start-of-frame delimiter (SFD) which has the predefined value 0xA7. During transmit,
the SHR is automatically generated by the radio transceiver, thus the Frame Buffer
shall contain PHR and PSDU only.
The transmission of the SHR requires 160 µs (10 symbols). As the frame buffer accessis normally faster than the over-air data rate, this allows the application software to
initiate a transmission without having transferred the full frame data already. Instead it ispossible to subsequently write the frame content.
During frame reception, the SHR is used for synchronization purposes. The matching
SFD determines the beginning of the PHR and the following PSDU payload data.
9.5.1.1.2 PHY Header (PHR)
The PHY header is a single octet following the SHR. The least significant 7 bits denotethe frame length of the following PSDU, while the most significant bit of that octet isreserved, and shall be set to 0 for IEEE 802.15.4 compliant frames.

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On receive the PHR is returned as the first octet during Frame Buffer read access.
Even though the standard only defines frame lengths ≤127 bytes, the radio transceiveris able to transmit and receive frame length values >127. For IEEE 802.15.4 compliant
operation bit 8 has to be masked by software. The reception of a valid PHR is signaled
by a TRX24_RX_START interrupt.
On transmit the PHR has to be written first to the Frame Buffer.
9.5.1.1.3 PHY Payload (PHY Service Data Unit, PSDU)The PSDU has a variable length between 0 and aMaxPHYPacketSize (127, maximum
PSDU size in octets) whereas the last two octets are used for the Frame Check
Sequence (FCS). The length of the PSDU is signaled by the frame length field (PHR)
as described in Table 9-15 below. The PSDU contains the MAC Protocol Layer Data
Unit (MPDU).
Received frames with a frame length field set to 0x00 (invalid PHR) are not by aninterrupt.
Table 9-15 below summarizes the type of payload versus the frame length value.
Table 9-15. Frame Length Field - PHR
Frame Length Value

Payload

0-4

Reserved

5

MPDU (Acknowledgement)

6–8

Reserved

9 - aMaxPHYPacketSize

MPDU

9.5.1.2 MAC Protocol Layer Data Unit (MPDU)
Figure 9-15 below shows the frame structure of the MAC layer.
Figure 9-15. IEEE 802.15.4 Frame Format - MAC-Layer Frame Structure (MPDU)

9.5.1.2.1 MAC Header (MHR) Fields
The MAC header consists of the Frame Control Field (FCF), a sequence number, andthe addressing fields (which are of variable length and can even be empty in certain
situations).

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9.5.1.2.2 Frame Control Field (FCF)
The FCF consists of 16 bits, and occupies the first two octets of either the MPDU or the
PSDU, respectively.
Figure 9-26. IEEE 802.15.4-2006 Frame Control Field (FCF)

Bit [2:0]: describe the frame type. Table 9-16 below summarizes frame types definedby IEEE 802.15.4, section 7.2.1.1.1.
Table 9-16. Frame Control Field – Frame Type Subfield
Frame Control Field Bit Assignments

Description

Frame Type Valueb2 b1 b0

Value

000

0

Beacon

001

1

Data

010

2

Acknowledge

011

3

MAC command

100 – 111

4–7

Reserved

This subfield is used for address filtering by the third level filter rules. Only frame types
0 – 3 pass the third level filter rules (refer to section "Frame Filtering" on page 54).
Automatic address filtering of the radio transceiver is enabled when using the
RX_AACK mode (refer to "RX_AACK_ON – Receive with Automatic ACK" on page 46).
A reserved frame (frame type value > 3) can be received if bit AACK_UPLD_RES_FT ofregister XAH_CTRL_1 is set. For details refer to chapter "Configuration of non IEEE
802.15.4 Compliant Scenarios" on page 52. Address filtering is also provided in BasicOperating Mode as explained in "Basic Operating Mode" on page 35.
Bit 3: indicates whether security processing applies to this frame.
Bit 4: is the “Frame Pending” subfield. This field can be set in an acknowledgment
frame (ACK) in response to a data request MAC command frame. This bit indicates thatthe node, which transmitted the ACK, has more data to send to the node receiving the
ACK.
For acknowledgment frames automatically generated by the radio transceiver, this bit isset according to the content of bit AACK_SET_PD of register CSMA_SEED_1 if thereceived frame was a data request MAC command frame.
Bit 5: forms the “Acknowledgment Request” subfield. If this bit is set within a data or
MAC command frame that is not broadcast, the recipient shall acknowledge thereception of the frame within the time specified by IEEE 802.15.4 (i.e. within 192 µs fornon beacon-enabled networks).
The radio transceiver parses this bit during RX_AACK mode and transmits an
acknowledgment frame if necessary.
In TX_ARET mode this bit indicates if an acknowledgement frame is expected after
transmitting a frame. If this is the case, the receiver waits for the acknowledgment
frame, otherwise the TX_ARET transaction is finished.

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Bit 6: the “Intra-PAN” subfield indicates that in a frame, where both, the destination andsource addresses are present, the PAN-ID of the source address filed is omitted. In
RX_AACK mode this bit is evaluated by the address filter logic of the radio transceiver.
Bit [11:10]: the “Destination Addressing Mode” subfield describes the format of thedestination address of the frame. The values of the address modes are summarized inTable 9-17 below according to IEEE 802.15.4:
Table 9-17. Frame Control Field – Destination and Source Addressing Mode
Frame Control Field Bit Assignments

Description

Addressing Modeb11 b10b15 b14

Value

00

0

PAN identifier and address fields are not present

011Reserved

102Address field contains a 16-bit short address

113Address field contains a 64-bit extended address

If the destination address mode is either 2 or 3 (i.e. if the destination address ispresent), it always consists of a 16-bit PAN-ID first followed by either the 16-bit or 64-bit
address as defined by the mode.
Bit [13:12]: the “Frame Version” subfield specifies the version number corresponding to
the frame. These register bits are reserved in IEEE-802.15.4-2003.
This subfield shall be set to 0 to indicate a frame compatible with IEEE 802.15.4-2003
and 1 to indicate an IEEE 802.15.4-2006 frame. All other subfield values shall bereserved for future use.
The bit AACK_FVN_MODE of register CSMA_SEED_1 controls the RX_AACK
behavior of frame acknowledgements. This register determines if, depending on the
Frame Version Number, a frame is acknowledged or not. This is necessary forbackward compatibility to IEEE 802.15.4-2003 and for future use. Even if frame version
numbers 2 and 3 are reserved, it can be handled by the radio transceiver. For details
refer to "CSMA_SEED_1 – Transceiver Acknowledgment Frame Control Register 2" onpage 129.
See IEEE 802.15.4-2006, section 7.2.3 for details on frame compatibility.
Table 9-18. Frame Control Field – Frame Version Subfield
Frame Control Field Bit Assignments

Description

Frame Version
b13 b12

Value

00

0

Frames are compatible with IEEE 802.15.4-2003

01

1

Frames are compatible with IEEE 802.15.4-2006

10

2

Reserved

11

3

Reserved

Bit [15:14]: the “Source Addressing Mode” subfield, with similar meaning as“Destination Addressing Mode” (refer to Table 9-17 above).
The subfields of the FCF (Bits 0–2, 3, 6, 10–15) affect the address filter logic of theradio transceiver while executing a RX_AACK operation (see "RX_AACK_ON –Receive with Automatic ACK" on page 46).

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ATmega128RFA1
9.5.1.2.3 Frame Compatibility between IEEE 802.15.4-2003 and IEEE 802.15.4-2006
All unsecured frames according to IEEE 802.15.4-2006 are compatible with unsecured
frames compliant with IEEE 802.15.4-2003 with two exceptions: a coordinatorrealignment command frame with the “Channel Page” field present (see IEEE 802.15.42006 7.3.8) and any frame with a MAC Payload field larger thanaMaxMACSafePayloadSize octets.
Compatibility for secured frames is shown in the following table, which identifies the
security operating modes for IEEE 802.15.4-2006.
Table 9-19. Frame Control Field – Security and Frame Version
Frame Control Field Bit Assignments

Description

Security Enabledb3

Frame Version
b13 b12000

No security. Frames are compatible between
IEEE 802.15.4-2003 and IEEE 802.15.4-2006.

001

No security. Frames are not compatible between
IEEE 802.15.4-2003 and IEEE 802.15.4-2006.

100

Secured frame formatted according toIEEE 802.15.4-2003. This frame type is notsupported in IEEE 802.15.4-2006.

1

01

Secured frame formatted according toIEEE 802.15.4-2006

9.5.1.2.4 Sequence Number
The one-octet sequence number following the FCF identifies a particular frame, so that
duplicated frame transmissions can be detected. While operating in RX_AACK mode,the content of this field is copied from the frame to be acknowledged into theacknowledgment frame.
9.5.1.2.5 Addressing Fields
The addressing fields of the MPDU are used by the radio transceiver for address
matching indication. The destination address (if present) is always first, followed by thesource address (if present). Each address field consists of the Intra PAN-ID and a
device address. If both addresses are present and the “Intra PAN-ID compression”
subfield in the FCF is set to one, the source Intra PAN-ID is omitted.
Note that in addition to these general rules IEEE 802.15.4 further restricts the valid
address combinations for the individual possible MAC frame types. For example thesituation where both addresses are omitted (source addressing mode = 0 anddestination addressing mode = 0) is only allowed for acknowledgment frames. The
address filter in the radio transceiver has been designed to apply to IEEE 802.15.4
compliant frames. It can be configured to handle other frame formats and exceptions.
9.5.1.2.6 Auxiliary Security Header Field
The Auxiliary Security Header specifies information required for security processing andhas a variable length. This field determines how the frame is actually protected (security
level) and which keying material from the MAC security PIB is used (seeIEEE 802.15.4-2006, 7.6.1). This field shall be present only if the Security Enabled

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subfield b3 is set to one (see section "Frame Compatibility between IEEE 802.15.42003 and IEEE 802.15.4-2006" on page 65). For details of its structure see
IEEE 802.15.4-2006, 7.6.2 Auxiliary security header.
9.5.1.2.7 MAC Service Data Unit (MSDU)
This is the actual MAC payload. It is usually structured according to the individual frame
type. A description can be found in IEEE 802.15.4-2006, chapter 5.5.3.2.
9.5.1.2.8 MAC Footer (MFR) Fields
The MAC footer consists of a two-octet Frame Checksum (FCS). For details refer to thefollowing section "Frame Check Sequence (FCS)" below.
9.5.2 Frame Check Sequence (FCS)The Frame Check Sequence (FCS) is characterized by:• Indicate bit errors based on a cyclic redundancy check (CRC) of 16 bit length;• Uses International Telecommunication Union (ITU) CRC polynomial;• Automatically evaluated during reception;• Can be automatically generated during transmission.
9.5.2.1 Overview
The FCS is intended for use at the MAC layer to detect corrupted frames at a first levelof filtering. It is computed by applying an ITU CRC polynomial to all transferred bytes
following the length field (MHR and MSDU fields). The frame check sequence has alength of 16 bit and is located in the last two bytes of a frame (MAC footer, see Figure
9-15 on page 62).
The radio transceiver applies an FCS check on each received frame. The result of the
FCS check is stored in bit RX_CRC_VALID of register PHY_RSSI.
On transmit the radio transceiver generates and appends the FCS bytes during theframe transmission. This behavior can be disabled by setting the bit
TX_AUTO_CRC_ON = 0 in register TRX_CTRL_1.
9.5.2.2 CRC calculation
The CRC polynomial used in IEEE 802.15.4 networks is defined by

G16 ( x ) = x 16 + x 12 + x 5 + 1
The FCS shall be calculated for transmission using the following algorithm:Let

M ( x) = b0 x k −1 + b1 x k − 2 + K + bk − 2 x + bk −1
be the polynomial representing the sequence of bits for which the checksum is to be
16
computed. Multiply M(x) by x giving the polynomial

N ( x) = M ( x) ⋅ x16
Divide N (x ) modulo 2 by the generator polynomial G16(x) to obtain the remainder
polynomial

R ( x ) = r0 x 15 + r1 x 14 + ... + r14 x + r15
The FCS field is given by the coefficients of the remainder polynomial, R(x).
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ATmega128RFA1Example:Consider a 5 octet ACK frame. The MHR field consists of0100 0000 0000 0000 0101 0110.
The leftmost bit (b0) is transmitted first in time. The FCS is in this case0010 0111 1001 1110.
The leftmost bit (r0) is transmitted first in time.
9.5.2.3 Automatic FCS generation
The automatic FCS generation is performed with register bit TX_AUTO_CRC_ON = 1(reset value). This allows the radio transceiver to autonomously compute the FCS. Fora frame with a frame length specified as N (3 ≤ N ≤ 127), the FCS is calculated on thefirst N-2 octets in the Frame Buffer and the resulting FCS field is transmitted in place ofthe last two octets from the Frame Buffer.
If the automatic FCS generation of the radio transceivers is enabled, the Frame Buffer
write access can be stopped right after MAC payload. There is no need to write FCS
dummy bytes.
In RX_AACK mode, when a received frame needs to be acknowledged, the FCS of the
ACK frame is always automatically generated by the radio transceiver, independent of
the TX_AUTO_CRC_ON setting.
Example:A frame transmission of length five with TX_AUTO_CRC_ON set, is started with a
Frame Buffer write access of five bytes (the last two bytes can be omitted). The first
three bytes are used for FCS generation; the last two bytes are replaced by theinternally calculated FCS.
9.5.2.4 Automatic FCS check
An automatic FCS check is applied on each received frame with a frame length N ≥ 2.
The bit RX_CRC_VALID of register PHY_RSSI is set if the FCS of a received frame isvalid. The register bit is updated when issuing a TRX24_RX_END interrupt and remains
valid until a new frame reception causes the next TRX24_RX_END interrupt.
In RX_AACK mode, the radio transceiver rejects the frame and the TRX24_RX_END
interrupt is not issued if the FCS of the received frame is not valid.
In TX_ARET mode, the FCS and the sequence number of an ACK are automaticallychecked. The ACK is not accepted if one of those is not correct.
9.5.3 Received Signal Strength Indicator (RSSI)The Received Signal Strength Indicator is characterized by:• Minimum RSSI level is -90 dBm (RSSI_BASE_VAL);• Dynamic range is 81 dB;• Minimum RSSI value is 0;• Maximum RSSI value is 28.
9.5.3.1 Overview
The RSSI is a 5-bit value indicating the receive power in the selected channel in stepsof 3 dB. No attempt is made to distinguish IEEE 802.15.4 signals from others. Only the67
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received signal strength is evaluated. The RSSI provides the basis for an ED
measurement. See section "Energy Detection (ED)" below for details.
9.5.3.2 Reading RSSIIn Basic Operating Mode the RSSI value is valid in any receive state, and is updated
every tTR25 = 2 µs to register PHY_RSSI.
It is not recommended to read the RSSI value when using the Extended Operating
Mode. The automatically generated ED value should then be used (see section "Energy
Detection (ED)" below).
9.5.3.3 Data Interpretation
The RSSI value is a 5-bit value indicating the receive power in steps of 3 dB and with arange of 0- 28.
An RSSI value of 0 indicates a receiver RF input power of PRF < -90 dBm. For an RSSI
value in the range of 1 to 28, the RF input power can be calculated as follows:
PRF = RSSI_BASE_VAL + 3 • (RSSI - 1) [dBm]
Figure 9-17. Mapping between RSSI Value and Received Input Power
10

Receiver Input Power P RF [dBm]0

Measured

-10

Ideal

-20
-30
-40
-50
-60
-70
-80
-90
-100
0

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

RSSI

9.5.4 Energy Detection (ED)The Energy Detection (ED) module is characterized by:• 85 unique energy levels defined;• 1 dB resolution.
9.5.4.1 Overview
The receiver ED measurement is used by the network layer as part of a channel
selection algorithm. It is an estimation of the received signal power within the bandwidthof an IEEE 802.15.4 channel. No attempt is made to identify or decode signals on thechannel. The ED value is calculated by averaging RSSI values over eight symbols(128 µs).
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ATmega128RFA1For High Data Rate Modes the automated ED measurement duration is reduced to
32 µs as described in "High Data Rate Modes" on page 86. The measurement period inthese modes is still 128 µs for manually initiated ED measurements as long as thereceiver is in RX_ON state.
9.5.4.2 Measurement Description
There are two ways to initiate an ED measurement:• Manually, by writing an arbitrary value to register PHY_ED_LEVEL, or• Automatically, after detection of a valid SHR of an incoming frame.
For manually initiated ED measurements the radio transceiver needs to be in one of thestates RX_ON or BUSY_RX. The end of the ED measurement is indicated by a
TRX24_CCA_ED_DONE interrupt.
The automatic ED measurement is started if a SHR is detected. The end of theautomatic measurement is not signaled by an interrupt.
The measurement result is stored after tTR26 = 140 µs (128 µs measurement durationand processing delay) in register PHY_ED_LEVEL.
Thus by using Basic Operating Mode a valid ED value from the currently received frameis accessible 108 µs after the TRX24_RX_START interrupt and remains valid until thenext incoming frame generates a new TRX24_RX_START interrupt or until another ED
measurement is initiated.
When using the Extended Operating Mode it is recommended to mask the
TRX24_RX_START interrupt. Hence the interrupt cannot be used as timing reference.
A successful frame reception is signalized by the TRX24_RX_END interrupt. The
minimum time span between a TRX24_RX_END interrupt and a following SFD
detection is tTR27 = 96 µs due to the length of the SHR. The ED value needs to be read
within 224 µs including the ED measurement time after the TRX24_RX_END interrupt.
Otherwise it could be overwritten by the result of the next measurement cycle. This isimportant for time critical applications or if the TRX24_RX_START interrupt is not used
to indicate the reception of a frame.
The values of the register PHY_ED_LEVEL are:Table 9-20. Register Bit PHY_ED_LEVEL Interpretation
PHY_ED_LEVEL

Description

0xFF

Reset value

0x00 … 0x54
Note:

ED measurement result of the last ED measurement

1. It is not recommended to manually initiate an ED measurement when using the
Extended Operating Mode.

9.5.4.3 Data Interpretation
The PHY_ED_LEVEL is an 8-bit register. The ED value of the radio transceiver has avalid range from 0x00 to 0x54 with a resolution of 1 dB. All other values do not occur. A
value of 0xFF indicates the reset value. A value of PHY_ED_LEVEL = 0 indicates thatthe measured energy is less than -90 dBm (see parameter RSSI_BASE_VAL in section"Receiver Characteristics" on page 508). Due to environmental conditions (temperature,
voltage, semiconductor parameters etc.) the calculated ED value has a maximum
tolerance of ±5 dB, this is to be considered as constant offset over the measurement
range.
An ED value of 0 indicates an RF input power of PRF ≤ -90 dBm. For an ED value in therange of 0 to 84, the RF input power can be calculated as follows:
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PRF = -90 + ED [dBm]
Figure 9-18. Mapping between values in PHY_ED_LEVEL and Received Input Power
10

Receiver Input Power P RF [dBm]0

Measured

-10

Ideal

-20
-30
-40
-50
-60
-70
-80
-90
-100
0

10

20

30

40

50

60

70

80

90

Register PHY_ED_LEVEL Value

9.5.4.4 Interrupt Handling
The TRX24_CCA_ED_DONE interrupt is issued at the end of a manually initiated ED
measurement.
Note that an ED request should only be initiated in one of the receive states. Otherwise
the radio transceiver generates a TRX24_CCA_ED_DONE interrupt but no ED
measurement was performed.
9.5.5 Clear Channel Assessment (CCA)
The main features of the Clear Channel Assessment (CCA) module are:• All 4 modes are available as defined by IEEE 802.15.4-2006 in section 6.9.9;• Adjustable threshold for energy detection algorithm.
9.5.5.1 Overview
A CCA measurement is used to detect a clear channel. Four modes are specified byIEEE 802.15.4-2006:
Table 9-21. CCA Mode Overview
CCA Mode70

Description

1

Energy above threshold.
CCA shall report a busy medium upon detecting any energy above the ED
threshold.

2

Carrier sense only.
CCA shall report a busy medium only upon the detection of a signal with themodulation and spreading characteristics of an IEEE 802.15.4 compliant signal.
The signal strength may be above or below the ED threshold.

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ATmega128RFA1
CCA Mode0, 3Description
Carrier sense with energy above threshold.
CCA shall report a busy medium using a logical combination of- Detection of a signal with the modulation and spreading characteristics ofthis standard and- Energy above the ED threshold.
Where the logical operator may be configured as either OR (mode 0) orAND (mode 3).

9.5.5.2 Configuration and CCA Request
The CCA modes are configurable via register PHY_CC_CCA.
Usimg the Basic Operating Mode, a CCA request can be initiated manually by setting
CCA_REQUEST = 1 of register PHY_CC_CCA, if the radio transceiver is in any RX
state. The current channel status (CCA_STATUS) and the CCA completion status(CCA_DONE) are accessible in register TRX_STATUS.
The CCA evaluation is done over eight symbol periods and the result is accessible
tTR28 = 140 µs (128 µs measurement duration and processing delay) after the request.
The end of a manually initiated CCA measurement is indicated by a
TRX24_CCA_ED_DONE interrupt.
The sub-register CCA_ED_THRES of register CCA_THRES defines the received power
threshold of the “energy above threshold” algorithm. The threshold is calculated by
RSSI_BASE_VAL + 2 • CCA_ED_THRES [dBm]. Any received power above this levelis interpreted as a busy channel.
Note that it is not recommended to manually initiate a CCA measurement when using
the Extended Operating Mode.
9.5.5.3 Data Interpretation
The current channel status (CCA_STATUS) and the CCA completion status(CCA_DONE) are accessible in register TRX_STATUS. Note, register bits CCA_DONE
and CCA_STATUS are cleared in response to a CCA_REQUEST.
The completion of a measurement cycle is indicated by CCA_DONE = 1. If the radiotransceiver detected no signal (idle channel) during the measurement cycle, the
CCA_STATUS bit is set to 1.
When using the “energy above threshold” algorithm, any received power above
CCA_ED_THRES level is interpreted as a busy channel. The “carrier sense” algorithm
reports a busy channel when detecting an IEEE 802.15.4 signal above the
RSSI_BASE_VAL (see parameter RSSI_BASE_VAL in "Transceiver Electrical
Characteristics" on page 507). The radio transceiver is also able to detect signals below
this value, but the detection probability decreases with the signal power.
9.5.5.4 Interrupt Handling
The TRX24_CCA_ED_DONE interrupt is issued at the end of a manually initiated CCA
measurement.
Note:

A CCA request should only be initiated in the receive states of Basic Operating Mode.
Otherwise the radio transceiver generates a TRX24_CCA_ED_DONE interrupt andsets the register bit CCA_DONE = 1 even if no CCA measurement was performed.

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9.5.5.5 Measurement TimeThe response time for a manually initiated CCA measurement depends on the receiverstate.
In RX_ON state the CCA measurement is done over eight symbol periods and theresult is accessible 140 µs after the request (see section "Configuration and CCA
Request" on page 71).
In BUSY_RX state the CCA measurement duration depends on the CCA Mode and the
CCA request relative to the reception of an SHR. The end of the CCA measurement isindicated by a TRX24_CCA_ED_DONE interrupt. The variation of a CCA measurement
period in BUSY_RX state is described in Table 9-22 below.
Table 9-22. CCA Measurement Period and Access in BUSY_RX state
CCA Mode1

Request within ED measurement(1)

Request after ED measurement

Energy above threshold.
CCA result is available after finishingautomated ED measurement period.

2

CCA result is immediately available
after request.

Carrier sense only.
CCA result is immediately available after request.

3

Carrier sense with Energy above threshold (AND).
CCA result is available after finishingautomated ED measurement period.

0Carrier sense with Energy above threshold (OR).
CCA result is available after finishingautomated ED measurement period.

Note:

CCA result is immediately available
after request.
CCA result is immediately available
after request.

1. After receiving the SHR an automated ED measurement is started with a length of
8 symbol periods (PSDU rate 250 kb/s), refer to section "Energy Detection (ED)"on page 68. This automated ED measurement must be finished to provide a result
for the CCA measurement. Only one automated ED measurement per frame isperformed.

It is recommended to perform CCA measurements in RX_ON state only. To avoid
accidental switching to BUSY_RX state the SHR detection can be disabled by setting
bit RX_PDT_DIS of register RX_SYN. Refer to section "Receiver (RX)" on page 74 fordetails. The receiver remains in RX_ON state to perform a CCA measurement until theregister bit RX_PDT_DIS is set back to continue the frame reception. In this case the
CCA measurement duration is 8 symbol periods.
9.5.6 Link Quality Indication (LQI)
According to IEEE 802.15.4 the LQI measurement is a characterization of the strength
and/or quality of a received packet. The measurement may be implemented using
receiver ED, a signal-to-noise ratio estimation or a combination of these methods. The
use of the LQI result by the network or application layers is not specified in thisstandard. LQI values shall be an integer ranging from 0x00 to 0xFF. The minimum andmaximum LQI values (0x00 and 0xFF) should be associated with the lowest andhighest quality compliant signals, respectively, and LQI values in between should be
uniformly distributed between these two limits.
9.5.6.1 Overview
The LQI measurement of the radio transceiver is implemented as a measure of the linkquality which can be described with the packet error rate (PER) of this link. A LQI value

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ATmega128RFA1
can be associated with an expected packet error rate. The PER is the ratio of erroneousreceived frames to the total number of received frames. A PER of zero indicates noframe error whereas at a PER of one no frame was received correctly.
The radio transceiver uses correlation results of multiple symbols within a frame todetermine the LQI value. This is done for each received frame. The minimum frame
length for a valid LQI value is two octets PSDU. LQI values are integers ranging from 0
to 255.
The following figure shows an example of a conditional packet error rate when receiving
a certain LQI value.
Figure 9-19. Conditional Packet Error Rate versus LQI
1
0.9
0.8
0.7

PER

0.6
0.5
0.4
0.3
0.2
0.1
0
0

50

100

150

200

250

LQI

The values are taken from received frames of PSDU length of 20 octets ontransmission channels with reasonable low multipath delay spreads. If the transmission
channel characteristic has a higher multipath delay spread than assumed in theexample, the PER is slightly higher for a certain LQI value. Since the packet error rate
is a statistical value, the PER shown in Figure 9-19 above is based on a huge numberof transactions. A reliable estimation of the packet error rate cannot be based on asingle or a small number of LQI values.
9.5.6.2 Request a LQI Measurement
The LQI byte can be obtained after a frame has been received by the radio transceiver.
One additional byte is automatically attached to the received frame containing the LQI
value. This information can also be read via Frame Buffer read access, see "Useraccessible Frame Content" on page 78. The LQI byte can be read after the
TRX24_RX_END interrupt.
9.5.6.3 Data Interpretation
According to IEEE 802.15.4 a low LQI value is associated with low signal strength
and/or high signal distortions. Signal distortions are mainly caused by interference
signals and/or multipath propagation. High LQI values indicate a sufficient high signal
power and low signal distortions.
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Note that the received signal power as indicated by the received signal strength
indication (RSSI) value or energy detection (ED) value of the radio transceiver do notcharacterize the signal quality and the ability to decode a signal.
As an example, a received signal with an input power of about 6 dB above the receiversensitivity likely results in a LQI value close to 255 for radio channels with very low
signal distortions. For higher signal power the LQI value becomes independent of theactual signal strength. This is because the packet error rate for these scenarios tends
towards zero and further increased signal strength i.e. increasing the transmission
power does not decrease the error rate any further. In this case RSSI or ED can beused to evaluate the signal strength and the link margin.
ZigBee networks often require the identification of the “best” routing between two
nodes. Both the LQI and the RSSI/ED can be used for this, dependent on the
optimization criteria. If a low packet error rate (corresponding to high throughput) is the
optimization criteria then the LQI value should be taken into consideration. If a lowtransmission power or the link margin is the optimization criteria then the RSSI/ED
value is also helpful.
Combinations of LQI, RSSI and ED are possible for routing decisions. As a rule ofthumb RSSI and ED values are useful to differentiate between links with high LQI
values. Transmission links with low LQI values should be discarded for routing
decisions even if the RSSI/ED values are high. This is because RSSI and ED do not
say anything about the possibility to decode a signal. It is only an information about thereceived signal strength whereas the source can be an interferer.

9.6 Module Description
9.6.1 Receiver (RX)9.6.1.1 Overview
The receiver is split into an analog radio front-end and a digital base band processor(RX BBP) according to the following figure. The digital base band processor and thecontrol engine are connected to the Frame Buffer and control registers which arelocated in the microcontroller I/O memory space (see "I/O Memory" on page 25 and"Transceiver to Microcontroller Interface" on page 31 ).
Figure 9-20. Receiver Block Diagram
Analog D om ainLO

D igital D om ain

I/O
M em ory
Space

R FP
LN A

PPF

BPF

Lim iter

RX
ADC

µC
I/F
$01FF

RX BBP

R FN

Fram eBuffer
$0180
$017F

AG C

R SSI

C ontrolRegisters$0140

The differential RF signal is amplified by a low noise amplifier (LNA), filtered (PPF) anddown converted to an intermediate frequency by a mixer. Channel selectivity is
performed using an integrated band pass filter (BPF). A limiting amplifier (Limiter)
provides sufficient gain to overcome the DC offset of the succeeding analog-to-digital

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ATmega128RFA1
converter (RX ADC) and generates a digital RSSI signal. The ADC output signal issampled and processed further by the digital base band receiver (RX BBP).
The RX BBP performs additional signal filtering and signal synchronization. The
frequency offset of each frame is calculated by the synchronization unit and is usedduring the remaining receive process to correct the offset. The receiver is designed tohandle frequency and symbol rate deviations up to ±120 ppm caused by combined
receiver and transmitter deviations. For details refer to chapter "General RF
Specifications" on page 507. Finally the signal is demodulated and the data are stored
in the Frame Buffer.
In Basic Operating Mode (see "Basic Operating Mode" on page 35), the reception of aframe is indicated by a TRX24_RX_START interrupt. Accordingly its end is signalized
by a TRX24_RX_END interrupt. Based on the quality of the received signal a linkquality indicator (LQI) is calculated and appended to the frame. For details refer to.
Additional signal processing is applied to the frame data to provide further status
information like ED value (register PHY_ED_LEVEL) and FCS correctness (register
PHY_RSSI).
Beyond these features the Extended Operating Mode of the radio transceiver supports
address filtering and pending data indication. For details refer to "Extended Operating
Mode" on page 43.
9.6.1.2 Frame Receive Procedure
The frame receive procedure including the radio s setup for reception and reading
PSDU data from the Frame Buffer is described in "Frame Receive Procedure" on page84.
9.6.1.3 Configuration
In Basic Operating Mode the receiver is enabled by writing command RX_ON to the
TRX_CMD bits of register TRX_STATE in the states TRX_OFF or PLL_ON. Similarly in
Extended Operating Mode the receiver is enabled for RX_AACK operation from thestates TRX_OFF or PLL_ON by writing the command RX_AACK_ON. There is no
additional configuration required to receive IEEE 802.15.4 compliant frames when using
the Basic Operating Mode. However, the frame reception in the Extended Operating
Mode requires further register configurations. For details refer to "Extended Operating
Mode" on page 43.
The receiver has an outstanding sensitivity performance of -100 dBm. At certain
environmental conditions or for High Data Rate Modes (see "High Data Rate Modes" onpage 86) it may be useful to manually decrease this sensitivity. This is achieved byadjusting the detector threshold of the synchronization header using the
RX_PDT_LEVEL bits of register RX_SYN. Received signals with a RSSI value below
the threshold do not activate the demodulation process.
Furthermore, it may be useful to protect a received frame against overwriting by
subsequent received frames.
A Dynamic Frame Buffer Protection is enabled with register bit RX_SAFE_MODE(TRX_CTRL_2) set (refer to "Dynamic Frame Buffer Protection" on page 91). After aframe has been received, the buffer is protected for new incoming frames and thereceiver remains in RX_ON or RX_AACK_ON state until the RX_SAFE_MODE bit iscleared by the controller. The Frame Buffer content is only protected if the FCS is valid.
A Static Frame Buffer Protection is enabled with bit RX_PDT_DIS of register RX_SYN
set. The receiver remains in RX_ON or RX_AACK_ON state and no further SHR is
detected until the register bit RX_PDT_DIS is set back.
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9.6.2 Transmitter (TX)
9.6.2.1 Overview
The transmitter consists of a digital base band processor (TX BBP) and an analog front
end as shown in the following figure.
Figure 9-21. Transmitter Block Diagram$0140

Ext. R F front-end andOutput Power C ontrol

D IG3/4

ControlR egisters
$017F
$0180

R FP
PA

Buf

PLL – TX M odulation

R FN

TX D ata

Analog D om ain

TX BBP

Fram eBuffer

D igital Dom ain

I/O
M em ory
Space

$01FF
µC
I/F

The TX BBP reads the frame data from the Frame Buffer and performs the bit-tosymbol and symbol-to-chip mapping as specified by IEEE 802.15.4 in section 6.5.2.
The O-QPSK modulation signal is generated and fed into the analog radio front end.
The fractional-N frequency synthesizer (PLL) converts the baseband transmit signal to
the RF signal which is amplified by the power amplifier (PA). The PA output is internallyconnected to bidirectional differential antenna pins (RFP, RFN) so that no externalantenna switch is needed.
9.6.2.2 Frame Transmit Procedure
The frame transmit procedure including writing PSDU data in the Frame Buffer andinitiating a transmission is described in section "Frame Transmit Procedure" on page
84. The controller must ensure to provide valid frame data before starting the frametransmission. For save operation, it is recommended to write the complete frame into
the Frame Buffer before starting the frame transmission.
9.6.2.3 Configuration
The maximum output power of the transmitter is typically +3.5 dBm. The output power
can be configured via the TX_PWR bits of register PHY_TX_PWR. The output power of
the transmitter can be controlled over a 20 dB range.
A transmission can be started from PLL_ON or TX_ARET_ON state by writing ‘1’ to bit
SLPTR of the TRXPR register or by writing TX_START command to the TRX_CMD bitsof register TRX_STATE.
9.6.2.4 TX Power Ramping
The PA buffer and PA are enabled sequentially to optimize the output power spectral
density (PSD). A timing example using default settings illustrates the sequence in thenext figure. In this example the transmission is initiated with the rising edge of the
SLPTR bit. The radio transceiver state changes from PLL_ON to BUSY_TX. The
modulation starts 16 µs after SLPTR.

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Figure 9-22. TX Power Ramping
0

TRX_STATEPLL_O N

2

4

6

8

10

12

14

16

18

Length [µ s]

BU SY_TX

SLPTR
PA buffer

PA_BUF_LT
PA_LT

PA

1

M odulation

1 0

1

1 0 0 1

1

When using an external RF front-end (refer to "RX/TX Indicator" on page 90) it may berequired to adjust the startup time of the external PA relative to the internal building
blocks to optimize the overall PSD. This can be achieved using register bits
PA_BUF_LT and PA_LT of register PHY_TX_PWR.
9.6.3 Frame Buffer
The radio transceiver contains a 128 byte dual port SRAM. One port of the frame buffer
is directly connected to the controller I/O space. Therefore random access to single
frame bytes is possible. The other port connects to the internal transmitter and receivermodules. Both ports are independent and simultaneously accessible for data
communication.
The Frame Buffer uses the controller I/O address space 0x180 to 0x1FF for RX and TX
operation of the radio transceiver and can keep one IEEE 802.15.4 RX or one TX frameof maximum length at a time.
Frame Buffer access is only possible if the radio transceiver is enabled (PRTRX24 bit in
the Power Reduction Register PRR1 is not set) and not in SLEEP state.
9.6.3.1 Data Management
Data in the Frame Buffer (received data or data to be transmitted) remain valid as longas:
• No new frame or other data are written into the buffer;• No new frame is received (in any BUSY_RX state);• No state change into radio transceiver SLEEP state is made;• No radio transceiver RESET (see bit TRXRST in "TRXPR – Transceiver Pin
Register" on page 169) or system reset took place;• Bit PRTRX24 in register "PRR1 – Power Reduction Register 1" on page 168 is notset;
By default there is no protection of the Frame Buffer against overwriting. If a frame isreceived during a Frame Buffer read access of a previously received frame, the stored
data might be overwritten.
Finally the application software should check the transferred frame data integrity by a
FCS check.
The state of the radio transceiver should be changed to PLL_ON state after reception toprotect the Frame Buffer content against overwriting with new, incoming frames. Thiscan be achieved by writing immediately the command PLL_ON to the TRX_CMD bits ofregister TRX_STATE after receiving the frame indicated by a TRX24_RX_END
interrupt.

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Alternatively Dynamic Frame Buffer Protection can be used to protect received frames
against overwriting. For details refer to "Dynamic Frame Buffer Protection" on page 91.
Both procedures do not protect the Frame Buffer from overwriting by the application
software.
In Extended Operating Mode during TX_ARET operation (see "TX_ARET_ON –Transmit with Automatic Retry and CSMA-CA Retry" on page 57) the radio transceiverswitches to receive if an acknowledgement of a previously transmitted frame wasrequested. During this period received frames are evaluated but not stored in the Frame
Buffer. This allows the radio transceiver to wait for an acknowledgement frame andretry the frame transmission without writing the frame data to the Frame Buffer again.
A radio transceiver state change except a transition to radio transceiver SLEEP state ora radio transceiver RESET does not affect the Frame Buffer content. The Frame Buffer
is powered off and the stored data gets lost if the radio transceiver is forced into radiotransceiver SLEEP state.
Access conflicts may occur when reading and writing data simultaneously at the two
independent ports of the Frame Buffer TX/RX BBP and Controller interface.
9.6.3.2 User accessible Frame Content
The radio transceiver supports an IEEE 802.15.4 compliant frame format as shown in
the following figure.
Figure 9-31. Transceiver Frame Structure0

Length [octets]

4

5

Frame

Preamble Sequence

SFD

Duration

4 octets / 128 µs

1AccessSHR not accesible
PHY generated

6

PHR (1)y+3Payloady+5FCSy octets / y • 32 µs (y <= 128)

y+6

LQI(2)1

TX: Frame Buffer content
RX: Frame Buffer content

Notes:

1. Stored into Frame Buffer for TX operation
2. Stored into Frame Buffer during frame reception.

A frame comprises two sections. The radio transceiver internally generated SHR field
and the user accessible part are stored in the Frame Buffer. The SHR contains thepreamble and the SFD field. The variable frame section contains the PHR and the
PSDU including the FCS (see "Overview" on page 66).
The Frame Buffer content differs depending on the direction of the communication(receive or transmit). To access the data follow the procedures described in "Radio
Transceiver Usage" on page 83.
During frame reception, the payload and the link quality indicator (LQI) value of a
successfully received frame are stored in the Frame Buffer. The radio transceiverappends the LQI value to the frame data after the last received octet. Information of theframe length is not stored in the Frame Buffer. The frame length information is locatedin register TST_RX_LENGTH.
The SHR (except the SFD used to generate the last octet of the SHR) can generally not
be read by the application software.

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The PHR and the PSDU need to be stored in the Frame Buffer for frame transmission.
The PHR byte is the first byte in the Frame Buffer (address 0x180) and must be
calculated based on the PHR and the PSDU. The maximum frame size supported by
the radio transceiver is 128 bytes. If the TX_AUTO_CRC_ON bit is set in register
PHY_TX_PWR, the FCS field of the PSDU is replaced by the automatically calculated
FCS during frame transmission. There is no need to write the FCS field when using theautomatic FCS generation.
Manipulating individual bytes of the Frame Buffer is simply possible by accessing theappropriate buffer address.
The minimum frame length supported by the radio transceiver for non IEEE 802.15.4
compliant frames is one byte (Frame Length Field + 1 byte of data).
9.6.4 Battery Monitor (BATMON)
The main features of the battery monitor are:• Configurable voltage threshold range from 1.7V to 3.675V• Generates an interrupt when supply voltage drops below the threshold
9.6.4.1 Overview
The battery monitor (BATMON) detects and indicates a low supply voltage of EVDD.
This is done by comparing the voltage of EVDD with a configurable, internal thresholdvoltage. A simplified schematic of the BATMON with the most important input andoutput signals is shown in the following figure.
Figure 9-24. Simplified Schematic of BATMONEVDD

BATMON_HR+
DAC

4BATMON_VTH

Threshold
Voltage

For input-to-output mapping
see BATMON register

BATMON_OK

-

„1“
clear
D
Q

BATMON_IRQ

9.6.4.2 Configuration
The Battery Monitor can be configured using the BATMON register. Register subfield
BATMON_VTH sets the threshold voltage. It is configurable with a resolution of 75 mV
in the upper voltage range (BATMON_HR = 1) and with a resolution of 50 mV in thelower voltage range (BATMON_HR = 0).
9.6.4.3 Data Interpretation
The bit BATMON_OK of register BATMON monitors the current value of the battery
voltage:• If BATMON_OK = 0 then the battery voltage is lower than the threshold voltage;• If BATMON_OK = 1 then the battery voltage is higher than the threshold voltage;

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The value BATMON_OK should be read out to verify the current supply voltage value
after setting a new threshold.
Note:

The battery monitor is inactive during SLEEP states. Refer to status register
TRX_STATUS for details.

9.6.4.4 Interrupt HandlingA supply voltage drop below the configured threshold value is indicated by the
BAT_LOW interrupt. The BAT_LOW status bit as well as the BATLOW_EN bit islocated in the BATMON register. If BATLOW_EN =0, no IRQ is issued, but the status
flag is set if the battery low event occurs.
The interrupt is only issued if BATMON_OK changes from 1 to 0 and the event is stored
until the IRQ handler is called or the BAT_LOW IRQ is cleared manually by writing ‘1’ tothe BAT_LOW status flag.
No interrupt is generated when:• The battery voltage is below the default 1.8V threshold at power up (BATMON_OK
was never 1) or• A new threshold is set which is still above the current supply voltage (BATMON_OK
remains 0).
Noise or temporary voltage drops may generate unwanted interrupts when the battery
voltage is close to the programmed threshold voltage. To avoid this:• Disable the BAT_LOW interrupt with the BATLOW_EN Bit in the BATMON registerand treat the battery as empty or• Set a lower threshold value.
9.6.5 Crystal Oscillator (XOSC)
The main features of the crystal oscillator are:• Amplitude controlled 16 MHz generation;• 215 µs typical settling time after leaving SLEEP state;• Configurable trimming with a capacitance array;
9.6.5.1 Overview
The crystal oscillator generates the reference frequency for the radio transceiver. Allother internally generated frequencies of the radio transceiver are derived from thisunique frequency. The overall system performance is therefore critically determined by
the accuracy of the crystal reference frequency. The external components of the crystal
oscillator should be selected carefully and the related board layout should be done withcaution as described in section "Application Circuits" on page 493.
The register XOSC_CTRL provides access to the control signals of the oscillator. Two
operating modes are supported. It is recommended to use the integrated oscillator
setup as described in Figure 9-25 on page 81. Nevertheless a reference frequency canbe fed to the internal circuitry by using an external clock reference as shown in Figure
9-26 on page 82.
9.6.5.2 Integrated Oscillator Setup
The output frequency of the internal oscillator depends on the load capacitance
between the crystal pins XTAL1 and XTAL2. The total load capacitance CL must be
equal to the specified load capacitance of the crystal itself. It consists of the external
capacitors CX and parasitic capacitances connected to the XTAL nodes.
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The following figure shows all parasitic capacitances, such as PCB stray capacitances
and the pin input capacitance summarized to CPAR.
Figure 9-25. Simplified XOSC Schematic with External Components

CPAR

CX

CX

CPAR

V EVDD

XTAL1

EVDD

16MHz

XTAL2

PCB
IC internal

CTRIM

CTRIM

XTAL_TRIM[3:0]

XTAL_TRIM[3:0]

EVDD

Additional internal trimming capacitors CTRIM are available. Any value in the range from0 pF to 4.5 pF with a 0.3 pF resolution is selectable using XTAL_TRIM of register
XOSC_CTRL. To calculate the total load capacitance, the following formula can beused
CL = 0.5 • (CX + CTRIM + CPAR).
The trimming capacitors provide the possibility to reduce frequency deviations caused
by variations of the production process or by tolerances of external components. Notethat the oscillation frequency can only be reduced by increasing the trimming
capacitance. The frequency deviation caused by one step of CTRIM decreases withincreasing values of the crystal load capacitor.
An amplitude control circuit is included to ensure stable operation under different
operating conditions and for different crystal types. Enabling the crystal oscillator after
leaving SLEEP state causes a slightly higher current during the amplitude build-up
phase to guarantee a short start-up time. The current is reduced to the amountnecessary for a robust oscillation during stable operation. This also keeps the drive
level of the crystal low.
Crystals with a higher load capacitance are generally less sensitive to parasitic pulling
effects caused by variations of external components or board and circuit parasitics. On
the other hand a larger crystal load capacitance results in a longer start-up time and ahigher steady state current consumption.
9.6.5.3 External Reference Frequency Setup
When using an external reference frequency, the signal must be connected topin XTAL1 as indicated in Figure 9-26 on page 82 and the bits XTAL_MODE of register
XOSC_CTRL need to be set to the external oscillator mode. The oscillation peak-topeak amplitude shall between 100 mV and 500 mV, the optimum range is between
400 mV and 500 mV. Pin XTAL2 should not be wired

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Figure 9-26. Setup for Using an External Frequency Reference

16 MHz

XTAL1

XTAL2

PCB
IC internal

9.6.6 Frequency Synthesizer (PLL)
The main features of the phase-locked loop are:
• Generate RX/TX frequencies for all 2.4 GHz channels of IEEE 802.15.4;• Autonomous calibration loops for stable operation within the operating range;• Two PLL-interrupts for status indication;• Fast PLL settling to support frequency hopping;
9.6.6.1 Overview
The PLL generates the RF frequencies for the radio transceiver. During receive
operation the frequency synthesizer works as a local oscillator for the receive frequencyof the radio transceiver. During transmit operation the voltage-controlled oscillator(VCO) is directly modulated to generate the RF transmit signal. The frequency
synthesizer is implemented as a fractional-N PLL.
Two calibration loops ensure correct PLL functionality within the specified operating
limits.
9.6.6.2 RF Channel Selection
The PLL is designed to support 16 channels in the 2.4 GHz ISM band with channel
spacing of 5 MHz according to IEEE 802.15.4. The center frequency of these channels
is defined as follows:
Fc = 2405 + 5 (k – 11) in [MHz], for k = 11, 12 ... 26
where k is the channel number.
The channel k is selected by the CHANNEL bits of register PHY_CC_CA.
9.6.6.3 Frequency Agility
When the PLL is enabled during state transition from TRX_OFF to PLL_ON the settling
time is typically tTR4 = 110 µs including the settling time of the analog voltage regulator(AVREG) and the PLL self calibration (refer to Table 9-8 on page 42Table 9-8 and ? ?
? ? ? ? ? ? ? ? ? ). A lock of the PLL is indicated with a TRX24_PLL_LOCK interrupt.
Switching between 2.4 GHz ISM band channels in PLL_ON or RX_ON states istypically done within tTR20 = 11 µs. This makes the radio transceiver highly suitable forfrequency hopping applications.
The PLL frequency is changed to the transmit frequency within tTR23 = 16 µs after
starting the transmit procedure and before starting the transmission. After thetransmission the PLL settles back to the receive frequency within tTR24 = 32 µs. Thisfrequency step does not generate a TRX24_PLL_LOCK or TRX24_PLL_UNLOCK
interrupt within these time spans.

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9.6.6.4 Calibration Loops
Due to temperature, supply voltage and part-to-part variations of the radio transceiver
the VCO characteristics diverge. Two automated control loops are implemented toensure a stable operation: center frequency (CF) tuning and delay cell (DCU)
calibration. Both calibration loops are initiated automatically when the PLL is enabledduring state transition from TRX_OFF to PLL_ON. The center frequency calibration isadditionally initiated when the PLL changes to a center frequency of another channel.
It is recommended to initiate the calibration loops manually if the PLL operates for along time on the same channel e.g. more than 5 min or the operating temperaturechanges significantly. Both calibration loops can be initiated manually by setting
PLL_CF_START = 1 of register PLL_CF and PLL_DCU_START = 1 of register
PLL_DCU. The device must be in PLL_ON or RX_ON state to start the calibration. The
completion of the center frequency tuning is indicated by a TRX24_PLL_LOCKinterrupt.
Both calibration loops may be run simultaneously.
9.6.6.5 Interrupt Handling
Two different interrupts indicate the PLL status. The TRX24_PLL_LOCK interrupt
indicates that the PLL has locked. The TRX24_PLL_UNLOCK interrupt indicates an
unexpected unlock condition.
A TRX24_PLL_LOCK interrupt is supposed to occur in the following situations:• State change from TRX_OFF to PLL_ON / RX_ON/ RX_AACK_ON/
TX_ARET_ON;• Channel change in states PLL_ON / RX_ON/ RX_AACK_ON/ TX_ARET_ON;
Any other occurrences of PLL interrupts indicate erroneous behavior and require
checking of the actual device status.
The state transition from BUSY_TX to PLL_ON after successful transmission does not
generate a TRX24_PLL_LOCK interrupt within the settling period.
9.6.7 Automatic Filter Tuning (FTN)The FTN is incorporated to compensate device tolerances for temperature, supply
voltage variations as well as part-to-part variations of the radio transceiver. The filtertuning result is used to correct the transfer function of the analog baseband filter andthe time constant of the PLL loop-filter (refer to "General Circuit Description" on page30).
An FTN calibration cycle is initiated automatically when entering the radio transceiver
TRX_OFF state from the SLEEP or RESET state.
Although receiver and transmitter are very robust against these variations, it isrecommended to initiate the FTN manually if the radio transceiver does not use the
SLEEP state. A calibration cycle is to be initiated in states TRX_OFF, PLL_ON or
RX_ON if necessary. This applies in particular to the High Data Rate Modes with amuch higher sensitivity to variations of the BPF transfer function. The recommended
calibration interval is 5 min or less.

9.7 Radio Transceiver Usage
This section describes the basic procedures to receive and transmit frames with theradio transceiver.

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9.7.1 Frame Receive Procedure
A frame reception comprises of two actions: The PHY listens for a frame, receives anddemodulates the frame to the Frame Buffer and signalizes its reception to theapplication software. The application software reads the available frame data from the
Frame Buffer after or during the progress of the frame reception.
While in state RX_ON or RX_AACK_ON the radio transceiver searches for incoming
frames on the selected channel. First a TRX24_RX_START interrupt indicates thedetection of an IEEE 802.15.4 compliant frame assuming the appropriate interrupts areenabled. The frame reception is completed when issuing the TRX24_RX_END
interrupt.
Different Frame Buffer read access scenarios are recommended for:• Non-time critical applications: read access starts after the TRX24_RX_END interrupt;• Time-critical applications: read access starts after the TRX24_RX_START interrupt;
The controller must ensure to read valid Frame Buffer contents. Reading frame data
before frame reception is finished can lead to invalid data, if buffer regions areaccessed which are not yet updated with the new frame.
While receiving a frame the data needs to be primarily stored in the Frame Buffer
before reading it. This is ensured by accessing the first Frame Buffer byte at least 32 µs
after the TRX24_RX_START interrupt.
It is recommended for operations considered to be not time-critical to wait for the
TRX24_RX_END interrupt before starting a Frame Buffer read access. The following
figure illustrates the frame receive procedure using the TRX24_RX_END interrupt.
Figure 9-27. Transactions between radio transceiver and microcontroller during receive

IRQ issued (RX_END)
Read TST_FRAME_LENGTH register(Register access)Microcontroller

Transceiver

IRQ issued (RX_START)Read frame data (Frame Buffer access)Critical protocol timing could require starting the Frame Buffer read access after the
TRX24_RX_START interrupt. The first byte of the frame data can be read 32 µs after
the TRX24_RX_START interrupt. The application software must ensure to read slower
than the frame is received. Otherwise a Frame Buffer under-run occurs and the frame
data may be not valid.
9.7.2 Frame Transmit Procedure
A frame transmission comprises of the two actions Frame Buffer write access andtransmission of the Frame Buffer content. Both actions can be run in parallel if requiredby critical protocol timing.
Figure 9-28 on page 85 illustrates the frame transmit procedure by consecutively writing
and transmitting the frame. The frame transmission is initiated writing SLPTR or writing

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command TX_START to register TRX_STATE after a Frame Buffer write access andwhile the radio transceiver is in state PLL_ON or TX_ARET_ON. The TRX24_TX_END
interrupt indicates the completion of the transaction.
Figure 9-28. Transaction between radio transceiver and microcontroller during transmit

Write TRX_CMD = TX_START, or write SLPTR(Register access)Microcontroller

Transceiver

Write frame data (Frame Buffer access)

IRQ issued (TX_END)

Alternatively a frame transmission can be started first, followed by the Frame Buffer
write access (PSDU data) as shown in Figure 9-29 below. This is applicable for time
critical applications.
A transmission is initiated either by writing SLPTR or by writing the TX_START
command to the TRX_CMD bits of register TRX_STATE. The radio transceiver thenstarts transmitting the SHR which is internally generated.
This first phase requires 16 µs for PLL settling and 160 µs for SHR transmission. The
PHR must be available in the Frame Buffer before this time elapses. Furthermore theFrame Buffer must be filled faster than the frame is transmitted to prevent a buffer
under-run.
Figure 9-29. Time Optimized Frame Transmit Procedure

Write frame data (Frame Buffer access)Microcontroller

Transceiver

Write TRX_CMD = TX_START, or write SLPTR(Register access)

IRQ issued (TX_END)

9.8 Radio Transceiver Extended Feature Set
9.8.1 Random Number Generator
The radio transceiver incorporates a 2-bit, noise observing, true random number
generator to be used to:• Generate random seeds for CSMA-CA algorithm (see"Extended Operating Mode" onpage 43);85
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• Generate random values for AES key generation (see "Security Module (AES)" onpage 92);
The random number is updated every tTR29 = 1 µs in Basic Operation Mode receive
states. The values are stored in bits RND_VALUE of register PHY_RSSI.
9.8.2 High Data Rate Modes
The main features of the High Data Rate Modes are:• High Data Rate Communication up to 2 Mb/s;• Support of Basic and Extended Operating Mode;• Support of other features of the Extended Feature Set;
9.8.2.1 Overview
The radio transceiver also supports alternative data rates higher than 250 kb/s forapplications beyond IEEE 802.15.4 compliant networks.
The selection of a data rate does not affect the remaining functionality. Thus it ispossible to run all features and operating modes of the radio transceiver in various
combinations.
The data rate can be selected by writing bits OQPSK_DATA_RATE of register
TRX_CTRL_2.
The High Data Rate Modes occupy the same RF channel bandwidth as theIEEE 802.15.4 – 2.4 GHz 250 kb/s standard mode. The sensitivity of the receiver isreduced due to the decreased spreading factor. The following table shows typicalvalues of the sensitivity for different data rates.
Table 9-23. High Data Rate Sensitivity
High Data Rate

Sensitivity

Comment

250 kb/s-100 dBm

PER ≤ 1%, PSDU length of 20 octets

500 kb/s-9 dBmPER ≤ 1%, PSDU length of 20 octets

1000 kb/s-9 dBmPER ≤ 1%, PSDU length of 20 octets

2000 kb/s-8 dBmPER ≤ 1%, PSDU length of 20 octets

By default there is no header based signaling of the data rate within a transmitted
frame. Thus nodes using a data rate other than the default IEEE 802.15.4 data rate of
250 kb/s are to be consistently configured in advance. The configurable start of framedelimiter (SFD) could be alternatively used as an indicator of the PHY data rate (see"Configurable Start-Of-Frame Delimiter (SFD)" on page 91).
9.8.2.2 High Data Rate Packet Structure
Higher data rate modulation is restricted to only the payload octets in order to allow
appropriate frame synchronization. The SHR and the PHR field are transmitted with theIEEE 802.15.4 compliant data rate of 250 kb/s (refer to "Introduction – IEEE 802.15.42006 Frame Format" on page 61).
A comparison of the general packet structure for different data rates with an example
PSDU length of 80 octets is shown in Figure 9-30 on page 87.

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Figure 9-30. High Data Rate Frame Structure

500 kb/s

PSDU: 80 octets

1000 kb/s

PSDU: 80 octets

2000 kb/s

PSDU: 80 octets

1472

2752 time [µs]

FCS

SFD
PHR

PSDU: 80 octets

832

FCS

250 kb/s

SFD
PHR

512

SFD
PHR

192

SFD
PHR

0

The effective data rate is smaller than the selected data rate due to the overheadcaused by the SHR, the PHR and the FCS. The overhead depends further on thelength of the PSDU. A graphical representation of the effective data rate is shown in thefollowing figure:
Figure 9-31. Effective Data Rate “B” for High Data Rate Mode
1600
2000
1000
500
250

1400
1200

B [kbps]1000
2000 kbps
8001000 kbps
600
500 kbps
400
250 kbps
200
0
0

20

40

60

80

100

120

PSDU length in octets

Therefore High Data Rate transmission and reception is useful for large PSDU lengths
due to the higher effective data rate or to reduce the power consumption of the system.
Furthermore the active on-air time using High Data Rate Modes is significantly reduced.
9.8.2.3 High Data Rate Frame Buffer Access
The Frame Buffer access to read or write frames for High Data Rate communication issimilar to the procedure described in "Frame Buffer" on page 77. However the last byte
in the Frame Buffer after the PSDU data is the ED value rather than the LQI value.
9.8.2.4 High Data Rate Energy Detection
According to IEEE 802.15.4 the ED measurement duration is 8 symbol periods. For
frames operated at higher data rates the automated ED measurement duration is
reduced to 32 µs to take the reduced frame length into account ("Energy Detection(ED)" on page 68).
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9.8.2.5 High Data Rate Mode Options
Receiver Sensitivity Control
The different data rates between PPDU header (SHR and PHR) and PHY payload(PSDU) cause a different sensitivity between header and payload. This can be adjusted
by defining sensitivity threshold levels of the receiver. The receiver does not receive
frames with an RSSI level below the defined sensitivity threshold level (register bits
RX_PDT_LEVEL > 0). Under these operating conditions the receiver current
consumption is reduced by 500 µA (refer to chapter "Current Consumption
Specifications" on page 509).
A description of the settings to control the sensitivity threshold with register RX_SYN
can be found in section "RX_SYN – Transceiver Receiver Sensitivity Control Register"on page 118.
Reduced Acknowledgment Timing
On higher data rates the IEEE 802.15.4 compliant acknowledgment frame responsetime of 192 µs significantly reduces the effective data rate of the network. To minimize
this influence in Extended Operating Mode RX_AACK (see section "RX_AACK_ON –Receive with Automatic ACK" on page 46), the acknowledgment frame response time
can be reduced to 32 µs. Figure 9-32 below illustrates an example for a reception andacknowledgement of a frame with a data rate of 2000 kb/s and a PSDU length of 80
symbols. The PSDU length of the acknowledgment frame is 5 octets according toIEEE 802.15.4.
Figure 9-32. High Data Rate AACK Timing
704

916

SFD

192 µs

PHR

544

SFD

PSDU: 80 octets

512

PHR

SFD

PHR

AACK_ACK_TIME = 1

PSDU: 80 octets

SFD

AACK_ACK_TIME = 0

192

PHR

0

time [µs]

ACK

ACK

32 µs

The acknowledgment time is reduced from 192 µs to 32 µs if bit AACK_ACK_TIME ofregister XAH_CTRL_1 is set.
9.8.3 Antenna Diversity
The main features of the Antenna Diversity implementation are:
• Improves signal path robustness between nodes;• Self-contained antenna diversity algorithm of the radio transceiver;• Direct register based antenna selection;
9.8.3.1 Overview
The receive signal strength may vary and affect the link quality even for small changesof the antenna location due to multipath propagation effects between network nodes.
These fading effects can result in an increased error floor or loss of the connection
between devices.
Antenna Diversity can be applied to reduce the effects of multipath propagation andfading hence improving the reliability of a RF connection between network nodes.

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Antenna Diversity uses two antennas to switch to the most reliable RF signal path. Thisis done by the radio transceiver during RX_LISTEN and RX_AACK_ON state without
interaction of the application software. Both antennas should be carefully separated
from each other to ensure highly independent receive signals.
Antenna Diversity can be used in Basic and Extended Operating Modes and can also
be combined with other features and operating modes like High Data Rate Mode and
RX/TX Indication.
9.8.3.2 Antenna Diversity Application Example
A block diagram for an application using an antenna switch is shown in the following
figure.
Figure 9-33. External Antenna Diversity – Block Diagram
ANT0

1

D IG 2

2

A T m ega 128R FA 1

D IG 4

7

AVSS

8

RFP

9

RFN

10 A V S S
...

DIG1

B1

DIG3

RFSwitch

SW 1

Balun

...

14

15

ANT1

Generally, the Antenna Diversity algorithm is enabled with bit ANT_DIV_EN=1 in
register ANT_DIV. For the External Antenna Diversity the control of the antenna switch(SW1) must be enabled by bit ANT_EXT_SW_EN of register ANT_DIV. Under thiscondition the control pins DIG1 and DIG2 are configured as outputs. DIG1 and DIG2
are used to feed the antenna switch signal and its inverse to the differential inputs of the
RF Switch (SW1).
The selected antenna is indicated by bit ANT_SEL of register ANT_DIV. The antenna
selection continues searching for new frames on both antennas after the frame
reception is completed. However the register bit ANT_SEL maintains its previous value(from the last received frame) until a new SHR has been found and the selection
algorithm locked into one antenna again. Then the register bit ANT_SEL is updated.
The antenna defined by the ANT_CTRL bits of register ANT_DIV is selected fortransmission. If for example the same antenna as selected for reception is to be used
for transmission, the antenna must be set using the ANT_CTRL bits based on the value
read from the ANT_SEL bit. It is recommended to read bit ANT_SEL after the
TRX24_RX_START interrupt.
The autonomous search and selection allows the use of Antenna Diversity during
reception even if the application software currently does not control the radiotransceiver for instance in Extended Operating Mode.
An application software defined selection of a certain antenna can be done by disabling
the automatic Antenna Diversity algorithm (ANT_DIV_EN = 0) and selecting one
antenna using register bit ANT_CTRL.
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If the radio transceiver is not in a receive or transmit state, it is recommended to disable
register bit ANT_EXT_SW_EN and to set the port pins DIG1 and DIG2 to output low(DDG1 = 1, PORTG1 = 0, DDF2 = 1, PORTF2 = 0) in order to reduce the power
consumption or avoid leakage current of the external RF switch especially during sleep
modes.
9.8.3.3 Antenna Diversity with Extended Operation Modes
A combination of Extended Operation Mode and antenna diversity is allowed.
While the radio transceiver is in RX_AACK_ON state, it switches to an antenna with areliable signal. The receive antenna selection is also used for transmission of an
automatic acknowledge frame.
While the radio transceiver is in TX_ARET state, the selected antenna is automaticallychanged for every frame transmission retry.
9.8.3.4 Antenna Diversity Sensitivity Control
The detection threshold of the receiver has to be adjusted due to a different receivealgorithm used by the Antenna Diversity algorithm. It is recommended to set bits
PDT_THRES of register RX_CTRL to 3.
9.8.4 RX/TX Indicator
The main features are:• RX/TX Indicator to control an external RF Front-End;• Application software independent RF Front-End Control;• Provide TX Timing Information;
9.8.4.1 Overview
While IEEE 802.15.4 is a low-cost, low-power standard, solutions supporting higher
transmit output power are occasionally desirable. A differential control pin pair can
indicate that the radio transceiver is currently in transmit mode to simplify the control ofan optional external RF front-end.
The control of an external RF front-end is done via the digital control pins DIG3/DIG4.
The function of this pin pair is enabled with bit PA_EXT_EN of register TRX_CTRL_1.
Pin DIG3 is set to low level and DIG4 to high level while the transmitter is turned off.
The two pins change the polarity when the radio transceiver starts transmitting. Thisdifferential pin pair can be used to control PA, LNA and RF switches.
If the radio transceiver is not in a receive or transmit state, it is recommended to disable
register bit PA_EXT_EN and to set the port pins DIG3 and DIG4 to output low (DDG0 =1, PORTG0 = 0, DDF3 = 1, PORTF3 = 0) in order to reduce the power consumption or
avoid leakage current of external RF switches and other building blocks especiallyduring sleep modes.
9.8.4.2 External RF-Front End Control
The setup time of the external power amplifier (PA) relative to the internal building
blocks should be adjusted when using an external RF front-end including a power
amplifier to optimize the overall power spectral density (PSD) mask.

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Figure 9-34. TX Power Ramping Control for RF Front-Ends
0

TRX_STATE

2

4

6

PLL_O N

8

10

12

14

16

18

Length [µs]BU SY_TX

SLPTR
PA_BUF_LT

PA buffer

PA_LT

PA

1

M odulation

1 0

1

1 0 0 1

1

DIG 3
DIG 4

The start-up sequence of the individual building blocks of the internal transmitter isshown in the previous figure. The transmission is actually initiated by writing ‘1’ to
SLPTR. The radio transceiver state changes from PLL_ON to BUSY_TX and the PLL
settles to the transmit frequency within 16 µs (parameter tTR23 at page 42). The
modulation starts 16 µs (parameter tTR10 at page 42) after the SLPTR=1. The PA
buffer and the internal PA are enabled during this time.
The control of an external PA is done via the differential pin pair DIG3 and DIG4.
DIG3 = H / DIG4 = L indicates that the transmission starts and can be used to enable
an external PA. The timing of pins DIG3/DIG4 can be adjusted relative to the start of theframe and the activation of the internal PA buffer. This is controlled using the register
bits PA_BUF_LT and PA_LT. For details refer to Figure 9-22 on page 77.
9.8.5 RX Frame Time Stamping
To determine the exact timing of an incoming frame e.g. for beaconing networks, theSymbol Counter should be used. SFD Time Stamping is enabled by setting bit SCTSE
of the Symbol Counter Control Register SCCR0. The actual 32 Bit Symbol Countervalue is captured in the SFD Time Stamp register SCTSR at the time, the SFD has
been received. For details see section "SFD and Beacon Timestamp Generation" onpage 135.
9.8.6 Configurable Start-Of-Frame Delimiter (SFD)The SFD is a field indicating the end of the SHR and the start of the packet data. The
length of the SFD is 1 octet (2 symbols). This octet is used for byte synchronization only
and is not included in the Frame Buffer.
The value of the SFD could be changed if it is needed to operate non IEEE 802.15.4
compliant networks. An IEEE 802.15.4 compliant network node does not synchronize toframes with a different SFD value.
The register SFD_VALUE contains the one octet start-of-frame delimiter (SFD) to
synchronize to a received frame. It is not recommended to set the low-order 4 bits to 0
due to the way the SHR is formed.
9.8.7 Dynamic Frame Buffer Protection
The ATmega128RFA1 continues the reception of incoming frames as long as it is in
any receive state. When a frame was successfully received and stored into the Frame
Buffer, the following frame will overwrite the Frame Buffer content again. To relax thetiming requirements for a Frame Buffer read access the Dynamic Frame Buffer
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Protection prevents that a new valid frame passes to the Frame Buffer until the buffer
protection bit is cleared (RX_SAFE_MODE = 0).
A received frame is automatically protected against overwriting:• in Basic Operating Mode, if its FCS is valid• in Extended Operating Mode, if an TRX24_RX_END interrupt is generated
The Dynamic Frame Buffer Protection is enabled, if register bit RX_SAFE_MODE(register TRX_CTRL_2, see "TRX_CTRL_2 – Transceiver Control Register 2" on page112) is set and the radio transceiver state is RX_ON or RX_AACK_ON.
Note that Dynamic Frame Buffer Protection only prevents write accesses from the airinterface not from the application software. The application software may still modify the
Frame Buffer content.
9.8.8 Security Module (AES)
The security module (AES) is characterized by:• Hardware accelerated encryption and decryption;• Compatible with AES-128 standard (128 bit key and data block size);• ECB (encryption/decryption) mode and CBC (encryption) mode support;• Stand-alone operation, independent of other blocks;
See TBD Application regarding the AES security module usage.
9.8.8.1 Overview
The security module is based on an AES-128 core according to the FIPS197 standard[5]. and provides two modes, the Electronic Code Book (ECB) and the Cipher Block
Chaining (CBC). The security module works independent of other building blocks of theradio transceiver. Encryption and decryption can be performed in parallel to a frametransmission or reception.
The ECB and CBC modules including the AES core are clocked with the 16 MHz Radio
Transceiver Crystal Oscillator.
Controlling the security block is possible over 5 Registers within AVR I/O space:
Table 9-24. Security Module Address Space Overview
Register Name

Description

AES_STATUS

AES status register

AES_CTRLAES control register

AES_KEY

Access to 16 Byte key buffer

AES_STATE

Access to 16 Byte data buffer

9.8.8.2 Security Module Preparation
The use of the security module requires a configuration of the security engine before
starting a security operation. The following steps are required:
Table 9-25. AES Engine Configuration Steps

92

Step

Description

Description

1

Key Setup

Write encryption or decryption key to KEY
buffer(16 consecutive byte writes to AES_KEY)

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Step

Description

Description

2

AES configuration

Select AES mode: ECB or CBC
Select encryption or decryption
Enable the AES Encryption Ready Interrupt
AES_READY

3

Write Data

Write plaintext or cipher text to DATA buffer(16 consecutive byte writes to AES_STATE)

4

Start operation

Start AES operation

5

Wait for AES finished:
1. AES_READY IRQ or
2. polling AES_DONE bit(register AES_STATUS) or
3. wait for 24 µs

Wait until AES encryption/decryption isfinished successfully

6

Read Data

Read cipher text or plaintext from DATA buffer(16 consecutive byte reads from AES_STATE)

Before starting any security operation a 16 Byte key must be written to the security
engine (refer to section "Security Key Setup" below). This can be done by 16
consecutive write accesses to the I/O register AES_KEY. An internal address counter isincremented automatically with every read/ write operation. An AES encryption/
decryption run resets the internal byte counter. If the key and data buffer has not beenread or written completely (all 16 Bytes), the following encryption/ decryption operation
will finish with an error.
The following step selects either Electronic Code Book (ECB) or Cipher Block Chaining(CBC) as the AES_MODE. These modes are explained in more detail in section"Security Operation Modes" on page 94. Encryption or decryption must be further
selected with bit AES_DIR of register AES_CTRL.
If the AES Error or AES Ready IRQ is used, the interrupt must be enabled with bit
AES_IM.
Next the 128-bit plain text or cipher text data has to be provided to the AES hardware
engine. The 16 data bytes must be consecutively written to the AES_STATE register.
The AES_STATE register can be accessed in the same way as the key register (refer to"Security Key Setup" below).
The encryption or decryption is initiated with bit AES_REQUEST = 1.
The operation takes 24 µs and the completed encryption/ decryption is indicated by the
AES_READY IRQ and the AES_DONE bit. The internal byte counter of the key anddata buffer is cleared and the resulting data can be read out.
For additional information about the key and data buffer please refer to section"AES_KEY – AES Encryption and Decryption Key Buffer Register" on page 102 and"AES_STATE – AES Plain and Cipher Text Buffer Register" on page 102.
Notes:

1. Access to the security block is not possible while the radio transceiver is in state
SLEEP.
2. All configurations of the security module, the SRAM content and keys are reset
during SLEEP or RESET states.

9.8.8.3 Security Key Setup
The key is stored in a 16 Byte sequential buffer. To read or write the contents of thebuffer, 16 consecutive read or write operations to the AES_KEY register are required.

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A 16-folded read access to registers AES_KEY returns the last round key of thepreceding security operation. This is the key required for the corresponding ECB
decryption operation after an ECB encryption operation. However the initial AES key
written to the security module in advance of an AES run (see step 1 in Table 9-25 on
page 92) is not modified during an AES operation. This initial key is used for the next
AES run although it cannot be read from AES_KEY.
Before accessing the Key Buffer it must be ensured, that the internal address counter is
initialized correctly. This is the cases after Radio Transceiver Reset (see TRXPR –Transceiver Pin Register on page 169) or a completed AES Encryption/ Decryption
operation. After an interrupted buffer read or write access, Address pointerreinitialization is recommended by a simple read access to the AES_CTRL register.
Note:

1. ECB decryption is not required for IEEE 802.15.4 or ZigBee security processing.
The radio transceiver provides this functionality as an additional feature.

9.8.8.4 Security Operation Modes
9.8.8.4.1 Electronic Code Book (ECB)
ECB is the basic operating mode of the security module and is configured by the
AES_CTRL register. The bit AES_MODE = 0 defines the ECB mode and bit AES_DIR
selects the direction to either encryption or decryption. The data to be processed has tobe written to registers AES_STATE.
A security operation can be started by writing the start command AES_REQUEST = 1(AES_CTRL register).
The ECB encryption operation is illustrated in Figure 9-35 below. Figure 9-36 below
shows the ECB decryption mode which is supported in a similar way.
Figure 9-35. ECB Mode - Encryption
Plaintext

Encryption
Key

Plaintext

Encryption
Key

Block Cipher
Encryption

Ciphertext

Block Cipher
Encryption

Ciphertext

Figure 9-36. ECB Mode - Decryption
Ciphertext

Decryption
Key

Block Cipher
Decryption

Plaintext

Ciphertext

Decryption
Key

Block Cipher
Decryption

Plaintext

Due to the nature of AES algorithm the initial key to be used when decrypting is not thesame as the one used for encryption. Instead it is the last round key. This last round94

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key is the content of the key address space stored after running one full encryption
cycle and must be saved for decryption. If the decryption key has not been saved, it has
to be recomputed by first running a dummy encryption (of an arbitrary plaintext) using
the original encryption key. Then the resulting round key must be fetched from the key
memory and written back into the key memory as the decryption key.
ECB decryption is not used by either IEEE 802.15.4 or ZigBee frame security. Both ofthese standards do not directly encrypt the payload. Instead they protect the payload by
applying a XOR operation between the original payload and the resulting (AES-) cipher
text with a nonce (number used once). As the nonce is the same for encryption anddecryption only ECB encryption is required. Decryption is performed by a XOR
operation between the received cipher text and its own encryption result concluding in
the original plain text payload upon success.
9.8.8.4.2 Cipher Block Chaining (CBC)In CBC mode the result of a previous AES operation is XOR-combined with the newincoming vector forming the new plaintext to encrypt as shown in the next figure. Thismode is used for the computation of a cryptographic checksum (message integrity
code, MIC).
Figure 9-37. CBC Mode - Encryption
Plaintext

Encryption
Key

Initialization Vector (IV)Block Cipher
Encryption

Encryption
Key

Plaintext

Block Cipher
Encryption

Ciphertext

Ciphertext

ECB
mode

CBC
mode

After preparing the AES key and defining the AES operation direction register bit
AES_DIR, the data has to be provided to the AES engine and the CBC operation canbe started.
The first CBC run has to be configured as ECB to process the initial data (plain text
XOR with an initialization vector provided by the application software). All succeeding
AES runs are to be configured as CBC by setting bit AES_MODE = 1 (AES_CTRL
register ). Bit AES_DIR (AES_CTRL register) must be set to AES_DIR = 0 to enable
AES encryption. The data to be processed has to be transferred to the AES_STATE
register. Setting bit AES_REQUEST = 1 (AES_CTRL register) as described in section"Security Operation Modes" on page 94 starts the first encryption. This causes the next
128 bits of plain text data to be XORed with the previous cipher text data, see Figure 937 above.
According to IEEE 802.15.4 the input for the very first CBC operation has to beprepared by a XOR operation of the plain text with the initialization vector (IV). The
value of the initialization vector is 0. However any other initialization vector can beapplied for non-compliant usage. This operation has to be prepared by the application
software.
Note that the MIC algorithm of the IEEE 802.15.4-2006 standard requires CBC mode
encryption only because it implements a one-way hash function.

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The status of the security processing is indicated by register AES_STATUS. After a
AES processing time of 24 µs the register bit AES_DONE changes to 1 (register
AES_STATUS) indicating that the security operation has finished (see "Digital Interface
Timing Characteristics" on page 507).
The end of the AES processing can also be indicated by the AES_READY Interrupt.
The bit AES_ER of register AES_STATUS is set if the operation has finished with anerror. Otherwise this bit is zero but AES_DONE is ‘1’.
9.8.8.5 AES Interrupt Handling
The AES Interrupt handling is slightly different from all other IRQ’s. If the AES_IM Bit(AES_CTRL Register) and the global interrupt enable flag is set, the AES core cangenerate an AES Ready Interrupt (AES_READY). If the IRQ is issued, the
AES_STATUS register must be read to check the finish status of the last operation. If
AES_DONE is set, the last AES operation finished successfully. If AES_ER is set, anerror occurred during the last operation. The AES_ER flag is cleared automaticallyduring the read access to the AES_STATUS register. The AES_DONE flag is cleared
during the next read or write access to the AES_STATE (AES data) register.
The two status flags must be cleared before a new Interrupt can be issued.
If AES_IM is not set, the processing status can be polled by software (AES_STATUS
register), but no Interrupt occurs.

9.9 Continuous Transmission Test Mode9.9.1 Overview
The 2.4GHz transceiver offers a Continuous Transmission Test Mode to support final
application / production tests as well as certification tests. In this test mode the radiotransceiver transmits continuously a previously transferred frame (PRBS mode) or acontinuous wave signal (CW mode).
In CW mode two different signal frequencies per channel can be transmitted:• f1 = fCH + 0.5 MHz• f2 = fCH - 0.5 MHz
Here fCH is the channel center frequency programmed by register PHY_CC_CCA.
Note that in CW mode it is not possible to transmit a RF signal directly on the channel
center frequency. PSDU data in the Frame Buffer must contain at least a valid PHR(see section "Introduction – IEEE 802.15.4-2006 Frame Format" on page 61). It is
recommended to use a frame of maximum length (127 bytes) and arbitrary PSDU data
for the PRBS mode. The SHR and the PHR are not transmitted. The transmission starts
with the PSDU data and is repeated continuously.
9.9.2 Configuration
All register configurations shall be setup as follows before enabling Continuous
Transmission Test Mode:• TX channel setting (optional);• TX output power setting (optional);• Mode selection (PRBS / CW);
An access to the registers TST_CTRL_DIGI and PART_NUM enables the Continuous
Transmission Test Mode.

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The transmission is started by enabling the PLL (TRX_CMD = PLL_ON) and writing the
TX_START command to register TRX_STATE.
Even for CW signal transmission it is required to write valid PSDU data to the Frame
Buffer. For PRBS mode it is recommended to write a frame of maximum length.
The detailed programming sequence is shown in Table 9-26 below. The column R/W
informs about writing (W) or reading (R) a register or the Frame Buffer.
Table 9-26. Continuous Transmission Programming Sequence
Step

Action

1

RESET

2

Register Access

IRQ_MASKW

0x01

Set IRQ mask register, enable
PLL_LOCK interrupt and set
global AVR IRQ enable3

Register Access

TRX_CTRL_1

W

0x00

Disable TX_AUTO_CRC_ON

4

Register Access

TRX_STATEW

0x03

Set radio transceiver state
TRX_OFF

5

Register Access

PHY_CC_CCA

W

0x33

Set IEEE 802.15.4 CHANNEL,
e.g. 19

6

Register Access

PHY_TX_PWR

W

0x00

Set TX output power, e.g. to Pmax

7

Register Access

TRX_STATUS

R

0x08

Verify TRX_OFF state8

Register Access

TST_CTRL_DIGI

W

0x0F

Enable Continuous Transmission
Test Mode – step # 1(1)

Register Access

TRX_CTRL_2

W

0x03

Enable High Data Rate Mode, 2
Mb/s

10

(1)

Register Access

RX_CTRLW

0xA7

Configure High Data Rate Mode

11

(2)

Frame Buffer
Write Access

9

Register

R/
W

Value

Description
Reset the transceiverW

Write PSDU data (even for CWmode), refer to Table 9-27 on
page 98

12

Register Access

PART_NUM

W

0x54

Enable Continuous Transmission
Test Mode – step # 2

13

Register Access

PART_NUMW

0x46

Enable Continuous Transmission
Test Mode – step # 3

14

Register Access

TRX_STATEW

0x09

Enable PLL_ON state

15

Interrupt event

R

0x01

Wait for PLL_LOCK interrupt

16

Register Access

W

0x02

Initiate Transmission,enter BUSY_TX state17

Measurement

18

Register Access

19

RESET

Notes:

TRX_STATE

Perform measurement
TRX_CTRL_2

W

0x00

Disable Continuous
Transmission Test Mode
Reset the transceiver

1. Only required for CW mode, do not configure for PRBS mode.
2. Frame Buffer content varies for different modulation schemes.

The content of the Frame Buffer has to be defined for Continuous Transmission PRBS
mode or CW mode. To measure the power spectral density (PSD) mask of thetransmitter it is recommended to use a random sequence of maximum length for the
PSDU data.

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To measure CW signals it is necessary to write either 0x00 or 0xFF to the Frame
Buffer. For details refer to Table 9-27 below.
Table 9-27. Frame Buffer Content for various Continuous Transmission Modulation
Schemes
Step

ActionFrame Content

Comment

11

Frame Buffer
Write Access

Random Sequence

modulated RF signal

0x00 (each byte)fCH – 0.5 MHz, CW signal

0xFF (each byte)

fCH + 0.5 MHz, CW signal

9.10 Abbreviations
AACK-

Automatic acknowledgement

ACK-

Acknowledgement

ADC-

Analog-to-digital converter

AD-

Antenna diversity

AGC-

Automated gain control

AES-

Advanced encryption standard

ARET

-

Automatic retransmission

AVREG

-

Voltage regulator for analog building blocks

AWGN

-

Additive White Gaussian NoiseBATMON-

Battery monitor

BBP-

Base band processor

BPF-

Band pass filter

CBC-

Cipher block chaining

CRC-

Cyclic redundancy check

CCA-

Clear channel assessment

CSMA-CA-

Carrier sense multiple access/Collision avoidance

CW-

Continuous wave

DVREG

98

-

Voltage regulator for digital building blocks

ECB-

Electronic code book

ED-

Energy detection

ESD-

Electro static discharge

EVM-

Error vector magnitude

FCF-

Frame control field

FCS-

Frame check sequence

FIFO

-

First in first out

FTN-

Filter tuning network

GPIO

-

General purpose input output

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ISM-

Industrial, scientific, and medical

LDO-

Low-drop output

LNA-

Low-noise amplifier

LO-

Local oscillator

LQI-

Link quality indicator

LSB-

Least significant bit

MAC-

Medium access control

MFR-

MAC footer

MHR-

MAC header

MSB-

Most significant bit

MSDU

-

MAC service data unit

MPDU

-

MAC protocol data unit

MSK-

Minimum shift keying

O-QPSK-

Offset - quadrature phase shift keying

PA-

Power amplifier

PAN-

Personal area network

PCB-

Printed circuit board

PER-

Packet error rate

PHR-

PHY header

PHY-

Physical layer

PLL-

Phase locked loop

POR-

Power-on reset

PPF-

Poly-phase filter

PRBS

-

Pseudo random bit sequence

PSDU

-

PHY service data unit

PSD-

Power spectral mask

QFN-

Quad flat no-lead package

RF-Radio frequency

RSSI

-

Received signal strength indicatorRX-

Receiver

SFD-

Start-of-frame delimiter

SHR-

Synchronization header

SPI-

Serial peripheral interface

SRAM

-

Static random access memory

SSBF

-

Single side band filter

TX-

Transmitter

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VCO

-

Voltage controlled oscillator

VREG

-

Voltage regulator

XOSC

-

Crystal oscillator

9.11 Reference Documents[1]

IEEE Std 802.15.4™-2006: Wireless Medium Access Control (MAC) andPhysical Layer (PHY) Specifications for Low-Rate Wireless Personal Area
Networks (LR-WPANs)[2]

IEEE Std 802.15.4™-2003: Wireless Medium Access Control (MAC) andPhysical Layer (PHY) Specifications for Low-Rate Wireless Personal Area
Networks (LR-WPANs)[3]

ANSI / ESD-STM5.1-2001: ESD Association Standard Test Method forelectrostatic discharge sensitivity testing – Human Body Model (HBM).

[4]

ESD-STM5.3.1-1999: ESD Association Standard Test Method for electrostatic
discharge sensitivity testing – Charged Device Model (CDM).

[5]NIST FIPS PUB 197: Advanced Encryption Standard (AES), Federal
Information Processing Standards Publication 197, US Department ofCommerce/NIST, November 26, 2001

[6]

ATmega128RFA1 Software Programming Model

9.12 Register Description
9.12.1 AES_CTRL – AES Control Register
Bit

7

6

5

4

NA ($13C)

AES_REQUESTRes

AES_MODERes

Read/Write
Initial Value

RW
0

R
0

RW
0

R
0

3

2

AES_DIR AES_IM
RW
0

RW
0

1

0

Res1

Res0

R
0

R
0

AES_CTRLThis register controls the operation of the security module. Do not access this registerduring AES operation to read the AES core status. A read or write access to the register
stops the ongoing processing. To read the AES status use bit AES_DONE of register
AES_STATUS. Note that the AES_CTRL register is cleared when entering the radiotransceiver SLEEP state.
• Bit 7 – AES_REQUEST - Request AES Operation.
A write access with AES_REQUEST = 1 initiates the AES operation.
• Bit 6 – Res - Reserved Bit
This bit is reserved for future use. The result of a read access is undefined. The register
bit must always be written with the reset value.
• Bit 5 – AES_MODE - Set AES Operation Mode
This register bit sets the AES operation mode (ECB/CBC Mode).

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Table 9-28 AES_MODE Register Bits
Register Bits

Value

Description

AES_MODE0

AES Mode is ECB (Electronic Code Book).

1

AES Mode is CBC (Cipher Block Chaining).

• Bit 4 – Res - Reserved Bit
This bit is reserved for future use. The result of a read access is undefined. The register
bit must always be written with the reset value.
• Bit 3 – AES_DIR - Set AES Operation Direction
This register bit sets the AES operation direction to either encryption or decryption.
Table 9-29 AES_DIR Register Bits
Register BitsValue

AES_DIR

Description0

AES operation is encryption.

1

AES operation is decryption.

• Bit 2 – AES_IM - AES Interrupt Enable
This register bit is used to enable the AES interrupt.
• Bit 1:0 – Res1:0 - Reserved Bit
These bits are reserved for future use. The result of a read access is undefined. The
register bits must always be written with the reset value.

9.12.2 AES_STATUS – AES Status Register
Bit

7

6

5

4

3

2

1

NA ($13D)

AES_ER

Res5

Res4

Res3

Res2

Res1

Res0

Read/Write
Initial Value

R
0

R
0

R
0

R
0

R
0

R
0

R
0

0

AES_DONE AES_STATUS
R
0This read-only register signals the status of the security module and operation. Notethat the AES_STATUS register is cleared when entering the radio transceiver SLEEP
state.
• Bit 7 – AES_ER - AES Operation Finished with Error
This register bit indicates an error during AES module run. An error occurs if accessing
AES_CTRL while an AES operation is running or if AES_KEY or AES_STATE Memory
is not loaded completely or less than 16 Byte read from AES_STATE.
• Bit 6:1 – Res5:0 - Reserved
These bits are reserved for future use.
• Bit 0 – AES_DONE - AES Operation Finished with SuccessThis register bit indicates a successfully finished operation of the AES module.

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9.12.3 AES_STATE – AES Plain and Cipher Text Buffer Register
Bit

7

6

5

4

NA ($13E)
Read/Write
Initial Value

3

2

1

0

AES_STATE7:0
RW
0

RW
0

RW
0

RW
0

AES_STATE

RW
0

RW
0

RW
0

RW
0

The AES_STATE register accesses a 16 byte internal data buffer. The buffer isaccessed by reading or writing 16 times to the same address location (AES_STATE). If
the buffer is not completely read or written an error occurs when an AES operation isstarted. Note that the AES_STATE register is cleared when entering the radiotransceiver SLEEP state.
• Bit 7:0 – AES_STATE7:0 - AES Plain and Cipher Text Buffer
These bits represent the data buffer for the AES operation.

9.12.4 AES_KEY – AES Encryption and Decryption Key Buffer Register
Bit

7

6

5

4

NA ($13F)
Read/Write
Initial Value

3

2

1

0

AES_KEY7:0
RW
0

RW
0

RW
0

RW
0

AES_KEY

RW
0

RW
0

RW
0

RW
0

The AES key register accesses a 128 Bit internal buffer that holds the Encryption or
Decryption Key. The AES_KEY buffer is a 16 Byte buffer. The buffer is accessed byreading or writing 16 fold to the same address location (AES_KEY). A read access toregisters AES_KEY returns the last round key of the preceding security operation. Thisis the key that is required for the corresponding ECB decryption operation after an ECB
encryption operation. However, the initial AES key written to the security module inadvance of an AES run is not modified during an AES operation. This initial key is used
for the next AES run even if it cannot be read from AES_KEY register. Note that the
AES_KEY register is cleared when entering the radio transceiver SLEEP state.
• Bit 7:0 – AES_KEY7:0 - AES Encryption/Decryption Key Buffer
These bits represent the data buffer for the AES Encryption/Decryption key.

9.12.5 TRX_STATUS – Transceiver Status Register
Bit

7

6

5

4

NA ($141)

CCA_DONECCA_STATUS

TST_STATUS

TRX_STATUS4

Read/Write
Initial Value

R
0

R
0

R
0

R
0

Bit

3

2

1

0

NA ($141)

TRX_STATUS3

TRX_STATUS2TRX_STATUS1TRX_STATUS0

Read/Write
Initial Value

R
0

R
0

R
0

R
0

TRX_STATUS

TRX_STATUS

This read-only register signals the present state of the radio transceiver as well as thestatus of the CCA operation. A state change is initiated by writing a state transition

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ATmega128RFA1
command to the TRX_CMD bits of register TRX_STATE. The register is not accessible
in SLEEP state.
• Bit 7 – CCA_DONE - CCA Algorithm Status
This bit indicates if a CCA request is completed. This is also indicated by a
TRX24_CCA_ED_DONE interrupt. Note that register bit CCA_DONE is cleared in
response to a CCA_REQUEST.
Table 9-30 CCA_DONE Register Bits
Register Bits

Value

Description

CCA_DONE0

CCA calculation not finished1

CCA calculation finished• Bit 6 – CCA_STATUS - CCA Status Result
The result of the CCA measurement is available in register bit CCA_STATUS after a
CCA request is completed. Note that register bit CCA_STATUS is cleared in response
to a CCA_REQUEST.
Table 9-31 CCA_STATUS Register Bits
Register Bits

Value

Description

CCA_STATUS

0Channel indicated as busy.

1

Channel indicated as idle.

• Bit 5 – TST_STATUS - Test mode status
This bit is reserved for internal use. It indicates the status of the test mode.
Table 9-32 TST_STATUS Register Bits
Register Bits

Value

Description

TST_STATUS

0

Test mode is disabled.

1

Test mode is active.

• Bit 4:0 – TRX_STATUS4:0 - Transceiver Main Status
The register bits TRX_STATUS signal the current radio transceiver status. Do not try toinitiate a further state change
while the radio transceiver is in
STATE_TRANSITION_IN_PROGRESS state. Values not listed in the following table
are reserved.
Table 9-33 TRX_STATUS Register Bits
Register Bits

Value

Description

0x01

BUSY_RX

0x02

BUSY_TX

0x06

RX_ON

0x08

TRX_OFF

0x09

PLL_ON

0x0F

SLEEP

0x11

BUSY_RX_AACK

0x12

BUSY_TX_ARET

0x16

RX_AACK_ON

0x19

TX_ARET_ON

TRX_STATUS4:0

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Register Bits

Value

Description

0x1F

STATE_TRANSITION_IN_PROGRESS

9.12.6 TRX_STATE – Transceiver State Control Register
Bit
NA ($142)76

5TRAC_STATUS2 TRAC_STATUS1 TRAC_STATUS04

TRX_CMD4

Read/Write
Initial Value

R
0

R
0

R
0

RW
0

Bit

3

2

1

0

NA ($142)

TRX_CMD3

TRX_CMD2

TRX_CMD1

TRX_CMD0

Read/Write
Initial Value

RW
0

RW
0

RW
0

RW
0

TRX_STATETRX_STATE

The states of the radio transceiver are controlled via register TRX_STATE using
register bits TRX_CMD. The read-only register bits TRAC_STATUS indicate the status
or result of an Extended Operating Mode transaction. A successful state transition shallbe confirmed by reading register bits TRX_STATUS. This register is used for both Basicand Extended Operating Mode.
• Bit 7:5 – TRAC_STATUS2:0 - Transaction Status
The status of the RX_AACK and TX_ARET procedure is indicated by register bits
TRAC_STATUS. TRAC_STATUS is only valid in Extended Operating Modes. Details of
the algorithm and a description of the status information are given in the RX_AACK_ON
and TX_ARET_ON sections of the data-sheet. Even though the reset value for register
bits TRAC_STATUS is 0, the RX_AACK and TX_ARET procedures set the register bits
to TRAC_STATUS = 7 (INVALID) when it is started. Not all status values are used inboth RX_AACK and TX_ARET transactions. In TX_ARET the status
SUCCESS_DATA_PENDING indicates a successful reception of an ACK frame withframe pending bit set to 1. In RX_AACK the status SUCCESS_WAIT_FOR_ACK
indicates an ACK frame is about to sent in RX_AACK slotted acknowledgment. Slotted
acknowledgment operation must be enabled with the SLOTTED_OPERATION bit ofregister XAH_CTRL_0. The application software must set the SLPTR bit of register
TRXPWR at the next back-off slot boundary in order to initiate a transmission of the
ACK frame. For details refer to IEEE 802.15.4-2006, chapter 5.5.4.1. Values not listed
in the following table are reserved.
Table 9-34 TRAC_STATUS Register Bits
Register Bits
TRAC_STATUS2:0

Value

Description

0

SUCCESS (RX_AACK, TX_ARET)

1

SUCCESS_DATA_PENDING (TX_ARET)

2

SUCCESS_WAIT_FOR_ACK (RX_AACK)3

CHANNEL_ACCESS_FAILURE (TX_ARET)

5

NO_ACK (TX_ARET)

7

INVALID (RX_AACK, TX_ARET)• Bit 4:0 – TRX_CMD4:0 - State Control Command

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A write access to register bits TRX_CMD initiates a state transition of the radiotransceiver towards the new state as defined by the write access. Do not try to initiate afurtherstatechange
while
the
radio
transceiverisin
STATE_TRANSITION_IN_PROGRESS
state
(see
TRX_STATUS
register).
FORCE_PLL_ON is not valid for the SLEEP state as well as during
STATE_TRANSITION_IN_PROGRESS towards the SLEEP state. Values not listed in
the following table are reserved and mapped to NOP.
Table 9-35 TRX_CMD Register Bits
Register Bits

Value

Description

TRX_CMD4:0

0x00

NOP

0x02

TX_START

0x03

FORCE_TRX_OFF

0x04

FORCE_PLL_ON

0x06

RX_ON

0x08

TRX_OFF

0x09

PLL_ON (TX_ON)

0x16

RX_AACK_ON

0x19

TX_ARET_ON

9.12.7 TRX_CTRL_0 – Reserved
Bit

7

6

5

4

3

2

1

0

NA ($143)

Res7

Res6

Res5

Res4

Res3

Res2

Res1

Res0

Read/Write
Initial Value

RW
0

RW
0

RW
0

RW
1

RW
1

RW
0

RW
0

RW
1

TRX_CTRL_0

This register is reserved for future use.
• Bit 7:0 – Res7:0 - Reserved
These bits are reserved for future use.

9.12.8 TRX_CTRL_1 – Transceiver Control Register 1
Bit

7

6

5

4

NA ($144)

PA_EXT_EN

IRQ_2_EXT_EN

TX_AUTO_CRC_ON

Res4

Read/Write
Initial Value

RW
0

RW
0

RW
1

R
0

3

2

1

0

NA ($144)

Res3

Res2

Res1

Res0

Read/Write
Initial Value

R
0

R
0

R
0

R
0

Bit

TRX_CTRL_1

TRX_CTRL_1

The TRX_CTRL_1 register is a multi purpose register to control various operating
modes and settings of the radio transceiver.
• Bit 7 – PA_EXT_EN - External PA support enable

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This register bit enables pin DIG3 and pin DIG4 to indicate the transmit state of theradio transceiver. The control of the external RF front-end is disabled when this bit is 0.
Both pins DIG3 and DIG4 are then low. The control of the external front-end is enabled
when this bit is 1. DIG3 and DIG4 then indicate the state of the radio transceiver. Pin
DIG3 is high and pin DIG4 is low in the state TX_BUSY. In all other states pin DIG3 is
low and pin DIG4 is high. It is recommended to set PA_EXT_EN=1 only in receive ortransmit states to reduce the power consumption or avoid leakage current of external
RF switches or other building blocks especially during SLEEP state.
• Bit 6 – IRQ_2_EXT_EN - Connect Frame Start IRQ to TC1
When this bit is set to one the capture input of Timer/Counter 1 is connected to the RX
frame start signal and pin DIG2 becomes an output, driving the RX frame start signal.
Antenna Diversity RF switch control (ANT_EXT_SW_EN=1) shall not be used at thesame time, because it shares the same device pin. The function IRQ_2_EXT_EN isavailable for alternate frame time stamping using Timer/Counter 1. In general thepreferred method for frame time stamping is using the symbol counter.
• Bit 5 – TX_AUTO_CRC_ON - Enable Automatic CRC Calculation
This register bit controls the automatic FCS generation for TX operations. The
automatic FCS algorithm is performed autonomously by the radio transceiver if register
bit TX_AUTO_CRC_ON=1.
• Bit 4:0 – Res4:0 - Reserved

9.12.9 PHY_TX_PWR – Transceiver Transmit Power Control Register
Bit

7

6

5

4

NA ($145)

PA_BUF_LT1

PA_BUF_LT0

PA_LT1

PA_LT0

Read/Write
Initial Value

RW
1

RW
1

RW
0

RW
0

Bit

3

2

1

0

NA ($145)

TX_PWR3

TX_PWR2

TX_PWR1

TX_PWR0

Read/Write
Initial Value

RW
0

RW
0

RW
0

RW
0

PHY_TX_PWR

PHY_TX_PWRThis register controls the output power and the ramping of the transmitter.
• Bit 7:6 – PA_BUF_LT1:0 - Power Amplifier Buffer Lead Time
These register bits control the enable lead time of the internal PA buffer relative to theenable time of the internal PA. This time is further used to derive a control signal for an
external RF front-end to switch between receive and transmit.
Table 9-36 PA_BUF_LT Register Bits
Register Bits

Value

Description

PA_BUF_LT1:0

0

0 µs

1

2 µs

2

4 µs

3

6 µs

• Bit 5:4 – PA_LT1:0 - Power Amplifier Lead Time
These register bits control the enable lead time of the internal power amplifier relative tothe beginning of the transmitted frame (SHR).

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Table 9-37 PA_LT Register Bits
Register Bits

Value

PA_LT1:0

Description

0

2 µs

1

4 µs

2

6 µs

3

8 µs

• Bit 3:0 – TX_PWR3:0 - Transmit Power Setting
These register bits determine the TX output power of the radio transceiver.
Table 9-38 TX_PWR Register Bits
Register Bits

Value

Description

TX_PWR3:00

3.0 dBm

1

2.8 dBm2

2.3 dBm3

1.8 dBm

4

1.3 dBm

5

0.7 dBm

6

0.0 dBm

7-1 dBm8-2 dBm9-3 dBm10-4 dBm11-5 dBm12-7 dBm13-9 dBm14-12 dBm

15-17 dBm

9.12.10 PHY_RSSI – Receiver Signal Strength Indicator Register
Bit

7

6

5

4

NA ($146)

RX_CRC_VALIDRND_VALUE1RND_VALUE0

RSSI4

Read/Write
Initial Value

R
0

R
0

R
0

R
0

Bit

3

2

1

0

NA ($146)

RSSI3

RSSI2

RSSI1

RSSI0

Read/Write
Initial Value

R
0

R
0

R
0

R
0

PHY_RSSI

PHY_RSSI

The PHY_RSSI register is a multi purpose register that indicates FCS validity, provides
random numbers and shows the current RSSI value.
• Bit 7 – RX_CRC_VALID - Received Frame CRC Status
Reading this register bit indicates whether the last received frame has a valid FCS ornot. The register bit is updated when issuing a TRX24_RX_END interrupt and remains

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valid until the next TRX24_RX_END interrupt is issued, caused by a new frame
reception.
Table 9-39 RX_CRC_VALID Register Bits
Register Bits

Value

Description

RX_CRC_VALID

0

CRC (FCS) not valid

1

CRC (FCS) valid• Bit 6:5 – RND_VALUE1:0 - Random Value
A 2-bit random value can be retrieved byreading register bits RND_VALUE. The value can be used for random numbers forsecurity applications. Note that the radio transceiver shall be in Basic Operating Modereceive state. The values are updated every 1 µs.
• Bit 4:0 – RSSI4:0 - Receiver Signal Strength Indicator
The result of the automated RSSI measurement is stored in these register bits. The
value is updated every 2µs in receive states. The read value is a number between 0
and 28 indicating the received signal strength as a linear curve on a logarithmic input
power scale (dBm) with a resolution of 3 dB. A RSSI value of 0 indicates a RF input
power lower than RSSI_BASE_VAL (-90 dBm). A value of 28 marks a power higher or
equal to -10 dBm.
Table 9-40 RSSI Register Bits
Register Bits

Value

RSSI4:0

Description0

Minimum RSSI value: P(RF) < -90 dBm

1

P(RF) = RSSI_BASE_VAL+3 · (RSSI-1)
[dBm]

2

...

28

Maximum RSSI value: P(RF) ≥ -10 dBm

9.12.11 PHY_ED_LEVEL – Transceiver Energy Detection Level Register
Bit

7

6

5

4

NA ($147)

ED_LEVEL7

ED_LEVEL6

ED_LEVEL5

ED_LEVEL4

Read/Write
Initial Value

R
1

R
1

R
1

R
1

Bit

3

2

1

0

NA ($147)

ED_LEVEL3

ED_LEVEL2

ED_LEVEL1

ED_LEVEL0

Read/Write
Initial Value

R
1

R
1

R
1

R
1

PHY_ED_LEVEL

PHY_ED_LEVELThis register contains the result of an Energy Detection measurement.
• Bit 7:0 – ED_LEVEL7:0 - Energy Detection Level
The minimum ED value (ED_LEVEL = 0) indicates a receiver power less than or equal
to RSSI_BASE_VAL. The range is 84 dB with a resolution of 1 dB and an absoluteaccuracy of ±5 dB. A manual ED measurement can be initiated by a write access to thisregister. A value of 0xFF signals that no measurement has yet been started (reset
value). The measurement duration is 8 symbol periods (128 µs) for a data rate of 250
kb/s. For High Data Rate Modes the automated measurement duration is reduced to 32

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ATmega128RFA1µs. For manually initiated ED measurements in these modes the measurement period isstill 128 µs as long as the receiver is in RX_ON state. A value other than 0xFF indicatesthe result of the last ED measurement.
Table 9-41 ED_LEVEL Register Bits
Register Bits

Value

Description

ED_LEVEL7:0

0x00

Minimum result of last ED measurement

0x01

P(RF) = RSSI_BASE_VAL+ED [dBm]

0x02

...

0x54

Maximum result of last ED measurement

0xFF

Reset value

9.12.12 PHY_CC_CCA – Transceiver Clear Channel Assessment (CCA) Control Register
Bit

7

6

5

4

NA ($148)

CCA_REQUESTCCA_MODE1

CCA_MODE0CHANNEL4

Read/Write
Initial Value

RW
0

RW
0

RW
1

RW
0

Bit

3

2

1

0

NA ($148)

CHANNEL3CHANNEL2CHANNEL1

CHANNEL0

Read/Write
Initial Value

RW
1

RW
0

RW
1

RW
1

PHY_CC_CCA

PHY_CC_CCA

This register is provided to initiate and control a CCA measurement.
• Bit 7 – CCA_REQUEST - Manual CCA Measurement Request
A manual CCA measurement is initiated with setting CCA_REQUEST=1. The end of
the CCA measurement is indicated by the TRX24_CCA_ED_DONE interrupt. Register
bits CCA_DONE and CCA_STATUS of register TRX_STATUS are updated after a
CCA_REQUEST. The register bit is automatically cleared after requesting a CCA
measurement with CCA_REQUEST=1.
• Bit 6:5 – CCA_MODE1:0 - Select CCA Measurement Mode
The CCA mode can be selected using these register bits. Note that IEEE 802.15.42006 CCA Mode 3 defines the logical combination of CCA Mode 1 and 2 with thelogical operators AND or OR. This can be selected with CCA_MODE=0 for logicaloperation OR and CCA_MODE=3 for logical operation AND.
Table 9-42 CCA_MODE Register Bits
Register Bits

Value

Description

CCA_MODE1:00Mode 3a, Carrier sense OR energy above
threshold1Mode 1, Energy above threshold2

Mode 2, Carrier sense only3

Mode 3b, Carrier sense AND energy above
threshold• Bit 4:0 – CHANNEL4:0 - RX/TX Channel Selection
These register bits define the RX/TX channel. The channel assignment is according toIEEE 802.15.4.

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Table 9-43 CHANNEL Register Bits
Register Bits

Value

Description

CHANNEL4:0

112405 MHz

12

2410 MHz

13

2415 MHz

142420 MHz

152425 MHz

16

2430 MHz17

2435 MHz

18

2440 MHz

192445 MHz20

2450 MHz

21

2455 MHz

22

2460 MHz

23

2465 MHz

24

2470 MHz

25

2475 MHz26

2480 MHz

9.12.13 CCA_THRES – Transceiver CCA Threshold Setting Register
Bit

7

6

NA ($149)

CCA_CS_THRES3

CCA_CS_THRES2

Read/Write
Initial Value

RW
1

RW
1

Bit

5

4

NA ($149)

CCA_CS_THRES1

CCA_CS_THRES0

Read/Write
Initial Value

RW
0

RW
0

Bit

3

2

NA ($149)

CCA_ED_THRES3

CCA_ED_THRES2

Read/Write
Initial Value

RW
0

RW
1

Bit

1

0

NA ($149)

CCA_ED_THRES1

CCA_ED_THRES0

Read/Write
Initial Value

RW
1

RW
1

CCA_THRES

CCA_THRES

CCA_THRES

CCA_THRES

This register sets the threshold level for the Energy Detection (ED) of the Clear Channel
Assessment (CCA).
• Bit 7:4 – CCA_CS_THRES3:0 - CS Threshold Level for CCA Measurement
These bits are reserved for internal use.
• Bit 3:0 – CCA_ED_THRES3:0 - ED Threshold Level for CCA Measurement

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These bits define the received power threshold of the Energy above thresholdalgorithm. The threshold is calculated by RSSI_BASE_VAL + 2CCA_ED_THRES[dBm]. Any received power above this level is interpreted as a busy channel.

9.12.14 RX_CTRL – Transceiver Receive Control Register
Bit

7

6

5

4

NA ($14A)

Resx7

Resx6

Resx5

Resx4

Read/Write
Initial Value

RW
1

RW
0

RW
1

RW
1

Bit

3

2

1

0

NA ($14A)

PDT_THRES3

PDT_THRES2

PDT_THRES1

PDT_THRES0

Read/Write
Initial Value

RW
0

RW
1

RW
1

RW
1

RX_CTRL

RX_CTRL

The register controls the sensitivity of the Antenna Diversity Mode. Note that in High
Data Rate modes the ACR module will always be disabled.
• Bit 7:4 – Resx7:4 - Reserved• Bit 3:0 – PDT_THRES3:0 - Receiver Sensitivity Control
These register bits control the sensitivity of the receiver correlation unit. If the Antenna
Diversity algorithm is enabled the value shall be set to PDT_THRES = 3. Otherwise it
shall be set back to the reset value. Values not listed in the following table are reserved.
Table 9-44 PDT_THRES Register Bits
Register Bits

Value

Description

PDT_THRES3:0

0x7

Reset value, to be used if Antenna Diversity
algorithm is disabled

0x3

Recommended correlator threshold forAntenna Diversity operation

9.12.15 SFD_VALUE – Start of Frame Delimiter Value Register
Bit

7

6

5

NA ($14B)
Read/Write
Initial Value

4

3

2

1

0

SFD_VALUE7:0
RW
1

RW
0

RW
1

RW
0

RW
0

SFD_VALUE
RW
1

RW
1

RW
1

This register contains the one octet start-of-frame delimiter (SFD) to synchronize to areceived frame. The lower 4 bits must not be all zero to avoid decoding conflicts.
• Bit 7:0 – SFD_VALUE7:0 - Start of Frame Delimiter Value
For compliant IEEE 802.15.4 networks set SFD_VALUE = 0xA7. This is the default
value of the register. To establish non IEEE 802.15.4 compliant networks the SFD value
can be changed to any other value. If enabled a RX_START interrupt is issued only if
the received SFD matches the register content of SFD_VALUE and a valid PHR is
received.

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Table 9-45 SFD_VALUE Register Bits
Register Bits

Value

Description

SFD_VALUE7:0

0xA7IEEE 802.15.4 compliant value of the SFD

9.12.16 TRX_CTRL_2 – Transceiver Control Register 2
Bit

7

6

5

4

NA ($14C)

RX_SAFE_MODE

Res4

Res3

Res2

Read/Write
Initial Value

RW
0

R
0

R
0

R
0

Bit

3

2

NA ($14C)

Res1

Res0

Read/Write
Initial Value

R
0

R
0

1

TRX_CTRL_2

0

OQPSK_DATA_RATE1 OQPSK_DATA_RATE0RW0TRX_CTRL_2

RW0This register controls the data rate setting of the radio transceiver.
• Bit 7 – RX_SAFE_MODE - RX Safe Mode
If this bit is set, the next received frame will be protected and not overwritten byfollowing frames. Set this bit to 0 to release the buffer (and set it again for further
protection).
• Bit 6:2 – Res4:0 - Reserved• Bit 1:0 – OQPSK_DATA_RATE1:0 - Data Rate Selection
A write access to these register bits sets the OQPSK PSDU data rate used by the radiotransceiver. The reset value OQPSK_DATA_RATE = 0 is the PSDU data rate according
to IEEE 802.15.4. All other values are used in High Data Rate Modes.
Table 9-46 OQPSK_DATA_RATE Register Bits
Register BitsValue

OQPSK_DATA_RATE1:0

Description

0

250 kb/s (IEEE 802.15.4 compliant)

1

500 kb/s

21000 kb/s

32000 kb/s

9.12.17 ANT_DIV – Antenna Diversity Control Register
Bit

7

6

5

4

NA ($14D)

ANT_SEL

Res2

Res1

Res0

Read/Write
Initial Value

R
0

R
0

R
0

R
0

Bit

3

2

1

0

NA ($14D)

ANT_DIV_EN

ANT_EXT_SW_EN

ANT_CTRL1

ANT_CTRL0

Read/Write
Initial Value

RW
0

RW
0

RW
1

RW
1

ANT_DIV

ANT_DIV

This register controls the Antenna Diversity.
• Bit 7 – ANT_SEL - Antenna Diversity Antenna Status
112

ATmega128RFA1
8266A-MCU Wireless-12/09

ATmega128RFA1This register bit signals the currently selected antenna path. The selection may bebased either on the last antenna diversity cycle (ANT_DIV_EN = 1) or on the content ofregister bits ANT_CTRL.
Table 9-47 ANT_SEL Register Bits
Register Bits
ANT_SEL

Value

Description

0

Antenna 0

1

Antenna 1• Bit 6:4 – Res2:0 - Reserved• Bit 3 – ANT_DIV_EN - Enable Antenna Diversity
If this register bit is set the Antenna Diversity algorithm is enabled. On reception of aframe the algorithm selects an antenna autonomously during SHR search. This
selection is kept until
1. a new SHR search starts or
2. receive states are left or
3. a manually programming of bits ANT_CTRL occurred. If ANT_DIV_EN = 1 the bit
ANT_EXT_SW_EN shall also be set to 1.
Table 9-48 ANT_DIV_EN Register Bits
Register Bits

Value

Description

ANT_DIV_EN

0

Antenna Diversity algorithm disabled

1

Antenna Diversity algorithm enabled• Bit 2 – ANT_EXT_SW_EN - Enable External Antenna Switch Control
If enabled, pin DIG1 and pin DIG2 become output pins and provide a differential control
signal for an external Antenna Diversity switch. The selection of a specific antenna isdone either by the automatic Antenna Diversity algorithm (ANT_DIV_EN = 1) or
according to bits ANT_CTRL if the Antenna Diversity algorithm is disabled. Do notenable Antenna Diversity RF switch control (ANT_EXT_SW_EN = 1) and RX Frame
Time Stamping (IRQ_2_EXT_EN = 1, see register TRX_CTRL_1) at the same time. If
this bit is set the control pins DIG1/DIG2 are activated in all radio transceiver states aslong as bit ANT_EXT_SW_EN is also set. If the radio transceiver is not in a receive ortransmit state, it is recommended to disable bit ANT_EXT_SW_EN to reduce the power
consumption or avoid leakage current of an external RF switch especially during
SLEEP state. The output pins DIG1 and DIG2 are pulled-down to digital ground if bit
ANT_EXT_SW_EN = 0.
Table 9-49 ANT_EXT_SW_EN Register Bits
Register Bits
ANT_EXT_SW_EN

Value

Description

0

Antenna Diversity RF switch control disabled

1

Antenna Diversity RF switch control enabled• Bit 1:0 – ANT_CTRL1:0 - Static Antenna Diversity Switch Control
These bits provide a static control of an Antenna Diversity switch. This register setting
defines the selected antenna if ANT_DIV_EN is set to 0 (Antenna Diversity disabled).
Register values 1 and 2 are valid for ANT_EXT_SW_EN = 1.
Table 9-50 ANT_CTRL Register Bits
Register Bits

Value

Description

ANT_CTRL1:0

0

Reserved

1

Antenna 1: DIG1=H, DIG2=L

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8266A-MCU Wireless-12/09

Register Bits

Value

Description

2

Antenna 0: DIG1=L, DIG2=H

3

Default value for ANT_EXT_SW_EN=0;
Mandatory setting for applications not using
Antenna Diversity

9.12.18 IRQ_MASK – Transceiver Interrupt Enable Register
Bit

7

6

5

4

NA ($14E)

AWAKE_EN

TX_END_EN

AMI_EN

CCA_ED_DONE_EN

Read/Write
Initial Value

RW
0

RW
0

RW
0

RW
0

Bit

3

2

1

0

NA ($14E)

RX_END_EN

RX_START_EN

PLL_UNLOCK_EN

PLL_LOCK_EN

Read/Write
Initial Value

RW
0

RW
0

RW
0

RW
0

IRQ_MASK

IRQ_MASK

This register is used to enable or disable individual interrupts of the radio transceiver.
An interrupt is enabled if the corresponding bit is set to 1. All interrupts are disabled
after the power up sequence or reset. If an interrupt is enabled it is recommended toread the interrupt status register IRQ_STATUS first to clear the history.
• Bit 7 – AWAKE_EN - Awake Interrupt Enable• Bit 6 – TX_END_EN - TX_END Interrupt Enable• Bit 5 – AMI_EN - Address Match Interrupt Enable• Bit 4 – CCA_ED_DONE_EN - End of ED Measurement Interrupt Enable• Bit 3 – RX_END_EN - RX_END Interrupt Enable• Bit 2 – RX_START_EN - RX_START Interrupt Enable• Bit 1 – PLL_UNLOCK_EN - PLL Unlock Interrupt Enable• Bit 0 – PLL_LOCK_EN - PLL Lock Interrupt Enable

9.12.19 IRQ_STATUS – Transceiver Interrupt Status Register
Bit

7

6

5

4

NA ($14F)

AWAKE

TX_ENDAMI

CCA_ED_DONE

Read/Write
Initial Value

RW
0

RW
0

RW
0

RW
0

Bit

3

2

1

0

NA ($14F)

RX_END

RX_START

PLL_UNLOCK

PLL_LOCK

Read/Write
Initial Value

RW
0

RW
0

RW
0

RW
0

IRQ_STATUS

IRQ_STATUS

This register contains the status of the pending interrupt requests. An interrupt is
pending if the associated bit has a value of one. Such a pending interrupts can be
manually cleared by writing a 1 to that register bit. Interrupts are automatically cleared
when the corresponding interrupt service routine is being executed.
• Bit 7 – AWAKE - Awake Interrupt Status
114

ATmega128RFA1
8266A-MCU Wireless-12/09

ATmega128RFA1• Bit 6 – TX_END - TX_END Interrupt Status• Bit 5 – AMI - Address Match Interrupt Status• Bit 4 – CCA_ED_DONE - End of ED Measurement Interrupt Status• Bit 3 – RX_END - RX_END Interrupt Status• Bit 2 – RX_START - RX_START Interrupt Status• Bit 1 – PLL_UNLOCK - PLL Unlock Interrupt Status• Bit 0 – PLL_LOCK - PLL Lock Interrupt Status

9.12.20 VREG_CTRL – Voltage Regulator Control and Status Register
Bit

7

6

5

4

NA ($150)

AVREG_EXT

AVDD_OK

Resx5

Resx4

Read/Write
Initial Value

RW
0

R
0

RW
0

RW
0

Bit

3

2

1

0

NA ($150)

Resx3

DVDD_OK

Resx1

Resx0

Read/Write
Initial Value

RW
0

R
0

RW
0

RW
0

VREG_CTRL

VREG_CTRL

This register controls the use of the voltage regulators and indicates their status.
• Bit 7 – AVREG_EXT - Use External AVDD Regulator
If set, this register bit disables the internal analog voltage regulator to apply an external
regulated 1.8V supply for the analog building blocks.
Table 9-51 AVREG_EXT Register Bits
Register Bits

Value

Description

AVREG_EXT0Internal AVDD voltage regulator for the
analog section is enabled.

1

Internal AVDD voltage regulator is disabled;use external regulated 1.8V supply voltage
for the analog section.

• Bit 6 – AVDD_OK - AVDD Supply Voltage Valid
This register bit indicates if the internal 1.8V regulated voltage supply AVDD has
settled. The bit is set to logic high if AVREG_EXT = 1.
Table 9-52 AVDD_OK Register Bits
Register Bits
AVDD_OK

Value

Description

0

Analog voltage regulator disabled or supply
voltage not stable1

Analog supply voltage has settled• Bit 5:3 – Resx5:3 - Reserved• Bit 2 – DVDD_OK - DVDD Supply Voltage Valid
This register bit indicates if the internal 1.8V regulated voltage supply DVDD has
settled. The bit is set to logic high if DVREG_EXT = 1.

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8266A-MCU Wireless-12/09

Table 9-53 DVDD_OK Register Bits
Register Bits

Value

Description

DVDD_OK

0

Digital voltage regulator disabled or supply
voltage not stable

1

Digital supply voltage has settled• Bit 1:0 – DVREG_TRIM1:0 - Reserved
Table 9-54 DVREG_TRIM Register Bits
Register Bits

Value

DVREG_TRIM1:0

Description

0

1.80V

1

1.75V

2

1.84V

3

1.88V

9.12.21 BATMON – Battery Monitor Control and Status Register
Bit

7

6

5

4

NA ($151)

BAT_LOW

BAT_LOW_EN

BATMON_OK

BATMON_HR

Read/Write
Initial Value

RW
0

RW
0

R
0

RW
0

Bit

3

2

1

0

NA ($151)

BATMON_VTH3

BATMON_VTH2

BATMON_VTH1

BATMON_VTH0

Read/Write
Initial Value

RW
0

RW
0

RW
1

RW
0

BATMONBATMON

This register configures the battery monitor to observe the supply voltage at EVDD. The
status of the EVDD supply voltage is accessible by reading bit BATMON_OK withrespect to the actual BATMON settings. Furthermore the Battery Monitor Interrupt canbe controlled with the bits BAT_LOW and BAT_LOW_EN similar to the function of the
IRQ_STATUS and IRQ_MASK register for other radio transceiver interrupts.
• Bit 7 – BAT_LOW - Battery Monitor Interrupt Status
A BATMON Interrupt is pending if this bit is set. Writing one to this bit if it has been at
one will clear the interrupt.
• Bit 6 – BAT_LOW_EN - Battery Monitor Interrupt Enable
The Battery Monitor Interrupt is enabled if this bit is set to one. The Battery Monitor will
not generate an interrupt if this bit is zero.
• Bit 5 – BATMON_OK - Battery Monitor Status
The register bit BATMON_OK indicates the level of the external supply voltage withrespect to the programmed threshold BATMON_VTH.
Table 9-55 BATMON_OK Register Bits
Register Bits

Value

Description

BATMON_OK

0

The battery voltage is below the threshold.

1

The battery voltage is above the threshold.

• Bit 4 – BATMON_HR - Battery Monitor Voltage Range
This bit sets the range and resolution of the battery monitor.

116

ATmega128RFA1
8266A-MCU Wireless-12/09

ATmega128RFA1
Table 9-56 BATMON_HR Register Bits
Register Bits

Value

Description

BATMON_HR

0

Enables the low range, see BATMON_VTH

1

Enables the high range, see BATMON_VTH• Bit 3:0 – BATMON_VTH3:0 - Battery Monitor Threshold Voltage
The threshold values for the battery monitor are set by these register bits according to
the following table.
Table 9-57 BATMON_VTH Register Bits
Register Bits

Value

Description

BATMON_VTH3:0

0x02.550V (BATMON_HR=1) 1.70V(BATMON_HR=0)

0x1

2.625V (BATMON_HR=1) 1.75V(BATMON_HR=0)0x2

2.700V (BATMON_HR=1) 1.80V(BATMON_HR=0)

0x3

2.775V (BATMON_HR=1) 1.85V(BATMON_HR=0)0x4

2.850V (BATMON_HR=1) 1.90V(BATMON_HR=0)

0x5

2.925V (BATMON_HR=1) 1.95V(BATMON_HR=0)

0x6

3.000V (BATMON_HR=1) 2.00V(BATMON_HR=0)

0x7

3.075V (BATMON_HR=1) 2.05V(BATMON_HR=0)

0x8

3.150V (BATMON_HR=1) 2.10V(BATMON_HR=0)

0x9

3.225V (BATMON_HR=1) 2.15V(BATMON_HR=0)0xA

3.300V (BATMON_HR=1) 2.20V(BATMON_HR=0)0xB

3.375V (BATMON_HR=1) 2.25V(BATMON_HR=0)0xC

3.450V (BATMON_HR=1) 2.30V(BATMON_HR=0)0xD

3.525V (BATMON_HR=1) 2.35V(BATMON_HR=0)0xE

3.600V (BATMON_HR=1) 2.40V(BATMON_HR=0)0xF

3.675V (BATMON_HR=1) 2.45V(BATMON_HR=0)

9.12.22 XOSC_CTRL – Crystal Oscillator Control Register
Bit

7

6

5

4

NA ($152)

XTAL_MODE3

XTAL_MODE2

XTAL_MODE1

XTAL_MODE0

Read/Write
Initial Value

RW
1

RW
1

RW
1

RW
1

XOSC_CTRL

117
8266A-MCU Wireless-12/09

Bit

3

2

1

0

NA ($152)

XTAL_TRIM3XTAL_TRIM2XTAL_TRIM1XTAL_TRIM0

Read/Write
Initial Value

RW
0

RW
0

RW
0

RW
0

XOSC_CTRL

This register controls the operation of the 16MHz crystal oscillator.
• Bit 7:4 – XTAL_MODE3:0 - Crystal Oscillator Operating Mode
These register bits set the operating mode of the 16 MHz crystal oscillator. For normal
operation the default value is set to XTAL_MODE = 0xF after reset. For use with an
external clock source it is recommended to set XTAL_MODE = 0x4.
Table 9-58 XTAL_MODE Register Bits
Register Bits

Value

Description

XTAL_MODE3:0

0x4

Internal crystal oscillator disabled; use
external reference frequency.

0xF

Internal crystal oscillator enabled; amplitude
regulation of oscillation enabled.

• Bit 3:0 – XTAL_TRIM3:0 - Crystal Oscillator Load Capacitance Trimming
These register bits control two internal capacitance arrays connected to pins XTAL1
and XTAL2. A capacitance value in the range from 0 pF to 4.5 pF is selectable with aresolution of 0.3 pF.
Table 9-59 XTAL_TRIM Register Bits
Register Bits

Value

Description

XTAL_TRIM3:0

0x0

0.0 pF, trimming capacitors disconnected

0x1

0.3 pF, trimming capacitor switched on

0x2

...

0xF

4.5 pF, trimming capacitor switched on

9.12.23 RX_SYN – Transceiver Receiver Sensitivity Control Register
Bit

118

7

6

NA ($155)

RX_PDT_DIS

Res2

Read/Write
Initial Value

RW
0

R
0

Bit

5

4

NA ($155)

Res1

Res0

Read/Write
Initial Value

R
0

R
0

Bit

3

2

NA ($155)

RX_PDT_LEVEL3

RX_PDT_LEVEL2

Read/Write
Initial Value

RW
0

RW
0

Bit

1

0

NA ($155)

RX_PDT_LEVEL1

RX_PDT_LEVEL0

Read/Write
Initial Value

RW
0

RW
0

RX_SYN

RX_SYN

RX_SYN

RX_SYN

ATmega128RFA1
8266A-MCU Wireless-12/09

ATmega128RFA1This register controls the sensitivity threshold of the receiver.
• Bit 7 – RX_PDT_DIS - Prevent Frame Reception
RX_PDT_DIS = 1 prevents the reception of a frame even if the radio transceiver is inreceive modes. An ongoing frame reception is not affected. This operation mode isindependent of the setting of register bits RX_PDT_LEVEL.
• Bit 6:4 – Res2:0 - Reserved• Bit 3:0 – RX_PDT_LEVEL3:0 - Reduce Receiver Sensitivity
These register bits reduce the receiver sensitivity such that frames with a RSSI level
below the RX_PDT_LEVEL threshold level are not received (RX_PDT_LEVEL>0). The
threshold level can be calculated according to the following formula: RX_THRES >RSSI_BASE_VAL+3·(RX_PDT_LEVEL-1), for RX_PDT_LEVEL>0. If register bits
RX_PDT_LEVEL>0 the current consumption of the receiver in states RX_ON and
RX_AACK_ON is reduced by 500 µA. If register bits RX_PDT_LEVEL=0 (reset value)
all frames with a valid SHR and PHR are received, independently of their signal
strength. Examples for certain register settings are given in the following table.
Table 9-60 RX_PDT_LEVEL Register Bits
Register Bits

Value

Description

RX_PDT_LEVEL3:0

0x0

RX_THRES ≤ RSSI_BASE_VAL (Reset
value); RSSI value not considered

0x1

RX_THRES > RSSI_BASE_VAL + 0 · 3;
RSSI > -90 dBm

0x2

...

0xE

RX_THRES > RSSI_BASE_VAL + 13 · 3;
RSSI > -51 dBm

0xF

RX_THRES > RSSI_BASE_VAL + 14 · 3;
RSSI > -48 dBm

9.12.24 XAH_CTRL_1 – Transceiver Acknowledgment Frame Control Register 1
Bit

7

6

5

NA ($157)

Res1

Res0

Read/Write
Initial Value

R
0

R
0

Bit

3

NA ($157)

Res

Read/Write
Initial Value

R
0

4

AACK_FLTR_RES_FT AACK_UPLD_RES_FT
RW
0
2

RW
0
1

AACK_ACK_TIME AACK_PROM_MODE
RW
0

XAH_CTRL_1

RW
0

0

Res

XAH_CTRL_1

R0

This register is a multi-purpose control register for various RX_AACK settings.
• Bit 7:6 – Res1:0 - Reserved Bit
This bit is reserved for future use. The result of a read access is undefined. The register
bit must always be written with the reset value.
• Bit 5 – AACK_FLTR_RES_FT - Filter Reserved FramesThis register bit shall only be set if AACK_UPLD_RES_FT = 1. If
AACK_FLTR_RES_FT = 1 reserved frame types are filtered similar to data frames as

119
8266A-MCU Wireless-12/09

specified in IEEE 802.15.4-2006. Reserved frame types are explained in IEEE 802.15.4
section 7.2.1.1.1. If AACK_FLTR_RES_FT = 0 a received, reserved frame is only
checked for a valid FCS.
• Bit 4 – AACK_UPLD_RES_FT - Process Reserved Frames
If AACK_UPLD_RES_FT = 1 received frames indicated as reserved are further
processed. A RX_END interrupt is generated if the FCS of those frames is valid. In
conjunction with the configuration bit AACK_FLTR_RES_FT set, these frames arehandled like IEEE 802.15.4 compliant data frames during RX_AACK transaction. An
AMI interrupt is issued if the address in the received frame matches the node address.
That means if a reserved frame passes the third level filter rules, an acknowledgment
frame is generated and transmitted if it was requested by the received frame. If this is
not wanted bit AACK_DIS_ACK in register CSMA_SEED_1 has to be set.
• Bit 3 – Res - Reserved Bit
This bit is reserved for future use. The result of a read access is undefined. The register
bit must always be written with the reset value.
• Bit 2 – AACK_ACK_TIME - Reduce Acknowledgment Time
According to IEEE 802.15.4, section 7.5.6.4.2 the transmission of an acknowledgment
frame shall commence 12 symbols (aTurnaroundTime) after the reception of the last
symbol of a data or MAC command frame. This is achieved with the reset value of theregister bit AACK_ACK_TIME. If AACK_ACK_TIME = 1 an acknowledgment frame isalternatively sent already 2 symbol periods (32 µs) after the reception of the last symbolof a data or MAC command frame. This may be applied to proprietary networks or
networks using the High Data Rate Modes to increase battery lifetime and to improve
the overall data throughput. This setting affects also to acknowledgment frame
response time for slotted acknowledgment operation.
Table 9-61 AACK_ACK_TIME Register Bits
Register Bits

Value

AACK_ACK_TIME

Description

0

12 symbols acknowledgment time

1

2 symbols acknowledgment time

• Bit 1 – AACK_PROM_MODE - Enable Promiscuous Mode
This register bit enables the promiscuous mode within the RX_AACK mode; refer toIEEE 802.15.4-2006 chapter 7.5.6.5. If this bit is set, every incoming frame with a valid
PHR finishes with a RX_END interrupt even if the third level filter rules do not match or
the FCS is not valid. The bit RX_CRC_VALID of register PHY_RSSI is set accordingly.
If this bit is set and a frame passes the third level filter rules, an acknowledgment frame
is generated and transmitted unless disabled by bit AACK_DIS_ACK of register
CSMA_SEED_1.
• Bit 0 – Res - Reserved Bit
This bit is reserved for future use. The result of a read access is undefined. The register
bit must always be written with the reset value.

9.12.25 FTN_CTRL – Transceiver Filter Tuning Control Register
Bit

120

7

6

5

4

NA ($158)

FTN_START

Resx6

Resx5

Resx4

Read/Write
Initial Value

RW
0

RW
1

RW
0

RW
1

FTN_CTRL

ATmega128RFA1
8266A-MCU Wireless-12/09

ATmega128RFA1
Bit

3

2

1

0

NA ($158)

Resx3

Resx2

Resx1

Resx0

Read/Write
Initial Value

RW
1

RW
0

RW
0

RW
0

FTN_CTRLThis register controls the operation of the calibration loop of the filter tuning network.
• Bit 7 – FTN_START - Start Calibration Loop of Filter Tuning Network
FTN_START = 1 initiates the calibration of the filter tuning network. When thecalibration cycle has finished after at most 25 µs the register bit is automatically reset to0.
• Bit 6:0 – Resx6:0 - Reserved

9.12.26 PLL_CF – Transceiver Center Frequency Calibration Control Register
Bit

7

6

NA ($15A)

PLL_CF_START

Resx6

Read/Write
Initial Value

RW
0

RW
1

Bit

5

4

NA ($15A)

Resx5

Resx4

Read/Write
Initial Value

RW
0

RW
1

Bit

3

2

NA ($15A)

Resx3

Resx2

Read/Write
Initial Value

RW
0

RW
1

Bit

1

0

NA ($15A)

Resx1

Resx0

Read/Write
Initial Value

RW
1

RW
1

PLL_CF

PLL_CF

PLL_CF

PLL_CF

This register controls the operation of the center frequency calibration loop.
• Bit 7 – PLL_CF_START - Start Center Frequency Calibration
PLL_CF_START = 1 initiates the center frequency calibration. The calibration cycle has
finished after 35 µs (typical). The register bit is cleared immediately after finishing thecalibration.
• Bit 6:0 – Resx6:0 - Reserved

9.12.27 PLL_DCU – Transceiver Delay Cell Calibration Control Register
Bit

7

6

5

4

NA ($15B)

PLL_DCU_START

Resx6

Resx5

Resx4

Read/Write
Initial Value

RW
0

R
0

RW
1

RW
0

PLL_DCU

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Bit

3

2

1

0

NA ($15B)

Resx3

Resx2

Resx1

Resx0

Read/Write
Initial Value

RW
0

RW
0

RW
0

RW
0

PLL_DCU

This register controls the operation of the calibration loop of the delay cell.
• Bit 7 – PLL_DCU_START - Start Delay Cell Calibration
PLL_DCU_START = 1 initiates the delay cell calibration. The calibration cycle has
finished after at most 6 µs. The register bit is cleared immediately after finishing thecalibration.
• Bit 6:0 – Resx6:0 - Reserved

9.12.28 PART_NUM – Device Identification Register (Part Number)
Bit

7

6

5

NA ($15C)
Read/Write
Initial Value

4

3

2

1

0

PART_NUM7:0
R
1

R
0

R
0

R
0

PART_NUM

R
0

R
0

R
1

R
1

This register contains the part number of the device.
• Bit 7:0 – PART_NUM7:0 - Part Number
These bits decode the part number of the device according to the following table.
Table 9-62 PART_NUM Register Bits
Register Bits

Value

Description

PART_NUM7:0

0x83

ATmega128RFA1 part number

9.12.29 VERSION_NUM – Device Identification Register (Version Number)
Bit

7

6

5

R
0

R
0

R
0

NA ($15D)
Read/Write
Initial Value

4

3

2

1

0

R
0

R
0

R
0

VERSION_NUM7:0
R
0

R
0

VERSION_NUM

This register contains the version number of the device. The device identification
overwrites the Reset value.
• Bit 7:0 – VERSION_NUM7:0 - Version Number
These bits decode the version number of the device according to the following table.
Table 9-63 VERSION_NUM Register Bits
Register Bits
VERSION_NUM7:0

122

Value

Description

2

Revision AB

3

Revision C

4

Revision D

ATmega128RFA1
8266A-MCU Wireless-12/09

ATmega128RFA1
9.12.30 MAN_ID_0 – Device Identification Register (Manufacture ID Low Byte)
Bit

7

6

5

NA ($15E)

4

3

2

1

0

MAN_ID_07:00

Read/Write
Initial Value

R
0

R
0

R
0

R
1

MAN_ID_0

R
1

R
1

R
1

R
1

Bits [7:0] of the 32-bit JEDEC manufacturer ID are stored in this register. Bits [15:8] arestored in register MAN_ID_1. The highest 16 bits of the JEDEC ID are not stored inregisters.
• Bit 7:0 – MAN_ID_07:00 - Manufacturer ID (Low Byte)
These bits contain bits [7:0] of the 32-bit JEDEC manufacturer ID.
Table 9-64 MAN_ID_0 Register Bits
Register Bits

Value

Description

MAN_ID_07:00

0x1f

Atmel JEDEC manufacturer ID, bits [7:0] of
32 bit manufacturer ID: 00 00 00 1F

9.12.31 MAN_ID_1 – Device Identification Register (Manufacture ID High Byte)
Bit

7

6

5

NA ($15F)

4

3

2

1

0

MAN_ID_17:10

Read/Write
Initial Value

R
0

R
0

R
0

R
0

MAN_ID_1

R
0

R
0

R
0

R
0

Bits [15:8] of the 32-bit JEDEC manufacturer ID are stored in this register. Bits [7:0] arestored in register MAN_ID_0. The highest 16 bits of the JEDEC ID are not stored inregisters.
• Bit 7:0 – MAN_ID_17:10 - Manufacturer ID (High Byte)
These bits contain bits [15:8] of the 32-bit JEDEC manufacturer ID.
Table 9-65 MAN_ID_1 Register Bits
Register Bits

Value

Description

MAN_ID_17:10

0x00

Atmel JEDEC manufacturer ID, bits [15:8] of
32 bit manufacturer ID: 00 00 00 1F

9.12.32 SHORT_ADDR_0 – Transceiver MAC Short Address Register (Low Byte)
Bit

7

6

5

NA ($160)
Read/Write
Initial Value

4

3

2

1

0

SHORT_ADDR_07:00
RW
1

RW
1

RW
1

RW
1

RW
1

SHORT_ADDR_0
RW
1

RW
1

RW
1

This register contains the lower 8 bits of the MAC short address for Frame Filter
address recognition.
• Bit 7:0 – SHORT_ADDR_07:00 - MAC Short Address
These bits contain the bits [7:0] of the MAC short address.

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9.12.33 SHORT_ADDR_1 – Transceiver MAC Short Address Register (High Byte)
Bit

7

6

5

NA ($161)
Read/Write
Initial Value

4

3

2

1

0

SHORT_ADDR_17:10
RW
1

RW
1

RW
1

RW
1

RW
1

SHORT_ADDR_1
RW
1

RW
1

RW
1

This register contains the upper 8 bits of the MAC short address for Frame Filter
address recognition.
• Bit 7:0 – SHORT_ADDR_17:10 - MAC Short Address
These bits contain the bits [15:8] of the MAC short address.

9.12.34 PAN_ID_0 – Transceiver Personal Area Network ID Register (Low Byte)
Bit

7

6

5

NA ($162)
Read/Write
Initial Value

4

3

2

1

0

PAN_ID_07:00
RW
1

RW
1

RW
1

RW
1

RW
1

PAN_ID_0
RW
1

RW
1

RW
1

This register contains the lower 8 bits of the MAC PAN ID for Frame Filter address
recognition.
• Bit 7:0 – PAN_ID_07:00 - MAC Personal Area Network ID
These bits contain the bits [7:0] of the MAC PAN ID.

9.12.35 PAN_ID_1 – Transceiver Personal Area Network ID Register (High Byte)
Bit

7

6

5

NA ($163)
Read/Write
Initial Value

4

3

2

1

0

PAN_ID_17:10
RW
1

RW
1

RW
1

RW
1

RW
1

PAN_ID_1
RW
1

RW
1

RW
1

This register contains the upper 8 bits of the MAC PAN ID for Frame Filter address
recognition.
• Bit 7:0 – PAN_ID_17:10 - MAC Personal Area Network ID
These bits contain the bits [15:8] of the MAC PAN ID.

9.12.36 IEEE_ADDR_0 – Transceiver MAC IEEE Address Register 0
Bit

7

6

5

NA ($164)
Read/Write
Initial Value

124

4

3

2

1

0

IEEE_ADDR_07:00
RW
0

RW
0

RW
0

RW
0

RW
0

IEEE_ADDR_0
RW
0

RW
0

RW
0

ATmega128RFA1
8266A-MCU Wireless-12/09

ATmega128RFA1This register contains the bits [7:0] of the MAC IEEE address for Frame Filter address
recognition.
• Bit 7:0 – IEEE_ADDR_07:00 - MAC IEEE Address
These bits map to the bits [7:0] of the 64 bit MAC IEEE address.

9.12.37 IEEE_ADDR_1 – Transceiver MAC IEEE Address Register 1
Bit

7

6

5

NA ($165)
Read/Write
Initial Value

4

3

2

1

0

IEEE_ADDR_17:10
RW
0

RW
0

RW
0

RW
0

RW
0

IEEE_ADDR_1
RW
0

RW
0

RW
0

This register contains the bits [15:8] of the MAC IEEE address for Frame Filter address
recognition.
• Bit 7:0 – IEEE_ADDR_17:10 - MAC IEEE Address
These bits map to the bits [15:8] of the 64 bit MAC IEEE address.

9.12.38 IEEE_ADDR_2 – Transceiver MAC IEEE Address Register 2
Bit

7

6

5

NA ($166)
Read/Write
Initial Value

4

3

2

1

0

IEEE_ADDR_27:20
RW
0

RW
0

RW
0

RW
0

RW
0

IEEE_ADDR_2
RW
0

RW
0

RW
0

This register contains the bits [23:16] of the MAC IEEE address for Frame Filter
address recognition.
• Bit 7:0 – IEEE_ADDR_27:20 - MAC IEEE Address
These bits map to the bits [23:16] of the 64 bit MAC IEEE address.

9.12.39 IEEE_ADDR_3 – Transceiver MAC IEEE Address Register 3
Bit

7

6

5

RW
0

RW
0

RW
0

NA ($167)
Read/Write
Initial Value

4

3

2

1

0

RW
0

RW
0

RW
0

IEEE_ADDR_37:30
RW
0

RW
0

IEEE_ADDR_3

This register contains the bits [31:24] of the MAC IEEE address for Frame Filter
address recognition.
• Bit 7:0 – IEEE_ADDR_37:30 - MAC IEEE Address
These bits map to the bits [31:24] of the 64 bit MAC IEEE address.

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9.12.40 IEEE_ADDR_4 – Transceiver MAC IEEE Address Register 4
Bit

7

6

5

NA ($168)
Read/Write
Initial Value

4

3

2

1

0

IEEE_ADDR_47:40
RW
0

RW
0

RW
0

RW
0

RW
0

IEEE_ADDR_4
RW
0

RW
0

RW
0

This register contains the bits [39:32] of the MAC IEEE address for Frame Filter
address recognition.
• Bit 7:0 – IEEE_ADDR_47:40 - MAC IEEE Address
These bits map to the bits [39:32] of the 64 bit MAC IEEE address.

9.12.41 IEEE_ADDR_5 – Transceiver MAC IEEE Address Register 5
Bit

7

6

5

NA ($169)
Read/Write
Initial Value

4

3

2

1

0

IEEE_ADDR_57:50
RW
0

RW
0

RW
0

RW
0

RW
0

IEEE_ADDR_5
RW
0

RW
0

RW
0

This register contains the bits [47:40] of the MAC IEEE address for Frame Filter
address recognition.
• Bit 7:0 – IEEE_ADDR_57:50 - MAC IEEE Address
These bits map to the bits [47:40] of the 64 bit MAC IEEE address.

9.12.42 IEEE_ADDR_6 – Transceiver MAC IEEE Address Register 6
Bit

7

6

5

NA ($16A)
Read/Write
Initial Value

4

3

2

1

0

IEEE_ADDR_67:60
RW
0

RW
0

RW
0

RW
0

RW
0

IEEE_ADDR_6
RW
0

RW
0

RW
0

This register contains the bits [55:48] of the MAC IEEE address for Frame Filter
address recognition.
• Bit 7:0 – IEEE_ADDR_67:60 - MAC IEEE Address
These bits map to the bits [55:48] of the 64 bit MAC IEEE address.

9.12.43 IEEE_ADDR_7 – Transceiver MAC IEEE Address Register 7
Bit

7

6

5

NA ($16B)
Read/Write
Initial Value

4

3

2

1

0

IEEE_ADDR_77:70
RW
0

RW
0

RW
0

RW
0

RW
0

IEEE_ADDR_7
RW
0

RW
0

RW
0

This register contains the bits [63:56] of the MAC IEEE address for Frame Filter
address recognition.
126

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ATmega128RFA1• Bit 7:0 – IEEE_ADDR_77:70 - MAC IEEE Address
These bits map to the bits [63:56] of the 64 bit MAC IEEE address.

9.12.44 XAH_CTRL_0 – Transceiver Extended Operating Mode Control Register
Bit

7

6

NA ($16C)

MAX_FRAME_RETRIES3

MAX_FRAME_RETRIES2

Read/Write
Initial Value

RW
0

RW
0

Bit

5

4

NA ($16C)

MAX_FRAME_RETRIES1

MAX_FRAME_RETRIES0

Read/Write
Initial Value

RW
1

RW
1

Bit

3

2

NA ($16C)

MAX_CSMA_RETRIES2

MAX_CSMA_RETRIES1

Read/Write
Initial Value

RW
1

RW
0

Bit

1

0

NA ($16C)

MAX_CSMA_RETRIES0SLOTTED_OPERATION

Read/Write
Initial Value

RW
0

RW
0

XAH_CTRL_0

XAH_CTRL_0

XAH_CTRL_0

XAH_CTRL_0

This register is used to control various settings of the Extended Operating Mode.
• Bit 7:4 – MAX_FRAME_RETRIES3:0 - Maximum Number of Frame Retransmission Attempts
The setting of MAX_FRAME_RETRIES in TX_ARET mode specifies the number ofattempts to retransmit a frame when it was not acknowledged by the recipient. The
transaction gets canceled if the number of attempts exceeds MAX_FRAME_RETRIES.
Table 9-66 MAX_FRAME_RETRIES Register Bits
Register Bits

Value

Description

MAX_FRAME_RETRIES3:0

0x0

Retransmission of frame is not attempted.

0x1

Retransmission of frame is attempted once.

0x2

...

0xF

Retransmission of frame is attempted 15
times.

• Bit 3:1 – MAX_CSMA_RETRIES2:0 - Maximum Number of CSMA-CA Procedure
Repetition Attempts
MAX_CSMA_RETRIES specifies the number of retries in TX_ARET mode to repeat the
CSMA-CA procedure before the transaction gets canceled. According to IEEE 802.15.4
the valid range of MAX_CSMA_RETRIES is 0 to 5. A value of MAX_CSMA_RETRIES =7 initiates an immediate frame transmission without performing CSMA-CA. This may
especially be required for slotted acknowledgment operation. MAX_CSMA_RETRIES =6 is reserved.

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Table 9-67 MAX_CSMA_RETRIES Register Bits
Register Bits

Value

Description

MAX_CSMA_RETRIES2:0

0x0

No repetition of CSMA-CA procedure

0x1

One repetition of CSMA-CA procedure

0x2

...

0x5

Five repetitions (highest IEEE 802.15.4
compliant value)

0x6

Reserved

0x7

Immediate frame re-transmission without
performing CSMA-CA• Bit 0 – SLOTTED_OPERATION - Set Slotted Acknowledgment
When using RX_AACK mode in networks operating in beacon or slotted mode
accordingtoIEEE
802.15.4-2006,
chapter
5.5.1
theregisterbit
SLOTTED_OPERATION indicates that acknowledgment frames are to be sent on backoff slot boundaries (slotted acknowledgment). If this register bit is set theacknowledgment frame transmission has to be initiated by the application software
using bit SLPTR of register TRXPR. This waiting state is signaled in sub register
TRAC_STATUS of register TRX_STATE with value SUCCESS_WAIT_FOR_ACK.
Table 9-68 SLOTTED_OPERATION Register Bits
Register Bits

Value

SLOTTED_OPERATION

Description0

The radio transceiver operates in unslottedmode. An acknowledgment frame isautomatically sent if requested.

1

The transmission of an acknowledgment
frame has to be controlled by the
microcontroller.

9.12.45 CSMA_SEED_0 – Transceiver CSMA-CA Random Number Generator Seed Register
Bit

7

6

5

NA ($16D)
Read/Write
Initial Value

4

3

2

1

0

CSMA_SEED_07:00
RW
1

RW
1

RW
1

RW
0

RW
1

CSMA_SEED_0
RW
0

RW
1

RW
0

This register contains the lower 8 bits of the CSMA_SEED. The upper 3 bits are part ofregister CSMA_SEED_1. CSMA_SEED is the seed for the random number generationthat determines the length of the back-off period in the CSMA-CA algorithm. It is
recommended to initialize registers CSMA_SEED by random values. This can be doneusing the bits RND_VALUE of register PHY_RSSI.
• Bit 7:0 – CSMA_SEED_07:00 - Seed Value for CSMA Random Number
Generator
These bits contain the bits [7:0] of the CSMA_SEED.

128

ATmega128RFA1
8266A-MCU Wireless-12/09

ATmega128RFA1
9.12.46 CSMA_SEED_1 – Transceiver Acknowledgment Frame Control Register 2
Bit

7

6

NA ($16E)

AACK_FVN_MODE1

AACK_FVN_MODE0

Read/Write
Initial Value

RW
0

RW
1

Bit

5

4

NA ($16E)

AACK_SET_PD

AACK_DIS_ACK

Read/Write
Initial Value

RW
0

RW
0

Bit

3

2

NA ($16E)

AACK_I_AM_COORD

CSMA_SEED_12

Read/Write
Initial Value

RW
0

RW
0

Bit

1

0

NA ($16E)

CSMA_SEED_11

CSMA_SEED_10

Read/Write
Initial Value

RW
1

RW
0

CSMA_SEED_1

CSMA_SEED_1

CSMA_SEED_1

CSMA_SEED_1

This register is a control register for RX_AACK and contains a part of the CSMA_SEED
for the CSMA-CA algorithm.
• Bit 7:6 – AACK_FVN_MODE1:0 - Acknowledgment Frame Filter Mode
The frame control field of the MAC header (MHR) contains a frame version subfield.
The setting of AACK_FVN_MODE specifies the frame filtering behavior of the radiotransceiver. According to the content of these register bits the radio transceiver passes
frames with a specific frame version number, number group or independent of theframe version number. Thus the register bits AACK_FVN_MODE define the maximum
acceptable frame version. Received frames with a higher frame version number thanconfigured do not pass the address filter and are not acknowledged.
Table 9-69 AACK_FVN_MODE Register Bits
Register Bits
AACK_FVN_MODE1:0

Value

Description

0

Acknowledge frames with version number 0

1

Acknowledge frames with version number 0
or 1

2

Acknowledge frames with version number 0
or 1 or 2

3

Acknowledge frames independent of frame
version number• Bit 5 – AACK_SET_PD - Set Frame Pending Sub-field
The content of AACK_SET_PD bit is copied into the frame pending subfield of theacknowledgment frame if the acknowledgment is the answer to a data request MAC
command frame. If in addition the bits AACK_FVN_MODE of this register are
configured to accept frames with a frame version other than 0 or 1, the content ofregister bit AACK_SET_PD is also copied into the frame pending subfield of theacknowledgment frame for any MAC command frame with a frame version of 2 or 3 thathave the security enabled subfield set to 1. This is done in the assumption that a futureversion of the IEEE 802.15.4 standard might change the length or structure of theauxiliary security header, so that it is not possible to safely detect whether the MAC
command frame is actually a data request command or not.
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• Bit 4 – AACK_DIS_ACK - Disable Acknowledgment Frame Transmission
If this bit is set no acknowledgment frames are transmitted in RX_AACK Extended
Operating Mode even if requested.
• Bit 3 – AACK_I_AM_COORD - Set Personal Area Network Coordinator
This register bit has to be set if the node is a PAN coordinator. It is used for addressfiltering in RX_AACK.
• Bit 2:0 – CSMA_SEED_12:10 - Seed Value for CSMA Random Number
Generator
These bits contain the bits [10:8] of the CSMA_SEED. The lower part is defined inregister CSMA_SEED_0. See register CSMA_SEED_0 for details.

9.12.47 CSMA_BE – Transceiver CSMA-CA Back-off Exponent Control Register
Bit

7

6

5

4

NA ($16F)

MAX_BE3

MAX_BE2

MAX_BE1

MAX_BE0

Read/Write
Initial Value

RW
0

RW
1

RW
0

RW
1

Bit

3

2

1

0

NA ($16F)

MIN_BE3

MIN_BE2MIN_BE1MIN_BE0

Read/Write
Initial Value

RW
0

RW
0

RW
1

RW
1

CSMA_BE

CSMA_BEThis register controls the back-off exponent for the CSMA-CA procedure.
• Bit 7:4 – MAX_BE3:0 - Maximum Back-off Exponent
These register bits define the maximum back-off exponent used in the CSMA-CA
algorithm to generate a pseudo random number for back off the CCA. For details refer
to IEEE 802.15.4-2006, section 7.5.1.4. Valid values are 3 to 8.
Table 9-70 MAX_BE Register Bits
Register Bits

Value

Description

MAX_BE3:0

1

This value is not valid for the maximum
back-off exponent.

2This value is not valid for the maximum
back-off exponent.

3

Minimum, IEEE compliant value for the
maximum back-off exponent.

4

...

8

Maximum, IEEE compliant value for the
maximum back-off exponent.

• Bit 3:0 – MIN_BE3:0 - Minimum Back-off Exponent
These register bits define the minimum back-off exponent used in the CSMA-CA
algorithm to generate a pseudo random number for back off the CCA. For details refer
to IEEE 802.15.4-2006, section 7.5.1.4. Valid values are MAX_BE, MAX_BE-1), ..., 0.
If MIN_BE = 0 and MAX_BE = 0 the CCA back off period is always set to 0.

130

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ATmega128RFA1
Table 9-71 MIN_BE Register Bits
Register Bits

Value

Description

MIN_BE3:00

Minimum value of minimum back-off
exponent.

1

...

8

Maximum value of minimum back-off
exponent. MIN_BE must be smaller or equal
to MAX_BE.

9.12.48 TST_CTRL_DIGI – Transceiver Digital Test Control Register
Bit

7

6

NA ($176)

Resx7

Resx6

Read/Write
Initial Value

RW
0

RW
0

Bit

5

4

NA ($176)

Resx5

Resx4

Read/Write
Initial Value

RW
0

RW
0

Bit

3

2

NA ($176)

TST_CTRL_DIG3

TST_CTRL_DIG2

Read/Write
Initial Value

RW
0

RW
0

Bit

1

0

NA ($176)

TST_CTRL_DIG1

TST_CTRL_DIG0

Read/Write
Initial Value

RW
0

RW
0

TST_CTRL_DIGITST_CTRL_DIGITST_CTRL_DIGITST_CTRL_DIGI

This register takes part in the activation sequence of the continuous transmission test
mode. Other functionality of this register is reserved for internal use.
• Bit 7:4 – Resx7:4 - Reserved• Bit 3:0 – TST_CTRL_DIG3:0 - Digital Test Controller Register
This sub-register selects a test controller function. All values not listed int the following
table are reserved for internal use.
Table 9-72 TST_CTRL_DIG Register Bits
Register Bits

Value

TST_CTRL_DIG3:0

Description

0

NORMAL (no test is active)

15

TST_CONT_TX (continuous transmit)

9.12.49 TST_RX_LENGTH – Transceiver Received Frame Length Register
Bit

7

6

5

4

NA ($17B)

RX_LENGTH7

RX_LENGTH6

RX_LENGTH5

RX_LENGTH4

Read/Write
Initial Value

RW
0

RW
0

RW
0

RW
0

TST_RX_LENGTH

131
8266A-MCU Wireless-12/09

Bit

3

2

1

0

NA ($17B)

RX_LENGTH3

RX_LENGTH2

RX_LENGTH1

RX_LENGTH0

Read/Write
Initial Value

RW
0

RW
0

RW
0

RW
0

TST_RX_LENGTH

This register contains the frame length information of a received frame. This information
is not stored in the frame buffer. The frame length information is written to this register
after the last received octet.
• Bit 7:0 – RX_LENGTH7:0 - Received Frame Length
These bits contain the length of the last received frame.

9.12.50 TRXFBST – Start of frame buffer
Bit

7

6

5

4

RW
0

RW
0

RW
0

RW
0

NA ($180)
Read/Write
Initial Value

3

2

1

0

RW
0

RW
0

RW
0

TRXFBST7:0
RW
0

TRXFBSTFirst byte of the 128 byte long frame buffer of the TRX24.
• Bit 7:0 – TRXFBST7:0 - Frame Buffer Start Byte

9.12.51 TRXFBEND – End of frame buffer
Bit

7

6

5

NA ($1FF)
Read/Write
Initial Value

4

3

2

1

0

TRXFBEND7:0
RW
0

RW
0

RW
0

RW
0

RW
0

TRXFBEND
RW
0

RW
0

RW
0

This register is the last byte of the 128 byte long frame buffer of the radio transceiver.
• Bit 7:0 – TRXFBEND7:0 - Frame Buffer End Byte

132

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ATmega128RFA1
10 MAC Symbol Counter10.1 Main Features
The MAC symbol counter provides symbol timing information for IEEE 802.15.4
wireless networks. The counter time base can be derived from the 16 MHz crystal or
the RTC (32.768 kHz crystal on TOSC) during operation. In deep-sleep mode thecounter operates from the RTC clock. The module provides the following features:• Backoff slot counter with interrupt generation• Counter clock source selection between XTAL1 (16 MHz) and TOSC1 (RTC)• Automatic RTC clock selection for sleep mode operation and automatic
fallback• 3 independent compare units with relative and absolute compare mode andinterrupt generation (support for slotted operation and superframe handling)• Low-power, deep-sleep mode operation and system wake up with all symbol
counter interrupt events• Automatic SFD and incoming beacon timestamping• Manual beacon timestamping• Manual timer synchronization within a 16 µs symbol period by resetting clockprescaler and backoff slot counter• Atomic read/write access for 32 bit registers

10.2 Clock source selection and Sleep/Active mode operation
The symbol counter can be sourced by the transceiver clock or by the asynchronousReal Time Clock (RTC) oscillator. If the transceiver goes from active mode into sleep
mode, the symbol counter clock source is switched to the RTC clock automatically. A
clock source change is indicated in the bit SCCKSEL of Register "SCCR0 – SymbolCounter Control Register 0" on page 143 . The bit SCCKSEL can not be written if theradio tranceiver is in SLEEP mode.
After wake up, the counter switches back to the clock source which was selected before
going to sleep mode. Switching the clock source from RTC to 16 MHz resets the 16
MHz clock prescaler. This makes sure, that after switching back the clock source, thesymbol counter starts counting with a full 16 µs symbol period.
The clock source can be selected with bit SCCKSEL in the SCCR0 Register10.3 32 bit Register Access (Atomic Read/Write)
All 32 bit registers support atomic read or write operation. That means reading or writing
the least significant xxxLL byte (the register name ends in LL) updates or captures thecomplete 32 bit value.
Read Access: 1. Reading the LL-Byte captures the 32 bit value in a temporary register
2. Read the upper 3 bytes
Write Access: 1. Write the upper 3 byte
2. Writing the LL-Byte stores the 32 bit value in the counter registers
The same temporary register is used for all 32 bit register of the MAX symbol counter.

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10.4 Symbol Counter (32 bit, SCCNT)The symbol counter is a 32 bit counter which can be sourced by a 62.5 kHz clock,derived from the 16 MHz system clock or from the RTC (32.768 kHz). If sourced by the
RTC, a special control circuitry ensures that the counter error does not exceed one
symbol period.
The symbol counter can be set or read from the controller. Reading must start with theleast significant byte. If the least significant byte is accessed, all 32 bit of the counterare captured. A read access to SCCNTLL requires a maximum of three AVR clocks.
Reading the upper three bytes of the counter requires two CPU clock cycles for each
byte.
Writing to the counter should start with the most significant byte. Writing the leastsignificant byte initiates the counter update and the new 32 bit counter value is loaded
into the counter with the next available counter clock edge. This can take up to 16 µs
beginning from the low byte write operation, if the counter is sourced by the RTC.
If the counter clock is derived from the 16 MHz clock system, the new counter value isstored immediately.
During the counter update cycle, the counter busy flag SCBSY in the SCSR register is
set to “1”. As long as this bit is “1”, no further read/write access to the counter should beinitiated. The same applies if the AVR is forced to any sleep mode with disabled AVRclock, right after writing to the SCCNT register. If the counter busy flag is not checked
before going to sleep, it is possible that the counter register is not updated correctly.
The symbol counter overflow is indicated by a overflow interrupt. The interrupt isgenerated when the counter turns from 0xFFFFFFFF to 0x00000000.

10.5 Symbol Counter SFD Timestamp Register (32 bit, SCTSR, Read Only)
The SFD timestamp register stores the symbol counter value at the time, the SFD has
been detected. The Register value becomes valid if a valid frame length byte (frame
length > 0) has been detected, but it is not checked if the received frame is valid (CRC
check). Timestamping must be enabled in the control register (Bit SCTSE of Register
SCCR0). A read access to SCTSRLL requires a maximum of three AVR clocks.
Reading the upper three bytes of the timestamp requires two CPU clock cycles for each
byte.
Note that there is no separate interrupt provided for timestamping. Instead the
TRX24_RX_START interrupt can be used (see "Interrupt Vectors in ATmega128RFA1"
on page 211).

10.6 Symbol Counter Beacon Timestamp Register (32 bit, SCBTSR)
If timestamping is enabled in the SCCR register, the beacon timestamp register is
updated with the SFD timestamp at the end of the received frame, if the received frame
was a beacon frame with valid FCS and:•Source PAN identifier == {PAN_ID_1, PAN_ID_0}•{PAN_ID_1, PAN_ID_0} == 0xFFFF

or
PAN_ID_0 and PAN_ID_1 are register of the radio transceiver, see "PAN_ID_0 –Transceiver Personal Area Network ID Register (Low Byte)" on page 124.
Beacon timestamps can also be generated manually. Writing “1” to SCMBTS ofRegister SCCR0 captures the current symbol counter value and stores it in the beacontimestamp register. The bit is cleared automatically afterwards.

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ATmega128RFA1
It is also possible to manually set the register in order to provide a distinct starting value
for the relative compare modes (see next section).

10.7 Compare Unit (3x 32 bit, SCOCR1, SCOCR2, SCOCR3)
The compare unit contains 3 independent 32 bit compare modules and is used tocompare the current counter value with the value stored in the compare register, andoptionally the beacon timestamp register. There are two possible modes available
which can be selected separately for all three compare modules:
1. Absolute Compare: In this mode the value stored in the compare register iscompared directly with the symbol counter value (SCCNT == SCOCRx). If the values
are equal an interrupt is generated.
2. Relative Compare: This mode allows the compare between the current symbol
counter value and the compare value plus the beacon timestamp value (SCCNT ==SCBTSR + SCOCRx). This mode can be used to generate an interrupt at a time offset
relative to the value stored in the beacon timestamp register.
Note that a beacon timestamp is valid after a valid FCS. The relative compare must
exceed the beacon length, otherwise no relative compare interrupt will occure.

10.8 Interrupt Control Registers
The interrupt status and mask registers control the interrupt generation. Each interrupt
can be enabled in SCIRQM (Symbol Counter IRQ Mask Register). If an interrupt
occurs, the appropriate interrupt flag within the interrupt status register is set regardlessof the interrupt mask register setting. If the appropriate interrupt is enabled, an interrupt
is generated.
The interrupt flags can be cleared either by:
1. Entering the respective interrupt handler, or
2. Writing “one” to the according interrupt flag in the interrupt status register.
All Interrupts can be used to wakeup the controller from any sleep state.

10.9 Backoff Slot Counter
The backoff slot counter can be used to provide accurate MAC protocol timing. The
counter is sourced by the transceiver clock and works only if the transceiver clock is
running. If the transceiver is disabled or in sleep mode the counter is also disabled.
The counter generates periodic Interrupts every 20 symbols, i.e. every 320 µs.

10.10 Symbol Counter Usage
10.10.1 SFD and Beacon Timestamp Generation
The SFD timestamp register is updated with the symbol counter value at the time theSFD value has been received completely. For an incoming frame, the register is valid
after the RX_START IRQ was issued until the next RX_START IRQ. SFD timestamps
are generated for all incoming frames with valid SFD and length field even if the PSDU
is corrupted (invalid FCS).

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Figure 10-1. SFD and Beacon Timestamp Generation

Note that Figure 10-1 contains no exact timing information; it is for visualization only.
The beacon timestamp register is updated with the SFD timestamp value at the end of
the frame (RX_END IRQ), if the received frame was a beacon frame with valid FCS and
expected source PAN identifier or { PAN_ID_1, PAN_ID_0} = 0xFFFF.
The register value is valid until a new beacon frame has been received or the beacontimestamp is updated manually. A manual beacon timestamp can be generated bywriting “1” to SCMBTS of the SCCR0 register.
10.10.2 Relative Compare Mode for Superframe Access Timing
The IEEE 802.15.4 describes a superframe structure which contains different time slots
where a device can access the channel.
The Symbol Counter together with the three compare units provide support for waking
up the device at the right time to receive the beacon for superframe synchronization
and at certain times within the superframe.
A typical superframe timing scenario using the symbol counter relative compare modeis shown in Figure 10-2 on page 137. The Symbol Counter values in the figure do notreflect realistic time intervals but demonstrate the principle of operation.

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ATmega128RFA1

BeaconActivation

635
636
637
638
640
641

480
481
482
483
484
485

402
403
404
405
406
407

Beacon

323
324
325
326
327
328
329

Activation

Figure 10-2. Relative Compare Mode

The compare match registers are programmed with symbol intervals relative to the
beacon frame SFD timestamp. For instance the SCCMP1 is programmed to 80,
because the first Granted Time Slot (GTS1) is expected 80 symbols after the beacon
frame. Register SCCMP2 is programmed to 156 to meet GTS3 156 symbols after the
beacon frame. SCCMP3 is programmed to 312. This is the time interval where thebeacon of the next superframe is expected. Because it requires some time to activate
the transceiver and there is also some timing drift possible, the compare interrupt must
be programmed to wake up some symbols in advance to make sure the next beacon is
not missed.
If the controller receives a compare match wake up event it is activating the transceiver.
After the frame operations are finished, the system can go back to sleep until the nextcompare match event occurs.

10.11 Register Description
10.11.1 SCCNTHH – Symbol Counter Register HH-Byte
Bit

7

6

5

NA ($E4)
Read/Write
Initial Value

4

3

2

1

0

SCCNTHH7:0
RW
0

RW
0

RW
0

RW
0

RW
0

SCCNTHH
RW
0

RW
0

RW
0

This register contains the most significant byte of the 32 bit Symbol Counter.
• Bit 7:0 – SCCNTHH7:0 - Symbol Counter Register HH-Byte

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10.11.2 SCCNTHL – Symbol Counter Register HL-Byte
Bit

7

6

5

NA ($E3)
Read/Write
Initial Value

4

3

2

1

0

SCCNTHL7:0
RW
0

RW
0

RW
0

RW
0

RW
0

SCCNTHL
RW
0

RW
0

RW
0

This register contains the second most significant byte of the 32 bit Symbol Counter.
• Bit 7:0 – SCCNTHL7:0 - Symbol Counter Register HL-Byte

10.11.3 SCCNTLH – Symbol Counter Register LH-Byte
Bit

7

6

5

4

RW
0

RW
0

RW
0

RW
0

NA ($E2)
Read/Write
Initial Value

3

2

1

0

RW
0

RW
0

RW
0

SCCNTLH7:0
RW0

SCCNTLH

This register contains the second least significant byte of the 32 bit Symbol Counter.
• Bit 7:0 – SCCNTLH7:0 - Symbol Counter Register LH-Byte

10.11.4 SCCNTLL – Symbol Counter Register LL-Byte
Bit

7

6

5

NA ($E1)
Read/Write
Initial Value

4

3

2

1

0

SCCNTLL7:0
RW
0

RW
0

RW
0

RW
0

RW
0

SCCNTLL
RW
0

RW
0

RW
0

This register contains the least significant byte of the 32 bit Symbol Counter.
• Bit 7:0 – SCCNTLL7:0 - Symbol Counter Register LL-Byte

10.11.5 SCTSRHH – Symbol Counter Frame Timestamp Register HH-Byte
Bit

7

6

5

R
0

R
0

R
0

NA ($EC)
Read/Write
Initial Value

4

3

2

1

0

R
0

R
0

R
0

SCTSRHH7:0
R
0

R
0

SCTSRHH

This register contains the most significant byte of the 32 bit frame (SFD) timestamp
register• Bit 7:0 – SCTSRHH7:0 - Symbol Counter Frame Timestamp Register HH-Byte

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ATmega128RFA1
10.11.6 SCTSRHL – Symbol Counter Frame Timestamp Register HL-Byte
Bit

7

6

5

NA ($EB)
Read/Write
Initial Value

4

3

2

1

0

SCTSRHL7:0
R
0

R
0

R
0

R
0

R
0

SCTSRHL
R
0

R
0

R
0

This register contains the second most significant byte of the 32 bit Frame (SFD)
Timestamp Register• Bit 7:0 – SCTSRHL7:0 - Symbol Counter Frame Timestamp Register HL-Byte

10.11.7 SCTSRLH – Symbol Counter Frame Timestamp Register LH-Byte
Bit

7

6

5

R
0

R
0

R
0

NA ($EA)
Read/Write
Initial Value

4

3

2

1

0

R
0

R
0

R
0

SCTSRLH7:0
R
0

R
0

SCTSRLH

This register contains the second least significant byte of the 32 bit Frame (SFD)
Timestamp Register• Bit 7:0 – SCTSRLH7:0 - Symbol Counter Frame Timestamp Register LH-Byte

10.11.8 SCTSRLL – Symbol Counter Frame Timestamp Register LL-Byte
Bit

7

6

5

NA ($E9)
Read/Write
Initial Value

4

3

2

1

0

SCTSRLL7:0
R
0

R
0

R
0

R
0

R
0

SCTSRLL
R
0

R
0

R
0

This register contains the least significant byte of the 32 bit Frame (SFD) Timestamp
Register• Bit 7:0 – SCTSRLL7:0 - Symbol Counter Frame Timestamp Register LL-Byte

10.11.9 SCBTSRHH – Symbol Counter Beacon Timestamp Register HH-Byte
Bit

7

6

5

RW
0

RW
0

RW
0

NA ($E8)
Read/Write
Initial Value

4

3

2

1

0

RW
0

RW
0

RW
0

SCBTSRHH7:0
RW
0

RW
0

SCBTSRHH

This register contains the most significant byte of the 32 bit Beacon Timestamp
Register. The Beacon Timestamp Register is updated with the contents of the Frame
Timestamp Register if the received frame was a valid beacon frame with matchingsource PAN identifier or register {PAN_ID_1, PAN_ID_0} = 0xFFFF.
• Bit 7:0 – SCBTSRHH7:0 - Symbol Counter Beacon Timestamp Register HHByte
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10.11.10 SCBTSRHL – Symbol Counter Beacon Timestamp Register HL-Byte
Bit

7

6

5

NA ($E7)
Read/Write
Initial Value

4

3

2

1

0

SCBTSRHL7:0
RW
0

RW
0

RW
0

RW
0

RW
0

SCBTSRHL
RW
0

RW
0

RW
0

This register contains the second most significant byte of the 32 bit Beacon Timestamp
Register.
• Bit 7:0 – SCBTSRHL7:0 - Symbol Counter Beacon Timestamp Register HLByte

10.11.11 SCBTSRLH – Symbol Counter Beacon Timestamp Register LH-Byte
Bit

7

6

5

RW
0

RW
0

RW
0

NA ($E6)
Read/Write
Initial Value

4

3

2

1

0

RW
0

RW
0

RW
0

SCBTSRLH7:0
RW
0

RW
0

SCBTSRLH

This register contains the second least significant byte of the 32 bit Beacon Timestamp
Register.
• Bit 7:0 – SCBTSRLH7:0 - Symbol Counter Beacon Timestamp Register LHByte

10.11.12 SCBTSRLL – Symbol Counter Beacon Timestamp Register LL-Byte
Bit

7

6

5

NA ($E5)
Read/Write
Initial Value

4

3

2

1

0

SCBTSRLL7:0
RW
0

RW
0

RW
0

RW
0

RW
0

SCBTSRLL
RW
0

RW
0

RW
0

This register contains the least significant byte of the 32 bit Beacon Timestamp
Register.
• Bit 7:0 – SCBTSRLL7:0 - Symbol Counter Beacon Timestamp Register LL-Byte

10.11.13 SCOCR1HH – Symbol Counter Output Compare Register 1 HH-Byte
Bit

7

6

5

RW
0

RW
0

RW
0

NA ($F8)
Read/Write
Initial Value

4

3

2

1

0

RW
0

RW
0

RW
0

SCOCR1HH7:0
RW
0

RW
0

SCOCR1HH

This register contains the most significant byte of the 32 bit compare value for the firstcompare unit

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ATmega128RFA1• Bit 7:0 – SCOCR1HH7:0 - Symbol Counter Output Compare Register 1 HH-Byte

10.11.14 SCOCR1HL – Symbol Counter Output Compare Register 1 HL-Byte
Bit

7

6

5

NA ($F7)
Read/Write
Initial Value

4

3

2

1

0

SCOCR1HL7:0
RW
0

RW
0

RW
0

RW
0

RW
0

SCOCR1HL
RW
0

RW
0

RW
0

This register contains the second most significant byte of the 32 bit compare value forthe first compare unit
• Bit 7:0 – SCOCR1HL7:0 - Symbol Counter Output Compare Register 1 HL-Byte

10.11.15 SCOCR1LH – Symbol Counter Output Compare Register 1 LH-Byte
Bit

7

6

5

NA ($F6)
Read/Write
Initial Value

4

3

2

1

0

SCOCR1LH7:0
RW
0

RW
0

RW
0

RW
0

RW
0

SCOCR1LH
RW
0

RW
0

RW
0

This register contains the second least significant byte of the 32 bit compare value forthe first compare unit
• Bit 7:0 – SCOCR1LH7:0 - Symbol Counter Output Compare Register 1 LH-Byte

10.11.16 SCOCR1LL – Symbol Counter Output Compare Register 1 LL-Byte
Bit

7

6

5

RW
0

RW
0

RW
0

NA ($F5)
Read/Write
Initial Value

4

3

2

1

0

RW
0

RW
0

RW
0

SCOCR1LL7:0
RW
0

RW
0

SCOCR1LL

This register contains the least significant byte of the 32 bit compare value for the firstcompare unit
• Bit 7:0 – SCOCR1LL7:0 - Symbol Counter Output Compare Register 1 LL-Byte

10.11.17 SCOCR2HH – Symbol Counter Output Compare Register 2 HH-Byte
Bit

7

6

5

NA ($F4)
Read/Write
Initial Value

4

3

2

1

0

SCOCR2HH7:0
RW
0

RW
0

RW
0

RW
0

RW
0

SCOCR2HH
RW
0

RW
0

RW
0

This register contains the most significant byte of the 32 bit compare value for thesecond compare unit
• Bit 7:0 – SCOCR2HH7:0 - Symbol Counter Output Compare Register 2 HH-Byte
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10.11.18 SCOCR2HL – Symbol Counter Output Compare Register 2 HL-Byte
Bit

7

6

5

NA ($F3)
Read/Write
Initial Value

4

3

2

1

0

SCOCR2HL7:0
RW
0

RW
0

RW
0

RW
0

RW
0

SCOCR2HL
RW
0

RW
0

RW
0

This register contains the second most significant byte of the 32 bit compare value forthe second compare unit
• Bit 7:0 – SCOCR2HL7:0 - Symbol Counter Output Compare Register 2 HL-Byte

10.11.19 SCOCR2LH – Symbol Counter Output Compare Register 2 LH-Byte
Bit

7

6

5

RW
0

RW
0

RW
0

NA ($F2)
Read/Write
Initial Value

4

3

2

1

0

RW
0

RW
0

RW
0

SCOCR2LH7:0
RW
0

RW
0

SCOCR2LH

This register contains the second least significant byte of the 32 bit compare value forthe second compare unit
• Bit 7:0 – SCOCR2LH7:0 - Symbol Counter Output Compare Register 2 LH-Byte

10.11.20 SCOCR2LL – Symbol Counter Output Compare Register 2 LL-Byte
Bit

7

6

5

NA ($F1)
Read/Write
Initial Value

4

3

2

1

0

SCOCR2LL7:0
RW
0

RW
0

RW
0

RW
0

RW
0

SCOCR2LL
RW
0

RW
0

RW
0

This register contains the least significant byte of the 32 bit compare value for thesecond compare unit
• Bit 7:0 – SCOCR2LL7:0 - Symbol Counter Output Compare Register 2 LL-Byte

10.11.21 SCOCR3HH – Symbol Counter Output Compare Register 3 HH-Byte
Bit

7

6

5

RW
0

RW
0

RW
0

NA ($F0)
Read/Write
Initial Value

4

3

2

1

0

RW
0

RW
0

RW
0

SCOCR3HH7:0
RW
0

RW
0

SCOCR3HH

This register contains the most significant byte of the 32 bit compare value for the third
compare unit
• Bit 7:0 – SCOCR3HH7:0 - Symbol Counter Output Compare Register 3 HH-Byte

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ATmega128RFA1
10.11.22 SCOCR3HL – Symbol Counter Output Compare Register 3 HL-Byte
Bit

7

6

5

4

NA ($EF)
Read/Write
Initial Value

3

2

1

0

SCOCR3HL7:0
RW
0

RW
0

RW
0

RW
0

SCOCR3HL

RW
0

RW
0

RW
0

RW
0

This register contains the second most significant byte of the 32 bit compare value forthe third compare unit
• Bit 7:0 – SCOCR3HL7:0 - Symbol Counter Output Compare Register 3 HL-Byte

10.11.23 SCOCR3LH – Symbol Counter Output Compare Register 3 LH-Byte
Bit

7

6

5

4

RW
0

RW
0

RW
0

NA ($EE)
Read/Write
Initial Value

3

2

1

0

RW
0

RW
0

RW
0

SCOCR3LH7:0
RW0

SCOCR3LH

RW
0This register contains the second least significant byte of the 32 bit compare value forthe third compare unit
• Bit 7:0 – SCOCR3LH7:0 - Symbol Counter Output Compare Register 3 LH-Byte

10.11.24 SCOCR3LL – Symbol Counter Output Compare Register 3 LL-Byte
Bit

7

6

5

4

NA ($ED)
Read/Write
Initial Value

3

2

1

0

SCOCR3LL7:0
RW
0

RW
0

RW
0

RW
0

RW
0

SCOCR3LL
RW
0

RW
0

RW
0

This register contains the least significant byte of the 32 bit compare value for the third
compare unit
• Bit 7:0 – SCOCR3LL7:0 - Symbol Counter Output Compare Register 3 LL-Byte

10.11.25 SCCR0 – Symbol Counter Control Register 0
Bit

7

6

5

4

3

NA ($DC)SCRESSCMBTSSCENSCCKSEL

SCTSE

Read/Write
Initial Value

RW
0

RW
0

RW
0

RW
0

RW
0

2

1

0

SCCMP3 SCCMP2 SCCMP1
RW
0

RW
0

SCCR0

RW
0

The Control Register 0 is used to setup the operating mode of the symbol counter andthe compare units• Bit 7 – SCRES - Symbol Counter Synchronization
If this bit is set to 1, the 16 MHz clock prescaler as well as the backoff slot counter iscleared. This function can be used to align the symbol timing within one 16 µs symbol
period and to restart the backoff slot counter with a complete 320 µs period. This
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feature works only if the symbol counter module operates with the 16 MHz clock fromXTAL1. After switching to RTC clock source, the symbol period synchronization is lost.
This bit is cleared automatically.
• Bit 6 – SCMBTS - Manual Beacon Timestamp
With this bit a manual beacon timestamp can be generated. If set to 1, the current
symbol counter value is stored into the beacon timestamp register. The bit is cleared
afterwards. The manual beacon timestamping can be used in conjunction with therelative compare mode of the three compare units to generate compare matchinterrupts without having a beacon frame received.
• Bit 5 – SCEN - Symbol Counter enable
This bit activates the symbol counter module. If the bit is not set, the counter, backoff
slot counter and the compare unit are disabled and disconnected from the clock. In thisway the power consumption can be reduced. All registers can be accessed, but write
access to the counter register SCCNT is not possible.
• Bit 4 – SCCKSEL - Symbol Counter Clock Source selectWith this bit the clock source for the symbol counter can be selected. If the bit is one,
the RTC clock from TOSC1 is selected, otherwise the symbol counter operates with theclock from XTAL1. During transceiver sleep modes the clock falls back to the RTC clock
source, regardless of the selected clock. After wakeup, it switches back to the previosly
selected clock source.
• Bit 3 – SCTSE - Symbol Counter Automatic Timestamping enable
This bit enables automatic SFD and Beacon Timestamping. If the bit is zero, no
automatic timestamp capturing is possible. Only manual beacon timestamping can beused.
• Bit 2 – SCCMP3 - Symbol Counter Compare Unit 3 Mode selectThis bit enables the relative compare mode for compare unit 3. If enabled, the countervalue is compared against the content of the beacon timestamp register plus thecontent of the compare register 3 (SCCNT == SCBTS+SCOCR3). Otherwise, thecounter is compared against the copare register 3 (SCCNT == SCOCR3).
• Bit 1 – SCCMP2 - Symbol Counter Compare Unit 2 Mode selectThis bit enables the relative compare mode for compare unit 2. If enabled, the countervalue is compared against the content of the beacon timestamp register plus thecontent of the compare register 2 (SCCNT == SCBTS+SCOCR2). Otherwise, thecounter is compared against the copare register 2 (SCCNT == SCOCR2).
• Bit 0 – SCCMP1 - Symbol Counter Compare Unit 1 Mode selectThis bit enables the relative compare mode for compare unit 1. If enabled, the countervalue is compared against the content of the beacon timestamp register plus thecontent of the compare register 1 (SCCNT == SCBTS+SCOCR1). Otherwise, thecounter is compared against the copare register 1 (SCCNT == SCOCR1).

10.11.26 SCCR1 – Symbol Counter Control Register 1
Bit

144

7

6

5

4

3

2

1

0

NA ($DD)

Res6

Res5

Res4

Resx4

Resx3

Resx2

Resx1

SCENBO

Read/Write
Initial Value

R
0

R
0

R
0

RW
0

RW
0

RW
0

RW
0

RW
0

SCCR1

ATmega128RFA1
8266A-MCU Wireless-12/09

ATmega128RFA1This register is used to enable the backoff slot counter.
• Bit 7:5 – Res6:4 - Reserved Bit
This bit is reserved for future use. The result of a read access is undefined. The register
bit must always be written with the reset value.
• Bit 4:1 – Resx4:1 - Reserved• Bit 0 – SCENBO - Backoff Slot Counter enable
If this bit is set, the backoff slot counter starts working. To enable the corresponding
IRQ the SCIRQM register must be updated.

10.11.27 SCSR – Symbol Counter Status Register
Bit

7

6

5

4

3

2

1

0

NA ($DE)

Res6

Res5

Res4

Res3

Res2

Res1

Res0

SCBSY

Read/Write
Initial Value

R
0

R
0

R
0

R
0

R
0

R
0

R
0

R
0

SCSR

• Bit 7:1 – Res6:0 - Reserved Bit
This bit is reserved for future use. The result of a read access is undefined. The register
bit must always be written with the reset value.
• Bit 0 – SCBSY - Symbol Counter busy
This bit is set if a write operation to the symbol counter register is pending. This bit isset after writing the counter low byte (SCCNTLL) until the symbol counter is updatedwith the new value. This update process can take up to 16 µs and during this time noread or write access to the 32 bit counter register should occure.

10.11.28 SCIRQS – Symbol Counter Interrupt Status Register
Bit

7

6

5

NA ($E0)

Res2

Res1

Res0

Read/Write
Initial Value

R
0

R
0

R
0

4

3

2

1

0

IRQSBO IRQSOF IRQSCP3 IRQSCP2 IRQSCP1
RW
0

RW
0

RW
0

RW
0

SCIRQSRW
0The Interrupt Status Register indicates pending interrupt requests. If the corresponding
interrupt mask bit is set, an interrupt service routine is called and the status bit iscleared automatically. It is also possible to clear the status bit by writing "1" to theselected bit.
• Bit 7:5 – Res2:0 - Reserved Bit
This bit is reserved for future use. The result of a read access is undefined. The register
bit must always be written with the reset value.
• Bit 4 – IRQSBO - Backoff Slot Counter IRQ
This interrupt is generated every 320 µs, that means every 20 symbols.
• Bit 3 – IRQSOF - Symbol Counter Overflow IRQ
This interrupt is generated when the 32 bit counter turns from 0xFFFFFFF to
0x00000000.
• Bit 2 – IRQSCP3 - Compare Unit 3 Compare Match IRQ
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This interrupt indicates a compare match on compare unit 3.
• Bit 1 – IRQSCP2 - Compare Unit 2 Compare Match IRQ
This interrupt indicates a compare match on compare unit 2.
• Bit 0 – IRQSCP1 - Compare Unit 1 Compare Match IRQ
This interrupt indicates a compare match on compare unit 1.

10.11.29 SCIRQM – Symbol Counter Interrupt Mask Register
Bit

7

6

5

NA ($DF)

Res2

Res1

Res0

Read/Write
Initial Value

R
0

R
0

R
0

4

3

2

1

0

IRQMBO IRQMOF IRQMCP3 IRQMCP2 IRQMCP1
RW
0

RW
0

RW
0

RW
0

SCIRQMRW
0

The Interrupt Mask Register is used to enable corresponding interrupts. After reset allinterrupts are disabled. Disabled interrupts are still captured in the interrupt status
register SCIRQS, but no interrupt is requested. Before enabling an interrupt, thecorresponding interrupt status bit should be cleared by writing a 1. If the status bit is set
and the IRQ gets enabled, the IRQ handler is called immediatly.
• Bit 7:5 – Res2:0 - Reserved Bit
This bit is reserved for future use. The result of a read access is undefined. The register
bit must always be written with the reset value.
• Bit 4 – IRQMBO - Backoff Slot Counter IRQ enable
This bit enables the SCNT_BACKOFF interrupt.
• Bit 3 – IRQMOF - Symbol Counter Overflow IRQ enable
This bit enables the SCNT_OVFL interrupt.
• Bit 2 – IRQMCP3 - Symbol Counter Compare Match 3 IRQ enable
This bit enables the SCNT_CMP3 interrupt.
• Bit 1 – IRQMCP2 - Symbol Counter Compare Match 2 IRQ enable
This bit enables the SCNT_CMP2 interrupt.
• Bit 0 – IRQMCP1 - Symbol Counter Compare Match 1 IRQ enable
This bit enables the SCNT_CMP1 interrupt.

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ATmega128RFA1
11 System Clock and Clock Options
This section describes the clock options for the AVR microcontroller.

11.1 Overview
Figure 11-1 below presents the principal clock systems in the AVR and theirdistribution. All of the clocks need not be active at a given time. In order to reduce
power consumption, the clocks to modules not being used can be halted by using
different sleep modes, as described in chapter "Power Management and Sleep Modes"
on page 156. The clock systems are detailed below.
Figure 11-1. Clock Distribution
Asynchronous
Timer

General I/O
ModulesADC

CPU CoreFlash and
EEPROMRAM

cp2extSymbolCounter

Radio
Transceivercp2adccp2ramregf

Clock
Multiplexer

Clock
Multiplexer
cp2calib

cp2corecp2io

AVR ClockControl Unit

cp2flash

Source clock
Reset Logic

Watchdog Timer

1/16 Clock Prescaler

System Clock
Prescaler

Clock
Multiplexer

cp2wdt1:2
Prescaler

Calibrated RC
Oscillator (16MHz)

Watchdog Oscillator(128kHz)XTAL2Transceiver Crystal
Oscillator(16MHz)

XTAL1

CLKI

External Clock

AMR

TOSC2

TOSC1

Timer/Counter
Oscillator(32.768kHz)

11.2 Clock Systems and their Distribution
11.2.1 CPU Clock – clkCPU
The CPU clock is routed to parts of the system concerned with operation of the AVR
core. Examples of such modules are the General Purpose Register File, the Status
Register and the data memory holding the Stack Pointer. Halting the CPU clock inhibits
the core from performing general operations and calculations.

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11.2.2 I/O Clock – clkI/O
The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and
USART. The I/O clock is also used by the External Interrupt module, but note that someexternal interrupts are detected by asynchronous logic, allowing such interrupts to be
detected even if the I/O clock is halted. Also note that start condition detection in the 2wire serial interface (TWI) module is carried out asynchronously when clkI/O is halted.
Similar the TWI address recognition in all sleep modes also occurs asynchronously.
11.2.3 Flash Clock – clkFLASHThe Flash clock controls operation of the Flash interface. The Flash clock is usuallyactive simultaneously with the CPU clock.
11.2.4 Asynchronous Timer Clock – clkASY
The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked
directly from an external clock or an external 32 kHz clock crystal. The dedicated clock
domain allows using this Timer/Counter as a real-time counter even if the device is in
sleep mode.
11.2.5 ADC Clock – clkADC
The ADC is provided with a dedicated clock domain. This allows halting the CPU andI/O clocks in order to reduce noise generated by digital circuitry. This gives moreaccurate ADC conversion results.

11.3 Clock Sources
The device has the following clock source options, selectable by Flash Fuse bits asshown below. The clock from the selected source is input to the AVR clock generator,
and routed to the appropriate modules.
(1)

Table 11-1. Device Clocking Options SelectDevice Clocking Option

CKSEL3:0

Transceiver clock

1111 – 0110

Reserved

0101 - 0100

Internal 128 kHz RC Oscillator

0011

Calibrated Internal RC Oscillator

0010

External Clock

0000

Reserved

0001

Notes:

1. For all fuses “1” means unprogrammed while “0” means programmed.

11.3.1 Default Clock Source
The device is shipped with internal RC oscillator at 16.0 MHz, the 1:2 prescaler enabled
and with the fuse CKDIV8 programmed, resulting in 1.0 MHz system clock. The startup
time is set to maximum time. (CKSEL = "0010", SUT = "10", CKDIV8 = "0"). The default
setting ensures that all users can make their desired clock source setting using any
available programming interface.
11.3.2 Clock Start-up Sequence
Any clock source needs a minimum number of oscillating cycles before it can beconsidered stable.

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To ensure sufficient startup time, the device issues an internal reset with a time-out
delay (tTOUT) after the device reset is released by all other reset sources. Section"Power-on Reset" on page 177 describes the start conditions for the internal reset. The
delay (tTOUT) is timed from the Watchdog Oscillator and the number of cycles in the
delay is set by the SUTx and CKSELx fuse bits. The selectable delays are shown in
Table 11-2 below. The frequency of the Watchdog Oscillator is voltage dependent asshown in section "Typical Characteristics" on page 510.
Table 11-2. Number of Watchdog Oscillator Cycles
Typ Time-out

Number of Cycles

0 ms

0

4.0 ms512

64 ms

8K (8,192)

Main purpose of the delay is to keep the AVR in reset until it is supplied with a stable
VDEVDD. The delay will not monitor the actual voltage and it will be required to select adelay longer than the DEVDD rise time. If this is not possible, an internal or external
Brown-Out Detection (BOD) circuit should be used. A BOD circuit will ensure sufficient
VDEVDD before it releases the reset, and the time-out delay can be disabled. Disabling
the time-out delay without utilizing a Brown-Out Detection circuit is not recommended.
The oscillator is required to oscillate for a minimum number of cycles before the clock is
considered stable. An internal ripple counter monitors the oscillator output clock, andkeeps the internal reset active for a given number of clock cycles. The reset is thenreleased and the device will start to execute. The recommended oscillator start-up timeis dependent on the clock type, and varies from 6 cycles for an externally applied clock
to 32K cycles for a low frequency crystal.
The start-up sequence for the clock includes both the time-out delay and the start-up
time when the device starts up from reset. When starting up from Power-save or Powerdown mode, DEVDD is assumed to be at a sufficient level and only the start-up time isincluded.

11.4 Calibrated Internal RC Oscillator
By default, the Internal RC Oscillator provides an approximate 16 MHz clock. The RC
oscillator is voltage and temperature dependent, but can be very accurately calibrated
by the user. See chapter "Clock Characteristics" on page 502 and "Internal Oscillator
Speed" on page 510 for more details. The device is shipped with the CKDIV8 Fuse andthe 1:2 system clock prescaler programmed. See section "System Clock Prescaler" on
page 152 for more details.
This clock may be selected as the system clock by programming the CKSEL Fuses asshown in Table 11-3 on page 150. If selected, it will operate with no external
components. During reset, hardware loads the pre-programmed calibration value into
the OSCCAL Register and thereby automatically calibrates the RC Oscillator. The
accuracy of this calibration is shown as Factory calibration in section "Clock
Characteristics" on page 502.
By changing the OSCCAL register (see "OSCCAL – Oscillator Calibration Value" onpage 153) from Software, it is possible to get a higher calibration accuracy than byusing the factory calibration. The accuracy of this calibration is shown as Usercalibration in section "Clock Characteristics" on page 502.

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When this Oscillator is used as the chip clock, the Watchdog Oscillator will still be used
for the Watchdog Timer and for the Reset Time-out. For more information on the preprogrammed calibration value, see the section "Calibration Byte" on page 467.
Table 11-3. Internal Calibrated RC Oscillator Operating Modes
Frequency Range (MHz)CKSEL3:0

9.6 ... 22.40010

Notes:(1)(2)

1. The device is shipped with this option selected.

When this Oscillator is selected, start-up times are determined by the SUT Fuses asshown in the following table.
Table 11-4. Start-up times for the internal calibrated RC Oscillator clock selection
Power Conditions

Start-up Time from Powerdown and Power-save

Additional Delay fromReset

SUT1:0BOD enabled

6 CK

14CK

00

Fast rising power

6 CK

14CK + 4.0 ms

Slowly rising power

6 CK

14CK + 64 ms

01

(1)

Reserved
Notes:

10
11

1. The device is shipped with this option selected

11.5 128 kHz Internal Oscillator
The 128 kHz Internal Oscillator is an ultra-low power RC oscillator providing a clock ofapproximate 128 kHz nominal frequency. This clock may be selected as the system
clock by programming the CKSEL Fuses to “0011” as shown in the following table.
Table 11-5. 128 kHz Internal Oscillator Operating Modes(1)

Nominal Frequency

CKSEL3:0

128 kHz

0011

Notes:

1. Note that the 128 kHz oscillator is a very low power clock source, and is notdesigned for high accuracy

When this clock source is selected, start-up times are determined by the SUT Fuses asshown in the following table.
Table 11-6. Start-up Times for the 128 kHz Internal Oscillator
Power Conditions

Start-up Time from Power-down
and Power-save

Additional Delay fromReset

SUT1:0BOD enabled

6 CK

14CK

00

Fast rising power

6 CK

14CK + 4.1 ms

01

Slowly rising power

6 CK

14CK + 64 ms

10

Reserved

1111.6 External ClockTo drive the device from an external clock source, CLKI should be used as shown in
Figure 11-2 on page 151. To run the device on an external clock, the CKSEL Fuses
must be programmed to “0000”.

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Figure 11-2. External Clock Drive Configuration
external clock

CLKI

VSS

When this clock source is selected, start-up times are determined by the SUT Fuses asshown in Table 11-8 below.
Table 11-7. External Clock Frequency
Nominal Frequency

CKSEL3:0

0 – 16 MHz

0000

Table 11-8. Start-up Times for the External Clock Selection
Power Conditions

Start-up Time from Power-down
and Power-save

Additional Delay fromReset

SUT1:0BOD enabled

6 CK

14 CK

00

Fast rising power

6 CK

14 CK + 4.0 ms

01

Slowly rising power

6 CK

14 CK + 64 ms

10

Reserved

11

When applying an external clock, it is required to avoid sudden changes in the applied
clock frequency to ensure stable operation of the microcontroller unit (MCU). A variationin frequency of more than 2% from one clock cycle to the next can lead to unpredictablebehavior. If changes of more than 2% are required, ensure that the MCU is kept in
Reset during the changes.
Note that the System Clock Prescaler can be used to implement run-time changes of
the internal clock frequency while still ensuring stable operation. Refer to section"System Clock Prescaler" on page 152 for details.

11.7 Transceiver Crystal Oscillator
The integrated crystal oscillator for the radio transceiver generates a low-jitter 16MHz
clock frequency. See section "Crystal Oscillator (XOSC)" on page 80 for details about
the operation of this oscillator. The AVR core and the radio transceiver operate
synchronously on the same clock if this oscillator is selected. If the transceiver crystal
oscillator is selected as AVR core clock, it remains enabled even if the radio transceiveris in SLEEP mode or its power reduction bit PRTRX24 is set.

Table 11-9. Transceiver Crystal Clock Operating Mode

Notes:(1)Frequency Range (MHz)CKSEL3:0

161111 - 0110

1. All CKSEL fuse values have the same significance.

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Table 11-10. Start-up Times for the Transceiver Oscillator Clock Selection
Power Conditions

Start-up Time fromPower-down andPower-save

Additional Delayfrom ResetCKSEL0

SUT1:0

fast rising power

258 CK

14CK + 4.1 ms

000

slowly rising power

258 CK

14CK + 65 ms

001

BOD enabled

1K CK

14CK + 0 ms

010

fast rising power

1K CK

14CK + 4.1 ms

0

11

slowly rising power

1K CK

14CK + 65 ms

100

BOD enabled

16K CK

14CK + 0 ms

1

01

fast rising power

16K CK

14CK + 4.1 ms

1

10

slowly rising power

16K CK

14CK + 65 ms

1

11

11.8 Clock Output Buffer
The device can output the system clock on the CLKO pin. To enable the output, the
CKOUT Fuse has to be programmed. This mode is suitable when the chip clock is used
to drive other circuits on the system. The clock also will be output during reset, and thenormal operation of I/O pin will be overridden when the fuse is programmed. Any clock
source, including the internal RC Oscillator, can be selected when the clock is output on
CLKO. If the System Clock Prescaler is used, it is the divided system clock that is
output.
Special attention is required to prevent unwanted radiation from the connected PCBclock trace. Proper filtering can help to suppress higher harmonics.

11.9 Timer/Counter Oscillator
The device can operate the Timer/Counter2 from the 32.768 kHz crystal oscillator or an
external clock source. See section "Application Circuits" on page 493 for the watch
crystal connection.

11.10 System Clock Prescaler
The ATmega128RFA1 has a system clock prescaler, and the system clock can bedivided by setting the “CLKPR – Clock Prescale Register”. This feature can be used todecrease the system clock frequency and the power consumption when therequirement for processing power is low. This can be used with all clock source options,and it will affect the clock frequency of the CPU and all synchronous peripherals. The
clocks clkI/O, clkADC, clkCPU, and clkFLASH are divided by a factor as shown in CLKPR –Clock Prescale Register on page 154.
The prescaler clock division factor of the internal RC-Oscillator is different from all otherclock sources, see register description CLKPR – Clock Prescale Register on page 154
Flash, EEPROM, Fuse- and Lock-bit programming is not allowed while using RCOscillator with CLKPS=0xF (clkCPU = 16MHz).
When switching between prescaler settings, the System Clock Prescaler ensures thatno glitches occur in the clock system. It also ensures that no intermediate frequency ishigher than neither the clock frequency corresponding to the previous setting nor theclock frequency corresponding to the new setting.
The prescaler is implemented as a ripple counter running at the frequency of theundivided clock, which may be faster than the CPU's clock frequency. Hence, it is not

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possible to determine the state of the prescaler - even if it were readable. The exact
time it takes to switch from one clock division to another cannot be exactly predicted.
From the time the CLKPS values are written, it takes between t1 + t2 and t1 + 2t2 before
the new clock frequency is active. In this interval 2 active clock edges are produced.
Here t1 is the previous clock period and t2 is the clock period corresponding to the newprescaler setting.
To avoid unintentional changes of clock frequency, a special write procedure must be
followed to change the CLKPS bits:
1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in
CLKPR to zero.
2. Within four cycles, write the desired value to CLKPS while writing a zero to
CLKPCE.
Interrupts must be disabled when changing prescaler settings to make sure the write
procedure is not interrupted.
It is not required to change the prescaler setting of an existing software package written
for an 8MHz internal RC oscillator. The change of the prescaler (additional 1:2 divider)is compensated by doubling the RC oscillator frequency of the ATmega128RFA1.

11.11 Register Description
11.11.1 OSCCAL – Oscillator Calibration Value
Bit

7

6

5

4

3

2

1

0

NA ($66)

CAL7

CAL6

CAL5

CAL4

CAL3

CAL2

CAL1

CAL0

Read/Write
Initial Value

R/W
0

R/W
0

R/W
0

R/W
0

R/W
0

R/W
0

R/W
0

R/W
0

OSCCALThe Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator
to remove process variations from the oscillator frequency. A preprogrammed
calibration value is automatically written to this register during chip reset, giving theFactory calibrated frequency. The application software can write this register to change
the oscillator frequency. The oscillator can be calibrated to frequencies as specified in
the section "Electrical Characteristics". Calibration outside that range is not guaranteed.
Note that this oscillator is used to time EEPROM and Flash write accesses and thesewrite times will be affected accordingly. The calibration to very high frequencies cancause EEPROM or Flash erase/write failures. The CAL7 bit determines the range of
operation for the oscillator. Setting this bit to 0 gives the lowest frequency range, setting
this bit to 1 gives the highest frequency range. The two frequency ranges areoverlapping, in other words a setting of OSCCAL = 0x7F gives a higher frequency than
OSCCAL = 0x80. The CAL6..0 bits are used to tune the frequency within the selected
range. A setting of 0x00 gives the lowest frequency in that range, and a setting of 0x7F
gives the highest frequency in the range.
• Bit 7:0 – CAL7:0 - Oscillator Calibration Tuning Value
Table 11-11 CAL Register Bits
Register Bits

Value

Description

CAL7:00x00

Calibration value for lowest oscillator
frequency

0x7f

End value of low frequency range calibration

0x80

Start value of high frequency range
calibration

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Register Bits

Value

Description

0xff

Calibration value for highest oscillator
frequency

11.11.2 CLKPR – Clock Prescale Register
Bit

7

6

5

4

NA ($61)

CLKPCE

Res2

Res1

Res0

Read/Write
Initial Value

RW
0

R
0

R
0

R
0

3

2

1

0

CLKPS3 CLKPS2 CLKPS1 CLKPS0
RW
0

RW
0

RW
0

CLKPR

RW
0

• Bit 7 – CLKPCE - Clock Prescaler Change Enable
The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The
CLKPCE bit is only updated when the other bits in CLKPR are simultaneously written to
zero. CLKPCE is cleared by hardware four cycles after it is written or when CLKPS bits
are written. Rewriting the CLKPCE bit within this time-out period does neither extend
the time-out period, nor clear the CLKPCE bit.
• Bit 6:4 – Res2:0 - Reserved• Bit 3:0 – CLKPS3:0 - Clock Prescaler Select Bits
These bits define the division factor between the selected clock source and the internal
system clock. These bits can be written run-time to vary the clock frequency to suit theapplication requirements. As the divider divides the master clock input to the MCU, thespeed of all synchronous peripherals is reduced when a division factor is used. The
division factors are given in the following table. Note that the factor is different whenusing the internal 16MHz RC oscillator as the clock source. The CKDIV8 Fuse
determines the initial value of the CLKPS bits. If CKDIV8 is not programmed, the
CLKPS bits will be reset to 0000. If CKDIV8 is programmed, CLKPS bits are reset to0011 giving a division factor of 8 at start up. This feature should be used if the selected
clock source has a higher frequency than the maximum frequency of the device at thepresent operating conditions. Note that any value can be written to the CLKPS bits
regardless of the CKDIV8 Fuse setting. The Application software must ensure that asufficient division factor is chosen if the selected clock source has a higher frequency
than the maximum frequency of the device at the present operating conditions. The
device is shipped with the CKDIV8 Fuse programmed.
Table 11-12 CLKPS Register Bits

154

Register Bits

Value

Description

CLKPS3:0

0x0

Division factor 1 / RC-Oscillator 2

0x1

Division factor 2 / RC-Oscillator 4

0x2

Division factor 4 / RC-Oscillator 8

0x3

Division factor 8 / RC-Oscillator 16

0x4

Division factor 16 / RC-Oscillator 32

0x5

Division factor 32 / RC-Oscillator 64

0x6

Division factor 64 / RC-Oscillator 128

0x7

Division factor 128 / RC-Oscillator 256

0x8

Division factor 256 / RC-Oscillator 512

0x9

Reserved

0xA

Reserved

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ATmega128RFA1
Register Bits

Value

Description

0xB

Reserved

0xC

Reserved

0xD

Reserved

0xE

Reserved

0xF

Division factor 1 only permitted for RCOscillator. Flash and EEPROM programming
is not allowed.

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12 Power Management and Sleep Modes
Sleep modes enable the application to shut down unused modules in the MCU, thereby
saving power. The AVR microcontroller and the RF transceiver provide various sleep
modes allowing the user to tailor the power consumption to the application’s
requirements.

12.1 Deep-Sleep Mode
When the microcontroller goes into Power-down or Power-save modes while thetransceiver is in SLEEP state the device enters the Deep-Sleep mode.
Sending the microcontroller to Power-down or Power-save is not allowed during thewake-up phase of the transceiver. The TRX24_AWAKE interrupt shall be used to wait
for the transceiver is operational.
The DVDD voltage regulator and the associated power chain will be switched off.
Remaining running logic will then be supplied from the Low Leakage Voltage Regulator.
Even the AVDD regulator will switched off. See chapter "Radio Transceiver" on page
160 how to disable the radio transceiver.
The SRAM blocks use the data retention mode to preserve its content while saving
leakage power. The Low Leakage Voltage Regulator has only limited driving
capabilities, see section "Supply Voltage and Leakage Control" on page 161 for details.
Therefore the remaining running logic must be clocked with low frequencies only.
The Deep-Sleep mode can be finished by a wake-up source shown by the Table 12-1
below. Then DVDD voltage regulator and the associated power chain will be switched
on. If the power-chain is completely enabled the standard AVR wake-up procedurecontinues (for details see chapter "Power-chain" on page 161).
Note that the wake-up time from Deep-sleep mode is significantly longer than the wakeup time from the Power-down or Power-save mode because the entire power-chain will
be restarted.
Additionally note that if the ADC is enabled and/or running a conversion, while entering
Deep-sleep mode, the ADC supply voltage is switched off. Therefore the ADC must be
disabled before entering Deep-sleep mode to avoid an undefined ADC operation.

12.2 AVR Microcontroller Sleep Modes
In chapter "System Clock and Clock Options" on page 147 the different clock systems
in the ATmega128RFA1, and their distribution were presented. Figure 11-1 on page
147 is helpful in selecting an appropriate sleep mode. The following table shows thedifferent sleep modes and their wake-up sources.
Table 12-1. Active Clock Domains and Wake-up Sources in the Different Sleep Modes

156

X

X

X

X

X

X

(2)

X

(3)

X

X

(2)

X

X

X

Transceiver

X

X

Symbol Counter

X(2)

Other I/O

X

WDT Interrupt

X

ADC

X

SPM/EEPROM
Ready

Timer Oscillator
EnabledX

Timer/Counter2

Main Clocksource EnabledX

TWI Address
MatchclkASYX

Wake-up Sources
INT7:0 and Pin
ChangeclkADCADCNRM

Oscillators

clkIO

Idle

clkFLASH

Sleep Mode

clkCPU

Active Clock Domains

X

X

X

X

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Active Clock Domains

Oscillators

Power-down

(3)

X

(3)

X

(3)

X

(3)

X

X

Power-saveStandby

Wake-up Sources

(2)

X

X

(1)

X

ExtendedStandby(2)

X
Notes:

X

X
X

(2)

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

1. Only recommended with external crystal or resonator selected as clock source.
2. If Timer/Counter2 is running in asynchronous mode.
3. For INT7:4, only level interrupt.

To enter any of the sleep modes, the SE bit in in the SMCR register (see "SMCR –Sleep Mode Control Register" on page 166) must be written to logic one and a SLEEP
instruction must be executed. The SM2, SM1, and SM0 bits in the SMCR Register
select which sleep mode will be activated by the SLEEP instruction. See chapter"Register Description" on page 166 for a summary.
If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up.
The MCU is then halted for four cycles in addition to the start-up time, executes theinterrupt routine, and resumes execution from the instruction following SLEEP. The
contents of the Register File and SRAM are unaltered when the device wakes up fromsleep. Note that SRAM data retention must be enabled in some sleep modes topreserve the memory contents (see section "SRAM with Data Retention" on page 163).
If a reset occurs during sleep mode, the MCU wakes up and executes from the Reset
Vector.
12.2.1 Idle Mode
When the SM2:0 bits are written to 000 in the SMCR register, the SLEEP instruction
makes the MCU enter Idle mode, stopping the CPU but allowing the SPI, USART,
Analog Comparator, ADC, 2-wire Serial Interface, Timer/Counters, Watchdog, and theinterrupt system to continue operating. This sleep mode basically halts clkCPU andclkFLASH, while allowing the other clocks to run.
Idle mode enables the MCU to wake up from external triggered interrupts as well asinternal ones like the Timer Overflow and USART Transmit Complete interrupts. If
wake-up from the Analog Comparator interrupt is not required, the Analog Comparator
can be powered down by setting the ACD bit in the Analog Comparator Control andStatus Register – ACSR. This will reduce power consumption in Idle mode. If the ADC
is enabled, a conversion starts automatically when this mode is entered.
12.2.2 ADC Noise Reduction Mode
When the SM2:0 bits are written to 001, the SLEEP instruction makes the MCU enter
ADC Noise Reduction mode (ADCNRM), stopping the CPU but allowing the ADC, theexternal interrupts, 2-wire Serial Interface address match, Timer/Counter2 and theWatchdog to continue operating (if enabled). This sleep mode basically halts clkI/O,
clkCPU, and clkFLASH, while allowing the other clocks to run.
This improves the noise environment for the ADC, enabling higher resolution
measurements. If the ADC is enabled, a conversion starts automatically when thismode is entered. Apart form the ADC Conversion Complete interrupt, only an External
Reset, a Watchdog System Reset, a Watchdog interrupt, a Brown-out Reset, a 2-wireserial interface interrupt, a Timer/Counter2 interrupt, an SPM/EEPROM ready interrupt,

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an external level interrupt on INT7:4 or a pin change interrupt can wakeup the MCU
from ADC Noise Reduction mode.
12.2.3 Power-down Mode
When the SM2:0 bits are written to 010, the SLEEP instruction makes the MCU enter
Power-down mode. In this mode, the 16 MHz crystal oscillator is stopped (if selected by
CKSEL fuses), while the external interrupts, the 2-wire Serial Interface, and theWatchdog continue operating (if enabled). Only an External Reset, a Watchdog Reset,a Brown-out Reset, 2-wire Serial Interface address match, an external level interrupt on
INT7:4, an external interrupt on INT3:0, a pin change interrupt, or a symbol counterinterrupt can wake up the MCU. This sleep mode basically halts all generated clocks,
allowing operation of asynchronous modules only.
Note that if a level triggered interrupt is used for wake-up from Power-down mode, thechanged level must be held for some time to wake up the MCU. Refer to section"External Interrupts" on page 218 for details.
When waking up from Power-down mode, there is a delay from the wake-up condition
occurs until the wake-up becomes effective. This allows the clock to restart and become
stable after have been stopped. The wake-up period is defined by the same CKSEL
Fuses that define the Reset Time-out period, as described in chapter "System Clockand Clock Options" on page 147.
12.2.4 Power-save Mode
When the SM2:0 bits are written to 011, the SLEEP instruction makes the MCU enter
Power-save mode. This mode is identical to Power-down, with one exception:
If Timer/Counter2 is enabled, it will keep running during sleep. The device can wake up
from either Timer Overflow or Output Compare event from Timer/Counter2 if thecorresponding Timer/Counter2 interrupt enable bits are set in TIMSK2, and the Global
Interrupt Enable bit in SREG is set. If Timer/Counter2 is not running, Power-down modeis recommended instead of Power-save mode.
The Timer/Counter2 can be clocked both synchronously and asynchronously in Powersave mode. If the Timer/Counter2 is not using the asynchronous clock, theTimer/Counter Oscillator is stopped during sleep. If the Timer/Counter2 is not using thesynchronous clock, the clock source is stopped during sleep. Note that even if thesynchronous clock is running in Power-save, this clock is only available for theTimer/Counter2. Timer/Counter2 operation is described in detail in section "8-bit
Timer/Counter2 with PWM and Asynchronous Operation" on page 309.
12.2.5 Standby Mode
When the SM2:0 bits are 110 and the crystal oscillator of the radio transceiver isselected, the SLEEP instruction makes the MCU enter Standby mode. This mode is
identical to Power-down with the exception that the Oscillator is kept running. FromStandby mode, the device wakes up in six clock cycles.
12.2.6 Extended Standby Mode
When the SM2:0 bits are 111 and the crystal oscillator of the radio transceiver isselected, the SLEEP instruction makes the MCU enter Extended Standby mode. Thismode is identical to Power-save mode with the exception that the oscillator is kept
running. From Extended Standby mode, the device wakes up in six clock cycles.

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12.3 Power Reduction Register
The Power Reduction Register (PRR), see "PRR0 – Power Reduction Register0" onpage 167, "PRR1 – Power Reduction Register 1" on page 168 and "PRR2 – Power
Reduction Register 2" on page 168, provide a method to stop the clock to individual
peripherals to reduce power consumption. The current state of the peripheral is frozen
and the I/O registers can not be read or written. Resources used by the peripheral when
stopping the clock will remain occupied. Hence the peripheral unit should in most cases
be disabled before stopping the clock. Waking up a module, which is done by clearing
the bit in PRR, puts the module in the same state as before the shutdown. Exceptions
are the SRAM blocks and the radio transceiver. The SRAM is shut down by a DRT
switch and the radio transceiver is in reset state if its respective power reduction bit isset.
Module shutdown can be used in Idle mode and Active mode to significantly reduce theoverall power consumption. See chapter "Typical Characteristics" on page 510 for
examples. In all other sleep modes, the clock is already stopped.

12.4 Minimizing Power Consumption
There are several issues to consider when trying minimizing the power consumption in
an AVR controlled system. In general, sleep modes should be used as much as
possible, and the sleep mode should be selected so that as few as possible of thedevice’s functions are operating. All functions not needed should be disabled. In
particular, the following modules may need special consideration when trying to achieve
the lowest possible power consumption.
12.4.1 Analog to Digital Converter
If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should
be disabled before entering any sleep mode. Refer to chapter "ADC – Analog to Digital
Converter" on page 410 for details on ADC operation.
12.4.2 Analog Comparator
When entering Idle mode, the Analog Comparator should be disabled if not used. Whenentering ADC Noise Reduction mode the Analog Comparator should also be disabled.
In other sleep modes, the Analog Comparator is automatically disabled. However, if theAnalog Comparator is set up to use the Internal Voltage Reference as input, the Analog
Comparator should be disabled in all sleep modes. Otherwise, the Internal Voltage
Reference will be enabled, independent of sleep mode. Refer to "AC – Analog
Comparator" on page 407 for details on how to configure the Analog Comparator.
12.4.3 Brown-out Detector
If the Brown-out Detector is enabled by the BODLEVEL Fuses, it will be disabled in
Deep-sleep mode. Refer to "Brown-out Detection" on page 178 for details on how to
configure the Brown-out Detector. It is recommended to enable the Brown-out Detector.
12.4.4 Internal Voltage Reference
The Internal Voltage Reference will be enabled when needed by the Brown-out
Detection, the Analog Comparator or the ADC. If these modules are disabled as
described in the sections above, the internal voltage reference will be disabled and notconsume power. When turned on again, the user must allow the reference to start up
before the output is used. If the reference is kept on in sleep mode, the output can be

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used immediately. Refer to "Internal Voltage Reference" on page 179 for details on thestart-up time.
12.4.5 Watchdog Timer
If the Watchdog Timer is not needed in the application, the module should be turned off.
If the Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence,always consume power. In the deeper sleep modes, this will contribute significantly tothe total current consumption. Refer to "Watchdog Timer" on page 180 for details on
how to configure the Watchdog Timer.
12.4.6 Port Pins
When entering a sleep mode, all port pins should be configured to use minimum power.
The most important is then to ensure that no pins drive resistive loads. In sleep modes
where both the I/O clock (clkI/O) and the ADC clock (clkADC) are stopped, the input
buffers of the device will be disabled. This ensures that no power is consumed by the
input logic when not needed. In some cases, the input logic is needed for detecting
wake-up conditions, and it will then be enabled. Refer to the section "I/O-Ports" on page186 for details on which pins are enabled. If the input buffer is enabled and the input
signal is left floating or have an analog signal level close to DEVDD/2, the input buffer
will use excessive power.
For analog input pins, the digital input buffer should be disabled at all times. An analog
signal level close to DEVDD/2 on an input pin can cause significant current even in
active mode. Digital input buffers can be disabled by writing to the Digital Input Disable
Registers DIDR1 and DIDR0. Refer to "DIDR1 – Digital Input Disable Register 1" onpage 409 and "DIDR0 – Digital Input Disable Register 0" on page 433 for details.
12.4.7 On-chip Debug System
If the On-chip debug system is enabled by the OCDEN Fuse and the chip enters sleep
mode, the main clock source is enabled, and hence, always consumes power. In the
deeper sleep modes, this will contribute significantly to the total current consumption.
There are three alternative ways to disable the OCD system:• Disable the OCDEN Fuse.
• Disable the JTAGEN Fuse.
• Write one to the JTD bit in MCUCR.
12.4.8 Symbol Counter
The Symbol Counter acts as a separate counter, which uses either the 16MHz clockfrom XTAL1/XTAL2 crystal pins or the clock from PG3/PG4 low frequency crystal pins.
If the Symbol Counter module is not used, it should be disabled, see section "MAC
Symbol Counter" on page 133.
12.4.9 Radio Transceiver
The radio transceiver module is automatically starting its state machine after power on.
While the CPU is in any sleep mode, the radio transceiver remains active. This enables
the radio transceiver to wakeup the MCU if a pending action is over (frame received ortransmission completed). The radio transceiver will be inactive during sleep, if either theits power reduction bit PRTRX24 in register PRR1 is set or it is send into SLEEP mode,see "PRR1 – Power Reduction Register 1" on page 168 for details.
The radio transceiver is derived from a stand alone solution that was partly controlled
by external pins. Now the radio transceiver is fully controlled by individual register bits.

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ATmega128RFA1
The radio transceiver has a separate reset signal. A radio transceiver reset is initiatedby setting bit TRXRST in register TRXPR. This bit is self-resetting.
The radio transceiver signal SLPTR can be controlled by the bit SLPTR in register
TRXPR and is used to set the radio transceiver into SLEEP mode (assuming
TRX_STATE is TRX_OFF). This bit has a multiple function, see section "Low-Power 2.4
GHz Transceiver" on page 29 for a detailed description of the radio transceiver.

12.5 Supply Voltage and Leakage Control
For battery applications using deep sleep periods, the leakage current defines thesystem life time. Due to the typical strong temperature dependency of the leakage
current, major contributors to the leakage budget are turned off:
• Analog and digital voltage regulator,• Non-volatile memory (NVM),• SRAM,• Digital signal processor of the radio transceiver including AES engine.
If the CPU uses one of the sleep modes “power-down” or “power-save”, the above
mentioned blocks will be switched off by power switches. When the CPU wakes up, theblocks are switched on again. There are some additional exceptions (internal voltage
regulator, SRAM, radio transceiver), see section "Power-chain" below .
The supply voltage control is mainly hidden to the application, it is not necessary toconfigure the supply voltage control. Nevertheless some configurations can be done inorder to get the maximum effect and the lowest sleep current, for details see section"SRAM with Data Retention" on page 163.
12.5.1 Power-chain
The following figure shows the major dependencies of the power-chain and how thepower switches are situated inside the chain.
Figure 12-1. Power-chain connections
pow erchain _ ok

pow er_control

bandgap

llv reg_ok

DVREG

drt_sw itch

drt_sw itch

pow er_ sw itch

pow er_sw itch

LLV R E G

SRAM #0

S R A M #3

R adioTransceiverNVM

trx 24 _sleeps

Startup and Wakeup from deep sleep
After power-on reset (POR) or wakeup from deep sleep the power switches of theblocks will be enabled one after another (power-chained) to decrease current peaks.
The blocks will be enabled in the following order:
1. Bandgap reference and voltage regulator,
2. Digital voltage regulator (DVREG) and low leakage voltage regulator (LLVREG),
3. SRAM block #0 (lower 4k bytes),
4. SRAM block #1,
5. SRAM block #2,

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6. SRAM block #3 (upper 4k bytes),
7. Radio transceiver including AES engine,
8. Non-volatile memory.
If the power-chain is completely enabled the standard AVR wake-up procedurecontinues.
Figure 12-2 shows the chained startup procedure after power up. A module is only
switched on if it is not deselected by power reduction register (PRR1 or PRR2). This ispossible for SRAM blocks and radio transceiver power switch. At the end of the startup,
the pin RSTON is enabled.
Figure 12-3 shows a similar procedure, the startup from deep sleep.
For further timing information see "Power Management Electrical Characteristics" onpage 503.
Figure 12-2. Timing visualization of power up
RSTO N
POR

startupbandgap

startup
DVREG

D R T sw itch
SRAM #0

D R T sw itch
S R A M #1

D R T sw itch
S R A M #2

D R T sw itch
S R A M #3

pow er sw itch pow er sw itchradio trans.
NVM

tP O R

tB G

tD V R E G

t D R T_ O N

t D R T_ O N

t D R T_ O N

t D R T_ O N

t P W R S W _O N

t P W R S W _O N

oscillator
startuptO S C_ S T A R T U P

tS T A R T U P

Figure 12-3. Timing visualization of wakeup from deep sleep
S LEE P

startupbandgap

startup
DVREG

D R T sw itch
S R A M #0

D R T sw itch
S R AM #1

D R T sw itch
S R A M #2

D R T sw itch
S R A M #3

pow er sw itch pow er sw itchradio trans.
NVM

tB G

tD V R E G

t D R T_ O N

t D R T_O N

t D R T _O N

t D R T _O N

tP W R S W _ O N

tP W R S W _ O N

oscillator
startupt O S C _S T A R T U P

tS T A R T UP

Sleep
Six sleep modes are defined for the CPU. Disabling the power-chain and thus switching
off of the above mentioned blocks makes only sense for the modes “power-down” and“power-save”. Also an enabled radio transceiver prevents the power-chain from being
disabled.
In order to disable the power-chain, one of the following conditions must fit:
• The radio transceiver has to be disabled (power reduction register PRR1 bit
PRTRX24).
• The radio transceiver is sent into SLEEP mode (register TRXPR bit SLPTR).
The SRAM blocks may be configured separately to decrease their leakage current (seesection "SRAM with Data Retention" on page 163).
The following table shows the different implemented sleep modes and the behavior of
the power-chain depending on the current state of the radio transceiver.
Table 12-2. Power states of microcontroller and radio transceiver162

AVR State

Radio Transceiver State

Powerchain

ON

ON

ON

ON

off (SLEEP or power reduction)

ON

off

(1…6)

ON

ON

off

(1,4…6)off (SLEEP or power reduction)

ON

ATmega128RFA1
8266A-MCU Wireless-12/09

ATmega128RFA1AVR State
(2,3)

off
DEEP SLEEP
Notes:

Radio Transceiver State

Powerchain

off (SLEEP or power reduction)

off

(7)

1. Idle2. Power Down
3. Power Save
4. ADC Noise Reduction Mode
5. Standby
6. Extended Standby
7.

12.5.2 SRAM with Data Retention
It is necessary to prevent any data loss of the SRAM when setting the CPU in one of
the sleep modes. For that purpose the SRAM blocks will not be completely switched off
if the power-chain is disabled. Instead the supply voltage for any individual SRAM blockis decreased to reduce its leakage current but guaranteeing its data retention.
The SRAM memory is divided into four separate blocks. Each block can be fully
switched off by setting the correspondent bit (PRRAM0 ... PRRAM3) in register PRR2
(see "PRR2 – Power Reduction Register 2" on page 168). This enables the application
software to switch off unused SRAM memory to save power and to reduce leakage
currents.
Every SRAM block can be enabled again by resetting the respective bit (PRRAM0 ...
PRRAM3) of register PRR2. For each SRAM block n the bit DRTSWOK of thecorresponding register DRTRAMn shows the state of the DRT switch (logic high means
SRAM block can be accessed).
If the power-chain is switched off during deep-sleep modes, the content of the SRAM
blocks must be sustained. To provide data retention and lowest leakage current, a dataretention block controls the SRAM behavior during deep-sleep. Since the leakage
current is dramatically depending from the voltage of the SRAM, the supply voltage canbe decreased by enabling the data retention mode DRT.
Every SRAM block n is controlled by its assigned register DRTRAMn. The bit ENDRT
enables the data retention mode during deep-sleep. If this bit is zero, the respective
SRAM block is completely switched off.
Table 12-3. SRAM behavior while in deep-sleep mode
ENDRTPower-chain

SRAM supply voltage

1ON

1.8V (DVDD)

0ON

1.8V (DVDD)

1

off

Reduced0

off

Disconnected

The lower 4-bit of the register DRTRAMn are reserved and should not be changed. The
reset value of the DRT voltage settings are preprogrammed during the manufacturing
process and need not to be changed.
12.5.3 Voltage Regulators (AVREG, DVREG)
The main features of the Voltage Regulator blocks are:• Bandgap stabilized 1.8V supply for analog and digital domain;

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• Low dropout (LDO) voltage regulator;• Configurable to use an external voltage regulator;
The internal voltage regulators supply a stabilized voltage to the ATmega128RFA1. The
AVREG provides the regulated 1.8V supply voltage for the analog section and the
DVREG supplies the 1.8V supply voltage for the digital section. The DVREG is enabledduring startup and is switched off if the power-chain is disabled. The AVREG is enabled
only on request by either the A/D converter or the radio transceiver.
A simplified schematic of the internal voltage regulator is shown in Figure 12-4 below.
Figure 12-4. Simplified Schematic of AVREG/DVREG(D )E V D D

B andgap
voltagereference

1 .25 V

AVDD,
DVDD

The voltage regulators require bypass capacitors for stable operation. The value of the
bypass capacitors determines their settling time. The bypass capacitors shall be placed
as close as possible to the pins and shall be connected to ground with the shortest
possible traces.
The voltage regulators can be configured with the register VREG_CTRL. It is
recommended to use the internal regulators but it is also possible to supply the low
voltage domains by an external voltage supply. For this configuration the internal
regulators need to be switched off by setting the register bits to the values
AVREG_EXT = 1 and DVREG_EXT = 1 (see "VREG_CTRL – Voltage Regulator
Control and Status Register" on page 115). A regulated external supply voltage of 1.8V
must then be connected to the pins 13, 14 (DVDD) and pin 29 (AVDD). When turningon the external supply ensure a sufficiently long stabilization time before interacting with
the ATmega128RFA1.
The status bits AVDD_OK = 1 and DVDD_OK = 1 of register VREG_CTRL indicate anenabled and stable internal supply voltage. Reading value 0 indicates that the internal
supply voltage is disabled or not yet settled to the final value.
Note that disabling the digital voltage regulator by DVREG_EXT bit is for internal use
only.
12.5.4 Low Leakage Voltage Regulator (LLVREG)
The main digital voltage regulator (DVREG) will be switched off during the deep sleep
modes “power-down” and “power-save”. The Low Leakage Voltage Regulator will thenkeep the digital supply voltage to provide data retention. No application software control
is required.
During the active power states, when the main voltage regulator supplies the chip, theLow Leakage Voltage Regulator is digitally calibrated. Its output voltage is adjusted tomatch the output voltage of the main regulator. This fixed calibration result is stored andused when the chip enters a power-down state where the main regulator is switched off.

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ATmega128RFA1
Because the calibration setting is fixed, temperature and load current variations during
the following Deep Sleep period are not regulated out. Thus the output voltage may drift
away from the target value. However the design guarantees that for allowed operating
conditions the output voltage will stay within valid limits. After every wake-up a new
calibration cycle is initiated.
The output driving capability of the Low Leakage Voltage Regulator is limited. Its main
purpose is to provide the leakage current of the connected analog and digital blocks.
At least one full calibration cycle of the Low Leakage Voltage Regulator has to becompleted before the power-chain can be disabled. Therefore if the CPU uses one ofthe deep sleep modes “power down” or “power save”, the power-chain is not disabled
before the Low Leakage Voltage Regulator completed this first calibration cycle.
By default the LLVREG automatically starts the calibration after finishing the power-on
reset and the wake-up/start-up procedures (see section "Low Leakage Voltage
Regulator Control" below for a detailed description of the Low Leakage Voltage
Regulator).
12.5.5 Low Leakage Voltage Regulator Control
The three register LLCR, LLDRL and LLDRH allow the software to monitor thecalibration process and to modify or correct the calibration results. The automatic
calibration is the normal operation mode. It is an internal process that does not require
any software interaction. Nevertheless the calibration is transparent for the user through
LLCR, LLDRL and LLDRH (control and data register respectively).
Before the device can enter the sleep mode “power down” or “power save” the firstcalibration cycle of the Low Leakage Voltage Regulator must be completed to get valid
data in LLDRL and LLDRH. The cycle time tLLVREG CALIB is not fixed. It depends on thetemperature, manufacturing process and the frequency of the 128 kHz RC oscillator(independent of the Watchdog setting).
Systems that require very short power-up times may temporarily disable the calibration
process by setting bit LLENCAL to 0.
The output voltage of the Low Leakage Voltage Regulator in sleep mode will be themost accurate if constantly calibrated to compensate for any environmental changes(e.g. temperature). However these changes may be slow enough to skip the calibrationthduring some power-up cycles (e.g. calibrate only every 10 power-up time and use theold calibration results during all other times).
After the completion of the power-up process the calibration will start automatically if bit
LLENCAL in the control register LLCR is 1 (default). The completion of a calibration
cycle is indicated by the bit LLDONE in that same register. After the first cycle thecalibration will continue to run until either the device goes into a sleep mode (“powerdown” or “power save”) or by setting the LLENCAL bit to 0. The output voltage of the
Low Leakage Voltage Regulator is then defined by the values in the data register
LLDRL and LLDRH and by the bits LLTCO and LLSHORT of the control register.
Write access to the three register is granted when the bit LLENCAL is set to 0. The
application software can then modify the calibration results. Higher values in the dataregister generate lower output voltages in the sleep modes. In general it is notrecommended nor required to alter the automatically generated calibration result.
The write access to the three register must follow a certain scheme to be successful.
The registers are implemented in the I/O clock domain while the logic of the Low
Leakage Voltage Regulator runs with 64 kHz (clock output of the 128 kHz RC oscillator
divided by 2). It takes at least two 64 kHz clock cycles before the data written to the165
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register take effect in the regulator circuit. The write access from the software must beaware of this process. Furthermore the value of LLDRH must be written first followed by
LLDRL. Otherwise the LLDRH write access will be ignored. The following Assembler
code fragment shows a working example. Note the polling of bit 3 LLCAL of the LLCR
register to verify the completion of the synchronization process.
Assembly Code Example…
clr r20IOST LLDRH,r18; write LLDRH first

IOST LLDRL,r19; write LLDRL second

IOST LLCR,r20; bit 0 cleared = disable automatic calibration; poll LLCAL bit of LLCR to check if automatic calibration is; turned of
wait_calib:
IOLD r20,LLCR
sbrc r20,3
rjmp wait_calib; not executed if bit 3 of LLCR is cleared…

12.6 Register Description
12.6.1 SMCR – Sleep Mode Control Register
Bit

7

6

5

4

3

2

1

0

$33 ($53)

Res3

Res2

Res1

Res0

SM2

SM1

SM0

SE

Read/Write
Initial Value

R
0

R
0

R
0

R
0

RW
0

RW
0

RW
0

RW
0

SMCR

The Sleep Mode Control Register contains control bits for power management.
• Bit 7:4 – Res3:0 - Reserved• Bit 3:1 – SM2:0 - Sleep Mode Select bit 2
These bits select between the five available sleep modes. Standby modes are only
recommended for use with external crystals or resonators.
Table 12-4 SM Register Bits
Register Bits

Value

Description

SM2:0

0x00

Idle

0x01

ADC Noise Reduction (If Available)

0x02

Power Down

0x03

Power Save

0x04

Reserved

0x05

Reserved

0x06

Standby0x07

Extended Standby• Bit 0 – SE - Sleep Enable

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ATmega128RFA1The SE bit must be written to logic one to make the MCU enter the sleep mode when
the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it
is the programmers purpose, it is recommended to write the Sleep Enable (SE) bit to
one just before the execution of the SLEEP instruction and to clear it immediately after
waking up.

12.6.2 PRR0 – Power Reduction Register0
Bit

7

6

5

4

3

2

1

0

NA ($64)PRTWI

PRTIM2

PRTIM0PRPGA

PRTIM1PRSPI

PRUSART0

PRADC

Read/Write
Initial Value

R/W
0

R/W
0

R/W
0

R/W
0

R/W
0

R/W
0

R/W
0

R/W
0

PRR0

• Bit 7 – PRTWI - Power Reduction TWI
Writing a logic one to this bit shuts down the TWI by stopping the clock to the module.
When waking up the TWI again, the TWI should be re initialized to ensure proper
operation.
• Bit 6 – PRTIM2 - Power Reduction Timer/Counter2
Writing a logic one to this bit shuts down the Timer/Counter2 module. When theTimer/Counter2 is enabled, operation will continue like before the shutdown.
• Bit 5 – PRTIM0 - Power Reduction Timer/Counter0
Writing a logic one to this bit shuts down the Timer/Counter0 module. When theTimer/Counter0 is enabled, operation will continue like before the shutdown.
• Bit 4 – PRPGA - Power Reduction PGA
Writing a logic one to this bit reduced the power consumption of the programmable gain
amplifier. The block is not turned off. Only the current levels in the amplifiers are
reduced. Reducing the PGA current levels is only recommended for slow ADC clock
frequencies. A new ADC conversion using the PGA should be delayed by a default
start-up time after changing (setting or resetting) this bit.
• Bit 3 – PRTIM1 - Power Reduction Timer/Counter1
Writing a logic one to this bit shuts down the Timer/Counter1 module. When theTimer/Counter1 is enabled, operation will continue like before the shutdown.
• Bit 2 – PRSPI - Power Reduction Serial Peripheral Interface
Writing a logic one to this bit shuts down the Serial Peripheral Interface by stopping theclock to the module. When waking up the SPI again, the SPI should be re initialized toensure proper operation.
• Bit 1 – PRUSART0 - Power Reduction USART
Writing a logic one to this bit shuts down the USART0 by stopping the clock to themodule. When waking up the USART0 again, the USART0 should be reinitialized toensure proper operation.
• Bit 0 – PRADC - Power Reduction ADC
Writing a logic one to this bit shuts down the ADC. The ADC must be disabled (reset
ADEN bit in register ADCSRA) before shut down. The analog comparator cannot use
the ADC input MUX when the ADC is shut down.

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12.6.3 PRR1 – Power Reduction Register 1
Bit

7

NA ($65)

Res

Read/Write
Initial Value

R
0

6

5

PRTRX24 PRTIM5
RW
0

RW
0

4

3

2

1

0

PRTIM4PRTIM3

PRUSART1

RW
0

RW
0

RW
0

PRR1

• Bit 7 – Res - Reserved Bit
This bit is reserved for future use. A read access always will return zero. A write accessdoes not modify the content.
• Bit 6 – PRTRX24 - Power Reduction Transceiver
Writing a logic one to this bit shuts down the transceiver (disconnect from the power
supply). In power-down and power-save modes the power-chain will be disabled when
this bit is one. Writing a logic zero to this bit will re-enable the transceiver.
• Bit 5 – PRTIM5 - Power Reduction Timer/Counter5
Writing a logic one to this bit shuts down the Timer/Counter5 module. When theTimer/Counter5 is enabled, operation will continue like before the shutdown.
• Bit 4 – PRTIM4 - Power Reduction Timer/Counter4
Writing a logic one to this bit shuts down the Timer/Counter4 module. When theTimer/Counter4 is enabled, operation will continue like before the shutdown.
• Bit 3 – PRTIM3 - Power Reduction Timer/Counter3
Writing a logic one to this bit shuts down the Timer/Counter3 module. When theTimer/Counter3 is enabled, operation will continue like before the shutdown.
• Bit 0 – PRUSART1 - Power Reduction USART1
Writing a logic one to this bit shuts down the USART1 by stopping the clock to themodule. When waking up the USART1 again, the USART1 should be reinitialized toensure proper operation.

12.6.4 PRR2 – Power Reduction Register 2
Bit

7

6

5

4

NA ($63)

Res3

Res2

Res1

Res0

Read/Write
Initial Value

R
0

R
0

R
0

R
0

3

2

1

0

PRRAM3 PRRAM2 PRRAM1 PRRAM0
RW
0

RW
0

RW
0

PRR2

RW
0

The Power Reduction Register PRR2 allows to individually disable all four SRAM
blocks. Setting any PRRAM3:0 bit to one will completely switch off (disconnect from thepower supply) the corresponding SRAM block. This enables the application to disable
unused SRAM memory to save power. Every SRAM block can be re-enabled byreseting the appropriate PRRAM3:0 bit.
• Bit 7:4 – Res3:0 - Reserved Bit
This bit is reserved for future use. A read access always will return zero. A write accessdoes not modify the content.
• Bit 3 – PRRAM3 - Power Reduction SRAM 3
Setting this bit to one will disable the SRAM block 3. Setting this bit to zero will enable
the SRAM block 3.

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ATmega128RFA1• Bit 2 – PRRAM2 - Power Reduction SRAM 2
Setting this bit to one will disable the SRAM block 2. Setting this bit to zero will enable
the SRAM block 2.
• Bit 1 – PRRAM1 - Power Reduction SRAM 1
Setting this bit to one will disable the SRAM block 1. Setting this bit to zero will enable
the SRAM block 1.
• Bit 0 – PRRAM0 - Power Reduction SRAM 0
Setting this bit to one will disable the SRAM block 0. Setting this bit to zero will enable
the SRAM block 0.

12.6.5 TRXPR – Transceiver Pin Register
Bit

7

6

5

4

3

2

1

0

NA ($139)

Res3

Res2

Res1

Res0

Resx3

Resx2

SLPTR

TRXRST

Read/Write
Initial Value

R
0

R
0

R
0

R
0

RW
0

RW
0

RW
0

RW
0

TRXPR

The register TRXPR allows to control basic actions of the radio transceiver like reset orstate transitions. The register bit functionality is inherited from the external pins of thestand-alone radio transceiver.
• Bit 7:4 – Res3:0 - Reserved• Bit 3:2 – Resx3:2 - Reserved• Bit 1 – SLPTR - Multi-purpose Transceiver Control Bit
The bit SLPTR is a multi-functional bit to control transceiver state transitions.
Dependent on the radio transceiver state, a rising edge of bit SLPTR causes thefollowing state transitions: TRX_OFF => SLEEP (level sensitive), PLL_ON =>BUSY_TX. Whereas the falling edge of bit SLPTR causes the following state transition:
SLEEP => TRX_OFF (level sensitive). When the radio transceiver is in TRX_OFF state
the microcontroller forces the transceiver to SLEEP by setting SLPTR = H. The
Transceiver awakes when the microcontroller releases the bit SLPTR. In states
PLL_ON and TX_ARET_ON, bit SLPTR is used as trigger input to initiate a TX
transaction. Here SLPTR is sensitive on rising edge only. After initiating a state change
by a rising edge at Bit SLPTR in radio transceiver states TRX_OFF, RX_ON or
RX_AACK_ON, the radio transceiver remains in the new state as long as the pin is
logical high and returns to the preceding state with the falling edge.
• Bit 0 – TRXRST - Force Transceiver Reset
The RESET state is used to set back the state machine and to reset all registers of thetransceiver to their default values. A reset forces the radio transceiver into the
TRX_OFF state and resets all transceiver register to their default values. A reset isinitiated with bit TRXRST = H. The bit is cleared automatically During transceiver reset
the microcontroller has to set the radio transceiver control bit SLPTR to the default
value.

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12.6.6 DRTRAM0 – Data Retention Configuration Register of SRAM 0
Bit

7

6

5

4

3

2

1

0

NA ($135)

Res1

Res0

DRTSWOK

ENDRT

Resx3

Resx2

Resx1

Resx0

Read/Write
Initial Value

R
0

R
0

R
0

RW
0

RW
0

RW
0

RW
0

RW
0

DRTRAM0

The DRTRAM0 register controls the behavior of SRAM block 0 in the power-states"power-save" and "power-down". To prevent any data loss the SRAM will notcompletely disconnected from the power supply. Reserved bits will be overwritten
during chip reset by the factory calibration and should not be modified.
• Bit 7:6 – Res1:0 - Reserved• Bit 5 – DRTSWOK - DRT Switch OKThis bit indicates the status of the SRAM power-switch. A logical one indicates that the
SRAM supply voltage is fully available and the memory may be accessed normally.
• Bit 4 – ENDRT - Enable SRAM Data Retention
During "Deep-Sleep" each SRAM block will either be switched off or provides dataretention of its memory content. This bit must set to one if data retention mode should
be used. Otherwise the SRAM is switched off (disconnected from the power supply)
and all its data are lost.
• Bit 3:0 – Resx3:0 - Reserved

12.6.7 DRTRAM1 – Data Retention Configuration Register of SRAM 1
Bit

7

6

5

4

3

2

1

0

NA ($134)

Res1

Res0

DRTSWOK

ENDRT

Resx3

Resx2

Resx1

Resx0

Read/Write
Initial Value

R
0

R
0

R
0

RW
0

RW
0

RW
0

RW
0

RW
0

DRTRAM1

The DRTRAM1 register controls the behavior of SRAM block 1 in the power-states"power-save" and "power-down". To prevent any data loss the SRAM will notcompletely disconnected from the power supply. Reserved bits will be overwritten
during chip reset by the factory calibration and should not be modified.
• Bit 7:6 – Res1:0 - Reserved• Bit 5 – DRTSWOK - DRT Switch OKThis bit indicates the status of the SRAM power-switch. A logical one indicates that the
SRAM supply voltage is fully available and the memory may be accessed normally.
• Bit 4 – ENDRT - Enable SRAM Data Retention
During "Deep-Sleep" each SRAM block will either be switched off or provides dataretention of its memory content. This bit must set to one if data retention mode should
be used. Otherwise the SRAM is switched off (disconnected from the power supply)
and all its data are lost.
• Bit 3:0 – Resx3:0 - Reserved

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ATmega128RFA1
12.6.8 DRTRAM2 – Data Retention Configuration Register of SRAM 2
Bit

7

6

5

4

3

2

1

0

NA ($133)

Resx7

Res

DRTSWOK

ENDRT

Resx3

Resx2

Resx1

Resx0

Read/Write
Initial Value

RW
0

R
0

R
0

RW
0

RW
0

RW
0

RW
0

RW
0

DRTRAM2

The DRTRAM2 register controls the behavior of SRAM block 2 in the power-states"power-save" and "power-down". To prevent any data loss the SRAM will notcompletely disconnected from the power supply. Reserved bits will be overwritten
during chip reset by the factory calibration and should not be modified.
• Bit 7 – Resx7 - Reserved• Bit 6 – Res - Reserved Bit
This bit is reserved for future use. A read access always will return zero. A write accessdoes not modify the content.
• Bit 5 – DRTSWOK - DRT Switch OKThis bit indicates the status of the SRAM power-switch. A logical one indicates that the
SRAM supply voltage is fully available and the memory may be accessed normally.
• Bit 4 – ENDRT - Enable SRAM Data Retention
During "Deep-Sleep" each SRAM block will either be switched off or provides dataretention of its memory content. This bit must set to one if data retention mode should
be used. Otherwise the SRAM is switched off (disconnected from the power supply)
and all its data are lost.
• Bit 3:0 – Resx3:0 - Reserved

12.6.9 DRTRAM3 – Data Retention Configuration Register of SRAM 3
Bit

7

6

5

4

3

2

1

0

NA ($132)

Res1

Res0

DRTSWOK

ENDRT

Resx3

Resx2

Resx1

Resx0

Read/Write
Initial Value

R
0

R
0

R
0

RW
0

RW
0

RW
0

RW
0

RW
0

DRTRAM3

The DRTRAM3 register controls the behavior of SRAM block 3 in the power-states"power-save" and "power-down". To prevent any data loss the SRAM will notcompletely disconnected from the power supply. Reserved bits will be overwritten
during chip reset by the factory calibration and should not be modified.
• Bit 7:6 – Res1:0 - Reserved• Bit 5 – DRTSWOK - DRT Switch OKThis bit indicates the status of the SRAM power-switch. A logical one indicates that the
SRAM supply voltage is fully available and the memory may be accessed normally.
• Bit 4 – ENDRT - Enable SRAM Data Retention
During "Deep-Sleep" each SRAM block will either be switched off or provides dataretention of its memory content. This bit must set to one if data retention mode should
be used. Otherwise the SRAM is switched off (disconnected from the power supply)
and all its data are lost.
• Bit 3:0 – Resx3:0 - Reserved

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12.6.10 LLCR – Low Leakage Voltage Regulator Control Register
Bit

7

6

NA ($12F)

Res1

Res0

Read/Write
Initial Value

R
0

R
0

5

4

LLDONE LLCOMP
R
0

R
0

3

2

LLCAL

LLTCO

R
0

RW
0

1

0

LLSHORT LLENCAL
RW
0

LLCR

RW
1

This register allows to monitor and to control the calibration process of the low-leakage
voltage regulator. The automatic calibration is the normal operation mode. However,certain circumstances may require to disable this automatic process for instance tosave power-up time. The results of the automatic calibration can also be modified whenrequired by the application for instance to get a higher or lower output voltage.
• Bit 7:6 – Res1:0 - Reserved Bit
This bit is reserved for future use. A read access always will return zero. A write accessdoes not modify the content.
• Bit 5 – LLDONE - Calibration Done
This bit indicates the last state of the calibration algorithm. The data register contents is
updated with new calibration data after the bit changed to 1. The bit will only be high forone 64kHz clock period, because a new calibration loop is started automatically.
• Bit 4 – LLCOMP - Comparator Output
This bit indicates the output state of the comparator of the low-leakage voltage
regulator. In this way the calibration progress can be directly monitored for debug
purposes. The state of the bit changes at most every 64kHz clock period.
• Bit 3 – LLCAL - Calibration Active
This bit indicates that the automatic calibration is in progress. The analog part of thecalibration circuit is powered up if the bit is 1.
• Bit 2 – LLTCO - Temperature Coefficient of Current SourceThis bit shows the status of the selection of the temperature coefficient. The state of the
bit is updated in the course of the automatic calibration. A valid value is present after
the LLDONE bit is 1 for the first time. Write access is only enabled when the automatic
calibration is turned off (LLENCAL is 0). This bit should not be changed without further
information.
• Bit 1 – LLSHORT - Short Lower Calibration Circuit
This bit shows the status of the short switch for the lower calibration circuit. The state of
the bit is updated in the course of the automatic calibration. A valid value is present
after the LLDONE bit is 1 for the first time. If this bit is set to 1 register LLDRL has nofunction. Write access is only possible when the automatic calibration is turned off(LLENCAL is 0). This bit should not be changed without further information.
• Bit 0 – LLENCAL - Enable Automatic Calibration
This bit enables the automatic calibration. The automatic calibration runs if the state of
the bit is 1. Write access to the two data register and the bits LLSHORT and LLTCO isthen denied. If the state of LLENCAL is 0 then the calibration algorithm is stopped andthe output voltage of the low-leakage voltage regulator is defined by the values in thetwo data register LLDRL and LLDRH and by the bits LLSHORT and LLTCO.

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12.6.11 LLDRH – Low Leakage Voltage Regulator Data Register (High-Byte)
Bit

7

6

5

NA ($131)

Res2

Res1

Res0

Read/Write
Initial Value

R
0

R
0

R
0

4

3

2

1

0

LLDRH4 LLDRH3 LLDRH2 LLDRH1 LLDRH0
RW
0

RW
0

RW
0

RW
0

LLDRH

RW
0

The high-byte of the calibration data can be accessed through this register. Writeaccess is only enabled when the bit LLENCAL of the LLCR register is 0. Then the databits LLDRH4:0 directly control the output voltage of the low-leakage voltage regulator.
Higher numbers generate lower voltages. If the bit LLENCAL is 1 then the results of theautomatic calibration are stored.
• Bit 7:5 – Res2:0 - Reserved
These bits are reserved for future use.
• Bit 4:0 – LLDRH4:0 - High-Byte Data Register Bits
Value of the high-byte calibration result
Table 12-5 LLDRH Register Bits
Register Bits

Value

Description

LLDRH4:0

0x00

Calibration limit for fast process corner/highoutput voltage

0x10Calibration limit for slow process corner/low
output voltage

12.6.12 LLDRL – Low Leakage Voltage Regulator Data Register (Low-Byte)
Bit

7

6

5

4

3

2

1

0

NA ($130)

Res3

Res2

Res1

Res0

LLDRL3LLDRL2LLDRL1LLDRL0

Read/Write
Initial Value

R
0

R
0

R
0

R
0

RW
0

RW
0

RW
0

RW
0

LLDRL

The low-byte of the calibration data can be accessed through this register. Write accessis only enabled when the bit LLENCAL of the LLCR register is 0. Then the data bits
LLDRL3:0 directly control the output voltage of the low-leakage voltage regulator.
Higher numbers generate lower voltages. The contents of this register is meaninglesswhen the bit LLSHORT of the LLCR register is 1. If the bit LLENCAL is 1 then the
results of the automatic calibration are stored.
• Bit 7:4 – Res3:0 - Reserved
These bits are reserved for future use.
• Bit 3:0 – LLDRL3:0 - Low-Byte Data Register Bits
Value of the low-byte calibration result
Table 12-6 LLDRL Register Bits
Register Bits

Value

Description

LLDRL3:0

0x00

Calibration limit for fast process corner/highoutput voltage

0x08

Calibration limit for slow process corner/low
output voltage

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12.6.13 DPDS0 – Port Driver Strength Register 0
Bit
NA ($136)

7

6

5

4

3

2

1

0

PFDRV1 PFDRV0 PEDRV1 PEDRV0 PDDRV1 PDDRV0 PBDRV1 PBDRV0

Read/Write
Initial Value

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

DPDS0

RW
0

The output driver strength can be set individually for each digital I/O port. The following
tables show output current levels for a typical supply voltage of DEVDD = 3.3V. Refer tosection "Electrical Characteristics" for details.
• Bit 7:6 – PFDRV1:0 - Driver Strength Port F
Table 12-7 PFDRV Register Bits
Register BitsPFDRV1:0

Value

Description

0

2 mA

1

4 mA

2

6 mA

3

8 mA

• Bit 5:4 – PEDRV1:0 - Driver Strength Port E
Table 12-8 PEDRV Register Bits
Register Bits

Value

Description

PEDRV1:0

0

2 mA

1

4 mA

2

6 mA

3

8 mA

• Bit 3:2 – PDDRV1:0 - Driver Strength Port D
Table 12-9 PDDRV Register Bits
Register Bits

Value

Description

PDDRV1:0

0

2 mA

1

4 mA

2

6 mA

3

8 mA

• Bit 1:0 – PBDRV1:0 - Driver Strength Port B
Table 12-10 PBDRV Register Bits

174

Register Bits

Value

Description

PBDRV1:0

0

2 mA

1

4 mA

2

6 mA

3

8 mA

ATmega128RFA1
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ATmega128RFA1
12.6.14 DPDS1 – Port Driver Strength Register 1
Bit

7

6

5

4

3

2

NA ($137)

Res5

Res4

Res3

Res2

Res1

Res0

Read/Write
Initial Value

R
0

R
0

R
0

R
0

R
0

R
0

1

0

PGDRV1 PGDRV0
RW
0

DPDS1

RW
0

The output driver strength can be set individually for each digital I/O port. The following
table shows output current levels for a typical supply voltage of DEVDD = 3.3V. Refer tosection "Electrical Characteristics" for details.
• Bit 7:2 – Res5:0 - Reserved• Bit 1:0 – PGDRV1:0 - Driver Strength Port G
Driver strength can be set for port G except the port pins PG3 and PG4. The leakage
current of the ports PG3 and PG4 is reduced.
Table 12-11 PGDRV Register Bits
Register Bits

Value

Description

PGDRV1:0

0

2 mA

1

4 mA

2

6 mA

3

8 mA

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13 System Control and Reset
13.1 Resetting the AVR
During reset, all I/O Registers are set to their initial values, and the program starts
execution from the Reset Vector. The instruction placed at the Reset Vector must be a
JMP – Absolute Jump – instruction to the reset handling routine. If the program neverenables an interrupt source, the Interrupt Vectors are not used, and regular programcode can be placed at these locations. This is also the case if the Reset Vector is in the
Application section while the Interrupt Vectors are in the Boot section or vice versa. The
circuit diagram in Figure 13-1 on page 177 shows the reset logic."System and ResetCharacteristics" on page 502 defines the electrical parameters of the reset circuitry.
The I/O ports of the AVR are immediately reset to their initial state when a reset source
goes active. This does not require any clock source to be running.
After all reset sources have gone inactive, a delay counter is invoked, stretching theinternal reset. This allows the power to reach a stable level before normal operation
starts. The time-out period of the delay counter is defined by the user through the SUT
and CKSEL Fuses. The different selections for the delay period are presented in "ClockSources" on page 148.

13.2 Reset Sources
The ATmega128RFA1 has five sources of reset:• Power-on Reset. The MCU is reset when the supply voltage is below the Power-on
Reset threshold (VPOT).
• External Reset. The MCU is reset when a low level is present on the RSTN pin for
longer than the minimum pulse length.
• Watchdog Reset. The MCU is reset when the Watchdog Timer period expires andthe Watchdog is enabled.
• Brown-out Reset. The MCU is reset when the supply voltage EVDD is below the
Brown-out Reset threshold (VBOT) and the Brown-out Detector is enabled.
• JTAG AVR Reset. The MCU is reset as long as there is a logic one in the ResetRegister, one of the scan chains of the JTAG system. Refer to the section "IEEE1149.1 (JTAG) Boundary-scan" on page 441 for details.

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ATmega128RFA1
Figure 13-1. Reset Logic
DATA BUS

EVDD

BORF
PORF
EXTRF
WDRF
JTRF

MCU Status
Register (MCUSR)

Brown-out
Reset Circuit

BODLEVEL [2..0]

DEVDD

Pull-up Resistor
SPIKE
FILTER

Reset Circuit

JTAG ResetRegister

Watchdog
Timer

S
COUNTER RESET

RSTN

Watchdog
Oscillator

Clock
Generator

CK

R

Q

INTERNAL RESETPower-onReset Circuit

Delay Counters
TIMEOUTCKSEL[3:0]
SUT[1:0]13.2.1 Power-on Reset
A Power-on Reset (POR) pulse is generated by a dynamic, on-chip detection circuit.
The POR is active when DEVDD is rising. The electrical characteristics are defined in"System and Reset Characteristics" on page 502. The POR circuit can be used totrigger the start-up reset. To detect a failure in the supply voltage (e.g. a voltage drop)
the brown-own detector should be used.
A Power-on Reset (POR) circuit ensures that the device is reset from Power-on.
Reaching the Power-on Reset threshold voltage invokes the delay counter, which
determines how long the device is kept in RESET after the DEVDD rise. The RESET
signal is activated again without any delay, when DEVDD decreases below thedetection level.
Figure 13-2. MCU Start-up, RSTN Tied to DEVDD
DEVDD

RSTN

TIME-OUT

V POT

V RST

tTOUT

INTERNAL
RESET

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Figure 13-3. MCU Start-up, RSTN Extended Externally
VCC

V POT

V RST

RSTN

tTOUT

TIME-OUT
INTERNAL
RESET

13.2.2 External Reset
An External Reset is generated by a low level on the RSTN pin. Reset pulses longer
than the minimum pulse width (see "System and Reset Characteristics" on page 502)
will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed
to generate a reset. When the applied signal reaches the Reset Threshold Voltage –VRST – on its positive edge, the delay counter starts the MCU after the Time-out period –tTOUT – has expired.
Figure 13-4. Reset During Operation
DEVDD

RSTN

TIME-OUT

V RST

tTOUT

INTERNAL
RESET

13.2.3 Brown-out Detection
ATmega128RFA1 has an On-chip Brown-out Detection (BOD) circuit for monitoring the
EVDD level during operation by comparing it to a fixed trigger level. The trigger level for
the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis
to ensure spike free Brown-out Detection. The hysteresis on the detection level should
be interpreted as VBOT+ = VBOT + VHYST/2 and VBOT-= VBOT - VHYST/2.
When the BOD is enabled, and EVDD decreases to a value below the trigger level(VBOT- in Figure 13-5 on page 179), the Brown-out Reset is immediately activated. WhenEVDD increases above the trigger level (VBOT+ in Figure 13-5 on page 179), the delay
counter starts the MCU after the Time-out period tTOUT has expired.
The BOD circuit will only detect a drop in EVDD if the voltage stays below the trigger
level for longer than tBOD given in "System and Reset Characteristics" on page 502.

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ATmega128RFA1
Figure 13-5. Brown-out Reset During Operation
EVDD

V BOT+V BOT-

RSTN

tTOUT

TIME-OUT
INTERNAL
RESET

13.2.4 Watchdog Reset
When the Watchdog times out, it will generate a short reset pulse of one CK cycle
duration. On the falling edge of this pulse, the delay timer starts counting the Time-out
period tTOUT. See "Watchdog Timer" on page 180. for details on operation of theWatchdog Timer.
Figure 13-6. Watchdog Reset During Operation
DEVDD

RSTN
1 CK Cycle
WDT
TIME-OUTRESET
TIME-OUT

tTOUT

INTERNAL
RESET

13.3 Internal Voltage Reference
ATmega128RFA1 features an internal bandgap reference. This reference is used forBrown-out Detection, and it can be used as an input to the Analog Comparator or the
ADC.
Voltage Reference Enable Signals and Start-up TimeThe voltage reference has a start-up time that may influence the way it should be used.
The start-up time is given in "System and Reset Characteristics" on page 502. To savepower, the reference is not always turned on. The reference is on during the following
situations:
1. When the BOD is enabled (by programming the BODLEVEL [2:0] Fuse).
2. When the bandgap reference is connected to the Analog Comparator (by setting the
ACBG bit in ACSR).
3. When the ADC is enabled.
Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC,
the user must always allow the reference to start up before the output from the Analog
Comparator or ADC is used. To reduce power consumption in Power-down mode, theuser can avoid the three conditions above to ensure that the reference is turned off
before entering Power-down mode.
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13.4 Watchdog Timer
13.4.1 Features• Clocked from separate On-chip Oscillator• 3 Operating modes- Interrupt- System Reset- Interrupt and System Reset• Selectable Time-out period from 16ms to 8s• Possible Hardware fuse Watchdog always on (WDTON) for fail-safe mode

128kHzOSCILLATORWATCHDOG
RESET
WDE

OSC/2K
OSC/4K
OSC/8K
OSC/16K
OSC/32K
OSC/64K
OSC/128K
OSC/256K
OSC/512K
OSC/1024K

Figure 13-7. Watchdog Timer

WDP0
WDP1
WDP2
WDP3
MCU RESET

WDIF

WDIE

INTERRUPT

13.4.2 Overview
ATmega128RFA1 has an Enhanced Watchdog Timer (WDT). The WDT is a timer
counting cycles of a separate on-chip 128 kHz oscillator. The WDT gives an interrupt ora system reset when the counter reaches a given time-out value. In normal operationmode, it is required that the system uses the WDR -Watchdog Timer Reset - instruction
to restart the counter before the time-out value is reached. If the system doesn't restart
the counter, an interrupt or system reset will be issued.
In Interrupt mode, the WDT gives an interrupt when the timer expires. This interrupt canbe used to wake the device from sleep-modes, and also as a general system timer.
One example is to limit the maximum time allowed for certain operations, giving aninterrupt when the operation has run longer than expected. In System Reset mode, theWDT gives a reset when the timer expires. This is typically used to prevent systemhang-up in case of runaway code. The third mode, Interrupt and System Reset mode,
combines the other two modes by first giving an interrupt and then switch to System
Reset mode. This mode will for instance allow a safe shutdown by saving criticalparameters before a system reset.
The Watchdog always on (WDTON) fuse, if programmed, will force the Watchdog Timer
to System Reset mode. With the fuse programmed the System Reset mode bit (WDE)and Interrupt mode bit (WDIE) are locked to 1 and 0 respectively. To further ensure

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ATmega128RFA1
program security, alterations to the Watchdog set-up must follow timed sequences. The
sequence for clearing WDE and changing time-out configuration is as follows:
1. In the same operation, write a logic one to the Watchdog change enable bit (WDCE)
and WDE. A logic one must be written to WDE regardless of the previous value ofthe WDE bit.
2. Within the next four clock cycles, write the WDE and Watchdog prescaler bits (WDP)
as desired, but with the WDCE bit cleared. This must be done in one operation.
The following code example shows one assembly and one C function for turning off theWatchdog Timer. The example assumes that interrupts are controlled (e.g. by disabling
interrupts globally) so that no interrupts will occur during the execution of thesefunctions.
Assembly Code Example
WDT_off:(1); Turn off global interrupt
cli; Reset Watchdog Timer
wdr; Clear WDRF in MCUSR
in

r16, MCUSR

andi

r16, (0xff & (0<<WDRF))

out

MCUSR, r16; Write logical one to WDCE and WDE; Keep old prescaler setting to prevent unintentional time-out
ldi r16, WDTCSR
ori r16, (1<<WDCE) | (1<<WDE)
sts WDTCSR, r16; Turn off WDT
ldi r16, (0<<WDE)
sts WDTCSR, r16; Turn on global interrupt
sei
ret
(1)

C Code Example
void WDT_off(void){
disable_interrupt();
watchdog_reset();/* Clear WDRF in MCUSR*/
MCUSR &= ~(1<<WDRF);/* Write logical one to WDCE and WDE *//* Keep old prescaler setting to prevent unintentional time-out */WDTCSR |= (1<<WDCE) | (1<<WDE);/* Turn off WDT */WDTCSR = 0x00;__enable_interrupt();}

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Note:

1. The example code assumes that the part specific header file is included.

If the Watchdog is accidentally enabled, for example by a runaway pointer or brown-out
condition, the device will be reset and the Watchdog Timer will stay enabled. If the code
is not set up to handle the Watchdog, this might lead to an eternal loop of time-out
resets. To avoid this situation, the application software should always clear the
Watchdog System Reset Flag (WDRF) and the WDE control bit in the initialization
routine, even if the Watchdog is not in use.
The following code example shows one assembly and one C function for changing thetime-out value of the Watchdog Timer.
(1,2)

Assembly Code Example
WDT_Prescaler_Change:; Turn off global interrupt cli; Reset Watchdog Timer
wdr; Start timed sequenceinr16, WDTCSR

orir16, (1<<WDCE) | (1<<WDE)

out

WDTCSR, r16; --Got four cycles to set the new values from here –; Set new prescaler(time-out) value = 64K cycles (~0.5 s)
ldi

r16, (1<<WDE) | (1<<WDP2) | (1<<WDP0)out

WDTCSR, r16; --Finished setting new values, used 2 cycles –; Turn on global interrupt
sei
ret
(1,2)

C Code Example
void WDT_Prescaler_Change(void){__disable_interrupt();__watchdog_reset();/* Start timed

equence */WDTCSR |= (1<<WDCE) | (1<<WDE);/* Set new prescaler(time-out) value = 64K cycles (~0.5 s) */WDTCSR= (1<<WDE) | (1<<WDP2) | (1<<WDP0);__enable_interrupt();}
Note:

1. The example code assumes that the part specific header file is included.
2. The Watchdog Timer should be reset before any change of the WDP
bits, since a change in the WDP bits can result in a time-out whenswitching to a shorter time-out period.

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13.5 Register Description
13.5.1 MCUSR – MCU Status Register
Bit

7

6

5

4

3

2

1

0

$34 ($54)

Res2

Res1

Res0

JTRF

WDRF

BORF

EXTRF

PORF

Read/Write
Initial Value

R
0

R
0

R
0

RW
0

R/W
0

R/W
0

R/W
0

R/W
0

MCUSR

The MCU Status Register provides information on which reset source caused an MCU
reset. To make use of the Reset Flags to identify a reset condition, the user should readand then Reset the MCUSR as early as possible in the program. If the register iscleared before another reset occurs, the source of the reset can be found by examining
the Reset Flags. Note, after power on the bit EXTRF has to be ignored.
• Bit 7:5 – Res2:0 - Reserved• Bit 4 – JTRF - JTAG Reset Flag
This bit is set if a reset is being caused by a logic one in the JTAG Reset Register
selected by the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset,
or by writing a logic zero to the flag.
• Bit 3 – WDRF - Watchdog Reset Flag
This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by
writing a logic zero to the flag.
• Bit 2 – BORF - Brown-out Reset Flag
This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by
writing a logic zero to the flag.
• Bit 1 – EXTRF - External Reset Flag
This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by
writing a logic zero to the flag.
• Bit 0 – PORF - Power-on Reset Flag
This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to
the flag.

13.5.2 WDTCSR – Watchdog Timer Control Register
Bit

7

6

5

4

3

2

1

0

NA ($60)

WDIF

WDIE

WDP3

WDCE

WDE

WDP2

WDP1

WDP0

Read/Write
Initial Value

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

WDTCSR• Bit 7 – WDIF - Watchdog Timeout Interrupt Flag
This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timeris configured for interrupt. WDIF is cleared by hardware when executing thecorresponding interrupt handling vector. Alternatively, WDIF is cleared by writing a logic
one to the flag. When the I-bit in SREG and WDIE are set, the Watchdog Time-out
Interrupt is executed.

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• Bit 6 – WDIE - Watchdog Timeout Interrupt Enable
When this bit is written to one and the I-bit in the Status Register is set, the Watchdog
Interrupt is enabled. If WDE is cleared in combination with this setting, the Watchdog
Timer is in Interrupt Mode, and the corresponding interrupt is executed if time-out in the
Watchdog Timer occurs. If WDE is set, the Watchdog Timer is in Interrupt and System
Reset Mode. The first time-out in the Watchdog Timer will set WDIF. Executing thecorresponding interrupt vector will clear WDIE and WDIF automatically by hardware(the Watchdog goes to System Reset Mode). This is useful for keeping the Watchdog
Timer security while using the interrupt. To stay in Interrupt and System Reset Mode,
WDIE must be set after each interrupt. This should however not be done within theinterrupt service routine itself, as this might compromise the safety-function of theWatchdog System Reset mode. If the interrupt is not executed before the next time-out,a System Reset will be applied.
Table 13-1. Watchdog Timer Configuration
(1)

WDTON

WDE

WDIE

Mode

Action on Time-out

1

0

0

Stopped

None

1

0

1

Interrupt Mode

Interrupt

1

1

0

System Reset Mode

Reset

1

1

1

Interrupt and System
Reset Mode

Interrupt, then go to
System Reset Mode

0

x

x

System Reset Mode

Reset

Note:

1. WDTON Fuse set to “0“ means programmed and “1” means un-programmed.

• Bit 4 – WDCE - Watchdog Change Enable
This bit is used in timed sequences for changing WDE and prescaler bits. To clear the
WDE bit, and/or change the prescaler bits, WDCE must be set. Once written to one,hardware will clear WDCE after four clock cycles.
• Bit 3 – WDE - Watch Dog Enable
When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared(zero) the Watchdog Timer function is disabled. WDE can only be cleared if the
WDTOE bit is set (one). To disable an enabled watchdog timer, the following proceduremust be followed: 1. In the same operation, write a logical one to WDTOE and WDE. A
logical one must be written to WDE even though it is set to one before the disable
operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. Thisdisables the watchdog. WDE is overridden by WDRF in MCUSR. This means that WDE
is always set when WDRF is set. To clear WDE, WDRF must be cleared first. Thisfeature ensures multiple resets during conditions causing failure, and a safe start-up
after the failure.
• Bit 5, 2:0 – WDP3:0 – Watchdog Timer Prescaler 3, 2, 1 and 0
The WDP3:0 bits determine the Watchdog Timer prescaling when the Watchdog Timeris running.
Table 13-2. WDP Register Bits

184

Register Bits

Value

Description

WDP3:00x00

Oscillator Cycles 2k, (16ms)

0x01

Oscillator Cycles 4k, (32ms)

0x02

Oscillator Cycles 8k, (64ms)

0x03

Oscillator Cycles 16k, (0.125s)

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ATmega128RFA1
Register Bits

Value

Description

0x04

Oscillator Cycles 32k, (0.25s)

0x05

Oscillator Cycles 64k, (0.5s)

0x06

Oscillator Cycles 128k, (1.0s)

0x07

Oscillator Cycles 256k, (2.0s)

0x08

Oscillator Cycles 512k, (4.0s)

0x09

Oscillator Cycles 1024k, (8.0s)

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14 I/O-Ports
14.1 Introduction
All ATmega128RFA1 ports have true Read-Modify-Write functionality when used as
general digital I/O ports. This means that the direction of one port pin can be changed
without unintentionally changing the direction of any other pin with the SBI and CBIinstructions. The same applies when changing drive value (if configured as output) or
enabling/disabling of pull-up resistors (if configured as input). Each output buffer has
symmetrical drive characteristics with both configurable sink and source capability.
Every port is individually configurable in four different drive strengths. The pin driver isstrong enough to drive LED displays directly. All port pins have individually selectable
pull-up resistors with a supply-voltage invariant resistance. All I/O pins have protection
diodes to both DEVDD and DVSS as indicated in Figure 14-1 below. Refer to "Electrical
Characteristics" on page 501 for a complete list of parameters.
Figure 14-1. I/O Pin Equivalent Schematic

All registers and bit references in this section are written in general form. A lower case“x” represents the numbering letter for the port, and a lower case “n” represents the bit
number. However, when using the register or bit defines in a program, the precise form
must be used. For example, PORTB3 for bit no. 3 in Port B, here documented generally
as PORTxn.
Three I/O memory address locations are allocated for each port, one each for the Data
Register – PORTx, Data Direction Register – DDRx, and the Port Input Pins – PINx.
The Port Input Pins I/O location is read only, while the Data Register and the Data
Direction Register are read/write. However, writing a logic one to a bit in the PINx
Register, will result in a toggle in the corresponding bit in the Data Register. In addition,
the Pull-up Disable – PUD bit in MCUCR disables the pull-up function for all pins in all
ports when set.
Using the I/O port as General Digital I/O is described in "Ports as General Digital I/O"
on page 187. Most port pins are multiplexed with alternate functions for the peripheralfeatures on the device. How each alternate function interferes with the port pin is
described in "Alternate Port Functions" on page 191. Refer to the individual module
sections for a full description of the alternate functions.
Note that enabling the alternate function of some of the port pins does not affect the useof the other pins in the port as general digital I/O.

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14.2 Ports as General Digital I/O
The ports are bi-directional I/O ports with optional internal pull-ups. Figure 14-2 below
shows a functional description of one I/O-port pin, here generically called Pxn.
Figure 14-2. General Digital I/O(1)

DPDS0/DPDS1

DPDS0/DPDS1:

Note:

drive strength register

1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port.
clkI/O, SLEEP, and PUD are common to all ports.

14.2.1 Configuring the Port
Drive strength of output buffers is configurable port-wise. Source/sink capably of 2mA,
4mA, 6mA or 8mA is selectable through registers DPDS1 and DPDS0. Note that pins
PG3 and PG4 of PORTG have fixed drive strength of 2mA to enable the operation of
the low power crystal oscillator.
14.2.2 Configuring the Pin
Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. The DDxn bits
are accessed at the DDRx I/O address, the PORTxn bits at the PORTx I/O address,
and the PINxn bits at the PINx I/O address.
The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written
logic one, Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is
configured as an input pin.
If PORTxn is written logic one when the pin is configured as an input pin, the pull-up
resistor is activated. To switch the pull-up resistor off, PORTxn has to be written logic
zero or the pin has to be configured as an output pin. The port pins are tri-stated whenreset condition becomes active, even if no clocks are running.
If PORTxn is written logic one when the pin is configured as an output pin, the port pin
is driven high (one). If PORTxn is written logic zero when the pin is configured as an
output pin, the port pin is driven low (zero).
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14.2.3 Toggling the Pin
Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of
DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port.
14.2.4 Switching Between Input and Output
When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn,
PORTxn} = 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} =0b01) or output low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up
enabled state is fully acceptable, as a high-impedant environment will not notice thedifference between a strong high driver and a pull-up. If this is not the case, the PUD bit
in the MCUCR Register can be set to disable all pull-ups in all ports.
Switching between input with pull-up and output low generates the same problem. The
user must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state({DDxn, PORTxn} = 0b11) as an intermediate step.
The following table summarizes the control signals for the pin value.

DDxn

PORTxnPUD(in MCUCR)

Table 14-1. Port Pin Configurations

I/O

0

0

X

Input

No

Tri-state (Hi-Z)

0

1

0

Input

Yes

Pxn will source current if ext. pulled low.

0

1

1

Input

No

Tri-state (Hi-Z)

1

0

X

OutputNo

Output Low (Sink)

1

1

X

OutputNo

Output High (Source)

Pull-upComment

14.2.5 Reading the Pin Value
Independent of the setting of Data Direction bit DDxn, the port pin can be read throughthe PINxn Register bit. As shown in Figure 14-2 on page 187, the PINxn Register bit
and the preceding latch constitute a synchronizer. This is needed to avoid meta-stability
if the physical pin changes value near the edge of the internal clock, but it also
introduces a delay. Figure 14-3 on page 189 shows a timing diagram of thesynchronization when reading an externally applied pin value. The maximum andminimum propagation delays are denoted tPD,MAX and tPD,MIN respectively.

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Figure 14-3. Synchronization when reading an external applied pin value

Consider the clock period starting shortly after the first falling edge of the system clock.
The latch is closed when the clock is low, and goes transparent when the clock is high,as indicated by the shaded region of the “SYNC LATCH” signal. The signal value islatched when the system clock goes low. It is clocked into the PINxn Register at thesucceeding positive clock edge. As indicated by the two arrows tPD,MAX and tPD,MIN, asingle signal transition on the pin will be delayed between ½ and 1½ system clock
period depending upon the time of assertion.
When reading back a software assigned pin value, a NOP instruction must be inserted
as indicated in Figure 14-4 below. The out instruction sets the “SYNC LATCH” signal at
the positive edge of the clock. In this case, the delay tPD through the synchronizer is 1
system clock period.
Figure 14-4. Synchronization when reading software assigned pin value

The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low,and define the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7.
The resulting pin values are read back again, but as previously discussed, a NOP
instruction is included to be able to read back the value recently assigned to some ofthe pins.

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Assembly Code Example(1)…
; Define pull-ups and set outputs high; Define directions for port pins
ldi r16,(1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0)
ldi r17,(1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0)
out PORTB,r16
out DDRB,r17; Insert nop for synchronizationnop; Read port pins
in r16,PINB…
C Code Example
unsigned char i;…
/* Define pull-ups and set outputs high *//* Define directions for port pins */PORTB = (1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0);DDRB = (1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0);/* Insert nop for synchronization*/__no_operation();/* Read port pins */i = PINB;…

Note:

1. For the assembly program, two temporary registers are used to minimize the timefrom pull-ups are set on pins 0, 1, 6, and 7, until the direction bits are correctly set,
defining bit 2 and 3 as low and redefining bits 0 and 1 as strong high drivers.

14.2.6 Digital Input Enable and Sleep Modes
As shown in Figure 14-2 on page 187, the digital input signal can be clamped to groundat the input of the Schmitt-Trigger. The signal denoted SLEEP in the figure, is set by the
MCU Sleep Controller in Power-down mode, Power-save mode, and Standby mode to
avoid high power consumption if some input signals are left floating, or have an analog
signal level close to VDEVDD/2.
SLEEP is overridden for port pins enabled as external interrupt pins. If the externalinterrupt request is not enabled, SLEEP is active also for these pins. SLEEP is also
overridden by various other alternate functions as described in "Alternate Port
Functions" on page 191.
If a logic high level (“one”) is present on an asynchronous external interrupt pin
configured as “Interrupt on Rising Edge, Falling Edge, or Any Logic Change on Pin”
while the external interrupt is not enabled, the corresponding External Interrupt Flag will
be set when resuming from the above mentioned Sleep mode, as the clamping in thesesleep mode produces the requested logic change.
14.2.7 Unconnected Pins
If some pins are unused, it is recommended to ensure that these pins have a definedlevel. Even though most of the digital inputs are disabled in the deep sleep modes as
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ATmega128RFA1
described above, floating inputs should be avoided to reduce current consumption in allother modes where the digital inputs are enabled (Reset-, Active- and Idle-mode).
The simplest method to ensure a defined level of an unused pin is to enable the internal
pull-up. In this case, the pull-up will be disabled during reset. If low power consumption
during reset is important, it is recommended to use an external pull-up or pull-down.
Connecting unused pins directly to DEVDD or DVSS is not recommended, since thismay cause excessive currents if the pin is accidentally configured as an output.

14.3 Alternate Port Functions
Most port pins have alternate functions in addition to being general digital I/O ports.
Figure 14-5 below shows how the port pin control signals from the simplified Figure14-2 on page 187 can be overridden by alternate functions. The overriding signals may
not be present in all port pins, but the figure serves as a generic description applicable
to all port pins in the AVR microcontroller family.
Figure 14-5. Alternate Port Functions

(1)

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Note:

1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port.
clkI/O, SLEEP, and PUD are common to all ports. All other signals are unique foreach pin.

The following table summarizes the function of the overriding signals. The pin and port
indexes from Figure 14-5 on page 191 are not shown in the succeeding tables. The
overriding signals are generated internally in the modules having the alternate function.
Table 14-2. Generic Description of Overriding Signals for Alternate Functions
Signal Name

Full Name

Description

PUOE

Pull-up Override
EnableIf this signal is set, the pull-up enable is controlled by
the PUOV signal. If this signal is cleared, the pull-up isenabled when {DDxn, PORTxn, PUD} = 0b010.

PUOV

Pull-up Override
Value

If PUOE is set, the pull-up is enabled/disabled when
PUOV is set/cleared, regardless of the setting of theDDxn, PORTxn, and PUD Register bits.

DDOE

Data Direction
Override Enable

If this signal is set, the Output Driver Enable iscontrolled by the DDOV signal. If this signal is cleared,
the Output driver is enabled by the DDxn Register bit.

DDOV

Data Direction
Override Value

If DDOE is set, the Output Driver is enabled/disabled
when DDOV is set/cleared, regardless of the setting of
the DDxn Register bit.

PVOEPort Value Override
EnableIf this signal is set and the Output Driver is enabled, theport value is controlled by the PVOV signal. If PVOE iscleared, and the Output Driver is enabled, the port
Value is controlled by the PORTxn Register bit.

PVOVPort Value Override
Value

If PVOE is set, the port value is set to PVOV,
regardless of the setting of the PORTxn Register bit.

PTOE

Port Toggle Override
EnableIf PTOE is set, the PORTxn Register bit is inverted.

DIEOE

Digital Input Enable
Override Enable

If this bit is set, the Digital Input Enable is controlled by
the DIEOV signal. If this signal is cleared, the Digital
Input Enable is determined by MCU state (Normalmode, sleep mode).

DIEOV

Digital Input Enable
Override ValueIf DIEOE is set, the Digital Input is enabled/disabled
when DIEOV is set/cleared, regardless of the MCU
state (Normal mode, sleep mode).

DI

Digital Input

This is the Digital Input to alternate functions. In the
figure, the signal is connected to the output of theSchmitt-Trigger but before the synchronizer. Unless the
Digital Input is used as a clock source, the module withthe alternate function will use its own synchronizer.

AIO

Analog Input/Output

This is the Analog Input/output to/from alternate
functions. The signal is connected directly to the pad,and can be used bi-directionally.

The following subsections shortly describe the alternate functions for each port, andrelate the overriding signals to the alternate function. Refer to the alternate function
description for further details.
14.3.1 Alternate Functions of Port B
The Port B pins with alternate functions are shown in the following table.

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Table 14-3. Port B Pins Alternate Functions
Port Pin

Alternate Functions

PB7

OC0A/OC1C/PCINT7 (Output Compare and PWM Output A for
Timer/Counter0, Output Compare and PWM Output C for Timer/Counter1 or
Pin Change Interrupt 7)

PB6

OC1B/PCINT6 (Output Compare and PWM Output B for Timer/Counter1 or
Pin Change Interrupt 6)

PB5

OC1A/PCINT5 (Output Compare and PWM Output A for Timer/Counter1 or
Pin Change Interrupt 5)

PB4

OC2A/PCINT4 (Output Compare and PWM Output A for Timer/Counter2 or
Pin Change Interrupt 4)

PB3

MISO/PDO/PCINT3 (SPI Bus Master Input/Slave Output, Programming Data
Output or Pin Change Interrupt 3)

PB2

MOSI/PDI/PCINT2 (SPI Bus Master Output/Slave Input , Programming Data
Input or Pin Change Interrupt 2)

PB1

SCK/PCINT1 (SPI Bus Serial Clock or Pin Change Interrupt 1)

PB0

SS¯ ¯ /PCINT0 (SPI Slave Select input or Pin Change Interrupt 0)

The alternate pin configuration is as follows:• OC0A/OC1C/PCINT7, Bit 7
OC0A, Output Compare Match A output: The PB7 pin can serve as an external output
for the Timer/Counter0 Output Compare. The pin has to be configured as an output(DDB7 set “one”) to serve this function. The OC0A pin is also the output pin for thePWM mode timer function.
OC1C, Output Compare Match C output: The PB7 pin can serve as an external output
for the Timer/Counter1 Output Compare C. The pin has to be configured as an output(DDB7 set (one)) to serve this function. The OC1C pin is also the output pin for thePWM mode timer function.
PCINT7, Pin Change Interrupt source 7: The PB7 pin can serve as an external interrupt
source.
• OC1B/PCINT6, Bit 6
OC1B, Output Compare Match B output: The PB6 pin can serve as an external output
for the Timer/Counter1 Output Compare B. The pin has to be configured as an output(DDB6 set (one)) to serve this function. The OC1B pin is also the output pin for thePWM mode timer function.
PCINT6, Pin Change Interrupt source 6: The PB6 pin can serve as an external interrupt
sourceOC1A, Output Compare Match A output: The PB5 pin can serve as an external
output for the Timer/Counter1 Output Compare A. The pin has to be configured as an
output (DDB5 set (one)) to serve this function. The OC1A pin is also the output pin for
the PWM mode timer function.
PCINT5, Pin Change Interrupt source 5: The PB5 pin can serve as an external interrupt
source.
• OC2A/PCINT4, Bit 4
OC2A, Output Compare Match output: The PB4 pin can serve as an external output for
the Timer/Counter2 Output Compare. The pin has to be configured as an output (DDB4
set (one)) to serve this function. The OC2A pin is also the output pin for the PWM mode
timer function.

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PCINT4, Pin Change Interrupt source 4: The PB4 pin can serve as an external interrupt
source.
• MISO/PDO/PCINT3 – Port B, Bit 3
MISO: Master Data input, Slave Data output pin for SPI channel. When the SPI isenabled as a master, this pin is configured as an input regardless of the setting of
DDB3. When the SPI is enabled as a slave, the data direction of this pin is controlled by
DDB3. When the pin is forced to be an input, the pull-up can still be controlled by the
PORTB3 bit.
PDO, SPI Serial Programming Data Output. During Serial Program Downloading, thispin is used as data output line (see section "Serial Downloading" on page 477 fordetails).
PCINT3, Pin Change Interrupt source 3: The PB3 pin can serve as an external interrupt
source.
• MOSI/PDI/PCINT2 – Port B, Bit 2
MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI isenabled as a slave, this pin is configured as an input regardless of the setting of DDB2.
When the SPI is enabled as a master, the data direction of this pin is controlled by
DDB2. When the pin is forced to be an input, the pull-up can still be controlled by the
PORTB2 bit.
PDI, SPI Serial Programming Data Input. During Serial Program Downloading, this pin
is used as data input line (see section "Serial Downloading" on page 477 for details).
PCINT2, Pin Change Interrupt source 2: The PB2 pin can serve as an external interrupt
source.
• SCK/PCINT1 – Port B, Bit 1
SCK: Master Clock output, Slave Clock input pin for SPI channel. When the SPI isenabled as a slave, this pin is configured as an input regardless of the setting of DDB1.
When the SPI0 is enabled as a master, the data direction of this pin is controlled by
DDB1. When the pin is forced to be an input, the pull-up can still be controlled by the
PORTB1 bit.
PCINT1, Pin Change Interrupt source 1: The PB1 pin can serve as an external interrupt
source.
• SS¯ ¯ /PCINT0 – Port B, Bit 0SS¯ ¯ : Slave Port Select input. When the SPI is enabled as a slave, this pin is configured
as an input regardless of the setting of DDB0. As a slave, the SPI is activated when thispin is driven low. When the SPI is enabled as a master, the data direction of this pin iscontrolled by DDB0. When the pin is forced to be an input, the pull-up can still becontrolled by the PORTB0 bit.
Table 14-4 below and Table 14-5 on page 195 relate the alternate functions of Port B to
the overriding signals shown in Figure 14-5 on page 191. SPI MSTR INPUT and SPISLAVE OUTPUT constitute the MISO signal, while MOSI is divided into SPI MSTROUTPUT and SPI SLAVE INPUT.
PCINT0, Pin Change Interrupt source 0: The PB0 pin can serve as an external interrupt
source.
Table 14-4. Overriding Signals for Alternate Functions in PB7:PB4

194

SignalName

PB7/OC0A/OC1C

PB6/OC1B

PB5/OC1APB4/OC2A

PUOE

0

0

0

0

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ATmega128RFA1
SignalName

PB7/OC0A/OC1C

PB6/OC1B

PB5/OC1APB4/OC2A

PUOV

0

0

0

0

DDOE

0

0

0

0

DDOV

0

0

0

0

PVOE

OC0/OC1CENABLE

OC1B ENABLE

OC1A ENABLE

OC2A ENABLE

PVOV

OC0/OC1C

OC1B

OC1A

OC2A

DIEOE

PCINT7•PCIE0PCINT6•PCIE0PCINT5•PCIE0PCINT4•PCIE0

DIEOV

1

1

1

1

DI

PCINT7 INPUT

PCINT6 INPUT

PCINT5 INPUT

PCINT4 INPUT

AIO

–

–

–

–

Table 14-5. Overriding Signals for Alternate Functions in PB3:PB0
SignalName

PB3/MISO/PDO

PB2/MOSI/PDI

PB1/SCKPB0/SS¯¯

PUOESPE•MSTR

SPE•(~MSTR)

SPE•(~MSTR)

SPE•(~MSTR)PUOVPORTB3•(~PUD)

PORTB2•(~PUD)

PORTB1•(~PUD)

PORTB0•(~PUD)

DDOE

SPE•MSTR

SPE•(~MSTR)

SPE•(~MSTR)

SPE•(~MSTR)

DDOV

0

0

0

0

PVOE

SPE•(~MSTR)

SPE•MSTR

SPE•MSTR0PVOVSPI SLAVEOUTPUT

SPI MSTROUTPUTSCK OUTPUT

0

DIEOE

PCINT3•PCIE0PCINT2•PCIE0PCINT1•PCIE0PCINT0•PCIE0

DIEOV

1

1

1

1

DI

SPI MSTR INPUT
PCINT3 INPUTSPI SLAVE INPUT
PCINT2 INPUTSCK INPUTPCINT1 INPUTSPI SS¯ ¯ PCINT0
INPUT

AIO

–

–

–

–

14.3.2 Alternate Functions of Port D
The Port D pins with alternate functions are shown in the following table.
Table 14-6. Port D Pins Alternate Functions
Port Pin

Alternate Function

PD7

T0 (Timer/Counter0 Clock Input)

PD6

T1 (Timer/Counter1 Clock Input)

PD5

XCK1 (USART1 External Clock Input/Output)

PD4

ICP1 (Timer/Counter1Input Capture Trigger)

PD3

INT3/TXD1 (External Interrupt3 Input or USART1 Transmit Pin)

PD2

INT2/RXD 1(External Interrupt2 Input or USART1 Receive Pin)

PD1

INT1/SDA (External Interrupt1 Input or TWI Serial Data)

PD0

INT0/SCL (External Interrupt0 Input or TWI Serial Clock)

The alternate pin configuration is as follows:• T0 – Port D, Bit 7
T0, this is Timer/Counter0 counter source.
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• T1 – Port D, Bit 6
T1, this is Timer/Counter1 counter source.
• XCK1 – Port D, Bit 5
XCK1, USART1 External clock: The Data Direction Register (DDD5) controls whether
the clock is output (DDD5 set) or input (DDD5 cleared). The XCK1 pin is active only
when the USART1 operates in Synchronous mode.
• ICP1 – Port D, Bit 4
ICP1 – Input Capture Pin 1: The PD4 pin can act as an input capture pin forTimer/Counter1.
• INT3/TXD1 – Port D, Bit 3
INT3, External Interrupt source 3: The PD3 pin can serve as an external interrupt
source to the MCU.
TXD1, Transmit Data (Data output pin for the USART1). When the USART1 Transmitteris enabled, this pin is configured as an output regardless of the value of DDD3.
• INT2/RXD1 – Port D, Bit 2
INT2, External Interrupt source 2: The PD2 pin can serve as an External Interrupt
source to the MCU.
RXD1, Receive Data (Data input pin for the USART1). When the USART1 receiver isenabled this pin is configured as an input regardless of the value of DDD2. When the
USART forces this pin to be an input, the pull-up can still be controlled by the PORTD2
bit.
• INT1/SDA – Port D, Bit 1
INT1, External Interrupt source 1: The PD1 pin can serve as an external interrupt
source to the MCU.
SDA, 2-wire Serial Interface Data: When the TWEN bit in TWCR is set (one) to enable
the 2-wire Serial Interface, pin PD1 is disconnected from the port and becomes theSerial Data I/O pin for the 2-wire Serial Interface. In this mode, there is a spike filter on
the pin to suppress spikes shorter than 50 ns on the input signal, and the pin is driven
by an open drain driver with slew rate limitation.
• INT0/SCL – Port D, Bit 0
INT0, External Interrupt source 0: The PD0 pin can serve as an external interrupt
source to the MCU.
SCL, 2-wire Serial Interface Clock: When the TWEN bit in TWCR is set (one) to enable
the 2-wire Serial Interface, pin PD0 is disconnected from the port and becomes theSerial Clock I/O pin for the 2-wire Serial Interface. In this mode, there is a spike filter on
the pin to suppress spikes shorter than 50 ns on the input signal, and the pin is driven
by an open drain driver with slew-rate limitation.
Table 14-7 below and Table 14-8 on page 197 relates the alternate functions of Port D
to the overriding signals shown in Figure 14-5 on page 191.
Table 14-7. Overriding Signals for Alternate Functions PD7:PD4

196

SignalName

PD7/T0PD6/T1PD5/XCK1

PD4/ICP1

PUOE

0

0

0

0

PUOV

0

0

0

0

DDOE

0

0

XCK1 OUTPUTENABLE

0

ATmega128RFA1
8266A-MCU Wireless-12/09

ATmega128RFA1
SignalName

PD7/T0PD6/T1PD5/XCK1

PD4/ICP1

DDOV

0

0

1

0

PVOE

0

0

XCK1 OUTPUTENABLE

0

PVOV

0

0

XCK1 OUTPUT

0

DIEOE

0

0

0

0

DIEOV

0

0

0

0

DI

T0 INPUTT1 INPUTXCK1 INPUTICP1 INPUT

AIO

–

–

–

–

Table 14-8. Overriding Signals for Alternate Functions PD3:PD0
SignalName

PD3/INT3/TXD1

PD2/INT2/RXD1

PD1/INT1/SDA

PD0/INT0/SCL

PUOE

TXEN1

RXEN1

TWEN

TWEN

PUOV

0

PORTD2&(~PUD)

PORTD1&(~PUD)

PORTD0&(~PUD)

DDOE

TXEN1

RXEN1

TWEN

TWEN

DDOV

1

0

SDA_OUTSCL_OUT

PVOE

TXEN1

0

TWEN

TWEN

PVOV

TXD1

0

0

0

DIEOE

INT3 ENABLE

INT2 ENABLE

INT1 ENABLE

INT0 ENABLE

DIEOV

1

1

1

1

DI

INT3 INPUT

INT2 INPUT/RXD1

INT1 INPUT

INT0 INPUT

AIO

-

-

SDA INPUTSCL INPUT

Note:

1. When enabled, the 2-wire Serial Interface enables Slew-Rate controls on the
output pins PD0 and PD1. This is not shown in this table. In addition, spike filters
are connected between the AIO outputs shown in the port figure and the digital
logic of the TWI module.

14.3.3 Alternate Functions of Port E
The Port E pins with alternate functions are shown in the following table.
Table 14-9. Port E Pins Alternate Functions
Port
Pin

Alternate Function

PE7

INT7/ICP3/CLK0 (External Interrupt7 Input, Timer/Counter3 Input Capture Trigger or
Divided System Clock)PE6

INT6/T3 (External Interrupt6 Input or Timer/Counter3 Clock Input)

PE5

INT5/OC3C (External Interrupt5 Input or Output Compare and PWM Output C for
Timer/Counter3)

PE4

INT4/OC3B (External Interrupt4 Input or Output Compare and PWM Output B for
Timer/Counter3)

PE3

AIN1/OC3A (Analog Comparator Negative Input or Output Compare and PWM Output A
for Timer/Counter3)

PE2

AIN0/XCK0 (Analog Comparator or Positive Input or USART0 external clock input/output)

PE1

TXD0 (USART0 Transmit Pin)

197
8266A-MCU Wireless-12/09

Port
Pin

Alternate Function

PE0

RXD0/PCINT8 (USART0 Receive Pin or Pin Change Interrupt8)• INT7/ICP3/CLKO – Port E, Bit 7
INT7, External Interrupt source 7: The PE7 pin can serve as an external interrupt
source.
ICP3, Input Capture Pin 3: The PE7 pin can act as an input capture pin forTimer/Counter3.
CLKO - Divided System Clock: The divided system clock can be output on the PE7 pin.
The divided system clock will be output if the CKOUT Fuse is programmed, regardlessof the PORTE7 and DDE7 settings. It will also be output during reset.
• INT6/T3 – Port E, Bit 6
INT6, External Interrupt source 6: The PE6 pin can serve as an external interrupt
source.
T3, this is the Timer/Counter3 counter source.
• INT5/OC3C – Port E, Bit 5
INT5, External Interrupt source 5: The PE5 pin can serve as an External Interrupt
source.
OC3C, Output Compare Match C output: The PE5 pin can serve as an External output
for the Timer/Counter3 Output Compare C. The pin has to be configured as an output(DDE5 set “one”) to serve this function. The OC3C pin is also the output pin for thePWM mode timer function.
• INT4/OC3B – Port E, Bit 4
INT4, External Interrupt source 4: The PE4 pin can serve as an External Interrupt
source.
OC3B, Output Compare Match B output: The PE4 pin can serve as an External output
for the Timer/Counter3 Output Compare B. The pin has to be configured as an output(DDE4 set (one)) to serve this function. The OC3B pin is also the output pin for thePWM mode timer function.
• AIN1/OC3A – Port E, Bit 3
AIN1 – Analog Comparator Negative input. This pin is directly connected to thenegative input of the Analog Comparator.
OC3A, Output Compare Match A output: The PE3 pin can serve as an External output
for the Timer/Counter3 Output Compare A. The pin has to be configured as an output(DDE3 set “one”) to serve this function. The OC3A pin is also the output pin for thePWM mode timer function.
• AIN0/XCK0 – Port E, Bit 2
AIN0 – Analog Comparator Positive input. This pin is directly connected to the positive
input of the Analog Comparator.
XCK0, this is the USART0 External clock. The Data Direction Register (DDE2) controls
whether the clock is output (DDE2 set) or input (DDE2 cleared). The XCK0 pin is active
only when the USART0 operates in Synchronous mode.
• TXD0 – Port E, Bit 1
TXD0, this is the USART0 Transmit pin.
• RXD0/PCINT8 – Port E, Bit 0
198

ATmega128RFA1
8266A-MCU Wireless-12/09

ATmega128RFA1
RXD0, USART0 Receive Pin. Receive Data (Data input pin for the USART0). When the
USART0 receiver is enabled this pin is configured as an input regardless of the value of
DDRE0. When the USART0 forces this pin to be an input, a logical one in PORTE0 willturn on the internal pull-up.
PCINT8, Pin Change Interrupt source 8: The PE0 pin can serve as an external interrupt
source.
Table 14-10 below and Table 14-11 below relates the alternate functions of Port E tothe overriding signals shown in Figure 14-5 on page 191.
Table 14-10. Overriding Signals for Alternate Functions PE7:PE4
SignalName

PE7/INT7/ICP3

PE6/INT6/T3

PE5/INT5/OC3C

PE4/INT4/OC3B

PUOE

0

0

0

0

PUOV

0

0

0

0

DDOE

0

0

0

0

DDOV

0

0

0

0

PVOE

0

0

OC3C ENABLE

OC3B ENABLE

PVOV

0

0

OC3C

OC3B

DIEOE

INT7 ENABLE

INT6 ENABLE

INT5 ENABLE

INT4 ENABLE

DIEOV

1

1

1

1

DI

INT7 INPUT / ICP3
INPUT

INT7 INPUT / T3
INPUT

INT5 INPUT

INT4 INPUT

AIO

–

–

–

–

Table 14-11. Overriding Signals for Alternate Functions PE3:PE0
SignalName

PE3/AIN1/OC3A

PE2/AIN0/XCK0

PE1/TXD0

PE0 /RXD0/PCINT8

PUOE

0

0

TXEN0

RXEN0

PUOV

0

0

0

PORTE0 & (~PUD)

DDOE

0

XCK0 OUTPUTENABLE

TXEN0

RXEN0

DDOV

0

1

1

0

PVOE

OC3BENABLE

XCK0 OUTPUTENABLE

TXEN0

0

PVOV

OC3B

XCK0 OUTPUT

TXD0

0

DIEOE

0

0

0

PCINT8 & PCIE1

DIEOV

0

0

0

1

DI

0

XCK0 INPUT

–

RXD0

PE0

0

0

0

PCINT8 INPUTAIO

AIN1 INPUT

AIN0 INPUT--

14.3.4 Alternate Functions of Port F
The Port F has an alternate function as analog input for the ADC as shown in Table
14-12 on page 200. If some Port F pins are configured as outputs, it is essential thatthese do not switch when a conversion is in progress. This might corrupt the result of
the conversion. If the JTAG interface is enabled, the pull-up resistors on pins PF7(TDI),
PF5(TMS), and PF4(TCK) will be activated even if a Reset occurs.
199
8266A-MCU Wireless-12/09

Table 14-12. Port F Pins Alternate Functions
Port Pin

Alternate Function

PF7

ADC7/TDI (ADC input channel 7 or JTAG Test Data Input)

PF6

ADC6/TDO (ADC input channel 6 or JTAG Test Data Output)

PF5

ADC5/TMS (ADC input channel 5 or JTAG Test Mode Select)

PF4

ADC4/TCK (ADC input channel 4 or JTAG Test Clock)

PF3

ADC3/DIG4 (ADC input channel 3 or Radio Transceiver RX/TX Indicator
Output)PF2

ADC2/DIG2 (ADC input channel 2 or Radio Transceiver Antenna Diversity
Control Output)

PF1

ADC1 (ADC input channel 1)

PF0

ADC0 (ADC input channel 0)• TDI, ADC7 – Port F, Bit 7
ADC7, Analog to Digital Converter, Channel 7.
TDI, JTAG Test Data In: Serial input data to be shifted in to the Instruction Register orData Register (scan chains). When the JTAG interface is enabled, this pin can not be
used as an I/O pin.
• TDO, ADC6 – Port F, Bit 6
ADC6, Analog to Digital Converter, Channel 6.
TDO, JTAG Test Data Out: Serial output data from Instruction Register or Data
Register. When the JTAG interface is enabled, this pin can not be used as an I/O pin.
The TDO pin is tri-stated unless TAP states that shift out data are entered.
• TMS, ADC5 – Port F, Bit 5
ADC5, Analog to Digital Converter, Channel 5.
TMS, JTAG Test Mode Select: This pin is used for navigating through the TAPcontroller state machine. When the JTAG interface is enabled, this pin can not be used
as an I/O pin.
• TCK, ADC4 – Port F, Bit 4
ADC4, Analog to Digital Converter, Channel 4.
TCK, JTAG Test Clock: JTAG operation is synchronous to TCK. When the JTAG
interface is enabled, this pin can not be used as an I/O pin.
• DIG4, ADC3 – Port F, Bit 3
ADC3, Analog to Digital Converter, Channel 3.
DIG4, Radio Transceiver RX/TX Indicator Output: If the bit PA_EXT_EN in
TRX_CTRL_1 is set to one then the PF3 pin serves as the Radio Transceiverreceive/transmit indicator output to control an external RF front-end.
• DIG2, ADC2 – Port F, Bit 2
ADC2, Analog to Digital Converter, Channel 2.
DIG2, Radio Transceiver Antenna Diversity Control Output: If the bit
ANT_EXT_SW_EN in ANT_DIV is set to one then the PF2 pin serves as a Radio
Transceiver output to control External Antenna Diversity.
• ADC1 – ADC0 – Port F, Bit 1:0
Analog to Digital Converter, Channel 1:0.

200

ATmega128RFA1
8266A-MCU Wireless-12/09

ATmega128RFA1
Table 14-13. Overriding Signals for Alternate Functions PF7:PF4
SignalName

PF7/ADC7/TDI

PF6/ADC6/TDO

PF5/ADC5/TMS

PF4/ADC4/TCK

PUOE

JTAGEN

JTAGEN

JTAGEN

JTAGEN

PUOV

1

0

1

1

DDOE

JTAGEN

JTAGEN

JTAGEN

JTAGENDDOV

0SHIFT_IR+SHIFT_DR

0

0

PVOE

0

JTAGEN

0

0

PVOV

0

TDO

0

0

DIEOE

JTAGEN

JTAGEN

JTAGEN

JTAGEN

DIEOV

0

0

0

0

DI

–

–

–

–

AIO

TDI/ADC7 INPUT

ADC6 INPUTTMS/ADC5INPUT

TCK/ADC4 INPUT

Table 14-14. Overriding Signals for Alternate Functions PF3:PF0
SignalName

PF3/ADC3/DIG4

PF2/ADC2/DIG2

PF1/ADC1

PF0/ADC0

PUOE

0

0

0

0

PUOV

0

0

0

0

DDOE

PA_EXT_EN

ANT_EXT_SW_EN

0

0

DDOV

PA_EXT_EN

ANT_EXT_SW_EN

0

0

PVOE

PA_EXT_EN

ANT_EXT_SW_EN

0

0

PVOV

DIG4

DIG2

0

0

DIEOE

0

0

0

0

DIEOV

0

0

0

0

DI

–

–

–

–

AIO

ADC3 INPUT

ADC2 INPUT

ADC1 INPUT

ADC0 INPUT

14.3.5 Alternate Functions of Port G
The Port G alternate pin configuration is as follows:
Table 14-15. Port G Pins Alternate Functions
Port Pin

Alternate Function

PG5

OC0B (Output Compare and PWM Output B for Timer/Counter0)

PG4

TOSC1 (RTC Oscillator Timer/Counter2)

PG3

TOSC2 (RTC Oscillator Timer/Counter2)

PG2

AMR (Automated Meter Reading - Counter Input for Timer/Counter2)

PG1

DIG1 (Radio Transceiver Antenna Diversity Control Output)

PG0

DIG3 (Radio Transceiver RX/TX Indicator Output)• OC0B – Port G, Bit 5
OC0B, Output Compare match B output: The PG5 pin can serve as an external output
for the TImer/Counter0 Output Compare. The pin has to be configured as an output(DDG5 set) to serve this function. The OC0B pin is also the output pin for the PWM
mode timer function.
• TOSC1 – Port G, Bit 4
201
8266A-MCU Wireless-12/09

TOSC2, Timer Oscillator pin 1: Setting the AS2 bit to one and the EXCLKAMR bit tozero in ASSR, enables asynchronous clocking of Timer/Counter2 by a Crystal
Oscillator. The pin PG4 is disconnected from the port, and becomes the input of theinverting Oscillator amplifier. In this mode, a Crystal Oscillator is connected to this pin,and the pin can not be used as an I/O pin.
TOSC2 – Port G, Bit 3
TOSC2, Timer Oscillator pin 2: Setting the AS2 bit to one and the EXCLKAMR bit tozero in ASSR, enables asynchronous clocking of Timer/Counter2 by a Crystal
Oscillator. The pin PG3 is disconnected from the port, and becomes the inverting outputof the Oscillator amplifier. In this mode, a Crystal Oscillator is connected to this pin, andthe pin can not be used as an I/O pin.
• AMR – Port G, Bit 2
AMR, Automated Meter Reading Input: Setting the AS2 and the EXCLKAMR bits in
ASSR to one, enables asynchronous clocking of Timer/Counter2 by the AMR pin• DIG1 – Port G, Bit 1
DIG1, Radio Transceiver Antenna Diversity Control Output: If the bit
ANT_EXT_SW_EN in ANT_DIV is set to one then the PG1 pin serves as a Radio
Transceiver output to control External Antenna Diversity.
• DIG3 – Port G, Bit 0
DIG3, Radio Transceiver RX/TX Indicator Output: If the bit PA_EXT_EN in
TRX_CTRL_1 is set to one then the PG0 pin serves as the Radio Transceiverreceive/transmit indicator output to control an external RF front-end.
Table 14-16 below relates the alternate functions of Port G to the overriding signals
shown in Figure 14-5 on page 191.
Table 14-16. Overriding Signals for Alternate Functions PG5:PG2

202

SignalName

PG5/OC0B

PG4/TOSC1

PG3/TOSC2

PG2/AMR

PUOE

–

AS2 &
(~EXCLKAMR)

AS2 &(~EXCLKAMR) &(~EXCLK)

AS2 & EXCLKAMR

PUOV

–

0

0

0

DDOE

–

AS2 &
(~EXCLKAMR)

AS2 &(~EXCLKAMR) &(~EXCLK)

AS2 & EXCLKAMR

DDOV

–

0

0

0

PVOE

OC0B Enable

0

0

0

PVOV

OC0B

0

0

0

DIEOE

–

AS2 &
(~EXCLKAMR)

AS2 &(~EXCLKAMR) &(~EXCLK)

AS2 & EXCLKAMR

DIEOV

–

EXCLK

0

1

DI

–

–

–

AMR

AIO

–

T/C2
OSC INPUT

T/C2
OSC OUTPUT–

ATmega128RFA1
8266A-MCU Wireless-12/09

ATmega128RFA1
Table 14-17. Overriding Signals for Alternate Functions PG1:PG0
SignalName

PG1/DIG1

PG0/DIG3

PUOE

0

0

PUOV

0

0

DDOE

ANT_EXT_SW_EN

PA_EXT_EN

DDOV

ANT_EXT_SW_EN

PA_EXT_EN

PVOE

ANT_EXT_SW_EN

PA_EXT_EN

PVOV

DIG1

DIG3

DIEOE

0

0

DIEOV

0

0

DI

–

–

AIO

–

–

203
8266A-MCU Wireless-12/09

14.4 Register Description

14.4.1 MCUCR – MCU Control Register
Bit

7

6

5

4

$35 ($55)

PUD

Read/Write
Initial Value

RW
0

3

2

1

0

MCUCR

The MCU Control Register contains control bits of the general Microcontroller Unit
functions.
• Bit 4 – PUD - Pull-up Disable
When this bit is written to one, the I/O ports pull-up resistors are disabled even if the
DDxn and PORTxn Registers are configured to enable the pull-up resistor ({DDxn,
PORTxn} = 2'b01). See section "Ports as General Digital I/O" for more details about thisfeature.

14.4.2 DPDS0 – Port Driver Strength Register 0
Bit
NA ($136)

7

6

5

4

3

2

1

0

PFDRV1 PFDRV0 PEDRV1 PEDRV0 PDDRV1 PDDRV0 PBDRV1 PBDRV0

Read/Write
Initial Value

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

DPDS0

RW
0

The output driver strength can be set individually for each digital I/O port. The following
tables show output current levels for a typical supply voltage of DEVDD = 3.3V. Refer tosection "Electrical Characteristics" for details.
• Bit 7:6 – PFDRV1:0 - Driver Strength Port F
Table 14-18 PFDRV Register Bits
Register BitsPFDRV1:0

Value

Description

0

2 mA

1

4 mA

2

6 mA

3

8 mA

• Bit 5:4 – PEDRV1:0 - Driver Strength Port E
Table 14-19 PEDRV Register Bits
Register Bits

Value

Description

PEDRV1:0

0

2 mA

1

4 mA

2

6 mA

3

8 mA

• Bit 3:2 – PDDRV1:0 - Driver Strength Port D

204

ATmega128RFA1
8266A-MCU Wireless-12/09

ATmega128RFA1
Table 14-20 PDDRV Register Bits
Register Bits

Value

Description

PDDRV1:0

0

2 mA

1

4 mA

2

6 mA

3

8 mA

• Bit 1:0 – PBDRV1:0 - Driver Strength Port B
Table 14-21 PBDRV Register Bits
Register BitsValue

PBDRV1:00

2 mA

Description

1

4 mA

2

6 mA

3

8 mA

14.4.3 DPDS1 – Port Driver Strength Register 1
Bit

7

6

5

4

3

2

1

NA ($137)

Res5

Res4

Res3

Res2

Res1

Res0

Read/Write
Initial Value

R
0

R
0

R
0

R
0

R
0

R
0

0

PGDRV1 PGDRV0
RW
0

DPDS1

RW
0

The output driver strength can be set individually for each digital I/O port. The following
table shows output current levels for a typical supply voltage of DEVDD = 3.3V. Refer tosection "Electrical Characteristics" for details.
• Bit 7:2 – Res5:0 - Reserved• Bit 1:0 – PGDRV1:0 - Driver Strength Port G
Driver strength can be set for port G except the port pins PG3 and PG4. The leakage
current of the ports PG3 and PG4 is reduced.
Table 14-22 PGDRV Register Bits
Register Bits

Value

Description

PGDRV1:0

0

2 mA

1

4 mA

2

6 mA

3

8 mA

14.4.4 PORTB – Port B Data Register
Bit

7

6

5

$05 ($25)
Read/Write
Initial Value

4

3

2

1

0

PORTB7:0
RW
0

RW
0

RW
0

RW
0

RW
0

PORTB
RW
0

RW
0

RW
0

If PORTBn is written logic one when the PORTB pin n is configured as an input pin, thepull-up resistor is activated. To switch the pull-up resistor off, PORTBn has to be written

205
8266A-MCU Wireless-12/09

logic zero or the pin has to be configured as an output pin. If PORTBn is written logic
one when the pin is configured as an output pin, the port pin is driven high (one). If
PORTBn is written logic zero when the pin is configured as an output pin, the port pin isdriven low (zero).
• Bit 7:0 – PORTB7:0 - Port B Data Register Value

14.4.5 DDRB – Port B Data Direction Register
Bit

7

6

5

4

3

2

1

0

$04 ($24)

DDB7

DDB6

DDB5

DDB4

DDB3

DDB2

DDB1

DDB0

Read/Write
Initial Value

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

DDRB

The DDBn bit in the DDRB Register selects the direction of the PORTB pin n. If DDBnis written logic one, PBn is configured as an output pin. If DDBn is written logic zero,PBn is configured as an input pin.
• Bit 7:0 – DDB7:0 - Port B Data Direction Register Value

14.4.6 PINB – Port B Input Pins Address
Bit

7

6

5

$03 ($23)
Read/Write
Initial Value

4

3

2

1

0

PINB7:0
R
0

R
0

R
0

R
0

PINB

R
0

R
0

R
0

R
0

This register allows access to the PORTB pins independent of the setting of the Data
Direction bit DDBn. The port pin can be read through the PINBn Register bit, andwriting a logic one to PINBn toggles the value of PORTBn.
• Bit 7:0 – PINB7:0 - Port B Input Pins Value

14.4.7 PORTD – Port D Data Register
Bit

7

6

5

$0B ($2B)
Read/Write
Initial Value

4

3

2

1

0

PORTD7:0
RW
0

RW
0

RW
0

RW
0

RW
0

PORTD
RW
0

RW
0

RW
0

If PORTDn is written logic one when the PORTD pin n is configured as an input pin, thepull-up resistor is activated. To switch the pull-up resistor off, PORTDn has to be written
logic zero or the pin has to be configured as an output pin. If PORTDn is written logic
one when the pin is configured as an output pin, the port pin is driven high (one). If
PORTDn is written logic zero when the pin is configured as an output pin, the port pin isdriven low (zero).
• Bit 7:0 – PORTD7:0 - Port D Data Register Value

206

ATmega128RFA1
8266A-MCU Wireless-12/09

ATmega128RFA1
14.4.8 DDRD – Port D Data Direction Register
Bit

7

6

5

4

3

2

1

0

$0A ($2A)

DDD7

DDD6

DDD5

DDD4

DDD3

DDD2

DDD1

DDD0

Read/Write
Initial Value

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

DDRD

The DDDn bit in the DDRD Register selects the direction of the PORTD pin n. If DDDnis written logic one, PDn is configured as an output pin. If DDDn is written logic zero,PDn is configured as an input pin.
• Bit 7:0 – DDD7:0 - Port D Data Direction Register Value

14.4.9 PIND – Port D Input Pins Address
Bit

7

6

5

4

R
0

R
0

R
0

R
0

$09 ($29)
Read/Write
Initial Value

3

2

1

0

R
0

R
0

R
0

PIND7:0PIND

R
0This register allows access to the PORTD pins independent of the setting of the Data
Direction bit DDDn. The port pin can be read through the PINDn Register bit, andwriting a logic one to PINDn toggles the value of PORTDn.
• Bit 7:0 – PIND7:0 - Port D Input Pins Value

14.4.10 PORTE – Port E Data Register
Bit

7

6

5

4

$0E ($2E)
Read/Write
Initial Value

3

2

1

0

PORTE7:0
RW
0

RW
0

RW
0

RW
0

PORTE

RW
0

RW
0

RW
0

RW
0

If PORTEn is written logic one when the PORTE pin n is configured as an input pin, thepull-up resistor is activated. To switch the pull-up resistor off, PORTEn has to be written
logic zero or the pin has to be configured as an output pin. If PORTEn is written logic
one when the pin is configured as an output pin, the port pin is driven high (one). If
PORTEn is written logic zero when the pin is configured as an output pin, the port pin isdriven low (zero).
• Bit 7:0 – PORTE7:0 - Port E Data Register Value

14.4.11 DDRE – Port E Data Direction Register
Bit

7

6

5

4

3

2

1

0

$0D ($2D)

DDE7

DDE6

DDE5

DDE4

DDE3

DDE2

DDE1

DDE0

Read/Write
Initial Value

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

DDRE

207
8266A-MCU Wireless-12/09

The DDEn bit in the DDRE Register selects the direction of the PORTE pin n. If DDEn
is written logic one, PEn is configured as an output pin. If DDEn is written logic zero,PEn is configured as an input pin.
• Bit 7:0 – DDE7:0 - Port E Data Direction Register Value

14.4.12 PINE – Port E Input Pins Address
Bit

7

6

5

4

R
0

R
0

R
0

R
0

$0C ($2C)
Read/Write
Initial Value

3

2

1

0

R
0

R
0

R
0

PINE7:0PINE

R
0This register allows access to the PORTE pins independent of the setting of the Data
Direction bit DDEn. The port pin can be read through the PINEn Register bit, andwriting a logic one to PINEn toggles the value of PORTEn.
• Bit 7:0 – PINE7:0 - Port E Input Pins Value

14.4.13 PORTF – Port F Data Register
Bit

7

6

5

4

$11 ($31)
Read/Write
Initial Value

3

2

1

0

PORTF7:0
RW
0

RW
0

RW
0

RW
0

PORTF

RW
0

RW
0

RW
0

RW
0

If PORTFn is written logic one when the PORTF pin n is configured as an input pin, thepull-up resistor is activated. To switch the pull-up resistor off, PORTFn has to be written
logic zero or the pin has to be configured as an output pin. If PORTFn is written logic
one when the pin is configured as an output pin, the port pin is driven high (one). If
PORTFn is written logic zero when the pin is configured as an output pin, the port pin isdriven low (zero).
• Bit 7:0 – PORTF7:0 - Port F Data Register Value

14.4.14 DDRF – Port F Data Direction Register
Bit

7

6

5

4

3

2

1

0

$10 ($30)

DDF7

DDF6

DDF5

DDF4

DDF3

DDF2

DDF1

DDF0

Read/Write
Initial Value

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

DDRF

The DDFn bit in the DDRF Register selects the direction of the PORTF pin n. If DDFn iswritten logic one, PFn is configured as an output pin. If DDFn is written logic zero, PFn
is configured as an input pin.
• Bit 7:0 – DDF7:0 - Port F Data Direction Register Value

208

ATmega128RFA1
8266A-MCU Wireless-12/09

ATmega128RFA1
14.4.15 PINF – Port F Input Pins Address
Bit

7

6

5

4

$0F ($2F)
Read/Write
Initial Value

3

2

1

0

PINF7:0
R
0

R
0

R
0

R
0

PINF

R
0

R
0

R
0

R
0

This register allows access to the PORTF pins independent of the setting of the Data
Direction bit DDFn. The port pin can be read through the PINFn Register bit, and writing
a logic one to PINFn toggles the value of PORTFn.
• Bit 7:0 – PINF7:0 - Port F Input Pins Value

14.4.16 PORTG – Port G Data Register
Bit

7

6

$14 ($34)

Res1

Res0

Read/Write
Initial Value

R
0

R
0

5

4

3

2

1

0

PORTG5 PORTG4 PORTG3 PORTG2 PORTG1 PORTG0
RW
0

RW
0

RW
0

RW
0

RW
0

PORTG

RW
0

If PORTGn is written logic one when the PORTG pin n is configured as an input pin, thepull-up resistor is activated. To switch the pull-up resistor off, PORTGn has to be written
logic zero or the pin has to be configured as an output pin. If PORTGn is written logic
one when the pin is configured as an output pin, the port pin is driven high (one). If
PORTGn is written logic zero when the pin is configured as an output pin, the port pin isdriven low (zero).
• Bit 7:6 – Res1:0 - Reserved Bit
This bit is reserved for future use. A read access always will return zero. A write accessdoes not modify the content.
• Bit 5:0 – PORTG5:0 - Port G Data Register Value

14.4.17 DDRG – Port G Data Direction Register
Bit

7

6

5

4

3

2

1

0

$13 ($33)

Res1

Res0

DDG5

DDG4

DDG3

DDG2

DDG1

DDG0

Read/Write
Initial Value

R
0

R
0

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

DDRG

The DDGn bit in the DDRG Register selects the direction of the PORTG pin n. If DDGnis written logic one, PGn is configured as an output pin. If DDGn is written logic zero,PGn is configured as an input pin.
• Bit 7:6 – Res1:0 - Reserved Bit
This bit is reserved for future use. A read access always will return zero. A write accessdoes not modify the content.
• Bit 5:0 – DDG5:0 - Port G Data Direction Register Value

209
8266A-MCU Wireless-12/09

14.4.18 PING – Port G Input Pins Address
Bit

7

6

5

4

3

2

1

0

$12 ($32)

Res1

Res0

PING5

PING4

PING3

PING2

PING1

PING0

Read/Write
Initial Value

R
0

R
0

R
0

R
0

R
0

R
0

R
0

R
0

PING

This register allows access to the PORTG pins independent of the setting of the Data
Direction bit DDGn. The port pin can be read through the PINGn Register bit, andwriting a logic one to PINGn toggles the value of PORTGn.
• Bit 7:6 – Res1:0 - Reserved Bit
This bit is reserved for future use. A read access always will return zero. A write accessdoes not modify the content.
• Bit 5:0 – PING5:0 - Port G Input Pins Value

210

ATmega128RFA1
8266A-MCU Wireless-12/09

ATmega128RFA1
15 Interrupts
This section describes the specifics of the interrupt handling as performed in
ATmega128RFA1. For a general explanation of the AVR interrupt handling, refer to"Reset and Interrupt Handling" on page 15.

15.1 Interrupt Vectors in ATmega128RFA1
Table 15-1. Reset and Interrupt Vectors
VectorNo.

ProgramAddress(2)Source0$0000(1)

RESET

1

$0002

INT0

External Interrupt Request 0

2

$0004

INT1

External Interrupt Request 1

3

$0006

INT2

External Interrupt Request 2

4

$0008

INT3

External Interrupt Request 3

5

$000A

INT4

External Interrupt Request 4

6

$000C

INT5

External Interrupt Request 5

7

$000E

INT6

External Interrupt Request 6

8

$0010

INT7

External Interrupt Request 7

9

$0012

PCINT0Pin Change Interrupt Request 0

10

$0014

PCINT1

Pin Change Interrupt Request 1

11$0016(3)PCINT2

Pin Change Interrupt Request 2

12

$0018

WDT

Watchdog Time-out Interrupt

13

$001A

TIMER2_COMPA

Timer/Counter2 Compare Match A

14

$001C

TIMER2_COMPB

Timer/Counter2 Compare Match B

15

$001E

TIMER2_OVF

Timer/Counter2 Overflow

16

$0020

TIMER1_CAPT

Timer/Counter1 Capture Event

17

$0022

TIMER1_COMPA

Timer/Counter1 Compare Match A

18

$0024

TIMER1_COMPB

Timer/Counter1 Compare Match B

19

$0026

TIMER1_COMPC

Timer/Counter1 Compare Match C

20

$0028

TIMER1_OVF

Timer/Counter1 Overflow

21

$002A

TIMER0_COMPA

Timer/Counter0 Compare Match A

22

$002C

TIMER0_COMPB

Timer/Counter0 Compare match B

23

$002E

TIMER0_OVF

Timer/Counter0 Overflow

24

$0030

SPI_STC

SPI Serial Transfer Complete

25

$0032

USART0_RX

USART0 Rx Complete

26

$0034

USART0_UDRE

USART0 Data Register Empty

27

$0036

USART0_TX

USART0 Tx Complete

28

$0038

ANALOG_COMP

Analog Comparator

Interrupt Definition
External Pin, Power-on Reset, Brown-out
Reset, Watchdog Reset, and JTAG AVR
Reset

211
8266A-MCU Wireless-12/09

212

VectorNo.

ProgramAddress(2)SourceInterrupt Definition

29

$003A

ADC

ADC Conversion Complete

30

$003C

EE_READYEEPROM Ready

31

$003E

TIMER3_CAPT

Timer/Counter3 Capture Event

32

$0040

TIMER3_COMPA

Timer/Counter3 Compare Match A

33

$0042

TIMER3_COMPB

Timer/Counter3 Compare Match B

34

$0044

TIMER3_COMPC

Timer/Counter3 Compare Match C

35

$0046

TIMER3_OVF

Timer/Counter3 Overflow

36

$0048

USART1_RX

USART1 Rx Complete

37

$004A

USART1_UDRE

USART1 Data Register Empty

38

$004C

USART1_TX

USART1 Tx Complete

39

$004E

TWI

2-wire Serial Interface

40

$0050

SPM_READYStore Program Memory Ready41$0052(3)

TIMER4_CAPT

Timer/Counter4 Capture Event

42

$0054

TIMER4_COMPA

Timer/Counter4 Compare Match A

43

$0056

TIMER4_COMPB

Timer/Counter4 Compare Match B

44

$0058

TIMER4_COMPC

Timer/Counter4 Compare Match C

45

$005A

TIMER4_OVF

Timer/Counter4 Overflow

46$005C(3)

TIMER5_CAPT

Timer/Counter5 Capture Event

47

$005E

TIMER5_COMPA

Timer/Counter5 Compare Match A

48

$0060

TIMER5_COMPB

Timer/Counter5 Compare Match B

49

$0062

TIMER5_COMPC

Timer/Counter5 Compare Match C

50

$0064

TIMER5_OVF

Timer/Counter5 Overflow

51$0066(3)Reserved

52$0068(3)Reserved

53$006A(3)Reserved

54$006C(3)Reserved

55$006E(3))

Reserved

56$0070(3)Reserved

57

$0072

TRX24_PLL_LOCKTransceiver PLL Lock

58

$0074

TRX24_PLL_UNLOCK

Transceiver PLL Unlock

59

$0076

TRX24_RX_START

Transceiver Receive Start

60

$0078

TRX24_RX_END

Transceiver Receive End

61

$007A

TRX24_CCA_ED_DONE

Transceiver CCAED Meassurement finished

62

$007C

TRX24_XAH_AMI

Transceiver Frame Address Match

63

$007E

TRX24_TX_END

Transceiver Transmit End

64

$0080

TRX24_AWAKE

Transceiver Wakeup finished

ATmega128RFA1
8266A-MCU Wireless-12/09

ATmega128RFA1
VectorNo.

ProgramAddress(2)SourceInterrupt Definition

65

$0082

SCNT_CMP1

Symbol Counter Compare Match 1

66

$0084

SCNT_CMP 2

Symbol Counter Compare Match 2

67

$0086

SCNT_CMP 3

Symbol Counter Compare Match 3

68

$0088

SCNT_OVFL

Symbol Counter Overflow

69

$008A

SCNT_BACKOFF

Symbol Counter Backoff Slot Counter

70

$008C

AES_READYAES Encryption Ready

71

$008E

BAT_LOW

Batterie Monitor Allert

Note:

1. When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader
address at reset, see "Memory Programming" on page 464.
2. When the IVSEL bit in MCUCR is set, Interrupt Vectors will be moved to the startof the Boot Flash Section. The address of each Interrupt Vector will then be theaddress in this table added to the start address of the Boot Flash Section.
3. Not usefull in ATmega128RFA1 due to limited pin count.

15.2 Reset and Interrupt Vector Placement
Table 15-2 below shows Reset and Interrupt Vectors placement for the various
combinations of BOOTRST and IVSEL settings. If the program never enables aninterrupt source, the Interrupt Vectors are not used, and regular program code can beplaced at these locations. This is also the case if the Reset Vector is in the Application
section while the Interrupt Vectors are in the Boot section or vice versa.
Table 15-2. Reset and Interrupt Vectors Placement(1)

BOOTRST

IVSEL

Reset Address

Interrupt Vectors Start Address

100x00000x00021

10x0000

Boot Reset Address + 0x0002

00Boot Reset Address

0x0002

0

1

Boot Reset Address

Boot Reset Address + 0x0002

Note:

1. The Boot Reset Address is shown in Table 30-7 on page 461 through Table 30-6
on page 461. For the BOOTRST Fuse “1” means unprogrammed while “0” means
programmed.

The most typical and general program setup for the Reset and Interrupt Vector
Addresses in ATmega128RFA1 is:Address
0x00000x00020x00040x00060x00080x000A
0x000C
0x000E0x00100x00120x00140x0016

Labels

Code
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp

RESET
INT0
INT1
INT2
INT3
INT4
INT5
INT6
INT7
PCINT0PCINT1
PCINT2

Comments;Reset Handler;IRQ0 Handler;IRQ1 Handler;IRQ2 Handler;IRQ3 Handler;IRQ4 Handler;IRQ5 Handler;IRQ6 Handler;IRQ7 Handler;PCINT0 Handler;PCINT1 Handler;PCINT2 Handler

213
8266A-MCU Wireless-12/09

0X00180x001A
0x001C0x001E
0x00200x00220x00240x00260x00280x002A
0x002C
0x002E0x00300x00320x00340x00360x00380x003A
0x003C
0x003E0x00400x00420x00440x00460x00480x004A
0x004C0x004E
0x00500x00520x00540x00560x00580x005A
0x005C
0x005E0x00600x00620x00640x00660x00680x006A
0x006C
0x006E
0x00700x00720x00740x00760x00780x007A
0x007C
0x007E0x00800x00820x00840x00860x00880x008A

214

jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp

WDT
TIM2_COMPA
TIM2_COMPB
TIM2_OVF
TIM1_CAPT
TIM1_COMPA
TIM1_COMPB
TIM1_COMPC
TIM1_OVF
TIM0_COMPA
TIM0_COMPB
TIM0_OVFSPI_STC
USART0_RX
USART0_UDRE
USART0_TX
ANA_COMPADC
EE_RDY
TIM3_CAPT
TIM3_COMPA
TIM3_COMPB
TIM3_COMPC
TIM3_OVF
USART1_RX
USART1_UDRE
USART1_TX
TWI
SPM_RDY
TIM4_CAPT
TIM4_COMPA
TIM4_COMPB
TIM4_COMPC
TIM4_OVF
TIM5_CAPT
TIM5_COMPA
TIM5_COMPB
TIM5_COMPC
TIM5_OVF
0x15e
0x15e
0x15e
0x15e
0x15e
0x15e
TRX24_PLL_LOCKTRX24_PLL_UNLOCKTRX24_RX_START
TRX24_RX_END
TRX24_CCA_ED_DONE
TRX24_XAH_AMI
TRX24_TX_END
TRX24_AWAKESCNT_CMP1SCNT_CMP2
SCNT_CMP3
SCNT_OVFLSCNT_BACKOFF;Watchdog Timeout Handler;Timer2 CompareA Handler;Timer2 CompareB Handler;Timer2 Overflow Handler;Timer1 Capture Handler;Timer1 CompareA Handler;Timer1 CompareB Handler;Timer1 CompareC Handler;Timer1 Overflow Handler;Timer0 CompareA Handler;Timer0 CompareB Handler;Timer0 Overflow Handler;SPI Transfer Complete Handler;USART0 RX Complete Handler;USART0,UDR Empty Handler;USART0 TX Complete Handler;Analog Comparator Handler;ADC Conversion Complete Handler;EEPROM Ready Handler;Timer3 Capture Handler;Timer3 CompareA Handler;Timer3 CompareB Handler;Timer3 CompareC Handler;Timer3 Overflow Handler;USART1 RX Complete Handler;USART1,UDR Empty Handler;USART1 TX Complete Handler;2-wire Serial Handler;SPM Ready Handler;Timer4 Capture Handler;Timer4 CompareA Handler;Timer4 CompareB Handler;Timer4 CompareC Handler;Timer4 Overflow Handler;Timer5 Capture Handler;Timer5 CompareA Handler;Timer5 CompareB Handler;Timer5 CompareC Handler;Timer5 Overflow Handler;0x15e <__bad_interrupt>;0x15e <__bad_interrupt>;0x15e <__bad_interrupt>;0x15e <__bad_interrupt>;0x15e <__bad_interrupt>;0x15e <__bad_interrupt>;Transceiver PLL Lock Handler;Transceiver PLL Unlock Handler;Transceiver RX Start Handler;Transceiver RX End Handler;Transceiver CCAED DONE Handler;Transceiver Addr. Match Handler;Transceiver Transmit End Handler;Transceiver Wake Up Handler;Symbol Counter Compare Match 1;Symbol Counter Compare Match 2;Symbol Counter Compare Match 3;Symbol Counter Overflow Handler;Symbol Backoff Slot Counter H.

ATmega128RFA1
8266A-MCU Wireless-12/09

ATmega128RFA1
0x008C0x008E;0x00900x00910x00920x00930x00940x0095...

jmp
jmp
RESET:

...

ldi
out
ldi
out
sei
<instr>...

AES_READY
BAT_LOW;Encryption/Decryption Ready H.
;Batterie Monitor Alert Handler

r16, high(RAMEND)
SPH,r16
r16, low(RAMEND)
SPL,r16;Main program start;Set Stack Pointer to top of RAM;Enable interrupts
xxx...

When the BOOTRST Fuse is unprogrammed, the Boot section size set to 8KBytes andthe IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the mosttypical and general program setup for the Reset and Interrupt Vector Addresses is:
Address Labels

Code

Comments________________________

0x0000 RESET:
0x00010x00020x00030x00040x0005.org 0xF002
0xF0020xF004... ... ... ;0xFO70ldi r16,high(RAMEND)
out SPH,r16
ldi r16,low(RAMEND)
out SPL,r16
sei<instr> xxx;Main program start;Set Stack Pointer to top of RAM

jmp EXT_INT0
jmp EXT_INT1;IRQ0 Handler;IRQ1 Handler

jmp USART3_TXC;USART3 TX Complete Handler;Enable interrupts

When the BOOTRST Fuse is programmed and the Boot section size set to 8KBytes,
the most typical and general program setup for the Reset and Interrupt Vector
Addresses is:
Address Labels.org 0x0002
0x00020x0004... ... ... ;.org 0xF000
0xF000 RESET:
0xF001
0xF0020xF0030xF0040xF005

Code

Comments________________________

jmp EXT_INT0
jmp EXT_INT1;IRQ0 Handler;IRQ1 Handler

ldi r16,high(RAMEND)
out SPH,r16
ldi r16,low(RAMEND)
out SPL,r16
sei<instr> xxx;Main program start;Set Stack Pointer to top of RAM;Enable interrupts

When the BOOTRST Fuse is programmed, the Boot section size set to 8KBytes andthe IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the mosttypical and general program setup for the Reset and Interrupt Vector Addresses is:
Address Labels.org 0xF000
0xF000
0xF0020xF004... ... ... ;0xF072 RESET:

Code

Comments________________________

jmp RESET
jmp EXT_INT0
jmp EXT_INT1;Reset handler;IRQ0 Handler;IRQ1 Handler

ldi r16,high(RAMEND); Main program start

215
8266A-MCU Wireless-12/09

0xF073
0xF0740xF0750xF076
0xFO77out SPH,r16
ldi r16,low(RAMEND)
out SPL,r16
sei<instr> xxx;Set Stack Pointer to top of RAM;Enable interrupts

15.3 Moving Interrupts Between Application and Boot Section
The MCU Control Register controls the placement of the Interrupt Vector table, see
Code Example below. For more details, see "Reset and Interrupt Handling" on page 15.
Assembly Code Example
Move_interrupts:; Get MCUCR
in r16, MCUCR
mov r17, r16; Enable change of Interrupt Vectors
ori r16, (1<<IVCE)
out MCUCR, r16; Move interrupts to Boot Flash section
ori r16, (1<<IVSEL)
out MCUCR, r17
ret
C Code Example
void Move_interrupts(void){uchar temp;/* Get MCUCR */temp = MCUCR;/* Enable change of Interrupt Vectors */MCUCR = temp|(1<<IVCE);/* Move interrupts to Boot Flash section */MCUCR = temp|(1<<IVSEL);}

15.4 Register Description
15.4.1 MCUCR – MCU Control Register
Bit

7

6

5

4

3

2

1

0

$35 ($55)

JTD

Res1

Res0

PUD

Res1

Res0

IVSEL

IVCE

Read/Write
Initial Value

RW
0

R
0

R
0

RW
0

R
0

R
0

RW
0

RW
0

MCUCR

The MCU Control Register contains control bits for general Microcontroller Unit
functions.
• Bit 7 – JTD - JTAG Interface Disable

216

ATmega128RFA1
8266A-MCU Wireless-12/09

ATmega128RFA1When this bit is zero, the JTAG interface is enabled if the JTAGEN Fuse isprogrammed. If this bit is one, the JTAG interface is disabled. In order to avoid
unintentional disabling or enabling of the JTAG interface, a timed sequence must be
followed when changing this bit: The application software must write this bit to thedesired value twice within four cycles to change its value. Note that this bit must not bealtered when using the On-chip Debug system.
• Bit 6:5 – Res1:0 - Reserved• Bit 4 – PUD - Pull-up Disable
When this bit is written to one, the I/O ports pull-up resistors are disabled even if the
DDxn and PORTxn Registers are configured to enable the pull-up resistor ({DDxn,
PORTxn} = 2'b01). See section "Ports as General Digital I/O" for more details about thisfeature.
• Bit 3:2 – Res1:0 - Reserved• Bit 1 – IVSEL - Interrupt Vector SelectWhen the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of theFlash memory. When this bit is set (one), the Interrupt Vectors are moved to thebeginning of the Boot Loader section of the Flash. The actual address of the start of the
Boot Flash Section is determined by the BOOTSZ Fuses. Refer to the section "Memory
Programming" for details. To avoid unintentional changes of Interrupt Vector tables, aspecial write procedure must be followed to change the IVSEL bit (see section "Moving
Interrupts Between Application and Boot Section" for details): 1. Write the Interrupt
Vector Change Enable (IVCE) bit to one; 2. Within four cycles, write the desired value
to IVSEL while writing a zero to IVCE. Interrupts will be automatically disabled while thissequence is executed. Interrupts are disabled in the same cycle IVCE is set, and theyremain disabled until after the instruction following the write to IVSEL. If IVSEL is not
written, interrupts remain disabled for four cycles. The I-bit in the Status Register isunaffected by the automatic disabling. Note that if Interrupt Vectors are placed in the
Boot Loader section and Boot Lock bit BLB02 is programmed, interrupts are disabled
while executing from the Application section. If Interrupt Vectors are placed in the
Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while
executing from the Boot Loader section.
• Bit 0 – IVCE - Interrupt Vector Change Enable
The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE iscleared by hardware four cycles after it is written or when IVSEL is written. Setting the
IVCE bit will disable interrupts as explained in the IVSEL description.

217
8266A-MCU Wireless-12/09

16 External Interrupts
The External Interrupts are triggered by the INT7:0 pin or any of the PCINT8:0 pins.
Observe that if enabled, the interrupts will trigger even if the INT7:0 or PCINT8:0 pinsare configured as outputs. This feature provides a way of generating a softwareinterrupt.
The Pin Change Interrupt PCI0 will trigger if any enabled PCINT7:0 pin toggles, Pinchange interrupt PCI1 if the enabled PCINT8 toggles. PCINT23:9 have no function
inside the ATmega128RFA1. Their corresponding I/O port are not implemented.
PCMSK1 and PCMSK0 Registers control which pins contribute to the pin changeinterrupts. PCI2 and PCMSK2 associated to PCINT23:16 have no task in this design.
Pin change interrupts on PCINT8:0 are detected asynchronously. This implies thatthese interrupts can be used for waking the part also from sleep modes other than Idle
mode.
The External Interrupts can be triggered by a falling or rising edge or a low level. This is
set up as indicated in the specification for the External Interrupt Control Registers –EICRA (INT3:0) and EICRB (INT7:4). When the external interrupt is enabled and isconfigured as level triggered, the interrupt will trigger as long as the pin is held low.
Note that recognition of falling or rising edge interrupts on INT7:4 requires the presenceof an I/O clock, described in "Overview" on page 3. Low level interrupts and the edge
interrupt on INT3:0 are detected asynchronously. This implies that these interrupts canbe used for waking the part also from sleep modes other than Idle mode. The I/O clockis halted in all sleep modes except Idle mode.
Note that if a level triggered interrupt is used for wake-up from Power-down, therequired level must be held long enough for the MCU to complete the wake-up to trigger
the level interrupt. If the level disappears before the end of the Start-up Time, the MCU
will still wake up, but no interrupt will be generated. The start-up time is defined by the
SUT and CKSEL Fuses as described in "Clock Sources" on page 148.

16.1 Pin Change Interrupt Timing
An example of timing of a pin change interrupt is shown in Figure 16-1 below.
Figure 16-1. Normal Pin Change Interrupt
pcint_in_(0)pin_lat

PCINT(0)

D
LE

clk

0

Q

pin_sync
PCINT(0) in PCMSK(x)pcint_synpcint_setflag
PCIF

x

clk

clk
PCINT(n)pin_latpin_sync
pcint_in_(n)pcint_synpcint_setflag
PCIF

218

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ATmega128RFA1
16.2 Register Description

16.2.1 EICRA – External Interrupt Control Register A
Bit

7

6

5

4

3

2

1

0

NA ($69)

ISC31

ISC30

ISC21

ISC20

ISC11

ISC10

ISC01

ISC00

Read/Write
Initial Value

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

EICRA

The External Interrupts 3 - 0 are activated by the external pins INT3:0 if the SREG I-flagand the corresponding interrupt mask in the EIMSK is set. The level and edges on theexternal pins that activate the interrupts are defined in the following tables. Edges on
INT3:0 are registered asynchronously. Pulses on INT3:0 pins wider than the minimum
pulse width of typical 50 ns will generate an interrupt. Shorter pulses are notguaranteed to generate an interrupt. If low level interrupt is selected, the low level mustbe held until the completion of the currently executing instruction to generate aninterrupt. If enabled, a level triggered interrupt will generate an interrupt request as longas the pin is held low. When changing the ISCn bit, an interrupt can occur. Therefore, it
is recommended to first disable INTn by clearing its Interrupt Enable bit in the EIMSKRegister. Then, the ISCn bit can be changed. Finally, the INTn interrupt flag should becleared by writing a logical one to its Interrupt Flag bit (INTFn) in the EIFR Register
before the interrupt is re-enabled. When changing the ISCn1/ISCn0 bits, the interrupt
must be disabled by clearing its Interrupt Enable bit in the EIMSK Register. Otherwise
an interrupt can occur when the bits are changed.
• Bit 7:6 – ISC31:30 - External Interrupt 3 Sense Control Bit
Table 16-126 ISC3 Register Bits
Register Bits

Value

Description

ISC31:30

0x00

The low level of INTn generates an interrupt
request.

0x01

Any edge of INTn generates asynchronously
an interrupt request.

0x02

The falling edge of INTn generates
asynchronously an interrupt request.

0x03

The rising edge of INTn generates
asynchronously an interrupt request.

• Bit 5:4 – ISC21:20 - External Interrupt 2 Sense Control Bit
Table 16-127 ISC2 Register Bits
Register Bits

Value

Description

ISC21:20

0x00

The low level of INTn generates an interrupt
request.

0x01

Any edge of INTn generates asynchronously
an interrupt request.

0x02

The falling edge of INTn generates
asynchronously an interrupt request.

0x03

The rising edge of INTn generates
asynchronously an interrupt request.

• Bit 3:2 – ISC11:10 - External Interrupt 1 Sense Control Bit

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Table 16-128 ISC1 Register Bits
Register Bits

Value

Description

ISC11:10

0x00

The low level of INTn generates an interrupt
request.

0x01

Any edge of INTn generates asynchronously
an interrupt request.

0x02

The falling edge of INTn generates
asynchronously an interrupt request.

0x03

The rising edge of INTn generates
asynchronously an interrupt request.

• Bit 1:0 – ISC01:00 - External Interrupt 0 Sense Control Bit
Table 16-129 ISC0 Register Bits
Register Bits

Value

Description

ISC01:00

0x00

The low level of INTn generates an interrupt
request.

0x01

Any edge of INTn generates asynchronously
an interrupt request.

0x02

The falling edge of INTn generates
asynchronously an interrupt request.

0x03

The rising edge of INTn generates
asynchronously an interrupt request.

16.2.2 EICRB – External Interrupt Control Register B
Bit

7

6

5

4

3

2

1

0

NA ($6A)

ISC71

ISC70

ISC61

ISC60

ISC51

ISC50

ISC41

ISC40

Read/Write
Initial Value

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

EICRB

The External Interrupts 7 - 4 are activated by the external pins INT7:4 if the SREG I-flagand the corresponding interrupt mask in the EIMSK is set. The level and edges on theexternal pins that activate the interrupts are defined in the following tables. Edges on
INT7:4 are registered asynchronously. Pulses on INT7:4 pins wider than the minimum
pulse width of typical 50 ns will generate an interrupt. Shorter pulses are notguaranteed to generate an interrupt. If low level interrupt is selected, the low level mustbe held until the completion of the currently executing instruction to generate aninterrupt. If enabled, a level triggered interrupt will generate an interrupt request as longas the pin is held low. When changing the ISCn bit, an interrupt can occur. Therefore, it
is recommended to first disable INTn by clearing its Interrupt Enable bit in the EIMSKRegister. Then, the ISCn bit can be changed. Finally, the INTn interrupt flag should becleared by writing a logical one to its Interrupt Flag bit (INTFn) in the EIFR Register
before the interrupt is re-enabled. When changing the ISCn1/ISCn0 bits, the interrupt
must be disabled by clearing its Interrupt Enable bit in the EIMSK Register. Otherwise
an interrupt can occur when the bits are changed.
• Bit 7:6 – ISC71:70 - External Interrupt 7 Sense Control Bit
Table 16-130 ISC7 Register Bits

220

Register Bits

Value

Description

ISC71:70

0x00

The low level of INTn generates an interrupt

ATmega128RFA1
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ATmega128RFA1
Register Bits

Value

Description
request.

0x01

Any edge of INTn generates asynchronously
an interrupt request.

0x02

The falling edge of INTn generates
asynchronously an interrupt request.

0x03

The rising edge of INTn generates
asynchronously an interrupt request.

• Bit 5:4 – ISC61:60 - External Interrupt 6 Sense Control Bit
Table 16-131 ISC6 Register Bits
Register Bits

Value

Description

ISC61:60

0x00

The low level of INTn generates an interrupt
request.

0x01

Any edge of INTn generates asynchronously
an interrupt request.

0x02

The falling edge of INTn generates
asynchronously an interrupt request.

0x03

The rising edge of INTn generates
asynchronously an interrupt request.

• Bit 3:2 – ISC51:50 - External Interrupt 5 Sense Control Bit
Table 16-132 ISC5 Register Bits
Register Bits

Value

Description

ISC51:50

0x00

The low level of INTn generates an interrupt
request.

0x01

Any edge of INTn generates asynchronously
an interrupt request.

0x02

The falling edge of INTn generates
asynchronously an interrupt request.

0x03

The rising edge of INTn generates
asynchronously an interrupt request.

• Bit 1:0 – ISC41:40 - External Interrupt 4 Sense Control Bit
Table 16-133 ISC4 Register Bits
Register Bits

Value

Description

ISC41:40

0x00

The low level of INTn generates an interrupt
request.

0x01

Any edge of INTn generates asynchronously
an interrupt request.

0x02

The falling edge of INTn generates
asynchronously an interrupt request.

0x03

The rising edge of INTn generates
asynchronously an interrupt request.

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16.2.3 EIMSK – External Interrupt Mask Register
Bit

7

6

5

4

3

2

1

0

$1D ($3D)

INT7

INT6

INT5

INT4

INT3

INT2

INT1

INT0

Read/Write
Initial Value

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

EIMSK

When an INT7:0 bit is written to one and the I-bit in the Status Register (SREG) is set(one), the corresponding external pin interrupt is enabled. The Interrupt Sense Control
bits in the External Interrupt Control Registers EICRA and EICRB define whether theExternal Interrupt is activated on rising or falling edge or level sensed. Activity on any ofthese pins will trigger an interrupt request even if the pin is enabled as an output. This
provides a way of generating a software interrupt.
• Bit 7:0 – INT7:0 - External Interrupt Request Enable
Table 16-134 INT Register Bits
Register Bits

Value

Description

INT7:00x00

All external pin interrupts are disabled.

0xff

All external pin interrupts are enabled.

16.2.4 EIFR – External Interrupt Flag Register
Bit

7

6

5

4

3

2

1

0

$1C ($3C)

INTF7

INTF6

INTF5

INTF4

INTF3

INTF2

INTF1

INTF0

Read/Write
Initial Value

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

EIFR

When an edge or logic change on the INT7:0 pin triggers an interrupt request, INTF7:0
becomes set (one). If the I-bit in SREG and the corresponding interrupt enable bit
INT7:0 in EIMSK are set (one), the MCU will jump to the interrupt vector. The flag iscleared when the interrupt routine is executed. Alternatively, the flag can be cleared bywriting a logical one to it. These flags are always cleared when INT7:0 are configured
as level interrupt. Note that when entering sleep mode with the INT3:0 interrupts
disabled, the input buffers on these pins will be disabled. This may cause a logicchange in internal signals which will set the INTF3:0 flags. See "Digital Input Enable
and Sleep Modes" for more information.
• Bit 7:0 – INTF7:0 - External Interrupt Flag
Table 16-135 INTF Register Bits

222

Register Bits

Value

Description

INTF7:00x00

No edge or logic change on INT7:0
occurred.

0x01

A edge or logic change on INT0 occurred
and triggered an interrupt request.

0x02

...

0x80

A edge or logic change on INT7 occurred
and triggered an interrupt request.

ATmega128RFA1
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ATmega128RFA1
16.2.5 PCICR – Pin Change Interrupt Control Register
Bit

7

6

5

4

3

2

1

0

NA ($68)

Res4

Res3

Res2

Res1

Res0

PCIE2

PCIE1

PCIE0

Read/Write
Initial Value

R
0

R
0

R
0

R
0

R
0

RW
0

RW
0

RW
0

PCICR

• Bit 7:3 – Res4:0 - Reserved Bit
This bit is reserved for future use. A read access always will return zero. A write accessdoes not modify the content.
• Bit 2 – PCIE2 - Pin Change Interrupt Enable 2
When the PCIE2 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),pin change interrupt 2 is enabled. Any change on any enabled PCINT23:16 pin willcause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is
executed from the PCI2 Interrupt Vector. PCINT23:16 pins are enabled individually by
the PCMSK2 Register. Note that the I/O ports corresponding to PCINT23:16 are not
implemented. Therefore PCIE2 has no function in this device.
• Bit 1 – PCIE1 - Pin Change Interrupt Enable 1
When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),pin change interrupt 1 is enabled. Any change on any enabled PCINT15:8 pin willcause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is
executed from the PCI1 Interrupt Vector. PCINT15:8 pins are enabled individually by
the PCMSK1 Register. Note that the I/O ports corresponding to PCINT15:9 are not
implemented.
• Bit 0 – PCIE0 - Pin Change Interrupt Enable 0
When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),pin change interrupt 0 is enabled. Any change on any enabled PCINT7:0 pin will cause
an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executedfrom the PCI0 Interrupt Vector. PCINT7:0 pins are enabled individually by the PCMSK0
Register.

16.2.6 PCIFR – Pin Change Interrupt Flag Register
Bit

7

6

5

4

3

2

1

0

$1B ($3B)

Res4

Res3

Res2

Res1

Res0

PCIF2

PCIF1

PCIF0

Read/Write
Initial Value

R
0

R
0

R
0

R
0

R
0

RW
0

RW
0

RW
0

PCIFR

• Bit 7:3 – Res4:0 - Reserved Bit
This bit is reserved for future use. A read access always will return zero. A write accessdoes not modify the content.
• Bit 2 – PCIF2 - Pin Change Interrupt Flag 2
When a logic change on any PCINT23:16 pin triggers an interrupt request, PCIF2
becomes set (one). If the I-bit in SREG and the PCIE2 bit in PCICR are set (one), theMCU will jump to the corresponding Interrupt Vector. The flag is cleared when theinterrupt routine is executed. Alternatively, the flag can be cleared by writing a logicalone to it. Note that the I/O ports corresponding to PCINT23:16 are not implemented.
Therefore PCIF2 has no function in this device.

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• Bit 1 – PCIF1 - Pin Change Interrupt Flag 1
When a logic change on any PCINT15:8 pin triggers an interrupt request, PCIF1
becomes set (one). If the I-bit in SREG and the PCIE1 bit in PCICR are set (one), theMCU will jump to the corresponding Interrupt Vector. The flag is cleared when theinterrupt routine is executed. Alternatively, the flag can be cleared by writing a logicalone to it. Note that the I/O ports corresponding to PCINT15:9 are not implemented.
• Bit 0 – PCIF0 - Pin Change Interrupt Flag 0
When a logic change on any PCINT7:0 pin triggers an interrupt request, PCIF0
becomes set (one). If the I-bit in SREG and the PCIE0 bit in PCICR are set (one), theMCU will jump to the corresponding Interrupt Vector. The flag is cleared when theinterrupt routine is executed. Alternatively, the flag can be cleared by writing a logicalone to it.

16.2.7 PCMSK2 – Pin Change Mask Register 2
Bit

7

6

5

4

NA ($6D)

PCINT23PCINT22

PCINT21

PCINT20

Read/Write
Initial Value

RW
0

RW
0

RW
0

RW
0

Bit

3

2

1

0

NA ($6D)

PCINT19

PCINT18

PCINT17

PCINT16

Read/Write
Initial Value

RW
0

RW
0

RW
0

RW
0

PCMSK2PCMSK2

Note that the PCMSK2 register has no function in this device. The I/O ports associatedto PCINT23:16 are not implemented. Normally each bit PCINT23:16 selects whether
the pin change interrupt is enabled on the corresponding I/O pin. If PCINT23:16 is set
and the PCIE2 bit in PCICR is set, the pin change interrupt is enabled on thecorresponding I/O pin. If PCINT23:16 is cleared, the pin change interrupt on thecorresponding I/O pin is disabled.
• Bit 7:0 – PCINT23:16 - Pin Change Enable Mask

16.2.8 PCMSK1 – Pin Change Mask Register 1
Bit

7

6

5

4

NA ($6C)PCINT15

PCINT14PCINT13PCINT12

Read/Write
Initial Value

RW
0

RW
0

RW
0

RW
0

Bit

3

2

1

0

NA ($6C)PCINT11

PCINT10

PCINT9PCINT8Read/Write
Initial Value

RW
0

RW
0

RW
0

RW
0

PCMSK1PCMSK1

Bit PCINT8 selects whether the pin change interrupt is enabled on the corresponding
I/O pin. If PCINT8 is set and the PCIE1 bit in PCICR is set, the pin change interrupt isenabled on the corresponding I/O pin. If PCINT8 is cleared, the pin change interrupt on
the corresponding I/O pin is disabled.

224

ATmega128RFA1
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ATmega128RFA1• Bit 7:1 – PCINT15:9 - Pin Change Enable Mask
Bits 15:9 of the PCMSK1 register have no function in this device. The I/O ports
associated to PCINT15:9 are not implemented.
• Bit 0 – PCINT8 - Pin Change Enable Mask 8
If this bit is set to one the pin change interrupt on the corresponding I/O pin is enabled.
If this bit is set to zero the pin change interrupt is disabled.

16.2.9 PCMSK0 – Pin Change Mask Register 0
Bit

7

6

5

4

3

2

1

0

NA ($6B)

PCINT7PCINT6

PCINT5

PCINT4

PCINT3

PCINT2

PCINT1

PCINT0

Read/Write
Initial Value

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

PCMSK0Each bit PCINT7:0 selects whether the pin change interrupt is enabled on thecorresponding I/O pin. If PCINT7:0 is set and the PCIE0 bit in PCICR is set, the pinchange interrupt is enabled on the corresponding I/O pin. If PCINT7:0 is cleared, the pinchange interrupt on the corresponding I/O pin is disabled.
• Bit 7:0 – PCINT7:0 - Pin Change Enable Mask

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17 8-bit Timer/Counter0 with PWM
17.1 Features• Two Independent Output Compare Units• Double Buffered Output Compare Registers• Clear Timer on Compare Match (Auto Reload)• Glitch Free, Phase Correct Pulse Width Modulator (PWM)• Variable PWM Period• Frequency Generator• Three Independent Interrupt Sources (TOV0, OCF0A, and OCF0B)

17.2 Overview
Timer/Counter0 is a general purpose 8-bit Timer/Counter module with two independent
Output Compare Units and with PWM support. It allows accurate program execution
timing (event management) and wave generation.
A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 17-1. For theactual placement of I/O pins refer to section "Pin Configurations" on page 2. CPUaccessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The devicespecific I/O Register and bit locations are listed in the "Register Description" on page
238.
Figure 17-1. 8-bit Timer/Counter Block Diagram
Count
Clear
Direction

TOVn(Int.Req.)
Control Logic

clkTn

Clock SelectEdge
Detector

TOP

Tn

BOTTOM( From Prescaler )Timer/Counter
TCNTn

=

=0
OCnA
(Int.Req.)
Waveform
Generation

=

OCnA

DATA BUS

OCRnA
Fixed
TOP
Value

Waveform
Generation

=

OCnB

OCRnB

TCCRnA226

OCnB(Int.Req.)

TCCRnB

ATmega128RFA1
8266A-MCU Wireless-12/09

ATmega128RFA1
17.2.1 Registers
The Timer/Counter (TCNT0) and Output Compare Registers (OCR0A and OCR0B) are
8-bit registers. Interrupt request signals (abbreviated to Int.Req. in the figure) are allvisible in the Timer Interrupt Flag Register (TIFR0). All interrupts are individuallymasked with the Timer Interrupt Mask Register (TIMSK0). TIFR0 and TIMSK0 are notshown in the figure.
The Timer/Counter can be clocked internally, via the prescaler or by an external clock
source on the T0 pin. The Clock Select logic block controls which clock source andedge the Timer/Counter uses to increment (or decrement) its value. The Timer/Counteris inactive when no clock source is selected. The output from the Clock Select logic isreferred to as the timer clock (clkT0).
The double buffered Output Compare Registers (OCR0A and OCR0B) are comparedwith the Timer/Counter value at all times. The result of the compare can be used by the
Waveform Generator to generate a PWM or variable frequency output on the Output
Compare pins (OC0A and OC0B); see "Output Compare Unit" on page 228 for details.
The Compare Match event will also set the Compare Flag (OCF0A or OCF0B) which
can be used to generate an Output Compare interrupt request.
17.2.2 Definitions
Many register and bit references in this section are written in general form. A lower case“n” replaces the Timer/Counter number (in this case 0). A lower case “x” replaces the
Output Compare Unit (in this case Compare Unit A or Compare Unit B). However whenusing the register or bit defines in a program, the precise form must be used i.e.,
TCNT0 for accessing Timer/Counter0 counter value and so on.
The definitions in Table 17-1 are also used extensively throughout the document.
Table 17-1. Definitions
BOTTOM

The counter reaches the BOTTOM when it becomes 0x00.

MAX

The counter reaches its MAXimum when it becomes 0xFF (decimal 255).

TOP

The counter reaches the TOP when it becomes equal to the highest value inthe count sequence. The TOP value can be assigned to be the fixed value
0xFF (MAX) or the value stored in the OCR0A Register. The assignment isdependent on the mode of operation.

17.3 Timer/Counter Clock Sources
The Timer/Counter can be clocked by an internal or an external clock source. The clock
source is selected by the Clock Select logic which is controlled by the Clock Select(CS02:0) bits located in the Timer/Counter Control Register (TCCR0B). For details on
clock sources and prescaler see Timer/Counter 0, 1, 3, 4, and 5 Prescaler on page 304

17.4 Counter Unit
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter
unit. Figure 17-2 shows a block diagram of the counter and its surroundings.

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Figure 17-2. Counter Unit Block Diagram
TOVn(Int.Req.)DATA BUS

Clock Select
count
clear

TCNTn

Control Logic

clkTn

Edge
DetectorTn

direction( From Prescaler )bottomtop

Signal description (internal signals):count

Increment or decrement TCNT0 by 1;

direction

Select between increment and decrement;

clear

Clear TCNT0 (set all bits to zero);clkTnTimer/Counter clock referred to as clkT0 in the following text;

top

Signalize that TCNT0 has reached maximum value;

bottomSignalize that TCNT0 has reached minimum value (zero);

Depending of the mode of operation used, the counter is cleared, incremented or
decremented at each timer clock (clkT0). clkT0 can be generated from an external orinternal clock source selected by the Clock Select bits (CS02:0). When no clock source
is selected (CS02:0 = 0) the timer is stopped. However, the TCNT0 value can beaccessed by the CPU regardless of whether clkT0 is present or not. A CPU write accessoverrides (has priority over) all counter clear or count operations.
The counting sequence is determined by the setting of the WGM01 and WGM00 bits
located in the Timer/Counter Control Register (TCCR0A) and the WGM02 bit located in
the Timer/Counter Control Register B (TCCR0B). There are close connections between
how the counter behaves (counts) and how waveforms are generated on the Output
Compare outputs OC0A and OC0B. For more details about advanced counting
sequences and waveform generation, see "Modes of Operation" on page 232.
The Timer/Counter Overflow Flag (TOV0) is set according to the mode of operation
selected by the WGM02:0 bits. TOV0 can be used for generating a CPU interrupt.

17.5 Output Compare Unit
The 8-bit comparator continuously compares TCNT0 with the Output Compare
Registers (OCR0A and OCR0B). The comparator signals a match whenever TCNT0
equals OCR0A or OCR0B. A match will set the Output Compare Flag (OCF0A or
OCF0B) at the next clock cycle of the timer. If the corresponding interrupt is enabled,
the Output Compare Flag generates an Output Compare interrupt. The Output
Compare Flag is automatically cleared when the interrupt is executed. The flag canalternatively be software-cleared by writing a logical one to its I/O bit location. The
Waveform Generator uses the match signal to generate an output according to theoperating mode set by the WGM02:0 bits and Compare Output mode (COM0x1:0) bits.
The MAX and BOTTOM signals are used by the Waveform Generator for handling thespecial cases of the extreme values in some modes of operation (refer to "Modes ofOperation" on page 232).

228

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ATmega128RFA1
Figure 17-3. Output Compare Unit, Block Diagram
DATA BUS

OCRnx

TCNTn

= (8-bit Comparator )OCFnx (Int.Req.)

topbottomWaveform Generator

OCnx

FOCn

WGMn1:0

COMnX1:0

The OCR0x Registers are double buffered when using any of the Pulse Width
Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modesof operation, the double buffering is disabled. The double buffering synchronizes the
update of the OCR0x Compare Registers to either TOP or BOTTOM of the counting
sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical
PWM pulses and thereby making the output glitch-free.
The OCR0x Register access may seem complex, but this is not the case. When the
double buffering is enabled, the CPU has access to the OCR0x Buffer Register. If
double buffering is disabled the CPU will access the OCR0x directly.
17.5.1 Force Output Compare
In non-PWM waveform generation modes, the match output of the comparator can beforced by writing a one to the Force Output Compare (FOC0x) bit. Forcing Compare
Match will not set the OCF0x Flag or reload/clear the timer, but the OC0x pin will be
updated as if a real Compare Match had occurred (the COM0x1:0 bits settings define
whether the OC0x pin is set, cleared or toggled).
17.5.2 Compare Match Blocking by TCNT0 Write
All CPU write operations to the TCNT0 Register will block any Compare Match that
occur in the next timer clock cycle, even when the timer is stopped. This feature allows
OCR0x to be initialized to the same value as TCNT0 without triggering an interrupt
when the Timer/Counter clock is enabled.
17.5.3 Using the Output Compare Unit
Since writing TCNT0 in any mode of operation will block all Compare Matches for one
timer clock cycle, there are risks involved when changing TCNT0 while using the Output
Compare Unit, independently of whether the Timer/Counter is running or not. If thevalue written to TCNT0 equals the OCR0x value, the Compare Match will be missed
resulting in an incorrect waveform generation. Similarly, do not write the TCNT0 value
equal to BOTTOM when the counter is down-counting.
The setup of the OC0x should be performed before setting the Data Direction Registerfor the port pin to output. The easiest way of setting the OC0x value is to use the Force
Output Compare (FOC0x) strobe bits in Normal mode. The OC0x Registers keep theirvalues even when changing between Waveform Generation modes.

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Be aware that the COM0x1:0 bits are not double buffered together with the compare
value. A Change of the COM0x1:0 bits will take effect immediately.

17.6 Compare Match Output Unit
The Compare Output mode (COM0x1:0) bits have two functions. The Waveform
Generator uses the COM0x1:0 bits for defining the Output Compare (OC0x) state at thenext Compare Match. The COM0x1:0 bits control also the OC0x pin output source.
Figure 17-4 shows a simplified schematic of the logic affected by the COM0x1:0 bit
setting. The I/O Registers, I/O bits and I/O pins in the figure are shown in bold. Only theparts of the general I/O Port Control Registers (DDR and PORT) affected by theCOM0x1:0 bits are shown. When referring to the OC0x state, the reference is to theinternal OC0x Register and not to the OC0x pin. The OC0x Register is reset to “0” if asystem reset occurs.
Figure 17-4. Compare Match Output Unit Schematic

COMnx1
COMnx0
FOCn

Waveform
Generator

D

Q
1

OCnx

DATA BUS

D

0

OCnx
Pin

Q

PORT
D

Q

DDR
clk I/O

The general I/O port function is overridden by the Output Compare (OC0x) from the
Waveform Generator if either of the COM0x1:0 bits are set. However the OC0x pin
direction (input or output) is still controlled by the Data Direction Register (DDR) of theport pin. The Data Direction Register bit of the OC0x pin (DDR_OC0x) must be set as
output before the OC0x value is visible at the pin. The port override function is
independent of the Waveform Generation mode.
The design of the Output Compare pin logic allows initializing the OC0x state before theoutput is enabled. Note that some COM0x1:0 bit settings are reserved for certain
modes of operation (see "Register Description" on page 238).
17.6.1 Compare Output Mode and Waveform Generation
The Waveform Generator uses the COM0x1:0 bits differently in Normal, CTC and PWM
modes. A setting of COM0x1:0 = 0 tells the Waveform Generator in all modes that noaction on the OC0x Register is to be performed on the next Compare Match. For
compare output actions in the non-PWM modes refer to Table 17-2. For fast PWM
mode refer to Table 17-3 and for phase correct PWM refer to Table 17-4.

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A state change of the COM0x1:0 bits will have effect at the first Compare Match after
the bits are written. For non-PWM modes the action can be forced to have immediate
effect by using the FOC0x strobe bits.
The following table shows the COM0x1:0 bit functionality when the WGM02:0 bits are
set to a normal or CTC mode (non-PWM).
Table 17-2. Compare Output Mode, non-PWM Mode
COM0A1COM0B1

COM0A0COM0B000Normal port operation, OC0x disconnected;

0

1

Toggle OC0x on Compare Match;

10

Clear OC0x on Compare Match;

1

1

Set OC0x on Compare Match;

Description

Table 17-3 shows the COM0x1:0 bit functionality when the WGM01:0 bits are set to fast
PWM mode.
Table 17-3. Compare Output Mode, Fast PWM Mode
COM0A1COM0B1

COM0A0COM0B000Normal port operation, OC0x disconnected.

0

1

WGM02 = 0: Normal Port Operation, OC0A Disconnected.
WGM02 = 1: Toggle OC0A on Compare Match.
OC0B: not applicable, reserved function;

1

0

Clear OC0x on Compare Match, set OC0x at BOTTOM, (noninverting mode).

1

1

Set OC0x on Compare Match, clear OC0x at BOTTOM, (invertingmode).

Note:

Description

A special case occurs when OCR0x equals TOP and COM0x1 is set. In this case, theCompare Match is ignored, but the set or clear is done at BOTTOM. See "Fast PWM
Mode" on page 233.

Table 17-4 shows the COM0x1:0 bit functionality when the WGM02:0 bits are set tophase correct PWM mode.
Table 17-4. Compare Output Mode, Phase Correct PWM Mode
COM0A1COM0B1

COM0A0COM0B000Normal port operation, OC0x disconnected.

0

1

WGM02 = 0: Normal Port Operation, OC0A Disconnected.
WGM02 = 1: Toggle OC0A on Compare Match.
OC0B: not applicable, reserved function;

1

0

Clear OC0x on Compare Match when up-counting. Set OC0x on
Compare Match when down-counting.

1

1

Set OC0x on Compare Match when up-counting. Clear OC0x on
Compare Match when down-counting.

Note:

Description

A special case occurs when OCR0x equals TOP and COM0x1 is set. In this case, theCompare Match is ignored, but the set or clear is done at TOP. See "Fast PWM
Mode" on page 233 for more details.

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17.7 Modes of Operation
The mode of operation i.e., the behavior of the Timer/Counter and the Output Compare
pins, is defined by the combination of the Waveform Generation mode (WGM02:0) andCompare Output mode (COM0x1:0) bits. The Compare Output mode bits do not affectthe counting sequence while the Waveform Generation mode bits do. The COM0x1:0
bits control whether the PWM output generated should be inverted or not (inverted or
non-inverted PWM). For non-PWM modes the COM0x1:0 bits control whether the
output should be set, cleared, or toggled at a Compare Match (see "Output Compare
Unit" on page 228).
For detailed timing information see "Timer/Counter Timing Diagrams" on page 236.
Table 17-5 shows the function of the WGM2:0 bits of registers TCCR0A and TCCR0B.
These bits control the counting sequence of the counter, the source for maximum(TOP) counter value, and what type of waveform generation to be used.
Table 17-5. Waveform Generation Mode Bit Description

Mode

WGM2

WGM1

WGM0

Timer/Counter
Mode of
Operation

0

0

0

0

Normal0xFF

Immediate

MAX

1

0

0

1

PWM, Phase
Correct

0xFF

TOP

BOTTOM

2

0

1

0

CTC

OCRA

Immediate

MAX

3

0

1

1

Fast PWM

0xFF

TOP

MAX

4

1

0

0

Reserved

–

–

–

5

1

0

1

PWM, Phase
Correct

OCRA

TOP

BOTTOM

6

1

1

0

Reserved

–

–

–

7

1

1

1

Fast PWM

OCRA

BOTTOMTOP

Notes:

TOP

Update of
OCRX at

TOV Flag(0,0)
Set on1. MAX = 0xFF
2. BOTTOM = 0x00

17.7.1 Normal Mode
The simplest mode of operation is the Normal mode (WGM02:0 = 0). In this mode thecounting direction is always up (incrementing) and no counter clear is performed. The
counter simply overruns when it passes its maximum 8-bit value (TOP = 0xFF) and thenrestarts from the BOTTOM (0x00). In normal operation the Timer/Counter Overflow
Flag (TOV0) will be set at the same timer clock cycle when the TCNT0 becomes zero.
th
The TOV0 Flag in this case behaves like a 9 bit, except that it is only set and not
cleared. However, the timer resolution can be increased by software utilizing the timer
overflow interrupt that automatically clears the TOV0 Flag. There are no special cases
to consider in the Normal mode. A new counter value can be written at anytime.
The Output Compare Unit can be used to generate interrupts at some given time. It is
not recommended to use the Output Compare for waveform generation in Normalmode, since this will occupy too much CPU time.
17.7.2 Clear Timer on Compare Match (CTC) ModeIn Clear Timer on Compare (CTC) mode (WGM02:0 = 2), the OCR0A Register is used
to manipulate the counter resolution. In CTC mode the counter is cleared to zero when
the counter value (TCNT0) matches OCR0A. The OCR0A value defines the TOP value
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for the counter, hence also its resolution. This mode allows greater control of theCompare Match output frequency. It also simplifies the operation of counting external
events.
The timing diagram for the CTC mode is shown in Figure 17-5. The counter value(TCNT0) increases until a Compare Match occurs between TCNT0 and OCR0A. The
counter (TCNT0) is then cleared.
Figure 17-5. CTC Mode Timing Diagram
OCnx Interrupt Flag Set

TCNTn

OCn
(Toggle)Period(COMnx1:0 = 1)

1

2

3

4

An interrupt can be generated each time the counter value reaches the TOP value by
using the OCF0A Flag. If the interrupt is enabled, the interrupt handler routine canupdate the TOP value. However, changing TOP to a value close to BOTTOM when the
counter is running with no or a low prescaler value must be done with care since the
CTC mode does not have the double buffering feature. If the new value written to
OCR0A is lower than the current value of TCNT0, the counter will miss the Compare
Match. The counter will then have to count to its maximum value (0xFF) and wrap
around starting at 0x00 before the Compare Match can occur.
For generating a waveform output in CTC mode, the OC0A output can be set to toggle
its logical level on each Compare Match by setting the Compare Output mode bits totoggle mode (COM0A1:0 = 1). The OC0A value will not be visible on the port pin unlessthe data direction of the pin is set to output. The generated waveform will have amaximum frequency of fOC0 = fclk_I/O/2 when OCR0A is set to zero (0x00). The waveform
frequency is defined by the following equation:f OC 0 x =f CLK _ I / O
2 ⋅ N ⋅ (1 + OCR 0 x)

The N variable represents the prescale factor (1, 8, 64, 256 or 1024).
As for the Normal mode of operation, the TOV0 Flag is set in the same timer clock cyclethat the counter changes from MAX to 0x00.
17.7.3 Fast PWM Mode
The fast Pulse Width Modulation (PWM) mode (WGM02:0 = 3 or 7) provides a highfrequency PWM waveform generation option. The fast PWM mode differs from theother PWM modes by its single-slope operation. The counter counts from BOTTOM to
TOP and then restarts from BOTTOM. TOP is defined as 0xFF when WGM2:0 = 3, and
OCR0A when WGM2:0 = 7. In non-inverting Compare Output mode the Output
Compare (OC0x) is cleared on the Compare Match between TCNT0 and OCR0x andset at BOTTOM. In inverting Compare Output mode the output is set on Compare
Match and cleared at BOTTOM. Due to the single-slope operation, the operating
frequency of the fast PWM mode can be twice as high as in the phase correct PWM
mode that uses dual-slope operation. This high frequency operation makes the fast
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PWM mode well suited for power regulation, rectification and DAC applications. The
high frequency allows physically small sized external components (coils, capacitors),
and therefore reduces total system cost.
In fast PWM mode, the counter is incremented until the counter value matches the TOP
value. The counter is then cleared at the following timer clock cycle. The timing diagram
for the fast PWM mode is shown in Figure 17-6. The TCNT0 value is shown in thetiming diagram as a histogram illustrating the single-slope operation. The diagram
includes non-inverted and inverted PWM outputs. The small horizontal line marks on
the TCNT0 slopes represent Compare Matches between OCR0x and TCNT0.
Figure 17-6. Fast PWM Mode Timing Diagram
OCRnx Interrupt Flag Set

OCRnx Update and
TOVn Interrupt Flag Set

TCNTn

OCnx

(COMnx1:0 = 2)

OCnx

(COMnx1:0 = 3)

Period

1

2

3

4

5

6

7

The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches TOP.
The interrupt handler routine can be used for updating the compare value if the interrupt
is enabled.
In fast PWM mode the compare unit allows generating PWM waveforms on the OC0x
pins. Setting the COM0x1:0 bits to 2 will produce a non-inverted PWM. An inverted
PWM output can be generated by setting the COM0x1:0 to 3. Setting the COM0A1:0
bits to 1 allows the OC0A pin to toggle on Compare Matches if the WGM02 bit is set.
This option is not available for the OC0B pin (see Table 17-3 on page 231). The actual
OC0x value will only be visible at the port pin if the data direction of the port pin is set to
output. The PWM waveform is generated by setting (or clearing) the OC0x Register at
the Compare Match between OCR0x and TCNT0, and by clearing (or setting) the OC0x
Register at the timer clock cycle when the counter is cleared (changes from TOP to
BOTTOM).
The PWM frequency for the output fOC0xPWM can be calculated with the following
equation:f OC 0 xPWM =f clk _ I / O
N ⋅ 256

The N variable represents the pre-scale factor (1, 8, 64, 256 or 1024).
The extreme values for the OCR0A Register represent special cases when generatinga PWM waveform output in the fast PWM mode. If the OCR0A is set equal to BOTTOM,
the output will be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR0A

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equal to MAX will result in a constantly high or low output (depending on the polarity ofthe output set by the COM0A1:0 bits.)
A frequency with 50% duty cycle waveform output in fast PWM mode can be achievedby setting OC0x to toggle its logical level on each Compare Match (COM0x1:0 = 1). The
generated waveform will have a maximum frequency of fOC0xPWM = fclk_I/O/2 when
OCR0A is set to zero. This feature is similar to the OC0A toggle in CTC mode, exceptthat in the fast PWM mode the double buffer feature of the Output Compare unit isenabled.
17.7.4 Phase Correct PWM Mode
The phase correct pulse-width modulation (PWM) mode (WGM02:0 = 1 or 5) provides aphase-correct, high-resolution PWM waveform generation option. The phase correct
PWM mode is based on a dual-slope operation. The counter counts repeatedly from
BOTTOM to TOP and then from TOP to BOTTOM. TOP is defined as 0xFF when
WGM2:0 = 1 and TOP = OCR0A when WGM2:0 = 5. In non-inverting Compare Output
mode, the Output Compare (OC0x) is cleared on the Compare Match between TCNT0
and OCR0x while up-counting, and OC0x is set on the Compare Match while downcounting. The operation is inverted in inverting Output Compare mode. The dual-slope
operation has a lower maximum operation frequency than single-slope operation.
However, due to the symmetric feature of the dual-slope PWM modes, these modes are
preferred for motor control applications.
In phase correct PWM mode the counter is incremented until the counter value matches
TOP. The counter changes the direction when reaching TOP. The TCNT0 value will beequal to TOP for one timer clock cycle. The timing diagram for the phase correct PWM
mode is shown in Figure 17-7 below. The TCNT0 value is shown in the timing diagram
as a histogram illustrating the dual-slope operation. The diagram includes non-inverted
and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes
represent Compare Matches between OCR0x and TCNT0.
Figure 17-7. Phase Correct PWM Mode Timing Diagram
OCnx Interrupt Flag Set

OCRnx Update

TOVn Interrupt Flag Set

TCNTn

OCnx

(COMnx1:0 = 2)

OCnx

(COMnx1:0 = 3)

Period1

2

3

The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches
BOTTOM. The Interrupt Flag can be used to generate an interrupt each time thecounter reaches the BOTTOM value.
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In phase correct PWM mode, the compare unit allows generating PWM waveforms on
the OC0x pins. Setting the COM0x1:0 bits to 2 will produce a non-inverted PWM. An
inverted PWM output can be generated by setting the COM0x1:0 to 3. Setting theCOM0A0 bits to 1 allows the OC0A pin to toggle on Compare Matches if the WGM02
bit is set. This option is not available for the OC0B pin (see Table 17-4 on page 231).
The actual OC0x value will only be visible at the port pin if the data direction for the port
pin is set to output. The PWM waveform is generated by clearing (or setting) the OC0x
Register at the Compare Match between OCR0x and TCNT0 when the counterincrements, and by setting (or clearing) the OC0x Register at Compare Match between
OCR0x and TCNT0 when the counter decrements. The PWM frequency for the output
fOC0xPCPWM when using phase-correct PWM can be calculated with the following
equation:f OC 0 xPCPWM =f clk _ I / O
N ⋅ 510The N variable represents the prescale factor (1, 8, 64, 256 or 1024).
The extreme values for the OCR0A Register represent special cases when generatinga PWM waveform output in the phase-correct PWM mode. If the OCR0A is set equal to
BOTTOM, the output will be continuously low and if set equal to MAX the output will be
continuously high for non-inverted PWM mode. For inverted PWM the output will havethe opposite logic values.
At the very start of period 2 in Figure 17-7 OCnx has a transition from high to low eventhough there is no Compare Match. The reason of this transition is to guarantee
symmetry around BOTTOM. There are two cases that give a transition without
Compare Match:• OCR0x changes its value from MAX like in Figure 17-7 on page 235. When the
OCR0x value is MAX the OC0x pin value is the same as the result of a downcounting Compare Match. To ensure symmetry around BOTTOM the OC0x value at
MAX must correspond to the result of an up-counting Compare Match.
• The timer starts counting from a value higher than the one in OCR0x. For thatreason it misses the Compare Match and hence the OC0x change that would have
happened on the way up.

17.8 Timer/Counter Timing Diagrams
The Timer/Counter is a synchronous design and the timer clock (clkT0) is therefore
shown as a clock enable signal in the following figures. The figures include information
on when Interrupt Flags are set. Figure 17-8 contains timing data for basic
Timer/Counter operation. The figure shows the count sequence close to the MAX value
in all modes other than phase correct PWM mode.
Figure 17-8. Timer/Counter Timing Diagram, no Prescaling
clkI/O
clkTn(clkI/O /1)

TCNTn

MAX - 1MAX

BOTTOM

BOTTOM + 1

TOVn

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Figure 17-9 shows the same timing data, but with the prescaler enabled.
Figure 17-9. Timer/Counter Timing Diagram with Prescaler (fclk_I/O/8)
clkI/O
clkTn(clkI/O /8)

TCNTn

MAX - 1MAX

BOTTOM

BOTTOM + 1

TOVn

Figure 17-10 shows the setting of OCF0B and OCF0A in all modes except CTC and
PWM mode, where OCR0A is TOP.
Figure 17-10. Timer/Counter Timing Diagram, setting of OCF0x with Prescaler (fclk_I/O/8)
clkI/O
clkTn(clkI/O /8)

TCNTn

OCRnx - 1

OCRnx

OCRnx + 1

OCRnx + 2

OCRnx Value

OCRnx

OCFnx

Figure 17-11 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode andfast PWM mode where OCR0A is TOP.
Figure 17-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match modewith Prescaler (fclk_I/O/8)
clkI/O
clkTn(clkI/O /8)

TCNTn
(CTC)
OCRnx

TOP - 1TOP

BOTTOM

BOTTOM + 1

TOP

OCFnx

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17.9 Register Description
17.9.1 GTCCR – General Timer/Counter Control Register
Bit

7

6

5

4

3

2

1

$23 ($43)

TSM

Res4

Res3

Res2

Res1

Res0

Read/Write
Initial Value

RW
0

R
0

R
0

R
0

R
0

R
0

0

PSRASY PSRSYNC
R
0

GTCCR

RW
0

• Bit 7 – TSM - Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In thismode the value that is written to the PSRASY and PSRSYNC bits is kept, hence
keeping the corresponding prescaler reset signals asserted. This ensures that thecorresponding Timer/Counters are halted and can be configured to the same value
without the risk of one of them advancing during the configuration. When the TSM bit is
written to zero, the PSRASY and PSRSYNC bits are cleared by hardware and theTimer/Counters simultaneously start counting.
• Bit 6:2 – Res4:0 - Reserved
This bit is reserved for future use. A read access always will return zero. A write accessdoes not modify the content.
• Bit 1 – PSRASY - Prescaler Reset Timer/Counter2
When this bit is one, the Timer/Counter2 prescaler will be reset. This bit is normally
cleared immediately by hardware. If the bit is written when Timer/Counter2 is operatingin asynchronous mode, the bit will remain one until the prescaler has been reset. The
bit will not be cleared by hardware if the TSM bit is set.
• Bit 0 – PSRSYNC - Prescaler Reset for Synchronous Timer/Counters
When this bit is one, the Timer/Counter0, Timer/Counter1, Timer/Counter3,
Timer/Counter4 and Timer/Counter5 prescaler will be reset. This bit is normally cleared
immediately by hardware, except if the TSM bit is set. Note that Timer/Counter0,
Timer/Counter1, Timer/Counter3, Timer/Counter4 and Timer/Counter5 share the sameprescaler and a reset of this prescaler will affect all timers.

17.9.2 TCCR0A – Timer/Counter0 Control Register A
Bit$24 ($44)
Read/Write
Initial Value

7

6

5

4

COM0A1 COM0A0 COM0B1 COM0B0
RW
0

RW
0

RW
0

RW
0

3

2

1

0

Res1

Res0

WGM01

WGM00

R
0

R
0

RW
0

RW
0

TCCR0A• Bit 7:6 – COM0A1:0 - Compare Match Output A Mode
These bits control the Output Compare pin (OC0A) behavior. If one or both of the
COM0A1:0 bits are set, the OC0A output overrides the normal port functionality of the
I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit
corresponding to the OC0A pin must be set in order to enable the output driver. When
OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the
WGM02:0 bit setting. The following shows the COM0A1:0 bit functionality when the
WGM02:0 bits are set to a normal or CTC mode (non-PWM). For the functionality inother modes refer to section "Operating Modes".

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Table 17-6 COM0A Register Bits
Register Bits

Value

Description

COM0A1:00

Normal port operation, OC0A disconnected

1

Toggle OC0A on Compare Match

2

Clear OC0A on Compare Match

3

Set OC0A on Compare Match• Bit 5:4 – COM0B1:0 - Compare Match Output B Mode
These bits control the Output Compare pin (OC0B) behavior. If one or both of the
COM0B1:0 bits are set, the OC0B output overrides the normal port functionality of the
I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit
corresponding to the OC0B pin must be set in order to enable the output driver. When
OC0B is connected to the pin, the function of the COM0B1:0 bits depends on the
WGM02:0 bit setting. The following shows the COM0B1:0 bit functionality when the
WGM02:0 bits are set to a normal or CTC mode (non-PWM). For the functionality inother modes refer to section "Operating Modes".
Table 17-7 COM0B Register Bits
Register Bits

Value

Description

COM0B1:00

Normal port operation, OC0B disconnected

1

Toggle OC0B on Compare Match

2

Clear OC0B on Compare Match

3

Set OC0B on Compare Match• Bit 3:2 – Res1:0 - Reserved Bit
This bit is reserved for future use. A read access always will return zero. A write accessdoes not modify the content.
• Bit 1:0 – WGM01:00 - Waveform Generation Mode
Combined with the WGM02 bit found in the TCCR0B Register, these bits control thecounting sequence of the counter, the source for maximum (TOP) counter value, andwhat type of waveform generation to be used according to the following table. Modes ofoperation supported by the Timer/Counter0 unit are: Normal mode (counter), Clear
Timer on Compare Match (CTC) mode, and two types of Pulse Width Modulation(PWM) modes (see section "Modes of Operation" for details).
Table 17-8 WGM0 Register Bits
Register Bits

Value

Description

WGM01:00

0x0

Normal mode of operation

0x1

PWM, phase correct, TOP=0xFF

0x2

CTC, TOP = OCRA

0x3

Fast PWM, TOP=0xFF

0x4

Reserved

0x5

PWM, Phase correct, TOP = OCRA

0x6

Reserved

0x7

Fast PWM, TOP=OCRA

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17.9.3 TCCR0B – Timer/Counter0 Control Register B
Bit

7

6

5

4

3

2

1

0

$25 ($45)

FOC0A

FOC0B

Res1

Res0

WGM02

CS02

CS01

CS00

Read/Write
Initial Value

W
0

W
0

R
0

R
0

RW
0

RW
0

RW
0

RW
0

TCCR0B• Bit 7 – FOC0A - Force Output Compare A
The FOC0A bit is only active when the WGM02:0 bits specify a non-PWM mode.
However, for ensuring compatibility with future devices, this bit must be set to zero
when TCCR0B is written in a PWM operation mode. When writing a logical one to the
FOC0A bit, an immediate Compare Match is forced on the Waveform Generation unit.
The OC0A output is changed according to its COM0A1:0 bits setting. Note that the
FOC0A bit is implemented as a strobe. Therefore it is the value present in the
COM0A1:0 bits that determines the effect of the forced compare. A FOC0A strobe will
not generate any interrupt nor will it clear the timer in CTC mode using OCR0A as TOP.
The FOC0A bit is always read as zero.
• Bit 6 – FOC0B - Force Output Compare B
The FOC0B bit is only active when the WGM02:0 bits specify a non-PWM mode.
However, for ensuring compatibility with future devices, this bit must be set to zero
when TCCR0B is written in a PWM operation mode. When writing a logical one to the
FOC0B bit, an immediate Compare Match is forced on the Waveform Generation unit.
The OC0B output is changed according to its COM0B1:0 bits setting. Note that the
FOC0B bit is implemented as a strobe. Therefore it is the value present in the
COM0B1:0 bits that determines the effect of the forced compare. A FOC0B strobe will
not generate any interrupt nor will it clear the timer in CTC mode using OCR0B as TOP.
The FOC0B bit is always read as zero.
• Bit 5:4 – Res1:0 - Reserved Bit
This bit is reserved for future use. A read access always will return zero. A write accessdoes not modify the content.
• Bit 3 – WGM02 Combined with the WGM01:0 bit found in the TCCR0A Register, these bits control thecounting sequence of the counter, the source for maximum (TOP) counter value, andwhat type of waveform generation to be used. Modes of operation supported by theTimer/Counter unit are: Normal mode (counter), Clear Timer on Compare Match (CTC)
mode, and two types of Pulse Width Modulation (PWM) modes (see section "Modes ofOperation").
• Bit 2:0 – CS02:00 - Clock SelectThe three Clock Select bits select the clock source to be used by the Timer/Counter0
according to the following table.If external pin modes are used for Timer/Counter0,transitions on the T0 pin will clock the counter even if the pin is configured as an output.
This feature allows software control of the counting.
Table 17-9 CS0 Register Bits

240

Register Bits

Value

Description

CS02:00

0x00

No clock source (Timer/Counter0 stopped)

0x01

clk_IO/1 (no prescaling)

0x02

clk_IO/8 (from prescaler)0x03

clk_IO/64 (from prescaler)

ATmega128RFA1
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ATmega128RFA1
Register Bits

Value

Description

0x04

clk_IO/256 (from prescaler)0x05

clk_IO/1024 (from prescaler)

0x06

External clock source on T0 pin, clock on
falling edge

0x07

External clock source on T0 pin, clock on
rising edge

17.9.4 TCNT0 – Timer/Counter0 Register
Bit

7

6

5

4

$26 ($46)

TCNT0_7

TCNT0_6

TCNT0_5

TCNT0_4

Read/Write
Initial Value

RW
0

RW
0

RW
0

RW
0

Bit

3

2

1

0

$26 ($46)

TCNT0_3

TCNT0_2

TCNT0_1

TCNT0_0

Read/Write
Initial Value

RW
0

RW
0

RW
0

RW
0

TCNT0

TCNT0

The Timer/Counter Register gives direct access, both for read and write operations, tothe Timer/Counter0 unit 8-bit counter. Writing to the TCNT0 Register blocks (removes)
the Compare Match on the following timer clock. Modifying the counter (TCNT0) while
the counter is running, introduces a risk of missing a Compare Match between TCNT0
and the OCR0x Registers.
• Bit 7:0 – TCNT0_7:0 - Timer/Counter0 Byte

17.9.5 OCR0A – Timer/Counter0 Output Compare Register
Bit

7

6

5

4

$27 ($47)

OCR0A_7

OCR0A_6

OCR0A_5

OCR0A_4

Read/Write
Initial Value

RW
0

RW
0

RW
0

RW
0

Bit

3

2

1

0

$27 ($47)

OCR0A_3

OCR0A_2

OCR0A_1

OCR0A_0

Read/Write
Initial Value

RW
0

RW
0

RW
0

RW
0

OCR0A

OCR0A

The Output Compare Register A contains an 8-bit value that is continuously comparedwith the counter value (TCNT0). A match can be used to generate an Output Compareinterrupt, or to generate a waveform output on the OC0A pin.
• Bit 7:0 – OCR0A_7:0 - Output Compare Register

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17.9.6 OCR0B – Timer/Counter0 Output Compare Register B
Bit

7

6

5

4

$28 ($48)

OCR0B_7

OCR0B_6

OCR0B_5

OCR0B_4

Read/Write
Initial Value

RW
0

RW
0

RW
0

RW
0

Bit

3

2

1

0

$28 ($48)

OCR0B_3

OCR0B_2

OCR0B_1

OCR0B_0

Read/Write
Initial Value

RW
0

RW
0

RW
0

RW
0

OCR0B

OCR0B

The Output Compare Register B contains an 8-bit value that is continuously comparedwith the counter value (TCNT0). A match can be used to generate an Output Compareinterrupt, or to generate a waveform output on the OC0B pin.
• Bit 7:0 – OCR0B_7:0 - Output Compare Register

17.9.7 TIMSK0 – Timer/Counter0 Interrupt Mask Register
Bit

7

6

5

4

3

2

1

0

NA ($6E)

Res4

Res3

Res2

Res1

Res0

OCIE0B

OCIE0A

TOIE0

Read/Write
Initial Value

R
0

R
0

R
0

R
0

R
0

RW
0

RW
0

RW
0

TIMSK0• Bit 7:3 – Res4:0 - Reserved
This bit is reserved for future use. A read access always will return zero. A write accessdoes not modify the content.
• Bit 2 – OCIE0B - Timer/Counter0 Output Compare Match B Interrupt Enable
When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, theTimer/Counter0 Compare Match B interrupt is enabled. The corresponding interrupt is
executed if a Compare Match in Timer/Counter0 occurs, i.e., when the OCF0B bit is set
in the Timer/Counter0 Interrupt Flag Register TIFR0.
• Bit 1 – OCIE0A - Timer/Counter0 Output Compare Match A Interrupt Enable
When the OCIE0A bit is written to one, and the I-bit in the Status Register is set, theTimer/Counter0 Compare Match A interrupt is enabled. The corresponding interrupt is
executed if a Compare Match in Timer/Counter0 occurs, i.e., when the OCF0A bit is set
in the Timer/Counter0 Interrupt Flag Register TIFR0.
• Bit 0 – TOIE0 - Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is written to one, and the I-bit in the Status Register is set, theTimer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed
if an overflow in Timer/Counter0 occurs i.e., when the TOV0 bit is set in theTimer/Counter0 Interrupt Flag Register TIFR0.

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17.9.8 TIFR0 – Timer/Counter0 Interrupt Flag Register
Bit

7

6

5

4

3

2

1

0

$15 ($35)

Res4

Res3

Res2

Res1

Res0

OCF0B

OCF0A

TOV0

Read/Write
Initial Value

R
0

R
0

R
0

R
0

R
0

RW
0

RW
0

RW
0

TIFR0

• Bit 7:3 – Res4:0 - Reserved
This bit is reserved for future use. A read access always will return zero. A write accessdoes not modify the content.
• Bit 2 – OCF0B - Timer/Counter0 Output Compare B Match Flag
The OCF0B bit is set when a Compare Match occurs between the Timer/Counter0 andthe data in OCR0B Output Compare Register. OCF0B is cleared by hardware when
executing the corresponding interrupt handling vector. Alternatively, OCF0B is clearedby writing a logic one to the flag. When the I-bit in SREG, OCIE0B (Timer/Counter
Compare B Match Interrupt Enable) and OCF0B are set, the Timer/Counter Compare
Match Interrupt is executed.
• Bit 1 – OCF0A - Timer/Counter0 Output Compare A Match Flag
The OCF0A bit is set when a Compare Match occurs between the Timer/Counter0 andthe data in OCR0A Output Compare Register. OCF0A is cleared by hardware when
executing the corresponding interrupt handling vector. Alternatively, OCF0A is clearedby writing a logic one to the flag. When the I-bit in SREG, OCIE0A (Timer/Counter
Compare A Match Interrupt Enable) and OCF0A are set, the Timer/Counter Compare
Match Interrupt is executed.
• Bit 0 – TOV0 - Timer/Counter0 Overflow Flag
The bit TOV0 is set when an overflow occurs in Timer/Counter0. TOV0 is cleared byhardware when executing the corresponding interrupt handling vector. Alternatively,
TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0(Timer/Counter0 Overflow Interrupt Enable) and TOV0 are set, the Timer/Counter0
Overflow interrupt is executed. The setting of this flag is dependent of the WGM02:0 bit
setting.

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18 16-bit Timer/Counter (Timer/Counter 1, 3, 4, and 5)
18.1 Features• True 16-bit Design (i.e., allows 16-bit PWM)
• Three independent Output Compare Units• Double Buffered Output Compare Registers• One Input Capture Unit
• Input Capture Noise Canceller• Clear Timer on Compare Match (Auto Reload)• Glitch-free, Phase Correct Pulse Width Modulator (PWM)• Variable PWM Period• Frequency Generator• External Event Counter• Numerous independent interrupt sourcesoTOV1, OCF1A, OCF1B, OCF1C, ICF1o

TOV3, OCF3A, OCF3B, OCF3C, ICF3o

TOV4, OCF4A, OCF4B, OCF4C

o

TOV5, OCF5A, OCF5B, OCF5C

18.2 Overview
The 16-bit Timer/Counter unit allows accurate program execution timing (event
management), wave generation and signal timing measurement.
Most register and bit references in this section are written in general form. A lower case“n” replaces the Timer/Counter number, and a lower case “x” replaces the Output
Compare unit channel. However when using the register or bit defines in a program, theprecise form must be used i.e., TCNT1 for accessing Timer/Counter1 counter value andso on.
A simplified block diagram of the 16-bit Timer/Counter is shown in Figure 18-1. For theactual placement of I/O pins, see section "Pin Configurations" on page 2. CPUaccessible I/O Registers, including I/O bits and I/O pins are shown in bold. The devicespecific I/O Register and bit locations are listed in the section "Register Description" onpage 266.
The Power Reduction Timer/Counter1 bit, PRTIM1, in "PRR0 – Power Reduction
Register0" on page 167 must be written to zero to enable Timer/Counter1 module.
The Power Reduction bits of Timer/Counter3 (PRTIM3), Timer/Counter4 bit (PRTIM4)
and Timer/Counter5 (PRTIM5) in "PRR1 – Power Reduction Register 1" on page 168
must be written to zero to enable the respective Timer/Counter module.
Note, note the complete Timer/Counter I/O functionality is provided for each
Timer/Counter module depending on the available I/O pins.

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Figure 18-1. 16-bit Timer/Counter Block Diagram

(1)

Count
Clear
Direction

TOVn(Int.Req.)
Control Logic

clkTn

Clock SelectEdge
Detector

TOP

Tn

BOTTOM( From Prescaler )Timer/Counter
TCNTn

=

=0
OCnA
(Int.Req.)
Waveform
Generation

=

OCnA

DATA BUS

OCRnA
OCnB
(Int.Req.)

Fixed
TOP
ValuesWaveform
Generation

=
OCRnB

OCnB

( From Analog
Comparator Ouput )ICFn (Int.Req.)
Edge
Detector

ICRn

Noise
Canceler
ICPn

TCCRnA

Notes:

TCCRnB

1. Refer to Figure 1-1 on page 2, Table 14-3 on page 193 and Table 14-9 on page197 for Timer/Counter1, 2 and 3 pin placements and description.

18.2.1 Registers
The Timer/Counter (TCNTn) Output Compare Registers (OCRnA/B/C) and Input
Capture Register (ICRn) are all 16-bit registers. Special procedures must be followed
when accessing the 16-bit registers. These procedures are described in the section"Accessing 16-bit Registers" on page 246. The Timer/Counter Control Registers(TCCRnA/B/C) are 8-bit registers and have no CPU access restrictions. Interrupt
requests (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag Register(TIFRn). All interrupts are individually masked with the Timer Interrupt Mask Register(TIMSKn). TIFRn and TIMSKn are not shown in the figure since these registers areshared by other timer units.
The Timer/Counter can be clocked internally, via the prescaler or by an external clock
source on the Tn pin. The Clock Select logic block controls which clock source andwhich clock edge the Timer/Counter uses to increment (or decrement) its value. The
Timer/Counter is inactive when no clock source is selected. The output from the clock
select logic is referred to as the timer clock (clkTn).
The double buffered Output Compare Registers (OCRnA/B/C) are compared with the245
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Timer/Counter value at all time. The result of the compare can be used by the
Waveform Generator to generate a PWM or variable frequency output on the Output
Compare pin (OCnA/B/C). See section "Output Compare Units" on page 252 for details.
The compare match event will also set the Compare Match Flag (OCFnA/B/C) which
can be used to generate an Output Compare interrupt request.
The Input Capture Register can capture the Timer/Counter value at a given external(edge triggered) event on either the Input Capture pin (ICPn) or on the Analog
Comparator pins (see "AC – Analog Comparator" on page 407). The Input Capture unit
includes a digital filtering unit (Noise Canceller) for reducing the chance of capturing
noise spikes.
The TOP value, or maximum Timer/Counter value, can in some modes of operation be
defined by either the OCRnA Register, the ICRn Register or by a set of fixed values.
When using OCRnA as TOP value in a PWM mode, the OCRnA Register can not be
used for generating a PWM output. However the TOP value will in this case be double
buffered allowing the TOP value to be changed at run time. If a fixed TOP value isrequired, the ICRn Register can be used as an alternative, freeing the OCRnA to be
used as PWM output.
18.2.2 Definitions
The following definitions are used extensively throughout the document:
Table 18-1. Definitions
BOTTOM

The counter reaches the BOTTOM when it becomes 0x0000.

MAX

The counter reaches its MAXimum when it becomes 0xFFFF (decimal 65535).

TOP

The counter reaches the TOP when it becomes equal to the highest value inthe count sequence. The TOP value can be assigned to be one of the fixedvalues: 0x00FF, 0x01FF, 0x03FF or to the value stored in the OCRnA or ICRn
Register. The assignment is dependent of the mode of operation.

18.3 Accessing 16-bit Registers
The TCNTn, OCRnA/B/C and ICRn are 16-bit registers that can be accessed by the
AVR CPU via the 8-bit data bus. The 16-bit register must be byte accessed using two
read or write operations. Each 16-bit timer has a single 8-bit register for temporary
storing of the high byte of the 16-bit access. The same Temporary Register is shared
between all 16-bit registers within each 16-bit timer. Accessing the low byte triggers the
16-bit read or write operation. When the low byte of a 16-bit register is written by theCPU, the written low byte and the high byte stored in the Temporary Register are bothcopied into the 16-bit register in the same clock cycle. When the low byte of a 16-bit
register is read by the CPU, the high byte of the 16-bit register is copied into the
Temporary Register in the same clock cycle as the low byte is read.
Not all 16-bit accesses use the Temporary Register for the high byte. Reading the
OCRnA/B/C 16-bit registers does not involve using the Temporary Register.
To do a 16-bit write, the high byte must be written before the low byte. For a 16-bit read,the low byte must be read before the high byte.
The following code examples show how to access the 16-bit timer registers assumingthat no interrupt updates the temporary register. The same principle can be useddirectly for accessing the OCRnA/B/C and ICRn Registers. Note that when using the Cprogramming language, the compiler handles the 16-bit access.

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ATmega128RFA1(1)

Assembly Code Examples...

; Set TCNTn to 0x01FF
ldi r17,0x01
ldi r16,0xFF
out TCNTnH,r17
out TCNTnL,r16; Read TCNTn into r17:r16
in r16,TCNTnL
in r17,TCNTnH...
(1)

C Code Examples
unsigned int i;...
/* Set TCNTn to 0x01FF */TCNTn = 0x1FF;/* Read TCNTn into i */i = TCNTn;...
Notes:

1. See "About Code Examples" on page 7.

The assembly code example returns the TCNTn value in the r17:r16 register pair.
It is important to notice that accessing 16-bit registers are atomic operations. If aninterrupt occurs between the two instructions accessing the 16-bit register and theinterrupt code updates the temporary register by accessing the same or any other of the
16-bit Timer Registers, then the result of the access outside the interrupt will becorrupted. Therefore the main code must disable the interrupts during the 16-bit accesswhen both the main code and the interrupt code update the temporary register.
The following code examples show how to do an atomic read of the TCNTn Register
contents. Reading any of the OCRnA/B/C or ICRn Registers can be done by using thesame principle.
The assembly code example returns the TCNTn value in the r17:r16 register pair.
(1)

Assembly Code Examples
TIM16_ReadTCNTn:; Save global interrupt flagin r18,SREG; Disable interrupts
cli; Read TCNTn into r17:r16
in r16,TCNTnL
in r17,TCNTnH; Restore global interrupt flagout SREG,r18
ret

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(1)C Code Examples
unsigned int TIM16_ReadTCNTn( void ){unsigned char sreg;
unsigned int i;/* Save global interrupt flag */sreg = SREG;/* Disable interrupts */__disable_interrupt();/* Read TCNTn into i */i = TCNTn;/* Restore global interrupt flag */SREG = sreg;
return i;}
Notes:

1. See "About Code Examples" on page 7 .

The following code examples show how to do an atomic write of the TCNTn Register
contents. Writing any of the OCRnA/B/C or ICRn Registers can be done by using thesame principle.
The assembly code example requires that the r17:r16 register pair contains the value tobe written to TCNTn.
(1)

Assembly Code Examples
TIM16_WriteTCNTn:; Save global interrupt flagin r18,SREG; Disable interrupts
cli; Set TCNTn to r17:r16
out TCNTnH,r17
out TCNTnL,r16; Restore global interrupt flagout SREG,r18
ret

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C Code Examples
void TIM16_WriteTCNTn( unsigned int i ){unsigned char sreg;
unsigned int i;/* Save global interrupt flag */sreg = SREG;/* Disable interrupts */__disable_interrupt();/* Set TCNTn to i */TCNTn = i;/* Restore global interrupt flag */SREG = sreg;}
Notes:

1. See "About Code Examples" on page 7 .

18.3.1 Reusing the Temporary High Byte Register
If writing to more than one 16-bit register where the high byte is the same for all
registers written, then the high byte only needs to be written once. However note thatthe same rule of atomic operation described previously also applies in this case.

18.4 Timer/Counter Clock Sources
The Timer/Counter can be clocked by an internal or an external clock source. The clock
source is selected by the Clock Select logic which is controlled by the Clock Select(CSn2:0) bits located in the Timer/Counter control Register B (TCCRnB). For details on
clock sources and prescaler, see "Timer/Counter 0, 1, 3, 4, and 5 Prescaler" on page304.

18.5 Counter Unit
The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directionalcounter unit. The following figure shows a block diagram of the counter and its
surroundings.
Figure 18-2. Counter Unit Block Diagram
DATA BUS (8-bit)
TOVn(Int.Req.)
TEMP (8-bit)
Clock SelectCount
TCNTnH (8-bit)

TCNTnL (8-bit)

TCNTn (16-bit Counter)

Clear
Direction

Control Logic

clkTn

Edge
Detector

Tn( From Prescaler )TOP

BOTTOM

Signal description (internal signals):Count

Increment or decrement TCNTn by 1;

Direction

Select between increment and decrement;

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ClearClear TCNTn (set all bits to zero);clkTnTimer/Counter clock;TOP

Signalize that TCNTn has reached maximum value;

BOTTOM

Signalize that TCNTn has reached minimum value (zero);

The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High(TCNTnH) contains the upper eight bits of the counter and Counter Low (TCNTnL)
contains the lower eight bits. The TCNTnH Register can only be indirectly accessed by
the CPU. When the CPU does an access to the TCNTnH I/O location, the CPU
accesses the high byte temporary register (TEMP). The temporary register is updatedwith the TCNTnH value when the TCNTnL is read and TCNTnH is updated with thetemporary register value when TCNTnL is written. This allows the CPU to read or write
the entire 16-bit counter value within one clock cycle via the 8-bit data bus. It is
important to notice that there are special cases of writing to the TCNTn Register giving
unpredictable results when the counter is running. These special cases are described in
the sections of their importance.
Depending on the mode of operation, the counter is cleared, incremented or
decremented at each timer clock (clkTn). The clkTn can be generated from an external orinternal clock source selected by the Clock Select bits (CSn2:0). The timer is stopped
when no clock source is selected (CSn2:0 = 0). However, the TCNTn value can beaccessed by the CPU independent of whether clkTn is present or not. A CPU write
overrides (has priority over) all counter clear or count operations.
The counting sequence is determined by the settings of the Waveform Generation
mode bits (WGMn3:0) located in the Timer/Counter Control Registers A and B(TCCRnA and TCCRnB). There are close connections between how the counterbehaves (counts) and how waveforms are generated on the Output Compare outputs
OCnx. For more details about advanced counting sequences and waveform generation,
see "Modes of Operation" on page 256.
The Timer/Counter Overflow Flag (TOVn) is set according to the mode of operation
selected by the WGMn3:0 bits. TOVn can be used for generating a CPU interrupt.

18.6 Input Capture Unit
The Timer/Counter incorporates an input capture unit that can capture external eventsand give them a time-stamp indicating time of occurrence. The external signal indicating
an event, or multiple events, can be applied via the ICPn pin or alternatively, for theTimer/Counter1 only, via the Analog Comparator unit. The time-stamps can then be
used to calculate frequency, duty-cycle and other features of the signal applied.
Alternatively the time-stamps can be used for creating a log of the events.
The Input Capture unit is illustrated by the block diagram shown in Figure 18-3. The
elements of the block diagram not direct parts of the input capture unit are gray shaded.
The small “n” in register and bit names indicates the Timer/Counter number.
A capture will be triggered when a change of the logic level (an event) occurs on the
Input Capture Pin (ICPn), or alternatively on the analog Comparator output (ACO), andthis change matches the setting of the edge detector. When a capture is triggered, the16-bit value of the counter (TCNTn) is written to the Input Capture Register (ICRn). The
Input Capture Flag (ICFn) is set at the same system clock as the TCNTn value iscopied into ICRn Register. If enabled (TICIEn = 1), the input capture flag generates aninput capture interrupt. The ICFn flag is automatically cleared when the interrupt is
executed. Alternatively the ICFn flag can be software-cleared by writing a logical one toits I/O bit location.

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Figure 18-3. Input Capture Unit Block Diagram

DATA BUS (8-bit)

TEMP (8-bit)

ICRnH (8-bit)
WRITE

ICRnL (8-bit)

TCNTnH (8-bit)

ICRn (16-bit Register)ACO*
AnalogComparator

ACIC*

TCNTnL (8-bit)

TCNTn (16-bit Counter)

ICNC

ICES

Noise
CancelerEdge
Detector

ICFn (Int.Req.)

ICPn

Note:

1. The Analog Comparator Output (ACO) can only trigger the Timer/Counter1 ICP –not Timer/Counter3, 4 or 5.

Reading the 16-bit value in the Input Capture Register (ICRn) is done by first reading
the low byte (ICRnL) and then the high byte (ICRnH). When the low byte is read thehigh byte is copied into the high byte Temporary Register (TEMP). The CPU will accessthe TEMP Register when reading the ICRnH I/O location.
The ICRn Register can only be written when using a Waveform Generation mode thatutilizes the ICRn Register for defining the counter’s TOP value. In these cases the
Waveform Generation mode (WGMn3:0) bits must be set before the TOP value can be
written to the ICRn Register. When writing the ICRn Register the high byte must be
written to the ICRnH I/O location before the low byte is written to ICRnL.
For more information on how to access the 16-bit registers refer to "Accessing 16-bit
Registers" on page 246.
18.6.1 Input Capture Trigger Source
The main trigger source for the input capture unit is the Input Capture Pin (ICPn).
Timer/Counter1 can alternatively use the analog comparator output as trigger source forthe input capture unit. The Analog Comparator is selected as trigger source by setting
the analog Comparator Input Capture (ACIC) bit in the Analog Comparator Control andStatus Register (ACSR). Be aware that changing trigger source can trigger a capture.
The input capture flag must therefore be cleared after the change.
Both the Input Capture Pin (ICPn) and the Analog Comparator output (ACO) inputs are
sampled using the same technique as for the Tn pin (Figure 19-1 on page 304). Theedge detector is also identical. However, when the noise canceller is enabled,
additional logic is inserted before the edge detector increasing the delay by four system
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clock cycles. Note that the input of the noise canceller and edge detector is always
enabled unless the Timer/Counter is set in a Waveform Generation mode that uses
ICRn to define TOP.
An input capture can be software-triggered by controlling the port of the ICPn pin.
18.6.2 Noise Canceller
The noise canceller improves noise immunity by using a simple digital filtering scheme.
The noise canceller input is monitored over four samples and all four must be equal forchanging the output that in turn is used by the edge detector.
The noise canceller is enabled by setting the Input Capture Noise Canceller (ICNCn) bitin Timer/Counter Control Register B (TCCRnB). When enabled the noise canceller
introduces additional four system clock cycles of delay from a change applied to the
input to the update of the ICRn Register. The noise canceller uses the system clock andis therefore not affected by the prescaler.
18.6.3 Using the Input Capture Unit
The main challenge when using the Input Capture unit is to assign enough processor
capacity for handling the incoming events. The time between two events is critical. The
ICRn will be overwritten with a new value if the processor has not read the captured
value in the ICRn Register before the next event occurs. In this case the result of thecapture will be incorrect.
When using the Input Capture interrupt, the ICRn Register should be read as early in
the interrupt handler routine as possible. Even though the Input Capture interrupt has
relatively high priority, the maximum interrupt response time is dependent on the
maximum number of clock cycles it takes to handle any of the other interrupt requests.
It is not recommended to use the Input Capture unit in any mode of operation where theTOP value (resolution) is actively changed while counting.
Measurement of the duty cycle of an external signal requires that the trigger edge ischanged after each capture. Changing the edge sensing must be done as early as
possible after the ICRn Register has been read. After a change of the edge, the Input
Capture Flag (ICFn) must be cleared by software (writing a logical one to the I/O bit
location). For measuring frequency only, the clearing of the ICFn Flag is not required (ifan interrupt handler is used).

18.7 Output Compare Units
The 16-bit comparator continuously compares TCNTn with the Output Compare
Register (OCRnx). If TCNTn equals OCRnx the comparator signals a match. A match
will set the Output Compare Flag (OCFnx) at the next clock cycle of the timer. If
enabled (OCIEnx = 1), the Output Compare Flag generates an Output Compareinterrupt. The OCFnx Flag is automatically cleared when the interrupt is executed.
Alternatively the OCFnx Flag can be software-cleared by writing a logical one to its I/O
bit location. The Waveform Generator uses the match signal to generate an output
according to the Waveform Generation mode bits (WGMn3:0) and Compare Output
mode bits (COMnx1:0). The TOP and BOTTOM signals are used by the Waveform
Generator for handling the special cases of the extreme values in some modes ofoperation (see "Modes of Operation" on page 256).
A special feature of Output Compare unit A allows it to define the Timer/Counter TOP
value i.e., the counter resolution. In addition to the counter resolution, the TOP value
defines the period time for waveforms generated by the Waveform Generator.

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Figure 18-4 shows a block diagram of the Output Compare unit. The small “n” in theregister and bit names indicates the device number (n = Timer/Counter n), and the “x”
indicates Output Compare unit A, B or C. The elements of the block diagram not direct
parts of the Output Compare unit are gray shaded.
Figure 18-4. Output Compare Unit Block Diagram
DATA BUS (8-bit)

TEMP (8-bit)

OCRnxH Buf. (8-bit)

OCRnxL Buf. (8-bit)

TCNTnH (8-bit)

OCRnx Buffer (16-bit Register)

OCRnxH (8-bit)

TCNTnL (8-bit)

TCNTn (16-bit Counter)

OCRnxL (8-bit)

OCRnx (16-bit Register)= (16-bit Comparator )OCFnx (Int.Req.)TOP
BOTTOM

Waveform Generator

WGMn3:0

OCnx

COMnx1:0

The OCRnx Register is double buffered when using any of the twelve Pulse Width
Modulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modesof operation, the double buffering is disabled. The double buffering synchronizes the
update of the OCRnx Compare Register to either TOP or BOTTOM of the counting
sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical
PWM pulses, thereby making the output glitch-free.
The OCRnx Register access may seem complex, but this is not the case. When the
double buffering is enabled, the CPU has access to the OCRnx Buffer Register. If
double buffering is disabled the CPU will access the OCRnx directly. The content of the
OCR1x (Buffer or Compare) Register is only changed by a write operation (theTimer/Counter does not update this register automatically as the TCNT1 and ICR1Register). Therefore OCR1x is not read via the high byte temporary register (TEMP).
However, it is a good practice to read the low byte first similar to accessing other 16-bit
registers. Writing the OCRnx Registers must be done via the TEMP Register since thecompare of all 16 bits is done continuously. The high byte (OCRnxH) has to be written
first. The TEMP Register will be updated with the value written by the CPU to the highbyte I/O location. Then when the low byte (OCRnxL) is written to the lower eight bits,
the high byte will be copied into the upper 8-bits of either the OCRnx buffer or OCRnx
Compare Register in the same system clock cycle.
For more information of how to access the 16-bit registers refer to "Accessing 16-bit
Registers" on page 246.

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18.7.1 Force Output Compare
In non-PWM Waveform Generation modes, the match output of the comparator can beforced by writing a one to the Force Output Compare (FOCnx) bit. Forcing compare
match will not set the OCFnx Flag or reload/clear the timer, but the OCnx pin will be
updated as if a real compare match had occurred (the COMn1:0 bits settings define
whether the OCnx pin is set, cleared or toggled).
18.7.2 Compare Match Blocking by TCNTn Write
All CPU writes to the TCNTn Register will block any compare match that occurs in thenext clock cycle of the timer even when the timer is stopped. This feature allows OCRnx
to be initialized to the same value as TCNTn without triggering an interrupt when theTimer/Counter clock is enabled.
18.7.3 Using the Output Compare Unit
Since writing TCNTn in any mode of operation will block all compare matches for one
timer clock cycle, there are risks involved when changing TCNTn using any of the
Output Compare channels, independent of whether the Timer/Counter is running or not.
If the value written to TCNTn equals the OCRnx value, the compare match will bemissed resulting in incorrect waveform generation. Do not write the TCNTn equal to
TOP in PWM modes with variable TOP values. The compare match for the TOP will beignored and the counter will continue to 0xFFFF. Similarly, do not write the TCNTnvalue equal to BOTTOM when the counter is down-counting.
The setup of the OCnx should be performed before setting the Data Direction Registerfor the port pin to output. The easiest way of setting the OCnx value is to use the Force
Output Compare (FOCnx) strobe bits in Normal mode. The OCnx Register keeps its
value even when changing between Waveform Generation modes.
Be aware that the COMnx1:0 bits are not double buffered together with the compare
value. A change of the COMnx1:0 bits will immediately take effect.

18.8 Compare Match Output Unit
The Compare Output mode (COMnx1:0) bits have two functions. The Waveform
Generator uses the COMnx1:0 bits for defining the Output Compare (OCnx) state at thenext compare match. Secondly the COMnx1:0 bits control the OCnx pin output source.
Figure 18-5 shows a simplified schematic of the logic affected by the COMnx1:0 bit
setting. The I/O Registers, I/O bits and I/O pins in the figure are shown in bold. Only theparts of the general I/O Port Control Registers (DDR and PORT) that are affected by
the COMnx1:0 bits are shown. When referring to the OCnx state, the reference is to theinternal OCnx Register and not to the OCnx pin. After a system reset the OCnx
Register will have a value of “0”.
The general I/O port function is overridden by the Output Compare (OCnx) from the
Waveform Generator if either of the COMnx1:0 bits are set. However, the OCnx pin
direction (input or output) is still controlled by the Data Direction Register (DDR) for the
port pin. The Data Direction Register bit for the OCnx pin (DDR_OCnx) must be set as
output before the OCnx value is visible on the pin. The port override function is
generally independent of the Waveform Generation mode, but there are some
exceptions. Refer to Table 18-2, Table 18-3 and Table 18-4 on page 256 for details.
The design of the Output Compare pin logic allows initialization of the OCnx state
before the output is enabled. Note that some COMnx1:0 bit settings are reserved forcertain modes of operation (see section "Register Description" on page 266).
The COMnx1:0 bits have no effect on the Input Capture unit.
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Figure 18-5. Compare Match Output Unit, Schematic

COMnx1

Waveform
Generator

COMnx0
FOCnx

D

Q
1

OCnx

DATA BUS

D

0

OCnx
Pin

Q

PORT
D

Q

DDR
clk I/O

18.8.1 Compare Output Mode and Waveform Generation
The Waveform Generator uses the COMnx1:0 bits differently in normal, CTC and PWM
modes. A setting of COMnx1:0 = 0 tells the Waveform Generator in all modes that noaction on the OCnx Register is to be performed on the next compare match. For
compare output actions in the non-PWM modes refer to Table 18-2. For fast PWM
mode refer to Table 18-3 and for phase-correct and phase-and-frequency-correct PWM
refer to Table 18-4.
A change of the COMnx1:0 bits state will have effect at the first compare match after
the bits are written. For non-PWM modes, the action can be forced to have immediate
effect by using the FOCnx strobe bits.
Table 18-2 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to anormal or a CTC mode (non-PWM).
Table 18-2. Compare Output Mode, non-PWM
COMnA1COMnB1
COMnC1COMnA0COMnB0COMnC000Normal port operation, OCnA/OCnB/OCnC disconnected.

0

1

Toggle OCnA/OCnB/OCnC on compare match.

10

Clear OCnA/OCnB/OCnC on compare match (set output to lowlevel).

1

1

Set OCnA/OCnB/OCnC on compare match (set output to highlevel).

Description

Table 18-3 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to thefast PWM mode.

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Table 18-3. Compare Output Mode, Fast PWM
COMnA1COMnB1
COMnC1COMnA0COMnB0COMnC000Normal port operation, OCnA/OCnB/OCnC disconnected.

0

1

WGM13:0 = 14 or 15: Toggle OC1A on Compare Match, OC1B and
OC1C disconnected (normal port operation). For all other WGM1
settings, normal port operation, OC1A/OC1B/OC1C disconnected.

10

Clear OCnA/OCnB/OCnC on compare match; set
OCnA/OCnB/OCnC at BOTTOM (non-inverting mode).

1

1

Set OCnA/OCnB/OCnC on compare match, clear
OCnA/OCnB/OCnC at BOTTOM (inverting mode).

Note:

Description

1. A special case occurs when OCRnA/OCRnB/OCRnC equals TOP and
COMnA1/COMnB1/COMnC1 is set. In this case the compare match is ignored, but
the set or clear is done at BOTTOM. See "Fast PWM Mode" on page 258 for moredetails.

Table 18-4 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to thephase correct and phase and frequency correct PWM mode.
Table 18-4. Compare Output Mode, Phase Correct and Phase/Frequency Correct
PWM
COMnA1COMnB1
COMnC1COMnA0COMnB0COMnC000Normal port operation, OCnA/OCnB/OCnC disconnected.

0

1

WGM13:0 =9 or 11: Toggle OC1A on Compare Match, OC1B and
OC1C disconnected (normal port operation). For all other WGM1
settings, normal port operation, OC1A/OC1B/OC1C disconnected.

10

Clear OCnA/OCnB/OCnC on compare match when up-counting.
Set OCnA/OCnB/OCnC on compare match when down-counting.

1

1

Set OCnA/OCnB/OCnC on compare match when up-counting.
Clear OCnA/OCnB/OCnC on compare match when down-counting.

Note:

Description

1. A special case occurs when OCRnA/OCRnB/OCRnC equals TOP and
COMnA1/COMnB1/COMnC1 is set. See "Phase and Frequency Correct PWM
Mode" on page 262 for more details.

18.9 Modes of Operation
The mode of operation i.e., the behavior of the Timer/Counter and the Output Compare
pins, is defined by the combination of the Waveform Generation mode (WGMn3:0) andthe Compare Output mode (COMnx1:0) bits. The Compare Output mode bits do notaffect the counting sequence, but the Waveform Generation mode bits do. The
COMnx1:0 bits control whether the PWM output generated should be inverted or not(inverted or non-inverted PWM). For non-PWM modes the COMnx1:0 bits control if theoutput should be set, cleared or toggle at a compare match (See "Compare Match
Output Unit" on page 254)

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Table 18-5. Waveform Generation Mode Bit Description
WGMn0)(PWMn0)Timer/Counter
Mode of Operation

TOP

Update of
OCRnx at

Mode

WGMn3

WGMn2
(CTCn)

0

0

0

0

0

Normal0xFFFF

Immediate

MAX

1

0

0

0

1

PWM, Phase Correct, 8-bit

0x00FFTOP

BOTTOM

2

0

0

1

0

PWM, Phase Correct, 9-bit

0x01FFTOP

BOTTOM

3

0

0

1

1

PWM, Phase Correct, 10-bit

0x3FF

TOP

BOTTOM

4

0

1

0

0

CTC

OCRnA

Immediate

MAX

5

0

1

0

1

Fast PWM, 8-bit

0x00FF

BOTTOM

TOP

6

0

1

1

0

Fast PWM, 9-bit

0x01FF

BOTTOM

TOP

7

0

1

1

1

Fast PWM, 10-bit

0x03FF

BOTTOM

TOP

8

1

0

0

0

PWM, Phase and Frequency
Correct

ICRn

BOTTOM

BOTTOM

9

1

0

0

1

PWM, Phase and Frequency
Correct

OCRnA

BOTTOM

BOTTOM

10

1

0

1

0

PWM, Phase Correct

ICRn

TOP

BOTTOM

11

1

0

1

1

PWM, Phase Correct

OCRnA

TOP

BOTTOM

12

1

1

0

0

CTC

ICRn

Immediate

MAX

13

1

1

0

1

(Reserved)

–

–

–

14

1

1

1

0

Fast PWM

ICRn

BOTTOM

TOP

15

1

1

1

1

Fast PWM

OCRnA

BOTTOMTOP

Notes:WGMn1(PWMn1)(1)

TOVn Flag
Set on1. The CTCn and PWMn1:0 bit definition names are obsolete. Use the WGMn2:0 definitions. However, the functionality
and location of these bits are compatible with previous versions of the timer.

For detailed timing information refer to "Timer/Counter Timing Diagrams" on page 264.
18.9.1 Normal Mode
The simplest mode of operation is the Normal mode (WGMn3:0 = 0). In this mode thecounting direction is always up (incrementing) and no counter clear is performed. The
counter simply overruns when it passes its maximum 16-bit value (MAX = 0xFFFF) andthen restarts from the BOTTOM (0x0000). In normal operation the Timer/Counter
Overflow Flag (TOVn) will be set in the same timer clock cycle as the TCNTn becomesthzero. In this case the TOVn Flag behaves like a 17 bit, except that it is only set and not
cleared. However the timer resolution can be increased by software when combinedwith the timer overflow interrupt that automatically clears the TOVn Flag. There are no
special cases to consider in the Normal mode. A new counter value can be written
anytime.
The Input Capture unit is easy to use in Normal mode. However it is important to notethat the maximum interval between the external events must not exceed the resolutionof the counter. The timer overflow interrupt or the prescaler must be used to extend theresolution for the capture unit if the intervals between events are too long.
The Output Compare units can be used to generate interrupts at some given time.
Using the Output Compare to generate waveforms in Normal mode is notrecommended because this will occupy too much CPU time.
18.9.2 Clear Timer on Compare Match (CTC) ModeIn Clear Timer on Compare (CTC) mode (WGMn3:0 = 4 or 12), the OCRnA or ICRn
Register are used to manipulate the counter resolution. In CTC mode the counter is
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cleared to zero when the counter value (TCNTn) matches either the OCRnA (WGMn3:0= 4) or the ICRn (WGMn3:0 = 12). The OCRnA or ICRn define the top value for thecounter, hence also its resolution. This mode allows greater control of the compare
match output frequency. It also simplifies the operation of counting external events.
The timing diagram for the CTC mode is shown in the following figure. The countervalue (TCNTn) increases until a compare match occurs with either OCRnA or ICRn,
and then counter (TCNTn) is cleared.
Figure 18-6. CTC Mode Timing Diagram
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set(Interrupt on TOP)

TCNTn

OCnA
(Toggle)Period(COMnA1:0 = 1)

1

2

3

4

Each time the counter reaches the TOP value an interrupt can be generated by either
the OCFnA or ICFn Flag according to the register used to define the TOP value. If theinterrupt is enabled, the interrupt handler routine can be used for updating the TOP
value. However, changing TOP to a value close to BOTTOM when the counter isrunning with no or a low prescaler value must be done with care since the CTC mode
does not have the double buffering feature. The counter will miss the compare match if
the new value written to OCRnA or ICRn is lower than the current value of TCNTn. The
counter will then have to count to its maximum value (0xFFFF) and wrap aroundstarting at 0x0000 before the compare match can occur. In many cases this feature is
not desirable. The fast PWM mode is available as an alternative using OCRnA for
defining TOP (WGMn3:0 = 15). The OCRnA then will be double buffered.
For generating a waveform output in CTC mode, the OCnA output can be set to toggle
its logical level on each compare match by setting the Compare Output mode bits totoggle mode (COMnA1:0 = 1). The OCnA value will not be visible on the port pin unlessthe data direction for the pin is set to output (DDR_OCnA = 1). The waveformgenerated will have a maximum frequency of fOCnA = fclk_I/O/2 when OCRnA is set to zero
(0x0000). The waveform frequency is given by the following equation:f OCnA =f CLK _ I / O
2 ⋅ N ⋅ (1 + OCRnA)

The N variable represents the prescaler factor (1, 8, 64, 256, or 1024).
As for the Normal mode of operation, the TOVn Flag is set in the same clock cycle ofthe timer when the counter changes from MAX to 0x0000.
18.9.3 Fast PWM Mode
The fast Pulse Width Modulation (PWM) mode (WGMn3:0 = 5, 6, 7, 14 or 15) provides
a high frequency PWM waveform generation option. The fast PWM differs from theother PWM options by its single-slope operation. The counter counts from BOTTOM to
TOP then restarts from BOTTOM. In non-inverting Compare Output mode, the Output
Compare (OCnx) is cleared on the compare match between TCNTn and OCRnx, and258

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OCnx is set at BOTTOM. In inverting Compare Output mode output is set on compare
match and cleared at BOTTOM. Due to the single-slope operation, the operating
frequency of the fast PWM mode can be twice as high as the phase-correct and phaseand frequency correct PWM modes that use dual-slope operation. This high frequency
makes the fast PWM mode well suited for power regulation, rectification and DAC
applications. High frequency allows physically small sized external components (coils,
capacitors), hence reducing total system cost.
The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either
ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to
0x0003), and the maximum resolution is 16-bit (ICRn or OCRnA set to MAX). The PWM
resolution RFPWM in bits can be calculated with the following equation:

R FPWM =log(TOP + 1)
log(2)

In fast PWM mode the counter is incremented until the counter value matches either
one of the fixed values 0x00FF, 0x01FF or 0x03FF (WGMn3:0 = 5, 6 or 7), the value in
ICRn (WGMn3:0 = 14) or the value in OCRnA (WGMn3:0 = 15). The counter is thencleared at the following timer clock cycle. The timing diagram for the fast PWM mode isshown in Figure 18-7. The figure shows fast PWM mode when OCRnA or ICRn is used
to define TOP. The TCNTn value is in the timing diagram shown as a histogram forillustrating the single-slope operation. The diagram includes non-inverted and inverted
PWM outputs. The small horizontal line marks on the TCNTn slopes represent compare
matches between OCRnx and TCNTn. The OCnx Interrupt Flag will be set when acompare match occurs.
Figure 18-7. Fast PWM Mode Timing Diagram
OCRnx / TOP Update
and TOVn Interrupt Flag
Set and OCnA Interrupt
Flag Set or ICFn
Interrupt Flag Set(Interrupt on TOP)

TCNTn

OCnx

(COMnx1:0 = 2)

OCnx

(COMnx1:0 = 3)

Period

1

2

3

4

5

6

7

8

The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches TOP. In
addition the OCnA or ICFn Flag is set at the same timer clock cycle as TOVn is set
when either OCRnA or ICRn is used to define the TOP value. If one of the interrupts areenabled, the interrupt handler routine can be utilized for updating the TOP and compare
values.
When changing the TOP value the program must ensure that the new TOP value ishigher or equal to the value of all of the Compare Registers. A compare match will
never occur between the TCNTn and the OCRnx if the TOP value is lower than any of
the Compare Registers. Note that when working with fixed TOP values the unused bits
are masked to zero when any of the OCRnx Registers are written.

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The procedure for updating ICRn differs from updating OCRnA when used for defining
the TOP value. The ICRn Register is not double buffered. This means that if ICRn ischanged to a low value while the counter is running with no or a low prescaler value,
there is a risk that the newly written ICRn value is lower than the current value of
TCNTn. In consequence the counter will miss the compare match at the TOP value.
The counter must then count to the MAX value (0xFFFF) and wrap around starting at
0x0000 before the compare match can occur. The OCRnA Register is double bufferedthough. This feature allows writing the OCRnA I/O location at anytime. When the
OCRnA I/O location is written the new value will be put first into the OCRnA Buffer
Register. The OCRnA Compare Register will then be updated with the value in the
Buffer Register at the next clock cycle of the timer when TCNTn matches TOP. The
update is done at the same timer clock cycle as the TCNTn is cleared and the TOVn
Flag is set.
The definition of TOP with the ICRn Register works well for fixed TOP values.
Combined with ICRn, the OCRnA Register is free to be used for generating a PWM
output on OCnA. However, if the base PWM frequency is actively changed (bymodifying the TOP value), working with the OCRnA as TOP is clearly a better choice
due to its double buffer feature.
In fast PWM mode the compare units allow the generation of PWM waveforms on the
OCnx pins. Setting the COMnx1:0 bits to 2 will produce a non-inverted PWM and an
inverted PWM output can be generated by setting the COMnx1:0 to 3 (see Table 18-3
on page 256). The actual OCnx value will only be visible on the port pin if the data
direction of the port pin is set to output (DDR_OCnx). The PWM waveform is generated
by setting (or clearing) the OCnx Register at the compare match between OCRnx and
TCNTn, and by clearing (or setting) the OCnx Register at the timer clock cycle thecounter is cleared (changes from TOP to BOTTOM).
The PWM frequency of the output fOCnxPWM can be calculated with the following
equation:f OCnxPWM =f clk _ I / O
N ⋅ (1 + TOP)The N variable represents the prescaler divider (1, 8, 64, 256 or 1024).
The extreme values for the OCRnx Register represent special cases when generating a
PWM waveform output in the fast PWM mode. If the OCRnx is set equal to BOTTOM(0x0000), the output will be a narrow spike for each TOP+1 timer clock cycle. Setting
the OCRnx equal to TOP will result in a constant high or low output (depending on thepolarity of the output set by the COMnx1:0 bits.)
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achievedby setting OCnA to toggle its logical level on each compare match (COMnA1:0 = 1).
This applies only if OCR1A is used to define the TOP value (WGM13:0 = 15). The
waveform generated will have a maximum frequency of fOCnA = fclk_I/O/2 when OCRnA is
set to zero (0x0000). This feature is similar to the OCnA toggle in CTC mode, except
the double buffer feature of the Output Compare unit is enabled in the fast PWM mode.
18.9.4 Phase Correct PWM Mode
The phase correct Pulse Width Modulation (PWM) mode (WGMn3:0 = 1, 2, 3, 10 or 11)
provides a high resolution phase correct PWM waveform generation option. The phasecorrect PWM mode is, like the phase and frequency correct PWM mode, based on adual-slope operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP
and then from TOP to BOTTOM. In non-inverting Compare Output mode, the Output
Compare (OCnx) is cleared on the compare match between TCNTn and OCRnx while
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up-counting, and set on the compare match while down-counting. In inverting Output
Compare mode, the operation is inverted. The dual-slope operation has a lower
maximum operation frequency than single slope operation. However these modes are
preferred for motor control applications due to the symmetric feature of the dual-slope
PWM modes.
The PWM resolution for the phase correct PWM mode can be fixed to 8, 9 or 10 bit, orbe defined by either ICRn or OCRnA. The minimum resolution allowed is 2 bit (ICRn or
OCRnA set to 0x0003), and the maximum resolution is 16-bit (ICRn or OCRnA set toMAX). The PWM resolution RPCPWM in bits can be calculated with the following equation:

RPCPWM =log(TOP + 1)
log(2)In phase correct PWM mode the counter is incremented until the counter value matches
either one of the fixed values 0x00FF, 0x01FF or 0x03FF (WGMn3:0 = 1, 2, or 3), thevalue in ICRn (WGMn3:0 = 10) or the value in OCRnA (WGMn3:0 = 11). The counterhas then reached the TOP and changes the count direction. The TCNTn value will beequal to TOP for one timer clock cycle. The timing diagram for the phase correct PWM
mode is shown on Figure 18-8 below. The figure shows phase correct PWM mode
when OCRnA or ICRn is used to define TOP. The TCNTn value is shown in the timing
diagram as a histogram illustrating the dual-slope operation. The diagram includes noninverted and inverted PWM outputs. The small horizontal line marks on the TCNTnslopes represent compare matches between OCRnx and TCNTn. The OCnx Interrupt
Flag will be set when a compare match occurs.
Figure 18-8. Phase Correct PWM Mode Timing Diagram
OCRnx/TOP Update and
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set(Interrupt on TOP)TOVn Interrupt Flag Set(Interrupt on Bottom)

TCNTn

OCnx

(COMnx1:0 = 2)

OCnx

(COMnx1:0 = 3)

Period1

2

3

4

The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches
BOTTOM. When either OCRnA or ICRn is used for defining the TOP value, the OCnAor ICFn Flag is set accordingly at the same timer clock cycle as the OCRnx Registers
are updated with the double buffer value (at TOP). The Interrupt Flags can be used togenerate an interrupt each time the counter reaches the TOP or BOTTOM value.
When changing the TOP value the program must ensure that the new TOP value ishigher or equal to the value of all of the Compare Registers. If the TOP value is lower
than any of the Compare Registers, a compare match will never occur between the
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TCNTn and the OCRnx. Note that when working with fixed TOP values, the unused bits
are masked to zero when any of the OCRnx Registers are written. As the third period
shown in Figure 18-8 illustrates, changing the TOP actively while the Timer/Counter isrunning in the phase correct mode can result in an asymmetrical output. The reason forthis can be found in the update time of the OCRnx Register. Since the OCRnx update
occurs at TOP, the PWM period starts and ends at TOP. This implies that the length of
the falling slope is determined by the previous TOP value, while the length of the risingslope is determined by the new TOP value. When these two values are not equal thetwo slopes of the period will differ in length. The difference in length gives theasymmetrical result of the output.
It is recommended to use the phase and frequency correct mode instead of the phasecorrect mode when changing the TOP value while the Timer/Counter is running. Whenusing a static TOP value there are practically no differences between the two modes ofoperation.
In phase correct PWM mode, the compare units allow generating PWM waveforms on
the OCnx pins. Setting the COMnx1:0 bits to 2 will produce a non-inverted PWM. An
inverted PWM output can be generated by setting the COMnx1:0 to 3 (see Table 18-4
on page 256). The actual OCnx value will only be visible on the port pin if the data
direction of the port pin is set to output (DDR_OCnx). The PWM waveform is generated
by setting (or clearing) the OCnx Register at the compare match between OCRnx and
TCNTn when the counter increments, and by clearing (or setting) the OCnx Register atcompare match between OCRnx and TCNTn when the counter decrements. The PWM
frequency of the output fOCnxPCPWM when using phase-correct PWM can be calculatedwith the following equation:f OCnxPCPWM =f clk _ I / O
2 ⋅ N ⋅ TOP)The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCRnx Register represent special cases when generating a
PWM waveform output in the phase correct PWM mode. If the OCRnx is set equal to
BOTTOM the output will be continuously low and if set equal to TOP the output will be
continuously high for non-inverted PWM mode. For inverted PWM the output will havethe opposite logic values. If OCR1A is used to define the TOP value (WGM13:0 = 11)
and COM1A1:0 = 1, the OC1A output will toggle with a 50% duty cycle.
18.9.5 Phase and Frequency Correct PWM Mode
The phase and frequency correct Pulse Width Modulation (PWM) mode (WGMn3:0 = 8or 9) provides a high resolution phase and frequency correct PWM waveformgeneration option. The phase and frequency correct PWM mode is, like the phasecorrect PWM mode, based on a dual-slope operation. The counter counts repeatedly
from BOTTOM (0x0000) to TOP and then from TOP to BOTTOM. In non-inverting
Compare Output mode, the Output Compare (OCnx) is cleared on the compare match
between TCNTn and OCRnx while up-counting, and set on the compare match while
down-counting. In inverting Compare Output mode, the operation is inverted. The dualslope operation gives a lower maximum operation frequency compared to the singleslope operation. However these modes are preferred for motor control applications dueto the symmetric feature of the dual-slope PWM modes.
The main difference between the phase correct and the phase and frequency correct
PWM mode is the time the OCRnx Register is updated by the OCRnx Buffer Register,(see Figure 18-8 on page 261 and Figure 18-9 on page 263).

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The PWM resolution for the phase and frequency correct PWM mode can be defined byeither ICRn or OCRnA. The minimum resolution allowed is 2 bit (ICRn or OCRnA set to
0x0003), and the maximum resolution is 16 bit (ICRn or OCRnA set to MAX). The PWM
resolution RPFCPWM in bits can be calculated with the following equation:

R PFCPWM =log(TOP + 1)
log(2)In phase and frequency correct PWM mode the counter is incremented until the countervalue matches either the value in ICRn (WGMn3:0 = 8), or the value in OCRnA(WGMn3:0 = 9). The counter has then reached TOP and changes the count direction.
The TCNTn value will be equal to TOP for one timer clock cycle. The timing diagram forthe phase correct and frequency correct PWM mode is shown in Figure 18-9 below.
The figure shows phase and frequency correct PWM mode when OCRnA or ICRn isused to define TOP. The TCNTn value is shown in the timing diagram as a histogramfor illustrating the dual-slope operation. The diagram includes non-inverted and inverted
PWM outputs. The small horizontal line marks on the TCNTn slopes represent compare
matches between OCRnx and TCNTn. The OCnx Interrupt Flag will be set when acompare match occurs.
Figure 18-9. Phase and Frequency Correct PWM Mode Timing Diagram
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set(Interrupt on TOP)

OCRnx/TOP Updateand
TOVn Interrupt Flag Set(Interrupt on Bottom)

TCNTn

OCnx

(COMnx1:0 = 2)

OCnx

(COMnx1:0 = 3)

Period1

2

3

4

The Timer/Counter Overflow Flag (TOVn) is set at the timer clock cycle when the
OCRnx Registers are updated with the double-buffered value (at BOTTOM). The OCnAor ICFn Flag is set after TCNTn has reached TOP when either OCRnA or ICRn is used
for defining the TOP value. The Interrupt Flags can then be used to generate aninterrupt each time the counter reaches the TOP or BOTTOM value.
When changing the TOP value the program must ensure that the new TOP value ishigher or equal to the value of all of the Compare Registers. If the TOP value is lower
than any of the Compare Registers, a compare match will never occur between the
TCNTn and the OCRnx.
As Figure 18-9 shows the output generated is, in contrast to the phase correct mode,
symmetrical in all periods. Since the OCRnx Registers are updated at BOTTOM, thelength of the rising and the falling slopes will always be equal. This gives symmetrical
output pulses and is therefore frequency correct.

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The definition of TOP with the ICRn Register works well when using fixed TOP values.
Combined with ICRn the OCRnA Register is available for generating a PWM output on
OCnA. However, if the base PWM frequency is actively changed by modifying the TOP
value, using the OCRnA as TOP is clearly a better choice due to its double buffer
feature.
In phase and frequency correct PWM mode, the compare units allow generating PWM
waveforms on the OCnx pins. Setting the COMnx1:0 bits to 2 will produce a noninverted PWM. An inverted PWM output can be generated by setting the COMnx1:0 to
3 (see Table 18-4 on page 256). The actual OCnx value will only be visible at the port
pin if the data direction of the port pin is set to output (DDR_OCnx). The PWM
waveform is generated by setting (or clearing) the OCnx Register at the compare match
between OCRnx and TCNTn when the counter increments, and by clearing (or setting)
the OCnx Register at compare match between OCRnx and TCNTn when the counter
decrements. The PWM frequency of the output fOCnxPFCPWM when using phase andfrequency correct PWM can be calculated with the following equation:f OCnxPFCPWM =f clk _ I / O
2 ⋅ N ⋅ TOP)The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCRnx Register represent special cases when generating a
PWM waveform output in the phase correct PWM mode. If the OCRnx is set equal to
BOTTOM the output will be continuously low and if set equal to TOP the output will be
set to high for non-inverted PWM mode. For inverted PWM the output will have theopposite logic values. If OCR1A is used to define the TOP value (WGM13:0 = 9) andCOM1A1:0 = 1, the OC1A output will toggle with a 50% duty cycle.

18.10 Timer/Counter Timing Diagrams
The Timer/Counter is a synchronous design and the timer clock (clkTn) is therefore
shown as a clock enable signal in the following figures. The figures include information
on when Interrupt Flags are set and when the OCRnx Register is updated with the
OCRnx buffer value (only for modes utilizing double buffering). Figure 18-10 shows atiming diagram for the setting of OCFnx.
Figure 18-10. Timer/Counter Timing Diagram, Setting of OCFnx, no Prescaling
clkI/O
clkTn(clkI/O /1)

TCNTn

OCRnx

OCRnx - 1

OCRnx

OCRnx + 1

OCRnx + 2

OCRnx Value

OCFnx

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Figure 18-11 shows the same timing data, but with the prescaler enabled.
Figure 18-11. Timer/Counter Timing Diagram, Setting of OCFnx with Prescaler(fclk_I/O/8)
clkI/O
clkTn(clkI/O /8)

TCNTn

OCRnx - 1

OCRnx

OCRnx + 1

OCRnx + 2

OCRnx Value

OCRnx

OCFnx

Figure 18-12 shows the count sequence close to TOP in various modes. When using
phase and frequency correct PWM mode the OCRnx Register is updated at BOTTOM.
The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP1 by BOTTOM+1 and so on. The same renaming applies for modes that set the TOVn
Flag at BOTTOM.
Figure 18-12. Timer/Counter Timing Diagram, no Prescaling
clkI/O
clkTn(clkI/O /1)

TCNTn(CTC and FPWM)

TCNTn(PC and PFC PWM)

TOP - 1TOP

BOTTOM

BOTTOM + 1

TOP - 1TOP

TOP - 1TOP - 2

TOVn (FPWM)
and ICFn (if used
as TOP)

OCRnx(Update at TOP)

Old OCRnx Value

New OCRnx Value

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Figure 18-13 shows the same timing data, but with the prescaler enabled.
Figure 18-13. Timer/Counter Timing Diagram with Prescaler (fclk_I/O/8)
clkI/O
clkTn(clkI/O/8)

TCNTn(CTC and FPWM)

TCNTn(PC and PFC PWM)

TOP - 1TOP

BOTTOM

BOTTOM + 1

TOP - 1TOP

TOP - 1TOP - 2

TOVn (FPWM)
and ICF n (if used
as TOP)

OCRnx

Old OCRnx Value(Update at TOP)New OCRnx Value

18.11 Register Description
18.11.1 TCCR1A – Timer/Counter1 Control Register A
Bit
NA ($80)

7

6

5

4

3

2

1

0

COM1A1 COM1A0 COM1B1 COM1B0 COM1C1 COM1C0 WGM11

Read/Write
Initial Value

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

WGM10

TCCR1A

RW
0• Bit 7:6 – COM1A1:0 - Compare Output Mode for Channel A
The COM1A1:0 bits control the output compare behavior of pin OC1A. If one or both of
the COM1A1:0 bits are written to one, the OC1A output overrides the normal portfunctionality of the I/O pin it is connected to. However note that the Data Direction
Register (DDR) bit corresponding to the OC1A pin must be set in order to enable theoutput driver. When the OC1A is connected to the pin, the function of the COM1A1:0
bits is dependent of the WGM13:0 bits setting. The following table shows the
COM1A1:0 bit functionality when the WGM13:0 bits are set to a normal or a CTC mode
(non-PWM). For the other functionality refer to section "Modes of Operation".
Table 18-6 COM1A Register Bits
Register Bits

Value

Description

COM1A1:00

Normal port operation, OCnA/OCnB/OCnC
disconnected.

1

Toggle OCnA/OCnB/OCnC on Compare
Match.

2

Clear OCnA/OCnB/OCnC on Compare
Match (set output to low level).

3

Set OCnA/OCnB/OCnC on Compare Match(set output to high level).

• Bit 5:4 – COM1B1:0 - Compare Output Mode for Channel B

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The COM1B1:0 bits control the output compare behavior of pin OC1B. If one or both of
the COM1B1:0 bits are written to one, the OC1B output overrides the normal portfunctionality of the I/O pin it is connected to. However note that the Data Direction
Register (DDR) bit corresponding to the OC1B pin must be set in order to enable theoutput driver. When the OC1A is connected to the pin, the function of the COM1B1:0
bits is dependent of the WGM13:0 bits setting. The following table shows theCOM1B1:0 bit functionality when the WGM13:0 bits are set to a normal or a CTC mode
(non-PWM). For the other functionality refer to section "Modes of Operation".
Table 18-7 COM1B Register Bits
Register Bits

Value

Description

COM1B1:00

Normal port operation, OCnA/OCnB/OCnC
disconnected.

1

Toggle OCnA/OCnB/OCnC on Compare
Match.

2

Clear OCnA/OCnB/OCnC on Compare
Match (set output to low level).

3

Set OCnA/OCnB/OCnC on Compare Match(set output to high level).

• Bit 3:2 – COM1C1:0 - Compare Output Mode for Channel C
The COM1C1:0 bits control the output compare behavior of pin OC1C. If one or both of
the COM1C1:0 bits are written to one, the OC1C output overrides the normal portfunctionality of the I/O pin it is connected to. However note that the Data Direction
Register (DDR) bit corresponding to the OC1C pin must be set in order to enable theoutput driver. When the OC1A is connected to the pin, the function of the COM1C1:0
bits is dependent of the WGM13:0 bits setting. The following table shows the
COM1C1:0 bit functionality when the WGM13:0 bits are set to a normal or a CTC mode
(non-PWM). For the other functionality refer to section "Modes of Operation".
Table 18-8 COM1C Register Bits
Register Bits

Value

COM1C1:00

Normal port operation, OCnA/OCnB/OCnC
disconnected.

Description

1

Toggle OCnA/OCnB/OCnC on Compare
Match.

2

Clear OCnA/OCnB/OCnC on Compare
Match (set output to low level).

3

Set OCnA/OCnB/OCnC on Compare Match(set output to high level).

• Bit 1:0 – WGM11:10 - Waveform Generation Mode
Combined with the WGM13:2 bits found in the TCCR1B Register, these bits control thecounting sequence of the counter, the source for maximum (TOP) counter value, andwhat type of waveform generation to be used. Modes of operation supported by theTimer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC)
mode, and three types of Pulse Width Modulation (PWM) modes. For more informationon the different modes see section "Modes of Operation".
Table 18-9 WGM1 Register Bits
Register Bits

Value

Description

WGM11:100x0

Normal mode of operation

0x1

PWM, phase correct, 8-bit

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Register Bits

Value

Description

0x2

PWM, phase correct, 9-bit

0x3

PWM, phase correct, 10-bit

0x4

CTC, TOP = OCRnA

0x5

Fast PWM, 8-bit

0x6

Fast PWM, 9-bit

0x7

Fast PWM, 10-bit

0x8

PWM, Phase and frequency correct, TOP =
ICRn

0x9

PWM, Phase and frequency correct, TOP =
OCRnA

0xA

PWM, Phase correct, TOP = ICRn

0xB

PWM, Phase correct, TOP = OCRnA

0xC

CTC, TOP = OCRnA

0xD

Reserved

0xE

Fast PWM, TOP = ICRn

0xF

Fast PWM, TOP = OCRnA

18.11.2 TCCR1B – Timer/Counter1 Control Register B
Bit

7

6

5

4

3

2

1

0

NA ($81)

ICNC1

ICES1

Res

WGM13

WGM12

CS12

CS11

CS10

Read/Write
Initial Value

RW
0

RW
0

R
0

RW
0

RW
0

RW
0

RW
0

RW
0

TCCR1B• Bit 7 – ICNC1 - Input Capture 1 Noise Canceller
Setting this bit (to one) activates the Input Capture Noise Canceler. When the Noise
Canceler is activated, the input from the Input Capture Pin (ICP1) is filtered. The filter
function requires four successive equal valued samples of the ICP1 pin for changing its
output. The input capture is therefore delayed by four Oscillator cycles when the noise
canceler is enabled.
• Bit 6 – ICES1 - Input Capture 1 Edge SelectThis bit selects which edge on the Input Capture Pin (ICP1) that is used to trigger acapture event. When the ICES1 bit is written to zero, a falling (negative) edge is usedas trigger. When the ICES1 bit is written to one, a rising (positive) edge will trigger thecapture. When a capture is triggered according to the ICES1 setting, the counter value
is copied into the Input Capture Register (ICR1). The event will also set the Input
Capture Flag (ICF1). This can be used to cause an Input Capture Interrupt, if thisinterrupt is enabled. When the ICR1 is used as TOP value (see description of the
WGM13:0 bits located in the TCCR1A and the TCCR1B Register), the ICP1 isdisconnected and consequently the input capture function is disabled.
• Bit 5 – Res - Reserved Bit
This bit is reserved for future use. A read access always will return zero. A write accessdoes not modify the content.
• Bit 4:3 – WGM11:10 - Waveform Generation Mode

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Combined with the WGM11:0 bits found in the TCCR1A Register, these bits control thecounting sequence of the counter, the source for maximum (TOP) counter value, andwhat type of waveform generation to be used. Modes of operation supported by theTimer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC)
mode, and three types of Pulse Width Modulation (PWM) modes. For more informationon the different modes see section "Modes of Operation".
Table 18-10 WGM1 Register Bits
Register Bits

Value

Description

WGM11:100x0

Normal mode of operation

0x1

PWM, phase correct, 8-bit

0x2

PWM, phase correct, 9-bit

0x3

PWM, phase correct, 10-bit

0x4

CTC, TOP = OCRnA

0x5

Fast PWM, 8-bit

0x6

Fast PWM, 9-bit

0x7

Fast PWM, 10-bit

0x8

PWM, Phase and frequency correct, TOP =
ICRn

0x9

PWM, Phase and frequency correct, TOP =
OCRnA

0xA

PWM, Phase correct, TOP = ICRn

0xB

PWM, Phase correct, TOP = OCRnA

0xC

CTC, TOP = OCRnA

0xD

Reserved

0xE

Fast PWM, TOP = ICRn

0xF

Fast PWM, TOP = OCRnA• Bit 2:0 – CS12:10 - Clock SelectThe three clock select bits select the clock source to be used by the Timer/Counter1
according to the following table. If external pin modes are used for the Timer/Counter1,transitions on the T1 pin will clock the counter even if the pin is configured as an output.
This feature allows software control of the counting.
Table 18-11 CS1 Register Bits
Register Bits

Value

Description

CS12:100x00

No clock source (Timer/Counter stopped)

0x01

clk_IO/1 (no prescaling)

0x02

clk_IO/8 (from prescaler)0x03

clk_IO/64 (from prescaler)0x04

clk_IO/256 (from prescaler)0x05

clk_IO/1024 (from prescaler)

0x06

External clock source on Tn pin, clock on
falling edge

0x07

External clock source on Tn pin, clock on
rising edge

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18.11.3 TCCR1C – Timer/Counter1 Control Register C
Bit

7

6

5

4

3

2

1

0

NA ($82)

FOC1A

FOC1B

FOC1C

Res4

Res3

Res2

Res1

Res0

Read/Write
Initial Value

RW
0

RW
0

RW
0

R
0

R
0

R
0

R
0

R
0

TCCR1C• Bit 7 – FOC1A - Force Output Compare for Channel A
The FOC1A bit is only active when the WGM13:0 bits specify a non-PWM mode. When
writing a logical one to the FOC1A bit, an immediate compare match is forced on the
waveform generation unit. The OC1A output is changed according to its COM1A1:0 bits
setting. Note that the FOC1A bits are implemented as strobes. Therefore it is the value
present in the COM1A1:0 bits that determine the effect of the forced compare. A
FOC1A strobe will not generate any interrupt nor will it clear the timer in Clear Timer on
Compare Match (CTC) mode using OCR1A as TOP. The FOC1A bits are always readas zero.
• Bit 6 – FOC1B - Force Output Compare for Channel B
The FOC1B bit is only active when the WGM13:0 bits specify a non-PWM mode. When
writing a logical one to the FOC1B bit, an immediate compare match is forced on the
waveform generation unit. The OC1B output is changed according to its COM1B1:0 bits
setting. Note that the FOC1B bits are implemented as strobes. Therefore it is the value
present in the COM1B1:0 bits that determine the effect of the forced compare. A
FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on
Compare Match (CTC) mode using OCR1B as TOP. The FOC1B bits are always readas zero.
• Bit 5 – FOC1C - Force Output Compare for Channel C
The FOC1C bit is only active when the WGM13:0 bits specify a non-PWM mode. When
writing a logical one to the FOC1C bit, an immediate compare match is forced on the
waveform generation unit. The OC1C output is changed according to its COM1C1:0 bits
setting. Note that the FOC1C bits are implemented as strobes. Therefore it is the value
present in the COM1C1:0 bits that determine the effect of the forced compare. A
FOC1C strobe will not generate any interrupt nor will it clear the timer in Clear Timer on
Compare Match (CTC) mode using OCR1C as TOP. The FOC1C bits are always readas zero.
• Bit 4:0 – Res4:0 - Reserved
These bits are reserved for future use.

18.11.4 TCNT1H – Timer/Counter1 High Byte
Bit

7

6

5

NA ($85)
Read/Write
Initial Value

4

3

2

1

0

TCNT1H7:0
RW
0

RW
0

RW
0

RW
0

RW
0

TCNT1H
RW
0

RW
0

RW
0

The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give
direct access, both for read and for write operations, to the Timer/Counter unit 16-bit
counter. To ensure that both the high and low bytes are read and written simultaneously
when the CPU accesses these registers, the access is performed using an 8-bit
temporary High Byte Register (TEMP). This temporary register is shared by all the other270

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ATmega128RFA1
16-bit registers. See section "Accessing 16-bit Registers" for details. Modifying thecounter (TCNT1) while the counter is running introduces a risk of missing a compare
match between TCNT1 and one of the OCR1x Registers. Writing to the TCNT1
Register blocks (removes) the compare match on the following timer clock for allcompare units.
• Bit 7:0 – TCNT1H7:0 - Timer/Counter1 High Byte

18.11.5 TCNT1L – Timer/Counter1 Low Byte
Bit

7

6

5

4

RW
0

RW
0

RW
0

RW
0

NA ($84)
Read/Write
Initial Value

3

2

1

0

RW
0

RW
0

RW
0

TCNT1L7:0
RW0

TCNT1LThe two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give
direct access, both for read and for write operations, to the Timer/Counter unit 16-bit
counter. To ensure that both the high and low bytes are read and written simultaneously
when the CPU accesses these registers, the access is performed using an 8-bit
temporary High Byte Register (TEMP). This temporary register is shared by all the other16-bit registers. See section "Accessing 16-bit Registers" for details. Modifying thecounter (TCNT1) while the counter is running introduces a risk of missing a compare
match between TCNT1 and one of the OCR1x Registers. Writing to the TCNT1
Register blocks (removes) the compare match on the following timer clock for allcompare units.
• Bit 7:0 – TCNT1L7:0 - Timer/Counter1 Low Byte

18.11.6 OCR1AH – Timer/Counter1 Output Compare Register A High Byte
Bit

7

6

5

NA ($89)
Read/Write
Initial Value

4

3

2

1

0

OCR1AH7:0
RW
0

RW
0

RW
0

RW
0

RW
0

OCR1AH
RW
0

RW
0

RW
0

The Output Compare Registers contain a 16-bit value that is continuously comparedwith the counter value (TCNT1). A match can be used to generate an Output Compareinterrupt, or to generate a waveform output on the OC1A pin. The Output Compare
Registers are 16-bit in size. To ensure that both the high and low bytes are written
simultaneously when the CPU writes to these registers, the access is performed using
an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all
the other 16-bit registers. See section "Accessing 16-bit Registers" for details.
• Bit 7:0 – OCR1AH7:0 - Timer/Counter1 Output Compare Register High Byte

18.11.7 OCR1AL – Timer/Counter1 Output Compare Register A Low Byte
Bit

7

6

5

NA ($88)
Read/Write
Initial Value

4

3

2

1

0

OCR1AL7:0
RW
0

RW
0

RW
0

RW
0

RW
0

OCR1AL
RW
0

RW
0

RW
0

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The Output Compare Registers contain a 16-bit value that is continuously comparedwith the counter value (TCNT1). A match can be used to generate an Output Compareinterrupt, or to generate a waveform output on the OC1A pin. The Output Compare
Registers are 16-bit in size. To ensure that both the high and low bytes are written
simultaneously when the CPU writes to these registers, the access is performed using
an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all
the other 16-bit registers. See section "Accessing 16-bit Registers" for details.
• Bit 7:0 – OCR1AL7:0 - Timer/Counter1 Output Compare Register Low Byte

18.11.8 OCR1BH – Timer/Counter1 Output Compare Register B High Byte
Bit

7

6

5

NA ($8B)
Read/Write
Initial Value

4

3

2

1

0

OCR1BH7:0
RW
0

RW
0

RW
0

RW
0

RW
0

OCR1BH
RW
0

RW
0

RW
0

The Output Compare Registers contain a 16-bit value that is continuously comparedwith the counter value (TCNT1). A match can be used to generate an Output Compareinterrupt, or to generate a waveform output on the OC1B pin. The Output Compare
Registers are 16-bit in size. To ensure that both the high and low bytes are written
simultaneously when the CPU writes to these registers, the access is performed using
an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all
the other 16-bit registers. See section "Accessing 16-bit Registers" for details.
• Bit 7:0 – OCR1BH7:0 - Timer/Counter1 Output Compare Register High Byte

18.11.9 OCR1BL – Timer/Counter1 Output Compare Register B Low Byte
Bit

7

6

5

NA ($8A)
Read/Write
Initial Value

4

3

2

1

0

OCR1BL7:0
R
0

RW
0

RW
0

RW
0

RW
0

OCR1BL
RW
0

RW
0

RW
0

The Output Compare Registers contain a 16-bit value that is continuously comparedwith the counter value (TCNT1). A match can be used to generate an Output Compareinterrupt, or to generate a waveform output on the OC1B pin. The Output Compare
Registers are 16-bit in size. To ensure that both the high and low bytes are written
simultaneously when the CPU writes to these registers, the access is performed using
an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all
the other 16-bit registers. See section "Accessing 16-bit Registers" for details.
• Bit 7:0 – OCR1BL7:0 - Timer/Counter1 Output Compare Register Low Byte

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18.11.10 OCR1CH – Timer/Counter1 Output Compare Register C High Byte
Bit

7

6

5

NA ($8D)
Read/Write
Initial Value

4

3

2

1

0

OCR1CH7:0
RW
0

RW
0

RW
0

RW
0

RW
0

OCR1CH
RW
0

RW
0

RW
0

The Output Compare Registers contain a 16-bit value that is continuously comparedwith the counter value (TCNT1). A match can be used to generate an Output Compareinterrupt, or to generate a waveform output on the OC1C pin. The Output Compare
Registers are 16-bit in size. To ensure that both the high and low bytes are written
simultaneously when the CPU writes to these registers, the access is performed using
an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all
the other 16-bit registers. See section "Accessing 16-bit Registers" for details.
• Bit 7:0 – OCR1CH7:0 - Timer/Counter1 Output Compare Register High Byte

18.11.11 OCR1CL – Timer/Counter1 Output Compare Register C Low Byte
Bit

7

6

5

4

R
0

RW
0

RW
0

RW
0

NA ($8C)
Read/Write
Initial Value

3

2

1

0

RW
0

RW
0

RW
0

OCR1CL7:0
RW0

OCR1CLThe Output Compare Registers contain a 16-bit value that is continuously comparedwith the counter value (TCNT1). A match can be used to generate an Output Compareinterrupt, or to generate a waveform output on the OC1C pin. The Output Compare
Registers are 16-bit in size. To ensure that both the high and low bytes are written
simultaneously when the CPU writes to these registers, the access is performed using
an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all
the other 16-bit registers. See section "Accessing 16-bit Registers" for details.
• Bit 7:0 – OCR1CL7:0 - Timer/Counter1 Output Compare Register Low Byte

18.11.12 ICR1H – Timer/Counter1 Input Capture Register High Byte
Bit

7

6

5

NA ($87)
Read/Write
Initial Value

4

3

2

1

0

ICR1H7:0
R
0

R
0

R
0

R
0

R
0

ICR1H
R
0

R
0

R
0

The Input Capture Register is updated with the counter (TCNT1) value each time an
event occurs on the ICP1 pin or on the Analog Comparator output. The Input Capture
Register can be used for defining the counter TOP value. The Input Capture Register is
16-bit in size. To ensure that both the high and low bytes are read simultaneously when
the CPU accesses these registers, the access is performed using an 8-bit temporary
High Byte Register (TEMP). This temporary register is shared by all the other 16-bit
registers. See section "Accessing 16-bit Registers" for details.
• Bit 7:0 – ICR1H7:0 - Timer/Counter1 Input Capture Register High Byte

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8266A-MCU Wireless-12/09

18.11.13 ICR1L – Timer/Counter1 Input Capture Register Low Byte
Bit

7

6

5

4

NA ($86)
Read/Write
Initial Value

3

2

1

0

ICR1L7:0
R
0

R
0

R
0

R
0

ICR1L

R
0

R
0

R
0

R
0

The Input Capture Register is updated with the counter (TCNT1) value each time an
event occurs on the ICP1 pin or on the Analog Comparator output. The Input Capture
Register can be used for defining the counter TOP value. The Input Capture Register is
16-bit in size. To ensure that both the high and low bytes are read simultaneously when
the CPU accesses these registers, the access is performed using an 8-bit temporary
High Byte Register (TEMP). This temporary register is shared by all the other 16-bit
registers. See section "Accessing 16-bit Registers" for details.
• Bit 7:0 – ICR1L7:0 - Timer/Counter1 Input Capture Register Low Byte

18.11.14 TIMSK1 – Timer/Counter1 Interrupt Mask Register
Bit

7

6

5

4

3

2

1

0

NA ($6F)

Res1

Res0

ICIE1

Res

OCIE1COCIE1BOCIE1A

TOIE1

Read/Write
Initial Value

R
0

R
0

RW
0

R
0

R
0

R
0

RW
0

RW
0

TIMSK1• Bit 7:6 – Res1:0 - Reserved Bit
This bit is reserved for future use. A read access always will return zero. A write accessdoes not modify the content.
• Bit 5 – ICIE1 - Timer/Counter1 Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts
globally enabled), the Timer/Counter1 Input Capture interrupt is enabled. The
corresponding Interrupt Vector is executed when the ICF1 Flag, located in TIFR1, isset.
• Bit 4 – Res - Reserved Bit
This bit is reserved for future use. A read access always will return zero. A write accessdoes not modify the content.
• Bit 3 – OCIE1C - Timer/Counter1 Output Compare C Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts
globally enabled), the Timer/Counter1 Output Compare C Match interrupt is enabled.
The corresponding Interrupt Vector is executed when the OCF1C Flag, located in
TIFR1, is set.
• Bit 2 – OCIE1B - Timer/Counter1 Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts
globally enabled), the Timer/Counter1 Output Compare B Match interrupt is enabled.
The corresponding Interrupt Vector is executed when the OCF1B Flag, located in
TIFR1, is set.
• Bit 1 – OCIE1A - Timer/Counter1 Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts
globally enabled), the Timer/Counter1 Output Compare A Match interrupt is enabled.

274

ATmega128RFA1
8266A-MCU Wireless-12/09

ATmega128RFA1
The corresponding Interrupt Vector is executed when the OCF1A Flag, located in
TIFR1, is set.
• Bit 0 – TOIE1 - Timer/Counter1 Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts
globally enabled), the Timer/Counter1 Overflow interrupt is enabled. The corresponding
Interrupt Vector is executed when the TOV1 Flag, located in TIFR1, is set.

18.11.15 TIFR1 – Timer/Counter1 Interrupt Flag Register
Bit

7

6

5

4

3

2

1

0

$16 ($36)

Res1

Res0

ICF1

Res

OCF1C

OCF1B

OCF1A

TOV1

Read/Write
Initial Value

R
0

R
0

RW
0

R
0

RW
0

RW
0

RW
0

RW
0

TIFR1

• Bit 7:6 – Res1:0 - Reserved Bit
This bit is reserved for future use. A read access always will return zero. A write accessdoes not modify the content.
• Bit 5 – ICF1 - Timer/Counter1 Input Capture Flag
This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture
Register (ICR1) is set by the WGM13:0 to be used as the TOP value, the ICF1 Flag is
set when the counter reaches the TOP value. ICF1 is automatically cleared when the
Input Capture Interrupt Vector is executed. Alternatively, ICF1 can be cleared by writing
a logic one to its bit location.
• Bit 4 – Res - Reserved Bit
This bit is reserved for future use. A read access always will return zero. A write accessdoes not modify the content.
• Bit 3 – OCF1C - Timer/Counter1 Output Compare C Match Flag
This flag is set in the timer clock cycle after the counter (TCNT1) value matches the
Output Compare Register C (OCR1C). Note that a Forced Output Compare (FOC1C)
strobe will not set the OCF1C Flag. OCF1C is automatically cleared when the Output
Compare Match C Interrupt Vector is executed. Alternatively, OCF1C can be cleared bywriting a logic one to its bit location.
• Bit 2 – OCF1B - Timer/Counter1 Output Compare B Match Flag
This flag is set in the timer clock cycle after the counter (TCNT1) value matches the
Output Compare Register B (OCR1B). Note that a Forced Output Compare (FOC1B)
strobe will not set the OCF1B Flag. OCF1B is automatically cleared when the Output
Compare Match B Interrupt Vector is executed. Alternatively, OCF1B can be cleared bywriting a logic one to its bit location.
• Bit 1 – OCF1A - Timer/Counter1 Output Compare A Match Flag
This flag is set in the timer clock cycle after the counter (TCNT1) value matches the
Output Compare Register A (OCR1A). Note that a Forced Output Compare (FOC1A)
strobe will not set the OCF1A Flag. OCF1A is automatically cleared when the Output
Compare Match A Interrupt Vector is executed. Alternatively, OCF1A can be cleared bywriting a logic one to its bit location.
• Bit 0 – TOV1 - Timer/Counter1 Overflow Flag
The setting of this flag is dependent of the WGM13:0 bits setting of the Timer/Counter1
Control Register. In Normal and CTC modes, the TOV1 Flag is set when the timer
275
8266A-MCU Wireless-12/09

overflows. TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt
Vector is executed. Alternatively, TOV1 can be cleared by writing a logic one to its bit
location.

18.11.16 TCCR3A – Timer/Counter3 Control Register A
Bit
NA ($90)

7

6

5

4

3

2

1

0

COM3A1 COM3A0 COM3B1 COM3B0 COM3C1 COM3C0 WGM31

Read/Write
Initial Value

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

WGM30

TCCR3A

RW
0• Bit 7:6 – COM3A1:0 - Compare Output Mode for Channel A
The COM3A1:0 bits control the output compare behavior of pin OC3A. If one or both of
the COM3A1:0 bits are written to one, the OC3A output overrides the normal portfunctionality of the I/O pin it is connected to. However note that the Data Direction
Register (DDR) bit corresponding to the OC3A pin must be set in order to enable theoutput driver. When the OC3A is connected to the pin, the function of the COM3A1:0
bits is dependent of the WGM33:0 bits setting. The following table shows the
COM3A1:0 bit functionality when the WGM33:0 bits are set to a normal or a CTC mode
(non-PWM). For the other functionality refer to section "Modes of Operation".
Table 18-12 COM3A Register Bits
Register Bits

Value

Description

COM3A1:00

Normal port operation, OCnA/OCnB/OCnC
disconnected.

1

Toggle OCnA/OCnB/OCnC on Compare
Match.

2

Clear OCnA/OCnB/OCnC on Compare
Match (set output to low level).

3

Set OCnA/OCnB/OCnC on Compare Match(set output to high level).

• Bit 5:4 – COM3B1:0 - Compare Output Mode for Channel B
The COM3B1:0 bits control the output compare behavior of pin OC3B. If one or both of
the COM3B1:0 bits are written to one, the OC3B output overrides the normal portfunctionality of the I/O pin it is connected to. However note that the Data Direction
Register (DDR) bit corresponding to the OC3B pin must be set in order to enable theoutput driver. When the OC3B is connected to the pin, the function of the COM3B1:0
bits is dependent of the WGM33:0 bits setting. The following table shows theCOM3B1:0 bit functionality when the WGM33:0 bits are set to a normal or a CTC mode
(non-PWM). For the other functionality refer to section "Modes of Operation".
Table 18-13 COM3B Register Bits

276

Register Bits

Value

Description

COM3B1:00

Normal port operation, OCnA/OCnB/OCnC
disconnected.

1

Toggle OCnA/OCnB/OCnC on Compare
Match.

2

Clear OCnA/OCnB/OCnC on Compare
Match (set output to low level).

3

Set OCnA/OCnB/OCnC on Compare Match

ATmega128RFA1
8266A-MCU Wireless-12/09

ATmega128RFA1
Register Bits

Value

Description(set output to high level).

• Bit 3:2 – COM3C1:0 - Compare Output Mode for Channel C
The COM3C1:0 bits control the output compare behavior of pin OC3C. If one or both of
the COM3C1:0 bits are written to one, the OC3C output overrides the normal portfunctionality of the I/O pin it is connected to. However note that the Data Direction
Register (DDR) bit corresponding to the OC3C pin must be set in order to enable theoutput driver. When the OC3C is connected to the pin, the function of the COM3C1:0
bits is dependent of the WGM33:0 bits setting. The following table shows the
COM3C1:0 bit functionality when the WGM33:0 bits are set to a normal or a CTC mode
(non-PWM). For the other functionality refer to section "Modes of Operation".
Table 18-14 COM3C Register Bits
Register Bits

Value

Description

COM3C1:00

Normal port operation, OCnA/OCnB/OCnC
disconnected.

1

Toggle OCnA/OCnB/OCnC on Compare
Match.

2

Clear OCnA/OCnB/OCnC on Compare
Match (set output to low level).

3

Set OCnA/OCnB/OCnC on Compare Match(set output to high level).

• Bit 1:0 – WGM31:30 - Waveform Generation Mode
Combined with the WGM33:2 bits found in the TCCR3B Register, these bits control thecounting sequence of the counter, the source for maximum (TOP) counter value, andwhat type of waveform generation to be used. Modes of operation supported by theTimer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC)
mode, and three types of Pulse Width Modulation (PWM) modes. For more informationon the different modes see section "Modes of Operation".
Table 18-15 WGM3 Register Bits
Register Bits

Value

Description

WGM31:30

0x0

Normal mode of operation

0x1

PWM, phase correct, 8-bit

0x2

PWM, phase correct, 9-bit

0x3

PWM, phase correct, 10-bit

0x4

CTC, TOP = OCRnA

0x5

Fast PWM, 8-bit

0x6

Fast PWM, 9-bit

0x7

Fast PWM, 10-bit

0x8

PWM, Phase and frequency correct, TOP =
ICRn

0x9

PWM, Phase and frequency correct, TOP =
OCRnA

0xA

PWM, Phase correct, TOP = ICRn

0xB

PWM, Phase correct, TOP = OCRnA

0xC

CTC, TOP = OCRnA

0xD

Reserved

277
8266A-MCU Wireless-12/09

Register Bits

Value

Description

0xE

Fast PWM, TOP = ICRn

0xF

Fast PWM, TOP = OCRnA

18.11.17 TCCR3B – Timer/Counter3 Control Register B
Bit

7

6

5

4

3

2

1

0

NA ($91)

ICNC3

ICES3

Res

WGM33

WGM32

CS32

CS31

CS30

Read/Write
Initial Value

RW
0

RW
0

R
0

RW
0

RW
0

RW
0

RW
0

RW
0

TCCR3B• Bit 7 – ICNC3 - Input Capture 3 Noise Canceller
Setting this bit (to one) activates the Input Capture Noise Canceler. When the Noise
Canceler is activated, the input from the Input Capture Pin (ICP3) is filtered. The filter
function requires four successive equal valued samples of the ICP3 pin for changing its
output. The input capture is therefore delayed by four Oscillator cycles when the noise
canceler is enabled.
• Bit 6 – ICES3 - Input Capture 3 Edge SelectThis bit selects which edge on the Input Capture Pin (ICP3) that is used to trigger acapture event. When the ICES3 bit is written to zero, a falling (negative) edge is usedas trigger. When the ICES3 bit is written to one, a rising (positive) edge will trigger thecapture. When a capture is triggered according to the ICES3 setting, the counter value
is copied into the Input Capture Register (ICR3). The event will also set the Input
Capture Flag (ICF3). This can be used to cause an Input Capture Interrupt, if thisinterrupt is enabled. When the ICR3 is used as TOP value (see description of the
WGM33:0 bits located in the TCCR3A and the TCCR3B Register), the ICP3 isdisconnected and consequently the input capture function is disabled.
• Bit 5 – Res - Reserved Bit
This bit is reserved for future use. A read access always will return zero. A write accessdoes not modify the content.
• Bit 4:3 – WGM31:30 - Waveform Generation Mode
Combined with the WGM31:0 bits found in the TCCR3A Register, these bits control thecounting sequence of the counter, the source for maximum (TOP) counter value, andwhat type of waveform generation to be used. Modes of operation supported by theTimer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC)
mode, and three types of Pulse Width Modulation (PWM) modes. For more informationon the different modes see section "Modes of Operation".
Table 18-16 WGM3 Register Bits

278

Register Bits

Value

Description

WGM31:30

0x0

Normal mode of operation

0x1

PWM, phase correct, 8-bit

0x2

PWM, phase correct, 9-bit

0x3

PWM, phase correct, 10-bit

0x4

CTC, TOP = OCRnA

0x5

Fast PWM, 8-bit

0x6

Fast PWM, 9-bit

ATmega128RFA1
8266A-MCU Wireless-12/09

ATmega128RFA1
Register Bits

Value

Description

0x7

Fast PWM, 10-bit

0x8

PWM, Phase and frequency correct, TOP =
ICRn

0x9

PWM, Phase and frequency correct, TOP =
OCRnA

0xA

PWM, Phase correct, TOP = ICRn

0xB

PWM, Phase correct, TOP = OCRnA

0xC

CTC, TOP = OCRnA

0xD

Reserved

0xE

Fast PWM, TOP = ICRn

0xF

Fast PWM, TOP = OCRnA• Bit 2:0 – CS32:30 - Clock SelectThe three clock select bits select the clock source to be used by the Timer/Counter3
according to the following table. If external pin modes are used for the Timer/Counter3,transitions on the T3 pin will clock the counter even if the pin is configured as an output.
This feature allows software control of the counting.
Table 18-17 CS3 Register Bits
Register Bits

Value

Description

CS32:300x00

No clock source (Timer/Counter stopped)

0x01

clk_IO/1 (no prescaling)

0x02

clk_IO/8 (from prescaler)0x03

clk_IO/64 (from prescaler)0x04

clk_IO/256 (from prescaler)0x05

clk_IO/1024 (from prescaler)

0x06

External clock source on Tn pin, clock on
falling edge

0x07

External clock source on Tn pin, clock on
rising edge

18.11.18 TCCR3C – Timer/Counter3 Control Register C
Bit

7

6

5

4

3

2

1

0

NA ($92)

FOC3A

FOC3B

FOC3C

Res4

Res3

Res2

Res1

Res0

Read/Write
Initial Value

RW
0

RW
0

RW
0

R
0

R
0

R
0

R
0

R
0

TCCR3C• Bit 7 – FOC3A - Force Output Compare for Channel A
The FOC3A bit is only active when the WGM33:0 bits specify a non-PWM mode. When
writing a logical one to the FOC3A bit, an immediate compare match is forced on the
waveform generation unit. The OC3A output is changed according to its COM3A1:0 bits
setting. Note that the FOC3A bits are implemented as strobes. Therefore it is the value
present in the COM3A1:0 bits that determine the effect of the forced compare. A
FOC3A strobe will not generate any interrupt nor will it clear the timer in Clear Timer on
Compare Match (CTC) mode using OCR3A as TOP. The FOC3A bits are always readas zero.

279
8266A-MCU Wireless-12/09

• Bit 6 – FOC3B - Force Output Compare for Channel B
The FOC3B bit is only active when the WGM33:0 bits specify a non-PWM mode. When
writing a logical one to the FOC3B bit, an immediate compare match is forced on the
waveform generation unit. The OC3B output is changed according to its COM3B1:0 bits
setting. Note that the FOC3B bits are implemented as strobes. Therefore it is the value
present in the COM3B1:0 bits that determine the effect of the forced compare. A
FOC3B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on
Compare Match (CTC) mode using OCR1B as TOP. The FOC3B bits are always readas zero.
• Bit 5 – FOC3C - Force Output Compare for Channel C
The FOC3C bit is only active when the WGM33:0 bits specify a non-PWM mode. When
writing a logical one to the FOC3C bit, an immediate compare match is forced on the
waveform generation unit. The OC3C output is changed according to its COM3C1:0 bits
setting. Note that the FOC3C bits are implemented as strobes. Therefore it is the value
present in the COM3C1:0 bits that determine the effect of the forced compare. A
FOC3C strobe will not generate any interrupt nor will it clear the timer in Clear Timer on
Compare Match (CTC) mode using OCR3C as TOP. The FOC3C bits are always readas zero.
• Bit 4:0 – Res4:0 - Reserved
These bits are reserved for future use.

18.11.19 TCNT3H – Timer/Counter3 High Byte
Bit

7

6

5

NA ($95)
Read/Write
Initial Value

4

3

2

1

0

TCNT3H7:0
RW
0

RW
0

RW
0

RW
0

RW
0

TCNT3H
RW
0

RW
0

RW
0

The two Timer/Counter I/O locations (TCNT3H and TCNT3L, combined TCNT3) give
direct access, both for read and for write operations, to the Timer/Counter unit 16-bit
counter. To ensure that both the high and low bytes are read and written simultaneously
when the CPU accesses these registers, the access is performed using an 8-bit
temporary High Byte Register (TEMP). This temporary register is shared by all the other16-bit registers. See section "Accessing 16-bit Registers" for details. Modifying thecounter (TCNT3) while the counter is running introduces a risk of missing a compare
match between TCNT3 and one of the OCR3x Registers. Writing to the TCNT3
Register blocks (removes) the compare match on the following timer clock for allcompare units.
• Bit 7:0 – TCNT3H7:0 - Timer/Counter3 High Byte

18.11.20 TCNT3L – Timer/Counter3 Low Byte
Bit

7

6

5

NA ($94)
Read/Write
Initial Value

280

4

3

2

1

0

TCNT3L7:0
RW
0

RW
0

RW
0

RW
0

RW
0

TCNT3L
RW
0

RW
0

RW
0

ATmega128RFA1
8266A-MCU Wireless-12/09

ATmega128RFA1
The two Timer/Counter I/O locations (TCNT3H and TCNT3L, combined TCNT3) give
direct access, both for read and for write operations, to the Timer/Counter unit 16-bit
counter. To ensure that both the high and low bytes are read and written simultaneously
when the CPU accesses these registers, the access is performed using an 8-bit
temporary High Byte Register (TEMP). This temporary register is shared by all the other16-bit registers. See section "Accessing 16-bit Registers" for details. Modifying thecounter (TCNT3) while the counter is running introduces a risk of missing a compare
match between TCNT3 and one of the OCR3x Registers. Writing to the TCNT3
Register blocks (removes) the compare match on the following timer clock for allcompare units.
• Bit 7:0 – TCNT3L7:0 - Timer/Counter3 Low Byte

18.11.21 OCR3AH – Timer/Counter3 Output Compare Register A High Byte
Bit

7

6

5

4

RW
0

RW
0

RW
0

RW
0

NA ($99)
Read/Write
Initial Value

3

2

1

0

RW
0

RW
0

RW
0

OCR3AH7:0
RW
0

OCR3AHThe Output Compare Registers contain a 16-bit value that is continuously comparedwith the counter value (TCNT3). A match can be used to generate an Output Compareinterrupt, or to generate a waveform output on the OC3A pin. The Output Compare
Registers are 16-bit in size. To ensure that both the high and low bytes are written
simultaneously when the CPU writes to these registers, the access is performed using
an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all
the other 16-bit registers. See section "Accessing 16-bit Registers" for details.
• Bit 7:0 – OCR3AH7:0 - Timer/Counter3 Output Compare Register High Byte

18.11.22 OCR3AL – Timer/Counter3 Output Compare Register A Low Byte
Bit

7

6

5

NA ($98)
Read/Write
Initial Value

4

3

2

1

0

OCR3AL7:0
RW
0

RW
0

RW
0

RW
0

RW
0

OCR3AL
RW
0

RW
0

RW
0

The Output Compare Registers contain a 16-bit value that is continuously comparedwith the counter value (TCNT3). A match can be used to generate an Output Compareinterrupt, or to generate a waveform output on the OC3A pin. The Output Compare
Registers are 16-bit in size. To ensure that both the high and low bytes are written
simultaneously when the CPU writes to these registers, the access is performed using
an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all
the other 16-bit registers. See section "Accessing 16-bit Registers" for details.
• Bit 7:0 – OCR3AL7:0 - Timer/Counter3 Output Compare Register Low Byte

281
8266A-MCU Wireless-12/09

18.11.23 OCR3BH – Timer/Counter3 Output Compare Register B High Byte
Bit

7

6

5

NA ($9B)
Read/Write
Initial Value

4

3

2

1

0

OCR3BH7:0
RW
0

RW
0

RW
0

RW
0

RW
0

OCR3BH
RW
0

RW
0

RW
0

The Output Compare Registers contain a 16-bit value that is continuously comparedwith the counter value (TCNT3). A match can be used to generate an Output Compareinterrupt, or to generate a waveform output on the OC3B pin. The Output Compare
Registers are 16-bit in size. To ensure that both the high and low bytes are written
simultaneously when the CPU writes to these registers, the access is performed using
an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all
the other 16-bit registers. See section "Accessing 16-bit Registers" for details.
• Bit 7:0 – OCR3BH7:0 - Timer/Counter3 Output Compare Register High Byte

18.11.24 OCR3BL – Timer/Counter3 Output Compare Register B Low Byte
Bit

7

6

5

4

R
0

RW
0

RW
0

RW
0

NA ($9A)
Read/Write
Initial Value

3

2

1

0

RW
0

RW
0

RW
0

OCR3BL7:0
RW0

OCR3BLThe Output Compare Registers contain a 16-bit value that is continuously comparedwith the counter value (TCNT3). A match can be used to generate an Output Compareinterrupt, or to generate a waveform output on the OC3B pin. The Output Compare
Registers are 16-bit in size. To ensure that both the high and low bytes are written
simultaneously when the CPU writes to these registers, the access is performed using
an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all
the other 16-bit registers. See section "Accessing 16-bit Registers" for details.
• Bit 7:0 – OCR3BL7:0 - Timer/Counter3 Output Compare Register Low Byte

18.11.25 OCR3CH – Timer/Counter3 Output Compare Register C High Byte
Bit

7

6

5

NA ($9D)
Read/Write
Initial Value

4

3

2

1

0

OCR3CH7:0
RW
0

RW
0

RW
0

RW
0

RW
0

OCR3CH
RW
0

RW
0

RW
0

The Output Compare Registers contain a 16-bit value that is continuously comparedwith the counter value (TCNT3). A match can be used to generate an Output Compareinterrupt, or to generate a waveform output on the OC3C pin. The Output Compare
Registers are 16-bit in size. To ensure that both the high and low bytes are written
simultaneously when the CPU writes to these registers, the access is performed using
an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all
the other 16-bit registers. See section "Accessing 16-bit Registers" for details.
• Bit 7:0 – OCR3CH7:0 - Timer/Counter3 Output Compare Register High Byte

282

ATmega128RFA1
8266A-MCU Wireless-12/09

ATmega128RFA1
18.11.26 OCR3CL – Timer/Counter3 Output Compare Register C Low Byte
Bit

7

6

5

NA ($9C)
Read/Write
Initial Value

4

3

2

1

0

OCR3CL7:0
R
0

RW
0

RW
0

RW
0

RW
0

OCR3CL
RW
0

RW
0

RW
0

The Output Compare Registers contain a 16-bit value that is continuously comparedwith the counter value (TCNT3). A match can be used to generate an Output Compareinterrupt, or to generate a waveform output on the OC3C pin. The Output Compare
Registers are 16-bit in size. To ensure that both the high and low bytes are written
simultaneously when the CPU writes to these registers, the access is performed using
an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all
the other 16-bit registers. See section "Accessing 16-bit Registers" for details.
• Bit 7:0 – OCR3CL7:0 - Timer/Counter3 Output Compare Register Low Byte

18.11.27 ICR3H – Timer/Counter3 Input Capture Register High Byte
Bit

7

6

5

4

R
0

R
0

R
0

R
0

NA ($97)
Read/Write
Initial Value

3

2

1

0

R
0

R
0

R
0

ICR3H7:0
R
0

ICR3H

The Input Capture Register is updated with the counter (TCNT3) value each time an
event occurs on the ICP3 pin. The Input Capture Register can be used for defining thecounter TOP value. The Input Capture Register is 16-bit in size. To ensure that both thehigh and low bytes are read simultaneously when the CPU accesses these registers,
the access is performed using an 8-bit temporary High Byte Register (TEMP). This
temporary register is shared by all the other 16-bit registers. See section "Accessing 16bit Registers" for details.
• Bit 7:0 – ICR3H7:0 - Timer/Counter3 Input Capture Register High Byte

18.11.28 ICR3L – Timer/Counter3 Input Capture Register Low Byte
Bit

7

6

5

NA ($96)
Read/Write
Initial Value

4

3

2

1

0

ICR3L7:0
R
0

R
0

R
0

R
0

R
0

ICR3L
R
0

R
0

R
0

The Input Capture Register is updated with the counter (TCNT3) value each time an
event occurs on the ICP3 pin. The Input Capture Register can be used for defining thecounter TOP value. The Input Capture Register is 16-bit in size. To ensure that both thehigh and low bytes are read simultaneously when the CPU accesses these registers,
the access is performed using an 8-bit temporary High Byte Register (TEMP). This
temporary register is shared by all the other 16-bit registers. See section "Accessing 16bit Registers" for details.
• Bit 7:0 – ICR3L7:0 - Timer/Counter3 Input Capture Register Low Byte

283
8266A-MCU Wireless-12/09

18.11.29 TIMSK3 – Timer/Counter3 Interrupt Mask Register
Bit

7

6

5

4

3

2

1

0

NA ($71)

Res1

Res0

ICIE3

Res

OCIE3COCIE3B

OCIE3A

TOIE3

Read/Write
Initial Value

R
0

R
0

RW
0

R
0

R
0

R
0

RW
0

RW
0

TIMSK3• Bit 7:6 – Res1:0 - Reserved Bit
This bit is reserved for future use. A read access always will return zero. A write accessdoes not modify the content.
• Bit 5 – ICIE3 - Timer/Counter3 Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts
globally enabled), the Timer/Counter3 Input Capture interrupt is enabled. The
corresponding Interrupt Vector is executed when the ICF3 Flag, located in TIFR3, isset.
• Bit 4 – Res - Reserved Bit
This bit is reserved for future use. A read access always will return zero. A write accessdoes not modify the content.
• Bit 3 – OCIE3C - Timer/Counter3 Output Compare C Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts
globally enabled), the Timer/Counter3 Output Compare C Match interrupt is enabled.
The corresponding Interrupt Vector is executed when the OCF3C Flag, located in
TIFR3, is set.
• Bit 2 – OCIE3B - Timer/Counter3 Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts
globally enabled), the Timer/Counter3 Output Compare B Match interrupt is enabled.
The corresponding Interrupt Vector is executed when the OCF3B Flag, located in
TIFR3, is set.
• Bit 1 – OCIE3A - Timer/Counter3 Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts
globally enabled), the Timer/Counter3 Output Compare A Match interrupt is enabled.
The corresponding Interrupt Vector is executed when the OCF3A Flag, located in
TIFR3, is set.
• Bit 0 – TOIE3 - Timer/Counter3 Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts
globally enabled), the Timer/Counter3 Overflow interrupt is enabled. The corresponding
Interrupt Vector is executed when the TOV3 Flag, located in TIFR3, is set.

18.11.30 TIFR3 – Timer/Counter3 Interrupt Flag Register
Bit

7

6

5

4

3

2

1

0

$18 ($38)

Res1

Res0

ICF3

Res

OCF3C

OCF3B

OCF3A

TOV3

Read/Write
Initial Value

R
0

R
0

RW
0

R
0

RW
0

RW
0

RW
0

RW
0

TIFR3

• Bit 7:6 – Res1:0 - Reserved Bit

284

ATmega128RFA1
8266A-MCU Wireless-12/09

ATmega128RFA1This bit is reserved for future use. A read access always will return zero. A write accessdoes not modify the content.
• Bit 5 – ICF3 - Timer/Counter3 Input Capture Flag
This flag is set when a capture event occurs on the ICP3 pin. When the Input Capture
Register (ICR3) is set by the WGM33:0 to be used as the TOP value, the ICF3 Flag is
set when the counter reaches the TOP value. ICF3 is automatically cleared when the
Input Capture Interrupt Vector is executed. Alternatively, ICF3 can be cleared by writing
a logic one to its bit location.
• Bit 4 – Res - Reserved Bit
This bit is reserved for future use. A read access always will return zero. A write accessdoes not modify the content.
• Bit 3 – OCF3C - Timer/Counter3 Output Compare C Match Flag
This flag is set in the timer clock cycle after the counter (TCNT3) value matches the
Output Compare Register C (OCR3C). Note that a Forced Output Compare (FOC3C)
strobe will not set the OCF3C Flag. OCF3C is automatically cleared when the Output
Compare Match C Interrupt Vector is executed. Alternatively, OCF3C can be cleared bywriting a logic one to its bit location.
• Bit 2 – OCF3B - Timer/Counter3 Output Compare B Match Flag
This flag is set in the timer clock cycle after the counter (TCNT3) value matches the
Output Compare Register B (OCR3B). Note that a Forced Output Compare (FOC3B)
strobe will not set the OCF3B Flag. OCF3B is automatically cleared when the Output
Compare Match B Interrupt Vector is executed. Alternatively, OCF3B can be cleared bywriting a logic one to its bit location.
• Bit 1 – OCF3A - Timer/Counter3 Output Compare A Match Flag
This flag is set in the timer clock cycle after the counter (TCNT3) value matches the
Output Compare Register A (OCR3A). Note that a Forced Output Compare (FOC3A)
strobe will not set the OCF3A Flag. OCF3A is automatically cleared when the Output
Compare Match A Interrupt Vector is executed. Alternatively, OCF3A can be cleared bywriting a logic one to its bit location.
• Bit 0 – TOV3 - Timer/Counter3 Overflow Flag
The setting of this flag is dependent of the WGM33:0 bits setting of the Timer/Counter3
Control Register. In Normal and CTC modes, the TOV3 Flag is set when the timer
overflows. TOV3 is automatically cleared when the Timer/Counter3 Overflow Interrupt
Vector is executed. Alternatively, TOV3 can be cleared by writing a logic one to its bit
location.

18.11.31 TCCR4A – Timer/Counter4 Control Register A
Bit
NA ($A0)
Read/Write
Initial Value

7

6

5

4

3

2

1

COM4A1 COM4A0 COM4B1 COM4B0 COM4C1 COM4C0 WGM41
RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

0

WGM40

TCCR4A

RW
0• Bit 7:6 – COM4A1:0 - Compare Output Mode for Channel A
The Timer/Counter4 has only limited functionality. Therefore the COM4A1:0 bits do notcontrol the output compare behavior of any pin. The following table shows the285
8266A-MCU Wireless-12/09

COM4A1:0 bit functionality when the WGM43:0 bits are set to a normal or a CTC mode
(non-PWM). For the other functionality refer to section "Modes of Operation".
Table 18-18 COM4A Register Bits
Register Bits

Value

Description

COM4A1:00

Normal operation

1

Reserved

2

Reserved

3

Reserved• Bit 5:4 – COM4B1:0 - Compare Output Mode for Channel B
The Timer/Counter4 has only limited functionality. Therefore the COM4B1:0 bits do notcontrol the output compare behavior of any pin. The following table shows the
COM4B1:0 bit functionality when the WGM43:0 bits are set to a normal or a CTC mode
(non-PWM). For the other functionality refer to section "Modes of Operation".
Table 18-19 COM4B Register Bits
Register Bits

Value

COM4B1:00

Normal operation

Description

1

Reserved

2

Reserved

3

Reserved• Bit 3:2 – COM4C1:0 - Compare Output Mode for Channel C
The Timer/Counter4 has only limited functionality. Therefore the COM4C1:0 bits do notcontrol the output compare behavior of any pin. The following table shows the
COM4C1:0 bit functionality when the WGM43:0 bits are set to a normal or a CTC mode
(non-PWM). For the other functionality refer to section "Modes of Operation".
Table 18-20 COM4C Register Bits
Register Bits

Value

Description

COM4C1:00

Normal operation

1

Reserved

2

Reserved

3

Reserved• Bit 1:0 – WGM41:40 - Waveform Generation Mode
Combined with the WGM43:2 bits found in the TCCR4B Register, these bits control thecounting sequence of the counter, the source for maximum (TOP) counter value, andwhat type of waveform generation to be used. Modes of operation supported by theTimer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC)
mode, and three types of Pulse Width Modulation (PWM) modes. For more informationon the different modes see section "Modes of Operation". Note that Timer/Counter4 has
only limited functionality. It cannot be connected to any I/O pin.
Table 18-21 WGM4 Register Bits

286

Register Bits

Value

Description

WGM41:40

0x0

Normal mode of operation

0x1

PWM, phase correct, 8-bit

0x2

PWM, phase correct, 9-bit

0x3

PWM, phase correct, 10-bit

0x4

CTC, TOP = OCRnA

ATmega128RFA1
8266A-MCU Wireless-12/09

ATmega128RFA1
Register Bits

Value

Description

0x5

Fast PWM, 8-bit

0x6

Fast PWM, 9-bit

0x7

Fast PWM, 10-bit

0x8

PWM, Phase and frequency correct, TOP =
ICRn

0x9

PWM, Phase and frequency correct, TOP =
OCRnA

0xA

PWM, Phase correct, TOP = ICRn

0xB

PWM, Phase correct, TOP = OCRnA

0xC

CTC, TOP = OCRnA

0xD

Reserved

0xE

Fast PWM, TOP = ICRn

0xF

Fast PWM, TOP = OCRnA

18.11.32 TCCR4B – Timer/Counter4 Control Register B
Bit

7

6

5

4

3

2

1

0

NA ($A1)

ICNC4

ICES4

Res

WGM43

WGM42

CS42

CS41

CS40

Read/Write
Initial Value

RW
0

RW
0

R
0

RW
0

RW
0

RW
0

RW
0

RW
0

TCCR4B• Bit 7 – ICNC4 - Input Capture 4 Noise Canceller
Timer/Counter4 has only limited functionality. It is not connected to any Input Capture
Pin. Therefore this bit has no meaningful function.
• Bit 6 – ICES4 - Input Capture 4 Edge SelectTimer/Counter4 has only limited functionality. It is not connected to any Input Capture
Pin. Therefore this bit has no meaningful function.
• Bit 5 – Res - Reserved Bit
This bit is reserved for future use. A read access always will return zero. A write accessdoes not modify the content.
• Bit 4:3 – WGM41:40 - Waveform Generation Mode
Combined with the WGM41:0 bits found in the TCCR4A Register, these bits control thecounting sequence of the counter, the source for maximum (TOP) counter value, andwhat type of waveform generation to be used. Modes of operation supported by theTimer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC)
mode, and three types of Pulse Width Modulation (PWM) modes. For more informationon the different modes see section "Modes of Operation". Note that Timer/Counter4 has
only limited functionality. It cannot be connected to any I/O pin.
Table 18-22 WGM4 Register Bits
Register Bits

Value

Description

WGM41:40

0x0

Normal mode of operation

0x1

PWM, phase correct, 8-bit

0x2

PWM, phase correct, 9-bit

0x3

PWM, phase correct, 10-bit

287
8266A-MCU Wireless-12/09

Register Bits

Value

Description

0x4

CTC, TOP = OCRnA

0x5

Fast PWM, 8-bit

0x6

Fast PWM, 9-bit

0x7

Fast PWM, 10-bit

0x8

PWM, Phase and frequency correct, TOP =
ICRn

0x9

PWM, Phase and frequency correct, TOP =
OCRnA

0xA

PWM, Phase correct, TOP = ICRn

0xB

PWM, Phase correct, TOP = OCRnA

0xC

CTC, TOP = OCRnA

0xD

Reserved

0xE

Fast PWM, TOP = ICRn

0xF

Fast PWM, TOP = OCRnA• Bit 2:0 – CS42:40 - Clock SelectThe three clock select bits select the clock source to be used by the Timer/Counter4
according to the following table. External pin modes cannot be used for theTimer/Counter4.
Table 18-23 CS4 Register Bits
Register Bits

Value

Description

CS42:400x00

No clock source (Timer/Counter stopped)

0x01

clk_IO/1 (no prescaling)

0x02

clk_IO/8 (from prescaler)0x03

clk_IO/64 (from prescaler)0x04

clk_IO/256 (from prescaler)0x05

clk_IO/1024 (from prescaler)

0x06

Reserved

0x07

Reserved

18.11.33 TCCR4C – Timer/Counter4 Control Register C
Bit

7

6

5

4

3

2

1

0

NA ($A2)

FOC4A

FOC4B

FOC4C

Res4

Res3

Res2

Res1

Res0

Read/Write
Initial Value

RW
0

RW
0

RW
0

R
0

R
0

R
0

R
0

R
0

TCCR4C• Bit 7 – FOC4A - Force Output Compare for Channel A
The FOC4A bit is only active when the WGM43:0 bits specify a non-PWM mode. When
writing a logical one to the FOC4A bit, an immediate compare match is forced. Due tothe limited functionality of the Timer/Counter4 the match has no direct impact on any
output pin. Note that the FOC4A bits are implemented as strobes. Therefore it is thevalue present in the COM4A1:0 bits that determine the effect of the forced compare. A
FOC4A strobe will not generate any interrupt nor will it clear the timer in Clear Timer on

288

ATmega128RFA1
8266A-MCU Wireless-12/09

ATmega128RFA1
Compare Match (CTC) mode using OCR4A as TOP. The FOC4A bits are always readas zero.
• Bit 6 – FOC4B - Force Output Compare for Channel B
The FOC4B bit is only active when the WGM43:0 bits specify a non-PWM mode. When
writing a logical one to the FOC4B bit, an immediate compare match is forced. Due tothe limited functionality of the Timer/Counter4 the match has no direct impact on any
output pin. Note that the FOC4B bits are implemented as strobes. Therefore it is thevalue present in the COM4B1:0 bits that determine the effect of the forced compare. A
FOC4B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on
Compare Match (CTC) mode using OCR4B as TOP. The FOC4B bits are always readas zero.
• Bit 5 – FOC4C - Force Output Compare for Channel C
The FOC4C bit is only active when the WGM43:0 bits specify a non-PWM mode. When
writing a logical one to the FOC4C bit, an immediate compare match is forced. Due tothe limited functionality of the Timer/Counter4 the match has no direct impact on any
output pin. Note that the FOC4C bits are implemented as strobes. Therefore it is thevalue present in the COM4C1:0 bits that determine the effect of the forced compare. A
FOC4C strobe will not generate any interrupt nor will it clear the timer in Clear Timer on
Compare Match (CTC) mode using OCR4C as TOP. The FOC4C bits are always readas zero.
• Bit 4:0 – Res4:0 - Reserved
These bits are reserved for future use.

18.11.34 TCNT4H – Timer/Counter4 High Byte
Bit

7

6

5

4

RW
0

RW
0

RW
0

RW
0

NA ($A5)
Read/Write
Initial Value

3

2

1

0

RW
0

RW
0

RW
0

TCNT4H7:0
RW
0

TCNT4H

The two Timer/Counter I/O locations (TCNT4H and TCNT4L, combined TCNT4) give
direct access, both for read and for write operations, to the Timer/Counter unit 16-bit
counter. To ensure that both the high and low bytes are read and written simultaneously
when the CPU accesses these registers, the access is performed using an 8-bit
temporary High Byte Register (TEMP). This temporary register is shared by all the other16-bit registers. See section "Accessing 16-bit Registers" for details. Modifying thecounter (TCNT4) while the counter is running introduces a risk of missing a compare
match between TCNT4 and one of the OCR4x Registers. Writing to the TCNT4
Register blocks (removes) the compare match on the following timer clock for allcompare units.
• Bit 7:0 – TCNT4H7:0 - Timer/Counter4 High Byte

18.11.35 TCNT4L – Timer/Counter4 Low Byte
Bit

7

6

5

NA ($A4)
Read/Write
Initial Value

4

3

2

1

0

TCNT4L7:0
RW
0

RW
0

RW
0

RW
0

RW
0

TCNT4L
RW
0

RW
0

RW
0

289
8266A-MCU Wireless-12/09

The two Timer/Counter I/O locations (TCNT4H and TCNT4L, combined TCNT4) give
direct access, both for read and for write operations, to the Timer/Counter unit 16-bit
counter. To ensure that both the high and low bytes are read and written simultaneously
when the CPU accesses these registers, the access is performed using an 8-bit
temporary High Byte Register (TEMP). This temporary register is shared by all the other16-bit registers. See section "Accessing 16-bit Registers" for details. Modifying thecounter (TCNT4) while the counter is running introduces a risk of missing a compare
match between TCNT4 and one of the OCR4x Registers. Writing to the TCNT4
Register blocks (removes) the compare match on the following timer clock for allcompare units.
• Bit 7:0 – TCNT4L7:0 - Timer/Counter4 Low Byte

18.11.36 OCR4AH – Timer/Counter4 Output Compare Register A High Byte
Bit

7

6

5

NA ($A9)
Read/Write
Initial Value

4

3

2

1

0

OCR4AH7:0
RW
0

RW
0

RW
0

RW
0

RW
0

OCR4AH
RW
0

RW
0

RW
0

The Output Compare Registers contain a 16-bit value that is continuously comparedwith the counter value (TCNT4). A match can be used to generate an Output Compareinterrupt. The Output Compare Registers are 16-bit in size. To ensure that both the highand low bytes are written simultaneously when the CPU writes to these registers, theaccess is performed using an 8-bit temporary High Byte Register (TEMP). This
temporary register is shared by all the other 16-bit registers. See section "Accessing 16bit Registers" for details.
• Bit 7:0 – OCR4AH7:0 - Timer/Counter4 Output Compare Register High Byte

18.11.37 OCR4AL – Timer/Counter4 Output Compare Register A Low Byte
Bit

7

6

5

NA ($A8)
Read/Write
Initial Value

4

3

2

1

0

OCR4AL7:0
RW
0

RW
0

RW
0

RW
0

RW
0

OCR4AL
RW
0

RW
0

RW
0

The Output Compare Registers contain a 16-bit value that is continuously comparedwith the counter value (TCNT4). A match can be used to generate an Output Compareinterrupt. The Output Compare Registers are 16-bit in size. To ensure that both the highand low bytes are written simultaneously when the CPU writes to these registers, theaccess is performed using an 8-bit temporary High Byte Register (TEMP). This
temporary register is shared by all the other 16-bit registers. See section "Accessing 16bit Registers" for details.
• Bit 7:0 – OCR4AL7:0 - Timer/Counter4 Output Compare Register Low Byte

290

ATmega128RFA1
8266A-MCU Wireless-12/09

ATmega128RFA1
18.11.38 OCR4BH – Timer/Counter4 Output Compare Register B High Byte
Bit

7

6

5

NA ($AB)
Read/Write
Initial Value

4

3

2

1

0

OCR4BH7:0
RW
0

RW
0

RW
0

RW
0

RW
0

OCR4BH
RW
0

RW
0

RW
0

The Output Compare Registers contain a 16-bit value that is continuously comparedwith the counter value (TCNT4). A match can be used to generate an Output Compareinterrupt. The Output Compare Registers are 16-bit in size. To ensure that both the highand low bytes are written simultaneously when the CPU writes to these registers, theaccess is performed using an 8-bit temporary High Byte Register (TEMP). This
temporary register is shared by all the other 16-bit registers. See section "Accessing 16bit Registers" for details.
• Bit 7:0 – OCR4BH7:0 - Timer/Counter4 Output Compare Register High Byte

18.11.39 OCR4BL – Timer/Counter4 Output Compare Register B Low Byte
Bit

7

6

5

4

R
0

RW
0

RW
0

RW
0

NA ($AA)
Read/Write
Initial Value

3

2

1

0

RW
0

RW
0

RW
0

OCR4BL7:0
RW0

OCR4BLThe Output Compare Registers contain a 16-bit value that is continuously comparedwith the counter value (TCNT4). A match can be used to generate an Output Compareinterrupt. The Output Compare Registers are 16-bit in size. To ensure that both the highand low bytes are written simultaneously when the CPU writes to these registers, theaccess is performed using an 8-bit temporary High Byte Register (TEMP). This
temporary register is shared by all the other 16-bit registers. See section "Accessing 16bit Registers" for details.
• Bit 7:0 – OCR4BL7:0 - Timer/Counter4 Output Compare Register Low Byte

18.11.40 OCR4CH – Timer/Counter4 Output Compare Register C High Byte
Bit

7

6

5

NA ($AD)
Read/Write
Initial Value

4

3

2

1

0

OCR4CH7:0
RW
0

RW
0

RW
0

RW
0

RW
0

OCR4CH
RW
0

RW
0

RW
0

The Output Compare Registers contain a 16-bit value that is continuously comparedwith the counter value (TCNT4). A match can be used to generate an Output Compareinterrupt. The Output Compare Registers are 16-bit in size. To ensure that both the highand low bytes are written simultaneously when the CPU writes to these registers, theaccess is performed using an 8-bit temporary High Byte Register (TEMP). This
temporary register is shared by all the other 16-bit registers. See section "Accessing 16bit Registers" for details.
• Bit 7:0 – OCR4CH7:0 - Timer/Counter4 Output Compare Register High Byte

291
8266A-MCU Wireless-12/09

18.11.41 OCR4CL – Timer/Counter4 Output Compare Register C Low Byte
Bit

7

6

5

NA ($AC)
Read/Write
Initial Value

4

3

2

1

0

OCR4CL7:0
R
0

RW
0

RW
0

RW
0

RW
0

OCR4CL
RW
0

RW
0

RW
0

The Output Compare Registers contain a 16-bit value that is continuously comparedwith the counter value (TCNT4). A match can be used to generate an Output Compareinterrupt. The Output Compare Registers are 16-bit in size. To ensure that both the highand low bytes are written simultaneously when the CPU writes to these registers, theaccess is performed using an 8-bit temporary High Byte Register (TEMP). This
temporary register is shared by all the other 16-bit registers. See section "Accessing 16bit Registers" for details.
• Bit 7:0 – OCR4CL7:0 - Timer/Counter4 Output Compare Register Low Byte

18.11.42 ICR4H – Timer/Counter4 Input Capture Register High Byte
Bit

7

6

5

4

R
0

R
0

R
0

R
0

NA ($A7)
Read/Write
Initial Value

3

2

1

0

R
0

R
0

R
0

ICR4H7:0
R
0

ICR4H

The Timer/Counter4 has only limited functionality. It is not connected to any I/O pin.
Therefore the contents of this register is never updated with the counter (TCNT4) value.
The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes
are read simultaneously when the CPU accesses these registers, the access isperformed using an 8-bit temporary High Byte Register (TEMP). This temporary register
is shared by all the other 16-bit registers. See section "Accessing 16-bit Registers" fordetails.
• Bit 7:0 – ICR4H7:0 - Timer/Counter4 Input Capture Register High Byte

18.11.43 ICR4L – Timer/Counter4 Input Capture Register Low Byte
Bit

7

6

5

NA ($A6)
Read/Write
Initial Value

4

3

2

1

0

ICR4L7:0
R
0

R
0

R
0

R
0

R
0

ICR4L
R
0

R
0

R
0

The Timer/Counter4 has only limited functionality. It is not connected to any I/O pin.
Therefore the contents of this register is never updated with the counter (TCNT4) value.
The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes
are read simultaneously when the CPU accesses these registers, the access isperformed using an 8-bit temporary High Byte Register (TEMP). This temporary register
is shared by all the other 16-bit registers. See section "Accessing 16-bit Registers" fordetails.
• Bit 7:0 – ICR4L7:0 - Timer/Counter4 Input Capture Register Low Byte

292

ATmega128RFA1
8266A-MCU Wireless-12/09

ATmega128RFA1
18.11.44 TIMSK4 – Timer/Counter4 Interrupt Mask Register
Bit

7

6

5

4

3

2

1

0

NA ($72)

Res1

Res0

ICIE4

Res

OCIE4COCIE4B

OCIE4A

TOIE4

Read/Write
Initial Value

R
0

R
0

RW
0

R
0

R
0

R
0

RW
0

RW
0

TIMSK4• Bit 7:6 – Res1:0 - Reserved Bit
This bit is reserved for future use. A read access always will return zero. A write accessdoes not modify the content.
• Bit 5 – ICIE4 - Timer/Counter4 Input Capture Interrupt Enable
The Timer/Counter4 has only limited functionality. It does not have an Input Capture
pin. Therefore this bit has no useful meaning.
• Bit 4 – Res - Reserved Bit
This bit is reserved for future use. A read access always will return zero. A write accessdoes not modify the content.
• Bit 3 – OCIE4C - Timer/Counter4 Output Compare C Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts
globally enabled), the Timer/Counter4 Output Compare C Match interrupt is enabled.
The corresponding Interrupt Vector is executed when the OCF4C Flag, located in
TIFR4, is set.
• Bit 2 – OCIE4B - Timer/Counter4 Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts
globally enabled), the Timer/Counter4 Output Compare B Match interrupt is enabled.
The corresponding Interrupt Vector is executed when the OCF4B Flag, located in
TIFR4, is set.
• Bit 1 – OCIE4A - Timer/Counter4 Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts
globally enabled), the Timer/Counter4 Output Compare A Match interrupt is enabled.
The corresponding Interrupt Vector is executed when the OCF4A Flag, located in
TIFR4, is set.
• Bit 0 – TOIE4 - Timer/Counter4 Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts
globally enabled), the Timer/Counter4 Overflow interrupt is enabled. The corresponding
Interrupt Vector is executed when the TOV4 Flag, located in TIFR4, is set.

18.11.45 TIFR4 – Timer/Counter4 Interrupt Flag Register
Bit

7

6

5

4

3

2

1

0

$19 ($39)

Res1

Res0

ICF4

Res

OCF4C

OCF4B

OCF4A

TOV4

Read/Write
Initial Value

R
0

R
0

RW
0

R
0

RW
0

RW
0

RW
0

RW
0

TIFR4

• Bit 7:6 – Res1:0 - Reserved Bit
This bit is reserved for future use. A read access always will return zero. A write accessdoes not modify the content.

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8266A-MCU Wireless-12/09

• Bit 5 – ICF4 - Timer/Counter4 Input Capture Flag
The Timer/Counter4 has only limited functionality. It does not have an Input Capture
pin. Therefore this bit has no useful meaning.
• Bit 4 – Res - Reserved Bit
This bit is reserved for future use. A read access always will return zero. A write accessdoes not modify the content.
• Bit 3 – OCF4C - Timer/Counter4 Output Compare C Match Flag
This flag is set in the timer clock cycle after the counter (TCNT4) value matches the
Output Compare Register C (OCR4C). Note that a Forced Output Compare (FOC4C)
strobe will not set the OCF4C Flag. OCF4C is automatically cleared when the Output
Compare Match C Interrupt Vector is executed. Alternatively, OCF4C can be cleared bywriting a logic one to its bit location.
• Bit 2 – OCF4B - Timer/Counter4 Output Compare B Match Flag
This flag is set in the timer clock cycle after the counter (TCNT4) value matches the
Output Compare Register B (OCR4B). Note that a Forced Output Compare (FOC4B)
strobe will not set the OCF4B Flag. OCF4B is automatically cleared when the Output
Compare Match B Interrupt Vector is executed. Alternatively, OCF4B can be cleared bywriting a logic one to its bit location.
• Bit 1 – OCF4A - Timer/Counter4 Output Compare A Match Flag
This flag is set in the timer clock cycle after the counter (TCNT4) value matches the
Output Compare Register A (OCR4A). Note that a Forced Output Compare (FOC4A)
strobe will not set the OCF4A Flag. OCF4A is automatically cleared when the Output
Compare Match A Interrupt Vector is executed. Alternatively, OCF4A can be cleared bywriting a logic one to its bit location.
• Bit 0 – TOV4 - Timer/Counter4 Overflow Flag
The setting of this flag is dependent of the WGM43:0 bits setting of the Timer/Counter4
Control Register. In Normal and CTC modes, the TOV4 Flag is set when the timer
overflows. TOV4 is automatically cleared when the Timer/Counter4 Overflow Interrupt
Vector is executed. Alternatively, TOV4 can be cleared by writing a logic one to its bit
location.

18.11.46 TCCR5A – Timer/Counter5 Control Register A
Bit
NA ($120)

7

6

5

4

3

2

1

0

COM5A1 COM5A0 COM5B1 COM5B0 COM5C1 COM5C0 WGM51

Read/Write
Initial Value

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

WGM50

TCCR5A

RW
0• Bit 7:6 – COM5A1:0 - Compare Output Mode for Channel A
The Timer/Counter5 has only limited functionality. Therefore the COM5A1:0 bits do notcontrol the output compare behavior of any pin. The following table shows the
COM5A1:0 bit functionality when the WGM53:0 bits are set to a normal or a CTC mode
(non-PWM). For the other functionality refer to section "Modes of Operation".
Table 18-24 COM5A Register Bits

294

Register Bits

Value

COM5A1:0

0

Description
Normal operation

ATmega128RFA1
8266A-MCU Wireless-12/09

ATmega128RFA1
Register Bits

Value

Description

1

Reserved

2

Reserved

3

Reserved• Bit 5:4 – COM5B1:0 - Compare Output Mode for Channel B
The Timer/Counter5 has only limited functionality. Therefore the COM5B1:0 bits do notcontrol the output compare behavior of any pin. The following table shows the
COM5B1:0 bit functionality when the WGM53:0 bits are set to a normal or a CTC mode
(non-PWM). For the other functionality refer to section "Modes of Operation".
Table 18-25 COM5B Register Bits
Register Bits

Value

Description

COM5B1:00

Normal operation

1

Reserved

2

Reserved

3

Reserved• Bit 3:2 – COM5C1:0 - Compare Output Mode for Channel C
The Timer/Counter5 has only limited functionality. Therefore the COM5C1:0 bits do notcontrol the output compare behavior of any pin. The following table shows the
COM5C1:0 bit functionality when the WGM53:0 bits are set to a normal or a CTC mode
(non-PWM). For the other functionality refer to section "Modes of Operation".
Table 18-26 COM5C Register Bits
Register Bits

Value

Description

COM5C1:00

Normal operation

1

Reserved

2

Reserved

3

Reserved• Bit 1:0 – WGM51:50 - Waveform Generation Mode
Combined with the WGM53:2 bits found in the TCCR5B Register, these bits control thecounting sequence of the counter, the source for maximum (TOP) counter value, andwhat type of waveform generation to be used. Modes of operation supported by theTimer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC)
mode, and three types of Pulse Width Modulation (PWM) modes. For more informationon the different modes see section "Modes of Operation". Note that Timer/Counter5 has
only limited functionality. It cannot be connected to any I/O pin.
Table 18-27 WGM5 Register Bits
Register Bits

Value

Description

WGM51:50

0x0

Normal mode of operation

0x1

PWM, phase correct, 8-bit

0x2

PWM, phase correct, 9-bit

0x3

PWM, phase correct, 10-bit

0x4

CTC, TOP = OCRnA

0x5

Fast PWM, 8-bit

0x6

Fast PWM, 9-bit

0x7

Fast PWM, 10-bit

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8266A-MCU Wireless-12/09

Register Bits

Value

Description

0x8

PWM, Phase and frequency correct, TOP =
ICRn

0x9

PWM, Phase and frequency correct, TOP =
OCRnA

0xA

PWM, Phase correct, TOP = ICRn

0xB

PWM, Phase correct, TOP = OCRnA

0xC

CTC, TOP = OCRnA

0xD

Reserved

0xE

Fast PWM, TOP = ICRn

0xF

Fast PWM, TOP = OCRnA

18.11.47 TCCR5B – Timer/Counter5 Control Register B
Bit

7

6

5

4

3

2

1

0

NA ($121)

ICNC5

ICES5

Res

WGM53

WGM52

CS52

CS51

CS50

Read/Write
Initial Value

RW
0

RW
0

R
0

RW
0

RW
0

RW
0

RW
0

RW
0

TCCR5B• Bit 7 – ICNC5 - Input Capture 5 Noise Canceller
Timer/Counter5 has only limited functionality. It is not connected to any Input Capture
Pin. Therefore this bit has no meaningful function.
• Bit 6 – ICES5 - Input Capture 5 Edge SelectTimer/Counter5 has only limited functionality. It is not connected to any Input Capture
Pin. Therefore this bit has no meaningful function.
• Bit 5 – Res - Reserved Bit
This bit is reserved for future use. A read access always will return zero. A write accessdoes not modify the content.
• Bit 4:3 – WGM51:50 - Waveform Generation Mode
Combined with the WGM51:0 bits found in the TCCR5A Register, these bits control thecounting sequence of the counter, the source for maximum (TOP) counter value, andwhat type of waveform generation to be used. Modes of operation supported by theTimer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC)
mode, and three types of Pulse Width Modulation (PWM) modes. For more informationon the different modes see section "Modes of Operation". Note that Timer/Counter5 has
only limited functionality. It cannot be connected to any I/O pin.
Table 18-28 WGM5 Register Bits

296

Register Bits

Value

Description

WGM51:50

0x0

Normal mode of operation

0x1

PWM, phase correct, 8-bit

0x2

PWM, phase correct, 9-bit

0x3

PWM, phase correct, 10-bit

0x4

CTC, TOP = OCRnA

0x5

Fast PWM, 8-bit

0x6

Fast PWM, 9-bit

ATmega128RFA1
8266A-MCU Wireless-12/09

ATmega128RFA1
Register Bits

Value

Description

0x7

Fast PWM, 10-bit

0x8

PWM, Phase and frequency correct, TOP =
ICRn

0x9

PWM, Phase and frequency correct, TOP =
OCRnA

0xA

PWM, Phase correct, TOP = ICRn

0xB

PWM, Phase correct, TOP = OCRnA

0xC

CTC, TOP = OCRnA

0xD

Reserved

0xE

Fast PWM, TOP = ICRn

0xF

Fast PWM, TOP = OCRnA• Bit 2:0 – CS52:50 - Clock SelectThe three clock select bits select the clock source to be used by the Timer/Counter5
according to the following table. External pin modes cannot be used for theTimer/Counter5.
Table 18-29 CS5 Register Bits
Register Bits

Value

Description

CS52:500x00

No clock source (Timer/Counter stopped)

0x01

clk_IO/1 (no prescaling)

0x02

clk_IO/8 (from prescaler)0x03

clk_IO/64 (from prescaler)0x04

clk_IO/256 (from prescaler)0x05

clk_IO/1024 (from prescaler)

0x06

Reserved

0x07

Reserved

18.11.48 TCCR5C – Timer/Counter5 Control Register C
Bit

7

6

5

4

3

2

1

0

NA ($122)

FOC5A

FOC5B

FOC5C

Res4

Res3

Res2

Res1

Res0

Read/Write
Initial Value

RW
0

RW
0

RW
0

R
0

R
0

R
0

R
0

R
0

TCCR5C• Bit 7 – FOC5A - Force Output Compare for Channel A
The FOC5A bit is only active when the WGM53:0 bits specify a non-PWM mode. When
writing a logical one to the FOC5A bit, an immediate compare match is forced. Due tothe limited functionality of the Timer/Counter5 the match has no direct impact on any
output pin. Note that the FOC5A bits are implemented as strobes. Therefore it is thevalue present in the COM5A1:0 bits that determine the effect of the forced compare. A
FOC5A strobe will not generate any interrupt nor will it clear the timer in Clear Timer on
Compare Match (CTC) mode using OCR5A as TOP. The FOC5A bits are always readas zero.
• Bit 6 – FOC5B - Force Output Compare for Channel B

297
8266A-MCU Wireless-12/09

The FOC5B bit is only active when the WGM53:0 bits specify a non-PWM mode. When
writing a logical one to the FOC5B bit, an immediate compare match is forced. Due tothe limited functionality of the Timer/Counter5 the match has no direct impact on any
output pin. Note that the FOC5B bits are implemented as strobes. Therefore it is thevalue present in the COM5B1:0 bits that determine the effect of the forced compare. A
FOC5B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on
Compare Match (CTC) mode using OCR5B as TOP. The FOC5B bits are always readas zero.
• Bit 5 – FOC5C - Force Output Compare for Channel C
The FOC5C bit is only active when the WGM53:0 bits specify a non-PWM mode. When
writing a logical one to the FOC5C bit, an immediate compare match is forced. Due tothe limited functionality of the Timer/Counter5 the match has no direct impact on any
output pin. Note that the FOC5C bits are implemented as strobes. Therefore it is thevalue present in the COM5C1:0 bits that determine the effect of the forced compare. A
FOC5C strobe will not generate any interrupt nor will it clear the timer in Clear Timer on
Compare Match (CTC) mode using OCR5C as TOP. The FOC5C bits are always readas zero.
• Bit 4:0 – Res4:0 - Reserved
These bits are reserved for future use.

18.11.49 TCNT5H – Timer/Counter5 High Byte
Bit

7

6

5

NA ($125)
Read/Write
Initial Value

4

3

2

1

0

TCNT5H7:0
RW
0

RW
0

RW
0

RW
0

RW
0

TCNT5H
RW
0

RW
0

RW
0

The two Timer/Counter I/O locations (TCNT5H and TCNT5L, combined TCNT5) give
direct access, both for read and for write operations, to the Timer/Counter unit 16-bit
counter. To ensure that both the high and low bytes are read and written simultaneously
when the CPU accesses these registers, the access is performed using an 8-bit
temporary High Byte Register (TEMP). This temporary register is shared by all the other16-bit registers. See section "Accessing 16-bit Registers" for details. Modifying thecounter (TCNT5) while the counter is running introduces a risk of missing a compare
match between TCNT5 and one of the OCR5x Registers. Writing to the TCNT5
Register blocks (removes) the compare match on the following timer clock for allcompare units.
• Bit 7:0 – TCNT5H7:0 - Timer/Counter5 High Byte

18.11.50 TCNT5L – Timer/Counter5 Low Byte
Bit

7

6

5

4

RW
0

RW
0

RW
0

RW
0

NA ($124)
Read/Write
Initial Value

3

2

1

0

RW
0

RW
0

RW
0

TCNT5L7:0
RW
0

TCNT5LThe two Timer/Counter I/O locations (TCNT5H and TCNT5L, combined TCNT5) give
direct access, both for read and for write operations, to the Timer/Counter unit 16-bit

298

ATmega128RFA1
8266A-MCU Wireless-12/09

ATmega128RFA1
counter. To ensure that both the high and low bytes are read and written simultaneously
when the CPU accesses these registers, the access is performed using an 8-bit
temporary High Byte Register (TEMP). This temporary register is shared by all the other16-bit registers. See section "Accessing 16-bit Registers" for details. Modifying thecounter (TCNT5) while the counter is running introduces a risk of missing a compare
match between TCNT5 and one of the OCR5x Registers. Writing to the TCNT5
Register blocks (removes) the compare match on the following timer clock for allcompare units.
• Bit 7:0 – TCNT5L7:0 - Timer/Counter5 Low Byte

18.11.51 OCR5AH – Timer/Counter5 Output Compare Register A High Byte
Bit

7

6

5

4

RW
0

RW
0

RW
0

RW
0

NA ($129)
Read/Write
Initial Value

3

2

1

0

RW
0

RW
0

RW
0

OCR5AH7:0
RW0

OCR5AHThe Output Compare Registers contain a 16-bit value that is continuously comparedwith the counter value (TCNT5). A match can be used to generate an Output Compareinterrupt. The Output Compare Registers are 16-bit in size. To ensure that both the highand low bytes are written simultaneously when the CPU writes to these registers, theaccess is performed using an 8-bit temporary High Byte Register (TEMP). This
temporary register is shared by all the other 16-bit registers. See section "Accessing 16bit Registers" for details.
• Bit 7:0 – OCR5AH7:0 - Timer/Counter5 Output Compare Register High Byte

18.11.52 OCR5AL – Timer/Counter5 Output Compare Register A Low Byte
Bit

7

6

5

NA ($128)
Read/Write
Initial Value

4

3

2

1

0

OCR5AL7:0
RW
0

RW
0

RW
0

RW
0

RW
0

OCR5AL
RW
0

RW
0

RW
0

The Output Compare Registers contain a 16-bit value that is continuously comparedwith the counter value (TCNT5). A match can be used to generate an Output Compareinterrupt. The Output Compare Registers are 16-bit in size. To ensure that both the highand low bytes are written simultaneously when the CPU writes to these registers, theaccess is performed using an 8-bit temporary High Byte Register (TEMP). This
temporary register is shared by all the other 16-bit registers. See section "Accessing 16bit Registers" for details.
• Bit 7:0 – OCR5AL7:0 - Timer/Counter5 Output Compare Register Low Byte

18.11.53 OCR5BH – Timer/Counter5 Output Compare Register B High Byte
Bit

7

6

5

NA ($12B)
Read/Write
Initial Value

4

3

2

1

0

OCR5BH7:0
RW
0

RW
0

RW
0

RW
0

RW
0

OCR5BH
RW
0

RW
0

RW
0

299
8266A-MCU Wireless-12/09

The Output Compare Registers contain a 16-bit value that is continuously comparedwith the counter value (TCNT5). A match can be used to generate an Output Compareinterrupt. The Output Compare Registers are 16-bit in size. To ensure that both the highand low bytes are written simultaneously when the CPU writes to these registers, theaccess is performed using an 8-bit temporary High Byte Register (TEMP). This
temporary register is shared by all the other 16-bit registers. See section "Accessing 16bit Registers" for details.
• Bit 7:0 – OCR5BH7:0 - Timer/Counter5 Output Compare Register High Byte

18.11.54 OCR5BL – Timer/Counter5 Output Compare Register B Low Byte
Bit

7

6

5

NA ($12A)
Read/Write
Initial Value

4

3

2

1

0

OCR5BL7:0
R
0

RW
0

RW
0

RW
0

RW
0

OCR5BL
RW
0

RW
0

RW
0

The Output Compare Registers contain a 16-bit value that is continuously comparedwith the counter value (TCNT5). A match can be used to generate an Output Compareinterrupt. The Output Compare Registers are 16-bit in size. To ensure that both the highand low bytes are written simultaneously when the CPU writes to these registers, theaccess is performed using an 8-bit temporary High Byte Register (TEMP). This
temporary register is shared by all the other 16-bit registers. See section "Accessing 16bit Registers" for details.
• Bit 7:0 – OCR5BL7:0 - Timer/Counter5 Output Compare Register Low Byte

18.11.55 OCR5CH – Timer/Counter5 Output Compare Register C High Byte
Bit

7

6

5

NA ($12D)
Read/Write
Initial Value

4

3

2

1

0

OCR5CH7:0
RW
0

RW
0

RW
0

RW
0

RW
0

OCR5CH
RW
0

RW
0

RW
0

The Output Compare Registers contain a 16-bit value that is continuously comparedwith the counter value (TCNT5). A match can be used to generate an Output Compareinterrupt. The Output Compare Registers are 16-bit in size. To ensure that both the highand low bytes are written simultaneously when the CPU writes to these registers, theaccess is performed using an 8-bit temporary High Byte Register (TEMP). This
temporary register is shared by all the other 16-bit registers. See section "Accessing 16bit Registers" for details.
• Bit 7:0 – OCR5CH7:0 - Timer/Counter5 Output Compare Register High Byte

300

ATmega128RFA1
8266A-MCU Wireless-12/09

ATmega128RFA1
18.11.56 OCR5CL – Timer/Counter5 Output Compare Register C Low Byte
Bit

7

6

5

NA ($12C)
Read/Write
Initial Value

4

3

2

1

0

OCR5CL7:0
R
0

RW
0

RW
0

RW
0

RW
0

OCR5CL
RW
0

RW
0

RW
0

The Output Compare Registers contain a 16-bit value that is continuously comparedwith the counter value (TCNT5). A match can be used to generate an Output Compareinterrupt. The Output Compare Registers are 16-bit in size. To ensure that both the highand low bytes are written simultaneously when the CPU writes to these registers, theaccess is performed using an 8-bit temporary High Byte Register (TEMP). This
temporary register is shared by all the other 16-bit registers. See section "Accessing 16bit Registers" for details.
• Bit 7:0 – OCR5CL7:0 - Timer/Counter5 Output Compare Register Low Byte

18.11.57 ICR5H – Timer/Counter5 Input Capture Register High Byte
Bit

7

6

5

4

R
0

R
0

R
0

R
0

NA ($127)
Read/Write
Initial Value

3

2

1

0

R
0

R
0

R
0

ICR5H7:0
R
0

ICR5H

The Timer/Counter5 has only limited functionality. It is not connected to any I/O pin.
Therefore the contents of this register is never updated with the counter (TCNT5) value.
The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes
are read simultaneously when the CPU accesses these registers, the access isperformed using an 8-bit temporary High Byte Register (TEMP). This temporary register
is shared by all the other 16-bit registers. See section "Accessing 16-bit Registers" fordetails.
• Bit 7:0 – ICR5H7:0 - Timer/Counter5 Input Capture Register High Byte

18.11.58 ICR5L – Timer/Counter5 Input Capture Register Low Byte
Bit

7

6

5

NA ($126)
Read/Write
Initial Value

4

3

2

1

0

ICR5L7:0
R
0

R
0

R
0

R
0

R
0

ICR5L
R
0

R
0

R
0

The Timer/Counter5 has only limited functionality. It is not connected to any I/O pin.
Therefore the contents of this register is never updated with the counter (TCNT5) value.
The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes
are read simultaneously when the CPU accesses these registers, the access isperformed using an 8-bit temporary High Byte Register (TEMP). This temporary register
is shared by all the other 16-bit registers. See section "Accessing 16-bit Registers" fordetails.
• Bit 7:0 – ICR5L7:0 - Timer/Counter5 Input Capture Register Low Byte

301
8266A-MCU Wireless-12/09

18.11.59 TIMSK5 – Timer/Counter5 Interrupt Mask Register
Bit

7

6

5

4

3

2

1

0

NA ($73)

Res1

Res0

ICIE5

Res

OCIE5COCIE5BOCIE5A

TOIE5

Read/Write
Initial Value

R
0

R
0

RW
0

R
0

R
0

R
0

RW
0

RW
0

TIMSK5• Bit 7:6 – Res1:0 - Reserved Bit
This bit is reserved for future use. A read access always will return zero. A write accessdoes not modify the content.
• Bit 5 – ICIE5 - Timer/Counter5 Input Capture Interrupt Enable
The Timer/Counter5 has only limited functionality. It does not have an Input Capture
pin. Therefore this bit has no useful meaning.
• Bit 4 – Res - Reserved Bit
This bit is reserved for future use. A read access always will return zero. A write accessdoes not modify the content.
• Bit 3 – OCIE5C - Timer/Counter5 Output Compare C Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts
globally enabled), the Timer/Counter5 Output Compare C Match interrupt is enabled.
The corresponding Interrupt Vector is executed when the OCF5C Flag, located in
TIFR5, is set.
• Bit 2 – OCIE5B - Timer/Counter5 Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts
globally enabled), the Timer/Counter5 Output Compare B Match interrupt is enabled.
The corresponding Interrupt Vector is executed when the OCF5B Flag, located in
TIFR5, is set.
• Bit 1 – OCIE5A - Timer/Counter5 Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts
globally enabled), the Timer/Counter5 Output Compare A Match interrupt is enabled.
The corresponding Interrupt Vector is executed when the OCF5A Flag, located in
TIFR5, is set.
• Bit 0 – TOIE5 - Timer/Counter5 Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts
globally enabled), the Timer/Counter5 Overflow interrupt is enabled. The corresponding
Interrupt Vector is executed when the TOV5 Flag, located in TIFR5, is set.

18.11.60 TIFR5 – Timer/Counter5 Interrupt Flag Register
Bit

7

6

5

4

3

2

1

0

$1A ($3A)

Res1

Res0

ICF5

Res

OCF5C

OCF5B

OCF5A

TOV5

Read/Write
Initial Value

R
0

R
0

RW
0

R
0

RW
0

RW
0

RW
0

RW
0

TIFR5

• Bit 7:6 – Res1:0 - Reserved Bit
This bit is reserved for future use. A read access always will return zero. A write accessdoes not modify the content.

302

ATmega128RFA1
8266A-MCU Wireless-12/09

ATmega128RFA1• Bit 5 – ICF5 - Timer/Counter5 Input Capture Flag
The Timer/Counter5 has only limited functionality. It does not have an Input Capture
pin. Therefore this bit has no useful meaning.
• Bit 4 – Res - Reserved Bit
This bit is reserved for future use. A read access always will return zero. A write accessdoes not modify the content.
• Bit 3 – OCF5C - Timer/Counter5 Output Compare C Match Flag
This flag is set in the timer clock cycle after the counter (TCNT5) value matches the
Output Compare Register C (OCR5C). Note that a Forced Output Compare (FOC5C)
strobe will not set the OCF5C Flag. OCF5C is automatically cleared when the Output
Compare Match C Interrupt Vector is executed. Alternatively, OCF5C can be cleared bywriting a logic one to its bit location.
• Bit 2 – OCF5B - Timer/Counter5 Output Compare B Match Flag
This flag is set in the timer clock cycle after the counter (TCNT5) value matches the
Output Compare Register B (OCR5B). Note that a Forced Output Compare (FOC5B)
strobe will not set the OCF5B Flag. OCF5B is automatically cleared when the Output
Compare Match B Interrupt Vector is executed. Alternatively, OCF5B can be cleared bywriting a logic one to its bit location.
• Bit 1 – OCF5A - Timer/Counter5 Output Compare A Match Flag
This flag is set in the timer clock cycle after the counter (TCNT5) value matches the
Output Compare Register A (OCR5A). Note that a Forced Output Compare (FOC5A)
strobe will not set the OCF5A Flag. OCF5A is automatically cleared when the Output
Compare Match A Interrupt Vector is executed. Alternatively, OCF5A can be cleared bywriting a logic one to its bit location.
• Bit 0 – TOV5 - Timer/Counter5 Overflow Flag
The setting of this flag is dependent of the WGM53:0 bits setting of the Timer/Counter5
Control Register. In Normal and CTC modes, the TOV5 Flag is set when the timer
overflows. TOV5 is automatically cleared when the Timer/Counter5 Overflow Interrupt
Vector is executed. Alternatively, TOV5 can be cleared by writing a logic one to its bit
location.

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19 Timer/Counter 0, 1, 3, 4, and 5 Prescaler
Timer/Counter 0, 1, 3, 4, and 5 share the same prescaler module, but theTimer/Counters can have different prescaler settings. The description below applies to
all Timer/Counters. Tn is used as a general name, n = 0, 1, 3, 4, or 5.

19.1 Internal Clock Source
The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 =1). This provides the fastest operation with a maximum Timer/Counter clock frequency
equal to system clock frequency (fCLK_I/O). Alternatively one of four taps from theprescaler can be used as a clock source. The prescaled clock has a frequency of either
fCLK_I/O/8, fCLK_I/O/64, fCLK_I/O/256 or fCLK_I/O/1024.

19.2 Prescaler Reset
The prescaler is free running, i.e., operates independently of the Clock Select logic of
the Timer/Counter, and it is shared by the Timer/Counter Tn. Since the prescaler is notaffected by the Timer/Counter’s clock select, the state of the prescaler will have
implications for situations where a prescaled clock is used. One example of prescaling
artifacts occurs when the timer is enabled and clocked by the prescaler (6 > CSn2:0 >1). The number of system clock cycles from the moment the timer is enabled until thefirst count occurs can be from 1 to N+1 system clock cycles, where N equals theprescaler divisor (8, 64, 256, or 1024).
It is possible to use the prescaler reset for synchronizing the Timer/Counter to program
execution. However care must be taken if the other Timer/Counter that shares the sameprescaler also uses prescaling. A prescaler reset will affect the prescaler period for allconnected Timer/Counters.

19.3 External Clock Source
An external clock source applied to the Tn pin can be used as Timer/Counter clock(clkTn). The Tn pin is sampled once every system clock cycle by the pin synchronization
logic. The synchronized (sampled) signal is then passed through the edge detector.
Figure 19-1 shows a functional equivalent block diagram of the Tn synchronization andedge detector logic. The registers are clocked at the positive edge of the internal
system clock (clkI/O). The latch is transparent in the high period of the internal system
clock.
The edge detector generates one clkTn pulse for each positive (CSn2:0 = 7) or negative(CSn2:0 = 6) edge it detects.
Figure 19-1. Tn/T0 Pin Sampling
Tn

D

Q

D

Q

D

Tn_sync(To ClockSelect Logic)Q

LE
clk I/O
Synchronization

Edge Detector

The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system
clock cycles from an edge applied to the Tn pin to the counter being updated.

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Enabling and disabling of the clock input must be done when Tn has been stable for atleast one system clock cycle. Otherwise there is a risk of generating a false
Timer/Counter clock pulse.
Each half period of the applied, external clock must be longer than one system clock
cycle to ensure correct sampling. The external clock must be guaranteed to have lessthan half the system clock frequency (fExtClk < fclk_I/O/2) given a 50/50% duty cycle. Since
the edge detector uses sampling, the maximum frequency of a detectable external
clock is half the sampling frequency (Nyquist sampling theorem). However due tovariation of the system clock frequency and duty cycle caused by Oscillator source(crystal, resonator and capacitors) tolerances, it is recommended to limit the maximum
frequency of an external clock source to less than fclk_I/O/2.5. An external clock source
can not be prescaled.
Figure 19-2. Prescaler for synchronous Timer/Counters
clk I/O

Clear

PSR10

Tn

Synchronization

Tn

Synchronization

CSn0

CSn0

CSn1

CSn1

CSn2

CSn2

TIMER/COUNTERn CLOCK SOURCE
clkTn

TIMER/COUNTERn CLOCK SOURCE
clkTn

19.4 Register Description
19.4.1 GTCCR – General Timer/Counter Control Register
Bit

7

6

5

4

3

2

$23 ($43)

TSM

Res4

Res3

Res2

Res1

Res0

Read/Write
Initial Value

RW
0

R
0

R
0

R
0

R
0

R
0

1

0

PSRASY PSRSYNC
R
0

GTCCR

RW
0

• Bit 7 – TSM - Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In thismode the value that is written to the PSRASY and PSRSYNC bits is kept, hence
keeping the corresponding prescaler reset signals asserted. This ensures that thecorresponding Timer/Counters are halted and can be configured to the same value
without the risk of one of them advancing during the configuration. When the TSM bit is
written to zero, the PSRASY and PSRSYNC bits are cleared by hardware and theTimer/Counters simultaneously start counting.
• Bit 6:2 – Res4:0 - Reserved

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This bit is reserved for future use. A read access always will return zero. A write accessdoes not modify the content.
• Bit 1 – PSRASY - Prescaler Reset Timer/Counter2
When this bit is one, the Timer/Counter2 prescaler will be reset. This bit is normally
cleared immediately by hardware. If the bit is written when Timer/Counter2 is operatingin asynchronous mode, the bit will remain one until the prescaler has been reset. The
bit will not be cleared by hardware if the TSM bit is set.
• Bit 0 – PSRSYNC - Prescaler Reset for Synchronous Timer/Counters
When this bit is one, the Timer/Counter0, Timer/Counter1, Timer/Counter3,
Timer/Counter4 and Timer/Counter5 prescaler will be reset. This bit is normally cleared
immediately by hardware, except if the TSM bit is set. Note that Timer/Counter0,
Timer/Counter1, Timer/Counter3, Timer/Counter4 and Timer/Counter5 share the sameprescaler and a reset of this prescaler will affect all timers.

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20 Output Compare Modulator (OCM1C0A)
20.1 Overview
The Output Compare Modulator (OCM) allows generation of waveforms modulated witha carrier frequency. The modulator uses the outputs from the Output Compare Unit C of
the 16-bit Timer/Counter1 and the Output Compare Unit of the 8-bit Timer/Counter0.
For more details about these Timer/Counters see "Timer/Counter 0, 1, 3, 4, and 5
Prescaler" on page 304 and "8-bit Timer/Counter2 with PWM and Asynchronous
Operation" on page 309.
Figure 20-1. Output Compare Modulator, Block Diagram
Timer/Counter 1

OC1C

Pin

Timer/Counter 0

OC1C /OC0A / PB7

OC0AWhen the modulator is enabled, the two output compare channels are modulated
together as shown in the block diagram (Figure 20-1 above).

20.2 Description
The Output Compare unit 1C and Output Compare unit 2 share the PB7 port pin for
output. The outputs of the Output Compare units (OC1C and OC0A) override thenormal PORTB7 Register when one of them is enabled (i.e., when COMnx1:0 is notequal to zero). When both OC1C and OC0A are enabled at the same time, themodulator is automatically enabled.
The functional equivalent schematic of the modulator is shown on in the following
figure. The schematic includes part of the Timer/Counter units and the port B bit 7
output driver circuit.
Figure 20-2. Output Compare Modulator, Schematic
COMA01
COMA00Vcc

COM1C1
COM1C0( From Waveform Generator )Modulator

0

D

1

Q

1

OC1C

Pin
0

( From Waveform Generator )D

Q

OC1C /
OC0A/ PB7

OC0A
D

Q

D

PORTB7QDDRB7DATABUS

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When the modulator is enabled the type of modulation (logical AND or OR) can beselected by the PORTB7 Register. Note that the DDRB7 controls the direction of theport independent of the COMnx1:0 bit setting.

20.3 Timing Example
Figure 20-3 below illustrates the modulator in action. In this example theTimer/Counter1 is set to operate in fast PWM mode (non-inverted) and Timer/Counter0
uses CTC waveform mode with toggle Compare Output mode (COMnx1:0 = 1).
Figure 20-3. Output Compare Modulator, Timing Diagram
clk I/O
OC1C(FPWM Mode)

OC0A(CTC Mode)

PB7(PORTB7 = 0)

PB7
(PORTB7 = 1)

(Period)12

3

In this example Timer/Counter2 provides the carrier while the modulating signal isgenerated by the Output Compare unit C of the Timer/Counter1.
The resolution of the PWM signal (OC1C) is reduced by the modulation. The reduction
factor is equal to the number of system clock cycles of one period of the carrier (OC0A).
In this example the resolution is reduced by a factor of two. The reason for the
reduction is illustrated in Figure 20-3 above at the second and third period of the PB7
output when PORTB7 equals zero. The period 2 high time is one cycle longer than the
period 3 high time, but the result on the PB7 output is equal in both periods.

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21 8-bit Timer/Counter2 with PWM and Asynchronous Operation
21.1 Features
Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module. The
main features are:• Single channel counter• Clear timer on compare match (auto reload)• Glitch-free, phase-correct pulse-width modulator (PWM)• Frequency generator• 10 bit clock prescaler• Overflow and compare match interrupt sources (TOV2, OCF2A and OCF2B)• Able to run with external 32 kHz watch crystal independent of the I/O clock21.2 Overview
A simplified block diagram of the 8-bit Timer/Counter is shown on Figure 21-1 on page310. For the current placement of I/O pins, see chapter "Pin Configurations" on page 2.
CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The
device-specific I/O Register and bit locations are listed in the "Register Description" onpage 323.
The Power Reduction Timer/Counter2 bit PRTIM2 in register PRR0 (see "PRR0 –Power Reduction Register0" on page 167) must be written to zero to enable
Timer/Counter2 module.
Note: OC2B is implemented but not routed to a pin and for this reason it can’t be used.
21.2.1 Registers
The Timer/Counter (TCNT2) and Output Compare Register (OCR2A and OCR2B) are 8
bit registers. Interrupt request (abbreviated to Int.Req.) signals are all visible in theTimer Interrupt Flag Register (TIFR2). All interrupts are individually masked with theTimer Interrupt Mask Register (TIMSK2). TIFR2 and TIMSK2 are not shown in the
figure.
The Timer/Counter can be clocked internally, via the prescaler, asynchronously clockedfrom the TOSC1/2 pins or alternatively from the Automated Meter Reading (AMR) pin
as detailed later in this section. The asynchronous operation is controlled by the
Asynchronous Status Register (ASSR). The Clock Select logic block controls whichclock source the Timer/Counter uses to increment (or decrement) its value. The
Timer/Counter is inactive when no clock source is selected. The output from the Clock
Select logic is referred to as the timer clock (clkT2).
The double buffered Output Compare Register (OCR2A and OCR2B) are comparedwith the Timer/Counter value at all times. The result of the compare can be used by the
Waveform Generator to generate a PWM or variable frequency output on the Output
Compare pins (OC2A and OC2B). See chapter "Output Compare Unit" on page 316 fordetails. The compare match event will also set the Compare Flag (OCF2A or OCF2B)
which can be used to generate an Output Compare interrupt request.
21.2.2 Definitions
Many register and bit references in this document are written in general form. A lower
case “n” replaces the Timer/Counter number, in this case 2. However, when using the309
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register or bit defines in a program, the precise form must be used, i.e., TCNT2 foraccessing Timer/Counter2 counter value and so on.

Figure 21-1. 8-bit Timer/Counter Block Diagram
TCCRnxcount

TOVn(Int.Req.)

clear

Control Logic

direction

BOTTOM

clkTn

TOP

TOSC1
Prescaler

T/C
Oscillator
TOSC2Timer/Counter
TCNTn

= 0

AMR

= 0x F F
OCnx(Int.Req.)

clkI/O

Waveform
Generation

=

OCnx

DATA BUS

OCRnx

Synchronized Status flags

clkI/O
Synchronization Unit
clkASY

Status flags

ASSRn
asynchronous mode
select (ASn)

The definitions in Table Table 21-1 below are also used extensively throughout thesection.
Table 21-1. Definitions
BOTTOM

The counter reaches the BOTTOM when it becomes zero (0x00).

MAX

The counter reaches its MAXimum when it becomes 0xFF (decimal 255).

TOP

The counter reaches the TOP when it becomes equal to the highest value in the
count sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX)or the value stored in the OCR2A Register. The assignment is dependent on themode of operation.

21.3 Timer/Counter Clock Sources
The Timer/Counter can be clocked by an internal synchronous or an external
asynchronous clock source. The clock source clkT2 is by default equal to the MCU
clock, clkI/O. When the AS2 bit in the ASSR Register is written to logic one, the clock
source is either taken from the Timer/Counter Oscillator connected to TOSC1 andTOSC2 or from the AMR pin. For details on asynchronous operation, see section
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ATmega128RFA1"Asynchronous Operation of Timer/Counter2" on page 320. For details on clock sources
and prescaler, see section "Timer/Counter Prescaler" on page 322.

21.4 Counter Unit
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter
unit. Figure 21-2 below shows a block diagram of the counter and its surrounding
environment.
Figure 21-2. Counter Unit Block Diagram
TOVn(Int.Req.)DATA BUS

TOSC1
count
TCNTn

clear

Control Logic

clkTn

Prescaler

T/C
Oscillator

directionbottom

TOSC2

top

AMR
cl k
I/O

Signal description (internal signals):count

Increment or decrement TCNT2 by 1.

direction

Selects between increment and decrement.

clear

Clear TCNT2 (set all bits to zero).

clkTnTimer/Counter clock, referred to as clkT2 in the following.

top

Signalizes that TCNT2 has reached maximum value.

bottomSignalizes that TCNT2 has reached minimum value (zero).

Depending on the mode of operation used, the counter is cleared, incremented, or
decremented at each timer clock (clkT2). clkT2 can be generated from an external orinternal clock source, selected by the Clock Select bits (CS22:0). When no clock source
is selected (CS22:0 = 0) the timer is stopped. However, the TCNT2 value can beaccessed by the CPU, regardless of whether clkT2 is present or not. A CPU write
overrides (has priority over) all counter clear or count operations.
The counting sequence is determined by the setting of the WGM21 and WGM20 bits
located in the Timer/Counter Control Register (TCCR2A) and the WGM22 located in theTimer/Counter Control Register B (TCCR2B). There are close connections between
how the counter behaves (counts) and how waveforms are generated on the Output
Compare outputs OC2A and OC2B. For more details about advanced counting
sequences and waveform generation, see chapter "Modes of Operation" below.
The Timer/Counter Overflow Flag (TOV2) is set according to the mode of operation
selected by the WGM22:0 bits. TOV2 can be used for generating a CPU interrupt.

21.5 Modes of Operation
The mode of operation, i.e., the behaviour of the Timer/Counter and the Output
Compare pins, is defined by the combination of the Waveform Generation mode
(WGM22:0) and Compare Output mode (COM2x1:0) bits. The Compare Output mode
bits do not affect the counting sequence, while the Waveform Generation mode bits do.
The COM2x1:0 bits control whether the PWM output generated should be inverted or
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not (inverted or non-inverted PWM). For non-PWM modes the COM2x1:0 bits control
whether the output should be set, cleared, or toggled at a compare match (see chapter"Compare Match Output Unit" on page 317).
For detailed timing information refer to chapter "Timer/Counter Timing Diagrams" onpage 319.
The following table shows the function of the WGM22:0 bits of registers TCCR2A and
TCCR2B. These bits control the counting sequence of the counter, the source for
maximum (TOP) counter value, and what type of waveform generation to be used.
Table 21-2. Waveform Generation Mode Bit Description

Mode

WGM2

WGM1

WGM0

Timer/Counter
Mode of
Operation

0

0

0

0

Normal0xFF

Immediate

MAX

1

0

0

1

PWM, Phase
Correct

0xFF

TOP

BOTTOM

2

0

1

0

CTC

OCRA

Immediate

MAX

3

0

1

1

Fast PWM

0xFF

TOP

MAX

4

1

0

0

Reserved

–

–

–

5

1

0

1

PWM, Phase
Correct

OCRA

TOP

BOTTOM

6

1

1

0

Reserved

–

–

–

7

1

1

1

Fast PWM

OCRA

BOTTOMTOP

Notes:

TOP

Update of
OCRX at

TOV Flag(1,2)
Set on1. MAX = 0xFF
2. BOTTOM = 0x00

21.5.1 Normal Mode
The simplest mode of operation is the Normal mode (WGM22:0 = 0). In this mode thecounting direction is always up (incrementing), and no counter clear is performed. The
counter simply overruns when it passes its maximum 8 bit value (TOP = 0xFF) and thenrestarts from the bottom (0x00). In normal operation the Timer/Counter Overflow Flag
(TOV2) will be set in the same timer clock cycle as the TCNT2 becomes zero. The
TOV2 Flag in this case behaves like a ninth bit, except that it is only set, not cleared.
However combined with the timer overflow interrupt that automatically clears the TOV2
Flag, the timer resolution can be increased by software. There are no special cases toconsider in the Normal mode, a new counter value can be written anytime.
The Output Compare unit can be used to generate interrupts at some given time. Using
the Output Compare to generate waveforms in Normal mode is not recommended,since this will occupy too much of the CPU time.
21.5.2 Clear Timer on Compare Match (CTC) ModeIn Clear Timer on Compare or CTC mode (WGM22:0 = 2), the OCR2A Register is used
to manipulate the counter resolution. In CTC mode the counter is cleared to zero when
the counter value (TCNT2) matches the OCR2A. The OCR2A defines the top value forthe counter, hence also its resolution. This mode allows greater control of the compare
match output frequency. It also simplifies the operation of counting external events.
The timing diagram for the CTC mode is shown in Table 20-3. The counter value(TCNT2) increases until a compare match occurs between TCNT2 and OCR2A, andthen counter (TCNT2) is cleared.

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Figure 21-3. CTC Mode, Timing Diagram
OCnx Interrupt Flag Set

TCNTn

OCn
(Toggle)Period(COMnx1:0 = 1)

1

2

3

4

An interrupt can be generated each time the counter value reaches the TOP value by
using the OCF2A Flag. If the interrupt is enabled, the interrupt handler routine can beused for updating the TOP value. However, changing TOP to a value close to BOTTOM
when the counter is running with none or a low prescaler value must be done with caresince the CTC mode does not have the double buffering feature. If the new value
written to OCR2A is lower than the current value of TCNT2, the counter will miss thecompare match. The counter will then have to count to its maximum value (0xFF) andwrap around starting at 0x00 before the compare match can occur.
For generating a waveform output in CTC mode, the OC2A output can be set to toggle
its logical level on each compare match by setting the Compare Output mode bits totoggle mode (COM2A1:0 = 1). The OC2A value will not be visible on the port pin unlessthe data direction for the pin is set to output. The waveform generated will have amaximum frequency of fOC2A = fclk_I/O/2 when OCR2A is set to zero (0x00). The
waveform frequency is defined by the following equationf OCnx =f clk _ I / O
2 ⋅ N ⋅ (1 + OCRnx)

The N variable represents the pre-scale factor (1, 8, 32, 64, 128, 256, or 1024).
As for the Normal mode of operation, the TOV2 Flag is set in the same timer clock cyclethat the counter counts from MAX to 0x00.
21.5.3 Fast PWM Mode
The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches TOP. If
the interrupt is enabled, the interrupt handler routine can be used for updating thecompare value.
In fast PWM mode, the compare unit allows generation of PWM waveforms on the
OC2x pin. Setting the COM2x1:0 bits to two will produce a non-inverted PWM and an
inverted PWM output can be generated by setting the COM2x1:0 to three. TOP isdefined as 0xFF when WGM22:0 = 3, and OCR2A when WGM22:0 = 7 (see section"Register Description" on page 323 for register TCCR2A). The actual OC2x value will
only be visible on the port pin if the data direction for the port pin is set as output. The
PWM waveform is generated by setting (or clearing) the OC2x Register at the compare
match between OCR2x and TCNT2, and clearing (or setting) the OC2x Register at the
timer clock cycle the counter is cleared (changes from TOP to BOTTOM).

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Figure 21-4. Fast PWM Mode, Timing Diagram
OCRnx Interrupt Flag Set

OCRnx Update and
TOVn Interrupt Flag Set

TCNTn

OCnx

(COMnx1:0 = 2)

OCnx

(COMnx1:0 = 3)

Period

1

2

3

4

5

6

7

The PWM frequency for the output can be calculated by the following equation:f OCnxPWM =f clk _ I / O
N ⋅ 256

The N variable represents the pre-scale factor (1, 8, 32, 64, 128, 256, or 1024).
The extreme values for the OCR2A Register represent special cases when generatinga PWM waveform output in the fast PWM mode. If the OCR2A is set equal to BOTTOM,
the output will be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR2A
equal to MAX will result in a constantly high or low output (depending on the polarity ofthe output set by the COM2A1:0 bits.)
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achievedby setting OC2x to toggle its logical level on each compare match (COM2x1:0 = 1). The
waveform generated will have a maximum frequency of foc2 = fclk_I/O/2 when OCR2A is
set to zero. This feature is similar to the OC2A toggle in CTC mode, except the double
buffer feature of the Output Compare unit is enabled in the fast PWM mode.
21.5.4 Phase Correct PWM Mode
The phase correct PWM mode (WGM22:0 = 1 or 5) provides a high resolution phasecorrect PWM waveform generation option. The phase correct PWM mode is based on adual-slope operation. The counter counts repeatedly from BOTTOM to TOP and thenfrom TOP to BOTTOM. TOP is defined as 0xFF when WGM22:0 = 1, and OCR2A when
WGM22:0 = 5. In non-inverting Compare Output mode, the Output Compare (OC2x) is
cleared on the compare match between TCNT2 and OCR2x while up-counting, and set
on the compare match while down-counting. In inverting Output Compare mode, theoperation is inverted. The dual-slope operation has lower maximum operation
frequency than single slope operation. However, due to the symmetric feature of thedual-slope PWM modes, these modes are preferred for motor control applications.
In phase correct PWM mode the counter is incremented until the counter value matches
TOP. When the counter reaches TOP, it changes the count direction. The TCNT2 value
will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct
PWM mode is shown on Figure 21-5 on page 315. The TCNT2 value is in the timing
diagram shown as a histogram for illustrating the dual-slope operation. The diagram

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includes non-inverted and inverted PWM outputs. The small horizontal line marks on
the TCNT2 slopes represent compare matches between OCR2x and TCNT2.
Figure 21-5. Phase Correct PWM Mode, Timing Diagram
OCnx Interrupt Flag Set

OCRnx Update

TOVn Interrupt Flag Set

TCNTn

OCnx

(COMnx1:0 = 2)

OCnx

(COMnx1:0 = 3)

Period1

2

3

The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches
BOTTOM. The Interrupt Flag can be used to generate an interrupt each time thecounter reaches the BOTTOM value.
In phase correct PWM mode, the compare unit allows generation of PWM waveforms
on the OC2x pin. Setting the COM2x1:0 bits to two will produce a non-inverted PWM.
An inverted PWM output can be generated by setting the COM2x1:0 to three. TOP isdefined as 0xFF when WGM22:0 = 3, and OCR2A when WGM22:0 = 7 (see section"Register Description" on page 323 for register TCCR2A). The actual OC2x value will
only be visible on the port pin if the data direction for the port pin is set as output. The
PWM waveform is generated by clearing (or setting) the OC2x Register at the compare
match between OCR2x and TCNT2 when the counter increments, and setting (orclearing) the OC2x Register at compare match between OCR2x and TCNT2 when the
counter decrements. The PWM frequency for the output when using phase correct
PWM can be calculated by the following equation:f OCnxPCPWM =f clk _ I / O
N ⋅ 510The N variable represents the pre-scale factor (1, 8, 32, 64, 128, 256, or 1024).
The extreme values for the OCR2A Register represent special cases when generatinga PWM waveform output in the phase correct PWM mode. If the OCR2A is set equal to
BOTTOM, the output will be continuously low and if set equal to MAX the output will be
continuously high for non-inverted PWM mode. For inverted PWM the output will havethe opposite logic values.
At the very start of period 2 in Figure 21-5 above OCnx has a transition from high to loweven though there is no Compare Match. The point of this transition is to guarantee
symmetry around BOTTOM. There are two cases that give a transition without
Compare Match.
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• OCR2A changes its value from MAX, like in Figure 21-5 on page 315. When the
OCR2A value is MAX the OCn pin value is the same as the result of a downcounting compare match. To ensure symmetry around BOTTOM the OCn value at
MAX must correspond to the result of an up-counting Compare Match.
• The timer starts counting from a value higher than the one in OCR2A, and for thatreason misses the Compare Match and hence the OCn change that would have
happened on the way up.

21.6 Output Compare Unit
The 8 bit comparator continuously compares TCNT2 with the Output Compare Register(OCR2A and OCR2B). Whenever TCNT2 equals OCR2A or OCR2B, the comparator
signals a match. A match will set the Output Compare Flag (OCF2A or OCF2B) at thenext timer clock cycle. If the corresponding interrupt is enabled, the Output Compare
Flag generates an Output Compare interrupt. The Output Compare Flag is
automatically cleared when the interrupt is executed. Alternatively, the Output Compare
Flag can be cleared by software by writing a logical one to its I/O bit location. The
Waveform Generator uses the match signal to generate an output according tooperating mode set by the WGM22:0 bits and Compare Output mode (COM2x1:0) bits.
The max and bottom signals are used by the Waveform Generator for handling thespecial cases of the extreme values in some modes of operation (chapter "Modes ofOperation" on page 311).
Figure 21-6 below shows a block diagram of the Output Compare unit.
Figure 21-6. Output Compare Unit, Block Diagram
DATA BUS

OCRn

TCNTn

= (8-bit Comparator )OCFn (Int.Req.)

topbottomWaveform Generator

OCxy

FOCn

WGMn1:0

COMn1:0

The OCR2x Register is double buffered when using any of the Pulse Width Modulation(PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes ofoperation, the double buffering is disabled. The double buffering synchronizes the
update of the OCR2x Compare Register to either top or bottom of the counting
sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical
PWM pulses, thereby making the output glitch-free.

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ATmega128RFA1The OCR2x Register access may seem complex, but this is not the case. When the
double buffering is enabled, the CPU has access to the OCR2x Buffer Register, and if
double buffering is disabled the CPU will access the OCR2x directly.
21.6.1 Force Output Compare
In non-PWM waveform generation modes, the match output of the comparator can beforced by writing a one to the Force Output Compare (FOC2x) bit. Forcing compare
match will not set the OCF2x Flag or reload/clear the timer, but the OC2x pin will be
updated as if a real compare match had occurred (the COM2x1:0 bits settings define
whether the OC2x pin is set, cleared or toggled).
21.6.2 Compare Match Blocking by TCNT2 Write
All CPU write operations to the TCNT2 Register will block any compare match that
occurs in the next timer clock cycle, even when the timer is stopped. This feature allows
OCR2x to be initialized to the same value as TCNT2 without triggering an interrupt
when the Timer/Counter clock is enabled.
21.6.3 Using the Output Compare Unit
Since writing TCNT2 in any mode of operation will block all compare matches for one
timer clock cycle, there are risks involved when changing TCNT2 when using the
Output Compare channel, independently of whether the Timer/Counter is running or
not. If the value written to TCNT2 equals the OCR2x value, the compare match will bemissed, resulting in incorrect waveform generation. Similarly, do not write the TCNT2
value equal to BOTTOM when the counter is down-counting.
The setup of the OC2x should be performed before setting the Data Direction Registerfor the port pin to output. The easiest way of setting the OC2x value is to use the Force
Output Compare (FOC2x) strobe bit in Normal mode. The OC2x Register keeps its
value even when changing between Waveform Generation modes.
Be aware that the COM2x1:0 bits are not double buffered together with the compare
value. A change of the COM2x1:0 bits will take effect immediately.

21.7 Compare Match Output Unit
The Compare Output mode (COM2x1:0) bits have two functions. The Waveform
Generator uses the COM2x1:0 bits for defining the Output Compare (OC2x) state at thenext compare match. Also, the COM2x1:0 bits control the OC2x pin output source.
Figure 20-7 shows a simplified schematic of the logic affected by the COM2x1:0 bit
setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only
the parts of the general I/O Port Control Registers (DDR and PORT) that are affectedby the COM2x1:0 bits are shown. When referring to the OC2x state, the reference is forthe internal OC2x Register, not the OC2x pin.
The general I/O port function is overridden by the Output Compare (OC2x) from the
Waveform Generator if either of the COM2x1:0 bits are set. However, the OC2x pin
direction (input or output) is still controlled by the Data Direction Register (DDR) for the
port pin. The Data Direction Register bit for the OC2x pin (DDR_OC2x) must be set as
output before the OC2x value is visible on the pin. The port override function is
independent of the Waveform Generation mode.
The design of the Output Compare pin logic allows initialization of the OC2x state
before the output is enabled. Note that some COM2x1:0 bit settings are reserved forcertain modes of operation. See section "Register Description" on page 323 for details.

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Figure 21-7. Compare Match Output Unit, Schematic

COMnx1
COMnx0
FOCn

Waveform
Generator

D

Q
1

OCnx

DATA BUS

D

0

OCnx
Pin

Q

PORT
D

Q

DDR
clk I/O

21.7.1 Compare Output Mode and Waveform Generation
The Waveform Generator uses the COM2x1:0 bits differently in normal, CTC, and PWM
modes. Setting the COM2x1:0 = 0 for all modes tells the Waveform Generator that noaction on the OC2x Register is to be performed on the next compare match. For
compare output actions in the non-PWM modes for fast PWM mode and for phasecorrect PWM refer to section "Register Description" on page 323 for register TCCR2A.
A change of the COM2x1:0 bits state will have effect at the first compare match after
the bits are written. For non-PWM modes, the action can be forced to have immediate
effect by using the FOC2x strobe bits.
The following table shows the COM2x1:0 bit functionality when the WGM02:0 bits are
set to a normal or CTC mode (non-PWM).
Table 21-3. Compare Output Mode, non-PWM Mode
COM2x1COM2x000Normal port operation, OC2x disconnected;

Description

0

1

Toggle OC2x on Compare Match;

10

Clear OC2x on Compare Match;

1

1

Set OC2x on Compare Match;

Table 17-3 shows the COM2x1:0 bit functionality when the WGM21:0 bits are set to fast
PWM mode.
Table 21-4. Compare Output Mode, Fast PWM Mode

318

COM2x1COM2x0Description00Normal port operation, OC2x disconnected.

0

1

WGM22 = 0: Normal Port Operation, OC2A Disconnected.
WGM22 = 1: Toggle OC2A on Compare Match.
OC2B: not applicable, reserved function;

ATmega128RFA1
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ATmega128RFA1COM2x1COM2x01

0

Clear OC2x on Compare Match, set OC2x at BOTTOM, (noninverting mode).

1

1

Set OC2x on Compare Match, clear OC2x at BOTTOM, (invertingmode).

Note:

Description

1. A special case occurs when OCR2x equals TOP and COM2x1 is set. In this case,
the Compare Match is ignored, but the set or clear is done at BOTTOM. See "FastPWM Mode" on page 313.

Table 17-4 shows the COM2x1:0 bit functionality when the WGM22:0 bits are set tophase correct PWM mode.
Table 21-5. Compare Output Mode, Phase Correct PWM Mode
COM2x1COM2x000Normal port operation, OC2x disconnected.

0

1

WGM22 = 0: Normal Port Operation, OC2A Disconnected.
WGM22 = 1: Toggle OC2A on Compare Match.
OC2B: not applicable, reserved function;

1

0

Clear OC2x on Compare Match when up-counting. Set OC2x on
Compare Match when down-counting.

1

1

Set OC2x on Compare Match when up-counting. Clear OC2x on
Compare Match when down-counting.

Note:

Description

1. A special case occurs when OCR2x equals TOP and COM2x1 is set. In this case,
the Compare Match is ignored, but the set or clear is done at TOP. See "Phase
Correct PWM Mode" on page 314 for more details.

21.8 Timer/Counter Timing Diagrams
The following figures show the Timer/Counter in synchronous mode, and the timer clock(clkT2) is therefore shown as a clock enable signal. In asynchronous mode, clkI/O should
be replaced by the Timer/Counter Oscillator clock. The figures include information onwhen Interrupt Flags are set. Figure 21-8 below contains timing data for basic
Timer/Counter operation. The figure shows the count sequence close to the MAX value
in all modes other than phase correct PWM mode.
Figure 21-8. Timer/Counter Timing Diagram, no Prescaling
clkI/O
clkTn(clkI/O /1)

TCNTn

MAX - 1MAX

BOTTOM

BOTTOM + 1

TOVn

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Figure 21-9 below shows the same timing data, but with the prescaler enabled.
Figure 21-9. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)
clkI/O
clkTn(clkI/O /8)

TCNTn

MAX - 1MAX

BOTTOM

BOTTOM + 1

TOVn

Figure 21-10 below shows the setting of OCF2A in all modes except CTC mode.
Figure 21-10. Timer/Counter Timing Diagram, Setting of OCF2A, with Prescaler(fclk_I/O/8)
clkI/O
clkTn(clkI/O /8)

TCNTn

OCRnx - 1

OCRnx

OCRnx + 1

OCRnx + 2

OCRnx Value

OCRnx

OCFnx

Figure 21-11 below shows the setting of OCF2A and the clearing of TCNT2 in CTC
mode.
Figure 21-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode,with Prescaler (fclk_I/O/8)
clkI/O
clkTn(clkI/O /8)

TCNTn
(CTC)

TOP - 1

OCRnx

TOP

BOTTOM

BOTTOM + 1

TOP

OCFnx

21.9 Asynchronous Operation of Timer/Counter2
When Timer/Counter2 operates asynchronously, some considerations must be taken.

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ATmega128RFA1• Warning: When switching between asynchronous and synchronous clocking ofTimer/Counter2, the Timer Registers TCNT2, OCR2x, and TCCR2x might becorrupted. A safe procedure for switching clock source is:
1. Disable the Timer/Counter2 interrupts by clearing OCIE2x and TOIE2.
2. Select clock source by setting AS2 as appropriate.
3. Write new values to TCNT2, OCR2x, and TCCR2x.
4. To switch to asynchronous operation: Wait for TCN2UB, OCR2xUB, and TCR2xUB.
5. Clear the Timer/Counter2 Interrupt Flags.
6. Enable interrupts, if needed.
• The CPU main clock frequency must be more than four times the Oscillator
frequency.
• When writing to one of the registers TCNT2, OCR2x, or TCCR2x, the value istransferred to a temporary register, and latched after two positive edges on TOSC1.
The user should not write a new value before the contents of the temporary register
have been transferred to its destination. Each of the five mentioned registers havetheir individual temporary register, which means that e.g. writing to TCNT2 does not
disturb an OCR2x write in progress. To detect that a transfer to the destination
register has taken place, the Asynchronous Status Register – ASSR has been
implemented.
• When entering Power-save or ADC Noise Reduction mode after having written to
TCNT2, OCR2x, or TCCR2x, the user must wait until the written register has been
updated if Timer/Counter2 is used to wake up the device. Otherwise, the MCU willenter sleep mode before the changes are effective. This is particularly important if
any of the Output Compare2 interrupt is used to wake up the device, since the
Output Compare function is disabled during writing to OCR2x or TCNT2. If the write
cycle is not finished, and the MCU enters sleep mode before the corresponding
OCR2xUB bit returns to zero, the device will never receive a compare matchinterrupt, and the MCU will not wake up.
• If Timer/Counter2 is used to wake the device up from Power-save or ADC Noise
Reduction mode, precautions must be taken if the user wants to re-enter one ofthese modes: The interrupt logic needs one TOSC1 cycle to be reset. If the time
between wake-up and re-entering sleep mode is less than one TOSC1 cycle, theinterrupt will not occur, and the device will fail to wake up. If the user is in doubt
whether the time before re-entering Powersave or ADC Noise Reduction mode issufficient, the following algorithm can be used to ensure that one TOSC1 cycle has
elapsed:1. Write a value to TCCR2x, TCNT2, or OCR2x.
2. Wait until the corresponding Update Busy Flag in ASSR returns to zero. .
3. Enter Power-save or ADC Noise Reduction mode.
• When the asynchronous operation is selected, the 32.768 kHz Oscillator forTimer/Counter2 is always running, except in Power-down and Standby modes. Aftera Power-up Reset or wake-up from Power-down or Standby mode, the user should
be aware of the fact that this Oscillator might take as long as one second to stabilize.
The user is advised to wait for at least one second before using Timer/Counter2
after power-up or wake-up from Power-down or Standby mode. The contents of all
Timer/Counter2 Registers must be considered lost after a wake-up from Powerdown or Standby mode due to unstable clock signal upon start-up, no matter
whether the Oscillator is in use or a clock signal is applied to the TOSC1 pin.
• Description of wake up from Power-save or ADC Noise Reduction mode when thetimer is clocked asynchronously: When the interrupt condition is met, the wake up
process is started on the following cycle of the timer clock, that is, the timer is always
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advanced by at least one before the processor can read the counter value. After
wake-up, the MCU is halted for four cycles, it executes the interrupt routine, andresumes execution from the instruction following SLEEP.
• Reading of the TCNT2 Register shortly after wake-up from Power-save may give an
incorrect result. Since TCNT2 is clocked on the asynchronous TOSC clock, reading
TCNT2 must be done through a register synchronized to the internal I/O clock
domain. Synchronization takes place for every rising TOSC1 edge. When waking up
from Powersave mode, and the I/O clock (clkI/O) again becomes active, TCNT2 will
read as the previous value (before entering sleep) until the next rising TOSC1 edge.
The phase of the TOSC clock after waking up from Power-save mode is essentiallyunpredictable, as it depends on the wake-up time. The recommended procedure forreading TCNT2 is thus as follows:
1. Write any value to either of the registers OCR2x or TCCR2x.
2. Wait for the corresponding Update Busy Flag to be cleared.
3. Read TCNT2.
• During asynchronous operation, the synchronization of the Interrupt Flags for the
asynchronous timer takes 3 processor cycles plus one timer cycle. The timer istherefore advanced by at least one before the processor can read the timer valuecausing the setting of the Interrupt Flag. The Output Compare pin is changed on thetimer clock and is not synchronized to the processor clock.
• If the CPU wakes up from asynchronous timer and goes back to sleep again, it may
wakeup multiple times or the IRQ is called multiple times. This may be avoided if the
CPU waits with the next sleep instruction until the next asynchronous clock arrives.

21.10 Timer/Counter Prescaler
Figure 21-12. Prescaler for Timer/Counter2
clkI/O

clkT2S/1024

EXCLKAMR

clkT2S / 256

clkT2S / 128

clkT2S/64

10-BI T T/C PRES CA LER

Clear

clkT2S/32

AMR

clkT2S
clkT2S/ 8

TOSC1

AS2
PS RASY

0

CS20
CS21
CS22

TIMER/ COUNTER2 CLOCK SOURCE
clkT2

The register ASSR defines the clock source for the asynchronous Timer/Counter2. The
clock source for Timer/Counter2 is named clkT2S. clkT2S is by default connected to themain system I/O clock clkIO. By setting the AS2 bit in ASSR, Timer/Counter2 isasynchronously clocked either from the TOSC1 or from the AMR pin. This enables theuse of Timer/Counter2 as a Real Time Counter (RTC).

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ATmega128RFA1
The TOSC1 pin is selected by setting the EXCLKAMR bit in the ASSR register to logic
zero. Under this condition TOSC1 and TOSC2 are disconnected from Port G and acrystal can then be connected between the TOSC1 and TOSC2 pins to serve as anindependent clock source for Timer/Counter2. The Oscillator is optimized for use with a
32.768 kHz crystal. By setting the EXCLK bit in the ASSR, a 32 kHz external clock can
be applied on TOSC1.
Setting the EXCLKAMR bit to logic one selects the AMR pin as the Timer/Counter2
clock source. Thus the 32 kHz oscillator can be used by the MAC symbol counter while
the Timer/Counter2 uses pin AMR as clock source, see "MAC Symbol Counter" on
page 133.
A complete overview of the implemented asynchronous clock sources can be found in
Table 21-6 below. The last column mentions which pins are available for GPIO
functionality. For details about the ASSR register refer to section "Register Description"
below.
For Timer/Counter2, the possible pre-scaled selections are: clkT2S/8, clkT2S/32, clkT2S/64, clkT2S/128, clkT2S/256, and clkT2S/1024. Additionally, clkT2S as well as 0 (stop) may
be selected. Setting the PSRASY bit in GTCCR resets the prescaler. This allows theuser to operate with a predictable prescaler.
Table 21-6. Asynchronous clock selection for Timer/Counter2 and Symbol-Counter
AS2

EXCLK

EXCLKAMR

Timer/Counter2
clock source

32 kHz crystal Osc.
(TOSC1/TOSC2)

PG2, PG3, PG4
as GPIOs

0

0

0

cp2io

off

PG2, PG3, PG4

0

1

0

not defined

not defined

not defined

1

0

0

32 kHz crystal Osc

on

PG2

1

1

0

TOSC1 (PG4)

off

PG2, PG3

0

0

1

cp2io

off

PG2, PG3, PG4

0

1

1

not defined

not defined

not defined

1

0

1

AMR (PG2)

on

1

1

1

AMR (PG2)

off

PG3, PG4

21.11 Register Description
21.11.1 TIMSK2 – Timer/Counter Interrupt Mask register
Bit

7

6

5

4

3

2

1

0

NA ($70)

Res4

Res3

Res2

Res1

Res0

OCIE2BOCIE2A

TOIE2

Read/Write
Initial Value

R
0

R
0

R
0

R
0

R
0

RW
0

RW
0

RW
0

TIMSK2• Bit 7:3 – Res4:0 - Reserved Bit
This bit is reserved for future use. A read access always will return zero. A write accessdoes not modify the content.
• Bit 2 – OCIE2B - Timer/Counter2 Output Compare Match B Interrupt Enable
When the OCIE2B bit is written to one and the I-bit in the Status Register is set (one),
the Timer/Counter2 Compare Match B interrupt is enabled. The corresponding interrupt
is executed if a compare match in Timer/Counter2 occurs, i.e., when the OCF2B bit isset in the Timer/Counter2 Interrupt Flag Register TIFR2.

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• Bit 1 – OCIE2A - Timer/Counter2 Output Compare Match A Interrupt Enable
When the OCIE2A bit is written to one and the I-bit in the Status Register is set (one),
the Timer/Counter2 Compare Match A interrupt is enabled. The corresponding interrupt
is executed if a compare match in Timer/Counter2 occurs, i.e., when the OCF2A bit isset in the Timer/Counter2 Interrupt Flag Register TIFR2.
• Bit 0 – TOIE2 - Timer/Counter2 Overflow Interrupt Enable
When the TOIE2 bit is written to one and the I-bit in the Status Register is set (one), theTimer/Counter2 Overflow interrupt is enabled. The corresponding interrupt is executed
if an overflow in Timer/Counter2 occurs i.e., when the TOV2 bit is set in theTimer/Counter2 Interrupt Flag Register TIFR2.

21.11.2 TIFR2 – Timer/Counter Interrupt Flag Register
Bit

7

6

5

4

3

2

1

0

$17 ($37)

Res4

Res3

Res2

Res1

Res0

OCF2B

OCF2A

TOV2

Read/Write
Initial Value

R
0

R
0

R
0

R
0

R
0

RW
0

RW
0

RW
0

TIFR2

• Bit 7:3 – Res4:0 - Reserved Bit
This bit is reserved for future use. A read access always will return zero. A write accessdoes not modify the content.
• Bit 2 – OCF2B - Output Compare Flag 2 B
The OCF2B bit is set (one) when a compare match occurs between the Timer/Counter2
and the data in OCR2B Output Compare Register2. OCF2B is cleared by hardware
when executing the corresponding interrupt handling vector. Alternatively, OCF2B iscleared by writing a logic one to the flag. When the I-bit in SREG, OCIE2B(Timer/Counter2 Compare Match Interrupt Enable), and OCF2B are set (one), theTimer/Counter2 Compare Match Interrupt is executed.
• Bit 1 – OCF2A - Output Compare Flag 2 A
The OCF2A bit is set (one) when a compare match occurs between the Timer/Counter2
and the data in OCR2A Output Compare Register2. OCF2A is cleared by hardware
when executing the corresponding interrupt handling vector. Alternatively, OCF2A iscleared by writing a logic one to the flag. When the I-bit in SREG, OCIE2A(Timer/Counter2 Compare Match Interrupt Enable), and OCF2A are set (one), theTimer/Counter2 Compare Match Interrupt is executed.
• Bit 0 – TOV2 - Timer/Counter2 Overflow Flag
The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is clearedby hardware when executing the corresponding interrupt handling vector. Alternatively,
TOV2 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE2A(Timer/Counter2 Overflow Interrupt Enable), and TOV2 are set (one), theTimer/Counter2 Overflow interrupt is executed. In PWM mode, this bit is set whenTimer/Counter2 changes counting direction at 0x00.

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ATmega128RFA1
21.11.3 TCCR2A – Timer/Counter2 Control Register A
Bit
NA ($B0)

7

6

5

4

COM2A1 COM2A0 COM2B1 COM2B0

Read/Write
Initial Value

RW
0

RW
0

RW
0

RW
0

3

2

1

0

Res1

Res0

WGM21

WGM20

RW
0

RW
0

RW
0

RW
0

TCCR2A• Bit 7:6 – COM2A1:0 - Compare Match Output A Mode
These bits control the Output Compare pin (OC2A) behavior. If one or both of the
COM2A1:0 bits are set, the OC2A output overrides the normal port functionality of the
I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit
corresponding to the OC2A pin must be set in order to enable the output driver. When
OC2A is connected to the pin, the function of the COM2A1:0 bits depends on the
WGM22:0 bit setting. The following table shows the COM2A1:0 bit functionality when
the WGM22:0 bits are set to a normal or CTC mode (non-PWM). Refer to section"Compare Match Output Unit" for a description of the functionality in the other modes.
Table 21-7 COM2A Register Bits
Register Bits

Value

Description

COM2A1:00

Normal port operation, OC2A disconnected

1

Toggle OC2A on Compare Match

2

Clear OC2A on Compare Match

3

Set OC2A on Compare Match• Bit 5:4 – COM2B1:0 - Compare Match Output B Mode
These bits control the Output Compare pin (OC2B) behavior. If one or both of theCOM2B1:0 bits are set, the OC2B output overrides the normal port functionality of the
I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit
corresponding to the OC2B pin must be set in order to enable the output driver. When
OC2B is connected to the pin, the function of the COM2B1:0 bits depends on the
WGM22:0 bit setting. The following table shows the COM2B1:0 bit functionality when
the WGM22:0 bits are set to a normal or CTC mode (non-PWM). Refer to section"Compare Match Output Unit" for a description of the functionality in the other modes.
Table 21-8 COM2B Register Bits
Register Bits

Value

Description

COM2B1:00

Normal port operation, OC2B disconnected

1

Toggle OC2B on Compare Match

2

Clear OC2B on Compare Match

3

Set OC2B on Compare Match• Bit 3:2 – Res1:0 - Reserved• Bit 1:0 – WGM21:20 - Waveform Generation Mode
Combined with the WGM22 bit found in the TCCR2B Register, these bits control thecounting sequence of the counter, the source for maximum (TOP) counter value, andwhat type of waveform generation to be used. Modes of operation supported by theTimer/Counter2 unit are: Normal mode (counter), Clear Timer on Compare Match(CTC) mode, and two types of Pulse Width Modulation (PWM) modes (see section"Modes of Operation" for details).

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Table 21-9 WGM2 Register Bits
Register Bits

Value

Description

WGM21:20

0x0

Normal mode of operation

0x1

PWM, phase correct, TOP=0xFF

0x2

CTC, TOP = OCRA

0x3

Fast PWM, TOP=0xFF

0x4

Reserved

0x5

PWM, Phase correct, TOP = OCRA

0x6

Reserved

0x7

Fast PWM, TOP=OCRA

21.11.4 TCCR2B – Timer/Counter2 Control Register B
Bit

7

6

5

4

3

2

1

0

NA ($B1)

FOC2A

FOC2B

Res1

Res0

WGM22

CS22

CS21

CS20

Read/Write
Initial Value

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

TCCR2B• Bit 7 – FOC2A - Force Output Compare A
The FOC2A bit is only active when the WGM bits specify a non-PWM mode. However,for ensuring compatibility with future devices, this bit must be set to zero when TCCR2B
is written in PWM mode operation. When writing a logical one to the FOC2A bit, animmediate Compare Match is forced on the Waveform Generation unit. The OC2A
output is changed according to its COM2A1:0 bits setting. Note that the FOC2A bit is
implemented as a strobe. Therefore it is the value present in the COM2A1:0 bits that
determines the effect of the forced compare. A FOC2A strobe will not generate any
interrupt, nor will it clear the timer in CTC mode using OCR2A as TOP. The FOC2A bit
is always read as zero.
• Bit 6 – FOC2B - Force Output Compare B
The FOC2B bit is only active when the WGM bits specify a non-PWM mode. However,for ensuring compatibility with future devices, this bit must be set to zero when TCCR2B
is written in PWM mode operation. When writing a logical one to the FOC2B bit, animmediate Compare Match is forced on the Waveform Generation unit. The OC2B
output is changed according to its COM2B1:0 bits setting. Note that the FOC2B bit is
implemented as a strobe. Therefore it is the value present in the COM2B1:0 bits that
determines the effect of the forced compare. A FOC2B strobe will not generate any
interrupt, nor will it clear the timer in CTC mode using OCR2B as TOP. The FOC2B bit
is always read as zero.
• Bit 5:4 – Res1:0 - Reserved• Bit 3 – WGM22 - Waveform Generation Mode
Combined with the WGM21:0 bits found in the TCCR2A Register, this bit controls thecounting sequence of the counter, the source for maximum (TOP) counter value, andwhat type of waveform generation to be used. See description of "TCCR2A Timer/Counter2 Control Register A" for details.
• Bit 2:0 – CS22:20 - Clock SelectThe three Clock Select bits select the clock source to be used by the Timer/Counter2. If
external pin modes are used for the Timer/Counter2, transitions on the T2 pin will clock326

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ATmega128RFA1
the counter even if the pin is configured as an output. This feature allows software
control of the counting.
Table 21-10 CS2 Register Bits
Register Bits

Value

Description

CS22:200x00

No clock source (Timer/Counter2 stopped)

0x01

clk_T2S/1 (no prescaling)

0x02

clk_T2S/8 (from prescaler)

0x03

clk_T2S/32 (from prescaler)

0x04

clk_T2S/64 (from prescaler)

0x05

clk_T2S/128 (from prescaler)

0x06

clk_T2S/256 (from prescaler)

0x07

clk_T2S/1024 (from prescaler)

21.11.5 TCNT2 – Timer/Counter2
Bit

7

6

5

4

RW
0

RW
0

RW
0

RW
0

NA ($B2)
Read/Write
Initial Value

3

2

1

0

RW
0

RW
0

RW
0

TCNT27:20
RW
0

TCNT2

The Timer/Counter Register gives direct access, both for read and write operations, tothe 8-bit counter unit of the Timer/Counter2. Writing to the TCNT2 Register blocks(removes) the Compare Match on the following timer clock. Modifying the counter(TCNT2) while the counter is running, introduces a risk of missing a Compare Match
between TCNT2 and the OCR2x Registers.
• Bit 7:0 – TCNT27:20 - Timer/Counter2 Byte

21.11.6 OCR2A – Timer/Counter2 Output Compare Register A
Bit

7

6

5

NA ($B3)
Read/Write
Initial Value

4

3

2

1

0

OCR2A7:0
RW
0

RW
0

RW
0

RW
0

RW
0

OCR2A
RW
0

RW
0

RW
0

The Output Compare Register A contains an 8-bit value that is continuously comparedwith the counter value (TCNT2). A match can be used to generate an Output Compareinterrupt, or to generate a waveform output on the OC2A pin.
• Bit 7:0 – OCR2A7:0 - Output Compare Register21.11.7 OCR2B – Timer/Counter2 Output Compare Register B
Bit

7

6

5

4

RW
0

RW
0

RW
0

RW
0

NA ($B4)
Read/Write
Initial Value

3

2

1

0

RW
0

RW
0

RW
0

OCR2B7:0
RW
0

OCR2B

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The Output Compare Register B contains an 8-bit value that is continuously comparedwith the counter value (TCNT2). A match can be used to generate an Output Compareinterrupt, or to generate a waveform output on the OC2B pin.
• Bit 7:0 – OCR2B7:0 - Output Compare Register21.11.8 ASSR – Asynchronous Status Register
Bit
NA ($B6)

7

6

5

4

3

2

1

0

EXCLKAMR EXCLK AS2 TCN2UB OCR2AUB OCR2BUB TCR2AUB TCR2BUB ASSR

Read/Write
Initial

RW
0

RW
0

RW
0

R
0

R
0

R
0

R
0

R
0

The register ASSR controls the asynchronous clocks for Timer/Counter2 and enables
the asynchronous 32kHz clock for the symbol counter. Three bits
(AS2,EXCLK,EXCLKAMR) are used to control the clocks. Note, to prevent clock spikes
on asynchronous clock wires, every access to ASSR should change only one of thethree bits.
• Bit 7 – EXCLKAMR - Enable External Clock Input for AMR
The bit EXCLKAMR extends the available clock sources for Timer/Counter2. If this bit is
written to one, and asynchronous clock is selected (bit AS2 set), AMR functionality isenabled and Timer/Counter2 is clocked by pin AMR.
• Bit 6 – EXCLK - Enable External Clock Input
When EXCLK is written to one, and asynchronous clock is selected, the external clock
input buffer is enabled and an external clock can be input on Timer Oscillator 1(TOSC1) pin instead of a 32 kHz crystal. Writing to EXCLK should be done before
asynchronous operation is selected. Note that the crystal Oscillator will only run when
this bit is zero.
• Bit 5 – AS2 - Timer/Counter2 Asynchronous Mode
When AS2 is written to zero, Timer/Counter2 is clocked from the I/O clock, clkI/O.
When AS2 is written to one, Timer/Counter2 is clocked from a crystal Oscillator
connected to the Timer Oscillator 1 (TOSC1) pin. When the value of AS2 is changed,
the contents of TCNT2, OCR2A, OCR2B, TCCR2A and TCCR2B might be corrupted.
• Bit 4 – TCN2UB - Timer/Counter2 Update Busy
When Timer/Counter2 operates asynchronously and TCNT2 is written, this bit becomes
set. When TCNT2 has been updated from the temporary storage register, this bit iscleared by hardware. A logical zero in this bit indicates that TCNT2 is ready to be
updated with a new value.
• Bit 3 – OCR2AUB - Timer/Counter2 Output Compare Register A Update Busy
When Timer/Counter2 operates asynchronously and OCR2A is written, this bit
becomes set. When OCR2A has been updated from the temporary storage register,
this bit is cleared by hardware. A logical zero in this bit indicates that OCR2A is ready to
be updated with a new value.
• Bit 2 – OCR2BUB - Timer/Counter2 Output Compare Register B Update Busy
When Timer/Counter2 operates asynchronously and OCR2B is written, this bit
becomes set. When OCR2B has been updated from the temporary storage register,328

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ATmega128RFA1
this bit is cleared by hardware. A logical zero in this bit indicates that OCR2B is ready to
be updated with a new value.
• Bit 1 – TCR2AUB - Timer/Counter2 Control Register A Update Busy
When Timer/Counter2 operates asynchronously and TCCR2A is written, this bit
becomes set. When TCCR2A has been updated from the temporary storage register,
this bit is cleared by hardware. A logical zero in this bit indicates that TCCR2A is readyto be updated with a new value.
• Bit 0 – TCR2BUB - Timer/Counter2 Control Register B Update Busy
When Timer/Counter2 operates asynchronously and TCCR2B is written, this bit
becomes set. When TCCR2B has been updated from the temporary storage register,
this bit is cleared by hardware. A logical zero in this bit indicates that TCCR2B is readyto be updated with a new value.

21.11.9 GTCCR – General Timer Counter Control register
Bit

7

6

5

4

3

2

1

$23 ($43)

TSM

PSRASY

Read/Write
Initial Value

RW
0

RW
0

0

GTCCR

• Bit 7 – TSM - Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In thismode the value that is written to the PSRASY and PSRSYNC bits is kept, hence
keeping the corresponding prescaler reset signals asserted. This ensures that thecorresponding Timer/Counters are halted and can be configured to the same value
without the risk of one of them advancing during the configuration. When the TSM bit is
written to zero, the PSRASY and PSRSYNC bits are cleared by hardware and theTimer/Counters simultaneously start counting.
• Bit 1 – PSRASY - Prescaler Reset Timer/Counter2
When this bit is one, the Timer/Counter2 prescaler will be reset. This bit is normally
cleared immediately by hardware. If the bit is written when Timer/Counter2 is operatingin asynchronous mode, the bit will remain one until the prescaler has been reset. The
bit will not be cleared by hardware if the TSM bit is set.

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22 SPI- Serial Peripheral Interface
22.1 Features
The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer
between the ATmega128RFA1 and peripheral devices or between several AVR
devices.
The ATmega128RFA1 SPI includes the following features:• Full-duplex, Three-wire Synchronous Data Transfer• Master or Slave Operation• LSB First or MSB First Data Transfer• Seven Programmable Bit Rates• End of Transmission Interrupt Flag
• Write Collision Flag Protection• Wake-up from Idle Mode
• Double Speed (CK/2) Master SPI Mode
22.2 Functional Description
USART can also be used in Master SPI mode, see "USART in SPI Mode" on page 368.
The Power Reduction SPI bit, PRSPI, in "PRR0 – Power Reduction Register0" on page
167 must be written to zero to enable SPI module. The block diagram of the SPI
interface is shown in Figure 22-1 on page 331.
The interconnection between Master and Slave CPUs with SPI is shown in Figure 22-2
on page 331. The system consists of two shift Registers, and a Master clock generator.
__
The SPI Master initiates the communication cycle when pulling low the Slave Select SS
pin of the desired Slave. Master and Slave prepare the data to be sent in theirrespective shift Registers, and the Master generates the required clock pulses on the
SCK line to interchange data. Data is always shifted from Master to Slave on the Master
Out – Slave In, MOSI, line, and from Slave to Master on the Master In – Slave Out,MISO, line. After each__data packet, the Master will synchronize the Slave by pullinghigh the Slave Select, SS, line.
__
When configured as a Master, the SPI interface has no automatic control of the SS line.
This must be handled by user software before communication can start. When this isdone, writing a byte to the SPI Data Register starts the SPI clock generator, and the
hardware shifts the eight bits into the Slave. After shifting one byte, the SPI clock
generator stops, setting the end of Transmission Flag (SPIF). If the SPI Interrupt Enable
bit (SPIE) in the SPCR Register is set, an interrupt is requested. The Master may
continue to shift the next byte__
by writing it into SPDR, or signal the end of packet bypulling high the Slave Select, SS line. The last incoming byte will be kept in the Buffer
Register for later use.
When configured__as a Slave, the SPI interface will remain sleeping with MISO tri-statedas long as the SS pin is driven high. In this state, software may update the contents of
the SPI Data Register, SPDR, but the data will not be shifted out by incoming clock
pulses on the SCK pin until the SS pin is driven low. As one byte has been completely
shifted, the end of Transmission Flag, SPIF is set. If the SPI Interrupt Enable bit, SPIE,
in the SPCR Register is set, an interrupt is requested. The Slave may continue to place
new data to be sent into SPDR before reading the incoming data. The last incoming
byte will be kept in the Buffer Register for later use.

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Figure 22-1. SPI Block Diagram

(1)

SPI2X

SPI2X

DIVIDER
/2/4/8/16/32/64/128

Note:

1. Refer to Figure 1-1 on page 2 and Table 14-3 on page 193 for SPI pin placement.

Figure 22-2. SPI Master-slave Interconnection

SHIFT
ENABLEThe system is single buffered in the transmit direction and double buffered in thereceive direction. This means that bytes to be transmitted cannot be written to the SPI
Data Register before the entire shift cycle is completed. When receiving data, however,a received character must be read from the SPI Data Register before the next characterhas been completely shifted in. Otherwise, the first byte is lost. In SPI Slave mode, the331
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control logic will sample the incoming signal of the SCK pin. To ensure correct samplingof the clock signal, the minimum low and high periods should be:
Low period:
High period:

longer than 2 CPU clock cycles
longer than 2 CPU clock cycles__
When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins isoverridden according to Table 21-1. For more details on automatic port overrides, refer
to "Alternate Port Functions" on page 191.
Table 22-1. Pin Overrides

(1)

Pin

Direction, Master SPI

Direction, Slave SPI

MOSIUser Defined

Input

MISO

Input

User Defined

SCK

User Defined

Input

SS

User Defined

Input

Note:

1.

See "Alternate Functions of Port B" on page 192 for a detailed description of how
to define the direction of the user defined SPI pins.

The following code examples show how to initialize the SPI as a Master and how to
perform a simple transmission. DDR_SPI in the examples must be replaced by theactual Data Direction Register controlling the SPI pins. DD_MOSI, DD_MISO and
DD_SCK must be replaced by the actual data direction bits for these pins. E.g. if MOSIis placed on pin PB5, replace DD_MOSI with DDB5 and DDR_SPI with DDRB.
Assembly Code Example(1)

SPI_MasterInit:; Set MOSI and SCK output, all others input
ldi r17,(1<<DD_MOSI)|(1<<DD_SCK)
out DDR_SPI,r17; Enable SPI, Master, set clock rate fck/16
ldi r17,(1<<SPE)|(1<<MSTR)|(1<<SPR0)
out SPCR,r17
ret
SPI_MasterTransmit:; Start transmission of data (r16)out SPDR,r16
Wait_Transmit:; Wait for transmission complete
sbis SPSR,SPIF
rjmp Wait_Transmit
ret

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ATmega128RFA1C Code Example(1)

void SPI_MasterInit(void){/* Set MOSI and SCK output, all others input */DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK);/* Enable SPI, Master, set clock rate fck/16 */SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0);}
void SPI_MasterTransmit(char cData){/* Start transmission */SPDR = cData;/* Wait for transmission complete */while(!(SPSR & (1<<SPIF)))
;
}
Note:

1.

See "About Code Examples" on page 7

Assembly Code Example(1)SPI_SlaveInit:; Set MISO output, all others input
ldi r17,(1<<DD_MISO)
out DDR_SPI,r17; Enable SPI
ldi r17,(1<<SPE)
out SPCR,r17
ret
SPI_SlaveReceive:; Wait for reception complete
sbis SPSR,SPIF
rjmp SPI_SlaveReceive; Read received data and returnin r16,SPDR
ret

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C Code Example(1)void SPI_SlaveInit(void){/* Set MISO output, all others input */DDR_SPI = (1<<DD_MISO);/* Enable SPI */SPCR = (1<<SPE);}char SPI_SlaveReceive(void){/* Wait for reception complete */while(!(SPSR & (1<<SPIF)));/* Return Data Register */return SPDR;
}
Note:

1.

See "About Code Examples" on page 7;__
22.3 SS Pin Functionality
22.3.1 Slave Mode__
When
the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When__
SS is held low, the SPI is activated, and MISO
becomes an output if configured so by__
the user. All other pins are inputs. When SS is driven high, all pins are inputs, and the
SPI is passive, which means
data. Note that the SPI__that it will not receive incoming__
logic will be reset once the SS pin is driven high. The SS pin is useful for packet/byte
synchronization to keep__ the slave bit counter synchronous with the master clock
generator. When the SS pin is driven high, the SPI slave will immediately reset the send
and receive logic, and drop any partially received data in the Shift Register.

22.3.2 Master Mode
When the SPI is configured as__ a Master__ (MSTR in SPCR is set), the user candetermine the direction of the SS pin. If SS is configured as an output, the pin is a
general output__ pin which does not affect__ the SPI system. Typically, the pin will be
driving the SS pin of the SPI Slave. If SS__is configured as an input, it must be held highto ensure Master SPI operation. If the SS pin__is driven low by peripheral circuitry when
the SPI is configured as a Master with the SS pin defined as an input, the SPI systeminterprets this as another master selecting the SPI as a slave and starting to send data
to it. To avoid bus contention, the SPI system takes the following actions:
1. The MSTR bit in SPCR is cleared and the SPI system becomes a Slave. As a resultof the SPI becoming a Slave, the MOSI and SCK pins become inputs.
2. The SPIF Flag in SPSR is set, and if the SPI interrupt is enabled, and the I-bit in
SREG is set, the interrupt routine will be executed.
Thus, when interrupt-driven
SPI transmission is used in Master mode, and there exists__
a possibility that SS is driven low, the interrupt should always check that the MSTR bit
is still set. If the MSTR bit has been cleared by a slave select, it must be set by the user
to re-enable SPI Master Mode.

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ATmega128RFA1
22.3.3 Data Mode
There are four combinations of SCK phase and polarity with respect to serial data,
which are determined by control bits CPHA and CPOL. The SPI data transfer formats
are shown in Figure 22-3 below and Figure 22-4 below. Data bits are shifted out andlatched in on opposite edges of the SCK signal, ensuring sufficient time for data signals
to stabilize. This is clearly seen in the summary of Table 22-2 below:
Table 22-2. CPOL Functionality
Leading Edge

Trailing Edge

SPI Mode

CPOL=0, CPHA=0

Sample (Rising)

Setup (Falling)

0

CPOL=0, CPHA=1

Setup (Rising)

Sample (Falling)

1

CPOL=1, CPHA=0

Sample (Falling)

Setup (Rising)

2

CPOL=1, CPHA=1

Setup (Falling)

Sample (Rising)3

Figure 22-3. SPI Transfer Format with CPHA = 0
SCK (CPOL = 0)
mode 0SCK (CPOL = 1)
mode 2
SAMPLE I
MOSI/MISOCHANGE 0
MOSI PIN
CHANGE 0
MISO PINSS

MSB first (DORD = 0) MSB
LSB first (DORD = 1) LSB

Bit 6
Bit 1

Bit 5
Bit 2

Bit 4
Bit 3

Bit 3
Bit 4

Bit 2
Bit 5

Bit 1
Bit 6

LSB
MSB

Figure 22-4. SPI Transfer Format with CPHA = 1
SCK (CPOL = 0)
mode 1
SCK (CPOL = 1)
mode 3
SAMPLE I
MOSI/MISOCHANGE 0
MOSI PIN
CHANGE 0
MISO PINSS

MSB first (DORD = 0)
LSB first (DORD = 1)

MSB
LSB

Bit 6
Bit 1

Bit 5
Bit 2

Bit 4
Bit 3

Bit 3
Bit 4

Bit 2
Bit 5

Bit 1
Bit 6

LSB
MSB

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22.4 Register Description

22.4.1 SPCR – SPI Control Register
Bit

7

6

5

4

3

2

1

0

$2C ($4C)

SPIE

SPE

DORD

MSTR

CPOL

CPHA

SPR1

SPR0

Read/Write
Initial Value

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

SPCR

• Bit 7 – SPIE - SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set
and the if the Global Interrupt Enable bit in SREG is set.s• Bit 6 – SPE - SPI Enable
When the SPE bit is set (one), the SPI is enabled. This bit must be set to enable any
SPI operations.
• Bit 5 – DORD - Data Order
When the DORD bit is written to one, the LSB of the data word is transmitted first.
When the DORD bit is written to zero, the MSB of the data word is transmitted first.
• Bit 4 – MSTR - Master/Slave SelectThis bit selects Master SPI mode when written to one, and Slave SPI mode when
written logic zero. If the Slave Select pin is configured as an input and is driven low
while MSTR is set, MSTR will be cleared and SPIF in SPSR are set. The user will thenhave to set MSTR to re-enable SPI Master mode.
• Bit 3 – CPOL - Clock polarity
When this bit is written to one, SCK is high when idle. When CPOL is written to zero,
SCK is low when idle. Refer to the "Data Modes" section for an example. The CPOL
functionality is summarized below.
Table 22-3 CPOL Register Bits
Register Bits
CPOL

Value

Description

0

Rising (Leading Edge), Falling (Trailing
Edge)

1

Falling (Leading Egde), Rising (TrailingEdge)• Bit 2 – CPHA - Clock Phase
The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading(first) or trailing (last) edge of SCK. Refer to the "Data Modes" section for an example.
The CPOL functionality is summarized below.
Table 22-4 CPHA Register Bits
Register Bits
CPHA

Value

Description0

Sample (Leading Edge), Setup (Trailing
Edge)

1

Setup (Leading Edge), Sample (TrailingEdge)• Bit 1:0 – SPR1:0 - SPI Clock Rate Select 1 and 0336

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ATmega128RFA1
These two bits control the SCK rate of the device configured as a Master. SPR1 and
SPR0 have no effect on the Slave. The relationship between SCK and the Oscillator
Clock frequency fosc is shown in the following table.
Table 22-5 SPR Register Bits
Register Bits

Value

Description

SPR1:00x00

fosc/40x01

fosc/16

0x02

fosc/64

0x03

fosc/128

0x04

fosc/20x05

fosc/80x06

fosc/32

0x07

fosc/64

22.4.2 SPSR – SPI Status Register
Bit

7

6

5

4

3

2

1

0

$2D ($4D)

SPIF

WCOL

Res4

Res3

Res2

Res1

Res0

SPI2X

Read/Write
Initial Value

R
0

R
0

R
0

R
0

R
0

R
0

R
0

RW
0

SPSR

• Bit 7 – SPIF - SPI Interrupt Flag
When a serial transfer is complete, the SPIF Flag is set. An interrupt is generated if
SPIE in SPCR is set and global interrupts are enabled. The SPIF Flag is also set if the
Slave Select pin is an input and is driven low when the SPI is in Master mode. SPIF iscleared by hardware when executing the corresponding interrupt handling vector.
Alternatively, the SPIF bit is cleared by first reading the SPI Status Register with SPIF
set and then accessing the SPI Data Register (SPDR).
• Bit 6 – WCOL - Write Collision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer.
The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status Registerwith WCOL set and then accessing the SPI Data Register.
• Bit 5:1 – Res4:0 - Reserved• Bit 0 – SPI2X - Double SPI Speed Bit
When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when
the SPI is in Master mode. This means that the minimum SCK period will be two CPU
clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to workat fosc/4 or lower. The SPI interface on the ATmega128RFA1 is also used for program
memory and EEPROM downloading or uploading. See section "Serial Downloading" forserial programming and verification.

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22.4.3 SPDR – SPI Data Register
Bit

7

6

5

$2E ($4E)
Read/Write
Initial Value

4

3

2

1

0

SPDR7:0
RW
X

RW
X

RW
X

RW
X

RW
X

SPDR
RW
X

R
0

R
0

The SPI Data Register is a read/write register used for data transfer between theRegister File and the SPI Shift Register. Writing to the register initiates datatransmission. Reading the register causes the Shift Register Receive buffer to be read.
• Bit 7:0 – SPDR7:0 - SPI Data Register

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23 USART
23.1 Features• Full duplex operation (independent serial receive and transmit registers)• Asynchronous or synchronous operation• Master or slave clocked synchronous operation• High resolution baud rate generator• Supports serial frames with 5, 6, 7, 8, or 9 data bits and 1 or 2 stop bits
• Odd or even parity generation and parity check supported by hardware• Data overrun detection• Framing error detection• Noise filtering includes false start bit detection and digital low pass filter• 3 separate interrupts on TX complete, TX data register empty and RX complete• Multi-processor communication mode
• Double speed, asynchronous communication mode

23.2 Overview
The Universal Synchronous and Asynchronous Serial Receiver and Transmitter(USART) is a highly flexible serial communication device.
The ATmega128RFA1 has two USART’s, USART0 and USART1. The functionality for
all two USART’s is described below. USART0 and USART1 have different I/O registers
as shown in "Register Summary" on page 496.
A simplified block diagram of the USART transmitter is shown in Figure 23-1 on page340 on page 340. CPU accessible I/O registers and I/O pins are shown in bold.
The Power Reduction USART0 bit, PRUSART0, in "PRR0 – Power Reduction
Register0" on page 167 must be disabled by writing a logical zero to it. The Power
Reduction USART1 bit, PRUSART1, in "PRR1 – Power Reduction Register 1" on page
168 must be disabled by writing a logical zero to it.
The dashed boxes in the block diagram Figure 23-1 on page 340 separate the threemain parts of the USART (listed from the top): clock generator, transmitter and receiver.
Control registers are shared by all units. The clock generation logic consists ofsynchronization logic for external clock input used by synchronous slave operation, andthe baud rate generator. The XCKn (transfer clock) pin is only used by synchronoustransfer mode. The transmitter consists of a single write buffer, a serial shift register,
Parity generator and control logic for handling different serial frame formats. The write
buffer allows a continuous transfer of data without any delay between frames. The
receiver is the most complex part of the USART module due to its clock and data
recovery units. The recovery units are used for asynchronous data reception. In
addition to the recovery units, the receiver includes a parity checker, control logic, ashift register and a two level receive buffer (UDRn). The receiver supports the same
frame formats as the transmitter, and can detect frame, data overrun and parity errors.

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Figure 23-1. USART Block Diagram(1)

Clock Generator

UBRR[H:L]
OSC

BAUD RATE GENERATORSYNC LOGICPINCONTROL

XCKTransmitter
TX

UDR (Transmit)

CONTROLDATA BUSPARITY
GENERATORPINTRANSMIT SHIFT REGISTERCONTROL

Receiver

RECEIVE SHIFT REGISTER

CLOCK

RX

RECOVERYCONTROLDATAPINRECOVERYCONTROL

UCSRA

RxD

PARITYUDR (Receive)

Note:

TxD

CHECKER

UCSRB

UCSRC

1. See "Figure 1-1" on page 2, Table 14-6 on page 195and Table 14-9 on page
197Table 14-9 on page 197for USART pin placement.

23.3 Clock Generation
The clock generation logic generates the base clock for the transmitter and receiver.
The USART supports four modes of clock operation: Normal asynchronous, double
speed asynchronous, master synchronous and slave synchronous mode. The UMSELn
bit in USART Control and Status Register C (UCSRnC) selects between asynchronousand synchronous operation. Double speed (asynchronous mode only) is controlled by
the U2Xn found in the UCSRnA register. When using synchronous mode (UMSELn =1), the data direction register for the XCKn pin (DDR_XCKn) controls whether the clock
source is internal (master mode) or external (slave mode). The XCKn pin is only active
when using synchronous mode.

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Figure 22-2 on page 331 shows a block diagram of the clock generation logic.
Figure 23-2. Clock Generation Logic, Block Diagram
UBRR

U2X

fosc
Prescaling
Down-Counter

UBRR+1

/2

/4

/2

0
1
0

OSC
DDR_XCK

XCK
Pin

xcki

Sync
RegisterEdge
Detector

0

1

UCPOL

txclk

UMSEL

1

xcko

DDR_XCK

1

0

rxclk

Signal description:
txclk
rxclk
xcki
xcko
fOSC

Transmitter clock (internal signal).
Receiver base clock (internal signal).
Input from XCK pin (internal signal). Used for synchronous slave operation.
Clock output to XCK pin (internal signal). Used for synchronous master
operation.
System clock frequency.

23.3.1 Internal Clock Generation – The Baud Rate Generator
Internal clock generation is used for the asynchronous and the synchronous mastermodes of operation. The description in this section refers to Figure 22-2 on page 331.
The USART Baud Rate Register (UBRRn) and the down-counter connected to it
function as a programmable prescaler or baud rate generator. The down-counter,running at system clock (fOSC), is loaded with the UBRRn value each time the counter
has counted down to zero or when the UBRRLn register is written. A clock is generated
each time the counter reaches zero. This clock is the baud rate generator clock output(= fOSC/(UBRRn+1)). The transmitter divides the baud rate generator clock output by 2,
8 or 16 depending on mode. The baud rate generator output is used directly by thereceiver’s clock and data recovery units. However, the recovery units use a statemachine that uses 2, 8 or 16 states depending on mode set by the state of the
UMSELn, U2Xn and DDR_XCKn bits.
Table 23-1 below contains equations for calculating the baud rate (in bits per second)and for calculating the UBRRn value for each mode of operation using an internallygenerated clock source.
Table 23-1. Equations for Calculating Baud Rate Register Setting
Operating Mode

Equation for Calculating(1)
Baud Rate

Equation for Calculating
UBRR Value

Asynchronous Normal Mode
(U2Xn = 0)

BAUD =f OSC
16(UBRRn + 1)

UBRRn =f OSC
−1
16 BAUD

Asynchronous Double Speed
Mode (U2Xn = 1)

BAUD =f OSC
8(UBRRn + 1)

UBRRn =f OSC
−1
8 BAUD

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Operating Mode
Synchronous Master Mode

Note:

Equation for Calculating(1)
Baud Rate

BAUD =f OSC
2(UBRRn + 1)

Equation for Calculating
UBRR ValueUBRRn =f OSC
−1
2 BAUD

1. The baud rate is defined to be the transfer rate in bit per second (bps).

BAUD
fOSC
UBRRn

Baud rate (in bits per second, bps)
System oscillator clock frequency
Contents of the UBRRHn and UBRRLn registers, (0-4095)

Some examples of UBRRn values for some system clock frequencies are found in
Table 23-14 on page 365.
23.3.2 Double Speed Operation (U2Xn)
The transfer rate can be doubled by setting the U2Xn bit in UCSRnA. Setting this bit
only has effect for the asynchronous operation. Set this bit to zero when usingsynchronous operation.
Setting this bit will reduce the divisor of the baud rate divider from 16 to 8, effectively
doubling the transfer rate for asynchronous communication. Note however that thereceiver will in this case only use half the number of samples (reduced from 16 to 8) fordata sampling and clock recovery, and therefore a more accurate baud rate setting andsystem clock are required when this mode is used. For the transmitter, there are nodownsides.
23.3.3 External Clock
External clocking is used by the synchronous slave modes of operation. The description
in this section refers to Figure 22-2 on page 331 for details.
External clock input from the XCKn pin is sampled by a synchronization register tominimize the chance of meta-stability. The output from the synchronization registermust then pass through an edge detector before it can be used by the transmitter andreceiver. This process introduces a two CPU clock period delay and therefore themaximum external XCKn clock frequency is limited by the following equation:f XCK <f OSC
4Note that fOSC depends on the stability of the system clock source. It is therefore
recommended to add some margin to avoid possible loss of data due to frequency
variations.
23.3.4 Synchronous Clock Operation
When synchronous mode is used (UMSELn = 1), the XCKn pin will be used as either
clock input (slave) or clock output (master). The dependency between the clock edges
and data sampling or data change is the same. The basic principle is that data input (onRxDn) is sampled at the opposite XCKn clock edge of the edge the data output (TxDn)
is changed.

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Figure 23-3. Synchronous Mode XCKn Timing
UCPOL = 1

XCK

RxD / TxD

SampleXCKUCPOL = 0

RxD / TxD

SampleThe UCPOLn bit UCRSC selects which XCKn clock edge is used for data sampling andwhich is used for data change. As Figure 22-3 on page 335 shows, when UCPOLn iszero the data will be changed at rising XCKn edge and sampled at falling XCKn edge. If
UCPOLn is set, the data will be changed at falling XCKn edge and sampled at rising
XCKn edge.

23.4 Frame Formats
A serial frame is defined to be one character of data bits with synchronization bits (startand stop bits), and optionally a parity bit for error checking. The USART accepts all 30
combinations of the following as valid frame formats:• 1 start bit• 5, 6, 7, 8, or 9 data bits
• no, even or odd parity bit• 1 or 2 stop bits
A frame starts with the start bit followed by the least significant data bit. Then the next
data bits, up to a total of nine, are succeeding, ending with the most significant bit. If
enabled, the parity bit is inserted after the data bits, before the stop bits. When acomplete frame is transmitted, it can be directly followed by a new frame, or thecommunication line can be set to an idle (high) state. Figure 23-4 below illustrates thepossible combinations of the frame formats. Bits inside brackets are optional.
Figure 23-4. Frame Formats
FRAME(IDLE)

St
(n)
P
Sp
IDLE

St

0

1

2

3

4

[5]

[6]

[7]

[8]

[P]

Sp1

[Sp2]

(St / IDLE)

Start bit, always low
Data bits (0 to 8)
Parity bit - can be odd or even
Stop bit, always highNo transfers on the communication line (RxDn or TxDn). An IDLE line must be
high

The frame format used by the USART is set by the UCSZn2:0, UPMn1:0 and USBSn
bits in UCSRnB and UCSRnC. The receiver and transmitter use the same setting. Notethat changing the setting of any of these bits will corrupt all ongoing communication forboth the receiver and transmitter.

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The USART Character Size (UCSZn2:0) bits select the number of data bits in theframe. The USART Parity Mode (UPMn1:0) bits enable and set the type of parity bit.
The selection between one or two stop bits is done by the USART Stop Bit Select(USBSn) bit. The receiver ignores the second stop bit. A frame error will therefore only
be detected in cases where the first stop bit is zero.
23.4.1 Parity Bit Calculation
The parity bit is calculated by doing an exclusive-or of all the data bits. If odd parity isused, the result of the exclusive or is inverted. The parity bit is located between the last
data bit and first stop bit of a serial frame. The relation between the parity bit and databits is as follows:

Peven = d n −1 ⊕ K ⊕ d 3 ⊕ d 2 ⊕ d1 ⊕ d 0 ⊕ 0
Podd = d n−1 ⊕ K ⊕ d 3 ⊕ d 2 ⊕ d1 ⊕ d 0 ⊕ 1
Peven
Podd
dn

Parity bit using even parity
Parity bit using odd parity
Data bit n of the character

23.5 USART Initialization
The USART has to be initialized before any communication can take place. The
initialization process normally consists of setting the baud rate, setting frame format andenabling the transmitter or the receiver depending on the usage. For interrupt driven
USART operation, the global interrupt flag should be cleared (and interrupts globally
disabled) when doing the initialization.
Before doing a re-initialization with changed baud rate or frame format, be sure that
there are no ongoing transmissions during the period the registers are changed. The
TXCn flag can be used to check that the transmitter has completed all transfers, andthe RXC flag can be used to check that there are no unread data in the receive buffer.
Note that the TXCn flag must be cleared before each transmission (before UDRn iswritten) if it is used for this purpose.
The following simple USART initialization code examples show one assembly and one
C function that are equal in functionality. The examples assume asynchronous
operation using polling (no interrupts enabled) and a fixed frame format. The baud rate
is given as a function parameter. For the assembly code, the baud rate parameter isassumed to be stored in the r17:r16 Registers.
Assembly Code Example
USART_Init:(1); Set baud rateout UBRRnH, r17
out UBRRnL, r16; Enable receiver and transmitter
ldi r16, (1<<RXENn)|(1<<TXENn)
out UCSRnB,r16; Set frame format: 8data, 2stop bit
ldi r16, (1<<USBSn)|(3<<UCSZn0)
out UCSRnC,r16
ret

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C Code Example#define FOSC 8000000// Clock Speed#define BAUD 9600
#define (MYUBRR FOSC/16/BAUD-1)
void main( void ){...
USART_Init ( MYUBRR );...} // main
void USART_Init( unsigned int ubrr){/* Set baud rate */UBRRnH = (unsigned char)(ubrr>>8);
UBRRnL = (unsigned char) ubrr;/* Enable receiver and transmitter */UCSRnB = (1<<RXEN)|(1<<TXEN);/* Set frame format: 8data, 2stop bit */UCSRnC = (1<<USBS)|(3<<UCSZ0);} // USART_Init
Note:

1. See "About Code Examples" on page 7

More advanced initialization routines can be made that include frame format asparameters, disable interrupts and so on. However, many applications use a fixed
setting of the baud and control registers, and for these types of applications theinitialization code can be placed directly in the main routine, or be combined withinitialization code for other I/O modules.

23.6 Data Transmission – The USART Transmitter
The USART transmitter is enabled by setting the Transmit Enable (TXEN) bit in the
UCSRnB register. When the transmitter is enabled, the normal port operation of the
TxDn pin is overridden by the USART and gives the function as the transmitter’s serial
output. The baud rate, mode of operation and frame format must be set up once before
doing any transmissions. If synchronous operation is used, the clock on the XCKn pin
will be overridden and used as transmission clock.
23.6.1 Sending Frames with 5 to 8 Data Bit
A data transmission is initiated by loading the transmit buffer with the data to betransmitted. The CPU can load the transmit buffer by writing to the UDRn I/O location.
The buffered data in the transmit buffer will be moved to the shift register when the shift
register is ready to send a new frame. The shift register is loaded with new data if it is in
idle state (no ongoing transmission) or immediately after the last stop bit of the previous
frame is transmitted. When the shift register is loaded with new data, it will transfer one
complete frame at the rate given by the baud rate register, U2Xn bit or by XCKn
depending on mode of operation.
The following code examples show a simple USART transmit function based on pollingof the Data Register Empty Flag (UDREn). When using frames with less than eight bits,
the most significant bits written to the UDRn are ignored. The USART has to be
initialized before the function can be used. For the assembly code, the data to be sent
is assumed to be stored in register r16.

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Assembly Code Example
USART_Transmit:(1); Wait for empty transmit buffer
sbis UCSRnA,UDREn rjmp USART_Transmit; Put data (r16) into buffer, sends the dataout UDRn,r16
ret(1)

C Code Example
void USART_Transmit( unsigned char data ){/* Wait for empty transmit buffer */while ( !( UCSRnA & (1<<UDREn)) );/* Put data into buffer, sends the data */UDRn = data;}
Note:

1. See "About Code Examples" on page 7

The function simply waits for the transmit buffer to be empty by checking the UDREnflag, before loading it with new data to be transmitted. If the data register empty
interrupt is utilized, the interrupt routine writes the data into the buffer.
23.6.2 Sending Frames with 9 Data Bit
If 9 bit characters are used (UCSZn2:0 = 7), the ninth bit must be written to the TXB8 bit
in UCSRnB before the low byte of the character is written to UDRn. The following code
examples show a transmit function that handles 9 bit characters. For the assembly
code, the data to be sent is assumed to be stored in registers r17:r16.
Assembly Code Example
USART_Transmit:(1)(2); Wait for empty transmit buffer
sbis UCSRnA,UDREn
rjmp USART_Transmit; Copy 9th bit from r17 to TXB8
cbi UCSRnB,TXB8
sbrc r17,0
sbi UCSRnB,TXB8; Put LSB data (r16) into buffer, sends the dataout UDRn,r16
ret

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ATmega128RFA1(1)(2)C Code Example
void USART_Transmit( unsigned int data ){/* Wait for empty transmit buffer */while ( !( UCSRnA & (1<<UDREn))) );/* Copy 9th bit to TXB8 */UCSRnB &= ~(1<<TXB8);
if ( data & 0x0100 )UCSRnB |= (1<<TXB8);/* Put data into buffer, sends the data */UDRn = data;}
Note:

1. These transmit functions are written to be general functions. They can be
optimized if the content of the UCSRnB is static. For example, only the TXB8 bitof the UCSRnB register is used after initialization.
2. See "About Code Examples" on page 7th

The 9 bit can be used for indicating an address frame when using multi processor
communication mode or for other protocol handling as for example synchronization.
23.6.3 Transmitter Flags and Interrupts
The USART transmitter has two flags that indicate its state: USART Data Register
Empty (UDREn) and Transmit Complete (TXCn). Both flags can be used for generatinginterrupts.
The Data Register Empty Flag (UDREn) indicates whether the transmit buffer is readyto receive new data. This bit is set when the transmit buffer is empty, and cleared when
the transmit buffer contains data to be transmitted that has not yet been moved into theshift register. For compatibility with future devices, always write this bit to zero whenwriting the UCSRnA register.
When the USART Data Register Empty Interrupt Enable (UDRIEn) bit in UCSRnB is
written to one, the USART data register empty interrupt will be executed as long as
UDREn is set (provided that global interrupts are enabled). UDREn is cleared by writing
UDRn. When interrupt-driven data transmission is used, the data register empty
interrupt routine must either write new data to UDRn in order to clear UDREn or disable
the data register empty interrupt, otherwise a new interrupt will occur once the interrupt
routine terminates.
The Transmit Complete Flag (TXCn) bit is set one when the entire frame in the transmit
shift register has been shifted out and there are no new data currently present in thetransmit buffer. The TXCn flag bit is automatically cleared when a transmission
complete interrupt is executed, or it can be cleared by writing a one to its bit location.
The TXCn flag is useful in half-duplex communication interfaces (like the RS-485
standard), where a transmitting application must enter receive mode and free thecommunication bus immediately after completing the transmission.
When the Transmission Complete Interrupt Enable (TXCIEn) bit in UCSRnB is set, the
USART transmission complete interrupt will be executed when the TXCn flag becomesset (provided that global interrupts are enabled). When the transmission complete
interrupt is used, the interrupt handling routine does not have to clear the TXCn flag.
This is done automatically when the interrupt is executed.

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23.6.4 Parity Generator
The parity generator calculates the parity bit for the serial frame data. When parity bit isenabled (UPMn1 = 1), the transmitter control logic inserts the parity bit between the last
data bit and the first stop bit of the frame that is sent.
23.6.5 Disabling the Transmitter
The disabling of the transmitter (setting the TXEN to zero) will not become effective until
ongoing and pending transmissions are completed, i.e., when the transmit shift registerand transmit buffer register do not contain data to be transmitted. The transmitter will nolonger override the TxDn pin when disabled.

23.7 Data Reception – The USART Receiver
The USART receiver is enabled by writing the Receive Enable (RXENn) bit in the
UCSRnB register to one. When the receiver is enabled, the normal pin operation of the
RxDn pin is overridden by the USART and given the function as the receiver’s serial
input. The baud rate, mode of operation and frame format must be set up once before
any serial reception can be done. If synchronous operation is used, the clock on the
XCKn pin will be used as transfer clock.
23.7.1 Receiving Frames with 5 to 8 Data Bits
The receiver starts data reception when it detects a valid start bit. Each bit that follows
the start bit will be sampled at the baud rate or XCKn clock, and shifted into the receive
shift register until the first stop bit of a frame is received. A second stop bit will beignored by the receiver. When the first stop bit is received, i.e., a complete serial frame
is present in the receive shift register, the contents of the shift register will be moved
into the receive buffer. The receive buffer can then be read by reading the UDRn I/Olocation.
The following code example shows a simple USART receive function based on pollingof the Receive Complete Flag (RXCn). When using frames with less than eight bits themost significant bits of the data read from the UDRn will be masked to zero. The
USART has to be initialized before the function can be used. The function simply waits
for data to be present in the receive buffer by checking the RXCn flag before reading
the buffer and returning the value.
Assembly Code Example(1)

USART_Receive:; Wait for data to be received
sbis UCSRnA, RXCn
rjmp USART_Receive; Get and return received data from bufferin r16, UDRn
ret

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C Code Example
unsigned char USART_Receive( void ){/* Wait for data to be received */while ( !(UCSRnA & (1<<RXCn)) );/* Get and return received data from buffer */return UDRn;
}

Note:

1. See "About Code Examples" on page 7

23.7.2 Receiving Frames with 9 Data Bitsth

If 9 bit characters are used (UCSZn2:0=7) the 9 bit must be read from the RXB8n bit in
UCSRnB before reading the low bits from the UDRn register. This rule applies to theFEn, DORn and UPEn status flags as well. Read status from UCSRnA, then data from
UDRn. Reading the UDRn I/O location will change the state of the receive buffer FIFO
and consequently the TXB8n, FEn, DORn and UPEn bits, which all are stored in the
FIFO, will change.
The following code example shows a simple USART receive function that handles bothnine bit characters and the status bits.
Assembly Code Example(1)

USART_Receive:; Wait for data to be received
sbis UCSRnA, RXCn
rjmp USART_Receive; Get status and 9th bit, then data from bufferin r18, UCSRnA
in r17, UCSRnB
in r16, UDRn
; If error, return -1
andi r18,(1<<FEn)|(1<<DORn)|(1<<UPEn)
breq USART_ReceiveNoError
ldi r17, HIGH(-1)
ldi r16, LOW(-1)
USART_ReceiveNoError:; Filter the 9th bit, then returnlsr r17andi r17, 0x01
ret

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(1)C Code Example
unsigned int USART_Receive( void ){unsigned char status, resh, resl;/* Wait for data to be received */while ( !(UCSRnA & (1<<RXCn)) );/* Get status and 9th bit, then data *//* from buffer */status = UCSRnA;
resh = UCSRnB;
resl = UDRn;/* If error, return -1 */if ( status & (1<<FEn)|(1<<DORn)|(1<<UPEn) )return -1;/* Filter the 9th bit, then return */resh = (resh >> 1) & 0x01;
return ((resh << 8) | resl);}
Note:

1. See "About Code Examples" on page 7

The receive function example reads all the I/O registers into the register file before any
computation is done. This gives an optimal receive buffer utilization since the buffer
location read will be free to accept new data as early as possible.
23.7.3 Receive Complete Flag and Interrupt
The USART receiver has one flag that indicates the receiver state.
The Receive Complete Flag (RXCn) indicates if there are unread data present in thereceive buffer. This flag is one when unread data exist in the receive buffer, and zero
when the receive buffer is empty (i.e., does not contain any unread data). If the receiver
is disabled (RXENn = 0), the receive buffer will be flushed and consequently the RXCnbit will become zero.
When the Receive Complete Interrupt Enable (RXCIEn) in UCSRnB is set, the USART
receive complete interrupt will be executed as long as the RXCn flag is set (provided
that global interrupts are enabled). When interrupt-driven data reception is used, thereceive complete routine must read the received data from UDRn in order to clear the
RXCn flag, otherwise a new interrupt will occur once the interrupt routine terminates.
23.7.4 Receiver Error Flags
The USART receiver has three error flags: Frame Error (FEn), Data OverRun (DORn)
and Parity Error (UPEn). All can be accessed by reading UCSRnA. Common for theerror flags is that they are located in the receive buffer together with the frame for which
they indicate the error status. Due to the buffering of the error flags, the UCSRnA must
be read before the receive buffer (UDRn), since reading the UDRn I/O location changes
the buffer read location. The error flags cannot be altered by the application software
doing a write to the flag location. However, all flags must be set to zero when the
UCSRnA is written for upward compatibility of future USART implementations. None of
the error flags can generate interrupts.
The Frame Error Flag (FEn) indicates the state of the first stop bit of the next readable
frame stored in the receive buffer. The FEn flag is zero when the stop bit was correctly
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read (as one), and the FEn flag will be one when the stop bit was incorrect (zero). This
flag can be used for detecting out-of-sync conditions, detecting break conditions andprotocol handling. The FEn flag is not affected by the setting of the USBSn bit in
UCSRnC since the receiver ignores all, except for the first, stop bits. For compatibility
with future devices, always set this bit to zero when writing to UCSRnA.
The Data OverRun Flag (DORn) indicates data loss due to a receiver buffer fullcondition. A data overrun occurs when the receive buffer is full (two characters), it is a
new character waiting in the receive shift register, and a new start bit is detected. If the
DORn flag is set there was one or more serial frame lost between the frame last readfrom UDRn, and the next frame read from UDRn. For compatibility with future devices,
always write this bit to zero when writing to UCSRnA. The DORn flag is cleared when
the frame received was successfully moved from the shift register to the receive buffer.
The Parity Error Flag (UPEn) indicates that the next frame in the receive buffer had aparity error when received. If parity check is not enabled the UPEn bit will always beread zero. For compatibility with future devices, always set this bit to zero when writing
to UCSRnA. For more details see "Parity Bit Calculation" on page 344 and "Parity
Checker" below.
23.7.5 Parity Checker
The parity checker is active when the high USART parity mode (UPMn1) bit is set. Typeof parity check to be performed (odd or even) is selected by the UPMn0 bit. Whenenabled, the parity checker calculates the parity of the data bits in incoming frames andcompares the result with the parity bit from the serial frame. The result of the check isstored in the receive buffer together with the received data and stop bits. The Parity
Error Flag (UPEn) can then be read by software to check if the frame had a parity error.
The UPEn bit is set if the next character that can be read from the receive buffer had aparity error when received .The parity checking was enabled at that point (UPMn1 = 1).
This bit is valid until the receive buffer (UDRn) is read.
23.7.6 Disabling the Receiver
In contrast to the transmitter, disabling of the receiver will be immediate. Data fromongoing receptions will therefore be lost. When disabled (i.e., the RXENn is set to zero)
the receiver will no longer override the normal function of the RxDn port pin. The
receiver buffer FIFO will be flushed when the receiver is disabled. Remaining data inthe buffer will be lost
23.7.7 Flushing the Receive Buffer
The receiver buffer FIFO will be flushed when the receiver is disabled, i.e., the buffer
will be emptied of its contents. Unread data will be lost. If the buffer has to be flushedduring normal operation, due to for instance an error condition, read the UDRn I/Olocation until the RXCn flag is cleared. The following code example shows how to flush
the receive buffer.
Assembly Code Example
USART_Flush:(1)

sbis UCSRnA, RXCn
ret
in r16, UDRn
rjmp USART_Flush

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(1)C Code Example
void USART_Flush( void ){unsigned char dummy;
while ( UCSRnA & (1<<RXCn) ) dummy = UDRn;}
Note:

1. See "About Code Examples" on page 7

23.8 Asynchronous Data Reception
The USART includes a clock recovery and a data recovery unit for handlingasynchronous data reception. The clock recovery logic is used for synchronizing theinternally generated baud rate clock to the incoming asynchronous serial frames at the
RxDn pin. The data recovery logic samples and low pass filters each incoming bit,thereby improving the noise immunity of the receiver. The asynchronous reception
operational range depends on the accuracy of the internal baud rate clock, the rate of
the incoming frames, and the frame size in number of bits.
23.8.1 Asynchronous Clock Recovery
The clock recovery logic synchronizes internal clock to the incoming serial frames.
Figure 23-5 below illustrates the sampling process of the start bit of an incoming frame.
The sample rate is 16 times the baud rate for Normal mode, and eight times the baudrate for double speed mode. The horizontal arrows illustrate the synchronization
variation due to the sampling process. Note the larger time variation when using the
double speed mode (U2Xn = 1) of operation. Samples denoted zero are samples done
when the RxDn line is idle (i.e., no communication activity).
Figure 23-5. Start Bit Sampling
RxD

IDLE

START

BIT 0

Sample(U2X = 0)

0

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

1

2

3

Sample(U2X = 1)

0

1

2

3

4

5

6

7

8

1

2

When the clock recovery logic detects a high (idle) to low (start) transition on the RxDn
line, the start bit detection sequence is initiated. Let sample 1 denote the first zerosample as shown in the figure. The clock recovery logic then uses samples 8, 9 and 10
for Normal mode, and samples 4, 5 and 6 for double speed mode (indicated withsample numbers inside boxes on the figure), to decide if a valid start bit is received. If
two or more of these three samples have logical high levels (the majority wins), the start
bit is rejected as a noise spike and the receiver starts looking for the next high to lowtransition. If however, a valid start bit is detected, the clock recovery logic is
synchronized and the data recovery can begin. The synchronization process isrepeated for each start bit.
23.8.2 Asynchronous Data Recovery
When the receiver clock is synchronized to the start bit, the data recovery can begin.
The data recovery unit uses a state machine that has 16 states for each bit in Normal
mode and eight states for each bit in double speed mode. Figure 23-6 on page 353

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shows the sampling of the data bits and the parity bit. Each of the samples is given a
number that is equal to the state of the recovery unit.
Figure 23-6. Sampling of Data and Parity Bit
BIT n

RxD

Sample(U2X = 0)

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

1

Sample(U2X = 1)

1

2

3

4

5

6

7

8

1

The decision of the logic level of the received bit is taken by doing a majority voting of
the logic value to the three samples in the centre of the received bit. The centre
samples are emphasized on the figure by having the sample number inside boxes. The
majority voting process is done as follows:
If two or all three samples have high levels, the received bit is registered to be logic 1. If
two or all three samples have low levels, the received bit is registered to be logic 0. This
majority voting process acts as a low pass filter for the incoming signal on the RxDn pin.
The recovery process is then repeated until a complete frame is received including thefirst stop bit. Note that the receiver only uses the first stop bit of a frame.
Figure 23-7 below shows the sampling of the stop bit and the earliest possible
beginning of the start bit of the next frame.
Figure 23-7. Stop Bit Sampling and Next Start Bit Sampling
STOP 1

RxD

(A)

(B)

(C)

Sample(U2X = 0)

1

2

3

4

5

6

7

8

9

10

0/1

0/1

0/1

Sample(U2X = 1)

1

2

3

4

5

6

0/1

The same majority voting is done to the stop bit as done for the other bits in the frame.
If the stop bit is registered to have a logic 0 value, the Frame Error Flag (FEn) will be
set.
A new high to low transition indicating the start bit of a new frame can come right after
the last of the bits used for majority voting. For normal speed mode, the first low level
sample can be at point marked (A) in Figure 23-7 above. For double speed mode thefirst low level must be delayed to (B). (C) marks a stop bit of full length. The early start
bit detection influences the operational range of the receiver.
23.8.3 Asynchronous Operational Range
The operational range of the receiver is dependent on the mismatch between thereceived bit rate and the internally generated baud rate. If the transmitter is sending
frames at too fast or too slow bit rates, or the internally generated baud rate of thereceiver does not have a similar (see Table 23-2 on page 354) base frequency, thereceiver will not be able to synchronize the frames to the start bit.

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The following equations can be used to calculate the ratio of the incoming data rate andinternal receiver baud rate.

Rslow =

( D + 1)SS −1 + D ⋅ S + SF

R fast =( D + 2)S( D + 1)S + S MF

Sum of character size and parity size (D = 5 to 10 bit)
Samples per bit. S = 16 for normal speed mode and S = 8 for double speedmode.
SFFirst sample number used for majority voting. SF = 8 for normal speed andSF = 4 for double speed mode.
SM
Middle sample number used for majority voting. SM = 9 for normal speed andSM = 5 for double speed mode.
Rslow is the ratio of the slowest incoming data rate that can be accepted in relation to
the receiver baud rate.
Rfast
is the ratio of the fastest incoming data rate that can be accepted in relation to
the receiver baud rate.
Table 23-2 below and Table 23-3 below list the maximum receiver baud rate error thatcan be tolerated. Note that normal speed mode has higher tolerance of baud ratevariations.
D
S

Table 23-2. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode
(U2Xn = 0)D
# (Data+Parity Bit)

Rslow (%)

Rfast (%)

Max Total Error (%)

Recommended Max
Receiver Error (%)

5

93.20

106.67+6.67/-6.8

± 3.0

6

94.12

105.79+5.79/-5.88

± 2.5

7

94.81

105.11+5.11/-5.19

± 2.0

8

95.36

104.58+4.58/-4.54

± 2.0

9

95.81

104.14+4.14/-4.19

± 1.5

10

96.17

103.78+3.78/-3.83± 1.5

Table 23-3. Recommended Maximum Receiver Baud Rate Error for Double Speed
Mode (U2Xn = 1)
D
# (Data+Parity Bit)

Rslow (%)

Rfast (%)

Max Total Error (%)

Recommended Max
Receiver Error (%)

5

94.12

105.66+5.66/-5.88

± 2.5

6

94.92

104.92+4.92/-5.08

± 2.0

7

95.52

104,35+4.35/-4.48

± 1.5

8

96.00

103.90+3.90/-4.00

± 1.5

9

96.39

103.53+3.53/-3.61

± 1.5

10

96.70

103.23+3.23/-3.30± 1.0

The recommendations of the maximum receiver baud rate error were made under theassumption that the receiver and transmitter equally divides the maximum total error.
There are two possible sources for the receiver baud rate error. The receiver’s system
clock will always have some minor instability over the supply voltage range and thetemperature range. When using the radio transceiver crystal oscillator (XOSC) togenerate the system clock, this is rarely a problem, but for the internal RC oscillator thesystem clock may differ more than 2% over the temperature range. The second source
for the error is more controllable. The baud rate generator can not always do an exact
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ATmega128RFA1
division of the system frequency to get the baud rate wanted. In this case an UBRR
value that gives an acceptable low error can be used if possible.

23.9 Multi-processor Communication Mode
Setting the Multi-processor Communication Mode (MPCMn) bit in UCSRnA enables afiltering function of incoming frames received by the USART receiver. Frames that do
not contain address information will be ignored and not put into the receive buffer. Thiseffectively reduces the number of incoming frames that has to be handled by the MCU,
in a system with multiple MCUs that communicate via the same serial bus. The
transmitter is unaffected by the MPCMn setting, but has to be used differently when it isa part of a system utilizing the multi-processor communication mode.
If the receiver is set up to receive frames that contain 5 to 8 data bits, then the first stop
bit indicates if the frame contains data or address information. If the receiver is set up
for frames with nine data bits, then the ninth bit (RXB8n) is used for identifying addressand data frames. When the frame type bit (the first stop or the ninth bit) is one, theframe contains an address. When the frame type bit is zero the frame is a data frame.
The multi-processor communication mode enables several slave MCUs to receive datafrom a master MCU. This is done by first decoding an address frame to find out which
MCU has been addressed. If a particular slave MCU has been addressed, it will receive
the following data frames as normal, while the other slave MCUs will ignore thereceived frames until another address frame is received.
23.9.1 Using MPCMn
For an MCU to act as a master MCU, it can use a 9 bit character frame format
th(UCSZn2:0 = 7). The 9 bit (TXB8n) must be set when an address frame (TXB8n = 1)
or cleared when a data frame (TXB = 0) is being transmitted. The slave MCUs must in
this case be set to use a 9 bit character frame format.
The following procedure should be used to exchange data in multi-processor
communication mode:
1. All slave MCUs are in multi-processor communication mode (MPCMn in UCSRnA is
set).
2. The master MCU sends an address frame, and all slaves receive and read thisframe. In the slave MCUs, the RXCn flag in UCSRnA will be set as normal.
3. Each slave MCU reads the UDRn register and determines if it has been selected. If
so, it clears the MPCMn bit in UCSRnA, otherwise it waits for the next address byte
and keeps the MPCMn setting.
4. The addressed MCU will receive all data frames until a new address frame isreceived. The other slave MCUs, which still have the MPCMn bit set, will ignore thedata frames.
5. When the last data frame is received by the addressed MCU, the addressed MCU
sets the MPCMn bit and waits for a new address frame from master. The process
then repeats from 2.
Using any of the 5 to 8 bit character frame formats is possible, but impractical since thereceiver must change between using n and n+1 character frame formats. This makes
full-duplex operation difficult since the transmitter and receiver uses the same charactersize setting. If 5 to 8 bit character frames are used, the transmitter must be set to use
two stop bit (USBSn = 1) since the first stop bit is used for indicating the frame type.

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Do not use read-modify-write instructions (SBI and CBI) to set or clear the MPCMn bit.
The MPCMn bit shares the same I/O location as the TXCn flag and this might
accidentally be cleared when using SBI or CBI instructions.

23.10 Register Description
23.10.1 UDR0 – USART0 I/O Data Register
Bit

7

6

5

4

NA ($C6)
Read/Write
Initial Value

3

2

1

0

UDR07:00
RW
0

RW
0

RW
0

RW
0

UDR0

RW
0

RW
0

RW
0

RW
0

The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers
share the same I/O address referred to as USART Data Register or UDR0. The
Transmit Data Buffer Register (TXB) will be the destination for data written to the UDR0
Register location. Reading the UDR0 Register location will return the contents of theReceive Data Buffer Register (RXB). For 5-, 6-, or 7-bit characters the upper unused
bits will be ignored by the Transmitter and set to zero by the Receiver. The transmit
buffer can only be written when the UDRE0 Flag in the UCSR0A Register is set. Data
written to UDR0 when the UDRE0 Flag is not set, will be ignored by the USARTTransmitter. When data is written to the transmit buffer and the Transmitter is enabled,
the Transmitter will load the data into the Transmit Shift Register when the Shift
Register is empty. Then the data will be serially transmitted on the TxD0 pin. The
receive buffer consists of a two level FIFO. The FIFO will change its state whenever thereceive buffer is accessed. Due to this behavior of the receive buffer, do not use ReadModify-Write instructions (SBI and CBI) on this location. Be careful when using bit test
instructions (SBIC and SBIS), since these also will change the state of the FIFO.
• Bit 7:0 – UDR07:00 - USART I/O Data Register23.10.2 UCSR0A – USART0 Control and Status Register A
Bit

7

6

5

4

3

2

1

0

NA ($C0)

RXC0

TXC0

UDRE0

FE0

DOR0

UPE0

U2X0

MPCM0

Read/Write
Initial Value

R
0

RW
0

R
1

R
0

R
0

R
0

RW
0

RW
0

UCSR0A• Bit 7 – RXC0 - USART Receive Complete
This flag bit is set when there are unread data in the receive buffer and cleared when
the receive buffer is empty (i.e., does not contain any unread data). If the Receiver isdisabled, the receive buffer will be flushed and consequently the RXC0 bit will become
zero. The RXC0 Flag can be used to generate a Receive Complete interrupt (seedescription of the RXCIE0 bit).
• Bit 6 – TXC0 - USART Transmit Complete
This flag bit is set when the entire frame in the Transmit Shift Register has been shiftedout and there are no new data currently present in the transmit buffer (UDR0). The
TXC0 Flag bit is automatically cleared when a transmit complete interrupt is executed,
or it can be cleared by writing a one to its bit location. The TXC0 Flag can generate aTransmit Complete interrupt (see description of the TXCIE0 bit).

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ATmega128RFA1• Bit 5 – UDRE0 - USART Data Register Empty
The UDRE0 Flag indicates if the transmit buffer (UDR0) is ready to receive new data. If
UDRE0 is one, the buffer is empty, and therefore ready to be written. The UDRE0 Flag
can generate a Data Register Empty interrupt (see description of the UDRIE0 bit).
UDRE0 is set after a reset to indicate that the Transmitter is ready.
• Bit 4 – FE0 - Frame Error
This bit is set if the next character in the receive buffer had a Frame Error when
received. I.e., when the first stop bit of the next character in the receive buffer is zero.
This bit is valid until the receive buffer (UDR0) is read. The FE0 bit is zero when thestop bit of received data is one. Always set this bit to zero when writing to UCSR0A.
• Bit 3 – DOR0 - Data OverRun
This bit is set if a Data OverRun condition is detected. A Data OverRun occurs when
the receive buffer is full (two characters), it is a new character waiting in the Receive
Shift Register and a new start bit is detected. This bit is valid until the receive buffer(UDR0) is read. Always set this bit to zero when writing to UCSR0A.
• Bit 2 – UPE0 - USART Parity Error
This bit is set if the next character in the receive buffer had a Parity Error when received
and the Parity Checking was enabled at that point (UPM01 = 1). This bit is valid until thereceive buffer (UDR0) is read. Always set this bit to zero when writing to UCSR0A.
• Bit 1 – U2X0 - Double the USART Transmission Speed
This bit only has effect for the asynchronous operation. Write this bit to zero when usingsynchronous operation. Writing this bit to one will reduce the divisor of the baud rate
divider from 16 to 8 effectively doubling the transfer rate for asynchronous
communication.
• Bit 0 – MPCM0 - Multi-processor Communication Mode
This bit enables the Multi-processor Communication mode. When the MPCM0 bit is
written to one, all the incoming frames received by the USART Receiver that do notcontain address information will be ignored. The Transmitter is unaffected by the
MPCM0 setting. For more detailed information see section "Multi-processor
Communication Mode".

23.10.3 UCSR0B – USART0 Control and Status Register B
Bit

7

6

5

4

3

2

1

0

NA ($C1)RXCIE0TXCIE0

UDRIE0

RXEN0

TXEN0

UCSZ02

RXB80

TXB80

Read/Write
Initial Value

RW
0

RW
0

RW
1

RW
0

RW
0

RW
0

R
0

W
0

UCSR0B• Bit 7 – RXCIE0 - RX Complete Interrupt Enable
Writing this bit to one enables interrupt on the RXC0 Flag. A USART Receive Complete
interrupt will be generated only if the RXCIE0 bit is written to one, the Global Interrupt
Flag in SREG is written to one and the RXC0 bit in UCSR0A is set.
• Bit 6 – TXCIE0 - TX Complete Interrupt Enable
Writing this bit to one enables interrupt on the TXC0 Flag. A USART Transmit Complete
interrupt will be generated only if the TXCIE0 bit is written to one, the Global Interrupt
Flag in SREG is written to one and the TXC0 bit in UCSR0A is set.
• Bit 5 – UDRIE0 - USART Data Register Empty Interrupt Enable
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Writing this bit to one enables interrupt on the UDRE0 Flag. A Data Register Emptyinterrupt will be generated only if the UDRIE0 bit is written to one, the Global Interrupt
Flag in SREG is written to one and the UDRE0 bit in UCSR0A is set.
• Bit 4 – RXEN0 - Receiver Enable
Writing this bit to one enables the USART Receiver. The Receiver will override normal
port operation for the RxD0 pin when enabled. Disabling the Receiver will flush thereceive buffer invalidating the FE0, DOR0 and UPE0 Flags.
• Bit 3 – TXEN0 - Transmitter Enable
Writing this bit to one enables the USART Transmitter. The Transmitter will override
normal port operation for the TxD0 pin when enabled. The disabling of the Transmitter(writing TXEN0 to zero) will not become effective until ongoing and pendingtransmissions are completed, i.e., when the Transmit Shift Register and Transmit Buffer
Register do not contain data to be transmitted. When disabled, the Transmitter will nolonger override the TxD0 port.
• Bit 2 – UCSZ02 - Character Size
The UCSZ02 bits combined with the UCSZ01:0 bit in UCSR0C sets the number of databits (Character Size) in the frame that the Receiver and Transmitter use.
• Bit 1 – RXB80 - Receive Data Bit 8
RXB80 is the 9th data bit of the received character when operating with serial frameswith nine data bits. The bit must be read before reading the lower 8 bits from UDR0.
• Bit 0 – TXB80 - Transmit Data Bit 8
TXB80 is the 9th data bit in the character to be transmitted when operating with serial
frames with nine data bits. The bit must be written before writing the lower 8 bits to
UDR0.

23.10.4 UCSR0C – USART0 Control and Status Register C
Bit
NA ($C2)

7

6

UMSEL01 UMSEL00

Read/Write
Initial Value

RW
0

RW
0

5

4

3

UPM01

UPM00

USBS0

RW
0

RW
0

RW
0

2

1

0

UCSZ01 UCSZ00 UCPOL0
RW
0

RW
1

UCSR0CRW
0• Bit 7:6 – UMSEL01:00 - USART Mode Select
These bits select the mode of operation of the USART0 as shown in the following table.
See section "USART in SPI Mode" for a full description of the Master SPI Mode(MSPIM) operation.
Table 23-4 UMSEL0 Register Bits
Register Bits

Value

Description

UMSEL01:00

0x00

Asynchronous USART

0x01

Synchronous USART

0x02

Reserved

0x03

Master SPI (MSPIM)• Bit 5:4 – UPM01:00 - Parity Mode
These bits enable and set type of parity generation and check. If enabled, theTransmitter will automatically generate and send the parity of the transmitted data bits
within each frame. The Receiver will generate a parity value for the incoming data and358

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ATmega128RFA1
compare it to the UPM0 setting. If a mismatch is detected, the UPE0 Flag in UCSR0A
will be set.
Table 23-5 UPM0 Register Bits
Register Bits

Value

Description

UPM01:00

0x00

Disabled

0x01

Reserved

0x02

Enabled, Even Parity

0x03

Enabled, Odd Parity• Bit 3 – USBS0 - Stop Bit SelectThis bit selects the number of stop bits to be inserted by the Transmitter. The Receiver
ignores this setting.
Table 23-6 USBS0 Register Bits
Register Bits

Value

Description

USBS0

0x00

1-bit

0x01

2-bit

• Bit 2:1 – UCSZ01:00 - Character Size
The UCSZ01:0 bits combined with the UCSZ02 bit in UCSR0B sets the number of databits (Character Size) in the frame that the Receiver and Transmitter use.
Table 23-7 UCSZ0 Register Bits
Register BitsValue

UCSZ01:00

0

5-bit

Description

1

6-bit

2

7-bit

3

8-bit

4

Reserved

5

Reserved

6

Reserved

79-bit• Bit 0 – UCPOL0 - Clock Polarity
This bit is used for synchronous mode only. Write this bit to zero when asynchronousmode is used. The UCPOL0 bit sets the relationship between data output change anddata input sample, and the synchronous clock (XCK0).
Table 23-8 UCPOL0 Register Bits
Register Bits
UCPOL0Value

Description

0

Rising XCKn Edge (Transmitted Data
Changed), Falling XCKn Edge (Received
Data Sampled)

1

Falling XCKn Edge (Transmitted Data
Changed), Rising XCKn Edge (Received
Data Sampled)

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23.10.5 UBRR0H – USART0 Baud Rate Register High Byte
Bit

7

6

5

4

NA ($C5)

Res3

Res2

Res1

Res0

Read/Write
Initial Value

R
0

R
0

R
0

R
0

3

2

UBRR11 UBRR10
RW
0

RW
0

1

0

UBRR9

UBRR8

RW
0

RW
0

UBRR0HUBRR0 is a 12-bit register which contains the USART baud rate. The UBRR0H
contains the four most significant bits, and the UBRR0L contains the eight leastsignificant bits of the USART baud rate. Ongoing transmissions by the Transmitter andReceiver will be corrupted if the baud rate is changed. Writing UBRR0L will trigger an
immediate update of the baud rate prescaler.
• Bit 7:4 – Res3:0 - Reserved Bit
This bit is reserved for future use. A read access always will return zero. A write accessdoes not modify the content.
• Bit 3:0 – UBRR11:8 - USART Baud Rate Register
These bits represent bits [11:8] of the Baud Rate Register. Sample values forcommonly used clock frequencies can be found in section "Examples of Baud Rate
Setting".

23.10.6 UBRR0L – USART0 Baud Rate Register Low Byte
Bit

7

6

5

4

3

2

1

0

NA ($C4)

UBRR7

UBRR6

UBRR5

UBRR4

UBRR3

UBRR2

UBRR1

UBRR0

Read/Write
Initial Value

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

UBRR0LUBRR0 is a 12-bit register which contains the USART baud rate. The UBRR0H
contains the four most significant bits, and the UBRR0L contains the eight leastsignificant bits of the USART baud rate. Ongoing transmissions by the Transmitter andReceiver will be corrupted if the baud rate is changed. Writing UBRR0L will trigger an
immediate update of the baud rate prescaler.
• Bit 7:0 – UBRR7:0 - USART Baud Rate Register
These bits represent bits [7:0] of the Baud Rate Register. Sample values for commonlyused clock frequencies can be found in section "Examples of Baud Rate Setting".

23.10.7 UDR1 – USART1 I/O Data Register
Bit

7

6

5

NA ($CE)
Read/Write
Initial Value

4

3

2

1

0

UDR17:10
RW
0

RW
0

RW
0

RW
0

RW
0

UDR1
RW
0

RW
0

RW
0

The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers
share the same I/O address referred to as USART Data Register or UDR1. The
Transmit Data Buffer Register (TXB) will be the destination for data written to the UDR1
Register location. Reading the UDR1 Register location will return the contents of the360

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ATmega128RFA1
Receive Data Buffer Register (RXB). For 5-, 6-, or 7-bit characters the upper unused
bits will be ignored by the Transmitter and set to zero by the Receiver. The transmit
buffer can only be written when the UDRE1 Flag in the UCSR1A Register is set. Data
written to UDR1 when the UDRE1 Flag is not set, will be ignored by the USARTTransmitter. When data is written to the transmit buffer and the Transmitter is enabled,
the Transmitter will load the data into the Transmit Shift Register when the Shift
Register is empty. Then the data will be serially transmitted on the TxD1 pin. The
receive buffer consists of a two level FIFO. The FIFO will change its state whenever thereceive buffer is accessed. Due to this behavior of the receive buffer, do not use ReadModify-Write instructions (SBI and CBI) on this location. Be careful when using bit test
instructions (SBIC and SBIS), since these also will change the state of the FIFO.
• Bit 7:0 – UDR17:10 - USART I/O Data Register23.10.8 UCSR1A – USART1 Control and Status Register A
Bit

7

6

5

4

3

2

1

0

NA ($C8)

RXC1

TXC1

UDRE1

FE1

DOR1

UPE1

U2X1

MPCM1

Read/Write
Initial Value

R
0

RW
0

R
1

R
0

R
0

R
0

RW
0

RW
0

UCSR1A• Bit 7 – RXC1 - USART Receive Complete
This flag bit is set when there are unread data in the receive buffer and cleared when
the receive buffer is empty (i.e., does not contain any unread data). If the Receiver isdisabled, the receive buffer will be flushed and consequently the RXC1 bit will become
zero. The RXC1 Flag can be used to generate a Receive Complete interrupt (seedescription of the RXCIE1 bit).
• Bit 6 – TXC1 - USART Transmit Complete
This flag bit is set when the entire frame in the Transmit Shift Register has been shiftedout and there are no new data currently present in the transmit buffer (UDR1). The
TXC1 Flag bit is automatically cleared when a transmit complete interrupt is executed,
or it can be cleared by writing a one to its bit location. The TXC1 Flag can generate aTransmit Complete interrupt (see description of the TXCIE1 bit).
• Bit 5 – UDRE1 - USART Data Register Empty
The UDRE1 Flag indicates if the transmit buffer (UDR1) is ready to receive new data. If
UDRE1 is one, the buffer is empty, and therefore ready to be written. The UDRE1 Flag
can generate a Data Register Empty interrupt (see description of the UDRIE1 bit).
UDRE1 is set after a reset to indicate that the Transmitter is ready.
• Bit 4 – FE1 - Frame Error
This bit is set if the next character in the receive buffer had a Frame Error when
received. I.e., when the first stop bit of the next character in the receive buffer is zero.
This bit is valid until the receive buffer (UDR1) is read. The FE1 bit is zero when thestop bit of received data is one. Always set this bit to zero when writing to UCSR1A.
• Bit 3 – DOR1 - Data OverRun
This bit is set if a Data OverRun condition is detected. A Data OverRun occurs when
the receive buffer is full (two characters), it is a new character waiting in the Receive
Shift Register and a new start bit is detected. This bit is valid until the receive buffer(UDR1) is read. Always set this bit to zero when writing to UCSR1A.
• Bit 2 – UPE1 - USART Parity Error

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This bit is set if the next character in the receive buffer had a Parity Error when received
and the Parity Checking was enabled at that point (UPM11 = 1). This bit is valid until thereceive buffer (UDR1) is read. Always set this bit to zero when writing to UCSR1A.
• Bit 1 – U2X1 - Double the USART Transmission Speed
This bit only has effect for the asynchronous operation. Write this bit to zero when usingsynchronous operation. Writing this bit to one will reduce the divisor of the baud rate
divider from 16 to 8 effectively doubling the transfer rate for asynchronous
communication.
• Bit 0 – MPCM1 - Multi-processor Communication Mode
This bit enables the Multi-processor Communication mode. When the MPCM1 bit is
written to one, all the incoming frames received by the USART Receiver that do notcontain address information will be ignored. The Transmitter is unaffected by the
MPCM1 setting. For more detailed information see section "Multi-processor
Communication Mode".

23.10.9 UCSR1B – USART1 Control and Status Register B
Bit

7

6

5

4

3

2

1

0

NA ($C9)RXCIE1TXCIE1

UDRIE1

RXEN1

TXEN1

UCSZ12

RXB81

TXB81

Read/Write
Initial Value

RW
0

RW
0

RW
1

RW
0

RW
0

RW
0

R
0

W
0

UCSR1B• Bit 7 – RXCIE1 - RX Complete Interrupt Enable
Writing this bit to one enables interrupt on the RXC1 Flag. A USART Receive Complete
interrupt will be generated only if the RXCIE1 bit is written to one, the Global Interrupt
Flag in SREG is written to one and the RXC1 bit in UCSR1A is set.
• Bit 6 – TXCIE1 - TX Complete Interrupt Enable
Writing this bit to one enables interrupt on the TXC1 Flag. A USART Transmit Complete
interrupt will be generated only if the TXCIE1 bit is written to one, the Global Interrupt
Flag in SREG is written to one and the TXC1 bit in UCSR1A is set.
• Bit 5 – UDRIE1 - USART Data Register Empty Interrupt Enable
Writing this bit to one enables interrupt on the UDRE1 Flag. A Data Register Emptyinterrupt will be generated only if the UDRIE1 bit is written to one, the Global Interrupt
Flag in SREG is written to one and the UDRE1 bit in UCSR1A is set.
• Bit 4 – RXEN1 - Receiver Enable
Writing this bit to one enables the USART Receiver. The Receiver will override normal
port operation for the RxD1 pin when enabled. Disabling the Receiver will flush thereceive buffer invalidating the FE1, DOR1 and UPE1 Flags.
• Bit 3 – TXEN1 - Transmitter Enable
Writing this bit to one enables the USART Transmitter. The Transmitter will override
normal port operation for the TxD1 pin when enabled. The disabling of the Transmitter(writing TXEN1 to zero) will not become effective until ongoing and pendingtransmissions are completed, i.e., when the Transmit Shift Register and Transmit Buffer
Register do not contain data to be transmitted. When disabled, the Transmitter will nolonger override the TxD1 port.
• Bit 2 – UCSZ12 - Character Size

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ATmega128RFA1
The UCSZ12 bits combined with the UCSZ11:0 bit in UCSR1C sets the number of databits (Character Size) in the frame that the Receiver and Transmitter use.
• Bit 1 – RXB81 - Receive Data Bit 8
RXB81 is the 9th data bit of the received character when operating with serial frameswith nine data bits. The bit must be read before reading the lower 8 bits from UDR1.
• Bit 0 – TXB81 - Transmit Data Bit 8
TXB81 is the 9th data bit in the character to be transmitted when operating with serial
frames with nine data bits. The bit must be written before writing the lower 8 bits to
UDR1.

23.10.10 UCSR1C – USART1 Control and Status Register C
Bit
NA ($CA)

7

6

UMSEL11 UMSEL10

Read/Write
Initial Value

RW
0

RW
0

5

4

3

UPM11

UPM10

USBS1

RW
0

RW
0

RW
0

2

1

0

UCSZ11 UCSZ10 UCPOL1
RW
1

RW
1

UCSR1CRW
0• Bit 7:6 – UMSEL11:10 - USART Mode Select
These bits select the mode of operation of the USART1 as shown in the following table.
See section "USART in SPI Mode" for a full description of the Master SPI Mode(MSPIM) operation.
Table 23-9 UMSEL1 Register Bits
Register Bits

Value

Description

UMSEL11:10

0x00

Asynchronous USART

0x01

Synchronous USART

0x02

Reserved

0x03

Master SPI (MSPIM)• Bit 5:4 – UPM11:10 - Parity Mode
These bits enable and set type of parity generation and check. If enabled, theTransmitter will automatically generate and send the parity of the transmitted data bits
within each frame. The Receiver will generate a parity value for the incoming data andcompare it to the UPM1 setting. If a mismatch is detected, the UPE1 Flag in UCSR1A
will be set.
Table 23-10 UPM1 Register Bits
Register Bits

Value

Description

UPM11:10

0x00

Disabled

0x01

Reserved

0x02

Enabled, Even Parity

0x03

Enabled, Odd Parity• Bit 3 – USBS1 - Stop Bit SelectThis bit selects the number of stop bits to be inserted by the Transmitter. The Receiver
ignores this setting.

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8266A-MCU Wireless-12/09

Table 23-11 USBS1 Register Bits
Register Bits

Value

Description

USBS1

0x00

1-bit

0x01

2-bit

• Bit 2:1 – UCSZ11:10 - Character Size
The UCSZ11:0 bits combined with the UCSZ12 bit in UCSR1B sets the number of databits (Character Size) in the frame that the Receiver and Transmitter use.
Table 23-12 UCSZ1 Register Bits
Register Bits

Value

Description

UCSZ11:10

0

5-bit

1

6-bit

2

7-bit

3

8-bit

4

Reserved

5

Reserved

6

Reserved

79-bit• Bit 0 – UCPOL1 - Clock Polarity
This bit is used for synchronous mode only. Write this bit to zero when asynchronousmode is used. The UCPOL1 bit sets the relationship between data output change anddata input sample, and the synchronous clock (XCK1).
Table 23-13 UCPOL1 Register Bits
Register BitsValue

UCPOL1

Description

0

Rising XCKn Edge (Transmitted Data
Changed), Falling XCKn Edge (Received
Data Sampled)

1

Falling XCKn Edge (Transmitted Data
Changed), Rising XCKn Edge (Received
Data Sampled)

23.10.11 UBRR1H – USART1 Baud Rate Register High Byte
Bit

7

6

5

4

NA ($CD)

Res3

Res2

Res1

Res0

Read/Write
Initial Value

R
0

R
0

R
0

R
0

3

2

UBRR11 UBRR10
RW
0

RW
0

1

0

UBRR9

UBRR8

RW
0

RW
0

UBRR1HUBRR1 is a 12-bit register which contains the USART baud rate. The UBRR1H
contains the four most significant bits, and the UBRR1L contains the eight leastsignificant bits of the USART baud rate. Ongoing transmissions by the Transmitter andReceiver will be corrupted if the baud rate is changed. Writing UBRR1L will trigger an
immediate update of the baud rate prescaler.
• Bit 7:4 – Res3:0 - Reserved Bit
This bit is reserved for future use. A read access always will return zero. A write accessdoes not modify the content.

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ATmega128RFA1
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ATmega128RFA1• Bit 3:0 – UBRR11:8 - USART Baud Rate Register
These bits represent bits [11:8] of the Baud Rate Register. Sample values forcommonly used clock frequencies can be found in section "Examples of Baud Rate
Setting".

23.10.12 UBRR1L – USART1 Baud Rate Register Low Byte
Bit

7

6

5

4

3

2

1

0

NA ($CC)

UBRR7

UBRR6

UBRR5

UBRR4

UBRR3

UBRR2

UBRR1

UBRR0

Read/Write
Initial Value

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

UBRR1LUBRR1 is a 12-bit register which contains the USART baud rate. The UBRR1H
contains the four most significant bits, and the UBRR1L contains the eight leastsignificant bits of the USART baud rate. Ongoing transmissions by the Transmitter andReceiver will be corrupted if the baud rate is changed. Writing UBRR1L will trigger an
immediate update of the baud rate prescaler.
• Bit 7:0 – UBRR7:0 - USART Baud Rate Register
These bits represent bits [7:0] of the Baud Rate Register. Sample values for commonlyused clock frequencies can be found in section "Examples of Baud Rate Setting".

23.11 Examples of Baud Rate Setting
For standard crystal and resonator frequencies, the most commonly used baud rates forasynchronous operation can be generated by using the UBRR settings in Table 23-14
below to Table 23-16 on page 367. UBRR values which yield an actual baud rate
differing less than 0.5% from the target baud rate, are bold in the table. Higher error
ratings are acceptable, but the Receiver will have less noise resistance when the error
ratings are high, especially for large serial frames (see "Asynchronous Operational
Range" on page 353). The error values are calculated using the following equation:

 BaudRate Closest Match
Error [% ] = 
− 1 ⋅ 100 %BaudRate
Table 23-14. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies
fOSC = 1.8432 MHz

fOSC = 2.0000 MHz

fOSC = 3.6864 MHz

Baud
Rate
(bps)

U2Xn = 0
UBRR

Error

UBRR

Error

UBRR

Error

UBRR

Error

UBRR

Error

UBRR

Error

2400

47

0.0%

95

0.0%

51

0.2%

103

0.2%

95

0.0%

191

0.0%

4800

23

0.0%

47

0.0%

25

0.2%

51

0.2%

47

0.0%

95

0.0%

9600

11

0.0%

23

0.0%

12

0.2%

25

0.2%

23

0.0%

47

0.0%

14.4k

7

0.0%

15

0.0%

8

-3.5%

16

2.1%

15

0.0%

31

0.0%

19.2k

5

0.0%

11

0.0%

6

-7.0%

12

0.2%

11

0.0%

23

0.0%

28.8k

3

0.0%

7

0.0%

3

8.5%

8

-3.5%

7

0.0%

15

0.0%

38.4k

2

0.0%

5

0.0%

2

8.5%

6

-7.0%

5

0.0%

11

0.0%

U2Xn = 1

U2Xn = 0

U2Xn = 1

U2Xn = 0

U2Xn = 1

365
8266A-MCU Wireless-12/09

fOSC = 1.8432 MHz

fOSC = 2.0000 MHz

fOSC = 3.6864 MHz

Baud
Rate
(bps)

U2Xn = 0
UBRR

Error

UBRR

Error

UBRR

Error

UBRR

Error

UBRR

Error

UBRR

Error

57.6k

1

0.0%

3

0.0%

1

8.5%

3

8.5%

3

0.0%

7

0.0%

76.8k

1

-25.0%

20.0%

1-18.6%

2

8.5%

2

0.0%

5

0.0%

115.2k

0

0.0%

1

0.0%

0

8.5%

1

8.5%

1

0.0%

3

0.0%

230.4k

-

-

0

0.0%

-

-

-

-

0

0.0%

1

0.0%

250k

-

-

-

-

-

-

0

0.0%%

0

-7.8%

1

-7.8%

Max.

(1)

Notes:

U2Xn = 1

115.2 kbps

U2Xn = 0230.4 kbps

U2Xn = 1

125 kbps

U2Xn = 0

U2Xn = 1

230.4 kbps

250 kbps

460.8 kbps

1. UBRR = 0, Error = 0.0%

Table 23-15. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued)
fOSC = 4.0000 MHz
Baud
Rate
(bps)

U2Xn = 0

fOSC = 7.3728 MHz
U2Xn = 1

U2Xn = 0

fOSC = 8.0000 MHz
U2Xn = 1

U2Xn = 0

U2Xn = 1

UBRR

Error

UBRR

Error

UBRR

Error

UBRR

Error

UBRR

Error

UBRR

Error

2400

103

0.2%

207

0.2%

191

0.0%

383

0.0%

207

0.2%

416

-0.1%

4800

51

0.2%

103

0.2%

95

0.0%

191

0.0%

103

0.2%

207

0.2%

9600

25

0.2%

51

0.2%

47

0.0%

95

0.0%

51

0.2%

103

0.2%

14.4k

16

2.1%

34

-0.8%

31

0.0%

63

0.0%

34

-0.8%

68

0.6%

19.2k

12

0.2%

25

0.2%

23

0.0%

47

0.0%

25

0.2%

51

0.2%

28.8k

8

-3.5%

16

2.1%

15

0.0%

31

0.0%

16

2.1%

34

-0.8%

38.4k

6

-7.0%

12

0.2%

11

0.0%

23

0.0%

12

0.2%

25

0.2%

57.6k

3

8.5%

8

-3.5%

7

0.0%

15

0.0%

8

-3.5%

16

2.1%

76.8k

2

8.5%

6

-7.0%

5

0.0%

11

0.0%

6

-7.0%

12

0.2%

115.2k

1

8.5%

3

8.5%

3

0.0%

7

0.0%

3

8.5%

8

-3.5%

230.4k

0

8.5%

1

8.5%

1

0.0%

3

0.0%

1

8.5%

3

8.5%

250k

0

0.0%

1

0.0%

1

-7.8%

3

-7.8%

1

0.0%

3

0.0%

0.5M

-

-

0

0.0%

0

-7.8%

1

-7.8%

0

0.0%

1

0.0%

-

-

-

-

-

-

0

-7.8%

-

-

0

0.0%

1M
Max.

(1)

Notes:

366

250 kbps

0.5 Mbps

460.8 kbps

921.6 kbps

0.5 Mbps

1 Mbps

1. UBRR = 0, Error = 0.0%

ATmega128RFA1
8266A-MCU Wireless-12/09

ATmega128RFA1
Table 23-16. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued)
fOSC = 11.0592 MHz
Baud
Rate
(bps)

U2Xn = 0

fOSC = 14.7456 MHz
U2Xn = 1

U2Xn = 0

fOSC = 16.0000 MHz
U2Xn = 1

U2Xn = 0

U2Xn = 1

UBRR

Error

UBRR

Error

UBRR

Error

UBRR

Error

UBRR

Error

UBRR

Error

2400

287

0.0%

575

0.0%

383

0.0%

767

0.0%

416

-0.1%

832

0.0%

4800

143

0.0%

287

0.0%

191

0.0%

383

0.0%

207

0.2%

416

-0.1%

9600

71

0.0%

143

0.0%

95

0.0%

191

0.0%

103

0.2%

207

0.2%

14.4k

47

0.0%

95

0.0%

63

0.0%

127

0.0%

68

0.6%

138

-0.1%

19.2k

35

0.0%

71

0.0%

47

0.0%

95

0.0%

51

0.2%

103

0.2%

28.8k

23

0.0%

47

0.0%

31

0.0%

63

0.0%

34

-0.8%

68

0.6%

38.4k

17

0.0%

35

0.0%

23

0.0%

47

0.0%

25

0.2%

51

0.2%

57.6k

11

0.0%

23

0.0%

15

0.0%

31

0.0%

16

2.1%

34

-0.8%

76.8k

8

0.0%

17

0.0%

11

0.0%

23

0.0%

12

0.2%

25

0.2%

115.2k

5

0.0%

11

0.0%

7

0.0%

15

0.0%

8

-3.5%

16

2.1%

230.4k

2

0.0%

5

0.0%

3

0.0%

7

0.0%

3

8.5%

8

-3.5%

250k

2

-7.8%

5

-7.8%

3

-7.8%

6

5.3%

3

0.0%

7

0.0%

0.5M

-

-

2

-7.8%

1

-7.8%

3

-7.8%

1

0.0%

3

0.0%

-

-

-

-

0

-7.8%

1

-7.8%

0

0.0%

1

0.0%

1M
Max.

(1)

Notes:

691.2 kbps

1.3824 Mbps

921.6 kbps

1.8432 Mbps

1 Mbps

2 Mbps

1. UBRR = 0, Error = 0.0%

367
8266A-MCU Wireless-12/09

24 USART in SPI Mode
The Universal Synchronous and Asynchronous Serial Receiver and Transmitter(USART) can be set to a master SPI compliant mode of operation. The Master SPI
Mode (MSPIM) has the following features:• Full duplex, three-wire synchronous data transfer• Master operation• Supports all four SPI modes of operation (mode 0, 1, 2, and 3)• LSB first or MSB first data transfer (configurable data order)• Queued operation (double buffered)• High resolution baud rate generator• High speed operation (fXCK,MAX = fCK/2)• Flexible interrupt generation

24.1 Overview
Setting both UMSELn1:0 bits to one enables the USART in MSPIM logic. In this modeof operation the SPI master control logic takes direct control over the USART
resources. These resources include the transmitter and receiver shift register andbuffers, and the baud rate generator. The parity generator and checker, the data andclock recovery logic, and the RX and TX control logic is disabled. The USART RX and
TX control logic is replaced by a common SPI transfer control logic. However, the pin
control logic and interrupt generation logic is identical in both modes of operation.
The I/O register locations are the same in both modes. However, some of thefunctionality of the control registers changes when using MSPIM.

24.2 USART MSPIM vs. SPI
The ATmega128RFA1 USART in MSPIM mode is fully compatible with the
ATmega128RFA1 SPI regarding:• Master mode timing diagram.
• The UCPOLn bit functionality is identical to the SPI CPOL bit.
• The UCPHAn bit functionality is identical to the SPI CPHA bit.
• The UDORDn bit functionality is identical to the SPI DORD bit.
However, since the USART in MSPIM mode reuses the USART resources, the use of
the USART in MSPIM mode is somewhat different compared to the SPI. In addition todifferences of the control register bits, and that only master operation is supported by
the USART in MSPIM mode, the following features differ between the two modules:• The USART in MSPIM mode includes (double) buffering of the transmitter. The SPI
has no buffer.
• The USART in MSPIM mode receiver includes an additional buffer level.
• The SPI WCOL (Write Collision) bit is not included in USART in MSPIM mode.
• The SPI double speed mode (SPI2X) bit is not included. However, the same effect isachieved by setting UBRRn accordingly.
• Interrupt timing is not compatible.
• Pin control differs due to the master only operation of the USART in MSPIM mode.
A comparison of the USART in MSPIM mode and the SPI pins is shown in Table 24–3
on page 373.

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ATmega128RFA1
24.2.1 Clock Generation
The Clock Generation logic generates the base clock for the Transmitter and Receiver.
For USART MSPIM mode of operation only internal clock generation (i.e. master
operation) is supported. The Data Direction Register for the XCKn pin (DDR_XCKn)
must therefore be set to one (i.e. as output) for the USART in MSPIM to operatecorrectly. Preferably the DDR_XCKn should be set up before the USART in MSPIM isenabled (i.e. TXENn and RXENn bit set to one).
The internal clock generation used in MSPIM mode is identical to the USART
synchronous master mode. The baud rate or UBRRn setting can therefore be
calculated using the same equations, see Table 24-1 below:
Table 24-1. Equations for Calculating Baud Rate Register Setting
Operating Mode

Equation for Calculating(1)
Baud Rate

Synchronous Master mode

BAUD =Note:f OSC
2(UBRRn + 1)

Equation for Calculating
UBRR ValueUBRRn =f OSC
−1
2 BAUD

The Baud rate is defined to be the transfer rate in bit per second (bps)
BAUD Baud rate (in bits per second, bps)
fOSC

System Oscillator clock frequency

UBRRn Contents of the UBRRHn and UBRRLn Registers, (0-4095)

24.3 SPI Data Modes and Timing
There are four combinations of XCKn (SCK) phase and polarity with respect to serial
data, which are determined by control bits UCPHAn and UCPOLn. The data transfer
timing diagrams are shown in Figure 24-1 below. Data bits are shifted out and latchedin on opposite edges of the XCKn signal, ensuring sufficient time for data signals tostabilize. The UCPOLn and UCPHAn functionality is summarized in Table 24-2 below.
Note that changing the setting of any of these bits will corrupt all ongoing
communication for both the receiver and transmitter.
Figure 24-1. UCPHAn and UCPOLn data transfer timing diagrams

UCPHA=0

UCPHA=1

UCPOL=0UCPOL=1

XCK

XCK

Data setup (TXD)

Data setup (TXD)

Data sample (RXD)

Data sample (RXD)

XCK

XCK

Data setup (TXD)

Data setup (TXD)

Data sample (RXD)

Data sample (RXD)

Table 24-2. UCPOLn and UCPHAn Functionality
UCPOLnUCPHAn

SPI Mode

Leading Edge

Trailing Edge

0

0

0

Sample (Rising)

Setup (Falling)

0

1

1

Setup (Rising)

Sample (Falling)

1

0

2

Sample (Falling)

Setup (Rising)

369
8266A-MCU Wireless-12/09

UCPOLn

UCPHAn

SPI Mode

Leading Edge

Trailing Edge

1

1

3

Setup (Falling)

Sample (Rising)

24.4 Frame Formats
A serial frame for the MSPIM is defined to be one character of 8 data bits. The USARTin MSPIM mode has two valid frame formats:• 8-bit data with MSB first• 8-bit data with LSB firstA frame starts with the least or most significant data bit. Then the next data bits, up to a
total of eight, are succeeding, ending with the most or least significant bit accordingly.
When a complete frame is transmitted, a new frame can directly follow it, or thecommunication line can be set to an idle (high) state.
The UDORDn bit in UCSRnC sets the frame format used by the USART in MSPIM
mode. The Receiver and Transmitter use the same setting. Note that changing thesetting of any of these bits will corrupt all ongoing communication for both the Receiverand Transmitter.
16-bit data transfer can be achieved by writing two data bytes to UDRn. A UART
transmit complete interrupt will then signal that the 16-bit value has been shifted out.
24.4.1 USART MSPIM Initialization
The USART in MSPIM mode has to be initialized before any communication can takeplace. The initialization process normally consists of setting the baud rate, setting
master mode of operation (by setting DDR_XCKn to one), setting frame format andenabling the Transmitter and the Receiver. Only the transmitter can operate
independently. For interrupt driven USART operation, the Global Interrupt Flag should
be cleared (and thus interrupts globally disabled) when doing the initialization.
Note:

To ensure immediate initialization of the XCKn output the baud-rate register(UBRRn) must be zero at the time the transmitter is enabled. Contrary to thenormal mode USART operation the UBRRn must then be written to the desired
value after the transmitter is enabled, but before the first transmission isstarted. Setting UBRRn to zero before enabling the transmitter is not necessary
if the initialization is done immediately after a reset since UBRRn is reset tozero.

Before doing a re-initialization with changed baud rate, data mode, or frame format, besure that there is no ongoing transmissions during the period the registers are changed.
The TXCn Flag can be used to check that the Transmitter has completed all transfers,
and the RXCn Flag can be used to check that there are no unread data in the receive
buffer. Note that the TXCn Flag must be cleared before each transmission (before
UDRn is written) if it is used for this purpose.
The following simple USART initialization code examples show one assembly and one
C function that are equal in functionality. The examples assume polling (no interrupts
enabled). The baud rate is given as a function parameter. For the assembly code, thebaud rate parameter is assumed to be stored in the r17:r16 registers.

370

ATmega128RFA1
8266A-MCU Wireless-12/09

ATmega128RFA1Assembly Code Example
USART_Init:(1)

clr r18
out UBRRnH,r18
out UBRRnL,r18; Setting the XCKn port pin as output, enables master mode.
sbi XCKn_DDR, XCKn
; Set MSPI mode of operation and SPI data mode 0.
ldi r18, (1<<UMSELn1)|(1<<UMSELn0)|(0<<UCPHAn)|(0<<UCPOLn)
out UCSRnC,r18; Enable receiver and transmitter.
ldi r18, (1<<RXENn)|(1<<TXENn)
out UCSRnB,r18 ; Set baud rate.
; IMPORTANT:; The Baud Rate must be set after the transmitter is enabled!
out UBRRnH, r17
out UBRRnL, r18
ret(1)

C Code Example
void USART_Init( unsigned int baud ){UBRRn = 0;/* Setting the XCKn port pin as output, enables master mode. */XCKn_DDR |= (1<<XCKn);/* Set MSPI mode of operation and SPI data mode 0. */UCSRnC = (1<<UMSELn1)|(1<<UMSELn0)|(0<<UCPHAn)|(0<<UCPOLn);/* Enable receiver and transmitter. */UCSRnB = (1<<RXENn)|(1<<TXENn);/* Set baud rate. *//* IMPORTANT:*//* The Baud Rate must be set after the transmitter is enabled */UBRRn = baud;}
Note:

1. See "About Code Examples" on page 7

24.5 Data Transfer
Using the USART in MSPI mode requires the Transmitter to be enabled, i.e. the TXENn
bit in the UCSRnB register is set to one. When the Transmitter is enabled, the normal
port operation of the TxDn pin is overridden and given the function as the Transmitter's
serial output. Enabling the receiver is optional and is done by setting the RXENn bit in
the UCSRnB register to one. When the receiver is enabled, the normal pin operation of
the RxDn pin is overridden and given the function as the Receiver's serial input. The
XCKn will in both cases be used as the transfer clock.
After initialization the USART is ready for doing data transfers. A data transfer is
initiated by writing to the UDRn I/O location. This is the case for both sending andreceiving data since the transmitter controls the transfer clock. The data written to371
8266A-MCU Wireless-12/09

UDRn is moved from the transmit buffer to the shift register when the shift register isready to send a new frame.
Note:

To keep the input buffer in sync with the number of data bytes transmitted, theUDRn register must be read once for each byte transmitted. The input buffer
operation is identical to normal USART mode, i.e. if an overflow occurs thecharacter last received will be lost, not the first data in the buffer. This meansthat if four bytes are transferred, byte 1 first, then byte 2, 3, and 4, and the
UDRn is not read before all transfers are completed, then byte 3 to be received
will be lost, and not byte 1.

The following code examples show a simple USART in MSPIM mode transfer function
based on polling of the Data Register Empty (UDREn) Flag and the Receive Complete(RXCn) Flag. The USART has to be initialized before the function can be used. For theassembly code, the data to be sent is assumed to be stored in Register r16 and thedata received will be available in the same register (r16) after the function returns.
The function simply waits for the transmit buffer to be empty by checking the UDREn
Flag, before loading it with new data to be transmitted. The function then waits for data
to be present in the receive buffer by checking the RXCn Flag, before reading the buffer
and returning the value.
(1)

Assembly Code Example
USART_MSPIM_Transfer:; Wait for empty transmit buffer
sbis UCSRnA, UDREn
rjmp USART_MSPIM_Transfer; Put data (r16) into buffer, sends the dataout UDRn,r16; Wait for data to be received
USART_MSPIM_Wait_RXCn:sbis UCSRnA, RXCn
rjmp USART_MSPIM_Wait_RXCn; Get and return received data from bufferin r16, UDRn
ret
(1)

C Code Example
unsigned char USART_Receive( void ){/* Wait for empty transmit buffer */while ( !( UCSRnA & (1<<UDREn)) );/* Put data into buffer, sends the data */UDRn = data;/* Wait for data to be received */while ( !(UCSRnA & (1<<RXCn)) );/* Get and return received data from buffer */return UDRn;}
Notes:

372

1. See "About Code Examples" on page 7

ATmega128RFA1
8266A-MCU Wireless-12/09

ATmega128RFA1
24.5.1 Transmitter and Receiver Flags and Interrupts
The RXCn, TXCn, and UDREn flags and corresponding interrupts in USART in MSPIM
mode are identical in function to the normal USART operation. However, the receiver
error status flags (FE, DOR, and PE) are not in use and are always read as zero.
24.5.2 Disabling the Transmitter or Receiver
The disabling of the transmitter or receiver in USART in MSPIM mode is identical infunction to the normal USART operation.

24.6 USART MSPIM Register Description
The following section describes the registers used for SPI operation using the USART.
24.6.1 UDRn – USART MSPIM I/O Data Register
The function and bit description of the USART data register (UDRn) in MSPI mode is
identical to normal USART operation. See "UDR0 – USART0 I/O Data Register" on
page 356.
24.6.2 UBRRnL and UBRRnH – USART MSPIM Baud Rate Registers
The function and bit description of the baud rate registers in MSPI mode is identical tonormal USART operation. See "UBRR0L – USART0 Baud Rate Register Low Byte" onpage 360 and "UBRR0H – USART0 Baud Rate Register High Byte" on page 360.
Table 24–3. Comparison of USART in MSPIM mode and SPI pins
USART_MSPIM

SPIComment

TxDn

MOSI

Master Out only

RxDn

MISO

Master In only

XCKn

SCK

(Functional identical)

(N/A)

SS
¯¯

Not supported by USART in MSPIM

24.6.3 UCSR0A – USART0 MSPIM Control and Status Register A
Bit

7

6

5

NA ($C0)

RXC0

TXC0

UDRE0

Read/Write
Initial Value

R
0

RW
0

R
0

4

3

2

1

0

UCSR0A• Bit 7 – RXC0 - USART Receive Complete
This flag bit is set when there are unread data in the receive buffer and cleared when
the receive buffer is empty (i.e., does not contain any unread data). If the Receiver isdisabled, the receive buffer will be flushed and consequently the RXC0 bit will become
zero. The RXC0 Flag can be used to generate a Receive Complete interrupt (seedescription of the RXCIE0 bit).
• Bit 6 – TXC0 - USART Transmit Complete
This flag bit is set when the entire frame in the Transmit Shift Register has been shiftedout and there are no new data currently present in the transmit buffer (UDR0). The
TXC0 Flag bit is automatically cleared when a transmit complete interrupt is executed,
or it can be cleared by writing a one to its bit location. The TXC0 Flag can generate aTransmit Complete interrupt (see description of the TXCIE0 bit).
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• Bit 5 – UDRE0 - USART Data Register Empty
The UDRE0 Flag indicates if the transmit buffer (UDR0) is ready to receive new data. If
UDRE0 is one, the buffer is empty, and therefore ready to be written. The UDRE0 Flag
can generate a Data Register Empty interrupt (see description of the UDRIE0 bit).
UDRE0 is set after a reset to indicate that the Transmitter is ready.

24.6.4 UCSR0B – USART0 MSPIM Control and Status Register B
Bit

7

6

5

4

3

NA ($C1)RXCIE0TXCIE0

UDRIE0

RXEN0

TXEN0

Read/Write
Initial Value

RW
0

RW
0

RW
1

RW
0

RW
0

2

1

0

UCSR0B• Bit 7 – RXCIE0 - RX Complete Interrupt Enable
Writing this bit to one enables interrupt on the RXC0 Flag. A USART Receive Complete
interrupt will be generated only if the RXCIE0 bit is written to one, the Global Interrupt
Flag in SREG is written to one and the RXC0 bit in UCSR0A is set.
• Bit 6 – TXCIE0 - TX Complete Interrupt Enable
Writing this bit to one enables interrupt on the TXC0 Flag. A USART Transmit Complete
interrupt will be generated only if the TXCIE0 bit is written to one, the Global Interrupt
Flag in SREG is written to one and the TXC0 bit in UCSR0A is set.
• Bit 5 – UDRIE0 - USART Data Register Empty Interrupt Enable
Writing this bit to one enables interrupt on the UDRE0 Flag. A Data Register Emptyinterrupt will be generated only if the UDRIE0 bit is written to one, the Global Interrupt
Flag in SREG is written to one and the UDRE0 bit in UCSR0A is set.
• Bit 4 – RXEN0 - Receiver Enable
Writing this bit to one enables the USART Receiver in MSPIM mode. The Receiver will
override normal port operation for the RxD0 pin when enabled. Disabling the Receiverwill flush the receive buffer. Only enabling the receiver in MSPI mode (i.e. setting
RXEN0=1 and TXEN0=0) has no meaning since it is the transmitter that controls thetransfer clock and since only master mode is supported.
• Bit 3 – TXEN0 - Transmitter Enable
Writing this bit to one enables the USART Transmitter. The Transmitter will override
normal port operation for the TxD0 pin when enabled. The disabling of the Transmitter(writing TXEN0 to zero) will not become effective until ongoing and pendingtransmissions are completed, i.e., when the Transmit Shift Register and Transmit Buffer
Register do not contain data to be transmitted. When disabled, the Transmitter will nolonger override the TxD0 port.

24.6.5 UCSR0C – USART0 MSPIM Control and Status Register C
Bit

7

6

5

NA ($C2)
Read/Write
Initial Value

4

3

2

1

0

UDORD0 UCPHA0 UCPOL0
RW
1

RW
1

UCSR0CRW
0• Bit 2 – UDORD0 - Data Order
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ATmega128RFA1When set to one the LSB of the data word is transmitted first. When set to zero the
MSB of the data word is transmitted first. Refer to section "Frame Formats" for details.
• Bit 1 – UCPHA0 - Clock Phase
The UCPHA0 bit setting determines if data is sampled on the leading (first) or tailing(last) edge of XCK0. Refer to the section "SPI Data Modes and Timing" for details.
• Bit 0 – UCPOL0 - Clock Polarity
The UCPOL0 bit sets the polarity of the XCK0 clock. The combination of the UCPOL0and UCPHA0 bit settings determine the timing of the data transfer. Refer to the section"SPI Data Modes and Timing" for details.

24.6.6 UCSR1A – USART1 MSPIM Control and Status Register A
Bit

7

6

5

NA ($C8)

RXC1

TXC1

UDRE1

Read/Write
Initial Value

R
0

RW
0

R
0

4

3

2

1

0

UCSR1A• Bit 7 – RXC1 - USART Receive Complete
This flag bit is set when there are unread data in the receive buffer and cleared when
the receive buffer is empty (i.e., does not contain any unread data). If the Receiver isdisabled, the receive buffer will be flushed and consequently the RXC1 bit will become
zero. The RXC1 Flag can be used to generate a Receive Complete interrupt (seedescription of the RXCIE1 bit).
• Bit 6 – TXC1 - USART Transmit Complete
This flag bit is set when the entire frame in the Transmit Shift Register has been shiftedout and there are no new data currently present in the transmit buffer (UDR1). The
TXC1 Flag bit is automatically cleared when a transmit complete interrupt is executed,
or it can be cleared by writing a one to its bit location. The TXC1 Flag can generate aTransmit Complete interrupt (see description of the TXCIE1 bit).
• Bit 5 – UDRE1 - USART Data Register Empty
The UDRE1 Flag indicates if the transmit buffer (UDR1) is ready to receive new data. If
UDRE1 is one, the buffer is empty, and therefore ready to be written. The UDRE1 Flag
can generate a Data Register Empty interrupt (see description of the UDRIE1 bit).
UDRE1 is set after a reset to indicate that the Transmitter is ready.

24.6.7 UCSR1B – USART1 MSPIM Control and Status Register B
Bit

7

6

5

4

3

NA ($C9)RXCIE1TXCIE1

UDRIE1

RXEN1

TXEN1

Read/Write
Initial Value

RW
0

RW
0

RW
1

RW
0

RW
0

2

1

0

UCSR1B• Bit 7 – RXCIE1 - RX Complete Interrupt Enable
Writing this bit to one enables interrupt on the RXC1 Flag. A USART Receive Complete
interrupt will be generated only if the RXCIE1 bit is written to one, the Global Interrupt
Flag in SREG is written to one and the RXC1 bit in UCSR1A is set.

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• Bit 6 – TXCIE1 - TX Complete Interrupt Enable
Writing this bit to one enables interrupt on the TXC1 Flag. A USART Transmit Complete
interrupt will be generated only if the TXCIE1 bit is written to one, the Global Interrupt
Flag in SREG is written to one and the TXC1 bit in UCSR1A is set.
• Bit 5 – UDRIE1 - USART Data Register Empty Interrupt Enable
Writing this bit to one enables interrupt on the UDRE1 Flag. A Data Register Emptyinterrupt will be generated only if the UDRIE1 bit is written to one, the Global Interrupt
Flag in SREG is written to one and the UDRE1 bit in UCSR1A is set.
• Bit 4 – RXEN1 - Receiver Enable
Writing this bit to one enables the USART Receiver in MSPIM mode. The Receiver will
override normal port operation for the RxD1 pin when enabled. Disabling the Receiverwill flush the receive buffer. Only enabling the receiver in MSPI mode (i.e. setting
RXEN1=1 and TXEN1=0) has no meaning since it is the transmitter that controls thetransfer clock and since only master mode is supported.
• Bit 3 – TXEN1 - Transmitter Enable
Writing this bit to one enables the USART Transmitter. The Transmitter will override
normal port operation for the TxD1 pin when enabled. The disabling of the Transmitter(writing TXEN1 to zero) will not become effective until ongoing and pendingtransmissions are completed, i.e., when the Transmit Shift Register and Transmit Buffer
Register do not contain data to be transmitted. When disabled, the Transmitter will nolonger override the TxD1 port.

24.6.8 UCSR1C – USART1 MSPIM Control and Status Register C
Bit

7

6

5

NA ($CA)
Read/Write
Initial Value

4

3

2

1

0

UDORD1 UCPHA1 UCPOL1
RW
1

RW
1

UCSR1CRW
0• Bit 2 – UDORD1 - Data Order
When set to one the LSB of the data word is transmitted first. When set to zero the
MSB of the data word is transmitted first. Refer to section "Frame Formats" for details.
• Bit 1 – UCPHA1 - Clock Phase
The UCPHA1 bit setting determines if data is sampled on the leading (first) or tailing(last) edge of XCK1. Refer to the section "SPI Data Modes and Timing" for details.
• Bit 0 – UCPOL1 - Clock Polarity
The UCPOL1 bit sets the polarity of the XCK1 clock. The combination of the UCPOL1and UCPHA1 bit settings determine the timing of the data transfer. Refer to the section"SPI Data Modes and Timing" for details.

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ATmega128RFA1
25 2-wire Serial Interface
25.1 Features• Simple yet powerful and flexible communication interface, only two bus lines
needed• Both master and slave operation supported• Device can operate as transmitter or receiver• 7-bit address space allows up to 128 different slave addresses• Multi-master arbitration support• Up to 400 kHz data transfer speed• Slew-rate limited output drivers• Noise suppression circuitry rejects spikes on bus lines• Fully programmable slave address with general call support• Address recognition causes wake-up when microcontroller is in sleep mode

25.2 2-wire Serial Interface Bus Definition
The 2-wire Serial Interface (TWI) is ideally suited for typical microcontroller applications.
The TWI protocol allows the systems designer to interconnect up to 128 different
devices using only two bi-directional bus lines, one for clock (SCL) and one for data
(SDA). The only external hardware needed to implement the bus is a single pull-up
resistor for each of the TWI bus lines. All devices connected to the bus have individual
addresses, and mechanisms for resolving bus contention are inherent in the TWI
protocol.
Figure 25-1. TWI Bus Interconnection
DEVDD

Device 1

Device 2

Device 3........

Device n

R1

R2

SDA

SCL

25.2.1 TWI Terminology
The following definitions are frequently encountered in this section.
Table 25-1. TWI Terminology
Term

Description

Master

The device that initiates and terminates a transmission. The Master also
generates the SCL clock.

Slave

The device addressed by a Master.

Transmitter

The device placing data on the bus.

ReceiverThe device reading data from the bus.

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The Power Reduction TWI bit, PRTWI bit in "PRR0 – Power Reduction Register0" onpage 167 must be written to zero to enable the 2-wire Serial Interface.
25.2.2 Electrical Interconnection
As depicted in Figure 25-1 on page 377, both bus lines are connected to the positive
supply voltage through pull-up resistors. The bus drivers of all TWI-compliant devices
are open-drain or open-collector. This implements a wired-AND function which isessential to the operation of the interface. A low level on a TWI bus line is generated
when one or more TWI devices output a zero. A high level is output when all TWI
devices trim-state their outputs, allowing the pull-up resistors to pull the line high. Notethat all AVR devices connected to the TWI bus must be powered in order to allow any
bus operation.
The number of devices that can be connected to the bus is only limited by the bus
capacitance limit of 400 pF and the 7-bit slave address space. A detailed specificationof the electrical characteristics of the TWI is given in "2-wire Serial Interface
Characteristics" on page 503. Two different sets of specifications are presented there,
one relevant for bus speeds below 100 kHz, and one valid for bus speeds up to 400
kHz.

25.3 Data Transfer and Frame Format
25.3.1 Transferring Bits
Each data bit transferred on the TWI bus is accompanied by a pulse on the clock line.
The level of the data line must be stable when the clock line is high. The only exception
to this rule is for generating start and stop conditions.
Figure 25-2. Data Validity
SDA

SCL
Data Stable

Data Stable

Data Change

25.3.2 START and STOP Conditions
The Master initiates and terminates a data transmission. The transmission is initiatedwhen the Master issues a START condition on the bus, and it is terminated when the
Master issues a STOP condition. Between a START and a STOP condition, the bus isconsidered busy, and no other master should try to seize control of the bus. A special
case occurs when a new START condition is issued between a START and STOP
condition. This is referred to as a REPEATED START condition, and is used when the
Master wishes to initiate a new transfer without relinquishing control of the bus. After a
REPEATED START, the bus is considered busy until the next STOP. This is identical to
the START behavior, and therefore START is used to describe both START and
REPEATED START for the remainder of this datasheet, unless otherwise noted. As
depicted below, START and STOP conditions are signaled by changing the level of the
SDA line when the SCL line is high.

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ATmega128RFA1
Figure 25-3. START, REPEATED START and STOP conditions

SDA

SCL

START

STOP

REPEATED START

START

STOP

25.3.3 Address Packet Format
All address packets transmitted on the TWI bus are 9 bits long, consisting of 7 address
bits, one READ/WRITE control bit and an acknowledge bit. If the READ/WRITE bit isset, a read operation is to be performed, otherwise a write operation should be
performed. When a Slave recognizes that it is being addressed, it should acknowledge
by pulling SDA low in the ninth SCL (ACK) cycle. If the addressed Slave is busy, or forsome other reason can not service the Master’s request, the SDA line should be left
high in the ACK clock cycle. The Master can then transmit a STOP condition, or a
REPEATED START condition to initiate a new transmission. An address packet
consisting of a slave address and a READ or a WRITE bit is called SLA+R or SLA+W,
respectively.
The MSB of the address byte is transmitted first. Slave addresses can freely beallocated by the designer, but the address 0000 000 is reserved for a general call.
When a general call is issued, all slaves should respond by pulling the SDA line low in
the ACK cycle. A general call is used when a Master wishes to transmit the samemessage to several slaves in the system. When the general call address followed by a
Write bit is transmitted on the bus, all slaves set up to acknowledge the general call willpull the SDA line low in the ack cycle. The following data packets will then be received
by all the slaves that acknowledged the general call. Note that transmitting the generalcall address followed by a Read bit is meaningless, as this would cause contention if
several slaves started transmitting different data.
All addresses of the format 1111 xxx should be reserved for future purposes.
Figure 25-4. Address Packet Format
Addr MSB

Addr LSB

R/W

ACK

7

8

9

SDA

SCL
1

2

START

25.3.4 Data Packet Format
All data packets transmitted on the TWI bus are nine bits long, consisting of one databyte and an acknowledge bit. During a data transfer, the Master generates the clock
and the START and STOP conditions, while the Receiver is responsible for
acknowledging the reception. An Acknowledge (ACK) is signaled by the Receiver

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pulling the SDA line low during the ninth SCL cycle. If the Receiver leaves the SDA line
high, a NACK is signaled. When the Receiver has received the last byte, or for somereason cannot receive any more bytes, it should inform the Transmitter by sending a
NACK after the final byte. The MSB of the data byte is transmitted first.
Figure 25-5. Data Packet Format
Data MSB

Data LSB

ACK

8

9

Aggregate
SDA
SDA from
Transmitter
SDA from
Receiver
SCL from
Master
1

2

7

SLA+R/W

STOP, REPEATEDSTART or Next
Data Byte

Data Byte

25.3.5 Combining Address and Data Packets into a Transmission
A transmission basically consists of a START condition, a SLA+R/W, one or more data
packets and a STOP condition. An empty message, consisting of a START followed by
a STOP condition, is illegal. Note that the Wired-ANDing of the SCL line can be used to
implement handshaking between the Master and the Slave. The Slave can extend the
SCL low period by pulling the SCL line low. This is useful if the clock speed set up by
the Master is too fast for the Slave, or the Slave needs extra time for processing
between the data transmissions. The Slave extending the SCL low period will not affect
the SCL high period, which is determined by the Master. As a consequence, the Slave
can reduce the TWI data transfer speed by prolonging the SCL duty cycle.
Figure 25-6 below shows a typical data transmission. Note that several data bytes canbe transmitted between the SLA+R/W and the STOP condition, depending on thesoftware protocol implemented by the application software.
Figure 25-6. Typical Data Transmission
Addr MSB

Addr LSB

R/W

ACK

Data MSB

7

8

9

1

Data LSB

ACK

8

9

SDA

SCL
1
START

2

SLA+R/W

2

7
Data Byte

STOP

25.4 Multi-master Bus Systems, Arbitration and Synchronization
The TWI protocol allows bus systems with several masters. Special concerns havebeen taken in order to ensure that transmissions will proceed as normal, even if two or
more masters initiate a transmission at the same time. Two problems arise in multimaster systems:

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ATmega128RFA1• An algorithm must be implemented allowing only one of the masters to complete thetransmission. All other masters should cease transmission when they discover thatthey have lost the selection process. This selection process is called arbitration.
When a contending master discovers that it has lost the arbitration process, it should
immediately switch to Slave mode to check whether it is being addressed by thewinning master. The fact that multiple masters have started transmission at thesame time should not be detectable to the slaves, i.e. the data being transferred on
the bus must not be corrupted.
• Different masters may use different SCL frequencies. A scheme must be devised tosynchronize the serial clocks from all masters, in order to let the transmission
proceed in a lockstep fashion. This will facilitate the arbitration process.
The wired-ANDing of the bus lines is used to solve both these problems. The serial
clocks from all masters will be wired-ANDed, yielding a combined clock with a highperiod equal to the one from the Master with the shortest high period. The low period of
the combined clock is equal to the low period of the Master with the longest low period.
Note that all masters listen to the SCL line, effectively starting to count their SCL highand low time-out periods when the combined SCL line goes high or low, respectively.
Figure 25-7. SCL Synchronization Between Multiple Masters
TA low

TA high

SCL from
Master A

SCL from
Master B

SCL Bus
Line
TBlow
Masters Start
Counting Low Period

TBhighMasters Start
Counting High Period

Arbitration is carried out by all masters continuously monitoring the SDA line after
outputting data. If the value read from the SDA line does not match the value theMaster had output, it has lost the arbitration. Note that a Master can only lose arbitration
when it outputs a high SDA value while another Master outputs a low value. The losing
Master should immediately go to Slave mode, checking if it is being addressed by thewinning Master. The SDA line should be left high, but losing masters are allowed togenerate a clock signal until the end of the current data or address packet. Arbitration
will continue until only one Master remains, and this may take many bits. If several
masters are trying to address the same Slave, arbitration will continue into the data
packet.
Note that arbitration is not allowed between:• A REPEATED START condition and a data bit.
• A STOP condition and a data bit.
• A REPEATED START and a STOP condition.
It is the user software’s responsibility to ensure that these illegal arbitration conditions
never occur. This implies that in multi-master systems, all data transfers must use thesame composition of SLA+R/W and data packets. In other words: All transmissions

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must contain the same number of data packets, otherwise the result of the arbitration is
undefined.
Figure 25-8. Arbitration Between Two Masters
START

Master A Loses
Arbitration, SDAA SDA

SDA from
Master A

SDA from
Master B

SDA Line

Synchronized
SCL Line

25.5 Overview of the TWI Module
The TWI module is comprised of several sub-modules, as shown in Figure 25-9 below.
All registers drawn in a thick line are accessible through the AVR data bus.
Figure 25-9. Overview of the TWI Module

Slew-rate
Control

SDA

Spike
FilterSlew-rate
Control

Spike
FilterBus Interface Unit
START / STOP
Control

Spike Suppression

Arbitration detection

Address/Data Shift
Register (TWDR)

Address Match Unit
Address Register(TWAR)

Address Comparator

382

Bit Rate Generator
Prescaler

Bit Rate Register(TWBR)

Ack

Control Unit
Status Register(TWSR)

Control Register(TWCR)

State Machine andStatus control

TWI Unit

SCL

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ATmega128RFA1
25.5.1 SCL and SDA Pins
These pins interface the AVR TWI with the rest of the MCU system. The output drivers
contain a slew-rate limiter in order to conform to the TWI specification. The input stages
contain a spike suppression unit removing spikes shorter than 50 ns. Note that theinternal pull-ups in the AVR pads can be enabled by setting the PORT bits
corresponding to the SCL and SDA pins, as explained in the I/O Port section. Theinternal pull-ups can in some systems eliminate the need for external ones.
25.5.2 Bit Rate Generator Unit
This unit controls the period of SCL when operating in a Master mode. The SCL period
is controlled by settings in the TWI Bit Rate Register (TWBR) and the Prescaler bits in
the TWI Status Register (TWSR). Slave operation does not depend on Bit Rate or
Prescaler settings, but the CPU clock frequency in the Slave must be at least 16 times
higher than the SCL frequency. Note that slaves may prolong the SCL low period,
thereby reducing the average TWI bus clock period. The SCL frequency is generated
according to the following equation:

SCL frequency =CPU Clock frequency
16 + 2(TWBR ) ⋅ 4 TWPS• TWBR = Value of the TWI Bit Rate Register.
• TWPS = Value of the prescaler bits in the TWI Status Register.
Note that pull-up resistor values should be selected according to the SCL frequency
and the capacitive bus line load. See in "2-wire Serial Interface Characteristics" on page503 for value of pull-up resistor.
25.5.3 Bus Interface Unit
This unit contains the Data and Address Shift Register (TWDR), a START/STOP
Controller and Arbitration detection hardware. The TWDR contains the address or databytes to be transmitted, or the address or data bytes received. In addition to the 8-bit
TWDR, the Bus Interface Unit also contains a register containing the (N)ACK bit to betransmitted or received. This (N)ACK Register is not directly accessible by theapplication software. However, when receiving, it can be set or cleared by manipulating
the TWI Control Register (TWCR). When in Transmitter mode, the value of the received(N)ACK bit can be determined by the value in the TWSR.
The START/STOP Controller is responsible for generation and detection of START,REPEATED START, and STOP conditions. The START/STOP controller is able todetect START and STOP conditions even when the AVR MCU is in one of the sleep
modes, enabling the MCU to wake up if addressed by a Master.
If the TWI has initiated a transmission as Master, the Arbitration Detection hardware
continuously monitors the transmission trying to determine if arbitration is in process. If
the TWI has lost an arbitration, the Control Unit is informed. Correct action can then be
taken and appropriate status codes generated.
25.5.4 Address Match Unit
The Address Match unit checks if received address bytes match the seven-bit addressin the TWI Address Register (TWAR). If the TWI General Call Recognition Enable(TWGCE) bit in the TWAR is written to one, all incoming address bits will also becompared against the General Call address. Upon an address match, the Control Unit
is informed, allowing correct action to be taken. The TWI may or may not acknowledge
its address, depending on settings in the TWCR. The Address Match unit is able to383
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compare addresses even if the AVR MCU is in sleep mode, enabling the MCU to wakeup if addressed by a Master. If another interrupt (e.g., INT0) occurs during TWI Powerdown address match and wakes up the CPU, the TWI aborts operation and return to it’s
idle state. If this cause any problems, ensure that TWI Address Match is the only
enabled interrupt when entering Power-down.
25.5.5 Control Unit
The Control unit monitors the TWI bus and generates responses corresponding tosettings in the TWI Control Register (TWCR). When an event requiring the attention of
the application occurs on the TWI bus, the TWI Interrupt Flag (TWINT) is asserted. In
the next clock cycle, the TWI Status Register (TWSR) is updated with a status code
identifying the event. The TWSR only contains relevant status information when the
TWI Interrupt Flag is asserted. At all other times, the TWSR contains a special status
code indicating that no relevant status information is available. As long as the TWINT
Flag is set, the SCL line is held low. This allows the application software to complete its
tasks before allowing the TWI transmission to continue.
The TWINT Flag is set in the following situations:• After the TWI has transmitted a START/REPEATED START condition.
• After the TWI has transmitted SLA+R/W.
• After the TWI has transmitted an address byte.
• After the TWI has lost arbitration.
• After the TWI has been addressed by own slave address or general call.
• After the TWI has received a data byte.
• After a STOP or REPEATED START has been received while still addressed as a
Slave.
• When a bus error has occurred due to an illegal START or STOP condition.

25.6 Using the TWI
The ATmega128RFA1 TWI is byte-oriented and interrupt based. Interrupts are issued
after all bus events, like reception of a byte or transmission of a START condition.
Because the TWI is interrupt-based, the application software is free to carry on otheroperations during a TWI byte transfer. Note that the TWI Interrupt Enable (TWIE) bit in
TWCR together with the Global Interrupt Enable bit in SREG allow the application todecide whether or not assertion of the TWINT Flag should generate an interrupt
request. If the TWIE bit is cleared, the application must poll the TWINT Flag in order todetect actions on the TWI bus.
When the TWINT Flag is asserted, the TWI has finished an operation and awaits
application response. In this case, the TWI Status Register (TWSR) contains a value
indicating the current state of the TWI bus. The application software can then decide
how the TWI should behave in the next TWI bus cycle by manipulating the TWCR and
TWDR Registers.
Figure 25-10 on page 385 is a simple example of how the application can interface tothe TWI hardware. In this example, a Master wishes to transmit a single data byte to a
Slave. This description is quite abstract, a more detailed explanation follows later in thissection. A simple code example implementing the desired behavior is also presented.

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ATmega128RFA1

Application
ActionFigure 25-10. Interfacing the Application to the TWI in a Typical Transmission
1. Application
writes to TWCR toinitiatetransmission of
START

TWI
HardwareAction

TWI bus3. Check TWSR to see if START wassent. Application loads SLA+W into
TWDR, and loads appropriate control
signals into TWCR, makin sure thatTWINT is written to one,and TWSTA is written to zero.

START

2. TWINT set.
Status code indicates
START condition sent

SLA+W

5. Check TWSR to see if SLA+W was
sent and ACK received.
Application loads data into TWDR, andloads appropriate control signals into
TWCR, making sure that TWINT iswritten to one

A

4. TWINT set.
Status code indicates
SLA+W sent, ACK
received

Data

7. Check TWSR to see if data was sent
and ACK received.
Application loads appropriate control
signals to send STOP into TWCR,
making sure that TWINT is written to one

A

6. TWINT set.
Status code indicatesdata sent, ACK received

STOP

Indicates
TWINT set

1. The first step in a TWI transmission is to transmit a START condition. This is done bywriting a specific value into TWCR, instructing the TWI hardware to transmit a
START condition. Which value to write is described later on. However, it is importantthat the TWINT bit is set in the value written. Writing a one to TWINT clears the flag.
The TWI will not start any operation as long as the TWINT bit in TWCR is set.
Immediately after the application has cleared TWINT, the TWI will initiate
transmission of the START condition.
2. When the START condition has been transmitted, the TWINT Flag in TWCR is set,
and TWSR is updated with a status code indicating that the START condition has
successfully been sent.
3. The application software should now examine the value of TWSR, to make sure that
the START condition was successfully transmitted. If TWSR indicates otherwise, theapplication software might take some special action, like calling an error routine.
Assuming that the status code is as expected, the application must load SLA+W into
TWDR. Remember that TWDR is used both for address and data. After TWDR has
been loaded with the desired SLA+W, a specific value must be written to TWCR,
instructing the TWI hardware to transmit the SLA+W present in TWDR. Which value
to write is described later on. However, it is important that the TWINT bit is set in thevalue written. Writing a one to TWINT clears the flag. The TWI will not start any
operation as long as the TWINT bit in TWCR is set. Immediately after the application
has cleared TWINT, the TWI will initiate transmission of the address packet.
4. When the address packet has been transmitted, the TWINT Flag in TWCR is set,
and TWSR is updated with a status code indicating that the address packet has
successfully been sent. The status code will also reflect whether a Slave
acknowledged the packet or not.
5. The application software should now examine the value of TWSR, to make sure thatthe address packet was successfully transmitted, and that the value of the ACK bit
was as expected. If TWSR indicates otherwise, the application software might takesome special action, like calling an error routine. Assuming that the status code is as
expected, the application must load a data packet into TWDR. Subsequently, a
specific value must be written to TWCR, instructing the TWI hardware to transmit thedata packet present in TWDR. Which value to write is described later on. However, it
is important that the TWINT bit is set in the value written. Writing a one to TWINT

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clears the flag. The TWI will not start any operation as long as the TWINT bit in
TWCR is set. Immediately after the application has cleared TWINT, the TWI will
initiate transmission of the data packet.
6. When the data packet has been transmitted, the TWINT Flag in TWCR is set, and
TWSR is updated with a status code indicating that the data packet has successfully
been sent. The status code will also reflect whether a Slave acknowledged thepacket or not.
7. The application software should now examine the value of TWSR, to make sure thatthe data packet was successfully transmitted, and that the value of the ACK bit was
as expected. If TWSR indicates otherwise, the application software might take somespecial action, like calling an error routine. Assuming that the status code is as
expected, the application must write a specific value to TWCR, instructing the TWI
hardware to transmit a STOP condition. Which value to write is described later on.
However, it is important that the TWINT bit is set in the value written. Writing a one
to TWINT clears the flag. The TWI will not start any operation as long as the TWINT
bit in TWCR is set. Immediately after the application has cleared TWINT, the TWI
will initiate transmission of the STOP condition. Note that TWINT is NOT set after a
STOP condition has been sent.
Even though this example is simple, it shows the principles involved in all TWI
transmissions. These can be summarized as follows:• When the TWI has finished an operation and expects application response, theTWINT Flag is set. The SCL line is pulled low until TWINT is cleared.
• When the TWINT Flag is set, the user must update all TWI Registers with the value
relevant for the next TWI bus cycle. As an example, TWDR must be loaded with thevalue to be transmitted in the next bus cycle.
• After all TWI Register updates and other pending application software tasks havebeen completed, TWCR is written. When writing TWCR, the TWINT bit should be
set. Writing a one to TWINT clears the flag. The TWI will then commence executing
whatever operation was specified by the TWCR setting.
In the following an assembly and C implementation of the example is given. Note thatthe code below assumes that several definitions have been made, for example by using
include-files.
Table 25-2. Code example
1

Assembly Code Example

C Example

Comments

ldi
r16,(1<<TWINT)|(1<<TWSTA)|TWCR = (1<<TWINT)|(1<<TWSTA)|

Send START condition(1<<TWEN)(1<<TWEN)
out TWCR, r162

wait1:

while (!(TWCR & (1<<TWINT)));

Wait for TWINT Flag set. This
indicates that the START condition
has been transmittedif ((TWSR & 0xF8) != START)Check value of TWI Status Register.
Mask prescaler bits. If status different
from START go to ERROR

in r16,TWCR
sbrs r16,TWINT
rjmp wait1
3

in r16,TWSR
andi r16, 0xF8

ERROR();

cpi r16, START
brne ERROR
ldi r16, SLA_W

TWDR = SLA_W;

out TWDR, r16

TWCR = (1<<TWINT)|(1<<TWEN);

ldi r16, (1<<TWINT)|(1<<TWEN)

Load SLA_W into TWDR Register.
Clear TWINT bit in TWCR to starttransmission of address

out TWCR, r16386

ATmega128RFA1
8266A-MCU Wireless-12/09

ATmega128RFA1
4Assembly Code Example

C Example

Comments

wait2:

while (!(TWCR & (1<<TWINT)));

Wait for TWINT Flag set. This
indicates that the SLA+W has beentransmitted, and ACK/NACK has
been received.

if ((TWSR & 0xF8) != MT_SLA_ACK)Check value of TWI Status Register.
Mask prescaler bits. If status different
from MT_SLA_ACK go to ERROR

in r16,TWCR
sbrs r16,TWINT
rjmp wait2
5

in r16,TWSR
andi r16, 0xF8

ERROR();

cpi r16, MT_SLA_ACK
brne ERROR
ldi r16, DATATWDR = DATA;

out TWDR, r16

TWCR = (1<<TWINT) | (1<<TWEN);

ldi r16, (1<<TWINT)|(1<<TWEN)

Load DATA into TWDR Register.
Clear TWINT bit in TWCR to starttransmission of dataout TWCR, r16
6

wait3:

while (!(TWCR & (1<<TWINT)));

Wait for TWINT Flag set. This
indicates that the DATA has beentransmitted, and ACK/NACK has
been received.

if ((TWSR & 0xF8) != MT_DATA_ACK)Check value of TWI Status Register.
Mask prescaler bits. If status different
from MT_DATA_ACK go to ERROR

in r16,TWCR
sbrs r16,TWINT
rjmp wait3
7

in r16,TWSR
andi r16, 0xF8

ERROR();

cpi r16, MT_DATA_ACK
brne ERROR
ldi r16,(1<<TWINT)|(1<<TWEN)|(1<<TWSTO)TWCR = (1<<TWINT)|(1<<TWEN)|(1<<TWSTO);

Transmit STOP condition

out TWCR, r1625.7 Transmission Modes
The TWI can operate in one of four major modes. These are named Master Transmitter(MT), Master Receiver (MR), Slave Transmitter (ST) and Slave Receiver (SR). Severalof these modes can be used in the same application. As an example, the TWI can use
MT mode to write data into a TWI EEPROM, MR mode to read the data back from the
EEPROM. If other masters are present in the system, some of these might transmit
data to the TWI, and then SR mode would be used. It is the application software that
decides which modes are legal.
The following sections describe each of these modes. Possible status codes aredescribed along with figures detailing data transmission in each of the modes. Thesefigures contain the following abbreviations:
S:
R:
Data:
SLA:
_
A:

START conditionRs:
REPEATED START condition
Read bit (high level at SDA)W:
Write bit (low level at SDA)
8-bit data byte
P:
STOP condition
Slave AddressA:
Acknowledge bit (low level at SDA)
Not acknowledge bit (high level at SDA)In Figure 25-12 on page 389 to Figure 25-18 on page 399 circles are used to indicatethat the TWINT Flag is set. The numbers in the circles show the status code held in
TWSR, with the prescaler bits masked to zero. At these points, actions must be takenby the application to continue or complete the TWI transfer. The TWI transfer issuspended until the TWINT Flag is cleared by software.
When the TWINT Flag is set, the status code in TWSR is used to determine theappropriate software action. For each status code, the required software action and

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details of the following serial transfer are given in Table 25-3 on page 390 to Table 25-6
on page 398. Note that the prescaler bits are masked to zero in these tables.
25.7.1 Master Transmitter ModeIn the Master Transmitter mode, a number of data bytes are transmitted to a Slave
Receiver (see Figure 25-11 below). In order to enter a Master mode, a START
condition must be transmitted. The format of the following address packet determines
whether Master Transmitter or Master Receiver mode is to be entered. If SLA+W istransmitted, MT mode is entered, if SLA+R is transmitted, MR mode is entered. All
status codes mentioned in this section assume that the prescaler bits are zero or aremasked to zero.
Figure 25-11. Data Transfer in Master Transmitter Mode
DEVDD

Device 1

Device 2

MASTER
TRANSMITTERSLAVERECEIVER

Device 3........

Device n

R1

R2

SDA

SCL

A START condition is sent by writing the following value to TWCR:
TWCR

TWINT

TWEA

TWSTA

TWSTO

TWWC

TWEN

–

TWIE

Value

1

X

1

0

X

1

0

X

TWEN must be set to enable the 2-wire Serial Interface, TWSTA must be written to one
to transmit a START condition and TWINT must be written to one to clear the TWINT
Flag. The TWI will then test the 2-wire Serial Bus and generate a START condition assoon as the bus becomes free. After a START condition has been transmitted, theTWINT Flag is set by hardware, and the status code in TWSR will be 0x08 (see Table
25-3 on page 390). In order to enter MT mode, SLA+W must be transmitted. This isdone by writing SLA+W to TWDR. Thereafter the TWINT bit should be cleared (bywriting it to one) to continue the transfer. This is accomplished by writing the following
value to TWCR:
TWCR

TWINT

TWEA

TWSTA

TWSTO

TWWC

TWEN

–

TWIE

Value

1

X

0

0

X

1

0

X

When SLA+W have been transmitted and an acknowledgement bit has been received,
TWINT is set again and a number of status codes in TWSR are possible. Possible
status codes in Master mode are 0x18, 0x20, or 0x38. The appropriate action to betaken for each of these status codes is detailed in Table 25-3 on page 390.
When SLA+W has been successfully transmitted, a data packet should be transmitted.
This is done by writing the data byte to TWDR. TWDR must only be written when
TWINT is high. If not, the access will be discarded, and the Write Collision bit (TWWC)
will be set in the TWCR Register. After updating TWDR, the TWINT bit should becleared (by writing it to one) to continue the transfer. This is accomplished by writing thefollowing value to TWCR:

388

ATmega128RFA1
8266A-MCU Wireless-12/09

ATmega128RFA1
TWCR

TWINT

TWEA

TWSTA

TWSTO

TWWC

TWEN

–

TWIE

Value

1

X

0

0

X

1

0

X

This scheme is repeated until the last byte has been sent and the transfer is ended bygenerating a STOP condition or a repeated START condition. A STOP condition is
generated by writing the following value to TWCR:
TWCR

TWINT

TWEA

TWSTA

TWSTO

TWWC

TWEN

–

TWIE

Value

1

X

0

1

X

1

0

X

A REPEATED START condition is generated by writing the following value to TWCR:
TWCR

TWINT

TWEA

TWSTA

TWSTO

TWWC

TWEN

–

Value

X

1

0

X

1

0

X

TWIE

After a REPEATED START condition (state 0x10) the 2-wire Serial Interface canaccess the same Slave again, or a new Slave without transmitting a STOP condition.
Repeated START enables the Master to switch between Slaves, Master Transmittermode and Master Receiver mode without losing control of the bus.
Figure 25-12. Formats and States in the Master Transmitter ModeMT

Successfulltransmission
to a slave
receiver

S

SLA

$08

W

A

DATA

$18

A

P

$28

Next transfer
started with arepeated start
condition

RS

SLA

W

$10
Not acknowledge
received after theslave address

A

R

P

$20
MR

Not acknowledge
received after a data
byte

A

P

$30
Arbitration lost in slave
address or data byte

A or A

Other master
continues$38
Arbitration lost andaddressed as slave

A$68

From master to slave

From slave to masterA or A

Other master
continues$38
Other master
continues

$78

DATA

To corresponding
states in slave mode

$B0

A

n

Any number of data bytes
and their associated acknowledge bits
This number (contained in TWSR) corresponds
to a defined state of the Two-Wire Serial Bus. The
prescaler bits are zero or masked to zero

389
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Table 25-3. Status codes for Master Transmitter Mode
Status Code(TWSR)
Prescaler
Bits are 0

Status of the 2-wire
Serial Bus and 2-wire
Serial Interface
Hardware

0x08

A START condition has
been transmitted
A repeated START
condition has beentransmitted
SLA+W has beentransmitted; ACK has
been received

0x10

0x18

0x20

0x28

0x30

0x38

SLA+W has beentransmitted; NOT ACK
has been received

Data byte has beentransmitted; ACK has
been received

Data byte has beentransmitted; NOT ACK
has been received

Arbitration lost in SLA+W
or data bytes

Application Software Response
To TWCR
STA

STO

TWINT

TWEA

Load SLA+W

0

0

1

X

Load SLA+W or

0

0

1

X

Load SLA+R

0

0

1

X

Load data byte o

0

0

1

X

No TWDR action or

1

0

1

X

No TWDR action or

0

1

1

X

No TWDR action

1

1

1

X

Load data byte or

0

0

1

X

No TWDR action or

1

0

1

X

No TWDR action or

0

1

1

X

No TWDR action

1

1

1

X

Load data byte or

0

0

1

X

No TWDR action or

1

0

1

X

No TWDR action or

0

1

1

X

No TWDR action

1

1

1

X

Load data byte or

0

0

1

X

No TWDR action or

1

0

1

X

No TWDR action or

0

1

1

X

No TWDR action

1

1

1

X

No TWDR action or

0

0

1

X

No TWDR action

1

0

1

X

To/from TWDR

Next Action Taken by TWI
Hardware
SLA+W will be transmitted; ACK orNOT ACK will be received
SLA+W will be transmitted; ACK orNOT ACK will be received
SLA+R will be transmitted; Logic willswitch to Master Receiver mode
Data byte will be transmitted and
ACK or NOT ACK will be received
Repeated START will be transmitted
STOP condition will be transmitted
and TWSTO Flag will be reset
STOP condition followed by a START
condition will be transmitted andTWSTO Flag will be reset
Data byte will be transmitted and
ACK or NOT ACK will be received
Repeated START will be transmitted
STOP condition will be transmitted
and TWSTO Flag will be rese
STOP condition followed by a START
condition will be transmitted andTWSTO Flag will be reset
Data byte will be transmitted and
ACK or NOT ACK will be received
Repeated START will be transmitted
STOP condition will be transmitted
and TWSTO Flag will be reset
STOP condition followed by a START
condition will be transmitted andTWSTO Flag will be reset
Data byte will be transmitted and
ACK or NOT ACK will be received
Repeated START will be transmitted
STOP condition will be transmitted
and TWSTO Flag will be reset
STOP condition followed by a START
condition will be transmitted andTWSTO Flag will be reset
2-wire Serial Bus will be released andnot addressed Slave mode entered
A START condition will betransmitted when the bus be-comesfree

25.7.2 Master Receiver ModeIn the Master Receiver mode, a number of data bytes are received from a Slave
Transmitter (for Slave see Figure 25-13 on page 391). In order to enter a Master mode,a START condition must be transmitted. The format of the following address packet
determines whether Master Transmitter or Master Receiver mode is to be entered. If
SLA+W is transmitted, MT mode is entered, if SLA+R is transmitted, MR mode isentered. All the status codes mentioned in this section assume that the prescaler bits
are zero or are masked to zero.

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ATmega128RFA1
Figure 25-13. Data Transfer in Master Receiver Mode
DEVDD

Device 1

Device 2

MASTERRECEIVERSLAVE
TRANSMITTER

Device 3........

Device n

R1

R2

SDA

SCL

A START condition is sent by writing the following value to TWCR:
TWCR

TWINT

TWEA

TWSTA

TWSTO

TWWC

TWEN

–

TWIE

Value

1

X

1

0

X

1

0

X

TWEN must be written to one to enable the 2-wire Serial Interface, TWSTA must be
written to one to transmit a START condition and TWINT must be set to clear the
TWINT Flag. The TWI will then test the 2-wire Serial Bus and generate a START
condition as soon as the bus becomes free. After a START condition has beentransmitted, the TWINT Flag is set by hardware, and the status code in TWSR will be
0x08 (see Table 25-4 on page 392). In order to enter MR mode, SLA+R must betransmitted. This is done by writing SLA+R to TWDR. Thereafter the TWINT bit should
be cleared (by writing it to one) to continue the transfer. This is accomplished by writing
the following value to TWCR:
TWCR

TWINT

TWEA

TWSTA

TWSTO

TWWC

TWEN

–

TWIE

Value

1

X

0

0

X

1

0

X

When SLA+R have been transmitted and an acknowledgement bit has been received,
TWINT is set again and a number of status codes in TWSR are possible. Possible
status codes in Master mode are 0x38, 0x40, or 0x48. The appropriate action to betaken for each of these status codes is detailed in Table 25-4 on page 392. Received
data can be read from the TWDR Register when the TWINT Flag is set high by
hardware. This scheme is repeated until the last byte has been received. After the lastbyte has been received, the MR should inform the ST by sending a NACK after the lastreceived data byte. The transfer is ended by generating a STOP condition or a repeated
START condition. A STOP condition is generated by writing the following value to
TWCR:
TWCR

TWINT

TWEA

TWSTA

TWSTO

TWWC

TWEN

–

TWIE

value

1

X

0

1

X

1

0

X

A REPEATED START condition is generated by writing the following value to TWCR:
TWCR

TWINT

TWEA

TWSTA

TWSTO

TWWC

TWEN

–

TWIE

Value

1

X

1

0

X

1

0

X

After a repeated START condition (state 0x10) the 2-wire Serial Interface can accessthe same Slave again, or a new Slave without transmitting a STOP condition. Repeated391
8266A-MCU Wireless-12/09

START enables the Master to switch between Slaves, Master Transmitter mode andMaster Receiver mode without losing control over the bus.
Table 25-4. Status codes for Master Receiver Mode
Status Code(TWSR)
Prescaler
Bits are 0

Status of the 2-wire
Serial Bus and 2-wire
Serial Interface Hardware

0x08

A START condition has
been transmitted
A repeated START
condition has beentransmitted
Arbitration lost in SLA+R
or NOT ACK bit

0x10

0x38

0x40

0x48

0x50

0x58

392

Application Software Response
To TWCR
To/from TWDR

STA

STD

TWINT

TWEA

Load SLA+R

0

0

1

X

Load SLA+R or

0

0

1

X

Load SLA+W

0

0

1

X

No TWDR action or

0

0

1

X

No TWDR action

1

0

1

X

SLA+R has beentransmitted; ACK has
been received

No TWDR action or

0

0

1

0

No TWDR action

0

0

1

1

SLA+R has beentransmitted; NOT ACK
has been received

No TWDR action or

1

0

1

X

No TWDR action or

0

1

1

X

No TWDR action

1

1

1

X

Data byte has been
received; ACK has beenreturned

Read data byte or

0

0

1

0

Read data byte

0

0

1

1

Data byte has been
received; NOT ACK has
been returned

Read data byte or

1

0

1

X

Read data byte or

0

1

1

X

Read data byte

1

1

1

X

Next Action Taken by TWI
Hardware
SLA+R will be transmitted ACK orNOT ACK will be received
SLA+R will be transmitted ACK orNOTACK will be received
SLA+W will be transmitted Logic willswitch to Master Transmitter mode
2-wire Serial Bus will be released
and not addressed Slave mode will
be entered
A START condition will betransmitted when the bus becomes
free
Data byte will be received and NOT
ACK will be returned
Data byte will be received and ACK
will be returned
Repeated START will be transmitted
STOP condition will be transmitted
and TWSTO Flag will be reset
STOP condition followed by a
START condition will be transmitted
and TWSTO Flag will be reset
Data byte will be received and NOT
ACK will be returned
Data byte will be received and ACK
will be returned
Repeated START will be transmitted
STOP condition will be transmitted
and TWSTO Flag will be reset
STOP condition followed by a
START condition will be transmitted
and TWSTO Flag will be reset

ATmega128RFA1
8266A-MCU Wireless-12/09

ATmega128RFA1
Figure 25-14. Formats and States in the Master Receiver ModeMR

Successfull
receptionfrom a slave
receiver

S

SLA

R

A

DATA

A

$40

$08

DATA

A

$50

P

$58

Next transfer
started with arepeated start
condition

RS

SLA

R

$10
Not acknowledge
received after theslave address

A

W

P

$48
MT

Arbitration lost in slave
address or data byte

A or A

Other master
continues

A$38
Arbitration lost andaddressed as slave

A

$68

$38
Other master
continues

$78

DATA

From master to slave

From slave to master

Other master
continues

To corresponding
states in slave mode

$B0

A

Any number of data bytes
and their associated acknowledge bits
This number (contained in TWSR) corresponds
to a defined state of the Two-Wire Serial Bus. The
prescaler bits are zero or masked to zeron

25.7.3 Slave Receiver ModeIn the Slave Receiver mode, a number of data bytes are received from a MasterTransmitter (see Figure 25-15 below). All the status codes mentioned in this section
assume that the prescaler bits are zero or are masked to zero.
Figure 25-15. Data transfer in Slave Receiver mode
DEVDD

Device 1

Device 2

SLAVE
RECEIVERMASTER
TRANSMITTER

Device 3........

Device n

R1

R2

SDA

SCL

To initiate the Slave Receiver mode, TWAR and TWCR must be initialized as follows:
TWAR

TWA6

TWA5

TWA4

Value

Device’s Own Slave Address

TWA3

TWA2

TWA1

TWA0

TWGCE

393
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The upper 7 bits are the address to which the 2-wire Serial Interface will respond whenaddressed by a Master. If the LSB is set, the TWI will respond to the general calladdress (0x00), otherwise it will ignore the general call address.
TWCR

TWINT

TWEA

TWSTA

TWSTO

TWWC

TWEN

–

TWIE

Value

0

1

0

0

0

1

0

X

TWEN must be written to one to enable the TWI. The TWEA bit must be written to one
to enable the acknowledgement of the device’s own slave address or the general calladdress. TWSTA and TWSTO must be written to zero.
When TWAR and TWCR have been initialized, the TWI waits until it is addressed by its
own slave address (or the general call address if enabled) followed by the data direction
bit. If the direction bit is “0” (write), the TWI will operate in SR mode, otherwise ST modeis entered. After its own slave address and the write bit have been received, the TWINT
Flag is set and a valid status code can be read from TWSR. The status code is used todetermine the appropriate software action. The appropriate action to be taken for eachstatus code is detailed in Table 25-5 below. The Slave Receiver mode may also beentered if arbitration is lost while the TWI is in the Master mode (see states 0x68 and0x78).
If the TWEA bit is reset during a transfer, the TWI will return a “Not Acknowledge” (“1”)
to SDA after the next received data byte. This can be used to indicate that the Slave is
not able to receive any more bytes. While TWEA is zero, the TWI does not
acknowledge its own slave address. However, the 2-wire Serial Bus is still monitored
and address recognition may resume at any time by setting TWEA. This implies that the
TWEA bit may be used to temporarily isolate the TWI from the 2-wire Serial Bus.
In all sleep modes other than Idle mode, the clock system to the TWI is turned off. If the
TWEA bit is set, the interface can still acknowledge its own slave address or thegeneral call address by using the 2-wire Serial Bus clock as a clock source. The partwill then wake up from sleep and the TWI will hold the SCL clock low during the wakeup and until the TWINT Flag is cleared (by writing it to one). Further data reception will
be carried out as normal, with the AVR clocks running as normal. Observe that if the
AVR is set up with a long start-up time, the SCL line may be held low for a long time,
blocking other data transmissions.
Note that the 2-wire Serial Interface Data Register – TWDR does not reflect the lastbyte present on the bus when waking up from these Sleep modes.
Table 25-5. Status Codes for Slave Receiver Mode
Status Code(TWSR)
Prescaler
Bits are 0

Status of the 2-wire
Serial Bus and 2-wire
Serial Interface
Hardware

0x60

0x68

0x70

394

Application Software Response
To TWCR
To/from TWDR

STA

STO

TWINT

TWEA

Own SLA+W has been
received; ACK has beenreturned

No TWDR action or

X

0

1

0

No TWDR action

X

0

1

1

Arbitration lost in
SLA+R/W as Master;own SLA+W has been
received; ACK has beenreturned
General call address has
been received; ACK has
been returned

No TWDR action or

X

0

1

0

No TWDR action

X

0

1

1

No TWDR action or

X

0

1

0

No TWDR action

X

0

1

1

Next Action Taken by TWI
HardwareData byte will be received and NOT
ACK will be returned
Data byte will be received and ACK
will be returned
Data byte will be received and NOT
ACK will be returned
Data byte will be received and ACK
will be returned
Data byte will be received and NOT
ACK will be returned
Data byte will be received and ACK
will be returned

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ATmega128RFA1
0x78

0x80

0x88

0x90

0x98

Arbitration lost in
SLA+R/W as Master;
General call address has
been received; ACK has
been returned
Previously addressedwith own SLA+W; data
has been received; ACK
has been returned
Previously addressedwith own SLA+W; data
has been received; NOTACK has been returned

Previously addressedwith general call; data
has been re-ceived; ACK
has been returned
Previously addressedwith general call; data
has been received; NOTACK has been returned

No TWDR action or

X

0

1

0

No TWDR action

X

0

1

1

Read data byte or

X

0

1

0

Read data byte

X

0

1

1

Read data byte or

0

0

1

0

Read data byte or

0

0

1

1

Read data byte or

1

0

1

0

Read data byte

1

0

1

1

Read data byte or

X

0

1

0

Read data byte

X

0

1

1

Read data byte or

0

0

1

0

Read data byte or

0

0

1

1

1

0

1

0

1

0

1

1

Read data byte or
Read data byte

Data byte will be received and NOT
ACK will be returned
Data byte will be received and ACK
will be returned
Data byte will be received and NOT
ACK will be returned
Data byte will be received and ACK
will be returned
Switched to the not addressed Slavemode; no recognition of own SLA or
GCA
Switched to the not addressed Slavemode; own SLA will be recognized;
GCA will be recognized if TWGCE =“1”
Switched to the not addressed Slavemode; no recognition of own SLA or
GCA; a START condition will betransmitted when the bus becomesfree
Switched to the not addressed Slavemode; own SLA will be recognized;
GCA will be recognized if TWGCE =“1”; a START condition will betransmitted when the bus becomes
free
Data byte will be received and NOT
ACK will be returned
Data byte will be received and ACK
will be returned
Switched to the not addressed Slavemode; no recognition of own SLA or
GCA
Switched to the not addressed Slavemode; own SLA will be recognized;
GCA will be recognized if TWGCE =“1”
Switched to the not addressed Slavemode; no recognition of own SLA or
GCA; a START condition will betransmitted when the bus becomesfree
Switched to the not addressed Slavemode; own SLA will be recognized;
GCA will be recognized if TWGCE =“1”; a START condition will betransmitted when the bus becomes
free

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0xA0

A STOP condition or
repeated START
condition has been
received while still
addressed as Slave

No action

0

0

1

0

0

0

1

1

1

0

1

0

1

0

1

1

Switched to the not addressed Slavemode; no recognition of own SLA or
GCA
Switched to the not addressed Slavemode; own SLA will be recognized;
GCA will be recognized if TWGCE =“1”
Switched to the not addressed Slavemode; no recognition of own SLA or
GCA; a START condition will betransmitted when the bus becomesfree
Switched to the not addressed Slavemode; own SLA will be recognized;
GCA will be recognized if TWGCE =“1”; a START condition will betransmitted when the bus becomes
free

Figure 25-16. Formats and States in the Slave Receiver Mode
Reception of the own
slave address and one ormore data bytes. All areacknowledged

S

SLA

W

A

DATA

$60

A

DATA

$80

Last data byte received
is not acknowledged

A

P or S

$80

$A0

A

P or S$88
Arbitration lost as masterand addressed as slave

A$68
Reception of the general calladdress and one or more data
bytes

General Call

A

DATA

$70

A

DATA

$90

Last data byte received is
not acknowledged

A

P or S

$90

$A0

A

P or S$98
Arbitration lost as master andaddressed as slave by general callA

$78

From master to slave

From slave to master

DATA

A

n

Any number of data bytes
and their associated acknowledge bits
This number (contained in TWSR) corresponds
to a defined state of the Two-Wire Serial Bus. The
prescaler bits are zero or masked to zero25.7.4 Slave Transmitter ModeIn the Slave Transmitter mode, a number of data bytes are transmitted to a Master
Receiver (see Figure 25-17 on page 397). All the status codes mentioned in this section
assume that the prescaler bits are zero or are masked to zero.

396

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Figure 25-17. Data Transfer in Slave Transmitter Mode
DEVDD

Device 1

Device 2

SLAVETRANSMITTERMASTERRECEIVER

Device 3........

Device n

R1

R2

SDA

SCL

To initiate the Slave Transmitter mode, TWAR and TWCR must be initialized as follows:
TWAR

TWA6

TWA5

TWA4

Value

Device’s Own Slave Address

TWA3

TWA2

TWA1

TWA0

TWGCE

The upper seven bits are the address to which the 2-wire Serial Interface will respondwhen addressed by a Master. If the LSB is set, the TWI will respond to the general calladdress (0x00), otherwise it will ignore the general call address.
TWCR

TWINT

TWEA

TWSTA

TWSTO

TWWC

TWEN

–

TWIE

Value

0

1

0

0

0

1

0

X

TWEN must be written to one to enable the TWI. The TWEA bit must be written to one
to enable the acknowledgement of the device’s own slave address or the general calladdress. TWSTA and TWSTO must be written to zero.
When TWAR and TWCR have been initialized, the TWI waits until it is addressed by its
own slave address (or the general call address if enabled) followed by the data direction
bit. If the direction bit is “1” (read), the TWI will operate in ST mode, otherwise SR modeis entered. After its own slave address and the write bit have been received, the TWINT
Flag is set and a valid status code can be read from TWSR. The status code is used todetermine the appropriate software action. The appropriate action to be taken for eachstatus code is detailed in Table 25-6 on page 398. The Slave Transmitter mode may
also be entered if arbitration is lost while the TWI is in the Master mode (see state
0xB0).
If the TWEA bit is written to zero during a transfer, the TWI will transmit the last byte of
the transfer. State 0xC0 or state 0xC8 will be entered, depending on whether the
Master Receiver transmits a NACK or ACK after the final byte. The TWI is switched to
the not addressed Slave mode, and will ignore the Master if it continues the transfer.
Thus the Master Receiver receives all “1” as serial data. State 0xC8 is entered if the
Master demands additional data bytes (by transmitting ACK), even though the Slave
has transmitted the last byte (TWEA zero and expecting NACK from the Master).
While TWEA is zero, the TWI does not respond to its own slave address. However, the2-wire Serial Bus is still monitored and address recognition may resume at any time bysetting TWEA. This implies that the TWEA bit may be used to temporarily isolate the
TWI from the 2-wire Serial Bus.
In all sleep modes other than Idle mode, the clock system to the TWI is turned off. If the
TWEA bit is set, the interface can still acknowledge its own slave address or thegeneral call address by using the 2-wire Serial Bus clock as a clock source. The part

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will then wake up from sleep and the TWI will hold the SCL clock will low during thewake up and until the TWINT Flag is cleared (by writing it to one). Further datatransmission will be carried out as normal, with the AVR clocks running as normal.
Observe that if the AVR is set up with a long start-up time, the SCL line may be held
low for a long time, blocking other data transmissions.
Note that the 2-wire Serial Interface Data Register – TWDR does not reflect the lastbyte present on the bus when waking up from these sleep modes.
Table 25-6. Status Code for Slave Transmitter Mode
Status Code(TWSR)
Prescaler
Bits are 0

Status of the 2-wire
Serial Bus and 2-wire
Serial Interface
Hardware

0xA8

0xB0

0xB8

0xC0

0xC8

398

Application Software Response
To TWCR
To/from TWDR

STA

STD

TWINT

TWEA

Own SLA+R has been
received; ACK has beenreturned

Load data byte or

X

0

1

0

Load data byte

X

0

1

1

Arbitration lost in SLA+R/W
as Master; own SLA+R has
been received; ACK has
been returned
Data byte in TWDR has
been transmitted; ACK has
been received

Load data byte or

X

0

1

0

Load data byte

X

0

1

1

Load data byte or

X

0

1

0

Load data byte

X

0

1

1

Data byte in TWDR has
been transmitted; NOTACK has been received

No TWDR action or

0

0

1

0

No TWDR action or

0

0

1

1

No TWDR action or

1

0

1

0

No TWDR action

1

0

1

1

No TWDR action or

0

0

1

0

No TWDR action or

0

0

1

1

No TWDR action or

1

0

1

0

No TWDR action

1

0

1

1

Last data byte in TWDR
has been transmitted(TWEA = “0”); ACK has
been received

Next Action Taken by TWI
HardwareLast data byte will be transmitted andNOT ACK should be received Data
byte will be transmitted and ACK
should be received
Last data byte will be transmitted andNOT ACK should be received Data
byte will be transmitted and ACK
should be received
Last data byte will be transmitted andNOT ACK should be received
Data byte will be transmitted and
ACK should be received
Switched to the not addressed Slavemode; no recognition of own SLA or
GCA
Switched to the not addressed Slavemode; own SLA will be recognized;
GCA will be recognized if TWGCE =“1”
Switched to the not addressed Slavemode; no recognition of own SLA or
GCA; a START condition will betransmitted when the bus becomesfree
Switched to the not addressed Slavemode; own SLA will be recognized;
GCA will be recognized if TWGCE =“1”; a START condition will betransmitted when the bus becomesfree
Switched to the not addressed Slavemode; no recognition of own SLA or
GCA
Switched to the not addressed Slavemode; own SLA will be recognized;
GCA will be recognized if TWGCE =“1”
Switched to the not addressed Slavemode; no recognition of own SLA or
GCA; a START condition will betransmitted when the bus becomesfree
Switched to the not addressed Slavemode; own SLA will be recognized;
GCA will be recognized if TWGCE =“1”; a START condition will betransmitted when the bus becomesfree

ATmega128RFA1
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ATmega128RFA1
Figure 25-18. Formats and States in the Slave Transmitter Mode
Reception of the own
slave address and one ormore data bytes

S

SLA

R

A

DATA

A

$A8
Arbitration lost as masterand addressed as slave

DATA

$B8

A

P or S$C0A$B0Last data byte transmitted.
Switched to not addressedslave (TWEA = ’0’)A

All 1’s

P or S$C8DATA

From master to slave

A

From slave to master

Any number of data bytes
and their associated acknowledge bits
This number (contained in TWSR) corresponds
to a defined state of the Two-Wire Serial Bus. The
prescaler bits are zero or masked to zeron

25.7.5 Miscellaneous States
There are two status codes that do not correspond to a defined TWI state, see Table
25-7 below.
Status 0xF8 indicates that no relevant information is available because the TWINT Flag
is not set. This occurs between other states, and when the TWI is not involved in a
serial transfer.
Status 0x00 indicates that a bus error has occurred during a 2-wire Serial Bus transfer.
A bus error occurs when a START or STOP condition occurs at an illegal position in theformat frame. Examples of such illegal positions are during the serial transfer of an
address byte, a data byte, or an acknowledge bit. When a bus error occurs, TWINT isset. To recover from a bus error, the TWSTO Flag must set and TWINT must be
cleared by writing a logic one to it. This causes the TWI to enter the not addressed
Slave mode and to clear the TWSTO Flag (no other bits in TWCR are affected). The
SDA and SCL lines are released, and no STOP condition is transmitted.
Table 25-7. Miscellaneous States
Status Code(TWSR)
Prescaler
Bits are 0

Status of the 2-wire
Serial Bus and 2-wire
Serial Interface Hardware

0xF8

No relevant state
information available
Bus error due to an illegal
START or STOP condition

0x00

Application Software Response
To TWCR
To/from TWDR

STA

TWDR action

No TWCR action

No TWDR action

STO

0

1

TWINT

TWEA

Next Action Taken by TWI
HardwareWait or proceed current transfer

1

X

Only the internal hardware isaffected, no STOP condi-tion is senton the bus. In all cases, the bus isreleased and TWSTO is cleared.

25.7.6 Combining Several TWI Modes
In some cases, several TWI modes must be combined in order to complete the desired
action. Consider for example reading data from a serial EEPROM. Typically, such atransfer involves the following steps:
1. The transfer must be initiated.
2. The EEPROM must be instructed what location should be read.
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3. The reading must be performed.
4. The transfer must be finished.
Note that data is transmitted both from Master to Slave and vice versa. The Mastermust instruct the Slave what location it wants to read, requiring the use of the MT mode.
Subsequently, data must be read from the Slave, implying the use of the MR mode.
Thus, the transfer direction must be changed. The Master must keep control of the bus
during all these steps, and the steps should be carried out as an atomic operation. If
this principle is violated in a multi-master system, another Master can alter the data
pointer in the EEPROM between steps 2 and 3, and the Master will read the wrong data
location. Such a change in transfer direction is accomplished by transmitting a
REPEATED START between the transmission of the address byte and reception of thedata. After a REPEATED START, the Master keeps ownership of the bus. The following
figure shows the flow in this transfer.
Figure 25-19. Combining Several TWI Modes to Access a Serial EEPROM
Master Transmitter

S

SLA+W

A

ADDRESSS = START

Master Receiver

A

Rs

SLA+R

A

DATA

Rs = REPEATED START

Transmitted from master to slaveAP

P = STOP

Transmitted from slave to master25.8 Multi-master Systems and Arbitration
If multiple masters are connected to the same bus, transmissions may be initiatedsimultaneously by one or more of them. The TWI standard ensures that such situations
are handled in such a way that one of the masters will be allowed to proceed with thetransfer, and that no data will be lost in the process. An example of an arbitration
situation is depicted below, where two masters are trying to transmit data to a Slave
Receiver.
Figure 25-20. An Arbitration Example
DEVDD

Device 1

Device 2

Device 3

MASTER
TRANSMITTERMASTER
TRANSMITTERSLAVERECEIVER........

Device n

R1

R2

SDA

SCL

Several different scenarios may arise during arbitration, as described below:• Two or more masters are performing identical communication with the same Slave.
In this case, neither the Slave nor any of the masters will know about the bus
contention.
• Two or more masters are accessing the same Slave with different data or direction
bit. In this case, arbitration will occur, either in the READ/WRITE bit or in the data
bits. The masters trying to output a one on SDA while another Master outputs a zero400

ATmega128RFA1
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ATmega128RFA1
will lose the arbitration. Losing masters will switch to not addressed Slave mode or
wait until the bus is free and transmit a new START condition, depending on
application software action.
• Two or more masters are accessing different slaves. In this case, arbitration will
occur in the SLA bits. Masters trying to output a one on SDA while another Master
outputs a zero will lose the arbitration. Masters losing arbitration in SLA will switch to
Slave mode to check if they are being addressed by the winning Master. If
addressed, they will switch to SR or ST mode, depending on the value of the
READ/WRITE bit. If they are not being addressed, they will switch to not addressed
Slave mode or wait until the bus is free and transmit a new START condition,
depending on application software action.
This is summarized in Figure 25-21 below. Possible status values are given in circles.
Figure 25-21. Possible Status Codes Caused by Arbitration
START

SLA

Data

Arbitration lost in SLA

Own
Address / General Callreceived

No

STOP

Arbitration lost in Data

38

TWI bus will be released and not addressed slave mode will be entered
A START condition will be transmitted when the bus becomes freeYes

Direction

Write

68/78

Read
B0

Data byte will be received and NOT ACK will be returned
Data byte will be received and ACK will be returned

Last data byte will be transmitted and NOT ACK should be received
Data byte will be transmitted and ACK should be received

25.9 Register Description
25.9.1 TWBR – TWI Bit Rate Register
Bit

7

6

5

4

RW
0

RW
0

RW
0

RW
0

NA ($B8)
Read/Write
Initial Value

3

2

1

0

RW
0

RW
0

RW
0

TWBR7:0RW
0TWBR

The SCL period is controlled by settings in the TWI Bit Rate Register (TWBR) and the
Prescaler bits in the TWI Status Register (TWSR). Slave operation does not depend on
Bit Rate or Prescaler settings, but the CPU clock frequency in the Slave must be atleast 16 times higher than the SCL frequency.
• Bit 7:0 – TWBR7:0 - TWI Bit Rate Register ValueThe TWBR register selects the division factor for the bit rate generator. The bit rate
generator is a frequency divider which generates the SCL clock frequency in the Mastermodes. See section "Bit Rate Generator Unit" for calculating bit rates.

401
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25.9.2 TWCR – TWI Control Register
Bit

7

6

5

4

3

2

1

0

NA ($BC)

TWINT

TWEA

TWSTA

TWSTO

TWWC

TWEN

Res

TWIE

Read/Write
Initial Value

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

R
0

RW
0

TWCR

The TWCR is used to control the operation of the TWI. It is used to enable the TWI, toinitiate a Master access by applying a START condition to the bus, to generate a
Receiver acknowledge, to generate a stop condition, and to control halting of the bus
while the data to be written to the bus are put into the TWDR. It also indicates a write
collision if data writing to TWDR is attempted while the register is inaccessible.
• Bit 7 – TWINT - TWI Interrupt Flag
This bit is set by hardware when the TWI has finished its current job and expects
application software response. If the I-bit in SREG and TWIE in TWCR are set, theMCU will jump to the TWI Interrupt Vector. While the TWINT Flag is set, the SCL low
period is stretched. The TWINT Flag must be cleared by software by writing a logic one
to it. Note that this flag is not automatically cleared by hardware when executing theinterrupt routine. Also note that clearing this flag starts the operation of the TWI. So allaccesses to the TWI Address Register (TWAR), TWI Status Register (TWSR) and TWI
Data Register (TWDR) must be complete before clearing this flag.
• Bit 6 – TWEA - TWI Enable Acknowledge Bit
The TWEA bit controls the generation of the acknowledge pulse. If the TWEA bit is
written to one, the ACK pulse is generated on the TWI bus if the following conditions
are met: 1. The devices own slave address has been received; 2. A general call has
been received, while the TWGCE bit in the TWAR is set. 3. A data byte has been
received in Master Receiver or Slave Receiver mode. By writing the TWEA bit to zero,the device can be virtually disconnected from the 2-wire Serial Bus temporarily.
Address recognition can then be resumed by writing the TWEA bit to one again.
• Bit 5 – TWSTA - TWI START Condition Bit
The application writes the TWSTA bit to one when it desires to become a Master on the
2-wire Serial Bus. The TWI hardware checks if the bus is available and generates a
START condition on the bus if it is free. However, if the bus is not free, the TWI waits
until a STOP condition is detected and then generates a new START condition to claim
the bus Master status. TWSTA must be cleared by software when the START condition
has been transmitted.
• Bit 4 – TWSTO - TWI STOP Condition Bit
Writing the TWSTO bit to one in Master mode will generate a STOP condition on the 2wire Serial Bus. When the STOP condition is executed on the bus, the TWSTO bit iscleared automatically. In Slave mode, setting the TWSTO bit can be used to recoverfrom an error condition. This will not generate a STOP condition, but the TWI returns toa well-defined not-addressed Slave mode and releases the SCL and SDA lines to ahigh impedance state.
• Bit 3 – TWWC - TWI Write Collision Flag
The TWWC bit is set when attempting to write to the TWI Data Register TWDR when
TWINT is low. This flag is cleared by writing the TWDR Register when TWINT is high.
• Bit 2 – TWEN - TWI Enable Bit
The TWEN bit enables TWI operation and activates the TWI interface. When TWEN is
written to one, the TWI takes control over the I/O ports connected to the SCL and SDA

402

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ATmega128RFA1
pins enabling the slew-rate limiters and spike filters. If this bit is written to zero, the TWI
is switched off and all TWI transmissions are terminated regardless of any ongoing
operation.
• Bit 1 – Res - Reserved Bit
This bit is reserved for future use. A read access always will return zero. A write accessdoes not modify the content.
• Bit 0 – TWIE - TWI Interrupt Enable
When this bit is written to one and the I-bit in SREG is set, the TWI interrupt request will
be activated for as long as the TWINT Flag is high.

25.9.3 TWSR – TWI Status Register
Bit

7

6

5

4

3

2

1

0

NA ($B9)

TWS7

TWS6

TWS5

TWS4

TWS3

Res

TWPS1

TWPS0

Read/Write
Initial Value

RW
0

RW
0

RW
0

RW
0

RW
0

R
0

RW
0

RW
0

TWSR

• Bit 7:3 – TWS4:0 - TWI Status
These 5 bits reflect the status of the TWI logic and the 2-wire Serial Bus. The different
status codes for both transmitter and receiver mode are described in the following table.
Note that the value read from TWSR contains both the 5-bit status value and the 2-bit
prescaler value. The application designer should mask the prescaler bits to zero whenchecking the Status bits. This makes status checking independent of prescaler setting.
This approach is used in this datasheet, unless otherwise noted.
Table 25-8 TWS Register Bits
Register Bits

Value

Description

TWS4:00x00

Bus error due to illegal START or STOP
condition.

0x08

A START condition has been transmitted.

0x10

A repeated START condition has beentransmitted.

0x18

SLA+W has been transmitted; ACK has
been received.

0x20

SLA+W has been transmitted; NOT ACK has
been received.

0x28

Data byte has been transmitted; ACK has
been received.

0x30

Data byte has been transmitted; NOT ACK
has been received.

0x38

Arbitration lost in SLA+W or data bytes(Transmitter); Arbitration lost in SLA+R or
NOT ACK bit (Receiver).

0x40

SLA+R has been transmitted; ACK has been
received.

0x48

SLA+R has been transmitted; NOT ACK has
been received.

0x50

Data byte has been received; ACK has been

403
8266A-MCU Wireless-12/09

Register Bits

Value

Description
returned.

0x58

Data byte has been received; NOT ACK has
been returned.

0x60

Own SLA+W has been received; ACK has
been returned.

0x68

Arbitration lost in SLA+R/W as Master; own
SLA+W has been received; ACK has beenreturned.

0x70

General call address has been received;
ACK has been returned.

0x78

Arbitration lost in SLA+R/W as Master;general call address has been received;
ACK has been returned.

0x80

Previously addressed with own SLA+W; data
has been received; ACK has been returned.

0x88

Previously addressed with own SLA+W; data
has been received; NOT ACK has beenreturned.

0x90

Previously addressed with general call; data
has been received; ACK has been returned.

0x98

Previously addressed with general call; data
has been received; NOT ACK has beenreturned.

0xA0

A STOP condition or repeated START
condition has been received while still
addressed as Slave.

0xA8

Own SLA+R has been received; ACK has
been returned.

0xB0

Arbitration lost in SLA+R/W as Master; own
SLA+R has been received; ACK has beenreturned.

0xB8

Data byte in TWDR has been transmitted;
ACK has been received.

0xC0

Data byte in TWDR has been transmitted;
NO ACK has been received.

0xC8

Last data byte in TWDR has beentransmitted (TWEA = 0); ACK has been
received.

0xF8

No relevant state information available;
TWINT = 0.

• Bit 2 – Res - Reserved Bit
This bit is reserved for future use. A read access always will return zero. A write accessdoes not modify the content.
• Bit 1:0 – TWPS1:0 - TWI Prescaler Bits
These bits can be read and written and control the bit rate of the prescaler.
Table 25-9 TWPS Register Bits

404

Register Bits

Value

Description

TWPS1:00x00

1

ATmega128RFA1
8266A-MCU Wireless-12/09

ATmega128RFA1
Register Bits

Value

Description

0x01

4

0x02

16

0x03

64

25.9.4 TWDR – TWI Data Register
Bit

7

6

5

4

3

2

1

0

NA ($BB)

TWD7

TWD6

TWD5

TWD4

TWD3

TWD2

TWD1

TWD0

Read/Write
Initial Value

RW
1

RW
1

RW
1

RW
1

RW
1

RW
1

RW
1

RW
1

TWDR

In Transmit mode, TWDR contains the next byte to be transmitted. In Receive mode,
the TWDR contains the last byte received. It is writable while the TWI is not in theprocess of shifting a byte. This occurs when the TWI Interrupt Flag (TWINT) is set by
hardware. Note that the Data Register cannot be initialized by the user before the firstinterrupt occurs. The data in TWDR remains stable as long as TWINT is set. While datais shifted out, data on the bus is simultaneously shifted in. TWDR always contains thelast byte present on the bus, except after a wake up from a sleep mode by the TWIinterrupt. In this case, the contents of TWDR is undefined. In the case of a lost bus
arbitration, no data is lost in the transition from Master to Slave. Handling of the ACK bit
is automatically controlled by the TWI logic. The CPU cannot access the ACK bit
directly.
• Bit 7:0 – TWD7:0 - TWI Data Register Byte

25.9.5 TWAR – TWI (Slave) Address Register
Bit

7

6

5

4

3

2

1

0

NA ($BA)

TWA6

TWA5

TWA4

TWA3

TWA2

TWA1

TWA0

TWGCE

Read/Write
Initial Value

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

TWAR

The TWAR should be loaded with the 7-bit Slave address (in the seven most significant
bits of TWAR) to which the TWI will respond when programmed as a Slave Transmitteror Receiver. This register is not needed in the Master modes. In multi-master systems
TWAR must be set in Masters which can be addressed as Slaves by other Masters.
The LSB of TWAR is used to enable the recognition of the general call address (0x00).
There is an associated address comparator that looks for the slave address (or generalcall address if enabled) in the received serial address. If a match is found, an interrupt
request is generated.
• Bit 7:1 – TWA6:0 - TWI (Slave) Address
These bits contain the TWI address operated as a Slave device.
• Bit 0 – TWGCE - TWI General Call Recognition Enable Bit
If set, this bit enables the recognition of a General Call given over the 2-wire Serial Bus.

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25.9.6 TWAMR – TWI (Slave) Address Mask Register
Bit

7

6

5

4

3

2

1

0

NA ($BD)

TWAM6

TWAM5

TWAM4

TWAM3

TWAM2

TWAM1

TWAM0

Res

Read/Write
Initial Value

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

R
0

TWAMR

• Bit 7:1 – TWAM6:0 - TWI Address Mask
The TWAMR can be loaded with a 7-bit Slave Address mask. Each of the bits in
TWAMR can mask (disable) the corresponding address bit in the TWI Address Register(TWAR). If the mask bit is set to one then the address match logic ignores the compare
between the incoming address bit and the corresponding bit in TWAR.
• Bit 0 – Res - Reserved Bit
This bit is reserved for future use. A read access always will return zero. A write accessdoes not modify the content.

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ATmega128RFA1
26 AC – Analog Comparator
The Analog Comparator compares the input values on the positive pin AIN0 and
negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage
on the negative pin AIN1, the Analog Comparator output, ACO, is set. The comparator’s
output can be set to trigger the Timer/Counter1 Input Capture function. In addition, thecomparator can trigger a separate interrupt, exclusive to the Analog Comparator. The
user can select Interrupt triggering on comparator output rise, fall or toggle. A block
diagram of the comparator and its surrounding logic is shown in Figure 26-1 below.
The Power Reduction ADC bit PRADC in PRR0 (see "PRR0 – Power Reduction
Register0" on page 167) must be disabled by writing a logical zero to be able to use the
ADC input multiplexer.
Figure 26-1. Analog Comparator Block Diagram

Note:

1. See Table 26-1 below.
2. Refer to Figure 1-1 on page 2 and Table 14-9 on page 197 for Analog Comparator
pin placement.

26.1 Analog Comparator Multiplexed Input
It is possible to select any of the ADC7:0 pins as the negative input of the Analog
Comparator. The ADC multiplexer is used to select this input and consequently the
ADC must be switched off to utilize this feature. If the Analog Comparator Multiplexer
Enable bit (ACME in ADCSRB) is set and the ADC is switched off (ADEN in ADCSRA iszero), MUX5 and MUX2:0 in ADMUX select the input pin to replace the negative input
to the Analog Comparator, as shown in Table 26-1 below. If ACME is cleared or ADEN
is set, AIN1 is applied to the negative input to the Analog Comparator.
Table 26-1. Analog Comparator Multiplexed Input
ACME

ADEN

MUX5

MUX2:0

Analog Comparator Negative Input

0

x

x

xxx

AIN1

1

1

x

xxx

AIN1

1

0

0

000

ADC0

1

0

0

001

ADC1

1

0

0

010

ADC2

1

0

0

011

ADC3

1

0

0

100

ADC4

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ACME

ADEN

MUX5

MUX2:0

Analog Comparator Negative Input

1

0

0

101

ADC5

1

0

0

110

ADC6

1

0

0

111

ADC7

26.2 Register Description
26.2.1 ACSR – Analog Comparator Control And Status Register
Bit

7

6

5

4

3

2

1

0

$30 ($50)

ACD

ACBG

Read/Write
Initial Value

RW
0

RW
0

ACO

ACI

ACIE

ACIC

ACIS1

ACIS0

R
NA

RW
0

RW
0

RW
0

RW
0

RW
0

ACSR

• Bit 7 – ACD - Analog Comparator Disable
When this bit is written logic one, the power to the Analog Comparator is switched off.
This bit can be set at any time to turn off the Analog Comparator. This will reduce power
consumption in Active and Idle mode. When changing the ACD bit, the Analog
Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise aninterrupt can occur when the bit is changed.
• Bit 6 – ACBG - Analog Comparator Bandgap SelectWhen this bit is set, a fixed bandgap reference voltage connects to the positive input of
the Analog Comparator. When this bit is cleared, AIN0 is applied to the positive input of
the Analog Comparator. When the bandgap reference is used as the input of theAnalog Comparator, it will take a certain time for the voltage to stabilize. If notstabilized, the first comparison may give a wrong value. See section "Internal Voltage
Reference" for details.
• Bit 5 – ACO - Analog Compare Output
The output of the analog comparator is synchronized and then directly connected to
ACO. The synchronization introduces a delay of 1-2 clock cycles.
• Bit 4 – ACI - Analog Comparator Interrupt Flag
This bit is set by hardware when a comparator output event triggers the interrupt mode
defined by ACIS1 and ACIS0. The Analog Comparator Interrupt routine is executed if
the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hard-ware when
executing the corresponding interrupt handling vector. Alternatively, ACI is cleared bywriting a logic one to the flag.
• Bit 3 – ACIE - Analog Comparator Interrupt Enable
When the ACIE bit is written logic one and the I-bit in the Status Register is set, theanalog comparator interrupt is activated. When written logic zero, the interrupt isdisabled.
• Bit 2 – ACIC - Analog Comparator Input Capture Enable
When written logic one, this bit enables the input capture function in Timer/Counter1 to
be triggered by the Analog Comparator. The comparator output is in this case directly
connected to the input capture front-end logic, making the comparator utilize the noise
canceler and edge select features of the Timer/Counter1 Input Capture interrupt. When
written logic zero, no connection between the Analog Comparator and the input capture
function exists. To make the comparator trigger the Timer/Counter1 Input Captureinterrupt, the ICIE1 bit in the Timer Interrupt Mask Register (TIMSK1) must be set.

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ATmega128RFA1• Bit 1:0 – ACIS1:0 - Analog Comparator Interrupt Mode Select
These bits determine which comparator events that trigger the Analog Comparator
interrupt. The different settings are shown in the following table. When changing the
ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by clearing its
Interrupt Enable bit in the ACSR Register. Otherwise an interrupt can occur when thebits are changed.
Table 26-2 ACIS Register Bits
Register Bits

Value

Description

ACIS1:0

0x00

Interrupt on Toggle

0x01

Reserved

0x02

Interrupt on Falling Edge

0x03

Interrupt on Rising Edge

26.2.2 ADCSRB – ADC Control and Status Register B
Bit

7

6

NA ($7B)

ACME

Read/Write
Initial Value

RW
0

5

4

3

2

1

0

ADCSRB• Bit 6 – ACME - Analog Comparator Multiplexer Enable
When this bit is written logic one and the ADC is switched off (ADEN in ADCSRA iszero), the ADC multiplexer defines the negative input of the Analog Comparator. When
this bit is written logic zero, AIN1 is applied to the negative input of the Analog
Comparator. For a detailed description of this bit, see section "Analog Comparator
Multiplexed Input".

26.2.3 DIDR1 – Digital Input Disable Register 1
Bit

7

6

5

4

3

2

1

0

NA ($7F)

AIN1D

AIN0D

Read/Write
Initial Value

RW
0

RW
0

DIDR1

• Bit 1 – AIN1D - AIN1 Digital Input Disable
When this bit is written logic one, the digital input buffer on the AIN1 pin is disabled. The
corresponding PIN Register bit will always read as zero when this bit is set. When an
analog signal is applied to the AIN1 pin and the digital input from this pin is not needed,
this bit should be written logic one to reduce power consumption in the digital input
buffer.
• Bit 0 – AIN0D - AIN0 Digital Input Disable
When this bit is written logic one, the digital input buffer on the AIN0 pin is disabled. The
corresponding PIN Register bit will always read as zero when this bit is set. When an
analog signal is applied to the AIN0 pin and the digital input from this pin is not needed,
this bit should be written logic one to reduce power consumption in the digital input
buffer.

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27 ADC – Analog to Digital Converter
27.1 Features• 10-bit Resolution• Differential Non-Linearity is less than ± 0.5 LSB• 2 LSB Integral Non-Linearity• 3 - 240 µs Conversion Time
• Up to 330 kSPS (Up to 570 kSPS with 8-bit Resolution)• 8 Multiplexed Single Ended Input Channels• 11 Differential Input Channels• 2 Differential Input Channels with an Optional Gain of 10x and 200x
• Internal Linear Temperature Sensor• Optional Left Adjustment for ADC Result Readout• 0 - VAVDD ADC Input Voltage Range• 0 - VEVDD Differential ADC Input Voltage Range• Selectable 1.5V, 1.6V or VAVDD ADC Reference Voltage• Free Running or Single Conversion Mode
• Interrupt on ADC Conversion Complete• Sleep Mode Noise Canceller
The ATmega128RFA1 features a 10-bit successive approximation ADC. The ADC isconnected to an 8-channel Analog Multiplexer which allows eight single-ended voltage
inputs constructed from the pins of Port F. The single-ended voltage inputs refer to 0V(AVSS).
The device also supports multiple differential voltage input combinations. Two of thedifferential inputs (ADC1 & ADC0 and ADC3 & ADC2) are equipped with aprogrammable gain stage, providing amplification steps of 0 dB (1x), 20 dB (10x) or 46
dB (200x) on the differential input voltage before the A/D conversion. The differential
input channels are constructed of pairs out of the 8 single-ended inputs. They share acommon negative terminal (ADC0, ADC1 or ADC2), while most of the other ADC inputs
can be selected as the positive input terminal. If 1x or 10x gain is used, 8 bit resolution
can be expected. If 200x gain is used, 6 bit resolution can be expected.
The ADC contains a Sample and Hold circuit which ensures that the input voltage to the
ADC is held at a constant level during conversion. A block diagram of the ADC is shownin Figure 27-1 on page 411.
The analog components of the ADC are supplied from the analog supply voltage AVDD.
AVDD is generated from EVDD by an internal voltage generator. The logic part of the
ADC is supplied from the digital supply voltage DVDD. DVDD is generated from
DEVDD also by an internal voltage generator.
Internal reference voltages of nominally 1.5V, 1.6V or AVDD (1.8V) are provided onchip. The 1.6V reference is calibrated to ± 1 LSB during manufacturing. The reference
voltage can be monitored at the AREF pin. Additional de-coupling capacitance at AREF
is not required. A high capacitive loading of AREF will de-stabilize the internal reference
voltage generation. An external reference voltage in the range of 0 < VAREF,EXT ≤ VAVDD
may be used but must be supplied with a very low impedance.

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ATmega128RFA1
The Power Reduction ADC bit, PRADC (see "PRR0 – Power Reduction Register0" onpage 167) must be disabled by writing a logical zero to enable the ADC.
Figure 27-1. Analog to Digital Converter Block Schematic
AD C ON VER SIONC OMPLETE IRQ
INTE RRUP T
FLAGSADTS [2:0]

TRIGGER
SELECT

ADC[9:0]ADIF

0

AD C DATA R EG ISTER(ADC H/AD CL)

ADFR

ADSC

ADPS[2:0]

ADIF

ADEN

ACCH

DIFF / GAIN SELECT

CHANNEL SELECTION

INTERNAL
REFERENCE(1.5V/1.6V)

15

AD C C TRL & STATUS
REGISTER A (AD CSR A)

PR ESC ALERM UX D EC ODER

AVD D

ADSUT[4:0]

AD C C TRL & STATU SREG ISTER C (ADC SR C)
ADTHT[1:0]

AD C CTRL & STATUS
R EGISTER B (ADC SR B)
MUX[5]ADLAR

MUX[4:0]

REFS[1:0]

ADC MULTIPLEXERSELECT (ADMU X)

ADIE

8-BIT D ATABU S

STA RT

C ON VER SION LOGIC

AREF

10-bit DAC
SAMPLE & H OLD
CO MPARATOR
ADC[2:0]GAIN
AMPLIFIER
AD C[7:0]
BA NDGAPREFERE NCE
1.2V
TEM PE RA TURES ENS OR

CLAMP
AD C
MULTIPLEXEROUTPUTDRT VO LTA GESRAM 2AVSS

27.2 Operation
The ADC converts an analog input voltage to a 10-bit digital value through successive
approximation. The minimum value represents 0V (conversion result 0x000) and the
maximum value in single ended mode represents the reference voltage minus 1 LSB(conversion result 0x3FF). The reference voltage can be measured at the AREF pin.
The internal, generated reference voltage can have the values 1.5V, 1.6V or AVDD
where the 1.6V has the highest absolute accuracy. The reference voltage is selected bywriting to the REFSn bits in the ADMUX Register. An external reference voltage canalso be selected. Such an external voltage must be supplied with a very low impedance
RAREF,EXT (see "ADC Electrical Characteristics" on page 505). The load current IL,AREF(see "ADC Electrical Characteristics" on page 505) seen by the external source is code
dependent and changes in the course of the successive approximation process (loadcurrent steps). The internal voltage reference (except AVDD) must not be decoupled by
an external capacitor. Adding unnecessary external capacitance at the AREF pin will

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cause instable operation of the internal reference voltage buffer and will not improvenoise immunity.
The analog input channel is selected by writing to the MUX bits in ADMUX and
ADCSRB. Any of the ADC input pins, as well as AVSS and a fixed bandgap voltage
reference can be selected as single ended inputs to the ADC. A choice of ADC input
pins can be selected as positive and negative inputs to the differential amplifier.
Furthermore the temperature sensor and the DRT voltages of SRAM2 can also beprocessed with the ADC.
If differential channels are selected, the amplified voltage difference between theselected input channel pair then becomes the input of the ADC. The respective pin
voltages for a differential measurement can be in the range from 0V to EVDD. In thisway it is possible to handle differential input voltages with a common mode value higher
than AVDD e.g. process a 50mV differential signal with a 2.5V common mode voltage.
If single ended channels are used, the gain amplifier is bypassed altogether. Any ADC
input voltage (single-ended or amplified-differential) exceeding AVDD will be internallyclamped to AVDD to avoid damaging the ADC circuitry. Note that the pin input current
will not increase if the clamp circuit is active.
The ADC is enabled by setting ADEN bit in ADCSRA. Voltage reference and input
channel selections will not go into effect until ADEN is set. The ADC does not consume
power when ADEN is cleared. It is required to disable the ADC before entering powersaving sleep modes.
The ADC generates a 10-bit result which is presented in the ADC Data Registers,
ADCH and ADCL. By default, the result is presented right adjusted, but can optionallybe presented left adjusted by setting the ADLAR bit in ADMUX.
If the result is left adjusted and no more than 8-bit precision is required, it is sufficient toread ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that thecontent of the Data Registers belongs to the same conversion. Once ADCL is read,
ADC access to Data Registers is blocked. This means that if ADCL has been read, anda conversion completes before ADCH is read, neither register is updated and the result
from the conversion is lost. When ADCH is read, ADC access to the ADCH and ADCL
Registers is re-enabled.
The ADC has its own interrupt which can be triggered when a conversion completes.
When ADC access to the Data Registers is prohibited between reading of ADCH and
ADCL, the interrupt will trigger even if the result is lost.

27.3 ADC Start-Up
After the ADC is enabled by setting ADEN, it will go through a start-up phase. The
analog supply voltage AVDD is turned on. It takes time tAVREG (see "Power Management
Electrical Characteristics" on page 503) µs for AVDD to stabilize. A stable AVDD
voltage is indicated by the AVDDOK bit in ADCSRB. After this the ADC and, fordifferential input channels also the gain amplifier, is powered up. The duration of thisphase depends on the ADC clock period and the configuration of the Start-Up andTrack-And–Hold Time bits, ADSUT4:0 and ADTHT1:0 in ADCSRC. For details about
the start-up timing refer to section "Pre-scaling and Conversion Timing" on page 413.
During the ADC start-up phase a conversion start can already be requested by writing a
logical one to the ADC Start Conversion bit, ADSC in ADCSRA. In this case aconversion is started directly after the start-up phase. During the start-up phase it is still
possible to change the analog input channel until the AVDDOK bit changes to logic one
or, if the AVDDOK bit is one, until the ADSC bit is set.

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ATmega128RFA1
27.4 Starting a Conversion
A single conversion is started by writing a logical one to the ADC Start Conversion bit,
ADSC. This bit stays high as long as the conversion is in progress and will be clearedby hardware when the conversion is completed. If a different data channel is selected
while a conversion is in progress, the ADC will finish the current conversion before
performing the channel change.
Alternatively, a conversion can be triggered automatically by various sources. Auto
Triggering is enabled by setting the ADC Auto Trigger Enable bit, ADATE in ADCSRA.
The trigger source is selected by setting the ADC Trigger Select bits, ADTS in ADCSRB(See description of the ADTS bits for a list of the trigger sources). When a positive edge
occurs on the selected trigger signal, the ADC prescaler is reset and a conversion isstarted. This provides a method of starting conversions at fixed intervals. If the trigger
signal still is set when the conversion completes, a new conversion will not be started. If
another positive edge occurs on the trigger signal during conversion, the edge will beignored. Note that an Interrupt Flag will be set even if the specific interrupt is disabled or
the Global Interrupt Enable bit in SREG is cleared. A conversion can thus be triggered
without causing an interrupt. However, the Interrupt Flag must be cleared in order totrigger a new conversion at the next interrupt event.
Figure 27-2. ADC Auto Trigger Logic
ADTS[2:0]

PRESCALER

START
ADIF

CLKADCADATE

SOURCE 1.
.
.
.
SOURCE n

CONVERSION
LOGIC
EDGE
DETECTORADSC

Using the ADC Interrupt Flag as a trigger source makes the ADC start a newconversion as soon as the ongoing conversion has finished. The ADC then operates inFree Running mode, constantly sampling and updating the ADC Data Register. The first
conversion must be started by writing a logical one to the ADSC bit in ADCSRA. In thismode the ADC will perform successive conversions independently of whether the ADC
Interrupt Flag, ADIF is cleared or not.
If Auto Triggering is enabled, single conversions can be started by writing ADSC in
ADCSRA to one. ADSC can also be used to determine if a conversion is in progress.
The ADSC bit will be read as one during a conversion, independently of how theconversion was started.

27.5 Pre-scaling and Conversion Timing
27.5.1 Prescaler
By default, the successive approximation circuitry requires an input clock frequency
between 50 kHz and 4 MHz. If a lower resolution than 10 bits is needed, the input clock

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8266A-MCU Wireless-12/09

frequency to the ADC can be as high as 8 MHz to get a higher sample rate. For
differential input channels the ADC clock speed is restricted to a maximum of 2 MHz.
Figure 27-3. ADC Prescaler
ADEN
START

Reset
7-BIT ADC PRESCALER

CK/64

CK/128

CK/32

CK/8

CK/16

CK/4

CK/2

CK

ADPS0
ADPS1
ADPS2

ADC CLOCK SOURCEThe ADC module contains a prescaler, which generates an acceptable ADC clock
frequency from any CPU frequency above 100 kHz. The pre-scaling is set by the ADPS
bits in ADCSRA. The prescaler starts counting from the moment when the ADC isenabled. The prescaler keeps running for as long as the ADEN bit is set, and iscontinuously reset when ADEN is low.
27.5.2 Start-Up Timing
The ADC is enabled by setting the ADEN bit in ADCSRA. First the analog voltage
regulator is powered up which takes tAVREG (see "Power Management Electrical
Characteristics" on page 503). A stable AVDD is indicated by the AVDDOK bit in
ADCSRB.
After AVDD has stabilized, the ADC is started. The ADC start-up time has a length oftADSU and can be adjusted by the Start-Up time bits ADSUT4:0 in ADCSRC. If
differential input channels are used, then an additional initialization period tAINIT isrequired by the gain amplifier. This period is configured by the Track-And-Hold Timebits, ADTHT1:0 in ADCSRC. ADSUT4:0 and ADTHT1:0 are fixed numbers of ADC
clock cycles and can be setup for different ADC clock speeds.
The minimum required ADC start-up time is 20 µs. Note that for the maximum ADC
speed of 8 MHz the start-up time can not be set higher than 16 µs in ADSUT4:0. Under
this condition the user has either to ensure that a conversion is not started earlier than
20 µs after the ADC is enabled or the first conversion result should be discarded.
For a summary of start-up times and sequences see Table 27-1 below, Table 27-2
below, Figure 27-4 on page 415 and Figure 27-5 on page 415.
Table 27-1. Start-Up Time, Single Ended Channels
Parameter

Duration in ADC Clock Cycles

ADC Start-Up Time tADSU

4(ADSUT+1), minimum 20 µs

Table 27-2. Start-Up Time, Differential Channels

414

Parameter

Duration in ADC Clock Cycles

ADC Start-Up Time tADSU

4(ADSUT+1), minimum 20 µs

ATmega128RFA1
8266A-MCU Wireless-12/09

ATmega128RFA1
Parameter

Duration in ADC Clock Cycles

Gain Amplifier Initialization Time tAINIT

2(ADTHT+2)

Figure 27-4. ADC Timing Diagram, Start-Up for Single Ended Channels
AVDD
P o w e r -U p

ADC
S t a rt -U p

C o n v e rs io n

A D C C lo c k
ADEN
AVDDOKADSC
A D IFADCH

S ig n a n d M S B o f R e s u lt
L S B o f R e s u lt

ADCLtAV PUtA D S U

11 T ADC_CLK
C o n v e rs io n
C o m p le te

S a m p le
& H o ld

M U X a n d R E F S U p d a te

Figure 27-5. ADC Timing Diagram, Start-Up for Differential Channels
AVDD
P o w e r -U p

ADC
S ta r t -U p

A m p lifie r
In it

C o n v e r s io n

A D C C lo c k
ADEN
AVDDOKADSC
A D IFADCH

S ig n a n d M S B

ADCLL S B o f R e s u lt
tA V P U
M U X a n d R E F S U p d a tetA D S U

t A IN IT

1 1 T AD C_CLK
S a m p le
& H o ld

C o n v e rs io n
C o m p le te27.5.3 Conversion Timing
The delay from requesting a conversion start by setting the ADSC bit in ADCSRA to themoment where the sample-and-hold takes place is fixed. The same fixed delay also
applies for auto triggered conversions. In this case three additional CPU clock cycles
are used for the trigger event synchronization logic. The delay depends on theprescaler configuration ADPS and if single-ended or differential channels are used. A
summary is given in Table 27-3 on page 416. All conversions take 11 ADC clock cycles.
When a conversion is complete, the result is written to the ADC Data Registers, and
ADIF is set. In Single Conversion mode, ADSC is cleared simultaneously. The software
may then set ADSC again, and a new conversion will be initiated at the earliest after thefollowing tracking phase. The tracking phase is required after each conversion. Its
duration can be adjusted according to the ADC clock speed by the ADTHT bits in
ADCSRC and is different for single-ended and differential channels. For details see
Table 27-4 on page 416.
In Free Running mode, a new conversion will be started immediately after the tracking
phase of the previous conversion while ADSC remains high. The calculation of theresulting sample rate is given in Table 27-5 on page 416.
For timing diagrams of single and auto triggered and free running conversions see
Figure 27-6 on page 416 to Figure 27-8 on page 417.

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8266A-MCU Wireless-12/09

Table 27-3. Conversion Start Delay
Channel

ADPS

Delay from Conversion Start Request to Sample &Hold tSCSMPSingle-Ended0, 1

2 CPU clock cycles

2

4 CPU clock cycles

30 CPU clock cycles

4…7

0 CPU clock cycles

0…7

2 ADC clock cycles

Differential

Table 27-4. Tracking Time
ChannelTracking Phase Duration tTRCK in ADC Clock Cycles

Single-Ended

ADTHT+1, minimum 500 ns

Differential

2ADTHT+3

Table 27-5. Sample Rate in Free Running Mode
ChannelSample Rate in ADC Clock Cycles

Single-Ended

ADTHT+12

Differential

2ADTHT+14

Figure 27-6. ADC Timing Diagram, Single Conversion
C o n ve rs io n

T ra c k in g

C o n ve rs io n

A D C C lo c k
AD EN
AD SC
A D IFADCH

S ig n a n d M S B o f R e s u lt

ADCL

L S B o f R e s u lt
tS C S M P
M U X a n d R E F S U p d a tetTR C K1 1 T A D C _ C LK
P re s ca le r R e s e t
andS a m p le & H o ld

C o n ve rs io n
C o m p le tetS C S M P
P re s ca le r
R e se t
andS a m p le
& H o ld

M U X a n d R E F S U p d a te

Figure 27-7. ADC Timing Diagram, Auto Triggered Conversion
C o n v e rs io n

T ra c kin g

C o n ve rs io n

A D C C lo ck
AD EN
T rig g e r S o u rc e
AD ATEA D IFADCH

S ig n a n d M S B o f R e s u lt

ADCL

L S B o f R e su lt
tS C S M P
M U X a n d R E F S U p d a te

416

1 1 T AD C_C LK
P re s ca le r R e s e t
andS a m p le & H o ld

C o n ve rs io n
C o m p le tetT R C K

tSC S M P

M U X a n d R E F S U p d a te

P re s ca le r
R e se t
andS a m p le
& H o ld

ATmega128RFA1
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ATmega128RFA1
Figure 27-8. ADC Timing Diagram, Free Running Conversion
C o n v e rs io n

T ra c k in g

C o n v e rs io n

A D C C lo c k
A D T S [2 :0 ]0ADSC
A D IFADCH

S ig n a n d M S B o f R e s u lt

ADCL

L S B o f R e s u lt
1 1 T A D C_C LK

tT RC KC o n v e rs io n
C o m p le te

M U X a n d R E F S U p d a te

1 1 T A D C _C L K
S a m p le & H o ld

27.6 Changing Channel or Reference Selection
The MUXn and REFSn bits in the ADMUX and ADCSRB Register are single bufferedthrough a temporary register to which the CPU has random access. This ensures thatthe channels and reference selection only takes place at a safe point during theconversion. The channel and reference selection is continuously updated either during
the AVDD power-up phase or until a conversion is started by setting ADSC. After thisthe channel and reference selection is locked to ensure a sufficient initialization andsampling time for the ADC. Continuous updating of the channel selection resumes after
the conversion has completed (ADIF in ADCSRA is set). The reference selection can
only be updated if the ADC is disabled and enabled again.
If Auto Triggering is used, the exact time of the triggering event can be undetermined.
Special care must be taken when updating the ADMUX Register, in order to control
which conversion will be affected by the new settings.
If both ADATE and ADEN in the ADSCRA Register are written to one, an interrupt
event can occur at any time. If the ADMUX Register is changed in this period, the user
cannot tell if the next conversion is based on the old or the new settings. ADMUX canbe safely updated in the following ways:
1. When ADATE or ADEN is cleared.
2. During a conversion
3. After a conversion, before the Interrupt Flag used as trigger source is cleared.
When updating ADMUX in one of these conditions, the new settings will affect the next
A/D conversion.
After the channel or reference voltage selection is updated a settling time is required for
the ADC and the gain amplifier or the reference voltage to stabilize. When changing
the channel selection while the ADC is enabled the required settling phase is
automatically inserted by the ADC interface, see section "ADC Input Channels" on page418. For consideration on changing the reference voltage selection please refer tosection"ADC Voltage Reference" on page 419.
27.6.1 Accessing the ADMUX Register
The channel selection bits MUX4:0 and MUX5 are located in two different register, the
ADMUX and the ADCSRB register. To ensure that changes go only into effect after
both register have been changed they are internally buffered (see Figure 27-9 on page
419 and Figure 27-10 on page 419). The MUX5 bit has to written first followed by awrite access to the MUX4:0 bits which triggers the update of the internal buffer. If only

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the MUX4:0 bits need to be modified then a write access to the MUX4:0 bits issufficient.
27.6.2 ADC Input Channels
The ADC input channels can be changed while the ADC is running under the condition
that the previous channel was a single-ended one. Changing between differential
channels however requires that the ADC is disabled and enabled again to make the
ADC go through the initial start-up phase.
If changing from single-ended to single-ended or from single-ended to differential input
channels a settling phase is automatically inserted by the ADC interface logic after the
input channel is modified. The settling phase is required by the ADC and the gain
amplifier to stabilize. If a conversions start is requested during this settling phase, bysetting ADSC or by a trigger event in Auto Triggered mode then the conversion isstarted only after the settling phase has completed.
In case the MUXn bits are altered during an ongoing conversion, the ADC input channel
is changed after the conversion has completed. MUXn changes occurring during the
tracking phase, which follows a conversion, will stop the tracking phase and the ADC
settling phase will be entered.
In Free Running mode MUXn can also be modified. In this case the ADC input channel
is changed after the conversion end or from the subsequent tracking phase. As aconsequence the time from one conversion to the next is extended by the duration of
the ADC settling phase.
The ADC settling time tASET depends on the previous and the new channel and on theconfiguration of the ADSUT4:0 and ADTHT1:0 bits as shown in Table 27-6 below.
Additionally a synchronization delay tCHDLY from 2 CPU to 2 ADC Clock cycles isrequired between changing the ADC input channel selection and the beginning of thesettling phase. For details see the timing diagrams Figure 27-9 on page 419 and Figure27-10 on page 419.
If the analog input signal encounters large variations it can be useful to manually reset
the ADC and the gain amplifier before starting a new conversion. To achieve this, thesettling phase can be forced without modifying MUXn by writing a logic one to theAnalog Channel Change bit ACCH in ADCSRB. Using the ACCH bit is only
recommended for single-ended input channels. For differential input channels the ADC
and the gain amplifier can be reset if the ADC is disabled and enabled again.

Table 27-6. Settling Time after Channel Changes

418

Channel Transition

Settling Time tASET in ADC Clock Cycles

Single-Ended or Differential to Single-Ended

ADTHT+2

Single-Ended to Differential

4(ADSUT+1) + 2(ADTHT+2)

Differential to Differential

Requires the ADC to be disabled and enabledagain.

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ATmega128RFA1
Figure 27-9. ADC Timing Diagram, Changing MUXn after a Conversion
C o n v e rs io n

A D C S e ttlin g

A D C C lo c k
M U X 5 :0

O ld C h a n n e l

M U X 5 :0 in te rn a l

N ew C hannel

O ld C h a n n e l

N ew C hannel

A D IFADCH

S ig n a n d M S B o f R e s u lt

ADCL

L S B o f R e s u lt
tA S E T
A D C In p u t
C h a n n e l ischangedtC HD LY

C o n v e rs io n
C o m p le te

N e w C o n v e rs io n
c a n b e s ta rte dfro m h e reFigure 27-10. ADC Timing Diagram, Changing MUXn during a Conversion
C o n ve rs io n

A D C S e ttlin g

A D C C lo ck
M U X 5 :0
M U X 5 :0 in te rn a l

O ld C h a n n e l

N ew C hannel
O ld C h a n n e l

N ew C hannel

A D IFADCH

S ig n a n d M S B o f R e s u lt

ADCL

L S B o f R e s u lt
1 1 T A DC_C LK
C o n ve rs io n
C o m p le tetA S E T
tC H D L Y

A D C In p u t
C h a n n e l is
ch a n g e d

N e w C o n v e rsio n
c a n b e sta rte dfro m h e re27.6.3 ADC Voltage Reference
The reference voltage for the ADC (VREF) indicates the conversion range for the ADC.
Single ended channels that exceed VREF will result 0x3FF. VREF can be selected by the
REFSn bits in the ADMUX register as either AVDD (1.8V), internal 1.5V or 1.6V
reference or an external voltage at the AREF pin.
AVDD is connected to the ADC through a passive switch. The internal 1.5V and 1.6V
references are generated from a bandgap reference (VBG) through an amplifier. In
either case, the external AREF pin is directly connected to the ADC and the reference
voltage can be measured at the AREF pin with a high impedance voltmeter. Whenusing the internal 1.5V or 1.6V references no external de-coupling capacitor must beconnected to AREF. High capacitive loading will de-stabilize the internal voltage
amplifier. The 1.6V reference voltage is calibrated to an absolute accuracy of 1 LSB
during the manufacturing process.
If the user has a fixed voltage source connected to the AREF pin, the user may not use
the other reference voltage options in the application, as they will be shorted to theexternal voltage. An external reference voltage must be supplied with a very low
impedance RAREF,EXT (see "ADC Electrical Characteristics" on page 505). The load
current IL,AREF (see "ADC Electrical Characteristics" on page 505) seen by the externalsource is code dependent and changes (current steps) in the course of the successive
approximation process. If no external voltage is applied to the AREF pin, the user may
switch between AVDD, 1.5V and 1.6V as reference selection.
Changes of the reference selection bits REFSn will only take effect until the first
conversion start is requested by setting ADSC in ADCSRA. After this the ADC has to be
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disabled and enabled again for new reference selections. For internal references astable voltage is indicated by the REFOK bit in ADCSRB.

27.7 ADC Noise Canceller
The ADC features a noise canceller that enables conversion during sleep mode to
reduce noise induced from the CPU core and other I/O peripherals. The noise canceller
can be used with ADC Noise Reduction and Idle mode. To make use of this feature, thefollowing procedure should be used:
1. Make sure that the ADC is enabled and is not busy converting. Single Conversion
mode must be selected and the ADC Conversion Complete interrupt must be
enabled.
2. Enter ADC Noise Reduction mode (or Idle mode). The ADC will start a conversion
once the CPU has been halted.
3. If no other interrupts occur before the A/D conversion completes, the ADC interrupt
will wake up the CPU and execute the ADC Conversion Complete interrupt routine.
If another interrupt wakes up the CPU before the A/D conversion is complete, thatinterrupt will be executed, and an ADC Conversion Complete interrupt request will
be generated when the A/D conversion completes. The CPU will remain in activemode until a new sleep command is executed.
Note that the ADC will not be automatically turned off when entering other sleep modes
than Idle mode and ADC Noise Reduction mode. The user is advised to write zero to
ADEN before entering such sleep modes to avoid excessive power consumption.
27.7.1 Analog Input Circuitry
The analog input circuitry for single ended channels is illustrated in Figure 27-11 on
page 421. An analog source applied to ADCn is subjected to the pin capacitance andinput leakage of that pin, regardless of whether that channel is selected as input for the
ADC. When the channel is selected, the source must drive the S/H capacitor throughthe series resistance (combined resistance in the input path).
The ADC is optimized for analog signals having output impedance ZOUT of
approximately 3 kΩ or less. If such a source is used, the sampling time will be
negligible. If a source with higher impedance is used, the correct sampling time will
depend on how much time is needed to charge the S/H capacitor, which can vary
widely. The user is recommended to only use low impedance sources with slowly
varying signals, since this minimizes the required charge transfer to the S/H capacitor.
The required tracking time (input sampling switch closed) tDTRCK to settle to within 1 LSB
can be estimated tot DTRCK = ( Z OUT / kΩ + 2000) ⋅ 0.097ns
for ZOUT > 3kΩ (worst case: maximum input step). A minimum tracking time of 500ns isguaranteed by the conversion logic. Based on the ADC clock frequency the bits
ADTHT[1:0] of register ADCSRC allow the adjustment of the tracking time to the user’s
requirements.
Tracking time requirements should also be considered for the differential mode. The
input signal is sampled by the gain amplifier. The value of the input capacitance CS/H
depends on the selected gain (~7pF for 200x gain, <1pF otherwise). The tracking isequal to 50% of the clock period of CKADC2. Hence in differential mode a slower clock
frequency is required for input sources with high impedance.

420

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ATmega128RFA1
Figure 27-11. Analog Input Circuitry
I IH
2k
ADCn
C S /H = 1 4 p F

I IL
V A V D D /2

Signal components higher than the Nyquist frequency (fADC/2) should not be present foreither kind of channels, to avoid distortion from unpredictable signal convolution. The
user is advised to remove high frequency components with a low-pass filter before
applying the signals as inputs to the ADC.
27.7.2 Analog Noise Canceling Techniques
Digital circuitry inside and outside the device generates EMI which might affect theaccuracy of analog measurements. If conversion accuracy is critical, the noise level canbe reduced by applying the following techniques:
1. Keep analog signal paths as short as possible. Make sure analog tracks run over the
ground plane, and keep them well away from high-speed switching digital tracks.
2. Use the ADC noise canceller function to reduce induced noise from the CPU.
3. If any ADC port pins are used as digital outputs, it is essential that these do notswitch while a conversion is in progress.
27.7.3 Offset Compensation Schemes
The differential amplifier has a built-in offset cancellation circuitry that nulls the offset ofdifferential measurements as much as possible. The remaining offset in the analog pathcan be measured directly by selecting the same channel for both differential inputs. This
offset residue can then be subtracted in software from the measurement results. The
offset on any channel can be reduced below one LSB using this kind of software based
offset correction.
27.7.4 ADC Accuracy Definitionsn

An n-bit single-ended ADC converts a voltage linearly between 0V and VREF in 2 stepsn(LSB’s). The lowest code is read as 0, and the highest code is read as 2 -1.
Several parameters describe the deviation from the ideal behavior:• Offset: The deviation of the first transition (0x000 to 0x001) compared to the idealtransition (at 0.5 LSB). Ideal value: 0 LSB.

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Figure 27-12. Offset Error
Output CodeIdeal ADC
Actual ADC

OffsetError

VREF Input Voltage• Gain Error: After adjusting for offset, the Gain Error is found as the deviation of thelast transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below
maximum). Ideal value: 0 LSB.
Figure 27-13. Gain Error
Output Code

Gain
Error

Ideal ADC
Actual ADC

VREF Input Voltage• Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the
maximum deviation of an actual transition compared to an ideal transition for any
code. Ideal value: 0 LSB.

422

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ATmega128RFA1
Figure 27-14. Integral Non-linearity (INL)
Output CodeINL
Ideal ADC
Actual ADC

VREF

Input Voltage• Differential Non-linearity (DNL): The maximum deviation of the actual code width(the interval between two adjacent transitions) from the ideal code width (1 LSB).
Ideal value: 0 LSB.
Figure 27-15. Differential Non-linearity (DNL)
Output Code
0x3FF

1 LSB

DNL

0x000
0

VREF Input Voltage• Quantization Error: Due to the quantization of the input voltage into a finite numberof codes, a range of input voltages (1 LSB wide) will code to the same value. It isalways ±0.5 LSB.
• Absolute Accuracy: The maximum deviation of an actual (unadjusted) transition
compared to an ideal transition for any code. This is the compound effect of offset,
gain error, differential error, non-linearity, and quantization error. Ideal value: ±0.5
LSB.

27.8 ADC Conversion Result
After the conversion is complete (ADIF is high), the conversion result can be found in
the ADC Result Registers (ADCL, ADCH).

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For single ended conversion, the result is

ADC =VIN ⋅1024
VREF

where VIN is the voltage on the selected input pin and VREF the selected voltage
reference (see "Table 27-10" on page 427 and "Table 27-11" on page 428). 0x000
represents analog ground, and 0x3FF represents the selected reference voltage minus
one LSB.
If differential channels are used, the result is

ADC =(VPOS − VNEG ) ⋅ GAIN ⋅ 512
VREF

where VPOS is the voltage on the positive input pin, VNEG the voltage on the negative
input pin, and VREF the selected voltage reference. The result is presented in two’s
complement form, from 0x200 (-512d) through 0x1FF (+511d). Note that if the user
wants to perform a quick polarity check of the result, it is sufficient to read the MSB ofthe result (ADC9 in ADCH). If the bit is one, the result is negative, and if this bit is zero,
the result is positive. Figure 27-16 below shows the decoding of the differential input
range.
Table 27-7 on page 425 shows the resulting output codes if the differential input
channel pair (ADCn - ADCm) is selected with a gain of GAIN and a reference voltage of
VREF.
Figure 27-16. Differential Measurement Range
Output code
0x1FF

0x000
- V REF/GAIN

0x3FF

0

VREF/GAIN

Differential Input
voltage (Volts)

0x200

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ATmega128RFA1
Table 27-7. Correlation Between Input Voltage and Output Codes
VADCn

Read CodeCorresponding Decimal Value

VADCm + VREF / GAIN

0x1FF

511

VADCm + 0.999 VREF / GAIN

0x1FF

511

VADCm + 0.998 VREF / GAIN

0x1FE

510

…

…

…

VADCm + 0.001 VREF / GAIN

0x001

1

VADCm

0x000

0

VADCm - 0.001 VREF / GAIN

0x3FF

-1

…

…

…

VADCm - 0.999 VREF / GAIN

0x201

-511

VADCm - VREF / GAIN

0x200

-512

Example:ADMUX = 0xED (ADC3 - ADC2, 10x gain, 1.6V reference, left adjusted result)
The voltage on ADC3 is 300 mV; the voltage on ADC2 is 425 mV.
ADCR = 512 * 10 * (300 - 425) / 1600 = -400 = 0x270.
ADCL will thus read 0x00, and ADCH will read 0x9C. Writing zero to ADLAR rightadjusts the result: ADCL = 0x70, ADCH = 0x02.

27.9 Internal Temperature Measurement
The on-chip temperature can be measured using a special setup of the A/D converter
inputs. The integrated temperature sensor provides a linear, medium-accurate voltage
proportional to the absolute temperature (in Kelvin). This voltage is first amplified withthe programmable gain amplifier and then processed with the A/D converter. A low
frequency of the conversion clock must be selected due to the nature of the input
signal. The absolute accuracy of the temperature measurement is limited bymanufacturing tolerances, noise from supply and ground voltages and the exactness of
the reference voltage. The following table summarizes the preferred setup of thetemperature measurement:
Table 27-8. Recommended ADC Setup for Temperature Measurement
Parameter

Register

Recommended Setup

ADC Channel

ADMUX,ADCSRB

Select the Temperature Sensor, MUX4:0 = 01001;
MUX5 = 1;

ADC Clock

ADCSRA

Select a clock frequency of 500kHz or lower;

VREF

ADMUX

Select the internal 1.6V reference voltage;

Start-up time

ADCSRCStandard requirement of 20µs is sufficient;

Tracking time

ADCSRC

Setting ADTHT = 0 is sufficient;

The A/D conversion result ADCTEMP will always be a positive number. The ideal result
can be calculated when using the internal 1.6V reference voltage according to thefollowing equation:

ADCTEMP = 241.4 + 0.885 ⋅ θ / °C
Similar the Celsius-temperature θ can be extracted from the A/D conversion result withthis formula:

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θ / °C = 1.13 ⋅ ADCTEMP − 272.8
Note that the above equations are only valid in the allowed operating temperature
range. The translation of the A/D measurement result to a Celsius-temperature value
can be easily achieved with a look-up table in software. The accuracy of thetemperature reading can be improved by averaging of multiple A/D conversion results.
In this way the impact of noise is reduced. The temperature sensor is connected to adifferential input channel with a gain of 10. The offset error of the channel can becorrected to the first order by using an appropriate channel (e.g. MUX4:0=01000,
MUX5=0, see Table 27-11 on page 428). The in that manner measured error of thedifferential signal processing is then subtracted from the temperature sensor ADC
reading.
Note that changing between the temperature sensor channel and the channel for theoffset error correction can lead to a large difference of the analog input voltage.
Therefore it is recommended to disable the ADC, select the new channel and thenenable the ADC again.

27.10 SRAM DRT Voltage Measurement
The decrease of the supply voltage of SRAM block 2 for the leakage current reduction
can also be measured using a special setup of the A/D converter inputs. The details of
the SRAM leakage current reduction are described in section "SRAM with Data
Retention" on page 163. The supply voltage of a disabled SRAM block can be reduced
to save leakage power while maintaining data retention. This feature applies to all four
SRAM blocks however only the voltage of SRAM block 2 can be verified using the A/D
converter.
The default factory setting for the data retention (DRT) voltage normally guarantees thebest leakage performances. Other values are nevertheless possible and can beselected by the application software. The true value of the supply voltage reduction isdepending on the manufacturing process and environmental conditions like
temperature. The A/D converter allows determining the value of the DRT voltage of
SRAM block 2. The same voltage setting results for all practical purposes in the same
supply voltage for all other SRAM blocks.
Care must be taken when verifying the DRT voltage of SRAM block 2 with the A/D
converter because it will be put into sleep mode and hence it is not available for theapplication program. Addressing the disabled SRAM will return invalid data (all dataread zero). The voltage measurement is split into two parts. One setting allows
measuring the voltage drop from DVDD. The other setting allows verifying the voltage
shift from DVSS. Both measurements are differential and use the programmable gain
amplifier. A low frequency of the conversion clock must be selected due to the highimpedance nature of the input signal. Accurate and stable voltage readings may just be
available after a long waiting time of up to 100 ms. This limitation is the consequence ofthe small leakage currents that discharge the internal de-coupling capacitances before
the supply voltage settles to the DRT value. The following table summarizes thepreferred setup of the DRT voltage measurement:
Table 27-9. Recommended ADC Setup for DRT Voltage Measurements

426

Parameter

Register

Recommended Setup

SRAM DRT on

DRTRAM2

Set bits DISPC and ENDRT to 1;

ADC Channel

ADMUX,

Select MUX4:0 = 10100 to measure VDRTBBP;
Select MUX4:0 = 11101 to measure VDRTBBN;

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ATmega128RFA1
Parameter

Register

Recommended Setup

ADCSRBMUX5 = 1;

ADC Clock

ADCSRA

Select a clock frequency of 500kHz or lower;

VREF

ADMUX

Select the internal 1.6V reference voltage;

Start-up time

ADCSRCStandard requirement of 20µs is sufficient;

Tracking time

ADCSRC

Setting ADTHT = 0 is sufficient;

The A/D conversion result will always be a positive number for both VDRTBBP and
VDRTBBN. The SRAM supply voltage is easily calculated according to the following
equation (see chapter "SRAM with Data Retention" on page 163):

VDD, SRAM , DRT = VDD − (VDRTBBP + VDRTBBN )The conversion result is coded as described in "ADC Conversion Result" on page 423
with a GAIN of 0.5. It is not possible to read both VDRTBBP and VDRTBBN at the same time.
However the time required for the A/D conversion is short compared to the time
constant of a DRT voltage change.

27.11 Register Description
27.11.1 ADMUX – ADC Multiplexer Selection Register
Bit

7

6

5

4

3

2

1

0

NA ($7C)

REFS1

REFS0

ADLAR

MUX4

MUX3

MUX2

MUX1

MUX0

Read/Write
Initial Value

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

ADMUX

• Bit 7:6 – REFS1:0: Reference Selection Bits
These bits select the voltage reference for the ADC, as shown in the following table.
Changes of these bits will only take effect until the first conversion start is requested by
setting ADSC. After this the ADC has to be disabled and enabled again for new
reference selections. The internal voltage reference options may not be used if anexternal reference voltage is being applied to the AREF pin.
Table 27-10. Reference Voltage Selections for ADC
REFS1

REFS0

Reference Voltage Selection

00

AREF, Internal VREF turned off

0

1

AVDD (1.8V)

10Internal 1.5V Voltage Reference (no external capacitor at AREF pin)1

1Internal 1.6V Voltage Reference (no external capacitor at AREF pin)

• Bit 5 – ADLAR: ADC Left Adjust Result
The ADLAR bit affects the presentation of the A/D conversion result in the ADC Data
Register. Write one to ADLAR to left adjust the result. Otherwise, the result is rightadjusted. Changing the ADLAR bit will affect the ADC Data Register immediately,
regardless of any ongoing conversions. For a complete description of this bit, see"ADCL and ADCH – The ADC Data Register" on page 432.
• Bits 4:0 – MUX4:0: Analog Channel and Gain Selection Bits
The value of these bits selects which combination of analog inputs is connected to the
ADC. See Table 27-11 on page 428 for details. If these bits are changed during a
conversion, the change will not go in effect until this conversion is complete (ADIF in
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8266A-MCU Wireless-12/09

ADCSRA is set). Note that the MUX5 bit is located in the ADCSRB register. A write
access to the MUX4:0 bits triggers the update of the internally buffered MUX5 bit, see"Accessing the ADMUX Register" on page 417 .
27.11.2 ADCSRB – ADC Control and Status Register B
Bit

7

6

5

4

3

2

1

0

NA ($7B)

AVDDOK

ACME

REFOK

ACCH

MUX5

ADTS2

ADTS1

ADTS0

Read/Write
Initial Value

R
0

R/W
0

R
0

R/W
0

R/W
0

R/W
0

R/W
0

R/W
0

ADCSRB• Bit 7 – AVDDOK: AVDD Supply Voltage OK
The analog functions of the ADC are powered from the AVDD domain. AVDD is
supplied from an internal voltage regulator. Setting the ADEN bit in register ADCSRA
will power-up the AVDD domain if not already requested by another functional group of
the device. The bit allows the user to monitor (poll) the status of the AVDD domain. A
status of 1 indicates that AVDD has been powered-up.
• Bit 6 – ACME: Analog Comparator Multiplexer Enable
This bit is used for the Analog Comparator only. See "ADCSRB – ADC Control andStatus Register B" on page 409 for details.
• Bit 5 – REFOK: Reference Voltage OK
The status of the internal generated reference voltage can be monitored through thisbit. Setting the ADEN bit in register ADCSRA will enable the reference voltage for the
ADC according to the REFSn bits in the ADMUX register. The reference voltage will beavailable after a start-up delay. A REFOK value of 1 indicates that the internal
generated reference voltage is approaching final levels.
• Bit 4 – ACCH: Analog Channel Change
The user can force a reset of the analog blocks by setting this bit to 1 without
requesting a different channel. The analog blocks of the ADC will be reset to handle
possible new voltage ranges. Such a reset phase is especially important for the gain
amplifier. It could be temporarily disabled by a large step of its input common voltage
leading to erroneous A/D conversion results. ACCH will read as one until the reset
phase of the analog blocks can be entered.
• Bit 3 – MUX5: Analog Channel and Gain Selection Bit
This bit is used together with MUX4:0 in ADMUX to select the analog input signals
connected to the ADC. See the following table for details. If this bit is changed during a
conversion, the change will not go in effect until this conversion is complete. Note that
the MUX5 bit is internally buffered and a write access to the MUX4:0 bits is required totrigger the update of the MUX5 bit, see "Accessing the ADMUX Register" on page 417 .
Table 27-11. Input Channel Selections
MUX5:0428

Single Ended
Input

000000ADC0000001ADC1000010ADC2000011ADC3000100ADC4000101ADC5Positive Differential
Input

Negative Differential
Input

Gain

N/A

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ATmega128RFA1
Positive Differential
Input

Negative Differential
Input

Gain

001000

ADC0

ADC0

10x

001001

ADC1

ADC0

10x

001010

ADC0

ADC0

200x

ADC1

ADC0

200x

ADC2

ADC2

10x

001101

ADC3

ADC2

10x

001110

ADC2

ADC2

200x

001111

ADC3

ADC2

200x

010000

ADC0

ADC1

1x

010001

ADC1

ADC1

1x

010010

ADC2

ADC1

1x

ADC3

ADC1

1x

ADC4

ADC1

1x

010101

ADC5

ADC1

1x

010110

ADC6

ADC1

1x

010111

ADC7

ADC1

1x

011000

ADC0

ADC2

1x

011001

ADC1

ADC2

1x

011010

ADC2

ADC2

1x

ADC3

ADC2

1x

011100

ADC4

ADC2

1x

011101

ADC5

ADC2

1x

MUX5:0Single Ended
Input

000110ADC6000111ADC7001011001100010011010100011011

N/A

N/A

N/A

0111101.2V (VBG)

0111110V (AVSS)

100000Reserved

100001

Reserved

100010Reserved

100011

Reserved

100100Reserved

100101

Reserved

100110Reserved

100111

Reserved

101000

N/A

N/A

N/A

Reserved

101001

Temperature Sensor

101010Reserved

101011

Reserved

101100Reserved

101101

Reserved

101110Reserved

429
8266A-MCU Wireless-12/09

Single Ended
Input

MUX5:0

Positive Differential
Input

Negative Differential
Input

101111

Reserved

110000Reserved

110001

Reserved

110010Reserved

110011

Reserved

N/A

110100SRAM Back-bias Voltage VDRTBBP

110101

Reserved

110110Reserved

110111

Reserved

111000Reserved

111001

Reserved

111010Reserved

N/A

111011

Reserved

111100Reserved

111101

SRAM Back-bias Voltage VDRTBBN

111110Reserved

111111

Reserved

Gain

N/A

• Bits 2:0 – ADTS2:0: ADC Auto Trigger Source
If ADATE in ADCSRA is written to one, the value of these bits selects which source will
trigger an A/D conversion. If ADATE is cleared, the ADTS2:0 settings will have noeffect. A conversion will be triggered by the rising edge of the selected Interrupt Flag.
Note that switching from a trigger source that is cleared, to a trigger source that is set,
will generate a positive edge on the trigger signal. If ADEN in ADCSRA is set, this will
start a conversion. Switching to Free Running mode (ADTS2:0=0) will not cause a
trigger event, even if the ADC Interrupt Flag is set.
Table 27-12. ADC Auto Trigger Source Selections
ADTS2

ADTS1

ADTS0

Trigger Source

0

0

0

Free Running mode

0

0

1

Analog Comparator

0

1

0

External Interrupt Request 0

0

1

1

Timer/Counter0 Compare Match A

1

0

0

Timer/Counter0 Overflow

1

0

1

Timer/Counter1 Compare Match B

1

1

0

Timer/Counter1 Overflow

1

1

1

Timer/Counter1 Capture Event

27.11.3 ADCSRA – ADC Control and Status Register A
Bit

430

7

6

5

4

3

2

1

0

NA ($7A)

ADEN

ADSC

ADATE

ADIF

ADIE

ADPS2

ADPS1

ADPS0

Read/Write
Initial Value

R/W
0

R/W
0

R/W
0

R/W
0

R/W
0

R/W
0

R/W
0

R/W
0

ADCSRA

ATmega128RFA1
8266A-MCU Wireless-12/09

ATmega128RFA1• Bit 7 – ADEN: ADC Enable
Writing this bit to one enables the ADC. The AVDD supply voltage will also be enabled
if not already available. By writing it to zero, the ADC is turned off. Turning the ADC off
while a conversion is in progress will terminate this conversion.
• Bit 6 – ADSC: ADC Start Conversion
In Single Conversion mode, write this bit to one to start each conversion. In Free
Running mode, write this bit to one to start the first conversion. The first conversion
after ADSC has been written after the ADC has been enabled, or if ADSC is written at
the same time as the ADC is enabled, will include a start-up time to initialize the analog
blocks of the ADC. The start-up time is defined by the ADSUT bits of register ADCSRC.
ADSC will read as one as long as a conversion is in progress. When the conversion iscomplete, it returns to zero. Writing zero to this bit has no effect.
• Bit 5 – ADATE: ADC Auto Trigger Enable
When this bit is written to one, Auto Triggering of the ADC is enabled. The ADC will
start a conversion on a positive edge of the selected trigger signal. The trigger source isselected by setting the ADC Trigger Select bits, ADTS in ADCSRB.
• Bit 4 – ADIF: ADC Interrupt Flag
This bit is set when an A/D conversion is completed and the Data Register are updated.
The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in
SREG are set. ADIF is cleared by hardware when executing the corresponding interrupt
handling vector. Alternatively, ADIF is cleared by writing a logical one to the flag.
Beware that if doing a Read-Modify-Write on ADCSRA, a pending interrupt can bedisabled. This also applies if the SBI and CBI instructions are used.
• Bit 3 – ADIE: ADC Interrupt Enable
When this bit is written to one and the I-bit in SREG is set, the ADC Conversion
Complete Interrupt is activated.
• Bits 2:0 – ADPS2:0: ADC Prescaler Select Bits
These bits determine the division factor between the CPU frequency and the input clock
to the ADC.
Table 27-13. ADC Prescaler Selections
ADPS2

ADPS1

ADPS0

Division Factor

0

0

0

2

0

0

1

2

0

1

0

4

0

1

1

8

1

0

0

16

1

0

1

32

1

1

0

64

1

1

1

128

27.11.4 ADCSRC – ADC Control and Status Register C
Bit
NA ($77)
Read/Write
Initial Value

7

6

ADTHT1 ADTHT0
RW
0

RW
1

5

Res0
RW
0

4

3

2

1

0

ADSUT4 ADSUT3 ADSUT2 ADSUT1 ADSUT0
RW
1

RW
0

RW
1

RW
0

ADCSRC

RW
0

431
8266A-MCU Wireless-12/09

This register defines the track-and-hold time for sampling the analog input voltage of
the ADC and it defines the start-up time for the analog blocks based on a number of
ADC clock cycles. The ADC clock is generated from the system clock with the ADC
prescaler. The bits ADPS2:0 of register ADCSRA set the prescaler ratio. Correct startup and track-and-hold times are important for precise conversion results.
• Bits 7:6 – ADTHT1:0: ADC Track-and-Hold Time
These bits define the number of ADC clock cycles for the sampling time of the analog
input voltage. For a complete description of this bit, see "Pre-scaling and Conversion
Timing" on page 413.
• Bit 5 – Res0: Reserved• Bits 4:0 – ADSUT4:0: ADC Start-up Time
These bits define the number of ADC clock cycles for the start-up time of the analog
blocks. For a complete description of this bit, see "Pre-scaling and Conversion Timing"on page 413.
27.11.5 ADCL and ADCH – The ADC Data Register
27.11.5.1 ADLAR = 0
Bit

15

14

13

12

11

10

9

8

NA ($79)

–

–

–

–

–

–

ADC9

ADC8

ADCH

NA ($78)

ADC7

ADC6

ADC5

ADC4

ADC3

ADC2

ADC1

ADC0

ADCL

Read/Write

7
R

6
R

5
R

4
R

3
R

2
R

1
R

0
R

R

R

R

R

R

R

R

R

Initial Value

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit

15

14

13

12

11

10

9

8

NA ($79)

ADC9

ADC8

ADC7

ADC6

ADC5

ADC4

ADC3

ADC2

ADCH

NA ($78)

ADC1

ADC0

–

–

–

–

–

–

ADCL

Read/Write

7
R

6
R

5
R

4
R

3
R

2
R

1
R

0
R

R

R

R

R

R

R

R

R

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

27.11.5.2 ADLAR = 1

Initial Value

When an A/D conversion is complete, the result is found in these two registers. If
differential channels are used, the result is presented in two’s complement form.
When ADCL is read, the ADC Data Register is not updated until ADCH is read.
Consequently, if the result is left adjusted and no more than 8-bit precision (7 bit + sign
bit for differential input channels) is required, it is sufficient to read ADCH. Otherwise,
ADCL must be read first, then ADCH.
The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result isread from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared(default), the result is right adjusted.

432

ATmega128RFA1
8266A-MCU Wireless-12/09

ATmega128RFA1• ADC9:0: A/D Conversion Result
These bits represent the result from the conversion as detailed in "ADC Conversion
Result" on page 423.
27.11.6 DIDR0 – Digital Input Disable Register 0
Bit

7

6

5

4

3

2

1

0

NA ($7E)

ADC7D

ADC6D

ADC5D

ADC4D

ADC3D

ADC2D

ADC1D

ADC0D

Read/Write
Initial Value

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

RW
0

DIDR0

• Bits 7:0 – ADC7D:ADC0D: Digital Input Disable
When this bit is written logic one, the digital input buffer on the corresponding ADC pin
is disabled. The corresponding PIN Register bit will always read as zero when this bit isset. When an analog signal is applied to the ADC7:0 pin and the digital input from thispin is not needed, this bit should be written logic one to reduce power consumption in
the digital input buffer.
27.11.7 DIDR2 – Digital Input Disable Register 2
Bit
NA ($7D)
Read/Write
Initial Value

7

6

5

4

3

2

ADC15D ADC14D ADC13D ADC12D ADC11D ADC10D
RW
0

RW
0

RW
0

RW
0

RW
0

1

0

ADC9D

ADC8D

RW
0

RW
0

RW
0

DIDR2

Reserved for future use.
• Bit 7:0 – ADC15D:ADC8D - Reserved Bits
This bit is reserved for future use. For ensuring compatibility with future devices, this bit
must be written to zero.

27.11.8 BGCR – Reference Voltage Calibration Register
Bit

7

6

5

4

NA ($67)Res

BGCAL_FINE3BGCAL_FINE2BGCAL_FINE1

Read/Write
Initial Value

R
0

RW
0

RW
0

RW
0

Bit

3

2

1

0

NA ($67)

BGCAL_FINE0BGCAL2BGCAL1BGCAL0

Read/Write
Initial Value

RW
0

RW
0

RW
0

RW
0

BGCR

BGCR

This register contains the calibration values of the reference voltage of the ADC. The
values are loaded from the fuse memory after power-up. They can be corrected by theapplication software e.g. to compensate for temperature changes. The internal 1.6V
reference voltage is calibrated and has therefore the highest accuracy compared to the
1.5V or AVDD reference.
• Bit 7 – Res - Reserved Bit
This bit is reserved for future use. A read access always will return zero. A write accessdoes not modify the content.
433
8266A-MCU Wireless-12/09

• Bit 6:3 – BGCAL_FINE3:0 - Fine Calibration Bits
These bits allow the calibration of the AREF voltage with a resolution of 2mV.
Table 27-14 BGCAL_FINE Register Bits
Register Bits
BGCAL_FINE3:0

Value

Description

0Center value

1

Voltage step up

8Voltage step down

7

Setting for highest voltage

15

Setting for lowest voltage• Bit 2:0 – BGCAL2:0 - Coarse Calibration Bits
These bits allow the calibration of the AREF voltage with a resolution of 10mV.
Table 27-15 BGCAL Register Bits
Register Bits
BGCAL2:0

434

Value

Description

4

Center value

3

Voltage step up

5

Voltage step down0

Setting for highest voltage

7

Setting for lowest voltage

ATmega128RFA1
8266A-MCU Wireless-12/09

ATmega128RFA1
28 JTAG Interface and On-chip Debug System
28.1 Features• JTAG (IEEE std. 1149.1 Compliant) Interface• Boundary-scan Capabilities According to the IEEE std. 1149.1 (JTAG)
Standard• Debugger Access to:o All Internal Peripheral Unitso Internal and External RAM
o The Internal Register File–Program Countero EEPROM and Flash Memories• Extensive on-chip debug Support for Break Conditions, Including
o AVR Break Instructiono Break on Change of Program Memory Flowo Single Step Breako Program Memory Breakpoints on Single Address or Address Rangeo Data Memory Breakpoints on Single Address or Address Range• Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAGInterface• On-chip debugging Supported by AVR Studio®

28.2 Overview
The AVR IEEE std. 1149.1 compliant JTAG interface can be used for• Testing PCBs by using the JTAG Boundary-scan capability• Programming the non-volatile memories, Fuses and Lock bits
• On-chip debugging
A brief description is given in the following sections. Detailed descriptions for
Programming via the JTAG interface, and using the Boundary-scan Chain can be foundin the sections "Programming via the JTAG Interface" on page 481 and "Programming
via the JTAG Interface" on page 481, respectively. The on-chip debug support isconsidered being private JTAG instructions, and distributed within ATMEL and toselected third party vendors only.
Figure 28-1 on page 436 shows a block diagram of the JTAG interface and the on-chip
debug system. The TAP Controller is a state machine controlled by the TCK and TMS
signals. The TAP Controller selects either the JTAG Instruction Register or one ofseveral Data Registers as the scan chain (Shift Register) between the TDI – input and
TDO – output. The Instruction Register holds JTAG instructions controlling the behaviorof a Data Register.
The ID-Register, Bypass Register, and the Boundary-scan Chain are the Data
Registers used for board-level testing. The JTAG Programming Interface (actuallyconsisting of several physical and virtual Data Registers) is used for serial programming
via the JTAG interface. The internal scan-chain and breakpoint scan-chain are used foron-chip debugging only.

435
8266A-MCU Wireless-12/09

Figure 28-1. Block Diagram
I/O PORT 0

DEVICE BOUNDARYBOUNDARY SCAN CHAIN

TDI
TDO
TCK
TMS

JTAG PROGRAMMING
INTERFACETAP
CONTROLLERFLASHMEMORYINSTRUCTIONREGISTERID
REGISTER
M
U
X

Address
Data

BREAKPOINTUNIT

BYPASSREGISTERINTERNAL
SCAN
CHAIN

AVR CPUPC
Instruction

FLOW CONTROLUNIT
DIGITALPERIPHERALUNITSANALOGPERIPHERIAL
UNITS

Analog inputs

BREAKPOINT
SCAN CHAIN
ADDRESSDECODERJTAG / AVR CORE
COMMUNICATIONINTERFACE

OCD STATUS
AND CONTROL

Control & Clock lines

I/O PORT n

28.3 TAP - Test Access Port
The JTAG interface is accessed through four of the AVR’s pins. In JTAG terminology,
these pins constitute the Test Access Port – TAP. These pins are:
• TMS: Test mode select. This pin is used for navigating through the TAP-controller
state machine.
• TCK: Test Clock. JTAG operation is synchronous to TCK.
• TDI: Test Data In. Serial input data to be shifted in to the Instruction Register or Data
Register (Scan Chains).
• TDO: Test Data Out. Serial output data from Instruction Register or Data Register.
The IEEE std. 1149.1 also specifies an optional TAP signal; TRST – Test ReSeT –which is not provided.
When the JTAGEN Fuse is un-programmed, these four TAP pins are normal port pins,
and the TAP controller is in reset. When programmed the input TAP signals areinternally pulled high and the JTAG is enabled for Boundary-scan and programming.
The device is shipped with this fuse programmed.
For the on-chip debug system, in addition to the JTAG interface pins, the RESET pin ismonitored by the debugger to be able to detect external reset sources. The debugger
can also pull the RESET pin low to reset the whole system, assuming only open
collectors on the reset line are used in the application.

436

ATmega128RFA1
8266A-MCU Wireless-12/09

ATmega128RFA1
Figure 28-2. TAP Controller State Diagram1

Test-Logic-Reset
00

Run-Test/Idle

1

Select-DR Scan

1

Select-IR Scan

0
1

0
1

Capture-DR

Capture-IR00

Shift-DR

0

1
1

Exit1-DR1

Exit1-IR

0

0

Pause-DR

0

0

Pause-IR1

1
0

Exit2-DR

Exit2-IR1

1

Update-DR
10

Shift-IR1

01

Update-IR01028.4 TAP Controller
The TAP controller is a 16-state finite state machine that controls the operation of theBoundary-scan circuitry, JTAG programming circuitry, or on-chip debug system. The
state transitions depicted in Figure 28-2 above depend on the signal present on TMS(shown adjacent to each state transition) at the time of the rising edge at TCK. The
initial state after a Power-on Reset is Test-Logic-Reset.
As a definition in this document, the LSB is shifted in and out first for all Shift Registers.
Assuming Run-Test/Idle is the present state, a typical scenario for using the JTAG
interface is:• At the TMS input, apply the sequence 1, 1, 0, 0 at the rising edges of TCK to enter
the Shift Instruction Register – Shift-IR state. While in this state, shift the four bits of
the JTAG instructions into the JTAG Instruction Register from the TDI input at therising edge of TCK. The TMS input must be held low during input of the 3 LSBs inorder to remain in the Shift-IR state. The MSB of the instruction is shifted in when
this state is left by setting TMS high. While the instruction is shifted in from the TDI
pin, the captured IR-state 0x01 is shifted out on the TDO pin. The JTAG Instruction

437
8266A-MCU Wireless-12/09

selects a particular Data Register as path between TDI and TDO and controls thecircuitry surrounding the selected Data Register.
• Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. The instruction
is latched onto the parallel output from the Shift Register path in the Update-IR state.
The Exit-IR, Pause-IR, and Exit2-IR states are only used for navigating the statemachine.
• At the TMS input, apply the sequence 1, 0, 0 at the rising edges of TCK to enter the
Shift Data Register – Shift-DR state. While in this state, upload the selected Data
Register (selected by the present JTAG instruction in the JTAG Instruction Register)from the TDI input at the rising edge of TCK. In order to remain in the Shift-DR state,
the TMS input must be held low during input of all bits except the MSB. The MSB ofthe data is shifted in when this state is left by setting TMS high. While the Data
Register is shifted in from the TDI pin, the parallel inputs to the Data Register
captured in the Capture-DR state is shifted out on the TDO pin.
• Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. If the selected
Data Register has a latched parallel-output, the latching takes place in the UpdateDR state. The Exit-DR, Pause-DR, and Exit2-DR states are only used for navigating
the state machine.
As shown in the state diagram, the Run-Test/Idle state need not be entered between
selecting JTAG instruction and using Data Registers, and some JTAG instructions may
select certain functions to be performed in the Run-Test/Idle, making it unsuitable as an
Idle state.
Note that independent of the initial state of the TAP Controller, the Test-Logic-Resetstate can always be entered by holding TMS high for five TCK clock periods. For
detailed information on the JTAG specification, refer to the literature listed in"Bibliography" on page 440.

28.5 Using the Boundary-scan Chain
A complete description of the Boundary-scan capabilities are given in the section "IEEE1149.1 (JTAG) Boundary-scan" on page 441.

28.6 Using the On-chip Debug System
As shown in Figure 28-1, the hardware support for on-chip debugging consists mainlyof• A scan chain on the interface between the internal AVR CPU and the internal
peripheral units.
• Breakpoint unit.
• Communication interface between the CPU and JTAG system.
All read or modify/write operations needed for implementing the debugger are done by
applying AVR instructions via the internal AVR CPU Scan Chain. The CPU sends theresult to an I/O memory mapped location which is part of the communication interface
between the CPU and the JTAG system.
The Breakpoint Unit implements Break on Change of Program Flow, Single Step Break,two program memory breakpoints and two combined breakpoints. Together, the four
breakpoints can be configured as either:• 4 single program memory breakpoints;• 3 single program memory breakpoint + 1 single data memory breakpoint;• 2 single program memory breakpoints + 2 single data memory breakpoints;

438

ATmega128RFA1
8266A-MCU Wireless-12/09

ATmega128RFA1• 2 single program memory breakpoints + 1 program memory breakpoint with mask(“range breakpoint”).
• 2 single program memory breakpoints + 1 data memory breakpoint with mask(“range breakpoint”).
A debugger, like the AVR Studio, may however use one or more of these resources for
its internal purpose, leaving less flexibility to the end-user.
A list of the on-chip debug specific JTAG instructions is given in "On-chip Debug
Specific JTAG Instructions" below.
The JTAGEN Fuse must be programmed to enable the JTAG Test Access Port. In
addition, the OCDEN Fuse must be programmed and no Lock bits must be set for the
on-chip debug system to work. As a security feature, the on-chip debug system isdisabled when either of the LB1 or LB2 Lock-bits are set. Otherwise, the on-chip debug
system would have provided a back-door into a secured device.
The AVR Studio enables the user to fully control execution of programs on an AVR
device with on-chip debug capability, AVR In-Circuit Emulator, or the built-in AVR
Instruction Set Simulator. AVR Studio supports source level execution of Assembly
programs assembled with Atmel Corporation’s AVR Assembler and C programs
compiled with third party vendors’ compilers. For a full description of the AVR Studio,
please refer to the AVR Studio User Guide. Only highlights are presented in thisdocument.
All necessary execution commands are available in AVR Studio, both on source leveland on disassembly level. The user can execute the program, single step through thecode either by tracing into or stepping over functions, step out of functions, place thecursor on a statement and execute until the statement is reached, stop the execution,and reset the execution target. In addition, the user can have an unlimited number ofcode breakpoints (using the BREAK instruction) and up to two data memory
Breakpoints, alternatively combined as a mask (range) breakpoint.

28.7 On-chip Debug Specific JTAG Instructions
The on-chip debug support is considered being private JTAG instructions, anddistributed within ATMEL and to selected third party vendors only. Instruction operation
codes are listed for reference.
28.7.1 PRIVATE0; 0x8
Private JTAG instruction for accessing on-chip debug system;
28.7.2 PRIVATE1; 0x9
Private JTAG instruction for accessing on-chip debug system;
28.7.3 PRIVATE2; 0xA
Private JTAG instruction for accessing on-chip debug system;
28.7.4 PRIVATE3; 0xB
Private JTAG instruction for accessing on-chip debug system;

28.8 Using the JTAG Programming Capabilities
Programming of the ATmega128RFA1 via JTAG is performed via the 4-pin JTAG port,
TCK, TMS, TDI, and TDO. These are the only pins that need to be controlled andobserved to perform JTAG programming (in addition to power pins). The JTAGEN Fusemust be programmed and the JTD bit in the MCUCR Register must be cleared toenable the JTAG Test Access Port.
439
8266A-MCU Wireless-12/09

The JTAG programming capability supports:• Flash programming and verifying.
• EEPROM programming and verifying.
• Fuse programming and verifying.
• Lock bit programming and verifying.
The Lock bit security is exactly as in parallel programming mode. If the Lock bits LB1 or
LB2 are programmed, the OCDEN Fuse cannot be programmed unless first doing achip erase. This is a security feature that ensures no back-door exists for reading out
the content of a secured device.
The details on programming through the JTAG interface and programming specific
JTAG instructions are given in the section "Programming via the JTAG Interface" onpage 481.

28.9 Bibliography
For more information about general Boundary-scan, the following literature can be
consulted:• IEEE: IEEE Std. 1149.1-1990. IEEE Standard Test Access Port and Boundary-scan
Architecture, IEEE, 1993.
• Colin Maunder: The Board Designers Guide to Testable Logic Circuits, AddisonWesley, 1992.

28.10 On-chip Debug Related Register in I/O Memory
28.10.1 OCDR – On-Chip Debug Register
Bit

7

6

5

$31 ($51)
Read/Write
Initial Value

4

3

2

1

0

OCDR7:0
RW
0

RW
0

RW
0

RW
0

RW
0

OCDR
RW
0

RW
0

RW
0

The OCDR Register provides a communication channel from the running program in
the microcontroller to the debugger. The CPU can transfer a byte to the debugger by
writing to this location. At the same time, an internal flag; I/O Debug Register Dirty
IDRD is set to indicate to the debugger that the register has been written. When the
CPU reads the OCDR Register the 7 LSB will be from the OCDR Register, while the
MSB is the IDRD bit. The debugger clears the IDRD bit when it has read theinformation. In some AVR devices, this register is shared with a standard I/O location.
In this case, the OCDR Register can only be accessed if the OCDEN Fuse isprogrammed, and the debugger enables access to the OCDR Register. In all othercases, the standard I/O location is accessed.
• Bit 7:0 – OCDR7:0 - On-Chip Debug Register Data
Table 28-16 OCDR Register Bits
Register Bits
OCDR7:0

440

Value
0

Description
Refer to the debugger documentation forfurther information on how to use thisregister.

ATmega128RFA1
8266A-MCU Wireless-12/09

ATmega128RFA1
29 IEEE 1149.1 (JTAG) Boundary-scan
29.1 Features• JTAG (IEEE std. 1149.1 compliant) Interface• Boundary-scan Capabilities According to the JTAG Standard• Full Scan of all Port Functions as well as Analog Circuitry having Off-chip
Connections• Supports the Optional IDCODE Instruction• Additional Public AVR_RESET Instruction to Reset the ATmega128RFA1

29.2 System Overview
The Boundary-scan chain has the capability of driving and observing the logic levels on
the digital I/O pins, as well as the boundary between digital and analog logic for analog
circuitry having off-chip connections. At system level, all ICs having JTAG capabilities
are connected serially by the TDI/TDO signals to form a long Shift Register. An external
controller sets up the devices to drive values at their output pins, and observe the input
values received from other devices. The controller compares the received data with the
expected result. In this way, Boundary-scan provides a mechanism for testing
interconnections and integrity of components on Printed Circuits Boards by using thefour TAP signals only.
The four IEEE 1149.1 defined mandatory JTAG instructions IDCODE, BYPASS,SAMPLE/PRELOAD, and EXTEST, as well as the AVR specific public JTAG instruction
AVR_RESET can be used for testing the Printed Circuit Board. Initial scanning of theData Register path will show the ID-Code of the device, since IDCODE is the default
JTAG instruction. It may be desirable to have the AVR device in reset during test mode.
If not reset, inputs to the device may be determined by the scan operations, and theinternal software may be in an undetermined state when exiting the test mode. Enteringreset, the outputs of any port pin will instantly enter the high impedance state, making
the HIGHZ instruction redundant. If needed, the BYPASS instruction can be issued tomake the shortest possible scan chain through the device. The device can be set in thereset state either by pulling the external RESET pin low, or issuing the AVR_RESET
instruction with appropriate setting of the Reset Data Register.
The EXTEST instruction is used for sampling external pins and loading output pins withdata. The data from the output latch will be driven out on the pins as soon as the
EXTEST instruction is loaded into the JTAG IR-Register. Therefore, the
SAMPLE/PRELOAD should also be used for setting initial values to the scan ring, toavoid damaging the board when issuing the EXTEST instruction for the first time.
SAMPLE/PRELOAD can also be used for taking a snapshot of the external pins during
normal operation of the part.
The JTAGEN Fuse must be programmed and the JTD bit in the I/O Register MCUCR
must be cleared to enable the JTAG Test Access Port.
When using the JTAG interface for Boundary-scan, using a JTAG TCK clock frequency
higher than the internal chip frequency is possible. The chip clock is not required to run.

29.3 Data Registers
The Data Registers relevant for Boundary-scan operations are:• Bypass Register• Device Identification Register
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• Reset Register• Boundary-scan Chain
29.3.1 Bypass Register
The Bypass Register consists of a single Shift Register stage. When the Bypass
Register is selected as path between TDI and TDO, the register is reset to 0 whenleaving the Capture-DR controller state. The Bypass Register can be used to shorten
the scan chain on a system when the other devices are to be tested.
29.3.2 Device Identification Register
Figure 29-1. The Format of the Device Identification Register
MSB
Bit
Device ID

31

LSB
28

27

12

11

1

0

VersionPart Number

Manufacturer ID

1

4 bits

16 bits

11 bits

1 bit

29.3.2.1 Version
Version is a 4-bit number identifying the revision of the component. The JTAG version
number follows the revision of the device. Revision A is 0x0, revision B is 0x1 and soon.
29.3.2.2 Part Number
The part number is a 16-bit code identifying the component. The JTAG Part Number for
ATmega128RFA1 is listed in Table 31-6 on page 467.
29.3.2.3 Manufacturer ID
The Manufacturer ID is a 11-bit code identifying the manufacturer. The JTAG
manufacturer ID for ATMEL is listed in Table 31-6 on page 467.
29.3.3 Reset Register
The Reset Register is a test Data Register used to reset the part. Since the AVR tristates Port Pins when reset, the Reset Register can also replace the function of theunimplemented optional JTAG instruction HIGHZ.
A high value in the Reset Register corresponds to pulling the external Reset low. The
part is reset as long as there is a high value present in the Reset Register. Dependingon the fuse settings for the clock options, the part will remain reset for a reset time-out
period (see "Clock Sources" on page 148) after releasing the Reset Register. The
output from this Data Register is not latched, so the reset will take place immediately,as shown in Figure 29-2 on page 443.

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ATmega128RFA1
Figure 29-2. Reset RegisterTo
TDO

From Other Internal andExternal Reset Sources
From
TDI

D

Q

Internal reset

ClockDR · AVR_RESET

29.3.4 Boundary-scan Chain
The Boundary-scan Chain has the capability of driving and observing the logic levels on
the digital I/O pins, as well as the boundary between digital and analog logic for analog
circuitry having off-chip connections.
See "Boundary-scan Chain" on page 444 for a complete description.

29.4 Boundary-scan Specific JTAG Instructions
The Instruction Register is 4-bit wide, supporting up to 16 instructions. Listed below are
the JTAG instructions useful for Boundary-scan operation. Note that the optional HIGHZ
instruction is not implemented, but all outputs with tri-state capability can be set in highimpedance state by using the AVR_RESET instruction, since the initial state for all port
pins is tri-state.
As a definition in this datasheet, the LSB is shifted in and out first for all Shift Registers.
The OPCODE for each instruction is shown behind the instruction name in hex format.
The text describes which Data Register is selected as path between TDI and TDO foreach instruction.
29.4.1 EXTEST; 0x0
Mandatory JTAG instruction for selecting the Boundary-scan Chain as Data Register for
testing circuitry external to the AVR package. For port-pins, Pull-up Disable, Output
Control, Output Data, and Input Data are all accessible in the scan chain. For Analog
circuits having off-chip connections, the interface between the analog and the digital
logic is in the scan chain. The contents of the latched outputs of the Boundary-scanchain is driven out as soon as the JTAG IR-Register is loaded with the EXTEST
instruction.
The active states are:
• Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain.
• Shift-DR: The Internal Scan Chain is shifted by the TCK input.
• Update-DR: Data from the scan chain is applied to output pins.
29.4.2 IDCODE; 0x1
Optional JTAG instruction selecting the 32 bit ID-Register as Data Register. The IDRegister consists of a version number, a device number and the manufacturer codechosen by JEDEC. This is the default instruction after power-up.

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The active states are:
• Capture-DR: Data in the IDCODE Register is sampled into the Boundary-scan
Chain.
• Shift-DR: The IDCODE scan chain is shifted by the TCK input.
29.4.3 SAMPLE_PRELOAD; 0x2
Mandatory JTAG instruction for pre-loading the output latches and taking a snap-shot of
the input/output pins without affecting the system operation. However, the output
latches are not connected to the pins. The Boundary-scan Chain is selected as Data
Register.
The active states are:
• Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain.
• Shift-DR: The Boundary-scan Chain is shifted by the TCK input.
• Update-DR: Data from the Boundary-scan chain is applied to the output latches.
However, the output latches are not connected to the pins.
29.4.4 AVR_RESET; 0xC
The AVR specific public JTAG instruction for forcing the AVR device into the Resetmode or releasing the JTAG reset source. The TAP controller is not reset by this
instruction. The one bit Reset Register is selected as Data Register. Note that the reset
will be active as long as there is a logic “one” in the Reset Chain. The output from thischain is not latched.
The active states are:
• Shift-DR: The Reset Register is shifted by the TCK input.
29.4.5 BYPASS; 0xF
Mandatory JTAG instruction selecting the Bypass Register for Data Register.
The active states are:
• Capture-DR: Loads a logic “0” into the Bypass Register.
• Shift-DR: The Bypass Register cell between TDI and TDO is shifted.

29.5 Boundary-scan Chain
The Boundary-scan chain has the capability of driving and observing the logic levels on
the digital I/O pins, as well as the boundary between digital and analog logic for analog
circuitry having off-chip connection.
29.5.1 Scanning the Digital Port Pins
Figure 29-3 on page 445 shows the Boundary-scan Cell for a bi-directional port pin. The
pull-up function is disabled during Boundary-scan when the JTAG IC contains EXTESTor SAMPLE_PRELOAD. The cell consists of a bi-directional pin cell that combines thethree signals Output Control - OCxn, Output Data - ODxn, and Input Data - IDxn, into
only a two-stage Shift Register. The port and pin indexes are not used in the following
description.
The Boundary-scan logic is not included in the figures in the datasheet. Figure 29-4 onpage 446 shows a simple digital port pin as described in the section "I/O-Ports" on page186. The Boundary-scan details from Figure 29-3 on page 445 replaces the dashed box
in Figure 29-4 on page 446.
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ATmega128RFA1When no alternate port function is present, the Input Data - ID - corresponds to the
PINxn Register value (but ID has no synchronizer), Output Data corresponds to the
PORT Register, Output Control corresponds to the Data Direction - DD Register, and
the Pull-up Enable - PUExn – corresponds to logic expression:

PUD ⋅ DDxn ⋅ PORTxn
Digital alternate port functions are connected outside the dotted box Figure 29-4 onpage 446 to make the scan chain read the actual pin value. For analog function, there isa direct connection from the external pin to the analog circuit. There is no scan chain on
the interface between the digital and the analog circuitry, but some digital control signal
to analog circuitry are turned off to avoid driving contention on the pads.
When JTAG IR contains EXTEST or SAMPLE_PRELOAD the clock is not sent out on
the port pins even if the CKOUT fuse is programmed. Even though the clock is output
when the JTAG IR contains SAMPLE_PRELOAD, the clock is not sampled by theboundary scan.
Figure 29-3. Boundary-scan Cell for Bi-directional Port Pin with Pull-up Function

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Figure 29-4. General Port Pin Schematic Diagram
See Boundary-scan
Description for Details!

PUExn

PUD

Q

D

DDxn

Q CLR

RESET

OCxn

WDx

Q

Pxn

ODxn

D

PORTxn

Q CLR

WRx

IDxn

DATA BUS

RDx

RESET
RRx

SLEEP

SYNCHRONIZER
D

Q

L

Q

D

RPx

Q

PINxn

Q

CLK I/O

PUD:
PUExn:
OCxn:
ODxn:
IDxn:
SLEEP:PULLUP DISABLE
PULLUP ENABLE for pin Pxn
OUTPUT CONTROL for pin Pxn
OUTPUT DATA to pin Pxn
INPUT DATA from pin Pxn
SLEEP CONTROL

WDx:
RDx:
WRx:
RRx:
RPx:
CLK I/O :WRITE DDRx
READ DDRx
WRITE PORTx
READ PORTx REGISTERREAD PORTx PIN
I/O CLOCK

29.5.2 Scanning the RSTN, CLKI and TST Pin
An observe-only cell as shown in Figure 29-5 below is inserted for the active low reset
signal RSTN, for the active high programming and test mode enable signal TSTN andfor the clock input CLKI.
Figure 29-5. Observe-only Cell
To
Next
Cell

ShiftDR

To System Logic

From System Pin

FF1
0
D

Q

1

From
Previous
Cell

446

ClockDR

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ATmega128RFA1
29.5.3 Scanning the RSTON Pin
For the low-active reset output pin RSTON a boundary-scan cell as shown in Figure29-6 below is inserted.
Figure 29-6. Boundary-scan Cell for Output Pins without Pull-up Function
To Next Cell

ShiftDREXTEST

From System Logic

FF0

LD0

0

D

D

1

0
From Previous
Cell

Q

Q

1
G

ClockDR

UpdateDR

29.6 Boundary-scan Related Register in I/O Memory
29.6.1 MCUCR – MCU Control RegisterBit

7$35 ($55)

JTD

Read/Write
Initial Value

RW
0

6

5

4

3

2

1

0

MCUCR

The MCU Control Register contains control bits for general Microcontroller Unit
functions.
• Bit 7 – JTD - JTAG Interface Disable
When this bit is zero, the JTAG interface is enabled if the JTAGEN Fuse isprogrammed. If this bit is one, the JTAG interface is disabled. In order to avoid
unintentional disabling or enabling of the JTAG interface, a timed sequence must be
followed when changing this bit: The application software must write this bit to thedesired value twice within four cycles to change its value. Note that this bit must not bealtered when using the On-chip Debug system.

29.6.2 MCUSR – MCU Status Register
Bit

7

6

5

4

$34 ($54)

JTRF

Read/Write
Initial Value

RW
0

3

2

1

0

MCUSR

The MCU Status Register provides information on which reset source caused an MCU
reset.

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• Bit 4 – JTRF - JTAG Reset Flag
This bit is set if a reset is being caused by a logic one in the JTAG Reset Register
selected by the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset,
or by writing a logic zero to the flag.

29.7 Boundary-scan Description Language Files
Boundary-scan Description Language (BSDL) files describe Boundary-scan capabledevices in a standard format used by automated test-generation software. The orderand function of bits in the Boundary-scan Data Register are included in this description.
BSDL files are available for ATmega128RFA1.

29.8 ATmega128RFA1 Boundary-scan Order
Table 29-1 on page 449 shows the Scan order between TDI and TDO when the
Boundary-scan chain is selected as data path. Bit 0 is the LSB; the first bit scanned in,and the first bit scanned out. The scan order follows the pin-out order. In Figure 29-3 onpage 445, PXn. Data corresponds to FF0, PXn. Control corresponds to FF1, PXn. Bit 4,
5, 6 and 7 of Port F is not in the scan chain, since these pins constitute the TAP pins
when the JTAG is enabled.

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ATmega128RFA1
Table 29-1. ATmega128RFA1 Boundary-Scan Order
Bit
NumberSignal Name

0

PF1.Control

1

PF1.Data

2

PF0.Control

ModulePort F

Bit
NumberSignal Name

36

CLKI.Data

37

PD7.Control

38

PD7.Data

ModuleClock Input (Input Only)

3

PF0.Data

39

PD6.Control

4

PE7.Control

40

PD6.Data

5

PE7.Data

41

PD5.Control

6

PE6.Control

42

PD5.Data

7

PE6.Data

43

PD4.Control

8

PE5.Control

44

PD4.Data

9PE5.Data

45

PD3.Control

10

PE4.Control

46

PD3.Data

11

PE4.Data

47

PD2.Control

12

PE3.Control

48

PD2.Data

13

PE3.Data

49

PD1.Control

14

PE2.Control

50

PD1.Data

15

PE2.Data

51

PD0.Control

16

PE1.Control

52

PD0.Data

17

PE1.Data

53

PG5.Control

18

PE0.Control

54

PG5.Data

19

PE0.Data

55

PG4.Control

20

PB7.Control

56

PG4.Data

21

PB7.Data

57

PG3.Control

22

PB6.Control

58

PG3.Data

23

PB6.Data

59

PG2.Control

24

PB5.Control

60

PG2.Data

25

PB5.Data

61

PG1.Control

26

PB4.Control

62

PG1.Data

27

PB4.Data

63

PG0.Control

28

PB3.Control

64

PG0.Data

29

PB3.Data

65

RSTON.Data

Reset Logic Output (Output Only
without Pull-up)

30

PB2.Control

66

RSTT.Data

Reset Logic (Observe Only)

31

PB2.Data

67

TST.Data

Test and Programming Mode
Enable (Observe Only)

32

PB1.Control

68

PF3.Control

33

PB1.Data

69

PF3.Data

34

PB0.Control

70

PF2.Control

35

PB0.Data

71

PF2.Data

Port EPort B

Port DPort GPort F

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30 Boot Loader Support – Read-While-Write Self-Programming
The Boot Loader Support provides a real Read-While-Write Self-Programming
mechanism for downloading and uploading program code by the MCU itself. Thisfeature allows flexible application software updates controlled by the MCU using a
Flash-resident Boot Loader program. The Boot Loader program can use any available
data interface and associated protocol to read code and write that (program) code into
the Flash memory, or read the code from the program memory. The program code
within the Boot Loader section has the capability to write into the entire Flash, including
the Boot Loader memory. The Boot Loader can thus even modify itself (including
erasing) from the code if the feature is not needed anymore. The size of the Boot
Loader memory is configurable with fuses and the Boot Loader has two separate setsof Boot Lock bits which can be set independently. This gives the user a unique flexibility
to select different levels of protection.

30.1 Features• Read-While-Write Self-Programming• Flexible Boot Memory Size
• High Security (Separate Boot Lock Bits for a Flexible Protection)• Separate Fuse to Select Reset Vector(1)• Optimized Page

Size

• Code Efficient Algorithm• Efficient Read-Modify-Write Support
Note:

1. A page is a section in the Flash consisting of several bytes (see "Table 31-7" onpage 467) used during programming. The page organization does not affect normal
operation.

30.2 Application and Boot Loader Flash Sections
The Flash memory is organized in two main sections: the Application section and the
Boot Loader section (see Figure 30-2 on page 452). The size of the different sections is
configured by the BOOTSZ Fuses as shown in Table 30-7 on page 461 and Figure 30-2
on page 452. These two sections can have different level of protection since they havedifferent sets of Lock bits.
30.2.1 Application Section
The Application section is the region of the Flash that is used for storing the application
code. The protection level for the Application section can be selected by the application
Boot Lock bits (Boot Lock bits 0, BLB0), see Table 31-2 on page 464. The Application
section can never store any Boot Loader code since the SPM instruction is disabled
when executed from the Application section.
30.2.2 BLS – Boot Loader Section
While the Application section is used for storing the application code, the Boot Loader
software must be located in the BLS. The SPM instruction can only initiate
programming when executed from the BLS. The SPM instruction can access the entire
Flash, including the BLS itself. The protection level for the Boot Loader section can beselected by the Boot Loader Lock bits (Boot Lock bits 1, BLB1), see Table 31-2 on page
464.

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30.3 Read-While-Write and No Read-While-Write Flash Sections
Whether the CPU supports Read-While-Write or if the CPU is halted during a Boot
Loader software update is dependent on the address that is being programmed. In
addition to the two sections that are configurable by the BOOTSZ Fuses as describedabove, the Flash is also divided into two fixed sections, the Read-While-Write (RWW)
section and the No Read-While-Write (NRWW) section. The limit between the RWWand NRWW sections is given in Table 30-1 on page 452 and Figure 30-1 below. The
main differences between the two sections are:• When erasing or writing a page located inside the RWW section, the NRWW section
can be read during the operation.
• When erasing or writing a page located inside the NRWW section, the CPU is halted
during the entire operation.
Note that the user software can never read any code that is located inside the RWW
section during a Boot Loader software operation. The syntax “Read-While-Write
section” refers to the section that is being programmed (erased or written) and not tothe section that actually is being read during a Boot Loader software update.
Figure 30-1. Read-While-Write vs. No Read-While-Write

Read-While-Write(RWW) Section

Z-pointer
Addresses RWW
SectionZ-pointer
Addresses NRWW
SectionNo Read-While-Write(NRWW) Section

CPU is Halted
During the Operation
Code Located in
NRWW Section
Can be Read During
the Operation

30.3.1 RWW – Read-While-Write Section
If a Boot Loader software update is programming a page inside the RWW section, it ispossible to read code from the Flash, but only code that is located in the NRWW
section. During an ongoing programming, the software must ensure that the RWW
section never is being read. If the user software is trying to read code that is locatedinside the RWW section (i.e., by load program memory, call, or jump instructions or aninterrupt) during programming, the software might end up in an unknown state. To avoid
this, the interrupts should either be disabled or moved to the Boot Loader section. The
Boot Loader section is always located in the NRWW section. The RWW Section Busybit (RWWSB) in the Store Program Memory Control and Status Register (SPMCSR) will
be read as logical one as long as the RWW section is blocked for reading. After a

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programming is completed, the RWWSB must be cleared by software before readingcode located in the RWW section. See "SPMCSR – Store Program Memory Control
Register" on page 462 for details on how to clear RWWSB.
30.3.2 NRWW – No Read-While-Write Section
The code located in the NRWW section can be read when the Boot Loader software is
updating a page in the RWW section. When the Boot Loader code updates the NRWW
section, the CPU is halted during the entire Page Erase or Page Write operation.
Table 30-1. Read-While-Write Features
CPU Halted?

Read-While-Write
Supported?

NRWW Section

No

Yes

None

Yes

No

Which Section does the Z-pointerAddress during the Programming?

Which Section can be Readduring Programming?

RWW Section
NRWW Section

Figure 30-2. Memory Sections
Program Memory
BOOTSZ = '10'

Program Memory
BOOTSZ = '11'0x0000Read-While-Write Section

Application Flash Section

End RWW
Start NRWW
Application Flash Section

Boot Loader Flash Section

End Application
Start Boot Loader
Flashend

No Read-While-Write Section

No Read-While-Write Section

Read-While-Write Section

0x0000Program Memory
BOOTSZ = '01'

Application Flash Section

End RWW
Start NRWW
Application Flash Section

Boot Loader Flash Section

Flashend
Program Memory
BOOTSZ = '00'

452

Read-While-Write Section

0x0000Application Flash Section

End RWW
Start NRWW
Application Flash Section
End Application
Start Boot Loader
Boot Loader Flash Section
Flashend

No Read-While-Write Section

No Read-While-Write Section

Read-While-Write Section

0x0000Note:

End Application
Start Boot Loader

Application Flash Section

End RWW, End Application
Start NRWW, Start Boot Loader

Boot Loader Flash Section

Flashend

1. The parameters in the figure above are given in Table 30-7 on page 461.

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ATmega128RFA1
30.4 Boot Loader Lock Bits
If no Boot Loader capability is needed, the entire Flash is available for application code.
The Boot Loader has two separate sets of Boot Lock bits which can be set
independently. This gives the user a unique flexibility to select different levels ofprotection.
The user can select:• To protect the entire Flash from a software update by the MCU.
• To protect only the Boot Loader Flash section from a software update by the MCU.
• To protect only the Application Flash section from a software update by the MCU.
• Allow software update in the entire Flash.
See Table 31-2 on page 464 for further details. The Boot Lock bits can be set insoftware and in Serial or Parallel Programming mode, but they can be cleared by a
Chip Erase command only. The general Write Lock (Lock Bit mode 2) does not control
the programming of the Flash memory by SPM instruction. Similarly, the general
Read/Write Lock (Lock Bit mode 1) does not control reading nor writing by(E)LPM/SPM, if it is attempted.
30.4.1 Entering the Boot Loader ProgramEntering the Boot Loader takes place by a jump or call from the application program.
This may be initiated by a trigger such as a command received via USART, or SPI
interface. Alternatively, the Boot Reset Fuse can be programmed so that the Reset
Vector is pointing to the Boot Flash start address after a reset. In this case, the Boot
Loader is started after a reset. After the application code is loaded, the program canstart executing the application code. Note that the fuses cannot be changed by the
MCU itself. This means that once the Boot Reset Fuse is programmed, the Reset
Vector will always point to the Boot Loader Reset and the fuse can only be changed
through the serial or parallel programming interface.
(1)

Table 30-2. Boot Reset Fuse
BOOTRST

Reset Address

1

Reset Vector = Application Reset (address 0x0000)

0Reset Vector = Boot Loader Reset (see Table 30-7 on page 461)

Note:

1. “1” means unprogrammed, “0” means programmed

30.5 Addressing the Flash During Self-Programming
The Z-pointer is used to address the SPM commands. The Z pointer consists of the Zregisters ZL and ZH in the register file, and RAMPZ in the I/O space. The number ofbits actually used is implementation dependent. Note that the RAMPZ register is only
implemented when the program space is larger than 64K bytes.
Bit

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

RAMPZ1

RAMPZ0RAMPZ
ZH (R31)

Z15

Z14

Z13

Z12

Z11

Z10

Z9

Z8

ZL (R30)

Z7

Z6

Z5

Z4

Z3

Z2

Z1

Z0

7

6

5

4

3

2

1

0

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Since the Flash is organized in pages (see "Table 31-7" on page 467), the Program
Counter can be treated as having two different sections. One section, consisting of theleast significant bits, is addressing the words within a page, while the most significant
bits are addressing the pages. This is shown in Figure 30-3 below. Note that the Page
Erase and Page Write operations are addressed independently. Therefore it is of major
importance that the Boot Loader software addresses the same page in both the Page
Erase and Page Write operation. Once a programming operation is initiated, theaddress is latched and the Z-pointer can be used for other operations.
The (E)LPM instruction uses the Z-pointer to store the address. Since this instruction
addresses the Flash byte-by-byte, also bit Z0 of the Z-pointer is used.
Figure 30-3. Addressing the Flash during SPM
BIT

15ZPCMSBZPAGEMSB

Z - REGISTER

1 0
0

PCMSB
PROGRAM
COUNTERPAGEMSB
PCPAGEPCWORD

PAGE ADDRESSWITHIN THE FLASH

WORD ADDRESSWITHIN A PAGE

PROGRAM MEMORY
PAGE

PAGE
INSTRUCTION WORD

PCWORD[PAGEMSB:0]:
00
01
02

PAGEEND

Note:

1. The different variables used in Figure 30-3 above are listed in Table 30-6 on page461.

30.6 Self-Programming the FlashThe program memory is updated in a page by page fashion. Before programming a
page with the data stored in the temporary page buffer, the page must be erased. The
temporary page buffer is filled one word at a time using SPM and the buffer can be filled
either before the Page Erase command or between a Page Erase and a Page Write
operation:
Alternative 1, fill the buffer before a Page Erase• Fill temporary page buffer,• Perform a Page Erase,• Perform a Page Write;
Alternative 2, fill the buffer after Page Erase• Perform a Page Erase,

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ATmega128RFA1• Fill temporary page buffer,• Perform a Page Write;
If only a part of the page needs to be changed, the rest of the page must be stored (forexample in the temporary page buffer) before the erase, and then be rewritten. Whenusing alternative 1, the Boot Loader provides an effective Read-Modify-Write feature
which allows the user software to first read the page, do the necessary changes, andthen write back the modified data. If alternative 2 is used, it is not possible to read theold data while loading since the page is already erased. The temporary page buffer canbe accessed in a random sequence. It is essential that the page address used in boththe Page Erase and Page Write operation is addressing the same page. For an
assembly code example see "Simple Assembly Code Example for a Boot Loader" on
page 458.
30.6.1 Performing Page Erase by SPM
To execute Page Erase, set up the address in the Z-pointer, write “X0000011” to
SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in
R1 and R0 is ignored. The page address must be written to PCPAGE in the Z-register.
Other bits in the Z-pointer will be ignored during this operation.
• Page Erase to the RWW section: The NRWW section can be read during the Page
Erase.
• Page Erase to the NRWW section: The CPU is halted during the operation.
30.6.2 Filling the Temporary Buffer (Page Loading)To write an instruction word, set up the address in the Z-pointer and data in R1:R0,
write “00000001” to SPMCSR and execute SPM within four clock cycles after writing
SPMCSR. The content of PCWORD in the Z-register is used to address the data in thetemporary buffer. The temporary buffer will be auto-erased after a Page Write operation
or by writing the RWWSRE bit in SPMCSR. It is also erased after a system reset. Notethat it is not possible to write more than one time to each address without erasing the
temporary buffer.
If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded
is still buffered.
30.6.3 Performing a Page Write
To execute Page Write, set up the address in the Z-pointer, write “X0000101” to
SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in
R1 and R0 is ignored. The page address must be written to PCPAGE. Other bits in the
Z-pointer must be written to zero during this operation.
• Page Write to the RWW section: The NRWW section can be read during the Page
Write.
• Page Write to the NRWW section: The CPU is halted during the operation.
30.6.4 Using the SPM Interrupt
If the SPM interrupt is enabled, the SPM interrupt will generate a constant interrupt
when the SPMEN bit in SPMCSR is cleared. This means that the interrupt can be usedinstead of polling the SPMCSR Register in software. When using the SPM interrupt, theInterrupt Vectors should be moved to the BLS section to avoid that an interrupt isaccessing the RWW section when it is blocked for reading. How to move the interrupts
is described in "Interrupts" on page 211.

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30.6.5 Consideration While Updating BLS
Special care must be taken if the user allows the Boot Loader section to be updated byleaving Boot Lock bit11 un-programmed. An accidental write to the Boot Loader itself
can corrupt the entire Boot Loader, and further software updates might be impossible. If
it is not necessary to change the Boot Loader software itself, it is recommended toprogram the Boot Lock bit11 to protect the Boot Loader software from any internal
software changes.
30.6.6 Prevent Reading the RWW Section During Self-Programming
During Self-Programming (either Page Erase or Page Write), the RWW section isalways blocked for reading. The user software itself must prevent that this section isaddressed during the self programming operation. The RWWSB in the SPMCSR will be
set as long as the RWW section is busy. During Self-Programming the Interrupt Vector
table should be moved to the BLS as described in "Interrupts" on page 211, or theinterrupts must be disabled. Before addressing the RWW section after the programmingis completed, the user software must clear the RWWSB by writing the RWWSRE. See"Simple Assembly Code Example for a Boot Loader" on page 458 for an example.
30.6.7 Setting the Boot Loader Lock Bits by SPM
To set the Boot Loader Lock bits and general Lock bits, write the desired data to R0,
write “X0001001” to SPMCSR and execute SPM within four clock cycles after writing
SPMCSR.
Bit

7

6

5

4

3

2

1

0

R0

1

1

BLB12

BLB11

BLB02

BLB01

LB2

LB1

See Table 31-2 on page 464 for how the different settings of the Boot Loader bits affect
the Flash access.
If bits 5:0 in R0 are cleared (zero), the corresponding Lock bit will be programmed if an
SPM instruction is executed within four cycles after BLBSET and SPMEN are set in
SPMCSR. The Z-pointer is don’t care during this operation, but for future compatibility it
is recommended to load the Z-pointer with 0x0001 (same as used for reading the Lockbits). For future compatibility it is also recommended to set bits 7 and 6 in R0 to “1”when writing the Lock bits. When programming the Lock bits the entire Flash can beread during the operation.
30.6.8 EEPROM Write Prevents Writing to SPMCSR
Note that an EEPROM write operation will block all software programming to Flash.
Reading the Signature Row, Fuses and Lock bits from software will also be prevented
during the EEPROM write operation. It is recommended that the user checks the status
bit (EEPE) in the EECR Register and verifies that the bit is cleared before writing to the
SPMCSR Register.
30.6.9 Reading the Fuse and Lock Bits from Software
It is possible to read both the Fuse and Lock bits from software. To read the Lock bits,
load the Z-pointer with 0x0001 and set the BLBSET and SPMEN bits in SPMCSR.
When an (E)LPM instruction is executed within three CPU cycles after the BLBSET and
SPMEN bits are set in SPMCSR, the value of the Lock bits will be loaded in thedestination register. The BLBSET and SPMEN bits will auto-clear upon completion ofreading the Lock bits or if no (E)LPM instruction is executed within three CPU cycles or
no SPM instruction is executed within four CPU cycles. When BLBSET and SPMEN are
cleared, (E)LPM will work as described in the Instruction Set Manual.
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ATmega128RFA1
Bit

7

6

5

4

3

2

1

0

Rd

-

-

BLB12

BLB11

BLB02

BLB01

LB2

LB1

The algorithm for reading the Fuse Low byte is similar to the one described above forreading the Lock bits. To read the Fuse Low byte, load the Z-pointer with 0x0000 and
set the BLBSET and SPMEN bits in SPMCSR. When an (E)LPM instruction is executed
within three cycles after the BLBSET and SPMEN bits are set in the SPMCSR, thevalue of the Fuse Low byte (FLB) will be loaded in the destination register as shown on
the next page. Refer to (see "Table 31-5" on page 466) for a detailed description andmapping of the Fuse Low byte.
Bit

7

6

5

4

3

2

1

0

Rd

FLB7

FLB6

FLB5

FLB4

FLB3

FLB2

FLB1

FLB0

Similarly, load 0x0003 in the Z-pointer for reading the Fuse High byte. When an (E)LPM
instruction is executed within three cycles after the BLBSET and SPMEN bits are set in
the SPMCSR, the value of the Fuse High byte (FHB) will be loaded in the destination
register as shown below. Refer to "Table 31-4" on page 465 for detailed description andmapping of the Fuse High byte.
Bit

7

6

5

4

3

2

1

0

Rd

FHB7

FHB6

FHB5

FHB4

FHB3

FHB2

FHB1

FHB0

Load 0x0002 in the Z-pointer for reading the Extended Fuse byte. When an (E)LPM
instruction is executed within three cycles after the BLBSET and SPMEN bits are set in
the SPMCSR, the value of the Extended Fuse byte (EFB) will be loaded in thedestination register as shown below. Refer to Table 31-3 on page 465 for detailed
description and mapping of the Extended Fuse byte.
Bit

7

6

5

4

3

2

1

0

Rd

-

-

-

-

-

EFB2

EFB1

EFB0

Fuse and Lock bits that are programmed will be read as zero. Fuse and Lock bits thatare un-programmed will be read as one.
30.6.10 Reading the Signature Row from Software
To read the Signature Row from software, load the Z-pointer with the signature byte
address given in Table 30-3 below and set the SIGRD and SPMEN bits in SPMCSR.
When a LPM instruction is executed within three CPU cycles after the SIGRD and
SPMEN bits are set in SPMCSR, the signature byte value will be loaded in thedestination register. The SIGRD and SPMEN bits will auto-clear upon completion ofreading the Signature Row or if no LPM instruction is executed within three CPU cycles.
When SIGRD and SPMEN are cleared, LPM will work as described in the Instruction
Set Manual. The Signature Row cannot be read during an EEPROM write/erase
operation.
Table 30-3. Signature Row Addressing
Signature Byte

Z-Pointer Address

Device Signature Byte 10x0000Device Signature Byte 20x0002

Device Signature Byte 30x0004

RC Oscillator Calibration Byte

0x0001Note:

2. All other addresses are reserved for future use.

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30.6.11 Preventing Flash Corruption
During periods of VDEVDD<1.8V, the Flash program can be corrupted because the supply
voltage is too low for the CPU and the Flash to operate properly. These issues are thesame as for board level systems using Flash, and the same design solutions should beapplied.
A Flash program corruption can be caused by two situations when the voltage is toolow. First, a regular write sequence to the Flash requires a minimum voltage to operatecorrectly. Secondly, the CPU itself can execute instructions incorrectly, if the supply
voltage for executing instructions is too low.
Flash corruption can easily be avoided by following these design recommendations(one is sufficient):
1. If there is no need for a Boot Loader update in the system, program the Boot Loader
Lock bits to prevent any Boot Loader software updates.
2. Keep the AVR RESET active (low) during periods of insufficient power supply
voltage. This can be done by enabling the internal Brown-out Detector (BOD) if theoperating voltage matches the detection level. If not, an external low VDEVDD reset
protection circuit can be used. If a reset occurs while a write operation is in progress,
the write operation will be completed under the condition that the power supply
voltage is sufficient.
3. Keep the AVR core in Power-down sleep mode during periods of low VDEVDD. This
will prevent the CPU from attempting to decode and execute instructions, effectively
protecting the SPMCSR Register and thus the Flash from unintentional writes.
30.6.12 Programming Time for Flash when Using SPM
The calibrated RC Oscillator is used to time Flash accesses. Table 30-4 below shows
the typical programming time for Flash accesses from the CPU.
Table 30-4. SPM Programming Time
SymbolMin Programming TimeMax Programming Time

Flash write (Page Write, and write
Lock bits by SPM)

3.7 ms

4.5 msFlash write (Page Erase)

7.3 ms

8.9 ms30.6.13 Simple Assembly Code Example for a Boot Loader
Assembly Code Example(1);-the routine writes one page of data from RAM to Flash; the first data location in RAM is pointed to by the Y pointer; the first data location in Flash is pointed to by the Z-pointer;-error handling is not included;-the routine must be placed inside the Boot space; (at least the Do_spm sub routine). Only code inside NRWW section; can be read during Self-Programming (Page Erase and Page Write).
;-registers used: r0, r1, temp1 (r16), temp2 (r17), looplo (r24),; loophi (r25), spmcrval (r20); storing and restoring of registers is not included in the routine; register usage can be optimized at the expense of code size;-It is assumed that either the interrupt table is moved to the; Boot loader section or that the interrupts are disabled.

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ATmega128RFA1Assembly Code Example(1).equ PAGESIZEB=PAGESIZE*2 ;PAGESIZEB is page in BYTES, not words.org SMALLBOOTSTART
Write_page:; Page Eraseldi spmcrval, (1<<PGERS) | (1<<SPMEN)
call Do_spm; re-enable the RWW section
ldi spmcrval, (1<<RWWSRE) | (1<<SPMEN)
call Do_spm; transfer data from RAM to Flash page buffer
ldi looplo, low(PAGESIZEB);init loop variable

ldi loophi, high(PAGESIZEB);not required for PAGESIZEB<=256

Wrloop:ld r0, Y+
ld r1, Y+
ldi spmcrval, (1<<SPMEN)
call Do_spm
adiw ZH:ZL, 2
sbiw loophi:looplo, 2;use subi for PAGESIZEB<=256

brne Wrloop; execute Page Write
subi ZL, low(PAGESIZEB);restore pointersbci ZH, high(PAGESIZEB);not required for PAGESIZEB<=256

ldi spmcrval, (1<<PGWRT) | (1<<SPMEN)
call Do_spm; re-enable the RWW section
ldi spmcrval, (1<<RWWSRE) | (1<<SPMEN)
call Do_spm; read back and check, optional
ldi looplo, low(PAGESIZEB);init loop variable

ldi loophi, high(PAGESIZEB);not required for PAGESIZEB<=256

subi YL, low(PAGESIZEB);restore pointersbci YH, high(PAGESIZEB)
Rdloop:elpm r0, Z+
ld r1, Y+
cpse r0, r1
jmp Error
sbiw loophi:looplo, 1;use subi for PAGESIZEB<=256

brne Rdloop; return to RWW section; verify that RWW section is safe to read
Return:in temp1, SPMCSR

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Assembly Code Example(1); If RWWSB is set, the RWW section is not ready yet
sbrs temp1, RWWSB
ret; re-enable the RWW section
ldi spmcrval, (1<<RWWSRE) | (1<<SPMEN)
call Do_spm
rjmp Return
Do_spm:; check for previous SPM complete
Wait_spm:in temp1, SPMCSR
sbrc temp1, SPMEN
rjmp Wait_spm; input: spmcrval determines SPM action; disable interrupts if enabled, store status
in temp2, SREGcli
; check that no EEPROM write access is present
Wait_ee:sbic EECR, EEPE
rjmp Wait_ee; SPM timed sequence
out SPMCSR, spmcrval
spm; restore SREG (to enable interrupts if originally enabled)out SREG, temp2
ret
Notes:

1. See "About Code Examples" on page 7.

30.6.14 Boot Loader Parameters for 128kByte of Flash Memory
In Table 30-7 on page 461 through Table 30-6 on page 461, the parameters used in thedescription of the Self-Programming are given.
Table 30-5. Read-While-Write Limit with 128kByte of Flash Memory
SectionPages

Address

Read-While-Write section (RWW)

480

0x0000 – 0xEFFF

No Read-While-Write section (NRWW)

32

0xF000 – 0xFFFF

Note:

460

(1)

1. For details about these two sections see "NRWW – No Read-While-Write Section"
on page 452 .

ATmega128RFA1
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ATmega128RFA1
Table 30-6. Explanation of different variables used in Figure 30-3 on page 454 and themapping to the Z-pointer for 128kByte of Flash Memory
Corresponding(2)
Z-value(1)

Variable

Value

PCMSB

15

Most significant bit in the Program Counter.
(The Program Counter is 16 bits PC[15:0])

PAGEMSB

6

Most significant bit which is used to address
the words within one page (128 words in apage requires seven bits PC [6:0]).
(3)

ZPCMSB

Z16

ZPAGEMSB

Z7

Description

Bit in Z-pointer that is mapped to PCMSB.
Because Z0 is not used, the ZPCMSB
equals PCMSB + 1.
Bit in Z-pointer that is mapped to PCMSB.
Because Z0 is not used; the ZPAGEMSB
equals PAGEMSB + 1.

PCPAGE

PC[15:7]

Z16 :Z8

Program Counter page address: Page
select, for Page Erase and Page Write.

PCWORDPC[6:0]

Z7:Z1

Program Counter word address: Word
select, for filling temporary buffer (must be
zero during Page Write operation)

Notes:(3)

1. Z0: should be zero for all SPM commands, byte select for the (E)LPM instruction.
2. See "Addressing the Flash During Self-Programming" on page 453 for details
about the use of Z-pointer during Self-Programming.
3. The Z-register is only 16 bits wide. Bit 16 is located in the RAMPZ register in the
I/O map.
(1)

Boot Loader Flash
SectionEnd Application
SectionBoot Reset Address(Start Boot Loader
Section)4

0x0000 –0xFDFF

0xFE00 –0xFFFF

0xFDFF

0xFE00

1

0

1024
words

8

0x0000 –0xFBFF

0xFC00 –0xFFFF

0xFBFF

0xFC00

0

1

2048
words

16

0x0000 –0xF7FF

0xF800 –0xFFFF

0xF7FF

0xF800

0

0

4096
words

32

0x0000 –0xEFFF

0xF000 –0xFFFF

0xEFFF

0xF000

Note:

Pages

512
words

Boot Size

1

BOOTSZ0

1

BOOTSZ1

Application Flash
SectionTable 30-7. Boot Size Configuration with 128kByte of Flash Memory

1. The different BOOTSZ Fuse configurations are shown in Figure 30-2 on page 452.

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30.7 Register Description
30.7.1 SPMCSR – Store Program Memory Control Register
Bit

7

6

5

$37 ($57)

SPMIE

RWWSB

SIGRD

Read/Write
Initial Value

RW
0

R
0

RW
0

4

3

2

RWWSRE BLBSET PGWRT
RW
0

RW
0

RW
0

1

0

PGERS

SPMEN

RW
0

RW
0

SPMCSRThe Store Program Memory Control Register contains the control bits needed to control
the Boot Loader operations. Note: Only one SPM instruction should be active at any
time.
• Bit 7 – SPMIE - SPM Interrupt Enable
When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one),
the SPM ready interrupt will be enabled. The SPM ready Interrupt will be executed aslong as the SPMEN bit in the SPMCR register is cleared.
• Bit 6 – RWWSB - Read While Write Section Busy
When a self-programming (page erase or page write) operation to the RWW section is
initiated, the RWWSB will be set (one) by hardware. When the RWWSB bit is set, the
RWW section cannot be accessed. The RWWSB bit will be cleared if the RWWSRE bit
is written to one after a self-programming operation is completed. Alternatively the
RWWSB bit will automatically be cleared if a page load operation is initiated.
• Bit 5 – SIGRD - Signature Row Read
If this bit is written to one at the same time as SPMEN, the next LPM instruction within
three clock cycles will read a byte from the signature row into the destination register. A
SPM instruction within four cycles after SIGRD and SPMEN are set, will have no effect.
This operation is reserved for future use and should not be used.
• Bit 4 – RWWSRE - Read While Write Section Read Enable
When programming (page erase or page write) to the RWW section, the RWW sectionis blocked for reading (the RWWSB will be set by hardware). To re-enable the RWW
section, the user software must wait until the programming is completed (SPMEN will
be cleared). Then, if the RWWSRE bit is written to one at the same time as SPMEN,
the next SPM instruction within four clock cycles re-enables the RWW section. The
RWW section cannot be re-enabled while the Flash is busy with a page erase or a page
write (SPMEN is set). If the RWWSRE bit is written while the Flash is being loaded, theFlash load operation will abort and the data loaded will be lost.
• Bit 3 – BLBSET - Boot Lock Bit Set
If this bit is written to one at the same time as SPMEN, the next SPM instruction withinfour clock cycles sets Boot Lock bits, according to the data in R0. The data in R1 andthe address in the Z pointer are ignored. The BLBSET bit will automatically be cleared
upon completion of the lock bit set, or if no SPM instruction is executed within four clock
cycles. A LPM instruction within three cycles after BLBSET and SPMEN are set in the
SPMCR register, will read either the Lock-bits or the Fuse bits (depending on Z0 in the
Z pointer) into the destination register.
• Bit 2 – PGWRT - Page Write
If this bit is written to one at the same time as SPMEN, the next SPM instruction withinfour clock cycles executes page write, with the data stored in the temporary buffer. The
page address is taken from the high part of the Z pointer. The data in R1 and R0 are
ignored. The PGWRT bit will auto-clear upon completion of a page write, or if no SPM

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ATmega128RFA1
instruction is executed within four clock cycles. The CPU is halted during the entire
page write operation if the NRWW section is addressed.
• Bit 1 – PGERS - Page Erase
If this bit is written to one at the same time as SPMEN, the next SPM instruction withinfour clock cycles executes page erase. The page address is taken from the high part of
the Z pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear uponcompletion of a page erase, or if no SPM instruction is executed within four clock
cycles. The CPU is halted during the entire page write operation if the NRWW section isaddressed.
• Bit 0 – SPMEN - Store Program Memory Enable
This bit enables the SPM instruction for the next four clock cycles. If written to one
together with either RWWSRE, BLB-SET, PGWRT or PGERS, the following SPM
instruction will have a special meaning, see description above. If only SPMEN is written,
the following SPM instruction will store the value in R1:R0 in the temporary page buffer
addressed by the Z pointer. The LSB of the Z pointer is ignored. The SPMEN bit will
auto-clear upon completion of an SPM instruction, or if no SPM instruction is executed
within four clock cycles. During page erase and page write, the SPMEN bit remain highuntil the operation is completed. Writing any other combination than "10001", "01001","00101", "00011" or "00001" in the lower five bits will have no effect.

30.7.2 NEMCR – Flash Extended-Mode Control-Register
Bit

7

6

5

4

3

2

1

0

NA ($75)

Resx7

ENEAM

AEAM1

AEAM0

Resx3

Resx2

Resx1

Resx0

Read/Write
Initial Value

RW
0

RW
0

RW
0

RW
0

RW
1

RW
0

RW
1

RW
0

NEMCR

The Flash Extended-Mode Control-Register handles the extended address-mode of theextra rows.
• Bit 7 – Resx7 - Reserved• Bit 6 – ENEAM - Enable Extended Address Mode for Extra Rows
When active high, the extended address mode of the extra rows is enabled. The
address is decoded from bits AEAM1:0 of this register.
• Bit 5:4 – AEAM1:0 - Address for Extended Address Mode of Extra Rows
These bits are only used when bit ENEAM of this register is set high. Then AEAM1:0
are used to decode the addresses of the extra rows. A value of 0 decodes the default
factory row that is also accessible when the extended address mode is deactivated.
Table 30-8 AEAM Register Bits
Register Bits
AEAM1:0

Value

Description

0

Factory Row

1User Row 1

2

User Row 2

3

User Row 3• Bit 3:0 – Resx3:0 - Reserved

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31 Memory Programming
31.1 Program And Data Memory Lock Bits
The ATmega128RFA1 provides six Lock bits which can be left un-programmed (“1”) or
can be programmed (“0”) to obtain the additional features listed in Table 31-2 below.
The Lock bits can only be erased to “1” with the Chip Erase command.
Table 31-1. Lock Bit Byte
Lock Bit Byte

(1)

Bit NoDescription

Default Value

−

7

−

1 (un-programmed)

−

6

−

1 (un-programmed)

BLB12

5

Boot Lock bit

1 (un-programmed)

BLB11

4

Boot Lock bit

1 (un-programmed)

BLB02

3

Boot Lock bit

1 (un-programmed)

BLB01

2

Boot Lock bit

1 (un-programmed)

LB2

1

Lock bit

1 (un-programmed)

LB1

0

Lock bit

1 (un-programmed)

Note:

1. “1” means un-programmed, “0” means programmed.

Table 31-2. Lock Bit Protection Modes
Memory Lock Bits

Protection TypeLB Mode

LB2

LB1

1

1

1

No memory lock features enabled.

0

Further programming of the Flash and EEPROM isdisabled in Parallel and Serial Programming mode.
The Fuse bits are locked in both Serial and Parallel(1)
Programming mode.
Further programming and verification of the Flash and
EEPROM is disabled in Parallel and Serial
Programming mode. The Boot Lock bits and Fuse bits
are locked in both Serial and Parallel Programming
(1)
mode.

2

1

3

0

0

BLB0 Mode

BL02

BL01

1

1

1

No restrictions for SPM or (E)LPM accessing theApplication section.

2

1

0

SPM is not allowed to write to the Application section.

0

SPM is not allowed to write to the Application section,and (E)LPM executing from the Boot Loader section
is not allowed to read from the Application section. If
Interrupt Vectors are placed in the Boot Loader
section, interrupts are disabled while executing fromthe Application section.

1(E)LPM executing from the Boot Loader section is notallowed to read from the Application section. If
Interrupt Vectors are placed in the Boot Loader
section, interrupts are disabled while executing fromthe Application section.

3

4

464

(1)(2)

00ATmega128RFA1
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ATmega128RFA1
Memory Lock Bits

Protection Type

BLB1 Mode

BL12

BL11

1

1

1

No restrictions for SPM or (E)LPM accessing the Boot
Loader section.

2

1

0

SPM is not allowed to write to the Boot Loader
section.

0

SPM is not allowed to write to the Boot Loader
section, and (E)LPM executing from the Application
section is not allowed to read from the Boot Loader
section. If Interrupt Vectors are placed in the
Application section, interrupts are disabled while
executing from the Boot Loader section.

1(E)LPM executing from the Application section is notallowed to read from the Boot Loader section. If
Interrupt Vectors are placed in the Application
section, interrupts are disabled while executing fromthe Boot Loader section.

3

0

4

0

Notes:

1. Program the Fuse bits and Boot Lock bits before programming the LB1 andLB2.
2. “1” means un-programmed, “0” means programmed.

31.2 Fuse Bits
The ATmega128RFA1 has three Fuse bytes. Table 31-3 below – Table 31-5 on page
466 describe briefly the functionality of all the fuses and how they are mapped into theFuse bytes. Note that the fuses are read as logical zero, “0”, if they are programmed.
Table 31-3. Extended Fuse Byte
Fuse Low Byte

Bit NoDescription

Default Value

−

7

−

1

−

6

−

1

−

5

−

1

−

4

−

1

3

−

1

BODLEVEL2(1)

2

Brown-out Detector trigger level1 (un-programmed)

BODLEVEL1(1)

1

Brown-out Detector trigger level1 (un-programmed)

BODLEVEL0(1)0

Brown-out Detector trigger level1 (un-programmed)−

Notes:

1. See Table 34-23 on page 503 for BODLEVEL Fuse decoding.

Table 31-4. Fuse High Byte
Fuse High Byte

Description

Default Value

OCDEN

(4)

7

Enable On-chip debugging(OCD)

1 (un-programmed, OCD
disabled)

JTAGEN

6

Enable JTAG interface

0 (programmed, JTAG
enabled)(1)

5

Enable Serial Program and Data
Downloading (SPI)

0 (programmed, SPI
programming enabled)(3)

4

Watchdog Timer always on

1 (un-programmed)

SPIEN

WDTON

Bit No465
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Fuse High Byte

Bit NoDescription

Default ValueEESAVE

3

EEPROM memory is preserved
through the Chip Erase

1 (un-programmed,
EEPROM not preserved)

BOOTSZ1

2

Select Boot Size (see Table 30-7
on page 461 for details)

0 (programmed)

BOOTSZ0

1

Select Boot Size (see Table 30-7
on page 461for details)

0 (programmed)

BOOTRST

0

Select Reset Vector

1 (un-programmed)

Notes:(2)(2)

1. The SPIEN Fuse is not accessible in serial programming mode.
2. The default value of BOOTSZ1:0 results in maximum Boot Size. See Table 30-7
on page 461 for details.
3. See "WDTCSR – Watchdog Timer Control Register" on page 183 for details.
4. Never ship a product with the OCDEN Fuse programmed regardless of the settingof Lock bits and JTAGEN Fuse. A programmed OCDEN Fuse enables someparts of the clock system to be running in all sleep modes. This may increase thepower consumption.

Table 31-5. Fuse Low Byte
Fuse Low Byte

Description

Default Value

7

Divide clock by 80 (programmed)

CKOUT

6

Clock output

1 (un-programmed)

SUT1

5

Select start-up time

1 (un-programmed)

SUT0

4

Select start-up time

0 (programmed)CKSEL3

3

Select Clock source

0 (programmed)CKSEL2

2

Select Clock source

0 (programmed)CKSEL1

1

Select Clock source

1 (un-programmed)

Select Clock source

(2)

(4)

(3)

CKDIV8CKSEL0Notes:

Bit No

0

(1)

(1)

(2)

0 (programmed)

(2)
(2)

1. The default value of SUT1:0 results in maximum start-up time for the default clock
source. See "System Control and Reset" on page 176 for details.
2. The default setting of CKSEL3:0 results in internal RC Oscillator @ 8 MHz. See"Table 11-1" on page 148 for details.
3. The CKOUT Fuse allows the system clock to be output on PORTE7. See "ClockOutput Buffer" on page 152 for details.
4. See "System Clock Prescaler" on page 152 for details.

The status of the Fuse bits is not affected by Chip Erase. Note that the Fuse bits arelocked if Lock bit1 (LB1) is programmed. Program the Fuse bits before programmingthe Lock bits.
31.2.1 Latching of Fuses
The fuse values are latched when the device enters programming mode and changesof the fuse values will have no effect until the part leaves Programming mode. This
does not apply to the EESAVE Fuse which will take effect once it is programmed. The
fuses are also latched on Power-up in Normal mode.

31.3 Signature Bytes
All Atmel microcontrollers have a three-byte signature code which identifies the device.
This code can be read in both serial and parallel mode, also when the device is locked.

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ATmega128RFA1
The three bytes reside in a separate address space. For the ATmega128RFA1 thesignature bytes are given in Table 31-6 below. Accessing the signature bytes fromsoftware is described in section "Reading the Signature Row from Software" on page457.
Table 31-6. Device and JTAG ID
Signature Byte Number
Part
ATmega128RFA1

JTAG

0

1

2

Part Number

Manufacturer ID

0x1E

0xA7

0x01

0xA7010x1F

31.4 Calibration Byte
The ATmega128RFA1 has a byte calibration value for the internal RC Oscillator. This
byte resides in the high byte of address 0x000 in the signature address space. Duringreset, this byte is automatically written into the OSCCAL Register to ensure correct
frequency of the calibrated RC Oscillator.

31.5 Page Size
Table 31-7. Number of Words in a Page and Number of Pages in the FlashFlash Size

Page Size

PCWORDNo. ofPages

PCPAGEPCMSB

64k words (128k bytes)

128 words

PC[6:0]512

PC[15:7]

15

Table 31-8. Number of Bytes in a Page and Number of Pages in the EEPROM
EEPROM Size

Page Size

PCWORDNo. ofPages

PCPAGEEEAMSB

4k bytes

8 bytes

EEA[2:0]512

EEA[11:3]

11

31.6 Parallel Programming Parameters, Pin Mapping, and Commands
This section describes how to parallel program and verify Flash Program memory,
EEPROM Data memory, Memory Lock bits, and Fuse bits in the ATmega128RFA1.
31.6.1 Signal Names
In this section, some pins of the ATmega128RFA1 are referenced by signal names
describing their functionality during parallel programming; see Figure 31-1 on page 468
and Table 31-9 on page 468. Pins not described in this table are referenced by theirdefault pin names.
The XA1/XA0 pins determine the action executed when the CLKI pin is given a positive
pulse. The bit coding is shown in Table 31-12 on page 469.
_____
When pulsing WR or OE or, the command loaded determines the action executed. The
different commands are shown in Table 31-13 on page 469.

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Figure 31-1. Parallel Programming

Note:

(1)

1. Unused Pins should be left floating.

Table 31-9. Pin Name Mapping
Signal Name in
Programming Mode___
RDY/BSY
__
OE
___
WR

Pin Name

I/O

Function

PD1

O

0: Device is busy programming, 1: Device isready for new command.

PD2

I

Output Enable (Active low).

PD3

I

Write Pulse (Active low).

BS1

PD4

I

Byte Select 1.

XA0

PD5

I

XTAL Action Bit 0.

XA1

PD6

I

XTAL Action Bit 1.

PAGEL

PD7

I

Program Memory and EEPROM data Page
Load.

BS2

PE2

I

Byte Select 2.

DATA

PB7-0

I/O

Bi-directional Data bus (Output when ¯OE¯ ¯ islow).

Table 31-10. BS2 and BS1 Encoding

468

BS2

BS1

Flash / EEPROM
Address

Flash Data
Loading / Reading

Fuse
Programming

Reading Fuseand Lock Bits

00

Low Byte

Low Byte

Low Byte

Fuse Low Byte

01High Byte

High Byte

High Byte

Lock Bits

10

Extended High
Byte

Reserved

Extended Byte

Extended Fuse
Byte

1

1

Reserved

Reserved

Reserved

Fuse High Byte

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ATmega128RFA1
Table 31-11. Pin Values Used to Enter Programming Mode
Pin

Symbol

Value

PAGEL

Prog_enable[3]0

XA1

Prog_enable[2]0

XA0

Prog_enable[1]0BS1

Prog_enable[0]0Table 31-12. XA1 and XA0 Encoding
XA1

XA0

Action when CLKI is Pulsed

00

Load Flash or EEPROM Address (High or low address byte
determined by BS2 and BS1).

0

1

Load Data (High or Low data byte for Flash determined by
BS1).

1

0

Load Command.

1

1

No Action, Idle.

Table 31-13. Command Byte Bit Encoding
Command Byte

Command Executed1000 0000

Chip Erase

0100 0000

Write Fuse bits

0010 0000

Write Lock bits

0001 0000

Write Flash0001 0001

Write EEPROM

0000 1000

Read Signature bytes and Calibration byte

0000 0100

Read Fuse and Lock bits

0000 0010

Read Flash0000 0011

Read EEPROM

31.7 Parallel Programming
Pulses of CLKI and in the following command sequences are assumed to be at least
250 ns wide unless otherwise noted.
31.7.1 Enter Programming Mode
The following algorithm puts the device in parallel programming mode:
1. Apply 3.3V between DEVDD and DVSS.
2. Set RSTN to 0 and TST to 0.
3. Set the Prog_enable pins listed in Table 31-11 above to “0000” and wait at least
100ns.
4. Set TST to 1. TST can be set high any time before but not after the rising edge of
RSTN (tTSTRNH).
5. Set RSTN to 1. Any activity on Prog_enable pins within 100 ns after RSTN is set to 1
will cause the device to fail entering programming mode.
6. Wait at least 50 µs before sending a command.

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31.7.2 Considerations for Efficient Programming
The loaded command and address are retained in the device during programming. For
efficient programming, the following should be considered.
• The command needs only be loaded once when writing or reading multiple memory
locations.
• Skip writing the data value 0xFF, that is the contents of the entire EEPROM (unlessthe EESAVE Fuse is programmed) and Flash after a Chip Erase.
• Address high byte needs only be loaded before programming or reading a new 256
word window in Flash or 256 byte EEPROM. This consideration also applies to
Signature bytes reading.
31.7.3 Chip Erase(1)

The Chip Erase will erase the Flash and EEPROM
memories plus Lock bits. The
Lock bits are not reset until the program memory has been completely erased. The
Fuse bits are not changed. A Chip Erase must be performed before the Flash and/or
EEPROM are reprogrammed.
Note:

1. The EEPROM memory is preserved during Chip Erase if the EESAVE Fuse isprogrammed.

Load Command “Chip Erase”
1. Set XA1, XA0 to “10”. This enables command loading.
2. Set BS1 to “0”.
3. Set DATA to “1000 0000”. This is the command for Chip Erase.
4. Give CLKI a positive pulse. This loads the command.
______
5. Give WR a negative pulse. This starts the Chip Erase. RDY/ BSY goes low.
___
6. Wait until RDY/BSY goes high before loading a new command.
31.7.4 Programming the FlashThe Flash is organized in pages; see Table 31-7 on page 467. When programming theFlash, the program data is latched into a page buffer. This allows one page of program
data to be programmed simultaneously. The following procedure describes how toprogram the entire Flash memory:
A. Load Command “Write Flash”
1. Set XA1, XA0 to “10”. This enables command loading.
2. Set BS1 to “0”.
3. Set DATA to “0001 0000”. This is the command for Write Flash.
4. Give CLKI a positive pulse. This loads the command.
B. Load Address Low byte (Address bits 7:0)
1. Set XA1, XA0 to “00”. This enables address loading.
2. Set BS2, BS1 to “00”. This selects the address low byte.
3. Set DATA = Address low byte (0x00 - 0xFF).
4. Give CLKI a positive pulse. This loads the address low byte.

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ATmega128RFA1
C. Load Data Low Byte
1. Set XA1, XA0 to “01”. This enables data loading.
2. Set DATA = Data low byte (0x00 - 0xFF).
3. Give CLKI a positive pulse. This loads the data byte.
D. Load Data High Byte
1. Set BS1 to “1”. This selects high data byte.
2. Set XA1, XA0 to “01”. This enables data loading.
3. Set DATA = Data high byte (0x00 - 0xFF).
4. Give CLKI a positive pulse. This loads the data byte.
E. Latch Data
1. Set BS1 to “1”. This selects high data byte.
2. Give PAGEL a positive pulse. This latches the data bytes. (see Figure 31-3 on page472 for signal waveforms).
F. Repeat B through E until the entire buffer is filled or until all data within the page isloaded.
While the lower bits in the address are mapped to words within the page, the higher bits
address the pages within the FLASH. This is illustrated in Figure 31-5 on page 472.
Note that if less than eight bits are required to address words in the page (page size <256), the most significant bit(s) in the address low byte are used to address the page
when performing a Page Write.
G. Load Address High byte (Address bits15:8)
1. Set XA1, XA0 to “00”. This enables address loading.
2. Set BS2, BS1 to “01”. This selects the address high byte.
3. Set DATA = Address high byte (0x00 - 0xFF).
4. Give CLKI a positive pulse. This loads the address high byte.
H. Program Page
1. Set BS2, BS1 to “00”___
2. Give WR___ a negative pulse. This starts programming of the entire page of data.
RDY/BSY goes low.
___
3. Wait until RDY/BSY goes high (See Figure 31-3 on page 472 for signal waveforms).
I. Repeat B through H until the entire Flash is programmed or until all data has been
programmed.
J. End Page Programming
1. Set XA1, XA0 to “10”. This enables command loading.
2. Set DATA to “0000 0000”. This is the command for No Operation.
3. Give CLKI a positive pulse. This loads the command, and the internal write signals
are reset.

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Figure 31-5. Addressing the Flash which is Organized in Pages
PCMSB
PROGRAM
COUNTER(1)

PAGEMSB
PCPAGEPCWORD

PAGE ADDRESSWITHIN THE FLASH

WORD ADDRESSWITHIN A PAGE

PROGRAM MEMORY

PAGE

PAGE

INSTRUCTION WORD

PCWORD[PAGEMSB:0]:
00
01
02

PAGEEND

Note:

1. PCPAGE and PCWORD are listed in Table 31-7 on page 467.

Figure 31-3. Programming the Flash Waveforms

Note:

(1)

1. “XX” is don’t care. The letters refer to the programming description above.

31.7.5 Programming the EEPROM
The EEPROM is organized in pages; see Table 31-8 on page 467. When programming
the EEPROM, the program data is latched into a page buffer. This allows one page ofdata to be programmed simultaneously. The programming algorithm for the EEPROM
data memory is as follows (refer to "Programming the Flash" on page 470 for details on
Command, Address and Data loading):
1. A: Load Command “0001 0001”.
2. G: Load Address High Byte (0x00 - 0xFF).
3. B: Load Address Low Byte (0x00 - 0xFF).
4. C: Load Data (0x00 - 0xFF).
5. E: Latch data (give PAGEL a positive pulse).

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ATmega128RFA1
K: Repeat 3 through 5 until the entire buffer is filled.
L: Program EEPROM page
1. Set BS2, BS1 to “00”.
______
2. Give WR a negative pulse. This starts programming of the EEPROM page. RDY/BSY
goes low.
___
3. Wait until to RDY/BSY goes high before programming the next page (See Figure 317 below for signal waveforms).
Figure 31-7. Programming the EEPROM Waveforms
K

DATA

A

G

B

C

E

B

C

E

0x11

ADDR. HIGH

ADDR. LOW

DATA

XX

ADDR. LOW

DATA

XX

L

XA1
XA0
BS1
BS2
CLKI
WR
RDY/BSY
RSTN
OE
PAGEL

31.7.6 Reading the FlashThe algorithm for reading the Flash memory is as follows (refer to "Programming theFlash" on page 470 for details on Command and Address loading):
1. A: Load Command “0000 0010”.
2. G: Load Address High Byte (0x00 - 0xFF).
3. B: Load Address Low Byte (0x00 - 0xFF).
__
4. Set OE to “0”, and BS1 to “0”. The Flash word low byte can now be read at DATA.
5. Set BS1 to “1”. The Flash word high byte can now be read at DATA.
__
6. Set OE to “1”.
31.7.7 Reading the EEPROM
The algorithm for reading the EEPROM memory is as follows (refer to "Programming
the Flash" on page 470 for details on Command and Address loading):
1. A: Load Command “0000 0011”.
2. G: Load Address High Byte (0x00 - 0xFF).
3. B: Load Address Low Byte (0x00 - 0xFF).
__
4. Set OE to “0”, and BS1 to “0”. The EEPROM Data byte can now be read at DATA.
__
5. Set OE to “1”.
31.7.8 Programming the Fuse Low Bits
The algorithm for programming the Fuse Low bits is as follows (refer to "Programming
the Flash" on page 470 for details on Command and Data loading):
1. A: Load Command “0100 0000”.

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2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.
______
3. Give WR a negative pulse and wait for RDY/BSY to go high.
31.7.9 Programming the Fuse High Bits
The algorithm for programming the Fuse High bits is as follows (refer to "Programming
the Flash" on page 470 for details on Command and Data loading):
1. A: Load Command “0100 0000”.
2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.
3. Set BS2, BS1 to “01”. This selects high data byte.
______
4. Give WR a negative pulse and wait for RDY/BSY to go high.
5. Set BS2, BS1 to “00”. This selects low data byte.
31.7.10 Programming the Extended Fuse Bits
The algorithm for programming the Extended Fuse bits is as follows (refer to"Programming the Flash" on page 470 for details on Command and Data loading):
1. A: Load Command “0100 0000”.
2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.
3. Set BS2, BS1 to “10”. This selects extended data byte.
______
4. Give WR a negative pulse and wait for RDY/BSY to go high.
5. Set BS2, BS1 to “00”. This selects low data byte.
Figure 31-8. Programming the Fuses Waveforms

31.7.11 Programming the Lock Bits
The algorithm for programming the Lock bits is as follows (refer to "Programming theFlash" on page 470 for details on Command and Data loading):
1. A: Load Command “0010 0000”.
2. C: Load Data Low Byte. Bit n = “0” programs the Lock bit. If LB mode 3 is active(LB1 and LB2 are programmed), it is not possible to program the Boot Lock bits by
any External Programming mode.
______
3. Give WR a negative pulse and wait for RDY/BSY to go high.
The Lock bits can only be cleared by executing Chip Erase.

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31.7.12 Reading the Fuse and Lock Bits
The algorithm for reading the Fuse and Lock bits is as follows (refer to "Programming
the Flash" on page 470 for details on Command and Data loading):
1. A: Load Command “0000 0100”.
__
2. Set OE to “0”, and BS2, BS1 to “00”. The status of the Fuse Low bits can now beread at DATA (“0” means programmed).
__
3. Set OE to “0”, and BS2, BS1 to “11”. The status of the Fuse High bits can now beread at DATA (“0” means programmed).
__
4. Set OE to “0”, and BS2, BS1 to “10”. The status of the Extended Fuse bits can now
be read at DATA (“0” means programmed).
__
5. Set OE to “0”, and BS2, BS1 to “01”. The status of the Lock bits can now be read at
DATA (“0” means programmed).
__
6. Set OE to “1”.
Figure 31-9. Mapping between BS1, BS2 and the Fuse and Lock Bits during Read
Fuse Low Byte0

Extended Fuse Byte

1

0
DATA
BS2
0

Lock Bits

1

Fuse High Byte

1

BS1

BS2

31.7.13 Reading the Signature Bytes
The algorithm for reading the Signature bytes is as follows (refer to "Programming theFlash" on page 470 for details on Command and Data loading):
1. A: Load Command “0000 1000”.
2. B: Load Address Low Byte (0x00 - 0x02).
__
3. Set OE to “0” and BS to “0”. The selected Signature byte can now be read at DATA.
__
4. Set OE to “1”.
31.7.14 Reading the Calibration Byte
The algorithm for reading the Calibration byte is as follows (refer to "Programming theFlash" on page 470 for details on Command and Data loading):
1. A: Load Command “0000 1000”.
2. B: Load Address Low Byte, 0x00.
__
3. Set OE to “0” and BS1 to “1”. The Calibration byte can now be read at DATA.
__
4. Set OE to “1”.

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31.7.15 Parallel Programming Characteristics
Figure 31-10. Parallel programming timing including some general timing requirements
tXLWL
tXHXL

CLKI
tDVXH

tXLDX

Data & Control(DATA, XA0/1, BS1, BS2)tPLBX t BVWL

tBVPH
PAGEL

tWLBX

tPHPL
tWLWH

WR

tPLWL
WLRL

RDY/BSYtWLRHFigure 31-11. Parallel programming loading sequence with timing requirements
LOAD ADDRESS(LOW BYTE)LOAD DATA LOAD DATA(HIGH BYTE)LOAD DATA(LOW BYTE)

tXLPH

t XLXH(1)

LOAD ADDRESS(LOW BYTE)

tPLXH

CLKI

BS1

PAGEL

DATA

ADDR0 (Low Byte)

DATA (Low Byte)

DATA (High Byte)

ADDR1 (Low Byte)

XA0

XA1

Note:

1. The timing requirements shown in Figure 31-10 above (i.e., tDVXH, tXHXL, and tXLDX)
also apply to loading operation.

Figure 31-12. Parallel programming reading sequence (within the same page) with(1)
timing requirements
LOAD ADDRESS(LOW BYTE)

READ DATA(LOW BYTE)

READ DATA(HIGH BYTE)LOAD ADDRESS(LOW BYTE)

tXLOL

CLKI
tBVDV

BS1
tOLDV

OE

tOHDZ

DATA

ADDR0 (Low Byte)

DATA (Low Byte)

DATA (High Byte)

ADDR1 (Low Byte)

XA0

XA1

Note:

476

1. The timing requirements shown in Figure 31-10 above (i.e., tDVXH, tXHXL, and tXLDX)
also apply to reading operation.

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ATmega128RFA1
Table 31-14. Parallel Programming Characteristics, VDEVDD = 3.3V ± 10%
SymbolParameter

Min

tTSTRNH

Delay TST High before RSTN High

0

ns

tDVXH

Data and Control Valid before CLKI High

67

ns

tXLXH

CLKI Low to CLKI High

200

ns

tXHXL

CLKI Pulse Width High

150

ns

tXLDX

Data and Control Hold after CLKI Low___
CLKI Low to WR Low

67

ns

tXLWL

0

ns

tXLPH

CLKI Low to PAGEL high

0

ns

tPLXH

PAGEL low to CLKI high

150

ns

tBVPH

BS1 Valid before PAGEL High

67

ns

tPHPL

PAGEL Pulse Width High

150

ns

tPLBX

BS1 Hold after PAGEL Low___
BS2/1 Hold after WR Low___
PAGEL Low to WR Low___
BS2/1 Valid to WR Low___
WR Pulse Width Low______
WR Low to RDY/BSY Low
___
___
(1)
WR Low to RDY/BSY High
___
___
(2)
WR Low to RDY/BSY High for Chip Erase__
CLKI Low to OE Low

67

ns

67

ns

67

ns

67

ns

150

ns

tWLBX
tPLWL
tBVWL
tWLWH
tWLRL
tWLRH
tWLRH_CE
tXLOL
tBVDV
tOHDZ
Notes:

Max

Units

0

1

µs

3.7

4.5

ms

12

14.5

ms

0

BS1 Valid to DATA valid__
OE Low to DATA Valid__OE High to DATA Tri-stated

tOLDV

Typ

0

ns
250

ns

250

ns

250

ns

1. tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lockbits commands.
2. tWLRH_CE is valid for the Chip Erase command.

31.8 Serial Downloading
Both the Flash and EEPROM memory arrays can be programmed using a serial
programming bus while RSTN is pulled to DVSS. The serial programming interface
consists of pins SCK, PDI (input) and PDO (output). After RSTN is set low, theProgramming Enable instruction needs to be executed first before program/erase
operations can be executed. NOTE, in Table 31-15 below, the pin mapping for serial
programming is listed.
31.8.1 Serial Programming Pin Mapping
Table 31-15. Pin Mapping Serial Programming
SymbolPins

I/O

Description

PDI

PB2

I

Serial Data In

PDO

PB3

O

Serial Data Out

SCK

PB1

I

Serial Clock

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Figure 31-13. Serial Programming and Verify

Notes:(1)(2)

1. If the device is clocked by the internal Oscillator, it is not required to connect aclock source to the CLKI pin.
2. VDEVDD-0.3V < VEVDD < VDEVDD+0.3V, both VEVDD and VDEVDD must stay in valid
supply voltage limits.

When programming the EEPROM, an auto-erase cycle is built into the self-timed
programming operation (in the Serial mode ONLY) and there is no need to first execute
the Chip Erase instruction. The Chip Erase operation turns the content of every memory
location in both the Program and EEPROM arrays into 0xFF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and highperiods for the serial clock (SCK) input are defined as follows:
Low: > 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz;
High: > 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz;31.8.2 Serial Programming Algorithm
When writing serial data to the ATmega128RFA1, data is clocked on the rising edge of
SCK.
When reading data from the ATmega128RFA1, data is clocked on the falling edge of
SCK. See Figure 31-15 on page 481 for timing details.
To program and verify the ATmega128RFA1 in the serial programming mode, thefollowing sequence is recommended (See four byte instruction formats in Table 31-17
on page 479):
1. Power-up sequence: Apply power between DEVDD and DVSS while RSTN andSCK are set to “0”. In some systems, the programmer can not guarantee that SCK isheld low during power-up. In this case, RSTN must be given a positive pulse of atleast two CPU clock cycles duration after SCK has been set to “0”.
2. Wait for at least 20 ms and enable serial programming by sending the Programming
Enable serial instruction to pin PDI.
3. The serial programming instructions will not work if the communication is out ofsynchronization. When in sync. the second byte (0x53), will echo back when issuing
the third byte of the Programming Enable instruction. Whether the echo is correct or

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ATmega128RFA1
not, all four bytes of the instruction must be transmitted. If the 0x53 did not echo
back, give RSTN a positive pulse and issue a new Programming Enable command.
4. The Flash is programmed one page at a time. The memory page is loaded one byte
at a time by supplying the 7 LSB of the address and data together with the Load
Program Memory Page instruction. To ensure correct loading of the page, the data
low byte must be loaded before data high byte is applied for a given address. The
Program Memory Page is stored by loading the Write Program Memory Page
instruction with the address lines 15:8. If polling (RDY/BSY¯ ¯ ¯ ) is not used, the user
must wait at least tWD_FLASH before issuing the next page (see Table 31-16 below).
Accessing the serial programming interface before the Flash write operation
completes can result in incorrect programming.
5. The EEPROM array is programmed one byte at a time by supplying the address anddata together with the appropriate Write instruction. An EEPROM memory location is
first automatically erased before new data is written. If polling is not used, the user
must wait at least tWD_EEPROM before issuing the next byte (see Table 31-16 below).
In a chip erased device, no 0xFFs in the data file(s) need to be programmed.
6. Any memory location can be verified by using the Read instruction which returns thecontent at the selected address at serial output PDO.
7. At the end of the programming session, RSTN can be set high to commence normal
operation.
8. Power-off sequence (if needed): Set RESET to “1”. Turn DEVDD power off.
Table 31-16. Minimum Wait Delay before Writing the Next Flash or EEPROM Location
SymbolMinimum Wait DelaytWD_FLASH

4.5 mstWD_EEPROM

9 ms

tWD_CHIPERASE

14.5 ms

31.8.3 Serial Programming Instruction Set
Table 31-17 below and Figure 31-14 on page 480 describe the Instruction set.
Table 31-17. Serial Programming Instruction Set(4)(5)

Instruction Format(1)

Instruction/Operation

Byte1

Byte2

Byte3

Byte4

Programming Enable

$AC

$53

$00

$00

Chip Erase (Program Memory/EEPROM)

$AC

$80

$00

$00

Poll RDY/BSY
¯¯¯

$F0

$00

$00

data byte out

Load Program Memory Page, High Byte

$48

$00

addr. LSB

high data byte inLoad Program Memory Page, Low Byte

$40

$00

addr. LSB

low data byte inLoad EEPROM Memory Page (page access)

$C1

$00

0000 000aa

data byte inRead Program Memory, High byte

$28

addr. MSB

addr. LSB

high data byte out

Read Program Memory, Low byte

$20

addr. MSB

addr. LSB

low data byte out

Read EEPROM Memory$A00000 aaaa

aaaa aaaa

data byte out

Read Lock Bits

$58

$00

$00

data byte out

Read Signature Byte

$30

$00

0000 000aa

data byte out

Load Instruction

Read Instruction

479
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Instruction Format(1)

Read Fuse Bits

$50

$00

$00

data byte out

Read Fuse High Bits

$58

$08

$00

data byte out

Read Extended Fuse Bits

$50

$08

$00

data byte out

Read Calibration Byte

$38

$00

$00

data byte out

Write Program Memory Page

$4C

addr. MSB

addr. LSB

$00

Write EEPROM Memory$C00000 aaaa

aaaa aaaa

data byte in

Write EEPROM Memory Page (page access)$C20000 aaaa

aaaa 00$00

Write Lock Bits

$AC

$E0

$00

data byte in

Write Fuse Bits

$AC

$A0

$00

data byte in

Write Fuse High Bits

$AC

$A8

$00

data byte in

Write Extended Fuse Bits

$AC

$A4

$00

data byte in

Write Instructions

Notes:(2)(3)

1. a = address.
2. Bits are programmed ‘0’, un-programmed ‘1’.
3. To ensure future compatibility, unused Fuses and Lock bits should be un-programmed (‘1’).
4. Refer to the corresponding section for Fuse and Lock bits, Calibration and Signature bytes and Page size.
5. See http://www.atmel.com/avr for Application Notes regarding programming and programmers.

If the LSB in RDY/BSY¯ ¯ ¯ data byte out is ‘1’, a programming operation is still pending.
Wait until this bit returns ‘0’ before the next instruction is carried out. Within the same
page, the low data byte must be loaded prior to the high data byte. After data is loaded
to the page buffer, program the EEPROM page; see Figure 31-14 below.
Figure 31-14. Serial Programming Instruction Example
Serial Programming Instruction
Load Program Memory Page (High/Low Byte)/
Load EEPROM Memory Page (page access)

Byte 1

Bit 15 B

Byte 2Byte 3

Adr MSB

Adr LSB

Write Program Memory Page/
Write EEPROM Memory Page

Byte 1

Byte 4

Byte 2Byte 3

Adr MSB

Adr LSB

Bit 15 B

0

Byte 40

Page Buffer
Page Offset

Page 0Page 1Page 2
Page Number

Page N-1

Program Memory/
EEPROM Memory

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ATmega128RFA1
31.8.4 Serial Programming Characteristics
For characteristics of the Serial Programming module see "SPI Timing Characteristics"
on page 504.
Figure 31-15. Serial Programming Waveforms
SERIAL DATA INPUT(MOSI)MSBLSBSERIAL DATA OUTPUT(MISO)MSBLSBSERIAL CLOCK INPUT(SCK)SAMPLE31.9 Programming via the JTAG Interface
Programming through the JTAG interface requires control of the four JTAG specificpins: TCK, TMS, TDI, and TDO. Control of the reset and clock pins is not required.
To be able to use the JTAG interface, the JTAGEN Fuse must be programmed. The
device is default shipped with the fuse programmed. In addition, the JTD bit in MCUCR
must be cleared. Alternatively, if the JTD bit is set, the external reset can be forced low.
Then, the JTD bit will be cleared after two chip clocks, and the JTAG pins are available
for programming. This provides a means of using the JTAG pins as normal port pins inrunning mode while still allowing In-System Programming via the JTAG interface. Notethat this technique can not be used when using the JTAG pins for Boundary-scan or
On-chip Debug. In these cases the JTAG pins must be dedicated for this purpose.
During programming the clock frequency of the TCK Input must be less than the
maximum frequency of the chip. The System Clock Prescaler can not be used to divide
the TCK Clock Input into a sufficiently low frequency.
As a definition in this datasheet, the LSB is shifted in and out first of all Shift Registers.
31.9.1 Programming Specific JTAG Instructions
The Instruction Register is 4-bit wide, supporting up to 16 instructions. The JTAG
instructions useful for programming are listed below.
The OPCODE for each instruction is shown behind the instruction name in hex format.
The text describes which Data Register is selected as path between TDI and TDO foreach instruction.
The Run-Test/Idle state of the TAP-controller is used to generate internal clocks. It canalso be used as an idle state between JTAG sequences. The state machine sequence
for changing the instruction word is shown in Figure 31-16 on page 482.

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Figure 31-16. State Machine Sequence for Changing the Instruction Word
1

Test-Logic-Reset
00

Run-Test/Idle

1

Select-DR Scan

1

Select-IR Scan

0
1

0
1

Capture-DR

Capture-IR00

Shift-DR

Shift-IR

0

1
1

1

Exit1-IR

0

0
Pause-IR

0

Pause-DR
1

0

1
0

Exit2-DR

Exit2-IR1

1
Update-IR

Update-DR1

0

1

Exit1-DR

0

1

0

1

0

31.9.2 AVR_RESET (0xC)
The AVR specific public JTAG instruction is used for setting the AVR device in the
Reset mode or taking the device out from the Reset mode. The TAP-controller is notreset by this instruction. The one bit Reset Register is selected as Data Register. Notethat the reset will be active as long as there is a logic “one” in the Reset Chain. The
output from this chain is not latched.
The active states are:
• Shift-DR: The Reset Register is shifted by the TCK input.
31.9.3 PROG_ENABLE (0x4)
The AVR specific public JTAG instruction enables programming via the JTAG port. The
16-bit Programming Enable Register is selected as Data Register. The active states are
the following:• Shift-DR: The programming enable signature is shifted into the Data Register.

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ATmega128RFA1• Update-DR: The programming enable signature is compared to the correct value,
and Programming mode is entered if the signature is valid.
31.9.4 PROG_COMMANDS (0x5)
The AVR specific public JTAG instruction is used for entering programming commands
via the JTAG port. The 15-bit Programming Command Register is selected as Data
Register. The active states are the following:• Capture-DR: The result of the previous command is loaded into the Data Register.
• Shift-DR: The Data Register is shifted by the TCK input, shifting out the result of theprevious command and shifting in the new command.
• Update-DR: The programming command is applied to the Flash inputs.
• Run-Test/Idle: One clock cycle is generated, executing the applied command.
31.9.5 PROG_PAGELOAD (0x6)
The AVR specific public JTAG instruction directly loads the Flash data page via the
JTAG port. An 8-bit Flash Data Byte Register is selected as the Data Register. This is
physically the 8 LSB’s of the Programming Command Register. The active states are
the following:• Shift-DR: The Flash Data Byte Register is shifted by the TCK input.
• Update-DR: The content of the Flash Data Byte Register is copied into a temporary
register. A write sequence is initiated that within 11 TCK cycles loads the content of
the temporary register into the Flash page buffer. The AVR automatically alternates
between writing the low and the high byte for each new Update-DR state, startingwith the low byte for the first Update-DR encountered after entering the
PROG_PAGELOAD command. The Program Counter is pre-incremented before
writing the low byte, except for the first written byte. This ensures that the first data is
written to the address set up by PROG_COMMANDS, and loading the last locationin the page buffer does not make the program counter increment into the next page.
31.9.6 PROG_PAGEREAD (0x7)
The AVR specific public JTAG instruction directly captures the Flash content via the
JTAG port. An 8-bit Flash Data Byte Register is selected as the Data Register. This is
physically the 8 LSB’s of the Programming Command Register. The active states are
the following:• Capture-DR: The content of the selected Flash byte is captured into the Flash Data
Byte Register. The AVR automatically alternates between reading the low and thehigh byte for each new Capture-DR state, starting with the low byte for the first
Capture-DR encountered after entering the PROG_PAGEREAD command. The
Program Counter is post-incremented after reading each high byte, including the firstread byte. This ensures that the first data is captured from the first address set up by
PROG_COMMANDS, and reading the last location in the page makes the program
counter increment into the next page.
• Shift-DR: The Flash Data Byte Register is shifted by the TCK input.
31.9.7 Data Registers
The Data Registers are selected by the JTAG instruction registers described in section"Programming Specific JTAG Instructions" on page 481. The Data Registers relevant
for programming operations are:
• Reset Register

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• Programming Enable Register• Programming Command Register• Flash Data Byte Register
31.9.8 Reset Register
The Reset Register is a Test Data Register used to reset the part during programming.
It is required to reset the part before entering Programming mode.
A high value in the Reset Register corresponds to pulling the external reset low. The
part is reset as long as there is a high value present in the Reset Register. Dependingon the Fuse settings for the clock options, the part will remain reset for a Reset Timeout period (refer to "Clock Sources" on page 148) after releasing the Reset Register.
The output from this Data Register is not latched, so the reset will take place
immediately, as shown in "Figure 29-2" on page 443.
31.9.9 Programming Enable Register
The Programming Enable Register is a 16-bit register. The content of this register iscompared to the programming enable signature, binary code 1010_0011_0111_0000.
When the content of the register is equal to the programming enable signature,
programming via the JTAG port is enabled. The register is reset to 0 on Power-on
Reset, and should always be reset when leaving Programming mode.
Figure 31-17. Programming Enable Register
TDI

D
A
T
A

0xA370=D

Q

Programming Enable

ClockDR & PROG_ENABLE

TDO

31.9.10 Programming Command Register
The Programming Command Register is a 15-bit register. This register is used toserially shift in programming commands, and to serially shift out the result of theprevious command, if any. The JTAG Programming Instruction Set is shown in Table
31-18 on page 485. The state sequence when shifting in the programming commands
is illustrated in Figure 31-19 on page 488.

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ATmega128RFA1
Figure 31-18. Programming Command Register
TDI

S
T
R
O
B
E
S

A
D
D
R
E
S
S
/
D
A
T
A

Flash
EEPROM
Fuses
Lock Bits

TDO

Table 31-18. JTAG Programming Instruction (set a = address high bits, b = address low bits, c = address extended bits,
H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care)
Instruction

TDI Sequence

TDO Sequence

Notes

1a. Chip Erase

0100011_10000000
0110001_10000000
0110011_10000000
0110011_10000000

xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx

1b. Poll for Chip Erase Complete

0110011_10000000

xxxxxox_xxxxxxxx

2a. Enter Flash Write

0100011_00010000xxxxxxx_xxxxxxxx

2b. Load Address Extended High Byte

0001011_cccccccc

xxxxxxx_xxxxxxxx

2c. Load Address High Byte

0000111_aaaaaaaa

xxxxxxx_xxxxxxxx

2d. Load Address Low Byte

0000011_bbbbbbbb

xxxxxxx_xxxxxxxx

2e. Load Data Low Byte

0010011_iiiiiiii

xxxxxxx_xxxxxxxx

2f. Load Data High Byte

0010111_iiiiiiii

xxxxxxx_xxxxxxxx

2g. Latch Data

0110111_00000000
1110111_00000000
0110111_00000000

xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx(1)2h. Write Flash Page

0110111_00000000
0110101_00000000
0110111_00000000
0110111_00000000

xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx(1)2i. Poll for Page Write Complete

0110111_00000000

xxxxxox_xxxxxxxx(2)3a. Enter Flash Read

0100011_00000010

xxxxxxx_xxxxxxxx

3b. Load Address Extended High Byte

0001011_cccccccc

xxxxxxx_xxxxxxxx

3c. Load Address High Byte

0000111_aaaaaaaa

xxxxxxx_xxxxxxxx

3d. Load Address Low Byte

0000011_bbbbbbbb

xxxxxxx_xxxxxxxx

3e. Read Data Low and High Byte

0110010_00000000
0110110_00000000
0110111_00000000

xxxxxxx_xxxxxxxx
xxxxxxx_oooooooo
xxxxxxx_oooooooo

(2)

(10)

(10)

Low byte
High byte

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Instruction

TDI Sequence

TDO Sequence

Notes

4a. Enter EEPROM Write

0100011_00010001

xxxxxxx_xxxxxxxx

4b. Load Address High Byte

0000111_aaaaaaaa

xxxxxxx_xxxxxxxx

4c. Load Address Low Byte

0000011_bbbbbbbb

xxxxxxx_xxxxxxxx

4d. Load Data Byte

0010011_iiiiiiii

xxxxxxx_xxxxxxxx

4e. Latch Data

0110111_00000000
1110111_00000000
0110111_00000000

xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx(1)

4f. Write EEPROM Page

0110011_00000000
0110001_00000000
0110011_00000000
0110011_00000000

xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx(1)

4g. Poll for Page Write Complete

0110011_00000000

xxxxxox_xxxxxxxx(2)5a. Enter EEPROM Read

0100011_00000011

xxxxxxx_xxxxxxxx

5b. Load Address High Byte

0000111_aaaaaaaa

xxxxxxx_xxxxxxxx

5c. Load Address Low Byte

0000011_bbbbbbbb

xxxxxxx_xxxxxxxx

5d. Read Data Byte

0110011_bbbbbbbb
0110010_00000000
0110011_00000000

xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_oooooooo

6a. Enter Fuse Write

0100011_01000000

xxxxxxx_xxxxxxxx

(10)

(10)

6b. Load Data Low Byte

0010011_iiiiiiii

xxxxxxx_xxxxxxxx(3)(6)

6c. Write Fuse Extended Byte

0111011_00000000
0111001_00000000
0111011_00000000
0111011_00000000

xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx(1)

6d. Poll for Fuse Write Complete

0110111_00000000

xxxxxox_xxxxxxxx(2)

6e. Load Data Low Byte

0010011_iiiiiiii

xxxxxxx_xxxxxxxx(3)(7)

6f. Write Fuse High Byte

0110111_00000000
0110101_00000000
0110111_00000000
0110111_00000000

xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx(1)

6g. Poll for Fuse Write Complete

0110111_00000000

xxxxxox_xxxxxxxx(2)

6h. Load Data Low Byte

0010011_iiiiiiii

xxxxxxx_xxxxxxxx(3)(8)

6i. Write Fuse Low Byte

0110011_00000000
0110001_00000000
0110011_00000000
0110011_00000000

xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx(1)

6j. Poll for Fuse Write Complete

0110011_00000000

xxxxxox_xxxxxxxx(2)

7a. Enter Lock Bit Write

0100011_00100000

xxxxxxx_xxxxxxxx

7b. Load Data Byte

0010011_11iiiiii

xxxxxxx_xxxxxxxx(4)(9)

7c. Write Lock Bits

0110011_00000000
0110001_00000000
0110011_00000000
0110011_00000000

xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx(1)

7d. Poll for Lock Bit Write complete

0110011_00000000

xxxxxox_xxxxxxxx

(2)

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ATmega128RFA1
Instruction

TDI Sequence

TDO Sequence

Notes

8a. Enter Fuse/Lock Bit Read

0100011_00000100

xxxxxxx_xxxxxxxx

8b. Read Extended Fuse Byte

0111010_00000000
0111011_00000000

xxxxxxx_xxxxxxxx
xxxxxxx_oooooooo(6)(5)

8c. Read Fuse High Byte

0111110_00000000
0111111_00000000

xxxxxxx_xxxxxxxx
xxxxxxx_oooooooo(7)(5)

8d. Read Fuse Low Byte

0110010_00000000
0110011_00000000

xxxxxxx_xxxxxxxx
xxxxxxx_oooooooo(8)(5)

8e. Read Lock Bits

0110110_00000000
0110111_00000000

xxxxxxx_xxxxxxxx
xxxxxxx_xxoooooo(9)(5)

8f. Read Fuses and Lock Bits

0111010_00000000
0111110_00000000
0110010_00000000
0110110_00000000
0110111_00000000

xxxxxxx_xxxxxxxx
xxxxxxx_oooooooo
xxxxxxx_oooooooo
xxxxxxx_oooooooo
xxxxxxx_oooooooo(5)
Fuse Ext. byte
Fuse High byte
Fuse Low byte
Lock bits

9a. Enter Signature Byte Read

0100011_00001000

xxxxxxx_xxxxxxxx

9b. Load Address Byte

0000011_bbbbbbbb

xxxxxxx_xxxxxxxx

9c. Read Signature Byte

0110010_00000000
0110011_00000000

xxxxxxx_xxxxxxxx
xxxxxxx_oooooooo

10a. Enter Calibration Byte Read

0100011_00001000

xxxxxxx_xxxxxxxx

10b. Load Address Byte

0000011_bbbbbbbb

xxxxxxx_xxxxxxxx

10c. Read Calibration Byte

0110110_00000000
0110111_00000000

xxxxxxx_xxxxxxxx
xxxxxxx_oooooooo

11a. Load No Operation Command

0100011_00000000
0110011_00000000

xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx

Notes:

1. This command sequence is not required if the seven MSB’s are correctly set by the previous command sequence(which is normally the case).
2. Repeat until o = “1”.
3. Set bits to “0” to program the corresponding Fuse, “1” to un-program the Fuse.
4. Set bits to “0” to program the corresponding Lock bit, “1” to leave the Lock bit unchanged.
5. “0” = programmed, “1” = un-programmed.
6. The bit mapping for Fuses Extended byte is listed in Table 31-3 on page 465.
7. The bit mapping for Fuses High byte is listed in Table 31-4 on page 465.
8. The bit mapping for Fuses Low byte is listed in Table 31-5 on page 466
9. The bit mapping for Lock bits byte is listed in Table 31-1 on page 464.
10. Address bits exceeding PCMSB and EEAMSB (Table 31-7 on page 467 and Table 31-8 on page 467) are don’t care.
11. All TDI and TDO sequences are represented by binary digits.

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Figure 31-19. State Machine Sequence for Changing/Reading the Data Word
1

Test-Logic-Reset
00

Run-Test/Idle

1

Select-DR Scan

1

Select-IR Scan

0
1

0
1

Capture-DR

Capture-IR00

Shift-DR

Shift-IR

0

1
1

1

Exit1-IR

0

0

Pause-DR

0

0

Pause-IR1

1
0

Exit2-DR

Exit2-IR1

1

Update-DR1

0

1

Exit1-DR

0

1

Update-IR01031.9.11 Flash Data Byte Register
The Flash Data Byte Register provides an efficient way to load the entire Flash page
buffer before executing Page Write, or to read out/verify the content of the Flash. A
state machine sets up the control signals to the Flash and senses the strobe signals
from the Flash, thus only the data words need to be shifted in/out.
The Flash Data Byte Register actually consists of the 8-bit scan chain and an 8-bit
temporary register. During page load, the Update-DR state copies the content of thescan chain over to the temporary register and initiates a write sequence that within 11
TCK cycles loads the content of the temporary register into the Flash page buffer. The
AVR automatically alternates between writing the low and the high byte for each new
Update-DR state, starting with the low byte for the first Update-DR encountered after
entering the PROG_PAGELOAD command. The Program Counter is pre-incremented
before writing the low byte, except for the first written byte. This ensures that the firstdata is written to the address set up by PROG_COMMANDS, and loading the lastlocation in the page buffer does not make the Program Counter increment into the next
page.

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ATmega128RFA1During Page Read, the content of the selected Flash byte is captured into the Flash
Data Byte Register during the Capture-DR state. The AVR automatically alternates
between reading the low and the high byte for each new Capture-DR state, starting withthe low byte for the first Capture-DR encountered after entering the
PROG_PAGEREAD command. The Program Counter is post-incremented after readingeach high byte, including the first read byte. This ensures that the first data is captured
from the first address set up by PROG_COMMANDS, and reading the last location in
the page makes the program counter increment into the next page.
Figure 31-20. Flash Data Byte Register
STROBESTDI

State
MachineADDRESSFlash
EEPROM
Fuses
Lock Bits
D
A
T
A

TDO

The state machine controlling the Flash Data Byte Register is clocked by TCK. During
normal operation in which eight bits are shifted for each Flash byte, the clock cycles
needed to navigate through the TAP-controller automatically feeds the state machinefor the Flash Data Byte Register with sufficient number of clock pulses to complete its
operation transparently for the user. However, if too few bits are shifted between each
Update-DR state during page load, the TAP-controller should stay in the Run-Test/Idle
state for some TCK cycles to ensure that there are at least 11 TCK cycles between
each Update-DR state.
31.9.12 Programming Algorithm
All references below of type “1a”, “1b”, and so on, refer to Table 31-18 on page 485.
31.9.13 Entering Programming Mode
1. Enter JTAG instruction AVR_RESET and shift 1 in the Reset Register.
2. Enter instruction PROG_ENABLE and shift 0b1010_0011_0111_0000 in the
Programming Enable Register.
31.9.14 Leaving Programming Mode
1. Enter JTAG instruction PROG_COMMANDS.
2. Disable all programming instructions by using no operation instruction 11a.
3. Enter instruction PROG_ENABLE and shift 0b0000_0000_0000_0000 in the
programming Enable Register.
4. Enter JTAG instruction AVR_RESET and shift 0 in the Reset Register.

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31.9.15 Performing Chip Erase
1. Enter JTAG instruction PROG_COMMANDS.
2. Start Chip Erase using programming instruction 1a.
3. Poll for Chip Erase complete using programming instruction 1b, or wait for tWLRH_CE(refer to Table 31-14 on page 477).
31.9.16 Programming the Flash
Before programming the Flash a Chip Erase must be performed, see section"Performing Chip Erase" above.
1. Enter JTAG instruction PROG_COMMANDS.
2. Enable Flash write using programming instruction 2a.
3. Load High byte of address using programming instruction 2c.
4. Load Low byte of address using programming instruction 2d.
5. Load data using programming instructions 2e, 2f and 2g.
6. Repeat steps 5 and 6 for all instruction words in the page.
7. Write the page using programming instruction 2h.
8. Poll for Flash write complete using programming instruction 2i, or wait for tWLRH (refer
to Table 31-14 on page 477).
9. Repeat steps 3 to 8 until all data have been programmed.
A more efficient data transfer can be achieved using the PROG_PAGELOAD
instruction:
1. Enter JTAG instruction PROG_COMMANDS.
2. Enable Flash write using programming instruction 2a.
3. Load the page address using programming instructions 2c and 2d. PCWORD (refer
to Table 31-7 on page 467) is used to address within one page and must be written
as 0.
4. Enter JTAG instruction PROG_PAGELOAD.
5. Load the entire page by shifting in all instruction words in the page byte-by-byte,
starting with the LSB of the first instruction in the page and ending with the MSB ofthe last instruction in the page. Use Update-DR to copy the contents of the Flash
Data Byte Register into the Flash page location and to auto-increment the Program
Counter before each new word.
6. Enter JTAG instruction PROG_COMMANDS.
7. Write the page using programming instruction 2h.
8. Poll for Flash write complete using programming instruction 2i, or wait for tWLRH (refer
to Table 31-14 on page 477).
9. Repeat steps 3 to 8 until all data have been programmed.
31.9.17 Reading the Flash
1. Enter JTAG instruction PROG_COMMANDS.
2. Enable Flash read using programming instruction 3a.
3. Load address using programming instructions 3c and 3d.
4. Read data using programming instruction 3e.
5. Repeat steps 3 and 4 until all data have been read.
A more efficient data transfer can be achieved using the PROG_PAGEREAD
instruction:
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ATmega128RFA1
1. Enter JTAG instruction PROG_COMMANDS.
2. Enable Flash read using programming instruction 3a.
3. Load the page address using programming instructions 3c and 3d. PCWORD (refer
to Table 31-7 on page 467) is used to address within one page and must be written
as 0.
4. Enter JTAG instruction PROG_PAGEREAD.
5. Read the entire page (or Flash) by shifting out all instruction words in the page (orFlash), starting with the LSB of the first instruction in the page (Flash) and ending
with the MSB of the last instruction in the page (Flash). The Capture-DR state both
captures the data from the Flash, and also auto-increments the program counter
after each word is read. Note that Capture-DR comes before the shift-DR state.
Hence, the first byte which is shifted out contains valid data.
6. Enter JTAG instruction PROG_COMMANDS.
7. Repeat steps 3 to 6 until all data have been read.
31.9.18 Programming the EEPROM
Before programming the EEPROM a Chip Erase must be performed, see "Performing
Chip Erase" on page 490.
1. Enter JTAG instruction PROG_COMMANDS.
2. Enable EEPROM write using programming instruction 4a.
3. Load High byte of address using programming instruction 4b.
4. Load Low byte of address using programming instruction 4c.
5. Load data using programming instructions 4d and 4e.
6. Repeat steps 4 and 5 for all data bytes in the page.
7. Write the data using programming instruction 4f.
8. Poll for EEPROM write complete using programming instruction 4g, or wait for tWLRH(refer to Table 31-14 on page 477).
9. Repeat steps 3 to 8 until all data have been programmed.
Note that the PROG_PAGELOAD instruction can not be used when programming the
EEPROM.
31.9.19 Reading the EEPROM
1. Enter JTAG instruction PROG_COMMANDS.
2. Enable EEPROM read using programming instruction 5a.
3. Load address using programming instructions 5b and 5c.
4. Read data using programming instruction 5d.
5. Repeat steps 3 and 4 until all data have been read.
Note that the PROG_PAGEREAD instruction can not be used when reading the
EEPROM.
31.9.20 Programming the Fuses
1. Enter JTAG instruction PROG_COMMANDS.
2. Enable Fuse write using programming instruction 6a.
3. Load data high byte using programming instructions 6b. A bit value of “0” will
program the corresponding fuse; a “1” will un-program the fuse.
4. Write Fuse High byte using programming instruction 6c.

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5. Poll for Fuse write complete using programming instruction 6d, or wait for tWLRH(refer to Table 31-14 on page 477).
6. Load data low byte using programming instructions 6e. A “0” will program the fuse, a“1” will un-program the fuse.
7. Write Fuse low byte using programming instruction 6f.
8. Poll for Fuse write complete using programming instruction 6g, or wait for tWLRH(refer to Table 31-14 on page 477).
31.9.21 Programming the Lock Bits
1. Enter JTAG instruction PROG_COMMANDS.
2. Enable Lock bit write using programming instruction 7a.
3. Load data using programming instructions 7b. A bit value of “0” will program thecorresponding lock bit, a “1” will leave the lock bit unchanged.
4. Write Lock bits using programming instruction 7c.
5. Poll for Lock bit write complete using programming instruction 7d, or wait for tWLRH(refer to Table 31-14 on page 477).
31.9.22 Reading the Fuses and Lock Bits
1. Enter JTAG instruction PROG_COMMANDS.
2. Enable Fuse/Lock bit read using programming instruction 8a.
3. To read all Fuses and Lock bits, use programming instruction 8e.
To only read Fuse High byte, use programming instruction 8b.
To only read Fuse Low byte, use programming instruction 8c.
To only read Lock bits, use programming instruction 8d.
31.9.23 Reading the Signature Bytes
1. Enter JTAG instruction PROG_COMMANDS.
2. Enable Signature byte read using programming instruction 9a.
3. Load address 0x00 using programming instruction 9b.
4. Read first signature byte using programming instruction 9c.
5. Repeat steps 3 and 4 with address 0x01 and address 0x02 to read the second andthird signature bytes, respectively.
31.9.24 Reading the Calibration Byte
1. Enter JTAG instruction PROG_COMMANDS.
2. Enable Calibration byte read using programming instruction 10a.
3. Load address 0x00 using programming instruction 10b.
4. Read the calibration byte using programming instruction 10c.

492

ATmega128RFA1
8266A-MCU Wireless-12/09

ATmega128RFA1
32 Application Circuits
32.1 Basic Application Schematic
A basic application schematic of the ATmega128RFA1 with a single-ended RFconnector is shown in Figure 32-1 below. The 50Ω single-ended RF input istransformed to the 100Ω differential RF port impedance using Balun B1. The capacitors
C1 and C2 provide AC coupling of the RF input to the RF port, capacitor C4 improvesmatching.
Figure 32-1. Basic Application schematic (Table 32-1 on page 494)
CX1

XTAL

CX2

CB2

59

58

57

56

AVDD

EVDD

AVSS

XTAL1

XTAL2

55

54

53
PE7

61 60

DVSS

62

DEVDD

63

AREF

1

CB1

AVSS

64

CR1

PF0

VDD

2

52

51

50

49
48
47

3

PE0 46

4

DVSS 455

DEVDD 44
PB7 436 PF7
7 AVSS

C1
RF

42

8 RFP
B1
C4
C2

41

ATmega128RFA1

9 RFN

40

10 AVSS

39

11 TST

38

12 RSTN37

13 RSTON

PB0 36

14 PG0

DVSS 35

CX3

XTAL
32kHz

DEVDD

DVSS

PD0

19

20

21

22

23

24

25

CB3

CB4

PD7

DVDD

18

DVDD

17

DVSS

16

DEVDD 34

PG5

15

26

27

28

29

30

31

33 CLKI

32

VDD

CX4

The power supply bypass capacitors (CB2, CB4) are connected to the external analog
supply pin (EVDD, pin 59) and external digital supply pin (DEVDD, pin 23). Pins 34, 44
and 54 supply the digital port pins.
Capacitors CB1 and CB3 are bypass capacitors for the integrated analog and digital
voltage regulators to ensure stable operation and to improve noise immunity.
Capacitors should be placed as close as possible to the pins and should have a lowresistance and low-inductance connection to ground to achieve the best performance.

493
8266A-MCU Wireless-12/09

The crystal (XTAL), the two load capacitors (CX1, CX2), and the internal circuitry
connected to pins XTAL1 and XTAL2 form the 16MHz crystal oscillator for the 2.4GHz
transceiver. To achieve the best accuracy and stability of the reference frequency, large
parasitic capacitances must be avoided. Crystal lines should be routed as short as
possible and not in proximity of digital I/O signals. This is especially required for theHigh Data Rate Modes.
The 32.768 kHz crystal connected to the internal low power (sub 1µA) crystal oscillator
provides a stable time reference for all low power modes including 32 Bit IEEE 802.15.4
Symbol Counter ("MAC Symbol Counter" on page 133) and real time clock application
using the asynchronous timer T/C2 ("8-bit Timer/Counter2 with PWM and
Asynchronous Operation" on page 309). Total capacitance including CX3, CX4 should
not exceed 15pF on both pins. The very low supply current of the oscillator requires
careful layout of the PCB and any leakage path must be avoided.
Crosstalk and radiation from switching digital signals to the crystal pins or the RF pins
can degrade the system performance. The programming of minimum drive strength
settings for the digital output signal is recommended (see "DPDS0 – Port DriverStrength Register 0" on page 174).

Table 32-1. Example Bill of Materials (BoM) for "Basic Application Schematic" on page 493
Designator

Description

Value

Manufacturer

Part Number

Comment

B1

SMD balun
SMD balun / filter

2.4 GHz

WuerthJohansonTechnology

748421245
2450FB15L0001

Filter included

0603YD105KAT2A
GRM188R61C105KA12D

X5R(0603)

10%

16V

CB1
CB3

LDO VREG
bypass capacitor

1 µF
AVX
(100nF minimum) Murata

CB2
CB4

Power supply bypass
capacitor

1 µF(100nF minimum)

CX1, CX2

Crystal load capacitor

12 pF

AVX
Murata06035A120JA
GRP1886C1H120JA01

COG(0603)

5%50V

C1, C2

RF coupling capacitor

22 pF

Epcos
Epcos
AVX

B37930
B3792006035A220JAT2A

C0G

5%

50V

C4 (optional) RF matching

0.47 pF

R1

CLKM low-passfilter resistor

680Ω

XTAL

Crystal(0402 or 0603)

Johnstech

CX-4025 16 MHz ACAL Taitjen
SX-4025 16 MHz Siward

Designed for fCLKM = 1 MHzXWBBPL-F-1
A207-011

XTAL 32kHz Crystal

Rs=100 kOhm

32.2 Extended Feature Set Application Schematic
The ATmega128RFA1 supports additional features like:• Security Module (AES)• High Data Rate Mode up to 2MBits/s• Antenna Diversity using alternate pin function DIG1/2 at Port G and F• RX/TX Indicator using alternate pin function DIG3/4 at Port G and F
An extended feature set application schematic illustrating the use of
ATmega128RFA1 Extended Feature Set, is shown in Figure 32-2 on page 495.

494

the

ATmega128RFA1
8266A-MCU Wireless-12/09

ATmega128RFA1
Figure 32-2. Extended Feature Application schematic
CX1

XTAL

CX2

CB2

59

58 57

56 55

54

53 52

EVDD

AVSS

XTAL2

DVSS

DEVDD

PE7

1

XTAL1

61 60
AVSS

63 62
AREF

CB1

PF0

64

CR1

AVDD

VDD

2

51

50

48
47

3

ANT0

PE0 46

4

DVSS 455

DEVDD 44
PB7 436 PF7
7 AVSS

N1
SW1

42

8 RFP

Balun

PA

RFSwitch

SW2

RFSwitch

N2
LNA

49

41

ATmega128RFA1

9 RFN

40

10 AVSS

39

11 TST

38

12 RSTN

37

B1

ANT1

13 RSTON

PB0 36
DVSS 35

14 PG0

CX3

XTAL
32kHz

DEVDD

DVSS

PD0

19

20 21

22

23

24

25 26

CB3

PD7

DVDD

18

DVDD

17

DVSS

16

DEVDD 34

PG5

15

CB4

VDD

27

28 29

30

31

33 CLKI

32

CX4

Although this example shows all additional hardware features combined, it is possible touse all features separately or in various combinations.

495
8266A-MCU Wireless-12/09

33 Register Summary
Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

(0x1FF)TRXFBENDTRXFBEND7TRXFBEND6TRXFBEND5TRXFBEND4TRXFBEND3TRXFBEND2TRXFBEND1

TRXFBEND0

132
132

...
(0x180)

TRXFBSTTRXFBST7

TRXFBST6

TRXFBST5

TRXFBST4

TRXFBST3

TRXFBST2

TRXFBST1TRXFBST0(0x17F)

Reserved

Res7

Res6

Res5

Res4

Res3

Res2

Res1

Res0

(0x17E)

Reserved

Res7

Res6

Res5

Res4

Res3

Res2

Res1

Res0

(0x17D)

Reserved

Res7

Res6

Res5

Res4

Res3

Res2

Res1

Res0

(0x17C)

Reserved

Res7

Res6

Res5

Res4

Res3

Res2

Res1

Res0

(0x17B)

TST_RX_LENGTH

RX_LENGTH7

RX_LENGTH6

RX_LENGTH5

RX_LENGTH4

RX_LENGTH3

RX_LENGTH2

RX_LENGTH1

RX_LENGTH0(0x17A)

Reserved

Res7

Res6

Res5

Res4

Res3

Res2

Res1

Res0

(0x179)Reserved

Res7

Res6

Res5

Res4

Res3

Res2

Res1

Res0

(0x178)Reserved

Res7

Res6

Res5

Res4

Res3

Res2

Res1

Res0

(0x177)

Reserved

Res7

Res6

Res5

Res4

Res3

Res2

Res1

Res0

(0x176)

TST_CTRL_DIGI

Res7

Res6

Res5

Res4

TST_CTRL_DIG3

TST_CTRL_DIG2

TST_CTRL_DIG1

TST_CTRL_DIG0(0x175)Reserved

Res7

Res6

Res5

Res4

Res3

Res2

Res1

Res0

(0x173)

Reserved

Res7

Res6

Res5

Res4

Res3

Res2

Res1

Res0

(0x172)

Reserved

Res7

Res6

Res5

Res4

Res3

Res2

Res1

Res0

(0x171)

Reserved

Res7

Res6

Res5

Res4

Res3

Res2

Res1

Res0

(0x170)Reserved

Res7

Res6

Res5

Res4

Res3

Res2

Res1

Res0

(0x16F)

CSMA_BEMAX_BE3

MAX_BE2

MAX_BE1

MAX_BE0MIN_BE3

MIN_BE2MIN_BE1MIN_BE0(0x16E)

CSMA_SEED_1

AACK_FVN_MODE1 AACK_FVN_MODE0 AACK_SET_PD

AACK_DIS_ACK AACK_I_AM_COORD CSMA_SEED_12 CSMA_SEED_11 CSMA_SEED_10

129(0x16D)

CSMA_SEED_0

CSMA_SEED_07 CSMA_SEED_06 CSMA_SEED_05 CSMA_SEED_04 CSMA_SEED_03 CSMA_SEED_02 CSMA_SEED_01 CSMA_SEED_00

128(0x16C)XAH_CTRL_0

MAX_FRAME_RETRIES3 MAX_FRAME_RETRIES2 MAX_FRAME_RETRIES1 MAX_FRAME_RETRIES0 MAX_CSMA_RETRIES2 MAX_CSMA_RETRIES1 MAX_CSMA_RETRIES0 SLOTTED_OPERATION

127(0x16B)

IEEE_ADDR_7

IEEE_ADDR_77

IEEE_ADDR_76

IEEE_ADDR_75

IEEE_ADDR_74

IEEE_ADDR_73

IEEE_ADDR_72

IEEE_ADDR_71

IEEE_ADDR_70

126(0x16A)

IEEE_ADDR_6

IEEE_ADDR_67

IEEE_ADDR_66

IEEE_ADDR_65

IEEE_ADDR_64

IEEE_ADDR_63

IEEE_ADDR_62

IEEE_ADDR_61

IEEE_ADDR_60

126(0x169)IEEE_ADDR_5

IEEE_ADDR_57

IEEE_ADDR_56

IEEE_ADDR_55

IEEE_ADDR_54

IEEE_ADDR_53

IEEE_ADDR_52

IEEE_ADDR_51

IEEE_ADDR_50

126(0x168)IEEE_ADDR_4

IEEE_ADDR_47

IEEE_ADDR_46

IEEE_ADDR_45

IEEE_ADDR_44

IEEE_ADDR_43

IEEE_ADDR_42

IEEE_ADDR_41

IEEE_ADDR_40

126(0x167)

IEEE_ADDR_3

IEEE_ADDR_37

IEEE_ADDR_36

IEEE_ADDR_35

IEEE_ADDR_34

IEEE_ADDR_33

IEEE_ADDR_32

IEEE_ADDR_31

IEEE_ADDR_30

125(0x166)

IEEE_ADDR_2

IEEE_ADDR_27

IEEE_ADDR_26

IEEE_ADDR_25

IEEE_ADDR_24

IEEE_ADDR_23

IEEE_ADDR_22

IEEE_ADDR_21

IEEE_ADDR_20

125(0x165)

IEEE_ADDR_1

IEEE_ADDR_17

IEEE_ADDR_16

IEEE_ADDR_15

IEEE_ADDR_14

IEEE_ADDR_13

IEEE_ADDR_12

IEEE_ADDR_11

IEEE_ADDR_10

125(0x164)

IEEE_ADDR_0

IEEE_ADDR_07

IEEE_ADDR_06

IEEE_ADDR_05

IEEE_ADDR_04

IEEE_ADDR_03

IEEE_ADDR_02

IEEE_ADDR_01

IEEE_ADDR_00

124(0x163)

PAN_ID_1

PAN_ID_17

PAN_ID_16

PAN_ID_15

PAN_ID_14

PAN_ID_13

PAN_ID_12

PAN_ID_11

PAN_ID_10

124(0x162)

PAN_ID_0

PAN_ID_07

PAN_ID_06

PAN_ID_05

PAN_ID_04

PAN_ID_03

PAN_ID_02

PAN_ID_01

PAN_ID_00

124(0x161)SHORT_ADDR_1

SHORT_ADDR_17 SHORT_ADDR_16 SHORT_ADDR_15 SHORT_ADDR_14 SHORT_ADDR_13 SHORT_ADDR_12 SHORT_ADDR_11 SHORT_ADDR_10

124(0x160)SHORT_ADDR_0

SHORT_ADDR_07 SHORT_ADDR_06 SHORT_ADDR_05 SHORT_ADDR_04 SHORT_ADDR_03 SHORT_ADDR_02 SHORT_ADDR_01 SHORT_ADDR_00

123(0x15F)

MAN_ID_1

MAN_ID_17

MAN_ID_16

MAN_ID_15

MAN_ID_14

MAN_ID_13

MAN_ID_12

MAN_ID_11

MAN_ID_10

123(0x15E)

MAN_ID_0

MAN_ID_07

MAN_ID_06

MAN_ID_05

MAN_ID_04

MAN_ID_03

MAN_ID_02

MAN_ID_01

MAN_ID_00

123(0x15D)

VERSION_NUM(0x15C)

PART_NUM

PART_NUM7

PART_NUM6

PART_NUM5

PART_NUM4

PART_NUM3

PART_NUM2

PART_NUM1

PART_NUM0122(0x15B)PLL_DCU

PLL_DCU_START

Res6

Res5

Res4

Res3

Res2

Res1

Res0

121

(0x15A)

PLL_CF

PLL_CF_START

Res6

Res5

Res4

Res3

Res2

Res1

Res0

121

(0x159)Reserved

Res7

Res6

Res5

Res4

Res3

Res2

Res1

Res0

(0x158)FTN_CTRLFTN_START

Res6

Res5

Res4

Res3

Res2

Res1

Res0

120

(0x157)

XAH_CTRL_1

Res1

Res0

Res

119

...

Reserved
RX_PDT_DIS

Res2

Res1

Res0

131

131

...

VERSION_NUM7 VERSION_NUM6 VERSION_NUM5 VERSION_NUM4 VERSION_NUM3 VERSION_NUM2 VERSION_NUM1 VERSION_NUM0

AACK_FLTR_RES_FT AACK_UPLD_RES_FTRes

AACK_ACK_TIME AACK_PROM_MODE

122(0x155)

RX_SYN...

Reserved(0x152)

XOSC_CTRLXTAL_MODE3

XTAL_MODE2

XTAL_MODE1

XTAL_MODE0XTAL_TRIM3XTAL_TRIM2XTAL_TRIM1XTAL_TRIM0117(0x151)BATMON

BAT_LOW

BAT_LOW_EN

BATMON_OK

BATMON_HR

BATMON_VTH3

BATMON_VTH2

BATMON_VTH1

BATMON_VTH0116(0x150)

VREG_CTRLAVREG_EXT

AVDD_OK

Res5

Res4

Res3

DVDD_OK

Res1

Res0

115

(0x14F)

IRQ_STATUS

AWAKE

TX_ENDAMI

CCA_ED_DONE

RX_END

RX_START

PLL_UNLOCK

PLL_LOCK

114(0x14E)

IRQ_MASK

AWAKE_EN

TX_END_EN

AMI_EN

CCA_ED_DONE_EN

RX_END_EN

RX_START_EN

PLL_UNLOCK_EN

PLL_LOCK_EN

114(0x14D)

ANT_DIV

ANT_SEL

Res2

Res1

Res0

ANT_DIV_EN

ANT_EXT_SW_EN

ANT_CTRL1

ANT_CTRL0112(0x14C)TRX_CTRL_2

RX_SAFE_MODE

Res4

Res3

Res2

Res1

Res0

(0x14B)

SFD_VALUESFD_VALUE7

SFD_VALUE6

SFD_VALUE5

SFD_VALUE4

SFD_VALUE3

SFD_VALUE2

SFD_VALUE1

SFD_VALUE0111(0x14A)

RX_CTRL

Res7

Res6

Res5

Res4

PDT_THRES3

PDT_THRES2

PDT_THRES1

PDT_THRES0111(0x149)

CCA_THRES

CCA_CS_THRES3 CCA_CS_THRES2 CCA_CS_THRES1 CCA_CS_THRES0 CCA_ED_THRES3 CCA_ED_THRES2 CCA_ED_THRES1 CCA_ED_THRES0110(0x148)PHY_CC_CCA

CCA_REQUESTCCA_MODE1

CCA_MODE0CHANNEL4CHANNEL3CHANNEL2CHANNEL1

CHANNEL0109(0x147)

PHY_ED_LEVEL

ED_LEVEL7

ED_LEVEL6

ED_LEVEL5

ED_LEVEL4

ED_LEVEL3

ED_LEVEL2

ED_LEVEL1

ED_LEVEL0108(0x146)

PHY_RSSI

RX_CRC_VALIDRND_VALUE1RND_VALUE0

RSSI4

RSSI3

RSSI2

RSSI1

RSSI0

107

(0x145)

PHY_TX_PWR

PA_BUF_LT1

PA_BUF_LT0

PA_LT1

PA_LT0

TX_PWR3

TX_PWR2

TX_PWR1

TX_PWR0

106

496

RX_PDT_LEVEL3 RX_PDT_LEVEL2 RX_PDT_LEVEL1 RX_PDT_LEVEL0130

OQPSK_DATA_RATE1 OQPSK_DATA_RATE0

118

112

ATmega128RFA1
8266A-MCU Wireless-12/09

ATmega128RFA1
Address

Name

Bit 7

(0x144)

TRX_CTRL_1

PA_EXT_EN(0x143)

TRX_CTRL_0

Res7(0x142)

TRX_STATE(0x141)

TRX_STATUS...

Reserved

Bit 6

Bit 5

IRQ_2_EXT_EN TX_AUTO_CRC_ON
Res6

Res5

TRAC_STATUS2 TRAC_STATUS1 TRAC_STATUS0
CCA_DONECCA_STATUS

TST_STATUS

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

Res4

Res3

Res2

Res1

Res0

105

Res4

Res3

Res2

Res1

Res0

105

TRX_CMD4

TRX_CMD3

TRX_CMD2

TRX_CMD1

TRX_CMD0104

TRX_STATUS4

TRX_STATUS3

TRX_STATUS2TRX_STATUS1TRX_STATUS0102(0x13F)

AES_KEY

AES_KEY7

AES_KEY6

AES_KEY5

AES_KEY4

AES_KEY3

AES_KEY2

AES_KEY1

AES_KEY0102(0x13E)AES_STATEAES_STATE7

AES_STATE6AES_STATE5AES_STATE4AES_STATE3AES_STATE2AES_STATE1

AES_STATE0102(0x13D)AES_STATUS

AES_ER

Res5

Res4

Res3

Res2

Res1

Res0

AES_DONE101(0x13C)AES_CTRLAES_REQUESTRes

AES_MODERes

AES_DIR

AES_IM

Res1

Res0

100

(0x13B)

Reserved

Res7

Res6

Res5

Res4

Res3

Res2

Res1

Res0

...

Reserved
Res3

Res2

Res1

Res0

Res3

Res2

SLPTR

TRXRST169(0x139)

TRXPR

...

Reserved(0x137)

DPDS1

Res5

Res4

Res3

Res2

Res1

Res0

PGDRV1PGDRV0175(0x136)DPDS0PFDRV1PFDRV0PEDRV1PEDRV0PDDRV1PDDRV0PBDRV1PBDRV0174(0x135)DRTRAM0

Res1

Res0

DRTSWOK

ENDRT

Res3

Res2

Res1

Res0

170

(0x134)DRTRAM1

Res1

Res0

DRTSWOK

ENDRT

Res3

Res2

Res1

Res0

170

(0x133)DRTRAM2

Res7

Res

DRTSWOK

ENDRT

Res3

Res2

Res1

Res0

171

(0x132)DRTRAM3

Res1

Res0

DRTSWOK

ENDRT

Res3

Res2

Res1

Res0

171

(0x131)

LLDRH

Res2

Res1

Res0

LLDRH4LLDRH3

LLDRH2LLDRH1LLDRH0173(0x130)

LLDRL

Res3

Res2

Res1

Res0

LLDRL3LLDRL2LLDRL1LLDRL0173(0x12F)

LLCR

Res1

Res0

LLDONE

LLCOMP

LLCAL

LLTCO

LLSHORT

LLENCAL

172...

Reserved(0x12D)

OCR5CHOCR5CH7OCR5CH6OCR5CH5OCR5CH4OCR5CH3OCR5CH2

OCR5CH1

OCR5CH0300(0x12C)OCR5CLOCR5CL7

OCR5CL6

OCR5CL5OCR5CL4

OCR5CL3

OCR5CL2

OCR5CL1

OCR5CL0301(0x12B)OCR5BHOCR5BH7OCR5BH6OCR5BH5OCR5BH4OCR5BH3

OCR5BH2

OCR5BH1

OCR5BH0299(0x12A)

OCR5BLOCR5BL7

OCR5BL6

OCR5BL5OCR5BL4OCR5BL3OCR5BL2OCR5BL1

OCR5BL0300(0x129)OCR5AHOCR5AH7OCR5AH6OCR5AH5OCR5AH4OCR5AH3OCR5AH2OCR5AH1

OCR5AH0299(0x128)OCR5ALOCR5AL7

OCR5AL6

OCR5AL5OCR5AL4OCR5AL3

OCR5AL2OCR5AL1

OCR5AL0299(0x127)ICR5H

ICR5H7ICR5H6ICR5H5ICR5H4ICR5H3ICR5H2ICR5H1ICR5H0301(0x126)

ICR5L

ICR5L7ICR5L6ICR5L5ICR5L4ICR5L3

ICR5L2ICR5L1ICR5L0301(0x125)

TCNT5HTCNT5H7

TCNT5H6

TCNT5H5

TCNT5H4

TCNT5H3

TCNT5H2

TCNT5H1

TCNT5H0298(0x124)

TCNT5LTCNT5L7

TCNT5L6

TCNT5L5

TCNT5L4

TCNT5L3

TCNT5L2

TCNT5L1

TCNT5L0298...

Reserved(0x122)

TCCR5C

FOC5A

FOC5B

FOC5C

Res4

Res3

Res2

Res1

Res0

297

(0x121)

TCCR5B

ICNC5

ICES5

Res

WGM53

WGM52

CS52

CS51

CS50

296

(0x120)

TCCR5A

COM5A1

COM5A0COM5B1COM5B0COM5C1COM5C0

WGM51

WGM50

294

...

Reserved(0xF8)SCOCR1HH

SCOCR1HH7

SCOCR1HH6SCOCR1HH5

SCOCR1HH4SCOCR1HH3SCOCR1HH2SCOCR1HH1

SCOCR1HH0

140(0xF7)SCOCR1HL

SCOCR1HL7

SCOCR1HL6

SCOCR1HL5

SCOCR1HL4

SCOCR1HL3

SCOCR1HL2

SCOCR1HL1

SCOCR1HL0

141(0xF6)SCOCR1LH

SCOCR1LH7

SCOCR1LH6

SCOCR1LH5

SCOCR1LH4

SCOCR1LH3SCOCR1LH2SCOCR1LH1

SCOCR1LH0141(0xF5)SCOCR1LL

SCOCR1LL7

SCOCR1LL6

SCOCR1LL5

SCOCR1LL4

SCOCR1LL3

SCOCR1LL2

SCOCR1LL1SCOCR1LL0

141(0xF4)SCOCR2HH

SCOCR2HH7

SCOCR2HH6SCOCR2HH5

SCOCR2HH4SCOCR2HH3SCOCR2HH2SCOCR2HH1SCOCR2HH0

141(0xF3)SCOCR2HLSCOCR2HL7

SCOCR2HL6

SCOCR2HL5

SCOCR2HL4

SCOCR2HL3SCOCR2HL2

SCOCR2HL1

SCOCR2HL0

142(0xF2)SCOCR2LH

SCOCR2LH7

SCOCR2LH6

SCOCR2LH5

SCOCR2LH4SCOCR2LH3SCOCR2LH2SCOCR2LH1SCOCR2LH0

142(0xF1)SCOCR2LL

SCOCR2LL7

SCOCR2LL6

SCOCR2LL5

SCOCR2LL4

SCOCR2LL3SCOCR2LL2SCOCR2LL1SCOCR2LL0

142(0xF0)SCOCR3HH

SCOCR3HH7

SCOCR3HH6SCOCR3HH5SCOCR3HH4SCOCR3HH3SCOCR3HH2

SCOCR3HH1

SCOCR3HH0

142(0xEF)SCOCR3HL

SCOCR3HL7

SCOCR3HL6SCOCR3HL5

SCOCR3HL4

SCOCR3HL3SCOCR3HL2

SCOCR3HL1

SCOCR3HL0

143(0xEE)SCOCR3LH

SCOCR3LH7

SCOCR3LH6

SCOCR3LH5

SCOCR3LH4SCOCR3LH3SCOCR3LH2

SCOCR3LH1

SCOCR3LH0

143(0xED)SCOCR3LL

SCOCR3LL7

SCOCR3LL6

SCOCR3LL5

SCOCR3LL4SCOCR3LL3SCOCR3LL2

SCOCR3LL1

SCOCR3LL0

143(0xEC)SCTSRHH

SCTSRHH7SCTSRHH6SCTSRHH5SCTSRHH4SCTSRHH3

SCTSRHH2SCTSRHH1

SCTSRHH0138(0xEB)SCTSRHLSCTSRHL7SCTSRHL6SCTSRHL5

SCTSRHL4

SCTSRHL3

SCTSRHL2

SCTSRHL1

SCTSRHL0

139(0xEA)SCTSRLH

SCTSRLH7

SCTSRLH6

SCTSRLH5

SCTSRLH4

SCTSRLH3

SCTSRLH2

SCTSRLH1

SCTSRLH0139(0xE9)SCTSRLL

SCTSRLL7

SCTSRLL6

SCTSRLL5

SCTSRLL4

SCTSRLL3

SCTSRLL2

SCTSRLL1

SCTSRLL0139(0xE8)SCBTSRHH

SCBTSRHH7

SCBTSRHH6

SCBTSRHH5

SCBTSRHH4

SCBTSRHH3

SCBTSRHH2

SCBTSRHH1

SCBTSRHH0139(0xE7)SCBTSRHLSCBTSRHL7

SCBTSRHL6SCBTSRHL5

SCBTSRHL4

SCBTSRHL3

SCBTSRHL2

SCBTSRHL1

SCBTSRHL0

140(0xE6)SCBTSRLH

SCBTSRLH7SCBTSRLH6SCBTSRLH5SCBTSRLH4SCBTSRLH3

SCBTSRLH2SCBTSRLH1

SCBTSRLH0

140(0xE5)SCBTSRLLSCBTSRLL7SCBTSRLL6SCBTSRLL5SCBTSRLL4SCBTSRLL3SCBTSRLL2SCBTSRLL1SCBTSRLL0140(0xE4)SCCNTHHSCCNTHH7SCCNTHH6SCCNTHH5SCCNTHH4SCCNTHH3SCCNTHH2SCCNTHH1

SCCNTHH0137(0xE3)SCCNTHLSCCNTHL7SCCNTHL6SCCNTHL5SCCNTHL4SCCNTHL3SCCNTHL2SCCNTHL1

SCCNTHL0138(0xE2)SCCNTLHSCCNTLH7SCCNTLH6SCCNTLH5SCCNTLH4SCCNTLH3SCCNTLH2SCCNTLH1SCCNTLH0138(0xE1)SCCNTLLSCCNTLL7SCCNTLL6SCCNTLL5SCCNTLL4SCCNTLL3SCCNTLL2SCCNTLL1SCCNTLL0

138(0xE0)SCIRQS

Res2

Res1

Res0

IRQSBOIRQSOF

IRQSCP3

IRQSCP2

IRQSCP1

145(0xDF)SCIRQM

Res2

Res1

Res0

IRQMBOIRQMOF

IRQMCP3

IRQMCP2

IRQMCP1

146

497
8266A-MCU Wireless-12/09

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

(0xDE)

SCSR

Res6

Res5

Res4

Res3

Res2

Res1

Res0

SCBSY

145

(0xDD)

SCCR1

Res6

Res5

Res4

Res4

Res3

Res2

Res1

SCENBO

144(0xDC)

SCCR0

SCRES

SCMBTSSCENSCCKSELSCTSE

SCCMP3

SCCMP2SCCMP1

143...

Reserved(0xD1)

Reserved

Res7

Res6

Res5

Res4

Res3

Res2

Res1

Res0

(0xD0)

Reserved

Res7

Res6

Res5

Res4

Res3

Res2

Res1

Res0

...

Reserved(0xCE)

UDR1

UDR17

UDR16

UDR15

UDR14

UDR13

UDR12

UDR11

UDR10

360

(0xCD)UBRR1H

Res3

Res2

Res1

Res0

UBRR11UBRR10

UBRR9

UBRR8

364

(0xCC)UBRR1L

UBRR7

UBRR6

UBRR5

UBRR4

UBRR3

UBRR2

UBRR1

UBRR0

365

...

Reserved(0xCA)UCSR1CUMSEL11

UMSEL10

UPM11

UPM10

USBS1

UDORD1

UCPHA1UCPOL1376(0xC9)UCSR1B

RXCIE1TXCIE1

UDRIE1

RXEN1

TXEN1

UCSZ12

RXB81

TXB81

375

(0xC8)UCSR1A

RXC1

TXC1

UDRE1

FE1

DOR1

UPE1

U2X1

MPCM1

375

...

Reserved(0xC6)

UDR0

UDR07

UDR06

UDR05

UDR04

UDR03

UDR02

UDR01

UDR00

356

(0xC5)UBRR0H

Res3

Res2

Res1

Res0

UBRR11UBRR10

UBRR9

UBRR8

360

(0xC4)UBRR0L

UBRR7

UBRR6

UBRR5

UBRR4

UBRR3

UBRR2

UBRR1

UBRR0

360

...

Reserved(0xC2)UCSR0CUMSEL01

UMSEL00

UPM01

UPM00

USBS0

UDORD0UCPHA0UCPOL0374(0xC1)UCSR0B

RXCIE0TXCIE0

UDRIE0

RXEN0

TXEN0

UCSZ02

RXB80

TXB80

374

(0xC0)UCSR0A

RXC0

TXC0

UDRE0

FE0

DOR0

UPE0

U2X0

MPCM0

373

...

Reserved(0xBD)

TWAMR

TWAM6

TWAM5

TWAM4

TWAM3

TWAM2

TWAM1

TWAM0

Res

406

(0xBC)

TWCR

TWINT

TWEA

TWSTA

TWSTO

TWWC

TWEN

Res

TWIE

402

(0xBB)

TWDR

TWD7

TWD6

TWD5

TWD4

TWD3

TWD2

TWD1

TWD0

405

(0xBA)

TWAR

TWA6

TWA5

TWA4

TWA3

TWA2

TWA1

TWA0

TWGCE

405

(0xB9)

TWSR

TWS7

TWS6

TWS5

TWS4

TWS3

Res

TWPS1

TWPS0

403

(0xB8)

TWBR

TWBR7

TWBR6

TWBR5

TWBR4

TWBR3

TWBR2

TWBR1

TWBR0

401

...

Reserved
EXCLKAMR

EXCLK

AS2

TCN2UBOCR2AUBOCR2BUBTCR2AUBTCR2BUB

328(0xB6)ASSR...

Reserved(0xB4)OCR2B

OCR2B7

OCR2B6

OCR2B5OCR2B4OCR2B3OCR2B2OCR2B1OCR2B0327(0xB3)OCR2A

OCR2A7

OCR2A6

OCR2A5

OCR2A4OCR2A3

OCR2A2OCR2A1OCR2A0327(0xB2)

TCNT2

TCNT27

TCNT26

TCNT25

TCNT24

TCNT23

TCNT22

TCNT21

TCNT20327(0xB1)

TCCR2B

FOC2A

FOC2B

Res1

Res0

WGM22

CS22

CS21

CS20

326

(0xB0)

TCCR2ACOM2A1COM2A0COM2B1COM2B0

Res1

Res0

WGM21

WGM20

325

...

Reserved(0xAD)OCR4CHOCR4CH7OCR4CH6OCR4CH5OCR4CH4OCR4CH3OCR4CH2

OCR4CH1

OCR4CH0291(0xAC)OCR4CLOCR4CL7

OCR4CL6

OCR4CL5

OCR4CL4OCR4CL3

OCR4CL2

OCR4CL1

OCR4CL0292(0xAB)OCR4BH

OCR4BH7OCR4BH6OCR4BH5OCR4BH4OCR4BH3OCR4BH2

OCR4BH1

OCR4BH0291(0xAA)OCR4BLOCR4BL7

OCR4BL6

OCR4BL5OCR4BL4OCR4BL3OCR4BL2OCR4BL1

OCR4BL0291(0xA9)OCR4AHOCR4AH7OCR4AH6OCR4AH5OCR4AH4OCR4AH3OCR4AH2OCR4AH1OCR4AH0290(0xA8)OCR4ALOCR4AL7

OCR4AL6

OCR4AL5OCR4AL4OCR4AL3OCR4AL2

OCR4AL1

OCR4AL0290(0xA7)ICR4H

ICR4H7ICR4H6ICR4H5ICR4H4ICR4H3ICR4H2ICR4H1ICR4H0292(0xA6)

ICR4L

ICR4L7

ICR4L6

ICR4L5ICR4L4ICR4L3

ICR4L2

ICR4L1ICR4L0292(0xA5)

TCNT4H

TCNT4H7

TCNT4H6

TCNT4H5

TCNT4H4

TCNT4H3

TCNT4H2

TCNT4H1

TCNT4H0289(0xA4)

TCNT4LTCNT4L7

TCNT4L6

TCNT4L5

TCNT4L4

TCNT4L3

TCNT4L2

TCNT4L1

TCNT4L0289...

Reserved(0xA2)

TCCR4C

FOC4A

FOC4B

FOC4C

Res4

Res3

Res2

Res1

Res0

288

(0xA1)

TCCR4B

ICNC4

ICES4

Res

WGM43

WGM42

CS42

CS41

CS40

287

(0xA0)

TCCR4A

COM4A1

COM4A0COM4B1COM4B0COM4C1COM4C0

WGM41

WGM40

285

...

Reserved(0x9D)OCR3CHOCR3CH7OCR3CH6OCR3CH5OCR3CH4OCR3CH3OCR3CH2OCR3CH1OCR3CH0282(0x9C)OCR3CLOCR3CL7

OCR3CL6

OCR3CL5

OCR3CL4

OCR3CL3

OCR3CL2

OCR3CL1

OCR3CL0283(0x9B)OCR3BHOCR3BH7

OCR3BH6OCR3BH5OCR3BH4OCR3BH3OCR3BH2OCR3BH1OCR3BH0282(0x9A)OCR3BLOCR3BL7

OCR3BL6

OCR3BL5

OCR3BL4OCR3BL3OCR3BL2OCR3BL1

OCR3BL0282(0x99)OCR3AHOCR3AH7OCR3AH6OCR3AH5OCR3AH4OCR3AH3OCR3AH2OCR3AH1OCR3AH0281(0x98)OCR3ALOCR3AL7

OCR3AL6

OCR3AL5OCR3AL4OCR3AL3OCR3AL2OCR3AL1

OCR3AL0281(0x97)ICR3H

ICR3H7ICR3H6ICR3H5ICR3H4ICR3H3ICR3H2ICR3H1ICR3H0283(0x96)ICR3L

ICR3L7

ICR3L6

ICR3L5ICR3L4

ICR3L3

ICR3L2ICR3L1ICR3L0283(0x95)

TCNT3H

TCNT3H7

TCNT3H6

TCNT3H5

TCNT3H4

TCNT3H3

TCNT3H2

TCNT3H1

TCNT3H0280(0x94)

TCNT3LTCNT3L7

TCNT3L6

TCNT3L5

TCNT3L4

TCNT3L3

TCNT3L2

TCNT3L1

TCNT3L0280...

Reserved

498

ATmega128RFA1
8266A-MCU Wireless-12/09

ATmega128RFA1
Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

(0x92)

TCCR3C

FOC3A

FOC3B

FOC3C

Res4

Res3

Res2

Res1

Res0

279

(0x91)

TCCR3B

ICNC3

ICES3

Res

WGM33

WGM32

CS32

CS31

CS30

278

(0x90)

TCCR3A

COM3A1COM3A0COM3B1COM3B0COM3C1COM3C0

WGM31

WGM30

276

...

Reserved(0x8D)OCR1CHOCR1CH7

OCR1CH6OCR1CH5OCR1CH4OCR1CH3

OCR1CH2

OCR1CH1

OCR1CH0273(0x8C)OCR1CLOCR1CL7

OCR1CL6

OCR1CL5

OCR1CL4

OCR1CL3

OCR1CL2

OCR1CL1

OCR1CL0273(0x8B)OCR1BHOCR1BH7

OCR1BH6OCR1BH5OCR1BH4OCR1BH3

OCR1BH2

OCR1BH1OCR1BH0272(0x8A)OCR1BLOCR1BL7

OCR1BL6

OCR1BL5

OCR1BL4

OCR1BL3

OCR1BL2

OCR1BL1OCR1BL0272(0x89)OCR1AHOCR1AH7

OCR1AH6OCR1AH5OCR1AH4OCR1AH3

OCR1AH2

OCR1AH1OCR1AH0271(0x88)OCR1ALOCR1AL7

OCR1AL6

OCR1AL5

OCR1AL4

OCR1AL3

OCR1AL2

OCR1AL1

OCR1AL0271(0x87)ICR1H

ICR1H7ICR1H6ICR1H5ICR1H4ICR1H3ICR1H2ICR1H1ICR1H0273(0x86)

ICR1L

ICR1L7

ICR1L6

ICR1L5

ICR1L4

ICR1L3

ICR1L2

ICR1L1ICR1L0274(0x85)

TCNT1H

TCNT1H7

TCNT1H6

TCNT1H5

TCNT1H4

TCNT1H3

TCNT1H2

TCNT1H1

TCNT1H0270(0x84)

TCNT1LTCNT1L7

TCNT1L6

TCNT1L5

TCNT1L4

TCNT1L3

TCNT1L2

TCNT1L1

TCNT1L0

271...

Reserved(0x82)

TCCR1C

FOC1A

FOC1B

FOC1C

Res4

Res3

Res2

Res1

Res0

270

(0x81)

TCCR1B

ICNC1

ICES1

Res

WGM13

WGM12

CS12

CS11

CS10

268

(0x80)

TCCR1A

COM1A1

COM1A0COM1B1COM1B0

COM1C1

COM1C0

WGM11

WGM10

266

(0x7F)

DIDR1

AIN1D

AIN0D

409

(0x7E)

DIDR0

ADC7D

ADC6D

ADC5D

ADC4D

ADC3D

ADC2D

ADC1D

ADC0D

433

(0x7D)DIDR2

ADC15D

ADC14DADC13DADC12D

ADC11D

ADC10D

ADC9D

ADC8D

433

(0x7C)

ADMUX

REFS1

REFS0

ADLAR

MUX4

MUX3

MUX2

MUX1

MUX0

427

(0x7B)ADCSRBAVDDOK

ACME

REFOK

ACCH

MUX5

ADTS2

ADTS1

ADTS0

428

(0x7A)ADCSRA

ADEN

ADSC

ADATE

ADIF

ADIE

ADPS2

ADPS1

ADPS0

430

(0x79)

ADCH

ADCH7

ADCH6

ADCH5

ADCH4

ADCH3

ADCH2

ADCH1

ADCH0

432

(0x78)

ADCL

ADCL7

ADCL6

ADCL5

ADCL4

ADCL3

ADCL2

ADCL1

ADCL0

432

(0x77)ADCSRCADTHT1ADTHT0Res0ADSUT4

ADSUT3

ADSUT2

ADSUT1ADSUT0431...

Reserved463(0x75)

NEMCR

Res7

ENEAM

AEAM1

AEAM0

Res3

Res2

Res1

Res0

(0x74)

Reserved

Res7

Res6

Res5

Res4

Res3

Res2

Res1

Res0

(0x73)TIMSK5

Res1

Res0

ICIE5

Res

OCIE5COCIE5BOCIE5ATOIE5302(0x72)TIMSK4

Res1

Res0

ICIE4

Res

OCIE4COCIE4B

OCIE4A

TOIE4

293(0x71)TIMSK3

Res1

Res0

ICIE3

Res

OCIE3COCIE3B

OCIE3ATOIE3

284(0x70)TIMSK2

Res4

Res3

Res2

Res1

Res0

OCIE2BOCIE2A

TOIE2

323(0x6F)TIMSK1

Res1

Res0

ICIE1

Res

OCIE1COCIE1BOCIE1A

TOIE1

274(0x6E)TIMSK0

Res4

Res3

Res2

Res1

Res0

OCIE0B

OCIE0A

TOIE0242(0x6D)PCMSK2

PCINT23PCINT22

PCINT21

PCINT20

PCINT19

PCINT18

PCINT17

PCINT16224(0x6C)PCMSK1

PCINT15

PCINT14PCINT13PCINT12PCINT11

PCINT10

PCINT9PCINT8224(0x6B)PCMSK0PCINT7PCINT6

PCINT5

PCINT4

PCINT3

PCINT2

PCINT1

PCINT0225(0x6A)

EICRB

ISC71

ISC70

ISC61

ISC60

ISC51

ISC50

ISC41

ISC40

220

(0x69)

EICRA

ISC31

ISC30

ISC21

ISC20

ISC11

ISC10

ISC01

ISC00

219

(0x68)

PCICR

Res4

Res3

Res2

Res1

Res0

PCIE2

PCIE1

PCIE0

223

(0x67)BGCR

Res

BGCAL_FINE3BGCAL_FINE2BGCAL_FINE1BGCAL_FINE0BGCAL2BGCAL1BGCAL0433(0x66)OSCCAL

CAL7

CAL6

CAL5

CAL4

CAL3

CAL2

CAL1

CAL0

153

(0x65)PRR1

Res

PRTRX24

PRTIM5PRTIM4PRTIM3

PRUSART1

168(0x64)

PRR0

PRTWI

PRTIM2

PRTIM0PRPGA

PRTIM1PRSPI

PRUSART0

PRADC

167

(0x63)

PRR2

Res3

Res2

Res1

Res0

PRRAM3PRRAM2PRRAM1PRRAM0168...

Reserved(0x61)

CLKPR

CLKPCE

Res2

Res1

Res0

CLKPS3

CLKPS2

CLKPS1

CLKPS0154(0x60)WDTCSR

WDIF

WDIE

WDP3

WDCE

WDE

WDP2

WDP1

WDP0

183

0x3F (0x5F)

SREG

I

T

H

S

V

N

Z

C

11

0x3E (0x5E)

SPH

SP15

SP14

SP13

SP12

SP11

SP10

SP9

SP8

13

0x3D (0x5D)

SPL

SP7

SP6

SP5

SP4

SP3

SP2

SP1

SP0

14

...

Reserved
Res5

Res4

Res3

Res2

Res1

Res0

RAMPZ1

RAMPZ0

14

SPMIE

RWWSB

SIGRD

RWWSREBLBSET

PGWRT

PGERS

SPMEN

462

0x3B (0x5B)

RAMPZ

...

Reserved

0x37 (0x57)

SPMCSR...

Reserved

0x35 (0x55)

MCUCR

JTD

Res1

Res0

PUD

Res1

Res0

IVSEL

IVCE

204

0x34 (0x54)

MCUSR

Res2

Res1

Res0

JTRF

WDRF

BORF

EXTRF

PORF

183

0x33 (0x53)

SMCR

Res3

Res2

Res1

Res0

SM2

SM1

SM0

SE

166

...

Reserved

0x31 (0x51)

OCDR

OCDR7

OCDR6

OCDR5

OCDR4

OCDR3

OCDR2

OCDR1

OCDR0

440

0x30 (0x50)

ACSR

ACD

ACBG

ACO

ACI

ACIE

ACIC

ACIS1

ACIS0

408

499
8266A-MCU Wireless-12/09

Address

Name

...

Reserved

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

0x2E (0x4E)

SPDR

SPDR7

SPDR6

SPDR5

SPDR4

SPDR3

SPDR2

SPDR1

SPDR0

338

0x2D (0x4D)

SPSR

SPIF

WCOL

Res4

Res3

Res2

Res1

Res0

SPI2X

337

0x2C (0x4C)

SPCR

SPIE

SPE

DORD

MSTR

CPOL

CPHA

SPR1

SPR0

336

0x2B (0x4B)

GPIOR2GPIOR27

GPIOR26

GPIOR25

GPIOR24

GPIOR23GPIOR22

GPIOR21

GPIOR20

26

0x2A (0x4A)

GPIOR1GPIOR17GPIOR16

GPIOR15GPIOR14GPIOR13GPIOR12GPIOR11GPIOR1026...

Reserved

0x28 (0x48)

OCR0B

OCR0B_7

OCR0B_6

OCR0B_5

OCR0B_4

OCR0B_3

OCR0B_2

OCR0B_1

OCR0B_0242

0x27 (0x47)

OCR0A

OCR0A_7

OCR0A_6

OCR0A_5

OCR0A_4

OCR0A_3

OCR0A_2

OCR0A_1

OCR0A_02410x26 (0x46)

TCNT0

TCNT0_7

TCNT0_6

TCNT0_5

TCNT0_4

TCNT0_3

TCNT0_2

TCNT0_1

TCNT0_02410x25 (0x45)

TCCR0B

FOC0A

FOC0B

Res1

Res0

WGM02

CS02

CS01

CS00

240

0x24 (0x44)

TCCR0A

COM0A1

COM0A0COM0B1COM0B0

Res1

Res0

WGM01

WGM00

238

0x23 (0x43)

GTCCR

TSM

Res4

Res3

Res2

Res1

Res0

PSRASYPSRSYNC

329

0x22 (0x42)

EEARH

Res3

Res2

Res1

Res0

EEAR11

EEAR10

EEAR9

EEAR8

23

0x21 (0x41)

EEARL

EEAR7

EEAR6

EEAR5

EEAR4

EEAR3

EEAR2

EEAR1

EEAR0

23

0x20 (0x40)

EEDR

EEDR7

EEDR6

EEDR5

EEDR4

EEDR3

EEDR2

EEDR1

EEDR0

23

0x1F (0x3F)

EECR

Res1

Res0

EEPM1

EEPM0

EERIE

EEMPE

EEPE

EERE

24

0x1E (0x3E)

GPIOR0GPIOR07

GPIOR06

GPIOR05

GPIOR04

GPIOR03

GPIOR02

GPIOR01

GPIOR00

26

0x1D (0x3D)

EIMSK

INT7

INT6

INT5

INT4

INT3

INT2

INT1

INT0

222

0x1C (0x3C)

EIFR

INTF7

INTF6

INTF5

INTF4

INTF3

INTF2

INTF1

INTF0

222

0x1B (0x3B)

PCIFR

Res4

Res3

Res2

Res1

Res0

PCIF2

PCIF1

PCIF0

223

0x1A (0x3A)

TIFR5

Res1

Res0

ICF5

Res

OCF5C

OCF5B

OCF5A

TOV5

302

0x19 (0x39)

TIFR4

Res1

Res0

ICF4

Res

OCF4C

OCF4B

OCF4A

TOV4

293

0x18 (0x38)

TIFR3

Res1

Res0

ICF3

Res

OCF3C

OCF3B

OCF3A

TOV3

284

0x17 (0x37)

TIFR2

Res4

Res3

Res2

Res1

Res0

OCF2B

OCF2A

TOV2

324

0x16 (0x36)

TIFR1

Res1

Res0

ICF1

Res

OCF1C

OCF1B

OCF1A

TOV1

275

0x15 (0x35)

TIFR0

Res4

Res3

Res2

Res1

Res0

OCF0B

OCF0A

TOV0

243

0x14 (0x34)

PORTG

Res1

Res0

PORTG5PORTG4

PORTG3

PORTG2PORTG1PORTG0209

0x13 (0x33)

DDRG

Res1

Res0

DDG5

DDG4

DDG3

DDG2

DDG1

DDG0

209

0x12 (0x32)

PING

Res1

Res0

PING5

PING4

PING3

PING2

PING1

PING0

210

0x11 (0x31)

PORTF

PORTF7PORTF6PORTF5PORTF4PORTF3PORTF2PORTF1PORTF0208

0x10 (0x30)

DDRF

DDF7

DDF6

DDF5

DDF4

DDF3

DDF2

DDF1

DDF0

208

0x0F (0x2F)

PINF

PINF7

PINF6

PINF5

PINF4

PINF3

PINF2

PINF1

PINF0

209

0x0E (0x2E)

PORTE

PORTE7PORTE6PORTE5PORTE4PORTE3PORTE2PORTE1PORTE0207

0x0D (0x2D)

DDRE

DDE7

DDE6

DDE5

DDE4

DDE3

DDE2

DDE1

DDE0

207

0x0C (0x2C)

PINE

PINE7

PINE6

PINE5

PINE4

PINE3

PINE2

PINE1

PINE0

208

0x0B (0x2B)

PORTD

PORTD7

PORTD6

PORTD5PORTD4PORTD3PORTD2PORTD1PORTD0206

0x0A (0x2A)

DDRD

DDD7

DDD6

DDD5

DDD4

DDD3

DDD2

DDD1

DDD0

207

0x09 (0x29)

PIND

PIND7

PIND6

PIND5

PIND4

PIND3

PIND2

PIND1

PIND0

207

0x08 (0x28)

PORTC

PORTC7PORTC6PORTC5PORTC4PORTC3

PORTC2PORTC1PORTC027

0x07 (0x27)

DDRC

DDC7

DDC6

DDC5

DDC4

DDC3

DDC2

DDC1

DDC0

28

0x06 (0x26)

PINC

PINC7

PINC6

PINC5

PINC4

PINC3

PINC2

PINC1

PINC0

28

0x05 (0x25)

PORTB

PORTB7PORTB6PORTB5PORTB4PORTB3PORTB2PORTB1PORTB0205

0x04 (0x24)

DDRB

DDB7

DDB6

DDB5

DDB4

DDB3

DDB2

DDB1

DDB0

206

0x03 (0x23)

PINB

PINB7

PINB6

PINB5

PINB4

PINB3

PINB2

PINB1

PINB0

206

0x02 (0x22)

PORTA

PORTA7PORTA6PORTA5PORTA4PORTA3

PORTA2PORTA1PORTA027

0x01 (0x21)

DDRA

DDA7

DDA6

DDA5

DDA4

DDA3

DDA2

DDA1

DDA0

27

0x00 (0x20)

PINA

PINA7

PINA6

PINA5

PINA4

PINA3

PINA2

PINA1

PINA0

27

Notes:

1. Reserved registers, bits and I/O memory addresses (marked as Res*) may not be modified.
2. I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, thevalue of single bits can be checked by using the SBIS and SBIC instructions.
3. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on all bits in the
I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers 0x00 to
0x1F only.
4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 – 0x3F must be used. When addressing I/O registers asdata space using LD and ST instructions, 0x20 must be added to these addresses. The device is a complex microcontroller with more
peripheral units than can be supported within the 64 location reserved in Op-code for the IN and OUT instructions. For the Extended I/Ospace from 0x60 – 0x1FF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.

500

ATmega128RFA1
8266A-MCU Wireless-12/09

ATmega128RFA1
34 Electrical Characteristics
34.1 Absolute Maximum Ratings
Note that stresses beyond those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions beyond those indicated in the operational
sections of this specification are not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
SymbolParameter

Condition

Min.

TSTOR

Storage temperature

TLEAD

Lead temperature

T = 10s,(soldering profile compliant with
IPC/JEDEC J-STD-020B)

VESD

ESD robustness

Compl. to [3],Compl. to [4]

Typ.

-50

Max.

Units

150

°C

260

°C

4
750

kV
V
VDD+0.3 V

PRF

Input RF level

VDIG

Voltage on all pins
(except pins 4, 5, 13, 14, 29)

-0.3

+14

VANA

Voltage on pins 4, 5, 13, 14, 29

-0.3

dBm

2.0

V

Max.

Units

+85

°C

34.1.1 Recommended Operating Range
SymbolParameter

TOP

Operating temperature range

VDD

Condition

Min.
-40
(2)

Supply voltage

Typ.

Voltage on pins 15,28(1)

External voltage supply

1.8

3.0

3.6

V

1.7

1.8

1.9

V

VDD1.8Supply voltage(on pins 13, 14, 29)

Notes:

1. Register VREG_CTRL needs to be programmed to disable internal voltage regulators and supply blocks by an external
1.8V supply, refer to section "Voltage Regulators (AVREG, DVREG)" on page 163.
2. Even if an implementation uses the external 1.8V voltage supply VDD1.8 it is required to connect VDD.

34.1.2 Digital Pin Characteristics
Test Conditions: TOP = 25°C (unless otherwise stated)
SymbolParameter

Condition(1)

VIH

High level input voltage

VIL

Low level input voltage

Min

Typ

Max

VDD –
0.4

(1)

V
0.4

(1)

For all output driver strengths defined in
DPDS0, DPDS1(1)

For all output driver strengths defined in
DPDS0, DPDS1

Units

VDD –
0.4

V

VOH

High level output voltage

VVOL

Low level output voltage

Note:

5. The capacitive load should not be larger than 50 pF for all I/Os when using the default driver strength settings, refer tosection "DPDS0 – Port Driver Strength Register 0" on page 174 and "DPDS1 – Port Driver Strength Register 1" onpage 175. Generally, large load capacitances increase the overall current consumption.

0.4

V

501
8266A-MCU Wireless-12/09

34.2 Clock Characteristics
34.2.1 Calibrated Internal RC Oscillator Accuracy
Table 34-2. Calibration Accuracy of Internal RC Oscillator
Frequency

VDEVDD

Temperature

Calibration Accuracy

Factory Calibration

16 MHz

3.0V

25°C± TBD %

User Calibration

TBD

1.8V – 3.6V

-TBD°C - TBD°C± TBD %

34.2.2 External Clock Drive
Figure 34-1 External Clock Drive Waveforms

V IH1
V IL1

Table 34-3. External Clock Drive
SymbolParameter

Min.

Max.

Units

1/tCLCL

Oscillator Frequency

16

MHz

tCLCL

Clock Period

62.5

ns

tCHCX

High Time

25

ns

tCLCX

Low Time

25

ns

tCLCH

Rise Time

0.1

µs

tCHCL

Fall Time

0.1µs∆tCLCL

Change in period from one clock cycle to the next

1

%

Max

Units

34.3 System and Reset Characteristics
Table 34-4. Reset, Brown-out and Internal Voltage Characteristics
SymbolParameter

Condition

Min

Typ

Power-on Reset Threshold Voltage(rising)

TBD

VPower-on Reset Threshold Voltage(1)(falling)

0.3

V

VPSR

Power-on slope rate

TBD

V/ms

VRST

RSTN Pin Threshold Voltage

tRST

Minimum pulse width on RSTN Pin

TBD

ns

VHYS

Brown-out Detector Hysteresis

50

mV

VPOT

0.2VDEVDDtBODMin Pulse Width on Brown-out Reset

VBG

Bandgap reference voltage

Note:

1. The Power-on Reset will not work unless the supply voltage has been below VPOT (falling).

502

VDEVDD = 3.0V, TA = 25°C

0.9VDEVDD V

100

ns

1.2

V

ATmega128RFA1
8266A-MCU Wireless-12/09

ATmega128RFA1
Table 34-23. BODLEVEL Fuse Coding
BODLEVEL2:0 Fuses

Min VBOD

Typ VBOD

111

Note:

Max VBODUnits

BOD Disabled

110

1.8

V

101

1.9

V

100

2.0

V

011

2.1

V

010

2.2

V

001

2.3

V

000

2.4

V

VBOT may be below nominal minimum operating voltage. The device is operated down to VDEVDD = VBOT during the
production test. This guarantees that a Brown-Out Reset will occur before VDEVDD drops to a voltage where correct
operation of the microcontroller is no longer guaranteed. The test is performed using BODLEVEL = 110 for 16 MHz
operation of the ATmega128RFA1.

34.4 Power Management Electrical Characteristics
34.4.1 Power Switches
Table 34-6. Timing Characteristics of the Power Switches
SymbolParameter

Condition

Min.

tPOR

Power-on reset time

Applies if the device is powered up

tBG

Bandgap startup time

Typ.

Max.

Units

TBD

µs

7

µs

tDRT_ONDRT switch switch-on time2

µs

tPWRSW_ON

Power switch switch-on time2

µs34.4.2 Voltage Regulators
Table 34-7. Timing Characteristics of the Voltage regulators
SymbolParameter

Condition

tAVREGPower up time AVREG

external capacity on pin AVDD TBD

TBD

µs

tDVREGPower up time DVREG

Startup after wakeup,
Startup after deep sleep,
external capacity on pin DVDD TBD
TRX24 and all SRAM modules enabled)

30

µs

TBD

µs

tBG

Min.

Power up time bandgap

Typ.

Max.

Units

34.5 2-wire Serial Interface Characteristics
The timing characteristics refer to Table 34-8.

Table 34-8 2-wire Serial Bus Requirements
SymbolParameter

VIL

Input Low-voltage

Condition

Min.

Max.

-0.5

0.3VDEVDD

Units
V

503
8266A-MCU Wireless-12/09

SymbolParameter

Condition

VIH

Input High-voltage

Vhys

Hysteresis of Schmitt Trigger Inputs

VOL

Output Low-voltage

tr

Min.

Max.

Units

0.7VDEVDDVDEVDD +0.5

VV

3mA sink current

0

0.4

V

Rise Time for both SDA and SCL

300

ns

tof

Output Fall Time from VIHmin to VILmax

250

ns

tSP

Spikes suppressed by the input filter

50

ns

Figure 34-2
tHIGH

tof
tLOW

tr
tLOW

SCL
tSU;STAtHD;STAtHD;DATtSU;DATSDAtSU;STO

tBUF

34.6 SPI Timing Characteristics
See Figure 34-3and Figure 34-4 for details.

Table 34-9. SPI Timing Parameters
Description

Mode

SCK period

MasterSee "SPCR – SPI Control Register" on
page 336.

SCK high/low

Master

50% duty cycle

Rise/fall time

Master

TBD

Typ

Setup

MasterTBD

Hold

Master

TBD

Out to SCK

Master

0.5 tSCKSCK to out

MasterTBD

SCK__ to out highSS low to out

Master

TBD

Slave

TBD

SCK period

Slave

4 tCK

SCK high/low

Slave

2 tCK

Rise/fall time

Slave

Setup

Slave

TBD

Hold

Slave

tCK

SCK to out
__
SCK
to
SS
high
__

Slave

SS
__ high to tri-state
SS low to SCK

Slave

(1)

Note:

504

Min

Slave
Slave

Max

Units

ns

TBD

TBD
TBD
TBD
TBD

1. In SPI Programming mode the minimum SCK high/low period is 2 tCLCL for fCK < 12
MHz and 3 tCLCL for fCK > 12 MHz.

ATmega128RFA1
8266A-MCU Wireless-12/09

ATmega128RFA1
Figure 34-3. SPI timing Requirements (Master Mode)
SS
6

1

SCK
(CPOL = 0)
2

2

SCK
(CPOL = 1)
4

MISO
(Data Input)

5

3

MSB

...

LSB

7

MOSI
(Data Output)

MSB

8

...

LSB

Figure 34-4. SPI timing Requirements (Slave Mode)
SS
10

9

16

SCK
(CPOL = 0)
11

11

SCK
(CPOL = 1)
13

MOSI
(Data Input)

14

12

MSB

...

LSB

15

MISO
(Data Output)

MSB

17

...

LSB

X

34.7 ADC Characteristics
Table 34-10. ADC Electrical Characteristics
SymbolParameter

Condition

Min

Typ

Max

Units

VINT1

Internal Voltage Reference

1.5

V

VINT2

Internal Voltage Reference

1.6

V

VINT3

Internal Voltage Reference

AVDD

V

RAREF,EXT

External Voltage ImpedanceΩIL,AREF

Load Current

A

Table 34-11. ADC Characteristics, Single Ended Channels
SymbolParameter
Resolution
Absolute accuracy (Including

Condition

Min

(1)

Typ

(1)

Max

(1)

Units

Single Ended Conversion CLKADC <= 4 MHz

10

Bits

Single Ended Conversion CLKADC > 8 MHz

8

Bits

Single Ended Conversion

TBD

LSB

505
8266A-MCU Wireless-12/09

SymbolParameter

Condition
VREF = 1.6V

VIN

(1)

Typ

(1)

Max

(1)

Units

CLKADC = 200kHz

Single Ended Conversion
VREF = 1.6V
CLKADC = 1MHz

TBD

LSB

Single Ended Conversion
VREF = 1.6V
CLKADC = 2MHz

TBD

LSB

Single Ended Conversion
VREF = 1.6V
CLKADC = 4MHz

TBD

LSB

Integral Non-Linearity (INL)

Single Ended Conversion
VREF = 1.6V
CLKADC = 4MHz

0.8

LSB

Differential Non-Linearity(DNL)

Single Ended Conversion
VREF = 1.6V
CLKADC = 4MHz

Gain Error

Single Ended Conversion
VREF = 1.6V
CLKADC = 4MHz

1

LSB

Offset Error

Single Ended Conversion
VREF = 1.6V
CLKADC = 4MHz

1.5

LSB

Conversion TimeFree Running Conversion

Clock Frequency

Single Ended Conversion

INL, DNL, quantization error,
gain and offset error)

VREF

Min

-0.5

LSB

3

240

µs

8000

kHz
V

Reference Voltage

1.5

AVDD

Input Voltage

0

AVDD

Input Bandwith

20

V
kHz

RREF

Reference Input Resistance

TBD

kΩ

RAIN

Analog Input Resistance

2

kΩ

Note:

1. Values are guidelines only
2. All values are valid for EVDD = 3.0V

Table 34-12. PGA and ADC Characteristics, Differential Channels
SymbolParameter
Resolution

Absolute accuracy (Including
INL, DNL, quantization error,
gain and offset error)

Integral Non-Linearity (INL)

Condition

506

(1)

Typ

(1)

Max

(1)

Units

Gain = 1x

10

Bits

Gain = 10x

10

Bits

Gain = 200x

10

Bits

TBD

LSB

TBD

LSB

TBD

LSB

Gain = 1x
VREF = 1.6V

CLKADC = 2MHz

Gain = 10x
VREF = 1.6V

CLKADC = 2MHz

Gain = 200x
VREF = 1.6V

CLKADC = 2MHz

Gain = 1x
VREF = 1.6V

CLKADC = 2MHz

Gain = 10x
VREF = 1.6V
Gain = 200x
VREF = 1.6V

Differential Non-Linearity
(DNL)

Min

Gain = 1x
VREF = 1.6V

3

LSB

5

LSB

10

LSB

CLKADC = 2MHz
CLKADC = 2MHz
-0.5

LSB

CLKADC = 2MHz

ATmega128RFA1
8266A-MCU Wireless-12/09

ATmega128RFA1
SymbolParameter

Offset Error

VREF

Typ

(1)

Max

(1)

Min

Gain = 10x
VREF = 1.6V

-0.75

LSB

TBD

LSB

Gain = 200x
VREF = 1.6V
Gain Error(1)

Condition

Units

CLKADC = 2MHz
CLKADC = 2MHz

Gain = 1x1Gain = 10x1.5

Gain = 200x10Gain = 1x
VREF = 1.6V

CLKADC = 2MHz

Gain = 10x
VREF = 1.6V

CLKADC = 2MHz

Gain = 200x
VREF = 1.6V

CLKADC = 2MHz

Conversion TimeFree Running Conversion

Clock Frequency

Single Ended Conversion

Reference Voltage

LSB

0.7

LSB

0.75

LSB

13

LSB

100

µs
2000

kHz

1.5

AVDD

V

VIN

Input Voltage

0

AVDD

V

VDIFF

Input Differential Voltage

-AVDD

AVDD

V

ADC Conversion Output

-512

511

LSB

Input Bandwith

20

kHz

RREF

Reference Input Resistance

TBD

kΩ

RAIN

Analog Input Resistance

2

kΩ

Note:

1. Values are guidelines only
2. All values are valid for EVDD = 3.0V

34.8 Transceiver Electrical Characteristics
34.8.1 Digital Interface Timing Characteristics
Test Conditions: TOP = 25°C, VDD = 3.0V, CL = 50 pF (unless otherwise stated)
Symbol Parametert12

AES core cycle timetIRQ

Interrupt event latency

Condition

Min.

Relative to the event to be indicated

Typ.

Max.

Units

24

µs

9

µs

34.8.2 General RF Specifications
Test Conditions (unless otherwise stated):
VDD = 3.0V, fRF = 2.45 GHz, TOP = 25°C, Measurement setup see Figure 32-1 on page493.
SymbolParameter

Condition

Min.

Typ.

Max.

Units

fRF

Frequency range

As specified in [1],[2]

2405

2480

MHz

fCH

Channel spacing

As specified in [1],[2]

5

MHz

fHDR

Header bit rate (SHR, PHR)

As specified in [1],[2]

250

kb/s

507
8266A-MCU Wireless-12/09

SymbolParameter

Condition

Min.

fPSDU

PSDU bit rate

As specified in [1],[2]OQPSK_DATA_RATE = 1
OQPSK_DATA_RATE = 2
OQPSK_DATA_RATE = 3

250
500
1000
2000

kb/s
kb/s
kb/s
kb/s

fCHIP

Chip rate

As specified in [1],[2]2000kchip/sfCLK

Crystal oscillator frequency

Reference oscillator

16

MHz

tXTAL

Reference oscillator settling time

Leaving SLEEP state to clock available atpin 17 (CLKM)

215

Symbol rate deviation
Reference frequency accuracy forcorrect functionality

PSDU bit rate

250 kb/s
500 kb/s
1000 kb/s
2000 kb/s

B20dB

20 dB bandwidthNote:

6. A reference frequency accuracy of ±40 ppm is required by [1], [2].

Typ.

(1)

-60
-40
-40
-30

Max.

Units

1000

µs

+60
+40
+40
+30

ppm
ppm
ppm
ppm

2.8

MHz

34.8.3 Transmitter Characteristics
Test Conditions (unless otherwise stated):
VDD = 3.0V, fRF = 2.45 GHz, TOP = 25°C, Measurement setup see Figure 32-1 on page493.
SymbolParameter

Condition

PTX

TX Output power

Maximum configurable TX output power
value
Register bit TX_PWR = 0

PRANGE

Output power range

16 steps, configurable inregister 0x05 (PHY_TX_PWR)

PACC

Output power tolerance
TX Return loss

PHARM

PSPUR

Min.

Typ.

Max.

Units

0

+3.5

+6

dBm

20

dB
±3

10

dB

EVM

8

%rms

Harmonicsnd
2 harmonicrd
3 harmonic

-38
-45

dBm
dBm

-36
-30
-47
-47

dBm
dBm
dBm
dBm

Spurious Emissions
30 – ≤ 1000 MHz>1 – 12.75 GHz
1.8 – 1.9 GHz
5.15 – 5.3 GHz

100Ω differential impedance,
PTX = +3.5 dBm

dB

Complies with
EN 300 328/440,
FCC-CFR-47 part 15,
ARIB STD-66, RSS-210

34.8.4 Receiver Characteristics
Test Conditions (unless otherwise stated):
VDD = 3.0V, fRF = 2.45 GHz, TOP = 25°C, PSDU bit rate = 250 kb/s, Measurement setup
see Figure 32-1 on page 493.

508

ATmega128RFA1
8266A-MCU Wireless-12/09

ATmega128RFA1
SymbolParameter

Condition

PSENS

Receiver sensitivity
250 kb/s
500 kb/s
1000 kb/s
2000 kb/s

AWGN channel, PER ≤ 1%,
PSDU length 20 octets
High Data Rate Modes:
PSDU length 20 octets

Antenna Diversity
RL

Return loss

NF

Noise figure

PRXMAX

Maximum RX input level

PACRN

Min.

Typ.

Max.

Units

-100
-96
-94
-86

dBm
dBm
dBm
dBm

250 kb/s, PSDU 20 octets

-99

dBm

100Ω differential impedance

10

dB

6

dB

PER ≤ 1%, PSDU length of 20 octets

10

dBm

Adjacent channel rejection:-5 MHzPER ≤ 1%, PSDU length of 20 octets,
PRF = -82 dBm

34

dB

PACRP

Adjacent channel rejection:+5 MHzPER ≤ 1%, PSDU length of 20 octets,
PRF = -82 dBm

38

dB

PAACRN

Alternate channel rejection:-10 MHzPER ≤ 1%, PSDU length of 20 octets,
PRF = -82 dBm

54

dB

PAACRP

Alternate channel rejection:+10 MHzPER ≤ 1%, PSDU length of 20 octets,
PRF = -82 dBm

54

dB

PSPUR

Spurious emissions:
LO leakage
30 – ≤ 1000 MHz>1 – 12.75 GHz-71

fRXTXOFFS TX/RX carrier frequency offset
rd

IIP3

3 – order intercept point

IIP2

2

nd

– order intercept point

RSSI tolerance

Sensitivity loss < 2 dB

-300

(1)

-57
-47

dBm
dBm
dBm

+300

kHz

At maximum gain
Offset freq. interf. 1 = 5 MHz
Offset freq. interf. 2 = 10 MHz

-14

dBm

At maximum gain
Offset freq. interf. 1 = 60 MHz
Offset freq. interf. 2 = 62 MHz

17

dBm

Tolerance within gain step±5

dB

RSSI dynamic range

81

dB

RSSI resolution

3

dB
dBm

RSSI sensitivity

Defined as RSSI_BASE_VAL-90

Minimum RSSI value

PRF ≤ RSSI_BASE_VAL

0

Maximum RSSI value

PRF > RSSI_BASE_VAL + 81 dB

28

Note:

1. Offset equals ±120 ppm

34.8.5 Current Consumption Specifications
Test Conditions (unless otherwise stated):
VDD = 3.0V, fRF = 2.45 GHz, TOP = 25°C, Measurement setup see Figure 32-1 on page
493.

509
8266A-MCU Wireless-12/09

SymbolParameter

Condition

IBUSY_TX

Supply current transmit state

PTX = 3 dBm
PTX = 1 dBm
PTX = -3 dBm
PTX = -17 dBm(current consumption is reduced at
VDD = 1.8V for each output power level)

14.5
10
9
8

mA
mA
mA
mA

IRX_ON

Supply current RX_ON state

RX_ON state

12.5

mA

IRX_ON_P

Supply current RX_ON state

RX_ON state, with register setting(1)
RX_PDT_LEVEL > 0

12.0

mA

IPLL_ON

Supply current PLL_ON state

PLL_ON state

5.7

mA

ITRX_OFF

Supply current TRX_OFF state

TRX_OFF state

0.4

mA

ISLEEP

Supply current SLEEP state

SLEEP state

0.02

µA

Note:

Min.

Typ.

Max.

Units

1. Refer to section "Figure 32-1" on page 493

34.8.6 Crystal Parameter Requirements
SymbolParameterf0

Crystal frequency

CL

Load capacitance

C0
R1

Condition

Min.

Typ.

Max.

16
8

Units
MHz

14

pF

Static capacitance7

pF

Series resistance100Ω

35 Typical Characteristics
35.1 Internal Oscillator Speed
t.b.d.

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ATmega128RFA1
36 Ordering Information
ATmega128RFA1
Speed (MHz)Power Supply

Ordering CodePackage

Packing

Operation Range

16

1.8 – 3.6V

ATmega128RFA1-ZU

PI

Tray

Industrial (-40ºC to 85ºC)

16

1.8 – 3.6V

ATmega128RFA1-ZUR

PI

Tape & Reel

Industrial (-40ºC to 85ºC)

Notes:

1. Pb-free packaging, complies to European Directive for Restriction of Hazardous Substances (RoHS directive).
Also Halide free and fully Green.

Package TypePI

64-lead, 9 x 9 x 0.9 mm Body, Quad Flat No-lead Package (QFN)

511
8266A-MCU Wireless-12/09

37 Packaging Information
PI
d
d

D

A

aaa C A
d

ccc C

A
A2
A3
A1
0.10

bbb C BE

LASER MARK FOR PIN 1
IDENTIFICATION IN THIS AREA

B

TOP VIEWSEATINGPLANECDRAWINGS NOT SCALED

D2SIDE VIEW

1.27
MILLIMETERSYMBOLR
PIN1 ID
0.20 R

E2

NOM. MAX.

A

---

---

0.90

A1

---

---

0.05

A2

---

0.65

0.70

0.30

0.007 0.010 0.012

0.18

5.55

L
b

e
L
j

0.10 m C A B

BOTTOM VIEW
ALL DIMENSIONS ARE IN MILLIMETERS.

MAX.

---

0.035

---

---

0.001

---

0.026 0.028

0.25

0.008 REF.

5.65

0.354 bsc
5.75

0.219 0.222 0.226

9.00 bsc

E

1.72

NOM.

---

9.00 bsc

D
D2

MIN.

0.20 REF.

A3
b

0.45

INCH

MIN.

0.354 bsc

E2

4.65

4.75

4.85

0.183 0.187 0.191

L

0.35

0.40

0.45

0.014 0.016 0.018

0.50 bsc

e
R

0.09

---

0.020 bsc
---

0.004

---

---

TOLERANCES OF FORM AND POSITION

aaa

0.10

bbb

0.10

0.004
0.004

ccc

0.05

0.002

02/12/2008

PACKAGE WARPAGE MAX 0.08 mm.

Atmel Nantes S.A.
La Chantrerie - BP 70602
44306 Nantes Cedex 3 - France

512

TITLE
PI - 64 leads - 9.0 x 9.0 mm - pitch 0.5mm
Quad Flat No Lead Package QFNDRAWING No.

REV.

PI

A

ATmega128RFA1
8266A-MCU Wireless-12/09

ATmega128RFA1
38 Errata
38.1 ATmega128RFA1 revision D (1.2)
•
•
•
•
•

Power-Chain turns off when power supply drops below 1.6V
JTAG interface reads wrong data
CSMA back-off calculation has reduced degree of randomness
Update of internal temporary registers for CSMA_SEED register may failInterrupt TRX24_CCA_ED_DONE may occur twice

38.2 ATmega128RFA1 revision C (1.1)
•
•
•
•
•
•
•

Power-Chain turns off when power supply drops below 1.6V
JTAG interface reads wrong data
CSMA back-off calculation has reduced degree of randomness
Update of internal temporary registers for CSMA_SEED register may failInterrupt TRX24_CCA_ED_DONE may occur twice
DVREG_EXT bit is not write-protected
ENDRT bits have wrong reset value

38.3 ATmega128RFA1 revision AB (1.0)
Not sampled.

38.4 Compiler package WinAVR-20090313
In the compiler package WinAVR-20090313 the SRAM start address has a wrong valueof 0x100. In this case the variables are randomly allocated across the extended I/Ospace 0x100 to 0x1FF. It causes an unpredictable behavior by random overwrite ofregisters (see also "JTAG interface reads wrong data" on page 514 and "DVREG_EXT
bit is not write-protected" on page 514).

Problem Fix/WorkaroundUse the linker option-Wl,--section-start=.data=0x800200

38.5 Detailed errata description
38.5.1 Power-Chain turns off when power supply drops below 1.6V
If the voltage of the pins DEVDD drops below 1.6V, the internal power chain turns off.
Some hardware settings (e.g. clock source) can alter their state unintentionally. Raising
the supply voltage above 1.8V again does not bring the circuit back to normal operation.
This condition can happen either by lowering the power supply voltage below 1.6V or
turn-off the supply source while other external devices are feeding DEVDD by theinternal ESD diodes of the IO stages (e.g. hardware debugger attached to the JTAG
interface) (2606).
If the power supply drops below 1.6V while being in Deep Sleep mode, the internal
power chain is not affected.

Problem Fix/Workaround
Turn on the Brown-Out Detector at any voltage level. The supply current in Deep Sleep
does not increase.

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38.5.2 JTAG interface reads wrong data
If the Power Reduction Register bits associated with the SRAM’s (PRRAM3…0 in
PRR2) and the 2.4GHz Transceiver (PRTRX24 in PRR1) are set, the JTAG interface
reads wrong data. (2613).

Problem Fix/WorkaroundDo not use PRRAM3…0 in PRR2 and PRTRX24 in PRR1. Force pin RSTN=0 and the
JTAG interface can erase the program memory.

38.5.3 CSMA back-off calculation has reduced degree of randomness
The CSMA back-off calculation in the transceiver extended operating modes has areduced degree of randomness (e.g. transceiver is in the state TX_ARET_ON) (2665).

Problem Fix/Workaround
Initialize CSMA_SEED registers with a random value.

38.5.4 Update of internal temporary registers for CSMA_SEED register may failThe update of the internal temporary registers of the CSMA_SEED registers may fail.
Read/write operation to the CSMA_SEED registers itself works as expected (2646).

Problem Fix/WorkaroundA sleep cycle of the transceiver updates the internal temporary registers.

38.5.5 Interrupt TRX24_CCA_ED_DONE may occur twice
When requesting a manually initiated CCA measurement in BUSY_RX state and during
an internal ED measurement, a TRX24_CCA_ED_DONE interrupt could be issued
immediately after the request. In this case the register bit CCA_DONE is equal to 0 and
an additional TRX24_CCA_ED_DONE interrupt is issued after finishing the CCA
measurement and register bit CCA_DONE is set to 1 (2000).

Problem Fix/Workaround
Prevent a frame reception during manually initiated CCA measurement• make sure that TRX_STATUS is not in RX_BUSY (i.e. start from state PLL_ON)• set bit RX_PDT_DIS=1• switch TRX_STATE to RX_ON• perform CCA measurement• set bit RX_PDT_DIS=038.5.6 DVREG_EXT bit is not write-protected
The external mode of the DVDD voltage regulator is not write-protected. If it is enabled(DVREG_EXT=1 in the register VREG_CTRL) with no external power supply for DVDD,
the device leaves normal operation and can’t be recovered by the Watchdog (2658).

Problem Fix/WorkaroundDo not write the bit DVREG_EXT in the register VREG_CTRL.

38.5.7 ENDRT bits have wrong reset value
The ENDRT bits in the registers DRTRAM3…0 have the wrong reset value. The dataretention of the associated SRAM in DEEP_SLEEP is disabled (2495).

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ATmega128RFA1
Problem Fix/Workaround
Set ENDRT=1 in DRTRAM3…0 at the beginning of the firmware program.

515
8266A-MCU Wireless-12/09

39 Revision history
Please note that the referring page numbers in this section are referring to thisdocument. The referring revision in this section are referring to the document revision

Rev. 8266A-MCU Wireless-12/09
1. Initial release

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ATmega128RFA1
Table of Contents
1 Pin Configurations.............................................................................. 2
2 Disclaimer............................................................................................ 2
3 Overview .............................................................................................. 3
3.1 Block Diagram ........................................................................................................ 3
3.2 Pin Descriptions...................................................................................................... 5
3.3 Compatibility to ATmega1281/2561 ....................................................................... 6

4 Resources............................................................................................ 7
5 About Code Examples........................................................................ 7
6 Data Retention..................................................................................... 7
7 AVR CPU Core..................................................................................... 9
7.1 Introduction............................................................................................................. 9
7.2 Architectural Overview ........................................................................................... 9
7.3 ALU – Arithmetic Logic Unit ................................................................................. 10
7.4 Status Register ..................................................................................................... 11
7.5 General Purpose Register File ............................................................................. 12
7.6 Stack Pointer ........................................................................................................ 13
7.7 Instruction Execution Timing ................................................................................ 15
7.8 Reset and Interrupt Handling ............................................................................... 15

8 AVR Memories................................................................................... 18
8.1 In-System Reprogrammable Flash Program Memory.......................................... 18
8.2 SRAM Data Memory ............................................................................................ 18
8.3 EEPROM Data Memory ....................................................................................... 20
8.4 EEPROM Register Description ............................................................................ 23
8.5 I/O Memory........................................................................................................... 25
8.6 General Purpose I/O Registers ............................................................................ 26
8.7 Other Port Registers............................................................................................. 26

9 Low-Power 2.4 GHz Transceiver...................................................... 29
9.1 Features ............................................................................................................... 29
9.2 General Circuit Description .................................................................................. 30
9.3 Transceiver to Microcontroller Interface............................................................... 31
9.4 Operating Modes .................................................................................................. 35
9.5 Functional Description.......................................................................................... 61
9.6 Module Description............................................................................................... 74
9.7 Radio Transceiver Usage..................................................................................... 83
9.8 Radio Transceiver Extended Feature Set ............................................................ 85

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9.9 Continuous Transmission Test Mode................................................................... 96
9.10 Abbreviations...................................................................................................... 98
9.11 Reference Documents...................................................................................... 100
9.12 Register Description ......................................................................................... 100

10 MAC Symbol Counter ................................................................... 133
10.1 Main Features................................................................................................... 133
10.2 Clock source selection and Sleep/Active mode operation ............................... 133
10.3 32 bit Register Access (Atomic Read/Write) .................................................... 133
10.4 Symbol Counter (32 bit, SCCNT) ..................................................................... 134
10.5 Symbol Counter SFD Timestamp Register (32 bit, SCTSR, Read Only) ........ 134
10.6 Symbol Counter Beacon Timestamp Register (32 bit, SCBTSR) .................... 134
10.7 Compare Unit (3x 32 bit, SCOCR1, SCOCR2, SCOCR3) ............................... 135
10.8 Interrupt Control Registers ............................................................................... 135
10.9 Backoff Slot Counter ........................................................................................ 135
10.10 Symbol Counter Usage .................................................................................. 135
10.11 Register Description ....................................................................................... 137

11 System Clock and Clock Options................................................ 147
11.1 Overview........................................................................................................... 147
11.2 Clock Systems and their Distribution ............................................................... 147
11.3 Clock Sources .................................................................................................. 148
11.4 Calibrated Internal RC Oscillator...................................................................... 149
11.5 128 kHz Internal Oscillator ............................................................................... 150
11.6 External Clock .................................................................................................. 150
11.7 Transceiver Crystal Oscillator .......................................................................... 151
11.8 Clock Output Buffer .......................................................................................... 152
11.9 Timer/Counter Oscillator .................................................................................. 152
11.10 System Clock Prescaler ................................................................................. 152
11.11 Register Description ....................................................................................... 153

12 Power Management and Sleep Modes ........................................ 156
12.1 Deep-Sleep Mode ............................................................................................ 156
12.2 AVR Microcontroller Sleep Modes ................................................................... 156
12.3 Power Reduction Register................................................................................ 159
12.4 Minimizing Power Consumption ....................................................................... 159
12.5 Supply Voltage and Leakage Control............................................................... 161
12.6 Register Description ......................................................................................... 166

13 System Control and Reset ........................................................... 176

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ATmega128RFA1
13.1 Resetting the AVR ............................................................................................ 176
13.2 Reset Sources .................................................................................................. 176
13.3 Internal Voltage Reference............................................................................... 179
13.4 Watchdog Timer ............................................................................................... 180
13.5 Register Description ......................................................................................... 183

14 I/O-Ports......................................................................................... 186
14.1 Introduction....................................................................................................... 186
14.2 Ports as General Digital I/O.............................................................................. 187
14.3 Alternate Port Functions................................................................................... 191
14.4 Register Description ......................................................................................... 204

15 Interrupts ....................................................................................... 211
15.1 Interrupt Vectors in ATmega128RFA1 ............................................................. 211
15.2 Reset and Interrupt Vector Placement ............................................................. 213
15.3 Moving Interrupts Between Application and Boot Section ............................... 216
15.4 Register Description ......................................................................................... 216

16 External Interrupts ........................................................................ 218
16.1 Pin Change Interrupt Timing ............................................................................ 218
16.2 Register Description ......................................................................................... 219

17 8-bit Timer/Counter0 with PWM ................................................... 226
17.1 Features ........................................................................................................... 226
17.2 Overview........................................................................................................... 226
17.3 Timer/Counter Clock Sources .......................................................................... 227
17.4 Counter Unit ..................................................................................................... 227
17.5 Output Compare Unit ....................................................................................... 228
17.6 Compare Match Output Unit............................................................................. 230
17.7 Modes of Operation .......................................................................................... 232
17.8 Timer/Counter Timing Diagrams ...................................................................... 236
17.9 Register Description ......................................................................................... 238

18 16-bit Timer/Counter (Timer/Counter 1, 3, 4, and 5)................... 244
18.1 Features ........................................................................................................... 244
18.2 Overview........................................................................................................... 244
18.3 Accessing 16-bit Registers............................................................................... 246
18.4 Timer/Counter Clock Sources .......................................................................... 249
18.5 Counter Unit ..................................................................................................... 249
18.6 Input Capture Unit ............................................................................................ 250
18.7 Output Compare Units...................................................................................... 252

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18.8 Compare Match Output Unit............................................................................. 254
18.9 Modes of Operation .......................................................................................... 256
18.10 Timer/Counter Timing Diagrams .................................................................... 264
18.11 Register Description ....................................................................................... 266

19 Timer/Counter 0, 1, 3, 4, and 5 Prescaler .................................... 304
19.1 Internal Clock Source ....................................................................................... 304
19.2 Prescaler Reset ................................................................................................ 304
19.3 External Clock Source...................................................................................... 304
19.4 Register Description ......................................................................................... 305

20 Output Compare Modulator (OCM1C0A)..................................... 307
20.1 Overview........................................................................................................... 307
20.2 Description........................................................................................................ 307
20.3 Timing Example................................................................................................ 308

21 8-bit Timer/Counter2 with PWM and Asynchronous Operation 309
21.1 Features ........................................................................................................... 309
21.2 Overview........................................................................................................... 309
21.3 Timer/Counter Clock Sources .......................................................................... 310
21.4 Counter Unit ..................................................................................................... 311
21.5 Modes of Operation .......................................................................................... 311
21.6 Output Compare Unit ....................................................................................... 316
21.7 Compare Match Output Unit............................................................................. 317
21.8 Timer/Counter Timing Diagrams ...................................................................... 319
21.9 Asynchronous Operation of Timer/Counter2.................................................... 320
21.10 Timer/Counter Prescaler ................................................................................ 322
21.11 Register Description ....................................................................................... 323

22 SPI- Serial Peripheral Interface.................................................... 330
22.1 Features ........................................................................................................... 330
22.2 Functional Description...................................................................................... 330__
22.3SS Pin Functionality ......................................................................................... 334
22.4 Register Description ......................................................................................... 336

23 USART............................................................................................ 339
23.1 Features ........................................................................................................... 339
23.2 Overview........................................................................................................... 339
23.3 Clock Generation.............................................................................................. 340
23.4 Frame Formats ................................................................................................. 343
23.5 USART Initialization ......................................................................................... 344

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23.6 Data Transmission – The USART Transmitter................................................. 345
23.7 Data Reception – The USART Receiver .......................................................... 348
23.8 Asynchronous Data Reception......................................................................... 352
23.9 Multi-processor Communication Mode............................................................. 355
23.10 Register Description ....................................................................................... 356
23.11 Examples of Baud Rate Setting ..................................................................... 365

24 USART in SPI Mode ...................................................................... 368
24.1 Overview........................................................................................................... 368
24.2 USART MSPIM vs. SPI .................................................................................... 368
24.3 SPI Data Modes and Timing ............................................................................ 369
24.4 Frame Formats ................................................................................................. 370
24.5 Data Transfer.................................................................................................... 371
24.6 USART MSPIM Register Description ............................................................... 373

25 2-wire Serial Interface................................................................... 377
25.1 Features ........................................................................................................... 377
25.2 2-wire Serial Interface Bus Definition ............................................................... 377
25.3 Data Transfer and Frame Format..................................................................... 378
25.4 Multi-master Bus Systems, Arbitration and Synchronization ........................... 380
25.5 Overview of the TWI Module ............................................................................ 382
25.6 Using the TWI................................................................................................... 384
25.7 Transmission Modes ........................................................................................ 387
25.8 Multi-master Systems and Arbitration .............................................................. 400
25.9 Register Description ......................................................................................... 401

26 AC – Analog Comparator ............................................................. 407
26.1 Analog Comparator Multiplexed Input.............................................................. 407
26.2 Register Description ......................................................................................... 408

27 ADC – Analog to Digital Converter.............................................. 410
27.1 Features ........................................................................................................... 410
27.2 Operation.......................................................................................................... 411
27.3 ADC Start-Up.................................................................................................... 412
27.4 Starting a Conversion....................................................................................... 413
27.5 Pre-scaling and Conversion Timing ................................................................. 413
27.6 Changing Channel or Reference Selection...................................................... 417
27.7 ADC Noise Canceller ....................................................................................... 420
27.8 ADC Conversion Result ................................................................................... 423
27.9 Internal Temperature Measurement................................................................. 425

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27.10 SRAM DRT Voltage Measurement ................................................................ 426
27.11 Register Description ....................................................................................... 427

28 JTAG Interface and On-chip Debug System............................... 435
28.1 Features ........................................................................................................... 435
28.2 Overview........................................................................................................... 435
28.3 TAP - Test Access Port .................................................................................... 436
28.4 TAP Controller .................................................................................................. 437
28.5 Using the Boundary-scan Chain....................................................................... 438
28.6 Using the On-chip Debug System .................................................................... 438
28.7 On-chip Debug Specific JTAG Instructions ...................................................... 439
28.8 Using the JTAG Programming Capabilities...................................................... 439
28.9 Bibliography...................................................................................................... 440
28.10 On-chip Debug Related Register in I/O Memory............................................ 440

29 IEEE 1149.1 (JTAG) Boundary-scan............................................ 441
29.1 Features ........................................................................................................... 441
29.2 System Overview ............................................................................................. 441
29.3 Data Registers.................................................................................................. 441
29.4 Boundary-scan Specific JTAG Instructions ...................................................... 443
29.5 Boundary-scan Chain....................................................................................... 444
29.6 Boundary-scan Related Register in I/O Memory.............................................. 447
29.7 Boundary-scan Description Language Files .................................................... 448
29.8 ATmega128RFA1 Boundary-scan Order ......................................................... 448

30 Boot Loader Support – Read-While-Write Self-Programming... 450
30.1 Features ........................................................................................................... 450
30.2 Application and Boot Loader Flash Sections ................................................... 450
30.3 Read-While-Write and No Read-While-Write Flash Sections .......................... 451
30.4 Boot Loader Lock Bits ...................................................................................... 453
30.5 Addressing the Flash During Self-Programming.............................................. 453
30.6 Self-Programming the Flash............................................................................. 454
30.7 Register Description ......................................................................................... 462

31 Memory Programming.................................................................. 464
31.1 Program And Data Memory Lock Bits .............................................................. 464
31.2 Fuse Bits........................................................................................................... 465
31.3 Signature Bytes ................................................................................................ 466
31.4 Calibration Byte ................................................................................................ 467
31.5 Page Size ......................................................................................................... 467

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31.6 Parallel Programming Parameters, Pin Mapping, and Commands ................. 467
31.7 Parallel Programming....................................................................................... 469
31.8 Serial Downloading .......................................................................................... 477
31.9 Programming via the JTAG Interface............................................................... 481

32 Application Circuits ...................................................................... 493
32.1 Basic Application Schematic ............................................................................ 493
32.2 Extended Feature Set Application Schematic.................................................. 494

33 Register Summary ........................................................................ 496
34 Electrical Characteristics ............................................................. 501
34.1 Absolute Maximum Ratings.............................................................................. 501
34.2 Clock Characteristics........................................................................................ 502
34.3 System and Reset Characteristics ................................................................... 502
34.4 Power Management Electrical Characteristics................................................. 503
34.5 2-wire Serial Interface Characteristics ............................................................. 503
34.6 SPI Timing Characteristics ............................................................................... 504
34.7 ADC Characteristics ......................................................................................... 505
34.8 Transceiver Electrical Characteristics .............................................................. 507

35 Typical Characteristics................................................................. 510
35.1 Internal Oscillator Speed .................................................................................. 510

36 Ordering Information .................................................................... 511
37 Packaging Information ................................................................. 512
38 Errata ............................................................................................. 513
38.1 ATmega128RFA1 revision D (1.2) ................................................................... 513
38.2 ATmega128RFA1 revision C (1.1) ................................................................... 513
38.3 ATmega128RFA1 revision AB (1.0) ................................................................. 513
38.4 Compiler package WinAVR-20090313 ............................................................ 513
38.5 Detailed errata description ............................................................................... 513

39 Revision history ............................................................................ 516
Table of Contents............................................................................... 517

523
8266A-MCU Wireless-12/09

Disclaimer

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