LTC3256
Wide VIN Range
Dual Output 350mA Step-Down
Charge Pump with Watchdog Timer
DESCRIPTIONFEATURES

Input Voltage Range: 5.5V to 38V
nn Independently Enabled 5V and 3.3V Fixed Outputs
nn 5V Output: 100mA Max
nn 3.3V LDO Output: 250mA Max
nn Multimode Step-Down Charge Pump (2:1, 1:1) with
Automatic Mode Switching
nn Low Quiescent Current
nn 20μA with Both Outputs Regulating (No Load)nn 0.5μA in Shutdown
nn Engineered for Diagnostic Coverage inISO26262 Systems
nn 1.1V Reference Output for System Diagnostics
nn Power-On Reset and Watchdog Controller with
Adjustable Timing
nn Overcurrent Fault Protection on Each Output
nn Overtemperature Protection
nn 150°C Max Operating Junction Temperaturenn Thermally Enhanced 16-Lead MSOP Packagenn

APPLICATIONS
Automotive ECU/CAN Transceiver Supplies
Industrial/Telecom Housekeeping Supplies
nn Low Power 12V to 5V and 3.3V Conversion
nn
nn

The LTC®3256 is a wide input range switched capacitor
step-down DC/DC converter that produces two regulated
outputs: a 5V output via direct connection to the charge
pump output, and a 3.3V output via a low dropout (LDO)
linear post-regulator. The device provides up to 350mAof total output current. At 12V VIN and maximum load on
both outputs, power dissipation is reduced by over 2W
compared to a dual LDO regulator solution.
The LTC3256 maximizes efficiency by running the charge
pump in 2:1 mode over as wide an operating range as possible, and automatically switches to 1:1 mode as needed
due to VIN and load conditions. Controlled input current andswitching slew rates minimize conducted and radiated EMI.
An integrated watchdog timer, independent power good
outputs and reset input ensure reliable system operationand fault monitoring. A buffered 1.1V reference output
enables system self-testing for safety critical applications.
The LTC3256 has numerous safety features including
overcurrent fault protection, overtemperature protection
and tolerance of 38V input transients. The LTC3256 isavailable in a thermally enhanced 16-lead MSOP plastic
package with exposed pad (MSE16).
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks andThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the propertyof their respective owners.

TYPICAL APPLICATIONHigh Efficiency Dual Output Power Supply

Power Dissipation vs Input Voltage
5.0

10µF
C+

RT
WT
5.5V TO 38VINPUT SUPPLY

VIN

10µF

C–
OUT5

LTC3256

EN5
EN3

GND

5V OUTPUT
10µF 100mA MAX

OUT3

3.3V LDO OUTPUT
10µF 250mA MAX

1M
PG5
PG3
RSTI
RST
WDI
REFOUT
3256 TA01

POWER DISSIPATION (W)OUTCP

3.3V LOAD = 250mA
5V LOAD = 100mA

4.5

1µF

4.0
3.5
3.0

IDEAL DUAL LDO

2.5
2.0
1.5
1.0

LTC3256

0.5
MICROCONTROLLER
INTERFACE

0.0

0.1µF

6

7

8

9

10 11 12 13 14 15 16

INPUT VOLTAGE (V)3256 TA01a

3256faFor more information www.linear.com/LTC3256

1

LTC3256
ABSOLUTE MAXIMUM RATINGSPIN CONFIGURATION(Notes 1, 2)

VIN, EN3, EN5, WDI..................................... –0.3V to 38V
OUTCP, OUT3, OUT5.................................. –0.3V to 5.5V
OUT3, OUT5 Short Circuit Duration.................. Indefinite
PG3, PG5, REFOUT................................ –0.3V to VOUTCP
RST............................................................ –0.3V to 5.5V
WT, RT................................................... –0.3V to VOUTCPRSTI .......................................................... –0.3V to 5.5V
Operating Junction Temperature Range (Notes 3, 4)
LTC3256E........................................... –40°C to 125°C
LTC3256I............................................ –40°C to 125°C
LTC3256H........................................... –40°C to 150°C
LTC3256MP........................................ –55°C to 150°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................... 300°C

TOP VIEW
C– 1
C+ 2
OUTCP 3
OUT5 4REFOUT 5
OUT3 6
PG3 7
PG5 8

17
GND

16
15
14
13
12
11
10
9

EN5
EN3
VIN
WDI
RSTI
RT
WT
RST

MS PACKAGE
16-LEAD PLASTIC MSOPTJMAX = 150°C, θJC = 10°C/W
θJA = 40°C/W
EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCBORDER INFORMATION http://www.linear.com/product/LTC3256#orderinfo
LEAD FREE FINISH

TAPE AND REELPART MARKING*PACKAGE DESCRIPTIONTEMPERATURE RANGE

LTC3256EMSE#PBF

LTC3256EMSE#TRPBF

3256

16-Lead Plastic MSOP

–40°C to 125°C

LTC3256IMSE#PBF

LTC3256IMSE#TRPBF

3256

16-Lead Plastic MSOP

–40°C to 125°C

LTC3256HMSE#PBF

LTC3256HMSE#TRPBF

3256

16-Lead Plastic MSOP

–40°C to 150°C

LTC3256MPMSE#PBF

LTC3256MPMSE#TRPBF

3256

16-Lead Plastic MSOP

–55°C to 150°C

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels throughdesignated sales channels with #TRMPBF suffix.

3256fa2

For more information www.linear.com/LTC3256

LTC3256
ELECTRICAL CHARACTERISTICS

The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 3). VIN = 12V, CFLY = 1µF unless otherwise noted.
SYMBOLPARAMETER

VIN

Operating Input Voltage Range (Note 5)

CONDITIONSl

VIN Undervoltage Lockout Thresholdl

VIN Quiescent Current
EN5 = EN3 = 0V
Only One Output Enabled
Both OUT3 and OUT5 Enabled

MIN

Shutdown
Output In Regulation, No Load
Output In Regulation, No Load

EN3, EN5 Input High Voltage
EN3, EN5 Input Low Voltage

TYP

MAX

UNITS

38

V

1.8

2.7

V

0.5
15
20

2
30
35

µA
µA
µA

1.2

2

V

5.5

0.4

0.9

–1

0

1

µA

3

µA

EN3, EN5 Input Low Current

VPIN = 0V

EN3, EN5 Input High Current

VPIN = 38V

1

V

Charge Pump Operation
VOUTCPOUTCP Regulation Voltage

EN3 and/or EN5 High

5.05

V

OUTCP Short Circuit Current

VOUTCP = GND

600

mA

Charge Pump Output Impedance

2:1 Step-Down Mode
1:1 Step-Down Mode, VIN = 5.5V

2
2

Ω
Ω

5V Output Operation
VOUT5

Fixed 5V Output Regulation (Note 5)

EN5 High, VIN = 5.5V, IOUT ≤ 100mA
EN5 High, VIN = 12V, IOUT ≤ 100mA
EN5 High, VIN = 38V, IOUT = 0mA

OUTCP to OUT5 Power Switch
On-ResistanceEN5 High

OUT5 Overvoltage Threshold

VOUT5 Rising Makes PG5 Go Low
VOUT5 Falling Makes PG5 Go Hi-Z

OUT5 Undervoltage Threshold

VOUT5 Rising Makes PG5 go Hi-Z
VOUT5 Falling Makes PG5 go Low

l
l
l

4.85
4.85
4.85

5.05
5.05
5.05

5.19
5.19
5.19

0.6
5.25
5.1

l

l

4.6

V
V
V
Ω

5.4

4.9
4.75

V
V
V
V

PG5 Output Low Voltage

IPG5 = 100µA

l

0.1

0.4

V

PG5 Output Hi-Z Leakage

VPG5 = 5V

l

–1

0

1

µA

EN3 High, VIN = 5.5V, IOUT ≤ 250mA
EN3 High, VIN = 12V, IOUT ≤ 250mA
EN3 High, VIN = 38V, IOUT = 0mA

l
l
l

3.170
3.200
3.234

3.30
3.30
3.30

3.366
3.366
3.366

V
V
V

OUT3 Overvoltage Threshold

VOUT3 Rising Makes PG3 Go Low
VOUT3 Falling Makes PG3 Go Hi-Z

l

3.465
3.35

3.58

V
V

OUT3 Undervoltage Threshold

VOUT3 Rising Makes PG3 Go Hi-Z
VOUT3 Falling Makes PG3 Go Low

3.3V LDO Operation
VOUT3

Fixed 3.3V LDO Output Regulation (Note 5)l

PG3 Output Low Voltage

IPG3 = 100µAl

PG3 Output Hi-Z Leakage

VPG3 = 5Vl

EN3 and/or EN5 High, IREFOUT = 0mA

l

3.04

3.24
3.135

V
V

0.1

0.4

V

–1

0

1

µA

1.068

1.1

1.132

V

2

4

kΩ

–1.9

–2.6

µA

Buffered 1.1V Reference Output (REFOUT)REFOUT Pin Output Voltage
REFOUT Pin Output ResistanceReset Timer Control (RT)
External Timer RT Pull-Up Current

VRT = 0.3V

l

–1.1

External Timer RT Pull-Down Current
Internal Timer RT Pull Down Current

VRT = 1.3Vl

1.1

VRT = VOUTCPl

RT Internal Timer Select Threshold

VRT Rising

l

1.8

1.9

2.6

µA

0.25

1

µA

2.3

2.7

V
3256faFor more information www.linear.com/LTC3256

3

LTC3256
ELECTRICAL CHARACTERISTICS

The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 3). VIN = 12V, CFLY = 1µF unless otherwise noted.
SYMBOLPARAMETERCONDITIONS

MIN

TYP

MAX

1.2

1.26

1.1

1.16

UNITS

Reset Timer Input (RSTI)RSTI Input High Voltage

l

RSTI Input Low VoltagelV
V

RSTI Input Low Current

VRST_IN = 0V

l

–1

0

1

µA

RSTI Input High Current

VRST_IN = 5V

l

–1

0

1

µA

260

ms

Reset Output (RST)tRST(INT)Internal Reset Timeout Period

VRT = VOUTCP

l

150

200

tRST(EXT)

External Reset Timeout Period

CRT = 2.2nF

l

26

32

44

ms

tUV

RSTI Low to RST Asserted

From RSTI falling to 1V or less

l

10

80

150

µs

RST Output Voltage Low

VOUTCP = 5V, IRST = 100µA

l

0.1

0.4

V

RST Output Voltage High Leakage

RST = 5V

l

–1

0

1

µA

External Timer WT Pull-Up Current

VWT = 0.3V

l

–1.1

–1.9

–2.6

μA

External Timer WT Pull-Down Current

VWT = 1.3V

l

1.1

1.9

2.6

μA

Internal Timer WT Detect Pull Down Current

VWT = VOUTCP

l

0.25

1

μA

WT Internal Timer Select Threshold

VWT Rising

l

1.8

2.3

2.7

V

1.6

2

s

Watchdog Timer Control (WT)Watchdog Input (WDI)tWDU(INT)Internal Watchdog Upper Boundary

VWT = VOUTCP

l

1.3
37.5

50

62.5

ms

200

260

340

ms

tWDL(INT)Internal Watchdog Lower Boundary

VWT = VOUTCPltWDR(EXT)

External Watchdog Reset TimeCWT = 2.2nF

ltWDU(EXT)

External Watchdog Upper BoundarytWDR(EXT) • (128/129)

mstWDL(EXT)

External Watchdog Lower BoundarytWDR(EXT) • (5/129)

ms

WDI Input High Voltage

1.2

WDI Input Low Voltage

0.4

0.9

2

V
V

WDI Input Low Current

VWD_IN = 0V

–1

0

1

µA

WDI Input High Current

VWD_IN = 5V

–1

0

1

µA

Input PulsewidthlNote 1: Stresses beyond those listed under Absolute Maximum Ratings may
cause permanent damage to the device. Exposure to any Absolute Maximum
Rating condition for extended periods may affect device reliability and lifetime.
Note 2: All voltages are referenced to GND unless otherwise specified.
Note 3: The LTC3256E is guaranteed to meet performance specifications
from 0°C to 85°C operating junction temperature. Specifications overthe –40°C to 125°C operating junction temperature range are assured bydesign, characterization and correlation with statistical process controls.
The LTC3256I is guaranteed over the –40°C to 125°C operating junction
temperature range. The LTC3256H is guaranteed over the –40°C to 150°C
operating junction temperature range. The LTC3256MP is guaranteed andtested over the –55°C to 150°C operating junction temperature range.
High junction temperatures degrade operating lifetimes; operating lifetime
is derated for junction temperatures greater than 125°C. Note that the
maximum ambient temperature consistent with these specifications isdetermined by specific operating conditions in conjunction with board layout,
the rated package thermal resistance and other environmental factors.

100

ns

The junction temperature (TJ, in °C) is calculated from the ambient
temperature (TA, in °C) and power dissipation (PD, in Watts) according to
the formula:
TJ = TA + (PD • θJA)
where θJA (in °C/W) is the package thermal impedance.
Note 4: This IC has overtemperature protection that is intended to protect
the device during momentary overload conditions. Junction temperatures
will exceed 150°C when overtemperature protection is active. Continuous
operation above the specified maximum operating junction temperature
may impair device reliability.
Note 5: The maximum operating junction temperature of 150°C must be
followed. Certain combinations of input voltage and output current willcause the junction temperature to exceed 150°C and must be avoided. See
Thermal Management section for information on calculating maximum
operating conditions. Due to thermal limitations of production equipment,
only no load regulation is checked at 38V.

3256fa4

For more information www.linear.com/LTC3256

LTC3256
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.
No Load Input Current
vs Input Voltage

Input Shutdown Current
vs Input Voltage

8
7
6
5
4

50

BOTH HIGH
EN5 HIGH
EN3 HIGH

40

IIN (µA)

IIN (µA)

50

125°C
85°C
25°C
–55°C

9

150°C
25°C
–55°C

40

30

IIN (µA)

10

Input Operating Current
vs Input Voltage

20

30

20

3
2

10

10

0

0

1
0

0

4

8

12 16 20 24 28 32 36 40

0

5

10

15

VIN (V)

20

25

30

3.35

3.35

3.30
3.25
150°C
25°C
–55°C

3.20

10

15

20

25

30

35

4.5

3.5

3.20

3.0

5

6

7

8

9

8

9

5.10

5.10
VOUT5 (V)

5.00
4.95
4.90

150°C
25°C
–55°C

4.85
25

30

35

40

Efficiency and Power Loss
vs Input Voltage

3256 G07

90

125°C
25°C
–55°C

IOUT5 = 100mA

5.05
5.00
4.95
4.90

3.5

60

3.0

50

8

9

10 11 12 13 14 15

2.0

30

1.5

20

1.0

0

7

2.5

EFFICIENCY

40

10
6

4.0

70

4.80

5

4.5
IOUT3 = 250mA
IOUT5 = 100mA

80

4.85

VIN (V)

VIN (V)10 11 12 13 14 153256 G06

EFFICIENCY (%)

5.15

20

7

0.5

LOSS
5

6

POWER LOSS (W)VOUT5 (V)

5.20

15

6

VIN (V)

5V Output Voltage
vs Input Voltage at 100mA

5.15

10

No Load53256 G05

IOUT5 = 10mA5

2.5

10 11 12 13 14 15

VOUTCP
VOUT5
VOUT3

4.0

VIN (V)

5.05

10 11 12 13 14 15

5.0

3.25

5V Output Voltage
vs Input Voltage at 10mA

0

9

5.5

125°C
25°C
–55°C

3256 G04

4.80

8Output Voltages vs Input Voltage

3.30

3.15

40

IOUT3 = 250mA

VIN(V)

5.20

73256 G03

VOUT (V)3.40

VOUT3 (V)VOUT3 (V)

3.45

3.40

5

6

VIN (V)

3.3V Output Voltage
vs Input Voltage at 250mA

IOUT3 = 25mA

053256 G02

3.3V Output Voltage
vs Input Voltage at 25mA

3.15

40

VIN (V)
3256 G01

3.45

35

EN3=EN5=HIGH

7

8

9

10 11 12 13 14 15

0.0

VIN (V)
3256 G08

3256 G09

3256faFor more information www.linear.com/LTC3256

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LTC3256
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.
Internal Watchdog Timeout
Period vs Input Voltage

Internal Reset Timeout Period
vs Temperature

REFOUT Voltage vs Input Voltage
1.14

0.30

1.8

1.13

1.7
0.25

1.10
1.09

0.20

0.15

150°C
25°C
–55°C

1.07
0

5

10

15

20

25

30

35

1.3
0.10
−60

40

VIN (V)

−30

0

30

60

90

120

1k
100
10
1

1k
3256 G13

30

60

90

120
3256 G12

RSTI Threshold vs Temperature

500k

1.230

100k
RSTI THRESHOLD (V)WATCHDOG TIMEOUT PERIOD, TRST(EXT) (ms)10k

0TEMPERATURE (°C)

Watchdog Timeout Period
vs WT Capacitance

50k

0.01
0.1
1
10
100
RT PIN CAPACITANCE, CRT (nF)−303256 G11

Reset Timeout Periodvs RT Capacitance

0.1
0.001

1.2
−60

150

TEMPERATURE (°C)
3256 G10RESET TIMEOUT PERIOD, TRST(EXT) (ms)

1.5
1.4

1.08

1.06

TIME (SEC)

1.6

1.11

TIME (SEC)

VREFOUT (V)

1.12

10k
1k
100

1.190

1.170

1.150

10
1
0.001

1.210

RISINGFALLING
0.01
0.1
1
10
100
WT PIN CAPACITANCE, CWT (nF)

1k
3256 G14

1.130
–60

–30

0
30
60
90
TEMPERATURE (°C)

120

150

3256 G15

3256fa6

For more information www.linear.com/LTC3256

LTC3256
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.
Output Ripple

Output Ripple

Output Ripple
OUTCP
AC 0.1V/DIV

OUTCP
AC 0.1V/DIV

OUTCP
AC 0.1V/DIV

OUT5
AC 0.1V/DIV

OUT5
AC 0.1V/DIV

OUT5
AC 0.1V/DIV

OUT3
AC 5mV/DIV

OUT3
AC 5mV/DIV

OUT3
AC 5mV/DIVREFOUT
AC 5mV/DIVREFOUT
AC 5mV/DIVREFOUT
AC 5mV/DIV

25µs/DIV

3256 G16

5µs/DIV

VIN = 12V
IOUT5 = 100mA
IOUT3 = 250mA

OUT3 Power-Up
EN3

1

EN3

0

OUT3
DC 1V/DIVOUT3
DC 1V/DIV

PG3

PG3

VIN = 5.5V
OUT5 = 20mA
IOUT3 = 100mA

OUT3 Power-Up

OUT3 Transient Response

OUT3
AC 20mV/DIV

100µs/DIVOUT5 Power-Up
EN5

0

1

3256 G20

OUTCP
DC 5V/DIVOUT5
DC 2V/DIVOUT5
DC 2V/DIV

250mA
IOUT3
20mA
100µs/DIV

VIN = 5.5V
ROUT3 = 33Ω

VIN = 12V

OUT5 Power-Up

OUT5 Transient Response

OUT5
AC 50mV/DIV
VIN=5.5V
IOUT5PG5500µs/DIV
VIN = 12V
ROUT5 = 100Ω

3256 G21

OUT5
AC 50mV/DIV
VIN=12V0

OUTCP
DC 5V/DIV

PG53256 G17

OUTCP
AC 0.1V/DIV

3256 G19

VIN = 12V
ROUT3 = 33Ω

EN5

VIN = 12V
IOUT5 = 20mA
IOUT3 = 100mA

0

OUTCP
DC 5V/DIV

1

5µs/DIV1OUTCP
DC 5V/DIV

100µs/DIV

3256 G17

3256 G22

100µs/DIV

3256 G23

100mA
10mA
100µs/DIV

3256 G24

VIN = 5.5V
ROUT5 = 100Ω

3256faFor more information www.linear.com/LTC3256

7

LTC3256
PIN FUNCTIONS
C– (Pin 1): Charge Pump Flying Capacitor Negative Connection.
C+ (Pin 2): Charge Pump Flying Capacitor Positive Connection.
OUTCP (Pin 3): Charge Pump Output. The charge pump
output should be bypassed with a 10µF or greater X7R
ceramic capacitor. The charge pump output is enabled ifeither ENx pin is logic high. OUTCP is the input supply
for the 3.3V LDO.
OUT5 (Pin 4): 5V Output Pin. Connects to the charge
pump output, OUTCP, through an internal power switch
controlled by the EN5 input when VIN > 10V (typical),and regulates to 5V with VIN as a power source when
VIN < 10V (typical).
REFOUT (Pin 5): 1.1V Reference Output. Provides a buffered version of the LTC3256’s internal bandgap reference
voltage with 2k output impedance (typical). To maximize
supply rejection, REFOUT should be bypassed with a 0.1µF
ceramic capacitor.
OUT3 (Pin 6): 3.3V Low-Dropout Linear Regulator (LDO)
Output Pin. The charge pump output, OUTCP, serves as
the 3.3V LDO’s input supply.
PG3 (Pin 7): Power Good Open Drain Logic Output. Goes
high impedance when OUT3 is near its final operating voltage. PG3 is intended to be pulled up to a low voltage supply(such as OUT3, OUT5 or OUTCP) with an external resistor.
PG5 (Pin 8): Power Good Open Drain Logic Output. Goes
high impedance when OUT5 is near its final operating voltage. PG5 is intended to be pulled up to a low voltage supply(such as OUT3, OUT5 or OUTCP) with an external resistor.
RST (Pin 9): Reset Open Drain Logic Output. The RST
pin is low impedance to GND during the reset period, andgoes high impedance during the watchdog period. RST is
intended to be pulled up to low voltage supply (such as
OUT3, OUT5, or OUTCP) with an external resistor.
WT (Pin 10): Watchdog Timer Control Pin. Attach an
external capacitor (CWT) to GND to set the watchdog
upper boundary timeout. Tie WT to OUTCP to generate atimeout of about 1.6s. Tie WT and WDI to GND to disable
the watchdog timer.

RT (Pin 11): Reset Timeout Control Pin. Attach an external
capacitor (CRT) to GND to set the reset timeout period,
RT can be left open to minimize the reset timeout. Tie RT
to OUTCP to generate a reset timeout of about 200ms.
RSTI (Pin 12): Reset Logic Comparator Input Pin. The RSTI
input is compared to a 1.2V (typical) threshold voltage. If
RSTI is below the threshold voltage the LTC3256 will enter
the reset state and drive the RST pin low. Once RSTI rises
above the threshold voltage, the reset timer is started andthe RST pin is held low until the reset period times out.
WDI (Pin 13): Watchdog Logic Input Pin. Application
circuitry must toggle the logic state of this pin such thatfalling edges occur at a rate faster than the watchdog upper boundary time but slower than the watchdog lower
boundary time. If these conditions are not met, RST will
be asserted low. Tie WT and WDI to GND to disable thewatchdog timer. Do not float this pin.
VIN (Pin 14): Power Input Pin. Input voltage for bothcharge pump and IC control circuitry.
EN3 (Pin 15): Logic input pin which enables the 3.3V LDO
when high and disables it when low. Bringing EN3 highcauses the charge pump to enable if it isn’t already on. The
LDO powers up once the charge pump output, OUTCP,
rises above 97.5% of its regulation value (typical). The
EN3 pin has a 1μA (typical) pull down current to groundand can tolerate 38V inputs.
EN5 (Pin 16): Logic Input Pin. Enables or disables the 5V
output, OUT5. Bringing EN5 high causes the charge pumpto enable if it isn’t already on. When the charge pump output
rises above 97.5% of its regulation value (typical), a fault
protected internal power switch connects OUTCP to OUT5,
delivering power to any OUT5 load. A soft-start circuit limits
any inrush current through the switch to help avoid glitching
the charge pump output. If the input voltage falls below 10V(typical) and the charge pump regulates to a voltage lower
than 5V, OUT5 receives its power directly from a VIN-powered
1:1 mode regulator. The EN5 pin has a 1μA (typical) pull
down current to ground and can tolerate 38V inputs.
GND (Exposed Pad): Ground. The exposed package pad isground and must be soldered to the PC board ground plane
for proper functionality and for rated thermal performance.
3256fa8

For more information www.linear.com/LTC3256

LTC3256
TIMING DIAGRAM
Reset Timing
RSTI
tUV

tRST

RST
3256 TD01

Watchdog Timing
WDI

RSTt < tWDLtRSTtWDL < t < tWDU

tWDR

tRST

3256 TD02

3256faFor more information www.linear.com/LTC3256

9

LTC3256SIMPLIFIED BLOCK DIAGRAM
VIN
2:1/1:1 MODE STEP-DOWN CHARGE PUMPEN5

OUT5 ONENABLE LOGICEN3OUTCP ON

VIN-POWERED
1:1 MODE
5V REGULATORVOUTCP
5.05V

OUT3 ON
5V

3.6V

–
+

5.5V

1.1V
BANDGAPREFERENCE

7.2V

1:1
MODE

–
+

REFOUT
2k

OUTCP
GOOD
RST

38V

VIN

C–

2:1
MODE
OUTCP

3.4V

3.3V 250mA LDO

–
+

3.3V

FAULT-PROTECTEDPMOS SWITCH

+
–
CLOCK
OSCILLATORWATCHDOG
TIMER

OUT5 INPUTSELECTOR

–
+

1.2V

5V

–
+
–
+
–
+

WT

WDI

10.1V

EXTERNAL
FLYINGCAPACITORCONNECTION

OUT3

RSTI

RT

C+

FALLINGEDGE
DETECTOR

PG3

POWER GOOD
WINDOW
COMPARATORS

PG5

–
+
OUT5

GND
3256 BD

3256fa10

For more information www.linear.com/LTC3256

LTC3256
APPLICATIONS INFORMATIONThe LTC3256 is an inductorless wide input range step-down
DC/DC converter that produces 5V and 3.3V regulated
outputs with a total output current of 350mA. It uses a
step-down charge pump with automatic 2:1/1:1 modeswitching as a pre-regulator for the 5V and 3.3V outputs.
This optimizes system efficiency and minimizes thermal
problems due to excess power dissipation. In typical
12V automotive systems, the LTC3256 reduces power
dissipation by a full 2W at maximum load relative to adual LDO solution.
Each regulated output may be independently enabled toprovide maximum flexibility. Enabling either of the regulator
outputs will first turn on the step-down charge pump. Oncethe charge pump nears its regulation point, the enabled
outputs will turn on in a controlled, soft-started manner.
The 3.3V output is provided by an LDO that is always
powered from the charge pump output. The 5V output
is typically powered from the regulated charge pump via
an overcurrent protected switch directly connected to thecharge pump output.
The charge pump typically produces a regulated 5.05V
output but allows this output to drop as needed in order tostay in 2:1 mode and maximize overall efficiency whenever
VIN falls below ~10.1V. If VIN falls near the low end of its
operating range, the charge pump automatically enters
1:1 mode as required to keep the 3.3V LDO in regulation.
Whenever the charge pump output drops below 5V, theregulated 5V output will automatically be supplied using
a simple gated switch regulator powered from VIN.
2:1 Step-Down Charge Pump Operation (VIN > ~10.1V)
The increased efficiency and reduced power dissipation
advantages of the LTC3256 arise from the use of a 2:1
step-down charge pump to perform the bulk of the voltage
step-down from VIN to 5V and 3.3V. An ideal 2:1 chargepump has the property that its input current is exactly
half its output current (See Figure 1). In real-world charge
pumps like the LTC3256, input current slightly exceeds
half the output current due to additional current needed
for biasing and for driving power switches.

IIN =

+
–

IDEAL 2:1 CHARGE PUMP

ILOAD
2

INPUT

OUTPUT

ILOAD

ILOAD

+

2

VOUT

GND

–

VIN

LOAD

3256 F01

IIN =

ILOAD

ILOAD
2

Figure 1. Steady-State Time-Averaged Current
Flows in an Ideal 2:1 Charge Pump

Figure 2 shows the power switch topology of the 2:1
step-down charge pump in the LTC3256. When operating in 2:1 mode, the part employs a two phase clock toturn on only switches A and C in one phase followed byswitches B and D only in the other phase. Current source
IA controls the maximum output current that the part candeliver. When the charge pump clock is active, VOUTCP
will increase towards VIN/2. Once VOUTCP reaches theappropriate regulation point, the charge pump shuts off
all four switches and enters a SLEEP state to minimize
quiescent current until the output voltage falls below its
regulation point.
VIN

+
–

IA

VIN

SWITCH A

SWITCH B

C+
OUTCP

CFLY

+

C–

VOUTCPGND
SWITCH D

SWITCH C
COUTCP
3256 F02–

Figure 2. LTC3256 2:1 Step-Down Charge
Pump Power Switch Topology

3256faFor more information www.linear.com/LTC3256

11

LTC3256
APPLICATIONS INFORMATION
Under typical conditions (VIN > 10.1V), the LTC3256
operates in 2:1 mode and both the 5V output and 3.3V
LDO are powered directly from the charge pump output(see Figure 3).

VOUTCP

5.05V

PMOS
SWITCH
VIN

12V INOUT5CHARGE PUMPIN 2:1 MODE
350mA
MAX OUTPUT

3.3V LDOOUT3

5V OUT
100mA MAX

3.6V

3.3V OUT
250mA MAX

VIN
5.5V

OUTCP

10.1V

38V

3256 F03

1:1
MODE

5.05V PREREGULATED OUTPUT FOR
EXTERNAL BYPASS CAPACITOR CONNECTION

Figure 3. Power Connections for Typical 12V VIN Operation

The overall efficiency and power dissipation under typical
2:1 step-down conditions can be approximated with theequations below.
Total LTC3256 efficiency when VIN > ~10.1V:
η≅

7.2V

5V •IOUT5 + 3.3V •IOUT3I⎛I⎞
VIN • ⎜ OUT5 + OUT3 ⎟⎝ 2
2 ⎠Total LTC3256 power dissipation when VIN > ~10.1V:
⎛V
⎞
⎛V
⎞
PD ≅ ⎜ IN – 5V ⎟ •IOUT5 + ⎜ IN – 3.3V ⎟ •IOUT3
⎝ 2
⎠
⎝ 2
⎠
2:1 Step-Down Charge Pump Operation(~7.2V < VIN < ~10.1V)
In this operating region, the charge pump regulates slightly
below VIN/2 in order to remain in 2:1 mode and maximize
overall VIN to 3.3V conversion efficiency. Figure 4 shows
typical charge pump step-down mode and output voltage
as a function of VIN.

2:1
MODE

Figure 4. Typical Charge Pump Output Voltage and Mode vs VIN

If OUT5 is enabled and the charge pump output falls below
5V, OUT5 is disconnected from the charge pump output
and a separate internal VIN-powered 1:1 step-down mode
regulator is used to regulate 5V at the OUT5 pin. Referto the Simplified Block Diagram. The 3.3V LDO remains
powered by the 2:1 charge pump output.
Overall efficiency and power dissipation in this operating
region can be approximated by the equations below.
Total LTC3256 efficiency when ~7.2V < VIN < ~10.1V:
5V •IOUT5 + 3.3V •IOUT3η≅
I⎛⎞
VIN • ⎜ IOUT5 + OUT3 ⎟⎝2 ⎠Total LTC3256 power dissipation when ~7.2V < VIN < ~10.1V:⎛V⎞
PD ≅ ( VIN – 5V ) •IOUT5 + ⎜ IN – 3.3V ⎟ •IOUT3⎝ 2⎠

3256fa12

For more information www.linear.com/LTC3256

LTC3256
APPLICATIONS INFORMATION
1:1 Step-Down Charge Pump Operation (VIN < ~7.2V)

Flying Capacitor Selection

At the low end of the VIN operating range, the minimum
charge pump regulation point is typically VOUTCP = 3.6V,
with the charge pump automatically switching to 1:1 mode
as needed to maintain regulation. Under 1:1 mode conditions, both the 5V and 3.3V outputs are powered directlyfrom VIN with no improvement in efficiency over a dual
LDO solution. The overall efficiency and power dissipation in 1:1 step-down mode can be approximated by theequations below.

The flying capacitor should always be a ceramic type.
Polarized capacitors such as tantalum or aluminumelectrolytics are not recommended. The flying capacitor
controls the strength of the charge pump. In order toachieve the rated output current, it is necessary for the
flying capacitor to have at least 0.4μF of capacitance over
operating temperature at 5.05V (see Ceramic Capacitor
Selection Guidelines). The voltage rating of the ceramic
capacitor should be 6V or greater.

Total LTC3256 efficiency when VIN < ~7.2V:

Ceramic Capacitor Selection Guidelinesη≅

5V •IOUT5 + 3.3V •IOUT3
VIN • (IOUT5 +IOUT3 )Total LTC3256 power dissipation when VIN < ~7.2V:
PD ≅ ( VIN – 5V ) •IOUT5 + ( VIN – 3.3V ) •IOUT3Referring to Figure 2, in 1:1 mode, charge pump switches C
and D remain off, and switches A and B are pulsed on andoff together to transfer charge directly from VIN to OUTCP.
VIN Bypass Capacitor Selection
The total amount and type of capacitance necessary for
input bypassing is very dependent on the impedance of the
input power source as well as existing bypassing already on
the VIN node. For optimal input noise and ripple reduction,
it is recommended that a low ESR ceramic capacitor beused for VIN bypassing. Low ESR will reduce the voltage
steps caused by changing input current, while the absolute
capacitor value will determine the level of ripple. An electrolytic or tantalum capacitor may be used in parallel with theceramic capacitor on VIN to increase the total capacitance,
but due to the higher ESR, it is not recommended that anelectrolytic or tantalum capacitor be used alone for input
bypassing. The LTC3256 will operate with capacitors lessthan 10μF, but depending on the source impedance, input
noise can feed through to the output causing degraded
performance. For best performance, 10μF or greater total
capacitance is suggested for VIN bypassing.

Capacitors of different materials lose their capacitancewith higher temperature and voltage at different rates.
For example, a ceramic capacitor made of X5R or X7R
material will retain most of its capacitance from –40°C
to 85°C, whereas a Z5U or Y5V style capacitor will lose
considerable capacitance over that range (60% to 80%
loss typical). Z5U and Y5V capacitors may also have avery strong voltage coefficient, causing them to lose anadditional 60% or more of their capacitance when the rated
voltage is applied. Therefore, when comparing different
capacitors, it is often more appropriate to compare theamount of achievable capacitance for a given case size
rather than discussing the specified capacitance value. For
example, over rated voltage and temperature conditions,a 4.7μF, 10V, Y5V ceramic capacitor in an 0805 case may
not provide any more capacitance than a 1μF, 10V, X5R
or X7R available in the same 0805 case. In fact, over bias
and temperature range, the 1μF, 10V, X5R or X7R will
provide more capacitance than the 4.7μF, 10V, Y5V. The
capacitor manufacturer’s data sheet should be consulted
to determine what value of capacitor is needed to ensure
minimum capacitance values are met over operating
temperature and bias voltage. Table 1 is a list of ceramic
capacitor manufacturers in alphabetical order:

3256faFor more information www.linear.com/LTC3256

13

LTC3256
APPLICATIONS INFORMATIONCERAMIC CAPACITOR MANUFACTURERWEBSITE

AVX

www.avxcorp.com

Kemet

www.kemet.com

Muratawww.murata.com

Taiyo Yuden

www.t-yuden.com

TDK

www.tdk.com

Wurth Elektronik

www.we-online.com

3.3V LDO Operation (OUT3)
The 3.3V LDO post-regulates the charge pump output toproduce a lower noise output than is typically available fromswitching regulators, and supports a load of up to 250mA.
To ensure stability, the LDO output should be bypassed
to ground with at least a 10µF X7R ceramic capacitor.
Drive the EN3 pin high or low to turn the LDO on or off,
respectively. When turning on the LDO, the LTC3256
checks whether the charge pump output (OUTCP) is on,
enabling the charge pump automatically if needed.
3.3V LDO Fault Protection
The 3.3V LDO output is current limited to 350mA (typical)
to protect against overloads and short circuits. In addition,
to reduce power dissipation during an output fault condition, foldback circuitry reduces the LDO current limit to116mA (typical) for VOUT3 < 0.9V (typical).
To avoid startup issues due to the foldback feature, it isrecommended that heavy loads on OUT3 be held off during
LDO startup until the PG3 pin goes Hi-Z to indicate that
the LDO has completed power up.
5V Output Operation (OUT5)
Bringing EN5 high enables the 5V output at the OUT5
pin. When the 5V output is enabled, the LTC3256 checks
whether the charge pump output (OUTCP) is on, enabling
the charge pump automatically if needed.

As shown in the Block Diagram, two on-board regulators
can drive the 5V output: the 2:1 charge pump and the
VIN-powered gated-switch regulator. Regulator selection
is automatic. The LTC3256 prefers the 2:1 charge pumpwhenever possible due to its increased efficiency, buttransitions automatically to the VIN-powered gated-switch
regulator as needed to maintain regulation depending online and load conditions.
To reduce 5V output noise and ripple, it is suggested thata low ESR (equivalent series resistance < 0.1Ω) ceramic
capacitor (10μF or greater) be used for OUT5 bypass.
Tantalum or aluminum electrolytic capacitors can beused in parallel with a ceramic capacitor to increase thetotal capacitance but should not be used alone becauseof their high ESR.
5V Output from 2:1 Charge Pump via Fault-Protected
PMOS Switch
If at least 5V (typical) is present at OUTCP when EN5 isbrought high, the LTC3256 connects OUT5 to OUTCP
via an internal PMOS power switch. Soft-start circuitry
controls the PMOS turn-on rate to limit in-rush current
draw from OUTCP. VOUT5 slews from zero to its final value
over roughly 1.5ms. See Figure 5.
OUT5 Startup Into No Load
5.5
5.0
4.5
OUT5 VOLTAGE (V)

Table 1

4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0

0

0.5

1

1.5 2 2.5
TIME (ms)

3

3.5

4

3256 G05

Figure 5. OUT5 Startup

3256fa14

For more information www.linear.com/LTC3256

LTC3256
APPLICATIONS INFORMATIONThe LTC3256 has current limit circuitry to protect against
overcurrent faults beyond hard shorts to ground.
Reset Generation (RSTI input, RST output)
The LTC3256 pulls the RST open-drain output low whenever RSTI is below threshold (typically 1.2V) or OUTCP
is not in regulation. RST remains asserted low for a reset
timeout period (tRST) once RSTI goes above the threshold
and OUTCP is in regulation. Requiring that OUTCP is inregulation ensures that at least one of the outputs (OUT5or OUT3) is enabled before the reset timeout period starts.
RST deasserts by going high impedance at the end of thereset timeout period.
The reset timeout can be configured to use an internal
timer without external components, or an adjustable timer
programmed by connecting an external capacitor fromthe RT pin to GND. Glitch filtering ensures reliable reset
operation without false triggering.
During initial power up, the RST output asserts low while
VIN is below the VIN undervoltage lockout threshold. The
state of OUTCP and RSTI have no effect on RST while
VIN is below the undervoltage lockout threshold. The
reset timeout period cannot start until VIN exceeds theundervoltage lockout threshold.
Selecting the Reset Timing Capacitor
The reset timeout period can be set to a fixed internal
timer or programmed with a capacitor in order to accommodate a variety of applications. Connecting a capacitor,
CRT, between the RT pin and GND sets the reset timeout
period, tRST. The following formula approximates the valueof capacitor needed for a particular timeout:
CRT = ( tRST −0.75ms) •For example, using a standard capacitor value of 2.2nF
would give a 32ms reset timeout period.
Figure 6 shows the desired reset timeout period as a function of the value of the timer capacitor. Leaving RT openwith no external capacitor generates a reset timeout ofapproximately 0.75ms. Shorting RT to OUTCP generates
a reset timeout of approximately 0.2s.
50k
RESET TIMEOUT PERIOD, TRST(EXT) (ms)Upon a hard short circuit to ground, OUT5’s foldback circuitry limits current to 85mA (typical). This limit remains
in effect for VOUT5 < 0.8V (typical). To avoid startup issues
due to this foldback feature, heavy loads on OUT5 shouldbe held off during OUT5 startup until PG5 goes Hi-Z.

10k
1k
100
10
1
0.1
0.001

0.01
0.1
1
10
100
RT PIN CAPACITANCE, CRT (nF)

1k
3256 F06

Figure 6. Reset Timeout Period vs RT Pin Capacitance

RST Output Characteristics
RST is an open-drain pin and thus requires an external
pull-up resistor to the logic supply. RST is typically pulled
up to OUT5, OUT3, or OUTCP, but can be pulled up to any
other supply voltage providing the voltage limits of thepin are observed.
Watchdog Timer (WDI input, RST output)
The LTC3256 includes a windowed watchdog functionthat can continuously monitor the application’s logic or
microprocessor and issue automatic resets to aid recovery
from unintended lockups or crashes. With the RSTI input
held above threshold, the application must periodicallytoggle the logic state of the watchdog input (WDI pin) inorder to clear the watchdog timer. Specifically, successive

67pF
ms

3256faFor more information www.linear.com/LTC3256

15

LTC3256
APPLICATIONS INFORMATION
falling edges on the WDI pin must be spaced by more than
the watchdog lower boundary but less than the watchdog
upper boundary. As long as this condition holds, RST
remains high impedance.
If a falling edge arrives before the watchdog lower boundary, or if the watchdog timer reaches the upper boundary
without seeing a falling edge on WDI, the watchdog timer
enters its reset state and asserts RST low for the reset
timeout period. Once the reset timeout completes, RST isreleased to go high and the watchdog timer starts again.
During power-up, the watchdog timer remains cleared while
RST is asserted low. As soon as the reset timer times out,
RST goes high and the watchdog timer is started.
Setting the Watchdog Reset Time
The watchdog upper boundary (tWDU) and lower boundary (tWDL) are not observable outside the part, only thewatchdog reset time (tWDR) of the part is observable via
the RST pin. The watchdog upper boundary (tWDU) occurs
one watchdog clock cycle before the watchdog reset time(tWDR). The internal watchdog reset time consists of 8193
clock cycles, so the internal watchdog upper boundarytime is essentially the same as the internal watchdog resettime. Conversely the external watchdog reset time consistsof only 129 clock cycles, so the external watchdog upperboundary should be more accurately calculated as:⎛ 128 ⎞t WDU(EXT) = t WDR(EXT) • ⎜⎟⎝ 129 ⎠The external watchdog lower boundary (tWDL(EXT)) occurs
five clock cycles into the watchdog reset time (tWDR(EXT)).
Thus the external watchdog lower boundary can be calculated from the external watchdog reset time as:⎛ 5 ⎞t WDU(EXT) = t WDR(EXT) • ⎜⎟⎝ 129 ⎠The internal watchdog lower boundary can be calculated
from the internal watchdog reset time by the following:t WDL(INT) =t WDR(INT)32
The watchdog reset time is adjustable and can be optimized for software execution. The watchdog reset timeis adjusted by connecting a capacitor, CWT, between the
WT and GND pins. Given a desired watchdog reset time
tWDR, the capacitor value is approximately:
8.8nFs
For example, using a standard capacitor value of 0.047μF
would give a 5.3s watchdog reset time. Shorting WT to
BIAS generates a timeout of approximately 1.6s. Connecting WT to GND disables the watchdog function.
C WT = ( t WDR −3.8ms) •Power Good Output Operation (PG3, PG5 Outputs)
A built-in dual supply monitor indicates which of the
OUT3 and OUT5 voltages are in regulation. The monitor
detects both overvoltage and undervoltage faults, reporting Power Good status via the PG3 and PG5 open-drain
outputs. These will be referred to as the PGx pins in thedescription below.
If the LTC3256 is shut down (EN3 and EN5 both low) orin undervoltage lockout, both PGx pins are pulled low.
Otherwise, behavior is as follows:
If the OUTx pin voltage is greater than the overvoltage
threshold or less than the undervoltage threshold, thecorresponding PGx pin will pull low. PGx becomes highimpedance when the OUTx pin voltage is between theovervoltage and undervoltage thresholds. Hysteresis isbuilt into the overvoltage and undervoltage comparators
to ensure PGx holds it's state when in regulation.

3256fa16

For more information www.linear.com/LTC3256

LTC3256
APPLICATIONS INFORMATIONA pull-up resistor can be inserted between PGx and a valid
logic supply (i.e. OUTCP, OUT5 or OUT3) to signal a power
good condition. The use of a large value pull-up resistor
on PGx and a capacitor placed between PGx and GND canbe used to delay the Power Good signal if desired.
1.1V Reference Output (REFOUT Output)
An internal bandgap voltage reference determines theregulation voltages at OUT3 and OUT5. A buffered version of this voltage reference appears at the REFOUT pin
when the LTC3256 is enabled. The output has a typical
impedance of 2k and can source but not sink current. To
maximize supply rejection, REFOUT should be bypassedwith a 0.1µF ceramic capacitor.
Thermal Management/Thermal Shutdown

ambient impedance well in excess of 40°C/W. See Linear
Technology's Application Notes for thermally Enhanced
Leaded packages.
Because of the wide input operating range it is possible toexceed the specified operating junction temperature andeven reach thermal shutdown (175°C typ).
The LTC3256 can operate up to 95°C at full load (IOUT3 =250mA, IOUT5 = 100mA) with VIN < 15V. Above 95°C, orwith input voltages greater than 15V, it is the responsibility of the user to calculate worst-case power dissipation
to make sure the LTC3256’s specified operating junction
temperature is not exceeded for extended periods of time.
Refer to the power dissipation equations provided earlier
for calculating power dissipation (PD) in the different
modes of operation.

The on chip power dissipation in the LTC3256 will cause thejunction to ambient temperature to rise at rate of 40°C/W
or more. To reduce the maximum junction temperature, agood thermal connection to the PC board is recommended.

For example, if it is determined that the maximum power
dissipation (PD) is 1.2W under normal operation, then thejunction to ambient temperature rise will be:

Connecting the die paddle (Pin 17) with multiple vias to alarge ground plane under the device can reduce the thermal
resistance of the package and PC board considerably. Poorboard layout and failure to connect the die paddle (Pin 17)
to a large ground plane can result in thermal junction toThus, the ambient temperature under this condition cannot
exceed 102°C if the junction temperature is to remain below
150°C and if the ambient temperature exceeds about 127°C
the device will cycle in and out of the thermal shutdown.

Junction to Ambient = 1.2W • 40°C/W = 48°C

3256faFor more information www.linear.com/LTC3256

17

LTC3256
PACKAGE DESCRIPTION

Please refer to http://www.linear.com/product/LTC3256#packaging for the most recent package drawings.
MSE Package
16-Lead Plastic MSOP, Exposed Die Pad(Reference LTC DWG # 05-08-1667 Rev F)

BOTTOM VIEW OFEXPOSED PAD OPTION
2.845 ±0.102(.112 ±.004)

5.10(.201)
MIN

2.845 ±0.102(.112 ±.004)

0.889 ±0.127(.035 ±.005)

81

1.651 ±0.102(.065 ±.004)

1.651 ±0.102 3.20 – 3.45(.065 ±.004) (.126 – .136)

0.305 ±0.038(.0120 ±.0015)
TYP

16

0.50
(.0197)BSC

4.039 ±0.102(.159 ±.004)(NOTE 3)

RECOMMENDED SOLDER PAD LAYOUT

0.254(.010)

0.35
REF

0.12 REF

DETAIL “B”
CORNER TAIL IS PART OF
DETAIL “B” THE LEADFRAME FEATURE.
FOR REFERENCE ONLY
9NO MEASUREMENT PURPOSE

16151413121110 90.280 ±0.076(.011 ±.003)
REF

DETAIL “A”
0° – 6° TYP

3.00 ±0.102(.118 ±.004)(NOTE 4)4.90 ±0.152(.193 ±.006)

GAUGE PLANE

0.53 ±0.152(.021 ±.006)
DETAIL “A”

1.10(.043)
MAX

0.18(.007)SEATING
PLANE

0.17 – 0.27(.007 – .011)
TYP

1234567 8

0.50(.0197)BSC

0.86(.034)
REF

0.1016 ±0.0508(.004 ±.002)

MSOP (MSE16) 0213 REV F
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD SHALLNOT EXCEED 0.254mm (.010") PER SIDE.

3256fa18

For more information www.linear.com/LTC3256

LTC3256
REVISION HISTORY
REV

DATE

DESCRIPTION

A

08/16

Updated feature list

PAGE NUMBER
13256faInformation furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnectionof its circuits
as describedherein will not infringe on existing patent rights.
For more
informationwww.linear.com/LTC3256

19

LTC3256
TYPICAL APPLICATION
Dual Power Supply with Sequenced Startup (3.3V, Then 5V)

10µF

1µF
C+
5.5V TO 38VINPUT SUPPLY

C–

VIN

OUTCP
OUT5
10µF

LTC3256

OUT3
1M

10µF

5V OUTPUT
100mA MAX

3.3V LDO OUTPUT
250mA MAX

PG3
EN5
10µF

EN3
RT
WT
0.01µF

6.8nF

GND

RST
RSTI
WDI
REFOUT
PG5

MICROCONTROLLER
INTERFACERELATED PARTS
PART NUMBER

DESCRIPTIONCOMMENTS

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Switched-Capacitor Wide Input Range Voltage Converter with
Shutdown

Wide Input Voltage Range: 2V to 18V, ISD < 8µA,
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LTC1514/LTC1515

Step-Up/Step-Down Switched Capacitor DC/DC Converters

VIN: 2V to 10V, VOUT: 3.3V to 5V, IQ = 60µA, SO8 Package

LTC1911250mA, 1.5MHz Inductorless Step-Down DC/DC Converter

VIN: 2.7V to 5.5V, VOUT = 1.5V/1.8V, IQ = 180µA,
MS8 Package

LTC3250/LTC3250-1.2 Inductorless Step-Down DC/DC Converter
LTC3250-1.5

VIN: 3.1V to 5.5V, VOUT = 1.2V, 1.5V, IQ = 35µA,
ThinSOT™ Package

LTC3251

500mA Spread Spectrum Inductorless Step-Down DC/DC Converter

VIN: 2.7V to 5.5V, VOUT: 0.9V to 1.6V, 1.2V, 1.5V,
IQ = 9µA, MS10E Package

LTC3252

Dual 250mA, Spread Spectrum Inductorless Step-Down DC/DC
Converter

VIN: 2.7V to 5.5V, VOUT: 0.9V to 1.6V, IQ = 50µA,
DFN12 Package

LT®1054/LT1054L

Switched Capacitor Voltage Converter with Regulator

VIN: 3.5V to 15V/7V, IOUT = 100mA/125mA, N8, S08,
SO16 Packages

LTC3200/LTC3200-5

Low Noise Doubler Charge Pump

IOUT = 100mA, 2MHz Fixed Frequency, MS8 and ThinSOT(LTC3200-5) Packages

LTC3245

Wide VIN Range, Low Noise, 250mA Buck-Boost Charge Pump

2.7V to 38V VIN Range, IQ = 18µA Operating, 4µA in
Shutdown, Multimode Operation (2:1, 1:1, 1:2) with
Automatic Mode Switching, 12V to 5V Efficiency = 81%,
Low Noise, Constant Frequency Operation

LTC3255

Wide VIN Range, Fault Protected 50mA Charge Pump

Input Voltage Range: 4V to 48V, Adjustable Regulated
Output: 2.4V to 12.5V, Output Current: 50mA Maximum,
16µA Quiescent Current in Regulation at No Load, Input
Fault Protection from –52V to 60V

LTC3260

Low Noise Dual Supply Inverting Charge Pump

VIN: 4.5V to 32V, ILDO± = 50mA, DE14, MSE16 Packages

LTC3261High Voltage, Low Quiescent Current Inverting Charge Pump

VIN: 4.5V to 32V, IOUT = 100mA, MSE12 Package

LTC3265

Low Noise Dual Supply with Boost and Inverting Charge Pumps

Boost Charge Pump Generates 2-VIN_P (VIN_P Range:
4.5V to 16V) Inverting Charge Pump Generates –VIN_N(VIN_N Range: 4.5V to 32V)
3256fa20 Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417
For more information www.linear.com/LTC3256(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC3256

LT 0816 REV A • PRINTED IN USA

 LINEAR TECHNOLOGY CORPORATION 2016