INA231
SBOS644D – FEBRUARY 2013 – REVISED JULY 2022

INA231 28-V, 16-Bit, I2C Output Current, Voltage and Power Monitor With Alert in
WCSP Package
1 Features

3 Description

•
•
•
•

The INA231 is a current-shunt and power monitor
with a 1.8-V compliant I2C interface that features 16
programmable addresses. The INA231 monitors bothshunt voltage drops and bus supply voltage, providing
increased protection by asserting the ALERT pin
if the values are outside the programmed range.
Programmable calibration value, conversion time,and averaging, combined with an internal multiplier,enable direct readouts of current in amperes andpower in watts, thus reducing host processing.

•
•
•
•
•

Bus voltage sensing from 0 V to 28 V
High- or low-side sensing
Current, voltage, and power reporting
High accuracy:– Gain error: 0.5% (maximum)– Offset: 50 μV (maximum)
Configurable averaging options
Programmable alert threshold
1.8-V I2C compliant
Power-supply operation: 2.7 V to 5.5 V
Start-up mode options:– INA231A: active conversion– INA231B: low-current power down

The INA231 senses current on bus voltages that varyfrom 0 V to 28 V, with the device powered from asingle 2.7-V to 5.5-V supply, drawing 330 μA (typical)of supply current. The INA231 is specified over theoperating temperature range of –40°C to +125°C.

2 Applications
•
•
•
•
•
•
•
•

Smartphones
Tablets
Servers
Computers
Power management
Battery chargers
Power supplies
Test equipment

The INA231 is available in two versions: the INA231A
starts up performing continuous conversions of theshunt and bus voltage, whereas the INA231B starts
up in low-current, power-down mode.
Packaging Information(1)PART NUMBER

PACKAGEBODY SIZE (NOM)

YFF (DSBGA-12)

1.65 mm × 1.39 mm
× 0.62 mm

YFD (DSBGA-12)

1.65 mm × 1.39 mm
× 0.40 mm

YFD (DSBGA-12)

1.65 mm × 1.39 mm
× 0.40 mm

INA231A

INA231B(1)

For all available packages, see the package option
addendum at the end of the datasheet.

Power Supply(0 V to 28 V)

HighSide
Shunt

CBYPASS
0.1 mF

VS(Supply Voltage)

BUS
INA231

SDA
SCL

´

Load

Power RegisterV

2

Current Register
ADC

LowSideShunt

I

Voltage Register

IC
Interface
ALERT
A0

Alert Register

A1

GND

High-or Low-Side Sensing

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison......................................................... 3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 4
7.1 Absolute Maximum Ratings........................................ 4
7.2 ESD Ratings............................................................... 4
7.3 Recommended Operating Conditions.........................4
7.4 Thermal Information....................................................4
7.5 Electrical Characteristics.............................................5
7.6 Timing Requirements: I2C Bus....................................6
7.7 Typical Characteristics................................................ 7
8 Detailed Description......................................................10
8.1 Overview................................................................... 10
8.2 Functional Block Diagram......................................... 10
8.3 Feature Description...................................................10

8.4 Device Functional Modes..........................................14
8.5 Programming............................................................ 15
8.6 Register Maps...........................................................22
9 Application and Implementation.................................. 28
9.1 Application Information............................................. 28
9.2 Typical Applications.................................................. 30
9.3 Power Supply Recommendations.............................31
9.4 Layout....................................................................... 31
10 Device and Documentation Support..........................33
10.1 Documentation Support.......................................... 33
10.2 Receiving Notification of Documentation Updates..33
10.3 Support Resources................................................. 33
10.4 Trademarks............................................................. 33
10.5 Electrostatic Discharge Caution..............................33
10.6 Glossary..................................................................33
11 Mechanical, Packaging, and Orderable
Information.................................................................... 33

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (March 2018) to Revision D (July 2022)
Page• Updated the numbering format for tables, figures, and cross-references throughout the document..................1• Added footnote to B2 and C2 pins......................................................................................................................3• Changed value from 40 ms to 40 µs in sentence: Full recovery from power-down mode requires 40 µs........ 10• Moved the Power Supply Recommendations and Layout sections to the Application and Implementation
section.............................................................................................................................................................. 31
Changes from Revision B (August 2017) to Revision C (March 2018)
Page• Added B version device and associated content ............................................................................................... 1
Changes from Revision A (June 2017) to Revision B (August 2017)Page• Changed NC pin description from "No internal connection" to "Do not connect, leave floating" ....................... 3• Changed SCL max value from VS + 0.3 V to 6 V in Absolute Maximum Ratings table...................................... 4• Added text to end of Layout Guidelines section clarifying no connection of NC pins....................................... 31
Changes from Revision * (February 2013) to Revision A (June 2017)
Page• Added Device Information, Recommended Operating Conditions, and ESD Ratings tables, and Detailed
Description , Application and Implementation, Power Supply Recommendations, Layout, Device andDocumentation Support , and Mechanical, Packaging, and Orderable Information sections.............................1• Added new WSCP-12 (YFD) package with 0.4-mm package height and associated content to data sheet......1• Added operating ambient temperature, TA to Absolute Maximum Ratings table................................................4• Added new note 1 to Timing Requirements: I2C Bus section ........................................................................... 6• Added test condition to Figure 2 ........................................................................................................................ 7

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5 Device Comparison
Table 5-1. Device Comparison
DEVICE
INA209DESCRIPTION
Current and power monitor with watchdog, peak-hold, and fast comparator functions

INA210, INA211, INA212, INA213, INA214,
Zerø-drift, low-cost, analog current shunt monitor series in small package
INA215
INA219Zerø-drift, bidirectional current power monitor with two-wire interface

INA226

High or Low-side, bidirectional current and power monitor with two-wire interface and programmable alert

6 Pin Configuration and Functions
1

2

3

A

SCL

SDA

ALERT

B

VS

NC

A0

C

GND

NC

A1

D

BUS

IN±

IN+

Not to scale

Figure 6-1. YFF and YFD Packages 12-Pin DSBGA Top View
Table 6-1. Pin Functions
PIN

(1)

TYPE

DESCRIPTION

NAME

NO.

A0

B3

Digital input

Address pin. Connect to GND, SCL, SDA, or VS. Table 8-2 shows pin settings and corresponding
addresses.

A1

C3

Digital input

Address pin. Connect to GND, SCL, SDA, or VS. Table 8-2 shows pin settings and corresponding
addresses.

ALERT

A3

Digital output

Multi-functional alert, open-drain output.

GND

C1

AnalogNC

B2, C2(1)

—

SCL

A1

Digital input

Serial bus clock line, open-drain input.

SDA

A2

Digital input/
outputSerial bus data line, open-drain input/output.

BUS

D1

Analog input

Bus voltage input.

IN–

D2

Analog input

Negative differential shunt voltage input. Connect to load side of shunt resistor.

IN+

D3

Analog input

Positive differential shunt voltage input. Connect to supply side of shunt resistor.

VS

B1

AnalogGroundDo not connect, leave floating.

Power supply pin, 2.7 V to 5.5 V.

Internally, B2 is connected to VS and C2 is connected to GND. Leave floating.

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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN

MAX

UNIT

6

V

Supply voltage, VS)(2)

Differential (VIN+) – (VIN–

–30

30

V

Common-mode

–0.3

30

V

SDA

GND – 0.3

6

V

SCL

GND – 0.3

6V

Input current into any pin

5mA

Open-drain digital output current

10

mA

125

°C

150

°C

150

°C

Analog inputs, IN+, IN–

Operating ambient temperature, TA–40

Junction temperature, TJ
Storage temperature, Tstg
(1)

(2)

–65

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stressratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated underRecommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
VIN+ and VIN– may have a differential voltage of –30 V to +30 V; however, the voltage at these pins must not exceed the range –0.3 V
to +30 V.

7.2 ESD Ratings
VALUE
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)V(ESD)

Electrostatic discharge Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2)1000

Machine model (MM)
(1)
(2)

UNIT

2500
V

150

JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions
MIN

NOM

MAX

UNIT

VCM

Common-mode voltage

0

28

V

VS

Operating supply voltage

2.7

5.5

V

TA

Operating ambient temperature

–40

125

°C

YFD (DSBGA)YFF (DSBGA)

UNIT

12 PINS

12 PINS

83.8

90.2

°C/W

7.4 Thermal Information
INA231
THERMAL METRIC(1)RθJA

Junction-to-ambient thermal resistanceRθJC(top)

Junction-to-case (top) thermal resistance

0.4

0.5

°C/W

RθJB

Junction-to-board thermal resistance

19.3

40.0

°C/W

ψJT

Junction-to-top characterization parameter

0.3

3.0

°C/W

ψJB

Junction-to-board characterization parameter

19.4

39.2

°C/W

RθJC(bot)

Junction-to-case (bottom) thermal resistance

N/A

N/A

°C/W

(1)

For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

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7.5 Electrical Characteristics
at TA = 25°C, VS = 3.3 V, VIN+ = 12 V, VSENSE = (VIN+ – VIN–) = 0 mV, and VBUS = 12 V (unless otherwise noted)
PARAMETERTEST CONDITIONS

MIN

TYP

MAX

UNIT

81.9175mV

SHUNT INPUT
Shunt voltage input
CMR

Common-mode rejection

VOS

Shunt offset voltage, RTI(1)PSRRvs power supply–81.92
VIN+ = 0 V to 28 V

100

120

dB

±10

±50

μV

TA = –40°C to +125°C

0.1

0.5

μV/°C

VS = 2.7 V to 5.5 V

10

μV/V

BUS INPUT
Bus voltage input range(2)VOSBus offset voltage, RTI(1)PSRRvs power supply

0

TA = –40°C to +125°C

BUS pin input impedance

28

V

±5

±30

mV

10

40

μV/°C

2

mV/V

830

kΩ

INPUT
IIN+, IIN-

Input bias current
Input leakage(3)10μA(VIN+) + (VIN–), Power-Down mode

0.1

0.5

μA

Shunt voltage

2.5

μV

Bus voltage

1.25

mV

DC ACCURACY
ADC native resolution
1 LSB step size

Shunt voltage gain error

Bus voltage gain error

16

0.2%
TA = –40°C to +125°C
TA = –40°C to +125°C

Differential nonlinearity

ADC conversion time

Bits

0.5%

10

50

0.2%

0.5%

10

50

±0.1

ppm/°Cppm/°CLSB

CT bit = 000

140

154

μs

CT bit = 001

204

224

μs

CT bit = 010

332

365

μs

CT bit = 011

588

646

μs

CT bit = 100

1.1

1.21

ms

CT bit = 101

2.116

2.328

ms

CT bit = 110

4.156

4.572

ms

CT bit = 111

8.244

9.068

ms

28

35

ms

2

μA

SMBus
SMBus timeout(4)DIGITAL INPUT/OUTPUT
Input capacitance
Leakage input current

30 ≤ VIN ≤ VS

0.5

pF

VIH

High-level input voltage

1.4

6

V

VIL

Low-level input voltage

–0.5

0.4

V

VOL

Low-level output voltage (SDA, ALERT)

0

0.4

V

IOL = 3 mA

Hysteresis

500

mV

POWER SUPPLY
Quiescent current

Power-Down mode

Power-on reset threshold

(1)
(2)

330

420

μA

3

7

μA

2

V

RTI = Referred-to-input.
Although the input range is 28 V, the full-scale range of the ADC scaling is 40.96 V. Do not apply more than 28 V. See the Basic
Analog-to-Digital Converter (ADC) Functions section for more details

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(3)
(4)

Input leakage is positive (current flowing into the pin) for the conditions shown at the top of this table. Negative leakage currents canoccur under different input conditions.
SMBus timeout in the INA231 resets the interface any time SCL is low for more than 28 ms.

7.6 Timing Requirements: I2C Bus
see (1)
FAST MODE
MIN

TYP

MAX

MIN

TYP

MAX

UNIT

INA231A

0.001

0.4

0.001

2.5

INA231B

0.01

0.4

0.01

2.5

Bus free time between stop and start
conditions

600

260

ns

Hold time after repeated START condition.
t(HDSTA) After this period, the first clock isgenerated.

100

100

ns

t(SUSTA) Repeated start condition setup time

100

100

ns

t(SUSTO) STOP condition setup time

100

100

ns

f(SCL) SCL operating frequencyt(BUF)

MHzt(HDDAT) Data hold time, VS ≤ 3.3 V

0

0

130

ns

t(HDDAT) Data hold time, VS > 3.3 V

10

10

130

ns

t(SUDAT) Data setup time

(1)

HIGH-SPEED MODE

100

50

ns

t(LOW) SCL clock low period

1300

260

ns

t(HIGH) SCL clock high period

600

60

ns

tF Data fall time

300

80

ns

tR Data rise time

300

80

ns

tF Clock fall time

300

40

ns

tR Clock rise time

300

40

ns

tR Clock/data rise time for SCLK ≤ 100 kHz

1000

ns

Values based on a statistical analysis of a one-time sample of devices. Minimum and maximum values are specified by design, but not
production tested.
t(LOW)tF

tR

t(HDSTA)SCLt(HDSTA)t(HIGH)t(HDDAT)t(SUSTO)t(SUSTA)t(SUDAT)SDAt(BUF)PSS

P

Figure 7-1. Bus Timing Diagram

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7.7 Typical Characteristics
at TA = 25°C, VS = 3.3 V,VIN+ = 12 V, VSENSE = (VIN+ – VIN–) = 0 mV, and VBUS = 12 V (unless otherwise noted)
0−10Population

Gain (dB)

−20
−30
−40
−50

1

10

100
1k
Frequency (Hz)

10k

100k

−50
−45
−40
−35
−30
−25
−20
−15
−10
−5
0
5
10
15
20
25
30
35
40
45
50

−60

G001

Conversion time = 1.1 ms

Input Offset Voltage (µV)

G002

Figure 7-3. Shunt Input Offset Voltage Production Distribution

Figure 7-2. Frequency Response

170
Common-Mode Rejection Ratio (dB)

10

Offset (µV)

0

−10

−20
−50

−25

0

25
50
Temperature (°C)

75

100

160

150

140
−50

125

−25

0

25
50
Temperature (°C)

G003

Figure 7-4. Shunt Input Offset Voltage vs Temperature

75

100

125
G004

Figure 7-5. Shunt Input Common-Mode Rejection Ratio vsTemperature
500

Population

Gain Error (m%)

400

300

200

Shunt Gain Error (m%)

0
−50

500

400

300

200

100

0

−100

−200

−300

−400

−500

100

G005

Figure 7-6. Shunt Input Gain Error Production Distribution

−25

0

25
50
Temperature (°C)

75

100

125
G006

Figure 7-7. Shunt Input Gain Error vs Temperature

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7.7 Typical Characteristics (continued)
at TA = 25°C, VS = 3.3 V,VIN+ = 12 V, VSENSE = (VIN+ – VIN–) = 0 mV, and VBUS = 12 V (unless otherwise noted)
300
250

Population

Gain Error (m%)

200
150
100
50

G007

Figure 7-8. Shunt Input Gain Error vs Common-Mode Voltage

30

25

27.5

20

22.5

15

17.5

10

12.5

5

7.5

36

0

32

2.5

8
12
16
20
24
28
Common−Mode Input Voltage (V)

−2.5

4

−5

0

−5

−50

−15

0

Input Offset Voltage (mV)G008

Figure 7-9. Bus Input Offset Voltage Production Distribution−0.6

Population

Offset (mV)

−0.8

−1

G009

500

25

400

20

300

200

100

0
−50

−25

0

25
50
Temperature (°C)

75

100

400

300

500
G010

125

15

10

5

0

0

G011

Figure 7-12. Bus Input Gain Error vs Temperature

8

Input Gain Error (m%)

Figure 7-11. Bus Input Gain Error Production Distribution

Input Bias Current (µA)

Gain Error (m%)

Figure 7-10. Bus Input Offset Voltage vs Temperature

200

125

100

100

0

75

−100

25
50
Temperature (°C)

−200

0

−300

−25

−400

−1.4
−50

−500

−1.2

4

8
12
16
20
24
28
Common-Mode Input Voltage (V)

32

36
G012

Figure 7-13. Input Bias Current vs Common-Mode Voltage

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7.7 Typical Characteristics (continued)
at TA = 25°C, VS = 3.3 V,VIN+ = 12 V, VSENSE = (VIN+ – VIN–) = 0 mV, and VBUS = 12 V (unless otherwise noted)
260
Input Bias Current − Shutdown (nA)

Input Bias Current (µA)

24

22

20

18

16
−50

−25

0

25
50
Temperature (°C)

75

100

140
100
60

−25

0

G013

25
50
Temperature (°C)

75

100

125
G014

Figure 7-15. Input Bias Current vs Temperature, Shutdown
2.6
Quiescent Current − Shutdown (µA)

500

Quiescent Current (µA)

180

20
−50

125

Figure 7-14. Input Bias Current vs Temperature

400

300

200

100
−50

220

−25

0

25
50
Temperature (°C)

75

100

2.4

2.2

2

1.8

1.6
−50

125

−25

0

G015

Figure 7-16. Active IQ vs Temperature

25
50
Temperature (°C)

75

100

125
G016

Figure 7-17. Shutdown IQ vs Temperature

500

300
250

Shutdown IQ (mA)

IQ (mA)

450

400

200
150
100

350
50
300

0
1

10

100

1,000

10,0001Frequency (kHz)

10

100

1,000

10,000Frequency (kHz)

Figure 7-18. Active IQ vs I2C Clock Frequency

Figure 7-19. Shutdown IQ vs I2C Clock Frequency

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8 Detailed Description
8.1 Overview
The INA231 is a digital, current-sense amplifier with an I2C- and SMBus-compatible interface. It provides digitalcurrent, voltage, and power readings necessary for accurate decision-making in precisely controlled systems.
Programmable registers allow flexible configuration for measurement resolution, as well as continuous-versustriggered operation. Detailed register information is shown in the Register Maps section. See the Functional
Block Diagram section for a block diagram of the INA231 device.

8.2 Functional Block Diagram
Power

(1)

Bus Voltage(1)´
Shunt Voltage
ChannelCurrent(1)

ADC

Bus Voltage
ChannelCalibration(2)´
Shunt Voltage(1)

Data Registers

A.
B.

Read-only
Read/write

Figure 8-1. Functional Block Diagram

8.3 Feature Description
8.3.1 Basic Analog-to-Digital Converter (ADC) Functions
The INA231 performs two measurements on the power-supply bus of interest. The voltage developed from theload current that flows through a shunt resistor creates the shunt voltage signal that is measured at the IN+ and
IN– pins. The device can also measure the power supply bus voltage by connecting this voltage to the BUS pin.
The differential shunt voltage is measured with respect to the IN– pin whereas the bus voltage is measured withrespect to ground.
The INA231 is typically powered by a separate supply that can range from 2.7 V to 5.5 V. The bus that is being
monitored can range in voltage from 0 V to 28 V.
Note
Based on the fixed 1.25 mV LSB for the bus voltage register, a full-scale register would result in a
40.96-V value. However, the actual voltage that is applied to the input pins of the INA231 should notexceed 28 V.
There are no special considerations for power-supply sequencing because the common-mode input range andpower-supply voltage are independent of each other; therefore, the bus voltage can be present with the supply
voltage off, and vice-versa.
As noted, the INA231 takes two measurements, shunt voltage and bus voltage. It then converts thesemeasurements to current, based on the Calibration register value, and then calculates power. See the Configure,Measure, and Calculate Example section for additional information on programming the calibration register.

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The INA231 has two operating modes, continuous and triggered, that determine how the ADC operates
after these conversions. When the INA231 is in the normal operating mode (that is, the MODE bits of theConfiguration register are set to '111'), it continuously converts a shunt voltage reading followed by a bus voltage
reading. After the shunt voltage reading, the current value is calculated based on Equation 3. This current
value is then used to calculate the power result using Equation 4. These values are subsequently stored inan accumulator, and the measurement and calculation sequence repeats until the number of averages set in
the Configuration register is reached. Note that the current and power calculations are based on the value
programmed into the Calibration register. If the Calibration register is not programmed, the result of the current
and power calculations is zero. Following every sequence, the present set of measured and calculated values
are appended to the previously collected values. After all of the averaging has been completed, the final values
for shunt voltage, bus voltage, current, and power are updated in the corresponding registers and can thenbe read. These values remain in the data output registers until they are replaced by the next fully completed
conversion results. Reading the data output registers does not affect a conversion in progress.
The mode control bits in the Configuration register also permit selecting specific modes to convert only the shunt
voltage or the bus voltage in order to further allow the monitoring function configuration to fit specific application
requirements.
All current and power calculations are performed in the background and do not contribute to conversion time.
In triggered mode, writing any of the triggered convert modes into the Configuration register (that is, the MODE
bits of the Configuration register are set to 001, 010, or 011) triggers a single-shot conversion. This action
produces a single set of measurements. To trigger another single-shot conversion, the Configuration registermust be written to again, even if the mode does not change.
In addition to the two operating modes (continuous and triggered), the INA231 also has a power-down mode that
reduces the quiescent current and turns off current into the INA231 inputs, which reduces the impact of supply
drain when the device is not being used. Full recovery from power-down mode requires 40 μs. The registers of
the INA231 can be written to and read from while the device is in power-down mode. The device remains in
power-down mode until one of the active modes settings are written into the Configuration register.
Although the INA231 can be read at any time, and the data from the last conversion remain available, theconversion ready flag bit (CVRF bit, Mask/Enable register) is provided to help coordinate single-shot or triggered
conversions. The CVRF bit is set after all conversions, averaging, and multiplication operations are complete fora single cycle.
The CVRF bit clears under these conditions:
1. Writing to the Configuration register, except when configuring the MODE bits for power-down mode; or
2. Reading the Status register.
8.3.1.1 Power Calculation
The current and power are calculated after shunt voltage and bus voltage measurements, as shown in Figure8-2. The current is calculated after a shunt voltage measurement based on the value set in the Calibration
register. If there is no value loaded into the Calibration register, the current value stored is zero. Power iscalculated following the bus voltage measurement based on the previous current calculation and bus voltage
measurement. If there is no value loaded in the Calibration register, the power value stored is also zero. These
calculations are performed in the background and do not add to the overall conversion time. These current
and power values are considered intermediate results (unless the averaging is set to 1) and are stored in aninternal accumulation register, not the corresponding output registers. Following every measured sample, thenewly-calculated values for current and power are appended to this accumulation register until all of the samples
have been measured and averaged based on the number of averages set in the Configuration register.

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Bus and Power Limit Detect
Following Every Bus Voltage Conversion

Current Limit Detect Following
Every Shunt Voltage Conversion

I

V

I
P

V

I
P

V

I

V

P

I
P

V

I
P

V

I
P

V

I
P

V

I
P

V

I

V

P

I
P

V

I
P

V

I
P

V

I
P

V

I
P

V

I
P

V
P

Power Average

Bus Voltage Average

Shunt Voltage Average

Figure 8-2. Power Calculation Scheme
In addition to the current and power accumulating after every sample, the shunt and bus voltage measurements
are also collected. After all of the samples have been measured and the corresponding current and power
calculations have been made, the accumulated average for each of these parameters is then loaded to thecorresponding output registers where they can then be read.
8.3.1.2 ALERT Pin
The INA231 has a single Alert Limit register (07h) that allows the ALERT pin to be programmed to respondto a single user-defined event or to a conversion ready notification if desired. The Mask/Enable register allows
for selection from one of the five available functions to monitor and set the conversion ready bit (CNVR, Mask/
Enable register) to control the response of the ALERT pin. Based on the function being monitored, a value would
then be entered into the Alert Limit register to set the corresponding threshold value that asserts the ALERT pin.
The ALERT pin allows for one of several available alert functions to be monitored to determine if a user-defined
threshold has been exceeded. The five alert functions that can be monitored are:• Shunt voltage overlimit (SOL)• Shunt voltage underlimit (SUL)• Bus voltage overlimit (BOL)• Bus voltage underlimit (BUL)• Power overlimit (POL)The ALERT pin is an open-drain output. This pin is asserted when the alert function selected in the Mask/Enableregister exceeds the value programmed into the Alert Limit register. Only one of these alert functions can be
enabled and monitored at a time. If multiple alert functions are enabled, the selected function in the highest
significant bit position takes priority and responds to the Alert Limit register value. For example, if the SOL andthe SUL are both selected, the ALERT pin asserts when the Shunt Voltage Over Limit register exceeds the value
in the Alert Limit register.
The conversion-ready state of the device can also be monitored at the ALERT pin to inform the user when thedevice has completed the previous conversion and is ready to begin a new conversion. The conversion readyflag (CVRF) bit can be monitored at the ALERT pin along with one of the alert functions. If an alert function
and the CNVR bit are both enabled for monitoring at the ALERT pin, then after the ALERT pin is asserted, theCVRF bit (D3) and the AFF bit (D4) in the Mask/Enable register must be read following the alert to determine thesource of the alert. If the conversion ready feature is not desired, and the CNVR bit is not set, the ALERT pin
only responds to an exceeded alert limit based on the alert function enabled.
If the alert function is not used, the ALERT pin can be left floating without impacting the operation of the device.
Refer to Figure 8-2 to see the relative timing of when the value in the Alert Limit register is compared to thecorresponding converted value. For example, if the alert function that is enabled is Shunt Voltage Over Limit(SOL), following every shunt voltage conversion the value in the Alert Limit register is compared to the measured
shunt voltage to determine if the measurements have exceeded the programmed limit. The AFF bit (D4, Mask/
Enable register) asserts high any time the measured voltage exceeds the value programmed into the Alert Limit
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register. In addition to the AFF bit being asserted, the ALERT pin is asserted based on the Alert Polarity bit(APOL, D1, Mask/Enable register). If the Alert Latch is enabled, the AFF bit and ALERT pin remain asserted until
either the Configuration register is written to or the Mask/Enable register is read.
The bus voltage alert functions (BOL and BUL, Mask/Enable register) compare the measured bus voltage to
the Alert Limit register following every bus voltage conversion and assert the AFF bit and ALERT pin if the limit
threshold is exceeded.
The power overlimit alert function (POL, Mask/Enable register) is also compared to the calculated power value
following every bus voltage measurement conversion and asserts the AFF bit and ALERT pin if the limit
threshold is exceeded.
The alert function compares the programmed alert limit value to the result of each corresponding conversion.
Therefore, an alert can be issued during a conversion cycle where the averaged value of the signal does notexceed the alert limit. Triggering an alert based on this intermediate conversion allows for out-of-range events
to be detected faster than the averaged output data registers are updated. This fast detection can be used tocreate alert limits for quickly changing conditions through the use of the alert function, as well as to create limits
to longer-duration conditions through software monitoring of the averaged output values.

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8.4 Device Functional Modes
8.4.1 Averaging and Conversion Time Considerations
The INA231 has programmable conversion times for both the shunt voltage and bus voltage measurements. The
conversion times for these measurements can be selected from as fast as 140 μs to as long as 8.244 ms. The
conversion time settings, along with the programmable averaging mode, allow the INA231 to be configured to
optimize the available timing requirements in a given application. For example, if a system requires that data
be read every 5 ms, the INA231 can be configured with the conversion times set to 588 μs and the averaging
mode set to 4. This configuration results in the data updating approximately every 4.7 ms. The INA231 can also
be configured with a different conversion time setting for the shunt and bus voltage measurements. This type ofapproach is common in applications where the bus voltage tends to be relatively stable. This situation allows forthe time spent measuring the bus voltage to be reduced relative to the shunt voltage measurement. The shunt
voltage conversion time can be set to 4.156 ms with the bus voltage conversion time set to 588 μs, and theaveraging mode set to 1. This configuration also results in data updating approximately every 4.7 ms.
There are trade-offs associated with the conversion time settings and the averaging mode used. The averaging
feature can significantly improve the measurement accuracy by effectively filtering the signal. This approachallows the INA231 to reduce noise in the measurement that may be caused by noise coupling into the signal.
A greater number of averages enables the INA231 to be more effective in reducing the noise component of themeasurement.
The conversion times selected can also have an impact on the measurement accuracy; this effect can be seenin Figure 8-3. Multiple conversion times are shown to illustrate the impact of noise on the measurement. In orderto achieve the highest accuracy measurement possible, use a combination of the longest allowable conversion
times and highest number of averages, based on the timing requirements of the system.

10mV/div

Conversion Time: 140ms

Conversion Time: 1.1ms

Conversion Time: 8.244ms

0

200

400

600

800

1000

Number of Conversions

Figure 8-3. Noise vs Conversion Time

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8.5 Programming
An important aspect of the INA231 is that it does not necessarily measure current or power. The INA231
measures both the differential voltage applied between the IN+ and IN– input pins and the voltage applied
to the BUS pin. In order for the INA231 to report both current and power values, both the Current register
resolution and the value of the shunt resistor present in the application that resulted in the differential voltage
being developed must be programmed. The Power register is internally set to be 25 times the programmed
least significant bit of the Current register (Current_LSB). Both the Current_LSB and shunt resistor value areused when calculating the Calibration register value. The INA231 uses this value to calculate the corresponding
current and power values based on the measured shunt and bus voltages.
The Calibration register is calculated based on Equation 1. This equation includes the term Current_LSB, theprogrammed value for the LSB for the Current register. This is the value used to convert the value in the Current
register to the actual current in amps. The highest resolution for the Current register can be obtained by using
the smallest allowable Current_LSB based on the maximum expected current, as shown in Equation 2. While
this value yields the highest resolution, it is common to select a value for the Current_LSB to the nearest roundnumber above this value to simplify the conversion of the Current register and Power register to amps andwatts, respectively. RSHUNT is the value of the external shunt used to develop the differential voltage across the
input pins. The 0.00512 value in Equation 1 is an internal fixed value used to make sure that scaling is properly
maintained.

0.00512CAL = Current_LSB · R

Current_LSB =

(1)

SHUNT

Maximum Expected Current
215

(2)

After the Calibration register has been programmed, the Current register and Power register are updated
accordingly based on the corresponding shunt voltage and bus voltage measurements. Until the Calibration
register is programmed, the Current and Power registers remain at zero.
8.5.1 Configure, Measure, and Calculate Example
In this example, shown in Figure 9-3, a nominal 10-A load creates a differential voltage of 20 mV across a 2-mΩshunt resistor. The bus voltage for the INA231 is measured at the external BUS input pin; in this example, BUS
is connected to the IN– pin to measure the voltage level delivered to the load. For this example, the BUS pin
measures less than 12 V because the voltage at the IN– pin is 11.98 V as a result of the voltage drop across theshunt resistor.
For this example, assuming a maximum expected current of 15 A, the Current_LSB is calculated to be 457.7
μA/bit using Equation 2. Using a value of 500 μA/bit or 1 mA/bit for the Current_LSB significantly simplifies theconversion from the Current register and Power register to amps and watts, respectively. For this example, avalue of 1 mA/bit was chosen for the Current register LSB. Using this value for the Current_LSB trades a small
amount of resolution for a simpler conversion process on the processor side. Using Equation 1 in this example
with a current LSB of 1 mA/bit and a shunt resistor of 2 mΩ results in a Calibration register value of 2560, or
A00h.
The Current register (04h) is then calculated by multiplying the decimal value of the Shunt Voltage register
contents by the decimal value of the Calibration register and then dividing by 2048, as shown in Equation 3. For
this example, the Shunt Voltage register value of 8000 is multiplied by the Calibration register value of 2560 andthen divided by 2048 to yield a decimal value for the Current register of 10000, or 2710h. Multiplying this valueby 1 mA/bit results in the original 10-A level stated in the example.
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Current =ShuntVoltage · CalibrationRegister
2048

(3)

The LSB for the Bus Voltage register (02h) is a fixed 1.25 mV/bit. This fixed value means that the 11.98 V
present at the BUS pin results in a register value of 2570h, or a decimal equivalent of 9584. Note that the MSBof the Bus Voltage register is always zero because the BUS pin is only able to measure positive voltages.
The Power register (03h) is then calculated by multiplying the decimal value of the Current register, 10000, by
the decimal value of the Bus Voltage register, 9584, and then dividing by 20,000, as defined in Equation 4. For
this example, the result for the Power register is 12B8h, or a decimal equivalent of 4792. Multiplying this result
by the power LSB (25 times the [1 × 10–3 Current_LSB]) results in a power calculation of (4792 × 25 mW/bit),or 119.8 W. The Power register LSB has a fixed ratio to the Current register LSB of 25 W/bit to 1 A/bit. For thisexample, a programmed Current register LSB of 1 mA/bit results in a Power register LSB of 25 mW/bit. This ratio
is internally programmed to make sure that the scaling of the power calculation is within an acceptable range. A
manual calculation for the power being delivered to the load would use a bus voltage of 11.98 V (12VCM – 20 mVshunt drop) multiplied by the load current of 10 A to give a result of 119.8 W.

Power =

Current · BusVoltage
20,000(4)

Table 8-1 shows the steps for configuring, measuring, and calculating the values for current and power for thisdevice.
Table 8-1. Configure, Measure. and Calculate Example(1)STEP #REGISTER NAME

ADDRESSCONTENTS

DEC

LSB

VALUE

Step 1

Configuration

00h

4127h

—

—

—

Step 2

Shunt

01h

1F40h

8000

2.5 µV

20m V

Step 3

Bus

02h

2570h

9584

1.25 mV

11.98 V

Step 4

Calibration

05h

A00h

2560

—

—

Step 5Current

04h

2710h

10000

1 mA

10 A

Step 6

Power

03h

12B8h

4792

25 mW

119.8 W

(1)

Conditions: Load = 10 A, VCM = 12 V, RSHUNT = 2 mΩ, and VBUS =11.98 V.

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8.5.2 Programming the Power Measurement Engine
8.5.2.1 Calibration Register and Scaling
The Calibration register makes it possible to set the scaling of the Current and Power registers to the values thatare most useful for a given application. One strategy may be to set the Calibration register so that the largest
possible number is generated in the Current register or Power register at the expected full-scale point. Thisapproach yields the highest resolution based on the previously-calculated minimum Current_LSB in the equation
for the Calibration register (Equation 1). The Calibration register can also be selected to provide values in the
Current and Power registers that either provide direct decimal equivalents of the values being measured, or
yield a round LSB value for each corresponding register. After these choices have been made, the Calibration
register also offers possibilities for end-user, system-level calibration. By physically measuring the current withan external ammeter, the exact current is known. The value of the Calibration register can then be adjusted
based on the measured current result of the INA231 to cancel the total system error, as shown in Equation 5.

Corrected_Full_Scale_Cal = trunc

Cal ´ MeasShuntCurrent
INA231_Current(5)8.5.3 Simple Current Shunt Monitor Usage (No Programming Necessary)
The INA231 does not require programming to read a shunt voltage drop and the bus voltage when using thedefault power-on reset configuration and running continuous conversions of the shunt and bus voltage.
Without programming the INA231 Calibration register, the device is unable to provide either a valid current or
power value because these outputs are both derived using the values loaded into the Calibration register.
8.5.4 Default INA231 Settings
The default power-up states of the registers are shown in the Register Details section of this data sheet. These
registers are volatile, and if programmed to a value other than the default values shown in Table 8-3, they must
be reprogrammed at every device power-up. Detailed information on programming the Calibration register isgiven in the Configure/Measure/Calculate Example section and calculated based on Equation 1.

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8.5.5 Writing to and Reading from the INA231
8.5.5.1 Bus Overview
The INA231 offers compatibility with both I2C and SMBus interfaces. The I2C and SMBus protocols are
essentially compatible with one another.
The I2C interface is used throughout this data sheet as the primary example, with SMBus protocol specified only
when a difference between the two systems is discussed. Two bidirectional lines, SCL and SDA, connect the
INA231 to the bus. Both SCL and SDA are open-drain connections.
The device that initiates a data transfer is called a master, and the devices controlled by the master are slaves.
The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access,and generates start and stop conditions.
To address a specific device, the master initiates a start condition by pulling the data signal line (SDA) from ahigh to a low logic level while SCL is high. All slaves on the bus shift in the slave address byte on the rising edgeof SCL, with the last bit indicating whether a read or write operation is intended. During the ninth clock pulse, theslave being addressed responds to the master by generating an Acknowledge bit (ACK) and pulling SDA low.
Data transfer is then initiated and eight bits of data are sent, followed by an ACK. During data transfer, SDA mustremain stable while SCL is high. Any change in SDA while SCL is high is interpreted as a start or stop condition.
After all data have been transferred, the master generates a stop condition indicated by pulling SDA from low tohigh while SCL is high. The INA231 includes a 28-ms timeout on its interface to prevent locking up the bus.
Accessing a specific register on the INA231 is accomplished by writing the appropriate value to the register
pointer. Refer to Table 8-3 for a complete list of registers and corresponding addresses. The value for theregister pointer (shown in Figure 8-7) is the first byte transferred after the slave address byte with the R/ W bit
low. Every write operation to the INA231 requires a value for the register pointer.
Writing to a register begins with the first byte transmitted by the master. This byte is the slave address, with the
R/ W bit low. The INA231 then acknowledges receipt of a valid address. The next byte transmitted by the masteris the address of the register that data are written to. This register address value updates the register pointer tothe desired register. The next two bytes are written to the register addressed by the register pointer. The INA231
acknowledges receipt of each data byte. The master may terminate data transfer by generating a start or stop
condition.
When reading from the INA231, the last value stored in the register pointer by a write operation determines
which register is read during a read operation. To change the register pointer for a read operation, a new value
must be written to the register pointer. This write is accomplished by issuing a slave address byte with the R/
W bit low, followed by the register pointer byte. No additional data are required. The master then generates
a start condition and sends the slave address byte with the R/ W bit high to initiate the read command. The
next byte is transmitted by the slave and is the most significant byte of the register indicated by the register
pointer. This byte is followed by an ACK from the master; then the slave transmits the least significant byte.
The master acknowledges receipt of the data byte. The master may terminate data transfer by generating a
Not-Acknowledge bit (No ACK) after receiving any data byte, or generating a start or stop condition. If repeatedreads from the same register are desired, it is not necessary to continually send the register pointer bytes; theINA231 retains the register pointer value until it is changed by the next write operation.
Figure 8-4 and Figure 8-5 show the write and read operation timing diagrams, respectively. Note that register
bytes are sent most-significant byte first, followed by the least significant byte.

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1

9

9

1

9

1

9

1

SCL

SDA

1

0

0

A3

A2

A1

A0

R/W

Start By
MasterFrame 1 Two-Wire Slave Address Byte

A.

P7

P6

P5

P4

P3

P2

P1

ACK ByTI-Device

D15 D14P0

D13

D12 D11 D10

D9

D8

(1)

D7

D6

D5

D4

D3

D2

D1

D0

ACK ByTI-Device

ACK ByTI-Device
Frame 2 Register Pointer Byte

ACK ByTI-Device

Frame 3 Data MSByte

Stop By
MasterFrame 4 Data LSByte

The value of the slave address byte is determined by the settings of the A0 and A1 pins. Refer to Table 8-2.

Figure 8-4. Timing Diagram for Write Word Format
1

9

1

1

9

9

SCL

SDA

0

1

0

A3

A2

A1

A0

R/W

Start By
MasterFrame 1 Two-Wire Slave Address Byte

A.
B.
C.

D15 D14D13

D12

D11 D10

D9(1)

Frame 2 Data MSByte

D7

D8

From
TI Device

ACK ByTI Device

D6

D5

D4

D3

D2

D1

D0

From
TI Device

ACK ByMaster(2)

No ACK By
MasterFrame 3 Data LSByte

(3)

Stop

(2)

The value of the slave address byte is determined by the settings of the A0 and A1 pins. Refer to Table 8-2.
Read data are from the last register pointer location. If a new register is desired, the register pointer must be updated. See Figure 8-7.
ACK by Master can also be sent.

Figure 8-5. Timing Diagram for Read Word Format
Figure 8-6 shows the timing diagram for the SMBus alert response operation. Figure 8-7 illustrates a typicalregister pointer configuration.
ALERT
1

9

1

9

SCL

SDA

0

0

0

1

1

0

0

R/W

Start By
Master

1

0

A3

A2

A1

A0

ACK ByFrom

TI Device

TI Device

Frame 1 SMBus ALERT Response Address Byte

A.

0

Frame 2 Slave Address Byte

0
NACK By
MasterStop By
Master(1)

The slave address byte value is determined by the settings of the A0 and A1 pins. Refer to Table 8-2.

Figure 8-6. Timing Diagram for SMBus Alert
1

9

1

9

SCL

¼

SDA

1

0

0

A3

A2

A1

A0

R/W

Start By
MasterFrame 1 Two-Wire Slave Address Byte

A.

P7

P6

P5

P4

P3

P2

P1

P0

ACK ByACK ByTI Device

TI Device

(1)

Stop

Frame 2 Register Pointer Byte

The slave address byte value is determined by the settings of the A0 and A1 pins. Refer to Table 8-2.

Figure 8-7. Typical Register Pointer Set

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8.5.5.1.1 Serial Bus Address

In order to communicate with the INA231, the master must first address slave devices using a corresponding
slave address byte. The slave address byte consists of seven address bits and a direction bit that indicates
whether the action is to be a read or write operation.
The INA231 has two address pins: A0 and A1. Table 8-2 describes the pin logic levels for each of the 16
possible addresses. The state of pins A0 and A1 is sampled on every bus communication. Set these pins before
any activity on the interface occurs.
Table 8-2. Address Pins andSlave Addresses

20

A1

A0

SLAVE ADDRESS

GND

GND

1000000

GND

VS

1000001

GND

SDA

1000010GND

SCL

1000011VS

GND

1000100

VS

VS

1000101

VS

SDA

1000110VS

SCL

1000111SDA

GND

1001000

SDA

VS

1001001

SDA

SDA

1001010SDA

SCL

1001011SCL

GND

1001100

SCL

VS

1001101

SCL

SDA

1001110SCL

SCL1001111

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8.5.5.1.2 Serial Interface

The INA231 operates only as a slave device on both the I2C bus and the SMBus. Connections to the bus
are made through the open-drain I/O lines, SDA and SCL. The SDA and SCL pins feature integrated spikesuppression filters and Schmitt triggers to minimize the effects of input spikes and bus noise. Although there is
spike suppression integrated into the digital I/O lines, use proper layout to minimize the amount of coupling into
the communication lines. This noise introduction could occur from capacitively coupling signal edges between
the two communication lines themselves or from other switching noise sources present in the system. Routing
traces in parallel with ground in between layers on a printed circuit board (PCB) typically reduces the effects ofcoupling between the communication lines. Shielding communication lines in general is recommended to reduce
to possibility of unintended noise coupling into the digital I/O lines that could be incorrectly interpreted as start orstop commands.
The INA231 supports the transmission protocol for Fast (1 kHz to 400 kHz) and High-speed (1 kHz to 2.5 MHz)
modes. All data bytes are transmitted most significant byte first.
8.5.5.2 High-Speed I2C Mode
When the bus is idle, both the SDA and SCL lines are pulled high by the pull-up devices. The master generates
a start condition followed by a valid serial byte containing High-Speed (HS) master code 00001XXX. Thistransmission is made in fast (400 kHz) or standard (100 kHz) (F/S) mode at no more than 400 kHz. The INA231
does not acknowledge the HS master code, but does recognize it and switches its internal filters to support
2.5-MHz operation.
The master then generates a repeated start condition (a repeated start condition has the same timing as
the start condition). After this repeated start condition, the protocol is the same as F/S mode except thattransmission speeds up to 2.5 MHz are allowed. Instead of using a stop condition, use repeated start conditions
to secure the bus in HS-mode. A stop condition ends the HS-mode and switches all the internal filters of the
INA231 to support the F/S mode. A bus timing diagram is shown in Figure 7-1.
8.5.6 SMBus Alert Response
The INA231 is designed to respond to the SMBus alert response address. The SMBus alert response provides
a quick fault identification for simple slave devices. When an alert occurs, the master can broadcast the alert
response slave address (0001 100) with the Read/Write bit set high. Following this alert response, any slave
devices that generated an alert identify themselves by acknowledging the alert response and sending theirrespective address on the bus.
The alert response can activate several different slave devices simultaneously, similar to the I2C general call. If
more than one slave attempts to respond, bus arbitration rules apply. The losing device does not generate an
acknowledge and continues to hold the ALERT line low until the interrupt is cleared.

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8.6 Register Maps
The INA231 uses a bank of registers for holding configuration settings, measurement results, minimum/
maximum limits, and status information. Table 8-3 summarizes the INA231 registers; refer to Figure 8-1 foran illustration of the registers.
All 16-bit INA231 registers are two 8-bit bytes through the I2C interface.
Table 8-3. Summary of Register Set
POINTERADDRESS

POWER-ON RESETHEXREGISTER NAMEFUNCTIONBINARYHEXTYPE(1)00

Configuration

This register resets all registers andcontrols shunt voltage and bus voltage,
ADC conversion times and averaging, as
well as the device operating mode.

01000001 00100111

4127

R/ W

01

Shunt Voltage

Shunt voltage measurement data

00000000 00000000

0000

R

02

Bus Voltage

Bus voltage measurement data

00000000 00000000

0000

R

00000000 00000000

0000

R

03

Power(2)This register contains the value of thecalculated power being delivered to the
load.

04

Current(2)This register contains the value of thecalculated current flowing through theshunt resistor.

00000000 00000000

0000

R

05

Calibration

This register sets the full-scale rangeand LSB of the current and power
measurements. This register sets theoverall system calibration.

00000000 00000000

0000

R/ W

06

Mask/Enable

This register sets the alert configurationand conversion ready flag.

00000000 00000000

0000

R/ W

07

Alert Limit

This register contains the limit value tocompare to the selected alert function.

00000000 00000000

0000

R/ W

(1)
(2)

Type: R = read-only, R/ W = read/write.
The Current register defaults to '0' because the Calibration register defaults to '0', yielding a zero current and power value until the
Calibration register is programmed.

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8.6.1 Configuration Register (00h, Read/Write)
Table 8-4. Configuration Register (00h, Read/Write) Descriptions
BIT #

D15

D14

D13

D12

D11

D10

D9

BIT
NAME

RST

—

—

—

AVG2

AVG1

AVG0

POR
VALUE

0

1

0

0

0

0

0

D8

D7

D6

VBUSCT2 VBUSCT1 VBUSCT0
1

0

0

D5

D4

D3

D2

D1

D0

VSHCT2

VSHCT1

VSHCT0

MODE3

MODE2

MODE1

1

0

0

1

1

1

The Configuration register settings control the operating modes for the INA231. This register controls theconversion time settings for both the shunt and bus voltage measurements, as well as the averaging mode
used. The operating mode that controls which signals are selected to be measured is also programmed in the
Configuration register.
The Configuration register can be read from at any time without impacting or affecting the device settings or
a conversion in progress. Writing to the Configuration register halts any conversion in progress until the write
sequence is complete, resulting in the start of a new conversion based on the new contents of the Configuration
register. This feature prevents any uncertainty in the conditions used for the next completed conversion.
RST:

Reset Bit

Bit 15

Setting this bit to 1 generates a system reset that is the same as a power-on reset; all registers are reset to default
values. This bit self-clears.

AVG:

Averaging Mode

Bits 9–11

These bits set the number of samples that are collected and averaged together. Table 8-5 summarizes the AVG bit
settings and related number of averages for each bit.

8.6.1.1 AVG Bit Settings [11:9]
Table 8-5. AVG Bit Settings [11:9](1) Description

(1)

AVG2
(D11)

AVG1
(D10)

AVG0
(D9)

NUMBER OF
AVERAGES

0

0

0

1

0

0

1

4

0

1

0

16

0

1

1

64

1

0

0

128

1

0

1

256

1

1

0

512

1

1

1

1024

Shaded values are default.

VBUS CT:Bus Voltage Conversion Time

Bits 6–8

These bits set the conversion time for the bus voltage measurement. Table 8-6 shows the VBUS CT bit options andrelated conversion times for each bit.

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8.6.1.2 VBUS CT Bit Settings [8:6]
Table 8-6. VBUS CT Bit Settings [8:6](1) Description(1)

VBUS CT2(D8)

VBUS CT1(D7)

VBUS CT0(D6)

CONVERSION TIME

0

0

0

140 µs001204 µs010332 µs01

1588 µs100

1.1 ms1012.116 ms

1

1

0

4.156 ms

1

1

1

8.244 ms

Shaded values are default.

VSH CT:

Shunt Voltage Conversion Time

Bits 3–5

These bits set the conversion time for the shunt voltage measurement. Table 8-7 shows the VSH CT bit options andrelated conversion times for each bit.

8.6.1.3 VSH CT Bit Settings [5:3]
Table 8-7. Register Description VSH CT Bit Settings [5:3](1)(1)

VSH CT2(D5)

VSH CT1(D4)

VSH CT0(D3)

CONVERSION TIME

0

0

0

140 µs001204 µs010332 µs01

1588 µs100

1.1 ms1012.116 ms

1

1

0

4.156 ms

1

1

1

8.244 ms

Shaded values are default.

MODE:

Operating Mode

Bits 0–2

These bits select continuous, triggered, or power-down mode of operation. These bits default to continuous shuntand bus measurement mode. The mode settings are shown in Table 8-8.

8.6.1.4 Mode Settings [2:0]
Table 8-8. Mode Settings [2:0](1)
MODE3
(D2)

MODE2
(D1)

MODE1
(D0)

MODE

0

0

0

Power-down (INA231B default)

0

0

1

Shunt voltage, triggered

0

1

0

Bus voltage, triggered

0

1

1

Shunt and bus, triggered

1

0

0

Power-down

1

0

1

Shunt voltage, continuous

1

1

0

Bus voltage, continuous

1

1

1

Shunt and bus, continuous (INA231A default)(1)

Shaded values are default.

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8.6.2 Shunt Voltage Register (01h, Read-Only)
The Shunt Voltage register stores the current shunt voltage reading, VSHUNT. Negative numbers are represented
in twos complement format. Generate the two's complement of a negative number by complementing theabsolute value binary number and adding 1. Extend the sign, denoting a negative number by setting the MSB =1.
Example: For a value of VSHUNT = –80 mV:
1. Take the absolute value: 80mV
2. Translate this number to a whole decimal number (80 mV ÷ 2.5 µV) = 32000
3. Convert this number to binary = 111 1101 0000 0000
4. Complement the binary result = 000 0010 1111 1111
5. Add '1' to the complement to create the two's complement result = 000 0011 0000 0000
6. Extend the sign and create the 16-bit word: 1000 0011 0000 0000 = 8300h
This register displays the averaged value if averaging is enabled. Full-scale range = 81.9175 mV (decimal =7FFF); LSB: 2.5 μV.
Table 8-9. Shunt Voltage Register (01h, Read-Only) Description
BIT #

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

BIT
NAME

SIGN

SD14

SD13

SD12

SD11

SD10

SD9

SD8

SD7

SD6

SD5

SD4

SD3

SD2

SD1

SD0

POR
VALUE

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

8.6.3 Bus Voltage Register (02h, Read-Only)
The Bus Voltage register stores the most recent bus voltage reading, VBUS.
This register displays the averaged value if averaging is enabled. Full-scale range = 40.95875 V (decimal =7FFF); LSB = 1.25 mV. Do not apply more than 28 V on the BUS pin.
Table 8-10. Bus Voltage Register (02h, Read-Only)(1) Description
BIT #

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

BIT
NAME

—

BD14

BD13

BD12

BD11

BD10

BD9

BD8

BD7

BD6

BD5

BD4

BD3

BD2

BD1

BD0

POR
VALUE

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

(1)

D15 is always zero because bus voltage can only be positive.

8.6.4 Power Register (03h, Read-Only)
This register displays the averaged value if averaging is enabled.
Table 8-11. Power Register (03h, Read-Only) Description
BIT #

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

BIT
NAME

PD15

PD14

PD13

PD12

PD11

PD10

PD9

PD8

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

POR
VALUE

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

The Power register LSB is internally programmed to equal 25 times the programmed value of the Current_LSB.
The Power register records power in watts by multiplying the decimal values of the current register with thedecimal value of the bus voltage register according to Equation 4.

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8.6.5 Current Register (04h, Read-Only)
If averaging is enabled, this register displays the averaged value.
Table 8-12. Current Register (04h, Read-Only) Description
BIT #

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

BIT
NAME

CSIGN

CD14

CD13

CD12

CD11

CD10

CD9

CD8

CD7

CD6

CD5

CD4

CD3

CD2

CD1

CD0

POR
VALUE

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

The value of the Current register is calculated by multiplying the decimal value in the Shunt Voltage register withthe decimal value of the Calibration register, according to Equation 3.
8.6.6 Calibration Register (05h, Read/Write)
This register provides the INA231 with the shunt resistor value that was present to create the measured
differential voltage. This register also sets the resolution of the Current register. The Current register LSB andPower register LSB are set through the programming of this register. This register is also used for overall systemcalibration. See the Configure, Measure, and Calculate Example for more information on programming thisregister.
Table 8-13. Calibration Register (05h, Read/Write) Description
BIT #

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

BIT
NAME

—

FS14

FS13

FS12

FS11

FS10

FS9

FS8

FS7

FS6

FS5

FS4

FS3

FS2

FS1

FS0

POR
VALUE

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

8.6.7 Mask/Enable Register (06h, Read/Write)
The Mask/Enable register selects the function that controls the ALERT pin, as well as how that pin functions.
If multiple functions are enabled, the highest significant bit position alert function (D15:D11) takes priority andresponds to the Alert Limit register.
Table 8-14. Mask/Enable Register (06h, Read/Write) Description
BIT #

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

BIT
NAME

SOL

SUL

BOL

BUL

POL

CNVR

—

—

—

—

—

AFF

CVRF

OVF

APOL

LEN

POR
VALUE

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

SOL:

Shunt Voltage Overvoltage1

Bit 15

Setting this bit high configures the ALERT pin to be asserted when the shunt voltage conversion exceeds the value
in the Alert Limit register.

SUL:

Shunt Voltage Undervoltage

Bit 14

Setting this bit high configures the ALERT pin to be asserted when the shunt voltage conversion drops below thevalue in the Alert Limit register.

BOL:

Bus Voltage Overvoltage

Bit 13

Setting this bit high configures the ALERT pin to be asserted when the bus voltage conversion exceeds the value in
the Alert Limit register.

BUL:Bus Voltage Undervoltage

Bit 12

Setting this bit high configures the ALERT pin to be asserted when the bus voltage conversion drops below thevalue in the Alert Limit register.

POL:Power Overlimit

Bit 11

Setting this bit high configures the ALERT pin to be asserted when the power calculation exceeds the value in theAlert Limit register.

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CNVR:

Conversion Ready

Bit 10Setting this bit high configures the ALERT pin to be asserted when the Conversion Ready Flag bit (CVRF, bit 3) isasserted, indicating that the device is ready for the next conversion.

AFF:

Alert Function Flag

Bit 4

Although only one alert function at a time can be monitored at the ALERT pin, the Conversion Ready bit (CNVR,
bit 10) can also be enabled to assert the ALERT pin. Reading the Alert Function Flag bit after an alert can help
determine if the alert function was the source of the alert.
When the Alert Latch Enable bit is set to Latch mode, the Alert Function Flag bit clears only when the Mask/Enableregister is read. When the Alert Latch Enable bit is set to Transparent mode, the Alert Function Flag bit is cleared
after the next conversion that does not result in an alert condition.

CVRF:

Conversion Ready Flag

Bit 3

Although the INA231 can be read at any time, and the data from the last conversion are available, this bit isprovided to help coordinate single-shot or triggered conversions. This bit is set after all conversions, averaging, andmultiplications are complete. This bit clears under the following conditions in single-shot mode:
1) Writing to the Configuration register (except for power-down or disable selections)
2) Reading the Mask/Enable register

OVF:

Math Overflow Flag

Bit 2This bit is set to 1 if an arithmetic operation results in an overflow error; it indicates that current and power data may
be invalid.

APOL:

Alert Polarity

Bit 1

Configures the latching feature of the ALERT pin and the flag bits.
1 = Inverted (active-high open collector)
0 = Normal (active-low open collector) (default)

LEN:

Alert Latch Enable

Bit 0

Configures the latching feature of the ALERT pin and flag bits.
1 = Latch enabled
0 = Transparent (default)
When the Alert Latch Enable bit is set to Transparent mode, the ALERT pin and flag bits reset to their idle states
when the fault has been cleared. When the Alert Latch Enable bit is set to Latch mode, the ALERT pin and flag bits
remain active following a fault until the Mask/Enable register has been read.

8.6.8 Alert Limit Register (07h, Read/Write)
The Alert Limit register contains the value used to compare to the register selected in the Mask/Enable registerto determine if a limit has been exceeded.
Table 8-15. Alert Limit Register (07h, Read/Write) Description
BIT #

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

BIT
NAME

AUL15

AUL14

AUL13

AUL12

AUL11

AUL10

AUL9

AUL8

AUL7

AUL6

AUL5

AUL4

AUL3

AUL2

AUL1

AUL0

POR
VALUE

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible fordetermining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

9.1 Application Information
The INA231 is a digital current shunt monitor with an I2C- and SMBus-compatible interface. This device provides
digital current, voltage, and power readings necessary for accurate decision-making in precisely-controlled
systems. Programmable registers allow flexible configuration for measurement resolution, as well as continuousversus-triggered operation. Detailed register information appears towards the end of this data sheet, beginningwith Table 8-3. See Figure 8-1 for a block diagram of the INA231.
Figure 9-1 shows a typical application circuit for the INA231. For power-supply bypassing, place a 0.1-μF
ceramic capacitor as close as possible to the supply and ground pins.
Power Supply(0 V to 28 V)

CBYPASS
0.1 mF

VS(Supply Voltage)

BUS

HighSide
Shunt

INA231
SDA
SCL

´

Load

Power RegisterV

2

Current Register
ADC

LowSideShunt

I

Voltage Register

IC
Interface
ALERT
A0

Alert Register

A1

GND

Figure 9-1. High- or Low-Side Sensing
9.1.1 Filtering and Input Considerations
Measuring current is often a noisy task, and such noise can be difficult to define. The INA231 offers several
options for filtering by allowing the conversion times and number of averages to be independently selected in
the Configuration register. The conversion times can be independently set for the shunt voltage and bus voltage
measurements to allow added flexibility in configuring the monitoring of the power-supply bus.
The internal ADC is based on a delta-sigma (ΔΣ) front-end with a 500-kHz (±30%) typical sampling rate. Thisarchitecture has good inherent noise rejection; however, transients that occur at or very close to the sampling
rate harmonics can cause problems. These signals are at 1 MHz and higher; therefore, manage them byincorporating filtering at the input of the INA231. The high frequency enables the use of low-value series
resistors on the filter with negligible effects on measurement accuracy. In general, filtering the INA231 input isonly necessary if there are transients at exact harmonics of the 500-kHz (±30%) sampling rate (greater than
1 MHz). Filter using the lowest possible series resistance (typically 10 Ω or less) and a ceramic capacitor.
Recommended values for this capacitor are 0.1 μF to 1.0 μF. Figure 9-2 shows the INA231 with an additional
filter added at the input.
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Power Supply(0 V to 28 V)

CBYPASS
0.1 mF
VS(Supply Voltage)

BUS

CFILTER
0.1 mF to 1 mF
Ceramic
Capacitor

SDA
SCL

´
RFILTER£10 W

IN+

Power RegisterV

2

Current Register
ADC
I

Load

RFILTER£10 W

Voltage Register

IC
Interface
ALERT
A0

INAlert Register

A1

GND

Figure 9-2. INA231 With Input Filtering
Overload conditions are another consideration for the INA231 inputs. The INA231 inputs are specified to tolerate
30 V across the inputs. A large differential scenario might be a short to ground on the load side of the shunt. This
type of event can result in full power-supply voltage across the shunt (as long as the power supply or energy
storage capacitors support it). Keep in mind that removing a short to ground can result in inductive kickbacks
that could exceed the 30-V differential and common-mode rating of the INA231. Inductive kickback voltages are
best controlled by zener-type transient-absorbing devices (commonly called transzorbs) combined with sufficientenergy storage capacitance.
In applications that do not have large energy-storage electrolytics on one or both sides of the shunt, an input
overstress condition may result from an excessive dV/dt of the voltage applied to the input. A hard physicalshort is the most likely cause of this event, particularly in applications with no large electrolytics present. This
problem occurs because an excessive dV/dt can activate the ESD protection in the INA231 in systems wherelarge currents are available. Testing has demonstrated that the addition of 10-Ω resistors in series with each
input of the INA231 sufficiently protect the inputs against this dV/dt failure up to the 30-V rating of the INA231.
Selecting these resistors in the range noted has minimal effect on accuracy.

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9.2 Typical Applications+12-V Supply

CBYPASS
0.1 mF
VS(Supply Voltage)

BUS

SDA
SCL

´
IN+

Power RegisterV

2

Current Register
ADC

RSHUNT
2 mW

I

Voltage Register

IC
Interface
ALERT
A0

INAlert Register

10A
Load

A1

GND

Figure 9-3. Monitoring a 10-A Load
9.2.1 Design Requirements
The INA231 measures the voltage developed across a current-sensing resistor (RSHUNT) when current passes
through the resistor. The device also measures the bus supply voltage, and calculates power when calibrated.
The INA231 comes with alert capability, where the alert pin can be programmed to respond to a user-defined
event, or to a conversion-ready notification. This design illustrates the ability of the alert pin to respond to a set
threshold. In this case, a 10 A are pulled through a 2-mΩ shunt resistor, generating a 20-mV shunt voltage dropthat is measured by the INA231. The bus supply is 12 V, and the BUS pin is tied to the IN– pin, so that the power
loss through the shunt resistor, however small, is not added to the power calculation performed by the INA231.
This configuration provides an accurate measurement the power dissipated by the load.
9.2.2 Detailed Design Procedure
The ALERT pin can be configured to respond to one of the five alert functions described in the ALERT Pin
section. The ALERT pin must to be pulled up to the vs pin voltage using a pull-up resistor. The Configuration
register is set based on the required conversion time and averaging. The Mask/Enable register is set to identify
the required alert function and the Alert Limit register is set to the limit value used for comparison.

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9.2.3 Application Curves

SHUNT Voltage(50 mV/div)

SHUNT Voltage(50 mV/div)

ALERT(2 V/div)

ALERT(2 V/div)

Figure 9-4 shows the ALERT pin response to a shunt overvoltage of 50 mV for a conversion time (tCT) of 140 μs.
and averaging set to 1. Figure 9-5 shows the response for the same limit, but with the conversion time reduced
to 1.1 ms.

Time (100 µs/div)

Time (1 ms/div)

Configuration register = 4005h
Mask/Enable register = 8008h
Alert Limit register = 4E20h,
tCT = 140 µs

Configuration register = 4125h
Mask/Enable register = 8008h
Alert Limit register = 4E20h,
tCT = 1.1 ms

Figure 9-4. Alert Response

Figure 9-5. Alert Response

9.3 Power Supply Recommendations
The INA231 input circuitry accurately measures signals on common-mode voltages beyond the device powersupply voltage, VS. For example, the voltage applied to the power-supply pin (VS) can be 5 V; however, the load
power-supply voltage being monitored (the common-mode voltage) can be as high as 28 V. The device can also
withstand the full 0-V to 28-V range at the input terminals, regardless of whether the device has power applied ornot.
Place the required power-supply bypass capacitors as close as possible to the supply and ground pins of thedevice. A typical value for this supply bypass capacitor is 0.1 μF. For more accurate results for applications withnoisy or high-impedance power supplies, use additional decoupling capacitors to reject power-supply noise.

9.4 Layout
9.4.1 Layout Guidelines
Connect the input pins (IN+ and IN–) to the sensing resistor using a Kelvin or 4-wire connection. These
connection techniques make sure that only the current-sensing resistor impedance is detected between the input
pins. Poor routing of the current-sensing resistor commonly results in additional resistance present between the
input pins. Given the very low ohmic value of the current-sensing resistor, any additional high-current-carrying
impedance causes significant measurement errors. Place the power-supply bypass capacitor as close as
possible to the supply and ground pins. Make sure the NC pins (B2 and C2) are not connected to anything.

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9.4.2 Layout Example

Tie to GND, VS,
SCL, or SDA to set
I2C address

RPULLUP

VIA to another layer

A0

A1

IN+

SDA

NC

NC

IN-

SCL

VS

GND

BUS

RPULLUPRPULLUP

I2C/SMBUS
interface

ALERT

RSHUNT

Alert output(Can be left floating
if unused)

VIA to GND
CBYPASSVIA to another layer

Connect to supply for VS

Figure 9-6. Layout Example

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10 Device and Documentation Support
10.1 Documentation Support
10.1.1 Related Documentation
For related documentation see the following:
INA231EVM Evaluation Board and Software Tutorial

10.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. Forchange details, review the revision history included in any revised document.

10.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straightfrom the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.

10.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.

10.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handledwith appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its publishedspecifications.

10.6 Glossary
TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and revision ofthis document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OUTLINEYFD0012DSBGA - 0.4 mm max height
SCALE 8.000

DIE SIZE BALL GRID ARRAY

B

A

E

BALL A1CORNERD

0.4 MAXCSEATING PLANE
0.175
0.125

BALL TYP

0.05 C

0.8
TYP
SYMM
D

1.2
TYP

C
SYMM

D: Max = 1.675 mm, Min =1.614 mm

B
0.4
TYP

12X
0.015

0.243
0.226
C A B

E: Max = 1.418 mm, Min =1.358 mm
A

2

1

3

0.4
TYP
4223364/A 10/2016

NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.

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SBOS644D – FEBRUARY 2013 – REVISED JULY 2022

EXAMPLE BOARD LAYOUTYFD0012DSBGA - 0.4 mm max height
DIE SIZE BALL GRID ARRAY(0.4) TYP

12X ( 0.225)

A(0.4) TYP

B
SYMM

C

D
1

2

3

SYMM

LAND PATTERN EXAMPLESCALE:40X

0.05 MAX( 0.225)METAL

METAL UNDERSOLDER MASK

0.05 MIN( 0.225)
SOLDER MASKOPENINGSOLDER MASKOPENINGNON-SOLDER MASKDEFINED(PREFERRED)SOLDER MASKDEFINEDSOLDER MASK DETAILSNOT TO SCALE
4223364/A 10/2016

NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
Refer to Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009).

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INA231www.ti.com

SBOS644D – FEBRUARY 2013 – REVISED JULY 2022

EXAMPLE STENCIL DESIGNYFD0012DSBGA - 0.4 mm max height
DIE SIZE BALL GRID ARRAY(0.4) TYP
(R0.05) TYP

12X ( 0.25)

A
(0.4)
TYP
B
SYMM

METAL
TYP

C

D
1

2
SYMM

3

SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCILSCALE:40X

4223364/A 10/2016

NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

36

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SBOS644D – FEBRUARY 2013 – REVISED JULY 2022

PACKAGE OUTLINE

YFF0012DSBGA - 0.625 mm max height
SCALE 8.000

DIE SIZE BALL GRID ARRAY

B

A

E

BALL A1CORNERD

0.625 MAXCSEATING PLANE
BALL TYP

0.30
0.12

0.05 C

0.8 TYP
0.4 TYP

D

SYMM

C
1.2
TYP

B

D: Max = 1.675 mm, Min =1.614 mm
E: Max = 1.418 mm, Min =1.358 mm

A

12X
0.015

0.3
0.2
C A

1

2

3

0.4 TYP

SYMM
B

4222191/A 07/2015

NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.

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SBOS644D – FEBRUARY 2013 – REVISED JULY 2022

EXAMPLE BOARD LAYOUT

YFF0012DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY(0.4) TYP
12X ( 0.23)

1

2

3

A
(0.4) TYP
B

SYMM

C

D
SYMM

LAND PATTERN EXAMPLESCALE:30X

0.05 MAX( 0.23)METAL

METAL UNDERSOLDER MASK

0.05 MIN( 0.23)
SOLDER MASKOPENINGSOLDER MASKOPENINGNON-SOLDER MASKDEFINED(PREFERRED)SOLDER MASKDEFINEDSOLDER MASK DETAILSNOT TO SCALE

4222191/A 07/2015

NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For more information,
see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).

38

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Product Folder Links: INA231

INA231www.ti.com

SBOS644D – FEBRUARY 2013 – REVISED JULY 2022

EXAMPLE STENCIL DESIGNYFF0012DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY(0.4) TYP
12X ( 0.25)(R0.05) TYP
1

2

3

A
(0.4) TYP
B
SYMM
METAL
TYP
C

D
SYMM

SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCILSCALE:30X

4222191/A 07/2015

NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

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39

PACKAGE OPTION ADDENDUM
www.ti.com

19-Aug-2021

PACKAGING INFORMATION
Orderable Device

Status(1)

Package Type Package Pins Package
Drawing
Qty

Eco Plan(2)

Lead finish/
Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

(3)

(4/5)

(6)

INA231AIYFDRACTIVE

DSBGA

YFD

12

3000

RoHS & GreenSNAGCU

Level-1-260C-UNLIM-40 to 125

I231YFD

INA231AIYFDTACTIVE

DSBGA

YFD

12

250

RoHS & GreenSNAGCU

Level-1-260C-UNLIM-40 to 125

I231YFD

INA231AIYFFRACTIVE

DSBGA

YFF

12

3000

RoHS & GreenSNAGCU

Level-1-260C-UNLIM-40 to 125

INA231

INA231AIYFFTACTIVE

DSBGA

YFF

12

250

RoHS & GreenSNAGCU

Level-1-260C-UNLIM-40 to 125

INA231

INA231BIYFDRACTIVE

DSBGA

YFD

12

3000

RoHS & GreenSNAGCU

Level-1-260C-UNLIM-40 to 125

231BYFD

INA231BIYFDTACTIVE

DSBGA

YFD

12

250

RoHS & GreenSNAGCU

Level-1-260C-UNLIM-40 to 125

231BYFD(1)

The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)

RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)

MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.
(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to twolines if the finish value exceeds the maximum column width.

Addendum-Page 1

SamplesPACKAGE OPTION ADDENDUM
www.ti.com

19-Aug-2021

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION
www.ti.com

19-Aug-2021

TAPE AND REEL INFORMATION*All dimensions are nominal

DevicePackage Package Pins
Type Drawing

SPQ

Reel
Reel
A0
Diameter Width (mm)(mm) W1 (mm)

B0
(mm)

K0
(mm)

P1
(mm)

W
Pin1
(mm) Quadrant

INA231AIYFDR

DSBGA

YFD

12

3000

180.0

8.4

1.49

1.76

0.5

4.0

8.0

Q1

INA231AIYFDT

DSBGA

YFD

12

250

180.0

INA231AIYFFR

DSBGA

YFF

12

3000

180.0

8.4

1.49

1.76

0.5

4.0

8.0

Q1

8.4

1.48

1.78

0.69

4.0

8.0

INA231AIYFFT

DSBGA

YFF

12

250

Q1

180.0

8.4

1.48

1.78

0.69

4.0

8.0

INA231BIYFDR

DSBGA

YFD

12

Q1

3000

180.0

8.4

1.49

1.76

0.5

4.0

8.0

Q1

INA231BIYFDT

DSBGA

YFD

12

250

180.0

8.4

1.49

1.76

0.5

4.0

8.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION
www.ti.com

19-Aug-2021*All dimensions are nominal

DevicePackage Type

Package Drawing

Pins

SPQ

Length (mm)Width (mm)Height (mm)INA231AIYFDR

DSBGA

YFD

12

3000

182.0

182.0

20.0

INA231AIYFDT

DSBGA

YFD

12

250

182.0

182.0

20.0

INA231AIYFFR

DSBGA

YFF

12

3000

182.0

182.0

20.0

INA231AIYFFT

DSBGA

YFF

12

250

182.0

182.0

20.0

INA231BIYFDR

DSBGA

YFD

12

3000

182.0

182.0

20.0

INA231BIYFDT

DSBGA

YFD

12

250

182.0

182.0

20.0

Pack Materials-Page 2

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