Quad-Channel Digital Isolators
ADuM1410/ADuM1411/ADuM1412

Data Sheet

FUNCTIONAL BLOCK DIAGRAMSGeneral-purpose multichannel isolation
SPI interface/data converter isolation
RS-232/RS-422/RS-485 transceivers
Industrial field bus isolation

15 GND2

VIA 3

ENCODEDECODE

14 VOA

VIB 4

ENCODEDECODE

13 VOB

VIC 5

ENCODEDECODE

12 VOC

VID 6

ENCODEDECODE

11 VODDISABLE 7

10 CTRL2

GND1 89

GND2

Figure 1. ADuM1410
VDD1 1
GND1 2

16 VDD2

ADuM1411

15 GND2

VIA 3

ENCODEDECODE

14 VOA

VIB 4

ENCODEDECODE

13 VOB

VIC 5

ENCODEDECODE

12 VOCVOD 6DECODEENCODE

11 VID

CTRL1 7

10 CTRL2

GND1 8

9 GND2

Figure 2. ADuM1411
VDD1 1
GND1 2

APPLICATIONS

16 VDD2

ADuM1410

06580-001

VDD1 1
GND1 206580-002

Low power operation
5 V operation
1.3 mA per channel maximum at 0 Mbps to 2 Mbps
4.0 mA per channel maximum at 10 Mbps
3 V operation
0.8 mA per channel maximum at 0 Mbps to 2 Mbps
1.8 mA per channel maximum at 10 Mbps
Bidirectional communication
3 V/5 V level translation
High temperature operation: 105°C
Up to 10 Mbps data rate (NRZ)
Programmable default output stateHigh common-mode transient immunity: >25 kV/µs
16-lead, RoHS compliant, SOIC wide body package
Safety and regulatory approvals
UL recognition: 3750 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice 5A
VDE certificate of conformity
DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12
VIORM = 560 V peakTÜV approval: IEC/EN 60950-1

16 VDD2

ADuM1412

15 GND2

VIA 3

ENCODEDECODE

14 VOA

VIB 4

ENCODEDECODE

13 VOBVOC 5DECODEENCODE

12 VICVOD 6DECODEENCODE

11 VID

CTRL1 7

10 CTRL2

GND1 89GND206580-003

FEATURES

Figure 3. ADuM1412

GENERAL DESCRIPTION
The ADuM1410/ADuM1411/ADuM14121 are four-channel
digital isolators based on Analog Devices, Inc., iCoupler®
technology. Combining high speed CMOS and monolithic air
core transformer technologies, these isolation components provide
outstanding performance characteristics superior to alternatives
such as optocoupler devices.
By avoiding the use of LEDs and photodiodes, iCoupler devices
remove the design difficulties commonly associated with optocouplers. The usual concerns that arise with optocouplers, suchas uncertain current transfer ratios, nonlinear transfer functions,and temperature and lifetime effects, are eliminated with the simple
iCoupler digital interfaces and stable performance characteristics.
The need for external drivers and other discrete components iseliminated with these iCoupler products. Furthermore, iCoupler1

devices consume one-tenth to one-sixth the power of optocouplers at comparable signal data rates.
The ADuM1410/ADuM1411/ADuM1412 isolators provide four
independent isolation channels in a variety of channel configurations and data rates (see the Ordering Guide) up to 10 Mbps.
All models operate with the supply voltage on either side ranging
from 2.7 V to 5.5 V, providing compatibility with lower voltage
systems as well as enabling voltage translation functionality acrossthe isolation barrier. All products also have a default output
control pin. This allows the user to define the logic state theoutputs are to adopt in the absence of the input power. Unlike
other optocoupler alternatives, the ADuM1410/ADuM1411/
ADuM1412 isolators have a patented refresh feature that ensures
dc correctness in the absence of input logic transitions andduring power-up/power-down conditions.

Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329.

Rev. M

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ADuM1410/ADuM1411/ADuM1412

Data SheetTABLE OF CONTENTS
Features .............................................................................................. 1

Recommended Operating Conditions .................................... 11

Applications ....................................................................................... 1

Absolute Maximum Ratings ......................................................... 12

Functional Block Diagrams ............................................................. 1

ESD Caution................................................................................ 12

General Description ......................................................................... 1

Pin Configurations and Function Descriptions ......................... 13

Revision History ............................................................................... 2

Typical Performance Characteristics ........................................... 17

Specifications..................................................................................... 3

Applications Information .............................................................. 19

Electrical Characteristics—5 V Operation................................ 3

PC Board Layout ........................................................................ 19

Electrical Characteristics—3 V Operation................................ 5

Propagation Delay-Related Parameters ................................... 19

Electrical Characteristics—Mixed 5 V/3 V or 3 V/5 V
Operation....................................................................................... 7

DC Correctness and Magnetic Field Immunity........................... 19

Package Characteristics ............................................................. 10
Regulatory Information ............................................................. 10
Insulation and Safety-Related Specifications .......................... 10Power Consumption .................................................................. 20
Insulation Lifetime ..................................................................... 20
Outline Dimensions ....................................................................... 22
Ordering Guide .......................................................................... 22

DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12
Insulation Characteristics.......................................................... 11

REVISION HISTORY
8/15—Rev. L to Rev. M
Changes to Table 5 and Table 6 ..................................................... 10
7/15—Rev. K to Rev. L
Changes to Table 5 and Table 6 ..................................................... 10
4/15—Rev. J to Rev. K
Changed ADuM141x to ADuM1410/ADuM1411/
ADuM1412 ..................................................................... Throughout
Change to Features Section ............................................................. 1
Changes to Table 5 and Table 6 ..................................................... 10
4/14—Rev. I to Rev. J
Change to Table 5 ........................................................................... 10
3/12—Rev. H to Rev. I
Created Hyperlink for Safety and Regulatory Approvals
Entry in Features Section................................................................. 1
Change to PC Board Layout Section............................................ 19
11/10—Rev. G to Rev. H
Added TÜV Approval to Features Section.................................... 1
Added TÜV Column, Table 5 ....................................................... 10
6/07—Rev. F to Rev. G
Updated VDE Certification Throughout ...................................... 1

Changes to Features and Applications ............................................1
Changes to DC Specifications in Table 1........................................3
Changes to DC Specifications in Table 2........................................5
Changes to DC Specifications in Table 3........................................7
Changes to Regulatory Information Section .............................. 10
Added Table 10 ............................................................................... 12
Added Insulation Lifetime Section .............................................. 21
2/07—Rev. E to Rev. F
Added ADuM1410ARWZ ................................................ Universal
Updated Pin Name CTRL to CTRL2 Throughout ........................1
Changes to Ordering Guide .......................................................... 21
10/06—Rev. D to Rev. E
Added ADuM1411 and ADuM1412 ............................... Universal
Deleted ADuM1310 ........................................................... Universal
Changes to Features ..........................................................................1
Changes to Specifications Section ...................................................3
Updated Outline Dimensions ....................................................... 20
Changes to Ordering Guide .......................................................... 20
3/06—Rev. C to Rev. D
Added Note 1 and Changes to Figure 2 ..........................................1
Changes to Absolute Maximum Ratings ..................................... 11
11/05—Revision C: Initial Version

Rev. M | Page 2 of 22

Data Sheet

ADuM1410/ADuM1411/ADuM1412

SPECIFICATIONSELECTRICAL CHARACTERISTICS—5 V OPERATION
4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operation range,
unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V. All voltages are relative to their respective ground.
Table 1.
Parameter
DC SPECIFICATIONS
Input Supply Current per Channel,
Quiescent
Output Supply Current per Channel,
Quiescent
ADuM1410, Total Supply Current,
Four Channels 1
DC to 2 Mbps
VDD1 Supply Current
VDD2 Supply Current
10 Mbps (BRWZ Version Only)
VDD1 Supply Current
VDD2 Supply Current
ADuM1411, Total Supply Current,
Four Channels1
DC to 2 Mbps
VDD1 Supply Current
VDD2 Supply Current
10 Mbps (BRWZ Version Only)
VDD1 Supply Current
VDD2 Supply Current
ADuM1412, Total Supply Current,
Four Channels1
DC to 2 Mbps
VDD1 or VDD2 Supply Current

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

IDDI (Q)

0.50

0.73

mA

IDDO (Q)

0.38

0.53

mA

IDD1 (Q)IDD2 (Q)

2.4
1.2

3.2
1.6

mA
mA

DC to 1 MHz logic signal frequency
DC to 1 MHz logic signal frequency

IDD1 (10)IDD2 (10)

8.8
2.8

12
4.0

mA
mA

5 MHz logic signal frequency
5 MHz logic signal frequency

IDD1 (Q)IDD2 (Q)

2.2
1.8

2.8
2.4

mA
mA

DC to 1 MHz logic signal frequency
DC to 1 MHz logic signal frequency

IDD1 (10)IDD2 (10)

5.4
3.8

7.6
5.3

mA
mA

5 MHz logic signal frequency
5 MHz logic signal frequency

IDD1 (Q), IDD2

2.0

2.6

mA

DC to 1 MHz logic signal frequency

4.6

6.5

mA

5 MHz logic signal frequency

+0.01

+10

µA

0 V ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2,
0 V ≤ VCTRL1, VCTRL2 ≤ VDD1 or VDD2,
0 V ≤ VDISABLE ≤ VDD1

(Q)

10 Mbps (BRWZ Version Only)
VDD1 or VDD2 Supply Current
All Models
Input Currents
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
Logic Low Output Voltages

IDD1 (10), IDD2 (10)
IIA, IIB, IIC,
IID, ICTRL1,ICTRL2, IDISABLE
VIH
VIL
VOAH, VOBH,
VOCH, VODH

−10
2.0

0.8
(VDD1 or VDD2) − 0.1(VDD1 or VDD2) − 0.4

VOAL, VOBL,
VOCL, VODL

Rev. M | Page 3 of 22

5.0
4.8
0.0
0.04
0.2

0.1
0.1
0.4

V
V
V
V
V
V
V

IOx = −20 µA, VIx = VIxH
IOx = −4 mA, VIx = VIxH
IOx = 20 µA, VIx = VIxLIOx = 400 µA, VIx = VIxLIOx = 4 mA, VIx = VIxL

ADuM1410/ADuM1411/ADuM1412
Parameter
SWITCHING SPECIFICATIONS
ADuM1410ARWZ/ADuM1411ARWZ/
ADuM1412ARWZ
Minimum Pulse Width 2
Maximum Data Rate 3
Propagation Delay 4
Pulse Width Distortion, |tPLH − tPHL|4
Propagation Delay Skew 5
Channel-to-Channel Matching 6
ADuM1410BRWZ/ADuM1411BRWZ/
ADuM1412BRWZ
Minimum Pulse Width2
Maximum Data Rate3
Propagation Delay4
Pulse Width Distortion, |tPLH − tPHL|4
Change vs. Temperature
Propagation Delay Skew5
Channel-to-Channel Matching,
Codirectional Channels6
Channel-to-Channel Matching,
Opposing-Directional Channels6
All Models
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient Immunity
at Logic High Output 7
Common-Mode Transient Immunity
at Logic Low Output7
Refresh Rate
Input Enable Time 8
Input Disable Time8
Input Dynamic Supply Current
per Channel 9
Output Dynamic Supply Current
per Channel9

SymbolData Sheet
Min

Typ

PW
tPHL, tPLH
PWD
tPSK
tPSKCD/OD

1
20

65

PW

Max

Unit

Test Conditions/Comments

1000

ns
Mbps
ns
ns
ns
ns

CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels

CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels

100
40
50
50

tPSK
tPSKCD

30
5

ns
Mbps
ns
ns
ps/°C
ns
ns

tPSKOD

6ns

CL = 15 pF, CMOS signal levels

CL = 15 pF, CMOS signal levels
VIx = VDD1 or VDD2, VCM = 1000 V,
transient magnitude = 800 V
VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V

tPHL, tPLH
PWD

100
10
20

30

50
5

5

tR/tF
|CMH|

25

2.5
35

ns
kV/µs

|CML|

25

35

kV/µs

fr
tENABLEtDISABLE
IDDI (D)

1.2

IDDO (D)

0.04

2.0
5.0
0.12

Mbps
µs
µs
mA/
Mbps
mA/
Mbps

VIA, VIB, VIC, VID = 0 V or VDD1
VIA, VIB, VIC, VID = 0 V or VDD1

The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output loadpresent. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section.
See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 throughFigure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1410/ADuM1411/ADuM1412 channel configurations.
2
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4
tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay ismeasured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
6
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
7|CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. |CML| is the maximum common-mode voltage slew ratethat can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transientmagnitude is the range over which the common mode is slewed.
8
Input enable time is the duration from when VDISABLE is set low until the output states are guaranteed to match the input states in the absence of any input data logictransitions. If an input data logic transition within a given channel does occur within this time interval, the output of that channel reaches the correct state within themuch shorter duration as determined by the propagation delay specifications within this data sheet. Input disable time is the duration from when VDISABLE is set highuntil the output states are guaranteed to reach their programmed output levels, as determined by the CTRL2 logic state (see Table 14).
9
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for informationon per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
1Rev. M | Page 4 of 22

Data Sheet

ADuM1410/ADuM1411/ADuM1412

ELECTRICAL CHARACTERISTICS—3 V OPERATION
2.7 V ≤ VDD1 ≤ 3.6 V, 2.7 V ≤ VDD2 ≤ 3.6 V; all minimum/maximum specifications apply over the entire recommended operation range,
unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.0 V. All voltages are relative to their respective ground.
Table 2.
Parameter
DC SPECIFICATIONS
Input Supply Current per Channel,
Quiescent
Output Supply Current per Channel,
Quiescent
ADuM1410, Total Supply Current,
Four Channels 1
DC to 2 Mbps
VDD1 Supply Current
VDD2 Supply Current
10 Mbps (BRWZ Version Only)
VDD1 Supply Current
VDD2 Supply Current
ADuM1411, Total Supply Current,
Four Channels1
DC to 2 Mbps
VDD1 Supply Current
VDD2 Supply Current
10 Mbps (BRWZ Version Only)
VDD1 Supply Current
VDD2 Supply Current
ADuM1412, Total Supply Current,
Four Channels1
DC to 2 Mbps
VDD1 or VDD2 Supply Current
10 Mbps (BRWZ Version Only)
VDD1 or VDD2 Supply Current
All Models
Input Currents

SymbolMin

Typ

Max Unit

IDDI (Q)

0.25

0.38 mAIDDO (Q)

0.19

0.33 mA

IDD1 (Q)

1.2

1.6

mA

IDD2 (Q)

0.8

1.0

mA

IDD1 (10)IDD2 (10)

4.5
1.4

6.5
1.8

mA
mA

5 MHz logic signal frequency
5 MHz logic signal frequency

IDD1 (Q)IDD2 (Q)

1.0
0.9

1.9
1.7

mA
mA

DC to 1 MHz logic signal frequency
DC to 1 MHz logic signal frequency

IDD1 (10)IDD2 (10)

3.1
2.1

4.5
3.0

mA
mA

5 MHz logic signal frequency
5 MHz logic signal frequency

IDD1 (Q), IDD2 (Q)

1.0

1.8

mA

DC to 1 MHz logic signal frequency

IDD1 (10), IDD2 (10)

2.6

3.8

mA

5 MHz logic signal frequency

IIA, IIB, IIC, IID,ICTRL1,ICTRL2, IDISABLE−10

Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages

VIH
VIL
VOAH, VOBH,
VOCH, VODH

1.6

Logic Low Output Voltages

VOAL, VOBL,
VOCL, VODL

+0.01 +10 µA

0.4(VDD1 or VDD2) − 0.1 3.0(VDD1 or VDD2) − 0.4 2.8
0.0
0.04
0.2

Rev. M | Page 5 of 22

0.1
0.1
0.4

V
V
V
V
V
V
V

Test Conditions/Comments

DC to 1 MHz logic signal
frequency
DC to 1 MHz logic signal
frequency

0 V ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2,
0 V ≤ VCTRL1, VCTRL2 ≤ VDD1 or VDD2,
0 V ≤ VDISABLE ≤ VDD1

IOx = −20 µA, VIx = VIxH
IOx = −4 mA, VIx = VIxH
IOx = 20 µA, VIx = VIxLIOx = 400 µA, VIx = VIxLIOx = 4 mA, VIx = VIxL

ADuM1410/ADuM1411/ADuM1412
Parameter
SWITCHING SPECIFICATIONS
ADuM1410ARWZ/ADuM1411ARWZ/
ADuM1412ARWZ
Minimum Pulse Width 2
Maximum Data Rate 3
Propagation Delay 4
Pulse Width Distortion, |tPLH − tPHL|4
Propagation Delay Skew 5
Channel-to-Channel Matching 6
ADuM1410BRWZ/ADuM1411BRWZ/
ADuM1412BRWZ
Minimum Pulse Width2
Maximum Data Rate3
Propagation Delay4
Pulse Width Distortion, |tPLH − tPHL|4
Change vs. Temperature
Propagation Delay Skew5
Channel-to-Channel Matching,
Codirectional Channels6
Channel-to-Channel Matching,
Opposing-Directional Channels6
All Models
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient Immunity
at Logic High Output 7
Common-Mode Transient Immunity
at Logic Low Output7
Refresh Rate
Input Enable Time 8
Input Disable Time8
Input Dynamic Supply Current
per Channel 9
Output Dynamic Supply Current
per Channel9

SymbolData Sheet
Min

Typ

PW
tPHL, tPLH
PWD
tPSK
tPSKCD/OD

1
20

75

PW

Max Unit

Test Conditions/Comments

1000 ns
Mbps
100 ns
40
ns
50
ns
50
ns

CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels

100

CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels

tPSKtPSKCD

30
5

ns
Mbps
ns
ns
ps/°C
ns
ns

tPSKOD

6ns

tPHL, tPLH
PWD

10
20

40

60
5

5

tR/tF
|CMH|

25

2.5
35

|CML|

25

35

fr
tENABLEtDISABLE
IDDI (D)

1.1
2.0
5.0
0.07

IDDO (D)0.02

ns
CL = 15 pF, CMOS signal levels
kV/µs VIx = VDD1 or VDD2, VCM = 1000 V,
transient magnitude = 800 V
kV/µs VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
Mbpsµs
VIA, VIB, VIC, VID = 0 V or VDD1µs
VIA, VIB, VIC, VID = 0 V or VDD1
mA/
Mbps
mA/
Mbps

The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output loadpresent. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section.
See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 throughFigure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1410/ADuM1411/ADuM1412 channel configurations.
2
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4
tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay ismeasured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
6
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
7|CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. |CML| is the maximum common-mode voltage slew ratethat can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transientmagnitude is the range over which the common mode is slewed.
8
Input enable time is the duration from when VDISABLE is set low until the output states are guaranteed to match the input states in the absence of any input data logictransitions. If an input data logic transition within a given channel does occur within this time interval, the output of that channel reaches the correct state within themuch shorter duration as determined by the propagation delay specifications within this data sheet. Input disable time is the duration from when VDISABLE is set highuntil the output states are guaranteed to reach their programmed output levels, as determined by the CTRL2 logic state (see Table 14).
9
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for informationon per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
1Rev. M | Page 6 of 22

Data Sheet

ADuM1410/ADuM1411/ADuM1412

ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V OPERATION
5 V/3 V operation: 4.5 V ≤ VDD1 ≤ 5.5 V, 2.7 V ≤ VDD2 ≤ 3.6 V; 3 V/5 V operation: 2.7 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 5.5 V; allminimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications
are at TA = 25°C; VDD1 = 3.0 V, VDD2 = 5 V; or VDD1 = 5 V, VDD2 = 3.0 V. All voltages are relative to their respective ground.
Table 3.
Parameter
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
5 V/3 V Operation
3 V/5 V Operation
Output Supply Current per Channel, Quiescent
5 V/3 V Operation
3 V/5 V Operation
ADuM1410, Total Supply Current,
Four Channels 1
DC to 2 Mbps
VDD1 Supply Current
5 V/3 V Operation

SymbolMin

Typ

Max Unit

0.50
0.25

0.73 mA
0.38 mA

0.19
0.38

0.33 mA
0.53 mA

2.4

3.2

mA

1.2

1.6

mA

0.8

1.0

mA

1.2

1.6

mA

DC to 1 MHz logic signal
frequency
DC to 1 MHz logic signal
frequency

8.6
3.4

11
6.5

mA
mA

5 MHz logic signal frequency
5 MHz logic signal frequency

1.4
2.6

1.8
3.0

mA
mA

5 MHz logic signal frequency
5 MHz logic signal frequency

2.2

2.8

mA

1.0

1.9

mA

0.9

1.7

mA

1.7

2.4

mA

DC to 1 MHz logic signal
frequency
DC to 1 MHz logic signal
frequency

5.4
3.1

7.6
4.5

mA
mA

5 MHz logic signal frequency
5 MHz logic signal frequency

2.1
3.8

3.0
5.3

mA
mA

5 MHz logic signal frequency
5 MHz logic signal frequency

IDDI (Q)IDDO (Q)

IDD1 (Q)

3 V/5 V Operation
VDD2 Supply Current
5 V/3 V Operation

10 Mbps (BRWZ Version Only)
VDD1 Supply Current
IDD1 (10)
5 V/3 V Operation
3 V/5 V Operation
VDD2 Supply Current
IDD2 (10)
5 V/3 V Operation
3 V/5 V Operation
ADuM1411, Total Supply Current, Four Channels1
DC to 2 Mbps
VDD1 Supply Current
IDD1 (Q)
5 V/3 V Operation
3 V/5 V Operation

DC to 1 MHz logic signal
frequency
DC to 1 MHz logic signal
frequency

IDD2 (Q)

3 V/5 V Operation
10 Mbps (BRWZ Version Only)
VDD1 Supply Current
5 V/3 V Operation
3 V/5 V Operation
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation

DC to 1 MHz logic signal
frequency
DC to 1 MHz logic signal
frequency

IDD2 (Q)

3 V/5 V Operation

VDD2 Supply Current
5 V/3 V Operation

Test Conditions/Comments

IDD1 (10)IDD2 (10)Rev. M | Page 7 of 22

ADuM1410/ADuM1411/ADuM1412
Parameter
Symbol
ADuM1412, Total Supply Current, Four Channels1
DC to 2 Mbps
VDD1 Supply Current
IDD1 (Q)
5 V/3 V Operation

Data Sheet
Min

Typ

Max Unit

2.0

2.6

mA

1.0

1.8

mA

1.0

1.8

mA

2.0

2.6

mA

DC to 1 MHz logic signal
frequency
DC to 1 MHz logic signal
frequency

4.6
2.6

6.5
3.8

mA
mA

5 MHz logic signal frequency
5 MHz logic signal frequency

2.6
4.6

3.8
6.5

mA
mA

5 MHz logic signal frequency
5 MHz logic signal frequencyμA

0 V ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2,
0 V ≤ VCTRL1, VCTRL2 ≤ VDD1 or VDD2,
0 V ≤ VDISABLE ≤ VDD1

3 V/5 V Operation
VDD2 Supply Current
5 V/3 V Operation

Logic High Input Threshold
5 V/3 V Operation
3 V/5 V Operation
Logic Low Input Threshold
5 V/3 V Operation
3 V/5 V Operation
Logic High Output Voltages

IDD1 (10)IDD2 (10)

IIA, IIB, IIC,
IID,ICTRL1, ICTRL2,−10
IDISABLE
VIH
2.0
1.6
VIL

+0.01

+10

V
V
0.8
0.4

VOAH, VOBH,
VOCH, VODH
Logic Low Output Voltages
VOAL, VOBL,
VOCL, VODLSWITCHING SPECIFICATIONS
ADuM1410ARWZ/ADuM1411ARWZ/
ADuM1412ARWZ
Minimum Pulse Width2
Maximum Data Rate3
Propagation Delay4
Pulse Width Distortion, |tPLH − tPHL|4
Propagation Delay Skew5
Channel-to-Channel Matching6

DC to 1 MHz logic signal
frequency
DC to 1 MHz logic signal
frequency

IDD2 (Q)

3 V/5 V Operation
10 Mbps (BRWZ Version Only)
VDD1 Supply Current
5 V/3 V Operation
3 V/5 V Operation
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
All Models
Input Currents

Test Conditions/Comments(VDD1 or(VDD1 or
VDD2) − 0.1 VDD2)(VDD1 or(VDD1 or
VDD2) − 0.4 VDD2) − 0.2
0.0
0.1
0.04
0.1
0.2
0.4

PW
tPHL, tPLH
PWD
tPSK
tPSKCD/OD

1
25

70

Rev. M | Page 8 of 22

V
VV

IOx = −20 μA, VIx = VIxH

V
V
V
V

IOx = −4 mA, VIx = VIxH
IOx = 20 μA, VIx = VIxLIOx = 400 μA, VIx = VIxLIOx = 4 mA, VIx = VIxL

1000 ns
CL = 15 pF, CMOS signal levels
Mbps CL = 15 pF, CMOS signal levels
100 nsCL = 15 pF, CMOS signal levels
40ns
CL = 15 pF, CMOS signal levels
50ns
CL = 15 pF, CMOS signal levels
50ns
CL = 15 pF, CMOS signal levels

Data SheetParameter
ADuM1410BRWZ/ADuM1411BRWZ/
ADuM1412BRWZ
Minimum Pulse Width2
Maximum Data Rate3
Propagation Delay4
Pulse Width Distortion, |tPLH − tPHL|4
Change vs. Temperature
Propagation Delay Skew5
Channel-to-Channel Matching,
Codirectional Channels6
Channel-to-Channel Matching,
Opposing-Directional Channels6
All Models
Output Rise/Fall Time (10% to 90%)
5 V/3 V Operation
3 V/5 V Operation
Common-Mode Transient Immunity at
Logic High Output 7
Common-Mode Transient Immunity at
Logic Low Output7
Refresh Rate
5 V/3 V Operation
3 V/5 V Operation
Input Enable Time 8
Input Disable Time8
Input Dynamic Supply Current
per Channel 9
5 V Operation

ADuM1410/ADuM1411/ADuM1412
Symbol

Min

Typ

PW

Test Conditions/Comments

tPSK

30

ns
CL = 15 pF, CMOS signal levels
Mbps CL = 15 pF, CMOS signal levelsns
CL = 15 pF, CMOS signal levelsns
CL = 15 pF, CMOS signal levels
ps/°C CL = 15 pF, CMOS signal levelsns
CL = 15 pF, CMOS signal levels

tPSKCD

5ns

CL = 15 pF, CMOS signal levels

tPSKOD

6ns

CL = 15 pF, CMOS signal levels

tPHL, tPLH
PWD

100
10
25

35

60
5

5

tR/tF

CL = 15 pF, CMOS signal levels
2.5
2.5

ns
ns

|CMH|

25

35

|CML|
fr

25

35

VIx = VDD1 or VDD2, VCM = 1000 V,
kV/µs transient magnitude = 800 V
VIx = 0 V, VCM = 1000 V, transient
kV/µs magnitude = 800 V

1.2
1.1
2.0
5.0

Mbps
Mbps
µs
VIA, VIB, VIC, VID = 0 V or VDD1µs
VIA, VIB, VIC, VID = 0 V or VDD1tENABLEtDISABLE
IDDI (D)0.12
3 V Operation
0.07
Output Dynamic Supply Current per
Channel95 V Operation

Max Unit

mA/
Mbps
mA/
Mbps

IDDO (D)0.04

3 V Operation
0.02

mA/
Mbps
mA/
Mbps

The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output loadpresent. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section.
See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 throughFigure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1410/ADuM1411/ADuM1412 channel configurations.
2
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4
tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay ismeasured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
6
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
7|CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. |CML| is the maximum common-mode voltage slew ratethat can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transientmagnitude is the range over which the common mode is slewed.
8
Input enable time is the duration from when VDISABLE is set low until the output states are guaranteed to match the input states in the absence of any input data logictransitions. If an input data logic transition within a given channel does occur within this time interval, the output of that channel reaches the correct state within themuch shorter duration as determined by the propagation delay specifications within this data sheet. Input disable time is the duration from when VDISABLE is set highuntil the output states are guaranteed to reach their programmed output levels, as determined by the CTRL2 logic state (see Table 14).
9
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for informationon per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
1Rev. M | Page 9 of 22

ADuM1410/ADuM1411/ADuM1412

Data Sheet

PACKAGE CHARACTERISTICS
Table 4.
Parameter
Resistance (Input to Output)1
Capacitance (Input to Output)1
Input Capacitance2
IC Junction to Case Thermal ResistanceSide 1
Side 2
1
2

Symbol
RI-O
CI-O
CI

Min

θJCI
θJCO

Typ
1012
2.2
4.0

Max

33
28

Unit
Ω
pF
pF

Test Conditions/Comments

°C/W
°C/W

Thermocouple located at center of package underside

f = 1 MHzThe device is considered a 2-terminal device; Pin 1 through Pin 8 are shorted together, and Pin 9 through Pin 16 are shorted together.
Input capacitance is from any input data pin to ground.

REGULATORY INFORMATIONThe ADuM1410/ADuM1411/ADuM1412 have been approved by the organizations listed in Table 5. See Table 10 and the Insulation Lifetime
section for recommended maximum working voltages for specific cross-isolation waveforms and insulation levels.
Table 5.
UL
Recognized Under
1577 Component
Recognition
Program1
Single Protection,
3750 V rms
Isolation
Voltage

File E214100
1

2

CSA
Approved under CSA
Component Acceptance
Notice 5A

CQC
Approved under
CQC11-471543-2012

VDE
Certified according to
DIN V VDE V 0884-10(VDE V 0884-10): 2006-122

TÜVApproved according toIEC 60950-1:2005 andEN 60950-1:2006

Basic insulation per
CSA 60950-1-03 andIEC 60950-1, 800 V rms(1131 V peak) maximum
working voltage
Reinforced insulation
per CSA 60950-1-03 andIEC 60950-1, 400 V rms(566 V peak) maximum
working voltage
File 205078

Basic insulation per
GB4943.1-2011, 600 V rms(848 V peak) maximum
working voltage, tropicalclimate, altitude ≤ 5000 m
Reinforced insulation per
GB4943.1-2011, 380 V rms(537 V peak) maximum
working voltage, tropicalclimate, altitude ≤ 5000 m
File CQC14001108689

Reinforced insulation,
560 V peak

3000 V rms reinforced isolation
at a 400 V rms working voltage,
3000 V rms basic isolation at a
600 V rms working voltage

File 2471900-4880-0001

Certificate B 10 03 56232 006

In accordance with UL 1577, each ADuM1410/ADuM1411/ADuM1412 is proof tested by applying an insulation test voltage ≥3000 V rms for 1 sec (current leakage
detection limit = 5 μA).
In accordance with DIN V VDE V 0884-10, each ADuM1410/ADuM1411/ADuM1412 is proof tested by applying an insulation test voltage ≥1050 V peak for 1 second(partial discharge detection limit = 5 pC). The asterisk (*) marked on the component designates DIN V VDE V 0884-10 approval.

INSULATION AND SAFETY RELATED SPECIFICATIONS
Table 6.
Parameter
Rated Dielectric Insulation Voltage
Minimum External Tracking (Creepage)

SymbolL(I02)

Value
3750
7.71

Unit
V rms
mm minMinimum External Air Gap (Clearance)

L(I01)

7.7

mm minMinimum Clearance in the Plane of the
Printed Circuit Board (PCB Clearance)
Minimum Internal Gap (Internal Clearance)
Tracking Resistance (Comparative Tracking
Index)
Isolation Group

L(PCB)

8.12

mm min

CTI

0.017
>400

mm minV

1
2

II

Conditions
1-minute duration
Measured from input terminals to output terminals, shortest
distance path along package body
Measured from input terminals to output terminals, shortest
distance through air
Measured from input terminals to output terminals, shortest
distance through air, line of sight, in the PCB mounting plane
Insulation distance through insulation
DIN IEC 112/VDE 0303 Part 1
Material Group (DIN VDE 0110, 1/89, Table 1)

Clearance and creepage measured by VDE is >8 mm for SOIC wide packages.
This value is for information only, to aid in PCB design. Package clearance is identical to creepage as specified in L(I02).

Rev. M | Page 10 of 22

Data Sheet

ADuM1410/ADuM1411/ADuM1412

DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 INSULATION CHARACTERISTICS
These isolators are suitable for reinforced electrical isolation within the safety limit data only. Maintenance of the safety data is ensured byprotective circuits. The asterisk (*) marked on packages denotes DIN V VDE V 0884-10 approval.
Table 7.
Description
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms
For Rated Mains Voltage ≤ 300 V rms
For Rated Mains Voltage ≤ 400 V rms
Climatic Classification
Pollution Degree per DIN VDE 0110, Table 1
Maximum Working Insulation Voltage
Input-to-Output Test Voltage, Method B1
Input-to-Output Test Voltage, Method A
After Environmental Tests Subgroup 1
After Input and/or Safety Test Subgroup 2
and Subgroup 3
Highest Allowable Overvoltage
Safety Limiting Values
Case Temperature
Side 1 Current
Side 2 Current
Insulation Resistance at TS

Conditions

VIORM × 1.875 = VPR, 100% production test, tm = 1 sec,
partial discharge < 5 pC
VIORM × 1.6 = VPR, tm = 60 sec, partial discharge < 5 pC

Characteristic

Unit

VIORM
VPR

I to IV
I to IIII to II
40/105/21
2
560
1050

V peakV peak896672

V peakV peakVTR

4000

V peak

TS
IS1
IS2
RS

150
265
335
>109

°C
mA
mA
Ω

VPR

VIORM × 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC
Transient overvoltage, tTR = 10 seconds
Maximum value allowed in the event of a failure;see Figure 4

VIO = 500 V

RECOMMENDED OPERATING CONDITIONS

350

Table 8.

300

Parameter
Operating Temperature
Supply Voltages1
Input Signal Rise and Fall Times

250
SIDE #2

200

150

1

SIDE #1

100
50
0
0

50

100
150
CASE TEMPERATURE (°C)

200

SymbolTA
VDD1, VDD2

Min
−40
2.7

Max
+105
5.5
1.0

Unit
°C
V
ms

All voltages are relative to their respective ground. See the DC Correctness
and Magnetic Field Immunity section for information on immunity to external
magnetic fields.

06580-007

SAFETY-LIMITING CURRENT (mA)

SymbolFigure 4. Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN V VDE V 0884-10

Rev. M | Page 11 of 22

ADuM1410/ADuM1411/ADuM1412

Data Sheet

ABSOLUTE MAXIMUM RATINGSTA = 25°C, unless otherwise noted.

Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at theseor any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.

Table 9.
Parameter
Storage Temperature (TST) Range
Ambient Operating Temperature(TA) Range
Supply Voltages (VDD1, VDD2)1
Input Voltages (VIA, VIB, VIC, VID, VCTRL1,VCTRL2, VDISABLE)1, 2
Output Voltages (VOA, VOB, VOC, VOD)1, 2
Average Output Current per Pin3
Side 1 (IO1)
Side 2 (IO2)
Common-Mode Transients4

Rating−65°C to +150°C−40°C to +105°C−0.5 V to +7.0 V−0.5 V to VDDI + 0.5 V

ESD CAUTION−0.5 V to VDDO + 0.5 V−18 mA to +18 mA−22 mA to +22 mA−100 kV/μs to +100 kV/μs

All voltages are relative to their respective ground.
VDDI and VDDO refer to the supply voltages on the input and output sides of agiven channel, respectively. See the PC Board Layout section.
3
See Figure 4 for maximum rated current values for various temperatures.
4
Refers to common-mode transients across the insulation barrier. Commonmode transients exceeding the absolute maximum ratings may cause
latch-up or permanent damage.
1
2

Table 10. Maximum Continuous Working Voltage 1
Parameter
AC Voltage, Bipolar Waveform
AC Voltage, Unipolar Waveform
Basic Insulation
Reinforced Insulation
DC Voltage
Basic Insulation
Reinforced Insulation
1

Max
565

Unit
V peakConstraint
50-year minimum lifetime

1131
560

V peakV peakMaximum approved working voltage per IEC 60950-1
Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10

1131
560

V peakV peakMaximum approved working voltage per IEC 60950-1
Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10

Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details.

Rev. M | Page 12 of 22

Data Sheet

ADuM1410/ADuM1411/ADuM1412

VDD1 1

16

VDD2

GND1* 2

15

GND2*

VIA 3

ADuM1410

14

VOA

VIB 4

TOP VIEW(Not to Scale)

13

VOB

12

VOC

VID 6

11

VOD

DISABLE 7

10

CTRL2

GND1* 8

9

GND2*

VIC 5

*PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED. CONNECTING BOTH
TO GND1 IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLYCONNECTED. CONNECTING BOTH TO GND2 IS RECOMMENDED.

06580-004

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

Figure 5. ADuM1410 Pin Configuration

Table 11. ADuM1410 Pin Function Descriptions
Pin No.
12Mnemonic
VDD1
GND1

3
4
5
6
7

VIA
VIB
VIC
VID
DISABLE

8

GND1

9

GND2

10

CTRL2

11
12
13
14
15

VOD
VOC
VOB
VOA
GND2

16

VDD2

Description
Supply Voltage for Isolator Side 1 (2.7 V to 5.5 V).
Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND1 isrecommended.
Logic Input A.
Logic Input B.
Logic Input C.
Logic Input D.
Input Disable. Disables the isolator inputs and halts the dc refresh circuits. Outputs take on the logic state
determined by CTRL2.
Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND1 isrecommended.
Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND2 isrecommended.
Default Output Control. Controls the logic state the outputs assume when the input power is off. VOA, VOB, VOC, and
VOD outputs are high when CTRL2 is high or disconnected and VDD1 is off. VOA, VOB, VOC, and VOD outputs are low when
CTRL2 is low and VDD1 is off. When VDD1 power is on, this pin has no effect.
Logic Output D.
Logic Output C.
Logic Output B.
Logic Output A.
Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND2 isrecommended.
Supply Voltage for Isolator Side 2 (2.7 V to 5.5 V).

Rev. M | Page 13 of 22

ADuM1410/ADuM1411/ADuM1412

Data Sheet
16 VDD2

VDD1 115 GND2*

VIA 3

ADuM1411

VIB 4

TOP VIEW(Not to Scale)

VIC 5
VOD 6

14 VOA
13 VOB
12 VOC
11 VID

CTRL1 7

10 CTRL2

GND1* 89GND2**PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED. CONNECTING BOTH
TO GND1 IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLYCONNECTED. CONNECTING BOTH TO GND2 IS RECOMMENDED.

06580-005

GND1* 2

Figure 6. ADuM1411 Pin Configuration

Table 12. ADuM1411 Pin Function Descriptions
Pin No.
12Mnemonic
VDD1
GND1

3
4
5
6
7

VIA
VIB
VIC
VOD
CTRL1

8

GND1

9

GND2

10

CTRL2

11
12
13
14
15

VID
VOC
VOB
VOA
GND2

16

VDD2

Description
Supply Voltage for Isolator Side 1 (2.7 V to 5.5 V).
Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND1 isrecommended.
Logic Input A.
Logic Input B.
Logic Input C.
Logic Output D.
Default Output Control. Controls the logic state the outputs assume when the input power is off. VOD output is highwhen CTRL1 is high or disconnected and VDD2 is off. VOD output is low when CTRL1 is low and VDD2 is off. When VDD2
power is on, this pin has no effect.
Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND1 isrecommended.
Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND2 isrecommended.
Default Output Control. Controls the logic state the outputs assume when the input power is off. VOA, VOB, and VOC
outputs are high when CTRL2 is high or disconnected and VDD1 is off. VOA, VOB, and VOC outputs are low when CTRL2 is
low and VDD1 is off. When VDD1 power is on, this pin has no effect.
Logic Input D.
Logic Output C.
Logic Output B.
Logic Output A.
Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND2 isrecommended.
Supply Voltage for Isolator Side 2 (2.7 V to 5.5 V).

Rev. M | Page 14 of 22

ADuM1410/ADuM1411/ADuM1412
VDD1 1

16

VDD2

GND1* 2

15

GND2*

VIA 3

ADuM1412

14

VOA

VIB 4

TOP VIEW(Not to Scale)

13

VOB

12

VIC

VOD 6

11

VID

CTRL1 710CTRL2

GND1* 8

9

GND2*

VOC 5

*PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED. CONNECTING BOTH
TO GND1 IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLYCONNECTED. CONNECTING BOTH TO GND2 IS RECOMMENDED.

06580-006

Data Sheet

Figure 7. ADuM1412 Pin Configuration

Table 13. ADuM1412 Pin Function Descriptions
Pin No.
12Mnemonic
VDD1
GND1

3
4
5
6
7

VIA
VIB
VOC
VOD
CTRL1

8

GND1

9

GND2

10

CTRL2

11
12
13
14
15

VID
VIC
VOB
VOA
GND2

16

VDD2

Description
Supply Voltage for Isolator Side 1 (2.7 V to 5.5 V).
Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND1 isrecommended.
Logic Input A.
Logic Input B.
Logic Output C.
Logic Output D.
Default Output Control. Controls the logic state the outputs assume when the input power is off. VOC and VOD
outputs are high when CTRL1 is high or disconnected and VDD2 is off. VOC and VOD outputs are low when CTRL1 is low
and VDD2 is off. When VDD2 power is on, this pin has no effect.
Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND1 isrecommended.
Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND2 isrecommended.
Default Output Control. Controls the logic state the outputs assume when the input power is off. VOA and VOB
outputs are high when CTRL2 is high or disconnected and VDD1 is off. VOA and VOB outputs are low when CTRL2 is low
and VDD1 is off. When VDD1 power is on, this pin has no effect.
Logic Input D.
Logic Input C.
Logic Output B.
Logic Output A.
Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND2 isrecommended.
Supply Voltage for Isolator Side 2 (2.7 V to 5.5 V).

Rev. M | Page 15 of 22

ADuM1410/ADuM1411/ADuM1412

Data Sheet

Table 14. Truth Table (Positive Logic)
VIx
Input 1H

CTRLX
Input 2
X

L

X

X

H or
NC
L

X

VDISABLE
State 3
L or
NC
L or
NC
H

VDDI
State 4
Powered

VDDOState 5
PoweredVOx
Output1
H

Description
Normal operation, data is high.

PoweredPoweredL

Normal operation, data is low.

X

PoweredH

H

X

PoweredL

Inputs disabled. Outputs are in the default state as determinedby CTRLX.
Inputs disabled. Outputs are in the default state as determined by
CTRLX.
Input unpowered. Outputs are in the default state as determinedby CTRLX.
Outputs return to input state within 1 µs of VDDI power restoration.
See the pin function descriptions (Table 11, Table 12, and Table 13) for
more details.
Input unpowered. Outputs are in the default state as determinedby CTRLX.
Outputs return to input state within 1 µs of VDDI power restoration.
See the pin function descriptions (Table 11, Table 12, and Table 13) for
more details.
Output unpowered. Output pins are in high impedance state.
Outputs return to input state within 1 µs of VDDO power restoration.
See the pin function descriptions (Table 11, Table 12, and Table 13) for
more details.

X

H or
NC

X

UnpoweredPowered

H

X

L

X

UnpoweredPowered

L

X

X

X

PoweredUnpoweredZ

VIx and VOx refer to the input and output signals of a given channel (A, B, C, or D).
CTRLX refers to the default output control signal on the input side of a given channel (A, B, C, or D).
Available only on the ADuM1410.
4
VDDI refers to the power supply on the input side of a given channel (A, B, C, or D).
5
VDDO refers to the power supply on the output side of a given channel (A, B, C, or D).
1
2
3

Rev. M | Page 16 of 22

Data Sheet

ADuM1410/ADuM1411/ADuM1412

TYPICAL PERFORMANCE CHARACTERISTICS
10

2.0

CURRENT (mA)

CURRENT/CHANNEL (mA)

8
1.5

5V
1.0

3V

6

5V

4

0.5
2

0

2

4
6
DATA RATE (Mbps)

8

10

0

06580-008

00Figure 8. Typical Supply Current per Input Channel vs. Data Ratefor 5 V and 3 V Operation

2

4
6
DATA RATE (Mbps)

81006580-011

3V

Figure 11. Typical ADuM1410 VDD1 Supply Current vs. Data Ratefor 5 V and 3 V Operation
10

1.0
0.9

8

0.7
0.6

CURRENT (mA)

5V

0.5
0.4

6

4

0.3
5V

3V

0.2

2

0.1

3V
0

2

4
6
DATA RATE (Mbps)

8

10

0

06580-009

00Figure 9. Typical Supply Current per Output Channel vs. Data Ratefor 5 V and 3 V Operation (No Output Load)

2

4
6
DATA RATE (Mbps)

81006580-012

CURRENT/CHANNEL (mA)

0.8

Figure 12. Typical ADuM1410 VDD2 Supply Current vs. Data Ratefor 5 V and 3 V Operation

1.4

10

1.2

CURRENT (mA)

0.8
5V
0.6

6

4
5V

0.4
3V

2

0.2
0
0

2

4
6
DATA RATE (Mbps)

81006580-010

3V

Figure 10. Typical Supply Current per Output Channel vs. Data Ratefor 5 V and 3 V Operation (15 pF Output Load)Rev. M | Page 17 of 22

0
0

2

4
6
DATA RATE (Mbps)

810Figure 13. Typical ADuM1411 VDD1 Supply Current vs. Data Ratefor 5 V and 3 V Operation

06580-013

CURRENT/CHANNEL (mA)8
1.0

Data Sheet
10

8

8

CURRENT (mA)

10

6

4

6

4
5V

5V
2

2
3V

0
0

2

4
6
DATA RATE (Mbps)

810Figure 14. Typical ADuM1411 VDD2 Supply Current vs. Data Ratefor 5 V and 3 V Operation

0
0

2

4
6
DATA RATE (Mbps)

81006580-015

3V06580-014

CURRENT (mA)

ADuM1410/ADuM1411/ADuM1412

Figure 15. Typical ADuM1412 VDD1 or VDD2 Supply Current vs. Data Ratefor 5 V and 3 V OperationRev. M | Page 18 of 22

Data Sheet

ADuM1410/ADuM1411/ADuM1412

APPLICATIONS INFORMATION
DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY

The ADuM1410/ADuM1411/ADuM1412 digital isolators
require no external interface circuitry for the logic interfaces.
Power supply bypassing is strongly recommended at the input
and output supply pins (see Figure 16). Bypass capacitors aremost conveniently connected between Pin 1 and Pin 2 for VDD1,
and between Pin 15 and Pin 16 for VDD2. The capacitor value
should be between 0.01 µF and 0.1 µF. The total lead length
between both ends of the capacitor and the input power supply
pin should not exceed 20 mm. Bypassing between Pin 1 and Pin 8
and between Pin 9 and Pin 16 should also be considered unless
both ground pins on each package are connected together close to
the package.

Positive and negative logic transitions at the isolator input
cause narrow (~1 ns) pulses to be sent to the decoder using thetransformer. The decoder is bistable and is, therefore, either set
or reset by the pulses, indicating input logic transitions. In theabsence of logic transitions at the input for more than ~1 µs, aperiodic set of refresh pulses indicative of the correct input stateis sent to ensure dc correctness at the output. If the decoder
receives no internal pulses of more than approximately 5 µs, theinput side is assumed to be unpowered or nonfunctional, in
which case the isolator output is forced to a default state (seeTable 14) by the watchdog timer circuit.

VDD1
GND1
VIA
VIB
VIC
VID
DISABLE
GND1

VDD2
GND2
VOA
VOB
VOC
VOD
CTRL2
GND2

ADuM1410

06580-016

PC BOARD LAYOUT

Figure 16. Recommended Printed Circuit Board Layout

In applications involving high common-mode transients, it isimportant to minimize board coupling across the isolation barrier.
Furthermore, users should design the board layout so that any
coupling that does occur equally affects all pins on a given
component side. Failure to ensure this can cause voltage
differentials between pins exceeding the absolute maximum
ratings of the device, thereby leading to latch-up or permanent
damage. See the AN-1109 Application Note for board layout
guidelines.

PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component. The input-tooutput propagation delay time for a high-to-low transition may
differ from the propagation delay time of a low-to-high transition.
INPUT (VIx)50%

The magnetic field immunity of the ADuM1410/ADuM1411/
ADuM1412 is determined by the changing magnetic field, which
induces a voltage in the transformer’s receiving coil large enoughto either falsely set or reset the decoder. The following analysis
defines the conditions under which this can occur. The 3 V
operating condition of the ADuM1410/ADuM1411/ADuM1412
is examined because it represents the most susceptible mode ofoperation.
The pulses at the transformer output have an amplitude greaterthan 1.0 V. The decoder has a sensing threshold at about 0.5 V, thus
establishing a 0.5 V margin in which induced voltages can be
tolerated. The voltage induced across the receiving coil is given by
V = (−dβ/dt) ∑ π rn2; n = 1, 2, … , N
where:β is magnetic flux density (gauss).
rn is the radius of the nth turn in the receiving coil (cm).
N is the number of turns in the receiving coil.
Given the geometry of the receiving coil in the ADuM1410/
ADuM1411/ADuM1412 and an imposed requirement that theinduced voltage be, at most, 50% of the 0.5 V margin at the
decoder, a maximum allowable magnetic field at a given frequency
can be calculated. The result is shown in Figure 18.

50%

Figure 17. Propagation Delay Parameters

Pulse width distortion is the maximum difference between thesetwo propagation delay values and an indication of how accurately
the timing of the input signal is preserved.
Channel-to-channel matching refers to the maximum amountthe propagation delay differs between channels within a single
ADuM1410/ADuM1411/ADuM1412 component.
Propagation delay skew refers to the maximum amount the
propagation delay differs between multiple ADuM1410/
ADuM1411/ADuM1412 components operating under the same
conditions.

Rev. M | Page 19 of 22

10

1

0.1

0.01

0.001
1k

10k
100k
1M
10M
MAGNETIC FIELD FREQUENCY (Hz)

100M

Figure 18. Maximum Allowable External Magnetic Flux Density

06580-018

06580-017

OUTPUT (VOx)tPHL

MAXIMUM ALLOWABLE MAGNETIC FLUXDENSITY (kgauss)

100

tPLH

ADuM1410/ADuM1411/ADuM1412

Data Sheet

For example, at a magnetic field frequency of 1 MHz, themaximum allowable magnetic field of 0.2 kgauss induces avoltage of 0.25 V at the receiving coil. This is about 50% of thesensing threshold and does not cause a faulty output transition.
Similarly, if such an event occurred during a transmitted pulse(and had the worst-case polarity), it would reduce the received
pulse from >1.0 V to 0.75 V, still well above the 0.5 V sensing
threshold of the decoder.
The preceding magnetic flux density values correspond to
specific current magnitudes at given distances from theADuM1410/ADuM1411/ADuM1412 transformers. Figure 19
shows these allowable current magnitudes as a function of
frequency for selected distances. As shown, the ADuM1410/
ADuM1411/ADuM1412 is extremely immune and can be affected
only by extremely large currents operated at high frequency very
close to the component. For the 1 MHz example noted previously, a
0.5 kA current would have to be placed 5 mm away from theADuM1410/ADuM1411/ADuM1412 to affect the operation of
the component.
DISTANCE = 1m
100

10
DISTANCE = 100mm
1
DISTANCE = 5mm
0.1

0.01
1k

10k

100k

1M

10M

100M

MAGNETIC FIELD FREQUENCY (Hz)06580-019

MAXIMUM ALLOWABLE CURRENT (kA)

1000

Figure 19. Maximum Allowable Current for Various
Current-to-ADuM1410/ADuM1411/ADuM1412 Spacings

Note that at combinations of strong magnetic field and highfrequency, any loops formed by printed circuit board traces can
induce error voltages sufficiently large enough to trigger thethresholds of succeeding circuitry. Care should be taken in thelayout of such traces to avoid this possibility.

POWER CONSUMPTION
The supply current at a given channel of the ADuM1410/
ADuM1411/ADuM1412 isolators is a function of the supply
voltage, the data rate of the channel, and the output load of thechannel.
For each input channel, the supply current is given by
IDDI = IDDI (Q)f ≤ 0.5 fr

IDDI = IDDI (D) × (2f − fr) + IDDI (Q)f > 0.5 fr

For each output channel, the supply current is given by
IDDO = IDDO (Q)f ≤ 0.5 fr

IDDO = (IDDO (D) + (0.5 × 10 ) × CL × VDDO) × (2f − fr) + IDDO (Q)f > 0.5 fr−3where:
IDDI (D), IDDO (D) are the input and output dynamic supply currents
per channel (mA/Mbps).
CL is the output load capacitance (pF).
VDDO is the output supply voltage (V).
f is the input logic signal frequency (MHz); it is half the input
data rate, expressed in units of Mbps.
fr is the input stage refresh rate (Mbps).
IDDI (Q), IDDO (Q) are the specified input and output quiescentsupply currents (mA).
To calculate the total VDD1 and VDD2 supply current, the supply
currents for each input and output channel corresponding to
VDD1 and VDD2 are calculated and totaled. Figure 8 and Figure 9
show per-channel supply currents as a function of data rate foran unloaded output condition. Figure 10 shows the per-channel
supply current as a function of data rate for a 15 pF output
condition. Figure 11 through Figure 15 show the total VDD1 andVDD2 supply current as a function of data rate for ADuM1410/
ADuM1411/ADuM1412 channel configurations.

INSULATION LIFETIME
All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of
insulation degradation is dependent on the characteristics of thevoltage waveform applied across the insulation. In addition to
the testing performed by the regulatory agencies, Analog
Devices carries out an extensive set of evaluations to determine
the lifetime of the insulation structure within the ADuM1410/
ADuM1411/ADuM1412.

Rev. M | Page 20 of 22

Data Sheet

ADuM1410/ADuM1411/ADuM1412
Note that the voltage presented in Figure 21 is shown as sinusoidal
for illustration purposes only. It is meant to represent any voltage
waveform varying between 0 V and some limiting value. The
limiting value can be positive or negative, but the voltage cannot
cross 0 V.
RATED PEAK VOLTAGE
06580-020

Analog Devices performs accelerated life testing using voltage
levels higher than the rated continuous working voltage.
Acceleration factors for several operating conditions are
determined. These factors allow calculation of the time to
failure at the actual working voltage. The values shown in
Table 10 summarize the peak voltage for 50 years of service life
for a bipolar ac operating condition and the maximum
CSA/VDE approved working voltages. In many cases, theapproved working voltage is higher than 50-year service life
voltage. Operation at these high working voltages can lead toshortened insulation life in some cases.

0V

Figure 20. Bipolar AC Waveform

RATED PEAK VOLTAGE

Bipolar ac voltage is the most stringent environment. The goalof a 50-year operating lifetime under the ac bipolar condition
determines the Analog Devices recommended maximum
working voltage.

RATED PEAK VOLTAGE

In the case of unipolar ac or dc voltage, the stress on the insulation
is significantly lower. This allows operation at higher working
voltages while still achieving a 50-year service life. The working
voltages listed in Table 10 can be applied while maintaining the
50-year minimum lifetime provided the voltage conforms toeither the unipolar ac or dc voltage case. Any cross-insulation
voltage waveform that does not conform to Figure 21 or Figure 22
should be treated as a bipolar ac waveform, and its peak voltage
should be limited to the 50-year lifetime voltage value listed inTable 10.

Rev. M | Page 21 of 22

06580-021

The insulation lifetime of the ADuM1410/ADuM1411/
ADuM1412 depends on the voltage waveform type imposed
across the isolation barrier. The iCoupler insulation structure
degrades at different rates depending on whether the waveform
is bipolar ac, unipolar ac, or dc. Figure 20, Figure 21, and Figure 22
illustrate these different isolation voltage waveforms.

0V

06580-022

Figure 21. Unipolar AC Waveform

0V

Figure 22. DC WaveformADuM1410/ADuM1411/ADuM1412

Data SheetOUTLINE DIMENSIONS
10.50 (0.4134)
10.10 (0.3976)

9167.60 (0.2992)
7.40 (0.2913)
8

1.27 (0.0500)
BSC
0.30 (0.0118)
0.10 (0.0039)
COPLANARITY
0.10

0.51 (0.0201)
0.31 (0.0122)

10.65 (0.4193)
10.00 (0.3937)

0.75 (0.0295)
45°
0.25 (0.0098)

2.65 (0.1043)
2.35 (0.0925)

SEATING
PLANE

8°
0°
0.33 (0.0130)
0.20 (0.0079)

COMPLIANT TO JEDEC STANDARDS MS-013-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FORREFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

1.27 (0.0500)
0.40 (0.0157)

03-27-2007-B

1

Figure 23. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body (RW-16)
Dimensions shown in millimeters and (inches)

ORDERING GUIDE
Number Number
Maximum
Maximumof Inputs, of Inputs, Maximum Propagation Pulse Width Temperature
Package
Model 1
Package Description
VDD1 Side VDD2 Side Data Rate Delay, 5 V
Distortion Range
OptionADuM1410ARWZ
4
0
1 Mbps
100 ns
40 ns−40°C to +105°C 16-Lead SOIC_W
RW-16
ADuM1410ARWZ-RL 4
0
1 Mbps
100 ns
40 ns−40°C to +105°C 16-Lead SOIC_W, 13” Tape and Reel RW-16
ADuM1410BRWZ
4
0
10 Mbps
50 ns
5 ns−40°C to +105°C 16-Lead SOIC_W
RW-16
ADuM1410BRWZ-RL 4
0
10 Mbps
50 ns
5 ns−40°C to +105°C 16-Lead SOIC_W, 13” Tape and Reel RW-16
ADuM1411ARWZ
3
1
1 Mbps
100 ns
40 ns−40°C to +105°C 16-Lead SOIC_W
RW-16
ADuM1411ARWZ-RL 3
1
1 Mbps
100 ns
40 ns−40°C to +105°C 16-Lead SOIC_W, 13” Tape and Reel RW-16
ADuM1411BRWZ
3
1
10 Mbps
50 ns
5 ns−40°C to +105°C 16-Lead SOIC_W
RW-16
ADuM1411BRWZ-RL 3
1
10 Mbps
50 ns
5 ns−40°C to +105°C 16-Lead SOIC_W, 13” Tape and Reel RW-16
ADuM1412ARWZ
2
2
1 Mbps
100 ns
40 ns−40°C to +105°C 16-Lead SOIC_W
RW-16
ADuM1412ARWZ-RL 2
2
1 Mbps
100 ns
40 ns−40°C to +105°C 16-Lead SOIC_W, 13” Tape and Reel RW-16
ADuM1412BRWZ
2
2
10 Mbps
50 ns
5 ns−40°C to +105°C 16-Lead SOIC_W
RW-16
ADuM1412BRWZ-RL 2
2
10 Mbps
50 ns
5 ns−40°C to +105°C 16-Lead SOIC_W, 13” Tape and Reel RW-16
1

Z = RoHS Compliant Part.

©2005–2015 Analog Devices, Inc. All rights reserved. Trademarks andregistered trademarks are the property of their respective owners.
D06580-0-8/15(M)Rev. M | Page 22 of 22