Nuclear Instruments and Methods in Physics Research A ∎ (∎∎∎∎) ∎∎∎–∎∎∎

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Nuclear Instruments and Methods inPhysics Research A
journal homepage: www.elsevier.com/locate/nima

Development of n þ -in-p planar pixel sensors for extremely highradiation environments, designed to retain high efﬁciency after
irradiation
Y. Unno b,n, S. Kamada a, K. Yamamura a, Y. Ikegami b, K. Nakamura b, Y. Takubo b,
R. Takashima c, J. Tojo d, T. Kono e, K. Hanagaki f,b, K. Yajima f, Y. Yamauchi f, M. Hirose g,
Y. Homma g, O. Jinnouchi g, K. Kimura g, K. Motohashi g, S. Sato g, H. Sawai g, K. Todome g,
D. Yamaguchi g, K. Hara h,i, Kz. Sato h, Kj. Sato h,i, M. Hagihara h, S. Iwabuchi haSolid State Div., Hamamatsu Photonics K.K., 1126-1, Ichino-cho, Higashi-ku, Hamamatsu-shi, Shizuoka 435-8558, Japan
Institute of Particle and Nuclear Study, KEK, Oho 1-1, Tsukuba, Ibaraki 305-0801, Japanc
Department of Science Education, Kyoto University of Education, Kyoto 612-8522, Japand
Department of Physics, Faculty of Science, Kyushu University, 744 Motooka, Nishi-ku, Fukuoka 819-0395, Japane
Ochadai Academic Production, Ochanomizu University, 2-1-1, Otsuka, Bunkyo-ku, Tokyo, 112-8610, Japanf
Department of Physics, Osaka University, Machikaneyama-cho 1-1, Toyonaka-shi, Osaka 560-0043, Japang
Institute of Science and Engineering, Tokyo Institute of Technology, Ookayama 2-12-1, Meguro-ku, Tokyo 152-8551, JapanhInstitute of Pure and Applied Sciences, University of Tsukuba, Tsukuba, Ibaraki 305-9751, Japani
Center for Integrated Research in Fundamental Science and Engineering, University of Tsukuba, Tsukuba, Ibaraki 305-8571, Japanb

art ic l e i nf o

a b s t r a c t

Article history:
Received 9 December 2015
Received in revised form
11 April 2016
Accepted 13 April 2016

We have developed n þ -in-p pixel sensors to obtain highly radiation tolerant sensors for extremely highradiation environments such as those found at the high-luminosity LHC. We have designed novel pixel
structures to eliminate the sources of efﬁciency loss under the bias rails after irradiation by removing thebias rail out of the boundary region and routing the bias resistors inside the area of the pixel electrodes.
After irradiation by protons with the ﬂuence of approximately 3 × 1015 neq/cm2, the pixel structure withthe polysilicon bias resistor and the bias rails removed far away from the boundary shows an efﬁciency
loss of <0.5% per pixel at the boundary region, which is as efﬁcient as the pixel structure without abiasing structure. The pixel structure with the bias rails at the boundary and the widened p-stop's underneath the bias rail also exhibits an improved loss of approximately 1% per pixel at the boundary
region. We have elucidated the physical mechanisms behind the efﬁciency loss under the bias rail with
TCAD simulations. The efﬁciency loss is due to the interplay of the bias rail acting as a charge collecting
electrode with the region of low electric ﬁeld in the silicon near the surface at the boundary. The region
acts as a “shield” for the electrode. After irradiation, the strong applied electric ﬁeld nearly eliminates theregion. The TCAD simulations have shown that wide p-stop and large Si–SiO2 interface charge (inversion
layer, speciﬁcally) act to shield the weighting potential. The pixel sensor of the old design irradiated by γrays at 2.4 MGy is conﬁrmed to exhibit only a slight efﬁciency loss at the boundary.
& 2016 Elsevier B.V. All rights reserved.

Keywords:
n-in-pp-type
Pixel
SiliconRadiation damage
HL-LHC

1. Introduction
We have developed radiation-tolerant, planar-process, position-sensitive, silicon sensors in p-type 6-inch silicon wafers forapplications in extremely high radiation environments [1–3]
where radiation damage is generated by charged and neutral
particles passing through the silicon sensors. Since the silicon bulknCorresponding author.
E-mail address: yoshinobu.unno@kek.jp (Y. Unno).

stays as p-type after irradiation, the p-type sensor requires lithographic processing only in the p–n junction side, simplifying the
fabrication and leading to low device cost. Reading the signals out
from the n-side enables the operation of the sensor withoutcompletely depleting the bulk and makes the sensor highly radiation tolerant. The planar silicon fabrication process is well established in the industry and is a cost-effective solution for large
volume device production.
Extremely high radiation environments are found in the large
hadron collider (LHC) [4]. The LHC accelerator complex is planned
to be upgraded to High Luminosity LHC (HL-LHC) [5] to reach a

http://dx.doi.org/10.1016/j.nima.2016.04.039
0168-9002/& 2016 Elsevier B.V. All rights reserved.

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2

(a)

(b)

(c)

Pixel
implant
Alelectrode

Bias rail
(Al)

Wide
p-stopp-stopBias resistor(PolySi)
Implant (n+)

Bias rail(PolySi)

Implant (p+)

Al metal

PolySiFig. 1. Pixel structures: (a) old structure in wafer layout #2, (b) Type 10 and (c) Type 13 in wafer layout #4 .

8530±20(µm)

10540±20

FE-I3 sensor

FE-I4 sensor

Fig. 2. Wafer layout #4 in 6-inch wafer, with 28 of ATLAS FE-I4 singles and 20 of FE-I3 singles of pixel sensors. Each FE-I4 and FE-I3 pixel sensor is 18.54 × 20.93 and10.54 × 8.53 mm2 in chip size, with a 336  80 and 160  18 matrix of 50  250 and 50  400 μm2 pixels, respectively, with unique pixel structure per sensor.

higher collision rate ( 5 × 1034 cm−2s−1 with “luminosity leveling”)
and consequently obtain an increase of one order in magnitude in
the number of accumulated events (3000 fb  1). The upgrade isscheduled during the LHC shutdown during the years 2024–2026.
Our study primarily aims to develop a planar pixel sensor for the
ATLAS detector, which is a general-purpose detector at a collision

point in the LHC ring [6], that will be upgraded for the HL-LHC [7].
Considering a safety factor of 2, the sensor must cope with a radiation speciﬁed: the accumulated ﬂow of particles (“ﬂuence”) ofapproximately 2 × 1016 1 MeV -neutrons equivalent (neq )/cm2 and3 × 1015 neq /cm2 at a radius of 4 cm for the inner pixel layers and at
15 cm for the outer pixel layers, respectively [8].

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Pixel
electrode(Al metal)

Table 1
Speciﬁcations of wafer layout #4 of n þ -in-p pixel
sensors.
Silicon wafer diameter
Wafer type
Crystal orientation
Resistivity
Thickness
ThinnedNumber FE-I4 sensors
Number FE-I3 sensors

6 inch (150 mm)
p-type, ﬂoat zone (FZ)〈100〉
3–7 kΩ cm
320 μm
150 μm28
20

3

Bias rail(Al metal)x7x9 wEx1
wEx2

x11
wEx1

x12
wEx1

x0

y3
y2
y1 y0

tAlu
tSio1
tPsub

y4

Pixel
implant (n+)

x8
wEx1 x10
wEx2

wNsub
x1

wGap
x3

wPsub
x5

tNsub

y5

wGap
x6

tSio2

wNsub
x4

x2

p-stop (p+)

1.1
15Type10 proton irrad. 4.2x10

Efficiency / 10 µm

1.05

Silicon bulk (p)2

neq /cm1
0.95

Backplane implant (p+)

0.9

y6

0.85

y7

tPback( ) : material, "+": density higher than Silicon bulk.

100 V
200 V
300 V
400 V

0.8
0.75

Fig. 5. TCAD 2D geometry of the pixel boundary region with the bias rail.

0.7
0

100

200

300

400

500

Coordinate in longer pixel side (µm)
Fig. 3. Efﬁciency mapping over two pixel regions projected on the long pixel side.
Pixel boundaries of the bias rail side and the no bias rail side are at 125 and 375 μm,
respectively.

0.03
15

proton (p) 3x10
γ (g) 2.4 MGy

0.025

Efficiency loss / pixel

tSi

0.02
0.015

Type2-BR p
Type2-NB p
Type12-BR p
Type12-NB p
Type8-BR g
Type8-NB g
Type13-BR p
Type19 p

Table 2
Parameters before and after irradiation in TCAD simulations.
Parameter

Non-irrad. Irrad.

Fluence ( neq/cm2 )0

3 × 1015

Effective space charge concentration (p-type), Neff(cm  3)Full depletion voltage, Vdep (V)Applied bias voltage, Vop (V)Leakage current, Ileak (a.u.)
Surface density of interface charge, Qf (cm  2)

2.6 × 1012

2.5 × 1013

44
100
1

430
430
∼103

1 × 1010

1 × 1012(a.u: arbitrary unit)
Table 3
Geometry parameters used in TCAD simulations.
Parameter

Value

Silicon thickness (tSi)
Bulk type
Pixel: implant type
Dopant concentration

150 μmp-typen-type

0.01
0.005
0
0

200

400

600

800

1000

Bias voltage (V)Fig. 4. Efﬁciency loss per pixel as a function of bias voltage in the bias rail (BR,ﬁlled) and the no bias bail (NB, open) regions, of Types 2 (Large offset, circle) and 12(Small offset, square) pixel structures after proton irradiation of 3 × 1015 neq/cm2 ,Type 8 (Old, diamond) after γ irradiation of 2.4 MGy. Those data of Types 13 (Widep-stop, vertical cross) and 19 (No bias, cross) after proton irradiation [16] are reproduced together.

2. KEK/HPK n þ -in-p pixel sensors

Implant width, depth (wNsub, tNsub)
Metal electrode
Overhang ( wEx1)
p-stop: implant type
Dopant concentration
Implant width (wPsub), narrow/wide
Implant depth (tPsub¼ tNsub)
Gap to Pixel implant (wGap), wide/narrow
Bias rail: metal, thickness
Overhang, wide/narrow ( wEx1, −2 × wEx1)
Insulator thickness ( tSio1)
Backplane implant, thickness (tPback)Dopant concentration

1 × 1019 cm−3
50, 1 μm
Al, DC-coupled
2 μm
p-type1 × 1016 cm−3
4 / 8 μm
1 μm
9.5/6.5 μm
Al, 1.8 μm
2/  4 μm
0.2 μmp-type, 3 μm
1 × 1018 cm−3

2.1. Pixel structure – “Old” design (wafer layout #2)
We have previously produced n þ -in-p pixel sensors1 in 6-inch
wafers (hereafter referred to as “wafer layout #2”) [2]. The sensors
were bump bonded to the ATLAS pixel readout ASIC, FE-I4 [9],irradiated at a ﬂuence of 2 × 1015 neq /cm2 with 23 MeV protons at
1
The superscript, þ, indicates that the density of the material is higher thanthat of the silicon bulk.

KIT [10], and tested by beam tests before and after the irradiation[11]. Several issues were identiﬁed on the basis of the results ofthese experiments.
The pixel structure of interest in the wafer layout #2 is shownin Fig. 1(a) (hereafter referred to as “Old” structure). Although theindividual pixels are to be DC coupled to the readout ASIC, we havedesigned a connection of bias potential to the individual pixels to

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Fig. 7. Electron density in the surface of silicon simulated with TCAD: (a) before
irradiation, Qf ¼ 1  1010 cm−2, bias voltage  100 V, (b) the same as (a) but
Qf ¼1  1012 cm−2, and (c) after irradiation, Qf ¼1  1012 cm−2, bias voltage  430 V.
The color scale is in the unit of volume density (cm  3). (For interpretation of thereferences to color in this ﬁgure caption, the reader is referred to the web version ofthis paper.)In the absence of irradiation, the loss was negligible.
2.2. Optimization of pixel structures – novel design (wafer layout#4)Fig. 6. Electric potential near the surface under the bias rail, with bias rail (black
circle) and without bias rail (light-color square): (a) before irradiation (Non-irrad.)and (b) after irradiation (Irrad.).

test the sensor without bump bonding to the ASIC. We use a bias
resistor made of polysilicon material to connect the individual
pixels to a bias rail common to a row of pixel pairs. The bias rail
was made of polysilicon in the design. Addition of a biasing network is a complication in the pixel structure but the quality control of the sensors would save time and cost at later assembly
stages.
In the old design, the bias rail runs in the middle of theboundary of a pair of pixels, which is shown horizontally in theﬁgure, and the bias resistors are routed to the pixel implants byencircling outside the pixels. The bias rail runs over the narrow
trace of p þ implant in the surface of silicon, called “p-stop”. The
p-stop is required to separate the n þ pixel implants. The bias rail
and the p-stop are separated spatially and electrically by the SiO2
surface passivation. The width of the p-stop was chosen to be
narrow according to the analysis of the designs [12]. The width of
the bias rail is wider than that of the p-stop to reduce the electricﬁeld at the edge of the p-stop.
Efﬁciency loss was observed for this layout. The loss of efﬁciency was most pronounced under the bias rails, and was smaller
but still noticeable under the bias resistors, compared to the loss atthe pixel boundaries in the opposite side where no bias rail exists.

We have then designed novel pixel structures to optimize thepixel structures to mitigate the problems found for sensors withwafer layout #2. The structures of special interest are shown in
Fig. 1, (b) Type 10 and (c) Type 13 in wafer layout #4. The physicalmechanisms behind the efﬁciency loss, especially the difference
between before and after irradiation, have been investigated andare presented in Section 4. Phenomenologically, we hypothesizedthat removal of the bias rails out of the boundary region and theplacement of the bias rails and bias resistor traces in the area ofand over the pixel implantation to shield them from the silicon
underneath will mitigate the efﬁciency loss. In Type10 (hereafterreferred to as “Large offset”), the common bias rail for a pair ofrows of pixels is split into individual bias rails per a row of pixels,
the bias rails are removed far away from the boundary, and thebias rails and the bias resistors are routed in the area of and overthe pixel implantation. In Type13 (hereafter referred to as “Widep-stop”), the common bias rails are kept at the boundaries, but
their width is smaller and the width of the p-stop is wider, which
is based on the hypothesis that the p-stop may function as a shield
for the bias rail.
The novel pixel structures are laid out in wafer layout #4 asshown in Fig. 2 in two types of sensors: FE-I4 (18.54 × 20.93 mm2)with a matrix of 336  80 of 50  250 μm2 pixels [9] and FE-I3(10.54 × 8.53 mm2) with 160  18 of 50  400 μm2 pixels [13]. The
detailed description of the novel pixel designs is given in Appendix
A along with relevant tables and ﬁgures. No additional cost is associated with the novel pixel structures in fabrication as the PolySi
process has already been included.
Typical parameters of the wafer layout #4 are summarized inTable 1. The thickness of the raw wafers is 320 μm. After the
fabrication of the front side, the thin sensors are fabricated bythinning the rear of the wafer to a thickness of 150 μm, followedby an additional process for the rear.

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5(V/cm)
1.00e+06

Non-irrad.

Irrad.
2.51e+05

6.31e+04(a)

1.58e+04

3.98e+03

1.00e+03(V)(b)

Fig. 8. 2D maps of the ﬁelds in the vicinity of bias rail, before and after irradiation in the left and right column, and in the rows of (a) electric ﬁeld E overlaid with ﬂow linesand (b) weighting potential of the bias rail VqA, respectively.

3. Results with test beams
Pixel sensors with the novel pixel structures were irradiated at
a ﬂuence of 3 to 5 × 1015 neq /cm2 with 70 MeV protons at CYRIC[14]. The samples were irradiated in an irradiation box attached toan X–Y stage to scan the beam uniformly over the samples. The
samples were cooled to  15 °C during the irradiation with thecold nitrogen gas from a liquid nitrogen dewar, and after irradiation stored cold in a freezer. A pixel sensor of the old design wasirradiated with γ rays at a dose of 2.4 MGy at TARRI [15]. These
irradiated samples were then tested using test beams at DESY with
4 GeV electrons and/or CERN with 120 GeV π's [16,17]. Based on
the energy of the beam particles, together with the distance between the telescope planes and the device under test (DUT), thepointing resolution of the beam particles at the DUT plane wasapproximately 30 and 8 μm at DESY and CERN, respectively.
3.1. Efﬁciency mapping over pixel boundaries
An example of the improvement of the novel pixel structure isillustrated in Fig. 3, using an efﬁciency mapping over two pixel
regions projected on the long pixel side. The DUT is KEK46 and150 μm thick with the Type 10 pixel structure, irradiated at

4.18 × 1015 neq /cm2 and tested at DESY. The boundary of the bias
rail side (Bias rail (hereafter referred to as BR)) is at 125 μm andthe opposite side (No bias rail (hereafter referred to as NB)) is at
375 μm. The curves are ﬁt to the data for guidance. The width ofthe efﬁciency loss is dominated by the pointing resolution. The
efﬁciency losses in the BR and NB boundaries are nearly symmetric; the effect of the bias rail is nearly eliminated. In the plot,
the efﬁciencies of the central region of the pixels are normalized tounity since the absolute efﬁciency was not reliable due to a technical issue in this test beam.
3.2. Efﬁciency loss per pixel – comparison of pixel structures
The efﬁciency loss at the boundary can be quantiﬁed as an “efﬁciency loss per pixel” by ﬁtting a Gaussian function to the efﬁciency
mapping over the pixel boundaries and dividing the integrated “area”
of the Gaussian by the length of two pixels. The calculation of “area”
eliminates the difference in the pointing resolutions at DESY and
CERN. A compilation of the efﬁciency loss per pixel at the boundaries
is shown in Fig. 4 for the DUT's of KEK84ch1 (150 μm, Type 2, p
3.03 × 1015), KEK71ch3 (150 μm, Type 12, p 3.08 × 1015), KEK93(320 μm, Type 8, γ 2.4 MGy), using the CERN data and KEK49ch3(150 μm, Type 13, p 3.20 × 1015) and KEK53ch3 (150 μm, Type 19, p
2.35 × 1015) using the DESY data. The letters “p” and “g” in the legend

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6(V/cm)

Irrad., wide p-stop

Non-irrad., Qf=1×1012

1.00e+06

2.51e+05

6.31e+04(a)

1.58e+04

3.98e+03

1.00e+03(V)(b)

Fig. 9. 2D maps of the ﬁelds in the vicinity of bias rail of the wide p-stop geometry after irradiation and the narrow p-stop geometry before irradiation with the interface
charge as that after irradiation in the left and right column, and in the rows of (a) electric ﬁeld E overlaid with ﬂow lines and (b) weighting potential of the bias rail VqA,
respectively.

indicate the proton and the γ irradiation, respectively. The efﬁciency
losses at the boundary of the bias rail side or the no bias rail side areindicated with the BR (with solid line) or NB (with dashed line),
respectively. The pixel structure of Type 2 is an equivalent of Type 10
but the bias rail is made from an aluminum material. Type 12 is avariation of Type 10 with the bias rails set at the edges of the pixels(hereafter referred to as “Small offset”). Type 8 is an equivalent of theold structure. Type 19 is the reference with no bias structure andrepresents the best case. The details of the pixel structures are presented in Appendix A.
There is a noticeable difference in bias voltage dependence
between the DUT's of the CERN (Types 2 and 12) and DESY data
(Types 13 and 19). The difference has been traced to the differencein the bias voltage dependence of the pulse height distribution,
most likely due to different tunings of the readout ASICs at different bias voltages. This difference can be removed by normalizing the NB data points by each other because the NB side isbasically the same as the no bias structure.
On the basis of Fig. 4, we have evaluated the pixel structure of
the bias rail side (BR), ﬁnding that
(1) Type 2 (Large offset) is as good as NB (No bias) side, the loss is<0.5% per pixel at the bias voltage >400 V ,(2) Type 12 (Small offset) and Type 13 (Wide p-stop) are similarly
good, the loss is approximately 1% at >600 V ,(3) These pixel structures exhibit greatly improved efﬁciency loss,
compared with the ≥3% loss of the “old” design [16], and(4) γ irradiation has no effect on the efﬁciency loss under the bias
rail.
The result (4) especially indicates that the efﬁciency loss under thebias rail is not caused by the surface charge in the Si–SiO2 interface
but caused by the radiation damage in the silicon bulk.

4. Understanding the underlying physics
We have used a semiconductor technology CAD (TCAD) program, ENEXSS [18], to calculate the electric ﬁelds in detail, including the effect of trapped charges in the interface. The region of
the pixel boundary with the bias rail is modeled and implemented
as a 2D geometry in the TCAD simulations as shown in Fig. 5. We
have approximated the conditions before and after irradiation
with three parameters according to the method elaborated in Ref.
[19]: effective space charge concentration (Neff) and leakage current (Ileak) in the silicon bulk, and ﬁxed interface charge (Qf) at the

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7

Table 4
Variation of pixel structure of FE-I4 sensors in wafer layout #4.
Type no.

Pixel size (μm2)

Bump pad

Bias type

PolySi routing

Bias rail

Bias rail offset

p-stop width

Bias rail material

(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
9
10
11
12
13
14
(15)
(16)
(17)
(18)
19
(20)
(21)
22
(23)
(24)
(25)
26
27
28

50  250

End

PolySi

Inside

1
2
1
2
1

Large

Narrow

Al

None

Wide

1
2
1
2
1

Large

Narrow
Narrowab

Comment

Small

Insidea
OutsideInside–PT

New default
Small
None

End

CenterWide
Narrow

Straight
Zigzag25  500

Old default
PolySi

None
PT
PolySi–
InsidebPT
PolySi–
Insideb–
Straight
1
2
Zigzag
2

–

1
–

Al
Wide
Narrow

Small
Large
–
None

Wide

Large

Narrow–Al
PolySi
Al

Small
Large
PolySiStaggered
End

None

–

–

No opening in the DC-Al metal of the pixel implant under the PolySi trace.
PolySi is routed along one side of the perimeter of pixel implant.

Table 5
Variation of pixel structure of FE-I3 sensors in wafer layout #4.
Type no.

Pixel size (μm2)

Bump pad

Bias type

PolySi routing

Bias rail

Bias rail offset

p-stop width

Bias rail material

FE-I4 sensor equivalent

(1)
(2)
(3)
(4)
(5)
(6)
7
8
9
(10)
(11)
(12)
13
(14)
(15)
16
(17)
(18)
19
20

50  400

End

PolySi

Inside

2

Large
Small
None

Narrow

Al

Type(2)
Type(4)
Type(5)Type(6)Type(7)
Type(8)Type10Type12
Type13
Type(16)
Type(17)
Type(18)
Type19Type(20)
Type(21)
Type22
Type(23)
Type(24)
Type27
Type28

a
b

1

Wide

Insidea
OutsideNarrow

PT

25  800

End

CenterStaggered
End

Inside2–1Straight
Zigzag

None
PT
PolySi–
InsidebPT
PolySi–
Insideb

None––
Straight
1
2
Zigzag
2
1
–

Large
Small
None

PolySi
Wide
Al

Small
Large
–
None
Large
Large
Small
Large
–

Narrow

Wide
Narrow–Al
PolySiAl
PolySi–No opening in the DC-Al metal of the pixel implant under the PolySi trace.
PolySi is routed along one side of the perimeter of pixel implant.

boundary between the silicon bulk and the surface SiO2. After irradiation, space charge concentration, leakage current, and ﬁxed
interface charge are taken to be increased by one order, three orders, and two orders of magnitude, respectively, caused by displacement and ionization damages. The parameters before andafter irradiation are summarized in Table 2, in columns of “Nonirrad.” and “Irrad.”, respectively (hereafter referred to as Non-irrad.
and Irrad.). The values of the geometry parameters are summarized in Table 3.

4.1. Effect of electric potential of the bias rail
In the DUTs with polysilicon bias resistors, the pixel electrode isconnected to the bias rail through the polysilicon resistor. The
pixel electrode is connected to the virtual ground of ASIC and thus
the bias rail is at the ground potential. We used TCAD simulations
to determine the electric ﬁeld in the boundary region near thesurface of the silicon (1 μm below the surface of silicon in the
TCAD geometry) with and without the bias rail. The electric

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8potentials before and after irradiation are shown in Fig. 6(a) and(b) for the narrow p-stop geometry (widths of bias rail and p-stopbeing 8 and 4 μm), with the Non-irrad. (bias voltage of  100 V)
and the Irrad. ( 430 V) conditions, respectively. The data obtainedwith and without the bias rail are shown by ﬁlled circles andsquares, respectively. The existence of the ground potential induced a difference of approximately 1 V over the electric potentialof 16 V before irradiation and of 2 V over 42 V after irradiation at
the location of the bias rail. The differences are small and thefractions to the total potential are similar before and after irradiation. The difference of the interface charge before and after irradiation generates a subtle difference in the shape of the electric
potential between the p-stop and the pixel electrode, but only
slightly inﬂuences the values of the potentials with and without
the bias rail. The existence or non-existence of the ground potential does not appear to be the source of efﬁciency loss at theboundary.
4.2. Charge induced on the bias rail
A moving charge in the presence of any number of electrodes
kept at constant voltages induces a mirror charge on the electrodes according to Ramo's theorem:

Q A = q·VqA,(1)

where QA is the charge induced on an electrode A, q is the charge
at a given position, and VqA is the “weighting potential” of theelectrode A at the position of the charge q. In a ﬁnite time, with afast readout electronics, instantaneous induced current iA is represented by the gradient of VqA along the direction of motion
multiplied by the drift velocity:iA = q·⎯⎯⎯⎯⎯→⎯⎯⎯⎯⎯→→ ∂VqA∂VqA dx
dVqA→ ∂VqA= q·() = q· v ·= q· μ E ·
,
∂x dt
∂x
dt
∂x

(2)

where μ is the charge carrier mobility and E is the electric ﬁeld.
Although the current has to be integrated to evaluate the charge,
an insight into the physics can be obtained qualitatively and visually from the maps of the electric ﬁeld E, the ﬂow lines of theelectric ﬁeld representing the drifting paths of the charge carriers,
and the weighting potential VqA.
Since the drifting carriers do not terminate on the bias rail, thecurrent induced on the bias rail is bipolar. The collection time ofcharge carriers (electrons in n þ electrode) is in the order of 10 ns.
Since we use a fast-shaping ampliﬁer (peaking time of approximately 20 ns), the early part of the bipolar signal will result in aﬁnite amount of charges induced on the bias rail. Thus, it is natural
to expect that charge will be lost to the bias rail, causing efﬁciency
loss. However, it is unclear why we observe efﬁciency loss only
after irradiation and not prior to it.
4.3. Visualization of the ﬁelds and predictions by TCAD
The weighting potential is independent of the space charge
distribution and actual voltages, however, it depends on the geometry of the electrodes and the resulting electric ﬁeld. In asemiconductor device the actual shape of the electrode is bias
dependent due to the change in depletion volume, for instance. In
the p-type device the effective extent of the n þ electrode is bias
dependent due to the existence of inversion layer in the n-side
surface of silicon. The radiation damage by charged particles on
the surface of device leaves positive ﬁxed charge at the interface of
Si–SiO2. The inversion layer is created by the electric potential of
the positive ﬁxed charges that repels the holes from the siliconsurface. The potential of the ﬁxed interface charge is partiallycompensated by the potential at the surface of silicon generated by

the bias voltage (see Fig. 6), thus the extent of the inversion layer isbias dependent.
Using the geometry setup and the conditions described above,
we extract two-dimensional maps of ﬁelds. The inversion layer isindeed simulated in the TCAD as shown as the electron density inthe surface of silicon in Fig. 7, (a) before irradiation (with Nonirrad. condition: Q f = 1 × 1010 cm−2, bias voltage  100 V), (b) as
same as (a) but Q f = 1 × 1012 cm−2, and (c) after irradiation (with
Irrad. condition: Q f = 1 × 1012 cm−2, bias voltage 430 V). There islittle inversion layer before irradiation due to the low density of
the interface charge. The inversion layer is visible with the interface charge density after irradiation; extends from the n þ electrode toward the p-stop (edge at  2 μm) approximately to  3and  5 μm with the bias voltage of 100 V and 430 V, respectively. Visual thickness of the layers in the plots should be dueto the resolution of the calculation and plotting.
The weighting potential of the electrode of interest is calculated from the difference of the two maps of the electric potential:
the map with the setup and that obtained by adding 1 V to theelectrode of interest over the setup. The remnant is the potential
where the selected electrode at unit potential, all other electrodes
at zero potential. The extracted ﬁelds are shown in Fig. 8 for the
narrow p-stop geometry in the rows of (a) electric ﬁeld E overlaid
with ﬂow lines of the ﬁeld and (b) weighting potential of the bias
rail VqA, in the columns of before (Non-irrad., 100 V) and after
irradiation (Irrad.,  430 V), respectively.
Examination of Fig. 8 shows that there are several distinctive
differences between the ﬁelds before and after irradiation. Prior toirradiation, the electric ﬁeld shows a large blob of low electric ﬁeld
region under the bias rail/p-stop, the ﬂow lines of the electric ﬁeld,
i.e., the path of drifting carriers are deﬂected from the low electricﬁeld region toward the pixel electrodes distinctly, and the intensity of the weighing potential of the bias rail is not extending in
the area and vicinity of the low electric ﬁeld region. The area oflow electric ﬁeld region appears to function as a shield against thedrift paths and the weighting potential. After irradiation, the blobof low electric ﬁeld region under the bias rail becomes minute, theﬂow lines are not deﬂected very much, and the intensity of theweighting potential extends more near to the bias rail and more
toward the backplane. The shrinkage of the blob is caused by thestrong electric ﬁeld generated by the large bias voltage applied tocope with the space charge (Neff) increased by the radiation damage in the silicon bulk. The extent of the inversion layer shields
the weighting potential to remain in the vicinity of the bias rail.
The charge induced on the bias rail is determined by the interplay of the weighting potential and the path of drifting carriers.
By overlaying the ﬂow lines over the weighting potentials, weobserve that before irradiation the drifting carriers from most of
the bulk do not pass high intensity region of the weighting potential, but after irradiation drifting carriers especially from thebulk under the bias rail pass through. On the basis of the visualization, we conclude that the charge induced on the bias rail issmall (almost zero) before irradiation but ﬁnite after irradiation.
The TCAD simulations have also predicted only a slight efﬁciency loss in the pixel structure with the wide p-stop geometry(widths of bias rail and p-stop being 4 and 8 μm) after irradiation,and in the old pixel structure after γ irradiation. Fig. 9 shows in therows of (a) electric ﬁeld overlaid with ﬂow lines and (b) weighting
potential, in the columns of the cases of wide p-stop geometry
after irradiation (Irrad., wide p-stop) and of narrow p-stop geometry before irradiation but with the interface charge as that after
irradiation (Non-irrad., Q f = 1 × 1012 cm−2), respectively. The latter
scenario corresponds to the case of γ irradiation. In both cases, theweighting potentials are very low and uniform over a wide region
including under the bias rail/p-stop region. The low electric ﬁeld

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No bias rail side (NB)

Bias rail side (BR)Type10,(2)9No bias rail side (NB)

Type9,(1)-BR

Type11,(3)-BR

Type12,(4)-BR

Type13,(5),(6)-BR

Type14-BR

Fig. 10. Pixel structures in wafer layout #4 of Types 1–6 and 9–14 with variations of
number of bias rails and their locations. Bias rail is made of polysilicon (Types 9–14)
or aluminum (Types 1–6).

region under the p-stop and the extent of the inversion layer are
nearly overlapping, thus seem to shield the weighting potential
against extending into the silicon bulk. The γ irradiation study was
motivated by the TCAD prediction.

5. Summary
We have developed n þ -in-p pixel sensors, using planar process
in p-type 6-inch silicon wafers to obtain highly radiation tolerant
sensors for extremely high radiation environments such thosefound in HL-LHC. We have designed novel pixel structures – wafer
layout #4 – to eliminate the efﬁciency loss at the pixel boundaryobserved in the old pixel structure of the wafer layout #2, especially after irradiation. The new pixel sensors were irradiated with
protons at a ﬂuence of approximately 3  1015 neq /cm2 at CYRIC or
with γ rays at a dose of 2.4 MGy at TARRI, and evaluated with test
beams at CERN and DESY.

Type(7)-BR
Bias rail side (BR)Type(8)Fig. 11. Pixel structures in wafer layout #4: Type 8 with polysilicon bias resistor
routing outside the pixel implant with the width of p-stop narrower than the widthof bias rail (narrow p-stop, old design), and Type 7 with wide p-stop.

Type(15)-BR

Type(17)-BR Among the novel pixel structures tested, the best pixel structure
to retain high efﬁciency after irradiation is the one with “Large
offset” where the bias rails removed far away from the boundary
and the polysilicon biasing resistor routed inside the pixel implant region, achieving an efﬁciency loss of <0.5% per pixel atthe boundary, as efﬁcient as that without the bias rail.
 If offsetting the bias rail were not applicable, the one with
“Wide p-stop” geometry could be an alternate solution,achieving a loss of approximately 1% per pixel at the boundary.
We have also obtained an understanding of the physics underlying the efﬁciency loss under the bias rail with TCAD simulations, by simulating the electric ﬁelds, especially the weighting
potential of the bias rail.

 The efﬁciency loss is due to the loss of charge induced on thebias rail.

 The difference of the charge induced on the bias rail before andafter irradiation is caused by the difference of the region of low
electric ﬁeld under the bias rail together with the extent of theinversion layer in the surface of silicon.
 Before irradiation, a large blob of low electric ﬁeld region underthe bias rail makes the weighting potential very low in the areaand vicinity, deﬂects drifting carries out of high intensity regionof the weighting potential.
 After irradiation, the blob becomes minute due to strong electric ﬁeld in the radiation-damaged silicon, which together with

Type19-BR

Type(16)-BR

Type(18)-BR

Fig. 12. Pixel structures of punch-through (PT) bias resistor in wafer layout #4:
Types 15 and 16 with narrow and wide p-stop, and 17 and 18 with small and large
offset of bias rails, respectively. Type 19 is without a biasing structure.

the extent of the inversion layer makes the weighting potential
to extend more into the silicon under the bias rail, makes
drifting carriers especially from the region under the bias rail topass through high intensity region of the weighting potential.
 The TCAD simulations have also shown that wide p-stop andlarge Si–SiO2 interface charge (inversion layer, speciﬁcally) act
to shield the weighting potential against extending into the silicon bulk. The pixel sensor with old pixel structures irradiatedwith γ rays has conﬁrmed little efﬁciency loss at the boundary.

Acknowledgments
The irradiations were performed, with protons at Cyclotron andPlease cite this article as: Y. Unno, et al., Nuclear Instruments & Methods in Physics Research A (2016), http://dx.doi.org/10.1016/j.
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10

NB

BP

Type27-BP
BR
Type28Type(20)-BR

Type(21)-BR

Type22-BR

Fig. 13. Pixel structures of the 25 × 500 μm2 pixel size with the bump bonding pads
at the end of the pixels in wafer layout #4: Type 28 without a biasing structure, 20
with PT biasing and wide p-stop, 21 with PolySi biasing and wide p-stop, and 22
with PolySi biasing and large offset of bias rails.

Radioisotope Center (CYRIC), Tohoku University, with Y. Sakemi, M. Ito,and T. Wakui, and with γ at Takasaki Advanced Radiation Research Institute, Japan Atomic Energy Agency. The research was supported andﬁnanced in part by the Japan Society for Promoting Science KAKENHI-A
Grant number 20244038 and KAKENHI-C Grant number 20540291, theMinistry of Education, Culture, Sports, Science and Technology – Japan,
KAKENHI for Research on Priority Area Grant number 20025007 andfor Scientiﬁc Research on Innovative Areas Grant number 23104002.

Appendix A. Pixel structures in wafer layout #4
In the wafer layout #4 (Fig. 2), we have designed several variations of the structures to investigate and evaluate the novel pixel
structures in FE-I4 and FE-I3 pixel sensors. The characteristics of
28 variations in the FE-I4 pixel sensors and 20 in that of the FE-I3
pixel sensors are summarized in Tables 4 and 5, respectively. The
material of the bias rail is either polysilicon (referred to as “PolySi”)
or aluminum (referred to as “Al”). The pixel structure with the Albias rail is symbolized with the type number in parenthesis. The
detailed views of the pixel structures are shown in Figs. 10–14. The
pixel structures of bias rail side and no bias rail side are labelledwith BR and NB, respectively.
A.1. FE-I4 sensors
The 19 variations from Types 1 to 19 are fabricated using a pixel
size of 50 × 250 μm2 (column “Pixel size” in the tables, Figs. 10–12).
The 9 variations from Types 20 to 28 are fabricated with a pixel
size of 25 × 500 μm2, mating to the same grid of the bump pads ofthe FE-I4 readout ASIC, splitting the 50 μm of short pixel direction
into two 25 μm pixels and merging two pixels to 500-μm-longpixels in the long pixel direction to study a ﬁner pitch of the pixels(Figs. 13 and 14).
In the 50 × 250 μm2 pixels, the location of the bump pads
(column “Bump pad”) is always at the end of pixel electrodes(referred to as “End”, e.g. Fig. 10) in the NB side for Types 1–19. In
the 25 × 500 μm2 pixels, the locations of the bump pads are, (1) atthe end of pixel electrodes for Type 20, etc. (Fig. 13), (2) at thecenter of pixel electrodes (referred to as “Center” in the tables, BP
in Fig. 14) for Type 23, etc., or (3) at the center and the end alternately (referred to as “Staggered”) for Type 27 (Fig. 14) to makethe pixel electrodes to be staggered by half pitch in the long pixel
direction. The staggered pixel layout is used to evaluate improvements in position resolution in the long pixel direction because more two-cluster hits are expected in the 25 μm pixels thanType(23)

Type(24)-BR Type26,(25)-BR

Fig. 14. Pixel structures of the 25 × 500 μm2 pixel size with the bump bonding pads
at the central region of the pixels or at staggered pixels in wafer layout #4: Type 23
with PT biasing and small offset of zigzag bias rail, 24 with PolySi biasing and small
offset of bias rails, 26 and 25 with PolySi biasing and large offset of bias rails, and 27
with PolySi biasing with half-pitch (250 μm) staggered pixels.

in the 50 μm pixels.
The bias resistor is either formed with a resistive trace ofpolysilicon material, approximately 5 kΩ/μm (column “Bias type”,
referred to as “PolySi”) or a punch-through structure with a narrowgap, approximately 18 μm between a bias dot (n þ implant) andthe pixel electrodes (n þ implant) (referred to as “PT”). The PolySi
resistor is routed (column “PolySi routing”) to place the trace either“inside” the area of pixel electrode (Fig. 10) to mitigate the efﬁciency loss under the trace or “outside” the pixel area for Types
7 and 8 (Fig. 11) as a reference to the old design.
One approach for the removal of the bias rail out of theboundary region is to use two bias rails for a pair of pixel rows
(column “Bias rail”), placing them in the pixel area largely awayfrom the boundary (referred to as “Large offset”, column “Bias rail
offset”, e.g. Fig. 10 Type 10) or just over the edge of the pixel
electrode (referred to as “Small offset”, Fig. 10 Type 12). The otheris to keep one bias rail at the boundary (referred to as “None”) but
to increase the width of the p-stop under the bias rail while
keeping the width of the bias rail narrow (referred to as “Wide”,
column “p-stop width”, Fig. 10 Type 13), otherwise narrow (referred to as “Narrow”, Fig. 10 Type 14).
In the case of PT structures, one PT dot is shared by four pixels
in a pair of pixel rows to which one bias rail is placed [20]. The bias
rail is either straight (referred to as “Straight”, column “Bias rail”)
with the wide p-stop under the bias rail (“Wide”, column “p-stop
width”) or zigzags (“Zigzag”, column “Bias rail”) by passing throughthe bias dot and then being largely removed away from theboundary region (“Large offset”, column “Bias rail offset”) or justover the edge of the pixel electrode (“Small offset”, Fig. 12).
The material of the bias rail is listed in the column “Bias railmaterial”. Historically, Al has been used. The resistance of thebiasing network is a source of electrical noise (parallel noise).
Larger resistance gives smaller noise, leading to our preference to“PolySi”.
The similar structures of PolySi and PT are implemented in the
25 × 500 μm2 pixels (Types 20–28, Figs. 13 and 14). The pixel
structure without the biasing network (“None”, column “Bias type”)
is used as the reference due to it showing the best performance(Type 19, Fig. 12 for the 50 × 250 μm2 and Type 28, Fig. 13 for the
25 × 500 μm2pixels).
A.2. FE-I3 sensors
The characteristics of the variations in the FE-I3 pixel sensors

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are summarized in Table 5. The pixel structures are limited to 20
variations due to the available space in the wafer layout. The 13
variations from Type 1 to 13 used 50 × 400 μm2 pixels. The 7 variations from Type 14 to 20 used 25 × 800 μm2 pixels. The basic
structures are copied from the FE-I4 pixel structures. The pixel
structures equivalent to the FE-I4 sensors are listed in the “FE-I4
sensor equivalent” column in Table 5.

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