LTC4331
I2C Slave Device ExtenderOver Rugged Differential Link
FEATURESDESCRIPTION

Up to 1MHz Serial Clock, Fast-mode Plus (Fm+)
n Selectable Link Baud Rates Extend I2C Up to
1200m
n Protected from Overvoltage Line Faults to ±60V
n ±40kV ESD on Link Pinsn IEC Level 4 ESD ±8kV and EFT ±5kV on Link Pins
n Extended Common Mode Range: ±15V
n Remote Interrupt/SMBALERT and Control Signals
n Low EMI Moden SMBus 3.0 Compatible
n I2C Idle Detection, and Stuck Bus Protection
n I2C Device Address Sharingn 3V to 5.5V Supply Voltage
n 1.62V to 5.5V Logic Supply
n 4mm × 5mm 20-Lead QFN package

The LTC®4331 is a point-to-point SMBus compatible I2C
slave device extender designed for operation in high noise
industrial environments. Using a ±60V fault protecteddifferential transceiver, the LTC4331 can extend an I2C/
SMBus bus, including SMBALERT and a control signal,
over a single twisted pair differential link up to 1200m.
With an extended common mode operating range thesolution provides tolerance to large ground differences
between nodes. For EMI sensitive environments, a slew
rate control pin reduces the EMI emitted from the differential link.

n

In addition, the LTC4331 can act as an I2C to I2C bridge
allowing independent bus frequencies between the local
and remote networks. The solution is completely transparent to the master requiring no additional code in mostcases; however, a control interface is provided for additional configuration and fault monitoring.

APPLICATIONSnn

A master controller fully supporting SCL clock-stretchingis strongly recommended.

Industrial Control and Sensors
Lighting and Sound System Control

All registered trademarks and trademarks are the property of their respective owners. Patent
Pending.

TYPICAL APPLICATION
Extended I2C Network Over 30m, 1MHz Fm+ SCL
5V

VL
10k
2.7k

SCL
SDA

MCU_INT

ALERT
CTRL

5V

LINK
D1

3.3V
4.7µF

VCC

3.3V

VL
LTC4331

2.7k
1µF

620Ω

MCU_SCL

1.5k

5V
4.7µF

1µF

MCU_SDAMCU_CTRL

VCC
LTC4331

2.7k

A

110Ω

110Ω

B
SLO

620Ω

620Ω

3.3V

REMOTE
A1/2

SCL

REM_SCLSDA

REM_SDA

ALERT
CTRL

REM_INT

A
B

5V

2.7k

620Ω

30m CAT5SLO

REM_CTRL
620Ω

LINK
REMOTESPEED1/2

10k

3.3V

3.3V

D2

SPEED1/2
V GROUND LOOP
≤15V PEAK
GND1
GND2

Rev 0

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LTC4331
TABLE OF CONTENTS
Features ............................................................................................................................ 1
Applications ....................................................................................................................... 1
Description......................................................................................................................... 1
Typical Application ............................................................................................................... 1
Absolute Maximum Ratings ..................................................................................................... 3
Pin Configuration ................................................................................................................. 3
Order Information ................................................................................................................. 3
Electrical Characteristics ........................................................................................................ 3
Switching Characteristics ....................................................................................................... 5
Typical Performance Characteristics .......................................................................................... 7
Pin Functions ...................................................................................................................... 8
Block Diagram..................................................................................................................... 9
Test Circuits ......................................................................................................................10
Timing Diagrams ................................................................................................................11
Applications Information .......................................................................................................12
Typical Applications .............................................................................................................24
Package Description ............................................................................................................25
Typical Application ..............................................................................................................26
Related Parts .....................................................................................................................26

Rev 0

2

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LTC4331
ABSOLUTE MAXIMUM RATINGSPIN CONFIGURATION(Note 1)
SLO

A

B

NC

TOP VIEW

20 19 18 17
VCC

1

16 GND

VL

2

15 SPEED2

ON

3

REMOTE

4

LINK

5

12 A2

RDY

6

11 A1

14 SPEED1

21
GND

8

9 10
NC

ALERT

7
SCL

13 CTRL

SDA

Supply Voltages
VCC........................................................... –0.3V to 6V
VL ............................................................ –0.3V to 6V
Logic Signals
ON, LINK, RDY, SCL, SDA,
ALERT, SLO .............................................. –0.3V to 6V
REMOTE, A1, A2, CTRL,
SPEED1, SPEED2 ................ –0.3V to 6.3 or VL + 0.3V
Interface I/O: A,B ........................................ –60V to 60V
Operating Ambient Temperature Range
LTC4331C ................................................ 0°C to 70°C
LTC4331I .............................................–40°C to 85°C
LTC4331H .......................................... –40°C to 125°C
Storage Temperature Range .............. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................... 300°C

UFD PACKAGE
20-LEAD (4mm × 5mm) PLASTIC QFNTJMAX = 150°C, θJA = 43°C/W, θJC = 3.4°C/W
EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCBORDER INFORMATIONLEAD FREE FINISH

TAPE AND REELPART MARKINGPACKAGE DESCRIPTIONTEMPERATURE RANGE

LTC4331CUFD#PBF

LTC4331CUFD#TRPBF

4331

20-Lead (4mm × 5mm) Plastic QFN

0°C to 70°C

LTC4331IUFD#PBF

LTC4331IUFD#TRPBF

4331

20-Lead (4mm × 5mm) Plastic QFN–40°C to 85°C

LTC4331HUFD#PBF

LTC4331HUFD#TRPBF

4331

20-Lead (4mm × 5mm) Plastic QFN–40°C to 125°C

Contact the factory for parts specified with wider operating temperature ranges.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.

ELECTRICAL CHARACTERISTICS

The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, VCC = 5V, VL = 3.3V, GND = 0V unless otherwise noted.
SYMBOL PARAMETERCONDITIONS

MIN

TYP

MAX

UNITS

5.5

V

40
12
65

µA
mA
mA

5.5

V

140

µA

Supplies
VCC

Operating Supply Rangel

ICC

Operating Supply Currentl
Low Power: ON = 0
Idle: ON = 1, I2C Bus Idle, Link = Fm+ ll
Active: I2C Transaction

VL

Logic Supply RangelIL

Logic Supply Current

l

3
1

1.62

Rev 0

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3

LTC4331
ELECTRICAL CHARACTERISTICS

The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, VCC = 5V, VL = 3.3V, GND = 0V unless otherwise noted.
SYMBOL PARAMETERCONDITIONS

MIN

TYP

MAX

UNITS

VCC
5

V
V

±250

mA

Differential Driver|VOD|

Differential Driver Output Voltage

R=∞
R = 27Ω (Figure 1)

l
l

IOSD

Maximum Driver Short-Circuit Current–60V ≤ (A or B) ≤ 60V (Figure 2)

l

1.5
1.5
±150

Differential Receiver
RIN

Receiver Input Resistance

VCM

Receiver Common Mode Input Voltage

VTH

Differential Input Signal Threshold0 ≤ VCC ≤ 5.5V (Figure 3)

112

kΩ

l

±15

V

–15V < VCM < 15V (Note 2)

l

±200

mV

Logic
VIH

High Level Input Voltage (ON, CTRL, REMOTE)

1.62V < VL < 5.5Vl0.8 • VL

V

High Level Input Voltage (SCL, SDA, ALERT)

1.62V < VL < 5.5V

l

1.35

V

High Level Input Voltage (SLO)

3V < VCC < 5.5V

l 0.67 • VCC

VIH3ST

High Level Input Voltage (A1, A2, SPEED1, SPEED2)l

VIM3ST

Mid Level Input Voltage (A1, A2, SPEED1, SPEED2)l

VIL3ST

Low Level Input Voltage (A1, A2, SPEED1, SPEED2)VIL

Low Level Input Voltage (ON, CTRL, REMOTE)

1.62V < VL < 5.5V

Low Level Input Voltage (SCL, SDA, ALERT)

1.62V < VL < 5.5V

Low Level Input Voltage (SLO)
Digital Input Current (SCL, SDA, ALERT)
Digital Input Current (ON, CTRL, A1, A2, REMOTE,
SPEED1, SPEED2)

VL – 0.25
0.45 • VL

V
V
0.55 • VL

V

l

0.25

V

l

0.2 • VL

V

l

0.8

V

3V < VCC < 5.5Vl0.33 • VCC

V

VIN = 0V to VL

l

±5

µA

VIN = 0V to VL

l

±60

µA

±5

µA
V

Digital Input Current (SLO)

0

l

VOH

High Level Output Voltage (CTRL)ILOAD = –500µA

l

VOL

Low Level Output Voltage (LINK, RDY, ALERT, CTRL)ILOAD = 500µA

l

0.2

Low Level Output Voltage (SCL, SDA)ILOAD = 20mA

IOZ

CIN

VL – 0.2

V

l

0.4

V

High-Z Output Leakage Current (SCL, SDA, ALERT, LINK)

l

±5

μA

High-Z Output Leakage Current (RDY)

l

–60

μA

Output Source Current (Short-Circuit) (CTRL)

–80

mA

Output Sink Current (Short-Circuit) (LINK, RDY, ALERT,
CTRL)

80

mA

Short-Circuit Current (SCL, SDA)

100

mA

10

pF

Input Pin Capacitance

SCL, SDA (Note 2)

Rev 0

4

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LTC4331
SWITCHING CHARACTERISTICS

The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, CL = 20pF, VCC = 5V, VL = 3.3V, GND = 0V; unless otherwise noted.
Conditions Fast-mode Plus, Fast-mode, and Standard-mode listed below as Fm+, Fm, and Sm respectively.
SYMBOLPARAMETERCONDITIONStON_LOW

Pulse Width of ON Low for Valid Reset Condition

MIN
l

TYP

MAX

1

UNITS
µs

Local Mode (REMOTE = 0)
I2C Bus IDLEtREADY

Delay From ON Rise to RDY Low

tREMOTE_RESET

Delay From Local ON Low for Valid Remote Reset
Condition

fSCL:SLAVE

Slave Device SCL Operating Frequency

tBUF:SLAVE

65

µs

l

180

ms

(Note 3)l

10

Bus free Time between STOP and START

SPEED1/SPEED2 = Fm+
SPEED1/SPEED2 = Fm
SPEED1/SPEED2 = Sm

l
l
l

0.5
1.3
4.7

µs
µs
µs

tSU:STA:SLAVE

Repeated Start Condition Setup TimeSPEED1/SPEED2 = Fm+
SPEED1/SPEED2 = Fm
SPEED1/SPEED2 = Sm

l
l
l

0.26
0.6
4.7

µs
µs
µs

tHD:STA:SLAVE

Hold Time after START Condition

SPEED1/SPEED2 = Fm+
SPEED1/SPEED2 = Fm
SPEED1/SPEED2 = Sm

l
l
l

0.26
0.6
4

µs
µs
µs

tSU:STO:SLAVESTOP Condition Setup TimeSPEED1/SPEED2 = Fm+
SPEED1/SPEED2 = Fm
SPEED1/SPEED2 = Sm

l
l
l

0.26
0.6
4

µs
µs
µs

tSU:DAT:FSLAVE

Data Setup Time from LTC4331

SPEED1/SPEED2 = Fm+
SPEED1/SPEED2 = Fm
SPEED1/SPEED2 = Sm

l
l
l

50
100
250

ns
ns
ns

tSU:DAT:TSLAVE

Data Setup Time to LTC4331

l

50

ns

tHD:DAT:TSLAVE

Data Hold Time to LTC4331

l

0

ns

tHD:DAT:FSLAVE

Data Hold Time from LTC4331

l

50

tTIMEOUT:SLAVESCL Low Timeout Detectionl28

tLOW:SLAVESCL Low Time

l

0.25

tHIGH:SLAVESCL High Time

l

0.25

tHIGH:IDLE

SCL High for Bus Idle Detection

l

70

µs
µs
µs
µs

1000

2000

kHz

ns
31.5

35

ms
µs

50

µs

Remote Mode (REMOTE = 1)
tSCL:MASTER

Master Device SCL Operating Period

SPEED1/SPEED2 = Fm+
SPEED1/SPEED2 = Fm
SPEED1/SPEED2 = Sm

l
l
l

1
2.5
10

tBUF:MASTERBus Free Time between STOP and START

SPEED1/SPEED2 = Fm+
SPEED1/SPEED2 = Fm
SPEED1/SPEED2 = Sm

l
l
l

0.5
1.3
4.7

0.6
1.5
5

µs
µs
µs

tHD:STA:MASTER

Hold Time after START Condition

SPEED1/SPEED2 = Fm+
SPEED1/SPEED2 = Fm
SPEED1/SPEED2 = Sm

l
l
l

0.26
0.6
4

0.3
0.8
4.2

µs
µs
µs

tSU:STA:MASTER

Repeated Start Condition Setup TimeSPEED1/SPEED2 = Fm+
SPEED1/SPEED2 = Fm
SPEED1/SPEED2 = Sm

l
l
l

0.26
0.6
4.7

0.3
0.8
4.8

µs
µs
µs

tSU:STO:MASTER

Setup Time for STOP

SPEED1/SPEED2 = Fm+
SPEED1/SPEED2 = Fm
SPEED1/SPEED2 = Sm

l
l
l

0.26
0.6
4

0.3
0.8
4.2

µs
µs
µs

Rev 0

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5

LTC4331
SWITCHING CHARACTERISTICS

The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, CL = 20pF, VCC = 5V, VL = 3.3V, GND = 0V; unless otherwise noted.
Conditions Fast-mode Plus, Fast-mode, and Standard-mode listed below as Fm+, Fm, and Sm respectively.
SYMBOLPARAMETER

tHD:DAT:FMASTER

Data Hold from LTC4331

CONDITIONS

MIN
l

TYP

MAX

UNITS

50

ns

tHD:DAT:TMASTER

Data Hold to LTC4331(Note 2)l0

ns

tSU:DAT:FMASTER

Data Setup from LTC4331

SPEED1/SPEED2 = Fm+
SPEED1/SPEED2 = Fm
SPEED1/SPEED2 = Sm

l
l
l

50
100
250

ns
ns
ns

tSU:DAT:TMASTER

Data Setup to LTC4331

l

50

tTIMEOUT:MASTERSCL Low Timeout Detectionl28

tLOW:MASTERSCL Low TimeSPEED1/SPEED2 = Fm+
SPEED1/SPEED2 = Fm
SPEED1/SPEED2 = Sm

l
l
l

0.6
1.5
5.8

µs
µs
µs

tHIGH:MASTERSCL High TimeSPEED1/SPEED2 = Fm+
SPEED1/SPEED2 = Fm
SPEED1/SPEED2 = Sm

l
l
l

0.4
1
3.8

µs
µs
µs

tF

Fall Time (SDA, SCL) (Note 5)lSPEED1/SPEED2 = Fm+lSPEED1/SPEED2 = Fm, Sm
CL = 550pF, RL = 1kΩ (Figure 5) (Note 2) l

120
300
25

ns
ns
ns

tR

Rise Time (SDA, SCL) (Note 5)

SPEED1/SPEED2 = Fm+
SPEED1/SPEED2 = Fm, Sm

120
300

ns
ns

tSPIKE

Noise Spike Suppression Time (SDA, SCL)

50

ns

15
1200

ns
ns

ns
31.5

l
l
l

0

l
l

500

35

ms

TransceivertRD, tFD

Driver Rise or Fall Time (Figure 4)

RDIFF = 54Ω, CL = 100pF, SLO = 1
RDIFF = 54Ω, CL = 100pF, SLO = 04800

tLINK_TIMEOUT

Response Time for LINK = 1 after Disconnection

REMOTE = 1
REMOTE = 0 (Note 4)168
96 • SF

msµs

ALERT Propagation Delay, Remote to Local

I2C Bus idle (Note 4)

0.8 • SF 2 • SF 26 • SF

µs

I2C Bus idle (Note 4)

SystemtALT_PROPtCTRL_PROP

Local CTRL Propagation Delay to Remote CTRL

0.8 • SF 2 • SF 26 • SF

µs

tSTART_PROP

I2C START Link Propagation Delay, Local to Remote (Note 4)

2 • SFµstLDAT_PROP

I2C DATA Link Propagation Delay, Local to Remote(Note 4)2 • SFµstSTOP_PROP

I2C STOP Link Propagation Delay, Local to Remote(Note 4)2 • SFµstRDAT_PROP

I2C DATA Link Propagation Delay, Remote to Local(Note 4)2 • SFµs

Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Guaranteed by design, not production tested.
Note 3: Local SCL frequencies between 1000kHz and 2000kHz are
allowed, however the effective link throughput maximum is 1000kHz. SCL
low clock-stretching by the LTC4331 must be respected.

Note 4: SF = Speed Factor. See Table 3.
Note 5: SCL and SDA rise and fall time measurement limits are defined asfollows:
Rise Time Limit: 0.65V to 1.5V
Fall Time Limit: 1.5V to 0.65V

Rev 0

6

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LTC4331
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VCC = 5V, VL = 3.3V, GND = 0V, unlessotherwise noted.

ICC vs Temperature Burst I2C
Write Traffic
58

ICC vs Temperature Burst I2C
Read Traffic
56

REMOTE = 0
1MHz SCL

54

42
38

=
SPD IDX = 0
SPD IDX = 1
SPD IDX = 2
SPD IDX = 3
SPD IDX = 4

3430

SPD IDX = 5
SPD IDX = 6
SPD IDX = 7
SPD IDX = 8

50
48
46
44

SPD IDX = 0
SPD IDX = 1
SPD IDX = 2
SPD IDX = 3
SPD IDX = 4

42
40

26
–75 –50 –25 0 25 50 75 100 125 150
AMBIENT TEMPERATURE (°C)

SPD IDX = 5
SPD IDX = 6
SPD IDX = 7
SPD IDX = 8

4.50

3.00
2.50
2.00
1.50

4.00
3.00
2.50
2.00
1.50
1.00

0.50

0.50
2.5 3 3.5 4 4.5 5 5.5
LOGIC SUPPLY VOLTAGE VL (V)

0
1.5

6

4331 G042

2.5 3 3.5 4 4.5 5 5.5
LOGIC SUPPLY VOLTAGE VL (V)

6

1.40
1.35
1.30
1.25
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
0.75
1.5

4331 G05

I2C SCL and SDA Output
VOL at 20mA vs Temperature

200
150
100
–75 –50 –25 0 25 50 75 100 125 150
AMBIENT TEMPERATURE (°C)

2.5 3 3.5 4 4.5 5 5.5
LOGIC SUPPLY VOLTAGE VL (V)

6

2.5

3.0

VOH

2.3

RDIFF = 100Ω

2.5
2.0

VOD (V)DRIVER OUTPUT VOLTAGE (V)250

2A/B Driver Differential Output
Voltage vs Temperature

3.5

300

VIH
VIL

4331 G06

A/B Driver Output Low/High
Voltage vs Output Current

350
OUTPUT VOLTAGE (mV)4331 G03

I2C SCL and SDA Input
VIL and VIH vs VL Supply

3.50

1.00

2

SPD IDX = 5
SPD IDX = 6
SPD IDX = 7
SPD IDX = 8

7.0–75 –50 –25 0 25 50 75 100 125 150
AMBIENT TEMPERATURE (°C)

INPUT VOLTAGE (V)3.50

SPD IDX = 0
SPD IDX = 1
SPD IDX = 2
SPD IDX = 3
SPD IDX = 4

7.4

VOH 2mA
VOL 2mA
VOH 4mA
VOL 4mA

5.00

OUTPUT VOLTAGE (V)INPUT VOLTAGE (V)

5.50

4.00

0
1.5

8.2

CTRL Output (2mA and 4mA)
VOL and VOH vs VL Supply

VIH
VIL

4.50

8.6

4331 G02

ON, CTRL, and REMOTE Inputs
VIL and VIH vs VL Supply
5.00

9.0

7.8

38
–75 –50 –25 0 25 50 75 100 125 150
AMBIENT TEMPERATURE (°C)

4331 G01

5.50

REMOTE = 0

9.4
CURRENT (mA)46

ICC vs Temperature I2C Bus Idle

9.8

52
CURRENT (mA)

CURRENT (mA)

REMOTE = 1
1MHz SCL

54

50

400

10.2

1.5

2.1

1.9
RDIFF = 54Ω

1.0
VOL

0.5
0.0

0

10

1.7

50

20
30
40
OUTPUT CURRENT (mA)

1.5
–50

0

50
100
TEMPERATURE (°C)

1504331 G07
4331 G08

4331 G09

Rev 0

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7

LTC4331
PIN FUNCTIONS
Logic (All Logic Side Inputs and Outputs Referenced
to GND and VL Except SLO, which Is Referenced to
GND and VCC)
VCC (Pin 1): Supply Voltage. 3V < VCC < 5.5V. Bypass with
4.7μF ceramic capacitor to GND.
VL (Pin 2): Logic Supply Voltage. 1.62V < VL < 5.5V.
Bypass with 1μF ceramic capacitor to GND.
ON (Pin 3): Enable Input. Set high for operation. Set low
for low power mode, in which the internal reset is held
and outputs are disabled. Connect to VL if unused.
REMOTE (Pin 4): Operating Mode Select Input. Set low
for local I2C slave mode. Set high for I2C master mode
when used on the remote side. REMOTE is weakly pulled
to GND.
LINK (Pin 5): Link Status Open-Drain Output. When inremote mode, LINK is driven low when the device establishes link communication. When in local mode, LINK isdriven low after the LTC4331’s I2C interface has joined theI2C bus in addition to establishing link communication.
The link status function is only valid when an LTC4331
configured to local mode (REMOTE set low) connects toa second LTC4331 configured to remote mode (REMOTE
set high). Connect to an external pull-up to VL to monitor
status, otherwise float or connect to GND.
RDY (Pin 6): I2C Ready Status Open-Drain Output. RDY
is driven low after the device’s I2C interface has joined thebus. Use to detect when the LTC4331’s control interface
is available in the absence of a connected link. RDY hasa weak internal pull-up to VL and is only valid when inlocal mode. In remote mode the pin can be unconnected.
SCL (Pin 7): I2C Serial Clock. Low side output driver andinput. Connect to an external pull-up.
SDA (Pin 8): I2C Serial Data. Low side output driver andinput. Connect to an external pull-up.
NC (Pins 9, 20): Unconnected Pins. Float or connect to
GND.
ALERT (Pin 10): SMBALERT/Interrupt. ALERT is an opendrain output in local mode and an input in remote mode.
Values set on the remote side ALERT propagate to the
local side ALERT pin. In addition, ALERT is the SMBALERT

function for the local side’s I2C control interface whenenabled. The ALERT pin switches to a level-sensitive active
low interrupt signal when register field INTR_MODE = 1.
Connect to an external pull-up on the local side. Do notallow the ALERT pin to float on the remote side.
A1 (Pin 11): I2C Device Address Select 1. A1 is a 3-state
input. A1 in conjunction with A2 selects one of eight possible I2C addresses assigned to the internal slave device.
Float pins A1 and A2 to disable the internal I2C device. Set
to high, low, or float as defined in Table 4.
A2 (Pin 12): I2C Device Address Select 2. A2 is a 3-State
input. A2 in conjunction with A1 selects one of eight possible I2C addresses assigned to the internal slave device.
Float pins A1 and A2 to disable the internal I2C device. Set
to high, low, or float as defined in Table 4.
CTRL (Pin 13): Local to Remote Control. Values set on thelocal side CTRL pin propagate to the remote side CTRL pinover the differential link. On the remote side, CTRL is not
driven at startup until the differential link is established.
CTRL has a weak pull-up to VL and can be unconnected
if not used.
SPEED1 (Pin 14): Link and Interface Timing Select 1.
SPEED1 is a 3-state input and in conjunction with SPEED2
selects link baud rate and I2C bus timing. Set to high, low,or float as defined in Table 2.
SPEED2 (Pin 15): Link and Interface Timing Select 2.
SPEED2 is a 3-state input and in conjunction with SPEED1
selects link baud rate and I2C bus timing. Set to high, low,or float as defined in Table 2.
GND (Pin 16): Ground.
SLO (Pin 17): Link Slow Mode Input. Set low to limit thelink transmitter slew rate which also limits the maximum
link rate set by SPEED1 and SPEED2. Only valid for SPEEDINDEX 0 and 1. SLO is referenced to GND and VCC. Do notallow pin SLO to float.
Link
A (Pin 18): Noninverting Link Transceiver Pin.
B (Pin 19): Inverting Link Transceiver Pin.
Rev 0

8

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LTC4331
BLOCK DIAGRAM
Local Mode
LINK

VCC
VL

SUPPLYMANAGER

SLO

ON
SCL

TX
FIFO

I2C
FRONT END

SDA

A

LINK
ENCODERB
LINK
CONTROLLER

RX
FIFO

LINK
DECODERALERTREMOTERDY

I2C
SLAVE DEVICEA1STATUSREGISTERSCONFIG

A2SPEED1

SPEED2CTRL

GND
4331 BDa

Remote Mode
LINK

VCC
VL

SUPPLYMANAGER

SLO

ON
SCL

TX
FIFO

I2C
FRONT END

SDA

A

LINK
ENCODERB
LINK
CONTROLLER

RX
FIFO

LINK
DECODERALERTREMOTECONFIG

RDY
A1

A2

SPEED1

SPEED2

VL
CTRL

GND
4331 BDb

Rev 0

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9

LTC4331
TEST CIRCUITSAADRIVER

IOSD

R

+
VOD
–

DRIVER

R

+
–

B

B

–60V TO 60V

4331 FO2
4331 FO1

Figure 1. Driver DC Characteristics

Figure 2. Driver Output Short-Circuit Current

IIN

VIN

+
–

A OR BB OR ARECEIVER

4331 FO3V
RIN = IN
IIN

Figure 3. Receiver Input Current and Input ResistanceA
CL
DRIVER

90%

(A–B)

RDIFF

10%

CL
B

0V

0V
tRD

90%
10%
tFD
4331 F04b

4331 FO4

Figure 4. Driver Timing Measurement

VL
RL

VL
1.5V

CL

0.65V

VOL

tF

4331 F05

Figure 5. SCL and SDA Driver Timing Measurement
Rev 0

10

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SCL

SDA

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LOCAL_nALERTREMOTE_nALERT

SDA

SCL

SDA

SCL

I2C STARTLOCAL_I2C

tHD:STAREMOTE_I2C

0.65V

1.5V

0.65V

1.5V

0.65VLtSU:DAT

0.8 VL
0.2 VL

0.2 VLt ALT_PROP

0.8VL

tHD:DAT

0.65VLt START_PROP

0.2VL

tDELAY

0.8 VLtDELAY

0.2 VL
0.5 VLtWIDTH

1.5V

tHIGH

tF

REMOTE_CTRL

LOCAL_CTRLtRDAT_PROP

Figure 8. Propagation Timing

0.8VL

tLDAT_PROP

0.2VL

0.65V

0.65V

REPEATED START

Figure 7. I2C Voltage Levels and Timing

tLOW

tR

tSU:STA

0.2VL

0.65V

tHD:STA

0.8VL

1.5V

tBUF

0.2VL

4331 FO6t STOP_PROP

1.5V

I2C STOPt CTRL_PROP

0.8VL

tSU:STO

Figure 6. Logic I/O Voltage Levels for Timing Specification (Except SCL and SDA)

0.8 VL4331 F08

4331 FO7

LTC4331

TIMING DIAGRAMS

Rev 0

11

LTC4331
APPLICATIONS INFORMATION
Overview
Two LTC4331 devices are required for a complete extended
I2C network. Using the REMOTE pin, one LTC4331 is configured to local mode and acts as a full-featured SMBus
compatible I2C slave device. Through this local interface
a master can address a remote slave device up to 1200m
away along a differential cable. On the remote network asecond LTC4331 configured to remote mode acts as an
I2C master device connected to the remote slave devices.
The master interface mirrors the local I2C transactions
on the remote network and transmits the remote slave
responses back to the local network. In most cases thelink is transparent; the remote slave devices appear as
local devices to a local master.
A separate addressable slave device contained in the local
side LTC4331 provides a control interface for optional
configuration and event monitoring of the link.
LOCAL MASTERµP

LOCAL SLAVE
SCL
SDA
ALERT
CTRL

DEVICELOCAL SLAVEREMOTE MASTER

LTC4331

LTC4331

REMOTE SLAVELOCAL MASTERµP

A
B
REMOTELOCAL SIDE

When operating as a slave-transmitter, the local LTC4331
must periodically stall the local I2C bus to account for
remote I2C bus and link latencies. It does this by clockstretching whenever a valid response is not yet available.
Therefore it is recommended that the local I2C master device fully support SCL clock-stretching for each
response (N)ACK and data bit. See section Considerations.
By using SCL clock-stretching to account for link andremote device latency, the local I2C clock rate is decoupledfrom the link baud rate and remote I2C clock rate. This
allows independent I2C bus rates between the local andremote networks.
Remote Mode

BREAK CONNECTIONS AND INSERT LTC4331 SOLUTIONLOCAL I2C BUS
MCU_SCL
MCU_SDAMCU_ALERTMCU_CTRL

differential link as an encoded bit-stream to a second
LTC4331 which is set to remote mode. After an I2C bus
turnaround, the device operates as a slave-transmitterand the differential link direction is reversed. The remote
LTC4331 transmits the response data measured from theremote I2C bus onto the twisted pair cable. The local side
LTC4331 then decodes the transmitted bit-stream into
I2C data events and drives them onto the local I2C bus.

TWISTED PAIRA
B
REMOTEREMOTE I2C BUS
REM_SCLREM_SDAREM_ALERTREM_CTRL

DEVICEVL
REMOTE SIDE

4331 F09

Figure 9. LTC4331 Solution Inserted Into an I2C Network.

Local ModeOn the local side, set the REMOTE pin low to put the
LTC4331 in local mode. In this mode the LTC4331 operates as a slave device. The I2C interface is designed tobe compatible with I2C Fast-mode Plus, Fast-mode, orStandard-mode class timing specifications selectableusing pins SPEED1 and SPEED2.
When operating as a slave-receiver the LTC4331 captures I2C START, STOP, and data events sent by a local
I2C master. The device transmits these events across theOn the remote side, set the REMOTE pin high to put the
LTC4331 in remote mode. In this mode the LTC4331
operates as an I2C master device. In normal operation
the remote master mirrors the I2C events produced by
the local I2C master. The device recreates the events using
Fast-mode Plus, Fast-mode, or Standard-mode class timing specifications. The timing class is selected by pins
SPEED1 and SPEED2.
The LTC4331 does not support multiple masters on the
remote I2C networks. The LTC4331’s I2C master device
interface is the only allowed master on the remote side
network. Remote slaves are also forbidden to switch
to master mode, for example as part of a host-notify
operation.
The LTC4331 master interface fully supports slave device
clock-stretching for all data bits in the packet.
I2C Transactions
A local master initiates a transaction by sending an I2C
START along with the slave address byte. The LTC4331
Rev 0

12

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LTC4331
APPLICATIONS INFORMATION
device, configured for local mode, encodes and transmits
the captured I2C events to the remote I2C network where
they are recreated on the remote I2C bus. If additional
LTC4331 devices configured as slaves, REMOTE set
low, are connected to the remote I2C network, they alsotransmit the events to the 3rd tier I2C network, and soon. The local side LTC4331 always holds SCL low on the
9th bit waiting for an (N)ACK response from the remoteslave device(s). When the local side LTC4331 receives the
response, SCL is released with the response data set on
the I2C bus. If the R/W bit is set to Write, the bus turns
around after the ACK and the local LTC4331 switches
back to slave-receive mode in order to capture the incoming write data. After the 8th SCL clock, the bus and link
direction reverse in order to retrieve the (N)ACK response
from the remote slave device. This sequence continues
until the master sends a START or STOP condition. Data
to be transferred across the link is stored in a buffer if thelocal I2C transaction is faster than the effective link rate.
See Figure 10.
If a local LTC4331 detects that all remote slaves have
NACK’d the slave address byte, it ceases transmitting further I2C data to the remote side until a STOP or REPEATEDSTART condition is detected. This feature prevents the
LTC4331 from stalling the bus unnecessarily when thetransaction is addressed to a separate local slave device.
Note that in this scenario, the remote side SCL is held low
until a STOP or START condition is detected. Unusuallylong cycle times could activate the tTIMEOUT condition.
In the case of a read transaction to a remote slave device,
the local LTC4331 slave device stalls the bus during theread data phase. During this time, the remote LTC4331
I2C master prefetches the next byte from the remote slave
device. The read data byte is transmitted across the differential link and stored in a local buffer. As bits become
available in the local buffer, the local LTC4331 drives them
onto SDA and releases SCL according to the configured
setup time tSU:DAT:SLAVE. After the complete byte has beenread, the I2C bus and differential link are turned around.
The local I2C master either ACKs or NACKs during thistime. If the master ACKs, the sequence is repeated. Thisbus and link direction is reversed, and the next byte isprefetched from the remote slave device. If the masterthen NACKs, the bus and link do not reverse direction.

The master is then expected to send a STOP or START
event. See Figure 11.
Differential Link
Internally, the LTC4331 utilizes a high performance RS485
compliant transceiver to communicate over the link. The
A and B pins are fault protected to ±60V. In addition, thetransceiver operates over an extended common mode
range of ±15V making it suitable for noisy environments
or systems with ground potential differences. Data is
exchanged between the LTC4331 devices using a custom
packet which has a selectable baud rate based on theconfiguration of the SPEED1 and SPEED2 pins. Selectablebaud rates over the cable allow balancing performancewith cable length specific to the application. Both sidesof the link must be set to the same speed configuration inorder to match the baud rates and allow communication.
The LTC4331 allows slew rate limiting over the differential
link outputs to reduce EMI in sensitive applications. Setting
the SLO pin low activates the slew rate limiting circuit.
Once in slew limiting mode, SPEED1 and SPEED2 pins
must only be configured for Speed Index 0 or 1. Setting
SPEED1/2 to a speed index of 2 or higher when SLO is low
results in link data corruption regardless of cable length.
The LTC4331 I2C slave device extension solution is pointto-point only. Multidrop or multipoint configurations on
the differential link are not allowed.
±40kV ESD Protection
The LTC4331 features exceptionally robust ESD protection. The link interface pins (A, B) feature protection to±40kV HBM with respect to GND, VCC (with a 4.7μF capacitor to GND), A or B without latchup or damage, during allmodes of operation or while unpowered.
Level 4 IEC ESD and EFT Protection
The improved ESD protection of the LTC4331 provides ahigh level of protection in the IEC ESD and EFT (Electrical
Fast Transient) tests. The IEC ESD stress exceeds that of
the HBM test in peak current, amplitude, and rise time,
while the EFT test provides a prolonged repetitive stress.
Combined with the HBM test, the IEC tests help ensurethat the LTC4331 is robust under a wide range of real

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Rev 0

13

14

REMOTE

LOCAL

SCL

SDA

SCL

SDA

START

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REMOTE

LOCAL

SCL

SDA

SCL

SDA

START

ADDRESS/WR

FROM SLAVE TO MASTERFROM MASTER TO SLAVESTARTFROM SLAVE TO MASTERFROM MASTER TO SLAVESTARTADDRESS/RD

ADDRESS/WR

ADDRESS/RD

ACK

ACK

ACK

Figure 11. Full Read

ACK

LTC4331 HOLDS SCL LOW
UNTIL ACK IS RECEIVED

Figure 10. Full Write

LTC4331 HOLDS SCL LOW
UNTIL ACK IS RECEIVEDREAD BYTEWRITE BYTE

READ BYTEWRITE BYTE

NACK

ACK

STOP

NACK

ACK

STOP

STOP

4331 F11

STOP4331 F10

LTC4331APPLICATIONS INFORMATION

Rev 0

LTC4331
APPLICATIONS INFORMATION
world hazards. The LTC4331 passes the following tests
on the A, B pins:

Link status can also be monitored using the control interface. See section Control Interface.

•

Ensure that the values set on local side SPEED1 andSPEED2 pins match the values set on remote side. Also,
do not exceed the cable length listed in Table 2 for the
given SPEED setting. The LTC4331 will not link if these
conditions are not met.

•

IEC 61000-4-2 Edition 2.0 2008-12 ESD Level 4: ±8kV
contact (A or B to GND, direct discharge to bus pinswith transceiver and protection circuit mounted on atest card with a low impedance ground discharge pathfrom board GND to ESD gun return lead, per Figure 4of the standard)
IEC 61000-4-4 Second Edition 2004-07 EFT Level 4:±5kV (A or B to GND, 5kHz repetition rate, 15ms burst
duration, 60 second test duration, discharge coupled
to bus pins through 100pF capacitor per paragraph7.3.2 of the standard). VCC pin requires a low inductance capacitor of at least 4.7µF to meet Level 4 rating.

Startup and Shutdown
Startup occurs when supply voltages are applied to pins
VCC and VL and the ON pin is high. All output pins are tristated during the first part of startup. After an initialization
sequence, the I2C interface and other pins are functional.
The local side LTC4331 monitors the I2C bus for inactivity
and probes the differential link. When the device detects
an idle condition on the local I2C bus, it drives pin RDY
low to indicate that it is ready to respond to I2C transactions. Thereafter a master can access the internal control
interface. In addition, once the device establishes linkcommunication with a remote LTC4331, it drives pin LINK
low and the remote I2C network can be accessed.
The ON pin can be used to set the LTC4331 to a lower
power state. By setting ON low, the LTC4331 is held inreset, all programmed configuration is set to the default
value, all output drivers are disabled, and the differential
transceiver is put into low power mode. If not used, tie
ON to VL.
Link Status
The LTC4331 provides the LINK pin which indicates if theremote I2C network has joined with the local I2C network.
LINK is driven low when bidirectional link communication is established and the I2C interface is ready. It is an
open-drain output and requires an external pull-up to VL
if used. At startup, the LINK pin output driver is disabled.

Note that the link status is indeterminate if the REMOTE
pin is incorrectly configured on either the local or remoteside LTC4331 device.
Ready Status
The RDY pin is driven low when the local side LTC4331
control interface is ready for access. It is an open-drain
output and only valid in local mode. When the device isfirst powered and pin ON is set high, the low output driveron RDY is disabled and the pin is weakly pulled to VL. An
internal I2C bus idle detection circuit prevents the interface
from interrupting an active transaction. This circuit drives
RDY low when either pin SCL is high for tREADY:IDLE or it
detects an I2C STOP which indicates the interface is readyand has joined the bus. The status of the link connection
does not affect the ready function. If pin LINK is high when
RDY is low, only the local side LTC4331 control interface
is available for access. The RDY pin is internally pulled to
VL. It is valid only in local mode.
A secondary function of RDY indicates if the internal buffer has filled, see section Considerations for more detail.
Interrupt/SMBALERTThe LTC4331 supports an interrupt signal that is mirroredfrom the remote network to the local network using thedifferential link. On the remote side ALERT is an input pinthat can be connected to remote I2C slave devices. Whileon the local side ALERT operates as an open-drain typeoutput that can be connected to a shared local interrupt
line. ALERT is periodically sampled and has a propagation
time of tALT_PROP.
If enabled, the local LTC4331’s control interface uses the
ALERT pin to report link and fault events. The local side
ALERT output is the logical AND of the remote ALERT and
the internal endpoint interrupt signal.
Rev 0

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LTC4331
APPLICATIONS INFORMATION
By default the local addressable slave device in the LTC4331
recognizes the Alert Response Address (ARA) and participates in the Alert Response protocol. If an EVENT is
triggered and its corresponding ALERT_EN bit is set high,
ALERT is driven low. If the master transmits the Alert Response protocol and the LTC4331’s internal slave addressis the lowest numerically, then the LTC4331 releases its
local alert output. Note that local ALERT could continue
to be low due to a low value from a remote ALERT pin.
The remote ALERT function in the LTC4331 is not directly
affected by an Alert Response transaction. The signal on
the remote ALERT pin is always propagated to the local
side if connected. If using SMBus slave devices on bothsides of the link that respond to the ARA, the remoteslaves must have higher priority device addresses thanthe devices on the local side, see section Considerations.

programmed into the bit field SW_CTRL. A separate bit
field CTRL_SEL selects pin or register control. By default
the value on local CTRL pin is used. Local CTRL values
transfer to the remote side CTRL only when the communication link is established and pin LINK is low.
At startup the CTRL output driver is disabled and a weakinternal pull-up prevents the pin from floating. The CTRL
pin’s output driver enables only when link communication isestablished. Thereafter, the remote CTRL pin’s output driveris always enabled except after a remote reset event where
it is disabled until link communication is reestablished.
I2C Address Translation

The LTC4331’s internal slave device can be programmed
to ignore the ARA and switch the function of pin ALERTfrom SMBALERT to interrupt mode. To switch to interrupt
mode set INTR_MODE in the CONFIG register to 1. To
clear the interrupt set the triggered event or the corresponding event enable bit to 0. This method is also valid
in SMBALERT mode in lieu of the ARA protocol.

The address translation feature allows the use of multiple
I2C slave devices with fixed or limited device address
ranges on the same network. The LTC4331 I2C slave device
automatically translates the incoming address using an
XOR function against the internal register ADDR_TRANS.
Address translation is enabled by setting this register toa non-zero value. ADDR_TRANS must be programmed
before any accesses to the remote slave if that slave
requires address translation or there will be a collision.
See Figure 12.

Control

Timeouts

Through the CTRL pin, the LTC4331 provides an additional signal to control a remote device’s input pin. Whenin remote mode, the CTRL pin is an output and reflects
the value either on the local side CTRL pin or the value

The LTC4331 respects SMBus SMBCLK low timeouts on
the SCL pin. When in local mode and SCL is held low for aminimum of tTIMEOUT:SLAVE:MAX, the I2C Interface is reset
and SCL and SDA are released if held low. On the remote

LTC4331
µP
SCL

SCL

ADDR = 0x10
ACK

SDA

SDA

0
0
1
0
0
0
0

0
0
0
0
1
1
0

INCOMING
ADDR

NACK

DEVICEREMOTE

LTC4331
0
0
1
0
1
1
0

A

A

B

B

SCL

REMOTE SLAVEADDR = 0x16

SDA

ACK

DEVICEADDR = 0x16

OUTGOING
ADDR

ADDR_TRANSREGISTERREMOTE
4331 F12ADDR = 0x16
LOCAL SLAVE

Figure 12. Address 0x10 Is Translated to 0x16 for the Remote Device
Rev 0

16

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LTC4331
APPLICATIONS INFORMATION
Considerations•

In addition, the local side LTC4331 slave interface contains
an SDA stuck-low prevention circuit which ensures the
LTC4331 does not hold SDA low when the I2C bus is idle.
This typically occurs when there is a loss of I2C protocol
synchronization between the master and slave devices.
If the LTC4331 is holding SDA low while SCL is high for
35ms, the interface is reset and SDA is released.

Table 1. Known I2C Master Devices Incompatible with
LTC4331 SCL Clock-Stretching

Remote Stuck Bus Protection
On the remote side, the LTC4331 master device can detectand attempt recovery from I2C bus faults. If the masterdevice senses that SDA is low when it should be high,it considers SDA stuck by a slave device. The LTC4331
enters a bus recovery routine which drives 16 SCL clocks
onto the bus and then issues a STOP event. This routine
is also entered if SDA is sensed low after a startup. If
successful, the LTC4331 master then ignores further
local I2C bus transactions until the local bus transmits a
STOP condition. If the routine is unsuccessful, it retries
whenever a local side master initiates a new transaction.
If the remote LTC4331 detects that SCL is stuck, it automatically NACKs all I2C transactions from the local bus
until it measures SCL high and receives a STOP commandfrom a local I2C master.
For both SCL and SDA fault conditions, the remote
LTC4331 sends a FAULT response to the local LTC4331
which sets the EXT_I2C_FAULT EVENT bit.
Remote Reset
The local side LTC4331 can trigger a remote side LTC4331
reset by holding the ON pin low for a minimum of tREMOTE_RESET. In addition, the remote LTC4331 is automatically
reset after tREMOTE_RESET if the link is disconnected. A
remote reset disables all remote side outputs, including
pin CTRL, until link communication is reestablished.

The LTC4331 relies on SCL clock-stretching to accountfor link and remote bus latencies. Using a local master,
either hardware or software based, that fully supports
clock-stretching is highly recommended for best performance. Alternately, the SCL frequency can also be
reduced such that the LTC4331’s SCL configured
low time and remote response time is less than themaster’s programmed SCL low time. The total clockstretching time of the local LTC4331 I2C slave device
depends on SPEED1 and SPEED2 pin settings andremote I2C Slave device timing requirements. This is
not recommended. See Figure 13.

DEVICE

ISSUE

WORKAROUND

All Raspberry Pi
models (Broadcom
BCM283X)

Hardware I2C
peripheral clockstretching issues

Use software based
I2C that fully supports
SCL clock-stretching

Analog Devices
DC590B QuikEval
controller

SCL signal path isnot bidirectional

Use Analog Devices
Linduino® w/DC590
sketch•The LTC4331 I2C Slave Extender does not support
remote I2C devices acting as masters. Therefore the
SMBus Address Resolution Protocol and Host Notify
Protocol are not supported.

•

When using SMBus ARA, if there are SMBus slave
devices on the local and remote side of the extender,
100

30m
600m

SCL FREQUENCY (kHz)side, the LTC4331 acting as an I2C master also releases
SCL and SDA if an remote slave is signaling a timeout. In
addition, the LTC4331 master sends a STOP event andrequires a local side STOP event before allowing further
remote I2C transactions. This ensures the local and remote
are synchronized.

10

4

5

6
SPEED INDEX

784331 F13

Figure 13. SCL Frequency Range when the I2C
Master Ignores Slave SCL Low Stretching

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Rev 0

17

LTC4331
APPLICATIONS INFORMATION
all local slave device addresses must be greater (lower
priority) than the remote slave device address. This is
to allow proper slave address negotiation.
•

Care must be taken when interrupting an I2C transaction
with a START or STOP. A START or STOP can only be
issued when the local side LTC4331 is in slave-receive
mode. Since internally the data is sampled on the risingedge, the local I2C bus is considered slave driven after
the last rising edge of SCL in a master driven data cycle.

•

The LTC4331 supports a faster local I2C clock rate
relative to the effective link rate. The device has a fixed
length internal buffer to hold a complete byte as it istransferred across the link at the rate set by SPEED1and SPEED2. During this time the local I2C bus stalls
preventing further I2C data from entering the buffer.
If however, a local master sends multiple consecutive START/STOP commands faster than the effective
link rate, this buffer can overflow. The LTC4331 provides two status indicators for this event. First, if thebuffer is full, then RDY rises indicating that the local
I2C interface is not ready and further START, STOP, orwrite data event can be lost. Second, a TX_BUFFER_OVERFLOW FAULT event occurs if a local master
writes additional I2C events while RDY is high.

•A remote slave device will not see a SCL timeout condition (bus reset) initiated by a local slave device if aremote device is not the target of the local Master.

Link Speed
The link baud rate is set using the SPEED1 and SPEED2
pins as shown in Table 2. Column I2C Class shows thetiming mode set on the local and remote I2C interfaces.
The Effective I2C Link Rate shows the rate I2C data propagates across the link. The local SCL frequency can exceed
this rate though increased clock-stretching times occur
as the Effective Link Rate decreases relative to the local
SCL frequency. The SPEED INDEX must be set to the samevalue on each side of the link.
Table 3. Speed Factors
SPEED INDEXSPEED FACTOR (SF)

8

1×

7

2×

6

4×

5

8×

4

10×

3

16×

2

32×

1

50×

0

80×

Control Interface
The LTC4331 contains an addressable slave device providing a control interface for configuration and monitoring. The internal slave is enabled by configuring pins A1
and A2 to assign the device a unique I2C address. When

Table 2. Link Speed
EFFECTIVE I2C
LINK RATEMAX CABLELENGTH (m) (Note 2)

SLEW RATE LIMITINGOPTION (Note 3)

Fm+

1MHz

30

No

Fm

500kHz

60

No

6

Fm

250kHz

200

No

5

Fm

125kHz600

NoSPEED1(Note 1)

SPEED2(Note 1)

SPEED INDEXI2C CLASS

L

L

8

Float

L

7

H

L

L

Float

L

H

4

Sm

100kHz

1200

No

H

Float

3

Sm

63kHz

1200+

No

Float

Float

2

Sm

31kHz

1200+

No

Float

H

1

Sm

20kHz

1200+

Yes

H

H

0

Sm

12.5kHz

1200+

Yes

Note 1: For assignments to float, 0.5 • VL can also be applied to pin.
Note 2: Evaluated with Cat5E Ethernet cable in a lab environment. Actual maximum cable length depends on type of cable and application environment.
Note 3: Using SLO.
Propagation times across the link for the SYSTEM timing specifications are based on the SPEED1 and SPEED2 pins.
Rev 0

18

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LTC4331
APPLICATIONS INFORMATION
both pins are unconnected, the internal slave is disabled.
The internal slave device recognizes the SMBus Write Byte
and Read/Receive Byte protocols with or without Packet
Error Correction (PEC) as shown in Figures 14 to 19.
S

The PEC byte is calculated as a CRC-8 checksum over all
bytes between the START and STOP conditions excluding
the ACK/NACK and Sr bits and last CRC byte. The polynomial used is x8 + x2 + x + 1 initialized to zero.

DEVICE ADDRWAREGISTER

A

DATA

A

3Eh

0

0

00h

0

01h

0

P
4331 F14

DEVICE ADDRESS = 3Eh. ACCESSING THE CONFIG REGISTERFROM MASTER TO SLAVE

S: START
Sr: REPEATED STARTFROM SLAVE TO MASTER

W: WRITE BIT (ACTIVE LOW)
A: (N)ACK BIT
P: STOP

Figure 14. Write Byte
S

DEVICE ADDRWAREGISTER

A

DATA

A

PEC

A

3Eh

0

0

00h

0

01h

0

9Ah

0

P
4331 F15

Figure 15. Write Byte + PEC
SDEVICE ADDRWAREGISTER

A

3Eh

0

0

00h

0

Sr

DEVICE ADDR

W

A

DATA

A

3Eh

1

0

01h

1

P
4331 F16

Figure 16. Read Byte
S

DEVICE ADDRWAREGISTER

A

3Eh

0

0

00h

0

Sr

DEVICE ADDR

W

A

DATA

A

PEC

A

3Eh

1

0

01h

0

96h

1

P
4331 F17

Figure 17. Read Byte + PEC
SDEVICE ADDR

W

A

DATA

A

3Eh

1

0

01h

1

P
4331 F18

Figure 18. Receive Byte
S

DEVICE ADDR

W

A

DATA

A

PEC

A

3Eh

1

0

01h

0

4Ch

1

P
4331 F19

Figure 19. Receive Byte + PEC

Rev 0

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19

LTC4331
APPLICATIONS INFORMATION
PEC transfers are recommended in high noise environments or high reliability systems.

Register Naming Conventions
RW

Read-Write

Table 4. Device Address

RO

Read Only

W0C

Write Zero to Clear

A1 (Note 1)A2 (Note 1)

DEVICE ADDR (7-Bit)

L

L

3Eh

Float

L

3Ch

H

L

3Fh

L

Float

3Dh

H

Float

75h

L

H

76h

Float

H

74h

H

H

77h

Float

Float

Internal Slave Device is Disabled

Note 1: For assignments to Float, 0.5 • VL can also be applied to pin.

Table 5. Register Map
REGISTER

NAME

DATA

00h

CONFIG

01h

STATUSDEFAULT

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

–

–

–

–

–

–

CTRL_SELINTR_MODE

0x00

Reserved

EXT_NALERTNALERTNLINK–SPEED_IDX

02h

EVENT

–

–

–

–

–

FAULT

LINK_LOST

LINK_GOOD

0x00

03h

ALERT_EN

–

–

–

–

–

FAULT_EN

LINK_LOST_EN

LINK_GOOD_EN

0x00

04h

FAULT

–

–

–

–

LINK_FAULT

I2C_WRITE_FAULT

05h

SCRATCH

06h

ADDR_TRANS

–

07h

CTRL

–

TX_BUF_OVERFLOW EXT_I2C_FAULTSCRATCHI2C_TRANS

–

–

–

–

0x00
0x08
0x00

–

–

SW_CTRL

0x00

CONFIG Register (RW)FIELD

DESCRIPTIONINTR_MODE

When low, the internal slave interrupt behavior on pin ALERT is SMBALERT. The internal slave device recognizes and responses toan ARA. When high, the internal slave device ignores the ARA.

CTRL_SEL

When low, the local CTRL pin input is mirrored to the remote CTRL output pin. When high, the value in register CTRL is used instead.

STATUS (RO)FIELD

DESCRIPTIONNLINKThe level driven by pin LINK. High impedance is interpreted as 1.

NALERT

The level driven by the local side pin ALERT. High impedance is interpreted as 1.

EXT_NALERTThe level driven into the remote ALERT pin. Link must be established.

SPEED_IDX<0-8>. Encoded index from values set on SPEED1 and SPEED2. See Table 2. Link Speed.

Rev 0

20

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LTC4331
APPLICATIONS INFORMATIONEVENT (W0C): Events Are Set by the System and Cleared by the User
FIELD

DESCRIPTIONLINK_GOOD

The local and remote I2C networks are connected.

LINK_LOST

The local and remote I2C networks have lost link communication.

FAULT

Set if any field in the FAULT register is set by the system. Clearing this bit clears all bits in the FAULT register.

ALERT_EN (RW): Asserts ALERT if Corresponding EVENT Bit Is Set
FAULT (RO): If the FAULT EVENT Bit Is Set, at Least One of the Following Bits Is Set.
To Clear, Clear the FAULT Event Bit
FIELD

DESCRIPTIONI2C_WRITE_FAULT

An incomplete write transaction after the internal address byte or PEC error detected.

LINK_FAULT

Link communication corruption detected.

EXT_I2C_FAULT

A fault, or stuck bus recovery occurred on the remote I2C bus.

TX_BUF_OVERFLOW The transmit buffer overflowed, I2C events lost.

SCRATCH (RW)FIELD

DESCRIPTIONSCRATCH

Used to test read/write access to the control interface.

ADDR_TRANS (RW)FIELD

DESCRIPTIONI2C_TRANS

Incoming 7-bit I2C addresses are translated to the remote network by: AddressOUT = I2C_TRANS XOR AddressIN

CTRL (RW)FIELD

DESCRIPTION

SW_CTRL

Sets the output value of the remote CTRL pin when CTRL_SEL is high.

PCB Layout
A ground plane layout is recommended. A 4.7μF bypass
capacitor should be placed no more than 7mm away fromthe VCC pin. The PC board traces connected to signals A
and B should be symmetrical and as short as possible tomaintain good differential signal integrity. Route the differential signals A and B as an edge coupled microstrip
with a differential impedance approximately matching thecable impedance.
Link Termination and Biasing
To minimize the transmission line reflections over thelink, a termination resistor should be connected between
pins A and B at each node. Each resistor’s value shouldclosely match the characteristic impedance of the differential cable to reduce reflections.
A bias resistor network should also be inserted at eachnode to maintain the idle state during link turnaroundwhen all drivers are momentarily disabled. See Figure 20.
For DC-coupled (non-isolated) link applications, select RB
and RT2 such that 200Ω ≤ RB ≤ 620Ω and 100Ω ≤ RT2≤ 110Ω.
Isolation
Galvanically isolating the link is supported with the
LTC4331 allowing applications with safety requirements
or applications with independent ground potentials. A bias
network along with termination resistors must be used

For more information www.analog.com

Rev 0

21

LTC4331
APPLICATIONS INFORMATION
on both sides of the link. For transformer applications,series resistors must be added to the A and B pins oneach side of the link. Use resistor values from 25Ω to50Ω. See Figure 21.
Table 6. Typical Resistor Values for Transformer Applications
VCC (V)RB (Ω)RS (Ω)

RT2 (Ω)

3.3

200

25

110

5.0

270

50

110

For capacitive isolation, select RB such that 200Ω ≤ RB ≤320Ω. C = 1μF rated capacitors support all SPEED INDEX
values. Smaller value capacitors can be used if the application only utilizes higher SPEED INDEX values. Ensure
the capacitors’ working voltages are much higher than the
expected ground offset voltage. See Figure 25.
Multiple Local Extender Network
Multiple LTC4331 devices operating in slave device modecan be connected to the same local SMBus network unlike
other extension solutions which typically restrict usage to
one extender device. This allows a star network of parallel LTC4331 devices extending separate remote SMBus
networks.
LINK indicates when the remote system is ready. OptionallyRDY can also be monitored to determine when the local
side control interface is ready to access in the absence ofa link. See Figure 23.

Auxiliary Protection for 5kV Surge, 5kV EFT, and 30kV
IEC ESDAn interface transceiver used in an industrial setting
may be exposed to extremely high levels of electricaloverstress due to phenomena such as lightning surge,
electrical fast transient (EFT) from switching high current inductive loads, and electrostatic discharge (ESD)from the discharge of electrically charged personnel orequipment. The LTC4331 is designed for high robustness
against ESD, but the on-chip protection is not able toabsorb the energy associated with the 61000-4-5 surgetransients. Therefore, a properly designed external protection network is necessary to achieve a high level ofsurge protection, and can also extend the ESD and EFT
performance of the LTC4331 to extremely high levels.
Refer to section Auxiliary Protection for IEC Surge,
EFT and ESD on page 17 of Analog Devices LTC2862A
Datasheet for a detailed description and diagram of theexternal protection network.
The network provides the following protection:•

EC 61000-4-2 ESD Level 4: ±30kV contact, ±30kV air(line to GND, direct discharge to bus pins with transceiver and protection circuit mounted on a groundreferenced test card per Figure 4 of the standard)•

IEC 61000-4-4 EFT Level 4: ±5kV (line to GND, 5kHz
repetition rate, 15ms burst duration, 60 second test
duration, discharge coupled to bus pins through100pF capacitor per paragraph 7.3.2 of the standard)•

IEC 61000-4-5 Surge Level 4: ±5kV (line to GND,
line to line, 8/20µs waveform, each line coupled togenerator through 80Ω resistor per Figure 14 of thestandard)

Multi-Tier Extender Network
The LTC4331 also supports chaining remote segments
into a single multi-tiered network. The maximum depth of
the I2C link network is limited only by the tTIMEOUT parameters of the I2C devices on the network. As the depth
increases, the clock-stretched low time of the devices
increases. No other I2C timing parameter is affected bydepth. See Figure 24.
Table 7. Recommended Transformers
MANUFACTURERPART NUMBER

ISOLATION VOLTAGE

CENTER TAP

CM CHOKE

SPEED INDEX SUPPORTED

Murata78601/9JC

1kVRMS

No

No

ALL

Pulse

PE-68386NL

1500VRMS

No

No

3, 4, 5, 6, 7, 8

Rev 0

22

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LTC4331
APPLICATIONS INFORMATION
VCC
LTC4331

VCC2
LTC4331

RB

RB

RT2

RT2

RB

RB

A

A

B

B

4331 F20

V GROUND LOOP
≤15V PEAK

Figure 20. Resistor Bias Network

VCC
LTC4331

VCC2

RB
A
RT2
B

RS

RS

RS

RS

LTC4331

RB
A
RT2
B
RB

RB

4331 F21

Figure 21. Transformer Application Resistor Network

VCC
LTC4331

RB

VCC2
C

LTC4331

RB

A

A
RT2

RT2

B

B
RB

C

RB
4331 F22

Figure 22. Capacitive Isolation Resistor Network

Rev 0

For more information www.analog.com

23

LTC4331
TYPICAL APPLICATIONSµP

LTC4331
SCL
SDA
GPI
GPO

SCL
SDA
ALERT
CTRL
REMOTESPEED1
SPEED2A1A2

LTC4331

A

25m

B

B

LTC4331
SCL
SDA
ALERT
CTRL
REMOTESPEED1
SPEED2
A1
A2

SCL
SDA
ALERT
CTRL
REMOTE

A

SPEED1
SPEED2I2C SLAVEDEVICE

LTC4331

A

600m

B

SCL
SDA
ALERT
CTRL
REMOTE

A
B

SPEED1
SPEED2I2C SLAVEDEVICE

4331 F23

Figure 23. Multiple Local Extender NetworkµP

LTC4331
SCL
SDA
GPI
GPO

SCL
SDA
ALERT
CTRL
REMOTESPEED1
SPEED2A1A2

LTC4331

A
B

25m

A
B

LTC4331

SCL
SDA
ALERT
CTRL
REMOTE

SCL
SDA
ALERT
CTRL
REMOTESPEED1
SPEED2SPEED1
SPEED2
A1
A2

I2C SLAVEDEVICE

LTC4331

A
B

600m

A
B

SCL
SDA
ALERT
CTRL
REMOTESPEED1
SPEED2I2C SLAVEDEVICE

4331 F24

Figure 24. Multi-Tier Extender Network

Rev 0

24

For more information www.analog.com

LTC4331
PACKAGE DESCRIPTIONUFD Package
20-Lead Plastic QFN (4mm × 5mm)

(Reference LTC DWG # 05-08-1711 Rev B)

0.70 ±0.05

4.50 ±0.05
1.50 REF
3.10 ±0.05

2.65 ±0.05
3.65 ±0.05

PACKAGE OUTLINE

0.25 ±0.05
0.50 BSC
2.50 REF
4.10 ±0.05
5.50 ±0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONSAPPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
4.00 ±0.10(2 SIDES)

0.75 ±0.05

PIN 1 NOTCH
R = 0.20 OR
C = 0.35

1.50 REF

R = 0.05 TYP

19

20
0.40 ±0.10

PIN 1
TOP MARK(NOTE 6)1
2
5.00 ±0.10(2 SIDES)

2.50 REF
3.65 ±0.10
2.65 ±0.10(UFD20) QFN 0506 REV B

0.200 REF
0.00 – 0.05

R = 0.115
TYP

0.25 ±0.05
0.50 BSC

BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATIONON THE TOP AND BOTTOM OF PACKAGE

Rev 0Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license For
is granted
implication orotherwise under any patent or patent rights of Analog Devices.
more byinformationwww.analog.com

25

LTC4331
TYPICAL APPLICATION
2.7V TO 5.5V

CH0
CH1

CH2

IN+

4-CHANNEL
MUX

IN–

CH3

1µF

VCC

LTC2493

2.7k

2.7k

24-BIT ∆∑ ADC
WITH EASY-DRIVE
REF–

10k

CA1
CA0

COM

ALERT
SPEED2SPEED1

fO

OSC

A2
A1

TEMPERATURESENSOR

4.7µF

VCC
620Ω

REMOTESDA
SCL
LTC4331
ON
SLO

SDA
SCL

REF+

VL

A
110Ω
B
620Ω
LINK
RDY
CTRL

GND

EEPROM
REMOTE MEASUREMENT DEVICE

3.3V TO 5V
4.7µF

VCC

1µF

VL

620Ω
A
LTC4331

110Ω
B

10k

ALERT
SPEED2SPEED1

620Ω
A2
A1
LINK
RDY
CTRL

ON
SLO

2.7k

SDA
SCL
REMOTE
GND

2.7k
µP

4331 F25

Figure 25. Extending an LTC2439 4-Channel ADC for Remote Measuring

RELATED PARTS
PART NUMBER

DESCRIPTIONCOMMENTS

LTC4316/LTC4317/
LTC4318

Single I2C/SMBus Address Translator

Resistor Configurable, 2.5V, 3.3V, and 5V Busses

LTC4312/LTC4314

Pin-Selectable, 2-Channel, 2-Wire Multiplexer with Bus
Buffers

Two or Four Pin Selectable Downstream Busses, VIL Up to 0.3V • VCC,
Rise Time Accelerators, 45ms Stuck Bus Disconnect and Recovery,±4kV HBM ESD

LTC4305/LTC4306

2-Channel, 2-Wire Bus Multiplexer with Capacitance
BufferingTwo or Four Software Selectable Downstream Busses, Stuck Bus
Disconnect, Rise Time Accelerators, Fault Reporting, ±10kV HBM ESD

LTC4310

Hot-Swappable I2C Isolators

Bidirectional I2C Communication between Two Isolated Busses

LTM2892

SPI/Digital or I2C µModule Isolator

3500VRMS Isolation, 6 Channels

SPI/Digital or I2C µModule Isolator with Adjustable ±12.5V

2500VRMS Isolation with Power in BGA Package

LTM2883/LTM2886/
and 5V Regulated PowerLTM2887

Rev 0

26

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