A STUDY ON TIMING-DRIVEN PLACEMENT AND
ROUTING ALGORITHMS IN VLSI LAYOUT DESIGN

December 1997

Tetsushi Koide

A STUDY ON TIMING-DRIVEN PLACEMENT AND ROUTING ALGORITHMS
IN VLSI LAYOUT DESIGNA Dissertation
by
TETSUSHI KOIDE

Dissertation submitted to the Graduate School of Engineering ofHiroshima University in partial fulfillment of the requirements
for the degree of DOCTOR OF ENGINEERTING

December 1997

To my parents
Shigemi and Ikuko Koide, andTo myfamily
Mari and Syusuke Koide

Al,stract
Advancements in semi-conductor technology has made it possible for VLSI circuits to containeven millions of gates. In addition, we expect VLSI circuits to realize better and wider performance, resulting in requiring faster operational speed and higher clock frequency. This, in turn,makes interconnection delays in wiring appear as another major factor that cannot be neglectedin evaluating the performance of a chip. Therefore layout design can no longer disregard interconnection delays against gate delays, and there is an urgency to develop timing-driven layout
tools which do explicitly take interconnection delays into account.
The main goal of this dissertation is to propose the timing-driven placement and global routing algorithms for two typical layout styles available to us: the one is the standard cell layoutstyle mainly used for designing ASICs, and the other is the building block layout style used
for designing microprocessors etc .. The proposed algorithms avoid violation of timing requirements of a VLSI circuit so as to prevent decline in the performance of the circuit. They also
minimize the chip area and the total wire length by estimating the routing area during placement
and global routing. Consequently, the proposed algorithms can produce layout design of a VLSI
circuit, without any violation of the timing requirement, in short turn-around-time.
Chapter 1 gives a general introduction to the VLSI layout design and the timing-driven layout
problem, and addresses the objectives of this dissertation. The timing-driven layout design forthe standard cell layout is discussed in Chapter 2 to Chapter 4, and that for the building blocklayout in Chapter 5.
In Chapter 2, the placement problem for the standard cell layout is discussed and a path-based timing-driven placement algorithm is proposed based on hierarchical partitioning andnonlinear programming with the Elmore delay model. Moreover, to reduce the computation
time further, the proposed placement algorithm is extended to a parallel algorithm running on amulti-processor workstation with shared memory. Its effectiveness is shown through numericalexperiments.
The global routing problem for the standard cell layout is examined in Chapter 3; a pathbased timing-driven global routing algorithm is proposed considering the channel density minimization with Elmore delay. In order to effectively utilize the over-the-cell area, the proposed
algorithm is extended to take the over-the-cell routing into account. Experimental results arealso shown to demonstrate the effectiveness of the proposed algorithm.
In Chapter 4, the detailed routing problem for the standard cell layout that makes use of thevover-the-cell area is treated, referred to as over-the-cell channel routing. Since the conventional
standard cell models were originally developed not for over-the-cell channel routing but rather
for conventional channel routing, they are not always suitable for the former. Thus, new standard
cell models are proposed, which are suitable for the over-the-cell routing, and new over-thecell channel routing algorithms are devised for the proposed cell models. Simulations havedemonstrated the effectiveness of the proposed routers. The proposed algorithms can be also
applied to conventional as well as the proposed cell models and can produce the comparable
results for the conventional cell models to the conventional routers.
Chapter 5 deals with several layout problems for the building block layout, such as ftoorplanning, pin assignment, and global routing. In the building block layout, there are two typesof blocks, that is, hard blocks and soft blocks. For the former, they are pre-designed and theshapes and pin positions of the blocks are pre-determined. On the other hand, since they are
not pre-designed in the latter, it is needed to specify the exact shapes and pin positions in thelayout design. Thus, a timing-driven ftoorplanning algorithm is newly proposed to determine
the shapes of soft blocks as well as the positions of blocks so as to minimize the chip area. For
pin assignment and global routing, as opposed to conventional approaches, pin assignment andglobal routing problems are combined into one problem so as to reduce the chip area, and atiming-driven algorithm integrating global routing and coarse pin assignment is proposed. The
proposed algorithm can also determine the shape and the position of soft blocks. Finally, channel
pin assignment is discussed and an optimal algorithm is proposed for the channel pin assignment
problem, which minimizes both the channel density and total wire length. Experimental results
for the industrial circuits show that the proposed algorithms are efficient and effective.
Finally, Chapter 6 summarizes the results of this dissertation and discusses topics related tofuture research.

VIAcknowledgments
During the course of this work, I have been fortunate to have received assistance from many
individuals. I especially would like to thank my supervisor Professor Hiroshi Sasaki for his
continuing support, encouragement and guidance for this work. I would also like to thank Professor Noriyoshi Yoshida and Associate Professor Shin'ichi Wakabayashi for his invaluable
coordination and support throughout the research work for this dissertation. I also thank Associate Professor lun'ichi Miyao of Hiroshima University for his support in my graduate schooldays, and also thank Technical Instructor Mr. Morishige Teruhira of Hiroshima University for
his friendly help and support.
I am very grateful to the member of my dissertation reviewing committee: Professor Tadashi
Ae, Professor Kenichi Morita and Professor Toshimasa Watanabe for their careful reading andinvaluable comments of this dissertation.
I also thank other past and present faculty members, Professors Takao Hinamoto, Tadao
Ichikawa, Kousei Iwase, Makoto Kaneko, Mitsuo Nagamachi, Akira Nakamura, Nobuto Nakamura, Mitsuo Ohta, Kenji Onaga, Shunji Osaki, Masatoshi Sakawa, Noriaki Setoh, Hideo Yamashita and Masafurni Yamashita for their guidance and lectures throughout my graduate school
career and for their valuable discussions.
I have also received many insightful comments and valuable discussions through the private
communication. In particular, I would like to acknowledge Dr. Toru Awashima, Ms. Naoko
Emura, Dr. Takashi Fujii, Dr. Nobuyuki Nishiguchi, Dr. Tsuneo Matsuda, Dr. Kazuhiko
Takamizawa, and Dr. Noriyoshi Yonezawa ofNEC Corporation, Mr. Masafurni Masuyama, Mr.
Nobuhito Ono, Mr. Takahiro Ozasa, and Mr. Kokoro Katou of Seiko Instruments Inc., Mr. Yutaka Tamiya of Fujitsu Laboratories Ltd., Prof. M. D. F. Wong of The University of Texas atAustion, Prof. 1. G. Tollis of The University of Texas at Dallas, Prof. C-K Cheng of The University of California, Sandiego, Prof. 1. Cong and Prof. A. B. Kahng of University of California,
Los Angeles, Prof. Carl Sechen of University of Washington, Dr. Bill Swartz of TimberWolf
Software, Inc., Prof. Masao Sato of Waseda University, Prof. Hidetoshi Onodera of Kyoto University, Prof. Kenji Ishida of Hiroshima City University, Prof. Michiroh Ohmura of Hiroshima
Institute of Technology, Prof. Yoko Kamidoi of Hiroshima City University, and Dr. Kazunori
Isornoto of Technical Research Center, Mazda Motor Corporation.
I appreciate past and present colleagues of the Electronic Circuits and Systems Laboratory
for their help and friendship. In particular, I wish to acknowledge Mr. Yoshiki Michimoto, Mr.
VB

Satoshi Yamamoto, Mr. Kazutoshi Yokoyama, Mr. Yoshihiro Toyohara, Mr. Naoko Oohashi,
Mr. Hidekazu Ogasawara, Mr. Noboru Onoe, Mr. Chin Saw Kiun, Mr. Koichi Hatta, Mr. Hideki
Mishima, Mr. Katsumi Yamatani, Mr. Toshichika Sakai, Mr. Yuichi Sakaue, and Mr. Tetsuya
Matsumoto for their valuable discussions. Also, I would like to acknowledge Mr. Hiroshi
Kusumoto, Mr. Hiroo Emoto, Mr. Tetsuya Miyoshi, Mr. Masahiro Irie, Mr. Yoshinori Katsura,
Mr. Takeshi Suzuki, Mr. Masahiro Tsuchiya, Mr. Mitsuhiro Ono, Mr. Hiroshi Nishikawa, Mr.
Sachihiro Oohira, Mr. Makoto Okamoto, Mr. Yutaka Nishimaru, Mr. Yasunori Negoro, Mr. Atsushi Ishibashi, Mr. Kazushi Itagawa, Mr. Shin' ichi Hiratani, and Mr. Tetsuya Miyake for theirimplementation of algorithms.
Finally, I want to acknowledge my wife Mari, my son Syusuke, my sister Emiko Awazu,
my brother N obuhisa Koide, and my parents Shigemi and Ikuko Koide for their continuous
encouragement and support. Without them, this dissertation would not have been written.

Vl11

Contents

1

Abstractv,Acknowledgments

vii

Table of Contentsix ·List of Figures

xiii

List of Tables

xvii

Introduction

1

1.1

VLSI Layout Design .

2

1.1.1

Design Styles

2

1.1.2

Design Stages

5

Timing-Driven Layout Design

9

1.2.1

Interconnection Capacitances and Resistances .

9

1.2.2

Timing Constraints

11

1.2.3

Previous Work .

12

1.3

Goal of the Dissertation

15

1.4

Organization of the Dissertation

17

1.2

2

A Timing-Driven Placement Algorithm for Standard Cell Layout

21

2.1

Introduction .

21

2.2

Preliminaries.

24

2.2.1

Layout and Delay Models

24

2.2.2

Timing Constraint . . . .

26

2.2.3

Problem Formulation . .

27

2.3

POPINS: A New Timing-Driven Placement Algorithm
2.3.1 Overview of POP INS . . . . . . . . . . . . .
2.3.2

28
28

Initial Placement Based on Timing-Driven Hierarchical Min-cut Partitioning (Phase 1) . . . . . . . . . . . . . . . . . . . . . . . . . . .

28

2.3.3

Iterative Improvement Based on Nonlinear Programming (Phase 2) .

30

2.3.4

Timing-Driven Row Assignment (Phase 3) . . . . . . . . . . . . .

35

IX

CONTENTS

x

2.4

2.5

2.6

3

4

2.4.1

Introducing Parallelism to Phase 1 : Overview

38
38

2.4.2

Introducing Parallelism to Phase 2 : Overview

39

2.4.3

Introducing Parallelism to Phase 3 : Overview

40

Extension to a Parallel Algorithm PAR-POPINS

Experimental Studies........ .

41

2.5.1

Evaluation of POPINS .. .

41

2.5.2

Evaluation of PAR-POPINS

44

Concluding Remarks. . . . . . . . . .

45

A Timing-Driven Global Routing Algorithm for Standard Cell Layout

47

3.1

Introduction .

47

3.2

Preliminaries.

48

3.3

TV-yR: A New Timing-Driven Global Router

50

3.3.1

Overview of the Algorithm . . . . . . .

50

3.3.2

Initial Global Routing (Phase 1) . . . . .

51

3.3.3

Iterative Improvement Based on Wiring Delay (Phase 2)

52

3.3.4

Iterative Improvement Based on Channel Density (Phase 3) .

54

3.3.5

Net Assignment with 0-1 ILP (Phase 4) . . . . .

56

3.3.6

Extension to the Over-the-Cell Channel Routing

59

3.4

Experimental Studies

63

3.5

Concluding Remarks.

65

Over-the-Cell Channel Routing Algorithms for Standard Cell Layout

67

4.1

Introduction . . . . . . . . . . . . . . . . .

67

4.2

New Cell Models for Over-the-Cell Routing.

70

4.3

4.4

4.2.1

The Boundary Terminal Model with Nonuniform OTC Routing Capacity 70

4.2.2

The Arbitrary Terminal Model with Obstacles on Arbitrary Positions.

71

Three-Layer Over-the-Cell Routing for the BTM-N . . . . .

73

4.3.1

Problem Formulation . . . . . . . . . . . . . . . .

73

4.3.2

Overview of the Routing Algorithm 3VR-BTM-N

74

4.3.3

Determination of Planar Routable Net Segments on M2 (Step 1)

75

4.3.4

Layer Reassignment and Planar Routing on M2 (Step 2)

76

4.3.5

OTC H-V Routing (Step 3) . . . . . . . . . . .

76

4.3.6

Planar Routing on M3 (Step 4).........

79

4.3.7

OTC H-V Routing on Unrouted Regions (Step 5)

81

Three-Layer Over-the-Cell Multi-Channel Routing for the ATM-O

81

4.4.1

81

Problem Formulation . . . . . . . . . . . . . .... . . . .

CO~vTENTS

4.5

4.6
5

Xl

4.4.2

Overview of the Algorithm 3VR-ATM-O

83

4.4.3

Multi-Channel Net Assignment (Phase 1) ..

83

4.4.4

Over-the-Cell Routing Considering Obstacles (Phase 2) .

86

4.4.5

Tenninal Reassignment and Channel Routing (Phase 3) .

4.4.6

Treatment of Timing Constraints in Phase 1

89
89

Experimental Studies....... .

90

4.5.1

Evaluation of 3VR-BTM-N

90

4.5.2

Evaluation of 3VR-ATM-O

92

Concluding Remarks. . . . . . . . .

94

lFloorplanning, Global Routing and Pin Assignment Algorithms for Building Block
Layout97

5.1

Introduction

97

5.2

TV-FPN: A Timing-Driven Floorplanning Algorithm

100

5.2.1

Problem Formulation . . . . . . . . . .

100

5.2.2

Overview of the Algorithm TV-FPN

101

5.2.3

Timing-Driven Topological Arrangement with Nonlinear Programming(Phase 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

5.2.4
5.3

5.4

5.5

TV-QRPA: A Timing-Driven Global Routing Algorithm with Coarse Pin
Assignment, Block Reshaping, and Positioning

108

5.3.1

Problem Formulation . . . . . . . . . .

108

5.3.2

Overview of the Algorithm TV-QRPA

110

5.3.3

Initial Routing . . . . . . . . . .

111

5.3.4

Rip-up and Rerouting . . . . . .

114

5.3.5

Block Reshaping and Positioning

115

ACPA1: An Optimal Channel Pin Assignment Algorithm

116

5.4.1

Channel Pin Assignment Problem .

116

5.4.2

A Linear Time Optimal Algorithm

118

5.4.3

Optimality of the Algorithm . . . .

122.......... .

122

5.5.1

Experimental Results of TV-FPN

122

5.5.2

Experimental Results of Phase 2 of TV-FPN

125

5.5.3

Experimental Results of TV-QRPA

126

Experimental Studies

5.5.4
5.5.5
5.6

Floorplanning with Topological Constraint Manipulation (Phase 2) . . . 104.... .
Experimental Results of ACPA1 .. . ... .
Experimental Results of TV-QRPA and ACPA1Concluding Remarks . . . . . . . . . . . . . . . .. . . . . . .

129
130
132

CONTENTS

xii

6

Conclusion

133

A

Details of the Timing-Driven Placement Algorithm in Chapter 2

137

A.l Definitions of the Tenninal and Wire Gains . . . .

137

A.2 Details of the Parallel Algorithm PAR-paPIN'S

138

B

C

A.2.1

Introducing Parallelism to Phase 1 .

138

A.2.2

Introducing Parallelism to Phase 2 .

140

A.2.3

Introducing Parallelism to Phase 3 .

142

A.3 Details of Experimental Results . . . . . .

143

A.3.1

Benchmark Data . . . . . . . . . .

143

A.3.2

Experimental Results of paPIN'S

145

A.3.3

Experimental Results of PAR-POP IN'S

145

A Global Routing Algorithm for Over-the-CeU Channel Routing

149

B.1

149

Preliminaries . . . . . . . . . . . . .

B.2 Overview of the Algorithm gROTC . . . . . . .

150

Details of the OTC Routing Algorithms in Chapter 4

153

C.l

Net Decomposition Methods for 3VR-BTM-N'

.

153

C.l.1

Two-Tenninal Net Decomposition in Step 1

153

C.l.2

Net Segment Decomposition in Step 2. . .

154

C.1.3

Two-Tenninal Net Decomposition in Step 3 .

155

C.2 Proof of Theorem 4.1

D........... .

155

C.3 Transformation from the BTM to the ATM-O

156

Proofs of Lemmas and Theorem for the ACPA 1 in Chapter 5

159

List of Figures
1.1

A VLSI design process.

2

1.2

A standard cell style. . .

4

1.3

A building block style ..

4

1.4

VLSI layout design stages. .

6

1.5

An example of layout design stages for building block layout style.

7

1.6

Basic interconnection parameters [4]. . . . . . . . . . . . . . . .

10

1.7

Impact of deep submicron design on overall ASIC/IC performance. .

10

1.8

A synchronous circuit. . .

11

1.9

Electrical model of a cell.

131.10 Delay model of a cell. . .

13

1.11 Treatment of timing constraints in net- and path-based algorithms.

14

2.1

A classification of timing-driven layout algorithms.

22

2.2

Interconnection delay model.

2.3

Estimation of the wire length of net ni.

..

25

2.4

A constrained circuit and constrained paths.

26

2.5

Flow of the proposed hierarchical quadratic partitioning.

29

2.6

Example of timing gain gtimingi'

30

2.7

Selection of a target subcircuit.

32

2.8

Variables for net ni. . . . . . .

32

2.9

Row Assignment.

35...... .

...... .

25

2.10 Introducing parallelism to phase 1..

39

2.11 The parallel algorithm of a bi-partitioning at the upper levels.

39

2.12 Introducing parallelism to phase 2 ..

39

2.13 Introducing parallelism to phase 3 ..

40

2.14 Shifting of the group boundaries.

40.

2.15 The distribution of the cut size for C 1.

43

2.16 CPU time comparison between POPINS and RITUAL.

43

3.1

The grid graph G = (V, E) .. . . . . . . . .

49

3.2

A timing constraint tT = (ST) eT) DelallowJ.

50

3.3

An example of phase 1.

52

.....
Xlll

LIST OF FIGURES

XIV

3.4

An example of phase 2. . . . . . . . . . . . . .

53

3.5

An example of phase 3. . . . . . . . . . . . . .

54

3.6

Iterative improvement based on channel density.

56

3.7

The net assignment. . . . . . . . . . . . . . . .

57

3.8

Overlapping switchable segments of the same net. .

58

3.9

Consideration of the-over-the-cell region in global routing.

60

3.10 The boundary tenninal model(BTM). . ..

61

3.11 An example of the OTC routing on the M2.

61

3.12 An example of TD-QROTC.

62. ..... .

4.1

Conventional cell models . .

68

4.2

The boundary terminal model(BTM).

71

4.3

The ATM-O and associated OTC routes ..

72

4.4

Over-the-cell region on the second layer.

73

4.5

Step 1: Planar routing on the second layer..

75

4.6

Step 2: Layer reassignment. . . . . . . . .

76

4.7

An example of the horizontal constraint graph Gt(I't).

77

4.8

The second term in equation (4.8) represents the possibility for segl to be routed
at the track Ys.

4.9...........

78

Step 3: Over-the-cell H-V routing ..

78

4.10 The definition of Xmin. . . . .

80

4.11 x' is in the interval [x, Xmin]. .

80

4.12 Steps 4 and 5. . . . . . . . .

81

4.13 Definition of tenninologies. .

82

4.14 Restriction of routing patterns ..

84

4.15 The constraints of 0-1 ILP problem.

84

4.16 The horizontal constraint graph Gj(t k ).

86

4.17 The definition of an unrouted interval and a subsegment.

87

5.1

The outline of TD-FPN.

5.2

A topological arrangement of 4 blocks and the corresponding topological con-101

straint set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

104

5.3

The channel intersection graph and the horizontal channel positioning graph.

108

5.4

The global routing graph G r = (v,., Er).

109

5.5

The outline of TD-QRPA. . . .

111

5.6

An example of the AS5MT(nj).

112

5.7

A channel and subchannels. . . .

117

LIST OF FIGURES

xv

5.8

A classification of nets in the subchannel SCi.

5.9

Pin assignment in a subchannel. . . . . . . .

118
119

5.10 An example of ACPA1 . . . . . . . . . . . .

121

5.11 The global placement result of TV - FPN for "ami33b". .

124

5.12 The floorplanning result of the proposed algorithm for "ami33b".

125

j\.1

An example of a vertical partitioning. . . . . . . . .

137

j\.2

An example of the terminal gain.

..........

138

j\.3 The processing flow of phase 1 of PAR-POPINS.

140

13.1

13.3 Phase 2: Determination of net segments routed in channels.

150
151
151

C.l

154

Net segments and a corresponding net connection graph G(T(ni).

13.2 Phase 1: Determination of net segments routed on OTCs. .

An example of the two-terminal decomposition for a multi-terminal net.

C.2 An example of the NS decomposition with linear assignment. .

154

C.3 An example of decomposition in Step 3. . . . . . . . . . . . .

155

C.4 Transformation of terminal positions for MCNC benchmarks. .

157

C.5 Transformation of terminal positions for PRIMARY 1.

157

1).1 The two possible patterns of Tj and B k • . . . . . . . .

161

List of Tables]l .1

Comparison of layout styles.

5

1.2Comparison of design quality for layout styles. .

5

]l.3

Scaling of local and global interconnections [4] ..

10

2.1

Characteristics of experimental data.. . . . . . .

41

2.2

Placement results of the proposed method POPINS and RITUAL [115].

42

2.3

The number of cut sizes of the proposed method POPINS and RITUAL [115]. 42

2.4

Results of phase 1 of PAR-POPINS and POPINS.

44

2.5

Results of phase 2 of PAR-POP INS and POPINS . . -. . . . . . .

44

2.6

Results of phase 3 of PAR-POPINS and POPINS. . . . . . . . .

45

2.7

The placement results of PAR-POPINS, POPINS, and RITUAL.

46

3.1

Benchmark data. . .

63

3.2

Results of TV-gR.

63

3.3

Comparison results with the conventional algorithm [52].

64

3.4

Results of each phase. . . . . . .

64

3.5

The CPU time of each phase(sec).

64

4.1

Characteristics of cell models. . .

68

4.2

Test data for the BTM-N.

4.3

Experimental results for the BTM-N (vs. planar routing [26]).

90
90

4.4

Experimental results for the BTM-N(vs. H-V routing). . . .

91

4.5

Experimental results for the BTM-U(vs. planar routing [26]).

91

4.6

Experimental data for the ATM-O . . . . . . . . . . . . . .

93

4.7

Experimental results for three-layer OTC routing methods. .

93

4.8

CPU time of 3VR-ATJ\;t-O-o. . . . . . . . . . . . . . . .

93

4.9

Experimental results for three-layer OTC routing methods for PRIMARY 1.

94 -

5.1

Experimental data of fioorplanning.

123

5.2

Results of phase 1 of TV-FPN. .

123

5.3

Results of phase 2 of TV-FPN. .

124

5.4

Global routing results of the fioorplanning results in Table 5.2.

125

5.5

Results of FA and the algorithm VT.. . . . . . . . . . . . . .

126

. ...

XVll

LIST OF TABLES

XVll1

5.6

Results of FA and the algorithm VT with hard blocks.

..

126

5.7

Experimental data for global routing with pin assignment. .

127

5.8

Results of TV-gRPA. . . . . . . . . . . . . . . . . ..

128

5.9

Results for looser timing constraints.

. . . . . . . . .. .

128

5.10 Results of TV-9RPA for the different timing constraints.

129

5.11 Experimental results of the CPAl. . . . . . . . . . . . . .

130

5.12 Experimental results by applying both TV-gRPA and ACPA1 . .

131

A.1 Experimental data of placement. . . . . . . . . . . . . . .

144

A.2 Placement results of POPINS and RITUAL [115]. . . .

145

A.3 All results of phase 1 of PAR-POPINS and POPINS. .

146

A.4 All results of phase2 of PAR-POPINS and POPINS. .

146

A.5 All results of phase3 of PAR-POPINS and POPINS. .

147

A.6 All placement results of PAR-POPINS, POPINS, and RITUAL. .

148

Chapter 1
Introduction
VLSI, or Very Large Scale Integration refers to a semiconductor technology which makes it
possible to implement large circuits of up to a million transistors on silicon. VLSI technology
has been successfully used to build microprocessors, signal processors, large capacity memories,
memory controllers, I/O controllers, etc .. Early ICs could only contain a couple of gates or flipflop, and a gate consisted of a single transistor with a resistor network to realize a logic function.
In a period of three and a half decades, there have been four generations of ICs with the numberof transistors on a single chip growing. State-of-the-art VLSI technology permits us to build alarge system with hundreds of thousands of transistors on a single chip. For example, the Intel
80286 microprocessor has over 100,000 transistors, the 80386 has 275,000 transistors, the 80486
has approximately 1,000,000 [4], while the Intel Pentium processor has over three million [lOS] .
Design of integrated circuits with the complexity shown above would not have been possible vvithout the assistance of computer programs during all phases of the design process as thesecomputer programs automate most of the design task. Designing a VLSI chip with the help ofcomputer programs is known as CAD, or Computer Aided Design. Design Automation (DA),on the other hand, is an entirely computerized design process with no or very little human intervention. CAD and DA research have a long history of over three decades, and now a number ofsophisticated design tools are available for designing integrated circuits.
VLSI design can be regarded as a sequence of processes which transform the specificationof an electrical circuit into mask patterns of a chip. The final stage of VLSI design is calledlayout (physical) design and, due to tight requirements and the very small size of individualcomponents, this is an extremely troublesome, error prone, but very important process. Today,
performance requirement of a VLSI chip has become more important than ever. Since VLSI
geornetries are being increasingly scaled down, interconnection delays have become a major
factor of influencing a chip's performance and therefore layout design can no longer afford toneglect the propagation delay among interconnection wires against gate delays. Consequently, it
is indispensable to develop timing-driven layout tools which consider the interconnection delay
explicitly. In this dissertation, timing-driven layout design algorithms are discussed.
The remainder of this chapter is organized as follows. Section 1.1 discusses the stages of thelayout design, and Section 1.2 presents a brief introduction "of a timing-driven layout design. In

CHAPTER 1. INTRODUCTION

2

Section 1.3, the goal of this dissertation is discussed, which is followed by the organization ofthis dissertation in Section 1.4.

1.1

VLSI Layout Design

Since the complexity of VLSI circuits is in the order of millions of transistors, designing VLSI
circuits is understandably a complex task. To reduce complexity in the design process, several
intermediate levels of abstractions are introduced [133].
A typical design process may berequirements

represented by the flow chart shownin Figure 1.1.

In layout design

which is discussed in this dissertation, the circuit representation ofeach component is converted into ageometric representation. Connections among different components
are also expressed as geometric patterns.

This geometric representa-tion of a circuit is called a layout.
The exact details of the layout also
depend on design rules, which are
guidelines based on the limitations

Design Specifications - - - specifications

Functional Design
behavioral description

Logic Design
structual representation

Circuit Design
structual representation~-----------------

Layout Design

physical representation

Fabricationof the fabrication process and theelectrical properties of the fabrication materials.

In the following,

Packaging and Testingl------'

we briefly describe the layout design
functional integrated circuit

step.

Figure 1.1: A VLSI design process.

1.1.1

Design Styles

Layout design is an extremely complex process and even after breaking the entire process up
into several conceptually easier steps, it has been shown that each step is computationally very
hard [83,100,105, 111,127]. However, market requirements demand a quick time-to-market andhigh yield. As a result, restricted models and design styles are used to reduce the complexity oflayout design.
The design styles can be broadly classified as either full-custoin or semi-custom. In a full

1.1. VLSI LAYOUT DESIGN

3

custom layout, handcrafted blocks of a circuit can be placed at any location on a silicon wafer
as long as all the blocks are non-overlapping. On the other hand, in a semi -custom layout, someparts of a circuit are predesigned and placed on some specific place on a silicon wafer. Selectionof a layout style depends on many factors including the type of a chip, the production cost,
and the requirement of time-to-market. While the full-custom layout is the preferred style formass produced chips, since a long period is generally required to produce a highly optimized
layout, it is prohibitively expensive for non-mass-produced chips. The class of circuits known
as Application-Specific Integrated Circuits (ASICs), falls into this category.
lJnlike microprocessors, an ASIC is a circuit which performs a specific function in a particular application. A digital filter is an example of an ASIC. Similarly, a chip which performs a
specific image processing function is another such example. Reduction of the time-to-market,
i.e., the sum of total design time, manufacturing time, and testing time, as well as optimizing
the area and performance of the chip, is of utmost importance in ASIC design. To reduce design
time, standard layout structures are used and therefore the semi-custom layout style is usually
preferred for ASICs.
Semi-custom layouts may be characterized by two basic geometric styles. These are row-

based (standard cell) and building-block (macro cell). Each style may be implemented withdifferent methodologies. The row-based style may be realized as the standard cell, gate array,or sea-oj-gates (SOG) design styles. The building block style may be implemented with macrocells,. Generally, in the row-based style, the cell instances can share power and ground lines,
so that this yields area savings implicitly. But the height of an individual cell is determined by
the largest cell height of the library and is fixed and this leads to area inefficiency. The building
block style, on the other hand, needs to have power and ground lines routed explicitly but thearea of the macro cells may be individually optimized and this gives the largest area savings;
hence the building block style is generally more area efficient than the row-based style.
The most flexible row-based style is the standard cell style. In this style, the designer canprogram all layers at fabrication and since all layers, including the diffusion layers, can be fabricated, the location, size, and the number of transistors of the cells are not fixed in the layout
design process. Usually, cells are pre-designed and standardized. A collection of these cells iscalled a cell library and it consists of 500 - 1200 cells. If desired, the designer can customize thestandard cells for a particular design. Figure 1.2 shows an example of standard cell design. The
chip can be divided into regions, the core region (area inside dotted square) and the 110 region(area outside). The connections of the outside world (the package terminal pin) and the chip
are n1ade using a bond pad cell. The regions between the standard cell rows are routing regions
known as channels. In the standard cell style, the heights of these channels are not fixed but
rather determined by the actual demand of routing. One disadvantage of the standard cell styleCHAPTER 1. INTRODUCTION

4

is the production cost. Performing all of the photolithography steps costs time and money, andwhile programming all layers leads to design flexibility, it requires unique photomasks for each
design. None of these photomasks can be used for any other future designs.

Figure 1.2: A standard cell style.

Figure 1.3: A building block style.

The standard cell, gate array, and sea-of-gates styles impose restrictions on the cells that areused to design the circuit. On the other hand, the design style which permits cells to vary inboth dimensions is called building block or macro cell design. Figure 1.3 shows an example ofthe building block design. In general, building blocks can take arbitrary shapes. Most layout
algorithms, however, limit the shapes to rectangles or rectilinear figures. Building blocks are
optimized for area and performance, but routing becomes more difficult. Characteristically,
the routing regions become complex and some area may become wasted. However, the area
efficiency of the building block style is still better than strict row-based styles. Moreover, sincecells with significant complexity are permitted in the library, registers, register files, arithmeticlogic units, memories, and other architectural building blocks can be accommodated in it.
There is an advantage in storing blocks such as arithmetic-logic units in a cell library. Suchblocks can often be designed to have good characteristics such as the small area and the shortest
circuit delay. Consider, for example, an 8-bit multiplier, which due to its regular structure, canbe laid out efficiently. If the same multiplier has to be designed using simple standard cells
such as fundamental logic gates only, it would be very difficult to predict how the cells will befinally arranged by a layout program. In general, the high performance of the multiplier may
be achieved only when the circuit is appropriately laid out, and hence it would be difficult torealize the highest performance of the multiplier with the standard cell design.
Similar to the standard cell layout style, all the processing steps are also required to manufacture a building block layout chip. Since there is more flexibility than standard cell design and1.1. VLSI LAYOUT DESIGN

5

building block layout comes closest to full-custom layout, it is much more difficult to develop
an automatic layout program for building block design style.
Finally, Table 1.1 summarizes the differences in the cell size, cell type, cell placement, andinterconnections in the layout styles mentioned above. Another comparison for application,
design time, fabrication effort, cost, and performance is also shown in Table 1.2.

Table 1.1: Comparison of layout styles.
Design sty Ie
full-custom
building blockstandard cellgate array
FPGA

cell size
variablevariable
fixed height
fixed
fixed

cell typevariablevariablet
variable
fixed
programmablethard block and soft block are used.

cell placement
variablevariablein rowt
fixed
fixed

interconnections
variablevariablevariablevariable
programmable+uneven height cells are also used.

Table 1.2: Comparison of design quality for layout styles.
Design stylefull-custom
building blockstandard cellgate array
FPGA

Application
chips for high-volume
production, e.g.,
microprocessors
general
ASICs
ASICs
ASICs

Designtime

Fabrication
EffortCost

Perfonnancehigh(4)high(2)high(4)High(4)high(1)low(3)
low(2)
low(l)high(2)high(2)low(1)nil

low(3)
low(3)
low(2)
low(1)high(2)high(l)low(4)
low(1)

Note that the number in the parentheses indicates a rank to grade the layout style in comparison to others in thesame category.

1.1.2

Design Stages

Once the design style has been chosen, layout design can begin. This is accomplished in several
stages, those being partitioning, floorplanning, placement, pin assignment, routing, compaction,and verification. The VLSI layout design stages are shown in Figure 1.4 and in the following,
we briefly describe each stage.
Partitioning is the first stage in the layout design process. The goal of this phase is to break
the netlist into two or more manageable pieces. There are two levels of partitioning: partitioninga system among multiple integrated circuits and partitioning a single integrated circuit design
into multiple components. Within a single integrated circuit, partitioning is performed whenever
macro cells exist, or when the number of cells is extremely large. Each piece of the netlist will
become a component in the floorplanning stage. If all the components are standard cells, andthe number of standard cells is sufficiently small, partitioning need not be performed. In theCHAPTER 1. INTRODUCTION

6

Circuit Design
Layout Design

Fabrication

Figure 1.4: VLSI layout design stages.

case that both macro blocks and standard cells are present in the design, the standard cells will
be partitioned into one or more soft blocks (soft macro) while predesigned macro blocks will
be partitioned into hard blocks (hard macro). A soft block is a block in which some geometricquantity, such as aspect ratio, pin locations, or shape, is unknown, whereas a hard block has all
its information determined. After partitioning, each integrated circuit will have a reduced netlist
ready for ftoorplanning. Figure 1.5 shows an example of layout design stages for the building
block layout style. In Figure 1.5(a), the input circuit has been partitioned into four blocks.

Floorplanning is the second stage in the layout design process. As its name suggests, thepurpose of ftoorplanning is to plan the overall physical structure of the integrated circuit. The
ftoorplanner's input consists of a partitioned netlist of building blocks modeling the physicalcomponents. Some components in this netlist may not be completely characterized in termsof area, aspect ratio, timing, or I/O terminal positions. The ftoorplanner will determine those
aspects not yet characterized of any soft blocks. The goal of the ftoorplanning is to determine
the relative position of the hard and soft blocks on the chip which minimizes the total area andmaximizes circuit performance. In Figure 1.5(b), the relative positions of four blocks and theregions in which four blocks will be placed have been determined. In the row based layout style,ftoorplanning may sometimes be skipped.

1.1. VLSI LAYOUT DESIGN

7

Component A

Component C

Component B

Component 0(d) Pin Assignment(a) Partitioning

I

A

C

B

0

chip

(b) AoorpJanningD~(e) Routing

blocksGJ(c) Placement(f) Compaction

Figure 1.5: An example of layout design stages for building block layout style.

Placement determines the exact positions of the cells on the chip. The ideal goal of placement is to position the cells to yield maximum performance using the minimum area. Unfortunately, this is an incredibly tough task because the number of possible placements grows
exponentially with the number of placeable objects. To calculate the exact area required for aplacement, we must complete the remaining steps of the layout design process. However, all ofthese subtasks are NP-complete problems, and there is no efficient ways to calculate the exact
area of a placement. Therefore, at the placement stage, we usually use an estimated area andan estimated wire length for the evaluation of the placement. In Figure 1.S(c), four blocks havebeen placed in each region. It should be noted that some space between the blocks is intentionally left empty to allow for interconnections between them.

Pin assignment is to define the signal that each pin will receive. This may be an optional
step if all pins have been already assigned by the designer. Pin assignment may be done during

8

CHAPTER 1. INTRODUCTION

floorplanning, placement or after placement is fixed and can sometimes even be carried out after
global routing. The objective of pin assignment is to assign pins to the net tenninals so as tominimize a given measure of wiring cost or routability. In the building block layout style, since
there are soft blocks which have not yet been designed, we need to detennine the pin positionsof the nets connecting the soft blocks. Good assignment of nets to pins can hence improve
the quality of the layout. On the other hand, in the other styles, since the blocks or cells are
already designed, it may be possible to interchange a few pins since some pins are functionallyequivalent and some are equipotential. In particular, in the row based layout style, the channel
density, which corresponds to the height of channel, can be reduced by pin assignment. In Figure
I.S(d), pin positions on the boundaries of each soft block have been detennined.

Routing completes the interconnections among cells according to the specified netlist. First,
the space not occupied by the blocks (called the routing space) is partitioned into rectangular regions called channels and switchboxes. The goal of routing is to complete all circuit connections
using the shortest possible wire length and using only the channels and switchboxes. This is usually done in two phases, referred to as the global routing and detailed routing phases. The global
router finds a list of channels and switchboxes which are to be used as a passageway for each net.
In other words, global routing specifies the different regions in the routing space through whicha net should be routed and the global routing results are fed to a detailed router on a channel bychannel basis. The detailed router creates the physical geometries necessary to manufacture thephotomasks. The detailed routing includes channel routing and switchbox routing, and is donefor each channel and switchbox. Since several existing channel routers can produce solutions
only one or two tracks beyond optimum for most channels, further improvement in the layout
area is impossible if routing is done only in channels. Recently, over-the-cell channel routing, inwhich the metal layers available over the cell area can be used for the routing, has been proposed
to reduce the channel routing space. Figure l.S(e) shows that the all interconnections between
the four blocks have been routed. In this example, there are 8 channels and I switchbox.

Compaction is an optional step to reduce the chip area while eliminating design rule violations. If a design has initial design rule violations, compaction could actually increase the sizeof the chip. Compaction also minimizes the area of an integrated circuit without changing its
topology. It is important to keep the topology unchanged to preserve the timing and perfonnanceoptimization of the previous phases. Figure I.S(f) shows the compacted layout.

Design Verification is the final step in the layout process. The design must be verified tomake sure that it satisfies the design rule, that it is functionally correct, and that it meets all of
the perfonnance criteria. Checkers have been developed to ensure that the design does not contain any design rule violations and a design rule checker (DRC) verifies that each mask geometry
meets all spacing and width constraints. After checking the layout for design rule violations and1.2. TIMING-DRIVEN LAYOUT DESIGN

9

removing any of these, the functionality of the layout is verified by circuit extraction. This is areverse engineering process and generates the circuit representation from the layout. Extracted
description is compared with the original circuit description to verify its correctness and geometric information is extracted to compute resistance and capacitance. This allows the accurate
calculation of the timing of each component including interconnections. If design verification
does not detect any errors, all layout information is sent for fabrication.

1.2

Timing-Driven Layout Design

1.2.1

Interconnection Capacitances and Resistances

One of the most important trends in semiconductor technology has been the scaling down ofdevice and line geometries. The minimum feature width of devices that can be etched on siliconhas decreased from about 8 microns in the late seventies to about 0.5 rv 0.35 microns today. The
switching speed of a metal-oxide semiconductor (MOS) transistor which is the basic component
for cells, has increased dramatically by a factor of 20.
A~s the minimum feature size is scaled down and the chip size increases, wiring capacitancebecomes more important than device capacitances. Transistor input capacitances decreases because gate, gate-drain overlap, and source/drain diffusion capacitances are reduced when feature size is miniaturized [4, 133]. Therefore interconnection capacitance dominates the gate
capacitance. However, the speed improvement expected from simple scalingl does not apply tocircuits that drive global communication lines. Simple scaling assumes a reduction in the capacitive loading due to wires. This is true locally when a circuit is connected only to its neighbors,but, for circuits that drive long global wires, the capacitive loading actually increases. Since thecritical paths that determine the overall performance of an integrated circuit are usually dominated by global wires, faster local circuits do not necessarily improve the clock frequency. This
negative effect of global wires hence decreases the performance of a chip.
To illustrate this effect, ideal (simple) scaling and quasi-ideal scaling2 of local and global interconnections are summarized in Table 1.3, and the basic interconnection parameters are shownin Figure 1.6 [4].
From Table 1.3, wiring capacitance of long global wires increases because interconnection
capacitance per unit length remains approximately constant and global wire lengths increase as
chips get larger. It should be pointed out that if an existing chip is scaled down, wire lengths
are reduced. In practice, however, as the technology is scaled down, designers want to put more
1Ideal scaling or simple scaling is a scaling of interconnections where all horizontal and vertical dimensions are
reduced by the same factor.
2Quasi-ideal scaling is a scaling of interconnections where the hori~ontal dimensions are scaled by 1/ S (as aretransistor), but the vertical dimensions are reduced only by 1/..;s to mruntain a small RC time constant.

CHAPTER 1. INTRODUCTION

10

Table 1.3: Scaling of local and global interconnections [4].
Ideal Scaling
FactorParameter
Width and separation (Wint' W sp )l/S
Thickness and insulator thickness (Hint' t ox )l/S
S2Resistance per unit length (~nt = pint W . IH . )~tmt
Capacitance per unit length (Cint = fox ~t
m
)
1
ox
S2
RC constant per unit length (~ntCint)
Local interconnection length (lloc)
1/ S
Local interconnection RC delay (~ntCintZfoc)
1
Se
Die size (Dc)
Global interconnection length (lint)
Se
Global interconnection RC delay (~ntCintqnt)
S2 Sb
S : Scaling factor for device dimensions.

Quasi-Ideal
Scaling Factor
l/S
1/.J§
S.J§
1/.J§

S
l/S
l/S
Se
Se
SSb

percentage contribution to
overall ICI ASIC signal delay
100%

50%

0%
0.5 f.t

Figure 1.6: Basic interconnection parameters[4].

0.35 f.t

process geometry

Figure 1.7: Impact of deep submicron design
on overall ASICIIC performance.

and more circuits on a chip and so the die size increases rather than decreases. Consequently,
global wire lengths get longer from one generation of chips to the next.
In addition to large capacitance loads resulting from long interconnections, the resistanceof the lines also becomes a major concern [4]. Because both interconnection resistance perunit length and global wire length increase as chips get larger, wiring resistance also increases.
Therefore since the capacitance and resistance of wires increase rapidly as the chip size grows
larger and the minimum feature size is reduced, once considered to be electrically negligible,
interconnections are becoming a major concern in the performance of integrated circuits. As
shown in Figure 1.7 [4], in 0.35 micron design rule, the interconnection delay is about 80 percentof the total delay and it is no longer negligible.

1.2. TIMING-DRIVEN LAYOUT DESIGN

1.2.2

11

Timing Constraints

In the layout design, a synchronous system can be viewed as a collection of blocks (cells) andnets interconnecting them. We will distinguish four types of blocks, namely: combinational,
synchronizing (flip-flops), primary inputs (PIs), and primary output (POs) as shown in Figure
1.8. The signals in the system originate in the PIs or flip-flops (FFs) , travel through the combinational blocks and wires interconnecting them and tenninate at the POs or FFs. There is aclock signal which synchronizes data transfers. It is distributed to all FFs. Both clock and data
signals experience delays between their source and the sinks. The data signals are delayed by
the combinational blocks' delays and by the delays introduced by the wire. The clock signal
suffers from both the wire and buffer delays.
Performance of a digital circuit is mea-

primary outputs

primary inputs

sured by its cycle time. Shorter cycle timemeans higher performance.

At the layout
combinati onal
circuitlevel, performance of a system is affected by
two factors, signal propagation time and clock

skew . In the case of a single clock signal,
clock skew is defined as the maximum difference of the delays from the clock source tothe clock pins on the latches. The clock cy-

clock: flip-flops (FFs)source ----+--i

cle period T, clock skew s, worst case signal
propagation delay del max and offset constantFigure 1.8: A synchronous circuit.

To satisfy the following condition for correct
timing.
T = s + del max + To

(1.1)

The constant To exists in all timing constraints which cannot be changed during the layout process. Equation (1.1) is frequently referred to as a long path constraint or a long path problem
because for a given clock period and skew this sets an upper bound on the longest path delayin the system. For a system to function properly, there are also requirements imposed on the
shortest delays between FFs and/or PIs/POs and this is called a short path constraint or a shortpath problem. They cannot be arbitrarily short. However, the short path constraints are usuallyaccounted for at the circuit design level [4]. The gates realizing the circuit are simply chosensuch that, even if wires had no delays, the delay would suffice to fulfill the short paths delay
requirement when the signal travels through them.
To shorten the cycle time, we try to minimize the skew s and the longest path delay del max •When circuit elements are being placed and interconnected, only the wire delays can change.

CHAPTER 1. INTRODUCTION

12

Changes in the topology and layout of the clock tree affect the clock skew. Changes in thepositions of blocks and routing of nets change the signal delays in the wires, and in effect thesignal path delays change.

1.2.3

Previous WorkAs seen in Section 1.1.2, the primary objective of the layout design has been the minimizationof the total wire length of the interconnections, which by and large implies the minimization of
the total chip area. Numerous commercial software products of design tools are now available
for gate array, sea-of-gate, and standard cell design styles. Unfortunately, until recently, timing has rarely been considered in layout design. As mentioned above, since the critical paths
that determine the overall performance of an integrated circuit are usually dominated by global
wires, faster local circuits do not necessarily improve the clock frequency. To minimize thenegative effects of the long wires, placement and global routing of an integrated circuit must
be constructed such that long wires are avoided on the critical paths. Thus timing-driven layout

design, which considers the wiring interconnection delay explicitly, has generated a great dealof interest recently.
In the layout design, since the interconnection delay is heavily influenced by the results ofthe placement stage, placement has the largest effect on the timing problem and it gives the upperbound of the clock frequency. Therefore a number of timing-driven placement algorithms havebeen proposed. Since even if the timing-driven placement tools produce good results, the actualinterconnection delay is determined in the routing stage, thus it is required to explicitly consider
the timing constraint in the routing stage, especially in the global routing stage. Therefore global
routing also has a large effect on the timing problem and a few timing-driven global routing
algorithms have been proposed. In the detailed routing stage, since the wiring interconnection
topology of each net and the regions through which each net should be routed are determined so
as to satisfy the timing constraints in the global routing stage, in general, it is sufficient for thedetailed routers to consider the minimization of the wire lengths of the nets. In the following,
we will briefly discuss the previous work for the timing-driven placement and the global routing
which will be discussed in this dissertation.
First, we will discuss the delay models which have been used in the timing-driven layout.
In general, electrical behavior of a cell is approximated by an equivalent resistance model. It isshown in Figure 1.9. Rout denotes the output resistance, Gout is the output capacitance and Gin
is the input capacitance of an input pin. The switch is controlled by the logic function of the
inputs. In addition to these electrical parameters, a cell is characterized by its area and intrinsic
delay Td .
The delay of a cell is estimated by the lumped RC model depiCted in Figure 1.10. In this1.2. TIMING-DRIVEN LAYOUT DESIGN

II~::alI2lell130

GndF]gure 1.9: Electrical model of a cell.

Figure 1.10: Delay model of a cell.

figure, the delay is equal to the product of the output resistance and the capacitive load of theoutput pin which includes the output capacitance of the cell and the fanout input capacitances.
Therefore referring to the Figure 1.10, the delay of cell A driving the cells B, C, and D isexpressed by the following equation.
(1.2)

Before placement is performed, the topologies and dimensions of particular wires are unknown, therefore the delay model for the nets cannot be very accurate. In most of the timingdriven placement algorithms, it is usually assumed that a net is modeled by a lumped capacitance. Let C w denote the capacitance per unit length of interconnecting wire. Let R~ut denotethe output resistance of the cell mi whose output drives the net ni. The delay of the net ni isdetermined from the following equation.
(1.3)

where Li is the interconnection wire length of the net ni. Since, in the placement stage, the actualinterconnection wire length Li can be unknown, a simple lower bound, that is, the half perimeterof the enclosing rectangle of all the pins belonging to the net, is often used for calculating L i .
The sum of the Manhattan distances between the source node and all sink nodes of a net is also
used. In the global routing stage, Li can be exactly calculated.
While in this simple RC model, in which the interconnection delay is proportional to the wire
length, the delay may introduce some inaccuracy, it is usually sufficient for those designs where
the assumption that wires introduce only capacitive delays holds. Since in this model, the delay
can be easily calculated, it has been used in most of timing-driven layout algorithms. However,as seen above, the capacitance and resistance of wires increase rapidly today, this assumption
no longer holds.
In order to consider the resistive behavior of interconnections, recently, the RC tree model[4, 107] or the Elmore delay model [4,34] is being used for delay estimation. Since these delay
models consider both interconnection wire resistance and capacitance and the delay is proportional to the square of the wire length, the delay estimation is more accurate than that of theCHAPTER 1. INTRODUCTION

14

simple RC model. However, since to calculate the delay, the structures and dimensions of treesof nets need to be known, these models cannot be used directly in the placement stage and somedevices to incorporate this model into placement algorithms are needed.
Next, we briefly discuss the previous work. The existing timing-driven placement algorithms
can be classified into two major categories; net-based algorithms and path-based algorithms.

Net-based algorithms try to satisfy timing constraints by assigning higher weights to nets
which are part of critical paths, or by transforming timing requirements into a set of upper bounds
on the net delays. For example as shown in Figure 1.11, in the net-based algorithms, timing
constraints between PIs (P II, P 12 , and Ph) and POs (POI and P0 2 ) are transformed into a
set of upper bounds on the net delays or lengths, that is, del nJ ::; Del nJ , del n2 ::; Del n2 and soon, or lnl ::; L nl , ln2 ::; L n2 , and so on where del ni , Del ni , lni' and Lni are the actual delay,
the upper bound delay, the actual wire length and the upper bound wire length, respectively.
These values, Del ni or Lni' are pre-determined. The net-based approach fits easily into the
traditional net-based layout design tools, but a major problem of this approach is the selectionof the weights or bounds. Furthermore, due to the neglected interactions between the nets, large
weights or fixed bounds on a set of nets may create excessive delays in other nets. Moreover,the use of individual net bounds may overconstrain the problem.

A

PII

n4

D

POI
PI2
E

G

PI3

n3

ns

P02

Figure 1.11: Treatment of timing constraints in net- and path-based algorithms.

Path-based algorithms overcome these difficulties by modeling the problem more accurately. In the path-based approach, the critical paths in the circuit are directly considered andthe placement algorithms try to place the blocks in a manner that the path length is kept sothat its timing constraint is satisfied. For example, as shown in Figure 1.11, in the path-basedalgorithms, timing constraints between PIs and POs are directly considered in the way that

delA + del nl + delF + del n4 + delD ::; DelpIl,POp where delA, del F, delD are gate delays, anddel ni , del n4 are net delays, and so on. Since the timing analysis is path-oriented, path-based
approaches are more suitable for the timing-driven layout than the net-based approach.

1.3. GOAL OF THE DISSERTATION15

For the global routing stage, although many global routing algorithms exist, only a few
timing-driven algorithms have been proposed. Most of those existing algorithms are net-based.
For net delay estimation, in the global routing stage, the actual interconnection wire length andinterconnection topology can be obtained, and so more accurate delay of a net can be estimatedusing this information. Usually, the RC tree model or Elmore delay model is used.

1.3

Goal of the Dissertation

Tl1is dissertation discusses the layout design for high-performance VLSI circuits. In recent
years, the performance of integrated circuits has been becoming higher and the operational speed
and the clock frequency of VLSI circuits faster. Moreover, the complexity of VLSI circuits has
also progressed to the order of millions of gates. To design high-performance VLSI circuits,
layout design algorithms must take the following three important issues into consideration:(i) Performance: satisfying the timing constraints given by the specification.
(ii) Layout efficiency: producing a compact circuit layout.
(iii) Layout design time: laying out an integrated circuit in short turn-around-time.
The goal of this dissertation is therefore to develop efficient and effective heuristic algorithms,
which consider the above issues, in the timing-driven layout design for two typical layout styles:

standard cell layout style, which is mainly used for designing ASICs, and building block layoutstyle, used for designing high density and high performance chips such as microprocessors.
First, to treat the performance issue, it is required to consider the following sub-issues in thedevellopment of layout design algorithms for the both layout styles.

1.1.

Accurate interconnection delay estimation : Due to the progress of the semiconductor
technologies, the traditional simple RC model is no longer effective, and the timing-driven
algorithms need to use a more accurate interconnection delay model.

1.2.

Long path delay problem: In general, the clock skew problem can be solved by equalizing
all distances from the source to FFs by constructing hierarchical trees, for example H-

trees, inserting buffers and so on [4]. The long path delay problem, on the other hand, isthe most difficult to solve in terms of timing problems and the most crucial to improve theperformance of integrated circuits.

1.3.

Pin-pair timing constraint: Usually, a timing constraint is given to a pair of pins, forexample, between an output pin of an FF and another input pin of an FF, and in the long
path problem it is specified by a maximum allowable propagation delay from a source pin
to a sink pin.

16

CHAPTER 1. INTRODUCTION

1.4.

Path-based algorithm: Since the timing analysis is path-oriented, path-based approaches
are more suitable for the timing-driven layout than the net-based approach.
Next, for the layout efficiency, the layout design algorithms should allow for the following

points for each layout style so as to produce a compact circuit layout.
For standard cell layout style:
2.IS. Minimization of routing congestion: In a standard cell layout style, cells are placed inrows. If two cells to be connected are sat in two non-adjacent rows, then their interconnection wires must pass through cell rows between the two rows. Therefore, to minimize
the chip area, the routing congestion of any region on the chip should be minimized anddistributed over that chip.
2.2S. Minimization of the total channel height: Since the chip width is fixed after the placement
stage, the minimization of the chip area is reduced to the minimization of the chip height,that is, the minimization of the total channel height.
2.3S. Development of a new standard cell model: In the standard cell layout design, we perform the layout design using a cell library, in which all cells have been pre-designed.
However, the conventional cell models were originally developed not for over-the-cellchannel routing, which is the most promising methodology to reduce the chip area, butrather for conventional channel routing. Therefore they are not always suitable for this.
For building block layout style:
2.1 B. Accurate estimation of routing area: Since, in the building block layout sty Ie, macro cells
are permitted to vary horizontally as well as vertically unlike the standard cell layout styleand are placed at any position in the chip, the routing stage is more complicated than thatof the standard cell layout style. Therefore a poor estimation of the routing area would
cause an increase in the chip area.
2.2B. Optimization of the shapes of soft blocks: In the building block layout style, the shapesof soft blocks are not pre-determined. Accordingly, their positions and shapes should bedetermined so as to minimize the chip area.
2.3B. Optimization of the pin positions of soft blocks: Since the pin positions of the nets connecting soft blocks are not determined in advance, a good pin assignment can improve thequality of the layout.
2.4B. Integration of pin assignment and global routing: In most of existing algorithms, pin
assignment and global routing are considered separately. However, since these stages arevery closely related to each other, they should be considered simultaneously to reduce thechip area and the total wire length.

1.4. ORGANIZATION OF THE DISSERTATION

17

Finally, in order to layout a VLSI circuit of more than 200K gates in a short tum-aroundtime, it is better to consider the following things in the development of layout design algorithms
for the both layout styles.

3.1.

Short computation time: Due to the practical requirement from the designers of VLSI
circuits, it is preferable that layout design tools finish each stage of the layout design
within at most a day for the designer to use them repeatedly and improve the quality of
the layout.

3.2. Hierarchical design methodology: One of the approaches to reduce the computation timeis to treat the problem hierarchically and to solve the sub-problem in each level of thehierarchy. This is called the hierarchical design methodology and is often used in thelayout design.

3.3.

Parallel processing: Parallel processing is also an effective methodology to reduce thecomputation time. To reduce the turn-around-time as well as to optimize the area andperformance of the chip, is an important issue in designing an ASIC. Recently, since
we can easily use a parallel processing workstation with 4 to 16 processors, introducing
parallel processing into layout design algorithms is a most promising approach if about
1/10 speedup of parallel algorithms is achieved.
Taking into account of the above issues, this dissertation discusses placement, global rout-ing, and detailed routing for the standard cell layout, andfloorplanning, pin assignment, andglobal routing for the building block layout. As mentioned in the previous section, placement,
ftoorplanning and global routing have the largest effect on the timing problem, that is, the performance of the integrated circuit. Consequently, for the placement, ftoorplanning and global
routing stages, we propose timing-driven algorithms. For the detailed routing stage for the standard cell layout style, we concentrate on the minimization of the chip area and the total wire
length of the integrated circuit. Since, in the building block layout style, detailed routing is
usually performed by a conventional channel router, we discuss channel pin assignment, which
optirrlizes the pin positions of blocks adjacent to a channel, so as to minimize the chip area andthe total wire length.

1.4

Organization of the Dissertation

This dissertation is organized as follows. In Chapter 2 to Chapter 4, the layout algorithms forthe standard cell layout will be presented.
In Chapter 2, the placement problem for the standard cell layout is discussed and a pathbased timing-driven placement algorithm, called POPINS, is proposed. To estimate the accu-

CHAPTER 1. INTRODUCTION

18

rate interconnection delay, the Elmore delay model is adopted explicitly as the interconnection
delay model so that we can apply POPINS to wider technologies than the conventional algorithms. POPINS is based on iterative improvement. First, an initial placement is generated
by a hierarchical timing-driven partitioning algorithm, and then it is improved iteratively. In thisimprovement step, POPINS selects a subcircuit and finds a new placement by nonlinear programming. Finally, in order to arrange cells in rows, timing-driven row assignment is performed.
Experimental results for benchmark data show that POPINS is more efficient and effective
than the previous timing-driven placement algorithms. Moreover, for further reduction of the°computation time, we extend POPINS to a parallel algorithm, called PAR-P PINS , running on a multi-processor workstation with shared memory and show its effectiveness throughsimulation experiments.
The global routing problem for the standard cell layout is examined in Chapter 3; a timingdriven global routing algorithm is proposed considering the channel density minimization. The
proposed router, called TV-QR, is based on a path-based algorithm and the Elmore delay modelis adopted for the delay calculation. Furthermore, it can minimize the channel density under the
given timing constraints. In the channel density minimization phase, we use 0-1 integer linear
programming. From the experimental results, we can see that TV-QR is better than the previous
net-based timing-driven algorithm. We also extend TV-QR to take over-the-cell(OTC) channelrouting into account. Although the conventional global routing algorithms do not consider the
OTC area, the proposed global router can explicitly consider this area which is used by an OTC
channel router.
In Chapter 4, the detailed routing problem for the standard cell layout that makes use of theover-the-cell areas is treated, referred to as the over-the-cell channel routing problem. Since thewiring interconnection topology of each net is determined so as to satisfy the timing constraints
in the global routing stage, we concentrate on the minimization of the chip area and the total
wire length. First, we propose two new standard cell models called BTM-N and ATM-O. Since
the conventional cell models were originally developed not for over-the-cell channel routing but
rather for conventional channel routing, they are not always suitable. The proposed cell models, on the other hand, are developed specifically for over-the-cell channel routing. Hence theover-the-cell area and the intra-cell area can be utilized so as to minimize the channel density.
Then, for these proposed standard cell models, we propose over-the-cell channel routing algorithms, called 3VR-BTM-N and 3VR-ATM-O, which can utilize the cell models efficiently.
Finally, we demonstrate the effectiveness of the proposed routers in simulation experiments. We
also show that the proposed algorithms can be applied to the conventional cell models and can
produce results comparable with the conventional routers.
Chapter 5 deals with the layout problems for the building block layout, such as ftoorplan-1.4. {JRGANIZATION OF THE DISSERTATION

19ning, pin assignment, and global routing. There are two types of blocks, that is, hard blocks
and soft blocks in the building block layout style, as mentioned in the previous section. For theformer, they are pre-designed and the shapes and pin positions of the blocks are pre-determined.
On the other hand, since they are not pre-designed in the latter, we need to specify the exact
shapes and pin positions in the layout design. In the ftoorplanning stage, we hence propose atiming-driven ftoorplanning algorithm TV-FPN which determines the shapes of soft blocks
as well as the positions of blocks so as to minimize the chip area. TV - FPN is based on bothnonlinear programming and topological constraint manipulation. Adopting the timing-driven
place1ment algorithm POPINS for the standard cell layout in Chapter 2 with some modification, we can effectively handle the timing constraint in ftoorplanning. Next, we propose atiming-driven global routing algorithm with pin assignment of soft blocks, called TV-QRPA.
Due to the high complexity of the layout problem, in most of existing algorithms, the pin assignment and global routing stages of the building block style are considered separately. However,since these stages are very closely related, they should be considered simultaneously to reducethe chip area. Therefore, for pin assignment and global routing, we combine pin assignment andglobal routing problems into one problem and propose an algorithm integrating global routing
and pin assignment. TV-QRPA also determines the shapes and the position of soft blocks.
Finally, channel pin assignment is discussed. In the building block layout style, detailed routing
is usually performed by a conventional channel router. To reduce the chip area and the total
wire length, we can optimize the pin positions of soft blocks which are adjacent to a channel
for channel routing. We hence propose an algorithm ACPA1 for the channel pin assignment
problem, which optimally minimizes both the channel density and total wire length in the channel and runs in a linear time on the number of pins in the channel. Experimental results for theindustrial circuits show that the proposed algorithms are very promising.
Finally, in Chapter 6, we summarize the results of this dissertation and discuss topics related
to future research.

Chapter 2
A T'iming-Driven Placement Algorithm for Standard Cell
LayoutThis chapter discusses timing-driven placement for standard cell layout, and proposes a pathbased timing-driven placement algorithm, called POPIN'S. To estimate the accurate interconnection delay, POPIN'S adopts the Elmore delay model [34] so that we can apply

POP'IN'S to wider technologies than the conventional algorithms. POPIN'S is based onhierarchical partitioning and nonlinear programming, and consists of three phases. In the firstphase, POPIN'S produces an initial placement by a timing-driven min-cut partitioning algorithm . Next, an iterative improvement phase betters the initial placement by nonlinear programming. The improvement problem is formulated as a problem of minimizing the total wire length
subject to timing constraints. Finally, a row assignment phase arranges cells in rows consideringtiming constraint. We also extend POPIN'S to a parallel algorithm, called PAR-POPIN'S,
running on a mUlti-processor workstation with shared memory. From the experimental resultscomparing with RITUAL [115], POPIN'S performs much better than RITUAL in regard to
the maximum violation ratio, the total wire length, and the cut size, and is more effective fromview points of the interconnection delay model and its extendability.

2.1

Introduction

There have been several studies about timing-driven placement, and they can be classified into
the following four approaches according to how to derive and treat timing constraints (Figure2.1), (1) net weighting approach [15,31,89, 103, 116], (2) net delay bounds approach [39,45,
53,97,122], (3) path weighting approach [44,91,131], and (4) path delay bounds approach[29,43,54,55, 114, 115].

Net weighting approach tries to satisfy timing constraints by assigning higher weights tonets which are part of timing critical pathsl (Figure 2.1(a)). The idea of net weights has beencombined with various concepts like iterative update of the net weights, recursive min-cut [Ill],and analytical placement. For example, the authors of [31] assign larger weights to the nets on
1Timing critical paths are usually specified by the designer based ~n simulation results in logic design before
layout design.
.

21

CHAPTER 2. TIMING-DRIVEN PLACEMENT

22-- • • • • • • • •~roachWeighting
based

1•

1.-.1 f.-.II~de~~(a) w J
Delay
boundsbasedPath based

Net based

de~

~
w2

de~

~

w3

(c)

del
~

~ 1

W

•1.-.1•f.-.II.-.I• • •1• • • ~ •1
de~
AI

de~
Aft

del

de~
AI

(b )DaLlOw) Dallow2 Dallow3

AI

(d)

/{liow

Figure 2.1: A classification of timing-driven layout algorithms.

critical paths than other nets, and critical paths are identified by path delay analysis in advance.
The placement algorithm treats those nets with larger weights preferentially to minimize interconnection delays on the critical paths. In [103], Riess et al. dynamically update the net weights
on the critical paths during successive placement improvement. They include these net weights
in the objective function of quadratic programming to minimize the weighted total wire lengthof nets.
Net delay (length) bounds approach tries to satisfy timing constraints by transforming timing
requirement into a set of upper bounds on net delays (Figure 2.1 (b)). Usually, upper bounds on
net delays can be transformed into constraints for the lengths of nets. For example, in [45],
Hauge et al. proposed the zero slack algorithm to compute delay bounds for all nets, and place
cells with these bounds by the placement algorithm based on a simulated annealing technique.
In [53], Igusa et al. assume that the designers could specify a set of upper bounds on the lengthsof timing critical nets, and min-cut placement techniques is applied to generate placements suchthat the estimated lengths of timing critical nets are kept within their upper bounds.
Path weighting approach treats constraints corresponding to maximum allowable delaysof critical paths, which is given in advance or is computed in the algorithms (Figure 2.1(c)).
Usually, these path delay constraints are transformed to some weights or costs based on theircriticality, and placement is done based on these criticality of the critical paths. For example,
in [44], the algorithm transforms the constraints of path delays to magnitudes of force, andplaces cells by a force directed pairwise relaxation algorithm using these magnitudes of force.
The author of [91] treated constraints of path delays as costs of paths and used these path delay
costs in hierarchical min-cut partitioning.

2.1. INTRODUCTION

23

Path delay bounds approach represents as timing constraints, path delay constraints directlyin the algorithms (Figure 2.1(d)). For example, in [29], Donath et al. represent timing constraints
as a set of parametric path delay equations at flip-flops(FFs) or primary outputs. They divide
the chip into several rectangles of the same size, partition a given set of logic circuits into thesome number of groups, and place each group into one rectangle on the chip. A placement
algorithm based on simulated annealing changes the positions of these groups based on timing
and wiring costs evaluated by parametric delay equations. Another strategy to deal with timing
constraints as path delay constraints is based on mathematical programming. The placement
problem is translated into a linear/quadratic programming problem by mapping both timing andphysical placement requirements into linear constraints. In [54] and [55], Jackson and Kuh
performed hierarchical placement based on linear programming with path delay constraints,
followed by a partitioning step. This objective function is a linear combination of the minimalslack on the longest path and the negative-weighted sum of wire capacitances. The second one
corresponds to the weighted sum of the length of all nets. This objective function is maximized
at each level of hierarchy in order to reduce the total wire length and timing violations. In [114]and [llI5], Srinivasan et al. developed a timing-driven placement algorithm, called RITUAL.
In the algorithm, the placement problem is formulated as a constrained quadratic programming
problem to minimize the total quadratic wire length under path delay constraint, and is solved
by a Lagrange relaxation technique.
The above net-based (net weighting and delay bounds) approaches can improve timing characteristics of a layout considerably without a significant increase in computation time, and they
can be easily implemented through extension of the existing algorithms. A major problem of the
net-based approaches, however, is that selection of optimal weights or bounds is very difficult.
Furthermore, because of neglecting interactions among nets, high weights or fixed bounds on aset of nets may create excessive delays in other nets. Moreover, use of individual net bounds
may result in overconstraining the problem, because timing constraints are intrinsically pathoriented, while they must be divided into net bounds before executing placement. On the other
hand, in the path-based (path weighting and path delay bounds) approaches, they need significantly more computation time due to the underlying mathematical models. The main advantage,
however, is that an optimal solution for each specified optimization problem can be guaranteed.
For the estimation of the interconnection delay, most of previous placement algorithms [29,43,54,55, 114, 115] use a simple RC model, and a wire length of each net is estimated on half
the perimeter of the bounding box of all the pins of a net [54,55] or on the sum of the Manhattan
distances among the source pin and all the load pins of a net [114, 115].
As seen above, many previous algorithms have suffered from trade-off between quality oflayouts and computation time. In particular, estimating interconnection delays tends to be inac-

CHAPTER 2. TIMING-DRIVEN PLACEMENT

24

curate because of some simplified assumptions on the delay models such as a simple RC model.
Since the capacitance and resistance of interconnection wires increase rapidly as mentioned in
Chapter I, placement algorithms should assume more accurate interconnection delay model. In
order to take advantage of precise mathematical models of path-based algorithms, we propose
in this chapter a path-based timing-driven placement algorithm, called POPINS 2, which utilizes nonlinear programming for placing a part of cells, instead of all cells, where we adopt
the Elmore delay model as an interconnection delay model. Moreover, for further reducing thecomputation time, we parallelize POPINS.
The remainder ·of this chapter is organized as follows. Section 2.2 describes an interconnection delay model and a timing constraint treated in this chapter, and formulates a timingdriven placement problem. In Section 2.3, we propose POPINS and in Section 2.4, we extend POPINS to a parallel algorithm, called PAR-POPINS, running on a multi-processor
workstation with shared memory. Section 2.5 shows experimental results and the evaluationof POPINS and PAR-POPINS. Finally, in Section 2.6, we summarize this chapter anddescribe future work.

2.2 Preliminaries
2.2.1

Layout and Delay Models

In this chapter, the row based design sty Ie such as the standard cell or the gate array layouts is
assumed. We also assume that the interconnections are realized by using two layers, the firstmetal layer (M!) and the second metal layer (M2). The MI layer is mainly used for horizontal
wiring and the M2 layer is mainly for vertical wiring.
An equivalent circuit of an interconnection is originally modeled as a distributed RC circuit,and the Elmore's delay equation [34] is often used to represent the interconnection delay. Whena multi-terminal net ni is implemented by a Steiner tree, Kuh gives an upper bound of the Elmore
delay from the source pin to a load pin j of net ni by the following equation [78] .
delij(Wi , L ij )= (cWi + L ClkJ(~O + r L ij ),

(2.1)

ki

where
Wi

: the total wire length of the Steiner tree of net ni.

Lij: the path length from the source to the load j of net ni.

c, r: the wire capacitance and resistance per unit length, respectively.

2POPINS: Performance Oriented Placement algorithm Improved by Nonlinear programming for Standard
cell layout.,

2.2. PRELIMINARIES

25

R;.o

: the equivalent output resistance of the source.

l:ki C lki: the sum of the load capacitances.

Figure 2.2 shows an example of the equivalent circuit of an interconnection represented by thedelay model. XiI, Xi2, Xi3 and Xi4 are wire lengths of each interval of the Steiner tree. In thiscase, 'Wi = Xii + Xi2 + Xi3 + Xi4, Lil = Xii + Xi2 + Xi3 and Li2 = Xii + Xi4, and we can compute
delays deli I (Wi, Lid and deli2(Wi, L i2 ) from equation (2.1).

xi2

source

=i -

xii

-

Xi3
load 1W'l·1- xi4load 2(a)load 1c$Tsource
RiO

I

T

Cll

Cl2

(b)

Figure 2.3: Estimation of the wire length of
net ni.

Figure 2.2: Interconnection delay model.
We employ equation (2.1) as the interconnection delay model. However, the wire capacitances are different between the first and second metal layers (Ml and M2), and hence wecompute the delay as the sum of delay of M 1 and M2. Furthermore, it is not practical to construct Steiner trees during placement from the point of computation time. Therefore the wire
length of net ni is estimated with half the perimeter length of a bounding box of enclosing all
the pins of net ni; the path length from the source to a load j of net ni with half the perimeter
length of a bounding box enclosing the source pin and load pin j. Figure 2.3 shows an exampleof the estimation of the wire length. Then the delay from the source pin to load pin j of net ni
is defined as,
delij(Wi, hi, ll ij , l2 ij ) = (CI . Wi + C2 . hi +L ClkJ(R;.O + TI • lI ij + T2 ·l2ij )

(2.2)

ki

where
: the width and height of the bounding box of net ni, respectively.
l1 ij, l2ij : the width and height of the bounding box enclosing the source pin and load pin jof net ni, respectively.

CHAPTER 2. TIMING-DRIVEN PLACEMENT

26(a) A timing constraint.

(c) Constrained paths.

(b) The constrained circuit.

Figure 2.4: A constrained circuit and constrained paths.

C1,C2: the capacitances of Ml and M2 per unit length, respectively.

T1,T2: the resistances of M 1 and M2 per unit length, respectively.

For example, we consider net ni shown in Fig. 2.3. Let the physical parameters as Cl = C2 =2.0x 10- 4 (pF//Lm), TI = T2 = 3.0x 10- 2 (0//Lm), ~ki C lki = 0.16(pF), and-Ro = 2.17x 10\0).
Let the length of the net ni be Wi = 100(/Lm), hi = 60(/Lm), llil = 80(/Lm), and l2il = 50(/Lm),
respectively. Then the delay deli2 from the source pin to the load pin 2 of the net ni is computed
as deli2 = (2.0 x 10- 16 x 100+2.0 X 10- 16 x 60+0.16 x 10- 12 )(2.17 x 103 +3.0 x 102 x 80+
3.0 X 102 x 50) = 4.17 x 10- 10 (s) = 0.417(ns).

2.2.2

Timing Constraint

In Chapter 2, the long path problem is considered and the related short path problem is ignored.
The work in this chapter could be extended to deal with both the problems. For simplicitX, it isassumed that edge triggered synchronizing elements are used. The methods described here canbe generalized to the case of level-sensitive latches. As there are many paths from a primary
input(PI) or an output of flip-flops(FFs) to a primary output(PO) or inputs of FFs, they can be
specified by pairs of pins, source ones and sink ones. Thus we specify a timing constraint as
tT = (ST)en Dela/low.,J, where ST is a source pin, eT is a sink pin, and Delallow .,- is the maximum

allowable propagation delay from the source to the sink. For example, if a circuit and its timing
constraint are given as shown in Fig. 2.4(a), the delay of any path from ST to en three paths in
the example, must be less than DelaLlow.,- (Fig. 2.4(c)).

2.2. PRELIMINARIES

2.2.3

27

Problem Formulation

We define some terminologies and symbols. Let L = (M, N) be a logic circuit where M={ml' rn2, ... , mM} is a set of cells and N = {nl' n2,"" nN} is a set of nets. Set Ni is a set ofnets connecting to cell mi, and a set M j is a set of cells connecting to net nj. Let P be a set ofpaths in the logic circuit L. For each path pEP, let M(P) be a set of cells which are on pathp and let N(P) be a set of nets which have connection to some cell on path p. For every timing

constraint tT E T, we define a constrained path for tT E T,. as any path p whose source is ST andsink is eT. Let CPT is a set of constrained paths specified by timing constraint tT E T and let

CP be a union of all sets of constrained paths CP n that is, CP = UVtrET CP T' Let Delallow(P)be the maximum allowable delay of pEP, and let Delact(P) be the actual propagation delay ofpEP.
For every timing constraint tT E T, let CL T = (CMT) CNT) be a constrained circuit, inwhich a set of cells and nets are defined as,

CM T =U M(P),U N(P).

CNT =VpECP rVpECP rIf CMt T are regarded as vertices and CNT as edges whose directions are given by corresponding
signal flows, a constrained circuit CL T is represented as a directed acyclic graph(Fig. 2.4(b)), in
which the source is ST and the sink is eT. Let Del actr be the actual propagation delay from ST toen defined as,
Del actr = max Delact(P).
VpECP r

(2.3)

For tilming constraint tT E T, if Del actr - Delallowr > 0, path p E CPT whose actual delay
Delact(P) is equal to Del actr is called a critical path. Figure 2.4 shows an example of our definition. Fig. 2.4(a) is a timing constraint tT = (ST) eT, Delallowr)' and Fig. 2.4(b) is the constrained
circuit corresponding to tT- There are three constrained paths as shown in Fig. 2.4(c).
Now, we formulate the timing-driven placement (TDP) problem.

[ The Timing-Driven Placement (TDP) Problem]
Inputs: a logic circuit L = (M, N), timing constraints T, and, physical parameters of equation(2.2) of the Elmore delay model

Output: positions of M which minimize the objective function
Obje(~tive Function:

the estimated total wire length of nets

Constraints: satisfy the layout model and the timing constraints ToPhysical parameters are constants for equation (2.2) for the interconnection delay. The estimatedtotal wire length is the sum of estimated wire length of all nets, and the wire length of a net isestimated by half the perimeter of bounding box of all the pins of the net.

28

CHAPTER 2. TIMING-DRIVEN PLACEMENT

2.3

POPINS: A New Timing-Driven Placement Algorithm

2.3.1

Overview of POPINS

Now we propose a timing-driven placement algorithm called POPINS. POPINS consistsof three phases [63]. First, we get an initial placement by a path-based timing-driven hierarchical min-cut placement algorithm and then improves it iteratively. In the improvement step,

POPINS selects a subcircuit, formulates the placement problem into a nonlinear programming
problem, and finds a new placement by solving the nonlinear programming problem. Because
the subcircuit includes at least one whole path which violates its associated delay requirement,
we can treat the timing constraint more flexibly than the net based approach. Moreover, to limit
the size of subcircuit makes it possible to reduce the computation time and to apply the algorithm
to large circuits. Finally, the placement is formed to a row based layout style at the timing-driven
row assignment phase. We will explain the details of each phase in the following subsections.

2.3.2

Initial Placement Based on Timing-Driven Hierarchical Min-cut
Partitioning (Phase 1)

In our initial placement, three points should be considered, to minimize the total wire length,
to distribute cells uniformly in the placement region, and to reduce the violations of timing
constraints as much as possible. As the violations will be eliminated in phase 2, it is not necessary
for the initial placement to satisfy all of the timing constraints.
We employ an extended version of the timing-driven min-cut placement algorithrn (TD-MCP) which we proposed in [131] as this phase, because it takes three points mentioned above
into account, produces a placement comparatively quickly, and uses the same interconnection
delay model as the proposed algorithm does. TD-MCP is based on ordinary hierarchicalquadratic partitioning. The quadratic partitioning is basically realized by applying the wellknown Fiduccia and Mattheysess' (FM) bi-partitioning algorithm [36] three times. Both logic
cells and a layout region in which the cells are placed at the center is divided into four parts(Fig.
2.5(a)).

The FM algorithm can obtain a good bi-partition in a short computation time 3 . However, thiscannot handle timing constrains. Therefore we extended the FM algorithm so as to consider thetiming constraints. The PM algorithm is based on iterative improvement, and at each iteration,
elementsOn this case, cells) with the maximal gain are moved to the opposite side of the partition
one by one. Let a cut size be the number of nets crossing the cut line. The gain for cell mi, wecall it cut gain, 9cut i here, means the amount of decrease in the cut size if mi is moved to the
opposite side. Once a cell is moved actually, it is locked and never moved any more. Then the
3The running time of the PM algorithm is O(n) where n is the number of tenrunals in the circuit.

2.3. 1)OPINS: A NEW TIMING-DRIVEN PLACEMENT ALGORITHM

~

•

1.1

29

flow of conventional partitioning methods.....................................................
.... .

0000

0 ..

o
o

(d)

(e)

( f) after 4 by 4
partitioning

Figure 2.5: Flow of the proposed hierarchical quadratic partitioning.

gains of all the cells connecting to that cell are updated. These operations are repeated until all
the ceHs are locked.
In addition to the gain for minimizing the cut size, in the timing-driven FM algorithm (TD-F M) ., we introduce three other gains; timing gain, gtimingi' terminal gain, gtermi' and wire gain,
gwirei. The terminal gain is to consider terminal positions of nets and can realize the similareffect of the terminal propagation technique [32] in short computation time. The wire gain is toconsider the wire length of nets. Since the minimization of the cut size doesn't always minimize
the total wire length of nets, we explicitly consider the total wire length during the partitioning
using the wire gain. In the following, we only explain the timing gain in detail. The definitionof the two other gains are described in Appendix A.l.
Let JiDel(p) for each constrained path p E CP be defined as follows:
flDel(p) = max(Delact(P) - Delall ow (P), 0).

(2.4)

flDel(p) means the excess of the delay time of p against the allowable delay time of p. If cell

mi is lmoved to the opposite side, the sum of the difference of flDel(p) of paths passing mi canbe written as,
gtimingi =L(flDel(p) - flDel(p),),(2.5)\fPEcplmi E CM(P)

where flDel(p) and flDel(p)' denote the excess of the delay of constrained path p before andafter rnoving the cell, respectively. We call gtimingi the timing gain. To move the cell with large
timing gain means to decrease the delay time of paths which contain it and violate their allowabledelay time. For example in Fig.2.6, there are two paths passing cell mi. Since flDel(PI) = 10,
I1De[(-P2) = 0, I1Del(p])' = 0, and flDel(P2)' = 0, the timing gain of mi is gtimingi = 10. If mi is

moved from the left region to the right region, the timing violation of the path p] is removed.
Consequently, the gain of cell mi is defined as the sum of the above four gains, that is,(2.6)

CHAPTER 2. TIMING-DRIVEN PLACE'MENT

30

partitioning

MJel(p f} = 10, ~Del(P2} = 0

partitioning

MJel(p f}' = 10, ~DeL(p2)' = 0, gtmingi = 10(a) before moving cell mi(b) after moving cell mi

Figure 2.6: Example of timing gain gtimingi.

where c\(, /3, " and {; denote positive constants 4.
In conventional hierarchical partitioning algorithms, partitionings are performed in the orderof Fig.2.5(a), (b), and (f). Since, in the conventional hierarchical partitioning, cells cannot be
moved to other partitioned regions which have been partitioned at an upper level partitioning,
the upper level partitionings influence the quality of lower level partitionings intrinsically. In

TV-MCP, we hence hierarchically apply the above bi-partitioning algorithm by shifting thepartitioned region as shown in Fig. 2.5(a}-v(f) to reduce the effect of upper level partitionings.
Since precise cell positions are already determined after the first partitioning as shown in Fig.
2.5(b), the timing, terminal, and wire gains can be accurately calculated and a good initial placement can be obtained.

2.3.3

Iterative Improvement Based on Nonlinear Programming (Phase 2)

An initial placement may violate some timing constraints. The objectives of phase 2 are toeliminate all the violations and to minimize the total wire length of the placement. To achieve theobjectives, we transform the placement improvement problem to a mathematical programming
problem. But mathematical programming tends to require much computation time and memory
space. Therefore we apply mathematical programming to subcircuits, for which the formulated
problem can be solved in a practical computation time and with practical size of memory space.
In the following, we first explain selection of a subcircuit and then formulate the placement
problem as a nonlinear programming problem.
4In our experiment, we set as Q = 1, f3 = 3, I = 4, and 8 = 2.

2.3. 1?OPINS: A NEW TIMING-DRIVEN PLACEMENT ALGORITHM

31

Selection of a Target Subcircuit
Now, 'we define a target subcircuit as Lmov = (M mov , N mov ), where Mmov is a set of cells, called
movable cells, of the subcircuit, and N mov is a set of nets, called movable nets, each connecting

to at least one movable cells. Cells other than movable cells in the whole circuit are called fixed
cells and their set is represented by M fix (= M - Mmov). Nets other than movable nets in thewhole circuit are calledfixed nets and their set is represented by N fix (= N - N mov ).
The target subcircuit is selected by the following target selection algorithm(TSSA). In thealgorithm, randi(O, 1) is a real number between 0 and 1 randomly generated for each cell mi.

[ The Target Subcircuit Selection Algorithm(TSSA) ]Step 1 :Find a constrained path p E CP which has the largest violation ratio (t7lact(P~))
and has note allowbeen selected in the last k(> 0) iterations;

Step 2 :Mmov = M(P);Mfix = M - Mmov;
N mov =N(p); N fix =N -Nmov ;Step 3 :Calculate connectivity of cells in M fix;

Step 4 :If (IMmovl + INmovl) 2: (preset value), then output Mmov and N mov and stop;

Step 5 :Search a cell mi E M fix in the decreasing order of its connectivity until the condition
randi(O, 1) 2: (preset value) is satisfied;

Step 6:

Mmov = Mmov U {md; Mfix = Mfix - {md;N mov = N mov U Ni; N fix = N fix - Ni;

Step 7 :Update connectivity of cells in M fix and go to Step 4;oFirst, T SSA finds one of constrained paths with a large violation ratio. The violation ratiois the value of actual delay time of a constrained path (or a constrained circuit) divided by theallowable delay time of it, i.e., Delact(P)/ Delallow(P). The candidates for the constrained path
are selected from constrained circuits which are the largest 10rv20 percent in all the constrained
circuits in point of the violation ratio. But, to improve the placement in a small number of
iteration, TSSA doesn't select any constrained circuits which have been selected in the lastk(> 0) iterations 5 of phase 2. First, let the constrained path be the initial subcircuit. Next, thesubcircuit is expanded by adding cells one by one. The added cell should have large connectivity,
which is the number of connections to the present subcircuit. To avoid repeatedly selecting
the same cell to be added to the target subcircuit at each iteration of phase 2 , we introduce
a randomness in the selection step of T SSA and determine whether the cell is included(See.
Step 5). If included, all the nets connecting to it are redefined as a set of movable nets. To
solve the problem in a practical computation time, we must limit the number of variables of themathematical programming problem. Hence, the growing process of the subcircuit continues
SIn the current implementation, we set k to three.

CHAPTER 2. TIMING-DRIVEN PIACE1~ENT

32

until the number of variables of the mathematical programming problem reaches to a given
constant (Fig. 2.7).
There are two reasons why we construct a target subcircuit in such a way. First, if a subcircuit
around a violated constrained path is improved at the same time, cells on the path must be able
to move fairly freely. Second, cells with many connections with the constrained path must be
included in the same constrained circuit so that moving the cells connecting with the constrained
path will be effective to reduce the timing violation.

load 1load 2(~i ' Ymax; );-rthe critical pathwith the maximum

load 4

... +

Ih

load3

o

Figure 2.7: Selection of a target subcircuit.

l'Wi

movable cell

II fixed cell

Figure 2.8: Variables for net ni.

Constraints of Nets
Next, we explain how to formulate the placement problem into a nonlinear programrning(NLP)
problem. To do this, we need variables to represent the wire lengths of movable nets as wellas the positions of movable cells. Let Xj and Yj be the X and Y coordinates of movable cell
mj E Mmovl respectively. Denote by Wi and hi the width and height of the bounding box of net

ni E N mov ) respectively(Fig.2.8).

Then, we can represent the bounding box of movable net ni

by the following inequalities:eN!:=I mk E M i n Mmovl

Xj-

Xk::; Wi }

\lmj

Yj

-

Yk::; h i\lni E N mov(2.7)

They mean that for any pair of movable cells connecting to ni, they are completely induded in
the bounding box of ni. When ni is connected to fixed cells, the following inequalities should

2.3.

~POPINS: A NEW TIMING-DRIVEN PLACEMENT ALGORITHM

33

be satisfied:- X mini

~ Wi,

Yj

- Y min ,~ hi

X maxi

- Xj

~ Wi,

Y maxi- Yj~ hi

X maxi- X mini~ Wi,

Y maxi- Y mini~ hiCl'{2 : X·J)

Vmj E Mi n M mov ,(2.8)

Vni E N mov

where X mini and X maxi (resp. Y mini and YmaxJ are the minimum and maximum X (resp. Y)
coordinates in fixed cells of Mi. If a net has some fixed cells, the bounding box of the fixed cells
can be constructed, and for any pair of a movable cell and the bounding box, their bounding box
is completely included in the bounding box of ni.
To calculate delay del ij from the source to load j of net ni, we introduce variables lI ij , l2ij
to represent the horizontal and vertical lengths of the bounding box of the source and load j.
ml E Mi is corresponding to
CS':

Xl

Xk
Xl

Xk

<
<

llij, YklI ij , Yl

Yl
Yk

<
<

l2 2J· .
l2 2J· .

}the source of ni,(2.9)

Vmk E Mi(k =ll),

Vni E N(P),Vp E CP IM(P)nMmov:fJ

where (Xk, Yk) and (Xl, Yl) denote the center coordinates of cells corresponding to the sourceand sinks of ni.

Constraints of Path Delay
In order to consider the timing constraints in the mathematical programming problem, as mentioned in the selection of a target sub circuit, target subcircuit £mov is made grow from a constrained path(Fig. 2.7). However, there are many other constrained paths which are partiallyor entirely included in the subcircuit. If this fact is not considered during the improvement, it
would. happen that while violation of the first selected constrained path might be eliminated,other constrained paths might cause timing violations. Therefore we have to consider all of theconstrained path delays in target subcircuit £mov as constraints. Constraints on constrained pathdelays can be written as follows.
CP :

2.:
2.: .

delij(Xmaxi - X mini , Y,naxi - Y mini , llij, l2 ij )Vni EN(p )nNf ix+

VniEN(p)nNm.ov

delilwi,hi,llij,l2ij) +2.:

Delswitchj<

Delallow(P ),VmjEM(p)Vp E CP I Me;) n Mmov =10,

(2.10)

CHAPTER 2. TIMING-DRIVEN PLACEMENT

34

where Delswitchj is the switching delay of cell mj. In this inequation, the right side means theallowable delay time of a path and the left side its actual delay time of it. The first tern1 of theleft side is the sum of delay of fixed nets, the second is the sum of delay of movable nets on it,
and the third is the sum of switching delay of cells on the path. From equation (2.2), the above
inequalities are quadratic.

NLP Formulation of the Problem
The objective of our placement improvement problem is to minimize the total wire length. However, a placement produced by mathematical programming with minimizing the total wire length
in general tends to make the distribution of cells imbalance, i.e., cells may concentrate in a 10cal layout region. This is because the objective is not concerned with the differences of length
between nets. If many cells overlap each other, they must be moved far away in the post processing, diminish the "goodness" of the placement obtained in phase 2. But it is difficult to add
more constraints or to add a special term in the objective function which explicitly makes cells
uniformly distributed on the chip so as to solve in a practical computation time. Therefore, to
distribute cells uniformly on the chip, we rearrange the objective function so as to minirnize thesum of the square of wire lengths. Thus, it tends to make the wire length of each net more eventhan a linear objective function even if the sum of wire length is the same in both objectives.
Based on the above arguments, we formulate the placement problem as the following mathematical programming problem:
mInlmlze

2:(Ji(W; + hf)(2.11)

VniENrnov

subject to

CNI U CN2 U CS u CP

where (Ji denote the constant considering a criticality of net ni. Since the objective and timing
constraints C P are quadratic, this problem is a nonlinear programming problem(NLP).

The Algorithm of Phase 2
Phase 2 of POPINS iteratively improves a placement so as to minimize the wire length andto satisfy the timing constrains. At each iteration, it first performs timing verification and calculates timing violation ratios for all the constrained circuits. Then, it constructs a target subcircuit,
solves the formulated nonlinear programming(NLP) problem, and places cells in the target subcircuit based on the result of NLP problem. These processes are repeated until the mlaximum
violation ratio becomes less than a pre-determined value or the iteration count reaches to a preset value. In the current implementation, we use the MINOS 5.4 [94] package to solve a NLP
problem. The MINOS 5.4 uses a projected augmented Lagrangian "algorithm to solve this type

2.3. POPINS: A NEW TIMING-DRIVEN PLACEMENT ALGORITHM

35

of NLP problem. The detailed description of MINOS 5.4 package is given in Ref. [94].
The outline of phase 2 is shown below.

[ Phase 2 : Iterative Improvement Based on NLP ]Step

1: Perform timing verification to all the constrained circuits; RepeatCount = 1;

Repea1t

Step
Step
Step
Step

2: Select a target subcircuit £mov to be improved;
3: Find all the constrained paths which pass the cells of Mmov;
4: Formulate the nonlinear programming problem (2.11) and solve it by MINOSS.4;
5: Perform timing verification to the constrained circuits CM T which have cells of
Mmov;

Step
Until

2.3.4

6: RepeatCount = RepeatCount + 1;

the maximum violation ratio becomes less than a pre-determined value, that is,
maxvPEcp(Delact(P)/ Delallow(P)) 5:(preset value 6)
or RepeatCount > (preset value7);oTiming-Driven Row Assignment (Phase 3)

Phase 3 assigns cells that are distributed on the chip in phase 2 to cell rows. Let R be the numberof cell rows, and let R 1 , R 2 , • •• , RR represent a set of cells in each row. Each cell is given its
area, and let a(M) denote the sum of the area of all the cells in M. The width of the chip isdetemlined by the width of the longest cell row, and if the widths of all the rows are same, then
the width of the chip is minimized. Thus we give the same capacity, denoted A, to all the cellrows, and all the cell rows must satisfy a(Ri) ~ A, i = 1, ... , R. The cell rows are given ycoordinates Yi, }ii, ... , YR ·'1Iml}l~~~1
g3~~
I-++-+-H-+HH+++-f~ ~ R4

1~I=r: ]==IfJIB3ffifIIfHH(a) row assignment of y-direction~

amtVWIilii~

ftm1XVMwttH(b) row assignment of x-direction

Figure 2.9: Row Assignment.

First, the proposed row assignment algorithm(TV- RA) groups cells between each two adjacent cell rows, and assigns cells in each group to slots in the two rows by the linear assignment
6Currently, we set the permissible violation ratio to 0.80.
71n the current implementation, we set the upper bound of the numt)er of iterations to 20.

CHAPTER 2. TIMING-DRIVEN PLACEMENT

36

considering the wire length and the timing constraints (row assignment of y-direction) (Fig.
2.9(a)). Next, TV-RA constructs cell groups based on x-coordinates of cells from left to rightof the chip(Fig. 2.9(b )), and reassigns cells in each group to the slots of the improved region by
the linear assignment in a similar way of the y-direction (row assignment of x-direction) . The
above operations are iteratively perfonned while the placement is improved. In the following,
row assignment of the y-direction is described.
First, we explain how to construct the groups. There are R groups, denoted QI, Q2, ... , Q R,
and they have capacities which are Ai = A, for i = 2, ... , R and Al = 3A12. All cells are sortedby their y-coordinates, and the first group Qi is constructed by adding cells in the sorting orderuntil the sum of the area of cells is equal to the capacity of the first group Qi. Similarly, theremaining groups are constructed. Next, cells are assigned to slots in cell rows. We transfonn
this assignment problem to a linear assignment problem. Because of a(Qi) 2:: A, if tlhe cells
in group Qi which are not assigned to the slots of cell row Ri but the slots of cell row Ri+l'then cells assigned to Ri+l are added to the next group Qi+l and are reassigned in the next linear
assignment problem.
The linear assignment problem LAP(Qi, Si) to assign cells in the group Qi to the slots of cellrow Ri is formulated as follows.

[Linear Assignment Problem: LAP(Qi, Si)]
minimize:

LmjHh LSkESi CjkZjk

subject to:

LSkESi Zjk = 1,

Vmj E Qi,

LmjE9i Zjk = 1,

VS k E Si,

Zjk E{O, 1},

Vmj E Qi,

VS k E Si

where Si denotes a set of slots to which all the cells in Qi are assigned, and Cjk represents a costwith which cell mj is assigned to slot Sk.
Let i1l i (mj, Sk) be a difference of the wire length of net ni connected to cell mj when mj
is assigned from the current position (slot) to slot Sk. The timing constraints are considered by
the criticality of nets. For the timing constraint tT E T, let DelaLlowT be the allowable delay and

Del actT be the actual delay. We define the degree of the violation of net ni, denoted Wi, as(2.12)

Let !(Wi) be a penalty function of the criticality Wi of net ni which depends on the violation ratio

2.3. P'OPINS: A NEW TIMING-DRIVEN PLACEMENT ALGORITHM

37

of path p passing it. In the present implementation, !(Wi) is defined as follows.
(Wi::; 0.7)
(0.7 < Wi ::; 0.9)
(0.9 < Wi)(2.13)

Constants kl and k2 are chosen based on experimental results.
Then cost Cj k is defined as
Cjk= L I1l i (mj, Sk)!(Wi).

(2.14)niENj

The tirning-driven row assignment algorithm TD-RA may be stated as follows.
[Phase 3 : Timing-Driven Row Assignment( TD-RA)]
Step
Repea1t

1: RepeatCount = 0;

1* Row assignment of y-direction *1
Step 2: Construct groups Q I, 92, ... , QR based on y coordinates of cells;
Step 3: i = 1;
RepeatStep 4: For path p E CP, update Delact(P), and for net ni, update Wi;
Step 5: For cell mj E 9i and slot Sk E Si, compute Cjk;
Step 6: Solve the linear assignment problem, LAP(9i, Si), and assign cellmi E 9i to M(R i ) or M(Ri+d where M(Ri) is a set of cells asStep
Step

signed to cell row Ri;
7: For cell mj E M(Ri), update its coordinates;

8: 9i+l = 9i+l U M(Ri+l);
i = i + 1;

Until
i > R;
1* Row assignment of x-direction *1
Step 9: Construct groups 9~, 9~, ... ,9k, based on x coordinates of cells;
Steo 10: i = 1;
RepeatStep 11: For path p E CP, update Delact(P), and for net ni, update Wi;
Step 12: For cell mj E 9~ and slot Sk E SI, compute Cjk;
Step 13: Solve the linear assignment problem, LAP(9~, SD, and assign cellmi E 9i to M(RD or M(R~+I) where M(RD is a set of cells assigned to improved region R~;
Step 14: For cell mj E M(RD, update its coordinates;

Step 13: 9~+1 = 9~+1 U M(R~+I);i = i + 1;
Until
i > R';
Step 14: RepeatCount = RepeatCount + 1;
Until

there is no improvement in the pre-determined number of consecutive iterations
or RepeatCount = (preset number) 8.

o

SIn the present implementation, if there is no improvement in three consecutive iterations or RepeatCount = 20,
the algorithm is terminated.
.

38

CHAPTER 2. TIMING-DRIVEN PIACf.;MENT

2.4

Extension to a Parallel Algorithm PAR-POPINSIn this section, to reduce the computation time further, we extend POPINS to a parallel algorithm running on a multi-processor workstation with shared memory [62]. We call this algorithm PAR-POPINS. To obtain high efficiency of parallel processing, we restrict the amountof communication among processors as small as possible by dividing the placement problem
into several number of sub-problems which can be treated independently. In phase 1, at theupper levels of partitioning hierarchy, we perform a bi-partitioning by several processors, andat the lower levels, perform partitionings of each region in a level by each processor in parallel.
In phase 2, we formulate a set of nonlinear programming problems for several target subcircuits
and solve them in parallel. In phase 3, we assign a set of row assignment problems to eachprocessor and again solve them in parallel. In the following, we briefly explain the overview of
introducing the parallelism to each phase. The details are described in Appendix A.2.

2.4.1

Introducing Parallelism to Phase 1 : Overview

At the upper levels of partitioning hierarchy, we have to handle the entire circuit as well as toreduce the computation time, and we perform a bi-partitioning by using several processors inparallel(Fig. 2.l0(b)). In general, it is difficult to directly make parallel a partitioning algorithm,
say the PM algorithm, based on group migration because it consists of a set of sequential operations intrinsically. In PAR-POPINS, we hence divide the entire set of cells into a sets of cells
and perform independently a partitioning of each set of cells. As illustrated in Fig. 2.11" we firstassign every cell to each processor based on an initial partition(Fig.2.11(c)). Here, if cells which
are connected to each other are assigned to different processors, the partitioning gain of thosecells would not be calculated correctly. Hence we introduce a set of separator cells that divide
the entire set of cells into a few sets of cells which have no connection among them. Next, eachprocessor performs independently the partitioning of cells assigned to it with the T1J-F.M mentioned in Section 2.3.2 (Fig.2.ll(d)), and then one processor performs the partitioning of the setof separator cells. To obtain a bi-partition of the whole cells, we merge the partitioning resultsof each processors(Fig.2.11(e)). Then, we reassign cells to each processor based on the current
bi-partition. These operations are iteratively performed until the bi-partition is not improved or
the iteration count reaches a preset value.
At the lower levels of hierarchy, since the size of the partitioning problem of each region, thatis, the number of cells to be partitioned, is smaller than that of the upper levels (Fig.2.1 O(c)), in

PAR-POPINS, we apply the partitioning algorithm described in Section 2.3.2 independently
to perform partitioning of each region at a level.

2.4. EXTENSION TOA PARALLEL ALGORITHM PAR-POPINS

Proc.l

•

hoc

'

Proc.

.ti9.1m-•I[ru[Q][9[ii]@)@]@]@]@]@][Q][ii]@]§~@]•

Proc.3(a) input circuit

Proc.211±1I~," . .
m ....

prOC'EJ'.' ''''..

39

Proc.4(b) upper levels(c) lower levels

Figure 2.10: Introducing parallelism to phase 1.

•._~_----J•

separator cells

I·I!I • ·E·_I(b) an initial partition

I

I

I

(c) processor assignment (d) perform partitioningsof cells
independently(e) marge results of all processors,and perform partitioningof a set of separator cells

Figure 2.11: The parallel algorithm of a bi-partitioning at the upper levels.

2.4.2

Introducing Parallelism to Phase 2 : Overview

As shown in Section 2.3.3, phase 2 iteratively improves the placement obtained by phase
1 using NLP. Introducing parallelism to phase 2 is achieved by solving a set of the
NLP problems for each target subcircuit by several processors in parallel (Fig.

2.12).

However, if one target subcircuit hasconnections with another target sub-target sub-circuits

circuit and they are improved concurrently, errors of wire length estimation and path delay estimation
may be occurred.

Therefore con-strained paths which are contained
several target subcircuits are divided
into subpaths by introducing sepa-

rator cells as shown in Fig. 2.12,
and we construct a set of target sub-selection of constrained paths

separator cell
soLve NLPs in paralleL

Figure 2.12: Introducing parallelism to phase 2.

circuits that have no direct connection with other target subcircuits,
which in time can be improved concurrently. The divided l)aths are independently consideredCHAPTER 2. TIMING-DRIVEN PLACEMENT

40

in the formulation of the NLP problem of each subcircuit.
In phase 2, PAR-POPINS works according to a master-slave computation model. Firstly,a master processor performs the timing verification and calculates violation ratios for all constrained circuits. Next, the it constructs a set of target subcircuits, forks slave processors, andsends a target subcircuit to each slave processor. Then, each slave processor formulates a NLP
problem, and solves it. Finally it sends the result of NLP problem back to the master processor.
These processes are repeated until the maximum violation ratio is less than a pre-determined
permissible value or the iteration count reaches to a preset value.

2.4.3

Introducing Parallelism to Phase 3 : Overview

Phase 3 assigns cells that have been distributed on the chip in phase 2 to cell rows. As shownin Fig. 2.13, parallel processing is introduced to assign a set of row assignment problems ofsome consecutive groups of cells to each processor, and each row assignment is independently
performed by each processor.

(a) Assignment of x-direction(b) Assignment of y-direction

Figure 2.13: Introducing parallelism to phase 3.
Proc. )

Proc. 2r

Proc.2~:!=:..."-:,'\.

Proc.)tIIt(a) First loop

II

I

R

I

~:

,~

,'\.'\.'\.'\.

' R4
Rs
Proc.2 , R6

I

I

II

(b) Next loop

Figure 2.14: Shifting of the group boundaries.

At each iteration of the outer loop of timing-driven row assignment(TD- RA), we change
cell groups assigned to processors by shifting the group boundaries as illustrated in Fig . 2.14. If
we use the same sets of cell groups at each iteration, then the cells in the last cell group of eachprocessor will be only placed at the same cell row (for example, R3 and 14 in Fig. 2.14( a)) in
the later loops. Consequently, these cells cannot be moved to the next cell row and this degrades2.5. EXPERIMENTAL STUDIES

41

the quality of the placement.

2.5

Experimental Studies

We have coded the proposed sequential and parallel placement algorithms, called

POPINS and PAR-POPINS, in C language. The algorithms have been implemented on
a SPARCserverl000 of Sun Microsystems, Inc. (135MIPSx 4 CPUs, 256MB main memory)on SunOS5.4 with multi-thread library. To show the effectiveness of the algorithms, we have
performed several experiments. Table 2.1 shows a part of the experimental data. The details of
the experimental results for all data are shown in Appendix A.3. In Table 2.1, data "primary2","avq-small" and "avq-Iarge" are the benchmark data distributed from Microelectronics Centerof North Carolina(MCNC) [77] and others are ISCAS benchmark data [11]. For ISCAS benchmarks, logic synthesis and technology mapping were performed by SIS 1.2 [110]. In this table,"#cons" is the number of timing constraints. For each data, we gave a clock cycle time as thetiming constraints. We first generated a placement by a non-timing-driven placement algorithm
and then determined the clock cycle time multiplying that of the placement by 0.8

A.J

0.9. The

details of the technological parameters are given in Appendix A.3.

Table 2.1: Characteristics of experimental data.
Data

II #cells I #nets I #I/O I #rows I #cons I

pnmaryavq-small
av -large

21854 22124
64
80 606425114 25384
64
86 6064#cons : the number of timing constraints.

2.5.1

Evaluation of POPINS

We compared POPINS with RITUAL [115]. RITUAL is one of the most powerful performance driven placement algorithms which can satisfy a given clock cycle, and applies the mathematical optimization method to the whole circuit. The interconnection delay model is different
from ours in that the wire resistance is not considered. Nevertheless, we evaluated the resultof RITUAL by using our model to compare with our res'ults. Since, in RITUAL, a cell isCHAPTER 2. TIMING-DRIVEN PLACEMENT

42

Table 2.2: Placement results of the proposed method POPINS and RITUAL [115].
Data

length()")

ttme
(sec

C1
C2
C5
C6
C7
s9234
s15850s38417
pnmaryavq-small

av -lar e

C5

RITUAL

POPINSo 0.77 0.17 24221879
0.83 0.17 22551201
POPINSo#Vios : the number of timing violations

385
291#h-cuts#v-cuts

:
:

(-)
(-)

156277268321

450367
the cut size of the horizontal direction
the cut size of the vertical direction

not permitted to have more than one output pins, we could not test "primary2"rv"avq.large".
In Tables 2.2 and 2.3, we show the placement results of POPINS and RITUAL. In Table

2.2, #Vios is the number of violated timing constraints, Delay Max., defined as Delay Max.

= maxVtrET Delact r / Delall owr , is called the maximum violation ratio and if it is less than or equal
to 1.0, the placement satisfies all timing constraints. Delay Ave. = I'~h LVtrET Del actr /lJel all owr
is the average violation ratio, and length is the total wire length estimated by the Manhattan
distance (A). time is the running time by a SPARCserverlOOO (seconds). For "sI5850" and"s38584", RITUAL was not able to produce the placement due to errors. In Table 2.3" #h-cuts
and #v-cuts show the distribution of the cut size on the chip for the horizontal and vertical directions, respectively. In this experiment, we uniformly generated 15 cut lines for each direction
and counted the number of nets crossing the corresponding cut line": #h-cuts Max. and #h-cuts

2.5. EXPERIMENTAL STUDIES

43

Ave. are the maximum and average cut sizes of the horizontal(x) direction, respectively. Similarly, #v-cuts Max. and #v-cuts Ave. are the maximum and average cut sizes of the vertical(y)direction, respectively.

140

The Distribution of the cut size for horizontal direction C I

120+ .. • . - -. ~The Distribution of the cut size for vertical direction C I

140! - - +- - ...,

....

....

.+

100

160

lH·U~ :-::-*.. . + .. +.

.•.. ~ ffiU~ :-::-. + - - +- - -+.... - -+ - - + ~'

120

:1 00

:l
;;;
:;80
u

Vi

:;80

u

60

60

40
40
20 0

20
I

2

3

4

5

6

7

8

9

10

11

12

13

14

15

00

16

1

2

3

4

5

6

Cut Line (X)

7

8

9

10

11

12

13

14

15

16

Cut Line (Y)Figure 2.15: The distribution of the cut size for Cl.

From the results of Table 2.2, POPINS improved the total wire length by 14.6% (ave.)and 33.3% (max.) compared with RITUAL. As to #h-cuts and #v-cuts, POPINS also produced smaller cut size placements than RITUAL. Figure 2.15 shows the graph representationsof the cut size distribution for the horizontal and vertical directions for data "C 1". As a result,

POPINS can produce better placements in regard to the maximUm/average violation ratio, thetotal wire length, and cutsize distribution.

time(sec)
140000[20000,/

CPU time comparison

RlTUAL I~ •• POPINS

100000
80000

/

40000
20000

V
/

_. ~

o
o

4000

/

!

V

/

/v

/

/

V

~.

8000

12000

16000

20000

24000

Number of cells

Figure 2.16: CPU time comparison between POPINS and RITUAL.

For the CPU time, since RITUAL applies the mathematical optimization method to thewhole circuit, as the number of cells increases, the computation time of RITUAL increases more
rapidly than that of POPINS as shown in Fig.2.16. The 'simulation results shown here have

CHAPTER 2. TIMING-DRIVEN PLACEMENT

44

Table 2.4: Results of phase 1 of PAR-POPINS and POPINS.
Data
C6

s38584
avq-small

POPINS

avq-Iarge

1

1.00

0.26

28457150(1.00)

18954

Table 2.5: Results of phase 2 of PAR-POPINS and POPINS.
Data
C6

s38584
avq-small
avq-large

POPINS

1

1.00

0.26

28457150(1.00)

1368(1.00)

demonstrated that the effectiveness of the combination of hierarchical partitioning and nonlinear
programming optimization.

2.5.2

Evaluation of PAR-POPINSIn order to evaluate each phase of the parallel algorithm, we compare the results of each phaseof PAR-POP INS with those of POP INS. The details of the experimental results are shownin Appendix A.3.3.
First, the comparison results of phase 1 of PAR-POPINS and those of POPTNS isshown in Table 2.4. It is obvious from Table 2.4 that the average total wire length of PAR-POPINS is comparable to that of POPINS, but the number of timing violations of PARPOPINS is larger than that of POPINS for every case. As to computation time, PARPOPINS was 1.2 (ave.) and 2.4 (max.) times faster than POPINS. From these sin1ulation
results, the parallelization of phase 1 is suitable for the large scale circuits.
Next, Table 2.5 shows the results of phase 2 of PAR-POPINS and POPINS. In
these experiments, we used the results of phase 1 of POPINS as the inputs of phase 2 of

PAR-POPINS and POPINS. From Table 2.5, PAR-POPINS produces the cOITlparable
results to POPINS in terms of the total wire length. As for the computation time, PARPOPINS takes longer than that of POPINS for "avqs". Since PAR-POPINS were2.6. CONCLUDING REMARKS

45

Table 2.6: Results of phase 3 of PAR-POPINS and POPINS.
Data

C6
s38584

avq-small
avq-Iarge

not able to remove 16 timing violations in "avqs" efficiently, PAR-POPINS tried to improve the placement repeatedly and the computation time was hence longer than POPINS.
For all data, PAR-POPINS is 1.7 (ave.) and 4.7 (max.) times faster than POPINS, but

PAR-POPINS is 2.6 (ave.) times faster except for "avqs". These simulation results demonstrated that the introduction of parallelism to phase 2, which solves the nonlinear programming
problems for each target subcircuit by several processors in parallel, is effective to reduce thecomputation time without degradation of results.
Next, we show the results of phase 3 of PAR-POPINS and POPINS in Table 2.6. Wealso used the results of phase 2 of POPINS as the inputs of phase 3 of PAR-POPINS andPOPINS. From Table 2.6, PAR-POPINS can produce a placement with satisfying all thetiming constraints in all the benchmark data. As to computation time, PAR-POPINS is 3.6(ave.) and 5.0 (max.) times faster than POPINS. As concerns the total wire length, the resultsof PAR-POPINS is 1.7% (ave.) longer than that of POPINS.
Finally, we compared PAR-POPINS with POPINS and RITUAL [115]. Table 2.7
shows the results of PAR-POPINS, POPINS, and RITUAL. In these experiments, the results of phases 1 and 2 of PAR-POPINS were used for the inputs of phases 2 and 3 of

PAR-POPINS, respectively. From Table 2.7, PAR-POPINS is 2.2 (ave.) and 3.3 (max.)
times faster than POPINS within 10.80/0 (ave.) degradation of the total wire length. For large
size data, PAR-POPINS is 2.1 (ave.) times faster than POPINS within 7.9% (ave.) degradation of the total wire length. Moreover, PAR-POPINS improved the total wire lengthby 9.3% (ave.) and 16.4% (max.) compared with RITUAL. As for computation time, PARPOPINS is 2.9 (ave.) times faster than RITUAL.

2.6

Concluding Remarks

In this chapter, a path-based timing-driven placement algorithm for standard cell layout, called

POPINS, has been proposed which is based on hierarchical partitioning and nonlinear pro-CHAPTER 2. TIMING-DRIVEN PLACEMENT

46

Table 2.7: The placement results of PAR-POPINS, POPINS, and RITUAL.
Data

MethodC5

C6
C7s15850s38417s38584
avq-small
avq-Iarge

POPINSRITUAL

o

0.83

0.17

22551201(1.00)

268321(- - -)

tNo results obtained.

gramming. POPINS can satisfy the timing requirement of the VLSI circuit by enforcing thepath delay timing constraints. The Elmore delay model is adopted since this is one of the mostaccurate models used in existing timing-driven placement algorithms. For further reduction of
the computation time of POPINS, we have developed a parallel version of POPINS, called

PAR-POPINS. Experimental results have shown that POPINS/ PAR-POPINS is more
effective than other existing timing-driven placement algorithms with respect to the interconnection delay model and its extendability.
Future work includes reduction of computation time of POPINS/ PAR-POPINS (particularly, that of phase 3), an extension of POPINS/ PAR-POPINS to handle a. routing
model with more than three layers, and development of a row assignment algorithm considering
global routes.
The current implementation of PAR-POPINS is intended for a shared-memory multiprocessor workstation. There are a number of issues to consider for implementation on different
parallel architectures, for example, a message-passing multi-processor and networks of workstations. Development of parallel placement algorithms for other type of parallel architectures
is also left as future work.

Chapter 3
A Timing-Driven Global Routing Algorithm for Standard
Cell Layout
This chapter discusses global routing for standard cell layout and proposes a timing-driven
global routing algorithm with the channel density minimization incorporated. The proposedrouter, called TV-QR, is based on a path-based algorithm and adopts the Elmore delay modelfor the interconnection delay calculation. Furthermore, it can minimize the channel density under given timing constraints. In the channel density minimization phase, we use 0-1 integer
linear programming. We also extend TV-QK~ to handle the layout model which allows the useof the over-the-cell region for routing. Through the simulation experiments, we show that TVQR algorithm gives better performance than the previously existing net-based timing-driven
algorithm [52].

3.1

Introduction

For standard cell layout, many global routing algorithms have been proposed [12,19,21,22,33,
46,82,83,90,93, 105, 111, 118, 128]. Although these algorithms are effective minimizing boththe channel density and the wire length, and can produce a good quality layout, unfortunately,
most of them do not take timing constraints into account. In Ref. [52], a global routing algorithm
for standard cell layout considering the interconnection delay has been proposed. Assuming thatthe timing constraint for each net is given as an upper bound of each net delay, this algorithm
solves the global routing problem to minimize the total channel density. However, the actual
timing constraints should be composed between the set of flip-flops(FFs) and the set of primary
inputs(PIs) or of primary outputs(POs). If we treat the timing constraints as constraints on nets,
then excessive delays in other nets may be created because of neglecting interactions amongnets. Moreover use of individual net bounds naay lead to overconstraining the problem, because
timing constraints are intrinsically path-oriented, while they must be divided into nets bounds.
Such an algorithm is a net-based one and it does not explicitly take the interconnection delay
between two registers into account. In routing one net, several Steiner tree construction algorithms have been proposed [9,24,50,85,99]. The objective is to minimize the interconnection
delay from the source to sinks of the net. The standard cell global routing has to explicitly con47

CHAPTER 3. TIMING-DRIVEN GLOBAL ROUTING

48

sider minimization of both the channel density and the interconnection delay between FFs andPIsIPOs. Hence we cannot directly use those algorithms in the standard cell global routing.
In this chapter, we first propose a timing-driven global routing algorithm for standard celllayout in two-layer routing model, in which only the channel region is allowed to be used forthe routing region. The proposed global router, called TV-on, can explicitly take the timing
constraints between FFs and PIslPOs into consideration and can minimize the channel region
under the given timing constraints. TV-on first determines an initial global route for each net,
and then improves initial global routes so that the timing constraints may be satisfied. With thetiming constraints maintained, Tv-gn further modifies the global routes so as to minirnize thechannel density. Finally, Tv-gn reassigns those nets incident to terminals on each cell row
to channels so as to minimize the channel density by means of 0-1 integer linear programming.
Experimental results show that Tv-gn is efficient and effective.
Next, we discuss the routing model in which routing is allowed not only in the channel
region but also the over-the-cell(OTC) region. OTC channel routing utilizing the OTe region
for routing has attracted considerable attention as we will address in Chapter 4. Since most of
conventional global routing algorithms assume that all nets have to be routed in the channels
only, minimization of the channel density does not always successfully lead to minimization of
the channel height. We, therefore, extend TV-on so that the OTC region may be incorporated
in the layout model.
The remainder of this chapter is organized as follows. Section 3.2 describes the interconnection delay model and the timing constraint, and formulates a timing-driven global routing
problem. In Section 3.3, we propose a timing-driven global router, called Tv-gn, and extend

Tv-gn to take OTC channel routing into consideration. Section 3.4 shows experimental results and the evaluation of Tv-gn. Finally, in Section 3.5, we summarize this chapter anddescribe future work.

3.2

Preliminaries

It is assumed that all cells have the same height and have equivalent terminals on both the top

and bottom sides of them. The cells have been placed in rows on the chip. The wiring of nets aredone using two layers; the first metallayer(Ml) and the second metallayer(M2). The M 1 layer ismainly used for horizontal wiring and the M2layer is mainly for vertical wiring. We defime a grid
graph G = (V, E) to be used in the algorithm as shown in Figure 3.1. Vertex v E V represents aterminal of each channel. A edge set E consists of two sets, E = Ev U E H, where Ev is a set ofvertical edges which represent equivalent terminals on both sides of cells and feedthroughs,
and E H is a set of horizontal edges which connect terminals of "each channel on the chip.

3.2. PRELIMINARIES49

Let e Hij represent a jth edge fromleft in ith channel and let E Hi
{eHij IVj} for all i=ell= 1,2"", q

where q is the total number of channels in the layout. The capacity ofedge ej E E v , denoted cap(ej), isequal to the number of wires thatcan pass through the corresponding
feedthroughs. Whereas, the capac-1

ity of edge e E E H is set to infinity.
For edge ej E E v , let d(ej) denotethe number of wires of global routes
that go through the feedthrough cor-horizontal edge e i in EH

vertical edge ej in Ey

vertexFigure 3.1: The grid graph G = (V, E).

responding to edge ej. For horizontal edge e E E H, let dee) represent
the number of wires of global routes that pass through the channel corresponding to edge e, andlet DHi denote the largest value of dee) in EH,i' i.e., DHi = max{ d(e)\e E EHi}'
Next, we define the delay model. We adopt the Elmore delay model as the interconnection
delay model. When a multi-terminal net ni is implemented by a Steiner tree, the interconnection
delay from the source to the load j for the net ni is given as follows.
delij(Wli, W2 i , Ll ij , L2ij ) = (Cl • Wl i + C2 . W2 i +L ClkJ(~O + Tl • Ll ij + T2 • L2ij ) (3.1)
kiwhere,

we, W2i:the total wire length of the Steiner tree for the net ni routed on Ml and M2,

respecti vel y.
Ll ij , L2ij : the path length from the source to a load j routed on Ml and M2, respectively.
Cl, C2: the capacitance of Ml and M2 per unit length, respectively.

Tl, T2: the resistance of Ml and M2 per unit length, respectively.

L:ki C lki: the sum of the load capacitance for the net ni·Ro: the equivalent output resistance of the source for the net ni.

Next, we define the timing constraint. "We specify a timing constraint as tr = (ST) er ,Delall owT ), where Sr is a source pin, er is a sink pin, and DelallowT is the maximum allowable de-lay from the source to the sink. The maximum allowable delay is given by users. For each timing
constraint tr E T, let CL r be a constrained circuit for tn in which a set of gateslFFs and nets
are on paths from Sr to ere Then a constrained circuit CL r can be shown by a directed acyclic
graph Gr = (vr, Er) (Fig. 3.2). Each vertex is corresponding to a gatelFF in the constrained

CHAPTER 3. TIMING-DRIVEN GLOBAL ROlJTING

50. . ., :path(a) a timing constraint t t(b) a constrained graph G tof t t

Figure 3.2: A timing constraint tT = (ST) eT) Del allow ...}.

circuit CLT and a directed edge (u, v), u, v E VT exists in ET when a gatelFF corresponding to
u is connected to a gatelFF corresponding to v. For each edge ej = (u, v) E ET, let n( ej) denotea net corresponding to the edge ej, and s(ej) and v(ej) represent source and load vertices on
the grid graph G corresponding to the vertices u, v E VT, respectively. Then the delay of edge
ej E ET can be defined as(3.2)
Let a constrained path for tT be any path whose source is ST and sink is eT on GT and let CPT
be a set of constrained paths for a timing constraint tT' The delay del(pT) of path p E CP n is
the sum of the delay of edges and vertices corresponding to gates on the path.
Now, we formulate the timing-driven global routing problem discussed in this chapter as follows. Given a cell placement, a set of nets, and a set of timing constraints 7 as inputs, the problem is to determine a Steiner tree Ti for each net ni, 1 ~ i ~ N, such that the timing constraints
and the capacity constraints are not violated, i.e., del(p) :s; Del allow .,-, Vp E CPT' Vt T E 7
and d(ej) ~ cap(ej)Vej E Ev. The objective function is to minimize the total channel height~1=1 D Hi ·3.3

TV-C)R: A New Timing-Driven Global Router

3.3.1

Overview of the Algorithm

The proposed Timing-Driven Global Router(7V-Qn) consists of four phases [66,117]. In phase
1, initial global routes are determined considering the minimization of the interconnection delayof each net. The interconnection delay of a net mainly depends on both the total interconnection
length and the path length from the source to loads of the net. Therefore 7V-Qn constructs atree considering the trade-off between the minimum spanning tree of the net and the shortest pathtree connecting the source and loads of the net. In phase 2, 7V-Qn first performs the timing

3.3. TV-Qn: A NEW TIMING-DRIVEN f;LOBAL ROUTER

51

verification and improve the global routes of nets which are on paths violating their timing
constraints so as to satisfy the timing constraints. Since all the paths satisfy the given timing
constraint after phase 2, phase 3 improve the global routes to minimize the channel density.
In this phase, the slacks of paths are first calculated, and based on the slack value, both the
maximum allowable delay and length for each net are calculated. Then the global routes are
improved to minimize the channel density within the maximum allowable length of each net.
Finally, in phase 4, a global route connecting two pins of a net in the same cell row is reassigned
either to the top or bottom channels adjacent to the cell row. The violation of the timing constraint
does not occur in this phase, because the length of the global route of a net will not change when
it is reassigned to either the top or the bottom channel. The objective of this phase is to minimize
the total channel density. The net assignment problem can be fonnulated as a 0-1 integer linear
programming problem. In the remainder of this section, we describe each phase of the proposed
algorithm in detail.

3.3.2

Initial Global Routing (Phas~e 1)

Phase 1 detennines initial global routes. First, we construct a complete graph GCi = (VCi, ECi)for each net ni, 1 ::; i ::; N (Fig.3.3(a)). Each vertex Vj E VCi represents a pair of the equivalentterminals. Each edge ejk E ECi has the weight corresponding to the Manhattan distance between
two vertices of the edge. We generate a global route for net ni by constructing a spanning tree
TCi on the complete graph GCi.

We assume that each net consists of one source Vo E VCi andsome number of loads Vj E VCi - {v o }. The interconnection delay from the source Vo to aload Vj mainly depends on both the total net length and the path length from the source Vo to
the load Vj. If we construct the minimum spanning tree, the total net length can be minimized.
However, the length from the source to a load may become long, and the interconnection delay
may be large. On the other hand, if we construct the shortest path tree, the path length fromthe source to all the loads can be minimized. However, the total net length may be long, andthe interconnection delay may also be large. Hence we adopt an algorithm proposed in [2],which combines the Prim's minimum spanning tree construction algorithm and the Dijkstra's
shortest path tree construction algorithm. In our tree construction algorithm, an edge which has
the largest weight is added to the tree one by one. The weight of an edge ejk E ECi is defined
as,
(3.3)
where K, denotes a parameter (0 ::; K ::; 1), Lk is the path length between the source Vo and theload Vb and ljk is the Manhattan distance of the edge ejk. If we set the parameter K to 1, thealgorithm can be regarded as the Dijkstra's shortest path tree construction algorithm. On theother hand, if we set K, to 0, the algorithm can be regarded as the Prim's minimum spanning tree

CHAPTER 3. TIMING-DRIVEN GLOBAL ROlJTING

52

a pair of equivalent terminals

source(a)complete graphspanning tree edge(b)

Steiner tree(c)grid graph G = (V, E)•(d)Figure 3.3: An example of phase 1.

construction algorithm.
After constructing the tree T Ci considering the trade-off of the minimum spanning tree andthe shortest path tree, we embed the tree TCi for net ni on the grid graph G taking the channel
density into account using the distance network heuristic algorithm of Steiner tree construction[76](Fig.3.3(d)). For the horizontal edge e E EHi of the grid graph, we define the cost c(e) as

dee)c(e) = DHi'

(3.4)

where d( e) represents the number of wires of the Steiner trees which pass through the horizontal
edge e, and D H i is the largest value of d( e) in E Hi. We embed a tree of each net based on
the tree TCi so as to minimize and uniform the channel density based on the edge cost c( e) byconstructing a minimum cost Steiner tree of each net. An example of the execution of phase 1
is shown in Figure 3.3.

3.3.3

Iterative Improvement Based on Wiring Delay (Phase 2)

In phase 2, the global routes are iteratively improved so as to satisfy the given timing constraints.
In order to effectively rip-up and reroute nets concerned with current timing violations, we define
the weight w(ej) of edge ej E ET for a timing constraint tT E T(Fig.3.2(b)). Let delc(ej) be
the current delay of the edge ej after phase 1. We define the lower bound delay dell(ej) of the3.3. TD-Qn: A NEW TIMING-DRIVEN (;LOBAL ROUTER

53

edge ej E ET asdell(ej) = (c· Wmin +L Clj)(Ro + r . Lmin) ,

(3.5)

j

where
W min : the net length of the minimum spanning tree of the net n(ej).
Lmin: the path length from the source s(ej) to the load v(ej) on the shortest path tree of the

net n(ej).
c, r: min(c}, C2) and min(r}, r2), respectively.

s, v pair which has the largest weightshortest path;- - I~I- -, -

lold '.............""""'-....IF--I-I
I I

r - '- --' -1
I~ - 1- -I -

IV

T -

r - ( -1- I_.1 - L _-r - '- "I., -- .J -I
I
I
T -,- r.1 -_I _ I
I
I-I - 1- L _1- I_ ~ _ 1__ 1__I _ ~ _ ~ -'IS(b) connect in the shortest path between

the source s and the load v
spanning tree edge;- -1- -1--'

1- - 1- -I --, - ., -rr - 1- _I -

-' -

1

1

-1- -1- -'I
I
L _1_ -IIr -'I _ ~ _

1

1

I

- L -1-1_ _ _ _ _ 1__I _ ~ _ ~ -'(c) remaining vertices are connected

I

L _1_ - I -

T -

r -

_.1 -

-I - 1-I - 1

I

1

I

r - 1- ___.........--i._.L..-.~
I_~-_ _ _ _ _ _ _ _ _ _ ~-'(d) embed the tree on the grid graphconsidering the congestion

Figure 3.4: An example of phase 2.

Let [nl(ej) be the influence of the edge ej which is the number of paths passing through theedge ej on GT [120]. Then the weight w(ej) of the edge ej is defined asw(ej)= [nl(ej) x (delc(ej) - dell(ej)).

(3.6)

From this definition of the edge weight, if the difference between the current delay and the lower
bound delay of an edge is large, and the number of paths passing through the edge is large, theedge has a large weight. Then, we rip-up the global route of the net n(ej) which has the largest
weight w(ej), and reroute the net n(ej) so as to minimize the delay from the source s(ej) to theload v(ej).
First, we reroute the net between the source s(ej) and the load v(ej) by the shortest path,and embed it on the grid graph G considering the channel density (Fig. 3.4(a,b)), where the costof the horizontal edge e E E H of the grid graph G is the s"a me as that used in phase 1. Next,

CHAPTER 3. TIMING-DRIVEN GLOBAL ROllTING

54

we construct the Steiner tree Tn(e-r:) connecting the remaining vertices of this net by using the)same algorithm of phase 1, and embed it on the grid graph G considering the channel density(Fig. 3.4(c,d)). This edge is locked during some number of improvement steps. We repeat these
operations until the given timing constraints are satisfied. By this procedure, the global route ofa net which tends to violate the timing constraint can be improved first.

3.3.4

Iterative Improvement Based on Channel Density (Phase 3)

Calculation of the Maximum Allowable Delay and Length of Net
In phase 2, the global routes have been improved so as to satisfy the timing constraints. In phase
3, the global routes are improved so as to minimize the channel density under the given timing
constraints. We first describe how we can reduce the channel density under the given timing
constraints. For example, in Figure 3.5(a), the delay time between two FFs is 15, because thedelay time of the lower path is 15, which is larger than that of the upper path. Since the timing
constraint between two FFs (Delall owr = 15) has already been satisfied until in phase 2, themaximum delay time between two flip-flops does not change even if we increase the delay timeof the upper path up to 15(Fig.3.5(b)). Therefore we can reroute and detour nets on the upper
path to improve the channel density. The difference of the maximum delay time of a path andthe actual delay time of the path is called slack of the path. Thus, in phase 3, we distribute theslack of each path to nets on a path to improve the channel density considering the global routeof each net.

increase of the delay

delay / arrival time / required time~54--... _-

allowable delay time = 15

delay time of top path
=1+2+1+5+1+4+1=15(a) before slack distribution(b) after slack distribution

Figure 3.5: An example of phase 3.

Let slack(ej) be the slack of edge ej E ET. First, we calculate slack(ej) for each edge
ej E ET, \ItT E T, and, for timing constraint tT E T, select the edge ej which has the non-zerosmallest slack value. Next we calculate the maximum allowable delay for the edge ej and selecta path p E CP n P : ei - t . . . - t ej - t . . . - t e'k on which the slack value of all the edges

3.3. TD-gn: A NEW TIMING-DRIVEN (;LOBAL ROUTER

55

are equal to slack(ej). Let slack(p) be the slack of the path p, i.e., slack(p) = slack(ej). Then
distribute slack(p) to the edges on the selected path p and determine the cost of all the edges on
the selected path p based on the channel congestion. The cost a( ej) of edge ej E ET is defined
as,
dee)
=
rnax
,
J
e EEH corresponding to ej D/(ej)

a(e~)

(3.7)

where D' (e) is the largest value of d( e) of edge e E E H on which the global route of Tn(e":) passes.
]

Since the case that the cost a(ej) is equal to 1 means that the global route Tn(ej) passes throughthe most congested edge on G, we should assign a larger slack value to this edge to detour thecongested region. We therefore distribute the slack value slack(p) to edges whose cost a(ej)is equal to 1. If the number of edges whose cost a(ej) = 1 is more than one, then slack(p) is
distributed to all the edges equally. If there is no edge with the cost a(ej) = 1, then slack(p) is
distributed to each edge ej according to the cost a(ej) (Fig. 3.5(b)). Since the distributed slack
can be considered as the maximum allowable delay of edge ej, the maximum allowable lengthof the global route Tn(e":)
is calculated based on the slack value by substituting it for equation
J(3.1). These operations are repeated until all the slacks of edges on GT, \;ft T E T, are equal to O.

Iterative Improvement of Global Routes
After the calculation of the maximum allowable length of each net, we improve the global routes
to minimize the channel density of each channel by rerouting nets within their maximum allowable lengths. For horizontal edge e E E H, we first calculate the edge cost c( e) which is definedin phase 1 (equation (3.4)). In order to improve the global routes so as to minimize the channel
density, we rip up routes of nets which passes the congested regions and reroute the nets withthe shortest paths within their maximum allowable length of the nets (Fig. 3.6). However, theconstrained shortest path problem is known to be an NP-hard [41], and there exists no algorithm solving the problem in a polynomial tirrle. Therefore we perform an exhaustive search tofind the constrained shortest path of each net. Restricting the searching region of a net within theminimum rectangle enclosing all the pins of the net as shown in Fig. 3.6(b), we can obtain theconstrained shortest path within a practical computation time. These rip-up and rerouting operations are performed for nets in the non-increasing order of the maximum allowable lengths ofnets until no more improvement can be achieved. During the iteration, we dynamically update
the maximum allowable lengths of nets. We show each step of the algorithm phase 3 as below.

[Phase 3:Iterative Improvement of Global ]Routes]
Step 3.1: Calculate slack(ej).
Step 3.2: Select edge (ej) that has the smallest slack value:-CHAPTER 3. TIMING-DRIVEN GLOBAL ROlJTING

56

constrained shortest path1- -11-~----I - I - I - T - r tl- I

1

I

I

I

,-11

I

I

I

I" - 11
I

I

I

I

I

- T-

- 1- t l - II(a) rip-up the net passing the congested
regions

I

- - t

I

I

I

I

I

I

- r tl- I

1- - 11
I

I

I
I
tl-I
I
I

~

I

I

I

1

-~ -...:- -~ -~ -:J - -search region(b) after determining the shortest pathwithin the maximum allowable length

Figure 3.6: Iterative improvement based on channel density.

Step 3.3: Select path p : ei ~ ... ~ ej ~ ... ~ e'k on which the slack value of all the edges
are equal to slack(ej).

Step 3.4: Calculate the cost c(e) of edge e E EH of the path p based on the channel density,and distribute the slack(ej) value to each edge based on this cost.

Step 3.5: Calculate the maximum allowable length for each edge based on the slack value distributed in Step 3.4.

Step 3.6: Improve the global route of the net to minimize the cost based on the channel density
within the calculated maximum allowable length.

Step 3.7: Update the slack value of each edge.
Step 3.8: If there is any path which has not been selected in Step 3.3, then go to Step 3.3.
Step 3.9: If all the slack values are equal to 0 or no more improvement can be achieved, terminate this procedure. Otherwise, go to Step 3.2.

3.3.5

Net Assignment with 0-1 ILP (Phase 4)

In the standard cell model which we assume in Chapter 3, each cell has equivalent terminals on
the top and bottom sides of the cell. A global route connecting to the terminals of a net in thesame cell row can be routed on the upper or lower channels adjacent to the cell row(Fig.3.7).
Such a routing segment connecting the two terminals is called a switchable routing slegment.
We also call a global route that is corresponding to the case in which the switchable routing
segment is flipped to the upper (resp. lower) channel, an upper (resp. lower) flipped routing

segment. Note that either the upper flipped routing segment or the lower flipped routing segment
is determined for the global route of the corresponding switchable routing segment after phase 3.
Since the length of a switchable routing segment will not change when it is assigned to either theupper or the lower channel adjacent to the cell row, violations of the timing constraints, which3.3. TV-QR: A NEW TIMING-DRIVEN (;LOBAL ROUTER

57++~r-----------~
a switchable routingI+r--____...a.-~_ _~_segment+,....-____...a.-....a.-_ _Ck+I J&..-_+
2+,....-~~--~----~+ ....._--'
J+,....-----~------(a) before reassignment(b) after reassignment

Figure 3.7: The net assignment.

have been satisfied in the previous phases, does not occur in this assignment. Therefore, in phase
4, we reassign all switchable routing segments for each cell row to either the upper or the lower
channels so as to minimize the total channel density. We formulate this net assignment problem
to a 0-1 integer linear programming problem. In the following, we formulate this multi-channel
assignment problem.
In the formulation, in order to reduce the number of constraints for calculating channel den-sities, we adopt the concept of zone used in channel routing algorithms [87,140]. By introducing
the zone representation, the constraints can be considered in each zone. Since, in general, thenumber of zones is fewer than the number of columns, we can reduce the number of constraints.
Let Dinitialk denote the initial channel density of the channel C k after phase 3. Let Dfina1k represent
the final channel density of the channel C k after the net assignment of the channel Ck. For aset of routing segments corresponding to global routes after phase 3, let den(Zj,k) be the channel
density of jth zone Zj,k of each channel C k after both flipped routing segments are added. In thefollowing, we call a flipped routing segment a switchable routing segment for simplicity. We
introduce two 0-1 variables Xi,k and Xi,k+l for each switchable routing segment i of the cell row
R k . If the switchable routing segment i of Rk is routed in channel C k then Xi,k

= 1, and if it is

not routed in C k then Xi,k = O. Similarly, Xi,k+l is defined. To model the overlapping between
two switchable routing segments i, j of the same net in C k shown in Fig.3.8(a), we introduce
new variables 0 Ii ,J',k = Xi ,k - l /\ XJ',k+l, 02i ,J',k = Xi "k-l /\ XJ' k - I, and, o3 i ,J',k = Xi ,k+l /\ XJ' ,k+l if weregard each variable as a Boolean variable. The integer linear programming formulations foro 1i ,j,b o2 i ,j,b and o3 i ,j,k are as follows.
ol i ,j,k::; 1,:Xi ,k - l +Xj,k+l -2 X ol i ,j ,k 2:: 0+ X j ,k - l - o2i ,j,k ::; 1,
Xi,k+l + Xj ,k+I - o3 i ,j ,k ::; 1,:1~i,k - I + X j,k - l -2 X o2 i ,j,k 2:: 0

X i ,k - I +Xj,k+l Xi,k - l

Xi ,k+ l+ Xj ,k+l" - 2 X o3 i ,j,k 2:: 0

CHAPTER 3. TIMING-DRIVEN GLOBAL ROUTING

58

case 1case 2

samenetcase 3(b) density is not reduced(a) overlapping cases 1, 2, and 3

Figure 3.8: Overlapping switchable segments of the same net.

The variables ol i ,j,b o2i ,j,b and o3 i ,j,k will be set to 1 if and only if both two routing segments
are not routed in C k . Because the density in a zone with two overlapping switchable routing
segments will be reduced by one if and only if both routing segments are routed other channels.
On the other hand, for the case in Fig.3.8(b), even if the switchable segment i is routed either
in C k or C k +1, the density of the zone is not reduced by one. Therefore, we do not consider
such a switchable segment i in the calculation of the density of the zone. Let OSWI b OSW2 b
and OSW3 k be sets of overlapping switchable segments for the cases o1 i ,j,k = 1, o2i ,j,k = 1,
and o3 i ,j,k = 1 of Fig 3.8(a). Let NSW k be a set of non-overlapping switchable segments in C brespectively.
Now, we show the 0-1 ILP problem formulation for the multi-channel net assignment problem as follows.

[The Multi-Channel Net Assignment Problem]qminimize : 2::= Dfuuzi kk=lsubject to :/ * Initial Density Constraints * /Dfinalk ~ Dinitialk 01k, 1 ~ k ~ q)

/ * Zone Equations * /Dfinalk +2::= Xi,k-l +iEZj,k/\iENSWk

3

2::=

Xi,k+liEzj,k/\iENSWk

+2::=
y=l

OYi,j,ki,jEZj,k/\i,jEOSWYk/ * Overlapping Segment Constraints * /ol i ,j,k ~ 1
Xi,k-l +Xj,k+l - 2 X ol i ,j,k 2: 0 01i,j E OSWl k ,Vk, 1 ~ k ~ q)Xi,k-l + X j,k-l - o2i ,j,k ~ 1
Xi,k-l + Xj,k+l -3.3. TV-gn: A NEW TIMING-DRIVEN (j~LOBAL ROUTER

59+ Xj,k-l - 2 X o2i ,j,k ~ 0 (Vi, j E= OSW2 k , Vk, 1 ::; k ::; q)Xi,k+l + Xj,k+l - o3 i ,j,k ::; 1Xi,k+l + Xj,k+l - 2 X o3 i ,j,k ~ 0 (Vi, j E OSW3 k , Vk, 1 ::; k ::; q)Xi,k-l/ * Net Incompatibility Constraints * /Xi,k + Xi,k+l = 1 (for all switchable segrtlent i of R k , Vk, 1 ::; k ::; q)/ * Variable Definitions * /o - 1 Integer Xi,k, ol i ,k, o2i ,k, o3 i ,k (for all switchable segment i in C k , Vk, 1 ::; k ::; q)The first set of constraints show that the final channel density D finalk after assigning the nets
does not exceed the initial channel density Dinitialk. By the second set of constraints, the' channel density minimization is directly considered. The third set of constraints represents the constraints for overlapping segments described above, and the fourth set of constraints represents
that the routing pattern for one net must be one. From the above formulation, we determine
the net assignment by solving this 0-1 integer linear programming problem. After solving the
net assignment problem with a mathematical programming package, we can obtain the net assignment for each channel and apply a conventional channel routing algorithm, for example
YACR2 [102], to finish detailed routing in each channel. In the current implementation of thealgorithm, we use the linear and integer programming program, Ip_solve2.0 [5].

3.3.6

Extension to the Over-the-Cell Channel Routing

In this subsection, we discuss the consideration of over-the-cell(aTC) channel routing in the

proposed algorithm Tv-gn. In detailed routing for the standard cell layout design, aTCchannel routing which utilizes the aTC region as the routing region, has been proposed [26].
In this design style, after determining net assignment to each channel in the global routing
step, track assignment both in channel and on aTC regions is performed by an aTC channel router [26,27,47,49]. However, conventional global routing algorithms do not assume aTCchannel routing but conventional channel routing, and therefore the minimization of channel
density in the global routing step does not always successfully lead to the minimization of the
final channel height.
For example of Fig. 3.9, if we determine net assignment for each channel to minimize thechannel density without considering the aTC region, then we obtain a set of global routes in Fig.
3.9(a). After this assignment, if we perform OTC channel routing that utilizes only one layer
on aTe region, then a routing result shown in Fig. 3.9(b) is obtained where the total channel
density is four. However, for the nets depicted bold lines, if we explicitly consider one layer
aTe routing region in global routing, we can reduce the toful channel density from four to two

CHAPTER 3. TIMING-DRIVEN GLOBAL ROU'TING

60(a) global routing results
without considering
over-the-cell region(b) over-the-cell routing
results after global
routing(c) global routing results
considering over-thecell region

Figure 3.9: Consideration of the-over-the-cell region in global routing.

by effectively utilizing the aTC routing region(Fig. 3.9(c)).
To apply TV-gn to the layout model which allows the use of the aTC region, we should
explicitly take the aTC regions into account during global routing. We therefore extend TV-

gn by adopting the idea of the algorithm which we have proposed in [64,65, 71]. In the algorithm of [64], during global routing, we perform the assignment of nets to be routed on theaTC, which is performed at the last step in conventional global routing algorithms. This algorithm consists of two phases. To minimize the total channel density, phase 1 determines a setof routes to be routed on aTC so as to maximize the utilization of the aTC, and then phase 2
constructs a set of Steiner tees to connect the remainder of pins for all the nets using the channel
regions so as to minimize the channel density (the brief description of the algorithm is describedin Appendix B). Therefore, in the extended algorithm, called TV-gn oTe after the constructionof global routes which satisfy the given the timing constraints, we perform the net assignment
to be routed on the aTC during global routing. Then we estimate the channel density of eachchannel based on the net assignment, and reroute nets so as to minimize the channel density. In
the following, we first define the cell model which is assumed in [64], and describe the outlineof the extended algorithm.
First, we define the standard cell model for aTC channel routing. We assume that t.he standard cell model is the Bottom Terminal Model(BTM) (the details of the BTM will be discussed
in Chapter 4). In the BTM, all the standard cells have the same height and they have equivalentterminals at the same x-coordinate of upper and lower sides of the cell(Fig. 3.10). In the routing
model shown in Fig. 3.10, we assume that the M1 and M2 are used for channel routing and theM2 is only used for the aTC connections. Since Vdd and Gnd buses are routed on the M2 inthe middle of a cell in advance, the aTC area for each cell is vertically divided into two partsby them in the middle of the cell and the number of available routing tracks, denoted t, on both

3.3. Tv-gn: A NEW TIMING-DRIVEN (j~LOBAL ROUTER

61

of the OTCs is given.
Since, in the above cell model, the routing on the OTCs is carried out on only one
layer(M2), we determine a set of routes so as
not to cross each other and to maximize the total weight of nets 1 to be routed on the OTCs.
We can solve this problem with the algorithm
based on dynamic programming which will bepresented in Section 4.3.6. Figure 3.11 shows
an example of the OTC routing. In this exam-

channel Cj
equivarent<fii-..;..t_+-;..;..........~-+-I
terminal} routingtracks , t
one-layer(M2)Figure 3.10:
model(BTM).

The

boundary

terminal

ple, nets which have terminals in the same cellrow is a set of candidates to be routed on the
OTC. For the candidate set, we apply the OTe routing algorithm to both the upper and lower
sides of the cell row and obtain a set of routes on the OTC for the cell row.
/net
~-

~

I

I
I

"---

----

(a) the candidates of the nets
to be routed on the OTeI~ III tftllkJll(b) applying the algorithm
to the lower cell side(c) applying the algorithm
to the upper cell side

Figure 3.11: An example of the OTC routing on the M2.

The Extended Algorithm: TV-9R oTc
Now, we propose TV-9R oTc . First, TV-gR.oTc finds global routes which satisfy the timing
constraints with phases 1 and 2 of TV-gR. Based on the global routes, Tv-gn oTc then determines a set of routes routed on the OTCs by applying the OTC routing algorithm based on
dynamic programming to each cell row. TV-9R oTc improves the global routes with phase 3of Tv-gn so as to minimize the total channel density which is determined by the set of nets
routed in the channels. Finally, TV-gR oTc optimizes the net assignment of channels with phase
4 of TV-gR. Figure 3.12 shows an example of the execution of the algorithm. The outline of

TV-9R oTc is as follows.
1The weight of a net is defined based on both the criticality and possibility ofthe reduction of the channel density"
for the net.

CHAPTER 3. TIMING-DRIVEN GLOBAL ROUTING

62(a) an initial global route which
satisfies the timing constraint(b) the corresponding routing topology(c) selection of the routes on the OTCs(d) the final routing results

Figure 3.12: An example of TV-9R oTc .

[Tv-9RaTc: The Timing-Driven Global Routing Algorithm for OTC Channel Routing]Phase 1 : Initial Global Routing: We determine initial global routes considering the minimization of the interconnection delay of each net with the tree construction algorithm
used in phase 1 of TV-gR.
Phase 2 : Iterative Improvement Based on Wiring Delay: First, we verify the timing constraints T.

If there exists a net on a path violating its timing constraint, we im-prove the global route of the net to satisfy the timing constraint with phase 2 of TVgR (Fig.3.12(a)). After this phase, all the timing constraints are satisfied.
Phase 3 : Selection of OTC Routes: Based on the global routes obtained in the above phases(Fig. 3. 12(b)), we select a set of candidates to be routed on the OTCs, and detennine theset of routes on the OTCs applying the algorithm which will be presented in Section 4.3.6
for each channel (Fig. 3.l2(c)).
Phase 4 : Iterative Improvement Based on Channel Density: After phase 3, we can know
the set of nets to be routed in the channels. First, we calculate the channel density of eachchannel. Next the slacks of paths are calculated, and based on the slack value, both the
maximum allowable delay and the maximum allowable length for each net are detennined.
Applying phase 3 of TV-QR, we improves the global routes so as to minimize the channel

3.4. EXPERIMENTAL STUDIES

63

density within the maximum allowable 1length of each net (Fig. 3. 12(d)).
Phase 5 : Net Assignment with 0-1 ILP: Finally, we improve the global routes by reassign theset of net segments routed in the channels either to the upper or lower channels adjacentto the cell row with phase 4 of TV-gR.

3.4

Experimental Studies

We have implemented TV-gR presented in Section 3.3 on a SPARC serverl000 (l35MIPS)
in C language. In Table 3.1, we show the experimental data. Data "fract" and "struct" arethe benchmark data distributed from MCNC. "c 1" rv "C7" are ISCAS benchmark data. In thistable, "#Const." is the number of timing constraints. As the timing constraint, we gave the clock
cycle for "C 1" rv "C7" and gave the values used in [63] for "fract" and "struct". We generated
cell placements with RITUAL [114] for "C2" and "C7", and with POPINS [63] for other data.
Detailed routing was done by two-layer channel router YACR2 [102]. For 0-1 ILP in phase 4,
we used the linear and integer programming program, Ip~0Ive2.0 [5].

Table 3.1: Benchmark data.

I Data I #Cells I #Nets I #Const. I #Rows I Const.(nsec) I
147
125
38
12
47.5
fract
1920
127
20
150.6
struct
1888
639
82
8
78.4
C1
607
270
590
963
9
37.7
C2
246
10
826
804
104.7
C3
334
1683
1560
13
73.4
C5
334
1561
14
72.6
1639
C6
2465
405
2150
18
67.4
C7
#Nets: Number of nets
#Cells :Number of cells,#Const.:Number of constraints #Rows: Number of cell rows
Const. :Timing constraint between two registers (nsec)

Table 3.2: Results of TV-gR.

I Data I LT I del(nsec) I L(JLm) I time(sec) I
34.3
137542
12.7
fract
91
142.0 1299014
479.6
struct 230
327414
61.7
163.3
C1
96
414862
238.4
115
35.3
C2
86.8
665773999.0
165
C336.9 1356640
2244.0272
C543.8 1237915
1083.5267
C6
63.6 1728857
5963.4
C7
337
del :MaJ(1mum delay(nsec)
LT:Number of tracks
L :Total net length(J1.m) time:Computation time(sec)CHAPTER 3. TIMING-DRIVEN GLOBAL ROI'lTING

64

Table 3.3: Comparison results with the conventional algorithm [52].

Tv-on
Data
C2
C7

"f.T

I del I time

115 I 35.3 I 238.4
337 I 63.6 I 5963.4

Conventional Algorithm
Timing Mode Density Mode
'LT
del
'LT
del
120
31.56 114
*39.83340 *89.32 325*94.73* : Tlmmg vIOlatIOn

Table 3.4: Results of each phase.
Phase 2Phase 3Phase 4Phase 1
Data
'LD
'LD
del
del
'LD
del 'LD
del95 34.3
91 34.3
fract
99 49.3 100 34.3
struct 246 152.7 245 142.0 238 142.0 230 142.0
C2
128 39.1 129 35.3 120 35.3 116 35.3
C7
371 91.9 365 63.6 345 63.6 337 63.6
'LD:Total channel density, del:Maxlmum delay(nsec)

Table 3.5: The CPU time of each phase(sec).

I Data "Phase 1 I Phase 2 I Phase 3 I Phase 4 I
fract
struct
C2
C7

0.5
3.2
1.3
4.5

2.4
85.9
36.4
122.2

7.6
228.8
155.4
5673.0

2.2
161.7
45.3
163.7

We compared Tv-gn with the conventional algorithm presented in [52]. In Tables 3.2 and
3.3, we show the experimental results of Tv-gn and the comparison with the conventionalalgorithm, respectively. The results of the conventional algorithm are quoted from [52], in which
the results for data "C2" and "C7" only have been reported. The evaluation of the delay is doneby the delay equation described in [52]. From Table 3.3, we can see that Tv-gn produces
good routing results with the smaller number of tracks, satisfying the given timing constraints.
In particular, the wiring delay of data C7 was reduced by 28.9%. We can also reduce the total
number of routing tracks by 2.5%(ave.) and 4.2%(max.) without timing violation comparedto the conventional algorithm [52]. The simulation results shown here have demonstrated thatTv-gn is quite promising.
Finally, in Tables 3.4 and 3.5, we show the results of each phase concerning with the number of tracks, the wiring delay, and the CPU time. From these results, Tv-gn can generate
the global routes which satisfy the given timing constraints until in phase 2. Furthemlore, we
can obtain further reduction of the routing tracks in phase 3 under satisfying the given timing
constraints.

3.5. CONCLUDING REMARKS65

We may conclude that TV-on is efficient and effective in regard to both the interconnection
delay and the minimization of the routing tracks.

3.5

Concluding Remarks

In this chapter, a path-based timing-driven global router(TV-On) for standard cell layout has
been proposed which minimizes channel density. TV-on has two features in comparison withthe conventional algorithm [52]. First, Tv-gn can explicitly consider the timing constraint
between two pins while the conventional algorithm considers the timing constraint for a net.
Second, it is able to explicitly minimize the channel density under the given timing constraints.
We have also extended TV-on to utilize over-the-cell channel routing. Experimental results
have shown that TV-on is effective for the minimization of the routing tracks under the given
timing constraints. Moreover, we can reduce the total number of routing tracks without timing
violation as compared with the conventional algorithm. Therefore we may claim that TV-on isefficient and effective in comparison with the conventional algorithm [52].
Future work includes a reduction of the computation time of TV-on (particularly, that ofphase 3) and an extension of TV-on to treat a multi-layer routing model. An extension of

TV-on to handle other standard cell models which we will discuss in the next chapter is also
an interesting topic.

Chapter 4Over-the-Cell Channel Routing Algorithms for Standard Cell
LayoutThis chapter discusses the detailed routing problem for the standard cell layout utilizing the overthe-cell(OTC) areas, that is, the over-the-cell channel routing problem. First, two new standard
cell models are proposed. Since the conventional cell models were originally developed not for
OTC channel routing but rather for conventional channel routing, they are not always suitable for
OTC channel routing. The proposed cell models, on the other hand, are developed specificallyfor OTC channel routing. Hence the OTC area as well as the intra-cell area can be effectively
utilized so as to minimize the channel density., Next, for these proposed standard cell models,
OTC channel routing algorithms which can utilize the cell models efficiently are proposed. For
the first model, we propose a single-channel routing algorithm, called 3DR-BTM-N, which
performs both planar and H -V routings taking the OTC routing capacity for each channel into
account. A multi-channel three-layer OTC routing algorithm(3DR-ATM-O) is proposed forthe second one which simultaneously handles all channels. A detailed routing problem undertiming constraints is also discussed for the second cell model. Finally, the effectiveness of 3DR-

BTM-N and 3DR-ATM-O is demonstrated in simulation experiments.

4.1

Introduction

In the standard cell layout design, the channel routing problem is an important problem and it
has been studied extensively. In fact, many two-layer and three-layer channel routers produce
solutions only one or two tracks beyond the optimum for most channels [112]. Accordingly,
further improvement in the layout area seems to be impossible if routing would be done only inchannels. For this reason, several researchers have suggested use of area "outside" the channel,
that is, area over the cell, to obtain further reduction in the channel height. This routing styleis referred to as over-the-cell (OTC, for short) channel routing. The OTC channel routing has
become possible due to the progress of semiconductor technology, which makes it possible touse the second (M2) and third (M3) metal layers for routing. Since the conventional channelrouting problem is known to be NP-hard [119]., and since the OTC channel routing problem is a
generalization of the conventional channel routing problem, 1t is easy to see that the OTC channel

67CHAPTER 4. OVER-THE-CELL ROUTING

68

routing problem is also NP-hard [26]. Therefore several heuristic OTC routing algorithms forseveral cell models have been proposed to obtain further reduction in the channel height [3,8,26,38,56,57,87,88,121,132].
In general, the cell models can be classified into four classes according to the terminal location. Based on the terminal location, four classes of cell models have been proposed: theBoundary Terminal Model (BTM) [27], the Center Terminal Model (CTM) [137], the ~v1iddle
Terminal Model (MTM) [7] and the Target Based Cells (TEC) [6]. Figure 4.1 illustrates thefour cell models and Table 4.1 shows characteristics and examples of OTC routing algorithms
for these cell models.
Table 4.1: Characteristics of cell models.

..

cell boundary

ceLLbou~~I
I: Vdd(M2)
GM(M2)=======================i/•terminal• • M2) ~ •• • • ••• •feedthrough( M2)
Vdd(Ml)

••
•• ••

••

(a) Bottom Terminal Model(BTM)(c) Middle Terminal Model(MTM)

ceLlbou~

cellbou~/

feedthrough( M2)
Vdd(Ml)• • • ••• • • • • •terminal M2)Jf

GM(Ml)(b) Center Terminal Model(CTM)~.Ijl)~1 I
terminal/GM(Ml)

feedthrough(M2)
Vdd(Ml)IE II
GM(MJ)(d) Target-Based Cell Model(TBC)

Figure 4.1: Conventional cell models.

The BTM is the most typical cell model and the BTM-based cell libraries have been used
extensively in the industry, and hence many researchers have studied OTC channel routing forthis cell models [20,26,27,47,48,86,87, 137]. Due to the limited use of the M2 and M3 layers
for intra-cell routing and the ease of handling the aTC routing problem, all of the conventionalrouters for the BTM assume that the number of available routing tracks on aTC does not dependon the column and it is always uniform. However, in a practical case:' there may exist sorne OTC

4.1. INTRODUCTION

69

regions which are actually routable but regarded as forbidden routing regions of OTC of theconventional BTM. Therefore, if we can utilize the OTC regions that the conventional routers
do not take into account, we can further reduce the channel height. In this case, the number ofavailable routing tracks on OTC varies column by column and it is not always uniform.
On the other hand, in most cell models exoept the TBC, terminals on the M2 layer of a cellrow need to be assigned in line either at the boundary or the center of the cell row. Then, an extra
routing region on the Mllayer is generally needed to align terminals. This extra routing region
hinders the minimization of the chip area. However, by allowing to use a part of the M2 layer aswell as the M 1 layer for intra-cell routing, we can reduce unnecessary routing regions. Note that,in the TBC, no part of the M2 layer is allowed to be used for intra-cell routing. Since the intracell routing with two metal layers have become possible due to the progress of semiconductor
technology [51, 112, 113, 121], in order to reduce the cell size, a part of the M2 layer as well as
the polysilicon and the M1layers should be used for intra-cell routing.
In this chapter, we propose two cell models for OTC channel routing. The one is an extension of the conventional BTM, in which the number of available tracks on the M2 layer of thecell model varies column by column. We call this model the Boundary Terminal Model with

Nonuniform aTe routing capacity (BTM-N). Since, in the BTM-N, we can utilize the OTC regions which the conventional BTM routers regard as forbidden regions, we can further reducethe channel height with the BTM-N. We can also use the same cell library for the conventional
BTM as the BTM -N without any additional design cost. The other has terminals placed on theM2 layer of a cell arbitrary, and allows the intra-cell routing on a part of the M2 layer of acell. We call this model the Arbitrary Terminal Model with Obstacles on arbitrary positions(ATM-O). Since, in the conventional cell models, in order to easily handle the routing problem,
terminals are aligned, the extra routing regions on the M 1 layer is needed to align terminal withintra-cell routing. On the other hand, in the ATM-O, terminals are placed arbitrarily on the M2
layer of a cell, no extra routing regions on the M 1 layer is needed like conventional models.
Therefore we can design cells of ATM -0 much easier than the conventional one and the widthand height of cells can be further reduced. Moreover the ATM-O is suitable for the multi-layer
routing. Unlike the BTM-N, cell libraries developed for the conventional cell models are notreused for the ATM-O. However, if we will newly design the cells, the ATM-O is the mostflexible and the smallest.
Conventional routing algorithms are developed for the cell models, in which the OTC routing
capacity is uniform and terminals are aligned either at the boundary or the center of the M2
layer. Since they cannot be applied effectively to our new cell models, we propose new threelayer OTC routing algorithms. For the BTM-Nr, we propose an algorithm which performs bothplanar and H-V routings taking nonuniformity of the OTC routing capacities into consideration

CHAPTER 4. OVER-THE-CELL ROllTING

70

and develop an optimal algorithm based on dynamic programming for the problem of selecting
planar routable nets on OTe for each channel. We called this algorithm 3VR-BTM·- N. A
multi-channel three-layer OTe routing algorithm, called 3VR-ATM-0, is proposed for the
ATM-O which simultaneously processes all the channels. Since the routing topology of each
net is determined so as to satisfy the timing constraints in both placement and global routing,if the routing topologies are not extremely changed, the timing constraints are usually satisfied.
However, in the multi-channel routing for the ATM-O, we may change the routing topologies
and, therefore, take the timing constraints into account. We discuss treatment of the timing
constraints in 3VR-ATM -0.
The remainder of this chapter is organized as follows. Section 4.2 presents two new cell
models for standard cell layout. In Sections 4.3 and 4.4, we propose 3VR-BTM -N and 3VR-

ATM-O for the proposed cell models, respectively, and for the ATM-O, we also discuss treatment of timing constraints in 3VR-ATM-0. Section 4.5 shows experimental results and theevaluation of the proposed algorithms. Finally, in Section 4.6, we summarize this chapter anddescribe future work.

4.2 New Cell Models for Over-the-Cell Routing
It is assumed that three metallayers(M1, M2, and, M3) are available for routing. M1 and M3
are used for horizontal wiring and M2 is used for vertical wiring. For each layer, there is a gridsuperimposed over the routing region. Wires will run along grid lines in rectilinear fashion. The
connection of the same net between adjacent layers can be realized by using vias that can beinserted at any grid point. A column and a track also represent a vertical and a horizontal lines
on a grid, respectively. In the following, we propose the new cell models, respectively.

4.2.1

The Boundary Terminal Model with Nonuniform OTC Routing Capacity

In the conventional BTM as shown in Fig. 4.2(a), terminals are located on the boundary of a cell and equi-potential terminals are on the same vertical column. The OTe regions of M2 of a cell row are divided into three regions, that is, the upper and lower routableregions and the middle forbidden routing region shown in Fig.

4.2(b).

In general, thepower/ground buses(Vdd/Gnd) of M2 and some intra-cell routing patterns of M2 exist in thethe middle forbidden routing region. A number of algorithms have been proposed for the
BTM [20,26,27,47,48,86,87, 137]. In all of the conventional algorithms for the BTM, inorder to make the OTe routing problem simple and easy to handle, they considered the BTM
as the cell model shown in Fig.4.2(b) and assume that the number of available routing tracks on

4.2. NEW CELL MODELS FOR OVER-THE-CELL ROUTING
A

~

71

intra-cell wirings of M2

VI. •

- -

- Vdd Bus(M2')• • .'-Gnd
Bus(M2)••(a) The boundary terminal cell model=========-===

over-the-cell)g7,"Ulin "gio",
forbidden
routing regions(c) BTM with non-uniform aTe routing capacity (BMT-N)
over-the-cellrouting regions
forbidden
routing regions
over-the-cellrouting regions• terminals•

forbidden routing regions•

Metal 2(intra-cell routing patterns and VddlGnd)(b) BTM with uniform aTe routing capacity (BMT-U)

Figure 4.2: The boundary terminal model(BTM).

OTe does not depend on the column but it is always uniform, even if there actually exists the
OTe routab1e region in the forbidden routing region. However, in a practical case, there may
exist some OTe routable regions in forbidden routing regions of OTe, in which M2 are notused for intra-cell routing (Fig. 4.2(a)). Therefore, if we can utilize the OTe routable regions
in some forbidden regions that the conventional routers do not consider for simplicity, we canreduce the height of channels further. In this case, the number of available routing tracks on
OTe varies column by column and it is not always uniform, that is, non-uniform(Fig.4.2(c)).
We therefore consider the BTM as the cell model in which the OTe routable regions is definedby the contour formed by obstacles as shown in Fig.4.2(c) and call it the BTM with non-uniform
routing capacity (BTM-N) [67,74]. In the foillowing, if we need to distinguish the BTM withuniform routing capacity and the BTM with non-uniform routing capacity, we call the BTM
with uniform and non-uniform routing capacities BTM-U(Fig.4.2(b)) and BTM-N(Fig.4.2(c)),
respecti vel y.

4.2.2

The Arbitrary Terminal Model with Obstacles on Arbitrary Positions

In the conventional cell models, terminals are aligned either at the boundary or at the center ofa cell row, and an intra-cell routing region on JM 1 layer is needed as an extra routing region toalign terminals. To eliminate this extra routing region, we propose a new cell model shown in
Fig.4.3.
Only po1ysilicon and M 1 layers have been usually used for intra-cell routing in the conventional cell models. However, with the progress: of semiconductor technology, intra-cell routing
with two metal layers has been available [51,112,113, 121]:'For example, in Ref. [51], Hsieh et

CHAPTER 4. OVER-THE-CELL ROUTING

72

cell boundary

j/feedthrough(M2)[.1. ~ .111~1.. I::::~•_ terminal(M2)obstacle( intra-cell routing in M2)

It
H.. III --:~ii#if- cellrow Jr"j+l

~~ !

..
~

~

~

cell
row rjo via (M2-M3 )' feedthrough(M2)-(a) Proposed cell model•twiring(M2)-wiring (M3)(b) OTe routing on M2 and M3layers

Figure 4.3: The ATM-O and associated OTC routes.

al. have presented two-metal CMOS leaf cells and an automatic layout generator and produced
compact layout compared with a conventional one-metal CMOS cells. Therefore, in order toreduce the chip area further, we propose the new cell model in which some parts of M2 layer
may be allowed to be used for intra-cell routing as well as polysilicon and M 1 layers. We
call this cell model the Arbitrary Terminal Model with Obstacles on arbitrary positions (ATM0) [68,126]. In this model, a routing pattern for intra-cell routing on M2layer is represented bya rectilinear polygon and such rectilinear polygons are regarded as obstacles when OTC routing
is performed. Thus obstacles may exist on M2 layer on arbitrary positions of OTC regions. Figure 4.3(b) shows an example of OTC routing for the new cell model. Note that, in this example,
we do not show intra-cell wiring but only the wiring for OTC routing.
In the ATM-O, terminals can be basically placed arbitrarily on M2layer of a cell. We assume
that there exists at most one terminal for each column and a terminal can be routed vertilcally byusing the column in which no obstacles exist from the terminal position to at least one side ofboundaries of the cell. Vdd/Gnd buses are placed on the boundary of Mllayer in a cell. Since
three metal layers are available for routing in our routing model, three-layer H-V-H routing isassumed for a channel region and two-layer V-H routing with M2 and M3layers is assumed for
the OTC region. It is also assumed that vias are available on the OTC region, and feedthroughs
are placed in M2Iayer(Fig.4.3(b)).
In the BTM-N, Vdd/Gnd buses are placed in the middle of cell rows on M2layer, and hencenets cannot cross M2layer on OTCs and cannot be routed in the adjacent cell rows. On the other
hand, in the ATM-O, there are no Vdd/Gnd buses at the middle of cell rows, nets can be routed in
the adjacent cell rows by crossing OTC regions. Therefore the ATM-O has much degree of the
OTC routability than the BTM-N. In this property of the ATM-O, in order to utilize OTCs of theadjacent cell rows, we propose a multi-channel routing algorithm which takes all the channels
simultaneously into account.

4.3. THREE-LAYER OVER-THE-CELL ROUTING FOR THE BTM-N

73

4.3

Three-Layer Over-the-C(~ll Routing for the BTM-N

4.3.1

Problem Formulation

In this subsection, we define some terminologies. Given a channel, let L be the length of thechannel, and N= {ni I i = 1, 2, ... ,N} be a set of nets to be routed. A set of terminals

on the top (resp. bottom) of the channel is denoted by Top = {tl, t2,"', t L } (resp. Bot ={b 1 , b2 , ••• , bL }). A number between 0 and N is assigned to each terminal. Terminals with thesame number i (l ::; i ::; N) must be connected by the net ni, while those with the number 0
designate unconnected terminals, that is, vacant terminals. Given a channel and a set of nets N,
we can order terminals of ni in the channel by their x-coordinate positions. A pair of terminals
with different x-coordinates, Pij, Pik E ni, defines a net segment segl = (Pij, Pik), segl E S of
the net ni and let net(segl) be the net number of segl. Let l(segl) and r(segl) be the column
numbers of the left and right terminals of segl E S, respectively and l(segl) =I r(segl). Let thelength of segl, denoted len(segl), be the horizontal distance between the left and right terminals
of segl, i.e., len(segl) = r(segl) - l(segl) > O. We assume that the available tracks, which are
horizontal grid lines for routing on OTe are nUlmbered from 1 to k from the cell boundary to thecenter of the cell row. In the following, we call a net segment NS for short.
In the BTM-N, the number of available
tracks, that is, the OTe routing capacity, isdifferent in each column, and therefore we define the M2 OTe routing capacity of the top(resp. bottom) cell row in a column x, denoted cap2t(x) (resp. cap2b(x)), as the maximum available track number in the column

x. The M3 routing capacity on the OTe of
the top (resp. bottom) cell row in a column x
is defined as cap3t(x) (resp. cap3b(x)). Notethat since there exists no obstacle in M3 ini-

c=J

over-the-ceLL region (M2)c:=Jobstacles (M2)

Figure 4.4: Over-the-cell region on the second
layer.

tially, cap3s(l)= cap3s(2) =,"', = cap3s(L)(s= t, b). Let cap2tmax (resp. cap2bmax) be themaximum M2 routing capacity of the top (resp. bottom) cell row, and it is defined as cap2tmax=
maxl~x~Lcap2t(x)(resp. cap2bmax= maxl~x~Lcap2b(x)). Similarly, the minimum M2 rout-ing capacity of the top (resp. bottom) cell row is defined as cap2tmin= minl<x<Lcap2t(x) (resp.
cap2bmin= minl ~ x~Lcap2b(x)). Let track(segl) denote a track number to which segl is assigned,

and track(segl) = 0 means that segl is not routed on OTe. Figure 4.4 shows the relation of OTerouting capacities on M2.

CHAPTER 4. OVER-THE-CELL ROUTING

74

Finally, the local density at a column x, denoted d(x), is equal to the number of nets whichhave not been routed on OTe yet and cross the column x, that is,d(x)= I{net(segl) I (l(segz) ::; x ::; r(segz»
1\ (track(segz) = 0) 1\ (net(segz) E N )}I.

(4.1)

Then let the channel density, denoted D, be the maximum local density among all the columns,
I.e.,

(4.2)
In this section, like the conventional approach [26], the OTe channel routing problem isdivided into three problems, that is, (1) the aTe routing, (2) the channel net segment selection,and (3) the channel routing problems. For the problem of the channel net segment selection,

we apply the similar algorithm proposed in [26]. For the channel routing problem, we apply aconventional three-layer channel router, for example [13]. In the following, we only discuss the
OTe routing.
Now we formulate the OTe routing problem as follows. Given sets of terminals of the top
and bottom sides of a channel, Top, Bot, a netlist N, and OTe routing capacities at all thecolumns of both the cell rows, cap2t(X) , cap2b(x), cap3t(x), cap3b(x) ( 1 ::; x ::; L ), theOTe routing problem for the BTM-N is to determine OTe routing patterns so as to minimize
the channel density D under the design rules and routing constraints.

4.3.2

Overview of the Routing Algorithm 3VR-BTM-N

In this subsection, we present an overview of a new OTe routing algorithm for the BTM-N,
called 3VR-BTM-N, [67,74]. The algorithm consists of five steps and performs planar routing
for the OTe regions near the channel and H- V routing for the OTe regions far from the channel.
In step 1, we assume that M2 routing capacity, which is actually non-uniform, is equal to M3
routing capacity, and select a set of planar routable NSs on M2 by applying the algorithm basedon dynamic programming(for short DP) [26] to both the cell rows. Because of the non-uniform
routing capacity of M2, some NSs cannot be actually routed on M2. Therefore, in step 2, someparts of routes routed at tracks track(segz) > cap2s(x)(S = t, b) are assigned to M3 by introducing
vias. Step 3 selects H-V routable NSs on M2 and M3 which do not cross the NSs routed on M2
in step 1, and performs H-V routing on the OTe regions far from the channel. In step 4, we
determine planar routable NSs on M3 with a new optimal algorithm to the problem of selecting
a set of planar routable nets with maximum weight for non-uniform routing capacity. Finally, instep 5, we apply the same procedure of step 3 and determine H-V routable NSs on the unrouted
OTe regions. In the following, we describe the details of each step:'

4.3. THREE-LAYER OVER-THE-CELL ROUTING FOR THE BTM-N

4.3.3

75

Determination of Planar Routable Net Segments on M2 (Step 1)

In step I, a set of planar routable NSs on M2 for both the cell rows are detennined. We temporarily assume that cap2s(x)= cap3s(x)(S = t, b) and then obtain a set of the maximum weighted
planar routable NSs applying the DP [26] for uniform routing capacity. Since the algorithm DP
presented in [26] can handle only a set of two-terminal nets, a set of multi-terminal nets need to
be decomposed to a set of two-terminal nets (net segments). In 3VR-BTM-N, a decomposition method similar to the method presented in [26] is applied. The details of the decomposition
method is described in Appendix C.I.I.
Next, the weight ofNS used in the DP is defined as follows. Let Count(segl) be the numberof columns in [l(segl), r(segl)] whose local density is equal to the channel density D, that is,Count(segz)= I{ x I (d(x) = jD) 1\ (l(segl) ~ x ~ r(segl) )}I.

(4.3)

This means the degree of the contribution to the channel density D for segz. The weight WI (segl)of segz defined as
WI (segz)= al x Count(segz) + (31 x len(segz),(4.4)

where at and {3I denote positive constants and al > > (31 so as to select nets which pass throughmany congested columns as much as possible I. From the definition of weight, as segl passes
through more congested columns in the channel and has a longer length, the weight WI (segl) isbigger. Hence we can expect for minimizing the channel density by selecting a set of NSs withthe maximum total weight.
In step 1, we first decompose the set of multi-terminal nets and obtain a set of NSs, denoted
as S. Next we apply the DP twice for the top and bottom cell rows in different order, and selecta set of planar routable NSs for each cell row S2s(S = t, b) which has a smaller channel density,or the same channel density and a larger total weight. Next, we route the NSs in S2s which canbe actually routed on M2 under the capacities cap2s(x).

5t---L-i I
1--....:1_1---41(a) before Step J

I

I 7

8
110
I ~

(b) after Step J

Figure 4.5: Step 1: Planar routing on the second layer.

IWe learned from experiments that 10.0 for a1 and 0 . 1 for {31 work "well.

ICHAPTER 4. OVER-THE-CELL ROUTING76

For example in Fig.4.5(a), cap2tmin = 2, N = {nt, n2, n3,"', n14}, and S = {seg}, seg2,

seg3, ... , segI4}. The numbers associated with the NSs indicate the net numbers. For easily
understanding, it is assumed that all the nets are two-terminal nets and the bottom cell row isomitted. Figure 4.5(b) shows the result of step 1.

4.3.4

Layer Reassignment and Planar Routing on M2 (Step 2)

All the NSs in S2sCS = t, b) determined in step 1 may not always be routed on M2 because

the M2 routing capacity is not uniform. For example in Fig.4.5(b), seg3 and segll cannot beplanar routable on M2. Hence in step 2, some parts of wirings routed at track track(segz) >cap2s(x)(S = t, b) are assigned to M3 by introducing vias. If the number of H-V routable NSs
can be increased by reassigning some NSs in S2s to M3, the NSs should be reassigned to M3.
Let Scross(segz) be a set of NSs which cross segl E S2s and which are H-V routable on OTC byreassigning segz to M3. The weight of Scross(segz) is defined as(4.5)
If WI (segl) < WI (Scross(segz)), then segz is reassigned to M3. Figure 4.6 shows the result of

step 2 where segI2 is reassigned to M3 to make H-V routing of seglO possible.
After the reassignment to M3, we determine the planar routable NSs on M2 once again by
applying the DP to the NSs in S - S3s which have not been reassigned to M3 yet. In orderto route many NSs on the OTe, we decompose segz E S - S2s into a set of NSs by using
vacant terminals. This NS decomposition is performed by linear assignment. The detallls of thedecomposition method in step 2 is described in Appendix C.l .2.
After the decomposition, we apply the DP
to the new set of NSs and perform the planar
routing on M2 once again. For the NSs thatwere not planar routed, we cancel their decomposition and perform the following steps

5~ I..---....:.1_1---II

I

I 7

8

I/O

I ~

I

3 rv 5 to this new set of NSs. In the following,
this new set of NSs is simply called the set of

Figure 4.6: Step 2: Layer reassigmment.

NSs.

4.3.5

OTe H-V Routing (Step 3)

In step 3, we select the H-V routable NSs on the OTC and perform H-V routing by inserting vias
on the OTC far from the channel, i.e., at track T ~ cap2smin (s = t, b). After steps 1 and 2, we
obtain the planar routable NSs on the top and bottom OTCs. For multi-terminal nets, we obtain aset of hyper-terminals that are maximal sets of terminals which are connected by wirings on the4.3. THREE-LAYER OVER-THE-CELL ROUTING FOR THE BTM-N

77

OTCs. The tenninals in each set of hyper-tenninals are connected together by OTC connections.
Therefore we need to choose net segments to connect all sets of hyper-tenninals of each net. We
use a heuristic algorithm presented in [26] to select net segments. In the following, let S' be theset of NSs after applying the selection algorithrn in [26]. We also decompose each net segments
in S' to a set of net segments like steps 1 and 2. Let S: and S~ be sets of NSs decomposed by adecomposition method using vacant tenninals on the top and bottom cell rows, respectively. The
details of the decomposition method in step 3 is presented in Appendix C.l.3. In the following,
we call the decomposed NSs NSs for simplicity.
Now we define horizontal constraint graphs(HCGs). Let MTs(segl) (s = t, b) be the maxi-

mum available track for segl to perform H-V routing on M2 and M3, that is,MTs(segz)= min{ cap2s(l(segl)), cap2s(r(segz))}.

(4.6)

Let Soverlap(Ys) be a set of NSs which overlap NSs routed on the track Ys of M3 of the OTC
in step 2. We define the Horizontal Constraint Graphs (HCGs) for a track Ys to be directed
weighted graphs Gs(Ys) =(Ys(Ys), Es(Ys)), (s = t, b). Set Ys(Ys) corresponds to the union of
the set of NSs routed at the track Ys in step 2 and the set ofNSs for which H-V routing can be
performed on the track Ys without overlapping the pre-routed NSs in S3t U S3b, i.e.,= {segl I (track(segl) = Ys 1\ segz E S3t U S3b)

Ys(Ys)(MTs(segl)

V

2: jr: 1\ segz E S~ - Soverlap(Ys))}.

(4.7)

A directed edge (Vl, Vj), Vl, Vj E Ys(Ys) is in l~sCYs) if and only if a pair of NSs, segz, segj E
S~ - Soverlap(Ys), satisfies that r(segz) < l(segj) or r(segl)= l(segj) 1\ net(segl) = net(segj),

where Vz, Vj E Ys(Ys) are vertices corresponding to segl and segj, respectively. Figure 4.7 shows
an example of the "horizontal constraint graph for a track. The weight w2(l, Ys) of vertex Vz att--~,_I----fl

5t---L-i 1
I

17

8
110
1~

I

Figure 4.7: An example of the horizontal constraint graph Gt(T;Jtrack Ys is defined as=(}:2 X+{2 X

1
7:)2 SLK (7:)2 1
t segl, s +b segl, s +Count(segl) + f32 >( SLK (1len(segl),(s = t, b),(4.8)

CHAPTER 4. OVER-THE-CELL R01JTING

78

where Q'2, f32, and'2 denote positive constants and SLKs(segl, Ts) = MTs(segl) - Ts. The firstterm represents the degree of the reduction of the channel density for segl and the second term
represents the possibility for segl to be routed at the track Ts. In order to select nets which has
much possibility of the reduction of the channel density, we set Q'2 ~ f32 ~ ,2 2. For exam-t----------2

4

4

4

------ 333

Tt••• % •• •
seg]
seg21

I

obstacles on M2•

tenninals

SLKlsegj. Tt} = 2 - 2 = 0

J

segl

1

(a)

•

SLKlseg2. Tt } = 3 - 2 = j

-~

1-1

(b)

(c)

Figure 4.8: The second term in equation (4.8) represents the possibility for segz to be routed at
the track Ts.

pIe in Fig. 4.8, if the current processing track is 7; = 2, then SLKt(segl, 7;) = 2 -- 2 = 0
and SLKt (seg2, 7;) = 3 - 2 = 1. If we route seg2 on track 2 without considering segl, thenseg} cannot be routed on tracks which are processed after track 2 any more (Fig.4.8(b)). However, considering SLKt(segi, 7;) values, we can route both the NSs on the OTC(Fig.4.8(c)). Let

LPs(Ts) be the longest path on Gs(Ts) and W 2(LPs(Ts)) be the sum of the weight w2(l, Ts) ofvertex Vl on LPs(Ts), i.e., W 2CLPsCTs)) = L-vIELPs(Ts) w2Cl, Ts). The NS with larger weight w2Cl, Ts)
is expected to have a better chance of reducing the resulting channel density and utilizing OTe
effectively.
After making GsCTs), we determine a setofNSs to be routed by H-V routing at the track

Ts by computing the longest path LPsCTs) on
Gs(Ts). Then we update the channel density and cancel the current NS decomposition of the unrouted NSs on the track Ts. We
start these operations at the minimum avail-Figure 4.9: Step 3: Over-the-cell H-V routing.

able track for H -V routing on M2, and repeat
these operations to all the available tracks for
H-V routing. The brief description of step 3 is as follows.
[Step 3 : OTe H -V Routing]
Step 3.1: Tt = Cap2tmin + 1 and 7b = Cap2bmin + 1, respectively.
Step 3.2: Decompose the set of NSs with vacant terminals(see Appendix C.1.3);
2We learned from experiments that 10.0 for Q2, 2.0 for f32, and 0.5 for,2 work well.

4.3. THREE-LAYER OVER-THE-CELL ROUTING FOR THE BTM-N

79

Step 3.3: Make GtCTiJ and GbCTb), respectively;
Step 3.4: Compute LPtCTiJ and LPbCTb), respectively;
Step 3.5: If W2 CLPt C1t)) > W2 CLPbCTb))
then route the NSs on LtCTiJ on the track 1t and 1t = 1t + 1;
else route the NSs on LbCTb) on the track Tb and Tb = Tb + 1;
Step 3.6: Update the channel density and cancel the current NS decomposition of the unrouted NSs;
Step 3.7: If Tt and Tb are equal to the maximum available track number for H- V routing on M2
then terminate;
otherwise go to Step3.2;

Figure 4.9 shows an example of step 3. The set of NSs {segl' seg7, seg9} on the longest path,
1 ---+ 7 ---+ 9, are routed at track 4.

4.3.6

Planar Routing on M3 (Step 4)

In step 4, we determine the planar routable NSs on M3. Since layer reassignment and H-Vrouting are performed in steps 2 and 3, cap3s(x) are not uniform like cap2s(x), we directly handle
the selection problem of a set of planar routable NSs with maximum weight for non-uniform
routing capacity. We use the same weight wl(segl) used in step 1, and assume that each NS is
assigned at only one track. In the following, we present an optimal algorithm based on dynamic

programming for the problem.
First, we define some terminologies to present the algorithm. For an instance I of the problem, let L be the channel length, that is, the number of terminals in I and k be the maximum
number of tracks allowed on the OTC. Let lex, y, z) denote an instance of the problem definedby restricting I to the interval [x, y] and allowing z tracks for routing. Let M(x, y, z) denotethe maximum weight of any routing solution for lex, y, z). Assume that segl of net ni has two
terminals at columns x and Xl, respectively. Let Xmin be the minimum column number /-L withminimum OTC routing capacity in the interval [x, y] such that z> cap(/-L) (x ~ /-L ~ y)(Fig.4.l0). Our goal is to find a maximum-weighted routing solution M(l, L, k) for the instance1(1, L, k). The following three cases are considered.

Case 1. Xl is not in the interval [x, y].
In this case, we cannot connect segl in any of the solutions for lex, y, z). Thus a routing solution
for lex, y, z) is also a routing solution for l(x + 1, y, z). Therefore,M(x, y, z)= M(x + 1, y, z) if x' ¢ [x, y].

(4.9)

Case 2. x' is in the interval [x, Xmin] (Fig.4.11(a».
Let J be a maximum-weighted routing solution for J(x, y, z). There are two subcases, depending
whether J mayor may not connect segz.

CHAPTER 4. OVER-THE-CELL ROUTING

80

Figure 4.10: The definition of Xmin.

f.-rx.yJ ~f.-rx.yJ ~(a) x' is in [x, xminl(b) x' is not in [x, xminl

Figure 4.11: x' is in the interval [x, Xmin].

Case 2.1. segl is not connected in J.

M(x, y, z)= M(x + 1, y, z).

(4.10)

Case 2.2. segl is connected in J.
M(x,y,z) = M(x+ 1,x' - 1,z - 1) + M(x' + l,y,Z)+wl(segl).

(4.11)

From (4.10) and (4.11), we obtain the following equation,
M(x, y, z)= max{M(x + 1, y, z), M(x + 1, x' - 1, Z - 1)+

M(X' + 1, y, z) + wI(segl)}.

(4.12)

Case 3. x' is in the interval [Xmin, y] (Fig.4.11(b)).
Case 3.1. segl is not connected in J.
M(x, y, z)= M(x + 1, y, z).

(4.13)

Case 3.2. segl is connected in J.
Since x' E [Xmin, y], segz is not connected at the track z, and thus segl must be connected at the
track less than cap(x). Hence,M(x, y, z)= M(x + 1, x' - 1, cap(x) - 1) + M(x' + 1, y, z) + wl(segl).

(4.14)

Then, from (4.13) and (4.14),
M(x, y, z)= max{M(x + 1, y, z), M(x + 1, x' - 1, cap(x) - 1)+

M(x' + 1, y, z) + wl(segZ)}.

(4.15)

Based on (4.9), (4.12), and (4.15), we obtain the following theorem.

Theorem 4.1 The selection problem of a set of planar routable NSs with maximum weight for

non-uniform routing capacity can be solved in O(k . £2) time, where £ is the channel length andk is the maximum number of available tracks on the OTe.
The proof of the theorem is shown in Appendix C.2.

0

4.4. THREE-LAYER OVER-THE-CELLMULTI-CHANNELROUTING FOR THE ATM-081

t---L-i(a) After Step 4.

(b) Final result.

Figure 4.12: Steps 4 and 5.

Based on Theorem 4.1, step 4 works as follows. First perform the two-terminal net decomposition method used in step 1. Next, apply the algorithm based on Theorem 4.1 twice for the
top and bottom cell rows in different order. Then select the optimal solution which has a smaller
channel density, or the same channel density and a larger total weight of NS. Figure 4.12(a)shows an example of step 4 of the top cell row. For the result of step 3 shown in Fig. 4.11, by
applying step 4, segs and seglO are selected and routed on M3.

4.3.7

OTC H-V Routing on Unroutled Regions (Step 5)

Finally, in step 5, we perform H-V routing on the unrouted regions with the same procedure ofstep 3. Unlike step 3, we process tracks from 1 to k so as to route NSs on the OTC as many
as possible. Figure 4. 12(b) shows an example of step 5 of the top cell row. We process all the
tracks from track 1, that is, the boundary of the cell row. Consequently seg6 is routed at track 2.
After this step, for nets which have not been routed on OTCs, we perform channel routing by aconventional channel router and complete the OTC channel routing.

4.4

Three-Layer Over-the-C~ell Multi-Channel Routing fortheATM-O

4.4.1

Problem Formulation

We define some terminologies to explain the proposed algorithm for the ATM-O. For readability,
we redefine some terminologies again which have been defined in Section 4.3. A set of cells
forms a cell row in a chip. A set of cell rows, denoted R = {Ttl T2,··· ,Tk}, is numbered fromthe bottom to the top of the chip(Fig. 4.13). Silmilarly, a channel is a region between adjacentcell rows, denoted C = {Co, Cl, ... 1 Ck}, which is numbered from the bottom to the top of thechip(Fig. 4.13). Let the extended channel eCj E EC be the routing region extended fromchannel Cj to obstacles andlor terminals on the OTCs of cell rows Tj and Tj+l(see Fig. 4.13).
Tracks on cell row T j are numbered from 1 to H from the' bottommost track, and is denoted

82

Ck

..--------..,

+

t+

Ck- ]
r-I- - - - - - - . ,extendedchanneL eCj• ~I______--......+ -........---..~

C]
r-I- - - - - - - . ,

r]

•
_

Vdd/Gnd(Ml)terminaL(M2)wiring(M2)•-feedthrough(M2)obstacle(M2)wiring(M3)Figure 4.13: Definition of terminologies.

Tj = {tt, t 2, ... ,tH}' Columns on cell row Tj are numbered from 1 to L j starting from theleftmost column. Let Lmax denote the maximum column number among all the cell rows, that
is, Lmax = max)~j~kLj.
It is assumed that each multi-terminal net is decomposed into a set of two-terminal nets inglobal routing, and for each two-terminal net, the channel number to be routed is assigned in
global routing. A netlist is defined as N = {n), n2, ... , nN} where ni is a net consisting of a pairof terminals. A set of nets to be routed in channel Cj is defined as Nj = {njl' nj2' ... , njq. }. The
J

location of terminal PI E P on cell row Tj is denoted triple (Xl, tl, j) where Xl, tz, and j denotethe column, the track, and the cell row numbers, respectively. Let the net segment segi E Seg
be an interval between the column position of the left and right terminals of net ni E N, and let
Seg = {seg}, seg2, ... ,segN} be a segment list corresponding to the netlist N.

The top (resp. bottom) OTC routing capacity at column X in cell row Tj, denoted capj(x)(resp. cap~(x)), is defined as the number of routable tracks between the bottom boundary of Tj(resp. the top boundary of Tj-l) and a terminal/obstacle that exists at X in Tj. If no terminals
or obstacles exist at X in Tj, capj(x) and cap~(x) are half the height of a cell, that is, capj(x) =r

LH/2 J, cap~(x) = H /2l Let cross..-Seg(x) denote a set of NSs crossing column x. Then,the local extended channel density dj(x) at column X of extended channel eCj is defined as
dj(x) = max{O, ICToss_seg(x)1 - (capj(x) + cap~+l(x))}. The extended channel density D j isdefined as D j = max}~x~max{Lj,Lj+d dj(x). The total extended channel density AD in the chip isdefined as AD = ~j=o D j .
Now, we formulate the OTC multi-channel routing problem for the ATM-O as follows.
Given a netlist N, obstacles on OTCs, and a set of extended channels EC, the problem is todetermine routing patterns in the channels and on the OTCs so as to minimize the total extended
channel density AD under the given layout constraints.

4.4. THREE-LAYER OTC MULTI-CHANNEL ROUTING FOR THE ATM-O

4.4.2

83

Overview of the Algorithm 3:DR-ATM-O

In the ATM-O, terminals can be located arbitrarily on a cell, and hence the OTC routing capacity
at each column, which is derived from terminal positions, is not always uniform. To effectively
utilize the ATM-O, we propose a new three-layer OTC routing algorithm, called 31JR-ATM -0, [68,126]. The proposed algorithm consists of three phases: (1) multi-channel net assignment,(2) over-the-cell routing considering obstacles, and (3) terminal reassignment and three-layer
channel routing. In phase 1, we simultaneously handle all the channels so as to determine themost effective routing patterns from a set of possible routing patterns. We formulate the problem
to a 0-1 integer linear programming problem and determine routing patterns by solving it. Next,
in phase 2, for the routing patterns selected in phase 1, OTC routing nets are greedily selected
for each track on OTCs. Since 31JR-ATM-O performs not only routing for an entire net but
also routing for a part of a net, the OTC regions are utilized effectively. Finally, in phase 3, a setof nets that have not been selected for OTC routing in phase 2 is routed in channels by using a
conventional channel router [13]. In the following, we present the details of each phase.

4.4.3

Multi-Channel Net Assignment (Phase 1)

In the ATM-O, if either terminals or obstacles don't exist at column x of cell row Tj, net n i canbe routed at the adjacent extended channel eCj lOr eCj - l by passing the column x of the cell row
T j. In other words, a net may have other routing patterns in addition to the routing pattern which

is determined by global routing in eCj. Although a net can be routed in any extended channel
far from eCj, the wire length of the net may become longer. Therefore, if terminals of a net
exist in the adjacent cell rows Tj - l and Tj, it is assumed that the three routing patterns (within
eCj - 2, eCj - l, and eCj) are available for the net on the maximum (Figure 4.14 (a».

On the other

hand, if terminals of a net exist in the same cellI row T j, it is assumed that the net can have thefour routing patterns (within eCj - 2, eCj - l, eCj, and eCj+l) on the maximum (Figure 4.14 (b». We
should select the most effective routing pattenls so as to minimize the total extended channel
density AD = L:J=o D j • We define the selection of the most effective routing patterns fromthe given possible routing patterns as the Multi-·Channel Net Assignment Problem (MCNAP). In
phase 1, the routing pattern of net ni in the MCNAP is determined so as to minimize the total
extended channel density AD.
Since the MCNAP has been shown to be NP-hard [26,112], in 31JR-A7M-O, the MCNAP is solved by applying a 0-1 integer linear programming(~P) technique. To formulate the
MCNAP as the 0-1 ~P problem, we need to generate constraints concerning with an extended
channel density D j for column x of cell row Tj. However, if constraints were generated in astraightforward manner, the number of constraints would become large. Therefore, in order to84(a) three patterns(b)/our patterns

Figure 4.14: Restriction of routing patterns.

•

a vacant column

:

ptj

I

:

Capl4)

t;; p
I

pt4

.--..

•

I I

(a) pattern incompatibLe•
I • • • • IH I
zone(b) vacant coLumn

ICaPb(~)•(c) zone density

Figure 4.15: The constraints of 0-1 ILP problem.

figure out the critical area of an extended channel, we borrow an idea of the zone representa-tion [140]. An advantage of adopting the zone representation in the formulation of the MCNAP
is that the number of constraints and variables of the 0-1 ILP problem can be reduced.
In the MCNAP, we generate the following three constraints, (1) the pattern incompatible

constraint, (2) the vacant column constraint, and (3) the zone density constraint.

(1) The Pattern Incompatible Constraint:

First, we explain the pattern incompatible con-straint. Figure 4.15 (a) illustrates an example of the pattern incompatible constraint. It is assumed that net ni has mi (from our assumption, mi~4) routing patterns, denoted PTi ={pt i1 , pti2, ... , ptimi}. To route all the net without having inconsistency, only one routing pattern ptik E PTi should be selected for net ni. We call this constraint the pattern incompati-

ble constraint. It is assumed that routing pattern ptik of net ni corresponds to 0-1 variable Yik(Yik E {O, I}). If Yik = 1, the net ni is routed with the routing pattern ptik. Otherwise, i.e.,
if Yik = 0, the net ni isn't routed with the routing pattern ptik. Then the pattern incompatible
constraint is represented by,mi(4.16)LYik = 1, Vni E N.
k=1(2) The Vacant Column Constraint: Next, we describe the vacant column constraint. We
define column x{ (1 ~ l ~ L j ) of cell row r j with no obstacles/terminals as a vacant column vx{

4.4. THREE-LAYER OTC MULTI-CHANNE:L ROUTING FOR THE ATM-O

85

of cell row r j. Now, we introduce a constraint for the vacant column vx{. As shown in Figure
4.15 (b), if more than one routing patterns of nets share the same vacant column vx{, it would
lead to a wire-short, and thus we must select one of these patterns. This constraint is called thevacant column constraint and expressed by,(4.17)
niEN ptik which passes V;j~This constraint allows at most one net to pass through vacant column vx{.
(3) The Zone Density Constraint: Finally, we explain the zone density constraint (Figure 4.15(c)). Let cross-seg(x) be the set ofNSs crossing the column x. Since NSs of different nets must
not overlap, the NSs of any two different nets in cross-seg(x) must not be placed on the same
horizontal track and this condition must be satisfied at every column. Zone zl E Zj in eCj isdefined as a maximal interval of columns such that there is a column x in the interval, for whichcross-seg(x) ~ cross-seg(y) holds for any column y in the interval.
To select the most effective routing patterns so as to minimize the the extended channel density D j , we formulate a constraint to consider the aTC routing capacities capj(x) and cap; + 1(x)of cell rows rj and rj+l at column x where a ternlinal is placed at column x. Let H be the numberof tracks on an aTC region and let PTi(zI) C .PTi be a set of routing patterns of net ni in zone
zl E Zj of eCj' Let Gapt(zl) (resp. Gapb(zl)) be the maximum of cap; +1(x) (resp. capj(x)) inzone zI of eCj. For zone zl E Zj in eCj, the actual zone density is equal to the difference between the number of nets passing through the zone and the sum of the maximum aTC routing
capacities of the adjacent cell rows. Therefore the zone density constraint is formulated as,niEN ptikEPTi<z{)

Since each extended channel density cannot be negative, we should have the following additional
constraints,
VeCj

E EG.

(4.19)

Consequently, the MCNAP is formulated as a 0-1 ILP problem as shown below.

[ The 0-1 ILP Formulation of the MCNAP ]kminimize

AD= ~Dj

subject to• the pattern incompatible constraint (4.16)

j=O• the vacant column constraint (4.17)• the zone density constraint (4.18,4.19)
In the current implementation of 3VR-ATM-CJ, we solve this 0-1 ILP problem by the 0-1 ILP

86

tk

I~ i 0'. •c!S •6
4 07

3h

7

I-J-f

I}
i

r

t

H~
1-6-i
extended
1--3 -f 1--5----4
channel eCj
1--2--1
1----7----ic·JI' 11' 1~1' I :@<t!iD

Figure 4.16: The horizontal constraint graph Gj(t k ).

package Ip~0Ive2.0 [5].

4.4.4Over-the-Cell Routing Considering Obstacles (Phase 2)

In phase 2, we select a set of aTC routing nets from the set of nets Nj = {njl' nh, ... , njqj }determined in phase 1, and generate the over-the-cell routing patterns for them so as to minimize
the extended channel density D j. We call this problem the aTC routing problem. Although thereare (k+ 1) extended channels, the aTC routing problem for each extended channel can be treatedindependently. In the following, we only discuss the aTC routing problem of extended channel
Before describing the details of phase 2, we extend the definition of the horizontal constraintgraph(HCG) in Section 4.3 for multi-channel routing. Let Segj(tk)(resp. SegJ(tk)) denote a setof NSs, each of which is H-V routable at the track tk on the aTC of the top and bottom cellrows of eej. Let Gj(t k ) and G~(tk) be the horizontal constraint graphs for track tk of the top andbottom cell rows of eej, respectively. The horizontal constraint graph Gj(tk)(S = t, b) for track
tk (tk E Tj+l if s

= t, tk E T j if s = b) is a directed weighted graph. Each vertex Vi E V/(t k ) inGj(t k ) (resp. Vi E V/(tk) in G~(tk)) is corresponding to a NS Segj(tk) C Segj(resp. SegJ(tk) CSegj). Directed edge eim = (Vi, Vm ) E EJ(tk)(S = t, b) is inserted from Vi to Vm if and only if

the two vertices Vi, Vm E V/(tk) corresponding to segi, segm E Segj(tk) satisfy the conditionsr(segi)< l(segm ) 1\ net(segi) =I net(segm) or r(segi) ~ l(segm ) 1\ net(segi) = net(segm ).

Figure 4.16 shows an example of the horizontal constraint graph Gj(tk) for track tk on the top
cell row rj+l.
Next, we define the weights of edge ejm and vertex Vi for the horizontal constraint graphGj(tk)(S = t, b). Phase 2 consists of two stages, and the horizontal constraint graph Gj(tk) is

employed in each stage. If segj and segk corresponding to vertices of edge ejk = (Vj, Vk) satisfy
net(segj)= net(segk), then the weight we(ejk) of edge ejk in stages 1 and 2 is 1, otherwise

4.4. THREE-LAYER OTe MULTI-eHANNl~L ROUTING FOR THE ATM-O

ilm::r:~:::;::!IWl

H~i

87

I ! !I ~m~~"'.4i1ID~"" t~ ~ ~~"'m ' j\..HiH·. ·
...

3

....

3

•

4

.

1

divided....J-+-2~4----.
.-J-+2+-3-1

next track3.....- - - - f

4
----.

1-3-1

Figure 4.17: The definition of an unrouted interval and a subsegment.

we(ejk)= O. The weight Wv(Vi) of vertex Vi corresponding to segi in stages 1 and 2 is defined as
Wv(Vi)dj(x)= kl x l(segi)~a,max- - + len(segi),~r(segi) D(4.20)jwhere kl denotes a positive constant3 • From the definition of this weight, a NS with a larger
value of the weight is considered to be more effective to reduce the extended channel density

D j, and has a larger possibility to be selected as an OTC routing net.
Phase 2 consists of two stages. In stage 1, a set of NSs which reduce the extended channel
density D j are selected from Segj and routed on the OTCs. In order to utilize the OTCs which
are not used for routing in stage 1, in stage 2, NSs which could not be routed in stage 1 are
divided into sub-NSs, and then the sub-NSs are tried to be routed in unrouted intervals of tracks
on the OTCs. An unrouted interval at track t:k on an OTC is an interval that is not used forrouting in stage 1. For example in Fig. 4.17, segl and seg2 are routed at track tb but the centerregion of track tk is not used for routing in stage 1. But seg3 and seg4 cannot be routed in thisun routed interval without dividing it. Dividing seg3 into two sub-NSs and seg4 into three subNSs based on columns that are not used for routing at tb seg4,1 and seg4,2 become routable att k • This dividing procedure can be applied to r~ss satisfying the condition that sub-NSs can berouted at track tk on the OTC region.
In stages 1 and 2, 31JR-A7Jvt-O selects OTC routing nets by finding a path, denoted
path(tk), that has the maximum total weight on Gj(tk)(S = t, b). The weight wp(path(tk)) ofpath(tk) on Gj(tk) is defined as,(4.21)

3In our experiment, we set k) = 300.

88
where k2 denotes a small positive constant4 • Finding path(tk) with the maximum total weighton Gj(tk) means to determine a set of NSs which do not overlap each other and reduce the extended channel density D j • The detailed description of phase 2 is as follows.
[Phase 2: Over-the-Cell Routing]Stage 1
Step 1 :Set the starting tracks, bt and tt, at cell rows Tj and Tj+l to
bt = H - max1:Sx:SLj capj(x) + 1, tt = max1:Sx:SLj+l cap~+l (x), respectively;

Step 2 :Calculate the weight Wv(Vi) of G~(bt) and Gj(tt) for segi E Segj(bt) and segi E Segj(tt) of
N j , respectively;

Step 3 :Make RCGs G;(bt) and Gj(tt), and find path(bt) and path(tt) that have the maximum total
weights, respectively;

Step 4 :If wp(path(bt)) > wp(path(tt)), then assign a set of NSs on path(bt) to the track bt and set
the current processed track ct = bt;
Otherwise, assign a set of NSs on path(tt) to the track tt and set the current processed track
ct = tt;

Step 5 :Update Segj of N j ;Stage 2
Step 6 :In order to utilize the unrouted regions on the current track ct, divide segi E Segj into subNSs at columns that are not used for routing of the track ct;

Step 7 :Update Segj of N j , calculate the weight Wv(Vi) for sub-NS segi E Segj;

Step 8 :Make ReGs Gj(ct) of the current routing track ct for the new Segj, and find path(ct) withthe maximum total weight;

Step 9 :Route sub-NSs of nets on path(ct) within the unrouted interval of the current routing track
ct;

Step 10: Merge sub-NSs that were not routed within the unrouted intervals in Step 9, and update Segj;
Step 11: If bt = Hand tt = 1, then terminate;
Otherwise, if bt was selected as the current processed track, then bt f - bt + 1 and go too
Step2, else tt f - tt - 1 and go to Step2;

Time complexity of phase 2 is as follows. Let INi 1be the number of nets to be routed within
the extended channel eej and H be the height of the cell row. In the aTC routing algorithm, thetime complexity to construct a HCG and to find a path for each track is O(INj 12 ). This process
is repeated for the H tracks of the cell row, and therefore the time complexity of phase 2 isO(H . INj 12 ).
4We set k2 = 0.01 in the current implementation.

4.4. THREE-LAYER OTC MULTI-CHANNE:L ROUTING FOR THE ATM-O

4.4.5

89

Terminal Reassignment and (~hannel Routing (Phase 3)

Phase 3 is performed for nets which have not been routed on aTCs in phase 2. First, a verticalconstraint graph [140] for the extended channel is constructed based on terminal positions ofunrouted nets. If there exist cycles in the vertical constraint graph, terminals are drawn out tothe appropriate positions at the boundaries of cell rows so as to break cycles as many as possible.
In the current implementation, we greedily change columns used to draw out terminals which
are on cycles if it is possible to change their positions. Since all the terminals of unrouted nets
are located at the boundaries of cell rows, this model can be regarded as the BTM. Then we apply
a conventional greedy three layer channel router [13] and the aTC channel routing is finished.

4.4.6

Treatment of Timing Constraiints in Phase 1

The routing topology of each net is determined so as to satisfy the timing constraints in both
placement and global routing. If we do not extremely change the routing topology, it is usually
enough to consider the minimization of the chip area and the total wire length in detailed routing.
However, in the multi-channel net assignment in phase 1, to minimize the total extended channel
density, we select the most effective routing patterns among the possible routing patterns for eachnet, and hence the routing topology of a net may be different from that obtained by global routing.
Therefore, for the timing-critical nets, we shou1ld take the timing constraints into account whenchanging the routing topologies.
A multi-terminal net is decomposed into a set of two-terminal nets based on the global routing results as mentioned in Section 4.4.3. Thus the timing constraint of a net can be divided
into a set of sub-constraints of two-terminal nets. For each two-terminal net, a timing constraint
can be given by the upper bound of the wire length of the net, denoted Lu(ni ). To satisfy thetiming constraint, we should not select the routing patterns which cause the timing violation of
the net in phase 1. Let h( ni) and v( ni) denote the horizontal and vertical wire lengths of net
ni, respectively. Let length(ni) be the sum of the horizontal and vertical lengths of net ni, thatis, length(ni) = h(ni) + v(ni). The horizontal length h(ni) of ni is equal to len(s egi) of thecorresponding segi . The vertical length v( ni) of ni depends on which routing patterns of net ni
is selected. For example in Fig. 4.14(a), if net ni is routed on the pattern pt2' v(ni) is equal tothe vertical length between the two terminals but if net ni is routed on the pattern ptl' it is longer
than that of pt 2 • Therefore, before the 0-1 ILP formulation, we remove all the patterns which
may cause the timing violation of net ni from the set of the candidate of patterns by comparing
the length of the pattern with the upper bound length Lu(ni) of net ni. Then we formulate the
MCNAP problem to the 0-1 ILP problem. Since all the remaining patterns of net n i can satisfy
the timing constraint, we can obtain the result so as to min'imize the total of extended channel

90
densities under the given timing constraints by solving the 0-1 ap problem.

4.5

Experimental Studies

4.5.1

Evaluation of 3VR-BTM-N

We have implemented 3VR-BTM-N for the BTM-N described in Section 4.3 in C language
on a SPARC station 2 (28.5MIPS), and tested it with the benchmarks 3a, 3b, 3c, and Difficult(forshort Diff) in [140] and industrial channel routing data ch 1 rv ch2. Table 4.2 summarizes the test
data. For data ch 1 rv ch2, we performed placement and global routing with TimberWolfSC4.2c[109] and the global routing system GLORIA [72] we have developed, respectively. For these
data, we randomly assigned the second layer OTC routing capacities(cap2s(x)) for each column
from 3 to 6, and obtained the BTM-N data. In Table 4.2, #nets and #cols are the numbers ofnets and columns for each data, respectively, and cap2smin, cap2smax, cap2save., and cap3s( *) are
the minimum, maximum, average second layer OTC routing capacities, and the third layer OTC
routing capacity, respectively.

Table 4 ..
2' Test data for the BTM-N
Name

#nets

#cols

m'ln

cap2s
max

ave.

cap3s(*)

3a
3b
3c
Diff
chI
ch2
ch3
ch4

30
47
54
72
276
104
129
504

45
75
103
175
886
646
646
1595

3
3
3
3
3
3
3
3

6
6
6
6
6
6
6
6

5.07
4.95
4.96
5.02
4.96
4.98
4.97
4.97

6
6
6
6
6
6
6
6

Table 4.3: Experimental results for the BTM-N (vs. planar routing [26])D after routing#tracksName
D
planar Ddiff 3VR-B1M-N
planar
3VR-B1M-N
6
3
10
3a
15
5
5
3
2
3
4
6
3b
17
6
9
2
11
3
7
3c
18
8
5
14
4
7
2
Diff
19
10
9
4
2
10
chI
16
7
3
6
ch2
21
9
16
7
5
8
3
3
ch3
6
11
17
5
3
6
ch4
40
30
34
4
15
17
2
~to_ta_l~II_16_3~11_____
8_1____~_11_5~__3_4~_____
46____- L_ _65__~_E~

Tdi~

4.5. EXPERIMENTAL STUDIES

91

Table 4.4: Experimental results for the BTM-N(vs. H-V routing).

I D IID after routing
II#tracksI
arne
3VR-B7JVt-N I H-V I DdifJ 3VR-B7JVt-N I H-V I TdiJf
3a
15
5
3
3
5
8
2
4
3b
17
6
10
4
6
2
3c
18
5
7
8
11
3
2
19
10
Diff
10
15
5
7
3
16
7
chI
10
4
3
5
1
21
ch2
9
2
2
11
5
6
4
ch3
17
6
10
4
3
1
40
ch4
30
33
3
15
17
2
81
46
I 108 I 27 II
I total I 163 II
I 60 I 14 I
I

N

Table 4.5: Experimental results for the BTM-U(vs. planar routing [26]).
D after routing#tracks
Name
D
3VR-B7M-N
planar DdifJ 3VR-B7M-N
planar Tdiff
4
3a
15
9
5
3
5
2
3b
17
6
2
8
3
5
2
3c
2
4
18
8
10
2
6
12
Diff
19
9
3
5
6
1
16
6
9
3
3
5
2
chI
ch2
14
21
5
5
7
2
9
ch3
17
5
10
5
3
5
2
ch4
29
32
15
17
40
3
2
104
28
41
15
76
56
total I 163 I

First, we compared our algorithm with Cong's OTC routing algorithm(DP) [26], which isbased on dynamic programming and does not consider the non-uniform routing capacity on the
OTC. In Cong's algorithm, we assumed that the cell model was BTM-U and M2 and M3 routing
capacities were uniform, that is, cap2s(x) = cap2smin = 3 and cap3s(x) = 6, and the planar
routing was performed in both M2 and M3 layers, respectively. In 3VR-BTM-N, we used
BTM-N in which the second OTC routing capacities for each column cap2s(x) were different,
and set cap2smin = 3 and cap3s(x) = 6. For both the OTC routing algorithms, three-layer channelrouting was performed with the greedy three-layer channel router in [13].
Table 4.3 shows the comparison results. In the table, DdifJ and TdifJ mean the differencesof the channel density and the number of tracks between 3VR-BTM-N and Cong's(planar)algorithms, respectively. From Table 4.3, AlgoBTM-N can route with about 4.3(ave.) and7(max.) smaller channel density than Cong's algorithm utilizing the OTC, and produces always
small height layouts.
In Table 4.4, we show the comparison results of the algorithm which only performs H-V
routing from 1 track to k track on the OTC. In Table 4.4, H- V means the channel densities of

92
the H-V routing algorithm. From the results, AlgoBTM-N can produce the routing results with
about 3.4(ave.) and 5(max.) smaller channel density than the H-V routing algorithm.
Finally, we applied 3VR-BTM-N to the BTM with unifonn routing capacity (BTM-U)
where the OTC routing capacities are cap2s(x) = 6 and cap3s(x) = 6. Table 4.5 shows the resultscompared with Cong's OTC routing algorithm [26]. Since, in 3VR-BTM-N, the planar and the
H-V routings are perfonned based on the minimum OTC routing capacity of M2 cap2smin, we
need to set cap2min some value so as to utilize the OTC effectively. It is difficult to know the bestvalue of cap2smin before the OTC routing and hence we set the second OTC routing capacity
cap2s(x) = 1 rv 6, and applied the planar routing of step 1 and the layer reassignment and planar

routing of step 2. After steps 1 and 2 for each cap2s(x), we reset cap2s(x) = 6, applied steps 3 rv
5, and selected the best routing result among them. From the results, AlgoBTM-N can produce
layouts with 3.5(in ave.) and 5(in max.) smaller channel density than Cong's algorithrn [26].
For most of data, the best routing result was obtained when cap2smin = 3 or 4. Although thenumber of available tracks on OTC of the planar routing algorithm may be double of that of the
H-V routing algorithm, it cannot always utilize these tracks because of the routing constraint
in which nets are not crossed each other. On the other hand, 3VR-BTM-N perfonns planar
routing for the OTC regions near the channel and H -V routing for the OTC regions far fromthe channel. Combining planar and H-V routing algorithms, AlgoBTM-N can utilize the OTC
effectively, that could hardly be achieved by existing algorithms. Thus the above results havedemonstrated the effectiveness of 3VR-BTM-N for the BTM-U.

4.5.2

Evaluation of 3VR-ATM-O

We have implemented 3VR-ATJvt-O for the ATM-O described in Section 4.4 in C language on
a SPARCserver 1000 (135MIPS) and tested it with benchmarks. For phase 1 of 3VR-ATM-O,
we used the 0-1 ILP package Ip_solve2.0 [5]. Table 4.6 shows experimental data. For PRJMARY
I benchmark in [49], placement and global routing were perfonned by TimberWolfSC [82] and a
global router [21], respectively. The rest of benchmarks are MCNC benchmarks and placement
and global routing were perfonned by TimberWolfSC4.2c [109] and GLORIA [72], respectively.
In original data, tenninals are placed at the boundary of a cell and equivalent tenninals are on
the vertical column. Since the cell model of the original data is different from the i\TM-O,
for 3VR-ATM-0, we transfonned these data of the BTM to the ATM-O. The details of thetransfonnation is described in Appendix C.3.
First, we compared 3VR-ATM -0 with a three-layer channel routing algorithm and three
conventional three-layer OTC routing algorithms. Those compared algorithms are as follows:(1) the three-layer greedy channel routing algorithm (3CR, for short) [13], (2) the three-layer

OTC routing algorithm for the BTM based on planar routing algorithm [27](3PR) + 3CR, in4.5. EXPERIMENTAL STUDIES

93

Table 4.6: Experimental data for the ATM-O.
Data
I #Nets I #Columns I #channels I #obstacleslrow I
PRIMARY I
1266
18
176
477
644
mult16
1920
1043
13
433
21
struct1920
635
203
primarySCI
1266
646
27
#obstacleslrow : the number of obstacles per a cell row.

Table 4.7: Experimental results for three-layer OTe routing methods.
PRIMARY I
mult16
structprimarySCI
average

289
188
284
419

172
99
153
221

95
52
95
127

84
58
88
107

78
53
89
120

64
40
66
74

32.6
23.1
30.2
41.7

23.8
31.0
25.0
15.7

I 31.9 I 23.9

17.9
24.5
25.8
38.3
26.6

Table 4.8: CPU time of 3VR-ATM-O-o .

Data
I Phase J(sec.) I Phase 2(sec.) I Phase 3(sec.) I Total(sec.) I
12.2
49.2
232.0
PRIMARY I
170.6
230.2
19.4
1375.21125.6
mult16
21.0
594.3
500.6
72.7
struct
58.5
396.5
156.3
181.7
primarySCI

which the planar routing is performed on M2 and M3 layers, (3) the three-layer OTC routing
algorithm for the BTM based on H-V routing algorithm [67](3HV) + 3CR, in which OTC routing
is performed on M2 and M3 layers, and (4) 3VR-BTM-N presented in Section 4.3 (3VR-

BTM-N ) + 3CR. For the conventional algorithms, the multi-channel net assignment(phase1) of 3VR-ATM-O was not applied, that is, each net was routed with the routing patterndetermined by the global router. Moreover, obstacles were not placed in each cell row and GTC
routing capacity of each cell row wa& set to 12 (The top and bottom GTC routing capacities were
6 and 6, respectively).
Tables 4.7 and 4.8 show the results of the proposed and conventional algorithms, respectively. In Table 4.7, D denotes the original channel density with two layers. L- T3AT M-O
denotes the total number of tracks obtained by 3VR-ATM-O. Similarly, L- T 3CR , L- T3PR ,L- T 3HV , and L- T3BT M-N are the total number of tracks obtained by each routing algorithm,
respectively, and %RT3PR ' %RT3HV ' and o/ORT3BTM _N denote the improvement ratio of 3VR-

ATM-O (L- T3AT M - O) to each routing algorithm, respectively. Table 4.8 shows the CPU timeof each phase of 3VR-ATM-O. From the results of Table 4.7, 3VR-ATM-O can route ina number of tracks of 31.9% (ave.) and 41.7'% (max.) better than the algorithm 3PR, 23.9%(ave.) and 31.0% (max.) better than the algorithm 3HV, and 26.6% (ave.) and 38.3% (max.)better than 3VR-BTM-N presented in Section 4.3 . Consequently, these experimental results

94
Table 4.9: Experimental results for three-layer OTC routing methods for PRIMARY I.

I channel I D I T 3cR I T 3PR I T 3HV I T3BTM - N I TW ILMA3 I TO-V3 I TO+V3 I T 1cR-3 II T3ATM - 0 I
1
2
3
4
5

-6
7
8
9
10
11
12
13
14
15
16
17
18
Total

11

16
21
24
20
23
22
21
21
14
16
14
13
13
10
11

13
6
II 289 I

6
9
11

15
11

12
14
16
13
8
12
8
8
7
6
6
7
3
172

3
6
7
9
9
8
7
8
5
6
4
5
4
4
3
3
4
1
95

0
4
7
9
8
8
6
7
6
6
4
4
4
3
3
2
3
0
84

2
5
6
6
7
7
5
7
6
5
4
3
3
3
3
2
3
1
78

2
5
6
9
7
7
5
7
6
5
5
4
3
4
2
2
3
1
83

1
5
6
6
6
7
4
7
6
4
3
3
3
3
2
2
3
0
71

2
4
5
4
4
5
5
8
6
4
4
3
3
4
3
3
3
1
71

3
6
8
10
8
10
7
9
7
7
6
5
4
4
3
3
3
1
104

I

II

1
3
6
7
4
8
6
5
5
3
3
2
2
3
1
2
3
0
64

have demonstrated the effectiveness of the proposed cell model and routing algorithm. From
Table 4.8, the CPU times of conventional algorithms are shorter than the sum of the CPU timeof phases 2 and 3 of 3DR-ATM -0. Although 3VR-ATM -0 takes a longer computation timethan the conventional algorithms, it is permissible for practical use.
Finally, we compared 3VR-ATM-0 with the conventional three-layer OTC rOlUting algorithms for the BTM, WILMA3 [95], 0-V3 [49], and 0+V3 [49], and the three-layer OTC
routing algorithm ICR-3 for the CTM in [137]. Table 4.9 shows the experimental results after
the OTC routing. The results of WILMA3, 0-V3, 0+V3 and, ICR-3 are referred from [95],and [49], [137], respectively. From Table 4.9, 3VR-ATM-0 can route in a total number oftracks of 62.8% better than the 3CR, 32.6% better than the 3PR, 23 .8% better than the 3HV,
17.90/0 better than 3DR-BTM-N, 22.9% better than the WILMA3, 9.9% better than the 0-V3
and 0+V3, and 38.5% better than the ICR-3, respectively. Therefore, we can conclude that boththe proposed cell model and the routing algorithm are effective in reducing the chip area.

4.6

Concluding Remarks

In this chapter, two new standard cell models have been proposed for OTC routing; the Boundary

Terminal Model with Nonuniform OTC routing capacity(BTM-N) and the Arbitrary Terminal
Model with Obstacles on arbitrary position(ATM-O). To effectively utilize the proposed cell
models, new three-layer routing algorithms, 3VR-BTM-N and 3VR-ATM-0 have been

4.6. CONCLUDING REMARKS

95

proposed. For the BTM-N, we have developed an optimal algorithm for the problem of selecting planar routable OTC nets for non-uniform routing capacities and proposed the routing
algorithm combining planar and H-V routings. The multi-channel OTC routing algorithm has
been proposed for the ATM-O which simultaneously optimizes the routing patterns of nets inall the channels with the 0-1 integer linear programming. We also extended 3DR-ATM-O tosolve OTC routing problem under given timing constraints. Experimental results have demonstrated that the proposed cell models and the routing algorithms are effective in reducing thechip area. Moreover, we have shown that 3DR-BTM-N and 3DR-ATM-O can be applied tothe conventional cell models and can produce results comparable with the conventional routers.
Future research includes an extension of the proposed algorithms to handle the other conventional cell models, for example, the MTM, the CTM and the TBC.

Chapter 5
Floorplanning, Global Routing and Pin Assignment
Algorithms for Building Block: Layout
This chapter discusses problems concerning building block layouts, such as ftoorplanning, pin
assignment, and global routing. First, timing-driven ftoorplanning algorithm is proposed; it
determines positions of blocks and fixes shapes of soft blocks so as to minimize the total chiparea. The proposed algorithm is based on both the placement algorithm presented in Chapter
2 and topological constraint manipulation. Next, we propose a timing-driven global routing
algorithm based on coarse pin assignment, block reshaping, and positioning. As opposed toconventional approaches, we combine pin assignment and global routing problems into one
problem. The proposed algorithm also adjusts shapes and positions of soft blocks. Finally, we
propose an algorithm for optimally solving the channel pin assignment and propose an optimalalgorithm for a channel pin assignment proble1TI.

5.1

Introduction

In building block layout, a VLSI circuit is partitioned into a set of components, referred to as
blocks, and there are two types of blocks, that is, hard blocks (hard macros) and soft blocks (softmacros). The former are pre-designed, that is, their shapes and pin positions are pre-determined.

Since this is not the case with the la~ter, we ar'e regarded to specify their exact shapes and pin
positions in layout design. The goal of building block layout design is to determine the shapes ofblocks, their positions, and the interconnections among them so that the chip area may be usedin the best possible way. Main difference from the standard cell layout design is that horizontal
and/or vertical size of blocks can be changed and that they can be placed at any position in thechip. Therefore we can optimize the area and the performance of chip in comparison with thestandard cell layout more rigidly. Routing area in the standard cell layout consists of a collectionof rectangles, while this is not the case in the building block layout: it consists of some channels
and a number of switchboxes. This makes both placement and routing to be more complicatedthan those of the standard cell layout.
Due to its high complexity, layout design is usually done in four stages, namely, jioorplanning, pin assignment, global routing, and detailed routing [83]. In detailed routing, conventional

97

98

CHAPTER 5. FLOORPLANNING, GLOBAL ROUTING AND PIN PSSIGNMENT

channel/switchbox routing algorithms are usually used. In this chapter, we discuss floorplanning, pin assignment and global routing for the building block layout.
In the building block layout design, floorplanning is the first and an essential design stage
to determine several important factors of the layout, such as the overall area required by a chip,
the sizes and shapes of blocks, pin and pad locations, etc .. The goal of floorplanning is to decide
topological proximity as well as appropriate shapes of blocks. Floorplanning is usually divided
into two steps [83]: global placement and detailed placement. In the global placement step, we
determine the relative positions of blocks so as to minimize the total wire length. Since blocks
are generally treated as points representing the center coordinates of the blocks, when we try toactually mount them on the chip, they may be overlapped each other because of their varietyof the shapes and the occupying areas. Several algorithms have been proposed for the global
placement step, for example, a min-cut based algorithm [79], a force-directed relaxation based
one [10 1], and a simulated annealing based one [108]. On the other hand, the detailed placement
is essentially a process that converts a given global placement floorplan into a legal optimal area
floorplan 1• Several algorithms have also been proposed for the detailed placement step: forexample, a simulated annealing based algorithm [136], and those that are based on a branch andbound approach [134J, a mathematical programming approach [92,104], or a constraint based
approach [30,35,129].
Similar to the placement step of the standard cell layout, this floorplanning step has a criticaleffect on the performance of a circuit. Therefore several timing-driven algorithms have been
proposed [40,97,106, 123, 141]. In [97], Ogawa et al. transformed timing constraints, given as
the maximum interconnection delays for nets, to net length constraints, and presented a timingdriven placement algorithm consisting of a bottom-up clustering phase and a top-down enumerative placement phase. They did not consider sizing of blocks. Tia and Liu [123] presented atiming-driven placement algorithm based on both a force-directed approach and a concept of awindow which estimates an initial placement of a block. They assumed the simple RC model
for modeling the interconnection delay and did not consider the sizing of blocks either.
After the floorplanning step, pin assignment and global routing are performed. In pin assignment, pin positions of soft blocks are determined so as to minimize the occupied chip area,
the total wire length, and so on. Several researchers have investigated pin assignment problems [10,23,98,138]. The topological pin assignment algorithm in [10] processes pins block byblock. [138] takes advantage of physical analogy between pin assignment and rotational torquein solving the problem. These two algorithms do not take global routing into account. Refs. [98]and [23] performed pin assignment and global routing simultaneously. In [98], the pin assign1We define a floorplan to be legal if there are no overlaps among blocks, and if the shapes and placement of theblocks satisfy both the aspect ratio bounds and pre-placement conditions.
.

5.1. INTRODUCTION

99

ment problem is solved by transforming it into a linear assignment problem. However, global
routing depends on initial assignment of pins and it seems difficult to consider the precise influence of the pin assignment to the channel density. This is because the cost of assigning eachpin to a slot is independent of the positions of other pins. In [23], pin assignment and global
routing are combined into one algorithm. First, it constructs, from a floor connection graph, asupergraph containing global routes of all nets and then sequentially eliminates edges, called"non-essential" edges, which do not belong to net connection tree. However, coarse pin assignment depends on the eliminating order of the "'non-essential" edges, while no "good" ordering
for edge deletion has been found yet. It is assumed that shapes and positions of all blocks are
fixed.
Several timing-driven algorithms for global routing have already been proposed. Some
Steiner tree construction algorithms for routing one net have been proposed [9,24, SO, 8S, 99]
while the objective is to minimize the interconnection delay from the source to loads of the net.
These algorithms do not take congestion of the routing regions into consideration. In the building block layout design, however, minimizing the chip area as well as interconnection delay isinevitable. In order to avoid poor estimation of chip area, it seems necessary to take advantage
of certain costs, such as, congestion of each routing regions, explicitly. Therefore we cannot
use these existing algorithms directly in globall routing for the building block layout design. In
addition, we can expect that performing simultaneously pin assignment and global routing maylead to further reduction of chip area, because they may heavily depend on each other.
Detailed routing follows global routing and it is usually done by means of any existing conventional channel router. In conventional channel routing, all pin positions of the top and thebottom of the channel have to be given in advance, while the pin positions of soft blocks areleft unfixed by the global routing in the building block layout. Since good assignment of thepin positions may possibly improve.quality of the layout, we try to optimize the pin positions
so as to minimize the chip area and the total wire length. This problem is called the channel pin
assignment (CPA) problem. The problems under certain constraints have been investigated byseveral researchers [16, 17,23, 2S, 42,80,84, 124, 12S]. For example, Leong and Liu [84] considered the permutation channel routing problem, in which some sets of pins can be permuted.
They proposed a heuristic algorithm, based on the simulated annealing technique, to minimize
the channel density. Cong [23] considered the CPA problem with permutable pins: pins are
assumed to be permutable and at most only one pin of every net can exist on each side of thechannel. An algorithm for optimally minimizing both the density and the total wire length of thechannel is proposed. In the building block layout, however, the top and/or the bottom of channel
is often partitioned into several intervals and pins can be permuted only within their associatedintervals. Therefore this algorithm is difficult to be applied to this type of channels.

lOO

CHAPTER 5. FLOORPIANNING, GLOBAL ROUTING AND PIN PSSIGf1vMENTIn this chapter, we propose a timing-driven floorplanning algorithm(TV-FPN), a timingdriven global routing algorithm with coarse pin assignment(TV-9nPA), and a channel pin
assignment algorithm(ACPAI ) for the building block layout. In TV-FPN, we apply thetiming-driven placement algorithm, POPINS ,presented in Chapter 2 to the global placement
step and then perform the detailed placement with an algorithm based on topological constraint
manipulation. For pin assignment and global routing, to get a high density layout, we combine
pin assignment and global routing problems into one problem and propose an algorithm integrating global routing and pin assignment(TV-gnPA). Tv-gnPA also adjusts the shapes
and positions of soft blocks and takes the timing constraints into consideration. After the global
routing step, the interconnection topology of each net is determined so as to satisfy the timing
constraints. Hence, in channel pin assignment, it is sufficient to consider the minimization of thechannel density and total wire length. We discuss the CPA problem which determines the positions of pins so as to minimize the density and the total wire length of the channel, and present a
linear time optimal algorithm, ACPAl , for an important special case of the CPA problem [73].
The remainder of this chapter is organized as follows. Section 5.2 presents a timing-driven
floorplanning algorithm based on a nonlinear programming and topological constraint manipulation. In Section 5.3, we propose a timing-driven global routing algorithm consisting lOf coarse
pin assignment, block reshaping, and block positioning. In Section 5.4, a linear time algorithm
is presented for optimally solving an important special case of the channel pin assignment problem. Section 5.5 shows experimental results and the evaluation of the proposed algorithms.
Finally, in Section 5.6, we summarize this chapter and describe future work.

5.2

TV-FPN: A Timing-Driven Floorplanning Algorithm

5.2.1

Problem Formulation

A chip is a rectangular region which is surrounded by I/O pins on its boundary and contains
blocks of different sizes within this boundary. A set of blocks M = {ml' m2, ... , mM} consistsof a set of hard blocks Mh and a set of soft blocks Ms. Let w(mj) and h(mj) denote the width
and the height of block mj, respectively, and let a(mj) and r(mj) indicate the area and the aspectratio of block mj, respectively. For hard block mhi E Mh, its width and height are fixed andthe pin positions are specified in advance. For soft block mSi EMs, its width and height are
temporarily given but not fixed, and its area and lower and upper bounds of its aspect ratio,(rZ(msi), r u(msi)), are specified. A set of nets N = {nl' n2, ... ,nN} describes the connectivity

information. For simplicity in the presentation, it is assumed that all pins of a block are locatedat the center of the block.
In general, a timing constraint can be specified between a primary input or an output of flip-

5.2. TV-FPN: A TIMING-DRIVEN FLOORPLANNING ALGORITHM

101

ftops(FFs) and a primary output or inputs of FFs. However, soft blocks are not pre-designed in
the hierarchical design of the building block layout and hence the timing constraints are separately treated as the timing constraints of the inside and outside of soft blocks. Therefore, inthis paper, we assume that a timing constraint is given between the source pin and a load pin of
net ni. Thus we specify a timing constraint of the source pin and a load pin j of net ni as the
maximum allowable propagation delay Delallowij from the source to the load. For the interconnection delay model, the Elmore delay model described in Section 2.2 is adopted and the delaydelij from the source to the load j of net ni is estimated by equation (2.2). Consequently, if
delij ::; Delallowij' then the timing constraint is satisfied.
Now, we formulate the timing-driven ftoorplanning problem (TDFP) as follows.

[The Timing-Driven Floorplanning Problern (TDFP)]
Inputs: (1) a set of blocks M = Mh u Ms, (2) a set of nets N,(3) timing constraints T, and, (4) physical parameters.
Output: a legal ftoorplan of M which minirnizes the objective function.
Objective Function: the chip area.
Constraints: (1) no two blocks overlap, (2) Vmsi EMs, rl(msi) ~ r(msi) ~ ru(msi), (3)Vmsi EMs, a(msi) = W(msi) x h(msi), and (4) satisfy the timing constraints T.

5.2.2

0

Overview of the Algorithm 7~V-FPN

The proposed ftoorplanning algorithm,
called TV- FPN, consists of two phases:(1) construction of a timing-driven t,?pologi-

44cal arrangement with nonlinear programming,(2) conversion of the topological arrangement
into a legal ftoorplan. In the first phase, we de-

3

1

2

3

termine a topological arrangement of blocks(2) phase 2

by applying the algorithm based on nonlin-(a) phase 1

ear programming presented in Chapter 2 with

Figure 5.1: The outline of TV-FPN.

some modification (Fig 5.1(a)). Next, we perform ftoorplan sizing which determines thesizes and shapes of blocks based on the topological arrangement obtained in the first phase so as
to minimize the chip area and to obtain a legal ftoorplan [60,61] (Fig 5.1(b)). In the following,
we present the details of each phase.

102

CHAPTER 5. FLOORPIANNING, GWBAL ROUTING AND PIN PSSIG]\lMENT

5.2.3

Timing-Driven Topological Arrangement with Nonlinear Programming (Phase 1)

Since the number of blocks in the hierarchical design of the building block layout is fewer thanthat of the standard cell layout design 2, we can obtain an initial topological arrange:ment ofblocks by applying phase 2 of the timing-driven placement algorithm, POPINS, presented
in Chapter 2. However, the width and height of blocks are much larger than those of standard
cells and some blocks may be overlapped each other. To minimize overlaps among blocks,
we select a target subcircuit Lmov = (M mov )N mov ), which has been defined in Chapter 2, andadd a set of constraints that specify a minimum separation of each pair of blocks. Then weformulate the problem into a nonlinear programming problem with the timing and minimum
separation constraints, and obtain a new topological arrangement of blocks by solving it. Thoseoperations are repeated until the topological arrangement satisfies the timing constraints and theratio of overlaps among blocks becomes less than a pre-determined value. Since the proposed
algorithm is similar to phase 2 of the algorithm presented in Chapter 2, in the following, we firstdescribe the formulation of the timing and minimum separation constraints and then present theoutline of the algorithm.

Constraints of Net Delay
Let Wi and hi denote the width and height of the bounding box of net ni E N, respectively. As
mentioned in Section 5.2.1, the timing constraints are specified by pairs of the source pin and aload pin j of net ni E N. Then the constraints of net delay can be written as follows.

CD:

(5.1)

Constraints of Minimum Separation
To control block overlaps in phase 1, we specify a minimum separation between two blocks.
The minimum separation is expressed by the Manhattan distance between the centers of two
blocks. The distance between blocks mj and mk, denoted distjk, is defined as,
dist jk = J(Xj - Xk)2 + (Yj - Yk)2.

(5.2)

To guarantee that mj and mk will not overlap, it is sufficient to have distjk ~ (w(mj)+w(mk)+h(mj)+h(mk»/2 where w(mj) and h(mj) are the width and height of mj) respectively. Clearly,

excessively stringent requirements might cause the algorithm to fail even though a feasible arrangement does exist. In phase 1 of the algorithm, we do not have to delete all the overlaps
because phase 2 does. To avoid over-constraining the problem, we set the minimum separation
2UsuaIly, the number of blocks is less than 30 ~ 40.

5.2. TV-FPN: A TIMING-DRIVEN FLOORPLANNINGALGORITHM

103

between mj and mk to(5.3)

where 'TJjk denotes a parameter and 0 ~ 'TJjk ~ 1. The parameter 'TJjk is set to 0.5 and is dynamically increased up to 1 during the iterative improvement step. If we would consider theminimum separation constraints for any pair of blocks, M (M - 1)/2 constraints are required
where M is the number of blocks. To solve the mathematical programming problem in a practical computation time, we therefore select the target sub-circuit Lmov = (M mov , N mov ) likethe algorithm presented in Chapter 2, and app1ly mathematical programming to Lmov. Then theconstraints of minimum separation can be represented as follows.

co:
(5.4)

NLP Formulation
Now, we formulate the topological arrangement problems with/without the minimum separation
constraints as the following nonlinear prograrnming problems.
[NLP without the minimum separation constraints]

L

minimizeO"i(w; + h;)(5.5)

VniENrnov

subject to

CIV1UCN2UCSuCD[NLP with the minimum separation constraints]

minimizeLO"i(w; + h;)(5.6)

VniENmovsubject to

CN1 U CN2 U CS u CD u CO

where O"i denotes a positive constant considering the criticality of net ni.
The brief description of phase 1 is as follows.

[ Phase 1: Timing-Driven Topological Arrangement(TV- T A) ]
Step
Step

1: RepeatCount = 1;
2: For all blocks, formulate the nonlinear programming problem without the minimum separation constraint (S.S) and obtain an initial topological arrangement by solving it by MINOSS.4;
RepeatStep 3: Select a target sub-circuit L: mov to be improved;
Step 4: For L mov , formulate the nonlinear programming problem with the minimum separation constraint (S.6) and solve it by MINOSS.4;
Step 5: Perform timing verification to N mov ;Step 6: RepeatCount = RepeatCount + 1;

104

CHAPTER 5. FLOORPLANNING, GLOBAL ROUTING AND PIN PSSIGNMENT

Until

both the maximum violation ratio and the overlapping ratio of blocks become less,than predetermined values, or RepeatCount > (preset value);o

Since the timing constraints are given for the source pin and a load pin of each net, in the selectionof a target sub-circuit of Step 3, we first select a net with the maximum violation ratio and then
expand the target sub-circuit based on the connectivity of the circuit.

5.2.4

Floorplanning with Topological Constraint Manipulation (Phase 2)

In phase 2, we determine the block attributes (e.g., absolute locations, dimensions for soft
blocks) so as to minimize the chip area. The output from phase 1 is a topological arrangement
optimized for timing and connectivity. In order to get a final legal floorplan, we must remove
all overlaps among blocks. This phase is performed without undoing any of the decisions of thefirst phase, i.e., topological proximity among blocks in the solution produced by the first phaseis maintained. We adopt a constraint-based approach to convert the topological arrangement
into a legal floorplan.
The topological arrangement is interpreted as a set of topological constraints. A topologicalconstraint set of blocks is given by two directed acyclic graphs (G H, G v ) : G H is' a horizontal
constraint graph and G v is a vertical constraint graph [130]. The node set of both IG Hand

Gv is exactly the set of blocks M. If (mi' mj), mi, mj E M, is an edge in G H, then mi is
to be placed to the left of mj' If (mi' mj), mi, mj E M, is an edge in G v , then mi is to beplaced below mj. Figure 5.2 shows an example of the topological arrangement of blocks andthe corresponding topological constraint set.
If (mil mj) appears inboth G Hand G v , then thisconstraint is said to be redundant.

In the exam-

ple, the constrains 1-t

2 in G H and G v are redundant.

4

3

To reduce thechip area, one of the redundant constraints need
to be deleted. A topologi-

Figure 5.2: A topological arrangement of 4 blocks and the corresponding topological constraint set.

cal constraint set is said tobe complete if a horizontal
or a vertical separation can be inferred from the constraint set for each pair of blocks. Otherwise,
the constraint set is said to be incomplete. A constraint set (G H, G v ) is said to be strongly complete if for any pair of blocks mi and mj, there is an edge connecting'them in either G H lOr G v or

5.2. TV-FPN: A TIMING-DRIVEN FLOORPLANNINGALGORITHM

105

both. A ftoorplan is defined to be legal if it has no overlaps, and the dimensions of blocks satisfy
the given bounds on aspect ratios. A legal ftoorplan of M is said to strongly respect a strongly
complete constraint set (G H, G v ), if for any pair of blocks mi and mj, they are not overlappedin the ftoorplan according to either their constraint in G H or their constraint in G v . An edge ein G H is said to be strongly redundant if (G H -- e) U G v = G H U G v . Strong redundancy of anedge in G v is similarly defined.
In phase 2, we consider the following ftoorplanning problem FTC (Floorplanning with Topological Constraint). Given a set of blocks, a strongly complete constraint set (G H, G v ), andbounds of aspect ratio for each soft block, the problem is to determine a legal ftoorplan, that is,
the absolute locations of the blocks and the dirnensions of the soft blocks, so as to minimize thechip area under the constraints such that the soft blocks must satisfy the given bounds on aspectratios and a ftoorplan must strongly respect the input topological constraint set.

The Floorplanning Algorithm FA
The proposed ftoorplan algorithm in phase 2, called FA, is an extension of the algorithm presented in [129,130], which we refer to as the conventional algorithm, or the algorithm VT, in
the following. The approach of the algorithm VT is to first derive a complete constraint set fromthe input relative placement and then to delete those redundant constraints on longest paths 3 on

G v and G H until no redundant edges in G v or G H exist. Next, soft blocks on longest paths on
G v and G H are reshaped for some constant times to further reduce the chip area. The algorithm

repeats both the steps until no improvement of the solution is achieved.
However, the algorithm VT has a few drawbacks. First, redundant constraints are deleted insome order, and once deleted, they will not be used again. Hence the ordering of the deletionof constraints may seriously affect the final results, and it is very difficult to avoid falling into
a local optimal. Second, only constraints and blocks on the longest path on the horizontal orvertical constraint graphs are deleted and reshaped. Thus, in the final result, there may exist
blocks without reshaping and there may be sorne redundant constraints left without removing.
Since the compaction result depends on the constraint graphs, removing the redundant edges
which are not on the longest paths may affect the compaction result so that a more compact
ftoorplan would be produced.
First, we hence propose some modification of the algorithm VT, which is used as a procedure in FA. In the algorithm VT, all soft blocks on the longest path in either the horizontal orvertical constraint graph are reshaped. In FA, we reshape all soft blocks on the longest path inboth horizontal and vertical constraint graphs to reduce the chip area for some constant times.
3The length of a path on G v is defined as the sum of the heights of blocks on the path. Let the longest path on
G v be a path with the maximum length. Similarly, the longest path on CHis defined.

106

CHAPTER 5. FLOORPLANNING, GLOBAL ROUTING AND PIN PSSIGN1UENTThe dimensions of each soft block on the selected longest path are reduced by a user-specified
dimension reduction factor. For soft blocks which are not on the selected longest path, we also
reshape the soft blocks with a user-specified dimension reduction factor to make their aspectratio close to one. In the following, the algorithm VT with the above modification is called theModified Vijayan and Tsay algorithm (the algorithm MVl).
Next, we describe a tentative insertion [61] of a constraint. In the algorithm VT, the orderingof constraints to be deleted may influence the final result. To search in a wide range of solution
space by changing the ordering of deletion of constraints, we modify the given constraint set
by tentatively inserting a dummy constraint Si, which is not contained in the original constraint
set (G H, G v ). This constraint is called a soft constraint. On the other hand, a ·non-redundantconstraint which is originally contained in the given constraint set (G H, G v ) is said to be a hardconstraint. This tentative insertion of a soft constraint Si is said to be tentative insertion. In
FA , we tentatively insert a soft constraint, and check whether one of the longest paths on theconstraint graphs G Hand G v is changed. If it is, we actually insert the soft constraint, update theconstraint set, and apply the algorithm MVT. If one of the longest paths on the constraint graphs
is changed, the ordering of the deletion of constraints is affected and may become different fromthe original ordering without tentative insertion. Therefore we may obtain a new floorplan which
is different from the floorplan that is produced without the tentative insertion and may have asmaller chip area.
In FA, we also check whether a directed cycle in the constraint graph exists or not, after inserting a soft constraint Si. If it exists, we don't insert the soft constraint Si. If a soft constraint is
successfully inserted, then we apply the algorithm MVT. Furthermore, each time MVT attempts
to delete a constraint, we check whether this constraint is soft or hard. If the constraint is a hardconstraint, then this removal is neglected. If MVT produces a floorplan, whose corresponding
constraint set still contains a soft constraint, we delete this constraint and apply the a]gorithm
MVT again. To improve the obtained solution, we reinsert not one deleted constraint but all
deleted constraints (mj, mi) relative to each block mi E M in the previous step and apply
MVT again to obtain a final result. By reinserting all the deleted constraints, the longest pathson the constraints graph of the best solution are largely changed. Thus we can have a chanceto escape a local optimal and expect that the chip area may become smaller because the search
space of FA is affected and changed by inserting deleted constraints.
The brief description of FA (phase 2) is as follows. During algorithm execution, JS4 keeps
the tentatively best solution. When updating the tentatively best solution, FA checks not only
the chip area but also timing violation. Thus, the final solution of phase 2 is assured to satisfy
the timing constraint.

5.2. TV-FPN: A TIMING-DRIVEN FLOORPLANNING ALGORITHM

107[Phase 2: Floorplanning with Topological Constraint Manipulation (FA)]Step 1: / * obtain an initial solution */Apply MVT to initial topological constraint :set S = (G H, Gv) in order to obtain an initial solution.
Let this solution be F. Compute the longest paths PH and pv on G Hand Gv, respectively.
Step 2: / * iterative improvement with tentativE~ insertion */For each constraint Si E S, do Steps 2.1 rv 2.5.
Step 2.1: / * check the effectiveness of a tentative insertion of soft constraint Si */Tentatively insert a soft constraint Si to the initial constraint set S, and compute longest
paths p~, p;,r on G~ and G;,r, respectively.
If p~ and p;,r are equal to PH and Pv, delete the soft constraint Si and continue the for loop.
Otherwise, let the updated constraint :set be S 1 = (G H, G v ) U {Si}.
Step 2.2: / * obtain a new solution */Apply MVT to the new constraint set 81. Let the obtained solution be Fl and the constraint
set corresponding to F 1 be S2.
Step 2.3: / * check the strongly respect plr operty */If S2 contains the tentatively inserted soft constraint Si, then delete Si from S2, i.e,
S2 ~ S2 - Si, because it is not contained the initial constraint set S, and apply MVT to
S2. Let the obtained result be Fl(The old Fl is discarded). Let the obtained constraint set
be S2(The old S2 is discarded).
Step 2.4: / * update the best solution */If area(Fl) < area(F) and there is no timing violation in Fl, then area(F) ~ area(F1),
F ~ F 1 and let the constraint set corresponding to the new F be S2.
Step 2.5: /* end for loop */Continue the for loop.
Step 3: /* optimize the best solution obtained in Step 2 */For the best solution obtained in Step 2, do Step 3.1.
Step 3.1: For each block mi, do steps 3.2 ''-' 3.5.
Step 3.2: Insert all deleted constraints (mj :, mi) relative to block mi into S2 of the best solution
F obtained in Step 2., i.e., S1 ~ S2 U {silsi = (mk' mi), mk E M, mi i mk}'
Step 3.3: Apply MVT to SI. Let the obtained solution be F2.
Step 3.4: If area(F2) < area(F) and there is no timing violation in F2, then area(F) +-area(F2) and F ~ F2.
Step 3.5: Continue thefor loop.

oStep 4: Output the best solution F.

The algorithm MVT runs in O(R(M + C») computation time where M and C are the numbers of blocks and constraints of the given constraint set S, respectively, and R is the maximum
number of iterations. The number of soft constraints is at most M(M - 1)/2. Therefore thetotal time complexity of FA is O(RM2(M + (7».

108

CHAPTER 5. FLOORPIANNING, GLOBAL ROUTING AND PIN ASSIGNMENT

5.3

TV-QRPA: A Timing-Driven Global Routing )~lgo­
rithm with Coarse Pin Assignment, Block Reshaping, andPositioning

After floorplanning, we obtain a legal floorplan, in which there is no overlaps and the dimensions of soft blocks satisfy the given bounds on aspect ratios. In this section, we discuss timingdriven global routing with pin assignment and propose a new global routing algorithm withcoarse pin assignment, block reshaping, and positioning [70,75]. The proposed algorithrn, called

TV-QRPA, performs global routing and coarse pin assignment simultaneously and optimizes
the positions and shapes of blocks based on the results of global routing and coarse pin assignment.

5.3.1

Problem Formulation

A set of blocks M consists of a set of hard blocks Mh and a set of soft blocks Ms. It is assumed
that a legal floorplan of blocks on the chip is given, but the exact positions of blocks are not fixed.
For some soft blocks, wires may pass through them depending on their internal design. We callthese wires feedthrough wires. The routing region is usually divided into a set of rectangularregions called channels and switchboxes [83]. A Channel segment CSj E C S is a rectangularrouting region between blocks or between a block and the chip boundary. Channel Ci E C: is a setof channel segments as defined by a channel determination algorithm, such as [18]. The routing
region can be usually represented by the channel intersection graph G = (V, E) [83, 111] (Fig.
5.3(a)). In order to represent the adjacency relation among channels and blocks and to estimate

G

B
B=
I

ms5

I

B

(a)G=(V,E)

Figure 5.3: The channel intersection graph and the horizontal channel positioning graph.

the chip size, two directed weighted graphs called vertical (resp. horzzontal) channel positioning

A TIMING-DRIVEN GLOBAL ROUTING A.LGORITHM

109

graphs G pv (resp. G ph ) [59] are created (Fig.5.3(b)). The vertices of G pv (G ph ) correspond tothe horizontal (vertical) edges of blocks and the chip, and the edges of G pv (G ph ) correspond tothe vertical (horizontal) edges of G and blocks. The chip width Wand the chip height H are
defined to be the lengths of the longest paths on G ph and G pv , respectively. The chip area A isdefined to be the product of the chip width and height, i.e., A = W x H.
Given a legal ftoorplan and a channel intersection graph G = (V, E), the global routing graphG r = (Yr., Er) is created. G r is an undirected graph defined as follows. Vertex set Yr. consists ofthree kinds of vertices corresponding to the vertices in G, the edges in G, and soft blocks Ms.
These vertices are called junction vertices, channel vertices, and block vertices, respectively.
Let V(Si), v(CSj), and V(msk) denote a
vertex corresponding to junction point Si,-.
"\

channel segment CSj, and soft block mSk,
respecti vel y.

/ ,~There are three types ofedges in Gr. For junction vertex V(Si)and channel vertex v( cs j), there is an-~

This edge is called a chan-nel edge and denoted by ee E Ee. For
channel vertex v(CSj) and block vertex
V(msk), there is an edge (v(CSj), V(msk))

I

AV'hanneledge-fieedthrough edge

"

v3
- -)

)

01.

f--

~
.... / r-......

v2

segment cs j is incident to the junction~ ssignment edge.........

",.... - - , LIedge (V(Si), v(CSj)) in G r if the channel
point Si.

l~

\ Vj

J

'\.

./

'V/
y

--

•
v4 •

..1

I

pins of net nj... a global routeof net nj-.

--

Figure 5.4: The global routing graph G r = (Yr., Er).

if the channel segment CSj is adjacent tothe soft block mSk. This edge is called an

assignment edge and denoted by ea E Ea. An edge corresponding to a set offeedthroughs of soft
block mSi E Ms is called afeedthrough edge and denoted by ef E E f . An assignment edge isused to represent a coarse pin assignment where coarse pin assignment is to determine on whichside of the block each pin of a net is assigned to. The weight for edge ex E Ex, x = {a, j, c}
is 3-tuple (C(e x ), P(e x ), D(e x )), where C(e x ), .P(ex ), and D(e x ) are the capacity, the number ofpassing wires and the length of the edge ex, respectively. For channel and feedthrough edges, thecapacity represents the maximum number of wires that are allowed to pass through the channelor the associated soft block. For assignment edge, the capacity is the number of pins that areallowed to assign to the associated boundary of the soft block. The length of an edge represents
the Manhattan distance between vertices of both ends of the edge. Figure 5.4 shows the global
routing graph G r corresponding to G of Fig. 5 . 3(a).
A set of pins of net nj E N are a subset of Yr.. Let Vnj be a set of vertices corresponding topins of net nj. For each pin of hard block mhi E;:: Mh, it is mapped to the closest channel vertex

110

CHAPTER 5. FLOORPIANNING, GLOBAL ROUTING AND PIN ASSIGNMENTof Gr depending on its position on the boundary of mh i . For each pin of soft block mSi EMs, it
is mapped to the corresponding block vertex V(msi). For net nj E N, a global route with coarse

pin assignment on G r is defined by a special Steiner tree T(nj), where T(nj) is a subgraph of
G r in which there is no two assignment edges connecting to a block vertex and a channel vertex
adjacent to the same boundary of the soft block. Global routing and coarse pin assignment for
all nets is to find a set of special Steiner trees T(N) = {T(nj)lnj EN}. The wire length L(nj)of net nj EN is defined to be the sum of the lengths of edges in T(nj). The estimated total wire
length W L is defined to be W L = L:njEN L(nj).
Similar to the ftoorplanning problem, a timing constraint of the source pin and a load pin jof net ni is specified by the maximum allowable propagation delay DelalloWij from the source tothe load. For the interconnection delay model, the Elmore delay model described in Section 3.2
is adopted and the delay delij from the source to the load j of net ni is estimated by equation(3.1). Consequently, if del ij ~ Delallowij' then the timing constraint of the net is satisfied.
Now we formulate the Timing-driven Global routing with Coarse pin assignment~ Blockreshaping and Positioning (TGCBP) problem as follows . Given a set of blocks M = MhUMs,
a netlist N, a ftoorplan and a set of timing constraints T as input, the TGCBP problem is todetermine the detailed positions of blocks, the shapes of soft blocks, and a set of global routes
T(N) such that the ordered pair of the area and the estimated total wire length (A, W L) is

minimized with respect to the lexicographical order (i.e., (AI, W L I ) ~ (A2' W L 2) if and only
if Al < A2 or AI =A2 and W L1 ~ W L 2) under the given timing and layout constraints (aspectratio of each soft block, relative positions of blocks, etc.).

5.3.2

Overview of the Algorithm TV-QRPA

The outline of TD-QRPA for the TGCBP problem is illustrated in a pseudo code fornl in Fig.
5.5. TD-QRPA is based on an iterative improvement paradigm and consists of three main
steps: initial routing, rip-up and rerouting, block reshaping, and positioning. To serve as aseed of the next iterations, the initial routing generates a complete, but possibly infeasible, setof global routes where "infeasible" means that Pee) may exceed G(e) for some edge e in Gr.
Then, the rip-up and rerouting, block reshaping, and positioning are performed in the mannerof simulated evolution [58] until a feasible solution is generated and the value of the objectivefunction is decreased as small as possible. At each iteration, we rip-up nets according to certain
probabilistic criteria and reroute them one at a time. The block reshaping and positioning adjust
the shapes of soft blocks and the positions of blocks to minimize the chip area considering theestimated channel density and the global routing result. These operations are repeated until thesolution is not improved.

A TIMING-DRIVEN GLOBAL ROUTING AlLGORITHM

Aleorithm for TGCBP
Initialization( );InitialRouting( );Evaluate&Selection();S = Shest = ljJ;

111/* initial routing *//* initialize solution */p = 0;/* initialize counter */repeat
ReRouting();
Evaluate&Selection();LongestPath();BlockReshaping();
Positioning();
if( cost(S) < cost( Shest) ) then
Shest = S;/* save best solution */p = 0;else

p = p + 1;
endif
until p > R;
return( Shest);/* increment counter *//* termination criterion *//* report best solution */Figure 5.5: The outline of TV-QRPA.

5.3.3

Initial Routing

To be served as a seed for the rip-up and rerouting process, this step generates global routes withcoarse pin assignment under the given timing constraints. Since the set of assignment edges inT(nj) specifies a coarse assignment of soft block pins, determining T(nj) means to performe

global routing and coarse pin assignment for net ni simultaneously. Among all special Steiner
trees, the one with minimal weight is called the special Steiner minimal tree (SSMT). The SSMT
corresponds to the optimal solution of global routing for a net. It has been shown that the SSMT
problem without the timing constraint is NP-hard [135] and we therefore present a heuristic
algorithm based on [76].
We consider the complete undirected distance graph Gl(nj) = CVz(nj), El(nj» for net nj
constructed from G r and Vnj in such a way that Vz(nj) = Vnj and, for every edge {Vi, Vk} E
El(nj), the weight of the edge {Vi, Vk} is set equal to the distance of the shortest path from Vi to
Vk in G r , that is, the sum of the length of edges ei E Er on the path. Note that, for each edge

in Gl(nj), there exists a corresponding shortest path in Gr. Considering the timing constraintof the net ni, the initial routing first constructs a spanning tree Tl(nj) on Gl(nj) by phase 1 of
the algorithm considering the trade-off between the shortest path and the minimum spanning
trees used in Chapter 3. Then it constructs a subgraph of G r by replacing each edge in the tree

112

CHAPTER 5. FLOORPLANNING, GLOBAL ROUTING AND PIN ASSIG"TMENT

Tz(nj) by its corresponding shortest path in Gr. Usually the resulting subgraph is a Steiner tree

spanning all the pins of the net, but in some cases there may exist cycles in the subgraph. Hencethe redundant edges are removed from the subgraph and a special Steiner tree T(nj) of the net
nj is obtained.

To minimize the chip area, we need to consider the routing congestion of Gr. We therefore
generate a set of special Steiner trees which consider the timing constraint of the net, and thenselect the best tree in the set of trees. To achieve this, we find the K j - 1 other shortest paths
for each edges in Tz(nj), and construct K;Vnj -11 other trees by replacing each edge in 11(nj) by
its corresponding set of shortest paths in Gr where K j denotes a positive constant defined by
the user. Then we select the tree which satisfies the timing constraint and has minimurn routing
cost, that is, produces the minimum chip area. For example shown in Figure 5.6, for net nj in
Fig.5.6(a), we construct the undirected distance graph Gl(nj) in Fig.5.6(b) and find a spanning
tree Tl(nj). Then we find other shortest paths for each edges in Tl(nj). In this example, we findtwo shortest paths between V4 and VI in Figs.5.6(c) and (d). In this way, we find the paths forthe other edges in Tl(nj) and construct a set of Steiner trees in Figs.5.6(e) and (f).

"'{

\Vi

\ V]_

/ ,r\ '~

r'\

--

l/7

/ ,T\

V "v3

,,--

'\

V2

f--)

-

}

v2
J

./

tilllv4 s~urct.

'V/

).l

I

l'

(a) the global routing graph G r and Vnj

"
. -t
- r--

~

I

\ Vj

'~
v3
.,.. // , r\\.

\,,_1-1v2y/...... -1-1

V

'\

v2

'\

---1 r - - )

v3

}
)

/

'V/ .-JJ ~ v4

Y'~....

,/ , f\

/

I

-

"'{

\ vi

~

v4

(c) a shortest path between V4 and vi

"'{

J

V
./

~

(b) undirected distance graph G[ (nj),-:7 "V3

"\

I

~

I

-

(d) another path between v4 and Vi(e) a global routing tree

"V/
)'

j

I

11'4

-

(f) another gLobal routing tree

Figure 5.6: An example of the AS5;\;tT(nj).

A TIMING-DRIVEN GLOBAL ROUTING A.LGORITHM

113

The proposed steiner tree construction algorithm, called AS5;\ltT(nj), to find a global routewith coarse pin assignment considering the tirrting constraint for nj E N is as follows.
[Algorithm AS5;\ItT(nj)]
Step 1: Set the cost of each assignment edge ea E Er which is not connected to a vertex in VnJ.
to infinite. Construct the complete undirected distance graph Gl(nj) = (Vl(nj), El(nj))
from G r and Vnj"
Step 2: Find a spanning tree Tl(nj) of Gl(nj) considering the timing constraint by the algorithm
which combines Prim's minimum spanning tree algorithm and Dijkstra's shortest path tree
algorithm [2].
Step 3: For each edge in Tl(nj), find K j - 1 other shortest paths.
Step 4: For each combination of the shortest paths of each edges, perform the following Steps
IVn· -11
4.1-4.3 and construct K j Jother trees.
Step 4.1: Construct the subgraph Gs(n)) of G r by replacing each edge in Tl(nj) by its
corresponding shortest path in Gr.
Step 4.2: Find the minimal spanning tree Ts(nj) of Gs(nj).
Step 4.3: Construct a special Steiner tree T(nj) by deleting edges in Ts(nj), if necessary,so that all the leaves in T(nj) are in Vnj"
Step 5: Evaluate all the trees produced in St€~P 4 based on the routing congestion, and selectthe best tree which satisfies the timing constraint and has the minimum routing cost.

0

In Steps 1 and 3, we use the shortest path algorithm [59] based on the A *-algorithm [96].
The AS5;\ItT(nj) needs to be as fast as possible because it is repeatedly used in the initialrouting and rerouting steps. AS5;\ItT(nj) is very efficient, and from experiments, we showedthat AS5;\ltT(nj) finds the shortest path about 70% faster than Dijkstra's ordinary shortest path
algorithm. Moreover, to generate K j - 1 other shortest paths for each net in Step 3, we can apply
a modified version of Dreyfus's algorithm [81] for finding the K j shortest paths between two
vertices on Gr. In the current implementation,. we temporary change the cost of Er and apply
the shortest path algorithm based on the A *-algorithm K j - 1 times.
In Step 5, we first check the timing constraint for all the trees produced in Step 4, thenevaluate the trees which satisfy the timing constraint based on the following evaluation functioneval(T(nj)), and select a tree which has the minimum value of eval(T(nj)).

114

CHAPTER 5. FLOORPLANNING, GLOBAL ROUTING AND PIN ASSIGl'lMENT
(5.7)

+
where

: the longest path length on G pv or G ph corresponding to the channel edge ei E Ec.
: the longest path length on Gpv or Gph which passes the channel vertex corresponding to the channel edge ei E Ec on G pv or G ph •Xl, X2, X3 : positive constants4

The time complexity of AS~T(nj) is as follows. Step 1 is done in O(IVnj 1111;. 12) time,
Step 2 is done in O(IVnj I 2 ) time, Step 3 is done in O(KjlVnj - 11111;.12) time, Step 4 is done
. O(Kj)IVn o-111 11;.)
12 tIme,.
.In 0 (KlVno-lllv.l·0 veral I speakIng,.
In
and Step 5 .
IS donej)r ) tIme.
Step
4 dominates the computation time. Hence, AS~T(nj) has a worst case time complexIVn - 111 11;.)12 where K denotes a constant defined by the user.
..'i From our experity of O(Kj)0jiments, it is observed that the running time of the shortest path algorithm based on the A *algorithm is proportional to 111;.1, and therefore the complexity of AS~T(nj) can be reduced
IVn o- 11
to O(Kj) 111;.1).
In the initial routing, all the nets are first sorted in ascending order according to half theperimeter length of the smallest bounding rectangles, each of which contains all the vertices
corresponding to the pins of a respective net. Next, for each net nj in the order obtained theabove, T(nj) is found by the algorithm AS~T(nj).

5.3.4

Rip-up and Rerouting

The rip-up and rerouting resolves both the timing and routing capacity violations introduced by
the block reshaping and positioning in the previous step. At each iteration, a some number ofnets are ripped-up according to certain probabilistic criteria, and then are rerouted one at a time
according to another set of criteria. Some existing violations of routing capacity is resolved andsome new ones may be introduced. This iterative process continues until a feasible solution withthe smallest cost is obtained.
To choose the set of nets to be ripped-up, we use the simulated evolution technique [58].
This is very suitable to our problem, in which the shapes and positions of blocks are changed
during iterations. To measure the badness of each net in the current configuration, that is, howmuch it is not suited in the configuration, we define the evaluation function badness(nj) for net
4In our implementation. let XI = 5000, X2 = 5000, X3 = 5000.
SIn the current implementation, K j is set to a value which satisfies K;Vnj-11 ::; 64.

A TIMING-DRIVEN GLOBAL ROUTING ALGORITHM

115

nj E N as follows.
badness(nj)actual wire length of nj)
lower bound of wire length of nj+ b x number of violations of channel edges= ax(+ c x number of violations of assignment and feedthrough edges
+ dx

L

P(ei)

eiET(nj)nEa C(ei)+ e x number of timing violations.

(5.8)

where a, b, c, and e denote constants. It is obvious that the timing violations are not allowed. We
do not prefer the long wires and want to minim~ze the chip area as much as possible. Although,the capacity violations on the channel edges can be resolved by the block reshaping and positioning steps later, the capacity violations on the assignment and feedthrough edges as well as
the timing violations may not be resolved by them completely. Hence the constants a, b, c, d ande are set in such a way that the timing violations and the capacity violations of assignment andfeedthrough edges will dominate the badness of a net while allowing the wire length to affectthe badness. Currently we set as a = 100, b = 50, c = 100, d = 10 and e = 1000.
Next we determine which nets are to be ripped-up and rerouted in a stochastic way. We
normalize badness(nj) between 0.0 and 1.0 and compare this value against a random number
uniformly distributed in the range between 0.1 to 0.9. For each net, if its normalized badness
times the parameter Select is greater than the generated random number, it is ripped up. The
ripped-up nets are sequentially rerouted by JlSStVtT(nj) according to their badness values,
highest badness values are ranked first. To shorten the computation time, in the ripped-up step,
we re-use the set of the trees obtained in the initial routing step, evaluate all the trees again basedon both the current congestion of G r and the dimensions of blocks, and select the best tree.

5.3.5

Block Reshaping and Positioning

In the block reshaping and positioning steps, we adjust the shapes and positions of blocks so as
to minimize the chip area. These steps are done by considering the channel density and global
routing information. First, we compute the length of the longest paths Lpv and Lph on Gpv
and G ph , respectively. Obviously, Lpv and Lph determine the height and width of the chip. To
minimize the chip area, we pick up a soft block which lies on the longest paths, and increase its
width or height by some value so as to reduce one of the longest path lengths. Then we obtain
the positions of blocks by applying the longest path algorithm [1]. These operations are repeateduntil the chip area is not reduced.

116

CHAPTER 5. FLOORPLANNING, GLOBAL ROUTING AND PIN ASSIGNMENT

5.4

ACPAI : An Optimal Channel Pin Assignment A~lgo­
rithm

5.4.1

Channel Pin Assignment Problem

In this subsection, we give a formulation of the channel pin assignment (CPA) problem and somebasic definitions. We assume that there is a virtual grid superimposed on the channel, and pins
can only be placed on grid points on the top and bottom sides of the channel. All the horizontal
wire segments are assigned to be on one layer and all the vertical wire segments on the otherlayer. Vias are used to connect wire segments on different layers.
Let L be the length of the channel, that is, the number of grid points on either side of thechannel. These grid points may be numbered 1 through L from left to right. A vertical grid line
is called a column. The top and the bottom sides of the channel are respectively partitioned into
sets of intervals. Let T = {Tl ,T2, .. ,Ty} (resp. B = {B 1 ,B2,· .. ,BB}) be a set of intervals on
the top (resp. bottom) side of the channel and are labeled T1,T2 ,··· ,Ty (resp. B I ,B2,··· ,BB)
from left to right. A set of pins assigned on the top (resp. bottom) side of the channel is denoted by TOP = {tI,t 2,··· ,ts}, S = ITOPI (respectively, BOTTOM={b l ,b2,··· ,btl, t =IBOTTOMI ). Let N ={ nl ,n2,· .. ,nn}, N = INI, be a net list of the channel, where nj is a setof pins belonging to net j, 1 ::; j ::; n.
Definition 5.1

For any interval x E TuB, let left(x) (resp. right(x)) be the numberof the leftmost (resp. rightmost) grid point in the interval x and left(Ty +l ) = left(BB+I)= right(Ty +l ) = right(BB+I) = L + 1 for convenience. For each interval x, let int(x) =[left(x), right(x)], where [a, b] represents the closed interval from a to b.

0

Definition 5.2 A pair of intervals T j and Bk is called overlapped if (left(Tj) < left(Bk)) /\(left(Bk) < right(Tj)) or (left(Bk) < left(Tj )) /\ (left(Tj) < right(Bk)). The overlapping

interval of a pair of intervals T j and Bb is denoted by overlap(Tj , Bk). A set of subchannels

SC is defined as a set of overlap(Tj , B k), 1 ::; j ::; T, 1 ::; k ::; B. They are labeled
SCI, SC2, ... ,SC[ according to the increasing order of their left(sCi), where l is the number ofsubchannels. Similarly, left(sCi), right(sCi), and int(sCi) are also defined.

0

Definition 5.3 For any subchannel SCi(= overlap(Tj , B k)) ESC, let short i be a interval x(= T j or B k) in which right(x) = right(sCi). Let longi be a interval x (= T j or B k) in whichright(sCi) < right(x). For any subchannel SCi, if columns of the rightmost grid points in T j

and Bk coincide, then let Bk be longi.

0

For example, in Fig. 5.7, the top and bottom sides of the channel are partitioned into T = 3,
B = 4 intervals, respectively, and there are six subchannels SCI rv S~. int(TI) = [1,6]" int(B 1)5.4. ACPAI : AN OPTIMAL CHANNEL PlN ASSIGNMENT ALGORITHM

117=[1,4], and int(T2) = [7,11]. SCI = overlap(T), Bd = [1,4], SC2 = overlap(T), B 2) = [5,6], andSC3 = overlap(T2, B 2) = [7, 11].

+

I---Tl
{1 ,4,5,6, 7,8}t I t 2 t 3 t.

T2

+

JI

T3

{13,14,16,24,25} {8,11, 12, 15, 16, 18, 19,20,22}

t5 t 6 t7 t 8t 9 t 10 t I~ t 12 t 13 t 14 t IS t 16 t 17 t 18 t 19 t ~I·• · · ~ I· . , . • • • . - . • I·
• • I· • • ..
I
I
~I

I
I
I

LEFT

\~,~1~'~}

SCI

I
I

:SC 2 :

I
I

SC 3

I
I
I

I
I
I

:SC 4 : SC s :

RIGHT

SC 6

=overlap(TJ ,B J J\~,~g:J~:

I
I
I
25}
I
I
I
I
I
I
I
I
I
I
4-~-"~'II,,
I~· ·~I· .1 • • • • • 1 • • 1• • • 1• • • • 1
bl b2 b3 b. bs b6 ~ b8 b9 blO hll bl2 bl3 bl • bls bl6 bl7 bl8 bl9 b20{2,5,6,9} {3,4,13, 14, 15,20,21 ,23,24} {12, 17, 19} {3,9,1 0,22}

1--8 1 JIE

82

liE 83-+-8 4---1

Figure 5.7: A channel and subchannels.

We assume there are pseudo-pins to which nets exiting from the left or right side of thechannel are to be connected, and denote these two sets of nets for pseudo-pins on the left andright sides of the channel by LEFT and RIG1{T, respectively.
Definition 5.4 For any interval x E TuB, let: pins(x) be a set of pins assigned to the interval

x and let nets(x) be a multiset of nets for pins assigned to the interval x where net(p) is the net
containing pin p.

0

In the following, for convenience, we denote net ni by the net number i. In Fig. 5.7,
for each interval x, nets(x) is shown as {it, i 2 , · · · , i x }. For example, for the interval T 1,

nets(T))={1,4,5, 6, 7,8}.
Definition 5.5 Let l(nk) be the leftmost pin position of net nk E N, and let r(nk) be therightmost pin position of net nk. Let the density at a column i, denoted D i , be Di = 1{nk Il(nk) ~i ~ r(nk), l(nk) =I r(nk)} I. Then the channel density in the channel, denoted D, is defined to

be D = maxl~i~L D i .

0Definition 5.6 Let the estimated wire length of net nb denoted LN(nk), be LN(nk) =r(nk) - l(nk) . Then the estimated total wire length T L in the channel is defined to be
TL= ~nkENLN(nk)'0

In the following, if some two pins t j , bk E ni, tj E TOP, bk E BOTTOM are assigned tothe same column, the pin pair tj and bk is said to be aligned.

CHAPTER 5. FLOORPLANNING, GLOBAL ROUTING AND PIN ASSIGNMENT

118

Now we formulate the channel pin assignment (CPA) problem as follows. Given sets ofintervals, T and B, on the top and bottom sides of the channel and a netlist N of the channel,
the problem is to determine a pin assignment so as to minimize the ordered pair (D, TL) withrespect to the lexicographical order, where (D', T L') < (D", T L") if and only if D' < D", orD' = D" and T L' ::; T L".

5.4.2

A Linear Time Optimal Algorithm

In this subsection, we present an optimal algorithm for an important special case of the CPA
problem, where, for each net, there is at most one pin within each interval in the channel. We
call it the problem CPAl. This constraint is reasonable in practice because usually there is at
most one pin of the same net on each side of a block in the top down hierarchical building blocklayout design. We say that a channel pin assignment is optimal if (D, T L) is minimized among
all the possible channel pin assignments.
In the problem CPAl, for each net nk E N, there is at most one pin within each interval(seeFig. 5.7). We introduce the net classes proposed in Ref. [23] to classify each net njlc in any
subchannel se.;, ESC. Note that, in Ref. [23], the net class was originally proposed to classify
nets for channel routing, where both the top and bottom sides of a channel consist of single

intervals (i.e., T = B = 1 ). We extend the net class of channel with one interval to the channel
with multiple intervals. Figure 5.8 illustrates the net classes. In each subchannel SCi ESC,
each net has at most two pins and at most two exits, since interval shorti and longi have at
most one pin belonging to some net. We classify a set of nets, which are corresponding tose.;, (= overlap(Tj , B k )) and in nets(shorti ) U nets(longi) and to which positions of pins are
not yet assigned, into one of the eight classes as shown in Fig. 5.8 depending on where nk has
pins on T j and/or Bk and has exits on the left and/or right side. We also call two LSi(resp. RSi )

I
~

=l

Pass by(PBi)

Left Single(LSi)

C

;r X

Left pair(LPi)=r--4

Right pair(RPi)Right Single(RSi)Balanced Single(BSi);! I

Balanced pair(BPi)Internal pair(IPi)Figure 5.8: A classification of nets in the subchannel se.;,.

~
MLSi

-r-1
~=
MRSi

5.4. ACPA1 : AN OPTIMAL CHANNEL PIN ASSIGNMENT ALGORITHM

Tj= [ongi

Tj

119= Longi

Bk = shortj

Figure S.9: Pin assignment in a subchannel.

nets a pair of matched LSi nets (M LSi nets)(resp. M RSi nets), if one net has a pinin the
top interval T j and the other net has a pin in the bottom interval Bk in the subchannel SCi. For
example, in Fig.S.7, in the subchannel SCI, short l = B I , longi = T I, overlap(TI , B 1) = [1,4],
LSI = {I, 2, 7}, RS I = {4, 8, 9}, IPI = {S}, LP1 = {6}, and RP1 = BS 1 = BPI = cP. In

the following, for the ease of description, for each subchannel SCi, we denote the set of nets innets(longJ or nets(shorti ) belonging to class Ii by Ii ( where Ii represents P B i , LSi, LPi ,etc.).
Now we present an optimal algorithm for CPA1, called ACPA1 [69,7S]. The basic idea of
our algorithm is the following: Scanning a subchannel SCi E

se from left to right, we classify

nets belonging to the intervals corresponding to the current subchannel (i.e., longi and shorti )into eight classes, assign positions to pins of I ~i nets so that they are aligned as many as possible,
and then assign positions to remaining pins de]pending on their classes such that nets going out
from the left side are assigned from left and nets going out from the right side are assigned fromright(Fig. S.9).
In the following, we assume that lejt(Tj) i lejt(B k ), for all j, k, 1 < j :::; T, 1 < k :::; B.
This assumption is reasonable since if lejt(Tj) = lejt(B k ), for some j, k, 1 < j:::; T, 1 < k :::;
B, then we can divide the channel into two paIts at the column left(Tj), and can process them

independently. We also need not consider all the P Bi nets in the assignment of a subchannel
SCi since there is no pin in the P Bi nets to be assigned in the subchannel SCi. Moreover, they do

not affect the optimal pin assignment for other nets. Therefore, in the following, we ignore the
P Bi nets in each subchannel SCi. The number of nets belonging to Ii is denoted by IIil, the setof nets belonging to Ii in the interval x is denoted by Ii (x ), and the number of columns in thesubchannel SCi is denoted by Iscil.
In ACPA1 , Assign_lmg(Num, NetClass, Side) (resp. Assign_rmg(Num, NetClass, Side))

is a procedure to assign pins of Num nets in NetClass one by one, one net per column from theleftmost (resp. rightmost) available ~rid point in int(sci) (resp. int(shorti)) of the Side of thecurrent subchannel SCi. If Side is both sides, then two pins of each net in NetClass on the top

120

CHAPTER 5. FLOORPLANNING, GLOBAL ROUTING AND PIN ASSIGNMENT

and bottom sides of the subchannel SCi are assigned to the leftmost (resp. rightmost) available
grid points on the same column in int(sCi). Assign_ag(Num,NetClass,Side) is also a procedure
to assign pins of Num nets in NetClass one by one, from the Wbitrary available ~rid point inint(sCi) in the Side of the current subchannel SCi.

Our channel pin assignment algorithm(ACPA1 ) for the problem CPA! is as follows.
[ Algorithm ACPAl ]Foreach subchannel SCi E se from left to right do
Step 1 Classify each net nk E nets(shorti) U nets(longi), to which no pin position has
been assigned in the current intervals shorti and longi, into one of the eight classes;
Step 2 If II Pil < ISCiI thenStep 2.1 If 1M LSil i 0 thenAssign_lmg(IM LSil, M LSi, both sides);1* Assign pins in LSi and LPi *1
Step 2.2 If IMLSil + ILPil + IIPil < ISCiI thenAssign_lmg(ILPil, LPi , both sides);Assign_lmg(lsCiI- (1M LSil + IL~I + II Pi/), LSi, interval containing LSi nets);
AssignJmg(IIPil, IPi , both sides);1* Assign pins in RSi and RPi *1
Step 2.2.1 If ISCiI :S (IMLSi U LSil + ILPil + IIPil + IRPi/) thenAssign_rmg(1 RPi I, RPi , both sides);Assign_rmg(IRPi(shorti) U RSi(shorti)l, RPi(shorti) U RSi(shorti) ,shorti);else 1* case of ISCiI > (1M LSi U LSi I + ILPil + IIPil + IRPi/) *1
Assign_rmg(lsCiI-(IM LSiULSil+ILPil+IIPil+ IRPi /), RSi(shorti)" shorti);
Assign_rmg(IRPil, RPi, both sides);Assign_rmg(IRSi(shorti)1 - ISCi/, RSi(shorti), shorti);

else 1* case of IMLSil + ILPil + IIPil ~ ISCiI *1
AssignJmg(lsCiI - II Pil - 1M LSil, LPi , both sides);AssignJmg(IIPil, IPi , both sides);Assign_rmg(IRPi(shorti) U RSi(shorti)l, RPi(shorti) U RSi(shorti), shorti);

else 1* case of IIPil ~ ISCiI *1
AssignJmg(lsCiI, IPi , both sides);Assign_rmg(II Pil - ISCiI, I Pi(shorti), shorti);
Assign_rmg(IRPi(shortd U RSi(shorti)l, RPi(shorti) U RSi(shorti), shorti);

1* Interchange pins in LPi and RSi or RPi *1
Step 3 If there exist pins in LPk(shorti)(l :S k :S i) that were assigned any grid point to
the right of the grid point to which pins in RSi(shorti) U RPi(shorti) are assigned, theninterchange one-by-one the pin in LPk(shorti) that was assigned to the rightmost grid pointwith the pin in RSi(shorti) U RPi(shorti) that was assigned to the leftmost grid point.

5.4. ACPA1 : AN OPTIMAL CHANNEL PIN ASSIGNMENT ALGORITHM.1

f---Tl(104,5,6,78)

liE
T2
liE
T3
(13,14,16,24,25) (8,11 12,15,16,18,19,20,22)

f---T1
1 6 7 5 (4,8)+

T2(13,14,16,24,25)

II,

121

·1

T3
(8,11,12,15,16,18,19,20,22)

I· • • • • .,. • • • .,. • • • .:. • • ·1:::

{1, 2, 6, 7 '15,21,24)'
,

LEFT

,
,
,

, (3, 10, 11,, 17,18,23,
, 25)

SCI

,

SC 2 ,

SC 3,, SC 4,SC s ,

RIGHT

SC s

:
:
'
I· (2,5,6,9)• • • (304,13,14,15,20,21,23,24)• .'. • • • .'. ·1·(12,17,19)· ·1·(3,9,10,22)· · ·1
I--Bl +
B2
+ 8 --+-8 ----134

2 6 9 5I--Bl(a) an input{3,4,13,14,15,20,21 ,23,24)

II,

II·

T3
(12,8,16,18,19,11,22)

II
L

8C 5

,, ,

,

1 6 7 5 8 4 24 13 14 16 25 15 20 8 12 19 16 22 18 11

~

8C 6

I

~

U

,,:1 ,,
, ,

'C'_

lct"'

''"'1

I'"''"' I

,

8 3

,
IT ,
I 11 :I

I!
I

2 6 9 5 21 4 24 13 14 23 3 15 20 (12,17,19)

B2(3,9,10,22)

II· 8 3--+-8 4----1(c) LS4={8,16j, RS4={3, 11,12, 18,19,22,23j,

2 6 9 5 21

I--Sl

II,

I

' -,...
,, I
I

1 ''"' I

:

I

I

I

:,I ~

I

I

I

+

(3,9,10,22)(b) LS1={l,2,7j, RS1={4,8,9j, IP1={5j,LP1={6j, RP1=BS1=BP1= 0

f---TlliET2
1 6 7 5 8 4 24 13 14 16 25 1520

I--B1

(12,17,19)

II, 8 3 --+-8 4----1

B2

"
v

I

'!>

,

,,...
IV

I

,
II
I

r.

I
I
4 24 13 14 23 3 15 20 17 1219 9 22 3 1082

II· B3--+-S 4----1(d) the final result

1P4={20j, LP4={15j, RP4=BS4=BP4= 0

Figure 5.10: An example of ACPA! .

Endforeach
Step 5 Assign_rmg(IRSz(longl)l, RSl(longl), longz);
Assign_ag(IBPz U BSt!, BPz U BSz, both side);o

Example 5.1 In Figure 5.10, an example of execution of ACPA1 is shown. Figure 5.10(a)shows an input for the algorithm. First, nets in nets(T]) and nets(Bd are classified into oneof the eight classes in Fig. 5.8. Next, those pins are assigned depending on their classes. In
Fig. 5.10(b), two pins of net 4 and net 8 in nets(T]), are not assigned since shortl = B 1•
They will be assigned in the next processing of SC2. After the processing of SC3, the processingof SC4 will start. Note that the classification of nets in nets(short4) and nets(long4) of SC4 isdone by checking both classes of the previous subchannel SC3 and configurations of nets in the

122

CHAPTER 5. FLOORPLANNING, GLOBAL ROUTING AND PIN ASSIGNMENT

new scanned interval T 3. In the processing of SC4 (Fig. 5.10(c)), two pins of net 3 andl net 23
belonging to RS4 in short4 (= B 2 ) are assigned one-by-one from the rightmost available grid
point. But the pin of net 15 belonging to LP4 in Short4 (= B 2 ) is assigned to the grid point to
the right of pins of RS4. Applying Step.3 of the algorithm, the pin of net 23 is interchanged
with the pin of net 15. Repeat these steps until the right side of the channel, and we obtain an
optimal pin assignment as th~ result of ACPA1 (Fig. 5.10(d)).

5.4.3

Optimality of the Algorithm

In this subsection, we discuss the correctness and optimality of ACPAI . First, we show threelemmas, from which we derive the main theorem later. The detailed proofs of lell1Jnas andtheorem can be found in Appendix D.
Lemma 5.1 There is no optimal assignment 1T, in which in any interval x a pin of a net inLSi(x) is assigned to the right of a pin of a net in RSi(x) U RPi(x). Similarly, there is no

optimal assignment 1T, in which in any interval x a pin of a net in RSi(x) is assigned to the leftof a pin of a net in LSi(x) U LPi(x).

0Lemma 5.2 Any assignment 1T in which all the pins are assigned so as to minimize the estimatedwire length T L can be transformed into an assignment 1T' in which for any subchannel SCi, all thepins of min(lsci!, II Pi!) nets in I Pi are aligned and all the pins are assigned so as to rninimize
the estimated wire length T L.

0

Lemma 5.3 Any assignment 1T in which for any subchannel SCi, all the pins of min(lscil, II Pil)
nets in I Pi are aligned and all the pins are assigned so as to minimize the estimated wire length

T L is an optimal assignment.

0

Based on the above lemmas we show the following main theorem.
Theorem 5.1 The algorithm ACPAI produces an optimal pin assignment of the problem CPA1

in Oem) computation time, where m is the number of pins.

5.5

Experimental Studies

5.5.1

Experimental Results of TV-FPN

0

In this subsection, we show experimental results of TV - FPN presented in Section 5.2.

TV- FPN has been implemented in C language on a Ultra COMPstation 170 running lOn Solaris5.5. EXPERIMENTAL STUDIES

123

2.5, and tested for MCNC benchmark data. Table 5.1 shows the experimental data and "ami33a","ami33b", and "ami33c" were generated by changing positions of I/O pads of "ami33". In theexperiment, all blocks were regarded as soft blocks. In the table, "#cons" is the number of nets
for which timing constraints were given.

Table 5.1: Experimental data of floorplanning.

I

I #riets I #blocks I #DO pads I #cons I

data
amI
amI

11

c

U if
1

1

data
ami33
ami33aami33bami33c

71276

o

0.97

0.13

6592.8To show the effectiveness of phase 1 of 7~D-FPN, we compared the results of phase 1of TD-FPN with TD-FPN without considering the timing constraints. In the experiment,
we set the permissible violation ratio and the overlapping ratio of blocks to 0.80 and 0.2, respectively. Table 5.2 shows the results of phase 1 and "without" and "with" mean the proposed
algorithms without and with considering the timing constraints, respectively. "Length" is theestimated total wire length, that is, the sum of half the perimeter length of the bounding box foreach net. The term "#vios" is the number of violated timing constraints and "Max vio" is the
maximum violation ratio for the given timing constraints, that is, maxdelij / Delallowij' "Overlap
ratio" is the ratio of the sum of the overlapped area of all the blocks to the total area of blocks.
"Time" is the running time by a Ultra COMPstation 170 (seconds).
From the results in Table 5.2, while TD-~'FPN without considering the timing constraints
violates some timing constraints, TD-FPN can produce the comparable results without any
timing violations. As for the running time, since we need to take the minimum separation constraints as well as the timing constraints into consideration, the running time of TD-FPN islonger than that of the standard cell placement algorithm POPINS presented in Chapter 2.
However, the number of blocks in the building block layout is generally small and therefore wethink this running time is still considered practical. Figure 5.11 shows the placement result ofphase 1 of TD-FPN for "ami33b".

124 ' CHAPTER 5. FLOORPLANNING, GLOBAL ROUTING AND PIN ASSIGNMENT

o

D

o

o

Figure 5.11: The global placement result of TD-FPN for "ami33b".

Table 5.3: Results of phase 2 of TD-FPN.

data

I Algo I

ami33

cony
pro

Area

I Length I #VlO I Max VlO I 'nme(sec) I

ami33aami33bami33ccony
pro1514513

69478

o

0.95

145.0

Next, in Table 5.3, we show the floorplanning results obtained by applying the detailed
placement step (phase 2) to the results of phase 1 in Table 5.2. For the results of phase 1 of

TD - FPN, we performed FA (phase 2 of TD-FPN) in Section 5.2.4. On the other hand,for the results of phase 1 of TD-FPN without timing constraints, we applied the algorithm
VT [130]. In Table 5.3, "pro" means TD-FPN and "conv" denotes the conventional algorithm
which does not consider the timing constraints in the global placement step and applies thealgorithm VT in the detailed placement step. "Area" denotes the area of the minimum rectangle
enclosing all the blocks. From the results, TD-FPN can successfully produce results without
any timing violations within a practical computation time. Since phase 1 is able to generate
the global placements that satisfy the given timing constrains and have few overlapped area, FA can produce the floorplanning without timing violations by maintaining topological proximity
between blocks in the solution produced by phase 1. Figure 5.12 shows the floorplanning resultof TD-FPN for "ami33b".

5.5. EXPERIMENTAL STUDIES

125

i=l

0

0

0

0

~

0

0
0

r--,...--

oJ

0

0

0

olD

0
0

0

r---

0
0

0

C-

GL o J
D

r----

0
0

0

I

0

0

0

I

I

0

I

0

0

I

Figure 5.12: The floorplanning result of the proposed algorithm for "ami33b".

Finally, in Table 5.4, we show the global routing results obtained by applying global routing to the floorplanning results in Table 5.2. For the ftoorplanning results of TD-FPN, weapplied TD-QRPA presented in Section 5.3, on the other hand, for those of the conventionalalgorithm, we applied TD-QRPA without considering the timing constraints, called QRPA. In
Table 5.4, "pro" and "conv" mean the global routing results of the above cases with and without
considering the timing constraints, respectively. For all the floorplanning results of TD - FPN,

TD-QRPA can produce the results without any timing violations and therefore the simulation
results in Table 5.4 have demonstrated the effectiveness of TD-FPN.

Table 5.4: Global routing results of the floorplanning results in Table 5.2.

I

data

I Algo I

Area[01466457

I Length I #VlO I Max VIO I TIme(sec) I

ami33
ami33aami33b)ami33c5.5.2

111349

0

0.98

4.4

Experimental Results of Phast~ 2 of TV-FPN'

To evaluate phase 2(FA) of TD- FPN, presented in Section 5.2, we compared phase 2 of F

A with the original Vijayan and Tsay algorithnl. The algorithms have been implemented in C
language on a Ultra COMPstation running on SunOS 5.5, and tested three MCNC benchmark

126

CHAPTER 5. FLOORPLANNING, GLOBAL ROUTING AND PIN ASSIGNMENT

data and two modified benchmark data. In Table 5.5, the characteristics of benchmark data andthe modified benchmark data are shown. The data "ami33a" and "ami33b" are obtained bychanging the positions of I/O pads of "ami33". In the experiment, the timing constraints were
not given and the maximum aspect ratio of each soft block was set to 1/3.

data

#nets

Table 5.5: Results of FA and the algorithm VT.
LH#IJO II #teons.

#bloeks
soft hard

II UH

Uv

area

alg.

area

VI'

27.42
23.28
13.24
11.66
1.93
1.56
2.30
1.90

xerox

203

10

0

2

39

36

19.35

FA

hp

83

11

0

45

23

55

8.83

FA

ami33

123

33

0

42

402

385

1.16

FA

ami33a

123

33

0

42

429

349

1.16

FA

ami33b

123

33

0

42

419

413

1.16

FA

I ave.

data

II

VT

VT

VT

VT

VT I

II !A

II

[%]
~
0.1

tIme
[sec]

1.00
0.85
1.7 15.0
1.00
0.1
0.88
1.8 12.0
1.00
3.0
0.81 1316.9 19.0
2.6
1.00
0.83 1663.0 17.0
1.9~
1.00
3.1
1.74 0.88 1164.8 12.0
9.37 11.00 I
1.~ .j=/8.03 0.85
653 .6 ~Table 5.6: Results of FA and the algorithm VT with hard blocks.
#teons.
#bloeks
LB
tlme~
#IJO
area ratio
alg.
#nets
sott

hard

l:iH

l:iv

area

[sec]

VT

xerox

203

9

1

2

39

36

19.35

FA

hp

83

9

2

45

23

55

8.83

FA

ami33

123

29

4

42

402

385

1.16

FA

ami33a

123

29

4

42

429

349

1.16

FA

ami33b

123

29

4

42

419

413

1.16

FA

I ave.

ratio

II

VI'

VT
VT
VT

II

27.57
24.63
13.24
11.32
1.97
1.57
2.32
1.91
1.9~

1.89

1.00
0.89
1.00
0.85
1.00
0.80
1.00
0.82
1.00
0.95

0.1
1.5
0.1
1.9
2.6
1285.6
2.6
764.9
3.3
1160.4

[%]
-

11.0
-

15.0
-

20.0
-

18.0
-

5.0

jll ~:i~ I b:~~ I 64~.~ 113.8 I

Table 5.5 shows the experimental results of FA and the algorithm VT. In the table, "'#tcons."is the number of topological constraints generated in the initial placement step and "ratio" is theratio of the chip area of FA to that of the algorithm VT [130]. "LB area" is the lower bound ofchip area, which is the total area of all blocks and "imp." is the improvement degree of FA to
the algorithm VT. From Table 5.5, the results of FA are 15.0% (ave.) and 19.0% (max.) better
than those of the algorithm VT, respectively. As for the computation time, as the nlllmber ofblocks increases, it becomes about 350 times longer than the algorithm VT. However, we think
this running time is still considered practical.
We also experimented the algorithms with data in which there 'are hard blocks. Table 5.6

5.5. EXPERIMENTAL STUDIES

127

shows the results of the both algorithms. From the results, FA produces 13.8% (ave.) and
20.0% (max.) better than the algorithm VT, respectively. The above results show that FA is
also effective for the data which contain hard blocks. In conclusion, the experimental results
have demonstrated that phase 2 of TV-FPJ,J is effective to produce a good floorplan in apractical computation time.

5.5.3

Experimental Results of TV--QRPA

We have implemented the proposed timing-driven global routing algorithm, TV-QRPA, presented in Section 5.3 in C language on a Ultra COMPstation 170 workstation running on Solaris
2.5, and performed some experiments. Table 5.7 shows the experimental data. Three real circuits (datal, data2, and data3) and two artificial circuits (data4 and dataS) were used as theexperimental data. Data4 was generated by combining data 1 and data2 and by modifying positions of blocks. Similarly, dataS was made by combining two sets of data3 and by changing
positions of blocks. For datal and data2, we rnanually generated the three different floorplans
with a layout editor. In Table 5.7, "#cons" is the number of timing constraints.
To the best of our knowledge, no algorithms integrating the global routing, pin assignment,
positioning, and block reshaping steps have been ever known. Consequently, to show the effectiveness of TV-QRPA, we compared results of TV-QRPA with the algorithm without
considering the timing constraints, called QR1?A, which have been proposed in [59].
Table 5.7: Experimental data for global routing with pin assignment.

I Data I #soft blocks I #hard blocks I #nets I #cons I
datal
data2
data3
data4
dataS

8
-14
13
22
28

6

0
3
6
0

2302
2302
2362
4404
4404

2302
2302
2306
4404
4404

Table 5.8 shows the experimental results. In Table 5.8, "without" and "with" mean thealgorithms without and with considering the tinting constraints, respectively. "Chip area" is the
product of the estimated chip width and height on G pv and G ph and "Length" is also the estimatedtotal wire length, that is, the sum of the lengths of global routes for all nets in Gr. The term"#vios" is the number of violated timing constraints and "Max vio" is the maximum violation
ratio for the given tinling constraints. "Time'" is the running time by a Ultra COMPstation
170 (seconds). From the results in Table 5.8, while QRPA violates some timing constraints,

TV-QRPA can produce the comparable results without any timing violations.

128

CHAPTER 5. FLOORPLANNING, GLOBAL ROUTING AND PIN ASSIG1VMENT

datalbdatalcdata2adata2bdata2c
data3
data4
dataS

DATA
datal adatal bdata1cdata2adata2bdata2c
data3
data4
dataS

x
32803(131 x 257)

1.04

693.2

1.01

o

0.99

1094.05.5. EXPERIMENTAL STUDIES

129

Next, Tables 5.9 and 5.10 show the results for the timing constraints which are looser thanthat of Table 5.8. In Table 5.10, "tight" and "loose" mean the results for the tight and loose
timing constraints, respectively. From the results, TV-QRPA can also produce the comparable
results without any timing violations. Moreover, TV-QRPA can obtain better results than the
results for the tight timing constraints. The running time of TV-QRPA with considering thetiming constraints is a little longer than QRPA, still it is fast. The above simulation results havedemonstrated the effectiveness of TV-QRPA.

data1adata1bdata1cdata2adata2bdata2c
data3
data4
dataS

5.5.4

x
32803(131 x 257)

1.04

693.2

1.01

o

0.99

1094.0Experimental Results of AC7=~l

We have implemented the channel pin assiglllment algorithm (ACPAI ) in Section 5.3 in C
language on a SPARCserverlOOO workstation (135 MIPS) running on Solaris 2.3. To show theeffectiveness of ACPA 1 , we have tested it on several instances of the channel routing problem,
including Deutsch's famous difficult example (diff) [28]. The characteristics of the test data andthe results are shown in Table 5.11, where the number of tracks (#T), the total wire length (WL),
and the number of vias (#vias) are obtained frona the channel routing results given by the greedy
channel router [37]. For the difficult example (diff), we partitioned the top side and the bottomside of the channel into intervals so that each interval does not include more than one pins of thesame net. Since no algorithm has previously been proposed for the CPA 1 problem, we compared
our algorithm with the random assignment and the pin assignment algorithm based on simulated
annealing proposed in the Ref. [84].

130

CHAPTER 5. FLOORPLANNING, GLOBAL ROUTING AND PIN ASSIGArMENT

datal

100

13/13

96

177.5
0.01

data2

100

10/10

70

335.8
0.01

data3

100

121 9

85

260.8
0.01

data4

180

20118

155

546.0
0.01

diff

174

18/20

72

5066
481.4
(3 19 20 2223
4922
402
0.01
(l)Random assignment, (2)Simulated annealing [84], (3)The proposed ACPA1 .

From the experimental results, to the random assignment, ACPAI achieves up to 25%
reduction of the channel density and 23% reduction of the estimated total wire length. Comparedwith the Ref. [84]'s algorithm, we obtain up to 3.8% reduction of the channel density and 13%
reduction of the estimated total wire length. After channel routing, to the algorithm of Ref. [84],ACPAI also gets up to 16% reduction of the number of tracks, 10.8% reduction of the total
wire length, and 18 % reduction of the number of vias. Experimental results also show that the
proposed algorithm ACPAI runs in a short computation time.

5.5.5

Experimental Results of TV-yRPA and ACPAI

Finally, we performed experiments by applying both TD-QRPA presented in Section 5.3 and

ACPAI presented in Section 5.4. In the experiments, we did not give the timing constraints.
We compared results of the proposed algorithm with two other algorithms. Algorithm 1 isto design all blocks as hard blocks in advance. In this case, pin positions and block shapes are
fixed during the global routing stage, and the positioning stage is executed at the end of them.
Algorithm 2 assigns pin positions before the global routing stage as proposed in [139], andexecutes rip-up & rerouting, block reshaping, and positioning in the same way as the proposed
algorithm. We also compared the proposed algorithm with two other algorithms, Algorithms
3 and 4, which are modification of the proposed algorithm. In Algorithm 3, the rip-up andrerouting stage is excluded from our algorithm. In Algorithm 4, the block reshaping stage is not
executed at each iteration, but the positioning stage is executed once at the end of the algorithm
to compact the chip area.
Table 5.12 shows the experimental results. Five real circuits are 'used as inputs of the exper-5.5. EXPERIMENTAL STUDIES

circuit 1

8

6

230

circuit 2

14

o

230

circuit 3

14

o

230

circuit 4

14

0

230

circuit 5133

22362 5903 3
4
ours

131

x
24226 (151 x 160)
23682 (152x 156)
23934 (152x 157)
23222 (151 x 153)

0.739
0.723
0.720
0.708

158.7
143.4
143.7
148.3

0.545
0.493
0.494
0.510

15.5
20.2
22.8
18.5

iments. Circuits 2, 3 and 4 are made from the same real circuit, but placed differently. For the
proposed algorithm and Algorithms 3 and 4, in order to determine exact pin positions nets on
the boundaries of blocks facing each channel, we applied ACPA1 to each channel after phase
1. "Chip area" in Table 5.12 is the product of estimated chip width and height on C pv and C phafter channel pin assignment and "Length" is the estimated total wire length, that is, the sum of
the horizontal length of all the nets in all the channels.
From the experimental results, the chip area is reduced by 7.0% (ave.), 14.2%(max) and thetotal wire length is reduced by 11.4% (ave.), 16.6%(max) compared with the algorithm proposedin [139](Algorithm 2). For example, for circuit 3, we obtain 26.7% reduction of the chip area(A)and 43.0% reduction of the total wire length(W L) compared with Algorithm 1. Furthermore,
we get 14.2% reduction of A and 16.6% reduction of W L for Algorithm 3. From these experimental results, the proposed algorithm can successfully reduce both the chip area and thetotal wire length efficiently. Furthermore, the rip-up and rerouting step with block reshaping
and positioning effectively improves the results.

132

CHAPTER 5. FLOORPIANNING, GLOBAL ROUTING AND PIN ASSIG1VMENT

5.6

Concluding Remarks

In this chapter, the layout problems for the building block layout have been discussed, suchas floorplanning, pin assignment, and global routing. First, a timing-driven floorplanning algorithm TV- FPN has been proposed which determines the positions of blocks and shapesof soft blocks so as to minimize the chip area. Nex~ a timing-driven global routing algorithm

Tv-gnPA has been proposed which simultaneously performs coarse pin assignment, block
reshaping, and positioning. As opposed to conventional approaches, we have combined pin assignment and global routing problems into one problem. Tv-gnPA can also adjust the shapes
and positions of soft blocks. To the best of our knowledge, no algorithms integrating these four
steps have been ever known. Finally, channel pin assignment has been discussed and an optimal algorithm ACPA! for the channel pin assignment problem CPA! has been proposed which
minimizes both the channel density and total wire length in the channel and runs in a linear timeon the number of pins in the channel. Experimental results have demonstrated that the proposed
algorithms are effective in regard to the chip area and total wire length minimization under the
given timing constraints.
Finally, we discuss about future work. In the case of floorplanning, a reduction of the computation time of TV-FPN and an extension of TV-FPN to optimize the dimensions ofblocks in the first phase are interesting topics. For global routing with pin assignment, while

Tv-gnPA has been originally devised to be applied to the two-layer routing technology, it canalso handle the three-layer routing model, in which terminals are placed on a layer of the blockboundary. However, if terminals are not placed on the boundary of a block, the pin assignment
problem is quite different from the problem discussed in this chapter, and Tv-gnp..'A cannot
be applied to it directly. An extension of Tv-gnPA to treat the above problem is a future
subject. As regards channel pin assignment, an extension of ACPA! to three-layer nlodel design, in which pins on the top/bottom side of the channel could be on Metal! or Metal 3, is aninteresting topic.

Chapter 6
Conclusion
In this dissertation, timing-driven placement and routing in VLSI layout design have been discussed and timing-driven placement and routing algorithms have been proposed for both standard cell and building block layout designs. In the proposed algorithms, the Elmore delay modelis adopted as the interconnection delay model.
In Chapter 2, a path-based timing-driven placement algorithm POPINS for standard celllayout has been proposed. The Elmore delay model is adopted as the interconnection delay
model and the timing constraints are assumed to be given for pairs of pins of internal cells.
Incorporating hierarchical partitioning and nonlinear programming into the algorithm, a goodplacement can be obtained in a practical computation time. We have also extended the algorithm
to a parallel algorithm, called PAR-POPIN~3, running on a shard memory multi-processor
workstation and have shown the effectiveness of the algorithm through simulation experiments.
A timing-driven global routing algorithm T1J-gR for standard cell layout has been proposed
in Chapter 3 considering channel density mininuzation. Although most of the conventional algorithms are net-based algorithms, the proposed algorithm is a path-based algorithm, which
explicitly considers the timing constraint between pairs of pins and minimizes the channel density under the given timing constraints. We have also discussed an extension of the proposed
algorithm to take over-the-cell channel routing into account. Finally, simulations have demonstrated that the algorithm is effective for both the interconnection delay minimization and thechannel density minimization.
Chapter 4 has discussed the over-the-cell(OTC) channel routing for standard cell layout.
First, two standard cell models have been proposed; the Boundary Terminal Model with Nonuniform OTC routing capacity (BTM-N) and the A.rbitrary Terminal Model with Obstacles on arbitrary position (ATM-O). In order to effectivelly utilize the cell models, new three-layer OTC
routing algorithms have been developed. For the BTM-N, the mixed planar and H-V OTC
routing algorithm 3VR-BTM-N has been presented and the multi-channel routing algorithm

3VR-ATM-O has been proposed for the ATM-·O based on 0-1 integer linear programnling. An
extension of the algorithm for the ATM-O to take the timing constraints into consideration has
been also discussed. Simulation experiments have shown that the cell models and the algorithms
are both effective in reducing the chip area.
133

134

CHAPTER 6. CONCLllSION

Chapter 5 has dealt with ftoorplanning, pin assignment and global routing for building blocklayout. For ftoorplanning, a timing-driven ftoorplanning algorithm TV-FPN has been proposed based on nonlinear programming and topological constraint manipulation. As regards
pin assignment and global routing, a timing-driven global routing algorithm TV-9n12A withcoarse pin assignment, block reshaping, and positioning has been presented. An optimal algorithm ACPA! has been developed for channel pin assignment which minimizes both thechannel density and total wire length in the channel. Finally, the effectiveness of the proposed
algorithms have been demonstrated in simulation experiments.
In this dissertation, we adopt the Elmore delay model in the proposed placement and global
routing algorithms, with which we can precisely take both interconnection wire resistance andcapacitance into account in the estimation of the interconnection delay. Since in deep submicronrules (e.g. 0.35 or 0.25/Lm) where the interconnection wire resistance dominates much more thanthe previous design rules, adopting the Elmore delay model is important to layout a high performance integrated circuit in short turn-around-time using the proposed algorithms. Moreover,in the case of the standard cell layout design, using both the proposed standard cell models andthe proposed timing-driven global/detailed routing algorithms for over-the-cell routing, it makes
possible to design a high density and a high performance ASIC in shorter turn-around-tirne. For
the building block layout design, as opposed to conventional approaches, since we sirnultaneously consider pin assignment, global routing, and block reshaping in the proposed algorithm,
we can obtain a high quality layout for the VLSI chip more easily. Furthermore, using the proposed timing-driven ftoorplanning and global routing algorithms, in which we have adopted theidea proposed in the algorithms for the standard cell layout, we can expect to design a highdensity and a high performance VLSI chip in shorter design time.
In future, the performance of integrated circuits will be becoming higher and the operational
speed and the clock frequency of VLSI circuits faster. The complexity of VLSI circuits will bealso progressed more and more. Thus, we should develop the new layout algorithm, with which
we can perform placement and routing in a short computation time and obtain a good quality
layout satisfying the given timing constraints. We would like to say that the proposed algorithms
in this dissertation are the solutions for the demands mentioned above. With the proposed algorithms, we can reduce the complexity of the design automation of high performance integrated
circuits and hence reduce the their design cost. In particular, since an ASIC is usually designed
for some particular application and is not mass-produced, it is usually designed by an electronicengineer who may not be a professional for designing the VLSI chips. From the results of thisdissertation, even such a non-professional engineer can easily design the VLSI chips. This contributes to the reduction of the design cost and the resolution of lack of the professional chip
design engineers.

135
Finally, we briefly discuss about future research for the VLSI layout design of the highperformance circuits.
(1) Sub-Quarter Micron Semi-Conductor Technology

In sub-quarter micron rule(e.g. 0.25 - 0.18J1.m), in order to improve overall packing densityof the chip, the wiring pitch will be less than 1.0jLm. On the other hand, to maintain a small interconnection resistance, the vertical dimension of wire is not scaled down the same order of thehorizontal dimension. Consequently, fringing capacitance, which is a capacitance between thefringe of wire and the ground plane, and crosstalk effects, which is caused by a coupling capacitance among parallel lines, become dominated than the previous design rules. Since crosstalkeffects may cause significant further delays or glitches in circuits, traditional critical path analysis may give incorrect results. Therefore it is necessary to consider the more precise delay
calculation model in sub-quarter micron rule. For the effect of the fringing capacitance, since it
can be assumed that the fringing capacitance of wire is proportional to the wire length, we can
extend the proposed algorithms to treat the effect by taking it into account in the calculation of
the interconnection capacitance of the Elmore delay. In the case of the crosstalk delay which is
caused by the cross coupling associated with electro-magnetic interference among the lines, it
depends on the input signal pattern of the adjacent lines unlike the gate delay or the interconnection delay. Therefore, to precisely estimate the crosstalk delay, it is required to develop thedelay calculation model considering the input signal patterns among the lines. Moreover, to reduce the crosstalk effects, we need to consider the coupling capacitance among parallel lines in
global and detailed routings. The development of the delay calculation model and the extensionof the proposed algorithms are interesting future work.
In sub-quarter micron semi-conductor technologies, the multi-layer routing more than four
layers will be realized. In this multi-layer routing, if all the routing layers are routed by thesame wiring pitch, the interconnection resistance is increased and the operational speed of theintegrated circuit can not be improved any more. One solution of the above issue is that thewiring pitches of the upper routing layers are not reduced like the lower routing layers. In
this situation, the wiring resistance and capacitance par unit length and the wiring pitch varyin each layer, and thus it is required to extend the proposed algorithms so as to treat physicalparameters which may be different for respective wiring layers. In particular, in the proposed
placementlftoorplanning algorithms, we do not determine the routing topology of each net andhence it is difficult to estimate the precise delay of the net. We therefore need to extend the
proposed placementlfloorplanning algorithms so as to determine the layer assignment of nets
during placementlftoorplanning. This extension of the algorithms is also future research.
(2) High Performance Chip
One approach to' reduce the interconnection delay and ' increase the operational clock fre-

136

CHAPTER 6. CONCLUSION

quency of the circuit is buffer(repeater) insertion and the other is wire sizing which varies thewire width and pitch so as to reduce the interconnection delay. As regards the buffer insertion
approach, it is necessary to determine the suitable positions and sizes of buffers considering thedriving strength of each buffer and the interconnection capacitance of each net. Since the sizesof buffers are usually larger than those of the ordinary cells, in order to reduce the dead space on
the chip, it is required to insert buffers in the placement step by estimating the interconnection
delay of each net. In the wire sizing approach, if a wire is widen, the wire resistance decreases
but the wire capacitance increases. Therefore we should develop the routing algorithm which
considers the above trade-off. The development of these algorithms is also an interesting topic.
(3)Ultra Large Scale Integration(ULSI) Chip
In sub-quarter micron rule, the complexity of the integrated circuits will be progressed tothe order of ten millions of gates. To design such ULSI circuits, we no longer treat the wholecircuit in the layout design in a time and need to introduce hierarchical design methodology.
Moreover, to reduce the computation time of the layout algorithms, distributed and parallel
processing, which have been considered in this dissertation, should be considered. On the other
hand, to reduce the problem sizes of layout problems, a clustering approach is also promising.
The development of a clustering algorithm considering the timing constraints and the integrationof the clustering algorithm to the placement and routing algorithms are also future work.

Appendix A
Details of the Timing-Driven Pllacement Algorithm in
Chapter 2
A.I

Definitions of the Terminal and Wire Gains

We explain a terminal gain which considers terminal positions of nets. We consider a vertical(resp. horizontal) partitioning shown in Fig. A.l. Let M mi be a set of cells connecting with cellmi E M and let Xi, Xj (resp. Yi, Yj) denote x-coordinates (resp. y-coordinate) of cell mi E M

and mj E Mmi, respectively. Let region_width (resp. region-.height) denote the width (resp.
height) of the region to be partitioned. We define the cost concerned with terminal positions ofnets connecting with the cell mi as,
termi =L

mj EMmiI~j x.~(k i j / Ch+regzon_wz tI)) ,(A. 1)

where k ij = 1 if mj is placed at the same sideagainst the cutline in which mi is placed, otherwise k ij = -1. For example in Fig. A.l,cells placed in the left part of the cut line havepositive costs, and cells placed in the right partof the cut line have negative costs. Then, thegain considering the terminal positions, called
terminal gain, is defined as(A.2)
where termi and term~ denote the costs before

Figure A.l: An example of a vertical partition-

and after moving cell mi, respectively. For

mg.

example in Fig.A.2, termi = (l + 1/2 + 1/3) - (l/2 + 1/3 + 1/3 + 1/3) = 1/3, term~ = (l/2 +1/2 + 1/2 + 1) - (l/2 + 1/3 + 1/4) = 17/12, and gtermi = 13/12. From the gain gtermi' we canrealize the similar effect of the terminal propagation method [32] in short computation time.
Next, we define the gain, called wire gain, to consider the wire length of nets. Since theminimization of the cut size doesn't always miniimize the total wire length of nets, we explicitly
consider the total wire length during partitioning. Let wirei be the total wire length of nets
137

138 APPENDIX A. DETAILS OF THE TIMING-DRIVEN PLACEMENT ALGORITHM

1

-112

-112

-113

1

112

-114

termi=(1 +113 +112)-(112+113 +113+113)=113

termi'=(I+II2+112+112)-(112+1I3+114)=17112(a) before moving cell mi(b) after moving cell mi

Figure A.2: An example of the terminal gain.

connecting with cell mi. In other words, wirei is the sum of half the perimeters of the enclosing
minimum rectangle of all the pins of nets connecting with the cell mi. Then we define the wire
gain as,(A.3)
where wirei and wire~ denote the total wire length before and after moving cell mi, respectively.

A.2

Details of the Parallel Algorithm PAR-POPINS

A.2.t

Introducing Parallelism to Phase t

In introducing parallelism to phase 1, at the upper levels, we perform a bi-partitioning by several

processors to reduce the computation time, and at the lower levels, partitionings of each region at
a level are done in parallel (Fig. 2.10). Since the bi-partitioning algorithm used in the proposedparallel algorithm is same as the algorithm described in Section 2.3, in the following, we will
explain the details of parallel processing of the upper levels and lower levels, respectively.

Partitioning at the Upper Levels of Hierarchy
At the top level of hierarchy, we have to handle the entire circuit. To reduce the computation
time, we perform a bi-partitioning by using several processors in parallel. In general, it is difficult to directly make parallel a partitioning algorithm, say the FM algorithm, based on groupmigration because it consists of a set of sequential operations intrinsically. In the proposed algorithm, we therefore divide the entire set of cells into the sets of cells and perform independently apartitioning of each set of cells. As shown in Fig. 2.11, we first assign every cell to each processor based on an initial partition(Fig.2.11(c)). Next, each processor Pi performs independently
the partitioning of cells assigned to it with the bi-partitioning algonthm mentioned in Section

A.2. DETAILS OF THE PARALLELALGOJUTHM PAR-POPINS

139

2.3(Fig.2.11(d)). To obtain a bi-partition of whole cells, we merge the partitioning results ofeach processors(Fig.2.11(e)). Then, we reassign cells to each processor based on the current
bi-partition. These operations are iteratively performed while the bi-partition is improved.
However, if cells which are connected to each other are assigned to different processors,
the partitioning gain of those cells cannot be calculated correctly. Then, we introduce a set ofseparator cells that divide the entire set of cells into a few sets of cells, which have no connection among them. Since the separator cells are not assigned to any processors, the positions ofseparator cells are fixed while each processor is performing the partitioning(Fig.2.11(d)). Thus,
to improve the partition, after each processor performed the partitioning, the partitioning of theset of separator cells are done with the same partitioning algorithm (Fig.2.11(e)). However, themovement of cells which improves the entire partition are difficult to realize because there aremany fixed cells that cannot be moved in the partitioning. We hence add some cells to the setof the separator cells in the breadth-first-search manner from the set of the separator cells, thenthe partitioning algorithm is applied to the set of the separator cells and added cells. Introducing
separator cells makes it possible to calculate the cut, terminal, and wire gains precisely. However, it is impossible to calculate the timing gain correctly, because the calculation of timing
gain needs to calculate a delay of a path, and it is difficult to separate cells in each path with noconnection. The terminal and wire gains are nolt useful for the top level partition, because there
is only one partitioning region, i.e., whole chip area, and these gains are used to consider theoutside of partitioning region. Hence, in the upper levels partitioning, the partitioning is hence
performed considering mainly the cut gain, and other gains are only used as auxiliary gains.
In the assignment of cells to processors(Fig.2.11(c)), we need to consider the following threepoints. First, we need to assign cells connected to each other, to the same processor to minimize
the number of separator cells as much as possible. Second, the number of cells assigned toeach processor needs to be same as much as possible, because the difference of computation
time of partitioning performed by each processor causes the degradation of the performance ofparallel processing. Finally, an initial partition of each set of assigned cells needs to be balanced,
because the cell assignment is performed based on an initial partition or the partition obtainedby the last iteration, and the partition can be used effectively for the next iteration. We therefore
perform a cell assignment to processors in the following way. First, a pair of seed cells for allprocessors, which has a connection and crosses the cut line, is randomly selected and is assigned
to a processor. Next, expand each set of cells assigned to a processor by adding cells one by
one considering the balance of each set of cells. The added cell should have large connectivity,
which is the number of connections to the present set of cells assigned to each processor. If theadded cell is connected to a cell which has already been assigned to other processor then the cellbecomes a separator cell and is added to the set of separator cells. These operations are repeated

140

APPENDIX A. DETAILS OF THE TIMING-DRIVEN PLACEMENT ALGOR1THM

until all cells have been added to some sets of cells assigned to a processor or a set of separator
cells.

Partitioning at the Lower Levels of Hierarchy
At the lower levels of hierarchy, there are many partitioning regions, and we have to performpartitionings of many circuits with the small number of cells(Fig.2.10(c)). Therefore we apply
independently the partitioning algorithm described in Section 2.3 to perform partitioning of eachregion at a level.
Figure A.3 shows an example ofprocessing flow which obtains a 4 by
4 partitioning from a 2 by 2 partitioning. In order to obtain high efficiency in parallel processing, updating the cell positions to calcu-

1~~ ~~I- -11-11- ~;::;#~~
II(a) after 2 by 2
partitioning

Proc.3(h) after 4 by 4

Proc.lProc.4

Proc.3 Proc.4
(c)

(b)

late timing, the terminal and wire
gains is perfonned asynchronously
by each processor during moving
cells in the partitioning algorithm.

partitioning

Proc.2(g)

Proc.lProc.2(f)Proc.2(e)

To reduce errors of the cell gain
caused by moving cells by other processors, we perform the partitioning, in which the directions of the

Figure A.3: The processing flow of phase 1 of PAR-POPINS.

cut lines of the adjacent two partitioning regions are different from each other as shown in Figs. A.3 (b) and (c). The influenceof errors is decreased in the lower levels because the partitioning regions are apart from eachother. Hence, we change the parameters of gain (a, /3", and 8) dynamically during the hierarchy of partitioning so that first, the cut gain is dominant, and the influence of the other gains
are increasing as the partitioning hierarchy goes down to lower levels. In addition to the above
consideration, the bi-partitioning algorithm is hierarchically applied by shifting the part.itioning
region as shown in Fig. A.3 (d)I'...J(g). Since the precise cell positions are already detemlined af-

ter the 4 x 4 partitioning as shown in Fig. A.3 (c), the terminal and wire gains can be accurately
calculated and a good initial placement can be obtained.

A.2.2

Introducing Parallelism to Phase 2

As seen in Section 2.3, in phase 2, iterative improvement based on NLP is performed to improve
an initial placement obtained by phase 1. The parallel processing is introduced by by solving theA.2. DETAILS OF THE PARALLELALGOJ,UTHM PAR-POPINS141

NLP problems for each target subcircuit by seve~ral processors in parallel (Fig. 2.12). However,
if each target subcircuit has connections with the other target subcircuits and is improved concurrently, errors of wire length estimation and path delay estimation may be occurred. Therefore
constrained paths which are contained several target subcircuits are divided into subpaths by introducing separator cells as shown in Fig. 2.12, and we construct a set of target subcircuits thathave no direct connection with other target subcircuits, which in time can be improved concurrently. The divided paths are independently considered in the formulation of the NLP problemof each subcircuit.
The selection algorithm of a target subcircuit is basically same as the sequential algorithm.
We moreover consider the following thing. To improve the target subcircuits in parallel, we
select a constrained path so as to have no connection with any other subcircuits improved byother processors. As increasing the number of cells, it may become easy because the placement
area is larger.
The parallel algorithm of phase 2 consists of one master process and several slave processes,
and improves a placement iteratively. At each iteration, the master process first performs thetiming verification and calculates violation ratios for all the constrained circuits. Next, the masterprocess constructs a target subcircuit and forks a slave process. Each slave process formulatesa NLP problem and solves it by MINOS5.4 and sends the result of NLP problem back to themaster process. These operations are repeated until the maximum violation ratio becomes lessthan a pre-determined value or the iteration count reaches to some preset value. The outline of
the algorithm of phase 2 is shown below.
[phase 2: Iterative Improvement Based on NLP (parallel Version)]
Master process:Step 1: Perfonn timing verification to all constrained circuits, and RepeatCount = 1.
RepeatStep 2: Select a target subcircuit Lmo'V to be improved and fork a slave process.
Step 3: If there is a slave process which has tenninated, then receive a result from theslave process;Step 4: Perfonn the timing verification of the constrained circuits CL T which Mmov U
CM T -:/0;
Step 5: If it cannot increase a slave process any more, then wait for computation of slave
processes;
Step 6: RepeatCount = RepeatCount + 1;
Until
the maximum violation ratio becomes less than a pre-determined value
or RepeatCount > (preset value);
Step 7: Wait for the termination of all slave processes, receive results from the slave processes,
and exit;
Slave process:Step

1: Find all constrained paths which pass cells in Mmov;

142

APPENDIX A. DETAILS OF THE TIMING-DRIVEN PLACEMENT ALGORITHM

Step

2: Formulate the nonlinear programming problem and solve it by MINOS5.4;

Step

3: Send the result back to the master process;

A.2.3

Introducing Parallelism to Phase 3

Phase 3 assigns cells that have been distributed on the chip in phase 2 to cell rows. As shown in
Fig. 2.13, parallel processing is introduced to the row assignments of some consecutive groupsof cells to each processor, and each linear assignment is independently performed by each processor.
First, to independently solve a set of linear assignment problems by each processor, weequally assign each processor Pj , (j = 1, 2, ... , P) to a set of consecutive cell rows, {R'llp x k+ 1 'R!jsXk+2' . " , R!jsX(k+l)}' (k= 0,1", " P - 1).

Next, a set of pairs (9i, Si), i = 1,2"", R are constructed where Si is a set of slots inwhich all the cells in 9i are assigned and 9i is a set of groups of cells, respectively. For each 9i,
capacities a(9i) of 9i is defined as,~Aa(9i) =_lA2

(if i = ~ x k + 1, (k = 0, 1, ... , P - 1) )R(else if i = p x k, (k = 1,2" .. ,P) )

(AA)

A

(otherwise)
where P and R are the number of processors and cell rows, respectively. We construct ceJll group

9i as follows. All cells are sorted by their y-coordinates, and the first group is constructed byadding cells in the sorting order until the sum of the area of cells is equal to the capacity of thefirst group. Similarly, the remaining groups are constructed. Then, each cell group is assigned
to the corresponding processor as follows. Groups 91, ... , 9IIp are assigned to processor PI,
groups 9 ll+l
, ... ,92 11 are assigned to processor P2 , and so on.
pp
Next, cells in 9i are assigned to slots in Ri by the timing-driven linear assignment algorithm described in Section 2.3 in parallel, that is, cells in the groups 91, 9 ~+1' ••• ,9 !js(P--l)+1 areassigned to slots in SI, S !js+1l ... ,S!js(P-l)+l concurrently. Since, in large circuits, cell groups
which are assigned concurrently are apart from each other, the influence of other processors in
the cost matrix calculation can be reduced. Because a(9i) ~ A, if cells in 9i which are notassigned to slots of the cell row Ri but slots of Ri+l' then the cells assigned to the cell rows Ri+l
are added to the next group 9i+l and reassigned in the next linear assignment problem.
After the row assignment of the y-direction, the row assignment of the x-direction is performed in the similar way of the y-direction. These operations are iteratively perfomled until
there is no more improvement of placement or RepeatCount is reached to some preset value, andwe obtain a final placement. At each iteration, we change cell groups assigned to processors byshifting the group boundaries as shown in Fig. 2.14, If we use the same sets of cell groups, thenA.3. DETAILS OF EXPERIMENTAL RESULTS

143

the cells in the last cell group of the set of cell group for processor Pi will be only placed at thesame cell row in the later loops. Consequently, these cells cannot be moved to the next cell row
and this degrades the quality of the placement. The outline of the timing-driven row assignment
algorithm is as follows.
[Phase 3 : The Parallel Row Assignment Algorithm]
Step
Repeat1: RepeatCount = O.

1* Row assignment of y-direction *1
Step 2: Construct cell groups 91, (h, ... ,9R;
Step 3: Assign cell groups to processors;
For each processor Pi in parallel
RepeatStep 4.1: j = the index of the first cell group assigned to processor Pi;
Step 4.2: For all cells mk E 9j, Sl E Sj, compute Ckl and solve the linear
assignment problem LAP(9j, Sj);

Step 4.3: For all cells mk E M(Rj), update their coordinates.
Step 4.4: 9j+l = 9j+l U M(Rj +1), j = j + 1;
Until
j > the index of the last cell group assigned to processor Pi;
1* Row assignment of x-direction *1
Step
Step

5: Construct cell groups 9~, 9~, ... ,9k;
6: Assign cell groups to processors;

For each processor Pi in parallel
RepeatStep 7.1: j = the index of the first cell group assigned to processor Pi;
Step 7.2: For all cells mk E 9j, Sl E Sj, compute Ckl and solve the linear
assignment problem LAP(9j, Sj);
Step 7.3: For all cells mk E= M(Ri), update their coordinates;
Step 7.4: 9j+l = 9j+l U Rj+l' j = j + 1;
Until
Step
Until

j > the index of the last cell group assigned to processor Pi;

8: Shift the cell groups of both the directions and RepeatCount = RepeatCount + 1;

there is no improvement or RepeatCount = (preset number);

A.3

Details of Experimental Results

A.3.1

Benchmark Data

We have coded the proposed sequential and parallel placement algorithms,

calledPOPINS and PAR-POPINS ,in C language. The algorithms have been implemented on
a SPARCserverlOOO of Sun Microsystems, Inc. (l35MIPSx 4 CPUs, 256MB main memory)on SunOS5.4 with multi-thread library. To show the effectiveness of the algorithms, we have
perfonned several experiments. Table A.l shows all example data of the experiments.

144 APPENDIX A. DETAILS OF THE TIMING-DRIVEN PLACEMENT ALGORITHM

Table A.1: Experimental data of placement.
Data II #cells I #riets I #DO I #rows I #cons I

s
1028
75
12
412
s9234
917
3228
3332 227221105
s158507734 134
s384177572
37 2619s385849344 342
46 27298964
s3593211838 12228 355
45 3488
ract
752
81
16
primary 1
985
398
2907
3136 10736
877
primary2
64
80 6064
avq-small 21854 22124
av -lar e 25114 25384
64
86 6064#cons : the number of timing constraints.

In Table A.1, data "primary2", "avq-small" and "avq-Iarge" are the benchmark data distributed from MCNC [77]. And others are ISCAS benchmark data [11]. For ISCAS benchmarks, logic synthesis and technology mapping were performed by SIS 1.2 [110] using a 0.5micron CMOS library. The values for intrinsic delay and the drive resistance for delay estimates
were used as specified in the library. In this table, "#cons" is the number of timing constraints.
For each data, we gave a clock cycle time as the timing constraints. We first generated a placement by a non-timing-driven placement algorithm and then determined the clock cycle time
multiplying that of the placement by 0.8 rv 0.9.
The technological parameters of the interconnection delay equation as follow.
MCNC benchmarks:
Cl
Tl

G lj

: 4.6 x 10- 5: 3.0 x 10- 2: 8.0 x 10- 3

pFlj.lm,

C2

Q/O,

T2

pF,

Ro

: 2.3 x 10- 5: 3.0 x 10- 2: 2.0 x 104

pFlj.lffi
Q/O.Q

ISCAS benchmarks:
Cl
Tl

Gl j

: 2.0 x 10- 4: 2.0 x 10- 2: 7.0 rv 8.0 X 10- 2

pFIJ-Lffi,

C2

Q/O,

T2

pF,

Ro

: 2.0 x 10- 4: 2.0 x 10- 2: 1.2 rv 2.7 X 103

pFIJ-Lffi
Q/O.Q

Note that we got the values from the MCNC benchmarks, but for Glj and Ro we set the:m referring the current technologies because there was no description about them in the benchmarks.

A.3. DETAILS OF EXPERIMENTAL RESULTS

145

Table A.2: Placement results of POPINS and RITUAL [115].
Data

Methodlength(>")

POPINSPOPINSPOPINSPOPINS

1126048 ( 5485418 ( 24221879 ( -

Cl
C2
C5
C6
C7
s1494
s9234
s15850s38417s38584

A.3.2

Experimental Results of POPINS

We compared POPINS with RITUAL [115]. In Table A.2, we show all placement results ofPOPINS and RITUAL. In Table A.2, #Vios is the number of violated timing constraints, Delay
Max. = maxVtrET Del actr / Delall owr , is called the maximum violation ratio and if it is less thanor equal to 1.0, the placement satisfies all timing constraints. Delay Ave. = Iii L:VtrET Delact r/ Delall owr is an average violation ratio, and length is the total wire length estimated by the
Manhattan distance (,X). time is the running time by a SPARCserverlOOO (seconds).

A.3.3

Experimental Results ofPAR·-POPINS

To evaluate the parallelization of each phase, we compare the results of each phase of PAR-POPINS with that of POP INS . In Table A.3, the results of phase 1 of PAR-POP INS andPOPINS are shown. Next, Table A.4 shows the results of phase 2 of PAR-POPINS andPOPINS for all data. In these experiments, the results of phase 1 of POPINS are used as

146

APPENDIX A. DETAILS OF THE TIMING-DRIVEN PLACEMENT ALGORITHM

Table A.3: All results of phase 1 of PAR-POPIN'S and POPIN'S.
Data

engt

tlme

(,X)

(sec)

C5
C6
C7

s15850s38417s38584s35932
primary2
avq-small
avq-Iarge

POPINS

1

1.00

0.26

28457150(1.00)

18954

Table A.4: All results ofphase2 of PAR-POPIN'S and POPIN'S.
Data
C5
C6
C7

s15850s38417s38584s35932
primary2
avq-small
avq-Iarge

1

1.00

0.26

28457150(1.00)

1368

A.3. DETAILS OF EXPERIMENTAL RESULTS

147

Table A.5: All results of phase3 of PAR-POPIN'S and POPIN'S.
Data

C5
C6
C7
s15850s38417s38584s35932prim ary 2
avq-small
avq-Iarge

POPINS

o

0.83

0.17

22551201(1.00)

247999(1.00)

the inputs of phase 2 of PAR-POPIN'S and 1'JOPIN'S . In this experiments, the parameter,
number of variables, which determines the size of a target sub-circuit is set to 300. The termi-

nation condition in this experiments is that the 10th loop of the improvements has already been
done. In Table A.5, the results of phase 3 of PAR-POP IN'S and POPIN'S are shown. The
results of phase 2 of POP IN'S are also used as the inputs of phase 3 of PAR-POPIN'S andPOPIN'S . The termination condition in this experiment is that the improvement does notoccur in three consecutive loops or the 20th loop of the assignment of the x and y directions has
already been done.
Finally, we compared PAR-POPIN'S wilth POPIN'S and RITUAL [115]. Table A.6
shows the results of PAR-POP IN'S , POPIJVS ,and RITUAL. For "sI5850" and "s38584",
RITUAL could not produce the placements due to errors. In these experiments, the resultsof phases 1 and 2 of PAR-POPIN'S were used for the inputs of phases 2 and 3 of PAR-POPIN'S ,respectively.

148

APPENDIX A. DETAILS OF THE TIMING-DRIVEN PLACEMENT ALGORITHM

Table A.6: All placement results of PAR-POPINS, POPINS, and RITUAL.
Data

C5
C6
C7

s15850s38417s38584s35932
primary2
avq-small
avq-Iarge

POPINSRITUALttNo results obtained.

o

0.83

0.17

22551201(1.00)(---)

268321(1.00)(---)

AppendixB
A Global Routing Algorithm for Over-the-Cell Channel
Routing
In this section, we briefly describe a global routing algorithm which we have presented in [64].
The proposed algorithm determines global routes for each net in both the channel and overthe-cell(OTC) regions simultaneously. The detailed description of the algorithm is presented
in [64].

B.1

Preliminaries

We assume that the standard cell model treated in the algorithm is the Bottom Terminal
Model(BTM) (the details of the BTM is discuss:ed in Chapter 4). In this mode, since Vdd andGnd busses are routed on the M2 in the middle of a cell, the OTC region is vertically divided into
two parts by them in the middle of the cell and the number of available routing tracks, denotedt, on both of the OTC regions is given.

Each net ni is defined as a set of terminals tj which are to be interconnected. A set ofnets defines netlist, N = {ni}. Let C be a set of channels. A pair of terminals (Ps, Pt) of
net ni E N are said to be adjacent in channel lC jinC if no terminal of the same net ni exists
between the positions of Ps and Pt on the same side of the cell row in which either Ps or Pt
belongs to. A pair of adjacent terminals (Ps, Pt) of net ni, defines a net segment segk = (Ps, Pt)of the net ni. Next we define a net connection graph for net ni E N to be an undirected graphGu(ni) = (Vu(ni),u E(ni)) . Vertex set Vu(ni) corresponds a set of terminals of net ni and edgee = (vs, Vt) is in Eu(ni) if and only if two terminals Ps,Pt define a net segment segk = (Ps,Pt)(Fig. B.1). Let Gu(N) be a union of net connection graphs Gu(ni) of ni E N, that is, Gu(N) =(UniEN Vu(ni), UniEN Eu(ni)). A global routing solution for net ni is a spanning tree of the net

connection graph Gu(ni), and let Tu(ni) be a se1t of edges in the spanning tree of ni. Note that
Tu(ni) is divided into a set of net segments routed in channel regions, denoted Tu(ni)', and a setof net segments routed on OTC regions, denoted Tu(ni)". A global routing solution for a set ofnets N is a spanning forest of the net connection graph Gu(N), and let Ta(N) be a set of edges
belonging to Tu(ni) for all nets ni E N, that is, Tu(N) = Uni EN Ta(ni) .
The global routing problem for considering OTC regions is as follows. Given a set of net
149

150

APPENDIX B. GLOBAL ROUT1NG CONSIDERING OTC CHANNEL ROUTING

I

I

I
I
I

I:::J
1

I~.

1

-= ¥

rb

1

termlna st----+----t

t---+---III . -net segments

Figure B.l: Net segments and a tcorresponding net connection graph Ga(ni).

connection graphs G a( ni) and an OTC routing capacity t for each cell row, the problem is tofind a set of spanning trees Ta(ni) = Ta(ni)' U Ta(ni)" so as to minimize the total channel density
which is determined by the set of net segments Ta( ni)" routed in channel regions under the given
layout constraints.

B.2

Overview of the Algorithm QROTeThe proposed global routing algorithm for OTC routing, called gROTC, consists of two phases.
In order to minimize the total channel density, phase 1 determines a set of net segments to berouted on the OTC regions so as to maximize the number of net segments, and phase 2 constructs
a set of spanning trees Ta(N) by determining a set of net segments to be routed in channels.
Since routing on the OTCs is carried out on only one layer(M2), phase 1 needs to determine
a set of net segments so as not to cross each other and to maximize the total weight of net
segments I to be routed on the OTCs. We solve this net segment selection problem of a cell row
with the algorithm DP presented in [26]. We determine the set of net segments TaCN)' to berouted on OTCs for each cell row by applying the algorithm DP to the lower side of the cell row
and next to the upper side of the cell row (Fig. B.2),
Phase 2 determines a set of net segments Ta(N)" to be routed in channels so as to connect
all the terminals of net ni E N. First, we update the set of net connection graphs Ga(N) by
deleting redundant edges considering the set of net segments routed on OTCs in phase 1, and addthem to the set of global routes Ta(N). Next, we estimate the channel density for each channel
and calculate the weight of edge e E Ea(N) where the weight of edge e is same as the weightof the net segment corresponding to the edge 2. Since, after phase 1, the global route Ta(ni) of
1The weight of a net segment is defined based on both the criticality and possibility of the reduction of thechannel density for the net segment.
2The weight of edge e E E(j(N) is defined based on the length of the net segment and the possibility of theB.2. OVERVIEW OF THE ALGORITHM 9ROTC

/

-

~-

net segment
..---

I

I

I

I

-

1..-.._

151'-(a) net segments in the cell row

IIFHJ III III IIRYIH(b) applying DP to the lower

cell side(c) applying DP to the upper
cell side

Figure B.2: Phase 1: Determination of net segments routed on OTCs.

I+

iterative improvementby edge insertion anddeletionI
I
I I

Figure B.3: Phase 2: Determination of net segments routed in channels.

net ni is partially constructed, we simultaneously construct the global routes Tu(N) for all thenets by applying an operation to select the minimum weighted edge e E Eu(.N) and adds it toTu(N) until all the terminal of each net are connected.

After the above construction of the global routes Tu(N), we improve Tu(]l/) by the edge insertion and deletion. First, we select net ni which passes through the column with the maximum

ratio of the local column density to the channel density, and insert another edge e E Eu(ni) which
passes through the column with the minimum ratio of the local column density to the channel
density. Next, we find a cycle on Tu(ni) and delete edge e' in the congested regions from Tu(ni)to break the cycle(Fig. B.3). Repeat these operations until the channel density of each channel
will not be improved for the some successive constant times.

reduction of the channel density.

Appendix C
Details of the OTC Routing Algorithms in Chapter 4
C.I

Net Decomposition Methods for 3VR-BTM-N

In this section, we describe net(net segment) decomposition methods for 3VR-B7M -N In
Section 4.3.

e.l.l

Two-Terminal Net Decomposition in Step I

First, we describe the two-terminal net decomposition method in Step 1. Since the algorithm
DP [26] in step 1 can handle only a set of two-terminal nets, a set of multi-terrninal nets need to

be decomposed to a set of two-terminal nets / NSs. For example, we consider the selection ofplanar routable nets of the top cell row as shown in Fig. C.l. In conventional routers [83, 140],
scanning the channel from left to right column by column, routers decompose multi-terminal
nets into two-terminal nets / NSs which are formed by each pair of successive terminals of thesame net. For example in Fig. C.l(a), the router of [140] decomposes a four-t(~rminal net to thethree net segments(NSs) before determining the aTC routing nets by the DP, but two of three
NSs cannot be routed on the top aTC region because there does not exist a vacant terminal intheir terminal positions.
To solve the above drawback of the conventional decomposition method, 'we propose a decomposition method for the aTC routing. In our decomposition method, we explicitly consider
the set of vacant terminals. It is assumed that, in the same side of the cell row, net nt has kterminals( k 2 3) including vacant terminals corresponding to terminals which are in the opposite side of the cell row. For example in Fig. C.l (b), the net has three tenminals including
one vacant terminal. Let Ptt, Pt2, ... , Ptk denote the k terminals. We shall replace the net nt byk(k - 1)/2 two-terminal net(net segments) which will be denoted t - i - j, (1 :s; i < j :s; k)(Fig. C.1(c». Specifically, we splitptl, (1 :s; l :s; k), into k - 1 terminals Ptl,t,Ptl,2,··· ,Ptl,k-l·(These terminals are placed next to each other as a group.) Ptl,i is assigned to net t - i - l for
l :s; j :s; l - 1, and Ptl,j is assigned to net t - l - (j + 1) for l :s; j :s; k - 1. For example, in the

proposed method, we can decompose the net to the three NSs utilizing a vacant terminal on the
top cell row shown in Fig. C.1 (c), and it is better to decompose the net to a set: of NSs that canbe routed on OTC. Therefore the proposed decomposition 'method is more effective and more
153

APPENDIX C. DETAILS OF THE OTC ROUTING ALGORITHMS154

OTe routing
patterns

These NSs can not be routed on the top OTe.

~nif\ nir=LJ

DPC: l:,\

>---<

DP

t~

I LJ
I ~
~"-I----i~ ~ ,,-1-2, ~I----i0~I•.--<>.
•Inini(a) a conventional method[9J• terminals

equivalent••(b) the proposed method

vacant terminals

t-l-~

•

(c) after terminal splitting• virtual terminals

Figure C.1: An example of the two-terminal decomposition for a multi-terminal net.

flexible than the conventional method in [140] because it makes the DP select the NSs which

reduce the channel density.

C.l.2

Net Segment Decomposition in Step 2

Next, we describe the NS decomposition method in Step 2. This NS decomposition is performedby linear assignment. Let Scross(S2s) (s = t, b) be the set of NSs which are crossed to the setof planar routed NSs, S2s, in Step 1. First, we define a cost matrix C which is used in linear
assignment. Let the value of the cost matrix elj E C be the sum of the weight of the left andright NSs, denoted Lsegl and Rsegl, when segl E Scross(S2s) is assigned to the vacant terminal
Pj of a cell row and is divided to two segments. Then elj is,(C.1)
where f(Lsegl) (resp. f(Regl)) is 1 if the decomposed Lsegl (resp. Rsegl) does not cross theplanar routed NSs of S2s in Step 1, otherwise O. The NS with a large cost has a high possibility. lo:L:l ..
Lseg

I

Rseg[

I

I

segl
I

I I

seg .
I
JI
segk
I

(a) segment decomposition

seg·

~
I

segk

I

(b) resulting aTe routing patterns

Figure C.2: An example of the NS decomposition with linear assignment.

to be planar routed. In the proposed routing algorithm, we decompose the NSs by the linear
assignment algorithm in [14] so as to maximize the total cost. An example of the NS decom-

C.2. PROOF OF THEOREM 4.1: tE ~

seg]•

0-----0

155

•
seg2
I

•

(a) for the top ceLL row

8

0--<>---0

I

seg1

~

•
I

g

se :

(b) for the bottom cell row

Figure C.3: An example of decomposition in Step 3.

position of Step 2 is shown in Fig. C.2. We repeatedly apply this method until all the vacantterminals are used or all the NSs are not decomposed any more.

e.I.3

Two-Terminal Net Decomposition in Step 3

Finally, we describe the NS decomposition method in Step 3. The decomposed NSs are used
for constructing RCGs for the top and bottom cell rows. The NS decomposition is perfonned
based on vacant terminal positions of the top and bottom cell rows, respectively. If there exist
vacant terminals on the cell row s (s = t, b) in the interval [l(segl), r(segl)] of segl E 5', we
decompose segl into a set of subsegments seg: E S~ based on the positions of the vacant terminals. For example in Fig. C.3, there are three vacant terminals on the top cell row in theinterval [l(segd, r(segl)]. Then segl is decomposed to the four subsegments in

S:. Similarly,

since there are two vacant terminals on the bottoIn cell row in the interval [l(segl), r(segd], thenit is decomposed to three subsegments in S~.

C.2

Proof of Theorem 4.1

Theorem 4.1 The selection problem of a set of planar routable NSs with the maximum weightfor nonuniform routing capacity can be solved in O(k . L2) time, where L is the channel lengthand k is the maximum number of available tracks on the GTe.
Proof' If L is the channel length and k is the number of available tracks in the problem,the maximum weight of solutions is M (l, L, k). According to the three recurrence relations(4.9), (4.12) and (4.15) in Section 4.3.6, M(l, L, k) can be computed by dynamic programming
as follows:

Algorithm C.l Dynamic Programming for Nonunifonn R~uting Capacity
1 beginAPPENDIX C. DETAILS OF THE OTC ROUTING ALGORITHMS

156

for Z = 1 to k do
for t = 1 to L - 1 dofor x = 1 to L - t do

2
3
4

1* Assume that net segment segi of net n i has one terminal at column x and the other at column
x' *1
Let y = x + t;
if x' tf. [x, y] then
I*Case 1 in Section 4.3.6*1
M(x, y, z) = M(x + 1, y, z);else if x' E [x, Xmin] then I*Case 2 in Section 4.3.6*1
M(x, y, z) = max{M(x+l, y, z), M(x+l, x' -1, z-l) +M(x'+l, y, Z)+wl(.segl)};else if x' E [Xmin, y] then I*Case in Section 4.3.6*1
M(x, y, z) = max{M(x + 1, y, z), M(x + 1, x' - 1, cap(x) - 1) +M(x' + 1, y, z) +

5
6
7
8
9
10
11

wl(segl)};

12
end
13
end
14
end
15 endNote that the list of elements of M(x, y, z) need not to be explicitly stored when it ]s computed in the body of the internal loop; rather M(x, y, z) may be represented by pointers to thesolution of the corresponding subproblems. Then the last step of the algorithm is to explicitly
enumerate the elements of M(l, L, k), which can be done in O(L) time by traversing back fromM(l, L, k) along these pointers. Therefore it is easy to see that this procedure takes O(k . L2)
time.
•

C.3

Transformation from the BTM to the ATM-O

In this section, we describe a transformation from the BTM to the ATM for the benchmarks usedin the experiments in Section 4.5. Since the cell model in the MCNC benchmarks is the BTM,
we transformed these benchmarks to the ATM-O by randomly assigning the track nurnbers toterminals(Fig. CA(b)). And then we placed obstacles on the M2layer of each cell(Fig. CA(c)).
The size of each obstacle is the same as a terminal, and each obstacle is placed on any column.
But if a terminal exist on a column, at most one obstacle is placed so that the terminal canbe vertically routed to at least one side of boundaries of the cell row by using that column.
For PRIMARY I benchmark [49] of the BTM, since a net(terminal) list of each channel was
separately given, we also transformed the data to the ATM-O and determined terminal positionsof each cell row Tj+l as the following way(Fig. C.5). First, terminals in the top side of a channel
Cj are randomly assigned to tracks from 1 to 6 of the cell row Tj+l without changing the originalcolumn number of terminals. Similarly, terminals in the bottom side of the channel Cj+l are
randomly assigned to tracks from 7 to 12 of the cell row Tj+l' Finally, obstacles are placed at

C.3. TRANSFORMATION FROM THE BTM TO THE ATM-O

1

....2

34
.... 5tk---- -tra~ks ttenninal (MI)tra~ks t ---~- t1
I2.. [Iill] ..

345

157

,

0 jstacle(M2)5.

I • • 3•

2~.

4• •

112

tracksItenninal (M2)(b)(a) original data of the BTM(c) new data of the ATM

Figure C.4: Transformation of temunal positions for MCNC benchmarks.

Cj+1

rj+1

Cj

L.-II e e • I

Ie e e • • I

w. .1.
..
-- 5

0

3

2

Cj+I

I

-----

12

terminal (Ml)

:

0

I
track

.. 4 -5
1 2

I•

••

-

_3. 2

-I

(a) original data o/the BTM

1. 2 •

4. 5 •

Cj

1° • • • • 1

I. • 8 8 81(b)(e) new data of the ATM

Figure C.5: Transformation of terminal positions for PRIMARY 1.

positions from track 1 to track 12 satisfying the condition in which temlinals can be routed by
the routing patterns obtained from the global routes. Capacities on the aTC region are set to 12.

AppendixD
Proofs of Lemmas and Theorlem for the ACPAI in Chapter 5
Lemma 5.1 There is no optimal assignment 'If, in which in any interval x a pin of a net inLSi(x) is assigned to the right of a pin of a net in RSi(x) U RPi (x). Similarly, there is no
optimal assignment 'If, in which in any interval x a pin of a net in RSi(x) is assigned to the leftof a pin of a net in LSi(x) U LPi(x).
0Proof' We assume there is an optimal assignment 'If in which in any interval x a pin of a net
in LSi(x) is assigned on the right of a pin of a net in RSi(x) or RPi(x). Then without increasingd(Ch ) of 'If, we can transform 'If to 'If' whose T L(Ch ) is smaller than that of 'If by interchanging

the pin of the net in LSi(x) with the pin of the net in RSi(x) or RPi(x) that was assigned on theleft of it. This contradicts the fact that we started with an optimal assignment 'If. For RSi (x), we
can prove it in a similar manner.

•

Lemma 5.2 Any assignment 'If in which all the pins are assigned so as to minimize the estimatedwire length T L can be transformed into an assignment 'If' in which for any subchannel SCi, all thepins of min(1 SCi I, II Pi I) nets in I Pi are aligned and all the pins are assigned so as to minimize
the estimated wire length T L.
Proof'

0Consider an optimal assignment 'If in which not all the pins of min(lsCiI, II Pil)

nets in I Pi are aligned. We show the transformation of the optimal assignment 'If into anotheroptimal assignment 'If' that satisfies the conditions of Lemma 5.2.
In the optimal assignment 'If, consider nets in I Pi, whose two pins, say a and b, are assigned
but not aligned in a subchannel SCi. Then the pin a should share a column with the rightmost
assigned pin of a net in LPi U LSi ( respectively, the leftmost assigned pin of a net in RPi
U RSi ), and the pin b should share another (~olumn with the leftmost assigned pin of a net in

RPi U RSi ( respectively, the rightmost assigned pin of a net in L~ U LSi ), since if not, we

could obtain an assignment in which T L is smaller than that of 'If. In this assignment, if weinterchange the pin b with the pin residing opposite side of a, D and T L remain unchanged.
Similarly, if we interchange the pin a with the pin residing opposite side of b, D and T L also
remain unchanged. Therefore we can continue interchanging pins in this way in the subchannel
SCi until min(lsCiI, II Pi/) nets of I Pi are aligned.

159

•

160

APPENDIX D. PROOFS OF LEMMAS AND THEOREM FOR THE ACPAI

Lemma 5.3 Any assignment 'Tr in which for any subchannel SCi, all the pins of min(1 SCi I, II Pi I)
nets in I Pi are aligned and all the pins are assigned so as to minimize the estimated wire length

T L is an optimal assignment.

0

A Sketch of Proof In general, any assignment 'Tr' can be transformed from the assignment'Tr by repeatedly interchanging a pair of pins. In the following, we prove the lemma by showing

the fact that there is no assignment 'Tr' which is transformed from 'Tr and whose channel density

D is smaller than that of the assignment 'Tr.
From the definition of the local channel density Dk at column k, Dk is equal to the nUInber ofnets crossing the column k. We assume that column k is in subchannel SCi. From the assuInption,
for any subchannel SCi, all the pins of min(lsCiI, II Pil) nets in I Pi are aligned. In the folllowing,
we consider the case that IIPil < ISCiI. For the case that IIPil 2: ISCiI, we can prove the lemma
in a similar way.
In the case that II Pi I < ISCi I, the local channel density Dk at column k is equal to the sumof (a) the number of LSi and LPi nets which are assigned in the column k and to the right of thecolumn k, (b) the number of RSi and RPi nets which are assigned in the column k and to theleft of the column k, and (c) the number of P B i , BSi , and BPi nets passing through the columnk.
Since in the assignment 'Tr, all the pins are assigned so as to minimize T L and all the pins of

II Pil nets in I Pi are aligned, it is enough to consider the following two cases; (1) LSi and LPi
nets are assigned to the left side of I Pi nets and RSi and RPi nets are assigned to the right sideof I Pi nets, (2) LSi and LPi nets are assigned to both the sides of I Pi and RSi and RPi nets arealso assigned to both the sides of I Pi nets.
From the definition of Db Dk can be decreased only if the number of nets in the cases (a)and (b) are decreased. For the case (1), we can show that Dk cannot be decreased by repeatedlyinterchanging any pair of pins. This can be proved by induction of the number of interchanging.
For the case (2), we can also show that Dk cannot be decreased by repeatedly interchanging any
pair of pins.
Thus, there is no assignment that Dk is smaller than that of the assignment 'Tr. This claim
holds for any k, and the lemma holds.

•

Theorem 5.2 Algorithm ACPA 1 produces an optimal pin assignment of Problem CPA] inOem) computation time, where m is the number of pins.
0
Proof First, we prove that the algorithm obtains an optimal pin assignment by inductionof the number of subchannels in which the algorithm assigns positions to the pins.
We first establish the basis step, that is, the assignment of pins in the SCI. Without loss ofgenerality, we assume right(T1) > right(B 1). Since the column ·of the rightmost grid point

161

;

;

I
I
I
I

I
I
I
I

:I SCi+l :IIii

Bk = short i+l

Bk = short i+ 1(a)Bk is not included in Tj •I(b)Bk is included in Tj .

Figure D.1: The two possible patterns of Tj and B k •of T. differs from the column of the rightmost grid point of B., we consider the following twocases (1) and (2) depending on the number of nets in each net class.
(1) Case o/(IMLS. U LS.(Tdl + ILP.I + lIpId) ~ Isc.l.

The algorithm assigns pins in M LS. U LP. pair-by-pair, one pair per column from the leftmost
available grid points on the column in SC., and all the pins of Isc.1 - (1M LSd + ILP11 + II PI!)
nets in LS. (Td one-by-one from the leftmost available grid point in T I • Next, the algorithm
assigns all the pins in I p. one-by-one, one net per column from the left most available grid
points on the column, and pins of RS. (B I ) U RPI (B I ) one-by-one from the rightmost available
grid point in B •. Finally, the algorithm assigns all the pins in BPI (B I ) U BS. (B.) one-by-one
in the arbitrary grid point in B I • This assignment satisfies Lemma 5.3.
(2) Case o/(IMLS. U LSI(T1)1 + ILP11 + IIPtl) < Isc.1

or (1M LSI U LSI (Bdl + ILPII + II PI!) < ISCII·
The algorithm assigns pins in M LSI, LPI , L8I , and I PI one-by-one, one net per column fromthe leftmost available grid points on the column in SCI in this order, and pins in RS I and RPI
one-by-one one net per column from the rightInost available grid points on the column in SC. inthis order. Next, the algorithm assigns pins in BPI(B 1) U BSI(B I ) one-by-one in the arbitrary
grid point in B I • This assignment also satisfies Lemma 5.3.
Next, we consider the assignment of pins from SCI to SCi+I under the inductive hypothesisthat the assignment of pins from SCI to SCi minimizes (D, T L). Without loss of generality, we
assume SCi+I = overlap(Tj , B k), shorti+I = Bb and longi+. =T j . Then, there are two possible
patterns of the relative position for interval Tj' and Bk in SCi+l (Fig. D.l (a), (b)). In the rest of
proof, we prove the case of Fig. D.1(a). We can prove the case of Fig. D.1(b) in a similar way.
First, we consider the case ILSi+1(Bk)1 =I O. In our algorithm, all the grid points in Bk of SCi
are used to assign pins of nets in LSi(Bk) U LPi(B k) U I ~(Bk). Since any grid point in Bk of
SCi is not used to assign a pin of nets in RSi (I3 k) U RPi(B k), the assignment of pins in SCi+1 is
independent of the assignment of pins before SCi+I. Therefore we can assign all the pins in SCi+I
in the same way of the basis step. This assigmnent satisfies' Lemma 5.3.

162

APPENDIX D. PROOFS OF LEMMAS AND THEOREM FOR THE A CPA 1
Next, we consider the case ILSi +1(Bk)1 = O. Then, there may be free grid points in Bk

of SCi. If IIPi +m I ~ ISCi+II, the algorithm assigns pins of ISCi+11 nets in I Pi +I , and assigns all
the remaining nets in the else part of Step.2 and Step.3 rv Step.5. This assignment satisfies
Lemma 5.3. If IIPi+I I < ISCi+tI and ILPi+II + IIPi+II ~ ISCi+I I, the algorithm first assigns
pins in LPi +I and I Pi +l in the else part of Step.2.2. Next the algorithm assigns pins of nets
in RSi +I (B k) and RPi +I (B k) one-by-one from the rightmost available grid point in B k. By
Lemma 5.1, any pin of nets in LPi + 1(B k ), assigned to the right of the pin of nets in RSi + I (B k )and RPi +I (B k ), will be interchanged in Step.3. Then this assignment satisfies Lemma 5.3. If
ISCi+11 ~ (1M LSi +I U LSi+II + ILPi+11 + IIPi+II + IRPi +1 I), the algorithm assigns pins of nets in
RPi+I and RSi +1 in Step.2.2.1. Then, applying Step.3, the assignment satisfies Lemma 5.3. If
ISCi+I I > (1M LSi +1 U LSi+11 + ILPi+II + IIPi+I I + IR~+II), the algorithm assigns pins of nets inthe else part of Step.2.2.1. This assignment also satisfies Lemma 5.3. Hence, from Lemma 5.3
and the inductive hypothesis, the assignment of pins from SCI to SCi+I minimizes (D, T L), andthe inductive hypothesis holds for SCi+I'
Next, time complexity of the algorithm ACPA1 is discussed. In the classification of nets in

Step.l, first, ne1ts in TI and Bl are classified. For any SCi, each net class is updated by checking
both the class of previous subchannel SCi-I and configuration of net in the new scanned interval.
Since this classification of any net takes 0(1), Step.l takes O(L~=1 Ipins(Tj)1 + L~=l Ipins(Bk)j)= O(ITOPI + IJ10TTOMj) = Oem). Checking each net in Step.3 whether a pin of nets in LPi

is assigned to the right of a pin of nets in RSi and RPi , takes 0(1) because the pins of nets in
LPi are assigned before assigning the pins of nets in RSi and RPi . Each interchange of a pinof nets in LPi to the right of a pin of nets in RSi and RPi takes O( 1). Since Step.2 rv Step.5
assign pins one-by-one, whole Step.2 rv Step.5 take Oem). Hence the time complexity of thealgorithm ACP.A1 is Oem).

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