T

Development of High-Speed Silicon Devices andTheir Design with Advanced Physical Models

Hiroshi Goto

January 1999

Abstract
In the field of high-speed silicon devices , silicon bipolar junction transistors(BJTs) had played a major role from the 1970s to the end of the 1980s. However,in the 1990s complementary metal-oxide-semiconductor (CMOS) .field effecttransistors (FETs) have been replacing their position. This dissertation explains
the reasons why BJTs were suitable for high-speed operation. This is concluded
from the development of technologies for BJTs and the analyses of devices
fabricated with these technologies. At the same time it clarifies why they were
replaced by CMOS transistors. The BJT's high driving capability and large power
dissipation were the both sides of a sword.
In the case of high-speed CMOS devices, the driving current of MOSFET
should be large enough, and device design must be based on precise
comprehension of carrier transport in MOSFETs. Therefore, we need accurate
device model as well as rigid device-structure information obtained byexperiments. This dissertation describes the device design methodology not only
based on inverse modeling to extract device structures consistent with all kinds ofexperimental results but also based on simulations by generalized hydrodynamic
model and full-band Monte Carlo model. The background and concept of themethodology is also discussed, and its necessity in future development is clarified.
Moreover, hot carrier modeling is discussed by employing full-band Monte Carlodevice simulation. Also, this dissertation clarifies the fact there is noexperimental evidence for the difference between the surface and bulk impact
ionization mechanism in silicon. The reported difference in the literature was only
caused by an unsound application of the local field model and was just an artifact.
Finally, by using these sophisticated models, the saturation drain current as well as
hot carrier effects of subquarter micron MOSFETs are analyzed. MOSFET design strategy
for the 0.1 J.L m regime is discussed and the importance of shallow junction forsource/drain extension is also clarified.

ii

Acknowledgments
I greatly acknowledge Professor Dr. Mitiko Miura-Mattausch for supporting
the preparation of this doctoral dissertation that is submitted to Hiroshima
University in Japari. I express my best thanks to my coworkers at Fujitsu Limited,
especially Dr. Christoph Jungemann, who was with Fujitsu Kawasaki in Japan
from April, 1995 to March, 1997 as a post-doctoral visiting researcher and mainly
contributed to the development of the full-band Monte Carlo device simulator
FALCON, and Mr. Seiichiro Yamaguchi for the major contribution to thedevelopment of the inverse modeling assisting program MOSFIT. I also
acknowledge my current and former colleagues, Mr. Kaina Suzuki for thedevelopment of the two-dimensional process simulator FIPS2, Mr. Yoji Nagase
for the development of the ac analysis routine for the two-dimensional device
simulator BIP2DAN, and Mr. Kenji Hashimoto for the development of thetransient analysis routine of the same program. In addition I owned quite much tothe people who worked together since my joining Fujitsu Limited in Kawasaki , todevelop not only bipolar device technologies such as IOP-11, U-FOX, ESPER, butalso quarter and subquarter micron CMOS technologies. Finally, I speciallyacknowledge my wife for her daily support to my work these ten years.

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To my wife a nd childrenIVTable of Contents
Abstract . .. .............. ..........................................................................ii

Ac kn ow led gm en ts .......................................................................... iii

Chapter 1 Introduction .................................................................................... 1
1.1 Motivation ......................................................................................................................... I
1.2 Scope and Organization.................................................................................................... 1
Chapter 2 Development of High-Speed Silicon Bipo lar Devices ...................... .4
2.1 Historical Back Ground .....................................................................................................4
2.2 Trench Isolation Techniques .............................................................................................. 5
2.2.l Introduction.................................................................................................................. 5
2.2.2 Trench Isolation by Oxide and Polysilicon..................................................................7
2.2.3 Trench Isolation with Thick Field Oxide ................................................................... 122.2.4 Benefits and Device Performance .............................................................................. 15
2.2.5 Limiting Aspects and Recent Improvements............................................................. 18
2.2.6 Conclusion.................................................................................................................. 19
2.3 Polysilicon Self-Aligned Structures ................................................................................ 19
2 .3 .1 Introduction................................................................................................................ 19
2.3 .2 Double Polysilicon Self-Aligned Structure ................................................................ 19
2.3.2.1 One-Mask Process .................................................................................................20
2.3.2.2 Two-Mask Process................................................................................................25
2.3.2.3 Three-Mask Process ..............................................................................................29
2.3.3 Single Polysilicon Self-Aligned Structure.................................................................29

2.3.4 Sidewall Base Contact Structures.............................................................................. 30
2.3.5 Polysilicon Emitter and Emitter-Base Heterojunction.............................................. .35
2.3.6 Conclusion .................................................................................................................. 37
2.4 Physics-Based Bipolar Transistor Design..................................................................... .37
2.4. l Introduction................................................................................................................3 7
2.4.2 Two-Dimensional Process/Device Simulation System..............................................38
2.4.3 Simulation of Pedestal-Collector Transistors .............................................................39v

2.4.3.1 Process Simulation................................................................................................ 39
2.4 .3 .2 Device Simulation................................................................................................ .41
2.4.4 Favorable Process Condition for Pedestal Collector..................................................44
2.4.5 Application to ECL Circuits....................................................................................... 46
2.4.6 Conclusion.................................................................................................................. 46

Chapter 3 Performance Es tim a tion of High-Speed Bipola r Device ............... .47
3.1 Introduction..................................................................................................................... 47
3.2 Strategy to Estimate ECL-Circuit Perfonnance ............................................................. .47
3.3 Optimization of ECL-Circuit Perfonnance ..................................................................... 54
3.4 Favorable Silicon BJT Features and Its Limitation........................................................ .56
3.5 Conclusion ....................................................................................................................... 58

C ha pter 4 Design Concept for High-Speed CMOS Device ..........•.................. 60
4. 1 Introduction ..................................................................................................................... 60
4.2 Requirements for High-Speed CMOS Device ................................................................61
4.3 Quarter and Subquarter Micron CMOS Technologies.................................................... 63
4.3.l Quarter Micron CMOS Technology........................................................................... 63
4.3.2 Subquarter Micron CMOS Technology..................................................................... 64
4.4 Conclusion .......................................................................................................................64

C hapter 5 Inver se M od elin g Technique for MOSFET Des ign ............•........... 65
5. I Introduction .....................................................................................................................65
5.2 Inverse Modeling Procedure ........................................................................................... 66
5.3 Extraction of a Deep Submicron MOSFET Structure..................................................... 68
5.4 Saturation Drain Current and Substrate Current. ........................................................... 77
5.5 Device Characteristic Prediclion..................................................................................... 79
5.6 Conclusion ...................................................................................................................... 80

C hapter 6 Carrier T ran sport in MOSFETs ......................•............................ 81
6.1 Introduction ..................................................................................................................... 81
6.2 Modeling of Carrier Transport in MOSFETs.................................................................. 82
6.2. l Particle-Based Model ................................................................................................. 82
6.2.1. 1 Full-Band Monte Carlo Device Simulator - FALCON ........................................ 83
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6.2.1.2 Simulation Results by FALCON.......................................................................... 85
6.2.2 Fluid-Based Model. .................................................................................................... 87
6.2.2. l Hydrodynamic Model versus Energy Transport Model.. ..................................... 87
6.2.2.2 Generalized Hydrodynamic Model.. .................................................................... 88
6.2.2.3 Guarantee of Simulation Accuracy by GHDM.................................................... 89
6.3 Impact Ionization in MOSFETs ...................................................................................... 90
6.3.1 Impact Ionization Models .......................................................................................... 91
6.3.2 Surface Impact Ionization .......................................................................................... 92

6.4 Conclusion ................................................ ........ ........................... ............. 98
Chapter 7 Physics-Based MOSFET Design .................................................... 99
7 .1 Introduction ....................................... ........................................................ 99
7.2 Hot Carrier Effects ofnMOSFET. ................................................................................ 100
7.3 Physics-Based MOSFET Design................................................................................. 104
7.4 Conclusion...................................... ~ ............................................................................ 106

Chapter 8 Conclusion .................................................................................. 107
8.1 Summary....................................................................................................................... 107
8.2 Future Work................................................................................................................... 108

Bibliogra phy ................................................................................. 11 0
List of Papers ... ............................................................................ 122

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List of Tables
Table 2.1 Typical address access time oflinear shrunk lkb ECL RAMs using JOP-II ........ 17
Table 2.2 Calculated deyice parameters and BVao··· .................................................... .44
Table 5.1 Extracted parameters for each device and measurement data. .............................. 69
Table 5.2 Extracted doping and structure-related parameters for a deep submicronnMOSFET (Lpoly=0.19 µ m). Gate oxide thickness is 6.3 nm and contact
resistance is 160Q µ m .........................................................................................76viii

List of Figures
Fig. 2.1 Fabrication process steps of a typical trench isolation technique ....................... 8
Fig. 2.2 Unfavorable trench shapes caused by trench etching.
(a) Black silicon (b) Sub-trench (c) Bowing (d) Laterally etched undercut.. ........ 9
Fig. 2.3 Typical trench-isolated structures.
(a) DGI (4] (b) IOP-II [5] (c) U-Iso [8] ....................... .............. .............. 11
Fig. 2.4 Fabrication process steps of U-FOX ...................................................... 13
Fig. 2.5 Fabrication process steps of [1 OJ ................... .. ...... ... ... .................. ....... 14
Fig. 2.6 Modified trench-isolated structures.
(a) [12,13] (b) [14] (c) [9] (d) [10] (e) [15,16) ................................ ........... 16
Fig. 2.7 SST-IA fabrication steps [31) ................................. .. .................. 21
Fig. 2.8 Cross-sectional view of the SST-lB transistor with selectively implanted pedestal
collector [32] ......... ........ ......................... ...... ................... .... ... ....... 22
Fig. 2.9 Fabrication steps of the new polysilicon self-aligned process [33] ...................24
Fig. 2.10 Fabrication steps of the self-aligned transistor process [36] ... ... ... .................26
Fig. 2.11 Fabrication steps of the double polysilicon self-aligned process using couplingbase implantation [52] ..... ..... ... .. ... ............................................... .... .28
Fig. 2.12 Fabrication steps of the single polysilicon self-aligned process [66) ............... 31
Fig. 2.13 Fabrication steps of the SICOS process [67) ..... . .................... .................33
Fig. 2.14 Fabrication steps of the SICOS process modified by the TOSS process (69] ..... .34
Fig. 2.15 Fabrication steps of the self-aligned selective poly-epi growth process (70] ...... 36
Fig. 2.16 One-dimensional doping profiles of analyzed transistors at the center of
emitter.......................................................... ...... ........... .. ...........40
Fig. 2.17 Two-dimensional doping distributions with concentration equi-contour lines .....40
Fig. 2.18 Schematic cross section of an analyzed transistor. The device length is 1.0 µ m . .41
Fig. 2.19 Cutoff frequency <fr) versus collector current Uc) characteristics ................... .42
Fig. 2.20 AC base resistance (rw) and base-collector capacitance (Cc0) versus collector
current Uc) characteristics ... ............. ...................... .. ... ...................... .42
Fig. 2.21 Current gain (hp£) versus collector current Uc) characteristic .......... ............. .43
Fig. 2.22 Collector-to-emitter current Uc) versus collector-to-emitter voltage (VcE) where
the base currents terminate ................................. .. ..............................43
Fig. 2.23 Relationship between BVCEo and fr for different phosphorus-ion-implanting
conditions. Dose conditions; 150KeV with 2 X 10 12/cm2, 1 X10 12/cm2 ; 300KeVlX

Fig. 3.1 Gate delay time versus switching current per gate (arbitrary unit) ................... .48
Fig. 3.2 Schematic cro~s-section of the analyzed transistor. ..................................... 49
Fig. 3.3 Impurity profiles for the analyzed transistor.
(a) Selectively implanted pedestal collector profile.
(b) Gradient collector profile ......... ..... . ........ . .............................. ......... 51
Fig. 3.4 Cutoff frequency and current gain versus collector current (pedestal collector) .... 52
Fig. 3.5 Cutoff frequency and current gain versus collector current (gradient collector) .... 52
Fig. 3.6 Analyzed circuit diagram ................................................................... 53
Fig. 3.7 Gate delay time versus switching current per gate (pedestal collector) .............. 55
Fig. 3.8 Gate delay time versus switching current per gate (gradient collector) .............. 55
Fig. 3.9 Schematic cross-section of the favorable BJT structure ................................ 57
Fig. 4.1 Cross-sectional structure of dual-gate CMOS device with CoSi 2 after
contact plug formation ............................................................... 63
Fig. 5.1 Flowchart of the "MOS FIT" program ............................................ 66
Fig. 5.2 C-V characteristics of a large-area nMOSFET comparing measurement andsimulation results after the gate oxide thickness and doping profile of polysilicongate are determined.
(a) Classical calculation. (b) Quantum mechanical calculation ....................... 70
Fig. 5.3 Subthreshold Id-Vg characteristics of a 1.0- µ m nMOSFET comparing
measurement and simulation results after the channel doping profile is extracted.
(Lines: measurement results, symbols: simulation results) ........................... 71
Fig. 5.4 Cgd-V characteristics of a finger gate nMOSFET comparing measurement andsimulation results after the source/drain doping profile is extracted. (Lines:
measurement results, symbols: simulation results) ..................................... 71
Fig. 5.5 Subthreshold Id-Vg characteristics of a 0.19- µ m nMOSFET comparing
measurement and simulation results after the channel doping profile is extracted.
(Lines: measurement results, symbols: simulation results) ........................... 72
Fig. 5.6 Mid-channel doping profiles depending on the gate length........................... 73
Fig. 5.7 DIBL effect for a 0.19- µ m nMOSFET comparing measurement and simulation
results after the channel doping profile and gate length are determined. (Lines:xmeasurement results, symbols: simulation results) ..................................... 74
Fig. 5.8 Implementation of the source/drain co ntact resistance for linear ld-Vg
calculation .............................. ........ ... .......... .......... .. ....... .......... .... 74
Fig. 5.9 Linear ld-Vg characteristics comparing measurement and simulation results
including source/drain contact resistance ...... .................... ... .... ... ............ 75
Fig. 5 .10 Final two-dimensional structure and doping profile of a 0 .19- µ m nMOSFET.
(Unit; µ m for axes and cm"3 for contour lines) ......................... .... .. .. ....... 75
Fig. 5.11 !d-Vd characteristics comparing measurement and simulation results using the
GHDM by GALENE-III for a 0.19- µ m nMOSFET. (Lines: measurement results,
symbols: simulation results) ............. ........ ................... ...... .. ... .... ........ 78
Fig. 5 .12 Substrate current characteristics comparing measurement and simulation results
using the full-band MC simulator FALCON for a 0. 19- µ m nMOSFET. (Lines:
measurement results, symbols: simulation results) .... ..... ......... ................... 78
Fig. 5.13 ld-Vd characteristics comparing measurement and predicted simulation results
using the GHDM by GALENE-111 for a different 0.19- µ m nMOSFET of whichsource/drain doping concentration is scaled to one-tenth. (Lines: measurement
results, symbols: simulation results) .... ......... .................. .. ...... ... ............79
Fig. 5 .14 Substrate current characteristics comparing measurement and predictedsimulation results using the full-band MC simulator FALCON for a different 0.19µ m nMOSFET of which source/drain doping concentration is scaled to one-tenth.

(Lines: measurement results, symbols: simulation results) ... ...... ... ..... ......... . 80
Fig. 6.1 Flowchart of the acceptance/rejection method for the selection of the final state
after scattering (random number r uniformly distributed in (0, 1]) ................... 84
Fig. 6.2 Substrate current and CPU times for (a) a 0.18 µ m nMOSFET and (b) a 1.0 µ m
nMOSFET for different drain voltages. (Lines: experiment, Symbol : FB-MC
sin1ulation) .. . ... .......................... . ........ .. ... ..... ................................ 86
Fig. 6.3 Schematic potential and electric fields for the II coefficient (left), at the Si/ Si02interface of a MOSFET (center) and for the quantum yield experiment (right) .... 91
Fig. 6.4 II coefficient versus inverse electric field for bulk silicon (solid line) as
giv en by van Overstratton, for MOSFETs (dashed line) and CCDs (dottedline) by Slotboom (133] and FB-MC results (symbol) .. . .... .. ............... 93
Fig. 6.5 Substrate current versus gate voltage for the shallow source/drain extension 0. 16 µm-nMOSFET (Vii=l .5,2.0,2.5,3.0,3.5V). (Lines: measurement, 0 : FB-MC withXl

surface roughness scattering,+ FB-MC without surface roughness scattering) .... 93
Fig. 6.6 Electric field (solid line) and II generation rate for the case B of the CCD
experiment [ 133] calculated with the LF model based on bulk parameters (dottedline), based on surface parameters (dashed line) and FB-MC results (dashed dottedline) ................................... . ....................................................... 95
Fig. 6.7 Multiplication factor for case B of the CCD, measured (solid line) [133], calculatedwith the LF model based on bulk parameters (dotted line), based on surface
parameters (dashed line) and FB-MC results (symbol) ....................... . ........ 96
Fig. 6.8 Confining electric field averaged with the II generation rate for the 0.16 µ. mnMOSFET .................................................. ... ............................... 97
Fig. 7.1 Electron distribution in a 0.16 µ. m-nMOSFET at different energy level. (Vd=2.5V,

Vg=l .5V, axes unit: µ m, contour line unit: cm·3 , dashed line denotes pnjunction) .................................................................................... l 01
Fig. 7.2 Hole distribution in a 0.16µ. m-nMOSFET at different energy level. (Vd=2.5V,
Vg=l.5V, axes unit: µ. m, contour line unit: cm·3 , dashed line denotes pnjunction) ............................................................ . ....................... l 02
Fig. 7.3 II generation rate caused by (a) electron and (b) hole. (Vd=2.5V, Vg=l.5V, axes
unit:µ m, contour line unit: s· 1cm·3, dashed line denotes pn-junction) ............. 103
Fig. 7.4 Currents of electrons and holes with certain energies hitting the Si/Si02 interface
for the 0.18 µ. m- (dashed line) and 0.16 µ m- (solid line) nMOSFETs ............ 104
Fig. 7.5 Simulated (a) Ion and (b) ti Vth versus poly-gate length characteristics for fourkinds of nMOSFET. (A: surface peak channel with source/drain extension x,=0.05µ m, B: surface peak channel with source/drain extension x1=0.03 µ. m, C: steep
retrograde channel with source/drain extension x1=0.05 µ m, D: steep retrograde
channel with source/drain extension xr0.03 µ m) ........ . ......... . ....... . .. ....... 105

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Chapter 1

Introduction

1.1 Motivation

In the field of high-speed silicon devices, silicon bipolar junction
transistors (BJTs) had played a major role from the 1970s to the end of the
1980s. However, in the 1990s complementary metal-oxide-semiconductor(CMOS) field effect transistors (FETs) have been replacing their position.
This dissertation tries to clarify the reason why BJTs were suitable for highspeed operation through the development of siliconbipolar device

technologies and physics-based device analyses. This dissertation also reveals
the reason why they were replaced by CMOS transistors. Then, to achieve
high-speed CMOS transistors, this dissertation makes clear the needs for thedevice design methodology based on accurate physical device modeling aswell as the importance of inverse modeling to determine device structure
consistent with all experimental results. Also is made distinct the necessity
for both particle-based full-band Monte Carlo and fluid-based generalizedhydrodynamic models for accurate device simulation. Finally, the MOSFET
design strategy for deep submicron regime will be discussed.
1.2 Scope and Organization

Chapter 2 describes the development of high-speed silicon bipolar
technology and physics-based BJT design. In the case of BJTs, it was easy to
reduce base width by employing a successive p-type and n-type diffusion
technique that can result in the base thickness of 50nm or so. By introducing
various kinds of self-alignment techniques such as deep trench isolation anddouble polysilicon self-aligned structures, BJTs enjoyed the benefit of shorttransit time i.e. high cutoff frequency caused by the thin base without needing
sophisticated lithography tools. As a result, they achieved more competitive
position to compound semiconductor devices and conquered the major
position in the field of high-speed large scale integrations (LSis).
Chapter 3 discusses circuit performance for high-speed BJT and clarifies
its advantages and limiting factors. The most effective circuit to explore thehigh-speed performance of BJT is emitter-coupled logic (ECL). In the case of1

ECL, emitter-coupled pair transistors are switched in accordance with input
signal applied to base without bringing them into the saturation operation
mode. This means each transistor . benefits from quick discharging andswitching. By using drift-diffusion-based device/circuit mixed simulator, theultimate performance of an ECL-like circuit was investigated for double
polysilicon self-aligned BJTs. As a result, it was found that the circuit delay
was no more limited by cutoff frequency or the forward transit time of the
BJT itself, but parasitic capacitance associated with a collector pull-up
resistor.

In

other

words,

collector-substratecapacitanceandloadedcapacitance including an emitter follower input capacitance limit the circuit
delay. Therefore, the reduction of base-collector and/or collector-substratecapacitance is more effective than the increment of cutoff frequency. On theother hand, in the case of ideal condition without any parasitic capacitancewith the collector pull-up resistor, the switching current of around 100 µA foreach gate is still needed to achieve minimum gate delay. This indicates that,in the case of one-million-gate circuit, the chip will dissipate lOOA in total,
far beyond the practical air-cooling limit. Accordingly, BJTs were not able toenjoy the progress of microfabrication technology brought by deep submicron
lithography.
Chapter 4 points out the reason why CMOS transistors replaced BJTs
even in the high-speed field . CMOS transistor is an ideal device from theviewpoint of power dissipation because it dissipates power only whenswitching. The major drawback to the CMOS transistor was the larger channel
length that was defined by minimum lithographic pattern. In the 1980s thechannel length was from one to two orders larger than the base width of BJT,
bringing MOSFETs lower cutoff frequency and larger transit time thanbipolar devices. However, the dramatic progress of optical lithography has

made it possible to realize deep submicron channel length. This results inhigher driving current as well as shorter switching time even by CMOS
circuits. Microprocessor is the main device benefited by this advantage, andhigh-speed LSis have been realized. Fundamental technological features forhigh performance CMOS devices are retrograde well, dual-gate surface
channel MOSFETs and a salicide structure. The former two features canrealize high freedom for choosing supply voltage and threshold voltage design
independently on the well structure especially in lower supply voltage2

regimes. The latter feature reduces parasitic resistance and, if combined withshallow trench isolation, parasitic capacitance associated with source/ drainjunction can be reduced. From the device-design point of view, optimization
for higher driving current with lower off-leakage current as well as hotcarrier-induced degradation immunity is the most important concern.
Chapter 5 describes the requirement of precise knowledge of the device
that is made by split lot experiments to design MOSFET effectively. For thispurpose, inverse modeling is a powerful technique. The concept of inverse
modeling, the procedure and application to quarter micron nMOSFETs aredemonstrated. By using inversely modeled information, driving current andhot carrier properties can be predicted and successfully designed.
Chapter 6 discusses what kind of device model should be used todescribe carrier transport in high-field regime to analyze driving current or
the saturation drain current of MOSFETs. We must use accurate device modelfor this operation regime. To this end drift-diffusion model is not enoughbecause thi s model assumes equilibrium carrier transport inside device. Not
only fluid-model-based generalized hydrodynamic model but also particlebased first-principle model using ensemble full-band Monte Carlo simulation
is inevitable. The background and concept of these approaches are also
discussed and clarified. Moreover, hot carrier property and its model
hierarchy is discussed based on the full-band Monte Carlo simulation analysis.
Also is studied the previously proposed surface impact ionization model
different from the bulk, and it is demonstrated that there is no experimental
evidence for the difference between the surface and bulk impact ionization insilicon. The difference was only caused by an unsound application of local
field model and just was an artifact.
Finally, in Chapter 7, by employing these sophisticated models, thesaturation drain current as well as the hot carrier effects of subquarter micron
MOSFETs are studied. Then, MOSFET design strategy for the 0.1- µ m
regime is discussed, and the importance of shallow junction for source/drain
extension is demonstrated.
In Chapter 8 as conclusion, the summary and future works for the sub0.1µ m regime are pointed out.

3

I

Chapter 2

Development of High-Speed Silicon Bipolar Devices

2.1 Historical BackgroundTo achieve high-speed operation, silicon bipolar devices have conquered
numerous process-technological obstacles. Since the discovery of pointcontact transistor by Bardeen and Brattain in 194 7 and the invention of
bipolar junction transistor by Shockley in 1948, several valuable process
innovations have been introduced. The first notable step was the developmentof integrated circuits and a planar technique by the end of the 1950s. Isolationof pn-junction and new epitaxial growth techniques had triggered a rapid
progress of bipolar ICs in the industry. Around 1970, two new process
techniques had been developed. One was the LOCOS (local oxidation ofsilicon) technique [1]. By employing LOCOS isolation instead of junction
isolation, dimensions of isolation regions were drastically reduced and thepacking density was much improved. The other was the DOPOS (doped
polysilicon) technique, which was the first polysilicon emitter process [2].
The DOPOS technique used impurity-doped polysilicon not only as an emitter
diffusion source but also as an emitter electrode. The DOPOS made possible
the achievement of much narrower and shallower emitters than those realized
by a conventional washed emitter technique , which had been the ultimate
refinement of the planar technique. In the 1970s, polysilicon techniques were
further improved so as to achieve various applications for bipolar devices. A
polysilicon self-aligned (PSA) process technique was one of the mostsophisticated example [3]. The PSA technique used a polysilicon baseelectrode as well as a graft base diffusion source, exactly as the polysiliconemitter. Another notable property of the PSA technique was the application of

the LOCOS technique to polysilicon films. By employing the PSA technique,the first fully self-aligned device structure that did not use tight lithographic
design rules was demonstrated.
In the early 1980s, new etching techniques were demonstrated; namely
the anisotropic dry etching techniques, such as reactive ion etching (RIE). By
using this technique, first, steep and narrow grooves or trenches were easily
realized for much improved isolation. Trench isolation began to replace
conventional oxide isolation, resulting in higher packing densities and smaller4

collector-substrate capacitance.

Second, the so-called sidewall

spacertechnique was developed , allowing self-aligned compact isolation between
stacking conducting layers of materials such as doped polysilicon. By
combining the sidewall spacer techniques and the polysilicon base and emitter,double polysilicon self-aligned processes emerged. A submicron distance
between the emitter and the base electrode was easily realized to achieve
lower base-collector capacitance and lower base resistance than with any
previous device structure. Anisotropic dry etching was also used to form steep
and narrow monosilicon mesas to act as intrinsic base and emitter regions. By
introducing sidewall contacted polysilicon base electrodes to the mesas, a new,sophisticated device structure was proposed. A sidewall base electrodecontact structure (SICOS) was another approach to achieve fully self-aligned
process. The SICOS was intended to realize an ideal one-dimensional device
structure suitable for upward operation. Other sidewall base contact structures
were also demonstrated by selective epitaxial growth as well as simultaneous
epitaxial polysilicon growth in steep grooves.
Self-aligned processes as well as polysilicon emitter have been standard
techniques for high performance silicon bipolar IC fabrication. Great efforts
have been spent to improve these techniques and many researchers have been
investigating the underlying device physics.

2.2 Trench Isolation Techniques
2.2. l Introduction
Isolation is one of the key techniques in integrated circuit processes.
When the first integrated circuit was invented by Kilby, two transistors andsome resistors made in a monolithic germanium chip were partially separated
by a slot and air. However, with the advent of the planar technique, pnjunction isolation became the major technique because Kilby's non-planar
structure was unfavorable for wiring process. Another approach was also tried
to improve the surface topography of air-isolated devices. This is the socalled dielectric isolation utili zing groove etching. Air isolation slots were
replaced by dielectric substrates in which active semiconductor islands were
sustained. The dielectric isolation achieved rather planar surfaces, but it was5too complicated for conventional devices. Only for very high voltage devices
has this technique been used.
After the LOCOS technique was developed, pn-junction isolation was
graduall y replaced by oxide isolation. At the same time there was a revival ofgroove isolation. In this case only laterally isolated regions were formed bygrooves filled with dielectric materials, and the substrate was isolated by pnjunction. Grooves were formed by anisotropic chemical etching. Both of these
isolation techniques achieved higher packing density than pn-junctionisolated devices. The scaling concept was also employed to achieve large
scale integration and high performance devices. When the devices are scaled,
not only active regions but also inactive regions such as the isolation should
be reduced. In the case of LOCOS isolation, the so-called bird's beak enlarges
the inactive regions. The length of the bird's beak is dependent on the
thickness of oxide and cannot be reduced proportionally to the scaling ratio.
This was the ultimate limitation of oxide isolation. On the other hand, thegroove isolation utilized anisotropically etched V-shaped grooves for
isolation using alkaline etchant applied to (100) silicon surface. The Vgroove's depth is 70% of its width, so the reduction of isolation regions islimited by the groove depth necessary to keep enough breakdown voltage.
In order to overcome these problems of conventional isolation
techniques, the bird's beak free and width-independent isolation scheme wasmost important, the result was the advent of trench isolation. This is a newtechnology employing novel etching techniques such as RIE to form narrowand steep U-shaped grooves, or trenches for isolation, but its root is based on
the classical idea of dielectric isolation.
Though a practical trench isolation technique was first disclosed in1978 [4], we demonstrated its application to practical devices for the first time
early in the 1980s[5]. Since the first application of trench isolation to lkb
ECL static RAMs in 1982 [5], many bipolar devices have been fabricated byvarious kinds of trench isolation techniques. In the case .of bipolar devices,
some trench isolation techniques have been used in volume production since
the early stage of the development, though trench isolation for MOS devices
are only introduced recently as a shallow trench isolation technique.
In the following subsections, process technologies, device structures,
application to devices and benefits and limiting aspects of trench isolation for
6

bipolar devices will be discussed.
2.2.2 Trench Isolation by Oxide and Polysilicon
Typical trench isolation techniques consist of three major process steps[5]. These are trench etching, trench filling and planarization. Figure 2.1
shows an example of process steps. As usual , an n+ buried layer and an nepitaxial layer are formed on a p-type substrate. On the n- epitaxial layer, anitride layer with thin pad oxide is deposited and a masking layer for trench
etching is also deposited. After the isolation pattern is formed, trench etching
follows using anisotropic dry etching such as RIE. The trenches penetrate
both the epitaxial and buried layers to reach the p-type substrate. The insideof the trenches is then oxidized to accomplish electrical isolation. After that,trenches are buried with undoped polysilicon. Excess polysilicon is polished
off until the nitride layer appears. Finally the surface of polysilicon isoxidized for capping. The trenches are filled with oxide and polysilicon.
Trench etching is one of the most important processes in trench isolation
techniques. The typical structure of narrow and deep trenches for isolation isachieved by anisotropic plasma etching. RIE is widely used for this purpose.
The etching conditions should be carefully optimized to avoid unfavorable
trench shapes. Figure 2.2 shows examples of maladapted trench structures.
Figure 2.2(a) shows so-called 'black-silicon' or needle-like silicon residues,and sub-trench at the corners of bottom edges of trenches is shown in Fig.
2.2(b). Figure 2.2(c) is the case of laterally-etched undercut that occurs at thehighly doped n+ buried layer. All of these unfavorable shapes cause large
leakage current between isolated elements. Figure 2.2(d) shows bowing. In
this case the trenches are not completely buried by filler materials and voids
occur in isolation regions. These voids may become sharp crevices after theplanarization step finishes. They cause bad metallization step coverage.
These trench shapes are strongly dependent on gas species, pressure,flow rates and power in RIE processes [6,7]. These etching conditions are notuniversal, so they should be optimized according to etching systems.
Trench filling and planarization processes are also important. Trenches
should be filled completely with filler materials. If not, nonplanar surfaces
occur after excess filler materials are removed. The filler materials should7l l l l
,

1

s i02

Si 3

• •
•

•

•

•

CVD
Poly silicon

•

.. .

Fig. 2. I Fabrication process steps of a typical trench isolation technique .

8_n_e_p1n+buried layer_.;----......

\ p sub.

/f\' .......... -- - ... -

I
/

(a)

(b)

(c)

(d)

Fig. 2.2 Unfavorable trench shapes caused by trench etching.
(a) Black silicon (b) Sub-trench (c) Laterally etched undercut (d) Bowing

also be deposited as uniformly as possible. There are variety of filler
materials such as CVD (chemical vapor deposition) oxide, CVD nitride andundoped polysilicon. When CVD oxide is used, trench shapes, especially the
sidewall taper should be optimized because CVD oxide does not show goodstep coverage inside trenches [4]. Until now, instead of CVD oxide, bias
sputtered oxide, ECR (electron cyclotron resonance) plasma enhanced CVD
oxide and boron-phosphorus silicate glass have been tried. Nevertheless, lowpressure CVD polysilicon shows excellent step coverage although it is not acomplete insulator. Undoped polysilicon is widely used as the filler material.
CVD nitride is a good insulator, but because of its high tension it is
impossible to fill trenches completely. Nitride is often used as a spacer
9between thermal oxide of trench surfaces and undoped polysilicon. Excess
filler materials are removed to attain a planar surface by controlled etch-backtechniquesorchemical-mechanical polishing(CMP)

technique.

This

planarization process requires high uniformity. In our experience, polishingtechniques are superior to controlled etch-back processes, resulting in recent
large stream of CMP process as a major planarizing technique.
Figure 2.3 shows the typical trench-isolated structures. Figure 2.3(a) is called
DG I (deep groove isolation) [4]. Trenches are etched by RIE using Cl 2/ Ar gas
mixture. Trench surfaces are oxidized and filled with CVD oxide. Excess
oxide was removed by a controlled etch-back technique. Figure 2.3(b) shows
our IOP-II (isolation by oxide and polysilicon; second version) (5). Trenches
are etched by RIE and filled with oxide and polysilicon. Excess polysilicon isremoved by a chemical-mechanical polishing technique. TOP-II is anadvanced version of conventional IOP using V-grooves, and only V-groove
etching was replaced by trench etching. Figure 2.3(c) exhibits U-Iso (Ugroove isolation) [8]. In this case, the trench is not U-shaped but Y-shaped.
The trench etching process consists of two steps. First, anisotropic chemical
etching of (I 00) surface is employed to form an overhung structure using anitride layer with side-etched pad oxide as a mask. Then anisotropic dry
etching such as reactive sputter etching using a CCli0 2 gas mixture follows
for trenches to penetrate an n+ buried layer. The inside of the trenches isoxidized and the second nitride layer is deposited to cover the trench surface.
Trenches are filled with undoped polysilicon. Excess polysilicon is removed
by a controlled etch-back technique.
The above-mentioned trench-isolated structures may be called the first
generation. In these trench isolation techniques, one attempts to reduce only
the isolation regions; other inactive regions such as field regions for wiring orshallow isolation for base and collector-reach-through regions are not taken
into account. As far as memory devices are concerned, there is no serious
problem. However, for high performance logic devices, those parasitic
inactive regions are fatal disadvantages for switching speeds. In order toovercome these disadvantages of the first generation, some processmodification followed. In the next subsection, process technologies anddevice structures of advanced trench isolation techniques, which may becalled the second generation, will be described.
10

CVD oxide

polySi

oxide

oxide

(b)

p 0 ly s i oxide

nitride~-rz:zzz.~(c)n+Fig. 2.3 Typical trench-isolated structures.
(a) DGI (4) (b) IOP-II (5) (c) U-lso (8)11J

2.2.3 Trench Isolation with Thick Field Oxide
Process modifications for the second generation may be roughly divided
into two types. One is the combination of LOCOS or ROX (recessed oxide)with deep trenches, and the other is the combination of shallow trenches withdeep ones. For instance, Figure 2.4 shows the process steps of our U-FOX( U-groove isolation with thick field oxide, renamed from IOP-L) or anadvanced version of IOP-11, combining LOCOS with trench isolation [9].
After the formation of an n· epitaxial layer by conventional means, its surface
is selectively oxidized except base, collector-reach-through regions and so on,
using the LOCOS technique. Then a new nitride layer and a masking layer fortrench etching are deposited. They are removed at the isolation regions andtrench etching follows. After the trenches have been etched, their surfaces areoxidized and filled with undoped polysilicon. Excess polysilicon is polished
off until the polysilicon not on the isolation regions is completely removed.
Then capping oxidation is performed. This process step sequence, or the
trench etching after the field LOCOS formation is favorable to the otheroption, or the LOCOS-after-trench process, avoiding nonplanar surface
topography as well as stress induced crystalline defects caused by cappingoxidation. The detail will be discussed later again.
To compare our U-FOX process with other approaches, anothertechnique is shown in Fig. 2.5 (10). In this technique, deep trenches fordevice isolation are first etched, using a thick oxide layer as a mask. Thenthe masking layer is selectively removed by the second isolation patterns,
which contain base- and collector-reach-through isolation and field regions.
Again trench etching is performed to give no penetrating shallow trenches.
Deep trenches penetrate then+ buried layer to reach also the p-type substrate.

Both deep and shallow trenches are buried with CVD oxide. The CVD oxide
itself does not achieve good step coverage in the trenches, but by optimizing
the distances between deep trenches in shallow ones, voids in the deep
trenches are elaborately covered by over-grown oxide. Excess oxide isremoved by a controlled etch-back technique in just the same way asreported for simplified buried oxide (BOX) isolation for MOS devices (11 ).

12

~'-fi_e '_d_a_x_"i-d__:_Pi_r_a_s_k_i_-1a~_y_er_
9

__

(a) .

n• b. I.
p- s ub .

(b}. . . . . . . . . . . . . . . . . . . . . . . . . . . ..
......
. . . . . . und oped poly s il ico n -:-:-: -:-:-:-:-:. . . . . . . .. . . . . . . . . .
•

•

t

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

(c)
n+p

-

... -- _.

oxj de(d)n..

Fig. 2.4 Fabri cation process steps of U-FOX.

13

•

•

•

•

..

n

1a1

n

n

n

n+
p

n

lbl

n+

n+

p

2nd Resist

(CJ

n+

p

Fig. 2.5 Fabrication process steps of [10].

There are also some structural modifications of these techniques.
Figure 2.6 shows structural variations of modified trench-isolated devices inthe second generation. Figure 2.6(a) is an example of deep trench isolation.
combined with recessed oxide. The recessed oxide is formed by recessing

silicon, using RIE followed by oxidation. Deep trenches are then etched,covered with a thin thermal oxide layer and filled with CVD oxide. In somecases there are voids in the middle of isolation regions [ 12, 13]. Figure 2. 6(b)is an example of a dual-depth trench-isolated structure (14]. Shallower
trenches, filled with oxide, nitride, and polysilicon isolate transistors andSchottky barrier diodes, and they may be able to isolate base and collectorreach-through regions. Figure 2.6(c) shows our U-FOX structure. LOCOS
technique is used for base and collector-reach-through isolation and field
14

oxide for wiring regions. Figure 2.6(d) is the final structure of the techniquementioned above (10]. Figure 2.6(e) is a modification of Fig. 2.6(a). As afiller material for deep trenches , CVD oxide is replaced by selective episilicon (15,16]. In this case, trenches of variable width can be filled andplanarized at the same process step. There are other variations on advanced
trench-isolated structures [ 17,18]. In ref. [ 17], field oxidation, as well as
capping oxidation of trench-filling polysilicon, performed after excess
polysilicon is removed by a controlled etch-back technique. In order to bury
the crevices which occur along the trench-edge surface, an etch-backtechnique of reflow glass is used The final device structure resembles Fig.
2.6(d). In ref. (18], vertical pnp transistors are formed as well as
conventional npn transistors, and new advantageous device structure isachieved. The main drawbacks to these techniques are rather complicateddual-depth trench etching process, poor step coverage of CVD oxide inside
trenches and larger collector-substrate parasitic capacitance caused by
selective epi-trench filling process.
2.2.4 Benefits and Device Performance
The trench isolation techniques mentioned above have a number ofadvantages, and bipolar devices using them have achieved higher performance
than conventionally isolated devices
First, higher packing density than in conventional isolation is achieved
because the trench depth is almost independent of its width and the bird's
beak is reduced much more than in LOCOS. The p+ channel stop layers arecompletely separated from n+ buried layers. Therefore, even if the trench
width is reduced, there is enough space that a depletion layer can sustain highbreakdown voltage. Also, the complete separation of the channel stop layers
and the n+ buried layers makes collector-substrate parasitic capacitancesmaller. Because the n+ buried layer islands are self-aligned to isolation
trenches, there is no mask alignment step between a buried layer and an
isolation pattern, and planar collector-substrate pn-junction is achieved,
which is also favorable for the reduction of its parasitic capacitance.

15

8

c

E

(a)

Al

SBD

E

B,.

(b)
Si 3N4

P·SUB

c

E

B

(c)
n+

Base

EmitterCollector

(d)

8

c

E

(e)

p

Fig. 2.6 Modified trench-isolated structures.
(a) [12,1 3] (b) [14] (c) [9] (d) [10] (e) [15 , 16]16

Table 2.1 is an example of device performance demonstrated by I kb
ECL (emitter coupled logic) static RAM (random access memory) using our
IOP-II [5]. The V-groove-based IOP device was shrunk at the ratios of 0.8,
0. 7 and 0.6. Trench width can be shrunk by the same factor as the active
regions, from 5 µ m of the V-groove to 4, 3.5 and 3 µ m of the trenches,
respectively. ·Because of this linear shrink, the typical access time can be
reduced in proportion to the shrinking factor. Our IOP-II also realized various
ECL static RAMs from 4kb to 64kb generations for high-speed cache RAM
applications [ 19-24]. On the other hand, the advantage of trench isolation wasshown using ring oscillator circuits by other researchers. The basic gate delayof an ECL circuit using with trench isolation was nearly 30% improved
compared with oxide isolation [8]Table 2.1 Typical address access time of linear shrunk I kb ECL RAM using IOP-11.

Shrink ratio

Isolation width ( µ m)

Access time (ns)Technology

1.0

5.0

7.4

IOP(V-groove)

0.8

4.0

5.8

IOP-II(Trench)

0.7

3.5

4.8

IOP-II(Trench)

0.6

3.0

4.4

IOP-Il(Trench)

Not only trench structures but also the modification in the second
generation have much improved device performance. By introducing thickfield oxide for wiring regions, parasitic capacitance between wiring layers
and substrate have been reduced. This approach is suitable for logic devices.
As well as the reduction of wiring-substrate capacitance, base-collector

parasitic capacitance is also reduced because LOCOS or shallow-trench-filled
oxide surrounds the base region to achieve a so-called walled base structure.
In the case of our U-FOX structure, the wiring delay time of 50ps/mm wasachieved for the first and second metallization layers using a 1.6-um wide
wiring pattern. A loaded gate delay of 323ps (basic delay= l 77 ps, FI=F0=3,
wiring length=2mm) using an ECL circuit was obtained at a switching currentof 0.2mA/gate [9]. The U-FOX structure made possible 3000- and 10,000gate ECL logic LSis for the Fujitsu mainframe computer FACOM-M780.
17

Other examples demonstrated by trench isolation techniques are listed in ref[25].
2.2.5 Limiting Aspects and Recent Improvements
Trench isolation is now a must for high performance bipolar devices. In
the early stage of the development, there were several problems, and thosewere broadly divided into two categories. One was the structural problem
and the other was the electrical problem. They were often strongly related
and the former, in particular, is apt to influence the latter. As previously
described in subsection 2.2.2, if the trench etching process is not optimized,
trench shapes may change variously. The structural problems without
electrical ones are usually bad step coverage of metallization layers caused
by voids or sharp crevices on isolation regions. To avoid these problems
trench shape should not show bowing or overhung and over etching in etchback processes to remove the excess filler materials should be carefully
controlled. Other maladapted trench structures such as black silicon, subtrench, laterally-etched undercut of highly doped buried layers often
accompany crystalline defects. These crystalline defects cause large leakage
current between isolated elements. Thus, trench-etching processes should be
optimized thoroughly to achieve the best conditions.
The most serious problem was how to get rid of isolation leakage
caused by crystalline defects. The crystalline defects often occur at stressconcentrated places such as sharp-edged corners caused by unfavorable
trench structures. However, even if the trench shapes show the ideal
structure, crystalline defects may sometimes appear. They seem to be
influenced by ion-implantation-induced damages and inadequate subsequent

heat processes. The use of Y-shaped trenches instead of U-shaped trenches is
one way to avoid stress-concentrated right-angled corners around top edgesof trenches at the expense of packing density [26). In relation to trench
isolation combined with LOCOS, some process modifications were also
proposed. One is the nitride liner between the oxide of the trench surface andfilled polysilicon [27], and another was the combination of selective
polysilicon oxidation (SEPOX) with trenches, which was applied to a CMOS
static RAM [28]. In both of these techniques, selective oxidation of field18

regions is performed at the same time as capping oxidation. Without thesemodifications large stress occurs at the top corner of trenches when single
crystalline silicon and filled polysilicon are oxidized simultaneous ly, andthey causes crystalline defects. Most recent approach to avoid large stress by
capping oxidation is to use soft reflow glass to fill the trench. Boronphosphorus silicate glass can be used for such purpose [29]2.2.6 Conclusion
Trench isolation is one of the key techniques in high performance
bipolar devices. It realizes higher packing density and smaller collectorsubstrate parasitic capacitance than conventional isolation techniques. It also
reduces wiring-substrate and base-collector parasitic capacitance withprocess modifications such as combining thick field oxide for wiring
regions.
2.3 Polysilicoo Self-Aligned Structures

2.3.1 Introduction
As describedin the historicalbackground section, self-aligned

techniques using polysilicon is another key feature to realize highperformance silicon BJTs. These self-aligned techniques consist of double
polysilicon and/or single polysilicon processes. Moreover, polysiliconemitter is also important to achieve shallow emitter that results in high cutoff
frequency. The polysilicon emitter is a root for wide-gap emitter, or emitterbase heterojunction BJT. In this section, these self-aligned and polysiliconrelated device structures will be discussed.
2.3.2 Double Polysilicon Self-Aligned Structure
In this subsection, various kinds of double-polysilicon self-al igned
processes and related device structures are discussed. The double polysilicon
self-aligned processes are roughly divided into three classes depending on thenumber of masks used to form the emitter and base regions. A one-mask
19

process can define not only the emitter and intrinsic base region, but also the
extrinsic (graft) base region by using the same mask. A super self-aligned
technology (SST) is a typical example of this type [30]. In the case of a twomask process, the extrinsic base regions are defined by a mask different fromthat of the emitter and intrinsic base region. Until now, these processes arewidely used in advanced bipolar IC production. Finally, Three-mask
processes use different masks to define the emitter, intrinsic base andextrinsic base regions, respectively.
2.3.2.1 One-Mask Process
A typical and the most successful one-mask process is the so-called SST.
The first version of this process was reported in 1980 [30], and some process
improvements have since been introduced. Major improvement was reported
in 1983 such as advanced SST [31 ]. Figure 2. 7 shows the fabrication steps of
the SST-I A (an advanced version of SST- I) process. After growing n-typeepitaxial layer on a p-type substrate and oxide isolation formation, an oxide
layer, a nitride layer and a polysilicon layer are deposited consecutively. The
polysilicon layer is selectively oxidized (above the oxide isolation regions).
The polysilicon in the area corresponding to the transistor emitter regions is
etched away (Fig. 2.7(a)), and then oxidized. The nitride is side-etchedfollowed by etching of the underneath oxide (Fig. 2. 7(b )). New polysilicon isdeposited to fill the overhung space and to connect the first polysilicon to theepitaxial layer. The excess polysilicon is etched away (Fig. 2.7(c)). Thermaloxide is grown and the intrinsic base region is formed by boron ion
implantation through the oxide. Then CVD oxide and polysilicon aredeposited. The emitter window is opened by dry etching (Fig. 2.7(d)). Finally,

the emitter area is diffused through the arsenic-implanted polysilicon layer(Fig. 2.7(e)).

20,....--- p+ poly Si{a )- Si 02~~~~.r--7-r-/-;:z:.:z::z:::z:::::z::::z:::z:=::z::77-r-"T"'?.-- - S i3 N4N- epi- Si 02N+
u-~-:----'-~~'\...L.-4-LL

p- subpoly Si( b){c }Undoped poly Si( d)C

N+ poly Si

E(e)Fig. 2.7 SST-IA fab rication steps [3 1).

21

8

N+ poly Si

p+ poly Si

B

B

Metal
-

~~~~--:----:""""'":'"(.- Si 02

p- sub
N selectively implanted collector
Fig. 2.8 Cross-sectional view of the SST-I B transistor with selectively implanted
pedestal collector (32).

In the SST process, all the active regions are defined by a single mask
pattern. The extrinsic base region is determined by the side-etched area in the
nitride layer under the base-electrode polysilicon. The distance between theemitter and the base electrode is about the thickness of the CVD oxide andpolysilicon. The emitter-window width can easily be made narrower than theoriginal mask feature to achieve a submicron width. As a result, the basecollector parasitic capacitance and extrinsic base resistance of the SSTtransistor are dramatically reduced. In addition to obtaining a higher cutoff
frequency, a selectively implanted pedestal collector process is used alongwith a low energy ion implantation for the intrinsic base region. Figure 2.8
shows the schematic cross-section of the improved structure. By using thisimproved process, named SST-lB, a peak cutoff frequency of 25.7 GHz(Vce=3V) was obtained, and a minimum basic gate de lay time of 20.5 ps by an
NTL circuit was demonstrated at a power dissipation of 2.32 mW/gate. At thesame time, a minimum basic gate delay time of 34. l ps by an ECL circuit at a22

power dissipation of 7.54 mW/gate was also reported [32]. The drawback to
the SST process is that there is a slight difficulty in defining a walled-basestructure to reduce the parasitic base-collector capacitance. If the walled-basestructure is required, a tight alignment control is needed between the fieldoxidation and the intrinsic-base masks at the expense of the one-mask selfalignment advantage.
Another successful one-mask process was demonstrated by depositing
the emitter polysilicon prior to the deposition of the base-electrodepolysilicon [33). Figure 2.9 shows the fabrication steps of this polysilicon
self-aligned technology. After LOCOS isolation, the intrinsic base region is
first implanted (Fig. 2.9(a)). Then, heavily implanted n-type polysilicon, CVD
oxide and nitride layers are deposited and successively etched where theintrinsic base and emitter region are defined (Fig. 2.9(b)). To isolate thesidewall of the n-type polysilicon, the second CVD oxide is deposited,followed by reactive ion etching (Fig. 2.9(c)). A second nitride is depositedand reactively etched to form a vertical nitride layer (Fig. 2.9(d)). By using
the first and second nitride as a mask, the surface of the extrinsic base area islocally oxidized, while the emitter is also driven into the intrinsic base region(Fig. 2.9(e)). The base contact window is opened by removing the nitride
layer. Then p-type doped polysilicon is deposited, which acts as the baseelectrode as well as the graft base diffusion source (Fig. 2.9(f)). By using thistechnique, a basic gate delay of 52 ps at a power dissipation of 0.16 mW/gate
employing a CML circuit was demonstrated. This process has the sameadvantages as those of the one-mask process, but there are some drawbacks
such as higher emitter series resistance caused by the polysilicon emitterelectrode without metallization, furthermore, this is an unwalled basestructure.
Other one-mask processes have been reported based on the same
fabricating sequence as the SST, for instance, as the side frame self-aligned(SFS) technology [34], or the selective diffusion by -exdiffusion (SDX)
technology [35]

23

p(a)

__

/

~..__z N_-~~+-~_@___~---.J --=--- Si 0 2
P-sub~- Si3N4..-----.... ·.·Si 02
N+ poly Si

( b)

(c )

( d}

{ e)

B

E

c

p+ poly Si{f )Fig. 2.9 Fabrication steps of the new polysilicon self-aligned process (33].

24

2.3.2.2 Two-Mask Process
Two-mask processes have been widely used to achieve the double
polysilicon self-aligned structures. The first and simplest example wasreported in 1980 as a self-aligned transistor [36]. Figure 2.10 shows its
fabrication steps. P-type boron doped polysilicon and CVD oxide layers aredeposited on an n-type epitaxial layer after conventional recessed oxide
isolation. The recessed oxide isolation defines not only collector reachthrough regions but also the total base regions (Fig. 2.10 (a)). The CVD oxideand polysilicon layers are preferentially etched by using an intrinsic-basewindow opening mask (Fig. 2.1 O(b )). The surface of the epitaxial layer andthe sidewall of polysilicon are oxidized, while the extrinsic (graft) base isdiffused from the boron_.doped polysilicon (Fig. 2.lO(c)). The intrinsic baseregion is opened by RIE. Finally, the intrinsic base is ion-implanted, and theemitter is also diffused into the same region (Fig. 2.lO(d)). Since this early
development, numerous process modifications and improvements have been
introduced by a number of researchers. These processes have been given
various names such as SAPT [17], OXIS-III [37], SDD [38], MOSAIC-III[39], ESPER [40), BSA [41] and many others [42-47].
The two-mask process uses different masks for the extrinsic (graft) baseand intrinsic base. Therefore, the walled-base structure can be easily obtained
without using a complicated side-etching technique, although this is at theexpense of alignment tolerance. Other properties of the two-mask processes
are fundamentally the same as those of the one-mask process. The mostsignificant and careful process control is required for the intrinsic-baseformation, the sidewall spacer etching, and the intrinsic base diffusion. There
are two options for the intrinsic base diffusion step and the sidewall-spaceretching step. One is to have the intrinsic base implantation prior to thesidewall spacer formation, and the other is to reverse the sequence of the two
steps. In the case of the first process sequence, the intrinsic base region is
implanted just adjacent to the extrinsic base. Because the extrinsic base isalready diffused vertically and laterally toward the intrinsic base region, therequisite low resistance cross-linking region between the intrinsic base andthe extrinsic base is stably obtained. Moreover, the lateral-encroachment of
the extrinsic base region can be covered by the sidewall spacer, which25

77777777/77777~ Si 02........... . ........ · .· .· . . .,___ p+ poly s1·. .. . . .. . . . .. . .

.......;---

(a)

( b)

(c )

( d)

Fig. 2. 10 Fabrication steps of the self-aligned transistor process [36].

26eliminates any emitter-base tunneling leakage current and ensures a highemitter-base reverse breakdown voltage. However, attention should be paid tothe sidewall-spacer-etching step to avoid overetching, because the intrinsic
base region is damaged and the base depth might be changed.
In the second process sequence, overetching of the sidewall spacer does
not damage the intrinsic base region, but the extrinsic base diffusion must be
carefully controlled. Too much lateral encroachment of the extrinsic baseresults in highly doped pn-junction at the emitter periphery, causing not only
reverse, but also forward tunneling leakage current [48]. Also caused isunfavorable degradation of de current gain as well as that of transientcharacteristics [49,50]. However, the peripheral punchthrough occurs when
the cross-linking region between the intrinsic and extrinsic base is notsatisfactorily diffused [51 ].
To avoid these contradictory problems, some process modifications havebeen reported to combine light-coupling ion implantation and base diffusion
through polysilicon [47,52]. The coupling base is lightly implanted afteretching the CVD oxide and the base polysilicon (Fig. 2.11 (a)). Then, CVD
oxide is deposited and etched by reactive ion etching to form the sidewall
spacer, and another polysilicon layer is deposited (Fig. 2.1 l(b)). The intrinsic
base is implanted and diffused through the polysilicon, while the extrinsic
base is also driven in (Fig. 2.1 l(c)). By using this technique, a cutoff
frequency of more than 30 GHz and a minimum basic gate delay of 24 ps at aswitching current of2.2 mA/gate by an LCML circuit have been reported [47].
The drawback to this coupling base technique is its process complexity andthe difficulty in controlling the intrinsic base-emitter depth because the boron
diffusion for the intrinsic base and the arsenic diffusion for the emitter
require different annealing conditions due to the difference between therespective diffusion coefficients.
Some authors haveinvestigated reliability of two-mask double

polysilicon self-aligned devices. They reported gain degradation underreverse emitter-base bias and high current forward base-emitter bias stressconditions when transistors are irradiated by laser, X-ray and electron beams[53-56]. Although not all the degradation mechanisms are understood, if theideal factor of the base current is kept unity, the electrical characteristics arefound to be unchanged under high-current stresses. This fact suggests that if27

the cross-linking region between the intrinsic and extrinsic base is wellcontrolled, the transistors have enough reliability to operate under normal
bias and environmental conditions.

(a)

~Si02
~-'--'-__....

~_;: ·.~··~~:z::z:::z:::::i=z=:z::::z::z::::t1.,.;:·~=--·_.:.....·:.:. . .:._·.:.__···;. . :,.· ·:~ p+ poly Si....:::-=-::__;·.··:......;·
·

(b}

( c)

Fig. 2.11 Fabrication steps of the doubl e polysilicon self-aligned process using
coupling base implantation [52).

Although the two-mask process requires alignment tolerance between
the field isolation and emitter opening masks, resulting in a little larger basearea than that of the one-mask process, good circuit performance was obtained.
For example, our ESPER process realized basic gate delay of 38.8ps by ECL
circuit at a switching current of l.28mA/gate [40]. In our case, the double
polysilicon self-aligned process was combined with the U-FOX structure. By
using this technology, 15,000 gate ECL array LSI with a loaded gate delay of28

220 ps (basic delay=80 ps, FI= F0=3, wiring length=2 mm) and 64kb-RAM
with 3,000 gate ECL array LSI (SRAM access time= l.15 ns) for the Fujitsu
mainframe computer F ACOM-M 1800 and super computer VP2000 series wererealized [57]. In addition to them experimental 50,000 gate sea-of-gate ECL
array and I 00,000 gate ECL standard cell LSis were also demonstrated(58,59]2.3.2.3 Three-Mask Process
There have not been so many examples of the three-mask processreported to date. This is not only because total active base area obtained by
the three-mask process is slightly reduced but also as a result of the number ofprocess steps being increased. However, the first double-polysilicon selfaligned process was demonstrated by a three-mask process named APSA, anadvanced version of PSA (60]. Historically, this process has some value, but
because of the drawbacks to the three-mask process, few efforts have been
made to improve it. Only one approach was reported as a salicide base contact
technology (SCOT) [61] .
2.3.3 Single Polysilicon Self-Aligned Process
Basically single polysilicon process originated from the DOPOS
technique [2]. At the early stage of development, some process improvements
attained to achieve self-aligned isolation between emitter and base electrodes,
such as stepped electrode transistor (SET) or elevated electrode IC (EEIC)(62,63]. In these processes, an overhang polysilicon emitter structure isolated
the emitter polysilicon and the base electrode metallization. Another approach
was also reported to use the sidewall spacer technique just as in double
polysilicon self-aligned processes. This self-aligned process employed thesidewall spacer between the emitter polysilicon and the aluminum baseelectrode (64]. All of these are two-mask processes, and the distance between
the emitter and the base electrodes is defined by self-al igned techniques.
However, the disadvantages of these processes are nonplanar surface
topographies of the SET or the EEIC and a high emitter series resistancecausedbytheabsenceof emitter metallization.
29

Because of thesedisadvantages, development efforts essentially instead focused on improving
the double-polysilicon self -aligned processes.
A single polysilicon three-mask process has also been reported [65]. It
was demonstrated as an example to avoid cross-linking problem of double
polysilicon self-aligned processes. Figure 2.12 shows the process steps [66].
After conventional oxide isolation, a nitride layer is preferentially patternedat the portion of intrinsic-base and emitter defining region. By using thenitride layer as a mask, the epitaxial layer is slightly oxidized, and apolysilicon sidewall spacer is formed. Highly doped extrinsic base regions are
implanted (Fig. 2. l 2(a)). After the polysilicon sidewall spacer is removed, thecross-link base regions are lightly implanted (Fig. 2.12 (b)). After removal of
the nitride, intrinsic base is implanted (Fig. 2.12 (c)). Emitter is diffused froman arsenic doped polysilicon layer (Fig. 2.12(d)). The emitter polysilicon iscovered with a silicide layer and an oxide layer on top. Another mask is used
to define the emitter electrode, which is covered by the capping oxide andnew sidewall spacers. The base contact window is opened at the same time
when the sidewall spacer is etched (Fig. 2.12(e)). By using this process, abasic gate delay of 49.8 ps for an ECL circuit was demonstrated at a switchingcurrent of 0.65 mA [65] .
In this three mask process, the cross-link region is made before theintrinsic base implantation, and only the emitter drive-in heat step is required
after the intrinsic base formation. Therefore, the cross-link problem inducedby the double polysilicon process is eliminated. However, this process
requires different masks for the intrinsic base region and base contact window
opening. Furthermore, the somewhat higher series resistance of the emitterelectrode is a drawback, although a silicide layer is deposited on the emitter
polysilicon.
2.3.4 Sidewall Base Contact Structures
Sidewall base contact structures were intended to achieve an ideal, onedimensional transistor structure eliminating any parasitic capacitance andresistance. A sidewall base contact structure was first reported as SICOS in
1981 (67). Since that time , much process modification had been reported.
Figure 2.13 shows the fabrication steps of the original SICOS. First, a
30

(a )

{ b)

{c }

... .. .. .. .. .. ..... . . . . . . .. .. . . .... .. . . . .

(d)?0JY · ~+ - ~~N+ po Iy s·I

Refractory meta I{ e)Fig. 2. 12 Fabrication steps of the single po lys ilicon self-aligned process [66).

31mesa-etched region is formed by reactive ion etching, using a multilayered
structure , successively including an oxide, a nitride, a polysilicon, a nitride
and a CVD oxide layer (Fig. 2. l 3(a)). After a slight sideetching of the mesa,
another nitride layer is deposited and a spacer is formed at the sidewall edge.
Then, the silicon surface is oxidized and the nitride spacer is removed (Fig.
2.13(b)). Another polysilicon layer is deposited and preferentially etchedwhere the base electrode is positioned (Fig. 2.13(c)). Finally the graft base isdiffused from the second polysilicon, which is boron-doped by ion
implantation. The intrinsic base is implanted through the first oxide on themesa and emitter is also diffused through another polysilicon layer (Fig.
2.13(d)).
The advantage of the SICOS is the nearly one-dimensional device
structure in addition to its full one-mask self-alignment feature. Consequently,
excellent upward operation has been reported since the early stage of thedevelopment. However, there has been a serious drawback to this process.
This is encroachment of the extrinsic (graft) base, which occurs not only
laterally but also vertically towards the buried collector layer. The lateralencroachment is the same problem as experienced by the double polysilicon
self-aligned processes, whereas the vertical encroachment is specific to the
SICOS structure. To reduce the extrinsic base resistance, the sidewall contact
area should be kept large, and the graft base should also be satisfactory
diffused. Therefore, the graft base is deeper than the intrinsic base region andthe collector-base junction area is much larger than the original dimension on
the mask. Hence, the collector-base junction capacitance can not be decreased
while maintaining low base resistance. Moreover, the vertical encroachmentof the extrinsic base causes the reduction of the base-collector reverse
breakdown voltage.

Great efforts had been paid to remove these complications. A selfaligned edge contact technology (SELECT) was applied to the original SICOS(68], whereby a basic gate delay of 48 ps was demonstrated by an ECL circuit
at a switching current of 0.58 mA. Another approach was also reported, thetwo-step oxidation of the sidewall surface (TOSS) (69]. Figure 2.14 shows the
improved process steps, which determines the base contact width. The mesa iscovered by a nitride frame (Fig. 2.14(a)). Then, the second mesa etching is
performedbyanisotropic
32

chemicaletching.

Si02
Si3N4
Poly Si
Si3N4
Si 02

. . ............
( b)

( c)

8

c

E

( d)

Fig. 2. 13 Fabrication steps of the SI COS process [67].

33The sidewall is again cove red by nitride (Fig. 2. 14(b)). Finall y, isolation isachieved by LOCOS, followed by the nitride removal (Fig. 2. 14(c)). These
process options have been introduced to control the s idewall contact width toprevent the vertical encroachment. Nevertheless, these process modifications
result in process compl exity and a higher base resistance. This si tuati on seems
to show that practical bipolar tran sistors are basically two-dimensional threeterminal devices, which never operates in one-dimensional mode because two
opposite conductive carriers must pass orthogonally to each other. T herefore,
to optimize the device structure, two-dimens ional feature, or the eq uivalent
distributed circuit characteristics should always be taken into account.

(a)

( b)

z:i:::z:o/Base contact
Isolation Si 02(c )Fig. 2.14 Fabrication steps of the SICOS process modified by the TOSS process [69).

34The other unique self-aligned approach for obtaining a sidewall basecontact structure was demonstrated by a selective epitaxial growth technique.
Strictly speaking, it was an epitaxial polysilicon simultaneous growthtechnique [70]. Figure 2.15 shows the process steps. After an n+ buried layer
is diffused, CVD oxide is deposited and active areas are opened byconventional- lithography and etching (Fig. 2. l 5(a)). Then, an n-type epitaxial
layer and a simultaneously grown polysilicon layer are continuously
deposited. The surface of the epitaxial polysilicon-layer is covered by nitride(Fig. 2.15(b )). By using a controlled planarization technique, the nitride andthe polysilicon on the field oxide are removed followed by base-electrodeboron-ion-implantation (Fig. 2. l 5(c), (d)). Hence, the polysilicon surface islocally oxidized. The nitride at the intrinsic base region is removed and the
intrinsic base is implanted (Fig. 2.15(e)). The emitter is diffused through apolysilicon layer from an arsenic doped spun-on-glass layer (Fig. 2. l 5(f)). By
using this process, a basic gate delay of 83 ps was demonstrated by an LCML
circuit at a 1 mW /gate power dissipation. Although the elegant feature of thetechnique was realized, this structure has the same problems as those of the
SICOS. Moreover, the peripheral area of the selective epitaxial region has
numerous crystalline defects, which must be eliminated to suppress noleakage current. Finally, there also seems to be some difficulty in achieving a
one-dimensional device structure using selective epitaxial techniques.
2.3.5 Polysilicon Emitter and Emitter-Base Heterojunction
In addition to various kinds of self-aligning techniques, two notableprocess techniques have also been employed or investigated in modern siliconbipolar devices. One is polysilicon emitter, which is the basic concept for
self-aligned transistor structures, and the other is emitter-base heterojunction.
Polysilicon emitter can enhance the de gain even with shallow base-emitter
junction. Nevertheless, the mechanism of the gain enhancement is not
perfectly understood, and much discussion had been reported at conferences
or in scientific papers. Although to describe all of these is beyond the scopeof this dissertation, the important point is that, by using polysilicon emitter,the current gain is no longer considered to be the limiting figure of merit forsilicon bipolar transistors with shallow base-emitter junctions.
35

{a}

....
. . .·. .·.... ..
. ·...· .~
·'~

Cb)

~w EpiA·.·.·.·.·.~
4·.·.·.· : .· +- Si3N4
r'·· .. . -!~.·.. .. · ~p I s·%t',0'.l

oy

i

{c )

... · p+ ... ·~

( d)

~·

.... ·'Q'. · ....

'llf4~~'i>Zii

( e)

B

c

E

~Poly Si(f }Fig. 2.15 Fabrication steps of the self-aligned se lective poly-epi growth process (7 0) .

36

Silicon-based heterojunction BJTs (HBTs), or the widegap emitter
and/or narrow gap base have also been proposed to enhance the polysiliconemitter effect. Silicon-germanium for the narrow gap base is now becoming
the most promising candidate, and a sophisticate process technology
combining selective ultra high vacuums (UHV) CVD epitaxial base withdouble-polysilicon self-aligned structure has also been proposed [71, 72).
2.3.6 Conclusion
The double polysilicon self-aligned structure is also another must for
high-speed silicon bipolar LSis. By employing this structure, BJTs had
achieved

high-speed

performancemorecompetitivethan

compoundsemiconductor devices without using tight lithographic design rules. BJTs
also utilized full advantage of polysilicon material properties, that haverecently been merged to silicon-based heterojunction BJTs.
2.4 Physics-Based Bipolar Transistor Design

2.4.1 Introduction
In order to extract ultimate high-speed performance of silicon BJTs,

well-balanced optima of device parameters such as cutoff frequency, baseresistance and base-collector capacitance have major concerns. For example,
by combining double polysilicon self-aligned processes, a pedestal-collectortransistor has revived to improve cutoff frequency using a selective-ionimplantation technique [32, 73-77). The transition was able to achievesatisfactorily high cutoff frequency without so much increase of baseresistance and base-collector capacitance because a pedestal collector is selfaligned to an intrinsic base region.
However, when a highly-doped collector is used to prevent base pushout (Kirk) effect, avalanche generation due to a stronger electric field at abase-collector junction makes collector-to-emitter breakdown voltage lower[78]. This low breakdown voltage seriously limits circuit design capability.
Therefore, an optimal process for pedestal-collector transistors shouldcarefully be maintained to realize not only well-balanced device parameters37but also high enough collector-to-emitter breakdown voltage.
In this section, will be described the favorable process conditions fordouble polysilicon self-aligned pedestal-collector transistors to match therequirements mentioned above by using a newly developed two-dimensional
process/device simulation system. The simulation system will be described insubsection 2.4.2, and the simulated results will be explained in subsection
2.4.3 . The process conditions for favorable highly-doped pedestal collectors
will be discussed in subsection 2.4.4. In addition to the simulation analyses,
will also be shown some experimental circuit performance improvements
demonstrated by ECL ring-oscillators and a 1/8 static frequency divider insubsection 2.4.5. Finally, the conclusion will be given in subsection 2.4.6.
2.4.2 Two-Dimensional Process/Device Simulation System
In the case of double polysilicon self-aligned processes, phosphorus orarsenic ions are selectively implanted just beneath an intrinsic base region toform a pedestal collector using a polysilicon base electrode covered withoxide as a mask (32] . The implanted ions are dispersed laterally along a basecollector junction, and the distributed impurity profile strongly affects not
only device parameters but also collector-to-emitter breakdown voltage.
Therefore, two -dimensional process simulation is inevitable to analyzetransistor characteristics precisely. For this purpose, we have developed a
new two-dimensional process simulator named FIPS2 based on a finite
difference method. FIPS2 is an enhanced version of a one-dimensional
process simulator named FIPS (79]. FIPS2 includes an epitaxial autodoping
model which solves a mass-balance equation on a substrate surface. It also
includes an empirical fitting model for channeling effects of shallow ion
implantation. In addition to the channeling model, parameters for Pearson
distribution functions obtained by Monte Carlo simulation are considered in
FIPS2 to calculate the pedestal collector profiles accurately. By using thesemodels, typical advanced bipolar processes are effectively analyzed.
The calculated two-dimensional doping profiles are transferred to a twodimensional device simulator named B/P2DAN. BIP2DAN is a driftdiffusion-model-based two-carrier device simulator which can calculate not
only de and ac characteristics but also transient characteristics with some38

lumped external circuit elements [79-81]. It also includes typical physicalmodels such as Shockley-Read-Hall, Auger recombination models , bandgap
narrowing effects, impurity concentration, electric field and temperaturedependent mobility models, impurity concentration dependent carrier li fetimes, and an avalanche generation model based on the Chynoweth law.
These process simulator and device simulator are combined directly. We
can accordingly analyze the relationship between process cond iti ons anddevice characteristics including collector-to-emitter breakdown voltages. We
have employed de and ac analyzing functions for this time to estimate theeffects of pedestal-collector-ion-implanting conditions to device parameters
and breakdown voltages.
2.4.3 Simulation of Pedestal-Collector Transistors
In this subsection, the simulation procedure is described including

device structures and process conditions.
2.4.3. l Process Simulation
We have assumed a typical double polysilicon self-aligned transistor
having a low-energy-boron-implanted base (less than l 0 Ke V) with a thinscreen oxide layer. It also has an n-type epitaxial layer of a typical thickness
on a heavily doped buried layer. We have chosen three acceleration energies
for phosphorus ion implantation to fo rm pedestal co llectors. Emitters havebeen assumed to be diffused from arsenic-implanted polysilicon. Figure 2.16
shows the one-dimensional doping profiles at the center of the emitter. The
ion-implanting conditions are also shown in Fig. 2.16. No implantation case is
the control sample for comparison, described as "Reference" in the figures.
Figure 2. 17 illustrates the two-dimensional impurity distributions
exhibited by concentration equi-contour lines. The peak positions and lateral
spreading of the pedestal collectors are clearly shown depending on theimplanting conditions.

39

J

..(.)(.)

Reference
1 SOkeV 2E12cm·2300keV 1E13cm·2400keV 1E13cm·2::::::;.. 1 020c:

Xje(A)

Xjb(A)

632
633
632
632

2097
1372
1581
1786

0

-ro 1018
.....
~

c:
Q.)
(.) 1016

c:

0
(.)

Referen ce

0

0.2

0.4

0.6

0.8

1.0

1.2

Depth (µm)
Fig. 2.16 One-dimensional doping profiles of analyzed transistors at the center of
emitter.

Si

Poly-Si,. ... ...... ·]I nEJN

I 0.Sµm

Reference

1 SOkeV

300keV

400keV

1 016

101 6

1 017

017

101 8

101 8

101 8

1018

1019

101 9

1019

101 9

(/ cc )
Fig. 2.17 Two-dimensional doping d istribut ions with concentration equi-contour lines.

40

2.4.3.2 Device Simulation
The impurity concentration tables obtained in Fig. 2.17 are transferred tothe device simulator. In the device simulator, only a single crystalline region
is remeshed and impurity concentration values are interpolated for the
Poisson and current-continuity equations.

Figure 2.18 illustrates theschematic cross-section of an analyzed transistor. The polysilicon emitter isassumed to be a 0.1-

µ m-thick extended

single crystalline emitter with amaximum activated impurity concentration of 1x1020 /cm 3 • The device lengthis set to be 1.0 µ m for convenient comparison to one another. The emitterarea is 0.2xl.O µ m2 and the base area is l.2xl.O µ m2 .
1.2

I·

0.2

·I

H
T""

E

l_

ci
~
,...

(µm)

c
Fig. 2.18 Schematic cross section of an analyzed transistor. The device length is 1.0 µm.

Figure 2.19 displays the cutoff frequency versus collector current
characteristics for each implantation case. The cutoff frequency is improvedby 80% in the maximum case by suppressing the Kirk effect. Ac baseresistances and base-collector capacitances are also shown in Fig. 2.20 asfunctions of collector current. The ac base resistances have been calculated by
the same way as the input impedance circle method that is usually used insmall signal measurements. The base resistance of the implantation energy of
150-Ke V case is increased, and the base-collector capacitances of allpedestal-collector cases are increased as well. Current gain dependence uponcollector current is shown in Fig. 2.21 .
41

300keV30-:c400keV "N

150keV-_

20(!)

Reference -.

....t10O'--~........===~-'--~~....L.~~_J_~~L_~__J

1 o-a 10-7

1 Q-6

1 o-s

1 Q-4

1 Q-3

10-2

le (A)
Fig. 2.19 Cutoff frequency ifr) versus collector current U c) characteristics.

3.0

1000
Vsc=OV

-....
u.

800
600

-a

400

..a
..a
)..

2.0

.._.

al
(.)

u

1.0

O Reference

D 300keV

6. 150keV

e 400keV

.._.

200
0
10-7

1 Q-6

1 o-s

1 Q-4

0

1 o -3le (A)
Fig. 2.20 AC base resistance (rw) and base-collector capacitance (Ccb) versus collector
current U c) characteristics.

42150keV

Vsc=OV

200

w
u.

..c

1 oo

Reference

O L-~-1-~-L~--L--~_._~-L==---'

10-8 1 o-7 1 o-6 1 o-s 1 o-4 1 o-3 10-2

le (A)
Fig. 2.21 Current gain (hFE) versus collector current U c) characteristic.

18 :0A
150keV

Reference

1 o-s....-...

<x:'-"1 0-6(..)--. IC=0.56µ A , -

10-7
10-8

~---_.__

1.0______.__

2.0

3.0

5.0

6.0

VcE (V)
Fig. 2.22 Collector-to-emitter current (I, ) versus co llector-to-emitter vo ltage (VCE)
where the base currents terminate.

43-

The collector-to-emitter breakdown voltage (BV,w) has been calculated
as follows. At first, the base-emitter forward voltage is supplied to a fixedvalue, and then the collector-to-emitter supply voltage is increased to find thebias point where the base current terminates. This means that the forward basecurrent is equal to the avalanche-generated reverse base current. Next, thebase-emitter forward voltage is increased slightly, and the collector-to-emitter
supply voltage is again swept in the same manner. After several iterative
calculations with different base-emitter forward voltages, we can find thecollector-to-emitter breakdown voltage with the base terminal open as afunction of collector-to-emitter current. Fig. 2.22 displays such relations forthe four cases. The BVCEo

is defined at the collector-to-emitter current of

0.56 µA which corresponds to 1 µA when an effective emitter area is 0.2x 1.8µm2.

Table 2 summarizes the calculated results of cutoff frequencies <fr), acbase resistance (rw ), base-collector capacitance (Ccb) and BVcw·
Table 2.2 Calculated device parameters and BVCEo

Pedestal l. I.

fr (GHz)@VCE= l V

r w ( Q)c,.b (fF)

BVcEO (V)

none

16.2

609.7

0.31

5.7

150KeV

22.0

707.9

0.58

2.2

300KeV

28.6

614.7

0.65

1.8

400KeV

24.0

600.5

0.52

2.7

2.4.4 Favorable Process Condition for Pedestal Collector

Generally speaking, there are two choices for the ion-implanting
condition to realize a highly-doped pedestal collector. One is a counter doping
technique to cut the base tail caused by channeling effect. The other is arather deeper doping technique to obtain a gradient collector so as to prevent
mainly the Kirk effect. According to the cases analyzed for this time, the150-KeV case is the former, and the 400-KeV case is the latter. In the case of
the counter doping technique, the base width is much more reduced to cause
the base Gummel number (effective hole numbers in the base per unit area)44

decrease than other cases. Therefore, not only the base resistance increases,
but also the current gain increases drastically as shown in Fig. 2.21. Thismeans there is less process latitude for B Vcw· On the contrary, in the case of
the gradient co llector doping, the base widths are not so much reduced.
Consequently, the current gain and the base resistance are not excessively
increased compared with the control device. This is a prom ising condition tokeep enough process latitude against the reduction of BVCEo·
Fig. 2.23 demonstrates the relationship between cutoff frequency and
BVCEo when the phosphorus-ion-implanting conditions for the collector arechanged. If the dosage is decreased, the B VCEo is increased while the cutoff
frequency is decreased. We can eas ily find that the 150-KeV case is moresensitive to the reduction of BVCEo fo r higher cutoff frequency. If theminimum BVCEo of 3 Vis required, the 400-KeV case is the best one with thehighest cutoff frequency and moderately low ac base resistance as well as
small base-collector capacitance.

35
300keV30....-...
N

:c

25

(.!)

. .._

20
.....
.....
0

~

15

Reference
10

0

1

2

3

4

5

6

7

8

BVcEO (V)Fig. 2.23 Relationship between BVao and fr for different phosphorus-ion-implanting
conditions. Dose conditions; 150KeV with 2 x 10 12/cm2, 1X10 12/cm 2 ; 300KeV with 1 X
10 13 /cm2, 2X 10 12 /cm 2 ; 400KeV with 1x10 13/cm 2 , 2X 10 12 /cm2 •45

2.4.S Application to ECL Circuits
By employing the optimizing method described above , we have tuned
experimentally our 0.5- µ m-minimum-design-ruled double polysilicon selfaligned process called ESPER [40] by using ECL circuits including ringoscillators and 1/ 8 static frequency dividers. As a result, we have obtained an
ECL gate delay time of 30.3 ps/gate at a switching current of 0.52 mA for
low-power gates with effective 0.2xl.8- µ m 2-area emitters. In the case ofhigh-power gates, which correspond to effective 0.2x4. 7- µ m2 -area emitters, agate delay time of 27.2 ps/gate at a switching current of 0.97 mA, and aminimum gate delay time of 26.3 ps/gate at a switching current of 1.64 mA
have been obtained. At the same time, a 1/8 static frequency divider using TF /F has been observed to operate up to a maximum frequency of 15.8 GHz[82], that was the highest value in 1990.
2.4.6 Conclusion
By using a two-dimensional process/device simulation system, process
conditions of highly-doped pedestal-collector transistors for well-balanced
device parameters and high enough BVCEo have been analyzed. As a result, a
gradient-collector-like profile has been proved to be superior to a counter
doping profile to cut a base channeling tail from the viewpoint of high enoughcutoff frequency , lower base resistance and smaller base-collector capacitancewith the minimum BVCEo of 3 V. By applying this optimization method topractical ECL circuits, a minimum ECL gate delay time of 26.3 ps/gate at aswitching current of 1.64 mA has been obtained experimentally. At the sametime, a 1/8 static frequency divider has been observed to operate up to 15.8

GHz.

46

Chapter 3
DevicePerformance Estimation of High-Speed Bipolar

3.1 Introduction

Numerous modern silicon BJT technologies have been investigated anddiscussed in the previous chapter. In this chapter, the performance estimationof silicon BJTs, not only from the process point of view, but al so from thecircuit designing point of view will be discussed, and will be clarified the
problems of high-speed bipolar devices for larger scale integration circuit.
There have been extensive circuit options for silicon bipolar !Cs such as
S-TTL, IIL, CML, ECL etc. However, the advent of BiCMOS technology,
which was aimed at achieving higher speed operation than CMOS and lesspower dissipation than TTL or ECL, displaced the S-TTL bipolar digital ICs
from its major position in the bipolar digital IC market. While the market
share of S-TTL or UL digital ICs decreased because of their poor costperformance figure of merit, only ECL devices seemed to pile up an
increasing market share. Until the end of the 1980s, the demand for siliconbipolar digital ICs focused on higher speed devices with higher level ofintegration or less cost than GaAs ICs. These high performance features wereachieved by ECL and ECL-like circuits.
3.2 Strategy to Estimate ECL-Circuit Performance

The advantages of ECL and ECL-like circuits are the high-speed nonsaturating operation of current switches and the high driving capability ofemitter follower stages. However, their large power dissipation is a mostserious disadvantage. The switching delay time (tpd) of ECL circuits depends
on the power dissipation or the switching current per gate as showing Fig. 3 .1.
The delay tpd is roughly expressed by the following equations:t pd = R L Cc + k 1 r 1 + r bCb(3. I)

Cc = k 2C1 c + k3 Ccs + k 4CL + k 5 CEF(3.2)

Cb = k6Cdc + k 7C1e + ksCJc

where

(3.3)
RL is the pull-up resistor, -r r is the transit time , rb is the baseresistance,

Cjc is the base-collector capacitance, Ccs is the collector-

47

substrate capacitance, Cl is the parasitic wiring capacitance, CEF is the input
capacitance associated with the emitter follower transistor, Cde is the diffusion
capacitance, C1e is the base-emitter capacitance andk 1 to k 8 are weighting

constants. Generall y, as shown in Fig. 3. 1, at lower power dissipation, thefirst term of eq. (3 .1) is the most dominant factor limiting the delay, and at
higher power dissipation, the third term plays a more important role thanothers. The minimum achievable delay time is restricted by the second term ofeq. (3 .1 ). Larger scale integration requires lower power dissipation per gate tokeep total power consumption per chip at a practical level. Therefore, lowswitching current per gate is accordingly needed, and a large pull-up resistor
is required if the voltage swing is fixed at a constant value to keep enoughnoise margins. Consequently, the first term, or the RC time constantassociated with the pull-up resistor, should be decreased to achieve higher
speed operation. For medium and small scale integrated circuits, the first term
as well as the other two terms should also be reduced to obtain shorter delay
times.

Q)

E
+-

RL Cc
fb Cb

~

0

{/
y

Q)

"O
Q)
+-

0
(.!)

Switching current
Fig. 3 .1 Gate delay time versus switch ing current per gate (arbitrary unit).

48

L

0.25 µm

L

L

L

B

L

B
/

I

p

I

I
---~

N

c
SE; 0.25 x I µm2 )( Se; I .25 x I µm2
Fig. 3 .2 Schematic cross-section of the analyzed transistor.

The most important matter when optimizing the transistor structure for
ultimate high speed operation is to evaluate quantitatively the contribution of
the RC time constants appearing in eq. (3 .1 ). Nevertheless, because of thenature of RC time constants, eq. (3. I) is not accurate when they are closely49related to one another. Additionally, not only the base resistance, but also the
diffusion capacitance and the base-collector capacitance are non-linearly
dependent on the switching current. Therefore, the most reliable way toestimate the switching delay time is direct numerical calculation by physicalsimulation of circuit performance without using an analytical circuit model.
Now, will be described some results obtained with such a numerical techniqueto estimate the ultimate performance of silicon bipolar ECL circuits. Figure 3.
2 shows the schematic cross-section of the simulated transistors. Because
two-dimensional device simulator has been used, a 0.25 X 1.0- µ m 2 walledemittertransistor,

suitablefortwo-dimensional

analyses,

has

been

investigated. Figure 3 .3 shows the impurity profiles corresponding to thecross-section in Fig. 3.2. The impurity profiles were obtained by a processsimulator. The polysilicon emitter is treated as a 0.1- µ m-thick extendedsingle-crystalline emitter, where the maximum ionized impurity concentration
is limited by 1 X 10 20cm ·3 • Figure 3 .3(a) displays nearly the same profile as
has been obtained experimentally by the selectively-implanted-pedestalco llector process described in the previous chapter. The calculated peak
cutoff frequency is 24 GHz at a collector current of 0 .18 mA as shown in Fig.
3.4 and the C jc is 0.53 fF while the ac base resistance is 400 Q at low
collector current. Figure 3.3(b) indicates rather shallower base with a gradientcollector profile. The calculated peak cutoff frequency is 56 GHz at acollector current of 0.32 mA as shown in Fig. 3 .5 , while the C jc is 1. 1 fF andthe ac base resistance is 570 Q at low collector current. Figure 3.6 indicates• the circuit diagram used to estimate the delay time. In Fig. 3.6, the terminal
current-voltage characteristics of transistors Q 1 and Q2 are directly obtained asa result of physical two-dimensional device simulation using a transient
analysis mode.

Other circuit parameters, such as RL, C and R 8 are introduced

as lumped values. The pull-up resistor RL is defined to fix the switchingcurrent. C contains all of the parasitic capacitance associated with the pull-up
resistor such as the collector-substrate capacitance, the wiring-substratecapacitance, the res istor-substrate capacitance and the junction capacitance
related to the emitter follower transistor.

Finally, the R8 is base-contact

resistance. The voltage swing is set to be 0.4V and the average delay time of
NOR and OR logic gate outputs is defined as the gate delay.

50Extended emitterI' [Ext.

IE20

(a)

base

I '

N+ 1

\

\p+

u
u

I
I

..........

I
I

•p

c

-0
0

"-

c:
Q)

u

c:

0

u

IE 15

{ X je = 76 nm

x jb = 190 nm
0
Depth

0.5
( µm)

Extended emitter

f

IE20
N+

( b)

Ext. base

\

\

\p+

u
u

\
I
I
\
\
I
I

..........

c:

-0
0

"-

N... ......

,

/

c:
Q)

LIn:. base

u

c:
0

u

IE 15

{ Xje = 31 nm

x jb = 106 nm
0
Depth

0.5
( µm)

Fig. 3 .3 Impurity profiles for the analyzed transistor.
(a) Selectively implanted pedestal collector profile. (b) Gradient collector profile.

51

b

A

(0 VcE = 3 V

N

I

- 50
(.9

100

>.

c:

()

c: .

0

Cl

Q)

::J
O"

--

cQ):

Q)

"'-

"'"'::J

u

0
: :J

u

Collector current{A)

Fig. 3.4 Cutoff frequency and current gain versus collector current (pedestal collector).

(d VcE = 3V

N

I

- 50

100

(.9

c:

>.

0
Cl

()

-

c:
Q)

::J
O"

c:

--

Q)

Q)

"'"'-

"'-

:::J

u

0

::J

u

OL-~~~~L-~~~-L-~L--~~~....____.._______.o

IE-5

IE-4

IE-3

Collector current (A)Fig. 3.5 Cutoff freq uency and current gain versus co llector current (grad ient collector).

52

c

c

VREF
(-l.2V)

Q1

VIN-1.0V~

-l.4V

H
20ps

• Transistor Q 1 , 02 ~2-D physical device simulation• RL, Re, C ~Lumped circuit parameters

RL ~ Pul I-up resistor
Re~ Base contact resistanceC ~ Al I parasitic capacitances
associated with RL(Sum of Ccs, CL, CEF etc.>
Fig. 3.6 Analyzed circuit diagram .

53

3.3 Optim ization of ECL-Circuit Performance

Figures 3.7 and 3.8 show the numerically calculated results according to
the two impurity-profile cases. In Fig. 3. 7, the basic gate delay timedependence on the switching current is displayed when the total parasitic
capacitance C and the lumped base contact resistance Re are changed asparameters. The modern microfabrication technique can make the total
parasitic capacitance c as small as 15 fF , with c cs=3fF , CEF=4fF and CL =8fF.
Because the base contact resistance is estimated at nearly 50 Q µ m2 , theresult, in the case of C= l 5fF and Re = 100 Q, can be recognized to indicate therealistic performance limitation; that is sub-40 ps/gate at lower power
dissipation and 20"-'25 ps/gate at higher power dissipation. The noticeable
fact revealed in Fig. 3. 7 is that the gate delay is strongly dependent on theparasitic capacitance C.
These results cannot only be derived from eq. (3.1 ). The base contact
resistance Re contributes to decreasing the delay time at higher current level,
as shown in Fig. 3.1. If the parasitic capacitance C is reduced to zero, even
sub-I 0 ps delay time can be obtained by the 24-GHz-peak-cutoff-frequency
transistors. Of course, this situation can not be realized in practical devices
because the emitter follower transistors are always coupled to the current
switches. However, this result proves that if C is reduced from 15 fF to 5 fF,
the delay time is remarkably improved by about a factor of two. Figure 3.8
shows similar results by the transistors with the shallower base, and with amuch higher peak cutoff frequency than that in Fig. 3. 7. The gate delay versus
switching current characteristics are shown for various C values. When
compared with Fig. 3. 7 at the same C value, (e.g. 5 fF) , there is not so muchdifference in delay times. Onl y at higher current levels, can the high-cutoff-

frequency transistor improve the delay, but the delay-time improvement is afew picosecond, although the cutoff frequency is improved more than twice.
On the contrary, at the lower current level, the high-cutoff-frequency

transistor shows greater delay, which may be a trade-off caused by the larger
Cw As shown in Figs. 3. 7 and 3. 8, the most crucial parameter affecting thegate delay time is the total parasitic capacitance associated with the pull-up
resistor. Surprisingly, the contribution of the peak cutoff frequency value ofthe switching transistors is not very large, even at the higher current levels.
54

-

100

a.

-

Q)

E

~

0

Q)

c

Ra

(fFJ [Q J(15, 100)(10 , 100)

(/)

10

( 5' 100)( 5' 0)( 0' 0)

~

=

"'O
Q)

0

(!)

IE-4

IE-3

Switching current (A)Fig. 3. 7 Gate delay time versus switching current per gate (pedestal collector) .

( /)

a.

C Rs
[fFJ [QJ

Q)(10, 0)"'"

E

0)~~
0)~

~

0

Q)

-0

-

10

' ... ...... ..... ....... ___ _-- --

Q)

0

C)

~ Pedestal

IE-4

IE-3

Switching current (A)Fig. 3.8 Gate delay time versus switching current per gate (gradient coll ector).

55b3.4 Favorable Silicon BJT Features and Its Limitation

As discussed in section 3.3, the most crucial parameter affecting the gate
delay of ECL circuits is the parasitic loading capacitance associated with thepull-up resistor. A high cutoff frequency requires shallower base and higher
collector impurity concentration, which cause higher intrinsic base resistanceand larger base-collector capacitance.

Hence,

the device parameters

corresponding to the active transistor region (e.g. the base-collector
capacitance, base resistance and cutoff frequency) should be moderately
optimized as shown in the last section of the previous chapter. Moreover,other parasitics such as contact resistance for the emitter or the base should
also be kept small enough not to affect the gate delay. The current gain is nolonger a figure of merit limiting circuit performance, even if an extendedsingle-crystalline emitter is used as shown in Figs. 3.4 and 3.5. The singlecrystalline or epitaxial emitter is also advantageous to reduce the emitter
series resistance, which often originates in the polysilicon emitter structure.
The high emitter series resistance should be avoided to maintain sufficienttransconductance for proper circuit operation.
By taking account of the properties discussed, the favorable silicon BJT
structure can be shown in Fig. 3.9 [81 ,83]. To reduce the parasitic capacitancesimultaneously associated with the pull-up resistor and the substrate, thetransistor should be fully iso lated by trenches and an SOI structure. Active
transistor regions are surrounded by thick insulators, and field regions arealso covered by thick insulators such as oxide. To reduce the parasitic
resistance associated with emitter and base, the contact area is covered bysilicides or low-resistance refractory metals. The emitter should also be
single-crystalline extended emitter or epitaxial emitter. The vertical profile
for the intrinsic base regions are optimized to achieve a reasonable trade-off
between the cutoff frequency, the base-collector capacitance, and the baseresistance, avoiding punchthrough and forward-biased tunneling with enoughcollector-to-emitter breakdown voltage. At the same time, the lateraldimension is optimized to avoid narrow emitter effect, peripheral forward- orreverse-biased tunneling. Because the circuit delay is no longer limited by theperformance of transistor, but rather by external parasitics, the practicality ofprocess improvements is an important matter. SOI is also applicable to bipolar
56

LSls now that a direct wafer bonding and thinning technique are available[84). Therefore, the transistor shown in Fig. 3.9 is based on the improvementof double-polysilicon self-aligned transisto rs. These features are now
demonstrated by several researchers including the fully isolated SOI structure,especially for mainframe-processor CPU LSis [85], and optical terminal ICs[86]. Other· options, such as si licon-based heterojunction BJT's (HBT's),
including wide gap emitter and narrow gap base, have been investigated.
Recently, practical process to achieve narrow gap base by selective-epitaxial
growth of a silicon-germanium strained- layer in the SST-like structure has
successfully been found as mentioned in the previous section. However, wemust keep in mind that Si-HBT itself cannot reduce the parasitic capacitanceassociated with the pull -up resistor.

c

E

B

silicide or
refractory meta I

dielectric

Fig. 3.9 Schematic cross-section of the favorable BJT structure.

57

LIn addition to process improvements, circuit techniques must also beenhanced. One example of such an approach is the so-called active pull-down
for emitter follower circuits (87] . A basic gate delay of 23 ps at a power
dissipation of only 2.1 mW/gate has been demonstrated based on a trench
isolated, double polysilicon, self-aligned transistor process. The basic gate
delay of ECL circuits is now less than 20 ps. Such a basic delay is not very
important, and the total delay of circuits with loaded capacitance or thesystem delay is much more relevant. To achieve higher speed operation ofchips that should be considered as a system, the important thing is the wellbalanced optimization of process technology, device structure and circuitdesigns.
So far as ECL and ECL-like circuits are concerned, the improvement of
the process technology as well as active pull-down emitter follower
techniques can not reduce the switching current itself. Even when the loaded
capacitance is reduced due to the smaller feature size brought by sophisticatedlithography tools, minimum switching current of around 100 µ A is at least
required as shown in Figs. 3.7 and 3.8. Therefore, if the chip contains morethan one-million gates, it dissipates 1OOA in total current, which is far beyond
the limit of practical air-cooling.
Non-saturating operation of BJT with continuous current flow is theadvantage of ECL circuit because this can avoid the large time constantcaused by saturation-mode operation. Ironically, this advantage directlyreflects the major drawback to ECL circuits, or the large power dissipation.
Today's microfabrication technology has brought us deep submicron era, anda full system-on-a-chip concept is theoretically achievable. However, for
high-speed bipolar LSis based on ECL circuits, this transition could no longer
afford any benefit.

3.5 Conclusion
To extract the high-speed performance of bipolar LSis, ECL and ECLlike circuits are the most suitable compared to other circuit architectures. As
far as the integration level is not very large, thi s advantage covered the
problems of higher power dissipation. However, when millions of gates on achip can be available due to the dramatic improvement of microfabrication

58

I

J

technology, the large power dissipation is no longer escaped. The high-speed
bipolar LSis have not been able to catch up the system-on-a-chip concept.

59

Chapter 4

Design Concept for High-Speed CMOS Device

4.1 Introduction

Historically, the concept of the field effect transistor was much older
than that of BJT. Basic patent was already issued in the 1930s. However, arealistic device never came to industry until the beginning of the 1970s. The
understanding of the physical mechanism of the surface states of silicon madepossible MOSFET for 1kb dynamic (D)RAM, which was developed by Intel.
Because of a contamination problem caused by mobile ions such as Na or K,
the first MOSFET was based on a p-type channel structure. Great efforts were
paid to conquer this problem, and by the end of the 1970s, n-type channel
MOSFETs were available for practical devices such as DRAMs. The n-typechannel can benefit high mobility of electron when compared to that of holein the p-type channel, and the device performance was improved inaccordance with the progress of optical lithography so that nMOS LSis
rapidly replaced pMOS LSis.
As MOSFETs are surface device, they do not require full isolation
between neighboring devices, and this situation is advantageous from thepacking-density point of view. In the 1980s, silicon bipolar, nMOS andCMOS LSis were in a quite competitive status for realization of very large
scale integration (VLSI). Among them CMOS device was also ideal from thepower-dissipation stand point, because it dissipates power only whenswitching. However, CMOS gate must use both nMOSFET and pMOSFET tomake even a basic inverter gate, that was thought to be a disadvantage
concerning packing density against nMOS-only devices. In the 1980s,
developments of MOS LS Is were focused on larger integration in accordancewith the progress of microfabrication technology. The nMOS LSis realized
higher packing density and larger integration level than bipolar LSis, but theyalso began to suffer from the problem of larger power dissipation. Therefore,by the end of 1980s, CMOS devices took over the nMOS position andachieved the major position of VLSI. At that time, submicron gate length wasrealized for MOSFETs in CMOS VLSis.
At the beginning of the 1990s, the transition occurred even in the area ofhigh-speed LSis. High-speed CMOS LSis appeared in a quite competitive

60

situation against bipolar LSis. One was a 90 MHz CMOS-RISC processor [88],and the other was a CMOS standard cell LSI [89]. The former realized thesame clock frequency as that of the ECL-based RISC processor at thatmoment, and the latter achieved circuit delay, even with a heavy loaded
capacitance, which was almost the same as that of the sophisticated ECL gatearray (57]. These high-speed features were mainly achieved by combining
submicron lithography and channel length optimization in their process
technologies. CMOS LSis began to benefit the fruit of microfabrication
technology progress not only in larger integration but also in higher speed
operation. At the same time, even in the field of mainframe computer, theadvantage of CMOS device against bipolar ECL devices was suggested for thecentral processing unit (CPU) LSis (90]. Now, the CMOS device has taken the
major place in almost any field of ultra large scale integrations (ULSls).
4.2 Requirements for High-Speed CMOS Device

As CMOS replaces ECL devices in the high-speed area, more than onemillion gate circuits for microprocessor with 500MHz clock cycle have beenrealized in the mid 1990s. Although CMOS devices dissipate minimum power,such a large scale and high-speed LSI consumes ac current of tens ampere .
. Hence, power dissipation problems are now becoming serious even in the caseof CMOS devices. Moreover, loaded gate delay, especially wiring delay, isalso becoming main concern just like the situation that once bipolar devices
faced in the end of the 1980s.
To achieve lower power dissipation for CMOS circuits, the mosteffective way is to reduce supply voltage because the power is in proportion
to the square of the voltage swing. For this purpose, the threshold voltages ofboth nMOSFET and pMOSFET should also be decreased. At the same time,these absolute values of threshold voltages should be the same from thecircuit-design point of view. This means the technological freedom of thethreshold voltage design especially for lower values is important. Besides, tosave the power dissipation, any parasitic capacitance associated with the drainjunction as well as source and gate series resistances should be reduced. For
such purposes key features for high-speed CMOS ULSis are summarized as
below:61a) Surface channel dual-gate n/pMOSFETs,b) Retrograde well structure,c) Salicide (se lf-aligned silicide) for source/drain/gate,d) Shallow trench isolation.
By using the surface channel MOSFET as well as the retrograde well structure,
the threshold voltage can be reduced easily and independently designed fromthe well structure sustaining lower well resistance to prevent a latch-up
problem. In the case of the retrograde well, the doping concentration
increases in the depth direction and a highly doped buried-layer-like profile iseasily obtained.

The surface channel pMOSFET can achieve lower

threshold voltage with a less short channel effect. To this end, the dual-gateprocess, or the process using n-type polysilicon gate for nMOSFETs and ptype polysilicon gate for pMOSFETs is favorable. The salicide process basedon CoSi 2 , which uses cobalt-and-silicon sintering process after sidewall
spacer formation without any mask step, can reduce the parasitic resistancenot only on the source/drain contact regions but also gate electrode even in
the sub-0.1 µ m regime. TiSi2 has been used for salicide process, but it suffers
higher resistance when the width of the silicide region approaches subquartermicron because the TiSi 2 crystalline phase transition from the higher
resistance C49 to the lower C54 becomes unstable and cannot be controlled
well. The shallow trench isolation not only can achieve higher packing
density than that of LOCOS but also can reduce parasitic junction capacitanceoriginated by the lateral diffusion of highly doped source/drain toward theisolation region. Moreover, it can realize better planarized surface topography
than that of LOCOS, which is favorable to keep enough depth-of-focus (DOF)
margin for optical lithography process. Figure 4.1 shows the typical crosssectional structure of a dual-gate CMOS device with CoSi 2 formed by thesalicide process. Inter-layer dielectric and W-filled contact plug as well as
local interconnect wiring are shown in the same figure.

62

ma
C2LZl
-

Local interconnect
W-plugC0-silicide

nMOSFET

pMOSFET'i

Inter-layer
dielectric

Shallow
trenchisolation
p-retrograde welln-retrograde wellp-substrate

Fig. 4.1 Cross-sectional structure of dual-gate CMOS device with CoSi 2 after contact
plug formation.

4.3 Quarter and Subquarter Micron CMOS Technologies
In this section, the quarter and subquarter micron CMOS device
technologies for high performance logic ULSis are described.
4.3.1 Quarter Micron CMOS Technology
Retrograde twin-well and dual-gate surface channel CMOS device wasdemonstrated based on Co-salicide process [91]. In this case LOCOS isolation
was still used. KrF excimer lithography tool (optical wavelength:248nm) wasused to realize minimum gate length of 0.24 µ m. Because the minimum
pattern feature is almost the same as the wavelength, the DOF can be kept
enough to allow rather uneven surface topography caused by LOCOS isolation.
In this technology, also employed local interconnect using thin TiN layer
directly deposited on the Co-silicide and field oxide layer. By using this local
interconnect technique for cross-coupling of embedded SRAM cell, 9.9- µ m 2
cell area has been realized [91 ]. This SRAM has achieved less than 2ns access
63

time [92]. The quarter micron CMOS technology has realized ECLcompatible high-speed and higher-density ULSis.
4.3.2 Subquarter Micron CMOS Technology
Based-on the quarter micron CMOS technology, it has been up-graded tothe minimum design rule of 0.2 µ m [93]. As the same KrF optical lithography
tool was employed, to keep enough DOF margin, shallow trench isolation
technique has been introduced. Other process technologies are basically thesame as those of the quarter micron technology. As an option, the first metallike local interconnect technique was also introduced instead of direct
deposited TiN layer on the silicide region as shown in Fig. 4.1. This is also
intended to keep enough DOF for the local-interconnect mask patterning
using the subquarter micron design rule. As a result the embedded SRAM
with the cell size around 4 µ m 2 has been realized with the access time of
1.4ns [93].

4.4 Conclusion
CMOS device has replaced bipolar devices even in the field of highspeed LSis. Although CMOS device is ideal from the power-dissipation pointof view, it has begun to suffer from larger power dissipation and wiring delay
problems brought by ULSI, which were once suffered by bipolar LSis.

64

Chapter 5

Inverse Modeling Technique for MOSFET Design

5.1 Introduction
In order to limit the development costs involved in deep submicron
CMOS technology, simulation techniques are used to reduce the number oftest wafer cycles. Unfortunately, deep submicron CMOS technology is toocomplex to be accurately modeled using the available process simulators.
Quantitative simulation of the reverse short-channel effect, for example, isstilldifficult.

Furthermore,

process

simulators

containmany

fitting

parameters, which further limit the predictive capabilities of these programs.
On the other hand, device simulation has recently attained a high level ofreliability, and it presents a detailed picture of the carrier transport processes
within a device which cannot be obtained by experimental means. Optimum
utilization of device simulation must be based on an accurate device structureand doping profile. Since process simulation cannot always provide this,inverse modeling is used to complement process simulation [94-98]. In thiscase, physically precise device models are used to extract the device structure
as well as the active impurity profiles from measurements on a specific device.
In MOSFETs, capacitance versus voltage (C-V) characteristics and draincurrent versus gate voltage (Id-Vg) characteristics in the so-called linear
device operation regime at low drain voltage (Vd < 0.1 V) are used because
they can be accurately modeled using the Poisson equation and the driftdiffusion (DD) model , respectively. The device structure and doping profile
are obtained by varying the initial structure until the simulated C-V and ld-Vg
characteristics match the experimental ones. The main drawback to inverse
modeling is that it is based on experimental data of an actual device andcannot predict a device structure. Thus it is not possible to optimize a device
structure before or even after its technological realization if we only have
limited experimental data. This disadvantage of inverse modeling is partiallyovercome by means of the proposed inverse modeling technique.
In the next section, our inverse modeling program is described, and theprocedure for extracting the structures of deep submicron MOSFETs is
explained in section 5.3. In section 5.4, device simulation results based on
inverse modeling are discussed, and in section 5.5 how to vary the device
65structure for different process parameters without further inverse modeling is
described.
5.2 Inverse Modeling Procedure

Figure 5. I shows the flowchart of the inverse modeling assisting
program named MOSFIT using the commercially available GALENE-III as
the main device simulator. GALENE-111 consists of not only the standard DD
model but also the generalized hydrodynamic model (GHDM) [99]. The
inversionlayer mobility models implemented

are thesemiempiricalapproaches proposed by Lombardi et al. [I 00] and Mujtaba et al. [ 101], which
are sufficient for the investigated range of channel doping concentrations.
Since all simulations for the inverse modeling are performed in the linear
regime, the somewhat uncertain value of saturation velocity in the channel
and the approximations of the DD model do not influence the results[102,103].

Process Simulation Results

START
Initial Structure &Measurement Data
C-V or 1-V Simulationi.-----.
(GALENEID)

Check Simulation Error
Optimization Program(Generate Next Structure)
NO

END

Fig. 5.1 Flowchart of the " MOSFIT" program.

66

The device structure defined in terms of doping profiles, oxide thickness
and so on, is specified in the input file of GALENE-III, which is generated by
the MOSFIT program. A two-dimensional doping profile is expressed in termsof a combination of step, Gauss ian and error functions , avoiding complicated
2-D spline functions suggested by others [94]. The one-dimensional channel
doping Nch(x) is defined asN,(x)=N, exp{-( x ;,~fI}(5.la)

2

N ,(x)=N,exp{-( x;,~f }(5. lb)N,(x)=N,exp{-( x;,x,r}(5.2)

Nch (x) = Nc (x) + N 5 (X) + Nw,(5.3)

where Nc, Ns, N w, Xc, Dc1, Dc2,D 5 ,Ec1,Ecl> Es ·are fitting parameters, and xs is thecoordinate of the silicon surface. The polysilicon gate doping NP(x) is definedas(5.4a)(5.4b)

where Xgs is the coordinate of gate polysilicon/gate oxide interface and Ng,
xg, D 8 ,E 8 are fitting parameters. The two-dimensional source/drain extension

doping NeJx) is defined as

(5.5)

2

N (x ,y) =~2 exp{-( x ;:2 )E, }•if(-Y ::2)

N ex (x ,y) = N, (x, y) + N 2 (x ,y)

(5.6)
(5.7)

67

fitting parameters.
The inverse modeling procedure using MOSFIT is described as follows.
First a MOSFET device structure and its doping profiles in the input file areexpressed in terms of the above given functions using a process simulator
output. C-V or 1-V characteristics are calculated, and the values obtained arecompared with experimental results. Then MOSFIT calculates the error andthe fitting parameters of those functions are changed in the input file using afree-software-based standard optimization program generating the new device
structure. Then C-V or 1-V characteristics are again calculated and the values
obtained are compared with the experimental results. These steps are iterated
until a satisfactory convergence is obtained. We ensure that the discrepancy
between the measurement and simulation results is reasonably small in orderto achieve a good fitting. Finally, when MOSFIT is converged, the structure
file contains the inversely extracted device topography and doping profile
based on the calculated electrical characteristics.
S.3 Extraction of a Deep Submicron MOSFET Structure
In order to obtain a complete MOSFET structure in the deep submicron
range, the procedure described in the previous section is applied to at least
three different device structures. The first device structure is a large-area
MOSFET (or MOS capacitor) to extract the gate oxide thickness and thedoping profile inside a polysilicon gate based on C-V measurement data. The
second device structure is a long-channel MOSFET to extract a channel
doping profile using the body effect of the subthreshold drain current versus
gate voltage (Jd-Vg) characteristics. The third device structure is a widechannel or finger-gate MOSFET to extract the source/drain profile as well as
the polysilicon gate length using split gate-to-drain/channel capacitanceversus voltage ( Cgd-V) characteristics. Table 5 .1 summarizes the required
devices, measurement data and extracted parameters.

68

Table 5.1 Extracted parameters for each device and measurement data

Device typeMeasurement data

Extracted parameter

Large-area MOSFET

C- V

Gate oxide thickness, gate doping

Long-channel MOSFET

Body effect ofChannel doping

subthreshold Id-Vg
Wide-channel MOSFET

Cgd-V

Source/drain extension doping

It is well known that quantum effects have a strong impact on the gate
capacitance and that the Schroedinger equation should be solved selfconsistently

with

the

Poissonequation[104].

However,

since

the

Schroedinger equation solver is very CPU intensive, the quantum effects are
ignored in our approach. Figure 5.2 shows an example of the C-V
characteristics fora large-area n-channel

MOSFET (n-channel

MOS

capacitance) calculated without quantum effects (a) and with quantum effects(b). In both cases, gate oxide thickness is determined by fitting thecapacitance value at the maximum voltage in the accumulation region. Goodagreement between simulated results and measured data is found for bothcases in the inversion region, once the doping profile in the polysilicon gate is
fitted . In the classical case, the quantum mechanical effect is effectively
considered in the gate doping profile and oxide thickness value. A good fit of
the capacitance in the inversion region ensures that the device simulation
reproduces the correct threshold voltage and inversion layer charge. On theother hand, the slight deviations observed from the measured data in theaccumulation region for the classical case can be ignored because they do notaffect the MOSFET on-current characteristics estimation, which is our main
goal.
Figure 5.3 shows subthreshold ld-Vg characteristics of a 1.0- µ m
nMOSFET, comparing the measurement and simulation results after thechannel doping profile is extracted. This good fit guarantees the channel
profile accuracy over a reasonable range of depth. In Fig. 5.4 source/drain
doping profile fitting is demonstrated for the finger gate nMOSFET Cgd-V
characteristics for different substrate bias conditions.

69

6.0
- - measurement• simulation

5.0

4.0

(a)
3.0

2.0

-4.0

-2,0

0.0

2.0

4.0

Gate Voltage(V}6.0- - meas urement• simulation

s.o
~·

E

::1.

(b)

-- 4.0
~

'QJ

"c

::

'c:i

3.0

Cll

c.
Cll

u

2.0

1.0

-4.0

-2.0

0.0

2.0

4.0

Gate Voltage(V)Fig. 5.2 C-V characteristics of a large-area nMOSFET comparing measurement andsimulation results after t he gate oxide th ickness and doping profile of polysi licon gate
are determined.
(a) Classical calculation. ( b) Quantum mechanical calculation.

70

lO~ r-r-............,........,._,,__,....,.........,.............,.....--........._,..,.....,....,.....,,.....

10~

I=

.... 10-8
QI::s""""
0·;=

Vb=O.O(mes.)·-·- Vb=-1.0(mes.)
Vb=-2.0(mes.)----· Vb=-3.0(mes.)
Vb=O.O(sim.)
Vb=-1.0(sim.)
Vb=-2.0(sim.)... Vb=-3.0(sim.)

10-10

•

"" 10-12Q

10· 14
0.0

••

0.5

1.0

1.5

2.0

2.5

Gate Voltage[V]Fig. 5.3 Subthreshold Id-Vg characteristics of a 1.0- µ. m nMOSFET comparing
measurement and simulati on results after the channe l doping profile is extracted.
(Lines: measurement results, symbols: simulation results)

0.5 0 ............................................,...........................................,........P'T'T........,!""'1.•.•..
I

0.45

Vb=O.O(mes.)----- Vb=-3.0(mes.)• Vb=O.O(sim..)• Vb=-3.0(sim..)

•

••
~
~

0.21)

0.20 a...-.........i..............i..............i........~......................................................
-3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0

Gate Voltage[V]Fig. 5.4 Cgd-V characteristics of a finger gate nMOSFET comparing measurement andsimulation

results after the source/drain dop ing

measurement results , symbo ls: simulation results)

71

profileis extracted.

(Lines :In the case of deep submicron MOSFETs, it is a well-known fact thattransient enhanced diffusion (TED) causes channel impurity redistribution
and boron pile-up occurs just in the vicinity of source/drain junction [ l 05].
Therefore, the channel profiles should be different from that of a long-channeltransistor. By changing the channel profile to fit the body effect for eachchannel length, we can obtain the channel-length-dependent doping profiles.
For example the subthreshold ld-Vg characteristics of a 0.19- µ m gate lengthnMOSFET are shown in Fig. 5.5, demonstrating a good fit between themeasurement and simulation results. The final one-dimensional channel
profile in the depth direction for each nMOSFET is shown in Fig. 5.6. Inorder to confirm the extracted gate length (Lpoly) value from Cgd-V
characteristics, drain-induced barrier-lowering (DIBL) effects are also
checked for the subthreshold Jd-Vg characteristics of each transistor. Figure
5. 7 shows that the DIBL effect is satisfactorily reproduced from low to highdrain voltage for the 0.19- µ m nMOSFET.

10.J

.

.......--:..,...·' •..,,'.' ... ,." /..,/ ~------,I
Vb=O.O(mes.)

10·5

...

s::s.

.•.•A.,'~.... 10·7. .•.f~c::

Cll::s"'"'C)....c::Cl=:...I ! : ,''... ,,.

10·'

I

/,/

·' fl. ,'

10·11
•

I

10·13
0.0

JI I 1Ii 11.

.'.i ..,''Il ,',.• ....
:

•

I

I

Ill / ,'·-·- Vb=-1.0(mes.)
Vb=-2.0(mes.)----- Vb=-3.0(mes.)• Vb=O.O(sim.)• Vb=-1.0(sim.)• Vb=-2.0(sim.).... Vb=-3.0(sim.)
1.0

0.5

1.5

Gate Voltage[V)Fig. 5.5 Subthreshold ld-Vg characteristics of a 0.19- µ m nMOSFET comparing
measurement and simulation results after the channel doping profile is extracted.
(Lines: measurement results, symbols: simulation results)72

In order to obtain the linear Jd-Vg characteristics for a deep submicron
MOSFET, we must consider the parasitic resistance which occurs due to thecontacts. In the case of a salicide process, silicide layers are formed on thesource/drain contact regions. We include the silicide-to-silicon contact
resistance as a low-mobility region atop the source/drain regions as shown in
Fig. 5.8. The mobility value is determined to reproduce the ld-Vg
characteristics in the linear regime including the body effect, the result of
which is shown in Fig. 5.9 for the 0. 19- µ m nMOSFET. Figure 5. 10 shows thefina l two-dimensional device structure and doping profile for the 0. 19- µ m
nMOSFET produced by our quarter-micron dua l-gate CMOS technology w ith
a Co-salicide process [91]. The extracted doping and structure-relatedparameters are summarized in Tab le 5.2.

10 18---- - L=20.0[µm]- ······· L=5.0(µm]·-·- L=l.O(µm]
L=0.19[µm)

e

.....

CJ
.......

.......=
0'.

·--.......... . .
........
--.. ...... ------~==-----------------.......
-. :-..···--····-······--·····----:::::;- -----------·- ·-·-·-· -·-----...........
~

....f

=
=
~

CJ

0

u

10 17
0.00

0.02

0.04

0.06

0.08

0.10

0.12

Deptb[µm]Fig. 5.6 Mid-channel doping profiles depending on the gate length.

73

-Vd=O.l(mes.)·-·- Vd=l.5(mes.)
Vd=2.0(mes.)----· Vd=2.5(mes.)• Vd=O.l(sim.)• V d=l.5(sim.)• V d=2.0(sim.)... V d=2.5(sim.)
10-13 ......._...__......._._-........._._-........._.__._._._
0.6
0.8
0.0
0.2
0.4

_._.

1.0

Gate Voltage[V]Fig. 5. 7 DIBL effect for a 0.19- µ m nMOSFET comparing measurement and simulation
results after the channel doping profi le and gate length are determined. (Lines:
measurement results , symbols : simulation results)dµ=-qnRc

Re: Contact Resistance [Q crn2 ]

Gate

Drain

Fig. 5.8 Implementation of the source/drain contact resistance for linear Jd-Vg
calculation.

74

- - Vb=O.O(mes.)·-·- Vb=-1.0(mes.)
Vb=-2.0(mes.)--- -- Vb=-3.0(mes.)• Vb=O.O(sim.)• Vb=-1.0(sim.)• Vb=-2.0(sim.)• Vb=-3.0(sim.)

0.00 ...............-~~.................i.......................i..........--......i
0.0
0.5
1.0
1.5
2.0
2.5

Gate VoltageM

Fig. 5.9 Linear Id-Vg characteristics comparing measurement and simulation results
including source/drain contact resistance.

-0.03

-0.00

.1oza·

0.03

101 9.2

2m 1019.s
1019.51016.6
I:'° 1016.4

0.06.... 1016.1
11 7
·

mi 10

•1017.4

0 .09

17

0.12
0.40

•10
17
•-10

0.43

0.46

0.49

0.52

0.55

Fig. 5.10 Final two-d imensional structure and doping profile of a 0.19- µ m nMOSFET.
(Unit; µ m for axes and cm· 3 for contour lines)

75.,..___________________________~~~~~~~~------~~II

Table 5.2 Extracted doping and structure-related parameters for a deep submicronnMOSFET (Lpoly=0.19 µ m) .Gate oxide thickness is 6.3 nm and contact resistance is
160Q µ m.

Gate doping

Ng(cm·3 )1.000 XI 0 20xg( µ m)-7. 91 7 x 10· 3Dg( µ m)8.951 x 10· 4

Eg

2.000

Channel profileNs(cm" 3 )-4.777Xl0 17

µ m)

0.000

Ds(µ m)1.917 X I 0·2

Xs (

1.526

Es
3

Nc(cm- )- l.31 5X 10 17xc(µ m)6.000 x 10·2

Dc1( µ m)

1.000

E c1

2.000
9.993 x 10· 1

Dc2( µ m)
Ec2

l.019

Nw

-8.000 x 10 16

Source/drain extension profile

N,(cm- 3 )l.500 x 10 20

x 1 ( µ m)

2.514 x 10· 7

D 1( µ m)

l.588 X I 0· 2

E,

1.998

R1 ( µ m)

1.125 x 10· 2y,( µ m)Lpoly/2

76

N 2 (cm-3 )1.784 x 10 19

X2 (/J.ffi)

2.200 x 10- 2

D 2( µ. m)

3.305 x 10- 2
1.842

E2

R 1 ( µ. m)

3.244 X 10"2Y2( µ. m)

Lpoly/2+0.02

5.4 Saturation Drain Current and Substrate Current

Based on the extracted deep submicron nMOSFET structure, the carriertransport in the high tangential field regime is investigated. Figure 5.11 shows
the saturation drain current versus drain voltage (Id-Ve/) characteristics of the
0.19- µ m gate length nMOSFET, comparing the measurement and simulation
results using the GHDM implemented in GALENE-111. In this simulation, thesaturation velocity in the inversion layer is set to be the experimental value of
9.23 X 10 6 cm/s obtained by Cooper and Nelson [102]. This value was derived
by a time-of-flight experiment using a large resistive gate MOSFET. Recently,a UC-Berkeley group has reported slightly lower values using thick gate oxidebulk and silicon-on-insulator (SOI) MOSFETs. These values range from 8.1
6

X 10

cm/s to 8.9 X 10 6 cm/s [103]. Therefore, the value at which thesaturation velocity is set may be slightly controversial, but our results
strongly suggest that the value obtained by Cooper and Nelson is reasonable.
The detail of the carrier transport model in MOSFETs will be discussed in thenext chapter.
The substrate current characteristics of the same MOSFET, calculated by
our full -band Monte Carlo device simulator FALCON are shown in Fig. 5.12

[ 106]. It is worth noting that our impact ionization model has been tuned toreproduce experimental results for the bulk impact ionization coefficient andquantum yield [ 107, I 08], and thus does not include any device-dependent
fitting parameters. The good agreement between the simulation andexperimental results for the drain and substrate current without any further
fitting demonstrates the high quality of the device structure and doping
profile obtained using our inverse modeling technique. The inverse modeling77

technique bas been successfully applied to other devices with quite different
device structures shown, for example, in [ 108].
The details of the full-band Monte Carlo device simulator FALCON will
also be discussed in the next chapter.

0.7
0.6

I

0.5

-::
c

0.4

:I

0.3

...,..

t.J..• .,..... ...........

I

JI•.. 0.2••••• Vg:=l.O(mes.)-_...,...,...-.>r1~~~~ -·-·- Vg:=l.5(mes.)
Vg:=2.0(mes.)

·'.•

.9
Q

~-

~

-

·'

•
•
•
•

....'.............
o.o ___....._ _..___ _....._ _..___ _,....................................... -c ...

0.1

0.0

0.5

1.0

l.5

2.0

Vg:=2.5(mes.)
Vg:=l.O(sim.)
Vg:=l.S(sim.)
Vg:=2.0(sim.)
Vg:=2.S(sim.)

2.5

Drain VoltageM

Fig. 5.11 Jd-Vd characteristics comparing measurement and simulation results using the
GHDM by GALENE-lll for a 0.19- µ m nMOSFET. (Lines: measurement results,
symbols: simulation results)•,.-·-·---·-·-·....·-·-·-·a.--·--,· ____.......

_....._~~-11~~~~~~/fj,· /....--··-----···...........
Z
j ii
/ /'

~........

; ,•
; •

/-~-

i

10"'

I/ ,..,

i : ,

0.0

:

-._.-_

•

•

---

•

--

,· .' i10·11 •

· - Vd=l.ti(mes.)••••• Vd=2.0(mea.)••~t~:~~=~~

Vd=3.5(mes.)
Vd=LS(sim.)
Vd=2.0(s.i m.)
Vd=2.S(sim.)
Vd=3.0(sim.)
Vd=3.S(sim.)

•

0.5

1.0

1.5

2.0

2.6

Gate VoltageM

Fig. 5.12 Substrate current characteristics comparing measurement and simulation
results using the full-band MC simulator FALCON for a 0.19- µ m nMOSFET. (Lines:
measurement results, symbols: simulation results)78

5.5 Device Characteristics Prediction
In this section we demonstrate that our inverse modeling technique is not
only able to reproduce experimental results but is also able to predict l-V
characteristics of differently processed devices [95). In Figs. 5.13 and 5.14,
the predicted and experimental values of J-V characteristics for saturation
drain currents and substrate currents are shown for a device with asource/drain extension implant dose ten-times lower than that of the 0.19- µ
m gate length nMOSFET. The device structure is the same as that of theabove-mentioned device with the exception of the peak values N 1, N 2 of theGaussian functions (eqs. (5.5) and (5.6)), which are decreased to one-tenth of
those for the 0.19- µ m gate length nMOSFET, having a gate oxide thickness
which is proportionally changed using optical measurement data after the gate
oxide growth. Based on this predicted device structure, the simulation
reproduces the terminal current voltage curves very well. Though it has notbeen shown here, similar results are obtained when the channel implant doseis changed [95]. Thus it is possible to determine device structures under
different process conditions without any further inverse modeling, removing
one of the main obstacles of device optimization based on inverse modeling.

0.7 ,_....-........~.........-........-~.........-___,

I.

0.6

••••
o.G

c 0.4
:::

1.0

2.0

1.5

.

_

_

_

_

.

.

.

.

.

.

.

_

.

.

.

.

_

.

.

_

_

~

_

.

.

_

o.o _ _ _.__
o.o
0.5

.

__...,..............-

.

c

f 0.2
Q

.

· ··-· Vg=l.O(mes.)
Vg=l.5(mes.)......- - - , ·- ·- Vg=2.0(mes.)
Vg=2.5(mes.).. Vg=LO(sim.)• Vg=l.li(sim.)• Vg=2.0(sim.)• Vg=2.5(sim.)

8 0.3

2.5

Drain Voltafe[VJ

Fig. 5. 13 ld-Vd characteristics comparing measurement and predicted simulation results
using the GHDM by GALENE-III for a different 0. 19- µ m nMOSFET of whichsource/drain doping concentration is scaled to one-tenth. (Lines: measurement results,
symbols: simulation results)

79

10...

____.

I lo"'

3.

c 10"'
~

G>

,.

•

o l0.1

__

,·'

,. /
:·

;
!:
~
~

/j/
10·

I •:•

11

11

•

•

..

f.;!',,''····-·····--~..................~..
Ii/,............

lo"'
io..
10·

•
."!..-·-·-·-'!-·-·-·----·-·-···__,_.•.:ti, /
•

"' •

0.0

0.5

•

,..,·'-··_,.

·.11.-'t/i I\,· \ r., ~: /1.~

•

:

•

1.0

1.11
2.0
Gate Voltage[VJ•··- Vd=l.5(mes.)••••• Vd=2.0(mes.)
Vd=2.5(mes.)••·• Vd =3.0(mes.)
Vd=3.5(mes.)• Vd=l.5(sim.)• Vd=2.0(sim.)• Vd=2.5(sim.)• Vd=3.0(sim.)• Vd=3.5(sim.)•

2.5

Fig. 5.14 Substrate current characteristics comparing measurement and predictedsimulation results using the full-band MC simulator FALCON for a different 0. 19- .um
nMOSFET of which source/drain doping concentration is scaled to one-tenth. (Lines:
measurement results, symbols: simulation results)

5.6 Conclusions
The proposed inverse modeling technique is simple, because it is basedon simple analytical functions for the doping profile available in standard
device simulation programs. On the other hand, it is flexible, because thedifferent parts of the doping profile arc extracted independently. Based on the

resulting device structure, device simulation yields good results not only forthe linear regime but also for the hot-carrier regime for which no fitting was
carried out. In addition, it is possible to vary the device structure to model
devices processed under different conditions. Good agreement between thesimulation and experimental results is found for these devices without any
further inverse modeling. This makes it possible to use the extracted device
structure for device optimization or the investigation of device parameter
fluctuations.
80

Chapter 6

Carrier Transport in MOSFETs

6.1 Introduction

To design hi gh performance deep submicron MOSFETs, it is importantto understand carrier transport phenomena in MOSFETs with the consistencyof physical models compared to observable electricalcharacteristics,

especially in the high-field or hot carrier transport regimes. The carriertransport behavior in MOSFETs can be described by the Botlzmann transport
equation (BTE) for electron and/or hole gas in crystalline silicon. Although
the original BTE was presented by Boltzmann to describe the behavior ofclassical gas more than one hundred years ago, it can be applied to thequantum mechanical elementary particles, or the electrons and holes inmodern semiconductor devices [ l 09].
Among three terminal semiconductor devices silicon MOSFET is socalled a surface device . A conductive channel region is induced by a gate
capacitance between source and drain pn-junctions. In the channel region
electrons (nMOSFET) or holes (pMOSFET) flow from the source (grand) tothe drain according to a supply voltage. Near the source of an enhancement
MOSFET, the inversion layer acts as the channel, but the channel depth
gradually diminishes along the channel. Beyond a pinch-off point the channel
disappears and the carriers flow like those in bulk silicon. Therefore, in orderto describe the carrier transport behavior in MOSFETs, both two-dimensional
and three-dimensional electron or hole gas should be characterized . Moreover,the channel carriers are scattered by donor or acceptor ions, lattice phononand surface roughness irregularity. In the vicinity of the drain junction very
high-electric field exists and causes impact ionization (II) scattering. These
scattering mechanism are inherently important to describe the carriertransport behavior or the terminal

current voltage characteristics

in

MOSFETs.
This chapter discusses the carrier transport phenomena based on the BTE
by investigating several approaches to tackle the transport models and clarify
which model should be used to describe electrical behavior of deep submicron
MOSFETs. In the next section, some approaches to solve the BTE are
discussed and especially the hierarchy from Monte Carlo particle-based model81

to fluid-based models, mainly from the viewpoint of non-equilibriumtransport, is focused . Then, in the third section some controversial argumentsof impact ionization models are discussed and clarified, followed by the final
conclusion section.

6.2 Modeling of Carrier Transport in MOSFETs
Basic equations to describe the carrier transport in silicon are the BTE,
Poisson equation and Schroedinger equation . The last one is only needed
when an inversion layer exists and electrons or holes behave as twodimensional gas. Among these equations the BTE is the most important and it
describes the distribution functionf (r ,k ,t) as follows :ff =(!!) ,(6.1)
I!+ di V ,f - qE(r,t)Va dt
a Collwhere r is the position vector, k is the momentum vector, q is the electron
charge, t is time, Eis external electric field and "Coll" means the collision
term by scattering. In order to solve this equation the most accurate way is theMonte Carlo (MC) particle method. The BTE is self-consistently solved with
the Poisson, and in some cases, Schroedinger equations.
6.2. 1 Particle-Based Model
Recent dramatic improvement of MC approach can make it possible toconsider MC simulators as an engineering tool [110-112] . The sophisticatedMC simulators contain accurate enough physical models to describe thecarrier transport in silicon MOSFETs. Not only the full-band (FB) structure
obtained by the pseudo-potential method but also impurity-carrier scattering,phonon-carrier scattering, surface roughness scattering and II scatteringmodels are implemented. As a result, as far as the carrier transport in bulk
silicon is concerned, there is no large discrepancy for the electron-phonon
scattering rates and impact ionization rates derived from various MC
simulators [ 113]. Even a CPU time problem has been resolved by combining astatistical enhancement technique like the multiple refresh method [ 114, 115 ],and a suitable convergence estimation method if self-consistent calculation82

with the Poisson equation 1s not necessary m such a case as to calculate
substrate currents [ 112, 116, 117].
6.2 .1. l Full-band Monte Carlo device Simulator - FALCON
Now, the sophisticated approach to reduce calculation time in the FBMC device simulator FALCON [112] is described . The most CPU intensive
part of calculation for scattering events in FB-MC simulation is the selectionof the final state in k-space after the scattering process and final energy band
have been decided. The time is spent mainly to find the final tetrahedron in
the grid of the discretized FB structu re. The probability of selecting a certain
tetrahedron, or the discretized k-space volume, is proportional to thetransition rate integrated over all possible final states contained in thetetrahedron. In [118], the transition probabilities (TP) are calculated for all
possible tetrahedra and the final tetrahedron is selected with the direct method ,or by gathering all possible probabilities however they may be small [ 119] .
This method consumes large amounts of CPU time, because the calculation of
the TP is CPU intensive and the number of possible final tetrahedra is verylarge. By using the acceptionlrejection (AIR) method [ 119], instead of thedirect method, the CPU time consumption can be reduced. With this method afinal tetrahedron is selected by choosing one of the possible final tetrahedrawith uniform probability which plays a threshold-like role . The selected
tetrahedron is accepted, if its TP is larger than the upper bound of the TP
times a uniformly distributed random number. Instead of calculating the TP
for every possible final tetrahedron, in the case of the AIR method, the TP iscalculated only for the selected tetrahedra. The number of AI R events is g ivenby the ratio of the upper bound of the TP to the average TP. As long as thisratio is smaller than the number of possible final tetrahedra, the AIR method
is faster than the direct method because the TP is evaluated less frequently .
This is the case for the scattering models given in [1 20] for which in averageless than 11 AIR steps (evaluations of the TP) are necessary. Since thisnumber is much smaller than the number of possible final tetrahedra, which isusuall y in the hundreds or thousands, the AIR method is faster than the direct
method without any approximation.
The upper bound of the TP can be calculated easily for the employed83scattering models [ 120], because the TP is proportional to the density of states(DOS) in each tetrahedron which depends only on energy. In the beginn ing ofa simulation an energy dependent look-up table is built w hich contains the
maximum DOS of the set of possible fi nal tetrahedra for the given energies.
Moreover, lists are built of all tetrahedra contai ning certain final energies.
With these lists, which are of the size of a few MBytes and built only once, it
is quite simple to select a fina l state. In Fig. 6. 1 the method is shown for ascattering process with a co nstant final

energy. Generali zation to a

momentum-dependent final energy is straightforward and does not necessari ly
impair efficiency. The same is true for a more complex momentum
dependence of the transition rate or a higher number of final tetrahedra
resulting from a finer grid in k-space, as long as the ratio of the upper boundof the TP to the average TP is not increased.

Get list of all
tetrahedra
containing the final
energy £ from table
Get Max{DOS(e)}from table

Select a tetrahedroni from list withuniform probability

yes
Select final state
within the selected
tetrahedron
Fig. 6.1 Flowchart of the acceptance/rejection method for the selection of the final state
after scattering (random number r uniformly distributed in [O , 1])84

l

The combined use of the AIR method for the selection of the final state
after scattering and the linear interpolation of the FB [ 111] together with thevariable 1 -scheme (the way to change the highest scattering rate dependingon the carrier energy to reduce self-scattering event) [ 121] and the efficient
formulation of the scattering processes [ 120] makes the program much fasterthan other FB-MC approaches [110, 119] without a loss in physical soundness
or numerical accuracy. The AIR method for the selection of the final state isso fast that less than 10% of the CPU time for a device simulation is spent forfinding the final states, thus making, for example, the stringent approximationof cellular automata [122] unnecessary.
the

In

case

of non-self-consistent

FB-MC

devicesimulations[ 116, 117, 123] the simulation particles are uncorrelated and the convergencecan be estimated with standard textbook formulas [ 116, 117, 124]. The average
substrate current (I) and its standard deviation

I N
I = - I I; andN i=I

2 -2] ,

1 [ I Na = - - - I I; -I-2

N -1 N l= I

a are:(6.2)

where I; is the substrate current generated by the particle i. From the central
limit theorem it follows that the distribution function of I approaches aGaussian distribution (124] and the probability (confidence level Peon) that I
is within the confidence interval of + 2 a around the expected value of I is:Peon ::::1

1
_2
2rca

.J

f:o:exp(- 2ax )dx 95.45%
2

2

=

(6.3)

Using the relative error r err== 2 a I I the simulation runs are stopped when arelative error of + I 0% (with a probability of 95.45%) has been reached.
6.2.1.2 Simulation Results by FALCON
Figure 6.2 shows the substrate currents of a 0.18- µ m and 1.0- µ m
nMOSFET calculated by FALCON and experimental results. The MOSFET
structures including the doping profiles are determined by the inverse
modeling technique as described in Chapter 5. The simulations have been85

I

performed without any statistical enhancement method, and the CPU times arefor a Super SPARC workstation. To our best knowledge these CPU times are
the small est ones achieved on an ordinary workstations for FB -MC
si mulations so far compared to other works [ 11 J, 125).

10·2

'E

~

10·3

.D

::>

CJ)

10·4

10·5
0.00

0.50

1.00

1.50

2.00

2.50

v gate [VJ
10·1
10·2

E

10·3

u

~
.D

•

10·4

::>

fl)

105

c.

10·6

0.0

0.5

1.0

1.5

2.0

2.5

3.0

Vgate [V]Fig . 6.2 Substrate current and CPU times for (a) a 0. 18µm nMOSFET and (b) a ·l.Oµm nMOSFET for different drain voltages. (Lines : experiment, Symbol: FB-MC
simulation)86

6 .2 .2 Fluid-Based ModelAs MOSFET is inherently a surface device, the carrier transport not onlyin the bulk but also at the surface should be accurately modeled. When the
inversion layer is modeled rigidly, the Schroedinger equation in addition to
the BTE and Poisson equation should be solved self-consi stently. Thissituation still causes the largest problem of the MC method, or the CPU timeburden. Therefore, as engineering tools we should use both FB-MC particlebased and fluid-based device simulators.
6.2.2. l Hydrodynamic Model versus Energy Transport Model
To so lve the BTE based on the fluid model , there are two approaches, anequilibrium way and a non-equilibrium way . The former is the so-called
drift-diffusion (DD) model. It is useful if the carrier temperature is low
enough to be nearly equal to that of the lattice, but it cannot be applied todeep submicron MOSFETs in high tangential field operation regime . The
latter approach contains two major non-equilibrium approximation methods.
These were believed to be suitable to solve the non-equilibrium carriertransport in the case of deep sub micron MOSFETs when carrier temperature is
far higher than the lattice temperature. In both approaches the BTE is
multiplied by powers of the momentum and integrated over momentum space
to result in "balance equations". The first one was originated to Stratton andcalled energy transport model (ETM) or energy balance model (EBM) [ 126].
The second one was proposed by Blotekjaer and called hydrodynamic model(HDM) from the analogy of fluid dynamics [ 127]. The difference of theseapproaches is already discussed by Apanovich et al . including terminology
comments for the ETM and EBM (128]. To solve the problem of the standard
or conventional HDM, the ETM was suggested as a better alternative[ 128, 129]. (Here, the term ETM is used as the same as EBM.) However, theapplicability of more sophisticated version of HDM or the generalizedhydrodynamic model (GHDM)[99] was never discussed in detail. Therefore,

in the next subsection this dissertation shows the difference of the GHDM
compared to other conventional HDM or ETM and clarifies the usefulness of
the GHDM to describe the carrier transport in deep submicron MOSFETs.

87_________________________________________
lI_.

6.2.2.2 Generalized Hydrodynamic Model
To avoid too strong velocity overshoot near the drain junction sufferedby the conventional HDM, the convective term or the thermal diffusion
current term is omitted in the case of the ETM [128, 129]. At a glance, thisassumption seems to be reasonable because the singularity of the carrier
velocity at the drain side is eliminated . But this situation is often
demonstrated by using a one-dimensional simple n+-i-n+ diode as a test device.
We must remember that MOSFET is never one-dimensional but at least twodimensional device even in the case of a long width transistor. The heatedcarriers in the vicinity of the drain junction act as a heat source for thethermal diffusion (convective) current, and it flows from the drain not only tothe source but also to the substrate in addition to the heat flux (conductive)
current. To the contrary, in a one-dimensional n+-i-n+ diode the electrons by
the thermal diffusion current as well as heat flux only flow from the drain to
the source. We can never estimate the deep penetration feature of hot carrier
distribution toward the substrate at the vicinity of the drain junction.
Therefore, the n+-i-n+ diode is not a suitable test device to check the model
accuracy of the carrier transport in MOSFETs. In order to testify the accuracyof the models, MOSFET itself must be used .
The most important standpoint of the GHDM is that it tries to solve theproblems encountered in the conventional HDM without neglecting thethermal diffusion current term . Too high carrier temperature or too large
velocity overshoot found in the conventional HDM is mainly caused by theparabolic band approximation. Real band structure of silicon is neither
parabolic nor uniform. This means that the effective mass of an electron cannever be expressed by a single scalar quantity, but that it must be a tensor
value and that carrier temperature can never be defined uniquely. Moreover,in the case of the conventional HDM the heat flux is estimated too large
resulting in deep carrier penetration toward the substrate at the vicinity of thedrain junction. To overcome these problems, from highly heuristic insight thatthe electrons in crystalline silicon still behave like classical uniform gas [130],
sophisticated modifications for the balance equations were developed basedon the following key features ;a) The carrier temperature is redefined by kinetic energy, not by average88energy or band energy.
b) In order to express the kinetic energy, the effective mass of electron isdefined by the average of an effective mass tensor trace.
c) By using these modified scalar temperature and effective mass, relaxation
times for momentum, energy and energy current flow are redefined.
d) The Wiedemann-Franz low for thermal conductivity is modified by a factorof the redefined relaxation time ratio between the energy current flow andmomentum.
These modifications

seem

to

be

trickyandmayarousesome

controversial issue concerning their physical meaning. However, thesemodified parameters are directly obtained by MC simulators using a simp lebulk test device [99], and, of course, a FB-MC device simu lator can also be
used for such a purpose [131]. Once those parameters are fixed , the numericalapproach for the conventional HDM based on relaxation time approximation
is extensively applied to solve the balance equations for the GHDM. The
appropriateness of the GHDM should be checked by MOSFET electricalcharacteristics.
For the carrier transport m the channel or the inversion layer, theSchroedinger equation should be so lved in addition to the Poisson and balance
equations. Otherwise, as an alternative way, the inversion layer mobility canbesemi-empirically

expressedmthebalanceequations

based

on

Matthies sen-rule like expression [ 100, 10 I]. In this case the effective fielddependent universality of low tangential field drift mobility should reproduce
experimental results. This requirement guarantees the accuracy of impurity
scattering, phonon scattering and surface roughness scattering models for the
inversion layer mobility. Moreover, the inversion layer mobility should
consistently reproduce high tangential field dependent carrier velocity
obtained by experiments. Although this approach is not rigorous to describe
the carrier transport in the inversion layer, the applicability should again bechecked by MOSFET itself
6.2 .2 .3 Guarantee of Simulation Accuracy by GHDM
As already shown in the previous chapter, if we can identify accurate
device structure as well as doping profiles in MOSFETs, the saturation drain
89currents are well simulated with a good fit to experimental results . Even , wecan predict ld-Vd characteristics for differently processed MOSFETs once we
use a well-defined device information based on inverse modeling as far as thedevice structure is not completely different . These results clearly demonstrate
the accuracy of the GHDM approach because no fitting on device level suchas the manipulation of doping profile, gate oxide thickness, gate length toreproduce experimental results is introduced. Only one fitting parameter is thesaturation velocity for the inversion layer, but it was set to be the value
obtained by a quite different experimental way, or the time-of-flightmeasurement. This fact is another proof to guarantee the physical models
implemented in the GHDM approach. Of course, there is still uncertainty toextend the GHDM to sub-0. 1- µ m gate-length regime, at least the GHDM canbe applied to subquarter micron gate length nMOSFETs.
6.3 Impact Ionization in MOSFETs
In deep submicron MOSFETs the high electric field near the pinch-off
point makes the carrier energy higher and so-called hot carriers are generated.
They induce II scattering and generate electron-hole pairs. These hot carriers
are the source of MOSFET reliability problems and there is always trade-off
between higher drain current and shorter device lifetime induced by the hot
carriers. Therefore, to utilize the maximum performance of MOSFET the
reliability edge for the best performance point should be detected as precisely
as possible. For this purpose the FB-MC device simulator is the mostpowerful tool to investigate the hot carrier properties. It is well known thatnMOSFET substrate current originates from the holes generated by II at thevicinity of the drain junction and is a very good monitor to guarantee thedevice lifetime. Concerning the II phenomena, recent FB-MC simulators
contain a state of the art model which has been tuned to reproduce
experimental results for the bulk impact ionization coefficient and quantum
yield (106, 125]. Electric field distribution in a MOSFET is in between these
two extreme cases as shown in Fig. 6.3. Therefore, the accuracy of the model
should be guaranteed by observable electrical characteristics such as substratecurrent of MOSFET.

90

JI coefficient

MOSFET

Quantum yield

p
0

t

e

n
t
i

a
I

F
i

e
I t - - - - - --

- -

d

x

x

x

Fig . 6.3 Schematic potential and electric fields for the II coefficient (left), at the
Si/Si02-interface of a MOSFET (center) and for the quantum yield experiment (right) .

6 .3 . 1 Impact Ionization Models

In the case of fluid-model-based device simulators, the II models can be
implemented in the balance equations. The local field model based on
Chynoweth's approximation [132] is the oldest and simplest. In this case, theelectron II generation rate G11 is expressed :Gu= a (P)ljn(P)I(6.4)

a (P)= a coexp(-E)E(P)) ,(6.5)
where P is a point in space, a co, Ec are parameters and j" is the electron
current density. Chynoweth ' s approximation (eq. (6.5)) describing

a

as a

function of the local electric field is well justified in silicon under nearlyhomogeneousmaterialparameters aand Ec over a large range of field strength.

CX>

and

field

conditions withdopingindependent

However, inside a MOSFET the electric field is strongly inhomogeneous
so that the approximation (6.5) becomes very poor. In order to overcome thisproblem, local temperature model and non-local lucky electron model havealso been proposed. The local temperature model expresses the II generation
rate as a function of local carrier temperature, and the lucky electron model
treats hot electron as a non-locally unscattered lucky carrier that gained91

higher energy from external field than the average energy. Especially, thenon-local lucky electron model contains the hard threshold model and the soft
threshold model. The II energy in silicon shows no abrupt threshold because
of indirect transition nature between valence and conduction bands caused byits band structure. As far as the electric field is much higher than the II
threshold, the hard threshold model can be applied without any serious
problem. But, when supply voltage is low enough for the electric field to bearound the threshold, the hard threshold model can no longer reproduce
experimental results. By using the soft threshold model, low voltage impact
ionization around the impact ionization threshold regime can be investigated[ 107]. Nevertheless, in this chapter the detail of these II models using fluid-

based models will not be discussed because the most accurate II model isbased on the particle-based FB-MC model.
6.3.1 Surface Impact Ionization
The term surface II was introduced in [ 13 3] and describes the effect that
the II coefficient in the vicinity of the Si/Si0 2-interface in MOS devices
seems to be reduced. In Fig. 6.4, II coefficients for CCDs (charge coupleddevice) and MOSFETs are shown which were obtained by reverse engineering
based on the local-field-DD model [133]. Comparison with the bulk casereveals a considerable reduction of the II coefficient close to the interface.
Different reasons are given for this effect and they will be discussed in thefollowing.
In [ 133 , 134] the difference between surface and bulk II is attributed to
the reduced mean free path of the carriers in the vicinity of the interface.
Within the lucky electron concept (135] the critical field in Chynoweth's law
in eq. (6.5) is inversely proportional to the mean free path A.:(6.6)
where q is the electron charge and E TH the threshold energy. A reduction inEe==

E rnl(q A) ,the mean free path, due to the enhanced scattering at the surface, results in alarger critical field and a reduced II coefficient. In the FB-MC model themean free path at the MOS interface is smaller due to surface roughness
scattering. But it has been doubted [125], that this effect is responsible for thestrong suppression of II in MOS devices. In Fig. 6.5 substrate current

92modeling results are shown, which were calculated with and without s urface
roughness scattering, and the observed differences are far too small to explain
the effect of surface II seen in Fig. 6.4.

104

'E

~
....
c<ll
;g

103

.

102

0

Qi
0

(.)

FB-MC

·· -- CCD
1

10--- MOSFET

-Bulk
10°
2 .00

4.00

6.00

8.00

10.0

1/E [cm/MV]

Fig. 6.4 II coefficient versus inverse electric field for bulk silicon (solid line) as givenby van Overstratton, fo r MOSFETs (dashed line) and CCDs (dotted line) by Slotboom[ 133] and FB-MC results (symbol ).

0.00

0.50

1.00

1.50

2.00

2.50

vgate [VJ

Fig. 6. 5 Substrate current versus gate voltage for the shallow source/drain extens ion
0. 16 µ m-nMOSFET (Vd=l.5,2.0,2.5,3.0,3.5V). (Lines: measurement, 0: FB-MC withsurface roughness scattering, + FB-MC without surface roughness scattering)93

To continue exploring the reasons for the different findings in [133] andtn thiswork, the CCD experiment of (133] is re-investigated. The lateralelectric field given in [133] for case B of the CCD experiment and thecorresponding spatial II generation rates are shown in Fig. 6 .6. The generation
rates have been calculated with the local field (LF) model with the bulk
parameters, the local field model with the surface II parameters of [ 13 3] andthe FB-MC model. In [133] it is stated that the local field model can beapplied to this case, because the electric field does not vary much overdistances comparable to one mean free path length which is in the order of 10
nm. Our FB-MC results, which are based on the best microscopic II model
available today, show that this statement is not correct. If it were correct, theresults of the local field model with bulk parameters and FB-MC should be
the same for the field distribution in the CCD experiment since FB-MC
reproduces the bulk results under homogeneous conditions (see Fig. 6.4) . But
as shown in Fig. 6. 7 the maximum .FB-MC II generation rate is strongly
reduced compared to the local field model with bulk parameters showing thatthe local field approximation fails for the rapidly varying electric fieldpresent in the CCD. The local field approximation is only valid, if the electricfield is nearly constant over the distance, which the electrons have to cover togain the energy necessary for II. The threshold energy of II is at least the gap
energy (1. leV). To gain this energy from the electric field given in Fig. 6 .6
the electrons have to travel along a distance of more than 70 nm, along which
the electric field varies strongly (roughly a factor of 2). Therefore thecondition of the nearly constant electric field is violated and the local fieldapproximation fails .
By reducing the II coefficient (switching from bulk to surface II) the
local field model can reproduce the reduction of the II rate (This effect has
been discussed in detail for exponentially growing fields in [ 13 6, 13 7]), but
the microscopic details are still poorly represented (see Fig. 6.6). The local
field model can neither reproduce the threshold characteristics of II nor the II
generation rate in the field free space on the right side. The experimentally
accessible multiplication factor can be calculated by integrating thegeneration rate over the device area, and in Fig. 6. 7 the results are shown for
the three different II models. For comparison the experimental results of [133]are shown. (The assumed electric fields may not exactly reproduce the94original ones of [ 133] . Nonetheless, the electric fields are similar to the onesof [133] and it is clearly shown that the local fie ld model fails due to thenonlocal nature of the transport caused by these strongly inhomogeneo us
electric fields.) The results of the local fie ld model relying on surface IIparameters agree well with the ones of the FB-MC model while the local fieldmodel with bulk parameters yields consistently higher values. This means thatthe suppression of the II coefficient in the case of the local field model isnecessary to counterbalance the overestimation of the II generation ratecaused by the failure of the local field model under inhomogeneous field
conditions. The effect of surface II found in [133] is therefore due to theinadequate local field model and not due to a difference of physics in bulk
si licon and at the surface of MOS devices.

1026

.. ·:

..
.
.
.. . ;~

250.0........
E(.)>........

200.0

~

'U
Cl>

-

(.)

150.0

..

..... ,,, ,I,' I..... , , f
...
i

Cf)

'·

,:,.

1024

"",.

I

I

I

100.0

1022
1020

I
;
;

.
•.i
,

1018

~

-

m
c
:i...

:i...

Cl>

c

Cl>
O>

i

1.60

.._
........

m

i
i

0.000

0

;

50.00

E
<D

I

I
I

("')

(.)

I

(.)

w

.,..,::"',

I

:i...

Cl>

,

-........

~

1016

1.70

1.80

1.90

x [µm]
Fig. 6.6 Electric field (solid line) and II generation rate for the case B of the CCD
experiment [ 133] calculated with the LF model based on bulk parameters (dotted line),
based on surface parameters (dashed line) and FB-MC results (dashed dotted line).

95-

.• .•••.•• ..

..
•

''

''

.
..

''

''

''

3.0 3.5 4.0 4.5 5.0 5.5 6.0

1/EMax [cm/MV]
Fig. 6.7 Multiplication factor for case B of the CCD, measured (solid line) [133),
calculated with the LF model based on bulk parameters (dotted line), based on surface
parameters (dashed line) and FB-MC results (symbol).

In [125] a theoretical model for II in nMOSFETs is proposed which
considers the quantization of the inversion layer. It is found that the II
coefficient in the inversion layer decreases with increasing electric field
perpendicular to the interface. For very high electric fields perpendicular to
the interface and under otherwise homogeneous conditions this II coefficient
is similar to the results found in [13 3] (see Fig. 11 of [125]). But the situation
in a MOSFET is different, because II mainly occurs behind the pinch-off
point, where the electric fields are too weak for a considerable confinement of
the carriers. In Fig. 6.8 the average value of the confining field, at theposition where II occurs is shown for the shallow source/drain extension
nMOSFET. Only confining (positive) electric fields perpendicular to the96interface (Ever) are taken into account and the average field (Ea ve) is defined asfollows:f (x, Y'f:>(Ever (x, Y))G(x, Y)dxyEver

fG(x,y)dry

E.,, =(6.7)
where G is the II generation rate. Only in the case where the gate voltage islarger than the drain voltage does a substantial confining field arise. But thesefields are still small compared to the fields necessary to reproduce surface IIwith the model proposed in [ 125] . Moreover, the strong dependence on theconfining field implies that the effect should be negligible for small gate
voltages. This is in contrast to the effect of surface II which reduces substratecurrent even for gate voltages near the threshold voltage. This means that thegenuinely new effect proposed in [125] does not explain surface II as
described in [133] and is only of minor importance regarding the problems
discussed in this work.

200.0....-.

E(.)

Vdrain = 3.5V

150.0

Vdrain= 1.SV

> 100.0
~

~

"O
Q)

;:

w

--- -- --50.00

0.000 ~--~----,...-------~
0.50

1.00

1.50

2.00

2.50

Vgate [V]Fig. 6.8 Confining electric field averaged with the II generation rate for the 0.16 µ mnMOSFET.

97

Another explanation for surface II is mechanical stress at the interface
due to the formation of the oxide. The magnitude of the stress should varywith the oxide thickness and accordingly the impact on II. Since the reported
FB-MC simulations are in close agreement with experiment for the full rangeof oxide thickness (5 . 3-42 nm) without accounting for mechanical stress [ 13 8],
it has to be concluded that the impact of this stress on II seems to be a minor
one. The same can be said for other unknown effects which might depend on
the specific process technology. The investigated devices belong to three
distinctly different technology generations (256KBit, J 6MBit, lGBit) andgood

resultsareobtainedbyabove-mentioned

FB-MC

simulations,irrespectively of the technology and without any fitting of model parameterson device level [107, 138].

6.4 Conclusion
To design deep submicron MOSFETs, especially in hot carrier transport
regimes, accurate physical models must be implemented in device simulators.
For such a purpose, we need particle-based FB-MC simulator for hot carrier
analyses and fluid-based GHDM device simulator for saturation drain current
estimation.
By using the FB-MC model

as physical reference it could bedemonstrated that the surface II effect is an artifact that appears only when
MOS substrate currents are described with II models which are not predictive,
because their physical base is not sufficiently sound . In addition, it waspossible to refute the various explanations given for surface II in the literature
by investigating them with the FB-MC model. Besides, this suggests thattoday's understanding of electron II is fundamental enough for predictive
device simulation .

98

Chapter 7

Physics-Based MOSFET Design

7.1 Introduction
As the microfabrication technology has brought the quarter to subquartermicron era, MOSFET performance in CMOS technology has caught up withthat of silicon BJT from the viewpoint of cutoff frequency or basic inverter
delay. This is mainly attributed to the deep submicron channel length that isreached around I 00 nm. To realize high-speed ULSI as a system-on-a-chip,higher driving capability for loaded capacitances, especially for wiring, andlower power dissipation for practical cooling instruments and/or longer
battery operation for mobile computing are strongly required. To this endlarger transconductance or higher saturation drain current should be realized
at lower supply voltage for the modern CMOS technology, that directly
demands smaller process margins. Moreover, as the semiconductor industry
matures, huge investment for a new fabrication line with a larger wafer
diameter is becoming a high-risk-taking burden. Therefore, the systematic
MOSFET design for the next generation CMOS technology in a costcompetitive way is one of the most important concerns that the industry isfacing.
Based on rnverse modeling and physically accurate device simulators
using particle- and fluid-based models, we can design MOSFETs for the next
generationtosatisfyrequireddeviceelectrical

specifications.

Deepsubmicron channel length with larger drain current accompanies higher
tangential field that directly causes hot carrier-induced problems such as thedevice performance degradation even at lower supply voltage. Hence, thereliability edge for the highest driving capability should be accurately
detected to maximize the break-even point for performance/lifetime tradeoff.
For this purpose the full-band Monte Carlo (FB-MC) device simulation isinevitable, and to predict the saturation drain current with reasonable CPU
time, the generalized hydrodynamic model (GHDM)-based simulation is also
unavoidable. In this chapter, some examples for hot carrier analyses andsaturation drain current design for subquarter micron MOSFETs aredescribed .

99

7.2 Hot Carrier Effects of nMOSFET
By usmg the FB-MC device simulator, not only observable substratecurrents but also unobservable hot carrier distributions or other physicalquantities can be analyzed. Figures 7 .1 and 7 .2 show the hot electron and hothole distributions for a 0.16- µ m-metallurgical-channel-length nMOSFET atthe supply voltage of 2.5V. Hot electrons are mainly distributed just insidethe drain junction beneath the gate electrode. This means the hot electron
damages mostly occur inside the drain junction under the gate electrode. To
increase the saturation drain current, instead of conventional LDD (lightly
doped drain), highly doped source/drain extension structure is adapted in thequarter micron CMOS technology. As shown in Fig. 5.10 derived by the
inverse modeling technique , the surface impurity concentration approaches
almost to 1 X 10 20 /cm3 • Therefore, the electric field at the vicinity of the drainjunction is no longer reduced unlike the case of an older LDD structure. On
the other hand, not many hot electrons are distributed under the sidewall
spacer outside the gate electrode. This suggests that typical degradation
mechanism caused by the LDD structure does not occur in the case of thesource/drain extension structure. Moreover, we can find broad distribution of
hot holes in the middle of the channel. As it is known that the activationenergy of hole to produce interface state is much lower than that of electron,
these rather warm holes may play an important role for device performancedegradation. Figure 7 .3 shows the impact ionization (II) generation rate
distribution caused by (a) channel electron and (b) secondary hole. Although
the amount of hot holes is smaller than that of hot electrons, they are mainly
located in the middle of the channel. If there might be increase of interface
state at this portion, surface-scattering-induced mobility degradation may
cause drain current decrease.
In Fig. 7.4 the currents of electrons and holes with certain energies

hitting the Si/Si02 -interface of the 0.16- µ m- and 0.18- µ m-channel-lengthnMOSFETs are shown [95]. The bias conditions are the ones of maximum
stress in the allowed bias range (Vgate = 1.5V and Vdrain = 2.75V). The shift
in the distributions for the 0.18- µ m device towards the drain (the poly-gateedge is at y = 0.11 µ m) reflects the increase in effective channel length
because it is made by ten times lower source/drain extension implant dose100compared to the 0.16- µ m device. The lower peak values of the particle
currents due to the field reduction are also caused by the lower doping
concentration in the source/drain extension of 0.18- µ m device. The decreaseis the strongest for the high energetic electrons, which are thought to play a
crucial rule in the hot carrier degradation process. In addition to this effect,
hot and warm holes are increased for the 0.16- µ m device with the higher
source/drain

extension implant

dose.

The

interfacestate

generation

mechanism caused by these holes should be investigated in future.
E=O.SeV

E=l.OeV

-0.05

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0.00

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E=l.SeV

E=2.0eV
-0.05

-0.05
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0.10
0.15
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14.0
111 10135• 10• 1013.0•0.30-0.12 -0.06 0.00 0.06 0.12 0.18 0.24

0.24

Fig. 7. I Electron distribution in a 0.16 µ m-nMOSFET at different energy level.
(Vd=2.5V, Vg=l .5V, axes unit:µ m, contour line unit: cm·3 , dashed line denotes pn-junction)101E=0.5eV

E=l.OeV
-0.05

-0.05
• 1015.S
1015.01014.S
1014.01013.S
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0.10
0.15
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E-1.5eV

E=2.0eV

-0.05
0.00
0.05
0.10
0.15
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--0.05• 1015.5• 1015.0
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b 10 ".., 1012.S• 1012.0• 1011.S• 1011.0

0.00

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0.25

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13 0illi 10 •- 1012.s• 1012.0• 1011.5• 1011.0

0.05
O.JO

0.15
0.20

•

0.30

-0.12 -0.06 0.00 0.06 0.12

-0. 12 -0.06 0.00 0.06 0.12 0.18 0.24

0.18 0.24

Fig. 7.2 Hole distribution in a 0. 16 µ. m-nMOSFET at different energy level. (Vd=2.5V ,Vg=1 .5V , axes unit: µ. m, contour line unit: cm·3, dashed line denotes po-junction)102

-0.050.00- 1027.2' 1026.4
1025.61024.81024.01023.21022.4- 1021.6• 1020.8- 1020.0

0.05
0.10

(a)
0.15
0.20

-

0.25
0.30
-0.12 -0.06

0.00

0.06

0.12

0.18

0.24

-0.05
0.00

- 1027.2
1026.41025.61024.81024.01023.21022.4- 1021.6- 1020.8- 1020.0

0.05

(b)

0.10
0.15
0.20

0.30
-0.12 -0.06

0.00

0.06

0.12

0.18

0.24

Fig. 7.3 II generation rate caused by (a) electron and (b) hole. (Vd=2.5V, Vg=l.SV, axes
unit:µ m, contour line unit : s· 1cm· 3 , dashed line denotes po-junction)

103

N

,...-,
.-..

E

(.)

>Q)

5

10

3

10

-~

10

x

10-1

..........,
:::J

1

'+=
Q)

I

1
I

-

(.)

10-

+='
:a...
ctS
0..

10-5

...

' ... ''' ' ''I '' . ... ... ...
'

3

I

0.000

.0500

.1 0000.150

Y [µm]
Fig. 7 .4 Currents of electrons and holes with certain energies hitting the Si/Si0 2
interface for the 0.18 µ m- (dashed line) and 0.16 µ m- (solid line) nMOSFETs.

7.3 Physics-Based MOSFET Design

To extract the highest performance of MOSFETs, not only hot carrier
effect, but also short channel effects must be taken into account. The
optimization of threshold voltage (Vth) roll-off is the most important topic

among the short channel effects because the process margin to keep the Vthroll-off small enough directly restricts CMOS circuit performance. To
increase the saturation drain current with less threshold voltage roll-off, socalled channel engineering should be considered. There are roughly two
approaches for the channel engineering, or one is the steep-retrograde channel
profile and the other is the higher peak concentration profile at the channel
surface as shown in Fig. 5.6. The advantage of the former is discussed as in[ 139], but this profile is not always suitable to prevent the short channel
104effect or the Vth roll-off. By usmg GHDM implemented in GALENE-III,
simulations are performed to clarify which approach is suitable for a 0.13- µm CMOS technology.

0.8~DeviceA(a)-o- DeviceB~

e 0.15 - - - - - - - - - - - ! . Device ctl-.

-~ · DeviceD

:1.

<e

0.1

..

...... ......

. . . . ·e:.... . . . [).
. . . x..

'-"g 0.65•. .

......

... ...

·t:,. .......... 0-~.... x

0.6
0.1

0.11

0.12

0.13

0.14 0.15

0.16

lpoly(µm)
0.15-o- Device A-o- Device B· -er · Device C
.-..
6. •
1-----=----"""""'"-~ · Device D..._, 0.1
(b)

>

...

.c

o._

.. ..

.....

--- .*----- ...

<]0.05---....

---a·-----~

0
0.1

0.11

0.12

0.13

0.14

0.15

0.16

Lpoly (µ m)
Fig. 7 .5 Simulated (a) Ion and (b) D. Vth versus poly-gate length characteristics for fourkinds of nMOSFET. (A: surface peak channel with source/drain extension xj=0.05 µ m,
B: surface peak channel with source/drain extension x1=0.03 µ m, C: steep retrograde
channel with source/drain extension X/=0.05 µ m, D: steep retrograde channel withsource/drain extension x1=0.03 µ m)

105-Figure 7 .5 shows the comparison between these two channel profiles
combined with two kinds of source/drain extension junction depth (x1=0.03
and 0.05 µ m) for (a) the saturation drain current (Ion when each off current islimited to lnA/ µ m) and (b) Vth roll-off (Ll Vth defined as the thresholdvoltage difference when poly-gate length is 10% reduced) as a function of thephysical poly-gate length (Lpoly)[140]. These results clearly show that thesurface peak channel with the shallower source/drain extension junction issuperior to the steep-retrograde channel profile with both deep and shallow
source/drain extension junction from the viewpoint of higher drain current
with less Vth roll-off. It is because the surface peak channel profile canachieve higher pinch-off voltage that directly brings higher driving current,
and the shallower source/drain extension improves the Vth roll-off. Moreover,in the saturation regime, impurity scattering is no longer dominant limiting
factor for drain current even in the higher channel concentration at the surface
although one of the reasons to use the steep retrograde channel profile is to
avoid the impurity scattering [139]. From this result, we can understand theimportance to realize shallower source/drain extension junction compared tothe manipulation of channel doping profile.
7 .4 Conclusion

By using the physically precise particle-based and fluid-based device
simulators, the next generation MOSFET structure has been analyzed. The
tradeoff between the device performance and hot carrier problems or shortchannel effects are quantitatively approached and solved to clarify the costcompetitive MOSFET development direction for the next generation CMOS
technology , and the importance of shallower source/drain extension junction
has been pointed out.

106Chapter 8

Conclusion

8.1 Summary
The development and advanced physics-based design of high-speed
silicon devices from BJT to CMOS have been described. In the 1980s, the BJT
played the major role in the high-speed field because of its thin base width
combined with sophisticated self-aligned device structures without dependingon tight lithographic design rules. Especially, the ECL circuit was the mostsuitable for high-speed operation because of its non-saturating BJT operation.
However, its larger power dissipation was the most serious limiting factor forlarger integration on a chip . Moreover, the circuit performance was no longer
limited by a basic gate delay, but loaded one in the end of the 1980s. At the
beginning of the 1990s the transition from BJT to CMOS occurred in thehigh-speed device field . MOSFET performance in CMOS technology caught
up with that of BJT by employing up-to-date micro fabrication technology.
Now the CMOS is the dominant high-speed and ultra large scale integration
device.
For high-speed CMOS devices , the device design methodology not only
based on inverse modeling to extract device structures consistent with all
kinds of electrical measurement results but also based on simulations bygeneralized hydrodynamic model and full-band Monte Carlo model has been
described. The background and concept of these approaches have also been
discussed and their necessity has been clarified . Moreover, hot carriermodeling has been investigated by employing full-band Monte Carlo device
simulation. Also , has been clarified the fact there is no experimental evidence
for the difference between the surface and bulk impact ionization in silicon.
The difference was only caused by an unsound application of local fieldmodel and just was an artifact.
Finally, by using these sophisticated models the saturation drain current
as well as hot carrier effects of subquarter micron MOSFETs have been
analyzed. MOSFET design strategy for the 0 . 1- µ m regime has been shown,and the importance of shallow junction for source/drain extension regions has
been made clear.

107-8.2 Future Work
Today ' s most advanced microfabrication technology has brought us deep
submicron era, and theoretically system-on-a-chip may be achievable.
However, the CMOS technology has begun to suffer from the same problems
as those silicon BJT once faced, or the larger power dissipation and by far
larger loaded gate delay than basic one. These problems affect more severe
crises in circuit and/or system design domain , but from the device technology
point of view, there are still several concerns which must be resolved . Toward
the sub-0. 1 µ m CMOS technology, the following topics shou ld be surveyed
and made clear.
a) The self-consistent solution system for the BTE, Poisson and Schroedinger
equations should be implemented, at least, in a two-dimensional device
simulator which is feasib le as an engineering tool to more accurately
comprehend carrier transport phenomena in the inversion layer. The nonequ ilibrium phenomena such as velocity overshoot or quasi-ballistic carriertransport may affect the drain current characteristics of sub-0.1 µ m
MOSFETs. To extract the enough driving capability with lower supply
voltage, accurate modeling of carrier transport in the inversion layer forhigh tangential field regime is strongly required .
b) The limit of the miniaturization of MOSFET must be surveyed from theviewpoint of on-current and off-current ratio to keep enough circuit
operation margin for CMOS techno logy. At the same time, the optimum
supply voltage and threshold voltage should be clarified for sub-0. 1 µ m
MOSFETs if they are useful for practical application. In the case of sub -0.1
µ m MOSFETs the short channel effect especially caused by drain-induced

barrier lowering becomes the dominant limiting factor. The device design
must solve the problem with enough process lat itude for practicalproduction circumstance in a cost competitive way.
c) Hole transportmechanism should be investigated by experimentallyconsistent physical model to realize predictive device simulation for
pMOSFETs. The valance band of silicon is more comp licated than the
conduction band. Accurate scattering models should be developed toexpress the hole transport in pMOSFETs.
d) Carrier and discrete-impurity-ion scattering model should be developed108and implemented in the above-mentioned device simulation program toevaluate the fluctuation of channel-dopant-ion' s position. The channel
doping of the sub-0.1 µ m MOSFETs is strongly related to the abovementioned topic b) . To reveal the channel structure avoiding the on-off
current ratio problem, the influence of dopant-ion locations should be
investigated whether an undoped channel is superior to a doped channel,
and if so, what kind of device structure should be employed for the sub-0. 1µ m MOSFETs including sophisticated device structures such as double-

gated SOL
These research topics will reveal the future direction of the semiconductor
industry based on CMOS technology and what will be achievable in the 21st
century.

109

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94. N. Khalil and J. Faricelli, " Inverse Modeling Profile Determinations: Implementation
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95. C. Jungemann, S. Yamaguchi and H. Goto, "Accurate Prediction of Hot-carrier Effects
for a Deep-Sub-µ m CMOS Technology Based on Inverse Modeling and Full Band
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105. C. S. Rafferty, H.-H. Vuong, S. A. Eshraghi, M. D. Giles, M. R Pinto and S. J.

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106. C. Jungemann, S. Yamaguchi and H. Goto, "On the Accuracy and Efficiency of
Substrate Current Calculation for Sub-µ m n-MOSFET's," IEEE Electron Device Lett.
vol.17 pp.464-466, 1996.
107. C. Jungemann, B. Meinerzhagen, S. Decker, S. Keith, S. Yamaguchi and H. Goto, "Is

Physically Sound and Predictive Modeling of NMOS Substrate Current Possible ?,"Solid-State Electron. vol.42 pp.647-655, 1998.
108. C. Jungemann, S. Yamaguchi and H. Goto, "Is there Experimental Evidence for a
Difference between Surface and Bulk Impact Ionization in Silicon?," IEEE IEDM Tech.
Dig., pp.383-386, 1996.
109. W. Haensch, "The Drift Diffusion Equation and Its Application to MOSFET
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118

112. C. Jungemann, S. Yamaguchi and H. Goto, "Efficient Full Band Monte Carlo Hot
Carrier Simulation for Silicon Devices," Proc. of European Solid-State Device Research
Conf. pp.821-824, 1996.
113. M. V. Fischetti and SE. Laux, "Monte Carlo Simulation of Electron Transport in Si:
The First 20 Years," Proc. of European Solid State Device Research Conf. pp.81 3-820,
1996.
114. C. Jungemann, S. Decker, R. Thoma, W. L. Engl and H. Goto, "Phase Space Multiple
Refresh: a Versatile Statistical Enhancement Method for Monte Carlo Simulation," Proc.
of Int. Conf on Simulation of Semiconductor Processes and Devices, pp.65-66, 1996.
115. C. Jungemann, S. Decker, R. Thoma, W.-L. Engl and H. Goto, ''Phase Space Multiple
Refresh: A General Purpose Statistical Enhancement Technique for Monte Carlo Device
Simulation," IEEE J. Techno. Comp. Aided Design, (2), 1997.
(http://www.ieee.org/joumal/tcad/accepted/jungemann-jan97/)116. C. Jungemann, S. Yamaguchi and H. Goto, "Convergence Estimation for Stationary
Ensemble Monte Carlo Simulations," Proc. of Int. Conf. on Simulation of
Semiconductor Processes and Devices, 209-212, 1997.
117. C. Jungemann, S. Yamaguchi and H. Goto, "Convergence Estimation for Stationary
Ensemble Monte Carlo Simulations," IEEE J. Techno. Comp. Aided Design, (IO), 1998.
(http://www.ieee.org/journal/tcad/accepted/jungemann-jan98/)
118. T. Kunikiyo, M. Takenaka, Y Kamakura, M. Yamaji, H. Mizuno, M. Morifuji, K.
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119. C. Jacoboni and L. Reggiani, "The Monte Carlo method for the solution of chargetransport in semiconductors with application to covalent materials," Rev. Mod. Phys.,vol. 55, pp. 645-705, 1983.
120. C. Jungemann, S. Keith, B. Meinerzhagen, and W. L. Engl, "On the influence of band
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129. S. E. Laux and M. Fischetti, "Transport Models for Advanced Device Simulation Truth or Consequence?," IEEE BCTM Tech. Dig., pp.27-34, 1995.
130. W. L. Engl, Private communication.
131. H. Kanata, C. Jungemann and S. Satoh, "Parameter Extraction of Hydrodynamic
Model by Using Fullband Monte Carlo Simulator," Tech. Rep. IEICE VLD97-74,
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138. B. Meinerzhagen, C. Jungemann, S. Decker, S. Keith, S. Yamaguchi and H. Goto,"Predictive and Efficient Modeling of Substrate Currents in n-channel MOSTransistors," Proc. of International Symposium on VLSI Technology, Systems andApplications, pp.232-235, 1997.
139. Y. Taur, D. A Buchanan, W. Chen, D. J. Frank, K. E. Ismai~ S.-H. Lo, G A Sai-

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121

List of Papers
1. Major Journal Papers
1.

H. Goto and K. lnayoshi, "Trench Isolation Schemes for Bipolar Devices - Benefits
and Limiting Aspects," Electronics and Photonics, vol.27, pp.61-77, 1988.

2.

H. Goto, "Future Bipolar Device Structures (invited)," Journal de Physique,
Colloque C4, supplement au n°9, Tome 49, pp.471-480, septernbre 1988.

3.

H. Goto, Y. Nagase, T. Takada, A. Tahara and Y. Momma, "Analysis of HighlyDoped-Collector Transistors by Using Two-Dimensional Process/Device Simulationand its Application of ECL Circuits," IEEE Trans. Electron Devices, vol.38, no.8,
pp.1840-1844' 1991.

4. C. Jungemann, B. Meinerzhagen, S. Decker, S. Keith, S. Yamaguchi and B. Goto, "lsPhysically Sound and Predictive Modeling ofNMOS Substrate Currents Possible?,"Solid-State Electron., vol.42, no.4, pp.647-655, 1998.
5.

B. Goto, S. Yamaguchi and C. Jungemann, "Inverse Modeling as a Basis for
Predictive Device Simulation of Deep Sub-micron Metal-Oxide-Semiconductor Field
Effect Transistors," Jpn. J. Appl. Phys., vol.37, Part 1, no. I 0, pp. 5437-5443, 1998.

2. Major International Conference Papers
1.

H. Goto, T. Takada, R. Abe, Y. Kawabe, K. Oarni and M. Tanaka, "An Isolation
Teclmology for High Performance Bipolar Memories -- IOP-II," IEEE IEDM Tech.
Dig., pp.58-61 , 1982.

2.

K. Toyoda, M. Tanaka, H. Isogai, C. Olmo, Y. Kawabe and H. Goto, "A 15ns 16Kb
ECL RAM with a PNP Load Cell," IEEE ISSCC Tech. Dig., pp. l 08-109, 1983.

3.

H. Goto, T. Takada, K. Nawata and Y. Kanai, "A New Isolation Technology for
Bipolar VLSI Logic Circuits (IOP-L)," Dig. of Tech. Papers, Symposium on VLSITechnology, pp.42-43, 1985.

4.

H. Goto and K. Inayoshi, "Trench Isolation Schemes for Bipolar Devices - Benefits
and Limiting Aspects," Proc. of 17th European Solid-State Device Research
Conference, pp.689-692, 1987.

5.

K. Ueno, H. Goto, E. Sugiyama and H. Tsunoi, "A Sub-40ps ECL Circuit at a
Switching Current of l.28mA," IEEE IEDM Tech. Dig., pp.371-374, 1987.

6.

T. Yamazaki, I. Namura, H. Goto, A. Tahara and T. Ito, "A 11.7 GHz 1/8-Divider
122

using 43 GHz Si High Speed Bipolar Transistor with Photoepitaxy Grown Ultra-Thin
Base," IEEE IEDM Tech. Dig., pp.309-312, 1990.
7.

T. Yamazaki, I. Namura, T. Sugii, H. Goto, A. Tahara and T. Ito, "High-Speed Si
Hetero-bipolar Transistor with a SiC Wide Gap Emitter and an Ultra-Thin Heavily
Doped Photoepitaxy Grown," IEEE BCTM Tech. Dig., pp. 71-74, 1991 .

8.

T. Jzawa, M. Katsube, Y. Yokoyama, K. Hashimoto, E. Kawamura, A. Shimizu, H.
Takagi, F. Inoue, H. Shimizu, K. Furumochi, H. Goto, S. Kawamura, K. Watanabe
and K. Aoyama, "A Novel Embedded SRAM Technology with 10 µ, m 2 full-CMOS
Cells for 0.25 µ m Logic Devices," IEEE IEDM Tech. Dig., pp.941-943, 1994.

9.

C. Jungemann, S. Decker, R. Thoma, W. L. Engl and H . Goto, "Phase Space Multiple

Refresh: a Versatile Statistical Enhancement Method for Monte Carlo Simulation,"
Proc. of Int. Conf. on Simulation of Semiconductor Processes and Devices, pp.65-66,
1996.
10. C. Jungemann, S. Yamaguchi and H. Goto, "Accurate Prediction of Hot-carrier
Effects for a Deep Sub-µ, m CMOS Technology Based on Inverse Modeling and FullBand Monte Carlo Device Simulation," Proc. of Int. Conf. on Simulation of
Semiconductor Processes and Devices, 59-60, 1996.
11. C. Jungemann, S. Yamaguchi and H. Goto, "Efficient Full Band Monte Carlo Hot
Carrier Simulation for Silicon Devices," Proc. of 26th European Solid-State Device
Research Conference, pp.821-824, 1996.
12. C. Jungemann, S. Yamaguchi and H. Goto, "Is There Experimental Evidence for a
Difference between Surface and Bulk Impact Ionization in Silicon," IEEE IEDM Tech.
Dig., pp.383-386, 1996.
13. Y. Takao, Y. Sanbonsugi, K. Watanabe, H. Takatsuka, T. Karasawa, E. Kawamura, K.
Hashimoto, H. Takagi, F. Inoue, H. Shimizu, T. Yamazaki, H. Goto, T. Sugii, M.
Miyajima, K. Watanabe and K. Aoyama, " A 4 µ, m2 Full-CMOS SRAM Cell
Technology for 0.2- µ m High-Performance Logic LSis," Dig. of Tech. Papers,
Symposium on VLSI Technology, pp.11-12, 1997.
14. B. Meinerzhagen, C. Jungemann, S. Decker, S. Keith, S. Yamaguchi and H. Goto,"Predictive and Efficient Modeling of Substrate Currents in n-channel MOSTransistors," Proc. of International Symposium on VLSI Technology, Systems andApplications, pp.232-235, 1997.
15. C. Jungemann, S. Yamaguchi and H. Goto, "Convergence Estimation for Stationary
Ensemble Monte Carlo Simulations," Proc. of Int. Con£ on Simulation of
Semiconductor Processes and Devices, pp.209-212, 1997.

123

..

--~~~~~----------------------------~~~~~~~~~~---

16. C. Jungemann, S. Yamaguchi and H. Goto, "Investigation of the Influence of Impact
Ionization Feedback on the Spatial Distribution of Hot Carriers in an NMOSFET,"
Proc. of 27th European Solid-State Device Research Conference, pp.336-339, 1997.
17. S. Yamaguchi and H. Goto, "Inverse Modeling - A Promising Approach to Know
What is Made and What should be Made," Proc. of Asia and South Pacific Design
Automation Conference, pp.117-121, 1998.
18. T. Tanaka, Se. Yamaguchi, Sa. Yamaguchi, K. Sukegawa and H. Goto, "Investigation
to Suppress Hot Carrier Effect in Pocket{Implanted nMOSFET by Full Band Monte
Carlo Simulation," Ext. Abst. of 6th Int. Workshop on Computational Electronics,
pp.214-217, 1998.
3. Book Chapter
1.

H. Goto, "High-Speed Silicon Bipolar !Cs," in "High-Speed Digital IC Technologies"edited by M. Rocchi, Artech House Inc., Ch.3, 1990.
4. Related Papers
1. K. Toyoda, M. Tanaka, H. Isogai, C. Ohno, Y Kawabe and H. Goto, "A High Speed
16Kbit ECL RAM," IEEE Journal of Solid-State Circuits vol.SC-18, no.5, pp.509-514,
1983.
2.

Y Nagase, K. Hashimoto, H. Goto, T. Nakadai, T. Nawata and T. Takada, "Analysis

of Bipolar Transistor's f-rlc Characteristics by Two Dimensional DC and AC Device
Simulation," Proc. ofNUPAD-II, Paper no.NUPAD-156, 1988.
3.

Y. Nagase, H. Goto and T. Takada, "Analysis of Pedestal-Collector Transistors by 2-D
Process and Device Simulation," Proc. of 7th VLSI Process/Device ModelingWorkshop, pp.40-41 , 1990.

4.

T. Sugii, T. Yamazaki, Y. Arimoto, T. Ito, I. Namura, H. Goto and A. Tahara, "SiCx:F
Hetero-Emitter and Epitaxial-Base Bipolar Transistors," Proc. of 4th Int. Conf.,
Amorphous and Crystalline Silicon Carbide N, pp.314-321, 1991.

5.

T. Sugii, T. Yamazaki, Y. Arimoto, T. Ito, Y Furumura, I. Namura, H. Goto and A.
Tahara, "SiC Growth and Its Application to High-Speed Si-HBTs," Proc. of 22nd
European Solid-State Device Research Conference, pp.335-342, 1992.

6.

H. Takatsuka, H. Sato, T. Izawa, T. Hisaeda, H. Goto and S. Kawamura, "Influence ofTilted High-Energy Ion-Implantation upon Scaled CMOS Structure," IEEE ICMTS

124

Tech. Dig., pp.247-251 , 1995.
7.

C. Jungernann, S. Yamaguchi and H. Goto, "On the Accuracy and Efficiency of
Substrate Current Calculations for Sub-µ. m n-MOSFET's," IEEE Electron Device
Lett., vol.17, no. I 0, pp.464-466, 1996.

8.

C. Jungemann, S. Decker, R Thoma, W.-L. Engl and B. Goto, "Phase SpaceMultiple Refresh: A General Purpose Statistical Enhancement Technique for Monte
Carlo Device Simulation," IEEE J. Techno. Comp. Aided Design, (2), 1997.
(http://www.ieee.oqy'joumal/tcad/accepted/jungemann-jan97/)

9.

N. Sugiyasu, K. Suzuki, S. Kojima, Y. Ohyama and H. Goto, "A New Practical
Approach to Implement a Transient Enhanced Diffusion Model into an FEM-based 2D Process Simulator," Materials Research Society Fall Meeting, Symposium Paper
no.Q-1.6, pp.370-371, 1997, also in "Semiconductor Process and Device Performance
Modeling," MRS Symposium Proc., vol.490, 1998.

I0. C. Jungemann, S. Yamaguchi and B . Goto, "Convergence Estimation for Stationary
Ensemble Monte Carlo Simulations," IEEE J. Techno. Comp. Aided Design, (10),1998. (http://www.ieee.org/journal/tcad/accepted/jungernann-jan98/)125