FEATURESFUNCTIONAL BLOCK DIAGRAM

isoPower integrated, isolated dc-to-dc converter
Regulated 3.15 V to 5.25 V output
Up to 150 mW output power
High common-mode transient immunity: >25 kV/µs
iCoupler integrated I2C digital isolator
Bidirectional I2C communication
3.0 V to 5.5 V supply/logic levels
Open-drain interfaces
Suitable for hot swap applications
30 mA current sink capability
1000 kHz maximum frequency
20-lead SSOP package with 5.3 mm creepage
High temperature operation: 105°C
Safety and regulatory approvals
UL recognition
2500 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice 5A
VDE Certificate of Conformity (pending)
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 560 V peak

APPLICATIONSIsolated I2C, SMBus, and PMBus interfaces
Multilevel I2C interfaces
Central office switching
Telecommunication and data communication equipment−48 V distributed power systems−48 V power supply modules
Networking
Disk arrays

GENERAL DESCRIPTION
Based on the iCoupler® and isoPower® chip scale transformer
technology, the ADM32601 is a hot swappable digital and power
isolator with two nonlatching, bidirectional communication
channels, supporting a complete isolated I2C interface, and an
integrated isolated dc-to-dc converter, supporting up to
150 mW of isolated power conversion.
iCoupler is a chip scale transformer technology with functional,
performance, size, and power consumption advantages ascompared to optocouplers. The bidirectional I2C channels
eliminate the need for splitting I2C signals into separate transmit
and receive signals for use with standalone optocouplers.

1

ADM3260
GNDP

DECODEENCODEGNDISOSCL2ENCODEDECODESCL1

SDA2

DECODEENCODE

SDA1

VDDP

ENCODEDECODEVDDISOGNDP

SIGNAL ISOLATIONGNDISONC

NC
GNDP

POWER ISOLATION

PDIS

PCS

VIN

OSC

GNDISO
VSEL

RECT

REG

VISO
GNDISO

GNDP

11890-001

Data Sheet

Hot Swappable, Dual I2C Isolators with
Integrated DC-to-DC Converter
ADM3260

Figure 1.

Table 1. Power Levels for Isolated Converter
Input Voltage (V)
5.0
5.0
3.3

Output Voltage (V)
5.0
3.3
3.3

Output Power (mW)
150
150
66

Based on the Analog Devices, Inc., isoPower technology, theon-chip isolated dc-to-dc converter provides a regulated, isolated
voltage of 3.15 V to 5.25 V with up to 150 mW of output power(see Figure 1).
With the ADM3260, the iCoupler and isoPower channels, alongwith the I2C transceivers, can be integrated with semiconductor
circuitry, which enables a complete isolated I2C interface andallows the power converter to be implemented in a small form
factor. The ADM3260 is available in 20-lead SSOP package andhas an operating temperature range of −40°C to+105°C.
isoPower uses high frequency switching elements to transfer power
through its transformer. Special care must be taken during printed
circuit board (PCB) layout to meet emissions standards. See the
AN-0971 Application Note for board layout recommendations.

Protected by U.S. Patents 5,952,849; 6,873,065; and 7,075,329. Other patents are pending.

Rev. B

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Technical Support
www.analog.com

ADM3260

Data SheetTABLE OF CONTENTS
Features .............................................................................................. 1

Recommended Operating Conditions .......................................9Applications ....................................................................................... 1

Absolute Maximum Ratings ......................................................... 10

Functional Block Diagram .............................................................. 1

ESD Caution................................................................................ 10

General Description ......................................................................... 1

VISO Voltage Truth Table ......................................................... 10

Revision History ............................................................................... 2

Pin Configuration and Function Descriptions........................... 11

Specifications..................................................................................... 3

Typical Performance Characteristics ........................................... 12

Electrical Characteristics—5 V Primary Input Supply/5 V
Secondary Isolated Supply........................................................... 3

Test Condition ................................................................................ 14

Electrical Characteristics—5 V Primary Input Supply/3.3 V
Secondary Isolated Supply........................................................... 3

Functional Description .............................................................. 15

Electrical Characteristics—3.3 V Primary Input Supply/3.3 V
Secondary Isolated Supply........................................................... 4

Typical Application Diagram .................................................... 16

DC-to-DC Converter Characteristics ....................................... 4
Digital Isolator DC Specifications .............................................. 5
Digital Isolator AC Specifications .............................................. 5
Package Characteristics ............................................................... 6
Regulatory Approvals................................................................... 7
Insulation and Safety Related Specifications ............................ 7
DIN V VDE V 0884-10 (VDE V 0884-10) Insulation
Characteristics .............................................................................. 8

Applications Information .............................................................. 15
Digital Isolator Startup .............................................................. 16
PCB Layout ................................................................................. 16
Thermal Analysis ....................................................................... 17
EMI Considerations ................................................................... 17
Insulation Lifetime ..................................................................... 17
Applications Example .................................................................... 18
Outline Dimensions ....................................................................... 19
Ordering Guide .......................................................................... 19

REVISION HISTORY
4/15—Rev. A to Rev. B
Changes to Features Section............................................................ 1
Changes to Table 9 and Table 10..................................................... 7
Changes to Functional Description Section ............................... 15
6/14—Rev. 0 to Rev. A
Changes to Pin 8, Table 16............................................................. 11
12/13—Revision 0: Initial Version

Rev. B | Page 2 of 19

Data Sheet

ADM3260

SPECIFICATIONSELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/5 V SECONDARY ISOLATED SUPPLY
All typical specifications are at TA = 25°C, VIN = VISO = 5 V, VSEL resistor network RBOTTOM = 10 kΩ, RTOP = 30.9 kΩ. Minimum/maximum
specifications apply over the entire recommended operation range which is 4.5 V ≤ VIN, VISO ≤ 5.5 V, and −40°C ≤ TA ≤ +105°C, unlessotherwise noted. Switching specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted.
Table 2.
Parameter
DC-TO-DC CONVERTER SUPPLY
Setpoint
Thermal CoefficientLine Regulation
Load Regulation
Output Ripple
Output Noise
Switching Frequency
Pulse-Width Modulation Frequency
Output Current
Efficiency at IISO (MAX)
IVIN, No VISO Load
IVIN, Full VISO Load
Thermal Shutdown
Shutdown Temperature
Thermal Hysteresis

Symbol

Min

Typ

VISO
VISO (TC)
VISO (LINE)
VISO (LOAD)
VISO (RIP)

5
−44
20
1.3
75

VISO (NOISE)
fOSC
fPWM
IISO (MAX)

200
125
600

Max

3

30

IVIN (Q)
IVIN (MAX)

29
6.8
104

TSHUTDOWN
THYST

154
10

12

Unit

Test Conditions/Comments

V
µV/°C
mV/V
%
mV p-pIISO = 15 mA, RBOTTOM = 10 kΩ, RTOP = 30.9 kΩ

mV p-p
MHz
kHz
mA
%
mA
mA

IISO = 15 mA, VIN = 4.5 V to 5.5 V
IISO = 3 mA to 27 mA
20 MHz bandwidth, COUTPUT_BYPASS = 0.1 µF||10 µF,
IISO = 27 mA
COUTPUT_BYPASS = 0.1 µF||10 µF, IISO = 27 mA

VISO > 4.5 V
IISO = 27 mA°C°C

ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY
All typical specifications are at TA = 25°C, VIN = 5 V, VISO = 3.3 V, VSEL resistor network RBOTTOM = 10 kΩ, RTOP = 16.9 kΩ. Minimum/
maximum specifications apply over the entire recommended operation range, which is 4.5 V ≤ VIN ≤ 5.5 V, 3 V ≤ VISO ≤ 3.6 V, and −40°C ≤TA ≤ +105°C, unless otherwise noted. Switching specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted.
Table 3.
Parameter
DC-TO-DC CONVERTER SUPPLY
Setpoint
Thermal CoefficientLine Regulation
Load Regulation
Output Ripple
Output Noise
Switching Frequency
Pulse-Width Modulation Frequency
Output Current
Efficiency at IISO (MAX)
IVIN, No VISO Load
IVIN, Full VISO Load
Thermal Shutdown
Shutdown Temperature
Thermal Hysteresis

Symbol

Min

Typ

VISO
VISO (TC)
VISO (LINE)
VISO (LOAD)
VISO (RIP)

3.3
−26
20
1.3
50

VISO (NOISE)
fOSC
fPWM
IISO (MAX)

130
125
600

Max

3

30

IVIN (Q)
IVIN (MAX)

24
3.2
85

TSHUTDOWN
THYST

154
10

8

Unit

Test Conditions/Comments

V
µV/°C
mV/V
%
mV p-pIISO = 15 mA, RBOTTOM = 10 kΩ, RTOP = 16.9 kΩ

mV p-p
MHz
kHz
mA
%
mA
mA
°C
°C

Rev. B | Page 3 of 19

IISO = 15 mA, VIN = 4.5 V to 5.5 V
IISO = 3 mA to 27 mA
20 MHz bandwidth, COUTPUT_BYPASS = 0.1 µF||10 µF,
IISO = 27 mA
COUTPUT_BYPASS = 0.1 µF||10 µF, IISO = 27 mA

3 V < VISO< 3.6 V
IISO = 27 mA

ADM3260

Data Sheet

ELECTRICAL CHARACTERISTICS—3.3 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY
All typical specifications are at TA = 25°C, VIN = VISO = 3.3 V, VSEL resistor network RBOTTOM = 10 kΩ, RTOP = 16.9 kΩ. Minimum/maximum
specifications apply over the entire recommended operation range which is 3.0 V ≤ VIN, VISO ≤ 3.6 V, and −40°C ≤ TA ≤ +105°C, unlessotherwise noted. Switching specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted.
Table 4.
Parameter
DC-TO-DC CONVERTER SUPPLY
Setpoint
Thermal CoefficientLine Regulation
Load Regulation
Output Ripple
Output Noise
Switching Frequency
Pulse-Width Modulation Frequency
Output Current
Efficiency at IISO (MAX)
IVIN, No VISO Load
IVIN, Full VISO Load
Thermal Shutdown
Shutdown Temperature
Thermal Hysteresis

Symbol

Min

Typ

VISO
VISO (TC)
VISO (LINE)
VISO (LOAD)
VISO (RIP)

3.3
−26
20
1.3
50

VISO (NOISE)
fOSC
fPWM
IISO (MAX)

130
125
600

Max

3

20

IVIN (Q)
IVIN (MAX)

27
3.3
77

TSHUTDOWN
THYST

154
10

10.5

Unit

Test Conditions/Comments

V
µV/°C
mV/V
%
mV p-pIISO = 10 mA, RBOTTOM = 10 kΩ, RTOP = 16.9 kΩ
IISO = 20 mA
IISO = 10 mA, VIN = 3.0 V to 3.6 V
IISO = 2 mA to 18 mA
20 MHz bandwidth, COUTPUT_BYPASS = 0.1 µF||10 µF,
IISO = 18 mA
COUTPUT_BYPASS = 0.1 µF||10 µF, IISO = 18 mAmV p-p
MHz
kHz
mA
%
mA
mA

3.6 V > VISO > 3 V
IISO = 18 mA°C°C

DC-TO-DC CONVERTER CHARACTERISTICS
All typical specifications are at TA = 25°C. Minimum/maximum specifications apply over the entire recommended operation range unlessotherwise noted. Switching specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted.
Table 5.
Parameter
UNDERVOLTAGE LOCKOUT
Positive Going Threshold
Negative Going Threshold
PDIS PIN
Input Threshold
Logic High
Logic Low
Input Current

Symbol

Min

Typ

VUV+
VUV−

VIH
VIL
IPDIS

Max

2.7
2.4

+0.01

Rev. B | Page 4 of 19

Test Conditions/Comments
VIN, VISO supply

VV

0.7 VIN−10Unit

0.3 VIN
+10

V
V
µA

0 V ≤ VPDIS ≤ VIN

Data Sheet

ADM3260

DIGITAL ISOLATOR DC SPECIFICATIONS
All minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted. All typical specifications are
at TA = 25°C, VDDISO = 3.3 V or 5 V, and VDDP = 3.3 V or 5 V, unless otherwise noted. All voltages are relative to their respective ground.
Table 6.
Parameter
I2C SIGNAL ISOLATION BLOCK
Input Supply Current
Side 1 (5 V)
Side 2 (5 V)
Side 1 (3.3 V)
Side 2 (3.3 V)
LEAKAGE CURRENTS

SymbolIDDISO1IDDP1IDDISO2
IDDP2
ISDA1, ISDA2, ISCL1, ISCL2

SIDE 1 LOGIC LEVELS
Logic Input Threshold 1
Logic Low Output Voltages

VSDA1T, VSCL1T
VSDA1OL, VSCL1OL

Input/Output Logic Low Level Difference 2
SIDE 2 LOGIC LEVELS
Input Voltage
Logic Low
Logic High
Output Voltage
Logic Low
1
2Min

ΔVSDA1, ΔVSCL1

500
600
600
50

VSDA2IL, VSCL2IL
VSDA2IH, VSCL2IH

0.7 VDDP

Typ

Max

Unit

Test Conditions/Comments

2.8
2.7
1.9
1.7
0.01

5.0
5.0
3.0
3.0
10

mA
mA
mA
mA
µA

VDDISO = 5 V
VDDP = 5 V
VDDISO = 3.3 V
VDDP = 3.3 V
VSDA1 = VDDISO, VSDA2 = VDDP,VSCL1 = VDDISO, VSCL2 = VDDP

700
900
850

mV
mV
mV
mV

0.3 VDDP

V
V

400

mV

VSDA2OL, VSCL2OL

ISDA1 = ISCL1 = 3.0 mA
ISDA1 = ISCL1 = 0.5 mA

ISDA2 = ISCL2 = 30 mA

VIL < 0.5 V, VIH > 0.7 V.
ΔVSDA1 = VSDA1OL – VSDA1T, ΔVSCL1 = VSCL1OL – VSCL1T. This is the minimum difference between the output logic low level and the input logic threshold within a given
component. This ensures that there is no possibility of the device latching up the bus to which it is connected.

DIGITAL ISOLATOR AC SPECIFICATIONS
All minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted. All typical specifications
are at TA = 25°C, VDDISO = 3.3 V or 5 V, and VDDP = 3.3 V or 5 V, unless otherwise noted. Refer to Figure 17. All voltages are relative totheir respective ground.
Table 7.
Parameter
MAXIMUM FREQUENCYOUTPUT FALL TIME
5 V Operation

Symbol

Typ

Max

Unit
kHz

Test Conditions/Comments

4.5 V ≤ VDDISO, VDDP ≤ 5.5 V, CL1 = 40 pF,
R1 = 1.6 kΩ, CL2 = 400 pF, R2 = 180 Ω

Side 1 Output (0.9 VDDISO to 0.9 V)
Side 2 Output (0.9 VDDP to 0.1 VDDP)
3 V Operation

tf1
tf2

Side 1 Output (0.9 VDDISO to 0.9 V)
Side 2 Output (0.9 VDDP to 0.1 VDDP)PROPAGATION DELAY
5 V Operation

tf1
tf2

Side 1 to Side 2
Rising Edge 1
Falling Edge 2

Min
1000

13
32

26
52

120
120

ns
ns
3.0 V ≤ VDDISO, VDDP ≤ 3.6 V, CL1 = 40 pF,
R1 = 1.0 kΩ, CL2 = 400 pF, R2 = 120 Ω

13
32

32
61

120
120

ns
ns
4.5 ≤ VDDISO, VDDP ≤ 5.5 V, CL1 = CL2 = 0 pF,
R1 = 1.6 kΩ, R2 = 180 Ω

tPLH12
tPHL12

95
162

130
275

Rev. B | Page 5 of 19

nsns

ADM3260
Parameter
Side 2 to Side 1
Rising Edge 3
Falling Edge 4
3 V Operation
Side 1 to Side 2
Rising Edge1
Falling Edge2
Side 2 to Side 1
Rising Edge3
Falling Edge4
PULSE WIDTH DISTORTION
5 V Operation
Side 1 to Side 2, |tPLH12 − tPHL12|
Side 2 to Side 1, |tPLH21 − tPHL21|
3 V Operation
Side 1 to Side 2, |tPLH12 − tPHL12|
Side 2 to Side 1, |tPLH21 − tPHL21|
COMMON-MODE TRANSIENT IMMUNITY 5

Data Sheet
SymbolMin

tPLH21
tPHL21

Typ

Max

Unit

31
85

70
155

ns
ns

Test Conditions/Comments

3.0 V ≤ VDDISO, VDDP ≤ 3.6 V, CL1 = CL2 = 0 pF,
R1 = 1.0 kΩ, R2 = 120 Ω
tPLH12
tPHL12

82
196

125
340

ns
ns

tPLH21
tPHL21

32
110

75
210

ns
ns
4.5 V ≤ VDDISO, VDDP ≤ 5.5 V, CL1 = CL2 = 0 pF,
R1 = 1.6 kΩ, R2 = 180 Ω

PWD12
PWD21

67
54

145
85

ns
ns
3.0 V ≤ VDDISO, VDDP ≤ 3.6 V, CL1 = CL2 = 0 pF,
R1 = 1.0 kΩ, R2 = 120 Ω

PWD12
PWD21
|CMH|, |CML|

114
77
35

25

215
135

ns
ns
kV/µs

tPLH12 propagation delay is measured from the Side 1 input logic threshold to an output value of 0.7 VDDP.
tPHL12 propagation delay is measured from the Side 1 input logic threshold to an output value of 0.4 V.
3tPLH21 propagation delay is measured from the Side 2 input logic threshold to an output value of 0.7 VDDISO.
4
tPHL21 propagation delay is measured from the Side 2 input logic threshold to an output value of 0.9 V.
5|CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDDP. |CML| is the maximum common-mode voltage slew
rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The
transient magnitude is the range over which the common mode is slewed.
1
2

PACKAGE CHARACTERISTICS
Table 8. Thermal and Isolation Characteristics
Parameter
Resistance (Input to Output) 1
Capacitance (Input to Output)1
Input Capacitance 2
IC Junction-to-Ambient Thermal Resistance

Symbol
RI-O
CI-O
CI
θJA

Min

Typ
1012
2.2
4.0
50

Max

Unit
Ω
pF
pF
°C/W

Test Conditions/Comments
f = 1 MHz
Thermocouple located at center of package underside,
test conducted on 4-layer board with thin traces 3

The device is considered a 2-terminal device: Pin 1 through Pin 10 are shorted together; and Pin 11 through Pin 20 are shorted together.
Input capacitance is from any input data pin to ground.
3
See the Thermal Analysis section for thermal model definitions.
12

Rev. B | Page 6 of 19

Data Sheet

ADM3260

REGULATORY APPROVALS
Table 9.
UL 1
Recognized Under 1577 Component
Recognition Program1
Single Protection, 2500 V RMS
Isolation Voltage
File E214100
1
2

CSA
Approved under CSA Component Acceptance
Notice 5A
Basic insulation per CSA 60950-1-03 and IEC 60950-1,
400 V rms (565 V peak) maximum working voltage
File 205078

VDE (Pending) 2
Certified according to DIN V VDE V 0884-10(VDE V 0884-10):2006-122
Reinforced insulation, 560 V peak
File 2471900-4880-0001

In accordance with UL 1577, each ADM3260 is proof tested by applying an insulation test voltage ≥ 3000 V rms for 1 second (current leakage detection limit = 10 µA).
In accordance with DIN V VDE V 0884-10, ADM3260 is proof tested by applying an insulation test voltage ≥1590 V peak for 1 second (partial discharge detection limit =5 pC). The * marking branded on the component designates DIN V VDE V 0884-10 approval.

INSULATION AND SAFETY RELATED SPECIFICATIONS
Table 10. Critical Safety Related Dimensions and Material Properties
Parameter
Rated Dielectric Insulation Voltage
Minimum External Air Gap (Clearance)

Symbol Value
2500
L(I01)
5.1

Minimum External Tracking (Creepage)

L(I02)

Minimum Clearance in the Plane of the Printed
Circuit Board (PCB Clearance)

L(PCB)

Minimum Internal Gap (Internal Clearance)
Tracking Resistance (Comparative Tracking Index)
Isolation Group

CTI

Unit Test Conditions/Comments
V rms 1-minute durationmm
Measured from input terminals to output terminals,
shortest distance through air
5.1
mm
Measured from input terminals to output terminals,
shortest distance path along body
5.5mm
Measured from input terminals to output terminals,
shortest distance through air, line of sight, in the PCB
mounting plane (for information only)
0.017 min mm
Distance through insulation>400
V
DIN IEC 112/VDE 0303, Part 1
II
Material group (DIN VDE 0110, 1/89, Table 1)

Rev. B | Page 7 of 19

ADM3260

Data SheetDIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS
This isolator is suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by theprotective circuits. The asterisk (*) marking on packages denotes DIN V VDE V 0884-10 approval.
Table 11. VDE Characteristics
Description
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms
For Rated Mains Voltage ≤ 300 V rms
For Rated Mains Voltage ≤ 400 V rms
Climatic Classification
Pollution Degree per DIN VDE 0110, Table 1
Maximum Working Insulation Voltage
Input-to-Output Test Voltage, Method b1
Input-to-Output Test Voltage, Method a
After Environmental Tests Subgroup 1
After Input and/or Safety Test Subgroup 2
and Subgroup 3
Highest Allowable Overvoltage
Surge Isolation Voltage
Safety Limiting Values
Case Temperature
Converter Safety Total Dissipated Power
VDDP + VDDISO Current
Insulation Resistance at TS for Isolated Converter

Test Conditions/Comments

VIORM × 1.875 = Vpd(m), 100% production test,
tini = tm = 1 sec, partial discharge < 5 pC
VIORM × 1.5 = Vpd(m), tini = 60 sec, tm = 10 sec,
partial discharge < 5 pC
VIORM × 1.2 = Vpd(m), tini = 60 sec, tm = 10 sec,
partial discharge < 5 pC
VIOSM(TEST) = 10 kV, 1.2 µs rise time, 50 µs, 50% fall time
Maximum value allowed in the event of a
failure (see Figure 2)

VIO = 500 V

Characteristic

Unit

VIORM
Vpd(m)

I to IV
I to IIII to II
40/105/21
2
560
1050

V peakV peakVpd(m)

840

V peakVpd(m)

672

V peak

VIOTM
VIOSM

3535
4000

V peakV peak

TS
IS1
ITMAX
RS

150
2.5
212
>109

°C
W
mA
Ω

350

3.0

300

2.0

1.5

1.0

0
0

50
100
150
AMBIENT TEMPERATURE (°C)

200

Figure 2. Isolated Converter Thermal Derating Curve, Dependence of Safety
Limiting Values on Case Temperature, per DIN V VDE V 0884-10

200
150
100
50
0

11890-002

0.5

250

0

50

100
150
CASE TEMPERATURE (°C)

20011890-003

SAFETY-LIMITING CURRENT (mA)

2.5
SAFE LIMITING POWER (W)SymbolFigure 3. Digital Isolator Thermal Derating Curve, Dependence of SafetyLimiting Values on Case Temperature, per DIN V VDE V 0884-10

Rev. B | Page 8 of 19

Data Sheet

ADM3260RECOMMENDED OPERATING CONDITIONS
Table 12.
Parameter
OPERATING TEMPERATURE 1
ISOLATED CONVERTER
Supply Voltages 2
VIN at VISO Set to Regulate to 3.3 V
VIN at VISO Set to Regulate to 5 V
DIGITAL ISOLATOR
Supply Voltages (VDDISO, VDDP) 3
Input/Output Signal Voltage (VSDA1, VSCL1, VSDA2, VSCL2)
Capacitive LoadSide 1 (CL1)Side 2 (CL2)STATIC OUTPUT LOADINGSide 1 (ISDA1, ISCL1)
Side 2 (ISDA2, ISCL2)
1
2
3

Value
−40°C to +105°C

3.0 V to 5.5 V
4.5 V to 5.5 V
3.0 V to 5.5 V
5.5 V
40 pF
400 pF
0.5 mA to 3 mA
0.5 mA to 30 mA

Operation at 105°C requires reduction of the maximum load current (see Table 13).
Each voltage is relative to its respective ground.
All voltages are relative to their respective ground.

Rev. B | Page 9 of 19

ADM3260

Data Sheet

ABSOLUTE MAXIMUM RATINGSTA = 25°C, unless otherwise noted.
Table 13.
Parameter
Storage Temperature (TST)
Ambient Operating Temperature (TA)
Supply Voltages (VIN, VISO) 1
Supply Voltages (VDDISO, VDDP)1
VISO Supply Current 2
TA = −40°C to +105°C
Digital Isolator Average Output
Current per Pin 3
Side 1 (IO1)
Side 2 (IO2)
Input/Output Voltage
Side 1 (VSDA1, VSCL1)3
Side 2 (VSDA2, VSCL2)3
Input Voltage (PDIS, VSEL)1, 4
Common-Mode Transients 5

Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at theseor any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.

Rating−55°C to +150°C−40°C to +105°C−0.5 V to +7.0 V−0.5 V to +7.0 V
30 mA

ESD CAUTION±18 mA±100 mA−0.5 V to VDDISO + 0.5 V−0.5 V to VDDP + 0.5 V−0.5 V to VIN + 0.5 V−100 kV/µs to +100 kV/µs

All voltages are relative to their respective ground.
VISO provides current for dc and dynamic loads on the VISO input/output
channels. This current must be included when determining the total VISO
supply current.
3
See Figure 3 for maximum rated current values for various temperatures.
4
VCC can be either VIN or VISO depending on the whether the input is on the
primary or secondary side of the device, respectively.
5
Refers to common-mode transients across the insulation barrier. Common-mode
transients exceeding the absolute maximum ratings may cause latch-up or
permanent damage.
1
2

Table 14. Maximum Continuous Working Voltage Supporting 50-Year Minimum Lifetime1
Parameter
AC Voltage
Bipolar Waveform
Unipolar Waveform
DC Voltage|DC Peak Voltage|
1

Maximum

Unit

Applicable Certification

560
560

V peakV peakAll certifications, 50-year operation

560

V peakRefers to the continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more information.

VISO VOLTAGE TRUTH TABLE
Table 15. Truth Table (Positive Logic)
VDDP (V)
5
5
3.3
3.3
5
5
3.3
3.3

VSEL Input
RBOTTOM = 10 kΩ, RTOP = 30.9 kΩ
RBOTTOM = 10 kΩ, RTOP = 30.9 kΩ
RBOTTOM = 10 kΩ, RTOP = 16.9 kΩ
RBOTTOM = 10 kΩ, RTOP = 16.9 kΩ
RBOTTOM = 10 kΩ, RTOP = 16.9 kΩ
RBOTTOM = 10 kΩ, RTOP = 16.9 kΩ
RBOTTOM = 10 kΩ, RTOP = 30.9 kΩ
RBOTTOM = 10 kΩ, RTOP = 30.9 kΩ

PDIS Input
Low
High
Low
High
Low
High
Low
High

VISO Output (V)
5
0
3.3
0
3.3
0
5
0

Rev. B | Page 10 of 19

Notes

Configuration not recommended

Data Sheet

ADM3260

GNDP

1

20

GNDISO

SCL2

2

19

SCL1

SDA2

3

18

SDA1

VDDP

4

17

VDDISO

GNDP

5

16

GNDISO

NC

6

15

NC

GNDP

7

14

GNDISO

PDIS

8

13

VSEL

VIN

9

12

VISO

GNDP 10

11

GNDISOADM3260
TOP VIEW(Not to Scale)11890-017

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN

Figure 4. Pin Configuration

Table 16. Pin Function Descriptions
Pin No.
1, 5, 7 ,10
2
3
4
6, 15
8

Mnemonic
GNDP
SCL2
SDA2
VDDP
NC
PDIS

9
11, 14, 16, 20
12

VIN
GNDISO

13

VSEL

17
18
19

VDDISO
SDA1
SCL1

VISO

Description
Ground Reference for Primary Side. Connect all GNDP pins to the primary ground reference.
Clock Input/Output, Primary Side.
Data Input/Output, Primary Side.
Digital Isolator Primary Supply Input, 3.0 V to 5.5 V.
No Connect. Do not connect to this pin.
Power Disable. When PDIS is tied to VIN, the power supply enters low power standby mode. When PDIS is tied
to GNDP, the power converter is active.
isoPower Converter Primary Supply Input, 3.0 V to 5.5 V.
Ground Reference for Isolated Side. Connect all GNDISO pins to the isolated ground reference.
Secondary Supply Voltage Output for Digital Isolator Isolated Side Power and External Loads. The output
voltage is adjustable from 3.15 V to 5.25 V.
Output Voltage Set. Provide a thermally matched resistor network between VISO and GNDISO to divide therequired output voltage to match the 1.25 V reference voltage. The VISO voltage can be programmed up to
20% higher or 75% lower than VIN but must be within the allowed output voltage range.
Digital Isolator Isolated Side Supply Input, 3.0 V to 5.5 V.
Data Input/Output, Isolated Side.
Clock Input/Output, Isolated Side.

Rev. B | Page 11 of 19

ADM3260

Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS
35

0.50

2.0
IVIN
POWER DISSIPATION

1.8

0.45

25
20

VIN = 5V/VISO = 5V
VIN = 5V/VISO = 3.3V
VIN = 3.3V/VISO = 3.3V

15
10

1.6

0.40

1.4

0.35

1.2

0.30

1.0

0.25

0.8

0.20

0.6

0.15

0.4

0.10

0.2

0.05

IVIN CURRENT (A)POWER DISSIPATION (W)EFFICIENCY (%)

30

5

0.02

0.04

0.06

0.08

LOAD CURRENT (A)0
3.0

Figure 5. Typical Power Supply Efficiency at 5 V/5 V, 5 V/3.3 V, and 3.3 V/3.3 V

3.5

4.0
4.5
5.0
VDDP SUPPLY VOLTAGE (V)

5.5

0
6.0

11890-008

011890-005

0Figure 8. Power Dissipation and IVIN Current vs. VDDP Supply Voltage

450

VISO (100mV/DIV)

350
300
250
200
150
100

90% LOAD

10% LOAD

0
0

10

20

30

40

IISO (mA)(1ms/DIV)

11890-009

VIN = 5V/VISO = 5V
VIN = 5V/VISO = 3.3V
VIN = 3.3V/VISO = 3.3V

5011890-006

POWER DISSIPATION (mW)

400

Figure 9. Typical VISO Transient Load Response, 5 V Output,
10% to 90% Load Step

Figure 6. Typical Total Power Dissipation vs. IISO
35

VISO (100mV/DIV)

30

IISO (mA)

25

20

15
90% LOAD

10VIN = 5V/VISO = 5V
VIN = 5V/VISO = 3.3V
VIN = 3.3V/VISO = 3.3V
0

25

50
IDDP (mA)

75

100(1ms/DIV)

Figure 7. Typical Isolated Output Supply Current (IISO) as a Function ofExternal Load at 5 V/5 V, 5 V/3.3 V, and 3.3 V/3.3 V

11890-010

0

10% LOAD

11890-007

5

Figure 10. Typical VISO Transient Load Response, 3.3 V Input, 3.3 V Output,
10% to 90% Load Step

Rev. B | Page 12 of 19

Data Sheet

ADM3260

VISO (100mV/DIV)

5.0

90% LOAD

4.0

3.5

3.0
30mA LOAD
20mA LOAD
10mA LOAD

2.5

2.0
3.0

11890-011

10% LOAD(1ms/DIV)

4.0

4.5

5.0

5.5

6.0

OUTPUT VOLTAGE (V)Figure 11. Typical VISO Transient Load Response, 5 V Input, 3.3 V Output,
10% to 90% Load Step

Figure 14. Relationship Between Output Voltage and Required Input Voltage,
Under Load to Maintain >80% Duty Factor in the PWM

4.970

500
450

POWER DISSIPATION (mW)

4.965

4.960
VISO (V)

3.5

11890-014

MINIMUM INPUT VOLTAGE (V)

4.5

4.955

4.950

400
350
300
250
VIN = 5V/VISO = 5V
200

VIN = 5V/VISO = 3.3V

4.945

0

1

2

3

4

TIME (µs)

100–4011890-012

4.940

Figure 12. Typical VISO = 5 V Output Voltage Ripple at 90% Load

–20

0
20
40
60
80
AMBIENT TEMPERATURE (°C)

100

120

11890-015

150

Figure 15. Power Dissipation with a 30 mA Load vs. Ambient Temperature

3.280

500
450

POWER DISSIPATION (mW)

3.276

3.274

VIN = 5V/VISO= 5V
VIN = 3.3V/VISO = 3.3V
VIN = 5V/VISO = 3.3V

400
350
300
250
200

3.272

3.270

0

1

2

3

4

TIME (µs)

Figure 13. Typical VISO = 3.3 V Output Voltage Ripple at 90% Load

100
–40

–20

0
20
40
60
80
AMBIENT TEMPERATURE (°C)

100

120

11890-016

150
11890-013

VISO (V)

3.278

Figure 16. Power Dissipation with a 20 mA Load vs. Ambient Temperature

Rev. B | Page 13 of 19

ADM3260

Data SheetTEST CONDITIONVDDISO
R1

SDA1
SCL1

CL1

CL1

ENCODEENCODEDECODEDECODEENCODEENCODEDECODE

SDA2

R2

R2

CL2

CL2

SCL2

GNDISO

GNDP

11890-004

R1

VDDP
DECODE

Figure 17. Timing Test Diagram

Rev. B | Page 14 of 19

Data Sheet

ADM3260

APPLICATIONS INFORMATIONFUNCTIONAL DESCRIPTION
The digital isolator block on the ADM3260 interfaces on eachside to a bidirectional I2C signal. Internally, the I2C interface issplit into two unidirectional channels communicating in
opposing directions via a dedicated iCoupler isolation channel
for each. One channel (the bottom channel of each channel pairshown in Figure 17) senses the voltage state of the Side 1 I2C pin(SCL1 or SDA1) and transmits its state to its respective Side 2
I2C pin (SCL2 or SDA2).
Both the Side 1 (isolated side) and the Side 2 (primary side) I2C
pins interface to an I2C bus operating in the 3.0 V to 5.5 V range.
A logic low on either pin causes the opposite pin to pull low
enough to comply with the logic low threshold requirements of theother I2C devices on the bus. To avoid I2C bus contention, input
a low threshold at SDA1 or SCL1 to guarantee at least 50 mV
less than the output low signal at the same pin. This step prevents
an output logic low at Side 1 from transmitting back to Side 2
and pulling down the I2C bus.
Because the Side 2 logic levels or thresholds are standard I2C
values, multiple ADM3260 devices connected to a bus by theirSide 2 pins communicate with each other and with other I2Ccompatible devices. I2C compatibility refers to situations inwhich the logic levels of a component do not necessarily meetthe requirements of the I2C specification but still allow thecomponent to communicate with an I2C-compliant device.
I2C compliance refers to situations in which the logic levels of
a component meet the requirements of the I2C specification.
However, because the Side 1 pin has a modified output level/
input threshold, this side of the ADM3260 communicates onlywith devices that conform to the I2C standard. In other words,
Side 2 of the ADM3260 is I2C compliant, whereas Side 1 is only
I2C compatible.
The output logic low levels are independent of the VDDISO and
VDDP voltages. The input logic low threshold at Side 1 is also
independent of VDDISO. However, the input logic low threshold at
Side 2 is at 0.3 VDDP, consistent with I2C requirements. The Side 1
and Side 2 pins have open-collector outputs whose high levels
are set via pull-up resistors to their respective supply voltages.

The dc-to-dc converter section of the ADM3260 works on
principles that are common to most modern power supplies.
It has a split controller architecture with isolated pulse-widthmodulation (PWM) feedback. VIN power is supplied to an
oscillating circuit that switches current into a chip-scale air coretransformer. Power transferred to the secondary side is rectified
and regulated to a value between 3.15 V and 5.25 V dependingon the setpoint supplied by an external voltage divider (seeEquation 1). The secondary (VISO) side controller regulates
the output by creating a PWM control signal that is sent to theprimary (VIN) side by a dedicated iCoupler data channel.
The PWM modulates the oscillator circuit to control the power
being sent to the secondary side. Feedback allows for significantly
higher power and efficiency.

VISO = 1.23 ×

RTOP + RBOTTOM(V)
RBOTTOM(1)

where:
RBOTTOM is a resistor between VSEL and GNDISO.
RTOP is a resistor between VSEL and VISO.
Because the output voltage is adjusted continuously, there are
an infinite number of operating conditions. This data sheet
addresses three discrete operating conditions in the Specifications
section. Many other combinations of input and output voltage arepossible; Figure 14 depicts the supported voltage combinationsat room temperature. Figure 14 was generated by using a fixed
VISO load and decreasing the input voltage until the PWM was
at 80% duty cycle. Each of the curves represents the minimum
input voltage that is required for operation under this criterion.
For example, if the application requires 30 mA of output current
at 5 V, the minimum input voltage at VIN is 4.25 V. Figure 14
also illustrates that a configuration with VIN = 3.3 V and VISO =5 V is not recommended. Even at 10 mA of output current, thePWM cannot maintain less than 80% duty factor, leaving no
margin to support load or temperature variations.
Typically, the dc-to-dc converter section of the ADM3260
dissipates about 17% more power between room temperatureand maximum temperature; therefore, the 20% PWM margin
covers temperature variations.
The isolated converter implements undervoltage lockout (UVLO)
with hysteresis on the input/output pins of the primary andsecondary sides as well as the VIN power input. This featureensures that the converter does not go into oscillation due tonoisy input power or slow power-on ramp rates.

Rev. B | Page 15 of 19

ADM3260

Data Sheet

DIGITAL ISOLATOR STARTUPPCB LAYOUT

Both the VDDISO and VDDP supplies of the digital isolator
block have an undervoltage lockout feature to prevent the signal
channels from operating unless certain criteria are met. Thisfeature prevents input logic low signals from pulling down the
I2C bus inadvertently during power-up/power-down.

Supply bypassing of the 0.15 W isoPower integrated dc-to-dc
converter with a low ESR capacitor is required as near the chippads as possible. The isoPower inputs require several passive
components to bypass the power effectively, as well as to set theoutput voltage and to bypass the core voltage regulator (seeFigure 21 through Figure 23).
PDIS
VIN

10µF

+

GNDP
0.1µF

11890-021

To enable the signal channels, the following two criteria must be met:
• Both supplies must be at least 2.5 V.
• At least 40 µs must elapse after both supplies exceed theinternal start-up threshold of 2.0 V.
Until both criteria are met for both supplies, pull the outputs ofthe digital isolator block of the ADM3260 high, ensuring a startup
that avoids any disturbances on the bus.

Figure 21. VIN Bias and Bypass Components

Figure 18 and Figure 19 illustrate the supply conditions for fastand slow input supply slew rates.

VSEL

30kΩ

GNDISO
0.1µF

10kΩ

10µF

+

MINIMUM RECOMMENDED
OPERATING SUPPLY, 3.0V

Figure 22. VISO Bias and Bypass Components

SUPPLY VALID

11890-018

INTERNAL START-UP
THRESHOLD, 2.0V

Figure 18. Digital Isolator Start-Up Condition, Supply Slew Rate > 12.5 V/ms

MINIMUM RECOMMENDED
OPERATING SUPPLY, 3.0V
MINIMUM VALID SUPPLY, 2.5V
SUPPLY VALID

11890-019

INTERNAL START-UP
THRESHOLD, 2.0V

40µs

Figure 19. Digital Isolator Start-Up Condition, Supply Slew Rate < 12.5 V/ms

TYPICAL APPLICATION DIAGRAM
Figure 20 shows a typical application circuit including the pull-up
resistors required for both Side 1 and Side 2 buses. Bypass capacitor
with values from 0.01 µF to 0.1 µF are required between VDDP
and GNDP and between VDDISO and GNDISO.
ISOLATIONBARRIER

VIN
GNDP
ON/OFF

5V_ISOVISO

GNDPGNDISO

SCL2

SCL1

SDA2

SDA1

VDDP

VDDISO

PDIS

VSEL

VDDP

VDDISOGNDP

GNDISO

SDA2

SDA1

SCL2

SCL1

ADM3260

GNDISO

PDIS

VSEL

VIN

VISO
GNDISO

BYPASS < 2mm

Figure 23. Recommended PCB Layout
SDA_ISO

11890-020

SCL_ISO

Figure 20. Typical Isolated I2C Interface Using the ADM3260

GNDISOGNDP

GNDP

GNDISOSDA
SCL

Do not exceed 2 mm for the total lead length between the endsof the low ESR capacitor and the input power supply.

GNDP

ADM3260

5V

The power supply section of the ADM3260 uses a 125 MHz
oscillator frequency to efficiently pass power through its chip-scaletransformers. Choose bypass capacitors carefully because they must
perform more than one function. Noise suppression requires a low
inductance, high frequency capacitor; ripple suppression andproper regulation require a large value bulk capacitor. Connect
these capacitors most conveniently between Pin VIN and
Pin GNDP for VIN and between Pin VISO and Pin GNDISO for
VISO. To suppress noise and reduce ripple, a parallel combinationof at least two capacitors is required. The recommended capacitor
values are 0.1 µF and 10 µF for VIN. The smaller capacitor musthave a low ESR; for example, use of an NP0 or X5R ceramic
capacitor is advised. Ceramic capacitors are also recommended
for the 10 mF bulk capacitance. Add an additional 10 nF
capacitor in parallel if further EMI/EMC control is desired.

Rev. B | Page 16 of 19

11890-023

MINIMUM VALID SUPPLY, 2.5V

40µs11890-022

VISO

Data Sheet

ADM3260

Power dissipation in the device varies with ambient temperature
due to the characteristics of the switching and rectification
elements. Figure 15 and Figure 16 show the relationshipbetween total power dissipation at two load conditions andambient temperature. Use this information to determine thejunction temperature at various operating conditions to ensurethat the device does not go into thermal shutdown unexpectedly.

EMI CONSIDERATIONS
The dc-to-dc converter section of the ADM3260 components
must operate at a very high frequency to allow efficient powertransfer through the small transformers. This high frequency
operation creates high frequency currents that propagate incircuit board ground and power planes, causing edge and dipole
radiation. Grounded enclosures are recommended for applications
that use these devices. If grounded enclosures are not possible,
follow good RF design practices in the layout of the PCB. See
the AN-0971 Application Note for the most current PCB layout
recommendations for the ADM3260.

The insulation lifetime of the ADM3260 depends on the voltage
waveform type imposed across the isolation barrier. The iCoupler
insulation structure degrades at different rates, depending onwhether the waveform is bipolar ac, unipolar ac, or dc. Figure 24,
Figure 25, and Figure 26 illustrate these different isolation voltage
waveforms.
Bipolar ac voltage is the most stringent environment. A 50-year
operating lifetime under the bipolar ac condition determines
the Analog Devices recommended maximum working voltage.
In the case of unipolar ac or dc voltage, the stress on the insulation
is significantly lower. This allows operation at higher working
voltages while still achieving a 50-year service life. The working
voltages listed in Table 14 can be applied while maintaining the
50-year minimum lifetime, provided that the voltage conforms toeither the unipolar ac or dc voltage cases. Any cross-insulation
voltage waveform that does not conform to Figure 25 or Figure 26
must be treated as a bipolar ac waveform, and its peak voltage mustbe limited to the 50-year lifetime voltage value listed in Table 14.

INSULATION LIFETIMERATED PEAK VOLTAGE
0V

Figure 24. Bipolar AC Waveform
RATED PEAK VOLTAGE

0V

All insulation structures eventually break down when subjected tovoltage stress over a sufficiently long period. The rate of insulation
degradation is dependent on the characteristics of the voltage
waveform applied across the insulation. Analog Devices conducts
an extensive set of evaluations to determine the lifetime of theinsulation structure within the ADM3260.

Figure 25. DC Waveform
RATED PEAK VOLTAGE

0V
NOTES
1. THE VOLTAGE IS SHOWN AS SINU SOIDAL FOR ILLUSTRATIONPUPOSES ONLY. IT IS MEANT TO REPRESENT ANY VOLTAGE
WAVEFORM VARYING BETWEEN 0V AND SOME LIMITING VALUE.
THE LIMITING VALUE CAN BE POSITIVE OR NEGATIVE,
BUT THE VOLTAGE CANNOT CROSS 0V.

Figure 26. Unipolar AC Waveform

Rev. B | Page 17 of 19

11890-026

The ADM3260 consist of four internal die attached to a split leadframe with four die attach paddles. For the purposes of thermal
analysis, treat the chip as a thermal unit, with the highest junction
temperature reflected in the θJA value from Table 8. The value of θJAis based on measurements taken with the devices mounted on a
JEDEC standard, 4-layer board with fine width traces and stillair. Under normal operating conditions, the ADM3260 operates
at a full load across the full temperature range without derating
the output current.

11890-024

THERMAL ANALYSIS

Accelerated life testing is performed using voltage levels higher
than the rated continuous working voltage. Acceleration factors forseveral operating conditions are determined, allowing calculationof the time to failure at the working voltage of interest. The values
shown in Table 14 summarize the peak voltages for 50 years ofservice life in several operating conditions. In many cases, theworking voltage approved by agency testing is higher than the
50-year service life voltage. Operation at working voltages
higher than the service life voltage listed leads to prematureinsulation failure.

11890-025

In applications involving high common-mode transients, design
the board layout such that any coupling that does occur affects all
pins on a given component side equally. Failure to ensure this cancause voltage differentials between pins, exceeding the absolute
maximum ratings specified in Table 13, and thereby leading tolatch-up and/or permanent damage.

ADM3260

Data SheetAPPLICATIONS EXAMPLE
RTN

12V

ADM1075–48V HOT SWAP
CONTROLLERAND
DIGITAL POWER
MONITORADP1046
ISOLATEDDIGITAL
DC-TO-DCCONVERTER–48V

3.3V MANAGEMENT BUS

3.3V_ISO
VISO

VIN

SDA1

SCL_ISO–48V

VDDP

ADM3260

SDA2

2
SCL1 POWER + I C SCL2
ISOLATORGNDPGNDISOSDA
SCLPROCESSOR

Figure 27. The ADM3260 Used in −48 V Power Monitoring and Control

Rev. B | Page 18 of 19

11890-027

VDDISOSDA_ISO

Data Sheet

ADM3260

OUTLINE DIMENSIONS
7.50
7.20
6.90

11

20

5.60
5.30
5.00
1

8.20
7.80
7.40

10

0.65 BSCSEATING
PLANE

8°
4°
0°

COMPLIANT TO JEDEC STANDARDS MO-150-AE

0.95
0.75
0.55
060106-A

0.38
0.22

0.05 MIN
COPLANARITY
0.10

0.25
0.09

1.85
1.75
1.65

2.00 MAX

Figure 28. 20-Lead Shrink Small Outline Package [SSOP](RS-20)Dimensions shown in millimeters

ORDERING GUIDE
Model 1
ADM3260ARSZ
ADM3260ARSZ-RL7
EVAL-ADM3260EBZ
1Temperature Range−40°C to +105°C−40°C to +105°C

Package Description
20-Lead Shrink Small Outline Package [SSOP]
20-Lead Shrink Small Outline Package [SSOP]
Evaluation Board

Z = RoHS Compliant Part.

I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2013–2015 Analog Devices, Inc. All rights reserved. Trademarks andregistered trademarks are the property of their respective owners.
D11890-0-4/15(B)Rev. B | Page 19 of 19

Package Option
RS-20
RS-20