2:8 LVDS 1.8V / 2.5V Fanout Buffer
for 1PPS and High-Speed Clocks

8P34S1208
Datasheet

Description

Features

The 8P34S1208 is a high-performance differential LVDS fanout
buffer. The device is designed for the fanout of 1PPS signals or
high-frequency, very low additive phase-noise clock and data
signals.

• Eight low skew, low additive jitter LVDS output pairs• Two selectable, differential clock input pairs• Differential CLK, nCLK pairs can accept the following

The 8P34S1208 supports fail-safe operation and ischaracterized to operate from a 1.8V or 2.5V power supply.
Guaranteed output-to-output and part-to-part skew
characteristics make the 8P34S1208 ideal for those clock
distribution applications demanding well-defined performanceand repeatability. Two selectable differential inputs and eight
low skew outputs are available. The integrated bias voltage
reference enables easy interfacing of single-ended signals tothe device inputs. The device is optimized for low power
consumption and low additive phase noise.

• Maximum input clock frequency: 1.5GHz• LVCMOS/LVTTL interface levels for the control input select pin• Output skew: 20ps (typical)• Propagation delay: 400ps (maximum)• Low propagation delay variation across temperature for 1PPS

differential input levels: LVDS, CML

applications• Low additive phase jitter, RMS; fREF = 156.25MHz, VPP = 1V,
12kHz–20MHz: 34fs (typical)• Device current consumption (IDD):• 120mA typical: 1.8V
• 132mA typical: 2.5V

• Full 1.8V or 2.5V supply voltage• Lead-free (RoHS 6), 28-Lead VFQFPN packaging• -40°C to +85°C ambient operating temperature• Supports case temperature up to +105°C• Supports PCI Express Gen1–5

Q2

nQ1

Q1

VDD

28-lead VFQFPN

13 nQ0

Q2

Q5 24

12 Q0

nQ2

nQ5 255.0 x 5.0 x 0.75 mm
package body

Q3

Q6 26

nQ3

nQ6 27

3.25 x 3.25 mm ePad SizeNBG Package

11 VREF0
10 nCLK0
9 CLK0Top View
1

2

3

4

5

6

7

VREF1

8 VDD

nCLK1

VDD 28

nQ5
Q6

SEL
VREF1

15

nQ4 23

Q5

nCLK1

16

14 GND

nQ4

CLK1

17

8P34S1208

Q4

VDD

18

CLK1

fREF

nQ1

19

SEL

nCLK0

Q4 22

20

nQ7

CLK0

Q1

21

Q7

VDD

nQ0

GND

VREF0

nQ2

Q0
Voltage
Reference

Q3

Pin Assignment
nQ3

Block Diagram

nQ6
Voltage
Reference©2014–2024 Renesas Electronics Corporation

Q7
nQ7

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8P34S1208 Datasheet

Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions[a]Number

Name

1, 14

GND

Power

Power supply pin.

2, 3

Q7, nQ7

OutputDifferential output pair 7. LVDS interface levels.

4

SEL

Input

Pulldown

Reference select control pin. See Table 3 for function. LVCMOS/LVTTL
interface levels.

5

CLK1

Input

Pulldown

Non-inverting differential clock/data input 1.

6

nCLK1

Input

Pullup/Pulldown

Inverting differential clock/data input 1. VDD/2 default when left floating.

7

VREF1

OutputBias voltage reference. Provides an input bias voltage for the CLK1, nCLK1
input pair in AC-coupled applications. Refer to Figures 2B and 2C for
applicable AC-coupled input interfaces.

8, 15, 28

VDD

Power

Power supply pin.

9

CLK0

Input

Pulldown

Non-inverting differential clock/data input 0.

10

nCLK0

Input

Pullup/Pulldown

Inverting differential clock/data input 0. VDD/2 default when left floating.

11

VREF0

OutputBias voltage reference. Provides an input bias voltage for the CLK0, nCLK0
input pair in AC-coupled applications. Refer to Figures 2B and 2C for
applicable AC-coupled input interfaces.

12, 13Q0, nQ0

OutputDifferential output pair 0. LVDS interface levels.

16, 17

Q1, nQ1

OutputDifferential output pair 1. LVDS interface levels.

18, 19Q2, nQ2

OutputDifferential output pair 2. LVDS interface levels.

20, 21Q3, nQ3

OutputDifferential output pair 3. LVDS interface levels.

22, 23Q4, nQ4

OutputDifferential output pair 4. LVDS interface levels.

24, 25Q5, nQ5

OutputDifferential output pair 5. LVDS interface levels.

26, 27

Q6, nQ6

OutputDifferential output pair 6. LVDS interface levels.

[a]

Type

Description

Pulldown and Pullup refers to an internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics
SymbolParameter

Test Conditions

Minimum

TypicalMaximum

Units

CIN

Input Capacitance2

pF

RPULLDOWN

Input Pulldown Resistor

51k

RPULLUP

Input Pullup Resistor

51k

Table 3. SEL Input Function Table[a]
Input

[a]

SEL

Operation0

CLK0, nCLK0 is the selected differential clock input.

1

CLK1, nCLK1 is the selected differential clock input.

SEL is an asynchronous control.

©2014–2024 Renesas Electronics Corporation

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8P34S1208 Datasheet

Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings arestress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC
Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affectproduct reliability.
Item

RatingSupply Voltage, VDD

4.6V

Inputs, VI-0.5V to 4.6V

Inputs, II

20mA

Outputs, IO
Continuous Current
Surge Current

10mA
15mA

Input Sink/Source, IREF

±2mA

Maximum Junction Temperature, TJ,MAX

125°C

Storage Temperature, TSTG

-65°C to 150°C

ESD - Human Body Model, NOTE 1

2000V

ESD - Charged Device Model, NOTE 1

1500V

NOTE 1: According to JEDEC JS-001-2012/JESD22-C101E.

DC Electrical Characteristics
Table 4. Power Supply DC Characteristics, VDD = 1.8V ±5%, TA = -40°C to +85°C
SymbolParameter

VDD

Power Supply Voltage

IDD

Power Supply Current

Test Conditions

Minimum

TypicalMaximum

Units

1.71

1.8

1.89

V

120

140

mA

Minimum

TypicalMaximum

Units

2.1

2.5

2.7

V

132

142

mA

Q0 to Q7 terminated 100 between nQx, Qx

Table 5. Power Supply DC Characteristics, VDD = 2.1V – 2.7V, TA = -40°C to +85°C
SymbolParameter

VDD

Power Supply Voltage

IDD

Power Supply Current

Test Conditions

Q0 to Q7 terminated 100 between nQx, Qx©2014–2024 Renesas Electronics Corporation

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8P34S1208 Datasheet
Table 6. LVCMOS/LVTTL DC Characteristics, VDD = 1.8V
±5%, 2.1V – 2.7V, TA = -40°C to +85°C
SymbolParameter

Test Conditions

VIH

Input High Voltage

VIL

Input Low Voltage, Note 1

IIH

Input High Current

SEL

VDD = VIN = 1.89V, 2.7V

IIL

Input Low Current

SEL

VDD = 1.89V, 2.7V, VIN = 0V

ILEAK

Input Leakage Current SEL

Minimum

TypicalMaximumUnits

0.65 * VDD

VDD + 0.3

V

-0.3

0.35 * VDD

V

150

µA

-10

µA

VIN = 2.7V, VDD = 0V

250

µA

Maximum

Units

150

µA

Note 1: VIL should not be less than -0.3V and VIH should not be higher than VDD.

Table 7. Differential Inputs Characteristics, VDD = 1.8V ±5%, 2.1V – 2.7V, TA = -40°C to +85°C
SymbolParameter

IIH

Input
High Current

IIL

Input
Low Current

ILEAK

Input Leakage
Current

VREF

Reference Voltage for Input
Bias[a]VPP

Peak-to-Peak Voltage

VCMR

Common Mode Input Voltage[b] [c]

[a]
[b]
[c]

Test Conditions

Minimum

Typical

CLK0, nCLK0,
CLK1, nCLK1

VIN = VDD = 1.89V, 2.7V

CLK0, CLK1

VIN = 0V, VDD = 1.89V, 2.7V

-10

µA

nCLK0, nCLK1

VIN = 0V, VDD = 1.89V, 2.7V

-150

µA

CLK0, nCLK0,
CLK1, nCLK1

VIN = 2.7V, VDD = 0V

250

µA

IREF = -100µA, VDD = 1.8V, 2.5V

0.7 * VDD

0.85 * VDDV

VDD = 1.89V, 2.7V

0.2

1.0

V

0.9

VDD – (VPP/2)

V

VREF specification is applicable to the AC-coupled input interfaces shown in Figures 2B and 2C.
Common mode input voltage is defined as crosspoint voltage.
VIL should not be less than -0.3V and VIH should not be higher than VDD.

Table 8. LVDS AC and DC Characteristics, VDD = 1.8V ±5%, 2.1V – 2.7V, TA = -40°C to +85°C [a]SymbolParameter

Test Conditions

Minimum

VOD

Differential Output Voltage

fREF < 1.5GHz,
outputs loaded with 100

VOD

Differential Output Voltage

fREF < 500MHz,
outputs loaded with 100VOD

VOD Magnitude Change

VOS

Offset Voltage

VDD = 1.8V ±5%

VOSOffset Voltage

VDD = 2.1V – 2.7VVOS

VOS Magnitude Change[a]TypicalMaximum

Units

247

454

mV

310

454

mV

50

mV

1.00

1.40

V

1.50

2.10

V

50

mV

Output drive current must be sufficient to drive up to 30cm of PCB trace (assume nominal 50 impedance).

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8P34S1208 Datasheet

AC Electrical Characteristics

Table 9. AC Electrical Characteristics, VDD = 1.8V ±5%, 2.1V – 2.7V, TA = -40°C to +85° [a]SymbolParameter

Test Conditions

fREF

Input
Frequency

CLK[0:1],
nCLK[0:1]

V/t

Input
Edge Rate

CLK[0:1],
nCLK[0:1]

tPD

Propagation Delay[b]tsk(o)

Minimum

TypicalMaximum

Units

1.5

GHz

1.5
CLK[0:1]; nCLK[0:1] to any Qx, nQx
for VPP = 0.4V

315

400

ps

Output Skew[c] [d]

20

40

ps

tsk(i)

Input Skew

10

45

ps

tsk(p)

Pulse Skew

6

20

ps

tsk(pp)Part-to-Part Skew[e]

250

ps

Buffer Additive Phase
Jitter, RMS; refer to
Additive Phase Jitter
SectiontJITtR / t F

MUXISOLATION
[a]
[b]
[c]
[d]
[e]
[f]

fREF = 100MHz

190

V/ns

fREF = 156.25MHz; square wave,
VDD = 1.8V ± 5%, 2.1V - 2.7V, VPP = 0.5V;
Integration range: 1kHz – 40MHz

45

63

fs

fREF = 156.25MHz square wave,
VDD = 1.8V ± 5%, 2.1V – 2.7V, VPP = 1V;
Integration range: 12kHz – 20MHz

34

47

fs

10% to 90%
outputs loaded with 100

305

400

ps

20% to 80%
outputs loaded with 100

175

260

ps

fREF = 100MHz

80

Output Rise/ Fall Time

Mux Isolation[f]dB

Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device ismounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions.
Measured from the differential input crossing point to the differential output crossing point
Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross points.
This parameter is defined in accordance with JEDEC Standard 65.
Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature andwith equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
Qx, nQx outputs measured differentially. See MUX Isolation diagram in the Parameter Measurement Information section.

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Table 10. Characteristics for 1PPS operation, VDD = 1.8V ±5%, 2.1V – 2.7V, TA = -40°C to +85°C[a] [b] [c] [d]SymbolParameter

Test Conditions

T

Input and Output Pulse Period

TP

Positive or Negative Pulse WidthtPD

Propagation Delay;

tsk(p)

Minimum

TypicalMaximum

1

s

100

ns
400

ps

Pulse Skew20

pstsk(i)

Input Skew

45

pstsk(o)

Output Skew[e]

40

ps

250

ps

400

ps

Qx/nQx to Qy/nQy

Part-to-Part SkewtR / tF

Output Rise/Fall Time

[b]
[c]
[d]
[e]
[f]

190

[f]

tsk(pp)[a]

CLKx/nCLKx to Qx/nQx

Units

10% to 90%

305

1PPS (one pulse per second) signals are defined as repetitive pulses with a rate (period) of 1Hz. The positive input pulse width mayvary. The active signal edge is the rising edge. Parameters in this table are characterized for a positive input pulse width of 100ns,
100ms and 500ms; All device interfaces are DC-coupled. Parameters are defined in accordance with ITU-T G.703 Amendment 1 Specifications for the physical layer of the ITU-T G8271/Y.1366 time synchronization interfaces.
Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
tPD, tSK(O), tSK(P) and tSK(P) parameters of differential signals are referenced to the crosspoint.
Differential outputs for 1PPS signal transmission are terminated balanced 100 according to the LVDS Output Load Test Circuit figures. The dedicated 1PPS outputs are the differential outputs Q0-Q3.
This parameter is defined in accordance with JEDEC Standard 65.
Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Eachdevice uses the same type of input.

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8P34S1208 Datasheet

Additive Phase Jitter
The spectral purity in a band at a specific offset from thefundamental compared to the power of the fundamental iscalled the dBc Phase Noise. This value is normally expressedusing a Phase noise plot and is most often the specified plot inmany applications. Phase noise is defined as the ratio of thenoise power present in a 1Hz band at a specified offset from thefundamental frequency to the power value of the fundamental.

This ratio is expressed in decibels (dBm) or a ratio of the powerin the 1Hz band to the power in the fundamental. When therequired offset is specified, the phase noise is called a dBc
value, which simply means dBm at a specified offset from thefundamental. By investigating jitter in the frequency domain, we
get a better understanding of its effects on the desired
application over the entire time record of the signal. It ismathematically possible to calculate an expected bit error rate
given a phase noise plot.

As with most timing specifications, phase noise measurements
have issues relating to the limitations of the measurement
equipment. The noise floor of the equipment can be higher orlower than the noise floor of the device. Additive phase noise isdependent on both the noise floor of the input source andmeasurement equipment.

Measured using a Wenzel 156.25MHz Oscillator as the input
source.

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8P34S1208 Datasheet

Parameter Measurement Information

1.8V LVDS Output Load Test Circuit

Differential Input Level

Pulse Skew

Output Skew

Part-to-Part Skew

Propagation Delay©2014–2024 Renesas Electronics Corporation

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8P34S1208 Datasheet

Output Rise/Fall Time, 20% – 80%

Output Rise/Fall Time, 10% – 90%

Differential Output Voltage Setup

Offset Voltage Setup

MUX Isolation

Input Skew

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8P34S1208 Datasheet

Applications Information
Wiring the Differential Input to Accept Single-Ended Levels
By keeping the same R3/R4 ratio, the values of the resistors canbe increased to reduce the loading for slower and weaker
LVCMOS driver. When using single-ended signaling, the noise
rejection benefits of differential signaling are reduced. Even though
the input can handle larger amplitude signaling, it is recommended
that the amplitude be reduced. For single-ended applications, theswing can be larger. Make sure the single-ended logic high andlogic low signal operates within specification limit. Though some of
the recommended components might not be used, the pads shouldbe placed in the layout. They can be utilized for debugging
purposes. The datasheet specifications are characterized andguaranteed by using a differential signal.

Figure 1A and Figure 1B show examples of how a differential input
can be wired to accept single-ended levels. The values below arefor when both the single ended swing and VDD are at the same
voltage. This configuration requires that the sum of the output
impedance of the driver (Ro) and the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination
at the input will attenuate the signal in half. This can be done in oneof two ways. First, R3 and R4 in parallel should equal thetransmission line impedance and the signal DC offset after AC
coupling should be equal to V1. For most Zo = 50Ω applications,
R3 = 100Ω and R4 can be 100Ω.

VDD

VDD
R3
100

Ro

R1
1k

R5
Zo = 50+

Ro+Rs=Zo
V1

LVC MOS Driv er

R4
100

C1
0.1uF

Receiv er-

R2
1k

Figure 1A. DC Coupling Example for Wiring a Differential Input to Accept Single-ended Levels

VDD

VDD
R3
100

Ro

R1
1k

C2

R5
Zo = 50

Ro+Rs=Zo

+

0.1uF

V1

LVC MOS Driv er

R4
100

C1
0.1uF

Receiv er-

R2
1k

Figure 1B. AC Coupling Example for Wiring a Differential Input to Accept Single-ended Levels©2014–2024 Renesas Electronics Corporation

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8P34S1208 Datasheet

Recommendations for Unused Input and Output Pins
Inputs

Outputs

CLK/nCLK Inputs

LVDS Outputs

For applications not requiring the use of a differential input, both
the CLK and nCLK pins can be left floating. Though not required,but for additional protection, a 1k resistor can be tied from CLK
to ground.

Unused LVDS outputs must either have a 100 differential
termination or have a 100 pull-up resistor to VDD in order toensure proper device operation

1.8V Differential Clock Input Interface
The CLK /nCLK accepts LVDS and other differential signals. The
differential input signal must meet both the VPP and VCMR input
requirements. Figures 2A to 2D show interface examples for the
CLK /nCLK input driven by the most common driver types. The

input interfaces suggested here are examples only. If the driver isfrom another vendor, use their termination recommendation.
Please consult with the vendor of the driver component to confirm
the driver termination requirements.

Figure 2A. Differential Input Driven by an
LVDS Driver - DC Coupling

Figure 2B. Differential Input Driven by an
LVPECL Driver - AC Coupling

Figure 2C. Differential Input Driven by an
LVDS Driver - AC Coupling

Figure 2D. Differential Input Driven by a CML Driver©2014–2024 Renesas Electronics Corporation

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8P34S1208 Datasheet

LVDS Driver Termination
be used with either type of output structure. The second figure,which can also be used with both output types, is an optionaltermination with center tap capacitance to help filter common modenoise. The capacitor value should be approximately 50pF. If using
a non-standard termination, it is recommended to contact Renesas
and confirm if the output structure is current source or voltage
source type. In addition, since these outputs are LVDS compatible,
the input receiver’s amplitude and common-mode input range
should be verified for compatibility with the output.

For a general LVDS interface, the recommended value for thetermination impedance (ZT) is between 90 and 132. The actual
value should be selected to match the differential impedance (Z0)of your transmission line. A typical point-to-point LVDS design uses
a 100 parallel resistor at the receiver and a 100 differential
transmission-line environment. In order to avoid any
transmission-line reflection issues, the components should besurface mounted and must be placed as close to the receiver as
possible. Renesas offers a full line of LVDS compliant devices with
two types of output structures: current source and voltage source.
The standard termination schematic as shown in the first figure canStandard LVDS Termination

Optional LVDS Termination©2014–2024 Renesas Electronics Corporation

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8P34S1208 Datasheet

VFQFPN EPAD Thermal Release PathThus, thermal and electrical analysis and/or testing arerecommended to determine the minimum number needed.
Maximum thermal and electrical performance is achieved when
an array of vias is incorporated in the land pattern. It is
recommended to use as many vias connected to ground as
possible. It is also recommended that the via diameter shouldbe 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel
plating. This is desirable to avoid any solder wicking inside thevia during the soldering process which may result in voids insolder between the exposed pad/slug and the thermal land.
Precautions should be taken to eliminate any solder voids
between the exposed heat slug and the land pattern. Note:
These recommendations are to be used as a guideline only. For
further information, please refer to the Application Note on the
Surface Mount Assembly of Amkor’s Thermally/ ElectricallyEnhance Leadframe Base Package, Amkor Technology.

In order to maximize both the removal of heat from the package
and the electrical performance, a land pattern must be
incorporated on the Printed Circuit Board (PCB) within thefootprint of the package corresponding to the exposed metal
pad or exposed heat slug on the package, as shown in Figure 4.
The solderable area on the PCB, as defined by the solder mask,
should be at least the same size/shape as the exposed pad/slugarea on the package to maximize the thermal/electricalperformance. Sufficient clearance should be designed on the
PCB between the outer edges of the land pattern and the inneredges of pad pattern for the leads to avoid any shorts.
While the land pattern on the PCB provides a means of heattransfer and electrical grounding from the package to the board
through a solder joint, thermal vias are necessary to effectively
conduct from the surface of the PCB to the ground plane(s).
The land pattern must be connected to ground through thesevias. The vias act as “heat pipes”. The number of vias (i.e. “heatpipes”) are application specific and dependent upon the
package power dissipation as well as electrical conductivity
requirements.

Figure 4. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)

Fail-Safe Operation
All clock inputs support fail-safe operation. That is, when thedevice is powered down, the clock inputs can be held at a DC
voltage of up to 4.6V without damaging the device or the input
pins.

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Power Considerations
This section provides information on power dissipation and junction temperature for the 8P34S1208I. Equations and example calculations
are also provided.
1.

Power Dissipation.

The total power dissipation for the 8P34S1208I is the sum of the core power plus the output power dissipation due to the load. The
following is the power dissipation for VDD = 2.7V, which gives worst case results.
The maximum current at 85°C is as follows:
IDD_MAX = 142mA•

Power (core)MAX = VDD_MAX * IDD_MAX = 2.7V * 142mA = 383.4mW
Total Power_MAX = 383.4mW

2.

Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that thebond wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow
and a multi-layer board, the appropriate value is 46.2°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.383W * 46.2°C/W = 102.7°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the typeof board (multi-layer).

Table 11. Thermal Resistance JA for 28 Lead VFQFPN
JA at 0 Air Flow0

1

2Multi-Layer PCB, JEDEC Standard Test Boards

46.2°C/W

39.4C/W

37.1°C/W©2014–2024 Renesas Electronics Corporation

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Reliability Information
Table 12. JA vs. Air Flow Table for a 28 Lead VFQFPN
JA at 0 Air Flow01246.2°C/W

39.4C/W

37.1°C/W

Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards

Transistor CountThe transistor count for the 8P34S1208 is: 976

Package Outline Drawings
The package outline drawings are located at the end of this document and are accessible from the Renesas website (see package links
in Ordering Information). The package information is the most current data available and is subject to change without revision of thisdocument.

Ordering Information
Table 13. Ordering Information
Part Number

Marking

Package

Carrier Type

Temperature Range

8P34S1208NBGIP34S1208NBGI

Lead-Free 28-VFQFPN

Tray-40C to +85C

8P34S1208NBGI8

P34S1208NBGI

Lead-Free 28-VFQFPN

Tape & Reel

-40C to +85C

8P34S1208NBGI/W

P34S1208NBGI

Lead-Free 28-VFQFPN

Tape & Reel

-40C to +85C

Table 14. Pin 1 Orientation in Tape and Reel Packaging
Part Number Suffix

Pin 1 Orientation

Illustration
Correct Pin 1 ORIENTATION8CARRIER TAPE TOPSIDE(Round Sprocket Holes)

Quadrant 1 (EIA-481-C)

USER DIRECTION OF FEEDCorrect Pin 1 ORIENTATION/WCARRIER TAPE TOPSIDE(Round Sprocket Holes)

Quadrant 2 (EIA-481-D/E)

USER DIRECTION OF FEED©2014–2024 Renesas Electronics Corporation

15

July 25, 2024

8P34S1208 Datasheet

Revision History
Revision Date

Description of Change

July 25, 2024

▪ Added Table 14.
▪ Updated part numbers in Ordering Information.

May 9, 2023

Updated IDD test conditions in Table 4 and Table 5.

June 13, 2022

▪ Updated the Block Diagram and product description on page 1

June 3, 2022

Updated the test condition and values for VREF in Table 7

May 26, 2022
May 17, 2022

▪ Updated the maximum value for the Input Leakage Current in Table 6 and Table 7▪ Added description of Fail-Safe Operation.
▪ Added leakage current spec in Table 6 and Table 7
Updated Features:

August 30, 2021

▪ Updated the “Maximum input clock frequency” bullet▪ Changed the “Propagation delay” to be 400ps▪ Added a bullet indicating support for “PCI Express Gen 1-5”

August 13, 2021

Updated Table 8.

August 5, 2021

▪ Updated DC Electrical Characteristics and AC Electrical Characteristics to support 2.5V operation▪ Completed other minor changes

September 8, 2020

Updated the section “Wiring the Differential Input to Accept Single-Ended Levels”.

January 22, 2014

Initial release.

©2014–2024 Renesas Electronics Corporation

16

July 25, 2024

5.00 ±0.10

Pin 1 ID

0.50
22

28

1

21

0.20

3.25 ±0.10
5.00 ±0.10

0.25

15

7

0.40
8

14

Top View

3.25 ±0.10

Bottom View

C

0.75 ±0.10
0.05 Max(0.20)

0.08 C Seating PlaneSide View

5.30

Package
Outline

0.25

NOTES:
1. JEDEC compatible.
2. All dimensions are in mm and angles are in degrees.
3. Use ±0.05 mm for the non-toleranced dimensions.
4. Numbers in ( ) are for references only.
3.25
4.20

3.25

Recommended Land Pattern(PCB Top View, NSMD Design)

5.30

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