White Paper
Battery Management
Battery Protection Using Low-Side FETs Controlled by GPIOs

Abstract
In an MCU plus battery front end (BFE) controlled battery pack, GPIOs may operate as an alternate protection
FET control path where low-side FETs are preferred. Use cases include (1) extending the upper voltage range ofbattery IC to higher voltages by shutting down the high-side charge pumps and (2) repurposing a high-side
solution to a low-side solution with minimal BOM changes. A solution with the ISL94216 device acts as a modelfor a low-side GPIO controlled solution; however, in this white paper, the techniques and principles for low-side
GPIO control generally apply to battery ICs with GPIOs (such as the ISL94216) and for battery pack MCUs withGPIOs (such as the RL78). The ISL94216 BFE simplifies the adoption of low-side control considerably byoffering bit settings to swap the control logic from the high-side FET pins to the built-in GPIOs.

Introduction
BFE devices (such as the ISL94216 or ISL94212) periodically check battery status and the operating
environment to prevent catastrophic failures, so when the devices are combined with an MCU, they optimize
battery life. For managing battery pack state, an internal analog-to-digital converter (ADC) provides accuratemonitoring of pack parameters, typically cell voltage, temperature, and load current. Also, a BFE typicallysupports communication protocols, and this allows customers to connect an MCU in a battery management
solution to control GPIOs or monitor the battery status.
The ISL94216 is a 16-cell BFE IC, an essential component of any battery management system (BMS), and theISL94216 is designed for both high-side and low-side FET control. The ISL94216 datasheet focuses on highside control; however, through a simple configuration setting, the ISL94216 seamlessly supports low-side power
FET control while retaining all control logic, firmware, and peripheral support circuitry. This white paper provides
a guide for using the ISL94216 in low-side battery applications, where the low-side control brings the added
benefit of extending the maximum voltage to 67.2V. A low-side configuration with a disabled charge pump allows
the ISL94216 to operate at a higher maximum pack voltage.
The maximum voltage for standard lithium-ion cells is ~4.2V. An operating maximum rating of 67.2V supports
16-cell series applications. Figure 1 shows the ISL94216 in a battery pack configured for a low-side application.

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Battery Protection Using Low-Side FETs Controlled by GPIOs White Paper

PACK+

ISL94216
BG

LDMON++

Q1-

VREG for Gate Drive
Voltage-EN_VREG

VDD

LD PRESIENABLE

4

VOUT

VCC

VSS

PACK

VSS

VSS

Rpu

ENB_CFETGPIO2

ENB_DFET EN1_Bar

EN2_Bar

GPIO05FET Driver
ISL89411

GPIO1Shut PWR
FETs Off (Sig)

DRV1

DRV2
Vd >Max Battery
Voltage

EN_VREGFETS_NOT_ON

IPACK

Rpu

GPIO3

FETS_ON

DFET_EN

CFET_EN

Rpu

FETS_OFFVPACKRpu

10V to 12V

2VBAT1VSSMCU
RX/RL78

63

PACK-DFET

CFET1Figure 1. ISL94216 Example Configuration for Low-Side Power FET Control

The circuit in Figure 1 is tuned for low-power and performance. This white paper details several control options
shown in the diagram.

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Contents
Abstract .................................................................................................................................................................. 1
Introduction ............................................................................................................................................................ 1
A Functional Overview .......................................................................................................................................... 4
Load Detection (1) ........................................................................................................................................... 4
GPIO Setup for Low-Side Operation (2) .......................................................................................................... 4
MCU (3) ........................................................................................................................................................... 5
VREG for Power FET Driver (4) ......................................................................................................................... 5
Power FET Driver (5) ....................................................................................................................................... 5
CFET and DFET Circuits (6)............................................................................................................................ 6Summary................................................................................................................................................................. 6
Revision History .................................................................................................................................................... 6

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A Functional Overview
The ISL94216 default configuration includes high-side FET control, and after a power-on reset (POR) or reset,
the device reconfigures easily to low-side control by the MCU (as described in the following sections). The
recommended low-side FET configuration, that is illustrated in Figure 1, operates as follows: It starts with thedevice in Low Power Mode, with no load or charger connected, and both the CFET and DFET are off. When aload is attached between the Pack+ and Pack- pins, the LDMON pin activates through the circuitry in Block 1
triggering the load present detect circuit and setting the ISL94216 Load PRESI bit (register 0x64), which wakes
the ISL94216 and changes the mode to IDLE. The transition to IDLE mode signals the load detection to theMCU. There are various firmware implementation options to signal the MCU to enable gate control, and one ofthese options is to have the MCU use the signal to the FETSON pin. Next, the MCU enables the Gate Driver
VREG shown in Block 4, through the EN_VREG signal. This regulator provides power to the gate drive voltage
controlled by the FET Driver in Block 5. The FET Driver enables DFET when signaled from the ISL94216
through GPIO2. These blocks are detailed in the following sections.

Load Detection (1)In high-side power FET configurations, the LDMON pin must be pulled below 1.2V for the LD PRESI bit to beset. In low-side applications, the PACK- pin is pulled towards PACK+ when a load is connected, the opposite
polarity of the load detect circuitry. The circuitry in the white box (1) reverses the polarity so that a load isdetectable for low-side power FET applications.
Using an NMOS with a resistor divider reverses the logic polarity of load detection. To connect to the NMOS
drain, the circuit repurposes the ISL94216 load detection internal pull-up resistor. The circuit is designed to havea pull-down resistance of 1MΩ; as well, an RGS resistance of 33kΩ and 1MΩ detects loads of 15kΩ or less. Forcharger detection, the ISL94216 relies on the MCU.

GPIO Setup for Low-Side Operation (2)The ISL94216 is designed for both high-side and low-side FET control. An internal change from high-side tolow-side FET control only requires a GPIO configuration setting. Low-side FET control uses the GPIO pins of theISL94216. Set the GPIO configuration bits, 0x12.[5:4], to Power FET Gate Drive Out (B11). This setting
connects GPIO2 to the DFET state and GPIO3 to the CFET state. These states are dependent on bits
0x24.1 DFET EN and 0x24.0 CFET EN (in datasheet sections “0x24.1 DFET EN” and “0x24.0 CFET EN”) alongwith other settings and faults as described in the datasheet section “CFET and DFET Pins (50, 51)”. The DFETand CFET states follow the same expected behavior of the DFET and CFET pins except that the state does notdepend on the (disabled in low-side mode) charge pump; as a result, although the high-side DFET and CFETpins are off, the state can be ON (LOW) when the 0x24.7 CPMP EN bit (datasheet section “0x24.7 CPMP EN”)
is 0 and/or the 0x65.5 CPMP NRDY bit (datasheet section “0x65.5 CPMP NRDY”) is 1.
A Hi-Z pin status for pins GPIO2 and GPIO3 equates to DFET and/or CFET being disabled. While the device isin SHIP and LOW POWER modes, the DFET and CFET pins are in a HI-Z state. All faults that control the power
FETs also control pins GPIO2 and GPIO3. For example, an open-wire detection automatically turns off thepower FETs for a high-side application. For a low-side application, the power FET GPIO pins are set to a HI-Z
state with an open-wire fault.
Error! Reference source not found. defines the logic state of the GPIO output pins (3, 2, 0) as a function of theGPIO1 input, the device Mode, and the internal DFET and CFET enable bits.

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Table 1. GPIO Pins in FETs Out Mode
Internal State Variable

Input PinOutput Pins

FETs OffFETs OnDFETCFETModeDFETCFET(GPIO1)(GPIO0)(GPIO2)(GPIO3)SCAN or IDLE

OFF

OFF

LOW

LOW

HI-Z

HI-Z

OFFON

LOW

HI-Z

HI-Z

LOW

ON

OFFLOW

HI-Z

LOW

HI-Z

ON

ONLOW

HI-Z

LOW

LOW

X

X

HIGH

LOW

HI-Z

HI-Z

X

X

X

HI-Z

HI-Z

Hi-Z

LOW POWER or SHIP

GPIO1 is configured as a FETs Off digital input pin. The pin allows the MCU to turn off the power FETs without
serial communication from the MCU to the device. If the logic input is high, both DFET and CFET GPIO pins,
along with the high-side DFET and CFET pins (if enabled), turn off. If the logic input is low, the DFET and CFET
states pass to GPIO2 and GPIO3. Before choosing this configuration, disable both CFET and DFET by setting
their enable bits to 0; next, write 0x3C to register 0x12.
GPIO0 is configured as a FETs ON digital output pin. The output of the pin is LOW when CFET and DFET areboth off. It is high impedance when one or both CFET and DFET GPIO outputs are ON.
Further details are in the datasheet, see section “0x12.5:4 GPIO CONFIG”.

MCU (3)
Just as in a high-side application, the ISL94216 is connected to an MCU to provide a full battery management
solution. The MCU is responsible for register configuration, reading data registers, control override, and otherfeatures such as external communications. Ideal choices for functionality and cost for the MCU include theRenesas 16-bit RL78 family and 32-bit RX family. Typically, the ISL94216 provides a full front-end battery
solution, so the MCU is selected without consideration for front-end functions. Most of the firmware that supports
a high-side FET solution operates in a low-side FET application with only the prior-noted minor updates required
to implement GPIO FET control.

VREG for Power FET Driver (4)The voltage regulator in Block 4 provides the gate drive voltages required by the CFET, DFET, and FET Driver.
The regulator input is connected to VPACK to prevent individual cell(s) from being loaded resulting in cellmismatches. The regulator powers the drive circuitry (for this example, with a regulated output of 12V using theISL89411) that turns ON and OFF the power FETs. An alternative PMIC that can supply the MCU is theRAA212832, which is a programmable buck with two LDO outputs. The voltage regulator is activated through asignal from the MCU on either a load or charger detect.

Power FET Driver (5)Block 5 consists of the ISL89411 dual FET driver that is designed for a gate voltage of 12V and an operating
voltage between 4.5V and 19V. A Zener is connected to DRV2 to protect the driver output pin when a load isconnected. This Zener should be selected with Zener voltage above the Max Battery Voltage. A series gate
resistor (not shown) should be added to the CFET and DFET gate connections, and the gate resistor should bechosen with consideration to any rise/fall time requirements.
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CFET and DFET Circuits (6)Block 6 shows the MOSFETs along with the related drive and protection circuitry. The order of the CFET andDFET is reversed on the low side from the high-side configuration, with the CFET next to the pack pin (Pack- forlow side). With the CFET at the Pack- terminal, the CFET may be exposed to higher voltages on a load connect;
therefore, a Zener across the FETs gate-source, or other protection circuitry is necessary to ensure that the gate
source voltage does not exceed the MOSFET maximum gate voltage rating.

SummaryGPIOs on the ISL94216 are configurable for low-side FET control with minimum effort to extend the battery frontend voltage operation. Depending on the requirements, alternative solutions using GPIOs are plausible; contact
your local Renesas sales representative for more information.

Revision History
Revision

Date1.0

Nov.19.20

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Description
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