Document No.: FT_000060
FT4232H QUAD HIGH SPEED USB TO MULTIPURPOSE UART/MPSSE IC
Datasheet Version 2.05
Clearance No.: FTDI#78

Future Technology
Devices International Ltd
FT4232H Quad High Speed
USB to Multipurpose
UART/MPSSE IC
The FT4232H is FTDI’s 5th generationof USB devices. The FT4232H is a USB
2.0
High
Speed
(480Mb/s)
to
UART/MPSSE ICs. The device features
4 UARTs. Two of these have an option
to independently configure an MPSSE
engine. This allows the FT4232H tooperate as two UART/Bit-Bang ports
plus two MPSSE engines used toemulate JTAG, SPI, I2C, Bit-bang orother synchronous serial modes. The
FT4232H has the following advanced
features:
•
•
•
•

•
•

•

•

Single chip USB to quad serial ports with avariety of configurations.
Entire USB protocol handled on the chip. No
USB specific firmware programming required.
USB 2.0 High Speed (480Mbits/Second) and Full
Speed (12Mbits/Second) compatible.
Two Multi-Protocol Synchronous Serial Engine(MPSSE) on channel A and channel B, tosimplify synchronous serial protocol (USB to
2
JTAG, I C, SPI or bit-bang) design.
Independent Baud rate generators.
RS232/RS422/RS485 UART Transfer Data Rateup to 12Mbaud. (RS232 Data Rate limited byexternal level shifter).
FTDI’s royalty-free Virtual Com Port (VCP) andDirect (D2XX) drivers eliminate the requirementfor USB driver development in most cases.
Optional traffic TX/RX indicators can be addedwith LEDs and an external 74HC595 shift
register.

•
•
•

•

•
•
•
•

•
•
•
•
•
•
•
•
•
•

Adjustable receive buffer timeout.
Support for USB suspend and resume conditions
via PWREN#, SUSPEND# and RI# pins.
Highly integrated design includes +1.8V LDO
regulator for VCORE, integrated POR function
and on chip clock multiplier PLL (12MHz –480MHz).
FTDI FT232B style, asynchronous serial UART
interface option with full hardware handshaking
and modem interface signals.
Fully assisted hardware or X-On / X-Off software
handshaking.
UART Interface supports 7/8 bit data, 1/2 stop
bits, and Odd/Even/Mark/Space/No Parity.
Auto-transmit enable control for RS485 serial
applications using TXDEN pin.
Operational configuration mode and USB
Description strings configurable in external
EEPROM over the USB interface.
Low operating and USB suspend current.
Configurable I/O drive strength (4,8,12 or 16mA)
and slew rate.
Supports bus powered, self powered and highpower bus powered USB configurations.
UHCI/OHCI/EHCI host controller compatible.
USB Bulk data transfer mode (512 byte packets
in High Speed mode).
Dedicated Windows DLLs available for USB to
2
JTAG, USB to SPI, and USB to I C applications.
+1.8V (chip core) and +3.3V I/O interfacing (+5V
Tolerant).
Extended -40°C to 85°C industrial operating
temperature range.
Compact 64-LD Lead Free LQFP or QFN
package+3.3V single supply operating voltage range.

Neither the whole nor any part of the information contained in, or the product described in this manual, may be adapted or reproduced in any material orelectronic form without the prior written consent of the copyright holder. This product and its documentation are supplied on an as-is basis and no warranty
as to their suitability for any particular purpose is either made or implied. Future Technology Devices International Ltd will not accept any claim for damages
howsoever arising as a result of use or failure of this product. Your statutory rights are not affected. This product or any variant of it is not intended for use
in any medical appliance, device or system in which the failure of the product might reasonably be expected to result in personal injury. This document
provides preliminary information that may be subject to change without notice. No freedom to use patents or other intellectual property rights is implied by
the publication of this document. Future Technology Devices International Ltd, Unit 1, 2 Seaward Place, Centurion Business Park, Glasgow G41 1HH
United Kingdom. Scotland Registered Company Number: SC136640

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1

Typical Applications•

Single chip USB to four channels UART (RS232,
RS422 or RS485) or Bit-Bang interfaces.

•••

Single chip USB to 2 JTAG channels plus 2
UARTS.

••

Single chip USB to 1 JTAG channel plus 3
UARTS.

•

Single chip USB to 1 SPI channel plus 3 UARTS.

•

Single chip USB to 2 SPI channels plus 2
UARTS.

•

Single chip USB to 2 Bit-Bang channels plus 2
UARTS.

•
•
•
•
•
•
•
•
•

•

Single chip USB to 1 SPI channel, plus 1 JTAG
channel plus 2 UARTS.

•

Single chip USB to 2 I C channels plus 2
UARTS.

•

Numerous combinations of 4 channels.

•

Upgrading Legacy Peripheral Designs to USB

Field Upgradable USB Products
Cellular and cordless phone USB data transfer
cables and interfaces.
Interfacing MCU / PLD / FPGA based designs to
USB
PDA to USB data transfer
USB Smart Card Readers
USB Instrumentation
USB Industrial Control
USB MP3 Player Interface
USB FLASH Card Reader / Writers
Set Top Box PC - USB interface
USB Digital Camera Interface
USB Bar Code Readers2

1.1

Driver Support

The FT4232H requires USB drivers (listed below) , available free from http://www.ftdichip.com, which
are used to make the FT4232H appear as a virtual COM port (VCP). This allows the user to communicate
with the USB interface via a standard PC serial emulation port (for example TTY). Another FTDI USB
driver, the D2XX driver, can also be used with application software to directly access the FT4232H
through a DLL.

Royalty free VIRTUAL COM PORT
(VCP) DRIVERS for...

Royalty free D2XX Direct Drivers(USB Drivers + DLL S/W Interface)•

Windows 2000, Server 2003, Server 2008•

Windows 2000, Server 2003, Server 2008•

Windows XP and XP 64-bit•

Windows XP and XP 64-bit•

Windows Vista and Vista 64-bit•

Windows Vista and Vista 64-bit•

Windows XP Embedded•

Windows XP Embedded•

Windows CE 4.2, 5.0, 5.2 and 6.0•

Windows CE 4.2, 5.0, 5.2 and 6.0•

Mac OS-X•

Linux (2.4 or later) and Linux x86_64

For driver installation, please refer to the application note:•

AN_106, “Advanced Driver Options”.

The following additional installation guides and technical notes are also available:

•
•
•
•
•
•
•

AN_103, “FTDI Drivers Installation Guide for VISTA”.
AN_104, “FTDI Drivers Installation Guide for WindowsXP”.
AN_109, “Programming Guide for High Speed FTCI2C DLL ”.
AN_110, “Programming Guide for High Speed FTCJTAG DLL ”.
AN_111, “Programming Guide for High Speed FTCSPI DLL ”.
AN_113, “Interfacing FT2232H Hi-Speed Devices To I2C Bus”.
TN_104, “Guide to Debugging Customers Failed Driver Installation”.

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1.2

Part Numbers

Part Number

Package

FT4232HL-XXXX

64 Pin LQFP

FT4232HQ-XXXX

64 Pin QFN

Note: Packing codes for xxxx is:- Reel: Taped and Reel (LQFP =1000 pcs per reel, QFN =4000 pcs per reel)-Tray: Tray packing, (LQFP =160 pcs per tray, QFN =260 pcs per tray)

Please refer to section 8 for all package mechanical parameters.

1.3

USB Compliant

At the time of writing this datasheet, the FT4232H (Rev B) was still to complete USB compliancy testing.

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FT4232H Block Diagram

Figure 2.1 FT4232H Block Diagram

For a description of each function please refer to Section 4.

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Table of Contents
1

Typical Applications ...................................................................... 2
1.1

Driver Support .................................................................................... 2

1.2

Part Numbers...................................................................................... 3

Note: Packing codes for xxxx is: ................................................................. 3
1.3

USB Compliant .................................................................................... 32

FT4232H Block Diagram ............................................................... 4

3

Device Pin Out and Signal Description .......................................... 7
3.1

64-Pin LQFP and 64-Pin QFN Package Schematic Symbol ................... 7

3.2

FT4232H Pin Descriptions ................................................................... 8

3.3

Common Pins .................................................................................... 10

3.4

Configured Pins ................................................................................ 12

3.4.1

FT4232H pins used as an asynchronous serial interface .................................................. 12

3.4.2

FT4232H pins used in a Synchronous or Asynchronous Bit-Bang Interface ........................ 13

3.4.3

FT4232H pins used in an MPSSE .................................................................................. 14

4

Function Description................................................................... 15
4.1

Key Features ..................................................................................... 15

4.2

Functional Block Descriptions ........................................................... 15

4.3

FT232 UART Interface Mode Description........................................... 17

4.3.1

RS232 Configuration .................................................................................................. 17

4.3.2

RS422 Configuration .................................................................................................. 18

4.3.3

RS485 Configuration .................................................................................................. 194.4

MPSSE Interface Mode Description. .................................................. 20

4.5

Synchronous and Asynchronous Bit-Bang Interface Mode Description
21

4.6

FT4232H Mode Selection................................................................... 23

5

Devices Characteristics and Ratings ........................................... 24
5.1

Absolute Maximum Ratings............................................................... 24

5.2

DC Characteristics............................................................................. 25

6

FT4232H Configurations ............................................................. 28
6.1

USB Bus Powered Configuration ...................................................... 28

6.2

USB Self Powered Configuration ....................................................... 30

6.3

Oscillator Configuration .................................................................... 32

6.4

4 Channel Transmit and Receiver LED Indication Example ............... 33

7

EEPROM Configuration................................................................ 34

8

Package Parameters ................................................................... 35
8.1

FT4232HQ, QFN-64 Package Dimensions .......................................... 36
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8.2

FT4232HL, LQFP-64 Package Dimensions ......................................... 37

8.3

Solder Reflow Profile ........................................................................ 39

Contact Information ................................................................... 41
Appendix A - List of Figures and Tables ..................................................... 42
List of Tables ............................................................................................. 42
Appendix B - Revision History.................................................................... 43

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3

Device Pin Out and Signal Description

The 64-pin LQFP and 64-pin QFN have the same pin numbering for specific functions. This pin numbering
is illustrated in the schematic symbol shown in Figure 3.1.

3.1

50

64-Pin LQFP and 64-Pin QFN Package Schematic Symbol

VREGINADBUS0ADBUS1ADBUS2
ADBUS3
ADBUS4
ADBUS5ADBUS6ADBUS749 VREGOUT

7
8
6
14

63
62
61
2

3
13

DM
DP
REF
RESET#

FT4232H

BDBUS0BDBUS1
BDBUS2
BDBUS3
BDBUS4
BDBUS5
BDBUS6
BDBUS7
CDBUS0
CDBUS1
CDBUS2
CDBUS3
CDBUS4
CDBUS5
CDBUS6
CDBUS7EECS
EECLKEEDATA

DDBUS0DDBUS1
DDBUS2
DDBUS3
DDBUS4
DDBUS5
DDBUS6
DDBUS7OSCIOSCO
PWREN#SUSPEND#

TEST

16
17
18
19
21
22
23
24
26
27
28
29
30
32
33
34
38
39
40
41
43
44
45
46
48
52
53
54
55
57
58
59
60
36

Figure 3.1 FT4232H Schematic Symbol

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3.2

FT4232H Pin Descriptions

This section describes the operation of the FT4232H pins. Both the LQFP and the QFN packages have thesame function on each pin. The function of many pins is determined by the configuration of the FT4232H.
The following table details the function of each pin dependent on the configuration of the interface. Each of
the functions are described in Table 3.1(Note: The convention used throughout this document for active low signals is the signal name followed by a#)

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FT4232H
Pins

Pin functions (depend on configuration)
ASYNC Serial(RS232)ASYNC BitSYNC Bitbangbang
Channel A

Pin #Pin Name

MPSSE

16

ADBUS0

TXD

D0

D0

TCK/SK

17

ADBUS1

RXD

D1

D1

TDI/DO18

ADBUS2

RTS#

D2

D2

TDO/DI19

ADBUS3

CTS#

D3

D3

TMS/CS

21

ADBUS4

DTR#

D4

D4

GPIOL022

ADBUS5

DSR#

D5

D5

GPIOL123

ADBUS6

DCD#

D6

D6

GPIOL224

ADBUS7

RI#/ TXDEN*

D7D7GPIOL3Channel B
26

BDBUS0

TXD

D0

D0

TCK/SK

27
28

BDBUS1

RXD

D1

D1

TDI/DOBDBUS2

RTS#

D2

D2

TDO/DI29

BDBUS3

CTS#

D3

D3

TMS/CS

30

BDBUS4

DTR#

D4

D4

GPIOL032

BDBUS5

DSR#

D5

D5

GPIOL133

BDBUS6

DCD#

D6

D6

GPIOL2

34

BDBUS7

RI#/ TXDEN*

D7D7GPIOL338

CDBUS0

TXD

D0

D0

RS232 or Bit-Bang interface

39

CDBUS1

RXD

D1

D1

RS232 or Bit-Bang interface

40

CDBUS2

RTS#

D2

D2

RS232 or Bit-Bang interface

41

CDBUS3

CTS#

D3

D3

RS232 or Bit-Bang interface

43

CDBUS4

DTR#

D4

D4

RS232 or Bit-Bang interface

44

CDBUS5

DSR#

D5

D5

RS232 or Bit-Bang interface

45

CDBUS6

DCD#

D6

D6

RS232 or Bit-Bang interface

46

CDBUS7

RI#/ TXDEN*

D7

D7

RS232 or Bit-Bang interface

Channel C

Channel D
48

DDBUS0

TXD

D0

D0

RS232 or Bit-Bang interface

52
53

DDBUS1

RXD

D1

D1

RS232 or Bit-Bang interface

DDBUS2

RTS#

D2

D2

RS232 or Bit-Bang interface

54

DDBUS3

CTS#

D3

D3

RS232 or Bit-Bang interface

55

DDBUS4

DTR#

D4

D4

RS232 or Bit-Bang interface

57

DDBUS5

DSR#

D5

D5

RS232 or Bit-Bang interface

58

DDBUS6

DCD#

D6

D6

RS232 or Bit-Bang interface

59

DDBUS7

RI#/ TXDEN*

D7

D7

RS232 or Bit-Bang interface

60

PWREN#PWREN#PWREN#PWREN#PWREN#36

SUSPEND#SUSPEND#SUSPEND#SUSPEND#SUSPEND#

Configuration memory interface
63

EECS

62

EECLK

61

EEDATA

Table 3.1 FT4232H Pin Configurations* RI#/ or TXDEN is selectable in the EEPROM. Default is RI#.

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3.3

Common Pins

The operation of the following FT4232H pins are the same regardless of the configured mode:Pin No.

Name12,37,64

VCORE

20,31,42,56

VCCIO

9

VPLL

4

VPHY

50

VREGIN49

VREGOUT

10

AGND

1,5,11,15,
25,35,47,51

GND

Type
POWER
Input
POWER
Input
POWER
Input
POWER
Input
POWER
Input
POWER
Output
POWER
Input
POWER
Input

Description+1.8V input. Core supply voltage input+3.3V input. I/O interface power supply input. Failure toconnect all VCCIO pins will result in failure of the device.

+3.3V input. Internal PHY PLL power supply input. It is
recommended that this supply is filtered using an LC filter.
+3.3V Input. Internal USB PHY power supply input. Note that thiscannot be connected directly to the USB supply. A +3.3V
regulator must be used. It is recommended that this supply isfiltered using an LC filter.
+3.3V Input. Integrated 1.8V voltage regulator input.

+1.8V Output. Integrated voltage regulator output. Connect to
VCORE with 3.3uF filter capacitor.

0V Analog ground.

0V Ground input.

Table 3.2 Power and Ground

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Pin No.

Name

Type

2

OSCI

INPUT

Oscillator input.

3

OSCO

OUTPUT

Oscillator output.

6

REF

INPUT

Current reference – connect via a 12K Ohm resistor @ 1% to
GND.

7

DM

INPUT

USB Data Signal Minus.

INPUT

USB Data Signal Plus.

8

DP

Description

13

TEST

INPUT

IC test pin – for normal operation should be connected to GND.

14

RESET#

INPUT

Reset input (active low).
Active low power-enable output.
PWREN# = 0: Normal operation.

60

PWREN#OUTPUT

PWREN# =1 : USB SUSPEND mode or device has not been
configured.
This can be used by external circuitry to power down logic whendevice is in USB suspend or has not been configured.

36

SUSPEND#OUTPUT

Active low when USB is in suspend mode.

Table 3.3 Common Function pins

Pin No.

63
62

61

Name

Type

EECS

I/O

EECLK

OUTPUT

EEDATA

I/O

Description

EEPROM – Chip Select. Tri-State during device reset.
Clock signal to EEPROM. Tri-State during device reset. When not in reset,
this outputs the EEPROM clock.
EEPROM – Data I/O Connect directly to Data-In of the EEPROM and toData-Out of the EEPROM via a 2.2K resistor. Also, pull Data-Out of the
EEPROM to VCC via a 10K resistor for correct operation. Tri-State during
device reset.

Table 3.4 EEPROM Interface Group

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3.4

Configured Pins

The following sections describe the function of the configurable pins referred to in Table 3.1 which isdetermined by how the FT4232H is configured.

3.4.1

FT4232H pins used as an asynchronous serial interface

The FT4232H any of the 4 channels can be configured as an asynchronous serial UART interface(RS232/422/485). When configured in this mode, the pins used and the descriptions of the signals areshown in Table 3.5.
ChannelA

ChannelB

ChannelC

ChannelD

Pin No.

Pin No.

Pin No.

Pin No.

16

26

38

17

27

18

RS232 Configuration
Description

Name

Type

48

TXD

OUTPUT

TXD = transmitter output

39

52

RXD

INPUT

RXD = receiver input

28

40

53

RTS#

OUTPUT

19

29

41

54

CTS#

INPUT

21

30

43

55

DTR#

OUTPUT

22

32

44

57

DSR#

INPUT

23

33

45

58

DCD#

INPUT

24

34

46

59

RI#/
TXDEN

INPUT/OUTPUT

RTS# = Ready To send
handshake output
CTS# = Clear To Send
handshake input
DTR# = Data Transmit Readymodem signaling line
DSR# = Data Set Ready modem
signaling line
DCD# = Data Carrier Detect
modem signaling line
RI# = Ring Indicator Control
Input. When the Remote Wakeup option is enabled in the
EEPROM, taking RI# low can beused to resume the PC USB Host
controller from suspend.
TXDEN = (TTL level). For use
with RS485 level converters.

Table 3.5 Channel A,B,C and Channel D Asynchronous Serial Interface Configured Pin Descriptions

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3.4.2

FT4232H pins used in a Synchronous or Asynchronous Bit-Bang Interface

The FT4232H channel A,B,C or channel D can be configured as a bit-bang interface. There are two typesof bit-bang modes: synchronous and asynchronous.
When configured in any bit-bang mode (synchronous or asynchronous), the pins used and thedescriptions of the signals are shown in Table 3.6
ChannelNumberPin Nos.

A

24,23,22,21,
19,18,17,16

B

Synchronous or Asynchronous Bit-Bang
Configuration Description

ADBUS[7:0]

I/O

Channel A, D7 to D0 bidirectional bit-bang data

BDBUS[7:0]

I/O

Channel B, D7 to D0 bidirectional bit-bang data

CDBUS[7:0]

I/O

Channel C, D7 to D0 bidirectional bit-bang data

DDBUS[7:0]

I/O

Channel D, D7 to D0 bidirectional bit-bang data

46,45,44,43,
41,40,39,38

D

Type

34,33,32,30,
29,28,27,26

C

Name

59,58,57,55
54,53,52,48

Table 3.6 Channel A,B,C and Channel D Synchronous or Asynchronous Bit-Bang Configured Pin
Descriptions

For a functional description of this mode, please refer to section 4.5 Synchronous and Asynchronous BitBang Interface Mode Description.

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3.4.3

FT4232H pins used in an MPSSE

The FT4232H channel A and channel B each have a Multi-Protocol Synchronous Serial Engine (MPSSE). Each MPSSE
can be independently configured to a number of industry standard serial interface protocols such as JTAG, I2C or SPI, or
it can be used to implement a proprietary bus protocol. For example, it is possible to use one of the FT4232H’s channels(e.g. channel A) to connect to an SRAM configurable FPGA such as supplied by Altera or Xilinx. The FPGA device would
normally be un-configured (i.e. have no defined function) at power-up. Application software on the PC could use theMPSSE to download configuration data to the FPGA over USB. This data would define the hardware function on power
up. The other MPSSE channel (e.g. channel B) would be available for another serial interface function while channel C
and channel D can be configured as UART or bit-bang mode. Alternatively each MPSSE can be used to control anumber of GPIO pins. When configured in this mode, the pins used and the descriptions of the signals are shown in
Table 3.7
Channel A

Channel B

Pin No.

Pin No.

Name

Type

MPSSE Configuration Description
Clock Signal Output. For example:

16

26

TCK/SKOUTPUT

JTAG – TCK, Test interface clock
SPI – SK, Serial Clock
Serial Data Output. For example:

17

27

TDI/DOOUTPUT

JTAG – TDI, Test Data Input
SPI – DO, serial data output
Serial Data Input. For example:

18

28

TDO/DIINPUTJTAG – TDO, Test Data output
SPI – DI, Serial Data Input
Output Signal Select. For example:

19

29

TMS/CSOUTPUT

JTAG – TMS, Test Mode SelectSPI – CS, Serial Chip Select21

30

GPIOL0I/O

General Purpose input/output

22

32

GPIOL1

I/O

General Purpose input/output

23

33

GPIOL2

I/O

General Purpose input/output

24

34

GPIOL3

I/O

General Purpose input/output

Table 3.7 Channel A and Channel B MPSSE Configured Pin Descriptions

For a functional description of this mode, please refer to section 4.4.
When either Channel A or Channel B or both channels are used in MPSSE mode, Channel C and Channel D
can be configured as asynchronous serial interface (RS232/422/485) or Bit-Bang mode or a combination ofboth.

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4

Function Description

The FT4232H is FTDI’s 5th generation of USB devices. The FT4232H is a USB 2.0 High Speed (480Mb/s)
to UART/MPSSE ICs. It has the capability of being configured in a variety of industry standard serialinterfaces.
The FT4232H has four independent configurable interfaces. Two of these interfaces can be configured as
UART, JTAG, SPI, I2C or bit-bang mode, using an MPSSE, with independent baud rate generators. The
remaining two interfaces can be configured as UART or bit-bang.

4.1

Key Features

USB High Speed to Quad Interface. The FT4232H is a USB 2.0 High Speed (480Mbits/s) to quad
flexible/configurable serial interfaces.
Functional Integration. The FT4232H integrates a USB protocol engine which controls the physical
Universal Transceiver Macrocell Interface (UTMI) and handles all aspects of the USB 2.0 High Speedinterface. The FT4232H includes an integrated +1.8V Low Drop-Out (LDO) regulator and 12MHz to 480MHz
PLL. It also includes 2kbytes Tx and Rx data buffers per channel. The FT4232H effectively integrates theentire USB protocol on a chip.
MPSSE.Multi-Purpose Synchronous Serial Engines (MPSSE), capable of speeds up to 30 Mbits/s, provides
flexible synchronous interface configurations.
Data Transfer rate. The FT4232H supports a data transfer rate up to 12 Mbit/s when configured as an
RS232/RS422/RS485 UART interface.
Latency Timer. This is really a feature of the driver and is used to as a timeout to flush short packets of databack to the PC. The default is 16ms, but it can be altered between 0ms and 256ms. At 0ms latency you get apacket transfer on every high speed microframe.

4.2

Functional Block Descriptions

Quad Multi-Purpose UART/MPSSE Controllers. The FT4232H has four independent UART/MPSSE
Controllers. These blocks control the UART data or control the Bit-Bang mode if selected by the SETUP
command. The blocks used on channel A and channel B also contain a MPSSE (Multi Protocol
Synchronous Serial Engine) in each of them which can be used independently of each other and theremaining UART channels. Using this it can be configured under software command to have 1 MPSSE + 3
UARTS (each UART can be set to Bit Bang mode to gain extra I/O if required) or 2 MPSSE + 2 UARTS.
USB Protocol Engine and FIFO control. The USB Protocol Engine controls and manages the interface
between the UTMI PHY and the FIFOs of the chip. It also handles power management and the USB protocol
specification.
Dual Port FIFO TX Buffer (2Kbytes per channel). Data from the Host PC is stored in these buffers to be
used by the Multi-purpose UART/FIFO controllers. This is controlled by the USB Protocol Engine and FIFO
control block.
Dual Port FIFO RX Buffer (2Kbytes per channel). Data from the Multi-purpose UART/FIFO controllers isstored in these blocks to be sent back to the Host PC when requested. This is controlled by the USB
Protocol Engine and FIFO control block.
RESET Generator - The integrated Reset Generator Cell provides a reliable power-on reset to the device
internal circuitry at power up. The RESET# input pin allows an external device to reset the FT4232H.
RESET# should be tied to VCCIO (+3.3v) if not being used.
Independent Baud Rate Generators - The Baud Rate Generators provides a x16 or a x10 clock input to the
UART’s from a 120MHz reference clock and consists of a 14 bit pre-scaler and 4 register bits which provide
fine tuning of the baud rate (used to divide by a number plus a fraction). This determines the Baud Rate of
the UART which is programmable from 183 baud to 12 million baud.
See FTDI application note AN232B-05 on the FTDI website (www.ftdichip.com) for more details.

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Clearance No.: FTDI#78+1.8V LDO Regulator. The +1.8V LDO regulator generates the +1.8 volts for the core and the USBtransceiver cell. Its input (VREGIN) must be connected to a +3.3V external power source. It is also
recommended to add an external filtering capacitor to the VREGIN. There is no direct connection from the+1.8V output (VREGOUT) and the internal functions of the FT4232H. The PCB must be routed to connect
VREGOUT to the pins that require the +1.8V including VREGIN.
UTMI PHY. The Universal Transceiver Macrocell Interface (UTMI) physical interface cell. This block handles
the Full speed / High Speed SERDES (serialise - deserialise) function for the USB TX/RX data. It also
provides the clocks for the rest of the chip. A 12 MHz crystal should be connected to the OSCI and OSCO
pins. A 12K Ohm resistor should be connected between REF and GND on the PCB.
The UTMI PHY functions include:•

Supports 480 Mbit/s "High Speed" (HS)/ 12 Mbit/s “Full Speed” (FS), FS Only and "Low Speed"
(LS).

•

SYNC/EOP generation and checking.

•

Data and clock recovery from serial stream on the USB.

•

Bit-stuffing/unstuffing; bit stuff error detection.

•

Manages USB Resume, Wake Up and Suspend functions.

•Single parallel data clock output with on-chip PLL to generate higher speed serial data clocks.

EEPROM Interface. When used without an external EEPROM the FT4232H defaults to a quad USB to an
asynchronous serial port device. Adding an external 93C46 (93C56 or 93C66) EEPROM allows each of thechip’s channels to be independently configured as a serial UART (RS232 mode), bit-bang mode or fast serial(opto isolation). The external EEPROM can also be used to customise the USB VID, PID, Serial Number,
Product Description Strings and Power Descriptor value of the FT4232H for OEM applications. Other
parameters controlled by the EEPROM include Remote Wake Up, Soft Pull Down on Power-Off and I/O pin
drive strength.
The EEPROM must be a 16 bit wide configuration such as a Microchip 93LC46B or equivalent capable of a
1Mbit/s clock rate at VCC = +3.00V to 3.6V. The EEPROM is programmable in-circuit over USB using autility program called MPROG available from FTDI’s web site (www.ftdichip.com). This allows a blank partto be soldered onto the PCB and programmed as part of the manufacturing and test process.
If no EEPROM is connected (or the EEPROM is blank), the FT4232H will default to serial ports. The device
uses its built-in default VID (0403), PID (6011) Product Description and Power Descriptor Value. In this case,the device will not have a serial number as part of the USB descriptor.

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4.3

FT232 UART Interface Mode Description

The FT4232H can be configured in similar UART modes as the FTDI FT232 devices (an asynchronous
serial interface). The following examples illustrate how to configure the FT4232H with an RS232, RS422
or RS485 interfaces. The FT4232 can be configured as a mixture of these interfaces.

4.3.1

RS232 Configuration

Figure 4.1 illustrates how the FT4232H channel A can be configured with an RS232 UART interface. Thiscan be repeated for channels B, C and D to provide a quad RS232, but has been omitted for clarity.

Figure 4.1 RS232 Configuration

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4.3.2

RS422 Configuration

Figure 4.2 illustrates how the FT4232H can be configured as a dual RS422 interface. The FT4232H canhave all 4 channels connected as RS422, but only channel A and channel C are shown for clarity.

FT4232H
60
PWREN#SUSPEND#
TXD

VCC
14 SP491
4

DB9-M
RS422 Channel A

10

36
5

16

3

17

2

D

TXDM_A

9

TXDP_A
RXDP_A

11

RXD
RTS#
CTS#
DTR#
DSR#
DCD#
RI#

18

R
6

19
21

4

22

5

23

12

120R

7

RXDM_A

VCC
14 SP491

GND

10
D

RTSM_A9

RTSP_ACTSP_A

3
11

24

2

R
6

12

120R

CTSM_A

7VCC
14 SP491

4

DB9-M
RS422 Channel C

10
5

D

38
TXD

TXDM_C

9

TXDP_C
RXDP_C

3
11

39
2

RXD

R

12

120R

40
RTS#

6

7

RXDM_C

VCC
14 SP491

GND

41
CTS#
43
DTR#

4

44
DSR#

10
5

45
DCD#
46
RI#

D

RTSM_C9

RTSP_CCTSP_C

3
11
2

R
6

7

12

120R
CTSM_C

Figure 4.2 Dual RS422 Configuration

In this case both channel A and channel C are configured as UART operating at TTL levels. The Sipex
SP491 is used as a level converter to convert the TTL level signals from the FT4232H to RS422 levels.
The PWREN# signal is used to power down the level shifters such that they operate in a low quiescentcurrent when the USB interface is in suspend mode.

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4.3.3

RS485 Configuration

Figure 4.3 illustrates how the FT4232H can be configured as a dual RS485 interface. The FT4232H canhave all 4 channels connected as RS485, but only channel A and channel C are shown for clarity.
D B 9 -M
R S485 C hannel A

FT4232HPW REN#

60
8

VCC
SP481

3
7
TXD
RXD
RTS#
CTS#
DTR#

16

4

17

2

18

D M _A

D
6

1

R

19

DPA
GND

5
120R

21
L IN K

DSR#
DCD#

TXDEN

22
23

24

D B 9 -M
R S485 C hannel C
8

VCC
SP481

3
7
38

4

39

2

TXD

D M _B

D
6

DP_B

RXD
40

1

R

GND

RTS#
41
CTS#

5
120R

43
DTR#

L IN K
44

DSR#
45
DCD#

TXDEN

46

Figure 4.3 Dual RS485 Configuration

In this case both channel A and channel C are configured as RS485 operating at TTL levels. This example
uses two Sipex SP491 devices but there are similar parts available from Maxim and Analog Devices
amongst others. The SP491 is a RS485 device in a compact 8 pin SOP package. It has separate enables
on both the transmitter and receiver. With RS485, the transmitter is only enabled when a character is beingtransmitted from the UART. The TXDEN pins on the FT4232H are provided for exactly that purpose, and so
the transmitter enables are wired to the TXDEN’s. The receiver enable is active low, so it is wired to the
PWREN# pin to disable the receiver when in USB suspend mode.
RS485 is a multi-drop network – i.e. many devices can communicate with each other over a single two wire
cable connection. The RS485 cable requires to be terminated at each end of the cable. Links are provided toallow the cable to be terminated if the device is physically positioned at either end of the cable.
In this example the data transmitted by the FT4232H is also received by the device that is transmitting. Thisis a common feature of RS485 and requires the application software to remove the transmitted data from thereceived data stream. With the FT4232H it is possible to do this entirely in hardware – simply modify theschematic so that RXD of the FT4232H is the logical OR of the SP481 receiver output with TXDEN using an
HC32 or similar logic gate.

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4.4

MPSSE Interface Mode Description.

MPSSE Mode is designed to allow the FT4232H to interface efficiently with synchronous serial protocols
such as JTAG, I2C and SPI Bus. It can also be used to program SRAM based FPGA’s over USB. The
MPSSE interface is designed to be flexible so that it can be configured to allow any synchronous serial
protocol (industry standard or proprietary) to be implemented using the FT4232H. MPSSE is only available
on channel A and channel B.
MPSSE is fully configurable, and is programmed by sending commands down the data stream. These canbe sent individually or more efficiently in packets. MPSSE is capable of a maximum sustained data rate of 30
Mbits/s.
When a channel is configured in MPSSE mode, the IO timing and signals used are shown in Figure 4.4 andTable 4.1. These show timings for CLKOUT=30MHz. CLKOUT can be divided internally to be provide aslower clock.

Figure 4.4 MPSSE Signal Waveforms

NAME
t1
t2
t3
t4
t5
t6

MIN
15
15
1
0
11

NOM
33.33
16.67
16.67

MAX

7.15

Units
ns
ns
ns
ns
ns

COMMENT
CLKOUT period
CLKOUT high period
CLKOUT low period
CLKOUT to TDI/DO delay
TDO/DI hold time
TDO/DI setup time

Table 4.1 MPSSE Signal Timings

MPSSE mode is enabled using Set Bit Bang Mode driver command. A hex value of 2 will enable it, and ahex value of 0 will reset the device. See application note AN2232L-02, “Bit Mode Functions for the
FT2232D” for more details and examples.
The MPSSE command set is fully described in application note AN_108 – “Command Processor For
MPSSE and MCU Host Bus Emulation Modes”.
The following additional application notes are available for configuring the MPSSE :•••AN_109 – “Programming Guide for High Speed FTCI2C DLL”
AN_110 – “Programming Guide for High Speed FTCJTAG DLL”
AN_111 – “Programming Guide for High Speed FTCSPI DLL”

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4.5

Synchronous and Asynchronous Bit-Bang Interface Mode Description

The FT4232H channel A,B,C or channel D can be configured as a bit-bang interface. There are two types ofbit-bang modes: synchronous and asynchronous.

Asynchronous Bit-Bang Mode
Asynchronous Bit-Bang mode is the same as BM-style Bit-Bang mode. On any channel configured inasynchronous bit-bang mode. data written to the device in the normal manner will be self clocked onto theparallel I/O data pins (those which have been configured as outputs). Each I/O pin can be independently set
as an input or an output. The rate that the data is clocked out at is controlled by the baud rate generator.
For the data to change there has to be new data written, and the baud rate clock has to tick. If no new data is
written to the channel, the pins will hold the last value written.

Synchronous Bit-Bang Mode
The synchronous Bit-Bang mode will only update the output parallel I/O port pins whenever data is sent fromthe USB interface to the parallel interface. When this is done, data is read from the USB Rx FIFO buffer andwritten out on the pins. Data can only be received from the parallel pins (to the USB Tx FIFO interface) when
the parallel interface has been written to.
With Synchronous Bit-Bang mode, data will only be sent out by the FT4232H if there is space in the
FT4232H USB TXFIFO for data to be read from the parallel interface pins. This Synchronous Bit-Bang mode
will read the data bus parallel I/O pins first, before it transmits data from the USB RxFIFO. It is therefore 1
byte behind the output, and so to read the inputs for the byte that you have just sent, another byte must be
sent.
For example :(1) Pins start at 0xFF
Send 0x55,0xAA
Pins go to 0x55 and then to 0xAA
Data read = 0xFF,0x55(2) Pins start at 0xFF
Send 0x55,0xAA,0xAA(repeat the last byte sent)
Pins go to 0x55 and then to 0xAA
Data read = 0xFF,0x55,0xAA
Synchronous Bit-Bang Mode differs from Asynchronous Bit-Bang mode in that the device parallel output isonly read when the parallel output is written to by the USB interface. This makes it easier for the controlling
program to measure the response to a USB output stimulus as the data returned to the USB interface is
synchronous to the output data.
Asynchronous Bit-Bang mode is enabled using Set Bit Bang Mode driver command. A hex value of 1 will
enable Asynchronous Bit-Bang mode.
Synchronous Bit-Bang mode is enabled using Set Bit Bang Mode driver command. A hex value of 4 will
enable Synchronous Bit-Bang mode.
See application note AN2232-02, “Bit Mode Functions for the FT2232” for more details and examples ofusing the bit-bang modes.
An example of the synchronous bi-bang mode timing is shown in Figure 4.5 and Table 4.2.

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Figure 4.5 Synchronous Bit-Bang Mode Timing Interface Example

It should be noted that the FT4232H does not output the WRSTB# or RDSTB# signals when configured in
bit-bang mode. Figure 4.5. and Table 4.2 show these signals for illustration purposes only.

NAME
t1
t2
t3
t4
t5
t6

Description
Current pin state is read
RDSTB# is set inactive and data on the paralle I/O pins is read and sent to the USB host.
RDSTB# is set active again, and any pins that are output will change to their new data
1 clock cycle to allow for data setup
WRSTB# goes active. This indicates that the host PC has written new data to the I/O parallel data
pins
WRSTB# goes inactive

Table 4.2 Synchronous Bit-Bang Mode Timing Interface Example Timings

WRSTB# = this output indicates when new data has been written to the I/O pins from the Host PC (via the

USB interface).
RDSTB# = this output rising edge indicates when data has been read from the I/O pins and sent to the Host
PC (via the USB interface).

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4.6

FT4232H Mode Selection

The 4 channels of the FT4232H reset to 4 asynchronous serial UART interfaces. Following a reset, therequired mode can be configured by sending the FT_SetBitMode command (refer to
D2XX_Programmers_Guide) to the USB driver software.
The EEPROM contents have no effect on the selected mode with the exception of selecting the TXDEN for
RS485 mode when asynchronous serial interface has been selected in software. If the device is reset, thenthe 4 channels must be reconfigured into the required mode.
Note that the mode of each of the 4 channels is independent of the other channels.
The MPSSE can be configured directly using the D2XX commands. The D2XX_Programmers_Guide isavailable from the FTDI website at
http://www.ftdichip.com/Documents/ProgramGuides/D2XX_Programmer's_Guide(FT_000071).pdf
Also the MPSSE command set is fully described in application note AN_108 – “Command Processor For

MPSSE and MCU Host Bus Emulation Modes”.

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5

Devices Characteristics and Ratings

5.1

Absolute Maximum Ratings

The absolute maximum ratings for the FT4232H devices are as follows. These are in accordance with the
Absolute Maximum Rating System (IEC 60134). Exceeding these values may cause permanent damage tothe device.
Parameter

Value

Unit

Storage Temperature-65°C to 150°C

Degrees C

Floor Life (Out of Bag) At Factory Ambient

168 Hours(30°C / 60% Relative Humidity)(IPC/JEDEC J-STD-033A MSL Level 3
Compliant)*

Hours

Ambient Operating Temperature (Power
Applied)-40°C to 85°C

Degrees C

MTTF FT4232HL

TBD

hours

MTTF FT4232HQ

TBD

hours

VCORE Supply Voltage-0.3 to +2.0

V

VCCIO IO Voltage-0.3 to +4.0

V

DC Input Voltage – USBDP and USBDM-0.5 to +3.63

V-0.3 to +5.8

V

DC Input Voltage – All Other Inputs-0.5 to + (VCCIO +0.5)

V

DC Output Current – Outputs

16

mA

DC Input Voltage – High ImpedanceBi-directionals (powered from VCCIO)

Table 5.1 Absolute Maximum Ratings* If devices are stored out of the packaging beyond this time limit the devices should be baked before
use. The devices should be ramped up to a temperature of +125°C and baked for up to 17 hours.

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5.2

DC Characteristics

DC Characteristics (Ambient Temperature = -40°C to +85°C)
Parameter

Description

Minimum

TypicalMaximum

Units

VCORE

VCC Core Operating
Supply Voltage

1.62

1.80

1.98

V

VCCIO*VCCIO Operating
Supply Voltage

2.97

3.30

3.63

V

VREGINVREGIN Voltage
regulator Input

3.00

3.30

3.60

V

VREGOUT

Voltage regulator
Output

1.71

1.80

1.89

V

Ireg

Regulator Current

150

mA

Icc1

Core Operating
Supply Current

---

mA

Icc1r

Core Reset Supply
Current

Icc1s

Core Suspend Supply
Current---70

Conditions

Cells are 5V
tolerant

VREGIN +3.3V
VCORE = +1.8V
Normal Operation
VCORE = +1.8V

---

5

500

---

mA

µA

Device in reset
state.
VCORE = +1.8V
USB Suspend

Table 5.2 Operating Voltage and Current*NOTE: Failure to connect all VCCIO pins will result in failure of the device.

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The I/O pins are +3.3v cells, which are +5V tolerant (except the USB PHY pins).
Parameter

Description

Minimum

Typical

2.40

3.14

Maximum

3.22

0.18

Vil

Input low SwitchingThresholdVihInput High SwitchingThreshold

Vt

Switching Threshold

Rpd

I/O Drive
strength* = 8mAV

I/O Drive
strength* = 12mA

V

I/O Drive
strength* = 16mA

V

Iol = +/-2mA
I/O Drive
strength* = 4mAV

I/O Drive
strength* = 8mAV

I/O Drive
strength* = 12mA

V

I/O Drive
strength* = 16mA

V

LVTTL

-

V

LVTTL

1.50

V

LVTTL

0.07

Rpu

V

Output Voltage Low

0.08

Vt+

Ioh = +/-2mA

0.40

0.12

Vt-

V

Output Voltage High

3.22

Vol

Conditions

I/O Drive
strength* = 4mA

3.20
Voh

Units

Schmitt trigger
negative goingthreshold voltage
Schmitt trigger
positive goingthreshold voltage

Input pull-up
resistance
Input pull-downresistance

Iin

Input Leakage Current

Ioz

Tri-state output
leakage current

-

2.0

0.80

1.10

-

V

1.60

2.0

V

40

75

190

KΩ

Vin = 0

40

75

190

KΩ

Vin =VCCIO

15

45

85

μA

Vin = 0μA

Vin = 5.5V or 0

0.80

+/-10

Table 5.3 I/O Pin Characteristics (except USB PHY pins)*The I/O drive strength and slow slew-rate are configurable in the EEPROM.

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DC Characteristics (Ambient Temperature = -40°C to +85°C)
Parameter

Description

Minimum

TypicalMaximum

Units

Conditions

VPHY,

PHY Operating Supply
Voltage

3.0

3.3

3.6

V

3.3V I/O

PHY Operating Supply
Current

---

30

60

mA

High-speed
operation at 480
MHz

PHY Operating Supply
Current

---

10

50

µA

USB Suspend

TypicalMaximum

Units

Conditions

VPLL
IccphyIccphy(susp)

Table 5.4 PHY Operating Voltage and Current

Parameter

Description

Minimum

Voh

Output Voltage HighVCORE0.2

Vol

Output Voltage Low

Vil

Input low SwitchingThresholdVihInput High SwitchingThreshold

V

-

2.0

-

0.2

V

0.8

V

V

Table 5.5 PHY I/O Pin Characteristics

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6

FT4232H Configurations

The following sections illustrate possible USB power configurations for the FT4232H.
All USB power configurations illustrated apply to both package options for the FT4232H device

6.1

USB Bus Powered Configuration

Bus Powered Application example 1: Bus powered configuration+3.3V+1.8V +1.8V +1.8V +3.3V +3.3V +3.3V +3.3V+3.3V
100nF 100nF 100nF
GND

4.7uF 4.7uF 100nF 100nF
GND

GND

+1.8V

49 VREGOUT

+1.8V

GND

3.3uF

100nF
GND

GND

GND

GND

1
2
3
4

VBUS
DD+
GND

7
8
6
+3.3V

0?

14

DM
DP
REF
RESET#

1K

GND
12K
GND

10K

10K
63
62
61

EECLK
EEDATAEECSEECLKEEDATA

1

3

3

12MHz

13

27pF
GND

GND

OSCO
TEST

51
47
35
25
15
11
5
1

2.2K

GND
GND
GND
GND
GND
GND
GND
GND

CS
VCC
ORG
4
D
Q
93C46
SCL
7
DU
GND

10

5

OSCI

8

AGND

1
6
3
2

16
17
18
19
21
22
23
24

BDBUS0BDBUS1
BDBUS2
BDBUS3
BDBUS4
BDBUS5
BDBUS6
BDBUS7

26
27
28
29
30
32
33
34

DDBUS0DDBUS1
DDBUS2
DDBUS3
DDBUS4
DDBUS5
DDBUS6
DDBUS7

+3.3V
2

GND

ADBUS0ADBUS1ADBUS2
ADBUS3
ADBUS4
ADBUS5ADBUS6ADBUS7

CDBUS0
CDBUS1
CDBUS2
CDBUS3
CDBUS4
CDBUS5
CDBUS6
CDBUS7+3.3V

10K

100nF 100nF 100nF 100nF

GND

GND

GND

+3.3V

56 VCCIO
42 VCCIO
31 VCCIO
20 VCCIO

50 VREGIN

64 VCORE
37 VCORE
12 VCORE

+3.3V

Vin
Vout
GND

100nF

GND

9 VPLLVPHY
4LDO +3.3V

GND

GND

PWREN#SUSPEND#

38
39
40
41
43
44
45
46
48
52
53
54
55
57
58
59
60
36

27pF
GND

GND

Figure 6.1 Bus Powered Configuration Example 1

Figure 6.1 illustrates the FT4232H in a typical USB bus powered design configuration. A USB bus powered
device gets its power from the USB bus. In this application, the FT4232H requires that the VBUS (USB
+5V) is regulated down to +3.3V (using an LDO) to supply the VCCIO, VPLL, VPHY and VREGIN.
VREGIN is the +3.3V input to the on chip +1.8V regulator. The output of the on chip LDO regulator(+1.8V) drives the FT4232H core supply (VCORE). This requires a minimum of a 3.3uF filter capacitor.

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Bus Powered Application example 2: Bus powered configuration (with additional 1.8V LDO voltage
regulator for VCORE)+3.3V+1.8V +1.8V +1.8V +3.3V +3.3V +3.3V +3.3V+3.3V
LDO +1.8V+1.8V

100nF 100nF 100nF

Vin
Vout
GND
100nF

4.7uF 4.7uF 100nF 100nF
GND

100nF

GND

GND

GND

GND

GND

GND

+1.8V

GND

ADBUS0ADBUS1ADBUS2
ADBUS3
ADBUS4
ADBUS5ADBUS6ADBUS7

16
17
18
19
21
22
23
24

BDBUS0BDBUS1
BDBUS2
BDBUS3
BDBUS4
BDBUS5
BDBUS6
BDBUS7

26
27
28
29
30
32
33
34

CDBUS0
CDBUS1
CDBUS2
CDBUS3
CDBUS4
CDBUS5
CDBUS6
CDBUS7

38
39
40
41
43
44
45
46

DDBUS0DDBUS1
DDBUS2
DDBUS3
DDBUS4
DDBUS5
DDBUS6
DDBUS7

48
52
53
54
55
57
58
59

PWREN#SUSPEND#

60
36

100nF
GND

GND

GND

1
2
3
4

7
8
6
+3.3V

14

DM
DP
REF
RESET#

1K

GND
12K
+3.3V
GND

10K

10K

10K
63
62
61

EECLK
EEDATAEECSEECLKEEDATA

+3.3V
2

3
13

27pF
GND

GND

OSCO
TEST

51
47
35
25
15
11
5
1

3
12MHz

1
2.2K

GND
GND
GND
GND
GND
GND
GND
GND

CS
VCC
ORG
4
D
Q
93C46
SCL
7
DU
GND

10

5

OSCI

8

AGND

1
6
3
2

GND

GND

+3.3V

56 VCCIO
42 VCCIO
31 VCCIO
20 VCCIO

100nF

49 VREGOUT

64 VCORE
37 VCORE
12 VCORE

50 VREGIN

9 VPLL
VPHY
4

+3.3V

Vin
Vout
GND

0?

GND

GND
GND
LDO +3.3V

VBUS
DD+
GND

100nF 100nF 100nF 100nF

GND

27pF
GND

GND

Figure 6.2 Bus Powered Configuration Example 2

Figure 6.3 illustrates the FT4232H in a typical USB bus powered configuration similar to Figure 6.1. The
difference here is that the +1.8V for the FT4232H core (VCORE) has been regulated from the VBUS aswell as the +3.3V supply to the VPLL, VPHY, VCCIO and VREGIN.

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6.2

USB Self Powered Configuration

Self Powered application example 1: Self powered configuration+3.3V+1.8V +1.8V +1.8V +3.3V +3.3V +3.3V +3.3V+3.3V
100nF 100nF 100nF
4.7uF
GND

4.7uF
GND

GND

100nF 100nF
GND

GND

+1.8V

49 VREGOUT

GND
100nF

16
17
18
19
21
22
23
24

BDBUS0BDBUS1
BDBUS2
BDBUS3
BDBUS4
BDBUS5
BDBUS6
BDBUS7

26
27
28
29
30
32
33
34

CDBUS0
CDBUS1
CDBUS2
CDBUS3
CDBUS4
CDBUS5
CDBUS6
CDBUS7

38
39
40
41
43
44
45
46

DDBUS0DDBUS1
DDBUS2
DDBUS3
DDBUS4
DDBUS5
DDBUS6
DDBUS7

48
52
53
54
55
57
58
59

PWREN#SUSPEND#

60
36

GND
GND

GND

GND

1
2
3
4

VBUS
DD+
GND

7
8
6

4.7K
14
0?

DM
DP
REF
RESET#

1K

GND

12K

10K
+3.3V

GND
GND

10K

10K

10K
63
62
61

EECLK
EEDATAEECSEECLKEEDATA

+3.3V
2

4

1

3

12MHz

13

27pF
GND

GND

OSCO
TEST

51
47
35
25
15
11
5
1

7

3

GND
GND
GND
GND
GND
GND
GND
GND

2.2K

10

5

CS
VCC
ORG
D
Q
93C46
SCL
DU
GND

OSCI

8
AGND

1
6
3
2

GND

ADBUS0ADBUS1ADBUS2
ADBUS3
ADBUS4
ADBUS5ADBUS6ADBUS7

3.3uF

100nF

GND

GND

GND

+3.3V

56 VCCIO
42 VCCIO
31 VCCIO
20 VCCIO

50 VREGIN

64 VCORE
37 VCORE
12 VCORE+3.3V

9 VPLLVPHY
4LDO +3.3V
Vin
Vout
GND

GND

+1.8V

Ext. Power Supply
1
2

GND

100nF 100nF 100nF 100nF

27pF
GND

GND

Figure 6.3 Self Powered Configuration Example 1

Figure 6.3 illustrates the FT4232H in a typical USB self powered configuration. A USB self powered device
gets its power from its own power supply and does not draw current from the USB bus. In this example
an external power supply is used. This external supply is regulated to +3.3V.
Note that in this set-up, the EEPROM should be configured for self-powered operation.

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Self Powered application example 2: Self powered configuration (with additional 1.8V LDO voltage
regulator for VCORE)+3.3V+1.8V +1.8V +1.8V +3.3V +3.3V +3.3V +3.3V+3.3V
LDO +1.8V+1.8V

100nF 100nF 100nF

Vin
Vout
GND

4.7uF 4.7uF 100nF 100nF

100nF

GND

100nF

GND

Ext. Power Supply

GND

GND

GND

GND

GND

+1.8V

GND

GND

49 VREGOUT

100nF

100nF
GND

GND

GND

VBUS
7
8
6
4.7K
14

0?

DM
DP
REF
RESET#

1K

GND
12K

10K
+3.3V

GND
GND

10K

10K

10K
63
62
61

EECLK
EEDATAEECSEECLKEEDATA

+3.3V
2

1

3
13

27pF
GND

GND

OSCO
TEST

51
47
35
25
15
11
5
1

3
12MHz

GND
GND
GND
GND
GND
GND
GND
GND

2.2K

OSCI

10

5

8
CS
VCC
ORG
4
D
Q
93C46
SCL
7
DU
GND

AGND

1
6
3
2

GND

GND

+3.3V

56 VCCIO
42 VCCIO
31 VCCIO
20 VCCIO

50 VREGIN

64 VCORE
37 VCORE
12 VCORE

+3.3V

Vin
Vout
GND

9 VPLLVPHY
4LDO +3.3V

1
2
3
4

GND

GND
GND

1
2

VBUS
DD+
GND

100nF 100nF 100nF 100nF

GND

ADBUS0ADBUS1ADBUS2
ADBUS3
ADBUS4
ADBUS5ADBUS6ADBUS7

16
17
18
19
21
22
23
24

BDBUS0BDBUS1
BDBUS2
BDBUS3
BDBUS4
BDBUS5
BDBUS6
BDBUS7

26
27
28
29
30
32
33
34

CDBUS0
CDBUS1
CDBUS2
CDBUS3
CDBUS4
CDBUS5
CDBUS6
CDBUS7

38
39
40
41
43
44
45
46

DDBUS0DDBUS1
DDBUS2
DDBUS3
DDBUS4
DDBUS5
DDBUS6
DDBUS7

48
52
53
54
55
57
58
59

PWREN#SUSPEND#

60
36

27pF
GND

GND

Figure 6.4 Self Powered Configuration Example 2

Figure 6.4 illustrates the FT4232H in a typical USB self powered configuration similar to Figure 6.3. The
difference here is that the +1.8V for the FT4232H core has been regulated from the external power
supply.
Note that in this set-up, the EEPROM should be configured for self-powered operation.

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6.3

Oscillator Configuration

FT4232H
27pF
2

OSCI

12MHz
Crystal
27pF
3

OSCO

Figure 6.5 Recommended FT4232H Crystal Oscillator Configuration.

Figure 6.5 illustrates how to connect the FT4232H with a 12MHz ± 0.5% crystal. In this case loading
capacitors should to be added between OSCI, OSCO and GND as shown. A value of 27pF is shown as thecapacitor in the example – this will be good for many crystals but it is recommended to select the loading
capacitor value based on the manufacturer’s recommendations wherever possible. It is recommended to use
a parallel cut type crystal.
It is also possible to use a 12 MHz oscillator with the FT4232H. In this case the output of the oscillator would
drive OSCI, and OSCO should be left unconnected. The oscillator must have a CMOS output drive
capability.

Parameter

Description

Minimum

TypicalMaximum

Units

OSCI Vin

Input Voltage

2.97

3.30

3.63

V

FIn

Input Frequency

12

MHz

Ji

Cycle to cycle jitter

< 150

pS

Conditions+/- 30ppm

Table 6.1 OSCI Input characteristics

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6.4

4 Channel Transmit and Receiver LED Indication Example

The following example illustrates how a 74HCT595 can be used to decode the EEDATA data to indicate Tx
and Rx on each of the channels. The associated LED will light when the Channel is transmitting or
receiving data.

Figure 6.6 Using 74HCT595 to Indicate Tx and Rx Data

In this configuration, the LEDs will flash when the EEPROM is accessed. For example during enumeration.
Under normal operation, the EECS is held low to disable access to the EEPROM. In this special case, the
EECLK will clock the EEDATA into the 74HCT595 shift register (with EECS low, therefore EEPROM ignoresthe EEDATA). Then EECS will pulse high. The rising edge of the EECS latches the data into a storage
register of the 74HCT595 which drives the LEDs.
Please refer to the 74HCT595 datasheet for further explanation.

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7

EEPROM Configuration

If an external EEPROM is fitted (93LC46/56/66) it can be programmed over USB using MPROG V3.4a or later. The
EEPROM must be 16 bits wide and capable or working at a VCC supply of +3.0 to +3.6 volts.

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8

Package Parameters

The FT4232H is available in two different packages. The FT4232HL is the LQFP-64 option and theFT4232HQ is the QFN-64 package option. The solder reflow profile for both packages is described in
Section 8.3

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8.1

FT4232HQ, QFN-64 Package Dimensions

Notes
1. All dimensions are in mm.
2. Pin 1 ID can be combination of DOT AND/OR Chamfer.
3. Pin 1 ID is NOT connected to the internal ground of the device. It is internally connected to the bottom side
central solder pad, which is 4.35 x 4.35mm.
4. Pin 1 ID can be connected to system ground, but it is not recommended using this as a ground point forthe device.
5. Optional Chamfer on corner leads.
Figure 8.1 64 pin QFN Package Details

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8.2

FT4232HL, LQFP-64 Package Dimensions
Top View
64

49

1

48
Line 1– FTDI Logo

FTDI
Indicates Pin#1 (Laser
Marked)16

10.000+/- 0.1

YYWW-AXXXXXXXXXXXX
FT4232HLLine 2– Date Code and RevisionLine 3– Wafer Lot NumberLine 4– FTDI Part Number

33
17

32

Dimensions are bodydimensions (mm)10.000+/- 0.1
D
D1
64

49

48

16

33

E1

1

E

17

e

32

1.0
o

+/- 1

o

b

1 . 4 + /- 0 . 0 5

1.6 0

MAX

12

0.05 Min
0.15 Max

c

c1

0.25

b1

0.2 Min
0.6+/- 0.15

Figure 8.2 64 pin LQFP Package Details

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SYMBOL

MIN

NOM

MAX

D

11.8

12

12.2

D1

9.9

10

10.1

E

11.8

12

12.2

E1

9.9

10

10.1

b

0.17

0.22

0.27

c

0.09

b1

0.17

c1

0.09

e

0.2
0.2

0.23
0.16

0.5 BSC

Table 8.1 64 pin LQFP Package Details – dimensions (in mm)

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8.3

Solder Reflow Profile

Figure 8.3 64 pin LQFP and QFN Reflow Solder Profile

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Pb Free Solder Process

SnPb Eutectic and Pb free (non(green material)

green material) Solder Process

3°C / second Max.

3°C / Second Max.

Profile Feature

Average Ramp Up Rate (Ts to Tp)

Preheat- Temperature Min (Ts Min.)

150°C

100°C

- Temperature Max (Ts Max.)

200°C

150°C

- Time (ts Min to ts Max)

60 to 120 seconds

60 to 120 seconds

217°C

183°C

60 to 150 seconds

60 to 150 seconds

260°C

see Table 8.3

30 to 40 seconds

20 to 40 seconds

Ramp Down Rate

6°C / second Max.

6°C / second Max.

Time for T= 25°C to Peak Temperature, Tp

8 minutes Max.

6 minutes Max.

Package Thickness

Volume mm3 < 350

Volume mm3 >=350< 2.5 mm

235 +5/-0 deg C

220 +5/-0 deg C≥ 2.5 mm

220 +5/-0 deg C

220 +5/-0 deg C

Time Maintained Above Critical Temperature
TL:- Temperature (TL)
- Time (tL)Peak Temperature (Tp)
Time within 5°C of actual Peak Temperature(tp)

Table 8.2 Reflow Profile Parameter Values

SnPb Eutectic and Pb free (non green material)

Pb Free (green material) = 260 +5/-0 deg C

Table 8.3 Package Reflow Peak Temperature

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9

Contact Information

Head Office – Glasgow, UK
Future Technology Devices International Limited
Unit 1, 2 Seaward Place,
Glasgow G41 1HH
United Kingdom
Tel: +44 (0) 141 429 2777
Fax: +44 (0) 141 429 2758
E-mail (Sales)
vinculum.sales@ftdichip.com
E-mail (Support) vinculum.support@ftdichip.com
E-mail (General Enquiries) admin1@ftdichip.com
Web Site URL
http://www.ftdichip.com
Web Shop URL http://www.ftdichip.com

Branch Office – Taipei, Taiwan
Future Technology Devices International Limited (Taiwan)
2F, No. 516, Sec. 1, NeiHu Road
Taipei 114
Taiwan , R.O.C.
Tel: +886 (0) 2 8797 1330
Fax: +886 (0) 2 8751 9737
E-mail (Sales)
tw.sales1@ftdichip.com
tw.support1@ftdichip.com
E-mail (Support)
E-mail (General Enquiries) tw.admin1@ftdichip.com
Web Site URL
http://www.ftdichip.com

Branch Office – Hillsboro, Oregon, USA
Future Technology Devices International Limited (USA)7235 NW Evergreen Parkway, Suite 600
Hillsboro, OR 97123-5803
USA
Tel: +1 (503) 547 0988
Fax: +1 (503) 547 0987
E-Mail (Sales)
E-Mail (Support)
Web Site URL

us.sales@ftdichip.com
us.admin@ftdichip.com
http://www.ftdichip.com

Branch Office – Shanghai, China

Future Technology Devices International Limited (China)
Room 408, 317 Xianxia Road,
ChangNing District,
ShangHai, China
Tel: +86 (21) 62351596
Fax: +86(21) 62351595
E-Mail (Sales): cn.sales@ftdichip.com
E-Mail (Support): cn.support@ftdichip.com
E-Mail (General Enquiries): cn.admin1@ftdichip.com
Web Site URL: http://www.ftdichip.com
Distributor and Sales Representatives
Please visit the Sales Network page of the FTDI Web site for the contact details of our distributor(s) and sales
representative(s) in your country.

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Appendix A - List of Figures and Tables
List of Tables
Table 3.1 FT4232H Pin Configurations ....................................................................................... 9
Table 3.2 Power and Ground ........................................................................................................ 10
Table 3.3 Common Function pins .................................................................................................. 11
Table 3.4 EEPROM Interface Group ............................................................................................... 11
Table 3.5 Channel A,B,C and Channel D Asynchronous Serial Interface Configured Pin Descriptions ...... 12
Table 3.6 Channel A,B,C and Channel D Synchronous or Asynchronous Bit-Bang Configured Pin
Descriptions ............................................................................................................................. 13
Table 3.7 Channel A and Channel B MPSSE Configured Pin Descriptions .................................. 14
Table 4.1 MPSSE Signal Timings ................................................................................................... 20
Table 4.2 Synchronous Bit-Bang Mode Timing Interface Example Timings .......................................... 22
Table 5.1 Absolute Maximum Ratings ............................................................................................ 24
Table 5.2 Operating Voltage and Current .............................................................................................. 25
Table 5.3 I/O Pin Characteristics (except USB PHY pins) .................................................................. 26
Table 5.4 PHY Operating Voltage and Current ................................................................................. 27
Table 5.5 PHY I/O Pin Characteristics ............................................................................................ 27
Table 6.1 OSCI Input characteristics ............................................................................................. 32
Table 8.1 64 pin LQFP Package Details – dimensions (in mm)........................................................... 38
Table 8.2 Reflow Profile Parameter Values ..................................................................................... 40
Table 8.3 Package Reflow Peak Temperature .................................................................................. 40

List of Figures
Figure 2.1 FT4232H Block Diagram ................................................................................................. 4
Figure 3.1 FT4232H Schematic Symbol ...................................................................................... 7
Figure 4.1 RS232 Configuration .................................................................................................... 17
Figure 4.2 Dual RS422 Configuration ............................................................................................. 18
Figure 4.3 Dual RS485 Configuration ............................................................................................. 19
Figure 4.4 MPSSE Signal Waveforms ............................................................................................. 20
Figure 4.5 Synchronous Bit-Bang Mode Timing Interface Example .................................................... 22
Figure 6.1 Bus Powered Configuration Example 1............................................................................ 28
Figure 6.2 Bus Powered Configuration Example 2............................................................................ 29
Figure 6.3 Self Powered Configuration Example 1 ........................................................................... 30
Figure 6.4 Self Powered Configuration Example 2 ........................................................................... 31
Figure 6.5 Recommended FT4232H Crystal Oscillator Configuration. ................................................. 32
Figure 6.6 Using 74HCT595 to Indicate Tx and Rx Data ................................................................... 33
Figure 8.1 64 pin QFN Package Details .......................................................................................... 36
Figure 8.2 64 pin LQFP Package Details ......................................................................................... 37
Figure 8.3 64 pin LQFP and QFN Reflow Solder Profile ..................................................................... 39

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Appendix B - Revision History
Revision History
Version draftInitial Datasheet Created

October 2008

Version Preliminary

Preliminary Datasheet Released

23rd October 2008

Version 1.00

Datasheet Released

4th November 2008

Version 1.10

QFN package update

November 2008

Version 2.00

Various Updates

January 2009

Version 2.01

Changed description of bit-bang mode

February 2009

Version 2.02

Corrected QFN tray numbers from 160 to 260 per tray

March 2009

Version 2.03

Corrected signal names in Fig 2.1
Added reference to AN_109, AN_110, AN_111 and AN_113.

19th May 2009

Corrected default of RI#/ TXDEN in table 3.1
Version 2.04

Added paragraph on latency timer to section 4.1

3rd June 2009

Version 2.05

Corrected Figures 6.2, 6.3 and 6.4 – missing regulators and better way

17th June 2009of holding self powered designs in reset if not connected to USB.
Corrected Max DC inputs on “DC Input Voltage –“All Other Inputs” pins from VCORE+0.5V to VCCIO+0.5V

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