3.3 VOLT CMOS SyncFIFO™
IDT72V201, IDT72V211
256 x 9, 512 x 9,
IDT72V221, IDT72V231
1,024 x 9, 2,048 x 9,
IDT72V241, IDT72V251
4,096 x 9 and 8,192 x 9
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018

FEATURES:

are very high-speed, low-power First-In, First-Out (FIFO) memories withclocked read and write controls. The architecture, functional operation and pin
assignments are identical to those of the IDT72201/72211/72221/72231/
72241/72251, but operate at a power supply voltage (Vcc) between 3.0V and
3.6V. These devices have a 256, 512, 1,024, 2,048, 4,096 and 8,192 x 9bit memory array, respectively. These FIFOs are applicable for a wide variety
of data buffering needs such as graphics, local area networks and interprocessor
communication.
These FIFOs have 9-bit input and output ports. The input port iscontrolled by a free-running clock (WCLK), and two Write Enable pins
(WEN1, WEN2). Data is written into the Synchronous FIFO on every
rising clock edge when the Write Enable pins are asserted. The output
port is controlled by another clock pin (RCLK) and two Read Enable pins
(REN1, REN2). The Read Clock can be tied to the Write Clock for single
clock operation or the two clocks can run asynchronous of one anotherfor dual-clock operation. An Output Enable pin (OE) is provided on theread port for three-state control of the output.
The Synchronous FIFOs have two fixed flags, Empty (EF) and Full (FF).
Two programmable flags, Almost-Empty (PAE) and Almost-Full (PAF), areprovided for improved system control. The programmable flags default to
Empty+7 and Full-7 for PAE and PAF, respectively. The programmable flag
offset loading is controlled by a simple state machine and is initiated by asserting
the Load pin (LD).
These FIFOs are fabricated using high-speed submicron CMOS
technology.

• 256 x 9-bit organization IDT72V201• 512 x 9-bit organization IDT72V211• 1,024 x 9-bit organization IDT72V221• 2,048 x 9-bit organization IDT72V231• 4,096 x 9-bit organization IDT72V241• 8,192 x 9-bit organization IDT72V251• 10 ns read/write cycle time
• 5V input tolerant• Read and Write clocks can be independent• Dual-Ported zero fall-through time architecture• Empty and Full Flags signal FIFO status• Programmable Almost-Empty and Almost-Full flags can be set toany depth• Programmable Almost-Empty and Almost-Full flags default to

Empty+7, and Full-7, respectively• Output Enable puts output data bus in high-impedance state• Advanced submicron CMOS technology• Available in 32-pin plastic leaded chip carrier (PLCC) and 32-pin

plastic Thin Quad FlatPack (TQFP)°C to +85°°C) is available• Industrial temperature range (–40°• Green parts available, see ordering information

DESCRIPTION:

The IDT72V201/72V211/72V221/72V231/72V241/72V251 SyncFIFOs™

FUNCTIONAL BLOCK DIAGRAM
D0 - D8

WCLK
WEN1

LD

WEN2
INPUT REGISTEROFFSET REGISTER
EF
PAE
PAF
FF

FLAG
LOGIC

WRITE CONTROLLOGICRAM ARRAY
256 x 9, 512 x 9,
1,024 x 9, 2,048 x 9,
4,096 x 9, 8,192 x 9

WRITE POINTERREAD POINTERREAD CONTROLLOGICOUTPUT REGISTERRESET LOGIC
RCLK
REN1
REN2
RS
OE

4092 drw 01

Q0 - Q8

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGESMARCH 2018

1
DSC-4092/7

COMMERCIAL AND INDUSTRIALTEMPERATURE RANGES

IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™
256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9

D1

1

24

WEN1

D0

2

23

WCLK

PAF

3

22

WEN2/LD

PAE

4

21

VCC

GND

5

20

Q8

19

Q7
Q6
Q5

WCLK
WEN1

WEN2/LD

Q0-Q8
RCLK
REN1
REN2
OE
EF
PAE
PAF
FF

VCC
GND

D8

D7

D6

D5

27

WCLK

PAE

8

26

WEN2/LD

GND

9

25

VCC

REN1

10

24

Q8

RCLK

11

23

Q7

REN2

12

22

Q6

OE

13

21

Q5

Q4

4092 drw02a

PLCC (J32-1, order code: J)
TOP VIEWPIN DESCRIPTIONS
RS

7

EF

Q4

Q3

TQFP (PR32-1, order code: PF)
TOP VIEW

Symbol
D0-D8

WEN1

PAF

14 15 16 17 18 19 204092 drw02

Q2

Q1

Q0

FF

OE
EF

9 10 11 12 13 14 15 16

RS

28

D0

Q3

8

17

32 31 30
1

Q2

18

2

Q1

REN2

7

3

6

5

Q0

RCLK

6

4

29

D1

FF

REN1

D4

32 31 30 29 28 27 26 25

D3

INDEX

D2

RS

D8

D7

D6

D5

D4

INDEX

D3

D2

PIN CONFIGURATION

Name
Data Inputs
Reset

I/O
Description
I Data inputs for a 9-bit bus.
I When RS is set LOW, internal read and write pointers are set to the first location of the RAM array, FF
and PAF go HIGH, and PAE and EF go LOW. A Reset is required before an initial Write after power-up.
Write ClockI Data is written into the FIFO on a LOW-to-HIGH transition of WCLK when the Write Enable(s) are asserted.
Write Enable 1
I If the FIFO is configured to have programmable flags, WEN1 is the only Write Enable pin. When WEN1 is
LOW, data is written into the FIFO on every LOW-to-HIGH transition WCLK. If the FIFO is configured tohave two write enables, WEN1 must be LOW and WEN2 must be HIGH to write data into the FIFO. Data
will not be written into the FIFO if the FF is LOW.
Write Enable 2/
I The FIFO is configured at Reset to have either two write enables or programmable flags. If WEN2/LD
Load
is HIGH at Reset, this pin operates as a second write enable. If WEN2/LD is LOW at Reset, this pin operates
as a control to load and read the programmable flag offsets. If the FIFO is configured to have two write
enables, WEN1 must be LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written
into the FIFO if the FF is LOW. If the FIFO is configured to have programmable flags, WEN2/LD is held LOW towrite or read the programmable flag offsets.
Data Outputs
O Data outputs for a 9-bit bus.
Read ClockI Data is read from the FIFO on a LOW-to-HIGH transition of RCLK when REN1 and REN2 are asserted.
Read Enable 1
I When REN1 and REN2 are LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK. Data
will not be read from the FIFO if the EF is LOW.
Read Enable 2
I When REN1 and REN2 are LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK.
AND INDUSTRIAL
Data will not be read from the FIFO if the EF is COMMERCIALLOW.
TEMPERATURE RANGES
Output Enable
I When OE is LOW, the data output bus is active. If OE is HIGH, the output data bus will be in a high-impedancestate.
Empty FlagO When EF is LOW, the FIFO is empty and further data reads from the output are inhibited. When EF is
HIGH, the FIFO is not empty. EF is synchronized to RCLK.
Programmable
O When PAE is LOW, the FIFO is almost-empty based on the offset programmed into the FIFO. The default
Almost-Empty Flag
offset at reset is Empty+7. PAE is synchronized to RCLK.
Programmable
O When PAF is LOW, the FIFO is almost-full based on the offset programmed into the FIFO. The default
Almost-Full Flag
offset at reset is Full-7. PAF is synchronized to WCLK.
Full FlagO When FF is LOW, the FIFO is full and further data writes into the input are inhibited. When FF is HIGH, the FIFO
is not full. FF is synchronized to WCLK.
Power
One 3.3V volt power supply pin.
GroundOne 0 volt ground pin.
2

COMMERCIAL AND INDUSTRIALTEMPERATURE RANGES

IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™
256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9

RECOMMENDED OPERATING
CONDITIONSABSOLUTE MAXIMUM RATINGS(1)SymbolVTERM(2)Com'l & Ind'l–0.5 to +5

TSTG

RatingTerminal Voltage with
Respect to GND
Storage Temperature

Unit
V–55 to +125

°C

IOUT

DC Output Current–50 to +50

mA

Symbol
VCC

Parameter
Supply Voltage
Commercial/Industrial
Supply Voltage
Input High Voltage
Commercial/Industrial
Input Low Voltage
Commercial/Industrial

Min.
3.0

Typ.
3.3

Max.
3.6

Unit
V

0
2.0

0
—

0
5.5

V
V

-0.5

—

0.8

V

TA

Operating Temperature
Commercial

0

—

70

°C

TA

Operating TemperatureIndustrial

-40

—

85

°C

GND
VIH

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operationof the device at these or any other conditions above those indicated in the operational
sections of the specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. VCC terminal only.

VIL

DC ELECTRICAL CHARACTERISTICS(Commercial: VCC = 3.3V ± 0.3V, TA = 0°C to +70°C;Industrial: VCC = 3.3V ± 0.3V, TA = -40°C to +85°C)

ParameterMin.

IDT72V201
IDT72V211
IDT72V221
IDT72V231
IDT72V241
IDT72V251
Commercial and Industrial(1)tCLK = 10, 15, 20 ns
Typ.

ILI

Input Leakage Current (Any Input)

–1

—

1

μA

ILO(3)

Output Leakage Current

–10

—

10

μA

VOH

Output Logic “1” Voltage, IOH = –2mA

2.4

—

—

V

VOL

Symbol
(2)

Max.

Unit

Output Logic “0” Voltage, IOL = 8mA

—

—

0.4

V

(4,5,6)

Active Power Supply Current

—

—

20

mA

(4,7)

Standby Current

—

—

5

mA

ICC1
ICC2

NOTES:
1. Industrial temperature range product for the 15ns speed grade is available as a standard device. All other speed grades are available by special order.
2. Measurements with 0.4 ≤ VIN ≤ VCC.
3. OE ≥ VIH, 0.4 ≤ VOUT ≤ VCC.
4. Tested with outputs disabled (IOUT = 0).
5. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz.
6. Typical ICC1 = 0.17 + 0.48*fS + 0.02*CL*fS (in mA) with VCC = 3.3V, TA = 25°C, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at fS/2,
CL = capacitive load (in pF).
7. All Inputs = VCC - 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.

CAPACITANCE (TA = +25°C, f = 1.0MHz)
SymbolCIN(2)

Parameter
Input CapacitanceConditions
VIN = 0V

Max.
10

Unit
pF

COUT(1,2)

Output Capacitance

VOUT = 0V

10

pF

NOTES:
1. With output deselected (OE ≥ VIH).
2. Characterized values, not currently tested.

3

COMMERCIAL AND INDUSTRIALTEMPERATURE RANGES

IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™
256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9

AC ELECTRICAL CHARACTERISTICS(1)(Commercial: VCC = 3.3 ±0.3V, TA = 0°C to + 70°C;Industrial: VCC = 3.3 ±0.3V, TA = -40°C to + 85°C)

SymbolfS

Parameter
Clock Cycle Frequency

Commercial
IDT72V201L10
IDT72V211L10
IDT72V221L10
IDT72V231L10
IDT72V241L10
IDT72V251L10
Min.
Max.
—
100

Com'l & Ind'l(2)IDT72V201L15
IDT72V211L15
IDT72V221L15
IDT72V231L15
IDT72V241L15
IDT72V251L15
Min.
Max.
—
66.7

Commercial
IDT72V201L20
IDT72V211L20
IDT72V221L20
IDT72V231L20
IDT72V241L20
IDT72V251L20
Min.
Max.
—
50

Unit
MHz

tA

Data Access Time

2

6.5

2

10

2

12

ns

tCLK

Clock Cycle Time

10

—

15

—

20

—

ns

tCLKH

Clock High Time

4.5

—

6

—

8

—

ns

tCLKL

Clock Low Time

4.5

—

6

—

8

—

ns

tDS

Data Setup Time

3

—

4

—

5

—

ns

tDH

Data Hold Time

0.5

—

1

—

1

—

ns

tENS

Enable Setup Time

3

—

4

—

5

—

ns

tENH

Enable Hold Time

0.5

—

1

—

1

—

ns

tRS

Reset Pulse Width(1)

10

—

15

—

20

—

ns

tRSS

Reset Setup Time

8

—

10

—

12

—

ns

tRSR

Reset Recovery Time

8

—

10

—

12

—

ns

tRSF

Reset to Flag and Output Time

—

10

—

15

—

20

ns

tOLZ

Output Enable to Output in Low-Z(3)

0

—

0

—

0

—

ns

tOE

Output Enable to Output Valid

3

—

3

8

3

10

ns

tOHZ

Output Enable to Output in High-Z(3)

3

—

3

8

3

10

ns

tWFF

Write Clock to Full Flag

—

6.5

—

10

—

12

ns

tREF

Read Clock to Empty Flag

—

6.5

—

10

—

12

ns

tAF

Write Clock to Almost-Full Flag

—

6.5

—

10

—

12

ns

tAE

Read Clock to Almost-Empty Flag

—

6.5

—

10

—

12

ns

tSKEW1

Skew time between Read Clock & Write
Clock for Empty Flag &Full Flag

5

—

6

—

8

—

ns

tSKEW2

Skew time between Read Clock & Write
Clock for Almost-Empty Flag &Almost-Full Flag

14

—

18

—

20

—

ns

NOTES:
1. Pulse widths less than minimum values are not allowed.
2. Industrial temperature range is available by special order for speed grades faster than 15ns.
3. Values guaranteed by design, not currently tested.

3.3V

COMMERCIAL AND INDUSTRIALTEMPERATURE RANGES330Ω
D.U.T.

AC TEST CONDITIONSIn Pulse Levels

Input Rise/Fall Times

3ns

Input Timing Reference Levels

1.5V

Output Reference Levels

1.5V

Output Load510Ω

GND to 3.0V

30pF*

4092 drw03

or equivalent circuit

See Figure 1

Figure 1. Output Load

*Includes jig and scope capacitances.
4

COMMERCIAL AND INDUSTRIALTEMPERATURE RANGES

IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™
256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9

SIGNAL DESCRIPTIONSOUTPUT ENABLE (OE)
When Output Enable (OE) is enabled (LOW), the parallel output buffers
receive data from the output register. When Output Enable (OE) is disabled(HIGH), the Q output data bus is in a high-impedance state.

INPUTS:DATA IN (D0 - D8)
Data inputs for 9-bit wide data.

WRITE ENABLE 2/LOAD (WEN2/LD)
This is a dual-purpose pin. The FIFO is configured at Reset to haveprogrammable flags or to have two write enables, which allows depth expansion.
If Write Enable 2/Load (WEN2/LD) is set high at Reset (RS = LOW), this pin
operates as a second Write Enable pin.
If the FIFO is configured to have two write enables, when Write Enable(WEN1) is LOW and Write Enable 2/Load (WEN2/LD) is HIGH, data can beloaded into the input register and RAM array on the LOW-to-HIGH transitionof every Write Clock (WCLK). Data is stored in the RAM array sequentially andindependently of any on-going read operation.
In this configuration, when Write Enable (WEN1) is HIGH and/or Write
Enable 2/Load (WEN2/LD) is LOW, the input register holds the previous dataand no new data is allowed to be loaded into the register.
To prevent data overflow, the Full Flag (FF) will go LOW, inhibiting further
write operations. Upon the completion of a valid read cycle, the Full Flag (FF)will go HIGH after tWFF, allowing a valid write to begin. Write Enable 1 (WEN1)and Write Enable 2/Load (WEN2/LD) are ignored when the FIFO is full.
The FIFO is configured to have programmable flags when the Write Enable
2/Load (WEN2/LD) is set LOW at Reset (RS = LOW). The IDT72V201/72V211/
72V221/72V231/72V241/72V251 devices contain four 8-bit offset registers
which can be loaded with data on the inputs, or read on the outputs. See Figure
3 for details of the size of the registers and the default values.
If the FIFO is configured to have programmable flags when the Write Enable
1 (WEN1) and Write Enable 2/Load (WEN2/LD) are set low, data on the inputs
D is written into the Empty (Least Significant Bit) Offset register on the first LOWto-HIGH transition of the Write Clock (WCLK). Data is written into the Empty (Most
Significant Bit) Offset register on the second LOW-to-HIGH transition of the Write
Clock (WCLK), into the Full (Least Significant Bit) Offset register on the third
transition, and into the Full (Most Significant Bit) Offset register on the fourthtransition. The fifth transition of the Write Clock (WCLK) again writes to the Empty(Least Significant Bit) Offset register.
However, writing all offset registers does not have to occur at one time. One
or two offset registers can be written and then by bringing the Write Enable 2/
Load (WEN2/LD) pin HIGH, the FIFO is returned to normal read/write
operation. When the Write Enable 2/Load (WEN2/LD) pin is set LOW, and Write
Enable 1 (WEN1) is LOW, the next offset register in sequence is written.
The contents of the offset registers can be read on the output lines when the
Write Enable 2/Load (WEN2/LD) pin is set low and both Read Enables (REN1,
REN2) are set LOW. Data can be read on the LOW-to-HIGH transition of theRead Clock (RCLK).
A read and write should not be performed simultaneously to the offset
registers.

CONTROLS:RESET (RS)Reset is accomplished whenever the Reset (RS) input is taken to a LOW state.
During reset, both internal read and write pointers are set to the first location.
A reset is required after power-up before a write operation can take place. The
Full Flag (FF) and Programmable Almost-Full Flag (PAF) will be reset to HIGH
after tRSF. The Empty Flag (EF) and Programmable Almost-Empty Flag (PAE)
will be reset to LOW after tRSF. During reset, the output register is initialized to
all zeros and the offset registers are initialized to their default values.
WRITE CLOCK (WCLK)
A write cycle is initiated on the LOW-to-HIGH transition of the Write Clock(WCLK). Data setup and hold times must be met in respect to the LOW-to-HIGH
transition of the Write Clock (WCLK). The Full Flag (FF) and Programmable
Almost-Full Flag (PAF) are synchronized with respect to the LOW-to-HIGH
transition of the Write Clock (WCLK).
The Write and Read clocks can be asynchronous or coincident.
WRITE ENABLE 1 (WEN1)
If the FIFO is configured for programmable flags, Write Enable 1 (WEN1)
is the only enable control pin. In this configuration, when Write Enable 1 (WEN1)
is low, data can be loaded into the input register and RAM array on the LOWto-HIGH transition of every Write Clock (WCLK). Data is stored in the RAM arraysequentially and independently of any on-going read operation.
In this configuration, when Write Enable 1 (WEN1) is HIGH, the input registerholds the previous data and no new data is allowed to be loaded into the register.
If the FIFO is configured to have two write enables, which allows for depth
expansion, there are two enable control pins. See Write Enable 2 paragraphbelow for operation in this configuration.
To prevent data overflow, the Full Flag (FF) will go LOW, inhibiting further
write operations. Upon the completion of a valid read cycle, the Full Flag (FF)will go HIGH after tWFF, allowing a valid write to begin. Write Enable 1 (WEN1)
is ignored when the FIFO is full.
READ CLOCK (RCLK)
Data can be read on the outputs on the LOW-to-HIGH transition of the Read
Clock (RCLK). The Empty Flag (EF) and Programmable Almost-Empty Flag
(PAE) are synchronized with respect to the LOW-to-HIGH transition of the Read
Clock (RCLK).
The Write and Read clocks can be asynchronous or coincident.
READ ENABLES (REN1, REN2)
When both Read Enables (REN1, REN2) are LOW, data is read from the
RAM array to the output register on the LOW-to-HIGH transition of the Read
Clock (RCLK).
When either Read Enable (REN1, REN2) is HIGH, the output register holds
the previous data and no new data is allowed to be loaded into the register.
When all the data has been read from the FIFO, the Empty Flag (EF) will go
LOW, inhibiting further read operations. Once a valid write operation has beenaccomplished, the Empty Flag (EF) will go HIGH after tREF and a valid read canbegin. The Read Enables (REN1, REN2) are ignored when the FIFO is empty.

WCLK

Selection

LD

WEN1

0

0

Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)

0

1

No Operation

1

0

Write Into FIFO

1

1

No Operation

NOTES:
1. For the purposes of this table, WEN2 = VIH.
2. The same selection sequence applies to reading from the registers. REN1 and REN2
are enabled and read is performed on the LOW-to-HIGH transition of RCLK.

Figure 2. Write Offset Register
5

COMMERCIAL AND INDUSTRIALTEMPERATURE RANGES

IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™
256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
IDT72V201 - 256 x 9-BIT
8

7

8

0

7

Default Value 007H

Default Value 007H

Default Value 007H

7

0

8

8

8

(MSB)

0

00
0

7

8

7

0

Full Offset (LSB) Reg.

Full Offset (LSB) Reg.

Default Value 007H

Default Value 007H

Default Value 007H

0

8

7

0

1

8

8

(MSB)

0

00

IDT72V251 - 8,192 x 9-BIT
0

7

8

0

7

Empty Offset (LSB) Reg.

Empty Offset (LSB)

Empty Offset (LSB)

Default Value 007H

Default Value 007H

Default Value 007H

0

2

8

0

1

(MSB)

IDT72V241 - 4,096 x 9-BIT
0

0

1

(MSB)

Full Offset (LSB)

0

3

8

0

4

(MSB)

(MSB)

(MSB)

000

0000

00000

7

0

8

Full Offset (LSB) Reg.
Default Value 007H
8

0

1

IDT72V231 - 2,049 x 9-BIT

80
Empty Offset (LSB) Reg.

0

8

7

Empty Offset (LSB)

8

8

8

Empty Offset (LSB) Reg.
88

IDT72V221 - 1,024 x 9-BIT

IDT72V211 - 512 x 9-BIT
0

0

2

0

7

8

0

7

Full Offset (LSB)

Full Offset (LSB)

Default Value 007H

Default Value 007H

8

0

3

8

0

4

(MSB)

(MSB)

(MSB)

000

0000

00000
4092 drw 05

Figure 3. Offset Register Location and Default Values

COMMERCIAL AND INDUSTRIALTEMPERATURE RANGES

6

COMMERCIAL AND INDUSTRIALTEMPERATURE RANGES

IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™
256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9

OUTPUTS:

IDT72V221, (2,048-m) writes for the IDT72V231, (4,096-m) writes for the
IDT72V241 and (8,192-m) writes for the IDT72V251. The offset “m” is definedin the Full Offset registers.
If there is no full offset specified, the Programmable Almost-Full flag (PAF)
will go LOW at Full-7 words.
The Programmable Almost-Full flag (PAF) is synchronized with respect to
the LOW-to-HIGH transition of the Write Clock (WCLK).

FULL FLAG (FF)The Full Flag (FF) will go LOW, inhibiting further write operation, when thedevice is full. If no reads are performed after Reset (RS), the Full Flag (FF)will go LOW after 256 writes for the IDT72V201, 512 writes for the IDT72V211,
1,024 writes for the IDT72V221, 2,048 writes for the IDT72V231, 4,096 writes
for the IDT72V241 and 8,192 writes for the IDT72V251.
The Full Flag (FF) is synchronized with respect to the LOW-to-HIGH
transition of the Write Clock (WCLK).

PROGRAMMABLE ALMOST-EMPTY FLAG (PAE)The Programmable Almost-Empty flag (PAE) will go LOW when the readpointer is "n+1" locations less than the write pointer. The offset "n" is definedin the Empty Offset registers. If no reads are performed after Reset theProgrammable Almost-Empty flag (PAE) will go HIGH after "n+1" for the
IDT72V201/72V211/72V221/72V231/72V241/72V251.
If there is no empty offset specified, the Programmable Almost-Empty flag
(PAE) will go LOW at Empty+7 words.
The Programmable Almost-Empty flag (PAE) is synchronized with respect
to the LOW-to-HIGH transition of the Read Clock (RCLK).

EMPTY FLAG (EF)The Empty Flag (EF) will go LOW, inhibiting further read operations, when
the read pointer is equal to the write pointer, indicating the device is empty.
The Empty Flag (EF) is synchronized with respect to the LOW-to-HIGH
transition of the Read Clock (RCLK).
PROGRAMMABLE ALMOST-FULL FLAG (PAF)
The Programmable Almost-Full flag (PAF) will go LOW when the FIFO
reaches the almost-full condition. If no reads are performed after Reset (RS),the Programmable Almost-Full flag (PAF) will go LOW after (256-m) writes for
the IDT72V201, (512-m) writes for the IDT72V211, (1,024-m) writes for the

DATA OUTPUTS (Q0 - Q8)
Data outputs for a 9-bit wide data.

TABLE 1 — STATUS FLAGS
IDT72V201

NUMBER OF WORDS IN FIFO
IDT72V211

IDT72V221

FF

PAF

PAE

EF

0
1 to n(1)(n+1) to (256-(m+1))

0
1 to n(1)(n+1) to (512-(m+1))

0
1 to n(1)(n+1) to (1,024-(m+1))

H
H
H

H
H
H

L
L
H

L
H
H

(256-m)(2) to 255(512-m)(2) to 511(1,024-m)(2) to 1,023

H

L

H

H

256

512

1,024

L

L

H

H

NUMBER OF WORDS IN FIFO
IDT72V231

IDT72V241

IDT72V251

FF

PAF

PAE

EF

0

0

0

H

H

L

L

H

H

L

H

1 to n(1)

1 to n(1)

1 to n(1)(n+1) to (2,048-(m+1))(n+1) to (4,096-(m+1))(n+1) to (8,192-(m+1))

H

H

H

H

(2)

(2,048-m) to 2,047(2)(4,096-m) to 4,095(2)(8,192-m) to 8,191

H

L

H

H

2,048

4,096

8,192

L

L

H

H

NOTES:
1. n = Empty Offset (n = 7 default value)
2. m = Full Offset (m = 7 default value)

7

COMMERCIAL AND INDUSTRIALTEMPERATURE RANGES

IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™
256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
tRS
RS
tRSS

tRSR

tRSS

tRSR

tRSS

tRSR

REN1,
REN2
WEN1

WEN2/LD (1)tRSF
EF, PAEtRSFFF, PAFtRSFOE = 1(2)

Q0 - Q8
OE = 04092 drw06

NOTES:
1. Holding WEN2/LD HIGH during reset will make the pin act as a second write enable pin. Holding WEN2/LD LOW during reset will make the pin act as a load enable for the programmableflag offset registers.
2. After reset, the outputs will be LOW if OE = 0 and high-impedance if OE = 1.
3. The clocks (RCLK, WCLK) can be free-running during reset.

Figure 4. Reset Timing

tCLK
tCLKH

tCLKL

WCLK
tDH

tDS
D0 - D8DATA IN VALID

tENH
tENS
NO OPERATION

WEN1
tENH

tENS
WEN2/
(If Applicable)

NO OPERATIONCOMMERCIAL AND INDUSTRIAL
tWFF
TEMPERATURE
RANGEStWFF
FF
tSKEW1(1)
RCLK

REN1,
REN2

4092 drw07

NOTE:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge for FF to change during the current clock cycle. If the time between
the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK edge.

Figure 5. Write Cycle Timing
8

COMMERCIAL AND INDUSTRIALTEMPERATURE RANGES

IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™
256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
tCLK
tCLKL

tCLKH
RCLK
tENS

tENH

REN1,
REN2

NO OPERATION
tREF

tREF

EF
tA
VALID DATA

Q0 - Q8
tOLZ

tOHZ

tOE
OE

tSKEW1 (1)

WCLK

WEN1

WEN2

4092 drw08

NOTE:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge for EF to change during the current clock cycle. If the time between
the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then EF may not change state until the next RCLK edge.

Figure 6. Read Cycle Timing

WCLK
tDS
D1

D0 - D8D2

D3

D0 (First Valid Write)

tENS
WEN1
tENS
WEN2
(If Applicable)

(1)

tFRL

tSKEW1
RCLK

tREF
EF
tENS

REN1,
REN2

tA

tA
D0

Q0 - Q8
tOLZ

D1

tOE

OE

NOTE:
1. When tSKEW1 ≥ minimum specification, tFRL = tCLK + tSKEW1When tSKEW1 < minimum specification, tFRL = 2tCLK + tSKEW1 or tCLK + tSKEW1
The Latency Timings apply only at the Empty Boundary (EF = LOW).

4092 drw09

Figure 7. First Data Word Latency Timing
9

COMMERCIAL AND INDUSTRIALTEMPERATURE RANGES

IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™
256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
NO WRITENO WRITENO WRITEWCLKtSKEW1tSKEW1tDS

D0 - D8
tWFF

tWFF

tWFF

FF
(1)

tENS

tENH

tENS

tENS

tENH

tENS

WEN1
(1)

WEN2
(If Applicable)

RCLK
tENS

REN1,
REN2

tENH

tENS

tENH

tA

OE LOWtA
Q0 - Q8DATA READDATA IN OUTPUT REGISTERNEXT DATA READ
4092 drw10

NOTE:
1. Only one of the two Write Enable inputs, WEN1 or WEN2, needs to go inactive to inhibit writes to the FIFO.

Figure 8. Full Flag Timing

WCLK
tDS

tDS
DATA WRITE 1

D0 - D8DATA WRITE 2

tENS

tENH

tENS

tENH

tENS

tENH

tENS

tENH

WEN1

WEN2
(If Applicable)(1)

tSKEW1(1)tFRL

tSKEW1

tFFL

RCLK
tREF

tREF

tREF

COMMERCIAL AND INDUSTRIALTEMPERATURE RANGES

EF
REN1,
REN2
OE LOWtA
Q0 - Q8DATA READDATA IN OUTPUT REGISTER

4092 drw11

NOTE:
1. When tSKEW1 ≥ minimum specification, tFRL maximum = tCLK + tSKEW1When tSKEW1 < minimum specification, tFRL maximum = 2tCLK + tSKEW1 or tCLK + tSKEW1
The Latency Timings apply only at the Empty Boundary (EF = LOW).

Figure 9. Empty Flag Timing
10

COMMERCIAL AND INDUSTRIALTEMPERATURE RANGES

IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™
256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
tCLKH

tCLKL
(4)

WCLK
tENS

tENH

tENS

tENH

WEN1

WEN2
(If Applicable)
tPAF
Full - (m + 1) words in FIFO

PAF

(1)

Full - m words in FIFOtSKEW2

(2)
(3)

tPAF

RCLK
tENS

tENH

REN1,
REN2

4092 drw12

NOTES:
1. m = PAF offset.
2. 256 - m words in FIFO for IDT72V201, 512 - m words for IDT72V211, 1,024 - m words for IDT72V221, 2,048 - m words for IDT72V231, 4,096 - m words for IDT72V241, 8,192 - mwords for IDT72V251.
3. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising edge of RCLK andthe rising edge of WCLK is less than tSKEW2, then PAF may not change state until the next WCLK rising edge.
4. If a write is performed on this rising edge of the write clock, there will be Full - (m-1) words in the FIFO when PAF goes LOW.

Figure 10. Programmable Full Flag Timing

tCLKH

tCLKL

WCLK
tENS

tENH

tENS

tENH

WEN1

WEN2
(If Applicable)

PAE

n + 1 words in FIFO

n words in FIFO (1)tSKEW2 (2)

tPAE

tPAE
(3)

RCLK
tENS
REN1,
REN2

tENH

4092 drw13

NOTES:
1. n = PAE offset.
2. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge for PAE to change during that clock cycle. If the time between the rising edge of WCLK andthe rising edge of RCLK is less than tSKEW2, then PAE may not change state until the next RCLK rising edge.
3. If a read is performed on this rising edge of the read clock, there will be Empty + (n-1) words in the FIFO when PAE goes LOW.

Figure 11. Programmable Empty Flag Timing
11

COMMERCIAL AND INDUSTRIALTEMPERATURE RANGES

IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™
256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9

tCLK
tCLKH

tCLKL

WCLK
tENS

tENH

LD
tENS
WEN1
tDS

tDH

D0 - D7
PAE OFFSET(LSB)PAE OFFSET(MSB)PAF OFFSET(LSB)PAF OFFSET(MSB)

4092 drw14

Figure 12. Write Offset Registers Timing

tCLK
tCLKH

tCLKL

RCLK
tENS

tENH

LD

COMMERCIAL AND INDUSTRIALTEMPERATURE RANGES

tENS
REN1,
REN2
tA
Q0 - Q7DATA IN OUTPUT REGISTEREMPTY OFFSET(LSB)

EMPTY OFFSET(MSB)FULL OFFSET(LSB)FULL OFFSET(MSB)
4092 drw15

Figure 13. Read Offset Registers Timing
12

COMMERCIAL AND INDUSTRIALTEMPERATURE RANGES

IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™
256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9

OPERATING CONFIGURATIONS

the Read Enable 2 (REN2) control input can be grounded (see Figure 14). In
this configuration, the Write Enable 2/Load (WEN2/LD) pin is set LOW at Resetso that the pin operates as a control to load and read the programmable flag
offsets.

SINGLE DEVICE CONFIGURATION
A single IDT72V201/72V211/72V221/72V231/72V241/72V251 may be
used when the application requirements are for 256/512/1,024/2,048/4,096/
8,192 words or less. When these FIFOs are in a Single Device Configuration,

RESET (RS)READ CLOCK (RCLK)WRITE CLOCK (WCLK)WRITE ENABLE 1 (WEN1)WRITE ENABLE 2/LOAD (WEN2/LD)
DATA IN (D0 - D8)
FULL FLAG (FF)
PROGRAMMABLE ALMOST-FULL (PAF)

IDT
72V201
72V211
72V221
72V231
72V241
72V251READ ENABLE 1 (REN1)OUTPUT ENABLE (OE)
DATA OUT (Q0 - Q8)
EMPTY FLAG (EF)
PROGRAMMABLE ALMOST-EMPTY (PAE)4092 drw16

READ ENABLE 2 (REN2)

Figure 14. Block Diagram of Single 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9 Synchronous FIFOWIDTH EXPANSION CONFIGURATION
Word width may be increased simply by connecting the corresponding input
controls signals of multiple devices. A composite flag should be created for eachof the end-point status flags (EF and FF). The partial status flags (AE and AF)
can be detected from any one device. Figure 15 demonstrates a 18-bit word
width by using two IDT72V201/72V211/72V221/72V231/72V241/72V251s.
Any word width can be attained by adding additional IDT72V201/72V211/
72V221/72V231/72V241/72V251s.
When these devices are in a Width Expansion Configuration, the Read
Enable 2 (REN2) control input can be grounded (see Figure 15). In thisconfiguration, the Write Enable 2/Load (WEN2/LD) pin is set LOW at Reset sothat the pin operates as a control to load and read the programmable flag offsets.

1,024/2,048/4,096/8,192 words. The existence of two enable pins on the read
and write port allow depth expansion. The Write Enable 2/Load pin is used asa second write enable in a depth expansion configuration thus the programmable flags are set to the default values. Depth expansion is possible by using
one enable input for system control while the other enable input is controlled byexpansion logic to direct the flow of data. A typical application would have theexpansion logic alternate data access from one device to the next in a sequential
manner. These FIFOs operate in the Depth Expansion configuration when thefollowing conditions are met:
1. The WEN2/ LD pin is held HIGH during Reset so that this pin
operates a second Write Enable.
2. External logic is used to control the flow of data.
Please see the Application Note" DEPTH EXPANSION OF IDT'S SYNCHRONOUS FIFOs USING THE RING COUNTER APPROACH" for detailsof this configuration.

DEPTH EXPANSIONThe IDT72V201/72V211/72V221/72V231/72V241/72V251 can beadapted to applications when the requirements are for greater than 256/512/

RESET (RS)DATA IN (D)18

RESET (RS)99READ CLOCK (RCLK)WRITE CLOCK (WCLK)READ ENABLE1 (REN1)

WRITE ENABLE1 (WEN1)WRITE ENABLE2/LOAD (WEN2/LD)
FULL FLAG (FF) #1
FULL FLAG (FF) #2
PROGRAMMABLE (PAF)

IDT
72V201
72V211
72V221
72V231
72V241
72V251

IDT
72V201
72V211
72V221
72V231
72V241
72V251

9READ ENABLE 2 (REN2)OUTPUT ENABLE (OE)
PROGRAMMABLE (PAE)
EMPTY FLAG (EF) #1
EMPTY FLAG (EF) #2
9

DATA OUT (Q)READ ENABLE 2 (REN2)

Figure 15. Block Diagram of 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, 4,096 x 18 and 8,192 x 18
Synchronous FIFO Used in a Width Expansion Configuration
13

184092 drw17

ORDERING INFORMATION
XXXXX
X
XX
X
X
Device Type Power Speed Package

X
X
Process/
Temperature
Range
BLANK
8

Tube or Tray
Tape and Reel

BLANK
I(1)

Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)

G(2)

Green

J
PF

Plastic Leaded Chip Carrier (PLCC, J32-1)
Plastic Thin Quad Flatpack (TQFP, PR32-1)

10
15
20

Commerical Only
Commerical & Industrial Clock Cycle Time (tCLK)
Speed in Nanoseconds
Commerical OnlyL

Low Power

72V201
72V211
72V221
72V231
72V241
72V251

256 x 9 ⎯ 3.3V SyncFIFO™
512 x 9 ⎯ 3.3V SyncFIFO™
1,024 x 9 ⎯ 3.3V SyncFIFO™
2,048 x 9 ⎯ 3.3V SyncFIFO™
4,096 x 9 ⎯ 3.3V SyncFIFO™
8,192 x 9 ⎯ 3.3V SyncFIFO™
4092 drw 18

NOTES:
1. Industrial temperature range product for the 15ns is available as a standard device. All other speed grades are available by special order.
2. Green parts available. For specific speeds and packages contact your sales office.
LEAD FINISH (SnPb) parts are in EOL process. Product Discontinuation Notice - PDN# SP-17-02

DATASHEET DOCUMENT HISTORY
01/11/2002
02/01/2002
02/08/2006
10/22/2008
08/08/2013
03/19/2018

pg. 3.
pg. 3.
pgs. 1 and 14.
pg. 14.
pgs. 1, 13 and 14.
Product Discontinuation Notice - PDN# SP-17-02
Last time buy expires June 15, 2018.

14

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