NID5100

1.2 V to 5.5 V, 1.5 A input polarity protected, low quiescentcurrent ideal diodeRev. 1 — 26 July 2024

Product data sheet

1. General description

2. Features and benefits

The NID5100 is an integrated ideal diode capableof replacing traditional diodes in low voltage
systems unable to tolerate the high voltage drops of
conventional Schottky components.

•
•
•
•

When enabled and forward biased, the device
regulates the voltage between the IN and OUT
pins resulting in a forward voltage drop, VREG,
approximately an order of magnitude smaller thansimilarly rated Schottky diodes. When OUT voltage ishigher than IN voltage, the NID5100 becomes reverse
biased with very low leakage current.
Integrated Reverse-Polarity Protection (RPP) prevents
damage to components connected to the OUT pin in
the event of a supply voltage reversal.
The enable pin, EN determines if NID5100 operates inforward regulation mode or body-diode mode.

•
•
•
•
•

•

Low loss replacement for power OR-ing diodes
Automatic transition between OR-ed supplies
Operating voltage range: 1.2 V to 5.5 V
Reverse voltage protection VIN: -6 V absolute
maximum
Supports forward current up to 1.5 A
Forward regulation voltage, VREG : 31 mV (typ) at
IOUT = 10 mA, VIN = 3.3 V
Active LOW control pin, EN
Output status indication, ST
Low current consumption:• 3.3 V shutdown current, IIN(SD): 170 nA (typ)• 3.3 V quiescent current, IIN(Q): 240 nA (typ)Specified over Tamb -40 °C to +125 °C

A variety of power OR-ing configurations are supported
for system flexibility:

3. Applications

•
•
•

•
•
•

Two, or more, NID5100 devices in combination
NID5100s and conventional Schottky diodes
An NID5100 and an external PMOS

An open-drain status pin, ST, is high-impedance when
NID5100 is enabled and in forward conduction and low
when disabled or in a reverse biased condition. The ST
pin can be used to control an external PMOS to OR an
additional supply, or connected to a microcontroller toindicate the status condition of NID5100.
The NID5100 is available in a standard
TSSOP6 (SOT363-2) with 2.1 mm x 1.25 mm x0.95 mm body package compatible with industry SC88/
SC70-6 packages providing a small PCB footprintcompared to conventional low-current diodes.

Building automation
Smart meters
OR-ed primary and battery backup
IN

OUT

EN

ST

RST
VIN1

CIN
REN

GND

COUT

RL

IN

OUT

EN

ST

CL

RST
VIN2

CIN
REN

GND

COUT

aaa-039725

Fig. 1.

Simplified application

NID5100

Nexperia

1.2 V to 5.5 V, 1.5 A input polarity protected, low quiescent current ideal diode4. Ordering information
Table 1. Ordering information
Type number
Package
NID5100GW

Temperature range

Name

Description

Version-40 °C to +125 °C

TSSOP6plastic thin shrink small outline package; 6 leads;
body width 1.25 mm

SOT363-2

5. Marking
Table 2. Marking code
Type number

Marking code

NID5100GW

u1

6. Pin configuration and description
6.1. Pin configuration
NID5100GW package
SOT363-2 (TSSOP6)
IN 1

6 OUT

GND 2

5 ST

EN 3

4 n.c.
aaa-039726

Fig. 2.

Pin configuration SOT363-2 (SC-88)

6.2. Pin description
Table 3. Pin description
SymbolPin

I/O

Description

IN

1

I

Device input. Analogous to the "anode" pin of a diode.

GND

2

-

Device ground.

EN

3

I

Active-low enable input. Drive EN low to enable the device. Drive high todisable the device. Drive this pin to a valid high or low level. Do not leave thispin floating.

n.c.

4

-

Not internally connected. Can be tied to GND or left floating.
Must be soldered to PCB pad for mechanical reliability.

ST

5

O

Active-low output. High-Z when chip is enabled and regulating IN to OUT
voltage, VREG. Pulled low when the chip is disabled, or reverse current
blocking. Connect to GND or leave floating if not used.

OUT

6

O

Device output. Analogous to the "cathode" pin of a diode.

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1.2 V to 5.5 V, 1.5 A input polarity protected, low quiescent current ideal diode7. Specifications
7.1. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter

Conditions

Min

Max

Unit

VIN

supply voltage

- 6.0

+ 6.0

V

VOUT

output voltage

- 0.3

+ 6.0

V

VEN

enable pin voltage

- 0.3

+ 6.0

V

VST

status pin voltage

- 0.3

+ 6.0

V

ISW(MAX) continuous switch current

-

+ 1.5

A

ISW(PLS) maximum pulsed switch
current≤120 ms, 2% Duty Cycle

-

+ 2.5

A

ID(PLS)

maximum pulsed body
diode current≤0.1 ms, 0.2% Duty Cycle

-

+ 2.5

A

IST

status pin current

- 1.0

-

mA

Tj

junction temperature

- 40

150

ºC

Tstg

storage temperature

- 65

150

ºC

Tlead

lead temperature

-

300

ºC

(10 s soldering time)

7.2. ESD ratings
Table 5. ESD ratings
SymbolParameter
VESD

electrostatic discharge

Conditions

Value

Unit

HBM: ANSI/ESDA/JEDEC JS-001 class 2

±2000

V

CDM: ANSI/ESDA/JEDEC JS-002 class C2a

±500

V

7.3. Recommended operating conditions
Table 6. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
SymbolParameter

VIN

supply voltage

VOUT

output voltage

VST

Min

Max

Unit

1.2

5.5

V

0.5

5.5

V

status pin voltage

0

5.5

V

VEN

enable pin voltage

0

5.5

V

Δt/ΔV

enable pin input transition
rise and fall rate

0

200

ms/V

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Product data sheet

Conditions
VIN ≥ 1.2 V

VIN = 1.2 to 5.5 V;
VEN = 0 to VIN or VIN to 0 V

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NID5100

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1.2 V to 5.5 V, 1.5 A input polarity protected, low quiescent current ideal diode7.4. Recommended components
Table 7. Recommended components
Nominal component values, not including derating factors.
Symbol Parameter

Conditions

Min

Nom

Max

Unit

0.1

1

-

μF

CIN

capacitance on IN

COUT

capacitance on OUT

An output capacitor is required forproper operation.

0.1

0.47

100

μF

REN

resistor on EN

Connected to GND [1]

0

50

100

kΩ

RST

resistor on ST

25

50

100

kΩ

[1]

If the EN pin is driven by a microcontroller, the value of REN should be chosen in accordance with the microcontrollers I/O pin drive
capability (VOH and VOL).

7.5. Thermal information
Table 8. Thermal information
Thermal resistance according to JEDEC51-5 and -7
SymbolParameter

SOT363-2

Unit

RΘJA

junction-to-ambient thermal resistance

256

°C/W

RΘJC(TOP)junction-to-case (top) thermal resistance

177

°C/W

ΨJT

junction-to-top characterization parameter

78

°C/W

NID5100
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1.2 V to 5.5 V, 1.5 A input polarity protected, low quiescent current ideal diode7.6. Electrical characteristics
Table 9. Static characteristics
CIN = 0.1 µF in parallel with 1 µF, COUT = 0.1 µF, VEN = 0 V, 1.5 V ≤ VIN ≤ 5.5 V. Typical values are at Tamb = 25 °C with an
input voltage of 3.3 V (unless otherwise noted).
SymbolParameter

Conditions

Min

Typ

Max

Unit
μA

Input supply (IN)IIN(SD)
IIN(Q)

shutdown current
quiescent current

VOUT = VIN = VEN = 3.3 V
IOUT = 0 A (VOUT = open)

Tamb = 25°C

-

0.17

0.24

Tamb = -40°C to 125°C

-

-

0.30

VOUT = VIN; VEN = 0 V
IOUT = 0 A (VOUT = open)

Tamb = 25°C

-

0.24

0.35

Tamb = -40°C to 125°C

-

-

0.40

VEN = 0 V
IOUT = 10 mA

Tamb = -40°C to 125°C

7

31

50

mV

VIN = 3.3 V
IOUT = - 500 mA
VEN = 0 V

Tamb = 25°C

-

115

-

mΩ

μA

Forward voltage regulation, VREG
VREG

forward regulation
voltage
VREG = VIN - VOUT

VIN = 5 V, or
VIN = 3.3 V

ON-resistance (RON). See Fig. 26.
RON

on-state resistancetransistor fullyenhanced

Reverse Current Blocking (RCB) and body diode characteristics
VRCB_R

reverse current
blocking activation
voltage(VOUT - VIN), VOUT rising above VIN Tamb = 25°C
VEN = 0 V

-

30.5

-

mV

VRCB_F

reverse current(VOUT - VIN), VOUT falling below VIN Tamb = 25°C
blocking deactivation VEN = 0 V
voltage-- 33.5

-

mV

VFWD

body diode forward
voltage

0.3

0.5

0.9

V

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Product data sheet

IOUT = 10 mA
VEN = VIN

Tamb = -40°C to 125°C

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1.2 V to 5.5 V, 1.5 A input polarity protected, low quiescent current ideal diodeSymbolParameter

Conditions

Min

Typ

Max

Unit

VIN = 3.3 V; VOUT = 4 V; VEN = 0 V Tamb = 25°C

-

130

180

nA

Tamb = -40°C to 85°C

-200

-

200

nA

Tamb = -40°C to 125°C

-220

-

220

nA

-

130

180

nA

Tamb = -40°C to 85°C

-200

-

200

nA

Tamb = -40°C to 125°C

-220

-

220

nA

VIN = 2 V; VOUT = 5.5 V; VEN = 0 V Tamb = -40°C to 85°C

-220

130

220

nA

-

330

410

nA

Tamb = -40°C to 85°C

-

-

500

nA

Tamb = -40°C to 125°C

-

-

800

nA

-

420

500

nA

Tamb = -40°C to 85°C

-

-

600

nA

Tamb = -40°C to 125°C

-

-

1000

nA

VIN = 2 V; VOUT = 5.5 V; VEN = 0 V Tamb = -40°C to 85°C

-

530

700

nA

Tamb = 25°C

-

150

500

nA

Tamb = -40°C to 85°C

-

-

800

nA

Tamb = -40°C to 125°C

-

-

825

nA

Tamb = -40°C to 85°C

-

-

3300

nA

Tamb = -40°C to 125°C

-

-

3500

nA

Tamb = -40°C to 85°C

-

-

1500

nA

Tamb = -40°C to 125°C

-

-

1650

nA

Leakage currents
IOUTIN(REV)OUT to IN leakage
current(current out of IN,
reverse biased)
device enabled

IOUT(REV)

current into OUT(reverse biased)

VIN = 3.3 V; VOUT = 5 V; VEN = 0 V Tamb = 25°C

VIN = 3.3 V; VOUT = 4 V; VEN = 0 V Tamb = 25°C

device enabled

VIN = 3.3 V; VOUT = 5 V; VEN = 0 V Tamb = 25°C

IOUTIN(DIS)

OUT to IN leakage
current(current out of IN,
reverse biased)
device disabled

VIN = VEN = 4.5 V; VOUT = 5.5 V

VIN = VEN = 1.5 V; VOUT = 5.5 V
VIN = VEN = 0 V; VOUT = 5.5 V

Enable (EN)VIL

LOW-level input
voltagedevice enabled

Tamb = -40°C to 125°C

-

-

0.4

V

VIH

HIGH-level input
voltagedevice disabled

Tamb = -40°C to 125°C

1.2

-

-

V

VHYS

enable pin hysteresis

Tamb = 25°C

-

45

-

mV

IIL

LOW-level input
current

VEN = 0 V

Tamb = 25°C

-30

0

30

nA

Tamb = -40°C to 125°C

-100

-

100

nA

IIH

HIGH-level input
current

VIN = 3.3 V
VEN = 3.3 V

Tamb = 25°C

-

15

-

nA

Tamb = -40°C to 125°C

-

-

150

nA

HIGH-level input
current(VEN > VIN)

VIN = 3.3 V
VEN = 5 V

Tamb = 25°C

-

20

-

nA

Tamb = -40°C to 125°C

-

-

150

nA

IST = 1 mA; VIN ≥ 1.8 V

Tamb = -40°C to 125°C

-

-

0.1

V

IST = 0.1 mA; VIN < 1.8 V

Tamb = -40°C to 125°C

-

-

0.1

V

VST = VIN
VEN = 0 V

Tamb = -40°C to 125°C

-150

-

150

nA

Status indication (ST)
VOL(ST)
IST

LOW-level output
ST pin leakage
current

NID5100
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1.2 V to 5.5 V, 1.5 A input polarity protected, low quiescent current ideal diode7.7. Dynamic characteristics
Table 10. Dynamic characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); typical values at Tamb = 25 °C;
CIN = 0.1 µF in parallel with 1 µF; and a load of CL = 100 nF in parallel with RL = 1 kΩ. See Fig. 22 and Fig. 23.
Symbol Parameter

Conditions

Min

Typ

Max

Unit

tON

VIN = 1.5 V

-

90

-

μs

VIN = 1.8 V

-

100

-

μs

VIN = 2.5 V

-

130

-

μs

VIN = 3.3 V

-

165

-

μs

VIN = 5 V

-

240

-

μs

VIN = 1.5 V

-

60

-

μs

VIN = 1.8 V

-

50

-

μs

VIN = 2.5 V

-

38

-

μs

VIN = 3.3 V

-

30

-

μs

VIN = 5 V

-

10

-

μs

VIN = 1.5 V

-

35

-

μs

VIN = 1.8 V

-

25

-

μs

VIN = 2.5 V

-

20

-

μs

VIN = 3.3 V

-

15

-

μs

VIN = 5 V

-

10

-

μs

VIN = 1.5 V

-

80

-

μs

VIN = 1.8 V

-

90

-

μs

VIN = 2.5 V

-

125

-

μs

VIN = 3.3 V

-

160

-

μs

VIN = 5 V

-

220

-

μs

VIN = 1.5 V

-

38

-

μs

VIN = 1.8 V

-

33

-

μs

VIN = 2.5 V

-

25

-

μs

VIN = 3.3 V

-

18

-

μs

VIN = 5 V

-

1

-

μs

tOFF

tFALL

tSTLZ

tSTZL

turn-on time

turn-off time

output FALL time

status, ST pin, delay time: low to high-impedance
EN transitions from high to low
RST = 50 kΩ to IN

status, ST pin, delay time: high-impedance to low
EN transitions from low to high
RST = 50 kΩ to IN

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1.2 V to 5.5 V, 1.5 A input polarity protected, low quiescent current ideal diode7.8. Typical Characteristics
VIN = 3.3 V, GND = 0 V, VEN = 0 V, CIN = 0.1 + 1 μF, COUT + CL = 0.1 + 1 μF to GND. Typical values at Tamb = 25 C, unlessotherwise noted.
Table 11. Typical Characteristics
aaa-039727

0.30
IIN(SD)(mA)(1)

IIN(Q)
(mA)

(1)

(2)
(5)

(5)

0.25

aaa-039728

0.30

0.25

(2)
(3)
(4)

0.20

0.15

(4)

0.20

(3)

1

2

3

4

VIN (V)

0.15

5

VEN = VIN

1

2

3

4

VIN (V)

5

VEN = 0 V

-40 ºC

25 ºC

85 ºC

105 ºC125 ºC-40 ºC

25 ºC

85 ºC

105 ºC125 ºC

(1)

(2)

(3)

(4)

(5)

(1)

(2)

(3)

(4)

(5)

Fig. 3.

Shutdown current versus input voltage

Fig. 4.

aaa-039729

140

aaa-039731

800

(1)

IOUT(R)(nA)

IOUT-IN(R)
(nA)

700

(2)

60

Quiescent supply current versus input voltage

600

(2)

-20

(1)

500

-100
-40

-15

10

35

60

85

110
135
Tamb (°C)

VEN = 0 V

400
-40

-15

10

35

60

85

110
135
Tamb (°C)

VEN = 0 V

VOUT = 5 V; VIN = 3.3 V

VOUT = 5.5 V; VIN = 2 V

VOUT = 5 V; VIN = 3.3 V

VOUT = 5.5 V; VIN = 2 V

(1)

(2)

(1)

(2)

Fig. 5.

OUT to IN leakage current (enabled, blocking)versus junction temperature

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Fig. 6.

OUT current (enabled, blocking) versus junction
temperature

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1.2 V to 5.5 V, 1.5 A input polarity protected, low quiescent current ideal diodeaaa-039730

300
IOUT-IN(R)(nA)

IOUT(R)
(nA)

(1)

100

aaa-039779

1100

900

(2)

(3)

-100

700

(3)

-300

(1)
(2)

500

-500
-40

-15

10

35

60

85

110
135
Tamb (°C)

VEN = VIN

300
-40

-15

10

35

60

85

110
135
Tamb (°C)

VEN = VIN

VOUT = 5 V;
VIN = 4.5 V

VOUT = 5.5 V;
VIN = 1.5 V

VOUT = 5.5 V;
VIN = 0 V

VOUT = 5 V;
VIN = 4.5 V

VOUT = 5.5 V;
VIN = 1.5 V

VOUT = 5.5 V;
VIN = 0 V

(1)

(2)

(3)

(1)

(2)

(3)

Fig. 7.

OUT to IN leakage current (disabled, blocking)versus junction temperature
aaa-039780

1.2

Fig. 8.

OUT current (disabled, blocking) versus
junction temperature
aaa-039781

50
VOL(ST)
(mV)

VEN
(V)

40

1.0

(1)

30
0.8

(3)

(1)

0.6

(2)

20

(2)

10
(4)

0.4
-40

-15

10

35

60

85

110
135
Tamb (°C)

VIN = 1.2 to 5 V

Fig. 9.

0
-40

(5)

-15

10

35

60

85

110
135
Tamb (°C)

VEN = VIN

VEN rising

VEN falling

IOL(ST) = 0.1 mA

(1)

(2)

1.2 V

1.8 V

2.5 V

3.3 V

5V

(1)

(2)

(3)

(4)

(5)

Enable threshold voltage versus temperature

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IOL(ST) = 1 mA

Fig. 10. Status pin output low level voltage

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1.2 V to 5.5 V, 1.5 A input polarity protected, low quiescent current ideal diodeaaa-039782

40
VRCB
(mV)

VFWD
(V)

(1)

20

aaa-039783

0.9

(1)

0.8
(2)

0.7

0

(3)

0.6

-20

(4)

(2)

(5)

-40
-40

-15

10

35

60

85

0.5

110
135
Tamb (°C)

VIN = VEN = 1.2 to 5 V; VOUT - VIN

1

2

3

4

VIN (V)

5

VEN = VIN

VRCB_R (enable)

VRCB_F (disable)-40 ºC

25 ºC

85 ºC

105 ºC125 ºC

(1)

(2)

(1)

(2)

(3)

(4)

(5)

Fig. 11. Reverse current blocking threshold voltage
versus temperature
aaa-039784

200

Fig. 12. Body diode forward voltage versus input
voltageaaa-039785

300

(1)

VREG
(mV)

(3)

150

(1)

VREG
(mV)

(2)

(2)
(3)

200
100

(4)
(5)

(4)

100

(5)

50

0

1

10

102

0

103
104
IOUT (mA)

1

10

102

103
104
IOUT (mA)

VIN = 3.3 V; VEN = 0 V; CL = 100 nF

VIN = 5 V; VEN = 0 V; CL = 100 nF-40 ºC

25 ºC

85 ºC

105 ºC125 ºC-40 ºC

25 ºC

85 ºC

105 ºC125 ºC

(1)

(2)

(3)

(4)

(5)

(1)

(2)

(3)

(4)

(5)

Fig. 13. Forward regulation voltage vs output current

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Fig. 14. Forward regulation voltage vs output current

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1.2 V to 5.5 V, 1.5 A input polarity protected, low quiescent current ideal diodeaaa-039786

600
VREG
(mV)

aaa-039787

800

(1)

VREG
(mV)

(2)

(1)
(2)

600

400
400

(3)

200

0

(3)

(4)
(4)

(5)

1

10

200

102

0

103
104
IOUT (mA)

VIN = 1.8 V; VEN = 0 V; CL = 100 nF

(5)

1

10

102

103
104
IOUT (mA)

VIN = 1.5 V; VEN = 0 V; CL = 100 nF-40 ºC

25 ºC

85 ºC

105 ºC125 ºC-40 ºC

25 ºC

85 ºC

105 ºC125 ºC

(1)

(2)

(3)

(4)

(5)

(1)

(2)

(3)

(4)

(5)

Fig. 15. Forward regulation voltage vs output current

Fig. 16. Forward regulation voltage vs output current

aaa-039797

aaa-039798

mm

VIN = 5 V; VEN = 0 V; CL = 100 nF; RL = 1 kΩ

VIN = 3.3 V; VEN = 0 V; CL = 100 nF; RL = 1 kΩFig. 17. Power up response

Fig. 18. Power up response

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1.2 V to 5.5 V, 1.5 A input polarity protected, low quiescent current ideal diodeaaa-039799

aaa-039800

VIN = 5 V; VEN = 0 to VIN; CL = 100 nF; RL = 47 Ω

VIN = 3.3 V; VEN = 0 to VIN; CL = 100 nF; RL = 33 Ω

Fig. 19. Enable and disable response

Fig. 20. Enable and disable response

A

IIN

IN

OUT

EN

ST

GND

IEN

A

RST

A
A

IST

A

IOUT

IGND

aaa-039930

Fig. 21. Current measurement test circuit
IN

OUT

EN

ST

RST
CIN

VIN

G

GND

COUT

RL

aaa-039931

Fig. 22. Timing response measurement circuit
VOUT ≈ VIN

VIN

VOUT

90%
VOUT = VIN - VFWD

tON

tOFF

tFALL

EN

ST

tSTLZ

CL

RL

10%

tSTZL

VIN1

VIH
VIL
0.9 × VIN

ST

RST

CL

VOL + 0.1 × VIN
aaa-039932

Fig. 23. Timing diagram

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1.2 V to 5.5 V, 1.5 A input polarity protected, low quiescent current ideal diode8. Functional Description
8.1. Functional diagram
IN

OUT

Gm
EN

GND

Comp
reversepolarity
protection

ST

+
VRCB
+
VREG
aaa-039971

Fig. 24. Functional diagram

8.2. Overview
The NID5100 consists of an internal PMOS transistor with its body diode oriented from IN (anode) to OUT (cathode);
reverse current protection; reverse polarity protection; gate regulation amplifier; control logic and a status flag, ST. The
device conducts from IN to OUT when enabled and forward biased and blocks when reverse biased. It mimics the behaviorof low voltage Schottky diodes with a fraction of the forward voltage drop and significantly lower reverse leakage current. It is
designed to operate from a 1.2 to 5.5 V supply making it suitable for use in a variety of low voltage applications.
OR-ing: The NID5100 supports a variety of power supply OR-ing, or redundant power backup, scenarios:
1.
2.
3.
4.

Low loss using "2 to n" NID5100s
Low loss dual OR-ing circuit consisting of one NID5100 and an external PMOS
Hybrid with one, or more, NID5100(s) in combination with Schottky diodes
Paralleling two or more NID5100s for high current loads

See application information sections for suggested implementations.

8.3. Feature Description
8.3.1. Enable, control logic and ST pin
The enable pin, EN, determines if the NID5100 operates in regulated conduction mode, VEN ≤ VIL, or body diode mode,
VEN ≥ VIH.
When the EN pin voltage, VEN ≤ VIL, the gate amplifier and control logic are operational and the device consumes low
quiescent current, IQ(EN).
The open-drain status, ST, pin provides real-time indication of the internal PMOS. See functional modes. When NID5100
is enabled, the ST pin indicates high when the internal PMOS is conducting. It indicates low when reverse biased andblocking. The ST pin is low when NID5100 is disabled. ST can be connected to a MCU input to provide status information orcontrol an external PMOS in a low-loss dual OR-ing application. If the ST pin is unused, connect to ground.

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1.2 V to 5.5 V, 1.5 A input polarity protected, low quiescent current ideal diode8.3.2. Device functional modes
Table 12 summarizes the device operating modes.
Table 12. Device functional modes
EN
State

IN-to-OUT

Power Dissipation

Status PIN State

HIGH

OFF

Diode

IOUT × VFWD

L

LOW

ON

Forward conduction

IOUT × (VIN - VOUT)

high-Z

LOW

RCB

Diode

IOUT(REV) × VOUT [1]L[1]

OUT current is leakage into device when reverse biased. See electrical characteristics tables.

8.3.3. Reverse Polarity Protection (RPP)
Reverse polarity conditions can occur when a power source's terminals are connected with opposite polarity, or a battery
is inserted incorrectly. Lossy power diodes and complicated ground connected discrete PMOS transistor circuits havehistorically been used to protect sensitive downstream circuits from polarity reversal conditions.
The NID5100 operates similarly. If a negative input voltage is applied to an unpowered NID5100, the PMOS will remain
off and prevent reverse current flow protecting downstream components. If the NID5100 is initially powered on andsubsequently experiences an input polarity reversal, the internal PMOS will turn off preventing the load from negative
voltage. RPP is active regardless of the state of the EN pin.
For autonomous operation with RPP, the EN pin must be tied to GND. A pull-down resistor, REN, is optional, but
recommended. If the ST pin is used for monitoring, it should be connected via a resistor, RST, to OUT or another voltage
source immune to reverse polarity conditions. RST should be sized to prevent exceeding the ST pin leakage current(see IST). Fig. 25 provides an application example.
-VIN

IN

OUT

EN

ST

RST
VIN

CIN
REN

GND

0V

COUT

RL

aaa-039933

Fig. 25. Single supply reverse polarity protection circuit

8.3.4. Gate regulation amplifier
When the NID5100 is enabled and forward biased, the gate regulation amplifier adjusts the internal PMOS gate voltage
to maintain the IN to OUT voltage, VREG. When operating in the forward voltage regulation region, the voltage drop isapproximately ten times smaller than a conventional Schottky diode aiding in the reduction of system power losses. At lightloads, the forward voltage drop from IN to OUT is maintained at VREG. As load current increases, the PMOS eventually
becomes fully enhanced and the IN to OUT voltage drop becomes proportional to the on-resistance of the PMOS multipliedby the load current. See right side inset of Fig. 26.

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1.2 V to 5.5 V, 1.5 A input polarity protected, low quiescent current ideal diode8.3.5. Reverse Current Blocking (RCB)
Reverse current blocking (RCB) protection is always active, regardless of the state of EN.
When EN is low and the output, OUT, is forced above the input, IN, the internal PMOS will switch off to stop the reverse
current. When the IN to OUT differential returns below VRCB_F, the device will turn back on and regulate IN to OUT at VREG.
When EN pin voltage is high, the internal PMOS is turned off and reverse current blocking (RCB) occurs through body diodeaction when VOUT is greater than VIN + VFWD. Forward conduction through the PMOS body diode resumes when VIN + VFWD
is greater than VOUT.
The NID5100 blocks reverse current via two mechanisms when enabled:
1. The VREG amplifier responds to common transients by naturally increasing the PMOS transistor resistance as the IN
to OUT voltage differential decreases. When VOUT nears and becomes larger than VIN the amplifier is regulating thetransistor gate and RDSON well below full enhancement increasing the impedance from OUT to IN until the PMOS
becomes full disabled.
2. In the event of an extremely fast transition to a reverse biased condition, such as a shorted input, the fast trip RCB
comparator reacts disabling the PMOS when VOUT - VIN = VRCB_R to limit reverse current.
VIN
VOUT

VRCB_R

IOUT

VREG

tOFF

1 / RON
VREG / RON

tON- VRCB_R

IOUT
0A

VREG

IRCB

V = VIN - VOUT

- VRCB_R / RONST
aaa-039934

Fig. 26. Reverse current blocking overview
Forward conduction: VIN ≥ (VOUT + VREG)
Reverse current blocking: VIN < VOUT
IN

OUT

EN

ST

RST
VIN

CIN
REN

GND

COUT

RL

aaa-039935

Fig. 27. Reverse current blocking

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1.2 V to 5.5 V, 1.5 A input polarity protected, low quiescent current ideal diode9. Application information
Note: Application implementation information in the following sections is not part of the Nexperia component
specification. Nexperia’s device users are responsible for determining suitability of components for their purposes, aswell as validating and testing their design implementation to confirm system functionality.
The NID5100 ideal diode is a versatile device suitable for protecting circuits from reverse polarity connections, reverse
current conditions, OR-ing and simple power multiplexing. The following sections provide application examples to aid thedesign of products using NID5100.

9.1. Reverse polarity protection
Universal DC power supplies are often used to replace an OEM wall charger which has been lost or broken. Commonly
these supplies are capable of reversing voltage polarity and if the user does not take care to ensure proper universal power
supply polarity setup, negative voltages could be applied to the device being powered causing it to be damaged. The
NID5100 senses reverse polarity connections and protects downstream components from exposure to negative voltages.
When reverse polarity protection is used, the ST pin should be connected to OUT or left floating. Connecting ST to IN may
result in device malfunction during supply reversal.
IN
universal
power
supply

+

OUT
RST

VIN

CIN

EN
REN

GND

ST

COUT

RL

aaa-039936

Fig. 28. Single supply reverse polarity protection scenario
Fig. 29 demonstrates the operation of NID5100 in the event of a positive to negative polarity reversal. VIN is initially 5 V, thenrapidly reverses to -5 V. VOUT drops to 0 V and the ST pin transitions from high to low.
aaa-039822

Fig. 29. 5 V to -5 V reverse polarity transition
Reverse polarity conditions can also occur in dual supply scenarios. Fig. 30 illustrates a situation in which a wall supply isproviding power with an incorrectly installed backup battery. So long as the OUT to IN conditions in limiting values are beobserved, the NID5100 can be use as shown without additional protection. For applications requiring a higher OUT to IN
differential, an external PMOS can be added in the power path, or paths, where reversal may occur - see Fig. 31 .

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1.2 V to 5.5 V, 1.5 A input polarity protected, low quiescent current ideal diode
IN
+
VIN1

RST
CIN

-

universal
power
supply

OUT

EN
REN

GND

universal
power
supply

COUT

ST

RL

IN

VIN1
+

IN

OUT

EN

ST

RST
RPD

CIN
REN

GND

CL

RL

OUT

IN

OUT

EN

ST

RST
VIN2

CIN

EN
REN

GND

ST

VIN2

Product data sheet

CIN
REN

aaa-039937

NID5100
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CL

RST

COUT

Fig. 30. Dual supply reverse polarity protection
scenario: |VIN1| ≤ 3 V and |VIN2| ≤ 3 V

COUT

GND

COUT

aaa-039938

Fig. 31. Dual supply reverse polarity protection with
PMOS: |VIN1| ≤ 5 V and |VIN2| ≤ 3 V

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1.2 V to 5.5 V, 1.5 A input polarity protected, low quiescent current ideal diode9.2. OR-ing examples
9.2.1. n+1 OR-ing using ideal diodes
There is no specific limitation to the number of NID5100 ideal diodes used for power OR-ing. The example below illustrates
a common two power supply scenario with smooth transitions between supplies.
Some devices operate from a fixed power supply such as a standard 5 V USB port output in normal conditions but must
quickly transition to a 3 V battery backup when the power supply is disabled or unplugged. Using two NID5100 devices in a
power OR-ing configuration, the downstream load remains uninterrupted when either the DC supply or the backup battery
are disconnected.
(5 V)

OUT

EN

ST

RST

+
VIN1

CIN

-

USB
adapter

IN

REN

GND

COUT

RL

(3 V)

IN

OUT

EN

ST

CL

RST
VIN2

CIN
REN

GND

COUT

aaa-039939

Fig. 32. OR-ing power supply and battery
The scope capture shows the output voltage (VOUT) being initially powered by VIN1 at 5 V. When VIN1 is removed, VIN2 at
3.3 V powers VOUT. When VIN1 is reconnected, VOUT is once again powered by VIN1. The ST pins of the NID5100's transition
to indicate which ideal diode is supplying the load.
aaa-039824

Fig. 33. OR-ed output transitions

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1.2 V to 5.5 V, 1.5 A input polarity protected, low quiescent current ideal diode9.2.2. OR-ing similar supply voltages
Some applications may require the OR-ing of supplies with similar voltages. Refer to Fig. 34 and Fig. 35. In this example,
the primary DC supply is 3.3 V with a 3 V battery backup. Consider the scenario where VIN1 is suppling the load, is removed
and subsequently restored.
Schottky circuit: As the two supplies differ by only 300mV, when VIN1 is restored, there may not be enough forward voltage,VF, across the diode in the VIN1 path to forward bias it until the battery voltage depletes sufficiently wasting energy in the
backup source.
NID5100 circuit: When VIN1 is restored, the reverse current blocking deactivation threshold, VRCB_F, of the 3.3 V supplied
NID5100 is easily exceeded allowing the 3.3 V supply to carry the full load. As the OUT is approximately 300 mV above
VIN2, the 3 V supplied NID5100 becomes reverse biased and the battery drain is minimized.
(3.3 V)(3.3 V)

IN

OUT

EN

ST

RST
CIN

VIN1

RPD

CIN

VIN1

COUT

REN
RL

GND

COUT

CL

CL

RL

(3 V)

(3 V)

IN

OUT

EN

ST

RST
VIN2

CIN

RPD

COUT

VIN2

CIN
REN

aaa-039940

Fig. 34. OR-ing supplies of similar voltages: Schottky

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GND

COUT

aaa-039941

Fig. 35. OR-ing supplies of similar voltages: NID5100

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1.2 V to 5.5 V, 1.5 A input polarity protected, low quiescent current ideal diode9.2.3. n+1 OR-ing using ideal and conventional diodes
When voltage drops and electrical losses of one of two power sources is not of concern, a combination of ideal diodes andconventional diodes can be implemented as shown in Fig. 36. In this example the AC-DC adapter is the primary powersource supplying 5 V to the system with three alkaline cells providing a 4.5 V backup. As stated in the OR-ing similar supply
voltages section, consideration should be given to the VF rating of the Schottky diode as well as worst case tolerances of the
supply voltages to ensure seamless transitions.
A resistor, RPD, connected to ground in the Schottky diode path is recommended to prevent diode reverse leakage during
blocking conditions from charging CIN1 and raising VIN1.
(5 V)
+
VIN1

CIN

-

universal
power
supply

COUT

RPD

RL

(4.5 V)

IN

OUT

EN

ST

CL

RST
VIN2

CIN
REN

GND

COUT

aaa-039957

RL = 47 Ω
Fig. 36. OR-ing with a combination of ideal and Schottky diodes
aaa-039914

Fig. 37. OR-ing NID5100 with Schottky (PMEG4010) output transitions

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1.2 V to 5.5 V, 1.5 A input polarity protected, low quiescent current ideal diode9.2.4. Paralleling NID5100 for thermal and sustained high current considerations
As with using any power semiconductor component, thermal ratings must be observed to maintain device reliability. Refer tothe thermal information table. System thermal analysis should be performed to ensure the device junction temperature, Tj,
remains below 150 °C under all operating conditions. If analyses of using a single NID5100 indicate a thermal violation, two
NID5100 can be paralleled to share the load current and lower internal power dissipation Fig. 38.
IN

OUT

EN

ST

RST
VIN

CIN
REN

GND

COUT

RL

IN

OUT

EN

ST

CL

RST
CIN
REN

GND

COUT

aaa-039958

Fig. 38. Paralleling two NID5100 ideal diodes for high current
Fig. 39 shows two NID5100's supporting a combined 2 A load current with 1 A current flowing in each NID5100.
aaa-039913

A
A
A

Fig. 39. Load sharing using two NID5100 ideal diodes

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1.2 V to 5.5 V, 1.5 A input polarity protected, low quiescent current ideal diode9.2.5. Priority OR-ing
More sophisticated systems may contain a microcontroller able to perform basic power management housekeeping
functions such as power source selection from supplies with similar voltages. In the example of figure Fig. 40, two NID5100
ideal diodes are connected in an OR-ing configuration from similar 5 V sources.
Refer to the device functional modes table for operation of the ST pin. In this application example, the ST pin of NID5100 U1
is connected via a pull-up resistor to VIN1 and the EN of NID5100 U2 providing a polarity inversion of the GPIO signal. Whendevice U1 is enabled, device U2 is disabled, and vice-versa allowing the MCU to select which supply sources the load.
When the microcontroller drives the GPIO low, NID5100 U1 is enabled sourcing VIN1 to OUT while U2 is disabled.
Conversely if the GPIO is driven high, NID5100 U2 is enabled sourcing VIN2 to OUT and NID5100 U1 is disabled. In either
scenario the RCB circuity remains active disabling the device with a low EN if VRCB_R is exceeded.
REN is recommended to be of high enough resistance to prevent loading the MCU GPIO output while ensuring EN is actively
driven in the event the GPIO is in a high impedance condition.
5.0 ± 0.25 V

IN

CIN

EN

VIN1

COUT

ST

GND

RL

NID5100 U1

I/O pin
MCU

OUT

REN
5.0 ± 0.25 V

VIN1

IN

OUT

RST1
VIN2

CIN

CL

RST
EN

GND

COUT

ST

NID5100 U2

aaa-039959

Fig. 40. Priority OR-ing using microcontroller
The scope capture shows EN1, EN2, VOUT, ST1, ST2, GPIO priority signal (PRI) connected to EN1, and the OUT1 andOUT2 currents.
Initially PRI is driven low pulling EN1 low, enabling NID5100 U1. VOUT is approximately equal to VIN1. Load is supplied from
OUT1. ST1, connected to EN2 is pulled above the VIH of NID5100 U2 with ST2 low indicating the device is disabled.
Next, EN1 is driven high, disabling NID5100 U1 causing ST1 to transition low, enabling NID5100 U2.
aaa-039825

RL = 47 Ω
Fig. 41. Priority OR-ing output transitions

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1.2 V to 5.5 V, 1.5 A input polarity protected, low quiescent current ideal diode9.2.6. OR-ing with discrete MOSFETIn this application, the EN pin of the NID5100 is always grounded “enabling” the device. When both the 5 V and 3.3 V
supplies are present, OUT is initially 5 V and the ST pin is high-Z with the RST resistor pulled up to VIN1, keeping the gate of
the external PFET high.
••If VIN1 is quickly removed, the ST pin output will transition low, enhancing the external PMOS. The load is then supplied
from VIN2.
If VIN1 is a slowly discharging battery, OUT will transition from being supplied by the NID5100 OUT pin to being suppliedby the external PMOS when VIN1 decreases below VIN2 by VFWD(ext_PMOS). Conversely, if VIN1 is slowly recharged, OUT
will be supplied from the PMOS until VIN1 + VREG ≥ VIN2 + VRDSON(ext_PMOS)
Note: The supply to the NID5100 (VIN1) should be the higher of the two supplies when both VIN1 and VIN2 are present.
5V

VIN1

IN

CIN

EN
REN

VIN1

OUT

GND

ST

COUT

RL

RST

CL

3.3 V

VIN2

CIN

COUT

RPD

aaa-039960

Fig. 42. OR-ing with external PMOS
The figures below show the switchover performance between VIN1 and VIN2. A resistor, RPD, to ground is recommended toprevent any reverse leakage from charging the 3.3 V CIN capacitor and raising the VIN2 voltage in the event the 3.3 V supply
is disconnected.
aaa-039823

RL = 47 Ω
Fig. 43. Switchover from VIN1 (5 V )to VIN2 (3.3 V) back to VIN1 (5 V)

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1.2 V to 5.5 V, 1.5 A input polarity protected, low quiescent current ideal diode10. Power supply recommendations
The device is designed to operate with a VIN range of 1.2 V to 5.5 V. The VIN power supply must be well regulated andplaced as close to the device terminal as possible. The power supply must be able to withstand all transient load current
steps.
In most situations, using an input capacitance (CIN) of 0.1 + 1 μF is sufficient to prevent the supply voltage from drooping.
In cases where the power supply is slow to respond to a large transient current or large load current step, additional bulk
capacitance may be required on the input.
An effective capacitance of ≥ 0.1 µF, after applying voltage and temperature derating factors, is required on the OUT pin toensure stability of the control loop Gm amplifier. NID5100 does not have over current protection and the maximum output
capacitance should not exceed approximately 100 µF.

11. Layout
Layout guidelines

ST

EN

n.c.

RST

GND

COUT

OUT

CHF

IN

REN

CIN

For best performance, all traces must be as short as possible. To be most effective, the input and output capacitors must beplaced close to the device to minimize the effects that parasitic trace inductances may have on normal operation. Using wide
traces for VIN, VOUT and GND helps minimize the parasitic electrical effects.

aaa-039972

NID5100
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1.2 V to 5.5 V, 1.5 A input polarity protected, low quiescent current ideal diode12. Package information
12.1. Package outline
TSSOP6: plastic thin shrink small outline package; 6 leads; body width 1.25 mm

D

SOT363-2

E

B

A

X

c
(6x)

y

HE

v M A

e1

6

5

4

pin 1 index

A

1

2

A1

3

A3

θ

Lp

w M B

bp
(6x)
e

A2

detail X

e

0

3 mm
scale

Dimensions (mm are the original dimensions)
Unit
mm

max
min

A

A1

A2

A3

bp

c

1.1
0.8

0.1
0

1.0
0.8

0.15

0.30 0.25
0.15 0.08

D(1)

E(1)

e

e1

HE

Lp

v

w

y

θ

2.2
1.8

1.35
0.65
1.15

1.3

2.4
1.8

0.46
0.26

0.3

0.1

0.1

8°
0°

Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
Outlineversion
SOT363-2References
IEC

JEDEC

JEITA

MO-203

SC-88A

sot363-2_po

Europeanprojection

Issue date21-12-15
21-12-16

Fig. 44. Package outline SOT363-2 (TSSOP6)

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1.2 V to 5.5 V, 1.5 A input polarity protected, low quiescent current ideal diode2.65

solder lands
2.35 1.5

0.4 (2×)

0.6 0.5(4×) (4×)

solder resist
solder paste

0.5
(4×)

0.6
(2×)

occupied area

0.6
(4×)

Dimensions in mm
1.8

sot363-2_fr

Fig. 45. Reflow soldering footprint SOT363-2 (TSSOP6)

13. Abbreviations
Table 13. Abbreviations
AcronymDescription

CDM

Charged Device Model

ESD

ElectroStatic Discharge

FET

Field-Effect Transistor

HBM

Human Body Model

IEC

International Electrotechnical Commission

JEDEC

Joint Electron Device Engineering Council

MOSFET

Metal-Oxide Semiconductor Field-Effect Transistor

PCB

Printed Circuit Board

PMOS

P-channel Metal-Oxide Semiconductor

14. Revision history
Table 14. Revision history
Document ID

Release date

Data sheet status

Change notice Supersedes

NID5100 v.1

20240726

Product data sheet-

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1.2 V to 5.5 V, 1.5 A input polarity protected, low quiescent current ideal diode15. Legal information

injury, death or severe property or environmental damage. Nexperia and its
suppliers accept no liability for inclusion and/or use of Nexperia products insuch equipment or applications and therefore such inclusion and/or use is at
the customer’s own risk.

Data sheet status

Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of thisdocument, and as such is not complete, exhaustive or legally binding.

Document status[1][2]

Product
status [3]Definition

Objective [short]data sheet

Development

This document contains data fromthe objective specification for
product development.

Preliminary [short]data sheet

Qualification

This document contains data fromthe preliminary specification.

Product [short]data sheet

Production

This document contains the productspecification.

[1]
[2]
[3]

Please consult the most recently issued document before initiating orcompleting a design.
The term 'short data sheet' is explained in section "Definitions".
The product status of device(s) described in this document may havechanged since this document was published and may differ in case ofmultiple devices. The latest product status information is available on
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Applications — Applications that are described herein for any of theseproducts are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
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NID5100

Nexperia

1.2 V to 5.5 V, 1.5 A input polarity protected, low quiescent current ideal diode© Nexperia B.V. 2024. All rights reserved

Contents

For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 26 July 2024

1. General description...................................................... 1
2. Features and benefits.................................................. 1
3. Applications.................................................................. 1
4. Ordering information....................................................2
5. Marking.......................................................................... 2
6. Pin configuration and description.............................. 2
6.1. Pin configuration..........................................................2
6.2. Pin description............................................................. 2
7. Specifications................................................................3
7.1. Limiting values.............................................................3
7.2. ESD ratings................................................................. 3
7.3. Recommended operating conditions........................... 3
7.4. Recommended components........................................ 4
7.5. Thermal information.....................................................4
7.6. Electrical characteristics.............................................. 5
7.7. Dynamic characteristics...............................................7
7.8. Typical Characteristics.................................................8
8. Functional Description...............................................138.1. Functional diagram.................................................... 13
8.2. Overview.................................................................... 13
8.3. Feature Description................................................... 13
8.3.1. Enable, control logic and ST pin.............................138.3.2. Device functional modes........................................ 14
8.3.3. Reverse Polarity Protection (RPP)......................... 14
8.3.4. Gate regulation amplifier........................................ 14
8.3.5. Reverse Current Blocking (RCB)............................15
9. Application information............................................. 16
9.1. Reverse polarity protection........................................ 16
9.2. OR-ing examples....................................................... 18
9.2.1. n+1 OR-ing using ideal diodes............................... 18
9.2.2. OR-ing similar supply voltages............................... 19
9.2.3. n+1 OR-ing using ideal and conventional diodes.... 20
9.2.4. Paralleling NID5100 for thermal and sustained
high current considerations................................................219.2.5. Priority OR-ing........................................................ 22
9.2.6. OR-ing with discrete MOSFET............................... 23
10. Power supply recommendations.............................24
11. Layout........................................................................ 24
12. Package information................................................ 25
12.1. Package outline....................................................... 25
13. Abbreviations............................................................ 26
14. Revision history........................................................26
15. Legal information......................................................27

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All information provided in this document is subject to legal disclaimers.

Rev. 1 — 26 July 2024

© Nexperia B.V. 2024. All rights reserved

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