AN90024

Resistor Equipped Transistors (RETs): Key parameters andapplication insights
Rev. 1.1 — 3 August 2021

application note

Document information
Information

Content

Keywords

RET, polysilicon resistors, digital transistor, pre-biased transistor

Abstract

This application note explains specific product and application aspects of Resistor Equipped
Transistors (RETs)

AN90024

Nexperia

Resistor Equipped Transistors (RETs): Key parameters and application insights

1. Introduction
Bipolar transistors are controlled via the base current applied. Because of high temperaturedependency of the voltage drop across the base-emitter path, it is required to add at least a series
resistors at the base for stable and safe operation of a transistor in most applications This isrequired to keep base current at a desired level.
To reduce the number of components and to make board designs less complex, Resistor-Equipped
Transistors (RET) have been introduced. These are single or dual transistors with resistors
integrated on the same die. The integrated resistors have higher tolerances than commonlyused external resistors. This fact makes RETs most suitable for switching applications where
the transistor operates either in on-state or off-state. This is the reason also, why RETs are often
referred to as digital transistors.

2. RET basics: topologies and nomenclature
RETs are available with NPN and PNP transistors. The most simple resistor configuration is aseries resistor applied at the base as shown in Fig. 1. Another option are RETs with a base divider.
Then there is a base series resistor R1 integrated and a second resistor R2 in parallel to the baseemitter path.

R1

aaa-033143

Fig. 1.

NPN RET with base resistor R1

Fig. 2 shows this topology with the base divider integration of R1 and R2. Both topologies can befound for PNP transistors as well of course.

R1

R2

aaa-033144

Fig. 2.

NPN RET with base divider R1 and R2

For R1 the value can be chosen from a list starting at 2.2 kΩ. Additional options are 4.7 kΩ, 10 kΩ,
22 kΩ and 47 kΩ. R2 option list starts with 10 kΩ with the additional choices of 22 kΩ and 47 kΩ.
For the ratio of the resistors there are several options from R2/R1 equal 1, 2.13, 4.55, 10 and 21.

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Resistor Equipped Transistors (RETs): Key parameters and application insights
Table 1 explains the nomenclature for single RETs. An example type name is NHDTA124ET
which can be decoded with the table below. Most important is the character indicating the Bipolar
Junction Transistor (BJT) type and collector current rating. The current clusters are lower or equal
higher than 500 mA. The characters A and B stand for PNP device whereas C and D are used
for NPN types. For the base resistor network, the series resistor R1 is defined by a base number
followed by a multiplier indication number. The character that follows informs the resistor ratio R1/
R2. Finally there is a character which tells the package variant. RETs are available in conventional
leaded packages such as SOT23 and SOT323 but also in leadless packages like SOT1215 which
is a DFN1010 or SOT883 which the same as DFN1006 so a 1 mm x 0.6 mm device.
Table 1. Nomenclature single RETS
st
nd
nd rd
1 letter
2 letter 2 3 letter
Company
Voltage
Indicator
Indicator
N=
Nexperia

H = high
voltage

P = Philips(legacy)st

Polarity
andCurrent

1 numberBasenumberfor R1

Multiplerfor R1

Resistor
Ratio R2/R1

Package
Indicator

DT = Digital
Transistor

A = PNP,< 500 mA

1 = nomeaning

1 =1

3 = x 10E3

T = R1 only

T = SOT23

BR = Low
VCEsatRET

B = PNP,≥ 500 mA2 = 2.2

4 = x 10E4

E=1
R1 = R2

U = SOT323

C = NPN,< 500 mA

4 = 4.7

5 = x 10E5

V = 0.213

M=
SOT883Comp. only: Comp. only:

W = 0.46

MB =SOT883B

X = 2.13

QA =SOT1215

Y = 4.55

QC =SOT8009

Z = 10QB =SOT8015

D = NPN,≥ 500 mA

3 = 3.3

2 = x 10E2

5 = 5.6

Table 2 shows an equivalent table for dual RETs. The naming structure is quite different from therd
one for single RETs. Very important is the 3 letter which informs the topology of the dual RET, so
if two NPNs or PNPs or a complementary pair can be found in the device.
Table 2. Nomenclature Double RETs
stnd
1 letter
2 letter
Package Indicator
Company
Voltage Indicator
Indicator
N = Philips (legacy)
P = Nexperia

H = High voltage

I = SOT457

ndrd

2 letter

3 letter

Number(s)M = no meaning

B = 2 x PNP

Consecutive
numberingU = SOT363

C = NPN/
PNP ≥ 500 mA

E = SOT666

D = NPN/PNP

Q = SOT1216

H = 2 x NPN

R = SOT1268

N = 2 x NPN>0 = 500 mA
P = 2 x PNP
500 mAT = 2 x PNP
X = 2 x NPN
Z = NPN/PNP

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Resistor Equipped Transistors (RETs): Key parameters and application insights

3. Application Examples
RETs are used as switches mainly, thus in the two states “on” and “off” This is why they arereferred to as digital transistors often. A basic example is shown in schematic diagram in using
an NPN-RET with integrated base series resistor. V1 is the control voltage and provides the basecurrent for the BJT. If V1 is below Voff the transistor is turned off. Vout is almost equal to V2. Once
V1 reaches the turn-on level, base current flows and Vout decreases. The switch changes into theon-state and Vout becomes equal to VCEsat.
The circuit has the behavior of an inverter with voltage translation. V2 can be chosen within thedatasheet limits of VCE of the chosen RET. The output voltage swing can be higher and lower thanthe control voltage V1. So voltage translation can be in provided up and down direction.

R2

Vout
R1

V2

V1

aaa-033145

Fig. 3.

Basic control BJT circuit with an NPN-RET

Fig. 4 is the equivalent circuit created with a PNP-RET. The control voltage V1 has to be negative
against the emitter of Q1 to get the RET turned on.

V1
R1

Q1
V2

Vout
R2

aaa-033146

Fig. 4.

AN90024

application note

Basic control BJT circuit with an NPN-RET

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Resistor Equipped Transistors (RETs): Key parameters and application insights
A very common load switch application with RETs in depicted in Fig. 5. The BJT Q2 switches theload current through the load resistor RL. Q2 conducts if Q1 is turned on. The control RET Q1
requires a positive base voltage to enable the load switch. The topology does not require high basecurrent nor high voltages for the control signal. Q2 can switch higher load voltages in compliance tothe rating of the chosen component (≤ 80 V) and also comparably high load currents of up to 500
mA. Low VCEsat RETs also called Performance-Based RETs (PBR), provide low residual collectoremitter voltages in on-state and therefore achieve high power-efficiency of the load switch. For RET
Q2 a product with a base resistor divider achieves a far better turn-off performance compared to a
RET with a series resistor in the base-path only. R4 accelerates turn-off time significantly because
Q2 is driven by an open-collector stage realized by Q1

R4
R3

Q2

Q1

R1

Vout
R2
RL

V1

V2

aaa-033147

Fig. 5.

Load switch with PNP RET in load path and NPN RET in control path

RETs can be used to combine multiple control signals towards one control signal output. Fig. 6
shows two input signals V1 and V2 as base drive for two RETs that share one collector resistor.
This circuit behaves like a NOR logic function. If one of the inputs is at high level or both, theoutput is providing a low state. Only if both input signals are low the output provides a high-levelsignal. The advantage of such RET solution against a standard logic gate is that the output can
support high voltages up to 80 V that cannot be found for logic families. The input drive can also
be designed very flexible via the selection of a suitable base resistor or base voltage divider. If
required, the NOR function can be changed into an OR function by adding an inverter stage asshown in Fig. 1 behind the output of the discussed circuit.

R5

Vout
R1

R2

V1

V3

R3

V2

R4

aaa-033148

Fig. 6.

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RETs in wired-NOR application

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AN90024

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Resistor Equipped Transistors (RETs): Key parameters and application insights
In a similar way, a NAND function can be implemented if RETs are connected in series for thecollector-emitter path like shown in Fig. 7. Only if both RETs are turned on at the same time, theoutput signal Vout provides a low level. If the output is inverted by another RET, an AND function
has been created.

R5

Vout
R1

R2

V1

V3

R3

R4

V2

aaa-033149

Fig. 7.

RETs in wired-NAND application

In Fig. 8 an application example for a push-pull stage is shown. The circuit is powered by twovoltage sources V2 and V3, providing a negative and positive polarity supply. Vout is terminated to
ground via Rload, which is the connection between the two voltage sources. Q1 and Q2 work as
emitter followers and amplify current provided by the input source V1.

Q1

R1

V3
R2

Vout

V1

Rload

R4
R3

V2
Q2

aaa-033150

Fig. 8.

AN90024

application note

Application example push-pull stage with RETs

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Resistor Equipped Transistors (RETs): Key parameters and application insights

4. Data sheet parameters
In this chapter the Nexperia data sheets for RETs are explained in detail. The major focus is on theelectrical parameters. For the discussion in this chapter a rather new Nexperia high voltage RET
has been chosen from an 80 V product series for reference.
The first chapter is the “General Description”. It informs the BJT polarity of the RET and the
packages available. Table 3 shows the product overview with the resistor variants R1/R2 of thechosen component. The complementary parts are mentioned if applicable.
Table 3. Product overview
R1
Type number

R2

kΩ

kΩ

NexperiaJEITA

NHDTC114EU

10

10SOT323SC-70

NHDTC124EU

22

22

NHDTA124EU

NHDTC144EU

47

47

NHDTA144EU

Package

PNP complement:
NHDTA114EU

A list of “Features and benefits” follows in the next section with. The major features like current
capability, high break down voltage and automotive qualification are mentioned here.
Features and benefits
•
•
•
•
•
•
•

100 mA output current capability
High breakdown voltage
Built-in resistors
Simplifies circuit design
Reduces component count
Reduces pick and place costs
AEC-Q101 qualified

The following section informs major application areas, . These are digital or switching applications
as discussed in more detail the prior chapter.
Applications••••

Digital applications
Cost saving alternative for BC846 series in digital applications
Controlling IC inputs
Switching loads“Quick reference data” are depicted in a brief table with electrical key parameters such as
maximum allowed VCE0 and output current IO.
Table 4. Quick reference data
Tamb = 25 °C unless otherwise specified.
SymbolParameter

Conditions

Min

Typ

Max

Unit

VCEO

collector-emitter voltage

open base

-

-

80

V

IO

output current

-

-

100

mA

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Resistor Equipped Transistors (RETs): Key parameters and application insights
The pinout of the RET is informed with the emitter, collector and input connections as shown below.
The input pin is also referred to as base although there are resistors integrated in between.
Table 5. Pinning
Pin

SymbolDescription

1

I

input (base)2

GND

GND (emitter)3

O

output (collector)

Simplified outline

Graphic symbol

3

O
I

R1
R2

GND
1

aaa-019964

2

The next section contains the ordering information.
Table 6. Ordering information
Type number
Package
NHDTC114EU

Name

Description

VersionSC-70

plastic surface-mounted package; 3 leads

SOT323NHDTC124EU
NHDTC144EU
The marking table in informs the marking of the devices. The last character “%” is a placeholder forthe manufacturing site.
Table 7. Marking
Type number

Marking code [1]

NHDTC114EU

5M%

NHDTC124EU

5Q%

NHDTC144EU

5S%

[1]

% = placeholder for manufacturing site code

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Resistor Equipped Transistors (RETs): Key parameters and application insights
The limiting values follow in the next section of the RET data sheet in Table 8.
VCB0 is the maximum collector-base voltage with an open emitter pin. VCE0 is the maximum allowed
collector-emitter voltage with an open base. For a RET where a resistor is placed between baseand emitter it could be called VCER as well because the input of the RET is open, but not the baseof the BJT. There is the relation to be considered for the breakdown voltage of the collector-emitter
path of a BJT as shown below:
VCES ≥ VCER ≥ VCE0
VCES is tested with the base being short-circuit to the emitter. For RETs the integrated resistors are
not taken into account for the nomenclature of parameters. Despite of integrated resistors the term
VCEO is used still. This is important to be taken into account for other key parameters as well likeleakage current ratings.
VI has a maximum rating of 10 V for the example data sheet of a PNP RET with a divider ratio of 1.
The BJT as a stand-alone device would have the limitation of VEB0 = 5 V. Due to the input divider
this value is doubled. The base-emitter diode is driven reverse and therefore does not conduct
below the limit value. For further details please refer to chapter 5.
For the other polarity of VI, base current flows, so there is a forward voltage drop across the baseemitter diode to be considered whereas the rest of the input voltage is present at the base series
resistor R1. The voltage limit is mainly defined by the maximum power dissipation of the integrated
resistor R1. Therefore maximum base current is limited by R1 and thus VI.
Total power dissipation Ptot is informed for two mounting conditions. One is meant for a single layer
FR4-PCB using a standard footprint. The second value is provided for a 4-layer FR4-PCB, where
bottom layer and the inside layers are solid copper planes.
Table 8. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Tamb = 25 °C unless otherwise specified.
SymbolParameter

Conditions

Min

Max

Unit

VCBO

collector-base voltage

open emitter

-

80

V

VCEO

collector-emitter voltage

open base

-

80

V

VEBO

emitter-base voltage

open collector

-

10

V

VI

input voltage
NHDTC114EU

-10

+40

V

NHDTC124EU

-10

+60

V

NHDTC144EU

-10

+80

V

IO

output current

-

100

mA

Ptot

total power dissipation

[1]

-

235

mW

[2]

-

315

mW

Tamb ≤ 25 °C

Tj

junction temperature

-

150

°C

Tamb

ambient temperature

-55

150

°C

Tstg

storage temperature

-65

150

°C

[1]
[2]

Device mounted on an FR4 Printed-Circuit-Board (PCB); single-sided copper; tin-plated and standard footprint.
Device mounted on an FR4 Printed-Circuit-Board (PCB);4-layer copper; tin-plated and standard footprint.

The maximum junction temperature for gold wire products is 150°C because otherwise the alumina
layer of the bond wire joint would be consumed up by diffusion processes of the alumina into thegold. For longer exposure to temperatures above 150°C the wire joint becomes unstable and canfail. Copper wire products can be specified up to 175°C. Storage and ambient temperature havethe same limits. With rising ambient temperature the maximum power that can be applied degradeswith a linear curve as shown in Fig. 9 below. A RET which is designed for Tj(max) = 175°C has aderating curve which reaches the x-axis at 175°C, so higher power can be dissipated comparably.

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Resistor Equipped Transistors (RETs): Key parameters and application insights
aaa-031869

400
Ptot
(mW)

(1)

300
(2)

200

100

0
-75

-25

25

75

125
175
Tamb (°C)(1) FR4 PCB, 4-layer copper, standard footprint(2) FR4 PCB, single-sided copper, standard footprint
Fig. 9.

Power derating curves SOT323 (SC-70)

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Resistor Equipped Transistors (RETs): Key parameters and application insights
Further thermal characteristics are provided in Table 9 in the example RET data sheet. Thermal
resistance Rth is informed for different mounting conditions. The values provided could also be
calculated from the related Ptot ratings in Tab. 6 with:Rth(j-a) = (Tj(max) – 25°C)/Ptot
For example for Rth(j-a) the calculation delivers:(150 °C - 25 °C)/0.235 W = 532 K/W
Table 9. Thermal characteristics
Tamb = 25 °C unless otherwise specified.
SymbolParameter

Conditions

Rth(j-a)thermal resistance from junction to ambientin free airRth(j-sp)[1][2]

thermal resistance from junction to solder point

Min

Typ

Max

Unit

[1]

-

-

532

K/W

[2]

-

-

397

K/W

-

-

150

K/W

Device mounted on an FR4 Printed-Circuit-Board (PCB); single-sided copper; tin-plated and standard footprint.
Device mounted on an FR4 Printed-Circuit Board (PCB), 4-layer copper, tin-plated and standard footprint.

Rth(j-sp) is the thermal resistance from junction to the solder point of the pin for the major thermal
path of the SMD package discussed. For RETs in SOT23 or SOT323 this is the collector lead.
The other two terminals for the emitter and base are connected via bond wires, so they do notcontribute to heat dissipation. Rth(j-a) informs about the thermal resistance from junction to ambient.
This value depends significantly on the mounting condition, for example PCB layout and type aswell as copper thickness.
Zth(j-a) is the transient thermal impedance from junction to ambient as depicted in Fig.8 and Fig.9.
These diagrams help to calculate a thermal scenario for applications where the RET is not run in
DC condition but where it operates in switching mode.
The Zth diagrams are provided for different mounting conditions. Zth is provided versus the pulse
length of the on-state for the RET. Curves are depicted for different duty cycles d from single eventswith d = 0 up to DC mode with d = 1. Duty cycle d is defined as:
d = ton /T, where ton is the on-state duration and T the cycle time.
The value for the DC-case is identical to the Rth(j-a) parameter in the data sheet. For long pulses
with about more than 10 seconds duration rather small SMD components get heated up to thesame temperature like for a constant on-state. This is why all curves start at the same level on theright side of the diagrams. If short pulses are applied, the values for Zth are becoming smaller, so
higher pulse power can be handled. The curves are getting flat for very short pulses and d > 0.05
in the diagram. This is the case because switching frequency is becoming quite high in this region
and the heat generation is averaging out in the crystal. There is almost no time for temperaturechanges between on-state and off-state.

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Resistor Equipped Transistors (RETs): Key parameters and application insights
aaa-031870

103
duty cycle = 1

Zth(j-a)
(K/W)

0.75

0.50

0.33
102

0.20
0.10
0.05

10

0.02

0.01

0
1
10-5

10-4

10-3

10-2

10-1

1

10

102

tp (s)

103

FR4 PCB, single-sided copper, tin-plated and standard footprint
Fig. 10. Transient thermal impedance from junction to ambient as a function of pulse duration; typical values
aaa-031871

103
duty cycle = 1

Zth(j-a)
(K/W)

0.75

102

0.33

0.50
0.20

0.10
0.05
10

0.02

0.01

0
1
10-5

10-4

10-3

10-2

10-1

1

10

102

tp (s)

103

FR4 PCB, 4-layer copper, tin-plated and standard footprint
Fig. 11. Transient thermal impedance from junction to ambient as a function of pulse duration; typical values
Every Zth-curve is valid for a specific mounting condition. Fig. 10 represents operation with astandard footprint on a single layer FR4 PCB and 35 µm copper layer whereas Fig. 11 is based on
a 4-layer FR4 PCB with the RET mounted on a standard footprint. All other three layers of the test
PCB are realized as solid copper areas.
If a very good thermal performance of a board design is required it can be recommended to havean extra thermal pad for the collector on the top layer with about 1 cm² to improve the thermal path
into the second layer. The second layer should provide a bigger copper area in order to get heatspread and dissipated via the PCB.
For calculation of the temperature increase of a RET in an application first the pulse power needs
to be derived. The Zth-curves are valid for rectangular-shaped power pulses. In many applications
the shape of the power pulse can deviate from this. Then it is possible in most cases to convert themeasured power pulse into a rectangular pulse with an equivalent pulse power.
The correct Zth value is derived by reading the thermal resistance at the given pulse length tp in
the curve with the relevant duty cycle. The temperature increase of the junction against ambient
temperature is calculated then with:∆T = Zth(j-a) * Pp (Pp = Pulse Power in Watt)
Tamb + ∆T may not exceed the defined Tj(max) found in the specification.

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Resistor Equipped Transistors (RETs): Key parameters and application insights
The next chapter in data sheets of RETs informs the electrical characteristics of the components.
Most characteristics are tested at an ambient temperature of 25° C unless another temperature isinformed for the test conditions. If the test condition can heat up the device significantly, the related
value is measured in a pulsed test mode in order to avoid self-heating.
Table 10. Characteristics
Tamb = 25 °C unless otherwise specified.
SymbolParameter

Conditions

Min

Typ

Max

Unit

V(BR)CBO

collector-basebreakdown voltage

IC = 100 µA; IE = 0 A

80

-

-

V

V(BR)CEOcollector-emitter
breakdown voltage

IC = 2 mA; IB = 0 A

80

-

-

V

ICBO

collector-base cut-off
current

VCB = 80 V; IE = 0 A

-

-

100

nA

ICEO

collector-emitter cut-off VCE = 60 V; IB = 0 A
current
VCE = 60 V; IB = 0 A; Tj = 150 °C

-

-

100

nA

-

-

5

µA

-

-

600

µA

NHDTC124EU

-

-

270

µA

NHDTC144EU

-

-

130

µA

50

-

-

70

-

-

IEBO

emitter-base cut-off current
NHDTC114EUhFE

VEB = 7 V; IC = 0 A

DC current gain
NHDTC114EU

VCE = 5 V; IC = 10 mA

NHDTC124EU

100

-

-

VCEsatNHDTC144EU
collector-emittersaturation voltage

IC = 10 mA; IB = 0.5 mA

-

-

100

mV

VI(off)off-state input voltage

VCE = 5 V ; IC = 100 µA

-

1.15

0.8

V

VI(on)

on-state input voltage
VCE = 0.3 V ; IC = 10 mA

NHDTC114EU

R1

2.5

1.8

-

V

NHDTC124EU

3

2.3

-

V

NHDTC144EU

5

3.3

-

V

NHDTC114EU

7

10

13

kΩ

NHDTC124EU

15.4

22

28.6

kΩ

NHDTC144EU

33

47

61

kΩ

[1]

0.8

1

1.2

[2]

-

170

-

MHz

-

-

2.5

pF

[1]

bias resistor 1 (input)

R2/R1

bias resistor ratio

fTtransition frequency

VCE = 5 V; IC = 10 mA; f = 100 MHz

Cc

collector capacitance

VCB = 10 V; IE = ie = 0 A; f = 1 MHz

[1]
[2]

See section "Test information" for resistor calculation and test conditions
Characteristics of built-in transistor

Table 10 starts with the break down voltages V(BR)CBO and V(BR)CEO, means break down voltagesof the collector-base path with an open emitter respectively collector-emitter path with an open
base.
Maximum leakage currents ICBO, ICEO and IBEO are informed next. These are the cut-off currents
for the collector-base, collector emitter and base-emitter path. The emitter-base cut-off current
values appear quite high compared to a stand-alone BJT. The reason for this is that the integrated
base resistors are located across this path. If an R2 resistor is present, the leakage current is
proportional to the sum of R1 and R2 at the specified conditions.

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Resistor Equipped Transistors (RETs): Key parameters and application insights
The hFE parameters for RETs are defined as IC/IIN. IIN is divided into the base current and thecurrent which flows through R2 which is IR2 = VBE/R2. Due to this fact hFE is smaller compared
to a RET with a series base resistor R1 only. And of course hFE is getting smaller the lower the
resistance of R2 is, because input current is drained away. This fact can be seen in Table 10
clearly.
VCEsat is the residual collector-emitter voltage in on-state of the RET switch. The test condition is to
apply 0.5 mA base drive and 10 mA collector current.
VI considerations
VI(off) informs at which input voltage the RET turns off. The test condition for off-state is to have acollector leakage current of 100 µA at a collector-emitter voltage of 5 V. The lower value provided
in the table as V(Ioff)max has to be considered as maximum allowed output level of the stage which
drives the RET. This condition has to be fulfilled for safe off-state of the RET.
For the other direction, the on-state, there is the important parameter VI(on)min to be considered.
The circuit controlling the RET has to provide this voltage for a safe turn on at least. As on-state
condition a collector current of 10 mA is defined while the collector-emitter voltage is 0.3 V. The
data sheet VI rating is valid for the test condition defined only. If a bigger collector current shall beswitched the RET requires more base drive voltage VI(on).
In Fig. 12 the switching characteristic of a RET is shown with a graph of VCE versus VI.
VI < VI(off)max: a RET is in off-state for every device shipped.
VI < VI(off)typ: a typical RET is in off-state.
VI > VI(on)typ: a typical RET is in on-state.
VI > VI(on)min: a RET is in on-state for every device shipped.
Fig. 12. RET Input voltage VI versus VCEcharacteristics
VCE

Off

On
VI(off)max

VI(off)typ

VI(on)typ

Input voltage

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Resistor Equipped Transistors (RETs): Key parameters and application insights
Table 11 shows the dependency of the on- and off-state input voltages on the resistor divider
configuration in RETs from the NHDTC series.
For the VI(off) condition a very small base current flows into the BJT (about 0.3 µA) . So the typicalvalue to turn off a RET is coupled almost directly to the resistor ratio R1/R2. It can be calculatedwith a voltage drop target across R2 or the base-emitter diode where the transistor is turned off.
This voltage is about 580 mV for the NHDTC series discussed. Therefore VI(off) values for a resistor
ratio equal 1 show the same voltages (rows 1-3 in Table 11).
The typical off-state voltages for R2 equal 47 kΩ and different R1 (2.2 kΩ, 4.7 kΩ and 10 kΩ ) arelower in accordance with the above described background. For VI(off) max an even value has been
defined which safeguards operation in the very left area of Fig. 12.
Table 11. VI(on) and VI(off) dependency on resistor configuration R1/R2
R1 / R2
VI(on) min
VI(on) typVI(on) max
VI(off) max
(kΩ)
(V)
(V)
(V)
(V)

RET Type

10 / 10

2.5

1.8

1.15

0.8

NHDTC114ET

22 / 22

3

2.3

1.15

0.8

NHDTC124ET

47 / 47

5

3.3

1.15

0.8

NHDTC144ET

2.2 / 47

1.2

0.81

595

0.5

NHDTC123JT

4.7 / 47

1.4

0.95

625

0.5

NHDTC114YT

10 / 47

1.6

1.22

690

0.5

NHDTC143ZT

The selection of a proper resistor divider option is important so that the control voltage window of
the RET fits well to the driving stage. The desired collector or load current has an impact on thebase current to be provided for the on-state. For a higher collector current a lower value for R1 and/or less bypass current through R2 is the direction to go.
For an application, temperature drift of the VI parameters needs some attention. VBE of BJTs
decreases over temperature with a coefficient of about -1.7 mV/K to -2.1 mV/K dependent on
chosen silicon diffusion details.
Current amplification hFE = IC/IB increases with about 1% per Kelvin for a stand-alone BJT.

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Resistor Equipped Transistors (RETs): Key parameters and application insights
In Fig. 13 the typical DC current gain as a function of collector current is shown for the ambient
temperatures 100 °C, 25 °C and -40 °C. Also for a RET with integrated poly-silicon resistor basedivider, hFE shows higher values the warmer Tamb becomes.
aaa-031707

103
hFE

(1)
(2)
(3)

102

10

1
10-1

1

10

IC (mA)102

VCE = 5 V
(1) Tamb = 100 °C(2) Tamb = 25 °C(3) Tamb = -40 °C
Fig. 13. NHDTC144EU: DC current gain as a function of collector current; typical values
In Fig. 14 of the data sheet, the typical On-state input voltage VI(on) is shown as a function of
IC. As to be expected a higher input voltage is required to drive more collector current at same
VCE. A low ambient temperature requires higher input voltage because VBE increases and hFE
drops. So turning on a RET switch at low temperature is the most critical operating condition for an
application and the user has to apply enough input voltage in order to turn on the device properly.
aaa-031709

102
VI(on)
(V)
10

(1)

1

(2)
(3)

10-1
10-1

1

10

IC (mA)102

VCE = 0.3 V(1) Tamb = -40 °C(2) Tamb = 25 °C(3) Tamb = 100 °C
Fig. 14. NHDTC144EU: On-state input voltage as a function of collector current; typicalvalues

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Resistor Equipped Transistors (RETs): Key parameters and application insights
Fig. 15 of the data sheet shows which VI(off) has to be applied typically to guarantee a safe turnoff of a RET switch. For this switching direction the input voltage has to be low enough for safe
operation. For the off-state high temperature condition is the most critical scenario. In this case thedriver circuit has to be designed in a way that it outputs a voltage well below typical VI(off) for thehighest temperature in the application.
aaa-031710

10

VI(off)
(V)
(1)

1

(2)
(3)

10-1
10-1

1

10

IC (mA)102

VCE = 5 V
(1) Tamb = -40 °C(2) Tamb = 25 °C(3) Tamb = 100 °C
Fig. 15. NHDTC144EU: On-state input voltage as a function of collector current; typicalvalues5. RET resistor specifics
R1, the series resistor towards the base of the BJT has a tolerance of typically +/- 30 %.
R2 is not defined directly but via a ratio R2/R1. This has a tolerance of ± 20% for 100 mA RETs and± 10% for 500 mA RETs as depicted in Table 12 below.
Table 12. Tolerances of integrated resistors in RETs
Resistor specification
Typical tolerances

RET types

R1

± 30%

all

R2/R1

± 20%

100 mA RETs

± 10%

500 mA RETs

This means for the range of R1:
R1min = 0.7 * R1typ
R1max = 1.3 * R1typ
For calculating the minimum and maximum values of R2, the tolerance for the resistor ratio has tobe considered. For 100 mA RETs it can be calculate with ± 20% tolerance according Tab.9:
R2min = 0.7 * R1typ * 0.8 * R2typ/R1typ = 0.56 * R2typ
R2max = 1.3 * R1typ * 1.2 * R2typ/R1typ = 1.56 * R2typ
The temperature dependency of the integrated polysilicon resistors can be described with thequadratic equation below. T0 is 25°C for the values provided in Tab. 10.
R(T) = R(T0) * ( 1 + α * (T – T0) + β * (T – T0)²)

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Resistor Equipped Transistors (RETs): Key parameters and application insights
Table 13 informs the coefficients α and β for Phosphorus-doped Poly-Silicon which is used forgeneration 1 RETs in Nexperia and Boron-doped Poly-Silicon used for generation 2 wafers. Fig. 16
shows the normalized resistance over temperature for these two process options. The resistance of
the integrated resistors decreases over temperature. The Boron-doped Poly-Silicon resistor show asmaller temperature dependance compared to the Phosphorus doping.
Table 13. Coefficients for thermal dependency of Poly-Silicon resistor values in RETsαβ
Phosphorus-doped Poly-Si-0.00229

7.26 * 10E-6

Boron-doped Poly-Si-0.00161

3.7275 * 10E-6

Fig. 16. Normalized resistance over temperature for Nexperia RETs
R(T)/
R25

aaa-033152

1.25

Gen 1: Phosphrous-doped Poly-Si
Gen 2: Boron-doped Poly-Si

1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
-60

-40

-20

0

20

40

60

80

100

120
140
160
Temperature (°C)

There are two more parameters in RET data sheets, (see Table 10) which are related to the
dynamic performance of these components; transition frequency fT and collector capacitanceCc. fT is the frequency where the current amplification of the BJT becomes equal to 1 for the test
condition defined.

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Resistor Equipped Transistors (RETs): Key parameters and application insights

6. Testing of RET resistors
The integrated resistors of RETs cannot be tested directly, because there is no access to the nodeof the base of the BJT. The resistors need to be tested between the contacts 1 and 2 as assigned
in Fig. 17. The collector contact is left floating.
3
1

R1

R2

2
aaa-033153

Fig. 17. RET with base resistor divider R1 and R2
For this test set up, an equivalent circuit can be depicted as shown in Fig. 18. The BJT is replaced
by a diode DBE representing the base-emitter path. The integrated resistors of the RET are present
with R1 and R2. The related voltages VBE representing the input voltage of the RET and thevoltage drop V1 at R1 respectively V2 at R2 are depicted.

V1

R1

VBE

IB
I2

ID
R2

V2

DBE

aaa-033154

Fig. 18. Equivalent circuit for testing of resistor divider values
Fig. 19 simplifies the circuit further if the polarity of VBE is taken into account. In case the voltage
applied has a positive polarity R2 is much bigger than RBE, so R2 can be neglected. In reverse
direction the base-emitter diode does not conduct, so the resistors themselves dominate the test
circuit.

R1

VBE

V1

IB

VBE
DBE

V2

R1

V1

R2

V2

IB

aaa-033155

Fig. 19. Simplified test circuit dependent on VBE polarity

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Resistor Equipped Transistors (RETs): Key parameters and application insights
Fig. 20 shows an I-V-curve of the base-emitter path, so VBE versus the input current IB, for an NPNRET with an R1 of 2.2 kΩ and R2 of 47 kΩ. The diagram is separated into 4 regions.
Region IV corresponds to reverse direction VBE, where in addition breakdown voltage of the baseemitter diode is exceeded. The steepness or dynamic resistance ∆V/∆I in this part of the curve is
R1, because the emitter-base diode clamps to the breakdown voltage.
Region III is the reverse blocking voltage range equivalent to the right part of Fig. 18. The
steepness is equivalent to R1 + R2. This value is tested in mass production under this condition.
Nexperia uses a two point testing method for a more exact measurement result, so R1 + R2 =∆VBE/∆IB.
In Region II the VBE path is biased in forward direction but the base-emitter diode is not conducting
significantly yet. The steepness of the curve is proportional to R1 + R2 like for Region III.
In Region I the diode conducts as depicted on the right side of Fig. 18. The curve ramps up with
R1 as steepness. To measure the steepness two operating points have to be chosen in order tocalculate ∆VBE/∆IB. R1 is measured following this test method in mass production. In Region I
single operating point measurement would not be sufficient because Vf of the base-emitter diodecreates an voltage offset of the curve that needs to be eliminated for resistor calculation. Fig. 21
shows an example where the two test points provide a good result for R1, with R1 = (V2 -V1) / (IB2
-IB1) as they are in the linear region of the curve.
With the value for R1 + R2 derived from Region III, R2 can be calculated easily and the ratio R2/R1
as well.
IB(A)

aaa-033156

3.0 m
2.5 m
2.0 m
1.5 m
1.0 m

500.0 µ0.0-500.0 µ
-10

-8

-6

-4

Region IV-2

Region III

02

VBE (V)

4

Region I

Region II

Fig. 20. Typical VBE versus IB curve for a RET with R1 = 2.2 kΩ and R2 = 47 kΩ
IB(A)

aaa-033157

400 µ
350 µ
300 µ
250 µ
200 µ

IB2
IB1

150 µ
100 µ
50 µ
0µ
0.0

0.2

0.4

0.6

0.8

Region II

1.0

1.2

VBE (V)

1.4

Region I

Fig. 21. Example for two test points on the I-V curve in Region I for calculation of theintegrated resistor R1

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Resistor Equipped Transistors (RETs): Key parameters and application insights

7. RETs exposed to ESD events
Bipolar transistors have a rather good ESD robustness compared to small size MOSFET
transistors. For MOSFETs the gate is the most vulnerable pin because gate oxide can getdamaged quite easily without a recovery from an exposure to surge events above the breakthroughvoltage. This is why most small-signal MOSFETs have an integrated gate-source ESD protection
nowadays. The ESD robustness level which is targeted for electronic components has the goal tosecure safe handling in mounting and board production. A standard level of robustness is a 2 kV
HBM (human body model) rating for ICs and discrete electronic components.
Discrete BJTs meet the target of a 2 kV HBM robustness without problems normally because pnjunctions facing a breakdown are not damaged if current and energy applied is comparably low.
In contrast RETs require some attention for ESD events because the integrated poly-silicon
resistors tend to be sensitive to surge pulses. This fact is not specific for any semiconductor
manufacturer in the market but requires general attention.
ESD damages can be seen at the resistor R1 most often. R2 is protected via the base-emitter
diode of the BJT which does either conduct in forward direction or clamps an incoming surge eventto a non-destructive level in reverse direction. Fig. 22 shows typical ESD related crystal damages
in the base resistor R1.

Fig. 22. Example for two test points on the I-V curve in Region I for calculation of theintegrated resistor R1
In modern ESD-safe manufacturing environment RETs can be mounted safely. If the base isattached to an interface for external connections, an additional external ESD protection might beconsidered.

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Resistor Equipped Transistors (RETs): Key parameters and application insights

8. Package overview for Nexperia RETs
Nexperia offers RETs in various package options. Table 14 shows the package types available
clustered into leaded and leadless types. The size of the package body is informed as well as thepower rating for a standard footprint on a single layer FR4 PCB.
The table shows that leadless packages provide a very good thermal performance while saving
board space. A DFN1006 RET performs as well as a much bigger SOT23 device. With a
DFN1412-6 RET up to 480 mW can be dissipated with a package area of 1.4 mm x 1.2 mm =1.68 mm² compared to 400 mW for a SOT457 and a much bigger package area of 4.35 mm². The
DFN1412 is 40% of the size of a SOT457 for the package body. In a design the occupied area
is even more important to be compared. For DFN1412 the occupied area is 1.6 mm x 1.71 mm= 2.736 mm². For SOT457 the area 5.3 mm x 5.05 mm = 26.765 mm² needs to be provided on aboard. So space saving is enormous for the DFN package as the factor is close to 10. The reason
is that the leads itself and the landing pads of a leaded package require significant extra spacecompared to a leadless device where the landing pads are almost under the package with small
areas outside the package body.
The thermal path from the crystal down into the PCB is short and direct. This is why Rth(j-sp) isvery small for DFN devices. Leadless packages allow a more compact design combined with ahigh power density. This helps designers to have a suitable solution for the industry trend towards
further miniaturization.
Table 14. Package options for RETs
Package
Packageclusternameleadedleadless[1]

AN90024

application note

RET
type

Size
(mm)

Ptot
(mW)
[1]

SOT23

single2.9 x 1.3 x 1

250

SOT323

single2 x 1.25 x 0.95

235

SOT457dual

2.9 x 1.5 x 1

400 (250)

SOT363dual

2 x 1.25 x 095

350 (235)

SOT666dual

1.6 x 1.2 x 0.55

300 (200)

DFN1006-3(SOT883)

single1 x 0.6 x 0.48

250

DFN1006B-3(SOT883B)

single1 x 0.6 x 0.37

250

DFN1010D-3(SOT1215)

single1.1 x 1 x 0.37

325

DFN1010B-6(SOT1216)

dual

1.1 x 1 x 0.37350 (230)

DFN1412-6(SOT1268-1)

dual

1.4 x 1.2 x 0.47

480 (325)

For dual types the first value is maximum power per device and the value in brackets is valid pertransistor.

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9. Revision history
Table 15. Revision history
Revision
Date
numberDescription

1.1

20210803

Minor formating corrections.

1.0

20210303

AN90024 initial version

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10. Legal information
Definitions
Draft — The document is a draft version only. The content is still underinternal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any representations or
warranties as to the accuracy or completeness of information included hereinand shall have no liability for the consequences of use of such information.

Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, Nexperia does not give any
representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for theconsequences of use of such information. Nexperia takes no responsibility
for the content in this document if provided by an information source outsideof Nexperia.
In no event shall Nexperia be liable for any indirect, incidental, punitive,
special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removalor replacement of any products or rework charges) whether or not suchdamages are based on tort (including negligence), warranty, breach ofcontract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, Nexperia’s aggregate and cumulative liability towards customer
for the products described herein shall be limited in accordance with theTerms and conditions of commercial sale of Nexperia.
Right to make changes — Nexperia reserves the right to make changes
to information published in this document, including without limitation
specifications and product descriptions, at any time and without notice. This
document supersedes and replaces all information supplied prior to the
publication hereof.
Suitability for use — Nexperia products are not designed, authorized or
warranted to be suitable for use in life support, life-critical or safety-criticalsystems or equipment, nor in applications where failure or malfunctionof an Nexperia product can reasonably be expected to result in personal
injury, death or severe property or environmental damage. Nexperia and its
suppliers accept no liability for inclusion and/or use of Nexperia products insuch equipment or applications and therefore such inclusion and/or use is at
the customer’s own risk.
Applications — Applications that are described herein for any of theseproducts are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using Nexperia products, and Nexperia accepts no liability forany assistance with applications or customer product design. It is customer’ssole responsibility to determine whether the Nexperia product is suitableand fit for the customer’s applications and products planned, as well as
for the planned application and use of customer’s third party customer(s).
Customers should provide appropriate design and operating safeguards tominimize the risks associated with their applications and products.
Nexperia does not accept any liability related to any default, damage, costs
or problem which is based on any weakness or default in the customer’s
applications or products, or the application or use by customer’s third party
customer(s). Customer is responsible for doing all necessary testing for thecustomer’s applications and products using Nexperia products in order toavoid a default of the applications and the products or of the application or
use by customer’s third party customer(s). Nexperia does not accept any
liability in this respect.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a priorauthorization from competent authorities.
Translations — A non-English (translated) version of a document is forreference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.

Trademarks
Notice: All referenced brands, product names, service names andtrademarks are the property of their respective owners.

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Resistor Equipped Transistors (RETs): Key parameters and application insights

List of Tables
Table 1. Nomenclature single RETS....................................3
Table 2. Nomenclature Double RETs...................................3
Table 3. Product overview....................................................7
Table 4. Quick reference data..............................................7
Table 5. Pinning................................................................... 8
Table 6. Ordering information.............................................. 8
Table 7. Marking.................................................................. 8
Table 8. Limiting values....................................................... 9
Table 9. Thermal characteristics........................................ 11
Table 10. Characteristics....................................................13
Table 11. VI(on) and VI(off) dependency on resistor
configuration R1/R2........................................................... 15
Table 12. Tolerances of integrated resistors in RETs......... 17
Table 13. Coefficients for thermal dependency of PolySilicon resistor values in RETs.......................................... 18
Table 14. Package options for RETs..................................22
Table 15. Revision history..................................................23

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Resistor Equipped Transistors (RETs): Key parameters and application insights

List of Figures
Fig. 1. NPN RET with base resistor R1............................... 2
Fig. 2. NPN RET with base divider R1 and R2.................... 2
Fig. 3. Basic control BJT circuit with an NPN-RET.............. 4
Fig. 4. Basic control BJT circuit with an NPN-RET.............. 4
Fig. 5. Load switch with PNP RET in load path and
NPN RET in control path..................................................... 5
Fig. 6. RETs in wired-NOR application................................ 5
Fig. 7. RETs in wired-NAND application.............................. 6
Fig. 8. Application example push-pull stage with RETs........6
Fig. 9. Power derating curves SOT323 (SC-70)................ 10
Fig. 10. Transient thermal impedance from junction toambient as a function of pulse duration; typical values...... 12
Fig. 11. Transient thermal impedance from junction toambient as a function of pulse duration; typical values...... 12
Fig. 12. RET Input voltage VI versus VCEcharacteristics.. 14
Fig. 13. NHDTC144EU: DC current gain as a functionof collector current; typical values......................................16
Fig. 14. NHDTC144EU: On-state input voltage as afunction of collector current; typical values........................ 16
Fig. 15. NHDTC144EU: On-state input voltage as afunction of collector current; typical values........................ 17
Fig. 16. Normalized resistance over temperature for
Nexperia RETs................................................................... 18
Fig. 17. RET with base resistor divider R1 and R2............ 19
Fig. 18. Equivalent circuit for testing of resistor divider
values................................................................................. 19
Fig. 19. Simplified test circuit dependent on VBE polarity.. 19
Fig. 20. Typical VBE versus IB curve for a RET with
R1 = 2.2 kΩ and R2 = 47 kΩ............................................ 20
Fig. 21. Example for two test points on the I-V curve inRegion I for calculation of the integrated resistor R1......... 20
Fig. 22. Example for two test points on the I-V curve inRegion I for calculation of the integrated resistor R1......... 21

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Resistor Equipped Transistors (RETs): Key parameters and application insights

Contents
1. Introduction................................................................... 2
2. RET basics: topologies and nomenclature................ 2
3. Application Examples.................................................. 4
4. Data sheet parameters................................................. 7
5. RET resistor specifics................................................17
6. Testing of RET resistors............................................ 19
7. RETs exposed to ESD events....................................21
8. Package overview for Nexperia RETs....................... 22
9. Revision history..........................................................23
10. Legal information......................................................24© Nexperia B.V. 2021. All rights reserved

For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 3 August 2021

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