2015 International Conference
on IC Design & Technology(ICICDT 2015)

Leuven, Belgium
1-3 June 2015

IEEE Catalog Number:
ISBN:

CFP15412-POD
978-1-4799-7670-6

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978-1-4799-7670-6

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TABLE OF CONTENTSSESSION A: LOW POWER MEMORY TECHNOLOGY AND CIRCUITS
Session Chair: Hideto Hidaka

Invited - Selectors for High Density Crosspoint Memory Arrays: Design Considerations, Device
Implementations and Some Challenges Ahead ................................................................................................................... 1
Bogdan Govoreanu, Leqi Zhang, Malgorzata Jurczak

Current Pulse Generator for Multilevel Cell Programming of Innovative PCM............................................................. 5Athanasios Kiouseloglou, Gabriele Navarro, Alessandro Cabrini, Guido Torelli, Luca Perniola

Design Technology Co-optimization for Enabling 5nm gate-all-around Nanowire 6T SRAM ....................................... 9Trong Huynh-Bao, Sushil Sakhare, Julien Ryckaert, Dmitry Yakimets, A. Mercha, D. Verkest, Aaron Voon-Yew
Thean, Piet Wambacq

Assessment of SiGe Quantum Well Transistors for DRAM Peripheral Applications ................................................... 13
R. Ritzenthaler, T. Schram, G. Eneman, A. Mocuta, N. Horiguchi, A. V.-Y. Thean, A. Spessot, M. Aoulaiche, P.
Fazan

Low Standby Power Capacitively Coupled Sense Amplifier for Wide Voltage Range Operation ofDual Rail SRAMs................................................................................................................................................................. 17Anuj Grover, Promod Kumar, Mohammad Daud, G. S. Visweswaran, Chittoor Parthasarathy, Jean-Philippe Noel,David Turgis, Bastien Giraud, Guillaume Moritz

A 6T-SRAM in 28nm FDSOI Technology with Vmin of 0.52V Using Assisted Read and WriteOperation.............................................................................................................................................................................. 21
Ashish Kumar, Vinay Kumar, Dhori Kedar Janardan, G.S.Visweswaran, Kaushik SahaSESSION B – EMERGING TECHNOLOGIES
Session Chairs: Thomas Ernst And Denis Flandre

Invited - NEMS Switches: Opportunities and Challenges in Emerging IC Technologies ............................................. 25Philip X.-L. Feng

Wide Band Study of Silicon-on-Insulator Photodiodes on Suspended Micro-Hotplates Platforms.............................. 31
N. André, G. Li, P. Gérard, O. Poncelet, Y. Zeng, S.Z. Ali, F. Udrea, L.A. Francis, D. Flandre

Evaluation of 32-Bit Carry-Look-Ahead Adder Circuit with Hybrid Tunneling FET and FinFETDevices .................................................................................................................................................................................. 35
Tse-Ching Wu, Chien-Ju Chen, Yin-Nien Chen, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang

Area and Routing Efficiency of SWD Circuits Compared to Advanced CMOS............................................................ 39Odysseas Zografos, P. Raghavan, Yasser Sherazi, Adrien Vaysset, Florin Ciubatoru, Bart Soree, Rudy Lauwereins,Iuliana Radu, Aaron TheanSESSION C – HIGH FREQUENCY BUILDING BLOCKS
Session Chairs: Stefano D’amico And Andrea Scarpa

Low-Phase Noise Variation VCO Implementing Resistorless Digitally Controlled Varactor....................................... 43
Mohammed Aqeeli, Abdullah Alburaikan, Xianjun Huang, Zhirun Hu

SESSION D: ADVANCED TRANSISTORS AND MATERIALS
Session Chairs: Bich-Yen Nguyen And Dina H. Triyoso

Invited - Dimensioning for Power and Performance Under 10nm: The Limits of FinFETs Scaling............................ 47
M. Garcia Bardon, P. Schuddinck, P. Raghavan, D. Jang, D.Yakimets, A. Mercha, D. Verkest, A. Thean

Impact of Fin Shape Variability on Device Performance Towards 10nm Node............................................................. 51
Kazuyuki Tomida, Keizo Hiraga, Morin Dehan, Geert Hellings, D. Jang, Kenichi Miyaguhi, Thomas Chiarella,
Minsoo Kim, A. Mocuta, Naoto Horiguchi, A. Mercha, D. Verkest, Aaron TheanModeling FinFET Metal Gate Stack Resistance for 14nm Node and Beyond ................................................................ 55
Kenichi Miyaguchi, Bertrand Parvais, Lars-Åke Ragnarsson, Piet Wambacq, P. Raghavan, A. Mercha, A. Mocuta,
D. Verkest, Aaron Thean

Static and Dynamic Power Management in 14nm FDSOI Technology........................................................................... 59
O. Weber, E. Josse, J. Mazurier, M. HaondLateral NWFET Optimization for Beyond 7nm Nodes .................................................................................................... 63
D. Yakimets, D. Jang, P. Raghavan, G. Eneman, H. Mertens, P. Schuddinck, A. Mallik, M. Garcia Bardon, N.
Collaert, A. Mercha, D. Verkest, A. Thean, K. De Meyer

Nonparabolicity and Confinement Effects of IIIV Materials in Novel Transistors ....................................................... 67
M. Ali Pourghaderi, A. Mocuta, Aaron TheanSESSION E – ADVANCED CMOS DEVICE RELIABILITY
Session Chairs: Koji Eriguchi And Yuichiro Mitani

Invited - PBTI for n-type Tunnel FinFETs........................................................................................................................ 70
W. Mizubayashi, T. Mori, K. Fukuda, Y. X. Liu, T. Matsukawa, Y. Ishikawa, K. Endo, S. O’uchi, J. Tsukada, H.
Yamauchi, Y. Morita, S. Migita, H. Ota, M. Masahara

Reliability Impact of Advanced Doping Techniques for DRAM Peripheral MOSFETs ............................................... 74
A. Spessot, R. Ritzenthaler, T. Schram, M. Aoulaiche, M. Cho, Maria Toledano Luque, Naoto Horiguchi, P. Fazan

Impact of Random Telegraph Noise on Ring Oscillators Evaluated by Circuit-level Simulations............................... 78
Azusa Oshima, P. Weckx, B. Kaczer, Kazutoshi Kobayashi, Takashi Matsumoto

Simple Technique for Prediction of Breakdown Voltage of Ultrathin Gate Insulator Under ESD
Testing .................................................................................................................................................................................. 82
Yuichiro Mitani, Kazuya Matsuzawa

Off-State Stress Degradation Mechanism on Advanced p-MOSFETs ............................................................................ 86
M. Cho, A. Spessot, B. Kaczer, M. Aoulaiche, R. Ritzenthaler, T. Schram, P. Fazan, Naoto Horiguchi, Dimitri
LintenSESSION F - CAD AND RELIABILITY CHALLENGES IN ADVANCED TECHNOLOGIES
Session Chair: Wei Guo And Thuy Dao

Invited - Deadspace-aware Power/Ground TSV Planning in 3D Floorplanning............................................................ 90
Shengcheng Wang, Farshed Firouzi, Fabian Oboril, Mehdi B. Tahoori

Impact of Device and Interconnect Process Variability on Clock Distribution.............................................................. 94
Nathalie Fievet, P. Raghavan, Rogier Baert, Frederic Robert, A. Mercha, D. Verkest, Aaron Thean

Impact of Time-dependent Variability on the Yield and Performance of 6T SRAM Cells in an
Advanced HK/MG Technology .......................................................................................................................................... 98
P. Weckx, B. Kaczer, J. Roussel, F. Catthoor, G. Groeseneken

Countering Early Propagation and Routing Imbalance of DPL Designs in a Tree-based FPGA............................... 102
Emna Amouri, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger

FinFET Stressor Efficiency on Alternative Wafer and Channel Orientations for the 14 nm Node andBelow................................................................................................................................................................................... 106
G. Eneman, A. De Keersgieter, A. Mocuta, N. Collaert, A. TheanSESSION G – POWER DEVICE RELIABILITY AND PLASMA-INDUCED DAMAGE
Session Chairs: Yuichiro Mitani And Koji Eriguchi

Invited - Trapping Induced Parasitic Effects in GaN-HEMT for Power Switching Applications.............................. 110
Gaudenzio Meneghesso, Matteo Meneghini, Enrico Zanoni, Piet Vanmeerbeek, Peter Moens

Plasma Induced Damage Investigation in the Fully Depleted SOI Technology............................................................ 114
M. Akbal, G. Ribes, M. Guillermet, L. Vallier

Plasma-induced Photon Irradiation Damage on Low-k Dielectrics Enhanced by Cu-line Layout............................. 118
Taro Ikeda, Akira Tanihara, Nobuhiko Yamamoto, Shigeru Kasai, Koji Eriguchi, Kouichi Ono

Surface Orientation Dependence of Ion Bombardment Damage During Plasma Processing ..................................... 122
Yukimasa Okada, Koji Eriguchi, Kouichi Ono

SESSION H - ANALOG AND MIXED-SIGNAL TECHNIQUES
Session Chair: Stefano D’amico And Andrea Scarpa

Invited - High-Speed Analog-to-Digital Converters in Downscaled CMOS ................................................................. 126
Annachiara Spagnolo, Bob Verbruggen, Stefano D’Amico, Piet Wambacq

Overview of Methods to Increase Linearity of High-performance ADC ...................................................................... 130
Hua Fan, Kehong Liu, Airong Liu, Lishan Lv, Zhiliang Qiao, Qiang Li

Optimal Design to Maximize Efficiency of Single-Inductor Multiple-Output Buck Converters in
Discontinuous Conduction Mode for IoT Applications .................................................................................................. 134
Yoshitaka Yamauchi, Yuki Yanagihara, Hiroshi Fuketa, Takayasu Sakurai, Makoto Takamiya

SESSION I - HIGH-POWER / HIGH-VOLTAGE
Session Chairs: Jan Ackaert And Thuy Dao

Invited - Thermal Experimental and Modeling Analysis of High Power 3D Packages ............................................... 138
H. Oprins, V. Cherman, G. Van der Plas, F. Maggioni, J. De Vos, E. Beyne

Metallization Scheme Optimization of Plasticencapsulated Electronic Power Devices ............................................... 142
Jan Ackaert, Tony Colpaert, Aditi Malik, Mario Gonzalez

I/O Thick Oxide Device Integration Using Diffusion and Gate Replacement (D&GR) Gate Stack
Integration.......................................................................................................................................................................... 146
R. Ritzenthaler, T. Schram, M. Cho, A. Mocuta, N. Horiguchi, A. V.-Y. Thean, A. Spessot, C. Caillat, M. Aoulaiche,
P. Fazan

Characterization of Onset Tunneling Voltage (Vonset) Walkout in High-Voltage Deep Trench
Isolation on SOI ................................................................................................................................................................. 150
Thuy Dao, Mu-Ling Ger, Jiangkai Zuo

SESSION J – I/O CIRCUITS AND ESD PROTECTION
Session Chairs: Philippe Galy And Lorenzo Cerati

Invited - Integrated Front-End/Back-End Simulation of Electromagnetic Fields, Lorentz Force
Effects and Fast Current Surges in Microelectronic Protection Devices ...................................................................... 154
Wim Schoenmaker, P. Galy

Impact of Local Interconnects on ESD Design................................................................................................................ 158
Mirko Scholz, Shih-Hung Chen, Geert Hellings, Dimitri Linten, Roman Boschke

ESD Protection Diodes in Optical Interposer Technology ............................................................................................. 162
Roman Boschke, G. Groeseneken, Mirko Scholz, Shih-Hung Chen, Geert Hellings, Peter Verheyen, Dimitri Linten

Preliminary 3D TCAD Electro-thermal Simulations of BIMOS Transistor in Thin Silicon Film for
ESD Protection in FDSOI UTBB CMOS Technology .................................................................................................... 166
S. Athanasiou, S. Cristoloveanu, P. Galy

A High-Speed 2xVDD Output Buffer With PVTL Detection Using 40-nm CMOS Technology................................. 170
Chua-Chin Wangy, Tsung-Yi Tsai, Wei Lin

SESSION K – 3D INTEGRATION AND LOWER POWER PROCESSORS
Session Chairs: Bich-Yen Nguyen And Juergen Pille

Invited - 3D Monolithic Integration: Stacking Technology and Applications .............................................................. 174
Ionut Radu, Bich-Yen Nguyen, Gweltaz Gaudin, Carlos Mazure

Through Silicon Via to FinFET Noise Coupling in 3-D integrated Circuits ................................................................. 177
A. Rouhi Najaf Abadi, W. Guo, X. Sun, K. Ben Ali, J.P Raskin, M. Rack, C. Roda Neve, M.Choi, V. Moroz, G. Van
der Plas, I. De Wolf, E. Beyne , P. Absil

Simple Wafer Stacking 3D-FPGA Architecture ............................................................................................................. 181
Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi

Design of a Low-power Fixed-point 16-bit Digital Signal Processor Using 65nm SOTB Process ............................... 185
Duc-Hung Le, Nobuyuki Sugii, Shiro Kamohara, Xuan-Thuan Nguyen, Koichiro Ishibashi, Cong-Kha PhamPower Measurements and Cooling of the Dome 28nm 1.8GHz 24-thread ppc64 µServer Compute
Node .................................................................................................................................................................................... 189
Ronald P. Luijten, Matteo Cossale, Rolf Clauberg, Andreas DoeringAuthor Index