AN50006

Power MOSFETs in linear modeRev. 2.0 — 12 April 2022

application note

Document information
Information

Content

Keywords

linear mode, saturation, MOSFET, SOA, temperature instability, Spirito effect, LDO, active clamp,
airbag, soft start, hot swap

Abstract

Understanding MOSFET’s linear mode operation and thermal instability while applying SOA
temperature derating methods to design more robust and reliable circuits

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Power MOSFETs in linear mode

1. Introduction
Power MOSFETs are extensively used as switches due to the very low RDSon and thus low
conduction losses. However, in many applications MOSFETs are used in their saturated state, withcertain cases requiring both these modes to be robust and performant within the same device.
This application note aims to describe the main characteristics of linear mode operation from atheoretical standpoint. Nevertheless, application-oriented topics are discussed in case of HotSOA derating and pulse shape conversion, while examples of schematics are given in the relative
paragraphs.

2. Linear mode definition
During linear mode a MOSFET operates in its saturated state, or saturation region, and it behaves
as a (gate) voltage controlled current source. Contrary to what happens when fully ON (or fullyenhanced), the drain-source impedance is relatively high, resulting in high power dissipation. In
linear mode, the power is given by the product of the drain current and the drain-source voltage(ID × VDS), which are both high at the same time.
Linear mode can be described analytically by the set of equations below. The MOSFET needs
to be ON (Equation 1) and the VDS greater than the overdrive voltage (VOD) (Equation 2). If theprevious two conditions are met the drain current will be proportional to the square of VOD (thus theapplied VGS) as shown in Equation 3, where k is a technological parameter fixed with the type oftrench technology used.

VGS > VGS(th)VDS > VGS

(1)

VGS(th) = VOD

I D = k ( VGS

VGS(th) )

2

(2)
(3)

The MOSFET’s output characteristic (Fig. 1) describes how ID changes with respect to VDS and
VGS:
•
•

For low VDS and around VGS of 7 V to 10 V, there is a linear relationship between current andvoltage. The MOSFET operates in its linear region (or ohmic region) and it behaves like a2
resistor (fully ON). In this case the power dissipated is low and given by ID × RDSon.
For higher VDS, and a given VGS, ID remains fairly constant. In saturation region, the current
increases as VGS increases. In this case the power dissipated is high and given by VDS × ID.

MOSFETs can operate in linear mode in two ways: indirectly, for a short time, as a consequence ofswitching or directly, for much longer time. In fact, linear mode is traversed every time a MOSFET
switches ON and OFF. With reference to Fig. 1, during turn ON the MOSFET’s working point
moves from high VDS and zero ID (OFF state) to a low VDS and high ID (curve 1). If the end goal
is to use the MOSFET as a switch then it is usually good practice to try to reduce the time andpower dissipated in linear mode, for instance by decreasing the switching time. Conversely, certain
applications require MOSFETs to purposely operate in linear mode (curve 2). In this case it isrecommended to:••AN50006

application note

Guarantee that the device operates within the SOA curve, for a given pulse duration andmounting base temperature (Tmb).
Employ adequate thermal management techniques.

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Power MOSFETs in linear mode

[1] RDSon operation ON/OFF trajectory; [2] linear mode operation ON/OFF trajectory
Fig. 1.

Example of MOSFET output characteristic: ON/OFF trajectories

3. Example of typical linear mode applications
3.1. Airbag applications

Fig. 2.

Airbag application schematic and waveforms

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3.2. Active clamp

Fig. 3.

Active clamp schematic and waveforms

3.3. Capacitor pre-charge (soft start / hot swap)

Fig. 4.

Soft start schematic and waveforms

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Power MOSFETs in linear mode

3.4. LDO (low dropout) regulators

Fig. 5.

LDO schematic and waveforms

4. SOA graph
The safe operating area (SOA) graph gives an indication of the amount of power a device cansafely handle before failing. The graph shows the drain current plotted against the drain-source
voltage. The limit depends on the time duration of the power and the working region the MOSFET
operates in. The graph is valid only for a constant mounting base temperature of 25 ˚C and either asingle pulse or DC operation. The SOA is especially useful in case of linear mode operation. Fig. 6
shows the area below which a MOSFET can safely and reliably operate for a pulse of 1 ms and thelimit at VDS = 3 V and pulse of 1 ms.

Fig. 6.

SOA: maximum current limits for 1 ms and at VDS = 3 V and 1 ms pulse
Fig. 7 shows how the SOA graph can be subdivided depending on the MOSFET’s working region(a time pulse of 1 ms is considered). In yellow the line corresponding to the limit in RDSon mode,

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Power MOSFETs in linear modein green the limit imposed by the package and in blue by avalanche (at the maximum rated
voltage, before avalanche occurs). For a more in-depth description of the SOA limits see AN11158:
Understanding power MOSFET data sheet parameters (3.1 Safe Operating Area (SOA) curves).
The red line shows the limit during linear mode operation. This limit is verified experimentally bykeeping VDS constant while the current is pulsed for a given duration. As shown in Equation 4, it
depends on the thermal impedance of the MOSFET (Zth), maximum junction temperature (Tj(max) =175 ˚C) and mounting base temperature (Tmb).

Tj(max) - Tmb
P = ID VDS = −ZthFig. 7.

(4)

SOA graph; curve limits
From Equation 4 it follows that the limit increases (more power can be dissipated) as the time
pulse decreases, since the Zth decreases with shorter time pulses (see Fig. 8). Finally, the dashed
red line indicates the Spirito region, where thermal instability occurs, more on this topic in section
Section 5.1.
aaa-028016

1
Zth(j-mb)
(K/W)

10-1

δ = 0.5
0.2
0.1
0.05

10-2

0.02

P

δ=

T

single shot
tp

10-3
10-6

tp

10-5

10-4

10-3

10-2

10-1

t
T
tp (s)

1

Tmb = 25 °C; IDM is a single pulse
Fig. 8.

Transient thermal impedance from junction to mounting base as a function of pulse duration; typicalvaluesAN50006

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Power MOSFETs in linear mode

5. Temperature dependency
5.1. Thermal instability
For a fixed VDS, the variation of drain current against gate bias voltage is plotted in the transfer
characteristic graph, shown in Fig. 9. Two lines are used to show the MOSFET operation at ajunction temperature of 25 ˚C (solid line) and 175 ˚C (dashed line). For a low enough VGS, the
MOSFET will conduct more current if it operates at 175 ˚C than at 25 ˚C, due to the negative
temperature coefficient of the threshold voltage (VGSth), as shown in Fig. 10. In this case the
MOSFET is operating in a region of thermal instability, identified by a positive temperature
coefficient of the current. This holds true even when considering a single spot on the silicon die.
ID
(A)

25 °C

negative temp.
coefficient

175 °CZTC point

positive temp.
coefficient

VGS (V)
aaa-002474

Fig. 9.

Transfer characteristics showing regions of positive and negative temperature
coefficient

However, this phenomenon can be avoided. In fact, for a given VDS, there is a critical current
above which there is a negative feedback and thus thermal stability. This is known as the Zero
Temperature Coefficient (ZTC) point.

VGS(th)(V)

aaa-018139

5

4
Max
3

Typ

2
Min
1

0
-60

-30

0

30

60

90

120 150
Tj (°C)180

ID = 1 mA; VDS = VGS
Fig. 10. Gate-source threshold voltage as a function of junction temperature

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Power MOSFETs in linear mode
On the SOA graph, thermal instability is indicated by a two-slopes line and an additional inflexion
point, as shown in Fig. 11 (the inflexion point is located at 5 V for a 1 ms pulse). The theoreticallimit, in the dashed blue line, is calculated using Equation 4, where Zth = Zth(j-mb). This limit canbe found using an RC thermal model, like the Cauer model shown in Fig. 12. The dashed redline indicates the real performance of the device. In this case Zth≠ Zth(j-mb) and therefore the limit
cannot be found using an electrical model. The reduction in performance can be quite severe: inthis case for a VDS of 20 V, the maximum current the MOSFET can handle goes from a theoretical
60 A down to around 15 A (75% less). This phenomenon is also known as Spirito effect, and it is1

caused by the uneven distribution of current across the silicon die . Below the ZTC point, if a small
region is at a higher temperature than the rest of the die, it will draw more current and dissipate
more power becoming even hotter. This process eventually leads to thermal runaway and thedestruction of the MOSFET as a three-terminal short. Burn marks will appear near the center ofthe die and close to the die bonding structure, as documented in AN11243: Failure signature ofelectrical overstress on power MOSFETs (1.3 Linear mode operation).

Fig. 11. SOA graph: Spirito effectMoreover, these hotspots are observed to occur more frequently at wider power pulses. Withreference to Fig. 11, for a time pulse of 10 ms the Spirito effect takes place at a lower VDS (around3 V) than for the 1 ms pulse (5 V) while DC operation is limited by thermal instability at any voltage.
R2

R1
C1

C2

Rn
Cn

aaa-031516

Fig. 12. Cauer RC thermal model
The uneven distribution of current across the silicon die is influenced by uniformity of the MOSFET
cells and integrity and uniformity of the die attachment. Besides, the type of die bonding technology
can also have a significant impact. As shown in Fig. 13, wire bonding increases current density insmall points of the die that can become hot spots. On the other hand, the copper clip of an LFPAK
prevents localised current crowding reducing the likelihood of hot spot formation.

1 Electro-thermal instability in low voltage power MOS: Experimental characterization - IEEE; G. Breglio, F.
Frisina, A. Magri, P. Spirito

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Power MOSFETs in linear mode

JDC Vol
2(A/m )

9.7768e+008
9.1661e+008
8.5554e+008
7.9447e+008
7.3340e+008
6.7233e+008
6.1126e+008
5.5019e+008
4.8912e+008
4.2805e+008
3.6698e+008
3.0592e+008
2.4485e+008
1.8387e+008
1.2271e+008
6.1638e+007
5.6895e+005

JDC Vol
2(A/m )

1.4914e+008
1.3394e+008
1.3074e+008
1.2154e+008
1.1234e+008
1.0314e+008
9.3937e+007
8.4737e+007
7.5536e+007
6.6336e+007
5.7136e+007
4.7936e+007
3.8735e+007
2.9535e+007
2.0335e+007
1.1134e+007
1.9341e+006a) LFPAK88b) D2PAK

Note: current density contour scaling is different for LFPAK88 and D2PAK, see accompanying colour scaling
Fig. 13. Current crowding contours for a) LFPAK88 and b) D2PAK packages
Also, cell density influences the shape of the SOA. Older trench (or planar) technologies show ahigher RDSon, due to the wider cell pitch and thus lower cell density. For a given total drain current,
cells in older technologies are more likely to operate beyond the ZTC point, where operation isthermally stable, since the current per cell is higher. Consequently, for a given die size, older trench(or planar) technologies show a higher RDSon but in turn perform better in linear mode.
The innovation introduced with new trench structures has deeply increased performances insome of the other fields, particularly in switching, avalanche and steady state behavior. Newer
technologies show generally worse linear mode capability, however, whenever harder requirements
have to be met the designer can either choose (in case the thermal design cannot be improved): a
MOSFET with lower Rth(j-mb) (corresponding to a bigger die), a bigger package, an older technology(with lower cell density) or a MOSFET from Nexperia’s ASFET portfolio with Enhanced SOA
capability.

5.2. Hot-SOA derating
The SOA graph in Nexperia’s data sheets is valid only for a mounting base temperature of 25 ˚C. If
the mounting base is held at a different temperature, then the graph must be derated, as generally
the capability at other temperatures is not characterized. In this case, either an approximated or an
exact indication of the new limit is found, depending on the device’s working region.
There are three main derating methods depending on which quantity is scaled or kept constant. If
the current is scaled, then the voltage will remain constant, vice versa if the voltage is scaled, thecurrent will remain constant. The third option is to scale both voltage and current thus keeping thepower constant. The RDSon, package, breakdown and linear mode limits are all predicted in thesame way by these methods. The only difference is in how the Spirito region is approximated, i.e.
the position of the inflexion point. For a given VDS the current scaling method returns the highest
limit, while the voltage scaling the lowest. Generally, when compared with a measured Hot-SOA
every method is observed to underestimate the device’s real performance, which gives somesafety margin from thermal instability. As shown in Fig. 14 the current scaling method usually gives
the best Spirito approximation. Table 1 summarizes the current limits predicted using the threemethods and measurement at VDS = 30 V, Tmb = 125 ˚C and pulse of 1 ms.

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Power MOSFETs in linear mode
aaa-034886

10 3
ID

(A)
10

2

measured

V

10

V&I
1

I
-1

10

10

-1

1

10

V DS (V)102

Fig. 14. Example of SOA derating methods against measurement for the BUK7Y2R0-40H
Table 1. Scaling methods against measured data
ID limit: VDS = 30 V; Tmb = 125 ˚C; pulse width = 1 ms
Measured

Current scaling

Voltage scaling

Power scaling

4A

1.5 A

1A

0.4 A

Before applying any of these methods, the power scale factor (kPSF) must be calculated. Thiscan be obtained by looking at the plot in Fig. 15, or using Equation 5. The graph is given in any
Nexperia’s data sheet and represents the normalized power dissipation as a function of mounting
base temperature. Due to its double scaling, the power scaling method make use of a different
coefficient calculated using Equation 6.
03na19

120
Pder
(%)
80

50 %
40

0

0

50

100

150

Tmb (°C)

200

Fig. 15. Normalized total power dissipation as a function of mounting base temperature:
power scale factor

175 °C - Tmb
kPSF = −175 °C - 25 °C
kPSF, pwr =AN50006

application note

175 °C - Tmb
kPSF = −175 °C - 25 °C

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(6)

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Power MOSFETs in linear mode
As an example, a MOSFET’s current limit is calculated using the current scaling method for
Tmb = 100 ˚C, VDS = 3 V and a pulse width of 1 ms:
1. The current limit at Tmb = 25 ˚C is 400 A, as shown in Fig. 16.
2. kPSF is calculated using Equation 5 and is exactly 0.5 (i.e. 50%).
3. The new limit at Tmb = 100˚C is 200 A, as calculated using Equation 7.

ID,limit (@100 °C) = kPSF ID,limit (@25 °C)
ID
(A)

(7)

aaa-028017

103

400

Limit RDSon = VDS / ID

tp = 10 µs

100 µs

102

DC
10
1 ms
10 ms
100 ms

1
10-1

1

3

10

VDS (V)102

Fig. 16. Data sheet SOA: current limit for Tmb = 25˚C
The complete Hot-SOA graph can be found by taking the following steps (current scaling method isused but this can be adapted to the other methods):
•
•
•
ID
(A)

The RDSon limit is not derated since it is calculated using RDSon at 175 ˚C.
Linear mode inflexion point and breakdown limit are shifted downwards, the new current limits
are found using the power scale factor (in this case 0.5). A new inflexion point for the Spirito
region is generated at half the current of the original one.
Finally, the lines can be extended to the endpoints using the same slope.
aaa-028017

103
Limit RDSon = VDS / ID

tp = 10 µs

100 µs102DC
10

5 V, 220 A

5 V, 110 A
1 ms

1
10-1

10 ms
100 ms1

10

VDS (V)102

Fig. 17. Derated SOA limits for Tmb = 100 ˚C and pulse of 1 ms, using current scaling method

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Power MOSFETs in linear mode

6. SOA: pulse shape conversion
In certain applications the power may not be a rectangular pulse, or the duration be different fromthe set given in the SOA graph. In both cases a power shape conversion can be carried out andoperation within SOA verified. This conversion is exact if the MOSFET is operating in ohmic modeor linear mode. However, it might be inaccurate for operation in the Spirito region.
If the MOSFET is not working in Spirito region, the pulse can be converted into a rectangular one
carrying the same amount of energy, by adjusting either the duration or the peak. Fig. 18 shows theconversion for a triangular power pulse. If the pulse duration is not part of the SOA graph, the limit
can be calculated using the value of thermal impedance found in the data sheet (or an RC thermal
model) and Equation 4. The use of thermal and electrothermal models is always recommended toaccurately predict the junction temperature.

Fig. 18. Power shape conversion of triangular pulse with MOSFET operating outside theSpirito region
If the device is working in Spirito region, the pulse cannot be converted by means of the thermal
impedance. In this case, the use of thermal and electrothermal models gives only an averagejunction temperature, which doesn’t reflect hot spots’ temperature. A conservative approach would
be to consider a rectangular pulse with the same peak and duration of the original one. However,
empirical evidence would suggest that triangular pulses can be converted into rectangularones having same duration but half the peak value. Testing has been conducted using theBUK7S1R0-40H and the active clamp circuit shown in Fig. 19. It is worth noting that these results
should be considered valid only for this specific device.

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Power MOSFETs in linear mode

Fig. 19. Active clamp circuit using the BUK7S1R0-40H
Active clamping is used in inductive switching, similarly to avalanche, however the device operates
in linear mode at a lower clamping voltage than in avalanche. With switch sw1 on the closed
position and MOSFET M1 turned ON, current can flow through the main circuit. Once the inductor
is “charged” the MOSFET is switched OFF. The energy stored in the inductor induces a highvoltage that breaks down the Zener diode ZD1. This, in turn, clamps the gate voltage turning ON
the MOSFET, which absorbs the energy released by the inductor. During this last activation the
MOSFET is working in linear mode, the VDS is fairly constant while its drain current decreases, as
shown in Fig. 20 (simulated). Therefore, the dissipated power is a triangular pulse lasting 1 ms.
ID

40

(A)

35

V DS

30

(V)

aaa-034875

ID

25

V DS

20
15
10
5
0
-5

0

0.5

1

1.5

2

2.5

time (ms)3

Fig. 20. MOSFET VDS and ID during active clamp
The circuit is used to test the BUK7S1R0-40H at VDS of 20 V, 22 V and 28 V. The limit is obtainedby derating the current at which destruction occurs by applying the same methodology used for
the SOA in data sheets. Fig. 21 shows the current capability against time in avalanche (IAL) and

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Power MOSFETs in linear mode
during active clamp at different clamping voltages. Table 2 summarises the results from the graphat a pulse of 1 ms. The current capability for a triangular pulse is shown to be around 2x the one
for a rectangular pulse. The current decreases as the voltage increases, as expected in case ofrectangular pulses.

103

aaa-034885

ID
(A)

(1)

2

10

(2)

10

(3)

(4)

1
10

-6

-4

-5

10

10

10

-3

10

time (s)-2(1) IAL; (2) VCL = 20 V; (3) VCL = 22 V; (4) VCL = 28 V
Fig. 21. Current versus time capability of avalanche and active clamp of BUK7S1R0-40H
Table 2. BUK7S1R0-40H: triangular and rectangular pulse capability
1 ms Active Clamp
1 ms SOA (data sheet)
Voltage (V)Current (A)Current (A)

20

35

16

22

31

14

28

15

8

The same principle applies to capacitive pre-charge, where the MOSFET dissipates a triangularpower pulse. However, in this case the ID is constant and VDS decreases. The reducing voltage
leads the working point to move towards the left of the SOA graph away from the Spirito region,
with lower risks of thermal instability with respect to active clamp.

7. Conclusion
In this application note an overview of power MOSFETs linear mode operation has been presented.
After a brief theoretical introduction highlighting the main differences with RDSon mode, the link
between linear mode and SOA have been described. This includes thermal instability (Spirito
region), Hot-SOA derating methods and pulse shape conversion.

8. Revision history
Table 3. Revision history
Revision
Date
numberDescription

2.0

2022-04-12

Text updated in Section 5.1.

1.0

2022-04-01

Initial version.

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modifications or additions. Nexperia does not give any representations or
warranties as to the accuracy or completeness of information included hereinand shall have no liability for the consequences of use of such information.

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or warranty that such applications will be suitable for the specified use
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List of Tables
Table 1. Scaling methods against measured data............. 10
Table 2. BUK7S1R0-40H: triangular and rectangularpulse capability...................................................................14
Table 3. Revision history....................................................14

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List of Figures
Fig. 1. Example of MOSFET output characteristic: ON/
OFF trajectories................................................................... 3
Fig. 2. Airbag application schematic and waveforms........... 3
Fig. 3. Active clamp schematic and waveforms................... 4
Fig. 4. Soft start schematic and waveforms......................... 4
Fig. 5. LDO schematic and waveforms................................ 5
Fig. 6. SOA: maximum current limits for 1 ms and at
VDS = 3 V and 1 ms pulse................................................. 5
Fig. 7. SOA graph; curve limits............................................6
Fig. 8. Transient thermal impedance from junction tomounting base as a function of pulse duration; typicalvalues................................................................................... 6
Fig. 9. Transfer characteristics showing regions ofpositive and negative temperature coefficient......................7
Fig. 10. Gate-source threshold voltage as a function ofjunction temperature............................................................ 7
Fig. 11. SOA graph: Spirito effect........................................ 8
Fig. 12. Cauer RC thermal model........................................ 8
Fig. 13. Current crowding contours for a) LFPAK88
and b) D2PAK packages......................................................9
Fig. 14. Example of SOA derating methods against
measurement for the BUK7Y2R0-40H...............................10
Fig. 15. Normalized total power dissipation as afunction of mounting base temperature: power scale
factor...................................................................................10
Fig. 16. Data sheet SOA: current limit for Tmb = 25˚C...... 11
Fig. 17. Derated SOA limits for Tmb = 100 ˚C andpulse of 1 ms, using current scaling method..................... 11
Fig. 18. Power shape conversion of triangular pulse
with MOSFET operating outside the Spirito region............ 12
Fig. 19. Active clamp circuit using the BUK7S1R0-40H.....13
Fig. 20. MOSFET VDS and ID during active clamp........... 13
Fig. 21. Current versus time capability of avalanche
and active clamp of BUK7S1R0-40H.................................14

AN50006

application note

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Rev. 2.0 — 12 April 2022

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AN50006

Nexperia

Power MOSFETs in linear mode

Contents
1. Introduction................................................................... 2
2. Linear mode definition................................................. 2
3. Example of typical linear mode applications............. 3
3.1. Airbag applications...................................................... 3
3.2. Active clamp................................................................ 4
3.3. Capacitor pre-charge (soft start / hot swap).................4
3.4. LDO (low dropout) regulators...................................... 5
4. SOA graph.....................................................................5
5. Temperature dependency............................................ 7
5.1. Thermal instability........................................................7
5.2. Hot-SOA derating........................................................ 9
6. SOA: pulse shape conversion...................................12
7. Conclusion.................................................................. 14
8. Revision history..........................................................14
9. Legal information........................................................15© Nexperia B.V. 2022. All rights reserved

For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 12 April 2022

AN50006

application note

All information provided in this document is subject to legal disclaimers.

Rev. 2.0 — 12 April 2022

© Nexperia B.V. 2022. All rights reserved

18 / 18