AN10441

Level shifting techniques in I²C-bus design
Rev. 2 — 10 February 2020

Application note

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ContentKeywords

I²C-bus, level shifting

Abstract

Logic level shifting may be required when interfacing legacy devices with newer devices that use asmaller geometry process. For bidirectional bus systems like the I²C-bus, such a level shifter mustalso be bidirectional, without the need of a direction control signal. The simplest way to solve thisproblem is by connecting a discrete MOSFET to each bus line.

AN10441

Nexperia

Level shifting techniques in I²C-bus design

1. Introduction
Present technology processes for integrated circuits with clearances of 0.5 µm and less limit themaximum supply voltage and consequently the logic levels for the digital I/O signals. To interface
these lower voltage circuits with existing 5 V devices, a level shifter is needed. For bidirectional
2bus systems like the I C-bus, such a level shifter must also be bidirectional, without the needof a direction control signal. The simplest way to solve this problem is by connecting a discrete
MOSFET to each bus line.

2

2. Bidirectional level shifter for Fast-mode and Standard-mode I C-bussystems
In spite of its surprising simplicity, such a solution not only fulfils the requirement of bidirectional
level shifting without a direction control signal, it also:•Isolates a powered-down bus section from the rest of the bus system•

Protects the ‘lower voltage’ side against high voltage spikes from the ‘higher-voltage’ side.

The bidirectional level shifter can be used for both Standard-mode (up to100 kbit/s) or in
2Fast-mode (up to 400 kbit/s) I C-bus systems. It is not intended for Hs-mode systems, which may
have a bridge with a level shifting possibility.

2.1. Connecting devices with different logic levels
Different voltage devices could be connected to the same bus by using pull-up resistors to thesupply voltage line. Although this is the simplest solution, the lower voltage devices must be 5 V
tolerant, which can make them more expensive to manufacture. By using a bidirectional level2shifter, however, it is possible to interconnect two sections of an I C-bus system, with each section
having a different supply voltage and different logic levels. Such a configuration is shown inFig. 1. The left ‘low-voltage’ section has pull-up resistors and devices connected to a 3.3 V supplyvoltage; the right ‘high-voltage’ section has pull-up resistors and devices connected to a 5 V supply
voltage. The devices of each section have I/Os with supply voltage related logic input levels and an
open-drain output configuration.
The level shifter for each bus line is identical and consists of one discrete N-channel enhancement
MOSFET; TR1 for the serial data line SDA and TR2 for the serial clock line SCL. The gates(g) have to be connected to the lowest supply voltage VDD1, the sources (s) to the bus lines ofthe ‘lower-voltage’ section, and the drains (d) to the bus lines of the ‘higher-voltage’ section.
Many MOSFETs have the substrate internally connected with its source, if this is not the case, anexternal connection should be made. Each MOSFET has an integral diode (n-p junction) between
the drain and substrate.
VDD2 = 5 V

VDD1 = 3.3 VRp
SDA1g

Rp

TR1sRpRp
SDA2dg TR2

SCL1s3.3 V DEVICE

SCL2d3.3 V DEVICE

5 V DEVICE

5 V DEVICE

mgk879Fig. 1.

AN10441

Application note

Bidirectional level shifter circuit connecting two different voltage sections in an2I C-bus system

All information provided in this document is subject to legal disclaimers.

Rev. 2 — 10 February 2020

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AN10441

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Level shifting techniques in I²C-bus design

2.1.1. Operation of the level shifter
The following three states should be considered during the operation of the level shifter:
1. No device is pulling down the bus line. The bus line of the ‘lower-voltage’ section is pulled up byits pull-up resistors Rp to 3.3 V. The gate and the source of the MOSFET are both at 3.3 V, soits VGS is below the threshold voltage and the MOSFET is not conducting. This allows the busline at the ‘higher-voltage’ section to be pulled up by its pull-up resistor Rp to 5 V. So the buslines of both sections are HIGH, but at a different voltage level.
2. A 3.3 V device pulls down the bus line to a LOW level. The source of the MOSFET alsobecomes LOW, while the gate stays at 3.3 V. VGS rises above the threshold and the MOSFET
starts to conduct. The bus line of the ‘higher-voltage’ section is then also pulled down to a LOWlevel by the 3.3 V device via the conducting MOSFET. So the bus lines of both sections go
LOW to the same voltage level.
3. A 5 V device pulls down the bus line to a LOW level. The drain-substrate diode of the MOSFET
the ‘lower-voltage’ section is pulled down until VGS passes the threshold and the MOSFET
starts to conduct. The bus line of the ‘lower-voltage’ section is then further pulled down to a
LOW level by the 5 V device via the conducting MOSFET. So the bus lines of both sections go
LOW to the same voltage level.
The three states show that the logic levels are transferred in both directions of the bus system,independent of the driving section. State 1 performs the level shift function. States 2 and 32perform a ‘wired-AND’ function between the bus lines of both sections as required by the I C-busspecification.
Supply voltages other than 3.3 V for VDD1 and 5 V for VDD2 can also be applied, e.g., 2 V for VDD1
and 10 V for VDD2 is feasible. In normal operation VDD2 must be equal to or higher than VDD1
(VDD2 is allowed to fall below VDD1 during switching power on/off).

3. Abbreviations
Table 1. Abbreviations
AcronymDescription
I C-bus

2Inter-Integrated Circuit bus

I/O

Input/Output

MOSFET

Metal-Oxide Semiconductor Field-Effect Transistor

4. Revision history
Table 2. Revision history
RevDateDescription

AN10441 v.2•20200210•AN10441 v.1

AN10441

Application note

20070618

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Initial version

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Level shifting techniques in I²C-bus design

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AN10441

Application note

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Rev. 2 — 10 February 2020

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AN10441

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Level shifting techniques in I²C-bus design

Contents
1. Introduction................................................................... 2
2. Bidirectional level shifter for Fast-mode and2Standard-mode I C-bus systems......................................2
2.1. Connecting devices with different logic levels..............2
2.1.1. Operation of the level shifter.................................... 3
3. Abbreviations................................................................ 3
4. Revision history............................................................35. Legal information......................................................... 4© Nexperia B.V. 2020. All rights reserved

For more information, please visit: http://www.nexperia.com
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Date of release: 10 February 2020

AN10441

Application note

All information provided in this document is subject to legal disclaimers.

Rev. 2 — 10 February 2020

© Nexperia B.V. 2020. All rights reserved

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