AN90011

Half-bridge MOSFET switching and its impact on EMC
Rev. 1.0 — 28 April 2020

application note

Document information
Information

Content

Keywords

half-bridge, EMC, MOSFET, snubber, voltage spikes, ringing, switching loss, reverse recovery

Abstract

Measuring and improving MOSFET switching behaviour to meet EMC requirements and optimize
reliability and efficency in half-bridge switching circuits.

AN90011

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Half-bridge MOSFET switching and its impact on EMC

1. Introduction
Modern switching converters for low voltages (< 100 V) predominantly use power MOSFETs as theswitching devices.
Switching converter applications includes inverters to synthesise AC waveforms, or for use
in DC-to-DC converters. The switching devices are often arranged in a simple half-bridge
configuration. At some point in time one of the MOSFETs will be actively switching (sometimes
called the control FET in DC-to-DC applications) and the other one will be switched off and acting
as a diode during the commutation event – this will be switched on once the switching event has
finished and acts as a synchronous rectifier, (in DC-to-DC converters this MOSFET is referred to asa syncFET).
The behaviour of the MOSFETs during the switching event strongly influences efficiency andelectromagnetic interference (emissions) goals.
In switch mode (PWM) designs, the switching behaviour of the MOSFET (or more generally theswitching power devices) can influence the efficiency and the emissions from the system. This will
apply to MOSFETs from any vendor, not just those from Nexperia.
This application note describes a technique to measure the switching efficacy and various
measures that can be taken to improve the switching behaviour, thus meeting efficiency, EMC
requirements and reliability goals.

2. Double pulse testingThis is a relatively simple method of determining the switching behaviour of a pair of MOSFETs ina half-bridge switching circuit. MOSFET Q1 is switched off and acts only as a diode, MOSFET Q2
is actively switched on and off twice: hence "double pulse testing". The behaviour at a particularcurrent level and DC voltage level can be analysed. This testing is useful for comparing MOSFETs
from different suppliers, since the detailed design – the technology - of the devices is unlikely to be
exactly the same. Fig. 1 shows the simplified schematic diagram of the double pulse test circuit.
+ve
power

Q1
Inductor

Gate
drive

Q2

RsenseCurrent
monitor-ve
power
aaa-031171

Fig. 1.

Simplified schematic diagram of the double pulse test circuit

Simplified switching behaviour is shown in Fig. 2

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Half-bridge MOSFET switching and its impact on EMC
60 V

V(sw_mode)
Switch node voltage

Turn off

Turn on

+ve
power

40 V
20 V
0V
0 µs
15 V

5 µs

10 µs

15 µs

20 µs

25 µs

30 µs

35 µs

40 µs

V(driver)
Driver signal

Gate
drive

10 V
5V
0V
0 µs
75 A

5 µs

10 µs

15 µs

20 µs

25 µs

30 µs

35 µs

40 µs

25 µs

30 µs

35 µs

40 µs

I(Rsense)

Current
monitor-ve
power

Low-side drain current

50 A
25 A
0A
0 µs

Fig. 2.

5 µs

10 µs

15 µs

20 µs

aaa-031198

Simplified switching behaviour
Three waveforms are shown in Fig. 2: the top one shows the switch node voltage, the middle
one shows the gate driver waveform to the low-side MOSFET and the lower waveform shows thecurrent in the low-side device. The regions of interest are at turn-off of the low-side switch andthen at turn-on for the second pulse. Assuming the gap between the first pulse and second pulse
is relatively short (but long enough to ensure proper switch off of the switched device before itis switched on again) then the current will be maintained at the target level since the diode will
present a voltage of around 1 V to the inductor, so di/dt will be low.
The MOSFET gate driver can be to the user’s choice however Nexperia uses a high current driver
so that the external gate drive resistor strongly determines the switching speed, rather than thisbeing influenced by the gate driver IC itself.

2.1. Measurement system
Current sensing is a critical consideration. A high bandwidth sensor is required. A coaxial shunt isused in Nexperia’s test circuit since the bandwidth can be more than 1 GHz however the additional
circuit inductance is in the region of 5 nH. Other methods of measuring current are possible suchas Rogowski coils, Hall Effect probes or current transformers but these also suffer from various
compromises either in bandwidth or significant additional circuit inductance. Some specialist
Rogowski based probes can reach ~80 MHz bandwidth. The goal is to have sufficient bandwidth in
the current sensor whilst minimising the additional circuit inductance. It may also be a requirement
to have isolation of the probe signal from the circuit (especially if double pulse testing is performedon high voltage systems).
Here are a few tips regarding the measurement system: the current rise time may be in the areaof up to 5 ns, so the current signal bandwidth would be 70 MHz, BW ≈ 0.35/trise, see ref (1).
A voltage rise time of 5 ns would also be of 70 MHz. The probe BW should be 3x to 5x signal
BW to take into account the 3 dB at the quoted BW. The oscilloscope should therefore have ananalogue bandwidth the same or higher than the probes when used with x10 voltage probes (1MΩ input impedance, note that the nominal oscilloscope bandwidth might quoted for a 50 Ω input
impedance). The probes should be correctly compensated before use. The sampling rate needs to
be at least 2.5x the analogue bandwidth for reasonable resolution. In this example the probes andoscilloscope would need to be 200 MHz analogue BW minimum and the sampling rate would need
to be 500 Msamples/s minimum.
Note also that it can take some time for signals to travel along probe cables so the voltage probes
and current probe cables should be the same length or the difference in time delay compensatedfor: a cable difference of 0.5 m could introduce a time difference of around 4 ns. This could have a

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Half-bridge MOSFET switching and its impact on EMC
significant effect on the measurement of switching energy. It is always worth spending a little time
to make sure that the measurement system is correctly set up for accuracy, see ref (1).
In double pulse testing, the waveforms of interest are low-side VDS (switch node voltage measured
as close to the MOSFET terminals as possible), high-side VDS (may be measured using a
differential probe method using high-side VD minus low-side VDS ), low-side VGS and low-side ID.
Ideally high-side VGS should also be measured.

2.2. MOSFET switching simulation
SPICE simulation is used to produce some example waveforms. The BUK7S1R0-40H is used
for most of this application note, except where otherwise stated. The simulation circuit is anapproximate model of the physical double pulse test circuit with parasitic elements added, seeFig. 3. Nexperia has found that there can be a good correlation between SPICE simulation andphysical measurements of the real circuit, as long as the device models are accurate (as is thecase for Nexperia MOSFET models) and the circuit is realistically modelled, see Appendix A.
Fig. 4 shows the MOSFET turn-off event and Fig. 5 shows the MOSFET turn-on event.
L20

HsD

1n
Rg1
(RG external)

L25

L10

L12

L14

L16

1n

1n

1n

1n

Lload

HsG

1n

L1
(ceresl)

M1
BUK7S1R0-40H

HsS

L21
1n

L22
1n
LsD
Rg2
(RG external)

L26

L11

LsG

1n

M2
BUK7S1R0-40H

Double pulse

1nL2(ceresl)
m=3

L3(ceresl)Vp

L4(ceresl)m=3

L5(elcoesl)

L6(elcoesl)m=3

L7(elcoesl)

L8(elcoesl)
m=3

C5

C6

C7

C8

C1

C2

C3

C4

(cerval)(cerval)m=3(cerval)(cerval)m=3

R1(ceresr)

R2(ceresr)

R3(ceresr)

R4(ceresr)

m=3R5(elcoesr)

V3(supply)m=3

R6(elcoesr)
m=3

L13

L15

L17

1n

1n

1n

R7
(elcoesr)

RsupplyR8(elcoesr)
m=3

Vn

L23
1n

RsenseL24
I

Fig. 3.

5n

aaa-031139

SPICE simulation circuit for double pulse test circuit

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Half-bridge MOSFET switching and its impact on EMC(V)

aaa-031185

60

I(Rsense)

50

90

40

30

30

0

V(HsD, HsS)

20

-30

V(LsG)

10-60

V(LsD)

0

-90
-120

-10
-20

(A)

60

13.2

13.4

13.6

13.8

14.0

14.2

14.4

14.6

t (µs)

14.8-150

I(Rsense) = low-side MOSFET drain current
V(HsD, HsS) = high-side MOSFET drain to source voltage
V(LsG) = low-side MOSFET gate to source voltage
V(LsD) = low-side MOSFET drain to source voltage
Fig. 4.
(V)

Turn-off waveform
aaa-031186

60
50

(A)

60

40

30

I(Rsense)30

0

V(LsD)

20

-30
-60

10

V(LsG)

0-90

V(HsD, HsS)

-10
-20

90

20.8

20.9

-120
21.0

21.1

21.2

21.3

21.4

21.5

t (µs)

21.6-150

I(Rsense) = low-side MOSFET drain current
V(LsD) = low-side MOSFET drain to source voltage
V(LsG) = low-side MOSFET gate to source voltage
V(HsD, HsS) = high-side MOSFET drain to source voltage
Fig. 5.

Turn-on waveform

2.3. MOSFET turn-off waveform description
These waveforms require some explanation as to why they look the way they do. Reference ismade to MOSFET capacitances, see Fig. 7. Consider first the turn-off waveform in Fig. 6. This isdivided into 6 time periods t0 to t5.

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Half-bridge MOSFET switching and its impact on EMC(V)

aaa-031188

60

I(Rsense)

50

90

40

30

30

0

V(HsD, HsS)

20

-60

V(LsD)

0
-10
-20

-30

V(LsG)

10

-90

t0
13.2

(A)

60

13.4

t1

t2

t3

13.6

13.8

t4

-120

t5

14.0

14.2

14.4

14.6

t (µs)

14.8-150

I(Rsense) = low-side MOSFET drain current
V(HsD, HsS) = high-side MOSFET drain to source voltage
V(LsG) = low-side MOSFET gate to source voltage
V(LsD) = low-side MOSFET drain to source voltage
Fig. 6.

MOSFET turn-off waveforms, showing reference time periods
During period t0, the low-side device is on and the high-side device is off. This is a steady state
condition. During time period t1, the device turn-off process begins as the gate driver removes
charge from the gate capacitance (CISS = CGS + CGD, see Fig. 7) of the device and the gatesource voltage starts to fall. VDS rises very slightly as the RDSon of the device begins to increase,in accordance with the “drain-source on-state resistance as a function of gate-source voltage”
characteristic found in Nexperia MOSFET data sheets.

CGD
NMOS

CDS

CGS

aaa-022333
Fig. 7.

MOSFET internal capacitances

During t2, once VGS falls to the minimum value required to sustain the output inductor current (asdetermined by the output characteristic, see Fig. 8), VGS is approximately constant (this is the"Miller Plateau" and the VGS value = Vp). During this time the gate driver current discharges CGD(causing VGS to fall and VDG to rise), until the switch node voltage has risen to a voltage that allows
the diode to conduct current. At this point VGS can fall to its threshold voltage (during t3) as current
is commuted from the low-side MOSFET to the high-side MOSFET body diode.

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Half-bridge MOSFET switching and its impact on EMC

400
IDD
10 V
(A)
(A)

aaa-030487

7V

6V

320

V
VGS= 5.5 V

Ohmic region
240

saturation region
5V

160

80

4.5
4.5VV
4V

0

Fig. 8.

01

2

3
VDS (V)

4

Example of MOSFET output characteristic

Towards the end of t2 and moving into t3, the low-side MOSFET VDS reaches the level of the DC
supply voltage and continues to increase. At this point the body diode of the high-side device canstart to turn on and the ID of the low-side MOSFET can commutate to the high-side device.
The rate at which this happens is now controlled by the gate driver discharging Ciss as in period
t1 and the incremental slope of the MOSFET transfer curve (transconductance) of the MOSFET(the transfer curve can be found in Nexperia Power MOSFET data sheets). The resulting rateof change of drain current dID/dt causes a voltage to be produced across all circuit inductances
affected by the change in ID. Referring to Fig. 3, the inductances affected by dID/dt include L10,
L11, L20, L21, L22, L23 and L24, as well as any component package inductances (for example L1,
L2 and others not shown in Fig. 3). This is known as the loop inductance. This results in the large
voltage overshoot seen on the low-side MOSFET VDS, the overshoot is 14.5 V. The peak value
corresponds to the peak dID/dt. The equal change of current in the high-side MOSFET source IS
results in a small negative voltage spike across the high-side device due to L20 and L21: note thatthe measuring point for the voltages includes some circuit impedance contribution in this example
and that the MOSFET model includes package parasitics.
This also adds to the voltage spike observed on the low-side MOSFET. The total circuit inductancefrom the capacitors through both MOSFETs is often referred to as the loop inductance. The sumof the layout (PCB) inductances is 10 nH in Fig. 3 however another 1 nH comes from the device
internal inductances, then there are additional inductances coming from the DC link capacitors
and layout which are not so simple to describe. The peak dID/dt is 1.1 A/ns in Fig. 4 so 12.1 V isdue to the inductances and the voltage overshoot is 13.0 V. Note that the high-side body diode isconducting, so this accounts for about 0.7 V of the difference.
At the end of t3 and start of t4, ID in the low-side MOSFET reaches zero. All the current has
transferred to the high-side MOSFET body diode. At this point, the voltage across the low-side
MOSFET is still more than 30 V given a supply voltage of 20 V. Oscillation is inevitable and asimple circuit model as shown in Fig. 9 illustrates the situation.

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Half-bridge MOSFET switching and its impact on EMC
Open switch
after short time(NC)

Rdamping(NC)

Initialvoltage= 12 V

COSS

Lparasitic

aaa-031172

Fig. 9.

Oscillation at MOSFET turn-off

COSS is the low-side MOSFET effective capacitance (CDS in parallel with CGD, CGS is shorted out
by the gate driver). This is VDS dependant and the value at 32 V is used in this example). Lparasitic
is the loop inductance. If COSS is averaged to 1.6 nF and Lparasitic is 11 nH then the oscillation
frequency will be 37.9 MHz. This is quite close to the observed oscillation frequency around
35 MHz. The damping resistance which is due to the device construction and resistance due tothe layout will reduce the frequency and non-linearity of COSS results in a slightly bigger effective
capacitance being present.
In period t5, the MOSFET turn-off switching transition is complete. The low frequency oscillationis due to resonance of the ceramic capacitors with the ESL of the electrolytic capacitors andlayout inductance. The resonant frequency is approximately 2 MHz in this example. The ceramic
capacitors are 100 nH and the ESL of the electrolytic capacitor is 20 nH in the simulated example,
on its own the resonant frequency is calculated at of 3.6 MHz. Factoring in the layout inductancewould account for the discrepancy. See Section 3.2.1 for more details about low frequency ringing.
The switching loss in the low-side MOSFET at turn-off, (over the t2 and t3 time periods), is given by:∫

V(LsD) ∗ I(Rsense)dt(1)

Where V(LsD) = low-side MOSFET drain to source voltage.
The switching loss in the high-side MOSFET is negligible.

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2.4. MOSFET turn-on waveform description
A typical turn-on waveform is shown in Fig. 10. In time period t0 the low-side MOSFET is off.
Current is flowing in the body diode of the high-side MOSFET. During t1 the gate voltage on the
low-side MOSFET starts to rise. Nothing happens until the threshold voltage is reached.

(V)

aaa-031189

60
50

(A)

60

40

30

I(Rsense)30

0

V(LsD)

20

-30
-60

10

V(LsG)

0-90

V(HsD, HsS)

-10
-20

90

t1

t0
20.8

20.9

21.0

t2
21.1

-120

t5
t3

t4

21.3

21.4

21.5

t (µs)

21.6-150

I(Rsense) = low-side MOSFET drain current
V(LsD) = low-side MOSFET drain to source voltage
V(LsG) = low-side MOSFET gate to source voltage
V(HsD, HsS) = high-side MOSFET drain to source voltage
Fig. 10. MOSFET turn-on waveforms, showing reference time periods
At the start of time period t2, the gate voltage continues to rise until significant current starts to flow.
The rate of change of drain current dID/dt increases and then becomes more constant, as definedby the transfer characteristic (see Nexperia MOSFET data sheet) dID/dt is also dependant on gate
driver current in Ciss. The circuit inductances start to interact with the MOSFET. Notice how the
MOSFET VDS falls and then plateaus at around 5 V in this example. This corresponds with thehighest dID /dt observed, interacting with the loop inductance (see Section 2.3). dID/dt is therefore
limited by the supply voltage and the loop inductance, rather than the MOSFET capability.
Another limitation to dID/dt is due to the device source and layout inductance to the connection of
the gate drive (represented by L23 in Fig. 3). Packages with a source clip such as LFPAK will havea higher did /dt capability compared to wire bonded packages such as DPAK due to the package
source inductance. Notice also the high-side VDS shows a “hump” due to dID/dt interacting with
L20 and L21 (see Fig. 3). VGS as observed at the pins of the low-side device is also affected due toinductance of the source leg, the actual VGS applied to the MOSFET die will be fairly constant due
to the MOSFET gate capacitance CGS, however the voltage across the package source inductanceis added. This can just be observed in Fig. 10. At the end of period t2 the low-side drain current
reaches the load inductance current. The low-side VDS doesn’t fall at this point. This is because
the high-side body diode must be turned off first. Note that the low-side MOSFET is experiencing
a relatively high current and also a relatively high VDS, hence there will be some switching loss
associated with this condition.
At the start of time period t3, the current in the low-side MOSFET increases beyond the load
current. The high-side MOSFET body diode is being switched off, a negative current is flowing in it
and the depletion layer inside the body diode is forming in order to support reverse voltage, charge
is being stored in the diode junction. This can be considered as a capacitance (sometimes referred
to as the diffusion capacitance Cd, the associated charge may be referred to as Qs). The low-side
drain current approaches its peak value.
Once the depletion layer begins to form, the high-side VDS will begin to increase. This happensat the start of period t4. The low-side VDS will fall. The low-side drain current will still increase alittle further before reaching a peak, partly due to charging the diffusion capacitance Cd but also
due to charging the junction capacitance Cj in the high-side body diode. The pn junction can beconsidered as a parallel plate capacitor, with the distance between the “plates” containing theAN90011application note

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Half-bridge MOSFET switching and its impact on EMC
depletion region as the dielectric material. There comes a point where the current flowing into thedepletion region becomes relatively small and the current flowing into the junction capacitancedominates. This is just before the peak current is observed in the low-side MOSFET. The junction
capacitance characteristic (especially with respect to VDS) now determines the rate of change ofcurrent observed in the body diode and low-side MOSFET. It also determines the rate of rise of
the high-side VDS. This is unlike the situation seen during turn-off, where the gate driver and CGD
control the dVDS/dt, now this is controlled by the energy stored in the loop inductance and COSS .
The charge stored in COSS (CJ = CDS, COSS ≈ CDS + CGD) is referred to as QOSS . The process ofswitching off the high-side MOSFET body diode during time periods t3 and t4 is known as reverse
recovery and is described in ref (5) and other references.
The high-side VDS will usually exceed the nominal DC supply level due to the dI/dt and loop
inductance. This is referred to as a VDS “spike” and can be problematic. Notice also that theobserved low-side VGS waveform shows some oscillations. VDS oscillations are coupled into the
MOSFET gate directly as a result of the capacitive divider formed by CGD and CGS (see Fig. 7).
Secondly, the observed waveform is affected by source lead and layout inductance, represented by
L23.
In period t5, a high-frequency decaying oscillation is observed superimposed on a lower frequency
DC link oscillation. The high-frequency oscillation is due to the resonance of the high-side COSSand the loop inductance Lparasitic. The low frequency oscillation is due to the resonance of the DC
link ceramic capacitors and inductance of the electrolytic capacitors and circuit layout as discussed
in the MOSFET turn-off condition, (see Section 3.2.1). The oscillations decay over time.
The switching loss in the low-side MOSFET at turn on, (over the t2, t3 and t4 time periods.), is givenby:∫

V(LsD) ∗ I(Rsense)dt(1)

The switching loss in the high-side MOSFET, (over the t4 time period), is given by:∫

V(HsD, HsS) ∗ (I(Rsense)-I(Lload))dt(2)

3. Methods to improve switching performance
In Section 2, the switch on and switch off transients were explored using double pulse testing.
In the waveforms presented, some undesirable effects can be seen such as the large voltage
spike on the high-side VDS when the low-side MOSFET switches on, also some oscillations atturn-on and turn-off. This is a cause of unwanted noise which may propagate to the outside world
and may interfere with the operation of radio systems but may also cause disturbances in otheranalogue and digital systems (hence the use of the terms such as electromagnetic compatibility orelectromagnetic interference: EMC / EMI).

3.1. Voltage spikes
VDS spikes are observed in both the switch off and switch on waveforms. At low-side turn on, it ispossible that the high-side VDS might experience a spike which may reach or exceed the rating of
the MOSFET. It is good practice to limit this spike to < 80% of the MOSFET rating to achieve good
reliability and also to keep the amplitude of the following oscillations quite small.
The following sections consider some methods to minimise these voltage spikes.

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Half-bridge MOSFET switching and its impact on EMC

3.1.1. Circuit layout
The loop inductance was described in Section 2.3 and Section 2.4. This total inductance should be
minimised as far as possible by using compact layout methods, so that the loop area is reduced:
if the loop is considered as a turn of a coil then a large coil diameter will result in a larger self
inductance. Furthermore, the magnetic field generated by the loop can interfere with nearby wiring
according to Faraday’s law.
+ve supply

ground plane(on another PCB layer)

2.07 nH
ground plane(on another PCB layer)+ve supply

4 mm

switch node
2.52 nH
1.55 nH

3.5 nH

4.04 nH

switch node

4.75 nH

2.07 nH

VDC

D1

3.5 nH

C

I/P

1.55 nH

VDC

4.04 nH

C

I/P

4.75 nH

D1

S2

2.52 nHS2

aaa-031121

PCB design 1: loop inductance = 10.3 nH

aaa-031122

PCB design 2: loop inductance = 8.2 nH

Fig. 11. Half-bridge layout possibilities showing inductances
A layout arrangement as shown in Fig. 11 helps to reduce the loop inductance. Design 1 has aloop inductance of 10.3 nH compared to design 2 with a loop inductance of 8.1 nH, according tosimulation (ignoring device inductances). Using smaller devices can help to reduce the loop area
further.
It was seen in Section 2 that switching behaviour depends on the gate driver voltage andimpedance, the package layout source inductance in the gate driver loop and the loop inductance.

3.1.2. Reducing di/dt
In the case of the low-side MOSFET switch off waveform (Fig. 4, Fig. 6), the voltage spike depends
on the loop inductance and the di/dt. Since the current is falling, the parasitic inductance will add

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Half-bridge MOSFET switching and its impact on EMC
to the supply voltage as seen at the drain terminal of the MOSFET. The ringing was due to thestep voltage change when the drain current (and di/dt) reaches zero. This can be achieved byslowing the gate drive by some method such as slew rate control at the driver IC, increasing gate
resistance or adding capacitance between gate and source. This will increase the switching time
and therefore the switch off loss.

ID
(A)

trr
dI/dt

ta

tb

0
0.25 IRM
dIR/dt
IRM

tb
S= t
a

t (s)

trr = ta + tb
Fig. 12. Reverse recovery waveform definitions
In the case of the low-side MOSFET switch on, it was seen in Fig. 10 that there is a significant
VDS spike across the high-side MOSFET which is acting as a diode. The spike is due to the loop
inductance and dIR/dt (see Fig. 12) which cannot be directly controlled but which is a function of
the dI/dt that is controllable. The time ta is approximately constant and it depends on the time ittakes for the depletion region to form in the pn junction of the body diode (i.e. recombination time).
A higher dI/dt will therefore result in a higher IRM value and higher energy in the loop inductance.
dI/dt and dIR/dt are related by the softness factor of the body diode (tb/ta), which is reasonably
constant over a range of dI/dt values. dIR/dt multiplied by the loop inductance causes a voltage
overshoot. This can be absorbed by the MOSFET output capacitance COSS. This capacitanceis non-linear with respect to VDS, (see Fig. 13), which doesn’t help with keeping VDS spikes
under control. COSS defines the shape of the tb region (and consequently the dIR/dt) and is acharacteristic of the MOSFET technology.
aaa-031120

20,000
COSS(pF)
16,00012,000

8,000

4,000

0

0

5

10

15

20

25

30
35
VDS (V)

Fig. 13. COSS as a function of VDS
Adding additional capacitance external to the MOSFET can help to “linearise” the capacitance andreduce the VDS spike. This is the capacitance part of an RC snubber.

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Half-bridge MOSFET switching and its impact on EMC

3.2. Ringing
This occurs because a stimulus is applied to a resonant circuit. In the half-bridge, inductances
are usually attributed to the circuit layout and parasitics within the components, usually the loop
inductance. Capacitances are attributed to the MOSFETs (e.g. COSS) and bypass capacitors

3.2.1. Bypass capacitors
Bypass capacitors should be placed as close to the half-bridge as possible (to minimise the loop
area as discussed in 3.2.1), ideally using surface mount devices. The value should be chosen suchthat resonance will be well damped. A 100 nF 100 V C0G capacitor has an ESL of approximately
1.1 nH and an ESR of 20 mΩ. A 1 μF 100 V X7R capacitor has similar ESL and ESR. This meansthat the 1 μF capacitor has a better damping capability compared to the 100 nF capacitor, since thecharacteristic impedance will be closer in value to the capacitor's ESR. The C0G is a more stabledielectric however a higher capacitance is more beneficial. It was shown that the 2 MHz oscillationis due to the capacitance of the ceramic bypass capacitors and the inductance of the layout andelectrolytic capacitors. This is also borne out in practice.
In the example simulation circuit, 100 nF capacitors are compared with 1 μF capacitors, seeFig. 14.
aaa-031191

45
VDS
40
(V)

VDS
40
(V)

35

35

30

30

25

25

20

20

15

15

10

10

5

5

0

0

-5
20.5

21.5

22.5

t (µs)

23.5

Cbypass = 100 nF

aaa-031192

45

-5
20.5

21.5

22.5

t (µs)

23.5

Cbypass = 1 μF

Fig. 14. Effect of bypass capacitor selection: 100 nF vs. 1 μF
The 2 MHz oscillation is shifted to a lower frequency and is a lower amplitude, the ESR and PCB
track resistance is providing damping. However the higher frequency oscillation of around 35 MHz
remains and is changed only slightly.

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3.2.2. Adding a snubber
By adding an RC snubber across the MOSFET drain and source, oscillations can be minimised.
AN11160 (ref 3) covers this topic. Another good reference is (ref 4) which proposes a method
to optimise the snubber capacitor. The snubber will attenuate the unwanted high frequency
oscillations as shown in Fig. 15. A 10 nF + 2.2 Ω snubber is applied to the high-side and lowside devices. VDS for the high-side device is shown at low-side turn-on (i.e. high-side body diodeturn-off). This also damps the oscillations at low-side turn-off. SPICE programs allow a sweep ofparameters to give an indication of the snubber values which are likely to give the desired outcome.
aaa-031194

45

aaa-031193

35
VDS(V) 30

VDS
40
(V)
35

25

30

20

25
20

15

15

10

10

5

5

0

0
-5
20.8

21

21.2

21.4

t (µs)

-5
20.8

21.6

without snubber

21

21.2

21.4

t (µs)

21.6

with snubber

Fig. 15. Effect of adding a snubber

3.3. Feedback into the gate signal
There is a risk of feedback into the gate signal due to high dVDS/dt. If this exceeds the gate
threshold voltage (VGS(th)) then a significant shoot through current can flow in the half-bridge. Thisis due to the MOSFET capacitances CGD , CDS and the external gate drive resistance forming
a potential divider. If a shoot through current occurs, this will significantly increase the switchinglosses. This is illustrated in Fig. 16, see ref (7).
i=C

dV
dt

18

MOSFET

VGS

RG

CGS

CDS
VGS

Voltage (V)

16
CGD

L

14
12
10
8

HS VGS (V)6

LS VGS (V)4

MOSFET

Switch Node (V)20Some of this charge is sunk by the driver but some will
charge CGS and VGS will increase. Both MOSFETs canpotentially be on at the same time causing a shortcircuit and current to shoot through the MOSFETs

VGS “bounces
back upduring the dV/dt

dV/dt across the highside FET causes acapacitive current tocharge CGD

0

2

4

6

Time (µs)

8aaa-026552

Fig. 16. Dynamic behaviour of a MOSFET half-bridge
Additional external capacitance is used to control dV/dt. Crss is relatively small and non-linear
giving rise to gate glitches and sudden shoot through current. The external capacitance would bemuch larger in value and quite linear, producing a controlled dV/dt. See section 3.4.2.

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Half-bridge MOSFET switching and its impact on EMC

3.4. Switching speed control
3.4.1. Effect of varying RG
Varying the external gate resistance will affect switching losses in the low-side MOSFET;
see Fig. 17, Fig. 18 and Fig. 19. In this case, measurements have been made using theBUK7S1R5-40H.
aaa-031195

160
E
(mJ)
120

turn-off energy

80
turn-on energy
40

0

0

20

40

60

80

100

RG

120

Fig. 17. Effect of varying RG on switching loss (example values only)
aaa-031196

6
di/dt(A/ns)

dIr/dt4

2

turn-on di/dt

turn-off di/dt
0

0

20

40

60

80

100

RG

120

Fig. 18. Effect of varying RG on turn-on di/dt, dIr/dt and turn-off di/dt (example values only)

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Half-bridge MOSFET switching and its impact on EMC
aaa-031197

12
dV/dt
(V/ns)
turn-on dV/dt
8

4

turn-off dV/dt
0

0

20

40

60

80

100

120

RG

Fig. 19. Effect of varying RG on turn-on dV/dt and turn-off dV/dt (example values only)
Increasing RG will increase switching loss but the benefit is better controlled switching andimprovements in spiking and ringing. There may also be an increased risk of gate bounce so it may
be necessary to add a small capacitor between gate and source.
For best performance, RG for turn-on should be large than RG for turn-off. di/dt is controlled by the
VGS value around the Miller plateau voltage Vp:
IG = (VGS - Vp) / RG for example:
IG(on) = (10 - 4.3) / 10 = 0.57 A
IG(off) = (0 - 4.3) / 10 = -0.43 A
Hence turn on di/dt may be different to turn off di/dt depending on the value of RG. di/dt can also
be controlled by carefully selecting the location of the gate drive ground connection point, this isequivalent to adjusting L23 in Fig. 3.

3.4.2. Effect of adding external gate to source capacitanceIn case of gate bounce risk, (see Section 3.3), an external CGS can be added to reduce the highfrequency impedance of the gate driver whilst still having relatively high RG The effect on switching
speed (di/dt) is relatively modest, as seen below in Fig. 20. This is for a BUK7S1R0-40H with an
RG external value of 22 Ω.
aaa-031498

1000
di/dt
turn-on

900

800
turn-off
700

600

500

0

2

4

6

8

CGS (nF)

10

Fig. 20. CGS effect on MOSFET di/dt

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3.4.3. Effect of adding gate to drain capacitance
Adding some drain voltage feedback via a gate – drain capacitor would reduce dV/dt without
affecting di/dt and will reduce the voltage spike at turn-off. Losses are increased. Reducing dV/dt
is beneficial because in a motor drive, the switch node voltage is presented directly to the motor
windings. The motor windings can act as antennae so that the frequency domain content of the
waveform can radiate into the environment. The highest frequency component of the waveform will
be approximately 0.35/rise time or 0.35/fall time.
aaa-031499

160
dV/dt
120

80

40

0

0

1

2

3

4

CGD (nF)

5

Fig. 21. External CGD effect on controlling MOSFET turn-off
Fig. 21 shows the effect of adding a capacitor to a BUK7S1R0-40H with a series resistor of 10 Ω.
Usually a series resistor RGD is added to CGD in order to prevent oscillations, see Fig. 22. The
value of CGD can be in the range of 1 – 5 nF for a device such as BUK7S1R0-40H, much bigger
than the value of the MOSFET internal Crss. The value of RGD can be in the range of 10 – 50 Ω forthis device, higher values start to diminish the effect of having the external CGD. Note that Fig. 22
applies to the low-side controlling switch in the case of the double pulse test circuit.
In the case of the MOSFET acting as a synchronous rectifier then the effect of adding external CGD
will reduce dv/dt however the value of dV/dt can be much higher. See Fig. 23.

RGD
CGD

aaa-031501

Fig. 22. Adding CGD and RGD

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Half-bridge MOSFET switching and its impact on EMC
aaa-031502

6000
dV/dt

4000

2000

0

0

1

2

3

4

QGD (nF)

5

Fig. 23. External CGD effect on the synchronous rectifier MOSFET
It is recommended that some SPICE simulation is performed first before experimenting todetermine the optimum values of external resistors and capacitors.

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4. Impact on EMC and efficiency
The significant voltage transients and oscillations which have been described in Section 2 are thesource of electromagnetic interference. This must be suppressed in order to meet CISPR25 based
requirements for automotive and CISPR 11 and the like for industrial, telecoms and consumer
equipment. These kinds of standards consider conducted and radiated emissions. How do thesetransient voltages and currents cause interference? In the next paragraphs, emissions from digital
circuits will be ignored however the same basic principles apply, the difference being that thevoltages are much lower than in the power circuit and the frequency rise and fall times are much
faster.
In an ideal PWM controlled half-bridge MOSFET circuit, it is still necessary to take care of EMI byusing screening and filters. This is because simple analysis of the half-bridge waveforms feature
rectangular blocks of current with fast rising and falling edges from the DC link and the output
switch node will feature fast rising and falling voltages. See Fig. 24
i

t

v
t
Vehiclebattery

3 or more
phasesDifferential
mode filter

aaa-031173

Fig. 24. Sources of electromagnetic noise in a half-bridge circuit
The purpose of the filter is to remove the high frequency content of current waveform so that thebattery delivers a clean current to the half-bridge circuit, otherwise significant amounts of highfrequency current in the supply cables can radiate and can introduce high frequency voltage
disturbances which could get into other equipment connected to the battery. The same principles
apply to AC supplied systems. Clearly any additional sources of noise in the circuit such as fromreverse recovery induced oscillations can get back into the supply: these should be suppressedat the source using the techniques described in Section 3, as well as making sure that the filter
has sufficient attenuation to meet the levels required in the relevant EMC standards. Note that theparasitic elements of filter components can render them potentially useless. Capacitors always
have series inductance and inductors have parallel capacitance, so they will only be effective overa limited frequency range.
The motor cables and motor windings can also act as radiating elements: the high frequency
content of the phase voltage is transmitted by the cables and motor windings. If the cables andload are of significant length, then they must be shielded. The shielding must form a Faraday cage,and slots or joints must be designed considering the effects that they have on the electromagnetic
environment. In this simplistic view, the effect of parasitic capacitance to earth has been ignored,
when subjected to dV/dt from half bridge circuits such as this, then parasitic currents can flow inboth the supply cables: these are common mode currents, the earth path is the invisible “current
return path”.

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Half-bridge MOSFET switching and its impact on EMC

5. Conclusions
This application note is intended to give the reader a reasonably detailed understanding of how
the half-bridge switching circuit is a source of electromagnetic noise and power loss. In particular,
the reverse recovery characteristic of the MOSFET body diode can be a key factor to achieving
good EMC behaviour and lower losses. Some techniques to reduce switching noise at source havebeen considered and a brief overview of how the noise propagates to the outside world have been
considered.

6. References
1.
2.
3.
4.
5.

High Speed Digital Design – a Handbook of Black Magic, Howard Johnson & Martin Graham
Power MOSFET frequently asked questions TN00008, section 7.8, Nexperia Semiconductors
Designing RC snubbers” AN11160, Nexperia Semiconductors
Optimising snubber design through frequency-domain analysis”, EDN
Semiconductor device modelling with SPICE 2nd Edition, Giuseppe Massobrio & Paulo
Antognetti
6. EMC for product designers, Tim Williams
7. Designing in MOSFETs for safe and reliable gate-drive operation AN90001, Nexperia
Semiconductors

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Half-bridge MOSFET switching and its impact on EMC

7. Appendix A: Comparison between SPICE simulation and practicalmeasurements for the BUK7S1R0-40H in a double pulse test circuit
The SPICE circuit used is as shown in Fig. 3. The following values were used in the simulation:
ceresr = 20m, ceresl = 1.13n, cerval = 100n, cerval1 = 100n, elcoesr = 40m, elcoesl = 20n.
Both turn-on and turn-off conditions are considered.
SPICE model is modified from standard: TT parameter is approximately half of published value (togive better reverse recovery alignment with double pulse measurements).
The following test conditions were applied: RG = 30 Ω, IL = 60 A, VDC = 20 V.

(V)

aaa-031186

60
50

(A)

60

40

30

I(Rsense)30

0

V(LsD)

20

-30
-60

10

V(LsG)

0-90

V(HsD, HsS)

-10
-20

90

20.8

20.9

-120
21.0

21.1

21.2

21.3

21.4

21.5

t (µs)

21.6-150

I(Rsense) = low-side MOSFET drain current
V(LsD) = low-side MOSFET drain to source voltage
V(LsG) = low-side MOSFET gate to source voltage
V(HsD, HsS) = high-side MOSFET drain to source voltage
Fig. 25. SPICE turn-on waveform(V)

aaa-031238

60
50

90

(A)

60

40

30

I(Rsense)30

0

V(LsD)

20

-30
-60

10

V(LsG)

0-90

V(HsD, HsS)

-10

-120
-150

-20
14.0

14.1

14.2

14.3

14.4

14.5

14.6

14.7

t (µs)

14.8

I(Rsense) = low-side MOSFET drain current
V(HsD, HsS) = high-side MOSFET drain to source voltage
V(LsG) = low-side MOSFET gate to source voltage
V(LsD) = low-side MOSFET drain to source voltage
Fig. 26. Measurement turn-on waveform

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AN90011

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Half-bridge MOSFET switching and its impact on EMC(V)

aaa-031185

60

I(Rsense)

50

90

40

30

30

0

V(HsD, HsS)

20

-30

V(LsG)

10-60

V(LsD)

0

-90
-120

-10
-20

(A)

60

13.2

13.4

13.6

13.8

14.0

14.2

14.4

14.6

t (µs)

14.8-150

I(Rsense) = low-side MOSFET drain current
V(LsD) = low-side MOSFET drain to source voltage
V(LsG) = low-side MOSFET gate to source voltage
V(HsD, HsS) = high-side MOSFET drain to source voltage
Fig. 27. SPICE turn-off waveform
(V)

60
50

aaa-031239

I(Rsense)

90

40

30

30

0

20
10
0

(A)

60

V(HsD, HsS)

-30

V(LsG)-60

V(LsD)

-90
-120

-10

-150

-20
11.0

11.2

11.4

11.6

11.8

12.0

12.2

12.4

t (µs)

12.6

I(Rsense) = low-side MOSFET drain current
V(HsD, HsS) = high-side MOSFET drain to source voltage
V(LsG) = low-side MOSFET gate to source voltage
V(LsD) = low-side MOSFET drain to source voltage
Fig. 28. Measurement turn-off waveform
Table 1. Measurement and SPICE simulation values
Turn-onTurn-on(measured)(SPICE)

AN90011application noteTurn-off(measured)Turn-off(SPICE)

di/dt

1.12 A/ns

1.12 A/ns

di/dt

0.82 A/ns

1.05 A/ns

dIr/dt2.96 A/ns

2.78 A/ns

dV/dt

0.31 V/ns

0.45 V/ns

ΔIRM

10.09 A

12.2 A

V(LsD)

29 V

34.2 Vta

11.43 ns12.8 ns

-

-

-

tb

5.17 ns

7.2 ns

-

-

-

dV/dt

4.54 V/ns

5.7 V/ns---

V(HsD, HsS)

27 V

41.2 V---All information provided in this document is subject to legal disclaimers.

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Half-bridge MOSFET switching and its impact on EMC

8. Revision history
Table 2. Revision history
Revision
Date
numberDescription

1.0

Initial version.

2020-04-28

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9. Legal information
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modifications or additions. Nexperia does not give any representations or
warranties as to the accuracy or completeness of information included hereinand shall have no liability for the consequences of use of such information.

Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, Nexperia does not give any
representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for theconsequences of use of such information. Nexperia takes no responsibility
for the content in this document if provided by an information source outsideof Nexperia.
In no event shall Nexperia be liable for any indirect, incidental, punitive,
special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removalor replacement of any products or rework charges) whether or not suchdamages are based on tort (including negligence), warranty, breach ofcontract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, Nexperia’s aggregate and cumulative liability towards customer
for the products described herein shall be limited in accordance with theTerms and conditions of commercial sale of Nexperia.
Right to make changes — Nexperia reserves the right to make changes
to information published in this document, including without limitation
specifications and product descriptions, at any time and without notice. This
document supersedes and replaces all information supplied prior to the
publication hereof.
Suitability for use — Nexperia products are not designed, authorized or
warranted to be suitable for use in life support, life-critical or safety-criticalsystems or equipment, nor in applications where failure or malfunctionof an Nexperia product can reasonably be expected to result in personal
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suppliers accept no liability for inclusion and/or use of Nexperia products insuch equipment or applications and therefore such inclusion and/or use is at
the customer’s own risk.
Applications — Applications that are described herein for any of theseproducts are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using Nexperia products, and Nexperia accepts no liability forany assistance with applications or customer product design. It is customer’ssole responsibility to determine whether the Nexperia product is suitableand fit for the customer’s applications and products planned, as well as
for the planned application and use of customer’s third party customer(s).
Customers should provide appropriate design and operating safeguards tominimize the risks associated with their applications and products.
Nexperia does not accept any liability related to any default, damage, costs
or problem which is based on any weakness or default in the customer’s
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Trademarks
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Half-bridge MOSFET switching and its impact on EMC

List of Tables
Table 1. Measurement and SPICE simulation values........ 22
Table 2. Revision history....................................................23

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Half-bridge MOSFET switching and its impact on EMC

List of Figures
Fig. 1. Simplified schematic diagram of the double
pulse test circuit................................................................... 2
Fig. 2. Simplified switching behaviour..................................3
Fig. 3. SPICE simulation circuit for double pulse test circuit 4
Fig. 4. Turn-off waveform..................................................... 5
Fig. 5. Turn-on waveform..................................................... 5
Fig. 6. MOSFET turn-off waveforms, showing
reference time periods......................................................... 6
Fig. 7. MOSFET internal capacitances................................ 6
Fig. 8. Example of MOSFET output characteristic............... 7
Fig. 9. Oscillation at MOSFET turn-off................................. 8
Fig. 10. MOSFET turn-on waveforms, showing
reference time periods......................................................... 9
Fig. 11. Half-bridge layout possibilities showing
inductances........................................................................ 11
Fig. 12. Reverse recovery waveform definitions................ 12
Fig. 13. COSS as a function of VDS..................................12
Fig. 14. Effect of bypass capacitor selection: 100 nF
vs. 1 μF.............................................................................. 13
Fig. 15. Effect of adding a snubber....................................14
Fig. 16. Dynamic behaviour of a MOSFET half-bridge.......14
Fig. 17. Effect of varying RG on switching loss
(example values only)........................................................ 15
Fig. 18. Effect of varying RG on turn-on di/dt, dIr/dt
and turn-off di/dt (example values only).............................15
Fig. 19. Effect of varying RG on turn-on dV/dt andturn-off dV/dt (example values only).................................. 16
Fig. 20. CGS effect on MOSFET di/dt............................... 16
Fig. 21. External CGD effect on controlling MOSFET
turn-off................................................................................ 17
Fig. 22. Adding CGD and RGD......................................... 17
Fig. 23. External CGD effect on the synchronousrectifier MOSFET............................................................... 18
Fig. 24. Sources of electromagnetic noise in a halfbridge circuit.......................................................................19
Fig. 25. SPICE turn-on waveform...................................... 21
Fig. 26. Measurement turn-on waveform........................... 21
Fig. 27. SPICE turn-off waveform...................................... 22
Fig. 28. Measurement turn-off waveform........................... 22

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Half-bridge MOSFET switching and its impact on EMC

Contents
1. Introduction................................................................... 2
2. Double pulse testing.................................................... 2
2.1. Measurement system.................................................. 3
2.2. MOSFET switching simulation.....................................4
2.3. MOSFET turn-off waveform description.......................5
2.4. MOSFET turn-on waveform description.......................9
3. Methods to improve switching performance............10
3.1. Voltage spikes........................................................... 10
3.1.1. Circuit layout...........................................................11
3.1.2. Reducing di/dt.........................................................11
3.2. Ringing.......................................................................133.2.1. Bypass capacitors...................................................13
3.2.2. Adding a snubber................................................... 14
3.3. Feedback into the gate signal................................... 14
3.4. Switching speed control.............................................15
3.4.1. Effect of varying RG................................................15
3.4.2. Effect of adding external gate to source
capacitance........................................................................ 16
3.4.3. Effect of adding gate to drain capacitance.............. 17
4. Impact on EMC and efficiency.................................. 19
5. Conclusions................................................................ 20
6. References.................................................................. 20
7. Appendix A: Comparison between SPICE
simulation and practical measurements for the
BUK7S1R0-40H in a double pulse test circuit............... 21
8. Revision history..........................................................23
9. Legal information........................................................24© Nexperia B.V. 2020. All rights reserved

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Date of release: 28 April 2020

AN90011application note

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Rev. 1.0 — 28 April 2020

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