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TPS63070
TPS630701
SLVSC58A – JUNE 2016 – REVISED AUGUST 2016

TPS63070 2-V to 16-V Buck-Boost Converter With 3.6-A Switch Current
1 Features

2 Applications

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Input Voltage Range: 2.0 V to 16 V
Output Voltage Range: 2.5 V to 9 V
Up to 95% Efficiency+/- 1% dc accuracy in PWM mode
+3% / -1% dc accuracy in PFM mode
2 A Output Current in Buck Mode
2 A Output Current in Boost Mode
(VIN = 4 V; Vout = 5 V)
Precise ENABLE input allows– user defined undervoltage lockout– exact sequencing
Automatic Transition Between Step Down and
Boost Mode
Typical Device Quiescent Current: 50 μA
Fixed and Adjustable Output Voltage Options
Power Save Mode for Improved Efficiency at Low
Output Power
Forced Fixed Frequency Operation at 2.4 MHz
and Synchronization Option
Power Good Output
VSEL simply allows output voltage change
Load Disconnect During Shutdown
Overtemperature Protection
Input / Output Overvoltage Protection
Available in QFN Package

3 Description
The TPS6307x is a high efficiency, low quiescentcurrent buck-boost converter suitable for applications
where the input voltage can be higher or lower thanthe output voltage. Output currents can go as high as
2 A in boost mode and in buck mode. The buck-boost
converter is based on a fixed frequency, pulse-widthmodulation (PWM) controller using synchronousrectification to obtain maximum efficiency. At low load
currents, the converter enters Power Save Mode tomaintain high efficiency over a wide load current
range. The converter can be disabled to minimize
battery drain. During shutdown, the load is
disconnected from the battery. The device is available
in a 2.5 mm x 3 mm QFN package.
Device Information(1)PACKAGEBODY SIZE (NOM)

TPS63070

PART NUMBER

VQFN

2.5 mm x 3 mm

TPS630701

VQFN

2.5 mm x 3 mm(1) For all available packages, see the orderable addendum atthe end of the datasheet.

Simplified Schematic

Efficiency vs Output Current; Vo = 5 V

L

100%

1.5 µH

VIN = 2.0 V to 16 V

C1

10 µF

CIN
2x10 µF
0805

90%
L2
TPS63070
VOUT

VIN

FB
VSEL

FB2

EN

PG

VOUT = 2.5 V to 9 V

10 µF
0603

0603

R5

C4

R1

COUT
3x22 µF
0805

R4
R2 100 kΩ

10 kΩ

CVAUX

PS/SYNC

PGND

VAUX

GND

80%
70%
Efficiency

L1

Dual LI-Ion Applications
Industrial Metering Equipment
DSC's and Camcorders
Notebook Computers
Ultra Mobile PC's and Mobile Internet Devices
Personal Medical Products

60%
50%
40%

3V
4.2 V
5V
7V
9V
12 V

30%
20%
10%

100 nF
Copyright © 2016, Texas Instruments Incorporated

0
100P

1m

10m
100m
Output Current (A)

1

2
D001

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

TPS63070
TPS630701
SLVSC58A – JUNE 2016 – REVISED AUGUST 2016

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Table of Contents
1
2
3
4
5
6
7

Features .................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions ......................... 3
Specifications......................................................... 4
7.1
7.2
7.3
7.4
7.5
7.6

8

Absolute Maximum Ratings ...................................... 4
ESD Ratings ............................................................ 4
Recommended Operating Conditions....................... 4
Thermal Information ................................................. 5
Electrical Characteristics........................................... 6
Typical Characteristics .............................................. 8

Detailed Description .............................................. 9
8.1
8.2
8.3
8.4
8.5

Overview ................................................................... 9
Functional Block Diagram TPS63070 ....................... 9
Functional Block Diagram TPS630701 ................... 10
Feature Description................................................. 10
Device Functional Modes........................................ 14

9

Application and Implementation ........................ 16
9.1 Application Information............................................ 16
9.2 Typical Application for adjustable version .............. 16
9.3 Typical Application for Fixed Voltage Version ....... 24

10 Power Supply Recommendations ..................... 28
10.1 Thermal Information .............................................. 28

11 Layout................................................................... 29
11.1 Layout Guidelines ................................................. 29
11.2 Layout Example .................................................... 29

12 Device and Documentation Support ................. 30
12.1
12.2
12.3
12.4
12.5
12.6
12.7

Device Support .................................................... 30
Related Links ........................................................ 30
Receiving Notification of Documentation Updates 30
Community Resources.......................................... 30
Trademarks ........................................................... 30
Electrostatic Discharge Caution ............................ 30
Glossary ................................................................ 30

13 Mechanical, Packaging, and Orderable
Information ........................................................... 31

4 Revision History
Changes from Original (June 2016) to Revision A
•

2

Page

Added full Production Data .................................................................................................................................................... 1

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5 Device Comparison Table
Device Number

Features

Output Voltage

Marking

TPS63070

output discharge = offadjustable

3070

TPS630701

output discharge = off

fixed 5 V

0701

6 Pin Configuration and Functions
QFN PACKAGE

Bottom View

Top View

FB2

10
VAUX

GND

FB

FB

5

10
4

3

2

1
PS/S

4 5

14

PG

3

11

9

6

VAUX

2

13

GND

1

PG

15

12 VIN

7

6 FB2

PS/S

VSEL

9

11

14

8

L1

7

13
EN

VOUT

PGND

8 VOUT

L2

L2

PGND

L1

VIN 12

15

EN
VSEL

Pin Functions
PIN

I/O

DESCRIPTION

NAME

NO.

EN

14

I

Enable input. Pull high to enable the device, pull low to disable the device.

FB

5

I

Voltage feedback of adjustable versions, must be connected to VOUT on fixed output voltage
versions

GND

4

L1

11

I

Control / logic ground
Connection for Inductor

L2

9

I

Connection for Inductor

PS/SYNC

1

I

Pull to low for forced PWM, pull high for PWM/PFM (power save) mode. Apply a clock signal tosynchronize to an external frequency.

PG

2

O

Open drain power good output

PGND

10

VIN

12, 13I

Supply voltage for power stage

VOUT

7,8

O

Buck-boost converter output

VAUX

3

O

Connection for Capacitor of internal voltage regulator. This pin must not be loaded externally.

VSEL

15

I

Voltage scaling input. A high level on this pin enables a transistor which pulls pin FB2 to GND.

FB2

6

O

Voltage scaling output. Connect a resistor from FB to FB2 to change the voltage divider ratio on the
feedback pin. A logic high level on VSEL will change the output voltage to a higher value. Leave thepin open or connect to GND if not used.

Power ground

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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)

Voltage range

MIN

MAX

UNIT

VIN, PS/SYNC, EN, VSEL

–0.3

20

V

L1

–0.3

20

V

L2, PG, VOUT, FB

–0.3

12

V

AUX

–0.3

7

V

FB2

–0.3

3

V

–40

150

°C

–65

150

Operating junction
temperature, Tj
Storage temperature
range, Tstg
(1)

°C

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings
VALUE
(1)

±2000

Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins (2)±500

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins
V(ESD)(1)(2)

Electrostatic discharge

UNIT
V

JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN

NOM

MAX

UNIT

Supply voltage at VIN

2.0

16

V

Output Voltage

2.5

9

V

2

A

2.8

µH

Output Current IOUT
Effective Inductance

0.7

1.5

Capacitance connected to VIN pin

4.7

10

Capacitance connected to VAUX pin
Total capacitance connected to VOUT pin (1)15Operating junction temperature range, TJ

–40

(1)

4

µF

100
47

nF
470

µF

125

°C

Due to the dc bias effect of ceramic capacitors, the effective capacitance is lower than the nominal value when a voltage is applied. This
is why the capacitance is specified to allow the selection of the minimal capacitor required with the dc bias effect for this type of
capacitor in mind. The capacitance range given above is for the nominal inductance of 1.5 µH. Please also see the detailed design
procedure in the application section about the ratio of inductance and minimum output capacitance.

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7.4 Thermal Information
TPS63070x
THERMAL METRIC (1)

VQFN

UNIT

13 PINS
RθJA

Junction-to-ambient thermal resistance

63

°C/W

RθJC(top)

Junction-to-case (top) thermal resistance

42

°C/W

RθJB

Junction-to-board thermal resistance

13

°C/W

ψJT

Junction-to-top characterization parameter

2.4

°C/W

ψJB

Junction-to-board characterization parameter

13

°C/W

RθJC(bot)

Junction-to-case (bottom) thermal resistance

n/a

°C/W

(1)

For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

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7.5 Electrical Characteristics
over VIN = 2V to 16V; Tj = -40°C to 125°C; typical values are at Tj = 25°C (unless otherwise noted)
PARAMETERTEST CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLY
VIN

Input voltage range

once started; Vout ≥ 3.0 V

2.0

16

V

VIN

Input voltage range

for start-up; Vout < 3.0 V

3.0

16

V

IOUT

Output current

during operation with either
VIN ≥ 4.5 V or VOUT ≥ 4.5 V
and the boost factor(VOUT/VIN) ≤ 1

2

A

IQ

Quiescent current

into VIN; IOUT= 0 mA,
VEN = VIN = 6 V, PFM
VOUT = 5 V; Tj = -40°C to 85°C

103

μA

IQ

Quiescent current

into VIN; IOUT= 0 mA,
VEN = VIN = 6 V, PFM
VOUT = 5 V; Tj = -40°C to 125°C

133

μA

IQ

Quiescent current

into VOUT; IOUT= 0 mA,
VEN = VIN = 6 V, VOUT = 5 V, PFM
Tj = -40°C to 85°C

9

μA

IQ

Quiescent current

into VOUT; IOUT= 0 mA,
VEN = VIN = 6 V, VOUT = 5 V, PFM
Tj = -40°C to 125°C

17

μA

ISD

Shutdown current

VEN = 0 V; Tj = -40°C to 85°C;
VIN = 5V

12

μA

ISD

Shutdown current

VEN = 0 V; Tj = -40°C to 85°C

26

μA

VUVLO

Undervoltage lockout threshold

VIN voltage falling

1.7

1.85

VUVLO,TH

Undervoltage lockout hysteresis

VIN voltage rising

525

850

mV

TSD

Thermal shutdown

160

°C

TSD

Thermal shutdown hysteresis

20

°C

54

5

2

1.95

V

LOGIC SIGNALS: EN, PS/SYNC, PG, VSEL
VTHR

Threshold Voltage rising edge for
EN pin and PS/SYNC used for
PWM/PFM mode change

0.77

0.8

0.83

V

VTHF

Threshold Voltage falling edge for
EN pin and PS/SYNC used for
PWM/PFM mode change

0.67

0.7

0.73

V

VIL

VSEL low level input voltage;
PS/SYNC low level input voltage
when used for synchronization

0.3

V

VIH

VSEL high level input voltage;
PS/SYNC high level input voltage
when used for synchronization

1.1
V

EN, PS/SYNC, VSEL input current

0.2

μA

VOL

PG output low voltage

IPG = -1 mA

0.4

V

ILKG

PG output leakage current

PG pin high impedance; VPG = 5 V

0.2

μA

IPG

PG sink current

1

mA

VTH_PGPower Good Threshold Voltage,rising Vout

94.5

96

98.5

%

VTH_PGPower Good Threshold Voltage,
falling Vout

90

92

94.5

%

VOUT

TPS63070 output voltage range (1)

2.5

9

V

VOUT

TPS630701 output voltage

VFB

TPS63070 feedback voltage
feedback impedance

OUTPUT

(1)
6

5.0

V

PS/SYNC = VIN

800

mV

for fixed voltage versions

1.5

MΩ

Please observe the minimum duty cycle in buck mode
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Electrical Characteristics (continued)
over VIN = 2V to 16V; Tj = -40°C to 125°C; typical values are at Tj = 25°C (unless otherwise noted)
PARAMETER
VOUT
VOUT

TEST CONDITIONS

MIN

MAX

UNIT

feedback leakage

for adjustable version; VFB = 0.8V

100

nA

TPS63070 output voltage accuracy

PS/SYNC = GND (PWM mode)

-1

1

%

TPS63070 output voltage accuracy

PS/SYNC = VIN (PFM mode);
VIN ≥ 3V

-1

3

%

2700

kHz

2800

kHz

4150

mA

duty cycle in buck mode
fSW

TYP

30

Oscillator frequency

2100

Frequency range for synchronization

2100

%
2400

IIN,max

Average, positive input current limit

VIN = 5.0V; VOUT = 6.5V;
Tj = 0°C to 125°C

3050

3600

IIN,max

Average, negative input current limit

VIN = 5.0V; VOUT = 6.5V;
Tj = 0°C to 125°C

1100

1800

RDS(ON)-High side switch on resistance

VIN = 5 V

50

80

mΩ

BUCK

Low side switch on resistance

VIN = 5 V

100

160

mΩ

RDS(ON)-High side switch on resistance

VIN = 5 V

40

70

mΩ

BOOST

Low side switch on resistance

VIN = 5 V

80

125

mΩ

RDS(ON)-FB2 resistance to GND
with VSEL = high

25

100

Ω

100

nA

FB2

ILKG

Input leakage current into FB2
with VSEL=low

VFB = VFB2 = 0.8V

FB2 sink current

VAUX

tdelay

tSS

mA

100

Line regulation

Power Save Mode disabled

Load regulation

Power Save Mode disabled

0.07

μA
%/V

0.2

%/A

VIN ≥ VOUT; VIN < 6V

VIN - 0.3

7

Maximum bias voltage

VIN < VOUT

VOUT 0.3

7

output discharge resistance

VIN ≥ 2.5V

250Ω

Start-up delay

time from EN = VIH to device starts
switching70

μs

time to ramp from 5% to 95% of
Vout; buck mode; VIN = 7.2 V,
Vout = 3.3 V, Iout = 500 mA

400

μs

time to ramp from 5% to 95% of
Vout; boost mode; VIN = 3.0 V,
Vout = 3.3 V, Iout = 250 mA

850

μs

soft-start time

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7.6 Typical Characteristics
90

60
-40
30
85
125

80

50
RDSon [m:]RDSon [m:]

70

-40
30
80
125

55

60
50
40

45
40
35
30

30

25

20

20
0

5

10
VIN [V]

15

20

0

Vout = 5V

I = 1A

10
VIN [V]

15

20
D020

Vout = 5V

Figure 1. Rds(on) of High-side Buck Switch

I = 1A

Figure 2. Rds(on) of High-side Boost Switch
150

120
-40
30
85
125

110
100

-40
30
85
125

140
130
120
RDSon [m:]RDSon [m:]

5

D019

90
80

110
100
90
80

70

70
60

60
50

50
0

5

10
VIN [V]

15

0

5

D021

Vout = 5V

I = 1A

Figure 3. Rds(on) of Low-side Boost Switch

8

20

10
VIN [V]

15

Vout = 5V20
D022

I = 1A

Figure 4. Rds(on) of Low-side Buck Switch

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8 Detailed Description
8.1 Overview
The TPS6307x use 4 internal N-channel MOSFETs to maintain synchronous power conversion at all possible
operating conditions. This enables the device to keep high efficiency over a wide input voltage and output power
range. To regulate the output voltage at all possible input voltage conditions, the device automatically switchesfrom buck operation to boost operation and back as required by the configuration. It always uses one active
switch, one rectifying switch, one switch on, and one switch held off. Therefore, it operates as a buck converter
when the input voltage is higher than the output voltage, and as a boost converter when the input voltage islower than the output voltage. There is no mode of operation in which all 4 switches are switching. The RMS
current through the switches and the inductor is kept at a minimum, to minimize switching and conduction losses.
For the remaining 2 switches, one is kept on and the other is kept off, thus causing no switching losses.
Controlling the switches this way allows the converter to always keep high efficiency over the complete input
voltage range. The device provides a seamless transition from buck to boost or from boost to buck operation.

8.2 Functional Block Diagram TPS63070
L1

L2

VIN

VOUT
VIN

VOUT

Bias
Regulator

VIN
VAUX
VOUT

VAUX

VAUX
PG

PS/SYNC

Current
Sensor

PGND

PGND

Gate
Control_

Modulator_+

Oscillator

FB

+
+
-

DeviceControl

EN

VREF

FB2

VSEL

GND

PGND

Temperature
Protection
PGND

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8.3 Functional Block Diagram TPS630701
L1

L2

VIN

VOUT
VIN

VOUT

Bias
Regulator

Current
Sensor

VIN
VAUX
VOUT

VAUX

VAUX

PGND
FB

_

Modulator

_

+
+

PG

PS/SYNC

PGND
Gate
Control

Oscillator+-

DeviceControl

VREF

EN

FB2

VSEL

GND

PGND

Temperature
Protection
PGND

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8.4 Feature Description
8.4.1

Control Loop Description

The controller circuit of the device is based on an average current mode topology. The average inductor current
is regulated by a fast current regulator loop which is controlled by a voltage control loop.
The non inverting input of the transconductance amplifier gmv can be assumed to be constant. The output of
gmv defines the average inductor current. The inductor current is reconstructed by measuring the current throughthe high side buck MOSFET. This current corresponds exactly to the inductor current in boost mode. In buckmode, the current is measured during the on-time of the same MOSFET. During the off-time, the current isreconstructed internally starting from the peak value reached at the end of the on-time cycle. The average
current is then compared to the desired value and the difference, or current error, is amplified and compared tothe sawtooth ramp of either the Buck or the Boost. Depending on which of the two ramps is crossed by thesignal, either the Buck MOSFETs or the Boost MOSFETs are activated. When the input voltage is close to the
output voltage, one buck cycle is followed by a boost cycle. In this condition, not more than three cycle in a rowof the same mode are allowed. This control method in the buck-boost region ensures a robust control and thehighest efficiency.
For an input voltage above 9 V, and Vout below 2.2 V, the switching frequency is reduced by a factor of 2 tokeep the minimum on-time at a reasonable value. For short circuit protection, at an output voltage below 1.2V,
the low side input FET and the high side output FET are not actively switched but their back-gate diode used for
conduction. Therefore an output voltage below 1.5V should in general be avoided.

10

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Feature Description (continued)
L2

L1

Vin

Vout
Boost
Drive

Buck
Drive

PWM

PWM

Buck
Ramp

Boost
Ramp

gmc

Rs
gmv

FB
Vref
0.8V

Ramp Generator

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Figure 5. Average Current Mode Control
8.4.2 Enable
The enable pin of the TPS63070 is not just a simple digital input but compares the voltage applied to a fixed
threshold of 0.8V for a rising voltage. This allows to drive the pin by a slowly changing voltage and enables theuse of an external RC network to achieve a precise power-up delay. The enable input threshold for a falling edge
is typically 100mV lower than the rising edge threshold. The TPS63070 starts operation when the rising thresholdis exceeded. For proper operation, the EN pin must be terminated and must not be left floating. Pulling the EN
pin low forces the device into shutdown. In this mode, the internal high side and low side MOSFETs are turned
off and the entire internal-control circuitry is switched off. The enable pin can also be used with an external
voltage divider to set a user-defined minimum supply voltage.
It is recommended to not connect EN directly to VIN but use a resistor in series in the range of 1kΩ to 1MΩ. If
several inputs like EN and PS/SYNC are connected to VIN, the resistor can be shared. No resistor is required if
the pin is driven from an analog or digital signal rather than a supply voltage.
8.4.3 Power Good
The device has a built in power good output that indicates whether the output voltage has reached its nominal
value. The PG signal is generated based on the status of the output voltage monitor. The power good circuit
operates as long as the converter is enabled and VIN is above the undervoltage lockout threshold.
If the output voltage has not reached the regulated condition, the PG pin is held low. When the regulated
condition is reached, PG is high impedance.
The PG output needs an external pull-up resistor. This resistor can be pulled to any voltage up to the maximum
output voltage rating.
Table 1. Power Good Status
EN

output voltage status

PG

low

output off

low

high

output voltage above power goodthresholdhigh impedance

highoutput voltage below power goodthreshold, in thermal shutdown or input /output overvoltage protection active

low

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8.4.4

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Soft Start

To minimize inrush current during start up, the device has a soft start. When the EN pin is set high, after athermal shutdown or after the undervoltage lockout threshold is exceeded, a soft-start cycle is started and the
input current is ramped until the output voltage reaches regulation. The device ramps up the output voltage in acontrolled manner, even if a large capacitor is connected at the output. During soft-start, as long as the output
voltage is below the power good threshold, the input current limit is reduced to typically 1A.
8.4.5 PS/SYNC
The PS/SYNC pin has two functions:• switching between forced PWM mode and power save mode
• synchronizing to an external clock applied at pin PS/SYNC
When PS/SYNC is set high, the device operates in power save mode at low output current. For an average
inductor current above a certain threshold the device switches to forced PWM mode. The automatic switch-overfrom PFM to PWM and vice versa is done such that the efficiency is kept at the maximum possible level. It is notbased on a fixed threshold but at a current that depends on input voltage and output voltage to keep the
efficiency at the maximum possible level.
The power save mode is disabled when PS/SYNC is set low. The device then operates in forced fixed frequency
PWM mode independent of the output current.
TPS6307x can be synchronized to an external clock applied at pin PS/SYNC. Details about the voltage level andfrequency range can be found in the electrical characteristics. When an external clock is detected, TPS6307x
switches from internal clock or power save mode to fixed frequency operation based on the external clock
frequency. When the external clock is removed, TPS6307x switches back to internal clock or power save mode
depending on the average inductor current and status of the PS/SYNC pin. The PS/SYNC pin has two parallel
input stages, a slow one with the precise threshold for PWM/PFM mode change and a fast digital input stage foran external clock signal for synchronization.
It is recommended to not connect PS/SYNC directly to VIN but use a resistor in series in the range of 1kΩ to
1MΩ. If several inputs like EN and PS/SYNC are connected to VIN, the resistor can be shared. No resistor isrequired if the pin is driven from an analog or digital signal rather than a supply voltage.
8.4.6

Short Circuit Protection

The TPS6307x provides short circuit protection to protect itself and the application. When the output voltage isbelow 1.2 V, the back-gate diodes of the low side input FET and high side output FET are used for rectification.
For an input voltage above 9 V and an output voltage below 2.2 V, the switching frequency is scaled to ½ of its
nominal value.

12

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8.4.7

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VSEL and FB2 pins

The VSEL pin allows to select between two different output voltages on the adjustable version. The voltage is set
by a resistor that is connected between the FB and the FB2 pin. FB2 is connected to GND if VSEL = high. FB2 ishigh impedance if VSEL= low.
1.5 µH
TPS63070
L1

L2

VIN

VOUT

VIN = 2.0 V to 16 V
2x10 µF
0805

10 µF

VOUT = Vo1 / Vo2
10 µF
0603

0603

R1

3x22 µF

FB
10 kΩ

PS/SYNC
EN

VSEL

R2

R3

FB2
PG
PGND

VAUX

GND

100 nF
Copyright © 2016, Texas Instruments Incorporated

Figure 6. Typical Application using VSEL
The resistor values for the feedback divider and FB2 are in the 50-500kΩ range. R3 is calculated as follows:(1)

8.4.8 Overvoltage Protection
TPS6307x has a built in over-voltage protection which limits the output voltage. The voltage is internally sensed
on the VOUT pin. In case the voltage on the feedback pin is not set correctly or the connection is open, this limits
the output voltage to a value that protects the output stage from a too high voltage by limiting it to a internally set
value.
Input over-voltage protection forces PFM mode to make sure the device is protected against boosting from theoutput to the input. This may happen if there is a large capacitor charged above the nominal voltage on the
output and the supply on the input is removed. In PWM mode, the device is able to provide current from theoutput to the input causing a rise in the input voltage. In PFM mode, the current to the input is blocked so the
input voltage can not rise. The input over-voltage protection does not protect the device from a too high voltage
applied to the input but just from operating such that the device itself causes a rise of the input voltage above
critical levels. Both over-voltage sensors are de-glitched by approximately 1µs.
8.4.9 Undervoltage Lockout
When the input voltage drops, the undervoltage lockout prevents mis-operation by switching off the device. The
converter starts operation when the input voltage exceeds the threshold by a hysteresis of typically 850 mV. This
relatively large hysteresis is needed to allow operation down to 2-V of supply voltage for the case when the
output voltage is up at 3-V or above but restrict start-up for the case when the output voltage is zero. For start-up
when the output voltage has not yet ramped, the rising UVLO threshold was set to a level that allows to start
TPS63070 at a supply voltage where the load does not demand much load current.
8.4.10 Overtemperature Protection
The junction temperature (Tj) of the device is monitored by an internal temperature sensor. When Tj exceeds thethermal shutdown temperature, the device goes into thermal shutdown. The power stage is turned off and PG
goes low. When Tj decreases below the hysteresis amount, the converter resumes normal operation, beginningwith a Soft Start cycle. To avoid unstable conditions, a hysteresis of typically 20°C is implemented on the thermal
shutdown temperature. In addition, the thermal shutdown is debounced by approximately 10 µs.

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8.5 Device Functional Modes
8.5.1 Power Save Mode
Depending on the load current, in order to provide the best efficiency over the complete load range, the device
works in PWM mode at an inductor current of approximately 650 mA or higher. At lighter load, the device
switches automatically in to Power Save Mode to reduce power consumption and extend battery life. The
PFM/PWM pin can be used to select between the two different operation modes. To enable Power Save Mode,the PFM/PWM pin must be set high.
During Power Save Mode, the part operates with a reduced switching frequency and supply current to maintainhigh efficiency. The output voltage is monitored by a comparator for the threshold "comp low" and "comp high" atevery clock cycle. When the device enters Power Save Mode, the converter stops operating and the output
voltage drops. The slope of the output voltage depends on the load and the output capacitance. When the output
voltage reaches the comp low threshold, at the next clock cycle the device ramps up the output voltage again bystarting operation. Operation can last for one or several pulses until the "comp high" threshold is reached. At thenext PFM cycle, if the output current is still lower than about 650 mA, the device switches off again and the same
operation is repeated. Instead, if at the next PFM cycle, the load is above approximately 650 mA , the device
automatically switches to PWM mode.
In order to keep high efficiency in PFM mode, there is only a comparator active to keep the output voltage
regulated. The AC ripple in this condition is increased, compared to the voltage in PWM mode. The amplitude ofthis voltage ripple typically is 50 mV pk-pk, with 22 µF effective capacitance. In order to avoid a critical voltage
drop when switching from 0 A to full load, the output voltage in PFM is typically 1 % above the nominal value in
PWM. This allows the converter to operate with a small output capacitor and still have a low absolute voltage
drop during heavy load transients.
Power Save Mode can be disabled by programming the PFM/PWM pin low.
Heavy Load transient step
PFM mode at light load
current

Comparator high

+1%*Vo50mV ripple in PFM

Comparator low

Vo

PWM mode
Absolute Voltage dropwith positioning

Figure 7. Dynamic Voltage Positioning
8.5.2 Current Limit
it is possible to calculate the output current in the different conditions in boost mode using Equation 2 andEquation 3 and in buck mode using Equation 4 and Equation 5.
V
-V
IN
OUT
V
OUT

(2)

Output Current Boost

IOUT = 0 x IIN (1-D)(3)

Duty Cycle BuckD=

Duty Cycle Boost

14

D=

V
OUT
V
IN

(4)

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Device Functional Modes (continued)
Output Current Buck

IOUT = ( 0 x IIN ) / D

(5)

With,
η = Estimated converter efficiency (use the number from the efficiency curves or 0.90 as an assumption)
f = Converter switching frequency (typical 2.4MHz)
L = Selected inductor value
IIN=Minimum average input current (, , and )8.5.3 Output Discharge Function (optional)
To make sure the load applied at TPS63070 is powered up from 0 V once TPS63070 is enabled, the device
features an internal discharge resistor for the output capacitor. The discharge function is enabled as soon as thedevice is disabled, in thermal shutdown or in undervoltage lockout. The minimum supply voltage required for thedischarge function to remain active when enabled is approximately 2 V. The discharge function is only active
after the device has been enabled at least once after supply voltage was applied.

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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

9.1 Application Information
The TPS6307x is a high efficiency, low quiescent current buck-boost converter suitable for applications where
the input voltage can be higher or lower than the output voltage. The TPS63070 is internally supplied from thehigher of the input voltage or output voltage. For proper operation either one or both need to have a voltage of
3.0 V or above but must not exceed their maximum rating.

9.2 Typical Application for adjustable versionL
1.5 µH
L1
VIN = 2.0 V to 16 V

C1

10 µF

CIN
2x10 µF
0805

L2
TPS63070
VOUT

VIN

VOUT = 2.5 V to 9 V

C4
10 µF
0603

R1

0603

R4
R2 100 kΩ

FB
R5

VSEL

FB2

EN

PG

COUT
3x22 µF
0805

10 kΩ

CVAUX

PS/SYNC

PGND

VAUX

GND

100 nF
Copyright © 2016, Texas Instruments Incorporated

Figure 8. Typical Application For Adjustable Version
9.2.1 Design Requirements
The design guidelines provide a component selection to operate the device within the recommended operating
conditions. The input and output capacitors have been split into a small 0603 size capacitor close to the device
pins and 0805 size capacitors to get the required capacitance.
Table 2. Bill of Materials

16

REFERENCEDESCRIPTIONIC

TPS63070RNM

VALUE

MANUFACTURER

L

XFL4020-152ME

1.5 µH

Coilcraft

CIN

GRM21BC71E106ME11L

2 x 10 µF / 25 V /X7S / 0805

MurataC1

TMK107BBJ106MA-T

10 µF / 25 V / X5R /0603

Taiyo Yuden

COUT

GRM21BC81C226ME44L

3 x 22 µF / 16 V /X6S / 0805

MurataC4

TMK107BBJ106MA-T

10 µF / 25 V / X5R /0603

Taiyo Yuden

Texas Instruments

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Table 2. Bill of Materials (continued)
REFERENCEDESCRIPTIONVALUE

MANUFACTURERCVAUX

TMK105B7104MV-FR

100 nF / 25V / X7R /0402

Taiyo Yuden

R1, R2

Metal Film Resistor ; 1%

depending on desired
output voltage

R4

Metal Film Resistor ; 1%

100 kΩ

9.2.2 Detailed Design Procedure
The TPS6307x series of buck-boost converter has internal loop compensation. Therefore, the external L-C filter
has to be selected according to the internal compensation. It's important to consider that the effective inductance,
due to inductor tolerance and current derating can vary between 20% and -30%. The same for the capacitanceof the output filter: the effective capacitance can vary between +20% and -80% of the specified datasheet value,
due to capacitor tolerance and bias voltage. For this reason, Output Filter Selection shows the nominal
capacitance and inductance value allowed. The effective capacitance of the adjustable version TPS63070 on the
output (in µF) needs to be at least 10 times higher than the effective inductance (in µH) to ensure a goodtransient response and stable operation.
Table 3. Output Filter Selection
INDUCTORVALUE [µH] (1)OUTPUT CAPACITOR VALUE [µF] (2)
47

68

100

1.0

22

√

√

√

1.5

√ (3)

√

√

√

√

2.2
(1)
(2)
(3)

Inductor tolerance and current de-rating is anticipated. The effective inductance can vary by +20% and–30%.
Capacitance tolerance and bias voltage de-rating of +20% and -50% is anticipated. For capacitors withlarger dc bias effect, a larger nominal value needs to be selected.
Typical application. Other check marks indicates recommended filter combinations

9.2.2.1 Programming The Output Voltage
While the output voltage of the TPS63070 is adjustable, the TPS630701 is set to a fixed voltage. For fixed output
versions, the FB pin must be connected to the output directly. The adjustable version can be programmed for
output voltages from 0.8V to 9V by using a resistive divider from VOUT to GND. The voltage at the FB pin(VREF)is regulated to 800mV. The value of the output voltage is set by the selection of the resistive divider from
Equation 6 . It is recommended to choose resistor values which allow a current of at least 2uA, meaning thevalue of R2 shouldn't exceed 400kΩ. Lower resistor values are recommended for highest accuracy and mostrobust design.

æVö
R1 = R 2 çç OUT - 1÷÷è V REFø(6)

Table 4. Typical Resistor Values
Output Voltage

R1

R2

3.3 V

470 kΩ

150 kΩ

5.0 V

680 kΩ

130 kΩ

5.3 V

560 kΩ

100 kΩ

5.5 V

300 kΩ

51 kΩ

6.5 V

360 kΩ

51 kΩ

9V

402 kΩ

39 kΩ

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9.2.2.2 Inductor Selection
For high efficiencies, the inductor should have a low dc resistance to minimize conduction losses. Especially athigh switching frequencies, the core material has a higher impact on efficiency. When using small chip inductors,
the efficiency is reduced mainly due to higher inductor core losses. This needs to be considered when selecting
the appropriate inductor. The inductor value determines the inductor ripple current. The larger the inductor value,
the smaller the inductor ripple current and the lower the conduction losses of the converter. Conversely, larger
inductor values cause a slower load transient response. To avoid saturation of the inductor, the peak current for
the inductor in steady state operation is calculated using Equation 8. Only the equation which defines the switch
current in boost mode is shown, because this provides the highest value of current and represents the criticalcurrent value for selecting the right inductor.
Duty Cycle Boost

D=

V
-V
IN
OUT
V
OUT

(7)

Iout
Vin ´ D
IPEAK =+
η ´ (1 - D)
2 ´ f ´ L

(8)Where,
D =Duty Cycle in Boost modef = Converter switching frequency (typical 2.4MHz)
L = Selected inductor valueη = Estimated converter efficiency (use the number from the efficiency curves or 0.90 as an assumption)
Note: The calculation must be done for the minimum input voltage which is possible to have in boost mode
Calculating the maximum inductor current using the actual operating conditions gives the minimum saturation
current of the inductor needed. It is recommended to choose an inductor with a saturation current 20% higher
than the value calculated from Equation 8. The following inductors are recommended for use:
Table 5. Inductor Selection(1)

INDUCTOR VALUECOMPONENT SUPPLIER (1)SIZE (LxWxH /mm)Isat/DCR

1.2 µH

Coilcraft, XFL4015-122ME

4 x 4 x 1.5

4.5 A / 18.8 mΩ

1.5 µH

Coilcraft, XFL4020-152ME

4 x 4 x 2.1

4.6 A / 14.4 mΩ

1.0 µH

Coilcraft, XFL4020-102ME

4 x 4 x 2.1

5.4 A / 10.8 mΩ

1 µH

Murata, 1277AS-H-1R0M

3.2 x 2.5 x 1.2

3.7 A / 45 mΩ

See Third-party Products Disclaimer

The inductor value also affects the stability of the feedback loop. In particular the boost transfer function exhibits
a right half-plane zero. The frequency of the right half plane zero is inverse proportional to the inductor value andthe load current. This means the higher the value of the inductance and load current, the more the right halfplane zero is moved to a lower frequency. This degrades the phase margin of the feedback loop. It is
recommended to choose the inductor's value in order to have the frequency of the right half plane zero >400
kHz. The frequency of the RHPZ is calculated using Equation 9.

(1 - D)2 ´ Voutf RHPZ =2p ´ Iout ´ L

(9)

With,
D =Duty Cycle in Boost mode
Note: The calculation must be done for the minimum input voltage which is possible to have in boost mode
If the operating conditions results in a frequency of the RHPZ of less than 400kHz, more output capacitanceshould be added to reduce the cross over frequency.

18

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9.2.2.3 Capacitor Selection
9.2.2.3.1

Input Capacitor

It is recommended to use a combination of capacitors on the input. A small size ceramic capacitor as close as
possible from the VIN pin to GND to block high frequency noise and a larger one in parallel for the required
capacitance on for good transient behavior of the regulator. X5R or X7R ceramic capacitor are recommended.
The input capacitor needs to be large enough to avoid supply voltage dips shorter than 5us as the undervoltage
lockout circuitry needs time to react.
9.2.2.3.2

Output Capacitor

Same as the input, the output capacitor should be a combination of capacitors optimized for suppressing highfrequency noise and a larger capacitor for low output voltage ripple and stable operation. The use of small X5R
or X7R ceramic capacitors placed as close as possible to the VOUT and GND pins of the IC is recommended. A
0603 size capacitor close to the pins of the IC and as many 0805 capacitors as required to get the capacitancegiven the output voltage and dc bias effect of the ceramic capacitors is best. The recommended typical output
capacitor values are outlined in Output Filter Selection. Please also see the Recommended Operating Conditions
for the minimum and maximum capacitance at the output.
Larger capacitors will cause lower output voltage ripple as well as lower output voltage drop during loadtransients.
Table 6. Typical Capacitors

(1)

VALUE

PART NUMBERCOMPONENTSUPPLIER (1)COMMENTSIZE (LxWxH mm)

22 µF

EMK212BBJ226MG-T

Taiyo Yuden

input capacitor for Vin ≤ 8 V

2 x 1.25 x 1.25

22 µF

TMK316BBJ226ML

Taiyo Yuden

input capacitor

3.2 x 1.6 x 1.6

10 µF

TMK107BBJ106MA-T

Taiyo Yuden

bypass capacitor directly at
device pins on VIN to GND
and VOUT to GND

1.6 x 0.8 x 0.8

10 µF

GRM21BC71E106ME11

Muratasmall body size; 2 parts
required if used at VIN > 6V

2 x 1.25 x 1.25

22 µF

GRM21BC81C226ME44

Muratasmall body size; 3 parts
required if used at Vo > 5V;
otherwise 2 parts

2 x 1.25 x 1.25

See Third-party Products Disclaimer

100%

100%

90%

90%

80%

80%

70%

70%

60%

60%

Efficiency

Efficiency

9.2.3 Application Curves

50%
40%

3V
4.2 V
5V
7V
9V
12 V

30%
20%
10%
0
100P

1m

Vout = 7 V

10m
100m
Output Current (A)

PFM

1

50%
40%

3V
4.2 V
5V
7V
9V
12 V

30%
20%
10%

2

0
100P

1m

D003

T = 25 °C

Figure 9. Efficiency vs Output Current

Vout = 7 V

10m
100m
Output Current (A)

PWM

1

2
D004

T = 25 °C

Figure 10. Efficiency vs Output Current

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100%

100%

90%

90%

80%

80%

70%

70%

60%

60%

Efficiency

Efficiency

SLVSC58A – JUNE 2016 – REVISED AUGUST 2016

50%
40%

3V
4.2 V
5V
7V
9V
12 V

30%
20%
10%
0
100P

1m

Vout = 9 V

10m
100m
Output Current (A)

PFM

1

50%
40%

3V
4.2 V
5V
7V
9V
12 V

30%
20%
10%
0
100P

2

T = 25 °C

Vout = 9 V

Figure 11. Efficiency vs Output Current

2
D006

T = 25 °C

7.14

3V
4.2 V
5V
7V
9V
12 V

7.21

Output Voltage (V)Output Voltage (V)

PWM

1

7.28
3V
4.2 V
5V
7V
9V
12 V

7.21

7.07
7
6.93
6.86

7.14
7.07
7
6.93
6.86

6.79
100P

1m

Vout = 7 V

10m
100m
Output Current (A)

PFM

1

6.79
100P

2

1m

D009

T = 25 °C

Vout = 7 V

Figure 13. Output Voltage vs Output Current

10m
100m
Output Current (A)

PWM

1

2
D010

T = 25 °C

Figure 14. Output Voltage vs Output Current

9.36

9.36

3V
4.2 V
5V
7V
9V
12 V

9.18

3V
4.2 V
5V
7V
9V
12 V

9.27

Output Voltage (V)9.27

Output Voltage (V)

10m
100m
Output Current (A)Figure 12. Efficiency vs Output Current

7.28

9.09
9
8.91
8.82

9.18
9.09
9
8.91
8.82

8.73
100P

1m

Vout = 9 V

10m
100m
Output Current (A)

PFM

1

2

8.73
100P

1m

D011

T = 25 °C

Figure 15. Output Voltage vs Output Current

20

1m

D005

Vout = 9 V

10m
100m
Output Current (A)

PWM

1

2
D012

T = 25 °C

Figure 16. Output Voltage vs Output Current

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1

4.5

0.9

4

0.8

3.5

0.7
0.6
0.5
0.4
0.3
-40qC
25qC
85qC
125qC

0.2
0.1

Max Output Current (A)Output Current (A)www.ti.com

3
2.5
2
1.5
-40qC
25qC
85qC
125qC

1
0.5

0

0
3

4

5

6

7

8
9 10 11 12 13 14 15 16
Input Voltage (V)D014

Vout = 7 V

2resistive load

3

4

5

6

7 8 9 10 11 12 13 14 15 16
Input Voltage (V)D017

Vout = 7 V

after start-up with
PG = highFigure 17. Typical Start-up Current
1

4.5

0.9

4

0.8

3.5

0.7
0.6
0.5
0.4
0.3
-40qC
25qC
85qC
125qC

0.2
0.1
0

Max Output Current (A)Output Current (A)Figure 18. Maximum Load Current vs Input Voltage

3
2.5
2
1.5
-40qC
25qC
85qC
125qC

1
0.5
0

3

4

5

6

7

8
9 10 11 12 13 14 15 16
Input Voltage (V)D015

Vout = 9 V

resistive load

2

3

4

5

6

7 8 9 10 11 12 13 14 15 16
Input Voltage (V)D018

Vout = 9 V

after start-up with
PG = highFigure 19. Typical Start-up Current
Figure 20. Maximum Load Current vs Input Voltage

Vout = 7 V

PFM

Vin = 4.2V

Figure 21. Load Transient Response

Vout = 7 V

PFM

Vin = 12V

Figure 22. Load Transient Response

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Vout = 9 V

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PFM

Vin = 4.2V

Figure 23. Load Transient Response

Vout = 7 V

PFM

Io = 1A

PFM

22

Vin = 12V

Vout = 9 V

PFM

Io = 1A

Figure 26. Line Transient Response

Io = 0.3A

Figure 27. Output Voltage Ripple

PFM

Figure 24. Load Transient Response

Figure 25. Line Transient Response

Vin = 5V; Vout = 7 V

Vout = 9 V

Vin = 5V; Vout = 7 V

PWM

Io = 1A

Figure 28. Output Voltage Ripple

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Vin = 12V; Vout = 7 V

PFM

Io = 0.3A

Figure 29. Output Voltage Ripple

Vin = 5V; Vout = 9 V

PWM

Io = 0.5A

PFM

PFM

Io = 0.1A

Figure 30. Output Voltage Ripple

Figure 31. Output Voltage Ripple

Vin = 4.5V; Vout = 7 V

Vin = 5V; Vout = 9 V

Vin = 12V; Vout = 9 V

PFM

Io = 0.1A

Figure 32. Output Voltage Ripple

Io = 0.5A

Vin = 7V; Vout = 9 V

Figure 33. Start-up Timing

PFM

Io = 0.5A

Figure 34. Start-up Timing

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9.3 Typical Application for Fixed Voltage Version
1.5 µH

L

TPS630701
L1
VIN = 2.0 V to 16 V

L2

CIN

10 µF

2x10 µF
0805

0603

VOUT
VIN

10 µF

COUT
3x22 µF
0805

0603

FB

R5

VOUT = 5 V

C4
C1

VSEL

FB2

EN

PG

R4
100 kΩ

10 kΩ

CVAUX

PS/SYNC

PGND

VAUX

GND

100 nF
Copyright © 2016, Texas Instruments Incorporated

Figure 35. Typical Application For Fixed Voltage Version With Minimum External Part Count And
Minimum Soft Start Time9.3.1 Design Requirements
The design guidelines provide a component selection to operate the device within the recommended operating
conditions. The input and output capacitors have been split into a small 0603 size capacitor close to the device
pins and 0805 size capacitors to get the required capacitance.
Table 7. Bill of Materials

24

REFERENCEDESCRIPTIONVALUE

MANUFACTURER

IC

TPS630701RNM

L

XFL4020-1.5µH

1.5 µH

Coilcraft

CIN

GRM21BC71E106ME11L

2 x 10 µF / 25 V /X7S / 0805

MurataC1

TMK107BBJ106MA-T

10 µF / 25 V / X5R /0603

Taiyo Yuden

COUT

GRM21BC81C226ME44L

3 x 22 µF / 16 V /X6S / 0805

MurataC4

TMK107BBJ106MA-T

10 µF / 25 V / X5R /0603

Taiyo YudenCVAUX

TMK105B7104MV-FR

100 nF / 25V / X7R /0402

Taiyo Yuden

R4

Metal Film Resistor ; 1%

100 kΩ

-Texas Instruments

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9.3.2 Detailed Design Procedure
The TPS6307x series of buck-boost converter has internal loop compensation. Therefore, the external L-C filter
has to be selected according to the internal compensation. It's important to consider that the effective inductance,
due to inductor tolerance and current derating can vary between 20% and -30%. The same for the capacitanceof the output filter: the effective capacitance can vary between +20% and -80% of the specified datasheet value,
due to capacitor tolerance and bias voltage. For this reason, Output Filter Selection shows the nominal
capacitance and inductance value allowed. For the fixed voltage version TPS630701, the effective capacitanceon the output (in µF) needs to be at least 15 times higher than the effective inductance (in µH) to ensure a goodtransient response and stable operation.

100%

100%

90%

90%

80%

80%

70%

70%

60%

60%

Efficiency

Efficiency

9.3.3 Application Curves

50%
40%

3V
4.2 V
5V
7V
9V
12 V

30%
20%
10%
0
100P

1m

Vout = 5 V

10m
100m
Output Current (A)

PFM

1

50%
40%

3V
4.2 V
5V
7V
9V
12 V

30%
20%
10%
0
100P

2

T = 25 °C

Vout = 5 V

Figure 36. Efficiency vs Output Current

10m
100m
Output Current (A)

PWM

1

2
D002

T = 25 °C

Figure 37. Efficiency vs Output Current
5.2

5.25
3V
4.2 V
5V
7V
9V
12 V

5.15
5.1

3V
4.2 V
5V
7V
9V
12 V

5.15

Output Voltage (V)5.2

Output Voltage (V)

1m

D001

5.05
5
4.95

5.1
5.05
5
4.95
4.9

4.9
4.85
100P

1m

Vout = 5 V

10m
100m
Output Current (A)

PFM

1

2

4.85
100P

1m

D007

T = 25 °C

Figure 38. Output Voltage vs Output Current

Vout = 5 V

10m
100m
Output Current (A)

PWM

1

2
D008

T = 25 °C

Figure 39. Output Voltage vs Output Current

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1

4.5

0.9

4

0.8

3.5

0.7
0.6
0.5
0.4
0.3
-40qC
25qC
85qC
125qC

0.2
0.1
0

Max Output Current (A)Output Current (A)SLVSC58A – JUNE 2016 – REVISED AUGUST 2016

3
2.5
2
1.5
-40qC
25qC
85qC
125qC

1
0.5
0

3

4

5

6

7

8
9 10 11 12 13 14 15 16
Input Voltage (V)D013

Vout = 5 V

resistive load

2

3

4

5

6

7 8 9 10 11 12 13 14 15 16
Input Voltage (V)D016

Vout = 5 V

after start-up with
PG = highFigure 40. Typical Start-up Current
Figure 41. Maximum Load Current vs Input Voltage

Vout = 5 V

PFM

Vin = 4.2V

Figure 42. Load Transient Response

Vout = 5 V

PFM

26

PFM

Vin = 12V

Figure 43. Load Transient Response

Io = 1A

Figure 44. Line Transient Response

Vout = 5 V

Vin = 4.2V; Vout = 5 V

PFM

Io = 0.3A

Figure 45. Output Voltage Ripple

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Vin = 4.2V; Vout = 5 V

PWM

Io = 1A

Vin = 7.2V; Vout = 5 V

Figure 46. Output Voltage Ripple

PFM

Io = 0.3A

Figure 47. Output Voltage Ripple

Vin = 4.5V; Vout = 5 V

PFM

Io = 0.5A

Figure 48. Start-up Timing

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10 Power Supply Recommendations
The TPS63070 device family has no special requirements for its power supply. The power supply output current
needs to be rated according to the supply voltage, output voltage and output current of TPS63070. Please see
the layout guidelines about the placement of the external components.

10.1 Thermal Information
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added
heat sinks and convection surfaces, and the presence of other heat-generating components affect the powerdissipation limits of a given component.
Three basic approaches for enhancing thermal performance are listed below.
• Improving the power dissipation capability of the PCB design• Improving the thermal coupling of the component to the PCB by soldering the PowerPAD™
• Introducing airflow in the system
For more details on how to use the thermal parameters in the dissipation ratings table please check the Thermal
Characteristics Application Note (SZZA017) and the IC Package Thermal Metrics Application Note (SPRA953).

28

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11 Layout11.1 Layout Guidelines
For all switching power supplies, the layout is an important step in the design, especially at high peak currents
and high switching frequencies. If the layout is not carefully done, the regulator could show stability problems aswell as EMI problems. Therefore, use wide and short traces for the main current path and for the power groundconnection. The input capacitor, output capacitor, and the inductor should be placed as close as possible to the
IC. Use a common ground node for power ground and a different one for control ground to minimize the effects
of ground noise. Connect these ground nodes at any place close to one of the ground pin of the IC.
A ceramic capacitor each, as close as possible from the VIN pin to GND and one from the VOUT pin to GND,
shown as C1 and C4 in the layout proposal are used to suppress high frequency noise. The case size should be0603 or smaller for good high frequency performance. Additional 0805 size input and output capacitors are used
to get the required capacitance on the input and output depending on the supply voltage range and the output
voltage.
The feedback divider should be placed as close as possible to the feedback pin of the IC. To lay out the control
ground, short traces are recommended as well, separation from the power ground traces. This avoids groundshift problems, which can occur due to superimposition of power ground current and control ground current.
In case any of the digital inputs EN, VSEL or PS/SYNC need to be tied to the input supply voltage VIN, a 10k
resistor must be used in series. One common resistor for all digital inputs that are tied to VIN is sufficient.

11.2 Layout Example

L1
GND

GND

COUT

CIN
C1

C4

VOUT

FB2
FB

R3

GND

PG

VAUX

EN
VSEL

PS/S

VIN

L2

L1

PGND

VIN

VOUT

R1
R2
CVAUX
Figure 49. EVM Layout

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12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOTCONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHERALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 8. Related LinksPARTS

PRODUCT FOLDERSAMPLE & BUY

TECHNICALDOCUMENTS

TOOLS &SOFTWARE

SUPPORT &COMMUNITY

TPS63070

Click here

Click here

Click here

Click here

Click here

TPS630701

Click here

Click here

Click here

Click here

Click here

12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that haschanged. For change details, review the revision history included in any revised document.

12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms ofUse.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools andcontact information for technical support.

12.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.

12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

30

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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and revision ofthis document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OPTION ADDENDUM

www.ti.com

8-Oct-2016

PACKAGING INFORMATION
Orderable Device

Status(1)

Package Type Package Pins Package
Drawing
Qty

Eco Plan

Lead/Ball Finish

MSL Peak Temp

(2)

(6)

(3)

Op Temp (°C)

Device Marking(4/5)

TPS630701RNMR

ACTIVE

VQFN-HR

RNM

15

3000

Green (RoHS& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

0701

TPS630701RNMTACTIVE

VQFN-HR

RNM

15

250

Green (RoHS& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

0701

TPS63070RNMR

ACTIVE

VQFN-HR

RNM

15

3000

Green (RoHS& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

3070

TPS63070RNMTACTIVE

VQFN-HR

RNM

15

250

Green (RoHS& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

3070

(1)

The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement thatlead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weightin homogeneous material)(3)

MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.
(6)

Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Addendum-Page 1

SamplesPACKAGE OPTION ADDENDUM

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8-Oct-2016

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION
www.ti.com

8-Oct-2016

TAPE AND REEL INFORMATION*All dimensions are nominal

DevicePackage Package Pins
Type Drawing

SPQ

Reel
Reel
A0
Diameter Width (mm)(mm) W1 (mm)

B0
(mm)

K0
(mm)

P1
(mm)

W
Pin1
(mm) Quadrant

TPS630701RNMR

VQFNHR

RNM

15

3000

330.0

12.4

2.8

3.3

1.2

8.0

12.0

Q1

TPS630701RNMTVQFNHR

RNM

15

250

180.0

12.4

2.8

3.3

1.2

8.0

12.0

Q1

TPS63070RNMRVQFNHR

RNM

15

3000

330.0

12.4

2.8

3.3

1.2

8.0

12.0

Q1

TPS63070RNMTVQFNHR

RNM

15

250

180.0

12.4

2.8

3.3

1.2

8.0

12.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION
www.ti.com

8-Oct-2016*All dimensions are nominal

DevicePackage Type

Package Drawing

Pins

SPQ

Length (mm)Width (mm)Height (mm)TPS630701RNMRVQFN-HR

RNM

15

3000

367.0

367.0

35.0

TPS630701RNMTVQFN-HR

RNM

15

250

210.0

185.0

35.0

TPS63070RNMR

VQFN-HR

RNM

15

3000

367.0

367.0

35.0

TPS63070RNMTVQFN-HR

RNM

15

250

210.0

185.0

35.0

Pack Materials-Page 2

PACKAGE OUTLINE

RNM0015A

VQFN - 1 mm max height
SCALE 4.000

PLASTIC QUAD FLATPACK - NO LEAD

2.6
2.4

B

A

PIN 1 INDEX AREA
3.1
2.9

1 MAX

C
SEATING PLANE

0.05
0.00

0.08 CPKG
2X 0.775

2X 0.725(0.2) TYP

2X 0.55

8

7

0.5 TYP

1.6
1.4

4

2X (0.25)

9
SYMM

1.5

1

11
2X

1

8X

0.5
0.3

15

13

1.25
1.05

12

2X

0.3
15X
0.2
0.1
0.05

C B
C

0.5
0.3

A
4222000/A 07/2015

NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.

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EXAMPLE BOARD LAYOUT

RNM0015A

VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

2X (0.75)
2X (0.725)
15

2X (0.525)

14

13

4X (0.6)

12

8X (0.6)
8X (0.25)
2X (1.35)

1

11
2X
(0.5)

SYMM

(2.8)
9

5X (0.5)
4

3X(0.25)(1.7)(R0.05) TYP

2X (0.25)

8

7

6

5

4X (0.25)(0.6)(1.15)

2X (0.775)
PKG

LAND PATTERN EXAMPLESCALE:20X

METAL

SOLDER MASKOPENINGSOLDER MASKOPENINGMETAL UNDERSOLDER MASK

0.05 MIN
ALL AROUND

0.05 MAXALL AROUNDSOLDER MASKDEFINEDPADS 7-13

NON SOLDER MASKDEFINEDPADS 1-6, 14 & 15

SOLDER MASK DETAILS
4222000/A 07/2015

NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
4. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

RNM0015A

VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

2X (0.75)
2X (0.725)
15

2X (0.525)
13

14

12

4X (0.6)

8X (0.6)
14X (0.25)
1

SOLDER MASKEDGE,TYP(1.06)

3X
EXPOSED
METAL

11
2X
EXPOSED
METAL

2X (0.72)
SYMM

10

(0.5)
TYP
5X (0.5)

(2.8)

9
4X
(0.575)(0.14)

4(R0.05) TYP

2X (0.25)

6

5

7

METAL UNDERSOLDER MASK
TYP

8

2X (0.388)

4X (0.25)(1.15)

2X (1.163)
PKG

SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
FOR EXPOSED PADS 9-11
85% PRINTED SOLDER COVERAGE BY AREASCALE:30X
4222000/A 07/2015

NOTES: (continued)
5. For alternate stencil design recommendations, see IPC-7525 or board assembly site preference.

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