AN50005

Paralleling power MOSFETs in high power applications
Rev. 1.1 — 13 September 2021

application note

Document information
Information

Content

Keywords

MOSFETs, paralleling, parameter spread, simulation

Abstract

This application note examines how current sharing imbalances between paralleled MOSFETs
are affected by various parameters. Guidelines are given on taking these into account in designs.
Realistic descriptions are provided to help designers to develop reliable and cost effective highpower solutions.

AN50005

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Paralleling power MOSFETs in high power applications

1. Introduction
In today’s automotive and power industries, higher power requirements are leading to moredesigns that require lower RDSon. Sometimes this is not achievable with a single packaged
MOSFET and the design will need to make use of two or more devices in parallel. Higher power
applications could also require the use of high performance substrates like heavy copper PCB, IMS(Insulated Metal Substrate) or DBC (Direct Bonded Copper) and even bare dies. By paralleling, thetotal current and thus dissipation is shared between each device. However, this is not as simple asapplying Kirchhoff’s current law: MOSFETs are not identical and thus they don’t share equally.
This application note describes how sharing imbalances between paralleled MOSFETs form as wellas guidelines and tools to take them into account. The final goal is to provide a set of best practices
that can help to design circuits with standard paralleled MOSFETs.

2. Applications
Applications that require paralleled MOSFETs can be categorized into two main groups dependingon the operation of the MOSFET: switch-mode and load switch.
The switch-mode types include motor drive applications, such as belt starter generators andsuperchargers, braking regeneration systems and switched mode power converters, such as
regulators (DC/DC) and other types of inverters (DC/AC). Here the half-bridge represents thefundamental cell block that all the major circuit topologies are based upon. The MOSFETs are
generally required to switch ON and OFF at a constant rate that can vary widely depending on theapplication, and are driven by a rectangular pulse with varying duty cycle (PWM). This is done with
the intent of modulating the output power of the system to the load.
Load switching mainly refers to applications where MOSFETs are used in series with the battery
such as in activation, safety switches and e-fuses, one example being battery isolation switches.
The MOSFETs are required to switch ON once and will remain fully ON until the system is switched
OFF. They might be swiftly switched OFF only in case some type of failure has been detected,
for example in case of short circuit. Additionally, these switches may come in a back-to-backconfiguration in order to offer an additional reverse polarity protection.
This application note focuses on switch-mode applications and the half-bridge configuration.

3. Key specifications
The most important figure to monitor is the MOSFET junction temperature. This is a function of
the power dissipated in each device which ideally should be uniform for all paralleled MOSFETs.
Since P = V × I and the same voltage is applied across all the paralleled MOSFETs, it is clearthat for ideal operation the current should be shared equally by each MOSFET and this is thesimplest metric to quantify how well the MOSFETs perform. However, an equally valid approachis to consider the dissipated energy (or power), as done throughout the majority of this application
note.
Current sharing in paralleled MOSFETs is mainly affected by the part to part variation of three
data sheet parameters: RDSon, QG(tot), and VGS(th). This will be described further in the appropriate
sections.
During the design phase, it is important to understand how to predict the worst case scenario
in part to part variation in order to produce a reliable design. As with many other aspects ofelectronics, the designer will eventually decide how much of a headroom to adopt against the
aforementioned worst case, maybe trading off some of the design robustness for improved
performance. As better said in “The Art of Electronics”:"This example illustrates a frequent designer’s quandary, namely a choice between aconservative circuit that meets the strict worst-case design criterion, and is therefore
guaranteed to work, and a better-performing circuit design that does not meet worst-case
specifications, but is overwhelmingly likely to function without problems. There are times when
you will find yourself choosing the latter, ignoring the little voice whispering into your ear." [1]AN50005

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Simulation setup
Disclaimer: this application note proposes the alteration of SPICE models. It is the user’s
responsibility to verify the model conformity to the data sheet, after any modification has
been implemented. This can be done by following the guidelines described in the appendix.
The circuit used in the application note is composed of 3 MOSFETs in parallel both at the high andlow side driving an inductive load, as shown in Fig. 1. The switching frequency is set at 20 kHz,duty cycle at 50 % and maximum VGS is 15 V. Each MOSFET is conducting a current of 50 A,
which is set by the constant current source of 150 A used in series with the load inductor. The
SPICE simulation contains also three 0 V generators, one in each low side MOSFET source path,
which are used to measure the low side drain current in order to calculate the dissipated energy
and power. BUK7S1R0-40H is used throughout this document, unless stated otherwise. As shownin Fig. 1, parasitic inductance linked to the layout has been added to the simulation. There is nodifference in terms of parasitics between the three branches (each branch corresponds to a single
MOSFET and the path connecting it to the others in parallel through inlet and outlet: VSUPPLY andphase for the high side, phase and GND for the low side).
This is an ideal scenario but achievable in practice within a reasonable margin. In this case any
imbalance will only be determined by the intrinsic differences between the MOSFETs themselves.
The importance of layout and influence of parasitics is discussed further in the corresponding
chapter.
It is worth noting that the guidelines and observations made from now on do not depend on thebattery voltage or other specifications, so they can be applied to a wide range of scenarios.
L1

Vp

L2

L3

L4

LB
Rsupply

Rgdrv1

Rg4

12 Ω

3.9 Ω
Rg5

CB
BH

Vsupply

Pdiss1

V=(V(Vd1)-V(Vs1))*I(VM1)

R1
1 kΩ

Rg6

∫

V= Pdiss1*dt

R4
1 kΩ
BL

Pdiss2

Ediss2B2B5

V=(V(Vd2)-V(Vs2))*I(VM2)

R2
1 kΩ

Pdiss3∫

V= Pdiss2*dt

V=(V(Vd3)-V(Vs3))*I(VM3)

R3
1 kΩ

B6

∫

V= Pdiss3*dt

Rg1

12 Ω

3.9 Ω

150 A

Rg2

L14

L8

L9

L10

L11

L12

L13

Vd1
Vs1

M1
BUK7S1R0-40H

Vd2
Vs2

M2
BUK7S1R0-40H

Vd3
Vs3

Lload
4 µH

M3
BUK7S1R0-40H

L15

3.9 Ω
Rg3
3.9 Ω

Ediss3

B3

Rgdrv2

V=V(VgsLS)
R5
1 kΩ

Iload

L7

3.9 Ω

B4

M6
BUK7S1R0-40H

L6

Ediss1

B1

M5
BUK7S1R0-40H

3.9 Ω

V=V(VgsHS)

RB

M4
BUK7S1R0-40H

L5

L16
L17

R6
1 kΩ

L18

L19

VM1

VM2

VM3

0V

0V

0V
aaa-033634

Fig. 1.

SPICE simulation circuit: half-bridge

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4. MOSFET dissipation and parameters' influence on current sharing
By understanding how MOSFET dissipation works and highlighting which are the main parameters
affecting it, it is possible to steer the worst case analysis towards a less burdensome but stillrealistic evaluation.
Power dissipation in a MOSFET employed in a half bridge is caused by two processes: conduction
and switching. Fig. 2 shows the current flowing through the paralleled MOSFETs in case of ideal
devices and the dissipated energy.

ID
(A)

55

125

ID
M1, M2, M3

45

E dissM1, M2, M3

3575

E COND

25

50

15

25

5

0

-5

Fig. 2.

E diss100 (µJ)

E SW(on)0

10

E SW(off)
20

30

40

time (µs)

50-25aaa-033643

MOSFETs drain current (ID) and energy dissipation (Ediss) - ideal case: equal MOSFETs. The turn-ON,
conduction and turn-OFF phases are indicated
The average power dissipated over a cycle can be found in a simulation environment or calculated,by taking into account each contribution separately. There is no hard separation between switching
and conduction losses. However, in a simulation environment, the dissipated power can help in
detecting this separation. Fig. 3 shows how the turn-ON phase has been found: the first point is set
at around 9.9 µs where the power is 0 W, the second point is set at 10.4 µs where the dissipatedpower is almost constant at around 1.8 W (dissipated power during conduction - Pcond). While thedrain current (ID) flowing through MOSFET M1 is shown in Fig. 3, the drain-to-source voltage (VDS)
across it rises before the current falls, hence the valid loss recorded here. Moreover, the increasein dissipated power starting at 10 μs and lasting around 100 ns is due to the gate charge required
to turn-ON the device.

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Paralleling power MOSFETs in high power applications
P

ID
(A)

55

I D M145
E diss M1

E SW(on)35
25
P diss M1

15
P

5
-5

Fig. 3.

COND

9.6

10

10.4

10.8

time (µs)

diss

E

diss

(W)
110

(µJ)
11

90

9

70

7

50

5

30

3

10

1

-10
11.2

-1
aaa-033730

MOSFETs drain current (ID), energy dissipation (Ediss) and power dissipation (Pdiss)- ideal case: equal MOSFETs. The turn-ON phase is indicatedFig. 4 shows how the turn-OFF phase has been found: the first point is set at 36.2 µs where thepower is 0 W, the second point is set at around 35.2 µs where the dissipated power starts toincrease from 1.8 W.
P
55
ID(A) 45E SW(OFF)25

E diss M1

15

P diss M1
P

5

COND

-5
34.6

Fig. 4.

E

diss(W) (µJ)
1100 120I D M1

35

diss

35

35.4

35.8

36.2

time (µs)

900

100

700

80

500

60

300

40

100

20

-100
36.6

-20

aaa-033731

MOSFETs drain current (ID), energy dissipation (Ediss) and power dissipation (Pdiss)- ideal case: equal MOSFETs. The turn-OFF phase is indicatedEquation 1 expresses the power dissipation in the MOSFET, while equations 2 and 3 show theindividual contributions from switching and conduction.

Pavg(tot) = Psw + Pcond
Psw = (E sw(ON) + E sw(OFF) )Pcond = E cond

f sw

(1)

f sw

(2)
(3)

Where Esw(ON) and Esw(OFF) are the energy dissipation during turn-ON and turn-OFF, Econd is
the energy dissipation during a single conduction phase and fsw the switching frequency. In thiscase, the total average power dissipated across each MOSFET over one cycle is around 2.1 W at
20 kHz.

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Paralleling power MOSFETs in high power applications
Table 1 shows the energy calculated during switching (divided into ON and OFF) and conduction.
The degree of sharing of each MOSFET can be defined in several ways. Here it is defined asratio between the energy dissipated in one MOSFET and the total energy dissipated in all of theparalleled devices, by using equation 4.

Total Energy Sharing =(ESW(ON) + ESW(OFF) + E SW(COND) ( (Mx)
100
n FET
Σ i =1 (ESW(ON) + ESW(OFF) + E SW(COND) ( (Mi)(4)

In this case, switching (Esw(ON) + Esw(OFF)) accounts for around 55 % of the overall dissipation.
However the switching:conduction dissipation ratio will depend on the switching frequency: a low
frequency will lead to conduction losses dominating whereas switching losses will dominate at highfrequency. Therefore, in order to simplify the evaluation, one might consider to take into accountonly parameters influencing the most important contribution.
With the MOSFET fully ON the only source of dissipation is given by its drain-to-source on state
resistance (RDSon). On the other hand, switching depends on threshold voltage (VGS(th)) and input
charge (QG(tot)).
Table 1. Summary - Ideal case: equal MOSFETs
DeviceESW(ON) [µJ]
ESW(OFF) [µJ]

ECOND [µJ]

Total Sharing

M1

5.1

52.8

46.1

33 %

M2

5.1

52.8

46.1

33 %

M3

5.1

52.8

46.1

33 %

5. Influence of parameter spread on current sharing performance
As previously mentioned, manufacturing spreads in data sheet parameters have a big impact
on current sharing. Spread refers to the difference between maximum and minimum of a certain
parameter. These spreads are unavoidable and caused by both intra- and inter- wafer variation
during the silicon die fabrication. Every MOSFET produced by any manufacturer will carry these
spreads. Nexperia’s power MOSFET fabrication processes are optimised to keep spreads as tightas possible in order to achieve good performance and reliability.
It is important to understand how each of the aforementioned parameters affect the current sharing
among paralleled devices, before describing techniques and guidelines to counteract them. Thiscan be done in a simulation environment. In the following section each parameter will be set atthe outmost values of its data sheet spread. In addition to the simulations presented here, theAppendix contains experimental measurement data from an identical setup using MOSFETs withsimilar parameter spreads.
It is worth noting that spreads are measured and thus guaranteed only at certain electricalconditions. For instance, the threshold voltage spread is specified between 1 µA and 100 mA
and at VDS of 5 V, as shown in Fig. 5. However, this same behaviour is not guaranteed at higher
currents.

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Paralleling power MOSFETs in high power applications
aaa-018138

10-1
ID
(A)
10-2
Min

10-3

Typ

Max

10-4

10-5

10-6

Fig. 5.

0

1

2

3

4
VGS (V)5BUK7S1R0-40H sub-threshold drain current as a function of gate-source voltage

5.1. Static operation (DC)5.1.1. Drain-source on-state resistance – RDSon
Table 2. BUK7S1R0-40H data sheet characteristics: RDSon
SymbolParameter
Conditions
RDSon

drain-source on-state
resistance

Min

Typ

Max

Unit

VGS = 10 V; ID = 25 A; Tj = 25 °C

0.62

0.88

1

mΩ

VGS = 10 V; ID = 25 A; Tj = 105 °C

0.87

1.3

1.6

mΩ

VGS = 10 V; ID = 25 A; Tj = 125 °C

0.97

1.4

1.75

mΩ

VGS = 10 V; ID = 25 A; Tj = 175 °C

1.2

1.8

2.2

mΩ

The total spread, as per data sheet, is ∆RDSon = 0.38 mΩ or ∆RDSon,rel = ± 21.6 % (relative
percentage with respect to the nominal value). The SPICE model of the device has been adjusted
to account for the RDSon spread. This is done by changing the value of the RD parameter, located in
the “Drain, gate and source resistances” section. The correct values can be found by sweeping theparameter after declaring a variable in the form of {variable}.
Table 3. SPICE model mod for RDSon spread
SPICE parameter – RDRDSon [mΩ]AN50005

application note

316.247u

0.62

576.260u

0.88

695.949u

1.00

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Rev. 1.1 — 13 September 2021

Conditions
VGS = 10 V, ID = 25 A,
Tj = 25 °C© Nexperia B.V. 2021. All rights reserved

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Paralleling power MOSFETs in high power applications
aaa-033644

70
ID
(A)

M1

50

M2
M3

30

10

-10

Fig. 6.

0

10

20

30

40

50

time (µs)

MOSFETs drain current (ID) - effects of RDSon spread

The simulation setup and results are summarized in Table 4. The MOSFET having lower RDSon(M1) will need to handle more energy, vice versa for M3. Both sharing during conduction andswitching are impacted. M1 is now dissipating 2.5 W, around 20% more than the ideal case (2.1 W)
while M3 is dissipating 1.7 W.
These results are valid only for the first cycles of operation, after which the temperaturedependency of the RDSon partly balance out the sharing, more information is provided in thecorresponding section on temperature dependency.
Table 4. Summary - Effects of RDSon spread
DeviceRDSon [mΩ] ESW(ON) [µJ]
ESW(OFF)[µJ]

EnergySharing
Switching

ECOND [µJ]

EnergySharing
Conduction

M1

0.62

5.0

65.9

40.7 %

52.9

39.4 %

M2

0.88

5.1

48.8

30.9 %

42.5

31.6 %

M3

1

5.1

44.3

28.4 %

38.9

29.0 %

5.2. Dynamic operation
5.2.1. Total input charge – QG(tot)Table 5 gives the typical and maximum values for gate charge parameters QG(tot), QGS and QGD;
refer to Fig. 7 for definitions of these parameters.
Table 5. BUK7S1R0-40H data sheet characteristics: gate charge
SymbolParameter
Conditions

Min

Typ

Max

Unit

QG(tot)total gate charge

-

98

137

nC

QGS

gate-source charge

-

27

40

nC

QGD

gate-drain charge

-

17

34

nC

AN50005

application note

ID = 25 A; VDS = 32 V; VGS = 10 V

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VDS
ID

VGS(pl)VGS(th)
VGS
QGS2
QGS1
QGS

QGD
QG(tot)Fig. 7.

003aaa508

Gate charge waveform definitions

The total spread, as per data sheet, is ∆QG(tot) = 39 nC or ∆QG(tot),rel = +40 %. In order to introduce
this spread in the SPICE model, it is necessary to evaluate separately the contribution of QGS and
QGD through CGS and CGD.
By doing so, the MOSFET will end up showing slightly higher maximum QG(tot), since it is muchharder to control the slope of the VGS curve after the plateau voltage (refer to Fig. 7). Moreover, thetwo capacitances will not necessarily behave in the same way: being mostly independent, it could
happen that a MOSFET shows, for instance, higher CGD and lower CGS, or any other combination
in between. To facilitate the evaluation, the two have been considered both at their typical andmaximum values only.
The SPICE model of the device has been adjusted to account for the CGD and CGS spread. Thisis done by changing the value of CGS and multiplying the CGD value by a specific coefficient
CGD_scale. The former is defined as a constant value while CGD as a voltage dependent value
at the line “G11 3 2 VALUE …” in the corresponding section. The correct values can be found bysweeping the parameter after declaring a variable in the form of {variable}.
Table 6. SPICE model mod for QG(tot) spread
SPICE parameter

AN50005

application note

ConditionsCGS

QGS [nC]

6.1n27.1489.24n

40.024

CGD_scale

QGD [nC]

0.84

17.0081.65

34.211

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VDS = 32 V;
ID = 25 A; VGS = 10 V

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Paralleling power MOSFETs in high power applications

ID

aaa-033646

70

M1

(A)

M2

50

M3
30

10

-10

Fig. 8.

0

10

20

30

40

time (µs)

50

MOSFETs drain current (ID) - effects of QG(tot) spread

The simulation setup and results are summarized in Table 7. The value of QG(tot) has been
calculated as the sum of the respective QGS and QGD (from Table 6). At turn-ON the device withlower input capacitance (M1) will switch ON first thus handling majority of the current. On theother hand, at turn-OFF the MOSFET with higher input capacitance (M3) will switch OFF last now
handling most of the current. The sharing during switching is the most impacted, while conduction
has changed only marginally. M3 is now dissipating 2.8 W (0.7 W more than the ideal case) while
M1 is dissipating 1.9 W.
Table 7. Summary - Effects of QG(tot) spread
DeviceQG(tot) [nC] ESW(ON) [µJ]
ESW(OFF)[µJ]

EnergySharing
Switching

ECOND [µJ]

EnergySharing
Conduction

M1

94.4

9.4

35.7

21.4 %

49.9

35.8 %

M2

125.7

6.9

60.8

31.9 %

46.1

33.2 %

M3

158.0

4.7

94.4

46.7 %

43.2

31.0 %

5.2.2. Gate-source threshold voltage – VGS(th)Table 8. BUK7S1R0-40H data sheet characteristics: VGS(th)SymbolParameter
Conditions
VGS(th)gate-source thresholdvoltage

Min

Typ

Max

Unit

ID = 1 mA; VDS=VGS; Tj = 25 °C

2.4

3

3.6

V

ID = 1 mA; VDS=VGS; Tj = 175 °C

1

-

-

V

ID = 1 mA; VDS=VGS; Tj = -55 °C

-

-

4.3

V

The total spread, as per data sheet, is ∆VGS(th) = 1.2 V or ∆VGS(th),rel = ± 20 %. The SPICE modelof the device has been adjusted to account for the VGS(th) spread. This is done by changing thevalue of the Vto parameter located in the “.MODEL MINT NMOS” section. The correct values canbe found by sweeping the parameter after declaring a variable in the form of {variable}.
Table 9. SPICE model mod for VGS(th) spread
SPICE parameter Vto
VGS(th) [V]

AN50005

application note

3.243

2.400

3.843

3.000

4.443

3.600

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Conditions
VDS = 12 V, ID = 1 mA

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Paralleling power MOSFETs in high power applications
The MOSFETs drain current is shown in Fig. 9. After turn-ON, the loop inductance present in thecircuit causes the current to stabilise only after 10 µs, further details in the Layout-dependent
parasitics section.

ID(A)

aaa-033645

110
90
70

M1
M2

50

M3

30
10
-10

Fig. 9.

0

10

20

30

40

time (µs)

50

MOSFETs drain current (ID) - effects of VGS(th) spread

The simulation setup and results are summarized in Table 10. The MOSFET having lower VGS(th)will need to handle more energy overall. At turn-ON M1 will switch ON first thus handling majorityof the current. Moreover, at turn-OFF the same MOSFET will switch OFF last, again, handling
most of the current. The sharing during switching is the most impacted, with one MOSFET (M3)participating only minimally in the process, while conduction has changed only marginally. M1 isnow dissipating 4.7 W (2.6 W more than the ideal case) while M3 only 1 W.
Table 10. Summary - Effects of VGS(th) spread
DeviceVGS(th) [V] ESW(ON) [µJ]
ESW(OFF)[µJ]

EnergySharing
Switching

ECOND [µJ]

EnergySharing
Conduction

M1

2.4

9.3

172.2

74.4 %

52.7

37.8 %

M2

3

5.1

48.7

22.1 %

45.7

32.8 %

M3

3.6

2.2

6.4

3.5 %

40.8

29.4 %

In conclusion, the MOSFET having lower VGS(th) will need to handle more energy both during
turn-ON and turn-OFF, while with the capacitance spread the switching energy will be balanced
between at least two devices. These results are valid only for the first cycles of operation, due
to the temperature dependency of the VGS(th). More information is provided in the corresponding
section on temperature dependency. Refer to Section 7.1 for an explanation of the shape of thecurrent between switching and conduction, as shown in Fig. 6, Fig. 8 and Fig. 9.

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Paralleling power MOSFETs in high power applications

5.3. Paralleled MOSFETs and temperature dependency
Each MOSFET can be thought as a system composed of an electrical subsystem in a feedback
loop with a thermal subsystem, as shown in Fig. 10.

ELECTRICALSUB-SYSTEMTHERMAL
SUB-SYSTEM

aaa-033729

Fig. 10. MOSFET electrical-thermal interaction
Power MOSFETs are often considered to be immune to thermal runaway due to the RDSon
temperature coefficient. However, this is only true for MOSFETs that are fully ON. When a
MOSFET is in the on-state, there are two competing effects that determine how its current behaves
with increasing temperature. As the temperature rises, VGS(th) falls, thereby increasing the current.
On the other hand, RDSon increases with increasing temperature, thereby reducing the current. The
resistance increase dominates at higher gate-source voltages (VGS), while the threshold-voltage
drop dominates at low VGS. Consequently, for a given VDS, there is a critical VGS below which there
is a positive feedback regime and above which there is a negative feedback and thermal stability.
This critical point is known as the Zero Temperature Coefficient (ZTC) point, Fig. 11.
aaa-032641

350

ID
(A)

280

210
ZTC
140

70

0

175°C

25°C
Tj = -55°C

0

1

2

3

4

5

6
7
VGS (V)

8

Fig. 11. BUK7S2R5-40H data sheet graph: transfer characteristic ZTC point
The interaction between thermal and electrical subsystems can be simulated using Nexperia
1

advanced models which make two additional thermal pins accessible: junction and case/mounting
base. Within these models, parameters of interest for the paralleling are modelled with increased
accuracy by including their temperature dependency. A circuit modelling the overall thermal system
MOSFET-PCB-ambient to the drain tab must be connected to the mounting base pin of the model.

1 The advanced models will be released later in 2021

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Paralleling power MOSFETs in high power applications

5.3.1. Temperature dependency during static operation (DC)In a parallel configuration, RDSon has the advantage of improving the sharing due to its positive
temperature coefficient (PTC), Fig. 12. As one MOSFET conducts more current and dissipates
more power, RDSon increases and the conduction losses change improving the sharing.

aaaa-026897

2.4
2
1.6
1.2
0.8
0.4
0
-60

a=

-30

0

30

60

90

120 150
Tj (°C)180

RDSon
RDSon(25°C)

Fig. 12. BUK7S2R5-40H data sheet graph: normalized on-state resistance as a function ofjunction temperature
Ideally this phenomenon is maximized when the thermal coupling between paralleled MOSFETs isless effective, as each MOSFET is less influenced by the others around it. However, this leads tohigher junction temperatures. This phenomenon can be described using the steady state simulation
shown in Fig. 13. This time, to simplify the interaction, only two MOSFETs have been used inparallel. Additionally, a second circuit is used to model the thermal coupling between the two
MOSFETs and their connection with the PCB.
The SPICE model of the devices have been adjusted in order for M1 to show lower RDSon(0.62 mΩ) than M2 (1 mΩ).

Tc1

Rgdrv

Rg1

12

3.9

Vgs

Rg2

15 V

3.9

M1

Tj

Tj1

M2

Tc1
Tcase
BUK7S1R0-40H_RDSonMIN

Tj

Tj2

Rload
119.3 mTc2
Tcase
BUK7S1R0-40H_RDSonMAX

Tc2

Rth(M1-M2)

Rpcb_M1
40

Rpcb_M2
40

Vsupply
12 V

Tamb
25 V
aaa-033635

Fig. 13. SPICE simulation circuit: thermal coupling

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Paralleling power MOSFETs in high power applications
With reference to the graph in Fig. 14: the total current flowing through the devices is set at 100 A
so that the leftmost y-axis shows current and sharing in percentage at the same time. In this casecurrent has been used to calculate the degree of sharing between the MOSFETs as this example
considers purely steady state conduction. As the thermal coupling between the two MOSFETs
worsens (Rth(M1-M2) increases) the junction temperature of M1 increases while the current
sharing in steady state improves (converges more towards 50 %). Moreover, even in case of highdecoupling the RDSon PTC will only improve the sharing by a maximum of around 2 % for each
MOSFET.
Therefore good thermal coupling between paralleled MOSFETs is to be preferred as it allows forlower junction temperatures. More details on this are provided in the PCB Layout influence: Circuit
layout section.

Current
sharing
(%)
ID

(A)

M1 current share
M1 T j100

aaa-033648

M2 current share
M2 T j200
Tj (°C)

80

180

60

160

40

140

20

120

0

0.1

1

10

100

100
1,000
R th(M1-M2) (K/W)

Fig. 14. Thermal coupling influence on sharing: RDSon(M1) = 0.62 mΩ and
RDSon(M2) = 1 mΩ

5.3.2. Temperature dependency during dynamic operation
Threshold voltage is characterized by a negative temperature coefficient (NTC): it decreases as thejunction temperature increases. This behaviour is more detrimental in case of paralleled MOSFETs.
For instance, a device with an initial higher junction temperature will exhibit an even lower VGS(th)which increases the current flowing through the MOSFET and thus the power that it dissipates.
As in the static case, good thermal coupling helps to keep the MOSFETs at similar temperatures.
Other guidelines could be adopted to mitigate temperature gradient across paralleled MOSFETs,
for more information refer to PCB Layout influence: Circuit layout.
Fig. 15 shows how the VGS(th) spread is almost constant with respect to the junction temperature,
however this behaviour is guaranteed only at a drain current of 1 mA. For a temperature differenceof 20 °C (from 25 to 45 °C) VGSth reduces by about 0.2 V.

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Paralleling power MOSFETs in high power applications

VGS(th)(V)

aaa-018139

5

4
Max
3

Typ

2
Min
1

0
-60

-30

0

30

60

90

120 150
Tj (°C)180

Fig. 15. BUK7S1R0-40H data sheet graph: gate-source threshold voltage as a function ofjunction temperature
Finally, unlike RDSon and VGS(th), input charge is shown to only slightly vary with temperature.

5.4. Data sheet and batch spreads
If considering multiple MOSFETs in parallel, data sheet spreads may be too conservative. The
design would certainly be reliable but the improved robustness to a wider worst case scenario
could end up being more expensive. In this case then, the designer would prefer to evaluate aless stringent worst case scenario that, even if not guaranteed like the data sheet, can still beconsidered realistic. This is done by looking at batch spreads.
A batch refers to a group of devices that go through the whole manufacturing process at thesame time. The number of dies in a batch can vary from a few thousands to over a few millions,depending on the size of the dies themselves. Within a set of paralleled MOSFETs, it is preferable
to choose parts coming from the same reel in order to increase the possibility of using devices fromthe same batch. Furthermore, using MOSFETs with identical batch codes, which can be found on
the package under the marking code, could be used to further narrow down the selection during
PCB assembly.
Spreads within a batch are observed to be much lower than the corresponding data sheet ones.
The same can be said even with those among different batches. Fig. 16 shows the spread of
VGS(th) for the BUK7S1R5-40H for 10 different batches. In this case the 6-sigma spread is observed
to be 0.42 V, from 2.86 V to 3.28 V. This value is calculated taking into account a small quantity ofoutliers (not shown in the plot of Fig. 16). Therefore, the observed worst case is given by a ΔVGS(th)= 0.42 V or ΔVGS(th),rel = ± 7 %, less than half of the guaranteed (data sheet) one.

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Paralleling power MOSFETs in high power applications
aaa-033732

4.6
V GS(th)
(V)

4.1

3.6

Data sheet max

3.1
2.6

2.1

Data sheet min

1.6
1

2

3

4

5

6

7

8

9

10
Batch

Fig. 16. VGS(th) batches spread for BUK7S1R5-40H
Fig. 17 shows the absolute value of the difference in VGS(th) (|∆VGS(th)|) between two consecutive
devices, within two different batches. In this case the 6-sigma spread is observed to be 0.25 V,
or ΔVGS(th),rel = ±4 %. Therefore, in case two consecutive MOSFETs coming from the same reelare used in parallel, the difference between their VGS(th) is observed to be even smaller than thatbetween multiple batches.
aaa-033949

0.3|∆V GS(th) |
(V)
0.2

0.1

0

Fig. 17. Absolute value of the difference in VGS(th) between two consecutive devices
Fig. 18 compares the MOSFETs drain current in case of data sheet and batch spread, Table 11
quotes the energy shared by each MOSFET. M1 is now dissipating a total of 2.8 W and M3 1.5 W.
Therefore, a difference of ±7 % in VGS(th) leads to a reduction of 1.9 W over a cycle of M1, reducing
the ratio between these two MOSFETs dissipation from almost 5:1 down to 2.5:1.

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Paralleling power MOSFETs in high power applications
ID(A)

aaa-033645

110

ID
(A)

90

aaa-033647

90
70
M1

70

M1

M3

M3
30

30

10

10
-10

M2

50

M2

50

0

10

20

30

40

time (µs)-1050a. data sheet spread

0

10

20

30

40

time (µs)

50b. batch spread

Fig. 18. MOSFETs drain current (ID) – data sheet and batch VGS(th) spread comparison
Table 11. Summary - Effects of VGS(th) batch spread
DeviceVGS(th) [V]
ESW [µJ]
EnergySharing
Switching
M1

ECOND [µJ]

EnergySharing
Conduction

2.79

97.0

51.3 %

48.7

35.6 %

M2

3

59.4

31.4 %

45.4

33.2 %

M3

3.21

32.6

17.2 %

42.7

31.2 %

6. Circuit optimisation
There are two main types of circuit modifications, each has a different impact on the current
sharing. These are: localized gate resistor and components in the MOSFETs source paths.

6.1. Localized gate resistor
The first type of circuit modification is also the most advantageous, it has no major drawbacks
and it is the simplest to implement. The modification involves splitting the gate resistor between
a localized one close to the gate of each MOSFET and a common resistor at the driver side, as
shown in Fig. 18 b. Doing so will counteract the spreads and improve the sharing, mainly duringswitching with little impact during conduction.
It is important to keep the localized resistance as low as possible to give maximum coupling
between the MOSFET gates, effectively allowing the input capacitances to be considered inparallel. A simple simulation can display this effect: two circuits modelling the driver and input
impedance of each MOSFET are used as comparison. Fig. 19 a. shows the control voltage at each
MOSFET gate, the voltage is slowed down in case of the MOSFET with higher Ciss, vice versa it isless filtered in case of lower capacitance.
By splitting the gate resistor the difference between the control voltages at each gate becomes
negligible (Fig. 19 b). With reference to the naming adopted in the SPICE circuits of Fig. 19, thegate resistor at the driver can be calculated as:

RG,drv = RG - RG,split
nFET
nFET

(5)

The value of RG,drv has been rounded to 12 Ω. A smaller RG,drv can be beneficial by reducing
the switching time where the unequal sharing occurs. In a similar manner, the smaller RG,split thebetter coupled the MOSFETs gate, but it is recommended not to go below 2-3 Ω. In general, a gate
resistor helps in dampening any oscillation in the gate-source loop that might compromise the EMC
performance of the system. Therefore, given a lower resistance of the gate resistor, it is importantto reduce as much as possible the loop inductance of the driver loop, for further information see
section: PCB layout influence.

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Paralleling power MOSFETs in high power applications
Rgdrv

Vg1

RG1
39 Ω

RG2
39 Ω

RG3
39 Ω

gate1

gate2

Ciss1
1 nF

Ciss2
2 nF

PULSE (0 15 0 1nF 1nF 1)

12 Ω

RGsplit1
3.9 Ω

RGsplit2
3.9 Ω

RGsplit3
3.9 Ω

gate3

gate1

gate2

gate3

Ciss3
3 nF

Ciss1
1 nF

Ciss2
2 nF

Ciss3
3 nF

Vg2

PULSE (0 15 0 1nF 1nF 1)

a. without gate resistor split

b. with gate resistor split

aaa-033636

Fig. 19. SPICE simulation circuit: gate resistor split comparison
aaa-033649

16
M1

V

GS

(V)

V

GS

(V)

M2

12

aaa-033650

16

12
M1

M3

M2

8

8

4

4

0

M3

0
0

10

20

30

40

time (µs)

500a. without gate resistor split

10

20

30

40

time (µs)

50b. with gate resistor split

Fig. 20. Gate-source voltage without and with gate resistor split
The great improvement of the resistor split can be easily appreciated by simulating the same halfbridge circuit using two different gate resistors setups and introducing some spread. This time an
arbitrary combination of all the spreads has been used. Fig. 21 shows the MOSFETs drain current
without gate resistor split, while Fig. 22 shows the MOSFETs drain current with gate resistor split.
aaa-033651

160
ID

(A)

M3

140
120
100

M1

80
60
M2

40
20
0
-20

0

10

20

30

40

time (µs)

50Fig. 21. MOSFETs drain current (ID) – without gate resistor split
The simulations setup and results are summarized in Table 12 and Table 13, while a final
comparison is given in Table 14. M3 is dissipating 8.2 W, M2 1.3 W and M1 2.0 W. At turn-ON
M1 is switching first, due to having both lower QG(tot) and VGS(th), thus handling the majority of thecurrent. On the other hand, at turn-OFF the MOSFET with higher input charge (M3) will switch lastand carry most of the current.

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Paralleling power MOSFETs in high power applications
Table 12. Summary - sharing without gate resistor split: RG = 39 Ω
DeviceRDSon
VGS(th) [V]QG(tot)ESW [µJ]
Energy ECOND [µJ] Energy
[mΩ]
[nC]
Sharing
Sharing
Switching
Conduction
M1

0.62

3.21

94.4

42.7

9.6 %

62.2

47.0 %

M2

1

3

125.7

29.0

6.5 %

35.2

26.6 %

M3

0.88

2.79

158.0

373.0

83.9 %

34.9

26.4 %

ID

aaa-033652

100

(A)

M3

80
M1

60
40

M2

20
0
-20

0

10

20

30

40

time (µs)

50Fig. 22. MOSFETs drain current (ID) – with gate resistor split
With the gate resistor split M3 is now dissipating 3.8 W, M2 2.0 W and M1 1.6 W. The
improvements are noticeable both at turn-ON, where the peaks are now almost identical, and turnOFF. During the latter the peak current through M3 has reduced from around 150 A down to almost
90 A. Sharing during conduction has improved as well, this is due to time it takes for the current toreach its conduction value following the turn-ON event. Overall, M3 is now dissipating 50 % lesspower.
Table 13. Summary - sharing with gate resistor split: RG,drv = 12 Ω and RG,split = 3.9 Ω
Device RDSon [mΩ] VGS(th) [V] QG(tot) [nC] ESW [µJ]
EnergyECOND
EnergySharing[µJ]
Sharing
Switching
Conduction
M1

0.62

3.21

94.4

30.0

12.4 %

52.3

39.6 %

M2

1

3

125.7

60.6

25.1 %

38.2

28.9 %

M3

0.88

2.79

158.0

150.5

62.4 %

41.4

31.5 %

Table 14. Summary – comparison of sharing with and without gate resistor split
DeviceTotal Energy Sharing

AN50005

application note

without gate resistor split

with gate resistor split

M1

18.1 %

22.1 %

M2

11.12 %

26.5 %

M3

70.7 %

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6.2. Components in the source path
Employing a resistor in series with each of the MOSFETs source path can lead to better sharing
during conduction. The main disadvantage is that of an additional source of power dissipation
which lowers the overall efficiency of the system and increases the burden on the cooling system.
Given the relatively high value of resistance needed to be effective, this solution will not be ideal in
all scenarios.
Certain designs might already include series resistors to monitor the current flowing through a half
bridge. However, the only way for them to be effective in case of paralleled MOSFETs is if they areplaced within the gate-source loop, as shown in Fig. 23. In case of current sensing, an additional
small resistor may be added to decouple each loop in order to reduce potential crosstalk between
each branch.
The resistor helps to counteract the spread of the RDSon, thus leading to better sharing duringconduction. Inductance located in the same place has a similar effect of slightly improving thesharing, this time during switching, by opposing quick changes in current (dI/dt) and thus lowering
the current peaks. On the other hand, conduction losses would increase slightly due to the larger
time constant of the current converging towards its conduction value (Itot / nFET).
Vp

L1

L2

L3

L4

LB
Rsupply

Rgdrv1

Rg4

12 Ω

3.9 Ω
Rg5

CB
BH

VsupplyRB

M5
BUK7S1R0-40H

M6
BUK7S1R0-40H

Iload
150 A

L6

3.9 Ω

V=V(VgsHS)

Rg6

L7

3.9 Ω

BL

M4
BUK7S1R0-40H

L5

Rgdrv2

Rg1

12 Ω

3.9 Ω

V=V(VgsLS)

Rg2

L14

L8

L9

L10

L11

L12

L13

Vd1
Vs1

M1
BUK7S1R0-40H

Vd2
Vs2

M2
BUK7S1R0-40H

Vd3
Vs3

Lload
4 µH

M3
BUK7S1R0-40H

L15

3.9 Ω
Rg3

L16

3.9 Ω
L17

L18

L19

Rx1

Rx2

Rx3

VM1

VM2

VM3

0V

0V

0V

aaa-033637

Fig. 23. SPICE simulation circuit: source resistors
The simulation setups and results are summarized in Table 15.

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Paralleling power MOSFETs in high power applications
ID(A)

aaa-033653

100
M3

80
M1

60
40

M2

20
0
-20

0

10

20

30

40

time (µs)

50Fig. 24. MOSFETs drain current (ID) – with a source resistor of 1 mΩ
Table 15. Summary – sharing with a source resistor of 1 mΩDeviceRDSon
VGS(th) [V]QG(tot)ESW [µJ]
Energy ECOND [µJ Energy
[mΩ]
[nC]
Sharing
Sharing
Switching
Conduction
M1

0.62

3.21

94.4

27.9

11.5 %

41.6

30.8 %

M2

1

3

125.7

66.5

27.4 %

47.3

35.1 %

M3

0.88

2.79

158.0

148.4

61.1 %

46.1

34.1 %The efficacy of the resistor on the current sharing depends on its value. If the aim is to balance
the current sharing, then the higher the resistance the better, as shown in Fig. 25. Naturally thedissipation will increase considerably with it. In order for it to be effective in counteracting the RDSon
spread it needs to be comparable with the actual RDSon of the MOSFET.
aaa-033654

70
ID

R S = 1 µΩ
R S = 250 mΩ
R S = 500 µΩ
R S = 1 mΩ

(A)
50

30

10

-10

0

10

20

30

40

time (µs)

50Fig. 25. MOSFETs drain current (ID) – effects of source resistor value

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Paralleling power MOSFETs in high power applications

7. PCB layout influence
Tight spreads and a good layout are two important factors when designing an application withparalleled MOSFETs. This chapter describes guidelines to achieve a good layout and how
parasitics influence the current sharing.
In a paralleled set of MOSFETs it is impossible to say beforehand where the device with lowest or
highest spreads will be placed. Therefore, it is important to lay out each branch in the same way,
failing to do so will result in the worsening of the worst case scenario.

7.1. Layout-dependent parasitics
In case of paralleled devices loop inductance and resistance in the path should be not only
minimised but also equalised for each branch.
Higher inductance slows down the current reaching its steady state value due to the higher
time constant of the circuit (τ = L/R), as shown in Fig. 26. The inductance decreases the peakcurrent slightly but increases the overall sharing unbalance. Moreover, both high and low sides will
experience larger voltage overshoots and oscillations in VDS (and VGS) due to resonance with thecapacitances in the circuit (Fig. 27), often exceeding the supply voltage. This also leads to higher
interference with nearby circuits and wiring.
In general, any rule that would be recommended for a single MOSFET can be applied here. For a
more in depth explanation of the switching behaviour of a half-bridge and EMC consideration refer
to “AN90011: Half-bridge MOSFET switching and its impact on EMC”[2]ID(A)

aaa-033647

90

ID

(A)

70

70

M1

M1

M2

50

50

M3

30

30

10

10

-10

aaa-033659

90

0

10

20

a. L11 = L12 = L13 = 1 nH

30

40

time (µs)

50

-10

M2

M3

0

10

20

30

40

time (µs)

50b. L11 = L12 = L13 = 4 nH

Fig. 26. MOSFETs drain current (ID) - effects of parasitic inductance

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Paralleling power MOSFETs in high power applications
aaa-033660

28
VDS

Lp_D = 4 nH

(V)20

Lp_D = 1 nH

12

4

-4
35.0

35.2

35.4

35.6

35.8

time (µs)

37.0

Fig. 27. Effects of higher parasitic inductance on low side VDS at turn-OFF
Differences between loop inductances lead to worse current sharing, as shown in Fig. 28.
ID(A)

aaa-033647

90

ID
(A)

70
M1
M2

50

70

M3
30

10

10

0

M1
M2

50

M3

30

-10

aaa-033662

90

10

20

30

40

a. L13 = 1 nH

time (µs)

50

-10

0

10

20

30

40

time (µs)

50b. L13 = 2 nH

(See circuit of Fig. 23)
Fig. 28. MOSFETs drain current (ID) - effects of parasitic inductance imbalance

7.2. Circuit layout
As in many other circumstances, the layout plays an important role in the final performance of anelectronic system, almost as much as the quality of the parts. In case of paralleled MOSFETs thelayout should be designed to provide: good thermal link between the devices, low and equal loop
inductance in the gate-source and source-drain loops and low and equal resistance between the
branches.
Good thermal coupling allows the devices to operate at similar lower temperatures. Furthermore,
the designer should aim at obtaining similar Rth(mb-amb) for each MOSFET. Multiple planes andthermal vias help in improving the heat exchange between devices and environment. Care should
be taken in the placement of the MOSFETs: for instance by avoiding placing a subset of the
MOSFETs near heat sinks, connectors or other components that may be keep them cooler thanthe other paralleled MOSFETs. For more information about this topic refer to “AN90003: LFPAKMOSFET thermal design guide” [3].
Low inductance in a loop can be achieved by reducing the area of the loop (thereby reducing theself-inductance) or by keeping the trace and its return path as close as possible to each other(thereby increasing the mutual inductance). Loop inductance in the gate-source loop can be
reduced by keeping the driver as close as possible to the MOSFETs and by running gate andsource traces parallel to each other, as shown in Fig. 29.

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Paralleling power MOSFETs in high power applications+ve supply

switch nodeaaa-033641

Fig. 29. Gate-source loop: possible layout
Inductance in the loop carrying the load current could be minimised, for instance, by employing
the design in Fig. 30. For further details refer to “AN90011: Half-bridge MOSFET switching and its
impact on EMC” [2].
+ve supply

ground plane(on another PCB layer)+ve supply

ground plane(on another PCB layer)

2.52 nH

2.07 nH

1.55 nH

4 mm

switch node

3.5 nH
4.04 nH

switch node

4.75 nH
1.55 nH

2.07 nH

D1
VDC
I/P

VDC
I/P

D1

4.04 nHC

3.5 nHC

2.52 nH

4.75 nH

S2

S2

aaa-031122

aaa-031121

Fig. 30. Half-bridge layout possibilities showing inductances
The placement of inlets and outlets plays another important role because it determines eachbranch parasitics. When using multiple devices in parallel, it could be helpful to use more than one
inlet and outlet. Using multiple smaller cables can be actually beneficial for other reasons too. The
positioning of these insertion points needs to be carefully planned. One possible way to facilitate

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Paralleling power MOSFETs in high power applications
this decision might be to use a CFD software and run a current density simulation. This type ofsimulation highlights the preferred path the current takes in a steady state condition (DC).
Fig. 31 shows the setup used for the simulations: 3 MOSFETs are placed in parallel both at highand low side. Each low side MOSFET is connected between phase (inlet), on the top layer, andground (outlet) on the bottom one (not shown in the picture), through a number of filled vias. Eachhigh side is instead connected between phase (outlet) and the positive supply (inlet) on the top
layer. A total current of 150 A is set to flow through the paralleled devices. Two simulations are
required, each with a single side active at a time.

aaa-033743

Fig. 31. CFD simulation setup
The results of the current density simulation for the low side and high side are shown in Fig. 32,
Fig. 33 and Fig. 34. Higher current density is shown in red, while low or null in blue. For instancethe high side simulation (Fig. 34) highlights a spot around M4 and inlet VBUS1 where current
density is higher, due to the position of the latter. By integrating the current density over the entire
surface of the die it is possible to calculate the sharing in steady state of the layout (between
30-40% in this particular case). These simulations have been obtained using scSTREAM.

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aaa-033747

Fig. 32. CFD current density simulation: Low side MOSFETs ON – Top sideaaa-033748

Fig. 33. CFD current density simulation: Low side MOSFETs ON – Bottom side

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aaa-033749

Fig. 34. CFD current density simulation: High side MOSFETs ON – Top side

8. Driving paralleled MOSFETs
When driving paralleled MOSFETs it is recommended to use one single gate driver. This is mainly
done to synchronize the devices operation as much as possible.
The gate driver should have enough peak current capability to fully charge and discharge the total
input capacitance of the paralleled MOSFETs. This requirement becomes more and more stringent
as the number of MOSFETs increases, especially if the switching time is required to be low, as thetotal input capacitance is now Ciss,tot = n.FETs × Ciss,max. Failing to do so means that the switching
speed will be set by the gate driver itself and not by the gate resistor.
As shown by the previous simulations turn-OFF dissipates more energy than turn-ON. One simple
way to reduce the switching losses is by decreasing the resistance of RG,drv only during the turnOFF. This can be done by using a combination of a smaller resistor in series with a diode, placedin parallel with RG,drv, as shown in Fig. 35. However, before choosing the right value of RG,OFF it
is recommended to take into account any parasitic inductance that may be present in the circuit: a
combination of fast turn-OFF and high inductance could potentially induce avalanche, which, in aparallel configuration, could greatly stress the device with lower breakdown voltage.
D1

Rg_OFF

Rgdrv
aaa-033642

Fig. 35. Speeding up turn-OFF switching

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9. Simulation tools
This chapter describes how to set up a simulation aimed at finding the worst case scenario in aset of paralleled MOSFETs. In this case SPICE has been used, however, the same ideas can beapplied to any other simulation tool that offers the same functionality.
The idea is to take into account MOSFET spreads in a simulation, in the same way of usualcomponents tolerances. Two types of simulations are discussed: probability distribution and worst
case scenario simulations.
Probability distribution simulation refers to a simulation where one or more parameters are definedby their probability distribution, generally shown to be approximately Gaussian (or Normal).
This type of simulation would have the advantage of weighting each possible combination by
the likelihood of it happening. In theory, this would yield a more realistic evaluation and thedesigner could run the simulation for a number of iterations corresponding to the design BOM(bill of materials). In practice this type of evaluation is impractical since the data corresponding
to parameters distribution (mainly sigma value) would need to be measured for each specificpart name, it would not be guaranteed and it would require additional expensive steps in the
manufacturing process.
With respect to a distribution based simulation, the worst case scenario reduces the number of
iterations by taking into account only the maximum distribution of a parameter around its typicalN
value. The amount of runs is reduced to 2 + 1, where N is the number of indexed parameters and
1 is the nominal case, which is computed at the end. This type of evaluation is based on data sheet
spreads, which are guaranteed. On the other hand, it might miss “local extrema”, i.e. points inside
the spread at which the outcome is worse than the one resulting from considering only maximum,
minimum and nominal.
The analysis requires four main figures:••••

Spreads, namely typical value and ∆ (tolerance)
A function binary(run, index) that creates a set of indexes for the various combinations
A function wc(nominal, tol, index) that reads these indexes and outputs the correct value for theparameter
A function that automatically measures the average dissipated power over a cycle

Besides, the spreads need to be symmetrical so, in case of RDSon, the evaluation will either use ahigher minimum or maximum resistance than the data sheet one. Instead, in case the data sheet
does not provide a minimum value, as for QG(tot), then the middle point can be considered asnominal.
Prior to running the simulation the spice model of each MOSFET needs to be modified to replace
the value of each parameter considered in the evaluation, with the output of the wc(nom, tol, index)
function, as shown below:••••

RDSon typical value 0.88 mΩ, tolerance ±0.12 mΩ
RD 3 4 {wc(576.2603u,tol_RD,3)} TC= 9.735m, 2.369u
QGS typical value 33.5 nC, tolerance ± 13 nC
CGS 2 6 {wc(7.67n,tol_CGS,6)}
QGD typical value 25.5 nC, tolerance ± 17 nC.params CGD_scale = {wc(1.245,tol_CGD,9)}…G11 3 2 VALUE {CGD_scale*V(13,0)*I(V11)}
VGS(th) typical value 3 V, tolerance ±0.21 V
Vto= {wc(3.843,tol_VGSth,0)}where: tol_RD = 119.68u, tolCGS = 1.57n, tol_CGD = 0.405 and tol_VGSth = 0.21.
In this particular case the number of parameters are 4, these change between the 3 paralleled
MOSFETs so the total number of indexed parameters is 12. Consequently the amount of
12
combinations will be 2 + 1 = 4097. Only one MOSFET can be considered for this evaluation. A
slightly modified version of the circuit seen in Fig. 1 is used for this simulation. Furthermore, thesmall circuit of Fig. 36 is required in order to automatically compute the power dissipated by the
MOSFET under investigation (the corresponding 0 V monitor generator is required too).

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P_diss

B1

R1
1 kΩ

V=(V(Vd1)-V(Vs1))*I(VM1)

aaa-033639

Fig. 36. SPICE simulation circuit: measure of MOSFET dissipated power
After the simulation is complete, the current through M1 can be displayed. The final result can beseen in Fig. 37, Fig. 38 and Fig. 39, which shows the first 20 iterations.
aaa-033663

160
I D 140

(A)

120
100
80
60
40
20
0
-20
0

10

20

30

40

50

time (µs)

Fig. 37. Worst case simulation combinations - MOSFET drain current (ID)P

aaa-033664

4.5

AV

(W)

3.9
3.3
2.7
2.1
1.5
0.9

0

0.8

1.6

2.4

3.2
run index (x1000)

4

Fig. 38. Worst case simulation combinations - MOSFET average power

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aaa-033746

4
P
(W)
3

2

1

0

0

4

8

12

16

run index

20

Fig. 39. Worst case simulation combinations - MOSFET average power
The worst case scenario is when a single MOSFET is dissipating around 4.2 W of power. In
case only the VGS(th) spread is taken into account then the worst case scenario is when a single
MOSFET is dissipating around 1.7 W of power. This result can be used in a simple networkmodelling the steady state temperature behaviour of the junction, as shown in Fig. 40. In this casea PCB thermal resistance of around 15 K/W is needed to guarantee the junction temperature to belower than the maximum 175 °C. This would mean that an IMS or DBC board might be needed,as the temperature at the interface between MOSFET and PCB is higher than the rating of FR4.
Alternatively, one might consider adding an additional MOSFET or selecting a lower RDSon part.
Tj

149.68 °C Rj_mb 148 °C

Tmb

0.4
R_pcb
15

Pdiss

Tamb

4.2 A

85 V

.op

aaa-033640

Fig. 40. SPICE simulation MOSFET temperatures check
This concept can be applied to a wide range of scenarios: for instance one could consider various
duty cycles, evaluating each worst case scenario and then plugging these values into the current
source of the circuit shown in Fig. 40. Furthermore the instantaneous power waveform of the worst
case could be exported and used within an RC thermal network to verify that the instantaneous
junction temperature is below 175 °C.

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10. Conclusion
This application note aims at giving the reader a description of how the sharing among paralleled
MOSFETs is influenced by parameters spreads (e.g. RDSon, VGS(th) and QG(tot)) and PCB layout.
The analysis is conducted considering switch-mode (PWM) applications and thus the half-bridge
topology.
During switching, VGS(th) spread contributes the most to current unbalances, affecting turn-ON
and turn-OFF in the same way: the device with lower VGS(th) will turn-ON first and turn-OFF last,dissipating more power during both events. Additionally, the NTC of VGS(th) leads to increased
dissipation as it further lowers the VGS(th) of the MOSFET that handles more power. The spreadin QG(tot) can be effectively counteracted by splitting the gate resistor between one close to the
MOSFETs gate and a common one at the driver side. This modification will improve the sharing
with huge benefits during switching.
The RDSon is not as significant as VGS(th) when considering MOSFETs in parallel since its PTC
improves the sharing during conduction and counteracts the imbalances caused by RDSon spread.
2
Additionally the losses during conduction (I ×R) are generally lower than the switching losses
therefore the imbalance will weigh less on the overall power sharing.
A worst case scenario simulation can be used to quantify and evaluate the performance ofparalleled devices. It can be useful to understand which and how many devices to use in parallel.
The worst case depends mainly on the spread of certain parameters. The VGS(th) batch variability isshown to be around half that indicated on the respective data sheet. Albeit not guaranteed, spread
between batches is more realistic and leads to a design with improved performance.

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11. Appendix
11.1. Experimental measurements
The following data shows the first two pulses of current flowing through 3 low side MOSFETs usedin parallel. The circuit topology employed is the half bridge driving a 4 µH inductive load. Fourmeasurements are shown. M1, M2 and M3 RDSon, QG(tot) and VGS(th) (measured at both 1 mA and1 A) are quoted in the tables for each measurement.
aaa-033750

45

ID

(A)

35

M1
M2
M3

25
15
5
-5

0

10

20

time (µs)

30Fig. 41. Measurements n.1: MOSFET drain current
Table 16. Summary measurements n.1
DeviceRDSon [mΩ] QG(tot) [nC]

VGS(th) [V]@1 mA

VGS(th)[V]@ 1 A

EnergySharing
Switching

EnergySharing
Conduction

M1

3.16

35.57

3.02

3.62

33.7 %

33.1 %

M2

3.02

36.45

3.02

3.63

32.5 %

32.9 %

M3

2.94

35.64

3.02

3.62

33.8 %

34.0 %

ID

aaa-033751

70

(A)

M3

50

30

M2
M1

10

-10

0

10

20

time (µs)

30Fig. 42. Measurements n.2: MOSFET drain current

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Table 17. Summary measurements n.2
DeviceRDSon [mΩ] QG(tot) [nC]

VGS(th) [V]@1 mA

VGS(th)[V]@ 1 A

EnergySharing
Switching

EnergySharing
Conduction

M1

3.07

38.14

3.46

4.10

8.2 %

32.8 %

M2

2.94

35.64

3.02

3.62

36.1 %

33.7 %

M3

3.14

33.74

2.80

3.39

55.7 %

33.5 %

ID

aaa-033752

50
M3

(A)
M2
M1

30

10

-10

0

10

20

time (µs)

30Fig. 43. Measurements n.3: MOSFET drain current
Table 18. Summary measurements n.3
DeviceRDSon [mΩ] QG(tot) [nC]

AN50005

application note

VGS(th) [V]@1 mA

VGS(th)[V]@ 1 A

EnergySharing
Switching

EnergySharing
Conduction

M1

3.16

35.57

3.02

3.62

32.0 %

32.9 %

M2

3.43

28.69

3.03

3.63

32.0 %

32.9 %

M3

3.05

44.50

3.02

3.62

36.0 %

34.2 %All information provided in this document is subject to legal disclaimers.

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ID

aaa-033753

70

(A)

M3

50

M2

30

M1

10

-10

0

10

20

time (µs)

30Fig. 44. Measurements n.4: MOSFET drain current
Table 19. Summary measurements n.4
DeviceRDSon [mΩ]QG(tot) [nC]

VGS(th) [V]@1 mA

VGS(th)[V]@ 1 A

EnergySharing
Switching

EnergySharing
Conduction

M1

3.16

35.57

3.02

3.62

25.5 %

33.2 %

M2

3.05

44.50

3.02

3.62

27.5 %

33.2 %

M3

3.14

33.74

2.80

3.39

45.3 %

33.6 %

11.2. Simulations
The following simulations can be used to verify a SPICE model conformity to data sheet.

RDSon simulation
aaa-033728

M1

ID
BUK7S1R0-40H

25 A

VGS
0V

.inc BUK7S1R0-40H.lib.dc VGS 5 15 .1

Fig. 45. SPICE simulation circuit: RDSon check

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aaa-033756

1.8
RDSon
(mΩ)
1.4

1

0.6

5

7

9

11

13

V GS (V)15

Fig. 46. SPICE simulation circuit: RDSon as a function of VGS

QG(tot) simulation
aaa-033757

VGS

M1

BUK7S1R0-40H

I2

{ID}

D1

I1

D_clamp

PULSE(0 1m 1n 1n 1n 200u 400u 1).inc BUK7S1R0-40H.lib.dc VGS 5 15 .1.subckt D_clamp anode cathode.D1 anode cathode clamp_D.model clamp_D D(Rs=1e-6 Bv={Vdd} Vj={Vf} ibv={ID}.ends.param Vdd=32 ID=25 Vf=1

Fig. 47. SPICE simulation circuit: QG(tot) check

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Paralleling power MOSFETs in high power applicationsV

aaa-033758

16
GS

(V)

12

8

4

0

0

4

8

12

time (µs)

16-3Note: the charge can be found by multiplying the horizontal axis by 10 C/s.
Fig. 48. SPICE simulation circuit: VGS as a function of time

VGS(th) simulation
aaa-033759

M1

VDS
12 V

BUK7S1R0-40H

VGS
0V.inc BUK7S1R0-40H.lib.dc VGS 2.3 3.3 .01

Fig. 49. SPICE simulation circuit: VG(th) checkaaa-033760

16

ID
(mA)

12

8

4

0

2.2

2.6

3.0

V GS (V)

3.4

Fig. 50. SPICE simulation circuit: VG(th) check

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12. References
1. “The Art of Electronics”, by Paul Horowitz and Winfield Hill: §3.6.3. Paralleling MOSFETs, page.
213
2. AN90011: Half-bridge MOSFET switching and its impact on EMC
3. AN90003: LFPAK MOSFET thermal design guide”
4. BUK7S1R0-40H data sheet

13. Revision history
Table 20. Revision history
Revision
Date
numberDescription

1.1

2021-09-13

Minor update, values corrected in Table 12 and Table 14.

1.0

2021-09-07

Initial version.

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List of Tables
Table 1. Summary - Ideal case: equal MOSFETs................ 6
Table 2. BUK7S1R0-40H data sheet characteristics:
RDSon.................................................................................. 7
Table 3. SPICE model mod for RDSon spread....................7
Table 4. Summary - Effects of RDSon spread..................... 8
Table 5. BUK7S1R0-40H data sheet characteristics:
gate charge.......................................................................... 8
Table 6. SPICE model mod for QG(tot) spread................... 9
Table 7. Summary - Effects of QG(tot) spread...................10
Table 8. BUK7S1R0-40H data sheet characteristics:
VGS(th)...............................................................................10
Table 9. SPICE model mod for VGS(th) spread.................10
Table 10. Summary - Effects of VGS(th) spread................ 11
Table 11. Summary - Effects of VGS(th) batch spread.......17
Table 12. Summary - sharing without gate resistor
split: RG = 39 Ω.................................................................19
Table 13. Summary - sharing with gate resistor split:
RG,drv = 12 Ω and RG,split = 3.9 Ω................................. 19
Table 14. Summary – comparison of sharing with andwithout gate resistor split................................................... 19
Table 15. Summary – sharing with a source resistor of
1 mΩ...................................................................................21
Table 16. Summary measurements n.1............................. 32
Table 17. Summary measurements n.2............................. 33
Table 18. Summary measurements n.3............................. 33
Table 19. Summary measurements n.4............................. 34
Table 20. Revision history..................................................37

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List of Figures

Fig. 27. Effects of higher parasitic inductance on low
side VDS at turn-OFF........................................................ 23

Fig. 1. SPICE simulation circuit: half-bridge.........................3

Fig. 28. MOSFETs drain current (ID) - effects ofparasitic inductance imbalance.......................................... 23

Fig. 2. MOSFETs drain current (ID) and energy
dissipation (Ediss) - ideal case: equal MOSFETs. The
turn-ON, conduction and turn-OFF phases are indicated.... 4
Fig. 3. MOSFETs drain current (ID), energy dissipation(Ediss) and power dissipation (Pdiss) - ideal case:equal MOSFETs. The turn-ON phase is indicated............... 5
Fig. 4. MOSFETs drain current (ID), energy dissipation(Ediss) and power dissipation (Pdiss) - ideal case:equal MOSFETs. The turn-OFF phase is indicated............. 5

Fig. 29. Gate-source loop: possible layout.........................24
Fig. 30. Half-bridge layout possibilities showing
inductances........................................................................ 24
Fig. 31. CFD simulation setup........................................... 25
Fig. 32. CFD current density simulation: Low side
MOSFETs ON – Top side.................................................. 26
Fig. 33. CFD current density simulation: Low side
MOSFETs ON – Bottom side.............................................26

Fig. 5. BUK7S1R0-40H sub-threshold drain current as
a function of gate-source voltage........................................ 7

Fig. 34. CFD current density simulation: High side
MOSFETs ON – Top side.................................................. 27

Fig. 6. MOSFETs drain current (ID) - effects of RDSon
spread...................................................................................8

Fig. 35. Speeding up turn-OFF switching.......................... 27

Fig. 7. Gate charge waveform definitions............................ 9

Fig. 36. SPICE simulation circuit: measure of
MOSFET dissipated power................................................ 29

Fig. 8. MOSFETs drain current (ID) - effects of QG(tot)spread.................................................................................10

Fig. 37. Worst case simulation combinations MOSFET drain current (ID)................................................29

Fig. 9. MOSFETs drain current (ID) - effects of
VGS(th) spread.................................................................. 11

Fig. 38. Worst case simulation combinations MOSFET average power................................................... 29

Fig. 10. MOSFET electrical-thermal interaction................. 12

Fig. 39. Worst case simulation combinations MOSFET average power................................................... 30

Fig. 11. BUK7S2R5-40H data sheet graph: transfer
characteristic ZTC point..................................................... 12

Fig. 40. SPICE simulation MOSFET temperatures check.. 30

Fig. 12. BUK7S2R5-40H data sheet graph: normalized
on-state resistance as a function of junction temperature..13

Fig. 41. Measurements n.1: MOSFET drain current.......... 32

Fig. 13. SPICE simulation circuit: thermal coupling........... 13

Fig. 43. Measurements n.3: MOSFET drain current.......... 33

Fig. 14. Thermal coupling influence on sharing:
RDSon(M1) = 0.62 mΩ and RDSon(M2) = 1 mΩ...............14

Fig. 44. Measurements n.4: MOSFET drain current.......... 34

Fig. 15. BUK7S1R0-40H data sheet graph: gatesource threshold voltage as a function of junction
temperature........................................................................ 15

Fig. 46. SPICE simulation circuit: RDSon as a functionof VGS................................................................................35

Fig. 16. VGS(th) batches spread for BUK7S1R5-40H....... 16

Fig. 42. Measurements n.2: MOSFET drain current.......... 32

Fig. 45. SPICE simulation circuit: RDSon check................34

Fig. 47. SPICE simulation circuit: QG(tot) check............... 35

Fig. 17. Absolute value of the difference in VGS(th)between two consecutive devices......................................16

Fig. 48. SPICE simulation circuit: VGS as a function oftime..................................................................................... 36

Fig. 18. MOSFETs drain current (ID) – data sheet andbatch VGS(th) spread comparison.....................................17

Fig. 50. SPICE simulation circuit: VG(th) check.................36

Fig. 49. SPICE simulation circuit: VG(th) check.................36

Fig. 19. SPICE simulation circuit: gate resistor split
comparison......................................................................... 18
Fig. 20. Gate-source voltage without and with gate
resistor split........................................................................ 18
Fig. 21. MOSFETs drain current (ID) – without gate
resistor split........................................................................ 18
Fig. 22. MOSFETs drain current (ID) – with gate
resistor split........................................................................ 19
Fig. 23. SPICE simulation circuit: source resistors............ 20
Fig. 24. MOSFETs drain current (ID) – with a source
resistor of 1 mΩ................................................................. 21
Fig. 25. MOSFETs drain current (ID) – effects ofsource resistor value..........................................................21
Fig. 26. MOSFETs drain current (ID) - effects ofparasitic inductance........................................................... 22

AN50005

application note

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Rev. 1.1 — 13 September 2021

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AN50005

Nexperia

Paralleling power MOSFETs in high power applications

Contents
1. Introduction................................................................... 2
2. Applications.................................................................. 2
3. Key specifications........................................................ 2
4. MOSFET dissipation and parameters' influenceon current sharing............................................................. 4
5. Influence of parameter spread on current
sharing performance......................................................... 6
5.1. Static operation (DC)................................................... 7
5.1.1. Drain-source on-state resistance – RDSon.................7
5.2. Dynamic operation.......................................................8
5.2.1. Total input charge – QG(tot)....................................... 8
5.2.2. Gate-source threshold voltage – VGS(th)................. 10
5.3. Paralleled MOSFETs and temperature dependency.. 125.3.1. Temperature dependency during static
operation (DC)....................................................................13
5.3.2. Temperature dependency during dynamic
operation.............................................................................145.4. Data sheet and batch spreads.................................. 15
6. Circuit optimisation.................................................... 17
6.1. Localized gate resistor...............................................176.2. Components in the source path.................................20
7. PCB layout influence..................................................227.1. Layout-dependent parasitics......................................227.2. Circuit layout..............................................................23
8. Driving paralleled MOSFETs......................................27
9. Simulation tools..........................................................28
10. Conclusion................................................................ 31
11. Appendix....................................................................32
11.1. Experimental measurements................................... 32
11.2. Simulations...............................................................34
12. References................................................................ 37
13. Revision history........................................................37
14. Legal information......................................................38© Nexperia B.V. 2021. All rights reserved

For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 13 September 2021

AN50005

application note

All information provided in this document is subject to legal disclaimers.

Rev. 1.1 — 13 September 2021

© Nexperia B.V. 2021. All rights reserved

41 / 41