TPS23731
SLVSER7 – OCTOBER 2020

TPS23731 IEEE 802.3bt Type 3 Class 1-4 PoE PD with No-Opto Flyback DC-DC
Controller
1 Features

3 Description•

The TPS23731 device combines a Power over
Ethernet (PoE) powered device (PD) interface, anda current-mode DC-DC controller optimized for
flyback switching regulator designs where the use of
primary-side regulation (PSR) is supported. The PoEinterface supports the IEEE 802.3bt and IEEE 802.3atstandards for applications needing up to 25.5 W orless at PD input.

•

•

•
•

Complete IEEE 802.3bt Type 3 (Class 1-4) and802.3at PoE PD Solution– EA Gen 2 logo-ready (PoE 2 PD Controller)– Robust 100-V, 0.3-Ω (typ) Hotswap MOSFET– Supports power levels for up to 30-W operation
Integrated PWM controller for flyback configuration– Flyback control with primary-side regulation• Supports CCM operation• ±1.5% (typ, 5-V output) load regulation(0-100% load range) — with Sync FET• ±3% (typ, 12-V output) load regulation(5-100% load range) — diode rectified– Also supports secondary-side regulation– Soft-start control with advanced startup andhiccup mode overload protection– Soft-stop shutdown– Adjustable frequency with synchronization– Programmable frequency dithering for EMI
Automatic Maintain Power Signature (MPS)– Auto-adjust to PSE type and load current with
auto-stretch
Primary adapter priority input–40°C to 125°C junction temperature range

Programmable spread spectrum frequency dithering(SSFD) is provided to minimize the size and cost of
EMI filter. Advanced Startup with adjustable soft-starthelps to use minimal bias capacitor while simplifying
converter startup and hiccup design, also ensuringthat IEEE 802.3bt/at startup requirements are met.
The soft-stop feature minimizes stress on switchingsync FET(s), allowing FET BOM cost reduction.
The PSR feature of the DC-DC controller uses
feedback from an auxiliary winding for control of
the output voltage, eliminating the need for external
shunt regulator and optocoupler. It is optimized
for continuous conduction mode (CCM), and canwork with secondary side synchronous rectification,
resulting in optimum efficiency, regulation accuracy
and step load response over multiple outputs.

2 Applications
Video and VoIP Telephones
Access Points
Security Cameras
Redundant Power Feeds or Power Sharing

The DC-DC controller features slope compensation
and blanking. Typical switching frequency is 250 kHz.
The automatic MPS enables applications with low
power modes or multiple power feeds. It automaticallyadjusts its pulsed current amplitude and durationaccording to PSE Type and system conditions, tomaintain power while minimizing consumption.
Device Information(1)PART NUMBER
TPS23731
(1)

DEN

+

CBULK

RCL CCL
DCL
VOUT2

APDO
COUT2

T2P

58V
RCLS

RCS

COUT

COMP
CCOMP

APD

RAPD1

RAPD2

RUV1

LINEUV

CDTR

DCC
RCOMP
CVCC

FB

R1
CCC2

CP

FRS

RFRS

VOUT1

VCC
VSS

RDTR

48V
Adapter

CS

CLS

I_in

DA

7.00 mm × 5.00 mm

T1

VCC
RAPD

VSON (45)

BODY SIZE (NOM)

GATE

0.1 F

RUV2

PACKAGEFor all available packages, see the orderable addendum atthe end of the data sheet.

RT2P

From Ethernet
Transformers

TPS23731
VDD
RDEN

From Spare
Pairs orTransformers

•
•
•
•

R2

SST

CSST

EA_DISDTHR
VB
RTN GND I_STP PSRSCVB

RI_STP

Simplified Application
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 6
7.1 Absolute Maximum Ratings ....................................... 6
7.2 ESD Ratings .............................................................. 6
7.3 Recommended Operating Conditions ........................7
7.4 Thermal Information ...................................................7
7.5 Electrical Characteristics: DC-DC Controller
Section ......................................................................... 7
7.6 Electrical Characteristics PoE ..................................10
7.7 Typical Characteristics.............................................. 13
8 Detailed Description......................................................17
8.1 Overview................................................................... 17
8.2 Functional Block Diagram......................................... 18
8.3 Feature Description...................................................19

8.4 Device Functional Modes..........................................27
9 Application and Implementation.................................. 41
9.1 Application Information............................................. 41
9.2 Typical Application.................................................... 41
10 Power Supply Recommendations..............................44
11 Layout........................................................................... 45
11.1 Layout Guidelines................................................... 45
11.2 Layout Example...................................................... 45
11.3 EMI Containment.................................................... 45
11.4 Thermal Considerations and OTSD........................ 45
11.5 ESD.........................................................................45
12 Device and Documentation Support..........................46
12.1 Documentation Support.......................................... 46
12.2 Support Resources................................................. 46
12.3 Trademarks............................................................. 46
12.4 Electrostatic Discharge Caution..............................46
12.5 Glossary..................................................................46
13 Mechanical, Packaging, and Orderable
Information.................................................................... 46

4 Revision History

2

DATE

REVISION

NOTES

October 2020*

Initial release.

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5 Device Comparison Table
TPS23730

TPS23731

TPS23734

Class Range

KEY FEATURES

1-6

1-4

1-4

ACF Support

Yes

No

Yes

SSFD

Yes

Yes

Yes

Soft-stop

Yes

Yes

Yes

Advanced Startup

Yes

Yes

Yes

PSR (Flyback)

Yes

Yes

Yes

Auto MPS

Yes

Yes

Yes

PPD

Yes

No

No

APD

Yes

Yes

Yes

TPH/TPL (parallel) or TPL(serial)T2P, APDO

T2P, APDOPoE allocated power and AUX power
indicator(s)6 Pin Configuration and Functions

36

40

EA_DIS

41

37

VBG

42

VB

NC

43

38

VCC

44

39

GATE

45

PSRS

CP

LINEUV

GND

CS

1

35

COMP

AGND

2

34

FB

DTHR

3

33

SST

FRS

4

32

I_STP

APD

5

31

NC

NC

6

30

TEST

RTN

7

RTN

8

29

NC

RTN

9

28

VSS

27

VSS

26

NC

PAD_G

NC

10

EMPS

11

25

NC

NC

12

24

DEN

APDO

13

23

VDD

PAD_S

18

19

20

21

REF

NC

NC

NC

CLS

NC

17

NC

22

16

NC

T2P

15

14

Figure 6-1. Package Pinout
Table 6-1. Pin Functions
PIN
NO.

NAME

1

CS

I/O
I/O

DESCRIPTION
DC-DC controller current sense input. Connect directly to the external power current sense
resistor.

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Table 6-1. Pin Functions (continued)
PIN

4

I/O

DESCRIPTION

NO.

NAME

2

AGND

-

AGND is the DC-DC converter analog return. Tie to RTN and GND on the circuit board.

3

DTHR

O

Used for spread spectrum frequency dithering. Connect a capacitor (determines the modulating
frequency) from DTHR to RTN and a resistor (determines the amount of dithering) from DTHR to
FRS. If dithering is not used, short DTHR to VB pin.

4

FRS

I

This pin controls the switching frequency of the DC-DC converter. Tie a resistor from this pin to
RTN to set the frequency.

5

APD

I

Primary auxiliary power detect input. Raise 1.5 V above RTN to disable pass MOSFET, also
turning class off. If not used, connect APD to RTN.

7, 8, 9RTN-

RTN is the output of the PoE hotswap and the reference ground for the DC-DC controller.

11

EMPS

I

Automatic MPS enable input, referenced to RTN, internally pulled-up to 5-V internal rail. Tie to
RTN to disable automatic MPS.

13

APDO

O

Active low output referenced to RTN, indicates that an auxiliary power adapter is detected via the
APD input.

14

T2P

O

Active low output that indicates a PSE has performed the IEEE 802.3at Type 2 hardware
classification, or APD is active.

17

REF

O

Internal 1.25-V voltage reference. Connect a 49.9-kΩ_1% resistor from REF to VSS.

21

CLS

O

Connect a resistor from CLS to VSS to program the classification current.

23

VDD

—

Positive input power rail for PoE interface circuit and source of DC-DC converter start-up current.
Bypass with a 0.1 µF to VSS and protect with a TVS.

24

DEN

I/O

Connect a 25.5-kΩ resistor from DEN to VDD to provide the PoE detection signature. Pulling thispin to VSS during powered operation causes the internal hotswap MOSFET to turn off.

27, 28VSS-

Negative power rail derived from the PoE source.

30

TEST

O

Used internally for test purposes only. Leave open.

32

I_STP

I

This pin sets the SST discharge current during a soft-stop event independently from the settingused during a regular soft-start event. Connect a resistor from this pin to AGND to set the DC/DC
soft-stop rate.

33

SST

I/O

A capacitor from SST to RTN pin sets the soft-start (ISSC charge current) and the hiccup timer (ISSD
discharge current) for the DC-DC converter. Connect a capacitor from this pin to RTN to set the
DC/DC startup rate.

34

FB

I

Converter error amplifier inverting (feedback) input. If flyback configuration with primary-side
regulation, it is typically driven by a voltage divider and capacitor from the auxiliary winding,working with CP pin, FB also being connected to the COMP compensation network. If optocoupler
feedback is enabled, tie FB to VB.

35

COMP

I/O

Compensation output of the DC-DC convertor error amplifier or control loop input to the PWM. If
the internal error amplifier is used, connect the compensation networks from this pin to the FB pin
to compensate the converter. If optocoupler feedback is enabled, the optocoupler and its network
pulled up to VB directly drives the COMP pin.

36

EA_DISI

Error Amplifier disable input, referenced to AGND, internally pulled-up to 5V internal rail. Leave
EA_DIS open to disable the Error amplifier, to enable optocoupler feedback for example. Connect
to AGND otherwise.

37

VB

O

5-V bias rail for DC/DC control circuits and the feedback optocoupler (when in use). Connect a
0.1-uF capacitor from this pin to AGND to provide bypassing.

38

LINEUVI

LINEUV is used to monitor the bulk capacitor voltage to trigger a soft-stop event when anundervoltage condition is detected if APD is low. If not used, connect LINEUV to VB pin.

39

PSRS

I

PSR Sync enable input, referenced to AGND, internally pulled-up to 5V internal rail. PSRS works
with CP pin to support flyback architecture using primary-side regulation. Leave PSRS open if
the flyback output stage is configured with synchronous rectification and uses PSR. If dioderectification is used, or for applications not using PSR, connect PSRS to AGND.

40

VBG

O

5-V bias rail for the switching FET gate driver circuit. For internal use only. Bypass with a 0.1-μF
ceramic capacitor to GND pin.

42

VCC

I/O

DC/DC converter bias voltage. The internal startup current source and converter bias winding
output power this pin. Connect a 1µF minimum ceramic capacitor to RTN.

43

GATE

O

Gate drive output for the main DC-DC converter switching MOSFET

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Table 6-1. Pin Functions (continued)
PIN

I/O

DESCRIPTIONCPO

CP provides the clamp for the primary-side regulation loop. Connect this pin to the lower end of thebias winding of the flyback transformer.

45

GND

-

.Power ground used by the flyback power FET gate driver and CP. Connect to RTN.

6, 10, 12,
15, 16,18-20, 22,
25, 26, 29,
31, 41NC-

No connect pin. Leave open.

47

PAD_S

-

The exposed thermal pad must be connected to VSS. A large fill area is required to assist in heatdissipation.

46

PAD_G

-

The exposed thermal pad must be connected to RTN. A large fill area is required to assist in heatdissipation.

NO.

NAME

44

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7 Specifications
7.1 Absolute Maximum Ratings
Voltage are with respect to VSS (unless otherwise noted)(1)Input voltage

Voltage

Sourcing current
Sourcing current

MIN

MAX

VDD, DEN, GND, AGND, RTN(2)

–0.3

100

VDD to RTN

–0.3

100

APD, FB, CS, EA_DIS, LINEUV, PSRS, EMPS, all to RTN

–0.3

6.5

FRS(3), COMP, VB(3), VBG(3), I_STP(3), DTHR(3), SST(3), all to RTN

-0.3

6.5

VCC to RTN

-0.3

19

GATE(3) to RTN-0.3

VCC+0.3

CP to GND

-0.3

60

GND, AGND, all to RTN

-0.3

0.3

REF(3) , CLS(3)

-0.3

6.5

T2P, APDO , all to RTN

-0.3

19

VB, VBG, VCC

Internally limited

COMP

Internally limited

REF

Internally limited

CLS
RTN

Sinking current

UNIT
V

V

mA
65

mA

1

mA

Internally limited

DEN
COMP

Internally limited

Sinking current

T2P, APDO

10mA

Peak sourcing
current

CP

2

A

Peak sinking current CP

0.7

TJ(max)Maximum junction temperature

Tstg

Storage temperature

(1)

(2)
(3)

Internally Limited
–65

A
°C

150

°C

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stressratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated underRecommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
IRTN = 0 for VRTN > 80 V.
Do not apply voltage to these pins.

7.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)V(ESD)

Electrostatic discharge

UNIT

±2000

Charged-device model (CDM), per JEDEC specification JESD22-C101(2)±500

IEC 61000-4-2 contact discharge(3)±8000

IEC 61000-4-2 air-gap discharge(3)±15000

V

(1)
(2)
(3)

JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Surges per EN61000-4-2, 1999 applied between RJ-45 and output ground and between adapter input and output ground of
the TPS23730, TPS23730EVM-093 evaluation module (documentation available on the web). These were the test levels, not the
failure threshold.

6

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7.3 Recommended Operating Conditions
Voltage with respect to VSS (unless otherwise noted)
MIN

NOM

MAX

VDD, RTN, GND, AGND

0

VCC to RTN

0

16

0

VB

Input voltage range APD, EA_DIS, LINEUV, PSRS, FB, all to RTN

UNIT

60
V

CS to RTN

02

CP to GND

0

45
VB

V

0

VCC

V

Voltage range

COMP to RTN

Voltage range

T2P, APDO, all to RTN

Sinking current

RTN

0.65

A

Sinking current

T2P, APDO

3

mA

VCC

20

VB

5

Sourcing current
CapacitanceResistanceResistance

TJ(1)

VB, VBG(1)

0.08

0.1

1

VCC

0.7

1

100

I_STOP

16.5

CLS(1)30

REF(1)

48.9

Synchronization pulse width input (when used)

35

Operating junction temperature

–40

mA
μF

499

KΩ
Ω

49.9

50.9

kΩ
ns

125

°C

Voltage should not be externally applied to this pin.

7.4 Thermal Information
THERMAL METRIC

RMT (VSON)

UNIT

45 PINS
RθJA (1)Junction-to-ambient thermal resistance

38.5

RθJC(top)

Junction-to-case (top) thermal resistance

23.6

Junction-to-board thermal resistance

19.3

Junction-to-top characterization parameter

6.8

RθJB

(1)

ψJT (1)
ψJB

(1)

°C/W

Junction-to-board characterization parameter

19.3

RθJC(bot_POE)

Junction-to-case (bottom PAD_S pad) thermal resistance

3.9

RθJC(bot_DCDC)

Junction-to-case (bottom PAD_G pad) thermal resistance

9.1

(1)

Thermal metrics are not JEDEC standard values and are based on the TPS23731EVM-095 evaluation board.

7.5 Electrical Characteristics: DC-DC Controller Section
Unless otherwise noted, VVDD = 48 V; RDEN = 25.5 kΩ; RFRS = 60.4 kΩ; RI_STP = 499 kΩ; CLS, T2P, APDO, and PSRS open;
CS, EA_DIS, APD, EMPS, AGND and GND connected to RTN; FB, LINEUV and DTHR connected to VB; CVB = CVBG = 0.1
μF; CVCC = 1 μF; CSST = 0.047 μF; RREF = 49.9 kΩ; 8.5 V ≤ VVCC ≤ 16 V; –40°C ≤ TJ ≤ 125°C. Positive currents are into pins
unless otherwise noted. Typical values are at 25°C.
[VVSS = VRTN], all voltages referred to VRTN , VAGND and VGND unless otherwise noted.
PARAMETERTEST CONDITIONS

MIN

TYP

MAX

UNIT

8

8.25

8.5

V

5.85

6.1

6.35

V

2

2.15

2.3

V

DC-DC SUPPLY (VCC)
VCUVLO_R

VVCC rising

VCUVLO_F Undervoltage lockout

VVCC falling, VFB = VRTNVCUVLO_

Hysteresis(1)H

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7.5 Electrical Characteristics: DC-DC Controller Section (continued)
Unless otherwise noted, VVDD = 48 V; RDEN = 25.5 kΩ; RFRS = 60.4 kΩ; RI_STP = 499 kΩ; CLS, T2P, APDO, and PSRS open;
CS, EA_DIS, APD, EMPS, AGND and GND connected to RTN; FB, LINEUV and DTHR connected to VB; CVB = CVBG = 0.1
μF; CVCC = 1 μF; CSST = 0.047 μF; RREF = 49.9 kΩ; 8.5 V ≤ VVCC ≤ 16 V; –40°C ≤ TJ ≤ 125°C. Positive currents are into pins
unless otherwise noted. Typical values are at 25°C.
[VVSS = VRTN], all voltages referred to VRTN , VAGND and VGND unless otherwise noted.
PARAMETER
IRUN

Operating current

TEST CONDITIONS

MIN

TYP

MAX

UNIT

1.2

2

2.4

mA

VVDD ≥ 28V, VVCC = 11.7 V

21.5

30

34

VVDD = 10.2V, VVCC = 8.6 V

1

6

17.5

VVDD = 10.2V, VVCC = 6.8 V

VVCC = 10 V, VFB = VRTN , RDT = 24.9 kΩ, CP with
2-kΩ pull up to 30 V
VAPD = 2.5V

IVC_STtST

Startup source current

Startup time, CVCC = 1 μF

VVC_ST

VCC startup voltage

VVC_SSTP VCC soft-stop voltage

mA

8

16

32

VVDD = 10.2 V, VVCC(0) = 0 V, measure time until
VCUVLO_R

0.25

0.7

1.15

ms

VVDD = 35 V, VVCC(0) = 0 V, measure time until
VCUVLO_R

0.24

0.35

0.48

ms

Measure VVCC during startup, IVCC = 0 mA

11

12.5

14

Measure VVCC during startup, IVCC = 21.5 mA

11

12.5

14

VLINEUV < VLIUVF, Measure VVCC during soft-stop, IVCC
= 0 mA

11

12.5

14

VLINEUV < VLIUVF, Measure VVCC during soft-stop, IVCC
= 21.5 mA

11

12.5

14

VFB = VRTN, 8.5 V ≤ VVCC ≤ 16 V, 0 ≤ IVB ≤ 5 mA

4.75

5.0

5.25

V

223

248

273

kHz

74.5%

78.5%

82.5%

2

2.2

2.4

V

V

VB
Voltage
DC-DC TIMING (FRS)fSW

Switching frequency

VFB = VRTN, Measure at GATE

DMAX

Duty cycle

VFB = VRTN, RDT = 24.9 kΩ, Measure at GATE

VSYNC

Synchronization

Input threshold

V

FREQUENCY DITHERING RAMP GENERATOR (DTHR)IDTRCH

Charging (sourcing) current

0.5 V < VDTHR < 1.5 V

IDTRDC

Discharging (sinking) current

0.5 V < VDTHR < 1.5 V

VDTUT

Dithering upper threshnold

VDTLT

Dithering lower threshold

VDTPP

Dithering pk-pk amplitude

3 x IFRS
47.2

49.6

µA
52.1

3 x IFRS

µA
µA

47.2

49.6

52.1

µA

VDTHR rising until IDTHR > 0

1.41

1.513

1.60

V

VDTHR falling until IDTHR < 0

0.43

0.487

0.54

V

1.005

1.026

1.046

V

1.723

1.75

1.777

V

0.5

μA

ERROR AMPLIFIER (FB, COMP)

8

VREFC

Feedback regulation voltage

IFB_LKFB leakage current (source or
VFB = 1.75 V
sink)

GBW

Small signal unity gain
bandwidth

0.9

1.2

MHz

AOL

Open loop voltage gain

70

80

db

VZDC

0% duty-cycle threshold

VCOMP falling until GATE switching stops

1.35

1.5

ICOMPHCOMP source current

VFB = VRTN , VCOMP = 3 V

1ICOMPLCOMP sink current

VFB = VVB , VCOMP = 1.25 V

2.1

VCOMPHCOMP high voltage

VFB = VRTN , 15 kΩ from COMP to RTN

VCOMPLCOMP low voltage

VFB = VVB , 15 kΩ from COMP to VB

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4

1.65

V
mA

6

mA
VB

V

1.1

V

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7.5 Electrical Characteristics: DC-DC Controller Section (continued)
Unless otherwise noted, VVDD = 48 V; RDEN = 25.5 kΩ; RFRS = 60.4 kΩ; RI_STP = 499 kΩ; CLS, T2P, APDO, and PSRS open;
CS, EA_DIS, APD, EMPS, AGND and GND connected to RTN; FB, LINEUV and DTHR connected to VB; CVB = CVBG = 0.1
μF; CVCC = 1 μF; CSST = 0.047 μF; RREF = 49.9 kΩ; 8.5 V ≤ VVCC ≤ 16 V; –40°C ≤ TJ ≤ 125°C. Positive currents are into pins
unless otherwise noted. Typical values are at 25°C.
[VVSS = VRTN], all voltages referred to VRTN , VAGND and VGND unless otherwise noted.
PARAMETERTEST CONDITIONS

MIN

TYP

MAX

UNIT

70

100

130

kΩ

ΔVCS / ΔVCOMP , 0 V < VCS < 0.22 V

0.19

0.2

0.21

V/V

7.5

10

12.5

µA

COMP input resistance, error
amplifier disabled

EA_DIS open

COMP to CS gain
SOFT-START, SOFT-STOP (SST, I_STP)
ISSC

Charge current

SST charging, 6.35 V ≤ VVCC ≤ 16 V

ISSD

Discharge current

SST discharging, 6.35 V ≤ VVCC ≤ 16 V

VSFST

Soft-start lower threshold

VSTUOF

Startup turn off threshold

VSSOFS

3

4

5

µA

0.15

0.2

0.25

V

VSST rising until VCC startup turns off

1.99

2.1

2.21

V

Soft-start offset voltage,closed-loop mode

VFB = VRTN, VSST rising until start of switching

0.2

0.25

0.3

V

Soft-start offset voltage, peakcurrent mode

VCOMP = VVB, VSST rising until start of switching,
EA_DIS open

0.55

0.6

0.65

V

2.6

V

VSSCL

Soft-start clamp

2.3

ISSD_SP

SST discharge current in soft- RI_STP = 499 kΩ, VLINEUV < VLIUVF
stop mode
RI_STP = 16.5 kΩ, ,VLINEUV < VLIUVF

1.5

2

2.5

52.5

60.6

67.5

End of soft-stop threshold

VFB = VRTN, VLINEUV < VLIUVF

0.15

0.2

0.25

VSSTPEN
DµA
V

CURRENT SENSE (CS)VCSMAX

Maximum threshold voltage

VFB = VRTN, VCS rising

0.227

0.25

0.273

V

tOFFD_IL

Current limit turn off delay

VCS = 0.3 V

25

41

60

ns

tOFFD_PW

PWM comparator turn off
delay

VCS = 0.15 V, EA_DIS open, VCOMP = 2 V

25

41

60

ns

Blanking delay

In addtition to tOFFD_IL and tOFFD_PW

75

95

115

ns

VSLOPEInternal slope compensation
voltage

VFB = VRTN, Peak voltage at maximum duty cycle,
referred to CS

51

66

79

mV

ISL_EX

Peak slope compensation
current

VFB = VRTN, ICS at maximum duty cycle (accomponent)

14

20

26

μA

Bias current

DC component of CS current

-3

-2

-1

μA

LINE UNDERVOLTAGE, SOFT-STOP (LINEUV)VLIUVFVLIUVH

LINEUV falling thresholdvoltage

VLINEUV falling

2.86

2.918

2.976

V

Hysteresis(1)

57

82

107

mV

Leakage current

VLINEUV = 3 V

1µA

Peak source current

VFB = VRTN , VVCC = 10 V, VGATE = 0 V, pulsed
measurement

0.3

0.5

0.8

A

Peak sink current

VFB = VRTN , VVCC = 10 V, VGATE = 10 V, pulsed
measurement

0.6

0.9

1.45

A

Rise time(2)tprr10-90 , CGATE = 1 nF , VVCC = 10 V

30

ns

Fall time(2)tpff90-10 , CGATE = 1 nF , VVCC = 10 V

15ns

ICP = 100 mA

1.5

3.3

Ω

0.6

0.85

V

GATE

CLAMPING FET (CP)RDS(ON)CL

CP FET on resistance

CLAMPING DIODE (CP)VFCP

CP Diode forward voltage

VPSRS = 0 V, ICP = 15 mA

0.45

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7.5 Electrical Characteristics: DC-DC Controller Section (continued)
Unless otherwise noted, VVDD = 48 V; RDEN = 25.5 kΩ; RFRS = 60.4 kΩ; RI_STP = 499 kΩ; CLS, T2P, APDO, and PSRS open;
CS, EA_DIS, APD, EMPS, AGND and GND connected to RTN; FB, LINEUV and DTHR connected to VB; CVB = CVBG = 0.1
μF; CVCC = 1 μF; CSST = 0.047 μF; RREF = 49.9 kΩ; 8.5 V ≤ VVCC ≤ 16 V; –40°C ≤ TJ ≤ 125°C. Positive currents are into pins
unless otherwise noted. Typical values are at 25°C.
[VVSS = VRTN], all voltages referred to VRTN , VAGND and VGND unless otherwise noted.
PARAMETER
CP Leakage current

TEST CONDITIONS

MIN

TYP

VPSRS = 0 V, VCP = 45 V

MAX

UNIT

20

µA
V

AUXILIARY POWER DETECTION (APD, APDO)
VAPDEN
VAPDH
VAPL

APD threshold voltage

VAPD rising

1.42

1.5

1.58

Hysteresis(1)

0.075

0.095

0.115

V

1

µA

Leakage current

VAPD = 5 V

APDO output low voltage

VAPD = 5 V, IAPDO = 1 mA, startup has completed

Leakage current

VAPDO = 10 V

0.27

0.5

V

1

µA

165

°C

THERMAL SHUTDOWN
Turnoff temperature

145

155

Hysteresis(2)
(1)
(2)

15

°C

The hysteresis tolerance tracks the rising threshold for a given device.
These parameters are provided for reference only, and do not constitute part of TI's published device specifications for purposes of TI's
product warranty.

7.6 Electrical Characteristics PoE
Unless otherwise noted, VVDD = 48 V; RDEN = 25.5 kΩ; RFRS = 60.4 kΩ; RI_STP = 499 kΩ; CLS, T2P, APDO, and PSRS open;
CS, EA_DIS, APD, EMPS, AGND and GND connected to RTN; FB, LINEUV and DTHR connected to VB; CVB = CVBG = 0.1
μF; CVCC = 1 μF; CSST = 0.047 μF; RREF = 49.9 kΩ; –40°C ≤ TJ ≤ 125°C. Positive currents are into pins unless otherwise
noted. Typical values are at 25°C.
VVCC-RTN = 0 V, all voltages referred to VVSS unless otherwise noted.
PARAMETERTEST CONDITIONS

MIN

TYP

MAX

UNIT

3.5

6.9

13.9

µA

0.1

5

µA

Measure IVDD + IDEN + IRTN, VVDD = 1.4 V

53.5

56.5

58.6

μA

Measure IVDD + IDEN + IRTN, VVDD = 10 V, Not in
mark

391

398

406.2

μA

3

4

5

V

PD DETECTION (DEN)

Ilkg

Detection bias current

DEN open, VVDD = 10 V, Not in mark, Measure
IVDD + IRTN

DEN leakage current

VDEN = VVDD = 60 V, Float RTN, Measure IDEN

Detection current

VPD_DIS

Hotswap disable
threshold

DEN falling

PD CLASSIFICATION (CLS)

ICLS

10

Classification signature
current

RCLS = 806 Ω

13 V ≤ VDD ≤ 21 V,
Measure IVDD + IDEN +
IRTN

1.9

2.5

2.9

mA

RCLS = 130 Ω

13 V ≤ VDD ≤ 21 V,
Measure IVDD + IDEN +
IRTN

9.9

10.6

11.3

mA

RCLS = 69.8 Ω

13 V ≤ VDD ≤ 21 V,
Measure IVDD + IDEN +
IRTN

17.6

18.6

19.4

mA

RCLS = 46.4 Ω

13 V ≤ VDD ≤ 21 V,
Measure IVDD + IDEN +
IRTN

26.5

27.9

29.3

mA

RCLS = 32 Ω

13 V ≤ VDD ≤ 21 V,
Measure IVDD + IDEN +
IRTN

37.8

39.9

42

mA

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7.6 Electrical Characteristics PoE (continued)
Unless otherwise noted, VVDD = 48 V; RDEN = 25.5 kΩ; RFRS = 60.4 kΩ; RI_STP = 499 kΩ; CLS, T2P, APDO, and PSRS open;
CS, EA_DIS, APD, EMPS, AGND and GND connected to RTN; FB, LINEUV and DTHR connected to VB; CVB = CVBG = 0.1
μF; CVCC = 1 μF; CSST = 0.047 μF; RREF = 49.9 kΩ; –40°C ≤ TJ ≤ 125°C. Positive currents are into pins unless otherwise
noted. Typical values are at 25°C.
VVCC-RTN = 0 V, all voltages referred to VVSS unless otherwise noted.
PARAMETERTEST CONDITIONS
13 V ≤ VDD ≤ 21 V,
Measure IVDD + IDEN +
IRTN

MIN

TYP

MAX

UNIT

37.8

39.9

42

mA

ICLS

Classification signature
RCLS = 32 Ω
current, 3rd class event

VCL_ONClassification regulator
lower threshold rising

VVDD rising, ICLS ↑

11.4

12.2

13

V

VCL_H

Classification regulator
lower threshold

Hysteresis(1)

0.8

1.2

1.6

V

VVDD rising, ICLS ↓

21

22

23

V

VCU_H

Classification regulator
upper threshold

Hysteresis(1)

0.5

0.77

1

V

VMSR

Mark state reset
threshold

VVDD falling

3

3.9

5

V

Mark state resistance

2-point measurement at 5 V and 10.1 V

6

10

12

kΩ

Ilkg

Leakage current

VVDD = 60 V, VCLS = 0 V, VDEN = VVSS, Measure
ICLS

1

μA

tLCF_PDLong first class event
timingClass 1st event time duration for short MPS

VCU_OFF

76

81.5

87

ms

RTN (PASS DEVICE)
0.3

0.55

Ω

ILIM

ON-resistance
Current limit

VRTN = 1.5 V, pulsed measurement

0.75

0.925

1.1

A

IIRSH

inrush current limit

VRTN = 2 V, VVDD: 20 V → 48 V, measure IRTN ,pulsed measurement

100

140

180

mA

Percentage of inrush current.

tINR_DEL

80%

90%

99%

Inrush delay

80

84

88

ms

Foldback voltage
threshold

VRTN rising

13.5

14.8

16.1

V

Foldback deglitch time

VRTN rising to when current limit changes toinrush current limit. This applies in normal
operating condition or during auto MPS mode.

1.5

1.8

2.1

ms

Leakage current

VVDD = VRTN = 100 V, VDEN = VVSS

70

μA

0.5

V

1

µA

Inrush termination

PSE TYPE INDICATION (T2P)
Output low voltage

IT2P = 1 mA, after 2- or 3-event classification,
startup has completed, VRTN = 0 V

Leakage current

VT2P-RTN = 10 V, VRTN = 0 V

0.27

PD INPUT SUPPLY (VDD)
VUVLO_R

Undervoltage lockout
threshold

VVDD rising

35.8

37.6

39.5

V

VUVLO_F

Undervoltage lockout
threshold

VVDD falling

30.5

32

33.6

V

VUVLO_H

Undervoltage lockout
threshold

Hysteresis (1)

5.7

6.0

6.3

V

IVDD_ON

Operating current

40 V ≤ VVDD ≤ 60 V, Startup completed, VVCC =10 V, Measure IVDD

650

1040

µA

IVDD_OFFOff-state current

RTN, GND and VCC open, VVDD = 30 V, Measure
IVDD

730

µA

MPS total VSS current
for Type 1-2 PSE

EMPS open, inrush delay has completed, 0 mA ≤IRTN ≤ 10 mA, measure IVSS

15.5

mA

MPS
IMPSL

10

12.5

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7.6 Electrical Characteristics PoE (continued)
Unless otherwise noted, VVDD = 48 V; RDEN = 25.5 kΩ; RFRS = 60.4 kΩ; RI_STP = 499 kΩ; CLS, T2P, APDO, and PSRS open;
CS, EA_DIS, APD, EMPS, AGND and GND connected to RTN; FB, LINEUV and DTHR connected to VB; CVB = CVBG = 0.1
μF; CVCC = 1 μF; CSST = 0.047 μF; RREF = 49.9 kΩ; –40°C ≤ TJ ≤ 125°C. Positive currents are into pins unless otherwise
noted. Typical values are at 25°C.
VVCC-RTN = 0 V, all voltages referred to VVSS unless otherwise noted.
PARAMETER
IMPSH

tMPSL

tMPSH

TEST CONDITIONS

MIN

TYP

MAX

UNIT

EMPS open, inrush delay has completed, 0 mA ≤IRTN ≤ 16 mA, measure IVSS

16.25

19

21.5

mA

MPS pulsed current
duty-cycle

EMPS open

26.2%

26.6%

26.9%

MPS pulsed mode duty MPS pulsed current ON
EMPS open
cycle for Type 1-2 PSE time

76

81.5

87

ms

225

245

ms

MPS total VSS current
for Type 3-4 PSE

MPS pulsed current
OFF time

EMPS open

MPS pulsed current
duty-cycle, no pulse
stretching

EMPS open

2.9%

3.0%

3.1%

EMPS open

7.2

7.7

8.1

ms

EMPS open

238

250

265

ms

MPS pulsed current ON
EMPS open
time stretching limit

54

57

62

ms

148

158

168

°C

MPS pulsed current
MPS pulsed mode duty- ON time, no pulse
cycle for Type 3-4 PSE stretching
MPS pulsed current
OFF time

THERMAL SHUTDOWN
Turnoff temperature
Hysteresis(2)

15

(1)
(2)

The hysteresis tolerance tracks the rising threshold for a given device.
These parameters are provided for reference only.

12

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7.7 Typical Characteristics
0.96

12.5

0.95

Current Limit (A)VDD Bias Current (PA)

10

7.5

5

TJ = -40qC
TJ = 25qC
TJ = 125qC

2.5

2

3

4
5
6
7
VDD-VSS Voltage (V)

8

9

0.93
0.92
0.91

0
1

0.94

0.9
-50

10

-25

0
25
50
75
Junction Temperature (qC)

D001

Figure 7-1. Detection Bias Current vs Voltage

100

125
D003

Figure 7-2. PoE Current Limit vs Temperature
1000

0.5

VDD Total Supply Current (PA)950
Pass FET Resistance (:)

0.45
0.4
0.35
0.3
0.25

900
850
800
750
700
650
TJ = -40qC
TJ = 25qC
TJ = 125qC

600
550

0.2
-50

-25

0
25
50
75
Junction Temperature (qC)

100

500
25

125

VVCC = 11.7 V
TJ = -40qC
TJ = 25qC
TJ = 125qC
20

25

30
35
40
45
VDD-RTN Voltage (V)

35

50

55

40
45
50
VDD-VSS Voltage (V)

55

60
D005

Figure 7-4. VDD Supply Current vs Voltage

VCC Sourcing Current (mA)

VCC Sourcing Current (mA)

Figure 7-3. Pass FET Resistance vs Temperature
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
15

30

D004

60

35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
10

VVCC = 6.8 V
TJ = -40qC
TJ = 25qC
TJ = 125qC
15

D006

Figure 7-5. Converter Startup Current vs VDD Input Voltage

20

25
30
35
40
VDD-RTN Voltage (V)

45

50

55
D007

Figure 7-6. Converter Startup Current vs VDD Input Voltage

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7.7 Typical Characteristics (continued)
13

SST Discharging Current (PA)12.5

VCC Voltage (V)

12
11.5
11
10.5
10
9.5
TJ = -40qC
TJ = 25qC
TJ = 125qC

9
8.5
8
0

3

6

9
12
15
18
21
VCC Sourcing Current (mA)

24

27

30

0

50

D008

Figure 7-7. Converter Startup Voltage vs Current

100 150 200 250 300 350 400
I_STP Programmable Resistance (k:)

450

500
D009

Figure 7-8. Controller SST Soft Stop Sink Current vs
Programmed Resistance
450

3
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2
1.9
1.8
1.7
1.6
1.5

400
Switching Frequency (kHz)VCC Operating Current (mA)

65
60
55
50
45
40
35
30
25
20
15
10
5
0

RFRS = 37.4 k:
RFRS = 60.4 k:
RFRS = 301 k:

RFRS = 37.4 k:
RFRS = 60.4 k:
RFRS = 301 k:

350
300
250
200
150
100
50

9

9.75

10.5

11.25
12
VCC Voltage (V)

12.75

0
-50

13.5

-25

D010

Figure 7-9. Controller Bias Current vs Voltage

0
25
50
75
Junction Temperature (qC)

100

125
D011

Figure 7-10. Switching Frequency vs Temperature
81

800

Maximum Duty Cycle (%)

Switching Frequency (kHz)

80.5
600

400

200

80

RFRS = 37.4 k:
RFRS = 60.4 k:
RFRS = 301 k:

79.5
79
78.5
78
77.5
77
76.5

0
0

5

10
15
20
25
30
35
40
45
Programmable Conductance (106/RFRS (:-1)

50
D012

Figure 7-11. Switching Frequency vs Programmed Resistance

14

76
-50

-25

0
25
50
75
Junction Temperature (qC)

100

125
D013

Figure 7-12. Maximum Duty Cycle vs Temperature

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1.76

24

1.758

23.2

Slope Compensation Current (PA)FB Regulation Voltage (V)7.7 Typical Characteristics (continued)

1.756
1.754
1.752
1.75
1.748
1.746
1.744
1.742
1.74
-50

-25

0
25
50
75
Junction Temperature (qC)

100

21.6
20.8
20
19.2
18.4
17.6
16.8
16
-50

125

0
25
50
75
Junction Temperature (qC)

4
3.6

COMP Sourcing Current (mA)

100

98.5
98
97.5
97
96.5
96
95.5

125
D015

TJ = -40qC
TJ = 25qC
TJ = 125qC

3.2
2.8
2.4
2
1.6
1.2
0.8
0.4

95
-50

0
-25

0
25
50
75
Junction Temperature (qC)

100

125

0

0.5

1

D016

Figure 7-15. Blanking Period vs Temperature

1.5

2
2.5
3
3.5
COMP Voltage (V)

100

18

90

Gain Amplitude (dB)

16
14
12
10
8
6
TJ = -40qC
TJ = 25qC
TJ = 125qC

2
0.8

1.2

1.6
2
2.4 2.8
COMP Voltage (V)

3.2

3.6

70

D019

60
50
40
30
20
10
0

4

-20
100

D020

Figure 7-17. Error Amplifier Sink Current

5

-10

0
0.4

4.5

TJ = -40qC
TJ = 25qC
TJ = 125qC

80

4

4

Figure 7-16. Error Amplifier Source Current

20

0

100

Figure 7-14. Current Slope Compensation Current vs
Temperature

99.5
99

COMP Sinking Current (mA)

-25

D014

Figure 7-13. Feedback Regulation Voltage vs Temperature

Blanking Period (ns)

22.4

1k

10k
100k
Frequency (Hz)

1M

5M
D021

Figure 7-18. Error Amplifier Gain vs Frequency

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7.7 Typical Characteristics (continued)
135
TJ = -40qC
TJ = 25qC
TJ = 125qC

120

Phase Margin (q)

105
90
75
60
45
30
15
0
100

1k

10k
100k
Frequency (Hz)

1M

5M
D022

Figure 7-19. Error Amplifier Phase vs Frequency

16

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8 Detailed Description
8.1 Overview
The TPS23731 device is a 45-pin integrated circuit that contains all of the features needed to implement a single
interface IEEE 802.3bt Type 3 Class 1-4 and IEEE802.3at powered device (PD), combined with a current-mode
DC-DC controller optimized for flyback switching regulator design. The TPS23731 applies to flyback converter
applications, also supporting the use of primary side control.
Basic PoE PD functionality supported includes detection, hardware classification, and inrush current limit during
startup. DC-DC converter features include startup function and current mode control operation. The TPS23731
device integrates a low 0.3-Ω internal switch to minimize heat dissipation and maximize power utilization.
A number of input voltage Oring options or input voltage ranges are also supported by use of APD input.
The TPS23731 device contains several protection features such as thermal shutdown, current limit foldback, anda robust 100-V internal return switch.

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8.2 Functional Block Diagram

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8.3 Feature Description
See Figure 9-1 for component reference designators (RCS for example ), and Electrical Characteristics: DC-DC
Controller Section for values denoted by reference (VCSMAX for example). Electrical Characteristic values takeprecedence over any numerical values used in the following sections.
8.3.1 CLS Classification
An external resistor (RCLS in Figure 9-1 ) connected between the CLS pin and VSS provides a classification
signature to the PSE. The controller places a voltage of approximately 1.25 V across the external resistor
whenever the voltage differential between VPD and VSS lies from about 11 V to 22 V. The current drawn by
this resistor, combined with the internal current drain of the controller and any leakage through the internal pass
MOSFET, creates the classification current. Table 8-1 lists the external resistor values required for each of the
PD power ranges defined by IEEE802.3at. The maximum average power drawn by the PD, plus the power
supplied to the downstream load, should not exceed the maximum power indicated in Table 8-1. The TPS23731
supports class 0 – 4 power levels. Holding APD high disables the classification signatures.
Table 8-1. Class Resistor Selection
CLASS

POWER AT PD PI

RESISTOR (Ω)

MINIMUM (W)

MAXIMUM (W)

0

0.44

12.95

806

1

0.44

3.84

130

2

3.84

6.49

69.8

3

6.49

12.95

46.4

4

12.95

25.5

32

8.3.2 DEN Detection and Enable
DEN pin implements two separate functions. A resistor (RDEN in Figure 9-1) connected between VDD and
DEN generates a detection signature whenever the voltage differential between VDD and VSS lies fromapproximately 1.4 to 10.9 V. Beyond this range, the controller disconnects this resistor to save power. The
IEEE 802.3bt and IEEE 802.3at standards specify a detection signature resistance, Rdetect from 23.75 kΩ to26.25 kΩ, or 25 kΩ ± 5%. TI recommends a resistor of 25.5 kΩ ± 1% for RDEN.
Pulling DEN to VSS during powered operation causes the internal hotswap MOSFET and class regulator
to turn off. If the resistance connected between VDD and DEN is divided into two roughly equal portions,then the application circuit can disable the PD by grounding the tap point between the two resistances, while
simultaneously spoiling the detection signature which prevents the PD from properly re-detecting.
8.3.3 APD Auxiliary Power Detect
The APD pin is used in applications that may draw power either from the Ethernet cable or from an auxiliary
power source. When a voltage of more than about 1.5 V is applied on the APD pin relative to RTN, the
TPS23731 does the following:
•
•
•
•
•

Internal pass MOSFET is turned off
Classification current is disabled
The LINEUV input is disabled
Maintain Power Signature (MPS) pulsed mode is disabled
T2P and APDO outputs are turned on (low state)This also gives adapter source priority over the PoE. A resistor divider (RAPD1–RAPD2 in Figure 9-1) provides
system-level ESD protection for the APD pin, discharges leakage from the blocking diode (DA in Figure 9-1) andprovides input voltage supervision to ensure that switch-over to the auxiliary voltage source does not occur atexcessively low voltages. If not used, connect APD to RTN.

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8.3.4 Internal Pass MOSFET
RTN pin provides the negative power return path for the load. It is internally connected to the drain of the PoE
hotswap MOSFET, and the DC-DC controller return. RTN must be treated as a local reference plane (groundplane) for the DC-DC controller and converter primary to maintain signal integrity.
Once VVDD exceeds the UVLO threshold, the internal pass MOSFET pulls RTN to VSS. Inrush limiting prevents
the RTN current from exceeding a nominal value of about 140 mA until the bulk capacitance (CBULK in Figure9-1) is fully charged. Two conditions must be met to reach the end of inrush phase. The first one is when the
RTN current drops below about 90% of nominal inrush current at which point the current limit is changed to0.925 A, while the second one is to ensure a minimum inrush delay period of 80 ms (tINR_DEL) from beginning of
the inrush phase. DC-DC converter switching is permitted once both inrush conditions are met, meaning that thebulk capacitance is fully charged and the inrush period has been completed.
If VRTN - VVSS ever exceeds about 14.8 V for longer than 1.8 ms, then the PD returns to inrush limiting; notethat in this particular case, the second condition described above about inrush phase duration (80 ms) is notapplicable
8.3.5 T2P and APDO Indicators
The state of T2P is used to provide information relative to the allocated power. Table 8-2 lists T2P statecorresponding to various combinations of PSE Type, PD Class and allocated power. The allocated power isdetermined by the number of classification cycles having been received. The PSE may also allocate a lower
power than what the PD is requesting, in which case there is power demotion. The APDO output can also be
used to indicate the presence of auxiliary power adapter via the APD input.
Table 8-2. T2P and Allocated Power Truth Table, with APD Low(1)

PSE TYPEPD CLASSNUMBER OF CLASSCYCLESPSE ALLOCATED
POWER AT PD (W)

T2P(1)

1-4

0

1

12.95

HIGH

1-4

1

1

3.84

HIGH

1-4

2

1

6.49

HIGH

1-4

3

1

12.95

HIGH

2

4

2

25.5

LOW

3-4

4

2,3

25.5

LOW

If APD is high, both T2P and APDO outputs become low.

During startup, the T2P output is enabled only once the DC-DC controller has reached steady-state, the softstart having been completed. This output will return to a high-impedance state in any of the following cases:••••

DC-DC controller is back to soft-start mode
DC-DC controller transitions to soft-stop mode
DC-DC controller shuts off due to reasons including VVCC falling below VCUVLO_F, or the PoE hotswap is ininrush limit while APD is low
The device enters thermal shutdown

Note that in all these cases, as long as VDD-to-VSS voltage remains above the mark reset threshold, theinternal logic state of this signal is remembered such that this output will be activated accordingly after thesoft-start has completed. This circuit resets when the VDD-to-VSS voltage drops below the mark reset threshold.
The T2P can be left unconnected if not used.
8.3.6 DC-DC Controller Features
The TPS23731 device DC-DC controller implements a typical current-mode control as shown in Functional Block
Diagram. Features include oscillator, overcurrent and PWM comparators, current-sense blanker, soft-start, softstop and gate driver. In addition, an internal current-compensation ramp generator, frequency synchronization
logic, built-in frequency dithering functionality, thermal shutdown, and start-up current source with control areprovided.

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The TPS23731 is optimized for isolated converters, supporting the use of PSR (flyback configuration) and
optocoupler feedback .
To support PSR, the TPS23731 includes an internal error amplifier, and the voltage feedback is from the bias
winding.
If optocoupler feedback is used, the error amplifier is disabled (by use of EA_DIS input). In this case, theoptocoupler output directly drives the COMP pin which serves as a current-demand control to the PWM.
In both cases, the COMP signal is directly fed to a 5:1 internal resistor divider and an offset of VZDC/5 (~0.3
V) which defines a current-demand control for the pulse width modulator (PWM). A VCOMP below VZDC stops
converter switching, while voltages above (VZDC + 5 × (VCSMAX + VSLOPE)) does not increase the requested peakcurrent in the switching MOSFET.
The internal start-up current source and control logic implement a bootstrap-type startup. The startup current
source charges CVCC from VDD and maintain its voltage when the converter is disabled or during the soft-start
period, while operational power must come from a converter (bias winding) output.
The bootstrap source provides reliable start-up from widely varying input voltages, and eliminates the continual
power loss of external resistors.
The peak current limit does not have duty cycle dependency unless RS is used as shown in Figure 8-2 toincrease slope compensation. This makes it easier to design the current limit to a fixed value.
The DC-DC controller has an OTSD that can be triggered by heat sources including the VB regulator, GATE
driver, bootstrap current source, and bias currents. The controller OTSD turns off VB, the switching FET, resets
the soft-start generator, and forces the VCC control into an undervoltage state.
8.3.6.1 VCC, VB, VBG and Advanced PWM Startup
The VCC pin connects to the auxiliary bias supply for the DC-DC controller. The switching MOSFET gate driverdraws current directly from the VCC pin. VB and VBG outputs are regulated down from VCC voltage, theformer providing power to the internal control circuitry and external feedback optocoupler (when in use), andthe latter providing power to the switching FET gate predriver circuit. A startup current source from VDD to
VCC implements the converter bootstrap startup. VCC must receive power from an auxiliary source, such as an
auxiliary winding on the flyback transformer, to sustain normal operation after startup.
The startup current source is turned on during the inrush phase, charging CVCC and maintaining its voltage,and it is turned off only after the DC-DC soft-start cycle has been completed, which occurs when the DC-DC
converter has ramped up its output voltage and VSST has exceed approximately 2.1 V (VSTUOF), as shown in
Figure 8-1. Internal loading on VCC, VB and VBG is initially minimal while CVCC charges, to allow the converter
to start. Due to the high current capability of the startup source, the recommended capacitance at VCC isrelatively small, typically 1 μF in most applications.
Once VVCC falls below its UVLO threshold (VCUVLO_F, approximately 6.1 V), the converter shuts off and thestartup current source is turned back on, initiating a new PWM startup cycle.
If however a VVCC fall (below approximately 7.1 V) is due to a light load condition causing temporary switchingstop, the startup is immediately and for a short period turned back on to bring VCC voltage back up, with noconverter interruption.

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tinrush max
PSE

Operational Mode

PSE Inrush
tinrush min

PD

VCC Startup Source ON

End of Soft-Start, Startup source
turned off
PD + Power Supply Fully
Operational

HSW cap
recharge

Wait Soft Start

High current startup is ON for the whole soft-start
cycle to allow low VCC capacitance

Ensures interoperability with
PSE inrush limit

Figure 8-1. Advanced Startup
Note that the startup current source is also turned on while in soft-stop mode.
8.3.6.2 CS, Current Slope Compensation and blanking
The current-sense input for the DC-DC converter should be connected to the high side of the current-sense
resistor of the switching MOSFET. This voltage drives the current limit comparator and the PWM comparator(see Block Diagram of DC-DC controller). A leading-edge blanking circuit prevents MOSFET turn-on transientsfrom falsely triggering either of these comparators. During the off time, and also during the blanking time that
immediately follows, the CS pin is pulled to AGND through an internal pulldown resistor.
The current limit comparator terminates the on-time portion of the switching cycle as soon as VCS exceeds
approximately 250 mV (VCSMAX) and the leading edge blanking interval has expired. If the converter is not incurrent limit, then either the PWM comparator or the maximum duty cycle limiting (DMAX) circuit terminates theon time.
Current-mode control requires addition of a compensation ramp to the sensed inductive (transformer or inductor)
current for stability at duty cycles near and over 50%. The TPS23731 provides an internal slope compensation
circuit which generates a current that imposes a voltage ramp at the positive input of the PWM comparator tosuppress sub-harmonic oscillations. This current flows out of the CS pin. If desired, the magnitude of the slope
compensation can be increased by the addition of an external resistor RS (see Figure 8-2) in series with the CS
pin. It works with ramp current (IPK = ISL-EX, approximately 20 μA) that flows out of the CS pin when the MOSFET
is on. The IPK specification does not include the approximately 2-μA fixed current that flows out of the CS pin.
The TPS23731 has a maximum duty cycle limit of 78%, permitting the design of wide input-range converters
with a lower voltage stress on the output rectifiers. While the maximum duty cycle is 78%, converters may bedesigned that run at duty cycles well below this for a narrower, 36-V to 57-V range.
Most current-mode control papers and application notes define the slope compensation values in terms of
VPP/TS (peak ramp voltage / switching period); however, Electrical Characteristics: DC-DC Controller Section
specifies the slope peak (VSLOPE) based on the maximum duty cycle. Assuming that the desired slope, VSLOPE-D(in mV/period), is based on the full period, compute RS per Equation 1 where VSLOPE, DMAX, and ISL-EX are from
Electrical Characteristics: DC-DC Controller Section with voltages in mV, current in μA, and the duty cycle isunitless (for example, DMAX = 0.78).
R S :3; =

22

V
(mV)
WD
BVSLOP E_D :mV; F @ SLOPE
ISL_EX (JA)

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AC

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AGND
GND

RTN

GATE

CS
RS
CS

RCS

Figure 8-2. Additional Slope Compensation
The TPS23731 blanker timing is precise enough that the traditional R-C filters on CS can be eliminated. Thisavoids current-sense waveform distortion, which tends to get worse at light output loads. There may be somesituations or designers that prefer an R-C approach, for example if the presence of RS causes increased noise,due to adjacent noisy signals, to appear at CS pin. The TPS23731 provides a pulldown on CS (~400 Ω) during
the GATE OFF-time to improve sensing when an R-C filter must be used, by reducing cycle-to-cycle carry-overvoltage on CS.
Routing between the current-sense resistor and the CS pin should be short to minimize cross-talk from noisy
traces such as the gate drive signal and the CP signal.
8.3.6.3 COMP, FB, EA_DIS, CP, PSRS and Opto-less Feedback
The TPS23731 DC-DC controller implements current-mode control as shown in Functional Block Diagram, using
internal (via pins FB input and COMP output, with EA_DIS pulled low) or external (via COMP input, with EA_DIS
open) voltage control loop error amplifier to define the input reference voltage of the current mode control
comparator which determines the switching MOSFET peak current.
VCOMP below VZDC causes the converter to stop switching. The maximum (peak) current is requested at
approximately (VZDC + 5 × (VCSMAX + VSLOPE)). The AC gain from COMP to the PWM comparator is typically 0.2.
In flyback applications and with the internal error amplifier enabled, the TPS23731 DC-DC controller can operatewith feedback from an auxiliary winding of the flyback power transformer to achieve primary side regulation(PSR), eliminating the need for external shunt regulator and optocoupler. One noteworthy characteristic of thisPSR is that it operates with continuous (DC) feedback, enabling better optimization of the power supply, andresulting in significantly lower noise sensitivity.
When combined with secondary-side synchronous rectification (with PSRS open), the opto-less operation of
the TPS23731 is achieved with a unique approach which basically consists in actively cancelling (throughthe use of CP output) the leading-edge voltage overshoot (causing the feedback capacitor to peak-charge)
generated by the transformer winding. When combined with a correctly designed power transformer, less than
±1.5% load regulation (typical) over the full output current range becomes achievable in applications making
use of secondary-side synchronous rectifiers. Operation is in continuous conduction mode (CCM), also enabling
multi-output architectures.
Opto-less operation of the TPS23731 also applies (with PSRS pulled low) to single-output flyback converter
applications where a secondary-side diode rectifier is used. In typical 12-V output application and whencombined with a correctly designed power transformer, ~±3% load regulation over a wide (< 5% to 100%)
output current range can be achieved.
In applications where the internal error amplifier is disabled, the COMP pin receives the control voltage typicallyfrom a TL431 or TLV431 shunt regulator driving an optocoupler, using VB pin as a pull up source, although otherconfigurations are possible.

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8.3.6.4 FRS Frequency Setting and Synchronization
The FRS pin programs the (free-running) oscillator frequency, and may also be used to synchronize the
TPS23731 converter to a higher frequency. The internal oscillator sets the maximum duty cycle and controls thecurrent-compensation ramp circuit, making the ramp height independent of frequency. RFRS must be selected
per Equation 2.
R FRS (k3) =15000
fSW (kHz)(2)

The TPS23731 may be synchronized to an external clock to eliminate beat frequencies from a sampled system,or to place emission spectrum away from an RF input frequency. Synchronization may be accomplishedby applying a short pulse ( > 25 ns) of magnitude VSYNC to FRS as shown in Figure 8-3. RFRS must be
chosen so that the maximum free-running frequency is just below the desired synchronization frequency. The
synchronization pulse terminates the potential ON-time period, and the OFF-time period does not begin until thepulse terminates. A short pulse is preferred to avoid reducing the potential ON-time.

TSYNC

RFRS

FRS
47pF

TSYNC

1000pF

VSYNC

RTN

47pF

Synchronization
Pulse

RFRS

FRS

RT

Synchronization
Pulse

RTN

Figure 8-3 shows examples of nonisolated and transformer-coupled synchronization circuits. RT reduces noise
susceptibility for the isolation transformer implementation. The FRS node must be protected from noise because
it is high impedance.

1:1

VSYNC

Copyright © 2016, Texas Instruments Incorporated

Figure 8-3. Synchronization
8.3.6.5 DTHR and Frequency Dithering for Spread Spectrum Applications
The international standard CISPR 22 (and adopted versions) is often used as a requirement for conductedemissions. Ethernet cables are covered as a telecommunication port under section 5.2 for conducted emissions.
Meeting EMI requirements is often a challenge, with the lower limits of Class B being especially hard. Circuitboard layout, filtering, and snubbing various nodes in the power circuit are the first layer of control techniques.
A more detailed discussion of EMI control is presented in Practical Guidelines to Designing an EMI Compliant
PoE Powered Device With Isolated Flyback, SLUA469. Additionally, IEEE 802.3at sections 33.3 and 33.4 andIEEE 802.3bt sections 145.3 and 145.4 have requirements for noise injected onto the Ethernet cable based oncompatibility with data transmission.
A technique referred to as frequency dithering can also be used to provide additional EMI measurement
reduction. The switching frequency is modulated to spread the narrowband individual harmonics across a wider
bandwidth, thus lowering peak measurements.
Fully programmable frequency dithering is a built-in feature of the TPS23731. The oscillator frequency can bedithered by connecting a capacitor from DTHR to RTN and a resistor from DTHR to FRS. An external capacitor,
CDTR (Figure 9-1), is selected to define the modulation frequency fm. This capacitor is being continuously
charged and discharged between slightly less than 0.5 V and slightly above 1.5 V by a current source/sink
equivalent to ~3x the current through FRS pin. CDTR value is defined according to:3W
R FRS (3)
CDTR =
2.052 × fm (Hz)24

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fm should always be higher than 9 kHz, which is the resolution bandwidth applied during conducted emission
measurement. Typically, fm should be set to around 11 kHz to account for component variations.
The resistor RDTR is used to determine ∆f, which is the amount of dithering, and its value is determinedaccording to:
R DTR (3) =0.513 × R FRS (3)
%DTHR

(4)

For example, a 13.2% dithering with a nominal switching frequency of 250 kHz results in frequency variation of±33 kHz.
8.3.6.6 SST and Soft-Start of the Switcher
Converters require a soft-start to prevent output overshoot on startup. In PoE applications, the PD also needs
soft-start to limit its input current at turn on below the limit allocated by the power source equipment (PSE).
For flyback applications using primary-side control, the TPS23731 provides closed loop controlled soft-start,
which applies a slowly rising ramp voltage to a second control input of the error amplifier. The lower of thereference input and soft-start ramp controls the error amplifier, allowing the output voltage to rise in a smoothmonotonic fashion.
In all other applications where secondary-side regulation is used, the TPS23731 provides a current-loop
soft-start, which controls the switching MOSFET peak current by applying a slowly rising ramp voltage to asecond PWM control input. The lower of COMP-derived current demand and soft-start ramp controls the PWM
comparator. Note that in this case there is usually a (slower) secondary-side soft-start implemented with thetypical TL431 or TLV431 error amplifier to complement the action of the primary-side soft-start.
The soft-start period of the TPS23731 is adjustable with a capacitor between SST and RTN. During soft-start,
CSST (Figure 9-1) is being charged from less than 0.2 V to 2.45 V by a ~10µA current source. Once VSST has
exceeded approximately 2.1 V (VSTUOF), the VCC startup is also turned off.
The actual control range of the primary-side closed-loop soft-start capacitor voltage is between 0.25V and2V nominally. Therefore, the soft-start capacitor value must be based on this control range and the required
soft-start period (tSS) according to:
CSS (nF) =ISSC :JA; x t SS (ms)(2 F 0.25)(5)

The actual control range of the current-loop soft-start capacitor voltage is between 0.6V and 1.2V nominally.
Therefore, the soft-start capacitor value must be based on this control range and the required soft-start period(tSS) according to:
CSS (nF) =ISSC :JA; x t SS (ms)(1.2 F 0.6)(6)Note that the VCC startup turns off only when 2.1 V is reached, allowing additional time for the secondary-sidesoft-start to complete. For more details regarding the secondary-side soft start, refer to Application Information.
8.3.6.7 SST, I_STP, LINEUV and Soft-Stop of the Switcher
The soft-stop feature is provided by the TPS23731 to minimizes stress on switching power components causedby power shutdown, allowing FET BOM cost reduction. Soft-stop action consists in discharging in a controlled
way the output capacitor of the converter, sending back the energy to the input bulk capacitor.
Once the LINEUV input detects that the input power source has been removed (while APD is also low), the SST
capacitor is discharged with a constant current, ramping down the switching MOSFET peak current. The SST
discharge current (ISSD_SP) is defined with RI_STP according to:
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ISS D_SP (JA) =1000
R I_STP :kÀ;(7)

To accelerate the impact of the soft-stop, the internal peak current limit threshold is also immediately stepped
down to approximately 50 mV at beginning of soft-stop.
8.3.7 Switching FET Driver - GATEGATE is the gate drive outputs for the DC-DC converter's main switching MOSFET.
GATE's phase turns the main switch on when it transitions high, and off when it transitions low. It is also held low
when the converter is disabled.
8.3.8 EMPS and Automatic MPS
To maintain PSE power in situation of very low IRTN condition, the TPS23731 generates a pulsed current throughVSS pin with an amplitude adjusted such that its net current reaches a level high enough to maintain power.
The pulsed current amplitude (IMPSL, IMPSH) and duration (tMPSL, tMPSH) are automatically selected according to
PSE Type (1-2, 3-4), to maintain PSE power while minimizing power consumption. Auto-stretch feature is also
used to cancel the impact of system conditions (bulk capacitance and PoE cable impedance) on the effective
pulsed current duration. See Figure 8-4, where the illustrated pulsed current is coming out of the VSS pin, while
ILOAD is the DC current going into the RTN pin.
TMPS

Pulse
Stretching

IEEE IHold

ILoad

IEEE IHold

TMPS

0 mA
Unloaded power
supplyMeasured IVSS
Adds only the extra current to reach IHold

Stretches the pulse if necessary based on measured current

Figure 8-4. Auto MPS
Note that prior to entering the MPS mode, a light load condition is detected on RTN pin with a deglitch time
period of approximately 5 ms.
8.3.9 VDD Supply Voltage
VDD connects to the positive side of the input supply. It provides operating power to the PD controller, allows
monitoring of the input line voltage and serves as the source of DC-DC converter startup current. If VVDD falls
below its UVLO threshold and goes back above it, or if a thermal shutdown resumes even if VVDD remains above
its UVLO threshold, the TPS23731 returns to inrush phase.
8.3.10 RTN, AGND, GND
RTN is internally connected to the drain of the PoE hotswap MOSFET, while AGND is the quiet analog reference
for the DC-DC controller return. GND is the power ground used by the flyback power FET gate driver and CP
output, and should be tied to AGND and RTN plane. The AGND / GND / RTN net should be treated as a local
reference plane (ground plane) for the DC-DC control and converter primary. The PAD_G exposed thermal pad
is internally connected to RTN pin.
8.3.11 VSS
VSS is the PoE input-power return side. It is the reference for the PoE interface circuits, and has a currentlimited hotswap switch that connects it to RTN. VSS is clamped to a diode drop above RTN by the hotswap
switch. The PAD_S exposed thermal pad is internally connected to VSS pin. This pad must be connected to VSS
pin to ensure proper operation.

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8.3.12 Exposed Thermal pads - PAD_G and PAD_S
PAD_G should be tied to a large RTN copper area on the PCB to provide a low resistance thermal path to thecircuit board.
PAD_S should be tied to a large VSS copper area on the PCB to provide a low resistance thermal path to thecircuit board. TI recommends maintaining a clearance of 0.025” between VSS and high-voltage signals such as
VDD.

8.4 Device Functional Modes
8.4.1 PoE Overview
The following text is intended as an aid in understanding the operation of the TPS23731, but it is not a substitutefor the actual IEEE 802.3bt or 802.3at standards. The IEEE 802.3bt standard is an update to IEEE 802.3-2018,
adding Clause 145 (PoE), including power delivery using all four pairs, high-power options, additional features toreduce standby power consumption and enhanced classification.
Generally speaking, a device compliant to IEEE 802.3-2012 is referred to as a Type 1 (Class 0-3) or 2 (Class4) device, and devices with higher power and enhanced classification is referred to as Type 3 (Class 5, 6) or
4 (Class 7, 8) devices. Type 3 devices will also include Class 0-4 devices that are 4-pair capable. Standards
change and must always be referenced when making design decisions.
The IEEE 802.3at and 802.3bt standards define a method of safely powering a PD (powered device) over a
cable by power sourcing equipment (PSE), and then removing power if a PD is disconnected. The processproceeds through an idle state and three operational states of detection, classification, and operation. Thereis also a fourth operational state used by Type 3 and 4 PSEs, called "connection check", to determine if the
PD has same (single interface) or independent (dual interface or commonly referred to "dual-signature" in the
IEEE802.3bt standard) classification signature on each pairset. The PSE leaves the cable unpowered (idle state)while it periodically looks to see if something has been plugged in; this is referred to as detection. The low power
levels used during detection and connection check are unlikely to damage devices not designed for PoE. If avalid PD signature is present, the PSE may inquire how much power the PD requires; this is referred to asclassification. The PSE may then power the PD if it has adequate capacity.
Type 3 or Type 4 PSEs are required to do an enhanced hardware classification of Type 3 or 4 respectively. Type
2 PSEs are required to do Type 1 hardware classification plus a data-layer classification, or an enhanced Type2 hardware classification. Type 1 PSEs are not required to do hardware or data link layer (DLL) classification. A
Type 3 or Type 4 PD must do respectively Type 3 or Type 4 hardware classification as well as DLL classification.
A Type 2 PD must do Type 2 hardware classification as well as DLL classification. The PD may return thedefault, 13-W current-encoded class, or one of four other choices if Type 2, one of six other choices if Type 3,
and one of eight other choices if Type 4. DLL classification occurs after power-on and the Ethernet data link has
been establishedOnce started, the PD must present the maintain power signature (MPS) to assure the PSE that it is still present.
The PSE monitors its output for a valid MPS, and turns the port off if it loses the MPS. Loss of the MPS returns
the PSE to the idle state. Figure 8-5 shows the operational states as a function of PD input voltage.

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Normal Operation
42.5

6.9

0
2.7

10.1

14.5

20.5

30

37

57 PI Voltage (V)42Normal Operation
250Ps
TransientClass-Mark
Transition

Lower Limit 13W Op.

Mark
T2 Reset
Range

Maximum Input
VoltageMust Turn On byVoltage Rising

Shutdown

Classify

DetectLower Limit Operating Range

Must Turn Off by Voltage FallingClassification
Upper Limit

Classification
Lower Limit

Detection
Upper Limit

Detection
Lower LimitSLVSER7 – OCTOBER 2020

Figure 8-5. Operational States
The PD input, typically an RJ-45 eight-lead connector, is referred to as the power interface (PI). PD input
requirements differ from PSE output requirements to account for voltage drops and operating margin. The
standard allots the maximum loss to the cable regardless of the actual installation to simplify implementation.
IEEE 802.3-2008 was designed to run over infrastructure including ISO/IEC 11801 class C (CAT3 per TIA/
EIA-568) that may have had AWG 26 conductors. IEEE 802.3at Type 2 and IEEE 802.3bt Type 3 cabling power
loss allotments and voltage drops have been adjusted for 12.5-Ω power loops per ISO/IEC11801 class D (CAT5or higher per TIA/EIA-568, typically AWG 24 conductors). Table 8-3 shows key operational limits broken out for
the two revisions of the standard.
Table 8-3. Comparison of Operational Limits
STANDARD

POWER LOOPRESISTANCE(MAX)

PSE OUTPUT
POWER (MIN)PSE STATIC OUTPUT
VOLTAGE (MIN)

STATIC PD INPUT VOLTAGEPD INPUTPOWER (MAX)

POWER ≤ 13 W

POWER > 13 W

13 W

37 V – 57 V

N/A

25.5 W

37 V – 57 V

42.5 V – 57 V

IEEE802.3-2012
802.3at (Type 1)

20 Ω

802.3bt (Type 3)

12.5 Ω

802.3at (Type 2)
802.3bt (Type 3)

12.5 Ω

30 W

50 V

802.3bt (Type 3)

6.25 Ω (4-pair)

60 W

50 V

51 W

N/A

42.5 V - 57 V

802.3bt (Type 4)

6.25 Ω (4-pair)

90 W

52 V

71.3 W

N/A

41.2 V - 57 V

15.4 W

44 V
50 V

The PSE can apply voltage either between the RX and TX pairs (pins 1–2 and 3–6 for 10baseT or 100baseT),or between the two spare pairs (4–5 and 7–8). Power application to the same pin combinations in 1000/2.5G/5G/
10GbaseT systems is recognized in IEEE 802.3bt. 1000/2.5G/5G/10GbaseT systems can handle data on all
pairs, eliminating the spare pair terminology. Type 1 and 2 PSEs are allowed to apply voltage to only one set ofpairs at a time, while Type 3 and 4 PSEs may apply power to one or both sets of pairs at a time. The PD uses
input diode or active bridges to accept power from any of the possible PSE configurations. The voltage drops
associated with the input bridges create a difference between the standard limits at the PI and the TPS23731
specifications.
A compliant Type 2, 3 or 4 PD has power management requirements not present with a Type 1 PD. These
requirements include the following:
1. Must interpret respectively Type 2, 3 or 4 hardware classification.
2. Must present hardware Class 4 during the first two classfication events, applicable to Type 2 and 4 PDs, aswell as to Type 3 PD with Class level 4 or higher.
3. If Type 3 Class 5-6 or Type 4 single interface PD, it must present hardware Class in the range of 0 to 3
during the third and any subsequent classification events.
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4. Must implement DLL negotiation.
5. Must draw less than 400 mA from 50 ms until 80 ms after the PSE applies operation voltage (power up), if
Type 2 or 3, single interface PD. This covers the PSE inrush period, which is 75 ms maximum.
6. Must draw less than 800 mA total and 600 mA per pairset from 50 ms until 80 ms after the PSE applies
operation voltage (power up), if Type 4 (Class 7-8) single interface PD.
7. Must not draw more than 60 mA and 5 mA any time the input voltage falls below respectively 30 V and 10 V.
8. Must not draw more than 13 W if it has not received at least a Type 2 hardware classification or received
permission through DLL.
9. Must not draw more than 25.5 W if it has not received at least 4 classification events or received permission
through DLL.
10. Must not draw more than 51 W if it has not received at least 5 classification events or received permission
through DLL.
11. Must meet various operating and transient templates.
12. Optionally monitor for the presence or absence of an adapter.
As a result of these requirements, the PD must be able to dynamically control its loading, and monitor T2P forchanges. APDO can also be used in cases where the design needs to know specifically if an adapter is plugged
in and operational.
8.4.2 Threshold Voltages
The TPS23731 has a number of internal comparators with hysteresis for stable switching between the various
states as shown in Figure 8-5. Figure 8-6 relates the parameters in Electrical Characteristics PoE to the PoE
states. The mode labeled idle between classification and operation implies that the DEN, CLS, and RTN pins are
all high impedance. The state labeled Mark, which is drawn in dashed lines, is part of the Type 2-3-4 hardware
class state machine.

Functional
State

PD Powered
Idle
ClassificationMark

VDD-VSS

Detection
VCL_H
VMSR

VCL_ONVCU_H

VUVLO_H

VCU_OFFVUVLO_R

Note: Variable names refer to Electrical Characteristic
Table parameters

Figure 8-6. Threshold Voltages
8.4.3 PoE Start-Up Sequence
The waveforms of Figure 8-7 demonstrate detection, classification, and start-up from a Type 2 PSE with Class
4 hardware classification. The key waveforms shown are VVDD-VSS, VRTN-VSS, and IPI. IEEE802.3bt and IEEE
802.3at require a minimum of two detection levels; however, four levels are shown in this example. Four levels
guard against misdetection of a device when plugged in during the detection sequence.
VRTN to VSS falls as the TPS23731 charges CBULK following application of full voltage. In Figure 8-9, theconverter soft-start is also delayed until the end of inrush period.

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DC-DC enabled afterStartup delay
InrushIPI

Voltage: 10V/div

VVDD-VSSClass Mark
Detect
VRTN-VSS

Time: 50ms/div
Figure 8-7. PoE Start-Up Sequence
8.4.4 Detection
The TPS23731 is in detection mode whenever VVDD-V SS is below the lower classification threshold. When the
input voltage rises above VCL_ON, the DEN pin goes to an open-drain condition to conserve power. While indetection, RTN is high impedance, almost all the internal circuits are disabled, and the DEN pin is pulled to VSS.
An RDEN of 25.5 kΩ (1%), presents the correct signature. It may be a small, low-power resistor because it only
sees a stress of about 5 mW. A valid PD detection signature is an incremental resistance between 23.75 kΩ and26.25 kΩ at the PI.
The detection resistance seen by the PSE at the PI is the result of the input bridge resistance in series withthe parallel combination of RDEN and the TPS23731 bias loading. The incremental resistance of the input diodebridge may be hundreds of ohms at the very low currents drawn when 2.7 V is applied to the PI. The input bridge
resistance is partially cancelled by the effective resistance of the TPS23731 during detection.
8.4.5 Hardware Classification
Hardware classification allows a PSE to determine a PD’s power requirements before powering, and helps withpower management once power is applied. Type 2, 3, and 4 hardware classification permits high power PDs todetermine whether the PSE can support its high-power operation. The number of class cycles generated by thePSE prior to turn on indicates to the PD if it allots the power requested or if the allocated power is less thanrequested, in which case there is power demotion.
A Type 2 PD always presents Class 4 in hardware to indicate that it is a 25.5W device. A Class 5 or 6 Type
3 PD presents Class 4 in hardware during the first two class events and it presents Class 0 or 1, respectively,
for all subsequent class events. A Class 7 or 8 Type 4 PD presents Class 4 in hardware during the first twoclass events and it presents Class 2 or 3, respectively, for all subsequent class events. A Type 1 PSE will treat
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a Class 4 to 8 device like a Class 0 device, allotting 13 W if it chooses to power the PD. A Type 2 PSE will treata Class 5 to 8 device like a Class 4 device, allotting 25.5W if it chooses to power the PD. A Class 4 PD thatreceives a 2-event class, a Class 5 or 6 PD that receives a 4-event class, or a Class 7 or 8 PD that receives
a 5-event class, understands that the PSE has agreed to allocate the PD requested power. In the case where
there is power demotion, the PD may choose to not start, or to start while not drawing more power than initiallyallocated, and request more power through the DLL after startup. The standard requires a Type 2, 3 or 4 PD
to indicate that it is underpowered if this occurs. Startup of a high-power PD at lower power than requested
implicitly requires some form of powering down sections of the application circuits.
The maximum power entries in Table 8-1 determine the class the PD must advertise. The PSE may disconnect
a PD if it draws more than its stated class power, which may be the hardware class or a DLL-derived power
level. The standard permits the PD to draw limited current peaks that increase the instantaneous power above
the Table 8-1 limit; however, the average power requirement always applies.
The TPS23731 implements one- to two-event classification. RCLS resistor value defines the class of the PD. DLL
communication is implemented by the Ethernet communication system in the PD and is not implemented by the
TPS23731.
The TPS23731 disables classification above VCU_OFF to avoid excessive power dissipation. CLS voltage isturned off during PD thermal limiting or when APD or DEN is active. The CLS output is inherently current-limited,
but should not be shorted to VSS for long periods of time.
Figure 8-8 shows how classification works for the TPS23731. Transition from state-to-state occurs whencomparator thresholds are crossed (see Figure 8-5 and Figure 8-6). These comparators have hysteresis,
which adds inherent memory to the machine. Operation begins at idle (unpowered by PSE) and proceeds withincreasing voltage from left to right. A 2-event classification follows the (heavy lined) path towards the bottom,
ending up with a low T2P along the lower branch that is highlighted. Once the valid path to the PSE detection isbroken, the input voltage must transition below the mark reset threshold to start anew.

Idle

Detect

Mark
Reset

Mark

Class

BetweenRangesClass

BetweenRangesClass

UVLO
Falling

UVLO
RisingOperatingT2P
open-drain

TYPE 1 or 3 PSE
Hardware Class

BetweenRangesPoE Startup Sequence
Mark

Class

BetweenRangesTYPE 2 or 3 PSE
Hardware ClassUVLO
RisingOperating
T2P low

UVLO
Falling

Figure 8-8. Up to Two-Event Class Internal States
8.4.6 Maintain Power Signature (MPS)The MPS is an electrical signature presented by the PD to assure the PSE that it is still present after operating
voltage is applied. For a Type 1 or Type 2 PD, a valid MPS consists of a minimum dc current of 10 mA, or a
10-mA pulsed current for at least 75 ms every 325 ms, and an AC impedance lower than 26.3 kΩ in parallel with

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0.05 μF. Only Type 1 and Type 2 PSEs monitor the AC MPS. A Type 1 or Type 2 PSE that monitors only the AC
MPS may remove power from the PD.
To enable applications with stringent standby requirements, IEEE802.3bt introduced a significant change
regarding the minimum pulsed current duration to assure the PSE will maintain power. This applies to all Type 3
and Type 4 PSEs, and the pulse duration is ~10% of what is required for Type 1 and 2 PSEs. The MPS current
amplitude requirement for Class 5-8 PDs have also increased to 16 mA at the PSE end of the ethernet cable.
If the current through the RTN-to-VSS path is very low, the TPS23731 automatically generates the MPS
pulsed current through the VSS pin, with an amplitude adjusted such that its net current reaches a levelhigh enough to maintain PSE power. The TPS23731 is also able to determine if the PSE is of Type 1-2 orType 3-4, automatically adjusting the pulsed current amplitude, duration and duty-cycle, while minimizing power
consumption. Note that the IEEE802.3bt requirement for the PD is applicable at the PSE end of the cable.
That means that depending the cable length and other parameters including the bulk capacitance, a longer
pulse duration may be required to ensure a valid MPS. For that purpose, the TPS23731 provides auto-stretch
capability which is used to cancel the impact of such system conditions on the effective pulsed current duration.
See Figure 8-4.
When APD is pulled high or when DEN is pulled to VSS (forcing the hotswap switch off), the DC MPS will not be
met. A PSE that monitors the DC MPS will remove power from the PD when this occurs.
8.4.7 Advanced Start-Up and Converter Operation
The internal PoE undervoltage lockout (UVLO) circuit holds the hotswap switch off before the PSE provides
full voltage to the PD. This prevents the converter circuits from loading the PoE input during detection andclassification. The converter circuits discharges CBULK, CVCC, CVB and CVBG while the PD is unpowered. Thus
VVDD-RTN will be a small voltage until just after full voltage is applied to the PD, as seen in Figure 8-7.
The PSE drives the PI voltage to the operating range once it has decided to power up the PD. When VVDD
rises above the UVLO turnon threshold (VUVLO-R, approximately 37.6 V) with RTN high, the TPS23731 enables
the hotswap MOSFET with an approximately 140-mA (inrush) current limit. See the waveforms of Figure 8-9
for an example. Converter switching is disabled while CBULK charges and VRTN falls from VVDD to nearly VVSS;
however, the converter start-up circuit is allowed to charge CVCC (the VB regulator also powers the internalconverter circuits as VVCC rises). Once the inrush current falls about 10% below the inrush current limit, thePD current limit switches to the operational level (approximately 925 mA). Additionally, once the inrush period
duration has also exceeded approximately 84 ms (end of inrush phase), the converter switching is allowed tostart, once VVCC also goes above its UVLO (approximately 8.25 V).
Continuing the start-up sequence shown in Figure 8-9, once VVCC goes above its UVLO , the soft-start (SST)
capacitor is first discharged with controlled current (ISSD) below nominally 0.2 V (VSFST) if the discharge was notalready completed, then it is gradually recharged until it reaches ~0.25 V (VSSOFS in closed-loop mode) at which
point the converter switching is enabled, following the closed loop controlled soft-start sequence. Note that thestartup current source capability is such that it can fully maintain VVCC during the converter soft-start without
requiring any significant CVCC capacitance, in 48 V input applications. At the end of the soft-start period, more
specifically when SST voltage has exceeded ~2 V (VSTUOF), the startup current source is turned off. VVCC falls
as it powers the internal circuits including the switching MOSFET gate. If the converter control-bias output rises
to support VVCC before it falls to VCUVLO_F (~6.1 V), a successful start-up occurs. Figure 8-9 shows a small droop
in VVCC while the output voltage rises smoothly and a successful start-up occurs.
Figure 8-10 also illustrates similar scenario if optocoupler feedback is used instead of PSR. In this case, theconverter switching is enabled when VSST exceeds approximately 0.6 V (VSSOFS in peak current mode).

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50V/div

VVDD-RTN
Converter
startsPI powered
Inrush

100mA/div

IPI

VVCC-RTN

Startup turn off,
T2P enabled

5V/div
5V/div

VOUT

Output Voltage

Inrush Delay

1V/div

VSST

Soft Start

Time: 20ms/div
Figure 8-9. Power Up and Start - Flyback with PSR

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50V/div

VVDD-RTN
Converter
startsPI powered
Inrush

100mA/div

IPI

VVCC-RTN
Startup turn off

5V/div
5V/div

VOUT

SecondarySoft Start
dependent

Output Voltage

Inrush Delay

1V/divPrimary Ipeak
Soft Start

VSST

Time: 20ms/div
Figure 8-10. Power Up and Start - with Opto Feedback
The converter shuts off when VVCC falls below its lower UVLO. This can happen when power is removed fromthe PD, or during a fault on a converter output rail. When one output is shorted, all the output voltages fall
including the one that powers VCC. The control circuit discharges VCC until it hits the lower UVLO and turns
off. A restart initiates if the converter turns off and there is sufficient VDD voltage. This type of operation issometimes referred to as hiccup mode, which when combined with the soft-start provides robust output shortprotection by providing time-average heating reduction of the output rectifier.
Figure 8-11 illustrates the situation when there is severe overload at the main output which causes VCC hiccup.
After VCC went below its UVLO due to the overload, the startup source is turned back on. Then, a new soft-start
cycle is reinitiated, the soft-start capacitor being first discharged with controlled current, introducing a shortpause before the output voltage is ramped up.

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VOUT overload
Converter
Turn off then restart
IPI

200mA/div
Startup turn off
VVCC-RTN
VCC
UVLO

5V/div

VSST

1V/div

5V/div

Soft Start

Output Voltage

VOUT

Time: 10ms/div
Figure 8-11. Restart Following Severe Overload at Main Output of PSR Flyback DC-DC Converter
Also, when a VCC fall occurs, the TPS23731 can differentiate between an overload and a light load condition.
For example a diode-rectified flyback with optocoupled feedback may have its VCC rail to fall in situation of lightload due to temporary switching stop. In this case, the output voltage has to be maintained and a soft-start would
not be acceptable. To address this case, if VVCC falls below approximately 7.1 V due to light load, the TPS23731
turns back on the startup immediately and for a short period of time to bring VCC voltage back up, and there is
no soft-start recycling.

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IOUT

VVCC-RTN

Startup turn on then off
VCUVStartup turn on
for short time

5V/div

10V/div

VOUT

VCC falls due toswitching interruption
at light load

Vout is maintained, no soft
start recycling

Time: 10ms/div
Figure 8-12. Startup Operation if VCC Undervoltage is caused by Light Load Condition of Diode-rectified
Flyback DC-DC Converter
If VVDD-VSS drops below the lower PoE UVLO (VUVLO_F, approximately 32 V), the hotswap MOSFET is turnedoff, but the converter still runs (unless LINEUV input is pulled low). The converter stops if VVCC falls below the
VCUVLO_F (~6.1 V), the hotswap is in inrush current limit, the SST pin is pulled to ground, or the converter is inthermal shutdown.
8.4.8 Line Undervoltage Protection and Converter Operation
When the input power source is removed, there are circumstances where stress may occur on the powercomponents.
For example, situations where the output voltage capacitor may be able to back drive its secondary-side sync
MOSFET after the flyback converter switching has stopped completely, either temporarily or not. Such situation
could apply at power down or next soft-start.
To address this case, once the LINEUV voltage falls below VLIUVF, the TPS23731 transitions to soft-stop mode.
It turns on temporarily the startup to maintain VVCC, then uses the SST control to ramp down the switching
MOSFET peak current. As a result, the converter output is discharged in a controlled way, the energy ofthe output capacitor being sent back to the input bulk capacitor. Also note that at beginning of soft-stop, the
TPS23731 temporarily forces the peak current to a low value (VCS maximum at approximately 50 mV), until SST
voltage becomes low enough to decrease it further. This advanced feature allows the soft-stop to immediately
start discharging the output capacitor, regardless of the output load level, minimizing any system tradeoffs for
optimum switching MOSFETs protection. See Figure 8-13.
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Power
down

VDD
LINEUV

Soft Stop begins
immediately at max
discharge current

VOUT

SST

xxxxxx
xxx

CS

x

x

Figure 8-13. Soft-Stop Operation

Once the soft-stop operation has been completed and to avoid subsequent oscillations caused by the impact of
the energy transfer on the LINEUV voltage, an internal load (~7 mA) is applied on VDD for approximately 160
ms, before the converter is allowed to restart.
8.4.9 PD Self-Protection
IEEE802.3bt includes new PSE output limiting requirements for Type 3 and 4 operation to cover higher power
and 4-pair applications. Type 2, 3 and 4 PSEs must meet an output current vs time template with specified
minimum and maximum sourcing boundaries. The peak output current per each 2-pair may be as high as
50 A for 10 μs or 1.75 A for 75 ms, and the total peak current becomes twice these values when power isdelivered over 4 pairs. This makes robust protection of the PD device even more important than it was in IEEE
802.3-2012.
The PD section has the following self-protection functions.
•••

Hotswap switch current limit
Hotswap switch foldback
Hotswap thermal protection

The internal hotswap MOSFET of the TPS23731 is protected against output faults and input voltage steps with acurrent limit and deglitched foldback. High stress conditions include converter output shorts, shorts from VDD to
RTN, or transients on the input line. An overload on the pass MOSFET engages the current limit, with VRTN-VSS
rising as a result. If VRTN rises above approximately 14.8 V for longer than approximately 1.8 ms, the current
limit reverts to the inrush limit, and turns the converter off, although there is no minimum inrush delay period (84ms) applicable in this case. The 1.8-ms deglitch feature prevents momentary transients from causing a PD reset,
provided that recovery lies within the bounds of the hotswap and PSE protection. Figure 8-14 shows an example
of recovery from a 15-V PSE rising voltage step. The hotswap MOSFET goes into current limit, overshooting toa relatively low current, recovers to 925-mA full current limit, and charges the input capacitor while the converter
continues to run. The MOSFET did not go into foldback because VRTN-VSS was below 14.8 V after the 1.8-ms
deglitch.

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IPI
250mA/div

CBULKcompletes charge
while converter
operates

VVSS-RTN § -15V
10V/div

VVDD-VSS

20V/div

Time: 400us/div
Figure 8-14. Response to PSE Step Voltage
The PD control has a thermal sensor that protects the internal hotswap MOSFET. Conditions like start-up or
operation into a VDD to RTN short cause high power dissipation in the MOSFET. An overtemperature shutdown(OTSD) turns off the hotswap MOSFET and class regulator, which are restarted after the device cools. The PD
restarts in inrush phase when exiting from a PD overtemperature event.
Pulling DEN to VSS during powered operation causes the internal hotswap MOSFET to turn off. This featureallows a PD with secondary-side adapter ORing to achieve adapter priority. Take care with synchronous
converter topologies that can deliver power in both directions.
The hotswap switch is forced off under the following conditions:••••

VAPD above VAPDEN (approximately 1.5 V)
VDE N ≤ VPD_DIS when VVDD-VSS is in the operational range
PD over temperature
VVDD-VSS < PoE UVLO (approximately 32 V)

8.4.10 Thermal Shutdown - DC-DC Controller
The DC-DC controller has an OTSD that can be triggered by heat sources including the VB and VBG regulators,
GATE driver, startup current source, and bias currents. The controller OTSD turns off VB, VBG, the GATE driver,and forces the VCC control into an under-voltage state.
8.4.11 Adapter ORing
Many PoE-capable devices are designed to operate from either a wall adapter or PoE power. A local power
solution adds cost and complexity, but allows a product to be used if PoE is not available in a particularinstallation. While most applications only require that the PD operate when both sources are present, the38

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VSS

VDD

DEN
CLS

Low Voltage
OutputPower
Circuit

TPS23731

RCLS

58V

From Spare
Pairs orTransformers

0.1uF

RDEN

From Ethernet
Transformers

TPS23731 device supports forced operation from either of the power sources. Figure 8-15 illustrates three
options for diode ORing external power into a PD. Only one option would be used in any particular design.
Option 1 applies power to the device input, option 2 applies power between the device PoE section andthe power circuit, and option 3 applies power to the output side of the converter. Each of these options
has advantages and disadvantages. A detailed discussion of the device and ORing solutions is covered inapplication note Advanced Adapter ORing Solutions using the TPS23753, (SLVA306).

RTN
Adapter
Option 1

Adapter
Option 2

Adapter
Option 3

Figure 8-15. ORing Configurations
Preference of one power source presents a number of challenges. Combinations of adapter output voltage(nominal and tolerance), power insertion point, and which source is preferred determine solution complexity.
Several factors contributing to the complexity are the natural high-voltage selection of diode ORing (the simplest
method of combining sources), the current limit implicit in the PSE, PD inrush, and protection circuits (necessary
for operation and reliability). Creating simple and seamless solutions is difficult if not impossible for many of the
combinations. However, the TPS23731 device offers several built-in features that simplify some combinations.
Several examples demonstrate the limitations inherent in ORing solutions. Diode ORing a 48-V adapter with
PoE (option 1) presents the problem that either source may have the higher voltage. A blocking switch would
be required to assure that one source dominates. A second example is combining a 12-V adapter with PoE
using option 2. The converter draws approximately four times the current at 12 V from the adapter than it doesfrom PoE at 48 V. Transition from adapter power to PoE may demand more current than can be supplied by the
PSE. The converter must be turned off while CIN capacitance charges, with a subsequent converter restart at thehigher voltage and lower input current. A third example is use of a 24-V adapter with ORing option 1. The PD
hotswap would have to handle two times the current, and have 1/4 the resistance (be 4 times larger) to dissipate
equal power.
The most popular preferential ORing scheme is option 2 with adapter priority. The hotswap MOSFET is disabled
when the adapter is used to pull APD high, blocking the PoE source from powering the output. This solution
works well with a wide range of adapter voltages, is simple, and requires few external parts. When the AC
power fails, or the adapter is removed, the hotswap switch is enabled. In the simplest implementation, the PD
momentarily loses power until the PSE completes its start-up cycle.
The DEN pin can be used to disable the PoE input when ORing with option 3. This is an adapter priority
implementation. Pulling DEN low, while creating an invalid detection signature, disables the hotswap MOSFET,
and prevents the PD from redetecting. This would typically be accomplished with an optocoupler that is driven
from the secondary side of the converter. Another option 3 alternative which does not require DEN optocoupler isachievable by ensuring that the auxiliary voltage is always higher then the converter output; in this case, the PSE
power can then be maintained by use of the auto MPS function of the TPS23731.
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The IEEE standards require that the PI conductors be electrically isolated from ground and all other system
potentials not part of the PI interface. The adapter must meet a minimum 1500-Vac dielectric withstand test
between the output and all other connections for options 1 and 2. The adapter only needs this isolation for option
3 if it is not provided by the converter.
Adapter ORing diodes are shown for all the options to protect against a reverse-voltage adapter, a short on theadapter input pins, and damage to a low-voltage adapter. ORing is sometimes accomplished with a MOSFET in
option 3.

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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible fordetermining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

9.1 Application Information
The TPS23731 supports power supply topologies that require a single PWM gate drive with current-mode
control. Figure 9-1 provides an example of a synchronous FET rectified primary-side-regulated flyback converter.

9.2 Typical Application

+

DEN

RAPD

VDD
RDEN

T1

VCC
CBULK

RCL CCL
DCL

RT2P

From Ethernet
Transformers

TPS23731

VOUT2

APDO
COUT2

T2P
GATE

0.1 F
58V
RCLS

From Spare
Pairs orTransformers

RCS

VSS

COUT

COMP
CCOMP

APD

RAPD1

RAPD2

RFRS

CVCC

R1
CCC2

CP

FRS
RDTR

DCC
RCOMP

FB

LINEUV
RUV1

DA

VOUT1

VCC

I_in
RUV2

48V
Adapter

CS

CLS

R2

SST

CSST

EA_DISDTHR
VB
RTN GND I_STP PSRS

CDTR

CVB

RI_STP

Figure 9-1. Basic TPS23731 Implementation

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9.2.1 Design Requirements
Selecting a converter topology along with a converter design procedure is beyond the scope of this application
section.
The TPS23731 has the flexibility to be used in high power density flyback topologies such as primary side
regulation synchronous or non-synchronous flyback.
Examples to help in programming the TPS23731 and additional design consideration are shown in Detailed
Design Procedure. For a more specific converter design example, refer to the EVM that is designed for thedesign parameters in Table 9-1.
Table 9-1. Design Parameters
MAX

UNIT

Input voltage

PARAMETERPower applied through PoE or adapter

TEST CONDITIONS

0

57

V

Operating voltage

After startup

30

57

V

40

57

V

Adapter voltage
Input UVLO

Rising input voltage at device terminals
Falling input voltage

MIN TYPICAL

—

40

30.5

—

V

Detection voltage

At device terminals

1.4

10.1

V

Classification voltage

At device terminals

11.9

23

V

Class 4

Class signature A

38

42

mA

DCDC Topology

Primary Side Regulated Synch Flyback

Output Voltage

5V

Output Current

5A

End-to-End Efficiency At full load

89%

Switching Frequency

250

kHz

9.2.1.1 Detailed Design Procedure
9.2.1.1.1 Input Bridges and Schottky Diodes

Using Schottky diodes instead of PN junction diodes for the PoE input bridges will reduce the power loss by
about 30%. These are often used to maximize the efficiency when FET bridge architectures are not used.
Schottky diode leakage current and different input bridge architectures can impact the detection signature.
Setting reasonable expectations for the temperature range over which the detection signature is accurate is thesimplest solution. Adjusting RDEN slightly may also help meet the requirement.
A general recommendation for the input rectifiers are 2 A, 100-V rated discrete or bridge schottky diodes.
The allows the option of either a discrete schottky bridge or a FET-Diode bridge for 1-2% higher overall systemefficiency.
9.2.1.1.2 Input TVS Protection

A TVS, across the rectified PoE voltage must be used. TI recommends a SMAJ58A, or a part with equal to or
better performance, for general indoor applications. If an adapter is connected from VDD to RTN, as in ORing
option 2 above, voltage transients caused by the input cable inductance ringing with the internal PD capacitancecan occur. Adequate capacitive filtering or a TVS must limit this voltage to be within the absolute maximum
ratings. Outdoor transient levels or special applications require additional protection.
ESD events between the PD power inputs and converter output, cause large stresses in the hotswap MOSFET if
the input TVS becomes reverse biased and transient current around the TPS23731 is blocked. A SMAJ58A is agood initial selection between RTN (cathode) and VSS (anode).
9.2.1.1.3 Input Bypass Capacitor

The IEEE 802.3bt standard specifies an input bypass capacitor (from VDD to VSS) of 0.05 μF to 0.12 μF. Typicallya 0.1-μF, 100-V, 10% ceramic capacitor is used.
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9.2.1.1.4 Detection Resistor, RDEN

The IEEE 802.3bt standard specifies a detection signature resistance, RDEN from 23.7 kΩ to 26.3 kΩ, or 25 kΩ ±5%. Choose an RDEN of 25.5 kΩ.
9.2.1.1.5 Classification Resistor, RCLS.

Connect a resistor from to VSS to program the classification current according to the IEEE 802.3bt standard. The
class power assigned should correspond to the maximum average power drawn by the PD during operation.
Select RCLSx according to Table 8-1.
9.2.1.1.6 APD Pin Divider Network, RAPD1, RAPD2

The APD pin can be used to disable the TPS23731 device internal hotswap MOSFET giving the adapter source
priority over the PoE source. An example calculation is provided, see SLVA306.
9.2.1.1.7 Setting Frequency (RFRS) and Synchronization

The converter switching frequency is set by connecting RFRS from the FRS pin to AGND.
As an example:
1. Optimal switching frequency (fSW) for isolated PoE applications is 250 kHz.
2. Compute RFRS per Equation 2.
3. Select 60.4 kΩ.
The TPS23731 device may be synchronized to an external clock to eliminate beat frequencies from a sampled
system, or to place emission spectrum away from an RF input frequency. Synchronization may be accomplishedby applying a short pulse (TSYNC) of magnitude VSYNC to FRS as shown in Figure 8-3. RFRS should bechosen so that the maximum free-running frequency is just below the desired synchronization frequency. The
synchronization pulse terminates the potential on-time period, and the off-time period does not begin until thepulse terminates. The pulse at the FRS pin should reach between 2.5 V and VB, with a minimum width of 25 ns(above 2.5 V) and rise and fall times less than 10 ns. The FRS node should be protected from noise because it
is high-impedance. An RT on the order of 100 Ω in the isolated example reduces noise sensitivity and jitter.
9.2.1.1.8 Bias Supply Requirements and CVCC

Advanced startup in the TPS23731 allows for relatively low capacitance on the bias circuit. It is recommended touse a 1-µF 10% 25-V ceramic capacitor on CVCC.
9.2.1.1.9 APDO, T2P Interface

The APDO, T2P pins are active low, open-drain outputs which give an indication about the PSE allocatedpower. Optocouplers can interface these pins to circuitry on the secondary side of the converter. A high-gain
optocoupler and a high-impedance (for example, CMOS) receiver are recommended. Please see the as an
example circuit. Below is an example design calculation.
1. Let VCC = 12-V, VOUT = 5-V, = 10-kΩ, VTPx-OUT (low) = 400-mV maximum.
a. ITPx-OUT = 0.46 mA.
2. The optocoupler CTR will be needed to determine . A device with a minimum CTR of 300% at 5-mA LED
bias current is selected. CTR will also vary with temperature and LED bias current. The strong variation of
CTR with diode current makes this a problem that requires some iteration using the CTR versus IDIODE curveon the optocoupler data sheet.
a. The approximate forward voltage of the optocoupler diode is 1.1 V from the data sheet.
b. ITPx-MIN = 1 mA and RTPx = 10.6 kΩ.
3. Select 10.7-kΩ resistor.
9.2.1.1.10 Output Voltage Feedback Divider, RAUX, R1,R2

R1, R2 and set the output voltage of the bias winding of the converter.

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V VCC

VREFC R1 R 2
R2(8)

9.2.1.1.11 Frequency Dithering for Conducted Emissions Control

For optimum EMI performance, CDTR and RDTR should be calculated as described in DTHR and Frequency
Dithering for Spread Spectrum Applications.
These equations yield CDTR = 2.2 nF and RDTR = 235 kΩ where a 237-kΩ standard resistor can be used.

10 Power Supply Recommendations
The TPS23731 converter must be designed such that the input voltage of the converter is capable of operating
within the IEEE 802.3 protocol at the recommended input voltage as shown in Table 8-3 and the minimum
operating voltage of the adapter if applicable.

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11 Layout11.1 Layout Guidelines
The layout of the PoE front end should follow power and EMI/ESD best practice guidelines. A basic set ofrecommendations include:• Parts placement must be driven by power flow in a point-to-point manner; RJ-45, Ethernet transformer, diodebridges, TVS and 0.1-μF capacitor, and TPS23731.
• All leads should be as short as possible with wide power traces and paired signal and return.
• There should not be any crossovers of signals from one part of the flow to another.
• Spacing consistent with safety standards like IEC60950 must be observed between the 48-V input voltage
rails and between the input and an isolated converter output.
• The TPS23731 should be located over split, local ground planes referenced to VSS for the PoE input and to
RTN for the switched output.
• Large copper fills and traces should be used on SMT power-dissipating devices, and wide traces or overlay
copper fills should be used in the power path.
• It is recommended having at least 8 vias (PAD_G) and 5 vias on (PAD_S) connecting the exposed
thermal pad through a top layer plane (2 oz. copper recommended) to a bottom VSS plane (2 oz. copper
recommended) to help with thermal dissipation.

11.2 Layout Example
A detailed PCB layout can be found in the user’s guide of the TPS23731EVM-095 that show the top and bottom
layer and assemblies as a reference for optimum parts placement.

11.3 EMI Containment
•
•
•
•
•
•
•
•
•
•
•
•

Use compact loops for dv/dt and di/dt circuit paths (power loops and gate drives).
Use minimal, yet thermally adequate, copper areas for heat sinking of components tied to switching nodes(minimize exposed radiating surface).
Use copper ground planes (possible stitching) and top layer copper floods (surround circuitry with groundfloods).
Use 4 layer PCB if economically feasible (for better grounding).
Minimize the amount of copper area associated with input traces (to minimize radiated pickup).
Use Bob Smith terminations, Bob Smith EFT capacitor, and Bob Smith plane.
Use Bob Smith plane as ground shield on input side of PCB (creating a phantom or literal earth ground).
Use of ferrite beads on input (allow for possible use of beads or 0-Ω resistors).
Maintain physical separation between input-related circuitry and power circuitry (use ferrite beads asboundary line).
Possible use of common-mode inductors.
Possible use of integrated RJ-45 jacks (shielded with internal transformer and Bob Smith terminations).
End-product enclosure considerations (shielding).

11.4 Thermal Considerations and OTSD
Sources of nearby local PCB heating should be considered during the thermal design. Typical calculations
assume that the TPS23731 is the only heat source contributing to the PCB temperature rise. It is possible fora normally operating TPS23731 device to experience an OTSD event if it is excessively heated by a nearby
device.

11.5 ESD
ESD requirements for a unit that incorporates the TPS23731 have a much broader scope and operational
implications than are used in TI’s testing. Unit-level requirements should not be confused with reference design
testing that only validates the ruggedness of the TPS23731.

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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:• IEEE Standard for Information Technology … Part 3: Carrier sense multiple access with collision detection(CSMA/CD) access method and physical layer specifications, IEEE Computer Society, IEEE 802.3™at(Clause 33)• Information technology equipment – Radio disturbance characteristics – Limits and methods ofmeasurement, International Electrotechnical Commission, CISPR 22 Edition 5.2, 2006-03• Advanced Adapter ORing Solutions using the TPS23753, Eric Wright, TI, SLVA306• Practical Guidelines to Designing an EMI-Compliant PoE Powered Device With Isolated Flyback, Donald V.
Comiskey, TI, SLUA469

12.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straightfrom the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.

12.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.

12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handledwith appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its publishedspecifications.

12.5 Glossary
TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and revision ofthis document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGING INFORMATION
Orderable Device

Status(1)

Package Type Package Pins Package
Drawing
Qty

Eco Plan(2)

Lead finish/
Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

(3)

(4/5)

(6)

TPS23731RMTR

ACTIVE

VQFN

RMT

45

3000

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 125

TPS23731
DB0 WA1(1)

The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)

RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)

MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.
(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to twolines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

SamplesPACKAGE MATERIALS INFORMATION
www.ti.com

18-Dec-2020

TAPE AND REEL INFORMATION*All dimensions are nominal

DeviceTPS23731RMTR

Package Package Pins
Type Drawing

SPQ

VQFN

3000

RMT

45

Reel
Reel
A0
Diameter Width (mm)(mm) W1 (mm)
330.0

16.4

Pack Materials-Page 1

5.25

B0
(mm)

K0
(mm)

P1
(mm)

W
Pin1
(mm) Quadrant

7.25

1.45

8.0

16.0

Q1

PACKAGE MATERIALS INFORMATION
www.ti.com

18-Dec-2020*All dimensions are nominal

DevicePackage Type

Package Drawing

Pins

SPQ

Length (mm)Width (mm)Height (mm)TPS23731RMTR

VQFN

RMT

45

3000

367.0

367.0

35.0

Pack Materials-Page 2

PACKAGE OUTLINE
VQFN - 1 mm max height

RMT0045A

PLASTIC QUAD FLATPACK-NO LEAD
A

5.1
4.9

B

PIN 1 INDEX AREA

7.1
6.9

1 MAX

C
SEATING PLANE
2.9±0.1
PKG

13

1.4
1.3751
0.6
2X
5.2(0.1) TYP
22

14

39X 0.4

0.08 C

1.4

0.05
0.00

23

10

2.15±0.1

47

9

PKG

0.2

29
30

1.4

2.1±0.1

46

45X 0.5
0.3

35

1

PIN 1 ID
(OPTIONAL)

0.6

45

36

3.6
3.7±0.1

45X 0.25
0.15

0.1
0.05

C A B
C

4225180/A 08/2019

NOTES:
1.
2.
3.

All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
This drawing is subject to change without notice.
The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

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EXAMPLE BOARD LAYOUT
VQFN - 1 mm max height

RMT0045APKG

45X (0.2)
45X (0.6)

39X (0.4)

(1.6)

(3.7)
(3.6)

(0.625)

PLASTIC QUAD FLATPACK-NO LEAD

36

45

1

35

(2.205)46(1.4)(R0.05)
TYP
30

PKG

(6.8) (5.2)

29

(0.6)
(1.4)

(2.1)

(0.595)(0.2)(0.55)

947

10(1.375) (2.15)

(2.2)
23

13

(Ø0.2) VIA
TYP
14

22

(2.9)
(1.4)

(1.2)

(4.8)

LAND PATTERN EXAMPLEEXPOSED METAL SHOWNSCALE: 12X

0.05 MAXALL AROUND

METAL

0.05 MIN
ALL AROUNDSOLDER MASKOPENINGEXPOSED METALEXPOSED METALSOLDER MASKOPENINGNON- SOLDER MASKDEFINED(PREFERRED)METAL UNDERSOLDER MASKSOLDER MASKDEFINEDSOLDER MASK DETAILS

4225180/A 08/2019

NOTES: (continued)
4.
5.

This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shownon this view. It is recommended that vias under paste be filled, plugged or tented.

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EXAMPLE STENCIL DESIGNVQFN - 1 mm max height

RMT0045A

PLASTIC QUAD FLATPACK-NO LEAD

PKG

45X (0.2)
45X (0.6)

39X (0.4)(1.25)(3.6)

6X (1.05)
36

45

1

35

6X (0.94)(1.97)

46(R0.05)TYP(0.83)
30

PKG(6.8) (5.2)

29

(0.6)
(1.4)

9

(0.2)
(0.795)10

4X (0.96)

47(1.955)METAL TYP
23

13

14

22

4X (1.27)(1.4)(0.735)(4.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
PAD 46: 76%; PAD 47: 78%
SCALE: 12X

4225180/A 08/2019

NOTES: (continued)
6.

Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

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