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TPS61230ASLVSCZ5A – JULY 2016 – REVISED AUGUST 2016

TPS61230A 5-V / 6-A High Efficiency Step-Up Converter in 2.0-mm x 2.0-mm VQFN
Package
1 Features

3 Description

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The TPS61230A device is a high efficiency fully
integrated synchronous boost converter. It integrates
6-A, 21-mΩ and 18-mΩ power switches, which iscapable of delivering up to 2.4-A output current at 5-V
output with the 2.5-V input supply. The low RDS_ON
switches enable the power conversion efficiency up to
96% and minimize the thermal stress in very compact
solution size.

1

Input Voltage Range: 2.5 V to 4.5 V
Output Voltage Range: 2.5 V to 5.5 V
Two 21-mΩ (LS) / 18-mΩ (HS) MOSFETs
20-µA Quiescent Current
6-A Valley Switching Current Limit
1.15-MHz Quasi-Constant Switching Frequency
PFM Operation at the Light Load
1.05-ms Soft Start Time
True Load Disconnect
NOT Support Vin > Vout Operation
Output Short Protection
Over Voltage Protection
Thermal Shutdown
2.0-mm x 2.0-mm VQFN 7-Pin Package

2 Applications
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Power Banks, Battery Backup Units
USB Power Supply
Tablet PCs
Audio Power Amplifier
Battery Powered Products

The typical operating frequency is 1.15 MHz, whichallows the use of small inductor and capacitors toachieve a small solution size. The TPS61230A
provides an adjustable output voltage via an external
resistor divider.
During the light load condition, the TPS61230A
automatically enters into the PFM operation for
maximizing the efficiency with the lowest quiescentcurrent. In the shutdown by pulling EN pin to the logic
low, the load is completely disconnected from the
input, and the input current consumption is reduced
to below 1.0 μA.
When the output is shorted, the device enters into the
hiccup protection mode and recovery automaticallywhen the output short is released. Other features likethe output over voltage protection, thermal shutdown
protection are integrated.
The device is available in a 2.00-mm x 2.00-mm x
0.9-mm VQFN package and requires the minimum
amount of external components.
Device Information
PART NUMBER
TPS61230A

PACKAGEVQFN (7)BODY SIZE (NOM)
2.00 mm x 2.00 mm

space
Typical Application

Efficiency

L
1uH

100

R1
316kŸ

TPS61230A
CBST

VIN

VIN

FB

OFF

90

C2
2x22 uF

R2
100kŸ

C1
10 uF
ON

VOUT
5V/2.4A

VOUT

GND
EN

Efficiency (%)

SW
C3
10nF

80
70
60

Copyright © 2016, Texas Instruments Incorporated

VIN = 3.0 V
VIN = 3.6 V
VIN = 4.3 V

50
40
0.00010.001

0.01
Load (A)

0.1

1

3
D001

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

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Table of Contents
1
2
3
4
5
6
7

Features .................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions ......................... 3
Specifications......................................................... 4
7.1
7.2
7.3
7.4
7.5
7.6

8

Absolute Maximum Ratings ...................................... 4
ESD Ratings ............................................................ 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 4
Electrical Characteristics........................................... 5
Typical Characteristics .............................................. 6

Detailed Description .............................................. 8
8.1
8.2
8.3
8.4

Overview ................................................................... 8
Functional Block Diagram ......................................... 8
Feature Description................................................... 9
Device Functional Modes........................................ 11

9

Application and Implementation ........................ 12
9.1 Application Information............................................ 12
9.2 Typical Applications ................................................ 12

10 Power Supply Recommendations ..................... 17
11 Layout................................................................... 18
11.1 Layout Guidelines ................................................. 18
11.2 Layout Example .................................................... 18
11.3 Thermal Considerations ........................................ 18

12 Device and Documentation Support ................. 20
12.1
12.2
12.3
12.4
12.5
12.6
12.7

Device Support .................................................... 20
Documentation Support ........................................ 20
Receiving Notification of Documentation Updates 20
Community Resources.......................................... 20
Trademarks ........................................................... 20
Electrostatic Discharge Caution ............................ 20
Glossary ................................................................ 20

13 Mechanical, Packaging, and Orderable
Information ........................................................... 20

4 Revision History
Changes from Original (July 2016) to Revision A
•

2

Page

Changed from Product Preview to Production Data .............................................................................................................. 1

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5 Device Comparison Table
PART NUMBER(1)

OUTPUT VOLTAGE

TPS61230A

Adjustable

TPS61230xA (1)Fixed Vout, 3.7, 4.3, 4.5, 4.8, 5.0, 5.1, 5.4

Product Preview: Contact TI factory for more information.

6 Pin Configuration and Functions

SW

5

VOUT

7

CBST

EN

FB

VIN

1

2

3

4

RNS Package
7-Pin VQFNTop View

6

GND

Not to scale

Pin Functions
PIN

I/O

DESCRIPTIONNAMENUMBER

CBST

1IBoot strap capacitor for the supply of high-side MOSFET driver. An external capacitor is required
between the SW and CBST pins to provide supply voltage to the high-side MOSFET gate driver.

EN

2

I

This is the enable pin of the device. Connecting this pin to ground ( < 0.4 V ) forces the device into
shutdown mode. Pulling this pin to high ( > 1.2 V ) enables the device. This pin must be terminated but
not floating.

FB

3

I

Voltage feedback of adjustable output voltage. Connecting a resistor divider network from the output of
the converter to the FB pin. Must be connected to VOUT on fixed output voltage version.

VIN

4

I

Supply voltage for the internal circuitry.

SW

5

I/O

Switching node of the boost regulator. It is connected to the drain of the internal low side power FET
and the source of the internal high-side power FET.

GND

6

–

Ground pin. Return for the internal voltage reference and analog circuits, also the source terminal of
the low-side FET switch.

VOUT

7

O

Boost converter output.

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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN

MAX

UNIT

VIN, EN, VOUT, FB

-0.3

6

V

SW

-0.3

7

V

CBST

-0.3

12

V

Operating junction temperature range, TJ

-40

150

°C

Storage temperature range, Tstg

-65

150

°C

Voltage range at terminals

(1)
(2)

(2)

Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability.
All voltages are with respect to network ground terminal.

7.2 ESD Ratings
VALUE
V(ESD)(1)(2)

Electrostatic discharge

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)±2000

Charged-device model (CDM), per JEDEC specification JESD22C101 (2)

±750

UNIT
V

JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing withless than 500-V HBM is possible with the necessary precautions.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing withless than 250-V CDM is possible with the necessary precautions.

7.3 Recommended Operating Conditions
MIN
VIN

Input voltage range

VOUT

Output voltage rangeL

Effective inductance range

CI
CO
TJ

TYP

2.5
0.47

1

Effective input capacitance range

1

10Effective output capacitance range

15

22

Operating junction temperature

-40

MAX

UNIT

4.5

V

5.5

V

1.3

µH
µF

80

µF

125

°C

7.4 Thermal Information
TPS61230A
THERMAL METRIC (1)RNS (VQFN)

UNIT

7 PIN
RθJA

Junction-to-ambient thermal resistance (no vias)

93

°C/W

RθJA

Junction-to-ambient thermal resistance (with vias underneath)

56

°C/W

RθJB

Junction-to-board thermal resistance

28.4

°C/W

RθJC

Junction-to-case thermal resistance

57.8

°C/W

ψJT

Junction-to-top characterization parameter

2.0

°C/W

ψJB

Junction-to-board characterization parameter

28.1

°C/W

(1)

4

For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

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7.5 Electrical Characteristics
TJ = -40 °C to 125 °C and VIN = 3.6 V. Typical values are at TJ = 25 °C, unless otherwise noted.
PARAMETERTEST CONDITIONS

MIN

TYP

MAX

UNIT

4.5

V

Power Supply
VIN

Input voltage range

VVIN_UVLO

Input under voltage lockout

2.5

VVIN_HYS

VIN UVLO hysteresis

IQ_VIN

Quiescent current into VIN pin

IC enabled, No load , No Switching, VOUT = 5 V,
VIN = 4.2 V

20

50

µA

IQ_VOUT

Quiescent current into VOUT pin

IC enabled, No load, No Switching VOUT = 5 V

25

55

µA

ISD

Shutdown current into VIN

IC disabled, TJ < 85°C, VIN = 4.2 V

0.2

1

µA

5.5

V

1.195

1.219

V

VIN rising

2.5
150

V
mV

OutputVOUT

Output voltage range

VFB_PWM

Feedback voltage

PWM mode

2.5

VFB_PFM

Feedback voltage

PFM mode

VOVP

Output overvoltage protection threshold

ILKG_FB

Leakage current into FB pin

VFB = 1.2 V

RDS(on)High-side MOSFET on resistance

VIN = 3.6 V, VOUT = 5 V, CBST = 10 nF,

RDS(on)Low-side MOSFET on resistance

VIN = 3.6 V, VOUT = 5 V, CBST = 10 nF

fsw

Switching frequency

VIN = 3.6 V, VOUT = 5 V, PWM Operation

tON_min

Minimum on time

1.171

101.2
5.7

5.8

% VFB
5.99

V

20

nA

18

35

mΩ

21

36

mΩ

1150

1495

kHz

180

ns

Power Switch

805

Linear mode, VOUT = 2.5 V

1.02

Linear mode, VOUT = 0 V

0.06

A

ILIM_PRE

Pre-charge mode and short circuitcurrent limit (DC charge mode)

ILIMIT

Switching valley current limit

tstartup

Soft Start time (boost)

VIN = 3.6 V, VOUT = 5 V

TSD

Thermal shutdown threshold

TJ rising

160°C

Thermal shutdown hysteresis

TJ falling below TSD

10°C

THC_OFFTime for the hiccup off time

VIN = 3.6 V

23

ms

THC_ONTime for the hiccup on time

VIN = 3.6 V

3.5

ms

0.6

A

4.8

6.3

7.8

A

0.3

1.05

1.9

ms

Protection

Logic Interface
VEN_H

EN Logic high threshold

VEN_L

EN Logic low threshold

ILKG_EN

EN pin input leakage current

1.0
0.4
Connected to 3.6V VIN

V
0.1

0.3

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7.6 Typical Characteristics

100

100

90

95

80

90

Efficiency (%)

Efficiency (%)

VIN = 3.6 V, VOUT = 5.0 V, TJ = -40°C to 125 °C, unless otherwise noted.

70
60
VIN = 3.0 V
VIN = 3.6 V
VIN = 4.3 V

50
40
0.00010.001

0.01
Load (A)

0.1

1

85
80
Load = 10 mA
Load = 100 mA
Load = 1 A
Load = 2A

75
70
2.5

3

2.7

TA = 25 ºC
Figure 1. Efficiency vs. Output Current

3.3 3.5 3.7
Input Voltage (V)

3.9

4.1

4.34.4
D001

Figure 2. Efficiency vs. Input Voltage
5.15

Load = 10 mA
Load = 100 mA
Load = 1 A
Load = 2 A

5.10

Output Voltage (V)

5.16
5.12
5.08
5.04

5.05

5.00

4.95

5.00
4.96
2.5

3

3.5
Input Voltage (V)4

VIN = 3.0 V
VIN = 3.6 V
VIN = 4.3 V

4.90
0.0001

4.5

0.001

D001

TA = 25 ºC

0.01
Load (A)

0.1

1

3
D001

TA = 25 ºC
Figure 3. Line Regulation

Figure 4. Load Regulation

1.8

30

HS FET On Resistance (m:)

VIN = 3.0 V
VIN = 3.6 V
VIN = 4.2 V

1.7
1.6

Frequency (MHz)

3.1

TA = 25 ºC

5.20

Output Voltage (V)

2.9

D001

1.5
1.4
1.3
1.2

25

20

15

1.1
1.0
0.3

0.5

0.7

0.9

1.1
1.3
Load (A)

1.5

1.7

10
-40

-20

D001

TA = 25 ºC

VOUT = 5 V
Figure 5. Frequency vs. Load

6

1.9 2

0

20
40
60
80
Junction Temperature (oC)

100

120
D001

VIN = 3.6V

Figure 6. High-Side FET Rdson vs Junction Temperature

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Typical Characteristics (continued)
VIN = 3.6 V, VOUT = 5.0 V, TJ = -40°C to 125 °C, unless otherwise noted.
1.210
1.205
25

Reference Voltage (V)LS FET On Resistance (m:)

30

20

15

1.195
1.190
1.185

10
-40

-20

0

VOUT = 5 V

20
40
60
80
Junction Temperature (oC)

100

1.180
-40

120

-20

0

D001

20
40
60
80
Junction Temperature (oC)

100

120
D001

VIN = 3.6V

Figure 7. Low-Side FET Rdson vs Junction Temperature

Figure 8. Voltage Reference vs Junction Temperature
6.5

40

Switch Valley Current Limit (A)35
Quiescent Current (PA)

1.200

30
25
20
15
TJ = -40oC
TJ = 25oC
TJ = 85oC

10
5
2.5

3

3.5
Input Voltage (V)

4

6

5.5

5

4.5

TJ = -40oC
TJ = 25oC
TJ = 125oC

4
2.5

4.5

3

D001

Figure 9. Quiescent Current vs Input Voltage

3.5
Input Voltage (V)

4

4.5
D001

Figure 10. Switch Valley Current Limit vs Input Voltage
1.2

2.4

1.0

EN Logic Threshold (V)VIN UVLO Threshold (V)

1.1

2.3

2.2

0.9
0.8
0.7
0.6
0.5
0.4

VIN Rising
VIN Falling
2.1
-40

-20

0

20
40
60
80
Junction Temperature (oC)100

EN Rising
EN Falling

0.3

120

0.2
-40

-20

D001

Figure 11. Vin UVLO Threshold vs Junction Temperature

0

20
40
60
80
Junction Temperature (oC)

100

120
D001

Figure 12. EN logic Threshold vs Junction Temperature

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8 Detailed Description
8.1 Overview
The TPS61230A is a high efficiency synchronous boost converter with integrating the 21-mΩ low side FET and
18-mΩ high side FET. The device could deliver up to 12-W output power with 5.5-V maximum output voltage
from single cell Li-Iron battery. TPS61230A uses a quasi constant on-time valley current mode which provides an
excellent transient response. The TPS61230xA typically operates at a quasi-constant 1.15-MHz frequency pulse
width modulation (PWM) at the moderate to heavy load currents, allows the use of small inductor and capacitors
to achieve a compact solution size.
During the PWM operation, a simple circuit predicts the required on time (with the VIN / VOUT ratio) of the owside FET. At the beginning of each switching cycle, the low-side FET turns on and the inductor current ramps up
to the peak current determined by the on-time and the inductance. Once the on-timer expires, the high-side FETturns on and the inductor current decays to a preset valley current threshold determined by the Error Amplifier’s
output. The switching cycle repeats again by calculating the on time and activating the low-side FET.
At the light load currents, TPS61230A operates in Power Save Mode with pulse frequency modulation (PFM) and
improves the efficiency under the light load.
Internal soft-start and loop compensation simplifies the design process and minimizes the number of external
components.

8.2 Functional Block Diagram
L

VIN

CIN
VIN

CBST

SW

4

5

1
VOUT
7

UVLO
ThermalShutdown

ON
OFF

VIN

COUT

VOUT

EN
2

Gate Driver

Current Sense

Logic

VOUT

R2

REF
3

FB
R1

Soft Start
Control

Pulse Modulator

OVP & Short
Protection

VOUT

GND
6

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8.3 Feature Description
8.3.1 Startup
When the device is enabled, the high-side FET turns on to charge the output capacitor linearly by a DC current
which is called the pre-charge phase. The pre-charge startup phase terminates until the output voltage being
close to the input voltage (typically VOUT = VIN -115mV). Once the output capacitor has been biased close to
the input voltage (VOUT = VIN -115mV), the device starts switching which is called the boost soft start phase.
During the soft start phase, there is a soft start voltage controlling the FB pin voltage, and the output voltage
rising slope follows the soft start voltage slew rate (typically). The soft start phase completes when the soft start
voltage reaches the internal reference voltage. The device begins to operate normally and regulates the output
voltage at the pre-set target value.
Table 1. Start-up Mode Description
MODE

DESCRIPTIONCONDITION

Pre-charge

Vout linearly startup without switching

VOUT < VIN – 115mV

Boost Soft Start

Vout startup with switching phase

VOUT > VIN -115mV

8.3.2 Enable and Disable
The device is enabled by setting EN pin to a voltage above 1.2V. At first, the internal reference is activated andthe internal analog circuits are settled. Afterwards, the startup is activated and the output voltage ramps up. With
the EN pin pulled to ground, the device enters into the shutdown mode. In the shutdown mode, the TPS61230A
stops switching and the internal control circuitry is turned off.
8.3.3 Under-Voltage Lockout (UVLO)
The under voltage lockout circuit prevents the device from malfunctioning at the low input voltage of the battery
from the excessive discharge. The device starts operation once the rising VIN trips the under-voltage lockout
threshold (UVLO) , and it disables the output stage of the converter once the VIN is below UVLO falling
threshold.
8.3.4 Current Limit Operation
During the startup phase, the output current is limited to the pre-charge current limit which is proportional to the
output voltage. The device could support minimum 1.0A output current at 2.5V input.
The TPS61230A employs a valley current sensing scheme at the normal boost switching phase. The switch
valley current limit detection occurs during the off time through the sensing the voltage drop across the rectifier
FET. If the switch valley current is lower than the valley current limit level, the device turns off the rectifier FET.
The maximum continuous output current (IOUT_LIM), prior to entering current limit operation, can be defined by:
1
IOUT _ LIM (1 D) u (IVALLEY _ LIM
'IL )
(1)
2
VIN u K
D 1
VOUT
(2)

'IL

VIN D
u
L
f

(3)

If the output current is further increased and the output voltage is pulled blow the input voltage, the TPS61230A
enters into the hiccup protection mode. The average current and thermal will be much lowered at the hiccup
steady state and the device could recovery automatically as long as the over load condition being released.

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Loadincreasing

IOUT_LIM

IVALLEY_LIM

IOUT(1-D)TDT
T=1/f¨,L = (VIN / L) x (D / f)Figure 13. Current Limit Operation
8.3.5 Over Voltage Protection
The device stops switching as soon as the output voltage exceeds the over voltage protection (OVP) threshold.
Both of the low side FET and high side FET turn off. The device resumes the normal operation when the output
voltage is below the OVP threshold.
8.3.6 Load Disconnect
The TPS61230A disconnects the output from the input of the power supply when the device is shutdown. In caseof a connected battery it prevents it from being discharged during the shutdown of the converter.
8.3.7 Thermal Shutdown
The TPS61230A has a built-in temperature sensor which monitors the internal junction temperature, TJ. If thejunction temperature exceeds the threshold (160 °C typical), the device goes into the thermal shutdown, and thehigh-side and low-side FETs turn off. When the junction temperature falls below the thermal shutdown falling
threshold (150 °C typical), the device resumes the operation.

10

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8.4 Device Functional Modes
The TPS61230A has two operation modes, as shown in Table 2.
Table 2. Operation Mode Description
MODE

DESCRIPTIONCONDITION

PWM

Boost in normal switching operation Heavy load

PFM

Boost in power save operation

Light load

8.4.1 PWM Mode
The TPS61230A typically operates at a quasi-constant 1.15 MHz frequency pulse width modulation (PWM) at
moderate to heavy load currents.
8.4.2 PFM Mode
The device integrates a power save mode with the pulse frequency modulation (PFM) to improve the efficiency at
the light load. In the PFM mode, the device starts to switch when the output voltage trips below a set thresholdvoltage. When the output voltage ramping over the PFM threshold, the device stops switching. The DC output
voltage in PFM mode rises above the nominal output voltage in PWM mode by 1.2%.
VOUT
PFM at light load

¨9=1.012 x VOUT_NORM

PWM at medium toheavy load
VOUT_NORMt

Figure 14. Output Voltage in PFM / PWM Mode

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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

9.1 Application Information
The TPS61230A is designed to operate from an input voltage supply range between 2.5 V and 4.5 V with amaximum output current of 2.4 A. The device operates in PWM mode for medium to heavy load conditions and in
the PFM mode at the light load currents. In PWM mode the TPS61230A converter operates with the nominal
switching frequency of 1.15 MHz which provides a controlled frequency variation over the input voltage range. As
the load current decreases, the converter enters into the PFM mode, reducing the switching frequency andminimizing the quiescent current to achieve the high efficiency over the entire load current range.

9.2 Typical Applications
9.2.1 TPS61230A 2.5-V to 4.5-V Input, 5-V Output Converter
L
1uH
SW
C3
10nF

R1
316kŸ

TPS61230A
CBST

VIN

FB

VIN

OFF

C2
2x22 uF

R2
100kŸ

C1
10 uF
ON

VOUT
5V/2.4A

VOUT

GND
EN
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Figure 15. TPS61230A 5-V Output Typical Application
9.2.1.1 TPS61230A 5-V Output Design Requirements
Use the following typical application design procedure to select the external components values for the
TPS61230A device.
Table 3. TPS61230A 5-V Output Design Parameters
DESIGN PARAMETERS

EXAMPLE VALUES

Input Voltage Range

2.5 V to 4.5 V

Output Voltage

5.0 V

Output Voltage Ripple+/- 3% VOUT

Transient Response+/- 10% VOUT

Input Voltage Ripple+/- 200mV

Output Current Rating

2.4 A

Operating frequency

1.15 MHz

9.2.1.2 TPS61230A 5-V Detailed Design Procedure
Table 4. TPS61230A 5-V Output List of Components

12

REFERENCEDESCRIPTIONMANUFACTURER

L

1.0 μH, Power Inductor, XFL4020-102MEB

Coilcraft

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Table 4. TPS61230A 5-V Output List of Components (continued)
REFERENCEDESCRIPTIONMANUFACTURER

CIN

22 μF 6.3V, 0805, X5R ceramic, GRM21BR61A226ME44

MurataCOUT

2 × 22 μF 10V, 0805, X5R ceramic, GRM21BR61A226ME44

MurataCBST

10 nF, X7R ceramic

MurataR2

316k, Resistor, Chip, 1/10W, 1%

Vishay-Dale

R1

100k,Resistor, Chip, 1/10W, 1%

Vishay-Dale

9.2.1.2.1 Programming The Output Voltage

The TPS61230A's output voltage need to be programmed via an external voltage divider to set the desired
output voltage.
An external resistor divider is used, as shown in Equation 4. By selecting R1 and R2, the output voltage is
programmed to the desired value. When the output voltage is regulated, the typical voltage at the FB pin is VFB.
The following equation can be used to calculate R1 and R2.
R1 ö
R1 ö
æ
æ
VOUT = VFB ´ ç 1 += 1.195V ´ ç 1 +÷÷è R2 ø
è R2 ø
(4)
R2 is typically around 100kΩ to ensure that the current following through R2 is at least 100 times larger than FB
pin leakage current. Changing R2 towards a lower value increases the robustness against noise injection.
Changing the R2 towards higher values reduces the quiescent current for achieving highest efficiency at low load
currents.
For the fixed output voltage version, the FB pin must be tied to the output directly.
9.2.1.2.2 Inductor and Capacitor Selection

The second step is the selection of the inductor and capacitor components.
9.2.1.2.2.1 Inductor Selection

A boost converter requires two main passive components for storing energy during the conversion, an inductor
and an output capacitor. It is advisable to select an inductor with a saturation current rating higher than thepossible peak current flowing through the power FETs. The inductor peak current varies as a function of the load,
the input and output voltages and is estimated using Equation 5.
IOUT
1 V ´D
IL(PEAK ) =+ ´ IN(1 - D) ´ h 2 L ´ fSW
(5)
Where
η = Power conversion estimated efficiency
Selecting an inductor with the insufficient saturation performance can lead to the excessive peak current in theconverter. This could eventually harm the device and reduce reliability. It's recommended to choose thesaturation current for the inductor 20%~30% higher than the IL(PEAK), from Equation 5. The following inductors arerecommended to be used in designs.
Table 5. List of Inductors
INDUCTANCE[µH]

CURRENTRATING [A]DC RESISTANCE
[mΩ]

1.0

9.0

12

744 383 560 10

Wurth

1.0

5.1

10.8

XFL4020-102MEB

Coilcraft

PART NUMBER

MANUFACTURER

9.2.1.2.2.2 Output Capacitor Selection

For the output capacitor, it is recommended to use small X5R or X7R ceramic capacitors placed as close as
possible to the VOUT and GND pins of the IC. If, for any reason, the application requires the use of large
capacitors which can not be placed close to the IC, using a smaller ceramic capacitor of 1 µF in parallel to thelarge one is highly recommended. This small capacitor should be placed as close as possible to the VOUT and
GND pins of the IC.
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Care must be taken when evaluating a capacitor’s derating under bias. The bias can significantly reduce
capacitance. Ceramic capacitors can loss as much as 50% of their capacitance at rated voltage. Therefore, leave
margin on the voltage rating to ensure adequate effective capacitance.
The ESR impact on the output ripple must be considered as well, if tantalum or electrolytic capacitors are used.
Assuming there is enough capacitance such that the ripple due to the capacitance can be ignored, the ESR
needed to limit the VRipple is:VRipple(ESR ) = IL(PEAK ) ´ ESR(6)9.2.1.2.2.3 Input Capacitor Selection

Multilayer X5R or X7R ceramic capacitors are an excellent choice for input decoupling of the step-up converteras they have extremely low ESR and are available in small footprints. Input capacitors should be located as
close as possible to the device. While a 10 μF input capacitor is sufficient for most applications, larger values
may be used to reduce input current ripple without limitations. Take care when using only ceramic input
capacitors. When a ceramic capacitor is used at the input and the power is being supplied through long wires,such as from a wall adapter, a load step at the output can induce ringing at the VIN pin. This ringing can couple
to the output and be mistaken as loop instability or could even damage the part. Additional "bulk" capacitance(electrolytic or tantalum) should in this circumstance be placed between CIN and the power source to reduce theringing that can occur between the inductance of the power source leads and CIN.
9.2.1.2.3 Loop Stability, Feed Forward Capacitor

The third step is to check the loop stability. The stability evaluation is to look from a steady-state perspective at
the following signals:• Switching node, SW• Inductor current, IL• Output ripple, VRipple(OUT)
When the switching waveform shows large duty cycle jitter or the output voltage or inductor current shows
oscillations, the regulation loop may be unstable. This is often a result of board layout and/or L-C combination.
The load transient response is another approach to check the loop stability. During the load transient recovery
time, VOUT can be monitored for settling time, overshoot or ringing that helps judge the converter’s stability.
Without any ringing, the loop has usually more than 45° of phase margin.
As for the heavy load transient applications such as a 2 A load step transient, a feed forward capacitor in parallelwith R1 is recommended. The feed forward capacitor increases the loop bandwidth by adding a zero.

14

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9.2.1.3 TPS61230A 5-V Output Application Performance Plots
VOUT (AC) 20 mV/div

VOUT (AC) 30 mV/div

SW 2 V/div

SW 3 V/div
IL 2 A/div

IL 1 A/div
Time scale: 20 Ps/div

Time scale: 20 Ps/div

VOUT = 5 V, VIN = 3.6 V, IOUT = 2 A, TA = 25 ºC, L = 1 µH,
COUT = 2x22 µF

VOUT = 5 V, VIN = 3.6 V, IOUT = 10 mA, TA = 25 ºC

Figure 16. Steady State Switching at PWM

Figure 17. Steady State Switching at PFM

EN 2 V/div
Load 1.5 A/div
VOUT 5V Offset 100 mV/div
VOUT 2 V/div

IL 1 A/div
IL 1 A/div
Time scale: 500 Ps/div

Time scale: 10 ms/div

VOUT = 5 V, VIN = 3.6 V, ROUT = 5 Ω, TA = 25 ºC

VOUT = 5 V, VIN = 3.6 V, IOUT = 0 - 2 A Sweep, TA = 25 ºC

Figure 18. Startup by EN

Figure 19. Load Sweep

Load 500 mA/div
Load 200 mA/div
VOUT (AC) 200 mV/div

VOUT AC 200 mV/div

IL 1 A/div

IL 1 A/div

Time scale: 50 Ps/div

Time scale: 500 Ps/div

VOUT = 5 V, VIN = 3.6 V, IOUT = 0.1 - 1 A with 10 µs slew rate,
TA = 25 ºC

VOUT = 5 V, VIN = 3.6 V, IOUT = 0.5 - 1 A with 10 µs slew rate,
TA = 25 ºC

Figure 20. Load Transient PFM / PWM

Figure 21. Load Transient PWM

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VIN 500 mV/div

VOUT (AC) 20 mV/div

VOUT 2 V/div

IL 1 A/div

IL 1 A/div

Time scale: 200 Ps/div

Time scale: 20 Ps/div

VOUT = 5 V, VIN = 3.6 - 4.2 V, Slew rate 50 µs, IOUT = 1 A,
TA = 25 ºC

VOUT = 5 V, VIN = 3.6 V, IOUT = 1 A before short, TA = 25 ºC

Figure 22. Line Transient

Figure 23. Output Short Entry

VOUT 10 mV/div

IL 200 mA/div
Time scale: 10 ms/div

VOUT = 5 V, VIN = 3.6 V, IOUT short, TA = 25 ºC
Figure 24. Output Short Steady State

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9.2.2

SLVSCZ5A – JULY 2016 – REVISED AUGUST 2016

Systems Example - TPS61230A with Feed Forward Capacitor for Best Transient Response

As for the heavy load transient applications such as a 2 A load step transient, a feed forward capacitor in parallelwith R1 is recommended. The feed forward capacitor increases the loop bandwidth by adding a zero. This results
in a lower output voltage drop, as shown in . See Application Note SLVA289.for the feed forward capacitor
selection.
L
1uH
R1
316kŸ

TPS61230A
CBST

VIN

VIN

FB

OFF

C2
10 pF

C2
2x22 uF

R2
100kŸ

C1
10 uF
ON

VOUT
5V/2.4A

VOUT

SW
C3
10nF

GND
EN
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Figure 25. TPS61230A 5-V Output with Cff Typical Application

10 Power Supply Recommendations
The device is designed to operate from an input voltage supply range between 2.5 V and 4.5 V. This input supply
must be well regulated. If the input supply is located more than a few inches from the converter, additional bulk
capacitance may be required in addition to the ceramic bypass capacitors. An electrolytic or tantalum capacitor
with a value of 47 μF is a typical choice.

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11 Layout11.1 Layout Guidelines
For all switching power supplies, the layout is an important step in the design, especially at high peak currents
and high switching frequencies. If the layout is not carefully done, the regulator could show stability problems aswell as EMI problems. Therefore, use wide and short traces for the main current path and for the power groundtracks. The input capacitor, output capacitor, and the inductor should be placed as close as possible to the IC.
Use a common ground node for power ground and a different one for control ground to minimize the effects ofground noise. Connect these ground nodes at the GND pin of the IC. The most critical current path for all boost
converters is from the switching FET, through the synchronous FET, then the output capacitors, and back toground of the switching FET. Therefore, the output capacitors and their traces should be placed on the sameboard layer as the IC and as close as possible between the IC’s VOUT and GND pin.
See Figure 26 for the recommended layout.

11.2 Layout Example
Top Layer

Bottom Layer

VIN

L

CIN

SW

GND

GND
4

6

VIN

FB

3

RUP_FB

COUT1

COUT2

5

2
CBST

VOUT

1

GND

EN
7

RDOWN_FB

SW

VOUT

CBST

Figure 26. Layout Recommendation

11.3 Thermal Considerations
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added
heat sinks and convection surfaces, and the presence of other heat-generating components affect the powerdissipation limits of a given component.
Two basic approaches for enhancing thermal performance are listed below.
• Improving the power dissipation capability of the PCB design
18

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Thermal Considerations (continued)•

Introducing airflow in the system

For more details on how to use the thermal parameters in the dissipation ratings table please check the Thermal
Characteristics Application Note (SZZA017) and the IC Package Thermal Metrics Application Note (SPRA953).

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12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOTCONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHERALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:• Thermal Characteristics Application Note (SZZA017)• IC Package Thermal Metrics Application Note (SPRA953)

12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that haschanged. For change details, review the revision history included in any revised document.

12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms ofUse.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools andcontact information for technical support.

12.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.

12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and revision ofthis document. For browser-based versions of this data sheet, refer to the left-hand navigation.

20

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30-Aug-2016

PACKAGING INFORMATION
Orderable Device

Status(1)

Package Type Package Pins Package
Drawing
Qty

Eco Plan

Lead/Ball Finish

MSL Peak Temp

(2)

(6)

(3)

Op Temp (°C)

Device Marking(4/5)

TPS61230ARNSR

ACTIVE

VQFN-HR

RNS

7

3000

Green (RoHS& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM-40 to 125

12EI

TPS61230ARNSTACTIVE

VQFN-HR

RNS

7

250

Green (RoHS& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM-40 to 125

12EI

(1)

The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement thatlead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weightin homogeneous material)(3)

MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.
(6)

Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Addendum-Page 1

SamplesPACKAGE OPTION ADDENDUM

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30-Aug-2016

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION
www.ti.com

30-Aug-2016

TAPE AND REEL INFORMATION*All dimensions are nominal

DevicePackage Package Pins
Type Drawing

SPQ

Reel
Reel
A0
Diameter Width (mm)(mm) W1 (mm)TPS61230ARNSR

VQFNHR

RNS

7

3000

180.0

8.4

TPS61230ARNSTVQFNHR

RNS

7

250

180.0

8.4

Pack Materials-Page 1

B0
(mm)

K0
(mm)

P1
(mm)

W
Pin1
(mm) Quadrant

2.3

2.3

1.15

4.0

8.0

Q1

2.3

2.3

1.15

4.0

8.0

Q1

PACKAGE MATERIALS INFORMATION
www.ti.com

30-Aug-2016*All dimensions are nominal

DevicePackage Type

Package Drawing

Pins

SPQ

Length (mm)Width (mm)Height (mm)TPS61230ARNSR

VQFN-HR

RNS

7

3000

210.0

185.0

35.0

TPS61230ARNSTVQFN-HR

RNS

7

250

210.0

185.0

35.0

Pack Materials-Page 2

PACKAGE OUTLINE

RNS0007A

VQFN - 1 mm max height
SCALE 4.750

PLASTIC QUAD FLATPACK - NO LEAD

2.1
1.9

B

A

PIN 1 INDEX AREA
2.1
1.9

1 MAX

C
SEATING PLANE
0.08 C

PKG(0.2) TYP

1.1
0.9
2X

0.35
0.25

0.8
0.6

0.05
0.00

7

6

0.015 PIN 5

0.54

PKG
5

0.3
0.2

3X

0.45
0.35

0.45
0.35
4

1
3X 0.52X 1.5

4X

0.3
0.2
0.1
0.05

C B
A
C ALL PADS
4222253/A 09/2015

NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.

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EXAMPLE BOARD LAYOUT

RNS0007A

VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

3X (0.5)

PKG

4X (0.25)

4

1
4X (0.6)(0.015)
PIN 5

(0.9)

(2.4)
5

PKG
(0.54)(0.25)
7

6(R0.05) TYP(0.6)(0.75)

2X (0.3)

(0.9)
(1.2)

LAND PATTERN EXAMPLESCALE:25X

0.05 MAXALL AROUND
METAL

0.05 MIN
ALL AROUNDSOLDER MASKOPENINGSOLDER MASKOPENINGSOLDER MASKDEFINEDPADS 5-7

NON SOLDER MASKDEFINEDPADS 1-4

METAL UNDERSOLDER MASKSOLDER MASK DETAILS

4222253/A 09/2015

NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
4. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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EXAMPLE STENCIL DESIGN

RNS0007A

VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

3X (0.5)
PKG

4X (0.25)
1

4(R0.05) TYP

4X (0.6)
4X
EXPOSED METAL
3X(0.015)
PIN 5

(0.9)

2X (0.86)

3X (0.66)

5(0.54)PKG

3X (0.25)
7
6

2X (0.525)(0.8)

SOLDER MASKEDGE, TYP

(0.263)(0.8)(0.938)

3X (0.3)

METAL UNDERSOLDER MASKTYPSOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
PAD 5: 79%, PADS 6 & 7: 85%
SCALE:30X

4222253/A 09/2015

NOTES: (continued)
5. For alternate stencil design recommendations, see IPC-7525 or board assembly site preference.

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