DIODE
APPLICATIONHANDBOOKFUNDAMENTALS,

CHARACTERISTICS,

APPLICATIONSDesign Engineer’s Guide

Diode Application Handbook
Fundamentals, Characteristics, Applications

Design Engineer’s Guide

Contributors
Reza Behtash
Sebastian Fahlbusch
Surabhi HiremathSebastian Klötzer
Srikanth Yedehalli Lakshmeesha
Burkhard Laue
Nima Lotfi
Martin Röver
Guido Söhrn
Burkhard Stasik
Olaf Vogt

Diode Application Handbook
Fundamentals, Characteristics, Applications
Design Engineer’s Guide
Copyright © Nexperia UK (Ltd)May 2022
www.nexperia.com
ISBN 978-0-9934854-9-7
All rights reserved.
No part of this publication may be reproduced or
distributed in any form or by any means without
the prior written permission of the author.

Introduction

1

Diode fundamentals

2

Data sheet parameters

3

Thermal considerations

4

Diode packaging

5

Reliability aspects

6

Diode applications and use cases

7

Summary8

Abbreviations
Legal information

Diode Application Handbook

Preface
Welcome to the Nexperia Diode Applications Handbook. Like all of our other
Design Engineer’s Guides, the Diode Handbook is intended to be a practical,
comprehensive and up-to-date reference work written by engineers for engineers,
sharing expertise, application insights and best practice to help designers optimize
their electronic circuits.
Nexperia and diodes share a common history dating back for the whole of thecommercialisation of electronics. Diodes were – of course – one of the fundamental
electronic components, first developed over 100 years ago. Similarly, Nexperia cantrace its history back over 100 years with names like Mullard, Philips, Valvo,
Signetics and NXP ringing through its lineage. Today, Nexperia’s extensive portfolio
includes diodes, bipolar transistors, ESD protection devices, MOSFETs, GaN FETs
and analog & logic ICs, totaling more than 15.000 parts. Virtually every electronic
design in the world uses Nexperia components, and these products are recognized
as benchmarks in efficiency – in process, size, power and performance. 250 million
parts are shipped every single day.
Despite being first developed in the early years of last century, diodes continue toplay a vital part in electronic circuits. But, of course they have evolved beyond allrecognition from the days of pioneers like Walter Schottky. Most recently, of course
we have seen new materials such as silicon carbide emerge which are enabling therealization environmentally-responsible electric vehicles with the performance andrange demanded by customers.
The goal of this new handbook – or to give it its full name – Diode Application
Handbook – Fundamentals, Characteristics, Applications: Design Engineer’s Guide
is to be recognized as the technical dictionary for semiconductor diodes, sharing
technical and application insights between the engineering community. Therefore,
we proudly invite you to study our Diode Application Handbook – the table ofcontents will make it easy to navigate.
Finally, I would like to thank Dr.-Ing. Reza Behtash, who has significantly
contributed to this edition.
Olaf Vogt
Director Product Application Engineering
Nexperia

Diode Application Handbook

Table of Contents
Chapter 1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Chapter 2
Diode fundamentals
2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.3
2.4
2.4.1
2.4.2
2.5
2.5.1
2.5.2
2.5.3
2.5.4
2.5.5
2.5.6
2.5.7
2.6
2.6.1
2.6.2
2.6.3
2.6.4
2.7
2.7.1
2.7.2
2.7.3

Different types of diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Structure and functional principle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Recovery rectifiers (P(I)N diodes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Planar Schottky diode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Trench Schottky diode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Silicon germanium (SiGe) diode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Static behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dynamic behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Forward recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reverse recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Benchmarking of different technologies
in terms of switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Evaluation parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sample selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Impact of the temperature on the switching performance . . . . . . . . . .
Why is the Trench Schottky diode superior
in terms of switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Impact of the slope gradient on switching performance . . . . . . . . . . . .
Impact of the turn-off current on switching performance. . . . . . . . . . .
Impact of the reverse voltage on switching performance . . . . . . . . . . .
SiC rectifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Material properties of 4H-SiC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SiC enabling superior power diodes andchanging the high voltage diode landscape. . . . . . . . . . . . . . . . . . . . . . . .
Advanced SiC MPS process for maximum performance . . . . . . . . . . . . .
Zener diodes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Datasheet parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Zener diodes package overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

20
22
22
23
24
27
29
34
34
35
37
37
38
39
41
44
45
46
48
48
49
50
62
64
64
65
66

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Chapter 3
Data sheet parameters
3.1
3.2
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
3.2.6
3.2.7

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Understanding Nexperia datasheet parameters andwhere they can be found. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Quick reference data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pinning-, ordering- and marking information. . . . . . . . . . . . . . . . . . . . . . .
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Datasheet temperature curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package outline & recommended footprint
for reflow soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter 5
Diode packaging
78
78
78
81
81
85
88
93

4.3.3
4.3.4
4.4
4.4.1
4.4.2

5.1
5.2
5.2.1
5.2.2
5.3
5.3.1
5.3.2
5.4
5.4.1
5.4.2

Through-hole packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Packages for surface-mounted devices . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Wire-bonded leaded packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Clip Flat Power (CFP) packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Leadless packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Leadframe-based Dual-Flat-No-Leads packages (DFN) . . . . . . . . . . . . . . 134
Chip Scale Packages (CSP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Soldering techniques. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

96

Chapter 4
Thermal considerations
4.1
4.1.1
4.1.2
4.1.3
4.1.4
4.1.5
4.1.6
4.2
4.2.1
4.2.2
4.3
4.3.1
4.3.2

Diode Application Handbook

Diode as a thermal system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Measurement of thermal resistances. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Definition of thermal resistances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Approximations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Clip bonded packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Multiple chip devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Rth(j-c) and why we call it Ψ(j-top). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Thermal considerations in forward bias. . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Continuous current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Pulsed operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Thermal considerations in reverse bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Rectifier as thermal system – thermal runaway. . . . . . . . . . . . . . . . . . . . . 111
The safe operating area (SOA) of a rectifier
in reverse direction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Impact of technology on the SOA of a rectifier. . . . . . . . . . . . . . . . . . . . . 115
Impact of package on the SOA of a rectifier. . . . . . . . . . . . . . . . . . . . . . . . 117
Transient effects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
The dynamic thermal impedance Zth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Foster and Cauer model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Chapter 6
Reliability aspects
6.1
6.2
6.3
6.4
6.5

Probability of failure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Reliability tests & failure modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Automotive-grade qualification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Mission profiles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Nexperia’s high robustness specification . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Chapter 7
Diode applications and use cases
7.1
7.2
7.3
7.4
7.5
7.6
7.6.1
7.6.2
7.7
7.7.1
7.7.2
7.7.3
7.7.4

Polarity protection diode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Zener applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
ORing applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Switching diode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Bootstrap diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Overview of hard-switching DC-DC converter topologies . . . . . . . . . . . 170
Principles of hard-switching topologies. . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Diode power losses in CCM, BCM and DCM. . . . . . . . . . . . . . . . . . . . . . . . 174
Topologies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Buck converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Boost converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Buck-boost converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Flyback converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

1

Diode Application Handbook

Chapter 8
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  190

Chapter 1

Abbreviations  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  192

Introduction

Legal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

Introduction

nexperia | Design Engineer’s Guide

15

nexperia | Design Engineer’s Guide

The history of semiconductor diodes underpins the entire history of electronics,
and while it is easy to overlook diodes, today they have never been more relevant
or diverse. Nexperia’s diode expertise stretches back to the 1950s and the Valvo/
Philips Semiconductors facilities in Hamburg, Germany. In the intervening 70 years
the company has built a very broad portfolio of devices including Small Signal
Switching and Zener Diodes, very efficient Schottky Diodes and Power Rectifiers inmodern Trench technologies.
Highlighting a few important milestones:
The development of special diodes with variable junction capacity, so called“Vericap” diodes, begins in 1964.
In the 1970s the production of Glass Diodes in the famous SOD68 commences.
Nexperia is still known as the packaging innovator – the famous SOT23 3-pin
package, invented in 1969, is still the world’s largest-selling semiconductor
package. In the 1980s and 1990s the number of ‘leaded SMD’ massively increased
due to high-volume consumer products like PCs, Laptops, TVs etc. In the early 2000
diodes in leadless packages were introduced, supporting the needs of the recordbreaking Mobile / Smart Phone Industry. Latest packaging considerations are
discussed in Chapter 5 of this handbook.
The first decade of the 21st century was also when Nexperia built its successful
ESD Diode product portfolio (readers are advised to read the ESD Application
Handbook and the ESD Automotive Edition.)
Developments continue apace and in this current decade, there have been, perhaps
for some, surprising introductions. How familiar, for example, are most readerswith new silicon germanium products (the first SiGe rectifiers were brought tomarket in 2020 by Nexperia)? Another case in point is silicon carbide. A visit to a
trade show or quick web search will confirm that SiC outperforms silicon devices incertain applications. But what are the material properties that deliver thisperformance boost and how can designers benefit most from new SiC rectifiers?
This book will tell you.
The content of the Diode Application Handbook will benefit readers by sharing a
wealth of technical information, from basic fundamentals up to design ideas.
Chapter 2 explains the fundamentals, looking at diode types and behavior.
Chapter 3 looks at the parameters commonly listed in diode datasheets, and how
to interpret that information. Chapter 4 is devoted to thermal considerations, andChapter 5 focuses on one of Nexperia’s key strengths: packaging innovation, which
is so influential on reliability and performance. Chapter 6 concerns itself withreliability, including Automotive-grade qualification. The application’s chapter (7) atthe end of the handbook highlights several basic functions (including polarity

16

Diode Application Handbook

protection and freewheeling functionality for inductive loads) that diodes provide
in electronic systems. These sub-circuit insights help to address real-world
challenges in electronic design.
Earlier, we mentioned electric vehicles as one obvious example of an application
where new diode technologies are playing a vital, enabling role: in reality, very few
electronic systems exist without some form of diode performing a vital function.
Diodes are used in data centers, 5G, robotics, IoT systems, ‘smart’ installations –home/office/factory/city – medical equipment, in consumer electronics like mobile
phones and in high-reliability mission-critical space expiration.

1
Introduction

Introduction

1

Efficiency is the mantra of our times, either for reasons of size, power consumption,
performance or cost, or perhaps all four. Correct component selection will optimize
the final design; poor choices will lead to compromise. As one of the mostfundamental electronics building blocks, the diode is – as readers will see – notmerely the humble discrete component that can be considered at the last minute.
The Diode Applications Handbook will satisfy engineers who wish to get moreinsights on fundamentals and applications insights. The focus on engineering
aspects and technical challenges provides vital background information that will
enable the engineer to optimize designs to ensure best product performance. But
the book never falls into the trap of becoming a mere academic exercise. Its pages
detail practical solutions to real world problems with applicable circuits andformulas. Chapter 7, Diode applications and use cases, is particularly strong herewith sections on polarity protection, ORing, hard switching, power supply design
and more.
This reference work represents the collected knowledge of some of our industry’s
most respected experts. But these are people who deal on a daily basis withquestions from engineers. They know what questions are commonly asked andthey are delighted to be able to share their research and experience widely andfreely. We hope that you find this work informative and useful.
Nexperia continually updates product information and application notes.
Please visit our Nexperia Encyclopaedia handbook series
www.nexperia.com/design-engineers-guides to read our other handbooks:• MOSFET & GaN FET Application Handbook• LOGIC Application Handbook• ESD Application Handbook and• ESD Application Handbook: Automotive Edition

17

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2

Diode Application Handbook

Chapter 2
Diode fundamentals

Diode fundamentals

Introduction

1192.1 Different types of diodes

Schottky diode
Schottky contact

PN diode

Anode

Anode

Ohmic contact

Vms
n- epi layer

Vpnp+ epi layer

Vf
Vdriftn- epi layern+ substrate

Vf
Vdriftn+ substrate

Ohmic contact

CathodeCathodeSiGe

aaa-034511

Figure 1 | Sketch showing the layer structure of Schottky (left) and PN diodes.

SiC

Schottky(Fast) Recovery

200 V
100 V

1200 V
650 V

Maximum
reversevoltage

Diode Application Handbook

An ideal diode will generally have a low forward voltage drop, a high reverse
blocking voltage, zero leakage current and a low parasitic capacitance, facilitating ahigh switching speed. When considering the forward voltage drop, there are twomain elements contributing to the overall voltage drop VF, as shown in Figure 1:
the voltage drop across the junction – a p-n junction in case of recovery rectifiers
and Zener diodes and a metal-semiconductor junction in case of Schottky rectifiers;
and the voltage drop across the drift region. The forward voltage drop across the
p-n junction is intrinsically determined by the built-in voltage and hence, mainly by
the chosen semiconductor and its doping. On the other hand, the forward voltage
drop across the metal-semiconductor interface in a Schottky barrier rectifier can be
modified by the choice of the Schottky metal, with the Schottky barrier being theresult of the difference between the metal work function and the electron affinityof the semiconductor. By using Schottky metals with a low metal work function, thevoltage drop across the metal semiconductor interface can be minimized. However,there is a trade-off between the forward voltage drop across the junction and theleakage current of the Schottky rectifier, as the level of the leakage current is also
determined by the Schottky barrier and the electrical field across the metal
semiconductor interface. In addition to this trade-off, the advantage of a low
voltage drop across the junction can disappear when the thickness of the drift
region is increased in order to achieve a high reverse blocking voltage. This is thereason why the reverse blocking voltage of Schottky rectifiers is traditionallylimited to well below 200V. These considerations lead to the overview of utilized
technologies for discrete diodes based on maximum reverse voltage, as shown in
Figure 2. As already mentioned, Schottky diodes are normally used up to a
maximum reverse voltage of approx. 200V; beyond 200V, Schottky diodes lose theirintrinsic advantage. After this point, recovery rectifiers are used. A distinction ismade for recovery rectifiers between different switching speeds. This classification
will be described in the chapter on dynamic behavior (2.4). The operating range of asilicon carbide (SiC) diode starts at 650V. Thanks to the wide bandgap of SiC thisrange extends to well above 1700V. Figure 2 also shows a new technology calledsilicon germanium (SiGe). The maximum reverse voltage range of SiGe diodes is
between 100 and 200V, at around about the interface between Schottky diodes
and recovery rectifiers.

2
Diode fundamentals

nexperia | Design Engineer’s Guide

aaa-034510

Diode fundamentals

2This chapter will discuss the various diode types and technologies regarding theirinternal structure, static and dynamic behavior.

Figure 2 | Overview of different technologies for discrete diodes
depending of max. reverse voltage.

20

21

2.2.1 Recovery rectifiers (P(I)N diodes)
Recovery rectifiers are based on a classical p-n junction in the device structure. An
n-doped drift layer is epitaxially grown on the n+ substrate which serves as thecathode of the vertical device. The anode of the diode is realized by implanting anddiffusing a p dopant into the epitaxial layer. The p diffusion step determines the
profile of the p well, and it is therefore crucial for the breakdown voltage of thediode. The maximum reverse voltage of recovery rectifiers starts at around 200V
and increases to approximately 1700V. Diodes at the higher end of the reverse
voltage range consist of a p-i-n-junction rather than a p-n interface, as the almost
undoped layer between the p and n region allows for a further expansion of thedepletion layer while the device is reverse biased. A top metallization layer is used
to create an ohmic contact to the anode of the diode.
The Scanning Electron Microscope (SEM) image in Figure 3 shows the cross sectionof a recovery rectifier. In order to highlight the different doping regions, thesample has been treated with a special etchant, making the doping interfaces
clearly visible. In this picture one can see very clearly the shape of the p well at theedge of the active region. This shape decides the contour of the depletion regionof the p-n junction when the diode is reverse biased, and together with the field
plate it forms the termination area for this device. Proper edge termination of theactive cell is important in order to avoid the crowding of the electrical field in thisarea which could lead to premature breakdown and increased leakage current.
Figure 4 illustrates a simplified sketch showing the contour of the depletion region
and the resulting crowding of the electrical field at the edge of the active cell. As
we will see later on, the termination design can also impact the dynamic behaviorof the device. The epitaxial layer of recovery rectifiers is often intentionallycontaminated with gold or platinum. The Au and Pt atoms in the silicon layers act as
traps for the charge carriers and reduce the lifetime of minority carriers. Thisso-called ‘lifetime kill’ has a huge impact on the dynamic behavior of the device andwill be discussed in section 2.4.

22

Figure 3 | SEM picture
showing the crosssection of a recovery
rectifier. The sample
has been etched inorder to decorate thedifferent doping
regions.

Electrode

Diode fundamentals

2.2 Structure and functional principle

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2

Oxide

E-ﬁeld crowding

Depletion region contour

nFigure 4 | The so-called ‘E-Field crowding’ at the edge of the active cell
leads to premature breakdown and increased leakage current.
A proper edge termination prevents the increased electrical field concentration
at the edge of the active cell.

2.2.2 Planar Schottky diodeThe Schottky diode – named after its inventor, the German physicist Walter Hans
Schottky – consists essentially of a metal-semiconductor interface. Because of its
low forward voltage drop and high switching speed, the Schottky diode is widelyused in a variety of applications, such as the boost and buck diode in power
conversion circuits. The electrical performance of a Schottky diode is, of course,
subject to physical trade-offs, primarily between the forward voltage drop, theleakage current and the reverse blocking voltage. The most importantconsideration for balancing the trade-off between the forward voltage drop andthe leakage current is the chosen Schottky metal. The higher the metal work

23

Figure 5 | SEM picture
showing the crosssection of a planar
Schottky diode. The
sample has been
etched in order tohighlight the different
doping regions. The
termination consistingof guard ring and field
plate is clearly visible.

Figure 5 illustrates the cross section of a planar Schottky diode. The sample has
been etched in order to delineate the different doping regions in the device. The
etching also highlights the edge termination concept of the planar Schottky diode.
The so-called ‘guard ring’ consists of a p-doped region beneath the oxide opening
at the edge of the active area. The guard ring has a huge impact on the leakage
current of the Schottky diode as it prevents the electrical field crowding at theedge of the active region, as discussed earlier and shown in Figure 4. But the guard
ring is also ultimately a pn junction at the edge of the active area parallel to theactual metal-semiconductor junction. When the diode is forward biased with a highforward voltage – high enough to switch on this pn diode, the guard ring
contributes to the forward current of the Schottky diode, enhancing the current
capability of the device. But it can also have a detrimental effect on the switching
behavior of the Schottky, as will be discussed later in the dynamic behavior
section 2.4.

2.2.3 Trench Schottky diodeThe widely-known one-dimensional silicon limit describes the general trade-off
between the achievable breakdown voltage and the specific on-resistance of asilicon layer sandwiched between two electrodes. One could overcome the 1D
silicon limit and decrease the specific on-resistance for a given breakdown voltage
by flattening the profile of the electrical field in the semiconductor layer. In an ideal
case, the electrical field would be constant along the drift layer rather than having
a peak surpassing the critical electrical field in the given semiconductor. There arebasically two concepts for flattening the electrical field profile which are used incommercial products: the super junction and the trench. The concept behind the24

Trench Schottky rectifier is termed ‘RESURF’ (reduced surface field). The RESURF
effect is illustrated in Figure 6. In a planar Schottky rectifier the equipotential lines
are concentrated close the top electrode, resulting in a high electrical field near thesurface. This results in a strong increase of the leakage current with increasing
reverse voltage, and an early breakdown when the critical electrical field isexceeded near the surface.

metal
potential
lines

Diode fundamentals

function of the Schottky metal, the higher the barrier height, and therefore thehigher the forward voltage drop and the lower the leakage current of the Schottky
diode (and vice versa). The breakdown voltage of the Schottky diode on the other
hand is primarily determined by the choice of the epitaxial layer thickness anddoping.

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2n-type drift
regionn+ substrate

doping.

Figure 6 | Equipotential lines in a planar Schottky rectifier (left) andin a Trench Schottky rectifier (right) in reverse direction.
The top metal layer represents the anode, the bottom metal layer is the cathode.

By etching trenches into the silicon and filling them with polysilicon – electricallyseparated from the drift region by a thin dielectric – the trenches act like a field
plate in the semiconductor, depleting the drift region in reverse direction andresulting in a flattened electrical field profile along the drift region. Therefore, themaximum electrical field is occurring inside the dielectric layer at the bottom of thetrench rather than at the surface of the epi layer. The trench concept gives thedevice designer an additional degree of freedom to design and to optimize thedevice with respect to one of its parameters. Therefore, it is possible to use
trenches to reduce the leakage current of the Schottky diode for a given epitaxial
layer thickness, doping and Schottky metal. This is illustrated in Figure 7, where thereverse characteristics of a planar Schottky diode is compared to a Trench Schottky
diode with the same epitaxial structure (doping and thickness), and the same
Schottky metal and die size.

25

10 −

Planar Schottky

10 −

10 −

Trench Schottky

Same epi, same Schottky metal
Trench Schottky
Planar Schottky

10 −
0

5

10

15

20

25

30

35

40

45

50

55

60

65

70

Reverse Voltage (V)Figure 7 | The reverse characteristics of a planar Schottky vs. a Trench Schottky withthe same epitaxial thickness and doping, same Schottky metal and die size.

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2.2.4 Silicon germanium (SiGe) diode
Silicon germanium (SiGe) is a compound semiconductor well known as the basematerial for hetero-junction bipolar transistors (HBT) since the 1990s. Over the lastyears, Nexperia has adapted this Technology for use in diodes. At the beginning of2020 the first SiGe rectifiers were brought to the market by Nexperia.
When considering performance, the SiGe diode can be interpreted as a hybrid
technology between Schottky and a recovery rectifier (PN diode). It combines thehigh efficiency of Schottky rectifiers, in terms of a low forward voltage drop, withthe low reverse leakage currents and the thermal stability of PN diodes.

10 −

10 −

Diode Application Handbook

Figure 8 | SEM picture
showing the crosssection of a trench
Schottky diode.
The edge termination
area is highlighted andconsists of a wide
trench covered by afield plate. Consequent­ly there is no guard ringand thus no pn junction(as would occur for aplanar Schottky).

However, it is also possible to use trench technology to improve the forward
voltage drop Vf of the Schottky diode, by increasing the doping concentration of
the epitaxial layer without sacrificing the leakage current level of the device. Thiscan also be useful for a die-shrink to house the diode in a smaller package.

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Leakage current (A)Diode fundamentals

2

To better comprehend the excellent trade-off between VF and IR Figure 9 shows
the structure of the SiGe diode. The epitaxial layers of the devices are grown on
standard n+ silicon substrates. Therefore, conventional tools and processes areused for mass production. On top of the n− drift layer there is a very thin and highly
p-doped silicon germanium layer. One obstacle to overcome is the accurate
formation of the SiGe interface, as the lattice mismatch between silicon andgermanium is greater than 4%. To prevent the interface having misfit dislocations,investigations have shown that reliable junctions may be formed if the germanium
content is low and the SiGe layer is thin. [Ashburn, Peter (2003): SiGe Heterojunction
Bipolar Transistors, University of Southampton, UK: John Wiley & Sons, Ltd]. The
cathode of the diode consists of the back side metallization which forms an ohmic
contact, as with other diode types.
The thin SiGe layer leads to a big gradient of the electron concentration, as
illustrated in Figure 9. Along with the higher intrinsic carrier concentration of SiGe
compared to Si (n2iSiGe >> n2iSi as a result of the smaller band gap), this leads to a
. Thissignificant diffusion component of the current in the structure: J = q × Dn × ∂n∂xmeans that for a given forward voltage drop, a higher current density can beachieved with this structure as compared to a pure p-n junction. Equally, if Vf islower, there is less stored charge in the layer for a given current density. This also
results in an improvement in the switching behavior of the SiGe diode as compared
to recovery rectifiers, as will be shown in section 2.5.

The cross section of a trench Schottky diode is shown in Figure 8. Aside from thetrenches, an obvious difference to a planar Schottky design is the termination
concept, which consists of a wide trench. A field plate covers this trench to its
center. Consequently, there is no guard ring and thus no pn junction in the device,at least for trench Schottky diodes with a maximum reverse voltage of up to
approximately 100V. The impact of this termination concept on the switching
behavior of the Trench Schottky diode will be discussed in section 2.5.4.

26

27

AnodeElectron concentration

p+ SiGen- epi layern+ substrate

Ohmic contact

CathodeFigure 9 | Structure of the SiGe diode together with simplified electron concentration
along the structure. The very thin and highly p-doped silicon germanium layer together withthe higher intrinsic carrier concentration of SiGe (due to its narrower bandgap leading to∂nni2SiGe » ni2Si ) leads to a significant diffusion current in the structure: J = q × Dn × ∂x.

The static behavior of a diode is described by its current/voltage (IV) characteristics
in forward and reverse direction in the data sheet. As an example, the IV
characteristics of the Schottky diode PMEG045V150EPD are shown in Figure 10.
Both the forward characteristics and the reverse characteristics exhibit a strong
temperature dependence. The higher the temperature the lower the forward
voltage drop, and the higher the leakage current of the diode in reverse direction.
This is the case for all diode technologies, whether controlled by a metal
semiconductor junction as in the case of Schottky diodes or a pn junction as forrecovery rectifiers. In forward direction, the exponential dependence of theforward current on the forward voltage can be seen as a straight line on thelogarithmic scale. As a general approximation, a voltage drift of approximately−1.7mV per Kelvin increase can be assumed for the impact of temperature on VF(and approximately −2mV per Kelvin for recovery rectifiers). At higher currents, theimpact of the voltage drop across the epitaxial layer increases and limits thecurrent capability of the device. This leads to the observation that in this region,
the curves for almost all temperatures run together. In reverse direction (right
picture in Figure 10) there is also an exponential impact of the temperature on thereverse leakage current. Here, too, the exponential temperature dependence is not
limited just to Schottky devices; it is also the case for recovery rectifiers. It is alsointeresting to mention that the different diode technologies share the fact that the
breakdown mechanism in these devices is dominated by the avalanche breakdown.

IF (A)
10

Diode fundamentals

Schottky contact

2.3 Static behavior

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IR (A)
10 −
10 −
10 −

10

10 −
1

10 −
Tj = 175°C
Tj = 150°C
Tj = 125°C
Tj = 100°C
Tj = 85°C
Tj = 25°C
Tj = −40°C

10 −

Tj = 25°C
Tj = −40°C

Tj = 150°C
Tj = 125°C
Tj = 100°C
Tj = 85°C

10 −
10 −
10 −

10 −

10 −
0

0.2

0.4

0.6

0.8

0

10

20

30

VF (V)

40

50

VR (V)

Figure 10 | IV characteristics of PMEG045V150EPD. Left: forward characteristics,
right: reverse characteristics. Please note: all points are measured in pulsed mode,
excluding any self-heating of the device.

28

29

Now let us compare the static behavior of the different described diodetechnologies. Since the currents of the diodes in forward and reverse direction
naturally scale with the size of the die (strictly speaking with the size of the activearea), a normalization of the currents with respect to the die size is necessary inorder to have a fair comparison of the different technologies. And as the different
diode technologies are designed for different voltage ranges, it is also necessary tochoose a voltage range that is reasonably suitable for all technologies. For thisreason, Figure 11 shows the forward current density for several diode types used in
the 100V voltage range. The diode technologies under investigation are: 120V
silicon germanium, planar Schottky with a barrier height of 805meV, planar
Schottky with a barrier height of 665meV, 200V hyper fast recovery rectifier (hyper
fast recovery rectifiers are not available below 200V) and finally 100V Trench
Schottky with a barrier height of 750meV. In this graph, the forward current isnormalized with respect to the active area of the device. For Trench Schottky
devices this means that the currents are normalized with respect to the sum of all
mesa areas.
As expected, the forward voltage drop Vf is the highest for the hyper fast recovery
rectifier for a given current density. The reason is obvious: the built-in voltage
across the pn junction needs first to be equalized before a significant amount of
current starts to flow. Thanks to the bipolar nature of the hyper fast recovery
rectifier, these devices show a distinctive current-carrying capability up to highcurrent densities.
The advantage of silicon germanium technology described in 2.2.4 can also be seenin Figure 11 as the SiGe diode exhibits significantly more current density for a given
forward voltage compared to the hyperfast recovery rectifier. So, if the die size islimited by a specific type of package (and thus by the maximum die size in thispackage) it can be advantageous to use a SiGe die instead of a recovery diode inorder to get more current out of the given package.
Now let’s have a look at the unipolar devices in Figure 11. In a Schottky diode, theforward current is transported via thermionic emission. The majority carriers haveto overcome the barrier height in order to transport the current. Therefore, thehigher the barrier height the higher the necessary forward voltage for a given
current density. This is the reason why the planar Schottky device with a barrierheight of 805meV exhibits the highest forward voltage drop amongst theinvestigated Schottky diodes. The planar Schottky with a barrier height of 665meV
has a low forward voltage drop for low current densities, however the curve30

flattens out very quickly. This is due to the thick drift layer of this 100V device withsuch low barrier height, which is necessary to achieve the required breakdown
voltage and to control the leakage current in reverse direction. This thick drift layer
leads to a significant voltage drop across this layer at higher current densities,
limiting the current transport capability of the diode. This is already described in
section 2.1 which details why the reverse blocking voltage of Schottky diodes islimited to a voltage range of 150–200V. Otherwise very high barrier heights would
be necessary for higher reverse voltages, which, in turn, would increase theforward voltage drop and diminish the current capability.

Diode fundamentals

In contrast to tunneling breakdown, the breakdown voltage caused by avalanche
effect increases with temperature, as the rate of scattering mechanisms for theelectrons increases with temperature, reducing the energy of the charge carriers
and thus reducing the avalanche effect.

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2

10
25°C
10

1

10 −
120 V SiGe Rectiﬁer
100 V planar Schottky | φB = 805 meV
100 V planar Schottky | φB = 665 meVHyperfast 200 V recovery rectiﬁer
100 V - Trench Schottky | φB = 750 meV

10 −

10 −
200

300

400

500

600

700

800

900

1000

1100

1200

VF (mV)
Figure 11 | Pulsed forward current density (normalized forward current
with respect to the active area) for different 100V technologies at room temperature.

Section 2.2.3 describes that, because of the RESUR effect, Trench Schottky devices
can have a significantly higher doping level in the drift layer compared to theirplanar counterparts, without suffering penalties regarding breakdown voltage orleakage current. This can be seen in Figure 11. The Trench Schottky device with abarrier height of 750meV has a higher forward voltage drop for low current
densities compared to the planar Schottky with a barrier height of 665meV.
However the curve doesn’t flatten when the forward voltage is increased – as incase of the planar Schottky. This is due to the higher doping of the drift layer,
resulting in significantly less voltage drop across the drift layer. The low-ohmic drift
layer reveals yet another phenomena, the so-called ‘hole-injection’. There are holes
above the Fermi level in the Schottky metal which can be injected from the metal
into the semiconductor (equivalent to valence band electrons in the semiconductor
acquiring enough thermal energy to leave the silicon and enter into one of the31In equilibrium or in low forward voltage bias, the injected holes are ‘trapped’ in a
potential well below the valance band. But if the Schottky diode is under strong
forward bias, the holes can leave the potential well and contribute to the current in
the device. So, surprisingly, the unipolar Schottky diode can also have a bipolar
component under strong forward bias, especially for high barrier types. This can beseen in Figure 11 for the Trench Schottky device at around 700mV forward bias.
The whole injection can also be observed for the planar Schottky diode with thebarrier height of 805meV at around 750mV, whereby it is less pronounced, as ahigher forward voltage would be necessary in order to drive this device into strong
forward bias.
The forward characteristics is Figure 11 were all measured at room temperature. At
higher temperatures the curves will of course shift but the order and the discussed
tendencies will remain intact.
Now let’s consider the reverse characteristics of the same devices which werediscussed in forward bias. Again, for this comparison of different technologies it isappropriate to normalize their reverse currents with respect to the active area ofthe die. However, a graphic of the leakage current density at all temperatures andall voltages fr all technologies would quickly become very confusing. For thisreason we have concentrated on a fixed voltage and will discuss development of
the leakage current density over the temperature range for a fixed voltage. A
reverse bias voltage of −60V has been chosen for comparing the reverse
characteristics of the different 100V technologies. −60V is high enough to reflect
the blocking capability of the diodes but also low enough not to be affected by the
incipient breakdown of the device.
The result is displayed in Figure 12. The hyper fast recovery rectifier, a device basedon a pn junction, has a very low leakage level. The leakage current density increases
approximately one order of magnitude for every 40°C increase in junction
temperature. Interestingly, the leakage current density for the SiGe diode is evenbelow the level of the recovery rectifier up to a junction temperature of 90°C. The
rate at which the leakage current of the SiGe diode increases is steeper than for thehyper fast recovery rectifier. This is due the hybrid nature of the SiGe diode, also
featuring a Schottky contact. Overall, the level of the leakage current density for
the SiGe diode is very low, comparable to the hyper fast recovery rectifier. Together
with the advantages already discussed over the hyper fast recovery rectifier in the32

forward direction (see Figure 11), the value proposition of the SiGe diode becomesapparent. With regard to Schottky diodes, the influence of the electron barrierheight as the determining factor can be seen quite clearly. As expected the planar
Schottky device with the lowest barrier height (665meV) shows the highest leakage
current density, which again illustrates the well-known trade-off between theforward voltage drop and the leakage current for Schottky diodes. The exponential
dependence of the leakage current on the barrier height leads to a significantly
reduced leakage current levels for the device with the barrier height of 805meVcompared to the one with 665meV. In the case of the trench diode, despite theadvantages in the forward direction, there are no disadvantages in the reverse bias.
The leakage current is determined by the barrier height and the trench technology
helps to control the course of the leakage current over the reverse voltage despite
the high doping level in the epitaxial drift layer. (This is not shown in this graph,please refer to a Trench Schottky diode data sheet.)

Diode fundamentals

empty states above Fermi level in the metal, leaving behind a hole in the valenceband). The barrier height for these holes entering the semiconductor is nothigh – just the difference between the band gap energy of silicon and the barrierheight for the electrons. This, in turn, means that the hole injection is higher whenthe metal work function of the chosen Schottky metal is higher (‘low leakage’
Schottky metals have more hole injection).

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Diode fundamentals

2

1
10 −
10 −
10 −
10 −
10 −
10 −
10 −
10 −
120 V SiGe Rectiﬁer
100 V planar Schottky | φB = 805 meV
100 V planar Schottky | φB = 665 meVHyperfast 200 V recovery rectiﬁer
100 V - Trench Schottky | φB = 750 meV

10 −
10 −
10 −
0

50

100

150

200

TJ (°C)
Figure 12 | Dependence of the leakage current density (normalized leakage current
with respect to the active area) at a reverse bias voltage of −60V on the junction temperaturefor different 100V technologies.

33

2.4.2 Reverse recovery

2.4 Dynamic behavior
In many applications, a diode is not operated statically, but it is switched on and off
continuously. The switching performance of the diode is critical for the efficiency ofa system, such as, for example switched-mode converters.

2.4.1 Forward recovery
When a diode is switched on, it takes some time for the low-doped drift zone tobecome flooded with charge carriers. Thus, an increased initial forward voltage
drop can be observed when the diode is switched on, because the drift zone does
not yet have the necessary conductivity. This so-called forward recovery of thediode is characterized by the parameter VFRM which describes the switch-on
voltage peak and the forward recovery time tfr. Depending on the thickness anddoping of the drift layer, the forward recovery can be quite noticeable and must be
considered during circuit design.

dlF
dt

trr

time
25%

Qrr

IR

Reverse recovery describes the dynamics with which the diode switches from theforward direction into the reverse blocking stage. When the diode is biased in theforward direction, the bulk material is flooded with charge carriers. If the polarityof the voltage across the diode is now reversed, it takes a finite amount of time
until these excess charge carriers are removed. Only then can the space-charge
region build up and the reverse voltage can be taken by the diode.
Figure 13 illustrates the defined parameters of the ramp reverse recovery. First, thediode is biased in forward direction, carrying the current IF. It is obvious that thelevel of the forward current has a significant impact on the excess charge in thedevice and therefore on the dynamics of how fast the stored charge can beremoved. This impact will be discussed later in detail. The rate di/dt defines how
fast the forward current through the diode is switched off. Here, too, it is evident
that a higher di/dt places higher demands on the switching performance of thediode. As shown in Figure 13, the current through the diode even passes the zeroline and becomes negative. Notice that at this point that there is still excess charge
in the device and no space-charge region has yet built up. The space-charge region
starts to build up when the maximum reverse current IRM is reached, and then it willtake over the reverse voltage. The negative current starts to decrease while thereverse voltage across the diode starts to increase. Eventually the negative current
through the device adjusts to the leakage current of the diode. The time between
the point when the current crosses the zero line and becomes negative and thepoint in time when it reaches 25% of the maximum reverse current IRM (this point
being extrapolated linearly as shown is the graph – in some data sheets 10% is
specified instead of 25%) is called reverse recovery time trr. The next importantparameter is the stored charge Qrr in the device which corresponds to the area
below the horizontal zero line (the integral of the diode current within trr).

100%

IRM
SwitchFigure 13 | The ramp reverse recovery definition for diodes.

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VR

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After defining the parameters of theramp reverse recovery let’s have a look
how these parameters impacts theswitching losses in a switched-mode
converter.

DUT

RshuntLσ

34

iF

Figure 14 | Double-pulse test:
basic circuit used for characterizing
the switching behavior of the diode.

35

t1

t2

t3

t4

IF + IRM

2.5 Benchmarking of different
technologies in terms of switching
In this section the switching behavior of different diode technologies will bepresented and discussed. As an informative introduction, the operating points andevaluation parameters as well as their calculation method are first presented.

ISwitchIF

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Diode Application Handbook

VDS

2.5.1 Evaluation parameters
dt
dI/
VSwitchVF

t
QRR

IDiodeIRM
VDiodeVR

Unlike the operating parameters which are manually set beforehand, evaluation
parameters are extracted and calculated from the measured current trajectory.
They directly represent the switching performance.
Figure 16 shows an approximated reverse recovery current trajectory. The
corresponding explanation of the numbers provides the definitions of theevaluated parameters which were extracted and used for the evaluation of thediode performances (which are number 1 to 5).

36

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Figure 15 | Graph showing current and voltage waveforms of a diode andthe associated switch during the diode turn-off phase.

Figure 14 shows a double pulse testing circuit. Double pulse testing is the standard
method for measuring the switching performance of a semiconductor device. It
consists basically of a switch which is used to charge the inductance with magnetic
energy. By adjusting the width of the first pulse, the required current through theinductance is set while the diode is biased in reverse direction. Then the switch isturned off and the second pulse turns on the device under test (DUT). At this point,
the turn-on behavior of the diode can be investigated (forward recovery). Now thecurrent is flowing through the diode. At a given point, t1 as shown in Figure 15, theswitch turns on and starts to turn off the current through the diode with thedefined di/dt ramp. As discussed, the diode current will even turn negative andintersects the x-axis at t2. At this point the switch is still carrying the entire input
voltage. Only at time t3 is the maximum reverse current reached and the spacecharge region of the diode begins to form. Now the diode starts to take over thevoltage. From this point on, power loss needs to be dissipated in the diode,contributing to switching losses of the circuit. As seen at t3 the switch must not
only carry the current IF, but also the recovery current IRM of the diode, which
increases the switching losses in the switch further. At t4 the space-charge region in
the diode is fully built up and the reverse voltage across the diode equalizes to the
input voltage.

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2

1

4

Zero

5

0.10 IRM

3
2

Figure 16 | Schematic of the reverse recovery trajectory with the corresponding parameters.

1.	IF – Forward conduction current
2.	diF/dt – Rate of diode current change through zero crossing
3.	IRM – Maximum reverse recovery current
4.	trr – Reverse recovery time, measured from zero crossing where the diodecurrent changes from positive to negative, to the point at which the straight line
through IRM and 10% of IRM passes through zero (10% level used for following
measurements).
5.	Qrr – Reverse recovery charge: area under the curve defined by IRM and trr
6.	Softness factor SFrr – Quotient of di/dt before IRM occurs divided by
di/dt after IRM occurs

37

Operating points –switching performance

Units for all the following tablesof the evaluation parameters:

The following list gives an overview ofthe different parameter variations
under which the reverse recovery wasmeasured and compared:• Qrr is given in [nC]
• IRM is given in [A]• trr is given in [ns]• SFrr is dimensionless

Different parameter variations
Current edge steepness(in A/ns)−0.4(±20%)−0.7(±20%)−1(±20%)

DC link voltage (in V)

24

48

75

Turn-off current (in A)

1

3

5

Case Temperatures (in °C)

−40

25

85

Table 1: Rated current and voltage of the compared devices.
Technology

Voltage /current Rating

Package

PMEG120G30ELP

Silicon germanium

120V / 3A

SOD128PNE20030EP

Hyper fast recovery

200V / 3A

SOD128RB058LAM150TR

Planar Schottky

150V / 3A

SOD128PMEG100T30ELP

Trench Schottky

100V / 3A

SOD128

Product

2.5.3 Impact of temperature on the switching performance
90

150

Please notice that there is a ‘cross-influence’ of the listed operating parameters. As
an example, the turn-off current proportionally increases the current edge
steepness di/dt, without any other changes in the gate circuit. Once the influenceof changing the turn-off current or dc-link voltage exceeds a set limit, the gate
resistor must be adjusted in order to guarantee as similar slope gradients as
possible. Therefore, small variations in the di/dt values can be avoided. For thatreason, the edge steepness parameters are given in ranges in which the di/dt
values were held for the specific measurements. Nevertheless, comparability in thefollowing measurements is guaranteed within each set of measurements, as theoperating conditions were absolute equal and therefore free of di/dt variations orother cross-interferences. Here, a set is defined as the measurement of all diodes
at the same operating point.

Figure 17 depicts the forward current IF
during the transition from forward bias
into reverse direction for a dc-link
voltage of 48V and a turn-off current of
3A, at room temperature and at 150°C
case temperature. Only thetemperature as an operating parameter
was varied as stated below. The key
factor in this comparison is the very
steep current slope of di/dt = −1A/ns
which is very close to the realapplication and 5 to 10 times higher
compared to usual test conditions indatasheets.

IDIODE (A)
6
4
2
0
−2
−4
−6
−8

Tc = 25°C
Vdc = 48V
di/dt = −1A/ns

PMEG120G30ELPPNE20030EP
RB058LAM150TR
PMEG100T30ELP−10165 170 175 180 185 190 195 200 205 210
64

2.5.2 Sample selection

Fixed operating parameter:
Vdc = 48V
IF = 3A
di/dt = −1 (±20%)

The different diode technologies investigated in this section are: silicon
germanium, Trench Schottky, Planar Schottky and reverse recovery diode. Table 1
summarizes the chosen products.

Varied operating parameter:
Case temperature –Tc = [ −40°C, 25°C, 85°C , 150°C ]Naturally, the competing devices for analysis were selected to have as similar
operating ranges as possible and the same packaging (SOD128). As no 100V
recovery rectifiers were available for the chosen current range, 200V types wereused instead.

38

2

Diode Application Handbook

Diode fundamentals

nexperia | Design Engineer’s Guide

aaa-034526

Diode fundamentals

2

2
0
−2
−4
−6
−8

Tc = 150°C
Vdc = 48V
di/dt = −1A/ns−10
165 170 175 180 185 190 195 200 205 210

Time (ns)Figure 17 | Reverse recovery current fordifferent technologies at room temperature
and at 150°C case temperature.
Vdc = 48V, IF = 3A and di/dt = −1A/ns.

39

nexperia | Design Engineer’s Guide

Table 2 lists the corresponding
evaluated parameters Qrr, Irrm, trr andSFrr which were derived from thefigures above.

2.5.4 Why is the Trench Schottky diode superior in terms of switching

Units for all the following tablesof the evaluation parameters:• Qrr is given in [nC]
• IRM is given in [A]• trr is given in [ns]• SFrr is dimensionless

Table 2: Reverse recovery evaluation parameters for different
temperatures. Other operating parameters kept constant at
Vdc = 48V, IF = 3A and di/dt = −1A/ns.
Product

Qrr @ T =IRM @ T =

−40°C

25°C

85°C

150°C

−40°C

25°C

85°C

150°C

PMEG120G30ELP

13.6

19.1

25.5

33.1

4.02

4.42

4.87

5.3

PNE20030EP

25.8

37.3

52.1

80.5

6.28

7.11

8.12

9.24

RB058LAM150TR

11.9

26.3

33.5

41.6

5.18

5.18

5.2

5.25

PMEG100T30ELP

4.8

4.7

6.8

14

2.3

2.1

2.3

3.32

Product

trr @ T =SFrr @ T =

−40°C

25°C

85°C

150°C

−40°C

25°C

85°C

150°C

PMEG120G30ELP

6.4

8.24

9.7

11.2

0.66

0.87

0.94

0.96

PNE20030EP

8.2

11.1

13.6

18

0.59

0.82

0.94

1.17

RB058LAM150TR

5.3

10.6

12

14.2

0.36

1

1.19

1.37

PMEG100T30ELP

3.6

3.8

4.9

6.9

0.36

0.42

0.44

0.34

Key observations
For nearly all operating points, the Trench Schottky diode outperforms all othercompeting diodes. This holds for Qrr, IRM and trr values. As a trade-off compared tothe other technologies, the Trench Schottky diode shows a higher snappiness andsubsequent oscillation. It is also remarkable that the 120V SiGe diode has lessstored charge than the 150V planar Schottky diode, in spite of the very low leakage
current that this product has. As expected, the hyper fast recovery rectifierswitches the slowest and has the highest amount of stored charge. Here thebipolar nature of the hyper fast diode becomes noticeable despite the life-timekilling material in the epitaxial layers. However, one should also note the smoothswitching of this hyper fast diode.

40

Diode Application Handbook

The measurements in Figure 17 illustrate the superior performance of Trench
Schottky diodes in terms of switching when compared to all other technologies.
A look at the data sheets shows that the Trench Schottky diode even shows thehighest parasitic capacitance compared to all the other products. In this respect thequestion arises how this happens. The answer can be found in Figure 8. As shown inthe cross section, there is no guard ring in the termination design for the 100V
Trench Schottky diodes. The impact can be best be investigated by using physicaldevice simulations. For this reason, the switching behavior of the planar Schottky
diode PMEG10030ELP and of the Trench Schottky diode PMEG100T030ELP was
simulated. The simulated switching performance is illustrated in Figure 18. Device
simulations confirm the measured superior switching performance of the Trench
Schottky diode PMEG100T030ELP compared to its planar counterpart
PMEG10030ELP. In the device simulation it is easy to omit the guard ring of theplanar Schottky diode and to investigate the impact of the guard ring on theswitching performance. The blue curve in Figure 18 shows the planar diode without
the guard ring. In fact, the planar Schottky diode without guard ring is now
approaching the Trench Schottky diode. However there is still a gap between theplanar Schottky diode without guard ring and the Trench Schottky diode in terms of
Qrr and trr. Obviously, the missing guard ring in the Trench Schottky device can
explain a large part of the difference, but not all. The second factor why the
Trench-Schottky diode switches much faster and with less stored charge is thesignificant size difference of the active areas. For a fair comparison of the die sizes,
it is necessary to subtract the dead area caused by the trenches from the active
area of the Trench Schottky diode, comparing only the effective active area thatreally contributes to the forward current to that of its planar counterpart. This isshown in Figure 19. This way to compare the active areas reveals that the Trench
Schottky PMEG100T030ELP occupies only 44% of the active area of its planarcounterpart PMEG10030ELP. In summary, the superior switching behavior of theTrench Schottky diode can be explained by the lack of a guard ring with a parasitic
pn junction and by its much smaller active area compared to other devices. Please
notice that the impact of the guard ring on the switching behavior is very much die
size dependent, as the area of the guard ring with a fixed width increases linearly,
while the active area itself increases exponentially with increasing die pitch. So thebigger the die size the less pronounced is the impact of the guard ring on theswitching performance. The influence of the guard is also dependent on how far
the diode is biased in the forward direction, and thus how much the guard ring is
triggered to conduct current. We will see in 2.5.6 that this has a huge impact on theswitching performance.

2
Diode fundamentals

Diode fundamentals

241

PMEG100T030ELP
PMEG100T030ELP
PMEG10030ELP
PMEG10030ELP
PMEG10030ELP w/o guarding
PMEG10030ELP w/o guarding

Vdc = 48V
di/dt = −1A/ns

Diode fundamentals−10

If only the ‘’effective’’ active surface
area is considered:
APMEG100T030ELPAPMEG10030ELP

= 44%

Anode

Abbildung Kontur 0,5 pt
Abbildung fett 1 pt
Beschriftung/Pfeil 0,3 pt
Grid
Grid gestrichelt

aaa-034791

2.5
2.0

Figure 19 | For a fair comparison of the die
sizes, only the effective active areas should becompared. Using this method to compare active
PMEG120G30ELP
areas reveals
that the Trench Schottky
IR (A)
PNE20030EP
RB058LAM150TR
PMEG100T030ELP
occupies only 44% of the
PMEG100T30ELP
active area of its planar counterpart−0
PMEG10030ELP.
Tc = 25°C

aaa-034527

The reason for the switching behavior is now clarified. But the question still
remains: why is the parasitic capacitance of Trench Schottky diode so large and why
it is not affecting the switching performance? This can again be answered with alook at the cross section of the device. The cross section of a Trench unit cell isshown in Figure 20, together with the resulting equivalent circuit diagram of thecell. In this Figure one can see the parasitic capacitance Cdiode that exists in each
Schottky diode due to the metal-semiconductor junction in the device. However,with Trench Schottky diodes there is a second parasitic capacitance in the device
structure. Called CTrench, this capacitance is caused by the thin dielectric in the
trenches which are filled with poly silicon. This high parasitic capacitancecontributes to the overall parasitic capacitance of the Trench Schottky diode,resulting in a high specified parasitic capacitance in the data sheet. However theparasitic capacitance CTrench can be quickly charged and discharged through thehighly doped poly silicon layer in the trenches. It is not affected by the dynamics ofcharge carriers in the drift region, which is the case for the capacitance Cdiode.

2

Diode Application Handbook

aaa-034528

nexperia | Design Engineer’s Guide

IDiode (A)Diode fundamentals

2

RTrenchCDiode1.5

CTrench1.0
0.5

RDrift0Cathode

−0.5
−1.0
−1.5
10 −

Figure 20 | Cross section of a unit cell in a Trench Schottky diode and the resulting
equivalent circuit diagram of the Trench Schottky diode. The thin dielectric in the Trenches
contributes to a high overall parasitic capacitance of the Trench Schottky diode.

VR = −48V
25°C
10 −

10 −

10 −

10 −

10 −

Time (s)Figure 18 | Simulated ramp reverse recovery of three different diodes.
PMEG100T030ELP (Trench Schottky), PMEG10030ELP (planar Schottky) and
PMEG10030ELP without guard ring.

42

43

2

Diode Application Handbook

In this section the reverse recovery process is evaluated for different values of theslope steepness di/dt. Figure 21 shows the decrease to di/dt = −0.4A/ns as areference. The quantified parameter including the ones for di/dt = −0.7A/ns arelisted in Table 3.

The diodes were also tested for different turn-off currents. The turn-off current hasa significant influence on the di/dt and therefore on the reverse recovery process.
Figure 22 illustrates the reduced turn-off current of 1A. The evaluated parameter
for a higher turn-off current of 5A where no ranking changes occur, is listed inTable 15.

Varied operating parameter:
Slope steepness:
di/dt = −0.4A/ns
di/dt = −0.7A/ns

4
PMEG120G30ELPPNE20030EP
RB058LAM150TR
PMEG100T30ELP

3
2

0
−1

−3

Figure 21 | Reverse recovery current forlower current slope steepness of −0.4A/ns.
Other operating parameters kept constant at
Vdc = 48V, IF = 3A and Tc = 25°C.

Tc = 25°C
Vdc = 48V
di/dt = −0.4 A/ns

−4
170 175 180 185 190 195 200 205 210 215 220 225

Time (ns)Table 3: Reverse recovery evaluation parameters for slope steepness.

3
2
1
0

Varied operating parameter:
Turn-off current:
IF = [1A ; 5A]

1−2

Fixed operating parameter:
Vdc = 48V
Tc = 25°C
di/dt = −1 (±20%)

IDIODE (A)Fixed operating parameter:
Vdc = 48V
IF = 3A
Tc = 25°C

aaa-034531

2.5.6 Impact of the turn-off current on switching performanceaaa-034530

2.5.5 Impact of the slope gradient on switching performance

Diode fundamentals

nexperia | Design Engineer’s Guide

IDIODE (A)Diode fundamentals

2

-1
-2
-3
-4
-5

Figure 22 | Reverse recovery current
for 1A turn-off current. Other operating
parameters kept constant at
Vdc = 48V, Tc = 25°C and di/dt = −1A/ns.

-6
160

PMEG120G30ELPPNE20030EP
RB058LAM150TR
PMEG100T30ELP

Tc = 25°C
Vdc = 48V
di/dt = −1A/ns
165

170

175

180

185

190

195

Time (ns)Table 4: Reverse recovery evaluation parameters fordifferent turn-off current.

Other operating parameters kept constant at Vdc = 48V, iF = 3A and Tc = 25°C.
Product

Qrr @

IRM @

trr @

SFrr @

A/ns

−0.4

−0.7

−0.4

−0.7

−0.4

−0.7

−0.4

−0.7

PMEG120G30ELP

12.6

15.4

2

2.8

13.4

11.4

1.5

1.3

PNE20030EP

22.7

28.3

3.1

4.4

16.8

14.6

1.2

1.1

RB058LAM150TR

20

22.7

2.4

3.3

18.7

14.6

1.7

1.4

PMEG100T30ELP

2.5

3.3

0.8

1.3

5

4.4

0.78

0.5

Key observations
The Trench Schottky diode also remains superior to all competing technologies atlower switching speeds. Nothing else changes in the order in terms of switching
speed and amount of stored charge, with SiGe in second place and planar Schottky
and hyperfast diode in third and fourth place.

44

Other operating parameters kept constant at Vdc = 48V, Tc = 25°C and di/dt = - 1A/ns.
Product

Qrr @

IRM @

trr @

SFrr @

iF =

1A

5A

1A

5A

1A

5A

1A

5A

PMEG120G30ELP

7.5

31

3

6.1

4.7

9.4

0.73

0.74

PNE20030EP

17.6

50.6

5.5

8.6

6.4

12

0.5

0.77

RB058LAM150TR

5.5

49

2.7

7.4

3.8

12.3

0.4

0.88

PMEG100T30ELP

4.3

6

2.1

2.6

3.4

4

0.36

0.4

Key observations
The investigated products have a nominal current rating of 3A. The higher turn-off
current results in a higher forward voltage drop, triggering the parasitic pn junctionin the termination area even more. Therefore, as shown in Table 4 there is asignificant increase at 5A turn-off current for all diode technologies that use theguard-ring as termination concept in terms of Qrr, Irrm and trr values. The impact on
Trench Schottky diodes is much less pronounced due to the lack of pn junction in
the device structure. At the same time, it is also very important to note that at

45

4
2

60

40

-2

30
20
PMEG120G30ELPPNE20030EP
RB058LAM150TR
PMEG100T30ELP

-6
-8
-10
170

Tc = 25°C
Vdc = 48V
di/dt = −1A/ns

50

0

-4

In summary, next to ambient temperature, the turn-off current has the greatest
influence on switching behavior of the diodes and should be taken into accountduring circuit design.

70

180

190

200

210

220

PMEG120G30ELPPNE20030EP
RB058LAM150TR
PMEG100T30ELP

10
0
−10
170

230

180

190

200

210

220

Diode fundamentals

Tc = 25°C
Vdc = 48V
di/dt = −1A/ns

aaa-034532-2

6

VDIODE (A)Diode fundamentals

lower turn-off current of 1A (well below the current rating of the products) theadvantage of the Trench-Schottky diode diminishes, as the parasitic pn diode loses
importance in the structure of the other diodes. As shown in Table 4 for 1A turn-off
current, the planar Schottky product is almost on par with the Trench Schottky interms of Qrr, Irrm and trr. This is consistent with the simulation results discussed in
2.5.4. Consequently, depending on the current level and the current density of thedevice, in addition to the switching frequency, duty cycle and temperature, theoptimal diode technology for each application may be a different one.

2

Diode Application Handbook

aaa-034532-1

nexperia | Design Engineer’s Guide

IDIODE (A)2230Time (ns)Time (ns)6
Tc = 25°C
Vdc = 90V
di/dt = −1A/ns

4
2

90
80

50
40

−4

30
PMEG120G30ELPPNE20030EP
RB058LAM150TR
PMEG100T30ELP

−6
−8
−10
170

Tc = 25°C
Vdc = 90V
di/dt = −1A/ns

100

60

−2

Table 5: Reverse recovery evaluation parameters fordifferent dc-link voltages Vdc

110

70

0

Varied operating parameter:
dc link voltage:
Vdc = [48V ; 90V]

aaa-034532-4

IDIODE (A)Fixed operating parameter:
IF = 3A
Tc = 25°C
di/dt = −1A/ns (±20%)

VDIODE (A)In this section, the variation of the
dc-link voltage is investigated andpresented. The reverse voltage during
the switching process is depicted on theright side in Figure 23 next to thecorresponding current trajectory.
Quantified results are presented inTable 5.

aaa-034532-3

2.5.7 Impact of the reverse voltage on switching performance

PMEG120G30ELPPNE20030EP
RB058LAM150TR
PMEG100T30ELP

20
10
0
-10

180

190

200

210

220

230

170

180

190

200

Time (ns)

Diode

46

Qrr @

IRM @

trr @

SFrr @

Vdc=

75V

90V

75V

90V

75V

90V

75V

90V

PMEG120G30ELP

19.3

19.3

4.1

4.1

8.6

8.9

0.93

0.74

PNE20030EP

38.1

37.9

6.8

6.6

12

12.3

0.93

0.96

RB058LAM150TR

27.3

27.4

5

4.8

11.1

11.3

1.1

1.1

PMEG100T30ELP

4.5

4.5

2

1.9

3.8

3.8

0.42

0.45

210

220

230

Time (ns)Figure 23 | Reverse recovery and reverse voltage for different dc-link voltages.
Fixed operating parameters IF = 3A, Tc = 25°C, di/dt = - 1A/ns

Key observations
The trajectories of the voltages are consistent with the corresponding current
curves, both in terms of oscillation and slope steepness. The performance ranking
among the diodes remains unchanged from the first observations with the Trench
Schottky diodes being dominant in terms of Qrr, Irrm and trr. The 120V SiGe producttakes second place and remains ahead of the Planar Schottky and the hyper fast
recovery diodes.

47

2

Diode Application Handbook

Energy Gap

Si
4H-SiCin eV

2.6.1 Introduction

5

Silicon carbide, often simply abbreviated as SiC, is a compound semiconductor thatconsists of both silicon and carbon atoms. Unlike other materials, silicon carbide
exists in many crystal structures. This phenomenon is called polymorphism. For SiC,
more than 250 different polytypes are known. Each polytype has its own uniqueproperties. For commercial power electronic power devices, the polytype 4H-SiC is
predominantly used. The arrangement of a 4H-SiC crystal is depicted in Figure 24.

a = 0.31nm

C atomc/n = 0.25nm

Si atomaaa-033941

2.6 SiC rectifier

A
C

4
3

Melting Point

Electric Field2

in ×1000 °C

in MV/cm

Diode fundamentals

nexperia | Design Engineer’s Guide

10

aaa-033940

Diode fundamentals

2

B
C

A

B

B

B

A

C

A

B

A

C

C

C

B

B

B

A

A

A

C

3C-SiC

4H-SiC

6H-SiC

Figure 24 | SiC polytypes

4H-SiC crystal structure, later simply called SiC, has several material benefits oversilicon. These are leveraged in modern high voltage diodes to specifically createhigh performance diode solutions for switched-mode power conversion
applications. Significant application examples include:• Switched-mode Power Supplies (SMPS)• On-Board Chargers (OBC)• Inverters (Traction & Photovoltaic)• Charging Stations• Electric Aircraft Propulsion• Uninterruptible Power Supplies (UPS)48

Electron Velocity
in 10 cm/s

Thermal Conductivity
in W/cmK

Figure 25 | Comparison of Si and SiC material properties.

2.6.2 Material properties of 4H-SiC
Compared to Si and as depicted in Figure 25, SiC has an energy gap around threetimes higher, and a ten times higher dielectric breakdown field strength. The
electron velocity is also more than twice as high as it is for silicon. Besides theseelectrical benefits, the thermal performance of SiC is also advantageous. Both thethermal conductivity (SiC 4.9W/cmK vs Si 1.5W/cmK) and also the melting point(SiC 2700°C vs Si 1400 °C) are much higher.
These superior material properties are utilized to manufacture power
semiconductors which exceed the performance of their Si-based counterparts andpermit operation even under harsh environmental conditions.
As far as power diodes are concerned, the combination of the ten times higher
dielectric breakdown field strength and the nearly three times higher energy gap
are utilized for a new sort of power diode which is perfectly-made for switch-mode
applications. A detailed description on how SiC’s material advantages positively
affect power diodes’ performance will follow in the next section.

49

2.6.3 SiC enabling superior power diodes andchanging the high voltage diode landscape
As a consequence of SiC’s ten times higher dielectric breakdown field strength, amuch thinner drift layer is sufficient to achieve the same blocking voltage, ascompared to silicon-based devices. A simplified explanation is shown in Figure 26,
assuming a Schottky-metal contact for both silicon and silicon carbide materials.
Another aspect refers to the possible higher doping concentration which lowers
the resistance of the already thinner drift layer even more. In theory, SiC can reduce
the resistance per unit area of the drift layer to 1/300 of that of Si for the same
breakdown voltage. Therefore, at a given current rating, SiC diodes can be
manufactured with a lower voltage drop and smaller die size. This results in better
conduction, and also, due to the smaller die size and lower switching charge, fasterswitching time and lower switching losses. These SiC benefits become technicallyand commercially relevant at blocking voltages of 600V and above.

|E|
SiC᾿s breakdown
electric ﬁeld
strength~ 3MV/cm

Area = blocking voltage

Same voltage class!

Si᾿s breakdown
electric ﬁeld
strength~ 0.3MV/cm

x

SiC
SBD

metal

Si
SBD

metal

drift
layer

Same
voltage
class
drift
layer

Figure 26 | SiC dielectric field strength and energy gap advantage.

50

Diode Application Handbook

Figure 27 shows the split between Si and SiC diode technologies against blocking
voltage. On the left, conventional Si-based technologies are depicted. In the
Si-domain and below 100V diodes utilizing the advantageous properties of
Schottky-metal contacts are usually the dominant solution. They offer a very low
cut-in voltage and, due to the majority carrier based conduction mechanism, analmost purely capacitive – and therefore very fast – switching behavior. Between
100V and 200V the leakage currents and thus the thermal stability of Si Schottky
diodes becomes more and more challenging to control. Additionally, the influenceof the drift layer resistance rises significantly so that at a blocking voltage range ofaround 100V to 200V, the transition from Schottky-based diodes towards PN-based
diodes takes place. Due to the bipolar nature of PN diodes, the thermal stability ishigher compared to unipolar devices. However, due to the presence of minority
carriers, stored charges lead to reverse recovery effects, higher switching times
and thus higher losses in switched-mode operation. Therefore, in silicon and atblocking voltages of 600V and above, only PN-based rectifiers are available.
Switched-mode applications in this voltage range must, therefore, deal with thementioned disadvantages of the silicon PN diodes. As a consequence, the efficiency
of certain power applications cannot be further improved because Si-based PN
diode solutions have reached their physical limitations.

2
Diode fundamentals

nexperia | Design Engineer’s Guide

aaa-033942

Diode fundamentals

2

On the other hand, with SiC and its higher energy gap, Schottky power diodes canstill be manufactured with low leakage current and high thermal stability atblocking voltage levels of 600V and above. As a consequence, SiC allows the
exploitation of the advantages of unipolar Schottky-contact based power diodes involtage ranges where Silicon-based power diode counterparts are already bipolar
devices. This means that at blocking voltage levels between 600V and 1700V, SiC
can make use of its two major advantages compared to Silicon, the lower voltage
drop and the better switching performance. Firstly, this is originated by the thinner
drift layer and smaller die sizes at a given current as already shown in Figure 26. The
drawback of the higher energy gap and the resulting high cut-in voltage iscompensated with the much smaller required drift layer and the utilization of the
Schottky-diodes’ semiconductor-metal junction.
Secondly, consider the ability to continue to make use of Schottky diode structuresat blocking voltage levels where silicon-based diodes are bipolar PN diodes. This
minimizes switching losses due to the absence of the comparably higher reverse
recovery charge compared to the lower capacitive charge of Schottky diodes.
Consequently, SiC Schottky diodes offer faster switching times than Si-based
competing diodes without compromising the conduction performance and thestability.

51

Schottky diode1200 V+ Lower VF+ Lower QC− Higher leakage− Lower IFSM

Change frombipolar to
unipolar device
Signiﬁcant lower
recovery loss andhigher frequency

PN diode− Higher VF− Higher QRR+ Lower leakage+ Higher IFSM

650 V
100 V

Si

In order to overcome the drawbacks of pure SiC Schottky diodes, Nexperia has
designed a hybrid SiC diode concept which combines the best of both worlds, see
Figure 28. The result is a product with the superior conduction and switching
performance of Schottky diodes and the higher thermal stability and surge current
robustness of bipolar diodes. This hybrid diode is called ‘Merged PIN Schottky’ or
MPS. A detailed explanation of the functionality of MPS diodes is given in the next
section.

Merged PIN Schottky (MPS):
A closer look into high-end silicon carbide power diodes

SiC
Schottky anode

Both

Figure 27 | Comparison of Si and SiC power diodes vs blocking voltage.

aaa-033944

Although pure SiC-based Schottky devices have a comparably low forward voltage
drop VF and fast switching times, the imperfections at the metal-semiconductor
interface lead to leakage currents higher than theoretically expected. Additionally,
the unipolar nature makes these devices susceptible to surge current situations
such as load dumps or line drop outs. As a consequence, a pure SiC Schottky diodeconcept doesn’t allow the exploitation of SiC’s full potential.

Voltage
1200 V
Change frombipolar to
unipolar device

100 V+ Lower VF+ Lower QC− Higher leakage− Lower IFSM

Combination of
Schottky diode(normal operation)n− SiC epi layer

andn+ SiC substrate

PN diode(surge current event)

Ohmic cathodeA simplified cross section of an MPS diode is shown in Figure 29. Unlike pure
Schottky devices, MPS diodes do not only possess a metal-semiconductor interface.
P-doped areas are also embedded within the drift zone which form a p-ohmic
contact with the metal at the Schottky anode and a PN junction with the lightly
n-doped SiC drift or epi layer. As depicted in the equivalent circuit in Figure 29, an
MPS diode monolithically possesses both a Schottky diode and a PN diode portion.
Both diodes contribute to the overall current depending on the mode of operation.
This will be described in detail later.

650 V

Schottky diodep+

Figure 29 | Simplified "Merged PIN Schottky" diode cross section and equivalen circuit.

Signiﬁcant lower
recovery loss andhigher frequencySip+aaa-033945

Voltage2

Diode Application Handbook

Diode fundamentals

nexperia | Design Engineer’s Guide

aaa-033943

Diode fundamentals

2

SiC
Nexperia’s
SiC MPS diodePN diode− Higher VF− Higher QRR+ Lower leakage+ Higher IFSM

+ Lower VF+ Lower QC/QRR+ Lower leakage+ Higher IFSM

Figure 28 | SiC MPS diode.

52

53

MPS in blocking operation
Another aspect of the MPS diode contributes to the blocking behavior. As shown in
Figure 30, the p-areas (also often called p-pillars or p-wells) stabilize such diodes
and reduce the leakage currents under reverse bias.

Anode

SiC merged PIN Schottky diodeMax ﬁeldstrength atmetal barrierHigh leakage
current

max


E
min

p+

p+

Max ﬁeldstrength indrift layern−Lower leakage
currentn+Blocking
voltage

Anode

Cathoden−

MPS in nominal forward operation and overcurrent events


E

n+

CathodeBlocking
voltage

Figure 30 | Comparison of e-field distribution of pure Schottky diodes & MPS at reverse bias.

The electric field strength distribution during reverse bias situations is depicted in
Figure 30 on the left-hand side, for a pure Schottky configuration. From thecathode side, the electric field strength gradually extends across the drift layer andreaches its peak at the metal-semiconductor interface at the anode side.
Consequently, the maximum electric field strength occurs at a location where acomparably high density of defects and imperfections are present. As aconsequence, these pure Schottky devices possess a relatively high leakage current
which can only be countered with a thicker drift layer than should theoretically beneeded. However, this is disadvantageous for lowest drift-resistance and hence fordiodes for power electronic applications.
The inserted p-areas in the MPS structure dramatically change the electric fieldstrength distribution compared to a pure Schottky structure. This is shown in theright-hand cross section of Figure 30. The depletion regions of the adjacent PN
junctions caused by the inserted p-areas deflect the maximum field strength, whichis shifted away from the metal interface into the drift layer region. The almost
defect-free area of this layer and the significantly reduced electric field strength
stress at the metal interface at the anode side significantly reduce the leakage
current compared to a pure Schottky counterpart of the same geometry and same
applied reverse voltage. The effectiveness of this pinch-off is determined by the
relative area and geometrical layout of the p-area implant, its doping

54

concentration, the spacing between adjacent p areas as well as the encompassed
Schottky area, and its metal-SiC barrier height. These are fundamental design
parameters that affect the device characteristics. A large p+ implanted area is
expected to result in a higher on-state voltage due to a smaller Schottky
conducting area, but may offer lower leakage due to a more effective pinch-off of
the Schottky portion. Alternatively, by keeping the leakage current and thegeometry of both – the pure Schottky diode and the Merged PIN Schottky diode –the MPS diode can operate at higher breakdown voltages without expanding thedrift layer and the associated drift resistance, which is electrically beneficial for
power applications in particular.

As previously mentioned, the inserted p-areas not only relieve the electric fieldstrength stress at the metal-semiconductor interface under reverse bias situations
to lower the leakage current. The associated pn junctions of the p-areas are also
designed such that they can also carry significant current in forward bias situations.
This feature is used to overcome the limitations of unipolar devices with theircomparably higher differential resistances compared to bipolar counterparts at agiven crystal size. In Figure 31, the MPS cross section, the equivalent circuit and the
I-V-curves of a pure Schottky, a pure PN and a MPS diode is shown as examples. As
shown in Figure 29 and Figure 31, an MPS diode possesses two monolithicallyintegrated diodes, the Schottky and the PN diode.

Schottky anodeaaa-033946

Pure SiC Schottky diode2

Diode Application Handbook

Diode fundamentals

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aaa-034533

Diode fundamentals

2

Equivalent circuit
Overcurrent event:PN supportsp+p+n− SiC epi layer

Pure
SchottkyIF

MPS
Normaloperation:
Schottky
only

PN
junctionn+ SiC substrate
VF,0S
Schottkyknee voltage

VF,0PNVF

PN
knee voltage

Ohmic cathodeFigure 31 | Merged PIN Schottky diodes under nominal and overcurrent situation.

55

nexperia | Design Engineer’s Guide

Diode fundamentals

Under nominal current conditions, the voltage drop of the MPS is so low that only
the Schottky area actively contributes to the overall current, and the integrated PN
diode remains inactive. This is indicated as the green current in the equivalentcircuit in Figure 31, where the forward current is only conducted through the
Schottky area of the MPS diode under a certain threshold. This is called ‘unipolar
mode’ and the device acts in pure Schottky mode with a low cut-in voltage andpurely capacitive switching performance. The corresponding low cut-in voltage of
the Schottky area and the PN junctions of the MPS area are indicated in the
I-V-curve in Figure 31.
Typical I-V-curves of a SiC MPS under nominal current conditions at different
junction temperatures are depicted in Figure 32. Nominal current conditions can beassumed for the majority of switched-mode applications of such devices. The SiC
diodes possess three different areas in the I-V-curve with different temperaturedependencies with NTC, ZTC and PTC behavior.

aaa-034534

IF (A)In the lower current range, the SiC diodes’ cut-in voltage decreases with increasing
junction temperature, resulting in an NTC behavior. With increasing current, thedrift resistance becomes more relevant. As a result, there is an I-V-point which has
no temperature dependency. All I-V-curves at different junction temperaturesintersect at this point. This point possesses a zero temperature coefficient (ZTC) andindicates the transition from NTC to PTC diode behavior. As illustrated in Figure 32,
the steepness of the I-V-curves decline with increasing junction temperature. At
currents above the ZTC point, the device shows a clear PTC behavior enabling
parallelization of SiC diodes for applications with higher current demand.

18
25°C
75°C
100°C
150°C
175°C

16
14
12
10
8
6
4
2
0
0

0.4

0.8

1.2

1.6

2.0

VF (V)
Figure 32 | Temperature dependency onto the static I-V-curve of a SiC MPS
under nominal current conditions.

56

Diode Application Handbook

However, if we extrapolate the I-V-curve of a pure Schottky device, the comparablyhigh differential resistance of unipolar devices is disadvantageous. Particularly inthe presence of high current exceeding the nominal current range, the comparablyhigh differential results in high on-state losses and poor over-current capability. To
overcome this drawback at transient high-current situations such as surge currents,
pure Schottky devices need to be paralleled to handle these currents. In real-world
applications the diode selection often must be over-dimensioned purely for thistransient situation. This is often disadvantageous from a commercial and also a
performance perspective. The MPS design overcomes the drawback of devices withpure forward Schottky behavior.

2
Diode fundamentals

2

The PN diode of the MPS structure behaves exactly diametrically to the Schottky
diode. The initial cut-in voltage of the monolithically-integrated PN diode is so highso that under nominal application conditions, this part of the MPS will not
contribute to the overall current. Here, the MPS acts as a pure Schottky diode.
However, at high forward current situations and due to the comparably highdifferential resistance of the Schottky area MPS, the voltage drop becomes so highthat the integrated PN junction is triggered and holes are injected. According to
the equivalent circuit in Figure 31, both diodes carry the current. The formerly pureunipolar device becomes a bipolar device. The injected holes significantly increase
the conductivity of the diode resulting in a much steeper I-V-curve and a muchhigher current-handling capability, and thus higher IFSM. This mode of operation iscalled bipolar mode.
The static I-V forward performance of an MPS diode including the bipolar mode atover-current events is illustrated in Figure 33. The corresponding dynamic
performance when the same diode is stressed with a 10ms sinusoidal current isshown in Figure 34. It can be clearly seen that a superior transient behavior of the
MPS diode can significantly relief the thermal stress of the power diode during
surge current situations. Not only can this action prevent thermal runaway anddestruction of the device, the reduced impact on the junction temperature is also
beneficial for the device’s lifetime and reliability, and should be taken into
consideration during an engineer’s parts selection, especially for heavy duty,
long-lifetime or safety-relevant applications.
The reason for this beneficial performance can best be described by thoroughly
looking at the static I-V-curve at higher currents. Consider the static measurements
in Figure 33. The different temperature behavior of both integrated diodes within
the MPS structure behave differently. With rising junction temperature, thedifferential resistance of the Schottky part increases resulting in flatter I-V-curves
with increasing temperature. On the other hand, the threshold where the PN diodeof the MPS kicks in decreases. From an application perspective this is extremely
beneficial since the protective nature of this bipolar mode is even more important at

57

9
IF (A)VF (V)

80
70

8
7

60

6

50

5

40

4

30

3

20

2

10

1

0

0

aaa-034535

IF (A)

0
100
−55°C
25°C
75°C
100°C
150°C
175°C

90
80
70
60

40
30
20
10
0
1

2

3

4

5

6

7

VF (V)
Figure 33 | Static I-V-behavior of SiC MPS diodes including overcurrent.

As individual and application-specific as it is for hardware designer to select themost suitable SiC diode for their power design, so it is for the semiconductor
design process of MPS diodes.
The ratio between Schottky area and PN area within an MPS diode correlates with
the normal forward conduct capability and the surge current handling. The higher
the PN portion of a SiC MPS at a given die size, the higher the over-current
capability of the device will be. However, this will adversely affect the low voltage
drop under nominal current conditions. Thus, a trade-off must be found between
lowest achievable voltage-drop under nominal current conditions and highest
possible over-current robustness. The optimum is always application-specific.
Nexperia has chosen a trade-off ratio between PN and Schottky width within the
SiC MPS diodes which will be most suitable for wide range of hard- and softswitching applications.

58

2

4

6

8

10

Time (ms)Figure 34 | Dynamic overcurrent behavior during 10ms sinusoidal current stress.

SiC MPS diode’s reverse recovery advantage

500Diode fundamentals

90

aaa-034752

higher junction temperatures. SiC diodes without the MPS concept, with the same
nominal current rating as SiC MPS, show an inferior over-current capability and may
not withstand the same over-current as the more robust MPS designs. For specificapplications such as power factor correction or power supplies where transient overcurrents can occur due to load dumps or line drop outs, hardware designers mustfactor this into their design considerations. As a consequence, designers have to add
a more complex protective circuit to prevent over-currents and/or over-specify
when SiC diodes without MPS concept are to be used. Both will negatively affect thecost structure. Nexperia’s robust SiC MPS diode solves this issue, reducing systemcomplexity without the need of expensive over-dimensioning.

2

Diode Application Handbook

VF (V)

nexperia | Design Engineer’s Guide

IF (A)

Diode fundamentals

2

Besides the static advantages, SiC MPS diodes offer advantages during dynamic
operation in switching mode. One major advantage over silicon-based PN diodes
relates to the reverse recovery behavior. As already described, under nominal
conditions SiC MPS diodes behave like Schottky-diodes. Unlike conventional Si fast
recovery diodes, only majority carriers contribute to the overall current for SiC
diodes. As a result, SiC diodes show a purely capacitive switching behavior, resulting
in a lower reverse recovery charge than a Si fast recovery diode with the same
electrical rating. The important reverse recovery charge is one of the main loss
contributors and thus adversely affects converter efficiency. SiC’s reverse recovery
charge is not only lower than silicon-based counterparts. In Figure 35 the effects ofparameters relevant to converter performance – such as different diode turn-off
currents and junction temperatures – are depicted. Obviously, SiC shows an almost
constant behavior in the presence of such variations. SiC does not exhibit most of
the non-linear behavior of Si fast recovery diodes. Hence, its behavior is easier topredict for power designers because they don’t have to take various ambient
temperatures and load conditions into consideration. Both diode technologies
share the fact that the blocking voltage will affect the capacitive portion of theoverall recovery charge. For Si-based PN diodes this portion is comparatively small
because the recovery charge is dominated by the stored minority carriers during
turn-off of the diode. Hence, the voltage dependence of the capacitive charge isoften negligible.
Due to the absence of minority carriers in a SiC diode, the capacitive charge is the
only contributor to the reverse recovery charge, and thus causes losses duringswitching. In Figure 36 the dependency of the applied blocking voltage on the

59

10

0

0

−10

−10

−20

−20

VR = 400V

aaa-034625-2

VR = 400V

IF (A)

10

aaa-034625-1

10

10

10
10 −

10 −

1

10

10

Diode fundamentals

aaa-034626

Capacitance (pF)

capacitive charges is illustrated. The effective capacitive charge can be extracted
from the diode capacitance behavior vs the applied voltage by calculating the area
below the capacitance voltage function. As depicted in Figure 36, higher voltages
result in higher charge and thus higher stored energy. This capacitive charge of thediode induces losses in the transistor in the switching cell in typical powerelectronic topologies, and must therefore be taken into consideration during theselection phase of the diode-transistor pair selection. As illustrated in Figure 36,
this stored energy is comparably low compared to the reverse recovery charge of Si
counterparts. But although this energy is low, it can be become relevant especiallyin high-frequency converters.

2

Diode Application Handbook

QC (nC)

nexperia | Design Engineer’s Guide

IF (A)

Diode fundamentals

2

10

40

30

20

5A
10A

5A
10A

−30

−30
3.54

3.55

3.56

3.57

3.58

3.59

3.60

10
3.54

3.55

3.56

Time (µs)

3.59

3.60

0

0

VR = 400V0EC (µJ)10aaa-034625-4

VR = 400V

IF (A)

SiC diode (PSC1065K)
aaa-034625-3

IF (A)

3.58

Time (µs)

Si diode

10

3.57

0

200

400

600

0

200

400

600

800

12

8
−10

−10

−20

−20

4
−30

−40

25°C
85°C
125°C
150°C

25°C
85°C
125°C
150°C

−30

−40

5.10 5.11 5.12 5.13 5.14 5.15 5.16 5.17 5.18 5.19

5.10 5.11 5.12 5.13 5.14 5.15 5.16 5.17 5.18 5.19

Time (µs)

Time (µs)

0800

Vr (V)
Si diode

SiC diode (PSC1065K)

Figure 35 | Comparison of reserve recovery behavior of SiC vs. Si diodes.

60

Figure 36 | Voltage dependency of the capacitive charge of SiC diodes andresulting stored energy.

61

2.6.4 Advanced SiC MPS process for maximum performance
As described earlier, the ratio between PN and Schottky area at a given die size
determines the performance, both under nominal current and over-current
conditions, and always leads to a trade-off between both aspects for a MPS diode.
In order to further optimize these characteristics, more advanced process steps are
required. One major influential parameter is the die thickness and its reduction for
the final MPS design. The unprocessed silicon carbide substrate is n-doped. The
epitaxial layers are subsequently grown on the SiC substrate. These substrates havea thicknesses of up to 500µm. Due to the doping concentration which is relatively
low for SiC n-substrates, its influence on the total on-resistance of the processed
diode is not negligible. As a consequence, both the voltage drop under normal
operation as well as the over-current handling is adversely affected. As depicted in
Figure 37, the thick substrate layer has no further electrical function but
unfortunately acts as a series resistance through which the total current must flow.

aaa-033947

To overcome this drawback, the underside of the substrate has to be thinned bygrinding. However, due to the hardness of SiC (around 9.2 to 9.3 on the Mohs
scale), grinding requires an advanced manufacturing process capability and precise
control of the material quality. Inappropriate and inferior processes steps can leadto non-uniformities of die thickness or even die cracks, resulting in inferior
performance or even device failures.

Current ﬂow
Current ﬂow

Bond metal
Schottky metalp+

Schottkyarea

Bond metalp+

Schottky metalp+n- SiC epi layer
n+ SiC substrate

110µm
Back side metalp+n- SiC epi layer

Rsub1

350µm

Schottkyarea
n+ SiC substrate

Rsub2

Back side metal

Figure 37 | Substrate resistance reduction through back-side grinding.

Nexperia’s SiC MPS diodes are all ground down to a minimum thickness of
substrate to maximize the diodes’ performance without compromising mechanicalstability.

62

2

Diode Application Handbook

Another positive aspect of the underside grinding refers to the thermal
performance. As shown in Figure 38, the portion of the n-doped substrate on thethermal path is massively reduced.

Current ﬂow
Current ﬂow

Bond metal
Schottky metalp+

Schottkyarea

Bond metalp+

Schottky metalp+

Heat
Rth, sub1

350µm

110µm
Back side metal

Diode fundamentals

nexperia | Design Engineer’s Guide

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Diode fundamentals

2

Schottky
area
Heat

p+

Rth, 2

Back side metal

Figure 38 | Thermal improvement of Nexperia’s backside optimized technology compared to a
thick substrate solution.

When the diode has to dissipate heat, for example during forward conduction, thegreater part of the heat flow is conducted through the diode’s underside via thelead frame into the PCB. A thick substrate inserts not only an unnecessary electricalresistance, it also impacts the heat flow. Thus, it has negative impact on the
maximum achievable performance and also the lifetime of the device. In contrast,
using Nexperia’s thin SiC technology massively improves the thermal performance.
As a result, this leads to a lower thermal resistance, higher dissipated power andtherefore higher power density. The surge current capability at given die size, inparticular when the duration of such transient over-currents is comparably large, isalso higher. Another consideration relates to the lifetime of the device. At a given
power loss within a given application, the junction temperature swing is lower forthe thinner device, leading to a longer lifetime and improved device reliability.
Although SiC diodes are already available in the market, there are still majordifferences in the ways various SiC manufacturers produce their parts. To enable
designers to fully exploit the superior material properties of SiC versus Si, anadvanced SiC design like the Merged PIN Schottky with optimized PN and Schottky
ratio as well as quality and process control and special substrate handling isrequired. Nexperia has mastered all of these design and production steps toguarantee the maximum performance, highest reliability and best quality
standards.

63

2.7 Zener diodes

Breakdownarea

Forwardconduction

IZ

When biased in the forward direction Zener diodes have the same characteristic asa silicon p-n diode. Most important for Zener diode applications is the characteristic
when biased in the reverse direction, where Zener diodes have a small leakage
current below a specific breakdown voltage. Above the breakdown voltage, the IV
characteristic shows a steep increase of current. Zener diodes can operate
constantly as voltage stabilizers at or above the breakdown voltage, VZ.

VBR

Both effects, zener and avalanche, are
not distinguished when naming Zener
diodes. No matter which physical effectdominates the breakdown of the
pn-junction, all voltage reference diodes
are referred to as Zener diodes.

V

0.7

Figure 40
I-V-characteristic of a Zener diode.

Cathode2.7.2 Datasheet parameters
Anode
Figure 39 | Common symbols
for a Zener diode.

Figure 40 shows the example of an IV curve of a zener diode. For positive voltages,
the diode is in forward conduction. The current increases quite steeply if a voltage
of about 0.7V is exceeded. In reverse direction, an area is depicted where the diodeis blocking. Once the breakdown voltage is reached, current increases significantly.
The voltage drop across the diode is kept almost constant in this area. An ideal
Zener diode would keep VZ constant independent on the current. In practice,bigger than zero. Zener diodes for voltages up to about 5V are realized with highly
doped substrates. For such pn-diodes, an electrical breakdown happens if electrons
can tunnel from the valence band into the conduction band across the depletionarea of the reverse biased junction. The free charge carriers create a sudden
increase in reverse current once the field strength is high enough. Clarence Melvin
Zener discovered this effect in 1934 and gave his name to the resulting diodes. For
Zener diodes with a breakdown voltage higher than 5V, a different breakdown
effect becomes dominant. This is called the ‘avalanche’ breakdown and occurs
when the electrical field across the pn-junction accelerates electrons in thetransition area. These electrons create electron-hole pairs. Holes move to thenegative electrode and get filled again, whereas the electrons move to the positiveelectrode. This motion of holes and electrons creates a leakage current through anegative biased diode. With high field strength, the mobile holes and electrons cangenerate more charge carriers by freeing up adjacent bound electrons. This processof generating more charge carriers creates an avalanche, causing a high current toflow once a specific reverse voltage is exceeded.

64

Reverseblocking

2.7.1 Introduction

These components are produced formany different voltages withguaranteed small ranges for VZ tested
at a defined reverse current IZ.
Figure 39 shows common symbols for azener diode.

2

Diode Application Handbook

Diode fundamentals

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Diode fundamentals

2

Nexperia datasheets for Zener diodes start with a section ‘General description’. The
package type is given here. Datasheets for Zener diodes address the whole familyof products including all working voltages. In the section ‘Features and benefits’,
the working voltage range is mentioned. For Zener diodes that are offered withdifferent tolerance selections of VZ, is the nominal working voltage, thisinformation is provided as well.
The chapter ‘Quick reference data’, as shown in Table 6, shows the maximum
forward voltage VF at a forward current IF of 10mA for Tamb = 25°C. In order to avoid
significant self-heating, this parameter is tested in pulsed mode.
The maximum total power dissipation Ptot is informed together with thedescription of the related mounting condition. Table 6 below is an example fromthe datasheet of BZX884S.

Table 6: ‘Quick reference data’ is an example
from a Zener diode data sheet.
Tj = 25°C unless otherwise specified
SymbolParameter

Conditions

VFforward voltage

Ir = 10mA

Ptot

total power
dissipation

Min

Typ

Max

Unit

[1]

–

–

0,9

V

[2]

–

–

365

mW

[1] Pulse test: tp ≤ 300μs; δ ≤ 0.02
[2] Device mounted on a FR4 PCB, single sided 70μm copper, tin-plated and standard footprint.

65

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Diode Application Handbook

Table 7 details the pinning of the diode. As for other diodes, the cathode is clearlymarked with a bar in order to ensure correct mounting in the desired direction.
Table 8 provides ordering information with type number, exact name, description
and package style.

Table 9: Section in the data sheet showing different working voltages
with corresponding marking codes.
Type Number

Mark.
Code

Type Number

Mark.
Code

Type Number

Mark.
Code

Table 7: Data sheet information regarding the pinningof an example Zener diode.

BZX884S-B2V42A

BZX884S-B27

3A

BZX884S-C8V2

5K

BZX884S-B2V7

2B

BZX884S-B30

3B

BZX884S-C9V1

5L

BZX884S-B3V0

2C

BZX884S-B33

3C

BZX884S-C10

3Y

BZX884S-B3V3

2D

BZX884S-B36

3D

BZX884S-C11

3Z

BZX884S-B3V6

2E

BZX884S-B39

3E

BZX884S-C12

4A

BZX884S-B3V92F

BZX884S-B43

3F

BZX884S-C13

4B

BZX884S-B4V32G

BZX884S-B47

3G

BZX884S-C15

4C

BZX884S-B4V72H

BZX884S-B51

3H

BZX884S-C16

4D

BZX884S-B5V1

2J

BZX884S-B56

3J

BZX884S-C18

4E

BZX884S-B5V6

2K

BZX884S-B62

3K

BZX884S-C20

4F

BZX884S-B6V2

2L

BZX884S-B68

3L

BZX884S-C22

4G

BZX884S-B6V8

N3

BZX884S-B75

3M

BZX884S-C24

4H

BZX884S-B7V5

2M

BZX884S-C2V4

4K

BZX884S-C27

4J

BZX884S-B8V2

2N

BZX884S-C2V7

4L

BZX884S-C30

4M

BZX884S-B9V1

2P

BZX884S-C3V0

4R

BZX884S-C33

4N

BZX884S-B102Q

BZX884S-C3V3

4S

BZX884S-C36

4P

BZX884S-B11

2R

BZX884S-C3V6

4T

BZX884S-C39

4Q

BZX884S-B122S

BZX884S-C3V9

4U

BZX884S-C43

4V

BZX884S-B13

2T

BZX884S-C4V3

4U

BZX884S-C47

4W

BZX884S-B15

2U

BZX884S-C4V7

4Y

BZX884S-C51

4Z

BZX884S-B16

2V

BZX884S-C5V1

5B

BZX884S-C56

5A

BZX884S-B18

2W

BZX884S-C5V6

5C

BZX884S-C62

5D

BZX884S-B20

2X

BZX884S-C6V2

5F

BZX884S-C68

5E

BZX884S-B22

2Y

BZX884S-C6V8

5G

BZX884S-C75

5H

BZX884S-B24

2Z

BZX884S-C7V5

5J

–

–

Pin

Symbol Description

1

K

cathode [1]

2

A

anode

Simplified outline

1

2
Transparent
top view

Graphic symbol

AK

006aaa152[1] The marking bar indicates the cathode.

Table 8: Ordering information in the data sheetof an example Zener diode.
Type Number

BZX884S series[1]

Package
Name

Description

Version

DFN1006BD-2

Leadless ultra small plastic
package with sidewettableflanks (SWF); 2 terminals;
0.65mm pitch; 1× 0.6 × 0.47mm
body

SOD882BD[1] The series includes 37 breakdown voltages with nominal working voltages from 2.4V to 75V and±2% and approximately ±5% tolerance.

The next datasheet section is named ‘Marking’ as illustrated in Table 9 . All available
products with different working voltages in the two tolerance bands are listed
together with the marking code. The name of later generation Zener diodes is
simple to interpret. First, the Zener diode family name can be found. In the given
example BZX884S. After this a character for tolerance is added. An indicator ‘B’stands for 2% tolerance, the character ‘C’ for about 5%.
Nexperia introduced a bigger portfolio of zener diodes with an ‘A’ tolerance rating
for the VZ, which means 1% accuracy in order to address a growing demand forhigher precision. Diodes in packages SOT23, SOD323 and SOD123F can be chosen.

Diode fundamentals

Diode fundamentals

2

After this, the working voltage follows, e.g. 2V4 for VZ =2.4V. Integer voltage
ratings show a number only and no V as separator.

66

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nexperia | Design Engineer’s Guide

Table 10 contains the ‘Limiting values’. The maximum forward current IF is defined
as well as the maximum total power dissipation Ptot, followed by the maximum
junction temperature Tj and the allowed temperature ranges for ambient Tamb andstorage Tstg.

Table 10: Specified limiting values in the data sheetof an example Zener diode.

ParameterIF

forward current

Ptot

total power dissipation

Conditions

Min

Max

Unit

–

200

mA

–

365

mW

Tj

junction temperature

–

150

°C

Tamb

ambient temperature

−55

+150

°C

Tstg

storage temperature

−65

+150

°C

Tamb = 25°C

[1][1] Device mounted on a FR4 PCB, single sided 70μm copper, tin-plated and standard footprint.

Table 11 details Rth(j-a) for standard footprint on a single-sided PCB with 70 µm
copper plating. This value could also be calculated with (150K–25K)/0.365W basedon the limiting values given in Table 10.

Table 11: Definition of the junction to ambient thermal resistancein the data sheet of an example Zener diode.
SymbolParameter

Conditions

Rth(j-a)thermal resistancefrom junction toambient

in free air[1]

In Table 12 showing ‘characteristics’, the maximum forward voltage drop at IF of
10mA is informed, as in Table 6.

Table 12: Section “characteristics“ in the data sheet ofan example Zener diode.
Tj = 25°C unless otherwise specified

In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol2

Diode Application Handbook

Min

Typ

Max

Unit

–

–

340

K/W

SymbolParameter

Conditions

VFforward voltage

Ir = 10mA

[1]

Min

Typ

Max

Unit

–

–

0,9

V

Diode fundamentals

Diode fundamentals

2[1] Pulse test: tp ≤ 300μs; δ ≤ 0.02

The three tables summarized in Table 13 list several very important parameters ofthe diodes. First column is the name extension, followed by a column for theaccuracy ranges provided per diode. The third column provides minimum andmaximum VZ values for a reverse current of 5mA. When VZ equals or exceeds 27V
the testing current is reduced. An IZ of 2mA instead of 5mA is applied because
power dissipation would become quite high with P = VZ * IZ in case of a highbreakdown voltage. Additional operating cases are tested in mass production toensure that the whole VZ-IZ curve is correct in the reverse blocking area as well as inforward conduction and in breakdown area.
Z
and listed in the fourth column.
The differential resistance is defined as rdif = ∆V
∆IZThis is the steepness of the VZ-IZ curve. The ideal would be a dynamic resistance of
0 ohms or a perpendicular curve. In this case, VZ would not change with reverse
current and the breakdown voltage would stay stable, independent of the current
applied.

The fifth column lists the maximum reverse or leakage current at about 2/3 of VBR.
The next column contains the thermal coefficient SZ in mV/K valid for an IZ of 5mA.
The breakdown voltage is dependent on the junction temperature and can becalculated with the simple formula below:[1] Device mounted on a FR4 PCB, single sided 70μm copper, tin-plated and standard footprint.

VZ = VZ(nominal) + SZ × (Tj − 25°C)
For low voltage zener diodes, SZ is a negative coefficient, so VZ decreases overtemperature. The breakdown mechanism is the Zener effect. Above about 6V, thesign of SZ changes and the avalanche effect becomes dominant.
Finally there is a column for the diode capacitance Cd tested at VR = 0V andf = 1MHz.

68

69

Table 13: Characteristics per typeWorking
voltageVZ (V)

3V0

3V3

3V6

3V9

4V3

4V7

5V1

5V6

6V2

6V8

Sel

Reversecurrent
IR (μA)IZ = 5mA

IZ = 1mA

IZ = 5mA

Min

Typ

Typ

Max

B

2.35

2.45

C

2.20

2.60

B

2.65

2.75

C

2.50

2.90

B

2.94

3.06

C

2.80

3.20

B

3.23

3.37

C

3.10

3.50

B

3.53

3.67

C

3.40

3.80

B

3.82

3.98

C

3.70

4.10

B

4.21

4.39

C

4.00

4.60

B

4.61

4.79

C

4.40

5.00

B

5.00

5.20

C

4.80

5.40

B

5.49

5.71

C

5.20

6.00

B

6.08

6.32

C

5.80

6.60

B

6.66

6.94

C

6.40

7.20

[1] f = 1MHz; VR = 0V

275

300

325

350

375

400

410

425

400

80

40

30

Max

600

600

600

600

600

600

600

500

480

400

150

80

70

75

80

85

85

85

80

50

40

15

6

6

Max

100

100

95

95

90

90

90

80

60

40

10

15

Temperature Diodecoefficient
capacitanceSZ (mV/K)
Cd (pF) [1]
IZ = 5mA

Max VR (V)

50

20

10

5

5

3

3

3

2

1

3

2

1.0

1.0

1.0

1.0

1.0

1.0

1.0

2.0

2.0

2.0

4.0

4.0

Min

−3.5

−3.5

−3.5

−3.5

−3.5

−3.5

−3.5

−3.5

−2.7

−2.0

0.4

1.2

Max

0.0

0.0

0.0

0.0

0.0

0.0

0.0

0.2

1.2

2.5

3.7

4.5

Sel

2V7

Differential
resistance
rdif (Ω)

BZX884S

Tj = 25°C unless otherwise specified

2V4

70

Tj = 25°C unless otherwise specified

BZX884S-B2V4 to BZX884S-C24

Working
voltageVZ (V)

2

Diode Application Handbook

Min

7V5

B

7.35

7.65

C

7.00

7.90

8V2

B

8.04

8.36

C

7.70

8.70

B

8.92

9.28

C

8.50

9.60

B

9.80 10.20

C

9.40 10.60

B

10.80 11.20

C

10.40 11.60

B

11.80 12.20

C

11.40 12.70

B

12.70 13.30

C

12.40 14.10

B

14.70 15.30

C

13.80 15.60

B

15.70 16.30

C

15.30 17.10

B

17.60 18.40

C

16.80 19.10

B

19.60 20.40

C

18.80 21.20

B

21.60 22.40

C

20.80 23.30

B

23.50 24.50

C

22.80 25.60

Max

260

260

260

260

260

260

260

170

170

170

120

120

9V1

10

11

12

13

15

16

18

20

22

24

Differential
resistance
rdif (Ω)

Reversecurrent
IR (μA)

Temperature Diodecoefficient
capacitanceSZ (mV/K)
Cd (pF) [1]

IZ = 5mA

IZ = 1mA

IZ = 5mA

Max

Typ

Max

Typ

Max

Max VR (V)

Min

Max

Max

30

80

6

15

1

5.0

2.5

5.3

150

40

80

6

15

0.7

5.0

3.2

6.2

150

40

100

6

15

0.5

6.0

3.8

7.0

150

50

150

8

20

0.2

7.0

4.5

8.0

90

50

150

10

20

0.1

8.0

5.4

9.0

85

50

150

10

25

0.1

8.0

6.0

10.0

85

50

170

10

30

0.1

8.0

7.0

11.0

80

50

200

10

30

0.05

10.5

9.2

13.0

75

50

200

10

40

0.05

11.2

10.4

14.0

75

50

225

10

45

0.05

12.6

12.4

16.0

70

60

225

15

55

0.05

14.0

14.4

18.0

60

60

250

20

55

0.05

15.4

16.4

20.0

60

60

250

25

70

0.05

16.8

18.4

22.0

55

[1] f = 1MHz; VR = 0V

IZ = 5mA

Diode fundamentals

nexperia | Design Engineer’s Guide

BZX884S

Diode fundamentals

271Figure 41 shows the I-V-curve of diode
BZX884S-B/C6V8 for forward direction
with a logarithmic scale for IF.

Tj = 25°C
10

Working
voltageVZ (V)

Differential
resistance
rdif (Ω)

IZ = 2mA

IZ = 0.5mA

IZ = 2mA

Min

Max

Typ

Max

Typ

Max

Max VR (V)

Min

Max

Max

10 −

27

B

26.50 27.50

65

300

25

80

0.05

21.4

25.3

50

10 −

C

25.10 28.90

30

B

29.40 30.60

C

28.00 32.00

33B

32.30 33.70

C

31.00 35.00

B

35.30 36.70

C

34.00 38.00

B

38.20 39.80

C

37.00 41.00

101

IZ = 2mA

18.9

70

300

30

80

0.05

21.0

24.4

29.4

50

75

325

35

80

0.05

23.1

27.4

33.4

45

80

350

35

90

0.05

25.2

30.4

37.4

45

80

350

40

130

0.05

27.3

33.4

41.2

45

Figure 41 | Forward current as a function of
forward voltage; typical values BZX884S-B/
C6V8-Q.

B

42.10 43.90

C

40.00 46.00

0.5

85

375

45

150

0.05

30.1

37.6

46.6

0.4

0.6

0.8

SZ (mV/K)
12

Tj = 25°C to 150°C

40

15
4V7
13
12
11
10
9V1
8V2
7V5
6V8
6V2
5V6
5V1

0
8
4V3

47

B

46.10 47.90

C44.00 50.00

85

375

50

170

0.05

32.9

42

51.8

40

−0.5
2V4

4

2V7

3V9

−1

51

B

50.00 52.00

C

48.00 54.00

B

54.90 57.10

90

400

60

180

0.05

35.7

46.6

57.2

40
3V6

56

C

52.00 60.00

B

60.80 63.20

C

58.00 66.00

68B

66.60 69.40

C

64.00 72.00

75

B

73.50 76.50

C

70.00 79.00

62

−1.5

100

120

425

450

70

80

200

215

0.05

0.05

39.2

43.4

52.2

58.8

63.8

71.6

40

1.0

VF (V)

Figure 42 depicts how the temperature coefficient SZ varies over the working
current IZ. For lower working voltages there is a quite significant influence on thiscoefficient. From Figure 43 it can be concluded that SZ becomes almost constantover IZ for working voltages above 7.5V.

SZ (mV/K)

43

10 −

mld44539

Temperature Diodecoefficient
capacitanceSZ (mV/K)
Cd (pF) [1]

mld44436

Reversecurrent
IR (μA)10

Sel

Tj = 25°C unless otherwise specified

IF (mA)

Diode fundamentals

BZX884S-B27 to BZX884S-C75

2

Diode Application Handbook

aaa-028551

nexperia | Design Engineer’s Guide

BZX884S

Diode fundamentals

2

0

3V3
3V0
Tj = 25°C to 150°C

−2
10−¹

1

10

10²

−4
10−¹

1

10

10²

IZ (mA)IZ (mA)

Figure 42 | Temperature coefficient as afunction of working current; typical values
BZX884S-B/C2V4-Q to B/C4V7-Q.

Figure 43 | Temperature coefficient as afunction of working current; typical values
BZX884S-B/C5V1-Q to B/C15-Q.

35

150

475

90

240

0.05

47.6

65.6

79.8

35

170

500

95

255

0.05

52.5

73.4

88.6

35

[1] f = 1MHz; VR = 0V

72

73

Diode fundamentals

For Zener diodes the I-V characteristic in reverse direction shows how effectively
the component can be used to stabilize a voltage. For low Zener voltages, thebreakdown voltage increases significantly versus reverse current as shown in
Figure 44. In this diagram the reverse direction I-V-curves from 2.4 V up to 6.8 V are
depicted. Figure 45 and Figure 46 show the reverse direction characteristics forhigher voltage Zener diodes from the BZX884S series. These devices get quite
close to an ideal Zener diode which would have a perpendicular I-V characteristic at
the nominal VZ voltage, so reverse current IZ would not have an impact on the
breakdown voltage.

IR (A)
10 −

2V4

10 −

2V7

−

3V0
3V3

10 

3V6 3V94V3 4V7 5V1

10 −
−

10 
5V6

10 −

6V2

10 −
Tj = 25°C
−

10 
4

6

Figure 44 | Reverse current as a function
reverse voltage; typical values (BZX884S-B/
C2V4-Q to B/C6V8-Q.

8aaa-006666

VR (V)IR (A)10 −
Tj = 25°C
10 −

10 12

7V5

15

18

22

8V2

10 −

aaa-006667

2

Nexperia offers zener diodes in a wide range of packages. Table 14 shows all
options from small DFN1006 packages up to the bigger variants like SOT223 withincreasingly higher power capability.
The values in column 3 apply for mounting the devices on an FR4 PCB with astandard footprint. The board uses single-sided copper with tin-plating.

Table 14: Nexperia’s packages for zener diodes,
configuration and Ptot ratings.
Package nameconfiguration

Ptot (mW)

DFN1006BD-2(SOD882BD)

single365

DFN1006(D)-2(SOD882)

single250

SOD523

single300

SOD323

single300/400/490

SOD323F

single310

SOT23

single, dual

250/300

SOT323Single, dual

250/275/300/350

SOD123

single365/590

IR (A)10 −

SOD123F

single500/830

30 36

10 −

27

33

43
39

51
47

62
56

75

SOT89

single1000

68

SOT223

single1500

SOD80C(MiniMelf)single500

SOD27(DO-35)

single500

SOD66(DO-41)single1000/1300

10 −
11 13

9V1

16

20

24
10 −

10 −

10 −

10 −

10 −
−

10 
10 −
10 −
10 −
Tj = 25°C

10 −

10 −
0

74

2.7.3 Zener diodes package overview

6V8

10 −

0

2

Diode Application Handbook

Diode fundamentals

nexperia | Design Engineer’s Guide

aaa-006665

2

5

10

15

20

25

20

40

60

80

VR (V)VR (V)

Figure 45 | Reverse current as a function
reverse voltage; typical values (BZX884S-B/
C7V5-Q to B/C24-Q.

Figure 46 | Reverse current as a function
reverse voltage; typical values (BZX884S-B/
C27-Q to B/C75-Q.

75

76

nexperia | Design Engineer’s Guide

3

Diode Application Handbook

Chapter 3
Data sheet parameters

Data sheet parameters

Diode fundamentals

277

3.1 Introduction
In the course of selecting the most suitable diode for any application there is no
way around taking a look into the datasheet. This selection process needs to be
carried out with a lot of care since different semiconductor manufacturers specify
the same parameter under different conditions, making two different products
hard to compare. Knowing this already highlights that understanding datasheet
parameters is key to successful application design.
The objective of this chapter is to provide engineers with an efficient path througha Nexperia diode datasheet and highlight special application and technology
related parameters. We have taken as our example the PMEG45T20EXD-Q
datasheet. The PMEG45T20EXD-Q is an 45V 2A trench MEGA (maximum efficiency
general application) automotive qualified (according to AEC-Q101) Schottky barrier
rectifier. In this case 45V is the reverse blocking voltage and 2A the average DC
forward current.

3.2 Understanding Nexperia datasheet
parameters and where they can be foundSince Nexperia offers a wide portfolio of diodes, sections of special diode products
can deviate from the generic structure. Nevertheless, the following subsection isrepresentative of the general datasheet structure for Nexperia diodes. Datasheets
for zener diodes address a complete diode family not a single product only.
Therefore they include a special subsection with a table specific parameters likebreakdown voltages VZ, thermal coefficient of VZ and others.

3

Diode Application Handbook

Table 15: Example: Quick reference data out of
the PMEG45T20EXD-Q datasheet.
SymbolParameter

Conditions

Min

Typ

Max

Unit

IF(AV)

average forward
currentδ = 0.5; f = 20kHz;
square wave;
Tsp ≤ 166°C

–

–

2

A

VR

reverse voltage

Tj = 25°C

–

–

45

V

VF

forward voltage

IF = 2A; pulsed;
Tj = 25°C

[1]

–

500

560

mV

IR

reverse current

VR = 45V; pulsed;
Tj = 25°C

[1]

–

4

25

μA

VR = 45V; pulsed;
Tj = 125°C

[1]

–

3

9

mA

Data sheet parametersnexperia | Design Engineer’s Guide[1] Very short pulse, in order to maintain a stable junction temperature.

The average forward current IF(AV) of the diode specifies the current capability for a
specific waveform without damage occurring through overheating. When
comparing multiple IF(AV) ratings, special attention must paid to the measurement
conditions. Nexperia specifies IF(AV) for a 20kHz square wave with a 50% duty cycle
δ. The duty cycle definition is given in Figure 47. For a δ of 0.5 and a switching1= 50µs and t1 = t2 ∙ δ = 25µs.
frequency f of 20kHz t2 = 20kHz

P

duty cycle δ =t2006aaa812

Data sheet parameters

3

t1
t2

t1

3.2.1 Quick reference data
Section 4 in the datasheet is a good early indicator of whether a particular diode issuitable for the target application. In the ‘Quick reference data’ section the mostimportant electrical characteristics of the device are summarized in the table.
Table 15 shows the excerpt from the respective section of the PMEG45T20EXD-Q
datasheet.

78t

Figure 47 | Duty cycle definition. Nexperia
specifies IF(AV) for a 20kHz square wave with a
50% duty cycle.

79nexperia | Design Engineer’s Guide

The current ratings for the typical waveforms can be obtained using following
equations:

IF(AV) = I M ∙ δ
IRMS = IF(AV) at DC & IRMS = I M ∙ √ δHere IM is defined as peak current and IRMS as the root mean square current (RMS).
At DC, IRMS equals the average current. In other words the IRMS value gives thesame heating effect as IF(AV) for DC condition or any other DC current of samevalue. Some vendors specify the IF(AV) using positive 60Hz half sine waves.
Calculating the average power for both current waveforms over two periods of thehalf sine wave leads to the result that the average power in the square wave isroughly the same order of magnitude as the sine half wave itself.
Please note: the IF(AV) rating is specified according to a maximum solder pointtemperature. In this case it is 166°C.
The next value in the ‘Quick reference data’ table is the reverse blocking voltage VR.
This determines the maximum allowable reverse voltage the diode is able towithstand before entering breakdown operation, which usually leads to destructionof the part. The reverse blocking voltage alongside the average current are the key
parameters used in the naming convention of Nexperia diodes. Thus the
PMEG45T20EXD-Q has a VR of 45V and a maximum IF(AV) of 2A. As mentioned in
sub-section 1.3, both forward and reverse characteristics exhibit a strong
temperature dependency. Thus when discussing the forward voltage and theleakage current in the ‘Quick reference data section’ it should be highlighted thatthese two values are measured using a very short pulse at room temperature(footnote 1 in Table 15) to avoid self-heating . The forward voltage drop of a diode,VF, determines conduction loss of the diode when it is forward biased. This is very
important in high efficiency applications like SMPS, or for reverse polarity
protection. Here, VF should be kept as low as possible. The last value in the ‘Quickreference table’ is the reverse current IR, also known as the leakage current. This is
the amount of current which will pass through the diode when it is reverse biased.
With reverse power PR = VR × IR, the leakage current IR defines how much power isgenerated in reserve direction for a given reverse voltage.

80

3

Diode Application Handbook

3.2.2 Pinning-, ordering- and marking information
After the most relevant technical parameters have been discussed, sections 5–7
cover product specific information, such as ordering code and markings, as can beseen in Table 16. Here the transparent top view in the simplified outline column is agreat help when employing the device during the prototyping phase while using
manual assembly.

Table 16: Pinning information of the PMEG45T20EXD-Q.
Pin

Symbol Description

1

K

cathode

2

A

anode

Simplified outline

Graphic symbol

K

Data sheet parameters

Data sheet parameters

3A
sym001The Ordering Information table (Table 17) contains a unique type number. This
gains more importance if a die is available in multiple packages. If that is the case,the last letter (for newer packages the last two letters) is the package designator.
Besides the type number, the package name, body dimension and version is given.

Table 17: Ordering information PMEG45T20EXD-Q.
Type Number

PMEG45T20EXD-Q

Package
Name

Description

Version

CFP2-HP

SOD323HP: plastic surface-mounted package withsolderable lead ends;
2.2 × 1.3 × 0.68mm body

SOD323HP

3.2.3 Limiting values
Section 8 is the most crucial section of the datasheet and should be studied withgreat care before operating the device. The limiting values state the specified
absolute maximum ratings that the device can operate to. These values areguaranteed by Nexperia and in are accordance to the ‘Absolute Maximum rating
System’ (IEC60134). Stresses beyond those levels or any other condition is notrecommended or guaranteed. Exposure to absolute maximum ratings for extended
periods of times may also have an influence on device functionality. The limiting
values for the PMEG45T20EXD-Q are depicted in Table 18.

813

Diode Application Handbook

Parameter

Conditions

Min

Max

Unit

VR

reverse voltage

Tj = 25°C

–

45

V

IF

forward current

δ = 1; Tsp ≤ 165°C

–

2.8

A

IF(AV)

average forward
currentδ = 0.5; f = 20kHz; square
wave; Tsp ≤ 166°C

–

2

A

non-repetitive peak
forward current

tp = 8.3ms; half sine wave;
Tj(init) = 25°C–

total power
dissipation

Tamb ≤ 25°C

Ptot

60

50

40

30

22

A
20

[1]

–

0.65

W

[2]

–

1.2

W

10

Tj

junction temperature

–

175

°C

Tamb

ambient temperature

−55

175

°C

Tstg

storage temperature

−65

175

°C

[1] Device mounted on a FR4 Printed-Circuit Board (PCB), single sided copper, tin-plated and standard footprint.
[2] Device mounted on a FR4 PCB, single sided copper, tin-plated mounting pad for cathode 1cm2.

The reverse voltage VR and the average forward current IF(AV) have already been
discussed in the ‘Quick reference data’ section. In comparison to IF(AV), the forward
current IF states the maximum constant current allowed for a duty cycle operationof 1 – in other words, DC conditions. Here, solder point temperature has been kept
below 165°C. Contrary to IF, the non-repetitive peak forward current IFSM specifies
the maximum allowed single current pulse. Hence IFSM is a measure for the surge
current capability of a diode. It is important to notice that IFSM is valid for single
events, like inrush currents at start-up or in load dump scenarios, only. The test
pulse used to characterize this is a single cycle, half sine wave with a pulse length tp
of 8.3ms which corresponds to 60Hz half sine wave. This pulse has historicalbackground since diodes where originally used to rectify 50/60Hz main from AC to
DC. The current pulse is depicted in Figure 48 for a diode which has an IFSM value of
50A.

0
0

1

2

3

4

5

6

7

8

9

Time (ms)Figure 48 | IFSM measurement: half sine wave with a pulse width of 8.3ms for a clip bonded diode.

Experience has shown that the IFSM capability of a device will already varysignificantly when comparing two devices in the same package with different active
chip areas (Figure 49) or bonding technologies (Figure 50). Even mounting
conditions have an impact on IFSM.
aaa-034627

IFSM

aaa-034537

SymbolIF (A)

Table 18: Limiting values PMEG45T20EXD-Q.

Data sheet parametersnexperia | Design Engineer’s Guide

Measured IFSM (A)Data sheet parameters

3

90
80
70
60
50
40
30
20
0.5

0.7

0.9

1.1

1.3

1.5

Active area of the die (mm)Figure 49 | IFSM for a 5.5ms square wave pulse as a function of active chip area.

82

83

Configuration
1x500 µm wire - 1.64x1.64 mm2 die size
1x500 µm wire - 3x3 mm2 die size
2x200 µm wire - 3x3 mm2 die size
2x300 µm wire - 3x3 mm2 die size

90
80
70
60
50
40
30

Mean
163
188.4
210.9
256.5

StDev
2.404
1.430
1.370
2.014

N
10
10
10
10

AD
0.319
0.338
0.437
0.281

P
0.473
0.424
0.234
0.559

20
10
5
1
150

175

200

225

250

275

IPulse (A)Figure 50 | Probability Plot of D²PAK for different Bonding technologies.

Also, trying to approximate IFSM for different pulse length is not that simple since
there is no fully linear relationship. It can be stated that IFSM increases for shortpulse durations, if the junction temperature does not exceed the silicon limit, andvice versa. For long pulse duration the power dissipating capabilities of the package
and the connection to the solder point contributes to the IFSM capability compared
to short pulse durations. Here, all generated heat needs to be dissipated in thejunction itself. The initial junction temperature when measuring IFSM Tj(init) is 25°C.
The device junction heats up to a high temperature while experiencing the test
pulse, therefore the IFSM value will degrade fast for Tj(init) above 25°C.
The total power dissipation, Ptot, is the maximum allowable power the diode is able
to dissipate during steady state operation while not exceeding the maximum
allowable junction temperature, in this case 175°C. During measurement, theambient temperature is controlled to be equal or less than 25°C. Ptot depends
greatly on the mounting conditions as can be seen in case of the PMEG45T20EXD-Q
in Table 18. Here, there are two Ptot values stated. The first one is for standard
footprint on the PCB as in Nexperia’s footprint recommendation at the end of thedatasheet. Here no optimal heat spread into the PCB is provided and thus thebenefits of CFP2-HP package cannot be fully used. This is different for the second
Ptot value in the table. This power is meant for a 1cm² heat sink which is located at
the cathode tab. This condition is thermally comparable to a four-layer PCB andenables the PMEG45T20EXD-Q to dissipate nearly twice as much continuous powercompared to the standard footprint. For ease of visualization, both layout variants
are depicted in Figure 51.

84

Vwith groundplate
0-10

Figure 51 | Example CFP2-HP test boards: 1cm² mounting pad for cathode vs. standard footprint.
L tip

VSwitchThe maximum junction temperature TJ dictates the temperature limit of the die.
Time (ns)
100 V
Violating this limit may damage the diodeirreversibly, as exceeding any of the
300 Vother limiting values would also do. The
ambient Tamb is typically equal
500maximumV
700theV storage temperature T . The
to the maximum TJ. The same is true forstg
minimum and maximum Tamb indicates the temperature environment that thedevice can be in while complying with the other datasheet parameters. Tstg sets thetemperature range in which the device can be stored without affecting its
reliability. For long term storage, an inert atmosphere will prohibit device
degradation.

Data sheet parameters

95

Kann die Headline
in die BU integriert werden?

Abbildung Kontur 0,5 pt
Abbildung fett3.2.4
1 pt
Thermal characteristics
Beschriftung/Pfeil 0,3 pt
GridThis sub-section of the datasheet provides information about the thermal behavior
Grid gestricheltof the device, considering different reference points and conditions. The thermal
resistance Rth is the steady-state parameter of how much the device will heat up
for a constant power flow under DC conditions. Hence the unit is Kelvin per Watt. In
other datasheets this is sometimes expressed as Celsius per Watt. Since thethermal resistance describes temperature difference, both are the same. The
subscript j-x states temperature difference from junction point of view to a specificreference point. A high-level visualization of prominent heat paths is shown on the
cross section of typical clip bonded package depicted in Figure 52.

Minor heat path

Encapsulation surfaces

Major heat pathaaa-034609

Normal: 95% CI

3Diode Application Handbook

Power (W)99

aaa-034628

nexperia | Design Engineer’s Guide

Percent

Data sheet parameters

3

Junction
Solder point of
second heat path

Solder point ofﬁrst heat path

PCB

Figure 52 | Cross section of a typical clip bonded flat power package – heat paths highlighted.

85

nexperia | Design Engineer’s Guide

Nexperia uses two different thermal resistances to specify the thermal
characteristics of its devices. The first value is the thermal resistance from thejunction to ambient and can be identified by the index (j-a). The second value isfrom junction to the solder point of the cathode tab (indicated as “first heat path”
in Figure 52) and has the index (j-sp). For completeness, the minor thermal heat
path from junction to the topside of the case is also indicated in Figure 52. This
heat path might be prominent if topside cooling is to be considered. Some
Nexperia packages such as CCPAK12 support topside cooling. The main heat pathfor SMD components is from junction to solder point into the PCB. For comparing
packages from different vendors by using Rth(j-a) it is very important to also checkthe parameters like PCB type and footprint which have a huge impact on the Rth(j-a).
The thermal characteristics for the PMEG45T20EXD-Q under DC conditions areshown in Table 19.

Table 19: Thermal characteristics of the PMEG45T20EXD-Q.
SymbolParameter

Conditions

Rth(j-a)thermal resistancefrom junction toambient

in free airRth(j-sp)

thermal resistancefrom junction tosolder point

Min

Typ

Max

Unit

[1] [2]

–

–

230

K/W

[1] [3]

–

–

125

K/W

[4]

–

–

6

K/W

3

Diode Application Handbook

package, the diode can fail. This is called ‘thermal runaway’ and will be explained in
more detail in chapter 3.3. To avoid this, the following formula should be
adhered to:1
δPdiss<δTJ
R th(j–a)
Figure 53 shows the comparison of thermal plots for a standard footprint layout
and one using a 1cm² heat sink with the PMEG45T20EXD at a continuous power
dissipation of 1.07W, using infrared camera measurement. The temperature
difference in thermal equilibrium is greater than 30°C. Note the infrared camera
only captures the topside temperature. The actual junction temperature is higher.

Data sheet parameters

Data sheet parameters

3

Figure 53
Comparison of infrared
camera measurementsof PMEG45T20EXD-Q
on standard footprint(top) and on footprint
with 1cm² heatsink at
1.07W continuous
power dissipation.

[1]		 For Schottky barrier diodes thermal runaway has to be considered, as in some applications the reverse power
losses PR are a significant part of the total power losses.
[2] Device mounted on a FR4 Printed-Circuit Board (PCB), single sided copper, tin-plated and standard footprint.
[3] Device mounted on a FR4 PCB, single sided copper, tin-plated mounting pad for cathode 1cm2.
[4]		 Soldering point of cathode tab.

Nexperia specifies the thermal resistance from the junction to the ambient Rth(j-a)
for two different mounting conditions. The first value is valid for the use ofstandard footprint. It delivers the highest thermal resistance since the diode has alimited heat path. The diode will heat up faster for the same amount of dissipatedpower compared to the second value which uses a 1cm² heat sink for the cathode.
As mentioned by footnote 1 in Table 19, when the reverse power losses generated
within the diode due to leakage current exceed the power dissipated by the86

The Rth(j-sp) in Table 19 characterizes the heat transfer from the junction throughthe leadframe up to the solder point of the cathode tab. Therefore it is not
influenced by the type of PCB or the kind of footprint. This is the reason why no
definition of the mounting condition is needed for this parameter. As Rth describes
the steady state operation, the thermal impedance Zth represents the dynamic
thermal behavior. Since Zth(j-x) is a dynamic parameter, it is shown in the curves as afunction of pulse duration for different duty cycles. For duty cycle definition pleaserefer to Figure 47. A duty cycle of 0 equals single pulse operation and a duty cycleof 1 indicates DC operation. Figure 54 shows an array of Zth(j-a) curves as a functionof pulse duration and duty cycle for PMEG45T20EXD-Q.

87

10
10
1

10 −

duty cycle = 1
0.50

0.75

0.33
0.25 0.20
0.10
0.05
0.02
0.01

Table 20: Datasheet characteristics of the PMEG45T20EXD-Q.
SymbolParameter

Conditions

Min

Typ

V(BR)B

reverse breakdown voltage

IR = 1mA; pulsed; Tj = 25°C

[1]

45

–

–

V

VF

forward voltage

IF = 0.1A; pulsed; Tj = 25°C

[1]

–

330

385

mV

IF = 0.5A; pulsed; Tj = 25°C

[1]

–

390

445

mV

IF = 0.7A; pulsed; Tj = 25°C

[1]

–

410

465

mV

IF = 1A; pulsed; Tj = 25°C

[1]

–

430

490

mV

IF = 2A; pulsed; Tj = 25°C

[1]

–

500

560

mV

IF = 2A; pulsed; Tj = −40°C

[1]

–

540

600

mV

IF = 2A; pulsed; Tj = 125°C

[1]

–

440

500

mV

IF = 2A; pulsed; Tj = 150°C

[1]

–

430

490

mV

VR = 10V; pulsed; Tj = 25°C

[1]

–

2

10

μA

VR = 45V; pulsed; Tj = 25°C

[1]

–

4

25

μA

VR = 45V; pulsed; Tj = 125°C

[1]

–

3

9

mA

VR = 45V; pulsed; Tj = 150°C

[1]

–

11

40

mA

VR = 4V; f = 1MHz; Tj = 25°C

–

160

–

pF

VR = 10V; f = 1MHz;
Tj = 25°C

–

100

–

pF

reverse recovery
time step
recoveryIF = 0.5A; IR = 1A;
IR(meas) = 0.25A; Tj = 25°C

–

5

–

ns

reverse recovery
time ramp
recoverydlF/dt = 100A/μs; IF = 1A;
VR = 30V, Tj = 25°C

–

9

–

ns

IRM

peak reverse
recovery current

dlF/dt = 100A/μs; IF = 1A;
VR = 30V, Tj = 25°C

–

0.38

–

A

QRR

reverse recovery
chargedlF/dt = 100A/μs; IF = 1A;
VR = 30V, Tj = 25°C

–

2.5

–

nC

VFRM

peak forward
recovery voltage

IF = 0.5A; dlF/dt = 20A/μs;
Tj = 25°C

–

405

–

mV

0

−

10 
10 −

10 −

10 −

10 −

10 −

1

10

10

10

tp (s)
Figure 54 | Zth(j-a) as a function of pulse duration and duty cycle for PMEG45T20EXD-Q;
typical values.

The key information given by these curves is that the device can sustain more
power for small duty cycles or short pulse duration. The rise of junction
temperature for a given power dissipation can be calculated via equation:IR

reverse current

ΔT = | Ztℎ(j−x) | ∙ Pdiss
Where Pdiss is the dissipated power by the diode. Zth(j-x) indicates how the device
responds to transient thermal events and converges to the thermal resistance Rth
for long pulse duration. For the steady state the above equation can be written as:

CD

trr

ΔT = | Rtℎ(j−x) | ∙ Pdiss
For a more detailed derivation of the thermal resistance please refer to chapter 4.

3.2.5 Electrical characteristics
The complete electrical characteristics of the diode are provided in section 10 ofthe datasheet. The reverse and forward parameters stated here are measured
using very short pulses to avoid self-heating of the device.

3

Diode Application Handbook

diode capacity

Max Unit

Data sheet parameters10

aaa-033396

nexperia | Design Engineer’s Guide

Zth(j-a) (K/W)

Data sheet parameters

3[1] Very short pulse, in order to maintain a stable junction temperature.

88

89

As described in chapter 1, diodes can be operated in three different states. To
enter breakdown operation, the reverse voltage must be greater than or equal to
the reverse breakdown voltage V(BR)R. The forward voltage drop VF has alreadybeen introduced in the section discussing the quick reference data. In Table 20 VF isgiven for different operating points and junction temperatures. For a more detailed
representation of the forward characteristics, the forward current as a function of
forward voltage should be studied, as illustrated in Figure 55. These curves are
given for the complete temperature range of the device and allow the user toestimate device performance under different conditions.
As for the forward characteristics, the reverse characteristics are stated for
different operating points. As already mentioned in the quick reference section, for
the PMEG45T20EXD-Q the reverse current increases by three orders of magnitude
for a temperature difference of 100°C. If the temperature is kept constant and VR is
reduced by factor of 4, IR reduces by a factor of two only. Figure 56 depicts thereverse current as a function of reverse voltage for different temperatures.

The following parameters describe the transient response of the diode. Due to thenature of the junction, any variation in applied voltage will cause a change for thenumber of charge carriers. If the voltage is applied in reverse direction, electriccharge is stored at the depletion region. This charge is then acting like a parallel
plate capacitor. The resulting capacitance is called junction capacitance CD and isdQ. The
directly linked to the change in charge for a given voltage change by CD = dVR
junction capacitance is also called transition capacitance and therefore denoted as
CT in datasheets of other vendors. Since the junction capacitance generally varies
not only with voltage but also with frequency, CD is specified at a dedicatedfrequency. Many manufacturers, including Nexperia, specify CD at 1MHz andprovide it as function of reverse voltage as can be seen in Figure 57. The
capacitance CD decreases with increasing reverse voltage.

Cd (pF)350
f = 1MHz
Tamb = 25°C

10

aaa-033399

aaa-033398

300

IF (A)IR (A)
10 −
10 −

−

10 

10 −

10 −

Tj = 85°C
Tj = 25°C
Tj = −40°C

0
0

0.4

0.8

10

20

30

40

50

VR (V)10 −
10 −
1.2

VF (V)

Figure 55 | Forward current as a function of
forward voltage; typical values
PMEG45T20EXD-Q.

90

Tj = 170°C
Tj = 150°C
Tj = 125°C
Tj = 100°C

10 −

10 −
0

200

50

10 −
Tj = 175°C
Tj = 150°C
Tj = 125°C
Tj = 100°C
Tj = 85°C
Tj = 25°C
Tj = −40°C

250

100

10 −

10 −

Figure 57 | Diode capacitance as a function ofreverse; PMEG45T20EXD-Q.

150

10 −

1

3

Diode Application Handbook

Data sheet parametersnexperia | Design Engineer’s Guide

aaa-033400

Data sheet parameters

3

0

10

20

30

40

50

VR (V)

Figure 56 | Reverse current as a funtion ofreverse voltage and temperature;
PMEG45T20EXD-Q.

The time required by the device to establish full blocking capability after one
current commutation is called reverse recovery time trr. Nexperia provides two
reverse recovery times. One for step response as shown in Figure 58 and one forramp response depicted in Figure 59. The definition of trr for ramp recovery
including all the related datasheet parameters like peak reverse recovery current
IRM and the reverse recovery charge Qrr has already been thoroughly described in
section 1.4.2. In summary the trr for ramp recovery is an important design
parameter which must always be considered in switching applications, since thediode trr can limit the maximum switching speed.

91Since such di/dt behavior is often present in switching application where a current
limiting inductor is present, VFRM is an important parameter to consider in thediode selection process diodes since it might impact conduction losses.

trr

IR(meas)

time

time
IR

Qrr

100%

IRM

IR

trr

Figure 58 | Reverse recovery definition;
step recovery.

3.2.6 Datasheet temperature curves

25%

Figure 59 | Reverse recovery definition;
ramp recovery.

The trr for a step recovery determines how long it takes the diode to restore
blocking state after an instantaneous change of polarity. trr consists of two
intervals in time. The first part is the delay caused due to removal of the stored
charge in the form of excess carries into their respective region, which is calledstorage time. During this time, a negative current IR is flowing through the diode.
The time to recover from this to a specified reverse current level IR(meas) is called
transition time. Diodes can be classified depending on their trr into fast and slow
recovery diodes. trr can range from a few microseconds (PN junction) down to a
few nanoseconds (Schottky diodes).
While the reverse recovery time describes the behavior when the diode changes
from on to off state, the peak forward voltage is a measure of how much overshootvoltage drop will be present once the diode is turned on, before decreasing to VF
for the on state. Hence it is a measure for forward recovery tfr. Like trr for ramp
recovery, the forward recovery is defined for a specified ramp as defined underconditions for this measurements in Table 20. The forward recovery definition is
given in Figure 60.

The section covers the temperature curves which are part of the characteristics
section.
Figure 61 shows the average reverse power dissipation PR(AV) as a function of VR. In
the off state there is power dissipation due to the leakage current through thediode being almost simultaneously present with a reverse voltage applied. The
curves are given for a constant TJ of 100°C (self-heating is neglected in this graph)and different duty cycles δ. The duty cycle is the time where the diode is in reverse
direction divided by the cycle time T. As expected for small δ, the average power
dissipation is less compared to larger δ. Since the IR increases exponentially as the
VR increases , PR(AV) increases as well with PR(AV) = VR × IR.

PR(AV) (W)0.035δ = 1; DCδ = 0.9
δ = 0.8
δ = 0.5
δ = 0.2

0.030
0.025

Data sheet parameters

dlF
dt

3

Diode Application Handbook

aaa-033402

IFIF

003aac562

nexperia | Design Engineer’s Guide

006aad022

Data sheet parameters

3

0.020
0.015
0.010
0.005
Tj = 100°C

001aab912

0

IF

time
VF

VFRM
VF

Figure 60 | Forward
recovery definition.

0

10

20

30

40

50

VR (V)

Figure 61 | Average reverse power dissipation
as a function of reverse voltage; typical values.

The next two curves (Figure 62 and Figure 63) show the IF(AV) for a constant TJ of
175°C (maximum junction temperature) and different duty cycles as a function of
Tamb. The switching frequency is set to 20kHz. The difference between the two
curves is the mounting condition. Figure 62 shows IF(AV) for standard footprint andFigure 63 for a 1cm² mounting pad attached to the cathode. The curves are
consistent to the Zth graphs of the datasheet. The relation between Ipeak andaverage forward current as a function of ambient temperature as well as the shapeof the curves will be explained in the next chapter.

time

92

93

2

3
δ = 1; DCδ = 0.5; f = 20kHz
δ = 0.2; f = 20kHz
δ = 0.1; f = 20kHz

VR (V)

2

50

1

1

Tj = 175°C
0
50

50

40

40

30

30

20

20

Tj = 175°C

00

VR (V)

Data sheet parametersδ = 1; DCδ = 0.5; f = 20kHz
δ = 0.2; f = 20kHz
δ = 0.1; f = 20kHz

These curves show that the derating of VRmax can be compensated to for a tocertain amount degree by good thermal management on the PCB. For more details
regarding safe operation are please refer to 4.3.

aaa-033502

3

IF(AV) (A)3

Diode Application Handbook

aaa-033501

IF(AV) (A)aaa-033404

nexperia | Design Engineer’s Guide

aaa-033403

Data sheet parameters

3

100

150

200

0

50

100

150

200

Tamb (°C)

Tamb (°C)

Figure 62 | Average forward current as afunction of ambient temperature;
typical values – standard footprint.

Figure 63 | Average forward current as afunction of ambient temperature;
typical values – 1cm² mounting pad.

10

IF(AV) (A)3

Tth = 125K/W

0

0
0

50

100

150

200

0

Tj (°C)
aaa-033405

Figure 64 | Average forward current as afunction of solder point temperature;
typical values.

10
Tth = 230K/W

50

100

150

200

Tj (°C)

Figure 65 | Derated maximum reverse voltage
as a function of junction temperature;
typical values – thermal resistance junction toambient as defined for standard footprint.

Figure 66 | Derated maximum reverse voltage
as a function of junction temperature;
typical values – thermal resistance junction
to ambient as defined for 1cm² cathodemounting pad.

aaa-033503

2

VR (V)In Figure 64, IF(AV) is depicted versus Tsp,
so not versus Tamb as in prior diagrams.
From Figure 64 the maximum allowable
solder point temperature can beextracted from DC condition to pulsed
operations.

50

1

Tj = 175°C

δ = 1; DCδ = 0.5; f = 20kHz
δ = 0.2; f = 20kHz
δ = 0.1; f = 20kHz

40

0
0

50

100

150

200

The last set of curves describes derating VRmax with respect to the junction
temperature for three different conditions. These graphs define basically the safe
operating area of the diode in reverse direction:
1. Standard footprint on FR4 PCB (Rth(j-a) = 230K/W) – Figure 65
2. Mounting pad for cathode 1cm² on FR4 PCB (Rth(j-a) = 125K/W) – Figure 66
3.		Soldering point of cathode tab Rth(j-s) = 6K/W – Figure 67

9430

Tsp (°C)
20

10

0
0

50

100

150

200

Tj (°C)

Figure 67 | Derated maximum reverse voltage
as a function of junction temperature;
typical values – thermal resistance of junction
solder point Rth(j-s) = 6K/W.

95

3

Diode Application Handbook

The last two subsections provide information about the package outline in
Figure 68, and the recommended footprint for reflow soldering shown in Figure 69.

1.7

0.4

1.0

1.6

0.5

0.9
0.8

1.5

1.4
1.2

0.75
0.61

0.98
0.82
1

1

1.6

1.4

1.2

1.1

1.50
1.26
2.7
2.6

sod323hp_fr

3.2.7 Package outline & recommended footprint for reflow soldering

1.0

0.78 0.88 0.98 1.18

0.42

2.5

2.3
2.1

Data sheet parametersnexperia | Design Engineer’s Guide

sod323hp_mo

Data sheet parameters

3

0.38

3.3

recommended stencil thickness: 0.1 mm
0.80
0.64
2

2
0.25
0.11

Dimensions in mm

0.75
0.65

occupied area

solder resist

solder landsolder paste

Dimensions in mm

21-04-14

Issue date: 21-04-02

Figure 69: Reflow soldering footprint for CFP2-HP (SOD323HP).

Figure 68 | Package outline CFP2-HP (SOD323HP).

The package outline is a technical drawing showing a first angle projection(European projection – indicated by the symbols in the bottom right corner
Figure 68) of the package.
The recommend footprint for reflow soldering gives information about layer set up
for the specific footprint with respect to solder resist (a protective layer against
oxidation and which also prevents solder bridges from forming between closely
spaced solder pads), solder paste (decides how bigdetermines the size of the
opening for the solder pad is in the stencil) and solder land (the actual solder pad
for the pin – often slightly bigger than the footprint itself). Additionally, theoccupied area on the PCB can be derived from the drawing in Figure 69. All
dimensions are provided in mm. The recommended stencil thickness for the
CFP2-HP footprint is 0.1mm.

96

97

98

nexperia | Design Engineer’s Guide

4

Diode Application Handbook

Chapter 4
Thermal considerations

Thermal considerations

Data sheet parameters

3994.1 Diode as a thermal system

A

B
Bond wire

A typical small signal or medium power semiconductor device can be broken down
to some major components which define the thermal behavior of the device.

A third class of packages includes additional terminals with a comparably large area
to allow the efficient dissipation of heat from the device to its surroundings, often
referred to as ‘package heatsink’. A diagram of a wire bonded device with apackage heatsink is shown in Figure 70c. Also, the combination of a packageheatsink with a clip frame is available for efficient heat dissipation and robust
package performance (Figure 70d).
PCBs (printed circuit board) are the connection of small signal devices to theenvironments. They are suppling the electrical power to the device and they arealso the main element to dissipate heat away from the device. For bigger powerdevice packages (e.g. TO220) a second path can be present by adding a coolingelement like passive heatsinks.
PCBs can have significant impact on the overall thermal device performance. They
can limit the performance of the device or make use of the full potential of thedevice by smart design of the thermal dissipation paths. PCB design for goodthermal behavior is a science of its own and will not be covered in detail in thishandbook, except for a small excurse in section 3.1.4.

Semiconductor chip

Semiconductor chip

Clipframe

Encapsulation

Encapsulation
Leadframe

Leadframe

Figure 70a shows a simple structure diagram of a wire bonded semiconductor
device with its major component leadframe, semiconductor chip, wire bonding andencapsulation. For some of the more power-oriented package architectures, thewire bond is replaced with clip frame connection which is more comparable to theleadframe itself (further referred to as clip-bond packages). A diagram can befound in Figure 70b.

4

Diode Application Handbook

C

Leadframe

Leadframe

D
Bond wire

Leadframe
withside wetable
ﬂanks(optional)

Encapsulation

Semiconductor chip

Semiconductor chip

Clipframe

Leadframe with
exposed packageheatsink

Encapsulation

Thermal considerations

nexperia | Design Engineer’s Guide

aaa-034539

Thermal considerations

4

Leadframe with
exposed packageheatsink

Figure 70 | A: wire bonded package, e.g. SOT23 – B: clip bonded package, e.g. CFP5.
C: wire bonded with package heatsink, e.g. DFN2020D-3.
D: clip bonded with package heatsink, e.g. LFPAK56 or CFP15B.

In the upcoming chapters the formal definition of thermal resistances as used by
Nexperia will be given. This is followed by considerations of different packagearchitectures and the discussion will conclude with some explanations that go
beyond single chip semiconductor devices.

4.1.1 Measurement of thermal resistances
Team Nexperia measures the thermal resistances of its small signal devices on
standardized PCBs with different footprints. The outcome is commonly shown inthe datasheets of the devices as the Rth(j-a) values for different PCBs.
The extraction of Rth(j-sp) values follows the Transient Dual Interface Method (TDIM)
according to JESD51-14 (alternative method on dedicated PCBs).

100

101

nexperia | Design Engineer’s Guide

4.1.2 Definition of thermal resistances
A thermal resistance can be considered to be completely analogous to an electricalresistance. This analogy helps in many situations to help think ‘thermally’ when
making decisions concerning heat dissipation.
Definition:
The resistance R(X-Y) is defined between two physical points as the temperature
difference ΔT(X-Y) between this points divided by the power P(X-Y) dissipated along
the path between points X and Y:

R(X-Y) =ΔT(X-Y)P(X-Y)

Minor heat path
Major heat path
Junction

aaa-034540

Reference points X and Y can be every point in the thermal system underinvestigation. In Nexperia datasheets, the common situation is point X to be thejunction of the semiconductor device (Tj) and the point Y to be the solder point of
the package or the ambient (temperature). This is depicted in Figure 71.

Solder point
mounting base
Ambient

4

Diode Application Handbook

In this way Nexperia defines and uses several common Rth(j-Y) values as found in
Table 21.

Table 21: Definition of common Rth(j-Y) values.
Value
Junction toambient

Junction tosolder point /mounting baseJunction to
top / case

Solder point
to ambient

Sign

Description

Rth(j-a)Overall thermal resistance of the system
including package, solder joints, PCB and
optional other thermal design relevant
components.

Rth(j-sp)
Rth(j-mb)

Thermal resistance of the device. Reference
point on the outside of the package is the pin or
package heatsink of the main heat dissipation
path. Mounting base is mainly used for power
oriented packages with a package heatsink,solder point is mainly used for smaller SMD or
DFN packages.

Rth(j-top)Rth(j-c)

Thermal resistance of the minor heat dissipation
path from device junction to the hottest spot
on the top surface of the device. This parameter
is not used nor accessible in real applications
without top side cooling (see 3.1.6 for details).

Rth(sp-a)

Thermal resistance of the whole system without
the packaged device. Reference point on thedevice side is always the connection point to themain heat dissipation path of the device.
Ambient reference point is always the ambient
air temperature (commonly 25°C or room
temperature).

Y(j-top)

Coefficient characterizing the temperature
difference from device junction to the hottest
spot on the top surface of the device incorrelation to the overall device power. Strictly
speaking not a thermal resistance (see 3.1.6 fordetails).

PCB

Figure 71 | Sketch showing the main heat flow.

102

Coefficientjunction to top

Thermal considerations

Thermal considerations

4

103

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Diode Application Handbook

4.1.3 Approximations

4.1.4 Clip bonded packages

Looking at the formal definition of a thermal resistance we can see that for thecommonly used Rth values from Table 21 some approximations have been applied
and there are inaccuracies which are commonly not spoken out in the field anddatasheets.

Clip bond packages differ thermally in one significant way from wire bonded
packages. The heat dissipation from the junction of the device has two different
paths it can follow, as shown in Figure 73. Along the leadframe, as for wire bonded
packages and along the clipframe, which is a similarly good dissipation path as via
the leadframe. This has some interesting implications and opportunities forthermal design of the PCB.

Besides the main heat dissipation path shown in Figure 71 for a wire bonded
semiconductor device, there are also minor heat dissipation paths, as shown in
Figure 72.

Minor heat path

Minor heat path

Encapsulation surfaces

Major heat pathaaa-034608

Encapsulation surfaces

Major heat path

Thermal considerations

nexperia | Design Engineer’s Guide

aaa-034609

Thermal considerations

4

Junction

Junction
Solder point of
second heat path
Solder point ofminor heat path

Solder point ofﬁrst heat path

Solder point of
main heat path

PCB

PCB
Figure 73 | Heat dissipation flow in clip-bonded packages.
Figure 72 | Sketch highlighting minor heat dissipation paths.

Looking at Rth(j-a) values, we can use the formula given in 3.1.2 to calculate thethermal resistance, since in the end, all power from the device is dissipated to theambient between the reference points junction and ambient.
Looking at the Rth(j-sp) values we come to the first approximation. The minor power
dissipation paths as shown in Figure 72 are considered negligible and theircontribution is omitted in the calculation of thermal resistances. In reality, thepower dissipated between the reference points is lower than the overall power
dissipated at the device.
For wire bonded devices this approximation is reasonable, since all the minor paths
are low in contribution. The situation becomes more complex looking at clip
bonded or multi die devices, or even at thermal resistances which are consideredminor. The next chapters will cover clip bonded devices, multi die devices and will
look at the commonly used ‘Rth(j-c)’ or ‘Rth(j-top)’ value.

104

Firstly, the definition of a Rth(j-sp) value is not as straight forward as for wire bonded
packages. While wire bonded packages have only one significant dissipation path,clip bonded packages have two. Looking at the definition of the thermal resistancethis means that the solder reference point is split into two, which do not necessarilyneed to have the same temperature. The thermal resistance of the whole device is
now a parallel network of two resistances, which do not necessarily need to be at
the same reference point (temperature) on the side of the solder point.
Nevertheless, Nexperia follows the same procedure to extract the Rth(j-sp) values
for clip bonded devices as for wire bonded devices. The value characterizes themain dissipation path through the die to the leadframe to the solder point (most of
the time cathode pin). This makes the values of clip bonded products comparable
to the wire bonded products, if used in a similar PCB layout. Nevertheless, theoverall potential of the device is typically higher, since the second path is not used
to its full possibilities while extracting the Rth(j-sp) value.
The fact that there is a second significant dissipation path creates some good
opportunities in PCB design. Whilst with wire bonded devices the only option is toremove heat via a single path (most via the cathode pin), with clip bonded devices
both terminals can be used. This significantly improves the thermal performance ofthe system by offering good thermal paths on the PCB for all terminals. The
following thermal simulation is intended to illustrate this.

105nexperia | Design Engineer’s Guide

The simulation of the heat dissipation in a PMEG6030ELP in CFP5 package showsthat 35% of the heat can be transferred via the cupper clip into the anode pin while
the heat dissipation through the leadframe into the cathode pin accounts for 65%
of the overall heat dissipation. This means there is the potential to remove asignificant amount of the dissipated power through the anode pin into the PCB.
This also gives the possibility to place the cooling pad for the diode on the PCB
differently, if necessary for the PCB design. Simulations in Figure 74 show that witha 1cm² heatsink area at the anode pin instead at the cathode pin only a reduction of
overall dissipated power of ~5% has to be accepted (assuming a maximum junction
temperature of 150°C).
It is obvious that the additional heat dissipation path also offers the possibility todissipate more power in the clip bonded package. By placing 0.5cm2 heat sink areasat each terminal of the package, as illustrated in Figure 74, it is possible to run thediode at the same junction temperature with approx. 20% more overall power
dissipation compared to a standard design where only the cathode side has a heatsink the size of 1cm².

Diode Application Handbook

4.1.5 Multiple chip devices
Devices with more than one chip can be very complex thermally in the real world,
since the operational state of the first chip will influence the (thermal) behavior of
the second and vice versa. Strictly speaking the Rth(j-sp) of the first device is afunction of the temperature of the second chip.
In datasheets, Nexperia gives the Rth(j-sp) of one of the chips while the second one isinactive (no heat generation). This is the same approach as for the clip bonded
devices, where the Rth(j-sp) is retrieved in the same way as for all single chip wire
bonded devices. In this way also the Rth(j-sp) values of dual or multi chip devices arecomparable to the single chip devices and each chip of the device can becharacterized independently. Since the vast majority of multi-chip devices are
symmetric dual chip devices, we only give one valid Rth(j-sp) value for each chip inthe device (while the others are inactive).

4
Thermal considerations

Thermal considerations

4

To give a rough overview on what the influence of the second chip in the device is,thermal resistances Rth(j-a) are given ‘per chip’ (only one chip active) and ‘per device’(both chips on the same Tj). These are the corner stones of the thermal range thewhole device can be operated in.

4.1.6 Rth(j-c) and why Nexperia calls it Ψ(j-top)

PCB type

70µm Cu
Single layer
FR4 PCB

The topic of Rth(j-c) can be confusing. There are several definitions of this resistanceand most of the time it is not stated clearly what is meant by this parameter. Fromdiscussions with customers we see that some people consider it to be the thermal
resistance of the device from junction to a package heatsink (e.g. screw hole of
TO220), which would be the same as Nexperia’s Rth(j-sp) or Rth(j-mb) values. Others
refer to it as the thermal resistance from the junction of the device to the top of
the plastic body of the package. This is a thermal resistance on a minor heatdissipation path and some implications need to be considered when working withthis parameter.

Heatsink area atcathode pin (cm²)

Heat sink area atanode pin (cm²)

Ptot atTj=150°C (mW)

0.5

0.5

1337

106%

1

0

1260

100%

0

1

1190

94%

6

0

1940

100%

3

3

2329

120%

Figure 74 | Simulations also show that splitting the heatsink between both terminals(as shown in Figure 4) is advantageous to heat dissipation.
If a 1cm² heatsink is split into two 0.5cm² heatsinks beneath both terminals, the power that can be
dissipated by the diode at the same temperature increases by 6%.
Two 3cm² heatsinks allow for approximately 20% more power dissipation than with a standard
design and a 6cm² heatsink at only the cathode.

106

Most of the time, the Rth(j-c) parameter for small signal devices can be thought of as
the relation of the top package temperature to the junction temperature in
relation to the power dissipated over the device. The application behind this is themeasurement of the top package temperature with an IR camara to calculate thejunction temperature together with the overall power dissipated in the device. Thisis perfectly valid, but some considerations need to be taken into account. These
considerations are the reason why Nexperia calls this parameter Y(j-top).

107

nexperia | Design Engineer’s Guide

Firstly, we need to know that we are looking at a minor heat dissipation path, which
is usually neglected in the overall picture (compare Figure 72). If we follow strictly
the definition of a thermal resistance (see 3.1.2) to calculate thermal resistancefrom junction to case (top of the package) Rth(j-c) = Rth(j-top) we need to take thetemperature difference from the junction of the device to the top of the package
and divide it by the power dissipated along the same (!) path. Note: this is not theoverall power of the device in operation, nor is it close to it. It is a fraction of theoverall power which is for most small signal devices below 1% of the overall power
consumption. Or to put it in other words, the real Rth(j-top) is not accessible in realapplications nor is it useful for the purposes of calculating the junction
temperature via the top package temperature and the overall device power
consumption.
The coefficient in question is, strictly speaking, not even a thermal resistance, sincetemperature difference and power dissipation path differ from each other.
Therefore, Nexperia calls this coefficient Y(j-top).
As in the previous chapters concerning clip bonded packages or multiple die
devices, we are considering heat as a resistor network. Again, the parameter is now
dependent on the condition of the reference points. We need to take into accountthat the proportions of the heat going through the different dissipation paths(major and minor) may shift depending on the ambient conditions. For example,
devices on a PCB with an overall low Rth(sp-a) dissipate a higher percentage of thepower over the main dissipation path than devices on a PCB with high thermal
resistance. In consequence, the relations between these two paths is shifted andthe value of Y(j-top) changes with the ambient conditions.
It is not only the PCB that will affect this value. All ambient conditions which affectthe heat dissipation from the device will do so: e.g. forced air flow or free air flow;high overall temperature level or low overall temperature level; temperature
gradients or even heat radiation from nearby surfaces. The Y(j-top) parameter iscurrently only available on request and there will be no single value, always a range.
The parameter is retrieved via thermal simulations of the system on different PCB
layouts (i.e. ambient conditions).

4

Diode Application Handbook

4.2 Thermal considerations in forward bias
As with any other electronic device, diodes have to be operated within the
maximum junction temperature as defined in the data sheet. In forward bias,
power is dissipated in the device, increasing the junction temperature. The
resulting temperature rise must not exceed the specified maximum junction
temperature. If the specified junction temperature is exceeded the reliability of thediode may be affected leading to failures.

4.2.1 Continuous current

Thermal considerations

Thermal considerations

4

In case of a continuous forward current, the rated current through the diode can beeasily calculated. The following input is needed to calculate this: the specified
maximum junction temperature Tjmax; the specified thermal resistance junction toambient according to the utilized PCB type and the footprint; the ambient
temperature Ta ; and the forward voltage drop VF at rated TJmax and at theappropriate value of IF:

IF =Tjmax − Ta
VF × Rth(j-a)

This equation can be solved for Ta to calculate the maximum ambient temperature
for a given forward current.

4.2.2 Pulsed operation
In a pulsed operation the junction temperature also depends on the width and the
duty cycle of the pulse. As these are dynamic processes, it is now necessary to use
the thermal impedance Zth rather than the steady-state thermal resistance Rth. The
thermal impedance is specified in the data sheet of the diode based on the thermal
response curve, as described in 0. With a current pulse of a given pulse width tp,
duty cycle δ and peak current Ipeak the maximum tolerable ambient temperature iscan be calculated from:

Ta = Tjmax − Ipeak × VF × Zth(j-a)(δ, tp)
Tjmax is here again the maximum specified junction temperature. VF is the forward
voltage drop at rated TJmax and Zth(j-a)(δ, tp) is the thermal impedance junction toambient being a function of the pulse width tp and the duty cycle δ.

108

109

nexperia | Design Engineer’s Guide

This equation can also be used to calculate the peak current, the average current
and the root mean square of the current for a given ambient temperature. The
following example is a rectangular signal:
I

I√δ

Ipeak = average = rms =δ

4Diode Application Handbook

4.3 Thermal considerations in reverse bias

Tjmax − Ta
VF × Zth(j-a)(δ, tp)

This is also how the graphs in the data sheets are calculated, and with which
manufacturers indicate the average current depending on the ambient
temperature and the solder point temperature for a given switching frequency, as
shown in Figure 75. If the solder point temperature is selected as the reference
point, the equations shown above still apply, only the ambient temperature is
replaced by the solder point temperature.

In the reverse direction, the device self-heating caused by the leakage current of
the diode is extremely important for a safe operation of the diode. The boundaries
for safe operation of the diode in reverse bias are defined by the safe operatingarea (SOA) graph of the diode in its data sheet. Operating a rectifier within its safe
operating area with a sufficient safety margin is crucial for a robust design,especially at the high ambient temperatures seen in high power density or hightemperature automotive applications. This section describes what thermal stability
and the associated thermal runaway of the diode mean; subsequently, thecalculation of the SOA is demonstrated. The main factors influencing the thermal
limits of a rectifier are discussed.

Thermal considerations

Thermal considerations

4

IF(AV) (A)
3.5

Tj = 175°C

aaa-033547

aaa-033546

4.3.1 Rectifier as thermal system – thermal runaway

IF(AV) (A)5
Tj = 175°C

3.0

4

The thermal stability of a rectifier in reverse direction is determined by theinteraction of its leakage current which causes self-heating, and the capability of
the rectifier to dissipate this heat through the thermal resistance in the system. In
thermal equilibrium, the junction temperature of the device can be described asfollows with a fixed ambient temperature Ta as thermal ‘ground’:

2.5

Tj = Rth(j-a) × Pdissipated + Ta

3

2.0
1.5

2

where Rth(j-a) is the thermal resistance between junction and ambient, and Pdissipatedis the amount of dissipated power in the device.

1.0

δ = 1; DCδ = 0.5; f = 20kHz
δ = 0.2; f = 20kHz
δ = 0.1; f = 20kHz

0.5

δ = 1; DCδ = 0.5; f = 20kHz
δ = 0.2; f = 20kHz
δ = 0.1; f = 20kHz

1

0

0
0

50

100

150

200

Tamb (°C)

0

50

100

150

200

Tsp (°C)

Figure 75 | Average forward current of an exemplary diode as a function of the duty cycle and of
the ambient temperature of solder point temperature.

Please notice that the average currents in Figure 75 are bordered by plateaus. The
plateaus are set by the manufacturers, defining a maximum root mean squarecurrent through the diode. This value is defined by the current carrying capability of
the connections inside the package and the external connections.

110

A steady state condition is achieved as the result of two competing processes: thecapability of the thermal system to dissipate heat through the thermal resistance(as described by the formula above) and the self-heating of the device (Pgenerated)
generated by its own reverse leakage current (and, technically-speaking, also by
possible switching losses), with increasing leakage current over the junction
temperature. These processes are shown in Figure 76.
In Figure 76, the curve representing the dissipated power intersects the x-axis atambient temperature and then rises with a slope which is proportional to thethermal conductance (1/Rth) of the system. The generated power caused by theleakage current of the diode increases exponentially when the junction
temperature increases, as the leakage current increases exponentially overtemperature. The intersections of the two curves give the co-ordinates for an
equilibrium condition. The first intersection corresponds to the stable operation of
the system. As long as the generated power through self-heating is smaller than111

nexperia | Design Engineer’s Guide

4

Diode Application Handbook

However, if more power is generated than dissipated (intersection representing
unstable operation) the junction temperature increases until the device eventually
becomes thermally unstable. This is termed ‘thermal runaway’. The device will draw
more and more current until it fails completely due to thermal overstress. Figure 77
shows an x-ray picture of a device which has failed due to thermal runaway. In thiscase, the fusing current of the wire bond has been exceeded. In the case of clip
bond packages, the die itself would be destroyed by thermal overstress. The
discoloration of the epoxy molding compound testifies to the high heat
experienced by the device.
The temperature gap between stable and unstable operation is the safety marginof the system. With an increase in ambient temperature, this safety margin shrinks
until the stable and the unstable conditions coincide (Figure 78). This is obviously
dP= R1 occurs.
the case when the condition generated
dT

Thermal considerations

the dissipated power, the junction temperature of the device decreases and, inthermal equilibrium, converges toward a stable condition. Interestingly, this simple
model also explains the heating-up of the device when the system is switched on,as the junction temperature converges to the stable condition (illustrated in
Figure 76 by the red arrow pointing to the stable condition).



Figure 77 | Failed device due to thermal runaway. The X-ray picture reveals that the fusing currentof the wire bond has been exceeded. In the left hand picture, the epoxy molding compound is
discolored through the heat.

aaa-031555

Thermal considerations

4

P (W)
2

th

aaa-031553

1.5

P (W)
2

2

1

1

2

0.5

stable condition
0
0

Tamb

50

100

1

0.5

unstable condition

1.5

112

1

150

Tj (°C)

Figure 76 | The equilibrium condition is theoutcome of two parallel processes: thegenerated power (self-heating) caused by thereverse leakage current of the rectifier(red line – nr. 2) and the capability of the system
to dissipate power through the thermal
conductance (blue line – nr. 1). Theintersections of the two graphs are theco-ordinates where this occurs. The values of x
and y axes are exemplary.

0
0

Tamb

50

100

150

Figure 78 | With an increase in ambient
temperature, the dissipated power curve(line 2) moves along the x-axis while thegenerated power curve (line 1) remains
unchanged. The safety margin shrinks until thestable and the unstable conditions coincide anddP
1
the condition generated= R for thermaldTthrunaway is fulfilled.

Tj (°C)

113

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Diode Application Handbook

4.3.2 The safe operating area (SOA) of a rectifier in reverse direction

4.3.3 Impact of technology on the SOA of a rectifier

The limits given by the thermal runaway condition define the safe operating area ofa rectifier in reverse direction. For each reverse bias voltage, VR, the corresponding
leakage current, IR, is measured over junction temperature. By applying theformula:According to the formula dPgenerated= R1 there is a strong impact of the thermaldTthresistance of the system on the SOA of the rectifier as described in previous
section. As a result, the SOA of a rectifier can be extended by using packages with alow junction-to-solder-point thermal resistance Rth(j-sp), and/or by using PCBs or
substrates with improved thermal properties, e.g. ceramic PCBs.

the temperature limit for thermal runaway can be calculated for each reverse bias
point for a given Rth. As a result, a curve is generated which shows the maximum
thermally stable reverse voltage for a rectifier based on its junction temperature,
as shown in Figure 79. In practice, the SOA graph in Figure 79 is used as follows:
for a given application where the Rth(j-a) of the product is known, the requested
maximum reverse voltage defines the maximum junction temperature according tothis graph. Now, the generated power can be calculated by taking into account theleakage current of the device at the given reverse voltage and junction
temperature as given in the rectifier datasheet. Finally the maximum allowableambient temperature can be easily calculated:aaa-034610

dPgenerated
× Rth ≥ 1 (with Pgenerated = VR × IR)
dT
1
10 −

Thermal considerations

nexperia | Design Engineer’s Guide

JR (A/mm) @ VR = 100V

Thermal considerations

4

10 −
10 −
10 −
10 −
10 −
10 −

Tamb_max = Tj _max − Pgenerated × Rth(j-a)

10 −120V SiGe Rectiﬁer
Low IR planar Schottky
Low Vf planar Schottky
Hyperfast recovery rectiﬁer
100V Trench Schottky

10 −
10 −

aaa-031556

Percent of rated peak reverse voltage (%)
120
For a deﬁned Rth

10 −
0

100

25

50

75

100

125

150

175

200

TJ (°C)80

Figure 80 | Leakage current density of five different rectifier technologies measured at 100V
reverse bias over temperature.

60

40

20

0
0

50

100

150

200

Junction temperature (°C)

114

Figure 79 | Plotting the maximum reverse
voltage and junction temperature of therectifier. For a given Rth, the derating curve
defines the maximum reverse voltage therectifier can withstand before going into
thermal runaway.

115• 100V low leakage current planar Schottky;• 100V low Vf planar Schottky;• 200V hyperfast recovery rectifier;• 120V SiGe (silicon germanium) rectifier• 100V Trench Schottky
As expected, the highest leakage current density is observed for the low Vf
Schottky rectifier technology, since this uses a Schottky metal with a low work
function. The leakage current density of the low leakage planar Schottky
technology is two orders of magnitude lower, showing the exponential impact of
the barrier height on the leakage current. A very low reverse current density isachieved by the hyperfast recovery rectifier (an even lower leakage current can be
expected for recovery rectifiers with standard switching speeds, not shown in thiscomparison). Interestingly, the leakage current density for the novel SiGe rectifier
technology is at the same level as for the hyperfast recovery rectifier. The Trench
Schottky technology reveals a slighter higher reverse leakage current density overtemperature compared to the low leakage planar Schottky. This illustrates the
improved IR/Vf trade-off of the Trench technology, as described in section 1.2.3.
The decisive factor in determining the thermal stability of the rectifier in reverse
direction is not the leakage current itself but the increase rate in leakage current
over temperature. Therefore, the graphs in Figure 80 need to be differentiatedwith respect to temperature. The results are shown in Figure 81. Due to the
exponential progress of the reverse leakage current density over the temperature,
its derivative is also exponential and therefore linear on a log-scale. After the= dIdTR × VR > R1 ) the
derivation (as indicator of thermal stability according to dPgenerateddTthorder remains the same, with SiGe and hyperfast technologies showing the highest
potential for thermal stability and the low Vf planar Schottky with the lowest
potential in this regard.

10 −
10 −
10 −
10 −
10 −

Thermal considerations

Another important aspect is the impact of the chosen rectifier technology on the
SOA, as the generated power is caused by the reverse leakage current of therectifier at a given bias point. In order to compare the leakage current of different
technologies, it makes sense to use the leakage current density rather the leakage
current itself. This method eliminates the impact of the die size and makes a faircomparison of the different technologies possible. The graphs in Figure 80 show
the behavior of the leakage current density at the reverse voltage of 100V
depending on the junction temperature for five different technologies. The chosen
technologies are as follows:

4

Diode Application Handbook

aaa-034611

nexperia | Design Engineer’s GuidedJR/dT (A/mm/°C) @ VR = 100V

Thermal considerations

4

10 −
10 −
10 −
10 −
120V SiGe Rectiﬁer
Low IR planar Schottky
Low Vf planar Schottky
Hyperfast recovery rectiﬁer
100V Trench Schottky

10 −
10 −
10 −
0

25

50

75

100

125

150

175

200

T (°C)

Figure 81 | Derivative of leakage current density at 100V reverse bias with respect to junction
temperature for different rectifier technologies.

4.3.4 Impact of package on the SOA of a rectifier
In order to study the influence of the package on the safe operating area for agiven technology, it is again necessary to use normalized currents to exclude theinfluence of crystal sizes. As a consequence, the thermal resistance must also be
normalized. For this purpose, the thermal resistance is normalized with respect tothe package size (strictly speaking, to the footprint area). In this way a stability
factor can now be calculated for a given reverse voltage:
dJ R
× VR × RT
dTWith RT being the normalized thermal resistance of the system.

116

117

10
VR = 100V
RT = 630K/W/mm²

10
10Stability
limit

1
10 −
10 −
10 −

120V SiGe Rectiﬁer
Low IR planar Schottky
Low Vf planar Schottky
Hyperfast recovery rectiﬁer
100V Trench Schottky

10 −
10 −
10 −

aaa-034612

VR = 100V
RT = 2970K/W/mm²

10
10

25

50

75

100

125

150

175

200

TJ (°C)
Figure 83 | Stability factors for different technologies in DFN1110D-3 (SOT8015) package at 100V
reverse voltage. For stability factors greater than 1 (stability limit), the rectifier will become
thermally unstable. For this comparison the Rth(j-a) of DFN1110D-3 on a standard footprint on asingle layer PCB has been normalized with respect to recommended footprint area of this package.

Stability
limit

1

aaa-034614

Stability factor

010

Thermal considerations

As long as this equation remains below 1 the system is thermally stable; systems
with values greater than 1 will eventually get thermally unstable. Following up on
Figure 81, the stability limits are shown for different technologies in SOT23. For
this comparison, the Rth(j-a) of a SOT23 on standard footprint and single layer PCB
has been normalized with respect to recommended footprint area of SOT23. This
result states that under these conditions, a planar low Vf Schottky diode in 100V
reverse bias can only be operated up to a junction temperature of 41°C without
thermal runaway. The SiGe diode and the hyperfast recovery rectifier on the other
hand can handle junction temperatures beyond 150°C without becoming thermallyunstable. Now for comparison let’s do the same exercise for the DFN package
DFN1110D-3 (SOT8015). As described in 4.3.1 below, DFN packages are very
compact housings that are nevertheless thermally excellent. The results are shownin Figure 83. The stability limit for the planar low Vf Schottky technology at 100V
reverse voltage is shifted to Tj = 62°C. This results highlights the high thermal
potential of DFN packages despite the much smaller package size. Keep in mind
that the absolute value of thermal resistance junction to ambient for this package isbigger than for SOT23. However, this value is achieved on a much smaller footprint.

4

Diode Application Handbook

aaa-034613

nexperia | Design Engineer’s Guide

Stability factor

Thermal considerations

4

Convection

10 −

Radiation
10 −
Die

Die bond

Lead-frame

Solder

Cth2

Cth3

Cth4

PCB

10 −

Ptot (tpulse)
120V SiGe Rectiﬁer
Low IR planar Schottky
Low Vf planar Schottky
Hyperfast recovery rectiﬁer
100V Trench Schottky

10 −
10 −

Tj

Cth1

Tsp

Cth5

Tambient

10 −
0

25

50

75

100

125

150

175

200

TJ (°C)
Figure 82 | Stability factors for different technologies in SOT23 package at 100V reverse voltage.
For stability factors greater than 1 (stability limit), the rectifier will become thermally unstable. For
this comparison the Rth(j-a) of SOT23 on a standard footprint on a single layer PCB has beennormalized with respect to recommended footprint area of SOT23.

118

Figure 84 | A diode in a SMD package as thermal system. The heat is transferred from thereference point “j” (junction) to the reference point “ambient”. For transient processes not only thethermal resistances need to be considered but also the thermal capacitances in the system, which,according to the electrical analogy, must first be charged before the heat can spread. The dynamic∂Tthermal impedance describes this heat transfer: Zth(j-a)(tpulse) = ∂P .
tot

119

In pulsed applications, the device as the thermal system might not reach the steadystate condition during the course of operation. In this case it does not make sense
to use the steady state thermal resistance, rather the dynamic thermal impedancemust now be used.

4.4.1 The dynamic thermal impedance Zth
The dynamic thermal impedance Zth basically describes the time dependence of theheat transfer. For transient processes not only the thermal resistances need to beconsidered but also the thermal capacitances in the system, which, according to theelectrical analogy, must first be charged before the heat can spread (Figure 84).
This transient heat flow between two reference points, A and B, resulting in atemperature difference between these points, is described by the dynamic thermal
impedance Zth which is a function of the applied pulse to the system:∂T
Zth(A–B)(tpulse) =| t = tpulse∂P
As described in chapter 2, the Zth values are specified as a set of curves in the data
sheet. They can be used to calculate the heating of the diode as a thermal system
under pulsed conditions. Here, the pulse width and the duty cycle of the signal
must be taken into account.

4.4.2 Foster and Cauer model
As shown in Figure 84 the dynamic thermal behavior of discrete semiconductor
devices can be described by a RC thermal network. Foster and Cauer models areequivalent electrical representations of the thermal RC network that can represent
the thermal performance of a discrete device, and used within a SPICE
environment. This section provides some basic theory behind the principle, andhow to implement Foster and Cauer RC thermal models. For convenience, Foster
and Cauer RC thermal models are referred to as RC models in the following pages.
Several methods of using RC thermal models, including worked examples, will be
described.

120

RC models are derived from the heat-up curves based on the dynamic thermal
impedance of a device, as shown in Figure 85 for PMEG050T150EIPD. As alreadydescribed in chapter 3, this Figure represents the thermal behavior of a device
under transient power pulses. Zth can be generated by measuring the power losses
as a result of applying a step function of varying time periods.

10

duty cycle = 1
0.75
0.50

Thermal considerations

4.4 Transient effects

4

Diode Application Handbook

aaa-027070

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Zth(j-a) (K/W)

Thermal considerations

4

0.33

0.25
0.20
0.10

10
0.05

0.02
0.01
0

1
10 −

10 −

10 −

1

10

10

10

tp (s)

Figure 85 | Transient thermal impedance for PMEG050T150EIPD from junction to ambient as afunction of pulse duration and duty cycle. Device mounted on standard footprint and on a single
layer FR4 PCB; typical values.

According to Figure 85, a device subjected to a power pulse of duration >200
seconds, i.e. steady-state, has reached thermal equilibrium and the Zth plateaus
becomes the Rth. The Zth illustrates the fact that materials have thermal inertia.
Thermal inertia means that temperature does not change instantaneously. As aresult, the device can handle greater power for shorter duration pulses. Zth curves
for repetitive pulses with different duty cycles are also shown in Figure 85. These
curves represent the additional RMS temperature rise due to the dissipation of
RMS power.

121

Table 22: Elements of electrical and thermal analogy.

Calculating junction temperature rise
To calculate the temperature rise within the junction of a semiconductor device
with a single active area (i.e. heat source at the junction), the power and duration of
the pulse delivered to the device must be known. If the power pulse is a square,then the dynamic thermal impedance can be read from the Zth chart. The productof this value with the power gives the temperature rise within the junction. If
constant power is applied to the device, the steady state thermal impedance can beused i.e. Rth. Again the temperature rise is the product of the power and the Rth.

Type

Resistance

Potential

EnergyCapacitanceElectrical(R = V/I)

R = ohmic
resistance(Ohms)

V = electricalpotential (Volts)

I = current(Amps)

C = capacitance(Farads)

Thermal(Rth = K/W)

Rth = thermal
resistance(K/W)

K = temperature
difference(Kelvin)

W = dissipatedpower (Watts)

Cth = thermal
capacitance(thermal mass)

For a transient pulse e.g. sinusoidal or pulsed, the temperature rise within thedevice junction becomes more difficult to calculate.
The mathematically-correct way to calculate Tj rise after an event with the duration
τ is to apply the convolution integral. The calculation expresses both the power
pulse and the Zth curve as functions of time, and use the convolution integral toproduce a temperature profile:∆Tj = ∫ 0τ P(t)dZth(τ – t)dt
dt

However, this is difficult as the Zth(τ–t) is not defined mathematically. An alternative
way is to approximate the waveforms into a series of rectangular pulse and apply
superposition. While relatively simple, applying superposition has its disadvantages.
The more complex the waveform, the more superpositions that must be imposed
to model the waveform accurately.
To represent Zth as a function of time, we can draw upon the thermal electricalanalogy and represent it as a series of RC charging equations or as an RC ladder.
Zth can then be represented in a SPICE environment for ease of calculation of thejunction temperature.

Association between thermal and electrical parameters
The thermal electrical analogy is summarized in Table 22. If the thermal resistanceand capacitance of a semiconductor device is known, electrical resistances andcapacitances can represent them respectively. Using current as power, and voltage
as the temperature difference, any thermal network can be handled as an electrical
network.

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Thermal considerations

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Foster and Cauer RC thermal models
Foster models are derived by semi-empirically fitting a curve to the Zth, the resultof which is a one-dimensional RC network shown in Figure 86 . The R and C values ina Foster model do not correspond to geometrical locations on the physical device.
Therefore, these values cannot be calculated from device material constants as canbe in other modeling techniques. Finally, a Foster RC model cannot be divided orconnected through, i.e. have the RC network of a heat sink connected.

R1

R2

Rn

C1

C2

Cn

aaa-010334

Thermal considerations

4

Figure 86
Foster RC thermal
model.

Foster RC models have the benefit of ease of expression of the thermal impedanceZth. For example, by measuring the heating or cooling curve and generating a Zthcurve, the following equation can be applied to generate a fitted curve as shown in
Figure 87:

Zth(t) = ∑t−nτ i ) where τ = R × C
Ri
×
(1
−
e
i
i
i
i=1

The model parameters Ri and Ci are the thermal resistances and capacitances used
to create the thermal model depicted in Figure 86. The parameters in the analyticalexpression can be optimized until the time response matches the transient system
response by applying a least square fit algorithm.

123

R1
C1

Foster models have no physical meaning since the node-to-node heat capacitances
have no physical reality. However, a Foster model can be converted into its Cauer
counterpart by means of a mathematical transformation.

Zth
Zth Curve
overlaid withsummed RC

R2

Rn

C2

Cn

Nexperia provides Foster and Cauer RC models for many of its products on the
product information pages. The models can be found under the tabs
‘Documentation’ and ‘Support’. Foster and Cauer RC thermal models allow
application engineers to perform fast calculations of the transient response of a
package to complex power profiles. In the following sections, examples of using RC
thermal models will be presented. Foster models and Cauer models are equivalent
representations of the device thermal behavior but in the described examples Cauer
models will be used as more representative of the physical structure of the device.

Table 23: PMEG050T150EIPD
Cauer model netlist
RC ModelZth************* Part: PMEG050T150EIPD

RC curves,
representing
RC elements* Cauer style thermal RC networkmodel of Rth(j-sp).
Time************.subckt cauer 1 6 7

Figure 87 | Foster RC thermal model. Individual Ri and Ci combinations sum up to make the Zthcurve.

As seen for the Foster model, the Cauer model also consists of an RC network but
the thermal capacitances are all connected to the thermal ground, i.e. ambient
temperature as represented in Figure 88. The nodes in the Cauer model can havephysical meaning and allow access to the temperature of the internal layers of thesemiconductor structure.

R1

1

2

0.113734

R2

2

3

0.0998565

R3

3

4

0.229452

R44

50.346807R55

60.0136469

C1

1

7

0.00317279

C2

2

7

0.00101058

C3

3

7

0.00491032

C4

4

7

0.00614301

C5

5

7

0.0274844.end cauer

124

Figure 88
Cauer RC thermal
model.

Thermal considerations

The individual expression, ‘i’, also draws parallels with the electrical capacitor
charging equation. Figure 87 shows how the individual Ri and Ci combinations sum
up to make the Zth curve.

An n-stage Cauer model can be derived from an n-stage Foster model and they will
be equivalent representations of the device thermal performance.

4

Diode Application Handbook

aaa-031516

nexperia | Design Engineer’s Guide

aaa-010335

Thermal considerations

4

The netlist in Table 23 describes the
Cauer network and can be used to build
the Spice schematic shown in Figure 89.
Pin 1 in the netlist can be identified as
the junction temperature pin Tj in theschematic. Similarly pins 6 and 7 as theTamb pins in the schematic.
In order to simulate, only device pins 6
and 7 are tied to the ambient voltage
source, as shown in Figure 89. One of
the advantages of using Cauer models isthat external networks can be added tothe device model, for example to model
PCBs and heatsinking. In order to do so,
pin 7 will be tied to ambient, and pin 6
to the first pin of the external Cauer
network. For correct results, the end pinof the external Cauer network must be
tied to the ambient source.

125Thermal simulation example

4

Diode Application Handbook

Figure 89 | PMEG050T150EIPD
Cauer model setup in Spice.

PMEG050T150EIPD

RC thermal models are generated from the Zth heat-up curves. This example shows
how to work back from the RC model and plot a Zth curve within a SPICE simulator.
This makes it easier when trying to read values of the Zth curve from the data sheet.

Tj
C1
0.00317279

R1
0.113734

Tamb
I=1

This example and subsequent others use the RC thermal model of
PMEG050T150EIPD. Tsp represents the solder point temperature. It is treated as an
isothermal, and for this example is set at 0°C. A single shot pulse of 1 W power isdissipated in the device. For a single shot pulse, the time period between pulses isinfinite and therefore the duty cycle δ = 0. Thus the junction temperature Tj
represents the transient thermal impedance Zth.

Ptot

C2
0.00101058

R2
0.0998565

TambC30.00491032

R3
0.229452

Tamb
C40.00614301

Thermal considerations

nexperia | Design Engineer’s Guide

aaa-034615

Thermal considerations

4

R4
0.346807

Tamb
C50.0274844

Tj = Tsp + ∆T = 0°C + ∆T = ∆T

1. Set up the RC thermal model of PMEG050T150EIPD in SPICE as shown in
Figure 89
2. Set the value of voltage source Vsolderpoint to 0, which is the value of Tsp
3. Set the value of the current source Ptot to 1
4. Create a simulation profile and set the run time to 100 ms
5. Run the simulation
6. Plot the voltage at node Tj
The simulation result in Figure 90 shows the junction temperature (voltage at Tj)
which is also the thermal impedance of PMEG050T150EIPD. The values of Zth atdifferent times can be read using the cursors on this plot within SPICE. The value ofthe current source in this example is set to 1 A to represent 1 W dissipating throughthe device. It can be easily changed to represent any value of power. The simulationcommand can be changed for any duration to represent a range of square power
pulses. The SPICE simulation can also be used to investigate the junction
temperature for any power profile applied to the diode.

126

Tamb

Figure 90 (below) | Simulated junction
temperature vs. time for an applied power of
1W to PMEG050T150EIPD. Solder pointtemperature set at 0°C.

Vsolderpoint0

aaa-034616

The equation above demonstrates that with P = 1W, the magnitude of Zth equates
to ΔT. The following steps are used to set up and run simulations:

Tamb

Simulated Juntion temperature (°C)

∆T = P ∙ Zth = 1W ∙ Zth

R5
0.0136469

1

10 −

10 −

Cauer model PMEG050T 150EIPD
TSP = 0°C
−

10 
10 −

10 −

1

10

10

time (ms)

127

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Diode Application Handbook

Chapter 5
Diode packaging

Diode packaging

Thermal considerations

4129

nexperia | Design Engineer’s Guide

Nexperia offers a wide range of packages for diodes, ranging from through-holepackages – a technology which marked the beginning of the mass production ofelectronics products in the 1950s – to the most modern packages in the industry.
A categorized overview of the Nexperia diode package portfolio is shown in
Figure 91.

Surface Mount Technology /Devices (SMT/SMD)LEADED
Packages

Through
Hole
Technology
LEADLESS
Packages

WIRED
Packages

Wire bonded

Clipbonded/CFP(Clip Flat
Power)DFN(Discrete Flat
No Lead)

CSP(Chip Scale
Package)SpecialForm
Factors

Axial
leadedSOD123, SOD123F,
SOD323, SOD323F,
SOD523, SOT143B,
SOT223, SOT23,
SOT323, SOT353,
SOT363, SOT457,
SOT663, SOT666,
SOT89

CFP2-HP,
CFP3-HP,
CFP3,
CFP5,
CFP15B

DFN1608D-2,
DFN1006-2,
DFN1006D-2,
DFN1006BD-2,
DFN2020-3,
DFN2020D-3,
DFN1010D-3,
DFN1412D-3,
DFN1110D-3,
DFN1006-3,
DFN1412-6

DSN0603-2,
DSN1006-2,
DSN1006U-2,
DSN1608-2

SOD80CSOD27,
SOD68

Figure 91 | Categorized overview of Nexperia diode package portfolio.

In the following chapters, package families are presented with their individual
benefits in the applications.

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Diode Application Handbook

5.1 Through-hole packages
From the beginning of the mass production of electronics in the 1950s until theearly 1980s through-hole was the standard technology for board mounting. But
from the 1980s until today, through-hole has been widely replaced by surfacemount technology (SMT) which opened the way to higher integration andminiaturization. Another reason for the phase-out of through-hole packages was
the increasing operating frequencies of electronic applications which made theusage of these packages with their high parasitic inductances – caused by the longleads – undesirable.

5
Diode packaging

Diode packaging

5

But through-hole packages still have advantages in certain circumstances, e.g.
• if large components are required.
• if the space directly on the board is used for surface-mounted devices(SMD) and the through-hole component with its long wires can be placedon a ‘second floor’.
• if very tough mechanical stresses and strains need to be considered (e.g.
for connectors).
• in special application areas such as power MOSFETs and IGBTs.
• if very simple electronic applications can be realized very cost efficiently
by using through-hole technology.
The usual soldering technique for through-hole components is wave soldering. But
it is also possible to mount these products using today’s common reflow solderlines. Please refer to 4.4 for explanation of different soldering techniques.

5.2 Packages for surface-mounted devices
The introduction of surface-mounted devices in the 1980s into mass production
opened the way for the cost-efficient production of ever-more complex electronic
applications thanks to the rapid increase of the component density on a PCB. Thiswas enabled by significant and frequent miniaturization steps at component andboard level. For the PCBs this meant the steady reduction of the linewidth of theprinted-circuit tracks resulting in a massive increase in the line density, and thesteady increase in the number of layers in the PCB. Furthermore, the introductionof SMD products opened the way to use both sides of the PCB for mounting
devices.

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nexperia | Design Engineer’s Guide

Development of surface-mount technology started in the 1960s. For Nexperia, theera of surface-mounted devices began with the introduction of the famous SOT23
package in 1969 which is still a high-runner in the market.

5.2.1 Wire-bonded leaded packages
Nexperia offers a large variety of wire-bonded leaded-packages. These packages
are the correct choice for standard application requirements, i.e. if there are no
increased requirements for power, heat dissipation, parasitic inductance or
capacitance.
In this package family we find the oldest and most common SMD packages in thediscrete semiconductor industry, which still represent the largest volume in themarket by number of products sold.
All packages of this category (see Figure 92) are suitable for wave soldering andreflow soldering. The quality of the soldering process can be easily monitored byautomated optical inspection (AOI). These packages are qualified for automotive
use according to AEC-Q101.

SOD1232.68 × 1.6 × 1.15

SOD123F
2.6 × 1.6 × 1.1

SOD323
1.7 × 1.25 × 0.95

SOD323F
1.7 × 1.25 × 0.7

SOD523
1.2 × 0.8 × 0.6

5

Diode Application Handbook

5.2.2 Clip Flat Power (CFP) packages
The CFP-package has been designed for increased requirements in terms of power.
The clip bonding which is used in these packages reduces the on-resistance of the
product due to enlarged contact areas compared to single wire bonds. Parasitic
inductance is reduced thanks to the elimination of the wire bonds. Furthermore,
the architecture of the clip bonded packages improves the heat dissipation
significantly, making them the preferred choice for power applications.

Diode packaging

Diode packaging

5

CFP packages used for Nexperia’s diodes (see Figure 93) are all qualified forautomotive use according to AEC-Q101 and suitable for wave soldering and reflow
soldering.
Due to the high requirements concerning power (temperature) and heatdissipation, clip-bonded packages today (in 2021) still use solder alloys with highlead content for internal package soldering. These solder alloys are used for theirunique properties, such as high melting points and high thermal conductivity which
ensures the performance and reliability of these packages. Nexperia and othersemiconductor manufacturers are working on potential lead-free solutions toreplace these alloys to support environmental initiatives.

CFP2-HP
2.2 × 1.3 × 0.68

CFP3-HP
2.6 × 1.6 × 1.1

CFP3
2.6 × 1.7 × 1

CFP5
3.8 × 2.6 × 1

CFP15B
5.8 × 4.3 × 0.95

Figure 93 | Table of Nexperia diode CFP packages with outline and dimensions in mm.

SOT143B
2.9 × 1.3 × 1

SOT223
6.5 × 3.5 × 1.65

SOT23
2.9 × 1.3 × 1

SOT3232 × 1.25 × 0.95

SOT353
2.1 × 1.25 × 0.95

SOT363
2.1 × 1.25 × 0.95

SOT457
2.9 × 1.5 × 1

SOT663
1.6 × 1.2 × 0.55

SOT666
1.6 × 1.2 × 0.55

SOT89
4.5 × 2.5 × 1.5

Figure 92 | Table of Nexperia diode leaded-packages with outline and dimensions in mm.

132

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nexperia | Design Engineer’s Guide

5.3.2 Chip Scale Packages (CSP)

5.3 Leadless packages
5.3.1 Leadframe-based Dual-Flat-No-Leads packages (DFN)DFN packages are the next significant step in miniaturization. They also offer
improved performance in terms of parasitic inductance and capacitance due toshorter wire bonds and no leads. They also show an improved thermal performanceby providing one contact pad – or even a large exposed die pad – for direct heattransfer from the silicon to the PCB. The footprints of DFN packages also simplify
PCB trace routing.
For a growing part of Nexperia’s DFN package portfolio we offer alternative padarchitectures with side wettable flanks. These pads are not completely terminatedon the bottom side of the product but offer a solderable area on the side wall of
the device. This means that after successful reflow soldering, a solder meniscus isvisible at the side wall of the device pad. This meniscus can easily be detected using
AOI equipment which makes these packages the preferred choice for applications
which require extremely high reliability.
The DFN packages for Nexperia’s diodes (see Figure 94) are all qualified forautomotive use according to AEC-Q101 and suitable for reflow soldering.

DFN1006-2
1 × 0.6 × 0.5

DFN1006-3
1 × 0.6 × 0.48

DFN1006BD-2
1 × 0.6 × 0.48

5

Diode Application Handbook

DFN1006D-2
1 × 0.6 × 0.4

DFN1010D-3
1.1 × 1 × 0.37

Nexperia’s chip scale packages facilitate electrical functionality on the smallest
possible PCB area. The length and height dimensions of the product are thedimensions of the silicon die itself, as the product is basically a naked die withplated contact pads underneath to enable the solder contact to the PCB. Besides
minimizing the footprint area, this architecture delivers the lowest values forparasitic inductance and capacitance. This package architecture is called DSN(Discrete Silicon No lead) at Nexperia. Compared to plastic packages, DSN packages
require smaller pads and less solder paste to be applied to the PCB for the reflow
process. Please take note of the package-related application notes for DSN reflow
soldering and footprint recommendations at nexperia.com.

Diode packaging

Diode packaging

5

Strongly related to the naked silicon DSN packages are overmolded derivatives
offered by Nexperia. These packages are completely encapsulated in a thin layer ofmold compound and are listed as DFN packages in the Nexperia package catalog(see Figure 95). But due to the very thin overmolding, these packages are also truechip scale packages as the area ratio between the final product and theencapsulated silicon die is only just below 1.
All chip scale packages can only be mounted using reflow soldering.

DSN0603-2
0.6 × 0.3 × 0.3

DSN1006-2
1 × 0.6 × 0.27

DSN1006U-2
1 × 0.6 × 0.27

DSN1608-2
1.6 × 0.8 × 0.29

Figure 95 | Table of Nexperia diode CSP packages with small sketch and dimensions in mm.

DFN1110D-3
1.1 × 1 × 0.48

DFN1412-6
1.4 × 1.2 × 0.47

DFN1412D-3
1.4 × 1.2 × 0.47

DFN1608D
1.6 × 0.8 × 0.37

DFN2020-3
2 × 2 × 0.65

DFN2020D-3
2 × 2 × 0.65

Figure 94 | Table of Nexperia diode DFN packages with outline and dimensions in mm.

134

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5.4 Soldering techniques
5.4.1 Wave soldering
Wave soldering is the oldest way of mass soldering devices onto PCBs. Wave
soldering was introduced when the boards were single-sided and devices used
packages with Through-Hole-Technology (THT). The packages had pins or wires
which penetrated plated holes in the PCB, and were wave-soldered on theunderside of the PCB.
The next evolutionary step was the double-sided PCB with circuitry on both sides ofthe board. This technology provided enabled SMD packages to be placed on thesolder site of the PCB and fixed with glue underneath the package body. These
SMD packages and the through-hole packages were then fluxed and soldered usinga wave-soldering process.
With advancing miniaturization in PCB and package technology, wave soldering has
increasingly been replaced by new soldering techniques, namely reflow soldering. If
wave soldering is still required or has its benefits – e.g., for mechanical reasons forconnectors or large capacitors – selective wave soldering technologies have beendeveloped which allow the application of a solder wave on very small areas
measuring just few square millimeters.

Diode Application Handbook

After solder paste print and device placement, the PCB – with the devices sticking
in the solder paste – is driven at a defined speed through the heating zones of a
reflow oven. The result of these defined conditions is a temperature-over-time
profile which each individual device experiences. For a successful reflow process
this temperature profile needs to fulfill certain criteria:• limits in the rate of heat-up and cool down steps• limits for the time period above liquidus temperature5
Diode packaging

Diode packaging

5

The temperature profile depends on many parameters, including the number of
PCB layers, the copper density on the PCB, the device size, and its thermal mass toname just a few. It is obvious that the temperature profile will not be the sameacross the whole board – there will be local differences. Hence, it is important to
see that the solder reflow process must be optimized for each individual PCB
layout. The semiconductor manufacturer can only specify the range of what thetemperature profile should look like for an individual IC or discrete device. The
definition of the reflow process is the task of the board manufacturer.

5.4.2 Reflow solderingWith ever-continuing miniaturization, the need for higher and higher pin counts for
ICs and the accompanying introduction of new package architectures (e.g., QFN,
BGA, chip scale package etc.), wave soldering technology was replaced by reflow
soldering which today is the most common way to mass solder devices on PCBs.
The fact that modern package architectures use the area underneath the package
body for solder contacts means that wave soldering is not an option anymore.
Furthermore, the pitch sizes between the contacts have often been reduced to alevel which makes reflow soldering a necessity.
Solder paste is printed into the PCB through a mask (stencil). For very advanced
requirements or prototyping there are also tools available for direct solder paste
printing (dispenser) – comparable to ink jet printers. Solder paste is a suspension offlux and solder powder. It forms the solder joint between PCB pad and device pad
after the reflow, and fixes the device after the pick and place process on the PCB
before the reflow. If required, a dot of glue underneath the device can be appliedon the PCB to support adhesion. The classification of the solder paste (determinedby parameters like viscosity and particle size of the solder powder) needs to fit to
the PCB and stencil characteristics (minimum pad/hole sizes, stencil thickness etc.).

136

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6

Diode Application Handbook

Chapter 6
Reliability aspects

Reliability aspects

Diode packaging

5139

nexperia | Design Engineer’s GuideAs Nexperia we follow our ZERO quality policy:

6

Diode Application Handbook

6.1 Probability of failure

Z ZERO customer incidents is our ambition
E EVERYONE is responsible for quality
R RECOGNIZED leadership in quality
O OBSESSION for consistent quality
To achieve our ambitions, reliability testing is one of the major considerations
during the qualification of our products as well as when monitoring production.
Reliability testing can guarantee that products will perform according to their
specifications over the specified lifetimes of the electronic applications.

Figure 96 shows three different types of failure rates. Early failure rate (EFR),
intrinsic failure rate (IFR) and the wear-out period.
The two important periods for the product reliability assessment are Early Failure
Rate (EFR) and Intrinsic Failure Rate (IFR). EFR is a declining failure rate. These are
failures due to weak products with macroscopic defects. The flat portion of the
failure rate curve (IFR) consists of random failures and the failure rate is relatively
constant. This is the behavior observed in large populations of mature parts and iscommonly referred to as the useful life of the product.

Reliability aspects

Reliability aspects

6

Wear-out is generally not a concern for well-developed semiconductor
technologies.

• Fundamental wear-out mechanism of part (silicon or package)• Drift in a device parameter• Latent manufacturing defects• Manufacturing process excursions
Reliability qualification can address only some of these causes of field failures.

aaa-034629

The parts can fail in the field for a variety of generic reasons:

IFR (Intrinsic Failure Rate)
Random failures at low, constant failure rate

Failure
rate
λ

EFR

Useful life period

Since reliability qualification is a one-time event, it normally does not address issues
such as manufacturing process excursions or ‘maverick lots’ (maverick lot is an
outlier lot which is still within specifications).

Wearout
periodReliability qualification mainly focuses on:• Detecting fundamental wear-out mechanisms• Detecting design marginality combined with parameter drift• Determining failure rates due to latent manufacturing defects

140

0

λ

Time

Figure 96: Plot of typical failure rate over time, commonly known as ‘bathtub-curve’.

141nexperia | Design Engineer’s Guide

6.2 Reliability tests & failure modes
To check the product reliability before a general release to production, several
tests are necessary which focus on a calculated accelerated aging of different partsof the product (die, package & interconnections). Acceleration usually consists ofhigh temperature or a high applied voltage.
We can categorize these tests in different chapters:• Manufacture• Operation• Thermo-Mechanical• Standby/Storage

Reliability tests – operation
Table 25: Reliability tests for investigation of failure modes
caused during operation.
Test

Explanation

Conditions

HTRB

High Temperature Reverse Bias

Oven @ 150°C
1000h
max. reverse bias

Acceleration: Peck model,
Temp, V_bias
HTOLHigh Temperature Operating Life
Acceleration: Peck model,
Temp, V_bias

Reliability tests – manufacturing & design

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Reliability aspects

Reliability aspects

6

Oven @ 150°C
1000h
max forward bias

Potential failure modes:

Table 24: Reliability tests for investigation of failure modes
caused by manufacturing and design.
Test

Explanation

Conditions

Preconditioning

Simulate temperature + humidity
prior to reflow solder (defines the
moisture sensitivity level (MSL))

24h bake 125°C, 168h H3TRB, 3x
reflow

Solderability

Test proper lead finish (tin) toensure high speed soldering

immerse for 5s in Pb-free solder
bath, device may be pre-aged by
8h steam or 16h dry bake

Solder Heat

Test ability to withstandimmersion during wave soldering

Immerse in Pb-free solder bathfor 30s

Potential failure modes:

Figure 98 | Potential failure modes during device operation: crystal defects (left),incomplete trench (center) and lifted bond due to intermetallic corrosion.

Reliability tests – thermo-mechanical
Table 26: Reliability tests for investigation of failure modes
caused by thermo-mechanical stress.
Test

Explanation

Conditions

TC

Temperature Cycling

dual climate chamber @up to −65°C, +150°C
device swaps every 20min, 1000cyc

Acceleration: Coffin-Manson, dT
IOL

Figure 97 | Potential failure modes might be caused by manufacturing: broken wedge (left),package crack.

142

TS

Intermittent Operational Life
Acceleration: Coffin-Manson, dT

electr. test rack, device powered on/
off every 2 min,min. temp swing: 100°C (due to Ptot
during t_on); 15kcyc

Temperature Shocklike TC but with liquid baths

dual climate chamber @up to −65°C, +150°C

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Potential failure modes:

Potential failure modes:

6
Reliability aspects

Reliability aspects

6

Figure 99 | Potential failure modes caused by thermo-mechanical stress: intermetallic corrosion,cracks in silicon caused by wire bonding, cracks in bond line, cracks in passivation layer, broken
stitch, lifted bond wire.

Reliability tests – standby/storage

Figure 100 | Potential failure modes caused by exposure to humidity and harsh environment:
corrosion (top pictures), lifted bond wire, moisture penetration into package.

Table 27: Reliability tests for investigation of failure modes
caused by exposure to harsh environment.

During qualification, Nexperia never runs all these listed tests, as some of themcover each other with higher stress levels or extended test duration.

Test

Explanation

Conditions

H3TRB

High Humidity/High Temperature
Reverse Bias

climate chamber,
1000h, 85°C, 85%RH, biased
at 80% of rated breakdown voltage

Acceleration: Peck model, Temp,%RH, V_bias
AC

Autoclave
Acceleration: Peck model, Temp, %RH

UHAST

Highly Accelerated Stress Test
Acceleration: Peck model, Temp,%RH, unbiased

HAST

Highly Accelerated Stress Test
Acceleration: Peck model, Temp,%RH, V_bias

144

pressured steam chamber
96h, 121°C, 100%rH, 1bar

During the setup of Nexperia’s qualification strategy, and in parallel to this test
selection for a new product family, our company would also consider a structuralsimilarity approach which allows it to perform reliability tests on specific products
from the new product family (e.g., smallest and biggest die within a certain family
from the same wafer process).
For reliability testing we follow Nexperia’s Reliability Qualification Specification as
well as the related JEDEC standards for the different tests.

pressured steam chamber
96h, 130°C, 85%rH, 1.5bar

pressured steam chamber
96h, 130°C, 85%rH, 1.5bar, biased at
80% of rated voltage

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6.3 Automotive-grade qualification

6.5 Nexperia’s high robustness specification

Besides our large consumer/industrial grade qualified portfolio Nexperia has
released most of its parts with AEC-Q101 certification, the official automotive
qualification guideline.

Nexperia’s aim is to produce high-quality products. Therefore, we define our High
Robustness Specification accordingly. This document describes the qualification
requirements for products to be released as ‘High Robustness Products’ – products
which are used in extreme automotive customer applications such as Engine
Control Units or gear boxes.

The difference between the reliability tests for consumer/industrial andautomotive products is the test duration (e.g., 500 cycles vs. 1000 cycles TC) which
results in a guarantee of longer product lifetime.

6.4 Mission Profiles
A product’s intended application area is characterized by a Mission Profile (MP),which is a collection of relevant environmental and functional loads that a productwill be exposed to during its full life cycle.
Nexperia uses the following generic Mission Profiles:• Automotive for Discrete devices, according AEC-Q101• Automotive, Grade 1 for ICs, according AEC-Q100• Non-automotive, based on Home Mission Profile from Legacy NXP and on
JESD47• Non-automotive, based on Industrial Mission Profile Legacy NXP and on
JESD47• Non-automotive, based on Infrastructure Mission Profile Legacy NXP andon JESD47
If the customer mission profile deviates from the Generic Mission Profiles, Nexperia
is happy to work closely with the customer, to calculate and align on the test
conditions and duration to meet the customer’s expectations.

On top of AEC-Q101 we add some very ambitious tests:
2x AEC-Q101:
The test time of all reliability tests
according to AEC-Q101 or -Q100(whichever is applicable) must be
extended by the factor of 2.
Zero delamination:
The products must not show any sign ofdelamination of the mold compoundfrom any other component of thedevice (e.g., leadframe, clip, wire, die)after pre-conditioning according to
MSL 1.
PCB bending test:
The products must withstand at least
1.0mm of PCB bending according toIEC-60068-2-21. In addition, themaximum possible bending deflection
before the parts fail electrically must be
determined.
Vibration test:
A vibration test in accordance with
IEC60068-2, 64 using the specified
conditions must be passed.

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Reliability aspects

Reliability aspects

6

Drop test:
A drop test using the following
conditions must be performed: pulse
width (measured at 10% of amplitude):
0.5ms +/-30%, Cpk>1.33, acc. peak
1500g +/-20%, Cpk>1.33 (see picture).
The samples are monitored electricallythroughout the test. The number ofsamples to be tested are 135 per(leader-)type, distributed on 9 test
boards.
Power thermal cycling:
The PTC test is a combination of TC and
IOL which leads to a high stress at theinterconnection between PCB and
Product. 2600 PTC test cycles are
required.
• TCT condition: −40°C to 105°C,
90min/cycle• IOL condition: Seven powered
component cycles (5 minutes on, 5
minutes off) with a temperature riseof 30K ± 2K between solder joint of
the component on the PCB and analuminum base plate attached to the
PCB are required.

147

150
component solder joint
heatsink reference
climate chamber

ΔT: 30K
110

70

30

−10

PTC cycle time 90 min

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Chapter 7
Diode applications
and use cases

Diode applications and use cases

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Temperature (°C)

Reliability aspects

6

−50
0

40

80

120

160

Test time (min)Figure 101 | Power temperature cycling. Power temperature cycling is a very specific test
combining TC and IOL which leads to a high stress at the interconnection (solder joints) between
PCB and Product.

For any questions about Nexperia’s qualification strategy don’t hesitate to get intouch with us.

148

149

After changing the battery, or during maintenance, the battery leads may bereconnected in the opposite polarity. Wrong polarity of the battery can potentiallylead to fatal errors in the electronic units of a vehicle. Therefore, a measure isnecessary to protect the sensitive electronic system from reverse battery
protection.
Using a diode in series in the supply line can be considered as the simplest and mostcost-efficient way to realize a reverse battery protection circuit, as shown in
Figure 102.

Vbat+

Figure 102 | Reverse battery protection byusing a diode in series in the supply line.

Load

Vbat−

Load dump
Load dump describes the condition that occurs when the alternator is charging thebattery and the connection to the battery is suddenly lost while other loads remain
connected. ISO 16750-2 and ISO 7637-2 (Figure 103) specify automotive load dump
transients for 12V & 24V systems. According to these standards, the surgetransients can last up to 400ms. Normally the reverse protection diode is precededby a TVS diode which clamps the voltage level of the transient. Nevertheless, thevoltage transient can cause a high peak current through the internal resistance of
the alternator and the dynamic resistance of the diode. Therefore it is necessary tochoose diodes with a high surge current capability for reverse battery protection.
Keep in mind that the surge current capability of the diode is specified through the
IFSM parameter which is usually defined for rectangular and sinusoidal pulse forms
for a pulse width in the range of 8ms, while a load dump peak current can last up to
400ms,– much longer. The choice of the reverse polarity protection diode must be
decided on a case-by-case basis, considering the pulse duration, the selected TVS
diode and the internal resistance of the alternator. However, it can be generally
recommended to use a diode in a clip-bonded package, such as the Clip-bonded
Flatpower (CFP) package family from Nexperia, as such products come with asignificantly larger surge current capability thanks to the use of a solid copper clip.

The steady state conduction losses Ploss can be easily calculated by taking into
account the forward voltage drop Vf of the diode at a given temperature and theload current Iload:

Ploss = Iload × Vf (T)It is obvious from this equation that a diode for reverse polarity protection is usefulfor relatively small load currents only, otherwise the power dissipation increases
too much, adversely affecting the efficiency of the system. In practice, therefore,
diodes are used as reverse polarity protection for load currents up to
approximately 2–3A.
Apart from the power dissipation that the diode must be able to dissipate in thegiven package, there are other aspects that must be taken into account. These are
discussed below.

150

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7

U
td
tr
US
0.9 (US - UA) + UA

0.1 (US - UA) + UAUA
0t

Board net

Us (V)Ri (Ω)

id (ms)tr (ms)12V

65 to 87

0.5 to 4

40 to 400

10 +0/-5

24V

123 to 174

1 to 8100 to 350

10 +0/-5

151

td
tr
US
0.9 (US - UA) + UA

US*
0.1 (US - UA) + UAUA
0t

Board net

Us (V)Us* (V)Ria (Ω)td (ms)T3 (ms)12V

79 to 10135

0.5 to 4

40 to 400

5 to 1024V

151 to 202

Not specified

1 to 8100 to 350

5 to 10

Battery disconnection from an inductive load
ISO 7637-2 also describes what happens when the connection to the battery isinterrupted while an inductive load is applied in parallel with other loads. The
inductive load will generate a negative voltage across the loads. This condition istested according the test pulse shown in Figure 104.
As shown in the table, the reverse peak voltage applied to the anode of the diodecan be up to −100V for a 12V board net. The diode must be designed in such a waythat the dissipated power in the reverse direction on the time scale of the pulse
does not exceed the specified avalanche energy of the diode. Another important
point to consider is the leakage current of the diode. Especially at high ambient
temperatures, the diode will carry a leakage current that can stress the sensitive
load. Therefore some designers use recovery rectifiers instead of Schottky diodes
in order to control the leakage current. However, due to the pn junction, recovery
rectifiers have a high forward voltage drop, compromising the efficiency of thereverse polartiy circuit. This is where SiGe diodes can help. This new hybrid
technology combines the advantages of Schottky diodes with the low leakage
current of recovery rectifiers. Please refer to chapter 1 for more details.

V

t2
t3

Figure 103 | Test pulses for characterizing the load dump transients.
Left: unsuppressed transient, right: suppressed transient.

UA
0

Diode applications and use cases

U

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7

0.1 USt

US
0.9 US
tr
td
t1

Board
net

Ua
(V)

Us
(V)

Ri
(Ω)

td
(ms)

tr
(µs)

t1
(s)

t2
(ms)

t3
(us)

12V

13.5 ± 0.5−75 to −150

102

0.5 to 1

> 0.5

200

< 100

24V

27 ± 0.5−300 to −600

50

1

1.5 to 3

> 0.5

200

< 100

Figure 104 | Test pulse for characterizing transients caused by
the disconnection of batterie from an inductive load.

152

153

7.2 Zener applications
Zener diodes are often used togenerate a stabilized voltage. In
Figure 105 a Zener diode ZD1 isconnected to a voltage source via aseries resistor. The load resistor RLOAD isconnected in parallel to the Zener
diode. This load could also be asophisticated electronic circuit requiringa stable supply voltage.

R1
VOUT

Vin

ZD1

RLOAD

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Diode Application Handbook

The basic voltage stabilizer circuit shown in Figure 105 is used for low power
requirements. For load circuits with a higher power requirement, it is not efficientthat the full current through R1 heats up the Zener diode when the load is turnedoff, or that so much heat is generated if load current consumption drops duringuse. The circuit in Figure 106 improves this significantly. The Zener diode ZD1 isdriven in breakdown via R1. The base of the bipolar transistor Q1 is connected tothe stabilized voltage across ZD1. The output voltage at RLOAD is determinedaccording to the equation: VOUT = VZ − VBE.
Power dissipation in the Zener diode is almost independent from the load current if
it is assumed that the base current is only a small part of the current through R1.
For output voltages of about 5V, the circuit has quite a good thermal stability
because the thermal coefficient of the Zener voltage of about −2.0mV/K iscompensated for by a decrease of VBE with a very similar coefficient.

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7

ZD1

VOUT

Figure 106 | Voltage Stabilizer with a bipolartransistor and Zener diode voltage reference.

PR1 =(V IN − V Z )2
R1

The Zener diode has maximum power dissipation if no load is connected. In thiscase, all the current via R1 flows through the diode:

PZD1 = VZ × IZ = VZ ×

154

VIN − VZ
R1

VOUT

ZD1

Q1

Vin

VIN − VZ
IZ(min) + I LOAD(max)The power dissipated in R1 is:

Q1
R1

R1

RLOAD

R1 =

Vin

aaa-033934

The value of series resistor R1 has to be chosen such that residual current flows
through the Zener diode also for the highest load current that may be expected.
The minimum current through the Zener diode should ensure that the diodeoperates in the steep region of reverse conduction. The current used for themeasurement of VZ in the datasheet is a good guide, this means about 5mA forvalues of VZ up to 17V and 2mA for Zener diodes with high Zener voltages.

aaa-033933

Figure 105 | Voltage Stabilizer with a
Zener diode.

R2

S1

Figure 107 | Load switch with P-Channel FET
and Zener diode for gate voltage clamping.

Another important application for Zener diodes is the clamping of undesired
over-voltages. In Figure 107 a simple load switch is depicted. The gate oxide of
MOSFETs is sensitive to over-voltages. Internal ESD diodes of FETs should not be
used for clamping in an application because the gate-source voltage VGS is above
datasheet limits in this case. The breakdown voltage of the ESD diode is higher than
the specified VGS-rating. In the application example a P-channel FET switches theload current. The FET turns on once the gate has a negative voltage versus thesource. If switch S1 is turned on, the voltage divider of R2 and R1 with ZD1 inparallel define the gate voltage to be higher than VGS(th). The voltage at the gate islimited by ZD1 to a level which is within the VGS rating of the FET with some safetymargin. The gate voltage can be adjusted by a resistor divider without a Zener
diode. However, in this case, the circuit is not safe if VIN sees over-voltage events.

155

Zener diodes can be used for all kind of
applications where voltage levels haveto be clamped or kept below a limit.
Figure 109 shows a level limiter for an
AC source. For a sine wave source themaxima and minima are symmetricallyclipped to VZ + VF.

156

+V

R1

Figure 110 is a SPICE simulation result of a 1kHz sine wave voltage source supplied
through a 220 ohm resistance to two Zener diodes with a VZ of 5.6V. The two Zener
diodes are connected in series with their anodes connected (as shown in
Figure 109). It can be seen that the clipping levels are about 0.6V higher than VZ, as
can be expected. Using a similar approach, Zener diodes are often implemented for
ESD and surge pulse protection of signal lines. With the voltage clipping function
they prevent excessive over-voltages that could endanger and damage electronic
circuits.

L1

ZD1

aaa-033938

D1
VOUT

Figure 108 is another solution forprotecting a MOSFET. The FET Q1 isswitching an inductive load. The
inductance has no free-wheeling diode.
Once the switch turns off, the current
continues to flow. L1 creates a voltage
which is high enough to break throughthe drain-source path of the FET.
However, with the Zener diode applied
between the drain and gate of the FET,the FET can switch on again slightly sothat the VDS rating is not exceeded. The
FET runs in linear mode for a shortduration and the energy stored in the
inductor is dissipated in the FET in acomparably short time. Compared to asimple free-wheeling diode parallel to
L1, a higher voltage loss across thedrain-source path leads to higher power
and faster decay of the stored energy inthe inductor.

aaa-033935

The resistor R1 has to be applied for discharge of the gate once the load switch isturned off. S1 is usually realized using an N-channel control FET or a BJT.

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Diode Application Handbook

8
6

R2

Q1

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4
20

Figure 108 | Protection of a switch for an
inductive load with a Zener diode.

VOUT

R1

−2

aaa-033936

Diode applications and use cases

7

ZD1

−4
−6
−8
0

1

2

3

4

AC

5

6

time (ms)ZD2
Figure 110 | Symmetrical clipping of 1 kHz sine wave with BZT52H-B5V6.

Figure 109 | Example for level clipping of AC
voltage by Zener diodes.

Zener diodes are often used as voltage references. Figure 109 shows an example
where an op-amp is used as a non-inverting buffer to provide the reference voltage
created by the Zener diode ZD1 as an output voltage with low impedance for theconnected electronic loads. The current through the Zener diode can be chosen tobe small compared to the circuit shown in Figure 105. In order to support suchapplications with a narrow spread of VZ at low Zener currents, dedicated low
current Zener diode families are offered. Instead of the 5mA current rating used
for standard Zener diodes, these components are rated for 50µA. If standard Zener
diodes are used for low current applications, the parts should be tested upfront, inorder that clamping works as desired.

157

Figure 111
Zener diode as voltage
reference with an
Op-Amp buffer.

+V

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Diode Application Handbook

7.3 ORing applications

IC1

ZD1

-

VOUT

aaa-034632

R1

+
12V
Battery

R2

BackupBattery

SystemLoad

R3

Figure 113 | Diagram of a system with two power sources for increased safety through supply
redundancy. The main power source and the backup battery are isolated from each other by two
ORing diodes.

Irrespective of the chosen supplier, it can happen that at certain special Zener
voltages the avalanche effect can be observed with some delay. Therefore, noise as
shown in Figure 112 can occur for a very small current IZ. If the Zener diode crystals
are doped with gold or platinum, these impurities can deliver the necessary carriers
for avalanche breakdown at low bias currents. This ensures that an avalanche
breakdown happens safely and accurately, even with low avalanche currents.

aaa-033939

As an experiment to check the reliable operation of Zener diodes at low currents, ahigh impedance, say 1MΩ, can be put in series with the Zener. A low current
created by a current source is pushed through the diode while VZ is tested using anoscilloscope. Figure 112 shows the example of such undesired behavior.

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Diode applications and use cases

7

In systems that have to meet high safety requirements, a power architecture withredundancy is mandatory. An example of this is the emergency call system in a car.
In such a case, at least two power supplies are connected to the load. There is amain power supply and a back-up battery as shown in Figure 113. Diodes are used
to isolate the two power supplies from each other. Very similar to the case ofreverse polarity protection, diodes are a simple and cost-efficient solution for
power supply redundancy applications. However, due to the relatively high power
losses in the diode, diodes are only suitable for small currents. In order to keepthese losses low, Schottky diodes usually preferred, since they have a smaller
forward voltage drop compared to diodes with a pn junction. Another requirement
is a low reverse leakage current, even at high ambient temperatures. The reason
for this requirement is because the two power supplies don’t necessarily have thesame voltage levels, which means that one diode will be biased in reverse. The
leakage current of the diode would then by fed into the back-up battery which
could potentially cause damage to the battery.
Here, again, the IR/VF trade-off of diodes comes into play. Nexperia offers a whole
range of Schottky diodes with low reverse leakage current in different packages. Ifvery low reverse leakage currents at high ambient temperatures are required, SiGe
diodes can also be used here, as they exhibit relatively low forward voltage drops
despite their extremely low reverse leakage current.

Figure 112 | VZ of a 75V Zener diode with IZ = 30µA supplied via a 1MW impedance,
showing unstable avalanche events.

158

159

7.4 Switching diodeSwitching diodes can be found in nearly every electronic application. In this section,some examples are discussed that can be found in many applications.
Switching diodes can be used in extremely low cost solutions for simple, slowspeed logic functions as depicted in Figure 114. The control signals S1 and S2 areconnected via two diodes to a resistor R1. Once at least one signal has a positive
voltage level significantly above VF, a current will flow through R1. If we see thesimple circuit as a logic function, an OR-gate is created. There is a positive voltage
at R1 if one input signal, S1 or S2, or both, get a positive input voltage. The circuit
can be extended easily to connect more control signals in this way by adding more
diodes.
The diodes decouple the input signals from each other. If one signal shows alogic-high state, no current will flow back into the other signals with a logic-low
state. If this circuit is connected to a switching stage, such as a BJT or FET, many
types of actuators and loads can be controlled. These can work with different
voltages than the input signals S1 and S2.

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Diode Application Handbook

If the switching diodes are connected in reverse compared to Figure 114, i.e. with
common anodes at the node Sout as shown in Figure 116, the voltage at R1 is VF,
once at least one input has ground level. If all inputs provide a logic-high state, thevoltage of the signal Sout will also provide a logic high state. The circuit discussed
provides an AND function. Again, it can be expanded for a higher number of inputs
by adding more diodes. Adding a FET with a threshold voltage above VF provides
the option to switch various loads, and the drain signal has a clean low level if theapproach is used as NAND function. Signal Sout in Figure 117 can then be used as
proper control signal for further circuitry.
The AND function is often used if
several control signals have to bepresent with a positive voltage, all at
the same time. There may be several
switches safeguarding the propercondition of a system – for example, alldoors closed – and some supply
voltages may be mandatory to enable afurther operation.

D1

R1

DC

S1

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SOUT

D2
S2

Figure 116 | Diodes AND function.
aaa-034636

Figure 115 depicts such a situation. Q1 switches a load resistor Rload. The load
supply voltage can be chosen without constraints if a suitable FET is selected. The
voltage at the drain pin can be seen as the inverted signal of the voltage at R1. The
OR-gate created by the diodes is followed by an inverter, so a NOR-gate has been
built.

aaa-034633

aaa-034634

RLOAD

D1
S1

D1
S1

S2

D2
S2

160

DC

SOUT
D2

DC

R1

Figure 114 | Diodes used for a logic-OR
function.

Q1

SOUT
Q1

S1

RLOAD
D2

R1
D1

S2
R1

Figure 115 | Diode’s OR function extended
with FET switch added.

Figure 117 | Diodes AND function with FET switch added

161

VCC

Figure 118 | Switching diodes
applied as input protection.

S1

The capacitors must be specified with a capacitance that is high enough to achievea maximum ripple voltage target on VOUT. The values depend on switchingfrequency and maximum load current.
Figure 119
Voltage inverter withcharge pump approach.

C1

D1

VOUT

Osc.
D1

C2

Diode applications and use cases

Diode applications and use cases

Switching diodes are often used for voltage clamping in a rail-to-rail approach.
Figure 118 depicts this solution. If a negative voltage surge pulse against groundlevel enters the system, the low side diode becomes conductive and clamps thevoltage of signal S1 to −VF. For positive surge events, the upper diode starts to
conduct once the voltage exceeds VCC + VF. Usually, big capacitors are connected tothe supply line, called VCC in the example, and the impedance of the line is often
quite low, with many loads connected. Therefore, voltage VCC will not increasemuch as a result of an ESD strike which does not have high energy. If higher energy
pulses and long duration over-voltage pulses can be expected, a Zener or TVS diodecan be added in reverse direction to the supply. In Figure 118 the TVS diode isshown connected with dashed lines, and the over-voltage is limited to VBR + VF. VBR
is the breakdown voltage of the Zener diode and VF is the forward voltage drop of
the upper switching diode in Figure 118.

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Figure 120 depicts a charge pump circuit which can double the supply voltage.
There is a DC supply V1 and an oscillator that is assumed to toggle between groundlevel and a positive voltage V1. If the oscillator outputs ground level, C1 is charged
to V1-VF. C2 also gets charged to V1 − 2 × VF. Once the oscillator toggles to the
output voltage V1, the negative pole of the charged C1 is moved up by V1, so
charge can flow from C1 into C2 increasing the output voltage.
For VOUT there is the equation: VOUT = 2 × V1 − 4 × VF.
The circuit for voltage doubling can be extended with additional stages, so that an
input voltage can be multiplied by a factor N, assuming we neglect the forward
voltage losses of the diodes.
Figure 120
Voltage doubling circuitwith charge pumpapproach.

aaa-034639

Charge pumps, created with capacitors for energy storage and diodes as switchingelements, are another application example for switching diodes. In applications
with operational amplifiers, a negative supply voltage is very often required inorder to use the ground as reference for the amplifier, rather than a resistor divider
in a single supply design. Figure 119 shows a voltage inverter. The oscillator toggles
between GND level and a voltage V1. If the output of the oscillator outputs the
positive voltage V1, C1 gets charged to V1-VF via D1. The positive pole of thecharged capacitor is then connected to ground once the voltage source switches to
GND. By this switching event there is now a negative voltage against ground at theminus pole of the capacitor. Diode D1 is reverse-biased and does not conduct. D2,
however, is biased in the positive direction, so C2 gets charged with a negative
voltage against GND. With the next oscillator cycle, D2 blocks a discharge of C2 andC1 gets recharged via D1. VOUT is the inverted positive voltage from the oscillator,
reduced by the forward voltage losses of the two diodes, so VOUT = V1 – 2 × VF.

C1

Osc.
D1

V1

D2

VOUT

C2

.

162

163

D1

AC

VOUT

R1

Figure 121 | Peak voltage detector,
AM-demodulator.

7.5 Bootstrap diode
Another typical application of switching diodes can be found in the bootstrap
circuit, a common way to supply the high-side gate driver in half-bridge circuits. The
bootstrap circuit as depicted in Figure 123 is comprised of the bootstrap diode
Dboot for voltage blocking, a current limiting resistor Rboot and the capacitance
Cboot for energy storage. It is a low-cost alternative to isolated supplies for bothlow- and high-voltage applications. While some integrated circuits for half-bridge
applications already include an integrated diode, a discrete component solution canbe used for virtually any half-bridge design, leaving the circuit designer with amaximum degree of freedom.

+VDC

C1

discharging path

Dboot

T1
Cboot

D1

aaa-034641

This disadvantage of the simple circuit depicted in Figure 121 is solved with themore sophisticated approach shown in Figure 122. The positive input of an
operational amplifier is connected to the AC source. The output is connected to adiode and directly coupled back to the negative input from the cathode side. C1 isthen charged to exactly the positive peak voltage of the input signal. Negative
polarity input voltages let the operational amplifier clip at the maximum negative
output voltage. The diode blocks this voltage, so the voltage at C1 is not hampered.

VOUT

Diode applications and use cases

Figure 121 shows a simple peak voltage detector. There is an AC source rectified by
the diode D1. C2 is charged to the positive peak voltage of the incoming signal,
reduced by VF. The circuit works as a peak voltage detector. Via a discharge resistor
R1, C2 is discharged again, and does not remain forever at the highest voltage everapplied. With an RC time constant τ = R1 × C1, a discharge of C1 can be achieved.
With a time constant chosen significantly higher than the duration Tin of one single
oscillation in the input signal, an AM demodulator is built. The amplitude of the
input signal must be significantly bigger than VF of the switching diode. For the AM
demodulation, the carrier signal should not fall below, or close to, VF.

7

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7

GATE
DRIVE

Rboot
VSW
charging path

+Vaux

GATE
DRIVE

T2

GND

Figure 123 | Half-bridge with bootstrap circuit for high-side gate drive supply.

AC-IN

R1

C1

Figure 122 | Precision peak voltage detector.

164

165

Although the bootstrap circuit consists of only three components, very carefulselection of each component is important for good performance of the entire
half-bridge. The following section is intended to provide an overview of typicaldesign considerations when choosing a bootstrap diode.
Blocking voltage
The bootstrap diode must be designed for the same blocking voltage as thehalf-bridge FETs. It must be able to block the static HV supply voltage VDC plus any
additional turn-off overshoot during operation of the half-bridge circuit.
Dynamic vs. static performance
Both the dynamic switching and the static conducting properties must be
considered carefully and a trade-off is often required when selecting the bootstrap
diode. In lower frequency designs switching up to tens of kHz, the dynamic
properties of fast modern diodes are usually sufficient and a device with low VF andlow leakage can be selected. However, for high-frequency, fast-switching
applications, choosing a small diode with low junction capacitance Cj and best
possible reverse recovery properties (minimal trr and Qrr) is mandatory. The stored
charge on the diode will be moved on and off during each switching cycle and canlead to considerable losses in Rboot at high frequency. In very high frequency
designs, the charging current in the bootstrap diode might not decay to zero
before the low-side FET T2 is turned off and reverse-recovery will occur. During thisoperation, an additional charge Qrr is transferred back from the high-side capacitor
during turn-off. This increases the total required charging current, as shown in thecomparison between a hyperfast silicon diode and a silicon-carbide MPS (Merged
PIN Schottky – please refer to chapter 1.6) diode in Figure 124. In addition, snappy
diode recovery can lead to strong ringing that might cause EMI problems, and caneven trigger the UVLO protection of the gate drive circuit. For these reasons,
Schottky diodes can be a good choice for high frequency designs, even though
their static stored charge is usually larger than that of comparably rated p(i)n-diodes.

166

Figure 124
Bootstrap current
waveform of Si and SiC
bootstrap diodes in a
400V, 750kHz
half-bridge circuit.

200

0

−200
Hyperfast Diode, 600 V, 1 A
−400
0

500

1000

1500

400
200

Diode applications and use cases

As illustrated in Figure 123, there are two main states. While the low-side (LS)transistor T2 is on, the switch-node of the half-bridge is pulled close to the ground
potential (GND) and Cboot is charged through Rboot and Dboot by the auxiliary supply
voltage Vaux. As soon as the low-side FET turns off and the high-side (HS) FET T1
turns on, Vsw is pulled to the HV supply voltage VDC and the bootstrap diode will
start blocking. In this state, the high-side gate circuit is separated from the supply
rails and will only be powered by the bootstrap capacitor.

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Bootstrap current (mA)

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70
SiC MPS Diode, 650 V, 1 A
−200
0

500

1000

1500

t (ns)As a drawback, the small diode will have a lower current capability and higher
forward voltage drop VF. The forward voltage VF directly impacts the amplitude of
the high-side gate drive voltage VCboot. As shown in Figure 123, Cboot is connected
to Vaux during the charging phase via Rboot and Dboot leading to the voltage
equation

VCboot = Vaux − VF − Rboot ∙ iboot
For low-frequency designs, the charging time constant τboot = Cboot ∙ Rboot is typicallyconsiderably lower than the conduction time of the low-side transistor T2, as longas the circuit is not operated at very small duty cycles. This allows iboot to decay to 0
and VCboot will mostly depend on the forward voltage drop of the diode at very low
current. In low-voltage designs, the use of a Si-Schottky diode with its very low
forward voltage drop can therefore ensure that the high-side gate supply voltage isvery close to Vaux. In contrast, at high switching frequency and in high-voltage
designs, VCboot can drop significantly below Vaux. Both HV p(i)n-diodes and SiC
Schottky diodes show significantly higher forward voltage drop and the bootstrap
current in high-frequency operation might not decay to zero, leading to additional
voltage drop across Rboot. Figure 125 shows the results of an LTSpice simulation of
a 400V converter operated at a high switching frequency of 500kHz with three1671.10μs
1.06μs1.02μs0.98μszoom on turn-off

different bootstrap diode models. It can be seen that the forward characteristics ofthe diodes have direct impact on the high-side supply voltage VCboot, and thus
might influence the switching performance of the HS FET. The zoomed turn-on andturn-off current waveforms of the bootstrap diodes in Figure 125 also show the
impact of the stored charge on the diodes. The 1A hyperfast diode has the smallest
static charge but still leads to lowest HS supply voltage due to its larger VF drop.
Since charging currents do not decay to zero in this scenario, both silicon diodes
show reverse recovery. It must be noted that most available diode models for
LTSpice might not properly simulate reverse-recovery and thus a measurement isalways advisable for these very high frequency converter designs.
Current ratings
As part of the start-up routine in bootstrap powered half-bridges, the low-side
transistor is turned on constantly to charge up the bootstrap capacitor Cboot on thehigh-side. The peak current handling capability of the bootstrap diode must be
sufficient to support the first current pulse with a peak value ofîboot = (Vaux − VF)/Rboot.

7

This is usually more of a challenge in low-frequency designs with larger Cboot since
peak duration is longer. In continuous operation, the current requirement is usually
many times lower when only the driving losses of the HS FET need to be covered.
Nevertheless, the steady-state condition should be considered carefully as well, forexample when additional loads on the high side are powered through thebootstrap supply.

10.08

10.15

10.22

10.29

10.36

10.43

10.50

10.57

10.64

10.71

10.78

−450

−360

−270

−180

0

−90

90

180

270

360

450

540

10.85

Vcboot (V)

630

0.1μs

0.3

0.5μs

0.7

0.9μs

600V | 3A | hyperfast

1.1

1.3μs

160.00ns

zoom on turn-on

180.00ns

200.00ns

220.00ns

600V | 1A | hyperfast
650V | 1A | SiC MPS

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iboot (mA)

Figure 125 | Simulated waveforms (LTSpice) at 500kHz for different diode types,
Cboot = 1µF, Rboot = 10Ω, Vaux = 12V.

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For the following explanations and waveforms, some assumptions have to be madefor the sake of simplicity:

7.6 Overview of hard-switching
DC-DC converter topologies
In this section, the fundamentals of hard-switching topologies with special
emphasis on the resulting diode stress is presented. In particular, the impact of thediode technology on the overall losses of the converter is discussed. Various
voltage requirements of DC-DC converter applications influence the usability ofdifferent diode technologies. Therefore, one aim of this section is to give guidancein selecting the most suitable diode technology, when considering the different
voltage and application requirements.

Power converters use the switching mode of semiconductors to efficiently convert
electrical energy from one form to another. With only minor differences, allconverters obey the same principles. In the following section, this fact is utilized to
explain the basic principles of hard-switching topologies, and in particular, to describe
the operation of diodes in this environment. The basic fundamentals of power diodes
used in switch-mode will first be described in detail using the buck-converter which is
the most generic topology. Later, these same principles will be applied to othercommon structures. The particularities of these converter topologies – especiallyfrom the diode perspective – will be presented and illustrated.

aaa-034645

The schematic representation of a non-isolated asynchronous buck-converter isillustrated in Figure 126. As depicted, it consists of input and output capacitors tostabilize the dc voltages, a power inductor, a power transistor and a power diode. The
load, represented as an ohmic resistance, symbolizes that converted electrical energy
is transformed into another form of energy, such as mechanical or thermal energy.

iLsource

C1

VIN

L

D

1.	All devices are assumed to be ideal:• No losses• No parasitic elements• Ideal switching transitions with infinite steepness• Zero on-resistance and cut-in voltage for the power semiconductors• Infinite off-resistance for the power semiconductors• Passive components have a purely linear behavior
2.	The converter operates in steady-state conditions.
3.	The capacitors have finite capacitances, but their values are high enoughsuch that variations in their voltages can be ignored.

7.6.1 Principles of hard-switching topologies

T

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C2

R

load
VOUT

7
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7

4.	The inductor has a finite inductance and its current can possess atriangular AC ripple current in addition to its DC bias current.
5.	A fixed switching frequency is used. The voltage conversion from input tooutput is controlled via the duty cycle.
Once the principal function of the converter is described and the behavior of power
diode has been shown, the non-ideal behavior of the diode in a hard-switching
DC-DC converter application will be described in greater detail.
Given the previously-mentioned simplifications, a buck (also called step-down)
converter converts an input DC voltage Vin into a lower output DC voltage VOUT by
periodically switching the transistor T on and off. The current paths during on-stateand off-state of the transistor are depicted in Figure 127 and Figure 128. The
corresponding, idealized, triangular inductor current waveform for both states is
illustrated in Figure 129. During the on-state, energy is stored in the magnetic fieldof the power inductor, resulting in a linear rising current flowing through it. Oncethe transistor is turned-off, the stored energy in the magnetic field cannot instantly
vanish. As a result, the current flows through a new path presented by the power
diode. This operation is called ‘free-wheeling’ and the diode is often referred to asa ‘free-wheeling diode’ which maintains the energy supply of the load through thestored energy in the power inductor and output capacitor, resulting in a linearlydeclining inductor current and declining stored magnetic energy. In this way,energy is transferred from the input to the power inductor, and stored in its
magnetic field during on-state, and this particular amount of energy is thentransferred from the magnetic field to the load during freewheeling. This process
happens periodically providing a continuous power supply to the load.

Figure 126 | Schematic of a buck converter.

170

171

source
VIN

I

II

Ton

Toff

L

iT

C1

D

C2

R

load
VOUT

I: Transitor ont

Figure 129 | Inductor, transistor and diode current waveforms.

CCM
VL
T

source
VIN

C1

BCM

iL

D

DCM

iL

L

iL

t

C2

R

load

iD

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Figure 127 | Transistor in on-state and diode in off-state.

tiD

Diode applications and use cases

TiL

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VL

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t
iD

VOUT

iD

t

t

t

II: Transitor off
VD

VD

Vin

VD

Vin

Figure 128 | Transistor in off-state and diode in on-state.

Regardless of the load condition of the converter, and the amount of stored energy
in the magnetic field of the power inductor, the waveform always remains
triangular, as shown in Figure 129 , but the inductor current may possess zerocurrent phases. Three different operational modes can be distinguished. First, theinductor current can be continuously non-zero during the switching period. Second,the current can reach zero at the exact end of the period. Thirdly, it can reach zero
during the freewheeling phase prior to the end of the switching cycle. These threemodes are referred to as continuous conduction mode (CCM), boundary conduction
mode (BCM), and discontinuous conduction mode (DCM) respectively, as shown in
Figure 130.

Vin
Vout

t

t

t

Figure 130 | Diode current and voltage waveforms in a buck converter
under continuous current mode (CCM), boundary conduction mode (BCM) anddiscontinuous conduction mode (DCM) conditions.

CCM, BCM and DCM will affect the loss distribution of the diode. These losses will
be explained for the buck converter and then for the other common topologies.

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CCM

BCM

iD

DCM

iD

iD

t

t

t

Figure 131 | Diode current waveform in CCM. BCM, DCM.

18
25°C
75°C
100°C
150°C
175°C

16
14
12

Conduction loss of the diodeaaa-034534

The depicted triangular current waveform of the inductor assumes losslesscomponents in a buck converter. In reality, a power converter is obviously not
lossless. Nevertheless, in the majority of real world designs with lossy inductors,
this triangular waveform assumption still holds true. The reason for this is because
the amount of stored magnetic energy per cycle is usually magnitudes higher thanthe energy loss per cycle. Therefore, only a small amount of energy loss isneglected compared to the stored energy in the magnetic field. In real world
applications, the true inductor waveform follows an exponential function but
appears to be a triangular waveform because the time constant of it is much higher
than the switching period of the converter. As a consequence, the loss mechanismin the diode can be described by using the lossless triangular waveforms.

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7.6.2 Diode power losses in CCM, BCM and DCM

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IF (A)

Diode applications and use cases

7

10

Looking at the diode currents in Figure 131, it can be seen that the diode current
consists of a DC portion and an AC portion. That means that depending on the
I-V-curve (see Figure 132) of the diode, at each moment during the diodeconduction phase the instantaneous power losses in the diode are different.

8
6
4
2

The total conduction losses can be expressed as the mean value of theinstantaneous power losses during the converter operation:

0
0

0.4

0.8

1.2

1.6

2.0

VF (V)Pc =1 T
1∫ P (t) ∙ dt = ∫ 0T id(t) ∙ vF (id(t),Tj ) ∙ dt
T 0 c
TWith T being the duration of one switching period. Usually, the non-linear behaviorof the diode’s I-V-curve prohibits the solution of this equation. In particular, thefeedback of the losses on the junction temperature Tj which in return, affects the
I-V-curve of the lossy diode, leads to a complex non-linear equation. Therefore, thecomplete thermal path from junction to ambient has to be taken into account. The
conduction loss equation for Pc has to be solved iteratively, or by using numericalmethods or simulation.
However, in order to estimate the losses analytically, the expected worst caseconditions should be used for a first initial calculation. That means that besides thefull knowledge of the converter operational conditions, the following assumptions
are needed:

Figure 132 | I-V curve of SiC diode PSC1065K at different junction temperatures.

By simplifying and expressing the corresponding I-V curve characteristics of thediode using a differential resistance rd and a cut-in voltage VF0 an analyticalworst-case conduction loss estimation can be performed. With this analysis and theactual triangular DC-biased diode current waveform of the converter, the complex
equation of the conduction loss of the diode can be simplified to:

Pc =

1 T
1
∫ P (t) ∙ dt = ∫ 0T id(t) ∙ vF (id(t),Tj ) ∙ dt ~ VF0(Tj ) × Id(avg) + rd(Tj )T 0 c
T× (Id(rms) )²

Where Id(avg) equals the average value and Id(rms) the root mean square value of thediode waveform.

• Given and fixed worst-case ambient temperature Ta(max)• Maximum thermal resistance from junction to ambient• Worst-case I-V-curves of the chosen diode• Knowledge of the switching losses and blocking losses of the diode

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If this calculated worst-case conduction loss, combined with switching and blocking
loss, is less than the maximum power which the device can dissipate through thegiven thermal resistance, the diode will operate under stable conditions. Moreover,this calculated loss can be used to estimate the corresponding junction
temperature which will be lower than the initially assumed worst-case junction
temperature. As a next iterative step, and to improve the accuracy of thecalculation, the I-V curve corresponding to the calculated junction temperature canbe used instead of the worst-case I-V curve. By doing so, the newly calculated
conduction losses will be lower and more accurate.

Blocking loss of the diodeThis element of the power losses of the diode only occurs during blocking
operation. As depicted in Figure 130, during blocking operation, the off-statevoltage Voff can be assumed to be a constant value. During the blocking phase, thediode is thus permanently reverse-biased with the off state voltage Voff. The
imperfection of each diode technology during reverse operation causes a small
leakage current ileakage. The actual magnitude of this leakage current is dependent
on the applied negative reverse voltage and the associated junction temperature.
As a result, the associated diode leakage current, in combination with the off-statevoltage, generates losses. Although the leakage current is comparably small due tothe high off-state voltage, the resulting loss can be significant depending on thechosen diode technology. This loss portion is called blocking losses and can be
described as:

Pb =

1 T
1
∫ P (t) ∙ dt = ∫ 0T Vr ∙ ileakage(Voff,Tj) ∙ dt =T 0 b
TVoff × ileakage(Voff,Tj) × (1 − δ)With δ being the duty cycle of the converter. As can immediately be seen, theblocking loss equation depends on the off-state voltage during blocking operation,
the leakage current as a function of the applied reverse bias Voff and the actual
junction temperature, as well as the duty cycle of the converter. Thus the equation
is non-linear which is caused by the complex non-linear behavior of the leakage
current against junction temperature, and the applied off-state voltage.
Additionally, the feedback of this loss on the junction temperature, and thus, thethermal path from junction to heatsink, is required. This loss portion can only be
accurately calculated by using iterative steps or numerical solution approaches.

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Diode Application Handbook

In order to estimate the losses, a comparable approach to the conduction loss
estimation method can be used. For this, the worst case leakage current is used forthe initial calculation. Additionally, the following assumptions are accepted:• Given and fixed worst-case ambient temperature Ta(max)• Maximum thermal resistance from junction to ambient• Worst-case I-V curves of the used diode• Knowledge of the switching losses and conduction losses of the diodeBy using the worst-case leakage current, which is usually at the highest junction
temperature, the associated worst-case blocking loss can be calculated using theabove equation. If the device has the capability to dissipate more power through its
thermal resistance than the total generated power losses, consisting of the
conduction loss, switching loss and calculated worst-case blocking loss, the diodecan operate under steady state conditions. Furthermore, the associated junction
temperature – given the assumption of worst case leakage current – can becalculated, which can be used for the next iterative calculation. This calculated
junction temperature can then be used to determine the actual effective leakage
current, which will be lower than the worst case leakage current.

7
Diode applications and use cases

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7

By repeating the blocking loss calculations according to the equation above, and byusing the newly-calculated leakage current instead of the worst case leakage
current, the calculated blocking loss will be more accurate and also lower than theinitial approximation. By successive repetition of this iterative process – there-calculated blocking losses, corresponding junction temperature, and newlydetermined corresponding reverse static characteristics of the diode – the accuracyof this estimation will improve, and the iterative steps will ultimately converge.
In the majority of switched-mode applications where the topology is equipped withsilicon PN diodes or SiC diodes, the occurring blocking loss is very low and canusually be neglected in the total power loss calculation. For Si-based Schottky diodetechnologies, however, the leakage current and the associated blocking losses canbecome a significant factor, especially for low VF types (low Schottky barrier);
therefore these losses must be taken into account.

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Switching loss of the diode

Forward recovery loss of the diodeThe transition from off-state to on-state of the diode and vice versa is not ideal. In
Figure 133, both transition phases, diode turn-on and diode turn-off, as part of theinductor current phases are shown. The phase III describes the diode turn-on andphase III the diode turn-off. During these transitions, diodes experience a loss
which is neither static on-state loss nor static off-state loss.

Forward recovery occurs during the turn-on transition from an initially reverse
biased off-state to the on-state of the diode. After the dv/dt voltage transition, andduring the di/dt turn-on ramp, the transient forward voltage drop across the diodeis higher compared to the associated static I-V curve. As a result, this transient
forward over-voltage causes additional losses beyond the expected losses
according to the static I-V curve. It is caused by the initially low conductivity of thediode which takes a finite amount of time to reach its higher final conductivity. The
associated forward recovery energy loss can be calculated by integrating the
instantaneous power loss, by capturing the diode forward and forward voltage
waveforms:

This loss portion is called switching loss, dynamic loss or recovery loss, and can be
distinguished as forward recovery or reverse recovery loss. All elements, evenparasitic elements of the commutation cell, as illustrated in Figure 134, contributeto the losses of the diode, but these will not be discussed in for the sake ofsimplicity.
Please refer to chapter 1 for switching characteristics of different diodetechnologies.

iL

I  IIIII  III

0

Figure 133
Diode turn-on andturn-off transitions.
Power (W)II  It + t fr

Eon = ∫ t 0
Vwith groundplate
0
−10

L tip

Time (ns)t

VSwitchid(t) ∙ vF(t,Tj) ∙ dt

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The integration of the instantaneous energy loss usually covers the period from thestart of the di/dt ramp (t0) to when the forward over-voltage collapses back toapproximately 110% of the steady-state value (t0+tfr with tfr being the forward
recovery time).
100 V power loss can be calculated by multiplying the forward
The corresponding
300 V
recovery energy500
loss
by the switching frequency of the power converter:V

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700 V

VL
T

source

C1

L

D

VIN

R

VOUT
Grid gestrichelt
Commutation cell

Figure 134 | Commutation, state transition phase.

178

C2

Abbildung Kontur 0,5 pt
Abbildung fett 1 pt
load
Beschriftung/Pfeil 0,3 pt
Grid

Pon = Eon × fsw
The forward recovery characteristic is not a fixed diode-specific behavior; it isinfluenced by several parameters which, in turn, alter the loss. The amount ofover-voltage and thus the amount of forward recovery loss depends on several
diode-specific design parameters which will not be discussed in this applicationrelated section. But there are some parameters which are indeed related to theapplication and influence the forward recovery behavior:• di/dt slew-rate• turn-on current (after diode turn-on)• applied reverse voltage (prior to the turn-on event)• ambient temperature179

nexperia | Design Engineer’s Guide

However, compared to reverse recovery losses (which are explained in the next
section), this loss portion is low and can usually be ignored in the overall total
power loss calculation of the diode. Nevertheless, there are some applicationspecific situations where forward recovery loss can become relevant in hardswitching converter topologies.
In Figure 131, the three different modes of operation are shown. For CCM, bothreverse recovery and conduction losses will dominate the loss distribution so thatforward recovery is of minor concern. In contrast to the continuous conductionmode, in boundary and discontinuous conduction modes the diode turn-off underzero current conditions will result in a quasi-lossless, reverse-recovery-free turn-off.
However, the diode still shows hard turn-on during these operation modes which,in turn, leads to forward recovery loss. A particular situation in BCM and DCM
modes where forward recovery may be of relevance for precise power loss
calculation is at low-load conditions of the converter combined with high switchingfrequency and fast slew rates during turn-on.

Reverse recovery loss

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Diode Application Handbook

Instantaneous power can be calculated from the captured current and voltage
waveforms of the diode. In order not to miscalculate and misinterpret the results,
the lossless amount of stored capacitive energy Ec must be subtracted.
An accurate calculation is a complex task and requires many measurements of thereverse recovery waveforms. However, a first rough estimation of the expected
losses is given by:

Eoff = Qrr × Vr(off)With Qrr being the specified stored charge in the datasheet and Vr(off) the off-statevoltage in the application. Although the inductor waveforms are similar for all
hard-switching DC-DC-converters, the off-state voltage Vr(off) of the diode isstressed differently depending on the chosen technology. Therefore, the following
section will describe particularities of widely used converter topologies so thatapplication engineers can consider their loss estimation and diode selection.

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7

In contrast to forward recovery, reverse recovery occurs when the diode has tochange from forward conduction state to reverse-biased off-state or blocking
state. The turn-off transition happens with a finite di/dt slew rate, as shown in
Figure 15 in chapter 1. When, after a certain amount of time (t2 in Figure 15), theturn-off current reaches zero-crossing, the stored charges, which are still within thediode, prevent the diode from blocking. Instead, the voltage across the diode stays
at nearly zero. In order to remove these charges from the device, a significant
reverse current flows through the channel. Depending on the chosen diodetechnology, this charge contains either pure capacitive charge (Schottky), or both
capacitive and stored charge due to minority carriers. In case of stored minority
carriers in the junction (PN diodes), the time the diode requires to be able to blockagain is comparably large compared to pure capacitive charge-based devices like
Schottky diodes. This is because the stored charge carriers have to recombine in thejunction. Please refer to Figure 35 for a comparison between truly capacitive
turn-off of a SiC diode versus the bipolar turn-off of a silicon recovery diode.
The associated turn-off energy can be calculated by integrating the instantaneous
power within the limits given in Figure 15, with t2 being the first zero crossing andt4 being the second zero crossing of the current:tEoff = ∫ t 4 id(t) ∙ vD(t) ∙ dt − Ec
2

180

181

In this section, the most common topologies for DC-DC converters are described.
All these topologies obey the principles of hard-switching as described in section
6.6.1. Furthermore, the loss calculation is also always similar for all topologies andhas already been described in section 6.6.2. Therefore, only the individual
particularities of the topology and their impact on losses will be discussed.

7.7.2 Boost converter
The opposite of a buck converter, the boost converter elevates a lower DC input
voltage to a higher DC output voltage. The schematic of the boost converter
topology is depicted in Figure 135. In contrast to the buck – and excludingtransient over-voltages during diode turn-off transition – the diode has to block andwithstand the DC output voltage rather than the DC input voltage (see Figure 136).

7.7.1 Buck converter
A buck converter, also known as a step-down converter, is a system which converts
a DC input voltage to a DC output voltage with lower value using the switchingmode of power semiconductors. A schematic representation of the non-isolated
topology of an asynchronous buck converter is given in Figure 126. As described in
the previous section, 6.6.1, and illustrated in Figure 130, the diode has to block the
input voltage Vin (transient overvoltage excluded). Therefore, for the selection of
the diode, the highest expected average and RMS diode current, as well as thehighest input voltage must be taken into account for the appropriate current andvoltage ratings.
The conduction loss calculation can be used as described in section 6.6.2.1. This
calculation is universally true for all converters, so no adaptations are required. On
the other hand, the remaining loss portions, blocking loss and forward as well as
reverse recovery loss are affected by the topology choice. For blocking loss
estimation in a buck converter, the maximum reverse voltage Vr,max across thediode equals the maximum DC input voltage Vin,max. The associated leakage current
at this voltage needs to be taken into account. Regarding the forward and reverse
recovery losses, measurements at worst-case operating conditions (highest
junction temperature, highest expected commutation speed and highest forward
current at maximum input voltage) are required to estimate the highest losses thediode will have to handle in the buck converter. If BCM or DCM are the only modesof operation, reverse recovery losses usually can be neglected.

iL

iD

iT

VDC

VOUT

Diode applications and use cases

7.7 Topologies

7

Diode Application Handbook

aaa-034653

nexperia | Design Engineer’s Guide

Figure 135 | Schematic of a boost converter

CCM

BCM

iL

iL

t

t
iD

t
VD

Vout

t
iD

t
VD

DCM

iL

iD

aaa-034654

Diode applications and use cases

7

t
VD

Vout

Vout
Vout − Vin

t

t

t

Figure 136 | Diode current and voltage waveforms in a boost converter under continuous current
mode (CCM), boundary conduction mode (BCM) and discontinuous conduction mode (DCM)
conditions.

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The output voltage related blocking voltage stress must be considered both for theselection of the suitable blocking voltage capability of the diode and also for the
power loss calculation.
For the blocking voltage capability, the highest possible voltage conversion rate in
the boost converter must be considered for correct diode selection. To calculate
the blocking loss, the reverse and forward recovery losses and the maximum
output DC voltage (rather than the input voltage) must be used. This is the majordifference from a buck converter, especially when assuming a fixed input DC link
voltage Vin. This means for the maximum reverse voltage Vr(max) across the diode,Vr(max) = VOUT(max). So, the corresponding diode leakage current at highest output
voltage of the converter must be used for accurate blocking loss estimation. Thatmeans that, in contrast to the buck converter, the converter operation at the chosen
duty cycle and the resulting DC output voltage at a given fixed DC input voltage, hasa direct impact on the voltage stress the freewheeling diodes have to withstand.
For the forward and reverse recovery loss calculations, functions such as junction
temperature, commutation speed and forward current have the same impact on
the recovery losses as in a buck converter. However, the input voltage is not
significant for the recovery loss calculation at a given diode forward current. The
recovery behavior and losses vary with the resulting DC output voltage, and thus
are implicitly dependent on the duty cycle and the mode of converter operation.
Especially under CCM conditions, reverse recovery has a major influence on the loss
distribution. Otherwise, the losses are almost negligible due to the zero current
turn-off transition (zero current switching) of the diode.

7

Diode Application Handbook

The buck-boost converter consists of the same number of elements as the buck andboost converters. However, the arrangement is different. As can be seen in
Figure 137, the power inductor is positioned in the middle between the power
semiconductors. As a result, the corresponding energy transfer leads to an inverted
DC output voltage compared to the DC input voltage.

CCM

BCM

iL

t
iD

iL

t
iD

Vout + Vin

t
iD

t

t
VD

DCM

iL

VD

Vout + Vin

Diode applications and use cases

nexperia | Design Engineer’s Guide

aaa-034656

Diode applications and use cases

7

t
VD

Vout + Vin
Vout

t

t

t

Figure 138 | Diode current and voltage waveforms in a buck-boost converter under continuous
current mode (CCM), boundary conduction mode (BCM) and discontinuous conduction mode (DCM)
conditions.

7.7.3 Buck-boost converter

iT

iL

VDC

aaa-034655

The buck-boost converter unifies the properties of both buck and boost converters.
Buck-boost is able to convert a input DC voltage to a higher, equal or lower DC
output voltage VOUT depending on the chosen duty cycle. The topology of abuck-boost-converter is illustrated in Figure 137.

iD

VOUT

The corresponding current and voltage waveforms of the buck-boost converter are
shown in Figure 138. As previously explained, all converters obey the principles ofhard-switching which always results in the same triangular waveforms, independentof the actual topology. However, the voltage blocking stress on the diode is
topology-dependent. The diode in this particular topology has to block andwithstand a voltage, which is the sum of both the DC input and the converted DC
output voltages, which is a direct consequence of the inversion behavior of thearrangement. In that regard, the diode losses in a buck-boost converter are
affected by both the fixed DC input voltage and the DC output voltage, which isagain a consequence of the duty cycle. Therefore the maximum reverse voltage
across the diode is: Vr(max) = Vin(max) + VOUT(max). So the maximum expected output
voltage at maximum DC input voltage must be considered for diode selection. Also
the recovery losses are dependent on the sum of these two voltages. All otheraspects for the recovery loss calculation remain the same.

Figure 137 | Schematic of a buck-boost converter.

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Diode Application Handbook

A flyback converter is a DC-DC converter whose mode of operation is very similar tothe buck-boost converter except that it provides galvanic isolation between the DC
input and DC output voltage. The flyback topology can be derived from thebuck-boost converter which will not be shown in this publication for sake ofsimplicity. Galvanic isolation is achieved by using a coupled inductor with two
windings which share the same magnetic core, instead of one power inductor. The
schematic is shown in Figure 139.
In contrast to a transformer, this coupled inductor principle stores magnetic energy
during the transistor turn-on phase. This stored magnetic energy is eventuallytransferred to the secondary side so that the mode of operation obeys theprinciples of hard-switching, as previously explained. The turns ratio between
primary and secondary side windings provides another opportunity to adjust theDC output voltage at a given DC input voltage, in contrast to previously-mentioned
converters. The turn ratio ‘a’ (here defined as ratio of secondary to primary side
winding NNps ) also influences the magnitude of the secondary-side current. In all theother previously mentioned converters, the magnitude of current the diode has tocarry at the start of the diode phase is equal to the maximum transistor current at
the end of the transistor conduction phase (see Figure 129). Depending on theturns ratio ‘a’, the maximum peak transistor current and diode current may differ.
Both secondary and primary sides are coupled via the magnetic flux of themagnetic core so that the primary side and secondary side inductor current are
inversely proportional to the turns ratio ‘a’. As shown in Figure 140, the secondaryside inductor current and the diode current are the same, and the peak value isinversely proportional to the peak transistor and thus peak primary current.

iL1

iL2

iD
VOUT

VDC

iT

CCM

BCM

iL

aaa-034658

7.7.4 Flyback converter
DCM

iL

iL

iL,p
iL,s
t
iD

t
iD

Vout + Vin • a

iD

t

t
VD

t

VD

Vout + Vin • at
VDVout + Vin • a
Vout

t

t

Diode applications and use cases

nexperia | Design Engineer’s Guide

aaa-034657

Diode applications and use cases

7tFigure 140 | Diode current and voltage waveforms in a flyback converter under continuous
current mode (CCM), boundary conduction mode (BCM) and discontinuous conduction mode (DCM)
conditions.

For correct diode selection, another aspect, the turns ratio ‘a’ of the coupledinductor, must be considered. This affects the blocking voltage capability and also
the current rating.
For correct diode selection, another aspect, the turns ratio ‘a’ of the coupledinductor, must be considered. This affects the blocking voltage capability and also
the current rating.
The maximum off-state voltage of the diode excluding transient over-voltages
equals the sum of the DC output and the DC input voltage multiplied by the turns
ratio. Thus Vr(max) = a × Vin(max) + VOUT(max) must be taken into account under all
possible converter scenarios (with ‘a’ being defined as ratio of secondary to primaryside winding NNps ). The additional dependency of the turns ratio must be considered
for blocking and recovery losses dependent on the chosen mode of operation(CCM, BCM DCM). The diode current, on the other hand, is inversely proportional to
the turns ratio ‘a’. That means that, especially at a low turns ratio, the secondaryside inductor current and thus the diode current can be significantly higher. This
must also be considered for the conduction loss estimation and diode selection forthe chosen diode technology.

Figure 139 | Schematic of a flyback converter.

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8

Diode Application Handbook

Chapter 8
Summary

Summary

Diode applications and use cases

7189nexperia | Design Engineer’s Guide

Discrete diodes are still a very important and basic component of electronicsystems. Their electrical and thermal properties as well as their reliability aredecisive for the overall performance and robustness of the entire electronicsystem.
There are a wide variety of diode technologies available in different packages andform factors. This handbook summarizes the choices available on the market anddiscusses their device structure. Interestingly, there are still new developments indiscrete diodes. Specifically, the SiGe diode technology newly developed by
Nexperia should be noted here.

Diode Application Handbook

Abbreviations

Abbreviations

Summary8

The normalization of the currents with respect to the die size in this handbook
allows a fair comparison of the different technologies. Both the static and dynamic
behavior of the diodes are discussed and compared.
A separate section is devoted to the novel Schottky diodes based on silicon carbide,and the advantages that SiC diodes bring are presented and compared to silicon
diodes.
Diode packaging plays no less a role than the semiconductor element housed
inside the packaging. Therefore, different package styles for discrete diodes arepresented. The associated thermal properties of the diodes are discussed in a
separate chapter. Of particular note here is the phenomenon of diode called
thermal runaway, which is often overlooked by design engineers and can lead to
failures of the system.
Since diodes are also used in critical infrastructure and automotive electronics, thestress tests performed by Nexperia to qualify and release diodes are also touched
upon in a chapter in this book.
Last but not least, the last chapter of the handbook discusses important diodeapplications. Here, the general consideration of losses in switched-mode converters
should be emphasized.
For questions and suggestions do not hesitate to contact us.
www.nexperia.com/about/worldwide-locations/sales-offices

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AC
BCM

Autoclave
Boundary conduction mode

CCM
CdContinuous current mode
Diode parasitic capacitance

DCM
di/dt
Dn
EFR
Eoff
Eon

fsw
H3TRB
HAST
HTOL
HTRB

iboot
îboot
IF
IF(AV)
IFR
IFRM
IFSM

192

Discontinuous conduction
mode
Current edge steepness /slope gradientDiffusion coefficient
Early failure rateTurn-off energy
Forward recovery energy
loss

IOL
IR
IRM

IZ

Intermittent operational life
Reverse current
Peak reverse recovery
current
Root mean square of
forward current
Zener current

JR

Reverse current density

MPS
MSL

Merged PIN Schottky
Moisture sensitivity level

IRMS

Current through thebootstrap diodePeak current through thebootstrap diode
Forward current
Average forward current
Intrinsic failure rate
Repetitive peak forward
current
Non-repetitive peak forward
current

rdif
RT

Rth(j-a)Rth(j-c)Rth(j-mb)
Rth(j-sp)

Rth(j-top)
ni
Np
Ns

Intrinsic carrier
concentration
Primary side winding
Secondary side winding

Switching frequency
High humidity / hightemperature reverse bias
Highly accelerated stresstest – biased
High temperature
operating life
High Temperature reverse
bias

Diode Application Handbook

PB
PC
Pdiss
Pgenerated

Ptot

Blocking loss
Conduction loss
Dissipated power
Self-heating generated byreverse leakage current
DC conduction loss
Forward recovery loss
Average reverse power
dissipation
Total power dissipationq
Qrr

Elementary charge
Reverse recovery charge

Pload
Pon
PR(AV)

Rth(sp-a)

SFrr
SiC
SiGe
SOA
SZ

Tamb
Tc
TC
Tj
Tjmax
tp
trr
TS
Tstg
UHAST

Differential resistance
Normalized thermal
resistance is with respect topackage footprint
Thermal resistance junction
to ambient
Thermal resistance junction
to case
Thermal resistance junction
to mounting base
Thermal resistance junction
to solder point (usually thecathode path)
Thermal resistance junction
to topThermal resistance solder
point to ambient
Softness factor
Silicon carbide
Silicon germanium
Safe operating area
Thermal coefficient of Zener
voltageAmbient temperature
Case temperature
Temperature cycling
Junction temperatureSpecified maximum junction
temperature
Pulse width
Reverse recovery time
Temperature shock
Storage temperture

VCbootVdrift
Vf
VFRM
Vms

Vpn
VR
VZ

High-side supply voltage –voltage across bootstrap
capacitance
Forward voltage drop acrossdrift layer
Forward voltage drop
Peak forward recovery
voltage
Forward voltage drop acrossmetal semiconductor
interface
Forward voltage drop acrosspn junction
Reverse voltage
Zener voltage

Yth(j-top)

Thermal coefficient junction
to topZth(x-y)Thermal impedance
between point x and yδDuty cycle

ΦB

Barrier height

Abbreviations

Abbreviations

nexperia | Design Engineer’s Guide

Highly accelerated stress
test

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Diode Application Handbook

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195

Definitions
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review and subject to formal approval, which may result in modifications oradditions. Nexperia does not give any representations or warranties as to theaccuracy or completeness of information included herein and shall have no liability
for the consequences of use of such information.

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and/or use of Nexperia products in such equipment or applications and therefore
such inclusion and/or use is at the customer’s own risk.

196

Diode Application Handbook

Applications — Applications that are described herein for any of these products arefor illustrative purposes only. Nexperia makes no representation or warranty thatsuch applications will be suitable for the specified use without further testing or
modification.
Customers are responsible for the design and operation of their applications andproducts using Nexperia products, and Nexperia accepts no liability for any
assistance with applications or customer product design. It is customer’s sole
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associated with their applications and products.

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Nexperia does not accept any liability related to any default, damage, costs or
problem which is based on any weakness or default in the customer’s applications
or products, or the application or use by customer’s third party customer(s).
Customer is responsible for doing all necessary testing for the customer’s
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the applications and the products or of the application or use by customer’s third
party customer(s). Nexperia does not accept any liability in this respect.
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Notesnexperia | Design Engineer’s Guide

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Diode Application Handbook
Fundamentals, Characteristics, Applications
Design Engineer’s Guide
Copyright © Nexperia UK Ltd.
May 2022
www.nexperia.com
ISBN 978-0-9934854-9-7
All rights reserved.
No part of this publication may be reproduced or
distributed in any form or by any means without
the prior written permission of the author.