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Failure signature of electrical overstress on power MOSFETs
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Information

Content

Keywords

Power MOSFETs, Electrical Overstress (EOS), Unclamped Inductive Switching (UIS)

Abstract

When Power MOSFETs fail, there is often extensive damage. Examination of the size andlocation of the burn mark, the failure signature, provides information about the type of fault
condition which caused the failure. This document provides a catalogue of failure signatures from
common electrical overstress failure modes. The catalogue can be used in forensic investigationof the underlying root cause of failure to improve module design and reliability.

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Failure signature of electrical overstress on power MOSFETs

1

Introduction
Power MOSFETs are used to switch high voltages and currents, while minimizing theirown internal power dissipation. Under fault conditions however, it is possible to apply
voltage, current and power exceeding the MOSFET capability. Fault conditions canbe either due to an electrical circuit failure or a mechanical fault with a load such as a
seized motor. This leads to Electrical Overstress (EOS). Typically the consequence of
EOS is the short circuiting of at least 2 of the 3 MOSFET terminals (gate, drain, source).
In addition, high local power dissipation in the MOSFET leads to MOSFET damage
which manifests as burn marks, die crack and in extreme cases as plastic encapsulation
damage.
Examination of the size and location of the burn mark, the failure signature, provides
information about the type of fault condition which caused the failure. Common fault
conditions are:• ElectroStatic Discharge (ESD)• Unclamped Inductive Switching (UIS) - commonly called Avalanche or Ruggedness• Linear Mode operation• Over-current
Packaged MOSFETs have been deliberately destroyed under these conditions. Images
recorded of the ensuing burn marks on the silicon surface, provide a ‘Rogue’s Gallery’ toaid the explanation of EOS failures.
Section 1.1 to Section 1.4 gives an overview of the common failure signatures.
Appendices in Section 2.1 to Section 2.17 provide further images.

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1.1 ESD - Human body model
1.1.1 EOS method
ESD pulses were applied using a standard Human-body Model ESD circuit; for details
see AEC - Q101 - REV - May 15, 1996. Voltage of the applied pulse was progressively
increased until device failure was observed.
R1

S1

1500 Ω

HIGH VOLTAGE
PULSE
GENERATOR

C1
100 pFS2

terminal A

DUT
SOCKET

short

R2
500 Ω

terminal B
aaa-004855

Figure 1. Typical circuit for Human body Model ESD simulation

1.1.2 Fault condition simulated
Human body model ESD simulates situations when a voltage spike is applied to the
MOSFET exceeding the maximum voltage that can be sustained by the gate oxide ofeither gate-source or gate-drain. The pulse is applied with 1500 Ω series resistance
between the voltage origin and the MOSFET, which limits the rate of rise of the MOSFET
gate voltage. Either human handling, electrical test equipment or malfunctioning circuits
can easily apply such voltage pulses.

1.1.3 Signature
Failure site is found in an edge cell of the MOSFET structure. Outer edge cells and cells
near the gate are the first to be subjected to the incoming voltage pulse and are thus
the first sites where the voltage exceeds the gate-oxide capability. The signature differsfrom Machine Model failures in that the fail site does not show such a strong tendency togroup near the gate, due to the slower rise in gate voltage.

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Failure signature of electrical overstress on power MOSFETs
Table 1. Examples of Human Body Model ESD failure signature

Device name

Cell pitch(μm)

BUK9508-55A

9 (hexagon)

Fail site is gate oxide ofedge cell; see Section
2.1 “Human body model
EOS of BUK9508-55A”
for further images

BUK9Y40-55B

4 (stripe)

Fail site is gate oxide ofedge cell; see Section
2.2 “Human body model
EOS of BUK9Y40-55B”
for further images

PSMN011-30YL

2 (stripe)

Fail site is gate oxide ofedge cell; see Section 2.3“Human body model EOS
of PSMN011-30YL” forfurther images

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Device name

Cell pitch(μm)

PSMN8R5-100PSF

2.5 (stripe)

Fail site is gate oxide ofedge cell, see Section 2.4"Human body model EOS
of PSMN8R5-100PSF" forfurther images.

BUK7Y3R0-40H

1.5 (stripe)

Fail site is gate oxide ofedge cell, see Section 2.5"Human body model EOS
of BUK7Y3R0-40H" forfurther images.

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Failure signature of electrical overstress on power MOSFETs

1.2 Unclamped Inductive Switching (UIS) (Avalanche or Ruggedness)
1.2.1 EOS method
Inductive energy pulses were applied using a standard UIS circuit; for details see
AEC - Q101-004 - REV - May 15, 1996. A fixed inductance value is selected. Current
in the inductor prior to switching the MOSFET was progressively increased until device
failure was observed.
Table 2. UIS ruggedness test circuit and waveforms
Vbr
BVdss
Iav
drain
I
gate
voltage

VDD

L

L

gate
source

0
tav
VDD

Vg
tg(on)

aaa-004859

Figure 2. Circuit diagram for UIS ruggedness test

aaa-004860

Figure 3. Waveforms obtained from UIS test

1.2.2 Fault condition simulated
UIS simulates situations when a MOSFET is switched off in a circuit in which there
is inductance. The inductance can be deliberate (such as an injector coil in a diesel
engine system), or parasitic. As the current cannot decay to zero instantaneously throughthe inductance, the MOSFET source-drain voltage increases to take the device intoavalanche breakdown. The energy stored in the inductance is then dissipated in the
MOSFET.

1.2.3 Signature
Failure site is found in an active MOSFET cell. The burn-mark is usually round in shape,
indicating a central failure site and subsequent thermal damage.
If the avalanche event is long in duration (~ ms), then burn marks locate at central sites
on the die, where there is maximum current flow and reduced heat dissipation. The sites
are often adjacent to wire bonds/clip bonds where current density is high, but not directly
under the wire bond/clip bond as it provides a local heat sink. Failure is at the hottest
location of the die. For short avalanche events
For short avalanche events (~ μs), the burn marks can take on more random locations
over the die surface. The temperature rise in the chip is more uniform with negligible
chance for current crowding and local heating on these time scales. For even shorter
avalanche events, the burn marks can locate at die corners due to the discontinuity in cellstructure at these locations.
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Failure signature of electrical overstress on power MOSFETs
Table 3. Examples of Unclamped Inductive Switching failure signature

Device name

Cell pitch(μm)

BUK7L06-34ARC

9 (hexagon)round burn in active
area; see Section 2.6“Unclamped inductive
switching EOS ofBUK7L06-34ARC” forfurther images

BUK9Y40-55B

4 (stripe)

round burn in active
area; see Section 2.7“Unclamped Inductive
Switching EOS ofBUK9Y40-55B” for further
imagesPSMN7R0-30YL

2 (stripe)

round burn in active
area; see Section 2.8“Unclamped inductive
switching EOS ofPSMN7R0-30YL” forfurther images

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Failure signature of electrical overstress on power MOSFETs
Device name

Cell pitch(μm)

PSMN8R5-100PSF

2.5 (stripe)

Round burn in active
area; see Section 2.9"Unclamped inductive
switching EOS ofPSMN8R5-100PSF" forfurther images.

BUK7Y3R0-40H

1.5 (stripe)

Round burn in active
area; see Section 2.10
"Unclamped inductive
switching EOS ofBUK7Y3R0-40H" forfurther images.

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1.3 Linear mode operation
1.3.1 EOS method
A Safe Operating Area (SOA) graph is included in all power MOSFET data sheets.
Outside the defined safe region, the power dissipated in the FET cannot be removed,
resulting in heating beyond the device capability and then device failure.
MOSFETs were taken and a fixed source-drain voltage applied. Current pulses ofdefined duration were applied and the current was increased until MOSFET failure wasobserved.
aaa-004864

103
ID
(A)

limit RDSON = VDS / ID

102

tp = 10 s

10

100 s

1

1 ms
10 ms
100 ms

DC
10-1
1

10

VDS (V)

102

Figure 4. Safe operating area; continuous and peak drain currents as a function of drainsource voltage

1.3.2 Fault condition simulated
Linear mode operation is common during device switching or clamped inductive
switching and is not a fault condition unless the SOA is exceeded. Linear mode EOS
simulates situations when a MOSFET is operated in Linear mode for too long. Thissituation can also occur if, when intending to turn the FET on, the gate signal voltage to
the FET is too low. This condition can also arise when intending to hold the FET in the
Off-state with high drain-source voltage. If the gate connection is lost, the gate voltage
capacitively rises and the same Linear mode fault condition occurs

1.3.3 Signature
The hottest location of the die is a failure site that is usually at central sites on thedie. The center of the die is where there is maximum current flow and reduced heatdissipation. The sites are often adjacent to wire bonds/clip bonds where current density ishigh, but not directly under the wire bond/clip bond as it provides a local heat sink.

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Failure signature of electrical overstress on power MOSFETs
Table 4. Examples of linear mode failure signature

Device name

Cell pitch(μm)

BUK7L06-34ARC

9 (hexagon)

Burns located in centerof die adjacent to wirebonds; see Section 2.11
“Linear mode EOS ofBUK7L06-34ARC” forfurther images

BUK9Y40-55B

4 (stripe)Burn adjacent to locationof clip bond in center ofdie; see Section 2.12
“Linear mode EOS ofBUK9Y40-55B” for further
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Failure signature of electrical overstress on power MOSFETs
Device name

Cell pitch(μm)

PSMN7R0-30YL

2 (stripe)

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Comments
Burn adjacent to locationof clip bond in center ofdie; see Section 2.13
“Linear mode EOS ofPSMN7R0-30YL” forfurther images

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Failure signature of electrical overstress on power MOSFETs
Device name

Cell pitch(μm)

PSMN8R5-100PSF

2.5 (stripe)Burn between sourcebond wires in active
area, see Section 2.18
"Linear mode EOS ofPSMN8R5-100PSF" forfurther images.

BUK7Y3R0-40H

1.5 (stripe)Burn close to the source
clip location in the active
area, see Section 2.19
"Linear mode EOS ofBUK7Y3R0-40H" forfurther images.

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Failure signature of electrical overstress on power MOSFETs

1.4 Over-current
1.4.1 EOS method
The maximum current-handling capability is specified on the data sheet for PowerMOSFETs. This capability is based on the current handling capability of wires or clips,
before which fusing will onset, combined with the ability to dissipate heat. Exceeding thisrating can result in catastrophic failure.
ID
IDM

drain current

peak drain current

VGS = 10 V; Tmb = 100 °C; see Figure 1

-

53

A

VGS = 10 V; Tmb = 25 °C; see Figure 1

-

76

A

tp ≤ 10 µs; pulsed; Tmb = 25 °C; see Figure 3

-

260

A
aaa-005071

Figure 5. Example of maximum current rating from the data sheet of PSMN7R0-30YL

1.4.2 Fault condition simulatedOver-current occurs if a FET is turned on with no element in the circuit to limit the current,
resulting in a supply voltage being applied fully over the drain-source terminals of the
FET. Typically this occurs if a load has been short-circuited. Alternatively if 2 FETs areoperating in a half-bridge, over-current can ensue if both are turned on together.

1.4.3 Signature
Failure site is initially where the current handling connections (wires or clips) meet thedie. Normally damage is extensive however in over-current conditions, and spreads overthe entire die surface with evidence of melted metallization and solder joints.
For wire-bonded packages, there is often evidence of fused wires. For clip-bonded
packages, die crack is commonly observed.

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Failure signature of electrical overstress on power MOSFETs
Table 5. Examples of over-current failure signature

Device name

Cell pitch(μm)

BUK7L06-34ARC

9 (hexagon)

Burns located in centerof die adjacent to wirebonds. Secondary
damage of remelted top
metal and solder die
attach; see Section 2.14
“Over-current EOS ofBUK7L06-34ARC” forfurther images

PSMN7R0-30YL

2 (stripe)Burn adjacent to locationof clip bond in center ofdie; see Section 2.15
“Over-current EOS ofPSMN7R0-30YL” forfurther images

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2

Appendices2.1 Human Body Model EOS of BUK9508-55A

Table 6. Human body model EOS

BUK9508-55A
Cell structure:
Package:
Die size:
EOS condition:

9 mm hexagons
TO-2205.5 mm x 4.5 mm
5 kV HBM pulse

Fails located in edge cells, distributed around edge of device

Figure 7. Sample image 4; after AI removal, close-up
Figure 6. Sample image 4; after AI removal

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Figure 8. Sample image 19; after AI removal

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Figure 9. Sample image 19; after TEOS removal, closeup

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2.2 Human Body Model EOS of BUK9Y40-55B
Table 7. Human body model EOS

BUK9Y40-55B
Cell structure:
Package:
Die size:
EOS condition:

4 μm stripe
LFPAK (clip bond)
2.5 mm x 1.35 mm
450 V to 650 V HBM
pulse

Fails located randomly over die with increased grouping in edge cells. Somefails subjected to ATE testing to create additional damage to highlight failsite

Figure 10. Sample image 5; after AI removals

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Figure 11. Sample image 5; after TEOS removal, closeup

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2.3 Human Body Model EOS of PSMN011-30YL
Table 8. Human body model EOS

PSMN011-30YL
Cell structure:
Package:
Die size:
EOS condition:

2 μm stripe
LFPAK (clip bond)
1.7 mm x 1.2 mm
200 V to 210 V HBM
pulseeFails located in edge cells

Figure 12. Sample image 2; after AI removal

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Figure 13. Sample image 4; after AI removal

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Failure signature of electrical overstress on power MOSFETs

Figure 14. Sample image 5; after AI removal

Figure 15. Sample image 10; after AI removal

2.4 Human Body Model EOS of PSMN8R5-100PSF
Table 9. Human body model EOS

PSMN8R5-100PSF
Cell structure:
Package:
Die size:
EOS condition:

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2.5 μm stripe
SOT78
4 mm x 2.67 mm
1.4 kV to 1.8 kV HBM
pulse

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Failure signature of electrical overstress on power MOSFETs

Figure 16. Device 4 after Al removal

Figure 17. Device 7 after Al removal

Figure 18. Device 5 after TEOS removal

Figure 19. Device 10 following decapsulation

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2.5 Human Body Model EOS of BUK7Y3R0-40H
Table 10. Human body model EOS

BUK7Y3R0-40H
Cell structure:
Package:
Die size:
EOS condition:

1.5 μm stripe
SOT6692.65 mm x 2.15 mm
2 kV HBM pulse

Figure 20. Device 2 after Al, barrier and TEOS etch

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Figure 21. Device 3 after Al, barrier and TEOS etch

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Failure signature of electrical overstress on power MOSFETs

Figure 22. Device 4 after Al, barrier and TEOS etch

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2.6 Unclamped Inductive Switching EOS of BUK7L06-34ARC
Table 11. Unclamped inductive switching EOS

BUK7L06-34ARC
Cell structure:
Package:
Die size:
EOS condition:

9 mm hexagons Small round burn marks, randomly distributed over active area, close to but notdirectly under wire-bonds
TO-220 (clipbond)
4.3 mm x 4.3 mm
0.2 mH; 80 A to
110 A

Figure 23. Sample image 1

Figure 24. Sample image 2

Figure 25. Sample image 3

Figure 26. Sample image 4

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2.7 Unclamped Inductive Switching EOS of BUK9Y40-55B
Table 12. Unclamped inductive switching EOS

BUK9Y40-55B
Cell structure:
Package:
Die size:
EOS condition:

4 μm stripe
LFPAK (clip bond)
2.5 mm x 1.35 mm
Red dots: 0.1 mH,
76 A to 80 A
Yellow dots: 15 mH, 7 A
to 9 A

Small round burn marks, randomly distributed over active area, close to
but not directly under clip bondFigure 27. Sample image 41; 0.1 mH

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Figure 28. Sample image 43; 0.1 mH

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Figure 29. Sample image 51; 15 mH

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Figure 30. Sample image 55; 15 mH

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2.8 Unclamped Inductive Switching EOS of PSMN7R0-30YL
Table 13. Unclamped inductive switching EOS

PSMN7R0-30YL
Cell structure:
Package:
Die size:
EOS condition:

2 μm stripe
LFPAK (clip bond)
2.5 mm x 1.35 mm
Red dots: 0.1 mH,
48 A to 51 A
Yellow dots: 3.5 mH,
16 A to 18 A

Small round burn marks, randomly distributed over active area, close to
but not directly under clip bondFigure 31. Sample image 6; 0.1 mH

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Figure 32. Sample image 8; 0.1 mH

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Figure 33. Sample image 18; 3.5 mH

Figure 34. Sample image 20; 3.5 mH

2.9 Unclamped Inductive Switching EOS of PSMN8R5-100PSF
Table 14. Unclamped inductive switching EOS

PSMN8R5-100PSF
Cell structure:
Package:
Die size:
EOS condition:

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2.5 μm stripe
SOT78
4 mm x 2.67 mm
Teal dot – 25 mH
Orange dot – 100 uH

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Figure 35. Device 1 upper (orange) hotspot

Figure 36. Device 1 lower (orange) hotspot

Figure 37. Device 4 upper (orange) hotspot

Figure 38. Device 4 lower (orange) hotspot

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Failure signature of electrical overstress on power MOSFETs

Figure 39. Device 6 (teal) hotspot

Figure 40. Device 7 (teal) hotspot

Figure 41. Device 8 (teal) hotspot

Figure 42. Device 9 (teal) hotspot

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2.10 Unclamped Inductive Switching EOS of BUK7Y3R0-40H
Table 15. Unclamped inductive switching EOS

BUK7Y3R0-40H
Cell structure:
Package:
Die size:

Figure 43. Device 1

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1.5 μm stripe
SOT6692.65 mm x 2.15 mm

Figure 44. Device 2

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Failure signature of electrical overstress on power MOSFETs

Figure 45. Device 3

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2.11 Linear mode EOS of BUK7L06-34ARC
Table 16. Linear mode EOS

BUK7L06-34ARC
Cell structure:
Package:
Die size:
EOS condition:

9 mm hexagon
TO-220 (clip bond)
4.3 mm x 4.3 mm
15 V, 3 A Burn marks located in middle ofthe die adjacent to wire bonds
30 V, 1.5 A Burn mark and location are
more discrete at 20 V, 1.5 A

Figure 46. Sample image 1: 15 V, 3 A

Figure 47. Sample image 2: 15 V, 3 A

Figure 48. Sample image 3: 15 V, 3 A

Figure 49. Sample image 4: 15 V, 3 A

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Failure signature of electrical overstress on power MOSFETs

Figure 50. Sample image 1: 30 V, 1.5 A

Figure 51. Sample image 2: 30 V, 1.5 A

Figure 52. Sample image 3: 30 V, 1.5 A

Figure 53. Sample image 4: 30 V, 1.5 A

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Failure signature of electrical overstress on power MOSFETs

2.12 Linear mode EOS of BUK9Y40-55B
Table 17. Linear mode EOS

BUK9Y40-55B
Cell structure:
Package:
Die size:
EOS condition:

4 μm stripe
LFPAK (clip bond)
2.5 mm x 1.35 mm
20 V, 3.5 A, 30 ms
20 V, 3 A, 60 ms
30 V, 1.4 A, 60 ms

Burn marks in center of die, adjacent but not directly under clip bond –can cause die cracking

Figure 54. Sample image 61; 20 V, 3.5 A, 30 ms

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Figure 55. Sample image 62; 20 V, 3.5 A, 30 ms

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Failure signature of electrical overstress on power MOSFETs

Figure 56. Sample image 63; 20 V, 3.5 A, 30 ms

Figure 57. Sample image 64; 20 V, 3.5 A, 30 ms

Figure 58. Sample image 66; 20 V, 3 A, 60 ms

Figure 59. Sample image 67; 20 V, 3 A, 60 ms

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Failure signature of electrical overstress on power MOSFETs

Figure 60. Sample image 68; 20 V, 3 A, 60 ms

Figure 61. Sample image 69; 20 V, 3 A, 60 ms

Figure 62. Sample image 71; 30 V, 1.4 A, 60 ms

Figure 63. Sample image 72; 30 V, 1.4 A, 60 ms

Figure 64. Sample image 73; 30 V, 1.4 A, 60 ms

Figure 65. Sample image 74; 30 V, 1.4 A, 60 ms

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2.13 Linear mode EOS of PSMN7R0-30YL
Table 18. Linear mode EOS

PSMN7R0-30YL
Cell structure:
Package:
Die size:
EOS condition:

2 μm stripe
LFPAK (clip bond)
2.3 mm x 1.35 mm
0.1 mH, 48 A to 51 A
3.5 mH, 16 A to 18 A

Burn marks in center of die, adjacent but not directly under clip bondFigure 66. Sample image 1; 15 V, 2.5 A, 100 ms

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Figure 67. Sample image 2; 15 V, 2.5 A, 100 ms

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Failure signature of electrical overstress on power MOSFETs

Figure 68. Sample image 4; 15 V, 2.5 A, 100 ms

Figure 70. Sample image 11; 15 V, 5 A, 1 ms

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Figure 69. Sample image 5; 15 V, 2.5 A, 100 ms

Figure 71. Sample image 12; 15 V, 5 A, 1 ms

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Failure signature of electrical overstress on power MOSFETs

Figure 73. Sample image 14; 15 V, 5 A, 1 ms
Figure 72. Sample image 13; 15 V, 5 A, 1 ms

2.14 Linear mode EOS of PSMN8R5-100PSF
Table 19. Linear mode EOS

PSMN8R5-100PSF
Cell structure:
Package:
Die size:
EOS condition:

AN11243

Application note

2.5 μm stripe
SOT78
4 mm x 2.67 mm
Teal dot – 50 V 10 ms
pulse length
Orange dot – 70 V, 1 ms
pulse length

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Failure signature of electrical overstress on power MOSFETs

Figure 74. Device 5 upper (orange) hotspot

Figure 75. Device 6 lower (orange) hotspot

Figure 76. Device 7 upper (orange) hotspot

Figure 77. Device 8 lower (orange) hotspot

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Failure signature of electrical overstress on power MOSFETs

Figure 78. Device 1 (teal) hotspot

Figure 79. Device 2 (teal) hotspot

Figure 80. Device 3 (teal) hotspot

Figure 81. Device 4 (teal) hotspot

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2.15 Linear mode EOS of BUK7Y3R0-40H
Table 20. Linear mode EOS

BUK7Y3R0-40H
Cell structure:
Package:
Die size:
EOS condition:

1.5 μm stripe
LFPAK (clip bond)
2.3 mm x 1.35 mm
0.1 mH, 48 A to 51 A
3.5 mH, 16 A to 18 A

Burn marks in center of die, adjacent but not directly under clip bondFigure 82. Sample image 1; 15 V, 2.5 A, 100 ms

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Figure 83. Sample image 2; 15 V, 2.5 A, 100 ms

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Failure signature of electrical overstress on power MOSFETs

Figure 84. Sample image 4; 15 V, 2.5 A, 100 ms

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Failure signature of electrical overstress on power MOSFETs

2.16 Over-current EOS of BUK7L06-34ARC
Table 21. Over-current EOS

BUK7L06-34ARC
Cell structure:
Package:
Die size:
EOS condition:

9 mm hexagon
TO-220 (clip bond)
4.3 mm x 4.3 mm
120 A

Extensive damage starting from die where wire bonds
meet die.
Secondary damage of reflowed solder and even fused
wires are visible

Figure 85. Sample image 1

Figure 86. Sample image 2

Figure 87. Sample image 3

Figure 88. Sample image 4

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Failure signature of electrical overstress on power MOSFETs

2.17 Over-current EOS of PSMN7R0-30YL
Table 22. Over-current EOS

PSMN7R0-30YL
Cell structure:
Package:
Die size:
EOS condition:

2 μm stripe
LFPAK (clip bond)
2.3 mm x 1.35 mm
35 A, 35 ms

Burn marks in center of die, adjacent but not directly under clip bondSome evidence of die-cracking.

Figure 89. Sample image 6

Figure 90. Sample image 7

Figure 91. Sample image 8

Figure 92. Sample image 9

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Failure signature of electrical overstress on power MOSFETs

3

Abbreviations
Table 23. Abbreviations

4

AcronymDescription

EOS

Electrical Overstress

ESD

ElectroStatic Discharge

UIS

Unclamped Inductive Switching

Revision history

Table 24. Revision history

Rev

Date

Description

02

20171219

superseeds Rev 01

Modifications:• Section ESD - Machine model removed• Additional EOS example added

01

20121029

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5

Legal information

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associated with their applications and products. Nexperia does not accept
any liability related to any default, damage, costs or problem which is basedon any weakness or default in the customer’s applications or products, orAN11243

Application notethe application or use by customer’s third party customer(s). Customer is
responsible for doing all necessary testing for the customer’s applications
and products using Nexperia products in order to avoid a default of theapplications and the products or of the application or use by customer’s third
party customer(s). Nexperia does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
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Failure signature of electrical overstress on power MOSFETs

TablesTab. 1.
Tab. 2.
Tab. 3.
Tab. 4.
Tab. 5.
Tab. 6.
Tab. 7.
Tab. 8.
Tab. 9.
Tab. 10.
Tab. 11.

Examples of Human Body Model ESD
failure signature .................................................4
UIS ruggedness test circuit and waveforms ...... 6
Examples of Unclamped Inductive Switching
failure signature .................................................7
Examples of linear mode failure signature ...... 10
Examples of over-current failure signature ...... 14
Human body model EOS ................................ 15
Human body model EOS ................................ 17
Human body model EOS ................................ 18
Human body model EOS ................................ 19
Human body model EOS ................................ 21
Unclamped inductive switching EOS ...............23

Tab. 12.
Tab. 13.
Tab. 14.
Tab. 15.
Tab. 16.
Tab. 17.
Tab. 18.
Tab. 19.
Tab. 20.
Tab. 21.
Tab. 22.
Tab. 23.
Tab. 24.

Unclamped inductive switching EOS ...............24
Unclamped inductive switching EOS ...............26
Unclamped inductive switching EOS ...............27
Unclamped inductive switching EOS ...............30
Linear mode EOS ........................................... 32
Linear mode EOS ........................................... 34
Linear mode EOS ........................................... 37
Linear mode EOS ........................................... 39
Linear mode EOS ........................................... 42
Over-current EOS ............................................44
Over-current EOS ............................................45
Abbreviations ...................................................46
Revision history ...............................................46

Fig. 34.
Fig. 35.
Fig. 36.
Fig. 37.
Fig. 38.
Fig. 39.
Fig. 40.
Fig. 41.
Fig. 42.
Fig. 43.
Fig. 44.
Fig. 45.
Fig. 46.
Fig. 47.
Fig. 48.
Fig. 49.
Fig. 50.
Fig. 51.
Fig. 52.
Fig. 53.
Fig. 54.
Fig. 55.
Fig. 56.
Fig. 57.
Fig. 58.
Fig. 59.
Fig. 60.
Fig. 61.
Fig. 62.
Fig. 63.
Fig. 64.
Fig. 65.
Fig. 66.
Fig. 67.
Fig. 68.
Fig. 69.
Fig. 70.
Fig. 71.
Fig. 72.

Sample image 20; 3.5 mH .............................. 27
Device 1 upper (orange) hotspot .....................28
Device 1 lower (orange) hotspot ..................... 28
Device 4 upper (orange) hotspot .....................28
Device 4 lower (orange) hotspot ..................... 28
Device 6 (teal) hotspot .................................... 29
Device 7 (teal) hotspot .................................... 29
Device 8 (teal) hotspot .................................... 29
Device 9 (teal) hotspot .................................... 29
Device 1 .......................................................... 30
Device 2 .......................................................... 30
Device 3 .......................................................... 31
Sample image 1: 15 V, 3 A .............................32
Sample image 2: 15 V, 3 A .............................32
Sample image 3: 15 V, 3 A .............................32
Sample image 4: 15 V, 3 A .............................32
Sample image 1: 30 V, 1.5 A .......................... 33
Sample image 2: 30 V, 1.5 A .......................... 33
Sample image 3: 30 V, 1.5 A .......................... 33
Sample image 4: 30 V, 1.5 A .......................... 33
Sample image 61; 20 V, 3.5 A, 30 ms .............34
Sample image 62; 20 V, 3.5 A, 30 ms .............34
Sample image 63; 20 V, 3.5 A, 30 ms .............35
Sample image 64; 20 V, 3.5 A, 30 ms .............35
Sample image 66; 20 V, 3 A, 60 ms ............... 35
Sample image 67; 20 V, 3 A, 60 ms ............... 35
Sample image 68; 20 V, 3 A, 60 ms ............... 36
Sample image 69; 20 V, 3 A, 60 ms ............... 36
Sample image 71; 30 V, 1.4 A, 60 ms .............36
Sample image 72; 30 V, 1.4 A, 60 ms .............36
Sample image 73; 30 V, 1.4 A, 60 ms .............36
Sample image 74; 30 V, 1.4 A, 60 ms .............36
Sample image 1; 15 V, 2.5 A, 100 ms .............37
Sample image 2; 15 V, 2.5 A, 100 ms .............37
Sample image 4; 15 V, 2.5 A, 100 ms .............38
Sample image 5; 15 V, 2.5 A, 100 ms .............38
Sample image 11; 15 V, 5 A, 1 ms ................. 38
Sample image 12; 15 V, 5 A, 1 ms ................. 38
Sample image 13; 15 V, 5 A, 1 ms ................. 39

FiguresFig. 1.
Fig. 2.
Fig. 3.
Fig. 4.
Fig. 5.
Fig. 6.
Fig. 7.
Fig. 8.
Fig. 9.
Fig. 10.
Fig. 11.
Fig. 12.
Fig. 13.
Fig. 14.
Fig. 15.
Fig. 16.
Fig. 17.
Fig. 18.
Fig. 19.
Fig. 20.
Fig. 21.
Fig. 22.
Fig. 23.
Fig. 24.
Fig. 25.
Fig. 26.
Fig. 27.
Fig. 28.
Fig. 29.
Fig. 30.
Fig. 31.
Fig. 32.
Fig. 33.

Typical circuit for Human body Model ESD
simulation .......................................................... 3
Circuit diagram for UIS ruggedness test ........... 6
Waveforms obtained from UIS test ................... 6
Safe operating area; continuous and peakdrain currents as a function of drain-source
voltage ............................................................... 9
Example of maximum current rating from thedata sheet of PSMN7R0-30YL ........................13
Sample image 4; after AI removal ...................15
Sample image 4; after AI removal, close-up .... 15
Sample image 19; after AI removal .................16
Sample image 19; after TEOS removal,
close-up ........................................................... 16
Sample image 5; after AI removals ................. 17
Sample image 5; after TEOS removal, closeup .................................................................... 17
Sample image 2; after AI removal ...................18
Sample image 4; after AI removal ...................18
Sample image 5; after AI removal ...................19
Sample image 10; after AI removal .................19
Device 4 after Al removal ................................20
Device 7 after Al removal ................................20
Device 5 after TEOS removal ......................... 20
Device 10 following decapsulation .................. 20
Device 2 after Al, barrier and TEOS etch ........ 21
Device 3 after Al, barrier and TEOS etch ........ 21
Device 4 after Al, barrier and TEOS etch ........ 22
Sample image 1 .............................................. 23
Sample image 2 .............................................. 23
Sample image 3 .............................................. 23
Sample image 4 .............................................. 23
Sample image 41; 0.1 mH .............................. 24
Sample image 43; 0.1 mH .............................. 24
Sample image 51; 15 mH ............................... 25
Sample image 55; 15 mH ............................... 25
Sample image 6; 0.1 mH ................................ 26
Sample image 8; 0.1 mH ................................ 26
Sample image 18; 3.5 mH .............................. 27

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Failure signature of electrical overstress on power MOSFETs
Fig. 73.
Fig. 74.
Fig. 75.
Fig. 76.
Fig. 77.
Fig. 78.
Fig. 79.
Fig. 80.
Fig. 81.
Fig. 82.

Sample image 14; 15 V, 5 A, 1 ms ................. 39
Device 5 upper (orange) hotspot .....................40
Device 6 lower (orange) hotspot ..................... 40
Device 7 upper (orange) hotspot .....................40
Device 8 lower (orange) hotspot ..................... 40
Device 1 (teal) hotspot .................................... 41
Device 2 (teal) hotspot .................................... 41
Device 3 (teal) hotspot .................................... 41
Device 4 (teal) hotspot .................................... 41
Sample image 1; 15 V, 2.5 A, 100 ms .............42

AN11243

Application noteFig. 83.
Fig. 84.
Fig. 85.
Fig. 86.
Fig. 87.
Fig. 88.
Fig. 89.
Fig. 90.
Fig. 91.
Fig. 92.

Sample image 2; 15 V, 2.5 A, 100 ms .............42
Sample image 4; 15 V, 2.5 A, 100 ms .............43
Sample image 1 .............................................. 44
Sample image 2 .............................................. 44
Sample image 3 .............................................. 44
Sample image 4 .............................................. 44
Sample image 6 .............................................. 45
Sample image 7 .............................................. 45
Sample image 8 .............................................. 45
Sample image 9 .............................................. 45

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Contents
1
1.1
1.1.1
1.1.2
1.1.3
1.2
1.2.1
1.2.2
1.2.3
1.3
1.3.1
1.3.2
1.3.3
1.4
1.4.1
1.4.2
1.4.3
2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
2.14
2.15
2.16
2.17
3
4
5

Introduction ......................................................... 2
ESD - Human body model ................................ 3
EOS method ...................................................... 3
Fault condition simulated ...................................3
Signature ............................................................3
Unclamped Inductive Switching (UIS)(Avalanche or Ruggedness) .............................. 6
EOS method ...................................................... 6
Fault condition simulated ...................................6
Signature ............................................................6
Linear mode operation .......................................9
EOS method ...................................................... 9
Fault condition simulated ...................................9
Signature ............................................................9Over-current .....................................................13
EOS method .................................................... 13
Fault condition simulated .................................13Signature ..........................................................13
Appendices ........................................................ 15
Human Body Model EOS of BUK9508-55A ..... 15
Human Body Model EOS of BUK9Y40-55B .....17
Human Body Model EOS of PSMN011-30YL ...18
Human
Body
Model
EOS
of
PSMN8R5-100PSF ..........................................19
Human Body Model EOS of BUK7Y3R0-40H ...21
Unclamped Inductive Switching EOS ofBUK7L06-34ARC .............................................23
Unclamped Inductive Switching EOS ofBUK9Y40-55B ..................................................24
Unclamped Inductive Switching EOS ofPSMN7R0-30YL .............................................. 26
Unclamped Inductive Switching EOS ofPSMN8R5-100PSF ..........................................27
Unclamped Inductive Switching EOS ofBUK7Y3R0-40H ...............................................30
Linear mode EOS of BUK7L06-34ARC ........... 32
Linear mode EOS of BUK9Y40-55B ................34
Linear mode EOS of PSMN7R0-30YL .............37
Linear mode EOS of PSMN8R5-100PSF ........ 39
Linear mode EOS of BUK7Y3R0-40H ............. 42
Over-current EOS of BUK7L06-34ARC ........... 44
Over-current EOS of PSMN7R0-30YL .............45
Abbreviations .................................................... 46
Revision history ................................................ 46
Legal information .............................................. 47

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Date of release: 19 December 2017
Document identifier: AN11243