LPC2101/02/03
Single-chip 16-bit/32-bit microcontrollers; 8 kB/16 kB/32 kB
flash with ISP/IAP, fast ports and 10-bit ADC
Rev. 03 — 7 October 2008

Product data sheet

1. General description
The LPC2101/02/03 microcontrollers are based on a 16-bit/32-bit ARM7TDMI-S CPU withreal-time emulation that combines the microcontroller with 8 kB, 16 kB or 32 kB of
embedded high-speed flash memory. A 128-bit wide memory interface and a uniqueaccelerator architecture enable 32-bit code execution at the maximum clock rate. For
critical performance in interrupt service routines and DSP algorithms, this increases
performance up to 30 % over Thumb mode. For critical code size applications, thealternative 16-bit Thumb mode reduces code by more than 30 % with minimal
performance penalty.
Due to their tiny size and low power consumption, the LPC2101/02/03 are ideal for
applications where miniaturization is a key requirement. A blend of serial communications
interfaces ranging from multiple UARTs, SPI to SSP and two I2C-buses, combined withon-chip SRAM of 2 kB/4 kB/8 kB, make these devices very well suited for communication
gateways and protocol converters. The superior performance also makes these devices
suitable for use as math coprocessors. Various 32-bit and 16-bit timers, an improved
10-bit ADC, PWM features through output match on all timers, and 32 fast GPIO lines withup to nine edge or level sensitive external interrupt pins make these microcontrollers
particularly suitable for industrial control and medical systems.

2. Features
2.1 Key featuresn 16-bit/32-bit ARM7TDMI-S microcontroller in tiny LQFP48 and HVQFN48 packages.
n 2 kB/4 kB/8 kB of on-chip static RAM and 8 kB/16 kB/32 kB of on-chip flash program
memory. 128-bit wide interface/accelerator enables high-speed 70 MHz operation.
n ISP/IAP via on-chip bootloader software. Single flash sector or full chip erase in
100 ms and programming of 256 bytes in 1 ms.
n EmbeddedICE-RT offers real-time debugging with the on-chip RealMonitor software.
n The 10-bit ADC provides eight analog inputs, with conversion times as low as 2.44 µs
per channel and dedicated result registers to minimize interrupt overhead.
n Two 32-bit timers/external event counters with combined seven capture and sevencompare channels.
n Two 16-bit timers/external event counters with combined three capture and sevencompare channels.
n Low power Real-Time Clock (RTC) with independent power and dedicated 32 kHz
clock input.
n Multiple serial interfaces including two UARTs (16C550), two Fast I2C-buses(400 kbit/s), SPI and SSP with buffering and variable data length capabilities.

LPC2101/02/03

NXP Semiconductors

Single-chip 16-bit/32-bit microcontrollers

n
n
n
n
n
n
n
n

Vectored interrupt controller with configurable priorities and vector addresses.
Up to thirty-two 5 V tolerant fast general purpose I/O pins.
Up to 13 edge or level sensitive external interrupt pins available.
70 MHz maximum CPU clock available from programmable on-chip PLL with apossible input frequency of 10 MHz to 25 MHz and a settling time of 100 µs.
On-chip integrated oscillator operates with an external crystal in the range from 1 MHz
to 25 MHz.
Power saving modes include Idle mode, Power-down mode with RTC active, andPower-down mode.
Individual enable/disable of peripheral functions as well as peripheral clock scaling foradditional power optimization.
Processor wake-up from Power-down mode via external interrupt or RTC.

3. Ordering information
Table 1.

Ordering information

Type number

Package
Name

Description

Version

LPC2101FBD48

LQFP48plastic low profile quad flat package; 48 leads;
body 7 × 7 × 1.4 mm

SOT313-2

LPC2102FBD48

LQFP48plastic low profile quad flat package; 48 leads;
body 7 × 7 × 1.4 mm

SOT313-2

LPC2103FBD48

LQFP48plastic low profile quad flat package; 48 leads;
body 7 × 7 × 1.4 mm

SOT313-2

LPC2102FHN48

HVQFN48plastic thermal enhanced very thin quad flat
package; no leads; 48 terminals; body
7 × 7 × 0.85 mm

SOT619-7

LPC2103FHN48

HVQFN48plastic thermal enhanced very thin quad flat
package; no leads; 48 terminals; body
7 × 7 × 0.85 mm

SOT619-7

3.1 Ordering options
Table 2.

Ordering options

Type number

Flash memory

RAM

ADC

Temperature
range (°C)

LPC2101FBD48

8 kB

2 kB

8 inputs−40 to +85

LPC2102FBD48

16 kB

4 kB

8 inputs−40 to +85

LPC2103FBD48

32 kB

8 kB

8 inputs−40 to +85

LPC2102FHN48

16 kB

4 kB

8 inputs−40 to +85

LPC2103FHN48

32 kB

8 kB

8 inputs−40 to +85

LPC2101_02_03_3

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4. Block diagram
TMS
TRST

LPC2101/2102/2103

P0[31:0]

HIGH SPEED
GENERALPURPOSE I/O

8 kB
BOOT ROMTDI
TCK

XTAL2 VDD(3V3) VDD(1V8)
XTAL1

TDO

RST

VSS

TEST/DEBUG
INTERFACE
PLL

ARM7TDMI-S
AHB BRIDGE

systemclock

ARM7 local bus

SYSTEM
FUNCTIONSVECTORED
INTERRUPTCONTROLLER

AMBA AHB(Advanced High-performance Bus)INTERNAL
SRAM
CONTROLLERMEMORYACCELERATOR

2 kB/4 kB/
8 kB SRAM

8 kB/16 kB/
32 kB FLASHAHB TO APBBRIDGE
APB (ARM
peripheral bus)

EINT2 toEINT0(1)

EXTERNAL
INTERRUPTS

I2C-BUS SERIALINTERFACES 0 AND 1

3 × CAP0(1)4 × CAP1(1)3 × CAP2(1)3 × MAT0(1)4 × MAT1(1)
3 × MAT2(1)
4 × MAT3(1)CAPTURE/COMPARE
EXTERNAL COUNTERTIMER 0/TIMER 1/
TIMER 2/TIMER 3

SPI AND SSPSERIAL INTERFACES

AD0[7:0]ADC

UART0/UART1

GENERALPURPOSE I/O

REAL-TIME CLOCK

WATCHDOGTIMERSYSTEM CONTROL

P0[31:0]

SCL0, SCL1(1)SDA0, SDA1(1)SCK0, SCK1(1)
MOSI0, MOSI1(1)
MISO0, MISO1(1)SSEL0, SSEL1(1)TXD0, TXD1(1)RXD0, RXD1(1)DSR1, CTS1,
RTS1, DTR1
DCD1, RI1
RTCX1
RTCX2
VBAT

002aab814(1) Pins shared with GPIO.

Fig 1.

Block diagram

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5. Pinning information

37 P0.12/DSR1/MAT1.0/AD0.5

38 P0.25/AD0.6

39 P0.26/AD0.7

40 VDD(3V3)

41 P0.13/DTR1/MAT1.1

42 VDDA

43 VSS

44 P0.14/DCD1/SCK1/EINT1

45 P0.15/RI1/EINT2

46 P0.16/EINT0/MAT0.2

47 P0.17/CAP1.2/SCL1

48 P0.18/CAP1.3/SDA1

5.1 Pinning

P0.19/MAT1.2/MISO1

1

36 P0.11/CTS1/CAP1.1/AD0.4

P0.20/MAT1.3/MOSI1

2

35 P0.10/RTS1/CAP1.0/AD0.3

P0.21/SSEL1/MAT3.0

334 P0.24/AD0.2

VBAT

4

33 P0.23/AD0.1

VDD(1V8)

5

RST

6

VSS

7

P0.27/TRST/CAP2.0

8

29 P0.8/TXD1/MAT2.1

P0.28/TMS/CAP2.1

9

28 P0.7/SSEL0/MAT2.0

32 P0.22/AD0.0

LPC2101FBD48
LPC2102FBD48
LPC2103FBD48

31 VSSA
30 P0.9/RXD1/MAT2.2

P0.29/TCK/CAP2.2 10

27 DBGSEL

Fig 2.

P0.6/MOSI0/CAP0.2 24

P0.5/MISO0/MAT0.1 23

P0.4/SCK0/CAP0.1 22002aab821

Pin configuration (LQFP48)

LPC2101_02_03_3

Product data sheet

P0.3/SDA0/MAT0.0 21

VSS 19RTCX1 20

VDD(3V3) 17
P0.2/SCL0/CAP0.0 18

P0.31/TDO 16

P0.30/TDI/MAT3.3 15

25 RTCX2
P0.1/RXD0/MAT3.2 14

26 RTCKXTAL2 12
P0.0/TXD0/MAT3.1 13

XTAL1 11

© NXP B.V. 2008. All rights reserved.

Rev. 03 — 7 October 2008

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37 P0.12/DSR1/MAT1.0/AD0.5

38 P0.25/AD0.6

40 VDD(3V3)
39 P0.26/AD0.7

41 P0.13/DTR1/MAT1.1

43 VSS
42 VDDA

44 P0.14/DCD1/SCK1/EINT1

45 P0.15/RI1/EINT2

46 P0.16/EINT0/MAT0.2

terminal 1
index area

47 P0.17/CAP1.2/SCL1

48 P0.18/CAP1.3/SDA1

Single-chip 16-bit/32-bit microcontrollers

P0.19/MAT1.2/MISO1

1

36 P0.11/CTS1/CAP1.1/AD0.4

P0.20/MAT1.3/MOSI1

2

35 P0.10/RTS1/CAP1.0/AD0.3

P0.21/SSEL1/MAT3.0

334 P0.24/AD0.2

VBAT

4

33 P0.23/AD0.1

VDD(1V8)

5

RST

6

VSS

7

P0.27/TRST/CAP2.0

8

29 P0.8/TXD1/MAT2.1

P0.28/TMS/CAP2.1

9

28 P0.7/SSEL0/MAT2.0

32 P0.22/AD0.0

LPC2102FHN48
LPC2103FHN48

31 VSSA
30 P0.9/RXD1/MAT2.2

P0.29/TCK/CAP2.2 10

27 DBGSEL

P0.6/MOSI0/CAP0.2 24

P0.5/MISO0/MAT0.1 23

P0.4/SCK0/CAP0.1 22

RTCX1 20

P0.3/SDA0/MAT0.0 21

VSS 19P0.2/SCL0/CAP0.0 18

VDD(3V3) 17

P0.31/TDO 16

P0.30/TDI/MAT3.3 15

25 RTCX2
P0.0/TXD0/MAT3.1 13

26 RTCKXTAL2 12
P0.1/RXD0/MAT3.2 14

XTAL1 11002aad918

Transparent top viewFig 3.

Pin configuration (HVQFN48)

LPC2101_02_03_3

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5.2 Pin description
Table 3.

Pin description

Symbol

Pin

P0.0 to P0.31

P0.0/TXD0/
MAT3.113[1]P0.1/RXD0/
MAT3.2

14[1]P0.2/SCL0/CAP0.018[2]P0.3/SDA0/
MAT0.021[2]P0.4/SCK0/CAP0.122[1]P0.5/MISO0/
MAT0.123[1]P0.6/MOSI0/
CAP0.224[1]P0.7/SSEL0/
MAT2.028[1]P0.8/TXD1/
MAT2.129[1]P0.9/RXD1/
MAT2.230[1]P0.10/RTS1/
CAP1.0/AD0.3

35[3]

Type

Description

I/O

Port 0: Port 0 is a 32-bit I/O port with individual direction controls for each bit.
A total of 31 pins of the Port 0 can be used as general purpose bidirectional
digital I/Os while P0.31 is an output only pin. The operation of port 0 pins
depends upon the pin function selected via the pin connect block.

I/O

P0.0 — General purpose input/output digital pin.

O

TXD0 — Transmitter output for UART0.

O

MAT3.1 — PWM output 1 for Timer 3.

I/O

P0.1 — General purpose input/output digital pin.

I

RXD0 — Receiver input for UART0.

O

MAT3.2 — PWM output 2 for Timer 3.

I/O

P0.2 — General purpose input/output digital pin. Output is open-drain.

I/O

SCL0 — I2C0 clock Input/output. Open-drain output (for I2C-bus compliance).

I

CAP0.0 — Capture input for Timer 0, channel 0.

I/O

P0.3 — General purpose input/output digital pin. Output is open-drain.

I/O

SDA0 — I2C0 data input/output. Open-drain output (for I2C-bus compliance).

O

MAT0.0 — PWM output for Timer 0, channel 0. Output is open-drain.

I/O

P0.4 — General purpose input/output digital pin.

I/O

SCK0 — Serial clock for SPI0. SPI clock output from master or input to slave.

I

CAP0.1 — Capture input for Timer 0, channel 1.

I/O

P0.5 — General purpose input/output digital pin.

I/O

MISO0 — Master In Slave Out for SPI0. Data input to SPI master or data
output from SPI slave.

O

MAT0.1 — PWM output for Timer 0, channel 1.

I/O

P0.6 — General purpose input/output digital pin.

I/O

MOSI0 — Master Out Slave In for SPI0. Data output from SPI master or data
input to SPI slave.

I

CAP0.2 — Capture input for Timer 0, channel 2.

I/O

P0.7 — General purpose input/output digital pin.

I

SSEL0 — Slave Select for SPI0. Selects the SPI interface as a slave.

O

MAT2.0 — PWM output for Timer 2, channel 0.

I/O

P0.8 — General purpose input/output digital pin.

O

TXD1 — Transmitter output for UART1.

O

MAT2.1 — PWM output for Timer 2, channel 1.

I/O

P0.9 — General purpose input/output digital pin.

I

RXD1 — Receiver input for UART1.

O

MAT2.2 — PWM output for Timer 2, channel 2.

I/O

P0.10 — General purpose input/output digital pin.

O

RTS1 — Request to Send output for UART1.

I

CAP1.0 — Capture input for Timer 1, channel 0.

I

AD0.3 — ADC 0, input 3.

LPC2101_02_03_3

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Table 3.

Pin description …continued

SymbolPin

Type

Description

P0.11/CTS1/
CAP1.1/AD0.4

36[3]

I/O

P0.11 — General purpose input/output digital pin.

I

CTS1 — Clear to Send input for UART1.

I

CAP1.1 — Capture input for Timer 1, channel 1.

I

AD0.4 — ADC 0, input 4.

I/O

P0.12 — General purpose input/output digital pin.

I

DSR1 — Data Set Ready input for UART1.

O

MAT1.0 — PWM output for Timer 1, channel 0.

I

AD0.5 — ADC 0, input 5.

I/O

P0.13 — General purpose input/output digital pin.

O

DTR1 — Data Terminal Ready output for UART1.

O

MAT1.1 — PWM output for Timer 1, channel 1.

P0.12/DSR1/
MAT1.0/AD0.537[3]P0.13/DTR1/
MAT1.141[1]P0.14/DCD1/
SCK1/EINT1

44[4]P0.15/RI1/
EINT2

45[4]

P0.16/EINT0/
MAT0.246[4]P0.17/CAP1.2/
SCL1

P0.18/CAP1.3/
SDA1

P0.19/MAT1.2/
MISO1

P0.20/MAT1.3/
MOSI1

P0.21/SSEL1/
MAT3.0

47[5]

48[5]

1[1]

2[1]

3[1]

I/O

P0.14 — General purpose input/output digital pin.

I

DCD1 — Data Carrier Detect input for UART1.

I/O

SCK1 — Serial Clock for SPI1. SPI clock output from master or input to slave.

I

EINT1 — External interrupt 1 input.

I/O

P0.15 — General purpose input/output digital pin.

I

RI1 — Ring Indicator input for UART1.

I

EINT2 — External interrupt 2 input.

I/O

P0.16 — General purpose input/output digital pin.

I

EINT0 — External interrupt 0 input.

O

MAT0.2 — PWM output for Timer 0, channel 2.

I/O

P0.17 — General purpose input/output digital pin. The output is notopen-drain.

I

CAP1.2 — Capture input for Timer 1, channel 2.

I/O

SCL1 — I2C1 clock Input/output. This pin is an open-drain output if I2C1
function is selected in the pin connect block.

I/O

P0.18 — General purpose input/output digital pin. The output is notopen-drain.

I

CAP1.3 — Capture input for Timer 1, channel 3.

I/O

SDA1 — I2C1 data Input/output. This pin is an open-drain output if I2C1
function is selected in the pin connect block.

I/O

P0.19 — General purpose input/output digital pin.

O

MAT1.2 — PWM output for Timer 1, channel 2.

I/O

MISO1 — Master In Slave Out for SSP. Data input to SSP master or data
output from SSP slave.

I/O

P0.20 — General purpose input/output digital pin.

O

MAT1.3 — PWM output for Timer 1, channel 3.

I/O

MOSI1 — Master Out Slave for SSP. Data output from SSP master or data
input to SSP slave.

I/O

P0.21 — General purpose input/output digital pin.

I

SSEL1 — Slave Select for SPI1. Selects the SPI interface as a slave.

O

MAT3.0 — PWM output for Timer 3, channel 0.

LPC2101_02_03_3

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Single-chip 16-bit/32-bit microcontrollers

Table 3.

Pin description …continued

SymbolPin

Type

Description

P0.22/AD0.0

32[3]

I/O

P0.22 — General purpose input/output digital pin.

I

AD0.0 — ADC 0, input 0.

P0.23/AD0.1

33[3]

I/O

P0.23 — General purpose input/output digital pin.

I

AD0.1 — ADC 0, input 1.

P0.24/AD0.2

34[3]

I/O

P0.24 — General purpose input/output digital pin.

I

AD0.2 — ADC 0, input 2.

P0.25/AD0.6

38[3]

I/O

P0.25 — General purpose input/output digital pin.

I

AD0.6 — ADC 0, input 6.

P0.26/AD0.7

39[3]

I/O

P0.26 — General purpose input/output digital pin.

I

AD0.7 — ADC 0, input 7.

P0.27/TRST/
CAP2.08[1]I/O

P0.27 — General purpose input/output digital pin.

I

TRST — Test Reset for JTAG interface.

I

CAP2.0 — Capture input for Timer 2, channel 0.

I/O

P0.28 — General purpose input/output digital pin.

I

TMS — Test Mode Select for JTAG interface.

I

CAP2.1 — Capture input for Timer 2, channel 1.

I/O

P0.29 — General purpose input/output digital pin.

I

TCK — Test Clock for JTAG interface. This clock must be slower than 1⁄6 of
the CPU clock (CCLK) for the JTAG interface to operate.

P0.28/TMS/
CAP2.19[1]P0.29/TCK/
CAP2.210[1]P0.30/TDI/
MAT3.315[1]P0.31/TDO

16[1]

I

CAP2.2 — Capture input for Timer 2, channel 2.

I/O

P0.30 — General purpose input/output digital pin.

I

TDI — Test Data In for JTAG interface.

O

MAT3.3 — PWM output 3 for Timer 3.

OP0.31 — General purpose output only digital pin.

O

TDO — Test Data Out for JTAG interface.

RTCX1

20[6]

I

Input to the RTC oscillator circuit.

RTCX2

25[6]

O

Output from the RTC oscillator circuit.

RTCK

26[6]

I/O

Returned test clock output: Extra signal added to the JTAG port. Assists
debugger synchronization when processor frequency varies. Bidirectional pin
with internal pull-up.

XTAL1

11

I

Input to the oscillator circuit and internal clock generator circuits.

XTAL2

12

O

Output from the oscillator amplifier.

DBGSEL

27

I

Debug select: When LOW, the part operates normally. When HIGH, debug
mode is entered. Input with internal pull-down.

RST

6

I

External reset input: A LOW on this pin resets the device, causing I/O ports
and peripherals to take on their default states and processor execution to
begin at address 0. TTL with hysteresis, 5 V tolerant.

VSS

7, 19, 43I

Ground: 0 V reference.

VSSA

31

I

Analog ground: 0 V reference. This should be nominally the same voltage
as VSS but should be isolated to minimize noise and error.

VDDA

42

I

Analog 3.3 V power supply: This should be nominally the same voltage as
VDD(3V3) but should be isolated to minimize noise and error. The level on thispin also provides a voltage reference level for the ADC.

LPC2101_02_03_3

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Table 3.

Pin description …continued

SymbolPin

Type

Description

VDD(1V8)5I

1.8 V core power supply: This is the power supply voltage for internal
circuitry and the on-chip PLL.

VDD(3V3)

17, 40I

3.3 V pad power supply: This is the power supply voltage for the I/O ports.

VBAT

4

I

RTC power supply: 3.3 V on this pin supplies the power to the RTC.

[1]

5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control.

[2]Open-drain 5 V tolerant digital I/O I2C-bus 400 kHz specification compatible pad. It requires external pull-up to provide an output
functionality. Open-drain configuration applies to ALL functions on that pin.

[3]

5 V tolerant pad providing digital I/O (with TTL levels and hysteresis and 10 ns slew rate control) and analog input function. If configured
for an input function, this pad utilizes built-in glitch filter that blocks pulses shorter than 3 ns. When configured as an ADC input, digital
section of the pad is disabled.

[4]

5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control. If configured for an input
function, this pad utilizes built-in glitch filter that blocks pulses shorter than 3 ns.

[5]Open-drain 5 V tolerant digital I/O I2C-bus 400 kHz specification compatible pad. It requires external pull-up to provide an output
functionality. Open-drain configuration applies only to I2C function on that pin.

[6]

Pad provides special analog functionality.

LPC2101_02_03_3

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6. Functional description
6.1 Architectural overview
The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers highperformance and very low power consumption. The ARM architecture is based on
Reduced Instruction Set Computer (RISC) principles, and the instruction set and related
decode mechanism are much simpler than those of microprogrammed Complex
Instruction Set Computers (CISC). This simplicity results in a high instruction throughput
and impressive real-time interrupt response from a small and cost-effective processor
core.
Pipeline techniques are employed so that all parts of the processing and memory systems
can operate continuously. Typically, while one instruction is being executed, its successor
is being decoded, and a third instruction is being fetched from memory.
The ARM7TDMI-S processor also employs a unique architectural strategy known as
Thumb, which makes it ideally suited to high-volume applications with memory
restrictions, or applications where code density is an issue.
The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the
ARM7TDMI-S processor has two instruction sets:• The standard 32-bit ARM set.
• A 16-bit Thumb set.
The Thumb set’s 16-bit instruction length allows it to approach twice the density ofstandard ARM code while retaining most of the ARM’s performance advantage over a
traditional 16-bit processor using 16-bit registers. This is possible because Thumb code
operates on the same 32-bit register set as ARM code.
Thumb code is able to provide up to 65 % of the code size of ARM, and 160 % of theperformance of an equivalent ARM processor connected to a 16-bit memory system.
The particular flash implementation in the LPC2101/02/03 allows for full speed execution
also in ARM mode. It is recommended to program performance critical and short code
sections in ARM mode. The impact on the overall code size will be minimal but the speed
can be increased by 30 % over Thumb mode.

6.2 On-chip flash program memory
The LPC2101/02/03 incorporate a 8 kB, 16 kB or 32 kB flash memory system
respectively. This memory may be used for both code and data storage. Programming of
the flash memory may be accomplished in several ways. It may be programmed in system
via the serial port. The application program may also erase and/or program the flash while
the application is running, allowing a great degree of flexibility for data storage field
firmware upgrades, etc. The entire flash memory is available for user code as thebootloader resides in a separate memory.
The LPC2101/02/03 flash memory provides a minimum of 100,000 erase/write cycles and20 years of data-retention memory.

LPC2101_02_03_3

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6.3 On-chip static RAM
On-chip static RAM may be used for code and/or data storage. The SRAM may beaccessed as 8-bits, 16-bits, and 32-bits. The LPC2101/02/03 provide 2 kB, 4 kB or 8 kB ofstatic RAM.

6.4 Memory map
The LPC2101/02/03 memory map incorporates several distinct regions, as shown in
Figure 4.
In addition, the CPU interrupt vectors may be re-mapped to allow them to reside in either
flash memory (the default) or on-chip static RAM. This is described in Section 6.17
“System control”.

4.0 GB

0xFFFF FFFFAHB PERIPHERALS
0xF000 0000

3.75 GBAPB PERIPHERALS
3.5 GB

0xE000 0000

3.0 GB

0xC000 0000

RESERVED ADDRESS SPACE

2.0 GB
BOOT BLOCK

0x8000 0000
0x7FFF FFFF
0x7FFF E000
0x7FFF DFFFRESERVED ADDRESS SPACE
0x4000 2000
0x4000 1FFF
8 kB ON-CHIP STATIC RAM (LPC2103)
4 kB ON-CHIP STATIC RAM (LPC2102)
2 kB ON-CHIP STATIC RAM (LPC2101)

0x4000 0800
0x4000 07FF
0x4000 0000

1.0 GBRESERVED ADDRESS SPACE
32 kB ON-CHIP NON-VOLATILE MEMORY(LPC2103)
16 kB ON-CHIP NON-VOLATILE MEMORY(LPC2102)

0.0 GB

0x4000 1000
0x4000 0FFF

8 kB ON-CHIP NON-VOLATILE MEMORY(LPC2101)0x0000 8000
0x0000 7FFF
0x0000 4000
0x0000 3FFF
0x0000 2000
0x0000 1FFF
0x0000 0000
002aab822

Fig 4.

LPC2101/02/03 memory map

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6.5 Interrupt controller
The VIC accepts all of the interrupt request inputs and categorizes them as FIQ, vectored
IRQ, and non-vectored IRQ as defined by programmable settings. The programmableassignment scheme means that priorities of interrupts from the various peripherals can be
dynamically assigned and adjusted.
FIQ has the highest priority. If more than one request is assigned to FIQ, the VIC
combines the requests to produce the FIQ signal to the ARM processor. The fastest
possible FIQ latency is achieved when only one request is classified as FIQ, because thenthe FIQ service routine does not need to branch into the interrupt service routine but canrun from the interrupt vector location. If more than one request is assigned to the FIQ
class, the FIQ service routine will read a word from the VIC that identifies which FIQ
source(s) is (are) requesting an interrupt.
Vectored IRQs have the middle priority. Sixteen of the interrupt requests can be assigned
to this category. Any of the interrupt requests can be assigned to any of the 16 vectored
IRQ slots, among which slot 0 has the highest priority and slot 15 has the lowest.
Non-vectored IRQs have the lowest priority.
The VIC combines the requests from all the vectored and non-vectored IRQs to produce
the IRQ signal to the ARM processor. The IRQ service routine can start by reading a
register from the VIC and jumping there. If any of the vectored IRQs are pending, the VIC
provides the address of the highest-priority requesting IRQs service routine, otherwise it
provides the address of a default routine that is shared by all the non-vectored IRQs. The
default routine can read another VIC register to see what IRQs are active.

6.5.1 Interrupt sources
Each peripheral device has one interrupt line connected to the Vectored Interrupt
Controller, but may have several internal interrupt flags. Individual interrupt flags may also
represent more than one interrupt source.

6.6 Pin connect block
The pin connect block allows selected pins of the microcontroller to have more than one
function. Configuration registers control the multiplexers to allow connection between thepin and the on chip peripherals. Peripherals should be connected to the appropriate pins
prior to being activated, and prior to any related interrupt(s) being enabled. Activity of any
enabled peripheral function that is not mapped to a related pin should be considered
undefined.
The pin control module with its pin select registers defines the functionality of the
microcontroller in a given hardware environment.
After reset all pins of Port 0 are configured as input with the following exceptions: If debug
is enabled, the JTAG pins will assume their JTAG functionality. The pins associated with
the I2C0 interface are open-drain.

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6.7 Fast general purpose parallel I/O
Device pins that are not connected to a specific peripheral function are controlled by the
GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate
registers allow setting or clearing any number of outputs simultaneously. The value of theoutput register may be read back, as well as the current state of the port pins.
LPC2101/02/03 introduce accelerated GPIO functions over prior LPC2000 devices:• GPIO registers are relocated to the ARM local bus for the fastest possible I/O timing.
• Mask registers allow treating sets of port bits as a group, leaving other bits
unchanged.

• All GPIO registers are byte addressable.
• Entire port value can be written in one instruction.
6.7.1 Features• Bit-level set and clear registers allow a single instruction set or clear of any number ofbits in one port.

• Direction control of individual bits.
• Separate control of output set and clear.
• All I/O default to inputs after reset.
6.8 10-bit ADC
The LPC2101/02/03 contain one ADC. It is a single 10-bit successive approximation ADC
with eight channels.

6.8.1 Features• Measurement range of 0 V to 3.3 V.
• Each converter capable of performing more than 400,000 10-bit samples per second.
• Burst conversion mode for single or multiple inputs.
• Optional conversion on transition on input pin or Timer Match signal.
• Every analog input has a dedicated result register to reduce interrupt overhead.
6.9 UARTs
The LPC2101/02/03 each contain two UARTs. In addition to standard transmit andreceive data lines, UART1 also provides a full modem control handshake interface.
Compared to previous LPC2000 microcontrollers, UARTs in LPC2101/02/03 include a
fractional baud rate generator for both UARTs. Standard baud rates such as 115200 canbe achieved with any crystal frequency above 2 MHz.

6.9.1 Features• 16 byte Receive and Transmit FIFOs.
• Register locations conform to 16C550 industry standard.
• Receiver FIFO trigger points at 1, 4, 8, and 14 bytes
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Single-chip 16-bit/32-bit microcontrollers• Built-in fractional baud rate generator covering wide range of baud rates without aneed for external crystals of particular values.

• Transmission FIFO control enables implementation of software (XON/XOFF) flow
control on both UARTs.

• UART1 is equipped with standard modem interface signals. This module also
provides full support for hardware flow control (auto-CTS/RTS).

6.10 I2C-bus serial I/O controllers
The LPC2101/02/03 each contain two I2C-bus controllers.
The I2C-bus is bidirectional, for inter-IC control using only two wires: a Serial Clock Line
(SCL), and a Serial Data Line (SDA). Each device is recognized by a unique address andcan operate as either a receiver-only device (e.g., LCD driver) or a transmitter with thecapability to both receive and send information such as serial memory. Transmitters
and/or receivers can operate in either master or slave mode, depending on whether thechip has to initiate a data transfer or is only addressed. The I2C-bus is a multi-master bus,
it can be controlled by more than one bus master connected to it.
The I2C-bus implemented in LPC2101/02/03 supports bit rates up to 400 kbit/s (Fast
I2C-bus).

6.10.1 Features• Compliant with standard I2C-bus interface.
• Easy to configure as Master, Slave, or Master/Slave.
• Programmable clocks allow versatile rate control.
• Bidirectional data transfer between masters and slaves.
• Multi-master bus (no central master).
• Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.

• Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.

• Serial clock synchronization can be used as a handshake mechanism to suspend andresume serial transfer.

• The I2C-bus can also be used for test and diagnostic purposes.
6.11 SPI serial I/O controller
The LPC2101/02/03 each contain one SPI controller. The SPI is a full duplex serialinterface, designed to handle multiple masters and slaves connected to a given bus. Onlya single master and a single slave can communicate on the interface during a given datatransfer. During a data transfer the master always sends 8 bits to 16 bits of data to theslave, and the slave always sends 8 bits to 16 bits of data to the master.

6.11.1 Features• Compliant with SPI specification.
• Synchronous, Serial, Full Duplex, Communication.
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Single-chip 16-bit/32-bit microcontrollers• Combined SPI master and slave.
• Maximum data bit rate of one eighth of the input clock rate.
6.12 SSP serial I/O controller
The LPC2101/02/03 each contain one SSP. The SSP controller is capable of operation on
a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on thebus. However, only a single master and a single slave can communicate on the bus during
a given data transfer. The SSP supports full duplex transfers, with data frames of 4 bits to
16 bits flowing from the master to the slave and from the slave to the master. Often only
one of these data streams carries meaningful data.

6.12.1 Features• Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National
Semiconductor’s Microwire buses• Synchronous serial communication• Master or slave operation• 8-frame FIFOs for both transmit and receive• Four bits to 16 bits per frame
6.13 General purpose 32-bit timers/external event counters
The Timer/Counter is designed to count cycles of the Peripheral Clock (PCLK) or an
externally supplied clock and optionally generate interrupts or perform other actions at
specified timer values, based on four match registers. It also includes four capture inputs
to trap the timer value when an input signal transitions, optionally generating an interrupt.
Multiple pins can be selected to perform a single capture or match function, providing anapplication with ‘or’ and ‘and’, as well as ‘broadcast’ functions among them.
The LPC2101/02/03 can count external events on one of the capture inputs if theminimum external pulse is equal or longer than a period of the PCLK. In this configuration,
unused capture lines can be selected as regular timer capture inputs or used as externalinterrupts.

6.13.1 Features• A 32-bit timer/counter with a programmable 32-bit prescaler.
• External event counter or timer operation.
• Four 32-bit capture channels per timer/counter that can take a snapshot of the timer
value when an input signal transitions. A capture event may also optionally generate
an interrupt.

• Four 32-bit match registers that allow:– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.

• Four external outputs per timer/counter corresponding to match registers, with thefollowing capabilities:– Set LOW on match.
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Single-chip 16-bit/32-bit microcontrollers– Set HIGH on match.
– Toggle on match.
– Do nothing on match.

6.14 General purpose 16-bit timers/external event counters
The Timer/Counter is designed to count cycles of the peripheral clock (PCLK) or an
externally supplied clock and optionally generate interrupts or perform other actions at
specified timer values, based on four match registers. It also includes three capture inputs
to trap the timer value when an input signal transitions, optionally generating an interrupt.
Multiple pins can be selected to perform a single capture or match function, providing anapplication with ‘or’ and ‘and’, as well as ‘broadcast’ functions among them.
The LPC2101/02/03 can count external events on one of the capture inputs if theminimum external pulse is equal or longer than a period of the PCLK. In this configuration,
unused capture lines can be selected as regular timer capture inputs or used as externalinterrupts.

6.14.1 Features• Two 16-bit timer/counters with a programmable 16-bit prescaler.
• External event counter or timer operation.
• Three 16-bit capture channels that can take a snapshot of the timer value when an
input signal transitions. A capture event may also optionally generate an interrupt.

• Four 16-bit match registers that allow:– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.

• Four external outputs per timer/counter corresponding to match registers, with thefollowing capabilities:– Set LOW on match.
– Set HIGH on match.
– Toggle on match.
– Do nothing on match.

6.15 Watchdog timer
The purpose of the watchdog is to reset the microcontroller within a reasonable amount oftime if it enters an erroneous state. When enabled, the watchdog will generate a system
reset if the user program fails to ‘feed’ (or reload) the watchdog within a predeterminedamount of time.

6.15.1 Features• Internally resets chip if not periodically reloaded.
• Debug mode.
• Enabled by software but requires a hardware reset or a watchdog reset/interrupt to bedisabled.
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Single-chip 16-bit/32-bit microcontrollers• Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.
• Flag to indicate watchdog reset.
• Programmable 32-bit timer with internal pre-scaler.
• Selectable time period from (TPCLK × 256 × 4) to (TPCLK × 232 × 4) in multiples of
TPCLK × 4.

6.16 Real-time clock
The Real-Time Clock (RTC) is designed to provide a set of counters to measure time
when normal or idle operating mode is selected. The RTC has been designed to use little
power, making it suitable for battery powered systems where the CPU is not running
continuously (Idle mode).

6.16.1 Features• Measures the passage of time to maintain a calendar and clock.
• Ultra-low power design to support battery powered systems.
• Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and Day
of Year.

• Can use either the RTC dedicated 32 kHz oscillator input or clock derived from theexternal crystal/oscillator input at XTAL1. The programmable reference clock divider
allows fine adjustment of the RTC.

• Dedicated power supply pin can be connected to a battery or the main 3.3 V.
6.17 System control
6.17.1 Crystal oscillator
On-chip integrated oscillator operates with external crystal in range of 1 MHz to 25 MHz.
The oscillator output frequency is called fosc and the ARM processor clock frequency isreferred to as CCLK for purposes of rate equations, etc. fosc and CCLK are the same value
unless the PLL is running and connected. Refer to Section 6.17.2 “PLL” for additional
information.

6.17.2 PLL
The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input
frequency is multiplied up into the range of 10 MHz to 70 MHz with a Current Controlled
Oscillator (CCO). The multiplier can be an integer value from 1 to 32 (in practice, themultiplier value cannot be higher than 6 on this family of microcontrollers due to the upper
frequency limit of the CPU). The CCO operates in the range of 156 MHz to 320 MHz, so
there is an additional divider in the loop to keep the CCO within its frequency range while
the PLL is providing the desired output frequency. The output divider may be set to divideby 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2,
it is insured that the PLL output has a 50 % duty cycle. The PLL is turned off andbypassed following a chip reset and may be enabled by software. The program must
configure and activate the PLL, wait for the PLL to lock, and then connect to the PLL as aclock source. The PLL settling time is 100 µs.

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6.17.3 Reset and wake-up timer
Reset has two sources on the LPC2101/02/03: the RST pin and watchdog reset. The RST
pin is a Schmitt trigger input pin with an additional glitch filter. Assertion of chip reset byany source starts the wake-up timer (see wake-up timer description below), causing theinternal chip reset to remain asserted until the external reset is de-asserted, the oscillator
is running, a fixed number of clocks have passed, and the on-chip flash controller has
completed its initialization.
When the internal reset is removed, the processor begins executing at address 0, which is
the reset vector. At that point, all of the processor and peripheral registers have been
initialized to predetermined reset values.
The wake-up timer ensures that the oscillator and other analog functions required for chip
operation are fully functional before the processor is allowed to execute instructions. Thisis important at power on, all types of reset, and whenever any of the aforementionedfunctions are turned off for any reason. Since the oscillator and other functions are turned
off during Power-down mode, any wake-up of the processor from Power-down mode
makes use of the wake-up timer.
The wake-up timer monitors the crystal oscillator as the means of checking whether it issafe to begin code execution. When power is applied to the chip, or some event caused
the chip to exit Power-down mode, some time is required for the oscillator to produce a
signal of sufficient amplitude to drive the clock logic. The amount of time depends on
many factors, including the rate of VDD ramp (in the case of power on), the type of crystal
and its electrical characteristics (if a quartz crystal is used), as well as any other external
circuitry (e.g., capacitors), and the characteristics of the oscillator itself under the existing
ambient conditions.

6.17.4 Code security
This feature of the LPC2101/02/03 allow an application to control whether it can be
debugged or protected from observation.
If after reset on-chip bootloader detects a valid checksum in flash and reads 0x8765 4321
from address 0x1FC in flash, debugging will be disabled and thus the code in flash will beprotected from observation. Once debugging is disabled, it can only be enabled by
performing a full chip erase using the ISP.

6.17.5 External interrupt inputs
The LPC2101/02/03 include up to three edge or level sensitive external interrupt inputs as
selectable pin functions. When the pins are combined, external events can be processedas three independent interrupt signals. The external interrupt inputs can optionally be
used to wake-up the processor from Power-down mode.
Additionally all 10 capture input pins can also be used as external interrupts without theoption to wake the device up from Power-down mode.

6.17.6 Memory mapping control
The memory mapping control alters the mapping of the interrupt vectors that appear
beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the on-chip
flash memory, or to the on-chip static RAM. This allows code running in different memory
spaces to have control of the interrupts.
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6.17.7 Power control
The LPC2101/02/03 supports two reduced power modes: Idle mode and Power-downmode.
In Idle mode, execution of instructions is suspended until either a reset or interrupt occurs.
Peripheral functions continue operation during Idle mode and may generate interrupts tocause the processor to resume execution. Idle mode eliminates power used by theprocessor itself, memory systems and related controllers, and internal buses.
In Power-down mode, the oscillator is shut down and the chip receives no internal clocks.
The processor state and registers, peripheral registers, and internal SRAM values arepreserved throughout Power-down mode and the logic levels of chip output pins remain
static. The Power-down mode can be terminated and normal operation resumed by either
a reset or certain specific interrupts that are able to function without clocks. Since all
dynamic operation of the chip is suspended, Power-down mode reduces chip power
consumption to nearly zero.
Selecting an external 32 kHz clock instead of the PCLK as a clock-source for the on-chip
RTC will enable the microcontroller to have the RTC active during Power-down mode.
Power-down current is increased with RTC active. However, it is significantly lower than in
Idle mode.
A power control for peripherals feature allows individual peripherals to be turned off if they
are not needed in the application, resulting in additional power savings during active andIdle mode.

6.17.8 APB
The APB divider determines the relationship between the processor clock (CCLK) and theclock used by peripheral devices (PCLK). The APB divider serves two purposes. The firstis to provide peripherals with the desired PCLK via APB so that they can operate at the
speed chosen for the ARM processor. In order to achieve this, the APB may be slowed
down to 1⁄2 to 1⁄4 of the processor clock rate. Because the APB must work properly at
power-up (and its timing cannot be altered if it does not work since the APB divider control
registers reside on the APB), the default condition at reset is for the APB to run at 1⁄4 of theprocessor clock rate. The second purpose of the APB divider is to allow power savings
when an application does not require any peripherals to run at the full processor rate.
Because the APB divider is connected to the PLL output, the PLL remains active (if it was
running) during Idle mode.

6.18 Emulation and debugging
The LPC2101/02/03 support emulation and debugging via a JTAG serial port.

6.18.1 EmbeddedICE
Standard ARM EmbeddedICE logic provides on-chip debug support. The debugging of
the target system requires a host computer running the debugger software and an
EmbeddedICE protocol convertor. The EmbeddedICE protocol converter converts the
remote debug protocol commands to the JTAG data needed to access the ARM core.
The ARM core has a debug communication channel function built-in. The debug
communication channel allows a program running on the target to communicate with thehost debugger or another separate host without stopping the program flow or even
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entering the debug state. The debug communication channel is accessed as aco-processor 14 by the program running on the ARM7TDMI-S core. The debug
communication channel allows the JTAG port to be used for sending and receiving data
without affecting the normal program flow. The debug communication channel data andcontrol registers are mapped in to addresses in the EmbeddedICE logic. The JTAG clock(TCK) must be slower than 1⁄6 of the CPU clock (CCLK) for the JTAG interface to operate.

6.18.2 RealMonitor
RealMonitor is a configurable software module, developed by ARM Inc., which enables
real time debug. It is a lightweight debug monitor that runs in the background while users
debug their foreground application. It communicates with the host using the DCC, which ispresent in the EmbeddedICE logic. The LPC2101/02/03 contain a specific configuration of
RealMonitor software programmed into the on-chip boot ROM memory.

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7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).[1]Symbol

Min

Max

Unit

supply voltage (1.8 V)

[2]

−0.5

+2.5

V

VDD(3V3)

supply voltage (3.3 V)

[3]

−0.5

+3.6

V

VDDA

analog 3.3 V pad supply voltage

−0.5

+4.6

V

Vi(VBAT)

input voltage on pin VBATVDD(1V8)

Parameter

Conditions

−0.5

+4.6

V

[4]

−0.5

+5.1

V

5 V tolerant I/O
pins[5][6]

−0.5

+6.0

V

other I/O pins

[5]

−0.5

VDD + 0.5[7] V

supply current[8]-100[9]

ISS

ground current

[10]

-

100[9]

mA

Tstg

storage temperature

[11]

−65

+150

°C

Ptot(pack)total power dissipation (per package)

based on packageheat transfer, notdevice power
consumption

-

1.5

W

Vesd

electrostatic discharge voltage

Human Body
Model (HBM)

−4000

+4000

V[12]

Machine Model
(MM)

−200

+200

V[13]

Charged Device
Model (CDM)

−800

+800

V[14]

for the RTC

analog input voltage

VIA

input voltage

VI

IDD

mA

[1]

The following applies to the limiting values:a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive
static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.
b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unlessotherwise noted.

[2]Core and internal rail.

[3]

External rail.

[4]

On ADC related pins.

[5]

Including voltage on outputs in 3-state mode.

[6]

Only valid when the VDD(3V3) supply voltage is present.

[7]

Not to exceed 4.6 V.

[8]Per supply pin.

[9]

The peak current is limited to 25 times the corresponding maximum current.

[10] Per ground pin.
[11] Dependent on package type.
[12] Performed per AEC-Q100-002.
[13] Performed per AEC-Q100-003.
[14] Performed per AEC-Q100-011.

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8. Static characteristics
Table 5.
Static characteristics
Tamb= −40 °C to +85 °C for commercial applications, unless otherwise specified.
SymbolParameter

Conditions

Min

Typ[1]

Max

Unit

1.65

1.8

1.95

V

supply voltage (1.8 V)[2]

VDD(3V3)

supply voltage (3.3 V)

[3]

3.0

3.3

3.6

V

VDDA

analog 3.3 V pad supply
voltage

3.0

3.3

3.6

V

Vi(VBAT)

input voltage on pin VBAT

2.0[4]

3.3

3.6

V

VDD(1V8)

Standard port pins, RST, RTCKIIL

LOW-level input current

VI = 0 V; no pull-up

-

-

3

µA

IIH

HIGH-level input current

VI = VDD(3V3); no pull-down

-

-

3

µA

IOZ

OFF-state output current

VO = 0 V, VO = VDD(3V3); no
pull-up/down

-

-

3

µA

IlatchI/O latch-up current−(0.5VDD(3V3)) < VI <(1.5VDD(3V3));

-

-

100

mA

VI

input voltage

0

-

5.5

V

0

-

VDD(3V3)

V

Tj < 125 °C

VOoutput voltage

pin configured to provide a
digital function[5][6][7]

output active

VIH

HIGH-level input voltage

2.0

-

-

V

VIL

LOW-level input voltage

-

-

0.8

V

Vhys

hysteresis voltage

-

0.4

-

V

VDD(3V3) −
0.4

-

-

V

VOH

HIGH-level output voltage

IOH = −4 mA

[8]

VOL

LOW-level output voltage

IOL = −4 mA

[8]

-

-

0.4

V

HIGH-level output current

VOH = VDD(3V3) − 0.4 V

[8]

−4

-

-

mA

VOL = 0.4 V

[8]

4

-

-

mA

-

-

−45

mA

-

-

50

mA

IOH
IOL

LOW-level output current

IOHS

HIGH-level short-circuit
output current

VOH = 0 V

[9]

IOLS

LOW-level short-circuit
output current

VOL = VDDA

[9]

Ipd

pull-down current

VI = 5 V[10]Ipupull-up current

VI = 0 V

10

50

150

µA

−15

−50

−85

µA

0

0

0

µA

executed from flash; allperipherals enabled via
PCONP register but notconfigured to run;
CCLK = 70 MHz

-

41

70

mA

VDD(1V8) = 1.8 V; Tamb = 25 °C

-

2.5

25

µA

VDD(1V8) = 1.8 V; Tamb = 85 °C

-

35

105

µA

[11]

VDD(3V3) < VI < 5 V[10]IDD(act)

active mode supply
current

VDD(1V8) = 1.8 V; Tamb = 25 °C;
code

while(1){}IDD(pd)Power-down mode supply
current

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Table 5.
Static characteristics …continued
Tamb= −40 °C to +85 °C for commercial applications, unless otherwise specified.
Min

Typ[1]Max

Unit

VDD(1V8) = 1.8 V;
Vi(VBAT) = 2.5 V

-

7

12

µA

VDD(1V8) = 1.8 V;
Vi(VBAT) = 3.0 V

-

8

12

µA

-

10

15

µA
V

SymbolParameter

IBATpdPower-down mode battery RTC clock = 32 kHz
supply current[12](from RTCX pins);
Tamb = 25 °C;

IBATact

active mode battery
supply current[12]Conditions

CCLK = 70 MHz;PCLK = 17.5 MHz;PCLK enabled to RTCK;
RTC clock = 32 kHz(from RTCX pins);
Tamb = 25 °C;
VDD(1V8) = 1.8 V;
Vi(VBAT) = 3.0 V

I2C-bus pins
VIH

HIGH-level input voltage

0.7VDD(3V3) --VIL

LOW-level input voltage--

0.3VDD(3V3) V

Vhys

hysteresis voltage-

0.5VDD(3V3) -

V

-

-

V

[8]

VOL

LOW-level output voltage

IOLS = 3 mA

ILI

input leakage current[13]0.4VI = VDD(3V3)

-

2

4

µA

VI = 5 V

-

10

22

µA

Oscillator pins
Vi(XTAL1)

input voltage on pin XTAL1

0

-

1.8

V

Vo(XTAL2)

output voltage on pin
XTAL2

0

-

1.8

V

Vi(RTCX1)

input voltage on pin
RTCX1

0

-

1.8

V

Vo(RTCX2) output voltage on pin
RTCX2

0

-

1.8

V

[1]

Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages.

[2]

Core and internal rail.

[3]

External rail.

[4]

The RTC typically fails when Vi(VBAT) drops below 1.6 V.

[5]Including voltage on outputs in 3-state mode.

[6]

VDD(3V3) supply voltages must be present.

[7]

3-state outputs go into 3-state mode when VDD(3V3) is grounded.

[8]

Accounts for 100 mV voltage drop in all supply lines.

[9]

Allowed as long as the current limit does not exceed the maximum current allowed by the device.

[10] Minimum condition for VI = 4.5 V, maximum condition for VI = 5.5 V.
[11] Applies to P0.25:16.
[12] On pin VBAT.
[13] To VSS.

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Single-chip 16-bit/32-bit microcontrollers

Table 6.
ADC static characteristics
VDDA = 2.5 V to 3.6 V; Tamb = −40 °C to +85 °C unless otherwise specified. ADC frequency 4.5 MHz.
SymbolParameter

Conditions

VIA

analog input voltage

0

Cia

analog input capacitance[1][2][3]-integral non-linearity[1][4]

EO

offset error[1][5]

EG

gain error[1][6]

ET

absolute error[1][7][1]

Conditions: VSSA = 0 V, VDDA = 3.3 V.

[2]

The ADC is monotonic, there are no missing codes.

[3]

The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 5.

[4]

The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after
appropriate adjustment of gain and offset errors. See Figure 5.

[5]

The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits theideal curve. See Figure 5.

[6]

The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset
error, and the straight line which fits the ideal transfer curve. See Figure 5.

[7]

The absolute error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated ADC
and the ideal transfer curve. See Figure 5.

differential linearity errorED
EL(adj)Min

LPC2101_02_03_3

Product data sheet

Typ

Max

Unit

-

VDDA

V

-

1

pF

-

±1

LSB

-

-

±2

LSB

-

-

±3

LSB

-

-

±0.5

%

-

-

±4

LSB

© NXP B.V. 2008. All rights reserved.

Rev. 03 — 7 October 2008

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LPC2101/02/03

NXP Semiconductors

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offset
error
EO

gain
error
EG

1023

1022

1021

1020

1019

1018

(2)

7
code
out

(1)

6

5
(5)

4
(4)

3
(3)

2

1 LSB
(ideal)

1

0
1

2

3

4

5

offset error
EO

6

7

1018

1019

1020

1021

1022

1023

1024

VIA (LSBideal)
1 LSB =VDDA − VSSA
1024

002aac046(1) Example of an actual transfer curve.
(2) The ideal transfer curve.
(3) Differential linearity error (ED).
(4) Integral non-linearity (EL(adj)).
(5) Center of a step of the actual transfer curve.

Fig 5.

ADC conversion characteristics

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9. Dynamic characteristics
Table 7.
Dynamic characteristics
Tamb = 0 °C to 70 °C for commercial applications, −40 °C to +85 °C for industrial applications, VDD(1V8), VDD(3V3) over
specified ranges[1].
SymbolParameter

Conditions

Min

Typ[2]Max

Unit

External clock
fosc

oscillator frequency

10

-

25

MHz

Tcy(clk)

clock cycle time

40

-

100

ns

tCHCX

clock HIGH timeTcy(clk) × 0.4

-

-

ns

tCLCX

clock LOW timeTcy(clk) × 0.4

-

-

ns

tCLCH

clock rise time

-

-

5

ns

tCHCL

clock fall time

-

-

5

ns

Port pins (except P0.2 and P0.3)
tr(o)output rise time

-

10

-

ns

tf(o)

output fall time

-

10

-

ns

20 + 0.1 × Cb[3]

-

-

ns

I2C-bus pins (P0.2 and P0.3)
output fall timetf(o)VIH to VIL[1]Parameters are valid over operating temperature range unless otherwise specified.

[2]

Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages.

[3]

Bus capacitance Cb in pF, from 10 pF to 400 pF.

LPC2101_02_03_3

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10. Package outline
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm

SOT313-2

c

y
X

36

25

A

37

24

ZE

e

E HE

A A2

(A 3)

A1

w M

θ

bp

pin 1 index

Lp
L

13

48
1

detail X

12
ZD

e

v M A

w M

bp
D

B

HD

v M B

0

2.5

5 mm

scale
DIMENSIONS (mm are the original dimensions)
UNIT

A
max.

A1

A2

A3

bp

c

D (1)

E (1)

e

HD

HE

L

Lp

v

w

y

Z D (1) Z E (1)

θ

mm

1.6

0.20
0.05

1.45
1.35

0.25

0.27
0.17

0.18
0.12

7.1
6.9

7.1
6.9

0.5

9.15
8.85

9.15
8.85

1

0.75
0.45

0.2

0.12

0.1

0.95
0.55

7
o
0

0.95
0.55

o

Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

Fig 6.

REFERENCESOUTLINE
VERSION

IEC

JEDEC

SOT313-2

136E05MS-026JEITAEUROPEAN
PROJECTION

ISSUE DATE
00-01-19
03-02-25

Package outline SOT313-2 (LQFP48)

LPC2101_02_03_3

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Rev. 03 — 7 October 2008

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LPC2101/02/03

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Single-chip 16-bit/32-bit microcontrollers

HVQFN48: plastic thermal enhanced very thin quad flat package; no leads;
48 terminals; body 7 x 7 x 0.85 mm
D

SOT619-7AB

terminal 1
index area

E

A
A1
c

detail X

e1

C

e

y1 C

v M C A B
w M C

b

1/2 e
13

y

24

L

25

12

e

e2

Eh
1/2 e

1

36

terminal 1
index area

48

37
X

Dh
0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)
UNIT

A(1)
max

A1

b

c

D (1)

Dh

E (1)

Eh

e

e1

e2

L

v

w

y

y1

mm

1

0.05
0.00

0.30
0.18

0.2

7.1
6.9

3.45
3.15

7.1
6.9

3.45
3.15

0.5

5.5

5.5

0.5
0.3

0.1

0.05

0.05

0.1

Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included

Fig 7.

REFERENCESOUTLINE
VERSION

IEC

JEDEC

JEITA

SOT619-7---

MO-220---EUROPEAN
PROJECTION

ISSUE DATE
05-10-24
05-10-25

Package outline SOT619-7 (HVQFN48)

LPC2101_02_03_3

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Rev. 03 — 7 October 200828 of 32

LPC2101/02/03

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Single-chip 16-bit/32-bit microcontrollers

11. Abbreviations
Table 8.

Acronym list

AcronymDescription

ADC

Analog-to-Digital Converter

AMBA

Advanced Microcontroller Bus Architecture

APB

Advanced Peripheral Bus

DCC

Debug Communications Channel

DSP

Digital Signal Processor

FIFOFirst In, First Out

FIQ

Fast Interrupt Request

GPIO

General Purpose Input/Output

IAP

In-Application Programming

IRQ

Interrupt Request

ISP

In-System Programming

PLL

Phase-Locked Loop

PWM

Pulse Width Modulator

SPI

Serial Peripheral Interface

SRAM

Static Random Access Memory

SSI

Synchronous Serial Interface

SSP

Synchronous Serial Port

TTL

Transistor-Transistor Logic

UART

Universal Asynchronous Receiver/Transmitter

VIC

Vectored Interrupt Controller

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Rev. 03 — 7 October 2008

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LPC2101/02/03

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Single-chip 16-bit/32-bit microcontrollers

12. Revision history
Table 9.

Revision history

Document ID

Release date

Data sheet status

ChangenoticeSupersedes

LPC2101_02_03_3

20081007

Product data sheet-

LPC2101_02_03_2

Modifications:• Updated data sheet status to Product data sheet.
• Table 1 and Table 2: added LPC2102FHN48 and LPC2103FHN48.
• Table 1, Table 2, Table 3 and related figures: removed LPC2103FA44.
• Table 3: updated pad descriptions.
• Table 3: updated description of pin 47, SCL1.
• Table 3: updated description of pins VDDA and VDD(1V8).
• Table 4: changed storage temperature range from −40 °C/125 °C to −65 °C/150 °C.
• Table 5: added or modified values for IDD(act), IDD(pd), IBATpd, IBATact.
• Table 5: removed “CCLK = 10 MHz” and associated values for IDD(act).
• Section 5: added Figure 3.
• Section 10: added Figure 7.

LPC2101_02_03_2

20071218

Preliminary data sheet-

LPC2101_02_03_1

LPC2101_02_03_1

20060118

Preliminary data sheet--

LPC2101_02_03_3

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LPC2101/02/03

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13. Legal information
13.1 Data sheet status
Document status[1][2]Product status[3]Definition

Objective [short] data sheet

Development

This document contains data from the objective specification for product development.

Preliminary [short] data sheet

Qualification

This document contains data from the preliminary specification.

Product [short] data sheet

Production

This document contains the product specification.

[1]

Please consult the most recently issued document before initiating or completing a design.

[2]

The term ‘short data sheet’ is explained in section “Definitions”.

[3]

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.

13.2 Definitions
Draft — The document is a draft version only. The content is still underinternal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences ofuse of such information.
Short data sheet — A short data sheet is an extract from a full data sheetwith the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed andfull information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, thefull data sheet shall prevail.

13.3 Disclaimers
General — Information in this document is believed to be accurate andreliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of suchinformation and shall have no liability for the consequences of use of suchinformation.
Right to make changes — NXP Semiconductors reserves the right to makechanges to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications andtherefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of theseproducts are for illustrative purposes only. NXP Semiconductors makes norepresentation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are soldsubject to the general terms and conditions of commercial sale, as publishedat http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unlessexplicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and suchterms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.

13.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.

14. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com

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Single-chip 16-bit/32-bit microcontrollers

15. Contents
1
2
2.1
3
3.1
4
5
5.1
5.2
6
6.1
6.2
6.3
6.4
6.5
6.5.1
6.6
6.7
6.7.1
6.8
6.8.1
6.9
6.9.1
6.10
6.10.1
6.11
6.11.1
6.12
6.12.1
6.13
6.13.1
6.14
6.14.1
6.15
6.15.1
6.16
6.16.1
6.17
6.17.1
6.17.2
6.17.36.17.46.17.5
6.17.6
6.17.7

General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Key features . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6
Functional description . . . . . . . . . . . . . . . . . . 10
Architectural overview. . . . . . . . . . . . . . . . . . . 10
On-chip flash program memory . . . . . . . . . . . 10
On-chip static RAM. . . . . . . . . . . . . . . . . . . . . 11
Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 11
Interrupt controller . . . . . . . . . . . . . . . . . . . . . 12
Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 12
Pin connect block . . . . . . . . . . . . . . . . . . . . . . 12
Fast general purpose parallel I/O . . . . . . . . . . 13
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
UARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
I2C-bus serial I/O controllers. . . . . . . . . . . . . . 14
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
SPI serial I/O controller. . . . . . . . . . . . . . . . . . 14
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
SSP serial I/O controller . . . . . . . . . . . . . . . . . 15
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
General purpose 32-bit timers/external
event counters . . . . . . . . . . . . . . . . . . . . . . . . 15
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
General purpose 16-bit timers/external
event counters . . . . . . . . . . . . . . . . . . . . . . . . 16
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . 16
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Real-time clock . . . . . . . . . . . . . . . . . . . . . . . . 17
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
System control . . . . . . . . . . . . . . . . . . . . . . . . 17
Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . 17
PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Reset and wake-up timer . . . . . . . . . . . . . . . . 18
Code security . . . . . . . . . . . . . . . . . . . . . . . . . 18
External interrupt inputs . . . . . . . . . . . . . . . . . 18
Memory mapping control . . . . . . . . . . . . . . . . 18
Power control . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.17.86.18
6.18.1
6.18.2
7
8
9
10
11
12
13
13.1
13.2
13.3
13.4
14
15

APB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Emulation and debugging. . . . . . . . . . . . . . . .
EmbeddedICE . . . . . . . . . . . . . . . . . . . . . . . .
RealMonitor . . . . . . . . . . . . . . . . . . . . . . . . . .
Limiting values . . . . . . . . . . . . . . . . . . . . . . . .
Static characteristics . . . . . . . . . . . . . . . . . . .
Dynamic characteristics . . . . . . . . . . . . . . . . .
Package outline . . . . . . . . . . . . . . . . . . . . . . . .
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . .
Revision history . . . . . . . . . . . . . . . . . . . . . . .
Legal information . . . . . . . . . . . . . . . . . . . . . .
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information . . . . . . . . . . . . . . . . . . . .
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

19
19
19
20
21
22
26
27
29
30
31
31
31
31
31
31
32

Please be aware that important notices concerning this document and the product(s)described herein, have been included in section ‘Legal information’.

© NXP B.V. 2008.

All rights reserved.

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 7 October 2008
Document identifier: LPC2101_02_03_3