NBM7100A; NBM7100B

Coin cell battery life booster with adaptive power
optimizationRev. 2 — 2 August 2024

1. General description

Product data sheet

2. Features and benefits

The NBM7100A/B is a battery energy management
device designed to maximize usable capacity from
non-rechargeable, primary batteries when used in lowvoltage, low-power applications requiring burst current
loads. The devices overcome voltage drop and battery
life limitations associated with extracting high pulse
currents (Fig. 1) from lithium primary batteries suchas 3 V lithium manganese dioxide (LiMnO2) coin cells.
which are commonly used in wireless, low-power IoT
sensor applications.
The NBM7100A/B contains two stages of highefficiency DC-DC conversion and an intelligent learningalgorithm. The first stage DC-DC conversion transfersenergy from the lithium battery at a low constantcurrent to a capacitive storage element. Once charged,
a second DC-DC conversion cycle utilizes this stored
energy to supply a regulated voltage with high pulse
load current capability on the VDH output pin. The
battery is never directly subjected to large load pulse
currents, resulting in a longer, more predictable battery
lifetime.
The proprietary learning algorithm monitors the energy
used during repetitive load pulse cycles and optimizes
first stage DC-DC conversion to minimize the residual
charge in the storage capacitor.
A serial interface allows a microcontroller to change
default configuration settings and read-back system
information.
Table 1. Related devices
Type
Bus
Auto
numberinterface
start

Pulse
ILOAD

NBM7100A

I²C

Yes≥ 200 mA

NBM7100B

SPI

No≥ 200 mA

•
•
•
•
•
•
•
•
•

Programmable constant battery load current: 2 mA
to 16 mA
Protection against battery voltage dips (Brown-out)
Pulse output current: > 200 mA
Low ripple regulated programmable output voltage,
VDH: 1.8 V to 3.6 V
Ultra-low standby current: 20 nA (typ)Peak conversion efficiency up to 93% with adaptive
optimization
Integrated fuel gauge
Small 16 pin lead-free package(SOT763-1/DHVQFN16;
2.5 mm × 3.5 mm × 0.85 mm)
Specified from -40 °C to +85 °C

3. Applications•••

Battery powered wireless microcontroller
applications (IoT): Bluetooth®, LoRaWAN®,
Sigfox™, LTE-M, NB-IoT, Zigbee, etc.
Industrial: temperature, occupancy, e-metering,
electronic shelf label, asset tracking, irrigation
monitoring
Consumer/wearable: location tags, heart ratemonitor, blood glucose meter, remote controls, key
fobs

LX1

LX2

CAP
VDHS

VBT

ILOAD
100 mACSTORE

L

TX/RX

VDH

TX/RX

VDP
NBM7100ASENSO R

SCL

10 mA

SDA

Sleep

RDY
ADR

1-100 µA

TSTtime (ms)Fig. 1.

START

IoT pulsed load profile

VSS

VSS P

aaa-036448

RF MCU

Temperature
Pre ssure
Flow
Occupancy
etc...

aaa-036457

Fig. 2.

Simplified Application

NBM7100A; NBM7100B

Nexperia

Coin cell battery life booster with adaptive power optimization

4. Ordering information
Table 2. Ordering information
Type number
Package
NBM7100ABQNBM7100BBQ

Temperature range

Name

Description

Version-40 °C to +85 °C

DHVQFN16 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 16 terminals;
body 2.5 × 3.5 × 0.85 mm

SOT763-1

5. Marking
Table 3. Marking codes
Type number

Marking code

NBM7100ABQ

M7100A

NBM7100BBQ

M7100B

6. Pin configuration and description
6.1. Pin configuration

1

terminal 1
index area

16 SCLK

16 SCLSDA
1

terminal 1
index area

SDO

NBM7100BBQ package
SOT763-1 (DHVQFN16)

NBM7100ABQ package
SOT763-1 (DHVQFN16)TST

215 VDPTST

2

15 VDPRDY

3

14 VDHRDY

3

14 VDHADR

4

13 LX1CSN

4

13 LX1START

512 VSSP

SDI

5

12 VSSP

VSS

6

11

LX2

VSS

6

VBT

7

10 CAP

VBT

7Transparent top view

11

LX2

9
VDHS

10 CAP
89
VDHS

aaa-036497

VSS(1)

n.c.

8
n.c.

VSS(1)

aaa-036498

Transparent top view(1) Ground pad should be connected to the analog ground pin VSS.
Fig. 3.

Pin configuration SOT763-1 (DHVQFN16)

NBM7100
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NBM7100A; NBM7100B

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Coin cell battery life booster with adaptive power optimization

6.2. Pin description
Table 4. Pin description
SymbolPin

NBM7100A NBM7100B

1

SDA

SDO

I/O

Description

I (A) O (B) serial data I/O (I²C) / serial data out MISO (SPI)

2

TST

I

factory test only, tie to VSS

3

RDY

O

status output

4

ADR

CSN

I

address pin (I²C) / chip select (SPI; active LOW)

5

START

SDI

I

start pin (active high) [1] / serial data in MOSI (SPI)

6

VSS

PWR

analog ground, should be connected to VSSP on PCB

7

VBT

PWR

input supply to the IC (typically from a battery).

8

n.c.

n.a.

not internally connected. connect to PCB pad.

9

VDHS

I

sense input

10

CAP

PWR

11

LX2

-

12

VSSP

PWR

13

LX1

-

inductor connection 1

14

VDH

O

regulated supply output (see output configuration)

15

VDP

O

permanent supply output (see output configuration)

I

serial clock input SCL (I²C); SCLK (SPI)-

this is not a supply pin; should be soldered to PCB and connected to VSS
externally; used to heat-sink the device to the circuit board.

16

SCL
Pad

[1]

SCLK

storage capacitor
inductor connection 2
power (switching) ground, should be connected to VSS on PCB

Connect to VSS with a pull-down resistor when not actively driving.

NBM7100
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NBM7100A; NBM7100B

Nexperia

Coin cell battery life booster with adaptive power optimization

7. Specifications
7.1. Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter

Conditions

Min

Max

Unit

-0.3

6.0

V

VVBT

supply voltage pin VBT

VI

input voltage

VDHS
NBM7100A: ADR, START, SCL, SDA
NBM7100B: CSN, SDI, SDO and SCLK

-0.3

VVDP+0.3 V

VOoutput voltage

VDH and VDP

-0.3

6.0

V

VCAP

storage voltage pin CAP

-0.3

12.0

V

IO

output current

-

500

mA

Tamb

ambient temperature

-40

+85

°C

Tstg

storage temperature

-65

+150

°C

VDH, LX1, LX2 and CAP

7.2. ESD ratings
Table 6. ESD ratings

VESD

electrostatic discharge voltage

Value

Unit

HBM: ANSI/ESDA/JEDEC JS-001 Class 2± 2000V

CDM: ANSI/ESDA/JEDEC JS-002 Class C2a

± 500

V

7.3. Thermal information
Table 7. Thermal information
Thermal resistance according to JEDEC51-5 and -7
SymbolParameter

SOT763-1

Unit

RΘJA

junction-to-ambient thermal resistance

82

K/W

RΘJC(TOP)junction-to-case (top) thermal resistance

50

K/W

ΨJT

junction-to-top characterization parameter

7K/W

7.4. Recommended operating conditions
Table 8. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter

Conditions

Min

Max

Unit

VVBT

supply voltage

VBT pin

2.4

3.6

V

VI/O

input/output voltage

RDY
NBM7100A: SCL, SDA, START, ADR
NBM7100B: CSN, SDI, SDO, SCLK

0

VVDP

V

IO

output current

VDP pin (Standby state)

0

5

mA

IO

output current

VDH pin (Active state)

0

200

mA

NBM7100
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NBM7100A; NBM7100B

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Coin cell battery life booster with adaptive power optimization

7.5. Recommended components
Table 9. Recommended components
Nominal component values, not including tolerance or derating factors. [1]Symbol Parameter

Min

Nom

Max

Unit

CVBT

capacitance on VBT

1

2

-

μF

CVDP

capacitance on VDP

1

2

-

μF

CVDH

capacitance on VDH

22

-

-

μF

CCAP

energy storage capacitance

4.7

-

470

μF

L [2]

inductance between LX1 and LX2-

15 [3]

-

μH

[1]
[2]
[3]

Nominal component values shown - does not include derating factors.
Ensure inductor saturation current, ISAT, rating > 1 A.
Assume ± 20% tolerance.

7.6. Electrical characteristics
Table 10. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); typical values are at 25°C (unlessotherwise noted).
VVBT = 3.0 V; CVBT = 1 µF; CVDP = 1 µF; CVDH = 22 µF; L = 15 µH; unless otherwise specified.
SymbolParameter

Conditions

Tamb = −40 °C to +85 °C

Unit

Min

Typ

Max

Input
VPOR

power on reset Device starting voltage for operation at battery
insertTA = -40 ºC

1.3

-

2.7

V

VPOR

power on reset Device starting voltage for operation at battery
insert25 ºC ≤ TA ≤ 85 ºC

1.3

-

2.3

V

εV

absolute
voltage error

-

-

5

%

charge current Charge state, ich = 000b

1.4

2.0

2.6

mA

Charge state, ich = 001b

2.8

4.0

5.2

mA

Charge state, ich = 010b

5.6

8.0

10.4

mA

Charge state, ich = 011b

11.2

16

20.75

mA

Charge state, ich = 100b (VCAP > VVBT)

35

50

85

mA

Conversion efficiency (Charge state)

-

80

-

%

VFIX, VCAP(max), VSET, and VEW

Capacitor charge current from VBT pin
ICH

EFFch

converter
efficiency

Supply current from VBT pin
IQ_STBquiescentcurrent

Standby state

-

20

-

nA

IQ_CM

quiescentcurrent

Continuous mode, CSTORE charged

-

1.8

-

µA

IQ_ACT

quiescentcurrent

Active state, ILOAD = 10 mA

-

0.4

-

mA

NBM7100
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Coin cell battery life booster with adaptive power optimization
SymbolParameter

Conditions

Tamb = −40 °C to +85 °C

Unit

Min

Typ

Max

VDH output
VO

-

VSET

-

V

ΔVDH(ΔIO) VDH load
regulation

output voltage Active state, IVDH > 1 mA
see Fig. 12

-

±1

-

%

EFFACT

converter
efficiency

Active state

-

90

-

%

RVDP

outputresistancepin VDP

-

20

30

Ω

No load detection
No load detection is active in the Auto mode only. It set the device into standby state when the load current is below thethreshold INL for more the TNL.
The detected load detection current is the sum of currents in the VDP and VDH outputs.
INL

thresholdcurrent

No load Current threshold

TNL

detection time No load Detection time

-

100

-

µA

-

20

-

ms

Table 11. Logic inputs/outputs (SDA/SDO), RDY, (ADR/CSN), (START/SDI) and (SCL/SCLK) pins
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); typical values are at 25°C (unlessotherwise noted).
VVBT = 3.0 V; CVBT = 1 µF; CVDP = 1 µF; CVDH = 22 µF; L = 15 µH; unless otherwise specified.
SymbolParameter

Conditions

Tamb = −40 °C to +85 °C

Unit

Min

Typ

Max
-

II

input current

-

0

VIL

LOW-level
input voltage

-

-

VIH

HIGH-level
input voltage

0.7 x VVDP

-

-

V

VH

hysteresis
voltage

0.16V x VDP

-

-

V

VOL

LOW-level
IOL = 3 mA
output voltage

-

-

VOH

HIGH-level
IOH = 2 mA
output voltage[1][1] 0.7 x VVDP-

μA

0.3 x VVDP V

0.2 x VVDP V-

V

For NBM7100A open drain output at SDA pin excluded.

NBM7100
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Coin cell battery life booster with adaptive power optimization

7.7. Dynamic characteristics
Table 12. Timing requirements and switching characteristics of logic inputs/outputs I²C (NBM7100A, SDA and SCL
pins
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); typical values are at 25°C (unlessotherwise noted).
VVBT = 2.4 V to 3.6 V; CVBT = 1 µF; CVDP = 1 µF; CVDH = 22 µF; L = 15 µH. At recommended operating conditions; voltages
are referenced to GND (ground = 0 V); for waveforms see Fig. 28; for test circuit see Fig. 31.
SymbolParameter

Conditions

Tamb = -40 °C to +85 °C
Min

Typ

Max

Unit

Timing requirements
fclk

clock frequency

SCL

-

-

1

MHz

tlow

low time

SCL

500

-

-

ns

thigh

high time

SCL

260

-

-

ns

tsu;sta

set-up time

START; for repeated START condition

260

-

-

ns

th;stahold time

START; for repeated START condition

260

-

-

ns

tsu;stoset-up time

STOP; for STOP condition

260

-

-

ns

tbuf

bus free time

between STOP and START

500

-

-

ns

tsu;dat

set-up time

SDA

50

-

-

ns

th;dathold time

SDA

0

-

-

ns

tr

rise time

SCL

-

-

120

ns

tr

rise time

SDA

-

-

120

ns

tf

fall time

SCL

-

-

120

ns

tf

fall time

SDA

-

-

120

ns

Switching characteristics
tvd_datvalid time, data

SDA; in Tx mode

-

-

450

ns

tvd_ack

valid time,
acknowledge

SDA; in Tx mode

-

-

450

ns

tof

output fall timein Tx mode, CL = 10 pF, 70% - 30%

-

-

120

ns

NBM7100
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Coin cell battery life booster with adaptive power optimization
Table 13. Timing requirements and switching characteristics of logic inputs/outputs SPI (NBM7100B, SDO, CSN, SDI
and SCLK pins
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); typical values are at 25°C (unlessotherwise noted).
VVBT = 2.4 V to 3.6 V; CVBT = 1 µF; CVDP = 1 µF; CVDH = 22 µF; L = 15 µH. At recommended operating conditions; voltages
are referenced to GND (ground = 0 V); for waveforms see Fig. 29 and Fig. 30; for test circuit see Fig. 32.
SymbolParameter

Conditions

Tamb = -40 °C to +85 °C
Min

Typ

Max

Unit

Timing requirements
fclk

clock frequency

SCLK

-

-

4

MHz

tclk

period time

SCLK; see Fig. 29(5)and Fig. 30

(5)

250

-

-

ns

tCSH

reset time(6)

CSN; see Fig. 29

(9)

200

-

-

ns

tlow

low time

SCLK

100

-

-

ns

thigh

high time

SCLK

tsu

setup time

CSN; see Fig. 29thhold timetsu

setup timeth

hold timeand Fig. 30

100

-

-

ns

and Fig. 30

(3)

100

-

-

ns

and Fig. 30

(4)

0

-

-

ns

and Fig. 30

(1)

10

-

-

ns

and Fig. 30

(2)

20

-

-

ns

(3)

CSN; see Fig. 29(4)

SDI; see Fig. 29(1)

SDI; see Fig. 29(2)

Switching characteristics
tdav

valid time

SDO; after neg clock edge, incl 3-state/(6)
active delay; see Fig. 30

-

-

100

ns

trel

release time

SDO; after CSN transition to high;(7)
see Fig. 30

-

-

100

ns

tf

fall time

SDO; CL = 10 pF, 70% - 30%

-

-

10

ns

tr

rise time

SDO; CL = 10 pF, 30% - 70%

-

-

10

ns

Table 14. Switching characteristics of RDY output
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); typical values are at 25°C (unlessotherwise noted).
VVBT = VVDP = 2.4 V to 3.6 V; CVBT = 1 µF; CVDP = 1 µF; CVDH = 22 µF; L = 15 µH. At recommended operating conditions;voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 31 and Fig. 32.
SymbolParameter

Conditions

Min

Typ

Max

tr

rise time

RDY; CL = 10 pF, 30% - 70%

-

-

10

ns

tf

fall time

RDY; CL = 10 pF, 70% - 30%

-

-

10

ns

tW(EW)

EW pulse width

RDY; Early Warning active

2.6

-

6.5

μs

NBM7100
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Product data sheet

Tamb = -40 °C to +85 °C

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Rev. 2 — 2 August 2024

Unit

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Coin cell battery life booster with adaptive power optimization

7.8. Typical characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); typical values are at 25°C (unlessotherwise noted).
VVBT = 3.0 V; CVBT = 1 µF; CVDP = 1 µF; CVDH = 22 µF; L = 15 µH; unless otherwise specified.
aaa-036472

60
IQ_STB
(nA)
48

(3)
(2)

36

(2)

860

12
0
-40

Fig. 4.

(3)

1190

(1)

24

aaa-036473

1850
IQ_CM
(nA)
1520

530

-15

10

35

60
Tamb (°C)

(1)

200
-40

85

-15

(1): VVBT = 2.4 V(1): VVBT = 2.4 V(2): VVBT = 3.0 V(2): VVBT = 3.0 V(3): VVBT = 3.6 V(3): VVBT = 3.6 V

IQ_STB versus temperature

Fig. 5.

1035

60
Tamb (°C)

85

IQ_CM versus temperature
aaa-036474

450
IQ_ACT
(uA)
420

(3)

390
(2)

360
330
300
-40

(1)

-15

10

35

60
Tamb (°C)85(1): VVBT = 2.4 V(2): VVBT = 3.0 V(3): VVBT = 3.6 V
Fig. 6.

IQ_ACT versus temperature

NBM7100
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Coin cell battery life booster with adaptive power optimization
aaa-036475

100
Efficiency
(%)
90

80

(8)
(12)
(3)
(7)
(11)
(2)
(6)
(4)
(10)
(1)
(5)
(9)

70

60

50

1

102
ILOAD (mA)

10

VCAP = 4 V
VVDH = VSET:

1.8 V

2.4 V

3.0 V

3.6 V

-40 ºC

(1)

(2)

(3)

(4)

25 ºC

(5)

(6)

(7)

(8)

85 ºC

(9)

(10)

(11)

(12)

Fig. 7.

Active state efficiency versus load current, VCAP = 4 V
aaa-036476

100
Efficiency
(%)
88

88

76

76

(1)
(5)
(9)
(2)
(6)
(10)
(3)
(7)
(11)
(4)
(8)
(12)

64

52

40

aaa-036477

100
Efficiency
(%)

1

10

(1)
(5)
(9)
(2)
(6)
(10)
(3)
(7)
(11)
(4)
(8)
(12)

64

52

40

102
ILOAD (mA)

1

10

VVDH = VSET = 1.8 V

102
ILOAD (mA)

VVDH = VSET = 2.4 V

VCAP :

4.0 V

6.0 V

8.0 V

11.0 V

VCAP :

4.0 V

6.0 V

8.0 V

11.0 V-40 ºC

(1)

(2)

(3)

(4)

-40 ºC

(1)

(2)

(3)

(4)

25 ºC

(5)

(6)

(7)

(8)

25 ºC

(5)

(6)

(7)

(8)

85 ºC

(9)

(10)

(11)

(12)

85 ºC

(9)

(10)

(11)

(12)

Active state efficiency versus load current,
VVDH = VSET = 1.8 V

Fig. 9.

Fig. 8.

NBM7100
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Product data sheet

Active state efficiency versus load current,
VVDH = VSET = 2.4 V

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NBM7100A; NBM7100B

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Coin cell battery life booster with adaptive power optimization
aaa-036478

100
Efficiency
(%)
88

88

76

76

(1)
(5)
(9)
(2)
(6)
(10)
(3)
(7)
(11)
(4)
(8)
(12)

64

52

40

aaa-036479

100
Efficiency
(%)

1

(5)
(9)
(2)
(6)
(10)
(1)
(3)
(7)
(11)
(4)
(8)
(12)

64

52

40

102
ILOAD (mA)

10

1

102
ILOAD (mA)

10

VVDH = VSET = 3.0 V

VVDH = VSET = 3.6 V

VCAP :

4.0 V

6.0 V

8.0 V

11.0 V

VCAP :

4.0 V

6.0 V

8.0 V

11.0 V-40 ºC

(1)

(2)

(3)

(4)

-40 ºC

(1)

(2)

(3)

(4)

25 ºC

(5)

(6)

(7)

(8)

25 ºC

(5)

(6)

(7)

(8)

85 ºC

(9)

(10)

(11)

(12)

85 ºC

(9)

(10)

(11)

(12)

Fig. 10. Active state efficiency versus load current,
VVDH = VSET = 3.0 V

Fig. 11. Active state efficiency versus load current,
VVDH = VSET = 3.6 V
aaa-036480

3.7
Load reg
(V)

(8)

(4)

(12)

3.3
(7)

(3)

(11)

2.9

2.5

(2)

(10)

(6)

2.1
(1)

1.7

0

40

(5)

80

(9)

120

160
ILOAD (mA)

200

VCAP = 4 V
VVDH = VSET:

1.8 V

2.4 V

3.0 V

3.6 V

-40 ºC

(1)

(2)

(3)

(4)

25 ºC

(5)

(6)

(7)

(8)

85 ºC

(9)

(10)

(11)

(12)

Fig. 12. Active state VVDH regulation versus load current, VCAP = 4 V

NBM7100
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Nexperia

Coin cell battery life booster with adaptive power optimization
aaa-036481

1.81
Load reg(V)

aaa-036482

2.41
Load reg
(V)
2.39

1.79

(9)

(9)
(5)

1.78

(1)

(2)

(10)
(6)

(3)

(11)
(7)

(8)

(10)
(6)

(12)
(1)

2.36

(4)

1.76

1.75

(5)

2.38

(2)

(3)

(7)

(11)
(12)

(8)

(4)

2.35

0

40

80

120

160
ILOAD (mA)

2.34

200

0

40

VVDH = VSET = 1.8 V

80

120

160
ILOAD (mA)

200

VVDH = VSET = 2.4 V

VCAP :

4.0 V

6.0 V

8.0 V

11.0 V

VCAP :

4.0 V

6.0 V

8.0 V

11.0 V-40 ºC

(1)

(2)

(3)

(4)

-40 ºC

(1)

(2)

(3)

(4)

25 ºC

(5)

(6)

(7)

(8)

25 ºC

(5)

(6)

(7)

(8)

85 ºC

(9)

(10)

(11)

(12)

85 ºC

(9)

(10)

(11)

(12)

Fig. 13. Active state VVDH regulation versus load
current, VVDH = VSET = 1.8 V

Fig. 14. Active state VVDH regulation versus load
current, VVDH = VSET = 2.4 V

aaa-036484

3.01
Load reg(V)

aaa-036483

3.62
Load reg
(V)

3

3.6

(9)

(9)
(10)

2.98

(5)

2.97

(1)

(6)

(7)

(11)

3.58

(12)

(1)

3.57
(2)

(3)

(6)

(7)

(8)
(2)

(3)

(11)

(12)

(8)

(4)

(4)

2.95

2.94

(5)

(10)

3.55

0

40

80

120

160
ILOAD (mA)

3.53

200

0

40

VVDH = VSET = 3.0 V

80

120

160
ILOAD (mA)

200

VVDH = VSET = 3.6 V

VCAP :

4.0 V

6.0 V

8.0 V

11.0 V

VCAP :

4.0 V

6.0 V

8.0 V

11.0 V-40 ºC

(1)

(2)

(3)

(4)

-40 ºC

(1)

(2)

(3)

(4)

25 ºC

(5)

(6)

(7)

(8)

25 ºC

(5)

(6)

(7)

(8)

85 ºC

(9)

(10)

(11)

(12)

85 ºC

(9)

(10)

(11)

(12)

Fig. 15. Active state VVDH regulation versus load
current, VVDH = VSET = 3.0 V

NBM7100
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Fig. 16. Active state VVDH regulation versus load
current, VVDH = VSET = 3.6 V

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Nexperia

Coin cell battery life booster with adaptive power optimization
aaa-036485

1.81
VVDH
(V)

(6)

1.8

(12)

(7)

aaa-036486

2.41
VVDH
(V)

(11)

(11)

(6)

2.4

(12)

(7)

(13)
(8)

1.79 (1)

1.77

(1)

(14)

(2)
(9)
(3)

(15)

(9)

(3)

(10)

(15)

(4)

2.36

(4)

(5)

1.75

4

(14)

2.37 (2)

(10)

1.76

(13)

(8)

2.39

5.6

7.2

8.8

10.4
VCAP (V)

2.35

12

4

5.6

VVDH = VSET = 1.8 V

7.2

8.8

10.4
VCAP (V)12

VVDH = VSET = 2.4 V

IVDH :

10 mA

50 mA

100 mA

150 mA

200mA

IVDH :

10 mA

50 mA

100 mA

150 mA

200mA-40 ºC

(1)

(2)

(3)

(4)

(5)

-40 ºC

(1)

(2)

(3)

(4)

(5)

25 ºC

(6)

(7)

(8)

(9)

(10)

25 ºC

(6)

(7)

(8)

(9)

(10)

85 ºC

(11)

(12)

(13)

(14)

(15)

85 ºC

(11)

(12)

(13)

(14)

(15)

Fig. 17. Active state VVDH regulation versus VCAP ,VVDH = VSET = 1.8 V

Fig. 18. Active state VVDH regulation versus VCAP ,VVDH = VSET = 2.4 V

aaa-036487

3.01
VVDH
(V)

(11)
(6)

3

(12)

(7)
(8)

2.98

3.6

(7)

(12)
(13)

(8)

(14)

3.59

(14)

(10)

2.97 (2)

(6)

(13)

(9)

(1)

aaa-036488
(11)

3.62
VVDH
(V)

(15)

(9)
(1)

3.57

(15)

(10)

(2)
(3)

2.95 (4)

(3)

3.56

(4)

(5)

2.94

4

5

6

7

8

9

10
11
VCAP (V)

3.54

12

(5)

4

5

VVDH = VSET = 3.0 V
10 mA

50 mA

100 mA

150 mA-40 ºC

(1)

(2)

(3)

25 ºC

(6)

(7)

(8)

85 ºC

(11)

(12)

(13)

8

9

10
11
VCAP (V)

12

200
mA

IVDH :

10 mA

50 mA

100 mA

150 mA(4)(5)-40 ºC

(1)

(2)

(3)

(4)

(5)

(9)

(10)

25 ºC

(6)

(7)

(8)

(9)

(10)

(14)

(15)

85 ºC

(11)

(12)

(13)

(14)

(15)

Fig. 19. Active state VVDH regulation versus VCAP ,VVDH = VSET = 3.0 V

Product data sheet

7

VVDH = VSET = 3.6 V

IVDH :NBM7100
Submit document feedback

6

200
mA

Fig. 20. Active state VVDH regulation versus VCAP ,VVDH = VSET = 3.6 V

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NBM7100A; NBM7100B

Nexperia

Coin cell battery life booster with adaptive power optimization
aaa-036489

IVBT(mA) 16ICAP(mA)

aaa-036490

24
(4)

(8)

(12)

18
(4) (8) (12)1212(3) (7) (11)

8

(3)
(7)
(11)

(2) (6) (10)64(1) (5) (9)

0
2.5

2.7

2.9

3.1

0

3.3
3.5
VVBT (V)

(6)

(2)

(10)

(5)

0

1

(1)

(9)

2

VCAP = 5.0 V

34
5VCAP (V)VVBT = 3.0 V

ICH :

2 mA

4 mA

8 mA

16 mA

ICH :

2 mA

4 mA

8 mA

16 mA

-40 ºC

(1)

(2)

(3)

(4)

-40 ºC

(1)

(2)

(3)

(4)

25 ºC

(5)

(6)

(7)

(8)

25 ºC

(5)

(6)

(7)

(8)

85 ºC

(9)

(10)

(11)

(12)

85 ºC

(9)

(10)

(11)

(12)

Fig. 21. Charging state supply current IVBT versus
supply voltage VVBT, VCAP = 5.0 V
IVBT
(mA)

Fig. 22. Charging state capacitor current ICAP versus
capacitor voltage VCAP, VVBT = 3.0 V

aaa-036491

10

ICAP
(mA)

aaa-036492

14
(3)

12

9
(2) (6) (10)(4) (8) (12)

10

8

(6)

(9)

(2)

(8)

8
7
(1) (5) (9)6(3) (7) (11)

6

(5)
(7)

4

(4)
(1)

5
2.5

2.7

2.9

3.1

2

3.3
3.5
VVBT (V)012

ICH = 8 mA

3

4
5
VCAP (V)ICH = 8 mA

VCAP :

4.0 V

6.0 V

8.0 V

11.0 VVVBT :

2.5 V

3.0 V

3.6 V

-40 ºC

(1)

(2)

(3)

(4)

-40 ºC

(1)

(2)

(3)

25 ºC

(5)

(6)

(7)

(8)

25 ºC

(4)

(5)

(6)

85 ºC

(9)

(10)

(11)

(12)

85 ºC

(7)

(8)

(9)

Fig. 23. Charging state supply current IVBT versus
supply voltage VVBT, ICH = 8 mA

NBM7100
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Fig. 24. Charging state capacitor current ICAP versus
capacitor voltage VCAP, ICH = 8 mA

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NBM7100A; NBM7100B

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Coin cell battery life booster with adaptive power optimization
aaa-036493

IVBT
(mA)

(2) (6) (10)(3) (7) (11)59

aaa-036494

100
ICAP
(mA)

(3)
(6)

80

(4) (8) (12)

(9)
(2)
(5)

60

(8)

51
40
43
20

(1)

(1) (5) (9)

35
2.5

2.7

(4)

2.9

3.1

0

3.3
3.5
VVBT (V)

(7)

0

1

2

ICH = 50 mA

3

4
5
VCAP (V)ICh = 50 mA

VCAP :

4.0 V

6.0 V

8.0 V

11.0 VVVBT :

2.5 V

3.0 V

3.6 V

-40 ºC

(1)

(2)

(3)

(4)

-40 ºC

(1)

(2)

(3)

25 ºC

(5)

(6)

(7)

(8)

25 ºC

(4)

(5)

(6)

85 ºC

(9)

(10)

(11)

(12)

85 ºC

(7)

(8)

(9)

Fig. 25. Charging state supply current IVBT versus
supply voltage VVBT, ICH = 50 mA

Fig. 26. Charging state capacitor current ICAP versus
capacitor voltage VCAP, ICH = 50 mA
aaa-036495

90
Efficiency(%)(1) (5) (9)(3) (7) (11)8274(4) (8) (12)(2) (6) (10)

66

58

50
2.5

2.7

2.9

3.1

3.3
3.5
VVBT (V)ICh = 8 mA
VCAP :

4.0 V

6.0 V

8.0 V

11.0 V-40 ºC

(1)

(2)

(3)

(4)

25 ºC

(5)

(6)

(7)

(8)

85 ºC

(9)

(10)

(11)

(12)

Fig. 27. Charging state efficiency versus supply voltage VVBT, ICH = 8 mA

NBM7100
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Coin cell battery life booster with adaptive power optimization

7.9. Timing diagrams
tf

SDA

tr

tSU;DAT

70%
30%

70%
30%

cont.
tVD;DATtHD;DATtf

SCL
tHD;STA

S

tHIGH

tr
70%
30%

70%
30%

70%
30%

1/fSCLcont.
9th clocktLOW

1st clock cycle
tBUF
70%
30%

SDA
tSU;STAtHD;STAtVD;ACKtSU;STO

70%
30%

SCL
Sr

P

9th clockS
aaa-036466

NBM7100A only
Fig. 28. Definition of timing parameters for SCL and SDA signals
(3)

(5)

(4)

(6)

CSN
(1)

(2)

SCLK
SDI
(mosi)

R/W = 0SDO
(miso)

addr<6>

addr<0>data<7>

data<0>(3-state)
repeat to sendmore bytes of dataaaa-036467

NBM7100B only
Fig. 29. SPI write cycle

NBM7100
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Coin cell battery life booster with adaptive power optimization
(3)

(5)

(4)

(9)

CSN
(1)

(2)

(8)

SCLK
SDI
(mosi)

R/W = 1

addr<6>

addr<0>(6)

SDO(miso)(3-state)(7)
data<0>data<7>(3-state)

repeat to sendmore bytes of dataaaa-036468

NBM7100B only
Fig. 30. SPI read cycle

NBM7100
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Coin cell battery life booster with adaptive power optimization

7.10. Test circuits
VDP

SCL

1
RDY
START

VBT

C4

16

SDA
2

15

3

14

4

13

5

12

6

11

VSS(1)

C3

L1

CAP

9

C1

VDH
ILOAD

10
8

7

VDP

C2

CSTORENC
Connect VSS withVSSP on 1 spot
VSSP

VSS

aaa-036464

C1 = 1 µF (X7R/10 V)
C2 = 10 µF (X7R/16 V)
C3 = 22 µF (X7R/16 V)
C4 = 1 µF (X7R/10 V)
L1 = 15 µH
Fig. 31. NBM7100A test circuit

16

SCLK

1

SDO
2

15

3

14

CSN

4

13

SDI

5

12

RDY

6

VBT

VSS(1)

C3

VDH
ILOAD

L1

11

9

C1

VDP

CAP

10
8

7

C4

C2

NC

CSTORE

Connect VSS withVSSP on 1 spot
VSS

VSSP
aaa-036465

C1 = 1 µF (X7R/10 V)
C2 = 10 µF (X7R/16 V)
C3 = 22 µF (X7R/16 V)
C4 = 1 µF (X7R/10 V)
L1 = 15 µH
Fig. 32. NBM7100B test circuit

NBM7100
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Coin cell battery life booster with adaptive power optimization

8. Detailed description
8.1. Functional diagram
L
Cbyp ass

LX1

VBT

LX2
CAP

2-16 mA

CSTOREBOOSTCONVERTER

VDHS

BUCK
REGULATOR

VDH
CVDH
VDP
CVDP

START-UP
Vref

OPTIMIZERSCL | SCLKSDA | SDO

I2C/SPI
CONTROL

START | SDIVBTCAP VDHSCOMPARATORSADR | CSN

RDY

NBM71 00A/B
VSS

VSS P

aaa-036469

Fig. 33. Functional diagram

8.2. Overview
The NBM7100A/B is a battery energy management device designed to maximize usable capacity from non-rechargeable,
primary batteries when used in low-voltage, low-power applications requiring burst current loads.
Battery capacity, expressed as milliampere-hours (mAh) is the amount of current withdrawn from a cell multiplied times thenumber of hours the cell can deliver the current to a specific end-point voltage, often referred to as the cut-off voltage. Cell
capacity varies in response to the applied load and temperature. The shape of the curve depends upon battery construction
and chemistry. Primary battery data sheets provide characteristic curves to aid the system designer in estimating the lifeof the cell under load and temperature conditions. Illustrative, hypothetical characteristic curves are shown in Table 15.
Fig. 34 highlights the effect of temperature on primary cell capacity and Fig. 35 shows the result of increasing constantcurrent loading on capacity. The diagrams illustrate how usable battery capacity is adversely affected by both its operating
environment and operating condition.

NBM7100
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NBM7100A; NBM7100B

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Coin cell battery life booster with adaptive power optimization
Table 15. Example primary battery characteristics
IL > I L > I L

Voltage

Voltage

50°C
25°C
-20°C
cut-off

cut-off
Battery capacity

Battery capacity

aaa-036450

aaa-036449

Fig. 34. Battery discharge pattern - constant resistanceload at various temperatures

Fig. 35. Battery discharge pattern - constanttemperature at various resistance loads

The NBM7100A/B uses two stages of high efficiency DC-DC conversion to buffer the battery from high current, shortduration load transients. The first stage conversion, or charge cycle, is initiated in advance of a period of heavy load current.
During the charge cycle, energy is transferred from the battery to an external storage capacitor at constant current from thebattery. Once charged, the second stage of DC-DC conversion, or active cycle, transfers energy from the storage capacitor
to a fixed voltage output capable of supplying high load current. The peak current drawn from the battery remains very low
during the charge cycle and is minimal in the active cycle decreasing the repetitive stress on the battery and maximizing
the usable capacity. When not operating in charge or active state, the NBM7100A/B enters a low quiescent current standby
state. An intelligent learning algorithm monitors the load pulse characteristics and optimizes energy transfer to the capacitor.

ICAP
(mA)

20

capacitor charging current

VDH
VBT

0

time
IVBT

20
IVBT
(mA)

time
pulse current load

200
IVDH
(mA)

VBT

0

VDH
DC-DC

CAP

IVDH

time

4
IR droop
0

VVDH
(V)

CAP

ICAP

battery current (@ ICH)
0

VVBT
(V)

DC-DC

time
VVDH = VSET

4

VVDH = VVBTVVDH = VVBT

0

time

db
y

e
tiv

time

st
an

ac

ar
ch

st
an

db
y

0

ge

MAX
VCAP
(V)

aaa-036496

Fig. 36. Standby - Charge - Active - Standby cycle
NBM7100
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NBM7100A; NBM7100B

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Coin cell battery life booster with adaptive power optimization
The NBM7100A/B is ideal for applications supplied from non-rechargeable, primary cell batteries with high internal
impedance. Common examples include: lithium metal primary batteries such as 3V lithium manganese dioxide (LiMnO2 example "CR 2032 coin cell"), 3.6 V lithium thionyl chloride (Li-SOCl2 - example "LS 14250" ½ AA), and emerging paper
printed types. Lithium metal batteries are commonly selected for low-voltage, low-power electronics due to their superiorenergy density (Wh/kg) and long storage life. A comparison of lithium batteries is shown in Table 16. The 2 × "AA" alkaline
column is included for reference.
Table 16. Basic primary cell battery comparison
LiMnO2
CR 2032

Li-SOCl2
LS 14250 (½ AA)

2 × "AA"
Alkaline

3V

3.6 V

3V

280 Wh/kg

500 Wh/kg

200 Wh/kg

240 mAh (0.2 mA)

1200 mAh (0.5 mA)~ 4000 mAh (@ 250 mA)(2 × 2000mAh)

2V

2V

1.6 V
(2 × 0.8 V)

shelf life

10+ years

10+ years

5-7 years

operating temperature-30 to 60ºC

-55 to 85ºC

0 to 60ºC

internal resistance [1]10 Ω (BoL)
70 Ω (EoL)

10 Ω (BoL)
70 Ω (EoL)< 1 Ω (over lifetime)

open circuit voltage (BoL)
energy density
capacity
cut-off voltage[1]

BoL: Beginning of life
EoL: End of life

Many battery powered electronic loads do not operate with a constant current drain from the primary cell, rather are made ofshort periods of relatively high current followed by much longer periods of very low current. The resulting average current isvery low, often only a few 10s of μA. It is complicated to accurately estimate the effect variable loading on battery capacity,
but important to realize the usable capacity will be lower than the average indicates as the chemical reaction rate needed tosupport a load pulse of tON is higher than that required in the tOFF condition scales non-linearly.
Fig. 37 depicts a pulsed load having a peak current IPK and a background (continuous) current drain of IBKG. During theload pulse, the battery voltage droops for two reasons Fig. 38: 1) I × R drop due to the pulsed current and 2) the chemical
reaction rate in response to the load step. When the IPK is released and the battery loading returns to IBKG, the battery
voltage returns close to its value before the load pulse was applied. Over time and repetitive pulses, battery chemicals are
depleted and the starting and recovery voltages decrease.
tOFF

IAVG
IBKG

average

VoltageLoa d Curr ent

tON
IPK

I×R

chemical recovery
reaction
time

time

time

aaa-036451

Fig. 37. Pulsed load

NBM7100
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aaa-036452

Fig. 38. Battery voltage under pulsed load

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Coin cell battery life booster with adaptive power optimization

IPK
IR

IBKG

IAVG (continuous)

cut-off

Internal resistance(IR)

VoltageFig. 39 compares a continuous current drain, IAVG equal to the duty cycle average of IPK and IBKG to the piecewisecomponents of IPK and IBKG to illustrate battery capacity under pulsed conditions are not equivalent to a steady-state current
drain of an average equivalent load. Maximum battery life is achieved when the battery is exposed to low DC current, ideally< 10 mA.

Capacity (mAh)aaa-036453

Fig. 39. Battery capacity: pulsed load vs continuous load

NBM7100
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8.3. Operating modes
The NBM7100 has three operating modes:
1. Continuous mode
2. On-demand mode
3. Auto mode (NBM7100A only)
When the NBM7100A/B is in one of the three operating modes, the device may transition between different States ofoperation: Standby, Charge, or Active. The Standby state is not an Operating mode, but is represented in Fig. 40 for clarity
of device behavior while not in one of the three operating modes.

8.3.1. Mode overview

0
Load current

0
4
VVDH
(V)

t
Load current

200
IVDH
(mA)
0

VVDH = VVBT

4
VVDH
(V)

battery current

IVBT
(mA)

0

t
Load current

200
IVDH
(mA)
t

VVDH = VSET

0
4
VVDH
(V)

VVDH = VVBTVVDH = VSET

VCAP
(V)

Leakage currentt
Load current

0
4
VVDH
(V)

VVDH = VVBTVVDH = VSET

4
VVDH
(V)

VVDH = VVBT

VCAP
(V)

VCAP
(V)

VCAP
(V)

VCAP
(V)

t

0

t

H

H

H

H

H

RDY

RDY

RDY

RDY

L

L

L

t

L

t

standbyactivechargestandbystandbyactivechargestandbyactiveH
STARTchargeH
START

refresh monitor

H
Serialdata
Ltstandby

H

L

t

t

L

Serialdata
Lt

VVDH = VVBT

0

RDY

t

VVDH = VSET

t
MAX

0

t

t
MAX

t

Load current

0

MAX

0

t

200
IVDH
(mA)
t

t

0

MAX

0

battery current

IVBT
(mA)

0
200
IVDH
(mA)

t

t
MAX

battery current

IVBT
(mA)

Auto (long START)
20

L

t

standby

0
200
IVDH
(mA)

battery current

IVBT
(mA)

Auto (short START)
20

activebattery current

On-demand
20

chargeIVBT(mA)Continuous
20

standbyStandby state20taaa-036459

Fig. 40. Mode diagrams

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Mode Controls
Table 17. command and set3 Registers - Mode control
Register 8
0x08(write)Code (bin)Function

Remarkbit [0] eod(enable On-demand)

0

off

-

1

on

-

bit [1] ecm(enable Continuous mode)

0

off

-

1

on

-

bit [2] act(force Active state)

0

off

-

1

on

force active

bit [3] rstpf(reset optimizer)

0

-

-

1

reset

reset optimizer result of active profile
prof[5:0]

0

off

default for NBM7100B version [1]1ondefault for NBM7100A version

Register 11 (write)
bit [7] automode[1]

NBM7100B cannot be written to 1.

8.3.2. Continuous mode
Continuous mode is intended for applications requiring instant pulse load capability. It is initiated by setting the ECM bit
0x08[1] (see Mode controls). In Continuous mode, the external storage capacitor is charged and the DC-DC converter isidled. The CAP pin voltage is "monitored," and if the capacitor voltage, VCAP as indicated in vcap drops below the end of
charge VFIX as programmed in vfix the DC-DC is automatically enabled to "refresh" the capacitor to the target VFIX voltage.
When an Active command is received then the stored energy in the capacitor is immediately available at full power as aregulated supply voltage at pin VDH. The storage capacitor will get recharged automatically after the device has delivered
its energy pulse to the load. The RDY signal indicates when the storage capacitor has been charged or recharged to VFIX.
Active state and recharging can be toggled as needed. The device returns to Standby mode by resetting both the ECM andACT bits.

8.3.3. On-demand mode
On-demand mode is initiated by setting eod bit 0x08[0] (see Mode controls). This mode is intended to maximize battery
lifetime in low duty cycle applications where the system is in sleep-mode most of the time. In this mode the energy is firstextracted from the battery and stored in a capacitor (Cstore) connected to the CAP pin. The stored energy is then madeavailable at full power as a regulated supply voltage at pin VDH. The RDY output indicates when the output VDH is ready todeliver power. On-demand mode is ended by resetting the eod and act bits.

8.3.4. Auto mode (NBM7100A only)
Auto mode utilizes the START pin to set and reset the eod bit without requiring the serial bus. One cycle is initiated by arising edge on the START pin. When charging is finished the Active state will begin automatically and the RDY pin will gohigh to confirm that the VDH pin is regulating to VSET and ready to deliver full power. The Auto mode can be enabled or
disabled by the automode bit 0x11[7]. To prevent unintended Auto mode triggering due to a floating input condition, theSTART pin should be connected to VSS via a pull-down resistor. The pull-down resistor should be sized appropriately for the
IOH of the external microcontroller driving the pin.
In Auto mode, there are two ways to define the end of the Active state:
1. Short pulse on START: From standby mode, a short pulse (≥ 10 µs) is applied on the START pin. A charge cycle initiates
followed by automatic transition to Active state. A short START pulse is defined as the time the START pin is driven highuntil Active state is reached at the conclusion of the Charge state. 10 µs ≤ tSTART(short) ≤ time(Charge state ends) as indicated

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Coin cell battery life booster with adaptive power optimizationby the rdy bit or the RDY pin. The Active state automatically ends when the combined VDP and VDH load current isbelow INL for approximately TNL.
2. Long pulse on START: From standby mode, the START pin is driven high and maintained high until the Active cycle
begins as indicated by a high transition on the RDY pin. The Active state is ended when the START pin is driven low.
When a long START pulse is initiated, the START pin should be maintained high until the high current load pulse on VDH
is concluded.
Note: in case the START pin is set low during the charge state, this will be interpreted as a short pulse.
At power-on, the default settings of the NBM7100A are:••••

Auto mode is ON (see Mode controls)
VSET = 3.0 V
Ich = 8 mA
Profile number = 1 (Optimization is active for profile 1)
When other settings are required, a serial bus command is required to change the default settings.

The NBM7100A can be switched between Continuous mode, On-demand mode and Auto mode at any time.

8.4. Feature description
8.4.1. Chip control
Refer to functional diagram. The chip control consists of the device state machine; serial bus interface; status, configurationand control registers; the optimizer engine, and fuel gauge functions. It enables and disables peripheral analog blocks asrequired to execute the state machine.

8.4.1.1. Serial bus
The NBM7100A/B is controlled using a serial bus interface. Reading or writing of settings may be performed approximately
20 ms after power-on reset is cleared and device start-up completed. Initiating communication while the device is in startup
may result in register errors. Internal registers allow control of the Standby-Charge-Active cycling process (On-demandmode) or the Charge-Active cycling process (Continuous mode), reading of device status indications, and adjustment ofdevice operating parameters.

8.4.1.1.1. NBM7100A I²C interface
The NBM7100A is protocol compatible to Fast Mode Plus I²C interface (1 MHz). The NBM7100A is a slave device and has
two programmable slave addresses. Each I²C transaction requires a register address followed by one or more data bytes.
The register address is auto-incremented after each data-byte.
For reading data, the selection of the register address and the reading of the data must occur in one single transaction.
Switching from write to read mode (or vice versa) must be done with a repeated Start condition. Register selection is always
cleared after a STOP (P) command. If no register is selected while reading, the status register will appear as the first data
byte.
Single byte write to register (N)S SLAVE ADDRESS W A DATA (REG ADDR = N)ADATA (N)A P

Multiple byte write to register (N + 1)
S SLAVE ADDRESS W A DATA (REG ADDR = N)ADATA (N)A

Multiple read from register (M) and (M + 1)
S SLAVE ADDRESS W A DATA (REG ADDR = M) A Sr SLAVE ADDRESS R AMultiple read of registers (0 - 2)
S SLAVE ADDRESS R ADATA (0)A

DATA (1)A

DATA (2)DATA (N + 1)
DATA (M)A

A P
DATA (M + 1)

A P

A P

LegendFrom Master to Battery Booster

S Start condition

W Write bit (0)A Acknowledge bit

From Battery Booster to Master

P Stop condition

R Read bit (1)Sr Repeated Start condition
aaa-036470

Fig. 41. I²C transfers

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Two I²C slave addresses are available for the NBM7100A :Table 18. I²C addresses
ADR pinI²C Slave address

00x2E (010 1110 R/Wn)

1

0x2F (010 1111 R/Wn)

8.4.1.1.2. NBM7100B Serial Peripheral Interface (SPI)The NBM7100B supports bidirectional communication with a master system controller (MCU) via a 4-wire SPI mode 0
compatible serial communication interface. It is a transmit/receive slave-only interface. The master device initiates datatransfers on the bus and must generate the Clock (SCLK) and Chip Select Not (CSN) signals. The data input is SDI (MOSI),and the data output is SDO (MISO). Each transmission starts with the falling edge of CSN and ends with the rising edge.
During a transmission, commands and data are controlled by SCLK and CSN according to the following rules:
•
•
•
•
•
•
•
•
•
•

Commands and data are shifted MSB first, LSB last.
Input bit is sampled at the rising edge of SCLK.
In read mode, data bits are shifted out at the falling edge of SCLK. After the device has been selected with the fallingedge of CSN, the first byte defines data direction and register address. MSB = 1 for Read, or MSB = 0 for Write, followedby 7-bits for the address in the register space.
The rising edge of CSN ends all data transfer, terminating any previous command and clears the address pointers.
If an invalid command is received, no data is shifted out of the circuit until the falling edge of CSN. This reinitializes theserial communication.
Data that is written to the NBM7100B immediately follows the first address byte.
Data that is read from the device at the rising edge of SCLK immediately follows the last bit of the address byte.
Maximum SCLK clock frequency is 4 MHz (500 Kbyte/s)
An SPI command can be followed by multiple data bytes within one transmission. The register address pointer is autoincremented.
SPI mode 0 means that the parameters Clock Polarity (CPOL) and the Clock Phase (CPHA) are both 0.

8.4.1.1.3. Device register overview
Refer to the register map. Short description of the registers and their functions follows. Additional details can be found in therespective feature sections.
setx registers [0x09:0x13] configure the active mode regulated output voltage vset[3:0] (VDH); the charge state target
voltage vfix[3:0], VFIX and maximum voltage for the storage capacitor vcapmax (VCAP(MAX)); the capacitor charging current
ich[2:0] (ICH); low voltage monitor thresholds for battery vmin[2:0] (VMIN), and capacitor early warning vew[3:0] (VEW);
enable/disable the internal power path switch between VDP and VDH vdhhiz; enable/disable auto mode automode; and adjust
the voltage margin of the optimizer function opt_marg[1:0].
status register [0x00] provides indication the capacitor is charged and is the device is ready (rdy) to support a highcurrent load on the VDH pin. The RDY output pin reflects the present status of the rdy bit without requiring serial bus datatransactions. Monitor alarms for low battery, VMIN, (lowbat); low capacitor voltage, VEW, early warning (ew) and low output
voltage in the Active state, VDH (alarm) provide a view of device and system conditions.
command register [0x08] is used to set the device operating modes: enable On-demand, enable Continuous, and Active.
The MSBs of [0x08] and LSBs of [0x07] are used to set the optimizer profile number prof[5:0] (1d to 63d). Each profile
setting can be used optimize the energy transfer of one unique repetitive load condition (see Section 8.4.5). The leastsignificant bits of the optimizer profile setting are deliberately located in the command register to facilitate a single write
transaction for the first 14 settings (1d to 14d).
vcap register [0x05] is utilized in the charge and active states to provide near real-time indication of storage capacitor
voltage. The registers are not updated in the standby state. The vchend register is a translated digital mapping of the target
VCAP voltage obtained from vfix[3:0] in [0x08] when the prof[5:0] bits are all reset [0h], or voptx[3:0] hidden registers used by
the optimizer to set the target capacitor charging voltage threshold associated with each profile.
chengy registers [0x01:0x04] provide indication of the charge removed from the battery following one enable On-demand or
upon completion of a Continuous mode cycle. The registers are reset before the charging cycle begins and should be readand accumulated by an external microcontroller while the device is in the active or standby state.

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8.4.1.2. The ready (RDY) output signal and rdy bit
The RDY signal is driven high indicating that the NBM7100A/B is ready to provide full power to its load. It can serve as
an interrupt signal to a connected microcontroller. Its behavior is different (see below) in On-demand mode than it is inContinuous mode. The rdy bit in 0x00[0] follows the RDY signal.

RDY in On-demand mode
The RDY signal will go high when the capacitor charge level is reached, and the VDH output voltage is regulating to VSET.
The RDY signal will go low if:••

The eod bit is reset (see Mode controls) or
The storage capacitor is depleted.

If Early Warning is activated and the voltage at the storage capacitor drops below VEW (see capacitor early warning voltage),then the RDY signal will pulse low for tEW, then resume high state until one of the above On-demand mode conditions is
met.

RDY in Continuous mode
The RDY signal will go high when the voltage at pin CAP has reached VFIX.
The RDY signal will go low if:••

The act bit is reset (see Mode controls) or
The storage capacitor is depleted.

If Early Warning is activated and the voltage at the storage capacitor drops below VEW (see capacitor early warning voltage),then the RDY signal will pulse low for tEW, then resume high state until one of the above Continuous mode conditions is
met..

8.4.2. States of operation
The NBM7100A/B has four main states of operation as shown in Table 19.
Table 19. States of operation
Operating stateContinuous mode
(1) ecm bit set(2) act bit set(3) act bit reset…..
from Charge or Active
return to Standby:(4) Reset ecm and act

Battery insertion

StartupStandby(1)
Charge(2)

On-demand mode

(4)

Auto mode001 (1) 10 µs start pulse
010 (1) eod bit set
101 (2) Charge ready110 (2) Charge ready010 (occurs autonomously)(4) no_load current(4) eod bit reset
000

001
101
000

(1) eod bit set(2) Force active
000 (before Charge ready)(3) Continue charge(2) Charge ready(occurs autonomously)(4) EOD bit reset

001
101
000

001 (1) START = 1
101 (2) Charge ready(4) START = 0
001
101
000

The three digits represent the value of the bits (act; ecm; eod) in register 8 (see Section 10.2),
either controlled through a serial bus command, or (in bold italic) changed by the internal
logic.

(3)
Activeaaa-036463

8.4.2.1. Startup state
When a battery or other voltage source is sensed at the VBT pin and the sensed voltage is higher than VPOR level, internal
power switches connect VBT and outputs VDP and VDH (See POR VBT fast ramp). Approximately 20 ms after start-up, theStandby state is entered.

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Note: The register map indicates the default state of all bits at startup. Reading or writing to the serial bus during theStartup state may cause corruption of the non-volatile memory. Serial bus transactions should not be initiated until
approximately 20 ms after VVBT > VPOR when the device has entered the Standby state.

8.4.2.2. Standby state
The Standby state is a low power operating condition where the quiescent current consumption is almost negligible; theserial port is active and ready to receive commands; and the VBT to VDP switch is enabled.
In the Standby state, the device is inactive. The supply current drawn from the battery is very low, IQ_STB and the device iswaiting for a serial bus command or START command (NBM7100A). While the device is in Standby state, device settings
can be programmed. For example: maximum storage voltage, VCAP(MAX); the charging current, ICH; and the active mode
VDH output voltage, VSET.
The VBT to VDH switch is enabled at POR by default. Alternatively, for a high-impedance VDH output in the Standby andCharge states, set vdhhiz = 1 (see VDH).
The register settings are retained while supply voltage at VBT input is not interrupted.
The RDY output and rdy register bit is low in Standby state.
The chip will exit Standby and enter the Charge state by:•••

the setting of eod (Enable On-demand) bit, or
setting the ecm (Enable Continuous Mode) bit, or
activation with the START pin (NBM7100A) with automode = 1.

8.4.2.3. Charge state
The DC-DC boost converter is enabled with VBT as the input and CAP as the output. The external storage capacitor ischarged from VBT using constant current, ICH, as set by the ich[3:0] bits in 0x10[7:5]. The ich bits provide 4 normal charging
current settings and one high current (emergency) level. Using the lowest ICH setting maximizes battery life at the expenseof a long charging time.
In the Charge state, if VVBT drops below the programmed VBT input minimum threshold, VMIN as set by the vmin[2:0] bits
in 0x10[2:0], the NBM7100A/B pauses charging until VBT recovers above VMIN at which point charging resumes. If VBTremains below the VMIN threshold for more than 16 µs, the lowbat alarm status bit will be set to indicate the battery may benearing end of life.
vmin[2:0] is an aid for maintaining a minimum battery voltage. Battery voltage drop could be caused by multiple factors
including, current consumed by other functions in the application connected directly to the battery, end of battery life, a low
operating temperature or the formation of a passivation layer inside the battery (in case of Li-Thionyl batteries).
While above VMIN, charging continues until the “End-of-charge” voltage is reached.
••

Fixed (optimizer disabled): The “End-of-charge” voltage as set by vfix (optimizer profile = 0)
Optimizer (enabled): The “End-of-charge” voltage as set by voptx (hidden register location) as controlled by the
optimizer (optimizer profile ≠ 0)

The vcapmax bit in 0x12[4] defines, VCAP(MAX), the maximum storage capacitor voltage allowed during the Charge state. For
safety reasons the value VCAP(MAX) will never be exceeded even if a higher fixed End-of-charge voltage is programmed.
The progress of charging the storage capacitor can be monitored by reading the vcap status register 0x05[4:0].
In On-demand mode, the device will automatically enter Active state after reaching the End-of-charge voltage.
In Continuous mode the device will stay in Charge state and the charge level of the capacitor will be maintained at the
programmed level. This will compensate for any leakage from the storage capacitor. This charge maintenance uses minimal
power from the battery.

8.4.2.4. Emergency charge state
The normal charge currents ich[3:0] = 0h, 1h, 2h, or 3h are intended to limit the battery current for optimal efficiency andbattery lifetime. The lower the charge current, the longer the time to charge the storage capacitor. In cases where a shorter
charge time prevails above battery lifetime, the emergency charge mode (ich[3:0] = 4h) is available. In emergency charge
mode, the battery current is increased to 50 mA (typical). vmin[2:0] continues to function as described in Charge state.

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8.4.2.5. Active state
In the Active state both the VDP and VDH outputs are supplied from the integrated switching regulator using the storage
capacitor as its energy source. In this state the current consumed by the NBM7100A/B from the battery is very low, IQ_ACT.
The output voltage (VDP and VDH) is determined by the value programmed in the set1 register using the vset[3:0] (VSET)
bits.
On-demand mode: The Active state is entered automatically after charging has been completed. The Active state can also
be initiated prior to completion of the charge cycle (force active) by setting the act bit high. Active state ends by resetting theeod bit and returns to the Standby state.
Continuous mode: The Active state is entered at any time by setting the act bit. Active state ends by resetting the act bit
and returns to the Charge state. Resetting the ecm and act bits returns the device to Standby.

8.4.2.6. Capacitor input voltage Early Warning alarm
In the Active state the storage capacitor is the energy source for the DC-DC converter. As the capacitor is discharged by theload its voltage drops. A programmable early warning alarm is available to alert the system when VCAP drops below the VEW
threshold set by the vew[3:0] bits indicating a limited amount of energy is remains in the capacitor. The eew bit enables ordisables the alarm indication. The condition of the alarm is indicated by the ew bit in the status register 0x00[6]. When theew bit goes high, the RDY pin pulses low for tEW providing two mechanisms for the system to receive an indication the alarm
has triggered. The power on default state for eew is disabled.

8.4.2.7. VDH output voltage alarm
In the Active state, if the load current exceeds the capability of the regulator, the VDH voltage may drop below the
programmed target voltage, VSET triggering the VDH alarm. The condition of the alarm is indicated by the alarm bit in thestatus register 0x00[5]. When the alarm bit is set, the RDY pin is driven low providing dual mechanisms for the system toreceive the indication. If the load current is reduced, VDH may recover to VSET before the Active state concludes; however,
the alarm bit and RDY pin low indications will not reset until the next Charge state is initiated.
The maximum load current depends on the operating point of the DC-DC converter in the Active state: capacitor voltage(input supply to the DC-DC); the programmed VDH voltage VSET (output of the DC-DC); external components ratings andtolerances; and the ambient temperature. Some typical characteristics are given in Application curves.

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8.4.3. DC-DC converter
The NBM7100 integrates a variation of a classical peak-current mode control "4-switch buck-boost" with a fixed frequencyof 1 MHz. The DC/DC converter operates with discontinuous conduction mode for light loads and transitions to continuous
conduction mode as the load current increases. Refer to Fig. 42.

VBT

VDH

LX1

LX2

CAP

SW4

SW1

SWc

SW2

SW3

VSS P
capacitor
precha rge

VSS P
aaa-036458

Fig. 42. DC-DC converter switches
In the charge state when VCAP < 1.6 V, the storage capacitor is initially charged at low current via the capacitor precharge
switch.
In the Charge state when VCAP > 1.6 V, the DC-DC converter operates in boost mode to draw constant programmed
charging current (ICH) from the battery and charge the energy storage capacitor connect to the CAP pin.
The charging transition threshold can be seen in the typical characteristics section of the datasheet in the charging state
capacitor current ICAP versus capacitor voltage, VCAP plots.
Boost mode (Charge)••

Primary phase: SWc and SW3 are ON
Secondary phase: SW2 and SW4 are ON

In the Active state, the dc/dc converter uses the energy available in the storage capacitor to deliver a regulated output (VSET)
on the VDH pin capable of supporting pulsed current loads.
Buck mode (Active)••

Primary phase: SW1 and SW4 are ON
Secondary phase: SW3 and SW4 are ON

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8.4.4. VDP and VDH output configuration
Fig. 43 provides a simplified representation of the internal power switches within the NBM7100A/B devices.
VDP

VBT

VDH

LX1

LX2

CAP

VBT_to_VDH
VDP_to_VDH
VDP_to_VBT

SW4

SW1

SWc
SW2

SW3
VSS P

DC/DC

capacitor
precharge
aaa-036471

Fig. 43. Internal switches

8.4.4.1. VDP
VDP is a 'permanent' supply output pin. It is internally connected to VBT in the Standby and Charge states via the
VBT_to_VDP switch. In the active state, VBT connects to VDH via the VBT_to_VDH switch. It provides power to 'always
on' system loads (e.g. host microcontroller core and I/O). Due to the variable range of output voltages between VBT andthe regulated VDH, care should be taken to ensure loads connected to the VDP pin will not be subjected unintended overvoltage or under-voltage conditions.
The VDP pin should be connected to a bypass capacitor. See Recommended components.

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8.4.4.2. VDH
The vdhhiz bit 0x10[4] is 0b upon entry into the Standby state following POR, connecting VBT to VDH. Unless the vdhhiz is
set via the serial interface, VDH pin remains internally connected to VBT in all states of operation except the Active state.
In the Active state, VDH supplies a regulated output voltage according to vset[3:0] in 0x09[3:0]. Table 20 summarizes thedevice default switch connections.
Table 20. VDP and VDH operation, vdhhiz 0x10[4] = 0 (default operation)
State
VDP
VDH
StandbyConnect to VBTConnect to VBTChargeConnect to VBTConnect to VBT

Diagram
DC-DC
REGULATOR

VDH

VBT

VDP
aaa-036684

Fig. 44. Standby andchargeActiveConnect to VDH

Connect to DC-DC output
vset

DC-DC
REGULATOR

VDH

VBT

VDP
aaa-036685

Fig. 45. Active
If the vdhhiz bit 0x10[4] is set via the serial interface, the VDH output becomes high impedance if the device is not in the
Active state as indicated in Table 21. The high impedance configuration is useful in cases where it is preferable to switch
off a load (e.g. a sensor) connected to the VDH pin. When the high impedance vdhhiz mode is not required, all loads
can be supplied from the VDH pin simplifying system configuration. When high impedance mode is enabled, the hostmicrocontroller should be supplied from the VDP pin or directly from the battery.
Table 21. VDP and VDH operation, vdhhiz 0x10[4] = 1 (high-Z operation)
State
VDP
VDH
StandbyConnect to VBT

Hi-ZChargeConnect to VBT

Hi-ZDiagram
DC-DC
REGULATOR

VDH

VBT

VDP
aaa-036686

Fig. 46. Standby andchargeActiveConnect to VDH

Connect to DC-DC output
vset

DC/DC
REGULATOR

VDH

VBT

VDP
aaa-036687

Fig. 47. Active
In more complex RF microcontroller applications with multiple input voltage pins, the VDP output can be connected to thecore and I/O functions supply inputs, while the VDH output is connected to the high current RF power supply input.

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Coin cell battery life booster with adaptive power optimization
The VDH pin should be connected to a bypass capacitor after accounting for derating characteristics to achieve theminimum capacitance indicated in the Recommended components table.

8.4.4.3. Setting VDH output voltage, VSET (Active state)
Upon completion of a Charge state, the device transitions to the Active state at which time VDH becomes a regulated
voltage output denoted as VSET as configured in vset[3:0] in 0x09[3:0]. Unless overwritten via the serial bus, the default VSET
voltage is 3.0 V.
For some applications it may be beneficial to change VSET during the Active state. For example, an RF microcontroller
in a sensor application needs to transmit several data packets to a remote receiver. The initial data packet is transmitted
at maximum power likely requiring a VSET voltage of 3.6 V. After receiving an acknowledgement of a successful linkwith receiver, the RF microcontroller may determine a lower transmit power is sufficient and decrease the VSET voltage
dynamically to 3 V for duration of this transmit/receive period.

8.4.5. Adaptive power optimization
The NBM7100A/B applies a proprietary learning algorithm to adaptively determine and optimize the amount of energy to
be transferred from the battery and stored in the capacitor. This optimization engine can learn up to 63 load profiles. Eachlearned profile is retained in a reserved register location used by the optimization engine.
Each optimizer setting is used to store one load profile. Each stored load profile should be reasonably consistent andrepetitive in energy requirements.
If prof[5:0] = 0h, the optimizer is disabled and the storage capacitor is charged according to the vfix[3:0] registers.

Load current

Profile(1)

Profile(2)...

Profile
(n)

...

time
aaa-036454

Fig. 48. Load profiles
The optimizer engine works by measuring the residual energy level in the storage capacitor after each load pulse andpredicts the optimized energy level to charge the storage capacitor for the next pulse.
Optimizer profile 1 and 'extra safe' optimization margin are enabled by default after the device POR threshold is cleared.
Assigning a different profile, prof[5:0] in 0x07, 0x08, or altering the optimization margin, opt_margin in 0x13, is performed via
the serial bus.
The optimizer margin voltages in opt_marg[1:0] correspond approximately to the first four VOPTx levels and is analogous to
the first four VFIX levels.

8.4.5.1. Optimizer initialization and downward increment
Each optimizer profile setting learns the repetitive energy requirement of the assigned load. The number of repeated load
pulses needed to reach an optimized level will vary depending upon the energy consumed. Reserved register locations
maintain the target capacitor charging voltages for each profile, VOPTx. VOPTx is analogous to the user programmable VFIX
setting (optimizer profile = 0), the exception being the optimizer engine automatically increments VOPTx during the initial
learning phase and in response to changes in the load profile.
At the start of the optimization process, VOPTx is set to VCAP(MAX) according to the vcapmax setting. When On-demand isinitiated via register write or START pin (NBM7100A), the capacitor charges to VCAP(MAX). When charging is complete, theNBM7100A/B initiates an ACTIVE cycle during which the load is applied. At the conclusion of the Active cycle the capacitor
voltage is compared to the VOPT_MARGIN, opt_marg[1:0], threshold.
••

If VCAP > VOPT_MARGIN, the voptx register is decremented one setting.
If VCAP < VOPT_MARGIN, the voptx register is incremented by at least one setting.

Fig. 49 is an example of an optimizer initialization sequence. The initialization sequence occurs after device power on, or if
the optimizer profile is reset, by selecting a profile number using and writing 1b to rstpf 0x08[3].

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Initial conditions for initialization example:
1.
2.
3.
4.
5.

Device powered and POR cleared (battery insertion).
vcapmax 0x12[4] = 1b.
VCAP at zero or holding residual charge.
VOPT_MARGIN 0x13[1:0] = 11b (default)
prof = 1b (default)

IVBT
(mA)

20
battery curren t (@ ICH )0pulse current load

200
IVDH
(mA)
0

MAX

V CAP
(V)

(2)
(1)

(3)

(3)

(3)

(4)

(4)

(4)

(3)

(2)

(3)

(1)

(2)

(3)
(4)
(3)

(1)

(2)

(3)

(1)

VOPTx
[4:0 ]
11b VOPT_ MARGIN00b[2:0 ]

0

RDY

H

a
st

L

b
nd

y

by
by ge vebyge v ege ve
ge ve
ar cti and har acti and har acti andar acti
ch
ch a
c
c
st
st
st
A

B

C

D

t

aaa-036455(1) Standby state: VCAP decreases due to leakage current.
(2) Charge: capacitor charged to VOPTx reserved register setting.
(3) Active: DC-DC providing regulated VDH. No load is applied.
(4) Load: load pulse supplied from VDH output.
Fig. 49. Optimizer profile initialization and down increment
Table 22. Optimizer profile initialization and down increment
A
B
VOPTx = VCAP(MAX) [15d]VOPTx = [14d]CD

VOPTx = [13d]VOPTx = [13d](1) Standby.
(2) On-demand cycle initiated: Charging.
(3) Active, no load.
(4) Active, with load.
(3) Active, no load.
(1) Standby, no load.
VCAP > VOPT_MARGIN
decrement VOPTx

VCAP > VOPT_MARGIN
decrement VOPTx

VCAP = VOPT_MARGIN
no change VOPTx

VCAP = VOPT_MARGIN
no change VOPTx

During A, B, and C as the optimization level is being approached, the charging energy from the battery is reduced becoming
approximately constant in D and subsequent repetitions of D (not shown).
If after optimization, the load pulse energy is reduced by either or both reducing the peak current in the pulse, or the time thepulse persists, the state machine takes action to reduce VOPTx until a new optimized level is reached.

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8.4.5.2. Optimizer upward increment
If after completing an initial or downward optimization sequence as shown in Optimizer initialization and downward
increment, the load increases either or both in amplitude or duration, the optimizer state machine will respond with upward
incrementation until a new steady-state optimization level is reached.
Initial conditions for upward increment example:
1.
2.
3.
4.

Device has previously optimized the selected load profile.
VCAP at zero or holding residual charge.
VOPT_MARGIN 0x13[1:0] = 11b (default)
prof = 1b (default)

IVBT
(mA)

20

battery curren t (@ I CH )0
pulse current load

200
IVDH
(mA)
0

(3)

MAX

(4)

V CAP
(V)

(2)

(3)

(3)

(3)

(3)

(4)
(3)

(2)

(4)
(2)

(3)

(1)

(1)

(4)
(3)

(2)

(4)
(2)

(3)

(1)

(3)

(1)

VOPTx
[4:0 ]
11b VOPT_ MARGIN00b[2:0 ]

0

RDY

H
L

a
st

by ge i v e
byge i v e dby
nd har ac t and har ac t
an
t
c
c
st
s
A

ch

B

ar

C

ge t i v e dby
ac t an
s

ch

ar

ge

ac

tiv

D

e
a
st

nd

by

ch

ar

ge

ac

tiv

e

E

aaa-036456(1) Standby state: VCAP decreases due to leakage current.
(2) Charge: capacitor charged to VOPTx reserved register setting.
(3) Active: DC-DC providing regulated VDH. No load is not applied.
(4) Load: load pulse supplied from VDH output.
Fig. 50. Optimizer up increment
Table 23. Optimizer up increment
A
B
VOPTx = VCAP(MAX) [11d]C

VOPTx = VCAP(MAX)[11d]; load
duration increases

D
VOPTx = [13d]E
VOPTx = [14d]VOPTx = [15d](1) Standby.
(2) On-demand cycle initiated: Charging.
(3) Active, no load.
(4) Active, with load.
(3) Active, no load.
(1) Standby, no load.
VCAP = VOPT_MARGIN
no change VOPTx

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VCAP < VOPT_MARGIN
increment VOPTx

VCAP < VOPT_MARGIN
increment VOPTx

VCAP < VOPT_MARGIN
increment VOPTx

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Coin cell battery life booster with adaptive power optimization
During B, the change in load is large enough to result in an ending VCAP voltage well below optimizer margin voltage (11b)and results in an incrementation of two steps. At the conclusion of C and D, VCAP is remains below the optimizer margin
voltage, but is less severe resulting in a single step increments. The energy transferred from the battery increases in eachcycle. In E, the VCAP is just above the margin voltage and optimization is complete. Subsequent load profiles identical to E
will not change the VOPTx and are not shown.

8.4.5.3. Optimizer in steady state
Optimizer initialization and downward increment and Optimizer upward increment give an overview of the load profile
optimization process. It is unlikely a load profile will be 100% consistent in magnitude and duration in an application, . Under
these circumstances, the optimizer state machine may toggle between several levels. The overall result is less charge loss
and more efficient use of battery capacity compared to charging to VFIX to VCAP(MAX) regardless of load energy required.

8.4.6. Fuel Gauge
While the charging process is ongoing, the number of conversion cycles to charge CSTORE is counted. Each conversion
cycle represents a fixed amount of charge taken up from the battery irrespective of the charge level of CSTORE based on one
switching cycle of the DC-DC boost regulator. The accumulated result of counting repetitive conversion cycles represents
a good indication of the battery capacity used. The counting result is stored in the 32 bit word of the fuel gauge registers
chenergy.
The accumulated results in these registers can be read from the serial bus at any time in the Standby state. The register isreset if:••in Continuous mode the Active state transitions to the Charge state: 0x08[2:0] transitions from 6h to 2h.
in On-demand mode the Active state transitions to the Charge state: 0x08[2:0] transitions from 5h to 1h.

For an estimate of the battery lifetime the results must be accumulated by the host microcontroller. Each count (QN) of thefuel gauge register represents an electrical charge:
Table 24. Fuel Gauge
Note: The Fuel Gauge does not take the bias currents of the Battery booster circuit into account.
ICH[2:0] = 0-3 (normal charge)

ICH[2:0] = 4 (emergency charge)

Filling in the typical values for VVBT, TP and L:VVBT = 3 V
L = 15 µH
TP = 1 µs
results in:

or in usual battery capacity

or in usual battery capacity

QN is the equivalent charge associated with 1 count in the fuel-gauge counter, expressed in Coulomb or in Ampere/Hours.
VVBT is the assumed battery voltage.
IL(peak) is the peak inductor current.
tprim is the duration of the primary DC-DC conversion phase.
TP is the conversion period time (1 µs).
9
As an example: the capacity of a typical CR2032 battery (220 mAh) is represented by a total of 50·10 counts.

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9. Register map
NBM7100A/B
Table 25. Condensed register map
Register

Bit

No
.

HEX

7

6

5

4

3

2

1

0

Register
name

R/W

0

0x00

lowbat

ew

alrm

-

-

-

-

rdy

statusR

1

0x01

chengy[31]chengy[30]chengy[29]chengy[28]chengy[27]chengy[26]chengy[25]chengy[24]chenergy

R

2

0x02

chengy[23]chengy[22]chengy[21]chengy[20]chengy[19]chengy[18]chengy[17]chengy[16]chenergy

R

3

0x03

chengy[15]chengy[14]chengy[13]chengy[12]chengy[11]chengy[10]chengy[9]chengy[8]chenergy

R

4

0x04

chengy[7]chengy[6]chengy[5]chengy[4]chengy[3]chengy[2]chengy[1]chengy[0]chenergy

R

5

0x05

-

-

-

vcap[4]vcap[3]vcap[2]

vcap[1]vcap[0]

vcap

R

6

0x06

-

-

-

vchend[4]vchend[3]vchend[2]vchend[1]vchend[0]vchend

R

7

0x07

-

-

-

-

-

-

prof[5]prof[4]

profile_msb

R/W

8

0x08

prof[3]prof[2]

prof[1]

prof[0]

rstpf

act

ecm

eod

command

R/W

9

0x09

vfix[3]vfix[2]

vfix[1]

vfix[0]vset[3]vset[2]

vset[1]vset[0]

set1

R/W

10

0x0A

ich[2]

ich[1]

ich[0]

vdhhizvmin[2]vmin[1]vmin[0]

set2

R/W

11

0x0B

automode

-

-

eew

vew[3]

vew[2]

vew[1]

vew[0]

set3

R/W

12

0x0C

-

-

-

vcapmax

-

-

-

-

set4

R/W

13

0x0D

-

-

-

-

-

-

opt_marg[1]opt_marg[0]

set5

R/W

At startup all bits are cleared except for:prof[5:0]

00001

Profile_index = 1

vset[3:0]

1001

Vset = 3.0 V

ich[2:0]100

Ich = 8 mA

automode*

Set for NBM7100A (I²C) only

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10. Programming Tables
10.1. Status information
Table 26. status Register - Status information
Register 0
Explanation
0x00(read)

Reset condition

bit [7], Low battery input
voltage (vmin)

Once set, this alarm is not cleared without
power cycling the device.

Occurs in Charge state.
vmin = 1: Indicates that a low battery
condition (VMIN threshold) occurred during
charge state.
VVBT < VMIN

bit [6], Capacitor input voltage Occurs in Active state.
Early warning (ew)ew = 1: Indicates that the storage capacitor
voltage has fallen below the VEW threshold
during active state.
VCAP < VEW
RDY pin pulses low for tEW

Cleared at the start of the next charging
cycle.

bit [5], VDH output Alarm(alarm)Occurs in Active state.
Cleared at the start of the next charging
alarm = 1: Indicates that a VDH alarm
cycle.
condition occurred during active state (toohigh load current or too low voltage at VCAP).
VDH < VSETRDY is driven low.

bit [0], Ready (rdy)rdy = 1: Output status indication. See
Section 8.4.1.2.

10.2. Mode controls
Table 27. command and set3 Registers - Mode control
Register 8
Code (bin)
0x08(write)Function

Remarkbit [0] eod(enable On-demand)

0

off

-

1

on

-

bit [1] ecm(enable Continuous mode)

0

off

-

1

on

-

bit [2] act(force Active state)

0

off

-

1

on

force active

bit [3] rstpf(reset optimizer)

0

-

-

1

reset

reset optimizer result of active profile
prof[5:0]

0

off

default for NBM7100B version [1]1ondefault for NBM7100A version

Register 11 (write)
bit [7] automode[1]

NBM7100B cannot be written to 1.

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10.3. VDH Output voltage control (VSET)
Table 28. set1 Register - Output voltage control vset[3:0]: (VSET)
Register 9
Code (bin)
0x09(write)

VSET

Unit

bits [3:0]

0000

1.8

V

0001

2.0

V

0010

2.2

V

0011

2.4

V

0100

2.5

V

0101

2.6

V

0110

2.7

V

0111

2.8

V

1000

2.9

V

default 1001

3.0

V

1010

3.1

V

1011

3.2

V

1100

3.3

V

1101

3.4

V

1110

3.5

V

1111

3.6

V

Table 29. set1 Register - End-of-charge voltage vfix[3:0]: (VFIX)
Code (bin)Register 9 [1]0x09(write)

VFIX

Unit

bits [7:4]

0001

3.4

V

0010

4.4

V

0011

5.2

V

0100

5.9

V

0101

6.5

V

0110

7.1

V

0111

7.7

V

1000

8.2

V

1001

8.7

V

1010

9.1

V

1011

9.5

V

1100

9.9

V

1101

10.3

V

1110

10.7

V

1111

11.0

V

10.4. Capacitor end-of-charge voltage (VFIX)

VFIX applies if prof[5:0] = 0h
(profile = 0)[1]

The default state is 0000. This register should be set to a defined value if prof = 0h.

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10.5. Capacitor maximum storage voltage (VCAP(MAX))
Table 30. set4 Register - Maximum storage voltage vcapmax: (VCAP(MAX))
Code (bin)
VCAP(MAX)
Register 12
0x0C(write)Unit

bit [4]

default 0

9.9

V

1

11.0

V

10.6. VBT pin minimum input voltage comparator threshold (VMIN)
Table 31. set2 Register - Input threshold voltage vmin[2:0]: (VMIN)
Code (bin)Register 10
0x0A(write)

VMIN

Unit

bits [2:0]

default 000

2.4

V

001

2.6

V

010

2.8

V

011

3.0

V

100

3.2

V

ICH

Unit

000

2.0

mA

001

4.0

mA

default 010

8.0

mA

011

16.0

mA

emergency charge, ICH = max 100

50.0

mA

10.7. Capacitor charge current (ICH)
Table 32. set2 Register - Charge current ich[2:0]: (ICH)
Code (bin)Register 10
0x0A(write)bits [7:5]

do not use

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101
110
111

undefined

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10.8. CAP pin input voltage comparator Early Warning voltage (VEW)
Table 33. set3 Register - Early Warning voltage vew[3:0] and eew (VEW)
Code (bin)VEW
Register 11
0x0B(write)Unit

bits [3:0]

default 0000

2.4

V

0001

2.6

V

0010

2.8

V

0011

3.0

V

0100

3.2

V

0101

3.4

V

0110

3.6

V

0111

4.0

V

1000

4.4

V

1001

4.8

V

0

off

1

on

Bit [4] EEW (enable early warning)

10.9. VDH switch configuration
Table 34. set2 Register - VDH switch configuration vdhhiz
Code (bin)Register 10
0x0A(write)bit [4], VDH high-impedance modein Standby and Active states

Parameter

0

VVDH = VVBT

1high impedance

10.10. Optimizer profile selection
Table 35. profile_msb and command Registers - Optimizer profiles: prof[5:0]
Code (bin)ProfileRegister 7 & 8number
0x07 & 0x08
(write)Remarkbits R7[1:0] R8[7:4]
If profile = 0 is selected, no
optimization occurs, VFIX isapplied

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00 0000-

Fixed mode

default 00 0001

1-00 0010

2

-

….

..

-

11 111163-

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10.11. Optimization margin voltage
Table 36. set5 Register - Optimization margin: opt_marg[1:0]Register 13
Code (bin)0x0D(write)bits [1:0]Target VSTORE

Unit

00

minimum

3.41

V

01

nominal

4.39

V

10

safe

5.21

V

extra safe

5.91

V

default 11

10.12. Fuel gauge
Table 37. chengy Registers: Fuel gauge
Register 1 - 4
Explanation
0x01 - 0x04
(read)
Register [1:4]

Register 1 (MSB): 4 (LSB) represents
the 32 bit result of the energy
measurement. See
Section 8.4.6

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Reset condition

Reset at the start of the next charge
cycle.

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10.13. Storage capacitor voltage status (VCAP)
Table 38. vcap and vchend Registers - Storage capacitor status vcap[4:0] (VCAP) and end of charge vchend[4:0]comparator thresholds associated for vfix[3:0]Note: Register 5 (VCAP) is only maintained during charge and active state. In case VCAP voltage drops in STB state due toleakage this is not represented. Register 6 (VCHEND) is set at the start of the CHARGE state.
Register 5 Actual VCAP
0x05
(read)

Code (bin)

VCAP; VCHEND

00000

1.40 V

00001

1.51 V00010

1.80 V

00011

2.19 V

00100

2.40 V

00101

2.60 V00110

2.79 V00111

3.01 V

01000

3.20 V

01001

3.41 V01010

3.61 V

01011

3.99 V01100

4.39 V

01101

4.80 V01110

5.21 V

01111

5.59 V

10000

5.91 V

10001

6.02 V

10010

6.40 V

10011

6.55 V

10100

6.80 V

10101

7.14 V10110

7.23 V10111

7.68 V11000

8.19 V

11001

8.65 V11010

9.10 V11011

9.53 V11100

9.91 V

11101

10.33 V11110

10.69 V11111

11.07 V

Register 6 Target Charge voltage (VCHEND)
0x06(read)
bits [4:0]

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Coin cell battery life booster with adaptive power optimization

11. Application and implementation
11.1. Application information
Note: Application implementation information in the following sections is not part of the Nexperia component
specification. Nexperia’s device users are responsible for determining suitability of components for their purposes, aswell as validating and testing their design implementation to confirm system functionality.
The NBM7100A/B is an integrated power management device ideally suited at transferring energy from high impedancebatteries at a programmable rate to an intermediate storage capacitor where it is subsequently supplied to pulse current
loads. The two-stage transfer process minimizes stress on the battery extending the lifetime.

11.2. Typical application
A typical implementation consists of a radio frequency microcontroller, and a NBM7100A/B pulse load power management
device.
CSTORE
L
CBYP
LX1

VBAT

CVBT

LX2 CAP
VDHS

VBT

VDH

VDP
NBM7100A

CVDH

CVDP

1k

1k

SENSO RSCLSDARF MCU

RDY
ADR
100 k

START
TST

VSS

VSS P

100 k

aaa-036462

Fig. 51. Example application

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Table 39. Design requirements
Parameter

ValuesBattery typeCR2032

Input (battery) voltage

2.4 ≤ VVBT ≤ 3.0 V

Regulated output voltage
at VDH pin (Active state)

1.8V ≤ VSET ≤ 3.6 V

Load profile current

up to 100 mA

Load profile duration

up to 200 ms

VCAP(MAX)

11 V

Use optimizer

No

Cstore capacitor type

polymer

11.3. DC-DC switching frequency and inductor selection
The internal DC-DC converter operates at a fixed frequency of approximately 1 MHz. It is not user adjustable. It is designed
to operate with 15 µH (± 20%, standard tolerance) and a saturation current rating of 1 A (minimum). Using an inductor withsignificantly different ratings may cause control loop instability.
Table 40. Recommended inductors
Type number
L (µH)DCR (mΩ)saturation current

Size (l × w × h)mmvendor

XGL4040-153ME

15

80

1.2

4 × 4 × 4.1

Coilcraft

SRN4018-150M

15

264

1.1

4 × 4 × 1.8

Bournes

74404042150

15

210

1.4

4 × 3.3 × 1.8

Wurth

11.4. Output voltage setting, VSETThe VDH output pin is regulated at the value of VSET during the active state. The default value is 3.0 V and may be adjusted
in register 0x09[3:0]. Refer to Setting VDH output voltage, VSET (Active state).

11.5. Input capacitor, CVBT and charge current, ICH setting
During the charge state the DC-DC converter operates in boost mode. A constant current is drawn from the VBT pin
according the ich setting in register 0x10[7:5]. The capacitor ripple current is negligible and a 6.3V ceramic, 1 µF (minimum)
located close to the VBT pin is suggested.
The default charging current, ICH, is 8 mA. It can be adjusted in the set2 register 0x10[7:5] via the serial interface.

11.6. Output capacitors, CVDP and CVDH
The VDP pin connects to VBT via an internal power switch in all states, except Active where it is connected to the regulated
DC-DC output, VDH. The VDP output cannot be disabled via serial interface and as it is intended to supply always 'on'system loads of up to 10 mA. A 6.3V, 1 µF ceramic located close to the VDP pin is suggested.
The VDH pin is the output of the DC-DC converter during an active cycle. To ensure stability and low output ripple under all
DC-DC operating conditions, a derated capacitance of 22 µF is recommended. Check manufacturer derating curves andselect a suitable capacitor voltage rating to achieve the derated minimum. In this example, a 16 V, 22 µF, X7R with < |-10| %DC bias is chosen. The VDH output may be disabled when not in the Active state by setting vdhhiz = 1.

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11.7. Storage capacitor, CSTORE
Sizing the energy storage capacitor depends on the worst case load profile required in the application. A suggested
approach is to calculate the energy in µJ required to support the load pulse. The area under the curve gives a first orderapproximation of the minimum energy needed for the load, not considering conversion losses or leakage currents. See
figure Fig. 37.
The type (ceramic, electrolytic, polymer, film, supercapacitor) of a single storage capacitor, or parallel combination ofmultiple capacitors used in an application depends on: PCB area available, volume available within the end-productenclosure, cost, etc. The critical factors in the final selection are: 1) a voltage rating higher than VCAP(MAX), and 2) anequivalent series resistance (ESR) less than 1 Ω.
1. Area under pulse load portion of the curve (charge in microcoulombs). CHG = tON × IPK in µC. Wherea. tON = duration of the load pulse in ms.
b. IPK = load pulse current in mA.
2. Calculate the energy, E, in microjoules, µJ by multiplying above by VSET and add margin for energy conversion andleakage losses: 15 - 20%. Assume 20% as a starting point for a factor of 1.2.
E = charge × voltage = CHG × VSET × 1.2 in µJ.
3. Calculate ΔVCSTORE = (VCSTORE(high) - VCSTORE(low)), where
a. VCSTORE(low) = VSET + 0.3 V. Add 0.3 V, or greater, to the regulated VSET voltage to account for DC-DC dropout when
the capacitor voltage depletes close to the regulation voltage.
b. VCSTORE(high) = VFIX in 0x09[7:4], and VFIX ≤ VCAP(MAX). See Section 8.4.2.3.
2
2
4. Calculate nominal CSTORE capacitance in µF: CSTORE = (2 × E) / (VCSTORE(high) - VCSTORE(low) ) µF
5. Apply appropriate voltage and temperature ratings based on storage capacitor type: Aluminum electrolytic, Aluminium
polymer, ceramic, supercapacitor, etc.
6. Select standard value larger than calculated in step 4 with an ESR < 1 ohm and voltage rating larger than VCAP(MAX).
Additional ceramic capacitors, CBYP may be used to decrease the effective ESR.
7. Test system under load profile used in step 1. Additional margin may be required to account for early warning responsetime and serial port communication from microcontroller. Iterate as necessary.
In this design example a load of 100 mA for 10 ms is chosen. Calculation steps show below:
1. CHG = 100 mA × 10 ms = 1000 µC
2. E = 1000 µC × 3.0 V × 1.2 = 4320 µJ (20% margin assumed in 1.2 multiplier)
3. a. VCSTORE(low) = VSET + margin V = 3.0 V + 0.5 V (extra conservative) = 3.5 V
b. Set VCSTORE(high) = Vfix = VCAP(MAX) = 11 V
22
4. CCSTORE(nom) = 2 × 4320 µJ / (11 V - 3.5 V ) = 79.4 µF
5. Assume Cstore capacitor tolerance of ± 20 % (typical for an electrolytic). CCSTORE(actual) = 79.4 µF × 1.2 = 95.3 µF.
6. Select a 16 V rated capacitor with closest standard value of 100 µF.
7. Select 16 V (or higher) rated, low ESR parallel ceramic, CBYP = 10 µF

11.8. External resistors
NBM7100A: I²C SCL and SDA pull-up resistors: consult with Table 12, the host controller data sheet and industry I²C
specifications to size the SCL and SDA pin pullup resistors. For this application example, PCB trace capacitance, Cb,
is assumed to be < 400 pF, allowing Fast-mode Plus (1 Mbit/s) data transfer. 1 kΩ resistances as indicated in example
application diagram are used as a compromise between signal integrity and power consumption.
NBM7100A ADR pin pullup or pull-down resistor: Refer to Table 18 for available slave addresses. For a '1' connect the ADR
pin to the VDP pin via a pullup resistor. For '0' connect the ADR pin to the VSS pin with a pull-down resistor. A standard
resistor value between 1kΩ and 100 kΩ is suggested, but can be omitted so long as a '1' or '0' electrical connection is madevia PCB trace. A pull-down of 100 kΩ is chosen for this example.
NBM7100A: START pin resistor: To prevent spurious initiation of Auto mode during power-up or due to a high-Z condition
from an external host, a pull-down resistor is recommended. The value of resistor should be low enough to ensure the
START pin is held low when not being actively driven, and high enough to prevent loading the external host controller output
when driven high. A pull-down of 100 kΩ is chosen for this example.

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11.9. Suggestions for controlling NBM7100A/B via serial interface
At initialization:
1. Do not initiate any read or write sequences until at least 20 ms after the NBM7100A/B has completed power-on reset(battery insertion).
2. As required by the application after POR, update default registers as needed:a. Write 0x10: vmin, vdhhiz, ich.
b. Write 0x11: vew, eew. Monitoring the early warning indication is suggested.
c. Write 0x12: vcapmax.
d. Write 0x13: opt_marg.
Initiating On-demand
1.
2.
3.
4.
5.

Write 0x08 and 0x09: set prof number or use Vfix.
Write 0x09: vset and vfix. vfix required if optimizer not used.
Write 0x08: set eod bit.
Monitor RDY pin with GPIO, or poll 0x00[0] for RDY = 1. When RDY =1, VDH = VSET.
Apply pulsed load and monitor RDY pin for ew, or continuously poll 0x00 for alrm, ew, and lowbat indications
a. If ew via RDY or 0x00, disable load, write 0x08[2:0] as 000b to enter standby. Capacitor is near depletion.
b. If alrm, disable load, write 0x08[2:0] as 000b to enter standby. The DC-DC is no longer able to regulate VDH due tooverload or capacitor is near depletion.
c. If lowbat, battery is becoming depleted and needs replacement. Operation may continue.
6. Load pulse complete, write 0x08[2:0] as 000b to enter standby.
7. Repeat sequence for subsequent On-demand cycles.
Initiating Continuous
1.
2.
3.
4.

Write 0x08 and 0x09: set prof number or use VFIX.
Write 0x09: vset and vfix. vfix required if optimizer not used.
Write 0x08: set ecm bit.
Monitor RDY pin with GPIO, or poll 0x00[0] for RDY = 1.
When RDY =1, Write 0x08[2] to enter active mode, VDH = VSET.
5. Apply pulsed load and monitor RDY pin for ew, or continuously poll 0x00 for alrm, ew, and lowbat indications
a. If ew via RDY or 0x00, disable load, write 0x08[2:0] as 000b to enter standby. Capacitor is near depletion.
b. If alrm, disable load, write 0x08[2:0] as 000b to enter standby. The DC-DC is no longer able to regulate VDH due tooverload or capacitor is near depletion.
c. If lowbat, battery is becoming depleted and needs replacement. Operation may continue.
6. Load pulse complete, write 0x08[2:0] as 000b to enter standby; or 0x08[2:0] as 010b to return to Continuous mode.
7. Repeat sequence for subsequent Continuous mode cycles.

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11.10. Application curves
VVBT = 3.0 V; CVBT = 1 µF; CVDP = 1 µF; CVDH = 22 µF; L = 15 µH; unless otherwise specified.
aaa-036688

VVBT ramps from 0 to 3 V in 12.5 ms

aaa-036689

VVBT ramps from 0 to 3 V in 5 µs

Fig. 52. POR (VBT slow ramp)

Fig. 53. POR (VBT fast ramp)
aaa-036690

VVBT = VDP = VDH = 3 V
VFIX = 11 V; ICH = 8 mA
Standby → Continuous → Standby

aaa-036691

VVBT = VDP = VDH = 3 V
VFIX = 11 V; ICH = 8 mA
Continuous mode: monitor, refresh, monitor

Fig. 54. Continuous mode

Fig. 55. Continuous mode with VCAP refresh pulses
aaa-036847

VVBT = VDP = VDH = 3 V
VFIX = 11 V; ICH = 8 mA
Continuous mode: monitor, refresh, monitor
Fig. 56. Continuous mode with single VCAP refresh pulse, VCAP: AC coupled

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aaa-036692

VBT = 3 V; VDP = VDH = VSET = 3.6 V
VFIX = 11 V
ILOAD = 2 x 50 mA for 50 ms
Load applied 1.25 sec after RDY = H, then at a 450
ms interval
Fig. 57. Continuous to active mode transition (IVBT)

aaa-036693

VBT = 3 V; VDP = VDH = VSET = 1.8 V
VFIX = 11 V
ILOAD = 2 x 50 mA for 50 ms
Load applied 1.25 sec after RDY = H, then at a 450
ms interval
Fig. 58. Continuous to active mode transition (IVBT)
aaa-036694

VBT = 3 V; VDP = VDH = VSET = 3.6 V
VFIX = 11 V
ILOAD = 100 mA for 100 ms
Load pulse applied at 1.25 sec after RDY = H
Fig. 59. Continuous to active mode transition (ILOAD)

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aaa-036695

aaa-036696

VVBT = 3 V; VDP = VDH = VSET = 3.6 V
VFIX = 11 V
ILOAD = 100 mA for 100 ms
Load applied 1.25 sec after RDY = H transition

VVBT = 3 V; VDP = VDH = VSET = 1.8 V
VFIX = 11 V
ILOAD = 50 mA for 200 ms
Load applied 1.25 sec after RDY = H transition

Fig. 60. On-demand to active mode transition (ILOAD)

Fig. 61. On-demand to active mode transition (ILOAD)
aaa-036697

VBT = 3 V
VDH pin: high-Z (stdby and charge)
VDH = VSET = 3.6 V (active)
VFIX = 11 V
ILOAD = 100 mA for 100 ms
Load applied 1.25 sec after RDY = H transition
Fig. 62. On-demand to active mode transition (vdhhiz = 1)

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aaa-036699

aaa-036698

VVBT = 3 V; VDP = VDH = VSET = 3.6 V
Optimizer profile 1 enabled, Opt margin ='safe' (5.21 V)
VEW = 4.8 V
ILOAD = 50 mA for 100 ms (load pulses 1-10, 12-15)
ILOAD = 50 mA for 130 ms (11th load), triggers EW(RDY briefly low)

VVBT = 3 V; VDP = VDH = VSET = 3.6 V
ILOAD = 50 mA for 100 ms

Fig. 63. Optimizer start, down regulation, Early Warning Fig. 64. Start pulse short - 10 µs (NBM7100A)
enabledaaa-036700

VVBT = 3 V; VDP = VDH = VSET = 3.6 V
ILOAD = 50 mA for 100 ms

aaa-036701

VVBT = 3 V; VDP = VDH = VSET = 3.2 V
VEW = 4.4 V
ILOAD = 100 mA for 160 ms

Fig. 65. Start pulse long - 4.5 sec (NBM7100A)

Fig. 66. Load pulse - 0 to 100 mA , Early Warning
enabled (NBM7100A)

11.11. Power supply recommendations
The device is designed to operate from a battery with a voltage range of 2.4 V to 5.5 V. VVBT should connect directly to thepositive battery terminal with a bypass capacitor of CVBT (see Section 7.5). In most situations, using an input capacitance(CVBT) of 1 μF is sufficient to prevent the supply voltage from dipping during device operation.

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12. Layout
Layout guidelines
Improper layout can cause unstable operation, load regulation problems, increased ripple and noise. For best performance,
all traces should be kept short.
The CVBT, CVDH, CSTORE, and CVDP capacitors must be placed close to the device to minimize the effects that parasitic trace
inductances may have on normal operation.
The DC-DC converter has two loops: boost mode from VBT to CAP and buck mode from CAP to VDH. For optimal
performance, loop areas should be as small as possible.
Serial bus line routing is least critical, however, avoid running serial bus traces near or under the DC-DC converter loops.

VSS P

VDH
VDP

VBT

aaa-036460
Circle indicates CR2032 diameter
Fig. 67. layout example

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13. Package information
13.1. Package outline
DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
SOT763-1
16 terminals; body 2.5 x 3.5 x 0.85 mm

B

D

A

A
E

A1

c

detail X

terminal 1
index area

terminal 1
index area

C

e1
e

b

2

7

y

y1 C

v M C A B
w M C

L

1

8

Eh

e
16

9

15

10
Dh

X

0

2.5

5 mm

scale
DIMENSIONS (mm are the original dimensions)
UNIT

A(1)
max.

A1

b

c

D (1)

Dh

E (1)

Eh

e

e1

L

v

w

y

y1

mm

1

0.05
0.00

0.30
0.18

0.2

3.6
3.4

2.15
1.85

2.6
2.4

1.15
0.85

0.5

2.5

0.5
0.3

0.1

0.05

0.05

0.1

Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCESOUTLINE
VERSION

IEC

JEDEC

JEITA

SOT763-1---

MO-241---EUROPEAN
PROJECTION

ISSUE DATE
02-10-17
03-01-27

Fig. 68. Package outline SOT763-1 (DHVQFN16)

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14. Revision history
Table 41. Revision history
Document ID

Release date

Data sheet status

Change notice Supersedes

NBM7100 v.2

20240802

Product data sheet-

Modifications:

•
•
•
•

NBM7100 v.1

20230629

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NBM7100 v.1

Table 7: added reference to JEDEC51-5 and -7.
Table 10: 1) EFFch corrected; 2) IQ_ACT corrected.
Fig. 50: figure corrected.
Fig. 63: graph corrected.
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15. Legal information

injury, death or severe property or environmental damage. Nexperia and its
suppliers accept no liability for inclusion and/or use of Nexperia products insuch equipment or applications and therefore such inclusion and/or use is at
the customer’s own risk.

Data sheet status

Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of thisdocument, and as such is not complete, exhaustive or legally binding.

Document status[1][2]

Product
status [3]Definition

Objective [short]data sheet

Development

This document contains data fromthe objective specification for
product development.

Preliminary [short]data sheet

Qualification

This document contains data fromthe preliminary specification.

Product [short]data sheet

Production

This document contains the productspecification.

[1]
[2]
[3]

Please consult the most recently issued document before initiating orcompleting a design.
The term 'short data sheet' is explained in section "Definitions".
The product status of device(s) described in this document may havechanged since this document was published and may differ in case ofmultiple devices. The latest product status information is available on
the internet at https://www.nexperia.com.

Definitions
Draft — The document is a draft version only. The content is still underinternal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any representations or
warranties as to the accuracy or completeness of information included hereinand shall have no liability for the consequences of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheetwith the same product type number(s) and title. A short data sheet isintended for quick reference only and should not be relied upon to containdetailed and full information. For detailed and full information see the relevant
full data sheet, which is available on request via the local Nexperia sales
office. In case of any inconsistency or conflict with the short data sheet, thefull data sheet shall prevail.
Product specification — The information and data provided in a Productdata sheet shall define the specification of the product as agreed between
Nexperia and its customer, unless Nexperia and customer have explicitly
agreed otherwise in writing. In no event however, shall an agreement bevalid in which the Nexperia product is deemed to offer functions and qualities
beyond those described in the Product data sheet.

Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, Nexperia does not give any
representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for theconsequences of use of such information. Nexperia takes no responsibility
for the content in this document if provided by an information source outsideof Nexperia.
In no event shall Nexperia be liable for any indirect, incidental, punitive,
special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removalor replacement of any products or rework charges) whether or not suchdamages are based on tort (including negligence), warranty, breach ofcontract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, Nexperia’s aggregate and cumulative liability towards customer
for the products described herein shall be limited in accordance with theTerms and conditions of commercial sale of Nexperia.
Right to make changes — Nexperia reserves the right to make changes
to information published in this document, including without limitation
specifications and product descriptions, at any time and without notice. This
document supersedes and replaces all information supplied prior to the
publication hereof.
Suitability for use — Nexperia products are not designed, authorized or
warranted to be suitable for use in life support, life-critical or safety-criticalsystems or equipment, nor in applications where failure or malfunctionof an Nexperia product can reasonably be expected to result in personal

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Applications — Applications that are described herein for any of theseproducts are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using Nexperia products, and Nexperia accepts no liability forany assistance with applications or customer product design. It is customer’ssole responsibility to determine whether the Nexperia product is suitableand fit for the customer’s applications and products planned, as well as
for the planned application and use of customer’s third party customer(s).
Customers should provide appropriate design and operating safeguards tominimize the risks associated with their applications and products.
Nexperia does not accept any liability related to any default, damage, costs
or problem which is based on any weakness or default in the customer’s
applications or products, or the application or use by customer’s third party
customer(s). Customer is responsible for doing all necessary testing for thecustomer’s applications and products using Nexperia products in order toavoid a default of the applications and the products or of the application or
use by customer’s third party customer(s). Nexperia does not accept any
liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above thosegiven in the Recommended operating conditions section (if present) or theCharacteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — Nexperia products are
sold subject to the general terms and conditions of commercial sale, as
published at http://www.nexperia.com/profile/terms, unless otherwise agreed
in a valid written individual agreement. In case an individual agreement isconcluded only the terms and conditions of the respective agreement shallapply. Nexperia hereby expressly objects to applying the customer’s generalterms and conditions with regard to the purchase of Nexperia products bycustomer.
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or construed as an offer to sell products that is open for acceptance or the
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or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a priorauthorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific Nexperia product is automotive qualified, theproduct is not suitable for automotive use. It is neither qualified nor tested inaccordance with automotive testing or application requirements. Nexperia
accepts no liability for inclusion and/or use of non-automotive qualified
products in automotive equipment or applications.
In the event that customer uses the product for design-in and use inautomotive applications to automotive specifications and standards,
customer (a) shall use the product without Nexperia’s warranty of the
product for such automotive applications, use and specifications, and (b)whenever customer uses the product for automotive applications beyond
Nexperia’s specifications such use shall be solely at customer’s own risk,and (c) customer fully indemnifies Nexperia for any liability, damages or failed
product claims resulting from customer design and use of the product for
automotive applications beyond Nexperia’s standard warranty and Nexperia’s
product specifications.
Translations — A non-English (translated) version of a document is forreference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.

Trademarks
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10.8. CAP pin input voltage comparator Early
Warning voltage (VEW)....................................................... 41

Contents
1. General description...................................................... 1
2. Features and benefits.................................................. 1
3. Applications.................................................................. 1
4. Ordering information....................................................2
5. Marking.......................................................................... 2
6. Pin configuration and description.............................. 2
6.1. Pin configuration..........................................................2
6.2. Pin description............................................................. 3
7. Specifications................................................................4
7.1. Limiting values.............................................................4

10.9. VDH switch configuration..................................... 41
10.10. Optimizer profile selection..................................41
10.11. Optimization margin voltage.................................. 42
10.12. Fuel gauge............................................................42
10.13. Storage capacitor voltage status (VCAP)................ 43
11. Application and implementation..............................44
11.1. Application information.............................................44
11.2. Typical application....................................................44
11.3. DC-DC switching frequency and inductor selection..45
11.4. Output voltage setting, VSET.................................... 45

7.2. ESD ratings................................................................. 4

11.5. Input capacitor, CVBT and charge current, ICH
setting................................................................................. 45

7.3. Thermal information.....................................................4

11.6. Output capacitors, CVDP and CVDH.......................... 45

7.4. Recommended operating conditions........................... 4

11.7. Storage capacitor, CSTORE....................................... 46

7.5. Recommended components........................................ 5

11.8. External resistors..................................................... 46

7.6. Electrical characteristics.............................................. 5

11.9. Suggestions for controlling NBM7100A/B via
serial interface....................................................................47

7.7. Dynamic characteristics...............................................7
7.8. Typical characteristics..................................................97.9. Timing diagrams........................................................ 16
7.10. Test circuits..............................................................18
8. Detailed description................................................... 19
8.1. Functional diagram.................................................... 19
8.2. Overview.................................................................... 19
8.3. Operating modes....................................................... 23
8.3.1. Mode overview....................................................... 23
8.3.2. Continuous mode....................................................24
8.3.3. On-demand mode...................................................24
8.3.4. Auto mode (NBM7100A only)................................24

11.10. Application curves..................................................48
11.11. Power supply recommendations............................ 51
12. Layout........................................................................ 52
13. Package information................................................ 53
13.1. Package outline....................................................... 53
14. Revision history........................................................54
15. Legal information......................................................55© Nexperia B.V. 2024. All rights reserved

For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 2 August 2024

8.4. Feature description.................................................... 25
8.4.1. Chip control............................................................ 25
8.4.2. States of operation................................................. 27
8.4.3. DC-DC converter.................................................... 30
8.4.4. VDP and VDH output configuration.................... 31
8.4.5. Adaptive power optimization...................................33
8.4.6. Fuel Gauge.............................................................36
9. Register map...............................................................37
10. Programming Tables................................................ 38
10.1. Status information................................................. 38
10.2. Mode controls.......................................................... 38
10.3. VDH Output voltage control (VSET).......................... 39
10.4. Capacitor end-of-charge voltage (VFIX)....................39
10.5. Capacitor maximum storage voltage (VCAP(MAX)).....40
10.6. VBT pin minimum input voltage comparator
threshold (VMIN)................................................................ 40
10.7. Capacitor charge current (ICH)..............................40

NBM7100
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Rev. 2 — 2 August 2024

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