Monolithic pixel detectors fabricated with single anddouble SOI wafers

1High Energy Accelerator Research Organiation (KEK), Tsukuba, Japan
University of Tsukuba, Tsukuba, Japan
3
Kyoto University, Kyoto, Japan
E-mail: tmiyoshi@post.kek.jp
2

Monolithic pixel detectors have been fabricated with single and double SOI wafers using SOI
technology for a next-generation radiation sensor. A single SOI sensor consists of a thin SOI layer
as SOI-CMOS circuit, a thick silicon substrate as a sensor, and a buried oxide layer as an insulator
between two silicon layers. A double SOI sensor has another thin SOI layer to prevent unwantedeffects such as the back-gate effect, the sensor – circuit crosstalk and total ionization dose effect.
In 2013, the integration type pixel sensor, INTPIXh2, has been fabricated for the evaluation of
single and double SOI sensors. The document describes comparison test results in single anddouble SOI sensors by measuring the leakage current and X-ray spectra. X-ray spectra in double
SOI sensors were obtained for the first time. The problem and future prospect are discussed.

Technology and Instrumentation in Particle Physics 2014
2-6 June, 2014
Amsterdam, the Netherlands*Speaker Copyright owned by the author(s) under the terms of the Creative Commons Attribution-NonCommercial-ShareAlike Licence.

http://pos.sissa.it

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Toshinobu Miyoshi * 1, Yasuo Arai1, Yowichi Fujita1, Kazuhiko Hara2, Shunsuke
Honda2, Yoichi Ikegami1, Yukiko Ikemoto1, Shingo Mitsui1, Ayaki Takeda3, Kazuya
Tauchi1,Toru Tsuboyama1, Yoshinobu Unno1

Monolithic pixel detectors fabricated with single and double SOI wafers

Toshinobu Miyoshi

1.Introduction

2. Design of INTPIXh2
The integration-type pixel sensor, INTPIXh2, was fabricated in the first multi-project
wafer (MPW) run in 2012 (MX1594). Table 1 shows the specification of INTPIXh2. The
pixel size is 18 x 18 m2 and the number of pixels is 280 (H) x 240 (V) resulting in asensor area of 5.04 x 4.32 mm2. The chip includes raw and column address decoders, 3bias circuit blocks, and a column buffer array. IO pads are available on one side, andinclude analog buffer circuit blocks. In the process, NCZ, NFZ and DSOI wafers wereutilized. The DSOI wafer was fabricated using NCZ wafers and therefore the resistivityof the substrate is the same as NCZ wafer, about 700 cm. The substrate thickness ofthe NCZ and DSOI samples is 300 m. The resistivity of NFZ substrate is 2-7 k cm
depending on process. The substrate thickness is 500 m. Operation voltage was set to100 V for NCZ and NFZ sensors. In the DSOI sensor, operation voltage was set to 60 Vin section 3 or 100 V in section 4. 2PoS(TIPP2014)044
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Monolithic pixel sensors using SOI technology could be among the next generation ofsemiconductor radiation sensor. This is because of the following features: It utilizes SOICMOS process and thus high speed and low noise circuits compared with bulk CMOS
ones are available; No bump bonding is needed; the sensor contact area can easily be
reduced to less than 1 m resulting in high sensor gain. We have developed SOI pixel
sensors since 2005 as part of the Detector Technology Project (DTP) at KEK, and wereported the performance and evaluation test results in refs. [1-4]. The SOI monolithic
pixel sensor has mainly three known problems. The first is the back-gate effect in whichhigh voltages at the back side of silicon substrate affect the behavior of transistors in theSOI layer. The second is radiation tolerance, especially the total ionization dose (TID)
effect in which holes generated by radiation in the Buried OXide (BOX) layer affect thetransistor performance. The third is the crosstalk between sensor and circuit. To solvethese problems, we are trying several solutions. One solution is to utilize a double SOI(DSOI) wafer including two thin SOI layers. It can be developed by applying the Smart
CutTM method (Soitec) twice [5]. In 2011, we developed the DSOI sensor for the firsttime and observed two major problems. One was the lower breakdown voltage at the edgeof the bias ring due to the remaining middle SOI layer. In addition, the middle SOI layers
between pixels caused a flat potential distribution affecting the charge collection
efficiency. To solve these problems, a test chip named INTPIXh2 was developed in 2012.
Three types of wafers, N-type Czochralski (NCZ), N-type Float Zone (NFZ) and DSOI
were used to develop the INTPIXh2 sensors. We performed comparison tests using thesesensors. In section 2, the design of INTPIXh2 is described. The test results of themeasurement of X-ray spectra and the leakage current are presented in section 3 and 4.
The problems emerging during the test and future prospects are discussed in section 5.

Monolithic pixel detectors fabricated with single and double SOI wafers

Toshinobu Miyoshi

Table 1 Specification of INTPIXh2chip size [mm2]pixel size [m2]# of pixels
Sensitive area [mm2]sensor thickness
[m]

6x6
18x18
280 (H) x 240 (V)5.04 (H) x 4.32 (V)
300
500
300

Fig. 1 shows the pixel circuit and Fig. 2 shows top and side views of the pixel layout. The
INTPIXh2 includes 3 test pixel structures, named “r1(R1)”, “r2(R2)” and “r3(R3)”. The
number of pixel in r1 is 280 (H) x 128(V), in r2, 128 (H) x 112 (V), and in r3, 152 (H) x112 (V). Only pixels in r1 have a gain switch, as shown in Fig. 1, to select high or low
gain mode. R2 only has Buried-N-Well (BNW) between pixels. In the DSOI, each region
has different intermediate SOI shapes because the SOI below transistors can not beremoved. The pixel in r1 has a large DMOS capacitor between pixels and therefore theintermediate SOI area is large, and eventually it is connected between adjacent pixels
aligned vertically. R2 has the smallest intermediate SOI islands. The intermediate SOI in
r1 and r2 is floating. On the other hand, the pixel in r3 has an intermediate SOI contact
and therefore its potential can be controlled. The area of the intermediate SOI layer in apixel is 14 by 14 m. All the pixels have a Buried P-Well (BPW), which is connected tothe sense node (P+), and therefore at the same potential [4].

Fig. 1 INTPIXh2 pixel circuit

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NCZ
NFZ
DSOI

Monolithic pixel detectors fabricated with single and double SOI wafers

Toshinobu Miyoshi

3. Measurement of Am-241 X-ray spectra
X-ray spectra were measured in NCZ-, NFZ-, and DSOI-INTPIXh2 using an Am-241
source. The DAQ system was put into thermostat chamber and kept in at -60 oC. Limitedpixels (100 x 100 pixels) were selected to extract the spectra. Estimated depletion depth
for those is about 150 m for NCZ-, 300 m for NFZ-, and 100 m for DSOI-INTPIXh2,respectively. X-ray was measured in 1 msec per frame, and accumulated 20000 frames,
for a total irradiation time of 20 sec. Am-241 source with 4 MBq was used. Fig. 3 showsan X-ray spectrum in region 3 of NFZ-INTPIXh2. Energies of measurable X-rays are
13.95, 17.75, 20.78, 26.34, and 59.45 keV. With such a thin silicon thickness of SOIsensors, it is difficult to identify the 26.34 keV X-ray peak in some regions. Therefore
part of X-ray peaks were utilized to evaluate the sensor gain. Fig. 4 shows X-ray spectra
for the 3 regions of the NCZ-, NFZ- and DSOI-INTPIXh2 samples. Cluster size
distributions are also shown. Fig. 5 shows the sensor gain curves in each wafer and eachregion. The features of sensors in each wafer were the following:(1) In the NCZ-INTPIXh2, the energy resolution in r1 and r3 was good. Sensor gain washigh in r2. Pixels in r3 showed the best performance because both of the energy
resolution and the sensor gain was good. The sensor gain was low in r1 probably
because it has an additional leak path for gain switch. The energy resolution was notgood in region 2 probably because there is BNW between pixels.
(2) In the NFZ-INTPIXh2, the energy resolution was good for all the regions. Cluster
size was relatively large probably because the NFZ wafer was thick. Because theNFZ wafer had high resistivity, the 59.45 keV X-ray peak was clearly observed.
Sensor gain was low compared with NCZ sensors in r2 and r3. This means theprobability of recombination is slightly high in NFZ wafer partly because the electricfield is weak when applying the same voltage at the back side of wafer. The reason
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Fig. 2 Top and side views of pixels in three regions (r1:left, r2:middle, r3:right).

Monolithic pixel detectors fabricated with single and double SOI wafers

Toshinobu Miyoshi

The best energy resolution for the13.95 keV peak is 6% (rms) with cluster size = 2 at r3of NCZ-INTPIXh2, about 0.8 keV. The pixel circuit has no correlated double sampling(CDS) circuit and therefore the result was not good the other integration-type pixel
sensors in ref. [6]. When the input transistor in the pixel circuit changes from NMOS toPMOS, the resolution might be improved, as shown in ref. [7].

Fig. 3 Am-241 X-ray spectrum measured by r3 of the NFZ-INTPIXh2 SOI sensor.
Characteristic X-ray energies are also shown.

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might also be related to wafer fabrication process. The difference of sensor gain
between regions was found to be small.
(3) In the DSOI-INTPIXh2, specific features were seen in each regions. In r1, the sensor
gain was very low. As explained in section 2, the middle SOI layer between pixels
might cause a flatness of potential and therefore a part of generated charges istrapped in a small region between pixels. In r2, the spectrum shape was almost thesame as NCZ-INTPIXh2. The gain was not decreased because the middle SOI area
is small, as shown in Fig. 2, and there are BNW between pixels. In r3, the sensor
gain was extracted using the limited number of pixels, the limited cluster size andthe 59.45 keV peak, and it was slightly lower. This may have two reasons: anadditional parasitic capacitance between the middle SOI layer and the BPW area, orthat the area of middle SOI layer is large and there is no BNW between pixels. Somecharges could be trapped at the surface between pixels. The energy resolution wasvery bad probably because the potential fluctuation of middle SOI area in each pixel
was high due to high resistivity of middle SOI layer. The resistivity of the middle
SOI layer will be reduced in the next fabrication.

Monolithic pixel detectors fabricated with single and double SOI wafers

Toshinobu Miyoshi

Fig. 5 Pixel gain curves for 3 regions of NCZ-, NFZ-, and DSOI-INTPIXh2. The
numbers near fit graph are the sensor gains in mV/ke.
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Fig. 4 Am-241 X-ray spectra and cluster distributions for 3 regions of NCZ-, NFZ- andDSOI-INTPIXh2.

Monolithic pixel detectors fabricated with single and double SOI wafers

Toshinobu Miyoshi

4. Pixel leakage current

Fig. 6 Temperature dependence of pixel dark rate
7

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Leakage current measurement was performed at different temperatures. In thismeasurement, the back bias voltage was set to 100 V for all sensors. For each temperature,
the average value of pixel output voltage within several integration times was extracted.
The voltage shift corresponds to the pixel leakage current. Fig. 6 shows the Arrhenius
plot of the dark rate in three pixel types of three sensors. When the slope (activationenergy) is close to a half of excitation energy, Eg/2 = 0.56 eV, most of leakage current
source is thermal generation current in the substrate. Pixels with lower activation energies
were seen to exhibit a higher dark current. When the dark rate is 10-3 V/ms, the pixelleakage current in nA/cm2 is equal to 50 x G, where G is the sensor gain in mV/ke,assuming that the substrate leak is dominant in pixel leak current. Other sources might beprotection diode, the gain switch, or any other transistors connected the sensor signal path.
Compared with regions, r2 has the highest leakage current probably because it has BNW
between pixels and therefore there might be a current source at the interface between Si
and BOX above the BNW. The leakage current in r1 was more than that in r3 probably
because the gain switch might form another leakage current path.
The features of leakage current in each region is the following;(1) In NCZ-INTPIXh2, the minimum leakage current was 16 nA/cm2 at -60 oC in r3. The
slope is slightly small compared with Eg/2, implying that there are other current
sources.
(2) In NFZ-INTPIXh2, the leakage current was low. The minimum leakage current was
4 nA/cm2 at -60 oC and r3. The curve was fit except data at -50 and -60 oC. Above 40 oC, the substrate generation current is dominant because the slope is close to Eg/2.
Below 10 nA/cm2, there might be other sources of leakage current.
(3) In DSOI-INTPIXh2, the minimum leakage current was 140 nA/cm2 at -60oC in r3.
The reason of the high leakage current is unknown. The slope is less than a half ofactivation energy and therefore some leakage current sources other than the case ofNCZ and NFZ wafers might be present.

Monolithic pixel detectors fabricated with single and double SOI wafers

Toshinobu Miyoshi

5. Summary and outlook

Acknowledgement
We would like to thank all the members of the SOIPIX collaboration. We appreciate J. Haba
for their continuing support to this project. This work was partly performed under the approval ofthe Photon Factory Program Advisory Committee (Proposal No. 2013G708). This work is also
supported by VLSI Design and Education Center (VDEC), the University of Tokyo with thecollaboration of Cadence Corporation, Synopsys Corporation, and Mentor Graphics Corporation.

References[1] Y. Arai, in proceedings of VIRTEX2013 PoS(Vertex2013)021[2] T. Miyoshi et al., Physics Procedia, Vol. 37 (2012) 1039.
[3] Y. Arai et al., Nucl. Instr. And Meth. A 636 (2011) S31.
[4] Y. Arai et al., Nucl. Instr. And Meth. A 623 (2010) 186.
[5] N. Daval et al., in proceedings of VLSI Technology, Systems, and Applications (VLSI-TSA), 22-24
April (2013).
[6] S. Nakashima, Nucl. Instr. And Meth. A 731, Pages 74-78 (2013)[7] A. Takeda, IEEE Nucl. Sci. Sym. Conference Record, Oct.27 – Nov.2 (2013),
DOI:10.1109/NSSMIC.2013.6829699[8] S. Honda et al., “Total Ionization Damage Compensations in Double Silicon-on-Insulator Pixel
Sensors”, this conference.

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We have developed an integration-type pixel sensor, INTPIXh2, with single and double SOIwafer. In the DSOI-INTPIXh2, the leakage current was higher than that of NCZ- and NFZINTPIXh2, and thus the energy resolution of Am-241 spectra was high. It was realized that
optimization of BPW, BNW and middle SOI area was a key issue when utilizing the DSOI wafer
as a sensor. From the second MPW runs, a double SOI wafer made by a different vendor will beused. The properties of double SOI sensors might be changed even though the basic properties
are expected to be the same. As for the sensor and circuit crosstalk, we will evaluate them byusing counting type pixel sensors currently under design. The TID tolerance study is described in
ref [8]. Our goal in this study is to develop integration-type sensors with 10 mV/ke- of sensor
gain, without the back-gate effect and sensor-circuit crosstalk, and TID tolerance above 10 Mrad.