I2C GPIO Expanders
Increase system flexibility andreusability in the system design

I2C GPIO expanders offer a solution to the challenges faced by system engineers inintegrating next-generation technologies with legacy sub-systems. The use of a common bus
for communication between different sub-systems and peripherals allows for a modular andflexible design that can be reused for multiple purposes. The expanders provide additionalGPIOs, solving the problem of limited GPIOs and enabling the integration of advanced andlegacy peripheral devices. By using I2C GPIO expanders, system engineers can maximize
system reuse and integration of new feature sets, thereby meeting the demands ofconsumers and staying ahead in a rapidly evolving technology landscape.

The newest I2C GPIO expander portfolio offered by Nexperia
provides excellent performance in pin-to-pin compatible
packages with industry-standard footprints. The use of
the I2C interface standard, which is a shared bus based ona controller and target protocol, reduces board routing
complexity and minimizes manufacturing costs. The I2C
bus can be routed throughout the system, which helps in
reducing the number of board layers and maximizing systemreuse. The advantage of I2C is its ability to support multiple
nodes, which increases system flexibility and allows for theintegration of new peripherals and feature sets. Overall,the I2C GPIO expanders from Nexperia offer a cost-effectiveand flexible solution for expanding the number of GPIOs ina system.

Applications› Servers, Routers› Hardware control monitors,› Gaming consoles› TV & Monitors› IOTs, Battery powered applications› Automotive applications like ADAS, BCM, VCU, DCU,Car radio, Instrument cluster› Medical devices using sensors› Controlling and monitoring digital outputs such as LEDsand relays› Reading digital inputs such as switches and sensors› Interfacing with other I2C devices in the system, such asdisplays and sensors› Implementing a multi-master I2C bus for increased systemcomplexity and functionality.

2Features

Benefits

I²C bus to parallel port expander

Eliminates expensive congested PCB since a trace or wire is not needed foreach signal.

Single supply GPIO expander supporting 1.65V to 5.5V operationLowers I/O usage & reduces the system BOM and manufacturing costSerial to parallel (SDA to P0-P16) and parallel to serial (P0-P16) conversion with
I2C protocol

Board-space and Processor-pin saving

Schmitt-trigger action allows slow input transition and better switching noise
immunity at the SCL and SDA inputs

In case of migrating to more advance core processor, the processor's IO
voltage may be connected to a single voltage domain

Low power consumption 2.5uA max

Eases choice to add or remove peripheral devices based on the target feature
set adding to scalability

400kHz operation (FM I2C mode)

50ns spike filter allows further usage in noisy server environment providing
robust solution

Glitch free Power up with all channels configured as inputs with Pull-ups

Lower propagation delay than the competition enabling fast response from I2C
signals to GPIO signals

Latched outputs with 25 mA drive maximum capability for directly driving LEDs

Supports maximal system reuse

Support Polarity Inversion Register and Interrupt feature

Supports usage of multiple NCA9555 on the same bus

External RESET pin to reset state machine and internal registers

Low latency can be achieved using RESET feature

Noise filters on SCL and SDA inputs

Supports multiple NCA9555 I2C GPIO on the same Bus

Specified from -40 °C to +85 °C and -40 °C to +125 °C

Block diagram – NCA9555

NCA9555
P1_0
8-bit

A0
A1A2

P1_1
P1_2

Write pulse

P1_3

GPIO
Ports

P1_4
P1_5

Read pulse

P1_6
P1_7

Input ﬁlter

SCL
SDA

I2C BusControl
P0_0

8-bit

P0_1
P0_2

VCC

Power-on-reset

Write pulse

GPIO
Ports

P0_3
P0_4
P0_5

Read pulse

P0_6

GND

VCC

LP Filter

Figure 1: NCA9555 block diagram

P0_7

INT3Reading and writing to port registers
I2C bus devices are available in a wide range of functions.
Each target device has its own I2C bus address, selectableusing address pins set high (1) or low (0). Information istransmitted byte by byte, and each byte is acknowledged by
the receiver. There can be multiple devices on the same bus,
and more than one IC can act as controller. The controller roleis typically played by a microcontroller.

The NCA9555 is an I²C bus target device. Data is exchanged
between the controller and NCA9555 through write and readcommands using I²C bus. The two communication lines are aserial data line (SDA) and a serial clock line (SCL). Both lines
must be connected to a positive supply via a pull-up resistor
when connected to the output stages of a device. Datatransfer may be initiated only when the bus is not busy.
Controller

Write data
S

Target address

WA<DataAn data bytes

DataA

P

Transmitter

Receiver
SCL>
Controller

Read data
S

TargetSDA

TargetSDA

Target address

RA<DataAn data bytes

S = Start Condition

R/W = Read / Write

A = NOT Acknowledge

P = Stop Condition

DataAP

Transmitter

ReceiverSCL>

A = Acknowledge

Figure 2 : Read and write to ports

Writing to the port registers
Data is transmitted to the NCA9555 by sending the device
address and setting the read-write bit to a logic 0.
The command byte is sent after the address and determines
which register will receive the data following the commandbyte. Eight registers within the NCA9555 are configured tooperate as four register pairs. The four pairs are input port,output port, polarity inversion, configuration registers.

SCL1

2345678• • •9Slave adress
SDAS0

10

Data to port 0

Command byte

0 A2 A1 A0 0Start condition

After sending data to one register, the next data byte issent to the other register in the pair. For example, if thefirst byte is sent to Output Port 0 (register 2), the next byte
is stored in Output Port 1 (register 3). There is no limitationon the number of data bytes sent in one write transmission.
In this way, the host can continuously update a register pair
independently of the other registers, or the host can simply
update a single register.

R/W

A

000

Acknowledge
from slave00010A 0.7

Data to port 1

Data 00.0 A 1.7

Acknowledge
from slave

Data 1

1.0 A

Acknowledge
from slave

P

Stopcondition

Write to porttv(Q)Data out from port 0tv(Q)Data out from port 1

Data valid002aah344

Figure 3 : Write to control registers

4

Reading the port registers
In order to read data from the NCA9555, the bus master mustfirst send the NCA9555 address with the least significant bit
set to a logic 0. The command byte is sent after the addressand determines which register will be accessed. After arestart, the device address is sent again, but this time theleast significant bit is set to a logic 1. Data from the register
defined by the command byte is sent by the NCA9555.
Data is clocked into the register on the rising edge of theacknowledge clock pulse.

After the first byte is read, additional bytes may be read but
the data now reflects the information in the other registerin the pair. For example, if Input Port 1 is read, the next byte
read is Input Port 0. There is no limit on the number of databytes received in one read transmission, but on the final byte
received the bus master must not acknowledge the data.
After a subsequent restart, the command byte contains thevalue of the next register to be read in the pair. For example,
if Input Port 1 was read last before the restart, the registerthat is read after the restart is the Input Port 0.

Data into port 0
Data into port 1
INT
trst(INT)

tv(INT)SCL

1 2 3 4 5 6 7 8 9
Slave adress

SDA

I0.x

I1.x

I0.x

I1.x

Stop conditionS 0 1 0 0 A2 A1 A0 1 A 7 6 5 4 3 2 1 0 A 7 6 5 4 3 2 1 0 A 7 6 5 4 3 2 1 0 A 7 6 5 4 3 2 1 0 1 P

Start condition

R/W Acknowledge
from slave

Acknowledge
from master

Acknowledge
from master

Acknowledge
from master

Non acknowledge
from master

Read from port 0
Read from port 1002aah347

Figure 4 : Read from register

Application design-in information
VCC
3.3V
10kΩ

10kΩ

Controlled switch (CBT)

2kΩ

10kΩ

VCC
SCL

P1_0SDA

P1_1

RESET

P1_2

INT

P1_3Master
controller

SUB-System 2(e.g. Temp sensor)

P1_4
GND

P1_5

INT

P1_6
NCA9555

P1_7

SUB-System 3(e.g. Alarm system)

P0_0

ALARM

P0_1
P0_2
P0_3
P0_4

A2

P0_5

A1

P0_6

A0

P0_7
GND

P0_0, P0_2, P0_3 configured as outputs.
P0_1, P0_4, P0_5 configured as inputs.
P0_6, P0_7 and (P1_0 to P1_7) configured as inputs.
(1) Internal pull-up may be used to eliminate external components.
Figure : 5 Typical Application

SUB-System 1(e.g. Counter)

Enable10 Digit
numerickeypad53.3VWhen the I/Os are used to control LEDs, they are normallyconnected to VCC through a resistor. Since the LED acts as adiode, when the LED is off the I/O VI is about 1.2 V less thanVCC. The supply current, ICC, increases as VI becomes lower
than VCC.

5VVCC

Designs needing to minimize current consumption, such asbattery power applications, should consider maintaining theI/O pins greater than or equal to VCC when the LED is off.
Fig. 7 shows VCC less than the LED supply voltage by at least
1.2 V. Both methods maintain the I/O VI at or above VCC andprevents additional supply current consumption when theLED is off.

LEDPnFigure 7: Device supplied by a lower voltage

Typical charactertics
25
ICC(µA)

2ICC(µA)

20

1.6

15

1.2

100.8

50.4

0-40

-15

103560
Tamb (ºC)

0-40

85

-15

10356085
Temperature (ºC)

fSCL = 400 kHz
VCC = 1.65 V
VCC = 1.8 V
VCC = 2.3 V
VCC = 2.5 V

VCC = 3.3 V
VCC = 3.6 V
VCC = 5.0 V
VCC = 5.5 V

VCC = 1.65 VVCC = 1.8 V
VCC = 2.3 V
VCC = 2.5 V

Supply current versus ambient temperature

VCC = 3.3 V
VCC = 3.6 V
VCC = 5.0 V
VCC = 5.5 V

Standby supply current versus ambient temperature

25ICC(µA)

ICC(mA)

120

0.8

15

0.6

10

0.4

5

0.2

0
1.5

Tamb = 25 ºC; fSCL = 400 kHz
22.5

3

3.5

4

4.5

5
5.5
VCC (V)

Supply current versus supply voltage

0VCC = 5.5 V
Tamb = -40 ºC
Tamb = 25 ºC
Tamb = 85 ºC
0246810121416Number of I/O held LOW

Supply current versus number of I/O held LOW

Product Portfolio
FamilyDescription

VCC (V)

Tamb(°C)

Nr ofpins

Package
nameNCA9555PW

Low-voltage 16-bit I²C and SMBus I/O expander with interrupt output
and configuration registers

1.65 - 5.5-40~85

24

TSSOP24

NCA9555BY

Low-voltage 16-bit I²C and SMBus I/O expander with interrupt output
and configuration registers

1.65 - 5.5-40~85

24

HWQFN24

NCA9539PW

Low-voltage 16-bit I²C and SMBus low-power I/O expander with interrupt output, reset pin and configuration registers

1.65 - 5.5-40~8524TSSOP24

NCA9539BY*

Low-voltage 16-bit I²C and SMBus low-power I/O expander withinterrupt output, reset pin and configuration registers

1.65 - 5.5-40~8524

HWQFN24

NCA9535PW

Low-voltage 16-bit I²C and SMBus low-power I/O expander with interrupt output and configuration registers

1.65 - 5.5-40~8524

TSSOP24

NCA9535BY*

Low-voltage 16-bit I²C and SMBus low-power I/O expander with interrupt output and configuration registers

1.65 - 5.5-40~8524HWQFN24

NCA9595PW

Low voltage 16-bit I²C and SMBus I/O expander with interrupt output,
configuration registers and programmable pull-up resistors

1.65 - 5.5-40~85

24TSSOP24

PCA9555PW

Low-voltage 16-bit I²C-bus I/O port with interrupt and weak pull-up

2.3 - 5.5-40~8524

TSSOP24

PCA9539PW

Low-voltage 16-bit I²C and SMBus low-power I/O expander with interrupt output, reset pin and configuration registers

2.3 - 5.5-40~85

24TSSOP24

PCA9535PW

Low-voltage 16-bit I²C and SMBus low-power I/O expander with interrupt output and configuration registers

2.3 - 5.5-40~85

24TSSOP24

NCA9595PW-Q100

Low voltage 16-bit I²C and SMBus I/O expander with interrupt output,configuration registers and programmable pull-up resistors

1.65 - 5.5-40~125

24

TSSOP24

NCA9555PW-Q100

Low-voltage 16-bit I²C and SMBus I/O expander with interrupt output
and configuration registers

1.65 - 5.5-40~125

24

TSSOP24

NCA9555BY-Q100

Low-voltage 16-bit I²C and SMBus I/O expander with interrupt output
and configuration registers

1.65 - 5.5-40~12524

HWQFN24

NCA9539PW-Q100

Low-voltage 16-bit I²C and SMBus low-power I/O expander with interrupt output, reset pin and configuration registers

1.65 - 5.5-40~12524

TSSOP24

NCA9539BY-Q100*

Low-voltage 16-bit I²C and SMBus low-power I/O expander with interrupt output, reset pin and configuration registers

1.65 - 5.5-40~125

24

HWQFN24

NCA9535PW-Q100

Low-voltage 16-bit I²C and SMBus low-power I/O expander with interrupt output and configuration registers

1.65 - 5.5-40~125

24

TSSOP24

NCA9535BY-Q100*Low-voltage 16-bit I²C and SMBus low-power I/O expander with interrupt output and configuration registers

1.65 - 5.5-40~125

24

HWQFN24* in development

SOTPackage suffix

No of pins

Package dimensions

Pitch (mm)Package

SOT355-1PW

24

7.8 x 4.4 x 1.1

0.65

TSSOP24

SOT8041BY

244 x 4 x 0.75

0.5

HWQFN24© 2023 Nexperia B.V.
All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent ofthe copyright owner. The information presented in this document does not form part of any quotationor contract, is believed to be accurate and reliable and may be changed without notice. No liability will
be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor
imply any license under patent- or other industrial or intellectual property rights.

nexperia.com

Date of release:April 2023