Low Noise, Low Drift, Low Power,
3-Axis MEMS Accelerometers
ADXL354/ADXL355

Data SheetFEATURESFUNCTIONAL BLOCK DIAGRAMS
V1P8ANALDO

VSUPPLY

V1P8DIG

RANGE

POWER
MANAGEMENT

LDO

XOUT
ANALOGFILTER

ST1
3-AXISSENSOROUTTEMPSENSORTEMPCONTROLLOGIC

ADXL354
VSSIO

ST2
STBY
VDDIO
14205-002

YOUT

VSS

Figure 1. ADXL354 Functional Block Diagram
V1P8ANALDO

VSUPPLY

V1P8DIG

LDO

VDDIO

ADXL355

POWER
MANAGEMENT

ADC

3-AXISSENSORANALOGFILTERADC

DIGITALFILTERCONTROL
LOGIC

ADC
TEMP
SENSOR

ADC

FIFO

VSSIO

VSS

SERIAL
I/O

INT1
INT2
DRDY
CS/SCL
SCLK/VSSIOMOSI/SDAMISO/ASEL

14205-001

Hermetic package offers excellent long-term stability
0 g offset vs. temperature (all axes): 0.15 mg/°C maximum
Ultralow noise density (all axes): 20 μg/√Hz (ADXL354)
Low power, VSUPPLY (LDO enabled)
ADXL354 in measurement mode: 150 μA
ADXL355 in measurement mode: 200 μA
ADXL354/ADXL355 in standby mode: 21 μA
ADXL354 has user adjustable analog output bandwidth
ADXL355 digital output features
Digital serial peripheral interface (SPI)/I2C interfaces
20-bit analog-to-digital converter (ADC)
Data interpolation routine for synchronous sampling
Programmable high- and low-pass digital filters
Electromechanical self test
Integrated temperature sensor
Voltage range options
VSUPPLY with internal regulators: 2.25 V to 3.6 V
V1P8ANA, V1P8DIG with internal low dropout regulator (LDO)
bypassed: 1.8 V typical ± 10%
Operating temperature range: −40°C to +125°C
14-terminal, 6 mm × 6 mm × 2.1 mm, LCC package,
0.26 grams

Figure 2. ADXL355 Functional Block Diagram

APPLICATIONSInertial measurement units (IMUs)/altitude and headingreference systems (AHRSs)
Platform stabilization systems
Structural health monitoring
Seismic imaging
Tilt sensing
Robotics
Condition monitoring

GENERAL DESCRIPTION
The analog output ADXL354 and the digital output ADXL355
are low noise density, low 0 g offset drift, low power, 3-axis
accelerometers with selectable measurement ranges. The
ADXL354B supports the ±2 g and ±4 g ranges, the ADXL354C
supports the ±2 g and ±8 g ranges, and the ADXL355 supports
the ±2.048 g, ±4.096 g, and ±8.192 g ranges. The ADXL354/
ADXL355 offer industry leading noise, minimal offset drift overtemperature, and long term stability enabling precisionapplications with minimal calibration.
1

Highly integrated in a compact form factor, the low power
ADXL355 is ideal in an Internet of Things (IoT) sensor nodeand other wireless product designs.
The ADXL355 multifunction pin names may be referenced bytheir relevant function only for either the SPI or I2C interfaces.

Protected by U.S. Patents 8,472,270; 9,041,462; 8,665,627; 8,917,099; 6,892,576; 9,297,825; and 7,956,621.

Rev. 0Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or otherrights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700©2016 Analog Devices, Inc. All rights reserved.
www.analog.com
Technical Support

ADXL354/ADXL355

Data SheetTABLE OF CONTENTS
Features .............................................................................................. 1

NVM_BUSY ............................................................................... 28

Applications ....................................................................................... 1

External Synchronization and Interpolation .......................... 29

Functional Block Diagrams ............................................................. 1

ADXL355 Register Map ................................................................. 31

General Description ......................................................................... 1

Register Definitions........................................................................ 32

Revision History ............................................................................... 2

Analog Devices ID Register ...................................................... 32

Specifications..................................................................................... 3

Analog Devices MEMS ID Register......................................... 32

Analog Output for the ADXL354 ............................................... 3

Device ID Register ..................................................................... 32

Digital Output for the ADXL355 ............................................... 4

Product Revision ID Register ................................................... 32

SPI Digital Interface Characteristics for the ADXL355 .......... 5

Status Register ............................................................................. 32

2

I C Digital Interface Characteristics for the ADXL355 ........... 6

FIFO Entries Register ................................................................ 33

Absolute Maximum Ratings............................................................ 8

Temperature Data Registers ...................................................... 33

Thermal Resistance ...................................................................... 8

X-Axis Data Registers ................................................................ 33

ESD Caution .................................................................................. 8

Y-Axis Data Registers ................................................................ 34

Pin Configurations and Function Descriptions ........................... 9

Z-Axis Data Registers ................................................................ 34

Typical Performance Characteristics ........................................... 11

FIFO Access Register ................................................................. 35

Root Allan Variance (RAV) ADXL355 Characteristics ......... 19

X-Axis Offset Trim Registers .................................................... 35

Theory of Operation ...................................................................... 20

Y-Axis Offset Trim Registers .................................................... 35

Analog Output ............................................................................ 20

Z-Axis Offset Trim Registers .................................................... 36

Digital Output ............................................................................. 21

Activity Enable Register ............................................................ 36

Axes of Acceleration Sensitivity ............................................... 21

Activity Threshold Registers ..................................................... 36

Power Sequencing ...................................................................... 22

Activity Count Register ............................................................. 36

Power Supply Description ......................................................... 22

Filter Settings Register ............................................................... 37

Overrange Protection................................................................. 22

FIFO Samples Register .............................................................. 37

Self Test ........................................................................................ 22

Interrupt Pin (INTx) Function Map Register......................... 37

Filter ............................................................................................. 23

Data Synchronization ................................................................ 38

Serial Communications ................................................................. 25

I2C Speed, Interrupt Polarity, and Range Register ................. 38

SPI Protocol ................................................................................. 25

Power Control Register ............................................................. 38

I2C Protocol ................................................................................. 26

Self Test Register ......................................................................... 39

Reading Acceleration or Temperature Data from the Interface....................................................................................................... 26

Reset Register .............................................................................. 39
Recommended Soldering Profile ................................................. 40

FIFO ................................................................................................. 27

PCB Footprint Pattern ............................................................... 41

Interrupts ......................................................................................... 28

Packaging and Ordering Information ......................................... 42

DATA_RDY................................................................................. 28

Outline Dimensions ................................................................... 42

DRDY Pin .................................................................................... 28

Branding Information................................................................ 42

FIFO_FULL ................................................................................. 28

Ordering Guide .......................................................................... 42

FIFO_OVR .................................................................................. 28
Activity ......................................................................................... 28

REVISION HISTORY
9/2016—Revision 0: Initial Version
Rev. 0 | Page 2 of 42

Data SheetADXL354/ADXL355

SPECIFICATIONSANALOG OUTPUT FOR THE ADXL354
TA = 25°C, VSUPPLY = 3.3 V, x-axis acceleration and y-axis acceleration = 0 g, and z-axis acceleration = 1 g, unless otherwise noted.
Table 1.
Parameter
SENSOR INPUT
Output Full-Scale Range (FSR)
Resonant Frequency 1
Nonlinearity
Cross Axis Sensitivity
SENSITIVITY
Sensitivity at XOUT, YOUT, ZOUT

Sensitivity Change due to Temperature
0 g OFFSET
0 g Output for XOUT, YOUT, ZOUT
0 g Offset vs. Temperature (X-Axis, Y-Axis, and Z-Axis) 2
Repeatability 3
Vibration Rectification Error (VRE) 4
NOISE DENSITY
X-Axis, Y-Axis, and Z-Axis
Velocity Random WalkBANDWIDTH
Internal Low-Pass Filter Frequency
SELF TEST
Output Change
X-AxisY-AxisZ-AxisPOWER SUPPLY
Voltage Range
VSUPPLY 5
VDDIO
V1P8ANA, V1P8DIG with Internal Low Dropout
Regulator (LDO) Bypassed
Current
Measurement ModeVSUPPLY (LDO Enabled)
V1P8ANA (LDO Disabled)
V1P8DIG (LDO Disabled)Standby ModeVSUPPLY (LDO Enabled)
V1P8ANA (LDO Disabled)
V1P8DIG (LDO Disabled)
Turn On Time 6

Test Conditions/Comments
Each axis
ADXL354B, supports two ranges
ADXL354C, supports two ranges

Min

Rev. 0 | Page 3 of 42

g
g
kHz
%
%

400
200
100
±0.01

432
216
108

mV/g
mV/g
mV/g
%/°C

−75
−0.15

±25
±0.1
±3.5
±9
<0.4

+75
+0.15

mg
mg/°C
mg
mg
g

Fixed frequency, 50% response
attenuation

2 g range
Power-off to standby

Unit

368
184
92

X-axis and y-axis
Z-axisVSUPPLY = 0 V

Max

±2/±4
±2/±8
2.4
0.1
1

±2 g
Ratiometric to V1P8ANA
±2 g
±4 g
±8 g
−40°C to +125°C
Each axis, ±2 g
Referred to V1P8ANA/2−40°C to +125°C
X-axis and y-axis
Z-axis±2 g range, in a 1 g orientation,offset due to 2.5 g rms vibration
±2 g

Typ

2.25
V1P8DIG
1.62

20
9
13

µg/√Hzµm/sec/√Hrµm/sec/√Hr

1500

Hz

0.3
0.3
1.5

g
g
g

2.5
2.5
1.8

3.6
3.6
1.98

V
V
V

150
138
12

µA
µA
µA

21
7
10
<10
<10

µA
µA
µA
ms
ms

ADXL354/ADXL355
Parameter
OUTPUT AMPLIFIER
Swing
Output Series Resistance
TEMPERATURE SENSOR
Output at 25°C
Scale Factor
TEMPERATURE
Operating Temperature Range

Data Sheet
Test Conditions/Comments

Min

No load

0.03

Typ

Max

Unit

V1P8ANA − 0.03
32

V
kΩ

892.2
3.0

mV
mV/°C

−40

+125

°C

The resonant frequency is a sensor characteristic. An integrated analog 1.5 kHz (−6 dB) sinc low-pass filter that cannot be bypassed limits the actual output response.
The temperature change is −40°C to +25°C or +25°C to +125°C.
3
Repeatability is predicted for a 10 year life and includes shifts due to the high temperature operating life test (HTOL) (TA = 150°C, VSUPPLY = 3.6 V, and 1000 hours),
temperature cycling (−55°C to +125°C and 1000 cycles), velocity random walk, broadband noise, and temperature hysteresis.
4
The VRE measurement is the shift in dc offset while the device is subject to 2.5 g rms of random vibration from 50 Hz to 2 kHz. The device under test (DUT) is
configured for the ±2 g range and an output data rate of 4 kHz. The VRE scales with the range setting.
5
When V1P8ANA and V1P8DIG are generated internally, VSUPPLY is valid. To disable the LDO and drive V1P8ANA and V1P8DIG externally, connect VSUPPLY to VSS.
6
Standby to measurement mode; valid when the output is within 1 mg of the final value.
1
2

DIGITAL OUTPUT FOR THE ADXL355
TA = 25°C, VSUPPLY = 3.3 V, x-axis acceleration and y-axis acceleration = 0 g, and z-axis acceleration = 1 g, and output data rate (ODR) =500 Hz, unless otherwise noted. Note that multifunction pin names may be referenced by their relevant function only.
Table 2.
Parameter
SENSOR INPUT
Output Full Scale Range (FSR)

Test Conditions/Comments
Each axis
User selectable

Nonlinearity
Cross Axis Sensitivity
SENSITIVITY
X-Axis, Y-Axis, and Z-Axis Sensitivity±2 g

X-Axis, Y-Axis, and Z-Axis Scale Factor

Sensitivity Change due to Temperature
0 g OFFSET
X-Axis, Y-Axis, and Z-Axis 0 g Output
0 g Offset vs. Temperature (X-Axis, Y-Axis, and Z-Axis) 1
Repeatability 2
Vibration Rectification 3
NOISE DENSITY
X-Axis, Y-Axis, and Z-Axis
Velocity Random WalkOUTPUT DATA RATE AND BANDWIDTH
Low-Pass Filter Passband Frequency
High-Pass Filter Passband Frequency When Enabled(Disabled by Default)

Each axis
±2 g
±4 g
±8 g
±2 g
±4 g
±8 g
−40°C to +125°C
Each axis, ±2 g
−40°C to +125°C
X-axis and y-axis
Z-axis±2 g range, in a 1 g orientation,offset due to 2.5 g rms vibration
±2 g

Min

Rev. 0 | Page 4 of 42

Max

Unit
g
g
g
% FS
%

±2.048±4.096±8.1920.1
1235,520
117,760
58,880

256,000
128,000
64,000
3.9
7.8
15.6
±0.01

276,480138,240
69,120

LSB/g
LSB/g
LSB/g
µg/LSBµg/LSBµg/LSB
%/°C

−75
−0.15

±25
±0.02
±3.5
±9
<0.4

+75
+0.15

mg
mg/°C
mg
mg
g

25
9
13

X-axis and y-axis
Z-axisUser programmable, Register 0x28
User programmable, Register 0x28
for 4 kHz ODR

Typ1
0.0095µg/√Hzµm/sec/√Hrµm/sec/√Hr
1000
10

Hz
Hz

Data SheetADXL354/ADXL355

Parameter
SELF TEST
Output Change
X-AxisY-AxisZ-AxisPOWER SUPPLY
Voltage Range
VSUPPLY Operating 4
VDDIO
V1P8ANA and V1P8DIG with Internal LDO Bypassed
Current
Measurement ModeVSUPPLY (LDO Enabled)
V1P8ANA (LDO Disabled)
V1P8DIG (LDO Disabled)Standby ModeVSUPPLY (LDO Enabled)
V1P8ANA (LDO Disabled)
V1P8DIG (LDO Disabled)
Turn On Time 5

Test Conditions/Comments

Min

Typ

Max

g
g
g

0.3
0.3
1.5

VSUPPLY = 0 V

2.25
V1P8DIG
1.62

2 g range
Power-off to standby

TEMPERATURE SENSOR
Output at 25°C
Scale Factor
TEMPERATURE
Operating Temperature Range

2.5
2.5
1.8

Unit

3.6
3.6
1.98

V
V
V

200
160
35.5

µA
µA
µA

21
7
10
<10
<10

µA
µA
µA
ms
ms

1852
−9.05

LSB
LSB/°C

−40

+125

°C

The temperature change is −40°C to +25°C or +25°C to +125°C.
Repeatability is predicted for a 10 year life and includes shifts due to the HTOL (TA = 150°C, VSUPPLY = 3.6 V, and 1000 hours), temperature cycling (−55°C to +125°C and1000 cycles), velocity random walk, broadband noise, and temperature hysteresis.
3
The VRE measurement is the shift in dc offset while the device is subject to 2.5 g rms random vibration from 50 Hz to 2 kHz. The DUT is configured for the ±2 g range
and an output data rate of 4 kHz. The VRE scales with the range setting.
4
When V1P8ANA and V1P8DIG are generated internally, VSUPPLY is valid. To disable the LDO and drive V1P8ANA and V1P8DIG externally, connect VSUPPLY to VSS.
5
Standby to measurement mode; valid when the output is within 1 mg of final value.
1
2

SPI DIGITAL INTERFACE CHARACTERISTICS FOR THE ADXL355
Note that multifunction pin names may be referenced by their relevant function only.
Table 3.
Parameter
DC INPUT LEVELS
Input Voltage
Low Level
High Level
Input Current
Low Level
High Level
DC OUTPUT LEVELS
Output Voltage
Low Level
High Level
Output Current
Low Level
High Level

SymbolTest Conditions/Comments

VIL
VIH

Min

Typ

Max

Unit

0.3 × VDDIO

V
V

0.7 × VDDIO

IIL
IIH

VIN = 0 V
VIN = VDDIO

VOL
VOH

IOL = IOL, MIN
IOH = IOH, MAX

IOL
IOH

VOL = VOL, MAX
VOH = VOH, MIN

−0.1
0.1

0.2 × VDDIO
0.8 × VDDIO−10
4Rev. 0 | Page 5 of 42

µA
µA

V
V
mA
mA

ADXL354/ADXL355

Data SheetParameter
AC INPUT LEVELSSCLK Frequency
SCLK High TimeSCLK Low Time
CS Setup TimeCS Hold Time
CS Disable Time
Rising SCLK Setup TimeMOSI Setup TimeMOSI Hold TimeAC OUTPUT LEVELS
Propagation Delay
Enable MISO Time
Disable MISO Time

SymbolTest Conditions/Comments

Min

Typ

0.1
40
40
20
20
40
20
20
20

tHIGH
tLOW
tCSS
tCSH
tCSD
tSCLKS
tSU
tHD
tP
tEN
tDIS

CLOAD = 30 pF

Max

Unit

10

MHz
ns
ns
ns
ns
ns
ns
ns
ns

30

ns
ns
ns

30
20

tCSD
CS
tCSS

tHIGH

tCSH

tLOW

tSCLKS

SCLK

tSU

tHD

MOSI

tDIS

tP

14205-003

tEN
MISO

Figure 3. SPI Interface Timing Diagram

I2C DIGITAL INTERFACE CHARACTERISTICS FOR THE ADXL355
Note that multifunction pin names may be referenced by their relevant function only.
Table 4.
Parameter
DC INPUT LEVELS
Input Voltage
Low Level
High Level
Hysteresis of Schmitt
Trigger Inputs
Input Current
DC OUTPUT LEVELS
Output Voltage
Low Level
Output Current
Low Level

SymbolTest Conditions/
Comments

VIL
VIH
VHYS
IIL

VOL1
VOL2
IOL

Min

I2C_HS = 0 (Fast Mode)
Typ Max

I2C_HS = 1 (High Speed Mode)
Min
Typ
Max

0.3 × VDDIO
0.7 × VDDIO
0.05 × VDDIO
0.1 × VDDIO < VIN <0.9 × VDDIO−10IOL = 3 mA
VDD > 2 V
VDD ≤ 2 V
VOL = 0.4 V
VOL = 0.6 V

20
6Rev. 0 | Page 6 of 42

0.3 × VDDIO
0.7 × VDDIO
0.1 × VDDIO

Unit

V
V
μA

+10

μA

0.4
0.2 × VDDIO

V
V
mA
mA

Data SheetADXL354/ADXL355

Parameter
AC INPUT LEVELSSCLK Frequency
SCL High Time
SCL Low Time
Start Setup Time
Start Hold TimeSDA Setup TimeSDA Hold Time
Stop Setup TimeBus Free TimeSCL Input Rise TimeSCL Input Fall TimeSDA Input Rise TimeSDA Input Fall Time
Width of Spikes to
SuppressAC OUTPUT LEVELS
Propagation Delay
Data
Acknowledge
Output Fall Time

SymboltHIGH
tLOWtSUSTAtHDSTAtSUDATtHDDATtSUSTO
tBUF
tRCL
tFCL
tRDA
tFDA
tSP

Test Conditions/
Comments

Min

I2C_HS = 0 (Fast Mode)
Typ Max

0
260
500
260
260
50
0
260
500

I2C_HS = 1 (High Speed Mode)
Min
Typ
Max

1

0
60
160
160
160
10
0
160

3.4

120
120
120
120
50

Not shown in Figure 4

Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

80
80
160
160
10

CLOAD = 500 pF
tVDDATtVDACKtF

97
Not shown in Figure 4

450
450
120

20 × (VDD/5.5)

27

tFDA

135

tRDA

ns
ns
ns

tBUF

SDA

tVDDATtSUDATtHDDATtLOWtVDDAT
SCL

Figure 4. I2C Interface Timing Diagram

Rev. 0 | Page 7 of 42tVDACK
tFCL

tHIGH

tRCL

tSUSTOtSUSTA
14205-004

tSUSTA tHDSTAADXL354/ADXL355

Data Sheet

ABSOLUTE MAXIMUM RATINGSTHERMAL RESISTANCE

Table 5.
Parameter
Acceleration (Any Axis, 0.1 ms)
Unpowered
VSUPPLY, VDDIO
V1P8ANA, V1P8DIG Configured as Inputs
ADXL354
Digital Inputs (RANGE, ST1, ST2, STBY)
Analog Outputs (XOUT, YOUT, ZOUT, TEMP)ADXL355
Digital Pins (CS, SCLK, MOSI, MISO,
INT1, INT2, DRDY)
Operating Temperature Range
Storage Temperature Range

Thermal performance is directly linked to printed circuit board(PCB) design and operating environment. Careful attention to
PCB thermal design is required.

Rating5,000 g
5.4 V
1.98 V

Table 6. Thermal Resistance−0.3 V to VDDIO + 0.3 V−0.3 V to V1P8ANA + 0.3 V−0.3 V to VDDIO + 0.3 V

Package TypeE-14-11
1

θJA
42

Unit
°C/W

Thermal impedance simulated values are based on a JEDEC 2S2P thermal
test board with four thermal vias. See JEDEC JESD51.

ESD CAUTION−40°C to +125°C−55°C to +150°C

Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at theseor any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.

Rev. 0 | Page 8 of 42

Data SheetADXL354/ADXL355

12 X OUTY

11 VSUPPLYRANGE 1
ST1 2

ADXL354

10 V1P8ANA

ST2 3TOP VIEW(Not to Scale)

9

VSS

8

V1P8DIGZ

STBY 7VSSIO 6

VDDIO 5

TEMP 4X

14205-007

13 Y OUT

14 ZOUTPIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

Figure 5. ADXL354 Pin Configuration

Table 7. ADXL354 Pin Function Descriptions
Pin No.
1

Mnemonic
RANGE

2
3
4
5
6
7

ST1
ST2
TEMP
VDDIO
VSSIO
STBY

8

V1P8DIG

910

VSS
V1P8ANA11

VSUPPLY

12
13
14

XOUT
YOUT
ZOUT

Description
Range Selection Pin. Set this pin to ground to select the ±2 g range, or set this pin to VDDIO to select the ±4 g
or ±8 g range. This pin is model dependent (see the Ordering Guide section).
Self Test Pin 1. This pin enables self test mode.
Self Test Pin 2. This pin activates the electromechanical self test actuation.
Temperature Sensor Output.
Digital Interface Supply Voltage.
Digital Ground.
Standby or Measurement Mode Selection Pin. Set this pin to ground to enter standby mode, or set this pin
to VDDIO to enter measurement mode.
Digital Supply. This pin requires a decoupling capacitor. If VSUPPLY connects to VSS, supply the voltage to thispin externally.
Analog Ground.
Analog Supply. This pin requires a decoupling capacitor. If VSUPPLY connects to VSS, supply the voltage to thispin externally.
Supply Voltage. When VSUPPLY equals 2.25 V to 3.6 V, VSUPPLY enables the internal LDOs to generate V1P8DIG and
V1P8ANA. For VSUPPLY = VSS, V1P8DIG and V1P8ANA are externally supplied.
X-Axis Output.
Y-Axis Output.
Z-Axis Output.

Rev. 0 | Page 9 of 42

12 INT1Y

11 VSUPPLY

CS/SCL 1
SCLK/VSSIO 2

ADXL355

10 V1P8ANA

MOSI/SDA 3

TOP VIEW(Not to Scale)

9

VSS

8

V1P8DIGX
Z

RESERVED 7VSSIO 6

VDDIO 5

MISO/ASEL 414205-006

13 INT2

Data Sheet
14 DRDYADXL354/ADXL355

Figure 6. ADXL355 Pin Configuration

Table 8. ADXL355 Pin Function Descriptions
Pin No.
1

Mnemonic
CS/SCL2

SCLK/VSSIO

3

MOSI/SDA

4

MISO/ASEL

5
6
7
8

VDDIO
VSSIO
RESERVED
V1P8DIG

910

VSS
V1P8ANA11

VSUPPLY

12
13
14

INT1
INT2
DRDY

Description
Chip Select for SPI (CS).
Serial Communications Clock for I2C (SCL).
Serial Communications Clock for SPI (SCLK).
Connect to VSSIO for I2C (VSSIO).
Master Output, Slave Input for SPI (MOSI).
Serial Data for I2C (SDA).
Master Input, Slave Output for SPI (MISO).
Alternate I2C Address Select for I2C (ASEL).
Digital Interface Supply Voltage.
Digital Ground.
Reserved. This pin can be connected to ground or left open.
Digital Supply. This pin requires a decoupling capacitor. If VSUPPLY connects to VSS, supply the voltage to thispin externally.
Analog Ground.
Analog Supply. This pin requires a decoupling capacitor. If VSUPPLY connects to VSS, supply the voltage to thispin externally.
Supply Voltage. When VSUPPLY equals 2.25 V to 3.6 V, VSUPPLY enables the internal LDOs to generate V1P8DIG and
V1P8ANA. For VSUPPLY = VSS, V1P8DIG and V1P8ANA are externally supplied.
Interrupt Pin 1.
Interrupt Pin 2.
Data Ready Pin.

Rev. 0 | Page 10 of 42

Data SheetADXL354/ADXL355

TYPICAL PERFORMANCE CHARACTERISTICS
All figures include data for multiple devices and multiple lots, and they were taken in the ±2 g range, unless otherwise noted.
1

10

XOUT (g)

1

0.1

100

1000

FREQUENCY (Hz)

0.01
10

14205-207

0.01
10Figure 7. ADXL354 Frequency Response for X-Axis

100

1000

FREQUENCY (Hz)

14205-210

0.1

Figure 10. ADXL355 Normalized Frequency Response for X-Axis at 4 kHz ODR

10

1

Y-AXIS (g)YOUT (g)

1

0.1

1000

FREQUENCY (Hz)Figure 8. ADXL354 Frequency Response for Y-Axis

0.01
10

Figure 11. ADXL355 Normalized Frequency Response for Y-Axis at 4 kHz ODRZ-AXIS (g)

1

1

100

1000

FREQUENCY (Hz)

14205-209

ZOUT (g)1000

FREQUENCY (Hz)

10

0.1
10

100

14205-211

100

0.1

0.01
10

100
FREQUENCY (Hz)Figure 9. ADXL354 Frequency Response for Z-Axis

1000

14205-2120.01
1014205-208

0.1

Figure 12. ADXL355 Normalized Frequency Response for Z-Axis at 4 kHz ODRRev. 0 | Page 11 of 42

ADXL354/ADXL355
15.00

Data Sheet
1.00

MAXIMUM CHANGE = 1.69mg
AVERAGE CHANGE = 1.18mg

RELATIVE SENSITIVITY (%)

RELATIVE OFFSET (mg)

10.00

5.00

0

MAXIMUM CHANGE = 0.60%
AVERAGE CHANGE = 0.34%

0.50

0

–5.00

55

105

TEMPERATURE (°C)

–0.65
–45

14205-213

5

105

Figure 16. ADXL354 X-Axis Sensitivity Relative to 25°C vs. Temperature
1.00

MAXIMUM CHANGE = 3.12mg
AVERAGE CHANGE = 1.85mg
RELATIVE SENSITIVITY (%)

10.00
RELATIVE OFFSET (mg)55
TEMPERATURE (°C)

Figure 13. ADXL354 X-Axis Zero g Offset Relative to 25°C vs. Temperature
15.00

5

14205-216

–0.50
–9.75
–45

5.00

0

MAXIMUM CHANGE = 0.54%
AVERAGE CHANGE = 0.28%

0.50

0

–5.00

55

105

TEMPERATURE (°C)

–0.65
–45

14205-214

5

105

Figure 17. ADXL354 Y-Axis Sensitivity Relative to 25°C vs. Temperature
1.00

MAXIMUM CHANGE = 3.12mg
AVERAGE CHANGE = 1.85mg

RELATIVE SENSITIVITY (%)

10.00
RELATIVE OFFSET (mg)55
TEMPERATURE (°C)

Figure 14. ADXL354 Y-Axis Zero g Offset Relative to 25°C vs. Temperature
15.00

5

14205-217

–0.50

–9.75
–45

MAXIMUM CHANGE = 0.99%
AVERAGE CHANGE = 0.51%

0.50

5.00

0

0

–5.00

55
TEMPERATURE (°C)

105

–0.65
–40

14205-215

5

10

60
TEMPERATURE (°C)

Figure 15. ADXL354 Z-Axis Zero g Offset Relative to 25°C vs. Temperature

11014205-218

–0.50

–9.75
–45

Figure 18. ADXL354 Z-Axis Sensitivity Relative to 25°C vs. Temperature

Rev. 0 | Page 12 of 42

ADXL354 2g OFFSET Z-AXIS (g)

30

20

10

0

0

ADXL354 2g SENSITIVITY X-AXIS (V/g)

Figure 19. ADXL354 Zero g Offset Histogram at 25°C, X-Axis

80

70
70

60
60

50

40

30

20

10
10

0
0

ADXL354 2g SENSITIVITY Y-AXIS (V/g)

Figure 20. ADXL354 Zero g Offset Histogram at 25°C, Y-Axis

45

40

25

20

15

5

0

0

ADXL354 2g SENSITIVITY Z-AXIS (V/g)

Figure 21. ADXL354 Zero g Offset Histogram at 25°C, Z-Axis

Figure 24. ADXL354 Sensitivity Histogram at 25°C, Z-Axis

Rev. 0 | Page 13 of 4214205-222

40

14205-223

70

0.368
0.370
0.372
0.374
0.376
0.378
0.380
0.382
0.384
0.386
0.388
0.390
0.392
0.394
0.396
0.398
0.400
0.402
0.404
0.406
0.408
0.410
0.412
0.414
0.416
0.418
0.420
0.422
0.424
0.426
0.428
0.430
0.432

50

HITS PER BIN (Count)

60

0.368
0.370
0.372
0.374
0.376
0.378
0.380
0.382
0.384
0.386
0.388
0.390
0.392
0.394
0.396
0.398
0.400
0.402
0.404
0.406
0.408
0.410
0.412
0.414
0.416
0.418
0.420
0.422
0.424
0.426
0.428
0.430
0.432

80

HITS PER BIN (Count)

14205-219

8014205-224

ADXL354 2g OFFSET Y-AXIS (g)14205-220

10

0.075
0.070
0.065
0.060
0.055
0.050
0.045
–0.040–0.035–0.030–0.025–0.020–0.015–0.010–0.005
0
0.005
0.010
0.015
0.020
0.025
0.030
0.035
0.040
0.045
0.050
0.055
0.060
0.065
0.070
0.075

HITS PER BIN (Count)
70

0.368
0.370
0.372
0.374
0.376
0.378
0.375
0.377
0.379
0.381
0.383
0.385
0.387
0.389
0.391
0.393
0.395
0.397
0.399
0.401
0.403
0.405
0.407
0.409
0.416
0.418
0.420
0.422
0.424
0.426
0.428
0.430
0.432

30

HITS PER BIN (Count)

20

0.075
0.070
0.065
0.060
0.055
0.050
0.045
–0.040–0.035–0.030–0.025–0.020–0.015–0.010–0.005
0
0.005
0.010
0.015
0.020
0.025
0.030
0.035
0.040
0.045
0.050
0.055
0.060
0.065
0.070
0.075

HITS PER BIN (Count)

ADXL354 2g OFFSET X-AXIS (g)14205-221

HITS PER BIN (Count)

Data SheetADXL354/ADXL355

60

50

40

30

20

Figure 22. ADXL354 Sensitivity Histogram at 25°C, X-Axis

50

40

30

Figure 23. ADXL354 Sensitivity Histogram at 25°C, Y-Axis

70

35

60

50

40

30

10

20

10

Data Sheet
0.68

0.6

0.58

0.5

0.48

0.4
0.3

0.18

0.1

0.08

0

1

2

3

4

INPUT VIBRATION (g rms)

–0.02

4

6

8

10

0

–0.1

–0.1

–0.3
–0.4

–0.2
–0.3
–0.4

–0.5

–0.5

–0.6

–0.6

2
INPUT VIBRATION (g rms)

3

4

–0.7

–0.1

–0.1

–0.2

–0.2

OFFSET SHIFT (g)

0

–0.3
–0.4

–0.6

INPUT VIBRATION (g rms)

14205-227

–0.6

4

8

10

–0.4
–0.5

3

6

–0.3

–0.5

2

4

Figure 29. ADXL354 Vibration Rectification Error (VRE),
Y-Axis Offset from +1 g, ±8 g Range, Y-Axis Orientation = +1 g

0

1

2

INPUT VIBRATION (g rms)

Figure 26. ADXL354 Vibration Rectification Error (VRE),
Y-Axis Offset from +1 g, ±2 g Range, Y-Axis Orientation = +1 g

0

0

–0.7

0

2

4

6

8

10

INPUT VIBRATION (g rms)

Figure 30. ADXL354 Vibration Rectification Error (VRE),
Z-Axis Offset from +1 g, ±8 g Range, Z-Axis Orientation = +1 g

Figure 27. ADXL354 Vibration Rectification Error (VRE),
Z-Axis Offset from +1 g, ±2 g Range, Z-Axis Orientation = +1 g

Rev. 0 | Page 14 of 4214205-230114205-226014205-229

OFFSET SHIFT (g)

–0.2

–0.7

2

Figure 28. ADXL354 Vibration Rectification Error (VRE),
X-Axis Offset from +1 g, ±8 g Range, X-Axis Orientation = −1 g

0

–0.7

0

INPUT VIBRATION (g rms)

Figure 25. ADXL354 Vibration Rectification Error (VRE),
X-Axis Offset from +1 g, ±2 g Range, X-Axis Orientation = −1 g

OFFSET SHIFT (g)

0.28

0.2

0

OFFSET SHIFT (g)0.38

14205-228

OFFSET SHIFT (g)0.7

14205-225

OFFSET SHIFT (g)

ADXL354/ADXL355

Data Sheet
15.00

ADXL354/ADXL355
1.00

MAXIMUM DELTA = 6.5mg
AVERAGE DELTA = 1.7mg

RELATIVE SENSITIVITY (%)

RELATIVE OFFSET (mg)

10.00

5.00

0

MAXIMUM CHANGE = 0.78%
AVERAGE CHANGE = 0.72%

0.50

0

–5.00

55

105

TEMPERATURE (°C)

–0.65
–45

14205-231

5

105

Figure 34. ADXL355 X-Axis Sensitivity Relative to 25°C vs. Temperature
1.00

MAXIMUM DELTA = 3.2mg
AVERAGE DELTA = 1.4mg

RELATIVE SENSTIVITY (%)

10.00

RELATIVE OFFSET (mg)55

TEMPERATURE (°C)

Figure 31. ADXL355 X-Axis Zero g Offset Relative to 25°C vs. Temperature
15.00

5

5.00

0

14205-234

–0.50
–9.75
–45

MAXIMUM CHANGE = 0.78%
AVERAGE CHANGE = 0.72%

0.50

0

–5.00

55

105

TEMPERATURE (°C)

–0.65
–45

14205-232

5

105

TEMPERATURE (°C)

Figure 32. ADXL355 Y-Axis Zero g Offset Relative to 25°C vs. Temperature
15.00

55

5

14205-235

–0.50
–9.75
–45

Figure 35. ADXL355 Y-Axis Sensitivity Relative to 25°C vs. Temperature
1.00

MAXIMUM DELTA = 10.6mg
AVERAGE DELTA = 5.3mg

MAXIMUM CHANGE = 0.47%
AVERAGE CHANGE = 0.3%

RELATIVE SENSTIVITY (%)

RELATIVE OFFSET (mg)

10.00

5.00

0

0.50

0

–5.00

5

55
TEMPERATURE (°C)

105

–0.65
–45

14205-233

–9.75
–45

5

55
TEMPERATURE (°C)

Figure 33. ADXL355 Z-Axis Zero g Offset Relative to 25°C vs. Temperature

105

14205-236–0.50

Figure 36. ADXL355 Z-Axis Sensitivity Relative to 25°C vs. Temperature

Rev. 0 | Page 15 of 42

0

OFFSET (mg)100Figure 37. ADXL355 Zero g Offset Histogram at 25°C, X-Axis
SENSITIVITY (lsb/g)

80

70

50

40

30

10

0

Figure 38. ADXL355 Zero g Offset Histogram at 25°C, Y-Axis
SENSITIVITY (LSB/g)

45

40

25

20

15

10

0

Figure 39. ADXL355 Zero g Offset Histogram at 25°C, Z-Axis

Figure 42. ADXL355 Sensitivity Histogram at 25°C, Z-Axis

SENSITIVITY (LSB/g)

Rev. 0 | Page 16 of 4214205-240

2014205-24130

14205-242

40235520237158238797240435242074243712245350246989248627250266251904253542255181
256819258458260096261734263373265011
26665026828826992627156527320327484227648050

HITS PER BIN (Count)70

235520237158238797240435242074243712245350246989248627250266251904253542255181
256819258458260096261734263373265011
26665026828826992627156527320327484227648060

HITS PER BIN (Count)

14205-237

–75
–69
–63
–57
–51
–45
–39
–33
–27
–21
–15
–9
–3
3
9
15
21
27
33
39
45
51
57
63
69
75

HITS PER BIN (Count)
80235520237158238797240435242074243712245350246989248627250266251904253542255181
256819258458260096261734263373265011
26665026828826992627156527320327484227648030

HITS PER BIN (Count)

OFFSET (mg)14205-238

OFFSET (mg)14205-239

0

–75
–69
–63
–57
–51
–45
–39
–33
–27
–21
–15
–9
–3
3
9
15
21
27
33
39
45
51
57
63
69
75

HITS PER BIN (Count)
0

–75
–69
–63
–57
–51
–45
–39
–33
–27
–21
–15
–9
–3
3
9
15
21
27
33
39
45
51
57
63
69
75

HITS PER BIN (Count)

ADXL354/ADXL355
Data Sheet

60

60

50

40

30

20

10

Figure 40. ADXL355 Sensitivity Histogram at 25°C, X-Axis

60

50

40

30

20

20

10

Figure 41. ADXL355 Sensitivity Histogram at 25°C, Y-Axis

60

35

50

40

30

20

5

10

ADXL354/ADXL355
0.68

0.6

0.58

0.5

0.48

OFFSET SHIFT (g)

0.7

0.3

0.38
0.28

0.2

0.18

0.1

0.08

0

1

2

3

4

INPUT VIBRATION (g rms)

–0.02

8

10

–0.1

–0.2

OFFSET SHIFT (g)

–0.3
–0.4
–0.5

–0.2
–0.3
–0.4
–0.5

–0.6

–0.6
1

2

3

4

INPUT VIBRATION (g rms)

–0.714205-244

0

–0.1

–0.1

–0.2

–0.2

OFFSET SHIFT (g)

0

–0.3
–0.4

–0.6

INPUT VIBRATION (g rms)

14205-245

–0.6

4

8

10

–0.4
–0.5

3

6

–0.3

–0.5

2

4

Figure 47. ADXL355 Vibration Rectification Error (VRE),
Y-Axis Offset from +1 g, ±8 g Range, Y-Axis Orientation = +1 g

0

1

2

INPUT VIBRATION (g rms)

Figure 44. ADXL355 Vibration Rectification Error (VRE),
Y-Axis Offset from +1 g, ±2 g Range, Y-Axis Orientation = +1 g

0014205-247

OFFSET CHANGE (g)

6

0

–0.1

OFFSET CHANGE (g)4

Figure 46. ADXL355 Vibration Rectification Error (VRE),
X-Axis Offset from +1 g, ±8 g Range, X-Axis Orientation = −1 g

0

–0.7

2

INPUT VIBRATION (g rms)

Figure 43. ADXL355 Vibration Rectification Error (VRE),
X-Axis Offset from +1 g, ±2 g Range, X-Axis Orientation = −1 g

–0.7

0

Figure 45. ADXL355 Vibration Rectification Error (VRE),
Z-Axis Offset from +1 g, ±2 g Range, Z-Axis Orientation = +1 g

–0.7

0

2

4

6

8

10

INPUT VIBRATION (g rms)

Figure 48. ADXL355 Vibration Rectification Error (VRE),
Z-Axis Offset from +1 g, ±8 g Range, Z-Axis Orientation = +1 g

Rev. 0 | Page 17 of 4214205-248

014205-246

0.414205-243

OFFSET CHANGE (g)Data Sheet

1.15

0.002

1.05

0

0.95

–0.002–0.004

0.85

10

60

110

–0.006TEMPERATURE (°C)

Figure 49. ADXL354 Temperature Sensor Output and Linearity Offset vs.
Temperature

2100

4

1900
1700

–2

1300

–4

1100
900
700
–40

–6

TEMPERATURE SENSOR OUTPUT
LINEARITY
10

60

110

–8

TEMPERATURE (°C)

Figure 52. ADXL355 Temperature Sensor Output and Linearity Offset vs.
Temperature
100
90

70

80

HITS PER BIN (Count)

60
50
40
30
20

70
60
50
40
30
20

10
14205-251

10

0 125 129 133 137 141 145 149 153 157 161 165 169 173
TOTAL SUPPLY CURRENT (µA)

Figure 50. ADXL354 Total Supply Current, 3.3 V

30
25
20
15
10

ADXL355 CLOCK FREQUENCY (Hz)

14205-25253800 3840 3880 3920 3960 4000 4040 4080 4120 4160 4200

0180 184 188 192 196 200 204 208 212 216 220 224 228
TOTAL SUPPLY CURRENT (µA)

Figure 53. ADXL355 Total Supply Current, 3.3 V

35

HITS PER BIN (Count)

0

1500

80

0

2

Figure 51. ADXL355 Internal Clock Frequency Histogram

Rev. 0 | Page 18 of 4214205-253

0.75
–40

6

14205-250

0.004

2300

ADXL355 TEMPERATURE SENSOR
LINEAR OFFSET (LSB)

1.25

ADXL354 TEMPERATURE SENSOR
LINEAR OFFSET (V)

0.006

TEMPERATURE SENSOR OUTPUT
LINEARITYADXL355 TEMPERATURE SENSOR OUTPUT (LSB)

Data Sheet

14205-249

1.35

HITS PER BIN (Count)

ADXL354 TEMPERATURE SENSOR OUTPUT (V)ADXL354/ADXL355

Data SheetADXL354/ADXL355

ROOT ALLAN VARIANCE (RAV) ADXL355 CHARACTERISTICS
All figures include data for multiple devices and multiple lots, and they were taken in the ±2 g range, unless otherwise noted.
1000

100

100

RAV (µg)

RAV (µg)

1000

10

0.1

1

10

100

1000

INTEGRATION TIME (Seconds)

Figure 54. ADXL355 Root Allan Variance (RAV), X-Axis

RAV (µg)

100

1

10

100

INTEGRATION TIME (Seconds)

1000

14205-255

10

0.1

0.1

1

10

100

1000

INTEGRATION TIME (Seconds)

Figure 56. ADXL355 Root Allan Variance (RAV), Z-Axis

1000

1
0.01

1
0.01

Figure 55. ADXL355 Root Allan Variance (RAV), Y-Axis

Rev. 0 | Page 19 of 4214205-2561
0.0114205-254

10

ADXL354/ADXL355

Data Sheet

THEORY OF OPERATIONVDDIO (±4g, ±8g)
GND ( ± 2g)

0.1µF

11 VSUPPLYRANGE 1

10 V1P8ANA

ST1 2
ST2 3

2.25V TO 3.6V

0.1µF

ADXL354

STBY 7VSSIO 6

VDDIO 5

TEMP 49VSS

8

V1P8DIGADC VREF

VDDIO (MEASUREMENT)GND (STANDBY)

1µF

1µF

0.1µF

0.1µF

2.25V TO 3.6V

Figure 57. ADXL354 Application Circuit

Rev. 0 | Page 20 of 42

1µF

1µF

14205-022

The ADXL355 includes antialias filters before and after the highresolution Σ-Δ ADC. User-selectable output data rates and filter
corners are provided. The temperature sensor is digitized with a
12-bit successive approximation register (SAR) ADC.

The ADXL354 outputs two forms of filtering: internal antialiasing filtering with a cutoff frequency of approximately 1.5 kHz,and external filtering. The external filter uses a fixed, on-chip,
32 kΩ resistance in series with each output in conjunction withthe external capacitors to implement the low-pass filter antialiasing
and noise reduction prior to the external ADC. The antialias
filter cutoff frequency must be significantly higher than thedesired signal bandwidth. If the antialias filter corner is too low,ratiometricity can be degraded where the signal attenuation isdifferent than the reference attenuation.
12 XOUTThe analog accelerometer outputs of the ADXL354 are ratiometricto V1P8ANA; therefore, carefully digitize them correctly. The
temperature sensor output is not ratiometric. The XOUT, YOUT,and ZOUT analog outputs are filtered internally with an antialiasing filter. These analog outputs also have an internal 32 kΩ
series resistor that can be used with an external capacitor to set
the bandwidth of the output.

Figure 57 shows the ADXL354 application circuit. The analog
outputs (XOUT, YOUT, and ZOUT) are ratiometric to the 1.8 V
analog voltage from the V1P8ANA pin. V1P8ANA can be poweredwith an on-chip LDO that is powered from VSUPPLY. V1P8ANA canalso be supplied externally by forcing VSUPPLY to VSS, which
disables the LDO. Due to the ratiometric response, the analog
output requires referencing to the V1P8ANA supply when
digitizing to achieve the inherent noise and offset performanceof the ADXL354. The 0 g bias output is nominally equal to
V1P8ANA/2. The recommended option is to use the ADXL354
with a ratiometric ADC (for example, the Analog Devices, Inc.,
AD7682) with V1P8ANA providing the voltage reference. Thisconfiguration results in self cancellation of errors due to minor
supply variations.

13 YOUTThe micromachined, sensing elements are fully differential,
comprising the lateral x-axis and y-axis sensors and the vertical,
teeter totter z-axis sensors. The x-axis and y-axis sensors andthe z-axis sensors go through separate signal paths that minimize
offset drift and noise. The signal path is fully differential, except
for a differential to single-ended conversion at the analog
outputs of the ADXL354.

ANALOG OUTPUT

14 ZOUTThe ADXL354 is a complete 3-axis, ultralow noise and ultrastableoffset MEMS accelerometer with outputs ratiometric to the analog
1.8 V supply, V1P8ANA. The ADXL355 adds three high resolution
ADCs that use the analog 1.8 V supply as a reference to provide
digital outputs insensitive to the supply voltage. The ADXL354B
is pin selectable for ±2 g or ±4 g full scale, the ADXL354C is pin
selectable for ±2 g or ±8 g full scale, and the ADXL355 is
programmable for ±2.048 g, ±4.096 g, and ±8.192 g full scale.
The ADXL355 offers both SPI and I2C communications ports.

Data SheetADXL354/ADXL355

DIGITAL OUTPUT

AXES OF ACCELERATION SENSITIVITY

Figure 59 shows the ADXL355 application circuit with therecommended bypass capacitors. The communications interface
is either SPI or I2C (see the Serial Communications section for
additional information).

Figure 58 shows the axes of acceleration sensitivity. Note thatthe output voltage increases when accelerated along thesensitive axis.
Z

The ADXL355 includes an internal configurable digital bandpass filter. Both the high-pass and low-pass poles of the filter
are adjustable, as detailed in the Filter Settings Register section
and Table 43. At power-up, the default conditions for the filters
are as follows:

X

1µF

10 V1P8ANAADXL355

0.1µF

TOP VIEW(Not to Scale)

VSS

8

V1P8DIG

1µF

RESERVED 7VSSIO 6

VDDIO 5

MISO/ASEL 4

9

1µF

1µF

0.1µF

0.1µF

2.25V TO 3.6V

Figure 59. ADXL355 Application Circuit

Rev. 0 | Page 21 of 4214205-021

MOSI/SDA 3

0.1µF

11 VSUPPLY

CS/SCL 1
SCLK/VSSIO 2

2.25V TO 3.6V

12 INT1

13 INT2

14 DRDY

Figure 58. Axes of Acceleration Sensitivity

14205-005

High-pass filter (HPF) = dc (off)Low-pass filter (LPF) = 1000 Hz
Output data rate = 4000 Hz

SPI/I2C
INTERFACE





Y

ADXL354/ADXL355

Data Sheet

POWER SEQUENCING

VDDIOThere are two methods for applying power to the device.
Typically, internal LDO regulators generate the 1.8 V power forthe analog and digital supplies, V1P8ANA and V1P8DIG, respectively.
Optionally, connecting VSUPPLY to VSS and driving V1P8ANA andV1P8DIG with an external supply can supply V1P8ANA and V1P8DIG.

The VDDIO value determines the logic high levels. On the analog
output ADXL354, VDDIO sets the logic high level for the self test
pins, ST1 and ST2, as well as the STBY pin. On the digital output
ADXL355, VDDIO sets the logic high level for communications
interface ports, as well as the interrupt and DRDY outputs.

When using the internal LDO regulators, connect VSUPPLY to a
voltage source between 2.25 V to 3.6 V. In this case, VDDIO andVSUPPLY can be powered in parallel. VSUPPLY must not exceed the
VDDIO voltage by greater than 0.5 V. If necessary, VDDIO can be
powered before VSUPPLY.

The LDO regulators are operational when VSUPPLY is between
2.25 V and 3.6 V. V1P8ANA and V1P8DIG are the regulator outputs inthis mode. Alternatively, when tying VSUPPLY to VSS, V1P8ANA andV1P8DIG are supply voltage inputs with a 1.62 V to 1.98 V range.

When disabling the internal LDO regulators and using an external
1.8 V supply to power V1P8ANA and V1P8DIG, tie VSUPPLY to ground,and set V1P8ANA and V1P8DIG to the same final voltage level. In thecase of bypassing the LDOs, the recommended power sequence isto apply power to VDDIO, followed by applying power to V1P8DIG
approximately 10 µs later, and then applying power to V1P8ANA
approximately 10 µs later. If necessary, V1P8DIG and VDDIO can be
powered from the same 1.8 V supply, which can also be tied to
V1P8ANA with proper isolation. In this case, proper decoupling
and low frequency isolation is important to maintain the noise
performance of the sensor.

To avoid electrostatic capture of the proof mass when theaccelerometer is subject to input acceleration beyond its fullscale range, all sensor drive clocks turn off for 0.5 ms. In the±2 g/±2.048 g range setting, the overrange protection activates
for input signals beyond approximately ±8 g/±8.192 g (±25%),
and for the ±4 g/±4.096 g and ±8 g/±8.192 g range setting, thethreshold corresponds to about ±16 g (±25%).

POWER SUPPLY DESCRIPTIONOVERRANGE PROTECTION

When overrange protection occurs, the XOUT, YOUT, and ZOUT pinson the ADXL354 begin to drive to midscale. The ADXL355
floats toward zero, and first in, first out (FIFO) begins fillingwith this data.

SELF TESTThe ADXL354/ADXL355 have four different power supply
domains: VSUPPLY, V1P8ANA, V1P8DIG, and VDDIO. The internal
analog and digital circuitry operates at 1.8 V nominal.

The ADXL354 and ADXL355 incorporate a self test featurethat effectively tests their mechanical and electronic systems
simultaneously. In ADXL354, drive the ST1 pin to VDDIO to
invoke self test mode. Then, by driving the ST2 pin to VDDIO,
the ADXL354 applies an electrostatic force to the mechanicalsensor and induces a change in output in response to the force.
The self test delta (or response) is the difference in output
voltages between when ST2 is high and ST2 is low, both when
ST1 is asserted. After the self test measurement is complete,bring both pins low to resume normal operation.

VSUPPLYVSUPPLY is 2.25 V to 3.6 V, which is the input range to the two
LDO regulators that generate the nominal 1.8 V outputs for
V1P8ANA and V1P8DIG. Connect VSUPPLY to VSS to disable the LDO
regulators, which allows driving V1P8ANA and V1P8DIG from anexternal source.

V1P8ANA
All sensor and analog signal processing circuitry operates inthis domain. Offset and sensitivity of the analog output
ADXL354 are ratiometric to this supply voltage. When using
external ADCs, use V1P8ANA as the reference voltage. The digital
output ADXL355 includes ADCs that are ratiometric to V1P8ANA,
thereby rendering offset and sensitivity insensitive to the valueof V1P8ANA. V1P8ANA can be an input or an output as defined by thestate of the VSUPPLY voltage.

The self test operation is similar in the ADXL355, except ST1and ST2 can be accessed through the SELF_TEST register(Register 0x2E).
The self test feature rejects externally applied acceleration andonly responds to the self test force, which allows an accurate
measurement of the self test, even in the presence of externalmechanical noise.

V1P8DIG
V1P8DIG is the supply voltage for the internal logic circuitry. A
separate LDO regulator decouples the digital supply noise fromthe analog signal path. V1P8ANA can be an input or an output as
defined by the state of the VSUPPLY voltage. If driven externally,
V1P8DIG must be the same voltage as the V1P8ANA voltage.

Rev. 0 | Page 22 of 42

Data SheetADXL354/ADXL355

0–10

The analog, low-pass antialiasing filter in the ADXL354/
ADXL355 provides a fixed bandwidth of approximately
1.5 kHz, which is where the output response is attenuated byapproximately 50%. The shape of the filter response in thefrequency domain is that of a sinc3 filter.
The ADXL354 x-axis, y-axis, and z-axis analog outputs include
an amplifier followed by a series 32 kΩ resistor and output tothe XOUT, the YOUT, and the ZOUT pins, respectively.
The ADXL355 provides an internal 20-bit, Σ-Δ ADC to digitize
the filtered analog signal. Additional digital filtering (beyond theanalog, low-pass, antialiasing filter) consists of a low-pass digitaldecimation filter and a bypassable high-pass filter that supports
output data rates between 4 kHz and 3.9 Hz. The decimation
filter consists of two stages. The first stage is fixed decimation
with a 4 kHz ODR with a low-pass filter cutoff (50% reductionin output response) at about 1 kHz. A variable second stage
decimation filter is used for the 2 kHz output data rate and below(it is bypassed for 4 kHz ODR). Figure 60 shows the low-passfilter response with a 1 kHz corner (4 kHz ODR) for the

–20
–30
–40
–50
–60
–70
1

10

100
INPUT FREQUENCY (Hz)

1k

10k

14205-023

The ADXL354/ADXL355 use an analog, low-pass, antialiasing
filter to reduce out of band noise and to limit bandwidth. The
ADXL355 provides further digital filtering options to maintainexcellent noise performance at various ODRs.

ADXL355. Note that Figure 60 does not include the fixed
frequency analog, low-pass, antialiasing filter with a fixedbandwidth of approximately 1.5 kHz.

DIGITAL LPF RESPONSE (dB)

FILTER

Figure 60. ADXL355 Digital Low-Pass Filter (LPF) Response for 4 kHz ODRThe ADXL355 pass band of the signal path relates to the
combined filter responses, including the analog filter previously
discussed, and the digital decimation filter/ODR setting. Table 9shows the delay associated with the decimation filter for eachsetting and provides the attenuation at the ODR/4 corner.

Table 9. Digital Filter Group Delay and Profile
Programmed ODR (Hz)4000
4000/2 = 2000
4000/4 = 1000
4000/8 = 500
4000/16 = 250
4000/32 = 125
4000/64 = 62.5
4000/128 ~ 31
4000/256 ~ 16
4000/512 ~ 8
4000/1024 ~ 4Delay
ODR (Cycles)
Time (ms)
2.52
0.63
2.00
1.00
1.78
1.78
1.63
3.26
1.57
6.27
1.54
12.34
1.51
24.18
1.49
47.59
1.50
96.25
1.50
189.581.50
384.31

Rev. 0 | Page 23 of 42

Attenuation
Decimator at ODR/4 (dB)
Full Path at ODR/4 (dB)
−3.44
−3.63
−2.21
−2.26
−1.92
−1.93
−1.83
−1.83
−1.83
−1.83
−1.83
−1.83
−1.83
−1.83
−1.83
−1.83
−1.83
−1.83
−1.83
−1.83
−1.83
−1.83

ADXL354/ADXL355

Data Sheet

The ADXL355 also includes an interpolation filter after thedecimation filters to produce oversampled/upconverted datathat provides an external synchronization option. See the Data
Synchronization section for more details. Table 11 shows thedelay and attenuation relative to the programmed ODR.

Group delay is the digital filter delay from the input to the ADC
until data is available at the interface (see the Filter section).
This delay is the largest component of the total delay fromsensor to serial interface.
40

32.2122
DELAY (ODR CYCLES)

The ADXL355 also includes an optional digital high-pass filter
with a programmable corner frequency. By default, the highpass filter is disabled. The high pass corner frequency, where
the output is attenuated by 50%, is related to the ODR, and the
HPF_CORNER setting in the filter register (Register 0x28,
Bits[6:4]). Table 10 shows the HPF_CORNER response. Figure 61
and Figure 62 show the simulated high-pass filter response anddelay for a 10 Hz cutoff.

30

20

0

9.8801FREQUENCY (kHz)

14205-025

1
0–10

Figure 62. High-Pass Filter Delay Response for a 4 kHz ODR and an
HPF_CORNER Setting of 001 (Register 0x28, Bits[6:4])

–20

–30

–40

–50
0

9.8801100
FREQUENCY (kHz)

14205-024

AMPLITUDE RELATIVE TO FULL SCALE (dB)

10
0
–3

Figure 61. High-Pass Filter Pass-Band Response for a 4 kHz ODR and an
HPF_CORNER Setting of 001 (Register 0x28, Bits[6:4])

Table 10. Digital High-Pass Filter Response
HPF_CORNER Register Setting(Register 0x28, Bits[6:4])
000
001
010
011
100
101
110

HPF_CORNER Frequency, −3 dB Point Relative to ODR Setting
Not applicable, no high-pass filter enabled
24.7 × 10−4 × ODR
6.2084 × 10−4 × ODR
1.5545 × 10−4 × ODR
0.3862 × 10−4 × ODR
0.0954 × 10−4 × ODR
0.0238 × 10−4 × ODR−3 dB at 4 kHz ODR (Hz)
Off
9.88
2.48
0.62
0.15450.038160.00952

Table 11. Combined Digital Interpolation Filter and Decimation Filter Response
Interpolator Data Rate Resolution
Relative to 64 × ODR (Hz)64 × 4000 = 256000
64 × 2000 = 128000
64 × 1000 = 64000
64 × 500 = 32000
64 × 250 = 16000
64 × 125 = 8000
64 × 62.5 = 4000
64 × 31.25 = 2000
64 × 15.625 = 1000
64 × 7.8125 = 500
64 × 3.90625 = 250

Combined Interpolator/
Decimator Delay (ODR Cycles)
3.51661
3.01262.752
2.6346
2.57732.54732.53257
2.52452
2.520452.51942.51714

Combined Interpolator/
Decimator Delay (ms)
0.88
1.51
2.75
5.27
10.31
20.38
40.52
80.78
161.31
322.48644.39Rev. 0 | Page 24 of 42

Combined Interpolator/Decimator
Output Attenuation at ODR/4 (dB)
−6.18
−4.93
−4.66
−4.58
−4.55
−4.55
−4.55
−4.55
−4.55
−4.55
−4.55

Data SheetADXL354/ADXL355

SERIAL COMMUNICATIONSADXL355

SPI PROTOCOL
Wire the ADXL355 for SPI communication as shown in theconnection diagram in Figure 63. The SPI protocol timing isshown in Figure 64 to Figure 67. The timing scheme follows theclock polarity (CPOL) = 0 and clock phase (CPHA) = 0. The
SPI clock speed ranges from 100 kHz to 10 MHz.

PROCESSOR

CS

DOUT

MOSI

DOUT

MISO

DIN

SCLK

DOUT

14205-026

The 4-wire serial interface communicates in either the SPI or
I2C protocol. It affectively autodetects the format being used,requiring no configuration control to select the format.

Figure 63. 4-Wire SPI Connection

CS
1

2

3

4

5

6

7

8

A6

A5

A4

A3

A2

A1

A0 RW

9

10

11

12

13

14

15

16

D7

D6

D5

D4

D3

D2

D1

D0

15

16

MOSI
MISO

14205-027

SCLK

Figure 64. SPI Timing Diagram—Single-Byte Read

CS
1

2

3

4

5

6

7

8

9

10

11

12

13

14

A6

A5

A4

A3

A2

A1

A0 RW D7 D6 D5 D4 D3 D2 D1 D0

MOSI
MISO

14205-028

SCLK

Figure 65. SPI Timing Diagram—Single-Byte Write

CS
1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

SCLK
A6 A5 A4 A3 A2 A1 A0 RW
BYTE nBYTE 1D7 D6 D5 D4 D3 D2 D1 D0 D7

MISO

D0 D7 D6 D5 D4 D3 D2 D1 D014205-029

MOSI

Figure 66. SPI Timing Diagram—Multibyte Read

CS
1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

SCLK

A6 A5 A4 A3 A2

A1 A0 RW D7 D6 D5 D4 D3 D2 D1 D0 D7

D0 D7 D6 D5 D4 D3 D2 D1 D0

MISO

Figure 67. SPI Timing Diagram—Multibyte Write

Rev. 0 | Page 25 of 4214205-030

BYTE nBYTE 1MOSIADXL354/ADXL355

Data Sheet

I2C PROTOCOL

recent available. It is not guaranteed that XDATA, YDATA, andZDATA form a set corresponding to one sample point in time.
The routine used to retrieve the data from the device controls
this data set continuity. If data transfers are initiated when the
DATA_RDY bit goes high and completes in a time
approximately equal to 1/ODR, XDATA, YDATA, and ZDATA
apply to the same data set.

Figure 68 to Figure 70 detail the I2C protocol timing. The I2C
interface can be used on most buses operating in I2C standard
mode (100 kHz), fast mode (400 kHz), fast mode plus (1 MHz),and high speed mode (3.4 MHz). The ADXL355 I2C device ID
is as follows:

ASEL (pin) = 0, device address = 0x1D
ASEL (pin) = 1, device address = 0x53

READING ACCELERATION OR TEMPERATUREDATA FROM THE INTERFACE

For multibyte read or write transactions through either serialinterface, the internal register address autoincrements. Whenthe top of the register address range, 0x3FF, is reached the autoincrement stops and does not wrap back to Hex Address 0x00.

Acceleration data is left justified and has a register address
order of most significant data to least significant data, whichallows the user to use multibyte transfers and to take only as
much data as required—either 8 bits, 16 bits, or 20 bits plus themarker. Temperature data is 12 bits unsigned, right justified.
The data in XDATA, YDATA, and ZDATA is always the mostThe address autoincrement function disables when the FIFO
address is used, so that data can be read continuously from the
FIFO as a multibyte transaction. In cases where the starting
address of a multibyte transaction is less than the FIFO address,
the address autoincrements until reaching the FIFO address,
and then stops at the FIFO address.

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37

SCL

SDA

REGISTER ADDRESS

A5 A4 A3 A2 A1 A0 RW AK

A60

REPEATSTART

A6 A5 A4 A3 A2 A1 A0 AK

DEVICE ADDRESS
A6 A5 A4 A3 A2DATA BYTE

A1 A0 RW AK

0

STOP

D6 D5 D4 D3 D2 D1 D0

SINGLE BYTE READ

AK

INDICATE SDA ISCONTROLLED BY ADXL355

14205-031

DEVICE ADDRESS

START

2

Figure 68. I C Timing Diagram—Single-Byte Read

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

DEVICE ADDRESSSTARTREGISTER ADDRESS

A6 A5 A4 A3 A2 A1 A0 RW AK

SDA

0DATA BYTE

A6 A5 A4 A3 A2 A1 A0 AK D7 D6 D5 D4 D3 D2 D1 D0 AK

STOP

14205-032

SCL

Figure 69. I2C Timing Diagram—Single-Byte Write

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 19

START

SDA

DEVICE ADDRESS
A6 A5 A4 A3 A2 A1 A0 RW AK

REGISTER ADDRESS0DATA BYTE 1

A6 A5 A4 A3 A2 A1 A0 AK D7 D6 D5 D4 D3 D2 D1 D0 AK D7

Figure 70. I2C Timing Diagram—Multibyte Write

Rev. 0 | Page 26 of 42

DATA BYTE n
D0 AK D7 D6 D5 D4 D3 D2 D1 D0 AK

14205-033

SCL

Data SheetADXL354/ADXL355

FIFO
Figure 71 shows the organization of the data in the FIFO. The
acceleration data is twos complement, 20-bit data. The FIFO
control logic inserts the two LSB reads on the interface. Bit 1
indicates that an attempt was made to read an empty FIFO, andthat the data is not valid acceleration data. Bit 0 is a marker bit
to identify the x-axis, which allows a user to verify that the
FIFO data was correctly read. An acceleration data point for agiven axis occupies one FIFO location. The read pointer, RD_PTR,
points to the oldest stored data that was not read already fromthe interface (see Figure 71). There are no physical x-acceleration,y-acceleration, or z-acceleration data registers. This data also comes
directly from the most recent data set in the FIFO, which points
to by the z pointer, Z_PTR, (see Figure 71).

FIFO operates in a stream mode, that is, when the FIFO
overruns new data overwrites the oldest data in the FIFO. A
read from the FIFO address guarantees that the three bytes
associated with the acceleration measurement on an axis allpertain to the same measurement. The FIFO never overruns,
and data is always taken out in sets (multiples of three data
points).
There are 96 21-bit locations in the FIFO. Each location
contains 20 bits of data and a marker bit for the x-axis data. A
single-byte read from the FIFO address pops one location fromthe FIFO. A multibyte read to the FIFO location pops the FIFO
on the read of the first byte and every third byte read thereafter.

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

Z_PTR

Z19 Z18 Z17 Z16 Z15 Z14 Z13 Z12

Z11 Z10

Z9

Z8

Z7

Z6

Z5

Z4

Z3

Z2

Z1

Z0

0

0

Z_PTR – 1

Y19 Y18 Y17 Y16 Y15 Y14 Y13 Y12

Y11 Y10 Y9

Y8

Y7

Y6

Y5

Y4

Y3

Y2

Y1

Y0

0

0

Z_PTR – 2

RD_PTRVIRTUAL BITS
(NOT ALLOCATED IN THE FIFO)ACCELERATION DATAEMPTY INDICATOR
X-AXIS MARKER
ASCENDING SPI ADDRESSES

Figure 71. FIFO Data OrganizationRev. 0 | Page 27 of 4214205-035

DATA SET. SAMPLE POINT
ASCENDINGIS THE SAME ACROSSA SINGLE X-AXIS, Y-AXIS, SPI ADDRESSESAND Z-AXIS DATA SET.

ASCENDING FIFO ADDRESSESZ_PTR + 1

ADXL354/ADXL355

Data Sheet

INTERRUPTS
The status register (Register 0x04) contains five individual bits,
four of which can be mapped to either the INT1 pin, the INT2 pin,or both. The polarity of the interrupt, active high or active low,
is also selectable via the INT_POL bit in the range (Register 0x2C)
register. In general, the status register clears when read, but thisis not the case if the condition that caused the interrupt persists
after the read of the register. The definition of persist varies
slightly in each case, but it is described in the following sections.
The DRDY pin is similar to an interrupt pins (INTx) but clears
very differently. This case is also described.

FIFO_FULL
The FIFO_FULL bit is set when the entries in the FIFO areequal to the setting of the FIFO_SAMPLES bits. It clears as
follows:••

If the entries in the FIFO fall below the FIFO_SAMPLES,
which is only the case if sufficient data is read from the
FIFO.
On a read of the status register, but only if the entries in the
FIFO are less than the FIFO_SAMPLES bits.

DATA_RDY

FIFO_OVRThe DATA_RDY bit is set when new acceleration data isavailable to the interface. It clears on a read of the status register.
It is not set again until acceleration data that is newer than thestatus register read is available.

The FIFO_OVR bit is set when the FIFO is so far overrange thatdata is lost. The specified size of the FIFO is 96 locations. Thereis an additional three location buffer to compensate for delaysin the synchronization of the clock domains. It is only when
there is an attempt to write past this 99 location limit that
FIFO_OVR is set.

Special logic on the clear of the DATA_RDY bit covers thecorner case where new data arrives during the read of the status
register. In this case, the data ready condition may be missedcompletely. This logic results in a delay of the clearing of
DATA_RDY of up to four 512 kHz cycles.

DRDY PINDATA is not a status register bit; it instead behaves similar to anunmaskable interrupt. DRDY is set when new acceleration data
is available to the interface. It clears on a read of the FIFO, on aread of XDATA, YDATA, or ZDATA, or by an autoclear
function that occurs approximately halfway between output
acceleration data sets.
DRDY is always active high. The INT_POL bit does not affect
DRDY. In EXT_SYNC modes, the first few DRDY pulses after
initial synchronization can be lost or corrupted. The length of
this potential corruption is less than the group delay.

A read of the status register clears FIFO_OVR. It is not set again
until data is lost subsequent to this data register read.

ACTIVITY
The activity bit (Register 0x04, Bit 3) is set when the measured
acceleration on any axis is above the ACT_THRESH bits for
ACT_COUNT consecutive measurements. An over thresholdcondition can shift from one axis to another on successive
measurements and is still counted toward the consecutive
ACT_COUNT count.
A read of the status register clears the activity bit (Register 0x04,
Bit 3), but it sets again at the end of the next measurement if theactivity bit (Register 0x04, Bit 3) conditions are still satisfied.

NVM_BUSY
The NVM_BUSY bit indicates that the nonvolatile memory(NVM) controller is busy, and it cannot be accessed to read,
write, or generate an interrupt.
A status register read that occurs after the NVM controller is nolonger busy clears NVM_BUSY.

Rev. 0 | Page 28 of 42

Data SheetADXL354/ADXL355

EXTERNAL SYNCHRONIZATION AND
INTERPOLATION
There are three possible synchronization options for the ADXL355,
shown in Figure 72 to Figure 74. For clarity, the clock frequencies
and delays are drawn to scale. The labels in Figure 72 to Figure 74
are defined as follows:•••

Internal ODR is the alignment of the decimated output
data based on the internal clock.
ADC clock shows the internal master clock rate
DRDY is an output indicator signaling a sample is ready.

EXT_SYNC = 01—External Sync and External Clock

The three modes are include as follows:•••

The advantage of this mode is that data is available at a user
defined sample rate and is asynchronous to the internal oscillator.
The disadvantage of this mode is that the group delay is increased,
and there is increased attenuation at the band edge. Additionally,
because there is a limit to the time resolution, there is some
distortion related to the mismatch of the external sync relative
to the internal oscillator. This mismatch degrades spectral
performance. The group delay is based on the decimation setting
and interpolation setting (see Table 11). Table 13 shows the delay
between the SYNC signal (input) to DRDY (output).

No external synchronization (internal clocks used)
Synchronization with interpolation filter enabled
Sync with an external sync and clock signals, nointerpolation filter

EXT_SYNC = 00—No External Sync or Interpolation
For this case, an internal clock that serves as the synchronization
master generates the data. No external signals are required, andthis is used commonly when the external processor retrieves
data from the device asynchronously and absolute synchronization
to an external source is not required. Use Register 0x28 to program
the ODR.
The device outputs a DRDY (active high) to signal that a new
sample is available, and data is retrieved from the real-timeregisters or the FIFO. The group delay is based on thedecimation setting as shown in Table 9.

In this case, an external source provides an external clock at afrequency of 4 × 64 × ODR. The external clock becomes themaster clock source for the device. In addition, an external
synchronization signal is needed to align the decimation filter
output to a specific clock edge, which provides full external
synchronization and is commonly used when a fixed external
clock captures and processes data, and asynchronous clock(s) are
not allowed. When using multiple sensors, synchronization with an
external master clock is beneficial and requires time alignment.
When configured for EXT_SYNC = 01 with an ODR of 4 kHz,the user must supply an external clock at 1.024 MHz (64 × 4 ×
4 kHz) on the INT2 pin (Pin 13), and an external synchronization
on DRDY pin (Pin 14), as shown in Table 12.
Special restrictions when using this mode include the following:•

EXT_SYNC = 10—External Sync with Interpolation
In this case, the internal clock generates data; however, aninterpolation filter provides additional time resolution of 64
times the programmed ODR. Synchronization using interpolation
filters and an external ODR clock is commonly used when theexternal processor can provide a synchronization signal (whichis asynchronous to the internal clock) at the desired ODR.
Synchronization with the interpolation filter enabled(EXT_SYNC = 10) allows the nonsynchronous external clock to
output data most closely associated with the external clock
rising edge. The interpolation filter provides a frequency
resolution related to ODR (see Table 11).

•••

An external clock (EXT_CLK) must be provided as well as
an external sync.
The frequency of EXT_CLK must be exactly 4 × 64 × ODR.
The width of sync must be a minimum of four EXT_CLK
periods.
The phase of sync must meet an approximate 25 ns setup
time to the EXT_CLK rising edge.

When using the EXT_SYNC mode and without providing sync,
the device runs on its own synchronization. Similarly, after
synchronization, the device continues to run synchronized to
the last sync pulse it received, which means that EXT_SYNC = 01
mode can be used with only a single synchronization pulse.
The interpolation filter provides a frequency resolution related to
the ODR (see Table 11). In this case, the data provided corresponds
to the external signal, which can be greater than the set ODR,
but the output pass band remains the same it was prior to theinterpolation filter.

Table 12. Multiplexing of INT2 and DRDY
EXT_CLK
0
0
1
1
0
0

Register or Bit Fields
EXT_SYNC[1:0] INT_MAP[7:4]
00
0000
00
Not 000000
0000
00
Not 00002
01
0000
011
Not 0000

INT2 (Pin 13)
Low
INT2
EXT_CLK
EXT_CLK
DRDY
INT2

Pins
DRDY (Pin 14)
DRDY
DRDY
DRDY
DRDY
SYNC
SYNC

Rev. 0 | Page 29 of 42

Comments
Synchronization is to the internal clocks, and there is
no external clock synchronization.

These options reset the digital filters on every
synchronization pulse and are not recommended.

ADXL354/ADXL355

Data Sheet

EXT_CLK
1
1

Register or Bit Fields
EXT_SYNC[1:0] INT_MAP[7:4]
011
0000
011
Not 00002

INT2 (Pin 13)
EXT_CLK
EXT_CLK

0
0
1
1

10
101
101
101

DRDY
INT2
EXT_CLK
EXT_CLK1
20000
Not 0000
0000
Not 0000

Pins
DRDY (Pin 14)
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC

Comments
External synchronization, no interpolation filter, andDRDY (active high) signals that data is ready. Data
represents a sample point group delay earlier in time.
External synchronization, interpolation filter, andDRDY (active high) signals that data is ready. Data
sample group delay earlier in time.

No DRDY.
No INT2, even though it is enabled.
GROUP DELAY(FIXED RELATIVE TO DRDY)SAMPLE POINT
INTERNAL ODR

14205-036

ADC MOD. CLK.
64× ODR
DRDY

Figure 72. External Synchronization Option—EXT_SYNC = 00, Internal Sync

SAMPLE POINTGROUP DELAY(FIXED RELATIVE TO SYNC)

INTERFACE SYNCHRONIZATION DELAY

INTERNAL ODR

14205-037

INTERPOLATOR
64× ODR
SYNC
110% ODRDRDYFigure 73. External Synchronization Option—EXT_SYNC = 10, External Sync, External Clock, Interpolation Filter

SAMPLE POINTGROUP DELAY(FIXED RELATIVE TO SYNC)

INTERNAL ODR
EXT_CLK(4 × 64) × SYNC
SYNCHRONIZE
14205-038

SYNC

LOST SAMPLE
DRDY

Figure 74. External Synchronization Option—EXT_SYNC = 01, External Sync, No Interpolation Filter

Table 13. EXT_SYNC = 10, DRDY Delay
ODR_LPF
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0x10

Delay (OSC Cycles)
8
10
14
22
38
70
134
262
1031
2054
4102

Rev. 0 | Page 30 of 42

Data SheetADXL354/ADXL355

ADXL355 REGISTER MAP
Note that while configuring the ADXL355 in an application, all configuration registers must be programmed before enabling measurement modein the POWER_CTL register. When the ADXL355 is in measurement mode, only the following configurations can change: the HPF_CORNER
bits in the filter register, the INT_MAP register, the ST1 and ST2 bits in the SELF_TEST register, and the reset register.
Table 14. ADXL355 Register Map
Hex. Addr. Register Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset R/W

0x00

DEVID_AD

DEVID_AD

0xAD R

0x01

DEVID_MST

DEVID_MST

0x1D R

0x02

PARTIDPARTID

0xED R

0x03

REVID

REVID

0x01

R

0x04

Status

FIFO_FULL DATA_RDY 0x00

R

0x05

FIFO_ENTRIES

0x00

R

0x06

TEMP2

0x00

R

0x07

TEMP1

Temperature, Bits[7:0]

0x00

R

0x08

XDATA3XDATA, Bits[19:12]

0x00

R

0x09

XDATA2XDATA, Bits[11:4]

0x00

R

0x0A

XDATA1

0x00

R

0x0B

YDATA3YDATA, Bits[19:12]

0x00

R

0x0C

YDATA2YDATA, Bits[11:4]

0x00

R

0x0D

YDATA1

0x00

R

0x0E

ZDATA3ZDATA, Bits[19:12]

0x00

R

0x0F

ZDATA2ZDATA, Bits[11:4]

0x00

R

0x10

ZDATA1

0x00

R

0x11

FIFO_DATAFIFO_DATA

0x00

R

0x1E

OFFSET_X_H

OFFSET_X, Bits[15:8]

0x00

R/W

0x1F

OFFSET_X_L

OFFSET_X, Bits[7:0]

0x00

R/W

0x20

OFFSET_Y_H

OFFSET_Y, Bits[15:8]

0x00

R/W

0x21

OFFSET_Y_L

OFFSET_Y, Bits[7:0]

0x00

R/W

0x22

OFFSET_Z_H

OFFSET_Z, Bits[15:8]

0x00

R/W

0x23

OFFSET_Z_L

OFFSET_Z, Bits[7:0]

0x00

R/W

0x24

ACT_EN

0x00

R/W

0x25

ACT_THRESH_H

ACT_THRESH, Bits[15:8]

0x00

R/W

0x26

ACT_THRESH_L

ACT_THRESH, Bits[7:0]

0x00

R/W

0x27

ACT_COUNTACT_COUNT

0x01

R/W

0x28

FilterReserved

0x00

R/W

0x29

FIFO_SAMPLES

Reserved

0x60

R/W

0x2A

INT_MAP

ACT_EN2 OVR_EN2 FULL_EN2 RDY_EN2

0x00

R/W

0x2B

Sync

EXT_SYNC

0x00

R/W

0x2C

Range

Range

0x81

R/W

0x2D

POWER_CTL

0x01

R/W

0x2E

SELF_TEST

0x00

R/W

0x2F

Reset

0x00

W

Reserved

NVM_BUSY Activity

Reserved

FIFO_OVR

FIFO_ENTRIESReserved

Temperature, Bits[11:8]

XDATA, Bits[3:0]

Reserved

YDATA, Bits[3:0]

Reserved

ZDATA, Bits[3:0]

Reserved

Reserved

ACT_Z

HPF_CORNER

ACT_X

ODR_LPFFIFO_SAMPLES
ACT_EN1 OVR_EN1

Reserved
I2C_HS

ACT_Y

INT_POL

FULL_EN1

EXT_CLK
Reserved

Reserved

RDY_EN1

DRDY_OFF TEMP_OFF STANDBY

Reserved

ST2
Reset

Rev. 0 | Page 31 of 42

ST1

ADXL354/ADXL355

Data SheetREGISTER DEFINITIONSThis section describes the functions of the ADXL355 registers. The ADXL355 powers up with the default register values, as shown in the
Reset column of Table 14.

ANALOG DEVICES ID REGISTER
This register contains the Analog Devices ID, 0xAD.

Address: 0x00, Reset: 0xAD, Name: DEVID_AD
Table 15. Bit Descriptions for DEVID_AD
Bits
[7:0]

Bit Name
DEVID_AD

Settings

Description
Analog Devices ID

Reset
0xAD

AccessR

ANALOG DEVICES MEMS ID REGISTER
This register contains the Analog Devices MEMS ID, 0x1D.

Address: 0x01, Reset: 0x1D, Name: DEVID_MST
Table 16. Bit Descriptions for DEVID_MST
Bits
[7:0]

Bit Name
DEVID_MST

Settings

Description
Analog Devices MEMS ID

Reset
0x1D

AccessR

DEVICE ID REGISTER
This register contains the device ID, 0xED (355 octal).

Address: 0x02, Reset: 0xED, Name: PARTID
Table 17. Bit Descriptions for PARTID
Bits
[7:0]

Bit Name
PARTID

Settings

Description
Device ID (355 octal)

Reset
0xED

AccessR

PRODUCT REVISION ID REGISTER
This register contains the product revision ID, beginning with 0x00 and incrementing for each subsequent revision.

Address: 0x03, Reset: 0x00, Name: REVID
Table 18. Bit Descriptions for REVID
Bits
[7:0]

Bit Name
REVID

Settings

Description
Mask revision

Reset
0x01

AccessR

STATUS REGISTER
This register includes bits that describe the various conditions of the ADXL355.

Address: 0x04, Reset: 0x00, Name: STATUS
Table 19. Bit Descriptions for STATUS
Bits
[7:5]
4
3
2
1
0

Bit Name
Reserved
NVM_BUSY
Activity
FIFO_OVR
FIFO_FULLDATA_RDY

Settings

Description
Reserved.
NVM controller is busy with either refresh, programming, or built-in, self test (BIST).
Activity, as defined in the THRESH_ACT and COUNT_ACT registers, is detected.
FIFO has overrun, and the oldest data is lost.
FIFO watermark is reached.
A complete x-axis, y-axis, and z-axis measurement was made and results can be read.

Rev. 0 | Page 32 of 42

Reset
0x0
0x0
0x0
0x0
0x0
0x0

AccessR
R
R
R
R
R

Data SheetADXL354/ADXL355

FIFO ENTRIES REGISTER
This register indicates the number of valid data samples present in the FIFO buffer. This number ranges from 0 to 96.
Address: 0x05, Reset: 0x00, Name: FIFO_ENTRIES
Table 20. Bit Descriptions for FIFO_ENTRIES
Bits
7

Bit Name
Reserved[6:0]

FIFO_ENTRIES

Settings

Description
Reserved

Reset
0x0

AccessR

Number of data samples stored in the FIFO

0x0

R

TEMPERATURE DATA REGISTERS
These two registers contain the uncalibrated temperature data. The nominal intercept is 1852 LSB at 25°C and the nominal slope is−9.05 LSB/°C. TEMP2 contains the four most significant bits, and TEMP1 contains the eight least significant bits of the 12-bit value.

Address: 0x06, Reset: 0x00, Name: TEMP2
Table 21. Bit Descriptions for TEMP2
Bits
[7:4]
[3:0]

Bit Name
Reserved
Temperature, Bits[11:8]

Settings

Description
Reserved.
Uncalibrated temperature data

Reset

Access0x0

R

Description
Uncalibrated temperature data

Reset
0x0

AccessR

Address: 0x07, Reset: 0x00, Name: TEMP1
Table 22. Bit Descriptions for TEMP1
Bits
[7:0]

Bit Name
Temperature, Bits[7:0]

Settings

X-AXIS DATA REGISTERS
These three registers contain the x-axis acceleration data. Data is left justified and formatted as twos complement.

Address: 0x08, Reset: 0x00, Name: XDATA3
Table 23. Bit Descriptions for XDATA3
Bits
[7:0]

Bit Name
XDATA, Bits[19:12]

Settings

Description
X-axis data

Reset
0x0

AccessR

Description
X-axis data

Reset
0x0

AccessR

Description
X-axis data
Reserved

Reset
0x0
0x0

AccessR
R

Address: 0x09, Reset: 0x00, Name: XDATA2Table 24. Bit Descriptions for XDATA2
Bits
[7:0]

Bit Name
XDATA, Bits[11:4]

Settings

Address: 0x0A, Reset: 0x00, Name: XDATA1
Table 25. Bit Descriptions for XDATA1
Bits
[7:4]
[3:0]

Bit Name
XDATA, Bits[3:0]
Reserved

Settings

Rev. 0 | Page 33 of 42

ADXL354/ADXL355

Data Sheet

Y-AXIS DATA REGISTERS
These three registers contain the y-axis acceleration data. Data is left justified and formatted as twos complement.

Address: 0x0B, Reset: 0x00, Name: YDATA3
Table 26. Bit Descriptions for YDATA3
Bits
[7:0]

Bit Name
YDATA, Bits[19:12]

Settings

Description
Y-axis data

Reset
0x0

AccessR

Description
Y-axis data

Reset
0x0

AccessR

Description
Y-axis data
Reserved

Reset
0x0
0x0

AccessR
R

Address: 0x0C, Reset: 0x00, Name: YDATA2Table 27. Bit Descriptions for YDATA2
Bits
[7:0]

Bit Name
YDATA, Bits[11:4]

Settings

Address: 0x0D, Reset: 0x00, Name: YDATA1
Table 28. Bit Descriptions for YDATA1
Bits
[7:4]
[3:0]

Bit Name
YDATA, Bits[3:0]
Reserved

Settings

Z-AXIS DATA REGISTERS
These three registers contain the z-axis acceleration data. Data is left justified and formatted as twos complement.

Address: 0x0E, Reset: 0x00, Name: ZDATA3
Table 29. Bit Descriptions for ZDATA3
Bits
[7:0]

Bit Name
ZDATA, Bits[19:12]

Settings

Description
Z-axis data

Reset
0x0

AccessR

Description
Z-axis data

Reset
0x0

AccessR

Description
Z-axis data
Reserved

Reset
0x0
0x0

AccessR
R

Address: 0x0F, Reset: 0x00, Name: ZDATA2Table 30. Bit Descriptions for ZDATA2
Bits
[7:0]

Bit Name
ZDATA, Bits[11:4]

Settings

Address: 0x10, Reset: 0x00, Name: ZDATA1
Table 31. Bit Descriptions for ZDATA1
Bits
[7:4]
[3:0]

Bit Name
ZDATA, Bits[3:0]
Reserved

Settings

Rev. 0 | Page 34 of 42

Data SheetADXL354/ADXL355

FIFO ACCESS REGISTER
Address: 0x11, Reset: 0x00, Name: FIFO_DATA
Read this register to access data stored in the FIFO.
Table 32. Bit Descriptions for FIFO_DATA
Bits
[7:0]

Bit Name
FIFO_DATA

Settings

Description
FIFO data is formatted to 24 bits, 3 bytes, most significant byte first. A read to thisaddress pops an effective three equal byte words of axis data from the FIFO. Two
subsequent reads or a multibyte read completes the transaction of this data onto theinterface. Continued reading or a sustained multibyte read of this field continues to
pop the FIFO every third byte. Multibyte reads to this address do not increment theaddress pointer. If this address is read due to an autoincrement from the previous
address, it does not pop the FIFO. Instead, it returns zeros and increments on to thenext address.

Reset
0x0

Access
R

Reset
0x0

Access
R/W

Reset
0x0

Access
R/W

Reset
0x0

Access
R/W

Reset
0x0

AccessR/W

X-AXIS OFFSET TRIM REGISTERS
Address: 0x1E, Reset: 0x00, Name: OFFSET_X_H
Table 33. Bit Descriptions for OFFSET_X_H
Bits
[7:0]

Bit Name
OFFSET_X,
Bits[15:8]

Settings

Description
Offset added to x-axis data after all other signal processing. Data is in twos complement
format. The significance of OFFSET_X[15:0] matches the significance of XDATA[19:4].

Address: 0x1F, Reset: 0x00, Name: OFFSET_X_L
Table 34. Bit Descriptions for OFFSET_X_L
Bits
[7:0]

Bit Name
OFFSET_X,
Bits[7:0]

Settings

Description
Offset added to x-axis data after all other signal processing. Data is in twos complement
format. The significance of OFFSET_X[15:0] matches the significance of XDATA[19:4].

Y-AXIS OFFSET TRIM REGISTERS
Address: 0x20, Reset: 0x00, Name: OFFSET_Y_H
Table 35. Bit Descriptions for OFFSET_Y_H
Bits
[7:0]

Bit Name
OFFSET_Y,
Bits[15:8]

Settings

Description
Offset added to y-axis data after all other signal processing. Data is in twos complement
format. The significance of OFFSET_Y[15:0] matches the significance of YDATA[19:4].

Address: 0x21, Reset: 0x00, Name: OFFSET_Y_L
Table 36. Bit Descriptions for OFFSET_Y_L
Bits
[7:0]

Bit Name
OFFSET_Y,
Bits[7:0]

Settings

Description
Offset added to y-axis data after all other signal processing. Data is in twos complement
format. The significance of OFFSET_Y[15:0] matches the significance of YDATA[19:4].

Rev. 0 | Page 35 of 42

ADXL354/ADXL355

Data Sheet

Z-AXIS OFFSET TRIM REGISTERS
Address: 0x22, Reset: 0x00, Name: OFFSET_Z_H
Table 37. Bit Descriptions for OFFSET_Z_H
Bits
[7:0]

Bit Name
OFFSET_Z,
Bits[15:8]

Settings

Description
Offset added to z-axis data after all other signal processing. Data is in twos complement
format. The significance of OFFSET_Z[15:0] matches the significance of ZDATA[19:4].

Reset
0x0

Access
R/W

Reset
0x0

AccessR/W

Address: 0x23, Reset: 0x00, Name: OFFSET_Z_L
Table 38. Bit Descriptions for OFFSET_Z_L
Bits
[7:0]

Bit Name
OFFSET_Z,
Bits[7:0]

Settings

Description
Offset added to z-axis data after all other signal processing. Data is in twos complement
format. The significance of OFFSET_Z[15:0] matches the significance of ZDATA[19:4].

ACTIVITY ENABLE REGISTER
Address: 0x24, Reset: 0x00, Name: ACT_EN
Table 39. Bit Descriptions for ACT_EN
Bits
[7:3]
2
1
0

Bit Name
Reserved
ACT_Z
ACT_Y
ACT_X

Settings

Description
Reserved.
Z-axis data is a component of the activity detection algorithm.
Y-axis data is a component of the activity detection algorithm.
X-axis data is a component of the activity detection algorithm.

Reset
0x0
0x0
0x0
0x0

Access
R
R/W
R/W
R/W

ACTIVITY THRESHOLD REGISTERS
Address: 0x25, Reset: 0x00, Name: ACT_THRESH_H
Table 40. Bit Descriptions for ACT_THRESH_H
Bits
[7:0]

Bit Name
ACT_THRESH[15:8]

Settings

Description
Threshold for activity detection. Acceleration magnitude must be above
ACT_THRESH to trigger the activity counter. ACT_THRESH is an unsigned
magnitude. The significance of ACT_TRESH[15:0] matches the significance of
XDATA, YDATA, and ZDATA[18:3].

Reset
0x0

Access
R/W

Reset
0x0

Access
R/W

Reset
0x1

AccessR/W

Address: 0x26, Reset: 0x00, Name: ACT_THRESH_L
Table 41. Bit Descriptions for THRESH_ACT_X_L
Bits
[7:0]

Bit Name
ACT_THRESH[7:0]

Settings

Description
Threshold for activity detection. Acceleration magnitude must be above
ACT_THRESH to trigger the activity counter. ACT_THRESH is an unsigned
magnitude. The significance of ACT_TRESH[15:0] matches the significance of
XDATA, YDATA, and ZDATA[18:3].

ACTIVITY COUNT REGISTER
Address: 0x27, Reset: 0x01, Name: ACT_COUNT
Table 42. Bit Descriptions for ACT_COUNT
Bits
[7:0]

Bit Name
ACT_COUNT

Settings

Description
Number of consecutive events above threshold required to detect activity

Rev. 0 | Page 36 of 42

Data SheetADXL354/ADXL355

FILTER SETTINGS REGISTER
Address: 0x28, Reset: 0x00, Name: Filter
Use this register to specify parameters for the internal high-pass and low-pass filters.
Table 43. Bit Descriptions for Filter
Bits
7
[6:4]

Bit Name
Reserved
HPF_CORNER

Settings

000
001
010
011
100
101
110
[3:0]

ODR_LPF
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010

Description
Reserved−3 dB filter corner for the first-order, high-pass filter relative to the ODR
Not applicable, no high-pass filter enabled
247 × 10−3 × ODR
62.084 × 10−3 × ODR
15.545 × 10−3 × ODR
3.862 × 10−3 × ODR
0.954 × 10−3 × ODR
0.238 × 10−3 × ODRODR and low-pass filter corner4000 Hz and 1000 Hz
2000 Hz and 500 Hz
1000 Hz and 250 Hz
500 Hz and 125 Hz
250 Hz and 62.5 Hz
125 Hz and 31.25 Hz
62.5 Hz and 15.625 Hz
31.25 Hz and 7.813 Hz
15.625 Hz and 3.906 Hz
7.813 Hz and 1.953 Hz
3.906 Hz and 0.977 Hz

Reset
0x0
0x0

Access
R
R/W

0x0

R/W

FIFO SAMPLES REGISTER
Address: 0x29, Reset: 0x60, Name: FIFO_SAMPLES
Use the FIFO_SAMPLES value to specify the number of samples to store in the FIFO. The default value of this register is 0x60 to avoid
triggering the FIFO watermark interrupt.
Table 44. Bit Descriptions for FIFO_SAMPLES
Bits
7
[6:0]

Bit Name
Reserved
FIFO_SAMPLES

Settings

Description
Reserved.
Watermark number of samples stored in the FIFO that triggers a FIFO_FULL condition.
Values range from 1 to 96.

Reset
0x0
0x60

AccessR
R/W

INTERRUPT PIN (INTx) FUNCTION MAP REGISTER
Address: 0x2A, Reset: 0x00, Name: INT_MAP
The INT_MAP register configures the interrupt pins. Bits[7:0] select which function(s) generate an interrupt on the INT1 and INT2 pins.
Multiple events can be configured. If the corresponding bit is set to 1, the function generates an interrupt on the interrupt pins.
Table 45. Bit Descriptions for INT_MAP
Bits
7
6
5
4
3
2
1
0

Bit Name
ACT_EN2OVR_EN2
FULL_EN2
RDY_EN2
ACT_EN1OVR_EN1
FULL_EN1
RDY_EN1

Settings

Description
Activity interrupt enable on INT2
FIFO_OVR interrupt enable on INT2
FIFO_FULL interrupt enable on INT2
DATA_RDY interrupt enable on INT2
Activity interrupt enable on INT1
FIFO_OVR interrupt enable on INT1
FIFO_FULL interrupt enable on INT1
DATA_RDY interrupt enable on INT1
Rev. 0 | Page 37 of 42

Reset
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0

Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

ADXL354/ADXL355

Data Sheet

DATA SYNCHRONIZATION
Address: 0x2B, Reset: 0x00, Name: Sync
Use this register to control the external timing triggers.
Table 46. Bit Descriptions for Sync
Bits
[7:3]
2
[1:0]

Bit Name
Reserved
EXT_CLK
EXT_SYNC

Settings

00
01
10
11

Description
Reserved.
Enable external clock.
Enable external sync control.
Internal sync.
External sync, no interpolation filter. After synchronization, and for EXT_SYNC within
specification, DATA_RDY occurs on EXT_SYNC.
External sync, interpolation filter, next available data indicated by DATA_RDY 14 to8204 oscillator cycles later (longer delay for higher ODR_LPF setting), data represents
a sample point group delay earlier in time.
Reserved.

Reset
0x0
0x0
0x0

AccessR
R/W
R/W

I2C SPEED, INTERRUPT POLARITY, AND RANGE REGISTER
Address: 0x2C, Reset: 0x81, Name: Range
Table 47. Bit Descriptions for Range
Bits
7

Bit Name
I2C_HS

6

INT_POL

Settings

0
1
[5:2]
[1:0]

Reserved
Range
01
10
11

Description
I2C speed.
1 = high speed mode.
0 = fast mode.
Interrupt polarity.
INT1 and INT2 are active low.
INT1 and INT2 are active high.
Reserved.
Range.
±2 g.
±4 g.
±8 g.

Reset
0x1

Access
R/W

0x0

R/W

0x0
0x1

R
R/W

POWER CONTROL REGISTER
Address: 0x2D, Reset: 0x01, Name: POWER_CTL
Table 48. Bit Descriptions for POWER_CTL
Bits
[7:3]
2
1

Bit Name
Reserved
DRDY_OFF
TEMP_OFF0

STANDBY

Settings

1

0

Description
Reserved.
Set to 1 to force the DRDY output to 0 in modes where it is normally signal data ready.
Set to 1 to disable temperature processing. Temperature processing is also disabled
when STANDBY = 1.
Standby or measurement mode.
Standby mode. In standby mode, the device is in a low power state, and thetemperature and acceleration datapaths are not operating. In addition, digital
functions, including FIFO pointers, reset. Changes to the configuration setting of thedevice must be made when STANDBY = 1. An exception is a high-pass filter that canbe changed when the device is operating.
Measurement mode.

Rev. 0 | Page 38 of 42

Reset
0x0
0x0
0x0

Access
R
R/W
R/W

0x1

R/W

Data SheetADXL354/ADXL355

SELF TEST REGISTER
Address: 0x2E, Reset: 0x00, Name: SELF_TEST
Refer to the Self Test section for more information on the operation of the self test feature.
Table 49. Bit Descriptions for SELF_TEST
Bits
[7:2]
1
0

Bit Name
Reserved
ST2
ST1

Settings

Description
Reserved.
Set to 1 to enable self test force
Set to 1 to enable self test mode

Reset
0x0
0x0
0x0

AccessR
R/W
R/W

RESET REGISTER
Address: 0x2F, Reset: 0x00, Name: Reset
Table 50. Bit Descriptions for Reset
Bits
[7:0]

Bit Name
Reset

Settings

Description
Write Code 0x52 to resets the device, similar to a power-on reset (POR)

Rev. 0 | Page 39 of 42

Reset
0x0

AccessW

ADXL354/ADXL355

Data Sheet

RECOMMENDED SOLDERING PROFILE
Figure 75 and Table 51 provide details about the recommended soldering profile.
CRITICAL ZONETL TO TP

tP

TP

tL

TSMAX
TSMIN

tS

RAMP-DOWNPREHEAT

t25°C TO PEAK
TIME

14205-039

TEMPERATURE

RAMP-UP
TL

Figure 75. Recommended Soldering Profile

Table 51. Recommended Soldering Profile
Profile Feature
Average Ramp Rate from Liquid Temperature (TL) to Peak Temperature (TP)Preheat
Minimum Temperature (TSMIN)
Maximum Temperature (TSMAX)Time from TSMIN to TSMAX (tS)TSMAX to TL Ramp-Up Rate
Liquid Temperature (TL)
Time Maintained Above TL (tL)Peak Temperature (TP)Time of Actual TP − 5°C (tP)
Ramp-Down Rate
Time from 25°C to Peak Temperature (t25°C TO PEAK)

Rev. 0 | Page 40 of 42

Sn63/Pb37
3°C/sec maximum

Condition
Pb-Free
3°C/sec maximum

100°C
150°C
60 sec to 120 sec
3°C/sec maximum
183°C
60 sec to 150 sec
240°C + 0°C/−5°C
10 sec to 30 sec
6°C/sec maximum
6 minutes maximum

150°C
200°C
60 sec to 180 sec
3°C/sec maximum
217°C
60 sec to 150 sec
260°C + 0°C/−5°C
20 sec to 40 sec
6°C/sec maximum
8 minutes maximum

Data SheetADXL354/ADXL355

PCB FOOTPRINT PATTERN
Figure 76 shows the PCB footprint pattern and dimensions in millimeters.
3.22mm0.68mm
0.70mm

3.80mm14 PLCS
1.8mm × 0.68mm

3.80mmFigure 76. PCB Footprint Pattern and Dimensions in Millimeters

Rev. 0 | Page 41 of 4214205-040

4.5mm

0.70mmADXL354/ADXL355

Data Sheet

PACKAGING AND ORDERING INFORMATIONOUTLINE DIMENSIONSDETAIL A

6.25
6.00 SQ
5.85

0.80
BSC

2.25
2.05
1.85

1.674 BSC
0.510 REF

0.30 SQ
12(PIN 1 INDEX)

14

11

1

DETAIL A

5.60
SQ

R 0.103(14 PLCS)

3.81
REF

0.508
BSC
4

8
7

TOP VIEW

0.10 BSC

R 0.203(14 PLCS)

0.15
BSC

5

BOTTOM VIEW

SIDE VIEW

2.20 REF

2.54 REF

0.914
BSC
05-27-2016-B

PKG-004554

R 0.25(4 PLCS)

Figure 77. 14-Terminal Ceramic Leadless Chip Carrier [LCC](E-14-1)
Dimensions shown in millimeters

BRANDING INFORMATIONPIN ONE LOCATOR, NO OTHER BRAND ON THIS LINEADXL354B, ADXL354C, OR ADXL355B#YYWW

TWO DIGIT YEAR, TWO DIGIT WEEK ID
SIX DIGIT LOT NUMBER

6 DIGIT LOT NUMBER

14205-078

NO BRAND ON THIS LINEPART NUMBER

Figure 78. Branding Information

ORDERING GUIDE
Model1
ADXL354BEZADXL354BEZ-RL
ADXL354BEZ-RL7
ADXL354CEZADXL354CEZ-RL
ADXL354CEZ-RL7
ADXL355BEZ

OutputMode
AnalogAnalogAnalogAnalogAnalogAnalogDigitalADXL355BEZ-RL

DigitalADXL355BEZ-RL7

DigitalMeasurement
Range (g)±2, ±4±2, ±4±2, ±4±2, ±8±2, ±8±2, ±8±2.048, ±4.096,±8.192±2.048, ±4.096,±8.192±2.048, ±4.096,±8.192

Specified
Voltage (V)
3.3
3.3
3.3
3.3
3.3
3.3
3.3

Temperature Range−40°C to +125°C−40°C to +125°C−40°C to +125°C−40°C to +125°C−40°C to +125°C−40°C to +125°C−40°C to +125°C

Package Description
14-Terminal LCC
14-Terminal LCC
14-Terminal LCC
14-Terminal LCC
14-Terminal LCC
14-Terminal LCC
14-Terminal LCC

Package
OptionE-14-1
E-14-1
E-14-1
E-14-1
E-14-1
E-14-1
E-14-1

3.3−40°C to +125°C

14-Terminal LCC

E-14-1

3.3−40°C to +125°C

14-Terminal LCC

E-14-1

EVAL-ADXL354BZ
EVAL-ADXL354CZEVAL-ADXL355Z
1

Evaluation Board for ADXL354BEZ
Evaluation Board for ADXL354CEZ
Evaluation Board for ADXL355BEZ

Z = RoHS-Compliant Part.

©2016 Analog Devices, Inc. All rights reserved. Trademarks andregistered trademarks are the property of their respective owners.
D14205-0-9/16(0)Rev. 0 | Page 42 of 42