LT3045-1
20V, 500mA, Ultralow Noise,
Ultrahigh PSRR Linear Regulator with VIOC Control
FEATURESDESCRIPTION

Ultralow RMS Noise: 0.8µVRMS (10Hz to 100kHz)
nn Ultralow Spot Noise: 2nV/√Hz at 10kHz
nn Ultrahigh PSRR: 76dB at 1MHz
nn Output Current: 500mA
nn Wide Input Voltage Range: 1.8V to 20V
nn Single Capacitor Improves Noise and PSRR
nn 100µA SET Pin Current: ±1% Initial Accuracy
nn VIOC Pin Controls Upstream Regulator to Minimize
Power Dissipation
nn Single Resistor Programs Output Voltage
nn Programmable Current Limit
nn Low Dropout Voltage: 260mV
nn Output Voltage Range: 0V to 15V
nn Programmable Power Goodnn Fast Start-Up Capability
nn Precision Enable/UVLO
nn Parallelable for Lower Noise and Higher Current
nn Internal Current Limit with Foldback
nn Minimum Output Capacitor: 10µF Ceramic
nn Reverse-Battery and Reverse-Current Protection
nn 12-Lead MSOP and 3mm × 3mm DFN Packages

The LT®3045-1 is a high performance low dropout linear
regulator featuring LTC’s ultralow noise and ultrahigh PSRR
architecture for powering noise sensitive applications. Designed as a precision current reference followed by a highperformance voltage buffer, the LT3045-1 can be easily
paralleled to further reduce noise, increase output current
and spread heat on the PCB. In addition to the LT3045
feature set, the LT3045-1 incorporates a VIOC tracking
function to control an upstream switching converter tomaintain a constant voltage across the LT3045-1 andhence minimize power dissipation.

APPLICATIONSThe LT3045-1 is stable with a minimum 10µF ceramic
output capacitor. Built-in protection includes reversebattery protection, reverse-current protection, internalcurrent limit with foldback and thermal limit with hysteresis.
The LT3045-1 is available in thermally enhanced 12-Lead
MSOP and 3mm × 3mm DFN packages.

nn

The device supplies 500mA at a typical 260mV dropout
voltage. Operating quiescent current is nominally 2.3mA
and drops to <<1µA in shutdown. The LT3045-1’s wide
output voltage range (0V to 15V) while maintaining unitygain operation provides virtually constant output noise,
PSRR, bandwidth and load regulation, independent of the
programmed output voltage. Additionally, the regulator
features programmable current limit, fast start-up capability and programmable power good to indicate output
voltage regulation.

RF Power Supplies: PLLs, VCOs, Mixers, LNAs, PAs
Very Low Noise Instrumentation
nn High Speed/High Precision Data Converters
nn Medical Applications: Imaging, Diagnostics
nn Post-Regulator for Switching Suppliesnn
nn

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Analog
Devices, Inc. Patents pending. All other trademarks are the property of their respective owners.

TYPICAL APPLICATION
IN

10nF

40.2k

LT8608
BST

EN/UV

SW

TR/SS

PG

0.22µF

100µA

–
+

PGFB
2.21k

FB

INTVCC GND

EN/UV

7.68k

VLDOIN – VLDOUT = 1V

OUT
OUTS

VIOC
SET

GND ILIMPG

VOUT: VARIABLE
IOUT(MAX): 500mA

4.7µF

10

1

10µF
30451 TA01a

1µF
fSW = 1MHz
L: XFL4020-222MECLDOIN = 4.3V
LDOOUT = 3.3V
100 ILOAD = 500mA

LT3045-1

IN
47µF

MODE
RT

2.2µH

NOISE (µV/√Hz)

VIN
12V

Noise Spectral Density
1000

249Ω

0.1

0.01

LDOOUT
LDOIN
Noise Floor
10

100

1k
10k 100k
FREQUENCY (Hz)

1M

10M

30451 TA01b

30451fa

For more information www.linear.com/LT3045-1

1

LT3045-1
ABSOLUTE MAXIMUM RATINGS (Note 1)
IN Pin Voltage..........................................................±22V
VIOC Pin Voltage (Note 10)...............................–0.3V, 4V
EN/UV Pin Voltage...................................................±22V
IN-to-EN/UV Differential..........................................±22V
PG Pin Voltage (Note 10)................................–0.3V, 22V
ILIM Pin Voltage (Note 10)................................–0.3V, 1V
PGFB Pin Voltage (Note 10)............................–0.3V, 22V
SET Pin Voltage (Note 10)...............................–0.3V, 16V
SET Pin Current (Note 7)..................................... ±20mA
OUTS Pin Voltage (Note 10)............................–0.3V, 16V
OUTS Pin Current (Note 7).................................. ±20mA

OUT Pin Voltage (Note 10)..............................–0.3V, 16V
OUT-to-OUTS Differential (Note 14)........................ ±1.2V
IN-to-OUT Differential..............................................±22V
IN-to-OUTS Differential............................................±22V
Output Short-Circuit Duration........................... Indefinite
Operating Junction Temperature Range (Note 9)
E-Grade, I-Grade................................ –40°C to 125°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature (Soldering, 10 Sec)MSE Package .................................................... 300°C

PIN CONFIGURATIONTOP VIEWTOP VIEWIN

1

12 OUTIN

2

11 OUT

VIOC

3

EN/UV

4

PG

5

ILIM

6

13
GND

IN 1
IN 2
VIOC 3
EN/UV 4PG 5ILIM 6

10 OUTS
9 GND
8 SET
7 PGFB

DD PACKAGE
12-LEAD (3mm × 3mm) PLASTIC DFNTJMAX = 150°C, θJA = 34°C/W, θJC = 5.5°C/W
EXPOSED PAD (PIN 13) IS GND, MUST BE SOLDERED TO PCB

13GND

12 OUT
11 OUT
10 OUTS
9 GND
8 SET
7 PGFBMSE PACKAGE
12-LEAD PLASTIC MSOPTJMAX = 150°C, θJA = 33°C/W, θJC = 8°C/W
EXPOSED PAD (PIN 13) IS GND, MUST BE SOLDERED TO PCBORDER INFORMATION http://www.linear.com/product/LT3045-1#orderinfo
LEAD FREE FINISH

TAPE AND REELPART MARKING*PACKAGE DESCRIPTIONTEMPERATURE RANGE

LT3045EDD-1#PBF

LT3045EDD-1#TRPBF

LHBR

12-Lead (3mm × 3mm) Plastic DFN–40°C to 125°C

LT3045IDD-1#PBF

LT3045IDD-1#TRPBF

LHBR

12-Lead (3mm × 3mm) Plastic DFN–40°C to 125°C

LT3045EMSE-1#PBF

LT3045EMSE-1#TRPBF

30451

12-Lead Plastic MSOP

–40°C to 125°C

LT3045IMSE-1#PBF

LT3045IMSE-1#TRPBF

30451

12-Lead Plastic MSOP

–40°C to 125°C

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels throughdesignated sales channels with #TRMPBF suffix.

LT3045 Options
PART NUMBER

VIOC FUNCTION

LT3045-1

Yes

LT3045No

230451fa

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LT3045-1
ELECTRICAL CHARACTERISTICS

The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.
PARAMETERCONDITIONSMINInput Voltage Rangel

Minimum IN Pin Voltage ILOAD = 500mA, VIN UVLO Rising
VIN UVLO Hysteresis(Note 2)

l

2
1.78
75

Output Voltage Range

VIN > VOUTl0

SET Pin Current (ISET)

VIN = 2V, ILOAD = 1mA, VOUT = 1.3V
2V < VIN < 20V, 0V < VOUT < 15V, 1mA < ILOAD < 500mA (Note 3)

l

99
98

Fast Start-Up Set Pin
Current

VPGFB = 289mV, VIN = 2.8V, VSET = 1.3V

Output Offset Voltage
VOS (VOUT – VSET)(Note 4)

VIN = 2V, ILOAD = 1mA, VOUT = 1.3V
2V < VIN < 20V, 0V < VOUT < 15V, 1mA < ILOAD < 500mA (Note 3)lLine Regulation: ∆ISET
Line Regulation: ∆VOS

VIN = 2V to 20V, ILOAD = 1mA, VOUT = 1.3V
VIN = 2V to 20V, ILOAD = 1mA, VOUT = 1.3V (Note 4)llLoad Regulation: ∆ISET
Load Regulation: ∆VOS

ILOAD = 1mA to 500mA, VIN = 2V, VOUT = 1.3V
ILOAD = 1mA to 500mA, VIN = 2V, VOUT = 1.3V (Note 4)

Change in ISET with VSET
Change in VOS with VSET
Change in ISET with VSET
Change in VOS with VSETVSET = 1.3V to 15V, VIN = 20V, ILOAD = 1mA
VSET = 1.3V to 15V, VIN = 20V, ILOAD = 1mA (Note 4)
VSET = 0V to 1.3V, VIN = 20V, ILOAD = 1mA
VSET = 0V to 1.3V, VIN = 20V, ILOAD = 1mA (Note 4)

Dropout Voltage(Note 5)ILOAD = 1mA, 50mA

TYP

100
100

MAX

UNITS

20

V

2

V
mV

15

V

101
102

µA
µA

2
–1
–2

mA
1
2

mV
mV

0.5
0.5

±2
±3

nA/V
µV/V

l

3
0.1

0.5

nA
mV

l
l
l
l

30
0.03
150
0.3

400
0.6
600
2

nA
mV
nA
mV

220

275
330

mV
mV

220

280
350

mV
mV

260

350
450

mV
mV

4
5.5
7
25

mA
mA
mA
mA
mA

l

ILOAD = 300mAl

ILOAD = 500mAl

GND Pin Current
VIN = VOUT(NOMINAL)(Note 6)ILOAD = 10µA
ILOAD = 1mA
ILOAD = 50mA
ILOAD = 100mA
ILOAD = 500mA

2.2
2.4
3.5
4.3
15

Output Noise Spectral
Density (Notes 4, 8)

ILOAD = 500mA, Frequency = 10Hz, COUT = 10µF, CSET = 0.47µF, VOUT = 3.3V
ILOAD = 500mA, Frequency = 10Hz, COUT = 10µF, CSET = 4.7µF, 1.3V ≤ VOUT ≤ 15V
ILOAD = 500mA, Frequency = 10kHz, COUT = 10µF, CSET = 0.47µF, 1.3V ≤ VOUT ≤ 15V
ILOAD = 500mA, Frequency = 10kHz, COUT = 10µF, CSET = 0.47µF, 0V ≤ VOUT < 1.3V

500
70
2
5

nV/√HznV/√HznV/√HznV/√HzOutput RMS Noise(Notes 4, 8)

ILOAD = 500mA, BW = 10Hz to 100kHz, COUT = 10µF, CSET = 0.47µF, VOUT = 3.3V
ILOAD = 500mA, BW = 10Hz to 100kHz, COUT = 10µF, CSET = 4.7µF, 1.3V ≤ VOUT ≤ 15V
ILOAD = 500mA, BW = 10Hz to 100kHz, COUT = 10µF, CSET = 4.7µF, 0V ≤ VOUT < 1.3V

2.5
0.8
1.8

µVRMS
µVRMS
µVRMS

Reference Current RMS BW = 10Hz to 100kHz
Output Noise (Notes 4, 8)

6

nARMS

Ripple Rejection
1.3V ≤ VOUT ≤ 15V
VIN – VOUT = 2V (Avg)(Notes 4, 8)

VRIPPLE = 500mVP-P, fRIPPLE = 120Hz, ILOAD = 500mA, COUT = 10µF, CSET = 4.7µF
VRIPPLE = 150mVP-P, fRIPPLE = 10kHz, ILOAD = 500mA, COUT = 10µF, CSET = 0.47µF
VRIPPLE = 150mVP-P, fRIPPLE = 100kHz, ILOAD = 500mA, COUT = 10µF, CSET = 0.47µF
VRIPPLE = 150mVP-P, fRIPPLE = 1MHz, ILOAD = 500mA, COUT = 10µF, CSET = 0.47µF
VRIPPLE = 80mVP-P, fRIPPLE = 10MHz, ILOAD = 500mA, COUT = 10µF, CSET = 0.47µF

117
90
77
76
53

dB
dB
dB
dB
dB

Ripple Rejection
0V ≤ VOUT < 1.3V
VIN – VOUT = 2V (Avg)(Notes 4, 8)

VRIPPLE = 500mVP-P, fRIPPLE = 120Hz, ILOAD = 500mA, COUT = 10µF, CSET = 0.47µF
VRIPPLE = 50mVP-P, fRIPPLE = 10kHz, ILOAD = 500mA, COUT = 10µF, CSET = 0.47µF
VRIPPLE = 50mVP-P, fRIPPLE = 100kHz, ILOAD = 500mA, COUT = 10µF, CSET = 0.47µF
VRIPPLE = 50mVP-P, fRIPPLE = 1MHz, ILOAD = 500mA, COUT = 10µF, CSET = 0.47µF
VRIPPLE = 50mVP-P, fRIPPLE = 10MHz, ILOAD = 500mA, COUT = 10µF, CSET = 0.47µF

104
85
72
64
54

dB
dB
dB
dB
dB

EN/UV Pin Threshold

EN/UV Trip Point Rising (Turn-On), VIN = 2V

EN/UV Pin Hysteresis

EN/UV Trip Point Hysteresis, VIN = 2V

l
l
l
l

l

1.18

1.24
130

1.32

V
mV
30451fa

For more information www.linear.com/LT3045-1

3

LT3045-1
ELECTRICAL CHARACTERISTICS

The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.
PARAMETERCONDITIONSEN/UV Pin Current

VEN/UV = 0V, VIN = 20V
VEN/UV = 1.24V, VIN = 20V
VEN/UV = 20V, VIN = 0V

MIN

MAX

UNITS

±1
15

µA
µA
µA

0.3

1
10

µA
µA

850
430

mA
mA
mA

0.03
8

l

Quiescent Current in
VIN = 6V
Shutdown (VEN/UV = 0V)
Internal Current Limit(Note 12)

TYP

l

l

VIN = 2V, VOUT = 0V
VIN = 12V, VOUT = 0V
VIN = 20V, VOUT = 0V

l

570

l

230

710
700
330

Programmable
Current Limit

Programming Scale Factor: 2V < VIN < 20V (Note 11)
VIN = 2V, VOUT = 0V, RILIM = 300Ω
VIN = 2V, VOUT = 0V, RILIM = 1.5kΩ

l
l

450
90

150
500
100

550
110

mA • kΩmA
mA

PGFB Trip PointPGFB Trip Point Rising

l

291

300

309

mV

PGFB Hysteresis

PGFB Trip Point Hysteresis

7

PGFB Pin Current

VIN = 2V, VPGFB = 300mVPG Output Low Voltage

IPG = 100µAl

PG Leakage Current

VPG = 20Vl

Reverse Input Current

VIN = –20V, VEN/UV = 0V, VOUT = 0V, VSET = 0Vl

Reverse Output Current

VIN = 0, VOUT = 5V, SET = Open

mV

25
30

14

Minimum Load Required VOUT < 1V
(Note 13)

l

nA
100

mV

1

µA

100

µA

25

µA

10

µA

Thermal Shutdown

TJ Rising
Hysteresis

165
8

°C
°C

Start-Up Time

VOUT(NOM) = 5V, ILOAD = 500mA, CSET = 0.47µF, VIN = 6V, VPGFB = 6V
VOUT(NOM) = 5V, ILOAD = 500mA, CSET = 4.7µF, VIN = 6V, VPGFB = 6V
VOUT(NOM) = 5V, ILOAD = 500mA, CSET = 4.7µF, VIN = 6V, RPG1 = 50kΩ,RPG2 = 700kΩ (with Fast Start-Up to 90% of VOUT)

55
550
10

ms
ms
ms

Thermal Regulation

10ms Pulse

–0.01

%/W

1

V/V

VIOC Amplifier Gain
Input-to-Output
Differential Voltage
VIOC Pin Voltage Range: VOUT > VVIOC + 0.5V
Control (VIOC) (Note 15)
VIOC Pin Voltage: VOUT ≤ 1.5V, VIN = 2.5V

1

4
1

VIOC Pin Source Currentl

VIOC Pin Sink Current: VIN ≥ 2.5VlNote 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The EN/UV pin threshold must be met to ensure device operation.
Note 3: Maximum junction temperature limits operating conditions. The
regulated output voltage specification does not apply for all possiblecombinations of input voltage and output current, especially due to theinternal current limit foldback which starts to decrease current limit at
VIN – VOUT > 12V. If operating at maximum output current, limit the input
voltage range. If operating at the maximum input voltage, limit the output
current range.

4

l

V
V

200

µA
15

µA

Note 4: OUTS ties directly to OUT.
Note 5: Dropout voltage is the minimum input-to-output differential
voltage needed to maintain regulation at a specified output current. The
dropout voltage is measured when output is 1% out of regulation. Thisdefinition results in a higher dropout voltage compared to hard dropout —which is measured when VIN = VOUT(NOMINAL). For lower output voltages,
below 1.5V, dropout voltage is limited by the minimum input voltage
specification. Please consult the Typical Performance Characteristics
for curves of dropout voltage as a function of output load current andtemperature measured in a typical application circuit.

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LT3045-1
ELECTRICAL CHARACTERISTICS
Note 6: GND pin current is tested with VIN = VOUT(NOMINAL) and a current
source load. Therefore, the device is tested while operating in dropout. Thisis the worst-case GND pin current. GND pin current decreases at higher
input voltages. Note that GND pin current does not include SET pin or ILIM
pin current but Quiescent current does include them.
Note 7: SET and OUTS pins are clamped using diodes and two 25Ω series
resistors. For less than 5ms transients, this clamp circuitry can carry
more than the rated current. Refer to Applications Information for more
information.
Note 8: Adding a capacitor across the SET pin resistor decreases output
voltage noise. Adding this capacitor bypasses the SET pin resistor’s
thermal noise as well as the reference current’s noise. The output noise
then equals the error amplifier noise. Use of a SET pin bypass capacitor
also increases start-up time.
Note 9: The LT3045-1 is tested and specified under pulsed load conditions
such that TJ ≈ TA. The LT3045-1E is 100% tested at 25°C and performanceis guaranteed from 0°C to 125°C. Specifications over the –40°C to 125°C
operating temperature range are assured by design, characterization, andcorrelation with statistical process controls. The LT3045-1I is guaranteed
over the full –40°C to 125°C operating temperature range. High junction

temperatures degrade operating lifetimes. Operating lifetime is derated atjunction temperatures greater than 125°C.
Note 10: Parasitic diodes exist internally between the VIOC, ILIM, PG,
PGFB, SET, OUTS, and OUT pins and the GND pin. Do not drive these pins
more than 0.3V below the GND pin during a fault condition. These pins
must remain at a voltage more positive than GND during normal operation.
Note 11: The current limit programming scale factor is specified while theinternal backup current limit is not active. Note that the internal current
limit has foldback protection for VIN – VOUT differentials greater than 12V.
Note 12: The internal back-up current limit circuitry incorporates foldback
protection that decreases current limit for VIN – VOUT > 12V. Some level of
output current is provided at all VIN – VOUT differential voltages. Consult the
Typical Performance Characteristics graph for current limit vs VIN – VOUT.
Note 13: For output voltages less than 1V, the LT3045-1 requires a 10µA
minimum load current for stability.
Note 14: Maximum OUT-to-OUTS differential is guaranteed by design.
Note 15: The VIOC buffer outputs a voltage equal to VIN – VOUT or
VIN – 1.5V (for VOUT ≤ 1.5V). See Block Diagram and Applications
Information for further information. The VIOC pin’s source current should
be set between 10µA and 200µA.

30451fa

For more information www.linear.com/LT3045-1

5

LT3045-1
TYPICAL PERFORMANCE CHARACTERISTICS TJ = 25°C, unless otherwise noted.
SET Pin Current
101.0

100.4
100.2
100.0
99.8
99.6
99.4

98

0 25 50 75 100 125 150
TEMPERATURE (°C)

99
100
101
ISET DISTRIBUTION (µA)

1.0
0.5
0
–0.5
–1.0

30451 G01

Offset Voltage

30451 G02

SET Pin Current

Offset Voltage (VOUT – VSET)
2.0

SET PIN CURRENT (µA)

IL = 1mA
100.8 VOUT = 1.3V
100.6

150°C
125°C
25°C
–55°C

100.4
100.2
100.0
99.8
99.6
99.4

99.0

2

2.0

100.0
99.8
99.6
99.4

6 8 10 12 14 16 18 20
INPUT VOLTAGE (V)30451 G07

IL = 1mA
VIN = 20V

–1.0

–2.0

0

2

4

6 8 10 12 14 16 18 20
INPUT VOLTAGE (V)30451 G06

0.20

20

V = 2.5V
18 ∆IIN= 1mA to 500mA
L
16 VOUT = 1.3V

150°C
125°C
25°C
–55°C

–0.5

0.18
0.16

14

0.14

12

0.12

10

0.10

VOS

8

0.08
0.06

6

–1.0

–2.0

4.5 6 7.5 9 10.5 12 13.5 15
OUTPUT VOLTAGE (V)–0.5

Load Regulation

0

99.0

3

4

0.5

–1.5
1.5

2

1.0

99.2
0

0

4

0.04

ISET

0.02

2
0

1.5

3

4.5 6 7.5 9 10.5 12 13.5 15
OUTPUT VOLTAGE (V)30451 G08

0–75 –50 –25∆ VOS (mV)

100.2

0.5

∆ISET (nA)

100.4

1.0

Offset Voltage (VOUT – VSET)

1.5
OFFSET VOLTAGE (mV)

100.6

150°C
125°C
25°C
–55°C

150°C
125°C
25°C
–55°C

30451 G05

SET Pin Current
IL = 1mA
VIN = 20V

030451 G04

101.0
100.8

IL = 1mA
VOUT = 1.3V

1.5

–1.5

99.2
–1
0
1
VOS DISTRIBUTION (mV)

0 25 50 75 100 125 150
TEMPERATURE (°C)
30451 G03

101.0

N = 3250–2–2.0–75 –50 –25

102

OFFSET VOLTAGE (mV)

99.0
–75 –50 –25

SET PIN CURRENT (µA)

VIN = 2V
IL = 1mA
VOUT = 1.3V

–1.5

99.2

6

Offset Voltage (VOUT – VSET)

1.5
OFFSET VOLTAGE (mV)

100.6

2.0

N = 3250

VIN = 2V
IL = 1mA
VOUT = 1.3V

100.8
SET PIN CURRENT (µA)

SET Pin Current

0
0 25 50 75 100 125 150
TEMPERATURE (°C)
30451 G09

30451fa

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LT3045-1
TYPICAL PERFORMANCE CHARACTERISTICS TJ = 25°C, unless otherwise noted.

VIN = 2V
VEN/UV = VIN
IL = 10µA
RSET = 13k

3.0
2.5
2.0
1.5
1.0
0.5

Quiescent Current
4.0

VEN/UV = 0V

45
QUIESCENT CURRENT (µA)

3.5

40
35
30
VIN = 20V

25
20

VIN = 2V

15
10

0
–75 –50 –25

0 25 50 75 100 125 150
TEMPERATURE (°C)

2.0
1.5
150°C
125°C
25°C
–55°C
0

1

4

300
250
200
150

150°C
125°C
25°C
–55°C

100

0

5

0

VIN = 5V
RSET = 33.2k

18
IL = 500mA

12
10
8
6
4
2
0
–75 –50 –25

IL = 300mA
IL = 100mA

300

30451 G16

IL = 1mA

200
150
100

0
–75 –50 –25

50 100 150 200 250 300 350 400 450 500
OUTPUT CURRENT (mA)

0 25 50 75 100 125 150
TEMPERATURE (°C)
30451 G15

GND Pin Current
18

12
10
8
6

0

150°C
125°C
25°C
–55°C
0

RSET = 33.2k

16

14

2

0 25 50 75 100 125 150
TEMPERATURE (°C)

IL = 500mA

250

50

16

4

IL = 1mA

IL = 400mA

350

VIN = 4.3V
RSET = 33.2k

20
GND PIN CURRENT (mA)

GND PIN CURRENT (mA)

14

400

GND Pin Current
22

16

6 8 10 12 14 16 18 20
INPUT VOLTAGE (V)30451 G14

GND Pin Current
18

4

RSET = 33.2k

450

350

30451 G1320

2

Dropout Voltage
500

400

50

2
3
OUTPUT VOLTAGE (V)030451 G12DROPOUT VOLTAGE (mV)DROPOUT VOLTAGE (mV)QUIESCENT CURRENT (mA)

2.5

0

0

RSET = 33.2k

450

3.0

0.5

1.0

Typical Dropout Voltage
500

VIN = 6V
VEN/UV = VIN
IL = 10µA

1.0

1.5

30451 G11

Quiescent Current
3.5

2.0

0 25 50 75 100 125 150
TEMPERATURE (°C)

30451 G10

4.0

2.5

0.5

5

0
–75 –50 –25

VEN/UV = VIN
3.5 IL = 10µA
RSET = 33.2kΩ
3.0 IVIOC = 10µA

50 100 150 200 250 300 350 400 450 500
OUTPUT CURRENT (mA)
30451 G17

GND PIN CURRENT (mA)QUIESCENT CURRENT (mA)

Quiescent Current
50

QUIESCENT CURRENT (mA)

Quiescent Current
4.0

14

RL = 6.6Ω

12
10

RL = 11Ω

8
6

RL = 33Ω

4

RL = 330Ω

20

RL = 3.3kΩ
01

2

3 4 5 6 7
INPUT VOLTAGE (V)

8

9

10

30451 G1830451fa

For more information www.linear.com/LT3045-1

7

LT3045-1
TYPICAL PERFORMANCE CHARACTERISTICS TJ = 25°C, unless otherwise noted.
EN/UV Turn-On Threshold

1.75

1.30

1.50
1.25
1.00
0.75
0.50

0
–75 –50 –25

185

1.28
1.26
1.24

VIN = 2V

1.22

VIN = 10V

1.20

RISING UVLOFALLING UVLO

0.25

1.18
–75 –50 –25

0 25 50 75 100 125 150
TEMPERATURE (°C)

EN/UV PIN CURRENT (µA)

EN/UV PIN CURRENT (µA)

3.5
3.0
2.5
2.0
150°C
125°C
25°C
–55°C

0.5
0

2

4

6 8 10 12 14 16 18 20
ENABLE PIN VOLTAGE (V)

8
7
6
5

VIN = 20V

4
3
2

–20
–30
–40
–50
–60
–70

–90

–100
–20 –18 –16 –14 –12 –10 –8 –6 –4 –2
ENABLE PIN VOLTAGE (V)

900

0

2

4

6 8 10 12 14 16 18 20
ENABLE PIN VOLTAGE (V)Internal Current Limit
600

RILIM = 0Ω
VOUT = 0V

500
CURRENT LIMIT (mA)

700
600
500
400
300
200
100

0
–20 –18 –16 –14 –12 –10 –8 –6 –4 –2
ENABLE PIN VOLTAGE (V)030451 G25

VIN = 20V
RILIM = 0Ω
VOUT = 0V

400
300
200
100

VIN = 2.5V
VIN = 12V

0–75 –50 –25

030451 G24

800

0.1

150°C
125°C
25°C
–55°C

–80

Internal Current Limit

0.2

VIN = 2V

01000

CURRENT LIMIT (mA)

INPUT CURRENT (µA)–101Input Pin Current
150°C
125°C
25°C
–55°C

0 25 50 75 100 125 150
TEMPERATURE (°C)

30451 G23

0.3

8

80

Negative Enable Pin Current
VIN = 2V

30451 G22

VIN = 2V

VIN = 2V

95

0

9

4.5

1.0

110

30451 G21

EN/UV PIN CURRENT (µA)

VIN = 20V

1.5

125

EN/UV Pin Current

4.0

VIN = 10V

140

50
–75 –50 –25

0 25 50 75 100 125 150
TEMPERATURE (°C)

10

5.0

155

30451 G20

EN/UV Pin Current
5.5

170

65

30451 G19

0EN/UV Pin Hysteresis
200

EN/UV PIN HYSTERESIS (mV)

1.32

TURN-ON THRESHOLD (V)INPUT UVLO THRESHOLD (V)Minimum Input Voltage
2.00

0 25 50 75 100 125 150
TEMPERATURE (°C)
30451 G26

0–75 –50 –25

0 25 50 75 100 125 150
TEMPERATURE (°C)
30451 G27

30451fa

For more information www.linear.com/LT3045-1

LT3045-1
TYPICAL PERFORMANCE CHARACTERISTICS TJ = 25°C, unless otherwise noted.
Internal Current Limit

Programmable Current Limit

1000

900
800
CURRENT LIMIT (mA)

CURRENT LIMIT (mA)

800
700
600
500
400
300

150°C
125°C
25°C
–55°C

200
100
0

RILIM = 300Ω
VOUT = 0V

600
500
400
300

100

VIN = 2.5V
VIN = 12V

0–75 –50 –25

2 4 6 8 10 12 14 16 18 20
INPUT-TO-OUTPUT DIFFERENTIAL (V)

400
300
200

2.5VIN
5VIN
10VIN

100

0
–75 –50 –25

30451 G30

PGFB Hysteresis

VIN = 2V

7

304
302
300
298
296
294

5
4
3
2
1

290
–75 –50 –25

0–75 –50 –25

0 25 50 75 100 125 150
TEMPERATURE (°C)

0 25 50 75 100 125 150
TEMPERATURE (°C)
30451 G33

30451 G32

ISET During Start-Up with Fast
Start-Up Enabled

100
VIN = 2VVPGFB = 290mV
IPG = 100µA

90
80
70

30

60

IPG (nA)35

3.0
VPG = 2VVPGFB = 310mV

2.5

50
40

15

30

10

20

5

10
0
–75 –50 –25

VIN = 2.5V
VPGFB = 290mV
VSET = 1.3V

2.0
ISET (mA)

50

30451 G34

VIN = 2V

6

PG Pin Leakage Current

0 25 50 75 100 125 150
TEMPERATURE (°C)

0 25 50 75 100 125 150
TEMPERATURE (°C)

8306

PG Output Low Voltage

VPG (mV)

60

0 25 50 75 100 125 150
TEMPERATURE (°C)

30451 G31

20

VIN = 12V20

292

50 100 150 200 250 300 350 400 450 500
OUTPUT CURRENT (mA)25

VIN = 2.5V

80

PGFB HYSTERESIS (mV)ILIM PIN CURRENT (uA)500

PGFB RISING THRESHOLD (mV)

308

600

0
–75 –50 –25

100

PGFB Rising Threshold

700

40

120

310

VILIM = 0V
900 RSET = 13k

45

140

30451 G29

ILIM Pin Current

800

RILIM = 1.5k
VOUT = 0V

40

200

1000

0

160

700

30451 G28

0180

CURRENT LIMIT (mA)

RILIM = 0Ω

9000Programmable Current Limit
200

1000

1.5
1.0
0.5

0 25 50 75 100 125 150
TEMPERATURE (°C)
30451 G35

0–75 –50 –25

0 25 50 75 100 125 150
TEMPERATURE (°C)
30451 G36

30451fa

For more information www.linear.com/LT3045-1

9LT3045-1
TYPICAL PERFORMANCE CHARACTERISTICS TJ = 25°C, unless otherwise noted.
Output Overshoot Recovery
Current Sink

3.5

12
VPGFB = 290mV
VSET = 1.3V
OUTPUT SINK CURRENT (mA)

3.0

ISET (mA)

2.5
2.0
1.5
1.0
0.5
0

0

2

6
4
2

VOUT Forced Above VOUT(NOMINAL)

0

5

100

60

20

7 8 9 10 11 12 13 14 15
OUTPUT VOLTAGE (V)1001k
10k 100k
FREQUENCY (Hz)

120

120

100
90

80

100

80
70
60

1k
10k 100k
FREQUENCY (Hz)

1M

10M

20

100
90
80
70
60
50
40

10

100

1k
10k 100k
FREQUENCY (Hz)

100kHz500kHz
1MHz
2MHz

20

VOUT ≥ 1.3V
0.6V < VOUT < 1.3V
VOUT ≤ 0.6V

30

10
1M

10M
30451 G42

30

40

1M

Power Supply Ripple Rejection50
VIN = 5V
RSET = 30.1k
COUT = 10µF
CSET = 0.47µF

30451 G43

1010M

PSRR (dB)

PSRR (dB)

PSRR (dB)

100

10

1M

VIN = VOUT + 2V
IL = 500mA
COUT = 10µF
CSET = 0.47µF

110

20

VIN = 5V
RSET = 30.1k
30 CSET = 0.47µF
IL = 500mA
20
10
100
1k
10k 100k
FREQUENCY (Hz)40

Power Supply Ripple Rejection
as a Function of Error Amplifier
Input Pair

Power Supply Ripple Rejection

40

60
50

VIN = 5V
RSET = 30.1k
COUT = 10µF
IL = 500mA
107030451 G41

140

IL = 500mA
IL = 300mA
IL = 100mA
IL = 50mA
IL = 1mA

100

80

70

COUT = 10µF
COUT = 22µF

110

80

30451 G40

60

Power Supply Ripple Rejection

90

30
6

0 25 50 75 100 125 150
TEMPERATURE (°C)
30451 G39

90

40

5

2

30451 G38CSET = 4.7µF
CSET = 0.47µF

50

4

3

120

110

2

0

4

Power Supply Ripple Rejection

PSRR (dB)

CURRENT (mA)450
–75 –50 –25

20

120

IIN WHEN VEN = 0V
IOUT WHEN VEN = 0V
IIN WHEN VEN = VIN
IOUT WHEN VEN = VIN

6

10
15
VOUT – VSET (mV)

PSRR (dB)

VIN = 5V
RSET = 33.2k

VIN = 5V
RSET = 33.2k
VOUT – VSET > 5mV

6130451 G37

8

150°C
125°C
25°C
–55°C

8

0

4 6 8 10 12 14 16 18 20
VIN-TO-VSET DIFFERENTIAL (V)7

VIN = 5V
RSET = 33.2k

10Output Overshoot Recovery
Current Sink

OUTPUT SINK CURRENT (mA)

ISET During Start-Up with Fast
Start-Up Enabled

10M

30451 G4400

IL = 500mA
RSET = 30.1k
COUT = 10µF
CSET = 0.47µF

12
3
4
INPUT–TO–OUTPUT DIFFERENTIAL (V)530451 G45

30451fa

For more information www.linear.com/LT3045-1

LT3045-1
TYPICAL PERFORMANCE CHARACTERISTICS TJ = 25°C, unless otherwise noted.
Integrated RMS Output Noise(10Hz to 100kHz)

Integrated RMS Output Noise(10Hz to 100kHz)RMS OUTPUT NOISE (µVRMS)

1.0
0.8
0.6
0.4

7
6
5
4
3
2
1

0.2
0

0.1
1
10
SET PIN CAPACITANCE (µF)

Noise Spectral Density

1.0
0.8
0.6
0.4

CSET = 0.047µF
CSET = 0.47µF
CSET = 1µF
CSET = 4.7µF
CSET = 22µF

10

1M

10M
30451 G49

0

1.5

3

4.5 6 7.5 9 10.5 12 13.5 15
OUTPUT VOLTAGE (V)30451 G48

Noise Spectral Density

OUTPUT NOISE (nV/√Hz)

OUTPUT NOISE (nV/√Hz)

1.2

30451 G47

1000

1 V = 5VIN
RSET = 33.2k
COUT = 10µF
ILOAD = 500mA
0.1
10
100
1k
10k 100k
FREQUENCY (Hz)

1.4

0

100

30451 G46

100

1.6

0.2

0
0.01

50 100 150 200 250 300 350 400 450 500
LOAD CURRENT (mA)

VIN = VOUT + 2V
COUT = 10µF
CSET = 4.7µF
ILOAD = 500mA

1.8

Noise Spectral Density

1000

1000

100

100

10

COUT = 10µF

1 V = 5VIN
RSET = 33.2k
COUT = 22µF
CSET = 4.7µF
ILOAD = 500mA
0.1
10
100
1k
10k 100k
1M
FREQUENCY (Hz)10M

OUTPUT NOISE (nV/√Hz)

RMS OUTPUT NOISE (µVRMS)

VIN = 5V
COUT = 10µF
RSET = 33.2k
ILOAD = 500mA

8

1.2

0

2.0

9

VIN = 5V
RSET = 33.2k
1.6 COUT = 10µF
CSET = 4.7µF
1.4
1.8

RMS OUTPUT NOISE (µVRMS)

2.0

Integrated RMS Output Noise(10Hz to 100kHz)

IL = 500mA
IL = 300mA
IL = 100mA
IL = 10mA
IL = 1mA

10

1 V = 5VIN
RSET = 33.2k
CSET = 4.7µF
COUT = 10µF
0.1
10
100
1k
10k 100k
FREQUENCY (Hz)10M
30451 G51

30451 G50

Noise Spectral Density as
a Function of Error Amplifier
Input Pair

1M

Output Noise: 10Hz to 100kHz

Load Transient Response

OUTPUT NOISE (nV/√Hz)

1000

100

VOUT ≥ 1.3V
0.6V < VOUT < 1.3V
VOUT ≤ 0.6V

OUTPUT
CURRENT
500mA/DIV

5µV/DIV
VIN = 5V
RSET = 33.2k
COUT = 10µF
CSET = 4.7µF
IL = 500mA

10

1 V =VIN
OUT + 2V
IL = 500mA
COUT = 10µF
CSET = 4.7µF
0.1
10
100
1k
10k 100k
FREQUENCY (Hz)OUTPUT
VOLTAGE
20mV/DIV
1ms/DIV

1M

30451 G53

10M
30451 G52

20µs/DIV
VIN = 5V
RSET = 33.2k
COUT = 10µF
CSET = 0.47µF
LOAD STEP = 10mA TO 500mA

30451 G54

30451fa

For more information www.linear.com/LT3045-1

11

LT3045-1
TYPICAL PERFORMANCE CHARACTERISTICS TJ = 25°C, unless otherwise noted.
Start-Up Time with andwithout Fast Start-Up Circuitry forLarge CSET

Line Transient Response

Input Supply Ramp-Up andRamp-Down

500mV/DIVINPUT VOLTAGEOUTPUT WITH
FAST START–UP(SET AT 90%)

INPUT
VOLTAGE
500mV/DIV

2V/DIVOUTPUT
VOLTAGE
1mV/DIVPULSE EN/UVOUTPUT WITHOUT
FAST START–UP

30451 G55

5µs/DIV

VIN = 5V
RSET = 33.2k
COUT = 10µF
CSET = 4.7µF
RL = 6.6Ω

VIN = 4.5V TO 5V
RSET = 33.2k
COUT = 10µF
CSET = 0.47µF
IL = 500mA

VIOC VOLTAGE (V)

1.06
1.04

VIN = 4.3V
VOUT = 3.3V
IOUT = 1mA

1.08
1.06

1.02
1.00
0.98
0.96

1.04
1.02
1.00
0.98
0.96

0.94

0.94

0.92

0.92
0.90

0 25 50 75 100 125 150
TEMPERATURE (°C)

150°C
125°C
25°C
–55°C
0

25

50 75 100 125 150 175 200
VIOC SOURCE CURRENT (µA)

30451 G58

30451 G59

VIOC Sink Current

VIOC SINK CURRENT (µA)

–18
–16
–14

VIOC Voltage
1.10

VIN = 4.3V
VOUT = 3.3V
VVIOC = 2V
IOUT = 1mA

1.06

–12
–10
–8
–6

1.04
1.02
1.00
0.98
0.96

–4

0.94

–2

0.92

0
–75 –50 –25

VIN = 4.3V
VOUT = 3.3V
IVIOC = 100µA

1.08

VIOC VOLTAGE (V)–20

0 25 50 75 100 125 150
TEMPERATURE (°C)

0.90

150°C
125°C
25°C
–55°C
0

50 100 150 200 250 300 350 400 450 500
OUTPUT LOAD CURRENT (mA)

30451 G60

1230451 G57

VIOC Voltage
1.10

VIN = 4.3V
VOUT = 3.3V
IVIOC = 100µA
IOUT = 1mA

0.90–75 –50 –25

50ms/DIV
VIN = 0V TO 5V
VEN/UV = VINRSET = 33.2k
COUT = 10µF
CSET = 0.47µF
RL = 6.6Ω

VIOC VOLTAGE (V)1.08

OUTPUT VOLTAGE

30451 G56

100ms/DIV

VIOC Voltage
1.10

2V/DIV30451 G61

30451fa

For more information www.linear.com/LT3045-1

LT3045-1
PIN FUNCTIONS
IN (Pins 1, 2): Input. These pins supply power to theregulator. The LT3045-1 requires a bypass capacitor at theIN pin. In general, a battery’s output impedance rises withfrequency, so include a bypass capacitor in battery-powered
applications. While a 4.7µF input bypass capacitor generally suffices, applications with large load transients may
require higher input capacitance to prevent input supply
droop. Consult the Applications Information section on theproper use of an input capacitor and its effect on circuit
performance, in particular PSRR. The LT3045-1 withstands
reverse voltages on IN with respect to GND, OUTS and OUT.
In the case of a reversed input, which occurs if a battery
is plugged-in backwards, the LT3045-1 acts as if a diodeis in series with its input. Hence, no reverse-current flows
into the LT3045-1 and no negative voltage appears at theload. The device protects itself and the load.
VIOC (Pin 3): Voltage for Input-to-Output Control. The
LT3045-1 incorporates a tracking function to control theswitching pre-regulator powering the LT3045-1. The VIOC
pin is the output of this tracking function that drives the preregulator’s feedback (FB) pin to maintain the LT3045-1’s
input voltage at VOUT + VVIOC. This function minimizes
power dissipation while maintaining PSRR performance.
See Applications Information section for details.
EN/UV (Pin 4): Enable/UVLO. Pulling the LT3045-1’s EN/
UV pin low places the part in shutdown. Quiescent current
in shutdown drops to less than 1µA and the output voltage turns off. Alternatively, the EN/UV pin can set an input
supply undervoltage lockout (UVLO) threshold using a
resistor divider between IN, EN/UV and GND. The LT3045-1
typically turns on when the EN/UV voltage exceeds 1.24V
on its rising edge, with a 130mV hysteresis on its fallingedge. The EN/UV pin can be driven above the input voltage
and maintain proper functionality. If unused, tie EN/UV to
IN. Do not float the EN/UV pin.
PG (Pin 5): Power Good. PG is an open-collector flag thatindicates output voltage regulation. PG pulls low if PGFB
is below 300mV. If the power good functionality is notneeded, float the PG pin. A parasitic substrate diode exists
between PG and GND pins of the LT3045-1; do not drive
PG more than 0.3V below GND during normal operationor during a fault condition.

ILIM (Pin 6): Current Limit Programming Pin. Connecting a
resistor between ILIM and GND programs the current limit.
For best accuracy, Kelvin connect this resistor directly to
the LT3045-1’s GND pin. The programming scale factor
is nominally 150mA•kΩ. The ILIM pin sources current
proportional (1:500) to output current; therefore, it also
serves as a current monitoring pin with a 0V to 300mV
range. If the programmable current limit functionality is
not needed, tie ILIM to GND. A parasitic substrate diodeexists between ILIM and GND pins of the LT3045-1; do
not drive ILIM more than 0.3V below GND during normal
operation or during a fault condition.
PGFB (Pin 7): Power Good Feedback. The PG pin pulls
high if PGFB increases beyond 300mV on its rising edge,
with 7mV hysteresis on its falling edge. Connecting an
external resistor divider between OUT, PGFB and GND
sets the programmable power good threshold with thefollowing transfer function: 0.3V • (1 + RPG2/RPG1). As
discussed in the Applications Information section, PGFB
also activates the fast start-up circuitry. Tie PGFB to IN
if power good and fast start-up functionalities are notneeded, and if reverse input protection is additionallyrequired, tie the anode of a 1N4148 diode to IN and its
cathode to PGFB. See the Typical Applications section for
details. A parasitic substrate diode exists between PGFB
and GND pins of the LT3045-1; do not drive PGFB morethan 0.3V below GND during normal operation or during
a fault condition.
SET (Pin 8): SET. This pin is the inverting input of the error amplifier and the regulation set-point for the LT30451. SET sources a precision 100µA current that flows
through an external resistor connected between SET and
GND. The LT3045-1’s output voltage is determined by
VSET = ISET • RSET. Output voltage range is from zero to
15V. Adding a capacitor from SET to GND improves noise,
PSRR and transient response at the expense of increased
start-up time. For optimum load regulation, Kelvin connect the ground side of the SET pin resistor directly tothe load. A parasitic substrate diode exists between SET
and GND pins of the LT3045-1; do not drive SET morethan 0.3V below GND during normal operation or during
a fault condition.
30451fa

For more information www.linear.com/LT3045-1

13

LT3045-1
PIN FUNCTIONSGND (Pin 9, Exposed Pad Pin 13): Ground. The exposed
backside is an electrical connection to GND. To ensure
proper electrical and thermal performance, solder the
exposed backside to the PCB ground and tie it directly
to the GND pin.
OUTS (Pin 10): Output Sense. This pin is the noninverting input to the error amplifier. For optimal transient
performance and load regulation, Kelvin connect OUTS
directly to the output capacitor and the load. Also, tie the
GND connections of the output capacitor and the SET pin
capacitor directly together. A parasitic substrate diodeexists between OUTS and GND pins of the LT3045-1; do
not drive OUTS more than 0.3V below GND during normal
operation or during a fault condition.

14

OUT (Pins 11, 12): Output. These pins supply power to theload. For stability, use a minimum 10µF output capacitor
with an ESR below 20mΩ and an ESL below 2nH. Largeload transients require larger output capacitance to limit
peak voltage transients. Refer to the Applications Information section for more information on output capacitance. A
parasitic substrate diode exists between OUT and GND pinsof the LT3045-1; do not drive OUT more than 0.3V below
GND during normal operation or during a fault condition.

30451fa

For more information www.linear.com/LT3045-1

V

V

–

+

–

+

300mV

1.24V

7

BIAS

For more information www.linear.com/LT3045-1

RPG1

RPG2

PGFB

+
–

PROGRAMMABLE
POWER GOOD+–

ENABLE
COMPARATOR

2mA

5
RPG

PG

FAST START-UP
DISABLE LOGIC

AV = 1

VIOC

– – +

1.5V

INPUT-TOOUTPUT
CONTROL

3

GND
9, 13

INPUT UVLOCURRENT LIMITTHERMAL SHDNDROPOUTFAST START-UP

CURRENTREFERENCE

8
RSET

SET

CSET

SET-TO-OUTS
PROTECTION
CLAMP

INPUT
UVLO

THERMAL
SHDN

100µA

OUTS
10

V

ERROR
AMPLIFIER

–

–

300mV

V

–

+
300mV

PROGRAMMABLE
CURRENT LIMITV+INTERNAL CURRENT
LIMIT

1.5V

+
–
+

OUTPUT OVERSHOOTRECOVERY

DRIVER

–
+

EN/UV

–
+

+
–

4

6

215Ω

QC

OUT

QPWR

11, 12

RILIM

ILIM

QP

IN
1, 2

VIN

30451 BD

COUT

CIN

VOUT
RL

LT3045-1

BLOCK DIAGRAM

30451fa15

LT3045-1
APPLICATIONS INFORMATIONThe LT3045-1 is a high performance low dropout linear
regulator featuring LTC’s ultralow noise (2nV/√Hz at
10kHz) and ultrahigh PSRR (76dB at 1MHz) architecture
for powering noise sensitive applications. Designed as aprecision current source followed by a high performance
rail-to-rail voltage buffer, the LT3045-1 can be easily paralleled to further reduce noise, increase output current andspread heat on the PCB. The device additionally features
programmable current limit, fast start-up capability andprogrammable power good.
The LT3045-1 is easy to use and incorporates all of theprotection features expected in high performance regulators. Included are short-circuit protection, safe operatingarea protection, reverse-battery protection, reverse-current
protection, and thermal shutdown with hysteresis.
In addition to the LT3045 feature set, the LT3045-1 incorporates a VIOC tracking function to control an upstream
switching converter to maintain a constant voltage acrossthe LT3045-1 and hence minimize power dissipation.
Output Voltage
The LT3045-1 incorporates a precision 100µA current
source flowing out of the SET pin, which also ties to theerror amplifier’s inverting input. Figure 1 illustrates thatconnecting a resistor from SET to ground generates a reference voltage for the error amplifier. This reference voltage
is simply the product of the SET pin current and the SET
pin resistor. The error amplifier’s unity-gain configuration
produces a low impedance version of this voltage on its
noninverting input, i.e. the OUTS pin, which is externallytied to the OUT pin.
VIN
5V ±5%
4.7µF

LT3045-1

IN
100µA

–
+

EN/UV

OUT

PGFB

VOUT, 3.3V
IOUT(MAX), 500mA

OUTS
VIOC

SET

GND ILIM

10µF

PG
30451 F01

0.47µF

33.2k

Figure 1. Basic Adjustable Regulator

16

The LT3045-1’s rail-to-rail error amplifier and current
reference allows for a wide output voltage range from 0V(using a 0Ω resistor) to VIN minus dropout — up to 15V.
A PNP-based input pair is active for 0V to 0.6V output
and an NPN-based input pair is active for output voltages greater than 1.3V, with a smooth transition between
the two input pairs from 0.6V to 1.3V output. While the
NPN-based input pair is designed to offer the best overall
performance, refer to the Electrical Characteristics Table fordetails on offset voltage, SET pin current, output noise and
PSRR variation with the error amp input pair. Table 1 lists
many common output voltages and their corresponding
1% RSET resistors.
Table 1. 1% Resistor for Common Output Voltages
VOUT (V)RSET (kΩ)

2.5

24.9

3.3

33.2

5

49.9

12

121

15

150

The benefit of using a current reference compared with avoltage reference as used in conventional regulators is thatthe regulator always operates in unity gain configuration,
independent of the programmed output voltage. This allows the LT3045-1 to have loop gain, frequency response
and bandwidth independent of the output voltage. As aresult, noise, PSRR and transient performance do notchange with output voltage. Moreover, since none of theerror amp gain is needed to amplify the SET pin voltage
to a higher output voltage, output load regulation is more
tightly specified in the hundreds of microvolts range andnot as a fixed percentage of the output voltage.
Since the zero TC current source is highly accurate, theSET pin resistor can become the limiting factor in achieving high accuracy. Hence, it should be a precision resistor.
Additionally, any leakage paths to or from the SET pin
create errors in the output voltage. If necessary, use highquality insulation (e.g., Teflon, Kel-F); moreover, cleaning of all insulating surfaces to remove fluxes and otherresidues may be required. High humidity environments
may require a surface coating at the SET pin to providea moisture barrier.
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LT3045-1
APPLICATIONS INFORMATION
Minimize board leakage by encircling the SET pin with aguard ring operated at a potential close to itself — ideallytied to the OUT pin. Guarding both sides of the circuitboard is recommended. Bulk leakage reduction depends
on the guard ring width. Leakages of 100nA into or out of
the SET pin creates a 0.1% error in the reference voltage.
Leakages of this magnitude, coupled with other sourcesof leakage, can cause significant errors in the output voltage, especially over wide operating temperature range.
Figure 2 illustrates a typical guard ring layout technique.

VIN

100µA

CIN
EN/UV
PGFB

12

2

11

3

10

4

13

VIOC

5

8
7

DEMO BOARD
PCB LAYOUT
ILLUSTRATES
4-TERMINALCONNECTION
TO COUTVOUT
IOUT(MAX): 500mA

OUTS
SET

GND

COUT

ILIM

CSET
30451 F03

OUT

Figure 3. COUT and CSET Connections for Best Performance

9

6

OUT

PG

RSET
1

LT3045-1

IN

SET30451 F02

Figure 2. DFN Guard Ring Layout

Since the SET pin is a high impedance node, unwanted
signals may couple into the SET pin and cause erratic
behavior. This is most noticeable when operating with aminimum output capacitor at heavy load currents. Bypassing the SET pin with a small capacitance to ground
resolves this issue — 10nF is sufficient.

Figure 3, minimize the effects of PCB trace and solder
inductance by tying the OUTS pin directly to COUT and
the GND side of CSET directly to the GND side of COUT,
as well as keep the GND sides of CIN and COUT reasonably
close. Refer to the LT3045-1 demo board manual for more
information on the recommended layout that meets theserequirements. While the LT3045-1 is robust enough not
to oscillate if the recommended layout is not followed,
depending on the actual layout, phase/gain margin, noise
and PSRR performance may degrade.

For applications requiring higher accuracy or an adjustable output voltage, the SET pin may be actively driven
by an external voltage source capable of sinking 100µA.
Connecting a precision voltage reference to the SET pin
eliminates any errors present in the output voltage dueto the reference current and SET pin resistor tolerances.

Stability and Output Capacitance

Output Sensing and Stability

Given the high PSRR and low noise performance attainedusing a single 10µF ceramic output capacitor, larger valuesof output capacitor only marginally improves the performance because the regulator bandwidth decreases withincreasing output capacitance — hence, there is little tobe gained by using larger than the minimum 10µF output
capacitor. Nonetheless, larger values of output capacitancedo decrease peak output deviations during a load transient.
Note that bypass capacitors used to decouple individualcomponents powered by the LT3045-1 increase the effective output capacitance.

The LT3045-1’s OUTS pin provides a Kelvin sense connection to the output. The SET pin resistor’s GND side
provides a Kelvin sense connection to the load’s GND side.
Additionally, for ultrahigh PSRR, the LT3045-1 bandwidthis made quite high (~1MHz), making it very close to atypical 10µF (1206 case size) ceramic output capacitor’s
self-resonance frequency (~1.6MHz). Therefore, it is very
important to avoid adding extra impedance (ESR and
ESL) outside the feedback loop. To that end, as shown in

The LT3045-1 requires an output capacitor for stability.
Given its high bandwidth, LTC recommends low ESR and
ESL ceramic capacitors. A minimum 10µF output capacitance with an ESR below 20mΩ and an ESL below 2nH is
required for stability.

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17LT3045-1
APPLICATIONS INFORMATION

X5R and X7R dielectrics result in more stable characteristics and are thus more suitable for LT3045-1. The X7R
dielectric has better stability across temperature, while the
X5R is less expensive and is available in higher values.
Nonetheless, care must still be exercised when using
X5R and X7R capacitors. The X5R and X7R codes only
specify operating temperature range and the maximum
capacitance change over temperature. While capacitancechange due to DC bias for X5R and X7R is better thanY5V and Z5U dielectrics, it can still be significant enoughto drop capacitance below sufficient levels. As shown in
Figure 6, capacitor DC bias characteristics tend to improveas component case size increases, but verification of
expected capacitance at the operating voltage is highly
recommended. Due to its good voltage coefficient in small
case sizes, LTC recommends using Murata’s GJ8 series
ceramic capacitors.

BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10µF

0
CHANGE IN VALUE (%)

X5R
–20
–40
–60
Y5V
–80
–100

0

2

4

14

6
12
8 10
DC BIAS VOLTAGE (V)1630451 F04

Figure 4. Ceramic Capacitor DC Bias Characteristics
40

BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10µF

20

X5R

0
–20
–40

Y5V

–60
–80
–100
–50

–25

0
25
75
50
TEMPERATURE (°C)

100

125

30451 F05

Figure 5. Ceramic Capacitor Temperature Characteristics
20

Voltage and temperature coefficients are not the only
sources of problems. Some ceramic capacitors have a
piezoelectric response. A piezoelectric device generates
voltage across its terminals due to mechanical stress uponit, similar to how a piezoelectric microphone works. For aceramic capacitor, this stress can be induced by mechanicalvibrations within the system or due to thermal transients.
LT3045-1 applications in high vibration environments
have three distinct piezoelectric noise generators: ceramic
output, input, and SET pin capacitors. However, due toLT3045-1’s very low output impedance over a wide frequency range, negligible output noise is generated using

CHANGE IN VALUE (%)

0

High Vibration Environments

18

20

CHANGE IN VALUE (%)

Give extra consideration to the type of ceramic capacitors
used. They are manufactured with a variety of dielectrics,
each with different behavior across temperature and applied
voltage. The most common dielectrics used are specified
with EIA temperature characteristic codes of Z5U, Y5V,
X5R and X7R. The Z5U and Y5V dielectrics are good forproviding high capacitance in the small packages, but theytend to have stronger voltage and temperature coefficientsas shown in Figure 4 and Figure 5. When used with a 5V
regulator, a 16V 10µF Y5V capacitor can exhibit an effective
value as low as 1µF to 2µF for the DC bias voltage applied
over the operating temperature range.

–20
–40
–60
–80

–100

MURATA: 25V,10%,
X7R/X5R, 10µF CERAMIC
1

5

10
15
DC BIAS (V)25

2030451 F06

GRM SERIES, 0805, 1.45mm THICKGRM SERIES, 1206, 1.8mm THICKGRM SERIES, 1210, 2.2mm THICK
GJ8 SERIES, 1206, 1.9mm THICK

Figure 6. Capacitor Voltage Coefficient for Different Case Sizes
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LT3045-1
APPLICATIONS INFORMATIONa ceramic output capacitor. Similarly, due to LT3045-1’s
ultrahigh PSRR, negligible output noise is generatedusing a ceramic input capacitor. Nonetheless, given thehigh SET pin impedance, any piezoelectric response
from a ceramic SET pin capacitor generates significant
output noise – peak-to-peak excursions of hundreds ofµVs. However, due to the SET pin capacitor’s high ESR
and ESL tolerance, any non-piezoelectrically responsive(tantalum, electrolytic, or film) capacitor can be used at
the SET pin – although electrolytic capacitors tend tohave high 1/f noise. In any case, use of a surface mountcapacitor is highly recommended.
Stability and Input Capacitance
The LT3045-1 is stable with a minimum 4.7µF IN pin capacitor. LTC recommends using low ESR ceramic capacitors.
In cases where long wires connect the power supply to
the LT3045-1’s input and ground terminals, the use of low
value input capacitors combined with a large load current
can result in instability. The resonant LC tank circuit formedby the wire inductance and the input capacitor is the cause
and not because of LT3045-1’s instability.
The self-inductance, or isolated inductance, of a wireis directly proportional to its length. The wire diameter,
however, has less influence on its self-inductance. For
example, the self-inductance of a 2-AWG isolated wirewith a diameter of 0.26" is about half the inductance of a
30-AWG wire with a diameter of 0.01". One foot of 30-AWG
wire has 465nH of self-inductance.
Several methods exist to reduce a wire’s self-inductance.
One method divides the current flowing towards theLT3045-1 between two parallel conductors. In this case,placing the wires further apart reduces the inductance; up
to a 50% reduction when placed only a few inches apart.
Splitting the wires connect two equal inductors in parallel.
However, when placed in close proximity to each other,
their mutual inductance adds to the overall self inductanceof the wires — therefore a 50% reduction is not possible
in such cases. The second and more effective techniqueto reduce the overall inductance is to place the forward
and return current conductors (the input and groundwires) in close proximity. Two 30-AWG wires separated

by 0.02" reduce the overall inductance to about one-fifthof a single wire.
If a battery mounted in close proximity powers the LT30451, a 4.7µF input capacitor suffices for stability. However,
if a distantly located supply powers the LT3045-1, use alarger value input capacitor. Use a rough guideline of 1µF(in addition to the 4.7µF minimum) per 6" of wire length.
The minimum input capacitance needed to stabilize theapplication also varies with the output capacitance aswell as the load current. Placing additional capacitanceon the LT3045-1’s output helps. However, this requires
significantly more capacitance compared to additional input
bypassing. Series resistance between the supply and theLT3045-1 input also helps stabilize the application; as little
as 0.1Ω to 0.5Ω suffices. This impedance dampens the
LC tank circuit at the expense of dropout voltage. A better
alternative is to use a higher ESR tantalum or electrolytic
capacitor at the LT3045-1 input in parallel with a 4.7µF
ceramic capacitor.
PSRR and Input Capacitance
For applications utilizing the LT3045-1 for post-regulating
switching converters, placing a capacitor directly at theLT3045-1 input results in AC current (at the switchingfrequency) to flow near the LT3045-1. This relatively highfrequency switching current generates a magnetic fieldthat couples to the LT3045-1 output, thereby degrading its
effective PSRR. While highly dependent on the PCB, theswitching pre-regulator, the input capacitance, amongst
other factors, the PSRR degradation can be easily over
30dB at 1MHz. This degradation is present even if theLT3045-1 is de-soldered from the board, because it effectively degrades the PSRR of the PC board itself. Whilenegligible for conventional low PSRR LDOs, LT3045-1’s
ultrahigh PSRR requires careful attention to higher orderparasitics in order to extract the full performance offeredby the regulator.
To mitigate the flow of high-frequency switching current
near the LT3045-1, the LT3045-1 input capacitor can be
entirely removed -- as long as the switching converter’s
output capacitor is located more than an inch away fromthe LT3045-1. Magnetic coupling rapidly decreases withincreasing distance. Nonetheless, if the switching pre30451fa

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19

LT3045-1
APPLICATIONS INFORMATION
regulator is placed too far away (conservatively morethan a couple inches) from the LT3045-1, with no input
capacitor present, as with any regulator, the LT3045-1
input will oscillate at the parasitic LC resonance frequency.
Besides, it is generally a very common (and a preferred)
practice to bypass regulator input with some capacitance.
So this option is fairly limited in its scope and not the mostpalatable solution.
To that end, LTC recommends using the LT3045-1 demoboard layout for achieving the best possible PSRR performance. The LT3045-1 demo board layout utilizes magnetic
field cancellation techniques to prevent PSRR degradation
caused by this high-frequency current flow—while utilizing
the input capacitor.
Filtering High Frequency Spikes
For applications where the LT3045-1 is used to postregulate a switching converter, its high PSRR effectively
suppresses any “noise” present at the switcher’s switchingfrequency — typically 100kHz to 4MHz. However, the very
high frequency (hundreds of MHz) “spikes” — beyond theLT3045-1’s bandwidth — associated with the switcher’s
power switch transition times will almost directly passthrough the LT3045-1. While the output capacitor is partly
intended to absorb these spikes, its ESL will limit its ability
at these frequencies. A ferrite bead or even the inductanceassociated with a short (e.g. 0.5”) PCB trace between theswitcher’s output and the LT3045-1’s input can serve as
an LC-filter to suppress these very high frequency spikes.
Output Noise
The LT3045-1 offers many advantages with respect tonoise performance. Traditional linear regulators haveseveral sources of noise. The most critical noise sources
for a traditional regulator are its voltage reference, error
amplifier, noise from the resistor divider network used forsetting output voltage and the noise gain created by thisresistor divider. Many low noise regulators pin out their
voltage reference to allow for noise reduction by bypassing
the reference voltage.
Unlike most linear regulators, the LT3045-1 does not use
a voltage reference; instead, it uses a 100µA current reference. The current reference operates with typical noise

20

current level of 20pA/√Hz (6nARMS over a 10Hz to 100kHz
bandwidth). The resultant voltage noise equals the current
noise multiplied by the resistor value, which in turn is RMS
summed with the error amplifier’s noise and the resistor’s
own noise of √4kTR — whereby k = Boltzmann’s constant
1.38 • 10–23J/K and T is the absolute temperature.
One problem that conventional linear regulators face isthat the resistor divider setting the output voltage gains up
the reference noise. In contrast, the LT3045-1’s unity-gain
follower architecture presents no gain from the SET pin
to the output. Therefore, if a capacitor bypasses the SET
pin resistor, then the output noise is independent of the
programmed output voltage. The resultant output noiseis then set just by the error amplifier’s noise — typically2nV/√Hz from 10kHz to 1MHz and 0.8µVRMS in a 10Hz
to 100kHz bandwidth using a 4.7µF SET pin capacitor.
Paralleling multiple LT3045-1s further reduces noise by√N, for N parallel regulators.
Refer to the Typical Performance Characteristics section
for noise spectral density and RMS integrated noise overvarious load currents and SET pin capacitances.
Set Pin (Bypass) Capacitance: Noise, PSRR, Transient
Response and Soft-Start
In addition to reducing output noise, using a SET pin bypass
capacitor also improves PSRR and transient performance.
Note that any bypass capacitor leakage deteriorates theLT3045-1’s DC regulation. Capacitor leakage of even 100nA
is a 0.1% DC error. Therefore, LTC recommends the useof a good quality low leakage ceramic capacitor.
Using a SET pin bypass capacitor also soft-starts the output
and limits inrush current. The RC time constant, formedby the SET pin resistor and capacitor, controls soft-start
time. Ramp-up rate from 0 to 90% of nominal VOUT is:tSS ≈ 2.3 • RSET • CSET (Fast Start-Up Disabled)
Fast Start-Up
For ultralow noise applications that require low 1/f noise(i.e. at frequencies below 100Hz), a larger value SET pin
capacitor is required, up to 22µF. While this would normallysignificantly increase the regulator’s start-up time, the30451fa

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LT3045-1
APPLICATIONS INFORMATION
LT3045-1 incorporates fast start-up circuitry that increases
the SET pin current to about 2mA during start-up.
As shown in the Block Diagram, the 2mA current source
remains engaged while PGFB is below 300mV, unless theregulator is in current limit, dropout, thermal shutdown
or input voltage is below minimum VIN.
If fast start-up capability is not used, tie PGFB to IN or to
OUT for output voltages above 300mV. Note that doing
so also disables power good functionality.

programmable power good and fast start-up capabilities
are disabled for output voltages below 300mV.
Externally Programmable Current Limit
The ILIM pin’s current limit threshold is 300mV. Connecting
a resistor from ILIM to GND sets the maximum current
flowing out of the ILIM pin, which in turn programs theLT3045-1’s current limit. With a 150mA • kΩ programming
scale factor, the current limit can be calculated as follows:
Current Limit =ENABLE/UVLO
The EN/UV pin is used to put the regulator into a micropower shutdown state. The LT3045-1 has an accurate
1.24V turn-on threshold on the EN/UV pin with 130mVof hysteresis. This threshold can be used in conjunction
with a resistor divider from the input supply to define an
accurate undervoltage lockout (UVLO) threshold for the
regulator. The EN/UV pin current (IEN) at the threshold fromthe Electrical Characteristics table needs to be consideredwhen calculating the resistor divider network:⎛ R ⎞VIN(UVLO) =1.24V • ⎜1+ EN2 ⎟ +IEN •REN2⎝ REN1 ⎠The EN/UV pin current (IEN) can be ignored if REN1 is lessthan 100k. If unused, tie EN/UV pin to IN.
Programmable Power GoodAs illustrated in the Block Diagram, power good threshold is user programmable using the ratio of two external
resistors, RPG2 and RPG1:⎛ R ⎞VOUT(PG _ THRESHOLD) = 0.3V • ⎜1+ PG2 ⎟ +IPGFB •RPG2⎝ RPG1 ⎠If the PGFB pin increases above 300mV, the open-collector
PG pin de-asserts and becomes high impedance. The
power good comparator has 7mV hysteresis and 5µs ofdeglitching. The PGFB pin current (IPGFB) from the Electrical
Characteristics table must be considered when determining
the resistor divider network. The PGFB pin current (IPGFB)
can be ignored if RPG1 is less than 30k. If power goodfunctionality is not used, float the PG pin. Please note that

150mA •kΩRILIM

For example, a 1kΩ resistor programs the current limit
to 150mA and a 2kΩ resistor programs the current limit
to 75mA. For good accuracy, Kelvin connect this resistor
to the LT3045-1’s GND pin.
In cases where IN-to-OUT differential is greater than 12V,
the LT3045-1’s foldback circuitry decreases the internalcurrent limit. As a result, internal current limit may override the externally programmed current limit level to keep
the LT3045-1 within its safe-operating-area (SOA). See
the Internal Current Limit vs Input-to-Output Differential
graph in the Typical Performance Characteristics section.
As shown in the Block Diagram, the ILIM pin sources current
proportional (1:500) to output current; therefore, it also
serves as a current monitoring pin with a 0V to 300mV
range. If external current limit or current monitoring is
not used, tie ILIM to GND.
Output Overshoot Recovery
During a load step from full load to no load (or lightload), the output voltage overshoots before the regulator
responds to turn the power transistor OFF. Given that there
is no load (or very light load) present at the output, it takes
a long time to discharge the output capacitor.
As illustrated in the Block Diagram, the LT3045-1 incorporates an overshoot recovery circuitry that turns on acurrent sink to discharge the output capacitor in the event
OUTS is higher than SET. This current is typically about
4mA. No load recovery is disabled for input voltages lessthan 2.5V or output voltages less than 1.5V.
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21

LT3045-1
APPLICATIONS INFORMATION
VIN
5V ±5%

If OUTS is externally held above SET, the current sinkturns ON in an attempt to restore OUTS to its programmed
voltage. The current sink remains ON until the external
circuitry releases OUTS.

LT3045-1

IN
100µA

10µF

–
+

EN/UV

OUT

PGFB
VIOC

20mΩ

OUTS
SET

GND ILIM

PG

VOUT
3.3V
IOUT(MAX)
1A

LT3045-1

IN
100µA

–
+

EN/UV

OUT

PGFB
VIOC

20mΩ

OUTS
SET

GND ILIM

PG

10µF

30451 F07

16.5k

Direct Paralleling for Higher Current

10µF

0.47µF

Higher output current is obtained by paralleling multiple
LT3045-1s. Tie all SET pins together and all IN pins together.
Connect the OUT pins together using small pieces of PCB
trace (used as a ballast resistor) to equalize currents in
the LT3045-1s. PCB trace resistance in milliohms/inch isshown in Table 2.
Table 2. PC Board Trace Resistance
WEIGHT (oz)10mil WIDTH

20mil WIDTH

1

54.3

27.1

2

27.1

13.6

Trace resistance is measured in mΩ/in.

The small worst-case offset of 2mV for each paralleled
LT3045-1 minimizes the required ballast resistor value.
Figure 7 illustrates that two LT3045-1s, each using a 20mΩPCB trace ballast resistor, provide better than 20% accurate
output current sharing at full load. The two 20mΩ external
resistors only add 10mV of output regulation drop with a
1A maximum current. With a 3.3V output, this only adds
0.3% to the regulation accuracy. As has been discussed
previously, tie the OUTS pin directly to the output capacitor.

Figure 7. Parallel Devices

More than two LT3045-1s can also be paralleled for evenhigher output current and lower output noise. Parallelingmultiple LT3045-1s is also useful for distributing heat on
the PCB. For applications with high input-to-output voltage
differential, an input series resistor or resistor in parallelwith the LT3045-1 can also be used to spread heat.
PCB Layout Considerations

Figure 8. Recommended DFN Layout

22

Given the LT3045-1’s high bandwidth and ultrahigh
PSRR, careful PCB layout must be employed to achieve
full device performance. Figure 8 shows a recommended
layout that delivers full performance of the regulator.
Refer to the LT3045-1’s DC2593A demo board manual
for further details.

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LT3045-1
APPLICATIONS INFORMATIONHigh Efficiency Linear Regulator: Voltage Input-toOutput Control (VIOC)
The VIOC pin is used to control an upstream switching
converter (e.g. buck, boost, buck-boost, etc) to maintaina constant voltage across the LT3045-1, regardless of
the LDO’s output voltage. This maximizes efficiency
while maintaining PSRR performance. The VIOC pin is
the output of a fast unity-gain amplifier that measuresthe difference between IN and OUT or 1.5V, whichever ishigher. As shown in Figure 9, the VIOC feature is simple
to use. Just tie the VIOC pin to the upstream switching
converter’s feedback (FB) pin, and this will regulate theLT3045-1’s input-to-output differential to the switching
converter’s feedback voltage. When paralleling multiple
LT3045-1s, tie the VIOC pin of one of the LT3045-1 to the
upstream switching converter’s feedback pin and float theremaining VIOC pins.

VIN

IN

VLDOINSW

FB

For example, for a switching converter with less than
100kHz bandwidth and a phase margin of 50°, using the
VIOC buffer, the phase margin will degrade by at most 2°.
Hence, the phase margin for the switching converter (using
the VIOC pin) will be at least 48°. Given the VIOC buffer isinside the switching converter’s feedback loop, the total
capacitance on the VIOC pin is required to be below 20pF.
As shown in Figure 10, the input-to-output differential
voltage is easily programmable to support different apLT3045-1

IN
EN/UV

UPSTREAM
DC/DC
CONVERTER

While the VIOC buffer is inside the switching converter’s
feedback loop, given the VIOC buffer’s high bandwidth,
the switching converter’s frequency compensation doesn’t
need to be adjusted. Phase delay through the VIOC buffer
is typically less than 2° for frequencies as high as 100kHz;
hence, within the switching converter’s bandwidth (usuallymuch less than 100kHz), the VIOC buffer will be transparent and just act like an ideal wire.

+ –

OUT

VLDOOUT: VARIABLE
IOUT(MAX): 500mA

OUTS

10µF

1×

PGFB
VFBSWITCHER

VIOC
SET

R1

ILIM

GND

PG
30451 F09

0.47µF

Figure 9. VIOC Basic Operation

VIN

IN

EN/UV

UPSTREAM
DC/DC
CONVERTER
FB

LT3045-1

IN

SW

R3
R2

+ –

OUT

VOUT: VARIABLE
IOUT(MAX): 500mA

OUTS

10µF

1×

PGFB
VIOC
SET

R1

GND

ILIM

PG
30451 F100.47µF

Figure 10. Programming Input-to-Output Differential
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23

LT3045-1
APPLICATIONS INFORMATION
plication needs (PSRR vs. power dissipation) using thefollowing equation:
VLDOIN – VLDOOUT = VVIOC = VFBSWITCHER •be programmed below the upstream switching converter’s
feedback pin. For VOUT ≤ 1.5V, the VIOC programming
range is 1V ±5%. If VIOC is set to be outside this range,
then the LT3045-1 input voltage will rise to the maximum
value set using R3. If VIOC functionality is not used, float
the VIOC pin.

R1+R2
R1

Furthermore, in the event the LT3045-1 SET pin opens up,
the LT3045-1 input voltage can rise up to the switcher’s
input voltage, and thus potentially violate the LT3045-1’s
absolute maximum rating. To prevent this, the maximum
LT3045-1 input voltage can be set using a resistor (R3)
between the VIOC and IN pins of the regulator such that:
V(MAX)LDOIN = VFBSWITCHER •Given the maximum VIOC programming voltage is dependent on VOUT, care must be taken in setting the VIOC
voltage. For instance, if VIOC is set to 1V, the LDO’s INto-OUT differential will be regulated to 1V for VOUT > 1.5V.
Similarly, if VIOC is set to 2V, the regulator’s IN-to-OUT
differential will be regulated to 2V for VOUT > 2.5V (i.e.
VVIOC + 0.5V). However, if the output voltage is below
2.5V, for this example, then the LDO will not be able todrive its VIOC pin to the right level of 2V. As a result, theupstream pre-regulator’s output will rise, thereby causing the LT3045-1 input voltage to rise to the maximum
voltage set using R3. Hence, for protection under various
fault conditions, the use of R3 to set the maximum VIN
voltage (below 20V) is required.

R1+R2+R3+ISINK • R3
R1

Moreover, the VIOC pin is capable of sourcing 200µA
and sinking 15µA of current. To mitigate the effect of thesink current on the maximum LDO input voltage (shown
above), choose R1 such that the resistor divider typicallyruns at least 100µA.
For VOUT > 1.5V, VIN = VOUT + VVIOC. The VIOC pin voltage (and hence the input-to-output differential) can be
programmed anywhere between a minimum of 1V anda maximum of 4V or VOUT – 0.5V (for VOUT > 1.5V),
whichever is lower. For applications where the feedback
pin of the switching regulator is below 1V, use resistors
R1 and R2 to make sure the VIOC pin is within the aforementioned range. Note that the VIOC pin voltage cannot
VIN
20V

IN

10nF

40.2k

LT8608
BST

EN/UV

SW

TR/SS

PG

0.22µF

2.2µH

LT3045-1

EN/UV

100µA

–
+

PGFB
2.21k

FB

INTVCC GND

Figure 11 shows a typical VIOC application used to postregulate the output of the LT8608 buck converter. The VIOC
voltage is set at 1V with the maximum LDO input voltage
set to 16.5V. Figure 12 shows the LDO’s input and output
voltage when pulsing the LT3045-1’s EN/UV pin, and as
IN

47µF

MODE
RT

Typical VIOC Application

7.68k

140k

VLDOIN – VLDOUT = 1V
VMAXLDOIN = 16.5V

OUT
OUTS

VIOC
SET

GND ILIM

PG

10µF
30451 F11

1µF
fSW = 1MHz
L: XFL4020-222MEC

VOUT: VARIABLE
IOUT(MAX): 500mA

4.7µF

249Ω

Figure 11. Typical LT3045-1 Post-Regulating Application

24

30451fa

For more information www.linear.com/LT3045-1

LT3045-1
APPLICATIONS INFORMATION
can be seen, when the LDO is disabled, the LDO input voltage goes to the maximum input voltage set by the resistor
divider on the VIOC pin. Figure 13 shows the load step
response of the LT8608 using the VIOC buffer. Figure 14
shows the LDO’s input and output voltage response to
stepping the set pin from 3V to 4V. Figure 15 shows the
LDO’s output and input voltage while ramping the SET
pin from 0V to 10V, and as can be seen, the LT8608’s
output voltage tracks the LT3045’s output voltage when
it is greater than 1.5V. Lastly, Figure 16 shows the noise
spectral density at the LT3045-1 input and output.

1V/DIVVSET AND LDOOUT ARE OVERLAID

0V

VSET
LDOIN
LDOOUT
1ms/DIV

30451 F14

VSET = 3V TO 4V
IL = 500mA

Figure 14. Stepping VSET from 3V to 4V (and Back to 3V)
VSETLDOOUT
LDOIN

5V/DIV
0V

2V/DIV
VEN/UVLDOIN
LDOOUT

0V
1V/DIVVSET AND LDOOUT ARE OVERLAID

0V
500ms/DIV30451 F12RSET = 33.2kΩ
RL = 6.6Ω
VIN LT8608 = 20V

Figure 15. Ramping VSET from 0V to 10V (and Back to 0V)

Figure 12. LT3045-1 EN/UV Pulse

1000

LDOIN = 4.3V
LDOOUT = 3.3V
100 ILOAD = 500mA

NOISE (µV/√Hz)

0mA
500mA/DIV
100mV/DIV

50mV/DIVILOAD
LDOIN (ac)LDOOUT (ac)200µs/DIVRSET = 33.2kΩ
ILOAD = 10mA to 500mA

30451 F15

5ms/DIV

IL = 500mA

30451 F13

10

1

0.1

0.01

LDOOUT
LDOIN
Noise Floor
10

100

1k
10k 100k
FREQUENCY (Hz)

1M

10M
30451 F16

Figure 13. Load Step Response Using the VIOC Buffer

Figure 16. LT3045-1’s Input and Output Noise Spectral Density

30451fa

For more information www.linear.com/LT3045-1

25

LT3045-1
APPLICATIONS INFORMATION
Thermal Considerations

Table 3. Measured Thermal Resistance for DFN Package

The LT3045-1 has internal power and thermal limiting
circuits that protect the device under overload conditions.
The thermal shutdown temperature is nominally 165°C
with about 8°C of hysteresis. For continuous normalload conditions, do not exceed the maximum junction
temperature (125°C for E- and I-grades). It is important toconsider all sources of thermal resistance from junction toambient. This includes junction-to-case, case-to-heat sinkinterface, heat sink resistance or circuit board-to-ambientas the application dictates. Additionally, consider all heatsources in close proximity to the LT3045-1.
The undersides of the DFN and MSOP packages have
exposed metal from the lead frame to the die attachment.
Both packages allow heat to directly transfer from the diejunction to the PCB metal to limit maximum operating
junction temperature. The dual-in-line pin arrangement
allows metal to extend beyond the ends of the packageon the topside (component side) of the PCB.
For surface mount devices, heat sinking is accomplishedby using the heat spreading capabilities of the PCB and its
copper traces. Copper board stiffeners and plated throughholes can also be used to spread the heat generated by
the regulator.
Tables 3 and 4 list thermal resistance as a function of copperarea on a fixed board size. All measurements were taken
in still air on a 4 layer FR-4 board with 1oz solid internal
planes and 2oz top/bottom planes with a total board thickness of 1.6mm. The four layers were electrically isolatedwith no thermal vias present. PCB layers, copper weight,
board layout and thermal vias affect the resultant thermal
resistance. For more information on thermal resistanceand high thermal conductivity test boards, refer to JEDEC
standard JESD51, notably JESD51-7 and JESD51-12.
Achieving low thermal resistance necessitates attention
to detail and careful PCB layout.

COPPER AREATOP SIDE*

BOTTOM SIDE

BOARD AREA

THERMALRESISTANCE

2500mm2

2500mm2

2500mm2

34°C/W

1000mm2

2500mm2

2500mm2

34°C/W

225mm22500mm2

2500mm2

35°C/W

100mm22500mm2

2500mm2

36°C/W*Device is mounted on topside

Table 4. Measured Thermal Resistance for MSOP Package
COPPER AREATOP SIDE*

BOTTOM SIDE

BOARD AREA

THERMALRESISTANCE

2500mm2

2500mm2

2500mm2

33°C/W

1000mm2

2500mm2

2500mm2

33°C/W

225mm22500mm2

2500mm2

34°C/W

100mm22500mm2

2500mm2

35°C/W*Device is mounted on topside

Calculating Junction Temperature
Example: Given an output voltage of 3.3V and input voltage
of 5V ± 5%, output current range from 1mA to 500mA,
and a maximum ambient temperature of 85°C, what is the
maximum junction temperature?
The LT3045-1’s power dissipation is:
IOUT(MAX) • (VIN(MAX) – VOUT) + IGND • VIN(MAX)where:IOUT(MAX) = 500mA
VIN(MAX) = 5.25V
IGND (at IOUT = 500mA and VIN = 5.25V) = 12.5mA
thus:
PDISS = 0.5A • (5.25V – 3.3V) + 12.5mA • 5.25V = 1W
Using a DFN package, the thermal resistance is in therange of 34°C/W to 36°C/W depending on the copper area.
Therefore, the junction temperature rise above ambient
approximately equals:
1W • 35°C/W = 35°C

26

30451fa

For more information www.linear.com/LT3045-1

LT3045-1
APPLICATIONS INFORMATION
The maximum junction temperature equals the maximum ambient temperature plus the maximum junction
temperature rise above ambient:
TJMAX = 85°C + 35°C = 120°C
Overload Recovery
Like many IC power regulators, the LT3045-1 incorporates
safe-operating-area (SOA) protection. The SOA protection
activates at input-to-output differential voltages greaterthan 12V. The SOA protection decreases the current limit
as the input-to-output differential increases and keeps
the power transistor inside a safe operating region for all
values of input-to-output voltages up to the LT3045-1’s
absolute maximum ratings. The LT3045-1 provides somelevel of output current for all values of input-to-output differentials. Refer to the Current Limit curves in the Typical
Performance Characteristics section. When power is first
applied and input voltage rises, the output follows the input
and keeps the input-to-output differential low to allow theregulator to supply large output current and start-up intohigh current loads.
Due to current limit foldback, however, at high input voltages a problem can occur if the output voltage is low andthe load current is high. Such situations occur after theremoval of a short-circuit or if the EN/UV pin is pulled highafter the input voltage has already turned ON. The load
line in such cases intersects the output current profile attwo points. The regulator now has two stable operating
points. With this double intersection, the input power
supply may need to be cycled down to zero and broughtback up again to make the output recover. Other linear
regulators with foldback current limit protection (such as
the LT1965 and LT1963A) also exhibit this phenomenon,
so it is not unique to the LT3045-1.

Protection Features
The LT3045-1 incorporates several protection features forbattery-powered applications. Precision current limit andthermal overload protection protect the LT3045-1 against
overload and fault conditions at the device’s output. For
normal operation, do not allow the junction temperature
to exceed 125°C (E-grade, I-grade).
To protect the LT3045-1’s low noise error amplifier, theSET-to-OUTS protection clamp limits the maximum voltage
between SET and OUTS with a maximum DC current of
20mA through the clamp. So for applications where SET
is actively driven by a voltage source, the voltage sourcemust be current limited to 20mA or less. Moreover, to limit
the transient current flowing through these clamps duringa transient fault condition, limit the maximum value of theSET pin capacitor (CSET) to 22µF.
The LT3045-1 also incorporates reverse input protection
whereby the IN pin withstands reverse voltages of up to–20V without causing any input current flow and without
developing negative voltages at the OUT pin. The regulator
protects both itself and the load against batteries that areplugged-in backwards.
In circuits where a backup battery is required, several
different input/output conditions can occur. The output
voltage may be held up while the input is either pulled to
GND, pulled to some intermediate voltage, or left opencircuit. In all of these cases, the reverse-current protection
circuitry prevents current flow from output to the input.
Nonetheless, due to the OUTS-to-SET clamp, unless theSET pin is floating, current can flow to GND through theSET pin resistor as well as up to 15mA to GND throughthe output overshoot recovery circuitry. This current flow
through the output overshoot recovery circuitry can besignificantly reduced by placing a Schottky diode between
OUTS and SET pins, with its anode at the OUTS pin.

30451fa

For more information www.linear.com/LT3045-1

27

LT3045-1
TYPICAL APPLICATIONS
12VIN to 3.3VOUT with 0.8µVRMS Integrated NoiseLT3045-1

IN

VIN
12V ±5%
4.7µF

100µA

–
+

EN/UV
200k
PG
VIOC

VOUT
3.3V
IOUT
200mA

OUT
OUTS

SET

GND

ILIM

10µF

PGFB

453k

4.7µF

750Ω

33.2k

49.9k
30451 TA02

Low Noise CC/CV Lab Power Supply
LT3045-1

IN

VIN
4.7µF

Ultralow Noise Current Source for RF Biasing Applications
VIN
1.8V TO 20V
4.7µF

100µA

–
+

EN/UV
PGFB

–
+

PGFB

OUT

VOUT

OUTS
SET

100µA
EN/UV

PG
VIOC

LT3045-1

IN

GND

ILIM

10µF

ROUT = R1 + RLOAD

OUT

PG
VIOC

R1
1Ω

VOUT(MAX): 15V

OUTS
SET

GND

ILIM

10µF
RLOAD

0.47µF

RSET

4.7µF

RIOUT

RSET
2k

30451 TA03

30451 TA04

VOUT(MAX) = 100μA • RSETIOUT(MAX) =28

150mA • kΩRIOUT

OUTPUT CURRENT NOISE = 0.8µVRMS/ROUTINCREASE R1 (AND RSET) TO REDUCE CURRENT NOISE

30451fa

For more information www.linear.com/LT3045-1

LT3045-1
TYPICAL APPLICATIONSProgramming Undervoltage Lockout
VIN
4V Turn-ON
3.4V Turn-OFF
4.7µF

LT3045-1

IN
100µA
PGFB
REN2
110k

PG

⎛ 110k ⎞VIN(UVLO)RISING =1.24V • ⎜1+⎟⎝ 49.9k ⎠

–
+

REN1
49.9k

VIOC

VOUT
3.3V
IOUT(MAX)
500mA

OUT

EN/UV

OUTS
SET

10µF

GND ILIM

30451 TA05

0.47µF

33.2k

Ratiometric Tracking
LT3045-1

IN
100µA

–
+

EN/UV
PGFB
IN

VIN
5.5V TO 20V

–
+

EN/UV
PGFB

0.1µF
OUT

PG
VIOC

0.1µF

OUTS
SET

GND

ILIM

10µF

VOUT
5V

OUTS

VIOC

100µA

10µF

OUT

PG

LT3045-1

SET

16.9k

GND

10µF

ILIM

30451 TA06

VOUT
3.3V
MIN LOAD 200µA

33.2k

30451fa

For more information www.linear.com/LT3045-1

29

LT3045-1
TYPICAL APPLICATIONS
Ultralow 1/f Noise Reference Buffer
VIN
6V ±5%

LT3045-1

IN
100µA

4.7µF

–
+

EN/UV
PGFB
1,2

6,7

LTC6655-5

VIOC

3,4,5

VOUT = 5V
IOUT(MAX)
500mA

OUT

PG

OUTS
SET

GND

10µF

ILIM

1k
30451 TA07

10µF

49.9k

4.7µF

Paralleling Multiple Devices Using ILIM (Current Monitor) to Cancel Ballast Resistor Drop

LT3045-1IN
10µF

LT3045-1

100µA
EN/UV

VOUT = 3.3V
IOUT(MAX) = 1A

PGFB

OUT

PG
VIOC

OUTS
SET

IN
100µA

–
+

GND

ILIM

+
–

VIN
5V ±5%

OUT
20mΩ

20mΩ

10µF

10µF

EN/UV
PGFB
PG

OUTS
ILIM

RILIM
287Ω

GND

SET VIOC

287Ω
30451 TA08

1µF

16.5k

N = NUMBER OF DEVICES IN PARALLELRCDC = CABLE (BALLAST RESISTOR) DROP CANCELLATION RESISTORRILIM = CURRENT LIMIT PROGRAMMING RESISTOR
RBALLAST = BALLAST RESISTORILIM = OUTPUT CURRENT LIMIT

30

RCDC
5Ω

RILIM = 150mA • kΩ/ILIM – RCDC • N= 287Ω (FOR 500mA ILIM PER REGULATOR)RCDC = RBALLAST • 500/N= 5Ω

30451fa

For more information www.linear.com/LT3045-1

LT3045-1
TYPICAL APPLICATIONS
Paralleling Multiple LT3045-1s for 2A Output Current
LT3045-1

IN

VIN
5V ±5%
22µF

LT3045-1

100µA

100µA

–
+

200k

OUT
PG

OUT
20mΩ

OUTS
SET ILIM

GND

+
–

EN/UV

PGFB

20mΩ

10µF

ILIM

10µF

EN/UV
PGFB
PG

OUTS
GND

SET VIOC

453k

49.9k

VOUT = 3.3V
IOUT(MAX) = 2A
DROPOUT = 300mV

0.8µVRMS4= 0.4µVRMSOUTPUT NOISE =LT3045-1

IN

LT3045-1

100µA
EN/UV
PGFB

OUT

PG
VIOC

OUT

OUTS
SET

IN

100µA

–
+

GND

+
–

VIOC

IN

ILIM

4.7µF

20mΩ

20mΩ

10µF

10µF

PGFB
PG

OUTS
ILIM

EN/UV

GND

SET VIOC8.25k30451 TA09

30451fa

For more information www.linear.com/LT3045-1

31

LT3045-1
TYPICAL APPLICATIONS
Low Noise Wheatstone Bridge Power Supply
LT1763 NOISE: 20µVRMS (10Hz TO 100kHz)
LT3045-1 NOISE: 0.8µVRMS (10Hz TO 100kHz)

LT3045-1

IN

VIN
5V ±5%
4.7µF

100µA
EN/UV
200k

–
+
OUT

PG

RESISTORTOLERANCEBRIDGE PSRRNOISE AT VBRIDGEUSING LT1763

NOISE AT VBRIDGEUSING LT3045-1

PERFECT
MATCHING

INFINITE

–

–

1%

40dB

200nVRMS

8nVRMS

5%26dB

1000nVRMS

42.5nVRMS

VOUT: 3.3V AND IOUT(MAX): 500mA
R1

OUTS

VIOC

SET

GND ILIM PGFB

10µF

R3
VBRIDGE

453k

+
R2

4.7µF

–
R4

49.9k

33.2k

30451 TA10PGFB Disabled without Reverse Input Protection
LT3045-1

IN

VIN
4.7µF

PGFB Disabled with Reverse Input Protection

4.7µF

100µA

–
+

EN/UV
PGFB

0.47µF

VIOC

OUT

VOUT

PGFB

OUTS
GND

ILIM

PG

10µF

RSET

0.47µF30451 TA11

32

–
+

1N4148

OUT

SET

100µA

EN/UV

PG
VIOC

LT3045-1

IN

VIN

VOUT

OUTS
SET

GND

ILIM

10µF

RSET

30451 TA1230451fa

For more information www.linear.com/LT3045-1

LT3045-1
PACKAGE DESCRIPTION

Please refer to http://www.linear.com/product/LT3045-1#packaging for the most recent package drawings.
DD Package
12-Lead Plastic DFN (3mm × 3mm)

(Reference LTC DWG # 05-08-1725 Rev A)

0.70 ±0.05

3.50 ±0.05
2.10 ±0.05

2.38 ±0.05
1.65 ±0.05
PACKAGEOUTLINE

0.25 ±0.05

0.45 BSC
2.25 REF

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONSAPPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

3.00 ±0.10(4 SIDES)

R = 0.115
TYP
7

0.40 ±0.10
122.38 ±0.10
1.65 ±0.10
PIN 1 NOTCH
R = 0.20 OR
0.25 × 45°
CHAMFERPIN 1
TOP MARK(SEE NOTE 6)6
0.200 REF

1

0.23 ±0.05
0.45 BSC

0.75 ±0.05
2.25 REF
0.00 – 0.05

(DD12) DFN 0106 REV A

BOTTOM VIEW—EXPOSED PAD

NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD AND TIE BARS SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE

30451fa

For more information www.linear.com/LT3045-1

33

LT3045-1
PACKAGE DESCRIPTION

Please refer to http://www.linear.com/product/LT3045-1#packaging for the most recent package drawings.
MSE Package
12-Lead Plastic MSOP, Exposed Die Pad(Reference LTC DWG # 05-08-1666 Rev G)

BOTTOM VIEW OFEXPOSED PAD OPTION
2.845 ±0.102(.112 ±.004)

5.10(.201)
MIN

2.845 ±0.102(.112 ±.004)

0.889 ±0.127(.035 ±.005)

61

1.651 ±0.102(.065 ±.004)

1.651 ±0.102 3.20 – 3.45(.065 ±.004) (.126 – .136)

12

0.65
0.42 ±0.038(.0256)(.0165 ±.0015)
BSC
TYP
RECOMMENDED SOLDER PAD LAYOUT

0.254(.010)

0.35
REF

4.039 ±0.102(.159 ±.004)(NOTE 3)0.12 REF

DETAIL “B”
CORNER TAIL IS PART OF
DETAIL “B” THE LEADFRAME FEATURE.
FOR REFERENCE ONLY
7
NO MEASUREMENT PURPOSE

12 11 10 9 8 7

0.406 ±0.076(.016 ±.003)
REF

DETAIL “A”
0° – 6° TYP

3.00 ±0.102(.118 ±.004)(NOTE 4)4.90 ±0.152(.193 ±.006)

GAUGE PLANE

0.53 ±0.152(.021 ±.006)
DETAIL “A”

1.10(.043)
MAX

0.18(.007)SEATING
PLANE

0.22 – 0.38(.009 – .015)
TYP

1 2 3 4 5 6

0.650(.0256)BSC

0.86(.034)
REF

0.1016 ±0.0508(.004 ±.002)

MSOP (MSE12) 0213 REV G
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD SHALLNOT EXCEED 0.254mm (.010") PER SIDE.

34

30451fa

For more information www.linear.com/LT3045-1

LT3045-1
REVISION HISTORY
REV

DATE

DESCRIPTION

A

09/17

Modified Typical Application circuit.

PAGE NUMBER
1

Modified conditions for 3 VIOC curves: IOUT = 1mA.

12

Modified Figure 11.

2330451fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representaFor more
informationwww.linear.com/LT3045-1
tion that the interconnectionof its circuits
as describedherein will not infringe on existing patent rights.

35

LT3045-1
TYPICAL APPLICATION
Parallel Devices
VIN

IN

UPSTREAM
DC/DC CONVERTERFBLT3045-1

IN

SW
R3

R2
R1

100µA

–
+

EN/UV

OUT

PGFB

20mΩ

OUTS
VIOC

SET

GND ILIM

PG

10µF

VOUT: VARIABLE
IOUT(MAX): 1A

LT3045-1

IN
100µA

–
+

EN/UV

OUT

PGFB
VIOC

20mΩ

OUTS
SET

GND ILIM

PG

10µF

30451 TA13

0.47µF

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3630451fa
LT 0917 REV A • PRINTED IN USA

For more information www.linear.com/LT3045-1

www.linear.com/LT3045-1

 LINEAR TECHNOLOGY CORPORATION 2017