TPS7A33
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SBVS169C – DECEMBER 2011 – REVISED FEBRUARY 2013

–36-V, –1-A, Ultralow-Noise Negative Voltage Regulator
FEATURESDESCRIPTION••The TPS7A33 series of linear regulators are negative
voltage (–36 V), ultralow-noise (16 μVRMS, 72 dB
PSRR) linear regulators capable of sourcing amaximum load of 1 A.

1

2

•
•
•
•
•
•
•

Input Voltage Range: –3 V to –36 V
Noise:– 16 μVRMS (10 Hz to 100 kHz)Power-Supply Ripple Rejection:– 72 dB (10 kHz)
Adjustable Output: –1.18 V to –33 V
Maximum Output Current: 1 A
Stable with Ceramic Capacitors ≥ 10 μF
Built-In Current-Limit and Thermal ShutdownProtection
Available in an External Heatsink-Capable,
High Thermal Performance TO-220 Package
Operating Temperature Range:–40°C to +125°C

APPLICATIONS

1 2 3 4 5 6 7

NC

NC

NC

IN

17

16

RGW PACKAGE
5-mm ´ 5-mm QFN-20(Top View)

18

KC PACKAGE
TO-220-7(Top View)

19

•
•
•
•
•

OUT

•
•

Supply Rails for Op Amps, DACs, ADCs, andOther High-Precision Analog Circuitry
Audio
Post DC/DC Converter Regulation and Ripple
Filtering
Test and Measurement
MedicalIndustrial Instrumentation
Base Stations and Telecom Infrastructure
12-V and 24-V Industrial Buses

20

•

15

IN

NC

2

14

NR/SS

13

EN

4

12

NC

5

11

NC

NC
NC

GND

In addition, the TPS7A33 family of linear regulators issuitable for post dc-dc converter regulation. By
filtering out the output voltage ripple inherent to dc-dc
switching conversion, maximum system performanceis ensured in sensitive instrumentation, medical, test
and measurement, audio, and RF applications.
For applications where positive and negative highperformance rails are required, consider the
TPS7A4700 positive high-voltage, ultra-low noise,
low-dropout linear regulator as well.

IN

OUT

+15 V

TPS7A47
+LDO
EN
GND

1

3

The TPS7A33 family is designed using bipolar
technology primarily for high-accuracy, high-precision
instrumentation applications, where clean voltage
rails are critical to maximize system performance.
This feature makes it ideal to power operational
amplifiers, analog-to-digital converters (ADCs),
digital-to-analog converters (DACs), and other highperformance analog circuitry.

+18 V

OUT

FB

The TPS7A33 series include a complementary metaloxide semiconductor (CMOS) logic-level-compatible
enable pin (EN) to allow for user-customizable power
management schemes. Other features available
include built-in current limit and thermal shutdown
features to protect the device and system during fault
conditions.

-18 V

IN

OUT

TPS7A33
-LDO
EN
GND

-15 V

6

7

8

9

10

GND

NC

NC

NC

EN
IN
NC FB
NR/SS GND OUT

NC

EVM

NOTE: RGW package is product preview.

Typical Application: Post DC/DC Converter
Regulation for High-Performance Analog Circuitry12Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does notnecessarily include testing of all parameters.

Copyright © 2011–2013, Texas Instruments Incorporated

TPS7A33
SBVS169C – DECEMBER 2011 – REVISED FEBRUARY 2013

www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION (1)PRODUCTVOUT
XX is nominal output voltage (01 = Adjustable). (2)YYY is package designator.
Z is package quantity.

TPS7A33xxyyyz

(1)
(2)

For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit thedevice product folder on www.ti.com.
For fixed –1.2-V operation, tie FB to OUT.

ABSOLUTE MAXIMUM RATINGS (1)Over operating free-air temperature range –40°C ≤ TJ ≤ +125°C, unless otherwise noted.
VALUE

Voltage

Current

Electrostatic discharge rating

(2)

MAX

UNIT

IN pin to GND pin

–36

+0.3

V

OUT pin to GND pin

–33

+0.3

V

OUT pin to IN pin

–0.3

+36

V

FB pin to GND pin

–2

+0.3

V

FB pin to IN pin

–0.3

+36

V

EN pin to GND pin

–36

+10

V

NR/SS pin to IN pin

–0.3

+36

V

NR/SS pin to GND pin

–2

+0.3

V

°C

Peak output

Temperature

(1)

MIN

Internally limited

Operating virtual junction, TJ, absolute maximum range (2)

–40

+150

Storage, Tstg

–65

+150

°C

Human body model (HBM)

1kV

Charged device model (CDM)

500

V

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolutemaximum rated conditions for extended periods may affect device reliability.
No permanent damage will occur to the part operating within this range though electrical performance is not ensured outside theoperating free-air temperature range.

THERMAL INFORMATIONTPS7A33
THERMAL METRIC (1)KC (TO-220)

RGW (QFN) (2)7 PINS

20 PINS

θJA

Junction-to-ambient thermal resistance

31.2

30.5

θJC(top)Junction-to-case(top) thermal resistance

40.0

27.6

θJB

Junction-to-board thermal resistance

17.4

N/A

ψJT

Junction-to-top characterization parameter

6.4

0.37

ψJB

Junction-to-board characterization parameter

17.2

10.6

θJC(bottom)

Junction-to-case(bottom) thermal resistance

0.8

4.1

(1)
(2)

2

UNITS

°C/W

For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The RGW package is product preview.

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SBVS169C – DECEMBER 2011 – REVISED FEBRUARY 2013

ELECTRICAL CHARACTERISTICS (1)At –40°C ≤ TJ ≤ +125°C, |VIN| = |VOUT(NOM)| + 1.0 V or |VIN| = 3.0 V (whichever is greater), VEN = VIN, IOUT = 1 mA, CIN = 10 μF, COUT = 10
μF, CNR/SS = 0 nF, and FB tied to OUT, unless otherwise noted.
TPS7A33
PARAMETER
VIN

Input voltage range

VREF

Internal reference

VUVLO

Under-voltage lockout threshold

TEST CONDITIONS

MIN

TYP

–35.0

UNIT

–3.0

V

–1.157

V

TJ = +25°C, VFB = VREF

–1.192

Output voltage range (2)|VIN| ≥ |VOUT(NOM)| + 1.0 V

–33.2

VREF

V

Nominal accuracy

TJ = +25°C, |VIN| = |VOUT(NOM)| + 0.5 V

–1.5

1.5

%VOUT

VOUT
Overall accuracy–1.175MAX-2.0

5.0 V ≤ |VIN| ≤ 35 V
1 mA ≤ IOUT ≤ 1 A|VOUT(NOM)| + 1.0 V ≤ |VIN| ≤ 35 V
1 mA ≤ IOUT ≤ 1 A

V

±1.0
–2.5

%VOUT
2.5

%VOUT

ΔVO(ΔVI)

Line regulation|VOUT(NOM)| + 1.0 V ≤ |VIN| ≤ 35 V

0.14

%VOUT

ΔVO(ΔIL)

Load regulation

1 mA ≤ IOUT ≤ 1 A

0.4

%VOUT

VIN = 95% VOUT(NOM), IOUT = 500 mA

290

mV

|VDO|

Dropout voltage

ILIM

Current limit

IGND

Ground current|ISHDN|

Shutdown supply current

I FB

Feedback current (3)|IEN|

Enable current

VIN = 95% VOUT(NOM), IOUT = 1 A

325

VOUT = 90% VOUT(NOM)

1900

800

mV

IOUT = 0 mA

210

IOUT = 500 mA

5

VEN = +0.4 V

1.0

3.0

μA

VEN = –0.4 V

1.0

3.0

μA

14

100

nA

VEN = |VIN| = |VOUT(NOM)| + 1.0 V

0.48

1.0

μA

VIN = VEN = –35 V

0.51

1.0

μA

VIN = –35 V, VEN = +10 V

0.50

1.0

μA

mA
μA

350

mA

V+EN_HI

Positive enable high-level voltage

2.0

10

V

V+EN_LO

Positive enable low-level voltage

0

0.4

V

V–EN_HI

Negative enable high-level voltage

VIN

–2.0

V

V–EN_LO

Negative enable low-level voltage

–0.4

0

V

Vn

Output noise voltage

VIN = –3 V, VOUT(NOM) = VREF, COUT = 22 μF,
CNR/SS = 10 nF, BW = 10 Hz to 100 kHz

16

μVRMS

PSRR

Power-supply rejection ratio

VIN = –6.2 V, VOUT(NOM) = –5 V, COUT = 22 μF,
CNR/SS = 10 nF, CFF (4) = 10 nF, f = 10 kHz

72

dB

TSD

Thermal shutdown temperature

Shutdown, temperature increasing

+170

°C

Reset, temperature decreasing

+150

°C

TJ

Operating junction temperature
range

(1)
(2)
(3)
(4)

–40

+125

°C

At operating conditions, VIN ≤ 0 V, VOUT(NOM) ≤ VREF ≤ 0 V. At regulation, VIN ≤ VOUT(NOM) – |VDO|. IOUT > 0 flows from OUT to IN.
To ensure stability at no load conditions, a current from the feedback resistive network equal to or greater than 5 μA is required.
IFB > 0 flows into the device.
CFF refers to a feed-forward capacitor connected to the FB and OUT pins.

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PARAMETRIC MEASUREMENT INFORMATIONTYPICAL APPLICATION CIRCUIT
VIN

OUT

IN
CIN
10 mF

CNR/SS
1 mF

EN

TPS7A3301

NR/SS

CFF
10 nF

FB
GND

VOUT = -15 V

R1
1.24 MW

Where:
COUT
47 mF

R2
105 kWVOUT³ 5 mA, andR1 + R2
R1 = R2

VOUT
-1
VREF

Maximize PSRR Performance and Minimize RMS NoisePIN CONFIGURATIONSKC PACKAGE
TO-220-7(TOP VIEW)

OUT

NC

NC

NC

IN

20

19

18

17

16

RGW PACKAGE
5-mm × 5-mm QFN-20(TOP VIEW)

OUT

1

15

IN

NC

2

14

NR/SS

FB

3

13

EN

NC

4

12

NC

NC

5

11

NC

GND

6

7

8

9

10

GND

NC

NC

NC

EN
IN
NC FB
NR/SS GND OUT

NC

1 2 3 4 5 6 7

PIN DESCRIPTIONS
NO.
NAME

RGW (1)DESCRIPTION

EN

1

13

This pin turns the regulator on or off. If VEN ≥ V+EN_HI or VEN ≤ V–EN_HI, the regulator is enabled.
If V+EN_LO ≥ VEN ≥ V–EN_LO, the regulator is disabled. The EN pin can be connected to IN, if not used. |VEN| ≤ |VIN|.

FB

7

3

This pin is the input to the control-loop error amplifier. It is used to set the output voltage of the device. It is
recommended to connect a 0.01-µF capacitor from FB to OUT (as close to the device as possible) to maximize ac
performance.

GND

4

7

GroundIN

3

15, 16NC

52, 4-6, 8-12,
17-19

NR/SS

2

14

Noise reduction pin. A capacitor connected from this pin to GND controls the soft-start function and allows RMS noise to
be reduced to very low levels. It is recommended to connect a 1-µF capacitor from NR/SS to GND (as close to thedevice as possible) to bypass the noise generated by the internal bandgap and maximize ac performance.

OUT

6

1, 20

Regulator output. A capacitor greater than or equal to 10 µF must be tied from this pin to ground to assure stability. It is
recommended to connect a 47-µF ceramic capacitor from OUT to GND (as close to the device as possible) to maximize
ac performance.

Tab

Tab

—

TAB is internally connected to GND. An external heatsink can be installed to provide additional thermal performance.

(1)
4

KC

Input supply. A capacitor greater than or equal to 10 nF must be tied from this pin to ground to assure stability. It is
recommended to connect a 10-µF capacitor from IN to GND (as close to the device as possible) to reduce circuit
sensitivity to printed-circuit-board (PCB) layout, especially when long input traces or high source impedances areencountered.
This pin can be left open or tied to any voltage between GND and IN.

RGW is a product-preview device.
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SBVS169C – DECEMBER 2011 – REVISED FEBRUARY 2013

FUNCTIONAL BLOCK DIAGRAM

GND

EN

EnableFB
Bandgap
NR/SS
UVLO
OUT
Error
Amp

Pass
DeviceThermalShutdown
Current
Limit

IN

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TYPICAL CHARACTERISTICSAt TJ = –40°C to +125°C, |VIN| = |VOUT(NOM)| + 1.0 V or |VIN| = 3.0 V (whichever is greater), VEN = VIN, IOUT = 1 mA, CIN = 22 μF,
COUT = 22 μF, CNR/SS = 0 nF, and the FB pin tied to OUT, unless otherwise noted.
FEEDBACK VOLTAGE vs INPUT VOLTAGE

FEEDBACK CURRENT vs TEMPERATURE−1.167100
9080−1.172

IFB (nA)

VFB (V)70−1.177

60
50
40
30

−1.182− 40°C+ 0°C+ 25°C−1.187
−40

−35

−30

−25
−20
−15
Input Voltage (V)20+ 85°C+ 125°C
−10

−5

10
0
−40 −25 −100

520 35 50 65
Temperature (°C)

Figure 1.

110 125

GROUND CURRENT vs INPUT VOLTAGE
10

5 µA
10 mA
500 mA
1000 mA− 40°C0°C+ 25°C+ 85°C+ 125°C

98

IGND (mA)

7
IGND (mA)95

Figure 2.

GROUND CURRENT vs INPUT VOLTAGE
10

80

1

6
5
4
3
2
1

TJ = +25°C
0.1
−30

−27

−24

−21

−18 −15 −12
Input Voltage (V)

−9

−6

−3

0
−30

0

IOUT = 500mA
−27

−24

Figure 3.
GROUND CURRENT vs OUTPUT CURRENT

−6

−3

0

ENABLE CURRENT vs ENABLE VOLTAGE
800
600
400
IEN (nA)

IGND (mA)−91000− 40°C0°C+ 25°C+ 85°C+ 125°C

1

200
0
−200
−400
−600
−800

0.1

1
10
Output Current (mA)

Figure 5.

6−18 −15 −12
Input Voltage (V)Figure 4.

10

0.1
0.01

−21

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100

1000

−1000
−35

− 40°C0°C+ 25°C+ 85°C+ 125°C−30−25−20 −15 −10−5Input Voltage (V)

0

5

10

Figure 6.

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SBVS169C – DECEMBER 2011 – REVISED FEBRUARY 2013

TYPICAL CHARACTERISTICS (continued)
At TJ = –40°C to +125°C, |VIN| = |VOUT(NOM)| + 1.0 V or |VIN| = 3.0 V (whichever is greater), VEN = VIN, IOUT = 1 mA, CIN = 22 μF,
COUT = 22 μF, CNR/SS = 0 nF, and the FB pin tied to OUT, unless otherwise noted.
QUIESCENT CURRENT vs INPUT VOLTAGE

SHUTDOWN CURRENT vs INPUT VOLTAGE

500

50
IOUT = 0µA− 40°C+ 0°C+ 25°C+ 105°C+ 125°C

40
35

300

ISHDN (µA)

IQ (µA)400− 40°C+ 0°C+ 25°C+ 105°C+ 125°C

45

200

30
25
20
15

100

10
5

0
−40

−35

−30

−25
−20
−15
Input Voltage (V)

−10

−5

0
−40

0

−35

−30

−25
−20
−15
Input Voltage (V)Figure 7.
DROPOUT VOLTAGE vs OUTPUT CURRENT

0

DROPOUT VOLTAGE vs TEMPERATURE
1000− 40°C0°C+ 25°C+ 85°C+ 125°C

900
800
700

900
800
700

600

VDO (mV)VDO (mV)−5

Figure 8.

1000

500
400

500
400
300

200

200

100

100
0

100

200

300

400 500 600 700
Output Current (mA)

800

50mA
200mA
400mA
800mA
1000mA

600

300

0

−10

0
−40 −25 −10

900 1000

5Figure 9.

20 35 50 65
Temperature (°C)

8095110 125

Figure 10.

ENABLE THRESHOLD VOLTAGE vs TEMPERATURE

LINE REGULATION

2.5

4

2

− 40°C0°C+ 25°C

3

Enable Threshold Positive

1.5+ 85°C+ 125°C

2
VOUT(NOM) (%)

VEN (V)

1
0.5
0

OFF

−0.5

1
0
−1

−1
−2
−1.5
−2
−2.5
−40 −25 −10−3Enable Threshold Negative
5

20 35 50 65
Temperature (°C)

Figure 11.

Copyright © 2011–2013, Texas Instruments Incorporated

80

95

110 125

−4
−40

−35

−30

−25
−20
−15
Input Voltage (V)

−10

−5

0

Figure 12.

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TYPICAL CHARACTERISTICS (continued)
At TJ = –40°C to +125°C, |VIN| = |VOUT(NOM)| + 1.0 V or |VIN| = 3.0 V (whichever is greater), VEN = VIN, IOUT = 1 mA, CIN = 22 μF,
COUT = 22 μF, CNR/SS = 0 nF, and the FB pin tied to OUT, unless otherwise noted.
LOAD REGULATIONPOWER-SUPPLY REJECTION RATIO vs COUT

4100
− 40°C+ 0°C+ 25°C3+ 85°C+ 125°C

IOUT = 1A
CNR = 10nF

90
80

2
PSRR (dB)

VOUT(NOM) (%)

70
1
0
−1

60
50
40
30

COUT = 10µF
COUT = 22µF
COUT = 47µF
COUT = 100µF

−2
20
−3
−4

10
0

100

200

300

400 500 600 700
Output Current (mA)

800

0900 1000

10

100

1k

Figure 13.
POWER-SUPPLY REJECTION RATIO vs CNR/SS

POWER-SUPPLY REJECTION RATIO vs CFF

IOUT = 1A
COUT = 22µF

80

70

70
PSRR (dB)

PSRR (dB)

80

60
50
40

VOUT = −5V
IOUT = 1A
COUT = 22µF
CNR SS = 10nF

90

30

60
50
40
30

20

20
CNR SS = 0nF
CNR SS = 10nF

10
10

100

1k

CFF = 0nF
CFF = 10nF

10
10k
100k
Frequency (Hz)

1M

0

10M

10

100

1k

Figure 15.

1M

10M

POWER-SUPPLY REJECTION RATIO vs VOUT

110

100

100

90

90

80

80

IOUT = 1A
COUT = 22µF

70

70

PSRR (dB)

PSRR (dB)10k
100kFrequency (Hz)Figure 16.

POWER-SUPPLY REJECTION RATIO vs IOUT

60
50
40
30

10
10

100

1k

60
50
40
30

IOUT = 1mA
IOUT = 200mA
IOUT = 500mA
IOUT = 1A

20

20
COUT = 22µF
CNR = 10nF
10k
100k
Frequency (Hz)Figure 17.

8

10M

100

90

0

1M

Figure 14.

100

0

10k
100k
Frequency (Hz)Submit Documentation Feedback

1M

10M

VOUT = −1.171V
VOUT = −5V

10
0

10

100

1k

10k
100k
Frequency (Hz)

1M

10M

Figure 18.

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SBVS169C – DECEMBER 2011 – REVISED FEBRUARY 2013

TYPICAL CHARACTERISTICS (continued)
At TJ = –40°C to +125°C, |VIN| = |VOUT(NOM)| + 1.0 V or |VIN| = 3.0 V (whichever is greater), VEN = VIN, IOUT = 1 mA, CIN = 22 μF,
COUT = 22 μF, CNR/SS = 0 nF, and the FB pin tied to OUT, unless otherwise noted.
OUTPUT SPECTRAL NOISE DENSITY vs OUTPUTCURRENT

POWER-SUPPLY REJECTION RATIO vs VDO

10110
VDO = 1VVDO = 750mVVDO = 500mV

100
90

IOUT = 1mA, VNOISE = 16.26µVRMS
IOUT = 1A, VNOISE = 16.48µVRMS

VDO = 350mVVDO = 300mV

Noise (µV/ Hz)

PSRR (dB)

80
70
60
50
40

1

0.1

30

10
0

COUT = 22µF
CNR SS = 10nF
BWRMSNOISE [10Hz, 100kHz]

IOUT = 1A
CNR = 10nF
COUT = 22µF

20

10

100

1k

10k
100k
Frequency (Hz)

1M

0.01

10M

10

100

Figure 19.
OUTPUT SPECTRAL NOISE DENSITY vs CNR/SSOUTPUT SPECTRAL NOISE DENSITY vs VOUT(NOM)

Noise (µV/ Hz)

Noise (µV/ Hz)

VOUT = −1.171V, VNOISE = 16.48µVRMS
VOUT = −5V, VNOISE = 37µVRMS

1

0.1

1

0.1
IOUT = 1A
COUT = 22µF
CNR SS = 10nF
BWRMSNOISE [10Hz, 100kHz]

COUT = 22µF
BWRMSNOISE [10Hz, 100kHz]
100

1k
10k
Frequency (Hz)

100k

1M

0.01

10

100

1k
10k
Frequency (Hz)Figure 21.

Figure 22.

LOAD TRANSIENT

LOAD TRANSIENTIOUT = 1 mA to 500 mA
VIN = 16 V
VOUT = 15 V

VOUT (100 mV/div)

10

IOUT (500 mA/div)

VOUT (100 mV/div)

1M

10
CNR SS = 0nF, VNOISE = 78µVRMS
CNR SS = 10nF, VNOISE = 16µVRMS

IOUT (500 mA/div)

100k

Figure 20.

10

0.01

1k
10k
Frequency (Hz)1M

IOUT = 500 mA to 1 mA
VIN = 16 V
VOUT = 15 V

Time (100 ms/div)

Time (100 ms/div)

Figure 23.

Figure 24.

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100k

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TYPICAL CHARACTERISTICS (continued)
At TJ = –40°C to +125°C, |VIN| = |VOUT(NOM)| + 1.0 V or |VIN| = 3.0 V (whichever is greater), VEN = VIN, IOUT = 1 mA, CIN = 22 μF,
COUT = 22 μF, CNR/SS = 0 nF, and the FB pin tied to OUT, unless otherwise noted.

VOUT (100 mV/div)

VIN = -16 V to -26 V
VOUT = 15 V
IOUT = 500 mA

VIN (10 V/div)

LINE TRANSIENT

VIN = -26 V to -16 V
VOUT = 15 V
IOUT = 500 mA

VOUT (100 mV/div)

VIN (10 V/div)

LINE TRANSIENT

Time (500 ms/div)

Time (500 ms/div)

Figure 25.

Figure 26.
CAPACITOR-PROGRAMMABLE SOFT-STARTVOUT (5 V/div)

VIN (10 V/div)

CSS = 1 mF

Time (20 ms/div)

Figure 27.

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THEORY OF OPERATIONGENERAL DESCRIPTIONThe TPS7A33 belongs to a family of new-generation linear regulators that use an innovative bipolar process toachieve ultralow-noise and very high PSRR levels at a wide input voltage and current range. These features,combined with the external heatsink-capable, high thermal performance TO-220 package, make this device ideal
for high-performance analog applications.

ADJUSTABLE OPERATIONThe TPS7A3301 has an output voltage range of –1.182 V to –33 V. The nominal output voltage of the device isset by two external resistors, as shown in Figure 28.
VIN

OUT

IN
CIN
10 mF

EN

GND

VOUT = -15 V

R1
1.24 MWFBTPS7A3301

NR/SS

CNR/SS
1 mF

CFF
10 nF

R2
105 kW

Where:
COUT
47 mF

VOUT
³ 5 mA, andR1 + R2
R1 = R2

VOUT
-1
VREF

Figure 28. Adjustable Operation for Maximum AC Performance
R1 and R2 can be calculated for any output voltage range using Equation 1. To ensure stability under no loadconditions at VOUT > VREF, this resistive network must provide a current equal to or greater than 5 μA.
VOUT
VOUT
³ 5 mA
R1 = R2- 1 , where
R1 + R2
VREF(1)
If greater voltage accuracy is required, take into account the output voltage offset contributions because of the
feedback pin current and use 0.1% tolerance resistors.
Table 1 shows the resistor combination to achieve a few of the most common rails using commercially-available,
0.1%-tolerance resistors to maximize nominal voltage accuracy while abiding to the formula shown in Equation 1:
Table 1. Suggested Resistors for Common Voltage Rails
VOUT

R1

R2

VOUT/(R1+R2)

NOMINAL ACCURACY–1.171 V

0Ω

∞

0 μA

±1.5%

–1.8 V76.8 kΩ

143 kΩ

8.18 μA±(1.5% + 0.08%)–3.3 V200 kΩ

110 kΩ

10.64 μA±(1.5% + 0.13%)–5 V

332 kΩ

102 kΩ

11.48 μA±(1.5% + 0.50%)–10 V

1.62 MΩ

215 kΩ

5.44 μA±(1.5% + 0.23%)–12 V

1.5 MΩ

162 kΩ

7.22 μA±(1.5% + 0.29%)–15 V

1.24 MΩ

105 kΩ

11.15 μA±(1.5% + 0.18%)–18 V

3.09 MΩ

215 kΩ

5.44 μA±(1.5% + 0.19%)–24 V

1.15 MΩ

59 kΩ

19.84 μA±(1.5% + 0.21%)

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ENABLE PIN OPERATIONThe TPS7A33 provides a dual-polarity enable pin (EN) that turns on the regulator when |VEN| > 2.0 V, whether
the voltage is positive or negative, as shown in Figure 29.
This functionality allows for different system power management topologies; for example:• Connecting the EN pin directly to a negative voltage, such as VIN, or• Connecting the EN pin directly to a positive voltage, such as the output of digital logic circuitry.

VOUT
VEN

VIN

Time (20ms/div)

Figure 29. Enable Pin Positive/Negative Threshold

CAPACITOR RECOMMENDATIONS
Low equivalent series resistance (ESR) capacitors should be used for the input, output, noise reduction, andbypass capacitors. Ceramic capacitors with X7R and X5R dielectrics are preferred. These dielectrics offer morestable characteristics. Ceramic X7R capacitors offer improved over-temperature performance, while ceramic X5R
capacitors are the most cost-effective and are available in higher values.
Note that high-ESR capacitors may degrade PSRR.

INPUT AND OUTPUT CAPACITOR REQUIREMENTS
The TPS7A33 family of negative, high-voltage linear regulators achieve stability with a minimum input and output
capacitance of 10 μF; however, it is highly recommended to use a 47-μF capacitor to maximize ac performance.

NOISE REDUCTION AND FEED-FORWARD CAPACITOR REQUIREMENTS
Although the noise-reduction (CNR/SS) and feed-forward (CFF) capacitors are not needed to achieve stability, it ishighly recommended to use a 0.01-μF feed-forward capacitor and a 1-μF noise-reduction capacitor to minimize
noise and maximize ac performance.

MAXIMUM AC PERFORMANCE
In order to maximize noise and PSRR performance, it is recommended to include 47-μF or higher input andoutput capacitors, 1-μF noise-reduction capacitors, and 0.01-μF feed-forward capacitors, as shown in Figure 28.
The solution shown delivers minimum noise levels of 16 μVRMS and power-supply rejection levels above 55 dBfrom 10 Hz to 1 MHz; see Figure 19.

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OUTPUT NOISE
The TPS7A33 provides low output noise when a noise-reduction capacitor (CNR/SS) is used.
The noise-reduction capacitor serves as a filter for the internal reference. By using a 1-μF noise reduction
capacitor, the output noise is reduced by almost 80% (from 80 μVRMS to 17 μVRMS); see Figure 21.
The TPS7A33 low output voltage noise makes it an ideal solution for powering noise-sensitive circuitry.

POWER-SUPPLY REJECTION
The 1-μF noise-reduction capacitor greatly improves TPS7A33 power-supply rejection, achieving up to 10 dB of
additional power-supply rejection for frequencies between 140 Hz and 500 KHz.
Additionally, ac performance can be maximized by adding a 0.01-μF feed-forward capacitor (CFF) from the FB pin
to the OUT pin. This capacitor greatly improves power-supply rejection at lower frequencies, for the band from100 Hz to 100 kHz; see Figure 15.
The very-high power-supply rejection of the TPS7A33 makes it a good choice for powering high-performance
analog circuitry, such as operational amplifiers, ADCs, DACS, and audio amplifiers.

TRANSIENT RESPONSE
As with any regulator, increasing the size of the output capacitor reduces over/undershoot magnitude, but
increases duration of the transient response.

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APPLICATION INFORMATIONPOWER FOR PRECISION ANALOG
One of the primary TPS7A33 applications is to provide ultralow-noise voltage rails to high-performance analog
circuitry in order to maximize system accuracy and precision.
The TPS7A33 family of negative, high-voltage linear regulators provides ultralow noise, positive and negative
voltage rails to high-performance analog circuitry such as operational amplifiers, ADCs, DACs, and audio
amplifiers.
Because of the ultralow noise levels at high voltages, analog circuitry with high-voltage input supplies can beused. This characteristic allows for high-performance analog solutions to optimize the voltage range, thus
maximizing system accuracy.

POST DC-DC CONVERTER FILTERING
Most of the time, the voltage rails available in a system do not match the voltage specifications demanded by
one or more of its circuits; these rails must be stepped up or down, depending on specific voltage requirements.
DC-DC converters are the preferred solution to stepping up or down a voltage rail when current consumption is
not negligible. They offer high efficiency with minimum heat generation, but they have one primary disadvantage:
they introduce a high-frequency component, and the associated harmonics, on top of the dc output signal.
If not filtered properly, this high-frequency component degrades analog circuitry performance, reducing overallsystem accuracy and precision.
The TPS7A33 offers a wide-bandwidth, very-high power-supply rejection ratio. This specification makes it ideal
for post dc-dc converter filtering, as shown in Figure 30. It is highly recommended to use the maximum
performance schematic shown in Figure 28. Also, verify that the fundamental frequency (and its first harmonic, if
possible) is within the bandwidth of the regulator PSRR, shown in Figure 16.

+18 V

IN

OUT

+15 V

TPS7A47
+LDO
EN
GND

-18 V

IN

OUT

TPS7A33
-LDO
EN
GND

-15 V

EVM

Figure 30. Post DC-DC Converter Regulation to High-Performance Analog Circuitry

AUDIO APPLICATIONS
Audio applications are extremely sensitive to any distortion and noise in the audio band from 20 Hz to 20 kHz.
This stringent requirement demands clean voltage rails to power critical high-performance audio systems.
The very-high power-supply rejection ratio (> 60 dB) and low noise at the audio band of the TPS7A33 maximize
performance for audio applications; see Figure 16.

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LAYOUT
POWER DISSIPATION
The primary TPS7A33 application is to provide ultralow noise voltage rails to high-performance analog circuitry inorder to maximize system accuracy and precision. The high-current and high-voltage characteristics of thisregulator means that, often enough, high power (heat) is dissipated from the device itself. This heat, if dissipatedinto the PCB (as is the case with SMT packages), creates a temperature gradient in the surrounding area thatcauses nearby components to react to this temperature change (drift). In high-performance systems, such drift
may degrade overall system accuracy and precision.
Compared to surface-mount packages, the TO-220 (KC) package allows for an external heatsink to be used tomaximize thermal performance and keep heat from dissipating into the PCB.
Power dissipation depends on input voltage and load conditions. Power dissipation (PD) is equal to the product of
the output current times the voltage drop across the output pass element, as shown in Equation 2:
PD = (VIN - VOUT) IOUT
(2)

THERMAL PERFORMANCE AND HEATSINK SELECTION
Heat flows from the device to the ambient air through many paths, each of which represents resistance to theheat flow; this is called thermal resistance.
The total thermal resistance of a system is defined by: θJA = (TJ – TA)/PD; where: θJA is the thermal resistance (in°C/W), TJ is the allowable juntion temperature of the device (in °C), TA is the maximum temperature of theambient cooling air (in °C), and PD is the amount of power (heat) dissipated by the device (in W).
Whenever a heatsink is installed, the total thermal resistance (θJA) is the sum of all the individual resistancesfrom the device, going through its case and heatsink to the ambient cooling air (θJA = θJC + θCS + θSA).
Reallistically, only two resistances can be controlled: θCS and θSA. Therefore, for a device with a known θJC, θCS
and θSA become the main design variables in selecting a heat sink.
The thermal interface between the case and the heat sink (θCS) is controlled by selecting the correct heatconducting material. Once the θCS is selected, the required thermal resistance from the heatsink to ambient iscalculated by the following equation: θSA = [(TJ – TA)/PD] – [θJC+ θCS]. This information allows the the mostappropriate heatsink to be selected for any particular application.

PACKAGE MOUNTING
The TO-220 (KC) 7-lead, straight-formed package lead spacing poses a challenge when creating a suitable PCB
footprint without bending the leads. Component forming pliers, such as Excelta's Q-6482, can be used tomanually bend the package leads into a 7-lead stagger pattern with increased lead spacing that can be moreeasily used.
The TPS7A33 evaluation board layout can be used as a guideline on suitable PCB footprints, available atwww.ti.com

BOARD LAYOUT RECOMMENDATIONS TO IMPROVE PSRR AND NOISE PERFORMANCETo improve ac performance such as PSRR, output noise, and transient response, it is recommended that theboard be designed with separate planes for IN, OUT, and GND. The IN and OUT planes should be isolated fromeach other by a GND plane section. In addition, the ground connection for the output capacitor should connect
directly to the GND pin of the device.
Equivalent series inductance (ESL) and equivalent series resistance (ESR) must be minimized in order tomaximize performance and ensure stability. Every capacitor (CIN, COUT, CNR/SS, CFF) must be placed as close as
possible to the device and on the same side of the printed circuit board (PCB) as the regulator itself.
Do not place any of the capacitors on the opposite side of the PCB from where the regulator is installed. The useof vias and long traces is strongly discouraged because they may impact system performance negatively andeven cause instability.
If possible, and to ensure the maximum performance specified in this product datasheet, use the same layout
pattern used for the TPS7A33 evaluation board, available at www.ti.com.

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THERMAL PROTECTION
Thermal protection disables the output when the junction temperature rises to approximately +170°C, allowing
the device to cool. When the junction temperature cools to approximately +150°C, the output circuitry is enabled.
Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may
cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage as a result ofoverheating.
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate
heatsink. For reliable operation, junction temperature should be limited to a maximum of +125°C. To estimate themargin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal
protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection should
trigger at least +35°C above the maximum expected ambient condition of your particular application. Thisconfiguration produces a worst-case junction temperature of +125°C at the highest expected ambient
temperature and worst-case load.
The internal protection circuitry of the TPS7A33 has been designed to protect against overload conditions. It was
not intended to replace proper heatsinking. Continuously running the TPS7A33 into thermal shutdown degrades
device reliability.

SUGGESTED LAYOUT AND SCHEMATIC
Layout is a critical part of good power-supply design. There are several signal paths that conduct fast-changing
currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade
the power-supply performance. To help eliminate these problems, the IN pin should be bypassed to ground witha low ESR ceramic bypass capacitor with a X5R or X7R dielectric.
It may be possible to obtain acceptable performance with alternative PCB layouts; however, the layout shown in
Figure 31 and the schematic shown in Figure 32 have been shown to produce good results and are meant as a
guideline.

Figure 31. PCB Layout Example: Top Layer

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Figure 32. PCB Layout Example: Bottom Layer

Figure 33. Schematic for PCB Layout Example

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REVISION HISTORYNOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (March 2012) to Revision C

Page

•

Changed product status from Mixed Status to Production Data .......................................................................................... 1•

Added last paragraph in Description section ........................................................................................................................ 1•

Changed typical application block diagram .......................................................................................................................... 1•

Updated Figure 30 .............................................................................................................................................................. 14

Changes from Revision A (December 2011) to Revision B

Page

•

Changed product status from Production Data to Mixed Status .......................................................................................... 1•

Added RGW pin out drawing ................................................................................................................................................ 1•

Added RGW column to Thermal Information table ............................................................................................................... 2•

Added RGW pin out drawing to Pin Configurations section ................................................................................................. 4•

Added RGW and footnote 1 to Pin Descriptions table ......................................................................................................... 4

Changes from Original (December 2011) to Revision A
•

18

Page

Changed product status from Product Preview to Production Data ..................................................................................... 1

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PACKAGE OPTION ADDENDUM

www.ti.com

12-Nov-2012

PACKAGING INFORMATION
Orderable Device

Status(1)

Package Type Package Pins Package Qty
Drawing

Eco Plan

Lead/Ball Finish(2)

MSL Peak Temp

Samples(3)(Requires Login)

TPS7A3301KC

ACTIVE

TO-220KC

7

50

Pb-Free(RoHS)CU

Level-2-260C-1 YEARTPS7A3301RGWR

ACTIVE

VQFN

RGW

20

3000

Green (RoHS& no Sb/Br)

CU NIPDAU

Level-2-260C-1 YEARTPS7A3301RGWTACTIVE

VQFN

RGW

20

250

Green (RoHS& no Sb/Br)

CU NIPDAU

Level-2-260C-1 YEAR

(1)

The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement thatlead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weightin homogeneous material)(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION
www.ti.com

11-Aug-2012

TAPE AND REEL INFORMATION*All dimensions are nominal

DevicePackage Package Pins
Type Drawing

SPQ

Reel
Reel
A0
Diameter Width (mm)(mm) W1 (mm)TPS7A3301RGWR

VQFN

RGW

20

3000

330.0

12.4

TPS7A3301RGWT

VQFN

RGW

20

250

180.0

12.4

Pack Materials-Page 1

B0
(mm)

K0
(mm)

P1
(mm)

W
Pin1
(mm) Quadrant

5.3

5.3

1.5

8.0

12.0

Q2

5.3

5.3

1.5

8.0

12.0

Q2

PACKAGE MATERIALS INFORMATION
www.ti.com

11-Aug-2012*All dimensions are nominal

DevicePackage Type

Package Drawing

Pins

SPQ

Length (mm)Width (mm)Height (mm)TPS7A3301RGWR

VQFN

RGW

20

3000

367.0

367.0

35.0

TPS7A3301RGWT

VQFN

RGW

20

250

210.0

185.0

35.0

Pack Materials-Page 2

MECHANICAL DATAMSOT010 – OCTOBER 1994

KC (R-PSFM-T7)

PLASTIC FLANGE-MOUNT PACKAGE
0.156 (3,96)
0.146 (3,71)

0.420 (10,67)
0.380 (9,65)

DIA

0.113 (2,87)
0.103 (2,62)0.185 (4,70)
0.175 (4,46)
0.055 (1,40)
0.045 (1,14)

0.147 (3,73)
0.137 (3,48)

0.335 (8,51)
0.325 (8,25)
1.020 (25,91)
1.000 (25,40)
1

70.125 (3,18)(see Note C)

0.030 (0,76)
0.026 (0,66)
0.010 (0,25) M

0.050 (1,27)0.300 (7,62)

0.122 (3,10)0.102 (2,59)
0.025 (0,64)
0.012 (0,30)
4040251 / B 01/95

NOTES: A.
B.
C.
D.
E.

All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Lead dimensions are not controlled within this area.
All lead dimensions apply before solder dip.
The center lead is in electrical contact with the mounting tab.

POST OFFICE BOX 655303• DALLAS, TEXAS 75265

1

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