Omni

ision

Advanced Information
Preliminary Datasheet®

OV7670/OV7171 CMOS VGA (640x480) CAMERACHIPTM with OmniPixel ® Technology
General Description

Applications

The OV7670/OV7171 CAMERACHIPTM is a low voltage

CMOS image sensor that provides the full functionality ofa single-chip VGA camera and image processor in a small
footprint package. The OV7670/OV7171 provides
full-frame, sub-sampled or windowed 8-bit images in awide range of formats, controlled through the Serial
Camera Control Bus (SCCB) interface.
This product has an image array capable of operating at
up to 30 frames per second (fps) in VGA with complete
user control over image quality, formatting and output datatransfer. All required image processing functions,
including exposure control, gamma, white balance, color
saturation, hue control and more, are also programmablethrough the SCCB interface. In addition, OmniVision
CAMERACHIPs use proprietary sensor technology to
improve image quality by reducing or eliminating common
lighting/electrical sources of image contamination, suchas fixed pattern noise (FPN), smearing, blooming, etc., toproduce a clean, fully stable color image.

Pb

Note: The OV7670/OV7171 uses a
lead-free package.

Features
•
•
•
•
•
•

•
•
•
•
•
•
•
•
•

High sensitivity for low-light operation
Low operating voltage for embedded portable apps
Standard SCCB interface compatible with I2C
interface
Supports VGA, CIF, and resolutions lower than CIF
for RGB (GRB 4:2:2, RGB565/555), YUV (4:2:2) andYCbCr (4:2:2) formats
VarioPixel® method for sub-sampling
Automatic image control functions including:
Automatic Exposure Control (AEC), Automatic Gain
Control (AGC), Automatic White Balance (AWB),
Automatic Band Filter (ABF), and AutomaticBlack-Level Calibration (ABLC)
Image quality controls including color saturation,hue, gamma, sharpness (edge enhancement), andanti-blooming
ISP includes noise reduction and defect correction
Supports LED and flash strobe mode
Supports scaling
Lens shading correction
Flicker (50/60 Hz) auto detection
Saturation level auto adjust (UV adjust)Edge enhancement level auto adjust
De-noise level auto adjust

Ordering Information
Product

Package

OV07670-VL2A (Color, lead-free)

24 pin CSP2

OV07171-VL2A (B&W, lead-free)

24 pin CSP2

Version 1.01, July 8, 2005

•
•
•
•

Cellular and Picture Phones
Toys
PC Multimedia
Digital Still Cameras

Key Specifications
Array Element (VGA)
Digital Core
AnalogPower Supply
I/O
ActivePower
Requirements
StandbyOperation
Temperature
Range Stable Image

640 x 480
1.8VDC +10%
2.45V to 3.0V
1.7V to 3.0V
TBD
< 20 µA-30°C to 70°C
0°C to 50°C
• YUV/YCbCr 4:2:2• RGB565/555
Output Formats (8-bit)• GRB 4:2:2• Raw RGB Data
Lens Size 1/6"
Chief Ray Angle 24°
Maximum Image
30 fps for VGA
Transfer Rate
Sensitivity 1.1 V/Lux-sec
S/N Ratio 40 dB
Dynamic Range TBD
Scan Mode Progressive
Electronics Exposure Up to 510:1 (for selected fps)
Pixel Size 3.6 µm x 3.6 µm
Dark Current 12 mV/s at 60°C
Well Capacity 17 K e
Image Area 2.36 mm x 1.76 mm
Package Dimensions 3785 µm x 4235 µm

Figure 1 OV7670/OV7171 Pin Diagram (Top View)

A1

A2

A3

A4

AVDD

SIO_D

SIO_C

D1

D3

B1

B2

B3

B4

B5

PWDN

VREF2

AGND

D0

D2

C1

C2

DVDD

VREF1

D1

D2

VSYNC

HREF

A5

OV7670/OV7171

E1

E2

E3

E4

E5

PCLK

STROBE

XCLK

D7

D5

F1

F2

F3

F4

F5

DOVDD

RESET

DOGND

D6

D4

Proprietary to OmniVision Technologies

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OV7670/OV7171

CMOS VGA (OmniPixel®) CAMERACHIP™

Omni

ision

Functional Description
Figure 2 shows the functional block diagram of the OV7670/OV7171 image sensor. The OV7670/OV7171 includes:•
Image Sensor Array (total array of 656 x 488 pixels, with active pixels 640 x 480 in YUV mode)•
Analog Signal Processor•
A/D Converters•
Test Pattern Generator•
Digital Signal Processor (DSP)•
Image Scaler•
Timing Generator•
Digital Video Port•SCCB Interface•
LED and Strobe Flash Control Output

Figure 2 Functional Block Diagram

A/D

R
50/60 HzAuto
DetectB

Row SelectColumn Sense Amp

Clock

Buffer

DSP

Image

Test
Pattern
Generator

G
AnalogProcessing

BufferScaler(Lens shading
correction,
de-noise, white/black pixel
correction, auto
white balance,
etc.)

FIFO

Video
Port
D[7:0]

Exposure/Gain
DetectImage Array(656 x 488)
Registers

SCCB
InterfaceVideo Timing Generator
Exposure/GainControl

XCLK

2STROBE HREF

PCLK

VSYNC RESET

Proprietary to OmniVision Technologies

PWDN

SIO_C

SIO_D

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Functional Description

Image Sensor Array

Test Pattern Generator

The OV7670/OV7171 sensor has an image array of
656 x 488 pixels for a total of 320,128 pixels, of which
640 x 480 pixels are active (307,200 pixels). Figure 3
shows a cross-section of the image sensor array.

The Test Pattern Generator features the following:•
8-bar color bar pattern•
Fade-to-gray color bar pattern•
Shift "1" in output pin

Figure 3 Image Sensor Array
Microlens
Glass

Blue

Green

Red

Timing Generator
In general, the timing generator controls the following
functions:•
Array control and frame generation•
Internal timing signal generation and distribution•
Frame rate timing•
Automatic Exposure Control (AEC)•
External timing outputs (VSYNC, HREF/HSYNC, and
PCLK)

Analog Signal Processor
This block performs all analog image functions including:•
Automatic Gain Control (AGC)•
Automatic White Balance (AWB)

A/D Converters
After the Analog Processing block, the bayer pattern Raw
signal is fed to a 10-bit analog-to-digital (A/D) converter
shared by G and BR channels. This A/D converter
operates at speeds up to 12 MHz and is fully synchronous
to the pixel rate (actual conversion rate is related to theframe rate).
In addition to the A/D conversion, this block also has thefollowing functions:•
Digital Black-Level Calibration (BLC)•
Optional U/V channel delay•
Additional A/D range controls
In general, the combination of the A/D Range Multiplierand A/D Range Control sets the A/D range and maximum
value to allow the user to adjust the final image brightness
as a function of the individual application.
Version 1.01, July 8, 2005

Digital Signal Processor (DSP)
This block controls the interpolation from Raw data to
RGB and some image quality control.
•
Edge enhancement (a two-dimensional high passfilter)•Color space converter (can change Raw data to RGB
or YUV/YCbCr)•
RGB matrix to eliminate color cross talk•Hue and saturation control•
White/black pixel correction•
De-noise•Lens shading correction•
Programmable gamma control•
Transfer 10-bit data to 8-bit

Image ScalerThis block controls all output and data formatting required
prior to sending the image out. This block scales
YUV/RGB output from VGA to CIF and almost any size
under CIF.

Digital Video Port
Register bits COM2[1:0] increase IOL/IOH drive current
and can be adjusted as a function of the customer’sloading.

SCCB Interface
The Serial Camera Control Bus (SCCB) interface controls
the CAMERACHIP operation. Refer to OmniVision
Technologies Serial Camera Control Bus (SCCB)Specification for detailed usage of the serial control port.

LED and Strobe Flash Control Output
The OV7670/OV7171 has a Strobe mode that allows it towork with an external flash and LED.

Proprietary to OmniVision Technologies

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Omni

ision

Pin Description

Pin Description
Table 1
Pin Number

Pin Description
Name

Pin Type

Function/Description

A1

AVDD

Power

Analog power supply

A2

SIO_D

I/O

SCCB serial interface data I/O

A3

SIO_C

Input

SCCB serial interface clock input

A4

D1a

Output

YUV/RGB video component output bit[1]A5

D3

Output

YUV/RGB video component output bit[3]

B1

PWDN

Input (0)bPower Down Mode Selection
0: Normal mode
1: Power down mode

B2

VREF2

Reference

Reference voltage - connect to ground using a 0.1 µF capacitor

B3

AGND

Power

Analog ground

B4

D0

Output

YUV/RGB video component output bit[0]B5D2

Output

YUV/RGB video component output bit[2]

C1

DVDD

Power

Power supply (+1.8 VDC) for digital logic core

C2

VREF1

Reference

D1

VSYNC

OutputVertical sync output

D2

HREF

OutputHREF output

E1

PCLK

OutputPixel clock output

E2

STROBE

OutputLED/strobe control output

E3

XCLK

Input

System clock input

E4

D7

Output

YUV/RGB video component output bit[7]E5D5

Output

YUV/RGB video component output bit[5]

F1

DOVDD

Power

Digital power supply for I/O (1.7V ~ 3.0V)

F2

RESET

Input (0)Clears all registers and resets them to their default values.
0: Normal mode
1: Reset mode

F3

DOGND

Power

Digital ground

F4

D6

Output

YUV/RGB video component output bit[6]F5D4

Output

YUV/RGB video component output bit[4]Reference voltage - connect to ground using a 0.1 µF capacitora.

D[7:0] for 8-bit YUV or RGB (D[7] MSB, D[0] LSB)b.

Input (0) represents an internal pull-down resistor.

Version 1.01, July 8, 2005

Proprietary to OmniVision Technologies

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CMOS VGA (OmniPixel®) CAMERACHIP™

Omni

ision

Electrical Characteristics
Table 2Absolute Maximum Ratings

Ambient Storage Temperature-40ºC to +95ºC

Supply Voltages (with respect to Ground)

4.5 V

VDD-C

3V

VDD-IO

4.5 V

All Input/Output Voltages (with respect to Ground)-0.3V to VDD-IO+0.5V

Lead-free Temperature, Surface-mount process

245ºC

ESD Rating, Human Body model

2000V

NOTE:

Exceeding the Absolute Maximum ratings shown above invalidates all AC and DC electrical specifications and may
result in permanent device damage.

Table 3
Symbol5

VDD-A

DC Characteristics (-30°C < TA < 70°C)
Parameter

Condition

Min

Typ

Max

Unit

VDD-A

DC supply voltage – Analog

–

2.45

2.75

3.0

V

VDD-C

DC supply voltage – Digital Core

–

1.62

1.8

1.98

V

VDD-IO

DC supply voltage – I/O power

–

1.7

–

3.0V

V

IDDA

Active (Operating) Current

IDDS-SCCB

Standby Current

IDDS-PWDN

Standby Current

VIH

Input voltage HIGH

VIL

Input voltage LOW

VOH

Output voltage HIGH

VOL

Output voltage LOW

IOH

Output current HIGH

IOL

Output current LOWIL

Input/Output Leakage

See Note a
See Note c
CMOS

10 + 8b

mA

1

mA

10
0.7 x VDD-IO

CMOS

0.9 x VDD-IO

VV

0.1 x VDD-IO
See Note dµA
V

0.3 x VDD-IO

V

8

mA

15

mA

GND to VDD-IO

a.

VDD-A = 2.5V, VDD-C = 1.8V, VDD-IO = 2.5V
IDDA = ∑{IDD-IO+ IDD-C + IDD-A}, fCLK = 24MHz at 30 fps YUV output, no I/O loadingb.

IDD-C = 10mA, IDD-A = 8mA, without loadingc.

VDD-A = 2.5V, VDD-C = 1.8V, VDD-IO = 2.5V
IDDS-SCCB refers to a SCCB-initiated Standby, while IDDS-PWDN refers to a PWDN pin-initiated Standbyd.

Standard Output Loading = 25pF, 1.2KΩ

Proprietary to OmniVision Technologies

20

±1

µA

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ision

Table 4

Electrical Characteristics

Functional and AC Characteristics (-30°C < TA < 70°C)

SymbolParameter

Min

Typ

Max

Unit

Functional Characteristics
A/D

Differential Non-Linearity

+ 1/2

LSB

A/D

Integral Non-Linearity

+1

LSB

AGC

Range

30

dB

Red/Blue Adjustment Range

12dB

Inputs (PWDN, CLK, RESET)
fCLK

Input Clock Frequency

10

24

48

MHz

tCLK

Input Clock Period

21

42

100

ns

tCLK:DC

Clock Duty Cycle

45

50

55

%

tS:RESET

Setting time after software/hardware reset1

ms

tS:REG

Settling time for register change (10 frames required)

300

ms

400

KHz

SCCB Timing (see Figure 4)
fSIO_C

Clock Frequency

tLOW

Clock Low Period

1.3

µs

tHIGH

Clock High Period

600

ns

tAA

SIO_C low to Data Out valid

100

tBUF

Bus free time before new START

1.3

µs

tHD:STASTART condition Hold time

600

ns

tSU:STASTART condition Setup time

600

ns

tHD:DAT

Data-in Hold time0µs

tSU:DAT

Data-in Setup time

100

ns

tSU:STOSTOP condition Setup time

600

ns

tR, tFSCCB Rise/Fall times

tDH

Data-out Hold time

900

300
50

ns

ns
ns

Outputs (VSYNC, HREF, PCLK, and D[7:0] (see Figure 5, Figure 6, Figure 7, Figure 9, and Figure 10)tPDVPCLK[↓] to Data-out ValidtSU

D[7:0] Setup time

15

ns

tHD

D[7:0] Hold time

8

ns

tPHH

PCLK[↓] to HREF[↑]

0

5

ns

tPHL

PCLK[↓] to HREF[↓]

0

5

ns

• VDD:ns

VDD-C = 1.8V, VDD-A = 2.5V, VDD-IO = 2.5V

• Rise/Fall Times: I/O:
AC
Conditions:

55ns, Maximum
SCCB: 300ns, Maximum• Input Capacitance: 10pf
• Output Loading: 25pF, 1.2KΩ to 2.5V
24MHz
• fCLK:

Version 1.01, July 8, 2005

Proprietary to OmniVision Technologies

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CMOS VGA (OmniPixel®) CAMERACHIP™

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ision

Timing Specifications
Figure 4 SCCB Timing DiagramtF

t HIGHtRt HD:DATt SU:DAT

tLOW
SIO_C
t HD:STAtSU:STAtSU:STO

SIO_D
IN
t BUF
tAA

t DH

SIO_D
OUT

Figure 5 Horizontal Timing
tPCLK
PCLK

tPHL

t PHL
(Row Data)

HREF
tSU
t HD
D[7:0]

Last Byte

First Byte

Last BytetPDV

Figure 6 VGA Frame Timing
510 x tLINE
VSYNC
3 x tLINE

480 x tLINE
tLINE = 784 tP
144 tP

17 tLINE

10 tLINE

HREF
640 tP
80 tP

45 tP

19 tP

HSYNC

D[7:0]

Invalid Data

Invalid Data

P0 - P639
Row 0

Row 1

Row 2

Row 479NOTE:
For Raw data, tP = tPCLKFor YUV/RGB, tP = 2 x tPCLK

7

Proprietary to OmniVision Technologies

Version 1.01, July 8, 2005

Omni

ision

Timing Specifications

Figure 7 QVGA Frame Timing
VGA HREF(see Figure 7,
VGA Frame Timing)

QVGA HREF

Figure 8 QQVGA Frame Timing
VGA HREF(see Figure 7,
VGA Frame Timing)

QQVGA HREF
(1 from 4,
120 from 480)

Figure 9 CIF Frame Timing

VGA HREF(see Figure 7,
VGA Frame Timing)

CIF HREF(3 from 5)

Figure 10 QCIF Frame Timing
QVGA HREF(see Figure 7,
QVGA Frame Timing)

QCIF HREF(3 from 5)

Version 1.01, July 8, 2005

Proprietary to OmniVision Technologies

8OV7670/OV7171

CMOS VGA (OmniPixel®) CAMERACHIP™

Omni

ision

Figure 11 RGB 565 Output Timing Diagram
tPCLK
PCLK

tPHL

t PHL
(Row Data)

HREF
tSU
t HD
D[7:0]

Last Byte

First Byte

Last Byte

tPDV

D[7]

First Byte

Second Byte

R4

G2

D[7]

G0

D[6]
D[5]

D[6]
D[5]
D[4]
D[3]

B4
R0

D[2]
D[1]

G5

D[0]

G3

D[4]
D[3]
D[2]
D[1]

B0

D[0]

Figure 12 RGB 555 Output Timing Diagram
tPCLK
PCLK

tPHL

t PHL
(Row Data)

HREF
tSU
t HD
D[7:0]

Last Byte

First Byte

Last BytetPDVFirst Byte

Second Byte

D[7]

X

G2

D[7]

D[6]
D[5]

R4
G0

D[6]
D[5]

B4

D[4]
D[3]

9

D[2]
D[1]

R0
G4

D[0]

G3

Proprietary to OmniVision Technologies

D[4]
D[3]
D[2]
D[1]

B0

D[0]

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ision

Register Set

Register Set
Table 5 provides a list and description of the Device Control registers contained in the OV7670/OV7171. For all register
Enable/Disable bits, ENABLE = 1 and DISABLE = 0. The device slave addresses are 42 for write and 43 for read.

Table 5

Device Control Register List

Address(Hex)

Register
Name

Default
(Hex)

R/W

00

GAIN

00

RW

01

BLUE

80

RW

02

RED

80

RW

Description
AGC – Gain control gain setting
Bit[7:0]: AGC[7:0] (see VREF[7:6] (0x03) for AGC[9:8])• Range: [00] to [FF]AWB – Blue channel gain setting• Range: [00] to [FF]AWB – Red channel gain setting• Range: [00] to [FF]Vertical Frame Control

03

VREF

03

RW

Bit[7:6]:
Bit[5:4]:
Bit[3:2]:
Bit[1:0]:

AGC[9:8] (see GAIN[7:0] (0x00) for AGC[7:0])
Reserved
VREF end low 2 bits (high 8 bits at VSTOP[7:0]
VREF start low 2 bits (high 8 bits at VSTRT[7:0]Common Control 1
Bit[7]:
Bit[6]:
04

COM1

00

RW
Bit[5:2]:
Bit[1:0]:

Reserved
CCIR656 format
0: Disable
1: Enable
Reserved
AEC low 2 LSB (see registers AECHH for AEC[15:10] andAECH for AEC[9:2])

05

BAVE

00

RW

U/B Average Level
Automatically updated based on chip output format

06

GbAVE

00

RW

Y/Gb Average Level
Automatically updated based on chip output format
Exposure Value - AEC MSB 5 bits

07

AECHH

00

RW

08

RAVE

00

RW

Bit[7:6]:
Bit[5:0]:

Reserved
AEC[15:10] (see registers AECH for AEC[9:2] and COM1
for AEC[1:0])

V/R Average Level
Automatically updated based on chip output format
Common Control 2

09

COM2

Version 1.01, July 8, 2005

01

RW

Bit[7:5]:
Bit[4]:
Bit[3:2]:
Bit[1:0]:

Reserved
Soft sleep mode
Reserved
Output Drive Capability
00: 1x01: 2x10: 3x11: 4x

Proprietary to OmniVision Technologies

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OV7670/OV7171
Table 5CMOS VGA (OmniPixel®) CAMERACHIP™

Omni

ision

Device Control Register List (Continued)

Address(Hex)

Register
Name

Default
(Hex)

R/W

0A

PID

76

R

Product ID Number MSB (Read only)

0B

VER

70

R

Product ID Number LSB (Read only)

Description

Common Control 3
Bit[7]:
Bit[6]:
Bit[5]:

Bit[4]:

0C

COM3

00

RW

Bit[3]:

Bit[2]:

Bit[1:0]:

Reserved
Output data MSB and LSB swap
Tri-state option for output clock at power-down period
0: Tri-state at this period
1: No tri-state at this periodTri-state option for output data at power-down period
0: Tri-state at this period
1: No tri-state at this period
Scale enable
0: Disable
1: Enable - if set to a pre-defined format (seeCOM7[5:3]), then COM14[3] must be set to 1 formanual adjustment.
DCW enable
0: Disable
1: Enable - if set to a pre-defined format (seeCOM7[5:3]), then COM14[3] must be set to 1 formanual adjustment.
Reserved

Common Control 4
Bit[7:6]:
Bit[5:4]:
0D

COM4

40

RW

Bit[3:0]:
0E

COM5

01

RW

Reserved
Average option (must be same value as COM17[7:6])
00: Full window
01: 1/2 window
10: 1/4 window
11: 1/4 window
Reserved

Common Control 5
Bit[7:0]:

Reserved

Common Control 6
Bit[7]:

Bit[6]:
0F

COM6

43

RW
Bit[5]:
Bit[4:2]:
Bit[1]:
Bit[0]:

Output of optical black line option
0: Disable HREF at optical black
1: Enable HREF at optical black
BLC input selection
0: Use electrical black line as BLC signal
1: Use optical black line as BLC signal
Digital BLC enable
Reserved
Reset all timing when format changes
Reserved

Exposure Value
10

11

AECH

40

RW

Proprietary to OmniVision Technologies

Bit[7:0]:

AEC[9:2] (see registers AECHH for AEC[15:10] andCOM1 for AEC[1:0])

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ision

Table 5Address(Hex)

Register Set

Device Control Register List (Continued)
Register
Name

Default(Hex)

R/W

Description
Internal ClockBit[7]:

11

CLKRC

80

RW
Bit[6]:
Bit[5:0]:

Digital PLL option
0: Disable double clock option, meaning the maximum
PCLK can be as high as half input clock
1: Enable double clock option, meaning the maximum
PCLK can be as high as input clock
Use external clock directly (no clock pre-scale available)
Internal clock pre-scalarF(internal clock) = F(input clock)/(Bit[5:0]+1)•
Range: [0 0000] to [1 1111]

Common Control 7
Bit[7]:

12

COM7

00

RW

Bit[6]:
Bit[5]:
Bit[4]:
Bit[3]:
Bit[2]:
Bit[1]:

Bit[0]:SCCB Register Reset
0: No change
1: Resets all registers to default values
Reserved
Output format - CIF selection
Output format - QVGA selection
Output format - QCIF selection
Output format - RGB selection (see below)
Color bar
0: Disable
1: Enable
Output format - Raw RGB (see below)

YUV
RGB
Bayer RAW
Processed Bayer RAW

COM7[2]01
0
1COM7[0]001
1Common Control 8
Bit[7]:
Bit[6]:

Bit[5]:
13

COM8

8F

RW

Bit[4:3]:
Bit[2]:
Bit[1]:
Bit[0]:

Version 1.01, July 8, 2005

Enable fast AGC/AEC algorithm
AEC - Step size limit
0: Step size is limited to vertical blank
1: Unlimited step size
Banding filter ON/OFF - In order to turn ON the banding
filter, BD50ST (0x9D) or BD60ST (0x9E) must be set to a
non-zero value.
0: ON
1: OFF
Reserved
AGC Enable
AWB Enable
AEC Enable

Proprietary to OmniVision Technologies

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OV7670/OV7171
Table 5Address(Hex)

CMOS VGA (OmniPixel®) CAMERACHIP™

Omni

ision

Device Control Register List (Continued)
Register
Name

Default(Hex)

R/W

Description
Common Control 9
Bit[7]:
Bit[6:4]:

14

COM9

4A

RW

Bit[3:1]:
Bit[0]:

Reserved
Automatic Gain Ceiling - maximum AGC value
000: 2x001: 4x010
8x011: 16x
100: 32x
101
64x
110: 128x
111: Not allowed
Reserved
Freeze AGC/AEC

Common Control 10
Bit[7]:
Bit[6]:
Bit[5]:

15

COM10

00

RW

Bit[4]:
Bit[3]:
Bit[2]:

Bit[1]:
Bit[0]:

13

Reserved
HREF changes to HSYNC
PCLK output option
0: Free running PCLK
1: PCLK does not toggle during horizontal blank
PCLK reverse
HREF reverse
VSYNC option
0: VSYNC changes on falling edge of PCLK
1: VSYNC changes on rising edge of PCLKVSYNC negative
HSYNC negative

16

RSVD

XX

–

Reserved

17

HSTART

11

RW

Output Format - Horizontal Frame (HREF column) start high 8-bit (low3 bits are at HREF[2:0])

18

HSTOP

61

RW

Output Format - Horizontal Frame (HREF column) end high 8-bit (low3 bits are at HREF[5:3])

19

VSTRT

03

RW

Output Format - Vertical Frame (row) start high 8-bit (low 2 bits are at
VREF[1:0])

1A

VSTOP

7B

RW

Output Format - Vertical Frame (row) end high 8-bit (low 2 bits are at
VREF[3:2])
Data Format - Pixel Delay Select (delays timing of the D[7:0] data relative
to HREF in pixel units)

1B

PSHFT

00

RW

1C

MIDH

7F

R

Manufacturer ID Byte – High

(Read only = 0x7F)

1D

MIDL

A2

R

Manufacturer ID Byte – Low(Read only = 0xA2)

Proprietary to OmniVision Technologies• Range: [00] (no delay) to [FF] (256 pixel delay which accounts forwhole array)

Version 1.01, July 8, 2005

Omni

ision

Table 5Address(Hex)

Register Set

Device Control Register List (Continued)
Register
Name

Default(Hex)

R/W

Description
Mirror/VFlip EnableBit[7:6]:
Bit[5]:

1E

MVFP

00

RW

Bit[4]:

Bit[3]:
Bit[2]:
Bit[1:0]:
1F

LAEC

00

RW

Reserved
Mirror0: Normal image
1: Mirror image
VFlip enable
0: Normal image
1: Vertically flip image
Reserved
Black sun enable
Reserved

Reserved
ADC Control
Bit[7:4]:
Bit[3]:

20

ADCCTR004

RW
Bit[2:0]:

Reserved
ADC range adjustment
0: 1x range
1: 1.5x range
ADC reference adjustment
000: 0.8x
100: 1x111: 1.2x

21

ADCCTR1

02

RW

Bit[7:0]:

Reserved

22

ADCCTR2

01

RW

Bit[7:0]:

Reserved

23

ADCCTR3

80

RW

Bit[7:0]:

Reserved

24

AEW

75

RW

AGC/AEC - Stable Operating Region (Upper Limit)

25

AEB

63

RW

AGC/AEC - Stable Operating Region (Lower Limit)

26

VPT

D4

RW

AGC/AEC Fast Mode Operating Region
Bit[7:4]:
Bit[3:0]:

High nibble of upper limit of fast mode control zone
High nibble of lower limit of fast mode control zone

B Channel Signal Output Bias (effective only when COM6[3] = 1)
Bit[7]:
27

BBIAS

80

RW
Bit[6:0]:

Bias adjustment sign
0: Add bias
1: Subtract bias
Bias value of 10-bit range

Gb Channel Signal Output Bias (effective only when COM6[3] = 1)
Bit[7]:
28

GbBIAS

80

RW
Bit[6:0]:

29

RSVD

XX

–

Bias adjustment sign
0: Add bias
1: Subtract bias
Bias value of 10-bit range

Reserved
Dummy Pixel Insert MSB

2A

EXHCH

Version 1.01, July 8, 2005

00

RW

Bit[7:4]:
Bit[3:2]:
Bit[1:0]:

4 MSB for dummy pixel insert in horizontal direction
HSYNC falling edge delay 2 MSB
HSYNC rising edge delay 2 MSB

Proprietary to OmniVision Technologies

14

OV7670/OV7171
Table 5CMOS VGA (OmniPixel®) CAMERACHIP™

Omni

ision

Device Control Register List (Continued)

Address(Hex)

Register
Name

Default
(Hex)

R/W

2B

EXHCL

00

RW

Description
Dummy Pixel Insert LSB
8 LSB for dummy pixel insert in horizontal direction
R Channel Signal Output Bias (effective only when COM6[3] = 1)
Bit[7]:

2C

RBIAS

80

RW
Bit[6:0]:

Bias adjustment sign
0: Add bias
1: Subtract bias
Bias value of 10-bit range

2D

ADVFL

00

RW

LSB of insert dummy lines in vertical direction (1 bit equals 1 line)

2E

ADVFH

00

RW

MSB of insert dummy lines in vertical direction

2F

YAVE

00

RW

Y/G Channel Average Value

30

HSYST

08

RW

HSYNC Rising Edge Delay (low 8 bits)

31

HSYEN

30

RW

HSYNC Falling Edge Delay (low 8 bits)
HREF Control

32

HREF

80

RW

33

CHLF

08

RW

34

ARBLM

03

RW

35-36

RSVD

XX

–

37

ADC

04

RW

38

ACOM

12

RW

39

OFON

00

RW

Bit[7:6]:
Bit[5:3]:
Bit[2:0]:

HREF edge offset to data output
HREF end 3 LSB (high 8 MSB at register HSTOP)
HREF start 3 LSB (high 8 MSB at register HSTART)Array Current Control
Bit[7:0]:

Reserved

Array Reference Control
Bit[7:0]:

Reserved

Reserved
ADC Control
Bit[7:0]:

Reserved

ADC and Analog Common Mode Control
Bit[7:0]:

Reserved

ADC Offset Control
Bit[7:0]:

ReservedLine Buffer Test Option
Bit[7:6]:
Bit[5]:

Bit[4]:
3A

TSLB

0C

RW
Bit[3]:

Bit[2:0]:15

Proprietary to OmniVision Technologies

Reserved
Negative image enable
0: Normal image
1: Negative image
UV output value
0: Use normal UV output
1: Use fixed UV value set in registers MANU and MANVas UV output instead of chip output
Output sequence (use with register COM13[1] (0x3D))
TSLB[3], COM13[1]:00: Y U Y V
01: Y V Y U
10: U Y V Y
11: V Y U YReserved

Version 1.01, July 8, 2005

Omni

ision

Table 5Address(Hex)

Register Set

Device Control Register List (Continued)
Register
Name

Default(Hex)

R/W

Description
Common Control 11
Bit[7]:

Bit[6:5]:

3B

COM11

00

RW
Bit[4]:

Bit[3]:

Bit[2]:
Bit[1]:
Bit[0]:

Night mode
0: Night mode disable
1: Night mode enable - The frame rate is reduced
automatically while the minimum frame rate is limited
by COM11[6:5]. Also, ADVFH and ADVFL will be
automatically updated.
Minimum frame rate of night mode
00: Same as normal mode frame rate
01: 1/2 of normal mode frame rate
10: 1/4 of normal mode frame rate
11: 1/8 of normal mode frame rate
D56_Auto
0: Disable 50/60 Hz auto detection
1: Enable 50/60 Hz auto detection
Banding filter value select (effective only when
COM11[4] = 0)
0: Select BD60ST[7:0] (0x9E) as Banding Filter Value
1: Select BD50ST[7:0] (0x9D) as Banding Filter ValueReserved
Exposure timing can be less than limit of banding filter
when light is too strong
Reserved

Common Control 12
Bit[7]:
3C

COM12

40

RW
Bit[6:0]:

HREF option
0: No HREF when VSYNC is low
1: Always has HREF
Reserved

Common Control 13
Bit[7]:
Bit[6]:

3D

COM13

99

RW

Bit[5:2]:
Bit[1]:

Bit[0]:

Version 1.01, July 8, 2005

Gamma enable
UV saturation level - UV auto adjustment. Result is saved
in register SATCTR[3:0] (0xC9)
Reserved
UV swap (use with register TSLB[3] (0x3A))
TSLB[3], COM13[1]:00: Y U Y V
01: Y V Y U
10: U Y V Y
11: V Y U YReserved

Proprietary to OmniVision Technologies

16OV7670/OV7171
Table 5Address(Hex)

CMOS VGA (OmniPixel®) CAMERACHIP™

Omni

ision

Device Control Register List (Continued)
Register
Name

Default(Hex)

R/W

Description
Common Control 14
Bit[7:5]:
Bit[4]:

Bit[3]:
3E

COM14

0E

RW
Bit[2:0]:

Reserved
DCW and scaling PCLK enable
0: Normal PCLK
1: DCW and scaling PCLK, controlled by register
COM14[2:0] and SCALING_PCLK_DIV[3:0] (0x73))
Manual scaling enable for pre-defined resolution modes
such as CIF, QCIF, and QVGA
0: Scaling parameter cannot be adjusted manually
1: Scaling parameter can be adjusted manually
PCLK divider (only when COM14[4] = 1)000: Divided by 1
001: Divided by 2
010
Divided by 4011: Divided by 8
100: Divided by 16
101~111: Not allowed

Edge Enhancement Adjustment
3F

EDGE

88

RW

Bit[7:5]:
Bit[4:0]:

Reserved
Edge enhancement factor

Common Control 15
Bit[7:6]:

40

COM15

C0

RW

Bit[5:4]:

Bit[3:0]:17

Proprietary to OmniVision Technologies

Data format - output full range enable
0x: Output range: [10] to [F0]10: Output range: [01] to [FE]11: Output range: [00] to [FF]RGB 555/565 option (must set COM7[2] = 1 andCOM7[0] = 0)
x0: Normal RGB output
01: RGB 565
11: RGB 555
Reserved

Version 1.01, July 8, 2005

Omni

ision

Table 5Address(Hex)

Register Set

Device Control Register List (Continued)
Register
Name

Default(Hex)

R/W

Description
Common Control 16
Bit[7:6]:
Bit[5]:

Bit[4]:
41

COM16

10

RW

Bit[3]:
Bit[2]:
Bit[1]:

Bit[0]:

Reserved
Enable edge enhancement threshold auto-adjustment for
YUV output (result is saved in register EDGE[4:0] (0x3F)
and range is controlled by registers REG75[4:0] (0x75)
and REG76[4:0] (0x76))
0: Disable
1: Enable
De-noise threshold auto-adjustment (result is saved inregister DNSTH (0x4C) and range is controlled by register
REG77[7:0] (0x77))
0: Disable
1: Enable
AWB gain enable
Reserved
Color matrix coefficient double option
0: Original matrix
1: Double of original matrix
Reserved

Common Control 17
Bit[7:6]:

42

COM17

08

RW
Bit[5:4]:
Bit[3]:

Bit[2:0]:
43

AWBC1

14

RW

Reserved

44

AWBC2

F0

RW

Reserved

45

AWBC3

45

RW

Reserved

46

AWBC4

61

RW

Reserved

47

AWBC5

51

RW

Reserved

48

AWBC6

79

RW

Reserved

49-4A

RSVD

XX

–

Reserved

AEC window must be the same value as COM4[5:4])
00: Normal
01: 1/2
10: 1/4
11: 1/4
Reserved
DSP color bar enable
0: Disable
1: Enable
Reserved

Register 4B
4B

REG4B

00

RW

4C

DNSTH

00

RW

De-noise Threshold

4D-4E

RSVD

XX

–

Reserved

4F

MTX1

40

RW

Matrix Coefficient 1

50

MTX2

34

RW

Matrix Coefficient 2

Version 1.01, July 8, 2005

Bit[7:1]:
Bit[0]:

Reserved
UV average enable

Proprietary to OmniVision Technologies

18

OV7670/OV7171
Table 5CMOS VGA (OmniPixel®) CAMERACHIP™

Omni

ision

Device Control Register List (Continued)

Address(Hex)

Register
Name

Default
(Hex)

R/W

51

MTX3

0C

RW

Matrix Coefficient 3

52

MTX4

17

RW

Matrix Coefficient 4

53

MTX5

29

RW

Matrix Coefficient 5

54

MTX6

40

RW

Matrix Coefficient 6

55

BRIGHT

00

RW

Brightness Control

56

CONTRAS

40

RW

Contrast Control

57

CONTRASCENTER

80

RW

Contrast Center

Description

Matrix Coefficient Sign for coefficient 5 to 0
Bit[7]:

58

MTXS

1E

RW
Bit[6]:
Bit[5:0]:

Auto contrast center enable
0: Disable, center is set by register
CONTRAS-CENTER (0x57)
1: Enable, register CONTRAS-CENTER is updated
automaticallyReserved
Matrix coefficient sign
0: Plus
1: Minus

59-61

RSVD

XX

–

AWB Control

62

LCC1

00

RW

Lens Correction Option 1

63

LCC2

00

RW

Lens Correction Option 2

64

LCC3

10

RW

Lens Correction Option 3

65

LCC4

80

RW

Lens Correction Option 4
Lens Correction Control

19

Bit[7:3]:
Bit[2]:
Bit[1]:
Bit[0]:

Reserved
Lens correction control selectReserved
Lens correction enable

66

LCC5

00

RW

67

MANU

80

RW

Manual U Value (effective only when register TSLB[4] is high)

68

MANV

80

RW

Manual V Value (effective only when register TSLB[4] is high)Proprietary to OmniVision Technologies

Version 1.01, July 8, 2005

Omni

ision

Table 5Address(Hex)

Register Set

Device Control Register List (Continued)
Register
Name

Default(Hex)

R/W

Description
Fix Gain Control
Bit[7:6]:

Bit[5:4]:

69

GFIX

00

RW
Bit[3:2]:

Bit[1:0]:

6A

GGAIN

00

RW

G Channel AWB GainBit[7:6]:

6B

DBLV

3A

RW

Fix gain for Gr channel
00: 1x01: 1.25x
10: 1.5x
11: 1.75x
Fix gain for Gb channel
00: 1x01: 1.25x
10: 1.5x
11: 1.75x
Fix gain for R channel
00: 1x01: 1.25x
10: 1.5x
11: 1.75x
Fix gain for B channel
00: 1x01: 1.25x
10: 1.5x
11: 1.75xBit[5]:
Bit[4]:

Bit[3:0]:

PLL control
00: Bypass PLL
01: Input clock x4
10: Input clock x8
11: Input clock x16
Reserved
Regulator control
0: Enable internal regulator
1: Bypass internal regulator
Clock divider control for DSP scale control (valid only
when COM14[3] = 1)

6C

AWBCTR302

RW

AWB Control 3

6D

AWBCTR255

RW

AWB Control 2

6E

AWBCTR100

RW

AWB Control 1

6F

AWBCTR09A

RW

AWB Control 0
Bit[7]:70

SCALING_
XSC

4A

RW

Bit[6:0]:

Version 1.01, July 8, 2005

Test_pattern[0] - works with test_pattern[1] test_pattern(SCALING_XSC[7], SCALING_YSC[7]):00: No test output
01: Shifting "1"
10: 8-bar color bar
11: Fade to gray color bar
Horizontal scale factor

Proprietary to OmniVision Technologies

20

OV7670/OV7171
Table 5Address(Hex)

CMOS VGA (OmniPixel®) CAMERACHIP™

Register
Name

Default(Hex)

R/W

Description

SCALING_
YSC

35

RW

Bit[6:0]:
72

73

ision

Device Control Register List (Continued)

Bit[7]:71

Omni

SCALING_
DCWCTRSCALING_
PCLK_DIV

11

00

RW

DCW Control
Bit[7:0]:

DCW control parameter

Bit[7:4]:
Bit[3:0]:

Reserved
Clock divider control for DSP scale control (valid only
when COM14[3] = 1). Should change with COM14[2:0].
0000: Divided by 1
0001: Divided by 20010: Divided by 40011: Divided by 8
0100: Divided by 160101~1111: Not allowedBit[7:5]:
Bit[4]:

Reserved
DG_Manu
0: Digital gain control by VREF[7:6]
1: Digital gain control by REG74[1:0]Reserved
Digital gain manual control
00: Bypass
01: 1x10: 2x11: 4x

RW

74

REG74

00

RW

75

REG75

0F

RW

Test_pattern[1] - works with test_pattern[0] test_pattern(SCALING_XSC[7], SCALING_YSC[7])::00: No test output
01: Shifting "1"
10: 8-bar color bar
11: Fade to gray color bar
Vertical scale factor

Bit[3:2]:
Bit[1:0]:

Register 75
Bit[7:5]:
Bit[4:0]:

Reserved
Edge enhancement lower limit

Register 76
Bit[7]:
Bit[6]:
76

REG76

01

RW
Bit[5]:

Bit[4:0]:

21

Reserved
White pixel correction enable
0: Disable
1: Enable
Black pixel correction enable
0: Disable
1: Enable
Edge enhancement higher limit

Register 77

77

REG77

10

RW

78-79

RSVD

XX

–

Reserved

7A

GAM1

02

RW

Gamma Curve 1st Segment Input End Point 0x010 Output Value

7B

GAM2

07

RW

Gamma Curve 2nd Segment Input End Point 0x020 Output Value

7C

GAM3

1F

RW

Gamma Curve 3rd Segment Input End Point 0x040 Output Value

Proprietary to OmniVision Technologies

Bit[7:0]:

Offset, de-noise range control

Version 1.01, July 8, 2005

Omni

ision

Table 5

Register Set

Device Control Register List (Continued)

Address(Hex)

Register
Name

Default
(Hex)

R/W

7D

GAM4

49

RW

Gamma Curve 4th Segment Input End Point 0x080 Output Value

7E

GAM5

5A

RW

Gamma Curve 5th Segment Input End Point 0x0A0 Output Value

7F

GAM6

6A

RW

Gamma Curve 6th Segment Input End Point 0x0C0 Output Value

80

GAM7

79

RW

Gamma Curve 7th Segment Input End Point 0x0E0 Output Value

89

GAM8

87

RW

Gamma Curve 8th Segment Input End Point 0x100 Output Value

89

GAM9

94

RW

Gamma Curve 9th Segment Input End Point 0x120 Output Value

89

GAM10

9F

RW

Gamma Curve 10th Segment Input End Point 0x140 Output Value

89

GAM11

AF

RW

Gamma Curve 11th Segment Input End Point 0x180 Output Value

86

GAM12

BB

RW

Gamma Curve 12th Segment Input End Point 0x1C0 Output Value

87

GAM13

CF

RW

Gamma Curve 13th Segment Input End Point 0x240 Output Value

88

GAM14

EE

RW

Gamma Curve 14th Segment Input End Point 0x2C0 Output Value

89

GAM15

EE

RW

Gamma Curve 15th Segment Input End Point 0x340 Output Value

8A-91

RSVD

XX

–

Reserved

92

DM_LNL

00

RW

Dummy Line low 8 bits

93

DM_LNH00

RW

Dummy Line high 8 bits

94

LCC6

50

RW

Lens Correction Option 6 (effective only when LCC5[2] is high)

95

LCC7

50

RW

Lens Correction Option 7 (effective only when LCC5[2] is high)

96-9C

RSVD

XX

–

Reserved

9D

BD50ST

99

RW

50 Hz Banding Filter Value(effective only when COM8[5] is high and COM11[3] is high)

9E

BD60ST

7F

RW

60 Hz Banding Filter Value(effective only when COM8[5] is high and COM11[3] is low)XX–

Histogram-based AEC/AGC Control

9F-AB

Description

Register AC
Bit[7]:
Bit[6]:
Bit[5:4]:
AC

STR-OPT

00

RW
Bit[3:2]:
Bit[1:0]:

Strobe enable
R / G / B gain controlled by STR_R (0xAD) / STR_G(0xAE) / STR_B (0xAF) for LED output frame
Xenon mode option
00: 1 line
01: 2 lines
10: 3 lines
11: 4 lines
Reserved
Mode select
00: Xenon
01: LED 1&2
1x: LED 3

AD

STR_R

80

RW

R Gain for LED Output Frame

AE

STR_G

80

RW

G Gain for LED Output Frame

AF

STR_B

80

RW

B Gain for LED Output Frame

Version 1.01, July 8, 2005

Proprietary to OmniVision Technologies

22

OV7670/OV7171
Table 5CMOS VGA (OmniPixel®) CAMERACHIP™

Omni

ision

Device Control Register List (Continued)

Address(Hex)

Register
Name

Default
(Hex)

R/W

B0-B2

RSVD

XX

–

Reserved

B3

THL_ST

80

RW

Digital BLC Target

B4

RSVD

XX

–

Reserved

B5

THL_DLT

04

RW

Digital BLC Stable Range

B6-BD

RSVD

XX

–

Reserved

BE

AD-CHB00

RW

Bit[7]:
Bit[6]:
Bit[5:0]:

Reserved
Sign bit
ADC offset value

BF

AD-CHR00

RW

Bit[7]:
Bit[6]:
Bit[5:0]:

Reserved
Sign bit
ADC offset value

C0

AD-CHGb00

RW

Bit[7]:
Bit[6]:
Bit[5:0]:

Reserved
Sign bit
ADC offset value

C1

AD-CHGr00

RW

Bit[7]:
Bit[6]:
Bit[5:0]:

Reserved
Sign bit
ADC offset value

C2-C8

RSVD

XX

–

Description

Reserved
Saturation Control

C9

SATCTR

C0

RW

Bit[7:4]:
Bit[3:0]:

UV saturation control min
UV saturation control result

NOTE: All other registers are factory-reserved. Please contact OmniVision Technologies for reference register settings.

23

Proprietary to OmniVision Technologies

Version 1.01, July 8, 2005

Omni

ision

Package Specifications

Package Specifications
The OV7670/OV7171 uses a 24-ball Chip Scale Package 2 (CSP2). Refer to Figure 13 for package information, Table 6 forpackage dimensions and Figure 14 for the array center on the chip.

Note: For OVT devices that are lead-free, all part marking letters arelower case. Underlining the last digit of the lot number indicates CSP2 isused.
Figure 13 OV7670/OV7171 Package Specifications
A
1

2

3

S1
4

J1

S2

5

5

3

2

1

A

A

B

B
J2
B

4

C

C

D

D

E

E

wxyz
abcd

F

F

Center of BGA (Die) =Center of the package

Top View (Bumps Down)

Bottom View (Bumps Up)

GlassPart Marking Code:w- OVT Product Versionx- Year the part is assembledy- Month the part is assembledz- Wafer number
abcd - Last four digits of lot number

Die
C3

C2

C

C1

Table 6

Side View

OV7670/OV7171 Package Dimensions
Parameter

SymbolMinimum

NominalMaximum

Unit

Package Body Dimension X

A

3760

3785

3810

µm

Package Body Dimension Y

B

4210

4235

4260

µm

Package Height

C

825

885

945

µm

Ball Height

C1

130

160

190

µm

Package Body Thickness

C2

680

725

770

µm

Thickness of Glass Surface to Wafer

C3

425

445

465

µm

Ball Diameter

D

270

300

330

µm

Total Pin CountN

24

Pin Count X-axis

N1

5

Pin Count Y-axis

N2

6

Pins Pitch X-axis

J1

620

µm

Pins Pitch Y-axis

J2

620

µm

Edge-to-Pin Center Distance Analog X

S1

623

653

683

µm

Edge-to-Pin Center Distance Analog Y

S2

538

568

598

µm

Version 1.01, July 8, 2005

Proprietary to OmniVision Technologies

24

CMOS VGA (OmniPixel®) CAMERACHIP™

OV7670/OV7171

Omni

ision

Sensor Array Center
Figure 14 OV7670/OV7171 Sensor Array Center

A1

A2

A3

A4

A5

2361.6 µm

Package Center(0,0)

1756.8 µm
SensorArray

Array Center(201.8 µm, 486.38 µm)
OV7670/OV7171

TOP VIEWNOTES: 1. This drawing is not to scale and is for reference only.
2. As most optical assemblies invert and mirror the image, the chip is typically mountedwith pins A1 to A5 oriented down on the PCB.

25

Proprietary to OmniVision Technologies

Version 1.01, July 8, 2005

Omni

ision

Package Specifications

IR Reflow Ramp Rate Requirements
OV7670/OV7171 Lead-Free Packaged Devices
Note: For OVT devices that are lead-free, all part marking letters arelower case
Figure 15 IR Reflow Ramp Rate Requirements
300.0

Z1

Z2

Z3

Z4

Z5

Z6

Z7

end

280.0
260.0
240.0
220.0

Temperature (∞C )

200.0
180.0
160.0
140.0
120.0
100.0
80.0
60.0
40.0
20.0
0.0

0.0
-22

0.6

-2

18

38

1.1
58

78

1.6
98

118

2.2
138

158

2.8
178

198

3.3
218

238

3.9

258

278

298

318

338

358 369

Time (sec)
-0.3

-0.1

0.1

0.3

0.5

0.7

0.9

1.1

1.3

1.5

1.7

1.9

2.1

2.3

2.5

2.7

2.9

3.1

3.3

3.5

3.7

3.9

4.1

4.3

4.5

4.7

4.9

Time (min.)Table 7

Reflow Conditions
Condition

Exposure

Average Ramp-up Rate (30°C to 217°C)

Less than 3°C per second> 100°C

Between 330 - 600 seconds> 150°C

At least 210 seconds> 217°C

At least 30 seconds (30 ~ 120 seconds)

Peak Temperature

245°C

Cool-down Rate (Peak to 50°C)

Less than 6°C per second

Time from 30°C to 255°C

No greater than 390 seconds

Version 1.01, July 8, 2005

Proprietary to OmniVision Technologies

26

OV7670/OV7171

CMOS VGA (OmniPixel®) CAMERACHIP™

Omni

ision

Note:
•

All information shown herein is current as of the revision and publication date. Please referto the OmniVision web site (http://www.ovt.com) to obtain the current versions of all
documentation.

•

OmniVision Technologies, Inc. reserves the right to make changes to their products or to
discontinue any product or service without further notice (It is advisable to obtain current productdocumentation prior to placing orders).

•

Reproduction of information in OmniVision product documentation and specifications ispermissible only if reproduction is without alteration and is accompanied by all associatedwarranties, conditions, limitations and notices. In such cases, OmniVision is not responsible
or liable for any information reproduced.

•

This document is provided with no warranties whatsoever, including any warranty ofmerchantability, non-infringement, fitness for any particular purpose, or any warranty
otherwise arising out of any proposal, specification or sample. Furthermore, OmniVision
Technologies Inc. disclaims all liability, including liability for infringement of any proprietary
rights, relating to use of information in this document. No license, expressed or implied, byestoppels or otherwise, to any intellectual property rights is granted herein.

•‘OmniVision’, ‘VarioPixel’, ‘OmniPixel’ and are trademarks of OmniVision Technologies, Inc. Allother trade, product or service names referenced in this release may be trademarks or registeredtrademarks of their respective holders. Third-party brands, names, and trademarks are theproperty of their respective owners.

For further information, please feel free to contact OmniVision at info@ovt.com.

OmniVision Technologies, Inc.
1341 Orleans Drive
Sunnyvale, CA USA(408) 542-3000

27

Proprietary to OmniVision Technologies

Version 1.01, July 8, 2005

OV7670/OV7171

28

CMOS VGA (OmniPixel®) CAMERACHIP™

Proprietary to OmniVision Technologies

Omni

ision

Version 1.01, July 8, 2005

Omni

ision

TM

REVISION CHANGE LIST
Document Title: OV7670 Datasheet

Version: 1.0

DESCRIPTION OF CHANGES
Initial Release

Omni

ision

TM

REVISION CHANGE LIST
Document Title: OV7670 Datasheet

Version: 1.01

DESCRIPTION OF CHANGESThe following changes were made to version 1.0:
• Under LED and Strobe Flash Control Output section on page 3, changed text from “Referto the OmniVision Technologies LED Strobe Support document” to “The OV7670 has aStrobe mode that allows it to work with an external flash and LED”