TN00008
Rev. 7.0 — 9 August 2024

Technical notePower MOSFET frequently
asked questions and answers

Abstract:

This document provides answers to frequently asked questions regarding automotive MOSFET
platforms, devices, functionality and reliability. It is also applicable to non-automotive applications.

Keywords:

TrenchMOS generation 3, generation 6, generation 9, avalanche, ruggedness, linear mode, reliability,
thermal impedance, EMC, ESD, switching, thermal designTN00008

Nexperia

Power MOSFET frequently asked questions and answers

1. Introduction
This technical note provides several important questions regarding the use of MOSFETs and theplatforms required. Although it is focused on automotive applications, the principles can apply toindustrial and consumer applications. It strives to provide clear answers to these questions and thereasoning behind the answers.
This document is intended for guidance only. Any specific questions from customers should be
discussed with Nexperia power MOSFET application engineers.

2. Gate2.1. Q: Why is the VGS rating of Trench 6 automotive logic level
MOSFETs limited to 10 V and can it be increased beyond 10 V?
A: The VGS rating of 10 V given to Trench 6 logic level MOSFETs is driven by our <1 ppm failure
rate targets and was rated to the best industry practices at the time. The ppm failure figures are notgiven in any data sheet nor are they part of AEC-Q101 qualification. In other words, two devices
can both be qualified to AEC-Q101 and still have different ppm failure rate figures.
Methods of defining, characterising and protecting these ratings have improved and there is now
a possibility to operate beyond the given rating of 10 V. This will be a function of time, voltage andtemperature. For further explanation see below; more details are available in Nexperia applicationnote AN90001.
Additional information
There are two key words in the above question that are worth expanding on - “rating” and“logic level”.
Logic level MOSFETs are primarily intended for applications where the drive voltage is 5 V
and thus optimised accordingly. To achieve a fully-on MOSFET and best RDSon performancewith relatively low gate voltages these MOSFETs will need a thinner gate oxide than standardlevel parts which operate with a drive of 10 V VGS. Thinner gate oxides will breakdown at lower
voltages and will have a lower rating than standard level devices, (full details are given in
AN90001, section 5).
However, there are instances where logic level MOSFETs are chosen for non-logic levelapplications. For example, in automotive applications where the battery supply voltage candrop to a level where drive circuits need to operate below 6 V. Therefore, MOSFETs must turn
ON with lower gate voltages than standard level MOSFETs are capable of. Conversely, the
MOSFET gate needs to withstand the nominal battery voltage of approximately 12 V.
Is a logic level MOSFET suitable?
In terms of capability logic level MOSFETs are not expected to suddenly fail as soon as higher
voltages are applied. However, applying higher VGS than the maximum rated voltage willcompromise the <1 ppm failure rate and therefore Nexperia would not consider including theseratings in data sheets.
Nexperia's methodology of removing defectives and reducing early life failures is achieved
through effective screening at production. As a supplier Nexperia is committed to zero defects
and high quality levels. Therefore, the ratings may appear lower than our competitors wherecommitment to quality is possibly not as stringent. Nexperia VGS max ratings are based on
applying 100% max (rated) voltage at 175 °C for 1000 hours with failure rate <1 ppm – for moredetails see: AN90001 section 4.
Designers must consider failure rates figures for logic level MOSFETs when VGS in their data
sheets is rated to ±20 V
A model exists at Nexperia for calculating life failure rates with higher gate voltages against
temperatures. This information can be provided upon request as a calculated figure and will
only be given as a guide.

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2.2. Q: Why is VGS maximum limit of Trench 9 automotive logic level
MOSFETs different to previous generations?
A: The rating is based on meeting AEC-Q101 requirements, as it is with previous generations.
However, Nexperia has developed a new testing methodology which ensures <1 ppm failure rates
over lifetime at the rated VGS. This has been applied to Trench9 and its VGS rating is set to meetthis new requirement.
Additional information
Detailed explanation can be found in AN90001.

2.3. Q: What is the gate oxide capability for a logic level MOSFET(data sheet says only 10 V, will it break at 11 V?)
Logic level MOSFETs are primarily intended for applications where the drive voltage is 5 V andthus optimised accordingly. To achieve a fully-on MOSFET and best RDSon performance withrelatively low gate voltages these MOSFETs will need a thinner gate oxide than standard levelparts which operate with a drive of 10 V VGS at 175 °C . Thinner gate oxides will breakdown atlower voltages and will have a lower rating than standard level devices.
In terms of capability, logic level MOSFETs are not expected to suddenly fail as soon as higher
voltages are applied. However, applying higher VGS than the maximum rated voltage willcompromise the 1 ppm failure rate and therefore Nexperia would not consider including theseratings in data sheets and would not recommend exceeding them

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Power MOSFET frequently asked questions and answers

3. Thermals
3.1. Q: What’s the difference between Rth(j-mb) and Rth(j-amb)?
A: Power MOSFET data sheet provide values for both Rth(j-mb) and Rth(j-amb).
Rth(j-mb) refers to the thermal resistance between the junction and mounting base, for a specificpower profile. Note: some other vendors refer to the mounting base as the “case”. For Nexperia
surface mount devices, “case” usually means the plastic encapsulation of the package and has arelatively high thermal resistance to the junction, see Fig. 1.
mounting basemounting base"case''"case''

Mounting base is the metal bottom and tab; "case" refers to the plastic encapsulation of
the package
Fig. 1.

Package terminology: mounting base and "case"

The thermal heat path between the MOSFET junction to its mounting base is considered as oneof the most important thermal specifications on any data sheet. It is represented by the overall
junction to mounting base thermal resistance which is a value describing the ease with whichheat is conducted along this path due to the different materials which it is going through. In Fig. 2,
a MOSFET depiction is represented with the thermal resistive network between the junction tomounting base. As the MOSFET and its parts are 3 dimensional so is the heat path, thus the 2dimensional resistor network seen below is 3-dimensional in reality. It is important to rememberthat the Rth(j-mb) value encompasses the whole network. Lastly, the parameter describes the steadystate thermal characteristics, thus one should use average power dissipation values in order toobtain the temperatures reached by the MOSFET

[5]

.

Tc

Ti

Tmb

Fig. 2.

aaa-031980

Thermal path junction to mounting base
In contrast Rth(j-amb) refers to the thermal resistance difference from the junction to the ambient. The
junction to ambient is the full thermal path that needs to be considered and is a function of the PCB
design and cooling system too.
The thermal heat path between the MOSFET junction and the ambient encompasses paths within
the MOSFET itself as well as additional ones when a MOSFET is mounted onto a PCB. Hence,heat may spread from the junction towards the mounting base and the case. Afterwards, when theextremities of the MOSFET are reached, the heat will flow into the surroundings via the PCB or
directly from the case. These heat paths are depicted in Fig. 3.

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aaa-031981

a) heat moving from the junction to the mounting base and to the case top and afterwards to the ambient.

aaa-031982b) heat moving from the mounting base to the PCB and through it in order to reach the ambient.
Fig. 3.

Thermal path: junction to ambient

3.2. Q: When comparing Zth curves in some data sheets, there
appear to be some contradictions. From an Rth point of view, theBUK9Y38-100E (Trench generation 6) looks better (lower). However,from a Zth (at less than 100 ms) point of view, the BUK9Y30-75B(Trench generation 3) looks better. The shape of the graphs indicatesthat a more advanced model or measurement was done on the
Trench generation 6 part. Is this assumption correct?
A: The method for setting the Zth curve has changed between the Trench generation 3 parts(2008) and Trench generation 6 (2012). The die size is also different which changes the Zth and Rth
characteristics.
Additional information
The earlier method used empirical models for Zth (1 μs) and Rth, joined by an exponential line.
The latest method uses models for the Zth generated by Computational Fluid Dynamics (CFD)
simulation, verified by measurement.
The dies in the 2 parts have different dimensions and therefore they have different Zth.
The plots depicted in Fig. 4 compare the data sheet curves for the single shot Zth.
There is a good match between the limit lines for both parts. The biggest difference is in theregion 1 ms to 20 ms.
The conclusion from this comparison, is that the Trench generation 3 part is designed to workwithin these Zth limits. The Trench generation 6 part is an excellent alternative that has a very
high probability of working satisfactorily.
It is possible to assess how to rate the Trench generation 3 part using the new rules with amore accurate reflection of its true performance. Fig. 4 shows the new line in comparison withthe two data sheet lines.

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aaa-013060

10

(1)
(2)
(3)

Zth (j-mb)
(K/W)
1

10-1

10-2
10-6

10-5

10-4

10-3

10-2

10-1
1
tp (s)(1) BUK9Y38-100E(2) BUK9Y30-75B(3) BUK9Y30-75B (new test method)
Fig. 4.

Comparison of transient thermal impedance

Although there is a difference in the Rth, it is probably unimportant. In practice, it is the Rth(j-amb) thatis the limiting factor for the design. The Rth of the Printed-Circuit Board (PCB) that is common toboth parts, is dominant.
When considering the old test method with the new one for the BUK9Y30-75B, the other region ofdifference is below 10 μs.
For pulse duration between 1 μs and 2 μs, the temperature rise (or Zth(j-mb)) in the Trench
generation 3 part, is only a half of what the original data sheet curve predicted. The importance of
this factor depends on the application.

3.3. Q: It is understood that the values for thermal resistancelisted in data sheets are based on controlled conditions that do
not apply to typical applications. If this understanding is true, howis the proper thermal resistance/junction temperature accurately
calculated?
A: This understanding is correct. To ensure reliability of the MOSFET, always limit the maximum
junction temperature to 175 °C.
Additional information
It is understood that the typical values for thermal resistance listed in data sheets are
based on controlled conditions that do not apply to typical applications.
Device characterization at a junction temperature of 25 °C is the accepted standard in thesemiconductor industry. It is also most convenient for users to take measurements at thistemperature.
How is the proper thermal resistance calculated?
Only a maximum value of thermal resistance is given on Nexperia MOSFET data sheets. The
typical value is significantly less than the maximum. It is understood that thermal cycling can
induce an increase in Rth(j-mb) over the lifetime of the MOSFET.
A tolerance margin is included in the data sheet maximum Rth(j-mb) value which allows for an
increase over the lifetime of the MOSFET.
For worst case design analysis, always use the maximum value. Maximum Rth(j-mb) given on thedata sheet is evaluated from characterization measurements.
Its value is not dependent on temperature or other environmental conditions.

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Power MOSFET frequently asked questions and answers
How is junction temperature calculated?
MOSFETs usually operate with a junction temperature greater than 25 °C due to temperaturerise caused by the environment and/or power dissipation in the MOSFET.
If MOSFET power dissipation and mounting base temperature (Tmb) are known, MOSFET
junction temperature can be calculated. Use Equation (1), below to determine Tj.

T j = P × R th(j-mb) + Tmb(1)

SPICE thermal models of MOSFETs provide an excellent means of estimating Tj by simulation. It isparticularly useful when MOSFET power dissipation changes with time.

Worked example for a BUK7Y12-40E:
From the data sheet:
Maximum RDSon at 25 °C = 12 mΩ
Maximum RDSon at 175 °C = 23.6 mΩ
Maximum Rth(j-mb) at 2.31 K/W
From the application data:
PWM frequency = 100 Hz
Maximum duty cycle = 50 %Vsupply = 14 V
Rload = 0.7 Ω
Maximum ambient temperature = 85 °C
Maximum PCB temperature = 100 °C
Calculation based on average power, ignoring any temperature fluctuation due to the power
pulsing and also ignoring switching losses at 100 Hz:
Assume that the temperature of the MOSFET is initially 100 °C and its maximum RDSon is
18 mΩ. It is midway between 12 mΩ at 25 °C and 24 mΩ at 175 °C.
2When conducting, the MOSFETs power dissipation I × RDSon is: 20 x 20 x 0.018 = 7.2 W
The duty cycle is 50 %, so the average power dissipation = 7.2 x 0.5 = 3.6 W. It is assumed thatthe switching loss at 100 Hz can be ignored.
The rise of the MOSFET junction temperature, above the mounting base is: 2.31 x 3.6 = 8.3 K.
The maximum MOSFET die temperature in this situation is very safe at: 100 + 8.3 = 108.3 °C
To guarantee that the PCB temperature does not rise above 100 °C in an 85 °C ambient, thethermal resistance between PCB and ambient must be: (100 - 85)/3.6 = 4.2 K/W

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3.4. Q: What effect does changing the device have on Rth(j-amb)?
A: Rth(j-amb) is the thermal resistance of a device from junction to the ambient as shown in Fig. 5,
it is the sum of the thermal resistance from the junction to mounting base Rth(j-mb) and the thermal
resistance from mounting base to the ambient temperature Rth(mb-amb).

Tmb
Tamb

Tj
Rth(j-mb)

Rth(mb-amb)
Rth(j-amb)

Fig. 5.

MOSFET thermal resistance junction to ambient

Rth(j-mb) is in Nexperia’s control (it is a function of the die size and package design, for example
the bigger the die the lower the Rth(j-mb)). For a device with a large die in an LFPAK88 packageRth(j-mb) may be as low as 0.4 K/W and for a device with a small die in LFPAK33 it may be as highas 4 K/W.
However, Rth(mb-amb) is a function of the PCB design and the thermal management scheme and is
not under the control of Nexperia. A good multilayer FR4 design with thermal vias would be around30 - 40 K/W. Nexperia provide application notes such as AN90003 "LFPAK MOSFET thermal
design guide" to aid design.

Worked example for BUK9K6R2-40E and BUK761R6-40E
From the BUK9K6R2-40E data sheet, the Rth(j-mb) is 2.21 K/W.
However, the Rth(mb-amb) is in the control of the customer, i.e. it depends on the PCB design.
Assume the PCB assembly thermal resistance to ambient is 40 K/W.
A. Using a SOT1205 dual LFPAK56 (such as BUK9K6R2-40E)
Rth(j-amb) = Rth(j-mb) + Rth(mb-amb) = 2.21 + 40 = 42.21 K/W
B. Using a device with a larger die will result in a lower Rth(j-mb). For demonstration purposes a max
die D2PAK (BUK761R6-40E) with low Rth(j-mb) is used (0.43 K/W).
Rth(j-amb) = Rth(j-mb) + Rth(mb-amb) = 0.43 + 40 = 40.43 K/W
Since in this example the largest contribution to Rth(j-amb) comes not from the MOSFET but from the
PCB and cooling system,changing the device will have a relatively small effect on the Rth (j-amb).
So transposing this into temperature: ΔT = P x Rth(j-amb), then for a dissipation of 1 W:
A. 42.21 K/W: if Tamb = 105 °C then Tj = 105 + 42.21 =147.21 °C
B. 40.43 K/W: if Tamb = 105 °C then Tj = 105 + 40.43 = 145.43 °C
Rth(mb-amb) will change due to the package size, this effect is ignored here. The bigger package will
result in a lower mounting base to ambient thermal resistance. In example B above, Tj will probably
be a few degrees lower than calculated. Refer to AN90003 “Thermal design guide for LFPAK56D
and LFPAK33”[7]

for more detailed information.

To estimate Rth(j-amb), bias the body diode of the MOSFET with 1 W on the intended PCB design.
Use an infra-red camera or sensor to measure the temperature of the MOSFET plastic body, this isapproximately the same temperature as the junction.

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3.5. Q: Why is there no Rth(j-amb) in the data sheet?
A: Historically this value had not been included for automotive MOSFET data sheets, as the value
can vary hugely depending on PCB design and any cooling methods used in the system where
the MOSFET is being designed into. There have been examples of Rth(j-amb) for various packages
which are mentioned in application notes such as in LFPAK thermal design guide (AN90003) and
Thermal boundary condition study on MOSFET packages and PCB substrates (AN50019).
Newer automotive MOSFET data sheets do include a Rth(j-amb) value. Please refer to Section 3.12
for the details on how these values are derived.

3.6. Q: How can I achieve the Rth(j-mb) – I try to put the rated power inthe device, but the junction is getting too hot?
A: Rth(j-mb) tells you the temperature difference between the junction and mounting base for a given
power profile. Because of the power dissipation the mounting base to ambient path will also heatup, causing the junction temperature to rise further. The junction to ambient is the full thermal paththat needs to be considered and is a function of the PCB design too, please see AN90003 for moredetails.

3.7. Q: Why is there no Rth(j-case) in the data sheet?
A: The drain tab (mounting base) and source leads are the two main paths through which a downside cooling package dissipates heat. In fact, contrarily to some through hole packages (likeTO-220), SMD packages such as LFPAK and D2PAK get rid of all the heat through the PCB. Hot
air rises from the board and envelopes the device lowering the efficiency and thus the efficacy of
any heatsink attached to the top of the plastic case. Instead, when a substantial power needs to bedissipated, copper traces, vias and planes are employed in order to lower as much as possible theRth(j-a) of a device.

3.8. Q: Can I measure Tj from Tcase?
A: Tj is the junction temperature of the device under given operating conditions. This temperature
is calculated or inferred from the case and/or ambient temperature. However, Tcase is thetemperature of the case of the semiconductor device. Through measurements and thermal
simulations conducted on LFPAK56 devices, it is observed that in steady state conditions thetemperature measured on the top centre of the case is close to junction temperature value. The
outcome is not due to heat being dissipated from the top of the case but rather from the heatcoming out of the PCB which give rise to the temperature of the surrounding air immediately close
to the device, up to almost that of the junction.

3.9. Q: Why can an LFPAK88 have higher Rth(j-mb) than an
LFPAK56E?
A: Conduction is the predominant phenomena regulating heat flow from junction to mounting base.
The resulting resistance is inversely proportional to the cross-sectional area of the medium throughwhich heat energy propagates (die area, die attach material and mounting base) and directly to
its thickness (mounting base). Given an LFPAK56E and an LFPAK88 with the same die size, theformer has lower Rth(j-mb) because the thickness of its drain tab is lower. It is worth noting, however,that the thermal path doesn't end here and that the LFPAK88 shows better thermal performances
due to its lower Rth(j-amb) given by a much larger drain tab.

3.10. Q: Does the LFPAK88 have better or worse thermal impedance
than LFPAK56?
A: : For a given die size the LFPAK88 shows an overall better transient thermal impedance Zth(j-mb).
Additional information

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Referring to Fig. 6 we can see a much lower impedance in the region 20 μs to 10 ms. This is due tothe larger mounting base of the LFAPKK88. The greater volume of copper acts as a heatsink withlarger thermal capacitance that allows a faster absorption of heat from the die into the drain tab
itself. This is beneficial in short circuit events, inrush current events as well as other high current
events.
During steady state the LFPAK56E shows lower thermal resistance Rth(j-mb) due to the thinner draintab (see Section 3.9).
aaa-031684

1
Zth
(K/W)

BUK7J1R0-40H(LFPAK56E)

10-1

BUK7S1R0-40H(LFPAK88)

10-2

10-3

10-4
10-7

10-6

10-5

10-4

10-3

10-2

10-1

tp (s)

1

Based on thermal simulation
Fig. 6.

LFPAK88 (BUK7S1R0-40H) and LFPAK56E (BUK7J1R0-40H) transient thermal impedance comparison

3.11. Q: How much power can a MOSFET dissipate on FR4?
A: The junction to ambient (j-amb) thermal path includes all the system-level contributions
influencing a MOSFET’s thermal performance. This should be considered whenever longer power
pulses are used. For short time pulses (less than approximately 1 ms) the heat stays within the
MOSFET package. In these cases, the thermal impedance junction to mounting base (Zth(j-mb)) canbe used to calculate the power a MOSFET can safely dissipate.
The j-amb path contains the board or PCB, this can be the main bottleneck of a MOSFET’s thermal
performance.
Conduction

Ambient (Ta)Convection
Radiation

PCB

aaa-031985

Fig. 7.

Junction to ambient (j-amb) thermal propagation
The PCB is often made from FR4 material, which from a thermal and electrical perspective
is an insulator (thermal conductivity for a TG140 FR4 PCB is around 0.35 W/mK, conversely
for copper it is 385 W/mK). Fortunately, copper planes, vias and traces are used, not only as

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electrical interconnections but also to improve the thermal performance of the PCB, i.e. reduce its
thermal resistance. This can vary a lot depending on the amount of via holes, board and copper
thicknesses and chemical composition, among others. Generally, the Rth(j-amb) has been observed
to be 50 K/W for a PCB suspended in free air.
Assuming a maximum temperature of 130 °C for the FR4 and an ambient temperature of 85 °C(often used in automotive applications) then the maximum power a MOSFET can safely dissipate
can be calculated using Equation (2):P=

∆T
R th (j-amb)P=(130 ℃ 85 ℃) K/°C
TFR4,max
T amb== 0.9 W
50 K/W
R th (j-amb)(2)

The junction temperature is assumed to be close to the FR4 one since, in this case, Rth(j-mb) <<Rth(mb-amb). This result is often known as the 1 W rule (of thumb): a MOSFET can safely dissipate
a maximum of around 1 W continuously if soldered on a standard (FR4 TG140) PCB suspended infree air without heatsink.
For more information, please refer to AN90003: “LFPAK MOSFET thermal design guide”.

3.12. Q: What are the conditions used to derive Rth(j-amb) in
Automotive MOSFET data sheets?
•
•
•
•
•

Device is mounted on FR4 4-layer PCB, measuring 114 mm x 76 mm x 1.6 mm.
Copper thickness is 2 oz for top and bottom layers and 1 oz for internal layers.
Minimum copper footprint on top layer. 74 mm x 74 mm for buried and bottom layers.
1.2 mm array of 0.3 mm diameter thermal vias under MOSFET drain connecting layers 1, 2 and4.
PCB is horizontal in still air.

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4. MOSFET body diode4.1. Q: How much current can the MOSFET body diode carry?
A: The data sheet states the IS capability for the diode. The power constraints are the same as for
the MOSFET conduction. The diode is an integral part of the MOSFET structure. They are in effectthe same size and have the same thermal properties. The MOSFET can carry the same current
through the channel or in reverse through the body diode. The maximum steady state current in thediode is dependent on the total allowed power loss for the device. However, the diode current may
be different from the channel current because the power dissipation may be different under the 2modes of operation.
Additional information
The objective is to keep the junction temperature below Tj(max) so it is necessary to calculate
the diode dissipation. In a DC case, it is simply IF x VF. It is equivalent to VSD x IS as used in the
Nexperia MOSFET data sheet. For a worse case analysis, the max VF of the data sheet should
be used (normally 1.2 V).
Where the current is varying but in cyclic manner, the dissipation can be found using
Equation (3) below:

Power = VO × I(AV) + R S × I 2(RMS)(3)

where:
I(AV) is the average diode current
I(RMS) is the RMS diode current
RS is the slope of the ISD/VSD characteristic graph given in data
VO is typically where the RS line meets the axis at ISD = 0. For a conservative worst case analysis,use 1.2 V.
aaa-013061

100
ISD
(A)
80

60

40

20
(1)

0

0

0.5

(2)

(3)

1.0

VSD (V)

1.5(1) characteristic at 25 °C(2) idealized characteristic at 25 °C(3) worst case idealized characteristic at 25 °C
Fig. 8.

Diode characteristics

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For transient currents, a simulation using the SPICE model of the diode is useful but care isneeded because the model is for a typical part. Once the dissipation is known, standard thermal
analysis methods can be used to check that Tj is acceptable.
It can include SPICE simulation using RC thermal models.

4.2. Q: What is the importance of the Qr parameter?
A: When a MOSFET transitions from diode conduction to blocking state there is an additionalloss, called the diode recovery charge (Qr). The Qr needs to be factored in the switching loss
calculation of the application for accurate analysis. This switching transition also impacts on the
EMC performance and needs careful consideration - see AN90011 and TN90003 for more details.
Additional information
Qr is relevant in all half-bridge topologies, for example DC-to-DC convertors or motor control.
In both examples the MOSFET's body diode will be conducting in the forward direction before
it is required to block voltage in the reverse direction. This change of operation is called dioderecovery and takes time (reverse recovery time, trr) during which charge is stored (dioderecovery charge, Qr).The Qr adds additional losses to the switching transient.
In addition to switching losses the recovery of the diode is related to the EMC performance of a
MOSFET in an application. A fast recovery will cause high voltage spikes and a poorly damped
diode will cause voltage and current oscillations after the switching event causing EMI.

4.3. Q: What is the gate oxide capability for a logic level MOSFET(data sheet says only 10 V, will it break at 11 V?)
Logic level MOSFETs are primarily intended for applications where the drive voltage is 5 V andthus optimised accordingly. To achieve a fully-on MOSFET and best RDSon performance withrelatively low gate voltages these MOSFETs will need a thinner gate oxide than standard levelparts which operate with a drive of 10 V VGS at 175 °C . Thinner gate oxides will breakdown atlower voltages and will have a lower rating than standard level devices.
In terms of capability, logic level MOSFETs are not expected to suddenly fail as soon as higher
voltages are applied. However, applying higher VGS than the maximum rated voltage willcompromise the 1 ppm failure rate and therefore Nexperia would not consider including theseratings in data sheets and would not recommend exceeding them[4].

5. Safe operating area and linear mode operation
5.1. Q: The current derates with temperature. Is this limit based on
power dissipation?
A: The most important factor in current derating or power derating is junction temperature. Tj
is a function of power dissipation. Power dissipation is a function of ID current and on-state2
resistance (P = ID × R) when operating in the fully enhanced mode. It is the product of ID and
VDS when operating between on and off states. The RDSon of a MOSFET, increases with increasein temperature. Therefore, for a given maximum power dissipation, the maximum current must
be derated to match the maximum power dissipation. In Nexperia data sheets, graphs show thecontinuous drain current and normalized total power dissipation (see Fig. 10) as a function of themounting base temperature. These graphs can be used to determine the derating.

5.2. Q: Is it necessary to de-rate any limit (current, voltage, poweretc.) to achieve high reliability?
A: If current, voltage, power, junction temperature, etc. are within Nexperia data sheet limitations,no additional derating is needed. In the data sheet, there is a power derating curve based onjunction temperature. Junction temperature (Tj) is one of the most important factors for reliability.

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Particular care should be taken to extract enough heat from the device to maintain junction or dietemperature, below rated values. The device should be operated within the SOA region. It should
be de-rated if necessary (see Section 5.3) as recommended in the data sheet and it should bepossible to obtain optimum reliability.

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5.3. Q: How do I de-rate an SOA graph for temperatures other than
25 °C?
A: As an example, assume that the temperature required is 100 °C, instead of 25 °C. Tj rated is
175 °C for this automotive grade MOSFET. To de-rate when considering the effect of temperature
on SOA performance the current must be reduced, (see Fig. 9). To determine the new current(at temperature) for a fixed voltage, use the power derating line in Fig. 10. For example, power
at 100 °C = 50 % of power at 25 °C. Therefore, the 1.0 A line represents 0.5 A at 100 °C etc. It is
explained in Application Note AN11158. If necessary, the SOA lines for 1 ms, 10 ms etc. can beextended at the same slope to the right.

ID(A)

aaa-002475

103
Limit RDSon = VDS / ID
102

30 A at 100 °C

tp = 10 us

10DC
0.5 A at 100 °C

1 ms

1

10 ms
100 ms0.05 A at 100 °C

10-1
10-1

1

10

102

VDS (V)Tmb = 25 °C; IDM is single pulse
Fig. 9.

Example: BUK7Y12-55B SOA curve showing derating for 100 °C
03aa16

120
Pder
(%)
80

40

0

0

50

Pder =

100

Ptot

Ptot(25 °C)

150

Tmb (°C)

200

× 100%

Fig. 10. Normalized total power dissipation as a function of mounting base temperature

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Power MOSFET frequently asked questions and answers

5.4. Q: Is there a Spirito boundary limit line for linear mode
operation?
A: The Spirito region or hot spotting issue with new higher density technologies may have more
effect in the linear mode of operation. This effect is evident from the change in gradient in the limit
lines for 1 ms, 10 ms and 100 ms at higher VDS values (see Fig. 9). The 1 ms, 10 ms, 100 ms andDC lines at higher VDS values emphasize it. The reason is that most newer technologies pack moreparallel fundamental cells to share more current in a smaller die (lower RDSon per unit area). It
leads to an increased thermal coupling between cells. Also, to attain higher current densities, the
MOSFETs are designed with higher transconductance or gain (gfs = ID/VGS). It enables them tocarry higher currents even at lower VGS values. However VGS(th) (threshold voltage) has a negative
temperature coefficient which leads to a higher zero temperature coefficient crossover value. For
various reasons, the distribution of temperature in the die is never perfectly uniform. Therefore,
when the device is operated for extended periods in linear mode, hot spotting occurs. Due to theshift in threshold voltage, there is a risk of thermal runaway and device destruction where thehotspots form. Because of these reasons, special care should be taken when using trench orplanar MOSFETs for linear applications. Ensure that operation remains within the data sheet SOA
limits.

5.5. Q: Regarding the SOA curve for the 1 ms and 10 ms curves,
there is a bend-down at higher voltages and low currents. Why does
this bending disappear for longer and shorter pulse times?
aaa-022335

103
ID
(A)
102

Limit RDS(on) = VDS / ID
tp = 10 µs
100 µs

10
DC
1

1 ms
10 ms
100 ms

10-1
10-1

1

10

102

VDS (V)103

Fig. 11. Safe operating area: continuous and peak drain currents as a function of drain-source voltage
A: The inflexion points on the 1 ms and 10 ms lines represent the points where the ‘Spirito’
effect starts. At higher ID, the lines represent constant power (P); at lower ID, P decreases as ID
decreases. The 100 ms and DC lines are straight, but have higher negative gradients than constant
power lines, i.e. power also decreases as ID decreases. The flat portion of the DC line represents
package maximum ID.
The Spirito effect is a form of electro-thermal instability i.e. uneven die heating leading to hot-spot
formation. It happens because VGS(th) has a Negative Temperature Coefficient (NTC) at ID values
below IZTC (zero temperature coefficient current). The consequence is to reduce MOSFET power
dissipation capability in lower ID zones of the SOA chart.
Measurement at DC, 100 ms, 10 ms and 1 ms establishes SOA capability. The 100 μs and 10 μslines on this graph are theoretical constant power lines. They are realistic, as the Spirito effect ismuch less significant at higher currents and shorter pulse periods.
Reliable 100 μs SOA measurement capability has recently been achieved, so future data sheets
include 100 μs SOA lines based on measured data. It is now evident that the Spirito effect is

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Power MOSFET frequently asked questions and answers
apparent at 100 μs. Consequently, from 2016, new MOSFET releases have a measured 100 μs
SOA line in their data sheet SOA graph.
See AN11158 for further information.

5.6. Q: How does Nexperia ensure compliance with the SOA curve
during series production?
A: The factors influencing the compliance of the MOSFET with the data sheet SOA graph are:••the uniformity of the MOSFET cells across the active (trench) surface of the die
the integrity and uniformity of the die attachment (the solder layer between the die bottom(drain) surface and mounting base)

Cell uniformity must be good for the MOSFET to work. However, cell uniformity can never be
perfect and there is always some variation between cells.
The integrity of the soldering to attach the die must be good without voids or die tilt. If not, the local(junction to mounting base) thermal impedance varies with location across the die. It gives unevencooling. Uneven die surface cooling may be due to either or both of the factors stated. However,the consequence is the same i.e. SOA non-compliance with the data sheet graph.
In production, linear mode power pulse tests are used to stress the MOSFET thermally. If the diecooling is not sufficiently uniform, hotspots can form and the device parameters can change morethan expected. A decision to reject parts can be made based on the results.

5.7. Q: How can a part be identified when it is designed for linear
mode operation?
A: While all Nexperia MOSFETs can be used in linear mode operation, some Nexperia MOSFETs
are designed specifically to be used in linear mode. Please also check the Application Specific
MOSFETs selection of the Nexperia website. The device description in the data sheet states thatthe device is suitable for operation in linear mode. To determine the suitability for operation in linear
mode, perform a thorough analysis of the SOA graph. This analysis includes derating the SOAgraph for junction temperatures above 25 °C. The naming convention indicates that the MOSFET is
designed for linear mode applications, e.g. : BUK9Y7R0-60EL is an Application Specific MOSFET
for airbag applications with enhanced SOA. The letter L indicates it is designed for use in linear
mode applications.

5.8. Q: For parts designed for linear mode operation, are there any
restrictions (such as the Spirito boundary)?
A: Even if a MOSFET is intended for use in linear mode applications, the part must not be operated
outside its SOA. Post 2010, all Nexperia MOSFETs have a measured SOA characteristic. The
limit of linear mode capability on Nexperia parts is shown in the SOA characteristic. As a result,the boundary of what is safe is established via measurement rather than calculation. The Spirito
capability limit is shown in the SOA characteristic.

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5.9. Q: Can modern MOSFETs be used in linear mode?
A: Yes, modern power MOSFETs from Nexperia, can operate in linear mode. This may not be true
for devices from other vendors. The devices are typically dissipating higher power levels than theywould dissipate in switched-mode applications due to simultaneous occurrence of high voltage andcurrent[7].

MOSFETs can operate in linear mode in two ways: indirectly, for a short time, because of switchingor for some applications intentionally operating in the linear region. In fact, linear mode is traversed
every time a MOSFET switches ON and OFF. With reference to Fig. 12, during turn ON the
MOSFET’s working point moves from high VDS and zero ID (OFF state) to a low VDS and high ID(curve 1). If the end goal is to use the MOSFET as a switch then it is usually good practice to try to
reduce the time and power dissipated in linear mode, for instance by decreasing the switching time.
Conversely, certain applications require MOSFETs to purposely operate in linear mode (curve 2). In[6]
this case it is recommended to :••Guarantee that the device operates within the SOA curve, for a given pulse duration andmounting base temperature (Tmb).
Employ adequate thermal management techniques.

Fig. 12. MOSFET output characteristic: ON/OFF trajectories where curve 1 represents RDSon operation ON/OFF
trajectory and curve 2 is linear mode operation ON/OFF trajectory

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Power MOSFET frequently asked questions and answers

6. Avalanche ruggedness and Unclamped Inductive Switching (UIS)
6.1. Q: Are trench designs susceptible to the UIS issue (parasitic
BJT turn-on)?
A: In general - Yes, but Nexperia Trench MOSFETs are designed to suppress this effect. The
trench structure, unlike planar, can be very easily designed to suppress parasitic turn on of the BJT.
For new Nexperia MOSFET technologies, the failure mechanism is thermal, which represents thelimit of achievable UIS performance. Planar (on the left in the diagram) and trench (on the right in
the diagram) MOSFET technologies, are shown in Fig. 13. In the trench case, a design feature in
the source contact effectively short circuits the base-emitter of the parasitic BJT. In older planar
technology, the shorting of base to emitter of the parasitic bipolar is not as effective. It is due to thelonger path length in the n and p regions.
S

G

S

n

n
p

S

G

S

n

n

p

n

D

p

p

n

n

D

aaa-015947

Fig. 13. Simplified planar and trench technology

6.2. Q: Why are planar designs susceptible to failure during UIS?
A: All MOSFETs are susceptible to failure during UIS. It depends on whether the MOSFET Tj
reaches the intrinsic temperature of silicon. Furthermore, if the parasitic BJT is triggered, they canfail even earlier. It is because the BJT can be switched on relatively quickly but is slow to switch off.
Current can then crowd in a certain part of the device and failure results. Newer Nexperia trenchtechnologies are less vulnerable to triggering of the BJT than planar designs. See Section 7.1 andthe additional information associated with Section 6.3.

6.3. Q: How are parts constructed to minimize failure during UIS?
A: The base emitter path in the silicon design is designed to minimize the risk of triggering theparasitic BJT.
Additional information
There are two strategies employed to prevent triggering of the parasitic BJT:
1. Reduce the avalanche current per cell - To reduce the avalanche current per cell, there must bea higher cell density. It is easily achieved with trench technologies but more difficult with planar
devices. If improvements in planar technologies are seen, it is likely that modern fabricationequipment achieves a high enough cell density. Increasing cell density too much, deteriorates
linear mode performance (Spirito boundary occurs sooner), so cell density is a trade-off. For
this reason, Nexperia has not been as aggressive as other trench MOSFET manufacturers
in achieving very high cell densities. The target is to ensure that the thermal limit in UIS isachieved.
2. Ensure that the current flow during avalanche does not flow through the base-emitter regionof the BJT. This feature is the significant advantage of trench over planar. The parasitic bipolaris formed between the source of the MOSFET, the body region (i.e. channel) and the epi
region (i.e. the drain). If there is enough avalanche current through body junction, there may
be enough voltage developed to bias on the BJT leading to device destruction. In Nexperia

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devices, a modified source contact is used. This contact collects any avalanche current,
preventing it from biasing the BJT on.
For planar devices, strategies include reducing the gain of the BJT by placing high doped
implants close to the channel. It is similar to (2) in intention but it is not as effective.

6.4. Q: Is 100 % UIS testing required on MOSFETs?
A: UIS testing is a fundamental part of Nexperia's defect screening procedures. It is applied to all
devices. The test is designed to increase the junction temperature to Tj(max).

6.5. Q: I have parts not capable of parasitic BJT turn-on. Why?
A: Devices fail at the thermal limit. At the thermal limit, the silicon becomes intrinsic and blockingjunctions cease to exist. It is considered to be the only UIS-related failure mechanism in our
devices.

6.6. Q: What is the chart accuracy for avalanche current versus timein avalanche, or energy versus junction temperature?
A: Avalanche current versus time graphs are based on conditions that take a device to Tj(max) andtherefore, our ruggedness screening covers them. All Nexperia MOSFETs are ruggedness tested
during assembly and characterized during development. The graphs are accurate and provide theworst case capability of the device to ensure reliability.

6.7. Q: For energy versus junction temperature charts (if applicable),
how is the inductance, maximum current, time in avalanche etc.,
determined from the chart?
A: A temperature rise model is used, which is shown in AN10273 Power MOSFET single-shot andrepetitive avalanche ruggedness rating.
Additional information
Although energy levels for UIS are often quoted on data sheets, a single number canbe misleading. Therefore a graph is provided, that outlines conditions that take junction
temperature to Tj(max). The user must determine the current/time in avalanche based on theparticular conditions. Examples are provided in AN10273 Power MOSFET single-shot andrepetitive avalanche ruggedness rating.

6.8. Q: Are repetitive avalanche ratings the same as for a single
pulse?
A: No. The repetitive avalanche ratings are lower than the single pulse rating. Refer to the productdata sheet for the device capability. An example is shown in Fig. 14.
Additional information
Repetitive means that the avalanche event is an intended operating condition for the device.
Similarly, single-shot means that the MOSFET is expected to experience an avalanche event
as a result of some unintended fault condition. Only 1 fault can occur at a time, the MOSFET
must cool to the starting temperature and the junction temperature must not exceed 175 °C.
Degradation of device characteristics is likely after a relatively low number of occurrences.
Nexperia shows both single shot and repetitive avalanche capability in the MOSFET data sheet.
Generally, the repetitive current is 10 % of the single shot current capability for a given inductor(so the time in avalanche is shorter, see Fig. 14 and Section 6.14.
For calculating repetitive avalanche ratings, calculate the starting junction temperature for eachavalanche incident independently. The calculations are based on the frequency and duty cycleof avalanche condition and summed over the entire period of expected repeated avalanche.
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Power MOSFET frequently asked questions and answers
This topic is discussed in detail in Nexperia Application Note AN10273 Power MOSFET singleshot and repetitive avalanche ruggedness rating.

6.9. Q: Are there any special failure modes associated with repetitive
avalanche?
A: The device can sustain small amounts of damage with each avalanche event and over time they
can accumulate to cause significant parametric shifts or device failure. Nexperia has performed
research into this area and provides the repetitive ratings in the data sheet. See also Nexperia
Application Note AN10273 Power MOSFET single-shot and repetitive avalanche ruggedness
rating.

6.10. Q: How does the increase in cell density affect avalanche
capability of MOSFETs?
A: There are two failure modes: current (parasitic BJT turn-on) and thermal. Cell density has
implications for these failure modes.
Additional information
Current - If enough avalanche current flows through a cell, a voltage drop occurs in the pregion of the device as the avalanche current flows to the source contact. This volt drop
occurs in the base of a parasitic bipolar device. In this mode, the resistance in the p-region/base and the avalanche current (I = V/R) are important. Once VBE reaches the bipolar switchon threshold, the MOSFET is destroyed (VBE reduces with temperature). So at higher celldensities, for the same avalanche current, there are more cells and current per cell is reduced.
Each individual cell has less current and is less likely to trigger the parasitic device. It meansthat the total die current, required to cause a device to fail, increases. Additionally, since thecell is smaller, the path through the p-region to the source contact is reduced. It makes it evenharder to trigger the parasitic device and again increases the current required to destroy thedevice.
Thermal - If the avalanche current is such that the parasitic BJT is not triggered, the device
heats up. If the avalanche energy is sufficient, the silicon die reaches temperatures at which
the device starts to become intrinsic. The blocking-junction no longer exists, resulting in thedestruction of the device. It is what is meant when a reference is made regarding failure due
to reaching the thermal limit of a device. If the failure mode is thermal, changes in technology
cannot improve things significantly. New technologies are generally more robust in avalanche
conditions. Note, if a thermal limit is reached, the only solution is to improve the thermal
impedance at the device level. Moving to a smaller die can be detrimental.
Summary - New technologies improve the high current avalanche capability of a device due
to increased cell density and reduced parasitic NPN base resistance. Lower current, higher
energy (i.e. longer duration) avalanche capability is unchanged.

6.11. Q: How many times can a device sustain single avalanche
events?
Example - A device has an avalanche event once in two months so how many cycles of such anavalanche frequency can the device sustain? This question relates more to quality and reliability
but it is important nonetheless.
A: Refer to Section 6.8 of this document. For the answer to this question, refer to Section 2.4.3 ofAN11158 and all of AN10273.
Additional information
Keep each avalanche event within the safe limits for repetitive operation specified on the data
sheet and Tj below 175 °C. There should be no degradation of the MOSFET characteristics andno impact on MOSFET quality or reliability. There are some applications where MOSFETs are
repetitively avalanched (e.g. some engine controllers) and the reliability is good. Although thiscondition takes VDS beyond the data sheet maximum, the data sheet also specifies a maximum
avalanche energy.

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Power MOSFET frequently asked questions and answers
Extensive avalanche testing is performed on Nexperia MOSFETs. All the indications are thatthey are very robust. It is understood that most MOSFETs in automotive applications are likely
to experience avalanche conditions at some stage during their lifetime. It could be due tooccasional fault conditions or as a consequence of the circuit design (e.g. ABS solenoid valve
driver MOSFETs).

6.12. Q: Is it possible for the avalanche current on a device toexceed the package maximum current but not the die maximum
current?
A: The current specified in the avalanche graph should not be exceeded. It is restricted to the DC
rated current. The device factory test defines the limit which is guaranteed for the device.

6.13. Q: How is the avalanche rating on the body diode obtained(testing or modeling)? If it is tested, how is it tested and what circuit
model is used?
A: The avalanche rating is modeled first and the results are then verified by testing to destruction.
The test circuit used is similar to the one defined in JESD24-5. For SPICE modeling, the reverse
diode characteristics can be defined and modeled. By adding an RC thermal model of the Zthcharacteristic, it is possible to estimate the Tj of the device.
Additional information
The body diode of the MOSFET is not a single circuit element, but a structure distributed
throughout the MOSFET. There is a diode element associated with each cell. In behavior
terms, it can be represented as a single (Zener) diode in parallel with the single MOSFET(representing the sum of all the cells). The design of the MOSFET determines the avalanche
rating. Its representation in the model is based on parameters measured during characterization
testing.
The constraints are the same as for the MOSFET conduction. Diodes are an integral part of the
MOSFET structure. They are in effect the same size and have the same thermal properties.
The objective is to keep the junction temperature below Tj(max) so it is necessary to calculate
the diode dissipation.
For transient currents, the simulation using the SPICE model of the diode is useful but care isneeded because the model is for a typical part.
Once the dissipation is known, standard thermal analysis methods can be used to ensure that
Tj is acceptable.

6.14. Q: How is the repetitive avalanche safe operating area derived
in the data sheet graph? The repetitive avalanche SOA curve seems
to be the same as single-shot Tj = 170 °C.
A: The repetitive line is the line for a start temperature of 170 °C. It is because it predicts atemperature rise of 5 °C which is the maximum permissible rise from any starting temperature (seeAN10273). It also corresponds to 10 % of the single-shot current using the same inductor value,
see Fig. 14.
Additional information
The reason it applies to any temperature is because the temperature does not strongly
influence the wear-out caused by repetitive avalanche. The strongest influence is the current.
The avalanche current is composed of high energy charge carriers moving through thedepletion region. As they pass through, they can collide with the Si structure. There is a chancethat a high energy carrier (sometimes called a hot carrier) is produced that collides with the gate
oxide causing damage. It is not completely destroyed but it does cause it to wear out, which isobserved as parameter variation.

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Higher currents mean more electrons, more collisions and more frequent damaging events
leading to faster wear-out and lower reliability. The target should be a failure level <0.1 ppm
over the full vehicle life. Experiments indicate that if repetitive current is limited to 10 % of
single-shot current capability for Tj(start) = 25 °C, it results in a Tj increase of 5 °C. There is no
significant degradation of the device.
For example: A 15 mH inductor carrying ~19 A gives an avalanche time of ~5 ms. It has apeak temperature rise of 150 °C putting it on the limit line for Tj(start) = 25 °C.
By reducing the current to 10 % = 1.9 A, tAL reduces to ~500 μs and the temperature rise is
5 °C.
aaa-013064

103
IAL
(A)
(1)

102

(2)

10
(3)

1
(4)

10-1
10-3

10-2

10-1

1

tAL (ms)

10(1) = characteristic at 25 °C(2) = characteristic at 150 °C(3) = repetitive characteristic at <170 °C(4) = inductor characteristic
Fig. 14. Avalanche safe operating area

6.15. Q: What is the difference between avalanche breakdown andactive clamping for inductive loads?
A: Avalanche happens when VDS exceeds the BVDSS rating of the device when VGS = 0 V orlower. A typical example is when a flyback voltage generated during the turn off of an inductive
load or a spike voltage caused by the parasitic inductance present inside the circuit exceeds thebreakdown voltage of a MOSFETs body diode as shown in Fig. 15 (a). Here, the MOSFET isdriving an inductive load. If current is flowing through the inductor and the MOSFET is switched off
a voltage transient will appear on the drain (Vdrain). This voltage will rise to a sufficient level to allow
the inductor to maintain its current flow. When the MOSFET’s body diode reverse voltage rating is[2]reached, then the MOSFET conducts in avalanche mode . The advantage of avalanche modeis that no extra components are required. Nexperia MOSFETs have avalanche capability clearly
defined in the data sheet and some are qualified to operate in repetitive avalanche mode (these
are in the ASFET portfolio). The disadvantage of avalanche mode is that the breakdown voltage
may be too high for the system level requirements and is temperature sensitive, this may lead to ashorter switch off time which varies a little depending on temperature.
Active clamping is when a component network is placed in conjunction with the MOSFET to clamp
the maximum source-drain voltage at a value below BVDSS, thereby preventing avalanche. A typicalexample is addition of a rectifier diode in series with a Zener diode between gate and drain. During
inductive switching, the device operates in linear mode at a lower clamping voltage in comparison[4]

to avalanche as shown in Fig. 15 (b). When the MOSFET switches off, there will be a back-EMF
voltage induced at the MOSFET’s drain terminal (Vdrain). If the drain to source voltage exceeds theapproximate breakdown voltage of the clamping network, then a small current flows through theclamping network to the gate of the MOSFET and raises its potential, which partially turns on the
MOSFET so that the drain-source voltage is controlled precisely. This controls the rate of change

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Power MOSFET frequently asked questions and answers[6]of the drain current accurately . The advantage is a longer and accurately determined switch
off time which may be important for the system level operation. There are a few disadvantages of
the active clamp approach. The MOSFET will operate in linear mode which generally means thatthe user must be aware of the MOSFET‘s safe operating area in particular regarding the Spirito
effect. Normally switch-off times are still far shorter than the onset of current crowding and hotspot
formation. However if repetitive inductive switching is performed then the Spirito effect can becomea necessary consideration. The capability and reliability may also be worse than considering
avalanche mode of operation. The cost of the clamp network components is another consideration.
aaa-035738

L

L
VSupply(Vbatt+)VSupply(Vbatt+)VdrainClamping
network

Vdrain

VGS

VGS

ID

Iav
Current sensor(not required)(a) unclamped
MOSFET OFF avalanche current flows through body diode(b) clamped
MOSFET ON (linear mode) current flows through MOSFET channel

Fig. 15. Inductive load: body diode avalanche breakdown and active clamping

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7. Capacitive dV/dt issues
7.1. Q: Is there a particular capacitance or charge ratio that should
be used to prevent turn-on, or is it circuit dependent?
A: The capacitive dV/dt turn-on is strongly circuit dependent.
If the dV/dt across the MOSFETs drain to source is too high, it may charge CGD, which is thecapacitance between drain and gate, inducing a voltage at the gate. The gate voltage depends
on the pull-down resistor of the driver based on Equation (4):

VGS = R driver × C GD × dV / dt

(4)

In some bipolar drive circuits, such as emitter follower derived circuits, the problem isincreased. It is because the driver cannot pull the gate down to 0 V and has approximately
0.7 V offset.
It is also important that the driver is referenced to the MOSFET source and not to signal ground,which can be significantly different in voltage.
The ratio of CGD to CGS is a factor but a good drive circuit is the critical factor.
Even if a VGS spike is present, it is safe for the MOSFET as long as the dissipation is within
thermal limits and MOSFET SOA limits.

7.2. Q: How are parts constructed to minimize this effect?
A: Nexperia MOSFETs are designed with a high threshold at high temperatures and we check VGS
threshold at 25 °C is within data sheet limits. Logic level devices are designed and guaranteed tohave a minimum threshold voltage >0.5 V even at 175 °C.
Additional information
Maintain a reasonable ratio between CGD and CGS. The gate network structure of the device isdesigned to have good control of all areas of the die.

7.3. Q: How is dV/dt characterized?
A: It is usually measured in a half-bridge test circuit. It is a measure of the device dV/dt during
body diode reverse recovery. This data is not normally published in the data sheet. This dV/dt is inpractice the highest dV/dt the device experiences.
Additional information
Failure due to dV/dt is not something seen in modern low-voltage MOSFETs however, dV/
dt is normally characterized for Nexperia MOSFETs. The failure mode is that the capacitive
current resulting from dV/dt, triggers the parasitic BJT. However, as the voltages are low (dV/dt
is more an issue > 600 V) a current/charge high enough to trigger the parasitic BJT cannot be
generated.

7.4. Q: What diode or other parameters are important to assess
susceptibility? For example, maximum dV/dt and maximum IF.
A: High dV/dt can induce glitches onto the gate of the MOSFET. A snubber can help to reduce
dV/dt and the magnitude of the VDS spike if significant. The ratio of Coss at low VDS compared to
Coss value at high VDS is an indicator of the non-linearity of Coss. A very high ratio can indicate thatthe device can generate a high dV/dt. Gate driver circuit design can reduce the gate glitch, see
Section 7.1. The ratio of QGD to QGS and the gate threshold voltage can be used to indicate thesusceptibility of the device to gate glitches.

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7.5. Q: Is trench technology sensitive to this phenomenon?
A: In theory, all MOSFETs are.
Additional information
dV/dt induced turn-on of the parasitic bipolar transistor is not known as an issue in low voltage
Nexperia MOSFETs. If UIS parasitic turn-on is solved, then dV/dt induced turn-on is also
solved. Refer to Section 6.1 and Section 6.3 for more information.

7.6. Q: Does a soft recovery body diode give lower dV/dt and if so,
how is it designed and fabricated into the part?
A: Soft recovery does reduce the dV/dt. Although dV/dt is not an issue for the MOSFET, alower dV/dt is better for EMI, voltage spikes and crosstalk. The design and manufacture is very
specialized, involving proprietary information.

7.7. Q: How does temperature influence this sensitivity to dV/dt andwhy?
A: At high temperatures, it is easier to trigger a parasitic bipolar as its VBE reduces. But if the BJT
is effectively shorted out and current diverted away from it, as discussed in Section 6.1, then it is
not an issue.

7.8. Q: Can Nexperia provide RB, CDB, VBE saturation values in theparasitic BJT model, as shown in Figure 11?
A: These values are required to be able to calculate Equation 6. The aim is to obtain a dV/dt
value to check if parasitic BJT turns on, leading to device failure. It is impossible to measure thecharacteristics of the parasitic bipolar transistor as its terminals cannot be accessed independentlyof the MOSFET terminals. A parasitic bipolar transistor is always created when a MOSFET isfabricated. Referring to Fig. 16 it can be seen that there are two current paths which could cause
MOSFET problems. Current I1 flows via CGD and depending on CGS and RG it can cause the
MOSFET to switch on momentarily. It is often referred to as a gate glitch. Current I2 flows via CDB
and RB which can potentially switch on the parasitic BJT.
Additional information

V GS = I 1 × R G = R G × CGD × dV / dt

(5)

V BE = I 2 × R B = R B × CDB × dV / dt

(6)

DRAIN

D
I1

CGD

CDB
NPN
bipolartransistor

G
I2
RG

CGS

appliedramp
voltage

RB

S

SOURCE

aaa-013073

Fig. 16. Power MOSFET showing two possible mechanisms for dV/dt induced turn-on

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SOURCE

GATE

N+
RB

P

N

CDB

DRAIN

aaa-013074

Fig. 17. Physical origin of the parasitic BJT components that may cause dV/dt induced
turn-on
Additional information
Early lateral MOSFETs (structure shown in Fig. 17), were susceptible to failure caused by theturn-on of this parasitic transistor.
Modern power MOSFETs have greater cell density meaning the current per cell is reduce andthe voltage across RB is lowered. In addition, the geometry of each individual cell is smaller
compared to previous generations making RB shorter in length and therefore a lower value ofresistance. Both these greatly improving the immunity of modern trench MOSFETs (structure
shown in Fig. 18) to dV/dt latch-up.
In application tests we see dV/dt values in the order of 1 – 10 V/ns for T6 and T9 technology
when switched quickly using a high current gate driver with low gate resistance.

Source

Oxide
Gate

N
P
N
Drift Region

Substrate
Drain
aaa-013075

Fig. 18. Trench generation 6 structureTN00008
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7.9. Q: In a half-bridge configuration one MOSFET is driven off,
and the second MOSFET begins to turn on. The first MOSFET thatshould be off is turning back on again causing cross conduction andan over-current peak. What could be the cause? See Figure 13 forphenomena.
aaa-022330

12

current (A)VGS (V)

overcurrent
peak

6

10

5

8

4

voltage(V)

6

3
MOSFET turning
back on4

2

current
(A)

2

1

0

0

time

Fig. 19. Blue VGS trace shows gate bounce and the red current waveform spiking whengate bounce occurs
A: It is sometimes referred to as gate bounce. MOSFETs have internal stray capacitances coupling
all three terminals and the gate is floating. The capacitors are inherent to the internal structure of a
MOSFET, see Fig. 20.

CGD
NMOS

CDS

CGS

aaa-022333

Fig. 20. MOSFET Schematic representing the internal capacitances
CGD and CGS form a capacitive potential divider. When a voltage appears across the drain andsource of the MOSFET, it couples to the gate and causes the internal gate source capacitor to
charge. If the voltage on the gate increases beyond the MOSFET's threshold voltage, it starts
to turn back on which can cause cross conduction. The ratio of the capacitances CGD and CGS
determines the severity of this effect.
Additional information
Fig. 21 shows a simplified circuit that can exhibit this behavior. It could be a synchronous buckregulator or one leg of a 3-phase inverter. In both cases, the load is inductive. A current source
represents the inductive element in this circuit.

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high-sideFET

low-sideFET

aaa-022334

Fig. 21. Simplified schematic of a MOSFET half-bridge. The high-side and low-side
MOSFETs are switched antiphase to each other17
voltage(V)14

aaa-022331

VGS low-side (V)VGS high-side (V)VDS low-side (V)Current (A)

6

5

11

4

8

3

5

2

2

1

-1

current
(A)

time

0

Fig. 22. Waveforms showing the full detail of the gate bounce phenomenon
The waveforms in Fig. 22 show the critical part of the applications operation when the current
commutates from one MOSFET to the other. In this instance, the high-side MOSFET is being
switched on as the low-side one switches off. Current flows from the switch node. Note the lowside MOSFET behaves as a diode when it is switched off. This behavior is similar when current
flows into the switch node. In this case, the high-side device becomes the synchronous rectifier.
Referencing the waveforms in Fig. 22, the blue low-side VGS trace begins to drop and the lowside MOSFET turns off. The green low-side VDS trace going negative indicates that it has switched
off. The low-side MOSFET body diode begins to conduct the inductive current and there is a VF
drop of approximately 0.7 V. The high-side MOSFET begins to turn on to a point where it conducts
all of the load current. The low-side diode turns off and the low-side VDS can now increase to the
supply voltage. However, as the VDS rises, the dV/dt is coupled back to the low-side gate through
CGD. The blue low-side VGS trace begins to increase again. In this example, the gate voltage rises
sufficiently above the threshold voltage so that it is now turned back on again. Both high-side andlow-side MOSFETs are on simultaneously. The current rapidly increases due to the short circuit
across the supply as indicated by the red current trace.
There are several factors that influence this behavior, the most dominant of which is the gate
resistor. If the gate resistor is set to a level where the gate driver cannot sink the capacitively
coupled current, it must feed into the CGS. It causes the gate source voltage to rise as can be seenin Fig. 22.

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aaa-022332

12
voltage(V)

VGS at Rg = 100 Ω
VGS at Rg = 200 Ω
VGS at Rg = 300 Ω
Current at RG = 100 Ω
Current at RG = 200 Ω
Current at RG = 300 Ω

106current
(A)

5

8

4

6

3

4

2

2

1

0

0

Each waveform has a different external gate resistor. Increasing the gate resistor has adetrimental effect on the severity of the gate bounce.
Fig. 23. Effect of RG on VGS, and shoot-through current
It is good practice to keep the external gate resistor as low as possible. In reality, there is a limit to
how low this value can be, due to EMC considerations. Good design practices can be employed
to improve EMC while maintaining a low enough value of gate resistor to prevent gate bounce.
Simple alternatives to increasing the gate resistor include adding extra capacitors external to
the MOSFET between gate and source, located close to the MOSFET connections. It helps withradiated emissions without affecting the gate turn off waveforms as much.
Other key factors include the MOSFETs threshold voltage (Vth). The lower Vth is, the moreenhanced a MOSFET is for a given gate bounce voltage. It therefore increases the severity of thecross conduction. Vth is also temperature dependent. It reduces as die temperature increases,
further compounding the severity.

7.10. Q: Does the BUK9Y29-40E fulfill the following requirements?
Table 1. Turn on/off delay, rise time and fall time requirements
SymbolParameter
Conditions

Min

Typ

Max

Unit

td(on) + tr

turn on delay time +rise time combined

Tamb = 25 °C; VDS = 30 V; VGS = 5 V;
R = 50 ; RG(ext) = 5 Ω

8

13

18

ns

td(off) + tf

turn off delay time +fall time combined

Tamb = 25 °C; VDS = 30 V; VGS = 5 V;
RL = 50 Ω; RG(ext) = 5 Ω

9

14

19

ns

A: Typical values of td(on), tr, td(off), and tf are given in the BUK9Y29-40E data sheet:
Table 2. Turn on/off delays, rise time and fall time BUK9Y29-40E specifications
SymbolParameter
Conditions
Min

Typ

Max

Unit

td(on)

turn on delay time

Tamb = 25 °C; VDS = 30 V;
VGS = 5 V; RL = 5 Ω; RG(ext) = 5 Ω

-

6

-

ns

tr

rise time

Tamb = 25 °C; VDS = 30 V;
VGS = 5 V; RL = 5 Ω; RG(ext) = 5 Ω

-

7

-

ns

td(off)turn off delay time

Tamb = 25 °C; VDS = 30 V;
VGS = 5 V; RL = 5 Ω; RG(ext) = 5 Ω

-

9

-

ns

tf

fall time

Tamb = 25 °C; VDS = 30 V;
VGS = 5 V; RL = 5 Ω; RG(ext) = 5 Ω

-

5

-

ns

td(on) + tr must be between 8 ns and 18 ns. For the BUK9Y29-40E, this value is typically 13 ns.
td(off) + tf must be between 9 ns and 19 ns. For the BUK7Y29-40E, this value is typically 14 ns.

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Minimum and maximum values for td(on), tr, td(off), and tf are not stated in Nexperia MOSFET data
sheets. It is because accurate and repeatable measurements of these parameters, particularly tr
and tf, very much depend on the test environment.
Even measurement probe positioning is critical because stray inductances, capacitances andcoupling fields change when the probe is moved (unavoidable).
A good worst case estimate tolerance on these parameters is ±50 %, however these parameters
have only a very small effect on MOSFET dynamic operation.
The typical BUK9Y29-40E fulfills these requirements, but if these parameters are slightly different,
the consequences to the circuit switching performance are not significant. In the parametric test, a
50 Ω load resistor and 5 Ω external gate resistor are used. It is very unlikely that these values are
the same as the values used in the application.
Gate drive characteristics, MOSFET capacitances and the nature of the load circuit have much
more profound effects on the dynamic switching behavior of the MOSFET. Specifically, its power
loss, efficiency and EMC performance.

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8. Package and mounting
8.1. Q: On the drawing for the power SO8/LFPAK56 common
footprint, there are no vias on the exposed pad. Are the addition ofvias advised and, if so, which diameter?
A: If improved thermal resistance is required, vias can be added to the footprint. The effect ofadding vias is discussed in Section 3.5 of AN10874.
Additional information
Nexperia has used 0.8 mm successfully but it does not mean that other sizes would not work.
The vias should be pre-filled with solder and hot air leveled, to give a flat surface, before thedevices are placed.
If the vias are not pre-filled, there is a chance that the solder under the part is drawn into thevias, which may result in voids.
The extra process steps on the PCB and the potential problems mean that vias should not be
used unless they are needed. Consult the manufacturing process engineers regarding surface
mount and soldering process issues.

8.2. Q: How are devices tested for HV isolation tests? An application
is tested at approximately 1 kV for HV isolation testing acrossvarious terminals and a significant value is seen across the MOSFET.
Are there tests that perform HV isolation analysis and, if so, what arethey?
A: We do not perform any HV isolation tests on any automotive MOSFETs or specify any HVisolation parameter in our data sheets. Insulation testing is only applicable to TO-220F packages(Nexperia SOT186A)
Additional information
HV isolation is specified for MOSFETs with insulated drain tabs or in modules with isolatedbases. The test voltage applied in the Nexperia factory is 2.45 kV for 0.4 seconds (Vrms at
50 Hz).

8.3. Q: The efficiency of my DC-to-DC converter exceeds myrequirements. Can I use smaller, higher RDSon MOSFETs to savemoney?
Environmental conditions: 4-layer FR4 board at 105 °C ambient temperature.
A: Although it is possible to reduce efficiency, other factors become the constraints.
Additional information
The dominating factor is likely to be the temperature allowed at the solder joint between the
MOSFET and the PCB. It is unlikely that 125 °C may be exceeded with FR4. If the dissipationis 2 W, the thermal resistance of the path from the MOSFET mounting base to ambient must be<10 K/W.
(125 °C - 105 °C)/2 W = 10 K/W.
Some special arrangements are required to achieve this figure. However the customer has
indicated an allowed dissipation of 2 W so they may have some more information about theirsystem indicating that it is achievable.
If dissipation is increased to 5 W, the temperature at the mounting base reaches 155 °C which
is probably not allowed. The alternative would be to improve the thermal resistance to <4 K/W,
which is extremely challenging.
An indication as to what can be achieved, is given in AN10874 and AN90003.

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The junction temperature of the MOSFET has not yet been mentioned. It is because it is only
a few degrees higher than the mounting base. For example, consider an application for an
LFPAK56 device, such as BUK7Y7R6-40E. The thermal resistance is 1.58 K/W. So for 2 W, theTj would be 128.2 °C. For 5 W, it would be 133 °C (assuming Tmb can be held to 125 °C). Bothof these values are well below the Tj(max) of the MOSFET which is 175 °C.
So in summary, the limiting factor of what can be done with dissipation is the PCB and its
thermal path to ambient, not the MOSFET.

8.4. Q: What is the position of Nexperia on using Pb free solder forinternal soldering (die attach, clip attach)?
A: Nexperia is a member of the DA5 working group. It is a project consortium comprising Nexperia,
Bosch, Infineon, and ST. The goal is to find new solder materials or alternative die attach methods
which do not use lead. The European directive 2011/65/Eu exemption (RoHS), allows the useof lead in high melting point solders until 2016. So far, no reliable and cost effective alternative
process has been developed, especially where the requirements of AEC-Q101 are considered. An
extension to the expiry date of this exemption was applied for in January 2015 by representativesof the electronics industry, including the DA5 working group.
The End of Life Vehicle (ELV) Directive (2000/53/EG) also applies. A similar extension to the
Pb free exemption was applied for by the DA5 group in November 2013. It is expected that if
approved, this directive allows the use of Pb based solders until 2018 at the earliest. It has beenrequested that the EU aligns the Pb free exemption between the ELV directive and the RoHS
directive.

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9. SPICE models
9.1. Q: Is there is a large difference between the data sheet andthe SPICE model behavior and in particular, the gate charge
characteristics?
A: There is a strong similarity between the data sheet characteristics and the Nexperia SPICE
models at 25 °C. It is especially true for transfer curve, RDSon, diode characteristic, and gatecharge. The SPICE model also accounts for the package parasitic resistances and inductances.
Additional information
In PWM circuits, the SPICE model gives quite a good similarity to the behavior of the real
device. The SPICE model can therefore be used to give a good indication of the switchinglosses at turn-on and turn-off, as well as the conduction losses.
The SPICE model is only correct at 25 °C, the RDSon versus temperature characteristic can beused to estimate conduction losses at higher temperatures. Switching losses are known not tochange significantly with temperature.
The SPICE model also reflects a typical device according to the data sheet characteristics.
The method of creating models has been continuously improved over time. The latest model
creation process used for Trench generation 6 devices and newer technologies results inmodels which closely match measured device behavior.

9.2. Q: Why does the SPICE model not match the data sheet?
A: The SPICE models provided by Nexperia are generated from measurements performed ona sample of devices. Several parameters such as transfer characteristics, output characteristics
and gate charge are used. Values for parasitic package impedances and the data sheet maximum
RDSon value are combined to produce a model that emulates the behavior of the sample MOSFETs.
•

It is important to note that the SPICE models generated by Nexperia:• represent typical parts that can be found within the production distribution.
• are set close to the maximum RDSon of the part without adversely affecting the other model
parameters.
• are only valid for Tj = 25 °C.
Customers wishing to do design validation using a SPICE model, are advised to proceed withcaution given the information provided above. Nexperia encourages designers to perform
Monte Carlo simulations and use tolerance stacks in their simulation design. These factors
permit part to part variation of their whole system to be accounted for.
Nexperia can advise on what reasonable levels of tolerance on key parameters for the
MOSFET would be.

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10. MOSFET silicon technology
10.1. Q: What is drift engineering?
A: Drift engineering is optimizing of the drift region between the bottom of the trench and the epi/
substrate interface (light green area). The drift region supports most of the drain-source voltage inthe off state. The purpose of drift engineering is to reduce the resistance of the drift region while
maintaining the drain-source breakdown voltage V(BR)DSS capability (see Fig. 24).
SourceRpackage

SourceRmetal· Package type dependent· Leadframe/bond wires (clip)
resistance· Metal spreading resistance is layout andpackage dependent

Oxide

Switch
Gate

Gate

N
P

Drift

RswitchSubstrate

Specific RDS(on)(mΩ mm2)

N
Drift Region
RdriftSubstrate

Rsubstrate

Drain

T1

T2

T3

T4

T6

Technology

Drain

aaa-016144

Fig. 24. Resistance in power MOSFETs

10.2. Q: What is obtained from reduced cell pitch?
A: Reduced cell pitch generally results in lower resistance and higher capacitance. The goalof each new generation of MOSFET technology is to reduce RDSon without a large increase incapacitance that usually accompanies reduced cell pitch. Reduced cell pitch also reduces SOA
capability (linear mode operation) but improves avalanche capability.

10.3. Q: What is obtained from a shorter channel?
A: Shorter channel gives a lower RDSon and a lower CGS capacitance simultaneously. It has higher
leakage current and the transfer curve (ID versus VGS characteristic) becomes more dependent on
VDS. It is also observed in the output characteristics.

10.4. Q: What is obtained from thick bottom oxide?
A: Thick bottom oxide refers to gate oxide at the bottom of the trench (see Figure 16). It is madethicker than the gate oxide at the side of the trench. It acts as a thicker dielectric between the gate
and the drain resulting in a much lower CGD value.

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11. Supply and availability
11.1. Q: What statements can be made concerning the long-term
availability of previous generations of TrenchMOS parts?
A: Nexperia continues to supply older products where the volumes of manufacture are
economically viable. The sales price margin is commercially viable and there are no manufacturing
reasons which prevent manufacture.
A Discontinuation of Delivery (DoD) document notifies key customers (including distributors), whena part is planned to be withdrawn. It allows customers to make arrangements to buy sufficient
products for future requirements and if necessary qualify alternative products.

12. EMC and ESD
12.1. Q: I have EMC issues, what can I do?
A: We have a detailed appliaction note on this subject, AN90011, please refer to this for any EMC
related concerns.

12.2. Q: What parameters affect the ESD tolerance and how muchdoes it vary for a particular device?
A: The key parameters are the gate oxide breakdown voltage and the gate input capacitance (Ciss).
JESD22-A114 specifies the ESD Human Body Model test arrangement and results assessment
criteria.
Additional information
The main ESD failure mechanism for any MOSFET is due to breakdown of the gate oxide. The
point where the oxide is thinnest will be where failure is most likely to occur.
For Nexperia MOSFETs, factors which affect the thickness are:••Gate rating: usually standard level or logic level (note that other gate oxide ratings are available
from Nexperia)
Technology used: gate oxide thickness will vary according to the technology used. Check with
Nexperia for details of the oxide thickness or rating if this is critical information

The gate oxide is most sensitive between the gate and source. The gate to drain path (typicallythe gate oxide at the bottom of the trench and semiconductor junction in series) offers a higher
capability.
There are 6 combinations of applying an ESD pulse to a MOSFET:
Table 3. ESD test pulses pin combinations
Pin ESD pulse applied toPin(s) grounded

Pin floating

G

S

D

G

S, D

-

D

G

S

D

G, S

-

S

D

G

S

D, G

-

The ESD pulse can be positive or negative for each condition. The simplified capacitance model for
the MOSFET shown in Fig. 25 below is key to understanding how the gate oxide can be damagedby extreme voltage

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CGD
NMOS

CDS

CGS

aaa-022333

Fig. 25. MOSFET schematic representing the internal capacitances
The worst-case condition is always by applying the pulse to the gate pin with the source pin
grounded and the drain pin floating. This has been verified by experiment. In the case of the pulse
being applied between gate and source with the drain floating, the capacitance of the device isminimised, see Fig. 26 below. Grounding the drain, for example, would increase the gate – source
capacitance, so it becomes more difficult to damage the oxide.
Note that the body diode acts to protect the drain pin of the device: if drain goes negative due to
ESD pulse on the drain, then diode conducts. The body diode is capable of handling high current,much higher than due to ESD pulses so is not damaged by ESD. If the drain goes positive, thenthe diode will avalanche and easily absorb the ESD energy (like a TVS).
Drain floating

CGD
NMOS

Gate
ESD pulse

CDS

CGS

Sourceaaa-022333

Fig. 26. MOSFET schematic representing the internal capacitances

12.3. Q: How can gate-source ESD rating be estimated?
A: This formula estimates the ESD capability:
Vesd (HBM) = 16 × VGS(max) × Ciss (nF)
Additional information
The simplest approximation for ESD is to assume that the device fails when Ciss is charged
to the breakdown voltage of the gate oxide (VBR(ox)). As a conservative estimate VBR(ox) is
approximately 1.6 times the VGS rating as per the limiting values section in the data sheet.
Fig. 27 shows the ESD test setup, once ESD test has completed then the voltage across both
capacitors is the same and total charge is conserved. At the last surviving voltage, then voltage
across the capacitors is as follows:
Vesd × Cesd = VBR(ox) × Cesd + VBR(ox) × Ciss
Vesd = VBR(ox) × (Ciss/Cesd + 1)
Vesd = 10 × VBR(ox) × Ciss
Vesd = 16 × VGS(max) × Ciss

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RC

RD

M

charge current
limit resistor

VESD HIGH VOLTAGE
DC SOURCE

discharge
resistance

Ciss
CESD
100 pF

DeviceUnder
Teststorage
capacitor

aaa-031668

Fig. 27. Test circuit for ESD testing (human body model)

12.4. Q: Does relationship between Ciss and ESD rating change bytrench generation?
Yes. As per Section 12.3 the ESD rating relies upon Ciss and gate oxide breakdown voltage.
As Nexperia improves technology and the levels of quality and reliability also improve newgenerations tend to have stronger gate oxides. However as we improve our switching figure of
merit (QG × RDSon), now for the same RDSon new technologies will have lower Ciss and therefore
lower ESD rating.

12.5. Q: Why are Nexperia power MOSFETs not ESD protected on
the chip by gate-source protection networks?
In order to effectively screen MOSFETs with weak gate oxide and achieve <1 ppm quality levels,
Nexperia uses special test techniques which involve accurately measuring the gate-source leakage
behavior. Adding ESD protection networks means that it becomes very difficult to measure thegate-source leakage characteristics of the gate oxide because the ESD protection network will
have a significantly higher leakage current. This means we cannot screen out weaker oxides andwill result in a higher field failure rates. Furthermore, adding protection networks results in higher
production costs. ESD protection networks are therefore only used where necessary.
Generally, for larger MOSFETs with good gate oxide quality and relatively high Ciss there is noneed for ESD protection, as long as these are being mounted onto a PCB in a controlled ESD
environment. For special applications where the MOSFET would be subjected directly to ESD in afinished product such as a lithium ion battery module or a power or signal port then on-chip ESD
protection may be required to meet IEC 61000-4-2 or other ESD test specifications. Some verysmall MOSFETs from Nexperia may require on chip ESD protection networks in order to allow
handling (such as NX3008NBKW), even in well controlled manufacturing environments.

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Power MOSFET frequently asked questions and answers

13. Leakage, breakdown and MOSFET characteristics
13.1. Q: How does drain current (IDSS) vary with respect totemperature?
A: The fundamental relationship between drain leakage current and temperature is exponential
in form. The data sheet gives maximum values of IDSS at Tj = 25 °C and 175 °C. This example is
specific to Nexperia Trench generation 2 technology but the same principles can be applied forother Nexperia technology. An exponential fit to these points provides the plot of Fig. 28. It is also inline with some testing which is performed during the development of new MOSFET technologies.
Fig. 29 is the same curve, plotted with a log scale for IDSS to ease reading the value of 20 μA at
50 °C. These values are for a VDS at the rated voltage. Reducing voltage reduces leakage current.
Note that Fig. 28 and Fig. 29 are not in the device data sheets.

aaa-013067

600

aaa-013068

103
lDSS
(µA)

IDSS
(µA)

102
400

10
200

1
0

0

50

100

150

Tj (°C)

0200

Fig. 28. IDSS as a function of temperature, linear axes

50

100

150

Tj (°C)200

Fig. 29. IDSS as a function of temperature, log - linear
axes

13.2. Q: What is the relationship between breakdown voltage
V(BR)DSS at ID = 250 μA) and drain leakage current (IDSS)? Both state
the same VDSS value but the drain current is different.
A: Although these two parameters reference the voltage rating of the part, they look at different
characteristics of the product. Drain leakage current (IDSS) is the current which flows when VDS
equal to the rated voltage is applied. The test checks that the current is below the limit.
The breakdown voltage of a device V(BR)DSS is the VDS required to cause a drain current of 250 μA
to flow. In practice it is slightly higher than the rated voltage of the device and the actual voltage
varies for the same nominal type due to manufacturing variations. The minimum V(BR)DSS stated in
the data sheet is the rated voltage. Breakdown voltage looks at the characteristic of the part when it
is in avalanche. The mechanisms causing leakage current and avalanche current are different.

13.3. Q: Is the standard level gate device BUK7Y28-75B guaranteed
to work with a 7 V gate drive at -40 °C for 25 A?
A: Nexperia has a high degree of confidence that this scenario would be OK even in the worst
case. However, it cannot be 100 % guaranteed by a production test at 25 °C.
Referring to Fig. 30, the typical gate threshold voltage VGS(th) is 3 V. It rises to approximately
3.5 V at -55 °C (i.e. a rise of approximately 0.5 V). The highest VGS(th) rises from approximately

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4 V to 4.5 V (again, approximately 0.5 V). So in the worst case at -55 °C, the threshold voltage
shifts by 1.5 V from the typical 25 °C value.
Looking at Fig. 31, it would shift the gate drive curve from 7.0 V to 5.5 V for a worst case device(1.5 V shift).
aaa-013069

5
VGS(th)
(V)
4

max

3

typ

2

min

1

0
-60

0

60

120

Tj (°C)180

Fig. 30. Gate threshold voltage VGS(th) as a function of temperature
aaa-013070

100

10

ID
(A)

20

80

15

8

7

aaa-013071

120
RDS(on)
(mΩ)
100

4.5

5

5.5

6

7

80
60

8

6
5.5

40

0

VGS (V) = 20 V

VGS (V) = 4.5

0

2

4

6

8

10
15

40

5
20

60

20

VDS (V)10

Tj = 25 °C

0

0

20

40

60

80

ID (A)

100

Tj = 25 °C

Fig. 31. Drain current as a function of drain-source
voltage: typical values

Fig. 32. Drain-source on-state resistance as a functionof drain current: typical values

The 5.5 V drive curve allows more than 25 A and is still in the resistive RDS(on) region of the output
characteristic. However by ~ 30 A the resistance increases rapidly as the current saturates at
40 A., hence it is not advised to exceed 25 A significantly.
The RDSon values for the 5.5 V characteristic at 25 A in Fig. 32 is pessimistic for operation at -40°C. It uses the 25 °C RDSon curves, and the carrier mobility increases with lower temperatures
making the RDSon better. The threshold voltage increase has already been accounted for.
It explains why a 7 V gate drive at -40 °C would be OK for this particular standard level gate device(BUK7Y28-75B). The same principles can be applied to other Nexperia devices. However, thecustomer must judge whether there is adequate margin in the design, as the result may be slightly
different from what is observed.

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13.4. Q: What is the lowest voltage V(BR)DSS to be expected at -40 °C
for a 40 V device using Trench generation 6?
A: The following principle could be applied to any Nexperia MOSFET technology at any breakdown
voltage rating. In the data sheet, the values for minimum drain-source breakdown voltages are
specified at -55 °C and 25 °C. The correlation between V(BR)DSS and temperature is approximately
linear over this range. Therefore, a straight line can be plotted at Temperature (-55 °C and 25 °C)
versus V(BR)DSS (at -55 °C and 25 °C).
For example: a 40 V Trench generation 6 part, has a V(BR)DSS at -55 °C of 36 V and 40 V at 25 °C.
Using linear interpolation, gives a V(BR)DSS of 36.75 V at -40 °C.

13.5. Q: What factors affect the value of drain current according to
the transfer characteristic graph for BUK9275-55A, especially overthe VGS range of 2.2 V to 3.0 V?
A: The answer to this question is not simple - there are several factors which would affect the ID
value.
1. The graph depicted in Fig. 33 is typical. The BUK9275-55A MOSFET has a distribution ofparameter values within the production tolerance limits. The graph is only intended to illustrate
how ID, VDS and VGS are related when the MOSFET is operating for a particular VDS condition.
VGS(th) has a significant influence on the characteristic of a particular device. Temperature isalso a major factor. The limiting values and characteristics listed in the data sheet should be
used for circuit design.
2. Junction temperature Tj strongly affects the ID / VGS characteristic. The graph in Fig. 33 isfor Tj = 25 °C and Tj = 175 °C. The same graph for the same part with Tj = -55 °C, would bevery different. The mode of operation preferred by the customer is with VGS in the range 2.2
V to 3 V in the saturation region before full enhancement. In this mode, the MOSFET power
dissipation is likely to be significant. As a result, the junction temperature may be high. Figure
22 demonstrates how ID changes with Tj for a given VGS value.
3. A dashed vertical red line on the graph is shown at VGS = 2.2 V. If Tj increases from 25 °C to
175 °C, ID approximately doubles (from approximately 1 A to 2 A). However, at VGS = 2.8 V(dashed vertical green line), the same junction temperature change has no effect on ID. At VGS> 2.8 V, an increase in Tj results in a decrease in ID.
aaa-015948

25
ID
(A)
20

15

10

5

0

Tj = 175 °C

01

Tj = 25 °C

2
3
VDS = 25 V

4

VGS (V)

5

Fig. 33. Transfer characteristics: drain current as a function of gate-source voltage typical values
It is clear that the relationship between the MOSFET parameters is complex and their relationshipwith the thermal environment is also complex.

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13.6. Q: Can Nexperia provide CGD, CGS and CDS numerical values
for Tj = -55 °C and Tj = +175 °C (at VGS = 0 V, VDS = 16 V)? If it is
impossible to test, a theoretical one is also acceptable. A graph isprovided in Figure 23, but it is for Tj = +25 °C.
A: Unfortunately, Nexperia cannot supply values for these capacitances at the extremes of the
MOSFET operating temperature range requested. It is due to the limitations of our parametric test
equipment. However, we can comment on how these capacitances vary with temperature and the
MOSFET terminal voltages.
Ciss is the input capacitance formed by the parallel combination of CGS and CGD, and
CGS dominates. CGS is formed across the gate oxide so it does not vary significantly withtemperature or the MOSFET terminal voltages. As CGS depends on gate oxide thickness andother defined die feature dimensions, it should not vary much between samples.
Crss is the reverse transfer capacitance which is essentially the gate-drain capacitance (CGD).
It is formed across the MOSFET body diode depletion layer. This layer becomes thicker, as thereverse voltage (VDS) across it increases. Crss increases as VDS decreases. Crss has a greater
variability than Ciss because it depends on the body diode depletion layer.
Coss is the output capacitance formed by the parallel combination of CDS and CGD. The drainsource capacitance (CDS) also dominates this capacitance. It varies with VDS in a similar way to
Crss varying with VDS and it has similar variability to Crss for the same reasons.
These relationships are illustrated on the data sheet graph depicted by Fig. 34. It has been
observed that switching losses only slightly increase at Tj(max), in the order of 10 %, since thecapacitances only marginally change. Other factors can influence switching behavior, especiallywhere the gate driver current capability changes significantly with temperature. The depletion
layer thickness varies in proportion to the square root of the absolute temperature in K and it
affects Crss and Coss.
aaa-013072

104

C
(pF)

Ciss

103
Coss
Crss

102
10-1

1

10

VDS (V)102

Fig. 34. Input, output and reverse transfer capacitances as a function of drain-source
voltage: typical values, VDS = 0 V

13.7. Q: Can Nexperia provide the minimum VGS threshold values
for Tj from -55 °C to +175 °C? A graph is already in the data sheet.
However, the numerical data of minimum values in the range of -55°C to +175 °C are required for a standard level gate threshold.
A: Worst case values of minimum and maximum VGS(th) should be used for design purposes. They
are given in the data sheet Characteristics (see Table 4).

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Additional information
Table 4. Characteristics
Voltages are referenced to GND (ground = 0 V).
SymbolParameter

Conditions

Min

Typ

Max

Unit

VGS(th)gate-source thresholdvoltage

ID = 1 mA; VDS = VGS; Tj = 25 °C

2.4

3

4

V

ID = 1 mA; VDS = VGS; Tj = -55 °C

-

-

4.5

V

ID = 1 mA; VDS = VGS; Tj = 175 °C

1

-

-

V

These values are guaranteed worst case values. In this case, the 175 °C minimum VGS(th) is notless than 1 V. The -55 °C VGS(th) is not greater than 4.5 V.

13.8. Q: Can Nexperia provide the inherent RG component value with
Tj from -55 °C to +175 °C?
A: The measured RG value is in the range of 1 Ω to 3 Ω and it does not vary significantly withtemperature. In our general MOSFET characterization, it is presently not possible to test RG over
the temperature range.
Additional information
In a circuit such as the 3-phase motor drive circuit, switching speed is not usually criticallyimportant. The PWM frequency is usually moderate (<50 kHz). However, to mitigate emissions
due to high dV/dt, the circuit designer often deliberately slows the switching of the MOSFET.
A low value (10 Ω) fixed resistor connected between the gate driver output and the MOSFET
gate helps to stabilize the gate driver voltage and damp out any voltage transients oroscillations.
Often, even higher external gate driver resistor values are chosen to slow down the gate driverand reduce the EMI effects of the MOSFET switching.

13.9. Q: How is the maximum permissible drain current estimated,
at the point of VDS = 0.1 V, from the SOA curve of the BUK9K12-60E
shown in Figure 24? Some manufacturers describe down to the VDS
value in their SOA curves.
aaa-022335

103
ID
(A)
102

Limit RDS(on) = VDS / ID
tp = 10 µs
100 µs

10
DC
1

1 ms
10 ms
100 ms

10-1
10-1

1

10

102

VDS (V)103

Fig. 35. Safe operating area: continuous and peak drain currents as a function of drain-source voltage
A: The minimum current that is expected at a VDS of 0.1 V can be calculated from the maximum(175 °C) RDSon value (26 mΩ):TN00008
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Table 5. RDSon values
SymbolParameter
RDSon

drain-source on-state
resistanceConditions

Min

Typ

Max

Unit

VGS = 5 V; ID = 15 A; Tj = 25 °C

-

9.5

11.5

mΩ

VGS = 5 V; ID = 15 A; Tj = 175 °C

-

21.5

26

mΩ

The drain current that flows with these conditions is 0.1/0.026 = 3.846 A. The maximum dietemperature is the critical factor. Do not allow it to exceed 175 °C.
However, if the RDSon is not at the top limit of the value range or the die temperature is lower, it islower. As a result, the corresponding drain current is proportionately higher.
From Table 5 the maximum RDSon is 11.5 mΩ at Tmb = 25 °C. The maximum die temperature is
likely to be higher than 25 °C in most applications.
If the mounting base temperature is maintained at 100 °C or less, the (fully ON) MOSFET cansafely carry a continuous current up to 35 A, (see Table 6).
Table 6. ID values
SymbolID

Parameter

Conditions

Min

Typ

Max

Unit

drain current

Tmb = 25 °C; VGS = 5 V

-

-

35

A

Tmb = 100 °C; VGS = 5 V

-

-

35

A

The (fully ON) MOSFET can also sustain a current pulse of 204 A for a period up to 10 μs, (seeTable 7).
Table 7. IDM values
SymbolIDM

Parameter

Conditions

Min

Typ

Max

Unit

peak drain current

Tmb = 25 °C; tp ≤ 10 μs

-

-

204

A

13.10. Q: Is the BUK7K52-60E drain current specified individually foreach (FET1 and FET2) or as a total of 15.4 A?
Table 8. Drain specifications
SymbolParameter

Conditions

Min

Typ

Max

Unit

VDS

drain-source voltage

Tj ≥ 25 °C; Tj ≤ 175 °C

-

-

60

V

ID

drain current

VGS = 10 V; Tmb = 25 °C

-

-

15.4

A

Ptot

total power dissipation

Tmb = 25 °C

-

-

32

W

A: The ratings given on the data sheet are for each individual MOSFET in this device, (see Table
8).
Although there are two MOSFETs housed within the package, they are fully electrically isolated
from each other.
However, as the MOSFETs share a common package, there is a small amount of thermal coupling
between the two MOSFET dies through the plastic package material. The heat generated by thepower dissipated in one MOSFET increases the temperature of the other, even though the othermay not be dissipating power. In an application, there is also an external thermal coupling path via
the PCB to which the device is mounted. In practice, it is the main thermal coupling mechanism
between the two dies.
To guarantee long-term reliability, it is very important that the junction temperature of either of thedies is never allowed to exceed 175 °C.
The individual MOSFET mounting bases are the main exit routes for heat generated in the dies. In
practice, the mounting bases are soldered to copper pads on a Printed-Circuit Board (PCB). They
provide the electrical connections to the MOSFET drains and heat sinking. Both MOSFETs in the
package should operate at their rated power/current when their mounting bases are maintained at
25 °C. However, it is very difficult to achieve in practice and de-rating must be done in most cases.

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Example:Using a BUK7K52-60E for two MOSFETs in a half-bridge, driving an inductive load.
Assumptions:
MOSFETs conduct alternately, never together.
Switching losses are neglected.
PCB material is standard FR4.
Standard FR4 PCB material has a maximum operating temperature of 125 °C, although special
higher temperature materials are available.
The maximum temperature of the MOSFET mounting bases is limited to 125 °C by appropriate
PCB cooling. The maximum de-rated power that can be dissipated in one MOSFET is:
32/3 = 10.67 W.
Hence, the temperature rise of the die above the temperature of its mounting base is:10.67 (W) × 4.68 (K/W) = 49.9 K.
Therefore, the maximum die temperature is 125 + 49.9 = 174.9 °C, which is marginally safe.
Worst case RDSon at Tj = 175 °C = 101 mΩ.
Maximum allowed current = √(P/RDSon) = 10.28 A.
Note: This calculation is a theoretical example. The PCB cooling required to maintain a
125 °C mounting base temperature with 10.67 W power dissipation would be very difficult
to achieve in practice.

13.11. Q: How does V plateau shift with temperature and process
variation?
Data from a T9 MOSFET family device BUK7J1R4-40H is considered but the principle can beapplied to T6 devices also. The plateau voltage in the gate charge characteristic is the horizontal
portion of the graph (Fig. 36) and is related to the transfer characteristic (Fig. 37).

VGS
(V)

aaa-026115

10

aaa-026113

360

ID
(A)
300

8

240
6
VDS = 14 V

180

32 V

4
120
2

0

25°C

60

0

10

20

30

40

50

60
70
QG (nC)80

Tj = 25 °C; ID = 25 A

0

175°C
Tj = -55°C
0

1

2

3

4

5
6
VGS (V)

7

VDS = 8 V

Fig. 36. Gate-source voltage as a function of gatecharge; typical values

Fig. 37. Transfer characteristics; drain current as afunction of gate-source voltage; typical values

The plateau voltage is around 4.25 V typical for a current of 25 A. This corresponds to the value inthe transfer curve, also for a typical device. So at -55 °C then the plateau voltage will be 4.35 V andat 175 °C it will be 3.9 V for a typical device.
Note: transconductance reduces with increasing temperature, so the device will switch alittle slower and switching losses will increase.

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When considering a “worst case” device then the spread in gate threshold VGS(th) needs to beconsidered. It is assumed that the gain (transconductance) of the device is not affected by thesame process related reasons which affect VGS(th). The transfer curve for a typical device would beshifted along the VGS axis according to the delta in the VGS(th) (Fig. 38).
The plateau voltage at the 25 A test condition would be 3.65 V for minimum VGS(th) and 4.85 V
maximum VGS(th).

Fig. 38. Transfer characteristic at 25 °C

13.12. Q: What is the current which each device can conduct andhow does this relate to the device power rating for the SOT1205
device?
A. Consider a specific example such as BUK9K52-60E. The data sheet shows the following
capability:
Table 9. Quick reference data; BUK9K52-60E
SymbolParameter

Conditions

Min

Typ

Max

Unit

VDS

drain-source voltage

Tj ≥ 25 °C; Tj ≤ 175 °C

-

-

60

V

ID

drain current

VGS = 5 V; Tmb = 25 °C

-

-

16

A

Ptot

total power dissipation

Tmb = 25 °C

-

-

32

W

The key point is the Ptot of 32 W. This is per die at data sheet conditions which assume that themounting base is maintained at 25 °C. The maximum DC current allowed in each device would be
16.04 A, based on RDSon of 124.3 mΩ (VGS= 5 V) at 175 °C.

If both devices in the package are considered then the total power dissipation when both mounting
bases are maintained at 25 °C is 32 W x 2 = 64 W. This only applies when the mounting bases ofthe devices are maintained at 25 °C (using an infinite heatsink). The power capability will decreaseas the mounting base temperatures increase such that Tj does not exceed 175 °C. Consequently
the current will decrease as shown in the graph Fig. 39 of ID vs Tmb, if the mounting base ismaintained at a different temperature such as 125 °C, the current rating would be 9.26 A.

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ID(A)

003aaj559

20

16

12

8

4

0

0

30

60

90

120

150
Tmb (°C)

180

VGS ≥ 5 V
Fig. 39. Continuous drain current as a function of mounting base temperature
In practice it is not a realistic condition to mount the device on an infinite heatsink, the device might
be mounted on a PCB with Rth(mb-amb) = 50 °C / W. In which case how can the steady state current
capability be calculated?
The diagram in Fig. 40 below shows a simplified thermal model from the junction of each die toambient. It is assumed that there is good coupling on the substrate such as a PCB between thedevices (usually the case but not always) and that there is minimal coupling between the devices
within the package (this is >100 °C / W).
Tj2

Tj1
Rth j1 to j2
100 K/W

Rth j1 to mb1
4.7 K/W

Rth j2 to mb2
4.7 K/W
Rth mb1 to mb2
5 K/W

Tmb1

Tmb2

Rth mb2 to amb

Rth mb1 to amb
100 K/W

100 K/W

Tamb

Tamb

Fig. 40. Dual MOSFET thermal configuration
If the ambient temperature is 25 °C then the maximum total package power dissipation would be
2.87 W assuming the power is shared equally between the two dies.

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This corresponds to a maximum current of 3.40 A in each device simultaneously.

This will result in a mounting base temperature of 168.2 °C. This is above the typical transition
temperature for the PCB of 125 °C. The simplified thermal resistance model can be used to
calculate the power based on the actual conditions and requirements. For highly accurate
calculations, computational fluid dynamics simulations or calibrated measurements should be
conducted.

13.13. Q: What is meant by the ID(DC) max value in the data sheet?
A. ID(DC) max is the maximum continuous drain current the device can carry as a function ofmounting base temperature with the device fully on. Fig. 41 shows the theoretical current the
MOSFET should be capable of (solid line) and the dotted line (1) is the maximum DC rated line
as a successful practical demonstration of the maximum current rating of ID when operating
continuously[1], [8], [9].
aaa-029499

500
ID
(A)
400

(1)

300

200

100

0

0

25

50

75

100

125

150 175
Tmb (°C)

200

VGS ≥ 10 V
(1) 325 A continious current has been sucessfully demonstrated during application
tests. Practically the current will be limited by the PCB, thermal design and operating
temperature.
Fig. 41. An example showing the ID(DC)max line from BUK7S1R0-40H data sheet

13.14. Q: What is meant by the IDM value in the data sheet?
A. IDM max is the peak drain current. It is the maximum drain current the device is allowed to carryfor a pulse of 10 μs or less. It is usually 4 times the maximum theoretical silicon DC current and thishas been experimentally verified[8].

13.15. Q: Can a MOSFET work above the rated maximum junction
temperature?
A. MOSFET data sheets quote a maximum rated junction temperature, typically 175 °C. MOSFETs
are qualified to be reliable at this temperature. MOSFETs will not catastrophically fail intermediately
above this temperature but reliability cannot be guaranteed.

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14. MOSFET reliability
14.1. Q: How is the FIT-rate calculated?
A: FIT (Failure In Time) is commonly used to express component reliability. It is defined as the9number of failures occurring in 1 × 10 hours (1 billion hours).
At any elapsed time (t), the reliability (R) of a group of operating semiconductors is:
R(t) = (no - nf)/no
Where:
no is the original sample size and nf is the number of failures after time t.
99Over the standard time of 10 hours, it approximates to F = (1/no)*(nf/t)*10 .
Accelerated testing
A major factor in determining the reliability of a semiconductor is the total stress applied by
the application. Operating temperature results from ambient temperature and the heat due topower dissipation. It is the most important applied operating stress where a product is otherwise
generally operated within its ratings.
The Arrhenius equation is used to model the effect of temperature on component failure rate:(Ea/k)(1/T1 - 1/T2)

Acceleration factor = e(7)

Where:
Ea = activation energy (eV)-5k = Boltzmann constant (8.60 × 10 eV / K)
T1 = operating temperature (°C)
T2 = reliability test temperature (K referenced to absolute zero)
Accelerated testing makes components perform at high levels of (thermal) stress. The results arethen extrapolated to convert short life under severe conditions into the expected life under normal
conditions.
Under accelerated life test conditions:

F = ( n f / n 0 × A × t ) × 10

9

FITs

(8)

Time t is now equal to A × t, where A is the acceleration factor.
Based on the life-test results for an example part, the FIT data provided in Table 10 has been
calculated. Note that an adjustment is made to the number of failures based on Poissons
probability distribution. It is used to indicate the number of failures expected in a larger sample
depending on the confidence level. It is described in JEDEC JEP122F Section 5.18.1.4 and innumerous other references.

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Table 10. Calculated FIT data
Test nameHigh Temperature Reverse Bias (HTRB) +High Temperature Gate Bias (HTGB) +High Temperature Storage Bias (HTSL)Test temperature

175

Number of device hours

35,051,000

Number of observed failures

0

Confidence level

90%

Activation energy

0.7

eV

°C

Unit

Failure rate
Failure rate at

125

°C

at 90 % confidence = 6.725

FIT

Failure rate at85°C

at 90 % confidence = 0.688

FIT

Failure rate at55°C

at 90 % confidence = 0.086

FIT

Failure rate at25°C

at 90 % confidence = 0.0007

FIT
Unit

MTBF
Mean time before failure at
Mean time before failure at

125
85

°C

8

at 90 % confidence = 1.49 × 10

hour

°C

9

hour

10

hour

11

hour

at 90 % confidence = 1.45 × 10

Mean time before failure at55°C

at 90 % confidence = 1.16 × 10

Mean time before failure at25°C

at 90 % confidence = 1.40 × 10

15. References
1.
2.
3.
4.
5.
6.
7.
8.
9.

AN11158 — Understanding power MOSFET data sheet parameters
AN10273 — Power MOSFET single-shot and repetitive avalanche ruggedness rating
AN11160 — Designing RC snubbers
AN90001 — Designing in MOSFETs for safe and reliable gate-drive operation
AN90003 — Thermal design guide for LFPAK56D and LFPAK33
AN50006 — Power MOSFETs in linear mode
Baliga, B. Jayant, — ‘Fundamentals of Power Semiconductor Devices’, Springer, 2008
AN50014 — Understanding the MOSFET peak drain current rating
BUK7S1R0-40H — BUK7S1R0-40H data sheet

16. Revision history
Table 11. Revision history
Rev
Date

Description

TN00008 v.720240809

Section 3.5 updated. Section 3.12 added.

TN00008 v.620230112

New topics added.

TN00008 v.5

20200623

Section 5.3 updated.

TN00008 v.4

20200608

A number of corrections made and new topics added.

TN00008 v.3

20180912

This document has been revised to use the latest Nexperia format andadditional topics added.

TN00008 v.2

20161031

A number of corrections made and new topics added.

TN00008 v.1

20150806

Initial version.

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17. Legal information
Definitions
Draft — The document is a draft version only. The content is still underinternal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any representations or
warranties as to the accuracy or completeness of information included hereinand shall have no liability for the consequences of use of such information.

Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, Nexperia does not give any
representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for theconsequences of use of such information. Nexperia takes no responsibility
for the content in this document if provided by an information source outsideof Nexperia.
In no event shall Nexperia be liable for any indirect, incidental, punitive,
special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removalor replacement of any products or rework charges) whether or not suchdamages are based on tort (including negligence), warranty, breach ofcontract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, Nexperia’s aggregate and cumulative liability towards customer
for the products described herein shall be limited in accordance with theTerms and conditions of commercial sale of Nexperia.
Right to make changes — Nexperia reserves the right to make changes
to information published in this document, including without limitation
specifications and product descriptions, at any time and without notice. This
document supersedes and replaces all information supplied prior to the
publication hereof.
Suitability for use — Nexperia products are not designed, authorized or
warranted to be suitable for use in life support, life-critical or safety-criticalsystems or equipment, nor in applications where failure or malfunctionof an Nexperia product can reasonably be expected to result in personal
injury, death or severe property or environmental damage. Nexperia and its
suppliers accept no liability for inclusion and/or use of Nexperia products insuch equipment or applications and therefore such inclusion and/or use is at
the customer’s own risk.
Applications — Applications that are described herein for any of theseproducts are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using Nexperia products, and Nexperia accepts no liability forany assistance with applications or customer product design. It is customer’ssole responsibility to determine whether the Nexperia product is suitableand fit for the customer’s applications and products planned, as well as
for the planned application and use of customer’s third party customer(s).
Customers should provide appropriate design and operating safeguards tominimize the risks associated with their applications and products.
Nexperia does not accept any liability related to any default, damage, costs
or problem which is based on any weakness or default in the customer’s
applications or products, or the application or use by customer’s third party
customer(s). Customer is responsible for doing all necessary testing for thecustomer’s applications and products using Nexperia products in order toavoid a default of the applications and the products or of the application or
use by customer’s third party customer(s). Nexperia does not accept any
liability in this respect.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a priorauthorization from competent authorities.
Translations — A non-English (translated) version of a document is forreference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.

Trademarks
Notice: All referenced brands, product names, service names andtrademarks are the property of their respective owners.

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List of Tables
Table 1. Turn on/off delay, rise time and fall timerequirements.......................................................................30
Table 2. Turn on/off delays, rise time and fall timeBUK9Y29-40E specifications............................................. 30
Table 3. ESD test pulses pin combinations........................36
Table 4. Characteristics......................................................43
Table 5. RDSon values...................................................... 44
Table 6. ID values.............................................................. 44
Table 7. IDM values........................................................... 44
Table 8. Drain specifications.............................................. 44
Table 9. Quick reference data; BUK9K52-60E...................46
Table 10. Calculated FIT data............................................50
Table 11. Revision history.................................................. 50

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List of Figures

Fig. 30. Gate threshold voltage VGS(th) as a functionof temperature....................................................................40

Fig. 1. Package terminology: mounting base and "case"..... 4

Fig. 31. Drain current as a function of drain-source
voltage: typical values........................................................40

Fig. 2. Thermal path junction to mounting base...................4
Fig. 3. Thermal path: junction to ambient............................ 5
Fig. 4. Comparison of transient thermal impedance............ 6
Fig. 5. MOSFET thermal resistance junction to ambient......8
Fig. 6. LFPAK88 (BUK7S1R0-40H) and LFPAK56E(BUK7J1R0-40H) transient thermal impedancecomparison......................................................................... 10
Fig. 7. Junction to ambient (j-amb) thermal propagation.... 10
Fig. 8. Diode characteristics...............................................12
Fig. 9. Example: BUK7Y12-55B SOA curve showing
derating for 100 °C............................................................ 15
Fig. 10. Normalized total power dissipation as afunction of mounting base temperature............................. 15
Fig. 11. Safe operating area: continuous and peakdrain currents as a function of drain-source voltage.......... 16
Fig. 12. MOSFET output characteristic: ON/OFF
trajectories where curve 1 represents RDSon
operation ON/OFF trajectory and curve 2 is linear
mode operation ON/OFF trajectory....................................18

Fig. 32. Drain-source on-state resistance as a functionof drain current: typical values...........................................40
Fig. 33. Transfer characteristics: drain current as afunction of gate-source voltage - typical values................. 41
Fig. 34. Input, output and reverse transfer
capacitances as a function of drain-source voltage:
typical values, VDS = 0 V..................................................42
Fig. 35. Safe operating area: continuous and peakdrain currents as a function of drain-source voltage.......... 43
Fig. 36. Gate-source voltage as a function of gatecharge; typical values........................................................ 45
Fig. 37. Transfer characteristics; drain current as afunction of gate-source voltage; typical values.................. 45
Fig. 38. Transfer characteristic at 25 °C............................ 46
Fig. 39. Continuous drain current as a function ofmounting base temperature............................................... 47
Fig. 40. Dual MOSFET thermal configuration.................... 47
Fig. 41. An example showing the ID(DC)max line fromBUK7S1R0-40H data sheet............................................... 48

Fig. 13. Simplified planar and trench technology............... 19
Fig. 14. Avalanche safe operating area............................. 23
Fig. 15. Inductive load: body diode avalanche
breakdown and active clamping........................................ 24
Fig. 16. Power MOSFET showing two possible
mechanisms for dV/dt induced turn-on.............................. 26
Fig. 17. Physical origin of the parasitic BJT
components that may cause dV/dt induced turn-on...........27
Fig. 18. Trench generation 6 structure...............................27
Fig. 19. Blue VGS trace shows gate bounce and thered current waveform spiking when gate bounce occurs... 28
Fig. 20. MOSFET Schematic representing the internal
capacitances.......................................................................28
Fig. 21. Simplified schematic of a MOSFET halfbridge. The high-side and low-side MOSFETs are
switched antiphase to each other...................................... 29
Fig. 22. Waveforms showing the full detail of the gate
bounce phenomenon......................................................... 29
Fig. 23. Effect of RG on VGS, and shoot-through current.. 30
Fig. 24. Resistance in power MOSFETs............................ 35
Fig. 25. MOSFET schematic representing the internal
capacitances.......................................................................37
Fig. 26. MOSFET schematic representing the internal
capacitances.......................................................................37
Fig. 27. Test circuit for ESD testing (human body model).. 38
Fig. 28. IDSS as a function of temperature, linear axes.....39
Fig. 29. IDSS as a function of temperature, log - linear
axes.................................................................................... 39

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5. Safe operating area and linear mode operation....... 13

Contents
1. Introduction................................................................... 2
2. Gate................................................................................2
2.1. Q: Why is the VGS rating of Trench 6 automotive
logic level MOSFETs limited to 10 V and can it beincreased beyond 10 V?...................................................... 2
2.2. Q: Why is VGS maximum limit of Trench 9
automotive logic level MOSFETs different to previous
generations?.........................................................................3
2.3. Q: What is the gate oxide capability for a logic
level MOSFET (data sheet says only 10 V, will it breakat 11 V?).............................................................................. 3

5.1. Q: The current derates with temperature. Is thislimit based on power dissipation?......................................135.2. Q: Is it necessary to de-rate any limit (current,
voltage, power etc.) to achieve high reliability?................. 13
5.3. Q: How do I de-rate an SOA graph fortemperatures other than 25 °C?........................................ 15
5.4. Q: Is there a Spirito boundary limit line for linear
mode operation?................................................................ 16
5.5. Q: Regarding the SOA curve for the 1 ms and
10 ms curves, there is a bend-down at higher voltages
and low currents. Why does this bending disappear for
longer and shorter pulse times?........................................ 16

3. Thermals........................................................................4

5.6. Q: How does Nexperia ensure compliance with
the SOA curve during series production?.......................... 17

3.1. Q: What’s the difference between Rth(j-mb) andRth(j-amb)?.............................................................................. 4

5.7. Q: How can a part be identified when it isdesigned for linear mode operation?................................. 17

3.2. Q: When comparing Zth curves in some data
sheets, there appear to be some contradictions. Froman Rth point of view, the BUK9Y38-100E (Trench
generation 6) looks better (lower). However, from a Zth(at less than 100 ms) point of view, the BUK9Y30-75B(Trench generation 3) looks better. The shape of thegraphs indicates that a more advanced model ormeasurement was done on the Trench generation 6
part. Is this assumption correct?..........................................55.8. Q: For parts designed for linear mode operation,
are there any restrictions (such as the Spirito boundary)?.17

3.3. Q: It is understood that the values forthermal resistance listed in data sheets are basedon controlled conditions that do not apply to typicalapplications. If this understanding is true, how is
the proper thermal resistance/junction temperatureaccurately calculated?..........................................................6
3.4. Q: What effect does changing the device have onRth(j-amb)?.............................................................................. 8
3.5. Q: Why is there no Rth(j-amb) in the data sheet?........... 93.6. Q: How can I achieve the Rth(j-mb) – I try to put the
rated power in the device, but the junction is getting
too hot?................................................................................ 9
3.7. Q: Why is there no Rth(j-case) in the data sheet?...........93.8. Q: Can I measure Tj from Tcase?................................. 9
3.9. Q: Why can an LFPAK88 have higher Rth(j-mb)
than an LFPAK56E?............................................................ 93.10. Q: Does the LFPAK88 have better or worse
thermal impedance than LFPAK56?.................................... 9
3.11. Q: How much power can a MOSFET dissipate
on FR4?............................................................................. 10
3.12. Q: What are the conditions used to derive Rth(jamb) in Automotive MOSFET data sheets?........................ 11
4. MOSFET body diode.................................................. 124.1. Q: How much current can the MOSFET body
diode carry?....................................................................... 124.2. Q: What is the importance of the Qr parameter?........13
4.3. Q: What is the gate oxide capability for a logic
level MOSFET (data sheet says only 10 V, will it breakat 11 V?)............................................................................ 13

5.9. Q: Can modern MOSFETs be used in linear mode?.. 18
6. Avalanche ruggedness and Unclamped
Inductive Switching (UIS)................................................ 19
6.1. Q: Are trench designs susceptible to the UIS
issue (parasitic BJT turn-on)?............................................19
6.2. Q: Why are planar designs susceptible to failure
during UIS?........................................................................ 19
6.3. Q: How are parts constructed to minimize failure
during UIS?........................................................................ 19
6.4. Q: Is 100 % UIS testing required on MOSFETs?....... 20
6.5. Q: I have parts not capable of parasitic BJT turnon. Why?............................................................................ 20
6.6. Q: What is the chart accuracy for avalanche
current versus time in avalanche, or energy versus
junction temperature?........................................................ 20
6.7. Q: For energy versus junction temperature
charts (if applicable), how is the inductance, maximum
current, time in avalanche etc., determined from thechart?..................................................................................20
6.8. Q: Are repetitive avalanche ratings the same as
for a single pulse?............................................................. 20
6.9. Q: Are there any special failure modes
associated with repetitive avalanche?............................... 21
6.10. Q: How does the increase in cell density affectavalanche capability of MOSFETs?................................... 21
6.11. Q: How many times can a device sustain single
avalanche events?............................................................. 21
6.12. Q: Is it possible for the avalanche current on
a device to exceed the package maximum current but
not the die maximum current?........................................... 22
6.13. Q: How is the avalanche rating on the body
diode obtained (testing or modeling)? If it is tested,
how is it tested and what circuit model is used?................ 22
6.14. Q: How is the repetitive avalanche safe
operating area derived in the data sheet graph? The

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repetitive avalanche SOA curve seems to be the sameas single-shot Tj = 170 °C................................................. 2210.2. Q: What is obtained from reduced cell pitch?.......... 35

6.15. Q: What is the difference between avalanche
breakdown and active clamping for inductive loads?......... 23

10.4. Q: What is obtained from thick bottom oxide?......... 35

7. Capacitive dV/dt issues............................................. 25

10.3. Q: What is obtained from a shorter channel?.......... 35
11. Supply and availability............................................. 36

7.1. Q: Is there a particular capacitance or charge
ratio that should be used to prevent turn-on, or is it
circuit dependent?..............................................................25

11.1. Q: What statements can be made concerning
the long-term availability of previous generations ofTrenchMOS parts?............................................................. 36

7.2. Q: How are parts constructed to minimize thiseffect?................................................................................. 25

12. EMC and ESD........................................................... 36
12.1. Q: I have EMC issues, what can I do?.................... 36

7.3. Q: How is dV/dt characterized?.................................25

12.2. Q: What parameters affect the ESD tolerance
and how much does it vary for a particular device?........... 36

7.4. Q: What diode or other parameters are important
to assess susceptibility? For example, maximum dV/dt
and maximum IF.................................................................25
7.5. Q: Is trench technology sensitive to thisphenomenon?.....................................................................26
7.6. Q: Does a soft recovery body diode give lower
dV/dt and if so, how is it designed and fabricated into
the part?............................................................................. 26
7.7. Q: How does temperature influence thissensitivity to dV/dt and why?............................................. 26
7.8. Q: Can Nexperia provide RB, CDB, VBE saturation
values in the parasitic BJT model, as shown in Figure 11?26
7.9. Q: In a half-bridge configuration one MOSFET isdriven off, and the second MOSFET begins to turn on.
The first MOSFET that should be off is turning back onagain causing cross conduction and an over-current
peak. What could be the cause? See Figure 13 forphenomena.........................................................................28
7.10. Q: Does the BUK9Y29-40E fulfill the following
requirements?.....................................................................30

12.3. Q: How can gate-source ESD rating be estimated?.37
12.4. Q: Does relationship between Ciss and ESD
rating change by trench generation?................................. 38
12.5. Q: Why are Nexperia power MOSFETs not
ESD protected on the chip by gate-source protection
networks?........................................................................... 38
13. Leakage, breakdown and MOSFET
characteristics.................................................................. 39
13.1. Q: How does drain current (IDSS) vary withrespect to temperature?.....................................................39
13.2. Q: What is the relationship between breakdown
voltage V(BR)DSS at ID = 250 μA) and drain leakage
current (IDSS)? Both state the same VDSS value but thedrain current is different..................................................... 39
13.3. Q: Is the standard level gate device
BUK7Y28-75B guaranteed to work with a 7 V gate
drive at -40 °C for 25 A?................................................... 39

8. Package and mounting.............................................. 32

13.4. Q: What is the lowest voltage V(BR)DSS to be
expected at -40 °C for a 40 V device using Trench
generation 6?..................................................................... 41

8.1. Q: On the drawing for the power SO8/LFPAK56
common footprint, there are no vias on the exposed
pad. Are the addition of vias advised and, if so, whichdiameter?............................................................................32

13.5. Q: What factors affect the value of draincurrent according to the transfer characteristic graphfor BUK9275-55A, especially over the VGS range of
2.2 V to 3.0 V?.................................................................. 41

8.2. Q: How are devices tested for HV isolation
tests? An application is tested at approximately 1 kV
for HV isolation testing across various terminals anda significant value is seen across the MOSFET. Are
there tests that perform HV isolation analysis and, if
so, what are they?............................................................. 32

13.6. Q: Can Nexperia provide CGD, CGS and CDS
numerical values for Tj = -55 °C and Tj = +175 °C (atVGS = 0 V, VDS = 16 V)? If it is impossible to test, atheoretical one is also acceptable. A graph is provided
in Figure 23, but it is for Tj = +25 °C..................................428.3. Q: The efficiency of my DC-to-DC converter
exceeds my requirements. Can I use smaller, higher
RDSon MOSFETs to save money?......................................32
8.4. Q: What is the position of Nexperia on using Pb
free solder for internal soldering (die attach, clip attach)?..33
9. SPICE models............................................................. 34
9.1. Q: Is there is a large difference between the data
sheet and the SPICE model behavior and in particular,
the gate charge characteristics?........................................ 34
9.2. Q: Why does the SPICE model not match thedata sheet?........................................................................ 34
10. MOSFET silicon technology.................................... 35

13.7. Q: Can Nexperia provide the minimum VGS
threshold values for Tj from -55 °C to +175 °C? A
graph is already in the data sheet. However, thenumerical data of minimum values in the range of -55°C to +175 °C are required for a standard level gate
threshold.............................................................................42
13.8. Q: Can Nexperia provide the inherent RG
component value with Tj from -55 °C to +175 °C?.............43
13.9. Q: How is the maximum permissible draincurrent estimated, at the point of VDS = 0.1 V, from the
SOA curve of the BUK9K12-60E shown in Figure 24?
Some manufacturers describe down to the VDS value
in their SOA curves............................................................43

10.1. Q: What is drift engineering?...................................35

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13.10. Q: Is the BUK7K52-60E drain current specified
individually for each (FET1 and FET2) or as a total of
15.4 A?...............................................................................44
13.11. Q: How does V plateau shift with temperatureand process variation?.......................................................45
13.12. Q: What is the current which each device canconduct and how does this relate to the device power
rating for the SOT1205 device?.........................................46
13.13. Q: What is meant by the ID(DC) max value inthe data sheet?.................................................................. 48
13.14. Q: What is meant by the IDM value in the data
sheet?.................................................................................48
13.15. Q: Can a MOSFET work above the rated
maximum junction temperature?........................................48
14. MOSFET reliability.................................................... 49
14.1. Q: How is the FIT-rate calculated?..........................49
15. References................................................................ 50
16. Revision history........................................................50
17. Legal information......................................................51© Nexperia B.V. 2024. All rights reserved

For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 9 August 2024

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