Nexperia

Efficient prediction of ESD discharge current according to
OPEN Alliance 100BASE-T1 specification using SEED

Sergej Bub, Jan Preibisch, Jennifer Schütt, Steffen Holland, and Ayk Hilbrink

Abstract – In this paper the “ESD Discharge Current Measurement” recommended in [1] is modelled using SEED
methodology and compared with measurement. The characterisation and implementation of SEED model blocks(see Fig. 1) are discussed. Special attention is given to modelling of the common mode choke and external
ESD protection device because they are important factors determining the system-level ESD robustness of theoverall system. The transient system-level response on ESD pulses as well as the residual currents into IC are
evaluated using TLP and ESD generator models.

System PCB
IIC+(ESD)IESD
ESD-GunESDprotection

CMT

De-capsIext-ESDCMC

IC

IIC-(ESD)

Figure 1 - Equivalent circuit block diagram of SEED model for the ESD Discharge Current Measurement reference circuit. A detailed
description of each system model block will be given in Section II.

Introduction
Automotive Ethernet in the form of 100BASE-T1 according
to OPEN Alliance is getting more and more popular and will
be used by various car OEMs all around the world. In the
document [1] OPEN Alliance is proposing a measurement
called “ESD Discharge Current Measurement” which gives
an estimation of the overall system-level ESD robustness ofthe system. This test determines the residual current into
the PHY1, identifying the ESD robustness class according tohuman body model requirements [2].
System efficient ESD design (SEED) is a modelling
methodology aiming to predict the ESD robustness of asystem, evaluating transient currents and voltages during
an ESD event [3-6]. It is based on equivalent circuit andbehavioural models. Transmission Line Pulse (TLP) [7] andNetwork Analyser measurements are typically used as input
for characterisation of an individual element or system part.
Together with an appropriate model for the ESD generator,
the methodology has been used to study ESD events on
system-level for high-speed data transfer applications suchas USB3 [8].

In this paper, we are applying the SEED methodology toreplicate the ESD Discharge Current Measurement Test
recommended for 100BASE-T1 application. This analysis
allows to draw conclusions on how different parameters likeparasitic inductance of the external ESD protection device,
its trigger and snap-back behaviour influence the systemlevel ESD robustness. Furthermore, it allows to predict
the electromagnetic stress other passive devices in theapplication are exposed to during an ESD event.
The paper is structured as follows: Section II describes
the used test setup. Section III introduces the SEED
model derived from the measurement setup and show
characterisation and simulation results of each model block.
The outcome of the system model verification with ESD
generator is analysed in Section IV.
1

PHY stands for physical layer interface and refers to the transceiver.

Whereas the CMC is a single device with an inductanceof 200μH, the ESD device can be a single device which
integrates matched ESD protection for both data lines(used in this paper) or two separate devices each connected
between GND and one of the data lines. The PHY is replacedby the “Transceiver Emulation Network” retaining theelectrical behavior during the ESD test. In contrast to [1],here, a 2 Ω and a 50 Ω resistors are used. The 2 Ω resistor
emulates the typical behavior of the IC internal protection
in a simplified way, meanwhile the 50 Ω resistor minimizes
the measurement effort of the IC current. The CMT network,
located between the CMC and external ESD protection
devices, consists of four discrete elements: two 1 kΩ resistors
are connected together between the data lines. The middle
contact between those resistors and GND is accomplished
via a capacitor of 4.7 nF and a resistor of 100 kΩ in parallel.
The CMT network is followed by two 100 nF capacitancesused for decoupling. The input of the test board is directly
connected to the ESD device. The output connectors behindthe “Transceiver Emulation Network”
To measure the ESD Discharge current according to [1] the
MDI ground is connected to a ground plane with a minimum
size of 0.5 m by 0.5 m. The outputs are connected via a
50 Ω RF attenuator to an oscilloscope. The ESD pulse will
be generated by an ESD generator (ESD gun) whose tip isin direct contact to one of the input pins. Following theIEC61000-4-2 [9] the setup of the ESD is C = 150 pF and R =330 Ω. For 4kV and 6kV the discharge current is measured
and for passing the specification the limits according to [1]need to be fulfilled.

SEED Simulation
SEED is developed to perform system-level ESD analysis
using transient simulations. To do so, it is essential to havean appropriate model for each part of the target system.
Figure 1 shows schematically all necessary SEED model parts
implemented here.
To reduce the modelling effort and accelerate the simulation
process, a behavioural modelling approach is used. The
model is tuned on the device typical static and dynamic
characteristics. The model is implemented in form of anequivalent circuit consisting of lumped elements, controlled
sources and feedback loops, and S-Parameters blocks.
The Advanced Design System (ADS) from Keysight is usedhere to perform system-level transient analysis.
Characterisation and Modelling of the ESD Generator
To perform system-level simulations and achieve good
agreement with measurements a model of the ESD
generator has to be configured and tuned. The model usedhere is based on proposals discussed in [10]. The parametersof this model are tuned to fit the simulated current waveformon the measured waveform of the ESD generator. Here, aNoiseKen ESD generator was used. The calibration is done
according to IEC61000-4-2 [9]. The reference waveform forthe tuning of the model of the ESD generator is obtained
from a 2 kV discharge into a 2 Ω Pellegrini target fixed on thelarge coupling plane. The resulting current waveform was
captured at the gun tip with a F-65 current probe.
4.0

Measurement
Simulation

3.5
3.0

Current (A)ESD Discharge Current Measurement According
to OPEN Alliance
To measure the current which flows into a PHY during an ESD
event, a special PCB is recommended by the OPEN Alliance[1]. This test network resembles the Medium Dependent
Interface (MDI) where the PHY is replaced with a resistor
network. The block diagram in Fig. 1 shows the different
blocks of the MDI. It consists of an external ESD device, thecommon mode termination (CMT) elements, a decoupling
network, a common mode choke (CMC) and a 100BASE-T1
PHY (IC). A photograph of the used PCB is depicted in Fig. 2.

2.5
2.0
1.5
1.0
0.5
0.0
0

10

20

30

40

50

60

70

80

90

100

time, nsec

Figure 3 - Model and measurement of ESD generator waveform
at 2 kV on a 2 Ω reference target.

Figure 3 shows a comparison between simulated andmeasured time domain current curves in both first andsecond peak regions for a 2 kV discharge. A good agreementwith measurement can be observed.

Figure 2 - Photo of reference PCB, in the size of 10.25 cm by 5.95 cm,
for ESD Discharge Current Measurements.

14

Characterisation and Modelling of the Decoupling andTermination Network
The common-mode termination network and decoupling
capacitors are represented in the simulation using lumped
elements. The decoupling capacitors of 100nF separate the
IC and the connector pins galvanically. Furthermore, theyprotect against slow pulses, e.g. Surge [11], but not against
fast ESD pulses.

Simulation
Measurement (700V)

12Measurement (500V)
Measurement (300V)

10

Measurement (100V)

Current (A)

8
6
4
2

For characterisation of the CMC the TLP test method [7]was applied. The time domain IV-curves depicted in Figures
4 and 5 show the typical response of the CMC at different
TLP voltages. Here, we can clearly identify three regions ofresponse: dynamic (I), static or small-signal (II) and saturation(III) region.

800

Simulation
Measurement (700V)
Measurement (500V)

600

Measurement (300V)

0
-2
-20

20

40

60

80

100

120

Figure 5 - Current response of CMC on TLP pulses with 600ps rise and100ns duration time at different voltage levels with dynamic (I), staticor small-signal (II) and saturation (III) region.

Figure 6 summarizes the static and saturation regions fordifferent TLP voltages. Each point of the depicted IV curve
represents an averaged value of corresponding current andvoltage time domain curves as shown exemplary in Figures 4
and 5, evaluated in a window from 70 to 90 ns.
For better protection of the IC against high ESD currents, it
is important that the external protection triggers before the
CMC goes into saturation mode. The high voltage drop over
the CMC allows the external protection device to trigger.
20

Resistive
region15

Saturation
region10~2 ohm5

Small-Signal
regionMeasurement (100V)

0400

Voltage [V]0time, nsec

TLP Current (A)Characterisation and Modelling of CMC
A CMC of 200μH is recommended to be used in the IC
protection circuitry according to the specification [1]. The
model for the CMC is divided into a small-signal and a largesignal part. The small-signal model can be derived from a
S-parameters measurement of the CMC. A fitted lumped
circuit model could also be used in order to speed up thesimulation time [12]. Here, the measured S-Parameters
are imported directly into the simulation tool. Since
S-Parameters only enclose the small-signal behaviour,
partly including dynamic response and completely ignoring
the saturation effect, an extended model is developed to
improve dynamic and include saturation behaviour as well. As
already shown in [13], the dynamic behaviour of the external
ESD protection as well as the impact of the inductance,
here the CMC, are crucial for the accurate prediction of thecurrent waveforms at the IC.

~50% margin

Vt_ext_ESD

200

-5
0

0

50

100

150

200

TLP Voltage (V)

-200
-20

0

20

40

60

80

100

120

time, nsec

Figure 4 - Voltage response of CMC on TLP pulses with 600ps rise and100ns duration time at different voltage levels with dynamic (I), staticor small-signal (II) and saturation (III) region.

Figure 6 - TLP graph for CMC, voltage and current are averaged
between 70 and 90 ns. At 240 V the CMC goes into saturation. In
an effective ESD protection concept, the external ESD protection
should trigger before the CMC goes into saturation.

Therefore, it must be made sure that the ESD protection
device triggers first. This CMC brings a reasonable safetymargin between the trigger point of the external ESD
protection used here at 120 V and the 240 V where the CMC
starts to saturate. However, it is not sufficient to consider
only the static part of the CMC IV-curve for prediction of theoverall system robustness.

250

The dynamic response of the choke itself, see Figure 4, plays
a crucial role in the validation of the peak currents flowing
into the IC during the first peak of the ESD event. Figure 7
illustrates this dynamic behaviour of the choke by showing the
maximum current vs the peak voltage.

Saturation(2. Peak current
dominates)

14
12
10
8

4
2

15

0

Resistive

10

0

Simulation

16

6

20

5

Measurement

18

Current [A]25

Peak Current (A)20

Small-signal(1.Peak current
dominates)

0.2

0.4

0.6

0.8

1.0

Peak Voltage (V)Figure 7 - TLP graph for CMC based on peak voltage and current.

In contrast to Figure 6, current and voltage are not averaged,
but peak values are taken. For the correct evaluation of thesystem behaviour during the first peak of ESD pulse, thegreen trend line related to the development of the current
overshoot produced by CMC should be modelled accurately.
For modelling of the full CMC behaviour the S-Parameters
based CMC model (small-signal model) is extended with
two additional model blocks. The first block is responsible
for transition from static into saturation region, whereby
the resistance change of the CMC signal through path ismodelled. To realize this, a voltage controlled changeable
resistor (voltage controlled switch) is added in parallel tothe main model. For determination of the onset time of thesaturation effect a RC network is used to control the stateof the switch in dependence of the input voltage level andrise time.
A feedback loop keeps the switch control circuit in a definedcondition during the whole ESD event duration. To control
the increase time and decay time of the voltage and current
pulse of the CMC, an inductor is connected in series withthe switch. The second block added to the small-signal
CMC model improves the representation of the dynamic
behaviour, which mainly governs the voltage overshootgenerated by the CMC. This is implemented by adding of arise time filter into the signal path of the full CMC model.
The overall model is fitted by variation of the parameters
related to each model block.
Figures 4 and 5 show how the simulated voltage and current
time domain curves are matching very well the corresponding
measurements of the CMC. The resulting IV-curve of thetuned model is depicted in Figure 8.

0

50

100

150

200

250

Voltage [V]Figure 8 - Measured and simulated graph for CMC, voltage andcurrent are averaged between 70 and 90 ns of 100ns TLP pulses.

Characterisation and Modelling of External ESD Protection
According to the specification [1], the external ESD
protection is placed near the system board connector. In thisposition, it can guarantee a certain robustness level of theoverall system, protecting not only the IC but all discrete
components located in the signal path e.g. capacitors andthe CMC. In order to predict the behaviour of the system andits robustness at different ESD levels, a precise model of theexternal ESD protection is needed. Here, a silicon based ESD
protection2 with a trigger voltage of Vt = 120 V, a snap-backvoltage of Vh = 32 V and a dynamic resistance of Rdyn = 0.1 Ω
is used.
For the implementation, the static as well as the dynamic
behaviour of the chosen ESD protection device arecharacterized and modelled. For this purpose, an improved
dynamic model based on the approach described in [6] isused.
The static behaviour of the ESD protection device,consisting of leakage, snapback (turn-on), linear and nonlinear (thermal unstable) regions, is modelled with help of
voltage controlled switches and a diode SPICE model. The
RC network and feedback loop are responsible for the stateof the switches during a second peak of the ESD pulse. The
dynamic behaviour of the model is implemented via two
RC integration networks combined in a way to control thevoltage drop over ESD protection as well as its decay time
during the first peak of the applied ESD pulse.
The main advantages of the extended dynamic model arecorrect representation of the thermal behaviour of the
ESD protection device and a more accurate description ofboth the effect of conductivity modulation and inductive
overshoot. In this paper, the conductivity modulation effect isof highest importance for the representation of the voltage
overshoot which occurs on the external protection side andwill be translated over the CMC to the IC I/O pin in form ofpeak current.

By following the procedure described in [6], the improved
dynamic model is fitted to TLP measurement data as shownin Figure 9.
20

1.0
0.9
0.8
0.7
0.6

15

0.5

Turn - on Region

0.3
0.2

10

0.1
160

150

140

130

120

110

90

80

70

60

50

40

30

20

0

5

100

0.0
10

Current [A]0.4

Reference Board without External ESD Protection
Figure 11 shows TLP measurements of the reference system,
see Figure 2, including CMT, decoupling capacitors, CMC
and IC network, excluding external ESD protection andcompares them with simulation results achieved using all
the corresponding parts of described SEED model. Here, theESD generator model and the model of the external ESD
protection are not used. The TLP pulse is modelled with an
ideal pulse source and 200ps rise time filter, whereby themodelled pulse form is optimised on the captured pulse of
the target system at 100V TLP. The simulation resamples themeasurements to a high degree.

Simulation
Measurement20

Measurement
Simulation

0
20

60

40

80

100

15

120

Voltage [V]Figure 9 - Measured and simulated graph for external silicon-based ESD
protection, voltage and current are averaged between 70 and 90 ns.

Current [A]

0

10

5

In order to evaluate the dynamic characteristics of the ESD
device like conductivity modulation and inductive overshoot,special attention has to be given to the voltage and current
peaks which occur during the first nanoseconds of the applied
ESD pulse. In Figure 10, the peak voltage vs. TLP current
is shown. A strong conductivity modulation effect can beobserved. The improved dynamic model is capturing thiseffect very well.

0

50

100

150

200

250

300

Peak Voltage [V]Figure 11 - Measured and simulated graph for unprotected referenceboard, voltage and current are averaged between 70 and 90 ns of
100ns TLP pulses.

Reference Board with External ESD Protection
In Figure 12, the TLP graph of a reference board with external
ESD protection is shown in comparison with simulation results
using SEED. The simulation reproduces the measurement data
to an extraordinary degree.

20

15

Current [A]0Voltage Overshoot(Conductivity Modulation)
10

25

Measurement
Simulation

5

20

Simulation

0

50

100

150

200

250

300

350

Peak Voltage [V]Figure 10 - Measured and simulated graph for external silicon-based
ESD protection lean on peak voltage and current of 1ns rise time TLP
pulses.

Verification of System Model
After introducing the parts of the SEED model, the complete
system model, see Figure 1, is validated against measurementsof a reference board with and without external ESD protection
using TLP.

Current [A]Measurement
0

15

10

5

0
0

25

50

75

100

125

150

Peak Voltage [V]Figure 12 - Measured and simulated TLP graph for the reference board
with external ESD protection device, voltage and current are averaged
between 70 and 90 ns of 100ns TLP pulses.

Based on the results we can conclude that the implemented
SEED model is fully suitable not only for qualitative but
also quantitative prediction of the overall system-levelrobustness. Moreover, it can be used for preliminary tests
using different system blocks and components. Therefore, inthe next Section, this system model will be tested using ESD
Gun model, whereby the transient residual current flowing
into the IC will be evaluated.
Application
In real environment an ESD event may occur during humanbeing touches the GND or I/O pin(s) of the system board
connector. In this case, IEC61000-4-2 ESD pulses [9] will be
injected into the system and generate transient currents
which may destroy the system IC. Therefore, the ESD
generator model will be applied to demonstrate the ability ofthe proposed SEED model, which was discussed and verified
in Section III, to replicate the real ESD scenario emulated withhelp of ESD generator.
Figures 13 and 14 show results for positive ESD gun dischargeof 4 kV level. In this case ESD generator model and external
ESD protection model are used within the SEED model.
5Class II (JEDEC-HBM 2kV PHY)
Class I (JEDEC-HBM 4kV PHY)
SIM.: ESD current @IC PA, + 4kV
Meas.: ESD current @IC PA, + 4kV

4Current [A]

3
2
1
0
-1
-2
0

1

2

3

4

5

6

7

8

9

10

11

12

Time [ns]Figure 13 - Zoom in dynamic overshoot region of measured andsimulated graph for the reference board with external ESD protection
device for ESD gun discharge of +4kV.

5Class II (JEDEC-HBM 2kV PHY)
Class I (JEDEC-HBM 4kV PHY)
SIM.: ESD current @IC PA, + 4kV
Meas.: ESD current @IC PA, + 4kV

4Current [A]

3

1
0
-1
-2
10

20

30

40

50

60

70

80

90

Time [ns]Figure 14 - Measured and simulated graph for the reference board
with external ESD protection device for ESD gun discharge of +4kV.

The observed deviations between the simulated andmeasured results can be explained by electromagnetic
coupling effects, which are not encountered in theactual SEED model, i.e. effects related to crosstalk orelectromagnetic radiation of ESD generator relay. In suchcase, the maximal current measured at the IC I/O pin(s) may
be destructively attenuated by virtue of coupling effects
between the ESD gun and the test board components likeboard traces, CMT network or CMC.
To minimize these effects an additional effort could be spend
to improve the shielding of the board from the direct impactof the relay, here the ESD generator has not been shieldedagainst the DUT. Also, to improve the modelled behaviour ofthe system an S-Parameters model of PCB may be added to
the SEED model.
Conclusion
The application of SEED methodology on a such complex
circuit like 100BASE-T1, which consists of diverse
components modelled using sophisticated approaches
aiming to replicate both static and especially dynamic
behaviour of the whole system, has proven to be a goodsolution for estimation of the overall system transient
response under ESD conditions. Furthermore, it can beused for the prediction of the system-level ESD robustness
according to IEC61000-4-2 [9] and evaluation of the IC
robustness according to JEDEC-HBM [2] requirements.
The SEED model developed and verified in this paper may
be used to study the impact of variation of system andexternal ESD protection device parameters to achieve theoptimal protection of the system IC in order to minimize theengineering and verification time.
Acknowledgements
For providing of the test board for ESD verification tests anddetailed information about measurement setup used in [1],we want to thank Bernd Körber from University of Applied
Sciences Zwickau (Westsächsische Hochschule Zwickau).

20Both graphics demonstrate the resulting simulated current
curves in time domain concurrently showing the measured
current at IC I/O pin. The yellow and red dashed lines show
the limits of the I and II Class of the JEDEC-HBM standard [2]accordingly. The used SEED model provides an estimation of
the tested system predicting ca. 20% higher maximal current
peak. For the static part of the curve however, the simulation
rather underestimates the measurement. Despite thisdeviations, the proposed SEED model shows to be applicablefor the modelling of this measurement setup.

100References[1] 	OPEN Alliance, “IEEE 1000BASE-T1 EMC Test Specification for
ESD Suppression Devices”, Version 1.0, date 27.10.2017. Available
online: http://www.opensig.org/download/documen t/216/
OA+100Base-T1_ESD+device+Test+ Specification+v1.0_11_17.pdf[2]	JESD22-A114F, JEDEC Standard, Electrostatic Discharge (ESD)
Sensitivity Testing Human Body Model (HBM)[8]	G. Notermans, H.-M. Ritter, B. Laue, S. Seider, “Gun testsof a USB3 host controller board”, 38th Electrical Overstress
Electrostatic Discharge Symposium (EOS/ESD), 2016.
[9]	IEC61000-4-2, Edition 2.0 International Standard,
ESD Immunity Test, 2008.

[3] 	JEDEC 2011. JEP-161, System Level ESD Part 1: Common
Misconceptions and Recommended Basic Approaches.

[10]	S . Yang and D. J. Pommerenke, “Effect of Different Load
Impedances on ESD Generators and ESD Generator SPICE Models”,
IEEE TRANSACTIONS ON ELECTROMAGNETIC[4] 	JEDEC 2013. JEP-162, System Level ESD
Part 2: Implementation of effective ESD robust designs.

[11] 	IEC61000-4-5, Second edition International Standard,
Surge Immunity Test, 2005.

[5]	G. Notermans, S. Bub, and A. Hilbrink, “Predicting system level
ESD performance”, 32nd Conference on Modelling and Simulation,
2018.

[12]	S. Mortazavi, D. Schleicher, F. Schade and F. Gerfers.
„Charakterisierung der Gleichtaktdrossel für Multi-GigKommunikation in Automotive-Ethernet-Netzwerken“, Kongress
für Elektromagnetische Verträglichkeit, 2018.

[6]	P. Wei, G. Maghlakelidze, A. Patnaik, H. Gossner, D.
Pommerenke, “ TVS Transient Behavior Characterization and
SPICE-Based Behavior Model”, 40th EOS/ESD Symposium, 2018.

[13] 	Notermans, G.; Ritter H.-M.; Holland S.; and Pogany, D.
“Modeling dynamic overshoot in ESD protections”, submitted for
publication at 41th EOS/ESD Symposium, 2019.

[7]	EOS/ESD Association, “Std. Test Method For Electrostatic
Discharge Sensitivity Testing – Transmission Line Pulse (TLP) –Device Level”, Approved January 5, 2017.

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Date of release:
December 2019