LT3964
Dual 36V Synchronous 1.6A
Buck LED Driver with I2C
FEATURESDESCRIPTION

Wide Input Voltage Range: 4V to 36V
nn Two Independent 1.6A/40V Synchronous Bucks
nn I2C Interface for Internal True Color PWM™ Dimming(8192:1), Analog Dimming and Fault Reportingnn 1000:1 External True Color PWM Dimming and10:1 External Analog Dimming
nn PMOS Switch Driver for PWM and Output Disconnect
nn ±3% Constant Current Regulation
nn Adjustable Frequency: 200kHz to 2MHz
nn Frequency Synchronization with Clock Output
nn Programmable OPENLED Protection with Reportingnn Short-Circuit Protection with Reportingnn Programmable Undervoltage Lockout with Hysteresis
nn Internal Compensationnn 9 Unique Device Addresses for I2C
nn Available in 5mm × 6mm 36-Lead QFN Package

The LT®3964 is a dual synchronous step-down DC/DC
converter with I2C interface designed to operate as aconstant-current and constant-voltage source and is idealfor driving LEDs. The fixed frequency and peak current
mode topology result in stable operation over a wide rangeof supply and output voltages. The ground referred voltage FB pin serves as the input for several LED protection
features, and also allows the converter to operate as aconstant-voltage source. The maximum output current is
set by an external resistor, and the output current amplifier has a rail-to-rail common mode range. LT3964 uses
an I2C interface to communicate with a microcontroller
to read LED faults, write PWM and analog dimming registers and set fault masking. The I2C PWM input provides
LED dimming ratios up to 8192:1. The I2C programmable
CTRL register sets the gain of the external CTRL pin, andmaximum current sense threshold, providing additional
analog dimming capability.

nn

APPLICATIONSGeneral Purpose, Industrial, Medical andAutomotive Lighting
nn Constant-Current, Constant-Voltage Source

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and True
Color PWM is a trademark of Analog Devices, Inc. All other trademarks are the property of theirrespective owners. Protected by U.S. Patents, including 7199560, 7321203, 7746300.

nn

TYPICAL APPLICATION
50W Dual Buck 1A LED Driver
10µF
×2

2.2µF
100k

VIN1

BST1

GND

0.22µF

SW1

10µH
1M

EN/UVLO
3.92k PWM1PWM2INTVCC
2.2µF

PWM1
PWM2
CTRL1
CTRL2
INTVCCALERTINTVCC165k

LT3964ISP1
ISN1
PWMTG127.4k
2MHz

2-WIREI2C INTERFACE

0.22µF

GND

SW2

TSET
RT

FB2

10µH

90
85
80
75

100mΩ
1M

2.2µF

43.2k
SYNC/CLKOUT
SCL
SDA

BOTH CHANNELS ARE ON

BST2

2.2µF

499k

1A,
8 LEDs
UP TO
26V

43.2k

Efficiency, VIN
IN = 34V

95

2.2µF

FB1

100k

VIN2

100mΩ

EFFICIENCY (%)

31V TO 36V(ENABLED AT 33V,
SHUTDOWN
AT 31V)100

1A,
8 LEDs
UP TO
26V

70
100 200 300 400 500 600 700 800 900 1000
ILED (mA)
3964 TA01b

ISP2
ISN2
PWMTG2
ADDR1 ADDR2INTVCC3964 TA01a

3964f

For more information www.linear.com/LT3964

1

LT3964
ABSOLUTE MAXIMUM RATINGSPIN CONFIGURATION

BST1

SW1

SW1

NC

VIN1

VIN1

TSET

TOP VIEW

36 35 34 33 32 31 30 29
RT 1

28 ISP1

CTRL1 227 ISN1

CTRL2 326 PWMTG1

EN/UVLO 4

25 SGNDINTVCC 5

24 FB137PGND

ALERT 623 FB2

PWM1 722 SGNDPWM2 821 PWMTG2SDA 920 ISN2
19 ISP2

SCL 10
BST2

SW2

SW2

NC

VIN2

VIN2

ADDR1

11 12 13 14 15 16 17 18
ADDR2

VIN1, VIN2, EN/UVLO..................................................40V
ISP1, ISN1, ISP2, ISN2...............................................40V
PWMTG1, PWMTG2, RT........................................Note 2
SW1, SW2..................................................................40V
BST1, BST2.............................................................44.5V
BST1 to SW1, BST2 to SW2.....................................4.5V
FB1, FB2, CTRL1, CTRL2, ADDR1, ADDR2...................5V
SYNC/CLKOUT, PWM1, PWM2, TSET...........................6V
SDA, SCL, ALERT.........................................................6V
INTVCC...................................................................Note 3
Operating Junction Temperature (Notes 4, 5)
LT3964E/LT3964I............................... –40°C to 125°C
LT3964H............................................. –40°C to 150°C
Storage Temperature Range................... –60°C to 150°C

SYNC/CLKOUT(Note 1)

UHE PACKAGE
36-LEAD (5mm × 6mm) PLASTIC QFNθJA = 43°C/W, θJC = 5°C/W
EXPOSED PAD (PIN 37) IS PGND, MUST BE SOLDERED TO PCBORDER INFORMATION http://www.linear.com/product/LT3964#orderinfo
LEAD FREE FINISH

TAPE AND REELPART MARKINGPACKAGE DESCRIPTIONTEMPERATURE RANGE

LT3964EUHE#PBF

LT3964EUHE#TRPBF

3964

36-Lead (5mm × 6mm) Plastic QFN–40°C to 125°C

LT3964IUHE#PBF

LT3964IUHE#TRPBF

3964

36-Lead (5mm × 6mm) Plastic QFN–40°C to 125°C

LT3964HUHE#PBF

LT3964HUHE#TRPBF

3964

36-Lead (5mm × 6mm) Plastic QFN–40°C to 150°C

Consult LTC Marketing for parts specified with wider operating temperature ranges.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels throughdesignated sales channels with #TRMPBF suffix.

2

3964f

For more information www.linear.com/LT3964

LT3964
ELECTRICAL CHARACTERISTICS

The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN1 = 12V, VEN/UVLO = 5V, CTRL1 = CTRL2 = 2V, PWM1 = PWM2 = 2V
unless otherwise noted.
PARAMETERCONDITIONS

MIN

VIN1, VIN2 Operating Supply Rangel

VIN1 Pin Quiescent Current

Not Switching

VIN1 Pin Shutdown Current

EN/UVLO = 1.15V, PWM1,2 = 0V
EN/UVLO = 0V

VIN2 Pin Quiescent Current

Not Switching

VIN2 Pin Shutdown Current

EN/UVLO = 1.15V, PWM1,2 = 0V
EN/UVLO = 0V

EN/UVLO Threshold Voltage Falling

TYP

4

MAX
36

2.5

1

l

1.158

EN/UVLO Rising Hysteresis

1.18

V
mA

200
1

µA
µA

10

µA

1
1

µA
µA

1.202

V

60

EN/UVLO Input Low Voltage

UNITS

mV
0.4

EN/UVLO Pin Bias Current Low

EN/UVLO = 1.15V

4

EN/UVLO Pin Bias Current HighEN/UVLO = 1.3V

2

100

4

4.1

V
µA
nA

Linear Regulator
INTVCC Regulation Voltage

IINTVCC = –30mA, Non Switching

INTVCC Line Regulation

6V ≤ VIN1 ≤ 40V

0.03

%/V

INTVCC Load Regulation–30mA ≤ IINTVCC ≤ 0mA

0.03

%/mA

l

INTVCC Undervoltage Lockout

3.9

3.1

INTVCC Undervoltage Lockout Hysteresis

3.2

3.3

V

V

50

mV

INTVCC Current Limit

VIN1 = 12V, VINTVCC = 3V

110

mA

Dropout (VIN1 – VINTVCC)

VIN1 = 4V, IINTVCC = –20mA, Not Switching

300

mV

Error Amplifier
Full Scale LED Current Sense Threshold(V(ISP1-ISN1), V(ISP2-ISN2))

ISP1,2 = 24V, CTRL1,2 = 1.5V, ADIM1,2[7:0] = 0xFF
ISP1,2 = 0V, CTRL1,2 = 1.5V, ADIM1,2[7:0] = 0xFF

l
l

97
96

100
100

103
104

mV
mV

1/2 Scale LED Current Sense Threshold(V(ISP1-ISN1), V(ISP2-ISN2))

ISP1,2 = 24V, CTRL1,2 = 0.7V, ADIM1,2[7:0] = 0xFF
ISP1,2 = 0V, CTRL1,2 = 0.7V, ADIM1,2[7:0] = 0xFF

l
l

47
46

50
50

53
54

mV
mV

1/4th Scale LED Current Sense Threshold ISP1,2 = 24V, CTRL1,2 = 0.7V, ADIM1,2[7:0] = 0x7F
(V(ISP1-ISN1), V(ISP2-ISN2)) Modulated by
ISP1,2 = 0V, CTRL1,2 = 0.7V, ADIM1,2[7:0] = 0x7F
I2C Input ADIM1,2[7:0]

l
l

22
21

25
25

28
29

mV
mV

1/10th Scale LED Current Sense
Threshold (V(ISP1-ISN1), V(ISP2-ISN2))

ISP1,2 = 24V, CTRL1,2 = 0.3V, ADIM1,2[7:0] = 0xFF
ISP1,2 = 0V, CTRL1,2 = 0.3V, ADIM1,2[7:0] = 0xFF

l
l

7
6

10
10

13
14

mV
mV

ISP1,2/ISN1,2 Overcurrent Protection
Threshold (V(ISP1-ISN1), V(ISP2-ISN2))

ISP1,2 = 24V

C/10 Current Sense Threshold(V(ISP1-ISN1), V(ISP2-ISN2))

ISP1,2 = 24V
ISP1,2 = 0V

ISP1, ISP2 Input Current Bias Current

930
10
11

15
16

mV
mV

PWM1,2 = 2V (ACTIVE)
PWM1,2 = 0V (STANDBY)

350
5

8

µA
µA

ISN1, ISN2 Input Current Bias Current

PWM1,2 = 2V (ACTIVE)
PWM1,2 = 0V (STANDBY)

3010CTRL1, CTRL2 Input Bias Current

VCTRL1, VCTRL2 = 1V

CTRL1, CTRL2 PWM Shutdown Threshold

6
6

mV

l

CTRL1, CTRL2 PWM Threshold Hysteresis
FB1, FB2 Regulation Voltage (VFB)

µA
nA

20

200

nA

100

150

mV

30
ISP1,2 = 24V

l

1.163
1.17

1.18
1.18

mV
1.197
1.19

VFB + 43mV VFB + 53mV VFB + 63mV

FB1, FB2 Overvoltage Threshold

V
V
V
3964f

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3

LT3964
ELECTRICAL CHARACTERISTICS

The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN1 = 12V, VEN/UVLO = 5V, CTRL1 = CTRL2 = 2V, PWM1 = PWM2 = 2V
unless otherwise noted.
PARAMETERCONDITIONSMIN

FB1, FB2 OPENLED Threshold
FB1, FB2 SHORTLED Threshold

TYP

MAX

UNITS

VFB – 43mV VFB – 53mV VFB – 63mV

V

250

270

mV

200

nA

l

FB1, FB2 Pin Input Bias Current

Current Out of Pin, FB = 1V

20

Feedback Line Regulation

4V ≤ VIN1 ≤ 36V

0.001

%/V

630

mV

TSET Pin Voltage
TSET Pin Bias Current

Current Out of Pin, TSET = 400mV

40

200

nA

Oscillator
RT Pin Voltage
Switching Frequency

0.96
RT = 357k
RT = 60.4k
RT = 27.4k

l
l
l

186
0.93
1.86

SYNC/CLKOUT Pin Resistance to GND

200
1.0
2.0

V
214
1.07
2.14

100

SYNC/CLKOUT Input High Threshold

kΩ

1.5

V

SYNC/CLKOUT Input Low Threshold
30

kHz
MHz
MHz

50

0.4

V

70

%

SYNC/CLKOUT Output Duty Cycle

CONFIG[6] = 1 (Clock Output Enabled)

SYNC/CLKOUT Output Voltage HighCONFIG[6] = 1 (Clock Output Enabled)

4

SYNC/CLKOUT Output Voltage Low

CONFIG[6] = 1 (Clock Output Enabled)

0.1

SYNC/CLKOUT Output Rise TimeCSYNC/CLKOUT = 50pF, CONFIG[6] = 1 (ClockOutput Enabled)

40

ns

SYNC/CLKOUT Output Fall TimeCSYNC/CLKOUT = 50pF, CONFIG[6] = 1 (ClockOutput Enabled)

20

ns

V
0.3

V

Logic
ALERT Output Low

IALERT = 1mA

300

PWM1, PWM2 Input High Voltagel

PWM1, PWM2 Input Low Voltage

l

1.18
1.1

PWM1, PWM2 Resistance to GND

1.3

mV
V

1.15

V

280

kΩ

200

mΩ

Power Switch
Top Switch On Resistance

ISW = 1ATop Switch Current Limit
Bottom Switch On Resistance

l

1.8

2

180

Bottom Switch Current Limit
SW Leakage Current

1.6

ISW = 1A
1.6
VIN = 36V, VSW = 0V, 36V

2

–1.5

A
mΩ

2.4

A

1.5

µA

Minimum Off Time

20

50

70

ns

Minimum ON Time

20

40

65

ns

PWMTG Gate Driver
PWMTG ON Voltage (VISP1-PWMTG1,
VISP2-PWMTG2)

ISP1,2 = 36V

7.5

9.5

V

PWMTG OFF Voltage (VISP1-PWMTG1,
VISP2-PWMTG2)

ISP1,2 = 36V

0

0.3

V

PWMTG Turn-On Time

CLOAD = 500pF, ISP1,2 = 36V

70ns

PWMTG Turn-Off Time

CLOAD = 500pF, ISP1,2 = 36V

40

ns

4

3964f

For more information www.linear.com/LT3964

LT3964
ELECTRICAL CHARACTERISTICS

The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN1 = 12V, VEN/UVLO = 5V, CTRL1 = CTRL2 = 2V, PWM1 = PWM2 = 2V
unless otherwise noted.
PARAMETERCONDITIONS

MIN

TYP

MAX

UNITS

I2C Port (Note 6)
I2C Address

XXXX Bits Are Programmed by ADDR[1:2]

l

VIHA

High Level Input Voltage for Address Pins ADDR1, ADDR2

l

VILA

Low Level Input Voltage for Address Pins ADDR1, ADDR2

l

0.6

V

RINH

Resistance from ADDR1, ADDR2 to INTVCC to Set Chip
Address Bit to 1

l

10

kΩ

RINL

Resistance from ADDR1, ADDR2 to GND to Set Chip
Address Bit to 0

l

10

kΩ

RINF

Resistance from ADDR1, ADDR2 to GND or INTVCC to
Set Chip Address Bit to Float

l

1

MΩ

l

1.5

V

SDA and SCL Input High Voltage

110XXXX[R/W]
INTVCC – 0.8

V

0.4

V

SDA and SCL Input High Current

SDA, SCL = 3.3V

50

nA

SDA and SCL Input Low Current

Current Out of Pin, SDA, SCL = 0V

50nA

SDA Output Low Voltage

ISDA = 3mA

SDA and SCL Input Low VoltagelClock Operating Frequency

0.4

V

400

kHz

Bus Free Time Between Stop and Start
Condition (tBUF)

1.3

µs

Hold Time After Repeated Start
Condition (tHD,SDA)

0.6

µs

Repeated Start Condition Set-Up
Time (tSU,STA)

0.6

µs

Stop Condition Set-Up Time (tSU,STO)

0.6

µs

Data Hold Time Output (tHD,DAT(O))

0

Data Hold Time Input (tHD,DAT(I))

0nsData Set-Up Time (tSU,DAT)

250

ns

900

ns

SCL Clock Low Period (tLOW)

1.3

µs

SCL Clock High Period (tHIGH)

0.6

µs

Data Fall TimeCB = Capacitance of One Bus Line (pF)

20 + 0.1CB

300

ns

Data Rise TimeCB = Capacitance of One Bus Line (pF)

20 + 0.1CB

300

ns

50

ns

Input Spike Suppress Pulse Width (tSP)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Do not apply a positive or negative voltage source to PWMTG pin,otherwise permanent damage may occur.
Note 3: Do not apply a positive or negative voltage source to INTVCC pin,otherwise permanent damage may occur. IINTVCC = 5mA is the maximum
external load that can be applied. The internal load will be higher due to thepower consumption of the IC.
Note 4: The LT3964E is guaranteed to meet specified performancefrom 0°C to 125°C. Specifications over the –40°C to 125°C operating
temperature range are assured by design, characterization andcorrelation with statistical process controls. The LT3964I is guaranteed
to meet performance specifications over the –40°C to 125°C operating
temperature range. The LT3964H is guaranteed over the full –40°C to
150°C operating junction temperature range. High junction temperatures
degrade operating lifetimes. Operating lifetime is derated at junction
temperatures greater than 125°C.
Note 5: The LT3964 includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed the maximum operating junction temperaturewhen overtemperature is active. Continuous operating above the specified
maximum operating junction temperature may impair device reliability.
Note 6: All I2C serial port timing information is shown in Figure 15.

3964f

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5

LT3964
TYPICAL PERFORMANCE CHARACTERISTICS
EN/UVLO Thresholds vs
Temperature
4.4

1.25

1.22
1.21
1.20
1.19

3.8
3.6
3.4

FALLING THRESHOLD

1.18

VIN SHUTDOWN CURRENT (µA)

4.0

RISING THRESHOLD
IEN/UVLO (µA)

VEN/UVLO (V)

1.23

3.2

1.17
1.16
–55

–25

5
35
65
95
TEMPERATURE (°C)

125

3.0
–55

155

–25

5
35
65
95
TEMPERATURE (°C)

125

2.6
2.5
2.4
2.3

4.02
4.00
3.98

5
35
65
95
TEMPERATURE (°C)

125

155

INTVCC = 0V

IINTVCC (mA)

3.14

SWITCHING FREQUENCY (MHz)

3.26

FALLING THRESHOLD

0

5 10 15 20 25 30 35 40 45 50 55 60
LOAD CURRENT (mA)
3964 G06

10

50

3.16

3.95

INTVCCINTV
Current Limit
Limit vsvs VVIN
CC Current
IN

3.28

3.18

4.00

3964 G05

55

3.20

4.05

3.80
–25

3964 G4INTV
INTVCCUVLO vsvs Temperature
Temperature
CC UVLO

155

3.85

3.90
–55

155

125

3.90

3.92

RISING THRESHOLD

5
35
65
95
TEMPERATURE (°C)

VIN = 6V
VIN = 24V
VIN = 36V

4.10

3.94

125

–25

INTV
INTVCCvs Current
LOAD (3•VIN)
CC vs

4.15

3.96

3.22

140

4.20

INTVCC (V)INTVCC (V)

2.7

3.24

160

3964 G3

VIN = 6V
VIN = 24V
VIN = 36V

4.06

5
35
65
95
TEMPERATURE (°C)

180

100
–55

4.04

–25

EN/UVLO = 1.1V

200

155

CC

4.08

2.8

2.2
–55

220

INTVCC vs Temperature (3•VIN)
4.10

VIN = 6V
VIN = 24V
VIN = 36V

2.9

VIN = 6V
VIN = 24V
VIN = 36V

3964 G2

VIN Quiescent Current vs
Temperature
3.0

240

120

3964 G1

VIN QUIESCENT CURRENT (mA)

260

EN/UVLO = 1.1V

4.2

1.24

INTVCC (V)VIN Shutdown Current vs
Temperature

EN/UVLO Current vs Temperature

1.26

3.30

TA = 25°C, unless otherwise noted.

45
40
35
30

Switching Frequency vs RTT

1

3.12
3.10
–55

–25

5
35
65
95
TEMPERATURE (°C)

125

155
3964 G07

6

25

0

6

12

18
VIN (V)

24

30

363964 G08

0.1

10

100
RT (kΩ)

1000
3964 G09

3964f

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LT3964
TYPICAL PERFORMANCE CHARACTERISTICS
Frequency vs Temperature (1MHz)

Frequency vs Temperature(2MHz)
Temperature(2MHz)
2100

RT = 60.4k

Frequency vs Temperature (200kHz)
210

RT = 27.4k

2050

205

1100

2000

200

1050
1000
950

FREQUENCY (kHz)1150

FREQUENCY (kHz)

1950
1900
1850

850

1750

175

1.22

–25

5
35
65
95
TEMPERATURE (°C)

125

1700
–55

155

–25

VFB vs Temperature

VFB (V)

1.16
1.14
1.12

5
35
65
95
TEMPERATURE (°C)

125

155

1.12

1.21

1.11

1.20

FALLING THRESHOLD

1.19

1.17

1.07

1.16

1.06
–25

5
35
65
95
TEMPERATURE (°C)

125

VISP–ISN (mV)

265
260
FALLING THRESHOLD

250
245
–25

5
35
65
95
TEMPERATURE (°C)

125

155

3964 G16

30
28
26
24
22
20
18
16
14
12
10
8
6
4
–55

–25

5
35
65
95
TEMPERATURE (°C)

125

155

3964 G15

110

VISP–ISN vs CTRL
CTRL

100
90

RISING THRESHOLD

80
VISP–ISN (mV)

285

240
–55

1.05
–55

155

C/10 Threshold vs Temperature

270

FALLING THRESHOLD

3964 G14

290

255

1.09
1.08

1.15
–55

RISING THRESHOLD

1.10

1.18

295

155

1.14

RISING THRESHOLD

1.13

300

125

OPENLED Threshold vs
Temperature
OPENLED Threshold vs Temperature

1.22

SHORTLED Threshold vs

275

5
35
65
95
TEMPERATURE (°C)

3964 G12

1.23

Temperature
Temperature

RISING THRESHOLD

–25

1.15

3964 G13

280

170
–55

155

1.25

1.18

–25

125

OVFB Threshold vs Temperature

1.20

1.10
–55

5
35
65
95
TEMPERATURE (°C)

3964 G11

1.24

VFB (V)185
1803964 G10

VFB (mV)

190

1800

800
–55

RT = 357k

195

900

VFB (V)FREQUENCY (kHz)1200

TA = 25°C, unless otherwise noted.

70
60
50
40
30

FALLING THRESHOLD

20
10

–25

5
35
65
95
TEMPERATURE (°C)

125

155

3964 G1700

0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2.0
VCTRL (V)3964 G18

3964f

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7

LT3964
TYPICAL PERFORMANCE CHARACTERISTICS
104.0

VCTRL = 2V

90

VISP–ISN (mV)

VISP–ISN (mV)

70
60
50
40

101.0

51.0

100.0

10
64

99.0

97.0

47.0
–25

5
35
65
95
TEMPERATURE (°C)

46.0
–55

155

22.0

ISP = 24V
ISN = 0V
VCTRL = 2V

49.0

12.0

21.0

11.0

20.5

10.5

20.0
19.5

9.5

19.0

9.0

47.0

18.5

8.5

–25

5
35
65
95
TEMPERATURE (°C)

125

18.0
–55

155

–25

5
35
65
95
TEMPERATURE (°C)

3964 G22

125

VISP–ISN vs VFB
104

VCTRL = 2V

110

VCTRL = 2V

103

100

VISP–ISN (mV)

VISP–ISN (mV)

25

0
1.10

100
99
98

1.12

1.14
1.16
VFB (V)

1.18

1.20
3964 G25

155

VISP–ISN
ISP–ISN vs VTSETTSET at 90°C
VCTRL = 2V

70
60
50
40
30

96

20

95

10

94

125

80

101

50

5
35
65
95
TEMPERATURE (°C)

90

102

75

–25

3964 G24

VISP–ISN
ISP–ISN vs VISP
ISP

97

8

8.0
–55

155

3964 G23

100
VISP–ISN (mmV)

125

155

10.0

48.0

46.0
–55

125

ISP = 24V
ISN = 0V

11.5

VISP–ISN (mV)

50.0

5
35
65
95
TEMPERATURE (°C)

VISP–ISN 1/10 Scale (VCTRL =0.3V) vs Temperature

ISP=24V
ISN=0V

21.5

51.0

–25

3964 G21

VISP–ISN 1/5 Scale (VCTRL = 0.4V)vsvs Temperature
Temperature

VISP–ISN (mV)

VISP–ISN (mV)

52.0

125

3964 G20

VISP–ISN 1/2 Scale (ADIM = 0x7f)
vs Temperature
53.0

49.0
48.0

3964 G19

54.0

50.0

98.0

96.0
–55

96 128 160 192 224 256
ADIM CODE

ISP = 24V
ISN = 0V

53.0
52.0

20

32

54.0

102.0

30

0

VISP–ISN 1/2 Scale (VCTRL = 0.7V)vsvs Temperature
Temperature

ISP = 24V
ISN = 0V

103.0

80

0

VISP–ISN Full Scale vsTemperature
VISP–ISN Full Scale vs Temperature

VISP–ISN (mV)

100

VISP–ISN
ISP–ISN vs ADIM

TA = 25°C, unless otherwise noted.

0

4

8

12 16 20 24 28 32 36 40
VISP (V)3964 G26

0
660

680

700

720 740VTSET (mV)

760

780

800

3964 G27

3964f

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LT3964
TYPICAL PERFORMANCE CHARACTERISTICS
Minimum Off-Time vs

Minimum On-Time vsTemperature

56

56

54

55

52
50
48
46
44

53
52
51
50

40

49
–25

5
35
65
95
TEMPERATURE (°C)

125

1.95

54

42
38
–55

–25

5
35
65
95
TEMPERATURE (°C)

125

Top Switch Current Limit vsDuty Cycle
POWER SWITCH ON RESISTANCE (mΩ)

TOP SWITCH CURRENT LIMIT (A)400

FREQ = 1MHz

2.0
1.9
1.8
1.7
1.6
1.5
0

155

1.75
1.70

1.60
–55

155

250
VPWM
2V/DIV

200
150
100

100ns/DIV

50
0
–55

–25

5
35
65
95
TEMPERATURE (°C)

1253964 G33

1553964 G32

PWMTG Falling Edge

Transient Response at VIN = 34V
One LED On to Zero LED On

IL1200mA/DIV

IL1200mA/DIVI

ILED1200mA/DIV

LED1200mA/DIV

3964 G34

1253964 G30

Transient Response at VIN = 34V
Zero LED On to One LED On

VPWM
2V/DIV

5
35
65
95
TEMPERATURE (°C)

VPWMTG
5V/DIV300

3964 G31

VPWMTG
5V/DIV–25

PWMTG Rising Edge

TOP SWITCH
BOTTOM SWITCH

350

10 20 30 40 50 60 70 80 90 100
DUTY CYCLE (%)

100ns/DIV

1.80

Power Switch On-Resistance vs
Temperaturevs Temperature

2.1

1.4

1.85

3964 G29

3964 G28

2.2

1.90

1.65

48
–55

155

2.00

ILED = 1A

57

MIN OFF-TIME (V)MIN ON-TIME (V)58

ILED = 1A

58

Top Switch Current Limit vsTemperature

Temperature
Minimum
OFF Time vs Temperature

TOP SW CURRENT LIMIT (A)60

TA = 25°C, unless otherwise noted.

5µs/DIV
SEE MATRIX LED DRIVER ON PAGE 31

3964 G35

5µs/DIV

3964 G36

SEE MATRIX LED DRIVER ON PAGE 313964f

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9

LT3964
PIN FUNCTIONS
RT (Pin 1): Switching Frequency Adjustment Pin. Set themaster clock frequency using a resistor to GND (for resistor values, see Typical Performance curve or Table 3). Do
not leave the RT pin open.
CTRL1, CTRL2 (Pins 2, 3): Current Sense Threshold
Adjustment Pins. The V(ISP-ISN) threshold is regulated by
the internal 1.2V reference voltage, CTRL and ADIM[7:0]of the respective channel as follows:
V(ISP-ISN) = 0V, when VCTRL < 0.2V
V(ISP-ISN) = [(VCTRL –0.2V)/10]•(ADIM[7:0]+1)/256,
when 0.2V ≤ VCTRL ≤ 1.1V

ALERT (Pin 6): Chip Alert Status Report Pin. An opencollector pull-down on ALERT asserts when any of thefollowing conditions happen:
1. FB Overvoltage (VFB > 1.233V);
2. OPENLED (VFB > 1.127V and V(ISP-ISN) <10mV);
3. SHORTLED (VFB < 0.25V);
4. LED Overcurrent (V(ISP-ISN) > 930mV);
5. INTVCC undervoltage; or
6. Thermal shutdown.

V(ISP-ISN) = 100mV•(ADIM[7:0]+1)/256, when VCTRL > 1.3V

ALERT flag stays low until all alerts have been removed
and unlatched.

For 1.1V < VCTRL < 1.3V, the dependence of the current
sense threshold upon VCTRL transitions from a linear
function to a constant value, reaching 98% of full scalevalue, 100mV•(ADIM[7:0]+1)/256, by VCTRL = 1.2V. See
Table 1 for detailed information. Do not leave this pin open.

PWM1, PWM2 (Pins 7, 8): PWM Input Signal Pin. A
low signal turns off switching, reduces quiescent supply
current, and drives PWMTG to the ISP level. PWM has
an internal 280k pull-down resistor. If not used, connect
this pin to INTVCC.

EN/UVLO (Pin 4): Enable and Undervoltage Lockout Pin.
An accurate 1.18V falling threshold with externally programmable hysteresis detects when power is OK to enableswitching. Rising hysteresis is generated by the external
resistor divider and an accurate internal 4µA pull-downcurrent. Tie to 0.4V or less to disable the device.
INTVCC (Pin 5): Internal Low-Dropout Regulator Output.
INTVCC is regulated to 4V, and must be bypassed with an
external capacitor of at least 2.2μF. INTVCC is the power
supply for the internal DMOS gate driver and control
circuitry. Users may apply <5mA loads to INTVCC. Overloading INTVCC can cause unintentional device shutdown
from INTVCC current limiting or overheating due to power
dissipation.

10

SDA (Pin 9): Serial Data Line for I2C Port. Open-drain
output during read back.
SCL (Pin 10): Serial Clock Line for I2C Port.
ADDR2 (Pin 11): Address Select Pin. This pin is configured
as a three-state (LOW, HIGH, FLOAT) address control bit forthe device I2C address. See Table 14 for address selection.
ADDR1 (Pin 12): Address Select Pin. This pin is configured
as a three-state (LOW, HIGH, FLOAT) address control bit forthe device I2C address. See Table 14 for address selection.
VIN2 (Pins 13, 14): Input Supply for Channel 2. May be
driven by an independent supply, or connected to VIN1.
This signal must be locally bypassed. Be sure to place thepositive terminal of the input capacitor as close as possible to the VIN2 pin, and the negative terminal as close
as possible to the PGND pin (Pin 37).

3964f

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LT3964
PIN FUNCTIONS
SW1, SW2 (Pins 16, 17, 30, 31): SW Pins. The SW pins
are the outputs of the internal power switches of eachchannel. Tie each channel SW pins together and connect
them to the appropriate inductor and boost capacitor.
These nodes should be kept small on the PCB for good
performance.
BST1, BST2 (Pins 18, 29): Boost Pins. These pins are used
to provide a drive voltage, higher than the input voltage, tothe topside power switch of each channel. Place a 0.1µF
or larger boost capacitors as close as possible to the IC.
ISP1, ISP2 (Pins 19, 28): Connection Points for the Positive Terminals of the Current Feedback Resistors (RLED1,2).
Also serves as positive rails for PWMTG drivers.
ISN1, ISN2 (Pins 20, 27): Connection Points for the Negative Terminals of the Current Feedback Resistors (RLED1,2).
PWMTG1, PWMTG2 (Pins 21, 26): Top Gate Driver Outputs. An inverted and level-shifted version of the PWM
input signals. Used to drive the gate of an external PMOS
transistor between VISP and VISP – 7.5V to provide load-side
on/off control, PWM dimming and fault-mode disconnect.
Leave PWMTG unconnected if not used.
FB1, FB2 (Pins 23, 24): Voltage Loop Feedback Pins. The
FB pin is intended for constant-voltage regulation or for LED
protection/OPENLED detection. The LT3964 regulates the
FB pins to 1.18V(NOMINAL). If the FB input is regulating
the loop and V(ISP-ISN) is less than 10mV (Typical), thecorresponding OPENLED bit in the chip status register
is set and the ALERT pull-down is asserted. This action
may signal an OPENLED fault for that channel. If FB isdriven above 1.233V, the power switches are turned off
for that channel, the corresponding OVFB bit in the chip
status register is set, ALERT pull-down is asserted, and
the PWMTG pin for that channel is driven high to protect
the LEDs from an overcurrent event. If FB is driven below
0.25V, the power switches are turned off for that channel,
the corresponding SHORTLED bit in the chip status register
is set, ALERT pull-down is asserted, and the PWMTG pin
for that channel is driven high to isolate the LED stringfrom the power path. Do not tie these pins to GND.

VIN1 (Pins 33, 34): Input Supply. The VIN1 pins supply
current to the LT3964 internal circuitry and to the internal
topside power switch of Channel 1. This pin must be locally bypassed. Be sure to place the positive terminal of
the input capacitor as close as possible to the VIN1 pins,
and the negative terminal as close as possible to the PGND
pin (Pin 37).
TSET (Pin 35): Junction Temperature Adjustment Pin.
Programs LT3964 junction temperature breakpoint,beyond which LED currents will begin to decrease. Aninternal VPTAT threshold (see Block Diagram) increases
with junction temperature. When VPTAT exceeds TSET pin
voltage, LED currents are decreased. If the function is not
required, connect TSET pin to INTVCC pin.
SYNC/CLKOUT (Pin 36): The SYNC/CLKOUT pin can beused to synchronize the internal oscillator to an external
logic level signal. The RT resistor should be chosen to
program an internal switching frequency 10% slower
than the SYNC pulse frequency. Use a 50% duty cycle
waveform to drive this pin. When CONFIG[6] bit in thechip configuration register is set, a buffered version of
the clock signal is driven out of the SYNC/CLKOUT pin.
Note that the SYNC/CLKOUT pin is only meant to drive
capacitive loads up to 50pF. If not used, tie this pin to
GND with a 20k resistor.
SGND (Pins 22, 25): Chip Ground Pin.
PGND (Pin 37): Power Switch Ground. These pins are
the return path of the internal bottom-side power switch.
Place the negative terminal of the input capacitor as close
to the PGND pins as possible.
NC (Pins 15, 32): No Connect Pin.

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11

LT3964BLOCK DIAGRAM
REN1EN/UVLO

CIN1

REN2

35

CVCC

5

VIN1
33, 34

1

INTVCC

RT36

7

SYNC/CLKOUT

UVLO
TLIM

4V REG

1.18V REF

RT

PWM1

8

PWM2

OC1, 2SHORTLED1, 2
OPENLED1, 2

SHDN
4µA

LOGIC

OVFB1, 2

200kHz TO 2MHzOSCILLATOR

CH1, 2-ON
UVLO

RAMP
GENERATOR

TLIM

A1
BST1
28

SGND
22, 25S

TGOFFB1

A2
x1
ISP1
28

INTVCC

VLED1

–+

R1

20mV

ISN1
27
VTEMP
CTRL1 1.2V
2

+
+
+

A3

IREF

IOUT

FB1

8-BIT DAC

1.127VOPENLED1
A7
I2C INTERFACE

VLED1

10xR1

A8

0.25V

SHORTLED1FB1TGOFFB1

FB1
24

A6

10mV
ADIM1[7:0]

26

OC1

0.93V

A4

VISP1

A5

VLED1

VC

–

PWMTG1

ADIM1[7:0]

PGND
37

RFB1

R

ADIM2[7:0]Q

CH2-ONSYNCHRONOUS
CONTROLLER

BOTTOM
SWITCH

L1

M1

5

TOP
SWITCHSW1
30, 31INTVCC

RLED1

ALERT

INTVCC

CH1-ONCBST1TGOFFB1

TGOFFB2

INTVCC

RFB2

A9

FB1

VISP1 – 7.5V

2.5V
1.18V

OVFB1

1.233VA10
R2

REPLICATED FOR CHANNEL 2

A11

VTEMP

VPTAT

R3
TSET
35
INTVCC

12

RTSET2SDA
9SCL ADDR2 ADDR1
1011
12 3964 BD

RTSET13964f

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LT3964
OPERATION
The LT3964 is a dual constant-frequency, current mode
step-down DC/DC converter with internal synchronous
power switches. The operation of the LT3964 is best
understood by referring to the Block Diagram of the IC.
In normal operation, with the PWM pin is low or CH1,2_ON
signal is low, TGOFFB is disabled. The power switches areturned off, the PWMTG pin is pulled high to ISP to turnoff the PMOS disconnect switch, and the ISP and ISN pin
bias currents are reduced to several µA. When the PWM
pin and CH1,2_ON signal transitions high, the PWMTG
pin transitions low after a short delay. At the same time,
the bottom switch is turned on for a short period of time
to refresh the boost capacitor, followed by the top powerswitch turning on. A voltage input proportional to the top
switch current is added to a stabilizing slope compensation
ramp and the resulting top switch current sense signal is
fed into the negative terminal of the PWM comparator. The
current in the external inductor increases steadily during thetime the top switch is on. When the switch current sense
voltage exceeds the output of the error amplifier, labeled
VC, the latch is reset and the switch is turned off. During
the top switch off phase, the synchronous bottom switch ison until the next clock cycle begins or inductor current falls
to zero. If overload conditions result in more than 2A (Typ)flowing through the bottom switch, the next clock cycle will
be delayed until switch current returns to a safe level. At thecompletion of each oscillator cycle, internal signals such as
slope compensation return to their starting points and a newcycle begins with the set pulse from the oscillator. Throughthis repetitive action, the PWM control algorithm establishesa switch duty cycle to regulate a current or voltage in theload. The VC signal is integrated over many switching cycles
and is an amplified version of the difference between the
LED current sense voltage, measured between ISP and ISN,
and the target difference voltage set by the CTRL pin and
I2C input ADIM[7:0]. In this manner, the error amplifier sets
the correct top switch peak current level to keep the LED
current in regulation. If the error amplifier output increases,
more current is demanded in the switch; if it decreases, lesscurrent is demanded. The analog input at CTRL pin together
with the digital input ADIM[7:0] can be used to provide a
combination of temperature foldback protection via CTRL
and analog dimming via I2C, or a combination of analog
dimming via CTRL pin and LED binning via I2C.

In voltage feedback mode, the operation is similar to that
described above, except the voltage at the VC node is set by the
amplified difference of the internal reference of 1.18V (typical) and the FB pin. If FB is lower than the reference voltage,
the top switch current increases; if FB is higher than thereference voltage, the top switch demand current decreases.
The LED current sense feedback interacts with the voltage
feedback so that FB does not exceed the internal reference
and the voltage between ISP and ISN does not exceed thethreshold set by the product of the analog input at CTRL pin
and the digital input ADIM[7:0] through I2C. For accurate
current or voltage regulation, it is necessary to ensure that
under normal operating conditions, the appropriate loop is
dominant. To deactivate the voltage loop entirely, FB can be
set between 0.3V and 1.08V through a resistor network to
INTVCC pin. To deactivate the LED current loop entirely, the
ISP and ISN should be tied together and CTRL tied to INTVCC.
Two LED specific functions featured on the LT3964 arecontrolled by the voltage feedback FB pin. First, when the FB
pin exceeds a voltage 53mV lower (–4%) than the FB regulation voltage and V(ISP-ISN) is less than 10mV (Typical), theOPENLED bit, STATUS[1] or STATUS[5], is set in the channel status register. This function provides a status indicatorthat the load may be disconnected and the constant-voltage
feedback loop is taking control of the switching regulator.
When the FB pin drops below 0.25V (typical) after startup, the SHORTLED bit, STATUS[2] or STATUS[6], is set bycomparator A8. A blanking period occurs during start-up for
the SHORTLED protection feature from the EN/UVLO toggle.
LT3964 features a PMOS disconnect switch driver. The
PMOS disconnect switch can be used to improve the PWM
dimming ratio, and operate as fault protection as well. Oncea fault condition is detected, the PWMTG pin is pulled highto turnoff the PMOS switch. The action isolates the LED
array from the power path, preventing excessive current
from damaging the LEDs.
The I2C interface is used to communicate between
LT3964 and a microprocessor. LT3964 receives digital
PWM dimming and analog dimming commands from a
microprocessor and sends back the chip status, i.e., FB
overvoltage (FB > 1.233V), output short (FB < 0.25V) after
start-up, LED overcurrent V(ISP-ISN) > 930mV), OPENLED(FB > 1.127V and (V(ISP-ISN) < 10mV).
3964f

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13

LT3964APPLICATIONS INFORMATION
The following is a guide to selecting the external components and configuring the LT3964 according to therequirements of an application.
OPERATION MODE
The LT3964 has two operation modes: I2C mode (at least
one address pin is NOT grounded) and non-I2C mode (bothI2C address pins are grounded, i.e. ADDR1 = ADDR2 = GND).
In I2C mode, the LT3964 is initially set to be idle after

power on reset. It will stay in idle until an updated PWM
command is received via I2C interface.
In non-I2C mode, the LT3964 starts up right after thePWM pin input signal rising edge after power-on reset.
Non-I2C mode allows customers to access all the registers
except PWM dimming registers using the chip address(1100000 R/W).

Table 1. V(ISP-ISN) Threshold vs CTRL in Terms of ADIM[7:0]
VCTRL(V)

V(ISP-ISN) (mV)

1.1

90 • (ADIM[7:0]+1)/256

1.15

94.4 • (ADIM[7:0]+1)/256

1.2

97.8 • (ADIM[7:0]+1)/256

1.25

99.4 • (ADIM[7:0]+1)/256

1.3

100 • (ADIM[7:0]+1)/256

The CTRL pin should not be left open (tie to INTVCC if
not used). CTRL can also be used in conjunction with athermistor to provide overtemperature protection for the
LED load as shown in Figure 1, or with a resistor divider
to VIN to reduce output power and switching current when
VIN is low.
INTVCCILED =

100mV ADIM[7:0]+1•,VCTRL > 1.3V
RLED
256

ILED =VCTRL – 0.2V ADIM[7:0]+1•,0.2V < VCTRL < 1.1V
10 •RLED
256

ILED = 0,VCTRL < 200mV

When the CTRL pin voltage is between 1.1V and 1.3V,
the LED current varies with CTRL, but departs from theprevious equation by an increasing amount as the CTRL
voltage increases. Ultimately, above 1.3V, the LED current
no longer varies with CTRL. The typical V(ISP-ISN) thresholdvs CTRL in terms of ADIM[7:0] is listed in Table 1.

14

RCTRL2RNTC

LT3964RCTRL1CTRL

PROGRAMMING LED CURRENT WITH THE CTRL PIN
The LED current is programmed by placing an appropriate
value current sense resistor RLED between the ISP and ISN
pins. For best fault protection provided by the high side
PMOS disconnect switch, sensing of the current should
be done at the top of the LED string. The LED current isregulated by the internal 1.2V reference voltage, analog
input at CTRL and digital input ADIM[7:0] of analog dimming register:LT3964RCTRL1INTVCCCTRLRCTRL23964 F01

RNTC

Figure 1. Setting CTRL with NTC Resistors

The digital input ADIM1[7:0] (for Channel 1) of analog
dimming register shown in Table 2 can be accessed via
I2C, which provides additional analog dimming. The default
power-on value is 255.
The presence of a time varying differential voltage signal(ripple) across ISP and ISN at the switching frequency
is expected. The amplitude of this signal is increased byhigh LED load current, low switching frequency and/or asmaller value output filter capacitor. For best accuracy,
the amplitude of this ripple should be less than ±5mV.
SETTING SWITCHING FREQUENCY WITH THE RT PIN
The RT frequency adjust pin allows the user to program
the switching frequency from 200kHz to 2MHz to optimize
efficiency/performance or external component size. Higher
frequency operation yields smaller component size but increases switching losses, and may not allow sufficiently high3964f

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LT3964APPLICATIONS INFORMATIONor low duty cycle operation. Lower frequency operation gives
better performance at the cost of larger external component
size. For an appropriate RT resistor value see Table 3. An
external resistor from the RT pin to GND is required—do notleave this pin open.
Table 2. Channel 1 Analog Dimming Register
ANALOG DIMMINGREGISTER[BIT]VALUE

SETTING

ADIM1[0]01*0+1/256 of the Current Set by CTRL

ADIM1[1]01*0+1/128 of the Current Set by CTRL

ADIM1[2]01*0+1/64 of the Current Set by CTRL

ADIM1[3]01*0+1/32 of the Current Set by CTRL

ADIM1[4]01*0+1/16 of the Current Set by CTRL

ADIM1[5]01*0+1/8 of the Current Set by CTRL

ADIM1[6]01*0+1/4 of the Current Set by CTRL

ADIM1[7]01*0+1/2 of the Current Set by CTRL

*Denotes Default Power-On Value.

Table 3. RT Resistance Range
SWITCHING FREQUENCY

RT (kΩ)

2MHz

27.4

1.8MHz32.4

1.6MHz36.5

1.4MHz42.2

1.2MHz

49.9

1MHz

60.4

800kHz78.7

600kHz107

400kHz169500kHz133

300kHz232200kHz357

FREQUENCY SYNCHRONIZING AND CLOCK
The LT3964 switching frequency can be synchronized toan external clock using the SYNC/CLKOUT pin. For proper

operation, the RT resistor should be chosen for a switchingfrequency 10% lower than the external clock frequency.
Observation of the following guidelines about the SYNC
waveform will ensure proper operation of this feature.
Driving SYNC/CLKOUT with a 50% duty cycle waveform
is always a good choice, otherwise, maintain the duty
cycle between 20% and 60%. If the SYNC/CLKOUT pin is
not used, it should be connected to GND through a 20k
resistor or left floating (an internal 100k connects their
pin to GND).
CLOCK SYNCHRONIZATION OF ADDITIONALREGULATORSThe SYNC/CLKOUT pin of the LT3964 can be used to synchronize one or more other compatible switching regulator
ICs. The frequency of the master LT3964 is set by theexternal RT resistor, and the RT pin of all slave ICs musthave a resistor tied to ground. It is preferable for all slave
ICs to have the same internal free-running frequency. This
CLKOUT function is disabled initially after power on reset.
To enable this function, CONFIG[6] in the master LT3964’s
chip configuration register (see Table 11), has to be set tologic high via I2C interface. Note that the SYNC/CLKOUT
pin is only meant to drive capacitive loads up to 50pF.
UNDERSTANDING THE CURRENT LIMITThe LT3964 has a peak current limit of 1.8A (typical). The
inductor current, however, may exceed 1.8A when thefrequency is high and the output voltage is low as in ashort circuit. This is because there is a minimum on-time
for which the SW pin will be driven high each switching
period. The inductor current increases during this time, andif the frequency is high and the output voltage low, there
may not be enough off-time remaining in each switching
period for the inductor current to decrease back to the levelat which it started. In this case, the net inductor current
would increase with each switching period regardlessof the state of the CTRL pin. To prevent an unboundedinductor current that would damage the LT3964, theon-time is prohibited until the current decreases to lessthan the valley current limit (2A typical). The peak current
may increase to 1.8A (typical), but the off-time and theswitching period are extended until the inductor current
3964f

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15

LT3964APPLICATIONS INFORMATION
reaches equilibrium.
The above scenario generally ensues only when the output
voltage is shorted to ground. When instead the LED string isshorted to ground, the voltage across the external PWMTG
MOSFET (described later) is often high enough that therequired on-time is greater than the minimum on-time.
This means the inductor current can remain in regulationeven at the highest switching frequency.
SELECTING AN INDUCTOR
The LT3964 is designed to minimize solution size by
allowing the inductor to be chosen based on the output
load requirements of the application. The inductor mustbe rated for the current limit regardless of the intended
application.
In applications with 1μF or larger output filter cap andfixed output load, a good first choice of inductor can be
as follows:

VOUT
L=
1.2A • fSW

To avoid overheating and poor efficiency, an inductor
must be chosen with an RMS current rating that isgreater than the maximum expected output load of theapplication. In addition, the saturation current (typicallylabeled ISAT) rating of the inductor must be higher thanthe load current plus 1/2 of the inductor ripple current:
1∆IL2
where ILOAD(MAX) is the maximum output load for a given
application, and ∆IL is the inductor ripple current as calculated in the following equation:
IPEAK = ILOAD(MAX) +VOUT 
VOUT 
 1–
L • fSW 
VIN(MAX) 

In applications that have dynamic and time-varying output loads, there is usually no output capacitor. The input

16

The optimum inductor for a given application may differ
from the one indicated by this design guide. A larger value
inductor provides a higher maximum load current andreduces the output voltage ripple. For applications requiring high PWM dimming ratio, the value of the inductor
may be lower. But be aware that the low inductance may
result in discontinuous mode operation. The manufacturers
featured in Table 4 are recommended sources of inductors.
Table 4. Inductor Manufacturers
MANUFACTURERWEBSITE

Würth Elektronik

www.we-online.com

Coilcraftwww.coilcraft.com

Vishay Inter Technology

www.vishay.com

SELECTING AN OUTPUT CAPACITOR

In the above equation, VOUT is the output voltage and fSW
is the switching frequency.

∆IL =voltage of these applications is fixed and generated froma boost converter. The inductor ripples must be limited
to meet EMI requirement. For a given inductor ripple ∆IL,
the inductor should be selected as follows:
VINL=
4 • ∆IL • fSW

In applications with fixed LED load, the output capacitor
has two essential functions. It is first responsible for filtering the inductor current ripple so that the LED current will
have relatively little ripple. It also stabilizes the LT3964’s
current loop, since the LED string impedance and output
capacitor form the 2nd dominating pole in the loop, usually
between 10kHz and 40kHz. Ceramic capacitors have very
low equivalent series resistance (ESR) and provide thebest ripple performance. The sizing of the output capacitor
depends on the chosen switching frequency, the inductor value and equivalent LED string impedance. Use of a
X7R or X5R type ceramic capacitor is recommended. For
good starting values, see the Typical Applications section.
Consult factory applications for more detailed information.
When choosing a capacitor, special attention should begiven to calculate the effective capacitance under the relevant operating conditions of voltage bias and temperature.
A physically larger capacitor or one with a higher voltage
rating may be required. Sources of quality ceramic capacitors are listed in Table 5.
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LT3964APPLICATIONS INFORMATION
Table 5. Capacitor Manufacturers

MANUFACTURER
MurataTDK
Kemet
Taiyo Yuden
AVXWEBSITE
www.murata.com
www.tdk.com
www.kemet.com
www.t-yuden.com
www.avx.com

STABILIZING THE REGULATION LOOP
The LT3964 uses a transconductance error amplifier withinternal compensation. Thus, the current loop has the fixed
dominant pole and the zero internally. To compensate theloop, a 2nd pole has to be formed outside of LT3964. For
applications with an output capacitor, the output capacitor and the equivalent impedance form the 2nd pole. For
applications with dynamic and time-varying output loads
that have no output capacitor, the 2nd pole has to beformed between 10kHz and 40kHz with the LED sensing
resistor RLED as shown in Figure 2. The time constant of
the 2nd pole is CFILT(RLED + RFILT). ISN pin has typical
30μA loading current. To keep ISP-ISN threshold DC offset
less than 0.6mV (typical), RFILT has to be less than 20Ω.
L

RLED
CFILT

ISP

RFILT(OPT)ISN

LT3964high impedance, or there is significant inductance due tolong wires or cables, additional bulk capacitance may benecessary. This can be provided with a low performanceelectrolytic capacitor.
Step-down regulators draw current from the input supply inpulses with very fast rise and fall times. The input capacitor is required to reduce the resulting voltage ripple at theLT3964 and to force this very high frequency switchingcurrent into a tight local loop, minimizing EMI. A 4.7μF
capacitor is capable of this task, but only if it is placed
close to the LT3964 (see the PCB Layout section). A second
precaution regarding the ceramic input capacitor concerns
the maximum input voltage rating of the LT3964. A ceramic
input capacitor combined with trace or cable inductanceforms a high quality (under damped) tank circuit. If theLT3964 circuit is plugged into a live supply, the input voltage can ring to twice its nominal value, possibly exceeding
the LT3964’s voltage rating. This situation can be easily
avoided (see Linear Technology Application Note 88).
INTVCC REGULATOR
An internal low dropout (LDO) regulator produces the 4V
supply from VIN that powers the drivers and the internalbias circuitry. The INTVCC can supply enough current for
the LT3964’s circuitry and must be bypassed to groundwith a minimum of 2.2μF X7R or X5R ceramic capacitor.
Good bypassing is necessary to supply the high transientcurrents required by the power MOSFET gate drivers.
Applications with high input voltage and high switchingfrequency will increase die temperature because of thehigher power dissipation across the LDO.

3964 F02

Figure 2. Forming 2nd Pole with RLEDSELECTING THE INPUT CAPACITORS
Bypass the input of the LT3964 circuit with a ceramic capacitor of X7R or X5R type. Y5V types have poor performanceover temperature and applied voltage, and should not be
used. A 4.7μF to 10μF ceramic capacitor is adequate to
bypass the LT3964 and will easily handle the ripple current.
Note that larger input capacitance is required when a lower
switching frequency is used. If the input power source has

PROGRAMMING INPUT UNDERVOLTAGE LOCKOUT
The LT3964 will stop switching and disable the PWMTG
driver when the voltage at the EN/UVLO pin drops below
precisely 1.18V, but internal circuitry will continue drawing
current. A small 4μA pull-down current is active when EN/
UVLO is below this threshold. Full shutdown is guaranteed
when EN/UVLO is below 0.4V, and in full shutdown theLT3964 will draw less than 1μA.

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LT3964APPLICATIONS INFORMATION
An external voltage source can be used to set the voltage
at EN/UVLO and enable or disable the LT3964 at will. Alternatively, a resistor network can be placed between VIN and
EN/UVLO as shown in Figure 3. The following equations
should be used to determine the values of the resistor:
VIN(FALLING) = 1.18V •VIN(RISING) = 1.23V •REN1 +REN2
REN1

REN1 +REN2+ 4µA •REN2
REN1

Two external resistors program the maximum IC junction
temperature using a resistor divider from the INTVCC pin,
as shown in Figure 4. Choose the ratio RTSET1 and RTSET2
for the desired junction temperature. Figure 5 shows therelationship of TSET voltage to junction temperature.
A 10nF capacitor in parallel with RTSET1 is recommended
if the TSET node picks up switching noise due to bad PCB
layout practice.
INTVCCRTSET2VIN
REN2LT3964
TSET

C
(OPT)

LT3964RTSET13964 F04

EN/UVLO

Figure 4. Programming the TSET

REN13964 F03

950

Figure 3. EN/UVLO Resistor Configuration

900
850

USING THE TSET PIN FOR THERMAL PROTECTION

The operation of the thermal loop is simple. As the ambient temperature increases, so does the internal junction
temperature is reached, the LT3964 begins to linearly
reduce the LED current, as needed, to try and maintain thistemperature. This can only be achieved when the ambient
temperature stays below the desired maximum junction
temperature. If the ambient temperature continues to rise
past the programmed maximum junction temperature,
the LEDs current will be reduced to approximately zero.
While this feature is intended to directly protect the LT3964,
it can also be used to derate the LED current at high temperatures. Since there is a direct relationship between the
LED current and LT3964 junction temperature, the TSET
function also provides some LED current derating at hightemperatures.

18

800
VTSET (mV)The LT3964 contains a special programmable thermal
regulation loop that limits the internal junction temperature of the part. This thermal regulation feature provides
important protection at high ambient, and allows a give
application to be optimized for typical, not worst-case,ambient temperatures with the assurance that the LT3964
will automatically protect itself and the LED strings underworst-case conditions.

TSET

VISP–ISN FOLD BACK TO 95mV

750
700
650
600
550
500
450
–55

–25

5
35
65
95
TEMPERATURE (°C)

125

155

3964 F05

Figure 5. TSET Pin Threshold vs Junction Temperature

SELECTING A MOSFET FOR PWM DIMMING
Pulse-width-modulation of the LED current is an effective
way to control the brightness of the light without varying
its color. The brightness can also be adjusted with finer
resolution this way than by varying the current level.
The LT3964 features a PWMTG driver that is intended fora high-voltage PMOS switch in position to effect PWM
dimming by connecting and disconnecting the string ofLEDs from the output capacitor and the current sense
resistor. When the switch is open and the string is disconnected, the LED current will be zero. In contrast to a
low-side NMOS driver, this feature eliminates the need fora dedicated return path for the LED current in automotive
applications or other grounded-chassis systems.
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LT3964APPLICATIONS INFORMATION
A high side PMOS disconnected switch with a minimum
VTH of –1V to –2V is recommended in most LT3964 applications. The drain-source voltage rating of the chosen
PMOS should be greater than the maximum output voltage
set by the FB pin and ID rating should be above ILED. A
diode with anode connected to ground and cathode to thedrain of the PWMTG MOSFET as D1 shown in Figure 6 canprotect that device from overvoltage caused by excessive
inductance in the LED string. Table 6 lists three recommended manufacturers of PMOS devices.
L

RLED
COUT
D1
ISP

ISN

PWMTG

LT39643964 F06

Figure 6. Catch Diode for Short Circuit Protection with
Disconnect PMOS
Table 6. PMOS Manufacturers

MANUFACTURER
Infineon Technologies
Vishay Inter Technology
Renesas Electronics

WEBSITE
www.infineon.com
www.vishay.com
www.am.renesas.com

PROGRAMMING OUTPUT VOLTAGE (CONSTANTVOLTAGE REGULATION) OR OUTPUT CLAMP
For applications that have fixed LED loads and output
capacitor, the LT3964’s voltage feedback pin FB can beused to program the OPENLED clamp voltage by selecting
the values of RFB1 and RFB2 (see Figure 7) according to
the following equation:
VOUT = 1.18V •RFB1 +RFB2
RFB1

VOUT
RFB2
LT3964FB
RFB13964 F07

Figure 7. FB Resistor Configuration for Applications
with Output Capacitor

If the OPENLED clamp voltage is programmed correctly
using the resistor divider, then FB pin should never exceed
1.08V to guarantee that the LED current is only regulatedby CTRL pin when the LEDs are connected. For best performance, set OPENLED clamp voltage about 10% higher
than the maximum LED string voltage.
If the output voltage is near the maximum when the LED
string breaks, it may take too long for the feedback loop
to adjust the inductor current and avoid overcharging theoutput. Thus it is possible that the FB voltage can exceed
the 1.18V regulation voltage momentarily. However, if
the FB voltage exceeds 1.233V (typical), the overvoltage lockout threshold, the LT3964 will immediately stop
switching and the PWMTG driver is turned off. Meanwhile,
the STATUS[4] bit (for Channel 1) or STATUS[0] bit (forChannel 2) in the chip status register is written to logic
high, and the ALERT pin is also asserted.
For applications with wide dynamic and time-varying LED
loads, a 100nF capacitance is recommended at output node.
However, if output node can still overshoot beyond VIN
during open circuit (OPENLED), then a Schottky diode isrequired to clamp output to VIN shown in Figure 8. The BV
rating of the Schottky has to be higher than maximum VIN.
Another Schottky diode is recommended to protect ISP
and ISN from ringing below ground due to the excessive
inductance in the LED string. To avoid falsely triggering
SHORTLED (FB < 250mV), a resistor from INTVCC to FB
is included to disable this feature.

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LT3964APPLICATIONS INFORMATION
VIN

VSW
20V/DIVDCLAMP1
L

RLED

VOUT

SW

DCLAMP2

INTVCC

C OUT
100nF

CFILT
RFB2

RFILT (OPT)RFB3

VALERT
5V/DIV

RFB1

IPMOS
10A/DIVFB
LT3964VLED+
10V/DIV

ISP

500ns/DIVISN

3964 F09

Figure 9. PWMTG Response to Short Circuit Fault

3964 F08

Figure 8. Output Clamp for Applications with No
Output Capacitor

OPENLED DETECTION
To detect open-circuit condition at the output, the LT3964
monitors both output voltage and current. When FB exceeds
VFB – 53mV and V(ISP-ISN) is less than 10mV, the OPENLED
status bit, STATUS[5] for (Channel 1) or STATUS[1] for(Channel 2) in the chip status register, is written to logic
1, and the ALERT pin is also asserted.
SHORTLED AND OVERCURRENT PROTECTIONFEATUREThe resistor network formed by RFB1 and RFB2 also defines
the criteria for short circuit (SHORTLED). For the LT3964,
a short circuit is when FB is less than 250mV after initialstart-up. STATUS[6] (for Channel 1) or STATUS[2] (forChannel 2) in the chip status register is set at the same time.
An application without direct output sensing is shown in
Figure 6. LT3964 also monitors output overcurrent (V(ISPISN) > 930mV typically) to decide output short. Once anovercurrent is detected, STATUS[7] bit (for Channel 1) or
STATUS[3] bit (for Channel 2) in the chip status register
is set and ALERT pin will be pulled low simultaneously.
In both cases, LT3964 stops switching and pulls PWMTG
high intermediately to disconnect the LED array from thepower path as shown in Figure 9.

LT3964 has two different ways to respond to SHORTLED
or OC fault: hiccup or latchoff. The default is hiccup. Oncea fault is detected, an internal fault timer starts. When thetimer expires and the fault disappears, the LT3964 will restartup. The PWMTG is pulled high, and switching starts
after a fixed internal soft start time. Figures 10 and 11
show the LT3964 response to a short circuit fault in hiccup mode. In I2C mode, the ALERT pin is kept asserted
even though the fault is removed, whereas the ALERT pin
is de-asserted in non-I2C mode.
VSW
20V/DIV
VLED+
10V/DIV
VALERT
5V/DIV
VPMOS
10A/DIV
5ms/DIV

3964 F10

Figure 10. Hiccup Response to Short Circuit Fault in I2C Mode

VSW
20V/DIV
VLED+
10V/DIV
VALERT
5V/DIVIPMOS
10A/DIV
5ms/DIV

3964 F11

Figure 11. Hiccup Response to Short Circuit Fault in Non-I2C Mode

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LT3964APPLICATIONS INFORMATION
Latch-off mode is another way that the LT3964 can be
programmed to respond to faults. When a fault happens,
the CONFIG[7] in the chip configuration register (seeTable 11) is set via I2C, and LT3964 will stop switchingand pull PWMTG pin high immediately. LT3964 will stay
non-switching even if all faults have been removed asshown in Figure 12. To exit latchoff mode, the EN/UVLO
pin must be toggled low to high.
VSW
20A/DIV
VLED+
10V/DIV
VALERT
5V/DIVIPMOS
10A/DIV
5ms/DIV

3964 F12

Figure 12. Latch-off Response to a Short Circuit Fault

PRECAUTIONS REGARDING REVERSED INPUTCURRENT
LT3964 is not designed to run a large reversed input current, greater than 200mA continuously, from SW pin to
the VIN pin through the top switch when the top switch
is in off state. This cautionary note explains the situation
where this potentially damaging condition can develop,
and what measures can be taken to protect the top switch
if this condition is likely. Small negative inductor currents,
100mA or less, are expected and acceptable for periods
less than a switching cycle. This is expected during normal operation at low LED current. One event that causes
large, potentially damaging negative inductor currents toflow through the parasitic body diode of the top switch isa ground fault on the supply when the output is charged.
This input fault event is not common, but the user should

be aware of it. The three conditions which, when seen
together, are more likely to lead to a potentially damaging
reverse current level while the top switch is off are:
1. The buck output voltage is almost equal to VIN supply;
2. The output voltage is high at the beginning of theswitching cycle; and3. The inductor current is close to zero when the low sideturns on briefly to charge the BST capacitor
The reason these three conditions can lead to sustained
negative inductor current is because when the bottom
switch is ON, big voltage is seen across inductor to causea large negative inductor ripple even for 40ns period oftime (bottom switch minimum ON time). After the bottom switch turns off, both switches are in off state for theremaining switch cycle. Thus the negative inductor current
continues to flow backwards through the top switch body
diode for an extended period of time due to little voltage
across the inductor. The VIN equal to VOUT condition canbe encountered during an OPENLED event if the constantvoltage regulation is set close to VIN; and alternatively,
if VIN drops to a level where the LED Vf is close to VIN.
In the former instance (OPENLED) the switching will be
discontinuous since there is no load, so inductor current
is likely going negative during BST refresh cycle when low
switch is on. If this operational condition is expected (i.e.,
VOUT/(VOUT – VIN) > 10), a 10μH or larger value inductor
will prevent generating a large negative inductor current
during brief pulse on the synchronous FET. For applications that are running at high die temperature over 125°C,
a Schottky diode is strongly suggested to provide extra
protection and bypass negative inductor current aroundthe top switch, as shown in Figure 13.
LT3964

VIN
D1
SW

L

3964 F13

Figure 13. Reverse Input Current Protection

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21

LT3964APPLICATIONS INFORMATIONCHANNEL-LEVEL ALERT REPORTING
When a channel-level fault happens, the LT3964 will set
the corresponding reporting bit in the chip status register(see Table 7), which is also latched until the master sends
a command to reset it. If the corresponding bit in the chip
status register (see Table 8) is high, LT3964 will report
this fault by pulling down the ALERT pin.
Table 7. Chip Status Register
CHIP STATUS
REGISTER[BIT]

VALUE SETTINGSTATUS[0]0*1Ch1 Output Voltage Normal
Ch1 Output Overvoltage (OVFB)STATUS[1]0*1Ch1 LED Normal
Ch1 LED Open (OPENLED)STATUS[2]0*1Ch1 LED Normal
Ch1 LED Shorted (SHORTLED)

STATUS[3]0*1Ch1 Output Current Normal
Ch1 Output Overcurrent (OC)STATUS[4]0*1Ch2 Output Voltage Normal
Ch2 Output Overvoltage (OVFB)STATUS[5]0*1Ch2 LED Normal
Ch2 LED Open (OPENLED)STATUS[6]0*1Ch2 LED Normal
Ch2 LED Shorted (SHORTLED)

STATUS[7]0*1Ch2 Output Current Normal
Ch2 Output Overcurrent (OC)*Denotes Default Power-On Value.

Table 8. Chip Status Enable Register
CHIP STATUS ENABLE
REGISTER[BIT]VALUE

SETTING

STATEN[0]01*Disable Reporting Ch1 OVFB
Enable Reporting Ch1 OVFBSTATEN [1]01*Disable Reporting Ch1 OPENLED
Enable Reporting Ch1 OPENLED

STATEN [2]01*Disable Reporting Ch1 SHORTLED
Enable Reporting Ch1 SHORTLED

STATEN [3]01*Disable Reporting Ch1 OC
Enable Reporting Ch1 OC

STATEN [4]01*Disable Reporting Ch2 OVFB
Enable Reporting Ch2 OVFBSTATEN [5]01*Disable Reporting Ch2 OPENLED
Enable Reporting Ch2 OPENLED

STATEN [6]01*Disable Reporting Ch2 SHORTLED
Enable Reporting Ch2 SHORTLED

STATEN [7]01*Disable Reporting Ch2 OC
Enable Reporting Ch2 OC

The LT3964 will respond to the master alert response
inquiry (ARI) by sending back the chip address. If operated in I2C mode, the ALERT pin is kept asserted until thetransfer is successfully completed. After that, the LT3964
will not respond to future ARI requests until a new alert
event occurs and ALERT pin is asserted again. Once themaster receives the chip address, the master will decide
whether to read back the full alert information from LT3964
and reset the chip status register. To minimizing the alert
reporting, LT3964 doesn’t report the same fault over again
if the corresponding STATUS bit is not cleared.
In non-I2C mode, the LT3964 reports faults independentof the I2C register. Whenever LT3964 detects OVFB and
OPENLED faults, the ALERT pin is asserted. SHORTLED
and OC faults usually keep ALERT pin asserted until theinternal soft-start fault timer expires and the faults havebeen removed.
PWM DIMMING CONTROL FOR BRIGHTNESSPWM dimming is used to modulate the LED current between
zero and full current to achieve a precisely programmed
average current, without the possibility of color shift that
occurs at low current in LEDs. To make PWM dimming
more accurate, the switch demand current is stored on theinternal VC node during the quiescent phase when PWM islow. This feature minimizes recovery time when the PWM
signal goes high. To further improve the recovery time, adisconnect switch should be used in the LED current pathto prevent the output capacitor from discharging during the
PWM signal low phase. The minimum PWM on or off timedepends on the choice of operating frequency set by the
RT input. For best current accuracy, the minimum PWM
high time should be at least two switching cycles (1µs for
fSW = 2MHz).

*Denotes Default Power-On Value.

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LT3964APPLICATIONS INFORMATION
A low duty cycle PWM signal can cause excessive start-up
times if it were allowed to interrupt the soft-start sequence.
Therefore, once start-up is initiated, the LT3964 will ignore
a logical disable by the PWM input signal. The device willcontinue to soft-start with switching and TG enabled until
either the internal soft-start time expires or the output
current reaches one-fifth of the full-scale current. At thispoint the device will begin following the dimming control
as designated by PWM pin input or PWM input via I2C.
The internal PWM dimming signal is controlled by both
PWM pin input (PWMEXT) and I2C PWM registers (CH1PWM1, CH1PWM2, CH2PWM1, CH2PWM2). In non-I2C
mode, the PWM registers output are set to 1 permanently,
thus the internal PWM dimming signal is only gated by
PWMEXT. In I2C mode, PWM registers are initially set
to 0 after power on reset. It can be updated according tointended dimming frequency and dimming duty cycle. The
PWM registers for Channel 1 shown in Tables 9 and 10
have the following outputs:
PWM Frequency =PWM Duty Cycle =The LT3964 can drive a LED string in either PWM (pulse
width modulation) mode or BAM (Bit Angle Modulation)mode that is set by the combination of CONFIG[3]/[2] andCONFIG[1]/[0] as shown in Tables 11 and 12. Bit Angle
Modulation (BAM) is a LED drive technique that can be usedwith fixed or variable frequency modulation. In essence,the LED is driven by a pulse train that is the binary word
defining the value of required intensity. Each bit of thepulse train is stretched by a ratio defined by the binary
significance of each bit (CH1_ON[bit] or CH2_ON[bit]).
Table 13 shows the ratio by which each bit is stretched,and Figure 10 shows an BAM example for CH1_ON[6:0]= 001101b and SCALE[2:0] = 000b.
Table 9. Channel 1 (CH1) PWM Register 1 (CH1PWM1)CH1 PWM
REGISTER1[BIT]

VALUE SETTING

CH1PWM1[0]0*1

PWMON Time 5th MSB CH1_ON[8] = 0
PWMON Time 5th MSB CH1_ON [8] = 1

CH1PWM1[1]0*1

PWMON Time 4th MSB CH1_ON [9] = 0
PWMON Time 4th MSB CH1_ON [9] = 1

CH1PWM1[2]2
CH1_ON[SCALE[2:0]+5:0]

0*
1

PWMON Time 3rd MSB CH1_ON[10] = 0
PWMON Time 3rd MSB CH1_ON [10] = 1

CH1PWM1[3]0*1

PWMON Time 2nd MSB CH1_ON[11] = 0
PWMON Time 2nd MSB CH1_ON [11] = 1

2(SCALE[2:0]+6)

CH1PWM1[4]0*1

PWMON Time MSB CH1_ON[12] = 0
PWMON Time MSB CH1_ON[12] = 1

CH1PWM1[5]0*1

PWMON FREQ Scalar LSB SCALE[0] = 0
PWMON FREQ Scalar LSB SCALE[0] = 1

CH1PWM1[6]0*1

PWMON FREQ Scalar 2nd MSB SCALE[1] = 0
PWMON FREQ Scalar 2nd MSB SCALE[1] = 1

CH1PWM1[7]0*1

PWMON FREQ Scalar MSB SCALE[2] = 0
PWMON FREQ Scalar MSB SCALE[2] = 1

fSW(SCALE[2:0]+6)

where fSW is the switching frequency. For example, if
SCALE[2:0] = 7, then the PWM frequency is fSW/8192, and
the PWM duty cycle is CH1_ON[12:0]/8192. If SCALE[2:0]= 0, then PWM frequency is fSW/64. The higher order
bits, CH1_ON[12:6], are neglected and PWM duty cycle
is defined by CH1_ON[5:0]/64.
Note the maximum achievable PWM duty cycle set by PWM
registers is 8191/8192. To achieve 100% PWM dimming,
the CONFIG[3]/[2] in the chip configuration register has
to be cleared. Usually PWM registers offer better PWM
dimming performance as the dimming control signals arealigned up with the internal clock.

*Denotes Default Power-On Value for I2C Mode. PWMON Denotes PWMON TIME. FREQ Denotes PWM Frequency.

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LT3964APPLICATIONS INFORMATION
Table 10. Channel 1 (CH1) PWM Register 2 (CH1PWM2)

Table 12. I2C PWM Dimming Setting

CH1 PWM
REGISTER2 [BIT]CONFIG[3]/[2]

CONFIG[1]/[0]1

1

Bit Angle Modulation

10Regular Pulse Width Modulation

0x

I2C PWM Dimming Disabled(Always On)

CH1PWM2[0]VALUE SETTING0*1

PWMON Time LSB CH1_ON[0] = 0
PWMON Time LSB CH1_ON[0] = 1

CH1PWM2[1]0*1

PWMON Time 12th MSB CH1_ON[1] = 0
PWMON Time 12th MSB CH1_ON[1] = 1

CH1PWM2[2]0*1

PWMON Time 11th MSB CH1_ON[2] = 0
PWMON Time 11th MSB CH1_ON[2] = 1

CH1PWM2[3]0*1

PWMON Time 10th MSB CH1_ON[3] = 0
PWMON Time 10th MSB CH1_ON[3] = 1

ACTION

Table 13. Stretch Ratio of Each PWMON Bit
BIT POSITIONSTRETCHED BY

CH1_ON[12]

4096
2048

CH1PWM2[4]0*1

PWMON Time 9th MSB CH1_ON[4] = 0
PWMON Time 9th MSB CH1_ON[4] = 1

CH1_ON[11]CH1PWM2[5]0*1

PWMON Time 8th MSB CH1_ON[5] = 0
PWMON Time 8th MSB CH1_ON[5] = 1

CH1_ON[10]1024

CH1_ON[9]512

CH1PWM2[6]0*1

PWMON Time 7th MSB CH1_ON[6] = 0
PWMON Time 7th MSB CH1_ON[6] = 1

CH1_ON[8]256

CH1_ON[7]128

CH1PWM2[7]0*1

PWMON Time 6th MSB CH1_ON[7] = 0
PWMON Time 6th MSB CH1_ON[7] = 1

CH1_ON[6]64CH1_ON[5]32CH1_ON[4]16CH1_ON[3]8CH1_ON[2]4CH1_ON[1]2

CH1_ON[0]1*Denotes Default Power-On Value for I2C Mode.

Table 11. Chip Configuration Register
CHIP
CONFIGURATIONREGISTER [BIT]

VALUE SETTING

CONFIG[0]0*1Channel 2 PWM Mode
Channel 2 BAM Mode

CONFIG[1]0*1Channel 1 PWM Mode
Channel 1 BAM Mode

CONFIG[2]01*Channel 2 PWM Registers’ Output Disabled(Always On)
Channel 2 PWM Registers’ Output Enabled

CONFIG[3]01*Channel 1 PWM Registers’ Output Disabled(Always On).
Channel 1 PWM Registers’ Output Enabled

CONFIG[4]x

Not Used

CONFIG[5]x

No UsedCONFIG[6]0*1

Clock Output Disabled
Clock Output Enabled

CONFIG[7]0*1Latchoff Mode Disabled
Latchoff Mode Enabled

ONE PWM PERIOD = 64 CLOCK CYCLES
1 1

2

4

8

16

32

1 1
3964 F14

Figure 14. BAM Example*Denotes Default Power-On Value for I2C Mode. BAM Denotes Bit Angle
Modulation.

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LT3964APPLICATIONS INFORMATIONI2C OPERATIONI2C Acknowledge

I2C Interface

The acknowledge signal is used for handshaking between
the master and the slave. When the LT3964 is written to,it acknowledges its write address and subsequent register
address and data bytes. When reading from the LT3964,
it acknowledges its read address and 8-bit status byte. An
acknowledge pulse (active LOW) generated by the LT3964
lets the master know that the latest byte of information
was transferred. The master generates the clock cycle
and releases the SDA line (HIGH) during the acknowledge
clock cycle. The LT3964 pulls down the SDA line during
the write acknowledge clock pulse so that it is a stable
LOW during the HIGH period of this clock pulse.

The LT3964 communicates with a bus master using thestandard I2C 2-wire interface. The two bus lines, SDA and
SCL, must be HIGH when the bus is not in use. External
pull-up resistors or current sources are required onthese lines. The LT3964 is both a slave receiver and slavetransmitter. The I2C control signals, SDA and SCL have
TTL thresholds (min 1.5V high threshold and max 0.4V
low threshold). I2C internal logic gates are powered fromINTVCC. When INTVCC is below approximately 3.2V, theI2C serial port is reset to power-on states and registers
are set to default values.
I2C Bus Speed
The I2C port operates at speeds up to 400kHz. It has
built-in timing delays to ensure correct operation whenaddressed from an I2C compliant master device. It also
contains input filters designed to suppress glitches should
the bus become corrupted.
I2C START and STOP Conditions
Figure 15 shows I2C port timing information. A bus mastersignals the beginning of communications by transmitting
a START condition. A START condition is generated bytransitioning SDA from HIGH to LOW while SCL is HIGH.
The master may transmit either the slave write or theslave read address. Once data is written to the LT3964,
the master may transmit a STOP condition that commands
the LT3964 to act upon its new command set. A STOP
condition is sent by the master by transitioning SDA from
LOW to HIGH while SCL is HIGH. The bus is then free forcommunication with another I2C device.
I2C Byte Format
Each byte sent to or received from the LT3964 mustbe 8 bits long followed by an extra clock cycle for the
acknowledge bit. The data should be sent to the LT3964
most significant bit (MSB) first.

I2C Device Addressing
Eight distinct bus addresses are configurable using ADDR2
and ADDR1 pins. Table 14 shows the correspondence
between ADDR2 and ADDR1 pin states and addresses.
The least significant bit of the address byte, known as theread/write bit, is 0 when writing data to the LT3964 and
1 when reading from it. There is also one global addressavailable at 0001100R/W to send or inquire informationfrom all slaves on the same I2C bus (see I2C broadcast
mode for more information).
Table 14. Slave Address Map (110 A3 A2 A1 A0 R/W)
ADDR2

ADDR1

A3

A2

A1

A0

GND

FLOAT

0

0

0

1

GND

INTVCC

0

0

1

1

FLOAT

GND

0

1

0

0

FLOAT

FLOAT

0

1

0

1

FLOAT

INTVCC

0

1

1

1

INTVCC

GND

1

1

0

0

INTVCC

FLOAT

1

1

0

1

INTVCCINTVCC

1

1

1

1

GND*

GND

0

0

0

0

*Non-I2C Mode: Internal PWM Dimming Function is Disabled.

3964f

For more information www.linear.com/LT3964

25

LT3964APPLICATIONS INFORMATIONI2C Sub-Addressed Writing
The LT3964 has 9 command registers that can be accessedby the I2C port via a sub-addressed writing system. Eachwrite cycle of the LT3964 consists of a series of three bytes
beginning with the LT3964 write address. The second byteis the sub-address of the command register being written
to. The sub-address is a pointer to the register where thedata in the third byte will be stored. The third byte is thedata to be written to the just-received sub-address.
I2C Bus Write Operation
The master initiates communication with the LT3964 witha START condition and the LT3964 write address. If theaddress matches that of the LT3964, the LT3964 returns
an acknowledge pulse. The master should then deliver
the sub-address. Again the LT3964 acknowledges andthe cycle is repeated for the data byte. The data byte istransferred to an internal holding latch upon the return of
its acknowledgement by the LT3964. If desired a REPEATSTART condition may be initiated by the master whereanother device on the I2C bus is addressed. The LT3964
remembers the valid data it has received. Once all thedevices on the I2C have been addressed and sent valid
data and a global STOP has been sent, the LT3964 will
update its command latches with the data it has received.
Figure 16 shows the LT3964 I2C serial port write pattern.
I2C Sub-Addressed Reading
The LT3964 I2C interface supports random address readingof the I2C command and status registers. Before reading a
register, the register’s sub-address must be written. Send

26

a START condition followed by the LT3964 write address
followed by the sub-address of the register to be read.
The sub-address is now stored as a pointer to the register.
Send a REPEAT-START condition followed by the LT3964
read address. Following the acknowledgment of its readaddress the LT3964 returns one bit of information foreach of the next 8-clock cycles. A STOP condition is not
required for the read operation. The read sub-address isstored until a new sub-address is written. Verify the data
written to the internal data hold latches prior to committing data to the command registers by reading back thedata before sending a STOP condition. Continuously poll aregister by repeatedly sending a START condition followedby the LT3964 read address, and then clocking the dataout after the read address acknowledge. Figure 17 shows
the LT3964 I2C serial port read pattern.
I2C Command and Status Registers
There are nine I2C command/status registers and three
read-only I2C part number registers in the LT3964. All of
the information for these registers is shown in Tables 15.
I2C Broadcast (BCMODE)
The BCMODE write command (0001 1000) is used tosynchronize the PWM dimming cycles among the multiple
LT3964 slaves on the I2C bus. The LT3964 slaves must
be operating with a common external clock in order to besynchronized. The command does not modify any register
bits. It only resets each channel counter to synchronize
the dimming cycles.

3964f

For more information www.linear.com/LT3964

1

2

1

1

SCL

START

1

SDA

1

For more information www.linear.com/LT3964

3

0

0

A1
A0

4

A3

5

A2

6

7

2

1

SCL

ADDRESS

1

1

1

SDA

START

1

8

0

0

tr

7

A0

tf

8

0

0

9

ACK

REPEATED START
CONDITION

tSU, STAtSPtHD, STA

1

S7

2

S6

3

S5

4

S4

5

S3

6

S2

SUB ADDRESS

7

S1

8

S0

9

ACK

Figure 15. I2C Serial Port TimingtHD, DAT

1

R7

2

R6

4

5

S3

6

S2

7

S1

8

S0

3

0

0

2

3

0

0

4

A3

5

A2

6

A1

4

1

1

5

1

1

6

0

0

7

0

0

8

1

1

9

SLAVE
ACK

1

1

1

2

1

1

3

0

0

4

A3

5

A2

6

A1

7

A0

ALERT RESPONSE ADDRESSFROM SLAVE LT3964

7

A0

Figure 18. LT3964 I2C Serial Port Broadcast Read Pattern

2

1

SCL

0

1

1

9

1

1
REPEATED
START
ACK
1

ADDRESS

Figure 17. LT3964 I2C Serial Port Read Pattern

S4

BROADCAST MODE ADDRESS3S5SUB ADDRESS

3

8

0

0

R5

Figure 16. LT3964 I2C Serial Port Multiple Write Pattern

0

0

2

S6

6

A1

0

1

S7

5

A2

tHIGH

tSU, DAT

SDA

START

9

4

A3

ADDRESS

tLOW

ACK

3

0

0

START
CONDITION

tHD, STA

SCL

SDA

8

1

1

5

R3

9

1

R7

6

R2

3964 F18

MASTERNOT ACK
STOP

9

ACK

MNA

4

R4

DATA

7

R1

2

R6

STOP
CONDITION

3964 F15

8

R0

3

4

R4

5

R3

DATA

6

R2

STOP

3964 F16

9

ACK

START
CONDITION

R5tBUFtSU, STO

7

R1

8

R0

9

MNA

3964 F17

MASTERNOT ACKSTOP

LT3964

APPLICATIONS INFORMATION

3964f

27

LT3964APPLICATIONS INFORMATION
Table 15. LT3964 Command Register Table
REG

NAME

B[7]

B[6]

B[5]

B[4]

B[3]

B[2]

B[1]

B[0]

DEFAULT

0x01

CONFIG

Latchoff
Mode Enable
Bit
0 = Disabled
1 = Enabled

Clock Output
Enable Bit
0 = Disabled
1 = Enabled

Not Used

Not Used

Channel 1
Pulse Dim
Enable Bit
0 = Disabled(Always On)
1 = Enabled

Channel 2
Pulse Dim
Enable Bit
0 = Disabled(Always On)
1 = Enabled

Channel 1
Pulse Dim
Type Bit
0 = PWM Mode
1 = BAM Mode

Channel 2
Pulse Dim
Type Bit
0 = PWM Mode
1 = BAM Mode

00xx 1100

0x02

CH1PWM1

Channel 1
PWM FREQ
Scalar MSB

Channel 1
PWM FREQ
Scalar 2nd
MSB

Channel 1
PWM FREQ
LSB

Channel 1
PWM ONTime MSB

Channel 1
PWM ONTime 2ndMSB

Channel 1
PWM ONTime 3rdMSB

Channel 1
PWM ON Time
4th MSB

Channel 1
PWM ON Time
5th MSB

0000 0000

0x03

CH1PWM2

Channel 1
PWM ONTime 6th MSB

Channel 1
PWM ONTime 7th MSB

Channel 1
PWM ONTime 8th MSB

Channel 1
PWM ONTime 9th MSB

Channel 1
PWM ONTime 10th
MSB

Channel 1
PWM ONTime 11th
MSB

Channel 1
PWM ON Time
12th MSB

Channel 1
PWM ON Time
LSB

0000 0000

0x04

CH2PWM1

Channel 2
PWM FREQ
Scalar MSB

Channel 2
PWM FREQ
Scalar 2nd
MSB

Channel 2
PWM FREQ
LSB

Channel 2
PWM ONTime MSB

Channel 2
PWM ONTime 2ndMSB

Channel 2
PWM ONTime 3rdMSB

Channel 2
PWM ON Time
4th MSB

Channel 2
PWM ON Time
5th MSB

0000 0000

0x05

CH2PWM2

Channel 2
PWM ONTime 6th MSB

Channel 2
PWM ONTime 7th MSB

Channel 2
PWM ONTime 8th MSB

Channel 2
PWM ONTime 9th MSB

Channel 2
PWM ONTime 10th
MSB

Channel 2
PWM ONTime 11th
MSB

Channel 2
PWM ON Time
12th MSB

Channel 2
PWM ON Time
LSB

0000 0000

0x06

ADIM1

Channel 1
AnalogDimming
MSB

Channel 1
AnalogDimming 2nd
MSB

Channel 1
AnalogDimming 3rd
MSB

Channel 1
AnalogDimming 4th
MSB

Channel 1
AnalogDimming 5th
MSB

Channel 1
AnalogDimming 6th
MSB

Channel 1
AnalogDimming 7th
MSB

Channel 1
AnalogDimming LSB

1111 1111

0x07

ADIM2

Channel 2
AnalogDimming
MSB

Channel 2
AnalogDimming 2nd
MSB

Channel 2
AnalogDimming 3rd
MSB

Channel 2
AnalogDimming 4th
MSB

Channel 2
AnalogDimming 5th
MSB

Channel 2
AnalogDimming 6th
MSB

Channel 2
AnalogDimming 7th
MSB

Channel 2
AnalogDimming LSB

1111 1111

0x08

STATEN

Channel 2
Overcurrent
Reporting
Enable Bit
0 = Disabled
1 = Enabled

Channel 2
SHORTLED
Reporting
Enable Bit
0 = Disabled
1 = Enabled

Channel 2
OPENLED
Reporting
Enable Bit
0 = Disabled
1 = Enabled

Channel 2
Overvoltage
Reporting
Enable Bit
0 = Disabled
1 = Enabled

Channel 1
Overcurrent
Reporting
Enable Bit
0 = Disabled
1 = Enabled

Channel 1
SHORTLED
Reporting
Enable Bit
0 = Disabled
1 = Enabled

Channel 1
OPENLED
Reporting
Enable Bit
0 = Disabled
1 = Enabled

Channel 1
Overvoltage
Reporting
Enable Bit
0 = Disabled
1 = Enabled

1111 1111

0x09

STATUS

Channel 2
Overcurrent
Reporting Bit
0 = NO
1 = YES

Channel 2
SHORTLED
Reporting Bit
0 = NO
1 = YES

Channel 2
OPENLED
Reporting Bit
0 = NO
1 = YES

Channel 2
Overvoltage
Reporting Bit
0 = NO
1 = YES

Channel 1
Overcurrent
Reporting Bit
0 = NO
1 = YES

Channel 1
SHORTLED
Reporting Bit
0 = NO
1 = YES

Channel 1
OPENLED
Reporting Bit
0 = NO
1 = YES

Channel 1
Overvoltage
Reporting Bit
0 = NO
1 = YES

0000 0000

28

3964f

For more information www.linear.com/LT3964

LT3964APPLICATIONS INFORMATIONThe BCMODE read command (0001 1001) is used to inquire
about which LT3964 slave on the bus is sending the alert(see Alert Response Protocol section for details). This
command is two bytes long. The first byte is the broadcast
read address 00011001. The second byte 110A3A2A1A00
is sent by the alerting slave, where A3A2A1A0 is an input
logic value from the programmable address select pins
ADDR2 and ADDR1 shown in Table 14. Figure 18 shows
LT3964 BCMODE read pattern.
ALERT RESPONSE PROTOCOL
In a system where several slaves share a common interrupt
line, the master can use the alert response address (ARA) to
determine which device initiated the interrupt. The masterinitiates the ARA procedure with a START condition andthe special 7-bit ARA bus address (0001100) followed by
the read bit (R) = 1. If the LT3964 is asserting the ALERT
pin, it acknowledges and responds by sending its 7-bit
bus address (110A3A2A1A0) and a 0. While it is sending its
address, it monitors the SDA pin to see if another device issending an address at the same time using standard I2C bus
arbitration. If the LT3964 is sending a 1 and reads a 0 on
the SDA pin on the rising edge of SCL, it assumes anotherdevice with a lower address is sending and the LT3964
immediately aborts its transfer and waits for the next ARA
cycle to try again. If transfer is successfully completed, theLT3964 will de-assert its ALERT pin and will not respondto further ARA requests until a new alert event occurs.

It should only join the ground for the input and output
capacitors and the return path for the LED current at the
exposed pad. To keep thermal resistance low, extend theground plane as much as possible, and thermal vias underand near the LT3964 to additional ground planes within
the circuit board and on the bottom side.
There are a few other aspects of the board design that
improve performance. Likewise minimizing the area of
the SW and BST nodes reduces noise. The traces for FB
pins should be kept short to lessen the susceptibility ofthese high impedance nodes to noise. Minimizing the connections from the external current sense resistor RLED to
the ISP and ISN pins are essential for current regulation
accuracy. The INTVCC bypass capacitor as well as the BST
capacitor should be placed as closely as possible to theirrespective pins.
Figure 19 shows the simplified two sided layout of powercomponent placement with traces, ground plane and via
locations. Note that the 4-layer layout is recommended
for best performance. Please contact the factory for thereference layout design.
GND

VIN1

SW1

ISP1
BST1

ISN1

LED1+

PWMTG1DESIGNING THE PRINTED CIRCUIT BOARD
For proper operation and minimum EMI, care must be taken
during printed circuit board layout. Usually, large switchedcurrents flow through the local input capacitors and the VIN
and GND pins. The loops traveled by these currents should
be made as small as possible by keeping the capacitors as
close as possible to these pins. These capacitors, as wellas the large inductor, should be placed on the same sideof the board as the LT3964 and connected on the samelayer. Other large, bulk input capacitors can be safely placed
farther from the chip and on the other side of the board.
Create a Kelvin ground network by keeping the groundconnection for all of the other components separate.

FB1
FB2

GND

PWMTG2

BST2
VIN2

ISP2

SW2

ISN2

LED2+

GND
3964 F19

VIAS TO GROUND PLANE

ROUTING ON THE 2ND PLANE

Figure 19. Simplified Layout for Dual Buck LED Driver
3964f

For more information www.linear.com/LT3964

29

LT3964
TYPICAL APPLICATIONS
Short-LED Robust, 50W Dual Buck 1A LED Driver with Internal PWM Dimming
31V TO 36V(ENABLED AT 33V,
SHUTDOWN AT 31V)

CIN0
10µF
×2
50V

CIN1
2.2µF
50V

REN1
100k

VIN1

BST1

GND

SW1

CBST1
L1
0.22µF
10µH
RFB1
1M

EN/UVLO
REN2
3.92k
INTVCC
C2
2.2µF

INTVCCRTSET1
499k
RTSET2
165k

I

R1
100k

CIN2
2.2µF
50V

R2
27.4k
2MHz

2-WIRE

2C INTERFACE

PWM1
PWM2
CTRL1
CTRL2
INTVCCFB1

LT3964

GND

BST2

CBST2
L2
0.22µF
10µH

1A
UP TO
26V LEDs

RLED2
100mΩ
RFB3
1M

FB2
RFB4
43.2k

SYNC/CLKOUT

COUT2
2.2µF
50V

M2

1A
UP TO
26V LEDs

ISP2
ISN2
PWMTG2
ADDR1 ADDR2INTVCC

L1, L2: WURTH 74437349100
M1, M2: VISHAY Si2319CDS

COUT1
2.2µF
50V

ISP1
ISN1
PWMTG1

SW2

TSET
RT

SCL
SDA

M1

RFB2
43.2k

ALERT
VIN2

RLED1
100mΩ

3964 TA02a

PWM Dimming at VIN = 34V
ILED1
1A/DIVPWM DC = 4/8192

IL1
1A/DIV
ILED2
1A/DIVPWM DC = 6/8192

IL2
1A/DIV
1µs/DIV30

3964 TA02b

3964f

For more information www.linear.com/LT3964

LT3964
TYPICAL APPLICATIONS
Multi-Channel Boost Buck LED Driver
L1 10µH

VIN
6V TO 24V
ILED DERATESAT VIN < 8V

CIN1
10µF

RCTRL1100k

CTRL

RCTRL1
17.4k

+

REN1
105k

VIN

REN2
28k

REN3
100k

RSEN
10M

LT3757

VC

CSS
0.1µF

GND

C2
4.7µF

R1
10k
C1
10nF

VIN1

INTVCC
C3
2.2µF

INTVCCRTSET1
499k
RTSET2
165k

I

R3
100k

CIN3
2.2µF
50V

BST1

GND

SW1

R4
27.4k
2MHz

2-WIRE

2C INTERFACE

CTRL1
CTRL2
PWM1
PWM2
INTVCC

CBST1
0.22µF L2
10µH

LT3964ISP1
ISN1
PWMTG1
BST2

SW2

CBST2
0.22µF L3
10µH

RLED2
100mΩ

M3

COUT4
2.2µF
50V

RFB5
1M

TSET
RT

FB2

1A
UP TO
26V LEDs

RFB6
43.2k

SYNC/CLKOUT

L1: VISHAY SILICONIX IHLP-5050FD-01 10μH
L2, L3: WURTH 74437349100
M1: INFINEON BSC030N04NS
M2, M3: VISHAY Si2319CDS
D1: DIODES PDS1040

1A
UP TO
26V LEDs

RFB4
43.2k

GND

SCL
SDA

M2

COUT3
2.2µF
50V

RFB3
1M

FB1

ALERT
VIN2

RLED1
100mΩ

RFB2
11.8k

INTVCCISP2
ISN2
PWMTG2
ADDR1 ADDR2INTVCC3964 TA03a

Efficiency
Efficiency
94

BOTH CHANNELS ARE ON

92
90
EFFICIENCY (%)

CTRL
CTRL

COUT
4.7µF
50V

RFB1
261k

SENSE

EN/UVLO
REN4
3.92k

M1

34.5V
COUT1
47µF
50V

FBX

RT
SS

CIN2
2.2µF
50V

GATE

SHDN/UVLO

SYNC

R2
41.2k
300kHz

D1

88
86
84
82
80

6

8

10

12

14 16
VIN (V)

18

20

22

24

3964 TA03b

3964f

For more information www.linear.com/LT3964

31

LT3964
TYPICAL APPLICATIONSMatrix LED Driver
BST1

31V TO 36V(ENABLED AT 33V,
SHUTDOWN AT 31V)
CIN1
10µF
×2
50V

CIN2
2.2µF
50V

REN1
100k

SW1

VIN1
GND

CBST1 L1
0.22µF 68µH

RLED1
200mΩ
RFB1
1M RFB3
274k

FB1
RFB2
31.6k

EN/UVLO
REN2
3.92k

COUT1
100nF
50V

M1

LED1+

COUT2
10µF

SRC7
DRN6

C2
2.2µF

ALERT

INTVCC
PWM1
PWM2
CTRL1
CTRL2

SRC5
DRN4

PWMTG1SYNC/CLKOUT

CLOCK

ALERT
LT3964

CIN3
2.2µF
50V

INTVCCRTSET1
499k

VIN2

GND

BST2

CBST2
0.22µF L2
68µH
RFB4
1M RFB6
274k

FB2
R3
178k
360kHz

COUT3
100nF
50V

M2

LED2+

COUT4
10µF

2-WIREI2C INTERFACE

ADDR1

SRC2
DRN1

LEDREF
RTCLK

SRC1

SCL
SDA

DRN8

VIN

ISP2

SRC5
DRN4

PWMTG2

SCL
SDA

SRC4
DRN3
UP TO 26V LED

SRC3
DRN2
SRC2
DRN1

L1, L2: WURTH 7447709680
M1, M2: VISHAY Si2319CDS

SRC1

R1
100k
ALERT

LEDREF
CLOCK (FROM LT3964)
2-WIREI2C INTERFACE
31V TO 36V
REN5
49.9k
Q2

EN/UVLO

SRC6
DRN5

LED1+

5V

CIN5
1µF

GND

SRC3
DRN2

SRC7
DRN6

ISN2
INTVCC

VDD

ALERT
ADDR1
ADDR2
ADDR3
ADDR4

CIN4
1µF
50V

REN4
9.02k

LT3965SRC8DRN7INTVCC

RFB5
31.6k

RT
ADDR2

RLED2
200mΩ

SW2

TSET
RTSET2165k

EN/UVLOSRC4DRN3UP TO 26V LED

REN3
49.9k REN7
10k
Q1

SRC6
DRN5

ISN1

31V TO 36V

VIN

SRC8
DRN7

INTVCCISP1

INTVCC

DRN8

REN8
10k

CIN6
1µF
50V
LED2+

REN6
9.02k
5V
CIN7
1µF

VDD
LT3965
GND
ALERT

ALERT

ADDR1
ADDR2
ADDR3
ADDR4
LEDREF
RTCLK

LEDREF
CLOCK (FROM LT3964)

SCL
SDA

2-WIREI2C INTERFACE

3964 TA04a

Single LED PWM Dimmingat
IN ==34V
at VVIN
34V

Efficiency, VIN = 34V
100
98

VCLKOUT
5V/DIVBOTH CHANNELS ARE ON

96
PWM DC = 1/256

EFFICIENCY (%)

VDRAIN8
2V/DIVIN

IL1
500mA/DIV
ILED1500mA/DIV

94
92
90
88
86
84

5µs/DIV

3964 TA04b82
80

50 100 150 200 250 300 350 400 450 500
ILED (mA)
3964 TA04c

32

3964f

For more information www.linear.com/LT3964

LT3964
PACKAGE DESCRIPTION

Please refer to http://www.linear.com/product/LT3964#packaging for the most recent package drawings.
UHE Package
36-Lead Plastic QFN (5mm × 6mm)

(Reference LTC DWG # 05-08-1876 Rev Ø)
0.70 ±0.05

5.50 ±0.05
4.10 ±0.05
3.50 REF

PACKAGEOUTLINE

3.60 ±0.05
4.60 ±0.05

0.25 ±0.05
0.50 BSC
4.50 REF
5.10 ±0.05
6.50 ±0.05
PIN 1 NOTCH
R = 0.30 TYP
OR 0.35 × 45°
CHAMFER

RECOMMENDED SOLDER PAD LAYOUTAPPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

5.00 ±0.10

0.00 – 0.05
0.200 REF

R = 0.10
TYP

3.50 REF
29

36
0.40 ±0.10

PIN 1
TOP MARK(SEE NOTE 6)28

6.00 ±0.10

14.50 REF
4.60 ±0.10
3.60
±0.10
20

10
(UHE36) QFN 0410 REV Ø

0.75 ±0.05

190.25 ±0.05

11
R = 0.125
TYP

0.50 BSC
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATIONON THE TOP AND BOTTOM OF PACKAGE

3964f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnectionof its circuits
as describedherein will not infringe on existing patent rights.
For more
informationwww.linear.com/LT3964

33

LT3964
TYPICAL APPLICATION
Dual 1A Single LED Driver

LED

CIN1
2.2µF

REN1
100k

VIN1

BST1

GND

SW1

CBST1
0.22µF L1
2.2µH

INTVCC
C2
2.2µF

R1
100k

CIN2
2.2µF

INTVCC

FB1

ALERT
VIN2

R2
27.4k
2MHz

2-WIREI2C INTERFACE

LT3964

COUT1
2.2µF

ISP1
ISN1
PWMTG1
BST2

84
82
80
78
76
74
72
70

CBST2
0.22µF L2
2.2µH

RLED2
100mΩ

SW2
RFB3
1M

TSET
RT

M2

6

8

10

12

14 16
VIN (V)

18

20

22

24

3964 TA05b

COUT2
2.2µF

FB2
RFB4
357k

SYNC/CLKOUT
SCL
SDA

86
M1

RFB1
357k

GND

RTSET1
499k
RTSET2
165k

PWM1
PWM2
CTRL1
CTRL2
INTVCC

RLED1
100mΩ
RFB1
1M

EN/UVLO
REN2
28.7k

BOTH CHANNELS ARE ON

88

EFFICIENCY (%)

CIN3
10µF

Efficiency, ILED = 1A
90

6V TO 24V
(ENABLED AT 6V,
SHUTDOWN AT 5.2V)

ADDR1

ISP2
ISN2
PWMTG2ADDR23964 TA05a

INTVCC
L1, L2: COILCRAFT XAL4020-222MEB
M1, M2: VISHAY Si2365EDSRELATED PARTS
PART NUMBER DESCRIPTIONCOMMENTS

LT3922

36V, 2A Synchronous Step-Up LED Driver

VIN(MIN) = 2.8V, VIN(MAX) = 36V, VOUT = 40V, 128:1 Internal Dimming and
5,000:1 External Dimming, ISD = 1μA, 4mm × 5mm QFN-28

LT3932

36V, 2A Synchronous Step-Down LED Driver

VIN(MIN) = 3.6V, VIN(MAX) = 36V, VOUT = 0V to 36V, 128:1 Internal Dimmingand 5,000:1 External Dimming, ISD = 1μA, 4mm × 5mm QFN-28

LT3952

60V, 4A Synchronous Step-Up LED Driver

VIN(MIN) = 3V, VIN(MAX) = 42V, VOUT = 0V to 60V, 5:1 Internal Dimming and
4,000:1 External Dimming, ISD = 1μA, TSSOP-28E

LT3795High Side 110V, 1MHz LED Driver with 3,000:1 PWM
Dimming with Spread Spectrum Frequency Modulation

VIN(MIN) = 4.5V, VIN(MAX) = 110V, VOUT = 110VMAX, 3000:1 PWM, 20:1
Analog, ISD = <1µA, TSSOP-28E

LT3956

80VIN/80VOUT, ISW = 3.3A, 1MHz LED Driver with 3,000:1 VIN(MIN) = 4.5V, VIN(MAX) = 80V, VOUT = 40VMAX, 3000:1 PWM, 20:1
PWM Dimming
Analog, ISD = <1µA, 5mm × 6mm QFN-36

LT3761High Side 100V, 1MHz LED Controller with 3,000:1 PWM
Dimming and Internal PWM Generator

VIN(MIN) = 4.5V, VIN(MAX) = 60V, VOUT = 80VMAX, 3000:1 PWM, 20:1
Analog, ISD = <1µA, MSOP-16E

LT3755/
LT3755-1/
LT3755-2

High Side 75V, 1MHz LED Controller with 3,000:1 PWM
Dimming

VIN(MIN) = 4.5V, VIN(MAX) = 40V, VOUT = 5V to 75V, 3000:1 PWM, 20:1
Analog, ISD = <1µA, 3mm × 3mm QFN-16 and MSOP-16E

LT3756/
LT3756-1/
LT3756-2

High Side 100V, 1MHz LED Controller with 3,000:1 PWM
Dimming

VIN(MIN) = 6.0V, VIN(MAX) = 100V, VOUT = 5V to 100V, 3000:1 PWM, 20:1
Analog, ISD = <1µA, 3mm × 3mm QFN-16 and MSOP-16E

34

3964f
LT 0717 • PRINTED IN USA

For more information www.linear.com/LT3964

www.linear.com/LT3964
 LINEAR TECHNOLOGY CORPORATION 2017