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AN11599
Using power MOSFETs in parallel
Rev. 1 — 7 July 2015

Application note

Document information
Info

Content

Keywords

MOSFET, parallel, share, power, current, capability, group, array

Abstract

Increasing the capability of a MOSFET switch element by using several
individual MOSFETs connected in parallel can be useful. However, when
designing switch elements careful consideration of the circuit requirements
and the MOSFET characteristics and behavior must be applied. Thisapplication note explores some of the problems that can be experienced
when several MOSFETs are operated in a paralleled group. It alsosuggests ways to avoid the problems and minimize their effects.

AN11599

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Using power MOSFETs in parallel

Revision history
Rev

Date

Description

01

20150707

initial version

Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
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Using power MOSFETs in parallel

1. Introduction
One much publicized benefit of power MOSFETs (compared to other semiconductor
devices) is that it is easy to parallel them to create a group with increased capability.
Although this feature is superficially true, there are several potential problems that cancatch out the unwary circuit designer.
A MOSFET consists of a group of paralleled ‘cells’ fabricated on the surface of a silicondie. All the cells are created at the same time under the same conditions. When the
MOSFET is fully enhanced and conducts channel current, the temperatures of all the cells
are very similar. As the cells are structurally and thermally closely matched, they share
current and power well and the parameters of the MOSFET can be well-defined.
There is a range of values for the parameters of the MOSFET dies on a wafer. There is a
wider range for MOSFET dies on different wafers in the same production batch. The
range is even wider for all batches even though the MOSFETs are the same type.
MOSFETs with parameter values outside the data sheet limits are rejected.
The MOSFETs in a paralleled group should all be the same type, but their parameters
could be anywhere within the data sheet range. Their die temperatures are unlikely to be
the same. Consequently their power sharing is not perfect.
This document contains guidelines on how to design a group of MOSFETs to get the best
performance from them. The design must accommodate MOSFET variations within thedata sheet limits. It must also allow for MOSFET parameter variations over the range ofelectrical and environmental conditions. If all the MOSFETs in the group work within theirsafe maximum limits, the paralleled group of MOSFETs operates reliably.
It is technically and commercially undesirable to have to select MOSFETs and it should be
unnecessary. The circuit should be designed to accommodate any MOSFET within theworst case RDS(on) range.
The key data sheet limit which must not be exceeded is the maximum junction
temperature Tj(max) of 175 C.

2. Static (DC) operation
This situation is the simplest condition where current flows through a group of paralleled
MOSFETs that are fully enhanced (switched ON). A proportion of the total current flows
through each MOSFET in the group. At the initial point of turn on, the die temperatures of
all the MOSFETs in the group are the same. The drain current ID flowing in each MOSFET
is inversely proportional to its RDS(on) (the drain-source voltage VDS across all the
MOSFETs is the same).
The MOSFET with the lowest RDS(on) takes the highest proportion of the current anddissipates the most power (power dissipation P = VDS  ID).
All the MOSFETs heat up, but the MOSFET with the lowest RDS(on) heats up most(assuming the Rth(j-a) of all the MOSFETs is the same).

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Using power MOSFETs in parallel

MOSFET RDS(on) has a positive temperature coefficient. RDS(on) increases as Tj increases.
The die temperatures and RDS(on) values of all MOSFETs in the group rise, but the dietemperature of the lowest RDS(on) MOSFET increases disproportionately. The effect of thisbehavior is to redistribute the current towards the other (higher RDS(on)) MOSFETs in thegroup.
Stable thermal equilibrium is reached after a period of operation. The lowest RDS(on)MOSFET is the hottest, but carries a lower proportion of the current than it did initially.
The Positive Temperature Coefficient (PTC) of RDS(on) is a stabilizing influence that
promotes power sharing between the MOSFETs in the group. However, as stated earlier
the most important criterion is that the maximum junction temperature of any MOSFET inthe group must not exceed 175 C.
The cooling of each MOSFET in the group depends on its thermal resistance fromjunction to ambient. Die temperature influences the heat flow from adjacent MOSFETs.
Rather than considering the thermal resistance paths between the MOSFET dies, themain influence is the temperature of the common heatsink. All the MOSFET mounting
bases are bonded electrically and thermally to this heatsink.
The lowest RDS(on) MOSFET could be located anywhere in the group. The thermal
resistance from mounting base to ambient of all the MOSFETs in the group should be as
similar as possible and as low as possible. Cooling is optimized and independent oflocation.
This thermal resistance solely depends on the thermal characteristics and design of theassembly [Printed-Circuit Board (PCB) or heatsink] to which the MOSFET is thermallybonded.
Sometimes a value for Rth(j-a) is given in data sheets but this parameter is of very limited
value. It cannot be treated as a well-defined parameter because it also depends on otherexternal factors such as PCB construction, PCB orientation and air flow. The only
guaranteed thermal parameter is the thermal resistance from the MOSFET junction tomounting base Rth(j-mb).

2.1 Worked examples for static operation
The worked examples that follow are based on the BUK764R0-40E.
Table 1.

Thermal characteristics

SymbolParameter

Conditions

Rth(j-mb)

thermal resistance from junction to mounting baseRth(j-a)thermal resistance from junction to ambient

minimum footprint;
mounted on a PCB

Min

Typ

Max

Unit

-

-

0.82

K/W

-

50

-

K/W

A typical group of MOSFETs has a range of RDS(on) values. The distribution has a peak ataround the typical data sheet RDS(on) value; none should have an RDS(on) higher than thedata sheet maximum. The RDS(on) of about half of the samples is less than the typicalvalue.
Minimum RDS(on) is not given in the data sheet, but a good estimate is

AN11599

Application note

R DS(on)(min)  R DS(on)(max) – 2  R DS(on)(max) – R DS(on)(typ) (1)

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4 of fmAN11599

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Using power MOSFETs in parallel

The RDS(on) value range means that a group of typical MOSFETs is very unlikely to sharepower equally when they are operated in parallel.
The worst case would be when one of the MOSFETs has the minimum RDS(on) and all theothers have the maximum RDS(on).
Modeling of the electro-thermal system is complex because its electrical and thermal
characteristics are mutually dependent. However, an electro-thermally convergent Excelmodel can be used to estimate the performance characteristics of a paralleled group.
As an example, in a worst case situation three BUK764R0-40E MOSFETs are connectedin parallel; two have maximum RDS(on) of 4 m. The other has a lower than typical RDS(on)of 2.6 m.
The MOSFET with the lowest RDS(on) value takes the highest proportion of the current.
It therefore has the highest power dissipation.
The target is to keep the junction temperature of the hottest MOSFET below 175 C underworst case operating conditions.
These estimations are simplified illustrations. The thermal representation of the MOSFET
group is less complex than a real application. In a real application, there are other factors
such as neighboring components and orientation that would influence cooling. However,they show the approximate behavior of the group with two different Rth(j-a) values.
The first scenario shows the system with the thermal resistance from junction to ambientfor each MOSFET (Rth(j-a) = 20 K/W; Tamb = 125 C).

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Electrical and thermal schematic diagram of the three paralleled BUK764R0-40E
MOSFETs

Table 2 shows the maximum safe limits of VDS, ID, P and Tj for all the MOSFETs at thermal
equilibrium. At this point, the junction temperature of the hottest MOSFET is almost
175 C.

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Table 2.

MOSFET maximum conditions for Rth(j-a) = 20 K/W and Tamb = 125 C

MOSFET VDS Rth(j-a) RDS(on)(25C) Initial
Initial[V] [K/W] [m]RDS(on)(125C) current
[m]
ID
[A]

Initial
power
P
[W]

Initial Final
power RDS(on)share [m]
[%]

Final
current
ID[A]

Final Final Final
power Tj
powerP[C] share
[W]
[%]

M1

0.11 20

2.6

4.16

42.31

4.65

43.5

4.92

22.36

2.46

174

42.3

M2

0.11 20

4

6.4

27.50

3.03

28.3

7.21

15.26

1.68

159

28.9

M3

0.11 20

4

6.4

27.50

3.03

28.3

7.21

15.26

1.68

159

28.9

Total initial power P(M1 + M2 + M3) = 10.70 W
Total final power P(M1 + M2 + M3) = 5.82 W
The second scenario relates to the same electrical system, but with ideal thermal
characteristics. The thermal resistance Rth(j-a) of each MOSFET is 0.82 K/W. Thissituation corresponds to the ideal but unrealistic situation where each MOSFET isperfectly thermally bonded to an infinite heatsink (a heatsink with zero thermal
resistance).

0

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HOHFWULFDO
LQWHUIDFH

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96

Fig 2.

%8.5(5'6 RQ &  Pȍ

DDD

Electrical and thermal schematic diagram of the three paralleled BUK764R0-40E MOSFETs with ideal
thermal conditions

Table 3 shows the values of VDS, ID, P and Tj for all the MOSFETs at thermal equilibrium.
At this point, the junction temperature of the hottest MOSFET is almost 175 C.
Table 3.

MOSFET maximum conditions for Rth(j-a) = 0.82 K/W and Tamb = 125 C

MOSFET VDS[V]

Rth(j-a) RDS(on)(25C) Initial
Initial[K/W] [m]RDS(on)(125C) current
[m]
ID
[A]

Initial
power
P
[W]

Initial Final
power RDS(on)share [m]
[%]

Final
current
ID[A]

Final Final Final
power Tj
power[C] share
P
[W]
[%]

M1

0.55 0.82

2.6

4.16

211.54116.35 43.5

4.92

111.79

61.48

174

42.3

M2

0.55 0.82

4

6.4

137.50

75.63

28.3

7.21

76.28

41.96

159

28.9

M3

0.55 0.82

4

6.4

137.50

75.63

28.3

7.21

76.28

41.96

159

28.9

Total initial power P(M1 + M2 + M3) = 267.60 W
Total final power P(M1 + M2 + M3) = 145.39 W
Note: This scenario is ideal and unrealistic. It is included to illustrate the benefit ofreducing Rth(j-a) to maximize the usage of the MOSFET capabilities.
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In practice, Rth(j-a) is always greater than Rth(j-mb). The thermal bonding between the
MOSFET mounting base and the heatsink is never perfect and an infinite heatsink does
not exist in the real world.
In this case, the drain current (ID) of the MOSFETs becomes the limiting factor (the data
sheet maximum ID is 75 A).
To optimize MOSFET utilization, the MOSFETs must be able to dissipate as much power
as possible. At the same time, the junction temperature of the hottest MOSFET mustremain below the maximum safe temperature of 175 C.
The following conclusions can be drawn from Table 2 and Table 3:
1. It is beneficial to reduce Rth(j-a) as much as possible to optimize the MOSFET die
cooling.
2. It is beneficial to reduce the maximum ambient temperature to increase the available
thermal 'headroom'.
3. As a result of Table 2 and Table 3, it is clear that junction temperature difference
between the MOSFETs depends only on their RDS(on) values (assuming the Rth(j-a) for
each MOSFET is the same).
4. When the paralleled (fully enhanced) MOSFETs heat up during use, their power
distribution changes such that the cooler MOSFETs take a greater proportion of thepower. This effect is due to the PTC of RDS(on) and it acts to promote thermal stability.

3. MOSFET mounting for good thermal performance and power sharing
To get the most from the MOSFET group, the individual MOSFET should be mounted in a
way that causes their mounting base temperatures to be as similar as possible and also
as low as possible.
To realize this goal, the thermal resistance between each MOSFET (mounting base) andthe mounting bases of all the other MOSFETs in the group should be matched andminimized. They should be mounted symmetrically and as close together as possible on athermally conductive surface.
Heat flow can be considered to be analogous to electric current flow; so the thermalbonding points of the MOSFETs (usually the drain tabs) should be on a thermal ‘ring
main’. The low thermal resistance path allows heat to flow easily between the MOSFETs.
When heat flows easily between all the MOSFETs in the group, their mounting basetemperatures track together closely.
Note: This arrangement does not promote equal current sharing, but promotes better dietemperature matching. The temperatures of all the MOSFETs in the group can rise more
before the temperature of the hottest MOSFET reaches 175 C. Hence the power
dissipation capability of the group is maximized.
There are practical limits to the physical extent of the thermal ring main; ideally each
MOSFET should be next to all its neighbors. This condition limits the group to two or three
MOSFETs.

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Using power MOSFETs in parallel

DDD

This layout suits standard packaged MOSFETs (e.g. D2PAK, LFPAK and TO-220). The dark shaded area corresponds to thedrain tab of the device.

Fig 3.

A layout for six paralleled MOSFETs to promote good power sharing

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a. Two paralleled MOSFETs
where both devices arelocated directly opposite
each other on the two facesof a PCB
Fig 4.

DDD

DDD

b. Two paralleled MOSFETs
where the devices arelocated next to each other on
the same face of a PCB

c. Three paralleled MOSFETs
where the devices arelocated in a symmetrical loop
other on one face of a PCB

Good layout arrangements for two paralleled MOSFETs and three paralleled MOSFETs

A good way to parallel a pair of MOSFETs is to locate them on opposite faces of a PCB
forming a PCB ‘sandwich’ as in Figure 4a. Thermal vias between the copper ‘land’ areas
on the PCB reduce the electrical and thermal resistances between their mounting bases.
To parallel a pair of MOSFETs on the same face of a PCB, they can be mounted next toeach other as in Figure 4b.
A good way to parallel three MOSFETs is in a ring as in Figure 4c. This arrangement
allows all the MOSFET sources in the group to be connected to a ‘star’ point. The
electrical and thermal paths between the MOSFET drains match due to their symmetricalconnections to the drain loop.

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Minimizing and matching the electrical impedances in the source paths is more important
than matching the electrical impedance in the drain paths. This difference is because theirgate drives are related to the sources. Good impedance matching in both drain andsource is more important in high frequency switching circuits.
If similar electrical and thermal matching can be achieved, larger paralleled groups could
be considered. Groups of more than four or five become unwieldy so grouped sub groups
should be used.

DDD

DDD

a. Six paralleled MOSFETs based on two sub groupsof three MOSFETs
Fig 5.

b. Nine paralleled MOSFETs based on three
sub groups of three MOSFETs

Layouts using sub groups of three MOSFETs

In this group of 9 (3 groups of 3), there is a natural drain star point at the center of thegroup. There are separate source star points at the centers of each sub group. The sourcestar points can be connected on a layer of a multi-layer PCB.
There is a compromise between optimizing layout for power sharing and maximizing PCB
usage.
Electrically and thermally optimized layouts always use more PCB area than the minimum
possible, but utilization of MOSFET capability should be better. Areas of PCB that areunoccupied by MOSFETs or gate drive components are useful for thermal interfaces withheat sink or cooling air.

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4. Power sharing in dynamic operation [pulse and Pulse Width
Modulation (PWM) circuits]
Many MOSFET circuits are designed to operate in systems where they are switchedrepetitively (such as DC-to-DC converters). Paralleled MOSFETs can be used as theswitching elements in the system, but in addition to the guidelines set out for optimal
steady state power sharing. Some additional points must be considered so that the
MOSFETs share current during the switching transitions.
Good circuit and layout design is important. It influences the proportion of current carriedby each MOSFET in the group during and after the switching event.

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Fig 6.

Schematic diagram showing the stray source inductances and source resistances

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a. MOSFET drain current distribution immediately
after turn on. The time base scale is
100 ns/division.
Fig 7.

DDD

b. The same MOSFET drain current distribution as in
Figure 7a showing the changes as time progress.
The time base scale is 100 s/division.

Oscilloscope plots showing the MOSFET drain currents (black, red and blue) and drain source voltage(yellow) after turn on

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Figure 7a and Figure 7b show how the current distribution in three paralleled MOSFETs
initially depends on the source inductances in the MOSFET current paths, namely L1, L2and L3. As time progresses the resistances in the MOSFET current paths, namely
RDS(on) + R1, RDS(on) + R2 and RDS(on) + R3 determine the current distribution.
The same principles hold about impedance matching of the current paths to the
MOSFETs in the group. In this case, it is more important for the rates of change of current
in the MOSFETs to match. The source inductances are the key impedance as they affect
the gate-source voltages (gate drives) of the MOSFETs in the group.
This effect dominates more in high frequency and short duty cycle applications (e.g.
switched-mode power supplies). It may be insignificant in lower frequency applications
such as motor drives.

5. Partially enhanced (linear mode) power sharing
If a group of MOSFETs must operate in linear (partially enhanced) mode, great caution isneeded. MOSFETs simply paralleled together as they are for fully enhanced conduction
are very unlikely to share power or current well.
This behavior is due to the Negative Temperature Coefficient (NTC) of gate thresholdvoltage VGS(th). As the group of MOSFETs starts to enhance, the MOSFET with the lowest
VGS(th) starts to conduct channel current first. It dissipates more power than the others andheat up more. Its VGS(th) decreases even further which causes it to enhance further.
This unbalanced heating causes the hottest MOSFETs to take a greater proportion of thepower (and get even hotter). This process is unsustainable and can result in MOSFET
failure if the power is not limited. Great care is needed when designing paralleled power
MOSFET circuits that operate in the partially enhanced (linear mode) condition.
If all the MOSFETs in the group operate within their Safe Operating Area (SOA), they work
reliably. The SOA must be adjusted for the worst case mounting base temperature that
occurs in the application. Remember that the data sheet SOA graph applies only if the
MOSFET mounting base temperature is 25 C or less.
Adding external source resistors (R1 to R4 in the schematic; see Figure 8) provides thenegative feedback needed for stable operation. The gate-source voltage applied to
VGS(M1) = VG  ID(M1)  R1.
If the MOSFETs must also operate in fully enhanced mode (e.g. in ‘Hot Swap’ or ‘Soft
Start’ applications), the inclusion of these resistors is an efficiency disadvantage.
As the MOSFET channel current increases, its gate drive voltage reduces.
As the MOSFETs are operating in partial enhancement (where MOSFET RDS(on) is notimportant), there is no adverse effect caused by including these resistors. If the MOSFETs
must operate in both modes (as with active clamping after fully enhanced conduction), theinclusion of source resistors does have a negative impact.

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Using power MOSFETs in parallel

5/

0

0

5

0

5

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'

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Fig 8.

Schematic diagram of a group of four paralleled MOSFETs intended to operate inlinear mode

MOSFETs developed specifically for linear mode operation are available from NXP. They
can simplify the design of paralleled groups of MOSFETs intended for linear mode
operation.

6. Gate drive considerations
It is preferable to fit low value gate resistors between the gate driver and the gate of each
MOSFET in the group.
Their main function is to decouple the MOSFET gates from each other so they all receive
similar gate drive signals. Without these resistors, at turn on the Miller plateau of the
MOSFET with the lowest threshold voltage would act to clamp the gate-source voltages ofthe other MOSFETs in the group. This clamping effect tends to inhibit and delay theturning on of the other MOSFETs in the group. At turn off a similar process occurs.
Without these resistors, the MOSFET with the lowest threshold voltage would switch on
first and switch off last. The consequences of this effect may be insignificant in low
frequency high duty cycle applications. In higher frequency PWM applications, it could
cause a significant power imbalance between the MOSFETs. Positive feedback also
occurs in this case which increases the imbalance and could ultimately cause MOSFET
failure.
Gate resistors also help to damp out oscillatory transients on VGS. They also swamp any
effects caused by variations in the internal gate resistance RG(int) of the MOSFETs.

6.1 Should individual gate drivers be used for each MOSFET in thegroup?
Using individual gate drivers for each MOSFET in the group is usually unnecessary. They
may be necessary in applications where fast switching of a large group of large die
MOSFETs is needed. Here the MOSFETs should be arranged in smaller sub groups, each
sub group driven by an individual gate driver. Care should be taken to balance the circuitso the propagation delays of all the gate drivers are similar. This matching ensures thatthe switching of all the MOSFETs in the group is synchronized. Usually it is sufficient toAN11599

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Using power MOSFETs in parallel

drive the gate of each MOSFET in the group from the same gate driver. However, it isimportant to have a gate resistor between the gate driver output and the gate of each
MOSFET as mentioned earlier.

7. MOSFET packaging considerations for paralleled groups
Conventionally packaged surface-mounted MOSFETs (DPAK and D2PAK) are the mostwidely available types so they are considered first for paralleled groups. However, KGD
and LFPAK (power SO8) MOSFETs could offer better solutions.

7.1 Bare die (KGD) MOSFETs
These MOSFETs offer the densest and most flexible options for paralleled groups; they
are designed to suit a specific application. The die aspect ratio and gate pad location canbe designed specifically to suit the application. More source wire bonds can be fitted tothe die than can be fitted in a conventionally packaged MOSFET, so overall RDS(on) can be
reduced. Maximum drain current can be increased to achieve better performance from aparalleled group of MOSFETs. Special manufacturing facilities are required for KGD
assembly.

7.2 LFPAK MOSFETs
The power SO8 (LFPAK) MOSFETs offer the opportunity to manufacture the paralleled
MOSFET circuit conventionally. Higher component density and power capability are
possible (approaching that of KGDs). The connections to the source and gate are madeusing copper clips which give better electrical and thermal performance than aluminum
wire bonds in conventional packages.

8. Inductive energy dissipation in paralleled MOSFETs
8.1 Avalanching - low side MOSFET group driving a high side inductiveload
If the group of paralleled MOSFETs is driving an inductive load, energy stored in this load
must be safely dissipated when the current is switched off. A good way to manage thisenergy is to connect a ‘freewheel diode’ across the load; see Figure 9. Current flowing in
the MOSFET channel diverts into the diode when the MOSFETs switch off and the energy
is dissipated in the circuit resistances. However, it is not always possible and energy mustthen be dissipated safely in the MOSFETs.
If the battery polarity (Vsup) is reversed, the low impedance path through the freewheel
diode and the body diode can carry large damaging currents. Freewheel diodes are often
not used for this reason.

AN11599

Application note

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Using power MOSFETs in parallel

When the group of MOSFETs is switched off, the back e.m.f. from the inductive load may
be high enough to cause the drain-source voltage across the group of MOSFETs toexceed the drain-source breakdown voltage V(BR)DSS of one of the MOSFETs. It likely that
MOSFETs in the group have a range of V(BR)DSS values (even though they are the sametype). The current then flows through the body diode of the MOSFET with the lowest
V(BR)DSS in reverse (avalanche) conduction. This condition causes high-power dissipationand temperature rise in the MOSFET die (P = ID  V(BR)DSS). If the maximum 175 Cjunction temperature is exceeded, the thermal stress on the die could degrade or destroy
the MOSFET.
In the worst case, all the current which was flowing through the group of MOSFETs could
be diverted into the body diode of one MOSFET in the group. If this scenario is possible, it
is vital that a single MOSFET in the group can safely handle the total avalanche current
under worst case thermal conditions. V(BR)DSS has a positive temperature coefficientwhich tends to redistribute the current towards other MOSFETs with higher V(BR)DSS
values.

IUHHZKHHOGLRGH

0

0
'

5

9VXS

/

0
'

5

'

'

5

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DDD

Fig 9.

Low side MOSFET group driving a high side inductive load

8.2 Active clamping - high side MOSFET group driving a low sideinductive load
This configuration (see Figure 10) is often used in automotive applications. This topology
is useful because the vehicle chassis can be used as the negative supply return path tothe battery.

0
5

0
'

0
'

5

'

5

JDWHGULYH
/

9VXS

DDD

Fig 10. High side MOSFET group driving a low side inductive load
AN11599

Application note

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Rev. 1 — 7 July 2015

© NXP Semiconductors N.V. 2015. All rights reserved.

14 of fmAN11599

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Using power MOSFETs in parallel

In this circuit, the difference between the threshold voltages rather than V(BR)DSS spread
determines where the load current flows. The MOSFET with the lowest threshold voltage
conducts the greatest proportion of the current. The drain-source voltage across the
MOSFET group is Vsup + VGS and the power dissipation of the group is (Vsup + VGS)  ID.
As with the avalanche case, all the current (and hence all the power dissipation) could bediverted into a single MOSFET in the group.
This situation is worse than the avalanche case because MOSFET threshold voltage has
a negative temperature coefficient. This characteristic tends to direct the current flow
initially to the hottest MOSFET. This MOSFET then gets even hotter so that it retains thecurrent.

9. Summary
1. It is better to use a single large MOSFET rather than a group of smaller MOSFETs.
2. The power capability of a group of n MOSFETs never achieves n times the power
capability of a single MOSFET.
3. If it is necessary to use paralleled MOSFETs, use the lowest number possible as thebasic group size (3 maximum).
4. If a larger number is needed, use a group of basic groups i.e. 4 = 2 groups of 2;
6 = 2 groups of 3.
5. The circuit layout is a very important factor determining how well a group of paralleled
MOSFETs share power dissipation, particularly in higher frequency repetitive
switching circuits.
6. Consider LFPAKs (for repetitive switching applications) because of their small size,
good thermal performance and low package impedances.
7. Special care is needed when designing groups of MOSFETs that could operate inavalanche or active clamping mode.

10. Abbreviations
Table 4.

AN11599

Application note

Abbreviations

AcronymDescription

KGD

Known Good Die

MOSFET

Metal-Oxide Semiconductor Field-Effect Transistor

NTC

Negative Temperature Coefficient

PCB

Printed-Circuit Board

PTC

Positive Temperature Coefficient

PWM

Pulse Width Modulation

SOA

Safe Operating Area

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Rev. 1 — 7 July 2015

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Using power MOSFETs in parallel

11. Legal information
11.1

Definitions

Draft — The document is a draft version only. The content is still underinternal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences ofuse of such information.

11.2

Disclaimers

Limited warranty and liability — Information in this document is believed tobe accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy orcompleteness of such information and shall have no liability for theconsequences of use of such information. NXP Semiconductors takes noresponsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not suchdamages are based on tort (including negligence), warranty, breach ofcontract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordancewith the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to makechanges to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical orsafety-critical systems or equipment, nor in applications where failure or

AN11599

Application note

malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability forinclusion and/or use of NXP Semiconductors products in such equipment orapplications and therefore such inclusion and/or use is at the customer's own
risk.
Applications — Applications that are described herein for any of theseproducts are for illustrative purposes only. NXP Semiconductors makes norepresentation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer productdesign. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications andproducts planned, as well as for the planned application and use ofcustomer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with theirapplications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in thecustomer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications andthe products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a priorauthorization from competent authorities.
Translations — A non-English (translated) version of a document is forreference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.

11.3

Trademarks

Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.

All information provided in this document is subject to legal disclaimers.

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12. Contents
1
2
2.1
3
4

5
6
6.1
7
7.1
7.2
8
8.1
8.2
9
10
11
11.1
11.2
11.3
12

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Static (DC) operation . . . . . . . . . . . . . . . . . . . . . 3
Worked examples for static operation . . . . . . . 4
MOSFET mounting for good thermal
performance and power sharing . . . . . . . . . . . 7
Power sharing in dynamic operation[pulse and Pulse Width Modulation(PWM) circuits]. . . . . . . . . . . . . . . . . . . . . . . . . 10
Partially enhanced (linear mode) power
sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Gate drive considerations. . . . . . . . . . . . . . . . 12
Should individual gate drivers be used foreach MOSFET in the group? . . . . . . . . . . . . . 12
MOSFET packaging considerations forparalleled groups . . . . . . . . . . . . . . . . . . . . . . . 13
Bare die (KGD) MOSFETs . . . . . . . . . . . . . . . 13
LFPAK MOSFETs . . . . . . . . . . . . . . . . . . . . . . 13
Inductive energy dissipation in paralleled
MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Avalanching - low side MOSFET group drivinga high side inductive load . . . . . . . . . . . . . . . . 13
Active clamping - high side MOSFET groupdriving a low side inductive load . . . . . . . . . . . 14
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 16
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Please be aware that important notices concerning this document and the product(s)described herein, have been included in section ‘Legal information’.

© NXP Semiconductors N.V. 2015.

All rights reserved.

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 7 July 2015
Document identifier: AN11599