ARTICLE IN PRESS

Nuclear Instruments and Methods in Physics Research A 552 (2005) 292–328
www.elsevier.com/locate/nima

Design and performance of the ABCD3TA ASIC for readoutof silicon strip detectors in the ATLAS semiconductor tracker
F. Campabadala, C. Fletaa, M. Keya, M. Lozanoa, C. Martineza, G. Pellegrinia,
J.M. Raﬁa, M. Ullana, L.G. Johansenb, B. Mohnb, O. Oyeb, A.O. Solbergb,
B. Stugub, A. Ciocioc, R. Elyc, V. Fadeyevc, M. Gilchriesec, C. Haberc, J. Siegristc,
H. Spielerc, C. Vuc, P.J. Belld, D.G. Charltond, J.D. Dowelld, B.J. Gallopd,
R.J. Homerd, P. Jovanovicd, G. Mahoutd, T.J. McMahond, J.A. Wilsond,
A.J. Barre, J.R. Cartere, M.J. Goodricke, J.C. Hille, C.G. Lestere, M.A. Parkere,
D. Robinsone, F. Anghinolﬁf, E. Chesif, P. Jarronf, J. Kaplonf, A. Macphersonf,
H. Perneggerf, T. Pritchardf, S. Roef, A. Rudgef, P. Weilhammerf, W. Bialasg,
W. Dabrowskig,, M. Dwuznikg, B. Toczekg, S. Kopernyg, P. Bruckmanh,
S. Gadomskih, E. Gornickih, P. Maleckih, A. Moszczynskih, E. Staneckah,R. Szczygielh, M. Turalah, M. Wolterh, L. Feldi, C. Kettereri, J. Ludwigi,
J. Meinhardti, K. Rungei, A.G. Clarkj, M. Donegaj, M. D’Onofrioj, D. Ferrerej,
D. La Marraj, D. Macinaj, M. Mangin-Brinetj, B. Mikulecj, A. Zseneij,
R.L. Batesk, A. Cheplakovk, Y. Iwatal, T. Ohsugil, Y. Ikegamim, T. Kohrikim,
T. Kondom, S. Teradam, N. Ujiiem, Y. Unnom, R. Takashiman, P.P. Allporto,
A. Greenallo, J.N. Jacksono, T.J. Joneso, N.A. Smitho, G.A. Beckp, A.A. Carterp,
J. Morrisp, J. Morinp, V. Cindroq, G. Krambergerq, I. Mandićq, M. Mikužq,
I.P. Duerdothr, J.M. Fosterr, J. Paterr, S.W. Snowr, R.J. Thompsonr,
T.M. Atkinsons, B. Dicks, F. Faress, G.F. Moorheads, G.N. Taylors, L. Andricekt,
S. Bethket, D. Haufft, J. Kudlatyt, G. Lutzt, H.-G. Mosert, R. Nisiust, R. Richtert,
J. Schieckt, A-P. Colijnu, T. Cornelissenu, G.W. Gorﬁneu, F.G. Hartjesu,
N.P. Hesseyu, P. de Jongu, R. Kluitu, E. Koffemanu, A.J.M. Muijsu,
S.J.M. Peetersu, B. van Eijku, I. Nakanov, R. Tanakav, O. Dorholtw,
K.M. Danielsenw, T. Husew, H. Sandakerw, S. Stapnesw, N. Kundux,
R.B. Nickersonx, A. Weidbergx, J. Bohmy, M. Mikestikovay, J. Stastnyy,
Corresponding author. Tel.: +48 12 617 2959; fax: +48 12 634 0010

E-mail address: W.Dabrowski@ftj.agh.edu.pl (W. Dabrowski).
0168-9002/$ - see front matter r 2005 Elsevier B.V. All rights reserved.
doi:10.1016/j.nima.2005.07.002

ARTICLE IN PRESS
F. Campabadal et al. / Nuclear Instruments and Methods in Physics Research A 552 (2005) 292–328

293

Z. Broklovaz, J. Brozz, Z. Dolezalz, P. Kodysz, P. Kubikz, P. Reznicekz,
V. Vorobelz, I. Wilhelmz, P. Cermákaa, D. Chrenaa, T. Horazdovskýaa,
V. Linhartaa, S. Pospı́silaa, M. Sinoraa, M. Solaraa, B. Sopkoaa, I. Steklaa,
R.J. Apsimonab, L.E. Batchelorab, J.P. Bizzellab, N.G. Falconerab, M.J. Frenchab,
M.D. Gibsonab, S.J. Haywoodab, R.M. Matsonab, S.J. McMahonab,
M. Morrisseyab, W.J. Murrayab, P.W. Phillipsab, M. Tyndelab, E.G. Villaniab,
D.P. Cosgroveac, D.E. Dorfanac, A.A. Grilloac, S. Kachiguineac, F. Rosenbaumac,
H.F.-W. Sadrozinskiac, A. Seidenac, E. Spencerac, M. Wilderac, T. Akimotoad,
K. Haraad, K. Tanizakiad, N. Bingeforsae, R. Brennerae, T. Ekelofae, L. Eklundae,
J. Bernabeuaf, J.V. Civeraaf, M.J. Costaaf, J. Fusteraf, C. Garciaaf, J.E. GarciaNavarroaf, S. Gonzalez-Sevillaaf, C. Lacastaaf, G. Llosaaf, S. Marti-Garciaaf,
P. Modestoaf, F.J. Sanchezaf, L. Sospedraaf, M. VosafaInstituto de Microelectronica de Barcelona, IMB-CNM, CSIC, Barcelona, Spainb
University of Bergen, Bergen, NorwaycLawrence Berkeley Laboratory and University of California, Berkeley, CA, USAdSchool of Physics and Astronomy, The University of Birmingham, Birmingham, UKeCavendish Laboratory, Cambridge University, Cambridge, UKf
CERN, European Organization for Nuclear Research, Geneva, Switzerlandg
Faculty Physics and Applied Computer Science, AGH University Science Technology, Krakow, Polandh
The Henryk Niewodniczanski Institute of Nuclear Physics, Polish Academy of Sciences, Krakow, Polandi
Fakultat fur Physik, Albert-Ludwigs-Universitat, Freiburg, GermanyjSection de Physique, Université de Genève, Geneva, SwitzerlandkDepartment of Physics Astronomy, University of Glasgow, Glasgow, UKl
Department of Physics, Hiroshima University, Higashi-Hiroshima, Japanm
Institute of Particles and Nuclear Studies, KEK, Tsukuba, Japann
Kyoto University of Education, Fukakusa, Fushimi-ku, Japano
Department of Physics, Oliver Lodge Laboratory, University of Liverpool, Liverpool, UKp
Department of Physics, Queen Mary and Westfield College, University of London, London, UK
q
J. Stefan Institute and Department of Physics, University of Ljubljana, Ljubljana, SloveniarSchool of Physics and Astronomy, The University of Manchester, Manchester, UKsSchool of Physics, University of Melbourne, Parkville, Victoria 3010, Australiat
Max-Planck-Institut fur Physik, Munchen, Germanyu
NIKHEF, Amsterdam, The Netherlandsv
Physics Department, Okayama University, Okayama, Japanw
University of Oslo, Oslo, Norwayx
Department of Physics, Oxford University, Oxford, UKyAcademy of Sciences of the Czech Republic (ASCR), Prague, Czech RepubliczCharles University, Prague, Czech RepublicaaCzech Technical University, Prague, Czech Republicab
Rutherford Appleton Laboratory, Chilton, Didcot, UK
ac
Santa Cruz Institute for Particle Physics, University of California, Santa Cruz, CA, USAad
Institute of Physics, University of Tsukuba, Tsukuba, Japanae
Department of Radiation Sciences, Uppsala Universit, Uppsala, Sweden
afInstituto de Fisica Corpuscular (IFIC), Universidad de Valencia-CSIC, Valencia, Spain
Received 10 May 2005; received in revised form 4 July 2005; accepted 4 July 2005
Available online 25 July 2005

ARTICLE IN PRESS
294

F. Campabadal et al. / Nuclear Instruments and Methods in Physics Research A 552 (2005) 292–328

Abstract
The ABCD3TA is a 128-channel ASIC with binary architecture for the readout of silicon strip particle detectors in
the Semiconductor Tracker of the ATLAS experiment at the Large Hadron Collider (LHC). The chip comprises fast
front-end and amplitude discriminator circuits using bipolar devices, a binary pipeline for ﬁrst level trigger latency, asecond level derandomising buffer and data compression circuitry based on CMOS devices. It has been designed andfabricated in a BiCMOS radiation resistant process. Extensive testing of the ABCD3TA chips assembled into detector
modules show that the design meets the speciﬁcations and maintains the required performance after irradiation up to a
total ionising dose of 10 Mrad and a 1-MeV neutron equivalent ﬂuence of 2  1014 n/cm2, corresponding to 10 years ofoperation of the LHC at its design luminosity. Wafer screening and quality assurance procedures have been developedand implemented in large volume production to ensure that the chips assembled into modules meet the rigorous
acceptance criteria.
r 2005 Elsevier B.V. All rights reserved.
PACS: 29.40.Gx; 61.80. x; 61.82.Fk; 85.40. e; 85.40.Qx
Keywords: Front-end electronics; Binary readout; Silicon strip detectors; Tracking detectors; Radiation damage; Application speciﬁc
integrated circuits; Quality assurance

1. Introduction
The Semiconductor Tracker (SCT) together
with the Pixel Detector and the Transition Radiation Tracker (TRT) form the Inner Detector (ID)system in the ATLAS experiment being built for
the Large Hadron Collider (LHC) at the CERN
laboratory [1]. The SCT is built of double-sided
modules, each one consisting of two pairs of daisy
chained silicon strip sensors. The strips on the twosides are tilted by a small stereo angle of 40 Mrad,which provides the third space coordinate with amoderate resolution, i.e. z in the barrel part and r
in the endcap parts. In the barrel part the strips are
12.8-cm long with a constant pitch of 80 mm. In theendcap discs of the SCT there are ﬁve different
designs of the silicon strip sensor used. The
electrical parameters of the barrel and the endcap
sensors are very similar and the same front-end
electronics can be used for the sensor of each type.
Each module comprises 1536 strips to be readout by means of 12 128-channel front-end ASICs,
which are assembled into a hybrid circuit andattached to the sensor assembly. The complete
SCT detector will consist of 4088 silicon strip
detector modules comprising approximately 6.3
million readout channels.
There are two aspects that inﬂuence strongly thedesign of all components of the SCT, and of thefront-end ASIC in particular, namely the bunch
crossing frequency in the LHC of 40 MHz and therequired radiation resistance. The design speciﬁcations for the SCT front-end electronics, assuming
10-year operation of the LHC at the design
luminosity scenario, are: 10 Mrad of total ionisingdose and 2  1014 n/cm2 of 1-MeV neutron
equivalent ﬂuence, including 50% uncertainty.
The front-end ASIC must maintain the speciﬁed
performance parameters after irradiation up to theabove total ionising dose and 1-MeV equivalent
ﬂuence. In order to meet these requirements a
special radiation hard integrated circuit technology has to be used.
The moderate spatial resolution requirement of
the SCT can be achieved with strip pitch of 80 mm
and binary readout architecture that guarantees
resolution of 23 mm rms. The main advantage ofthe binary readout system is a drastic reduction ofdata to be read out as only addresses of channels
that have recorded hits above the threshold aretransmitted off the detector. For a big tracking
system like the SCT this is an important aspect
resulting in lower cost, a reduction of the material
required for the data transmission system, andsimpliﬁed off-detector readout electronics. On theother hand, in order to perform data sparsiﬁcationin the front-end electronics a very robust front-end
readout system is required. Besides the usual

ARTICLE IN PRESS
F. Campabadal et al. / Nuclear Instruments and Methods in Physics Research A 552 (2005) 292–328

requirements concerning noise, speed and power
dissipation, the channel-to-channel matching ofgain, and discriminator threshold become very
critical issues.
Another aspect, particularly important for thebinary readout architecture, is the immunity of theoverall system, and so of each component of thesystem, to external and internal interference,usually referred to as common mode noise. If
one takes into account irreducible noise sources
present in the front-end system, i.e. the paralleland series noise sources of the preampliﬁer and theshot noise of the detector leakage current, anachievable signal-to-noise ratio is about 15 at the
beginning of the experiment and about 10 after
irradiation of silicon strip detectors and front-end
electronics up to the levels as expected after 10
years of LHC operation. With these signal-to-noise
ratios there is very little room for setting thediscrimination threshold in such a way that thedetector is fully efﬁcient and the noise occupancy
is much lower than the physical data rate. Thus,
any degradation of the signal-to-noise ratio willlead to either a drastic reduction of efﬁciency or
increase of noise occupancy.
The ABCD3TA design is a single chip implementation of the binary readout architecture using
the DMILL technology—a radiation resistant
BiCMOS process comprising CMOS devices with
0.8 mm minimum gate length and bipolar devices
with the cut-off frequency of 5 GHz. The ﬁnal
design is an outcome of several prototyping steps.
The actual implementation of the required architecture and functionality depends strongly on theavailable technological options. At the beginningof the project a version based on two separate
chips: CAFE [2]—a front-end chip realised in the
MAXIM bipolar process and ABC [3]—a binary
pipeline chip realised in the Honeywell bulk
CMOS process, have been developed. The DMILL
process [4], which became available at a later stage,
permits combining all required functionality in asingle chip. The ABCD3TA design follows closely
the ﬁrst prototype developed in the DMILL
process, the SCT128B chip [5].
The ﬁrst ABCD prototype chip met most of therequirements, however, the spread of the discriminator threshold in the front-end exceeded the295

acceptable level. Analysis of the problem led us toa conclusion that given the matching parametersof the DMILL technology we could not achieve
the required performance following the original
circuit concept. Therefore, the design was upgraded and in the ABCD2T chip thresholdcorrection on a channel basis was implemented
by adding a 4-bit digital-to-analogue converter(TrimDAC) per channel [6,7]. Extensive radiation
testing performed for that prototype showed thatmatching performance degraded signiﬁcantly after
irradiation. In particular, after proton irradiation
up to the full ﬂuence the discriminator offset
spread exceeded the range of the TrimDAC.
Therefore, in the ﬁnal version ABCD3TA the
TrimDAC range adjustment was added to ensurethat the offset spread is covered even in the case ofa very large increase after irradiation, up to afactor of 5.

2. Requirements and speciﬁcation for the front-end
ASIC
2.1. Basic functionality
The ABCD3TA chip must provide all functions
required for processing signals from 128 strips of asilicon strip detector and transmitting data off thedetector module in the SCT. The basic functions
are the following: charge integration,
 pulse shaping, amplitude discrimination,
 latching data either in the edge sensing mode orin the level sensing mode, storage of data in the pipeline for the ﬁrst level(L1) trigger latency,

 derandomisation and compression of data, transmission of data from the chip via serial
daisy chained outputs.
The ABCD3TA is required to provide reportingof some of the errors that may occur:

 attempt to read out data from the chip when nodata is available,

ARTICLE IN PRESS
296

F. Campabadal et al. / Nuclear Instruments and Methods in Physics Research A 552 (2005) 292–328

 overﬂow of the derandomising buffer,
 derandomising buffer is no longer able to keep
track of the data held in it (chip reset required), conﬁguration error.
It is a system requirement that the fraction ofdata, which can be lost due to the readout buffer
on the chip overﬂowing, will remain less than 1%
for an occupancy up to 2% and an average trigger
rate of 100 kHz. This includes a large safety factor
as the expected worst case strip occupancy
averaged over strips and time is about 1%.
Furthermore, the chip shall incorporate featuresthat will enable the system to continue operating incase of a single chip failure.
In addition to the requirements concerning basic
functions related to receiving, storing and compressing the signals from the silicon strip detectors
the ABCD3TA chip must be equipped withfunctions that allow full testability at various stepsof module production, commissioning and running the experiment.
2.2. Parameters of silicon strip detectors
The SCT is built with single-sided AC coupled
p-on-n silicon strip detectors with polysilicon bias
resistors. The strip pitch is 80 mm and every strip isread out. A detailed description of the design andperformance of the sensors can be found elsewhere[8]. Here we recall only the electrical parametersthat are important for designing the front-end
electronics. It is worth noting that the speciﬁcations for the electronics and for the sensors havebeen elaborated as a common project so that theelectronics is optimised for this particular detector
design and the design of the strip detectors is
optimised for the binary readout scheme.
The electrical parameters of the SCT silicon
strip detectors are listed in Table 1.
2.3. Front-end basic requirements
Parameters and characteristics of the front-end
circuit are driven mainly by the parameters ofsilicon strip detectors used in the SCT, inparticular by the total strip capacitance and by
the LHC machine beam crossing rate of 40 MHz.
The noise performance is driven by the requirements regarding detection efﬁciency and noise
occupancy. In order to ensure that detection
efﬁciency is above 99% for each individual
module, taking into account the Landau distribution of the charge generated in silicon strip
detectors, smearing of charge by the magnetic
ﬁeld and charge division due to diffusion, thesignals from the silicon strips must be discriminated at a level corresponding to 1 fC. On theother hand, the noise occupancy is required to be
kept below 5  10 4. Combination of these twoconstraints leads to a requirement on the maximum Equivalent Noise Charge (ENC) of 1500
electrons rms for the nominal parameters of thesilicon strip detectors and of the ASICs as
measured on a fully populated unirradiatedmodule. Degradation of the ENC is expectedduring the lifetime of the experiment due tounavoidable radiation damage to the silicon strip

Table 1
Assumed detector electrical parameters

Coupling type to ampliﬁer
Coupling capacitance to amp
Total for 12 cm strips
Capacitance of strip to all neighbour strips
Capacitance of strip to backplane
Metal strip resistance
Bias Resistor
Max leakage current per strip for shot noise
Charge collection time

UnirradiatedIrradiatedAC
20 pF/cm
240 pF1.03 pF/cm
0.30 pF/cm
15 O/cm
0.75 MO2.0 nAo10 nsAC
20 pF/cm
240 pF1.40 pF/cm
0.30 pF/cm
15 O/cm
0.75 MO
2.0 mAo10 nsARTICLE IN PRESS
F. Campabadal et al. / Nuclear Instruments and Methods in Physics Research A 552 (2005) 292–328

detectors as well as to the readout ASICs. After
receiving nominal SCT ﬂuence the ENC of atypical module is required to stay below 1800
electrons rms.
Since the discrimination threshold is common
for all 128 channels in one chip, the above
requirements translate into a requirement concerning the channel-to-channel spread of threshold. The threshold variation in one ABCD3TA
chip must be much lower, by a factor of at least 5,
than the signal ﬂuctuations due to noise in order toensure that the channel-to-channel thresholdvariation will not affect signiﬁcantly the detection
efﬁciency and the noise occupancy.
Regarding the timing performance, there is abasic requirement that each signal recorded in thesilicon detectors is uniquely associated with thebeam crossing from which it originated. Thistranslates into a requirement that the timewalk
be less than 16 ns allowing some margins for time
jitter of the discriminator response and of theclock signals. The timewalk is deﬁned as the
maximum time variation in the output signal of
the comparator over an input signal range of
1.25–10 fC, with the comparator threshold set to
1 fC. Associated with this is a requirement on
double pulse resolution to be less than 50 ns for a
3.5 fC signal followed by another 3.5 fC signal.
Note that we allow for pile-up of signals corresponding to two consecutive beam collisions, i.e.
separated by 25 ns. Due to ﬁnite charge collection
time in the silicon strip detectors and requirementson the noise it is impossible to shape the signals in
the front-end circuit with the peaking time much
shorter than 25 ns, which would be required toobtain double pulse resolution of 25 ns. On theother hand probability of ﬁnding the signals in thesame channel for two consecutive beam collisions
is low given the expected worst case strip
occupancy in the SCT detectors of about 1%.
2.4. Data compression and readout
The data from silicon strip detectors has to be
kept in the front-end chips for a time period
corresponding to the ATLAS L1 trigger latency. A
L1 trigger latency of 3.3 ms is assumed, including
some margins for unknown ﬁbre lengths, which297

requires a 132 cells deep pipeline clocked at
40 MHz. If the data corresponding to a given
beam collision arrives at the end of the pipeline at
the same time as the L1 trigger signal the data
corresponding to three beam collisions, the given
one, one before and one after, are stamped as valid
and transferred to the derandomising buffer.
Otherwise the data is considered as non-valid
and is discarded at this point. This is a ﬁrst step atreducing the amount of data to be transmitted off
the detector. In the second step, only the addressesof channels with valid hits are encoded andtransmitted off the detector. For an occupancy
of 1%, i.e. hits in 1–2 channels of each chip, thisprovides another level of data compression. The
third step is that the data is encoded such that only
one address is transmitted for clusters of adjacent
hit channels since pairs of hit channels are quite
common.
The L1 trigger is generated with a Poissonian
distribution in time at a mean rate of 100 kHz forthe accelerator working at the nominal design
luminosity. In order to keep the number of opticallinks for transmission as low as possible it isrequired that the maximum data rate transmitted
off the detector corresponds to the average trigger
rate and not the peak value of the trigger rate. In
order to allow for such a solution the data has tobe derandomised in the front-end chip. It is
required that the derandomising buffer is eight
events deep, which was found by Monte Carlosimulation to guarantee that less than 1% of thedata will be lost due to overﬂow in the derandomising buffers.
The SCT modules are designed to be read out
via two optical links each, i.e. the data from six
ABCD3TA chips have to be multiplexed androuted serially into one link. The transmission rateof 40 Mbit/s will be sufﬁcient with a factor of 2
safety margin assuming the occupancy of thesilicon strip detectors of 1% and the L1 trigger
rate of 100 kHz. Note that there is no additional
readout IC on the module to take care oforganising and transmitting the data off thedetector. Such an extra readout IC would require
additional space on the modules and add material
in the tracker volume. Instead the readout control
has to be integrated in the ABCD3TA chips. The

ARTICLE IN PRESS
298

F. Campabadal et al. / Nuclear Instruments and Methods in Physics Research A 552 (2005) 292–328

compressed data are routed via a token ring for six
chips daisy chained on each side of the module.
2.5. System reliability
The SCT will operate within the large ATLAS
detector. Any maintenance of the SCT will require
removing several of the outer sections of the other
ATLAS components, a task requiring more than 1month. Therefore, maintenance opportunities are
expected to be at most once per year. For thisreason, the electronics is designed for highreliability and low maintenance. Minimising system complexity improves reliability by reducing
the number of components that can fail, which
also improves the detector performance by minimising material in the detector volume. Providing
redundancy where possible minimises the effects ofsingle point failures.
Each SCT module processes data from 1536
channels. In order to maximise system reliability,
several design features are employed to minimise
the chance for the loss of a total module in theevent of single device or single component failure.
One is the choice of a serial data path rather than aparallel data bus. The failure of a single driver on aparallel bus can disable the entire bus thus making
the entire module non-functional. The failure of adriver in a serial daisy chain will only break one
link. To prevent the breakage of one link fromdisabling the entire chain, each ABCD3TA chip isrequired to have an alternate data path, which willbypass the non-functioning chip. In case of failureof one of the two optical links, the data from bothsides of the module should be routed through thesingle functioning link.
To facilitate the serial data ﬂow without the useof a separate readout IC, a data format wasdeﬁned which allows a variable data length packet
per L1 trigger but does not require the length to be
speciﬁed at the beginning of the packet. Such alength ﬁeld at the beginning of the packet requires
extra data buffering to hold the data while thelength is determined. Instead, the data format
makes use of a trailer ﬁeld, which is a uniquepattern to denote the end of the packet.
In addition to a small number of single purpose
control lines, the ABCD3TA is controlled via

commands sent to one of the two serial command
inputs. To minimise system complexity, the L1
trigger commands as well as other calibration andconﬁguration commands are received via the same
serial input. To accomplish this, a hierarchicalcommand protocol is deﬁned which allows frequent
L1 triggers to be distinguished from longer, infrequently used commands without incurring any
trigger deadtime. A 3-bit code identiﬁes either an
L1 trigger or some other command. The 3-bit codetakes 3 clock cycles to be transmitted, which is theshortest time window allowed for consecutive L1
triggers by the ATLAS experiment, i.e. no morethan 1 trigger every 75 ns. If the 3-bit code identiﬁes
a non-L1-trigger command, then a longer command
string is assumed and some deadtime is assumed.
The longer control commands are further divided
into ‘‘Fast Control Commands’’ requiring a ﬁxed 4bit code length and ‘‘Slow Control Commands’’ ofarbitrary variable length. The fast commands
include those, which require synchronisation witha speciﬁc clock sequence. The slow commands areintended for loading conﬁguration registers. Care istaken in choosing the speciﬁc 3-bit and 4-bit
patterns for these command codes to require morethan a single bit ﬂip to cause misidentiﬁcation of acommand. Rather, a single bit ﬂip creates an invalid
command, which is ignored.
Another design feature to enhance reliability is
the requirement of two clock inputs and two
command inputs. One control line, by maintaining
either a high or low state, is used to specify
whether the chip should use the normal clock andcommand inputs or the alternate two inputs. This
allows the chip to continue to operate even if oneof the clock or command lines, provided via
optical links in the SCT system, fails during thelife of the experiment.
2.6. Testability
Particular requirements regard testability of the
ABCD3TA chip. Given very large numbers ofchips that are needed for construction of the SCT
detector it is important that all the components
used are fully tested before being assembled into
detector modules. This aspect is particularly
important for the ABCD3TA chips as eachARTICLE IN PRESS
F. Campabadal et al. / Nuclear Instruments and Methods in Physics Research A 552 (2005) 292–328

module comprises 12 of them and failure of one
chip or a large number of defective channels foundafter module assembly will disqualify the module
resulting in loss of other expensive components,
silicon sensors and hybrids. Therefore, theABCD3TA chips have to undergo very rigorous
quality assurance tests, which can be implemented
effectively provided that sufﬁcient testability functions are built in the ABCD3TA design. However,signiﬁcant amount of chip area cannot be devoted
to special testability functions since space andallowed material on the detector module isextremely limited. Extra test time is accepted
rather than adding extra test circuits, which would
reduce test time.
Full electrical functionality tests and measurements of all important analogue parameters of thefront-end have to be performed at the following
steps: (1) wafer testing, (2) testing after assembly ofchips on hybrids, (3) hybrid testing after burn-in, (4)testing of complete modules after assembly withsilicon sensors. These tests have to provide data forcalibration of the discriminator threshold scale withrespect to the input charge as well as for offset
corrections in the discriminators. In order to enablemeasurements of analogue parameters the front-end
has to be equipped with circuitry that can inject
charge signals into the preampliﬁer inputs, which
are equivalent to the physical signals from thesilicon strip detectors. The amplitude and the delayof the calibration signal with respect to the phase of
the master clock has to be adjusted via the control
logic. Furthermore, since in the binary readout
architecture the basic analogue parameters are
extracted from the discriminator threshold scans
and the delay scans of the calibration signals, thesescans have to be managed via the control logic.
The functionality and parameters of the digitalpart of the chip have to be tested by supplying test
vectors to the inputs of the digital part of chip.
These test vectors have to be delivered via thecontrol logic.

binary readout architecture, the front-end circuitry, discriminators, binary pipeline, derandomisingbuffer, data compression logic and the readout
control logic.
The preampliﬁer-shaper circuit delivers signals
with peaking time of 25 ns. This peaking time is
sufﬁcient for keeping the discriminator timewalkwithin the range of 16 ns and the double pulse
resolution below 50 ns. It also provides a reasonable optimum for relative contributions of theseries and parallel noise sources, given total strip
capacitance in a range 15–20 pF. The preampliﬁershaper circuit is followed by a discriminator with acommon threshold for all 128 channels, which iscontrolled by an internal 8-bit DAC. In the
ABCD3TA design, in addition to the threshold
control common for all channels we have implemented individual threshold correction per
channel using a 4-bit DAC (TrimDAC). The
TrimDACs are used only for correction of thethreshold offsets and are kept at ﬁxed settings
whereas the common threshold is adjusted to therequired value. Similarly, the threshold scans
which are used for extracting the basic analogue
parameters of the front-end circuit are performed
employing only the main 8-bit DAC common for
all channels in the chip.
The binary data from the discriminator output
are latched in the input register either in the edge
sensing mode or with the level sensing mode with atime resolution of 25 ns and clocked into a 132-cell

3. Overview of the ABCD3TA design
The block diagram of the ABCD3TA chip isshown in Fig. 1. It comprises all blocks of the299

Fig. 1. Block diagram of the ABCD3TA chip.

ARTICLE IN PRESS
300

F. Campabadal et al. / Nuclear Instruments and Methods in Physics Research A 552 (2005) 292–328

pipeline. The edge sensing mode puts a more
rigorous constraint on the timing performancecompared to the level sensing but minimises therate of data to be transmitted off the detector.
Upon receiving a trigger signal the data aretransferred from the pipeline to the second levelbuffer, which is a dual-port static RAM array 128bits wide and 24-words deep. For each L1 trigger
signal three columns from the pipeline are stored
in this derandomising buffer, so that the buffer iseffectively eight events deep. It compensates forrate ﬂuctuations of the L1 trigger. The hit patterns
from three consecutive bunch crossings corresponding to each L1 trigger signal are held in thebuffer pending readout. The data is then compressed in the data compression logic according to
one of four possible criteria (hit mode, levelmode, edge mode, test mode) and read out via atoken ring daisy chaining six chips into one
optical ﬁbre.
In addition to the basic functional blocks
mentioned above, the ABCD3TA chip comprises
calibration circuitry for internal generation ofcalibration pulses. The amplitudes of calibration
pulses are set by an 8-bit DAC and the delay ofcalibration pulses relative to clock phase iscontrolled by a delay buffer of 5-bit resolution.
The chip has been designed to work with two
power supply voltages: 3.5 V for the analogue
part and 4.0 V for the digital part, although
the nominal power supply voltage for the DMILL
technology used is 5 V. A requirement to reduce
the power supply voltages was driven by theconstraint on the power consumption. The
measured power consumption per chip is
260 mW for the analogue section and 140 mW
for the digital section at a clock frequency of
40 MHz, resulting in an average power less than
3 mW/channel.
The die area of the ABCD3TA chip is equal to6550  8400 mm2. The front-end part is built
mainly of bipolar devices and comprises about
30,000 components, while the digital part comprises about 200,000 CMOS devices. The pitch of
the input pads is 50 mm so that a pitch adapter isneeded to match the detector strip pitch of 80 mm.
The layout drawing of the ABCD3TA chip isshown in Fig. 2.

Fig. 2. Layout drawing of the ABCD3TA chip.

3.1. Front-end
The binary front-end circuit comprises thepreampliﬁer, shaper and the discriminator. The
diagram of the circuit implemented in the
ABCD3TA chip is shown in Fig. 3. The preampliﬁer is based on a transimpedance conﬁguration using a bipolar transistor with emitter area of(1.2  10) mm2 as the input device. For a bipolar
input transistor the dominant noise source, i.e. theequivalent voltage noise, depends, in the ﬁrst
approximation, on the value of the collector
current and is independent of the transistor size.
The size of the input transistor has been optimised
taking into account two other effects, namely theseries noise contribution from the base spread
resistance and the parallel shot noise of the basecurrent. The latter one increases after irradiation
due to a decrease of the current gain factor bU
In order to optimise the size of the input
transistor radiation effects in DMILL, bipolartransistors of various emitter areas have beenstudied [9]. Similar behaviour of b as observed forother bipolar technologies has been found, i.e. thedegradation of b due to radiation effects scaleswith the collector current density. Therefore, inorder to minimise the effect of radiation on the bfactor for a given collector current, the minimum
geometry input transistor would be preferable,
however, noise of the base spread resistance would
be too high for such a transistor. For the chosen

ARTICLE IN PRESS
F. Campabadal et al. / Nuclear Instruments and Methods in Physics Research A 552 (2005) 292–328

301

Fig. 3. Schematic diagram of the front-end circuitry implemented in the ABCD3TA chip.

geometry the base spread resistance is relatively
low, of the order 100 O, and b is expected to be notless than 40 after irradiation up to a total dose of
10 Mrad and an equivalent neutron ﬂuence of2  1014 n/cm2, as expected for the SCT detector.
The input stage is followed by a single-ended
voltage ampliﬁer built of two gain stages closedwith a resistive feedback loop, which determines
the gain. This stage introduces a pole in thepreampliﬁer transfer function that is responsible
for the integration time constant. Following thegain stage there is an ac coupled differential stage
converting the single-ended signal into a differential one, which is then applied to the discriminator. Although the ac coupling is not an ideal
solution as it may lead to a shift of the baseline forhigh rate of pulses, this conﬁguration is driven by
the critical aspect of the binary readout architecture, i.e. matching of the gain, noise and dc levels
at the shaper output since a common threshold forall 128 channels in the chip is applied. The
required uniformity is obtained by (i) suppressing
the dc gain by ac coupling between the ampliﬁer
and the discriminator, (ii) sufﬁciently high gain in

the preampliﬁer-shaper circuit, of the order of
50 mV/fC, and (iii) a differential scheme for setting
the discriminator threshold. Both stages following
the preampliﬁer, i.e. the single-ended stage and thedifferential one, provide additional poles so thatthe overall shaping function of the circuit isequivalent to a CR-(RC)3 ﬁlter with a peaking
time of about 20 ns. The peaking time becomescloser to 25 ns if one takes into account the chargecollection time in silicon strip detectors, which isabout 10 ns for the bias voltage above 300 V, as
foreseen to be applied in the SCT detectors.
3.1.1. Discriminator
The discriminator is designed as a differential
comparator in the Schmitt trigger conﬁguration
with capacitive positive feedback. The thresholdvoltage as well as the input signal are applieddifferentially. In this simple solution the timewalk,
an important parameter, is determined directly by
the rise time of the signal at the shaper output. The
requirement concerning the timewalk suits well tothe requirement concerning the shaper peaking
time which is driven by the three other issues: (i)ARTICLE IN PRESS302

F. Campabadal et al. / Nuclear Instruments and Methods in Physics Research A 552 (2005) 292–328

relative contribution from the parallel noise andthe series noise sources, (ii) ballistic deﬁcit, and (iii)
double pulse resolution. For the SCT detector it isrequired that, for the nominal threshold setting
corresponding to an input charge of 1 fC, thetimewalk is below 16 ns for an input signal range
from 1.25 to 10 fC.
The discriminator threshold is controlled by thedifferential voltage applied to the discriminatorinputs via the differential ampliﬁer preceding thediscriminator. Scanning of the threshold is a main
tool for measuring the analogue parameters.
Therefore, the threshold voltage that iscommon for all 128 channels in the chip isgenerated by an internal DAC with 8-bit resolution, which is set via the control logic. The
threshold setting covers a range from 0 to
640 mV with steps of 2.5 mV, which for thenominal gain of the front-end circuit of 50 mV/
fC corresponds to the range of input signals from 0
to 12.8 fC with a step size of 0.05 fC.
In this conﬁguration with a common thresholdvoltage for all 128 channels the actual thresholdfor each individual channel depends on thediscriminator offset as well as on the gain in thefront-end circuit for that particular channel. The
discriminator offset is determined only by theoffset and gain of the differential pair preceding
the discriminator. Initially it was assumed that therequired uniformity of the discriminator threshold
could be achieved by proper sizing of the devices
that contribute the offset in each channel, i.e. thetransistors and resistors in the differential pairpreceding the Schmitt trigger and the transistors of
the Schmitt trigger. Both stages are based on
bipolar devices, for which adequate matching of
the Vbe voltages was expected. Good matching of
the Vbe was conﬁrmed in the ﬁrst prototype,however, at the same time it was found thatmatching of the resistors was much worse compared to the expected values. As a result thethreshold spread was determined mostly bymatching of the resistors used as the load devicesof the differential ampliﬁer.
Furthermore, irradiation tests showed that thematching of those resistors degraded signiﬁcantly
after irradiation with charged particles, by a factor
of about 4.

Thus, in order to guarantee the required
uniformity in the ﬁnal ABCD3TA version, thethreshold correction on a channel basis has been
introduced. In each channel there is a 4-bit DAC,
named TrimDAC, which is used to compensate thethreshold offset. In addition, the range of the
TrimDAC can be set by two additional bits. For agiven step of the TrimDAC the expected rms valueof the threshold spread is step/O12. The TrimDAC ranges, corresponding steps and expected
relative spreads of the threshold for the nominal
setting of 50 mV, corresponding to an input chargeof 1 fC, are summarised in Table 2. The minimum
range (range 0) covers the expected thresholdspread at the beginning of the experiment before
signiﬁcant radiation damage occurs. With accumulated radiation damage the offset spread in thediscriminator will increase so it will require alarger range to make sure that all the channels canbe trimmed. Of course, the resulting spread of thethreshold will be higher for higher ranges used,however, the signal-to-noise ratio will also decrease. In order to introduce a safety margin forpossible unexpected effects that can occur in theexperiment, the maximum range has been chosen
to be a factor of 2 higher compared to the worst
case offset spread measured after proton irradiation up to the nominal ﬂuence of 3  1014 p/cm2(see section on radiation effects).
The discriminator output current is converted
into a full swing signal in the output inverter. The
stage of the Schmitt trigger and the output inverter
is supplied from the digital power supply so that
one avoids large voltage swings in the front-end
part connected to the analogue power supply. For
the positive current signal from p-on-n silicon strip
Table 2
Trim DAC range selection
TrimDAC range(mV)

TrimDAC
step (mV)

Relative threshold spreadfor the nominal thresholdsetting of 50 mV (1 fC)(1s) (%)

0–60
0–120
0–180
0–240

4
8
12
16

2.3
4.6
6.9
9.2

ARTICLE IN PRESS
F. Campabadal et al. / Nuclear Instruments and Methods in Physics Research A 552 (2005) 292–328

detectors the output inverter is HIGH when there
is no signal and is switched to LOW in response toa signal.
3.1.2. Calibration circuit
Each channel has an internal calibration capacitor of 100 fF connected to its input allowing
injection of test charges. The voltage step pulses
are generated by an internal chopper circuit, which
is triggered by a command. Every fourth channel
can be tested simultaneously with group selection
determined by a 2-bit binary coded calibration
address. The strobe and the address signals aredelivered from the control circuitry. The amplitudeof the voltage steps applied to the calibration
capacitors by the chopper is determined by aresistor and the current that is controlled by aninternal 8-bit digital-to-analogue converter (calibration DAC). The amplitude of the calibration
pulse can be set within a range from 0 to 160 mV
with 8-bit resolution, i.e. 0.625 mV/step. For thecalibration capacitor of 100 fF the charge range
and the resolution is 16 and 0.0625 fC/step,
respectively.
The duration of the strobe signal is ﬁxed andequal to 200 ns whereas the delay with respect tothe clock phase is controlled by a delay registerand can be tuned within a range of 50 ns with 5-bit
resolution, i.e. 1.56 ns/step. Since the delay circuit
is realised as a series of inverters, in order tominimise circuit complexity, the overall delay is
directly dependent on the process variation and,
therefore, has to be cross-calibrated using theexternal clock signal. It is therefore required thatin an extreme case of process variation the overall
delay covers at least one clock period of 25 ns,
which is the basic requirement for full characterisation.
The four calibration bus lines, each one
connecting the calibration capacitors of every
fourth channel, are also brought out to pads thatcan be directly driven from an external signal
generator. These pads are foreseen for crosschecking of the internal calibration circuitry andare not used on the detector modules. The featuresof the internal calibration circuit enable to test andcalibrate the ASICs either at the wafer level
or in situ.

303

3.2. Data buffering
The binary data produced at the discriminatoroutput has to be latched synchronously with theclock and then buffered on the chip until the chipreceives a L1 trigger. Latching and buffering thedata is performed in three blocks: input register,
pipeline and derandomising buffer.
3.2.1. Input register
A simpliﬁed schematic diagram of single channel of the input register is shown in Fig. 4. It
comprises three blocks: edge detecting circuit,masking logic and mask register cell. The input
register latches the incoming data, delivering to thepipeline a pulse of well-deﬁned width. In the basicmode of operation the data is latched in edge
sensing mode. The circuit detects a HIGH to LOWtransition in the discriminator output signal and,for each such transition found, the circuit generates a pulse of duration equal to one clock cycle
irrespective of the length of the incoming pulse.
The effect of this block is that only a single ‘‘1’’ iswritten into the pipeline for every hit detected
regardless of the response time of the discriminator. This circuitry can be turned on or off by
setting the appropriate bit in the conﬁguration
register. If the edge sensing function is turned off
the data is latched in the level mode, in which a

Fig. 4. Schematic diagram of the input register.

ARTICLE IN PRESS
304

F. Campabadal et al. / Nuclear Instruments and Methods in Physics Research A 552 (2005) 292–328‘‘1’’ is produced for each coincidence of the lowlevel at the discriminator output and the risingedge of the clock signal. For discriminator outputs
longer than one clock period the circuit produces
multiple responses written into the pipeline.
A trade-off between the edge sensing and thelevel sensing modes is the efﬁciency vs. readout
occupancy. An important parameter of the detector module is the in-time efﬁciency deﬁned as theprobability for a hit to be correctly associated witha given LHC beam crossing. In the level sensing
mode one can avoid in-time inefﬁciency, however,
the occupancy of readout channels is substantiallyhigher compared to the hit occupancy. Since formost of the hits the response of the discriminator
will be longer than 25 ns the average rate of data
written into the pipeline in the level sensing mode
will be about a factor of 2 higher than the rate ofdata at the discriminator output. In the edge
sensing mode the occupancy in the readout
channels is the same as the hit occupancy but thein-time efﬁciency becomes a critical parameter.
A part of the input register is the mask register,which serves a dual purpose. Firstly, the channelmask register can be used to turn off any bad or
noisy channel thus preventing increase of data rate
due to false hits. Secondly, it can be used for chip
testing to apply a set of test patterns to the pipeline
input. The contents of this register can be changed
by sending the appropriate control command tothe chip. In the test mode the digital part of the
ASIC, from the input register up to the output, canbe tested separately without using the signals fromthe front-end.
3.2.2. Pipeline
The binary pipeline is realised as a multiplexed
FIFO circuit. The operational principle of a single
pipeline channel is shown schematically in Fig. 5.
An array of m  n memory cells is controlled by m
non-overlapping clock signals. The input data in asingle channel is multiplexed into m rows. In eachclock cycle only one cell per row is switched. Afterm  (n 1) clock cycles the data is shifted to theend of the row and de-multiplexed to the output.
As a result only m out of m  n cells are switchedin each clock cycle while the effective delay
provided by such a block is equal to m  (n 1)clock cycles which is equivalent to m  (n 1)memory cells. In our case each pipeline channel
is built of a memory block of 12  12 cells resulting
in an effective depth of 132 cells since for eachclock cycle the data is copied from one column tothe following one. This way the data corresponding to a given time bin is always stored in two
adjacent columns.
The basic memory cell shown in Fig. 5b isrealised as a semi-static circuit. A particularfeature of this circuit is provided by the feedback
transistor, which maintains the output state
independently of leakage in the pass transistor
and threshold voltage shifts in the inverter, which
may appear after irradiation. In Fig. 5c the
structure of the output demultiplexing cell isshown.
The applied architecture results in two additional very valuable features: low power consumption and a very compact layout, which isparticularly important as the circuit is implemented in a 0.8 mm CMOS process of relatively low
density. The pipeline block of 128 channels,
each 132 bits deep, occupies an area of 9 mm2
only. The expected power consumption for thisblock is of the order of 140 mW/channel at a clock
frequency of 40 MHz and does not depend on thedata rate.
3.2.3. Derandomising readout buffer
The ABCD3TA chip contains a second level
readout buffer, which is realised as a dual port
static RAM array, 128 bits wide by 24 bits deep,
allowing simultaneous write and read operations.
Three bits of data are stored in this buffer for eachchannel per L1 trigger. These bits represent thethree beam crossings centred on the L1 trigger
time and are set if the input was above threshold
during the corresponding crossings. The task ofthis buffer is to remove the time ﬂuctuations fromthe L1 trigger distribution. The hit patterns
corresponding to each L1 trigger are stored in
the second level buffer pending a readout strobe.
Up to 8 events can be stored in the readout buffer,
which assures that the dead time will be less than
1% at the maximum ﬁrst level trigger rate of
100 kHz, provided that the strip occupancy is lessthan 2%.

ARTICLE IN PRESS
F. Campabadal et al. / Nuclear Instruments and Methods in Physics Research A 552 (2005) 292–328

Fig. 5. (a) Array of 12  12 memory cells, (b) structure of the storage cell, (c) structure of the output demultiplexing cell.

305

ARTICLE IN PRESS
306

F. Campabadal et al. / Nuclear Instruments and Methods in Physics Research A 552 (2005) 292–328

Fig. 6. Block diagram of the readout buffer.

A block diagram of the readout buffer is shownin Fig. 6. The RAM block is addressed by two
cycling pointers, a write pointer and a readpointer. Once the pointer has reached the end of
the RAM, it returns to the beginning the next time
it is incremented. The write pointer is allowed togo past the read pointer and over-write data thathas not yet been read out. However, if thishappens the Overﬂow ﬂag is set to indicate thatdata has been over-written. The read pointer is notallowed to pass the write pointer and if the readpointer should catch up with the write pointer the
Empty ﬂag is set. This is to prevent attempts toreadout the buffer when there is no data in it.
An overﬂow counter is used to track the numberof events that have been overwritten in the buffer.
This counter is incremented every time an event iswritten into the buffer while the buffer is full. The
output from this counter represents the number of
events from which data has been lost. This counteris decremented every event that is readout of thebuffer, until its value reaches zero. In this state, all
the events from which data have been lost arecleared and none of the data in the buffer
represents overwritten events. Should this counter
overﬂow, the Error ﬂag is set and it remains set
until either a software reset or a power-up reset has
been issued to the readout buffer and associatedlogic.
3.2.4. Data compression
Given the foreseen worst case strip occupancy of
1% on any event, very few channels will containhits. Therefore, compressing of data will result in asigniﬁcant reduction of the number of bits of datathat have to be read out of the chip for each event.

The data compression logic works by examining inturn the 3 bits of data that make up the hit pattern
for each channel. Each group of 3 bits is comparedagainst one of the four selectable criteria. If thepattern meets the criteria, then the hit pattern fromthat channel is sent to the readout circuitry fortransmission, if not, no data is sent from thatchannel and the hit pattern from the next channel
is examined. This process is repeated until the hit
patterns from all 128 channels have been examined. Table 3 shows the four selection criteria.
The data compression circuit operates as follows. After receiving an L1 trigger the three 128bit words that constitute an event are written into
the readout buffer. The ﬂag on the readout buffer
is set, indicating that there is data to be processed.
The data compression logic monitors the state ofthis ﬂag until it ﬁnds that there is data available.
Providing that the circuit is not already processing
data, it then proceeds to read in the three 128-bit
words that constitute an event from the readout
buffer. In the next step, the data compression logic
rearranges the order of the data from being three128-bit words into 128 3-bit words because thedata compression algorithm requires all threesamples of an event to be examined in parallel.
The data compression logic then starts to scanthrough all the channels in turn until it ﬁnds one,which has a pattern of hits that matches the chosendata selection criteria. If it ﬁnds such a pattern of
hits, it validates the data and attaches the 7-bit
channel address to the hit pattern. The logic thenwaits until the readout logic signals it to proceedby asserting the next input. If the next hit found ison the next adjacent channel, the ADJ bit isasserted with the data from the previous channel.
If no more hits are found, the END signal isasserted.
Table 3
Data compression criteria
Name ofHit patternselection criteria

Usage

Hit
Level
Edge
Test

Detector alignment
Normal data taking
Normal data taking
Test mode

1XX or X1X or XX1
X1X
01X
XXX

ARTICLE IN PRESS
F. Campabadal et al. / Nuclear Instruments and Methods in Physics Research A 552 (2005) 292–328

3.3. Data readout
The SCT module has 12 ABCD3TA chips, six
on each side. The compressed data is read out
from six chips via a token ring daisy chaining thechips on each side. The chips can be conﬁgured asa Master (M), Slave (S) or End (E) chip. On eachside the chips are conﬁgured as follows: one
Master, four Slaves and one End. The interconnections between the chips on the module areshown in Fig. 7. The black lines show the primaryconnections and grey lines show the redundantconnections. Each chip has a pair of token anddata inputs/outputs, normal (N) and redundant(B) used for bypass connections. The data outputof the Master chip is connected to the optical ﬁbre
interface.
After reception of an L1 Trigger, the Masterchip initiates a readout cycle by sending thepreamble bits at the start of each data block to
the optical link driver. It then appends its data bits
to the output stream sent to the optical link driver.
Once the last bit of data has been sent, the Masterchip sends a token to the Slave chip on its right.
The Slave chip on the right responds by sending its
data packet to the Master, which in turn isappended to the preamble and data bits from the
Master already sent to the optical link driver. Once

307

this Slave chip has ﬁnished sending its data, it also
passes on the token to the next chip on the right.
The next chip on the right passes its data onto theprevious chip on the left, which in turn passes itback to the Master chip for transmission to thelink driver. This process continues until the lastchip in the chain has sent its data. A bit is set in the
End chip in the chain to deﬁne it as the last chip.
When this chip has sent its data it appends a trailer
to the end of the data stream. While the Masterchip is outputting data, it is constantly looking forthe trailer pattern that has been carefully chosen to
be distinct from the data. Once it ﬁnds the trailer
pattern, it knows that all the data from the event
has been sent and it can start processing the next
event.
In the event of the failure of one of the Slave
chips, the previous and next chips in the chain areprogrammed to route their data and tokens
around the failed chip using the redundantconnection on the hybrids. If the End chip in the
chain should fail, then the last Slave chip in the
chain is programmed to perform the operation of
the End chip. In the event of the failure of a
Master chip in the chain, the data and tokens fromthe chain with the failed Master chip are routed to
the working Master chip on the other side of thehybrid.

Fig. 7. Interconnection of ABCD3TA chips on a 12-chip detector module.

ARTICLE IN PRESS
308

F. Campabadal et al. / Nuclear Instruments and Methods in Physics Research A 552 (2005) 292–328

3.3.1. Readout circuitry
The readout control circuitry is responsible for
capture and release of the token and outputting
data from the chip. The readout circuit always
waits until the token arrives. On arrival of thetoken, it checks if any hits have been found by thedata compression logic. If so, it then outputs theappropriate header pattern, the address of the hitchannel together with the data from that channel.
Once the readout circuitry has ﬁnished sending thedata from one channel, it proceeds to output thedata from the next channel. In the situation where
one or more neighbouring channels are to be readout, only the address of the ﬁrst channel is output,
but the data from all hit channels is sent. This
process continues until the data compression logic
indicates that all channels have been examined byasserting the End code. Once all the data
corresponding to a single event has been readout, a token is sent out to the next chip in thereadout chain. If the chip has no data to be readout, circuitry sends out the No-Hit-Data code andpasses the token on to the next chip in the chain.
In the case of an error condition occurring, e.g.
attempt to readout data while no data available,
the appropriate error code is sent by the readout
logic. If the chip is in the Send-Id mode ofoperation, no data or error codes are output fromthe chip but instead a special packet of datacontaining information about the chip’s current
conﬁguration is sent.
The building blocks of the readout circuitry are:

 Readout Controller Block—this block is enabledby placing the chip in the Master mode and has
to detect L1 trigger, issue a token, collect all thedata from the chips and tag the data with thebeam crossing number from which it came andthe number of the L1 Trigger.
 L1 Counter—is a 4-bit binary counter that isincremented every time the chip receives an L1
trigger.
 Beam Crossing Counter—is an 8-bit binary
counter that is incremented on every clock
cycle.
 Event FIFO—is a 24 location deep, 12-bit wide
FIFO. Each time the chip receives an L1
trigger, the output of the L1-Counter and theBeam Crossing Counter are loaded into the
FIFO prior to the counters being incremented.
These values are read from the FIFO every time
an event is read out and are used to tag the datawith 12-bits of information about the trigger
number and beam crossing number from which
the data came.
 Token Generation Logic—detects when the chip
has received an L1 trigger and when to generatea token to initiate the readout of data from that
L1 trigger. This logic waits until the Event
FIFO becomes not empty and it then issues atoken. It then monitors the data passing
through it from all the chips in the chain
looking for a ‘‘Trailer’’ bit pattern.
 Data Formatting Logic—attaches the header
information to the packets of data output fromthe chip on the Serial Data Output.
 Serial Data Output Driver—outputs the data to
the DAQ system.
3.4. Chip control
The command and control information allcomes into the chip on the command input pins.
The Command Decoder block decodes the command and sends the relevant instruction and data
to other parts of the chip. There are two mainclasses of information, which arrive here, L1
Trigger Commands and Control Commands.
These are distinguished by a 3-bit code.
Furthermore, two types of Control Commands
are possible, Fast Control Commands andSlow Control Commands. The two classes ofCommands and two types of Control Commandsare: L1 Trigger Command—in response the control
logic writes 3 samples from the pipeline into the
Readout Buffer.
 Fast Control Commands—this type of commandis sent when a command has to be issued to thechip more quickly than can be achieved bysending a slow command. There are only two
commands of this type: the Soft Reset andBeam Crossing Counter Reset. These commands will be sent to the chip at regularintervals during periods of time when no L1

ARTICLE IN PRESS
F. Campabadal et al. / Nuclear Instruments and Methods in Physics Research A 552 (2005) 292–328

Triggers will be sent to the chip in order toperform a limited reset of the chip.
 Slow Control Command—these are long packets
that enable the conﬁguration of all internalregisters of the chip and operation of the chip invarious test modes. All chips that receive thecommand must decode it, even if they do notact on it. This is to avoid un-addressed chips
erroneously decoding parts of the data ﬁeld as
the start of another command. To ensure thatthe chip does not respond to erroneouscommands the chip will be placed out of datataking mode for any command it receives which
affects the conﬁguration of the chip. Hence, itwill be necessary to issue a command to the chipto enable data taking after issuing a command
to change its conﬁguration. When the chip is
not in data taking mode, it will send its ID
instead of real data in response to an L1
Trigger.

3.5. Input/output circuits
The input/output circuits in the ABCD3TA chipare designed to ensure compatibility with thedesign of the overall readout system of the SCT
detector in the ATLAS experiment. In particular,
robust operation and low noise performance
should be maintained when the detector modules
are operated in the electrical environment of theexperiment. The signal receivers should provide
robust reception of signals and high rejection ofnoise, which may be generated by other components of the readout system. At the same time thenoise generated by the output signal drivers of the
ABCD3TA chips should be minimised. Since thefast signals, clock, commands and data, aretransmitted to and from the detector module
comprising 12 ABCD3TA chips by means of
optical links the noise considerations due toswitching of fast signals can be limited mostly toa single detector module.
In order to guarantee robust reception of signals
and low noise generation, all fast signals from andto the chip are transmitted in the differential
mode. In the ABCD3TA design the LVDS
standard, which has become the most popular309

differential data transmission standard in theindustry, has been adopted. The LVDS is a low
swing, differential signalling technology, whichallows data transmission at hundreds or eventhousands of Megabits per second over distancesof tens of metres, provided that proper cables areused.
On the SCT modules the distances of traces aremuch shorter and the nominal required speed of
40 Mbit/s is relatively slow compared to thecapability of standard LVDS circuits, however,
the reduced noise generated by them minimisesinterference to the front-end ampliﬁers allowing
simultaneous data acquisition and I/O operation.
The receivers of the clock and command signals
are designed to meet the speciﬁcation of the LVDS
standard. The driver circuits, which transmit thedata to the optical link driver is designed as an
LVDS type but with driving capability adjusted to
the requirement of the SCT detector module thus
minimising power consumption. The output data
is sent to the optical link driver only by the Masterchip and the output driver is not used in the Slaveand the End chips. In order to avoid dissipating
unnecessary power on the module, the drivercircuit is set in a power off mode when the chipis conﬁgured as a Slave or an END chip, which
reduces the power consumption per chip from
64 mW in active state to 4 mW when disabled.
The LVDS-like input/output circuits are usedalso for passing the data and token between
neighbouring chips on the module. The driving
capability of these circuits is much reduced
compared to the driver used for sending the data
off the Master chip as the distances to transmit thesignals are much shorter and the capacitive loadsof the traces do not exceed 10 pF for primaryconnections on the hybrid and 50 pF for redundant connections on the hybrid.

4. Design for large volume production
The full SCT requires 49,056 conforming
ASICs, not counting the spares. Obviously, given
the requirements for the overall efﬁciency of the
SCT to be better than 99%, use of any out-of-spec
chips would result in a degradation of the tracking

ARTICLE IN PRESS
310

F. Campabadal et al. / Nuclear Instruments and Methods in Physics Research A 552 (2005) 292–328

performance of the ATLAS detector. In additionsome losses are unavoidable through the fullconstruction process. A loss model was establishedfor losses that may occur in various steps startingfrom receiving the wafers from the foundry,
through wafer saw, hybrid and module assembly
and test culminating with installation of complete
modules. The assumed model resulted in arequirement of 61,000 conforming chips.
Based on the yield of 26% guaranteed by thefoundry vendor we ordered 961 6-in. wafers whichamounts to 250,000 chips to be tested. The numberof ordered wafers implied that wafer fabrication
would span 12–18 months and about 40 fabrication lots. Over this period of time the wafers could
display the full range of process variations.
Therefore, as a part of the design procedure andpreparation for production, extensive simulations
were made using corner model parameters supplied by the vendor, including post-rad conditions,combined with the assumed variation of temperature and power supply voltages.
In order to illustrate the issue let us recall a few
parameters from the corner models provided by
the vendor:

 the current gain factor b of bipolar transistors
may vary between production lots from 90 to350; for the worst case, after neutron irradiation, one has to accept b as low 40,
 the threshold voltage for the PMOS transistor
may vary between production lots from 0.69
to 1.15 V; in addition the maximum expected
drift after irradiation is up to 200 mV,
 the threshold voltage for the NMOS transistor
may vary between production lots from 0.69 to
1.05 V; in addition the maximum expected drift
after irradiation is up to 200 mV,
 the resistor value may vary between production
lots by 725%; in addition the resistor value
increases by 25% after irradiation.
On top of these variations, the design speciﬁcation also required that the IC meets the functional
speciﬁcations over the temperature range of
0–40 1C and for power supply voltages differing
by 7200 mV from the nominal values.

In the light of the above numbers it is clear thatparticular effort was needed to make the design
insensitive to the variations of process parameters,
temperature, power supply voltages and to radiation effects. In order to validate the design
extensive corner simulations have been performed
for all combinations of the corner models,
temperature and power supply voltages. As an
example the results of corner simulations for thegain of the front-end circuits are shown in Fig. 8.
Each point on the plot represents one combinationof the device corner parameters, temperature andbias voltage. There are nine corners for parametersof MOS transistors (PSET: 0–8) combined withfour values of resistors, three values of power
supply voltage and two temperatures. Given very
wide ranges of variation of all these parameterssome variations of the circuit parameters areunavoidable, but the fabricated chips must still
meet speciﬁcations. Although the corner parameters resulting from process variations are
speciﬁed by the vendor at the 3s level deviationfrom the nominal values and the probability ofoccurrence of some combinations is very low, it
was decided to require that for the simulations thecircuit should be fully functional for any combination of process, temperature and power supply
voltage variation. This conservative approach wastaken to provide an additional safety margin with

Fig. 8. Simulation of pulse gain of the full analogue chain as afunction of process parameter variations (resistors from 25%
to +50% (RSET from 1 to 2), CMOS corner parameters(PSET from 0 to 8), temperature 0 and 40 1C, power supply
7200 mV).

ARTICLE IN PRESS
F. Campabadal et al. / Nuclear Instruments and Methods in Physics Research A 552 (2005) 292–328

respect to unexpected situations that may appear
in the experiment.
For the digital blocks the following design
strategy has been applied. The standard cell libraryhas been parameterised for different corner parameters, power supply voltages and temperatures.
It was required that the digital circuits should
operate correctly at the nominal clock frequencyof 40 MHz over the temperature range of 0–40 1C
and for the power supply voltage differing by
7200 mV from the nominal value of 4 V. It is
worth noting that we have set the nominal digital
power supply voltage for the ABCD3TA design at
4 V, although the nominal power supply voltage
for the DMILL technology is 5 V and the foundryparameterisation is valid for 5 V power supply.
Reduction of the power supply voltage was
required to keep the power consumption as low
as possible.
Taking into account the corner parameters
resulting in the slowest operation of the digital
circuitry, degradation of the digital speed due toreduced power supply voltage, increased temperature and radiation effects, it has been found that
all these factors combined together may result inthe speed of the digital circuitry being reduced by afactor of 2 lower compared to the speed fornominal foundry parameters, power supply andtemperature 0 1C. For practical reasons most of
the digital simulations have been performed forthe nominal parameters and nominal conditions,while requesting that all digital circuitry should befully functional at the doubled clock frequency, i.e.
80 MHz.

311

like phase margin of the preampliﬁer, input
impedance of the preampliﬁer, power supply andcommon mode noise rejection ratio, immunity todigital noise.
In this section, we present examples of basic
electrical characteristics of the barrel SCT modules
being now produced in series. A photograph of thebarrel module is shown in Fig. 9. The details on
the module design and on the construction steps
can be found in Ref. [10]. The basic analogue
parameters are: gain, noise (ENC), thresholdspread, noise occupancy at a given threshold andtimewalk.
5.1. Gain offset and noise
Given the binary architecture of the ABCD3TA
chip, the parameters of the front-end channel canbe extracted from the threshold scans performedfor different amplitudes of test pulses. For eachvalue of the test charge the result of the thresholdscan is a complementary error function of which
the 50% point corresponds to the signal amplitude
at the discriminator input and the transition widthcontains information on noise spread. The calibration circuitry built in the ABCD3TA design
enables the testing of all the channels in the ASICs
mounted in a module without necessity of using
external test signals. As a result of the thresholdscans one obtains a response curve for eachindividual channel, i.e. the discriminator threshold

5. Module performance
Requirements for the analogue parameters andcharacteristics of the ABCD3TA ASICs are
speciﬁed for given parameters of the silicon strip
detectors. Therefore, the performance of the
ASICs should be validated by demonstrating thatthe requirements are met for a fully loaded module
designed according to the SCT speciﬁcation. It is
important to note that some design aspects can bedemonstrated only in the ﬁnal fully loaded
modules. This applies in particular to parameters

Fig. 9. Barrel module. Six ABCD3TA chips on one side of themodule are visible.

ARTICLE IN PRESS
312

F. Campabadal et al. / Nuclear Instruments and Methods in Physics Research A 552 (2005) 292–328

as a function of the input charge. From theresponse curve one then extracts the gain of thefront-end circuit and the discriminator offset foreach individual channel. From the error functions
one extracts the rms value of noise at thediscriminator input, which then can be translated
into the equivalent ENC at the input. Typical
distributions of gain offset and noise for 762
channels on one side of the module are shown in
Fig. 10.
The ENC for a fully populated module is below
1500 electrons rms and is consistent with the value
measured for a single channel with equivalent
input capacitance. The measurements shown
correspond to the hybrid temperature of 25 1C.
The ENC increases with increasing temperature by
about 5 electrons rms per degree.
Comparison
ofthechannel-to-channel
and chip-to-chip spread of the gain and of theoffset shows that for a threshold of 1 fC the offset
spread will dominate the effective thresholdspread.
5.2. Uniformity of threshold
Good channel-to-channel uniformity of thenominal 1 fC threshold is essential for operationof the binary readout system. The effective
discrimination threshold in terms of the input
charge is determined by the discriminator offset aswell as by the gain of the front-end circuit of agiven channel. The uniformity of the effective 1 fC
threshold is ensured through the ASIC thresholdcorrection circuit, where each channel is provided
with a trim DAC of 4-bit resolution with four
selectable ranges. The ﬁrst range (0–60 mV) is usedpre-irradiation, which gives channel-to-channelalignment at the 4 mV bin level with a thresholdof 100 mV for all channels. This is to becompared with the noise value of 12.5 mV.
Therefore, the channel-to-channel thresholdspread effectively contributes less than 1% to thepre-irradiation module noise values.
Fig. 11 shows the distribution of 1 fC threshold
before and after the trimming procedure. One cannotice that the spread of the threshold before
trimming is at the same level as the spread of thediscriminator offset shown in Fig. 10. This provesthat the offset spread dominates the uniformity ofthe effective threshold.
5.3. Noise occupancy at 1 fC threshold
The SCT design goal is to set the ASIC singlestrip binary readout threshold at 1 fC in order toensure high tracking efﬁciency for particles traversing the silicon at inclined angles, depositing
charge on more than one readout strip. The meannoise occupancy for all channels of a module isshown in Fig. 12. The noise occupancy of theindividual unirradiated modules at 1 fC, even if
operated at room temperature, is typicallyo1  10 5, which is well below the level of5  10 4 required for correct operation of the
SCT.
5.4. Timewalk
The requirement is that the timewalk should beless than 16 ns. Here, timewalk is deﬁned as the
maximum time variation in the comparator output
over a signal range of 1.25–10 fC, with thecomparator threshold set to 1 fC. Fig. 13 shows
measured data for one chip on a barrel module.
The top plot shows the delay of the comparator
response (in strobe delay units) versus injectedcharge (fC) and the bottom plot shows the
timewalk distribution in nanoseconds measured
for input charges from 1.25 to 10 fC as
deﬁned above. The speciﬁcation is met for all
channels with an additional safety margin of
about 4 ns.

6. Radiation effects
The detector together with its readout electronics will be located close to the interaction point
and so exposed to high levels of radiation. The
highest accumulated radiation levels expected in
the ATLAS SCT after 10 years of operation,
including 50% uncertainty, will be 10 Mrad of
total ionising dose and a 1 MeV neutron equivalent ﬂuence of 2  1014 n/cm2, causing displacement damage. The ABCD3TA chip is realised in a
BiCMOS technology so it is built of MOS

ARTICLE IN PRESS
F. Campabadal et al. / Nuclear Instruments and Methods in Physics Research A 552 (2005) 292–328

Fig. 10. Distributions of gain, offset and noise for 6 chips (762 channels).

313

ARTICLE IN PRESS
314

F. Campabadal et al. / Nuclear Instruments and Methods in Physics Research A 552 (2005) 292–328

Fig. 11. 1 fC threshold spread for 6 chips on one side of the module before and after trimming.

transistors, which are primarily susceptible toionising radiation, and bipolar transistors usingoxide-isolation structures, which are susceptible toboth displacement damage and ionising radiation.
High-energy particles present in the SCT radiationﬁeld will cause single event effects (SEE), whichhave to be taken into account as well. To validate
the design of the chips with respect to radiation
hardness, an extensive irradiation program has
been performed in which about 300 chips in total
have been irradiated with various radiation
sources.
In the ABCD3TA design there are someparticularly critical parameters and characteristics
that are affected by radiation: noise of the frontend, matching in the front-end circuit, in particular

the offset spread of the discriminator, speed of thefront-end and the speed of the digital CMOS
circuitry. Increase of power consumption after
irradiation is another critical aspect because of thelimited capability of the cooling system to remove
the heat from the active volume of the detector andbecause of limited capability of the power supply
system to deliver the power.
Given the particular composition of the radiation ﬁeld in the SCT detector and the complexityof radiation effects in the basic devices and in thecomplete integrated circuit, ideally, one would
prefer to perform radiation tests in the ﬁeld
identical or similar to the one expected in theexperiment. Such a source of radiation is, however,
not available. Therefore, irradiations of the

ARTICLE IN PRESS
F. Campabadal et al. / Nuclear Instruments and Methods in Physics Research A 552 (2005) 292–328

315

 200 MeV pion beam at PSI, Villigen, Switzerland, neutrons from the TRIGA reactor in Ljubljana,
Slovenia [12], 60Co source at different sites in California,USA, X-ray source at CERN.

Fig. 12. Measured mean noise occupancy for all channels of amodule. At 1 fC threshold the noise occupancy is 2.32  10 6.

The proton beam and the pion beam deliver
both the ionising dose and the displacement
damage as expected in the SCT detector. In orderto study and to factorise the ionising effects andthe displacement damage, the devices were tested
separately with X-rays and gamma photons
causing primarily ionisation damage and withneutrons causing primarily displacement damage.
The devices in the SCT detector will be exposed toneutrons with a broad energy spectrum, fromthermal up to tens of MeV of energy, so one
should verify whether displacement damage
caused by neutrons is of the same nature as thedisplacement damages caused by charged particles.
In addition to the commonly known and usuallyconsidered radiation effects in semiconductor
devices, there are two particular effects in the
ABCD3TA chips, which have been studied indetail, namely the low dose rate effect (LDRE) in
bipolar transistors and the damage of bipolartransistors caused by thermal neutrons.
Chips irradiated with charged particles andneutrons were mounted on hybrids and werebiased, conﬁgured and clocked during irradiation.
Analogue parameters were measured using theinternal calibration circuit of the ABCD3TA.
6.1. Analogue performance under irradiation

Fig. 13. Timewalk measurements for 128 channels in one chipon a barrel module.

ABCD3TA chips were performed using different
available facilities:

 24 GeV proton beam at CERN [11],The front-end stage of the ABCD3TA chip isbuilt as a transimpedance ampliﬁer using a bipolar
input transistor. One of the noise sources, which
contribute to the total ENC, is the shot noise of
the base current of the input transistor, which isincreased due to the decrease of the current gain
factor b. In bipolar transistors b is degraded byionisation effects as well as by displacement
damage. Irradiation with protons and neutrons
were therefore performed to study the noise
performance of the chips.

ARTICLE IN PRESS
316

F. Campabadal et al. / Nuclear Instruments and Methods in Physics Research A 552 (2005) 292–328

In the binary readout scheme precise control
over channel-to-channel threshold matching is oneof the most critical issues. Tests of the chip
prototypes showed that matching of the resistors
is the limiting factor for the offset spread in thediscriminator and that resistor matching degrades
signiﬁcantly after irradiation with neutrons or
protons. Threshold spread was therefore also amatter of concern after irradiation with protons
and neutrons.
6.1.1. Proton irradiation results
Irradiation with 24 GeV proton beam at the
CERN PS were performed in conditions mostsimilar to those expected in the experiment. The
radiation environment provided by the PS beam
was close to what is expected in the ATLAS
experiment, except for the neutron ﬁeld, and it
allowed for testing the components with respect tototal ionising dose, bulk damage due to charged
particles and SEE. Therefore, the PS facility wasused as the standard irradiation test bed for SCT
electronics.
During irradiation hybrids were kept inside a
cold box ﬂushed with nitrogen at a temperature ofabout 2 1C, which will be the operating temperature of the chips in the ATLAS experiment. At thistemperature the annealing of radiation damage inbipolar and CMOS structures is negligible. The
proton beam with a spot size of 1  2 cm2 wasscanned across the hybrid. Chips received the total
ﬂuence of 3  1014 p/cm2 during a period of about
10 days. The displacement damage of this proton
ﬂuence is equivalent to 1.8  1014 n/cm2 [13]. The
total ionisation dose delivered with this proton
ﬂuence was 10 Mrad.
Evolution of noise with ﬂuence measured inproton irradiation is shown in Fig. 14. The noise
increase after full ﬂuence agrees with expectations.
The noise shown in Fig. 14 was measured with
open inputs so that the capacitance at thepreampliﬁer input was negligible. In an SCT
module, i.e. with strips connected to inputs, thetotal noise will be dominated by the voltage noise
contribution due to the strip capacitance. As the
input voltage noise of preampliﬁer is determinedby the transconductance of the input transistor, it
is not inﬂuenced directly by the radiation effects.

Fig. 14. Evolution of noise with ﬂuence of 24 GeV protons for
six chips irradiated on a hybrid. Noise is expressed in thenumber of electrons of ENC.

However, due to decrease of b one has to reducethe collector current in the input transistor inorder to keep the base current and so the shotnoise within an acceptable range. As a result thetransconductance of the input transistor will be,
respectively, lower and the voltage noise higher.
Irradiation of full modules with protons provedthat required efﬁciency and noise occupancy could
be maintained also after irradiation [14].
An example of the evolution of untrimmed
threshold spread with ﬂuence for six chips isshown in Fig. 15. One can notice that the spreadincreases rapidly after initial radiation and thensaturates above 1  1014 p/cm2. One can also
notice some spread between the chips. Therefore,
as discussed in Section 3.1.1, an additional safety
factor has been foreseen in the range of the
TrimDAC to make sure that one can correct thethreshold for all the channels with peak-to-peakspread of up to 240 mV. It is expected, however,that for a majority of the chips trimming at range
1, i.e. 120 mV, will be sufﬁcient after receiving thefull expected ﬂuence and the threshold spread after
trimming will be negligible compared to noise.
6.1.2. Neutron irradiation results
Hybrids were irradiated with neutrons byinserting them into the reactor core through anirradiation tube. The neutron energy spectrum in
the irradiation tube spans from thermal energies to

ARTICLE IN PRESS
F. Campabadal et al. / Nuclear Instruments and Methods in Physics Research A 552 (2005) 292–328

317

Fig. 15. Evolution of the rms value of threshold spread at 1 fC
input charge with proton ﬂuence. No threshold trimming was
performed for these measurements.

Fig. 16. Evolution of noise with 1 MeV equivalent ﬂuence ofreactor neutrons for 6 chips irradiated on a hybrid. Noise isexpressed in the number of electrons of ENC.

about 10 MeV [15]. From the measured ﬂux the
NIEL equivalent ﬂux of 1 MeV neutrons wasdetermined [16] using the neutron damage function for silicon from [17]. The equivalent ﬂuence of2  1014 n/cm2, was delivered to the chips within
440 s. During this time chips received also about
the same ﬂuence of thermal neutrons and about
400 krad of ionisation dose from gamma background. Temperature of the chips during irradiation was about 3 1C.
Fig. 16 shows evolution of noise with ﬂuence of
1 MeV equivalent neutrons measured during irradiation in the reactor. One can note a slightly
larger noise increase at the same NIEL ﬂuence(note that the proton ﬂuence in Fig. 14 should be
multiplied by 0.6 to get the ﬂuence in units of
1 MeV neutrons) in chips irradiated with neutrons
as compared to protons. This effect was seen also
in other irradiation tests of SCT readout chips [8]including the irradiation of basic DMILL bipolar
test structures.
Recent irradiation results indicate that thiseffect can be explained by additional damage inbipolar transistors caused by thermal neutrons,
which are present in the reactor channel [18].
These are not present in the PS and also do notcontribute to the 1 MeV equivalent ﬂuence, however, they will be present in the SCT detector.
Displacement damage is enhanced in this case by
the energetic products of the nuclear reactions ofthermal neutrons and boron atoms used as dopingin the base of the bipolar transistors. The thermal
neutrons are captured by boron isotope 10B
resulting in a reaction 10B+n- 7Li+a. Althoughdoping concentration of boron in the base isrelatively low, of the order of 1018 cm 3, andabundance of 10B in natural boron is only about
10% the ﬂuence of a-particles and lithium ionsbecomes signiﬁcant due to the particularly highcross-section of boron to capture thermal neutrons
which reaches 3840 barns. The total energy of
2.3 MeV released in this reaction is divided
between the a-particle and the lithium ion anddeposited in a very short range of a few microns
from the interaction point. In addition, there areheavily doped p+ regions below the base contacts
and energetic a-particles and Li ions originatingfrom boron capture reactions in these regions cancontribute to the damage in the transistor base.
6.1.3. X-ray irradiation results
Comparison of the results from proton andneutron irradiation does not provide a deﬁnitive
answer whether ionisation effects present inproton irradiation contribute signiﬁcantly todegradation of the current gain factor b in bipolartransistors. In order make an estimate of ionisation effect on bipolar transistors the ABCD3TA
chips were irradiated with X-rays of 10 keVenergy. The irradiation was performed at a dose
rate of 36 krad/min up to a total dose of 10 Mrad.
The measurements were taken immediately after

ARTICLE IN PRESS
318

F. Campabadal et al. / Nuclear Instruments and Methods in Physics Research A 552 (2005) 292–328

Fig. 17. Noise as a function of the current in the input
transistor before and after X-ray irradiation.

irradiation so that no signiﬁcant annealing took
place.
Fig. 17 shows the noise as a function of thecollector current of the input transistor before andafter the X-ray irradiation. After the X-ray
irradiation one can see a small increase of noise
as predicted, since in this case only limited
degradation of the beta parameter is expected.
6.1.4. Low dose rate tests
All the irradiation tests reported above havebeen performed with dose rates 2–3 orders ofmagnitude higher than those expected in the
ATLAS experiment. Therefore, one should address a question about validity of such tests
performed on a time scale of days or weeks whenused for making predictions for 10 years ofoperation of the ATLAS experiment. Typically,
the effects caused by ionising radiation undergo
some annealing and irradiation at high dose rate
results in larger effects compared to irradiation up
to the same total dose but performed at low dose
rate. For CMOS devices and circuits a wellestablished annealing procedure has been elaborated that allows one to convert high dose rateirradiation results to irradiation conditions at low
dose rate [19].
Recently several reports have been published on
the LDRE observed in modern bipolar transistors
using oxide isolation technique when irradiatedwith ionising radiation [20,21]. The effect is
opposite to what is typically observed in CMOS
devices, i.e. irradiation with a low dose rate leads

to larger degradation of b compared to irradiation
with a high dose rate up to the same total dose.
This effect may lead to underestimation of theradiation damage when performing radiation tests
with a high dose rate, which is the only practical
way to achieve a full ATLAS dose. The ATLAS
experiment is intended to operate for ten
years, including periodic breaks. In the SCT
detector an average dose rate of 0.05 rad(SiO2)/s
is expected [1].
Many different approaches have been tried totest dose rate effects on bipolar technology, andrecent studies have shown that high temperatureirradiation at high dose rates can mimic the effectsof low dose rate irradiation [22–24]. It has been
seen that these effects are strongly technology
dependent, which means that each new technology
has to be tested. Since the DMILL technology usesoxide isolation technique in the structure of
bipolar transistors it is potentially susceptible to
the LDRE. Therefore, a dedicated irradiation
experiment has been performed in order to understand whether bipolar transistors in the DMILL
technology are susceptible to LDRE [25].
All irradiations have been done using threedifferent 60Co sources. A Pb+Al shielding box
has been used together with geometrical considerations in order to avoid dose enhancement
effects according to standards [26,27], guaranteeing less than a 20% systematic error in thedosimetry. The dosimetry was performed using
thermoluminiscent devices (TLD), also according
to standards [28]. Since the net results of ionisation
effects depend on the bias conditions during
irradiation, the transistors were kept biased inforward directions as used in analogue circuits.
The tests were performed in two steps.
In the ﬁrst phase of the experiment thetransistors were irradiated at a very wide rangeof dose rates, all reaching a total dose of
1 Mrad(SiO2) in order to obtain data even for
the very low dose rates in a reasonable period oftime. The dose rates chosen covered a range offour decades and the values were: 0.05, 0.28, 1.33,
31.1, 112, 575 rad(SiO2)/s. The relative decrease ofbeta (Db=b) in all these experiments was in therange 10–15% and there was no indication of
LDRE in these transistors.

ARTICLE IN PRESS
F. Campabadal et al. / Nuclear Instruments and Methods in Physics Research A 552 (2005) 292–328

319

of the CMOS circuits depends on the power supply
there are two parameters, which provide information about the speed margins of the chip:

However, in order to prove that the LDRE does
not appear at high doses at low dose rate,irradiation should be performed up to a total doseof 10 Mrad at dose rate of 0.05 rad/s, which would
correspond to the real conditions in ATLAS-SCT.
Such an experiment would take too long toprovide meaningful results. A solution to the
problem is to map out the damage on thetransistors vs. the total dose taking intermediate
measurements for increasing total doses up to
10 Mrad. In this way one can perform low dose
rate irradiation up to a certain achievable totaldose, and then estimate the damage at the ﬁnal
total dose by extrapolation. Furthermore, one cansee if irradiations done at different dose rates leadto divergence of curves corresponding to different
dose rates. The conditions of the four different
mapping experiments that have been performed
for this purpose can be seen in Table 4.
The results of this experiment for the DMILL
transistors are shown in Fig. 18. One can noticethat for all dose rates there is no signiﬁcantdependence on the dose rate. A somewhat larger
effect observed for the dose rate of 1.24 rad/s andfor the total dose above 2 Mrad is, however, muchsmaller compared to effects reported in theliterature for processes that exhibit LDRE. Basedon these results we have concluded that there is no
signiﬁcant LDRE that would have to be taken into
account for evaluating radiation hardness ofbipolar transistors in the DMILL technology.

 maximum speed measured at the nominal
supply voltage of 4 V, minimum supply voltage at which the chipworks correctly at 40 MHz.
Fig. 19 shows the degradation of speed of the
ABCD3TA chip after X-ray irradiation up to a
total dose of 10 Mrad. The results are shown for
the following digital tests:

 TEST 1—L1/BC counters check, which tests
the functionality of the two counters by readingout several even records;
0(Beta - Beta0) / Beta0 (%)

-20

-40

-60

0.05 r/s, room T
1.24 r/s, 10°C

-80

112 r/s, room T
112 r/s, room T

6.2. Digital performance under irradiation
-100
105

6.2.1. Digital speed
The primary radiation effect in the digital
CMOS circuitry of the ABCD3TA is a decreaseof the maximum clock frequency at which the chipcorrectly performs all operations. Since the speed

106
Total Dose (rad(SiO2))

107

Fig. 18. Mapping of the common emitter current gain change
for DMILL transistors irradiated at different dose rates up to
10 Mrad total dose.

Table 4
Dose rates and total dose samples taken in the different irradiation of mapping experiment
Exp #Dose rate (rad/s)

Total dose (Mrad)

1
2
3
4

112
112
1.24
0.05

1
0.5
1
0.06

3
1
1.4
0.10

5

7

10

2.2
0.16

2.4
0.25

3.2
0.35

5.2
0.50

6.2
0.67

6.8
0.81

7.8
0.90

1.0

ARTICLE IN PRESS
320

F. Campabadal et al. / Nuclear Instruments and Methods in Physics Research A 552 (2005) 292–328

required that all the digital blocks involved in thereadout of data operated correctly after receiving
the full dose of 10 Mrad.
After delivering an ionising dose to the chips, anincrease of current consumption in the digital partof the chips was observed. This current increase
was identiﬁed as the leakage current between MOS
transistors. The excess current did not inﬂuence
the digital performance of the chips. However, thepower consumption must comply with the limitations imposed by the power distribution andcooling systems of the SCT. It should be notedthat all measurements showed that the current
increase (on average 50 mA/chip) would be manageable in the ATLAS experiment.

Fig. 19. Maximum speed at supply voltage of 4 V (a) andminimum supply voltage at 40 MHz (b) as a function of total
ionising dose.

 TEST 2—conﬁguration check, which validates
write and read-back of the conﬁguration
register; TEST 3—L1 overﬂow check, which validates
the error ﬂags by forcing an overﬂow of thederandomising buffer; TEST 4—data taking, which tests the full data
path from pipeline through readout buffer.
We observe a degradation of speed almost by afactor of 2, nevertheless, after 10 Mrad the chip
still meets the requirement of 40 MHz operation at
the nominal supply voltage. It is worthy to notethat the results shown in Fig. 20 do not include
any annealing so that they represent worst casepost-radiation conditions.
Radiation resistance of the digital circuitry has
also been proven in proton irradiation tests.
During typical irradiations with a total ﬂuence of3  1014 p/cm2 the chips also received an ionisingdose of about 10 Mrad. Although the primary goalof this irradiation was testing the radiation
resistance of the front-end circuitry, the measurements of analogue parameters were performed at
the nominal clock frequency of 40 MHz. Thus, this

6.2.2. SEU test results
The SCT readout chips in the experiment will be
exposed to high-energy particles. A maximum of
3  1014 hadrons/cm2 with energy greater than
20 MeV will cross the ABCD3TA chips during
their lifetime. Study of the sensitivity of the chips
to SEE was therefore equally important as thestudy of the cumulative effects.
There are two major types of digital blocks in
the ABCD3TA chip that may be affected by SEE:
the pipeline and the static registers that contain
information about chip conﬁguration and settingsof operating points. A bit ﬂip in the pipeline causesa single data error and does not require intervention. The rate of such events has to be comparedwith the noise hit rate from the front-end. Errors
in the static registers may lead to changes in theoperating mode and will require reloading of thechip conﬁguration.
Measurements of the SEE have been done withthe 24 GeV proton beam at the CERN PS and the
200 MeV pion beam at the PSI [30]. Beam
structures at these two sites are quite different.
At the PS the beam is structured in short spills ofvery high intensity whereas at the PSI the pion
beam is quasi-continuous with 50 MHz structure.
Nevertheless results of measurements at the twosites are rather consistent. This is expected since
the cross-section for SEE is expected to saturate
well below 200 MeV [29].
The scheme of measurement was to write to amemory cell in the device, let a certain ﬂuence

ARTICLE IN PRESS
F. Campabadal et al. / Nuclear Instruments and Methods in Physics Research A 552 (2005) 292–328

321

Fig. 20. ABCD3TA production ﬂow.

traverse the device and then read the content of thecell. From the number of differences observed
between the written and read-back values andknown ﬂuence the probability for a bit ﬂip in suchcells was calculated. Measurements were done withpipeline and mask register cells. The latter wereused as the estimate of SEE rate also of other static
register cells in the chip. Results of measurements
using the proton and the pion beam are summarised in Table 5.
The numbers in Table 5 are used to estimate theimpact of SEE on the performance of the SCT. To
make a conservative estimation it can be takenthat the sensitivity of pipeline cells is 1012 particles/
cm2/ﬂip and of static registers 5  1013 particles/

cm2/ﬂip. During 10 years of LHC operation themachine will be running at high luminosity forabout 1/3 of the time i.e. about 108 s. To estimate
the worst case SEE rate it can be taken thatmaximum of 3  1014 fast particles/cm2 will crossthe chips during this time giving the maximum ﬂux
of 3  106 particles/(cm2 s). With 132 bits perchannel in the pipeline one expects an SEE rateof 10 11 per bunch collision (every 25 ns) per
channel. This number is negligible compared to the
expected noise occupancy of 5  10 4.
Similar consideration for static cells gives theSEE rate of 6  10 8 bit-ﬂips/s per cell. With 10
critical bits per chip and 6 chips daisy chained forone link and 96 links per off-detector readout

ARTICLE IN PRESS
322

F. Campabadal et al. / Nuclear Instruments and Methods in Physics Research A 552 (2005) 292–328

Table 5SEE sensitivity and corresponding cross-section measured at PS and PSI facilities
PS (24 GeV/c protons)

Pipeline cell
Mask register cell

PSI (200 MeV/c pions)

SEE sensitivity((p/cm2)/ﬂip)

SEE cross-section(cm2/bit)

SEE sensitivity((p/cm2)/ﬂip)

SEE cross-section(cm2/bit)(1.270.3)  1012
(7.076.0)  1013

(8.372.0)  10 13(1.471.2)  10 14(3.170.4)  1012
(4.771.7)  1013

(3.270.4)  10 13(2.170.7)  10 14

The sensitivity is given in units of ﬂuence of particles traversing the device, which will cause one bit ﬂip in one cell. Errors are statistical
only.

crate, the expected SEE rate is 3  10 4/crate/s.
Such an error rate can easily be handled byreloading chip conﬁgurations in regular intervals
from the off detector readout electronics.

testing. Given that bare, not packaged dice areassembled into the hybrids, the hybrid test was theﬁrst practical point where long-term testing could
be performed. The material ﬂow for the ASIC
production is shown in Fig. 20.

7. Large volume production

7.1. Wafer testing

As already stated, the full SCT requires 49,056
conforming ASICs installed but our model for
losses in assembly and installation created arequirement for 61,000 good chips. Given the
expected yield of 26% based upon the foundry’s
guarantee, the production plan was made for 961
wafers or roughly 250,000 ICs.
The production plan included the following
steps:

The assembly procedure of the SCT modules
requires that the ASICs be fully tested at the wafer
level. These tests should provide not only information about basic functionality but also fullcharacterisation of the analogue parameters. The
requirements to measure precisely the analogue
parameters at the wafer testing stage demanded
development of a custom wafer testing systemsince the program of measurements could not berealised using a standard IC tester. The basic
measurements performed for the ABCD3TA chips
include: Receipt of wafers from the foundry vendor withvisual inspection.

 Full functional test of each IC in wafer form
 Wafer saw and selection of good ICs.
 Assembly of ICs into hybrid circuits containing

 analogue front-end performance (gain, noiseand comparator offsets for every channel),

12 ICs each.
 Test of full hybrid circuit including long-term
test.

 digital functions (control register, addressing,

The resources of the ATLAS-SCT collaboration
are such that the testing and assembly workneeded to be shared by several institutions. The
testing of wafers was conducted at three sites: the
CERN laboratory in Switzerland, the Rutherford
Appleton Laboratory in the UK and the University of California, Santa Cruz in the US. The
good chips were then sent to several otherinstitutes for assembly into hybrids and long-term internal DACs linearity,
 I/O signal properties (timing, amplitudes, duty

communication, pipeline, output buffer), sensitivity of digital functionality to clock
frequency and supply voltage,

cycles), power consumption.
7.1.1. System overview
The block diagram of the wafer testing system isshown in Fig. 21. The system is based on the VMEARTICLE IN PRESS
F. Campabadal et al. / Nuclear Instruments and Methods in Physics Research A 552 (2005) 292–328

standard and consists of several custom designed
boards and control software. The system iscontrolled by a GUI written in Visual C++,
which runs in a PC under Microsoft Windows(W95/NT/2000). The GUI is based on the code forthe previous version of the test system [31]. The PC
communicates with the VME crate using the NIVXI interface from National Instruments.
The crate houses a custom-designed VME board
equipped with an ORCA3T FPGA. The FPGA
operates at 40 MHz and interprets the VME
commands, communicates with the ASIC under
test, and controls most critical parameters in thesystem. The data between the VME board and theprobe card are transmitted as differential signals.
Two intermediate boards, named Pin Driver andConnector Board, have been designed to transfer
and control the signals between the VME crate
and the probe station. The Connector Board
contains high current, high-speed drivers
AD53040 with variable output signal levels to test
ABCD3TA inputs. It contains also window
comparators discriminating on the upper andlower ABCD3TA output signal levels. The signal
delays and the window comparator levels arecontrolled by the FPGA through the DACs.

Fig. 21. The architecture of the ASIC wafer test system. All
hardware parts of the system and their communication are
shown.

323

The probe card has been designed using astandard probe card technology combined with acustom designed printed circuit board following
the rules required for low-noise analogue measurements.
The standard procedure of measuring theanalogue parameters of the ABCD3TA chips
requires the transmitting of large amounts of data
between the chip and the data acquisition system.
The transmission is one of the factors that drive
the testing time. Therefore, the VME board has
been designed to perform the low-level dataprocessing that reduces the amount of data to betransferred to the PC. The FPGA was programmed to be able to issue a sequence of
ABCD3TA input commands, which can be looped
over a given number of times. Furthermore, adedicated data-stream-decoding algorithm wasconceived to interpret the data from the chip andto extract the numbers of channels having hits.
The count of the number of hits for each channel isstored in a memory chip on the VME board. The
number of hits per channel, together with the
decoding algorithm error codes, is the only
information from the test to be read out. This
scheme greatly reduces the amount of informationtransferred from the VME board to the PC.
The functions of the digital circuitry of the IC
are veriﬁed using test vectors, which deﬁne thesequence of the IC’s control line values forconsecutive clock cycles. The IC’s output signals
are transmitted to the FPGA and compared withthe expected data corresponding to that particular
test vector. Only the binary result of the comparison is read out. Both the stimulus test vector andthe expected chip response are stored in memory
chips on the VME board, which makes it possible
to run the test vector multiple times without reloading. This allows repetitive testing todetect soft errors. The expected chip response
was obtained with Verilog simulation of the
ABCD3TA chip design. The FPGA algorithms
do not interfere with the test vector content, whichallowed for rapid test vector development without
ﬁrmware changes.
Digital tests can be performed at frequencies
higher than the nominal 40 MHz. This capability isachieved by buffering the signals in IDT72V2113

ARTICLE IN PRESS
324

F. Campabadal et al. / Nuclear Instruments and Methods in Physics Research A 552 (2005) 292–328

FIFOs, which are able to perform the read/write
operations at different frequencies. The FIFOs canhold the data for up to 262,000 clock cycles. The
data exchange between the FPGA and the FIFOs
is done at 40 MHz, and the data ﬂow between the
FIFOs and the probe card can be done at adifferent frequency in the range between 40 and
100 MHz.
The data taken required substantial, post-test
analysis to extract the analogue performance fromthe binary ASIC data. This was done initially at
the testing sites and then at CERN for all the data.
This ensured consistent treatment of data fromdifferent sites, allowed archiving of all data anduploading to a common database. These results
were used to make the ﬁnal selection of good
ASICs.
7.1.2. Testing procedures
7.1.2.1. Analogue tests. The basic method for thecharacterisation of the analogue circuitry of the
ABCD3TA relies on scanning the threshold while
injecting a ﬁxed calibration charge. This measures
the integral of the Gaussian distribution of noise
superimposed on the signal. Repeating these scans
for several amplitudes of calibration charges one
extract the gain, offset, noise and the trim DAC
performance. For each scanning point 200 triggers
are sent to the chip under test. With the test
parameters chosen for production testing, theaccuracy of noise measurement is dominated by
the 9% statistical uncertainty. The precision of thegain and trim DAC linearity measurements isdominated by 5% error on the calibration pulse
amplitude. Their statistical uncertainty is less than1%.
7.1.2.2. Digital tests. The test vectors have beendeveloped to characterise the performance ofdifferent parts of the digital circuit. The following
set is used in the test: Conﬁguration register R/W test—a value iswritten to the ABCD3TA conﬁguration register, then the chip is set to present the content of
the register on the output, and the values arecompared. All bits of the ABCD3TA conﬁguration register are scanned.

 Addressing, beam counter and the error code
test—the chip possesses an addressing scheme
to distinguish different chips on a module. The
counter of the LHC beam crossings is embedded in the output data to separate theinformation from different events. The bits ofboth counters are scanned. In addition, abnormal conditions are created and the chip
response is veriﬁed.
 Data compression logic test—functionality ofdifferent criteria for data sparsiﬁcation is
veriﬁed. Hits are placed in different time slices
relative to the trigger.
 Dynamic digital pipeline test—the digital data
are supplied to the input register of the digital
circuit according to channel mask. Time structure of the pipeline is scanned.
 Static digital pipeline test—the digital data aresupplied directly to the pipeline, avoiding the
input register.
 Redundant command line test—the dynamic
pipeline test is performed using the redundant
input command and clock lines.
 Data and token by-passing circuitry test—theinter-chip communication functions are tested.
The test vectors are run at a set of frequencies
from the nominal 40 MHz up to 90 MHz to ensure
sufﬁcient performance margin for radiation damage. The test vectors are also scanned over thedigital supply within +5% of the nominal 4.0 V.
The lower range of the scan is extended to monitor
the quality of the probe card contact with the chippads. The problems with the contact are revealed
by non-monotonic dependence of test vector
efﬁciency on the voltage.
7.1.2.3. Power consumption. We determine thepower consumed by the chip by measuring thecurrents, separately for the digital and analogue
parts. We calibrated each test system to within 1%
in this measurement. To simulate the conditions of
the experiment, the 100 kHz trigger rate is set whilea random 3% of channels have hits. The measurement is done separately for the ‘‘master’’ and‘‘slave’’ modes. Chips with power consumption
outside of a 30% margin from the wafer meanvalue are rejected.

ARTICLE IN PRESS
F. Campabadal et al. / Nuclear Instruments and Methods in Physics Research A 552 (2005) 292–328

7.1.2.4. Internal DACs. We verify the performance of comparator threshold voltage, input
transistor bias current and shaper current DACs
by doing a full scan of the respective DAC bits andmeasuring the voltage values with the test system
ADC. The linearity of the DACs is extracted andcompared with speciﬁcations. The error on eachmeasurement is 1%. It stems from the uncertaintyof the resistor values in the ampliﬁers used tomatch the signal ranges with the ADC inputs.

325

7.2. Quality assurance
A full quality assurance program has been
applied to the ABCD3TA ASICs at the following
stages: qualifying good dice on wafers as described in
the previous section,

 checking for infant mortality in ASICs assembled onto hybrids,

 monitoring radiation resistance on a sampling
7.1.2.5. I/O signals tests. We test the propertiesof ABCD3TA input or output signals by using test
vectors, stimulating the calibration signal andvarying the test conditions. We test the phases of
the input signals relative to the input clock byscanning their delays. Setup and hold timerequirements for inputs are veriﬁed in this way.
We test the phases of the output signals, relative tothe input clock, by scanning the delay for the data
receiving register latching clock and using themeasurements of the signal propagation times inthe system. We vary the swing of the input
differential signals to measure the minimal working value. We vary the thresholds of the window
comparators, placed after differential operational
ampliﬁers, to measure the swing of the output
differential signals. Finally, we vary the duty cyclesof the input clocks from 40% to 60% to ascertain
the stability of the chip performance against theclock shape variation.
7.1.2.6. Test specification. The test speciﬁcation
requires that chips pass the digital tests at
frequencies of 40 and 50 MHz and simultaneously
at digital voltages between 3.8 and 4.2 V. All chipchannels must respond to the calibration pulses.
We further select on the following criteria:

 channel noise and the average chip noise, the average chip gain,
 the trim DAC linearity,
 the average trim DAC ranges for a chip, channel offset,
 threshold DAC linearity,
 bias and shaper current DACs linearity,
 the chip power consumption.

basis, as these are destructive tests.
7.2.1. Infant mortality
A long duration test was performed for
ABCD3TA chips assembled on hybrids. The aimof this test was to catch infant mortality problems
in the ASICs. The test was therefore performed at
the ﬁrst stage where it was feasible and practicaland where replacing ASICs was still possible. The
test consisted of a long duration run at elevatedtemperature, initially for 90 h at a temperature of
55 1C, measured on the hybrid.
7.2.2. Radiation hardness quality assuranceWith respect to total ionising dose a ﬁrst step ofquality assurance procedure was radiation hardness veriﬁcation performed at the foundry as partof the acceptance criteria. Ten milliradian (SiO2)
radiation tests were done on a sampling basis tocontrol radiation hardness stability and to statistically measure the process capability to satisfy
radiation sensitive parameter drift tables as givenin the DMILL electrical speciﬁcation document.
Each production lot was controlled according to
the sampling plan deﬁned by the in-house procedure. After irradiation, in case one parameter
exhibited larger drift or greater absolute value
than expected, a deeper analysis was performed
and, when failure was conﬁrmed, wafers were
rejected.
Since some radiation effects are associated withparticular circuit conﬁgurations, in addition to thefoundry tests of the process control monitors, theABCD3TA chips have been checked for radiation
resistance on a sampling basis. From eachproduction lot four chips have been sampled
randomly from four different wafers and irra-

ARTICLE IN PRESS
326

F. Campabadal et al. / Nuclear Instruments and Methods in Physics Research A 552 (2005) 292–328

diated with X-rays. After irradiation the chips
were tested for digital functionality and power
consumption of the digital part.
In order to determine the speed margin of thedigital part, the complete digital test procedures
were run for a clock frequency of 50 MHz at
different values of the power supply voltage. Fig.
22 shows the minimum power supply voltage
required for correct digital operation at 50 MHz
clock frequency for samples irradiated with a doseof 10 Mrad at a high dose rate of 36 krad/min. The
measurements were performed immediately after
irradiation before any annealing took place. The
continuous shaded area at the bottom of the plotshows the minimum power supply voltages for
those lots before irradiation. One can see that for amajority of production lots there is a signiﬁcantsafety margin with respect to the nominal power
supply voltage of 4 V and clock frequency of
40 MHz. Only two lots that showed an increase of
the minimum Vdd above 4.5 V after irradiation
have been rejected.
High dose rate X-ray irradiation was performed
to screen for anomalous increase of the power
consumption in the digital part of the chip causedby radiation. The source of this current has been
identiﬁed as a leakage current between neighbouring NMOS devices. Detailed study of the nature ofthis leakage current showed that (i) this current
does not inﬂuence at all the functionality and the
speed of the digital circuitry and (ii) it anneals witha relatively short time constant of about 30 days at

a temperature of 25 1C. Based on the study of longterm annealing, a maximum excess current allowed
after high dose rate X-ray irradiation has been set
at 120 mA.
In a ﬁrst step, a sample chip per lot wasirradiated at the vendor facility with a dose of
10 Mrad in 3 h and power consumption of the chipmeasured. If the result complied with the limit, theproduction lot was accepted. If the result exceeded
the limit, additional irradiation was done and if
the high current was conﬁrmed the whole lot was
rejected. This was performed by the vendor on all
lots prior to being shipped and was in addition to
the normal irradiation of process control structures that the vendor was performing on each lot
to certify the lot as radiation-hard.
In the second step, the power consumption wasmonitored in the chips that were sampled andirradiated for monitoring radiation resistance withrespect to digital functionality. Fig. 23 shows theexcess currents measured immediately after X-ray
irradiation with a dose of 10 Mrad for the same
samples as shown in Fig. 22. No lot has been
rejected due to the post radiation excess digitalcurrent.
To screen for unexpected process changes thatwould inﬂuence the radiation hardness withrespect to bulk damage, three chips from each lot
were irradiated with neutrons in a reactor to a
ﬂuence of 2  1014 n/cm2 of 1 MeV equivalent
neutrons. Irradiations were done with chips
mounted on hybrids. Full functionality of chips

Fig. 22. Minimum power supply voltage for correct digital
operation at 50 MHz clock frequency for samples irradiatedwith a dose of 10 Mrad. Minimum power supply voltage before
the irradiation is shown as continuous grey area.

Fig. 23. Excess current measured after 10 Mrad X-ray irradiation for ABCD3TA chips from selected wafers of consecutive
production lots. Data is presented without annealing.

ARTICLE IN PRESS
F. Campabadal et al. / Nuclear Instruments and Methods in Physics Research A 552 (2005) 292–328

was tested before and after irradiation with a focus
on performance of the analogue part.

8. Summary
The ABCD3TA ASIC developed for binary
readout of silicon strip detectors meets therequirements of the ATLAS SCT. The performance of the chip has been demonstrated throughextensive evaluation of the prototypes as well as in
the series production of the SCT detector modules.
For a fully populated module built with silicon
strip detectors of a total length of 12.8 cm, an ENC
below 1500 electrons rms and a noise occupancy
below 1  10 4 are systematically achieved. After
irradiation up to full SCT doses, an ENC below
1800 electrons rms and a noise occupancy below
5  10 4 are maintained.
The required threshold uniformity in the amplitude discriminator has been achieved by implementing threshold trimming on a channel basis.
The equivalent input threshold spread is lower bya factor of 5 compared to the ENC and it does notcontribute signiﬁcantly to the noise occupancy andefﬁciency loss.
The chip design meets the timing requirements
achieving discriminator timewalk below 16 ns,
which ensures correct associations of all hits abovea threshold of 1 fC with the corresponding beamcrossing number.
The ABCD3TA chip design provides data
storage for the ﬁrst level trigger latency, data
derandomising and zero suppression so that only
addresses of hit strips are transmitted to the off
detector electronics. As a result the module
comprising 1536 readout channels is read out via
two optical links at 40 MHz rate. The readout
control logic is built into the ABCD3TA architecture so that no additional control chip isrequired on the module.
The ABCD3TA design has been optimised for
low power consumption. The chip operating at thenominal bias conditions and the nominal clock
frequency of 40 MHz typically dissipates a powerof 3.1 mW/channel. This number complies with therequirements of the SCT power supply and coolingsystems.

327

The radiation resistance of the ABCD3TA
design has been veriﬁed in numerous dedicatedirradiation tests speciﬁc for ionisation effects,
displacement damage and SEE. Moreover, theradiation resistance has been monitored on asampling basis through the entire production.
The results of the irradiation tests and radiation
hardness quality assurance program ensure thatthe chips will maintain required performance
during the lifetime of the ATLAS experiment.
The production and acceptance testing of
270,000 chips has been completed yielding a
sufﬁcient number of chips to build the SCT for
the ATLAS experiment.

Acknowledgements
We acknowledge the support of the funding
authorities of the collaborating institutes including
the Australian Research Council; the Australian
Department of Education, Science and Training;
the Polish State Committee for Scientiﬁc Research;
the Ministry of Education, Science and Sport of
the Republic of Slovenia; the Spanish National
Programme for Particle Physics; the Particle
Physics and Astronomy Research Council of theUnited Kingdom; the United States Departmentof Energy; and the United States National Science
Foundation.

References[1] ATLAS Inner Detector Technical Design Report, CERN/
LHCC/97-17, ATLAS TDR 5, vol. 2, 30 April 1997, pp.
427–439.
[2] T. Dubbs, et al., The development of the CAFE-P/CAFEM bipolar chips for the ATLAS Semiconductor Tracker,
in: Proceedings of the Fifth Workshop on Electronics for
LHC Experiments (CERN 99-09—CERN/LHCC/99-33),
CERN, 1999, pp. 123–127.
[3] D. Campbell, et al., The development of a rad-hard CMOS
chip for the binary readout of the ATLAS Semiconductor
Tracker, in: Proceedings of the Fifth Workshop on
Electronics for LHC Experiments (CERN 99-09—
CERN/LHCC/99-33), CERN, 1999, pp. 15–26.
[4] DMILL, a Mixed Analog-Digital Radiation-Hard Technology for High Energy Physics Electronics, RD29 Status
Report, CERN/LHCC/97-15, CERN, 1997.

ARTICLE IN PRESS
328

F. Campabadal et al. / Nuclear Instruments and Methods in Physics Research A 552 (2005) 292–328[5] W. Dabrowski, J. Kaplon, R. Szczygiel, Nucl. Instr. andMeth. A 421 (1999) 303.
[6] W. Dabrowski, et al., Progress in Development of theReadout chip for ATLAS Semiconductor Tracker, in:Proceedings of the Sixth Workshop on Electronics for
LHC Experiment (CERN 2000-010—CERN/LHCC/2000041), CERN, 2000, pp. 115–119.
[7] W. Dabrowski, et al., IEEE Trans. Nucl. Sci. NS-47 (2000)
1843.
[8] D. Robinson, et al., Nucl. Instr. and Meth. A 485 (2002)
84.
[9] F. Anghinolﬁ, et al., Development of Front-End Electronics for Silicon Strip Detectors Using the DMILLBiCMOS Rad-Hard Process, in: Proceedings of the Second
Workshop on Electronics for LHC Experiments (CERN/
LHCC/96-39), CERN, 1996, pp. 483–487.
[10] T. Kondo, et al., Nucl. Instr. and Meth. A 485 (2002) 27.
[11] M. Glaser, et al., Nucl. Instr. and Meth. A 426 (1999) 72.
[12] M. Ravnik, R. Jeraj, Nucl. Sci. Eng. 145 (2003) 145.
[13] G. Lindström, et al., Nucl. Instr. and Meth. A 466 (2001)
308.
[14] Y. Unno, et al., IEEE Trans. Nucl. Sci. NS-49 (2002)
1868.
[15] E. Krištof, Proceedings of the conference Nuclear Energy
in Central Europe ‘98, Terme Čatež, Slovenia, 1998, pp.
43–48.
[16] D. Žontar, et al., Nucl. Instr. and Meth. A 426 (1999) 51.
[17] A.M. Ougang, et al., IEEE Trans. Nucl. Sci. NS-37 (1990)
2219.
[18] I. Mandić, et al., IEEE Trans. Nucl. Sci. NS-51 (2004)
1752.

[19] P.S. Winokur, et al., IEEE Trans. Nucl. Sci. NS-41 (1994)
538.
[20] E.W. Enlow, et al., IEEE Trans. Nucl. Sci. NS-38 (1991)
1991.
[21] R.D. Schrimpf, IEEE Trans. Nucl. Sci. NS-43 (1996) 787.
[22] S.C. Witczak, et al., IEEE Trans. Nucl. Sci. NS-43(1996) 3151.
[23] O. Flament, et al., IEEE Trans. Nucl. Sci. NS-45 (1998)
1420.
[24] S.C. Witczak, et al., IEEE Trans. Nucl. Sci. NS-44(1997) 1989.
[25] M. Ullán, et al., IEEE Trans. Nucl. Sci. NS-49 (2002)
1106.
[26] Minimizing Dosimetry Errors in Radiation Hardness
Testing of Silicon Electronic Devices Using Co-60 Sources,
Annual Book Of ASTM Standards, American Society For
Testing And Materials (ASTM), E 1249–93, 1993.
[27] Standard Guide for Ionizing Radiation (Total Dose)
Effects Testing of Semiconductor Devices, Annual Book
Of ASTM Standards, American Society For Testing And
Materials (ASTM), F 1892–98, 1998.
[28] Application of Thermoluminiscence-Dosimetry (TLD)
Systems for Determining Absorbed Dose in RadiationHardness Testing of Electronic Devices, Annual Book Of
ASTM Standards, American Society For Testing And
Materials (ASTM), E668–97, 1997.
[29] M. Huhtinen, F. Faccio, Nucl. Instr. and Meth. A 450(2000) 155.
[30] L. Eklund, et al., Nucl. Instr. and Meth. A 515 (2003) 415.
[31] F. Anghinolﬁ, et al., IEEE Trans. Nucl. Sci. NS-49 (2002)
1080.