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TPS55340
SLVSBD4C – MAY 2012 – REVISED JANUARY 2015

TPS55340 Integrated 5-A Wide Input Range Boost/SEPIC/Flyback DC-DC Regulator
1 Features

3 Description

•
•
•
•
•
•
•
•
•
•

The TPS55340 is a monolithic, nonsynchronous,
switching regulator with integrated 5-A, 40-V powerswitch. The device can be configured in several
standard switching-regulator topologies, including
boost, SEPIC, and isolated flyback. The device has awide input voltage range to support applications with
input voltage from multicell batteries or regulated
3.3-V, 5-V, 12-V, and 24-V power rails.

1

•
•
•

Internal 5-A, 40-V Low-Side MOSFET Switch
2.9-V to 32-V Input Voltage Range±0.7% Reference Voltage
0.5-mA Operating Quiescent Current
2.7-µA Shutdown Supply Current
Fixed Frequency Current Mode PWM Control
Frequency Adjustable From 100 kHz to 1.2 MHz
Synchronization Capability to External Clock
Adjustable Soft-Start Time
Pulse Skipping for Higher Efficiency at Light
Loads
Cycle-by-Cycle Current Limit, Thermal Shutdown,
and UVLO Protection
QFN-16 (3-mm × 3-mm) and HTSSOP-14
Packages With PowerPAD™
Wide –40°C to 150°C Operating TJ Range

2 Applications
•
•
•
•
•

3.3-V, 5-V, 12-V, 24-V Power Conversion
Boost, SEPIC, and Flyback Topologies
Thunderbolt Port, USB Type-C Power Delivery,
Power Docking for Tablets and Portable PCs
Industrial Power Systems
ADSL Modems

The TPS55340 regulates the output voltage withcurrent mode PWM (pulse width modulation) control,and has an internal oscillator. The switchingfrequency of PWM is set by either an external resistor
or by synchronizing to an external clock signal. The
user can program the switching frequency from100 kHz to 1.2 MHz.
The device features a programmable soft-start
function to limit inrush current during start-up and hasother built-in protection features including cycle-bycycle overcurrent limit and thermal shutdown.
The TPS55340 is available in a small 3-mm × 3-mm
16-pin QFN as well as 14-pin HTSSOP packages
with PowerPAD for enhanced thermal performance.
The 5-A, 40-V TPS55340 boost converter in the
HTSSOP-14 package is pin-to-pin compatible withthe 3-A, 40-V TPS61175 and it extends the maximum
input voltage from 18 V to 32 V.
Device Information(1)PART NUMBER
TPS55340

PACKAGEBODY SIZE (NOM)

HTSSOP (14)5.00 mm × 4.40 mm

WQFN (16)3.00 mm × 3.00 mm(1) For all available packages, see the orderable addendum atthe end of the data sheet.

Typical Application (Boost)L

VIN

Efficiency vs Output Current

D

100

VOUT

95
CO

TPS55340
VIN

SW

EN

SW

FREQ

SW

SS

FB

RSH

COMP

PGND

SYNC

PGND

AGND

PGND

CSS
RFREQ

RC
CC

90
Efficiency (%)

CI

85
VOUT = 24 V
fSW = 600 kHz

80
75
70
65

RSL

VIN = 15 V
VIN = 12 V
VIN = 5 V

60
55
50

0

0.4

0.8
1.2
1.6
Output Current (A)

2

2.4
G031

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

TPS55340
SLVSBD4C – MAY 2012 – REVISED JANUARY 2015

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Table of Contents
1
2
3
4
5
6

Features .................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions ......................... 3
Specifications......................................................... 4
6.1
6.2
6.3
6.4
6.5
6.6

7

Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 4
Electrical Characteristics........................................... 5
Typical Characteristics .............................................. 6

Detailed Description .............................................. 9
7.1 Overview ................................................................... 9
7.2 Functional Block Diagram ......................................... 9

7.3 Feature Description................................................... 9
7.4 Device Functional Modes........................................ 12

8

Application and Implementation ........................ 13
8.1 Application Information............................................ 13
8.2 Typical Applications ................................................ 13

9 Power Supply Recommendations...................... 26
10 Layout................................................................... 26
10.1 Layout Guidelines ................................................. 26
10.2 Layout Example .................................................... 26
10.3 Thermal Considerations ........................................ 27

11 Device and Documentation Support ................. 28
11.1 Trademarks ........................................................... 28
11.2 Electrostatic Discharge Caution ............................ 28
11.3 Glossary ................................................................ 28

12 Mechanical, Packaging, and Orderable
Information ........................................................... 28

4 Revision History
Changes from Revision B (October 2012) to Revision C•

Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1

Changes from Revision A (October 2012) to Revision B
•

Page

Page

Corrected the pin numbers to the QFN-16 Package drawing ................................................................................................ 3

Changes from Original (May 2012) to Revision A

Page

•

Added PWP package ............................................................................................................................................................. 1•

Added HTSSOP-14 package to FEATURES ......................................................................................................................... 1•

Added 14-pin HTSSOP package to DESCRIPTION .............................................................................................................. 1•

Added paragraph to end of DESCRIPTION ........................................................................................................................... 1•

Added PWP package to PIN ASSIGNMENTS ....................................................................................................................... 3•

Added PWP package to PIN FUNCTIONS ............................................................................................................................ 3•

Added HTSSOP package to THERMAL INFORMATION ...................................................................................................... 4

2

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SLVSBD4C – MAY 2012 – REVISED JANUARY 2015

5 Pin Configuration and Functions

16

15

14

14-PinHTSSOP Package(Top View)

PGND

NC

SW

SW

16-PinQFN Package(Top View)

13

SW

1

12

PGND

VIN

2

11

PGND

EN

3

10

NC

PowerPAD

4
5

6

7

8

AGND

COMP

FB

9

SYNC

SS

FREQ

SW

1

14

SW

2

13

PGND

VIN

3

12

PGND

EN

4

11

NC

SS

5

10

FREQ

SYNC

6

9

FB

AGND

7

8

COMP

PowerPAD

PGNDPin Functions
PIN
NAME

DESCRIPTION

QFN-16

HTSSOP-14

AGND

6

7

Signal ground of the IC.

COMP

7

8

Output of the transconductance error amplifier. An external RC network connected to this pin
compensates the regulator feedback loop.

EN

3

4

Enable pin. When the voltage of this pin falls below the enable threshold for more than 1 ms,
the IC turns off.

FB

8

9

Error amplifier input and feedback pin for positive voltage regulation. Connect to the center tapof a resistor divider to program the output voltage.

FREQ

9

10

Switching frequency program pin. An external resistor connected between the FREQ pin and
AGND sets the switching frequency.
Reserved pin that must be connected to ground.

NC

10, 14

11

11, 12, 13

12, 13, 14

Power ground of the IC. It is connected to the source of the internal power MOSFET switch.

PowerPAD——

The PowerPAD should be soldered to the AGND. If possible, use thermal vias to connect tointernal ground plane for improved power dissipation.

SS

4

5

Soft-start programming pin. A capacitor between the SS pin and AGND pin programs soft-starttiming.

SW

1, 15, 16

1, 2

SW is the drain of the internal power MOSFET. Connect SW to the switched side of the boost
or SEPIC inductor or the flyback transformer.

SYNC

5

6

Switching frequency synchronization pin. An external clock signal can be used to set theswitching frequency between 200 kHz and 1.0 MHz. If not used, this pin should be tied to
AGND.

VIN

2

3

The input supply pin to the IC. Connect VIN to a supply voltage between 2.9 V and 32 V. It is
acceptable for the voltage on the pin to be different from the boost power stage input.

PGND

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6 Specifications
6.1 Absolute Maximum Ratings
over operating temperature range (unless otherwise noted) (1)Supply voltages on pin VIN (2)Voltage on pin EN

(2)

MIN

MAX

UNIT

–0.3

34

V

–0.3

34

V

Voltage on pins FB, FREQ, and COMP (2)

–0.3

3

V

Voltage on pin SS (2)

–0.3

5

V
V

Voltage on pin SYNC

(2)

–0.3

7

Voltage on pin SW (2)

–0.3

40

V

Operating junction temperature

–40

150

°C

Storage temperature, Tstg

–65

150

°C

(1)
(2)

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal

6.2 ESD Ratings
VALUE
V(ESD)(1)(2)

Electrostatic discharge

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)±2000

Charged device model (CDM), per JEDEC specification JESD22-C101, allpins (2)

±500

UNIT
V

JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions
MIN

NOM

MAX

UNIT

VIN

Input voltage range

2.9

32

V

VOUT

Output voltage range

VIN

38

V

VEN

EN voltage range

0

32

V

VSYN

External switching frequency logic input range

0

5

V

TA

Operating free-air temperature

–40

125

°C

TJ

Operating junction temperature

–40

150

°C

QFN
(16 PINS)HTSSOP(14 PINS)UNIT

6.4 Thermal Information
TPS55340
THERMAL METRIC (1)RθJA

Junction-to-ambient thermal resistance

43.3

43.2

RθJC(top)

Junction-to-case (top) thermal resistance

38.7

33.3

RθJB

Junction-to-board thermal resistance

14.5

28.3

ψJT

Junction-to-top characterization parameter

0.4

1.3

ψJB

Junction-to-board characterization parameter

14.5

28.1

RθJC(bot)

Junction-to-case (bottom) thermal resistance

3.5

3.9

(1)

4

°C/W

For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

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6.5 Electrical Characteristics
VIN = 5 V, TJ = –40°C to 150°C, unless otherwise noted. Typical values are at TA = 25°C.
PARAMETERTEST CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLY CURRENT
VIN

Input voltage range

IQ

Operating quiescent current into VIN

Device nonswitching, VFB = 2 V

2.9
0.5

32

ISD

Shutdown current

EN = GND

2.7

VUVLO

Undervoltage lockout threshold

VIN falling

Vhys

Undervoltage lockout hysteresis

V
mA

10

µA

2.5

2.7

V

120

140

160

mV

ENABLE AND REFERENCE CONTROL
VEN

EN threshold voltage

EN rising input

0.9

1.08

1.30

V

VEN

EN threshold voltage

EN falling input

0.74

0.92

1.125

V

VENh

EN threshold hysteresis

REN

EN pulldown resistor

Toff

Shutdown delay, SS discharge

VSYNh

SYN logic high voltage

VSYNl

SYN logic low voltage

0.16
400
EN high to low

950

V
1600

1.0

kΩ
ms

1.2

V
0.4

V

VOLTAGE AND CURRENT CONTROL
1.204

1.229

1.254

1.220

1.229

1.238

TA = 25°C

1.6

20

VFB = VREF + 200 mV, VCOMP = 1 V

42µA

VFB = VREF – 200 mV, VCOMP = 1 V

42

µA

VREF

Voltage feedback regulation voltage

IFB

Voltage feedback input bias current

Isink

COMP pin sink current

Isource

COMP pin source current

VCCLP

COMP pin clamp voltage

VCTH

COMP pin threshold

Gea

Error amplifier transconductance

Rea

Error amplifier output resistance

10

MΩ

fea

Error amplifier crossover frequency

500

kHz

TA = 25°C

High Clamp, VFB = 1 V

3.1

Low Clamp, VFB = 1.5 V

0.75

Duty cycle = 0%

360

nA

V

1.04
240

V

V
440

µS

FREQUENCY
fSW

Frequency

Dmax

Maximum duty cycle

VFREQ

FREQ pin voltage

Tmin_onMinimum on pulse width

RFREQ = 480 kΩ

75

94

RFREQ = 80 kΩ

460

577

130
740

RFREQ = 40 kΩ

920

1140

1480

VFB = 1.0 V, RFREQ = 80 kΩ

89%

96%

kHz

1.25

V

RFREQ = 80 kΩ

77ns

VIN = 5 V

60

110

VIN = 3 V

70

120

POWER SWITCHRDS(ON)N-channel MOSFET on-resistance

ILN_NFET

N-channel leakage current

VDS = 25 V, TA = 25°C

2.1

mΩ
µA

OCP and SS
ILIM

N-channel MOSFET current limit

D = DmaxISS

Soft-start bias current

VSS = 0 V

5.25

6.6

7.75

A

6

µA

THERMAL SHUTDOWN
Tshutdown

Thermal shutdown threshold

165

°C

Thysteresis

Thermal shutdown threshold
hysteresis

15°C

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6.6 Typical Characteristics
VIN = 5 V, TA = 25°C (unless otherwise noted)
8
Current Limit Threshold (A)Transconductance (µA/V)

400

380

360

340

320

7
6
5
4
3
2

300
−50

−25

0

25
50
75
Temperature (°C)

100

125

1
−50

150

Figure 1. Error Amplifier Transconductance vs Temperature

125

150
G002

VIN = 3 V
Resistance (mΩ)

Voltage Reference (V)

100

100

1.228

1.226

1.224

80
60
40

VIN = 12 V

VIN = 5 V25
5075
Temperature (°C)

100

20

1.22
−50

−25

0

25
50
75
Temperature (°C)

100

125

0
−50

150

−25

0

G003

Figure 3. Feedback Voltage Reference vs Temperature
1600

1400

1400

1200
Frequency (kHz)

1000
800
600
400

30

100
Resistance (kΩ)

500

150
G004

1000
800
600
RFREQ = 40 kΩ
RFREQ = 80 kΩ
RFREQ = 480 kΩ

400
200

200

125

Figure 4. RDS(ON) vs Temperature

1200
Frequency (kHz)

25
50
75
Temperature (°C)

120

1.222

0
−50

G005

Figure 5. Frequency vs FREQ Resistance

60

Figure 2. Switch Current Limit vs Temperature

1.23

0

−25

G001

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−25

0

25
50
75
Temperature (°C)

100

125

150
G006

Figure 6. Frequency vs Temperature

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Typical Characteristics (continued)
VIN = 5 V, TA = 25°C (unless otherwise noted)
400

700

350

600

RFREQ = 80 kΩ

500

Frequency (kHz)Frequency (kHz)

300
250
200
150

400

200

100

100

50

0
−50

0
0

5

10

15
20
25
30
Voltage on the VIN Pin (V)

35

40

0

25
50
75
Temperature (°C)

100

125

150
G007

Figure 8. Nonfoldback Frequency vs Foldback Frequency
2.7

3.5
3

Input Voltage (V)

2.66

2.5
COMP Pin Clamp HighCOMP Pin Clamp Low

2
1.5

2.62
UVLO Start
UVLO Stop
2.58

2.54

1
0.5
−50

−25

0

25
50
75
Temperature (°C)

100

125

2.5
−50

150

0

25
50
75
Temperature (°C)

100

125

150
G009

Figure 10. Input Voltage UVLO vs Temperature

1.3

100
RFREQ = 80 kΩ

EN Voltage Rising
EN Voltage Falling
Maximum Duty Cycle (%)

1.2
1.1
1
0.9
0.8
0.7
−50

−25

G008

Figure 9. COMP Clamp Voltage vs Temperature

Enable Voltage (V)

−25

D006

Figure 7. Minimum Switching Frequency for Quick Recovery
from Frequency Foldback

COMP Voltage (V)Non-Foldback
Foldback

300

99
98
97
96
95

−25

0

25
50
75
Temperature (°C)

100

125

150

94
−50

G010

Figure 11. Enable Voltage vs Temperature

−25

0

25
50
75
Temperature (°C)

100

125

150
G011

Figure 12. Maximum Duty Cycle vs Temperature

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Typical Characteristics (continued)
VIN = 5 V, TA = 25°C (unless otherwise noted)
100

8
RFREQ = 80 kΩ
7
Shutdown Current (µA)

Minimum On Time (ns)

95
90
85
80
75

6
5
4
3
2

70
−50

−25

0

25
50
75
Temperature (°C)

100

125

1
−50

150

−25

0

25
50
75
Temperature (°C)

G012

Figure 13. Minimum On-Time vs Temperature

100

125

150
G013

Figure 14. Shutdown Current vs Temperature

2.1

Supply Current (mA)

1.8
1.5
Switching
Non-Switching

1.2
0.9
0.6
0.3
−50

−25

0

25
50
75
Temperature (°C)

100

125

150
G014

Figure 15. Supply Current vs Temperature

8

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7 Detailed Description
7.1 Overview
The TPS55340 device is a monolithic, nonsynchronous, switching regulator with an integrated 5-A, 40-V powerswitch. The device can be configured in several standard switching-regulator topologies, including boost, SEPIC,
and isolated flyback. The device has a wide input voltage range to support applications with input voltage frommulticell batteries or regulated 3.3-V, 5-V, 12-V, and 24-V power rails.

7.2 Functional Block Diagram

VIN

SW

FB
Error
Amp

EN

1.229V
Reference

COMP
PWM
Control

Ramp
Generator

Gate
DriverLossless
Current Sense

S

Oscillator

SS

FREQ

SYNC

AGND

PGND

7.3 Feature Description
7.3.1 Operation
If designed as a boost converter, the TPS55340 device regulates the output with current-mode, pulse-widthmodulation (PWM) control. The PWM control circuitry turns on the switch at the beginning of each oscillator clock
cycle. The input voltage is applied across the inductor and stores the energy as inductor current ramps up.
During this portion of the switching cycle, the load current is provided by the output capacitor. When the inductor
current reaches a threshold level set by the error amplifier output, the power switch turns off and the external
Schottky diode is forward biased to allow the inductor current to flow to the output. The inductor transfers stored
energy to replenish the output capacitor and supply the load current. This operation repeats every switchingcycle. The duty cycle of the converter is determined by the PWM control comparator which compares the error
amplifier output and the current signal. The oscillator frequency is programmed by the external resistor orsynchronized to an external clock signal.

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Feature Description (continued)
A ramp signal from the oscillator is added to the inductor current ramp to provide slope compensation. Slope
compensation is required to avoid subharmonic oscillation that is intrinsic to peak-current mode control at duty
cycles higher than 50%. If the inductor value is too small, the internal slope compensation may not be adequate
to maintain stability.
The PWM control feedback loop regulates the FB pin to a reference voltage through a transconductance error
amplifier. The output of the error amplifier is connected to the COMP pin. An external RC compensation network
connected to the COMP pin is chosen for feedback loop stability and optimum transient response.
7.3.2 Switching Frequency
The switching frequency is set by a resistor (RFREQ) connected to the FREQ pin of the TPS55340. The
relationship between the timing resistance RFREQ and frequency is shown in the Figure 5. Do not leave this pin
open. A resistor must always be connected from the FREQ pin to ground for proper operation. The resistor value
required for a desired frequency can be calculated using Equation 1.
RFREQ(kΩ) = 57500 × ƒsw(kHz)–1.03(1)

For the given resistor value, the corresponding frequency can be calculated by Equation 2.
ƒsw(kHz) = 41600 × RFREQ(kΩ)–0.97(2)

The TPS55340 switching frequency can be synchronized to an external clock signal that is applied to the SYNC
pin. The required logic levels of the external clock are shown in Recommended Operating Conditions. The
recommended duty cycle of the clock is in the range of 10% to 90%. A resistor must be connected from the
FREQ pin to ground when the converter is synchronized to the external clock and the external clock frequency
must be within ±20% of the corresponding frequency set by the resistor. For example, if the frequency
programmed by the FREQ pin resistor is 600 kHz, the external clock signal should be in the range of 480 kHz to
720 kHz.
With a switching frequency below 280 kHz (typical) after the TPS55340 enters frequency foldback as describedin Overcurrent Protection and Frequency Foldback, if a load remains when the overcurrent condition is removed,
then the output may not recover to the set value. For the output to return to the set value, the load must be
removed completely or the TPS55340 power cycled with the EN pin or VIN pin. Select a nominal switchingfrequency of 350 kHz for quicker recovery from frequency foldback.
7.3.3 Overcurrent Protection and Frequency Foldback
The TPS55340 provides cycle-by-cycle overcurrent protection that turns off the power switch once the inductor
current reaches the overcurrent limit threshold. The PWM circuitry resets itself at the beginning of the next switch
cycle. During an overcurrent event, the output voltage begins to drop as a function of the load on the output.
When the FB voltage through the feedback resistors drops lower than 0.9 V, the switching frequency is
automatically reduced to 1/4 of the normal value. Figure 8 shows the nonfoldback frequency with an 80-kΩ timing
resistor and the corresponding foldback frequency. The switching frequency does not return to normal until theovercurrent condition is removed and the FB voltage increases above 0.9 V. The frequency foldback feature isdisabled during soft-start.
7.3.3.1 Minimum On-Time and Pulse Skipping
The TPS55340 PWM control system has a minimum PWM pulse width of 77 ns (typical). This minimum on-time
determines the minimum duty cycle of the PWM for any set switching frequency. When the voltage regulation
loop of the TPS55340 requires a minimum on-time pulse width less than 77 ns, the IC enters pulse skipping
mode. In this mode, the device will hold the power switch off for several switching cycles to prevent the output
voltage from rising above the desired regulated voltage. This operation typically occurs in light load conditions
when the PWM operates in discontinuous conduction mode. Pulse skipping increases the output ripple as shownin Figure 22.
7.3.4 Voltage Reference and Setting Output Voltage
An internal voltage reference provides a precise 1.229-V voltage reference at the error amplifier noninverting
input. To set the output voltage, select the FB pin resistor RSH and RSL according to Equation 3.

10

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Feature Description (continued)æRö
VOUT = 1.229 V ´ ç SH + 1÷
è R SLø

(3)

7.3.5 Soft-Start
The TPS55340 has a built-in soft-start circuit which significantly reduces the start-up current spike and output
voltage overshoot. When the IC is enabled, an internal bias current source (6 µA, typical) charges a capacitor(CSS) on the SS pin. The voltage at the capacitor clamps the output of the internal error amplifier that determines
the peak current and duty cycle of PWM controller. Limiting the peak switch current during start-up with a slow
ramp on the SS pin will reduce in-rush current and output voltage overshoot. Once the capacitor reaches 1.8 V,
the soft-start cycle is completed and the soft-start voltage no longer clamps the error amplifier output. When the
EN is pulled low for at least 1 ms, the IC enters the shutdown mode and the SS capacitor is discharged througha 5-kΩ resistor to prepare for the next soft-start sequence.
7.3.6 Slope Compensation
The TPS55340 has internal slope compensation to prevent subharmonic oscillations. The sensed current slopeof boost converter can be expressed as Equation 4:V
Sn = IN ´ RSENSE
L(4)

The slope compensation dv/dt can be calculated using Equation 5.
Se =0.32 V RFREQ
16 ´ (1 - D) ´ 6 pF+

0.5 mA
6 pF(5)In a converter with current mode control, in addition to the output voltage feedback loop, the inner current loop
including the inductor current sampling effect as well as the slope compensation on the small signal response
should be taken into account, which can be modeled as seen in Equation 6:
He(s) =

1
éæ
ù
Se ö
÷ ´ (1 - D) - 0.5 ús ´ êç 1 +
Sn ÷ø
êëçè
úû
1+
+
fsw

s2

(p ´ fsw )

2

where
•
•
•

RSENSE (15 mΩ) is the equivalent current sense resistor.
RFREQ is timing resistor used to set frequency.
D is the duty cycle.

(6)

NOTE
If Sn << Se, the converter operates in voltage mode control rather than current mode
control, and Equation 6 is no longer valid.
7.3.7 Enable and Thermal Shutdown
The TPS55340 enters shutdown when the EN voltage is less than 0.68 V (minimum) for more than 1 ms. In
shutdown, the input supply current for the device is less than 10 µA (maximum). The EN pin has an internal
950-kΩ pulldown resistor to disable the device if the pin is floating.
An internal thermal shutdown turns off the device when the junction temperature exceeds 165°C (typical). The
device will restart when the junction temperature drops by 15°C.

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Feature Description (continued)
7.3.8 Undervoltage Lockout (UVLO)
An undervoltage lockout circuit prevents mis-operation of the device at input voltages below 2.5 V (typical). Whenthe input voltage is below the UVLO threshold, the device remains off and the internal power MOSFET is turned
off. The UVLO threshold is set below minimum operating voltage of 2.9 V to ensure that a transient VIN dip will
not cause the device to reset. For the input voltages between UVLO threshold and 2.9 V, the device tries tooperate, but the electrical specifications are not assured.

7.4 Device Functional Modes
7.4.1 Operation With VIN < 2.9 V (Minimum VIN)
The TPS55340 device operates with input voltages above 2.9 V. The typical UVLO voltage (turning off) is 2.5 V
and the TPS55340 device remains off at input voltages lower than that point. For the input voltages between
UVLO threshold and 2.9 V, the device tries to operate, but the electrical specifications are not ensured.
7.4.2 Operation With EN Control
The enable rising-edge threshold voltage is 1.08 V (typical) with 0.16 V hysteresis (typical). With the EN pin held
below the turn-off voltage, the device is disabled and switching is inhibited. The IC quiescent current is reducedin this state. When the input voltage is above the UVLO threshold and the EN pin voltage increases above therising edge threshold, the device becomes active. Switching enables and the soft-start sequence initiates. The
TPS55340 device starts at the soft-start time determined by the external soft-start capacitor.
7.4.3 Operation at Light Loads
The device is designed to operate in high-efficiency, pulse-skipping mode under light load conditions.
Discontinuous-conduction-mode (DCM) operation initiates when the switch current falls to 0 A. During DCM
operation, the catch diode stops conducting when the switch current falls to 0 A. The switching node (the SWpin) waveform takes on the characteristics of DCM operation as shown in Figure 21. As the load decreases
further and when the voltage-regulation loop of TPS55340 device requires an on-time pulse width less than theminimum PWM pulse width of 77 ns (typical), the IC enters pulse-skipping mode. In this mode, the device holds
the power switch off for several switching cycles to prevent the output voltage from rising too much above thedesired regulated voltage.

12

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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

8.1 Application Information
The TPS55340 device can be configured in several standard switching-regulator topologies, including boost,
SEPIC, and isolated flyback. For example, the device configured in boost topology is widely used to convert alower dc voltage to a higher dc voltage with a maximum available switching current of 5.25 A. Use the following
design procedure to select component values for a boost converter design or SEPIC design for the TPS55340
device. Alternately, use the WEBENCH® software to generate a complete design. The WEBENCH software uses
an iterative design procedure and accesses a comprehensive database of components when generating adesign. This section presents a simplified discussion of the design process.

8.2 Typical Applications
The following section provides a step-by-step design approach for configuring the TPS55340 as a voltage
regulating boost converter, as shown in Figure 16. When configured as SEPIC or flyback converter, a different
design approach is required. A design example of SEPIC converter is provided in the next section.
8.2.1 Boost Converter

100 pF

Figure 16. Boost Converter Application Schematic
8.2.1.1 Design Requirements
For this design example, use the parameters listed in Table 1. These parameters are typically determined at thesystem level.

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Table 1. Design Parameters
PARAMETER

VALUE

Output voltage

24 V

Input voltage

5 V to 12 V

Maximum output current

800 mA

Transient response 50% load step (ΔVOUT = 3%)

960 mV

Output voltage ripple (0.5% of VOUT)

120 mV

8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Selecting the Switching Frequency (R4)

The first step is to decide on a switching frequency for the regulator. There are tradeoffs to consider for a higher
or lower switching frequency. A higher switching frequency allows for lower valued inductor and smaller output
capacitors leading to the smallest solution size. A lower switching frequency will result in a larger solution size
but better efficiency. The user will typically set the frequency for the minimum tolerable efficiency to avoid
excessively large external components.
A switching frequency of 600 kHz is a good trade-off between efficiency and solution size. The appropriate
resistor value is found from the resistance versus frequency graph of Figure 5, or calculated using Equation 1.
R4 is calculated to be 78.4 kΩ and the nearest standard value resistor of 78.7 kΩ is selected. A resistor must beplaced from the FREQ pin to ground, even if an external oscillation is applied for synchronization.
8.2.1.2.2 Determining the Duty Cycle

The input-to-output voltage conversion ratio of the TPS55340 is limited by the worst case maximum duty cycle of
89% and the minimum duty cycle which is determined by the minimum on-time of 77 ns and the switchingfrequency. The minimum duty cycle can be estimated with Equation 7. With a 600-kHz switching frequency theminimum duty cycle is 4%.
DPS = TON min × ƒsw(7)

The duty cycle at which the converter operates is dependent on the mode in which the converter is running. If theconverter is running in DCM, where the inductor current ramps to zero at the end of each cycle, the duty cycle
varies with changes of the load much more than it does when running in continuous conduction mode (CCM). In
CCM, where the inductor maintains a minimum dc current, the duty cycle is related primarily to the input andoutput voltages as computed below. Assume a 0.5-V drop VD across the Schottky rectifier. At the minimum inputof 5 V, the duty cycle will be 80%. At the maximum input of 12 V, the duty cycle is 51%.
+ VD - VINV
D = OUTVOUT + VD(8)At light loads the converter will operate in DCM. In this case the duty cycle is a function of the load, input andoutput voltages, inductance, and switching frequency as computed below. This can be calculated only after an
inductance is chosen in the following section. While operating in DCM with very light load conditions, the duty
cycle demand will force the TPS55340 to operate with the minimum on-time. The converter will then begin pulse
skipping which can increase the output ripple.
D=

2 ´ (VOUT + VD - VIN ) ´ L ´ IOUT ´ ¦ SW
VIN

(9)

All converters using a diode as the freewheeling or catch component have a load current level at which theytransit from DCM to CCM. At this point the inductor current just falls to zero during the off-time of the powerswitch. At higher load currents, the inductor current does not fall to zero and diode and switch current assume a
trapezoidal wave shape as opposed to a triangular wave shape. The load current boundary between
discontinuous conduction and continuous conduction can be found for a set of converter parameters as follows:

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For loads higher than the result of Equation 10, the duty cycle is given by Equation 8. For loads less than the
results of Equation 10, the duty cycle is given by Equation 9. For Equation 7 through Equation 10, the variable
definitions are as follows:• VOUT is the output voltage of the converter in V.
• VD is the forward conduction voltage drop across the rectifier or catch diode in V.
• VIN is the input voltage to the converter in V.
• IOUT is the output current of the converter in A.
• L is the inductor value in H.
• ƒSW is the switching frequency in Hz.
Unless otherwise stated, the design equations that follow assume that the converter is running in CCM which
typically results in a higher efficiency for the power levels of this converter.
8.2.1.2.3 Selecting the Inductor (L1)

The selection of the inductor affects steady-state operation as well as transient behavior and loop stability. These
factors make it the most important component in power regulator design. There are three important inductor
specifications: inductor value, dc resistance and saturation current. Considering inductor value alone is notenough. Inductor values can have ±20% tolerance with no current bias. When the inductor current approaches
saturation level, the effective inductance can fall to a fraction of the zero current value.
The minimum value of the inductor should be able to meet the inductor current ripple (ΔIL) requirement at worst
case. In a boost converter, maximum inductor current ripple occurs at 50% duty cycle. For the applications where
duty cycle is always smaller or larger than 50%, Equation 12 should be used with the duty cycle closest to 50%
and corresponding input voltage to calculate the minimum inductance. For applications that must operate with
50% duty cycle when input voltage is somewhere between the minimum and the maximum input voltage,
Equation 13 should be used. KIND is a coefficient that represents the amount of inductor ripple current relative tothe maximum input current (IINDC = ILavg). The maximum input current can be estimated with Equation 11, withan estimated efficiency based on similar applications (ηEST). The inductor ripple current will be filtered by theoutput capacitor. Therefore, choosing high inductor ripple currents will impact the selection of the output
capacitor because the output capacitor must have a ripple current rating equal to or greater than the inductor
ripple current. In general, the inductor ripple value (KIND) is at the discretion of the designer. However, thefollowing guidelines may be used.
For CCM operation, it is recommended to use KIND values in the range of 0.2 to 0.4. Choosing KIND closer to 0.2
results in a larger inductance value, maximizes the potential output current of the converter and minimizes EMI.
Choosing KIND closer to 0.4 results in a smaller inductance value, a physically smaller inductor, and improved
transient response, but potentially worse EMI and lower efficiency. Using an inductor with a smaller inductancevalue may result in the converter operating in DCM. This reduces the maximum output current of the boost
converter, causes larger input voltage and output voltage ripple, and reduced efficiency. For this design, choose
KIND = 0.3 and a conservative efficiency estimate of 85% with the minimum input voltage and maximum output
current. Equation 12 is used with the maximum input voltage because this corresponds to duty cycle closest to
50%. The maximum input current is estimated at 4.52 A and the minimum inductance is 7.53 µH. A standard
value of 10 µH is chosen.
IINDC =

VOUT ´ IOUT
hEST ´ VIN min

(11)

VIN
D
LO min ³´
IINDC ´ KIND ¦ SW

LO min ³(VOUT + VD )IINDC ´ KIND´

, D ≠ 50%, VIN with D closest to 50%(12)1, D=50%4 ´ ¦ SW

(13)

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After choosing the inductance, the required current ratings can be calculated. The inductor will be closest to its
ratings with the minimum input voltage. The ripple with the chosen inductance is calculated with Equation 14.
The RMS and peak inductor current can be found with Equation 15 and Equation 16. For this design the current
ripple is 663 mA, the RMS inductor current is 4.52 A, and the peak inductor current is 4.85 A. It is generally
recommended for the peak inductor current rating of the selected inductor be 20% higher to account fortransients during powerup, faults, or transient load conditions. The most conservative approach is to specify an
inductor with a saturation current greater than the maximum peak current limit of the TPS55340. This helps to
avoid saturation of the inductor. The chosen inductor is a Würth Elektronik 74437368100. It has a saturation
current rating of 12.5 A, RMS current rating of 5.2 A, and typical DCR of 27.0 mΩ.
V min Dmax
DIL = IN
´
LO
¦ SW
(14)

IL rms =æ DIL ö÷
è 12 ø

(IINDC )2 + ç

2

(15)

DI
IL peak = IINDC + L
2(16)

The TPS55340 has built-in slope compensation to avoid subharmonic oscillation associated with current mode
control. If the inductor value is too small, the slope compensation may not be adequate, and the loop can be
unstable.
8.2.1.2.4 Computing the Maximum Output Current

The overcurrent limit for the integrated power MOSFET limits the maximum input current and thus the maximum
input power for a given input voltage. Maximum output power is less than maximum input power due to power
conversion losses. Therefore, the current limit setting, input voltage, output voltage, and efficiency can all change
maximum current output (IOUTmax). The current limit clamps the peak inductor current; therefore, the ripple has
to be subtracted to derive maximum dc current. Decreasing the KIND or designing for a higher efficiency will
increase the maximum output current. This can be evaluated with the chosen inductance or the chosen KIND.
This should be evaluated with the minimum input voltage and minimum peak current limit (ILIM) of 5.25 A.
DIL ö
æ
æ K
ö
VIN min ´ ç ILIM ´ hEST VIN min ´ ILIM ´ ç 1 - IND ÷ ´ hEST
÷
2 ø
2 ø
è
è
IOUT max =
=
VOUT
VOUT

(17)

In this design with a 5-V input boosted to a 24-V output and a 10-μH inductor with an assumed Schottky forward
voltage of 0.5 V and estimated efficiency of 85%, the maximum output current is 871 mA. With the 12-V input
and increased estimated efficiency of 90%, the maximum output current increases to 2.13 A. This circuit wasevaluated to its maximum output currents with both the minimum and maximum input voltage.
8.2.1.2.5 Selecting the Output Capacitors (C8, C9, C10)

At least 4.7 µF of ceramic-type X5R or X7R capacitance is recommended at the output. The output capacitanceis mainly selected to meet the requirements for the output ripple (VRIPPLE) and voltage change during a loadtransient. Then the loop is compensated for the output capacitor selected. The output capacitance should bechosen based on the most stringent of these criteria. The output ripple voltage is related to the capacitance andequivalent series resistance (ESR) of the output capacitor. Assuming a capacitor with zero ESR, the minimum
capacitance needed for a given ripple can be calculated by Equation 18. If high ESR capacitors are used, it willcontribute additional ripple. The maximum ESR for a specified ripple is calculated with Equation 19. ESR ripple
can be neglected for ceramic capacitors but must be considered if tantalum or electrolytic capacitors are used.
The minimum ceramic output capacitance needed to meet a load transient requirement can be estimated by the
Equation 20. Equation 21 can be used to calculate the RMS current that the output capacitor needs to support.
Dmax ´ IOUT
COUT ³¦ SW ´ VRIPPLE(18)

æ
Dmax ´ IOUT öç VRIPPLE ÷¦ SW ´ COUT ø
ESR £ è
DIL
16

(19)

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DITRAN2 ´ p ´ ¦BW ´ DVTRAN

ICOrms = IOUT

(20)

Dmax
(1 - Dmax )(21)

Using Equation 18 for this design, the minimum output capacitance for the specified 120-mV output ripple is
8.8 µF. For a maximum transient voltage change (ΔVTRAN) of 960 mV with a 400-mA load transient (ΔITRAN) anda 6-kHz control loop bandwidth (fBW) with Equation 20, the minimum output capacitance is 11.1 µF. The moststringent criteria is the 11.1 µF for the required load transient. Equation 21 gives a 1.58-A RMS current in the
output capacitor. The capacitor should also be properly rated for the desired output voltage.
Care must be taken when evaluating ceramic capacitors that derate under dc bias, aging, and ac signal
conditions. For example, larger form factor capacitors (in 1206 size) have self-resonant frequencies in the rangeof converter switching frequency. Self-resonance causes the effective capacitance to be significantly lower. The
dc bias can also significantly reduce capacitance. Ceramic capacitors can lose as much as 50% of thecapacitance when operated at the rated voltage. Therefore, allow a margin in selected capacitor voltage rating toensure adequate capacitance at the required output voltage. For this example, three 4.7-µF, 50-V, 1210 X7R
ceramic capacitors are used in parallel leading to a negligible ESR. Choosing 50-V capacitors instead of 35-V
reduces the effects of dc bias and allows this example circuit to be rated for the maximum output voltage rangeof the TPS55340.
8.2.1.2.6 Selecting the Input Capacitors (C2, C7)

At least 4.7 µF of ceramic input capacitance is recommended. Additional input capacitance may be required tomeet ripple and/or transient requirements. High-quality ceramic, type X5R or X7R are recommended to minimize
capacitance variations over temperature. The capacitor must also have an RMS current rating greater than the
maximum RMS input current of the TPS55340 calculated with Equation 22. The input capacitor must also be
rated greater than the maximum input voltage. The input voltage ripple can be calculated with Equation 23.
DI
ICIrms = L
12
(22)
DIL
Vripple=+ DIL ´ RCINI
4 ´ ¦ SW ´ CIN(23)In the design example, the input RMS current is calculated to be 191 mA. The chosen input capacitor is a 10-µF,
35-V, 1210 X7R with 3-mΩ ESR. Although one with a lower voltage rating can be used, a 35-V rated capacitor
was chosen to limit the affects of dc bias and to allow the circuit to be rated for the entire input range of the
TPS55340. The input ripple is calculated to be 30 mV. An additional 0.1-µF, 50-V, 0603 X5R is located close to
the VIN and GND pins for extra decoupling.
8.2.1.2.7 Setting Output Voltage (R1, R2)

To set the output voltage in either DCM or CCM, select the values of R1 and R2 according to the following
equations:æ R1 ö
VOUT = 1.229 V ´ ç+ 1÷
è R2 ø
(24)

æ V
ö
R1 = R2 ´ ç OUT - 1÷
è 1.229 Vø(25)Considering the leakage current through the resistor divider and noise decoupling into the FB pin, an optimum
value for R2 is around 10 kΩ. The output voltage tolerance depends on the VFB accuracy and the tolerance of R1
and R2. In this example with a 24-V output using Equation 25, R1 is calculated to 185.3 kΩ. The nearest
standard value of 187 kΩ is used.
8.2.1.2.8 Setting the Soft-start Time (C7)

Choose the appropriate capacitor to set soft-start time and avoid overshoot. Increasing the soft-start time
reduces the overshoot during startup. A 0.047-µF ceramic capacitor is used in this example.
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8.2.1.2.9 Selecting the Schottky Diode (D1)

The high switching frequency of the TPS55340 demands high-speed rectification for optimum efficiency. Ensurethat the average and peak current ratings of the diode exceed the average output current and peak inductor
current. In addition, the reverse breakdown voltage of the diode must exceed the regulated output voltage. The
diode must also be rated for the power dissipated which can be calculated with Equation 26.
PD = VD × IOUT

(26)

In this conservative design example, the diode is chosen to be rated for the maximum output current of 2.13 A.
During normal operation with 800-mA output current and assuming a Schottky diode drop of 0.5 V, the diodemust be capable of dissipating 400 mW. The recommended minimum ratings for this design are a 40-V, 3-A
diode. However, to improve the flexibility of this design, a Diodes Inc B540-13-F in an SMC package is used with
voltage and current ratings of 40 V and 5 A.
8.2.1.2.10 Compensating the Control Loop (R3, C4, C5)

The TPS55340 requires external compensation which allows the loop response to be optimized for eachapplication. The COMP pin is the output of the internal error amplifier. An external resistor R3 and ceramic
capacitor C4 are connected to the COMP pin to provide a pole and a zero, shown in Figure 16. This pole andzero, along with the inherent pole and zero of a boost converter, determine the closed-loop frequency response.
This is important for converter stability and transient response. Loop compensation should be designed for theminimum operating voltage.
The following equations summarize the loop equations for the TPS55340 configured as a CCM boost converter.
They include the power stage output pole (ƒOUT) and the right-half-plane zero (ƒRHPZ) of a boost converter
calculated with Equation 27 and Equation 28, respectively. When calculating ƒOUT, it is important to include thederating of ceramic output capacitors. In the example with an estimated 10.2-µF capacitance, these frequencies
are calculated to be 980 kHz and 22.1 kHz, respectively. The dc gain (A) of the power stage is calculated with
Equation 27 and is 39.9 dB in this design. The compensation pole (ƒP) and zero (ƒZ) generated by R3, C4, andinternal transconductance amplifier are calculated with Equation 30 and Equation 31, respectively.
Most CCM boost converters will have a stable control loop if fZ is set slightly above ƒP through proper sizing of
R3 and C4. A good starting point is C4 = 0.1 µF and R3 = 2 kΩ. Increasing R3 or reducing C4 increases theclosed-loop bandwidth, and therefore improves the transient response. Adjusting R3 and C4 in the opposite
direction increases the phase and gain margin of the loop, which improves loop stability. It is generally
recommended to limit the bandwidth of the loop to the lower of either 1/5 of the switching frequency ƒSW or 1/3
the RHPZ frequency, ƒRHPZ shown in Equation 28. The spreadsheet tool located in the TPS55340 product folder
at www.ti.com can also be used to aid in compensation design.
2¦ OUT »
2p ´ ROUT ´ COUT
(27)
æ V ö
R
¦RHPZ » OUT ´ ç IN ÷
2p ´ L è VOUT ø

2
(28)

VIN
1.229
1
A=
´ Gea ´ 10MW ´´ ROUT ´
VOUT
VOUT ´ RSENSE
21
2p ´ 10MW ´ C4
1¦Z =2p ´ R3 ´ C4¦
¦ co1 = SW5¦
¦ co2 = RHPZ
3
¦P =

18

(29)
(30)
(31)
(32)
(33)

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Where
• COUT is the equivalent output capacitor (COUT= C8 + C9 + C10)
• ROUT is the equivalent load resistance (VOUT/IOUT)• Gea is the error amplifier transconductance located in Electrical Characteristics• RSENSE (15 mΩ, typical) is the sense resistor in the current control loop• ƒco1 and ƒco2 are possible bandwidths.
An additional capacitor from the COMP pin to GND (C5) can be used to place a high-frequency pole in thecontrol loop. This is not always necessary with ceramic output capacitors. If a nonceramic output capacitor isused, there is an additional zero (fZESR) in the control loop which can be calculated with Equation 35. The valueof C5 and the pole created by C5 can be calculated with Equation 36 and Equation 34, respectively. Finally, if
more phase margin is needed, an additional zero (fZFF) can be added by placing a capacitor (CFF) in parallel withthe top feedback resistor R1. It is recommended to place the zero at the target cross-over frequency or higher.
The feed-forward capacitor also adds a pole at a higher frequency. The recommended value of CFF can becalculated with Equation 37.
1¦P2 =2p ´ R3 ´ C5
(34)
1
¦ ZESR »2p ´ RESR ´ COUT
(35)

RESR ´ COUT
R3
1
CFF =
C5 =

2p ´ R1´ ¦ ZFF ´

(36)

VREF
VOUT

(37)

where RESR is the ESR of the output capacitor.
If a network measurement tool is available, the most accurate compensation design can be achieved following
this procedure. The power stage frequency response is first measured using a network analyzer at the minimum
5-V input and maximum 800-mA load. This measurement is shown in Figure 17. In this design only one pole andone zero are used, so the maximum phase increase from the compensation will be 180 degrees. For a60-degree phase margin, the power stage phase must be –120 degrees at its lowest point. Based on the target
6-kHz bandwidth, the measured power stage gain, KPS(fBW), is 24.84 dB and the phase is –110.3 degrees.
0

60
Gain
Phase

Gain (dB)

40

−30

20

−60

0

−90

−20

−120

−40

−150

−60
100

1k

10k
Frequency (Hz)

−180
100k
G016

Figure 17. Power Stage Gain and Phase of the Boost Converter
R3 is then chosen to set the compensation gain to be the reciprocal of the power stage gain at the target
bandwidth using Equation 38. C4 is then chosen to place a zero at 1/10 the target bandwidth with Equation 39.
In this case, R3 is calculated to be 2.56 kΩ and the nearest standard value of 2.55 kΩ is used. C4 is calculated
at 0.104 µF and the nearest standard value of 0.100 µF is used. Although not necessary because this designuses all ceramic capacitors, a 100-pF capacitor is selected for C5 to add a high-frequency pole at a frequency
100 times the target bandwidth.
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1

R3 =

K P S (¦ B W )
æ
ö
20
R2
ç G ea ´÷´ 10ç÷(R1 + R 2 )
è
ø
1
C4 =
¦
2p ´ R3 ´ BW
10

(38)

(39)

8.2.1.3 Application Curves
100
95

VOUT (ac coupled) = 500mV/div

Efficiency (%)

90
85
80
75

IOUT = 200mA/div

70
65
60
VIN = 5 V
VIN = 12 V

55
50

0

0.4

0.8
1.2
Output Current (A)1.6

2Time - 1ms/div

G017

Figure 18. Efficiency vs Output Current
IL = 1A/div

Figure 19. Load Transient Response
IL = 1A/div

VOUT (ac coupled) = 100mV/div

VOUT (ac coupled) = 10mV/div

SW = 20V/div

SW = 20V/div

Time - 1ms/div
Figure 21. DCM PWM Operation

Time - 1ms/div
Figure 20. CCM PWM Operation
VIN = 1V/div

IL = 200mA/div

EN = 2V/div

VOUT (ac coupled) = 20mV/div
SW = 10V/div

SW = 20V/div
VOUT = 10V/div

Time - 50ms/div
Figure 22. Pulse Skipping

20

Time - 500ms/div
Figure 23. Start-Up

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180

60
40

120

20

60

0

0

Phase (°)

Gain (dB)

IOUT = 800 mA

−60

−20
5 V Gain
5 V Phase
15 V Gain
15 V Phase

−40
−60
100

−120

1k

10k
Frequency (Hz)

−180
100k
G023

Figure 24. Closed-Loop Gain and Phase of the Boost Converter

8.2.2 SEPIC Converter

Lb
TP4

VIN

La
VIN
6-18V

12V, 1A
1

TP5
49.9
TP2

VIN

86.6k
SYNC
SYNC

1

TP3

Not Populated

Figure 25. SEPIC Converter Application Schematic
8.2.2.1 Design Requirements
The parameters listed in Table 2 are used for a SEPIC converter design. These calculations are performed only
for CCM operation. The use of a coupled inductor is assumed.
Table 2. Design Parameters
PARAMETER

VALUE

Output voltage

12 V

Input voltage

6 V to 18 V, 12 V nominal

Maximum output current

1A

Transient response 50% load step (ΔVOUT = 4%)

480 mV

Output voltage ripple (0.5% of VOUT)

60 mV
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8.2.2.2 Detailed Design Procedure
8.2.2.2.1 Selecting the Switching Frequency (R4)A 500-kHz switching frequency (ƒSW) is selected for this design. Using Equation 1, R4 is calculated and thenearest standard value of 95.3 kΩ is used.
8.2.2.2.2 Duty Cycle

The duty cycle of a SEPIC converter is calculated with Equation 40. With the 6-V minimum input voltage, theduty cycle is 68%; and with the 18-V maximum input voltage, the duty cycle is 41%.
VOUT + VD
D=
VOUT + VD + VIN(40)
8.2.2.2.3 Selecting the Inductor (L1)With an estimated 85% efficiency, the input current is calculated with Equation 9 to be 2.35 A. With KIND of 0.3
and the maximum 18-V input voltage, the minimum inductance is calculated to be 10.5 µH using Equation 41.
The nearest standard value of 12 µH is used. As mentioned previously, this equation assumes a coupledinductor is used.
VIN max´ Dmin
L³
2 ´ ¦ SW ´ IINDC ´ KIND
(41)
The inductor ripple current is recalculated to be 615 mA with Equation 42. The peak current is calculated to be
3.69 A. The typical current limit is used as the saturation rating for the inductor used. The RMS current for La isapproximately the average input current of 2.35 A. The RMS current for Lb is approximately the output current of
1 A. For this design, a CoilCraft MSD1260-123 is used with 6.86-A saturation, 74-mΩ DCR, and 3.12-A RMS
current rating for one winding.
V max´ Dmin
DIL = IN2 ´ ¦ SW ´ L(42)
DI ö æDI öæIL peak = ILa peak + ILb peak = ç IINDC + L ÷ + ç IOUT + L ÷
2 ø è
2 ø
è

(43)

8.2.2.2.4 Calculating the Maximum Output Current

The maximum output current with the minimum input voltage 6 V, chosen inductance 12 µH, 5.25-A minimum
current limit, and estimated 85% efficiency is calculated to be 1.47 A using Equation 44.
(ILIM - DIL )(ILIM - IINDC ´ KIND )IOUT max =
=
æ
ö æ
ö
VOUT
VOUT
+ 1÷ ç
+ 1÷
ç
V
min
V
min
´
h
´
h
EST
EST
è IN
ø è INø
(44)
8.2.2.2.5 Selecting the Output Capacitors (C8, C9, C10)

To meet the 60-mV ripple specification, the minimum output capacitance is calculated to be 22.5 µF with
Equation 45. This design uses ceramic output capacitors and the effects of ESR are ignored. To meet thetransient response of 500 mA with less than 480-mV voltage change and a 7-kHz control loop bandwidth, theminimum output capacitance is calculated to be 23.7 µF using Equation 46. The RMS current is calculated with
Equation 22 to be 1.44 A. The output capacitors used in this design are 3 × 22 µF, 25 V, X7R 1210 ceramic
capacitors. With voltage derating, the effective total output capacitance is estimated to be 30.4 µF.
Dmax ´ IOUT
COUT ³¦ SW ´ VRIPPLE(45)

COUT ³22

DITRAN
2p ´ ¦BW ´ DVTRAN(46)

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8.2.2.2.6 Selecting the Series Capacitor (C6)The series capacitor is chosen to limit the ripple current to 5% of the maximum input voltage. Using Equation 47
the minimum capacitance is 1.5 µF. Using Equation 48 the RMS current is calculated to be 1.63 A. A 2.2-µF
ceramic capacitor in a 1206 package is selected.
IOUT ´ Dmax
CP ³
0.05 ´ VIN max ´ ƒSW(47)

ICPrms = IINDC ´(1 - Dmax)
Dmax

(48)

8.2.2.2.7 Selecting the Input Capacitor (C2, C7)

Based on the minimum 4.7-µF ceramic recommended for the TPS55340, a 10-µF X7R input capacitor is usedwith an additional 0.1 µF placed close to the VIN and GND pins. With an estimated 6-µF capacitance after
voltage derating, the input ripple voltage is calculated to be 39.9 mV using Equation 49. The RMS current of the
input capacitance is calculated to be 0.177 A with Equation 50.
DIL
VIripple =4 ´ ¦ SW ´ CIN(49)

ICIrms =

DIL
12

(50)

8.2.2.2.8 Selecting the Schottky Diode (D1)The selected diode must have a minimum breakdown voltage (VBR) calculated with Equation 51 which is 30.5 V
in this design. The average current rating is recommended to be greater than the maximum output current. With
the maximum 18-V input, average current is calculated to be 2.6 A using Equation 17. The package must also becapable of handling the power dissipation. With an estimated 0.5-V forward voltage, power dissipation is
calculated with Equation 26 to be 500 mW. Diodes Inc B340B is chosen with a 40-V, 3-A rating in an SMB
package.
VBR = VO + VINmax + VF

(51)

8.2.2.2.9 Setting the Output Voltage (R1, R2)

With R2 fixed at 10 kΩ using Equation 25 the nearest standard value of 86.6 kΩ is chosen for R1.
8.2.2.2.10 Setting the Soft-start Time (C3)

The recommended 0.047-µF soft-start capacitor is used.
8.2.2.2.11 MOSFET Rating Considerations

In a SEPIC converter the MOSFET must be rated to handle the sum of the input and output voltages. In thisdesign with the maximum input voltage of 18 V and output voltage of 12 V, the FET will see approximately 30 V.
A 10% tolerance is recommended to account for any ringing. The 40-V rating of the TPS55340 power MOSFET
comfortably satisfies this requirement.
8.2.2.2.12 Compensating the Control Loop (R3, C4)This design was compensated by measuring the frequency response of the power stage at the lowest input
voltage of 6 V and choosing the components for the desired bandwidth. The lowest right half plane zero (ƒRHPZ)
is calculated to be 36.7 kHz with Equation 52. Using the recommendation to limit the bandwidth to 1/3 of ƒRHPZ,
the maximum recommended is 12.2 kHz.
VOUT
IOUT
¦RHPZ =2æ D ö
2´ p´L ´ç÷ç (1 - D ) ÷
è
ø
(52)

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This design also uses only one pole and one zero. To achieve approximately 60 degrees of phase margin, thepower stage phase must be no lower than approximately –120 degrees at the desired bandwidth. To ensure astable design, R3 was initially set to 1 kΩ and C4 was 1 µF. Figure 26 shows the measurement of the powerstage. At 7 kHz the power stage has a gain of 19.52 dB and phase of –118.1 degrees.
180
6 V Input Gain
6 V Input Phase

40

120
60

0

0

−20

−60

−40

−120

Gain (dB)

20

−60
100

1k

10k

Phase (°)

60

−180
100k

Frequency (Hz)G025

Figure 26. SEPIC Power Stage Gain and PhaseAs there are no changes in the transconductance amplifier, the equations used to calculate the external
compensation components in a boost design can be used in the SEPIC design. Using the maximum Gea from theelectrical specification of 440 µmho, Equation 38 calculates the nearest standard value of R3 to be 2.37 kΩ.
Using Equation 39, C4 is calculated to the nearest standard value of 0.1 µF.

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8.2.2.3 Application Curves
100
95

IOUT = 500mA/div

Efficiency (%)

90
85

VOUT (ac coupled) = 200mV/div

80
75
70
65
VIN = 6 V
VIN = 12 V
VIN = 18 V

60
55
50

0

0.2

0.4
0.6
0.8
Output Current (A)11.2Time - 500ms/div
Figure 28. Load Transient Response

G026

Figure 27. Efficiency vs Output Current

SW = 10V/div

VIN = 2V/div

ILb = 1A/div

EN = 2V/div
SW = 20V/div

ILa = 1A/div

VOUT = 5V/div
VOUT (ac coupled) = 50mV/div
Time - 1ms/div
Figure 30. Output Voltage Soft-start

60

180

40

120

20

60

0

0
−60

−20
−40
−60
100

Phase (°)

Gain (dB)Time - 2ms/div
Figure 29. CCM PWM Operation

6 V Gain
6 V Phase
18 V Gain
18 V Phase

−120

1k

10k
Frequency (Hz)

−180
100k
G030

Figure 31. Closed-Loop Gain and Phase of the SEPIC Converter

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9 Power Supply Recommendations
The device is designed to operate from an input voltage supply range between 2.9 V and 32 V. This input supply
must be well regulated. If the input supply is located more than a few inches from the TPS55340 converter
additional bulk capacitance may be required in addition to the ceramic bypass capacitors. An electrolytic
capacitor with a value of 100 μF is a typical choice.

10 Layout10.1 Layout Guidelines
As for all switching power supplies, especially those with high frequency and high switch current, printed-circuitboard (PCB) layout is an important design step. If the layout is not carefully designed, the regulator can sufferfrom instability as well as noise problems. The following guidelines are recommended for good PCB layout.
• To prevent radiation of high-frequency resonance problems, use proper layout of the high-frequency switchingpath.
• Minimize the length and area of all traces connected to the SW pin and always use a ground plane under theswitching regulator to minimize inter-plane coupling.
• The high current path, including the internal MOSFET switch, Schottky diode, and output capacitor, contains
nanosecond rise times and fall times. Keep these rise times and fall times as short as possible.
• Place the VIN bypass capacitor as close to the VIN pin and the AGND pin as possible to reduce the IC supply
ripple.
• Connect the AGND and PGND pins to thermal pad directly on the same layer.

10.2 Layout Example
LO

VI

VI
BypassCapacitor

VO

VI
High-Frequency
Bypass Capacitor

OutputFilterCapacitor

SW

SW

NC

PGND

16

15

14

13

VIN 2

11 PGND
PowerPad

CI
Bypass capacitor
for TPS55340.
Put close to Pin 2

Power Ground
12 PGNDSW 1Power Ground

OutputFilterCapacitor

EN

3

10 NC

SS

4

9
5

C(SS)

6

7

SYNC AGND COMP

FREQ
Frequency
Set
Resistor

8
FB

UVLO
Resistors

Connect to VO on the
inner or bottom layer

Compensation
Network

Feedback
Resistors
Connect to AGND on the
inner or bottom layer

Figure 32. TPS55340 Layout Example

26

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SLVSBD4C – MAY 2012 – REVISED JANUARY 201510.3 Thermal Considerations
The maximum IC junction temperature should be restricted to 150°C under normal operating conditions. This
restriction limits the power dissipation of the TPS55340. The TPS55340 features a thermally enhanced QFN
package. This package includes a PowerPAD that improves the thermal capabilities of the package. The thermal
resistance of the QFN package in any application greatly depends on the PCB layout and the PowerPAD
connection. The PowerPAD must be soldered to the analog ground on the PCB. Use thermal vias underneaththe PowerPAD to achieve good thermal performance.

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11 Device and Documentation Support
11.1 Trademarks
PowerPAD is a trademark of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.

11.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

11.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and revision ofthis document. For browser-based versions of this data sheet, refer to the left-hand navigation.

28

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PACKAGE OPTION ADDENDUM

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6-Oct-2014

PACKAGING INFORMATION
Orderable Device

Status(1)

Package Type Package Pins Package
Drawing
Qty

Eco Plan

Lead/Ball Finish

MSL Peak Temp

(2)

(6)

(3)

Op Temp (°C)

Device Marking(4/5)

TPS55340PWP

ACTIVEHTSSOP

PWP

14

90

Green (RoHS& no Sb/Br)

CU NIPDAU

Level-2-260C-1 YEAR

-40 to 150

55340

TPS55340PWPR

ACTIVEHTSSOP

PWP

14

2000

Green (RoHS& no Sb/Br)

CU NIPDAU

Level-2-260C-1 YEAR

-40 to 150

55340

TPS55340RTER

ACTIVE

WQFN

RTE

16

3000

Green (RoHS& no Sb/Br)

CU NIPDAU

Level-2-260C-1 YEAR

-40 to 150

55340

TPS55340RTET

ACTIVE

WQFN

RTE

16

250

Green (RoHS& no Sb/Br)

CU NIPDAU

Level-2-260C-1 YEAR

-40 to 150

55340

(1)

The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement thatlead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weightin homogeneous material)(3)

MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.
(6)

Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Addendum-Page 1

SamplesPACKAGE OPTION ADDENDUM

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6-Oct-2014

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS55340 :• Automotive: TPS55340-Q1• Enhanced Product: TPS55340-EP
NOTE: Qualified Version Definitions:• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects• Enhanced Product - Supports Defense, Aerospace and Medical Applications

Addendum-Page 2

PACKAGE MATERIALS INFORMATION
www.ti.com

6-Oct-2014

TAPE AND REEL INFORMATION*All dimensions are nominal

DevicePackage Package Pins
Type Drawing

SPQ

Reel
Reel
A0
Diameter Width (mm)(mm) W1 (mm)

B0
(mm)

K0
(mm)

P1
(mm)

W
Pin1
(mm) Quadrant

TPS55340PWPRHTSSOP

PWP

14

2000

330.0

12.4

6.9

5.6

1.6

8.0

12.0

Q1

TPS55340RTER

WQFN

RTE

16

3000

330.0

TPS55340RTET

WQFN

RTE

16

250

180.0

12.4

3.3

3.3

1.1

8.0

12.0

Q2

12.4

3.3

3.3

1.1

8.0

12.0

Q2

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION
www.ti.com

6-Oct-2014*All dimensions are nominal

DevicePackage Type

Package Drawing

Pins

SPQ

Length (mm)Width (mm)Height (mm)TPS55340PWPRHTSSOP

PWP

14

2000

367.0

367.0

35.0

TPS55340RTER

WQFN

RTE

16

3000

367.0

367.0

35.0

TPS55340RTET

WQFN

RTE

16

250

210.0

185.0

35.0

Pack Materials-Page 2IMPORTANT NOTICE
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