AN90003

LFPAK MOSFET thermal design guideRev. 4.1 — 22 August 2023

application note

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Content

Keywords

Thermal design, LFPAK56D, LFPAK33, LFPAK56, LFPAK88

Abstract

Thermal design guide: estimate of MOSFET power dissipation capability depending on PCB
design.

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LFPAK MOSFET thermal design guide

1. Introduction
This application note is a guide to assist design engineers in understanding the power dissipation
limits of the LFPAK family of packages. The maximum power that a MOSFET can dissipate
is considered as a function of the Printed Circuit Board (PCB) design, using some common
configurations. The application notes comprises of three main sections. The first section gives
some background on MOSFET power loss and the thermal environment. The next two sections
address separately the low power LFPAKs (LFPAK56D and LFPAK33) and the high power LFPAKs(LFPAK56 and LFPAK88).

2. MOSFET power dissipation and the design environment
During normal operation, MOSFETs can exhibit three kinds of power losses:•••

Switching losses – due to voltage and current being non-zero during the transition between the
ON and OFF states.
Conduction losses – when the device is fully on due to its on-state resistance RDSon.
Avalanche losses – if the device breakdown voltage is exceeded and an avalanche event
occurs.

The shape of the power can change depending on the nature of the load. A generalized model ofthe total power dissipated by a MOSFET is the sum of these three losses, see Equation (1).

Ptot = Psw + Pcond + Pav(1)

In addition to electrical requirements another challenge is often the harsh environment that adevice needs to operate in, particularly in terms of temperature. For instance, in automotive andindustrial applications it’s not uncommon to encounter high ambient temperature requirements,(from 85 °C up to 125 °C), this limits the amount of power that a MOSFET can safely handle.
Semiconductor devices are not the only parts to consider when dealing with high temperatures.
For instance, the PCB material FR4 has a maximum operating temperature of around 130 °C,
depending on manufacturer and chemistry, this is much lower than the limit specified for thejunction of a silicon die (175 °C).
Modern applications continue to push the limits of power MOSFETs, while searching for better andbetter performances. As a consequence thermals have become one of the most important aspectsof systems design. One way to address thermal issues is to carefully choose a device with theappropriate performances and provide a good enough path through which heat can flow freely,
avoiding any impact on the device reliability.

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LFPAK MOSFET thermal design guide2.1. Heat propagation phenomena
Heat propagates because of a temperature difference between the junction and the outside/
ambient. Propagation occurs from junction and the outside/ambient through different material, fromsolids (silicon, copper, FR4, aluminum) to fluids (surrounding air or even air pockets trapped in thesolder joints on the PCB). Heat finds a path whether it’s defined by an engineer or not. This meansthat if the path is not designed correctly then heat might get trapped and raise the temperature of
one or multiple mediums.
The physical phenomena by which heat can propagate are: conduction, convection and radiation.
Conduction

Ambient (Ta)Convection
Radiation

PCB

aaa-031985

Fig. 1.

Thermal propogation phenomena

2.1.1. Conduction
Conduction is the propagation of heat in a solid medium due to a temperature difference within
it, and it is caused by the random movement of atoms and molecules. The rate of heat flow Q is
directly proportional to the cross-section area A, temperature difference and thermal conductivity k.
It is inversely proportional to the length x of the heat path, see Equation (2).
solid medium
A
Q

T1

T2
x

Fig. 2.

Q
aaa-031976

Conduction in a solid medium

T1 - T2
Q = k · A· −x(2)

Thermal conductivity, measured as W/(mK), is a physical property of a material and defines its
ability to conduct heat. The higher its value the higher the rate of heat transfer, therefore the better
thermal conductor. From Equation 2 it can be derived that rate of heat flow is measured in W.
Therefore, heat is measured in Joule (Ws).
Table 1 lists some materials with their thermal conductivity values. Air is a very bad conductorof heat, thus a good thermal insulator. It’s thermal conductivity is 2,000 times lower than that ofsteel. Notice how thermal glue has a very low thermal conductivity of less than 2, (generic brand).
Thermal glue is not a good thermal conductor, however its main function is to create a good fit
between two surfaces that otherwise would form trapped pockets of air, which is 100 times a better
insulator than the glue itself.

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Table 1. Typical thermal conductivity values
Materialk (W/mK)

Air (not moving)

0.024

Brick

0.6

Glass

0.8

Thermal glue

1.78

Steel

50.2

Brass

109

Silicon130

Aluminium

205

Copper385

Silver406

Diamond1000

2.1.2. Convection
Convection is the transfer of heat from a solid body to a fluid due to its movement with respect
to the surface of the body, and it is promoted by a difference in temperature between the two
mediums. The fluid may be a gas (air) or a liquid.
Here the rate of heat flow depends only on surface A, temperature difference and convection
coefficient h, see Equation (3).
Tambair flowTsA

aaa-031977

Fig. 3.

Convection in free air

Q = h · A · (Ts - Tamb )(3)

The convection coefficient is not a physical property of the fluid (like the conduction coefficient)but an abstract quantity verified by experimentation. It depends on fluid density, velocity, viscosity,
turbulence and on the solid medium surface geometry.
2

The convection coefficient is measured in W/(m K). Table 2 lists some values measured in different
scenarios of free/natural and forced cooling.
Table 2. Thermal convection coefficient values
2
Flow typeh (W/m K)
Free airForced coolingGases

2 - 2025 - 300

Air

10

100

Liquids

50 - 1,000

100 - 40,000

Phase change

2,500 - 100,000

As can be seen during a phase change the convection coefficient rises dramatically up to 100,000.
This is due to the fact that during a phase change all the energy involved, and transferred to thefluid, is used to rearrange molecules structure and does not result in a temperature change.

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2.1.3. Radiation
Radiation is the propagation of heat via infrared radiation.
The main benefit of radiation is that as the ambient temperature increases, and the component
temperature with it, the heat transfer by radiation increases as well. As you can see in Equation(4), it depends on the fourth power of temperature. The radiation is bigger but not by a lot and theoverall effect is that radiation does not help a body get cooler.
T1

A

T2

Q

aaa-031978

Fig. 4.

Radiation44

Q = ε · σ ·A · (T1 - T2 )(4)

The amount of radiation is determined by the surface emissivity. Emissivity of a material ismeasured between 0 and 1. A perfect emitter is called a black body because it emits 100% of theenergy it absorbs, and is assigned an emissivity value of 1. Table 3 below gives emissivity values
for different materials.
Table 3. Typical emissivity values
Material

Emissivity coefficient (ε)

Aluminium, polished

0.05

Aluminium, oxidized

0.25Black electrical tape

0.95

Copper, polished

0.01

Copper, oxidized

0.65

Steel, oxidized

0.88

Water

0.98

A new piece of polished aluminum has emissivity of 0.05, (not good), its emissivity increases as
it oxides by 5 times. Every object emits thermal radiation, the amount of radiation that a particular
object emits as a function of wavelength looks as a bell shaped curve. Energy is emitted at all
frequencies but the major part of the emission occurs at a certain wavelength range which depends
on the source temperature. The higher the temperature the higher the frequency (lower the
wavelength), that is why we see materials change color as they heat up.
At the receiving side, for most of the surfaces, the same graph looks quite flat but to a very small
range of wavelengths at which the object absorbs all the impinging radiation. These surfaces arecalled selective surfaces, because they absorb only certain wavelengths.

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LFPAK MOSFET thermal design guide2.2. Thermal – Electrical analogy
When considering thermal propagation, classical methods of analysis may be used. These arebased on the thermal equations and thermal networks. These describe the paths through whichheat propagates through mediums or from one medium to another.
Any thermal network can be modelled by means of an electrical circuit. An analogy for every
thermal parameter can be found in the electrical domain. The respective analogues of electric
potential and current are temperature difference and rate of heat flow. Based on these it may beobserved that the thermal resistance is the ratio of temperature and rate of heat flow similarly
to how the voltage and current ratio defines the electrical resistance using Ohm’s law. The main
analogies may be seen in Table 4 below. Based on these, thermal networks can be solved using
many of the electrical theory laws such as Ohm’s and Kirchhoff’s laws. Also circuits can be
simplified by means of series and parallel resistor equivalences.
Table 4. Thermal and electrical analogous parameters
ThermalElectrical
Temperature T (°C)

Voltage V (V)Rate of heat flow Q (W)Current I (A)Thermal resistance Rth (K/W)

Resistance R (Ω)

Thermal capacitance Cth [W·s/K]

Capacitance C (A·s/V = F)

An example of a thermal circuit modelled in the electrical domain using a SPICE software may beseen in Fig. 5. Fig. 6 shows the response of this example circuit as a temperature plot, where thetransient and steady state thermal behaviour may be seen.
aaa-031984

T2

Tfinal

T2
C2

R2

I

Tamb

Tamb

time

aaa-031975

Fig. 5.

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SPICE modelFig. 6.

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LFPAK MOSFET thermal design guide2.2.1. Thermal resistance
Thermal resistance is a measure of the inertia of a material or medium towards heat flow, just likethe electrical resistance is to the movement of electrons. It is therefore a physical property of thespecific component. It is calculated as the ratio of the temperature difference between two points
and the rate of heat flow, therefore as K/W. The thermal and electrical models may be seen in the
pictures below.

Thermal model

Electrical model
V1

T1
Q
R th =

I

T1 - T2
Q

R=

T2

V1 - V2I

V2RCOND =L
k×A

RCONV =1
h×A

RRAD =

1
h R×A
aaa-031986

Fig. 7.

Thermal and electrical resistance models

Every phenomenon governing how heat flows, namely conduction, convection and radiation, has
its own thermal resistance. Each one of them depends inversely on a coefficient and surface or
cross section area of the material from where heat is generated or simply passing through. In
conduction the resistance depends directly to the length of the medium.

2.2.2. Thermal capacitance
Thermal capacitance, sometimes known also as thermal mass, is a property of a material
which represents how much heat (thermal energy) it can store in time, similar to its electricalcounterpart with electrical energy. Thermal capacitance provides also a quantity of the inertia
against temperature fluctuations, the higher the value the harder it will be to drive the stored energy
in or out.

Thermal model
Q

Electrical model

Q×t
ΔT =
C th

I
ΔV =

I×t
C

Cth = m × C p
aaa-031987

Fig. 8.

Thermal and electrical capacitance models

Thermal capacitance is typically referred to using the symbol Cth, and it’s measured as J/K. For abody of uniform composition, it can be approximated as the product of mass (m) of the body andspecific heat capacity (Cp), which is the heat capacity of a sample of the substance divided by themass of the sample.

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LFPAK MOSFET thermal design guide2.2.3. Transient and steady state thermal behavior••

Thermal transients describe temperatures which are changing, even at the end of the analysis
window. An example may be observed below in the yellow part of the junction temperature plot.
Steady state thermals describe the stable region where temperatures show minimal to nochange at all. These temperature remain unchanged with the passing of time and thus
represent the final values a system might show under constant conditions.
Tj

Transient region - Tj is still changing

Steady-state region - Tj is constanttPDt
aaa-031979

Fig. 9.

Transient and steady state thermal behavior

2.3. MOSFET steady state thermal characteristics
This section focuses on two important MOSFET thermal aspects. The junction to mounting basethermal resistance as well as the junction to ambient thermal resistance. The aim in this chapter is
to overview the two thermal paths and to show the thermal network which describes these paths.

2.3.1. Thermal resistance junction to mounting base - Rth(j-mb)
There is some confusion to why Nexperia does not state thermal resistance junction to case, Rth(jc), in its data sheets unlike its competitors. In JESD51-1, the definition of Rth(j-c) is the thermal
resistance produced when heat is transferred through the shortest path from the junction to theheat sunk surface of the case. This would be through to the mounting base of the device due to its
high thermal conductivity and surface area. Hence, it is the reason why Nexperia states Rth(j-mb) as
opposed to Rth(j-c) for standard power packages.
The thermal resistance from the MOSFET junction to its mounting base is one of the mostimportant specifications in a data sheet. This is because it is the most dominant heat path forstandard power packages, due to the large copper alloy mounting base. This is illustrated by thelarge red arrow representing heat flow in Fig. 10.

Tj
T mb

Tamb

aaa-035927

Fig. 10. Dominant thermal path from the die junction to the mounting base and ambient fora standard power packageRth(j-mb) describes the ease for heat to propagate in a one-dimensional path from the junction to
the external surface of the mounting base. This is calculated by taking the temperature difference
between junction and mounting base and dividing by the power dissipated between those two

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physical points. In doing so, it assumes that there are no other heat flow paths apart from those two
locations mentioned. In Fig. 11, the thermal resistance is represented with a simple resistor networkfrom the junction to the mounting base.
Tc

Ti

Tmb

aaa-031980

Fig. 11. Thermal path junction to mounting baseIn reality, the MOSFET and heat flow paths are 3-dimensional. Thus, one has to be aware thatRth(j-mb) and the network seen in Fig. 11, is actually an extensive 3-D parallel resistor network.
In addition, the parameter describes the thermal characteristics under steady-state conditions.
Therefore, the average power dissipation through the MOSFET should be used in order to obtainthe temperature values at various locations in the device.
The thermal resistance from junction to top-case for standard power packages is a confusingparameter to many people. It can be referred to by Rth(j-tc), Rth(j-top) or Rth(j-ctop). For the sake ofconsistency, it will be referred to by Rth(j-tc) for the remainder of this document. Nexperia receives anumber of these requests, as some would like to use the value to estimate the junction temperatureof a MOSFET. However, using the Rth(j-tc) value is unnecessary and below are some of the reasons
explaining why it is not stated on the data sheets of bottom-cooled MOSFETs.
It has already been established that the path at which heat flows from the junction to the ambientis through a parallel resistor network. As stated previously, the heat flow from the junction to themounting base is the dominant path due to the high thermal conductivity and large surface area ofthe mounting base. The surface of the top-case and the rest of the encapsulant for that matter, ismade from plastic. This material has a lower thermal conductivity and therefore a higher thermal
resistance compared to other materials in the device such as copper alloy and solder. Therefore,
heat takes longer to propagate through to the ambient via the encapsulant per unit time comparedto the large metallic mounting base. As such, it is considered to be a minor heat flow path shownby the small blue arrows in Fig. 12.

T tc

Tj
T mb

Tamb

aaa-035928

Fig. 12. Dominant and minor heat flow paths inside a MOSFET
Since the heat flow path through the top-case to the ambient is highly resistive, the power
dissipated through it can be assumed to be negligible. Thus Rth(j-tc) is not stated on the data sheets
for standard, bottom-cooled power packages.
Due to the slow propagation of heat through the top-case, it is found to be similar but slightly lower
in temperature compared to the junction at steady-state conditions. This has been verified throughvarious thermal simulations using CFD as illustrated in Table 5.

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Table 5. Percentage difference between junction temperature and top-case temperatureusing various mounting base copper areas
Mounting base area
Power input (W)
0.1 W

0.5 W

1W

10 mm x 10 mm

1.7%

2.9%

3.7%

20 mm x 20 mm

1.5%

2.8%

3.6%

30 mm x 30 mm

1.0%

2.7%

3.7%

From this data, it can be seen that the percentage difference in between junction temperature andtop-case temperature increases slightly as power input to the device increases. In addition, thereis negligible percentage difference between junction temperature and top-case temperature whenvarying the copper area that the device is mounted upon. This proves that the mounting base is thedominant path for heat to exit the device.
If one is able to use a thermocouple or a thermal camera to record the top-case temperature, thejunction temperature can be estimated with reasonable confidence as within 10 °C above thetopcase temperature. When using a thermocouple, slight differences in temperature readings may
come as a result of different wire lengths used. Also the method of attachment to the device cancause variations due to the slight heatsinking effect of the thermocouple. Therefore, the use ofa thermal camera would be the most preferred method to record the top-case temperature of abottom-cooled MOSFET.

2.3.2. Thermal resistance junction to ambient - Rth(j-a)
The thermal heat path between the MOSFET junction and the ambient encompasses paths within
the MOSFET itself as well as additional ones when a MOSFET is mounted onto a PCB. Hence,heat may spread from the junction towards the mounting base and the case. Afterwards, when theextremities of the MOSFET are reached, the heat will flow into the surroundings via the PCB or
directly from the case. These heat paths are depicted in Fig. 13.
Fig. 13 a) shows the heat moving from the junction to the mounting base and to the case top andafterwards to the ambient. Fig. 13 b) shows the heat moving from the mounting base to the PCB
and through it in order to reach the ambient.

aaa-031981

a)aaa-031982

b)Fig. 13. Thermal path junction to ambient
A simplified thermal circuit may be seen in Fig. 14. It is important to notice that the two thermal
paths from the component to the ambient are in parallel, thus improving both may be redundant.

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LFPAK MOSFET thermal design guide

Tcomponent
QPCB

Qcase

R PCB

R case-air

Tambaaa-031988

Fig. 14. Simplified Rth(j-a) thermal paths
A more cost effective method of reducing the thermal resistance between the MOSFET to thesurroundings may be to focus on one of the thermal paths and improve it in the best way possible.
Fig. 15 shows a thermal circuit which encompasses the MOSFET the PCB and the environment, it
may be observed that the three heat spreading methods are shown by individual thermal resistors.
In this particular case, the heat spreads:••••

Through conduction from the junction towards the outside of the MOSFET, represented by themounting base and the case.
From the case to the ambient the heat propagates through convection and radiation.
From the mounting base to the PCB and into it, conduction is again the main way of
propagation.
From the PCB into the environment convection and conduction are the main methods throughwhich heat propagates to the ambient, radiation is usually negligible.
DeviceMOSFET

RCONV
TC

TJ
RCOND

RRAD

PCB

Tmb

RCOND

RCOND

RCOND

RCOND

RCOND
RCONV

Junction
to mounting
base

RRAD

RCase-Air

RCONV
RRAD

RBoard

RCONV
RRAD

RCONV
RRAD

Tamb

aaa-031983

Fig. 15. Thermal circuit, MOSFET, PCB and environment
The thermal circuit seen in Fig. 15 is also represented in Fig. 1. Finally, the two thermal resistor
networks highlighted in green are also represented in Fig. 14.

2.3.3. PCB thermal limitation and the 1 Watt rule
As previously described, the junction to ambient thermal path contains the board or PCB.
This is often made from FR4 material, which from a thermal and electrical perspective is an
insulator. Moreover, planes, pours and traces of copper are also present as these provide thecircuit interconnections. Altogether we can consider them as forming the board and giving it acertain thermal characteristic called the board thermal resistance. It was found that this value is

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approximately 50-60 K/W, depending on the amount of copper, insulation layer thickness and otherfactors. Since this is specific to the materials and dimensions of a board, this limit is imposed.
Moreover, the ambient temperature in which a board operates, the thermal limitations of a system,
the FR4 temperature limit of 120 °C to 140 °C, as well as the temperature ranges within whicha board needs to function in, gives rise to a power limitation. These same dependencies can benoted from the following equations:[

Thermal resistivity −1=−
W
Thermal conductivity −
mK

[

[

[

[

[

[

[

[

mK
W

(5)

Thickness [m]mKK
Thermal resistance − = Thermal resitivity − × −(6)WW
Area [m 2][Temperature difference [K]K
Thermal resistance − = −WPower [W](7)

PCB thickness, area and thermal resistivity determine the PCB thermal resistance, given in K/W.
Hence, given a specific ambient temperature and a maximum FR4 temperature, or the system
maximum operation temperature, a ΔT is obtained.
Example: calculate the power dissipation of a MOSFET mounted on an FR4 PCB within an
automotive environment where the ambient temperature is 80 °C.
•••

The FR4 PCB material has a thermal resistance Rth(FR4 PCB) = 50 K/W
The FR4 PCB material maximum temperature (TFR4(max)) = 130 °C
The ambient temperature Tamb = 80 °C

ΔT = TFR4(max) - T(amb) = 130 °C - 80 °C = 50 °C

(8)

50 K
ΔT
P= −
= 1W
Rth(FR4 PCB) = −50 K/W(9)

Given the above ambient temperature and FR4 PCB characteristics, approximately 1 watt of power
may be dissipated in a MOSFET within this automotive environment.

2.3.4. Thermal nomenclature
Terminology surrounding thermal characterization of power MOSFETs has been revised multiple
times over the years. Regardless of these efforts, standards organizations and semiconductor
manufacturers may still use different names when referring to the same thermal parameter, or toslightly different variations of it. The terms often used to indicate one or the other type of thermal
resistance are: R and θ. In the case of junction to ambient, the Rth(j-amb) = Rθ(j-amb) = θ(j-amb).

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3. LFPAK56D and LFPAK33
3.1. Simple configuration with a single layer
In this section, we will present the maximum power dissipation results for a simple PCB
configuration using a single layer with varying copper area.
Results for the LFPAK56D and LFPAK33 packages are given, for the LFPAK56D with only one orwith both MOSFETs conducting.

3.1.1. LFPAK56D
Set-up:
•
•
•
•
•
•
•
•
•

1 layer on the top
MOSFET power dissipation is 0.1 W, 0.5 W and 1 W applied to each MOSFET
Maximum junction temperature of 175 °C
PCB material is standard FR4, 1.6 mm thickness, dimension 100 x 100 mm
Maximum PCB operating temperature of 120 °C
2Copper thickness is 2 oz./ft (70 μm)
The PCB is suspended in free air at ambient temperature of 20 °C
The simulation is carried out for conduction, convection and radiation heat transfer
There is no forced air cooling applied, i.e. only natural convection is modeled

The simplest possible PCB stack-up is that of a single top copper layer, see Fig. 16.
In this analysis, we will examine the variation in device junction temperature (Tj) as a function of the
top copper area.

Square of 100 mm

Length x

FR4Length x

Fig. 16. Copper area configuration: LFPAK56D, single top copper layer
The graph in Fig. 17 captures two important factors:••

AN90003application noteTj depends greatly on length “x” and thus copper area, the bigger the area the better thethermal performance
However, the ability of the top copper to provide heatsinking for the MOSFET shows a “law ofdiminishing returns”. In other words, we cannot keep on adding more copper area in the hope of

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LFPAK MOSFET thermal design guidecontinuing to reduce Tj. As can be seen from Fig. 17 below, Tj will plateau at around 50 °C (for0.5 W per MOSFET) no matter how much copper area we provide.
Care must be taken for Tj above 120 °C as PCB temperature directly under the transistor would beclose to the MOSFET Tj.
Tj
(°C)

180

(1) P = 2 x 0.1 W

160(2) P = 2 x 0.5 W(3) P = 2 x 1 W

140(4) PCB limit

(4)

120
100

(3)

80

(2)

60
40

(1)

20
0

0

10

20

30

40

50

60

Layer top side only, length "x" (mm)Fig. 17. Junction temperature as a function of copper side length x for LFPAK56D
An alternative to the previous approach is to look at the maximum power allowed before reaching
Tj(max) = 175 °C (MOSFET absolute max). Maximum power allowed is shown for different ambient
temperature and copper length. In this example the PCB temperature was not considered so caremust be taken for the resulting heat on the PCB.

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In Fig. 18 the maximum power for the conditions given is as follows:
Tamb = 20 °C: Max power is 2.6 W per MOSFET (2 × 2.6 W permissible in this package)
Tamb = 80 °C: Max power is 1.65 W per MOSFET (2 × 1.65 W permissible in this package)
3
Pmax
(W)
2.5

(1) Power per MOSFET, Tamb = 80 °C(2) Power per MOSFET, Tamb = 20 °C

2

(2)

1.5
(1)
1
0.5

0

0

10

20

30

40

50

60

Layer top side only, length "x" (mm)Fig. 18. Maximum permissible power dissipation as a function of copper side length x for LFPAK56D

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3.1.2. LFPAK56D only one MOSFET active at a time
In a typical half bridge application only one MOSFET conducts at a time. In the graph below,
Fig. 19, 1 W is dissipated in the left MOSFET (blue curve). We can see that 1 W dissipation in one
MOSFET is not equivalent to 0.5 W dissipation in each of the two MOSFETs (yellow curve).
180

Tj
(°C)

(1) P = 0.5 W

160(2) P = 1 W, left side(3) P = 2 x 1 W

140(4) PCB limit

(4)

120
100

(3)
(2)

80

(1)

60
40
20
0

0

10

20

30

40

50

60

Layer top side only, length "x" (mm)Fig. 19. Junction temperature as a function of copper side length x for LFPAK56D; one MOSFET conducting
As can be seen temperature is higher in the case of one MOSFET dissipating 1 W than it is with
two MOSFETs each dissipating 0.5 W. When only one MOSFET is active the second MOSFET
does not make a significant contribution to the total dissipation capability - meaning that if one
MOSFET is off the heating is not shared equally between the two. This is further explained by thethermal network shown in Fig. 21.
An alternative to the previous approach is to look at the maximum power allowed before reaching
Tj(max) = 175 °C (MOSFET absolute max). Maximum power allowed is shown for different ambient
temperature and copper length. In this example the PCB temperature was not considered so caremust be taken for the resulting heat on the PCB. In Fig. 20 the maximum power for the conditions
given is as follows:••
4

Tamb = 20 °C: Max power is 3.35 W with only left MOSFET
Tamb = 80 °C: Max power is 2.1 W with only left MOSFET(1) Power per MOSFET, Tamb = 80 °C

Pmax(2) Power per MOSFET, Tamb = 20 °C

(W)

3

(2)

2

(1)

1

0

0

10

20

30

40

50

Layer top side only, length "x" (mm)Fig. 20. Maximum power as a function of side length x for LFPAK56D; one MOSFET conducting

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LFPAK MOSFET thermal design guide
The concept of the second MOSFET half-sharing the thermal dissipation when turned off is not true
– see Fig. 21

Dual MOSFET thermal resistance configuration:
We can see that the thermal path between both MOSFETs inside the package is highly resistive(100 K/W).
Tj2

Tj1
Rth j1 to j2
100 K/W

Rth j1 to mb1
2.5 K/W

Rth j2 to mb2
2.5 K/W
Rth mb1 to mb2
50 K/W

Tmb1

Tmb2

Rth mb2 to amb

Rth mb1 to amb
30 K/W

30 K/W

Tamb

Tamb

Fig. 21. Thermal resistance configuration

3.1.3. LFPAK33
Set-up:
•
•
•
•
•
•
•
•
•

1 layer on the top
MOSFET power dissipation is 0.1 W, 0.5 W and 1 W applied in the MOSFET
Maximum junction temperature of 175 °C
PCB material is standard FR4, 1.6 mm thickness, dimension 100 x 100 mm
Maximum PCB operating temperature of 120 °C
2Copper thickness is 2 oz./ft (70 μm)
The PCB is suspended in free air at ambient temperature of 20 °C
The simulation is carried out for conduction, convection and radiation heat transfer
There is no forced air cooling applied i.e. only natural convection is modeled

The simplest possible PCB stack-up is that of a single top copper layer. In this analysis, we will
examine the variation in device junction temperature (Tj) as a function of top copper area.

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LFPAK MOSFET thermal design guide

Square of 100 mm

Length x

Length x

FR4

Fig. 22. Copper area configuration: LFPAK33, single top copper layer
The graph in Fig. 23 captures two important factors:••

Tj depends greatly on length “x” and thus copper area, the bigger the area the better thethermal performance
However, the ability of the top copper to provide heatsinking for the MOSFET shows a “law ofdiminishing returns”. In other words, we cannot keep on adding more copper area in the hope ofcontinuing to reduce Tj. As can be seen from Fig. 23 below, Tj will plateau at around 40 °C (for0.5 W per MOSFET) no matter how much copper area we provide.

Care must be taken for Tj above 120 °C as PCB temperature directly under the transistor would beclose to the MOSFET Tj.

Tj
(°C)

180

(1) P = 0.1 W

160(2) P = 0.5 W(3) P = 1 W

140(4) PCB limit

(4)

120
100
80

(3)

60

(2)

40

(1)

20
0

0

10

20

30

40

50

60

Layer top side only, length "x" (mm)Fig. 23. Junction temperature as a function of copper side length x for LFPAK33
An alternative to the previous approach is to look at the maximum power allowed before reaching
Tj(max) = 175 °C (MOSFET absolute max). Maximum power allowed is shown for different ambient
temperature and copper length. In this example the PCB temperature was not considered so caremust be taken for the resulting heat on the PCB.

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LFPAK MOSFET thermal design guideIn the graph below, Fig. 24, the maximum power for the conditions given is as follows:
Tamb = 20 °C: Max power is 3.7 W in the MOSFET
Tamb = 80 °C: Max power is 2.4 W in the MOSFET4
Pmax(W) 3.5(1) Power, Tamb = 80 °C(2) Power, Tamb = 20 °C

(2)

3
2.5

(1)

2
1.5
1
0.5
0

0

10

20

30

40

50

60

Layer top side only, length "x" (mm)Fig. 24. Maximum permissible power dissipation as a function of copper side length x for LFPAK33

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LFPAK MOSFET thermal design guide3.2. Usual configuration: 4 layers + vias
In this section, we will present the maximum power dissipation results for a PCB configuration
using 4 layers + vias for dissipation on the bottom layer, with varying copper area.
Results for the LFPAK56D and LFPAK33 packages are given, for the LFPAK56D with only one orwith both MOSFETs conducting.

3.2.1. LFPAK56D
Set-up:
•
•
•
•
•
•
•
•
•

4 layers + vias (vias number increases with the copper area with a maximum of 25 vias for eachside)
MOSFET power dissipation is 0.1 W, 0.5 W and 1 W applied to each MOSFET
Maximum junction temperature of 175 °C
PCB material is standard FR4, 1.6 mm thickness, dimension 100 x 100 mm
Maximum PCB operating temperature of 120 °C
2Copper thickness on all layers (external and internal) is 2 oz./ft (70 μm)
The PCB is suspended in free air at ambient temperature of 20 °C
The simulation is carried out for conduction, convection and radiation heat transfer
There is no forced air cooling applied i.e. only natural convection is modeled

The common PCB stack-up is 4 layers with vias under MOSFETs to create a dissipation path to theheatsink.
In this analysis, we will examine the variation in device junction temperature (Tj) as a function of top
copper area. In Fig. 25 below, we can see the vias configuration:

Square of 100 mm

Length x
vias
Length x

FR4

Fig. 25. Copper area configuration: LFPAK56D, 4 layers with vias

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Vias configuration: square vias used for ease of simulation.
Fig. 26. Sectional view: LFPAK56D
Table 6. Limitation of number of vias
X (mm)
vias configuration
minimalfootprint

2+2 vias

6

9+9 vias8

12+12 vias

10

20+20 vias

15

25+25 vias

20

25+25 vias

25

25+25 vias

30

25+25 vias

35

25+25 vias

40

25+25 vias

50

25+25 vias

Maximum numberof vias able to beinserted in the copper
surface

Vias pitch 2.5 mm
Vias side length 0.7 mm
Copper thickness 70 μm
No solder fill

25 vias maximum

The graph in Fig. 27 captures two important factors:••

Tj depends greatly on length “x” and thus copper area, the bigger the area the better thethermal performance
However, the ability of the top copper to provide heatsinking for the MOSFET shows a “law ofdiminishing returns”. In other words, we cannot keep on adding more copper area in the hopeof continuing to reduce Tj. As can be seen from the graph in Fig. 27, Tj will plateau at around
36 °C (for 0.5 W per MOSFET) no matter how much copper area we provide.

Care must be taken for Tj above 120 °C as the PCB temperature directly under the transistor would
be close to the MOSFET Tj.

Tj

180

(1) P = 2 x 0.1 W(2) P = 2 x 0.5 W

160
(°C)

(3) P = 2 x 1 W

140(4) PCB limit

(4)

120
100

(3)

80
60

(2)

40

(1)

20
0

0

10

20

30

40

50

60

Layer top side only, length "x" (mm)Fig. 27. Junction temperature as a function of copper side length x for LFPAK56D

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LFPAK MOSFET thermal design guideAn alternative to the previous approach is to look at the maximum power allowed before reaching
Tj(max) = 175 °C (MOSFET absolute max). Maximum power allowed is shown for different ambient
temperature and copper length. In this example the PCB temperature was not considered so caremust be taken for the resulting heat on the PCB.
In the graph below, Fig. 28 the maximum power for the conditions given is as follows:
Tamb = 20 °C: Max power is 5.3 W per MOSFET ( 2 × 5.3 W permissible in this package)
Tamb = 80 °C: Max power is 3.55 W per MOSFET ( 2 × 3.55 W permissible in this package)

Pmax
(W)

6

(1) Power per MOSFET, Tamb = 80 °C(2) Power per MOSFET, Tamb = 20 °C

5

(2)

4
3

(1)

2
1
0

0

10

20

30

40

50

60

Layer top side only, length "x" (mm)Fig. 28. Maximum permissible power dissipation as a function of copper side length x for LFPAK56D

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LFPAK MOSFET thermal design guide3.2.2. LFPAK56D only one MOSFET active at a time
In a typical half bridge application only one MOSFET conducts at a time. Fig. 29 below shows theresults for 1 W applied to the left MOSFET (blue curve). We can see that 1 W dissipated in one
MOSFET is not equivalent to 0.5 W dissipation in each of the two MOSFETs (yellow curve).
As can be seen temperature is higher in the case of one MOSFET conducting with 1 W than it iswith two MOSFETs each dissipating 0.5 W.

Tj
(°C)

180

(1) P = 2 x 0.5 W

160(2) P = 1 W, left side(3) P = 2 x 1W

140(4) PCB limit

(4)

120
100

(3)

80
60
40

(2)

20
0

(1)
0

10

20

30

40

50
60
Layer top side only, length "x" (mm)Fig. 29. Junction temperature as a function of copper side length x for LFPAK56D; one MOSFETAn alternative to the previous approach is to look at the maximum power allowed before reaching
Tj(max) = 175 °C (MOSFET absolute max). Maximum power allowed is shown for different ambient
temperature and copper length. In this example the PCB temperature was not considered so caremust be taken for the resulting heat on the PCB.
In Fig. 30 the maximum power for the conditions given is as follows:
•
•
7
Pmax
(W) 6

Tamb = 20 °C: Max power is 6 W with only left MOSFET
Tamb = 80 °C: Max power is 4 W with only left MOSFET(1) Power per MOSFET, Tamb = 80 °C(2) Power per MOSFET, Tamb = 20 °C

5
(2)

4
3

(1)

2
1
0

0

10

20

30

40

50

60

Layer top side only, length "x" (mm)Fig. 30. Power dissipation as a function of copper side length x for LFPAK56D; one MOSFET

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LFPAK MOSFET thermal design guideAs previously mentioned, when only one MOSFET is active the second MOSFET does not make asignificant contributution to the total dissipation capabilty – see Fig. 21.

3.2.3. LFPAK33
Set-up:
•
•
•
•
•
•
•
•
•

4 layers + vias (vias number increases with the copper area with a maximum of 25 vias for eachside)
MOSFET power dissipation is 0.1 W, 0.5 W and 1 W applied in the MOSFET
Maximum junction temperature of 175 °C
PCB material is standard FR4, 1.6 mm thickness, dimension 100 x 100 mm
Maximum PCB operating temperature of 120 °C
2Copper thickness on all layers (external and internal) is 2 oz./ft (70 μm)
The PCB is suspended in free air at ambient temperature of 20 °C
The simulation is carried out for conduction, convection and radiation heat transfer
There is no forced air cooling applied i.e. only natural convection is modeled

The common PCB stack-up is 4 layers with vias under the MOSFETs to create a dissipation path tothe heatsink.
In this analysis, we will examine the variation in device junction temperature (Tj) as a function of top
copper area.
In Fig. 31 below, we can see the vias configuration:

Square of 100 mm

Length x

vias
Length x

FR4

Fig. 31. copper area configuration: LFPAK33, 4 layers with vias

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LFPAK MOSFET thermal design guide

Vias configuration: square vias used for ease of simulation.
Fig. 32. Sectional view: LFPAK33
Table 7. Vias configuration
X (mm)
vias configuration
minimalfootprint

1 via

6

6 vias8

9 vias10

20 vias15

25 vias20

25 vias25

25 vias30

25 vias35

25 vias40

25 vias50

25 viasMaximum numberof vias able to beinserted in the copper
surface

Vias pitch 2.5 mm
Vias side length 0.7 mm
Copper thickness 70 μm
No solder fill

25 vias maximum

The graph Fig. 33 captures two important factors:••

Tj depends greatly on length “x” and thus copper area, the bigger the area the better thethermal performance
However, the ability of the top copper to provide heatsinking for the MOSFET shows a “law ofdiminishing returns”. In other words, we cannot keep on adding more copper area in the hope ofcontinuing to reduce Tj. As can be seen from Fig. 33 below Tj will plateau at around 33 °C (for0.5 W per MOSFET) no matter how much copper area we provide.

Care must be taken for Tj above 120 °C as PCB temperature directly under the transistor would beclose to the MOSFET Tj.

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LFPAK MOSFET thermal design guide

Tj
(°C)

180

(1) P = 0.1 W

160(2) P = 0.5 W(3) P = 1 W

140(4) PCB limit

(4)

120
100
80

(3)

60

(2)

40

(1)

20
0

0

10

20

30

40

50

60

Layer top side only, length "x" (mm)Fig. 33. Junction temperature as a function of copper side length x for LFPAK33
An alternative to the previous approach is to look at the maximum power allowed before reaching
Tj(max) = 175 °C (MOSFET absolute max). Maximum power allowed is shown for different ambient
temperature and copper length. In this example the PCB temperature was not considered so caremust be taken for the resulting heat on the PCB.
In the graph below the maximum power for the conditions given is as follows:
Tamb = 20 °C: Max power is 6.5 W in the MOSFET
Tamb = 80 °C: Max power is 4.3 W in the MOSFET

Pmax
(W)

7

(1) Power per MOSFET, Tamb = 80 °C(2) Power per MOSFET, Tamb = 20 °C

6
5

(2)

4
3

(1)

2
1
0

0

10

20

30

40

50

60

Layer top side only, length "x" (mm)Fig. 34. Maximum permissible power dissipation as a function of copper side length x for LFPAK33

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LFPAK MOSFET thermal design guide3.3. Placement advice for improved dissipation
In this section, we will present some results for two MOSFETs placed close to each other on asingle layer PCB with varying copper area.

3.3.1. LFPAK56D
Simulation of two MOSFETs placed next to each other is carried out and checked against results
seen in section 2.1. The aim is to understand the dissipation effect that the two LFPAK56D have on
one another.
Set-up
•
•
•
•
•
•
•
•
•

1 layer on the top side
MOSFET power dissipation is 0.5 W applied to each MOSFET
Maximum junction temperature of 175 °C
PCB material is standard FR4, 1.6 mm thickness, dimension 200 x 150 mm
Maximum PCB operating temperature of 120 °C
2Copper thickness on all layers (external and internal) is 2 oz./ft (70 μm)
The PCB is suspended in free air at ambient temperature of 20 °C
The simulation is carried out for conduction, convection and radiation heat transfer
There is no forced air cooling applied i.e. only natural convection is modeled

The simplest possible PCB stack-up is that of a single top copper layer. In this analysis, we will
examine the variation in device junction temperature (Tj) as a function of top copper area.
•••

2 mm gap between right and left copper layers
Simulation carried out for different length “x”
0.5 W applied on each internal MOSFET

200 mm2 mm between layers
kept constant
Length x

Length x

150 mmFR4

Fig. 35. Copper area configuration: LFPAK56D, single top copper layer
The graph in Fig. 36 shows:••AN90003application note

The results (in green) are similar to the ones observed in section 2.1 (slightly higher +3 °C)
This is due to the low conductivity of FR4, despite only 2 mm gap it showed no heat transferfrom one copper area to the otherAll information provided in this document is subject to legal disclaimers.

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LFPAK MOSFET thermal design guide

Tj
(°C)

180

(1) P = 0.5 W, single LFPAK56D

160(2) P = 0.5 W, two LFPAK56D next to each other(3) PCB limit

140

(3)

120

(2)

100
80
(1)

60
40
20
0

0

10

20

30

40

50

60

Layer top side only, length "x" (mm)Fig. 36. Junction temperature as a function of copper side length x for 2 LFPAK56D

3.3.2. LFPAK33
Simulation of two MOSFETs placed next to each other is carried out and checked against results
seen in section 2.3. The aim is to understand the dissipation effect that the two MOSFETs have on
one another.
Set-up:
•
•
•
•
•
•
•
•
•

1 layer on the top
MOSFET power dissipation is 0.5 W applied in the MOSFET
Maximum junction temperature of 175 °C
PCB material is standard FR4, 1.6 mm thickness, dimension 200 x 150 mm
Maximum PCB operating temperature of 120 °C
2Copper thickness is 2 oz./ft (70 μm)
The PCB is suspended in free air at ambient temperature of 20 °C
The simulation is carried out for conduction, convection and radiation heat transfer
There is no forced air cooling applied i.e. only natural convection is modeled

The simplest possible PCB stack-up is that of a single top copper layer. In this analysis, we will
examine the variation in device junction temperature (Tj) as a function of top copper area.
•••

AN90003application note

2 mm gap between right and left copper layers
Simulation carried out for different length “x”
0.5 W applied on each MOSFET

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LFPAK MOSFET thermal design guide

200 mmLength x

Length x

2 mm between layers
kept constant

150 mmFR4

Fig. 37. Copper area configuration: LFPAK33, single top copper layer
The graph in Fig. 39 shows:••••

The results for x > 20 mm are similar to the ones observed in section 2.3 (slightly higher +3 °C)
This is due to the low conductivity of FR4, despite only 2 mm gap it showed no heat transferfrom one copper area to the otherFor x < 20 mm results show up to 20 °C higher compared to the results from section 2.3.
This is due to the MOSFETs being brought closer to each other as a result of reduced copperarea – note that in this case the space between MOSFETs is half the space between MOSFETs
in the case of LFPAK56DIn Fig. 38 you can see that for x = 10 mm, the distance between the LFPAK33 MOSFETs isapproximatively 10 mm. Less than 20 mm apart, the MOSFETs are close enough to heat eachother, hence we start to see a temperature difference.

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LFPAK MOSFET thermal design guide

2 mm gap

x = 10 mm

2x + 2 = 22 mm

x = 10 mm

x = 10 mm

x + 2 = 12 mm

x = 10 mm

2 mm gap

Fig. 38. Copper area configuration: 2 x LFPAK33, 2 x LFPAK56D; separation between
MOSFETs

Tj
(°C)

180

(1) P = 0.5 W, single LFPAK33(2) P = 0.5 W, 2 x LFPAK33 next to each other(3) PCB limit

160
140

(3)

120

(2)

100
80
(1)

60
40
20
0

0

10

20

30

40

50

60

Layer top side only, length "x" (mm)Fig. 39. Junction temperature as a function of copper side length x for 2 LFPAK33

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LFPAK MOSFET thermal design guide3.4. Comparison between two LFPAK56 and one LFPAK56D, thenone LFPAK56D and two LFPAK33
In this section we will present some comparative results for different package devices on a single
layer board with varying copper area.

3.4.1. Two LFPAK56 to LFPAK56D
In this section the results of two single LFPAK56 MOSFETs are compared to the results of one dual
LFPAK56D MOSFET (see Section 3.1.1)
The aim is to highlight the benefit of using one LFPAK56D dual MOSFET instead of two single
LFPAK56 MOSFETs.
Set-up:
•
•
•
•
•
•
•
•
•

1 layer on the top
MOSFET power dissipation is 0.5 W applied to each MOSFET
Maximum junction temperature of 175 °C
PCB material is standard FR4, 1.6 mm thickness, dimension 100 x 100 mm
Maximum PCB operating temperature of 120 °C
2Copper thickness is 2 oz./ft (70 μm)
The PCB is suspended in free air at ambient temperature of 20 °C
The simulation is carried out for conduction, convection and radiation heat transfer
There is no forced air cooling applied, i.e. only natural convection is modeled

The simplest possible PCB stack-up is that of a single top copper layer. In this analysis, we will
examine the variation in device junction temperature (Tj) as a function of top copper area.
•••

Same gap between copper layer was used for both single LFPAK56 and dual LFPAK56D
Simulation carried out for different length “x”.
0.5 W applied on each MOSFET
Square of 100 mm
Length x

Length x

LFPAK56D

Length x

Length x

2 x LFPAK56
FR4

Fig. 40. Copper area configuration: 1 x LFPAK56D, 2 x LFPAK56, single top copper layer
The graph in Fig. 41 shows:•AN90003application note

Overall two single LFPAK56 show better heat dissipation than one dual LFPAK56D by up to
approximately 10 °C. This is due to the larger surface area of the LFPAK56 drain tab giving
improved heat spreading and thermal dissipation.

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LFPAK MOSFET thermal design guide
•
•

Tj
(°C)

Note that the 10 °C is the relative figure between the two packages, the most important factor isthe operating junction temperature
If there is enough margin before reaching 175 °C at the junction, then LFPAK56D offers an
attractive option due to its space saving

180(1) P = 2 x 0.5 W, single LFPAK56D(2) P = 2 x 0.5 W, two LFPAK56 next to each other160(3) PCB limit

140

(3)

120
100

(1)

80
60

(2)

40
20
0

0

10

20

30

40

50

60

Layer top side only, length "x" (mm)Fig. 41. Junction temperature as a function of copper side length x for 2 LFPAK56 and 1 LFPAK56D

3.4.2. LFPAK56D to two LFPAK33
In this section the results of one dual LFPAK56D MOSFET are compared to the results of two
single LFPAK33 MOSFETs (see section 4.2)
Aim is to highlight the benefit of using one LFPAK56D dual instead of two single LFPAK33.
Set-up:
•
•
•
•
•
•
•
•
•

1 layer on the top
MOSFET power dissipation is 0.5 W applied to each MOSFET
Maximum junction temperature of 175 °C
PCB material is standard FR4, 1.6 mm thickness, dimension 100 x 100 mm
Maximum PCB operating temperature of 120 °C
2Copper thickness is 2 oz./ft (70 μm)
The PCB is suspended in free air at ambient temperature of 20 °C
The simulation is carried out for conduction, convection and radiation heat transfer
There is no forced air cooling applied, i.e. only natural convection is modeled

The simplest possible PCB stack-up is that of a single top copper layer. In this analysis, we will
examine the variation in device junction temperature (Tj) as a function of top copper area.
•••

AN90003application note

Same gap between copper layer was used for both single LFPAK33 and dual LFPAK56D
Simulation carried out for different length “x”
0.5 W applied on each MOSFET

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LFPAK MOSFET thermal design guide
Square of 100 mm
Length x

Length x

LFPAK56D

FR4

Length x

Length x

2* LFPAK33

Fig. 42. Copper area configuration: 1 x LFPAK56D, 2 x LFPAK33, single top copper layer
The graph in Fig. 43 shows:
•
•
•

Tj
(°C)

Overall two single LFPAK33 show better heat dissipation than a dual LFPAK56D by up to
approximately 5 °C. This is due to the larger drain surface area of the LFPAK33 offering better
thermal dissipation, (less improvement than with LFPAK56 as LFPAK33 is a smaller package).
Note that the 5 °C is the relative figure between the two packages, the most important factor isthe operating junction temperature.
If there is enough margin before reaching 175 °C at the junction, then LFPAK56D offers an
attractive option due to all the advantages that one component offers versus two in terms of
PCB layout, placement, cost effectiveness, etc.

180(1) P = 2 x 0.5 W, single LFPAK56D(2) P = 2 x 0.5 W, two LFPAK33 next to each other(3) PCB limit

160
140

(3)

120
100
80

(1)

60

(2)

40
20
0

0

10

20

30

40

50

60

Layer top side only, length "x" (mm)Fig. 43. Junction temperature as a function of copper side length x for 1 LFPAK56D and 2 LFPAK33

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LFPAK MOSFET thermal design guide3.5. Impact of Rth(j-mb) compared to Rth(mb-a)
Dissipation losses from the MOSFET junction are not mainly limited by the thermal resistanceRth(j-mb) as this is very low. The high thermal path for heat dissipation is presented by the thermal
resistance Rth(mb-amb) (mounting base to PCB to ambient).
Legs

Plastic
encapsulation

Junction

Leadframe
components

Rth(j-top)Die

Rth(PCB-amb)

Rth(j-mb)

PCB
Rth (PCB)

Fig. 44. View of thermal resistances in and outside the MOSFET
Example: for the part number BUK7M15-60E (LFPAK33, 15 mΩ, 60 V) the maximum thermal
resistance junction to mounting base is 2.43 K/W:
Table 8. Thermal resistance BUK7M15-60E
SymbolParameter
Conditions

Min

Typ

Max

Unit

Rth(j-mb)

-

2.01

2.43

K/W

thermalFig. 5
resistancefrom junction
to mounting
base

Using thermal simulation (Flotherm) with the following conditions:
0.5 W of losses in the MOSFET, air ambient is 20 °C, 35 μm copper, we can calculate somethermal resistance.
•••Rth(j-mb) is 0.8 K/W• This is a lower value than given in the data sheet due to the simulation using ideal
conditions
As can be seen in Table 9 below, thermal resistance for other items have high value compared
Rth j-mb
The total thermal resistance, junction to ambient, is 59.4 K/W when using 65.4 °C as (ambient)reference point.

Table 9 lists temperatures for different points captured in the simulation and shown in Fig. 45.

AN90003application note

Table 9. Breakdown of thermal resistance for a simple case
Thermal resistance part Temperature (°C)

Rth (K/W)

Junction

95.1-

Mounting base

94.7

0.8

PCB under MOSFET

88.6

12.2

PCB to the right of the
MOSFET

86.6

4

Ambient air 0.5 mm over
the top of the PCB

79.1

15

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Thermal resistance part

Temperature (°C)

Rth (K/W)

Ambient air 1 mm over the 65.4
top of the PCB

27.4

AMBIENT AIR

95.1 °C
94.7 °C

65.4 °C

MOSFET
79.1 °C
PCB

88.6 °C

86.6 °C

Fig. 45. Thermal result, LFPAK33, 0.5 W, 20 °C ambient
Due to the very low thermal resistance between junction and mounting base it is very importantto take care of design surrounding the MOSFET, (i.e. thermal vias, copper area, heat sink, watercooling, air cooling), in order to reduce the total thermal resistance.

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4. LFPAK56 and LFPAK88
4.1. Simple configuration with a single layer
In this section, we will present the maximum power dissipation results for a simple PCB
configuration using a single layer with varying copper area.
Results are given for the LFPAK56 and LFPAK88 packages. Models used are based on 1 mΩ
LFPAK56E and LFPAK88.

4.1.1. Set-up:
•
•
•
•
•
•
•
•
•

1 copper layer on the top
MOSFET power dissipation is 1 W, 1.5 W and 2 W
Maximum junction temperature of 175 °C
PCB material is standard FR4, 1.6 mm thickness, dimension 100 x 100 mm
PCB operating temperature of 120 °C and Tj of 175 °C are highlighted in graphs
2
Copper thickness is 2 oz./ft (70 μm)
The PCB is suspended in free air at ambient temperature of 20 °C
The simulation is carried out for conduction, convection and radiation heat transfer
There is no forced air cooling applied, i.e. only natural convection is modeled

The simplest possible PCB stack-up is that of a single top copper layer, see Fig. 46.
In this analysis, we will examine the variation in device junction temperature (Tj) as a function of the
top copper area and calculate the maximum power that can be safely dissipated in the MOSFET toreach a Tj of 175 °C.

Square of 100 mm

FR4

Length x

Length x

aaa-029865

Fig. 46. Copper area configuration: LFPAK56, single top copper layer, the configuration is
the same for LFPAK88

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4.1.2. Junction temperature as a function of copper area
The graphs in Fig. 47 and Fig. 48 capture two important factors:••

Tj depends greatly on length “x” and thus copper area, the bigger the area the better thethermal performance
However, the ability of the top copper to provide heatsinking for the MOSFET shows a “law ofdiminishing returns”. In other words, we cannot keep on adding more copper area in the hopeof continuing to reduce Tj. As can be seen from Fig. 47 below, for LFPAK56, 1 W profile, Tj willplateau at around 55 °C.
Note: Standard FR4 PCBs operate at a maximum temperature of 120 °C, care must be
taken for Tj > 120 °C as the PCB area directly under the transistor will be close to the
MOSFET junction temperature, (due to low Rth(j-mb)).

The graphs below also shows the absolute minimum copper area needed for Tj ≤ 175 °C.
Tj

180

(5)

(1) P = 1 W(°C) 160(2) P = 1.5 W(3) P = 2 W

140(4) PCB limit(5) Tj limit

(4)

120
100

(3)
(2)

80

(1)

60
40
20
0

0

10

20

30

40

50

60

70

Layer top side only, length "x" (mm)Fig. 47. Junction temperature as a function of copper side length x for LFPAK56

Tj

180

(5)

(1) P = 1 W(°C) 160(2) P = 1.5 W(3) P = 2 W

140(4) PCB limit(5) Tj limit

(4)

120

(3)

100

(2)

80

(1)

60
40
20
0

0

10

20

30

40

50

60

70

Layer top side only, length "x" (mm)Fig. 48. Junction temperature as a function of copper side length x for LFPAK88

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4.1.3. Maximum allowed power dissipation as a function of copper area
The maximum allowed power dissipation is shown in Fig. 49 and Fig. 50 below, for different
ambient temperature and copper side length. In this example the PCB temperature was notconsidered so care must be taken for the resulting heat on the PCB.
From graphs in Fig. 49 and Fig. 50 the maximum permissible power, (Tamb = 20 °C), is 5.05 W and
5.9 W for the LFPAK56 and LFPAK88 packages respectively:

Pmax
(W)

6

Table 10. Maximum power dissipation
DeviceTamb = 20 °C

Tamb = 80 °C

LFPAK56

5.05 W

3.2 W

LFPAK88

5.9 W

3.8 W

(1) Tamb = 20 °C(1)(2) Tamb = 80 °C

5
4

(2)
3
2
1
0

0

10

20

30

40

50
60
70
Side length "x" of the Cu area (mm)Fig. 49. Maximum permissible power dissipation as a function of copper side length “x” for LFPAK56

Pmax
(W)

7
(1) Tamb = 20 °C

6(1)(2) Tamb = 80 °C

5
(2)

4
3
2
1
0

0

10

20

30

40

50
60
70
Side length "x" of the Cu area (mm)Fig. 50. Maximum permissible power dissipation as a function of copper side length “x” for LFPAK88

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LFPAK MOSFET thermal design guide4.2. Usual configuration: 4 layers + vias
In this section, we will present the maximum power dissipation results for a PCB configuration
using 4 layers + vias for dissipation on the bottom layer, with varying copper area.
Results are given for the LFPAK56 and LFPAK88 packages.

4.2.1. Set-up:
•
•
•
•
•
•
•
•
•

Four layers with vias (max number of vias is 25 and for small copper areas this number will
decrease accordingly, see Table 11)
MOSFET power dissipation is 1 W, 1.5 W and 2 W
Maximum junction temperature of 175 °C
PCB material is standard FR4, 1.6 mm thickness, dimension 100 x 100 mm
PCB operating temperature of 120 °C and Tj of 175 °C are highlighted in graphs
2
Copper thickness of all layers is 2 oz./ft (70 μm)
The PCB is suspended in free air at ambient temperature of 20 °C
The simulation is carried out for conduction, convection and radiation heat transfer
There is no forced air cooling applied, i.e. only natural convection is modeled

The common PCB stack-up is 4 layers with vias under the MOSFET to create a dissipation path toheatsink (no heat sink was used in simulation).
In this analysis, we will examine the variation in device junction temperature (Tj) as a function ofcopper area (same area size applied to all layers).
The configuration of the vias is shown below in Fig. 51 and Fig. 52:

VIAS

PCB: FR4 / 100 mm squareaaa-029866

Fig. 51. Copper area configuration: LFPAK56, 4 layers with vias, the configuration issimilar for LFPAK88

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LFPAK MOSFET thermal design guideaaa-029867

Vias configuration: square vias used for ease of simulation.
Fig. 52. Sectional view: LFPAK56
Table 11. Limitation of number of vias
X (mm)
Vias configuration
6

9 vias8

AN90003application note

10

20 vias15

25 vias20

25 vias25

25 vias30

25 vias35

25 vias40

25 vias45

25 vias50

25 vias60

25 viasComments

Vias information

Maximum number ofSquare vias: length 0.7 mm
vias able to be inserted Vias pitch:in the copper area
2.5 mm (between vias incolumns)
2.0 mm (between vias in
25 vias maximum
rows)
Copper thickness 70 μm
No solder fill

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LFPAK MOSFET thermal design guide4.2.2. Junction temperature as a function of copper area (4 layers and vias)
The graphs in Fig. 53 and Fig. 54 below show the junction temperature as a function of draincopper area following the same trend as the single layer PCB configuration in that:
•
•

Tj

180

Tj depends greatly on copper area
The ability of the top copper to provide heatsinking for the MOSFET shows a “law of diminishingreturns”.
(5)(1) P = 1 W(°C) 160(2) P = 1.5 W(3) P = 2 W

140(4) PCB limit(5) Tj limit

(4)

120
100

(3)

80

(2)

60

(1)

40
20
0

0

10

20

30

40

50

60

70

Four layers with vias, length "x" (mm)Fig. 53. Junction temperature as a function of copper side length x for LFPAK56

Tj

180

(5)

(1) P = 1 W(°C) 160(2) P = 1.5 W(3) P = 2 W

140(4) PCB limit(5) Tj limit

(4)

120
100

(3)

80

(2)

60

(1)

40
20
0

0

10

20

30

40

50

60

70

Four layers with vias, length "x" (mm)Fig. 54. Junction temperature as a function of copper side length x for LFPAK88

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4.2.3. Maximum allowed power dissipation as a function of copper area
(4 layers and vias)
From graphs in Fig. 55 and Fig. 56 the maximum power for a given package and conditions are as
follows:
Table 12. Maximum power dissipation
DeviceTamb = 20 °C

Tamb = 80 °C

LFPAK56

9.6 W

6.3 W

LFPAK88

10.65 W

6.9 W

12
Pmax

(1) Tamb = 20 °C(W) 10(2) Tamb = 80 °C

(1)

8
(2)

6
4
2
0

0

10

20

30

40

50
60
70
Side length "x" of the Cu area (mm)Fig. 55. Maximum permissible power dissipation as a function of copper side length “x” for LFPAK56
12
Pmax
(W)
10

(1) Tamb = 20 °C(1)(2) Tamb = 80 °C

8

(2)

6
4
2
0

0

10

20

30

40

50
60
70
Side length "x" of the Cu area (mm)Fig. 56. Maximum permissible power dissipation as a function of copper side length “x” for LFPAK88

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LFPAK MOSFET thermal design guide4.3. Simple configuration with a single split layer of copper
In this section, we will present the maximum power dissipation results as per the previous section
for a simple PCB configuration using a single layer and varying copper area, but with copper
layer split in two part (one part placed under the drain tab of the MOSFET and the other under thesource pins).
Results are given for the LFPAK88 package only.

4.3.1. Set-up:
•

•
•
•
•
•
•
•
•

1 copper layer on the top - split into two areas:• 3/5 of area under drain tab• 2/5 of area under source pins
MOSFET power dissipation is 1 W, 1.5 W and 2 W
Maximum junction temperature of 175 °C
PCB material is standard FR4, 1.6 mm thickness, dimension 100 x 100 mm
PCB operating temperature of 120 °C and Tj of 175 °C are highlighted in graphs
2
Copper thickness is 2 oz./ft (70 μm)
The PCB is suspended in free air at ambient temperature of 20 °C
The simulation is carried out for conduction, convection and radiation heat transfer
There is no forced air cooling applied, i.e. only natural convection is modeled

The simplest possible PCB stack-up is that of a single top copper layer, see Fig. 57.
In this analysis, we will examine the variation in device junction temperature (Tj) as a function of the
top copper area.

Square of 100 mm

PCB: FR4

aaa-029871

Fig. 57. Split copper area configuration: LFPAK88, single top layer with copper
The graph in Fig. 58 captures what has been previously mentioned in terms of copper area andheat dissipation i.e. the bigger the area the better the thermal performance. More importantly in thisconfiguration, it shows the importance in considering the source pins of an LFPAK MOSFET as athermal path for efficiently dissipating heat.
The graph in Fig. 58 also shows that coper area of length “x” = 40 mm in split copper configuration
provides a performance equivalent of that provided in the solid (non-split) copper area of length “x”= 60 mm.

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LFPAK MOSFET thermal design guide
Split copper configuration for length “x” = 40 mm is as follows:••

24 mm x 40 mm copper area placed under the drain tab of the LFPAK MOSFET
16 mm x 40 mm copper area placed under the source pins of the LFPAK MOSFET
Note: Standard FR4 PCBs operate at maximum temperature of 120 °C, care must be
taken for Tj > 120 °C as PCB area directly under the transistor would be close to the
MOSFET junction temperature (due to low Rth(j-mb)).

Results are for LFPAK88, but the principle applies to all Nexperia clip bond LFPAK devices. Tamb =20 °C: Max power of ~6 W is achieved with an area of 40 mm x 40 mm single copper layer in split
configuration, whist previously shown to require an area of 60 mm x 60 mm for single solid copper
layer.

Pmax
(W)

7

(1) Split single layer(2) Solid single layer

6

(1)

(2)

5
4
3
2
1
0

0

10

20

30

40

50
60
70
Side length "x" of the Cu area (mm)LFPAK88
Fig. 58. Maximum permissible power dissipation as a function of copper side length “x” for LFPAK88

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LFPAK MOSFET thermal design guide4.4. Impact of Rth(j-mb) compared to Rth(mb-amb)
The thermal resistance Rth(j-mb) of the MOSFET is very low and therefore dissipation losses
are mainly limited by the high thermal resistive path presented by Rth(mb-amb) (mounting base toambient).
Legs

Plastic
encapsulation

Junction

Leadframe
components

Rth(j-top)Die

Rth(PCB-amb)

Rth(j-mb)

PCB
Rth (PCB)

Fig. 59. View of thermal resistances in and outside the MOSFET
Example: for the part number BUK7S1R0-40H (LFPAK88, 1 mΩ, 40 V) the maximum thermal
resistance junction to mounting base is 0.4 K/W, see Table 13:
Table 13. Thermal resistance BUK7S1R0-40H
SymbolParameter
Conditions

Min

Typ

Max

Unit

Rth(j-mb)

-

0.35

0.4

K/W

thermalresistancefrom junction
to mounting
base

Using thermal simulation (Flotherm) with the following conditions:•••

1 W of losses in the MOSFET
Ambient air temperature of 20 °C
70 μm copper

we can calculate the thermal resistance for different paths, example:••••

1 W of losses in the MOSFET
Junction temperature = 52.2 °C
Mounting base temperature = 52.0 °C
RƟ = ∆T / P => Rth(j-mb) = 0. 2 K/W.

This is lower than the measured value given in the data sheet due to simulation using ideal
conditions.
As can be seen in Fig. 60 below, the thermal resistance between mounting base and ambient is ofmuch higher value (~30 K/W) than Rth(j-mb).

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LFPAK MOSFET thermal design guideFig. 60. Thermal resistance LFPAK88: single layer copper profile (50 x 50 mm)

Fig. 61. Thermal resistance LFPAK88: single layer copper profile (40 x 40 mm)

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LFPAK MOSFET thermal design guideFig. 62. Thermal resistance LFPAK88: single split layer copper profile (40 x 40 mm: split into 24 x 40 mm and16 x 40 mm)

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5. Conclusion
All the LFPAK packages offer a very good junction to mounting base thermal performance,
meaning that the mounting base can be near to the junction temperature, but this is often limited by
the PCB high temperature capability.
It is very important for designs to reduce the thermal resistance between mounting base and theambient environment as this will present the bottleneck in heat dissipation. All of Nexperia LFPAK
packages use clip bond technology making their source pins a good thermal path in addition to thethermal path provided by the drain tab. To take full advantage of this feature, it is important for PCB
layout designs to consider placing a good amount of copper under the source pins. The drain tab
still presents the main thermal path for heat dissipation and should be the focus for any thermal
design layout.
In all cases a configuration with 4 layers with vias substantially improves the heat dissipation.
This thermal guide establishes the necessary principles in thermal design approaches, combinedwith LFPAK packages features (i.e. low Rth(j-mb) and source clip bond) offer the designer good
options in optimizing PCB thermal design.
Good thermal design practices should be applied to take advantage of the very good thermal
performance LFPAK packages and Tj(max) must be kept < 175 °C for safe operation.

6. Revision history
Table 14. Revision history
Revision
Date
numberDescription

4.1

2023-08-22

Equations 5, 6 and 7 corrected.

4.0

2023-01-04

Section 2.3.1 updated.

3.1

2021-01-22

Equation 9 corrected.

3.0

2020-07-22

Section 2 added.

2.0

2019-05-09

Additional section added for LFPAK56 and LFPAK88.
Formatting of graphs updated.

1.0

2019-02-04

Initial version of the document.

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7. Legal information
Definitions
Draft — The document is a draft version only. The content is still underinternal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any representations or
warranties as to the accuracy or completeness of information included hereinand shall have no liability for the consequences of use of such information.

Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, Nexperia does not give any
representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for theconsequences of use of such information. Nexperia takes no responsibility
for the content in this document if provided by an information source outsideof Nexperia.
In no event shall Nexperia be liable for any indirect, incidental, punitive,
special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removalor replacement of any products or rework charges) whether or not suchdamages are based on tort (including negligence), warranty, breach ofcontract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, Nexperia’s aggregate and cumulative liability towards customer
for the products described herein shall be limited in accordance with theTerms and conditions of commercial sale of Nexperia.
Right to make changes — Nexperia reserves the right to make changes
to information published in this document, including without limitation
specifications and product descriptions, at any time and without notice. This
document supersedes and replaces all information supplied prior to the
publication hereof.
Suitability for use — Nexperia products are not designed, authorized or
warranted to be suitable for use in life support, life-critical or safety-criticalsystems or equipment, nor in applications where failure or malfunctionof an Nexperia product can reasonably be expected to result in personal
injury, death or severe property or environmental damage. Nexperia and its
suppliers accept no liability for inclusion and/or use of Nexperia products insuch equipment or applications and therefore such inclusion and/or use is at
the customer’s own risk.
Applications — Applications that are described herein for any of theseproducts are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using Nexperia products, and Nexperia accepts no liability forany assistance with applications or customer product design. It is customer’ssole responsibility to determine whether the Nexperia product is suitableand fit for the customer’s applications and products planned, as well as
for the planned application and use of customer’s third party customer(s).
Customers should provide appropriate design and operating safeguards tominimize the risks associated with their applications and products.
Nexperia does not accept any liability related to any default, damage, costs
or problem which is based on any weakness or default in the customer’s
applications or products, or the application or use by customer’s third party
customer(s). Customer is responsible for doing all necessary testing for thecustomer’s applications and products using Nexperia products in order toavoid a default of the applications and the products or of the application or
use by customer’s third party customer(s). Nexperia does not accept any
liability in this respect.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a priorauthorization from competent authorities.
Translations — A non-English (translated) version of a document is forreference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.

Trademarks
Notice: All referenced brands, product names, service names andtrademarks are the property of their respective owners.

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List of Tables
Table 1. Typical thermal conductivity values........................ 4
Table 2. Thermal convection coefficient values....................4
Table 3. Typical emissivity values........................................ 5
Table 4. Thermal and electrical analogous parameters........6
Table 5. Percentage difference between junction
temperature and top-case temperature using various
mounting base copper areas............................................. 10
Table 6. Limitation of number of vias................................. 21
Table 7. Vias configuration.................................................25
Table 8. Thermal resistance BUK7M15-60E...................... 34
Table 9. Breakdown of thermal resistance for a simple
case.................................................................................... 34
Table 10. Maximum power dissipation............................... 38
Table 11. Limitation of number of vias............................... 40
Table 12. Maximum power dissipation............................... 42
Table 13. Thermal resistance BUK7S1R0-40H..................45
Table 14. Revision history..................................................48

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LFPAK MOSFET thermal design guideFig. 32. Sectional view: LFPAK33......................................25

List of Figures
Fig. 1. Thermal propogation phenomena............................. 3
Fig. 2. Conduction in a solid medium.................................. 3
Fig. 3. Convection in free air................................................4
Fig. 4. Radiation................................................................... 5
Fig. 5. SPICE model............................................................ 6
Fig. 6. Response.................................................................. 6
Fig. 7. Thermal and electrical resistance models.................7
Fig. 8. Thermal and electrical capacitance models.............. 7
Fig. 9. Transient and steady state thermal behavior............ 8
Fig. 10. Dominant thermal path from the die junction to
the mounting base and ambient for a standard power
package................................................................................ 8

Fig. 33. Junction temperature as a function of copperside length x for LFPAK33................................................. 26
Fig. 34. Maximum permissible power dissipation as afunction of copper side length x for LFPAK33....................26
Fig. 35. Copper area configuration: LFPAK56D, single
top copper layer................................................................. 27
Fig. 36. Junction temperature as a function of copperside length x for 2 LFPAK56D........................................... 28
Fig. 37. Copper area configuration: LFPAK33, single
top copper layer................................................................. 29
Fig. 38. Copper area configuration: 2 x LFPAK33, 2 x
LFPAK56D; separation between MOSFETs.......................30
Fig. 39. Junction temperature as a function of copperside length x for 2 LFPAK33..............................................30

Fig. 11. Thermal path junction to mounting base................. 9

Fig. 40. Copper area configuration: 1 x LFPAK56D, 2 x
LFPAK56, single top copper layer..................................... 31

Fig. 12. Dominant and minor heat flow paths inside a
MOSFET...............................................................................9

Fig. 41. Junction temperature as a function of copperside length x for 2 LFPAK56 and 1 LFPAK56D..................32

Fig. 13. Thermal path junction to ambient......................... 10

Fig. 42. Copper area configuration: 1 x LFPAK56D, 2 x
LFPAK33, single top copper layer..................................... 33

Fig. 14. Simplified Rth(j-a) thermal paths...........................11
Fig. 15. Thermal circuit, MOSFET, PCB and environment. 11
Fig. 16. Copper area configuration: LFPAK56D, single
top copper layer................................................................. 13
Fig. 17. Junction temperature as a function of copperside length x for LFPAK56D.............................................. 14
Fig. 18. Maximum permissible power dissipation as afunction of copper side length x for LFPAK56D................. 15
Fig. 19. Junction temperature as a function of copperside length x for LFPAK56D; one MOSFET conducting..... 16
Fig. 20. Maximum power as a function of side length x
for LFPAK56D; one MOSFET conducting..........................16
Fig. 21. Thermal resistance configuration.......................... 17
Fig. 22. Copper area configuration: LFPAK33, single
top copper layer................................................................. 18
Fig. 23. Junction temperature as a function of copperside length x for LFPAK33................................................. 18
Fig. 24. Maximum permissible power dissipation as afunction of copper side length x for LFPAK33....................19
Fig. 25. Copper area configuration: LFPAK56D, 4
layers with vias.................................................................. 20
Fig. 26. Sectional view: LFPAK56D................................... 21
Fig. 27. Junction temperature as a function of copperside length x for LFPAK56D.............................................. 21
Fig. 28. Maximum permissible power dissipation as afunction of copper side length x for LFPAK56D................. 22
Fig. 29. Junction temperature as a function of copperside length x for LFPAK56D; one MOSFET.......................23
Fig. 30. Power dissipation as a function of copper side
length x for LFPAK56D; one MOSFET.............................. 23
Fig. 31. copper area configuration: LFPAK33, 4 layerswith vias............................................................................. 24

AN90003application noteFig. 43. Junction temperature as a function of copperside length x for 1 LFPAK56D and 2 LFPAK33..................33
Fig. 44. View of thermal resistances in and outside the
MOSFET.............................................................................34
Fig. 45. Thermal result, LFPAK33, 0.5 W, 20 °C ambient.. 35
Fig. 46. Copper area configuration: LFPAK56, single
top copper layer, the configuration is the same for
LFPAK88.............................................................................36
Fig. 47. Junction temperature as a function of copperside length x for LFPAK56................................................. 37
Fig. 48. Junction temperature as a function of copperside length x for LFPAK88................................................. 37
Fig. 49. Maximum permissible power dissipation as afunction of copper side length “x” for LFPAK56................. 38
Fig. 50. Maximum permissible power dissipation as afunction of copper side length “x” for LFPAK88................. 38
Fig. 51. Copper area configuration: LFPAK56, 4 layerswith vias, the configuration is similar for LFPAK88............ 39
Fig. 52. Sectional view: LFPAK56......................................40
Fig. 53. Junction temperature as a function of copperside length x for LFPAK56................................................. 41
Fig. 54. Junction temperature as a function of copperside length x for LFPAK88................................................. 41
Fig. 55. Maximum permissible power dissipation as afunction of copper side length “x” for LFPAK56................. 42
Fig. 56. Maximum permissible power dissipation as afunction of copper side length “x” for LFPAK88................. 42
Fig. 57. Split copper area configuration: LFPAK88,
single top layer with copper............................................... 43
Fig. 58. Maximum permissible power dissipation as afunction of copper side length “x” for LFPAK88................. 44

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LFPAK MOSFET thermal design guideFig. 59. View of thermal resistances in and outside the
MOSFET.............................................................................45
Fig. 60. Thermal resistance LFPAK88: single layer
copper profile (50 x 50 mm)...............................................46
Fig. 61. Thermal resistance LFPAK88: single layer
copper profile (40 x 40 mm)...............................................46
Fig. 62. Thermal resistance LFPAK88: single split
layer copper profile (40 x 40 mm: split into 24 x 40 mm
and 16 x 40 mm)................................................................ 47

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LFPAK MOSFET thermal design guide

Contents

4.2.3. Maximum allowed power dissipation as afunction of copper area (4 layers and vias)........................42

1. Introduction................................................................... 2

4.3. Simple configuration with a single split layer ofcopper.................................................................................43

2. MOSFET power dissipation and the design
environment........................................................................ 2

4.3.1. Set-up:.................................................................... 43

2.1. Heat propagation phenomena..................................... 3
2.1.1. Conduction................................................................3
2.1.2. Convection................................................................ 4
2.1.3. Radiation...................................................................5
2.2. Thermal – Electrical analogy....................................... 6
2.2.1. Thermal resistance................................................... 7
2.2.2. Thermal capacitance................................................ 7

4.4. Impact of Rth(j-mb) compared to Rth(mb-amb).................45
5. Conclusion.................................................................. 48
6. Revision history..........................................................48
7. Legal information........................................................49© Nexperia B.V. 2023. All rights reserved

For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 22 August 2023

2.2.3. Transient and steady state thermal behavior............ 8
2.3. MOSFET steady state thermal characteristics.............8
2.3.1. Thermal resistance junction to mounting base Rth(j-mb)..................................................................................82.3.2. Thermal resistance junction to ambient - Rth(j-a)......10
2.3.3. PCB thermal limitation and the 1 Watt rule............. 11
2.3.4. Thermal nomenclature............................................12
3. LFPAK56D and LFPAK33........................................... 13
3.1. Simple configuration with a single layer.....................133.1.1. LFPAK56D.............................................................. 13
3.1.2. LFPAK56D only one MOSFET active at a time.......16
3.1.3. LFPAK33.................................................................173.2. Usual configuration: 4 layers + vias...........................20
3.2.1. LFPAK56D.............................................................. 20
3.2.2. LFPAK56D only one MOSFET active at a time.......23
3.2.3. LFPAK33.................................................................24
3.3. Placement advice for improved dissipation................27
3.3.1. LFPAK56D.............................................................. 27
3.3.2. LFPAK33.................................................................28
3.4. Comparison between two LFPAK56 and one
LFPAK56D, then one LFPAK56D and two LFPAK33......... 31
3.4.1. Two LFPAK56 to LFPAK56D.................................. 31
3.4.2. LFPAK56D to two LFPAK33................................. 32
3.5. Impact of Rth(j-mb) compared to Rth(mb-a).................... 34
4. LFPAK56 and LFPAK88..............................................36
4.1. Simple configuration with a single layer.....................36
4.1.1. Set-up:.................................................................... 36
4.1.2. Junction temperature as a function of copper area. 37
4.1.3. Maximum allowed power dissipation as afunction of copper area...................................................... 38
4.2. Usual configuration: 4 layers + vias...........................39
4.2.1. Set-up:.................................................................... 39
4.2.2. Junction temperature as a function of copperarea (4 layers and vias)..................................................... 41

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