LT3942
36V, 2A Synchronous
Buck-Boost Converter and
LED Driver
DESCRIPTIONFEATURES
4-Switch Single Inductor Architecture Allows VIN
Above, Below or Equal to VOUT
nn Proprietary Peak-Buck Peak-Boost Current Modenn 3V to 36V Input Voltage Range
nn 0V to 36V Output Voltage Range
nn ±1.5% Output Voltage Regulation
nn ±3% LED Current Regulation
nn 5000:1 External and 128:1 Internal PWM Dimming
nn Rail-to-Rail LED Current Sense and Monitor Output
nn Open and Short LED Protection with Fault Reportingnn 300kHz to 2MHz Fixed Switching Frequency with
External Frequency Synchronization
nn Flicker-Free Spread Spectrum for Low EMI
nn Available in 28-Lead QFN (4mm × 5mm)

The LT®3942 is a monolithic 4-switch synchronous buckboost LED driver. The driver can regulate the LED string
current up to 34V with input voltages above, below, or
equal to the output voltage. The proprietary peak-buckpeak-boost current mode control scheme allows adjustable and synchronizable 300kHz to 2MHz fixed frequency
operation, or internal 25% triangle spread spectrum operation for low EMI. With 3V to 36V input, 0V to 36V output
and seamless low-noise transitions between operation
regions, the LT3942 is ideal for LED driver applicationsin automotive, industrial and battery-powered systems.

nn

The LT3942 provides LED current regulation with up to
128:1 internal and 5000:1 external PWM dimming using
an optional high-side PMOS switch. The CTRL pin provides flexible 20:1 analog dimming with ±2.5% LED current regulation at 100mV full scale. Robust fault protection detects an open or short LED condition, during which
the LT3942 retries, latches off, or keeps running.

APPLICATIONSGeneral Purpose LED Driver
Automotive and Industrial Lighting
nn Voltage Regulator with Accurate Current Limitnn
nn

All registered trademarks and trademarks are the property of their respective owners.

TYPICAL APPLICATION
93% Efficient, 12W (12V, 1A) 2MHz Buck-Boost LED Driver

VIN
8V TO 36V

499k

10µF

115k

1M

BST1 SW1
PVIN
VIN

34.8k

Efficiency vs VIN
100

100mΩ
1M

95

10µF

FB
69.8k
LT3942

100k
FAULT
VREF
0.22µF

ANALOG DIM
PWM DIM

0.1µF

SW2 BST2PVOUT

EN/UVLOOVLOINTVCC
1µF

3.3µH

EFFICIENCY (%)

0.1µF

ISP
ISN
PWMTG

1A

ISMON

VLED

VC
CTRL
PWM
RP

SS

GND

SYNC/SPRD

RT

1k
22nF
14.3k
2MHz

BUCK

90
BUCK–BOOST

85
80
75
70

12V
1A
LED

BOOST

VLED = 12V
ILED = 1A05

10

15 20 25 30
INPUT VOLTAGE (V)35403942 TA01b

2.2nF
3942 TA01a

Rev. 0Document Feedback

For more information www.analog.com

1

LT3942
ABSOLUTE MAXIMUM RATINGSPIN CONFIGURATION(Note 1)
SW2

SW2

BST2

BST1

SW1

SW1

TOP VIEW

PVIN, VIN, EN/UVLO...................................................40V
PVOUT, ISP, ISN..........................................................40V
SW1, SW2..................................................................40V
BST1, BST2................................................................45V
BST1−SW1, BST2−SW2, INTVCC.................................5V
OVLO, CTRL, FB, PWM, SYNC/SPRD, FAULT...............5V
ISP−ISN............................................................ −1V to 1V
Operating Junction Temperature (Notes 2, 3)
LT3942E.............................................. −40˚C to 125˚C
LT3942J/LT3942H............................... −40˚C to 150˚C
Storage Temperature Range.................... −65˚C to 150˚C

28 27 26 25 24 23
PVIN 122 PVOUT

PVIN 221 PVOUT

VIN 3

20 PWMTG

INTVCC 4

19 SYNC/SPRD

29
GND

EN/UVLO 5

18 RT

OVLO 6

17 VC

RP 7

16 FB

PWM 8

15 SS
FAULT

ISMON

ISN

ISP

VREF

CTRL

9 10 11 12 13 14

UFD PACKAGE
28-LEAD (4mm × 5mm) PLASTIC QFNθJA = 43°C/W, θJC = 3.4°C/W
EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCBORDER INFORMATIONLEAD FREE FINISH

TAPE AND REELPART MARKINGPACKAGE DESCRIPTIONTEMPERATURE RANGE

LT3942EUFD#PBF

LT3942EUFD#TRPBF

3942

28-Lead (4mm x 5mm) Plastic QFN–40˚C to 125˚C

LT3942JUFD#PBF

LT3942JUFD#TRPBF

3942

28-Lead (4mm x 5mm) Plastic QFN–40˚C to 150˚C

LT3942HUFD#PBF

LT3942HUFD#TRPBF

3942

28-Lead (4mm x 5mm) Plastic QFN–40˚C to 150˚C

Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.

ELECTRICAL CHARACTERISTICS

The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. PVIN = VIN = 12V, VEN/UVLO = VIN unless otherwise noted.
PARAMETERCONDITIONS

MIN

TYP

MAX

UNITS

36

V

0.9
2.6

2
4

µA
mA

36

V

20

0.1
40

0.5
60

µA
µA

0.3

0.6

0.9

V

Input and Output
PVIN/VIN Operating Voltage Range
PVIN/VIN Quiescent Currentl

VEN/UVLO = 0.3V
VEN/UVLO = 1.3V, Not Switching

PVOUT Operating Voltage Range
PVOUT Quiescent Current

3l

VEN/UVLO = 0.3V, PVOUT = 12V
VEN/UVLO = 1.3V, PVOUT = 12V, Not Switching

EN/UVLO Shutdown Thresholdl0Rev. 02

For more information www.analog.com

LT3942
ELECTRICAL CHARACTERISTICS

The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. PVIN = VIN = 12V, VEN/UVLO = VIN unless otherwise noted.
PARAMETERCONDITIONSEN/UVLO Enable Threshold

Falling

l

MIN

TYP

MAX

1.196

1.220

1.244

EN/UVLO Enable Hysteresis

15

UNITS
V
mV

EN/UVLO Hysteresis Current

VEN/UVLO = 0.3V
VEN/UVLO = 1.1V
VEN/UVLO = 1.3V

–0.1
2.2
–0.1

0
2.5
0

0.1
2.8
0.1

µA
µA
µA

OVLO Threshold

Rising

1.196

1.220

1.244

V

OVLO Hysteresis

35mV

Linear Regulators
INTVCC Regulation Voltage

IINTVCC = 10mA

3.5

3.65

3.8

V

INTVCC Load Regulation

IINTVCC = 0mA to 30mA

0.8

2

%

INTVCC Line Regulation

IINTVCC = 10mA, VIN = 4V to 36V

0.1

0.5

%

INTVCC Current Limit

VINTVCC = 3V

40

INTVCC Dropout Voltage (VIN – INTVCC)

IINTVCC = 10mA, VIN = 3V

INTVCC UVLO Threshold

Falling

2.27

INTVCC UVLO Hysteresis

mA

120

200

mV

2.37

2.47

V

120
1.97

mV

VREF Regulation Voltage

IVREF = 100µA

2.00

2.03

V

VREF Load Regulation

IVREF = 0mA to 1mA

0.5

1

%

VREF Line Regulation

IVREF = 100µA, VIN = 4V to 36V

0.1

0.5

VREF Current Limit

VREF = 1.8V

2.5

VREF UVLO Threshold

Fallingl

1.78

VREF UVLO Hysteresis

1.84

%
mA

1.90

45

V
mV

Current Regulation LoopCTRL Pin Current

VCTRL = 0.75V, Current Out of Pin

CTRL Dim-Off Threshold

Falling

l

0

13

50

nA

190

200

210

mV

CTRL Dim-Off Hysteresis

25

mV

Full Scale LED Current Regulation V(ISP-ISN)

VCTRL = 2V, VISP = 12V
VCTRL = 2V, VISP = 0V

l
l

97
97

100
100

103
103

mV
mV

1/2 LED Current Regulation V(ISP-ISN)

VCTRL = 0.75V, VISP = 12V
VCTRL = 0.75V, VISP = 0V

l
l

47.5
47.5

50
50

52.5
52.5

mV
mV

1/20th LED Current Regulation V(ISP-ISN)

VCTRL = 0.30V, VISP = 12V
VCTRL = 0.30V, VISP = 0V

l
l

3
3

5
5

7
7

mV
mV

ISP Pin Current

VPWM = 5V, VISP = VISN = 12V
VPWM = 5V, VISP = VISN = 0V
VEN/UVLO = 0V, VISP = VISN = 12V or 0V

–0.1

23
–10
0

0.1

µA
µA
µA

–0.1

23
–10
0

0.1

µA
µA
µA

36

V

ISN Pin Current

VPWM = 5V, VISP = VISN = 12V
VPWM = 5V, VISP = VISN = 0V
VEN/UVLO = 0V, VISP = VISN = 12V or 0V

ISP/ISN Input Common Mode Rangel0

ISP/ISN Low Side to High Side Switchover Voltage

VISP = VISN

1.7

V

ISP/ISN High Side to Low Side Switchover Voltage

VISP = VISN

1.6

V

2000

µS

LED Current Regulation Amplifier gm

Rev. 0For more information www.analog.com

3

LT3942
ELECTRICAL CHARACTERISTICS

The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. PVIN = VIN = 12V, VEN/UVLO = VIN unless otherwise noted.
PARAMETERCONDITIONS

MIN

TYP

MAX

UNITS

17

40

nA

Voltage Regulation LoopFB Pin Current

FB in Regulation, Current Out of Pin

FB Regulation Voltage

VC = 1.2V

FB Line Regulation

VIN = 3V to 36V

1.00

1.015

V

0.02

0.1

%

FB Load Regulation

0.02

0.1

%

FB Voltage Regulation Amplifier gm

650

µS

VC Output Impedance

10

MΩ

VC Standby Leakage Current

l

0.985

VC = 1.2V, PWM dimming off

–20

0

20

nA

Maximum Switch Current Limit

Peak-Buck Current Mode
Peak-Boost Current Mode

2.2
2.2

2.5
2.5

2.8
2.8

A
A

Switch A On-Resistance (From PVIN to SW1)

ISW = 1A

150mΩ

Switch B On-Resistance (From SW1 to GND)

ISW = 1A

150mΩ

Switch C On-Resistance (From SW2 to GND)

ISW = 1A

150mΩ

Switch D On-Resistance (From PVOUT to SW2)

ISW = 1A

150mΩPower Switches

Oscillator
Switching Frequency

VSYNC/SPRD = 0V, RT = 14.3kΩ
VSYNC/SPRD = 0V, RT = 43.2kΩ
VSYNC/SPRD = 0V, RT = 178kΩ

SYNC/SPRD Pin Current

VSYNC/SPRD = 3.6V

l

1900
925
275

2000
975
290

–0.1

0

2100
1025
305

kHz
kHz
kHz

0.1

µA

SYNC Frequency

300

2000

kHz

SYNC/SPRD Threshold Voltage

0.4

1.5

V

Highest Spread Spectrum Above Oscillator Frequency

VSYNC/SPRD = 3.6V

19

22

25

%

1.03

1.05

1.07

V

Fault
FB Overvoltage Threshold (VFB)

Rising

l
l

20

25

30

mV

Rising, V(ISP-ISN) = 0V

l

0.93

0.95

0.97

V

FB Open LED Hysteresis

V(ISP-ISN) = 0V

l

40

50

60

mV

FB Short LED Threshold (VFB)

Falling

l

0.23

0.25

0.27

V

l

40

50

60

mV

FB Overvoltage Hysteresis
FB Open LED Threshold (VFB)FB Short LED Hysteresis
ISP/ISN Over Current Threshold V(ISP-ISN)

VISP = 12V

ISP/ISN Open LED Threshold V(ISP-ISN)

Falling, VFB = 1.0V

ISP/ISN Open LED Hysteresis

VFB = 1.0V

700
8

11

mV
14

3

mV
mV

FAULT Pull-Down Resistance

130

200

Ω

SS Hard Pull-Down Resistance

130

200

Ω

SS Pull-Up Current

VFB = 0.8V, VSS = 0V

11

12.5

14

µA

SS Pull-Down Current

VFB = 1.0V, VSS = 2V

1.1

1.25

1.4

µA

SS Fault Latch-Off Threshold

1.75

V

SS Fault Reset Threshold

0.2

V

Rev. 04

For more information www.analog.com

LT3942
ELECTRICAL CHARACTERISTICS

The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. PVIN = VIN = 12V, VEN/UVLO = VIN unless otherwise noted.
PARAMETERCONDITIONS

MIN

TYP

MAX

UNITS

V(ISP-ISN) = 100mV, VISP = 12V/0V
V(ISP-ISN) = 10mV, VISP = 12V/0V
V(ISP-ISN) = 0mV, VISP = 12V/0V

1.22
0.32
0.22

1.25
0.35
0.25

1.28
0.38
0.28

V
V
V

Rising, RP = 10kΩ

1.3

1.4

1.5

V

Output Current Monitor
ISMON Voltage

PWM Dimming
External PWM Dimming Threshold
External PWM Dimming Hysteresis

200

Internal PWM Dimming Duty Cycle

VPWM = 1V, RP ≥ 28.7kΩ
VPWM = 1.5V, RP ≥ 28.7kΩ
VPWM = 2V, RP ≥ 28.7kΩ

Switching Frequency to Internal PWM Dimming Frequency
Ratio

RP = 28.7kΩ
RP = 332kΩ

Minimum VOUT for PWMTG to be On

PWM Dimming On

PWMTG On Voltage V(VOUT-PWMTG)

VOUT = 12V

4.6

PWMTG Off Voltage V(VOUT-PWMTG)

VOUT = 12V–0.1

PWM to PWMTG Turn On Propagation Delay
PWM to PWMTG Turn Off Propagation Delay

CPWMTG = 3.3nF to VOUT, 50% to 50%
CPWMTG = 3.3nF to VOUT, 50% to 50%

Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT3942E is guaranteed to meet performance specifications
from 0°C to 125°C operating junction temperature. Specifications overthe –40°C to 125°C operating junction temperature range are assured bydesign, characterization and correlation with statistical process controls.
The LT3942J and LT3942H are guaranteed over the –40°C to 150°C
operating junction temperature range.

mV
3
53

%
%
%

3

4.0

V

5

5.4

V

0

0.1

47
97
256
16384

130
120

V
ns
ns

Note 3: The LT3942 includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 150°C when overtemperature protection is active.
Continuous operation above the specified absolute maximum operating
junction temperature may impair device reliability or permanently damage
the device.

Rev. 0For more information www.analog.com

5LT3942TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency vs LED Current(Buck Region)

Efficiency vs LED Current(Buck-Boost Region)

Efficiency vs LED Current(Boost Region)

90

90

90

80

80

80

70
60
50
40

0.2

0.4
0.6
LOAD CURRENT (A)

0.8

70
60
50

FRONT PAGE APPLICATION
VIN = 24V, VLED = 12V, fSW = 2MHz
0

EFFICIENCY (%)

100

EFFICIENCY (%)

100

EFFICIENCY (%)

100

40

1

0.2

0.4
0.6
LOAD CURRENT (A)

0.8

3942 G01

60
50

FRONT PAGE APPLICATION
VIN = 12V, VLED = 12V, fSW = 2MHz
0

70

40

1

Switching Waveforms(Buck-Boost Region)

VSW1
10V/DIV

VSW2
10V/DIV

VSW2
10V/DIV

VSW2
10V/DIVIL
1A/DIVIL
1A/DIVIL
1A/DIV3942 G04

500ns/DIVFRONT PAGE APPLICATION
VIN = 12V, ILED = 1A

LED Current vsCombined PVIN/VIN

3942 G05

0.8500ns/DIVFRONT PAGE APPLICATION
VIN = 8V, ILED = 1A

Combined PVIN/VIN Shutdown
Current
3.0

FRONT PAGE APPLICATION

2.5

1.06
1.04

1

3942 G06

Combined PVIN/VIN Quiescent
Current
2.8

VIN = 36V
VIN = 12V
VIN = 3V

2.6

VIN = 36V
VIN = 12V
VIN = 3V

1.00
0.98

IQ (mA)2.0

1.02

IQ (µA)ILED (A)0.4
0.6
LOAD CURRENT (A)Switching Waveforms(Boost Region)

VSW1
10V/DIV

1.08

0.2

3942 G03

VSW1
10V/DIV

1.10

03942 G02

Switching Waveforms(Buck Region)

500ns/DIVFRONT PAGE APPLICATION
VIN = 24V, ILED = 1A

FRONT PAGE APPLICATION
VIN = 8V, VLED = 12V, fSW = 2MHz

1.5

2.4

2.2

1.0

0.96
0.94

2.0

0.5

0.92
0.90

0

5

10

15

20 25
VIN (V)

30

35

40

0
–50 –250

25 50 75 100 125 150
TEMPERATURE (°C)

3942 G07

3942 G08

1.8–50 –250

25 50 75 100 125 150
TEMPERATURE (°C)
3942 G09

Rev. 06

For more information www.analog.com

LT3942TYPICAL PERFORMANCE CHARACTERISTICS
INTVCC Voltage vs Temperature

INTVCC Voltage vs VIN

3.80

3.75

3.75

3.70

3.70

3.65

INTVCC UVLO Threshold
2.8
2.7

IINTVCC = 0mA

3.65
3.60

3.60
3.55

IINTVCC = 30mA

3.50

0

3.45

25 50 75 100 125 150
TEMPERATURE (°C)

0

5

10

15

3942 G10

VREF Voltage vs Temperature
2.03

2.03

2.02

2.02

2.01

2.01
VREF (V)2.04

IVREF = 0mA

1.99

20 25
VIN (V)

30

35

2.0
–50 –25

40

IVREF = 1mA3942 G12

VREF UVLO Threshold
2.00
1.95
1.90

IVREF = 100µA

2.00

25 50 75 100 125 150
TEMPERATURE (°C)

1.96

EN/UVLO Enable Threshold

0

5

10

15

20 25
VIN (V)

30

35

1.70
–50 –2540

0

25 50 75 100 125 150
TEMPERATURE (°C)

3942 G143942 G15

EN/UVLO Hysteresis Current

1.240

OVLO Threshold

3.0

1.25
1.24

1.235
2.8

1.230

1.23
1.22

1.220
1.215

2.6

VOVLO (V)RISING

1.225

IHYS (µA)

VEN/UVLO (V)FALLING

1.75

3942 G13

2.4

RISING

1.21
1.20
1.19

FALLING

1.18

FALLING

1.210

2.2

1.17

1.205
1.200
–50 –25

RISING
1.85
1.80

1.97
0

25 50 75 100 125 150
TEMPERATURE (°C)

1.98

1.97
1.96
–50 –2503942 G11

1.99

1.98

FALLING

2.3

VREF Voltage vs VIN

2.04

2.00

2.4

2.1

VREF (V)3.50–50 –25

RISING

2.5

2.2

3.55

VREF (V)VINTVCC (V)

VINTVCC (V)

VINTVCC (V)

2.6
IINTVCC = 10mA

1.16
025 50 75 100 125 150
TEMPERATURE (°C)

2.0
–50 –250

25 50 75 100 125 150
TEMPERATURE (°C)

3942 G16

3942 G17

1.15–50 –250

25 50 75 100 125 150
TEMPERATURE (°C)
3942 G18

Rev. 0For more information www.analog.com

7

LT3942TYPICAL PERFORMANCE CHARACTERISTICSCTRL Dim-Off Threshold
0.30

125

0.20
FALLING
0.15

75

50

25

0.10
–50 –2500

25 50 75 100 125 150
TEMPERATURE (°C)
3942 G19

100
98
96

0

0.25 0.50 0.75 1 1.25 1.50 1.75
VCTRL (V)94

2

FB Regulation vs Temperature
120

104

1.02

100

102

1.01

80

98

V(ISP–ISN) (mV)

1.03

VFB (V)

106

1.00
0.99

ISP = 0V
ISP = 12V
ISP = 36V

96
94
–50 –250

VIN = 3V
VIN = 12V
VIN = 36V

0.98
0.97
–50 –25

25 50 75 100 125 150
TEMPERATURE (°C)

0

300

5

10

15

20 25
VISP (V)

30

35

40

3942 G21

V(ISP-ISN) Regulation vs VFB

60
40

0
0.96 0.97 0.98 0.99

3942 G23

RDS(ON) vs Temperature

1 1.01 1.02 1.03 1.04
VFB (V)3942 G24

Minimum On-Time vsTemperature

Peak Current vs Temperature
2.60

15.00

2.55

250

14.00

2.50
200

DSW (%)ISW (A)

2.45

150

2.40
2.35

100
Switch A
Switch B
Switch C
Switch D500–50 –25020

25 50 75 100 125 150
TEMPERATURE (°C)

3942 G22

RDS(ON) (mOhm)

1023942 G20

V(ISP-ISN) Regulation vs
Temperature

100

V(ISP-ISN) Regulation vs VISP

104

V(ISP–ISN) (mV)

V(ISP–ISN) (mV)RISINGVCTRL (V)

106

100

0.25

V(ISP–ISN) (mV)

V(ISP-ISN) Regulation vs VCTRL

0

25 50 75 100 125 150
TEMPERATURE (°C)

2.30
BUCK
BOOST

2.25
2.20
–50 –250

25 50 75 100 125 150
TEMPERATURE (°C)

3942 G25

3942 G26

13.00

12.00

11.00

10.00
–50 –25SW1
SW2
0

25 50 75 100 125 150
TEMPERATURE (°C)
3942 G27

Rev. 08

For more information www.analog.com

LT3942TYPICAL PERFORMANCE CHARACTERISTICS
Maximum On-Time vsTemperature

FB Overvoltage Threshold

90.00

1.10
RISING

1.05

89.00

87.00

0.95

RISING

0.95

0.90

0.90

0.85

0.85

FALLING

86.00
SW1
SW2
0

0.80
–50 –25

25 50 75 100 125 150
TEMPERATURE (°C)

03942 G28

FB Short LED Threshold

SS Current vs Temperature

30

15.0

25

12.5

20

10.0

PULL–UP
V(ISP-ISN) (mV)RISING

0.25
FALLING
0.20
0.15

RISING

15
10

2.5

0
–50 –25

25 50 75 100 125 150
TEMPERATURE (°C)

0Frequency vs Temperature
1.25

ISMON Voltage vs V(ISP–ISN)

ISMON vs Temperature
1.50

0.95

1.00

0.85

VISMON (V)ISMON (V)RT = 43.2k

0.75
0.65

0
–50 –25

0

0.75
0.50

0.55
0.45

RT = 178k

V(ISP–ISN) = 100mV

1.25

1.05

1500

V(ISP–ISN) = 10mV

0.25

0.35

25 50 75 100 125 150
TEMPERATURE (°C)
3942 G34

25 50 75 100 125 150
TEMPERATURE (°C)
3942 G33

1.15

RT = 14.3k

500

03942 G32

2500

1000

PULL–DOWN

0–50 –25

25 50 75 100 125 150
TEMPERATURE (°C)

3942 G31

2000

7.5
5.0

FALLING5

0

25 50 75 100 125 150
TEMPERATURE (°C)
3942 G30

ISP/ISN Open LED Threshold

0.35

0.10
–50 –2503942 G29

0.40

0.30

0.80
–50 –25

25 50 75 100 125 150
TEMPERATURE (°C)

ISS (µA)

85.00–50 –25

VFB (V)

1.00
VFB (V)VFB (V)DSW (%)

88.00

1.05

FALLING

1.00

SWITCHING FREQUENCY (kHz)FB Open LED Threshold

1.10

0.25

V(ISP–ISN) = 0mV0

10 20 30 40 50 60 70 80 90 100
V(ISP–ISN) (mV)
3942 G35

0–50 –250

25 50 75 100 125 150
TEMPERATURE (°C)
3942 G36

Rev. 0For more information www.analog.com

9LT3942PIN FUNCTIONS
PVIN: Power Input. The PVIN pins connect to the power
input of the LED driver. Bypass this pin to ground with aceramic capacitor. The bypass capacitor should be placed
as close to the chip as possible with vias directly down to
the ground plane.
VIN: Bias Supply. The VIN pin supplies the internal circuitry
and the INTVCC linear regulator. Connect this pin to PVIN
or another power supply. Bypass this pin to ground witha ceramic capacitor.
INTVCC: Internal 3.6V Linear Regulator Output. Poweredfrom the VIN pin, the INTVCC supplies the internal control
circuitry and gate drivers. Bypass this pin to ground witha minimum 1µF ceramic capacitor.
EN/UVLO: Enable and Undervoltage Lockout. Force thepin below 0.3V to shut down the chip and reduce VIN quiescent current below 2µA. Force the pin above 1.235V for
normal operation. The accurate 1.220V falling threshold
can be used to program an undervoltage lockout (UVLO)
threshold with a resistor divider from PVIN to ground. An
accurate 2.5µA pull-down current allows the programming of PVIN UVLO hysteresis. If neither function is used,
tie this pin directly to VIN.
OVLO: Overvoltage Lockout. The OVLO pin can be used toprogram an overvoltage lockout (OVLO) threshold with aresistor divider from PVIN to ground. Force the pin above
1.220V to pull SS pin to ground and stop switching. If notused, tie this pin to ground.
RP: Internal PWM Dimming Frequency Setting. The RP
pin is used to set the internal PWM dimming frequency
with a resistor to ground. Do not use a resistor larger than
1MΩ and do not leave this pin open. For external PWM
dimming, tie this pin to ground.
PWM: PWM Dimming Input. The PWM pin can be usedin two ways: external PWM dimming and internal PWM
dimming. For external PWM dimming, drive this pin with adigital pulse from 0V to a voltage higher than 1.5V to control PWM dimming of the LED string. Make sure the RP

pin is tied to ground this case. For internal PWM dimming,
apply an analog voltage between 1V and 2V to generate
an internal digital pulse. If PWM dimming is not used, tie
this pin to INTVCC. Forcing the pin low turns off all powerswitches, disconnects the VC pin from all internal loads
and turns off PWMTG.
VREF: Voltage Reference Output. The VREF pin provides
an accurate 2V reference capable of supplying up to 1mA
current. Bypass this pin to ground with a minimum 0.22µF
ceramic capacitor.
CTRL: Control Input for LED Current Sense Threshold. The
CTRL pin is used to program the LED regulation current:V− 0.25V
ILED = CTRL
10 •R LED

The VCTRL can be set by an external voltage referenceor a resistor divider from VREF to ground. For 0.25V ≤VCTRL ≤ 1.15V, the current sense threshold linearly goesup from 0mV to 90mV. For VCTRL ≥ 1.35V, the current
sense threshold is constant at 100mV full scale value.
For 1.15V ≤ VCTRL ≤ 1.35V, the current sense thresholdsmoothly transitions from the linear function of VCTRL to
the 100mV constant value. Tie CTRL pin to VREF for the
100mV full scale threshold. Force the pin below 0.2V tostop switching.
ISP: Positive Terminal of LED Current Sense Resistor(RLED). Ensure accurate current sense with Kelvinconnection.
ISN: Negative Terminal of LED Current Sense Resistor(RLED). Ensure accurate current sense with Kelvinconnection.
ISMON: LED Current Monitor Output. The ISMON pin
generates a buffered voltage that is equal to ten times
V(ISP-ISN) plus 0.25V offset voltage. The voltage on the
ISMON pin will be 1.25V when V(ISP-ISN) is equal to
100mV full scale.

Rev. 010

For more information www.analog.com

LT3942PIN FUNCTIONSFAULT: LED Fault Open Drain Output. The FAULT pin ispulled low when any of the following conditions happens:
1. Open LED (VFB > 0.95V and V(ISP−ISN) < 10mV)
2. Short LED (VFB < 0.25V)
To function, this pin requires an external pull-up resistor.
The FAULT status is updated only during PWM high stateand latched during PWM low state.
SS: Soft-Start Timer Setting. The SS pin is used to set
soft-start timer by connecting a capacitor to ground. Aninternal 12.5µA pull-up current charging the external SS
capacitor gradually ramps up FB regulation voltage. A
22nF capacitor is recommended on this pin. Any UVLO,
OVLO, or thermal shutdown immediately pulls SS pin toground and stops switching. Using a single resistor fromSS to VREF, the LT3942 can be set in three different fault
modes during open or short LED fault conditions: hiccup(no resistor), latch-off (499k) and keep-running (100k).
See more details in the Applications Information section.
FB: Voltage Loop Feedback Input. The FB pin is used
for constant-voltage regulation and LED fault protection. The internal error amplifier with its output VC regulates VFB to 1.00V through the LED driver. During open
LED (VFB > 0.95V and V(ISP-ISN) < 10mV) or short LED(VFB < 0.25V) fault conditions, the part pulls the FAULT
pin low and enters one fault mode per customer setting.
During an overvoltage (VFB > 1.05V) condition, the partturns off all power switches and PWMTG.
VC: Error Amplifier Output to Set Inductor Current
Comparator Threshold. The VC pin is used to compensate the control loop with an external RC network. During
PWM low state, the VC pin is disconnected from all internal loads to store its voltage information for the highest
PWM dimming performance.
RT: Switching Frequency Setting. Connect a resistor fromthis pin to ground to set the internal oscillator frequency
from 300kHz to 2MHz.

SYNC/SPRD: Switching Frequency Synchronization or
Spread Spectrum. Ground this pin for switching at theinternal oscillator frequency. Apply a clock signal for
external frequency synchronization. Tie to INTVCC for
25% triangle spread spectrum above internal oscillator
frequency.
PWMTG: PWM Dimming Top Gate Drive. The PWMTG
pin produces a buffered and inverted version of the PWM
input signal and drives an external high side PMOS PWM
switch with a voltage swing from the higher voltage
between (PVOUT − 5V) and 1.2V to PVOUT. Leave this pin
open if not used.
PVOUT: Power Output. The PVOUT pins connect to thepower output of the LED driver and also serve as the positive rail for the PWMTG drive. Bypass this pin to groundwith a ceramic capacitor. The bypass capacitor should beplaced as close to the chip as possible with vias directly
down to the ground plane.
SW2: Boost Side Switch Node. The SW2 pin connects tothe internal power switches and swings from ground toa diode voltage above PVOUT. Minimize the PCB area andtrace length to keep EMI low.
BST2: Boost Side Bootstrap Floating Driver Supply. The
BST2 pin connects to an integrated bootstrap diode fromthe INTVCC pin and requires an external bootstrap capacitor to the SW2 pin.
BST1: Buck Side Bootstrap Floating Driver Supply. The
BST1 pin connects to an integrated bootstrap diode fromthe INTVCC pin and requires an external bootstrap capacitor to the SW1 pin.
SW1: Buck Side Switch Node. The SW1 pin connects
to the internal power switches and swings from a diodevoltage drop below ground up to PVIN. Minimize the PCB
area and trace length to keep EMI low.
GND (Exposed Pad): Ground. Solder the exposed pad
directly to the ground plane.

Rev. 0For more information www.analog.com

11

LT3942BLOCK DIAGRAM
28

27

SW1

24

SW1

23

SW2 SW2

VLS
1
2
26

4

PVIN

A

D

PVOUT

PVIN

PVOUT

BST1

BST2
B

21
25

C

D1

INTVCC22

D2

INTVCC
3

LINEARREGULATORAND
REFERENCE

VIN
1.220V

918
19

BUCK LOGIC

BOOST LOGIC
PWM_INT

VREF
BUCK_MODERT+

OSCILLATOR

5

0.2V

CTRL

1.220V

1.220V
EN/UVLO

+
–

+
–

+
–
–
+

+ –

PWM
LOGIC

ISMON_INT
FB
0.95V

FAULT

0.25V
FB

+
–
+
–

0.75V
EA2

+
+
–

SS
1V
FB

16

+
+
–

CTRL
1.25V

12.5µAISMON_INT
10µA

LED
FAULT
LOGIC

250mV

+

ISP

–

ISN

A = 10PWM_INT

11
12

A =1

1.25µA

GND
29

7

V(ISP-ISN)

VREF

+
–

8

1.05V
EA1

+
–

0.35V

RP

FB

INHIBIT
SWITCH

2.5µA

14

PWM
A2

+ –

6

20

PVOUT – 5V

SYNC/SPRD

OVLO

PWMTG

BOOST_MODE

A1

10

PVOUT

SS
15

VC
17

ISMON
13

3942 BD

Rev. 012

For more information www.analog.com

LT3942OPERATION
The LT3942 is a current mode LED driver that can regulate
LED current from input voltage above, below or equal
to the LED string voltage. Four internal low resistanceN-channel DMOS switches minimize the size of the application circuit and reduce power losses to maximize efficiency. Internal high side gate drivers, which require only
the addition of two small external capacitors, further simplify the design process. The ADI proprietary peak-buckpeak-boost current mode control scheme directly senses
the inductor current across the internal power switches
and provides smooth transition between buck region,
buck-boost region and boost region. The LT3942 can be
configured to operate over a wide range of switching frequencies, from 300kHz to 2MHz, allowing applications tobe optimized for broad area and efficiency. Its operation
can be best understood by referring to the Block Diagram.
Power Switch Control

PEAK-BUCKPEAK-BOOST

Figure 1 shows the topology of the LT3942 power stage,
which is comprised of four N-channel DMOS switches
and their associated gate drivers. Figure 2 shows thecurrent mode control as a function of PVIN/PVOUT ratio
and Figure 3 shows the operation region as a function of
PVIN/PVOUT ratio. The power switches are properly controlled to smoothly transition between modes and regions.
Hysteresis is added to prevent chattering between modes
and regions.
CBST1

BST1

There are total four states: (1) peak-buck current mode
control in buck region, (2) peak-buck current mode control in buck-boost region, (3) peak-boost current mode
control in buck-boost region and (4) peak-boost current
mode control in boost region. The following sections givedetailed descriptions for each state with waveforms, inwhich the shoot-through protection dead time between
switches A and B, between switches C and D are ignored
for simplification.

PVIN SW1

SW2 PVOUTBST2INTVCC

Figure 2. Current Mode vs PVIN/PVOUT Ratio
(4)
BUCK

(2)

BOOST
(1)
0.75 0.85

D
INTVCCB
GND

1.00
PVIN/PVOUT

LT3942INTVCC3942 F02(3)

INTVCCA

1.04

PVIN/PVOUT

BUCK-BOOST

CBST2

L

1.00

1.25 1.33
3942 F03

Figure 3. Operation Region vs PVIN/PVOUT Ratio

C
GND
3942 F01

Figure 1. Power Stage Schematic

Rev. 0For more information www.analog.com

13

LT3942OPERATION(1) Peak-Buck in Buck Region (PVIN >> PVOUT)
When PVIN is much higher than PVOUT, the LT3942 uses
peak-buck current mode control in buck region (Figure 4).
Switch C is always off and switch D is always on. At the
beginning of every cycle, switch A is turned on and theinductor current ramps up. When the inductor current hits
the peak buck current threshold commanded by VC voltage at buck current comparator A1 during (A+D) phase,switch A is turned off and switch B is turned on for the
rest of the cycle. Switches A and B will alternate, behaving
like a typical synchronous buck regulator.

A

B

20%

C

20%

80%

D

IL

80%

A+D
A+C

A+D
B+D

A+C

B+D
3942 F05

A

Figure 5. Peak-Buck in Buck-Boost Region (PVIN ~> PVOUT)

B(3) Peak-Boost in Buck-Boost Region (PVIN <~ PVOUT)

C

100% OFFD

100% ON

IL

A+D

B+D

3942 F04

Figure 4. Peak-Buck in Buck Region (PVIN >> PVOUT)(2) Peak-Buck in Buck-Boost Region (PVIN ~> PVOUT)
When PVIN is slightly higher than PVOUT, the LT3942 uses
peak-buck current mode control in buck-boost region(Figure 5). Switch C is always turned on for the beginning 20% cycle and switch D is always turned on for theremaining 80% cycle. At the beginning of every cycle,
switches A and C are turned on and the inductor current
ramps up. After 20% cycle, switch C is turned off andswitch D is turned on, and the inductor keeps ramping
up. When the inductor current hits the peak buck current
threshold commanded by VC voltage at buck current comparator A1 during (A+D) phase, switch A is turned off andswitch B is turned on for the rest of the cycle.

When PVIN is slightly lower than PVOUT, the LT3942 uses
peak-boost current mode control in buck-boost region(Figure 6). Switch A is always turned on for the beginning 80% cycle and switch B is always turned on for theremaining 20% cycle. At the beginning of every cycle,
switches A and C are turned on and the inductor current
ramps up. When the inductor current hits the peak boost
current threshold commanded by VC voltage at boost
current comparator A2 during (A+C) phase, switch C isturned off and switch D is turned on for the rest of thecycle. After 80% cycle, switch A is turned off and switch
B is turned on for the rest of the cycle.
A

80%

80%

B

20%

20%

C

D

IL

A+D
A+C

A+D
B+D

A+C

B+D
3942 F06

Figure 6. Peak-Boost in Buck-Boost Region (PVIN <~ PVOUT)
Rev. 014

For more information www.analog.com

LT3942OPERATION(4) Peak-Boost in Boost Region (PVIN << PVOUT)
When PVIN is much lower than PVOUT, the LT3942
uses peak-boost current mode control in boost region(Figure 7). Switch A is always on and switch B is always
off. At the beginning of every cycle, switch C is turnedon and the inductor current ramps up. When the inductor current hits the peak boost current threshold commanded by VC voltage at boost current comparator A2
during (A+C) phase, switch C is turned off and switch D
is turned on for the rest of the cycle. Switches C and D
will alternate, behaving like a typical synchronous boost
regulator.
A

100% ON

B

100% OFF

C

D

IL

A+C

A+D

3942 F07

Figure 7. Peak-Boost in Boost Region (PVIN << PVOUT)

Main Control Loop
The LT3942 is a fixed frequency current mode LED driver.
The inductor current is directly sensed across the internal
switch A. The current sense voltage is added to a slope
compensation ramp signal from the internal oscillator.
The summing signal is then fed into the positive terminals of the buck current comparator A1 and boost current
comparator A2. The negative terminals of A1 and A2 arecontrolled by the voltage on the VC pin, which is the diodeOR of error amplifiers EA1 and EA2.
Depending on the state of the peak-buck peak-boost current mode control, either the buck logic or the boost logic

is controlling the four power switches so that either theFB voltage is regulated to 1V or the current sense voltage
between the ISP and ISN pins is regulated by the CTRL
pin during normal operation. The gains of EA1 and EA2
have been balanced to ensure smooth transition between
constant-voltage and constant-current operation with thesame compensation network.
Light Load Current Operation
At light load, the LT3942 typically still runs at its fullswitching frequency in discontinuous conduction mode.
Both buck and boost reserve current sense thresholds
are set to be zero, thus preventing any reverse current
flowing from the output to the input. In the buck region,
switch B is turned off whenever the buck reverse current
threshold is triggered during (B+D) phase. In the boost
region, switch D is turned off whenever the boost reverse
current threshold is triggered during (A+D) phase. In the
buck-boost region, switch D is turned off whenever theboost reverse current threshold is triggered during (A+D)
phase, and both switches B and D are turned off whenever
the buck reverse current threshold is triggered during(B+D) phase.
As the load becomes lower and lower, or when a smaller
value inductor is used and the inductor current ripple isbigger, the LT3942 may run in pulse-skip mode, where
the switches are held off for multiple cycles (i.e., skipping
pulses) to maintain the regulation.
Internal Charge Path
Each of the two high side gate drivers is biased fromits floating bootstrap capacitor CBST1 and CBST2, which
is normally recharged by INTVCC through the integrated
bootstrap diode D1 and D2 when the top power switch isturned off. When the LT3942 operates exclusively in thebuck or boost regions, one of the top power switches isconstantly on. An internal charge path, from PVOUT and
BST2 to BST1 or from PVIN and BST1 to BST2, charges
the bootstrap capacitor to above 3.3V so that the top
power switch can be kept on.

Rev. 0For more information www.analog.com

15

LT3942OPERATION
Shutdown and Power-On-Reset
The LT3942 enters shutdown mode and drains less than
2µA quiescent current when the EN/UVLO pin is below its
shutdown threshold (0.3V minimum). Once the EN/UVLO
pin is above its shutdown threshold (0.9V maximum), theLT3942 wakes up start-up circuitry, generates the bandgap reference and powers up the internal INTVCC LDO.
The INTVCC LDO supplies the internal control circuitry
and gate drivers. When the EN/UVLO is between 0.9V and
1.220V, the LT3942 enters undervoltage lockout (UVLO)
mode with a hysteresis current (2.5µA typical) pulled into
the EN/UVLO pin. When the INTVCC pin is charged above
its rising UVLO threshold (2.49V typical), the EN/UVLO
pin exceeds its rising enable threshold (1.235V typical)
and the junction temperature is less than its thermal shutdown (165°C typical), the LT3942 enters enable modeand the EN/UVLO hysteresis current is turned off. Whenthe voltage on the OVLO pin, which is programmed by aresistor divider from PVIN to GND, exceeds its 1.220V rising threshold (with 35mV falling hysteresis), the LT3942
enters overvoltage lockout (OVLO) mode. Only when bothUVLO and OVLO are cleared, the voltage reference VREF
can be charged up from ground to regulation. From thetime of entering enable mode to the time of VREF passing
its rising UVLO threshold (1.89V typical), the LT3942 isgoing through a power-on-reset (POR), waking up theentire internal control circuitry and settling to the right
initial conditions. After the POR, the LT3942 is ready andwaiting for the signals on the CTRL and PWM pins tostart switching.
Start-Up and Fault Protection
Figure 8 shows the start-up and fault sequence for theLT3942. In the POR state, the SS pin is hard pulled downwith a 100Ω to ground. In a pre-biased condition, the SS
pin has to be pulled below 0.2V to enter the INIT state,
where the LT3942 wait 10µs so that the SS pin can be
fully discharged to ground. After the 10µs, the LT3942
enters the UP/PRE state when the PWMON signal goeshigh. The PWMON high signal happens when the CTRL pin
is above its rising dim-off thresholds (0.225V typical) andthe external or internal PWM dimming is on.

POR = HI OR
ISOC = HI
POR

INIT

• SS HARD PULL-DOWN• SWITCHING DISABLED• PWMTG TURNED OFF• NO OPEN/SHORT DETECTION• SS HARD PULL-DOWN• SWITCHING DISABLED• PWMTG TURNED OFF• NO OPEN/SHORT DETECTION

SS < 0.2V

WAIT 10µs AND
PWMON = HI
UP/TRY

UP/PRE• SS 12.5µA PULL-UP• SWITCHING DISABLED• PWMTG TURNED ON• NO OPEN/SHORT DETECTION• SS 12.5µA PULL-UP• SWITCHING DISABLED• PWMTG TURNED OFF• NO OPEN/SHORT DETECTION

SS > 0.25V

WAIT 10µs
UP/RUN• SS 12.5µA PULL-UP• SWITCHING ENABLED• PWMTG TURNED ON• NO OPEN/SHORT DETECTION

OK/RUNSS > 1.75V• SS 12.5µA PULL-UP• SWITCHING ENABLED• PWMTG TURNED ON• OPEN/SHORT DETECTION

SS < 0.2V ANDPWMON = HI

OPEN LED ORSHORT LED

DOWN/STOP• SS 1.25µA PULL-DOWN• SWITCHING DISABLED• PWMTG TURNED ON• NO OPEN/SHORT DETECTION

FAULT/RUN
SS < 1.7V• SS 1.25µA PULL-DOWN• SWITCHING ENABLED• PWMTG TURNED ON• OPEN/SHORT DETECTION
3942 F08

Figure 8. Start-Up and Fault Sequence

During the UP/PRE state, the SS pin is charged up by a
12.5µA pull-up current while the switching is disabled
and the PWMTG is turned off. Once the SS pin is charged
above 0.25V, the LT3942 enters the UP/TRY state, where
the PWMTG is turned on first while the switching is still
disabled. This is to check that the voltage on the output capacitor is not too high for the LED string before
any switching energy delivery. If a higher voltage output
capacitor is connected to a lower voltage LED string, theexcessive current flowing through the LED string and thecurrent sense resistor triggers the ISP/ISN over current(ISOC) signal and resets the LT3942 back to the POR
state. So the LT3942 will hiccup between 0V and 0.25V
and go through the POR, INIT, UP/PRE and UP/TRY statesto slowly discharge the higher voltage output capacitor
until its voltage drops closer to the lower voltage LED
Rev. 016

For more information www.analog.com

LT3942OPERATION
string. After 10µs in the UP/TRY state without triggering
the ISOC signal, the LT3942 enters the UP/RUN state.
In the UP/RUN state, the switching is enabled and thestart-up of the output voltage PVOUT is controlled by thevoltage on the SS pin. When the SS pin voltage is lessthan 1V, the LT3942 regulates the FB pin voltage to theSS pin voltage instead of the 1V reference. This allows theSS pin to be used to program soft-start by connecting an
external capacitor from the SS pin to GND. The internal
12.5µA pull-up current charges up the capacitor, creating
a voltage ramp on the SS pin. As the SS pin voltage rises
linearly from 0.25V to 1V (and beyond), the output voltage PVOUT rises smoothly to its final LED string voltage.
Once the SS pin is charged above 1.75V, the LT3942
enters the OK/RUN state, where the LED fault (both open
LED and short LED) detection is activated. The open LED
indicates that VFB > 0.95V and V(ISP-ISN) < 10mV, andthe short LED indicates that VFB < 0.25V. Both the open
LED and short LED faults are reported to the FAULT pin.

When either fault occurs, the LT3942 enters the FAULT/RUN state, where a 1.25µA pull-down current slowly discharges the SS pin. Once the SS pin is discharged below
1.7V, the LT3942 enters the DOWN/STOP state, where
the switching is disabled and the LED fault detection isdeactivated with the previous fault latched. Once the SS
pin is discharged below 0.2V and the PWMON signal is still
high, the LT3942 goes back to the UP/RUN state.
In an open or short LED condition, the LT3942 can be set
to hiccup, latch-off, or keep-running fault protection modewith a resistor between the SS and VREF pins. Without any
resistor, the LT3942 will hiccup between 0.2V and 1.75V
and go through the UP/RUN, OK/RUN, FAULT/RUN and
DOWN/STOP states until the fault condition is cleared.
With a 499k resistor, the LT3942 will latch off until the
EN/UVLO is toggled. With a 100k resistor, the LT3942 willkeep running regardless of the fault.

Rev. 0For more information www.analog.com

17

LT3942APPLICATIONS INFORMATION

Switching Frequency Selection
The LT3942 uses a constant frequency control scheme
between 300kHz and 2MHz. Selection of the switchingfrequency is a trade-off between efficiency and component size. Low frequency operation improves efficiency
by reducing switching losses, but requires larger inductor
and capacitor values. For high power applications, consider operating at lower frequencies to minimize switching losses. For low power applications, consider operating
at higher frequencies to minimize the total solution size.
In addition, the specific application can play an importantrole in switching frequency selection. In a noise-sensitive
system, the switching frequency is usually selected tokeep the switching noise out of a sensitive frequency
band.

Spread Spectrum Frequency Modulation
Switching regulators can be particularly troublesome forapplications where electromagnetic interference (EMI) isa concern. To improve the EMI performance, the LT3942
implements a triangle spread spectrum frequency modulation scheme. With the SYNC/SPRD pin tied to INTVCC,
the LT3942 spreads its switching frequency 25% above
the internal oscillator frequency. Figures 9 and 10 show
the noise spectrum of the front page application with ferrite bead EMI filter and spread spectrum enabled.
CISPR 25 Average Conducted EMI
70
AVERAGE CONDUCTED EMI (dBµV)

The front page shows a typical LT3942 application circuit.
This Applications Information section serves as a guideline for selecting external components for typical applications. The examples and equations in this section assumecontinuous conduction mode unless otherwise specified.

CLASS 5 AVERAGE LIMITNOISE FLOORSSFM ON WITH FILTER

60
50
40
30
20
10
0
–10
–20
0.1

Switching Frequency Setting

Figure 9. Conducted Average EMI Comparison
CISPR 25 Peak Conducted EMI
80

PEAK CONDUCTED EMI (dBµV)

60

RT (kΩ)
178

400

124

600

78.7

800

56.2

1000

43.2

0

1200

33.2

1400

26.1

–10
0.1

21.5
17.4

2000

14.3

CLASS 5 PEAK LIMITNOISE FLOORSSFM ON WITH FILTER

70

300

1800

100
3942 F09

fOSC (kHz)

1600

10
FREQUENCY (MHz)The switching frequency of the LT3942 can be set by
the internal oscillator. With the SYNC/SPRD pin pulled to
ground, the switching frequency is set by a resistor fromthe RT pin to ground. Table 1 shows RT resistor values
for common switching frequencies.
Table 1. Switching Frequency vs RT Value (1% Resistor)

1

50
40
30
20
10

1

10

100

FREQUENCY (MHz)3942 F10

Figure 10. Conducted Peak EMI Comparison

Rev. 018

For more information www.analog.com

CISPR 25 Average Conducted EMI

LT3942APPLICATIONS INFORMATION
Frequency Synchronization
The LT3942 switching frequency can be synchronized toan external clock using the SYNC/SPRD pin. Driving the
SYNC/SPRD with a 50% duty cycle waveform is always agood choice, otherwise maintain the duty cycle between
10% and 90%. Due to the use of a phase-locked loop
(PLL) inside, there is no restriction between the synchronization frequency and the internal oscillator frequency.
The rising edge of the synchronization clock represents
the beginning of a switching cycle, turning on switches
A and C, or switches A and D.
Maximum Output Current
The LT3942 uses the PVIN/PVOUT ratio to transition
between modes and regions. The IR drop in the power
path caused by RDS(ON) of power switches and DCR of
inductor can limit the output current capability. The maximum output current at certain PVOUT is typically determined by:
IOUT ≤ 0.1 • VOUT
The RDS(ON) and DCR increase at higher junction temperature and the process variation have been included in
the calculation above.
Meanwhile, the maximum output current also depends on
minimum PVIN, maximum VLED, LED current and switch
peak current limit.
Inductor Selection
The switching frequency and inductor selection are interrelated in that higher switching frequencies allow the useof smaller inductor and capacitor values. The inductor
value has a direct effect on ripple current. The highest current ripple ∆IL% happens in the buck region at PVIN(MAX)and the lowest current ripple ∆IL% happens in the boost
region at PVIN(MIN). For any given ripple allowance, theminimum inductance can be calculated as:
L BUCK >(PVOUT • PVIN(MAX ) – PVOUT)fSW • ILED(MAX ) • ∆IL % • PVIN(MAX )L BOOST >(PVIN(MIN)2 • PVOUT – PVIN(MIN)fSW • ILED(MAX ) • ∆IL % • PVOUT)

2

where:fSW is switching frequency∆IL% is allowable inductor current ripple
PVIN(MIN) is minimum power input voltage
PVIN(MAX) is maximum power input voltage
PVOUT is output voltage
ILED(MAX) is maximum LED current
Slope compensation provides stability in constant frequency current mode control by preventing subharmonic
oscillations at certain duty cycles. The minimum inductance required for stability can be calculated as:
L>VOUT
2 • fSW • ISW (MAX )where:fSW is switching frequency
ISW(MAX) is maximum switch current limit = 2A (Min)For high efficiency, choose an inductor with low core loss,
such as ferrite. Also, the inductor should have low DC
resistance to reduce the I2R losses and must be able tohandle the peak inductor current without saturating. To
minimize radiated noise, use a shielded inductor.
CIN and COUT Selection
Input and output capacitance is necessary to suppress
voltage ripple caused by discontinuous current moving
in and out the regulator. A parallel combination of capacitors is typically used to achieve high capacitance and low
equivalent series resistance (ESR). Dry tantalum, special
polymer, aluminum electrolytic and ceramic capacitors
are all available in surface mount packages. Capacitorswith low ESR and high ripple current ratings, such as
OS-CON and POSCAP are also available.

Rev. 0For more information www.analog.com

19

LT3942APPLICATIONS INFORMATION
Ceramic capacitors should be placed near the regulator
input and output to suppress high frequency switching
spikes. Ceramic capacitors, ≥ 1µF, should also be placed
from PVIN/VIN to GND and PVOUT to GND as close to
the LT3942 pins as possible. Due to their excellent low
ESR characteristics, ceramic capacitors can significantly
reduce input ripple voltage and help reduce power loss
in the higher ESR bulk capacitors. X5R or X7R dielectrics are preferred, as these materials retain their capacitance over wide voltage and temperature ranges. Many
ceramic capacitors, particularly 0805 or 0603 casesizes, have greatly reduced capacitance at the desired
operating voltage.
Input Capacitance CIN
Discontinuous input current is highest in the buck region
due to the switch A toggling on and off. Make sure that theCIN capacitor network has low enough ESR and is sized
to handle the maximum RMS current. In buck region, theinput RMS current is given by:
IRMS ≈ ILED(MAX ) •

PVOUT
PVIN

•

PVIN
PVOUT

–1

The formula has a maximum at PVIN = 2PVOUT, where
IRMS = ILED(MAX)/2. This simple worst-case condition
is commonly used for design because even significant
deviations do not offer much relief.
Output Capacitance COUT
Discontinuous current shifts from the input to the output
in the boost region. Make sure that the COUT capacitor
network is capable of reducing the output voltage ripple.
The effects of ESR and the bulk capacitance must be considered when choosing the right capacitor for a given
output ripple voltage. The maximum steady state ripple
due to charging and discharging the bulk capacitance isgiven by:
∆ VCAP (BOOST ) =(ILED • PVOUT – PVIN(MIN )COUT • PVOUT • fSW)∆ VCAP (BUCK ) =⎞⎛PVOUT ⎟PVOUT • ⎜ 1–⎟
⎜ PV
IN(MAX ) ⎠⎝8 • L • fSW2 • COUT

The maximum steady ripple due to the voltage drop
across the ESR is given by:∆ VESR(BOOST ) =PVOUT • ILED(MAX )PVIN(MIN)

• ESR

⎞
⎛
PVOUT ⎟⎜PVOUT • 1–⎟
⎜ PV
IN(MAX ) ⎠⎝∆ VESR(BUCK ) =• ESR
L • fSWINTVCC Regulator
An internal P-channel low dropout regulator produces
3.6V at the INTVCC pin from the VIN supply pin. The
INTVCC powers internal circuitry and gate drivers in theLT3942. The INTVCC regulator can supply a peak current of 40mA and must be bypassed to ground with aminimum of 1µF ceramic capacitor. Good local bypass isnecessary to supply the high transient current requiredby power switch gate drivers.
Higher input supply voltage applications with higher
switching frequencies may cause the maximum junction temperature rating for the LT3942 to be exceeded.
The system supply current is normally dominated by
the gate charge current that drives the four internal
power switches.
To prevent maximum junction temperature from being
exceeded, the input supply current must be checked operating in continuous mode at maximum PVIN/VIN.
High Side Gate Driver Supply (CBST1, CBST2)
The high side gate drivers for the two top power switches,
A and D, are driven between their respective SW and BST
pin voltages. The boost voltages are biased from floatingbootstrap capacitors CBST1 and CBST2, which are normallyrecharged through internal bootstrap diodes D1 and D2
Rev. 020

For more information www.analog.com

LT3942APPLICATIONS INFORMATION
when the respective top power switch is turned off. Bothcapacitors are charged to the same voltage as the INTVCC
voltage. In most applications, a typical 0.1µF, X5R or X7R
dielectric capacitor is adequate.

PVIN
R3
OVLO

Programming PVIN UVLO and OVLO

GND

A resistor divider from PVIN to the EN/UVLO pin implements PVIN undervoltage lockout (UVLO). The EN/UVLO
enable falling threshold is set at 1.220V with 15mV hysteresis. In addition, the EN/UVLO pin sinks 2.5µA when thevoltage on the pin is below 1.220V. This current provides
user programmable hysteresis based on the value of R1.
The programmable UVLO thresholds are:
VIN(UVLO+ ) = 1.235V •VIN(UVLO– ) = 1.220V •R1+ R2R2+ 2.5µA • R1

R1+ R2R2

Figure 11 shows the implementation of external shutdown
control while still using the UVLO function. The NMOS
grounds the EN/UVLO pin when turned on and puts theLT3942 in shutdown with quiescent current less than 2µA.
PVIN
R1EN/UVLO
R2

LT3942GND

RUN/STOPCONTROL(OPTIONAL)

3942 F12

Figure 12. PVIN Overvoltage Lockout (OVLO)

Programming LED Current
The LED current is programmed by placing an appropriate
value current sense resistor, RLED, in series with the LED
string. The voltage drop across RLED is (Kelvin) sensed
by the ISP and ISN pins. The CTRL pin should be tied to a
voltage higher than 1.35V to obtain the full-scale 100mV
obtain (typical) threshold across the sense resistor. The
CTRL pin can be used to dim the LED current to zero,
although relative accuracy decreases with the decreasing
sense threshold. When the CTRL pin voltage, VCTRL, isless than 1.15V, the LED current is:V– 250mV
ILED = CTRL
10 • RLED

When VCTRL is between 1.15V and 1.35V, the LED current
varies with VCTRL, but departs from the equation above
by an increasing amount as VCTRL increases. Ultimately,when VCTRL > 1.35V the LED current no longer varies. The
typical V(ISP-ISN) threshold vs VCTRL is listed in Table 2.
Table 2. V(ISP-ISN) Threshold vs VCTRL

3942 F11

Figure 11. PVIN Undervoltage Lockout (UVLO)

A resistor divider from PVIN to the OVLO pin implements
PVIN overvoltage lockout (OVLO). The OVLO risingthreshold is set at 1.220V with 35mV falling hysteresis.
Figure 12 shows the implementation of PVIN OVLO function. The programmable OVLO thresholds are:
VIN(OVLO+ ) = 1.220V •VIN(OVLO– ) = 1.185V •R3 + R4R4
R3 + R4R4R4LT3942VCTRL (V)

V(ISP-ISN) (mV)

1.15

90

1.20

94.5

1.25

98

1.30

99.5

1.35

100

When VCTRL is higher than 1.35V, the LED current is regulated to:
ILED =

100mV
RLED

Rev. 0For more information www.analog.com

21

LT3942APPLICATIONS INFORMATIONThe CTRL pin should not be left open (tie to VREF if notused). The CTRL pin can also be used in conjunction witha thermistor to provide overtemperature protection for
the LED load, or with a resistor divider to PVIN to reduce
output power and switching current when PVIN is low.
The presence of a time varying differential voltage ripple
signal across ISP and ISN at the switching frequency is
expected. The amplitude of this signal is increased byhigher LED load current, lower switching frequency orsmaller value output filter capacitor. Some level of ripple
signal is acceptable, and the compensation capacitor
on the VC pin filters the signal so the average difference
between ISP and ISN is regulated to the user-programmed
value. The ripple voltage amplitude (peak-to-peak) in
excess of 20mV should not cause mis-operation, but may
lead to noticeable offset between the average value andthe user-programmed value.
Monitoring LED Current
The ISMON pin provides a linear indication of the current
flowing through the LEDs. It outputs a buffered and amplified value of the voltage difference between ISP and ISN
pins. The equation for VISMON is:
VISMON = 10 • V(ISP–ISN) + 250mV
Dimming Control
There are two methods to control the LED current for dimming using the LT3942. One method uses the CTRL pin toadjust the current regulated in the LEDs. A second method
uses the PWM pin to modulate the LED current between
zero and full current to achieve a precisely programmed
average current.
Compared to the analog dimming method, the PWM dimming method offers much higher dimming ratio without
any color shift. To make PWM dimming more accurate, theswitch demand current is stored on the VC node when the
PWM signal is low. This feature minimizes recovery time
when the PWM signal goes high. To further improve therecovery time, a high side PMOS PWM switch should be
used in the LED current path to prevent the output capacitor from discharging during the PWM signal low phase.
The choice of switching frequency, inductor value andloop compensation affects the minimum PWM on time,22

below which the LT3942 loses the LED current regulation.
For the same application, the LT3942 achieves the highest
PWM dimming ratio (up to 5000:1) in buck region, themedium PWM dimming ratio (up to 2500:1) in buck-boost
region and the lowest PWM dimming ratio (up to 2000:1)
in boost region.
In either fixed frequency operation set by RT resistor or
spread spectrum frequency operation, the internal oscillator is synchronized to the PWM signal rising edge, thereby
providing flicker-free PWM dimming performance. In
external frequency synchronization operation, both SYNC
and PWM signals must have synchronized rising edges toachieve flicker-free PWM dimming performance.
The LT3942 provides both external PWM dimming andinternal PWM dimming. For external PWM dimming,choose RP resistor less than 30k and apply an external
PWM clock signal to the PWM pin. For internal PWM
dimming, choose RP resistor to one of the seven resistor values in Table 3 and apply analog DC voltage to the
PWM pin. The RP resistor sets the internal PWM dimming
frequency, and the 1V to 2V analog DC voltage on the
PWM pin sets the internal PWM dimming duty ratio from
0% to 100% with a discrete 1/128 step size, as shownin Figure 13.
Table 3. Internal PWM Dimming Frequency vs RP Value(1% Resistor)
RP (kΩ)fSW

fSW = 200kHzfSW = 1MHzfSW = 2MHz

< 20

External

External

External

External

28.7

fSW/28781Hz

3.91kHz

7.81kHz

47.5

fSW/29391Hz

1.95kHz

3.91kHz

76.8

fSW/210

195Hz

977Hz

1.95kHz118

fSW/211
fSW/212fSW/213fSW/214

98Hz

488Hz

977Hz

49Hz

244Hz

488Hz

24Hz

122Hz

244Hz

12Hz

61Hz

122Hz

169
237
332
100

ALWAYSON

PWMTG DUTY 50
RATIO (%)
0

ALWAYSOFF
3942 F13

0

0.5

1.0

1.5
PWM (V)

2.0

2.5

3.0

Figure 13. Internal PWM Dimming Duty Ratio vs PWM Voltage

For more information www.analog.com

Rev. 0LT3942APPLICATIONS INFORMATIONHigh Side PMOS PWM Switch Selection
A high side PMOS PWM switch is recommended in mostLT3942 applications to maximize the PWM dimming
ratio and protect the LED string during fault conditions.
Compared to a low side NMOS PWM switch, the high side
PMOS PWM switch allows a single wire to the LED string
and ground return path through chassis. The high side
PMOS PWM switch is typically selected for drain-source
voltage VDS, gate-source threshold voltage VGS(TH) andcontinuous drain current ID. For proper operations, VDS
rating should exceed the open LED regulation voltage set
by the FB pin, the absolute value of VGS(TH) should be lessthan 3V, and ID rating should be above ILED(MAX).

PWMTG to disconnect the LED string for protection. The
output overvoltage threshold can be set as:
VOUT(OVP ) = 1.05V •R5 + R6
R6

Make sure the expected VFB during normal operation
stays between the short LED rising threshold 0.3V andthe open LED falling threshold 0.9V:
0.3V ≤ VLED •R6
R5 + R6≤ 0.9V

These equations set the maximum LED string voltage withfull open LED protection for the LT3942 to be 34V.

Programming Output Voltage and Thresholds

FAULT Pin

The LT3942 has a voltage feedback pin FB that can beused to program a constant-voltage output. The output
voltage can be set by selecting the values of R5 and R6(Figure 14) according to the following equation:

The LT3942 provides an open-drain status pin, FAULT,
which is pulled low during either open LED or short LED
conditions. The open LED condition happens when the FB
pin is above 0.95V and the voltage across V(ISP-ISN) is lessthan 10mV. The short LED condition happens when the
FB pin is below 0.25V. The FAULT status is updated when
the SS pin is above 1.75V and the PWM signal is high.

VOUT = 1.00V •R5 + R6
R6
PVOUT

Soft-Start and Fault Protection

R5
FB
R6

LT3942
GND

3942 F14

Figure 14. Feedback Resistor Connection

In addition, the FB pin also sets output overvoltage threshold, open LED threshold and short LED threshold. For an
LED driver application with small output capacitors, theoutput voltage usually overshoots a lot during an open
LED event. Although the 1.00V FB regulation loop tries toregulate the output, the loop is usually too slow to preventthe output from overshooting. Once the FB pin hits its
overvoltage threshold 1.05V, the LT3942 stops switchingby turning off all four power switches and also turns off

As shown in Figure 8 and explained in the Operation section, the SS pin can be used to program soft-start by connecting an external capacitor from the SS pin to ground.
The internal 12.5µA pull-up current charges up the capacitor, creating a voltage ramp on the SS pin. As the SS pin
voltage rises linearly from 0.25V to 1V (and beyond), theoutput voltage rises smoothly and transitions into LED
current regulation. The soft-start range is defined to be
the voltage range from 0V to the FB voltage in LED current regulation. The soft-start time can be calculated as:tSS = VLED •

R6

•

CSS

R5 + R6 12.5µA

Make sure CSS is at least five to ten times larger than thecompensation capacitor on the VC pin. A 22nF ceramic
capacitor is a good starting point.

Rev. 0For more information www.analog.com

23

LT3942APPLICATIONS INFORMATIONThe SS pin is also used as a fault timer. Once an open
LED or a short LED fault is detected, a 1.25µA pull-downcurrent source is activated. Using a single resistor fromthe SS pin to the VREF pin, the LT3942 can be set to threedifferent fault protection modes: hiccup (no resistor),latch-off (499k) and keep-running (100k).
With a 100k resistor in keep-running mode, the LT3942
continues switching normally, either regulating the programmed PVOUT during open LED fault or regulating thecurrent during short LED fault. With a 499k resistor inlatch-off mode, the LT3942 stops switching until the EN/
UVLO pin is pulled low and high to restart. With no resistor in hiccup mode, the LT3942 enters low duty cycle
auto-retry operation. The 1.25µA pull-down current discharges the SS pin to 0.2V and then 12.5µA pull-up current charges the SS pin up. If the fault condition has notbeen removed when the SS pin reaches 1.75V, the 1.25µA
pull-down current turns on again, initiating a new hiccup
cycle. This will continue until the fault is removed.
Loop Compensation
The LT3942 uses an internal transconductance error
amplifier, the output of which, VC, compensates the control loop. The external inductor, output capacitor, andthe compensation resistor and capacitor determine theloop stability.
The inductor and output capacitor are chosen based on
performance, size and cost. The compensation resistor
and capacitor on the VC pin are set to optimize control
loop response and stability. For a typical LED application,
a 2.2nF compensation capacitor on the VC pin is adequate,
and a series resistor should always be used to increase
the slew rate on the VC pin to maintain tighter regulationof LED current during fast transients on the input supplyof the converter.

Efficiency Considerations
The power efficiency of a switching regulator is equal tothe output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Although all dissipative
elements in circuits produce losses, four main sources
account for most of the losses in LT3942 circuits:
1. DC I2R losses. These arise from the resistancesof the MOSFETs, sensing resistor, inductor and PC
board traces and cause the efficiency to drop at highoutput currents.
2. Transition loss. This loss arises from the brief amountof time switch A or switch C spends in the saturated
region during switch node transitions. It depends
upon the input voltage, load current, driver strengthand MOSFET capacitance, among other factors.
3. INTVCC current. This is the sum of the MOSFET driverand control currents.
4. CIN and COUT loss. The input capacitor has the difficult job of filtering the large RMS input current to theregulator in buck region. The output capacitor has thedifficult job of filtering the large RMS output current inboost region. Both CIN and COUT are required to have
low ESR to minimize the AC I2R loss and sufficient
capacitance to prevent the RMS current from causing
additional upstream losses in fuses or batteries.
When making adjustments to improve efficiency, the input
current is the best indicator of changes in efficiency. If you
make a change and the input current decreases, then theefficiency has increased. If there is no change in the input
current, then there is no change in efficiency.

Rev. 024

For more information www.analog.com

LT3942TYPICAL APPLICATIONS
93% Efficient 12W (12V, 1A) 2MHz Buck-Boost LED Driver
L1
3.3µH
0.1µF

3V TO 36V

+

10µF

22µF

SW1

SW2

BST2
PVOUT

LT3942

12VLED
1A

1M

GND
ISP

115k

ISN

OVLO

PWMTG

34.8k
INTVCCEXT SYNC

10µF

M1

64.9k
EN/UVLO

1M

100mΩ

FB

VIN

1µF

499k

BST1
PVIN

0.1µF

SSFM ONSYNC
NO SSFM/SYNC
FAULT

VREF

SYNC/SPRD
PWM

VREF

FAULT

2.2µF

ANALOG DIM
100k

100k

91k
INT
EXT/ON
EXT PWM DIM

ISMON

100k
INTVCC

100k

INTVCCCURRENT MONITOR

RP
332k
122Hz

CTRL
VREF

SS

VREF

0.1µF
0.22µF

D1: NEXPERIA PMEG2010EJ
L1: WURTH ELEKTRONIK 74438336033
M1: VISHAY SI2365DS

RT

VC
3.9k

14.3k
2MHz

3.3nF

INT
EXT/ON3942 TA02

Rev. 0For more information www.analog.com

25

LT3942TYPICAL APPLICATIONS
12W (12V, 1A) 2MHz Buck-Boost Voltage Regulator
L1
3.3µH
0.1µF

3V TO 36V

+

10µF

22µF
402k

BST1
PVIN

0.1µF

SW1

SW2

BST2
PVOUT

110k

50mΩ
47µF

4.7µF

12V
1A

FB

VIN

1µF

4.7µF

+

10k

1M

EN/UVLO

LT3942

GND

280k

10Ω

ISP
OVLO

1µF

ISN

10Ω

34.8k
INTVCCEXT SYNCSSFM ONSYNC
NO SSFM/SYNC

ISMON

SYNC/SPRD

VREF

PWM
FAULT

FAULT

100k

100k
INTVCCCURRENT MONITOR

PWMTG

2.2µF

CTRL
INTVCC
VREF

VREF

73.2k

RP
SS

VC

100k

RT
75k

0.1µF
0.22µF

14.3k
2MHz

L1: WURTH ELEKTRONIK 78438336033

680pF
3942 TA03

Rev. 026

For more information www.analog.com

LT3942TYPICAL APPLICATIONS
8W (24V, 330mA) 2MHz Buck-Boost LED Driver
L1
6.8µH
0.1µF

3V TO 36V

+

BST1
PVIN

10µF

22µF

SW1

270mΩ
4.7µF

M1

1M

24VLED330mA

35.7k
LT3942

GND
ISP

280k

ISN

OVLO

PWMTG

34.8k
INTVCCEXT SYNC

BST2
PVOUT
FB

EN/UVLO
1M

SW2

VIN

1µF

402k

0.1µF

SSFM ONSYNC
NO SSFM/SYNC
FAULT

VREF

SYNC/SPRD
PWM

VREF

FAULT

2.2µF

60.9k
100k

100k

91k
INT
EXT/ON
EXT PWM DIM

ISMON

100k
INTVCC

100k

INTVCCCURRENT MONITOR

RP
332k
122Hz

CTRL
VREF

SS

VREF

0.1µF
0.22µF

L1: COILCRAFT XEL4030-682ME
M1: VISHAY SI2319CDS

RT

VC
2.2k
4.7nF

INT
EXT/ON

14.3k
2MHz3942 TA04

Rev. 0For more information www.analog.com

27

LT3942TYPICAL APPLICATIONS
5W (6.5V, 800mA) 2MHz Buck-Boost LED Driver
L1
2.2µH
0.1µF

3V TO 36V

+

4.7µF

22µF

SW1

120mΩ
22µF

M2

1M

6.5VLED
800mA

124k
LT3942

GND
ISP

280k

ISN

OVLO

PWMTG

34.8k
INTVCCEXT SYNC

BST2
PVOUT
FB

EN/UVLO
1M

SW2

VIN

1µF

402k

BST1
PVIN

0.1µF

SSFM ONSYNC
NO SSFM/SYNC
FAULT

VREF

SYNC/SPRD
PWM

VREF

FAULT

2.2µF

110k
100k

100k

91k
INT
EXT/ON
EXT PWM DIM

ISMON

100k
INTVCC

100k

INTVCCCURRENT MONITOR

RP
332k
122Hz

CTRL
VREF

SS

VREF

0.1µF
0.22µF

RT

VC
3.3k
2.2nF

INT
EXT/ON

L1: WURTH ELEKTRONIK 74438336022
M1: VISHAY SI2329DS

14.3k
2MHz
3942 TA05

Rev. 028

For more information www.analog.com

LT3942
PACKAGE DESCRIPTIONUFD Package
28-Lead Plastic QFN (4mm × 5mm)

(Reference LTC DWG # 05-08-1712 Rev C)

0.70 ±0.05

4.50 ±0.05
3.10 ±0.05
2.50 REF

2.65 ±0.05
3.65 ±0.05

PACKAGE OUTLINE

0.25 ±0.05
0.50 BSC
3.50 REF
4.10 ±0.05
5.50 ±0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONSAPPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
4.00 ±0.10(2 SIDES)

0.75 ±0.05

R = 0.05
TYP

PIN 1 NOTCH
R = 0.20 OR 0.35
× 45° CHAMFER

2.50 REF
R = 0.115
TYP
27

28
0.40 ±0.10

PIN 1
TOP MARK(NOTE 6)1
2

5.00 ±0.10(2 SIDES)

3.50 REF
3.65 ±0.10
2.65 ±0.10(UFD28) QFN 0816 REV C

0.200 REF

0.25 ±0.05

0.00 – 0.05

0.50 BSC
BOTTOM VIEW—EXPOSED PAD

NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGHD-3).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATIONON THE TOP AND BOTTOM OF PACKAGE

Rev. 0Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license For
is granted
implication orotherwise under any patent or patent rights of Analog Devices.
more byinformationwww.analog.com

29

LT3942TYPICAL APPLICATION
Sequential Turn and Day Time Running
M3 TO M9

33k

L1
6.8µH

33nF

0.1µF
PVIN

FB1

EMIVIN
6V TO 18V

10µF

+

33µF

10µF

402k
1M

GND

1µF

102k

BST1
PVIN

SW2

100k

220nF

VIN
LT3942

GND

VREF

VCC

D_IO1
D_IO2
D_IO3
D_IO4
D_IO5
D_IO6
D_IO7
D_IO8
D_IO9
D_IO10
D_IO11
D_IO12

GND
FAULT

D_IO0

54.9k

INTVCC

µC

ISP

ISP

ISN

ISN

M12

RT

2.4k

510k

U1A

100k
FAULT

SSFM
ON
OFF

RP

0.1µF

ISN

INTVCC

FAULT

VC

FB2

DRAIN

VREF

SYNC/SPRD

0.1µF

ISP

56.2k

2.2µF

SS

M2
DRAIN
SHUNT1SHUNT2SHUNT3
SHUNT4
SHUNT5SHUNT6SHUNT7
AMBER
WHITE

383k

INTVCC

PWM

300mΩ

10k
10k

CTRL
5V
1µF

4.7µF

FB

EN/UVLO
VREF

PVOUT

BST2
PVOUT

34.8k

M1

U1 TO U4

0.1µF

SW1

OVLO

5V

1.5nF

INTVCCM3+U1BSHUNT1

M4+U2ASHUNT2

M5+U2BSHUNT3

M6+U3ASHUNT4

M7+U3BSHUNT5

M8+U4ASHUNT6

M9+U4BSHUNT7

14.3k
2MHz

AMBER
M10

15nF

M11

U5A
WHITE

FB1: TDK MPZ2012S331AT
FB2: TDK MPZ2012S102AT
L1: WURTH ELEKTRONIK 78438357068
M1, M2: ONSEMI 2N7002
M3 - M12: VISHAY Si2318CDS
U1 - U5 ONSEMI NC7WZ16P6X

PVIN
4.7µF

510k

10nF

IN
OUT
LT3065-5 OUT
IN
SHDN
SENSE
PWRGD
ADJ
IMAX
REF/BYP
GND
4.7k

U5B

5V
4.7µF
1nF

10nF
3942 TA06

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