X2SON – the smallest Logic leadless packages for use without step-down mask

Ultra-small 4, 5, 6 & 8-pin
MicroPak packages
with ≥ 0.4 mm pitch

Nexperia has developed the X2SON packages, part of MicroPak packages, to provide
the smallest footprint for logic functions while ensuring pad pitch remains 0.4mm
or over, making step-down masks unnecessary. Our X2SON packages are available in
low-power AUP, AXP, LV and LVC technology families covering over one hundred logicfunctions. Additional types are continuously added and the miniaturization processcontinues with the recent introduction of X2SON4. This new 4-pin package option
reduces footprint by 44% compared to the 5-pin X2SON5.
Key features›› Smaller footprint (up to -36% vs. GF & -25% vs. GN packages)›› High contact area-to-chip ratio and enhanced durability›› RoHS & dark-green compliant with NiPdAu leadframe finish›› Low profile height (0.35mm) and low width (0.8mm)
Benefits›› Lower PCB costs, easier placement and miniaturization›› No step-down stencil, lowering cost & facilitating assembly›› Future-proof, part of Nexperia’s recommended packages

Package name

Package version

Applications›› Mobile devices›› Portable computing›› IoT & wearables›› Consumer electronics
Most Mini Logic functions from the Nexperia portfolio are
now offered in X2SON, our smallest-footprint logic plastic
packages. The innovative X2SON package with GX/GX4 suffix
was introduced in 2012 with X2SON5, followed by X2SON6in 2015, X2SON8 in 2016 and X2SON4 in 2018. Nexperia has
been leading package innovation in logic and driving thetrend toward smaller packages and more power-efficienttechnologies and will continue to do so.

L (mm)W (mm)H (mm)P (mm)

SuffixX2SON4

SOT1269

0.60.60.32

≥ 0.4

GX4

X2SON5

SOT12260.8

0.80.35≥ 0.4

GX

X2SON6

SOT1255

1.00.80.35

≥ 0.4

GX

X2SON8

SOT1233

1.35

0.80.35≥ 0.4

GX

74AUP1G00

2-input NAND gate•

74AUP1T00

Translating 2-input NAND gate•

74AUP1G02

2-input NOR gate•

74AUP1T02

Translating 2-input NOR gate•

74AUP1G04

Inverter•

74AUP1T04

Translating inverter•

74AUP1G06

Inverter; open-drain•

74AUP1T08

Translating 2-input AND gate•

74AUP1G07

Buffer; open-drain•

74AUP1T14

Translating Schmitt-Trigger Inverter•

74AUP1G08

2-input AND gate•

74AUP1T17

Translating Schmitt-Trigger Buffer•

74AUP1G09

2-input AND gate; open-drain•

74AUP1T32

Translating 2-input OR gate•

74AUP1G125

Buffer/line driver (3-state)•

74AUP1T34

Dual supply translating buffer•

74AUP1G126

Buffer/line driver (3-state)•

74AUP1T50

Translating Schmitt-Trigger Buffer•

74AUP1G132

2-input NAND gate; Schmitt-trigger•

74AUP1T86

Translating 2-input X-OR gate•

74AUP1G14Inverter; Schmitt-trigger•

74AUP1T87

Translating 2-input X-NOR gate•

74AUP1G157

2-input multiplexer

74AUP1T97

Translating configurable gate

74AUP1G17

Buffer; Schmitt-trigger

74AVC1T45

Dual supply translating transceiver

74AUP1G240

Inverter/line driver (3-state)•

74AUP1G32

2-input OR gate•

74AXP1T14

Dual supply translating inverter;
Schmitt-trigger

74AUP1G3208

3-input OR-AND gate

74AUP1G34

Buffer••••••

74AUP1G38

2-input NAND gate; open-drain

74AUP1G57

Configurable gate; Schmitt trigger•••

74AUP1G58

Configurable gate; Schmitt trigger

74AUP1G74

D-type flip-flop with set and reset

74AUP1G79

D-type flip-flop; positive-edge trigger•

74AUP1G80

D-type flip-flop; positive-edge trigger•

74AUP1G86

2-input XOR gate•

74AUP1G97

Configurable gate; Schmitt trigger•

74AUP1G98

Configurable gate; Schmitt trigger•

74AUP1GU04

Unbuffered inverter•

74AXP1G00

2-input NAND gate•

74AXP1G02

2-input NOR gate••

74AXP1G04

Inverter•

74AXP1G06

Inverter; open-drain•

74AXP1G07

Buffer; open-drain•

74AXP1G08

2-input AND gate•

74AXP1G09

2-input AND gate; open-drain

Dual supply 2-input OR gate

74AXP1T34

Dual supply translating buffer

74AXP1T57

Dual supply translating configurablegate; Schmitt-trigger

74LV1T00

Translating 2-input NAND gate•

74LV1T02

Translating 2-input NOR gate•

74LV1T04

Translating inverter•

74LV1T08

Translating 2-input AND gate•

74LV1T32

Translating 2-input OR gate•

74LV1T34

Translating buffer•

74LV1T86

Translating 2-input X-OR gate•

74LV1T87

Translating 2-input X-NOR gate•

74LV1T125

Translating buffer; 3-state•

74LV1T126

Translating buffer; 3-state•

Description•

X2SON8••74AXP1T32

2G & 3G
Dual- &Triple-Gates

X2SON6••••

X2SON8•

X2SON5•

X2SON4•

X2SON6

Description

X2SON5

1T Single
Translators

X2SON4

X2SON8

X2SON6

X2SON5

Description

X2SON4

1G
Single-Gates

74AXP1G125

Buffer/line driver (3-state)•74AUP2G00

2-input NAND gate

74AXP1G14

Inverter; Schmitt-trigger•

74AUP2G04

Inverter•

74AXP1G17

Buffer; Schmitt trigger•

74AUP2G07

Buffer; open-drain•74AXP1G32

2-input OR gate•

74AUP2G082-input AND gate•

74AXP1G57

Configurable gate; Schmitt trigger•

74AUP2G125

Buffer/line driver (3-state)•74AXP1G58

Configurable gate; Schmitt trigger•

74AUP2G126

Buffer/line driver (3-state)•74AXP1G86

2-input XOR gate

74AUP2G132

2-input NAND gate; Schmitt-trigger

74AXP1G97

Configurable gate; Schmitt trigger

74AUP2G14

Inverter; Schmitt-trigger

74LVC1G00

2-input NAND gate•

74AUP2G32

2-input OR gate

74LVC1G02

2-input NOR gate•

74AUP2G34

Buffer•

74AUP3G34

Buffer•

74AXP2G07

Buffer; open-drain••

74AXP2G14

Inverter; Schmitt trigger••

74LVC2G002-input NAND gate

74LVC2G04

Inverter•

74LVC1G04

Inverter

74LVC1G06

Inverter; open-drain

74LVC1G07

Buffer; open-drain

74LVC1G08

2-input AND gate

74LVC1G113-input AND gate

•
••
•

•••
•
••
•

•

74LVC1G125

Buffer/line driver (3-state)•

74LVC2G06

Inverter; open-drain•

74LVC1G126

Buffer/line driver (3-state)•74LVC2G07

Buffer; open-drain•74LVC1G14

Inverter; Schmitt-trigger••

74LVC2G08

2-input AND gate

74LVC1G17Buffer; Schmitt-trigger••

74LVC2G32

2-input OR gate

74LVC1G3157

SPDT analog switch

74LVC2G34

Buffer

74LVC1G32

2-input OR gate

74LVC2G38

2-input NAND gate; open-drain•

74LVC1G332

3-input OR gate

74LVC2G86

2-input XOR gate•

74LVC1G34

Buffer•
••
•

•
•

•

74LVC1G38

2-input NAND gate; open-drain•Available functions

74LVC1G384

SPDT analog switch•

74LVC1G79

D-type flip-flop; positive-edge trigger•

74LVC1G80

D-type flip-flop; positive-edge trigger•›› Buffers & Inverters›› Gates (AND, NAND, OR,

74LVC1G86

2-input XOR gate•

74LVC1G97

Configurable gate; Schmitt trigger

74LVC1GU04

Unbuffered inverter••

NOR, XOR, XNOR)›› Schmitt-Triggers© 2018 Nexperia B.V.
All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent ofthe copyright owner. The information presented in this document does not form part of any quotationor contract, is believed to be accurate and reliable and may be changed without notice. No liability willbe accepted by the publisher for any consequence of its use. Publication thereof does not convey nor
imply any license under patent- or other industrial or intellectual property rights.

nexperia.com•›› Flip-Flops›› Configurable Gates›› Translators›› Analog Switches

Date of release:
June 2018
Printed:In the Netherlands