WIZ830MJ Datasheet(Ver. 1.1)

© 2008 WIZnet Inc. All Rights Reserved.
For more information, visit our website at www.wiznet.co.kr

WIZ830MJ Datasheet

Document History Information
RevisionVer. 1.0
Ver.1.1

DataJune 04, 2008
July 29, 2008

Description
Release with WIZ830MJ Launching
Modified dimensions(Symbol B and C).

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Datasheet© Copyright 2008 WIZnet Inc. All rights reserved

WIZ830MJ Datasheet

WIZnet’s Online Technical Support
If you have something to ask about WIZnet Products, Write down your question
on Q&A Board in WIZnet website (www.wiznet.co.kr). WIZnet Engineer will give ananswer as soon as possible.

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WIZ830MJ Datasheet

Table of Contents

1.

Introduction .............................................................................. 5
42.

3.

1.1.

Features ................................................................................................... 5

1.2.

Block Diagram .......................................................................................... 5

Pin Assignments & descriptions ................................................... 6
2.1.

Pin Assignments ....................................................................................... 62.2.

Power & Ground ....................................................................................... 7

2.3.

MCU Interfaces ........................................................................................ 72.4.

Network Indicator LED Signals ................................................................. 82.5.

Miscellaneous Signals .............................................................................. 8

Timing Diagrams ....................................................................... 9
3.1.

Reset Timing ............................................................................................ 9

3.2.

Register / Memory READ Timing.............................................................. 93.3.

Register / Memory WRITE Timing .......................................................... 104.

Dimensions ............................................................................. 115.

Schematic .............................................................................. 126.

Partlists .................................................................................. 13© Copyright 2008 WIZnet Inc. All rights reservedTOP
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1. Introduction
WIZ830MJ is the network module that includes W5300 (TCP/IP hardwired chip, include PHY),
MAG-JACK (RJ45 with X’FMR) with other glue logics. It can be used as a component and noeffort is required to interface W5300 and Transformer. The WIZ830MJ is an ideal option for users
who want to develop their Internet enabling systems rapidly.
For the detailed information on implementation of Hardware TCP/IP, refer to the W5300
Datasheet.
WIZ830MJ consists of W5300 and MAG-JACK.
 TCP/IP, MAC protocol layer: W5300
 Physical layer: Included in W5300
 Connector: MAG-JACK(RJ45 with Transformer)

1.1. Features

Supports 10/100 Base TX
High network performance : Up to 50Mbps
Supports half/full duplex operation
Supports auto-negotiation and auto cross-over detection
IEEE 802.3/802.3u Compliance
Operates 3.3V with 5V I/O signal tolerance
Supports network status indicator LEDs
Includes Hardware Internet protocols: TCP, IP Ver.4, UDP, ICMP, ARP, PPPoE, IGMP
Includes Hardware Ethernet protocols: DLC, MAC
Supports 8 independent connections simultaneously
Supports MCU bus Interface
Supports Direct/Indirect mode bus access
Supports 16/8 bit data bus width
Supports memory-to-memory DMA (only 16bit Data bus width & slave mode)
Supports Socket API for easy application programming
Supports hybrid TCP/IP stack(software and hardware TCP/IP stack)Supports PPPoE connection (with PAP/CHAP Authentication mode)
More flexible allocation internal TX/RX memory according to application throughput
Interfaces with two 2.54mm pitch 2 x 14 header pin

1.2. Block Diagram© Copyright 2008 WIZnet Inc. All rights reserved

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2. Pin Assignments & descriptions
2.1.

Pin Assignments

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I : Input
I/O : Bi-directional Input and output© Copyright 2008 WIZnet Inc. All rights reserved

O : Output
P : PowerWIZ830MJ Datasheet

2.2.

Power & GroundSymbol

Type

VCCP

GND

P

Pin No.
J1:1,
J1:18,
J2:16,

J2:1
J2:10,
J2:23,

Description
Power : 3.3 V power supply
J2:15,
J2:24

Ground72.3.

MCU Interfaces
Pin No.

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Symbol

TypeDescription

A[9:0]

I

J2:19 ~ J2:28

D[15:8]I/O

J1:2 ~ J1:9

D[7:0]

I/O

J1:10 ~ J1:17/CS

I

J2:19

Module Select : Active low.
/CS of W5300/RDIJ2:20

Read Enable : Active low.
/RD of W5300

/WRI

J2:21

Write Enable : Active low/WR of W5300

Address
Used as Address[9-0] pinData
16 bit-wide high data bus
In case of using 8 bit data bus, there are driven as
High-Z
Data
16 bit-wide low data bus

/INTO

J2:18

Interrupt : Active low
After reception or transmission it indicates that theW5300 requires MCU attention.
By writing values to the Interrupt Register(IR) ofW5300 the interrupt will be cleared by host.
All interrupts can be masked by writing values tothe IMR of W5300 (Interrupt Mask Register).
For more details refer to the W5300 Datasheet

BIT16ENI

J2:2

16/8 bit data bus select.
High : 16 bit data bus
Low : 8 bit data bus.

© Copyright 2008 WIZnet Inc. All rights reserved

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WIZ830MJ Datasheet

2.4.

Network Indicator LED Signals

SymbolType/LINKLEDO/TXLED/RXLED/COLLED/FDXLED/SPDLED/ACTLED

OO

OO

OO

Pin No.

Description

J2:3

Link LED
It indicates the link status ofmedia(10/100M).

J2:4

Transmit activity LED : Transmit
EnableIt notifies the output of transmit data
through TXOP/TXON(Transmit Activity).

J2:5

Receive activity LED : Transmit Data
It notifies the input of receive data fromRXIP/RXIN (Receive Activity)

J2:6

Collision LED : Transmit Data
It notifies when collisions occur.
It is valid at half-duplex, and is ignored atfull-duplex.

J2:7

Full duplex LED : Transmit Data
It outputs low at the full-duplex andoutputs high at the halfduplex
according to auto-negotiation or manual
configuration of OP_MODE[2:0].

J2:8

Link speed LED : Transmit Data
It is asserted low at the 100Mbps andhigh at the 10Mbps
according to auto-negotiation or manual
configuration of OP_MODE[2:0].

J2:9

Activity LED
It notifies the output of transmit data
through TXOP/TXON or the input ofreceive data from RXIP/RXIN.

2.5. Miscellaneous Signals
Symbol/RESET

TypeIPin No.

Description

J2:17

Reset : This pin is active low input toinitialize or re-initialize W5300.
RESET should be held at least 2us after
low assert, and wait for at least 10ms
after high de-assert in order for PLL logic
to be stable
Buffer Ready Indicator
BRDYn monitors TX/RX memory statusof each socket.
For more details refer to the W5300
Datasheet

BRDY[3:0]

OJ2:11 ~ J2:14

NC-J2 : 22, J2:25,
J2:27,
J2:28© Copyright 2008 WIZnet Inc. All rights reserved

J2:26,

Not Connect

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3. Timing Diagrams
WIZ830MJ provides following interfaces of W5300.
-. Direct/Indirect mode bus access

3.1.

Reset Timing

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Description
Reset Cycle Time
PLL Lock-in Time123.2.

Min
2 us50us

Max
10 sRegister / Memory READ Timing

DescriptiontADDRstADDRhtCS
tCSntRDtDATAstDATAhtDATAheAddress Setup Time after /CS and /RD low
Address Hold Time after /CS and /RD high
/CS Low Time/CS Next Assert Time
/RD Low TimeDATA Setup Time after /RD low
DATA Hold Time after /RD and /CS high
DATA Hold Extension Time after /CS high© Copyright 2008 WIZnet Inc. All rights reservedMinMax

65ns
28ns
65ns
42ns
-7ns
7ns
2XPLL_CLK

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WIZ830MJ Datasheet

3.3.

Register / Memory WRITE Timing

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DescriptiontADDRstADDRhtCS
tCSntWRtDATAstDATAftDATAh

Address Setup Time after /CS and /WR low
Address Hold Time after /CS or /RD high/CS low Time/CS next Assert Time/WR low Time
Data Setup Time after /WR low
Data Fetch Time
Data Hold Time after /WR high© Copyright 2008 WIZnet Inc. All rights reservedMinMax

50ns
28ns
50ns
7ns
14ns
7ns

7ns
-

7ns + 7XPLL_CLKtWR – tDATAs-WIZ830MJ Datasheet

4. Dimensions

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DatasheetSymbols

Dimensions (mm)Symbols

Dimensions (mm)

A

34.00

H6.50

B

30.48

I

2.54

C

25.40

J

2.54

D

3.00

K

15.90

E4.00

L

13.50

F50.00M

6.00

G3.30--© Copyright 2008 WIZnet Inc. All rights reserved

WIZ830MJ Datasheet

5. Schematic

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6. Partlists
Item

Q.ty

1

16

2

4

3
4
5

Reference
C1,C2,C3,C4,C5,
C7,C12,C13,C14,
C15,C16,C17,C18,
C20,C22,C23

Part

Tech. Characteristics

Package

0.1uF

50V-20% Ceramic

CASE 0603

C6,C8,C10,C11,10uF/16V16Vmin 10%EIA/IECQ 3216

121C9C19,C21
D116Vmin 10%
50V-20% Ceramic

EIA/IECQ 3216
CASE 0603
SC-59

63FB1,FB2,FB3

1uH, 50mA

CASE 0805

71FB4120 Ohm /100MHz

CASE 0805

82J1,J2

2 X 14 2.54mm pitch

DIP

910111213
1415161718
1911124011111R1
R2
R3
R4,R5
R6,R7,R8,R9
R10,R11,R13
R12U1U2
Y13.3uF/16V18pF
1SS1811uH
Chip Ferrite Inductor
120 Ohm Ferrite BEAD
2X14 28PIN 2.54mm
DIP STRAIGHT Header
12K (1%)300 (1%)

1/10W-1% SMD
1/10W-1% SMD
1/10W-5% SMD
1/10W-5% SMD
1/10W-1% SMD
1/10W-5% SMD
1/10W-5% SMD
WIZnet Hardware TCP/IP
Transformer + RJ-45
SMD Type, CL=18pF
1.6T 4LAYER

CASE 0603
CASE 0603
CASE 0603
CASE 0603
CASE 0603
CASE 0603
CASE 0603
LQFP100

1M
200
49.9 (1%)
Not mounted
4.7K
W5300
RJ113BZ
25MHz(SMD)
WIZ830MJ REV1.0 PCB© Copyright 2008 WIZnet Inc. All rights reserved

SX-1

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