1

Dream-Chip Project by ASET
(Final Results)
March 8th, 2013

Integration Basic Technology Research Lab.
3D-Integration Technology Research Development
Association of Super-Advanced Electronics Technologies ( ASET )This project is entrusted by NEDO “Development of Functionally Innovative 3D-Integrated Circuit (Dream Chip) Technology” .
The project is based on the Japanese government's METI “IT Innovation Program”.
March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

2Contents•Overview•Ultra-wide Bus SiP 3D Integration Technology•Mixed Signal 3D-Integraction Technology•Heterogeneous 3D integration technology•3D integration technology•Thermal / Chip Stacking Technology•Thin Wafer Technology•Design Environment technology•Chip Test Technology

March 8, 2013

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©2013 Association of Super-Advanced Electronics Technologies

3Dream-Chip Project by ASET

Overview

Harufumi Kobayashi

Integration Basic Technology Research Lab.
3D-Integration Technology Research Development
Association of Super-Advanced Electronics Technologies ( ASET )March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

4■ Organization
3D-Integration Technology Research Department : Hiroaki Ikeda
Standardization : Morihiro Kada
Integration Basic Technology Research Lab. : Harufumi Kobayashi(3)-CUltra-wide Bus SiP 3D Integration Technology : Shiro Uchiyama(3)-D

Digital-Analog 3D Integration Technology : Tadashi Kamada(3)-E

Heterogeneous 3D Integration Technology : Fumihiko Nakazawa(3)-B

3D-Integration Technology : Kenichi Takeda(2)-B

Thermal Management / Chip Stacking Technology : Fumiaki Yamada(2)-CThin Wafer Technology : Haruo Shimamoto

Project CodeMarch 8, 2013

Early Accomplished Project (FY2010)(1)-A Design Environment(2)-A Chip Test

©2013 Association of Super-Advanced Electronics Technologies

5■Activities■ Efficiently Element design technology with TSV■ Ultra-wide Bus SiP
・ 3D SiP Development■ Digital-Analog 3D■ Heterogeneous 3D・ Car driving support image
processing system

・ Creation of the new functional device

Application to 3D process anddesign technology■ 3D Process , Elemental Analysis Technology■ 3D Integration■ Thermal / Chip Stacking Technology ■ Thin Wafer
・ Thin Wafer Process Technology
・ 3D integration Technology
・ High Power Dissipation Technology
・ Elemental Circuit Technology
・ C2C（Chip to Chip） Bonding Technology
・ Device Characterization

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

6■Activities
Ultra-wide Bus SiP

Digital-Analog 3D（Memory + logic）（ image processing for Vehicle)

Sensor + Signal processing
Quality of Multi Power Supply
Interposer practical use

Ultra High pin count Design
PackagingOperation Noise reduction
DFT・Redundancy(MEMS)Non Silicon 3D Integration
High Frequency Signal Processing

By combining these elemental

Sensor Network
Apparatus

Ultra small , thin

Heterogeneous 3D

Multi Function
High Performance

Low Power Consumption
High Reliability

technologies, a market can beprovided with ultra small and multifunctions, and the apparatus
corresponding to a low power
consumption system to suitable cost
and time.

Via Last Process,W2W stacking
3D Integration TEG
10μm thickness wafer process
Thermal / Stress Evaluation Technology
High-speed Signal Transmission
Fine pitch C2C Bonding Technology Characteristic change of a thinned devic

3D Integration(Circuit , Process）

Thermal Management/
Chip Stacking
March 8, 2013

Thin Wafer©2013 Association of Super-Advanced Electronics Technologies

■ Ultra-wide Bus SiP 3D Integration Technology

7■ 3D SiP Development of Ultra-wide bus memory which canemploy the feature of TSV efficiently.
・ Connection between logic and memory with 4,096
bit width.
・ Throughput （100GB/sec）, Low power consumption

Epoxy
Resin
Under Fill

Sectional View

Logic

Organic
Interposer
Solder Ball

Top Side View

Back Side View

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

■ Digital-Analog 3D Integration Technology

8■ Technology development of the car driving support image
processing system
・ Development of Module with 2 sensor which can be measured Distance・ The distance between mutual sensor modules is 20 mm
・ Time-axis Distance measuring technology:10,000fps

Assembled in rearview mirror
CIS
CDS
ADC
IF

CIS
CDS
ADC
IF
Si-IP
DeCap
Organic
AlN

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

■ Heterogeneous 3D Integration Technology

9■ Creation of the new functional device by integration ofsilicon device and LTCC based device
・ The WLP package MEMS device optimized to 3D integration
・ CMOS Control IC
Optimization of circuit and physical interface design

Resistive VIA

Ceramic Filter
Substrate

Integrated wiring

CMOS control device

Raising ring
Connecting pad

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

10■ 3D Integration Technology■ 3D integration process technology
・ Development of Via Last TSV process
・ Development of W2W（Wafer on Wafer） stacking process■ Elemental circuit technology with TSV・ Modeling of TSV Electrical property
・ Layout design
・ Communication circuit of integrated device with TSV

To Core Circuit
4th Layer
4層目(B)
3rd Layer
3層目(A)
2nd Layer
2層目(A)
1st Layer
1層目(A)

I/O[0]

I/O[2]

I/O[1]

I/O[3]

2nd layer

Interposer
Siインターポーザー

200μm(b) 断面SEM写真

1st layer

4th Layer
4層目(B)

Bump
表バンプ

TSV

Bump
←バンプ

3rd Layer
3層目(A)TSV←TSVInterposer

2nd Layer
2層目(A)
4 Layer
４層積層Interposer
Siインターポーザー(a) SEM
鳥瞰SEM写真Photo(1)

1st Layer
1層目(A)

100μm

Interposer
Siインターポーザー

50μm(c) SEM
断面SEM写真（拡大）
Photo
(2)

March 8, 2013

I/O[0]

I/O[1]

I/O[2]

I/O[3]

Elemental Circuit (Integrated I/O )©2013 Association of Super-Advanced Electronics Technologies

■Thermal Management / Chip Stacking Technology

11■ Efficient cooling technology
・ Development of simulation and evaluation technology■ C2C（Chip to Chip） bonding technology
・ Bonding pin count : over 10,000 bumps / cm2■ Efficient cooling technology

CIS

CIS

CDS

CDS

ADC

ADC

IF

IF

■ C2C bonding technology

Si Interposer

インターポーザ

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

12■Thin Wafer Technology■ Thin wafer process technology
・ Process technology on 10μm thickness wafer■ Characteristic change of a thinned device
・ Elucidation of gettering effect

300mmφ10μm t thinned wafer

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

13■ ES#2：3D Integration TEG -1/2
■ 2008～2010：Basic technology Development on 3D Integration■ 2011～2012：design , Manufacturing , TSV Process , Evaluation
・ Wafer ： 300mm
・ Process rule：90nm
・ 3D Process:TSV , W2W , C2C
30mm
10mm

■ Thermal / Chip Stacking
Technology

25mm■ 3D-Integration Technology

10mm■ Ultra-wide Bus SiP
3D Integration Technology

5mm■ Thin Wafer Technology

5mmMarch 8, 2013©2013 Association of Super-Advanced Electronics Technologies

14■ ES#2：3D Integration TEG -2/2
■ Wafer～Bump/TSV/W２W,C2C～Evaluation
Wafer Photograph

bump

W2W 1
TSV/Bump

W2W 2
TSV/Bump

Dicing

Evaluation

C2C

Evaluation

Wafer#1

W2W

Wafer#2
Wafer#3
Bump/TSV

DicingWafer#1

C2C

Wafer#2
Wafer#3

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

15(3) Fundamental Technology Development and Design Definition of 3D Integration
Multifunctional High Density 3D Integration Technology(3)-C Ultra-wide Bus SiP 3D Integration Technology

Shiro Uchiyama

Integration Basic Technology Research Lab.
3D-Integration Technology Research Development
Association of Super-Advanced Electronics Technologies ( ASET )March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

16(3)-C Ultra-wide Bus SiP 3D Integration Technology

Possibility of the 3D structure to enable the memory by ultra wide bus
and the mutual combination of the logic.
Achievement of 3D structure including 4,096 ultra wide bus
between memory and logic.
Inserting Si interposer between memory and logic to secure
the flexibility of the terminal position of logic and memory.
We build 3D design technique including DFT.
Evaluation of the noise reduction technology and the transmission
energy.

〔Memory bus width and transmission ability (band width)〕

10000
Bus width

By introducing a ultra wide bus structure
100GByte/sec can be obtained.
Band Width (GB/sec)

Data transfer rate of current DRAM+Logic structure becomes
10GB/sec now, but it is necessary to maintain structure to largely
improve memory transmission ability between logics to meeta future performance demand (2 times/generation).
The interconnection by ultra wide bus more than the 1K bit widthis necessary.
To largely reduce energy for transmission, bus capacitanceless than ratio 1/10 conventionally is need.

Background

8192
4096
2048
1024
512
256
128
64

1000

100

10
100

200

400

800

1600

3200

Bus Speed (Mb/sec)[ Improvement of the transfer efficiency ]Evaluation of super low capacitance TSV structure to enablea technological advance of Si interposer.
We evaluate structure and the manufacturing method that can form
TSV insulation film of Silica filler.
Structure to enable bus capacitance reduction
largely reduces transmission energy.

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

17(3)-C Ultra-wide Bus SiP 3D Integration Technology

Challenges

Basic concept and advantage, Challenge of 3D SiP- Large reduction of the chip area
Advantage : Liberation from shrinkage trend by 3D structure, high density of system, etc
Challenge : Construction of 3D design technology, KGD, Thermal density increase, etc- Introduction of vertical connection concept (TSV)
Advantage : Reduction of wiring, Ease to increase bus width, etc
Challenge : Fine pitch TSV fabrication, Mass productions technology such as W2W technologies, etc- Introduction of heterogynous process and structure
Advantage : Variety of system choice, etc
Challenge : Diversification of a connection signal, power supply, etc< 3D-SiP Structure >4k I/O Wide Bus (micro Bump)- Construction of 3D SiP
3 die stacking structure (SRAM / Interposer / Logic) .
Transmission ability of ultra wide bus (4k I/O).
The circuitry which reduces a noise and transmission energy.
The high efficiency system connected with many pins.

SRAM
Si Interposer
TSV

Logic
Organic Interposer- Evaluation of super low capacitance TSV.
The TSV insulation film formation with Silica filler.
Design of application structure and the process.
Confirmation of application possibility to Interposer.

< Evaluation structure of Silica filler >March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

18(3)-C Ultra-wide Bus SiP 3D Integration Technology

R&D subject（3C1） Development of Ultra-wide Bus SiP 3D Integration Technology
We develop a 3D design technology including Si Interposer of ultra wide bus memory to be able to make use oftechnical superiority of 3D structure in greatly and evaluate SSO noise of ultra wide bus 3D SiP quantitatively anddemonstrate the effectiveness of the measures circuit.

MCHIP
Control Circuit- 100GByte/s data transmission in 4096 I/O, 200Mbit/s- SSO noise reduction by the phase-shift mode transmission

Data RAM- Technical establishment of 3D SiP test by the DFT construction- Establishment of the DFM technology including theredundancy technology and multi pin connection

Wide Bus I/F
Si-IP

MultiPin

DoubleBufferCommand

Clock

Redundancy
MemoryWide Bus I/F

Wide Bus I/F・・

RAM Port I/F

Data Register
Command

Acknowledge

SiInterposer

・・Control Circuit

PLL

Noise
Generator

Logic

Voltage
Monitor

Wide Bus I/F

Organic Substrate
LCHIP
Reset

Clock

Normal Bit (32)

Monitor Signal

March 8, 2013

Red. Bit (1)©2013 Association of Super-Advanced Electronics Technologies

(3)-C Ultra-wide Bus SiP 3D Integration Technology

19

Goal

Final target ：Trial manufacture of 3D SiP which interconnected a logic and ultra wide bus memory (more than 2k bit
bus width and ability for transmission 100GByte/s) in interposer evaluates it and inspects 3D SiP
superiority in the characteristics such as transmission ability or the consumption electricity.
We utilize result of the development of the signal transmission with the ultra wide bus and we
produce it experimentally and estimate it as improvement examination of the further control techniqueand get a prospect of the development that we included standardization in.
We perform the TEG implementation evaluation of silica filler insulating layer formation techniqueand get a prospect of the practical use.

Effect :・Design, DFT, DFM technology establishment of the ultra high band width information system
・Large reduction of the transmission energy
・Realization of high-performance Interposer by the super low capacitance TSV application

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

20（3C1） Ultra-wide Bus SiP 3D Integration Technology

Results

By connecting a logic, Si-IP, memory directly, because of low consumption energy and 4,096 bits I/O,
Development target is 100GByte/s(@200Mbit/s) bandwidth.

TotalInterconnects# of
Signals

VDD/GND

Redundancy
& NC

①

7,328

4,568

2,006

754

②

729

277

452

-

③

527

263

264

-

①
②
③

Memory+Si Interposer+
Logic

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

21（3C1） Ultra-wide Bus SiP 3D Integration Technology

Results
The primary design SiP develops construction of basic architecture, DFT, DFM, 4096I/O function.
The second design SiP develops evaluation of 100GByte/s transmission properties and the electricity.

Primary Design 3D-SiP (ES#1)

Second Design 3D-SiP (ES#2)

MemoryMemorySRAM

Test Circuit

SRAM Test Circuit
Wide I/O I/F

Wide I/O I/F

Si Interposer

Active Si Interposer

4096b
TSV

Signal/Power
Monitor Circuit

4096b
TSV

Logic
Logic

Wide I/O I/F

Wide I/O I/F
Monitor
SignalNoise Monitoring
Circuit

Test Circuit

Test Signal
March 8, 2013

Monitor
SignalTest Circuit
Test Signal©2013 Association of Super-Advanced Electronics Technologies

22（3C1） Ultra-wide Bus SiP 3D Integration Technology

Results
We constructed 3D SiP fabrication process at Via Last TSV and made use of these supply chain.

FEOL

TSV・Bump

Assembly

Foundry

ASET

OSAT

MemoryLogic
SiInterposer（Second
Design)F-Bump90nm Cu
M8 Routing
WSS Detach
Dicing

D2D StackUnderfill

D2S StackOver-Mold

Foundry

Si
Interposer（Primary
Design)350nm Al
M4 Routing

F-Bump
WSS
Thinning
Via-Last
B-BumpOrganic Interposer
March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

23（3C1） Ultra-wide Bus SiP 3D Integration Technology

Results

Primary design SiP develops a structure design and evaluation environment.
Second design SiP follows the 3D structure and takes measures with malfunction.
Primary Design 3D SiP
Logic

Si Interposer

Chip Size
Wafer

Second Design 3D SiP
Memory9.93mmx9.93mm
90nm Shuttle
TEG

350nm Shuttle
TEG

Active Si
Interposer

Logic

Memory9.93mmx9.93mm
90nm Shuttle
TEG

90nm Shuttle TEG

TSV Depth

50um

-

50um

-

TSV Diameter

20um

-

20um

-

TSV Pitch

200um

TSV
Fabrication

Connection
Underfill

200um

-

Via-Last

Assembly
Stacking

-

50um

OSAT

Face up
SolderFace down
SolderCUF(3)-C Ultra-wide Bus SiP 3D Integration
Technology-

Via-Last

OSAT
Face up-

50um

Face upFace up
SolderFace down
Solder

CUF

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

24（3C1） Ultra-wide Bus SiP 3D Integration Technology

Results
We made layout rules about TSV and Bump to take the adjustment of Foundry shuttle wafer and OSAT .

With Wafer Support Systems
OSAT Design Rule

trate
s
b
u
Si S
Foundry Design Rule

trate
s
b
u
Si S
F-BumpThinning
TSV
March 8, 2013

B-Bump©2013 Association of Super-Advanced Electronics Technologies

25（3C1） Ultra-wide Bus SiP 3D Integration Technology

Results

For the adjustment with organic IP located in a logic and the lower part, TSV for external signal / power supplies
was located around a chip edge, and 4096 I/O was located in chip center.

Logic

Si Interposer

Primary Design
3D SiP

Second Design
3D SiP

March 8, 2013

MemoryBank 4

Bank 0Bank 5

Bank 1

Bank 6

Bank 2

Bank 7

Bank 3

Bank 4

Bank 0Bank 5

Bank 1

Bank 6

Bank 2

Bank 7

Bank 3©2013 Association of Super-Advanced Electronics Technologies

（3C1） Ultra-wide Bus SiP 3D Integration Technology

26

Results

We assemble BGA package consist of ultra wide bus 3D SiP and build 3D system of the supermany pins connection.

MemorySiInterposer
MemoryLogic
TSV (50um Pitch)
Organic
Interposer

Logic

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

27（3C1） Ultra-wide Bus SiP 3D Integration Technology

Results
Memory area tested by BIST, and wide bus circuit tested using JTAG, another Logic circuit
checked using SCAN technology .

MCHIP
Control
Data RAM
Wide-Bus I/F

JTAG

SRAM
SRAM

BIST

Si-IP

4K-IO with
Redundancy IOs

Wide-Bus I/F

RAM Port I/F

Data Register

Command

Acknowledge

Control

SCAN
①

②

③

PLL

Noise
Generator

Test In

Voltage
Monitor

Test Out

LCHIP
Reset

CLK IN

Monitor

SignalTest Block Diagram
March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

28（3C1） Ultra-wide Bus SiP 3D Integration Technology

Results

We connect a test signal to not only the probe pad but also the Bump pad to carry out the test thatis similar to a wafer level and 3D SiP.
Primary Design 3D SiP
Wafer Level
Test Item

Second Design 3D SiP

3D SiP

Wafer Level

3D SiP

Logic

MemoryLogic

MemoryLogic

MemoryLogic

MemoryPower Lane Short

●

●

●

●

●

●

●

●

Pin Leak

●

●

●

－

●

●

●

－

IO Open/Short

●

●

●

－

●

●

●

－

Interconnect IO Loop

●

●

－

－

●

●

－

－

SCAN

●

●

●

●

●

●

●

●

MBIST

●

●

●

●

－

●

－

●

JTAG

－

－

●

●

－

－

●

●

Connection

－

－

●

●

－

－

●

●

PLL/DLL

●

●

●

●

●

●

●

●

TSV Path

－

－

●

●

－

－

●

●

Function

－

－

●

●

－

－

●

●

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

29（3C1） Ultra-wide Bus SiP 3D Integration Technology

Results

I/O to function the data transmission of the wide bus composes of a variable driver for an ability
for bus transmission evaluation, and operates at 1.2V ( mini-I/O ).

SiInterposer

Logic
Mini I/OO

Mini I/O

Bus Keeper

TSV & Bump

IO

I

MemoryIO

0.25mA

0.25mA

E2

I
E

E
E1

O

I/O
Control

0.50mA0.50mA

1.00mA

1.00mA

2.00mA

2.00mA

E1
I/O
Control
E2

Schematic diagram of Mini-I/O buffer circuit
March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

30（3C1） Ultra-wide Bus SiP 3D Integration Technology

Results

For simultaneous switching noise reduction of 4096 I/O, it is equipped with the phase-shift modewith the phase adjustment circuit, We reduce rush current by shifting the phase of the datatransmission timing.

Simultaneous 4k-I/O write/Read

Memory

V

τ

×4096
I

Rush Current of I/O

Logic
Phase Shift Mode

Logic

Logic

March 8, 2013

Δt

Δt

×512

Δt

×512

V

×512

Δt

×512

Δt

×512

Δt

×512

Δt

×512

×512

Δt

In case of 2k+2k Operation

Memory
×2048

×2048

MemoryΔtI

Rush Current reductionΔt©2013 Association of Super-Advanced Electronics Technologies

31（3C1） Ultra-wide Bus SiP 3D Integration Technology

Results

Bank is divided into 16 segments (32bits/segment). In each segment, phase shift circuit inserts
delay into master clock with 0.1ns step to generate slave clock.
X’tal

SEL

Master
Clock

Segment

Data[0]

Phase
Shift

Data[1]

Slave
Clock

Memory

x8
Bank

...

Bank

x8

Phase Shift Circuit

Segment

Clock Leaf
(Normal Circuit)

・・・

PLL

Logic

...

Clock
Phase
Clock

Data[31]
Data[32:63]
Data[64:95]
Data[96:127]
Data[128:159]
Data[160:191]
Data[192:223]
Data[224:255]
Data[256:287]
Data[288:319]
Data[320:351]
Data[352:383]
Data[384:415]
Data[416:447]
Data[448:479]
Data[480:511]

March 8, 2013

Phase
Shift

Operation Example
Master Clock
0.1ns

Slave
Clock

Data[0:31]
Data[32:63]
Data[64:95]
Data[96:127]
Data[128:159]
Data[160:191]
Data[192:223]
Data[224:255]©2013 Association of Super-Advanced Electronics Technologies

32（3C1） Ultra-wide Bus SiP 3D Integration Technology

Results

Maximum SSO noise has measured at 75MHz. This results is well coincident with the frequency ofanti-resonance peak of total PDN impedance (80MHz).
Total PDN impedances

IEEE CPMT Symposium Japan 2012
"PDN characteristics of 3D-SiP with a Wide-bus Structure Under
4k-IO Operations", by Atsushi Sakai et al
Best Paper Award

Measured SSO Noise waveform @ 4k-bit Write operation
I/O Strength： 0.5 mA, Monitor point：Bank4, 13 Level Phase Shift

50MHz

75MHz

100MHz200MHzw/ Phase Shift

w/o Phase
Shift

Clock
VDD

28mV

43mV

32mV

25mV

18mV

32mV

26mV

20mV

Clock
VDD

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

33（3C1） Ultra-wide Bus SiP 3D Integration Technology

Results

Even 200Mbit/s bus operation, comparative low speed realizes bus transmission ability of 102GByte/s
by constituting I/O to make use of 3D structure and achieves transmission energy of 0.56pJ/bit.
Tck - Vddm Shmoo

Vddm (V)

1.35

Consumption Energy dependence of Band width

● (5

A

5

A …, W mode)

(5

A

5

A …, R mode)■# of sample: 3

1.3
1.25

Iddm (mA)
400

PASS

5

A …, W mode)

(5

A

5

A …, R mode)

200
150

1.1

(0

100

FAIL

(0

102.4 GB/s

0.95

A

250

1.15

1

(5

300

1.2

1.05

350

Iddm = 385 mA (5 -> A, W mode)
Data Transfer Energy : 0.56 pJ/bit

10

4 4.5 5 5.5 6 6.5 7 7.5
Tck (nsec)

March 8, 20130
0

(all bit 1, R mode)

F
F

0
0

F …, W mode)
F …, R mode)(all bit 1, W mode)

20
40
60
80 100
Data bandwidth (GByte/s)

120©2013 Association of Super-Advanced Electronics Technologies

（3C1） Ultra-wide Bus SiP 3D Integration Technology

34

Results

We succeed in the monitor of the TSV I/O signal and evaluate ability for I/O strength dependence,and even ability for I/O strength of 0.25mA confirms that signal transmission is possible.

Voltage (V)

Vdd

1.2
1
0.8
0.6
0.4
0.2
0

Mini I/O
Rx
Tx

Measurement of I/O Signal

mBump
Vss

Eye diagram
capture05Mini I/O strength0.25 mA
0.50 mA
1.00 mA
2.00 mA

10

Time (ns)15

Vdd capture
Vss capture20

Tck = 5 ns
Timing resolution: 40 ps
Voltage resolution: 2 mVMarch 8, 2013

TSV and mBump

Mini I/O
Rx
Tx©2013 Association of Super-Advanced Electronics Technologies

35（3C1） Ultra-wide Bus SiP 3D Integration Technology

Results

For an ability for I/O strength optimization, We measure an eye opening using Vdd / Vss / signal monitor,
We confirm the change of the eye opening with a change of the ability for I/O strength.
ISSCC 2013
"A 100GB/s Wide I/O with 4096b TSVs Through an Active Silicon Interposer with In-Place
WaveformCapturing", by Satoshi Takaya,et al

Optimum Choice
I/O Strength: 0.50 mA
Vddm
A 5
1.2

I/O Strength: 0.25 mA

Voltage (V)

1.2

Vddm

A
5

0.8

5
A

0.8

0.4
0
0

5

I/O Strength: 1.00 mA
Vddm
A 5
1.2

A

0.8

0.4
A

5

Vss 5

A

1

2

3 4 5
Time (ns)

0
6

7

0

5

A

A

5

0.4
A

5

Vss 5
1

2

0

A
3 4 5
Time (ns)6

Tck = 5 ns
March 8, 2013

7

0

Vss 5
1

A
2

3 4 5
Time (ns)6

Timing resolution: 40 ps
Voltage resolution: 50 mV©2013 Association of Super-Advanced Electronics Technologies

736（3C1） Ultra-wide Bus SiP 3D Integration Technology

Results

We carry out a study of super low capacitance TSV enabling many function Interposer. We carry out
the TEG implementation evaluation of the silica filler insulating layer formation technique andestablish structure and the manufacturing method.

Lt an c
paci
a
C
ow

e TS

V

Si Interposer

Logic

TSV insulating layer

It is necessary to form a thick insulating layer to fabricate super low capacitance TSV.
-> Insulation film formation technology of film thickness more than 2um (CVD Filling limit - 2um).
-> Voidless and seamless property in the wide trench part.
-> Correspondence of the different trench width.
-> Reduction of the TSV stress.
Because it is not Dimension of Front-End process, we try development of Back-End
technology.
(Consideration of the development at Bump and TSV line)
We examine an application to the TSV insulation film formation with silica filler.
March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

37（3C1） Ultra-wide Bus SiP 3D Integration Technology

Results

We choose each element, condition of silica filler insulating layer formation and build a wafer process.
TEG implementation is a silica filler of the TSV sidewall insulation and evaluation of TSV conductor.

TEG structure

GND PAD① Annular Trench formation
・Leakage・Capacitance V

Daisy Chain

TSV Capacitance900②

y = 0.033 x

800

Silica filler fill

Cu
paste

③

Anneal (>500deg)

Capacitance [pF]

700

y = 0.0356x

600
500

TSV insulating layer：4um
TSV capacitance：33fF/TSV

400
300
200

Silica filler
Isolation

ECD Cu - TSV
Cu Paste - TSV

100
0
0

④

Liquid Silica coat /AnnealMarch 8, 2013

1000

2000

3000 4000# of TSV

5000

6000

7000

©2013 Association of Super-Advanced Electronics Technologies

(3)-C Ultra-wide Bus SiP 3D Integration Technology

38

Summary

1. Design technology development of the ultra wide bus SiP structure- We built the supply chain which ultra wide bus 3D SiP by devising a standard to takethe adjustment of Foundry, TSV, Bump process ,OSAT could produce experimentally.
- By constitution of I/O using 3D structure, even the movement that bus speed was
200Mbit/s, we could realize bus transmission ability of 102GByte/s.
- The transmission energy per bit demonstrated 3D structure superiority that transmission
was enabled by I/O of 0.56pJ while having ability for bus transmission of 102GByte/s.
- Evaluation of the real ability for I/O was enabled by monitoring an I/O signal, a power
supply connected in TSV, Bump and was able to show the guidance of the I/O design.
2. Research and development of the silica filler insulating layer formation technology- We formed Interposer which used silica filler as TSV insulation film and realized low
capacitance TSV which We could not form with the conventional insulation film.
- Furthermore, we made a simpler and easier process by introducing a paste metal
as TSV conductor.

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

39(3) Fundamental Technology Development and Design Definition of 3D Integration
Multifunctional High Density 3D Integration Technology(3)-D Mixed Signal 3D-Integraction Technology

Tadashi Kamada

Integration Basic Technology Research Lab.
3D-Integration Technology Research Development
Association of Super-Advanced Electronics Technologies ( ASET )March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

(3)-D Mixed Signal 3D-Integraction Technology R&D

40

BackgroundIn-vehicle electronic components still need low-pricing, low power, andhigh integration.
The trend of an in-vehicle electronic device
1. Low-pricing : Rise of Emerging Market
・Economy car ⇒Narrowing down of the function
・Simple vehicles structure ⇒Unstable power supply / EMC reduction at parts level
・Torrid zone / Rainy region ⇒ Environment resistance / Low power consumption

2. Diversification of Power : Rise of Electric Vehicle
Practical mileage ⇒ Weight saving / Low power
・Weight saving： Miniaturization / Reduction of heat and noise suppression parts
・Low power：Low-voltage-izing / Operating voltage control / Efficient-izing / Resume

3. Functional Safety : Driving Support System ～ Autonomous Car
・Evasion of fatal failure
High reliability and Low impedance of a power supply system
Improvement in connection reliability / Solid state integration
Reduction of a component countMultiplexing and diversification of processing
Combined use of different circuit form / parts / material(3)-D R&D for Mixed Signal 3D-Integraction Technology

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

41(3)-D Mixed Signal 3D-Integraction Technology R&D

Challenges

Heat / Restriction of integration / Stability of operation are subjects
The example of driving support system

Rear
CameraRear Side Radar

UltrasonicSensor

The system of which highreliability is required.

Short-distanceMilliwave Radar
Front surveillance
Imaging Sensor

The outstanding environment
resistance is necessity.
Front

Rear

The sensor which is not madeonly Si is used mostly.
Rear Radar

Front surveillance
Milliwave Radar

The throughput of about
1TOPS/W is required.

The subject of the present electronic components (semiconductor parts)
・ Generation of heat per processing is too large.
・ It does not become reasonable cost if it build not on one Si chip.
・ If independent, it does not operate stably. (ex. bypass capacitor / heat sink)⇒ In the present condition, a reliability demand is comparatively low and only thehigh product of added value is used.
(3)-D R&D for Mixed Signal 3D-Integraction Technology

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

42(3)-D Mixed Signal 3D-Integraction Technology R&D

R&D subject(3)-D/(1B1) Signal and Power Integrity Stabilization Technology
By this research, the interposer having the multi-electric supply capability, the narrow pitch and is the signal
connection of many pins, the small multi-bit signal throughput of a time skew, and the function of heat dissipation inorder to pull out enough the capability of the 3D LSI at the mixed signal 3D-integration technology of the stereo
imaging sensor module for the driving support image processing system for cars is developed.

(3)-D/(1B2) Evaluation and Inspection Technology of Interposer
By this research, from a low frequency wave to the high frequency domain of several gigahertz zone about themulti-power supply circuit source impedance for analog circuitry and digital circuits in the 3D-integrated system areevaluated.

(3D1) Fundamental Technology of 3D-Integraction
By this research, component development of the driving support image processing system for cars is performed. An
image processing system is made into stereo sensor module in which ranging is possible, and sets distance between
sensor modules to 20 mm which can be miniaturized. Si interposer which allotted the TSV type decoupling capacitor
is developed for the stability of operation in automobile environment. As distant ranging technology, the time
resolution of 10,000fps is utilized, time resolution is raised, and time-axis ranging technology is developed.

The image of a product＜ 3D imaging sensor module ＞＜ Evaluation board ＞＜ Assessment system＞

PCI-Express
CIS
CDS
ADC
IF

CIS
CDS
ADC
IF

Si-IP
DeCap
Organic board
AlN(3)-D R&D for Mixed Signal 3D-Integraction Technology

Various processing

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

(3)-D Mixed Signal 3D-Integraction Technology R&D

43

Goal

Target in 2012 Fiscal Year (Final Target) : Master Plan
Trial production evaluation of 3D-stacked-SiP of Mixed-Signal circuit required for image processing
systems (vision supporting system etc.) is performed, and then the fundamental technologies suchas electric supply technology and high-speed signal transmission technology are developed, andalso technical specifications is made.

Effect
The implementation guidelines of 3D-integration which can set an in-vehicle electronic device
become clear, and accelerate utilization.
①The structure, design manual, and effect of Si interposer which the environment resistance of LSI
raises become clear.
②The design flow in the case of developing SIP using the optimal semiconductor process forfunctional realization becomes clear.
③ The structure, design manuals (an organic g board, a lens, etc.), and effect of the secondary
packaging method of 3D LSI become clear.
④The prototype of the vision supporting system for the cars using hetero stacking is obtained. Of
course, these effects are not effects restricted to the in-vehicle electronic device, and it can apply
them widely.

(3)-D R&D for Mixed Signal 3D-Integraction Technology

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

（３D１） Mixed Signal 3D-Integraction Technology

44

Results■ Component Development of 3D imaging sensor module -1/2
Composition of the sensor module made as an experiment
The composition outline of a circuit block

Pixel

The pixel for infrared
rays is attached to theglass cap end of Ge
photo-diode.

Pixel

Pixel

Color Filter
Micro lensGlass CapGe Photo-diodeEvaluation Board

In order to utilize 3D structure and to take the circuit configuration of 480 parallel, the composition inwhich operation by 10,000fps is possible was developed.
（ Meisei Univ. ・Tohoku Univ.）(3)-D R&D for Mixed Signal 3D-Integraction Technology

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

45（３D１） Mixed Signal 3D-Integraction Technology

Results■ Component Development of 3D imaging sensor module -2/2
Electric power efficiency of ES2 has been improved 4 times to ES1
IF chip (ES2)

Principle of low-power-consumption(career reuse buffer)
Initial stateTransition state

After charge exchange

Compulsory winding up by thecapacitance decrease of acareer

A drift is carried out by theelectric field of a contiguity
transistor, and it settles in acontiguity transistor
Parasitism inductance which restricts drawing
out of an active career

Layout of actual buffer

pMOS area

Structure which
has differential
pMOS in the samen-WellEffect
ES1:450mW@200Mbps
ES2:225mW@400Mbps(3)-D R&D for Mixed Signal 3D-Integraction Technology

nMOS area

March 8, 2013

Structure which
has differential
nMOS in the samep-Well©2013 Association of Super-Advanced Electronics Technologies

（３D１） Mixed Signal 3D-Integraction Technology

46

Results■ Mixed Signal 3D-integrarion by TSV connection -1/3
C2C stacking process flow is completed
C2C Stacking Process Flow(a) Temporary adhesion(b) Chip thinning

Support wafer photograph(2-inch glass substrate)(c) VIA forming

Target Chip
Micro
Bump

Liner

Adhesives
Support wafer(d) TSV/Micro bumpforming(e) Thermo compression
bonding(f) Support wafer
exfoliation

Micro Bump

Si interposer
for assembly(g) Washing(h) Repeat (e)-(g)(i) Color Filter/
Micro lens forming
Glass→
Cap- It was stacked 4 chips at a time
this time.
- A numerical value is height(variation is about 5 micron).

（ Tohoku Univ.）(3)-D R&D for Mixed Signal 3D-Integraction Technology

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

（３D１） Mixed Signal 3D-Integraction Technology

47

Results■ Mixed Signal 3D-integrarion by TSV connection -2/3
Furthermore, the infrared photo-diode of Ｇｅ was stacked on a glass cap end
Device simulation result

Ge photo-diode production process(a) n+ forming(b) MESA forming(c) Wiring forming(d) Pasting ofglass and Ge(e) Ge tinningand M2 forming(f) Ge etching(h) Wiring forming(Cu Plating)(i) Insulating layer
and bump forming

Adhesives(g) Insulating layer
forming

Photograph after Ge etching(j) Pasting

Imaging sensor chip

The structure which forms aphoto-diode in a glass cap end
is devised.

(3)-D R&D for Mixed Signal 3D-Integraction Technology

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

48（３D１） Mixed Signal 3D-Integraction Technology

Results■ Mixed Signal 3D-integrarion by TSV connection -3/3
CIS / CDS / ADC / IF and Color Filter / Micro Lens / Glass Cap were stacked
Chip seen from the support board side

Completed stacking chip

Micro Bump

Surface

Si
Interposer

Back(a) After IF chip stacking (b) After ADC/IF chip stacking

40umt CIS

SectionCDS(c) After CDS/ADC/IF
chip stacking(c) After CIS/CDS/ADC/IF
chip stacking

Color Filter / Micro Lens forming

ADC

Note)
Before IF chip
stacking

Interposer
Cu/Sn Bump

M1

Metal
Cu TSV(3)-D R&D for Mixed Signal 3D-Integraction Technology

March 8, 2013

Si Sub.5μm
Cu TSV

Dielectric Layer©2013 Association of Super-Advanced Electronics Technologies

(3)-D/(1B1) Signal and Power Integrity Stabilization Technology

49

Results

Si-IP and DeCAP chip were unified

CIS
CDS
ADC
IF

CIS
CDS
ADC
IF

Si-IP
DeCap
Organic board
AlN

Si-IP with built-in DeCap

The layout result of Si-IP
with built-in DeCAP(3)-D R&D for Mixed Signal 3D-Integraction Technology

Trial production chip

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

50（３D１） Fundamental Technology of 3D-Integraction

Results■ Si interposer with TSV type decoupling capacitor -1/2
Property evaluation result
Voltage characteristic

Structure of
TSV capacitor

SiO2
High-k film

Design value
Capacity[pF]

Inner Cu
electrode25-piece parallel

Capacity[pF]

Sectional view

Plan view

Capacity characteristic

Flat9-piece parallel
4-piece parallel

Measured value

Half of design value

Ground Cu
electrode

Connectivity number of array [pcs]80V

Frequency characteristic

Capacity[F]Breakdown characteristic

Influence ofoutgoing lines

pcs
pcs
pcs
pcs
pcs

Frequency[Hz](3)-D R&D for Mixed Signal 3D-Integraction Technology

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

（３D１） Fundamental Technology of 3D-Integraction

51

Results■ Si interposer with TSV type decoupling capacitor -2/2
Source impedance was reduced in the large frequency domain
Trial Production Wafer

Impedance Measurement Result

No decoupling
capacitor

10 decoupling
capacitors(design :300pF)

Completed DeCAP Chip

By introducing a decoupling capacitor,
it checked that power supply impedance
decreased in a large frequency domain.
(3)-D R&D for Mixed Signal 3D-Integraction Technology

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

(3)-D/(1B2) Evaluation and Inspection Technology of Interposer

52

Results

High resistance Si is the interposer material which was not mostly subject to the
influence of the career, and was suitable for the high-speed signal.
It was evaluated whether the TSV in a high resistance Si (1000 or more ohm・cm)
interposer would operate as MOS capacitor by inputting the pulse signal of various
voltage and frequency into TSV.

In 1us or less (more than frequency 1 MHz) of pulse width,
it did not operate as a MOS capacitor.
（ Meisei Univ ・AIST）(3)-D R&D for Mixed Signal 3D-Integraction Technology

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

(3)-D/(1B2) Evaluation and Inspection Technology of Interposer

53

Results

Wiring of the De-CAP chip became 5 ohms of ADC1.0V power supply / 7.5 ohm-IF
1.2V power supplies which are intention of the original design
Impedance measurement result of the power supply wiring in De-CAP chip
Measuring Method

Measurement Result (DVD/S 10 No. 4)

ProbeTermination release

50 Ω
Zo=5.8 Ω (it is not0Ω)S

Short-circuit has notoccurred.

Probe

G

100 μm

100 mV/div., 5 ns/div.
（Meisei Univ.・AIST）(3)-D R&D for Mixed Signal 3D-Integraction Technology

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

54(3)-D/(1B1) Signal and Power Integrity Stabilization Technology

Results

Curvature simulation determined the layer structure of the evaluation board
Layer structureof evaluation board

Curvature simulation
After Press

At Reflow

Structure 14 layer with AlN heat spreader
Surface :PI-0.025+PEEK/PEI=0.03mm
Sheet
Inner layer :Cu/LCP=0..12/0.05mm

AlN spec.
Internals
Cu coinCu plate
300umΦ,Pitch 400um
Land
Thickness

Displacement (um)Co-planarity of pad center

After Reflow

50PadsAt Reflow:200℃
After Reflow:25℃
Maximum
Point

200℃：5.7um
25℃：16.2um
Maximum:4.5um

Structure of putting Cu under exothermic chip with 14layer +AlN
Cu is thinner is good for curvature (Convex of 600um at Cu=0.2t)
Co-planarity of the Si-IP mounting portion determined layer structure as target 50um
(3)-D R&D for Mixed Signal 3D-Integraction Technology

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

(3)-D/(1B1) Signal and Power Integrity Stabilization Technology
Evaluation board was completed based on the design
Curvature investigation
Imaging Sensor
by the reflow of sensor mounting area
（Si-IP/DeCap）
After heating
Before heating

A-A’

Between DeCap and
Evaluation board

55

Results

FPGA（23x23mm）

B-B’

Between FPGA and
Evaluation board

Cautions are required for the curvature of the fine pitch portion of Si-IP, and coexistenceof large-sized Si-IP and a large usual package.
(3)-D R&D for Mixed Signal 3D-Integraction Technology

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

(3)-D/(1B1) Signal and Power Integrity Stabilization Technology

56

Results

Design and trial production of the object lens and the heat pipe which considered
the heat dissipation from the surface
Driving support image processing system outline
Structure of a heat pipe

Structure of an object lens portion
Lens screwing
Skirt for straylight interception

15mm
25mm

Fixed screw
hole

Skirt for stray Lens mount Lens Fixed screw hole
light interception
Cu heat sink
Control signal
connecterCu coin

AlN heat sink

PCI-e connecter

Cu sheet

Cu coin was built in the evaluation board to miss theheat from the back, and also in order to correspond tohigh temperature, the mechanism in which heat was
directly diffused from Si-IP was examined.
(3)-D R&D for Mixed Signal 3D-Integraction Technology

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

（３D１） Fundamental Technology of 3D-Integraction

57

Results■Trial production and evaluation of the driving support image processing system for cars
Application software for evaluation using the feature of 3D stacking was created
InfraredSensitivity

3D sensor module

Skin
Recognition

HDR

High SpeedHigh
Sensitivity

Pedestrian
Recognition
Phase Only
Correlation
MethodNeighborhood Ranging

Small Size
StereoHigh Speed
Visible light
Communication(3)-D R&D for Mixed Signal 3D-Integraction Technology

March 8, 2013

Long distanceRanging,
Vehicle-to-vehicle
Communications©2013 Association of Super-Advanced Electronics Technologies

58（３D１） Fundamental Technology of 3D-Integraction

Results■Trial production and evaluation of the driving support image processing system for cars
Conclusion: Each developed fundamental technology was evaluated and the technicalspecification was drawn up.
Classification

Theme
CIS Chip
CDS ChipSensorModule
ADC Chip
IF Chip
3D1
Fundamental
C2C Stacking
Technology
Color Filter
Stacking
technology
Micro Lens
Hetero Stacking
TSV Decupling Capacitor
Specification
3B2
Evaluation
Impedance
Si
Interposer
DesignDeCap integrate
Transmission-Line
3B1
SI・PI
Broad
Evaluation
Board
Heat Dissipation
Secondary Mount
HDR
3D1
Skin Detection
Evaluation
Fundamental
Application Stereo Ranging
Technology
Visible Light comm.

(3)-D R&D for Mixed Signal 3D-Integraction Technology

･
･
･
･
･
･
･
･
･
･
･
･
･
･
･
･
･
･
･
･

Outline / Subject
480 parallel systems by TSV
Under ±1% error, 4step PGA
ENOB7.28b・With digital filter
225mW@400Mbps
Low yield , No working sample
RGB+IR structure
About 3um in height (10um□)
Ge photo-diode was stacked
Total 40nF・80V breakdown
High resistance Si can be used
Evaluation characteristic ~40GHz
1.2Ω at 5GHz with no resonance
Built with the Si-IP process
Simulations including Si-IP
Curvature was controlled to 70um
Unified AlN heat sink
20mm Si-IP and 27mm BGA
Block composition by 5pictures
1100nm and1400nm was used
Phase only correlation method
Ranging by visible light comm.

March 8, 2013

CIS operation waveform

3C1
Specification
IF Spec.
Circuit Diagram
Construction
Technical Spec.

･
･
･
･

Visible-light-comm.
experiment
L1

L2©2013 Association of Super-Advanced Electronics Technologies

59(3)-D Mixed Signal 3D-Integraction Technology R&D

Results

Application to the vision support system of a car
Application for small stereo and infrared detection and high frame rate
・QVGA, Small Size, Stereo
・High sensitivity (10μ■pixel)+IR(Ge Stacking)・1200fps high frame rate

Build in the room mirror

Sensor LCR(13×21mm)

CIS
CDS
ADC
IF

CIS
CDS
ADC
IF

Si-IP
DeCap
有機基板
AlN

Cu
CPU

SectionPower
Supply IC Miniaturization of sensor+CPU
2. Infrared Sensitivity Application- Improvement in sensitivity in the nightby IR detection.
- Pedestrian detection by skin detection

1. Small Stereo Application- Ranging (short distance)- Fail-safe- Obstacle Recognition

3. High Frame Rate Application
・ Transfer of the vehicles information by visible light and ranging
・Dynamic range expansion by multi-gain composition(3)-D R&D for Mixed Signal 3D-Integraction Technology

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

(3)-D Mixed Signal 3D-Integraction Technology R&D

60

Summary

1.The hetero stacking C2C process was developed, and 3D stacking of 4 chips was
carried out by TSV connection, and also the sensor module which stacked thecover glass which allotted the color filter ,micro lens and Ge photo-diode wascompleted.
2. For the stability of operation in automobile environment, Si interposer which allotted
the TSV type decoupling capacitor of total 70nF was developed, and theeffectiveness to a GHz band was confirmed.
3. According to the TSV connection stacking SiP structure which stacked six sorts of
10 chips as CIS/CDS/ADC/IF chip, and Si interposer / DeCAP chip, the stereo
imaging sensor module (10 mm of base length and a volume of about 350 mm2) inwhich ranging is possible was completed.
4. As a driving support image processing system for cars, the sensor module wassecondary mounted, and also the evaluation board equipped with a power supply,a high-speed interface, and heat dissipation was created and evaluated.
5. The application software for evaluation supposing practical use (distant place
ranging adapting the vehicle-to-vehicle communications of the visible light using
the rapidity of the sensor, etc.) was created and evaluated.
6. The specifications of the trial production sensor module were summarized to thetechnical specification.

(3)-D R&D for Mixed Signal 3D-Integraction Technology

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

61(3) Fundamental Technology Development and Design Definition of 3D Integration
Multifunctional High Density 3D Integration Technology(3)-E Heterogeneous 3D integration technology
Fumihiko Nakazawa

Integration Basic Technology Research Lab.
3D-Integration Technology Research Development
Association of Super-Advanced Electronics Technologies ( ASET )March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

62(3)-E Heterogeneous 3D integration technology

Background

Mobile communication of near future
Number of data will increase to 100-1000 times in 10 years.
800MHz

1. LTE⇒×5 High speed
2. Cognitive radio, software radio
System changes autonomously on
radio condition.
700MHz
4.9GHz

4.9GHzOnly 800MHz is available, mobile
phone uses 800MHz.

1.5GHz
2.4GHz800MHz
2.4GHzRapid Large size data transfer ofhigh resolution vide, result in useof both 800MHz and 2.4GHz

Wide availabilityof 2.4GHz, mobile
phone uses 2.4GHz.

Tunable radio is key technology
3. 4G technology⇒Wide band
62

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

(3)-E Heterogeneous 3D integration technology

March 8, 2013

63

Background©2013 Association of Super-Advanced Electronics Technologies

64(3)-E Heterogeneous 3D integration technology

Future：3D heterogeneous integration oftunable frequency device

Conventional: 2D integration of fixed
frequency devices
FilterFilterFilterSW
SW

SW

FilterSW
FilterFilterSWSW
FilterSW
Filter
LNA
PA
FilterFilterFilterInterposer
Interposer

Filter1) Tunable Filter
2) WLP MEMS switch (Tunableantenna）
3) Hetero 3D integration

FilterFilterSW

Challenges / Goal

SW

SW

miniaturize

SW
SW

Antenna
Filter
LNA
IPD
PA
DriverTunable filter(LTCC)March 8, 2013

WLP MEMS switch(Si)

Tunable antenna(Evaluation of MEMS switch)©2013 Association of Super-Advanced Electronics Technologies

(3)-E Heterogeneous 3D integration technology

65

R&D subject(3E1) R&D of Heterogeneous 3D integration technology(a) 3D integration RF module
Aiming for next generation RF module for mobile terminal, our goal is 3D
integrated RF module consisted of tunable filer formed directly on LTCC
wafer, low voltage and highly reliable operation WLP MEMS switch, anddriver IC for control these devices.
(b)ＭＥＭＳ tunable filter
To develop low insertion loss and excellent frequency performance chip
directly formed on LTCC wafer.
(c)WLP ＭＥＭＳ switch
To develop low voltage operation and highly reliable WLP MEMS switch,
along with WLP technology for miniaturization and low profile. To evaluate
WLP MEMS switch with promising application of tunable filter.
(d) Driver IC（Joint enforcement of Tokyo Institute of Technology）
To develop CMOS driver IC which operates 3.3V and control MEMS devices
with 15V, low power consumption, suitable physics for 3D integration.

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

(3E1) Heterogeneous 3D integration technology

66

Results(a)Structure of 3D integration ＲＦ module■Sectional view of structure

MEMS-SW

ＭＥＭＳ filter structure

Resistive VIA

Tunable filter ceramic
substrate

Integrated wiring

Raising ring
CMOS driver ＩＣ
Connecting pad■Up view

MEMS-SW
×6■Bottom view

n
e
e

n
O

r
c
S

March 8, 2013

CMOS driverＩＣ

Raising ring

Connecting pad©2013 Association of Super-Advanced Electronics Technologies

(3E1)Heterogeneous
Heterogeneous 3D
technology(3E1)
3Dintegration
integration
technology

67

Results

Demonstration of how to work

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

(3E1)
Heterogeneous 3D
technology(3E1)
Heterogeneous
3Dintegration
integration
technology

68

Results(a)Fabricated heterogeneous 3D integrated RF module

n
e
e

n
O

r
c
S

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

69

(3E1)
Heterogeneous 3D
technology(3E1)
Heterogeneous
3Dintegration
integration
technology

Results(b) MEMS tunable filter ：enables both center frequency and band width
Equivalent circuit of new filter
RF in

Cm

Equivalent circuit for f1 and f2
Cm

RF outf2
C1

C2

λ/4 - X

L1

L2

X
λ/4 + X

Attenuation

f1

LC1
Cc

Cc

f1

f2

Frequency

A steep frequency response can be obtained using two resonators
March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

(3E1)Heterogeneous
Heterogeneous 3D
technology(3E1)
3Dintegration
integration
technology

70

Results（ｂ）EM simulation and circuit design of MEMS tunable filter

n
e
e

n
O

r
c
S

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

71(3E1) Heterogeneous 3D integration technology

Results(b)MEMS tunable filter process
Form LTCC wiring wafer
1. LTCC配線ウエハの形成

Form pad
4. パッド形成

Form capacitor electrode, dielectric layer, 1st
2. キャパシタ下電極形成、誘電体膜形成、
layer coil
キャパシタ上部電極/一層目コイルの形成

Remove sacrifice layer and seed layer
5. 犠牲層除去、シード層除去
Form pole, sacrifice layer, 2nd layer coil
3. ポール形成、犠牲層形成、二層目コイル形成

71 / 6
March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

(3E1) Heterogeneous 3D integration technology

72

Results（ｂ）Fabricated MEMS tunable filter

n
e
e

n
O

r
c
S

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

(3E1) Heterogeneous 3D integration technology

73

Results(c)Structure of WLP MEMS switch
LTCC Cap wafer
Through hole via (THV)
Bonding material
MEMS switch SOI
wafer

Without backside hall

LTCC Cap
wafer

MEMS switch
SOI wafer

Hermetic via
Electrical contacts on multi-height

Hermetic and organic-contaminant-free

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

(3E1) Heterogeneous 3D integration technology

74

Results(c)Fabricated WLP MEMS switch（ before LTCC cap wafer bonding）
WLP sealing frame

RF input port
Bottomdriving
electrode

GND
Separate slit

PZT
actuatorTop
driving
electrode

WLP electricalcontacts

Bottom RF signal-line
Contact

MEMS switch
SOI wafer

RF output port

March 8, 201374

©2013 Association of Super-Advanced Electronics Technologies

(3E1) Heterogeneous 3D integration technology

75

Results（ｃ）WLP process
1. Filling and drying of Au
submicron particle slurry

4. Bonding LTCC and device SOI

Blade
Transferwafer
2. Photoresist removal

3. Transfer of Au submicronparticles onto LTCC

Bonded wafers
March 8, 201375

©2013 Association of Super-Advanced Electronics Technologies

76(3E1) Heterogeneous 3D integration technology

Results(c)Performance of fabricated WLP MEMS switch
Ceramic package
2.5×2.0×1.1 mm
ON state
OFF state
Ceramic package
WLP MEMS switch

Diced WLP chip
1.4×0.9×0.8 mm►►

1/5 in volume

Improved from 0.75 to 0.5 dB at
4 GHz

Electrical contact on multi-level height is achieved with low-resistivity.

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

(3E1) Heterogeneous 3D integration technology

77

Results(c) Evaluation of fabricated WLP MEMS switch
DC cold switching at 1 mW

Time of flight vapor analysis
Prebaked at 100 ℃ for 16-24 h
Limit of detection: 10 ppm

Short life time

Various gaseous species aredetected.
March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

(3E1) Heterogeneous 3D integration technology

78

Results(c）Bonding with Ar and additive gas environment
DC cold switching at 1 mW

Gas concentration (ppm)Time of flight vapor analysis
Prebaked at 100 ℃ for 16-24 h
Limit of detection: 10 ppm

Organic gases less than limit
of detection< 1 Ω up to 100
million cycles

Hermetic and organic-contaminant-free packaging is achieved.

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

79(3E1) Heterogeneous 3D integration technology

Results(c)Tunable antenna for evaluation of MEMS switch
Tunable antenna with switch structure ofelectrical length with MEMS switch.
Small size of 50×10×2 mm antenna isconstructed, and demonstrated under -6dB
performance.

50
10

0.8G

~

GND
1.7～2G

1.5G~

switchスイッチ
OFFmechanism
動作原理~

switch
スイッチ
ON

Ｔ：2mm

S11[dB]

SwitchAntenna
アンテナ性能performance（リターンロス）March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

(3E1) Heterogeneous 3D integration technology

80

Results(c)Prototype tunable antenna is constructed and evaluated.
Small sized prototype antenna to be installed in smart phone is constructed.
Prototype antenna demonstrated high efficiency of more than -5 dB withswitching of MEMS switch.

Up
conv
erter

昇圧回路

Signalsupply給電
Button
Cell
ボタン電池

MEMS
switchMEMSスイッチ
Charging
充電端子 padスピーカ
speaker

Antennaelement
アンテナ素子(止水外)充電端子、スピーカは1000nHを介してGNDに接続。
MEMSスイッチをOn/Offすることで1.5GHzを切り替える構造。

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

(3E1) Heterogeneous 3D integration technology

81

Results(d)Joint enforcement of Tokyo Institute of Technology
Voltage up converter from 3.3 to 20 V with 8 channel output port on low voltage
0.18μm CMOS.
昇圧回路
Up convertor

Vdd

S2

S1

S3

S4

S5

down
降圧回路
convertor

S11

Vout

Vdd

CLKCLK+

G

Ring
差動リング
発振回路
oscillatorS

D

PW DNW
Vdd

Vcont

Fabricated chip（3.5mm x 2.4 mm）

High voltage circuit with low voltage transistor
125kHz switching

Switching wave form (zl =1.3nF)

March 8, 2013

item
targetHigh voltage output
20V
Low voltage output<2V
Number of output 8chload impeadance
3MΩ, 1.3nF

measured result
19.6V
1.2V
8ch confirmed
3MΩ、1.3nF

rise / fall time

Tr/Tf < 100 μs

Tr:74.8us(15V)
Tf:97.4us(3.3V)

Power supply
chip size
CMOS process

3.3V
3.3V
< 3.5 × 2.4 mm 3.4 × 2.3 mm
0.18 μm
0.18 μm©2013 Association of Super-Advanced Electronics Technologies

(3)-E R&D of Heterogeneous 3D integration technology

82

Summary(3E1) R&D of Heterogeneous 3D integration technology

The MEMS tunable filter demonstrated both center
frequency and bandwidth tunability.
The WLP RF-MEMS switch had a small chip size andexhibited good RF performance.
The frequency reconfigurable antenna showed highradiation efficiency.
Driver IC of DC/DC converter from 3.3 to 20 V with 8
output on low voltage 0.18μm CMOS.

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

83(3) Fundamental Technology Development and Design Definition of 3D Integration
Multifunctional High Density 3D Integration Technology(3)-B 3D integration technology
Kenichi Takeda

Integration Basic Technology Research Lab.
3D-Integration Technology Research Development
Association of Super-Advanced Electronics Technologies ( ASET )March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

84

3D Integration Technology
Background:
Improved QoL by cyberphysical system↓
Bigdata analysis requires system-level
performance improvement→High bandwidth, low latency, small F/F

Mobile terminal
Low power
Wireless comm.

Massive data processing
Low power
High bandwidth

Background

Goal:
Next-generation 3D SiP system using
high-performance TSV
Si

TSV

Si
Si

Advantages

Lower power
Higher density
Lower latency

Challenges

Higher cost
Lack of standard

Sensing
Hybrid architecture
Low power

March 8, 2013

Micro bump

©2013 Association of Super-Advanced Electronics Technologies

85

3D Integration Technology

Challenges

Challenges: Establishment of TSV model and design guidelines
Approaches: Co-development of circuit and process technology
Development of standard library relating TSVProcess technology (wafer bonding, TSV fabrication)
Circuit technology (communication, power, test, redundancy)
Spec.

Si
Co-develop
Circuit design
Signaling
Power deliver
Clock deliver

Lack of design

Process design
ASET

Layout rule
Structure design
Process condition

Library

Lack of standard
processSi
TSV model•Electrical behavior•Keep-out zone
•Mechanical and thermal
characteristics

実装基板

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

3D Integration Technology

86

R&D subject(3B1) 3D integration circuit technology
1.Development of TSV model
1. TSV electrical model
2. TSV-related layout design (KOZ)
2.Development of 3D-related circuit
1. 3D Transmission circuit and clock distribution
2. 3D power supply(3B2) 3D integration process technology
1.Development of wafer-level 3D integration process
1. Hybrid wafer stacking
2. Via-last TSV formation after wafer thinning
2.Development of wafer stacking technology
1. Layout rule and process rule for wafer-level 3D integration

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

3D Integration Technology

87

Goal

Project goal
Establishing project standard library for 3D integration processrules, layout design rules, and electrical design rules.

Expected influences
Accelerating 3D system design and its related prototyping of nextgeneration 3D SiP system.

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

3D Integration Technology

88

Results■Two platform development
Two platforms for 3D integration were developed. C2C for rapid prototyping and W2W
for achieving superior electrical performance.

C2C

W2W

Advantages•Short TAT period•Well-developed process•Superior electricalperformance

TSV spec.

20μm diam., 50μm
length, 50.4μm pitch

8μm diam., 25μm
length, 25.2μm pitch

Purpose•Early-stage evaluation(prototyping)•Performance evaluation

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

89

Process Technology

Results■4 stacked device chip using C2C platform•One silicon interposer and four device chips.
•Successful MOSFET operation was confirmed.

4th
3rd
2nd
1st
Si interposer

200μm(b) cross‐sectional SEM

表Bump

4th chip
←Bump
←TSV

3rd chip
2nd chip
4 stacked chip
1st chipSi interposer

100μm

50mm

Si interposer

50μm(a) Bird’s‐eye view(c) High‐mag SEM crosssection

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

90

Process Technology

Results■Process flow and key technologies for W2W platform

1. co-planarization ofcopper and polymer

2. Simultaneously –formed ventilation
channel

3. Pre-cleaning forhybrid copper bonding

4. Precise wafer
thinning with NCG

5. Via-last TSV
formation for Cu
interconnect

#01

#01

Si25

(2) F2F bonding(3) Si thinning(4) TSV formation
6. B2F wafer bonding
#02

Si25
#01

#02

Si25

(5) Metal filling(6) Back-bump(7) B2F bonding(1) Bump formation’10 FY#02#01

7. Lithography-less
TSV reveal’11 FY
Si25(8) Si thinning
March 8, 2013(9) Backside ILD(10) Bonding pad’12 FY©2013 Association of Super-Advanced Electronics Technologies

91

Process Technology

Results■Pre-cleaning for hybrid wafer bonding
Hydrogen radical treatment provides both good copper-copper contact and sufficient
polymer adhesion.
Cu(a) Without pre-cleaning

polymer
Reduction by
H radical

sulfur(S)Cu

Cu bumppolymer

Bonding face→

SCu intensity(counts/sec)

800

Interface layer

Without treatment

Cu bump600300nm(b) With pre-cleaning

400
Ar plasmaCu bumpH radical

200

Bonding face→Cu bump

0
0

1

2
3
4
5
6
Depth from surface (nm)7

Sulfur SIMS profile on copper bump surface
March 8, 2013

300nm

SEM photos of bonded area
©2013 Association of Super-Advanced Electronics Technologies

92

Process Technology

Results■Via-last TSV formation to bonded wafer•Via-last TSV formation compatible with Cu/Low-k interconnect structure.
•Good electrical contact was obtained.

25mm

8mm
Si

TSV(Cu)
M1
M2

Cu/Low-k

M3polymer Cu
BondedinterfacepolymerCu

Si

SEM photo after TSV formation
March 8, 2013

High-mag view of contact area between
TSV-Cu and LSI-Cu interconnect.

©2013 Association of Super-Advanced Electronics Technologies

93

Process Technology

Results■three-wafer stacking•Three wafer stacking using 300 mm wafer confirms validity of the proposed process.

wafer3wafer2F2F:Face-to-face
B2F:Back-to-facewafer1Si-sub（>600μm）

wafer3wafer1（Si-IP）

22μm

wafer2

21μm

Cu
Cu

March 8, 2013

8μm

PBO

Thinned Si

Cu

PBO

8μm

Thinned Si©2013 Association of Super-Advanced Electronics Technologies

94

Process Technology

Results■Three-wafer stacking
3D LSI (two device chips and one Si-interposer chip) was successfully obtained andcircuit operations were confirmed.

3D LSI

Organic IP

Photograph of stacked wafer andits cross-sectional view.

3DLSI on an organic interposer
March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

95(3B1) Circuit Technology

Results■TSV layout design
・ Definition of TSV layout designs for C2C and W2W stackings’ and registration to library. Releasing metal layers
numbers 3-6 for routings of standard cells and matching TSV pad length and pitch to multiples of those of standard
cells enable to embedded TSV layout into core circuit area.
TSV pad length

Passivation

TSV pitch for W2W stacking（10 library pitch＝25.2 um）

TSVΦ

For connection withmump (7-8 layers)

P&R(3-6 layers)
For connection with
TSV(1-2 layers)

Alignment margin

Circuit area

TSV

P-wellP-sub

Well tap

Cross-sectional view of TSV design

Embedded TSV design into core circuit area.

TSV design rule (mm)Alignment margin Upper window

MethodTSVΦTSV lower
pad

W2W

10

20

5

C2C

20

30

5

March 8, 2013

Upper pad

TSV pitch

10

20

25.2

20

30

50.4

©2013 Association of Super-Advanced Electronics Technologies

96(3B1) Circuit Technology

Results■Data transmission between chips and modeling TSV characteristics
・Using optimized transmission circuit for 3D integration and low capacitance TSV shape, highest
transmission performance (power efficiency) in W2W stacking was obtained. Electrical model of
TSV was defined by measuring stacked TEG chips.
10

Cu-TSVCu-pillar

Data-rate density（Tbps/mm2）

1st layer

25 mm

25 mm

2nd layer

This work（W2W,via last）
ISSCC12（via mid.）

1

C2C stacking
3DIC2011

0.1

Micro bump
ISSCC04

0.01

Conventional 2D
ISSCC05

Si-interposer

0.001
0.01
Cross-sectional photo of 2 layers W2W stacking
Total cap. : Cv = 84fF

Cfr = 41fF

0.1

1

10

100

Power efficiency（Tbps/W）
Cv

Cox Cdep

Low freq.

Ch = 84fF

High freq.
(>10kHz)Rv =80mΩ

Cl = 70fF
Vch = 0V

Electrical model of TSV.

Vcl = 2V

Vcc

Capacitance model of TSVMarch 8, 2013©2013 Association of Super-Advanced Electronics Technologies

97(3B1) Circuit Technology

Results■3D clock synchronization technique（Collaboration with Tohoku Univ.）
・3D integration system faces clock skews resulting from process variations at wafer-to-wafer leveland power supply variations between chips. To decrease this clock skew, a 3D clock
synchronization circuit was developed and reduction by 60% was experimentally confirmed.

・Using 3D clock synchronization circuit clock skew
between stacked chips reduced by 60%.
・Phase detector also integrated for evaluation of
skew at resolution of 20 ps.

TSV pitch: 25 mm

FPGA
16 X 16
tile array

Embedded TSV into
core circuit area.

FPGA Block
16x16 tile array
Terminatory

root

Chip photo

Out

PLL
In

Phase comp.

Variable delay rol
nt
Co

root

Simulation (FF-SS)
Terminatryclock

Conventional

Out

PLL
In

Main clock

Variable delay lontCoPhase comp.

Measurement(TT)
従来

60%

r

This work

本技術

Reference clock via TSV interconnect
0

3D clock synchronization scheme

200

400

600

800

1000

Clock skew (ps)March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

98(3B1) Circuit Technology

Results■Reliability

102

102

101.5

101.5

101

Oscillation cycle variation （%）（100% at no TSV ）Oscillation cycle variation （%）（100% at no TSV ）・Evaluation of KOZ (Keep Out Zone) around TSV by measuring oscillation cycles of ring-OSCs.
Cycle variation less than 1% at distance of 2 um in C2C stacking.
Negligible cycle variation in W2W stacking.
・Current design rule defines 5um margin due to alignment margin, which is larger than the KOZ of
C2C stacking. Thu, FET characteristics variations need not be considered.

Design rule

100.5
100
99.5
99
98.5
98
0

2

4

6

8

10

101

Design rule

100.5
100
99.5
99
98.5
98
0

2

4

6

8

10

Distance between TSV and FET (mm)Distance between TSV and FET (mm)（a）50um pitch C2C stacking（b）25um pitch W2W stacking

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

99(3B1) Circuit Technology

Results■Stabilization of power supply for 3D integration（Collaboration with the Univ. of Tokyo）

Die photo

電源
回路

3.0mm

DC/DC
converter・Mounting DC/DC converter on the top of stacked dies enable to supply power at high voltage andlow current. Reduction of IR drop on TSV resistance to 1/4
In conventional approach was confirmed experimentally.

5mm

2.1mm

Proposed technique (BCT; Buck Converter on Top die)
5mm

Two half size of DC/DC
converters located on top andbottom dies.
L C
DCDC

C

キャパシタ
Capacitor

Twostacked dies
積層チップ
(90 nmCMOS
CMOS)
(90nm
)

インダクタ
Inductor

1.2V
L

Measurement result

Implementation

キャパシタ
Capacitor
DCDC

5mm

シリコン・インターポーザ
Silicon interposer

PCB

IR drop from Vdd on bottom
layer (mV)

Schematic

-10
-20

-78%
-30

Conventional-40

Measured
Simulated

-50
-60

3.3V

Distribution of 3.3V
→Current ：1.2/3.3

Proposed (BCT)0(Direct mounting of capacitors &inductors on top of stacked dies)

1

2

3

4

5

6

7

Position of chip layer
L C
Buck

Die 2
Die 1

Silicon interposer

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

8(3)-B R&D of 3D Integration Technology

100(3B1) Summary■ Definition of TSV layout designs for C2C and W2W stackings and registration to library.
■ Using optimized transmission circuit for 3D integration and low capacitance TSV shape, highest
transmission performance (power efficiency) in W2W stacking was obtained. Electrical model of
TSV was defined by measuring stacked TEG chips.
■ To decrease clock skew in 3D integration system, a 3D clock synchronization circuit was developed.
Reduction by 60% was experimentally confirmed.
■ KOZ (Keep Out Zone) around TSV was evaluated by measuring oscillation cycles of ring-OSCs.
Current design rule defines 5um margin due to alignment margin, which is larger than the KOZ of
C2C stacking. Thus, FET characteristics variations need not be considered.
■ Mounting DC/DC converter on the top of stacked dies enables to supply power at high voltage andlow current. Reduction of IR drop on TSV resistance to 1/4 in conventional approach was
confirmed experimentally.

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

(3)-B R&D of 3D Integration Technology

101

Summary(3B1) Summary■ Two types of 3D integration schemes (C2C and W2W) were developed. The usefulnessof these schemes was confirmed by their electrical characteristics.
■Sulfur-contained impurity degrades bondability between Cu bumps during Cu hybrid
bonding and hydrogen radical treatment effectively eliminates Cu sulfide from Cu bumpsurface.
■Via-last TSV process was developed and 3D LSI (two device chips and one Siinterposer chip) was successfully obtained and circuit operations were confirmed.

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

102(2) Evaluation and Analysis Technology Development for 3D Integration
Multifunctional High Density 3D Integration Technology(2)-B Thermal / Chip Stacking Technology

Fumiaki Yamada

Integration Basic Technology Research Lab.
3D-Integration Technology Research Development
Association of Super-Advanced Electronics Technologies ( ASET )March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

103(2)-B R&D for Thermal / Chip Stacking Technology

Background

Increasing power consumption and data rate on electronic devices in the future“2005,NEDO：「電子・情報技術ロードマップ」の狙いと半導体技術開発のあり方」より”■Increasing allowable power dissipation without
system mass enlargement:5W → 20W■High band width in 3D die stacking：Low power consumption with multi bits parallel connection（Ref. : T.Sakurai,ISSCC Workshop 2004）

Powerﾁｯﾌﾟあたりの消費電力（Ｗ）
consumption per chip (W)

1000

：MPU
：DSP

100

1. Development for 3D SiP chip stacking structure, material andcooling method allowing small-thin form factor and calmness under
20W/1cm2x1.4 /s
3year

高速化・高集積化により、更なる電力増加の傾向に！

4倍/3年

10
x4

s
ar
ye
/3

1

集積化の度合いにより、
分かれる

0.1

0.01
1980

Following development is required as next generation 3D
die stacking base technology

1.4倍/3年

1985

1990

1995
2000
時期（年）
Time (Year)

2005

2010

2015

3D Silicon Integration

1000002. >10mm pitch interconnection assuming micro level accuracy⇒ Project objectives are defined as following
Less than 5mm of diameter of bump connection(10mm pitch)
If assuming 1% of area penalty...
More than 10K/1cm2 of interconnections
Technology development for above chip interconnection and thereliability evaluation

Via density (via/mm2)

5 µm via pitch
10000
20 µm via pitch
1000
100

Transistor

Micro

Unit

Core

3D design level** IBM J R&D -2006, A. W. Topol et al.,(2)-B R&D for Thermal / Chip Stacking Technology

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

(2)-B R&D for Thermal / Chip Stacking Technology

104

Challenges[ Thermal ]• Necessity of thermal conductivity parameters and the design guideline for 3D chip stacking
structure• Application challenge for in-vehicle device of 3D stacking image sensor– Necessity of design directions for chip-chip high thermal conductive underfill andthermal bump placement– Necessity of cooling structure design with low temperature gradient for hightemperature in-car environment and allowable low Tj of image sensor[ Die stacking technology ]• Challenges for micro bump interconnection– Need more accuracy at micro bump joining– Countermeasure against solder bridge for narrow pitch• Low temperature soldering technology for low thermal resistance device for in-vehicle
application• Challenges for low stress and high reliable interconnection structure– Optimization of joint structure and material composition– Simulation and evaluation technology for mechanical stress and deformation• Non-destructive inspection and evaluation technology for internal micro-defect(2)-B R&D for Thermal / Chip Stacking Technology

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

105(2)-B R&D for Thermal / Chip Stacking Technology

R&D subject（2B1）-1 R&D of thermal performance and cooling solutions• Development of accurate thermal characteristic evaluation

HeaterAveraged thermal conductivity ofinterconnection and air

Air

Interconnection

Air

technology
Thermocouple• Development of small and more effective cooling system• Evaluation of high thermal conductive material

SampleThermocouple• R&D of cooling structure under high temperature

Si (50mm thick)Si (50mm thick)
100mm

200mm

200mm

Modeled temp. distribution

Interconnection and air

Interconnection

Heatsink

environment

The thermal resistance is derived by
the temp difference between above andbelow sample.

Air
Horizontally continuum modelAir

mm-scale model

Significant difference on temperature distribution (thermal resistance)（2B1）-2 R&D of Stacking & Joining evaluation procedure• Development of bonding technology, structure, material, process
and evaluation technology

Material -１ (Underfill )- Filler（size / quantity / resin )- Characteristic (CTE / Modulus /- Encapsulation process• Research of evaluation technology for micro joint

etc … )

Semiconductor• Development of reliability evaluation technology for micro joint• Proposal of optimal design and design ground rule

Supplier

Interposer
インターポーザ

supplier)
Material -2 ( Bump / material- Structure ( Size/height/pitch)- Composition (Cu -Cu / CuSn / SnAg / In etc … )- ProcessFatigue mechanism

Grain slipping• Stacking technology development for in-car device application
Reliability test
- Stress type (TC, THB etc … )- Stress condition(2)-B R&D for Thermal / Chip Stacking Technology

March 8, 2013

Test
vender
試験メーカー©2013 Association of Super-Advanced Electronics Technologies

(2)-B R&D for Thermal / Chip Stacking Technology

106

Goal

Objectives 2012.4-2013.3 (Final objective) ：• Evaluation and analysis technology development for heat release structure with morethan 20W power consumption per 3D stacking SiP• Development of optimal design and evaluation technology of thermal cooling structure
assuming in-car high temperature environment and proposal of thermal design guideline• Development of die bonding evaluation and analysis technology for in-car device andproposal of bonding evaluation technology specification

Benefits ：In order to realize 3D SiP device which requires more power dissipation and die
stacking with micro joint, the fundamental infrastructure of the structure design, thematerial development and the manufacturing process can be built and it makes the
product release to market easy.

(2)-B R&D for Thermal / Chip Stacking Technology

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

107（2B1）-1 R&D of thermal performance and cooling solutions

Results■ R&D of cooling structure under high ambient temperature (1/4)
Assuming the automobile interior, perform the optimization of cooling structure underhigh ambient temperature, and develop its evaluation procedure.
（Collaboration with Toyama Prefectural Univ.）

Proposal of cooling structure from the peripheral of Si IP and its overall design including lens units
Requirements• Heat generation of image sensor 2Wmax. x2、Tjmax. =85deg.C, Tambient=65deg.C• Unable to cool from the top of image sensor ⇒ Cooling from the peripheral of Si IP
Overall design of image sensor
Objective lensComponents

Cooling fins

Objective lens unit

Heatpipe
Cu heatsink
Cu heatsink

Heatpipe

3D image sensor x 2
3D image sensor
Organic substrate

Si Interposer
Organic substrate

Cross section(2)-B R&D for Thermal / Chip Stacking Technology

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

108（2B1）-1 R&D of thermal performance and cooling solutions

Results■ R&D of cooling structure under high ambient temperature (2/4)
Conditions

Examination of the temperature increase(DT) distribution in cooling structure

Tj Max.

85℃

T ambient

65℃

DT

20℃

DT : Temp. increase in the
package, including thecooling structure

Components
Distribution of DT

Objective lens unit

⊿T
Heatpipe

Cu heatsink
3D image sensor x 2
Si Interposer

Within 3D chip tack

10℃

Between Si IP andambient

10℃

Total

20℃

-> Replaced by a heaterTop view

3D imagesensorCu heatsink /heatpipe

Organic substrate

Lens and color-filter
Between Si IP and ambient
ΔT～10℃

Heat generation of image sensor ～ 2W x 2Image sensor

CDS

Image sensor

ΔT～10℃

CDS

ADC

ADC

Interface

Interface

Cu heatsink /heatpipe

Si interposer
Organics substrate(2)-B R&D for Thermal / Chip Stacking Technology

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

（2B1）-1 R&D of thermal performance and cooling solutions

109

Results■ R&D of cooling structure under high ambient temperature (3/4)
Proposal of necessary thermal bump density for the improvement of thermal performance within
3D chip stack■When cooled from the bottom of 3D chip stack, by increasing the thermal bump density between ADC and Interface,also between Interface and Si IP, DT within 3D chip stack is reduced to 10deg.C
Correlation between the Si IP thickness and the thermal performance
Heat flow bottleneck

Correlation between the thermal bump density and DT

110
100
90
80
70
60

Si IP
200
400
600
Si IP thickness
Si IP thickness (mm)(μm)

Si IP thickness as aparameter

Si IP thickness should
be more than 400mm

Heat flow within 3D chip stack
Image sensor~485mW

CDS~657ｍW

ADC~657ｍW

Interface

デジアナ混載デバイスのΔ T(C)
DT
within 3D chip stack (deg.C)

chip

DT within 3D chip stackMax. chip(deg.C)Max temp
chip temp.
(C)（Full area-array - thermal bump density 20%）

14
12
10
8
6
4
2
0

~255mW

Si Interposer

Target DT ：10deg.C

1
5%

2
5%

3
5%

4
5%

5%

5%

5%

5%

5%

5%

5%

20%

5%

10%

20%

20%

Thermal bump density

Heat generation ~2W x 2(2)-B R&D for Thermal / Chip Stacking Technology

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

110（2B1）-1 R&D of thermal performance and cooling solutions

Results■ R&D of cooling structure under high ambient temperature (4/4)

Components

Heatpipe

Cu Heatsink
3D image sensor⇒ Replaced by a heater

Si Interposer

Organic subs.

Heatpipe
Cooling fins

Cooling fan

DT between image sensor and ambient (℃)

Prototyping of cooling structure from the peripheral of Si IP, using heatpipe
Demonstration of DT within 3D chip stack below 11deg.C（Performed by Toyama Prefectural Univ.）
Adhesive （Epoxy）：0.4W/mK
Silicone grease ：4.5W/mK：assuming 15W/mK
SolderAdhesive (Measured)

Silicone grease (Measured)

Target of DT
Solder (Calculated)

Heat generation／Sensor
Contact between a heater and Cu heatsink significantly influences DT.

Temp. measurement point（Thermocouple）(2)-B R&D for Thermal / Chip Stacking Technology

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

111

Results•

Die stack technology, structure, material, process and evaluation technology
development–

Consideration of micro bump joint material and structure–

Discussion to electro-migration with considered structure–

Consideration of 3D stack joining process•

High accurate joining for 10mm pitch, 5mm solder bump performed successfully•

Measurement of micro bump strain with SEM-DICM （SEM－Digital Image
Correlation Method）•

R&D of 3D integration technology–•

C2C 4 die stacking with considered bump structure

R&D of digital-analog hybrid 3D integration technology–

Consideration of process flow for low temperature solder joining–

Consideration of micro bumping method for low temperature solder(2)-B R&D for Thermal / Chip Stacking Technology

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

112（2B1）-1 R&D of thermal performance and cooling solutions

Results■ R&D of Stacking & Joining, Structure, Materials Process and Evaluation Procedure （1/4）
Develop reliable chip interconnection technologies for over 10K bumps with less than 5mm in diameterby using test vehicles with fine pitch bumps, and develop reliability assessment technology byacceleration tests (temperature cycle, high temperature storage, and steady state temperature humidity
bias test for electro-migration).
Propose optimized interconnection structure and its chip-join process condition for advanced 3D-SiP.

Prioritization for bump material and chip join process selection, and selected results for fine pitchinterconnection technology study
Priority

Bump

Pad

Fine pitch
enableReliablejoint

Lowloadingpressurejoin

Material
cost

Bumping
processtime

Chipjoining
time

Low
cost
chip join
tool

Au

Au

△

○

○

○

◎

◎

◎

Au(stud)

Solder

△

×

◎

○

△

○

◎

Au

ACF on Au pad

△

△

◎

△

◎

○

◎

UBM+solder

Cu

△

○

◎

◎

◎

○

◎

UBM+Cu pillar+solder

Au+Ni+Cu

○

○

◎

◎

◎

○

◎

UBM+Cu pillar+Ni+solder

Au+Ni+Cu

○

○

◎

◎

◎

○

◎

Cu

Cu

◎

○

×

◎

◎

×

×

•
•

UBM - Cu pillar - solder system is adapted.
For ultra fine pitch bump, Ni barrier layer is adapted between Cu-pillar and solder(2)-B R&D for Thermal / Chip Stacking Technology

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

113（2B1）-2 R&D of Stacking & Joining evaluation procedure

Results■ R&D of Stacking & Joining, Structure, Materials Process and Evaluation Procedure （2/4）
Cu pillar-Ni barrier bump is suited for fine-pitch interconnections• Cu pillar and solder materials form Inter Metallic Compounds (IMCs) which have high-melting
temperatures during the wet-back process. One needs to raise the bonding temperature, if the
IMCs are near the surface of solder bumps.
• Reaction time of Cu and Sn is rapid. Ni barrier reduces Cu diffusion into solder materials. The
rate of formation of NiSn IMC is slower than that of CuSn IMC
1. Stabilize the bonding condition by reducing IMC layer
formationwith Ni barrier
w/o Ni barrier
SnAgCuIMC 0.5-1µm

Cu

Young’s modulus measurement of joint by nanoindentation
SnAgCuIMC:
0.1-0.2µm

Ni
Cu

w/o Ni barrier
Cu
CuSnIMC+
Ni

with Ni barrier
Cu
NiSnIMC+Ni

CuSnIMCw/o Ni barrier

Max. Relative 1st Principal Young's Modulus (GPa)Stress (%)

a protective layer(PtPd)

2．Effect of high-modulus of the interconnection tomechanical reliability ⇒ No significant difference
between Cu-Sn IMCs and Ni-Su IMCsNiSnIMC100
50
0Thick IMC layer formation ⇒rise in bonding temperatureThin IMC layer formation

3. Improve reliability by reducing void formation.
with Ni barrier
w/o Ni barrier Cu
Cu
Cu3Sn
Cu6Sn5Ni
A number of voids

NiSnIMCNi

FEA result
Cu
Ni
NiSn IMC
Ni

max

7

90 100 (%)

17 27 38 48 59 69 79

void formation decreasing(2)-B R&D for Thermal / Chip Stacking Technology

March 8, 2013

w/o
Ni barrier

withNi barrier

Maximum Stress by FEM
100
80
60
40
20
0
w/o
with
Ni barrier Ni barrier©2013 Association of Super-Advanced Electronics Technologies

114（2B1）-2 R&D of Stacking & Joining evaluation procedure

Results■ R&D of Stacking & Joining, Structure, Materials Process and Evaluation Procedure (3/4) Electro-migration test
using ES2 test vehicles
Test vehicles with 50μm pitch interconnections showed no failures during 700 hrs of electro-migration reliability
test with current density of 50kA/cm2 at 100deg.C.
Assembled test vehicle
No significant change or failures observed
during 700hrs of @100deg.C
Si interposer 15mm□725
mmt

Evolution of resistance of a tested chain

Resistance V1-V7 (Ω)

Si die 5mm□、50μmt

Ceramic Substrate 60mm□ 0.9mmt

t=700hrs@100℃

t=0hrs

1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0

0.245A (50kA/cm2)

0200Interconnection structure
EDX

400
600
800
Test duration (hrs)

1000

Cu

Si

SEM

Current direction

Cu TSV

Ti
Si

Ni
Sn
Ni

current in
Si-IP

current out

tested interconnections(2)-B R&D for Thermal / Chip Stacking Technology

TiSi

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

（2B1）-2 R&D of Stacking & Joining evaluation procedure

115

Results■ R&D of Stacking & Joining, Structure, Materials Process and Evaluation Procedure (4/4)
Multi-chip Stacking by Pre-apply ICF (Inter Chip Fill) Film
• Fits for narrow gaps in fine-pitch 3D integration• High process stability• Reduced temperature cycles, low stress bonding process

Batch solder bonding by ICF film

3-chp batch bonding by ICF

Film ICF w/dicing tape function
2-chip bonding

TV40N-1

TV40N-2

TV40N-3
Sub. For test

7.3 x 7.3 mm
Film
ICF

TV40-1 (650μmthick) Si chip

Joint Dev. w/Thin wafer WG

TV40-2(50μm thick
W/TSV)

TV40-3 (725μm thick)Si IP)

40μm pitch

70m Ohm / (bump + wiring)

TV40: 40 mm pitch Test Vehicle(2)-B R&D for Thermal / Chip Stacking Technology

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

116（2B1）-2 R&D of Stacking & Joining evaluation procedure

Results■ Process, material, inspection technology for fine-pitch 3D interconnection
Dynamic Alignment method for fine-pitch bonding (10-mm pitch, 5-mm dia.)• High precision and in-situ alignment method, utilizing IR transmissive observation• Up to 11,520 series bumps connected. Connection resistance: ~70mOhm/bump
Dynamic alignment method
1.
2.

Bump/Pad structures
SnAg

5 μmφ

(plating thickness:3μm)

Cu or Ni studContact: 2 μmφ(plating thickness:3μm)

6 μmφ(plating thickness:0.1μm)

Ni(plating thickness:3μm)

Coarse alignment(reflective light)

TiN/Al/TiN(a) Solder bump

4.

Au

WiringSi substrate

3.

Contact shockcorrection

Alignment at
small gap
(30 -60 mm)

Alignment withsolder melted

Contact: 3 μmφ(b) Au/Ni pad

Resistance [Ohm]Resistance of daisy chains
900
800
700
600
500
400
300
200
100
0

y = 0.0686x + 2.3845

0

5umf SnAg solder bumps

Au/Ni Pads(2)-B R&D for Thermal / Chip Stacking Technology

Cross-section of joined 10
mm pitch bumps
March 8, 2013

2000

4000
6000
8000
Number of bumps

10000

12000

Measurement result of daisy-chained joint©2013 Association of Super-Advanced Electronics Technologies

（2B1）-2 R&D of Stacking & Joining evaluation procedure

117

Results■R&D on reliability evaluation of fine-pitch 3D interconnection Collaboration with Kyoto Univ.
Observation of thermo-mechanical strain of 10mm pitch interconnection by SEM-DICM(Digital Image Correlation Method)• Strain measurement resolution of 25nm
Prototype : TV10（10mm pitch)
Example of SEM-DICM photo

Bump layout
100mm

10mm pitch

Elemental analysis by EDX
Ni
Ni3Sn
Ni3Sn4Ni3Sn
Ni(2)-B R&D for Thermal / Chip Stacking Technology

Measured strain at 125deg.C (Strain free at 25deg.C)
March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

（2B1）-2 R&D of Stacking & Joining evaluation procedure

118

Results■ R&D of 3D integration technology
Develop common essential technology for 3D integration, assess design standards as acommon library of building elements of 3D stricture.
ES#2 C2C 4-layer stackCu pillar/Ni barrier/SnAg solder bump structure for 4-layer ES2
Chip size(5mm)
Chip thickness
Min. pitch
TSV Dia.
Pad
Solder bump

Si-IP (t~725mm)

50um
50.4mm20mm
Au 0.1mm/Ni 6mm
SnAg 3mm/Ni/Cu 1mm

Al pad15×15 mm50um
50.4um

3rd Chip

50um

50.4um

4th Chip

2nd Chip

1st Chip

50um

50um

4-layer stacking by thermal
compression bonding

Observed area
4-layer daisy chain

Al wiring

Si-IP(725um thick)(2)-B R&D for Thermal / Chip Stacking Technology

3-layer daisy chain

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

119（2B1）-2 R&D of Stacking & Joining evaluation procedure

Results■ Analog/Digital hybrid 3D Integration(1/2)
Development of elemental technologies for constructing analog/digital hybrid
stacks for image processing system (sight assistance system).
Development of bonding process for automotive drive assist 3D image sensor• Bonding: Image sensor - Si interposer - DeCap chip (embedded de-coupling capacitor chip)• Min. bump pitch: 80 mm, bump size: 50 mm• Max. process temperature: 180deg.C (upper temp. limit of image sensor)
Joining process

Cleaning

SiIP

3D image sensor

Joining

Cleaning

Aliment/joining(160deg.C, 40N)
Ｆｌｕｘ (B) coat

DeCap

UF injection, debubble(RT/15m),
cure(120deg.C/2h, A. P.)

Flux removal

Image sensor

SiIP/DeCap
SiIP/DeCap

Cleaning
Cleaning

Flux removal(120deg.C /1h)

Ｆｌｕｘ (A)coating

Aliment/joining(160deg.C, 5N)

UF injection, de-bubble(RT/15m),
cure(120deg.C/2h)

SiIP cross-section(2)-B R&D for Thermal / Chip Stacking Technology

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

120（2B1）-2 R&D of Stacking & Joining evaluation procedure

Results■ Analog/Digital hybrid 3D Integration (2/2)
Low melting point solder bump fabrication for automotive drive assist 3D image
sensor （SiIP – DeCap joining）• Ball mounted SnBi eutectic solder (ball size 50mm dia. )• Solder height control by fly-cut (40mm ⇒ 10mm)
SiIP chip

DeCap chipLow M. P. SnBi solder ball
(50 mm)Fly-cut

Min. pitch 80 mm, 50 mm dia. bump(2)-B R&D for Thermal / Chip Stacking Technology

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

(2)-B R&D for Thermal / Chip Stacking Technology

121

Summary(2B1)-1 R&D of thermal performance and cooling solutions
1.

R&D of cooling structure under high temperature environment (digital-analog hybrid 3D integration technology –evaluation of cooling system prototype for drive assist 3D imaging sensor)

2.

•

Consideration of cooling structure that can release a heat only from underneath 3D stacking system•

Design and prototype parts build for objective lens holder combined with thermal plate•

Release of design guideline for thermal bump to reduce the thermal resistance between chips•

Capability validation of heat release of 4W power dissipation with ⊿T= 20℃

Consideration of guideline for UF thermal conductivity on chip with micro bumps(2B1)-2 R&D of Stacking & Joining evaluation procedure
1.

Joint structure, process technology
1.

Optimization of solder bump material and structure2.

Perform electro-migration evaluation with optimized structure3.

Succeeded 1 step 3D die stacking using pre-applied film ICF(Inter Chip Fill)2.

Succeeded 10μm pitch solder joining

3.

Enabled strain measurement of less than 10um pitch joint with SEM-DICM

4.

R&D of 3D integration technology
Performed 4 die stacking with ES#2 samples

5.

R&D of digital-analog hybrid 3D integration technology
Developed C2C joining process with micro low temperature solder
Processed SiIP - Decap(embedded capacitor) joining on drive assist 3D image sensor(2)-B R&D for Thermal / Chip Stacking Technology

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

122(2) Evaluation and Analysis Technology Development for 3D Integration
Multifunctional High Density 3D Integration Technology(2)-C Thin Wafer Technology

Haruo Shimamoto

Integration Basic Technology Research Lab.
3D-Integration Technology Research Development
Association of Super-Advanced Electronics Technologies ( ASET )March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

Background of Study

123

Background

Trend of Packaging■Shift from Chip stacked SiP・POP to 3D Packaging （More Than Moore)■Wafer Process applied Packaging Technology

Trend of CPU Performance & DRAM Band Width■High transmission rate (～12.8GB/s) DRAM requires Wide Bus I/O for power reduction■High-end Application needs High Speed Image Processing⇒TSV/3D Technology is inevitable for High Volume/High Speed World■ Ultra Thin Wafer Technology is important to achieve TSV/3D Structure■ Ion Contamination & TSV Stress affects the Device Electrical Characteristics(from Renesas Electronics)
March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

Issues for 3D-TSV Packaging[1] TSV formation:- Via filling- Front bump, Rear bump

[2] FC attach:- Thin chip pickup & bonding- UF formation (NCF/NCP)
Wide-I/O memory

mold resin

TSV

SoC

Challenges[3] Test:- Test methodology- Microbump probing

substrate[4] Thin wafer/chip handling:- Temporary support attach- Back Grinding- Debond- Gettering Effect124

Total thickness< 1.0mm[5] Substrate/Assembly:- Layer configuration- Warpage control- Molding for overhang

Ultra thin Wafer Handling(target:10μm,≦30μm）
Establish the process not to make influence
on device characteristics
・Mechanical stress・Impurity Ion Contamination
March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

Thin Wafer Technology

125

R&D subject（2C1）-1 Development of 10 μm Ultra Thin Wafer Thinning Process
Technology without any influence on Device characteristics（1）Backside Grinding： Considering about Gettering Potential and Stress Relief（2）Ultra Thin Wafer Handling■ High Temperature Resistance Adhesive for WSS■ 10 μm Ultra Thin Wafer Backside Grinding, Dicing, and Die Pick-up Technology（2C1）-2 Investigation of Device Characteristics Change by Wafer Thinning
Process depend on Metal Contamination and Mechanical（1）Countermeasure for Transistor/Device Characteristics Change(2）Design Guideline of Device Layout considering Device Characteristics Change■ Investigation of Intrinsic Gettering using BMD and Extrinsic Gettering using
Laser induced damaged Layer■ Investigation of DRAM Device Deviation by using ES#2TEG【Co-operated with TOHOKU University （Prof. Koyanagi ＆ Prof. Tanaka)】（2C1）-3 Development of Ultra Thin Wafer Thinning Process Technology for
W2W Structure（1）W2W Machining Technology■ Backside Grinding & Dicing Technology Development

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

Thin Wafer Technology

126

Goal

Final Target ：・Achieve the Ultra Thin Wafer Process Technology in high accuracy（TTV：±1μm）
・Investigation of Device Characteristics Change by Wafer Thinning
Mechanical Stress and Metal Contamination
・Propose the Evaluation Metrogy of Gettering Effect

Effects ：Realize the Development of advanced materials, process and device
technology depend on continuous Wafer Thinning Trends(1) reduction / exclusion of the Wafer/Die breaking potential(2)Realize the high reliability device without the device properties change

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

127

To achieve 10μm Wafer Thickness

Results■A summary of the Thin Wafer handling technology①Achieve 10μm handling from WSS to Die Pick-up（TTV±1μm）②Propose New Process for Dicing to UF③Propose New Measurement Method for Thin Die Strength

Process

WSS

Approach・Flatting Disk・GlassSpecification

Issue

Backside
Grinding

TSV
Formation

DicingPick-up

Bonding～UF・AutoTTV
・NCG

・high Temp.
adhesive

・Optimizationof Dicing Tape・SlidePick-up・PreapplyUF・Optimize Tape depend on Bump Array
・Tool Design dedicated to Chip Size・Voidless UF at narrow Gap

・WSS Standardization
・Stable Flexural Strength
Measurement Method

ICF : Inter Chip Fill

Standardization of
Flexural Strength
Measurement
March 8, 2013

Development of New
Process using ICF©2013 Association of Super-Advanced Electronics Technologies

Dicing/pickup Chalenge of Conventional Technology

128

Results■ Normal dicing tape is difficult to achieve dicing quality and easy pickup
DicingPickupCorrelation between(Dicing and pickup quality) vs (bump coverage)a normal dicing tape cannot
bury backside bumps
because of large chipping
and water influx under dicing.
Dicing Failure picture

when bumps are buried in the
dicing tape tightly, die cannot
be separated from dicing tape.
Pickup Failure picture(dicing tape backside）

Backside chipping

Water influx

Separated area is only edgeof die which is not bump.

March 8, 2013

good

Dicing quality

Pickup quality
bad

Dicing tape

Dicing quality
Pickup quality

Dicing blade

bad

Bump coverage

good

Dicing quality and easy pickup aretradeoff.
the optimal coverage changes withbump density and height. So wehave to select dicing tape depending
on bump density and height.

©2013 Association of Super-Advanced Electronics Technologies

129

New process flow “UBD method”

Results■Merit of UBD New method “UBD （Under-fill Before Dicing) ”①Prevention of dicing chipping and crack ②Easy pickup③Void less
④ICF layer guards backside bump
⑤apply to narrow die gap
Process flow

UBD process flow （new method）

Conventional flow
adhesive

Formation of
Backside bumpDicing tapelamination

ICF：Inter Chip Fill（NCF）
glass

glass
ICF
(NCF)

Dicingtape

The dicing tape with ICF
layer is laminated.

Glass debondblade

Die is not cracked underdicing, because backside
bumps are buried in ICF
layer tightly.

DicingPickup is easy, because
peel point is between ICF
and tape adhesive

PickupDie stackUnderfill

March 8, 2013

Void less. Narrow gap is OK.

©2013 Association of Super-Advanced Electronics Technologies

130

Concept of ICF Material Design

Results■ Design Concept of ICF Tape・It is important to control adhesive strength of each interface
Adhesive strength relation of Each interface（glass adhesive/wafer） ＜ ( dicing tape/ICF)＜＜ （wafer/ICF)

Adhesive power comparison(Glass adhesive/wafer) interface

Glass adhesive

waferOver 8 N/20mm （measurement limit）(wafer/ICF) interface

ICF

UV type(before UV）
Dicing tape(dicing tape/ICF) interface

Adhesive power measurement condition
glass adhesive/wafer interface ： 90° direction power at 170° peel
wafer/ICF interface：90°peeldicing tape/ICF interface：90°peel

UV type(after UV）
Non UV type

Adhesive power (N/20mm)

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

131

UBD Evaluation Result (1)Results■ Dicing & Pick-Up Evaluation

・No Chipping

・No Water Penetration

・Easy Pick-Up

Dicing Evaluation
Sample Structure
Issues

Improvement

TV40（40μm pitch Full Array）

ICF

11μ m ｔDicing Tape

110μ mCountermeasure

Bump Height：Ave10μm

Water Influx

Pick-up Evaluation
Needle Pick-up Method

Die Chipping

Improvement of Dicing Condition
and adhesive strength

March 8, 2013

Die Thickness

Pick-up Result

50μm

OK

15μm

OK

Die strength up by attached ICF
material ⇒Standard Die Pick-up Tool isenough for even 15μm thick©2013 Association of Super-Advanced Electronics Technologies

132

UBD Evaluation Result (2)Results■ C2C Flip Chip Bonding Evaluation

・Good Solder Joint
・No Void in ICF Under-fill
7.3mm□
Bump (168 pcs)

Si TEG （40μm pitch）

TSV

Bump (168 pcs)

40μmp Full Array

Si Interposer

Au/Ni

ICF
Si

Cu(3.5μm）

10μm（Bonding Condition）
Force: 50N
Pre Heat: 170℃
Post Heat: 280℃

Au/Ni(3μm)

ICF

SnAg
(3μm）

Si Interposer

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

UBD Evaluation Result (3)133Results■ ICF property optimal evaluation

・Sample 2 which is reduced flux cont. is the best in 4 sample.
・Flux reaction promotes ICF curing before bumps connect.

n
e
e

n
O

r
c
S

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

134

Cost Advantage

Results■ Summary of UBD Process

・ UBD process is cheaper than other conventional process about 13～24%
・ 10μm thick Die can be easily Pick-up
・ Good Solder Joint and less UF Voids

組立コスト相対比Assembly cost (arb. unit)

Assembly cost estimation（Dicing tape laminate ～UF injection）

△13%

△24%

Process costMaterial cost

ICF
UBD

（estimation condition）①300mmΦ, yield 70%②die size 8mm□
③assembly yield 100%UF
Conventional process

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

135

Proposal for SEMI Standardization■ New Proposal : CANTILEVER BENDING METHODResults（≦30um）

・ Possible to measurement even at 10μm thick Die
・ Start to standardize at SEMI-Japan 3D-IC Study Group
Initial Position
Bending Tool

Bending Region

Broken PointDie

Grind Side
Height : X

Stage

Stage

Stage

Measurement Force Result（10umthick）
Applied Force （ｇ）

Broken Point

Bending Strength：15.46g
Bending
RegionBending Value：240μm

InitialPosition

10μm
Die

3 point Bending Method
March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

Gettering Methods in Thin Wafer

136

Results■ Several Methods to protect metal contamination

・Fabrication of Gettering Layer
1）IG Layer ⇒ BMD2）EG Layer ⇒ Backside Grinding3）EG Layer ⇒ SiN Deposition
4）EG Layer ⇒ Laser Irradiation

Device Side

SiO2
Layer

Barrier
Metal

Fabricated in Front-end Process
Fabricated in Back-end Process

TSV

IG:intrinsic gettering
EG:extrinsic gettering
DZ:ｄenuded zone
BMD：bulk micro defects

DZ
BMD
IG Layer
EG Layer
Barrier Layer Damaged
Layer

InducedDefectMarch 8, 2013©2013 Association of Super-Advanced Electronics Technologies

137

Intrinsic Gettering by BMD

Results■ DZ Layer is controlled by Ar anneal［IG Layer]＝［Wafer Thickness]－［DZ Layer］■ Cu Diffused from IG Layer ⇒ Anneal ⇒ C-t method
2. Sample Cross Section

1. Evaluation Sample
Thickness
(μm)

BMD
(μm)

DZ
(μm)

60

40

90

10

10

40

40

10

100

50

10μm

DZ：10μm Wafer

DZ
BMD

ＢＭＤ
40μm
Back Side Thinning
DZ：40μm Wafer(Experiment Sample)

40μm
ＢＭＤ

DZ
BMD

DZ
100/
50um

BMD

10μm

IG Layer : X um
BMD > 1x10

90μm

9

60μm

Back Side Thinning/cm3

Cu 100nm
March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

138

Evaluation of BMD Gettering EffectResults■ BMD 60um has better Gettering Performance than P/P■ Lifetime slope of BMD is one half

Generation lifetime,
τg(μsec)

Wafer thickness :100(μm)

700Ref. sample (P/P-)
60μm
BMD 40μmDZ sample

600
500
400
300
200
100
0

0

50

100

150

Annealing time (min)x 300C°

Minority Carrier少数キャリアの寿命（τg）のアニール時間依存性
Lifetime dependency by Cu annealing time
March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

139

Extrinsic Gettering by Backside Finish

Results

UPG > DP-new > CMP■ Extrinsic Gettering Potential: DP-new > UPG > CMP⇒ Uniformity of Damaged Layer is Important
Damge after backgrinding
BG

Roughness

Damaged Layer

Thickness 10um

30um

UPG

BAD

GOOD

6.1nm

400nm

DPnew

GOOD

GOOD

1.6nm

100nm

CMP

GOOD

GOOD

0.17nm

50nm

Normalized generation lifetime(τg, %)■ Thickness of Damaged Layer：

DPnewTreated Wafer

p/p- Wafer

UPG Treated Wafer
CMP Treated Wafer

100

50

0

0

10

20

30

40

50

60

Annealing Time (min)UPG (Ultra Poly Grind)

DPnew (New Dry Polish)
March 8, 2013

CMP

©2013 Association of Super-Advanced Electronics Technologies

140

Extrinsic Gettering by Laser Irradiation

Results■ New Proposal for EG by using Laser Irradiation■ Defect Zone is variously fabricated by Laser Conditions
Sample Ａ

Sample Ｂ

Si(400)、Mo Target

Ｘ-ray
Topography

Warpage Control
Ｇreen Laser/
LD Power Density＝80%/89%

Energy Density/
Mild LD Power

NonIrradiation①①
White Image：
Large Warpage②②

NonIrradiation

200mmφ200mmφCross Section Observation

Depth : 17μm

330μm

PolishZone

3°②

Irradiation Polish
Zone
Zone

Irradiation
Zone

Diagonally
Polish （3°）＋
Selective Etching

100μm② 100μm

Depth ：1.5μm

30μm

3°

Defect AREA：Top Surface～1.5μm
March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

141

Evaluation of Gettering Effect by SIMS

Results■ Gettering Potential is detected near to Top Surface

ＳＩＭＳ Profile
Sample Ｂ②
Cu EG Region

Cu Conc.[atoms/cm3]

Sample B
Sample B②
Sample A②

Sample Ａ②
Cu EG Region

B

B

B②

B②
A②

A②

Detection Lower Limit
01

Depth[μm]TEM Observation

Ｂ②

A②
DefectDefectSample B②：
Top～1μm Cu Gettering
Sample A②：
1μm～6μm Cu Gettering≒Φ20nm size
Poly Si and/or
Amorphous Si

Dislocation
Network
March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

142

Comparison of EG EffectResults■ Gettering Potential is #2000＞LaserA＞DPnew＞LaserB

Cu Diffusion Evaluation by TXRF
Sample B

Sample C

Sample D

BottomSample A,B⇒ Laser Induced Defect

Top

DPnew

Laser

Non-Irradiation

Laser

Sample C,D⇒ BG Damaged Layer（DPnew,#2000BG）

Non-Irradiation

Gettering Potential：G

Cu Conc. [atoms/cm2]

Sample A

Normalized the Upper Data
（Ref.⇒■ bar）
Gettering Potential Index ：G

SIMS

G=

1
1-（(R-C）/R）

R：Cu Conc. of Top Surface at Non-EG Zone
C：Cu Conc. of Top Surface at EG Zone

1

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

Young’s Modulus of Thin Wafer

143

Results■ Young’s Modulus is drastically decreasing

under 50um thickness(Measurement : Nano-Indenter method)

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

DRAM Retention Characteristics Change

144

Results（ about 50% is reduced）■ No difference between Twin and Triple Well w/o Cu Contamination■ Some damage depend on Wafer Thinning induce Degradation■ Retention Time is depend on Si Thickness

Well Structure

Memory area
メモリセルが形成されている部分

Die:200μmｔ

March 8, 2013

Die:30μmｔ©2013 Association of Super-Advanced Electronics Technologies

W2W Structure Dicing Result

145

Results■ Chipping Counts are depend on W2W Bond Resin■ Need control Si 1st Cutting Depth and specify Cu Area on Dicing Street

W2W Structure（Cu pattern exists on whole Dicing Street ）747um

3 Die Stacked

Dicing Area

IP
Cu
ES01
Cu

22um
12um
25um
8um
680um

PBO

（Dicing Speed：10mm/s）
Chipping

1st Cut

Cutting Depth

ES02

Dicing Evaluation

Bonｄ Resin
Epoxy
PBO
Polyimide○：＜10μm
×：Si Crack

After 1st Cut

Numbers of Chipping points/Dicing Street：Blade 30krpm

ReduceSurface Bottom○○○～△ ○～△△
×△：＜20μm

Chipping Mode

Cutting Depth：50um：Blade 50krpm

ReduceMetal exists in Dicing Street

Cutting Depth：250um

No Metal exists

Chipping points are reduced by Si 1st Cutting Depth
March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

Thin Wafer Technology

146

Summary（2C1）-1 Development of 10 μm Ultra Thin Wafer Machining Technology
without any influence on Device characteristics
・TTV：±1μm is achieved on the Wafer with μBump
・High Thermal Resistance Adhesive for WSS is introduced
・New Process UBD（Underfill Before Dicing) is proposed for Cost Reduction
・New Method of Flexural Bending Strength is proposed to SEMI for Standardization（2C1）-2 Investigation of Device Characteristics Change by Wafer Thinningdepend on Metal Contamination and Mechanical・Degradation of DRAM retention characteristics reduce to ½ is mainly induced bywafer thinning process because of mechanical strain
・We were able to propose about possibility of new Gettering technique and show theBase Data for considering each device structure.
・Si bulk Young’s Modulus is drastically reduced under 30um by strain in the
crystalline structure（2C1）-3 Development of Ultra Thin Wafer Machining Technology for W2W
Structure
・TTV：±1μm is also achieved on the W2W（2/3 Wafer Stacked) Structure
・Si １st Cutting Depth is important to reduce Si Chipping under Dicing Process when
Cu is left in the entire surface on a Dicing Street.
March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

147

Multifunctional High Density 3D Integration Technology(1)-A Design Environment technology(Finished by FY2010)

Hideki Tanaka
1st Solution Business Unit
Renesas Electronics Corporation

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

148(1)-A R&D of Design Environment
Digital Consumer Product System

Target of Electromagnetic Analysis Time

SiP

PWB
A
GHz Analog
SignalRF-IC
Low Speed
DigitalHigh Speed
Memory(NAND)

SoC(Logic)Simulation Time
A'
Memory Bus(200MHz~1GHz)

Data ofInterposer

High Speed
Memory(SDRAM)

3D Modeling

2 Days2 DaysElectromagnetic
Analysis

1 Day

2 Months

Digital
(2.5Gbps~)

High Speed Memory

TSV

Generate
Circuits
1 Months

SoC(Through Si Via)

16Signals 128Signals
Target(Actual) (Estimate)High Speed
Serial

NAND FlashSiP

Background

SiP Interposer

Execute

Half
a day

3 Days

Output(PWB)- SI Evaluation Report- Receiving Terminal
Wave form

Cross Section of 3D-SiP Part (A-A’)

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

149(1)-A R&D of Design Environment

BackgroundRole of each simulator
Wire

TSV(Through Silicon Via)
LSI2
LSI1

Gold Stud Bump
LSI3
PKG
Interposer
Bypasscapacitor
Solder Ball
GND
IO PowerCore PowerElectrical circuit
Simulator [Wasabi]Electromagnetic
Simulator[Zantho]Circuit and Electromagnetic
Co-Simulator [MuSEJ]

Board

PWB

LSI

PKG

Avail.

RLGC

RLGC model extracted by Q3D etc. can be used.
SI analysis including PKG effects can be executed in short TAT.

Avail.

The behavior of the electromagnetic wave can be observed in time domain.
SI analysis including PKG effects can be executed by replacing from
LSI(I/O Buffer) netlist to compact model like as current sources.
To shorten computation time using by multiple GPUs.

Avail.

The fluctuation of power supply voltage induced by LSI can be analyzed intime domain. Simulation time is longer than single solver model because
Electromanetic simulator in co-sim model can handle only one GPU.

N/A

Avail.

Note

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

(1)-A R&D of Design Environment

150

R&D subject

1) R&D of 3D Electrical Circuit Simulation Technology
To develop the sufficient practical simulator by improving the calculating capabilityof 3D electrical circuit solver and 3D electromagnetic field solver. This simulator will
be used for analyzing next generation 3D SiP.
2) Investigation of enhancing Signal Integrity(SI) and Power Integrity(PI) technology
To develop the SI and PI technique to stabilize circuit operation
3) To design the specification of Interface(I/F) between several 3D Devices
To design the specification of electrical and mechanical interface which can connect
CMOS device, functional device and etc.
Intermediate Target (FY H22) :- 3D Electrical Circuit Simulator : To develop the simulation engine that can enable toanalyze more than two-order number of meshes and more than eight times wide signal
buses with the same computation time as present.
- SI and PI for 3D-SiP: To develop SI and PI technology for 3D SiP.
Final Target (FY H24) : Finishing the investigations with two years ahead of initialschedule because of achieving the final target at the intermediate point (FY H22).
- To complete the development and evaluation of the 3D electrical simulator which canenable to analyze more than two-order number of meshes and eight times wide signal
buses with current same computation time.
- To describe the specification of electrical and mechanical interface which canconnect CMOS device, functional device and etc.
March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

(1)-A R&D of Design Environment

151

R&D subject(1A1) R&D of High Speed Electrical Circuit Simulation Engine
To develop the innovative algorism for electrical circuit simulator engine to enablehigh speed analysis. e.g. RLGC-MNA *1, LIM *2, etc.
To develop the new simulator including new innovative algorithm.
To develop the 3D interface specification that can be used by all semiconductor
company at the design stage.

(1A2) R&D of High Speed 3D Electromagnetic Field Simulation Engine
To enhance the FDTD *3 algorism for 3D electromagnetic field analysis and to develop
the innovative algorism to enable high speed analysis.
To develop the new simulator including new innovative algorithm.
To develop the 3D interface specification that can be used by all semiconductor
company at the design stage.

(1A3) R&D of Co-Simulation Technology between High Speed Electrical
Circuit Engine and Electromagnetic Simulation Engine
To enable accurate simulation by integrating the electrical circuit simulator andelectromagnetic simulator as a co-simulation.

(1A4) Further Researching of the Co-Simulation Technology between
Thermal/Mechanical Simulator and Electrical Simulator
To study the requirements for co-simulation between thermal/mechanical simulator*1 MNA : Modify Nodal Analysis
and electrical simulator.
*2 LIM : Latency Insertion Method*3 FDTD : Finite-Difference Time-Domain

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

(1)-A R&D of Design Environment

152

Goal

Intermediate Target ( FY H22 ) :To develop the simulation engine that can enable to analyze morethan two-order number of meshes and more than eight times wide
signal buses with the same computation time as present.

Final Target ( FY H24 ) :To complete the development and evaluation of the 3D electricalsimulator which can enable to analyze more than two-order numberof meshes and eight times wide signal buses with the same
computation time as present.

Effect of This Research :In this research, it is possible to realize high speed 3D circuit
simulator and high speed 3D electromagnetic field simulator engines.
These simulators can improve the product competitivenesssignificantly in semiconductor companies because of minimizing
simulation time dramatically.
March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

(1)-A R&D of Design Environment

153

Results[ Summary]March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

(1)-A R&D of Design Environment

154

Results(1A1) R&D of High Speed Electrical Circuit Simulation Engine

It was confirmed that Wasabi is more than 1000 times faster thanconventional simulators in the case of 256 wires circuit.
Speedup Rate (aslx01)
10000
aslx01_1th
aslx01_2th
3677.3
aslx01_4th

2568.2

aslx01_8th

1854.8
845.2

1000
531.2
517.3
421.5

726.5
583.0

699.6

424.6

231.6

100

64

128
[Number of wires]
March 8, 2013

256

©2013 Association of Super-Advanced Electronics Technologies

155(1)-A R&D of Design Environment

Results(1A2) R&D of High Speed 3D Electromagnetic Field Simulation Engine

Orthogonal Mesh

Sub-Grid Method
Point- Clear and simple- Staircase
approximation- If there is nonorthogonal shape,small meshes areneeded to express
the correct shape.

Point- Local(small) meshes
are only needed atneighborhood ofanalysis shape.
- It is possible toanalyze each time step
between global
meshes and local
meshes.

Conform Grid Method

It doesn't need staircase
approximation.

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

(1)-A R&D of Design Environment

156

Results(1A2) R&D of High Speed 3D Electromagnetic Field Simulation Engine (Zantho)
It can be estimated that Zantho takes less than 10 hours for analysis of thewhole PKG. (It takes 7 months by using conventional simulator).

CPU Time [sec]Accelerated by GPU
X30~130(1.59day)x4.5(1.7h)

x5(7.6h)

Conform Grid
(Subcell)
Sub-Grid

FDTD Analysis Scale(# of Meshes x # of Time Step)

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

157(1)-A R&D of Design Environment

Results(1A3) R&D of Co-Simulation Technology between High Speed Electrical Circuit Engine
and Electromagnetic Simulation Engine
The target is divided into a part that requires high precision analysis which can besolved by electromagnetic simulator and the lumped-element part which can be analyzed
by the circuit simulator. Current source method is used for I/F between circuit simulator
and electromagnetic simulator.
Non-Linear Engine
Electromagnetic Field Analysis Engine
Chip 1

Chip 3Jisso Part (3D Mesh)

BufferGold bump+P/G net circuits circuits

Chip 2

Buffer+P/G net circuits

buff

I/F

I/F buff

BufferTSV+P/G net circuits circuits
buff

I/F

I/F buff

…

…

I/F

I/F buff

buff
buff

buff

buff

Power
and
GroundMarch 8, 2013

Bypasscapacitor

Other
Discretecomponents©2013 Association of Super-Advanced Electronics Technologies

(1)-A R&D of Design Environment

158

Summary

Summary
We developed the innovative circuit simulator including advanced
LIM for 3D electrical circuit. This simulator achieves 800 times
faster comparing with conventional circuit simulators.
We developed the innovative electromagnetic simulator including
grid reduction technology and GPU parallelism. This simulator
achieves 660 times faster comparing with conventional
electromagnetic simulators.
We confirmed the effect of new algorism (Advanced ADE-FDTD
Method).
We developed the high accurate noise estimation method to
combine the circuit simulator and electromagnetic simulator.
We confirmed that co-simulation between thermal/mechanicalsimulator and electrical simulator will be necessary to develop
the small and light digital home equipment or medical devices.
March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

Application status of "Zantho" in Renesas

159

1. Operating manual was published, and used widely in-house.
2. It is used for EMS and EMI pre-analysis of customer’s system board.
3. 6 products was analyzed by Zantho. The set board is about 20~30 cm
square, and has 4~8 layers (max. 30 layers).
4. Not only customer production support, it is used for basic feasibility study.
It contributed to the design of customer’s system board.

[ Main Improvements ]
No.

Item

Revision

Release date1

Place any medium (air etc.) to absorbing boundary insteadof the vacuum.

V2.7.1’11.12.02

2Improves user interface

V2.7.2’11.12.06

3Supports inductanceV2.7.2’11.12.06

4Dumps cross section view for ease of material settingV2.7.2’11.12.06

5

3D Electromagnetic viewing function

V2.7.3’11.12.08

6

Checking input syntax (Sim. time setting, etc.)

V2.7.4’12.01.06

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

Example of Signal Analysis between SoC and DDR 160

35mm

Non-Uniform

Non-Uniform

Uniform

Non-Uniform

SoC

Uniform
Non-Uniform

Nx

Ny

Nz

Total

Memory[GB]

TAT[h]

1515

1519

101

230M

17.57

10.05** 7 months is required by using only CPU

10mm
35mm

Only focused area is divided into 12um
uniform grids, and other areas are
divided non-uniform grid.

DQ50 Signals
Zantho(SoC)
Zantho(DDR)
SIWave(SoC)
SIWave(DDR)

10mm

DDR

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

161

IssuesThis tool is expected to be used in EMI/EMS analysis not only 3D
integrated circuits by taking advantage of the FDTD characteristics.
However target to be analyzed is too large, it is necessary to reduceuse of memory .
Customer PCB
100M Cells(50um grid)
74GByteIn order to suppress less than
18GByte memory use (it is limit of
3GPUs), it needs to be more than 4times memory reduction.

Improving
memoryefficiency

Analysis area
1/√2
GPU Limit(18GB))

Current

Improving
MemoryMarch 8, 2013

Reducing
Analysis area
©2013 Association of Super-Advanced Electronics Technologies

162

Multifunctional High Density 3D Integration Technology(2)-A Chip Test Technology(Finished by FY2010)

Shigeru Kannari

Chip Test Technology Research Lab.
3D-Integration Technology Research Development
Association of Super-Advanced Electronics Technologies ( ASET )March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

(2)-Ａ R&D of Chip Test Technology

163

ObjectObject of R&D
Standard 3D-IC’s production
process

Wafer

First
Circuit making
MiddleProcessing of TSV

wiringLast
Getting
KGD
3D stacking

Wafer Test & Burn-in＊KGD（ KGD:Known Good Die ）3D Stacking

Connectiontestn（levels）
Final test

Wafer to Wafer

Die to Wafer

Die to Die

Test technology of getting KGD by low cost, for all the kinds of 3D stacking method⇒R&D for the test technology of the method to get KGD in a wafer level
March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

164(2)-Ａ R&D of Chip Test Technology
Necessity of Known Good Die (KGD)【Yield of each die vs. after Stacking 】
1

Yield after Stacking

3D-SiC using many chips(Dies)If Yield of Dies is low⇒ Yield of 3D-SiC falls in proportion
to the Yield of Dies , Suddenly
For getting KGD,
It’s necessary to satisfy two condition.
1)At speed test on wafer
2)Wafer or Die Level Burn-in

1 チップの良品率
Yield in 1chip = 99%
0.8
95%

0.6
90%
80%

0.4
70%
60%

0.2
0

2

4

6

8

10

Number of Dies in 3D-SiP

New process for KGDConvenional
Conventional

Why is 1-TD Full-Wafer Contactor Studied?

High
temp.
Low
Temp.
temp.
High
Temp. Low
Functional
Functiontest Test

Background

High/Low
Hightemp.
Temp. High/Low
High
temp.temp.

Burn-in
Functional
Function
PackageBurn-In
ウェハ状態におけるtest Test
Implementation

Functional Test
test
Function
AtAt
speed
speed

・高速テスト（実動作速度：at speed）

・バーンイン・スクリーニング
New・一括テスト（ウェハ一括テスト）
Newprocess
Process
KGD
KGD
High/Low
High/Low
temp.⇒ 良品デバイス(KGD)のテスト・コ
temp.
to 3D Stacking
Wafer
Waferburn-in
Burn-In スト削減& testTest&

March 8, 2013

・High speed prove card and die-level
sockets are very expensive.
・It is effective for cost reduction to
performburn-in and test, simultaneously.
・The 1-TD Probe enables Integrationof Wafer-Wafer and Wafer-Dies.

©2013 Association of Super-Advanced Electronics Technologies

(2)-Ａ R&D of Chip Test Technology

165

Background

Study about Target of Device
Number ofchips / wafer
SoC high end

SoC
Middle end

SoC low end

DRAM

Flash・memory

Power supply・number of
GND

Number of signals

VDD
GND

256 ~ / chip
256 ~ / chip

I/O

total

250K / wafer

total 250K / wafer

VDD
GND

100 ~ / chip
100 ~ / chip

I/O

total

400K / wafer

total 500K / wafer

VDD
GND

50 ~ / chip
50 ~ / chip

total

500K / wafer

1000～1500

VDD
GND

25 ~ / chip
25 ~ / chip

Dr.
I/O

30 ~ / chip
15 ~ / chip500～1500

total
VDD
GND

75K / wafer
10 ~ / chip
10 ~ / chip

total
Dr.
I/O

68K / wafer
10 ~ / chip
10~ / chiptotal

30K / wafer

total

60K / wafer

500

1000～2000

3000～5000

I/O

512 ~ / chip

256 ~ 512 / chip

256 ~ / chip

total 750K / wafer

Power ・ current
consumption / wafer～ 10kA～ 30kW～ 5kA～ 15kW～ 5kA～ 10kW～ 300A～ 400W～100A～ 200W

Source : Prepared by Chip Test Research Laboratory using ITRS`s road map, etc.

Target device
・Number of chips／wafer：over 2000
・Power・current consumption ／wafer：5kA、15kW
・Total number of power・ＧＮＤ・signals／wafer：Over 1milion terminals
・Amount of information needed for test／chip ：Max 15Gbps
March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

166(2)-Ａ R&D of Chip Test Technology

Background

Challenge(1)Development of new structure probe card
・Probe which realizes necessary number of connections
・Assured probing method against increasing contacts【Load necessary probing】

Probe card

【Conventional wafer・test
structure】 Test System
Test head

4g
Wafer
Wafer tray
Prober4g/pad x 150 pads/chip x 2000 chips = 1.2t

0.6t
・Limitations of necessary load of 1-TD contact with wafer status⇒ Proposing non-contact probe
・Introduction of capacitive-coupling method
・Transmitter & Receiver circuit for capacitive-coupling probe（Probe chip）
March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

(2)-Ａ R&D of ChipTest Technology
Characteristics of capacitive-coupling method

Capacitive

167

Background

InductiveddNumber of contacts

☺

１

２

Sharing DUT bonding pad andnon-contact electrode

☺

Yes

No

☺

No
need

Need

<10μm

<100μ
m

Fine process requirement
Transmission distance☺

・Easy to increase terminals, space-saving、easy to manufacture⇒Small overhead of DUT and probe card
・Transmission distance⇒If electrodes of DUT and probe are able to become close,
the problem of transmission distance can be solved.
March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

(2)-Ａ R&D of Chip Test Technology
Characteristic comparison of the non-contact method

168

Background
C-Couple > L-Couple

n
e
e

n
O

r
c
S

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

169(2)-Ａ R&D of Chip Test Technology

BackgroundHeat-exchange efficiency
smallerbigger

Challenge(2)Development of power supply and thermal control
・The method of power supply growing with refinement of device process
・The method of thermal control according to wafer self-heating
15kW/300mmφ is・corresponding 15 times of electric hot plate・heats ５℃ in a second 1cm thickness copper plate

15k W/Wafer⇒ 2. 2×１０5 W/m2

3k W/Wafer
1k W/Wafer 125℃
125℃

85℃

85℃ 125℃ 85℃

Boil・
Latent heat of condensation
Forced circulation（Water）

Forced circulation（Air）
Natural circulation(Water)Natural circulation
Source：Shoji,「heat-transfer engineering」University of Tokyo Press
(Air)
100

101

102

103

104

Surface heat-transfer coefficient105(h [W/m2K])

Impossible with conventional air or liquid ⇒Proposing thermal control by elect efficiency of heat exchange (latent heat)
March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

(2)-Ａ R&D of ChipTest Technology

170

Background

Problem（３）Development of connection probe card and tester
・The method which supply high speed signal and power to probe card
Power supply 150Kpoint

Power supply system

Testermain
frame

Signalextension

SignalsystemProbe
card【Signal connection image】

Wafer

Signalcompress

Signal 150Kpoint

・In case of connecting probe card and tester main frame : Signal form 40K points
・It’s necessary to implement each connection point to probe card and tester
・Higher pin count and down-sizing is realized.
・Easiness of insertion-extraction at the time of changing probe card／connection stability／necessary pressure for contact are realized.
It’s difficult by conventional mechanical connector.
⇒ Proposing non-contact connection of signal system
March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

(2)-Ａ R&D of ChipTest Technology

171

R&D subject〔Image of probe card for next generation
wafer test (example) 〕（２Ａ１） R&D of 1-TD Wafer contact/non-contact capacitive-coupling probing
technology（2A1）-1 R&D of the 1TD probing technology of 300K pin/the 300mm wafer（2A1）-2 R&D of non-contact probing technology corresponding to probe cardwith high pin count probes
・R&D of probe card using non-contact (C-coupling ,L-coupling) probe
・Development of probes for high speed(chip access of over 15Gbps environment)
・Speeding up of non-contact probe/receiver circuit（２Ａ２） R&D of power supply & thermal control for measured device（2A2）-1 R&D of power supply technology for probe card
（2A2）-2 R&D of wafer thermal control technology〔Image of non-contact probe circuit (receiver) 〕

Wafer burn-in test under high temperature such as －４０～１２５℃ to realize KGD・Development of method which supply ５kA current to wafer
・Arrangement of large current power supply on probe, and cooling method
・Development of thermal control method of 10kW class heat generation,and cooling method（２Ａ３） R&D of connection technology between probing part and test system
・Connection technology which enable High speed/High density/High inter digitation
precision/Easing the inserting and removing force
・Development of high density & small connector of non-contact (Capacitive coupling,
Inductive-coupling) probe
・Trial make and evaluation of chip for Capacitive coupling, Inductive-coupling・Development of the large current supply connector

March 8, 2013

〔Image of connection structure between probecard and test head〕©2013 Association of Super-Advanced Electronics Technologies

(2)-Ａ R&D of Chip Test Technology

172

Goal

Interim target （Fiscal year 2010） ： Totally 300K probes are equipped, and about the parts of them, - high speed digital signal test
probe- , the basic technology for probe method for 300mm Wafer corresponding to over 15Gbps signal is developed.
About multiple probe card, the realization of non-contact connection method is evaluated.
Final target（Fiscal year 2012） ： As the probe corresponding to 300mm wafer, it is confirmed that 1-TD access to more than 300K
tested probes is possible. And about high speed signal test terminal, it’s confirmed weather the test using more than 15Gbps signal
is possible.
・ About 1 probe card, more than 10kW stable power supply technology is developed.
・ During the chip test on probe card, the thermal control technology which enables burn-in test at the heat range-40℃～+125℃ is developed.
・ Connecting the probe developed by the end of fiscal year 2010 to the tester, and it’s evaluated,
between probe card and test equipment, it is proved that the 40K system of test signal transmission including more than
500Mbps high speed test signal is possible.

Development of the probe card to get KGD⇒
An effect: KGD test environment of 3D-IC isregulated well and leads to the test cost reduction

1)

Development of the basic techniqueof the 300mm wafer probe method
・ 300K pin ,signal transmission of 15Gbps/DUT
are possible
・ Inspection of the non-contact probing technique2) Power supply (more than 10kW) and Temperature
control (-40 ～+125℃)
3) Signal connection technology more than
200ch/500Mbps
4) Actual proof test :・Confirmation of collective access being possible
・ Confirmation of what can test 15Gbps/DUT

Wafer
Development concept (figure of image)・186K pin
Mixture of a contact probe(150K pin) andthe non-contact probe(36K pin)・ Transmission speed 1Gbps

Non-Contact Probe
Tester Chip
（ Capacitive Coupling Pads
&Probe chip）
Cooling / Thermal control
March 8, 2013

Non-contact signal
connect（Capacitive
Coupling)©2013 Association of Super-Advanced Electronics Technologies

(2)-Ａ R&D of Chip Test Technology

173

Concept（１－１） R&D of the 1TD probing technology of 300K pin /the 300mm wafer
Concept of the probe card development

Signal Line【 Figure of structure image 】
DC-DC Converter
テストチップ（圧縮・展開、シリパラ変換）
Tester Chip
センスチップProbe（C結・ChipL結） ﾟContact Probe for Power

Wafer

Capacitive-Coupling Probe

Wafer Tray

1)Probing method: Pressurization using atmospheric pressure ⇒ 700kgf max.
2) Contact probe for power supply: Thin out of pins ⇒ 15K pin (75 pin / tip @2000chips/wafer)
3) Non-contact probe for signal : Thinning out test pins using the JTAG technology,
a compression SCAN technique ,Transmission speed 1Gbps/ pin ⇒ 36K pins
4) Mixture of a contact probe and the non-contact probe

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

(2)-Ａ R&D of Chip Test Technology

174

Concept（１－１）R&D of the 1TD probing technology of 300K pin /the 300mm wafer

Pressurization using atmospheric pressure

Atmospheric Pressure (9.8 N/cm2)

Wafer Tray
Ceramic Ring
Wafer

Vacuum Valve
Internal pressure (0.3~9 N/cm2)
Vacuum seal Ring

Maximum load :15.3[cm] 2 x π x 97[kPa] = 7,129 [N] ≈ 700kgf
Probe technology of the membrane method
・It is realized load of up to 700Kgf by pressurization using atmospheric pressure
・It is certain and keeps stable contact resistance a contact for the temperature change* It has been announced in Semiconductor Wafer Test Workshop 2009 (U.S. San Diego)
March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

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175

Results（１－１） R&D of the 1TD probing technology of 300K pin /the 300mm wafer【Development target specification】
・Target Wafer： 300mmφ・Contact probe： 15K
・Non-contact Probe ： 36K pin/Wafer
・Pad size： 60μm・Pad pitch： 90μm min.
・Current： 5ＫＡ・Power：15ｋＷ・ Temperature range ：－40～＋125℃

300mm

The Appearance photograph of the probe card （550mm×480mm)

Probing technology with 150K contact probes and 36K non-contact probes wasdeveloped
March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

176(2)-Ａ R&D of Chip Test Technology

Results（１－１） R&D of the 1TD probing technology of 300K pin /the 300mm wafer
Cross section of the probe card
Vacuumvalve
ポリイミド・メンブレン

Wafer Tray

Vacuum valve

Wafer

Tester chip

⑤Main board

common part

④Anisotropic
conductive rubber sheet

Probe chip

③Organic interposerPartdepending ona kind(2)Anisotropic
conductive rubber sheet①Polyimide
membrane

Wafer

Contacting pad

Non-contact pads

Contacting pad

The probe card which was comprised of 5 laminar structure
March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

177(2)-Ａ R&D of Chip Test Technology

Results（１－１） R&D of the 1TD probing technology of 300K pin /the 300mm wafer

Pressurization technique of the non-contact pad(1)Atmospheric Pressure (100kPa)

Wafer Tray
Wafer

Vacuum Valve

Probe chip
Before vacuum differential
pressure

１0kPa
１0KPa
Open
March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

178(2)-Ａ R&D of Chip Test Technology

Results（１－１）R&D of the 1TD probing technology of 300K pin /the 300mm wafer

Pressurization technique of the non-contact pad(2)Atmospheric Pressure (100kPa)

Wafer Tray
Wafer

Vacuum Valve

Probe Chip
After vacuum differential
pressure

20kPa
10KPa
C-Coupling
March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

179(2)-Ａ R&D of Chip Test Technology

concept（１－２）R&D of non-contact probing technology corresponding toprobe card with high pin count probes
Probe Chip

clock

Probe Card
TX（Transmitter）

DUTs on the Wafer
RX（Receiver）

data
FAD

DUT
RX（Receiver）

Transmission
TX（Transmitter）
line

Ｃｉｒｃｕｉｔ

clock
data

FAD

FAD: Feed-forward All-digital De-skewer（automatically skew adjustment）

Signal transmission technology with the transmission line in the probe cardwith complicated wiring structure» Reduction of the channel skews ⇒ Automatically skew adjustment» Reduction of the broadband signal reflection⇒ Low Pass Filter in a RX
March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

180(2)-Ａ R&D of Chip Test Technology

Results（１－２）R&D of non-contact probing technology corresponding toprobe card with high pin count probes
Transmitter
Data：8ch、Clock：1ch
Receiver
Data：8ch、Clock：1ch

clock
data(TX)

Measurement
waveform（1.8Gbps）

Measurement
environments＜Improvement items of trial chip on fiscal year 2010＞①Reinforcement of the restraint of the power supply voltagechange of RX circuit(2)Addition of power supply stabilization circuit③Equilibrium transmission of power supply line on evaluationboard

data(RX)

Number ofchannels
Transmission
speed

2009(*)

2010

4ch

8ch

1Gbps

1.8Gbps（*)At the time ISSCC2010 announcement

Probe chip (capacitive-coupling) was developed, and1Gbps non-contact transmission technology was established.
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(2)-Ａ R&D of Chip Test Technology

181

Results（２－１）R&D of power supply technology for probe card
Development target specification

40mm
Amp (amperometry ）DAC（Output voltage setting)

DC/DC

9A

3A

3A
38mm

3A
3A

Converter

9A

Current monitor
resistanceLow on-resistance
CMOS-SW(P-MOS)

Low on-resistance
CMOS-SW(N-MOS)•microcomp
uter・Substrate size 38mm×40mm
・Single-side 30A both-side 60A
Supply 7.5kA loading 125 pieces
・Power supply to 4DUT by single-side
・Arbitrary voltage output control by digitalpotential meter・Power ON/OFF control with low resistance CMOS-SW
・Whole the substrate is heat sinkby using copper core（1mmt）substrate
・The AD/DA built-in microcomputer deployment- Communication facility with tester chip
- Analog signal measurement of monitor DUT
of current consumption- DC/DC adjustment and self control ofpower supply module ID- self-interception function and power mask function

・Power supply to the tester chip/probe chip

Second trial manufacture of 3 power sources・12
outputs power supply module

Development of power supply technology which is over 15kW per wafer
March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

182(2)-Ａ R&D of Chip Test Technology

concept（２－２）R&D of wafer thermal control technology

Development concept of thermal control technology
・15kW wafer cooling and thermal control of±3℃ per 300mmφ in-plane
・Cooling wafer by taking advantage of water latent heat
・Wafer tray structure which has high specific thermal
conductivity, low contact thermal resistanceTarget specification

・Support 300mm diameter wafer
・Over 25 W/cm2 quantity of heat transfer
・Thermal control range : 70℃～150℃±3℃（When 20ｋW heat generated）

Basic structure

Equivalent circuit

Wafer
15kW
contact thermal
resistance

Wafer tray

⇒ 2. 2×１０5 W/m2

0.25℃/W
Thermal control plate
Sense

Thermal control equipment

March 8, 2013

Thermalcontrol©2013 Association of Super-Advanced Electronics Technologies

183(2)-Ａ R&D of Chip Test Technology

Results（２－２）R&D of wafer thermal control technology
Thermal control range
180

Controlled-temperature ；ST（℃）

160

Upper limit of control

140
120
100
80
60

Lower limit of control

40
20
0

5

10

15

20

heat generation load；Q（kW）

Experimental device forcooling technology by the latent heat

It is developed that the 20kW cooling & thermal control technology(70℃～+150℃)
which enables 1-TD wafer burn-in test.
March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

184(2)-Ａ R&D of Chip test technology

concept（３）R&D of connection technology between probing part and test system

Adopted capacitive-coupling method＜Advantage of non-contact connector＞
１）No signal break by contact damage２）No wear, infinite durability of insert & remove３）Realized to change to ZIF by no drive mechanism.
→breakthrough of the downsizing
and multi-polarization

Connector
body

FPC

Probe chip
（non-contact
communication
function）

Taking advantage of the characteristic mentioned above,
invented the concept which enable to compose
by minimal parts（Before interdigitation）

Non-contact
Pad（C-coupling）

Board

Current of electrical signal（After interdigitation）＜cross-sectional view of the development
concept of the non-contact connector＞

Press between coupling pad byreaction force of FPC,
then keep coupling distance.

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

185(2)-Ａ R&D of ChipTest Technology

Results（３） R&D of connection technology between probing part and test system

The trial product appearance

Capacitive-coupling pad（0.5mm pitch）

Transmission wave form

Development target specification
・ Signal channels ： 200
・ Pad placement：
0.5mm pitch、4x50mm
・ Non-contact pad size：0.3mm
・ Signal transmission speed ：500Mbps～1Gbps
・ Size：約30x6x5(mm)BER bathtub curve
1.00E+00
500Mbps
1Gbps
1.5Gbps
1.7Gbps

1.00E-01
1.00E-02
1.00E-03

Bit Error Rate

1.00E-04
1.00E-05
1.00E-06
1.00E-07
1.00E-08
1.00E-09

500Mbps

1Gbps

1.00E-10

0.85UI@500Mbps

1.00E-11
1.00E-12
-500

-400

-300

-200

-100

0

100

200

300

400

500

UI

Non-contact connector (capacitive-coupling) of 200 channel / over 500Mbps transmission speed was developed.
March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

186(2)-Ａ R&D of Chip Test Technology

concept（４）Trial manufacture and system evaluation of the 1-TD wafer probe card
High speed bus（7.5Gbps)
Tester chip・
controllerHigh speed bus（7.5Gbps)

Tester chip
＃１

Tester chip
＃５００Power supply
modulePower supply
module

Probe
chip
＃１

Probe
chip
＃５００

Probe card

capacitive-coupling

capacitive-coupling

ＤＵＴ Wafer
ＤＵＴ
ＤＵＴ
ＤＵＴ
ＤＵＴ

ＤＵＴ
ＤＵＴ
ＤＵＴ
ＤＵＴ

・1-TD test for maximum 2000 DUT（Maximum speed １Ｇｂｐｓ／pin）⇒Tester chips & probe chips function and power supply modules are mounted on theprobe card, which has both contact and non-contact probe.
・Targeting the test with ＪＴＡＧ technology, compress scan technology.

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

187(2)-Ａ R&D of Chip Test Technology

Results（４） Trial manufacture and system evaluation of the 1-TD wafer probe card

Test technology which is able to 1-TD burn-in & test was developed.

Tester chip (ASIC ver.)・chip size 5x5mm

Probe chip（ASIC ver.）・chip size 4.3x4.3mm

clock

data(RX)

Measurement waveform whenTransmission speed 1Gbps（non-contact communication）

・ The 1-TD wafer probe card (300mm diameter Wafer size , 1/10 chip count)
・It was confirmed that the test of the maximum transmission speed of 15Gbps/DUT is possible.
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188

Summary
We developed 1-TD wafer test technology aimed at getting KGD for 3D-IC
１．The 1-TD wafer probe technology to make ultra high pin count coexist with non-contact probe wasdeveloped.
・Probing technology with 150k contact probes and 36k non-contact probes was developed.
・1Gbps non-contact signal transmission technology by capacitive-coupling method wasestablished.
２．The power supply technology and thermal control technology which is able to 1-TD burn-in wasdeveloped and experimental proved.
・Power supply method of over 10kA per wafer was developed.
・20kW thermal control technology(70℃～+150℃) by cooling latent heat was developed.
３．Non-contact signal connect technology was developed.
・Non-contact connector (capacitive-coupling) of 200 ch/over 500Mbps transmission speed wasdeveloped.
４．Test technology which is able to 1-TD burn-in & test was developed.
・Trial manufacture and system evaluation of the 1-TD wafer probe card using 300mm Wafer , 1/10
chip counts.
・It was confirmed that the test of the maximum transmission speed of 15Gbps/DUT is possible.

In the result, we achieved the final goal (fiscal year 2012)ahead of schedule, by the end of fiscal year 2010.
March 8, 2013©2013 Association of Super-Advanced Electronics Technologies

Acknowledge

189

This project is entrusted by NEDO “Development of Functionally Innovative
3D-Integrated Circuit (Dream Chip) Technology” .
The project is based on the Japanese government‘s METI “IT Innovation Program”.

March 8, 2013©2013 Association of Super-Advanced Electronics Technologies