Special Feature: Front-line Materials Research

Graphene Growth on Silicon Carbide
Hiroki Hibino†, Hiroyuki Kageshima, and Masao Nagase
Abstract

With the aim of developing a single-crystal graphene substrate, which is indispensable for practicalapplications of graphene, we are experimentally and theoretically investigating the structural and physical properties of graphene grown on silicon carbide by thermal decomposition.

1. Introduction
Graphene is a two-dimensional sheet of carbon
atoms in a honeycomb lattice: it corresponds tomonolayer (ML) graphite. Although graphene haslong been a subject of theoretical investigations, it
was not until 2004 that graphene was actually produced by mechanically exfoliating graphene flakes
from bulk graphite (exfoliation method) [1]. Since
then, graphene has come to be regarded as one of themore promising candidates for an electronics material in the post-Si era owing to its superior electronictransport properties and compatibility with planar
lithographic techniques.
Graphene has various potential applications. Its
huge carrier mobility at room temperature makes it
promising as a channel material in field effect transistors. In graphene, carriers can travel long distances
without scattering, which is a favorable characteristic
for quantum-effect and spintronics devices. Becausegraphene is highly sensitive to the environment
because of its pure two-dimensionality, it is applicable to highly sensitive chemical/biological sensors.
Other applications are also expected for graphenesheets comprising from one to a few layers of graphene, which is commonly referred to as few-layer
graphene (FLG). FLG exhibits intriguing physicalproperties, depending on the thickness. For example,owing to its flexibility, transparency, and good conductivity, it could be applicable to flexible transparent
electrodes.
In the exfoliation method, graphite flakes repeat† NTT Basic Research Laboratories
Atsugi-shi, 243-0198 Japan

edly peeled off with adhesive tape to cleave them in
two and make them thinner and thinner are deposited
on a Si substrate covered with thermal oxide. Exfoliated graphene does not require any special instruments, and the quality is good because it originatesfrom bulk graphite. In general, however, the flakes
are small, typically about 10 µm wide, and the yield
is low. Though the exfoliation method is suitable forbasic physics and device demonstrations, an alternative fabrication method is essential for graphene tobecome an industry.
For large-scale FLG production, methods of growing FLG epitaxially on SiC by thermal decomposition (Fig. 1) are attracting intense interest. When SiC
substrates are annealed at high temperatures, Si
atoms selectively desorb from the surface and the C
atoms left behind naturally form FLG. Because SiC isa wide-band-gap semiconductor, FLG on SiC canserve as a graphene substrate for electronics applications. SiC wafer technology is advancing rapidly interms of production cost and scale, and our results todate indicate that the thermal decomposition method
is indeed suitable for large-scale FLG fabrication.
However, two fundamental problems must be
solved before the thermal decomposition method canbe used industrially. First, the FLG obtained so far
has had a thickness distribution. Because the electronic properties of FLG depend on its thickness, wemust establish a reproducible way of growing wide,
uniform FLG with the desired thickness. Second, we
still do not fully understand how the SiC substrateaffects FLG’s physical properties. Without a practicalassessment of the substrate’s effects, it is difficult tochoose the most appropriate applications of FLG. In
this article, we describe how we are trying to solve
NTT Technical Review

Special Featurethese problems both experimentally and theoretically.
2. Theoretical investigation ofgraphene growth mechanism
To establish a method of growing large-scale FLG

SiCSiC
SiC

with the desired number of layers, we must clarify thegrowth mechanism. For this purpose, using a firstprinciples method, we theoretically calculated stablestructures that appear when C atoms are added one by
one on the SiC(0001) surface [2]. The stable structures at various C coverages are shown in Fig. 2. We
found that, at a C coverage of 8/3 MLs, corresponding to 8 C atoms on three SiC unit cells, C atoms forma graphene-like two-dimensional sheet and arestrongly stabilized. Figure 2(a) shows top and sideviews of the structure. Some C atoms in the twodimensional sheet form bonds with Si atoms on theSiC substrate. Therefore, the C sheet does not exhibit
the electronic band structure characteristic of graphene and is usually called a buffer layer or the 0thlayer.
When more C atoms are added, they become highly
unstable on the buffer layer and prefer to reside
between the buffer layer and SiC substrate, as shownin Fig. 2(b). At a C coverage of 16/3 MLs, a new buffer layer is formed at the interface and the original
buffer layer loses bonds with the substrate (Fig. 2(c)).
Therefore, the top C sheet possesses an electronicstructure similar to that of ideal ML graphene. This
top C sheet is ML graphene on SiC.
3. Evaluation of number of graphene layers

SiCFig. 1. Schematic illustration of thermal decomposition
method.

(a) C coverage: 8/3 MLs

A method of microscopically evaluating the number of graphene layers is a starting point for optimization of the growth conditions. The number of graphene layers on SiC can be determined from thequantized oscillations of the electron reflectivity [3].
Electrons have wave-like properties, and theirkinetic energy determines the wavelength. Therefore,(b) C coverage: 3 MLs(c) C coverage: 16/3 MLs

Fig. 2. Calculated stable structures for various C coverages.

Vol. 8 No. 8 Aug. 2010Special Feature

2Dark

Bright(c)3Dark8157SiC

3.0 eV(a) Electron interference2(d)7Electron reflectivity (arb. units)466543210
4.5 eV

8500 nm(b) LEEM instrument(c)−(d) LEEM images

2468Energy (eV)(e) Electron reflectivityFig. 3. Microscopic evaluation of number of graphene layers.

as schematically illustrated in Fig. 3(a), electrons
reflected from the graphene surface and graphene/
SiC interface can interfere, which causes the electron
reflectivity to change periodically as a function of theelectron energy and FLG thickness. The number ofgraphene layers can be determined from the reflectivity oscillations.
Low-energy electron microscopy (LEEM) is themost suitable technique for this purpose. In theLEEM instrument, electrons with typical energy of afew electronvolts are incident to the surface, andbackscattered electrons are used to form magnified
images of the surface. A photograph of our LEEM isshown in Fig. 3(b). LEEM images obtained at two
different energies are shown in Figs. 3(c) and (d). The
LEEM image intensity corresponds to the electronreflectivity. From LEEM images sequentiallyobtained while the electron beam energy waschanged, we obtained the energy dependence of theelectron reflectivity from regions 1 to 8, as shown in
Fig. 3(e). Periodic oscillations are clearly seen. Thinner FLG provided longer oscillation periods, indicating that graphene sheets 1–8 layers thick were formedon regions 1–8, respectively.

4. Understanding and controlling
growth processes
LEEM is also suitable for analyzing the graphene
growth processes. LEEM images in Fig. 4 indicate
structural changes that occurred when the SiC substrate was annealed gradually at high temperatures inan ultrahigh vacuum (UHV) with pressures of lessthan 10-8 Torr. After annealing at 1060ºC, preferential
nucleation of the buffer layer occurred at the atomic
steps on the SiC surface, where 1/3 of the ML of Si
adatoms was periodically arranged (Fig. 4(a)). Afterannealing at a higher temperature (Fig. 4(b)), thewhole surface was covered with the buffer layer andthe surface steps meandered widely. The number of Catoms in ML graphene is nearly equally to the number of C atoms in three SiC bilayers. This means thatmany atoms moved during the buffer layer formation,
which explains the step meandering. At the initialstage of graphene growth, ML graphene preferentially formed near the substrate steps (Fig. 4(c)).
When the annealing temperature was furtherincreased, bilayer (BL) graphene appeared before thebuffer layer completely disappeared (Fig. 4(d)). Thismeans that uniform ML graphene is difficult to growin UHV.
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SiC surface

Special Feature

500 nmBuffer layer
SiC(a) After annealing at 1060°C(b) After annealing at 1230°C

112

Buffer layer

112(c) After annealing at 1320°C

2(d) After annealing at 1360°CFig. 4. Evolution of SiC surface structures with annealing.

However, we found that further annealing led torelatively uniform BL graphene. Therefore, wefocused on optimizing the BL graphene growth conditions. At present, we can grow uniform BL graphene as large as several micrometers square, as
shown in Fig. 5(a) [4].
5. Local electrical conductivity measurements
To understand how the SiC substrate affects theFLG’s properties, we measured the local electricalconductivities of FLG using an integrated nanogap
probe (Fig. 5(b)). The nanogap probe contains two Pt

Vol. 8 No. 8 Aug. 2010

electrodes with a gap of 30 nm fabricated at the tip ofthe cantilever of an atomic force microscopy (AFM)
apparatus. As the surface morphology is obtained byAFM, electric currents between the electrodes aresimultaneously measured [5], [6].
An electrical conductivity map of BL graphene isshown in Fig. 5(c). Linear contrasts, which correspond to the substrate steps, reveal that the substratesteps modify the electrical conductivity. As shown inthe transmission electron microscopy (TEM) imagein Fig. 5(a), FLG covered the substrate steps like acarpet. FLG was locally bent near the steps, and thisbending could affect the carrier transport.

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16

Conductivity (µS)

Tip ofnanogap probe(30-nm gap)

Nanogap
Nanogap probe

Bilayer

30 nm
Electrode 1 Electrode 2 Electrode 1
Electrode 2

Trilayer

Nanoga1 µm(a) LEEM and TEM images of BLgraphene

pArrangementof nanogap probe
and sample

SaSideO 2 roSi lectetP

14121086~20 nm

4200204060

80100Position (nm)lemp

100 nm(b) Integrated nanoprobe(c) Local conductivity map and line profile

Fig. 5. Local electrical conductivity measurement using integrated nanogap probe.

6. Towards single-crystal graphene substrate

Acknowledgment

Our theoretical investigations have shown that a
new buffer layer is repeatedly inserted below the oldone. Therefore, FLG always maintains its epitaxialrelationship with the SiC substrate. The topmost graphene originates from the initial buffer layer and iscontinuous everywhere across the substrate step andacross the boundary between the regions with different numbers of graphene layers. These results showthat the thermal decomposition of SiC is a suitable
way of producing a large single-crystal graphene substrate.
By optimizing the growth conditions on the basis of
the microscopic evaluations of the number of graphene layers, we have succeeded in growing uniform
BL graphene a few micrometers in size by UHV
annealing. It has been reported that annealing in Ar
atmosphere greatly improves the uniformity of MLgraphene [7]. This suggests that annealing environment control could be useful for selectively growing
FLG with a desired thickness.
The local electrical conductivity measurementswith the nanogap probe have revealed that the conductivity was modified near the substrate steps. The
effects of the SiC substrate on the FLG’s properties
should be clarified in more detail. We need to exploit
the positive effects and eliminate the negative ones.
Furthermore, to expand the possibilities of graphene
technology, we need a method of transferring FLG on
SiC to other substrates.

This work was partly supported by Grants-in-Aidfor Scientific Research or KAKENHI (19310085,21246006) from the Japan Society for the Promotionof Science.

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Yamaguchi, “Microscopic Thickness Determination of Thin GraphiteFilms Formed on SiC from Quantized Oscillation in Reflectivity ofLow-energy Electrons,” Phys. Rev. B, Vol. 77, p. 075413, 2008.
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NTT Technical Review

Special Feature

Hiroki Hibino

Senior Research Scientist, Group Leader, Lowdimensional Nanomaterials Research Group,
Materials Science Laboratory, NTT Basic
Research Laboratories.
He received the B.S. and M.S. degrees in physics from the University of Tokyo in 1987 and1989, respectively, and the Ph.D. degree in pureand applied physics from Waseda University,
Tokyo, in 2006. Since joining NTT Basic
Research Laboratories in 1989, he has been
studying surface dynamical processes using
microscopic techniques. His research interests
include step structures on vicinal surfaces, surface mass transport, step instability during epitaxial growth, self-assembled nanostructure formation, and epitaxial graphene growth. He spent
one year as a visiting research professor at Arizona State University from 2000 to 2001. He wasa visiting professor at Kyushu University (2009–2010) and is currently one at Tokyo Institute ofTechnology (2007–). He received the Japan Society of Applied Physics (JSAP) Young Scientists
Award for the Presentation of an Excellent Paperin 1997 and the Sakaki Encouragement Awardfrom the 141st Committee on Microbeam Analysis of the Japan Society for the Promotion ofScience in 2008.

Masao Nagase

Professor, Material Science and Devices,
Department of Electrical and Electronic Engineering, Faculty of Engineering, the Universityof Tokushima.
He received the B.E., M.S., and Dr.Eng.
degrees in nanometrology for nanodevices fromWaseda University, Tokyo, in 1982, 1984, and1997, respectively. In 1984, he joined the LSILaboratories of Nippon Telegraph and TelephonePublic Corporation (now NTT), where he worked
on R&D of fabrication processes for submicrometer VLSIs. In 1996, he moved to NTT Basic
Research Laboratories, where he researchedfabrication processes for mesoscopic devices,such as single-electron, NEMS, and graphenedevices in the Nanostructure Technology
Research Group of the Physical Science Laboratory. He moved to the University of Tokushima in2010. He is a member of JSAP.

Hiroyuki Kageshima

Senior Research Scientist, Nanodevices
Research Group, Physical Science Laboratory,
NTT Basic Research Laboratories.
He received the B.S. degree in physics fromWaseda University, Tokyo, in 1986 and the M.S.
and D.S. degrees in physics from the Universityof Tokyo in 1988 and 1991, respectively. Sincejoining NTT Laboratories in 1991, he has been
studying physics in semiconductor nanostructures and computational physics technologies.
He received the Best Poster Paper Award at theFall Meeting of the Materials Research Society,Boston, USA, in 1997 and the JJAP Paper Awardof JSAP in 2000. He is a member of the PhysicalSociety of Japan and JSAP.

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