Sponsored by:

Supported by:Welcome from the Mayor of Las Vegas

2

Welcome from ECTC General and Program Chairs
On behalf of the Program Committee and Executive Committee, it is my pleasure to welcome you to the 63rd Electronic
Components and Technology Conference (ECTC) at The Cosmopolitan of Las Vegas, Nevada, USA. This premier international
conference is sponsored by the IEEE Components, Packaging and Manufacturing Technology Society (CPMT).
The ECTC Program Committee represents a wide range of disciplines and expertise from the electronics industry around theworld. We have selected more than 300 high-quality papers to be presented at the conference in 36 oral sessions, four interactive
presentation sessions, and one student posters session. The 36 oral sessions cover papers on 3D/TSV, embedded devices, LEDs,
Co-Design, RF packaging, and electrical and mechanical modeling, in addition to topics such as advanced packaging technologies,
all types and levels of interconnections, materials, assembly manufacturing, system packaging, optoelectronics, reliability, MEMS,
and sensors. The program committee strives to address new trends as well as ongoing technological challenges. Four Interactive
Presentation sessions feature technical presentations in a format that enhances and encourages interaction. One student poster session
focuses on research conducted in academia presented by the emerging scientists. Authors from companies, research institutes, anduniversities from over 25 countries will present at the ECTC, making it a truly diverse and global conference.
In addition to the technical sessions, panel and special sessions focusing on crucial topics presented by industry experts enhance thetechnical program. In the special session titled “The Role of Wafer Foundries in Next Generation Packaging,” held Tuesday, May
28, at 10 a.m., session chair Sam Karikalan will gather a panel of experts to present and discuss their proposed business models andstrategies for embracing the next generation packaging needs of the industry. Key questions on cost, technology, assembly expertiseand industry growth will be raised for the wafer foundries to address. Another special session will be held on Tuesday and will address“Modeling and Simulation Challenges in 3D Systems.” This session co-chaired by Yong Liu and Dan Oh is made up of keynote speakers
as well as highlighted 3D modeling papers and will be held at 2 p.m. The Panel Discussion on Tuesday evening at 7:30 p.m., chairedby Ricky Lee and Kouchi Zhang titled “LED for Solid-State Lighting – For a Brighter Future,” will discuss emerging LED packaging
technologies and market trends. The Plenary Session on Wednesday at 7:00 p.m., chaired by Lou Nicholls and titled “Packaging
Challenges Across the Wireless Market Supply Chain,” will unveil the latest challenges of this growing industry with speakers fromacross the supply chain. Thursday evening starts with the Gala Reception at 6:30 p.m. and is followed by the CPMT Seminar at 8:00
p.m., which is titled “Advanced Low Loss Dielectric Materials for High Frequency and High Bandwidth Applications” and chaired by
Kishio Yokouchi and Venky Sundaram.
The Professional Development Courses (PDCs), organized by the PDC Committee chaired by Kitty Pearsall, will be taught on
Tuesday, May 28 (8:00 a.m.-5:30 p.m.). World-class experts in their fields offer 16 courses on different topics. Participants cancatch up on new technology developments and broaden their technical knowledge base. The technical program and professional
development courses are supplemented by the Technology Corner Exhibits where leading companies, primarily in the electronics
components, materials, and packaging fields exhibit their latest technologies and products. The exhibitors invite you to their reception
on Wednesday at 5:30 p.m. Along with our receptions and coffee breaks every day, luncheons are another great opportunity to
network and discuss technical and business matters. It is my pleasure to announce that Dr. Chris Welty of IBM will be the invited
keynote speaker at the ECTC Luncheon on Wednesday.
ECTC offers many opportunities. Whether you are a manager, engineer, executive or a student, I invite you to experience the exciting
developments in electronic components and technology during the 2013 ECTC. I also would like to take this opportunity to thank oursponsors, exhibitors, authors, speakers, instructors, session chairs, committee members, and arrangements, finance, publication, andpublicity chairs, as well as all the volunteers for their support and hard work in making the 63rd ECTC a great success. I look forward
to a great experience in exciting Las Vegas on May 28 - 31, 2013.

Wolfgang Sauter
General Chair
IBM Corporation

Beth Keser
Program Chair
Qualcomm Technologies, Inc.
3

Welcome from ECTC Sponsoring Organization
It’s Vegas again!
According to the previous statistics,
every time ECTC was held in
Las Vegas, it was always a big crowd.
I believe the same trend will continue
in 2013. For people who survived
from 2012 (if you know what Imean), you deserve a big treat andshould enjoy yourself as much as
possible in Vegas. Thanks to the effort
of ECTC Executive Committee, thisyear we have the conference venue set up at the magnificent
Cosmopolitan. Undoubtedly everybody will have a good timeat this modern and well-equipped hotel.
In addition to the great venue, we also have a very strong
technical program this year, in particular, on the 3D/TSV
topics. I am very pleased to note that the ECTC Program
Committee improved the Advance Program and compileda table of “Session Summary by Interest Areas.” This will

be very helpful for the attendees to navigate themselves
among interested topics and sessions. I would like to take thisopportunity to thank the Program Committee members fortheir thoughtful planning and considerate arrangement.
As a common practice, there are a number of activities
organized by CPMT within ECTC. In the evening of May
28, there will be a panel session on “LED for Solid-State
Lighting.” This panel will discuss emerging LED packaging
technologies and global market trends. On May 30, CPMT
will sponsor a plenary luncheon and several important awards
will be presented during the luncheon. In the evening on thesame day, a CPMT seminar will be held right after the Gala
Reception. This seminar will focus on “Advanced Low Loss
Dielectric Materials for High Frequency and High Bandwidth
Applications.” On behalf of the IEEE CPMT Society, I would liketo invite all of you to attend these special events.
See you all there!
Ricky Lee
President, IEEE CPMT Society

Conference Policies and Guidelines
BadgesConference attendees MUST wear the official conference badge to be admitted to all training courses, sessions, meals,
Technology Corner exhibits and all conference sponsored social functions.
Medical Services
For emergency medical services, locate any hotel phone, whether in your room or elsewhere in the hotel, and follow its
directions for emergencies. Hotel “house” phones have been placed throughout the hotel and conference area for yourconvenience. If no phone can be located, please locate the nearest hotel staff or ECTC staff for assistance with your emergency.
The closest available hotel staff person may be at the front desk.
Personal Property
The hotel’s safety deposit box is available for storing your valuables; particularly cash and jewelry. If there is a mini-safe in yourroom, you should consider using it.
Smoking Policy
The hotel allows smoking on its premises in designated smoking areas; however, smoking is NOT permitted at any ECTC
activities including, but not limited to, functions, events, sessions, or seminars as well. Thank you for your consideration andcooperation.

4

Table of Contents
Conference Policies & Guidelines.........................................................................................4
ECTC Luncheon Speaker........................................................................................................5iNEMI 2013 Roadmap Workshop........................................................................................5
Registration...................................................................................................................................6
PDC Instructors and Proctors Breakfast...........................................................................6
Session Chairs & Speakers Breakfast...................................................................................6
Speaker Prep Room..................................................................................................................6
Miscellaneous Information.......................................................................................................6
Luncheons.....................................................................................................................................6
ECTC Panel Discussion............................................................................................................7
ECTC Plenary Session .............................................................................................................7
ECTC Modeling Session...........................................................................................................7
CPMT Seminar............................................................................................................................7
Special Session: Next Generation Packaging and Integration the Transformed Role of the Packaging Foundry...........................................................7
Professional Development Courses....................................................................................8
Session Chairs & Speaker Reception...................................................................................863rd ECTC Gala Reception ..................................................................................................8
Technology Corner Reception ............................................................................................8
ECTC Student Reception........................................................................................................8
Continuing Education Units....................................................................................................82012 ECTC Paper Awards.....................................................................................................9
Committee Meetings.................................................................................................................9
Session 1: 3D Assembly and Reliability.............................................................................10
Session 2: 3D Materials and Processing............................................................................10
Session 3: Novel Interconnections.....................................................................................10
Session 4: Reliability Test Methods....................................................................................11
Session 5: New Directions in Packaging...........................................................................11
Session 6: Optical Interconnects.........................................................................................11
Session 7: Interposers.............................................................................................................12
Session 8: 3D Reliability and Packaging Challenges......................................................12
Session 9: Advanced Flip Chip Technologies..................................................................12
Session 10: Advancements in Manufacturing Technology..........................................13
Session 11: Biomedical Electronics.....................................................................................13
Session 12: High Brightness LEDs and Material.............................................................13
Session 13: 3D Processing and Technology....................................................................14
Session 14: 3D TSV Interconnects Reliability.................................................................14
Session 15: Enabling Technologies for Flip Chip Assembly.......................................14
Session 16: Interconnect Reliability....................................................................................15
Session 17: Adhesives and Underfill Materials...............................................................15
Session 18: Thermal and Mechanical Modeling & Simulation...................................15

Session 19: Interposer Characterization..........................................................................16
Session 20: Challenges in 3D Integration.........................................................................16
Session 21: Advanced Substrate and Flip Chip Packaging .........................................16
Session 22: Solder and Material Characterization........................................................17
Session 23: Novel Technologies..........................................................................................17
Session 24: Power and Signal Integrity..............................................................................17
Session 25: 3D Microbump Structures and Silicon to Silicon Bonding.................18
Session 26: High Speed Interconnects & Power Distribution
in 3D Integration.......................................................................................................................18
Session 27: Wafer Level and Embedded Packaging......................................................18
Session 28: Drop and Dynamic Mechanical Reliability................................................19
Session 29: Substrates.............................................................................................................19
Session 30: Electrical Modeling and Measurements.....................................................19
Session 31: TSV Innovation and Implementation..........................................................20
Session 32: Thermal and Mechanical Modeling: LED and 3D Structures.............20
Session 33: MEMS and Sensor Packaging.........................................................................20
Session 34: New Developments in Wirebond Technology......................................21
Session 35: Solder and Bonding...........................................................................................21
Session 36: System Components for RF and Millimeter Wave...............................21
Session 37: Interactive Presentations 1 (9:00 a.m. - 11:00 a.m.)..............................22
Session 38: Interactive Presentations 2 (2:00 p.m. - 4:00 p.m)................................22
Session 39: Interactive Presentations 3 (9:00 a.m. - 11:00 a.m.)..............................22
Session 40: Interactive Presentations 4 (2:00 p.m. - 4:00 p.m.)...............................23
Session 41: Student Interactive Presentations (8:30 a.m. - 10:30 a.m.).................23
Technology Corner Booth Layout.....................................................................................24
Technology Corner Exhibits.......................................................................................... 25-35
ECTC Executive Committee...............................................................................................36
ECTC Program Committee.......................................................................................... 36-38
64th ECTC Call for Papers...................................................................................................3964th ECTC Dates and Location..........................................................................................40
Conference Sponsors....................................................................................................... 40-41
Media Sponsors.........................................................................................................................41
Hotel Layout..............................................................................................................................42
Conference at a Glance.........................................................................................................43

Conference organizers reserve the right to cancel or change this program without prior notice.

ECTC Luncheon Keynote Speaker
Wednesday, May 29, 2013 • 12:00PM
Chelsea 1 & 5

Engineering Challenges in Building Watson
Presenter: Dr. Chris Welty
Research Scientist at the
IBM T.J. Watson Research CenterTwo years ago, the Watson Question Answering system received
widespread attention and acclaim by winning a two-game
tournament of Jeopardy!, the TV quiz show, against the best
players in the game’s history. While a significant advance in natural language processing,
Watson was ultimately a system engineered by a talented team of researchers, and someof the challenges we faced and surmounted make good lessons for engineering in general.
Christoper A. Welty is a Research Scientist at IBM Thomas J. Watson Research Center in
New York, and formerly a professor in the Computer Science Department of Vassar
College and a distinguished lecturer of the Association for Computing Machinery. He isbest known for his work on ontologies and in the Semantic Web.
Welty was one of the developers of Watson, the IBM computer that defeated the best
players on the American game show Jeopardy!. He was one of the 12 original members of
the Watson team and is identified as a member of its “Core Algorithms Team.”2013 iNEMI Roadmap North American
Workshop
Tuesday, May 28, 2013
1:00PM - 6:00PM
Condesa 6, 2nd Floor
Since 1994, iNEMI (the International
Electronics Manufacturing Initiative) has
been developing a biennial technology
roadmap spanning a 10-year horizon.
Since 2011 iNEMI has been holding
roadmapping meetings at ECTC.
This year we will be holding an open
meeting to prioritize the research needs
identified in the 2013 Roadmap; theoutput will be the publication of the2013 iNEMI Research Priorities.  
Open to all conference attendees.
5Registration, Receptions and General Information
Registration

Professional Development Course Instructors Breakfast

ECTC registration will be open at the ECTC Registration Desk
located on the 4th floor in the Chelsea Commons Area.

PDC Instructors and Proctors are required to attend a briefing
breakfast.

Monday, May 27, 2013 – 3:00 p.m. - 5:00 p.m.

6:45 a.m. Tuesday – PDC Instructors and Proctor Briefing(Room Location: Chelsea 2)

Tuesday, May 28, 2013 – 6:45 a.m. - 8:15 a.m.*(AM PD Courses & Special Session Only)*

Session Chairs and Speakers Breakfast
Session Chairs and speakers are requested to attend acomplimentary continental breakfast on the morning of their
sessions/presentations. At this time, presentations will betransferred to the conference PC, which is loaded with Windows
XP and MS Office 2003.

Tuesday, May 28, 2013 – 8:15 a.m. - 5:00 p.m.
(All conference attendees)
Wednesday, May 29, 2013 – 6:45 a.m. - 4:00 p.m.
Thursday, May 30, 2013 – 7:30 a.m. - 4:00 p.m.
Friday, May 31, 2013 – 7:30 a.m. - 12:00 p.m.
*The above schedule for Tuesday will be vigorously enforced
to prevent students from being late for their courses. Please
make sure to take advantage of the 6:45am start time on
Tuesday, May 28 as registration becomes very congested prior
to the start of morning Professional Development Courses.

Door Registration Fees
Door Registration with Proceedings on USB driveIEEE Member Full Registration . . . . . . . . . . . . . . . . . . . . . . . . . . . $725
IEEE Member Speaker / Session Chair . . . . . . . . . . . . . . . . . . . . . $625
IEEE Member One Day  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  $475
IEEE Member Speaker One Day . . . . . . . . . . . . . . . . . . . . . . . . . . $350
Non-Member Full Registration . . . . . . . . . . . . . . . . . . . . . . . . . .  $870
Non-Member Speaker / Session Chair . . . . . . . . . . . . . . . . . . . .  $625
Non-Member One Day . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . $475
Non-Member Speaker One Day . . . . . . . . . . . . . . . . . . . . . . . . . . $350
Exhibit Booth Attendant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .$0
Student . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  $250
Student Speaker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . $250
Exhibits Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . $20
Tuesday Professional Development Courses
IEEE Members and Non-Members
Tuesday AM or PM Course with luncheon . . . . . . . . . . . . . . . . . $475
Tuesday All-Day Courses with luncheon . . . . . . . . . . . . . . . . . .  $675
Tuesday Student All-Day Courses with luncheon . . . . . . . . . . . . $125
Extra Luncheon Tickets for each day . . . . . . . . . . . . . . . . . . . . . . . $50
Extra Proceedings with registration  . . . . . . . . . . . . . . . . . . . . . .  $100

7:00 a.m. Wednesday thru Friday(Room Location: Chelsea 1)

Speaker Prep Room
Speakers should prepare and review their digital presentations asfollows: 7:00 a.m. – 5:00 p.m., Tuesday – Friday (Room Location:
Yaletown 3)(It is extremely important to assure that your presentation, presentation
software and computer work flawlessly with the digital projector provided.)

Miscellaneous Information
Hotel Concierge
The Hotel Concierge, located in the hotel lobby, can direct you to
any show or restaurant, or give suggestions for that special night out.
The Concierge can help to make your visit and conference experiencea memorable one!
Message Center
Please use the hotel switchboard or the ECTC Registration Desk
located on the 4th floor, Chelsea Commons, to leave and pickup
messages. The hotel number is +1-877-551-7772.
Press Room
Press Interviews will be scheduled on an as-requested basis. To
coordinate an interview with conference leadership or presenting
technical experts, please contact Eric Perfecto at
perfecto@us.ibm.com or +1-845-894-4400.

Luncheons
Tuesday, May 28, 2013
Noon (Chelsea 2)
The Electronic Components
and Technology Conference
will sponsor a luncheon for all
Professional Development Courses
attendees, proctors and PDC
committee members.

6

Wednesday, May 29, 2013
Noon (Chelsea 1 & 5)
The Electronic Components
and Technology Conference willsponsor a luncheon for conference
attendees. Best and Outstanding
Papers will be awarded. The guest
speaker will be Chris Welty of
IBM Corporation.

Thursday, May 30, 2013
Noon (Chelsea 1 & 5)
The IEEE Components, Packagingand Manufacturing Technology
Society will sponsor a luncheon for
conference attendees. The CPMT
awards will be presented.

Friday, May 31, 2013
Noon (Chelsea 1 & 5)
The ECTC Program Chair willsponsor a luncheon for conference
attendees.
There will be a raffle for attendees.

Special Session, panel session, Plenary Session, CPMT seminar and Modeling Session
2013 Special Session

2013 ECTC Plenary Session

Tuesday, May 28, 2013
10:00 AM – Noon
Condesa 3, 2nd Floor

Wednesday, May 29, 2013
7:00 - 9:00 p.m.
Mont-Royal 1 & 2, 4th Floor

The Role of Wafer Foundries
in Next Generation Packaging

Packaging Challenges Across the
Wireless Market Supply Chain

Chair: Sam Karikalan,
Broadcom Corporation
Speakers:
Jerry Tzou, TSMCDavid McCann, GLOBALFOUNDRIES
Kurt Huang, UMC
Jon Casey, IBM Corporation
Herb Huang, SMIC

Chair: Lou Nicholls, Amkor Technology
Speakers:
Timo Henttonen, Nokia
Steve Bezuk, Qualcomm Technologies, Inc.
Waite Warren, RFMD
Roger St. Amand, Amkor Technology
SoonJin Cho, SEMCO
2013 CPMT Seminar2013 ECTC Panel Session

Thursday, May 30, 2013
8:00 - 10:00 p.m.
Mont-Royal 1 & 2, 4th Floor

Tuesday, May 28, 2013
7:30 - 9:30 p.m.
Mont-Royal 1 & 2, 4th Floor
LED for Solid-State Lighting –For a Brighter Future

Advanced Low Loss DielectricMaterials for High Frequency andHigh Bandwidth Applications

Chair: Ricky Lee, Hong Kong University of
Science and Technology
Co-chair: Kouchi Zhang, TU Delft & Philips
Lighting

Chair: Kishio Yokouchi, Fujitsu
Interconnect Technologies Ltd.
Co-chair: Venky Sundaram, Georgia
Institute of Technology

Speakers:
Ling Wu,
China Solid-State Lighting Alliance, China
Mark McClear, Cree Components, USA
Ron Bonne, Philips Lumileds, USA
Nils Erkamp, TNO, The Netherlands
Michael McLaughlin,
Yole Development, USA

Speakers:
Yuya Suzuki, Zeon Corporation
Yasuyuki Mizuno, Tsukuba ResearchLaboratory, Hitachi Chemical Co., Ltd.
Shin Teraki, NAMICS Corporation
Hirohisa Narahashi, The Research Institutefor Bioscience Products & Fine Chemicals,
Ajinomoto Co., Inc.

2013 ECTC Modeling Session
Tuesday, May 28, 2013 • 2:00 - 4:30 p.m.
Condesa 3, 2nd Floor
Modeling and Simulation Challenges in 3D Systems
Chair: Yong Liu, Fairchild Semiconductor
Co-Chair: Dan Oh, Altera
Keynote Speaker: Thermo-Mechanical Modeling of 3D Integration Technology: Impact of Actual Process Conditions and Non-ideal Material Properties on
Modeling Results, Eric Beyne – IMECA Comparative Simulation Study of 3D/Through Silicon Stack Assembly Processes, Kamal Karimanal – Cielution LLC
Thermo-Mechanical Challenges for Processing and Packaging Stacked Ultrathin Wafers, Mario Gonzalez, Bart Vandevelde, Antonio La Manna, Bart Swinnen, and Eric
Beyne – IMEC
Keynote Speaker: Cloud-Based Scalable Electromagnetic Solvers for 3D Package Modeling, Vikram Jandhyala – University of Washington, Nimbic
Signal and Power Integrity Analysis of a 256GB/s Double-Sided IC Package with a Memory Controller and 3D Stacked DRAM, Wendem Beyene, Hai Lan, Scott Best,David Secker, Don Mullen, Ming Li, and Tom Giovannini – Rambus Inc.
Optimization of 3D Stack for Electrical and Thermal Integrity, Rishik Bazaz, Jianyong Xie, and Madhavan Swaminathan – Georgia Institute of Technology

These sessions/seminars are open to all conference attendees.

7Professional Development Courses
Tuesday, May 28, 2013
Morning Courses 8:00 AM – 12:00 PM

Afternoon Courses 1:15 – 5:15 PM

Yaletown 4
1.“Lead Free Solder Joint Reliability­Material
Consideration”
Course Leader: Ning­Cheng Lee – Indium
Corporation

Yaletown 4
9.“Packaging Failure Analysis – Failure Analysis
and Analytical Tools”
Course Leaders: Rajen Dias and Deepak Goyal –Intel Corporation

Nolita 3
2.“Multi-Physics Modeling in IC Packaging andMicrosystems”
Course Leader: Xuejun Fan – Lamar University

Nolita 3
10.“Modeling and Simulation of Reliability inElectronic Packaging”
Course Leaders: Craig Hillman and Nathan Blattau –DfR Solutions

Nolita 2
3.“Thermal and Mechanical Simulation
Techniques for 3D Stacking Yield andReliability”
Course Leader: Kamal Karimanal - Cielution LLC

Nolita 2
11.“TSV and Other Enabling Technologies for
3D IC Integration”
Course Leader: John Lau – Industrial Technology
Research InstituteNolita 1
4.“Wafer Level-Chip Scale Packaging (WLCSP)”
Course Leader: Luu Nguyen – Texas Instruments, Inc.

Nolita 1
12.“Chip Package Interaction with TSV
Reliability for 40 nm and Below”
Course Leader: C. S. Premachandran –GlobalFoundries

Mont-Royal 1
5.“Polymers and Nano-Composites forElectronic and Photonic Packaging”
Course Leaders: C.P. Wong – Georgia Tech; Daniel Lu– Henkel Corporation

Mont-Royal 1
13.“Polymers in Electronic Packaging”
Course Leaders: Jeffrey Gotro – InnoCentrix, LLC

Mont-Royal 2
6.“Power Electronics Thermal Packaging andReliability”
Course Leaders:Avram Bar­Cohen and Patrick
McCluskey – University of Maryland

Mont-Royal 2
14.“Flip Chip Packaging”
Course Leader: Eric Perfecto – IBM Corporation

Chelsea 1
7.“Fundamental Concepts, Reliability andMechanics in Electronic Packaging”
Course Leaders: Shubhada Sahasrabudhe and Sandeep
Sane – Intel Corporation

Chelsea 1
15.“Design for Package Reliability”
Course Leaders: Darvin Edwards and Yaoyu Pang –Texas Instruments, Inc.

Chelsea 5
8.“High-Frequency Modeling andOptimization of Interconnections in Electronic
Packaging”
Course Leaders: Ivan Ndip and Michael Toepper –Fraunhofer IZM

Chelsea 5
16.“IC Package Design for Signal/Power
Integrity and Electromagnetic Compatibility”
Course Leader: Sam Karikalan – Broadcom
Corporation

Refreshment Breaks – 10:00 - 10:20 a.m. & 3:00 - 3:20 p.m.
Mont-Royal Commons & Chelsea CommonsContinuing Education Units

ECTC Student Reception
Tuesday, May 28, 2013
5:00 - 6:00 p.m.
Room: Chelsea 2
Host: Eric Perfecto – IBM
Corporation
Students, have you ever wondered how
the ECTC technical committees review
and select papers? Or, just what subjects,
content and paper organization make astandout ECTC paper? Then please cometo the ECTC Student Reception. You’ll
have a chance to enjoy some good foodand meet with representatives of eachtechnical subcommittee. Don’t miss thischance for an inside view of technicalsubcommittee operations. Sponsored by
the IBM Corporation.
General Chair’s Speakers
Reception
Tuesday, May 28, 2013
6:00 - 7:00 p.m.
Room: Blvd Pool North (Outside
Pool Area, 4th floor, facing the Las
Vegas Strip); Rain backup: Chelsea 2
Invited session chairs and speakers arerequested to attend this reception.
Technology Corner Reception
Wednesday, May 29, 2013
5:30 - 6:30 p.m.
Room: Chelsea 3 & 4
All attendees and guests are invited toattend this exhibitor sponsored reception.
Please use this time to mix and mingle withall exhibitors, learn about their products
and services, and pick up a few giveaways.
63rd ECTC Gala Reception
Thursday, May 30, 2013
6:30 p.m.
Room: Chelsea 1 & 5
All badged attendees and guests are invited
to attend our Gala Reception. This isa great way to meet your conferencecolleagues, speakers, exhibitors, guests,
and the ECTC Executive Committee.

The IEEE Components, Packaging and Manufacturing Technology Society (CPMT) has been authorized to offer Continuing Education Units (CEUs) by the International
Association for Continuing Education and Training (IACET) for all Professional Development Courses that will be presented at the 63rd ECTC.
CEUs are recognized by employers for continuing professional development as a formal measure of participation and attendance in “non-credit” self-study courses,
tutorials, symposia and workshops. IEEE CPMT CEUs can be applied towards the “IEEE CPMT Professional Development Certificate.” Complete details, including
voluntary enrollment forms, will be available at the conference. All costs associated with ECTC Professional Development Courses CEUs will be underwritten by theconference, i.e. there are no additional costs for Professional Development Courses attendees to obtain CEU credit.

8

2012 ECTC Paper Awards
Best of Conference Papers

The Electronic Components and Technology Conference is proud
to announce the “Best of Conference” papers selected from the62nd ECTC proceedings. The authors of the Best Session Paper
share a check for US $2,500 and the authors of the Best Poster
Paper share a check for US $1,500. The winning authors also
receive a personalized plaque commemorating their achievement.

Best Session Paper(Session 28, paper 4)
Modeling and Reliability Characterization of Area-Array
Electronics Subjected to High-G Mechanical Shock Up to
50,000G
Pradeep Lall, Kewal Patel, Ryan Lowe, Mark Strickland, Jim Blanche, Dave
Geist, Randall Montgomery – Auburn University

Best Poster Paper(Session 37, paper 17)
Void Formation during Reflow Soldering

Outstanding Papers

The winning authors for Conference Outstanding Session and
Poster Papers receive a personalized plaque commemorating theirachievement and will share a check for US $1,000.

Outstanding Session Paper(Session 24, paper 6)
A 77 GHz SiGe Single-Chip Four-Channel Transceiver
Module with Integrated Antennas in Embedded WaferLevel BGA Package
M. Wojnowski, R. Lachner, J. Böck, G. Sommer, and K. Pressel – Infineon
Technologies AG

Outstanding Poster Paper(Session 37, paper 11)
3D Stacked Microfluidic Cooling forHigh Performance 3D ICs
Yue Zhang, Ashish Dembla, Yogendra Joshi, and Muhannad S. Bakir –Georgia Institute of Technology

Thomas D. Ewald – Robert Bosch GmbH, TU Dresden; Norbert Holle –Robert Bosch GmbH; Klaus-Jürgen Wolter – TU DresdenIntel Best Student Paper

The winning student receives a personalized plaque and a check for $2,500. The following paper was selected based on theIntel Best Student Paper competition conducted at the 62nd ECTC:(Session 34, Paper 4)Interlayer Dielectric Cracking in Back End of Line (BEOL) Stack
Sathyanarayanan Raghavan, Ilko Schmadlak
and Suresh K. Sitaraman – Georgia Institute of Technology

Committee Meetings • Associated Committee Members Only
Tuesday, May 28, 2013

Wednesday, May 29, 2013

Thursday, May 30, 2013

Friday, May 31, 2013

8:00 a.m. – 6:00 p.m.
INEMI Meeting
Condesa 6, 2nd floor

7:00 a.m. – 8:00 a.m.
CPMT Materials & Processes TC
Condesa 1, 2nd floor

7:00 a.m. – 8:00 a.m.
CPMT Photonics TC
Bellavista Boardroom, 2nd floor

7:00 a.m. – 8:00 a.m.
CPMT Nanotechnology TC
Condesa 1, 2nd floor

8:00 a.m. – 5:00 p.m.
ITRS Assemblies & Packaging
Technology Committee
Condesa 2, 2nd floor

7:00 a.m. – 8:00 a.m.
CPMT High-Density Substrates &Boards TC
Condesa 6, 2nd floor

7:00 a.m. – 8:00 a.m.
CPMT RF & THz Technologies TC
Condesa 6, 2nd floor

1:30 p.m. – 4:30 p.m.
ECTC Executive Committee
Jardins Boardroom, 2nd floor

5:00 p.m. – 7:00 p.m.
CPMT Region 8 Advisory Committee
Condesa 1, 2nd floor
9:00 p.m. – 10:30 p.m.
ECTC OPTO Committee
Yaletown 4, 4th floor

4:30 p.m. – 5:30 p.m.
CPMT Technical Committee Chairs
Condesa 6, 2nd floor
6:00 p.m. – 7:00 p.m.
Program Subcommittee Chairs &Assistant Chairs Reception
General Chair’s Suite(by invitation only)
6:30 p.m. – 7:30 p.m.
ECTC Interconnection Committee
Condesa 6, 2nd floor

7:00 a.m. – 8:00 a.m.
CPMT Thermal & Mechanical TC
Condesa 5, 2nd floor
5:30 p.m. – 6:30 p.m.
ECTC 2014 Program Committee
Meeting
Nolita 1, 4th floor
8:00 p.m.
ECTC Governing/Executive Committee
Reception
General Chair’s Suite

9

Program Sessions: Wednesday, May 29, 8:00 a.m. - 11:40 a.m.
Session 1:
3D Assembly and Reliability

Session 2:
3D Materials and Processing

Session 3:
Novel Interconnections

Committee:
Advanced Packaging

Committee:
Materials & Processing

Committee:
Interconnections

Mont-Royal 1

Mont-Royal 2

Nolita 1

Session Co-Chairs:
John Knickerbocker – IBM Corporation
Sam Karikalan – Broadcom Corporation

Session Co-Chairs:
Mikel Miller – Draper Laboratory
Bing Dang – IBM Corporation

Session Co-Chairs:
James E. Morris – Portland State University
Lei Shan – IBM Corporation

1.

1.

1.

8:00 a.m. – Reliability Studies on MicroBumps for 3D TSV Integration
Ho-Young Son, Sung-Kwon Noh, Hyun-Hee Jung,
Woong-Sun Lee, Jae-Sung Oh, and Nam-Seog Kim – SK
Hynix Inc.

2.

8:25 a.m. – Reliability Evaluation of a
CoWoS-Enabled 3D IC Package

Dong Wook Kim, Ramachandran Vidhya, Brian
Henderson, Urmi Ray, Sam Gu,Wei Zhao, Riko Radojcic,
and Matt Nowak – Qualcomm Technologies, Inc.;
Changmin Lee, Jongsik Paek, Kiwook Lee, and Ron
Huemoeller – Amkor Technology, Inc.

2.

Bahareh Banijamali, Suresh Ramalingam, and Liam
Madden – Xilinx, Inc.; Chien-Chia Chiu, Cheng-Chieh
Hsieh,Tsung-Shu Lin, Clark Hu, Shang-Yun Hou, ShinPuu Jeng, and Doug C.H.Yu – Taiwan Semiconductor
Manufacturing Company, Ltd.

3.

8:50 a.m. – TSV and Cu-Cu Direct Bond Wafer
and Package-Level Reliability

8:00 a.m. – Development of 3D ThroughSilicon Stack (TSS) Assembly for Wide IO
Memory to Logic Devices Integration

8:25 a.m. – Investigation on the Properties
and Processability of Polymeric Insulation
Layers for Through Silicon Via

Kyoung-Lim Suk and Kyung-Wook Paik – KAIST

2.

Songfang Zhao, Guoping Zhang, Chongnan Peng, andRong Sun – Chinese Academy of Sciences; S.W. Ricky
Lee – HKUST;Wenhui Zhu and Fangqi Lai – Kunshan Q
Technology Ltd.

3.

K. Hummler, B. Sapp, and I.Ali – SEMATECH; J.R. Lloyd– SUNY,Albany; S. Kruger and S. Olson – SEMATECH;
SUNY,Albany; S.B. Park, B. Murray, D. Jung, S. Cain,A. Park,and D. Ferrone – SUNY, Binghamton

8:50 a.m. – Process Integration of 3D SiInterposer with Double-Sided Active Chip
Attachments

8:00 a.m. – Effects of Nanofiber Materials of
Nanofiber Anisotropic Conductive Adhesives(Nanofiber ACAs) for Ultra-Fine Pitch
Electronic Assemblies

8:25 a.m. – A Novel Non-TSV Approach to
Enhancing the Bandwidth in 3-D Packages
for Processor-Memory Modules
Dev Gupta – APSTL

3.

P. J.Tzeng, J. Lau, C.J. Zhan,Y.C. Hsin, P.C. Chang,Y.H.
Chang, J.C. Chen, S.C. Chen, C.Y.Wu, C.K. Lee, H.H.
Chang, C.H. Chien, C.H. Lin,T.K. Ku, M.J. Kao – Industrial
Technology Research Inst. (ITRI); M. Li, J. Cline, K. Saito,
M. Ji – Rambus, Inc.

8:50 a.m. – Three-Path Electroplated Copper
Compliant Interconnects – Fabrication andModeling Studies
Raphael Okereke and Suresh K. Sitaraman – Georgia
Institute of Technology

Refreshment Break: 9:15 a.m. – 10:00 a.m. (Chelsea 3 & 4)
4.

10:00 a.m. – Generic Rules to Achieve Bump
Electromigration Immortality for 3D IC
Integration

4.

Hsiao-Yun Chen, Da-Yuan Shih, Cheng-Chang Wei,
Chih-Hang Tung,Yi-Li Hsiao, and Douglas Cheng-Hua
Yu – Taiwan Semiconductor Manufacturing Company;
Yu-Chun Liang and Chih Chen – National Chiao Tung
University

5.

10:25 a.m. – 3D Integration Technologies
Using Self-Assembly and Electrostatic
Temporary Multichip Bonding

10:50 a.m. – Electrical Investigation and Reliabilityof 3D Integration Platform Using CuTSVs andMicro-Bumps with Cu/Sn-BCB Hybrid Bonding5.

11:15 a.m. – Assembly of 3D Chip Stack with
30um-Pitch Micro Interconnects Using Novel
Arrayed-Particles Anisotropic Conductive
Film
Y.W. Huang,Y.M. Lin, C.J. Zhan, S.T. Lu, S.Y. Huang, J.Y.
Juang, C.W. Fan, S.C. Chung, J.S. Peng, S.M. Chen,Y.L. Lu,
J.H. Lau, and P.C. Chang – Industrial Technology ResearchInstitute (ITRI)

10

10:25 a.m. – WSS and ZoneBOND Temporary
Bonding Techniques Comparison for 80µm
and 55µm Functional Interposer Creation

6.

10:50 a.m. – Low Cost, Room Temperature
Debondable Spin-On Temporary Bonding
Solution: A Key Enabler for 2.5D/3D IC
Packaging5.

11:15 a.m. – Integration and Manufacturing
Aspects of Moving from WaferBOND HT-10.10
to ZoneBOND Material in Temporary Wafer
Bonding and Debonding for 3D Applications
Anne Jourdain,Alain Phommahaxay, Greet Verbinnen,
Gayle Murdoch,Andy Miller, Kenneth Rebibis, Gerald
Beyer, and Eric Beyne – IMEC;Alice Guerrero, Jeremy
Mc Cutcheon, Mark Privett, and Jason Neidrich –Brewer Science, Inc.

10:25 a.m. – A Highly Integratable MillimeterWave Silicon Waveguide Array for Terabit
Application
Qidong Wang, Daniel Guidotti, Jie Cui, Liqiang Cao,
Tianchun Ye, and Lixi Wan – Chinese Academy of
Sciences

6.

10:50 a.m. – Aluminum to Aluminum Bondingat Room Temperature
F. Marion, B. Goubault de Brugière,A. Bedoin, M.Volpert,
F. Berger,A. Gueugnot, R.Anciant, and H. Ribot – CEALETI

Ranjith S.E. John, Herman Meynen, Sheng Wang, PengFei Fu, Craig Yeakle, Sang Wook W. Kim, and Lyndon J.
Larson – Dow Corning Corporation; Scott Sullivan –Suss MicroTec

7.

10:00 a.m. – Ultra-Fine Trench Circuit on
Polymer Film
Takaharu Hondo,Yosuke Nitta, Kei Nakamura, Hiroyuki
Hirano, Masanobu Saruta,Toshiaki Inoue, and Osamu
Nakao – Fujikura, Ltd.

A. Jouve, K.Vial, E. Rolland, C. Laviron, M. Fournel, M.
Pellat, P. Montmeat, N.Allouti, and R. Eleouet – CEALETI; P. Coudrain and C.Aumont – STMicroelectronics

Yao Jen Chang, C.H. Chiang,T.H.Yu, C.H. Fan, and K.N.
Chen – National Chiao Tung University; C.T. Ko –National Chiao Tung University, Industrial Technology
Research Institute (ITRI); Z.C. Hsiao, H.C. Fu, and W.C.
Lo – Industrial Technology Research

7.

4.

J.A. Sharpe, M.B. Jordan, S.L. Burkett, and M.E. Barkey –University of Alabama

T. Fukushima, H. Hashiguchi, J. Bea, M. Murugesan, K.W.
Lee,T.Tanaka, and M. Koyanagi – Tohoku University

6.

10:00 a.m. – Analyzing the Behavior andShear Strength of Common Adhesives Used in
Temporary Wafer Bonding

7.

11:15 a.m. – Carbon Nanotube Array as High
Impedance Interconnects for Sensing Device
Integration
Dunlin Tan and Dominique Baillargeat – CINTRA; Chin
Chong Yap and Beng Kang Tay – Nanyang Technological
University; David Hee, Jong Jen Yu, Jean-Luc Reverchon,and Philippe Bois – Thales

Program Sessions: Wednesday, May 29, 8:00 a.m. - 11:40 a.m.
Session 4:
Reliability Test Methods

Session 5:
New Directions in Packaging

Session 6:
Optical Interconnects

Committee:
Applied Reliability

Committee:
Emerging Technologies

Committee:
Optoelectronics

Nolita 2

Nolita 3

Yaletown 4

Session Co-Chairs:
John H. L. Pang – Nanyang Technological University
Deepak Goyal – Intel Corporation

Session Co-Chairs:
Vasudeva P. Atluri – Renavitas Technologies
Joana Maria – IBM Corporation

Session Co-Chairs:
Alex Rosiewicz – Gooch & Housego
Ping Zhou – LDX Optronics, Inc.

1.

1.

1.

8:00 a.m. – Define Electrical Packing
Temperature Cycling Requirement with Field
Measured User Behavior Data
Min Pei, Ru Han, Daeil Kwon,Alan Lucero,Vasu
Vasudevan, Robert Kwasnick, and Praveen S. Polasam –Intel Corporation2.

8:25 a.m. – Characterization of Aging
Effects in Lead-Free Solder Joints using
Nanoindentation

Chaoqi Zhang – Georgia Institute of Technology; Hiren
D.Thacker, Ivan Shubin,Ashok V. Krishnamoorthy, James
G. Mitchell, and John E. Cunningham – Oracle Labs

2.

Jeffrey C. Suhling, Mohammad Hasnine, Muhannad
Mustafa, Barton C. Prorok, Michael J. Bozack, andPradeep Lall – Auburn University

3.

8:50 a.m. – Effects of Reliability Testing
Methods on Microstructure and Strength at
the Cu Wire-Al Pad Interface

8:00 a.m. – Large-Scale, Surface Tension
Assisted Ball-in-Pit Self Population for Chipto-Chip Passive Alignment

8:25 a.m. – Through-Silicon-Via Process
Control in Manufacturing for SiGe Power
Amplifiers

Lars Brusberg, Henning Schröder, and Julia Röder– Fraunhofer IZM; Richard Pitwon and Allen Miller– Xyratex Technology Ltd.; Simon Whalley – ILFA
Feinstleitertechnik GmbH; Christian Herbst, Marcel
Neitz, and Klaus-Dieter Lang – TU Berlin

2.

P. Su – Cisco Systems, Inc.; H. Seki, C. Ping, and S. Itoh –Sumitomo Bakelite; L. Huang, N. Liao, B. Liu, C. Chen,W.
Tai, and A.Tseng – Advanced Semiconductor EngineeringGroup

8:50 a.m. – High Frequency Scanning Acoustic
Microscopy Applied to 3D Integrated Process:
Void Detection in Through Silicon Vias

8:25 a.m. – Single-Chip 4 TX + 4 RX Optical
Module Based on Holey SiGe Transceiver IC
Fuad E. Doany, Daniel M. Kuchta,Alexander V. Rylyakov,
Christian W. Baks, Frank Libsch, and Clint L. Schow –IBM Corporation

J.P. Gambino,T. Doan, J.Trapasso, C. Musante, D. Dang,and D.Vanslette – IBM Corporation; D. Grant, D. Marx,and R. Dudley – Tamar Technology

3.

8:00 a.m. – Optical Backplane for Boardto-Board Interconnection Based on a Glass
Panel Gradient-Index Multimode WaveguideTechnology

3.

A. Phommahaxay, H. Philipsen,Y. Civale, K.Vandermissen,
S. Halder, G. Beyer, B. Swinnen, E. Beyne, and A. Miller– IMEC; I. De Wolf – IMEC, KU Leuven; P. Hoffrogge, S.
Brand, and P. Czurratis – PVA TePla Analytical Systems
GmbH

8:50 a.m. – FPC-Based Compact 25Gb/s Optical Transceiver Module for Optical
Interconnect Utilizing Novel High-Speed FPC
Connector
Takatoshi Yagisawa,Takashi Shiraishi,Tadashi Ikeuchi, andKazuhiro Tanaka – Fujitsu Laboratories Ltd.

Refreshment Break: 9:15 a.m. – 10:00 a.m. (Chelsea 3 & 4)
4.

10:00 a.m. – Use of RF-Based Technique as a
Metrology Tool for TSV Reliability Analysis

4.

Chukwudi Okoro, Pavel Kabos, Jan Obrzut, and Yaw S.
Obeng – NIST; Klaus Hummler – SEMATECH

5.

10:25 a.m. – On the Use of High Precision
Electrical Resistance Measurement for
Analyzing the Damage Development
During Accelerated Test of Pb-Free Solder
Interconnects

10:00 a.m. – Self-Alignment Structures for
Heterogeneous 3D Integration

4.

Hyung Suk Yang, Chaoqi Zhang, and Muhannad Bakir –Georgia Institute of Technology

5.

10:25 a.m. – Optimization of Wire-Rod
Electrostatic Fluid Accelerators

Yoichi Taira and Hidetoshi Numata – IBM Corporation

5.

Tsrong-Yi Wen,Tsan-Ting Shen, Hsiu-Che Wang, andAlexander Mamishev – University of Washington

10:50 a.m. – Unique Adhesion Testing and
MSL Modeling6.

11:15 a.m. – Acoustic Emission Detection of
BGA Components in Spherical Bend
W. Carter Ralph, Gregory L.. Daspit,Andrew W. Cain,and Randall S. Jenkins – Southern Research Institute;
Elizabeth F. Benedetto,Aileen M.Allen, and Keith
Newman – Hewlett Packard

6.

M. Balucani – Sapienza University of Rome, Rise
Technology; D. Ciarniello – Rise Technology; P. Nenzi, R.
Crescenzi, and K. Kholostov – Sapienza University ofRome; D. Bernardi – 2BG

Masazumi Amagai and Kentaro Takao – Texas
Instruments

7.

10:50 a.m. – New Selective Wet Processing

7.

11:15 a.m. – Microscrubbing: An Alternative
Method for 3D Thermocompression
Bonding CuCu Bumps and High Bump
Density Devices with Low Force,Time, andTemperature
Robert Daily,Wang Teng, Giovanni Capuz, and Andy
Miller – IMEC

10:25 a.m. – Modeling, Design, andFabrication of Ultra-High Bandwidth 3D
Glass Photonics (3DGP) in Glass Interposers
Bruce C. Chou,Vijay Sukumaran,Venky Sundaram, GeeKung Chang, and Rao Tummala – Georgia Institute ofTechnology;Yoichiro Sato – Asahi Glass Company; Jibin
Sun – TE Connectivity

J. Zhang, S. van der Zwaag, and H.W. Zeijl – Delft
University of Technology; G.Q. Zhang – Delft Universityof Technology, Philips Lighting

6.

10:00 a.m. – Optical Packaging of Silicon
Photonic Devices for External Connection of
Parallel Optical Signals

10:50 a.m. – Assembly Development of 1.3
Tb/s Full Duplex Optical Module
Yehoshua Benjamin, Kobi Hasharoni, and Michael Mesh –Compass Electro Optical Systems

7.

11:15 a.m. – Low-Loss Design and Fabricationof Multimode Polymer Optical WaveguideCircuit with Crossings for High-Density
Optical PCB
Takaaki Ishigure, Keishiro Shitanda, and Takuya Kudo –Keio University; Shotaro Takayama,Tetsuya Mori, Kimio
Moriya, and Koji Choki – Sumitomo Bakelite Co., Ltd.

11

Program Sessions: Wednesday, May 29, 1:30 p.m. - 5:10 p.m.
Session 7:
Interposers

Session 8:
3D Reliability and Packaging Challenges

Session 9:
Advanced Flip Chip Technologies

Committee:
Advanced Packaging

Committee:
Applied Reliability

Committee:
Interconnections

Mont-Royal 1

Mont-Royal 2

Nolita 1

Session Co-Chairs:
Subhash L. Shinde – Sandia National Laboratory
Peter Ramm – Fraunhofer EMFT

Session Co-Chairs:
Toni Mattila – Aalto University
Jeffrey Suhling – Auburn University

Session Co-Chairs:
Lou Nicholls – Amkor Technology, Inc.
William Chen – Advanced Semiconductor Engineering, Inc.

1.

1.

1.

1:30 p.m. – Full Integration of a 3D
Demonstrator with TSV First Interposer, Ultra
Thin Die Stacking, and Wafer Level Packaging
G. Parès, G. Simon – CEA-LETI; C. Karoui,A. Zaid, F.
Dosseul, M. Feron – STMicroelectronics;A.Attard – BESI
Austria; G. Klug – DISCO HiTec Europe; H. Luesebrink– PVA TePla AG; K. Martinschitz – EV Group; N. Launay –SPTS; S. Belhenini – LMR

2.

1:55 p.m. – Fabrication and Testing of Thin
Silicon Interposers with Multilevel Frontside
and Backside Metallization and Cu-Filled
TSVs

2.

2:20 p.m. – Interposer Technology for High
Bandwidth Interconnect Applications

1:55 p.m. – Impacts of Static and Dynamic
Local Bending of Thinned Si Chip on
MOSFET Performance in 3-D Stacked LSI

2.

H. Kino, J.C. Bea, M. Murugesan, K.W. Lee,T. Fukushima,
M. Koyanagi, and T.Tanaka – Tohoku University

3.

Mikael Detalle,A. La Manna, J. De Vos, P. Nolmans, R.
Daily,Y. Civale, G. Beyer, and E. Beyne – IMEC

2:20 p.m. – Reliability Characterization of
Chip-on-Wafer-on-Substrate (CoWoS) 3D IC
Integration Technology

1:30 p.m. – Challenges of Chip-to-Package
Interaction for 22nm Technology with Ultra
Low k and Pb-Free Interconnects
Chris Muzzy, Richard Bisson, John Cincotta, Danielle
Degraw, Edward Engbrecht, Jason Gill, Naftali Lustig,
Karen McLaughlin, Sylvain Ouimet, Joseph Ross, andDavid Turnbull – IBM Corporation

Kaya Demir, Koushik Ramachandran, Qiao Chen,Vijay
Sukumaran, Raghu Pucha,Venkatesh Sundaram, and Rao
Tummala – Georgia Institute of Technology;Yoichiro Sato
– Asahi Glass Co., Ltd.

D. Malta, M. Lueck,A. Huffman, C. Gregory, M. Butler, J.
Lannon, and D.S.Temple – RTI International

3.

1:30 p.m. – Thermomechanical andElectrochemical Reliability of Fine-Pitch
Through-Package-Copper Vias (TPV) in Thin
Glass Interposers and Packages

1:55 p.m. – Ultra-Thin and Ultra-High I/O
Density Package-on-Package (3D Thin PoP)
for High Bandwidth of Smart Systems
Sung Jin Kim, Chinmay Honrao, P. Markondeya Raj,Venky
Sundaram, and Rao Tummala – Georgia Institute ofTechnology

3.

2:20 p.m. – A PoP Structure to Support I/Oover 1000
Dyi-Chung Hu, Chun-Ting Lin, and Ying-Chih Chan –Unimicron Technology Corporation

Larry Lin,Tung-Chin Yeh, Jyun-Lin Wu, Gary Lu,Tsung-Fu
Tsai, Larry Chen, and An-Tai Xu – Taiwan Semiconductor
Manufacturing Company, Ltd.

Refreshment Break: 2:45 p.m. - 3:30 p.m. (Chelsea 3 & 4)
4.

3:30 p.m. – Package Demonstration of theInterposer with Integrated TSVs and Flexible
Compliant Interconnects

4.

Ivan Shubin,Alex Chow, Hiren Thacker, Kannan Raj,
Ashok Krishnamoorthy, James Mitchell, and John
Cunningham – Oracle; Eugene Chow and Dirk
DeBruyker – Palo Alto Research Center (PARC); Koji
Fujimoto – Dai Nippon Printing Co., Ltd.

5.

3:55 p.m. – Electrical and Morphological
Characterization for High Integrated Silicon
Interposer and Technology Transfer from200mm to 300mm Wafer

4:20 p.m. – Demonstration of Low Cost, High
Performance, and High Reliability of 2.5D
Polycrystalline Silicon Interposer with Fine
Pitch Through Vias, Redistribution Layers, andCu Microbump Interconnections

5.

4:45 p.m. – Development of Through Glass
Via (TGV) Formation Technology Using
Electrical Discharging for 2.5D/3D Integrated
Packaging
Shintaro Takahashi, Kohei Horiuchi, Kentaro Tatsukoshi,
Motoshi Ono, and Nobuhiko Imajo – Asahi Glass
Company, Ltd.;Tim Mobely – nMode Solutions, Inc.

12

3:55 p.m. – Reliability Study for Large Silicon
Interposers Report on Board

3:30 p.m. – Investigation of Novel Solder
Patterns for Power Delivery and Heat
Removal Support
Thomas Brunschwiler,Timo Tick, Gerd Schlottig, andStefano Oggioni – IBM Corporation;Yassir Madhour –IBM Corporation, Swiss Institute of Technology

5.

C. Ferrandon,Y. Lamy, F. De Crecy, and G. Simon – CEALETI; S. Joblot, P. Coudrain, P. Bar, D.Yap, R. Coffy, and J.F.
Carpentier – STMicroelectronics

3:55 p.m. – Modified Thermosonic FlipChip Bonding Based on Electroplated
Cu Microbumps and Concave Pads forHigh-Precision Low-Temperature Assembly
Applications
Thanh-Tung Bui, Motohiro Suzuki, Fumiki Kato, Naoya
Watanabe, Shunsuke Nemoto, Katsuya Kikuchi, andMasahiro Aoyagi – National Institute of AIST

6.

4:20 p.m. – Fracture Mechanics Lifetime
Modeling of Low Temperature Si Fusion
Bonded Interfaces Used for 3D MEMS
Device Integration

6.

4:20 p.m. – 10um Ag Flip-Chip by Solid-State
Bonding at 250ºC
Wen P. Lin and Chin C. Lee – University of California,
IrvineFalk Naumann, Michael Bernasch, and Matthias Petzold– Fraunhofer IWM; Joerg Siegert and Sara Camiello –ams AG

Venky Sundaram, Qiao Chen,Tao Wang, Hao Lu,Yuya
Suzuki, Raj Pulugurtha, and Rao Tummala – Georgia
Institute of Technology

7.

4.

B.Wunderle, Jens Heilmann, and Sridhar Ganesh Kumar– TU Chemnitz; Ole Hoelck – TU Chemnitz, Fraunhofer
IZM; Hans Walter, Olaf Wittler, Gunter Engelmann, andM. Jürgen Wolf – Fraunhofer IZM; Gottfried Beer andKlaus Pressel – Infineon Technologies AG

M. Sunohara, K. Miyairi, K. Mori, M. Higashi, and K.
Murayama – Shinko Electric Industries Co., Ltd.; J.
Charbonnier, M.Assous, J.P. Bally,T. Mourier, S. Minoret, D.
Mercier,A.Toffoli, E. Martinez, H. Feldis, G. Simon, and F.
Allain – CEA-LETI

6.

3:30 p.m. – Accelerated Reliability Testing andModeling of Cu-Plated Through Encapsulant
Vias (TEVs) for 3D-Integration

7.

4:45 p.m. – Extension of Micro-Raman
Spectroscopy for Full-Component StressCharacterization of TSV Structures
Qiu Zhao, J. Im, R. Huang, and P.S. Ho – University ofTexas,Austin

7.

4:45 p.m. – Transient Liquid Phase Sintered
Attach for Power Electronics
Hannes Greve and F. Patrick McCluskey – University of
Maryland; Liang-Yu Chen – Ohio Aerospace Institute; Ian
Fox – Aero Engine Controls

Program Sessions: Wednesday, May 29, 1:30 p.m. - 5:10 p.m.
Session 10: Advancements
in Manufacturing Technology

Session 11:
Biomedical Electronics

Session 12:
High Brightness LEDs and Material

Committee:
Assembly & Manufacturing Technology

Committee:
Emerging Technologies

Committee:
Optoelectronics

Nolita 2

Nolita 3

Yaletown 4

Session Co-Chairs:
Shawn Shi – Medtronic Corporation
Sharad Bhatt – Shanta Systems, Inc.

Session Co-Chairs:
C. S. Premachandran – GLOBALFOUNDRIES
Karlheinz Bock – Fraunhofer EMFT

Session Co-Chairs:
Henning Schroeder – Fraunhofer IZM
Stefan Weiss – Oclaro Switzerland GmbH

1.

1.

1.

1:30 p.m. – Strip Warpage Analysis of a
Flip Chip Package Considering the Mold
Compound Processing Parameters

Paolo Nenzi,Agnese Denzi, Konstantin Kholostov,Rocco Crescenzi, Francesca Apollonio, Micaela Liberti,
Paolo Marracino, Ruggero Cadossi, and Marco Balucani– University of Rome;Alessia Ongaro – University of
FerraraEric Ouyang and MyoungSu Chae – STATS ChipPAC,
Ltd.

2.

1:55 p.m. – Thermoplastic Based System-inPackage for RFID Application

2.

Christine Kallmayer, Barbara Pahl, and Arian Grams –Fraunhofer IZM; Joao Marques and Klaus-Dieter Lang –TU Berlin;Thomas Suwald – NXP Semiconductors

3.

2:20 p.m. – 3D Printing of Structures with
Embedded Circuit Boards Using Novel
Holographic Optics

1:30 p.m. – Smart Flexible Planar Electrodes
for Electrochemotherapy and Biosensing

1:55 p.m. – Flexible,Transparent Electronics
for Biomedical Applications

Marc Schneider, Benjamin Leyrer, Christian Herbold, andStefan Maikowske – Karlsruhe Institute of Technology

2.

Michael Klopfer, G.P. Li, and Mark Bachman – Universityof California, Irvine; Chris Cordonier, Koutoku Inoue,and Hideo Honma – Kanto Gakuin University

3.

2:20 p.m. – Epidermal Electronics for
Seamless Monitoring of Biopotential Signals

1:55 p.m. – LED Matrix Light Source for
Adaptive Driving Beam Applications
Gordon Elger, Benno Spinger, Nico Bienen, and Nils
Benter – Philips Technology GmbH3.

Mitul Dalal, Conor Rafferty,Yung-Yu Hsu, Henry Wei,
Kevin Dowling, Briana Morey, Greg Levesque, Gil
Huppert, Brian Elolampi, and Dan Davis – mc10, Inc.

Shuai Hou and John Tyrer – Loughborough University

1:30 p.m. – Very High Power Density LED
Modules on Aluminum Substrates with
Embedded Water Cooling

2:20 p.m. – Substrate Reflectivity Study forHigh Brightness LED Package
Chieh-Lung Lai, Song-Chun Wu, Jui-Feng Lai, and HsienWen Chen – Siliconware Precision Industries Co., Ltd.

Refreshment Break: 2:45 p.m. - 3:30 p.m. (Chelsea 3 & 4)
4.

3:30 p.m. – Low Temperature Fine Pitch Flexon-Flex (FOF) Assembly Using Nanofiber
Sn58Bi Solder Anisotropic Conductive Films(ACFs) and Ultrasonic Bonding Method

4.

3:55 p.m. – Effective Voiding Control of QFN
Via Solder Mask Patterning

5.

Derrick Herron,Yan Liu, and Ning-Cheng Lee – Indium
Corporation

6.

4:20 p.m. – Warpage Analysis andImprovement for a Power Module

4:45 p.m. – Solder Joint Properties of Sn-AgCu Solders on Environmental-Friendly Plasma
Surface Finish
Sang-Hyun Kwon, Kyoung-Ho Kim,Won-Il Seo, ChangWoo Lee, and Sehoon Yoo – Korea Institute of Industrial
Technology (KITECH); Nam-Sun Park – Jesagi HankookLtd.;Young-Bae Park – Andong National University

3:55 p.m. – 3-Axis MEMS AccelerometerBased Implantable Heart Monitoring Systemwith Novel Fixation Method

6.

4:20 p.m. – 3D IPAC – A New Passives andActives Concept for Ultra-MiniaturizedElectronic and Bioelectronic Functional
Modules

5.

4:45 p.m. – Anti-Counterfeit, Miniaturized,
and Advanced Electronic Substrates for
Medical Device Applications
Rabindra N. Das, Frank D. Egitto, and How Lin –Endicott Interconnect Technologies, Inc.

3:55 p.m. – High Refractive Index andTransparency Nanocomposites as
Encapsulant for High Brightness LED
Packaging
Yan Liu, Ziyin Lin, Xueying Zhao, and Kyoung-Sik Moon
– Georgia Institute of Technology; Sehoon Yoo – Korea
Institute of Industrial Technology; J. Choi – EI Lighting
Co.; C.P.Wong – Georgia Institute of Technology,
Chinese University of Hong Kong

6.

4:20 p.m. – Realization of High-Quality Light
Output Based on a Novel LED Packaging
Shuiming Li, Fei Chen,Yi Sun, Bin Cao, and Sheng Liu –Huazhong University of Science & Technology; Kai Wang
– Guangdong Real Faith Opto-Electronic Co., Ltd.

P. Markondeya Raj, Uei-Ming Jow, K.P. Murali, Himani Sharma,
Dibyajat Mishra, Saumya Gandhi, Maysam Ghovanloo, and
Rao Tummala – Georgia Institute of Technology; Jinxiang Dai
and T. Danny Xiao – Inframat Corporation

7.

3:30 p.m. – Evaluation of Directed SelfAssembly Process for LED Assembly on
Flexible Substrates
Anton Tkachenko, Robert F. Karlicek, Jr., and James J.Q.
Lu – Rensselaer Polytechnic InstituteFjodors Tjulkins,Anh Tuan Thai Nguyen, Nils Hoivik, Knut
E.Aasmundtveit, Erik Andreassen, Lars Hoff, and Kristin
Imenes – Vestfold University College

Yong Liu,Yumin Liu, Zhongfa Yuan,Tyler Chen, Keunhyuk
Lee, and Suresh Belani – Fairchild Semiconductor
Corporation

7.

4.

Erik Jung, Martin Blechert,Victoria Schuldt, and Moritz
Hubl – Fraunhofer IZM; Leopold Georg and KlausDieter Lang – TU Berlin

Tae Wan Kim, Kyoung-Lim Suk, and Kyung-Wook Paik
– KAIST5.

3:30 p.m. – Sensor Integrated Microfluidics
for Compact Micro-Reactors

7.

4:45 p.m. – Quasi-Conformal Phosphor
Dispensing on LED for White Light
Illumination
S.W. Ricky Lee, Xungao Guo, Daoyuan Niu, andJeffery C.C. Lo – Hong Kong University of Science &Technology

13

Program Sessions: Thursday, May 30, 8:00 a.m. - 11:40 a.m.
Session 13:
3D Processing and Technology

Session 14:
3D TSV Interconnects Reliability

Session 15: Enabling Technologies
for Flip Chip AssemblyCommittee:
Advanced Packaging

Committees: Interconnections / Applied
Reliability

Committee:
Assembly & Manufacturing Technology

Mont-Royal 1

Mont-Royal 2

Nolita 1

Session Co-Chairs:
Christopher Bower – Semprius, Inc.
Erik Jung – Fraunhofer IZM

Session Co-Chairs:
Akitsu Shigetou – National Institute for Materials Science
Scott Savage – Medtronic Microelectronics Center

Session Co-Chairs:
Valerie Oberson – IBM Corporation
Tom Poulin – Aerie Engineering

1.

1.

1.

8:00 a.m. – TSV Last for Hybrid Pixel
Detectors: Application to Particle Physics andImaging Experiments
D. Henry,A. Berthelot, R. Cuchet, and C. Chantre – CEALETI; J.Alozy and M. Campbell – CERN

2.

8:25 a.m. – Dielectric Stack Engineering for
Via-Reveal Passivation

Pradeep Lall, Kewal Patel, and Vikalp Narayan – Auburn
University

2.

Kath Crook, Mark Carruthers, Daniel Archard, Steve
Burgess, and Keith Buchanan – SPTS Technologies

3.

8:50 a.m. – Low-Cost Micrometer-Scale
Silicon Vias (SVs) Fabrication by MetalAssisted Chemical Etching (MaCE) and
Carbon Nanotubes (CNTs) Filling

8:00 a.m. – Model for Prediction of Packageon-Package Warpage and the Effect ofProcess and Material Parameters

8:25 a.m. – Design for Reliability of MultiLayer Thin Film Stretchable Interconnects

Sudarshan Rangaraj, Jeffrey Hicks, Michael O’Day,Ankur
Aggarwal,Terri Wilson, Ramanarayanan Panchapakesan,
Rohit Grover, and Guotao Wang – Intel Corporation

2.

Yung-Yu Hsu, Kylie Lucas, Dan Davis, Rooz Ghaffari,
Brian Elolampi, Mitul Dalal, John Work, Stephen Lee,
Conor Rafferty, and Kevin Dowling – mc10, Inc.

3.

8:50 a.m. – A More Practical Methodof Predicting Flip Chip Solder Bump
Electromigration Reliability

8:25 a.m. – Flip Chip Assembly Method
Employing Differential Heating/Cooling forLarge Dies with Coreless Substrates
Katsuyuki Sakuma, Edmund Blackshear, Krishna Tunga,
Chenzhou Lian, Shidong Li, Marcus Interrante, Oswald
Mantilla, and Jae-Woong Nah – IBM Corporation

3.

Shiguo (Richard) Rao – Vitesse Semiconductor
Corporation

Liyi Li,Yagang Yao, Ziyin Lin, and Yan Liu – Georgia
Institute of Technology; C.P.Wong – Georgia Institute ofTechnology, Chinese University of Hong Kong

8:00 a.m. – Low-k ILD Reliability throughChip-Package Assembly: Engineering
Appropriate Stress Tests and Process
Certification Criteria

8:50 a.m. – 3D Integration of CMOS Image
Sensor with Co-Processor Using TSV Last andMicro-Bumps Technologies
P. Coudrain, N. Chevrier,A. Farcy, O. Le-Briz –STMicroelectronics; D. Henry,A. Berthelot, J.
Charbonnier, S.Verrun, R. Franiatte, N. Bouzaida, G.
Cibrario – CEA-LETI; F. Calmon, I. O’Connor – INL;
T. Lacrevaz, B. Flechet, L. Fourneaud – Univ. de Savoie

Refreshment Break: 9:15 a.m. – 10:00 a.m. (Chelsea 3 & 4)
4.

10:00 a.m. – Impact of Post-Plating Anneal
and Through-Silicon Via Dimensions on Cu
Pumping

4.

Joke De Messemaeker, Olalla Varela Pedreira, Bart
Vandevelde, Harold Philipsen, Ingrid De Wolf, Eric Beyne,
and Kristof Croes – IMEC

5.

10:25 a.m. – A Quick-Turn 3D Structured
ASIC Platform for Cost-Sensitive Applications

10:50 a.m. – TSV-Based Quartz Crystal
Resonator Using 3D Integration and Si
Packaging Technologies

5.

11:15 a.m. – Total Cost Effective Scallop Free
Si Etching for 2.5D & 3D TSV Fabrication
Technologies in 300mm Wafer
Yasuhiro Morikawa,Takahide Murayama,Yuu Nakamuta,
Toshiyuki Sakuishi,Akiyoshi Suzuki, and Koukou Suu –ULVAC, Inc.

14

10:25 a.m. – Characterization of Plasticity
and Stresses in TSV Structures in Stacked Dies
using Synchrotron X-Ray Microdiffraction

6.

10:50 a.m. – X-Ray Micro-Beam Diffraction
Determination of Full-Stress Tensors in Cu
TSVs

5.

11:15 a.m. – Effect of Metal Finishing
Fabricated by Electro and Electroless Plating
Process on Reliability Performance of 30umPitch Solder Micro Bump Interconnection
J.Y. Juang, S.Y. Huang, C.J. Zhan,Y.M. Lin,Y.W. Huang, C.W.
Fan, S.C. Chung, S.M. Chen, J.S. Peng,Y.L. Lu, P.C. Chang,
J.H. Lau, and M.L.Wu – Industrial Technology ResearchInstitute (ITRI)

10:25 a.m. – No Clean Flux Technology forLarge Die Flip Chip Packages
Akihiro Horibe, Kang-Wook Lee, Keishi Okamoto,
Hiroyuki Mori, and Yasumitsu Orii – IBM Corporation;
Yuki Nishizako, Osamu Suzuki, and Yukio Shirai –NAMICS Corporation

6.

Chukwudi Okoro, Lyle E. Levine, Oleg Kirillov, and Yaw
S. Obeng – NIST; Ruqing Xu, Jonathan Z.Tischler, andWenjun Liu – Argonne National Laboratory; Klaus
Hummler – SEMATECH

7.

10:00 a.m. – Methodology to Evaluate PreApplied Underfill Materials with Concurrent
Flux Capability for Ultra-Fine Pitch SolderBased Interconnects
Sunoo Kim, Seth Kruger, Brian Sapp, and Sitaram
Arkalgud – SEMATECH; Ho Hyung Lee and Seungbae
Park – SUNY Binghamton

T. Jiang, C.L.Wu, J. Im, P.S. Ho, and R. Huang – Universityof Texas,Austin; P. Su, X. Liu, P. Chia, and L. Li – Cisco
Systems, Inc.; H.Y Son, J.S Oh, K.Y. Byun, and N.S. Kim –SK Hynix Inc.

Jian-Yu Shih, Cheng-Hao Chiang,Yu- Chen Hu, and KuanNeng Chen – National Chiao Tung University;Yen-Chi
Chen, Chih-Hung Chiu, Chung-Lun Lo, and Chi-Chung
Chang – TXC Corporation

7.

4.

Ryosuke Furuya, Chuanhong Fan, Osamu Asai, Ken
Suzuki, and Hideo Miura – Tohoku University

John Teifel, Richard S. Flores, Robert Jarecki,Todd Bauer,
and Subhash L. Shinde – Sandia National Laboratories

6.

10:00 a.m. – Improvement of the Reliabilityof TSV Interconnections by Controlling theCrystallinity of Electroplated Copper Thin
Films

10:50 a.m. – Ultra Large System-in-Package(SiP) Module and Novel Packaging Solution
for Networking Applications
Mudasir Ahmad, Mohan Nagar, and Weidong Xie – Cisco
Systems, Inc.; Miguel Jimarez and ChangGyun Ryu –Amkor Technology, Inc.

7.

11:15 a.m. – Low-Cost E-Band Flip-Chip
Assembly and Materials
Katarina Boustedt and Per Ligander – Ericsson AB

Program Sessions: Thursday, May 30, 8:00 a.m. - 11:40 a.m.
Session 16:
Interconnect Reliability

Session 17:
Adhesives and Underfill Materials

Session 18: Thermal andMechanical Modeling & Simulation

Committee:
Applied Reliability

Committee:
Materials & Processing

Committee:
Modeling & Simulation

Nolita 2

Nolita 3

Yaletown 4

Session Co-Chairs:
Vikas Gupta – Texas Instruments
Tz-Cheng Chiu – National Cheng Kung University

Session Co-Chairs:
Stephanie Potisek – Dow Chemical
Dwayne Shirley – Qualcomm Technologies, Inc.

Session Co-Chairs:
Erdogan Madenci – University of Arizona
Xuejun Fan – Lamar University

1.

1.

1.

8:00 a.m. – Electromigration of Solder Balls
for Wafer-Level Packaging with Different
Under Bump Metallurgy and Redistribution
Layer Thickness

C. Ferrandon,A. Jouve,Y. Lamy,A. Schreiner, P. Montmeat,
M. Pellat, M.Argoud, F. Fournel, G. Simon, and S. Cheramy– CEA-LETI; S. Joblot – STMicroelectronics

Christine Hau-Riege, Beth Keser,You-Wen Yau, and Steve
Bezuk – Qualcomm Technologies, Inc.

2.

8:25 a.m. – Electromigration Reliability andCurrent Carrying Capacity of Various WLCSPInterconnect Structures

2.

Ahmer Syed, Karthikeyan Dhandapani, Christopher
Berry, Robert Moody, and Riki Whiting – Amkor
Technology, Inc.

3.

8:50 a.m. – Reliability Modeling and Testingof Advanced QFN Packages

8:00 a.m. – Innovative Wafer-Level
Encapsulation & Underfill Material for
Silicon Interposer Application

8:25 a.m. – Wafer Level Underfill Entrapment
in Solder Joint During Thermocompression:
Simulation and Experimental Validation

Shidong Li,Tuhin Sinha,Taryn J. Davis, Kamal Sikka, andPaul Bodenweber – IBM Corporation

2.

A.Taluy – STMicroelectronics, University of Grenoble;
A. Jouve, R. Franiatte, S. Chéramy, and N. Sillon –CEA-LETI; S. Joblot, J. Bertheau,A. Farcy, and P.Ancey– STMicroelectronics;A. Sylvestre – University ofGrenoble3.

Li Li – Cisco Systems, Inc.

8:50 a.m. – Novel Surface Modification of
Nanosilica for Low Stress Underfill

8:00 a.m. – Modeling and Experimental
Study of Thin Bond Line Thermal Interface
Material Failure

8:25 a.m. – 3D vs 2D Modeling of the Effectof Die Size on Delamination in Encapsulated
IC Packages
Siow Ling Ho – Institute of Microelectronics,A*STAR;
Andrew A.O.Tay – National University of Singapore

3.

Ziyin Lin,Yan Liu, and Kyoung-Sik Moon – Georgia
Institute of Technology; C.P.Wong – Georgia Institute ofTechnology, Chinese University of Hong Kong

8:50 a.m. – Effective Package-On-Package
Warpage DOE Design with Analytical
MethodShengmin Wen and Wei Lin – Amkor Technology

Refreshment Break: 9:15 a.m. – 10:00 a.m. (Chelsea 3 & 4)
4.

10:00 a.m. – An Improved Model for
Predicting Fatigue-Crack Propagation
Behaviors in Multiple Solder Bumps on a
BGA Package

4.

10:25 a.m. – Grain Structure Evolution and
Its Impact on the Fatigue Reliability of LeadFree Solder Joints in BGA Packaging Assembly5.

Huili Xu and Choong-Un Kim – University of Texas,
Arlington;Tae-Kyu Lee – Cisco Systems, Inc.

6.

10:50 a.m. – Failure Analysis of Thermallyand Mechanically Stressed Plastic Core
Solder Balls

11:15 a.m. – An Eco-Friendly Cu-Zn Wetting
Layer for Highly Reliable Solder Joints
Young-Ho Kim, Sun-Chul Kim, and Young Min Kim –Hanyang University

10:25 a.m. – Development of Highly Reliable
Flip-Chip Bonding Technology Using NonConductive Adhesives (NCAs) for 20 µm Pitch
Application

6.

10:50 a.m. – High Thermal Conductive
Adhesive Film for Cu and Al Plate Adhesion inPower Electronics Package

5.

11:15 a.m. – The Effect of Coating Thickness
on the Electrical Performance of Novel
Isotropic Conductive Adhesives Prepared
Using Metallised Polymer Micro-Spheres

10:25 a.m. – A Preliminary Solder Joint
Life Prediction Model by Experiment and
Simulation for Translation of Use Condition
to Temperature Cycling Test Condition
Ru Han, Min Pei,Alan Lucero, Daeil Kwon,Yun Ge,
Richard Harries, Pardeep Bhatti, and Tieyu Zheng – Intel
Corporation

6.

10:50 a.m. – Use of Compliant Interconnects
for Drop Impact Isolation
Wei Chen,Anirudh Bhat, and Suresh K. Sitaraman –Georgia Institute of Technology

Toshihisa Nonaka,Akira Shimada, Koichi Aoki, andNoburo Asahi – Toray Industries, Inc.

7.

10:00 a.m. – Damage Pre-Cursor Based
Assessment of Impact of High Temperature
Storage on Reliability of Leadfree Electronics
Pradeep Lall, Kazi Mirza, Mahendra Harsha, and Jeff
Suhling – Auburn University; Kai Goebel – NASA Ames
Research Center

Sun-Chul Kim, Myung-Hwan Hong, Ji-Hyun Lee, andYoung-Ho Kim – Hanyang University

M.M.V.Taklo, J. Seland Graff, and D. Nilsen Wright –SINTEF; H. Kristiansen – Conpart AS; L. Hoff – Vestfold
University College; K.Waaler – WesternGeco AS

7.

4.

Satomi Kawamoto,Atsushi Saito,Yoshihide Fukuhara,
Hiromi Sone, and Masaaki Hoshiyama – NAMICS
Corporation

Takeshi Terasaki, Hisashi Tanie,Tetsuya Nakatsuka, Satoshi
Kurauchi,Tadayuki Yamashita, and Yuichi Furusawa –Hitachi; Hironori Imai – SCSK Corporation

5.

10:00 a.m. – The Optimization of theComposition of Non-Conductive Film andthe Lamination to Wafer

7.

11:15 a.m. – Prediction of Board-Level
Performance of WLCSPYumin Liu and Yong Liu – Fairchild Semiconductor
Corporation

S. Jain, D.C.Whalley, M. Cottrill, and C. Liu –Loughborough University;T. Helland – MosaicSolutions
AS; H. Kristiansen and K. Redford – Conpart AS15

Program Sessions: Thursday, May 30, 1:30 p.m. - 5:10 p.m.
Session 19:
Interposer Characterization

Session 20:
Challenges in 3D Integration

Session 21: Advanced
Substrate and Flip Chip Packaging

Committee:
Interconnections

Committee:
Assembly & Manufacturing Technology

Committee:
Advanced Packaging

Mont-Royal 1

Mont-Royal 2

Nolita 1

Session Co-Chairs:
Matthew Yao – Rockwell Collins
Katsuyuki Sakuma – IBM Corporation

Session Co-Chairs:
AndyTseng – Advanced Semiconductor Engineering, Inc.
Wei Koh – Pacrim Technology

Session Co-Chairs:
Young-Gon Kim – IDT
Raj N. Master – Microsoft Corporation

1.

1.

1.

1:30 p.m. – High Speed Signaling
Performance of Multilevel Wiring on Glass
Substrates for 2.5D Integrated Circuit andOptoelectronic Integration

1:55 p.m. – Unified Methodology for
Heterogeneous Integration with CoWoS
Technology

2.

Yi-Lin Chuang, Chung-Sheng Yuan, Ji-Jan Chen, ChingFang Chen, Ching-Shun Yang,Wei-Pin Changchien,Charles C.C. Liu, and Frank Lee – Taiwan Semiconductor
Manufacturing Company

3.

2:20 p.m. – Power Comparison of 2D, 3D,
and 2.5D Interconnect Solutions and Power
Optimization of Interposer Interconnects

1:30 p.m. – Nano-Silica Composite Laminate
Katsura Hayashi,Tadashi Nagasawa, Keisaku Matsumoto,and Shinya Kawai – Kyocera Corporation

Yuka Ito – Tohoku University, Sumitomo Bakelite Co.,
Ltd.;Takafumi Fukushima, Kang-Wook Lee,Tetsu Tanaka,
and Mitsumasa Koyanagi – Tohoku University; Koji Choki– Sumitomo Bakelite Co., Ltd.

Xiaoxiong Gu, Renato Rimolo-Donadio, Russell Budd,
Christian Baks, Lavanya Turlapati, Christopher Jahnes,
Daniel M. Kuchta, Clint L. Schow, and Frank Libsch – IBM
Corporation2.

1:30 p.m. – Flux-Assisted Self-Assembly with
Microbump Bonding for 3D Heterogeneous
Integration

1:55 p.m. – Micro-Bump Bondability Design
Rules for High Throughput 2.5D/3D ICs
Assembly2.

Chang-Lin Yeh,Yung-Yi Yeh, Jien-Cheng Chen, Jen-Chieh
Kao, Chang-Chi Lee, and Ho-Ming Tong – Advanced
Semiconductor Engineering, Inc.

3.

M.Ataul Karim and Paul D. Franzon – North Carolina
State University;Anil Kumar – GlobalFoundries

2:20 p.m. – Assembly Process Qualification
and Reliability Evaluations for
Heterogeneous 2.5D FPGA with HiCTE
Ceramic

1:55 p.m. – Copper-Filled Anodic Aluminum
Oxide: A Potential Substrate Material for a
High-Density Interconnection
Michio Horiuchi,Yuuichi Matsuda,Yasue Tokutake, Ryo
Fukasawa, and Tsuyoshi Kobayashi – Shinko ElectricIndustries

3.

2:20 p.m. – Development of a Low CTE Chip
Scale Package
Tomoyuki Yamada, Masahiro Fukui, Kenji Terada, andMasaaki Harazono – Kyocera SLC Technologies
Corporation; Charles Reynolds, Jean Audet, Sushumna
Iruvanti, Hsichang Liu, Scott Moore,Yi Pan, and Hongqing
Zhang – IBM Corporation

Ganesh Hariharan, Raghunandan Chaware, Laurene Yip,
Inderjit Singh, Kenny Ng, S.Y. Pai, Myongseob Kim, Henley
Liu, and Suresh Ramalingam – Xilinx, Inc.

Refreshment Break: 2:45 p.m. - 3:30 p.m. (Chelsea 3 & 4)
4.

3:30 p.m. – Large Silicon, Glass and Low
CTE Organic Interposers to Printed Wiring
Board SMT Interconnections Using Copper
Microwire Arrays

4.

3:55 p.m. – Towards Alternative Technologies
for Fine Pitch Interconnects

5.

J.P. Colonna, R. Segaud, F. Marion, M.Volpert,A. Garnier,
L. Di Cioccio, F. De Crécy, C. Laviron, and S. Chéramy
– CEA-LETI;Y. Beillard and S. Mermoz – CEA-LETI,STMicroelectronics

6.

4:20 p.m. – Warpage Control of Silicon
Interposer for 2.5D Package Application

4:45 p.m. – Development andCharacterization of a Through-Multilayer TSV
Integrated SRAM Module
Yunhui Zhu, Xin Sun, Runiu Fang, Xiao Zhong,Yuan Bian,
Meng Chen, Jing Chen,Wengao Lu, and Yufeng Jin –Peking Univ.; Shenglin Ma – Xiamen Univ., Peking Univ.;
Min Miao – Peking Univ., Beijing Information Science andTechnology Univ.

16

3:55 p.m. – Integration Challenges of TSV
Backside Via Reveal Process

6.

4:20 p.m. – Yield and Reliability in 3D
Interconnect and WLP - Ultra Thin Chip
Stacking

5.

4:45 p.m. – Package-on-Package with Very
Fine Pitch Interconnects for High Bandwidth
Ilyas Mohammed, Reynaldo Co, and Rajesh Katkar –Invensas Corporation

3:55 p.m. – Development of Chip-on-Chipwith Face-to-Face Technology as a Low Cost
Alternative for 3D Packaging
J. Sutanto, D.H. Kang, S.Y. Ma, J.H.Yoon, K.S. Oh, M. Oh,
K.R. Park, R. Lanzone, and R. Huemoeller – Amkor
Technology, Inc.

6.

Helge Luesebrink – PVA TePla AG, BU Plasma Systems;
Alastair Attard and Fabian Schnegg – Datacon
Technology GmbH; Gabriel Pares – CEA-LETI

7.

3:30 p.m. – Thermally Enhanced andThin Profile Flip Chip Packages for Tablet
Processor Applications
Hamid Eslampour, Mukul Joshi, KyungOe Kim, Sun Wei,
JaeHan Chung,TaeWoo Lee, HangChul Choi, and Roger
Emigh – STATS ChipPAC, Ltd.

Bo Kai Huang, Chien Ming Lin, Shin Jiang Huang, Ching
Wen Chiang, Pin Cheng Huang, Guang Xin Chen, Chun
Chieh Chao, and Chun Hung Lu – Siliconware Precision
Industries Co., Ltd.

K. Murayama, M.Aizawa, K. Hara, M. Sunohara, K. Miyairi,
K. Mori, and M. Higashi – Shinko Electric Industries Co.,
Ltd.; J. Charbonnier, M.Assous, J.P. Bally, and G. Simon –CEA-LETI

7.

4.

Akihiro Horibe, Keishi Okamoto, Hiroyuki Mori, andYasumitsu Orii – IBM Corporation; Kohichiro Kawate,
Yorinobu Takamatsu, and Hiroko Akiyama – Sumitomo
3M, Ltd.

Xian Qin, Sebastian Gottschall, Nitesh Kumbhat, P.
Markondeya Raj, Sungjin Kim,Venky Sundaram, and Rao
Tummala – Georgia Institute of Technology

5.

3:30 p.m. – Thermally Enhanced Pre-Applied
Underfills for 3D Integration

4:20 p.m. – Mechanical and Board Level
Reliability Considerations of Lidless Flip Chip
BGA Packaging
Shin Low, Inderjit Singh, Ganesh Hariharan, Laurene Yip,and Nael Zohni – Xilinx, Inc.; Mulugeta Abtew, Gowri
Shankar Solaiappan,Vineeth Vair, and Shane Lewis –Sanmina-SCI Corp.

7.

4:45 p.m. – Mechanical Properties of Sn-Bi
Bumps on Flexible Substrate
Min-Su Kim – University of Science & Technology, Korea
Institute of Industrial Technology (KITECH);Yong-Ho
Ko – Korea Institute of Industrial Technology (KITECH),
KAIST; Sehoon Yoo and Chang-Woo Lee – Korea
Institute of Industrial Technology (KITECH)

Program Sessions: Thursday, May 30, 1:30 p.m. - 5:10 p.m.
Session 22:
Solder and Material Characterization

Session 23:
Novel Technologies

Session 24:
Power and Signal Integrity

Committee:
Applied Reliability

Committee:
Materials & Processing

Committee:
Modeling & Simulation

Nolita 2

Nolita 3

Yaletown 4

Session Co-Chairs:
Dongming He – Qualcomm Technologies, Inc.
Donna M. Noctor – Siemens Industry, Inc.

Session Co-Chairs:
Yoichi Taira – IBM Japan
Choong Kooi Chee – Intel Corporation

Session Co-Chairs:
Kemal Aygun – Intel Corporation
Daniel de Araujo – Nimbic, Inc.

1.

1.

1.

1:30 p.m. – Reliability and Failure Mechanismof Solder Joints in Thermal Cycling Tests
Babak Arfaei – Universal Instruments Corporation,
SUNY Binghamton; Sam Mahin-Shirazi, Shantanu Joshi,Peter Borgesen, and Eric Cotts – SUNY Binghamton;
Martin Anselm – Universal Instruments Corporation;
James Wilcox – IBM Corporation; Richard Coyle –Alcatel-Lucent

2.

1:55 p.m. – Correlation of Reliability Models
Including Aging Effects with Thermal Cycling
Reliability Data

Amanpreet Kaur, Xianbo Yang, Kyoung Youl Park, andPremjeet Chahal – Michigan State University2.

Jeffrey C. Suhling, Mohammad Motalab, Muhannad
Mustafa, Jiawei Zhang, John L. Evans, Michael J. Bozack,and Pradeep Lall – Auburn University

3.

2:20 p.m. – Comparison of IMC Growth in
Flip-Chip Assemblies with 100- and 200-µmPitch SAC305 Solder Joints

1:30 p.m. – Reduced Graphene Oxide
Based Schottky Diode on Flex Substrate forMicrowave Circuit Applications

1:55 p.m. – Ultra-Thin, Self-Healing
Decoupling Capacitors on Thin GlassInterposers Using High Surface Area
Electrodes

Seunghyun Hwang, Daehyun Chung,Venkat Satagopan,
Sunil Sudhakaran, Daniel Lin, and Fathi Moghadam –NVIDIA Corporation

2.

Ye Tian – Huazhong University of Science andTechnology, Georgia Institute of Technology; Xi Liu, Justin
Chow, and Suresh K. Sitaraman – Georgia Instituteof Technology;Yi Ping Wu – Huazhong University of
Science and Technology

2:20 p.m. – Electrochemical Assembly of
SAM on Copper for Epoxy/Copper Adhesion
Improvement

1:55 p.m. – System Level Signal and Power
Integrity Analysis for 3200Mbps DDR4
Interface
June Feng, Bipin Dhavale, Janani Chandrasekhar,Yuri
Tretiakov, and Dan Oh – Altera Corporation

Parthasarathi Chakraborti, Himani Sharma, P.
Markondeya Raj, and Rao Tummala – Georgia Instituteof Technology

3.

1:30 p.m. – Simultaneous Switching Noise
Model by Distributed Power Port and
Ground Current Capture

3.

Stephen C.T. Kwok and Matthew M.F.Yuen – Hong Kong
University of Science & Technology

2:20 p.m. – Analysis of Power Integrity and
Its Jitter Impact in a 4.3Gbps Low-Power
Memory Interface
Hai Lan, Xinhai Jiang, and Jihong Ren – Rambus, Inc.

Refreshment Break: 2:45 p.m. - 3:30 p.m. (Chelsea 3 & 4)
4.

3:30 p.m. – Reliability and Shear Strengthof 42Sn-57Bi-1Ag (Wt.%) Lead-Free Solder
Joints after Thermal Aging and Salt Spray
Testing

4.

3:30 p.m. – Chip-Side-Healing as a Basis for
Robust Bare-Chip Assemblies

4.

Matthias Steiert and Jürgen Wilde – University ofFreiburg

3:30 p.m. – Unconditionally Stable Explicit
Method for the Fast 3D Simulation of OnChip Power Distribution Network
Tadatoshi Sekine and Hideki Asai – Shizuoka University

M. Mostofizadeh, J. Pippola, and L. Frisk – Tampere
University of Technology

5.

3:55 p.m. – Plastic Deformation Effect on Sn
Whisker Growth in Electroplated Sn and SnAg Solders

5.

4:20 p.m. – Effect of NCFs with ZnNanoparticles on the Interfacial Reactionsof 40 um Pitch Cu Pillar/Sn-Ag Bump for TSVInterconnection

6.

4:45 p.m. – Advanced In Situ Characterizationof TIM1 Reliability
Peng Li,Yongmei Liu,Alfred La Mar, and Deepak Goyal –Intel Corporation

4:20 p.m. – Development of Low Temperature
Sintered Nano Silver Pastes Using MO
Technology and Resin Reinforcing Technology

7.

4:45 p.m. – Facile Synthesis of BaTiO3Nanorods and Their Shape Effects on theDielectric Constants of Polymer Composites
Pengli Zhu and Rong Sun – Chinese Academy of Science;
C.P.Wong – Chinese University of Hong Kong

3:55 p.m. – Power Delivery Network Analysis
of 3D Double-Side Glass Interposers for High
Bandwidth Applications
Gokul Kumar, Srikrishna Sitaraman, Sung Jin Kim,Venky
Sundaram, and Rao Tummala – Georgia Institute ofTechnology; Jonghyun Cho and Joungho Kim – KAIST

6.

Koji Sasaki and Noritsuka Mizumura – NAMICS
Corporation

Ji-Won Shin,Yong-Won Choi,Young Soon Kim, andKyung-Wook Paik – KAIST; Un Byung Kang and Young
Kun Jee – Samsung Electronics Company, Ltd.

7.

5.

Rabindra N. Das, Frank D. Egitto, and Mark Poliks –Endicott Interconnect Technologies, Inc.

Sung K. Kang – IBM Corporation; Jaewon Chang andHyuck-Mo Lee – KAIST; Jaeho Lee – Hongik University;
Keun-Soo Kim – Hoseo University

6.

3:55 p.m. – Development of Biocompatible
Coatings on Flexible Electronics

4:20 p.m. – Fast Voltage Drop Modelingof Power Grid with Application to Silicon
Interposer Analysis
En-Xiao Liu and Er-Ping Li – Institute of High
Performance Computing, A*STAR7.

4:45 p.m. – Power Delivery Modeling for 3D
Systems with Non-Uniform TSV Distribution
Huanyu He and Jian-Qiang Lu – Rensselaer Polytechnic
Institute; Zheng Xu and Xiaoxiong Gu – IBM
Corporation17

Program Sessions: Friday, May 31, 8:00 a.m. - 11:40 a.m.
Session 25: 3D Microbump Structures
and Silicon to Silicon Bonding

Session 26: High Speed Interconnects &Power Distribution in 3D Integration

Session 27: Wafer Level
and Embedded Packaging

Committee:
Interconnections

Committee:
Electronic Components & RF

Committee:
Advanced Packaging

Mont-Royal 1

Mont-Royal 2

Nolita 1

Session Co-Chairs:
Tom Gregorich – Broadcom Corporation
Li Li – Cisco Systems, Inc.

Session Co-Chairs:
Rockwell Hsu – Tiva Systems Inc. at Cisco Systems, Inc.
Amit P. Agrawal – Cisco Systems, Inc.

Session Co-Chairs:
Luu T. Nguyen – Texas Instruments
Altaf Hasan – Intel Corporation

1.

1.

1.

8:00 a.m. – Key Elements for Sub-50µm Pitch
Micro Bump Processes
J. De Vos, L. Bogaerts,T. Buisson, C. Gerets, G. Jamieson,
K.Vandersmissen,A. La Manna, and E. Beyne – IMEC

2.

8:25 a.m. – Microstructural andMorphological Characterization of
SnAgCu Micro-Bumps for Integration in 3D
Interconnects

2.

8:50 a.m. – Mechanism of Low Temperature
Copper-to-Copper Direct Bonding for 3D
TSV Package Interconnection

8:25 a.m. – Characterization of Power
Delivery Network by Using Optimized Power/
Ground Port Termination Impedance

2.

Seungyong (Brian) Baek and Amit Agrawal – Cisco
Systems, Inc.; Jiali Lai – University of California, Davis3.

8:50 a.m. – An Air-Dielectric Via Structure for
20Gbps+ Board Connectors

8:25 a.m. – Optimization of Solder Heightand Shape to Improve the ThermoMechanical Reliability of Wafer-Level Chip
Scale Packages
Su-Chun Yang, Chung-Jung Wu, Da-Yuan Shih, Chih-Hang
Tung, Cheng-Chang Wei,Yi-Li Hsiao,Ying-Jui Huang,and Douglas Chen-Hua Yu – Taiwan Semiconductor
Manufacturing Company

3.

Xin Wu and David Dunham – Molex, Inc.; Nanju Na andJose A. Hejase – IBM Corporation

J. Cho, S.Yu, M.P.C. Roma, S. Maganty, and S. Park – SUNY,
Binghamton; E. Bersch, C. Kim, and B. Sapp – SEMATECH

8:00 a.m. – A Study of Wafer Level Package
Board Level Reliability
Steven Xu, Beth Keser, Christine Hau-Riege, Steve Bezuk,
and You-Wen Yau – Qualcomm Technologies, Inc.

Jose A. Hejase, Nanju Na, Nam Pham, and Lloyd Walls –IBM Corporation

J. Bertheau, R. Pantel, P. Coudrain, and N. Hotellier –STMicroelectronics; P. Bleuet and J. Charbonnier – CEALETI; F. Hodaj – SIMaP-UMR

3.

8:00 a.m. – A DC-Blocking Dielectric
Waveguide Via Design for High Speed
Signaling at Millimeter Wave Frequencies

8:50 a.m. – Wafer Level Packaging for Ultra
Thin (6 µm) High Brightness LEDs using
Embedding Technology
J. Kleff – TU Berlin; M.Töpper, L. Dietrich, and H.
Oppermann – Fraunhofer IZM; S. Herrmann – OSRAM
Opto Semiconductors GmbH

Refreshment Break: 9:15 a.m. - 10:00 a.m. (Mont-Royal Commons)4.

10:00 a.m. – Room-Temperature HighDensity Interconnection Using Ultrasonic
Bonding of Cone Bump for Heterogeneous
Integration

4.

10:25 a.m. – Low Temperature (<180°C)
Wafer-Level and Chip-Level In-to-Cu andCu-to-Cu Bonding for 3D Integration

5.

Y.S. Chien,Y.P. Huang, R.N.Tzeng, C.T. Chuang,W.
Hwang, J.C. Chiou, and K.N. Chen – National Chiao
Tung University; M.S. Shy,T.H. Lin, K.H. Chen, C.T. Chiu,
and H.M.Tong – Advanced Semiconductor Engineering(ASE) Group6.

10:50 a.m. – Hybrid Au-Au Bonding
Technology Using Planar Adhesive Structure
for 3D Integration

11:15 a.m. – High Throughput Cu-Cu Bonding
by Non-Thermocompression Method
Chuan Seng Tan and Gang Yih Chong – Nanyang
Technological University

18

10:25 a.m. – Wideband and Scalable
Equivalent-Circuit Model for Differential
Through Silicon Vias with Measurement
Verification

10:00 a.m. – Embedded Capacitors in the
Next Generation Processor
Yongki Min, Reynaldo Olmedo, Michael Hill, Kaladhar
Radhakrishnan, Kemal Aygun, Mostafa Kabiri-Badr,
Rahul Panat, Sriram Dattaguru, and Haluk Balkan – Intel
Corporation

5.

10:25 a.m. – 3D Power Module with
Embedded WLCSPShichun Qu, Jihwan Kim, Glen Marcus, and Matt Ring –Fairchild Semiconductor

Kuan-Chung Lu and Tzyy-Sheng Horng – National Sun
Yat-Sen University

6.

Masatsugu Nimura, Jun Mizuno, and Shuichi Shoji –Waseda University;Akitsu Shigetou – National Institutefor Materials Science (NIMS); Katsuyuki Sakuma – IBM
Corporation; Hiroshi Ogino and Tomoyuki Enomoto –Nissan Chemical Industries

7.

4.

M.H. Chang and W. Hwang – National Chiao Tung Univ.,
ASE Group;W.C Hsieh, P.C.Wu, C.T. Chuang, and K.N.
Chen – National Chiao Tung Univ.; C.C.Wang, C.Y.
Ting, K.H. Chen, C.T. Chiu, and H.M.Tong – Advanced
Semiconductor Engineering (ASE) Group

Takanori Shuto, Keiichiro Iwanabe, Li Jing Qiu, andTanemasa Asano – Kyushu University

5.

10:00 a.m. – Multi-Layer Adaptive PowerManagement Architecture for TSV 3DIC
Applications

10:50 a.m. – Wideband Ultralow PowerDistribution Network Impedance Evaluationof Decoupling Capacitor Embedded
Interposers for 3-D Integrated LSI System

6.

T. Braun, K.F. Becker, J. Bauer, and R.Aschenbrenner –Fraunhofer IZM; S.Voges,T.Thomas, R. Kahle, and K.D.
Lang – Technical University Berlin

Katsuya Kikuchi and MasahiroAoyagi – National Institute ofAIST;
Toshio Gomyo andToshikazu Ookubo –Association of SuperAdvanced ElectronicTechnologies (ASET);Toshio Sudo – Shibaura
Institute ofTechnology;Kanji Otsuka – Meisei University

7.

11:15 a.m. – A New Approach to Power
Integrity with Thinfilm Capacitors in 3D IPAC
Functional Module
Saumya Gandhi, P. Markondeya Raj,Venky Sundaram,
Himani Sharma, Madhavan Swaminathan, and Rao
Tummala – Georgia Institute of Technology

10:50 a.m. – From Wafer to Panel Level Mold
Embedding7.

11:15 a.m. – Reliability of Embedding
Concepts for Discrete Passive Components in
Organic Circuit Boards
R. Schwerz, B. Boehme, M. Roellig, and N. Meyendorf– Fraunhofer Institute for Non-Destructive Testing(IZFP-D); K.J.Wolter – TU Dresden

Program Sessions: Friday, May 31, 8:00 a.m. - 11:40 a.m.
Session 28: Drop andDynamic Mechanical Reliability

Session 29:
Substrates

Session 30: Electrical Modelingand Measurements

Committee:
Applied Reliability

Committee:
Materials & Processing

Committee:
Modeling & Simulation

Nolita 2

Nolita 3

Yaletown 4

Session Co-Chairs:
Darvin R. Edwards – Texas Instruments, Inc.
Lakshmi N. Ramanathan – Microsoft Corporation

Session Co-Chairs:
Lejun Wang – Qualcomm Technologies, Inc.
Daniel D. Lu – Henkel Corporation

Session Co-Chairs:
Wendem Beyene – Rambus Inc.
Jaemin Shin – Qualcomm Technologies, Inc.

1.

1.

1.

8:00 a.m. – Effect of Strain Rate on Adhesion
Strength of Anisotropic Conductive Films(ACF) Joints
J. Meng, P. Stark, and A. Dasgupta – University of
Maryland; M. Sillanpaa, Esa Hussa, Jukka P. Seppanen, Jouni
A. Raunio, and Ilkka J. Saarinen – Nokia Corporation2.

8:25 a.m. – An Approach to Board-Level
Drop Reliability Evaluation with Improved
Correlation with Use Conditions2.

8:50 a.m. – A New and Effective Drop
Test Evolution to Next-Gen Handheld
Applications

8:25 a.m. – The New Primer with Copper Foil
Corresponding to Semi-Additive Process for
Package Substrates

2.

Dongji Xie, Min Woo, Zhongming Wu, and Tom
McMullen – Nvidia Corporation; Ife Hsu and Ramgopal
Uppalapati – Intel Corporation;Yingliang Zhou – Huawei;
Andy Zhang – Texas Instruments, Inc.

8:50 a.m. – Dielectric Composite Material
with Good Performance and Processability
for Embedding of Active and Passive
Components into PCBs

8:25 a.m. – Circuit/Channel Co-Design
Methodology for Multimode Signaling
Zhuo Yan and Paul D. Franzon – North Carolina State
University; Kemal Aygün and Henning Braunisch – Intel
Corporation

Hitoshi Onozeki,Tsubasa Inoue, Katsuji Yamagishi,
Takahiro Tanabe,Takayuki Suzuki, Kenichi Ikeda, andNobuyuki Ogawa – Hitachi Chemical Co., Ltd.

3.

8:00 a.m. – System-Level Clock Jitter
Modeling for DDR Systems
Yujeong Shim, Dan Oh, Chuan Thim Khor, Bipin Dhavale,
Sunitha Chandra, Daniel Chow,Weichi Ding, Kundan
Chand,Aman Aflaki, and Mayra Sarmiento – Altera
Corporation

Yunxia Jin, Dunying Deng, and Fei Xiao – Fudan
University

T.T. Mattila, L.Vajavaara, and J. Hokka – Aalto University; E.
Hussa, M. Mäkelä, and V. Halkola – Nokia Corporation3.

8:00 a.m. – Site-Selective Fabrication ofPatterned Transparent Copper Mesh on
Flexible Substrates at Mild Temperature forGreen, Low Cost Electronics

3.

8:50 a.m. – Characterization of a Low-Power,
6.4 Gbps DDR DIMM Memory Interface
System
R. Kollipara, S. Chang, C. Madden, H. Lan, L.
Gopalakrishnan, S. Best,Y. Lu, S. Bangalore, G.E. Kumar,
P.K.Venkatesan, K.Vyas, K. Kaviani, M. Bucher, L. Luo, andK. Prabhu – Rambus, Inc.

Ryan Park, Jürgen Kress, and Norbert Galster – Atotech
Germany GmbH; Seunghyun Cho – Dongyang Mirae
University

Refreshment Break: 9:15 a.m. - 10:00 a.m. (Mont-Royal Commons)4.

10:00 a.m. – Effect of Aging on High-Strain
Rate Mechanical Properties of SAC105 and
SAC305 Lead-Free Alloys

4.

Pradeep Lall, Sandeep Shantaram, and Jeff Suhling –Auburn University; Dave Locker – US AMRDEC

5.

10:25 a.m. – Brittle Fracture of Intermetallic
Compounds in SAC Solder Joints under High
Speed Ball Pull/Pin Pull and Charpy Impact
Tests

10:50 a.m. – Combined Vibration and Thermal
Cycling Fatigue Analysis for SAC305 Lead
Free Solder Assemblies

5.

11:15 a.m. – Effects of Varying Amplitudes on
the Fatigue Life of Lead Free Solder Joints
M. Obaidat, S. Hamasha,Y. Jaradat,A. Qasaimeh, and P.
Borgesen – State University of New York, Binghamton; B.
Arfaei and M.Anselm – Universal Instruments

10:25 a.m. – A Lead-Frame Pre-Mold Coreless
Substrate Development

6.

10:50 a.m. – DBC Substrate for Si- and SiCBased Power Electronics Modules: Design,
Fabrication and Failure Analysis

5.

11:15 a.m. – A Monolithic Aluminum Circuit
Board Structure
Shou-Jen Hsu and Chin C. Lee – University of California,
Irvine10:25 a.m. – A Novel and Accurate
Methodology for Design andCharacterization of Wire-Bond Package
Performance for 5-10GHz Applications
Souvik Mukherjee and Django Trombley – Texas
Instruments, Inc.

6.

Ling Xu,Yang Zhou, and Sheng Liu – Huazhong
University of Science & Technology

7.

10:00 a.m. – Characterization, Modeling,
and Optimization of a 3D Embedded Trench
Decoupling Capacitors in Si-RF Interposer
Hélène Jacquinot – CEA-LETI; David Denis – IPDIA

Chang-Yi (Albert) Lan, C.S. Hsiao, Jensen Tsai, Eason
Chen, and Otis Hong – Siliconware Precision Industries
Co., Ltd.

J.H.L. Pang and F.L.Wong – Nanyang Technological
University; K.T. Heng,Y.S. Chua, and C.E. Long – DSO
National Laboratories

7.

4.

Yu-Hua Chen,Tzyy-Jang Tseng, and Dyi-Chung Hu– Unimicron Technology Corporation;Wei-Chung Lo –Industrial Technology Research Institute (ITRI)

Chaoran Yang – Hong Kong Univ. of Science &Technology; Guangsui Xu – HKUST LED-FPD, South
China Univ. of Technology; S.W. Ricky Lee – Hong
Kong Univ. of Science & Technology, HKUST LED-FPD;
Xinping Zhang – South China Univ. of Technology

6.

10:00 a.m. – An Innovative Embedded
Interposer Carrier for High Density
Interconnection

10:50 a.m. – High Frequency
Characterization and Analytical Modelingof Through Glass Via (TGV) for 3D Thin-Film
Interposer and MEMS Packaging
Cheolbok Kim and Yong-Kyu Yoon – University of
Florida7.

11:15 a.m. – PCB Pin-Field Considerations for
40 Gb/s SerDes Channels
Michael J. Degerstrom, Devon J. Post, Barry K. Gilbert,
and Erik S. Daniel – Mayo Clinic

19

Program Sessions: Friday, May 31, 1:30 p.m. - 5:10 p.m.
Session 31:
TSV Innovation and Implementation

Session 32: Thermal and MechanicalModeling: LED and 3D Structures

Session 33:
MEMS and Sensor Packaging

Committee:
Interconnections

Committee:
Modeling & Simulation

Committee:
Advanced Packaging

Mont-Royal 1

Mont-Royal 2

Nolita 1

Session Co-Chairs:
Gilles Poupon – CEA-LETI
Wei-Chung Lo – ITRI

Session Co-Chairs:
Suresh K. Sitaraman – Georgia Institute of Technology
Sandeep Sane – Intel Corporation

Session Co-Chairs:
S.W.Ricky Lee – Hong Kong Univ.of Science andTechnology
James Jian Zhang – Micron Technology, Inc.

1.

1.

1.

1:30 p.m. – Through Si Vias Using Liquid
Metal Conductors for Reworkable 3D
Electronics
George A. Hernandez, Daniel Martinez, Charles Ellis,
Michael Palmer, and Michael C. Hamilton – Auburn
University

2.

1:55 p.m. – Backside TSV Protrusions Inducedby Thermal Shock and Thermal Cycling

Cao Li,Tao Peng, Xuefang Wang, Mingxiang Chen,
and Sheng Liu – Huazhong University of Science &Technology

2.

Dingyou Zhang and James Jian-Qiang Lu – Rensselaer
Polytechnic Institute; Klaus Hummler and Larry Smith– SEMATECH

3.

2:20 p.m. – Microstructure Investigation of
TSV Copper Film

1:30 p.m. – Drop Impact Simulation andExperimental Validation on High Power Light
Emitting Diodes Modules

1:55 p.m. – L70 Life Prediction for Solid State
Lighting Using Kalman Filter and Extended
Kalman Filter Based Models

K. Zoschke, C.A. Manier, M.Wilke, N. Jürgensen, and H.
Oppermann – Fraunhofer IZM; D. Ruffieux – CSEM; J.
Dekker and H. Heikkinen – VTT Finland; S. Dalla Piazza –Micro Crystal AG; G.Allegato – STMicroelectronics; K.D.
Lang – TU Berlin

2.

Pradeep Lall and Junchao Wei – Auburn University; Lynn
Davis – RTI International

3.

W.N. Putra – Institute of Microelectronics (A*STAR),
Nanyang Technological University; H.Y. Li and A.D.Trigg– Institute of Microelectronics (A*STAR); C.L. Gan –Nanyang Technological University

2:20 p.m. – Effect of Temperature Gradienton Moisture Diffusion in High Power Devices
and the Applications in LED Packages

1:30 p.m. – Hermetic Wafer Level Packaging
of MEMS Components Using Through Silicon
Via and Wafer to Wafer Bonding Technologies

1:55 p.m. – Size-Free MEMS-IC High-Efficient
Integration by Using Carrier Wafer with SelfAssembled Monolayer (SAM) Fine Pattern
Jian Lu, Hideki Takagi, and Ryutaro Maeda – National
Institute of AIST;Yuta Nakano – National Institute of
AIST,Tokyo University of Science3.

2:20 p.m. – Outgassing Characterization of
MEMS Thin Film Packaging Materials
B. Savornin, X. Baillin, D. Saint Patrice, P. Nicolas, P.L.
Charvet, and J.L. Pornin – CEA-LETI; E. Blanquet and I.
Nuta – SIMAP

Xuejun Fan – Lamar University, State Key Lab of SolidState Lighting; Cadmus Yuan – State Key Lab of SolidState Lighting, Chinese Academy of Sciences

Refreshment Break: 2:45 p.m. - 3:30 p.m. (Mont-Royal Commons)4.

3:30 p.m. – Via-Middle Through-Silicon Via
with Integrated Airgap to Zero TSV-Induced
Stress Impact on Device Performance4.

Yann Civale, Stefaan Van Huylenbroeck,Augusto Redolfi,
Wei Guo, Khashayar Babaei, Patrick Jaenen,Antonio
La Manna, Gerald Beyer, Bart Swinnen, and Eric Beyne– IMEC5.

3:55 p.m. – Design and Fabrication of Ultra
Low-Loss, High-Performance 3D Chip-Chip
Air-Clad Interconnect Pathway

4:20 p.m. – Development of Ultra-Low
Capacitance Through-Silicon-Vias (TSVs) with
Air-Gap Liner

5.

4:45 p.m. – TSV Development,
Characterization and Modeling for 2.5DInterposer Applications
J.R.Tenailleau, F.Voiron, and C. Bunel – IPDIA;A. Brunet
and S. Borel – CEA-LETI

20

3:55 p.m. – Comparison of Thermal
Performance between Glass and Silicon
Interposers

6.

4:20 p.m. – Simulation of Electromigration
through Peridynamics

5.

4:45 p.m. – The Effect of Corner Glue on BGA
Package Temperature Cycling Performance:
A Modeling StudyMin Pei, Ru Han,Yun Ge, Sanjay Goyal,Venmathy
Rajarathinam, and Muffadal Mukadam – Intel
Corporation

3:55 p.m. – Hermetic Wafer-Level Glass
Sealing Enabling Reliable Low Cost Sensor
Packaging
Ulli Hansen and Simon Maus – MSG Lithoglas GmbH;Michael Töpper – Fraunhofer IZM

6.

Selda Oterkus, John Fox, and Erdogan Madenci –University of Arizona7.

3:30 p.m. – Surface Compliant Bonding
Properties of Low-Temperature Wafer
Bonding Using Sub-Micron Au Particles
Hiroyuki Ishida and Takuya Yazaki – Suss MicroTec KK;
Toshinori Ogashiwa,Yukio Kanehira, and Hiroshi Murai– Tanaka Kikinzoku Kogyo KK; Shin Ito and Jun Mizuno –Waseda University

Sangbeom Cho,Yogendra Joshi,Venky Sundaram, and
Rao Tummala – Georgia Institute of Technology;Yoichiro
Sato – Asahi Glass

Qianwen Chen, Cui Huang, and Zheyao Wang –Tsinghua University

7.

4.

Sheng-Tsai Wu, Heng-Chieh Chien, and John H. Lau –Industrial Technology Research Institute (ITRI); Ming Li,
Julia Cline, and Mandy Ji – Rambus, Inc.

Erdal Uzunlar, Rajarshi Saha,Vachan Kumar,Azad Naeemi,
and Paul A. Kohl – Georgia Institute of Technology; Rohit
Sharma – Indian Institute of Technology Ropar; Rizwan
Bashirullah – University of Florida

6.

3:30 p.m. – Thermal and Mechanical Design
and Analysis of 3D IC Interposer with
Double-Side Active Chips

4:20 p.m. – Cu/Sn SLID Wafer-Level Bonding
Optimization
Thi-Thuy Luu,Ani Duan, Kaiying Wang, Knut
Aasmundtveit, and Nils Hoivik – Vestfold University
College7.

4:45 p.m. – Reliability of Flip-Chip
Technologies for SiC-MEMS Operating at
500°C
Roderich Zeiser, Lukas Lehmann,Volker Fiedler, andJürgen Wilde – University of Freiburg

Program Sessions: Friday, May 31, 1:30 p.m. - 5:10 p.m.
Session 34: New Developments
in Wirebond Technology

Session 35:
Solder and Bonding

Session 36: System Components
for RF and Millimeter Wave

Committees:Assembly & Manufacturing
Technology / Interconnections

Committee:
Materials & Processing

Committee:
Electronic Components & RF

Nolita 2

Nolita 3

Yaletown 4

Session Co-Chairs:
Jie Xue – Cisco Systems, Inc.
Changqing Liu – Loughborough University

Session Co-Chairs:
Tieyu Zheng – Microsoft Corporation
Myung Jin Yim – Broadcom Corporation

Session Co-Chairs:
Lih-Tyng Hwang – National Sun Yat-Sen University
P. Markondeya Raj – Georgia Institute of Technology

1.

1.

1.

1:30 p.m. – Investigation of Charge Induced
Bond Pad Corrosion
Pei-Haw Tsao, Hung-Yu Chiu, H.C. Liao, K.C. Chen,
M.C. Sung,Worth Chen, and Antai Xu – Taiwan
Semiconductor Manufacturing Company, Ltd.

2.

1:55 p.m. – Effects of Bond Pad Probing for
Cu Wire Bond Packages

2.

2:20 p.m. – A Study of Free Air Ball Formationin Palladium-Coated Copper and Bare
Copper Bonding Wire

1:55 p.m. – The Growth and Segregation ofIntermetallic Compounds in the Bulk of Flip
Chip Sn2.4Ag Solder Joint under Electrical
Current Stressing

2.

Wei-Chieh Wang and Kwang-Lung Lin – National
Cheng Kung University;Ying-Ta Chiu and Yi-Shao Lai –Advanced Semiconductor Engineering, Inc.

3.

2:20 p.m. – Voiding Mechanism and Control
in BGA Joints with Mixed Solder Alloy System

1:55 p.m. – Novel Enhancement Techniquesfor Ultra-High-Performance Conformal
Wireless Sensors and “Smart Skins” Utilizing
Inkjet-Printed Graphene
Taoran Le, Ziyin Lin, C.P.Wong, and M.M.Tentzeris –Georgia Institute of Technology

3.

Yan Liu, Derrick Herron, Joanna Keck, and Ning-Cheng
Lee – Indium Corporation

Noritoshi Araki, Ryo Oishi, and Takashi Yamada – Nippon
Micrometal Corporation;Yasutomo Ichiyama – Nippon
Steel Technoresearch Corporation

1:30 p.m. – Low Cost BT Organic Material
for Wireless 60 GHz Application
Pouya Talebbeydokhti and Mohamed A. Megahed – Intel
Corporation

Bing Dang, Steven Wright, Joana Maria, Cornelia Tsang,
Paul Andry, Lovell Wiggins, and John Knickerbocker –IBM Corporation

John D. Beleran, Gaurav Mehta, Ninoy Milanes II,
and Nathapong Suthiwongsunthorn – United Testand Assembly Center, Ltd. (UTAC); Eu Jin Lee –GLobalFoundries

3.

1:30 p.m. – NiFe-Based Ball-LimitingMetallurgy (BLM) for Microbumps at 50um
Pitch in 3D Chip Stacks

2:20 p.m. – High Performance Plastic Molded
QFN Package with Ribbon Bonding and a
Defective PCB Ground
Yi-Chieh Lin,Wen-Hsian Lee,Tzyy-Sheng Horng, and
Lih-Tyng Hwang – National Sun Yat-Sen University

Refreshment Break: 2:45 p.m. - 3:30 p.m. (Mont-Royal Commons)4.

3:30 p.m. – Single Chip Plated Ni/Pd over
ALCAP Bond Pads for Flip Chip Applications
and Prototyping

4.

Brian J. Lewis, Daniel F. Baldwin, Paul N. Houston, Fei Xie,
and Le Hang La – Engent, Inc.

5.

3:55 p.m. – Low Cost Silver Alloy Wire
Bonding with Excellent Reliability
Performance

4:20 p.m. – Corrosion of the Cu/Al Interface
in Cu-Wire-Bonded Integrated Circuits

5.

4:45 p.m. – Molded Reliability Study for
Different Cu Wire Bonding Configurations
I. Qin, H. Xu, B. Milton, H. Clauberg, and B. Chylak –Kulicke and Soffa Industries, Inc.; H.Abe, D. Kang,Y.
Endo, M. Osaka, and S Nakamura – Hitachi Chemical
Company, Ltd.

3:55 p.m. – High Temperature Ag-In Joints
between Si Chips and Aluminum6.

4:20 p.m. – Failure Mechanisms of Sintered
Silver Interconnections for Power Electronic
Applications

5.

4:45 p.m. – Advanced Materials for Dropin Solution to Pb in High Temp Solders:The
Next Generation of Zinc-Based Solder Alloy
Jianxing Li and Brian Knight – Honeywell Electronic
Materials; Bih Wen Fon and Shutesh Krishnan – On
Semiconductor

3:55 p.m. – Ultra-Miniaturized and SurfaceMountable Glass-Based 3D IPAC Packages
for RF Modules
Y. Sato and M. Ono – Asahi Glass Company; S. Sitaraman,
V. Sukumaran, B. Chou, J. Min, M. Swaminathan,V.
Sundaram, and R.Tummala – Georgia Institute ofTechnology; C. Karoui, F. Dosseul, and C. Nopper –STMicroelectronics

6.

Thomas Herboth, Michael Guenther, and Andreas Fix– Robert Bosch GmbH; Juergen Wilde – University ofFreiburg

7.

3:30 p.m. – Enhanced Multilayer Organic
Packages with Embedded Phased-Array
Antennas for 60-GHz Wireless Communications
Xiaoxiong Gu, Duixian Liu, Maxim Piz,Alberto ValdesGarcia, Christian Baks, Bodhisatwa Sadhu, and Scott K.
Reynolds – IBM Corporation; Dong Gun Kam – IBM
Corporation,Ajou University;Arun Natarajan – IBM
Corporation, Oregon State University

Yuan-Yun Wu and Chin C. Lee – University of California,
IrvineJohn Osenbach, B.Q.Wang, Sue Emerich, John DeLucca,
and Dongmei Meng – LSI Corporation

7.

4.

Yoo-Sun Kim, Seung-Ho Kim, and Kyung-Wook Paik –KAISTC.H. Cheng, S.I. Chu,Y.Y. Shieh, C.Y. Sun, and C. Peng –Elite Semiconductor Memory Technology, Inc.; H.L. Hsiao– Tunghai University

6.

3:30 p.m. – Low Temperature Camera
Module Assembly Using Acrylic-Based Solder
ACFs with Ultrasonic-Assisted ThermoCompression Bonding Method

4:20 p.m. – Integration of Piezoelectric
Energy Harvesting and Antenna Elements on
a Common Substrate
Joshua C. Myers, B. Scott Strachan, Xianbo Yang, andPremjeet Chahal – Michigan State University

7.

4:45 p.m. – Second-Harmonic Nonlinearities
in RF Silicon Integrated Passive Devices
Robert Frye – RF Design Consulting, LLC; Kai Liu –STATS ChipPAC, Inc.; Robert Melville – Emecon, LLC

21

Interactive Presentations: Wednesday, May 29 and Thursday, May 30, 9:00 a.m. - 11:00 a.m. and 2:00 p.m. - 4:00 p.m.
Wednesday, May 29
Session 37: Interactive Presentations 1
9:00 a.m. - 11:00 a.m.
Committee: Interactive Presentations
Chelsea 3 & 4

21.

Session Co-Chairs:
Mark Poliks – Endicott Interconnect Technologies, Inc.
Mark Eblen – Kyocera America, Inc.

22.

1.

23.

2.

3.

4.

5.

6.

7.

8.

9.

10.
11.

12.

13.

14.

15.

16.

17.

18.
19.

20.

22

Adaptable and Integrated Packaging Platform for MEMSBased Combo Sensors Utilizing Innovative Wafer-Level
Packaging Technologies
Cheng-Hsiang Liu, Hong-Da Chang, Kuo-Hsiang Li, Chen-Han Lin,
Chia-Jung Hsu,Tse-Yuan Lin, Hsin-Hung Chou, Hsiao-Chun Huang,and Hsin-Yi Liao – Siliconware Precision Industries Co., Ltd.
Electrochromic Properties of Tungsten Trioxide
Nanostructures
Yi-Hsuan Huang, Chung-Jung Hung, and Tseung-Yuen Tseng –National Chiao Tung University
Wettability of Sn-Bi and Sn-Ag-Cu Lead-Free Solder Pastes
on Electroplated Co-P Films
Donghua Yang, Nianduan Lu, and Liangliang Li – Tsinghua
University
Enhanced Thermal Transport of Hexagonal Boron Nitride
Filled Polymer Composite by Magnetic Field-Assisted
Alignment
Ziyin Lin,Yan Liu, and Kyoung-Sik Moon – Georgia Institute ofTechnology; C.P.Wong – Georgia Institute of Technology, Chinese
University of Hong Kong
Small Diameter Via Filling Electrodeposition by Periodical
Reverse Current
Taro Hayashi, Kazuo Kondo,Takeyasu Saito, Naoki Okamoto, andMasayuki Yokoi – Osaka Prefecture University; Minoru Takeuchi
and Masaru Bunya – Nitto Boseki Co., Ltd.; Masao Marunaka and
Takayuki Tsuchiya – ShinMaywa Industries, Ltd.
Moisture Induced Swelling in Epoxy Moulding Compounds
H.Walter, O. Hölck,T. Braun, J. Bauer, and O.Wittler –Fraunhofer IZM; H. Dobrinski and J. Stuermann – Hella
Fahrzeugkomponenten GmbH; K.D. Lang – Fraunhofer IZM,TU
BerlinFine Pitch Flex-on-Flex (FOF) Assembly Using Nanofiber
Solder Anisotropic Conductive Films (ACFs) and Ultrasonic
Bonding Method
Sang Hoon Lee, Kyung-Lim Suk, and Kyung-Wook Paik – KAIST
Flux Function Added Solder Anisotropic Conductive Films(ACFs) for High Power and Fine Pitch Assemblies
Seung-Ho Kim,Yongwon Choi,Yoosun Kim, and Kyung-Wook
Paik – KAISTMicrowave Induced Plasma Decapsulation of Stressedand Delaminated High Pin-Count Copper Wire Bonded IC
Packages
J.Tang, J.B.J. Schelen, and C.I.M. Beenakker – Delft University ofTechnology; C.H. Chen and S.K. Liang – Advanced Semiconductor
Engineering, Inc.; E.G.J. Reinders and C.Th.A. Revenberg – MASER
Engineering B.V.
Glass Carrier Wafers for the Silicon Thinning Process for
Stack IC Applications
Aric Shorey, Bor-Kai Wang, and Rachel Lu – Corning, Inc.
Versatile Z-Axis Interconnection-Based Coreless Technology
Solutions for Next Generation Packaging
R.N. Das, F.D. Egitto, J.M. Lauffer, E. Chenelly, and M.D. Poliks –Endicott Interconnect Technologies, Inc.
Oxidation Resistance and Joining Properties of Cr-Doped Zn
Bonding for SiC Die-Attachment
S.W. Park,T. Sugahara, S. Nagao, and K. Suganuma – Osaka
University
Thermomechanical Reliability of Ag Flake Paste for DieAttached Power Devices in Thermal Cycling
Soichi Sakamoto, Shijo Nagao, and Katsuaki Suganuma – Osaka
University
A Breakthrough in Power Electronics Reliability – New Die
Attach and Wire Bonding Materials
Thomas Krebs, Susanne Duch,Wolfgang Schmitt, Steffen Kötter,Peter Prenosil, and Sven Thomas – Heraeus Material Technologies
GmbH & Co. KG
Bath Chemistry and Copper Overburden as Influencing
Factors of the TSV Annealing
P. Sättler and K.J.Wolter – TU Dresden; M. Böttcher andCatharina Rudolph – FhG ASSID
Nonlinear Viscoelastic Constitutive Model for Organic
Laminate Substrate
Tz-Cheng Chiu and Yao-Yu Chan – National Cheng Kung
University;Yi-Shao Lai – Advanced Semiconductor Engineering,Inc.
Effect of Processing Factors on Dielectric Properties of
BaTiO3/Hyperbranched Polyester Core-Shell Nanoparticles
Warda Benhadjala, Isabelle Bord-Majek, Laurent Béchou, and Yves
Ousten – University of Bordeaux; Ephraim Suhir – University ofCalifornia, Santa Cruz; Matthieu Buet, Fabien Rougé, and Vincent
Gaud – Polyrise SAS
Strength of Solid-State Silver Bonding between Copper
Yi-Ling Chen and Chin C. Lee – University of California, Irvine
Effect of Pad Design (SMD/NSMD),Via-in-Pad, and Reflow
Profile Parameters on Voiding During the Lead-Free Solder
Bumping Process
Ganesh Pandiarajan, Ross Havens, and Krishnaswami Srihari –State University of New York, Binghamton; Satyanarayan Iyer andGurudutt Chennagiri – SMART Modular Technologies, Inc.
Growth and Strength of the Solid Solution Phase (Ag) with
IndiumYuan-Yun Wu and Chin C. Lee – University of California, Irvine

24.

Assessment of Solder Pad Cratering Strength Using Cold Pin
Pull Test Method with Pre-Fabricated Pin Arrays
Qiming Zhang, Chaoran Yang, Mian Tao, and S.W. Ricky Lee– Hong Kong University of Science & Technology; Fubin Song –Celestica
Reliability of Isotropic Electrically Conductive Adhesives
under Condensing Humidity Testing
Laura Frisk, Sanna Lahokallio, Milad Mostofizadeh, Janne Kiilunen,
and Kirsi Saarinen – Tampere University of Technology
Ethylene-Vinyl Acetate as a Low Cost Encapsulant for
Hybrid Electronic and Fluidic Circuits
Sarkis Babikian,Wesley A. Cox-Muranami, Edward Nelson, G.P. Li,
and Mark Bachman – University of California, Irvine
Noise Coupling of Through-Via in Silicon and GlassInterposer
Manho Lee, Jonghyun Cho, Joohee Kim, Joungho Kim, and Jiseong
Kim – KAIST

15.

16.

17.

18.

Wednesday, May 29
Session 38: Interactive Presentations 2
2:00 p.m. - 4:00 p.m.
Committee: Interactive Presentations
Chelsea 3 & 4

19.

Session Co-Chairs:
Swapan Bhattacharya – Georgia Institute of Technology
Nam Pham – IBM Corporation

20.

1.

21.

2.

3.

4.
5.

6.

7.
8.

9.

10.

11.
12.

13.

14.

Fine-Pitch Backside Via-Last TSV Process with Optimization
on Temporary Glue and Bonding Conditions
E.H. Chen,T.C. Hsu, C.H. Lin, P.J.Tzeng, C.C.Wang, S.C Chen, J.C.
Chen, C.C. Chen,Y.C. Hsin, P.C. Chang,Y.H. Chang,Y.M. Lin, S.C.
Liao, and T.K. Ku, and S.C. Chen – Industrial Technology ResearchInstitute (ITRI)
Investigation of Micromachined LTCC Functional Modules
for High-Density 3D SIP Based on LTCC Packaging Platform
M. Miao – Beijing Info. Sci. and Tech. University, Peking Univ.;Y. Jin,
R. Fang, S. Guo, X. Zhang, and D. Hu – Peking Univ.; F. Mu and X.
Xiang – 43rd Inst. of China Elec.Tech. Group Corp.;Y. Zhang and
Z. Li – Beijing Info. Sci. and Tech. University
Advancements in Package-on-Package (PoP) Technology,
Delivering Performance, Form Factor & Cost Benefits in
Next Generation Smartphone Processors
Hamid Eslampour, Mukul Joshi, SeongWon Park, HanGil Shin, andJaeHan Chung – STATS ChipPAC, Ltd.
Fabrication of 3D-IC Interposers
John Keech, Satish Chaparala,Aric Shorey, Garrett Piech, and Scott
Pollard – Corning, Inc.
Development of Double Sided with Double-Chip Stacking
Structure Using Panel Level Embedded Wafer Level
Packaging
Yen-Fu Su and Kuo-Ning Chiang – National Tsing Hua University;
Chun-Te Lin and Tzu-Ying Kuo – Industrial Technology ResearchInstitute (ITRI)
Innovative Ultra Fine Line Ceramic Substrate for
Semiconductor Package
Nozomi Shimoishizaka,Takahiro Nakano, Mutsuo Tsuji, Eiji
Yamaguchi, Hiroaki Fujimoto, and Hirata Katsunori – ConnectTec
Japan Corporation
Development of Ultra-Thin Low Warpage Coreless Substrate
Yu Sun, Xiaofeng He, Zhongyao Yu, and Lixi Wan – Institute ofMicroelectronics, Chinese Academy of Science
A Compact ROSA Module for Serial 40-Gb/s Optical
Transceiver
Sae-Kyoung Kang, Joon Ki Lee, Joon-Young Huh, Kwangjoon Kim,
and Jonghyun Lee – Electronics and Telecommunications ResearchInstituteFanout Flipchip eWLB (Embedded Wafer Level Ball Grid
Array) Technology as 2.5D Packaging Solutions
Seung Wook Yoon, Patrick Tang, Roger Emigh,Yaojian Lin, Pandi C.
Marimuthu, and Raj Pendse – STATS ChipPAC
Novel Design and Reliability Assessment of a 3D DRAM
Stacking Based on Cu-Sn Micro-Bump Bonding and TSVInterconnection Technology
Cao Li, Xuefang Wang, Mingxiang Chen,Yaping Lv, and Sheng Liu– Huazhong University of Science & Technology,Wuhan National
Lab for Optoelectronics; Shengjun Zhou – Wuhan National Lab
for Optoelectronics, Shanghai Jiao Tong University
Assembly Tolerant Design of Multi-Cell Laser Power
Converters for Wafer-Level Photonic Packaging
S. Sohr, R. Rieske, K. Nieweglowski, and K.J.Wolter – TU Dresden
Reflection-Phase Variation of Cavity-Resonator-Integrated
Guided-Mode-Resonance Reflector for Guided-ModeExciting Surface Laser Mirror
Shogo Ura, Junichi Inoue,Tomonori Ogura, Kenzo Nishio, andYasuhiro Awatsuji – Kyoto Institute of Technology; Kenji Kintaka –National Institute of AIST
Process Integration of Backside Illuminated Image Sensor
with Thin Wafer Handling Technology
H.H. Chang, C.H. Chien, H.C. Fu,W.L.Tsai, C.W. Chiang, C.T. Ko,
Y.H. Chen, and W.C. Lo – Industrial Technology Research Institute(ITRI); K.C. Su and C.S. Li – Brewer Science
Impact of Wafer Thinning on High-k Metal Gate 20nm
DevicesA. Beece – Rensselaer Polytechnic Institute,
GlobalFoundries; R.Agarwal, J. Singh, S. Siddhartha, R.Alapati,
and T.Alvanos – GlobalFoundries; S. Chandrashekhar and
B. Parameshwaran – Suss MicroTec; J. Dumas – Disco Hi-Tech
America, Inc.

22.

23.

24.

25.

26.

27.

Design and Optimization of Planar Multimode Waveguides
for High-Speed, Board-Level Optical Interconnects
Krzysztof Nieweglowski, Ralf Rieske, Sebastian Sohr, and KlausJuergen Wolter – TU DresdenElectronic-Microfluidic System for Sorting Particles andWhole Blood Using Gel Electrodes
Jason Luo, Edward Nelson, G.P. Li, and Mark Bachman – Universityof California, Irvine
Wafer-Level Integration of Micro-Lens for THz Focal Plane
Array Application
Kyoung Youl Park, Nophadon Wiwatcharagoses, and Premjeet
Chahal – Michigan State University
Advanced LED Package with Temperature Sensors andMicrofluidic Cooling
H.Ye – Delft Univ. of Technology, Organization for Applied
Scientific Research (TNO); H.Van Zeijl, R. Sokolovskij, and G.Q.
Zhang – Delft Univ. of Technology;A.W.J. Gielen – Netherlands
Organization for Applied Scientific Research (TNO)
Micromachined Wearable/Foldable Super Wideband (SWA)
Monopole Antenna Based on a Flexible Liquid Crystal
Polymer (LCP) Substrate toward Imaging/Sensing/Health
Monitoring Systems
Cheolbok Kim, Kyoung Tae Kim, and Yong-Kyu Yoon – University
of Florida; Jong Kyu Kim – Attached Institute of ETRI
Three Dimensional Interconnect Using Au and Pillar Bumps
F.J.Wu, L.H. Ho, C.M. Kuo, C.J.Tu, C.T. Hsieh, C.H. Ni, S.C. Chang,
C.Y.Wu, H.Y. Huang, K.A. Lin, and Y.M. Hsu – Chipbond Technology
Corporation
Defect Analysis Using High Throughput Plasma FIB in
Packaging Reliability Investigations
F.Altmann, S. Klengel, J. Schischka, and M. Petzold – Fraunhofer
IWM
High Frequency DC-DC Converter with Co-Packaged Planar
Inductor and Power IC
N.Wang, J. Barry, S. Kulkarni, F.Waldron, J. Rohan, J. O’Brien,
A.M. Kelleher, S. Roy, C.Ó. Mathúna– Tyndall National Institute; J.
Hannon, R. Foley, K. McCarthy- Univ. College Cork; M. Barry –Microelectronics Competence Centre Ireland
Kinetics Study of Intermetallic Growth and Its Reliability
Implications in Pb-Free, Sn-Based Microbumps in 3D
Integration
Yiwei Wang, Jay Im, and Paul S. Ho – University of Texas,Austin;
Seung-Hyun Chae – Texas Instruments, Inc.
Laminates for Miniaturized Integrated Bioelectronic Protein
Analysis Systems
Sara Saedinia, Kevin Limtao, G.P. Li, and Mark Bachman –University of California, Irvine; Kent Nastiuk and John Krolewski– University of Rochester Medical Center
A New 2.5D TSV Package Assembly ApproachY. Lu,W.Yin, B. Zhang, D.Yu, and D. Shangguan – National Center
for Advanced Packaging, Chinese Academy of Sciences; L.
Wan – Chinese Academy of Sciences; G. Xia and F. Qin – Beijing
University of Technology; M. Ru and F. Xiao – Fudan University
Fabrication and Characterization of Novel Photodefined
Polymer-Enhanced Through-Silicon Vias for Silicon
Interposers
Paragkumar A.Thadesar and Muhannad S. Bakir – Georgia
Institute of Technology
Process Characteristics of a 2.5D Silicon Module Using
Embedded Technology as a Feasible Solution for System
Integration and Thinner Form-Factor
Ren-Shin Cheng,Yin-Po Hung,Tzu-Ying Kuo,Yu-Min Lin, FanJun Leu, and Tao-Chih Chang – Industrial Technology ResearchInstitute (ITRI)

Thursday, May 30
Session 39: Interactive Presentations 3
9:00 a.m. - 11:00 a.m.
Committee: Interactive Presentations
Chelsea 3 & 4
Session Co-Chairs:
Ibrahim Guven – University of ArizonaMark Poliks – Endicott Interconnect Technologies, Inc.
1.

2.

3.

4.

5.

6.

A Lumped/Discrete Port De-Embedding Method byPort Connection Error-Cancelling Network in Full-Wave
Electromagnetic Modeling of 3D Integration and Packaging
with Vertical Interconnects
Zhaoqing Chen – IBM Corporation
Current Density Effects on the Electrical Reliability of Ultra
Fine-Pitch Micro-Bump for TSV Integration
Young-Bae Park, Seung-Hyun Kim, Jong-Jin Park, and June-Bum
Kim – Andong National University; Ho-Young Son, Kwon-WhanHan, Jae-Sung Oh, and Nam-Seog Kim – SK Hynix Inc.; Sehoon
Yoo – Korean Institute of Industrial Technology
Fixture-Free Measurement Technique for PDN Discrete
Components
Di Hu, Jaemin Shin, and Timothy Michalka – Qualcomm
Technologies, Inc.
High-Performance RF Components Using CapacitivelyCoupled Contacts over III-N Heterostructures
F. Jahan,Y.H.Yang, and G. Simin – University of South Carolina; M.
Gaevski, J. Deng, and R. Gaska – Sensor Electronic Technology, Inc.;
M. Shur – Rensselaer Polytechnic InstituteHigh-Frequency (RF) Electrical Analysis of Through SiliconVia (TSV) for Different Designed TSV Patterns
Hsin-Kai Huang, Chun-Hsun Lin, Chris Liu, Kwan-Chin Fan, andHsin-Hung Lee – Siliconware Precision Industries Co., Ltd.
Fast Signal Integrity Methodology for PCB Pre-Layout
Analysis and Layout Quality Check
Jimmy Hsu,Thonas Su,Yuan-Liang Li, Edward Hsiung, Kai Xiao,
Xiaoning Ye, and Kai-Bin Wu – Intel Corporation

Wednesday & Thursday Refreshment Breaks: 9:15 a.m. - 10:00 a.m. and 2:45 p.m. - 3:30 p.m. • See pages 10-17 for location.

Interactive Presentations: Thursday, May 30, 2:00 p.m. - 4:00 p.m. and Friday, May 31, 8:30 a.m. - 10:30 a.m.
7.

8.

9.

10.

11.

12.

13.
14.
15.

16.
17.

18.

19.

20.

21.

22.

23.

24.

3D Antenna for GHz Application and Vibration Energy
Harvesting
Konstantin Kholostov, Paolo Nenzi, Fabrizio Palma, and Marco
Balucani – University of RomeElectrical Performance Modeling of Unbalanced Comb Tree
Networks on Advanced PCB Interconnects for High-Rate
Clock Signal Distribution
Thomas Eudes and Blaise Ravelo – ESIGELEC;Thierry Lacrevaz
and Bernard Fléchet – Université de Savoie
Far-End Crosstalk Cancellation Using Via Stub for DDR4
Memory Channel
Chien-Ming Nieh – University of Florida; Jongbae Park – Intel
Corporation
Practical Investigations of Fiber Weave Effects on HighSpeed Interfaces
Gerardo Romo-Luevano, Jaemin Shin, and Timothy Michalka –Qualcomm Technologies, Inc.
High-Speed Packages with Imperfect Power and Ground
PlanesKai Liu, Ma Phoo Pwint Hlaing,Yong Taek Lee, Hyun Tai Kim,
Gwang Kim, Susan Park, and Billy Ahn – STATS ChipPAC, Ltd.;
Robert Frye – RF Design Consulting, LLC
A Miniaturized Module for Bluetooth/GPS by Embedding
Capacitors in Printed-Circuit-Board and Using Interposer
Jong-In Ryu, Se-Hoon Park, Dongsu Kim, Jun-Chul Kim, and JongChul Park – Korea Electronics Technology Institute
Optimal Common-Mode Choke Selection for the HighDefinition Video Interface for the Mobile Application
Junwoo Lee,Youchul Jeong, and Baegin Sung – Silicon Image, Inc.
Pre-Emphasis Parameter Optimization for High Speed
Channels Using De-Convolution Approach
Jifeng Mao and Umesh Chandra – Dell Force10
Graphene Heat Spreader for Thermal Management of Hot
Spots
Zhaoli Gao – Chalmers University of Technology, Hong Kong
University of Science and Technology;Yong Zhang and Johan
Liu – Chalmers University of Technology, Shanghai University;
Yifeng Fu – SHT Smart High Tech AB; Matthew Yuen – Hong Kong
University
Modeling and Simulation of Low Duty Ratio Buck
Synchronous Converter under Large Load Current Switching
Jai P.Agrawal – Purdue University
Compact TSV-Based Wideband Bandpass Filters on 3-D IC
Ying-Cheng Tseng and Tzong-Lin Wu – National Taiwan University;
Peng-Shu Chen,Wei-Chung Lo, and Shih-Hsien Wu – Industrial
Technology Research Institute (ITRI)
Implementation of a MIMO Antenna Design for USB
Dongle Applications
Yu-Kai Tseng,Yi-Chieh Lin, and Lih-Tyng Hwang – National Sun
Yat-Sen University
Efficient Complex Broadside Coupled Trace Modelingand Estimation of Crosstalk Impact Using Statistical BER
Analysis for High Volume, High Performance Printed Circuit
Board Designs
Arun Reddy Chada, Songping Wu, Jun Fan, and James L. Drewniak– Missouri S&T EMC Laboratory; Bhyrav Mutnury – Dell, Inc.;
Daniel N. de Araujo – Nimbic
Terahertz Micropolarizers Using Carbon Microfibers
Amanpreet Kaur, Kyoung Youl Park, Xianbo Yang, Nophadon
Wiwatcharagoses, and Premjeet Chahal – Michigan State
University
Layout Parameter Optimization Based Power and Signal
Integrity Performance Improvement of High-Speed
Interfaces of Wirebond Packages
Om P. Mandhana and Jin Zhao – Intel Corporation
3D IC-Package-Board Co-Analysis Using 3D EM Simulation
for Mobile Applications
Darryl Kostka – CST of America;Taigon Song and Sung Kyu Lim –Georgia Institute of Technology
3D eWLB – Horizontal and Vertical Interconnects for
Integration of Passive Components
M.Wojnowski, G. Sommer, K. Pressel, and G. Beer – Infineon
Technologies AG
mmW Characterization of Wafer Level Passivation for 3D
Silicon Interposer
Y. Lamy, O. El Bouayadi, C. Ferrandon,A. Schreiner,A. Jouve, and L.
Dussopt – CEA-LETI;T. Lacrevaz, C. Bermond, and B. Fléchet –IMEP-LAHC; S. Joblot – STMicroelectronics

Thursday, May 30
Session 40: Interactive Presentations 4
2:00 p.m. - 4:00 p.m.
Committee: Interactive Presentations
Chelsea 3 & 4
Session Co-Chairs:
Patrick Thompson – Texas Instruments, Inc.
Rao Bonda – Amkor Technology
1.

2.

3.

4.

Piezoresistive Stress Sensor for Inline Monitoring During
Assembly and Packaging of QFNThomas Schreier-Alt and Frank Ansorge – Fraunhofer IZM;
Gerhard Chmiel – Elmos Semiconductor AG; Klaus-Dieter Lang
– TU Berlin
Thermo-Mechanical Reliability of Copper-Filled andPolymer-Filled Through Silicon Vias in 3D Interconnects
Xiang Gao, Run Chen, Xuefang Wang, and Sheng Liu – Huazhong
University of Science & Technology,Wuhan National Lab for
Optoelectronics; Xiaobing Luo – Huazhong University of Science& Technology,Wuhan National Lab for Optoelectronics
Electrochemical Reactions in Solder Mask of Flip ChipPlastic Ball Grid Array Package
Kang-Wook Lee, Stephane Barbeau, Francois Racicot, Douglas
Powell, Charles Arvin,Thomas Wassick, and Joseph Ross – IBM
Corporation
Design and Assembly Process Simulation for an Automotive
Power Module
Yong Liu, Qiuxiao Qian, Byoungok Lee,Taekkeun Lee, Joonseo

5.

6.

7.

8.

9.

10.

11.

12.

13.

14.

15.

16.

17.

18.

19.

20.

21.

22.
23.

24.

Son, and Oseob Jeon – Fairchild Semiconductor Corporation
Investigation of Copper-Tin Transient Liquid Phase Bonding
Reliability for 3D Integration
A. Garnier, C. Grémion, R. Franiatte, D. Bouchu, R.Anciant, and S.
Chéramy – CEA-LETI
Development of PCB Design Guide and PCB Deformation
Simulation Tool for Slim PCB Quality and Reliability
Soonwan Chung, Gyun Heo, Jae Kwak, Seunghee Oh,Yongwon
Lee, Changsun Kang, and Tackmo Lee – Samsung Electronics
Company, Ltd.
Thermal Cycling Effect on Intermetallic Formation with
Various Surface Finish of Micro Bump Interconnect for 3D
Package
Mu-Hsuan Chan,Yi-Chian Liao, Chun-Tang Lin, Kuan-WeirChuang, Huei-Nuan Huang, Chi-Tung Yeh,Wen-Tsung Tseng, andJeng-Yuan Lai – Siliconware Precision Industries Co., Ltd.
Development of 300 mm TSV Interposer with Redistribution
Layers on Both Sides Using MEMS Processes
S.Yoshimi, K. Fujimoto, and M.Akazawa – Dai Nippon Printing Co.,
Ltd., NMEMS Tech. Research Org.; H. Matsumoto, H. Mawatari, andK. Suzuki – Dai Nippon Printing Co., Ltd.;T. Itoh and R. Maeda –NMEMS Tech. Research Org.
Optical Transceiver Sub-System Package Based on SiOB
with 8×14Gbps Two-Way Bandwidth
Fengman Liu, Binbin Yang, Baoxia Li, Haidong Wang, and Lixi Wan –Institute of Microelectronics, Chinese Academy of Sciences
Understanding Loss Mechanisms of Passive Interconnectswith Innovative/Cost Effective Structure Implementations for
Supporting 28Gbps and Beyond Transmission
Namhoon Kim, Joong-Ho Kim, Ray Anderson, Paul Wu, andSuresh Ramalingam – Xilinx, Inc.
Numerical Comparison of the Thermal Performance of 3D
Stacking and Si Interposer Based Packaging Concepts
H. Oprins, B.Vandevelde, M. Badaroglu, M. Gonzalez, G.Van derPlas, and E. Beyne – IMEC
Investigation of Modern Electrically Conductive Adhesives
for Die-Attachment in Power Electronics Applications
Johanna Ocklenburg and Jürgen Wilde – University of Freiburg;
Eugen Rastjagaev – Infineon Technologies Austria AG
Shape Engineering of the Fillers in Stretchable, Electrically
Conductive Adhesives: Its Effect on Percolation andConductivity Change During Stretching
Zhuo Li, Kristen Hansen, and Kyoung-Sik Moon – Georgia
Institute of Technology; C.P.Wong – Georgia Institute ofTechnology, Chinese University of Hong Kong
Electrochemically Etched TSV for Porous Silicon Interposer
Technologies
Paolo Nenzi, Konstantin Kholostov, Rocco Crescenzi, and Marco
Balucani – University of Rome; Hanna Bondarenka and Vitaly
Bondarenko – BSUIR
Role of FBEOL Al Pads and Hard Dielectric for Improved
Mechanical Performance in Lead-Free C4 Products
E. Misra,T. Daubenspeck,T.Wassick, K.Tunga, D. Questad, G.
Osborne,T.M. Shaw, and K. McLaughlin – IBM Corporation
Modeling and Simulation of the Comb Structure in the
Presence of Imperfections
Zhang Luo, Sheng Liu, Gang Cao, and Xiaojie Chen – Huazhong
University of Science & Technology,Wuhan National Laboratory
for Optoelectronics
Realization of Ultra-Low Power I/O
L. Shan,T. Dickson,Y. Kwark, C. Baks, D. Becker, R. Krabbenhoft,
and T. Chainer – IBM Corporation; S. Mueller – TU Hamburg; M.
Hoshino, J. Kodemura, and M. Hashimoto – Zeon Corporation;T.
Jimbo and C. Blatt – Zeon Chemicals
Assembly Level Digital Image Correlation under Reflow andThermal Cycling Conditions
W.C. Ralph – Southern Research Institute; G.F. Raiser –Medtronic, Inc.
Thermo-Mechanical Simulations of a Copper to Copper
Direct Bonded 3D TSV Chip-Package Interaction Test Vehicle
Ah-Young Park, Daniel Ferrone, Stephen Cain, Dae Young Jung,
Bruce T. Murray, and Seungbae Park – SUNY Binghamton; Klaus
Hummler – SEMATECH
Characterization and Modeling of Copper TSVs for Silicon
Interposers
D. Malta, C. Gregory, M. Lueck, J. Lannon, J. Lewis, and D.Temple– RTI International; P. DiFonzo – U.S. Department of Defense; F.
Naumann and M. Petzold – Fraunhofer IWM
Design, Fabrication and Assembly of a Novel Electrical andMicrofluidic I/Os for 3D Chip Stack and Silicon Interposer
Li Zheng,Yue Zhang, and Muhannad S. Bakir – Georgia Instituteof Technology
Homogenization of TSV Interposer and Quick Assessment of
Its Thermomechanical Influence on 3D Packages
Cheng-Fu Chen – University of Alaska, Fairbanks
Post Assembly Warpage Prediction Using Refined Zigzag
Element
Bahattin Kilic – Intel Corporation;Atila Barut and Erdogan
Madenci – University of Arizona
Atomistic Study of Welding of Carbon Nanotubes onto
Metallic Substrates
Xiaohui Song – Wuhan National Lab for Optoelectronics, Henan
Academy of Sciences; Mingxiang Chen and Zhinyin Gan – Wuhan
National Lab for Optoelectronics

Friday, May 31
Session 41: Student Interactive Presentations 1
8:30 a.m. - 10:30 a.m.
Committee: Interactive Presentations
Chelsea 3

2.

3.
4.

5.

6.

7.

8.

9.

10.

11.

12.

13.

14.

15.

16.

17.

18.

19.

20.

21.

Session Co-Chairs:
Mark Poliks – Endicott Interconnect Technologies, Inc.
Mark Eblen – Kyocera America, Inc.
1.

Analyses of Propagation Behavior of Crack at Interface
between Die-Attach and Cu Base and Cracks’ Effects on
Reliability of High Brightness Light-Emitting Diode (LED)
Xiang Gao and Sheng Liu – Huazhong University of Science &Technology,Wuhan National Laboratory for Optoelectronics; Xin
Wu and Yong Xu – Wayne State University

22.

Packaging and Sensing Platform using Opto-Electronic Zinc
Oxide Nano-Heterostructure Integration
Anurag Gupta, Mitchell Spryn, Bruce Kim, and Susan Burkett –University of Alabama; Eugene Edwards, Christina Brantley, andPaul Ruffin – U.S.Army AMRDEC
Fluxless Tin Bonding of Silicon Chips to Iron
Shou-Jen Hsu and Chin C. Lee – University of California, Irvine
A Small Flat-Plate Vapor Chamber Fabricated by Copper
Powder Sintering and Diffusion Bonding for CoolingElectronic Packages
Run Hu,Tinghui Guo, Xiaolei Zhu, Sheng Liu, and Xiaobing Luo –Huazhong University of Science & Technology
Buffered Distributed Spray MOCVD Reactor for LED
Production
Shaolin Hu and Zhiyin Gan – Huazhong University of Science &Technology, Guangdong RealFaith Semiconductor Equipment Co.,
Ltd.; Sheng Liu – Huazhong University of Science & Technology
Injection Molding of a WDM System for POF
Communication
S. Höll, M. Haupt, and U.H.P. Fischer – Harz University of Applied
Studies and Research
TSV Electrical and Mechanical Modeling for ThermoMechanical Delamination
Kaushal Kannan, Sukeshwar Kannan, Bruce Kim, and Susan
Burkett – University of Alabama; Suresh Sitaraman – Georgia
Institute of Technology
D-Band Characterization of Co-Planar Wave Guide andMicrostrip Transmission Lines on Liquid Crystal Polymer
Wasif T. Khan,A. Cagri Ulusoy, and John Papapolymerou – Georgia
Institute of Technology
Optimization of Underfill Material for Better Reliability and
Thermal Behavior of 3D Packages with TSVs
Yeonsung Kim and S.B. Park – SUNY, Binghamton
3D Modeling of High Count Fine Pitch Flip Chip Assemblies
W. Kpobie – Ecole Nationale d’Ingénieurs de Metz (ENIM), CEALETI; N. Bonfoh, C. Dreistadt, and P. Lipinski – Ecole Nationaled’Ingénieurs de Metz (ENIM); M. Fendler – CEA-LETI
High Aspect Ratio Sub-100 nm Silicon Vias (SVs) by MetalAssisted Chemical Etching (MaCE) and Copper Filling
Liyi Li – Georgia Institute of Technology; C.P.Wong – Georgia
Institute of Technology, Chinese University of Hong Kong
Stretchable/Printed RF Devices Via High-Throughput, HighDefinability, Soft-Lithography Fabrication
Zhuo Li, Liyi Li, Kyoung-Sik Moon, Fan Cai, and John
Papapolymerou – Georgia Institute of Technology; C.P.Wong –Georgia Institute of Technology, Chinese University of Hong Kong
Stress Analysis in 3D IC Having Thermal Through Silicon Vias
(TTSV)
Shabaz Basheer Patel,Tamal Ghosh,Asudeb Dutta, and Shivgovind
Singh – Indian Institute of Technology Hyderabad
Electronic Packages for High Pressure Applications: A DomeShaped Cavity Design
Eric Jian Rong Phua – Institute of Microelectronics; Riko I Made,
Ahmed Sharif, Chee Cheong Wong, Zhong Chen, Daniel Rhee
MinWoo, and Chee Lip Gan – Nanyang Technological University
3D Chips Can Be Cool:Thermal Study of VeSFET-Based ICs
Xiang Qiu and Malgorzata Marek-Sadowska – University ofCalifornia, Santa Barbara;Wojciech Maly – Carnegie Mellon
University
Power Dissipation Analysis for Different Configurations ofTSVs at High (GHz) Frequencies
Aditya Vikram Singh, Divanshu Chaturvedi, Shiv Govind Singh,
and Mohammed Zafar Ali Khan – Indian Institute of Technology
Hyderabad
Fabrication of Deep Vias/Grooves as Interconnection Path by
Wet Etching for Wafer Level Packaging of GaAs Based Image
SensorShuangfu Wang, Jiaotuo Ye, and Le Luo – Chinese Academy of
Sciences
An Experimental Verified Model for Cu Electrodeposition
Simulation for the Filling of High Aspect Ratio ThroughSilicon Vias
H.Wu and Z.A.Tang – Dalian University of Technology; Z.Wang, C.
Song, D.Yu, and L.Wan – Chinese Academy of Sciences;W. Cheng– Jiangsu R&D Center for Internet of Things
Fabrication of Gel Glass Containing High Rendering
Phosphor Mixture Via Sol-Gel Process for LED Packaging
Liang Yang, Zhicheng Lv, Mingxiang Chen, and Sheng Liu –Huazhong University of Science & Technology
Implementation of Semiconducting Nanowires for the
Design of THz Detectors
Xianbo Yang,Amanpreet Kaur, and Premjeet Chahal – Michigan
State University
Study of Low Load and Temperature, High Heat-Resistant
Solid-Phase Sn-Ag Bonding with Formation of Ag3Sn
Intermetallic Compound Via Nanoscale Thin Film Control for
Wafer-Level 3D-Stacking for 3D LSI
Kiyoto Yoneta, Ryohei Sato,Yoshiharu Iwata, Koichiro Atsumi,
Kazuya Okamoto, and Yukihiro Sato – Osaka University
A Compact Inductively Coupled Connector for Mobile
Devices
Wenxu Zhao, Peter Gadfort, Evan Erickson, and Paul D. Franzon –North Carolina State University

Wednesday & Thursday Refreshment Breaks: 9:15 a.m. - 10:00 a.m. and 2:45 p.m. - 3:30 p.m. • See pages 10-17 for location.

23

Technology Corner Booth and Poster Layout
Technology Corner Exhibits

Wednesday, May 29, 2013 • 9:00 a.m. - Noon & 1:30 p.m. - 6:30 p.m.
Thursday, May 30, 2013 • 9:00 a.m. - Noon & 1:30 p.m. - 4:00 p.m.

Interactive Presentation Sessions

Wednesday, May 29, 2013 morning Interactive Presentations • 9:00 a.m. - 11:00 a.m.
Wednesday, May 29, 2013 afternoon Interactive Presentations • 2:00 p.m. - 4:00 p.m.
Thursday, May 30, 2013 morning Interactive Presentations • 9:00 a.m. - 11:00 a.m.
Thursday, May 30, 2013 afternoon Interactive Presentations • 2:00 p.m. - 4:00 p.m.
Friday, May 31, 2013 Student Interactive Presentations • 8:30 a.m. - 10:30 a.m.

The Cosmopolitan • Chelsea Ballroom

Interactive Presentations

Refreshment Breaks

Entrance

The Cosmopolitan • Chelsea Commons24

Technology Corner Exhibitors
3D Glass Solutions
4343 Pan American Freeway NE
Albuquerque, NM 87107
Phone: 866-559-8982
Fax: 866-561-0975
www.3dglassSolutions.com
Contact: Roger Cookroger.cook@3dglassSolutions.com
Booth CC11
3D Glass Solutions provides glass interposer,
Through-Glass (TGV) and complete glass microdevice fabrication services and products to a variety
of markets including semiconductor 2.D and 3D SIP,
BEOL, RF, MEMS, MOEMS, optoelectronics, labon-a-chip, microfluidics and a variety of others. Ourservices include design, process development, full
prototyping and fabrication services for micro-devices
in glass, fused silica and ceramic .Capabilities include
photo-lithography, thin films, etch, metrology and full3D surface structuring. Our patent pending photostructurable APEX™ GLASS enables us to produce
these 3D structured parts in a high volume batchprocess.
3D Systems Packaging Research Center (PRC)
Georgia Institute of Technology
813 Ferst Drive, NW
Atlanta, GA 30332-0560
Phone: 404-894-9097
Fax: 404-894-3842
www.prc.gatech.edu
Contact: Dr. Venky Sundaram
vs24@gatech.edu
Booth 317
The 3D Systems Packaging Research Center (PRC)
at the Georgia Institute of Technology is an IndustryCentric Global Academic Center dedicated toleading-edge research and education in the Systemon-a-Package (SOP) concept to enable highly
miniaturized, multi- to mega-functional systems ina single package. Led by Prof. Rao Tummala, the
PRC’s research encompasses advanced 3D systems
packaging technologies including: design and test; ultrathin and ultra-high density organic packages; glass andsilicon interposers; fine-pitch off-chip and board-levelinterconnections; thin film passives for power RF, signal
conditioning applications; and highly integrated functional
modules; all enabled by cross-disciplinary research,academic faculty and students. The PRC offers a variety
of industry partnerships that include one-on-one
contracts and consortia research programs. Benefits
include intellectual property rights, technology transfer,access to students for recruiting, one-on-one companyto-faculty relationships, state-of-the-art R&D facilities,
advanced technology prototypes (new), and more.
ACM Research, Inc.
42307 Osgood Road Suite # I
Fremont, CA.94539
Phone: 510-445-3700
Fax: 510-445-3708
www.acmrcsh.com
Contact: David Wang
dwang@acmrcsh.com
Booth 411
ACM Research, Inc. was founded in 1998 in Silicon
Valley. In September 2006, ACM shifted its focus toAsia, forming ACM Shanghai subsidiary. The company is
now located in Shanghai’s Zhangjiang High-Tech Park. In
where, it conducts research, development, engineering,
manufacturing, marketing, sales and service activities.
ACM specializes in wet process equipment including
single-wafer megasonic cleaning tools (Ultra C), copper
stress free polishing (Ultra SFP) and copper plating(Ultra ECP).
ACM has a strong IP portfolio with over 100 patents
filed internationally. ACM is committed to providing
customers with advanced technology solutions, lowcost of owner –ship, world-class products, service andengineering.

Aetrium
2350 Helen Street
North St. Paul, MN 55109
Phone: 651-770-2000
Fax: 651-770-7975
www.aetrium.com
info@aetrium.com
Booth 514
Aetrium is a leading provider of advanced Reliability
Test Systems to the global semiconductor industry.
Aetrium’s versatile test platform offers a large portfolioof reliability test applications in a single integrated system
including, Electromigration, CVTDDB, BTS, SILC,
BTI and HCI. A single Package Level Reliability (PLR)
test system supports multiple, independently running
experiments, each at different test temperatures (upto 450° C) and electrical bias conditions. The system
also supports Wafer Level Reliability (WLR) testing andis easily expanded or reconfigured to meet changing
requirements. Aetrium also offers a compact WLR
test system which essentially provides a zero-footprint
solution when integrated with a probe station. Aetrium
equips its customers for success by producing thefastest and most comprehensive intrinsic reliability datain the industry.
AGC
4375 NW 235th Avenue
Hillsboro, OR 97124
Phone: 714-745.3193
Fax: 503-844-9308
www.agcem.com
Contact: Vern Stygar
vstygar@agcem.com
Booth 405
AGC is a leading supplier of glass for the world’s
building, automotive and electronic device industries.
AGC’s products for electronics include alkali-freealumino-borosilicate glass, the material of choice forLED, MEMS, and interposer electronic substrates.
AGC’s EN-A1 (alumino-borosilicate) glass is particularly
suited for through glass vias (TGV) used in active andpassive applications where cost is a priority. For highfrequency applications above 10 GHz, AGC’s speciallyformulated AQ (synthetic quartz) product approaches
sapphire in Dk and Loss Tangent. AGC specialty glasses
are world renowned for providing unique glass solutions
to the electronics industry allowing the designer a fullrange of novel engineering approaches. With worldwide
glass making capability, AGC can support manufacturers
in Asia, Europe and North America.
AI TECHNOLOGY, INC.
70 Washington Road
Princeton Junction, NJ 08550
Phone: 609-799-9388
Fax: 609-799-9308
www.aitechnology.com
Contact: Richard Amighramigh@aitechnology.com
Booth 303
Since pioneering the use of flexible epoxy technology
for microelectronic packaging in 1985, AI Technology
has been one of the leading forces in the developmentof advanced material and adhesive solutions including:Insulated Metal Thermal Substrates, Gap-Filling
Compressible Phase-Change Pads, Thermal Gels,
Thermal Grease, Stress-free Adhesive Films, Adhesive
Pastes, RF/EMI shielding solutions, and Copper-Clad
Laminates. AI Technology’s ISO9001:2008 certified
facility produces an extensive line of adhesive materials
that include: Conductive and Dielectic materials, highoperating temperature adhesive solutions, room
temperature cure materials, solvent free material,
Z-Axis conductive material along with Mil-Std 883H
5015 & NASA-ESA Outgassing certified materials.
More recently, AIT has introduced more advanced
products for the LED and Solar Industry and is ITAR
registered.

ALLVIA, Inc.
657 N. Pastoria Ave.
Sunnyvale, CA 94085
Phone: 408-212-3200
Fax: 408-720-3334
www.allvia.com
Contact: Ed McBain
info@allvia.com
Booth 401
ALLVIA, Inc. provides Silicon Interposer and ThroughSilicon Via (TSV) foundry services to Semiconductor,
Optoelectronics and MEMS industries meeting thedemands of advanced vertical interconnects. 2.5D,
3D and System-in-Package (SiP) solutions. ALLVIA,
a leader in TSV development, provides design andprocessing for frontside (filled) and backside (conformal
plated) through silicon vias. With its full line of in-houseprocessing equipment, ALLVIA offers services for
prototyping as well as volume production runs.
Alpha Novatech, Inc.
473 Sapena Ct. #12
Santa Clara, CA 95054
Phone: 408-567-8082
Fax: 408-567-8053
www.alphanovatech.com
Contact: Glenn Summerfieldsales@alphanovatech.com
Booth 413
Alpha Novatech, Inc. is your partner for Thermal
Solutions. We offer a wide variety of standard heat sinks
and accessories.
Our product line includes natural convection, forced
convection, and active heat sinks. We also offer various
attachment methods and hardware for almost any
application. In addition, we can offer free heat sinkthermal simulations. Standard or custom heat sinks inprototype to production quantities Quick and easy
customization without NRE fees, while featuring shortlead times Standard parts are carried in stock Leadtime for custom parts of 1-2 weeks is possible for initialquantities
Amkor Technology, Inc.
1900 S. Price Road
Chandler, AZ 85286
Phone: 480-821-5000, ext. 7891
Fax:480-821-8263
www.amkor.com
Contact: Deborah Patterson
Deborah.Patterson@amkor.com
Booth 300
Amkor Technology, Inc. is one of the world’s largest
providers of advanced semiconductor assembly andtest services. Founded in 1968, Amkor has become astrategic manufacturing partner for many of the world’s
leading semiconductor companies and electronics
OEMs, providing a broad array of advanced package
design, assembly and test solutions. Amkor’s operationalbase encompasses more than 5 million square feet of
manufacturing facilities, product development centers,
and sales & support offices in Asia, Europe and theUnited States. Amkor offers a suite of services, including
electroplated wafer bumping, probe, assembly andfinal test. Amkor is a leader in advanced copper pillar
bump and packaging technologies which enables next
generation flip chip interconnect.

25

ASE Group
1255 E.Arques Ave.
Sunnyvale, CA 94085
Phone: 408-636-9500
Fax: 408-636-9485
www.aseglobal.com
Contact: Patricia MacLeod
patricia.macleod@aseus.com
Booth 417
ASE Group is the world’s largest provider of
independent semiconductor manufacturing services
in assembly and test. With over twelve facilities
worldwide, ASE is meeting the industry’s evolving
demand for critical IC features such as smaller
footprint, lower power, and higher performance.
ASE’s broad portfolio of technology and solutions
encompass IC test program design, front-end
engineering test, wafer probe, wafer bump, substrate
design and supply, wafer level package, flip chip, systemin-package, final test and electronic manufacturingservices. The Group generated sales revenues of$4.0 billion in 2010 and employs over 34,000 people
worldwide. For more information on the ASE portfolio
including our proven copper wire bond capabilities andour advances in 3D & TSV technologies, please visit
www.aseglobal.com.
Beam Services, Inc. / BSI Engineering
6960 Koll Center Parkway, Ste. 305
Pleasanton, CA 94566 USA
Phone: 925-462-8800
Fax: 925-462-1818
www.beamservices.com
Contact: Chip Maschal
chip.maschal@beamservices.com
Booth CC4
Beam Services is an International distributor for
semiconductor inspection equipment in the US /Canada and is also the manufacturer of electrostatic
temporary bond solutions. BSI provides installation,
applications, warranty, and post warranty support forour electrostatic temporary bond solutions and all of
the equipment we distribute. BSI recently created a
new Engineering division as a wholly owned subsidiary.
BSI-Engineering specializes in front-end and BEOL
electrostatic temporary bond solutions. This technology
was developed for the handling of thin substrates, small
form factor substrates, cingulated devices, and coupons.
Our front end solutions are based on standard SEMI
specified silicon wafers and are compatible with mosttool sets. Our new BEOL carriers are integrated into
standard JEDEC trays and are used for the handlingof devices post cingulation. These new carriers are
non-form factor dependent and can be equipped witha patented standby mode allowing for one year ofbonding force generation per charge.
Bergquist Company, The
18930 West 78th Street
Chanhassen, MN 55317
Phone: 952-835-2322
Fax: 952-835-0430
www.bergquistcompany.com
webmaster@bergquistcompany.com
Booth 400
The Bergquist Company is the industry leader inthe design and manufacturing of high performance
thermal management materials used to cool electronic
components. Bergquist supplies the world with someof the best-known brands in the business: Sil-Pad®
thermally-conductive interface materials, Gap Pad®
electrically insulating and non-insulating gap fillers,
Hi-Flow® phase change grease replacement materials,
Bond-Ply® thermally-conductive adhesive tapes,
and Thermal Clad® insulated metal substrates forsurface-mount applications. Bergquist also designs andmanufactures HeatSeal® membrane switches. The
company’s patented HeatSeal process thermally bonds
switch layers together, creating a seal impervious tomoisture, temperature extremes and cleaning chemicals.
HeatSeal also provides superior protection against ESD
events that can ruin ordinary membrane switches thatare bonded with pressure sensitive adhesive (PSA).

26

C2MI – MiQro Innovation Collaborative Centre
45, Boulevard de l’Aéroport
Bromont, QC J2L 1S8
CanadaPhone: 450-534-8000
Fax: 450-534-5760
www.c2mi.ca
Contact: Vincent Fortin
vincent.fortin@c2mi.ca
Booth 106
The MiQro Innovation Collaborative Centre (C2MI)
is an international beacon in advanced packaging andmicrosystems. Its goal is to allow its members tofoster the growth of the microelectronics industry
through the accelerated commercialization ofmarket-driven prototypes. More specifically, theC2MI strives to create a global Centre of Excellence
for Commercialization and Research (CECR) in
200mm-based microelectromechanical systems(MEMS) and 3D wafer level packaging (WLP) as wellas advanced technologies associated with the assemblyand packaging of silicon chips in addition to embedded
systems. The Centre provides an ideal environment for
its members to thrive through partnerships in a facility
that is state-of-the-art. In addition, the C2MI supports
its members through all phases of the development
process, helping them to achieve commercializationahead of the competition
Chip Scale Review
PO Box 9522
San Jose, CA 95157-0522
Phone: 408-429-8585
Fax: 408-429-8605
www.ChipScaleReview.com
Contact: Kim Newman
knewman@chipscalereview.com
Booth 506
Chip Scale Review is the leading internationaltest, assembly, and packaging magazine for WLP,
TSVs, 2D/3D device packaging and high-density
interconnection of microelectronics, ICs, MEMS, RF/wireless, optoelectronic and other wafer-fabricateddevices for the 21st century. Chip Scale Review ispublished six times in print and digital circulated toover 25,000 subscribers worldwide. CSR co-sponsors
the visionary 10th annual International Wafer-Level
Packaging Conference (IWLPC) with SMTA being
held Nov 4-7, 2013 in San Jose, California (www.
iwlpc.com). Drop off your business card to receive
a one year subscription or subscribe online at www.
ChipScaleReview.com
CORWIL Technology Corporation
1635 McCarthy Blvd.
Milpitas, CA 95035
Phone: 408-321-6404
Fax: 408-321-6407
www.CORWIL.com
Contact: Rosie Medina
info@corwil.com
Booth 412
CORWIL was founded in 1990 to provide highquality and responsive IC assembly and test services
to the semiconductor, OEM electronics, military andaerospace, and medical industries. CORWIL is adiversified provider of various services, including wafer
thinning and dicing, optical/manual inspection, and full
assembly (wirebond & flip chip) and testing of IC’s in
QFN, ceramic, and BGA packages, as well as complex
modules. CORWIL is a high volume subcontractor
of wafer dicing, visual inspection, and die pick & place
services with experience in exotic wafer materials suchas sapphire, gallium nitride, gallium arsenide, indium
phosphate, and silicon germanium. CORWIL is certified
QML (Q & V), ISO 9001:2000 & ITAR registered.

CPS Technologies Corporation
111 South Worcester Street
Norton, MA 02766
Phone: 508-222-0614
Fax: 508-222-0220
www.alsic.com
Contact: Bo Sullivan, Senior Account Manager
bsullivan@alsic.com
Booth 107
CPS Technologies Corporation is the worldwide leader
in the design and high-volume production of AlSiC(aluminum silicon carbide) for high thermal conductivity
and device compatible thermal expansion. AlSiC
thermal management components manufactured by
CPS include hermetic electronic packaging, heat sinks,
microprocessor flip chip heat spreader lids, thermal
substrates, IGBT base plates for motor controllers,cooler baseplates, Pin Fin baseplates for Hybrid Electric
Vehicles (HEV) and System in Package (SiP) HeatSpreader Lids that address multiple IC’s on a PCB witha single lid design.
CST of America, Inc.
492 Old Connecticut Path, Suite 505
Framingham, MA 01701
Phone: 508-665-4400
Fax: 508-665-4401
www.cst.com
Contact: Debra Gasser
Debra.Gasse@cst.com
Booth 204
CST of America, Inc. is the leading supplier of 3Delectromagnetic simulation tools in North America.
CST’s products aid in the microwave/RF and highspeed design of many consumer, industrial, aerospaceand research level components and systems includinginterconnects, packages, materials, wireless devices, andvehicles. The software has an excellent 3D interface
with robust imports from all the major CAD and EDA
vendors. Huge cost savings are possible, by reducing or
eliminating the hardware prototype stage of a design.
Key results can be analyzed and optimized based onuser goals.
CVInc
850 S. Greenville, Suite 108
Richardson, TX, 75081
Phone: 972-664-1568
Mobile: 214-557-1568
FAX: 972-664-1569
www.covinc.com
Contact: Terence Q. Collier
tqcollier@covinc.com
Booth 502
CVI specializes in a number of quick turn processing
for die bumping (single die, partial wafers andcomplete wafers), plating and assembly. Bumping
capabilities include solder bumps, gold stud bumps
and copper pillars. Our ability for in-house plating ofboth electrolytic and electroless (Cu, Sn, Ni, Au andPd) helps provide same day or next day processing ofbumping materials.
When board assembly is required our capable team canassist with conceptualization, layout and manufacture.
Fabrication materials for substrates and interposers
include silicon, quartz and alumina. CVI can takeelectrical schematics to complete layout and fabrication
for both PCB and small form factor CSP assembly.
If same day or next day bumping or single die bumping
is required please contact Terence Q. Collier.

Dassault Systémes, SIMULIA
166 Valley Street
Providence, RI 02909-2499
Phone: 510-449-2526
Fax: 401-276-4408
www.3ds.com/simulia.com
simulia.info@3ds.com
Contact: Sowmya Narayan
Sowmya.narayan@3ds.com
Booth 214As an integral part of Dassault Systèmes
3DEXPERIENCE platform SIMULIA applications forfinite element analysis, multiphysics simulation, design
optimization, and simulation lifecycle management
accelerate the process of making mission-critical designand engineering decisions, before committing to costly
and time-consuming physical prototypes.
DCG Systems, Inc.
45900 Northport Loop East
Fremont, CA 94538
Phone: 510-897-6800
Fax: 510-897-6801
www.dcgsystems.com
Contact: Nickey Berens
Nicole_berens@dcgsystems.com
Booth 500
The ELITE (Enhanced Lock-In Thermal Emission)utilizes Lock-In Thermography (LIT) to accurately andefficiently locate defects in x-y-z. ELITE incorporates
the highest sensitivity thermal emission camera in themarket (capable of detecting down to 20 nW of local
power dissipation), high resolution MWIR imaging witha large format InSb camera, 3D localization for throughpackage imaging including stacked-die analysis, contactless absolute temperature mapping. Further real-time,
pixel-wise IR lock-in thermography requires neither
post-processing nor limitations on integration time.
Applications of ELITE beyond leading-edge ICs range
from power devices to general non-destructive testing(NDT). DCG Systems, Inc. is the industry’s leading
supplier of semiconductor diagnostic, characterizationand defect localization solutions. DCG Systems delivers
the most comprehensive and advanced systems
available to enhance the yield and efficiency of today’s
micro-fabrication technologies.
DISCO Hi-Tec America, Inc.
3270 Scott BoulevardSanta Clara, CA 95054-3011
Phone: 408-987-3776
Fax: 408-987-3785
www.discousa.com
Contact: Devin Martin
devin_m@discousa.com
Booth 105
DISCO Corporation is the world leader in cutting,
grinding, and polishing technology.With more than
40 years of experience in precision processing awide variety of materials, DISCO has amassed a vast
knowledge base in these core competencies. Along with
providing related equipment and tooling, DISCO offersa variety of services including process optimization,
joint development initiatives, and consultative services.
Additionally, next generation product prototyping
and small run product output is available at theDevelopment Center in Santa Clara, CA. For more
information, please contact DISCO at (408) 987-3776.

Dow Corning Corporation
2200 W. Salzburg Road
Midland, MI 48686
Phone: 989-496-4839
Fax: 989-496-6824
www.dowcorning.com/electronics
Contact: Ken Seibert
ken.seibert@dowcorning.com
Booth 309
Dow Corning, headquartered in Midland, MI, is aleading supplier of silicon-based materials for wirebond, flip chip and advanced packaging applications. In
addition to the current product line of encapsulants,
die attach adhesives, lid seal adhesives, and thermalinterface materials, Dow Corning is investing in thedevelopment of new materials technology to meet thechallenging needs of emerging applications – including
wafer bonding, photopatternable silicones and opticalinterconnects. Dow Corning leads by delivering
innovative products, application technologies, andreliable global supply, making it easy to do business andwin in your markets.

EV Group, Inc.
7700 South River Parkway
Tempe, AZ 85284
Phone: 480-305-2400
Fax: 480-305-2401
www.evgroup.com
Contact: Carl Mann
SalesUS@EVGroup.com
Booth 406
EV Group (EVG) is a leading supplier of equipment
and process solutions for the manufacture ofsemiconductors, microelectromechanical systems(MEMS), compound semiconductors, power devices,and nanotechnology devices. Key products include
wafer bonding, thin-wafer processing, lithography/
nanoimprint lithography (NIL) and metrology
equipment, as well as photoresist coaters, cleaners
and inspection systems. Founded in 1980, EV Group
services and supports an elaborate network of global
customers and partners all over the world. Moreinformation about EVG is available at www.EVGroup.
com.

Dow Electronic Materials
455 Forest Street
Marlborough, MA 01752
Phone: 508-481-5970
www.dowelectronicmaterials.com
Contact: Bob Formanbforman@dow.com or 425-785-9817
Booth 216
Dow Electronic Materials, a global supplier ofmaterials and technologies to the electronics industry,
brings innovative leadership to the semiconductor,
interconnect, finishing, display, photovoltaic, LED and
optics markets. From advanced technology centersworldwide, teams of talented Dow research scientists
and application experts work closely with customers,
providing solutions, products and technical service
necessary for next-generation electronics. Dow’s
portfolio includes metallization, dielectric, lithography
and assembly materials for advanced semiconductor
packaging applications, such as bumping, pillars,
redistribution, passivation and UBM used for the latest
WLCSP, flip chip, SiP, and 3D chip packages.

ficonTEC (USA) Corporation
25 Calle Canela
San Clemente, CA 92673
Phone: 949-388-5800
Fax: 949-388-1489
www.ficontec.com
Contact: Soon Jangjang@ficontec.com
Booth 115
ficonTEC is a global, premier supplier of micron- andsubmicron-precision automation solution systems fordevice assembly and testing applications. Given its
unique capabilities, ficonTEC has become a strategic
manufacturing partner and a provider of various
automated assembly and test solutions for many of
the world’s leading device manufacturers and OEMs.
Such applications range from semi-automated andautomated submicron-precision eutectic and epoxy die
bonding and LDB soldering, six (6) axis micro-optics
alignment and assembly, micro-OE and fiber-optic
device assembly, among many. The solution is uniquely
provided through a collaborative engineering effort
with ficonTEC from the development to production
phases, captured in a semi-customized system product.
Customers’ system solutions are supported by
ficonTEC’s acclaimed worldwide Customer Service andSupport department.

Dynaloy- a subsidiary of Eastman Chemical
Company6445 Olivia Lane
Indianapolis, IN 46226
Phone: 317-788-5694
Fax: 317-788-5690
www.dynaloy.com
Contact: Diane Scheele
dscheele@eastman.com
Booth 504
Dynaloy develops, manufactures and markets advanced
cleaning solutions for the semiconductor industry.
Solving our customer’s cleaning challenges has madeDynaloy, a leading supplier of photoresist and residue
removers in Advanced Packaging processes. Dynaloy
specializes in developing innovative cleaning technologies
to meet the stringent requirements of even the mostdemanding applications. As a subsidiary of Eastman
Chemical Company, Dynaloy and Eastman combine
responsiveness, material science expertise and vast
resources to be a world leader in cleaning technologies.

Finetech
560 E. Germann Road, Suite 103
Gilbert, AZ 85297
Phone: 480-893-1630
www.finetechusa.com
Contact: Robert Avila
sales@finetechusa.com
Booth 306
Finetech offers precision bonders for advanced
packaging -- flip chip, laser bars & diodes, photonics
packaging, VCSELs, MEMs, sensors, Chip to Wafer(300mm), and 3Di/2.5D. A high degree of process
flexibility within one bonder makes these systems
ideal for R&D or prototype environments -- thermocompression, thermo-sonic, eutectic, epoxy, ACF &Indium bonding. Automated models are available with
sub-micron placement accuracy. The company also
provides advanced rework systems for today’s mostchallenging devices and applications. Finetech delivers
a flexible approach to customer support and welcomes
the opportunity to create customized, effective solutions
for specific applications.

27Fraunhofer Center for Applied Microstructure
Diagnostics CAM
Heideallee 1906120 Halle (Saale)
Germany
Phone: +49 (0) 345-55 89 130
Fax: +49 (0) 345-55 89 101
www.cam.fraunhofer.deContact: Prof. Dr. Matthias Petzold
matthias.petzold@iwmh.fraunhofer.de
Booth 402
We are a leading service provider of failure diagnostics
and material assessment for industry including
semiconductor technologies, microelectronic
components, microsystems and nanostructured
materials. We consider the entire work flow from
non-destructive defect localization over high precision
target preparation to cutting edge nanoanalytics
supplemented by micro-mechanical testing, finite
element modeling and numerical simulation. We
support cooperation partners in introducing innovative
materials and technologies, improving manufacturing
process steps, securing reliable field use of components,
analyzing field returns, and consequently optimizing
manufacturing yield, product quality, reliability, and cost
efficiency. Due to our close collaboration with leading
microelectronics manufacturers, we are able to support
test- and diagnostics equipment suppliers in exploringand evaluating upcoming markets and future application
fields. We provide innovative hard- and software
components, problem-adapted analysis work flows andindustry-compatible application str
Fraunhofer Institute for Reliability andMicrointegration IZM
Gustav-Meyer-Allee 25
13355 Berlin
Germany
Phone: +49 (0) 30-464-03-100
Fax: +49 (0) 30-464-03-111
www.izm.fraunhofer.deContact : Georg Weigelt
georg.weigelt@izm.fraunhofer.de
Booth 112
Invisible – but indispensable – nowadays nothingworks without highly integrated microelectronics andmicrosystem technology. Reliable and costeffective
assembly and interconnection technologies are thefoundation of integrating these in products. Fraunhofer
IZM, a worldwide leader in the development andreliability analysis of electronic packaging technologies,
provides its customers with tailor-made system
integration technologies on wafer, chip and board level.
Our research also ensures that electronic systems are
more reliable, so that we can accurately predict lifecycle.
FRT of America
1101 S. Winchester Boulevard, L-240
San Jose, CA 95128
Phone: 408-261-2632
Fax: 408-261-1173
www.frtofamerica.com
Contact: Paul Flynn
pflynn@frtofamerica.com
Booth 100
FRT is recognized as a valued partner for non-contact,
optical metrology systems. FRT of America serves
you by providing high-quality automated measuring
tools that fulfill your research, inspection and processverification needs. Delivering increased manufacturing
yield, enhanced productivity, improved quality andproduct performance, because that’s what it’s about at
the end of the day. The MicroProf TTV measures wafer
thickness, TTV, bow and warp for full thickness, thinned
and bonded wafers. The WLI PI is for measuring highaspect ratio TSV and bumped wafers. The CWL IR isfor measuring silicon thickness on bonded wafers. The
MicroSpy Topo DT is a high resolution microscope with
confocal and interferometric measuring modes.

28

Fujitsu Interconnect Technologies Limited(FICT)
250 E. Caribbean Dr.
Sunnyvale, CA 94089
Phone: 408-745-4984
Fax: 408-745-4971
http://jp.fujitsu.com/group/fict/en/
Contact: Hiro Inouehiroyuki.inoue@us.fujitsu.com
Booth 109
Fujitsu Interconnect Technologies Limited (FICT), a
wholly owned company of Fujitsu Limited of Japan,
provides innovative design and manufacturing solutions
for package substrates and printed circuit boards (PCBs)
to meet the needs of its global customer base. FICT’ssolutions enable its customers to migrate to newer,
complex designs, while reducing manufacturing time
and total cost. Multilayer PCB - Advanced technology
high-end printed circuit boards (PCBs) design andmanufacturing for network systems and high-end
servers. FCBGA - Ultra-Thin & High-density wiring
structure, applying core layer free, full build-up, and fullstacked-via technology.
HD Microsystems™, LLC
250 Cheesequake Road
Parlin, NJ 08859
Phone: 800-346-5656 or 512-301-5207
www.hdmicrosystems.com
Contact: Kevin DeMartini
Kevin.T.Demartini@dupont.com
Booths 312 & 314
HD Microsystems is a joint venture company of
Hitachi Chemical and DuPont Electronics specializingin spin-applied polyimide (PI) and polybenzoxazole(PBO) wafer dielectric coatings.HDM will highlight
new polymeric materials as well as innovative process
technologies for WLP and 3D/TSV applications,
including stress buffer materials (SB), redistribution
dielectric layers (RDL), wafer bonding adhesives(temporary and permanent) and interlayer dielectrics(ILD).
Henkel Electronic Materials
14000 Jamboree Rd.
Irvine, CA 91626
Phone: 714-368-8000
Fax: 714-368-2265
www.henkel.com/electronics
Contact: Douglass Dixon
electronics@us.henkel.com
Booth CC5
Henkel offers a complete range of semiconductor
packaging materials designed to meet the requirementsof today’s challenging devices. Our superior technology
known through the leading brands of Ablestik™,
Hysol®, and Multicore® includes die attach pastes,dicing die attach films for stacked package applications,
Wafer Backside Coating™ die attach solders, liquid
encapsulants, package-level underfills, mold compounds,
tacky fluxes and solder spheres.
Heraeus Materials Technology GmbH & Co.
Kg
Heraeusstr 12-14
Hanau 63450
Germany
Phone: +49.6181-359617
Fax: +49.6181-35169617
www.heraeus-contactmaterials.com
Contact: Miriam Elsner
miriam.elsner@heraeus.com
Booth 308
Worldwide Suppliers of Materials for the Electronics
and Semiconductor Market – Heraeus supplies solder
paste, sinter paste, fluxes, soft solder wire, solder
spheres, solder powders, thermally and electricallyconductive adhesives and variety of other adhesives
to the package and component assembly markets.
Moreover, the Business Unit Bonding Wires provides
bonding wires made of gold, aluminum, aluminum alloys
and copper, as well as precious and non-precious metal
ribbons. The Contact Materials Division of Heraeus
offers a wide range of innovative products to address
your contact material requirements.

Hesse Mechatronics, Inc.
225 Hammond Avenue
Fremont, CA 94539
Phone: (408) 436-9300
Fax: (484) 231-3232
www.hesse-mechatronics.com
Contact: Joseph S. Bubel
info@hesse-mechatronics.us
Booth 110
Hesse Mechatronics, a worldwide company based in
Paderborn, Germany, designs and manufactures highspeed fine pitch wedge bonders for production of RF,
microwave, optoelectronic, military and consumer
electronics devices and heavy wire bonders for
production of power electronics and automotive
devices. The company’s fully automatic wedge bonders
handle light and heavy wire applications with aluminumand gold round wire from 12.5 micron (.0005) to
500 microns (.020) in diameter, in addition to ribbon
wire from 6 x 35 microns up to .3 x 2 mm, including
HCR™ (High Current Ribbon). The company’s heavy
wire bonders also handle copper wire and ribbon.
The NEW Bondjet BJ931 High Speed Fully Automatic
Dual-Head Wedge Bonder meets the latest technology
and flexibility demands for automotive and powerelectronics applications.
High Connection Density, Inc. (HCD)
820A Kifer Road
Sunnyvale, CA 94086
Phone: 408-743-9700
Fax: 408-743-9701
www.hcdcorp.com
Contact: Charlie Stevenson
sales@hcdcorp.com
Booth 414
High Connection Density, Inc. (HCD) is a premiersupplier of board-to-board, flex-to-board, andpackage-to-board solderless connectors for BGA,LGA and socket applications. HCD’s SuperButton®
and SuperSpring® technology-based products are theperfect solution for projects requiring high frequency,
high current and low resistance. Designed for
manufacturability, HCD offers its innovative proprietary
technology at competitive prices.
Huntsman Advanced Materials
10003 Woodloch Forest Dr
The Woodlands, TX 77380
Phone: 888-564-9318
Fax: 281-719-4032
www.huntsman.com/advanced_materials
Contact: Doug Ellerbusch
doug_ellerbusch@huntsman.com
Booth 208
Huntsman Advanced Materials is a leading global
supplier of synthetic and formulated polymer systems
for customers requiring high performance materials
which outperform the properties, functionality anddurability of traditional materials. In the electronics
market, we provide advanced organic protective
solutions to build, structure and assemble printed circuitboards and to encapsulate, insulate and bond electricaland electronic components. Our brands, such as
Araldite® adhesive and laminating systems, Probimer®
solder masks and Euremelt® hot melt adhesives, arepioneers in the industry, serving customers for morethan 50 years. Our customers benefit from soundtechnical expertise and products that are tailor-made tomeet their requirements.

Hysitron, Inc.
9625 West 76th Street
Minneapolis MN 55344
Phone: 952-835-6366
Fax: 952-835-6166
www.hysitron.com
Contact: Andrew Romano
aromano@hysitron.com
Booth 508
As the world leader in nanomechanical metrology,
Hysitron® is dedicated to the development of nextgeneration testing solutions for microelectronics
characterization. Hysitron provides innovative solutions
to industry’s most challenging material integration
problems with our comprehensive nanomechanicaltesting suite of techniques and modular metrology
platforms that keep you at the forefront of materials
reliability. Stop by our booth to learn about our exciting
new developments in microelectronics characterizationand for in-depth discussions with our applications
specialists about our latest testing solutions. Hysitronis continuously redefining what is possible for materials
R&D, failure analysis, and process control.
IBM Microelectronics – Packaging
Development
2070 Route 52
Hopewell Junction, NY 12533
Phone: 845-892-0660
Fax: 845-892-6256
www-03.ibm.com/technology/
Contact: Barry Hochlowski
hochlb@us.ibm.com
Booth 410
IBM Microelectronics - a world leader in semiconductor
and packaging technology has formed a Packaging
Joint Development Ecosystem with leading assembly,
materials, and equipment providers. This ecosystemleverages IBM’s research and development resources
with synergistic skills from partner companies to solve
shared challenges and drive industry leadership in
semiconductor flip chip packaging. IBM’s packaging
technologies raise the bar on product performance,
power efficiency, integration and reliability. Advancesin semiconductor device performance and thetransition to environmentally friendly interconnects
drive complexity in the design and implementation of
appropriate packaging solutions. Increased use of multicore processors that drive larger die size, greater I/O
counts and enhanced cooling requirements have madethe co-development of silicon and packaging solutions
essential to the successful implementation of both. It’stime to differentiate your semiconductor packaging
technology….Smarter technology for a Smarter Planet.
IMAT Inc.
12516 NE 95th St., Suite D110
Vancouver, WA 98682
Phone: 360-256-5600
Fax: 360-256-7766
www.imatinc.com
Contact: Eric Feigner
ericf@imatinc.com
Booth: CC2
IMAT is a global source for wafers of all sizes withthermal oxide, various metal thin films, patterned
photoresist and dry films, plated copper, and otherprocesses. Established in 1995, our staff has met theneeds of a wide range of IC manufacturers, equipmentvendors, and research facilities. Metal films include
Ta, Cu, Ti, Al, W, Pt, Ru, Pd, Au, Ag, Co, Ni and Cr,
silicides, and alloys are also available. Photolithography
services include mask design and layout for your custom
applications or you may select from our library of
existing masks. We have established some processes
for 450mm substrate sizes such as metal evaporation,
anneal, and resist coat. We will be incorporating morecapabilities in the near future. Ask us about yourrequirements.

Industrial Technology Research InstituteBldg. 17, No. 195, Sec. 4 Chung Hsing Rd.
Chutung, Hsinchu, Taiwan
Phone: 886 3 5917024
Fax: 886 3 5917193
www.itri.org.tw
Contact: Dr. Robert Lo
lo@itri.org.tw
Booth 111
Industrial Technology Research Institute (ITRI)
celebrates 40 year anniversary in 2013,, is a nonprofit organization conducting in applied research andtechnological services. Electronics and Optoelectronics
Research Laboratories (EOL) is one of the core labs
, devoting to advanced researches in semiconductor
technologies and optoelectronics developments.
EOL has played a key role in Taiwan’s prominentelectronic and optoelectronic industries by staying tuned
with global trends of technology. EOL has successfully
empowered Taiwan and Worldwide partners/
industries in further enhancing their competitiveness in
manufacturing technologies and product developments.
The core competences of EOL are briefly introduced
below:• NVM Technology; • Roll-to-Roll flexible technology &OLED lighting; • Bio-photonic system and 3D Imaging
Technology; • LED Optoelectronic Semiconductor
Technology; • 3D IC/3D Integration & SiP Packaging
Technology on Si/Glass/AlN;• Power packing and Intelligent power Module.
Insidix
24 rue du Drac
Seyssins
France 38 180
Phone: +33 (0)4 38 12 42 80
Fax: +33 (0)4 38 12 03 22
www.insidix.com
Contact: Joe Thomas
joe@zntechnologies.com
Booth 408
TDM (Topography and Deformation Measurement)
is a patented INSIDIX technology that helps thedevelopment engineer increase the reliability of his
products, from simple components to highly complex
packaging, and allows the failure analysis engineer tounderstand more accurately the root causes of failures
observed in operations. The TDM operating system
combines a powerful, internally developed heating/cooling sequence with a sophisticated optical set-up for
3D topography analysis/warpage measurement underthermal stress of all kinds of materials, components
and sub-systems. TDM can impose the same thermal
profiles and cycles on the devices that they will actuallyexperience during the production process and during
normal use. Throughout the thermal cycle, TDM
measures the 3D deformation and warpage related tothe imposed thermal stress, thus revealing faults thatwould likely occur during normal production and use.

Interconnect Systems, Inc.
759 Flynn Road
Camarillo, CA 93012
Phone: 805-482-2870
Fax: 805-482-8470
www.isipkg.com
info@isipkg.com
Booth 201
Interconnect Systems, Inc. (ISI) is a leading providerof advanced packaging and interconnect solutions for
top-tier OEMs in a wide range of industries including
military/aerospace, computing/telecom, medical,
industrial, and automotive. ISI pioneered the conceptof Next Level Integration, an alternative design paththat integrates at the module level rather than thesilicon level, resulting in lower production costs andfaster time-to-market. ISI’s breadth of products includes
miniaturized FPGA systems, high density modules, 3D
and advanced packaging, IC obsolescence adapters, andstandard/custom interconnect solutions.
The company’s in-depth design and processdevelopment knowledge and extensive manufacturing
capabilities allow it to quickly execute on Next Level
Integration projects and thus provide a comprehensive
turnkey solution for its customers.
Invensas2702 Orchard Parkway
San Jose, CA 95134
Phone: 408-324-5121
www.invensas.com
Contact: Mason Woodford
mwoodford@invensas.com
Booth 114
A global leader in semiconductor interconnect solutions,
Invensas invents, productizes and acquires novel
technology to provide broader and more complete
solutions for its customers. The company uses
interconnectology to extend its design capabilities fromchip-level to board module and system-level, innovatingin areas such as mobile computing and communications,memory and data storage, and 3D-IC technologies
J-DEVICES Corporation
1913-2 Fukura Usuki-shi
Oita, Japan
Phone: +81-50-3161-4938 (Japan)
Phone: 408-918-3015 (US)Fax: +81-972-63-3160
www.j-devices.co.jp
Contact: Kazumi Allen
kazumi.allen@j-devices.com
Booth 403
J-DEVICES Corporation is a leading OSAT (Outsourced
Semiconductor Assembly and Test) company, providing
turnkey semiconductor backend services and expanding
service capability with an extremely high growth rate.
We are continuously developing the best assembly
and testing technology to continue achieving globallycompetitive cost and contribute to our customers’
success. Besides various types of general packaging
such as SOP, QFN, QFP, BGA, FBGA, FCBGA, SiP,
PoP, MEMS and CIS packages with best-in-class quality,
WFOP (Wafer level Fan Out Package) is one of ourinnovative milestones aligning to the migration of 3D
packaging in the future. We provide 2D/2.5D/3D
packaging solutions of outstanding performance withcompetitive cost. Let your imagination run with what
and how WFOP will carry into your products.

29

JSR Micro, Inc.
1280 N. Mathilda Ave.
Sunnyvale, CA 94089
Phone: 408-543-8800
Fax: 408-543-8964
www.jsrmicro.com/
Contact: James Chung
jchung@jsrmricro.com
Booth 407 & 409
JSR’s unique THB series of negative tone resists address
the needs of metal plating and bumping processes.
Excellent plating tolerance and ease of stripping allow
for fast processing with excellent exposure throughput
and superior process margins. THB cross-links on
exposure and is developable in standard TMAH yielding
high aspect ratio profiles for film thicknesses from 5 to100um. JSR’s WPR is a thick photosensitive dielectricthat is ideal for redistribution layers, stress buffer layers
and passivation. Available in positive and negative
tone, WPR is patternable and aqueous developable
and provides for low residual stress and low curetemperature.
Kyocera America
1401 Route 52, Suite 203
Fishkill, NY 12524
Phone: 845-896-0480
Contact: Tony Soldano
Tony.Soldano@Kyocera.com
Booth 304
KYOCERA SLC Technologies (KST) merges cuttingedge design with a wide range of semiconductor
packaging technologies to provide advanced routing
technology with thin multilayer structure. We offer
superior substrates for IC packages and high density
circuit boards for high performance, high reliability andgood cost performance.
KST created SHDBU substrates for high-speed
applications with high I/O count flip chip BGA. SHDBU
substrates have high density build-up and CPCORE as acore material CPCORE has features of both multilayer
ceramic technology and multilayer organic technology
and is flexible in routing design for enhanced electricalperformance.
KYOCERA SLC Technologies also provides FC-WSPs
in response to the demand for thin and small substrates
for markets such as digital handset equipment.
Metryx Ltd.
Unit 2 Manor Park
Nailsea Wall Lane, Nailsea
Bristol BS48 4DD
United Kingdom
Phone: +773-418-9916
www.metryx.net
Contact: Mark Berrymark.berry@metryx.net
Booth CC10
Metryx manufactures innovative mass metrology
equipment for use in semiconductor manufacturing.
All microelectronic devices are manufactured througha sequence of steps, adding or removing materials.
Patented technology from Metryx enables any masschange in these ultra-thin steps to be determined with
unprecedented atomic layer accuracy.
The mass response is used to characterize materials
and processes, or is implemented in statistical processcontrol (SPC) of the complete manufacturing sequence.
Mass metrology provides a rapid inline measurementon product wafers enabling an increase in test coveragewith high throughput. Mass as an SPC response
has been adopted by 200mm and 300mm Volume
Manufacturers for advanced technology nodes.

30

Mini-Systems, Inc. (MSI)
20 David Road
North Attleboro, MA 02760
Phone: 508-695-0203
Fax: 508-695-6076
www.Mini-SystemsInc.com
Contact: Craig Tourgeemsithick@mini-systemsinc.com
Booth 404
For over 40 years MSI has been delivering superior
quality products. Absolute tolerances starting at
0.01% and TCRs at ±2ppm/°C. Case Sizes start at
0101. Standard deliveries start in just 2 WEEKS! MSIs
manufactured products consist of precision:· Thin/Thick film Chip Resistors· QPL Resistors to MIL-PRF-55342· MOS Chip Capacitors· Chip Networks· Chip Attenuators· QPL Jumpers to MIL-PRF-32159/Mounting Pads
· Hermetic Packages· Three divisions located in MA.
Applications include Medical implantables, Military,
Aerospace, Microwave/RF and Telecommunications
MJS Designs, Inc.
4130 E. Wood St., Ste. 100
Phoenix, AZ 85040
Phone: 602-437-5068
Fax: 800-445-9442
www.mjsdesigns.com
Contact: Neil Munzinger
nmunzinger@mjsdesigns.com
Booth 212
Turn to MJS Designs for high-quality and accuracy incomplex printed circuit board, engineering design,
CAD layout, prototyping, box / system build, cable
assembly, procurement, volume assembly, test solutions
and fulfillment. MJS Designs is ISO 9001:2000 Certified,
AS9100C Certified (Aerospace) , ISO 13485:2003
Certified (Medical), ITAR Registered and ANSI / ESD
S.20.20-2007 Standard. The team at MJS Designs is
handpicked to provide exceptional customer service
and holds the following credentials; IPC-A-610E
Certified Production Staff, J-STD-001E Certified
Production Staff, IPC / WHMA-A-620 Certified
Mechanical Staff and CID + Certified Designers. From
prototype to production, MJS Designs delivers advanced
electronic manufacturing solutions with the quality andspeed required for today’s demanding applications,timelines and budgets. Join us - Facebook.com/
MJSDesignsInc.
Moldex3D North America
Moldex3D North America Sales & Support
Center
21800 Haggerty Road, Suite 109
Northville, MI, 48167
Phone: 248-946-4570   
Fax: 248-928-2270
www.moldex3d.com
Contact: Kenny Lu
kennylu@moldex3d.com
Booth 211
Moldex3D has been providing the professional CAE
analysis solution for the plastic injection molding
industry since 1995. Moldex3D IC Packaging provides acomplete series of molding solutions that help engineers
to simulate the complex chip encapsulation process,validate mold design, and optimize process conditions.
It helps designers to fully analyze the chip encapsulation
process from filling, curing, cooling, to advanced
manufacturing demands, such as underfill encapsulation,
post-molding annealing, stress distribution, or structural
evaluation. Significant molding problems can bepredicted and solved upfront, which helps engineers
enhance chip quality and prevent potential defects
more efficiently. Moldex3D is committed to provide
the advanced technologies and solutions for industrial
demands, and Moldex3D has extended its worldwide
sales and service network to provide local, immediate
and professional service.

Multitest
3021 Kenneth Street
Santa Clara , CA 95054
Phone: 512-517-2198
www.multitest.com
Contact: Klaus Ruhmer
k.ruhmer@multitest.com
Booth CC3
For more than 30 years Multitest has been a partner
to the international semiconductor industry providing
leading solutions for standard IC and sensor test.
Multitest offers a comprehensive portfolio of test
equipment and accessories that is unique in the industry:gravity, pick & place and strip handlers for standard
IC and sensor test, a broad range of Kelvin, RF andfine pitch contactors based on Cantilever and verticalprobe technology and finally load boards. Multitest“Plug &Yield™” stands for fully integrated and ideallyharmonized set-ups that combine and leverage thestrengths of each component. Multitest’s products
have been awarded with several industry prices. The
latest award was for the in-process test solution for 3D
packages.
NAGASE & CO., LTD. and Nagase ChemteXCO.
5-1, Nihonbashi-Kobunacho, Chuo-ku,
Tokyo, 103-8355 Japan
Phone: +81-3-3665-3300
Fax: +81-3-3665-3950
www.nagase.co.jp/english/index
www.nagasechemtex.co.jp/english/index
Contact: Nobuo Ogura
nobuo.ogura@nagase.co.jp
Booth 113
Nagase ChemteX is a leading company forsemiconductor encapsulant of epoxy resin. Ourline-up products and applications are as follow, NonConductive Paste(NCP) for Fine pitch FC-PKG,
Underfill for Pb-free, Liquid Molding Compound(LMC)
for FO-PKG like e-WLB and Wafer Process
Encapsulated Film(WPEF) for 3D PKG. We candeveloping for the package of Ultra Low K, Cu Post and3D(CoW, TSV and TMV).
NAMICS Technologies, Inc.
2055 Gateway Place, Suite 480
San Jose, CA 95110
Phone: 408-516-4611
Fax: 408-516-4617
www.namics.co.jp/eContact: Tony Ruscignosales@namics-usa.com
Booth 200
NAMICS CORPORATION is a leading source forunderfills, encapsulants, adhesives, and insulating
and conductive materials used by producers ofsemiconductor devices, passive components, and solar
cells. NAMICS subsidiary, DIEMAT, Inc. located in
Byfield, MA, specializes in the development of innovative
thermally conductive adhesives and sealing glasses.
Headquartered in Niigata, Japan with subsidiaries in theUSA, Europe, Taiwan, Korea, Singapore, and China,
NAMICS serves its worldwide customers with enablingproducts for leading edge applications.

NANIUM S.A.
Avenida 1º de Maio 801
4485-629 Vila do Conde
Portugal
Phone: +351 252 24 6301
Fax: +351 252 24 6001
www.nanium.com
Contact: Antonio Barnyantonio.barny@nanium.com
Booth 305
NANIUM is a world-class provider of semiconductor
assembly, packaging and test engineering andmanufacturing services, and a leader in 300mm waferlevel packaging (WLP). The company offers in-housecapabilities for the entire development chain, fromdesign to multiple packaging technologies, and theflexibility to tailor solutions that respond to the most
specific and demanding customer requirements. Since
production start in 2010, more than a quarter billion
eWLB components have been shipped. NANIUM iscontinuously developing new solutions, like System-inPackage (SiP) at the wafer level, to stay at the leadingedge of this technology. Since end of 2012, WLCSP
based on fan-in technologies is complementing theexisting fan-out WLP offer, which targets high pin
count and high performance products, SiPs and 3D
integration.
Newport Corp.
101 Billerica Ave.
N. Billerica, MA 01862
Phone: 978-667-9449
www.newport.com
Contact: Dan Crowley
dan.crowley@newport.com
Booth 104
Newport is a leading supplier of high precision dispense
and assembly equipment for the semiconductor andmicroelectronics industry offering systems for the
manufacture of Microwave, Optical, MCM’s and MEM’s
devices. With over two decades of advanced packaging
application experience, Newport products support
multiple interconnect technologies, including epoxy die
bonding, eutectic attach and flip chip. The ultra-precisionNewport MRSI-M3 with 3 micron accuracy, MRSI-M5
with 5 micron accuracy and MRSI-605 Assembly Work
Cells specialize in thin die handling and 3D packaging
and the Newport MRSI-175Ag Epoxy Dispenser is theleader for high precision conductive epoxy dispensing
including 125 micron dots
Nikon Metrology, Inc.
12701 Grand River Avenue
Brighton, MI 48116
Phone: 810-220-4360
Fax: 810-220-4300
www.nikonmetrology.com
Contact: Cali Schwartzly
Marketing_us@nikonmetrology.com
Booth 98
Nikon Metrology offers the most complete metrology
product portfolio, including X-ray and Computed
Tomography inspection systems and state-of-the-art
vision measuring instruments featuring optical andmechanical 3D metrology solutions. These innovative
metrology solutions respond to the advanced inspection
requirements of manufacturers active in aerospace,electronics, automotive, medical, consumer and otherindustries.

Nordson DAGE
48065 Fremont BoulevardFremont, CA 94538
Phone: 510-683-3930
Fax: 510-933-2966
www.nordsondage.com
Contact: Aram Kardjian
aram.kardjian@nordsondage.com
Booth 416
Nordson DAGE is the market leading providerof award winning test and inspection systems formechanical testing of electronic components and isrecognized as the industry standard. The 4000PLUS
platform compliments the 4000 series test systems, foradvanced bondtesting such as wire, lead and ribbon pull,
BGA sphere and package fatigue, PCB 3 point bend
testing, hot bump pull for PCB pad cratering testingin accordance with IPC9708, and shear testing. The
4000HS high speed bondtester, capable of testing solder
bumps in high speed shear and high speed cold bumppull modes, is becoming a viable alternative to board
level drop testing. The 4000HS, in addition to total andfractional values , provides bond energy results, proving
invaluable for failure mode analysis the detection of leadfree brittle fractures.

PAC TECH USA – Packaging Technologies,Inc.
328 Martin Avenue
Santa Clara, CA 95050
Phone: 408-588-1925 x 246
Fax: 408-588-1927
www.pactech.com
Contact: Richard McKee
sales@pactech-usa.com
Booth 301
Packaging Technologies GmbH (PAC TECH), a groupmember of NAGASE & CO., Ltd., is comprised of two
unique business units:

NTK Technologies, Inc.
3979 Freedom Circle Drive, Suite 320
Santa Clara, CA 95054
Phone: 408-727-5180
Fax: 408-7275076
www.ntktech.com
Contact: Mariel Stoops
scdinfo@ntktech.com
Booth 116
NTK is a global leader in Organic and Ceramic
Packaging. NTK’s Packaging is aligned to support
custom designs with varying volume requirements.
Our package design support is geared to stream-line
electrical and thermal design optimization. Materials
include HTCC, LTCC, and a variety of Organic andLaminate Materials and Technologies. NTK’s provensimulation tools have enabled optimum package designfor high speed communications in the 10G, 40G, 100G,and soon approaching 400G for both, ceramic andorganic packages. Advanced ceramic-based applications
available for Space Transformers for Probe, CCD and
CMOS Image Sensors.

Headquartered in Nauen, Germany, PAC TECH
has 100% subsidiaries: PAC TECH USA - Packaging
Technologies Inc. (Silicon Valley, USA) & PAC TECHASIA Sdn. Bhd. (Penang, Malaysia).

Ormet Circuits / NSCC
6555 Nancy Ridge Drive #200
San Diego, CA 92121
Phone: 858-831-0010
Fax: 858-455-7108
www.ormetcircuits.com
Contact: Peter Matturri
Support@ormetcircuits.net
Booth 516
Ormet and NSCC welcome you to visit exhibit
516 introducing new products for semiconductors
interconnect markets.
Ormet Circuits, Incorporated (Ormet) is a privately
held company, engaged in the design, manufacture, andsale of conductive pastes for use in the manufactureof advanced electronic devices. Ormet pastes arelead-free, highly electrically and thermally conductive
and provide good intermetallic joints at relatively low
temperatures.
Nippon Steel & Sumikin Chemical Co., Ltd., as a core
member of the Nippon Steel & Sumitomo Metal
Corp. Group, is the key industry of chemical products
fields, which are the products of coal tar chemicals,
petroleum chemistry, gasses, synthetic resins andelectronics materials. We have developed a high degreeof expertise in the application of these products to
respond a huge variety of needs in the industrial society.

Advanced Packaging Equipment Manufacturing:
Automatic wet chemical lines for high volume
electroless NiAu & NiPdAu bumping (PacLine 300
A50), laser solder jetting equipment (SB2-Jet), waferlevel solder ball transfer systems (Ultra-SB2), and laserassisted flip-chip bonders (Laplace).
Wafer Level Packaging & Bumping Services:
Subcontract wafer bumping with electroless Ni/Auor Ni/Pd under-bump-metallization (UBM) for FC or
WLCSP solder bumping, as well as NiPdAu for wirebonding. PAC TECH also offers AOI, X-Ray, RDL,
Thinning, Backmetal, Laser Marking, Dicing and Tape
& Reel.

Palomar Technologies
2728 Loker Ave.
West, Carlsbad, CA 92010
Phone: 760-931-3600
Fax: 760-931-5191
www.palomartechnologies.com
Contact: Jessica Sylvester
jsylvester@bonders.com
Booth CC6
Palomar Technologies, a former subsidiary of Hughes
Aircraft, is the global leader of automated high-accuracy,
large work area die attach and wire bond equipment
and precision contract assembly services. Customers
utilize the products, services and solutions from Palomar
Technologies to meet their needs for optoelectronic
packaging, complex hybrid assembly and micron-levelcomponent attachment.
Palomar Technologies Assembly ServicesTM(“Assembly Services”), located in Carlsbad, CA, is thecontract assembly, process development, test andprototyping division of Palomar Technologies. AssemblyServices provides process expertise with high-precision
die attach, wire bond and component placement
services, offering its customers an alternative route tomeet complex packaging needs for without investing in
capital equipment.
PURE TECHNOLOGIES
177 US Hwy # 1, No. 306
Tequesta, FL 33469 USA
Phone: 404-964-3791
Fax: 877-738-8263
Int’l Fax: +1-973-273-2132
www.puretechnologies.com
Contact: Jerry Cohn
jerry@puretechnologies.com
Booth 307
Pure Technologies manufactures low (0.02, 0.01 cph/cm2), ultra-low (0.005, 0.002 cph/2) and super ultralow (<0.001 cph/cm2) alpha emitting Tin (Sn), LeadFree (including all SAC) alloys, Pb and Pb/Sn alloys.
These ALPHALO® products are available in various
shapes and sizes – ingots, anodes, slugs, pellets, foil,rods, bricks, PbO and SnO powder, etc. for wafer-levelpackaging, interconnects, and sphere and powder/paste
manufacturing. ALPHA-LO® reduces or eliminatessoft errors from alpha particle emissions from solders,enhances performance reliability and reduces corporate
liability. All materials are guaranteed and certified to be
at secular equilibrium and are tested and retested overtime before shipping to insure that the alpha emission
rate is stable and will not increase over time.

31QualiTau
950 Benecia Ave
Sunnyvale CA, 94085
Phone: 408-522-9200
Fax: 408-522-8110
www.qualitau.com
sales@qualitau.com
Booth 203
QualiTau offers a variety of reliability and parametric
test equipment for the characterization anddevelopment of new materials used in the manufactureof Integrated Circuits. The DSPT 9012 (Desktop
Semiconductor Parametric Tester) is a PC Controlled
SMU test instrument built specifically for semiconductor
device characterization and testing. The MIRA, Infinity,
ACE, and Multi-Probe reliability test systems perform
tests for Hot Carrier Injection, Dielectric Breakdown,
Solder Bump at up to 8 Amps, and Electromigration attest temperatures up to 450C.
Quik-Pak
10987 Via Frontera
San Diego, CA 92127
Phone: 858-674-4676
Fax: 858-674-4681
www.icproto.com
Contact: Casey Krawiec
casey@icproto.com
Booth 311
Quik-Pak, a division of Delphon, provides IC packaging
and assembly services. The company’s newest offering
is its OmPP package. These pre-molded QFN packages
are cost-effective, come in a variety of sizes and are
ideal for prototype or production volume applications.
Quik-Pak also specializes in a variety of services thattogether provide a full turn-key packaging and assembly
solution including wafer preparation, die/wire bonding,remolding and marking/branding. Custom assembly
services are also offered for Flip Chip, Ceramic
Packages, Chip-on-Board, Stacked Die, MEMS, etc
Royce Instruments, Inc.
831 Latour Court, Suite C
Napa, CA 94558
Phone: 707-255-9078
Fax: 707-255-9079
www.royceinstruments.com
Contact: Greg Herasgheras@royceinstruments.com
Booth 102
Royce Instruments is your preeminent supplier of Bond
Testing and Die Sorting equipment. The new 600
Series of Bond Test Instruments brings unparalleled
networking capability and scalability to the bond test
market. With a choice of 3 bond testers, Royce offers
an instrument solution to meet the evolving needs ofmanufacturers and institutions worldwide. Royce Die
Sorters (AutoPlacer MP300 and DE35-ST) offer fullyautomatic and semi-automatic die sorting solutions fortoday’s challenging applications, including die as small as
200 um square or 50 um thick. For sensitive products
where the device surface cannot be touched (i.e.
MEMS), non-surface contact is available that grips thedevice from the edges. With quick tooling change-outs,
wafer mapping, and die inverter and inspection options,
Royce Die Sorters are ideal for high mix, medium
volume applications.

32

RTI International - Center for Materials &Electronic Technologies
3040 Cornwallis Road, Adv Tech Bldg
P.O. Box 12194
RTP, NC 27709
Phone: 919-248-1801
www.rti.org/microsystem
Contact: Alan Huffman
huffman@rti.org
Booth 310
RTI International’s Center for Materials and Electronic
Technologies is a world leader in advanced interconnect
and packaging technologies conducting R&D in sensors
and actuators, electronic material characterization,and novel device microfabrication. RTI provides stateof the art wafer bumping and WLP technologies,
supporting small- and mid-volume customers as well as
developmental applications. A recognized leader in 3D
integration, RTI works with commercial, government,
and academic clients to develop and implement
solutions. Fully integrated fabrication and analyticalfacilities allow RTI to support a diverse project base,from process development, proof of concept andprototyping, to small-scale production. The Centeris staffed with full time engineers and researchersdeveloping new technologies and solutions. RTI is a
non-profit research institute offering innovative research,technical expertise, and fabrication capabilities togovernments and businesses worldwide.
Rudolph Technologies
One Rudolph Road (PO Box 1000)
Flanders, NJ 07836
Phone: 973-691-1300
Fax: 973-691-4863
www.rudolphtech.com
info@rudolphtech.com
Booth CC8
Rudolph Technologies is a leader in the design,development, manufacture and support of defectinspection, advanced packaging lithography, processcontrol metrology, and data analysis systems andsoftware used by semiconductor device manufacturers
worldwide. Rudolph’s product suite offers hardware
and software solutions for the demanding requirementsof the advanced packaging market, including 2D/3Dbump inspection, RDL and overlay metrology, and alithography stepper specifically designed for the backend. Turn data into useful information with Rudolph’s
proprietary software solutions including run-to-run
control, fault detection and classification and yield
management systems.
Semiconductor Equipment Corporation
5154 Goldman Avenue
Moorpark, CA 93021
Phone: 805-529-2293
Fax: 805-529-2193
www.semicorp.com
Contact Name: Don Moore
dmooresec@aol.com
Booth 205
Semiconductor Equipment Corporation Produces manual, semiautomatic, and automatic
equipment for the Photonics, Semiconductor, MEMS,
SMT and Hybrid Industries. Products include flip-chipbonders, die bonders, diode laser bonders, eutectic
die bonders, manual pick & place, die rework, dicing
tape, manual and automatic dicing tape applicators,
heat release tape, backgrinding tape, backgrinding tapeapplicators, and die ejectors

SET – Smart Equipment Technology
131, impasse Barteudet
74490 Saint Jeoire, France
Phone: +33 (0) 450-35-83-92
Fax: +33 (0) 450-35-88-01
www.set-sas.fr
Contact: Gilbert Lecarpentier
glecarpentier@set-sas.fr
Booth 313
SET, Smart Equipment Technology (Former Suss
MicroTec Device Bonder Division) is a world leading
supplier of High Accuracy Assembly and Nano Imprint
Lithography Solutions. As a supplier of semiconductor
equipment dedicated to high-end applications for over
30 years and with more than 300 Device Bonders
installed worldwide, SET is globally renowned for theunsurpassed bonding accuracy (± 0.5 µm) and the highflexibility of its die and flip-chip bonders. SET’s productportfolio ranges from manual loading versions to fully
automated operation. The SET systems cover a wide
range of bonding applications and offer the uniqueability to handle both fragile and small components onto
substrates up to 300mm.
Shin-Etsu MicroSi, Inc.
10028 S. 51st Street
Phoenix, AZ 85044
Phone: 480-893-8898
Fax: 480-893-8637
www.microsi.com
info@microsi.com
Booth 315
Shin-Etsu Microsi, Inc. is a wholly owned subsidiaryof Shin-Etsu Chemical Ltd. Shin-Etsu MicroSi is aworld class supplier of packaging materials for thesemiconductor industry. With a global support
network, which includes Sales Engineers, R&D,
Manufacturing, Quality Assurance, and Logistics, we areable to quickly develop and provide new technologies
to benefit our customers. This allows our clients
to meet their ever changing technical, commercial
and environmental needs by implementing Shin-Etsu
MicroSi’s technology. Shin-Etsu MicroSi is known for
supplying high performance Thermal Interface Materials,
Underfills, Molding Compounds, High Purity Silicone
Encapsulants, and Die Attach Materials.
Shinko Electric America
2880 Zanker Road, Suite 204
San Jose, CA 95134
Phone: 408-232-0493
Fax: 408-955-0368
www.shinko.co.jp
Contact: Gary Ikarigary.ikari@shinko.com
Booth 206
Shinko Electric Industries Co., LTD. is a leading
manufacturer of a wide variety of materials usedin the packaging of integrated circuits such as:
Organic Substrates, Leadframes, TO-Headers andHeatspreaders. With headquarters located in Nagano,
Japan and offices worldwide, Shinko strives to provide
the ultimate in service and solutions for our customers.
For more about Shinko please visit our website atwww.shinko.com.

Sonnet Software
100 Elwood Davis Road
North Syracuse, NY 13212
Phone: 1-877-7SONNET or 315-453-3096
Fax: 315-451-1694
www.sonnetsoftware.com
Contact: Robert O’Rourke
info@sonnetsoftware.com
Booth 415
Sonnet® Software provides high-frequency
electromagnetic analysis software. The Sonnet
Suites extracts electromagnetic model extraction of
predominately 3D planar passive circuits and antennas,
including RFIC, MMIC, co-planar waveguide, RF PCB(single and multiple layers), RFID and RF packages
incorporating any number of stratified dielectric layerswith embedded planar metal traces. Sonnet will
premiere the latest software release, Sonnet Suites
Release 14, featuring technology layers for design flow
integration, faster simulations, EDA framework interface
enhancements, and more.
SPTS Technologies
1150 Ringwood Court
San Jose, CA 95131-1726
Phone: 408-571-1400
www.spts.com
Contact: Lisa Mansfieldenquiries@spts.com
Booth 101
SPTS Technologies designs, manufactures, sells, andsupports etch, PVD, CVD and thermal wafer processing
solutions for the MEMS, advanced packaging, LEDs, highspeed RF on GaAs, and power management device
markets. With manufacturing facilities in Newport,
Wales, Allentown, Pennsylvania, and San Jose,
California, the company operates across 19 countries
in Europe, North America and Asia-Pacific. For more
information about SPTS Technologies, please visit www.
spts.com
STATS ChipPAC
47400 Kato Road
Fremont, CA 94538
Phone: 510-979-8000
Fax: 510-979-8001
www.statschippac.com
Contact: Lisa Lavin
Lisa.Lavin@statschippac.com
Booth 217
STATS ChipPAC is a leading service provider ofsemiconductor design, wafer bump, probe, packaging
and test solutions for the communications, digitalconsumer and computing markets. With advanced
process technology and a global manufacturing presence
spanning Singapore, South Korea, China, Malaysia andTaiwan, STATS ChipPAC provides innovative and costeffect semiconductor solutions. STATS ChipPAC has
a leadership position in advanced package technology
such as fan-in and fan-out wafer level packaging, flip
chip interconnect, Through Silicon Via, 2.5D and 3D
integration to meet the increasing market demand
for next generation devices with higher levels of
performance, increased functionality and compact sizes.

SUSS MicroTec Inc.
A SÜSS MicroTec AG Company
430 Indio Way, Sunnyvale CA 94085
Phone: 408-940-0300
Fax: 408-940-0350
www.suss.com
Contact: Heike Mueller
heike.mueller@suss.com
Booth 117
With more than 60 years of engineering experience
SUSS MicroTec is a leading supplier of processequipment for microstructuring in the semiconductor
industry and related markets. Our portfolio covers acomprehensive range of products and solutions forbackend lithography, wafer bonding and photomask
processing, complemented by micro-opticalcomponents.
SUSS MicroTec provides cost-effective solutions withunsurpassed quality and cutting-edge technology,
enabling our customers to maximize yield at highthroughput thus reducing cost of ownership.
In close cooperation with research institutes andindustry partners SUSS MicroTec contributes to theadvancement of next-generation technologies such as
3D Integration and Nonoimprint Lithography as well as
key processes for WLP, MEMS and LED manufacturing.
With its global infrastructure for applications and service
SUSS MicroTec supports more than 8,000 installedsystems worldwide.
Tamar Technology
996 Lawrence Drive #202
Newbury Park, CA 91320
Phone: 805-480-3358
Fax: 805-498-7644
www.tamartechnology.com/
Contact: Russ Dudley
rdudley@tamartechnology.com
Booth 210
Tamar Technology develops and manufacturers highspeed non-contact metrology solutions for 3DIC
advanced packaging and related processes for MEMS,CMOS image sensors, compound semiconductors,
LED, and other market areas.
Tamar’s proprietary sensor technology offers maximum
flexibility and includes their Optical Stylus Probe (OSP),
Wafer Thickness Sensor (WTS), and Visible Thickness
Sensor (VTS) to support a variety of applications.
The measurement capabilities include through siliconvia (TSV) depth with unlimited aspect ratio, wafer
thickness and total thickness variation (TTV) for single
and multi-layer wafers, remaining silicon thickness (RST),
wafer shape, thin Si thickness, thick films and polymer
thickness, and other critical measurement requirements.
Tamar’s WaferScan system is modular in design and canbe configured for semi or fully automated operation forprocess development or HVM monitoring.

TechSearch International Inc.
4801 Spicewood Springs Rd., Suite 150
Austin, TX 78759
Phone: 512-372-8887
Fax: 512-372-8889
www.techsearchinc.com
Contacts: E. Jan Vardaman, Becky Travelstead
tsi@techsearchinc.com
Booth CC7
TechSearch International, Inc. has a 25-year historyof market and technology trend analysis focused on
semiconductor packaging, materials, and assembly.
Research topics include WLP, FC, CSPs, BGAs, 3D ICs
with TSVs, stacked die CSPs, and System-in-Package(SiP), embedded components, microvia substrates, LED
assembly, and Pb-free manufacturing. In conjunction
with SavanSys Solutions, wire bond, flip chip, WLP, and
3D IC trade-off cost models are offered. TechSearchInternational professionals have an extensive network ofmore than 15,000 contacts in North America, Asia, andEurope and travel extensively, visiting major electronics
manufacturing operations and research facilities
worldwide.
Teledyne Microelectronics
12964 Panama Street
Los Angeles, CA 90066
Phone: 310-574-2082
www.teledynemicro.com
Contact: Harry Kellzi
microelectronics@teledyne.com
Booth 103
Teledyne Microelectronics is a full service
microelectronics contract manufacturer offering
innovative approaches in high density packaging
and testing of microcircuits, multichip modules andmultichip assemblies. In both our facilities in Los
Angeles, California and our future production facility
in Lewisburg, Tennessee, we specialize in high density
microminiature devices utilizing the latest advanced
packaging techniques. Areas of high expertise include
PBGA, 3D stacking, RF/microwave packaging design
and assembly as well as optoelectronics XCVRs,
analog/digital circuits.
Tokyo Ohka Kogyo Co., Ltd.
TOK America, Inc.
190 Topaz St.
Milpitas CA 95035
Phone: 408-956-9901
Fax: 408-956-9995
www.tok.co.jp/en/index.php
Contact:Yoshi Arai
yoshi.arai@tokamerica.com
Booth 202
For over 50 years, TOK has been supplying superior
quality chemicals and equipment to the microelectronics
and semiconductor manufacturers of the world. TOK
is now offering materials and equipment to enablefabrication of 3DIC with TSVs. These products include
photoresists for plating (Au, Ni, Cu, Pb/Sn, SN/Ag),
photo definable insulators, and other materials targeted
for TSV, RDL, and MEMS applications. Please visit ourbooth to learn more about TOK’s products and how
TOK can help you solve your most challenging advanced
packaging requirements.

33

Toray Engineering Co., Ltd.
1-45,Oe 1-chome, Shiga,
520-2141 Japan
Phone: +81-77-544-6221
Fax: +81-77-544-1940
www.toray-engl.co.jp
Toray Engineering Co., Ltd.
411 Borel Avenue, Suite 520
San Mateo, CA 94402
Phone: 408-313-2408
Contact: Kyoji Ishikawa
kyoji_ishikawa@toray-eng.co.jp
Booth 302
Toray Engineering Co., Ltd provides Flip Chip
Bonding Equipment for Semiconductor Packaging (FC2000), Optoelectronics (OF2000) and LCD devices(CL2000FW, OS2000). Also, Vacuum Encapsulation
Equipment (VE500) and various Flexible substrates(TCP,interposer) manufacturing equipment such as
resist coater, proximity exposer, etching, developing line
are available.
Toray International America
411 Borel Avenue, Suite 520
San Mateo, CA 94402
Phone: 650-341-7152
Fax: 650-341-0845
www.toray.com
www.toray.co.jp/english/electronic
Contact: Hiroyuki Niwa
h.niwa@toray-intl.com
Booth 108
Toray Industries is a leading provider for Non-Conductive Film (NCF) for flip chip packages. Toray’s
unique polyimide and film processing technologies
provide excellent reliability and performance which
are already proven in the market. For over 3 years
Toray’s NCF has been used for mass production.
For more information on Toray’s products visit
www.toray.co.jp/english/electronic
Torrey Hills Technologies, LLC
6370 Lusk Blvd., Suite F-111
San Diego, CA 92121
Phone: 858-558-6666
Fax: 858-630-3383
www.torreyhillstech.com
Contact: Joyce Zhang
yzhang@torreyhillstech.com
Booth 207
Torrey Hills Technologies is a California based
manufacturer of tungsten-copper, molybdenum-copper,
Cu/Mo/Cu and Cu/Mo70Cu/Cu heat sinks commonlyused in the electronics industry. These products havehigh thermal conductivity and provide excellent CTE
matches. The company is also distributor of conveyor
belt furnaces, including fast fire and infrared furnaces thatcan work in a variety of atmospheres for drying, firing,brazing and many other applications. They are widelyused in PCB assembly, surface mount technology,
semiconductor packaging and solar cell processing
industries. Torrey Hills Technologies has been an INC
500|5000 for 4 consecutive years.

Towa Corporation
350 Woodview Avenue
Suite 200
Morgan Hill, CA 95037
Phone: 480-779-4440
Fax: 480-779-4413
www.towajapan.co.jp
Contact: LLoyd Tripp
ltripp@towa-usa.com
Booth 213
Towa Corporation is the market leader in providing
leading edge molding solutions to the semiconductor
industry. Towa proudly offers the latest compression
mold solutions for advanced applications such as wafer
level molding, large panel molding, stacked die, TSV
and Molded Underfill and LED’s. Towa’s compression
mold systems have proven to be the most costeffective, technologically advanced solutions for today’s
demanding applications. Towa also continues to be theleader in transfer mold systems for MCM, BGA andother semiconductor, automotive, medical packaging
applications. Towa has over 30 years of transformativetechnological leadership to support all of your packaging
needs.
Triton Micro Technologies, Inc.
1840 East River Road, Suite 201
Tucson, AZ 85718
Phone: 520-209-2475
Fax: 520-838-6027
www.tritonmicrotech.com
Contact: Steve Annassannas@tritonmicrotech.com
Booth 120
Triton Micro Technologies is the leader in the design
and manufacture of high-performance 2.5D and 3D
Through Glass Via (TGV) interposers.
As we rapidly approach the barrier and performance
limits of silicon, the need increases for a greater numberof components in smaller package areas and the needfor non-silicon based materials to better support thisnext generation assembly.
Triton’s proprietary technology offers faster cycle times,
KGD testing at higher packaging integration levels andthe lowest cost/unit in the marketplace.
USHIO America
5440 Cerritos Ave
Cypress, CA 90630
Phone: 800-838-7446
Fax: 800-776-3641
www.ushioamerica.com
Contact: Toru Fujinami
tfujinami@ushio.com
Booth 118
Ushio America, a leading global supplier ofsemiconductor fabrication equipment, subsystems
and components, has engaged in development,
manufacturing and sales in a wide range of productfields. As a world premier photolithography light source
provider, the Ushio Group leverages the industry’s
most advanced development capabilities to meetthe increasingly sophisticated and divergent productrequirements of the global semiconductor industry.
Ushio offers wide range lithography systems, including
the full-field projection exposure equipment, UX43Di FFPL300, WLP stepper UX7-3Di STEP300 and
stepper for organic substrate, UX5-3Di STEP500.
Subsystems and components solutions for Nano
Imprints Lithography templates cleaning subsystems,
mask cleaning subsystems, UV LED components, EUV
Lithography Source subsystems as well as the industrybenchmarked superior UV lamps are also available.

34

XIA LLC
31057 Genstar Rd.
Hayward, CA 94544
Phone: 510-401-5760
Fax: 510-401-5761
www.xia.com
Contact: Brendan McNally
bmcnally@xia.com
Booth 512
XIA LLC manufactures the UltraLo-1800, a next
generation alpha particle counter designed to measure
the alpha particle emissivity of solid materials. The
UltraLo-1800 is a revolutionary new design for ultralow background alpha particle counters that employs
the patented technique of electronic backgroundsuppression to drive achievable background rates to
0.0001 alphas/cm2/hr and below. This is a factorof 50 or more better than can be achieved by theconventional proportional counter systems that are
currently available. With the UltraLo-1800, it becomesfeasible to measure samples having emissivities in the0.001 to 0.0005 alphas/cm2/hr (ULA) range in fewer
than 10 hours, and to measure emissivities below
0.0005 alpha/cm2/hr (sub-ULA) in fewer than 100
hours.
XYZTEC
36 Balch Ave
Groveland, MA 01834
Phone: 978-880-2598
www.xyztec.com
Contact: Tom Haley
tom.haley@xyztec.com
Booth CC1XYZTEC offers the most flexible bond testing platform
on the market today…..The Condor Sigma! This system
offers up to 6 different sensors that are mounted ona revolving measurement unit (RMU)….no more
cartridge changes and the inherent wear problems
associated with them. The Sigma series features a single
platform with multiple test capabilities allowing endusers the added flexibility of performing many types oftests all in one system. In addition to standard bondtesting applications such as wire pull, ball shear and die
shear, the Condor series has the capability to perform
automated bond tests with pattern recognition, peel
testing, push testing, high impact testing, fatigue testing,lead fatigue, lid torque, stud pull, automated nondestruct bond pull and bend testing. The Sigma softwarewith fully integrated SPC is easy to use, comprehensive
and flexible.
Yield Engineering Systems, Inc.
203-A Lawrence Drive
Livermore, CA 94551
Phone: 925-373-8353 or 1-888-YES-3637
Fax: 925-373-8354
www.yieldengineering.com
Contact: Bill Moffat
bmoffat@yieldengineering.com
Booth 209
Yield Engineering Systems (YES) provides a wide
variety of processing equipment including high reliability
polymer processing tools for WLP type processes
and plasma systems for underfill treatment. YES
manufactures quality equipment for the Semiconductor,
MEMS, Photovoltaic, FPD, Medical, Nanotech industries
and more. Our tool line features high temperature
vacuum cure ovens, silane vapor deposition systems andplasma etch/clean tools. Our products are used for
precise surface modification, surface cleaning, underfill
processing and thin film coating of semiconductor
wafers, semiconductor and MEMS devices, biosensors
and medical slides.
Applications include high vacuum applications for MEMS,
low-k dielectric repair, polyimide and BCB bake, copper
anneal, anti-corrosive coating, photoresist adhesion or
stripping, silane/surface adhesion promotion, MEMS
coating to reduce stiction and image reversal.

YOLE DEVELOPPEMENTLe Quartz – 75 cours Emile Zola
69100 Lyon-Villeurbanne
FRANCE
Phone: +33-472-83-01-80
Fax: +33-472-83-01-83
www.yole.fr
Contact: Camille Favre
favre@yole.fr
Booth 510
Yole Développement has grown to become a groupof companies providing market research, technology
analysis, strategy consulting, media in addition tofinance services. With a solid focus on emerging
applications using silicon and/or micro manufacturing
Yole Développement group has expanded toinclude more than 40 associates worldwide covering
MEMS, MedTech, Advanced Packaging, Compound
Semiconductors, Power Electronics, LED, andPhotovoltaics.
CUSTOM STUDIES
Market data, market research and marketing analysis;
Technology analysis; Reverse engineering and reverse
costing; Strategy consulting; Corporate Finance Advisory
TECHNOLOGY & MARKET REPORTS
Collection of reports; Players & market databases;
Manufacturing cost simulation tools; Component
reverse engineering & costing analysis
MEDIA
Critical news, Bi-weekly: Micronews, the magazine;
In-depth analysis & Quarterly Technology Magazines:
MEMS Trends– 3D Packaging – iLED – Power Dev’;
Online www.i-micronews.com; Exclusive Webcasts

Zeon Corporation / Zeon Chemicals L.P.
5 Centerpointe Drive, 4th Floor, Suite 401
Lake Oswego, OR 97035
Phone: 971-204-0245
Fax: 971-204-0240
www.zeon.co.jp/business_e/enterprise/imagelec/
imagelec.html
www.zeonchemicals.com
Contact: Dr. Toshiko Jimbo
jimbo@zeonchemicals.com
Booth 215
Zeon Corporation, a leading Japanese technology
polymer company, and subsidiary Zeon Chemicals
L.P., USA have developed two innovative state-of-theart packaging materials: 1) “Ultra-Low Loss Build-Up
Film” used for Build-Up substrate for IC packages,
GPU, WLP, Si Interposer and any application requiringsuperior electrical properties, and 2) “Ultra-Low Loss
PCB Materials” low-loss laminate for both high k andlow k applications such as milli-wave radars, high-speed
servers and circuits, and RF/mobile applications fortechnology leading devices.

Zymet, Inc.
7 Great Meadow Lane
E. Hanover, NJ 07936
Phone: 973-428-6245
Fax: 973-428-5244
www.zymet.com
Contacts: Kelly Nostrame and Karl Loh
info@zymet.com
Booth 316
Adhesives and encapsulants for electronics andoptoelectronics assembly. Products include electricallyconductive and thermally conductive adhesives, ultralow stress adhesives, ACP’s and NCP’s, UV curable
glob top encapsulants, and underfill and reworkable
underfill encapsulants for flip chips, WLP’s, CSP’s,
BGA’s, and POP’s.

Ziptronix
800 Perimeter Parkway, Suite B
Morrisville, NC 27560
Phone: 919-459-2400
Fax: 919-459-2401
www.ziptronix.com
Contact: Kathy Cookk.cook@ziptronix.com
Booth CC9
Ziptronix is a pioneer in the development of lowtemperature direct bond technology for a variety
of semiconductor applications, including backsideilluminated (BSI) sensors, RF front-ends, pico projectors,
memories and 3D integrated circuits. Its patented,
scalable 3D-integration technology, including ZiBondTM
and DBI®, provides the lowest-cost bonding solution
for 3D technology enabling size reduction, yieldenhancement, lower production costs and power
consumption, and increased system performance. The
company holds thirty-nine U.S. patents and twentyeight international patents in nine foreign countries
and Europe and has more than forty-five U.S. andinternational patent applications pending. Ziptronix
licenses its technology throughout the semiconductor
supply chain, including OEMs, IDMs and fabrication
facilities, and operates a back-end-of-line R&D facility
with 6,000 square feet cleanroom space in North
Carolina.

35

2013 Executive
Committee

General Chair
Wolfgang Sauter
IBM Corporation
wsauter@us.ibm.com+1-802-769-3634
Program Chair
Beth Keser
Qualcomm Technologies, Inc.
beth@qti.qualcomm.com+1-858-658-3332
Assistant Program Chair
Alan Huffman
RTI International
huffman@rti.org+1-919-248-9216
Sponsorship Chair
Jr. Past General ChairDavid McCann
GLOBALFOUNDRIES
david.mccann@globalfoundries.com+1-518-222-6128
Sr. Past General Chair
Rajen DiasIntel Corporation
rajen.c.dias@intel.com+1-480-554-5202

Advanced Packaging
Chair
Joseph W. Soucy
Draper Laboratory
jsoucy@draper.com+1-617-258-2953
Assistant Chair
Raj N. Master
Microsoft Corporation
rajm@microsoft.com+1-650-693-0849
Daniel Baldwin
Engent, Inc.
Rozalia Beica
LAM Research AG
Christopher Bower
Semprius, Inc.
Jianwei Dong
Dow Electronic Materials
Paul M. Harvey
IBM Corporation

Assistant Chair
Scott Savage
Medtronic Microelectronics Centerscott.savage@medtronic.com+1-480-303-4749
Jo Caers
Royal Philips
Sridhar Canumalla
Microsoft Corporation
Tim Chaudhry
Broadcom Corporation
Tz-Cheng Chiu
National Cheng Kung University
Darvin R. Edwards
Texas Instruments, Inc.
Deepak Goyal
Intel Corporation
Vikas Gupta
Texas Instruments
Dongming He
Qualcomm Technologies, Inc.
Toni Mattila
Aalto University

Altaf Hasan
Intel Corporation

Finance Chair
Pat Thompson
Texas Instruments, Inc.
patrick.thompson@ti.com+1-214-567-0660

Donna M. Noctor
Siemens Industry, Inc.

Erik Jung
Fraunhofer IZMJohn H. L. Pang
Nanyang Technological University

Sam Karikalan
Broadcom Corporation

S.B. Park
Binghamton University

Publications Chair
Steve Bezuk
Qualcomm Technologies, Inc.
sbezuk@qti.qualcomm.com+1-858-651-2770

Beth Keser
Qualcomm Technologies, Inc.

Lakshmi N. Ramanathan
Microsoft Corporation

Young-Gon Kim
IDT

Ephraim Suhir
University of California, Santa Cruz

Publicity Chair
Eric D. Perfecto
IBM Corporation
perfecto@us.ibm.com+1-845-894-4400

John Knickerbocker
IBM Corporation

Jeffrey Suhling
Auburn University

Jeffrey A. Knight
Elliott Manufacturing

Dongji Xie
NVIDIA Corporation

John H. Lau
ITRIAssembly & Manufacturing
Technology
Chair
Paul Houston
Engentpaul.houston@engentaat.com+1-678-990-3320 ext. 229

Exhibits Chair
Bill Moody
B. Moody & Associates
b.o.moody@ieee.org+1-302-478-4143

S. W. Ricky Lee
Hong Kong University of Science andTechnology

Web Administrator
Henning BraunischIntel Corporation
braunisch@ieee.org+1-480-552-0844

Luu T. Nguyen
Texas Instruments

Professional Development
Courses Chair
Kitty Pearsall
IBM Corporation
kittyp@us.ibm.com+1-512-286-7957

Peter Ramm
Fraunhofer EMFT

Arrangements Chair
Lisa Renzi
Renzi & Company, Inc.
lrenzi@renziandco.com+1-703-863-2223
CPMT Representative
C. P. Wong
Georgia Institute of Technology
cp.wong@mse.gatech.edu+1-404-894-8391

36

2013 Program
Committee

Raj Pendse
STATS ChipPAC, Inc.

Subhash L. Shinde
Sandia National Laboratory
E. Jan Vardaman
TechSearch International, Inc.
James Jian Zhang
Micron Technology, Inc.
Applied Reliability
Chair
Keith Newman
Hewlett-Packardkeith.newman@hp.com+1-650-857-4482

Assistant Chair
Shichun Qu
Fairchild Semiconductor
shichun.qu@fairchildsemi.com+1-408-822-2064
Sai Ankireddi
Soraa, Inc.
Sharad Bhatt
Shanta Systems, Inc.
Claudius Feger
IBM Corporation
Vijay Khanna
IBM Corporation
Chunho Kim
Medtronic Corporation
Wei KohPacrim Technology

Choon Heung Lee
Amkor Technology Korea

Mahadevan K. Iyer
Texas Instruments, Inc.

Mali Mahalingam
Freescale Semiconductor, Inc.

Timothy G. Lenihan
TGL Consulting

Debendra Mallik
Intel Corporation

Li Li
Freescale Semiconductor, Inc.

Jae-Woong Nah
IBM Corporation

Sebastian Liau
ITRI

Hirofumi Nakajima
Renesas Electronics Corporation

Lianjun Liu
Freescale Semicondutor, Inc.

Valerie Oberson
IBM Corporation

Albert Lu
Singapore Institute of Manufacturing
Technology

Sande Petty-Weeks
Skyworks Solutions, Inc.
Tom Poulin
Aerie Engineering
Shawn Shi
Medtronic Corporation
Tom Swirbel
Motorola, Inc.
Sean Too
Microsoft Corporation
Andy Tseng
Advanced Semiconductor Engineering,Inc.
Shaw Fong WongIntel Corporation
Jie Xue
Cisco Systems, Inc.
Jin YangIntel Corporation
Electronic Components & RF
Chair
Manos M. Tentzeris
Georgia Institute of Technology
etentze@ece.gatech.edu+1-404-385-6006
Assistant Chair
Nanju NaIBM Corporation
nananju@us.ibm.com+1-512-286-9677
Amit P. Agrawal
Cisco Systems, Inc.
Eric Beyne
IMEC
Prem Chahal
Michigan State University

Andrea Paganini
IBM Corporation
Albert F. Puttlitz
Mechanical Eng. Consultant
P. Markondeya Raj
Georgia Institute of Technology
Thomas G. Reynolds, III
T3 Group LLC
Clemens Ruppel
TDK
Hideki Sasaki
Renesas Electronics Corporation
Grit Sommer
Infineon Technologies AG
Frank Theunis
EPCOS Netherlands BVEmerging Technologies
ChairMark Bachmann
University of California, Irvinembachman@uci.edu+1-949-824-6421
Assistant ChairJohn Cunningham
Oraclejohn.cunningham@oracle.com+1-858-526-9121
Isaac Robin Abothu
Consultant, Sol-Gel Process
Vasudeva P. Atluri
Renavitas Technologies
Karlheinz Bock
Fraunhofer EMFT

Koneru Ramakrishna
Anveshak Technology & Knowledge
SolutionsNancy Stoffel
GE Research
Klaus Juergen Wolter
Technische Universitaet Dresden
Allison Xiao
Henkel Corporation
Interconnections
Chair
Gilles Poupon
CEA LETI - MINATEC
gilles.poupon@cea.fr+33-4-38-78-53-99
Assistant Chair
Matthew Yao
Rockwell Collins
myao@rockwellcollins.com+1-319-295-0147
William Chen
Advanced Semiconductor Engineering, Inc.
Rajen DiasIntel Corporation
Bernd Ebersberger
Intel Mobile Communications
Tom Gregorich
Broadcom Corporation
Li Li
Cisco Systems, Inc.
Changqing Liu
Loughborough University
Wei-Chung Lo
ITRIJames Lu
Rensselaer Polytechnic InstituteVoya Markovich
Endicott Interconnect Technologies, Inc.
James E. Morris
Portland State University
Lou Nicholls
Amkor Technology, Inc.
Katsuyuki Sakuma
IBM Corporation
Lei Shan
IBM Corporation
Akitsu Shigetou
National Institute for Materials Science

Craig Gaw
Freescale Semiconductor, Inc.

Rabindra N. Das
Endicott Interconnect Technologies,
Inc.

Abhilash Goyal
OracleSteve Greathouse
Plexus Corporation

T. S. Horng
National Sun Yat-Sen University

Joana MariaIBM Corporation

Rockwell M. Hsu
Cisco Systems, Inc.

Goran Matijasevic
University of California, Irvine

C. P. Hung
Advanced Semiconductor Engineering, Inc.

Dave Peard
Henkel Corporation

Assistant Chair
Stephanie Potisek
Dow Chemical
slpotisek@dow.com+1-979-238-9573

Lih-Tyng Hwang
National Sun Yat-Sen University

C. S. Premachandran
GLOBALFOUNDRIES

Rajen Chanchani
Consultant

Materials & Processing
Chair
Diptarka Majumdar
Superior Graphite
diptarka@yahoo.com+1-919-418-8025

37

Choong Kooi CheeIntel Corporation

Wendem Beyene
RambusTim ChenDarbond Technologies Co., Ltd.

Henning BraunischIntel Corporation

Bing Dang
IBM Corporation

Daniel de Araujo
Nimbic, Inc.

Don Frye
Polyera Corporation

L. J. Ernst
Ernst Consultant

C. Robert Kao
National Taiwan University

Xuejun Fan
Lamar University

Dong Wook Kim
Qualcomm Technologies, Inc.

Bruce Kim
The University of Alabama

Chin C. Lee
University of California, Irvine
Kwang-Lung Lin
National Cheng Kung University

Michael Lamson
Consultant

Daniel D. Lu
Henkel Corporation

Sheng Liu
Huazhong University of Science andTechnology

Hongtao Ma
Bridgelux, Inc.

Yong Liu
Fairchild Semiconductor Corporation

Mikel Miller
Draper Laboratory

En-Xiao Liu
Institute of High Performance Consulting,
A*STAR

Kyung-Wook Paik
KAIST
Dwayne Shirley
Qualcomm Technologies, Inc.
Ivan Shubin
OracleYoichi Taira
IBM Corporation
Quinn Tong
Henkel Corporation
Lejun Wang
Qualcomm Technologies, Inc.
Myung Jin Yim
Broadcom Corporation
Tieyu Zheng
Microsoft Corporation
Modeling & Simulation
Chair
Suresh K. Sitaraman
Georgia Institute of Technology
suresh.sitaraman@me.gatech.edu+1-404-894-3405
Assistant Chair
Zhaoqing Chen
IBM Corporation
zhaoqing@us.ibm.com+1-845-435-5595

38

Pradeep Lall
Auburn University

Erdogan Madenci
University of Arizona

Harry G. Kellzi
Teledyne Microelectronic
Technologies
Michael Leers
Fraunhofer ILT
Masanobu Okayasu
OpnextAlex Rosiewicz
Gooch & Housego
Andrew Shapiro
JPL
Hiren Thacker
OracleMasao Tokunari
IBM Corporation
Shogo Ura
Kyoto Institute of Technology
Stefan Weiss
Oclaro Switzerland AG
Ping Zhou
LDX Optronics, Inc.
Interactive Presentations
Chair
Mark Poliks
Endicott Interconnect Technologies, Inc.
mark.poliks@eitny.com+1-607-755-2064

Dan OhAltera Corporation

Assistant ChairMark Eblen
Kyocera America, Inc.
mark.eblen@kyocera.com+1-858-614-2537

Gamal Refai-Ahmed
PreQual Technologies Corporation

Swapan Bhattacharya
Georgia Institute of Technology

Sandeep SaneIntel Corporation

Rao Bonda
Amkor Technology

Jaemin Shin
Qualcomm Technologies, Inc.

Ibrahim Guven
University of Arizona

Optoelectronics
Chair
Henning Schroeder
Fraunhofer IZM
henning.schroeder@izm.fraunhofer.de+49-30-46403-277

Nam Pham
IBM Corporation

Tony Mak
Middlesex Community College

Assistant Chair
Kannan Raj
Oraclekannan.raj@oracle.com+1-858-526-9208

Patrick Thompson
Texas Instruments, Inc.
Professional Development
Courses
Chair
Kitty Pearsall
IBM Corporation
kittyp@us.ibm.com+1-512-286-7957

Gordon Elger
Philips Technologie GmbH

Assistant Chair
Jeffrey Suhling
Auburn University
jsuhling@eng.auburn.edu+1-334-844-3332

Ramachandra Achar
Carleton University

Z. Rena Huang
Rensselaer Polytechnic Institute

Eddie Kobeda
IBM Corporation

Kemal Aygun
Intel Corporation

Soon JangficonTEC USA

Al Puttlitz
Mechanical Eng. Consultant

Fuad Doany
IBM Corporation

64th ECTC Call for Papers
First Call For Papers

64th Electronic Components and Technology Conference
www.ectc.net
To be held May 27 - May 30, 2014
at the Walt Disney World Swan and Dolphin Resort, Lake Buena Vista, Florida, USA
The Electronic Components and Technology Conference (ECTC) is the premier international electronics symposium that brings together the best in packaging, components
and microelectronic systems science, technology and education in an environment of cooperation and technical exchange. ECTC is sponsored by the Components,
Packaging and Manufacturing Technology (CPMT) Society of the IEEE. You are invited to submit abstracts that provide non-commercial information on new developments,
technology and knowledge in the areas including, but not limited to as given below under each technical subcommittee name. Authors are encouraged to review thesessions of the previous ECTC programs to determine the committee selection for their abstracts.

Advanced Packaging:
3D integration, embedded, and wafer level packaging, flip chip,advanced substrates, novel assembly technologies, interposers,
TSVs, MEMS & sensors, electronic (digital, analog, & RF),and
optoelectronic & photovoltaic device packaging.
Applied Reliability:
3D package reliability, characterization and test methods,
interconnection reliability; solder and material characterization,and next generation/novel packaging reliability.
Assembly and Manufacturing Technology:
Assembly challenges and solutions, manufacturing aspects of
3D/TSV, manufacturing challenges of wafer thinning and flip chipprocessing.
Electronic Components & RF:
Components (including embedded components) and modules
for RF/THz systems and bio applications, metamaterials,
wireless sensors, RFID, RF MEMS, flexible & printed electronics,“green” RF electronics, wireless power transmission, power
scavenging components, nano-based RF structures, and lowpower RF designs.
Emerging Technologies:
Emerging packaging concepts and technologies, emerging 3D
packaging concepts, novel approaches to packaging, organic IC &TFT, microfluidics and MEMs, anti-counterfeiting packaging, andpackaging for biosensing.
Interconnections:First- and second-level interconnections: designs, structures,processes, performance, reliability, test including TSV, Si
interposer, and interconnections for 3D integration, flip chip,solder bumping and Cu-pillar, wafer-level packaging, advanced
wirebonds, non-traditional interconnections (e.g. ECA, CNT,
You are invited to submit a <750-word abstract that describes the scope,
content, and key points of your proposed paper via the website at www.ectc.net.
If you have any questions, contact:
Alan Huffman, 64th ECTC Program Chair
RTI International
3040 Cornwallis Rd.
Research Triangle Park, NC 27709
Phone: +1-919-248-9216
Email: huffman@rti.org
Abstracts must be received by October 14, 2013. All abstracts must be submitted
electronically at www.ectc.net. You must include the mailing address, businesstelephone number and email address of presenting author(s) and affiliations of all
authors with your submission.

graphene, optical, etc), electromigration for 2.5D and 3D,substrates and PCB solutions for the next generation systems,
system packaging and heterogeneous integration.
Materials & Processing:
Adhesives and adhesion, lead free solder, novel materials
and processing; underfills, mold compounds, and dielectrics,
emerging materials and processing for 3D.
Modeling & Simulation:
Thermal, mechanical, electrical modeling and related
measurements, 3D/TSV design and modeling, signal andpower integrity, fracture and warpage in packages, material andfabrication modeling, first-level and second-level interconnects,
high-speed interconnects.
Optoelectronics:
Fiber optical interconnects, active optical cables, parallel opticaltransceivers, silicon and III-V photonics devices, optical chipscale and heterogeneous integration, micro-optical system
integration and photonic system-in-package, optoelectronic
assembly and reliability, materials and manufacturing technology,
high-efficiency LEDs and high power lasers, and integrated opticalsensors.
Interactive Presentations:
Papers may be submitted on any of the listed major topics;
presentation of papers in an interactive format is highly
encouraged at ECTC. Interactive presentations allow significant
interaction between the presenter and attendees, and areespecially suited for material that benefits from more explanation
than is practical for oral presentations. Highly rated abstracts not
fitting the theme of an oral session or submitted specifically forinteractive presentation, and abstracts that are selected at thediscretion of the program chair are included in the Interactive
Presentation sessions.
Professional Development Courses
In addition to abstracts for papers, proposals are solicited from individuals
interested in teaching educational professional development courses (4 hours)
on topics described in the Call for Papers. Using the format “Course Objectives/
Course Outline/Who Should Attend,” 200-word proposals must be submitted
via the website at www.ectc.net by October 14, 2013. If you have any questions,contact:
Kitty Pearsall, 64th ECTC Professional Development Courses Chair
IBM Corporation
IMAD 2M-001/Bldg 045
11400 Burnet Road
Austin, TX 78758
Phone: +1-512-286-7957
Email: kittyp@us.ibm.com

39

64th Electronic Components & Technology Conference
Walt Disney World Swan & Dolphin
Lake Buena Vista, Florida, USA • May 27 - 30, 2014
The fun and splendor of Walt Disney World and the greater Orlando
area awaits you in 2014. In the heart of the Walt Disney World®
Resort, the award-winning Walt Disney World Swan and Dolphin
Resort is your gateway to Central Florida’s greatest theme parks andattractions. The resort is located in between Epcot® and Disney’s
Hollywood StudiosTM, and nearby Disney’s Animal Kingdom® Theme
Park and Magic Kingdom® Park. Come discover our 17 world-classrestaurants and lounges, sophisticated guest rooms with Westin
Heavenly Beds® and the luxurious Mandara Spa. Enjoy five pools, twohealth clubs, tennis, nearby golf, and many special Disney benefits,
including complimentary transportation to Walt Disney World Theme
Parks and Attractions, and the Extra Magic Hours benefit.
Just minutes from the Walt Disney World Swan and Dolphin Resort
is Downtown Disney’s West Side and Marketplace. Downtown
Disney’s West Side showcases top-notch restaurants, a 24-screen
AMC Pleasure Island movie theater, and other uncommon shops.
Here you’ll also find the exquisite Cirque du Soleil La Nouba live
entertainment show and the DisneyQuest Indoor Interactive themepark.
Downtown Disney Marketplace provides an appealing place to take abreak from Disney Theme Parks and Water Parks. Check out the largest Disney character store in the world. Or, for more of a respite, relax anddine at a lakeside restaurant.
Should you decide to explore outside the Greater Lake Buena Vista area, Orlando boasts other parks and recreation areas tailor made forwhatever your pleasure. Favorites include Universal Orlando, SeaWorld, Gatorland, and Winter Park.

Conference Sponsors

Gala Reception Gold Sponsors
www.amkor.com

www.dowelectronicmaterials.com

www.nanium.com

Gala Reception Silver Sponsors
www.appliedmaterials.com

www.microsoft.com

www.statschippac.com

Program Sponsor
www.appliedmaterials.com
40

www.corning.com

www.globalfoundries.com

Conference Sponsors
Luncheon & Evening
Sponsors

www.aseglobal.com

www.globalfoundries.com

Thumb Drive Sponsor

Badge Lanyard Sponsor

www.amkor.com

www.hdmicrosystems.com

Student Paper Sponsor

Student Reception

www.intel.com

www.ibm.com

Refreshment Break Sponsors

www.inemi.org

www.jsrmicro.com

www.lamresearch.com

www.namics.co.jp/e/www.ncap-cn.com

www.invensas.com
www.qualcomm.com

www.spil.com.tw

www.tokamerica.com

Media Sponsors
Official Media Sponsor

www.chipscalereview.com
Additional Media Sponsors

www.3dincites.infoneedle.
com

www.yole.fr

www.edacafe.com

www.electronics-cooling.com

www.memsjournal.com

www.meptec.com

www.electroiq.com

www.taptimes.com

As of May 1, 2013www.electronics
protectionmagazine.com

www.thermalnews.com

41

42

Conference At A Glance
Monday,May 27, 2013
3:00 p.m. – 5:00 p.m.
Registration – Chelsea
Commons, 4th Floor

Tuesday,
May 28, 2013
6:45 a.m. – 8:15 a.m.
AM PD Courses
Registration Only
Registration – Chelsea
Commons, 4th Floor
7:00 a.m. – 7:45 a.m.
PD Courses Instructor andProctors Briefing & Breakfast
Chelsea 2
7:00 a.m. – 5:00 p.m.
Speakers Prep
Yaletown 3

3:00 p.m. – 3:20 p.m.
PM PD Course BreakMont-Royal Commons &Chelsea Commons

2:00 p.m. – 4:00 p.m.
Session 38: Interactive
Presentations 2
Chelsea 3 & 4

5:00 p.m. – 6:00 p.m.
ECTC Student Reception
Chelsea 2

2:45 p.m. – 3:30 p.m.
Refreshment BreakChelsea 3 & 4

6:00 p.m. – 7:00 p.m.
General Chair’s Speakers
Reception (by Invitation)
Outside Pool Area, 4th floor,
facing the Las Vegas Strip(Rain backup: Chelsea 2)

5:30 p.m. – 6:30 p.m.
Technology Corner Reception
Chelsea 3 & 4

7:30 p.m. – 9:00 p.m.
Panel Session
Mont-Royal 1 & 2, 4th floor

Wednesday,
May 29, 2013

8:00 a.m. – NoonAM PD Courses
See page 8 for locations

6:45 a.m. – 4:00 p.m.
Conference Registration
Chelsea Commons, 4th Floor

9:00 a.m. – 5:00 p.m.
iNEMI Roadmap Meeting
Condesa 6, 2nd floor

7:00 a.m. – 7:45 a.m.
Today’s Speaker’s Breakfast
Chelsea 1

10:00 a.m. – NoonSpecial Session
Condesa 3, 2nd floor

7:00 a.m. – 5:00 p.m.
Speakers Prep
Yaletown 3

10:00 a.m. – 10:20 a.m.
AM PD Course BreakMont-Royal Commons &Chelsea Commons

8:00 a.m. – 11:40 a.m.
Sessions 1, 2, 3, 4 , 5, 6
See pages 10 thru 11 for
Locations

11:00 a.m. – 1:15 p.m.
Conference Registration
PM PD Courses Registration –Chelsea Commons, 4th Floor

9:00 a.m. – 11:00 a.m.
Session 37: Interactive
Presentations 1
Chelsea 3 & 4

Noon
PD Courses Luncheon
Chelsea 2

9:00 a.m. – Noon
Technology Corner Exhibits
Chelsea 3 & 4

1:00 p.m. – 5:00 p.m.
Technology Corner Set-up
Chelsea 3 & 4
1:15 p.m. – 5:00 p.m.
Conference Registration
Chelsea Commons, 4th Floor
1:15 p.m. – 5:15 p.m.
PD PM Courses
See page 8 for locations
2:00 p.m. – 4:30 p.m.
Special Modeling Session
Condesa 3, 2nd floor

9:15 a.m. – 10:00 a.m.
Refreshment BreakChelsea 3 & 4
Noon
ECTC Luncheon
Chelsea 1 & 5
1:30 p.m. – 6:30 p.m.
Technology Corner Exhibits
Chelsea 3 & 4
1:30 p.m. – 5:10 p.m.
Sessions 7, 8, 9, 10, 11, 12 Seepages 12 thru 13 for Locations

7:00 p.m. – 9:00 p.m.
Plenary Session
Mont-Royal 1 & 2, 4th floor

Thursday,May 30, 2013
7:00 a.m. – 5:00 p.m.
Speakers Prep
Yaletown 3
7:00 a.m. – 7:45 a.m.
Today’s Speaker’s Breakfast
Chelsea 1
7:30 a.m. – 4:00 p.m.
Conference Registration
Chelsea Commons, 4th Floor
8:00 a.m. – 11:40 a.m.
Sessions 13, 14, 15, 16, 17, 18
See pages 14 thru 15 for
Locations
9:00 a.m. – 11:00 a.m.
Session 39: Interactive
Presentations 3
Chelsea 3 & 4
9:00 a.m. – Noon
Technology Corner Exhibits
Chelsea 3 & 4
9:15 a.m. – 10:00 a.m.
Refreshment BreakChelsea 3 & 4
Noon
CPMT Luncheon
Chelsea 1 & 5
1:30 p.m. – 4:00 p.m.
Technology Corner Exhibits
Chelsea 3 & 4
1:30 p.m. – 5:10 p.m.
Sessions 19, 20, 21, 22, 23, 24
See pages 16 thru 17 for
Locations

2:00 p.m. – 4:00 p.m.
Session 40: Interactive
Presentations 4
Chelsea 3 & 4
2:45 p.m. – 3:30 p.m.
Refreshment BreakChelsea 3 & 4
6:30 p.m. – 7:30 p.m.
Gala Reception
Chelsea 1 & 5
8:00 p.m. – 10:00 p.m.
CPMT Seminar
Mont-Royal 1 & 2, 4th floor

Friday,May 31, 2013
7:00 a.m. – 5:00 p.m.
Speakers Prep
Yaletown 3
7:00 a.m. – 7:45 a.m.
Today’s Speaker’s Breakfast
Chelsea 1
7:30 a.m. – Noon
Conference Registration
Chelsea Commons, 4th Floor
8:00 a.m. – 11:40 a.m.
Sessions 25, 26, 27, 28, 29, 30
See pages 18 thru 19 for
Locations
8:30 a.m. – 10:30 a.m.
Student Interactive Presentations
Chelsea 3
9:15 a.m. – 10:00 a.m.
Refreshment BreakMont-Royal Commons
Noon
Program Chair Luncheon
Chelsea 1 & 5
1:30 p.m. – 5:10 p.m.
Sessions 31, 32, 33, 34, 35, 36
See pages 20 thru 21 for
Locations
2:45 p.m. – 3:30 p.m.
Refreshment BreakMont-Royal Commons

43

Sponsored by:

Supported by: