Abridged Edition
V-by-One® HS plus Standard Ver 1.02

V-by-One® HS plus Standard
Version 1.02
March 31, 2024

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Copyright(C) 2024 THine Electronics, Inc.

Abridged Edition
V-by-One®HS plus Standard Ver 1.02

Table of Contents
1.1.

Objectives .................................................................................................................................................... 4

1.2.

Technical Overview ...................................................................................................................................... 4

1.2.1.

Transmitter........................................................................................................................................... 5

1.2.2.

Receiver ............................................................................................................................................... 5

1.2.3.

Transmission Mode Setting.................................................................................................................. 5

1.2.4.

Data Lane ............................................................................................................................................. 7

1.2.5.

Hot Plug Detect Signal (HTPDN)......................................................................................................... 10

1.2.6.

LOCKN Signal ...................................................................................................................................... 10

1.2.7.

Data Enable Signal (DE)...................................................................................................................... 11

1.2.8.

Multiplexing and De-multiplexing ..................................................................................................... 12

2.1.

Functional Specification ............................................................................................................................. 14

2.1.1.

Packer and Unpacker ......................................................................................................................... 14

2.1.2.

Scrambler and Descrambler of ENC(SE) mode .................................................................................. 26

2.1.3.

Scrambler and Descrambler of ENC(EE) mode .................................................................................. 29

2.1.4.

Encoder and Decoder of ENC(SE) mode ............................................................................................ 30

2.1.5.

Encoder and Decoder of ENC(EE) mode ............................................................................................ 31

2.1.6.

Serializer and Deserializer of ENC(SE) mode...................................................................................... 32

2.1.7.

Serializer and Deserializer of ENC(EE) mode ..................................................................................... 33

2.1.8.

Link Status Monitor............................................................................................................................ 34

2.1.9.

Error Monitor ..................................................................................................................................... 35

2.2.

Operating Specification.............................................................................................................................. 36

2.2.1.

Transmitter State Diagram ................................................................................................................. 36

2.2.2.

Receiver State Diagram ...................................................................................................................... 37

2.2.3.

Link Start up Flow .............................................................................................................................. 38

2.2.4.

Link Disable Flow ............................................................................................................................... 39

2.2.5.

Trainings ............................................................................................................................................. 40

2.3.

Test Pattern ................................................................................................................................................ 45

2.3.1.

PRBS7 Pattern .................................................................................................................................... 46

2.3.2.

PRBS9 Pattern .................................................................................................................................... 46

2.3.3.

K28.7 Pattern ..................................................................................................................................... 46

2.3.4.

V-by-One® HS plus Pattern ................................................................................................................. 47

3.1.

Overview .................................................................................................................................................... 48

3.2.

Transmitter Electrical Specification............................................................................................................ 49
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3.2.1.

HS Mode ............................................................................................................................................ 49

3.2.2.

HSP Mode .......................................................................................................................................... 52

3.3.

Receiver Electrical Specification ................................................................................................................ 56

3.3.1.

HS Mode ............................................................................................................................................ 56

3.3.2.

HSP Mode .......................................................................................................................................... 58

3.4.

Common Electrical Specification ............................................................................................................... 60

3.5.

Channel Specification ................................................................................................................................ 61

3.6.

Eye Diagram Measurement Setting ........................................................................................................... 62

3.6.1.

Reference CDR ................................................................................................................................... 62

3.6.2.

Reference Equalizer ........................................................................................................................... 63

3.7.

Power On/Off and Power Down Specification ........................................................................................... 65

4.1.

Byte Length and Color Mapping ................................................................................................................ 66

4.2.

Multiple Data Lane Combination ............................................................................................................... 68

4.2.1.

Allocation of Pixel to Data Lane ......................................................................................................... 68

4.2.2.

Inter-lane Skewing ............................................................................................................................. 72

4.2.3.

RGB+CMY Color Mode ....................................................................................................................... 72

4.3.

3D Frame Identification ............................................................................................................................. 73

4.3.1.

3D flag on Blanking Period ................................................................................................................. 73

4.3.2.

3D Flag on DE Active Period............................................................................................................... 74

4.4.

HDR Metadata ........................................................................................................................................... 76

4.5.

Countermeasure against Frequency Change ............................................................................................. 77

5.1.

Pin Assignments ......................................................................................................................................... 78

5.1.1.
5.2.

SSGSS Pin Assignment........................................................................................................................ 78

Interoperability Order of Priority ............................................................................................................... 83

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Abridged Edition
V-by-One®HS plus Standard Ver 1.02

Introduction
1.1.

Objectives

This document constitutes the standard for the video by one high speed plus(V-by-One® HS plus).
✔ V-by-One® HS plus targets a high speed data transmission of video signals based on the internal connectionof equipment.
✔ V-by-One® HS plus pursues easier usage and lower power consumption compared with the current internal
connection.
✔ V-by-One® HS plus supports up to 8Gbps data rate.
✔ V-by-One® HS plus supports scrambling and Clock Data Recovery (CDR) to reduce EMI.
✔ V-by-One® HS plus supports CDR to solve the skew problem between the clock and data.

1.2.

Technical Overview

With V-by-One® HS plus proprietary encoding/decoding scheme and CDR architecture, V-by-One® HS plus
technology enables the transmission up to 40bit Pixel Data, up to 24bit Control Data (CTL), Hsync, Vsync, and Data
Enable (DE) by some differential pair cables with minimal external components.
As shown in Figure 1, V-by-One® HS plus link includes data lanes, Hot Plug Detect signal (HTPDN), and CDR Locksignal (LOCKN). The number of data lanes is depended on the pixel rate and color depth (refer to Table 5). HTPDN
connection between the transmitter and receiver can be omitted as an application option. V-by-One® HS plus
technology implements the transmitter emphasis and receiver equalizer.
V-by-One ® HS plus
Transmitter

Pixel Data

Control Data

V-by-One® HS plus
Receiver

TX0n

RX0n

TX0p

RX0p

TX1n

RX1n

TX1p

RX1p

TXNn

RXNn

TXNp

RXNp

HTPDN
LOCKN

HTPDN
LOCKN

Pixel Data

Control Data

Indicates microstrip lines or cables with their differential characteristic impedance being Zdiff

Figure 1

V-by-One® HS plus Link System Diagram

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Abridged Edition
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1.2.1. Transmitter
V-by-One® HS plus transmitter consists of packer, scrambler, encoder, serializer, and transmitter link monitor (refer
to Figure 5). The transmitter link monitor constantly checks LOCKN and HTPDN signals. If the LOCKN signal is high,the transmitter executes the CDR training. The transmitter sends the CDR training pattern during the CDR training
mode. When CDR is locked, the transmitter shifts from the CDR training mode to the normal mode, and then it
starts to transmit input data from user logic.

1.2.2. Receiver
V-by-One® HS plus receiver consists of unpacker, de-scrambler, decoder, de-serializer, and receiver link monitor.
The receiver synchronizes the pixel clock by referring to the CDR training pattern in the CDR training mode. After
shifting from the CDR training mode to the normal mode, the receiver aligns byte and pixel header position using
ALN training pattern. About ALN training, refer to Chapter 2.2.5.2.

1.2.3. Transmission Mode Setting
V-by-One® HS plus transmission mode is defined as below.
06
SR
HS
08
SE
FR(
)_COL
_ENC
_RCH MR
HSP
10
EE
LR
12

Frequency Range (FR)

FR(HSP) and FR(HS) mean the frequency range.
Table 1 Frequency Range Definition
SymbolFR(HS)
FR(HSP)

Parameter
V-by-One® HS
mode
V-by-One® HS plus
mode

Conditions

Min.

Typ.

Max.

Unit

-

0.6

-

4.0

Gbps

-

0.6

-

8.0

Gbps

Color Depth (COL)
COL(06), COL(08), COL(10), and COL(12) stand for color depth.
Table 2 Color Depth Definition
SymbolCOL(06)
COL(08)COL(10)
COL(12)

Parameter
6bit / color
8bit / color
10bit / color
12bit / color

Conditions-

5

Color Depth
18
24
30
36

Unit
bit
bit
bit
bit

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Encoding (ENC)
ENC(SE) and ENC(EE) mean the encoding scheme. ENC(SE) is 8b/10b encoding scheme. It is the same as V-by-One®
HS. ENC(EE) is higher efficiency encoding scheme than 8b/10b (option for future use).
Table 3 Encoding Definition
SymbolENC(SE)
ENC(EE)

Parameter
Standard Encoding (8b/10b)
Enhanced Encoding (T.B.D.)

Conditions
option for future use

Reach (RCH)
RCH(SR), RCH(MR) and RCH(LR) mean channel loss. V-by-One® HS plus has three different PHY specification
corresponding to each of RCH(SR), RCH(MR) and RCH(LR) (refer to Chapter 3).
Table 4 Reach Definition
SymbolRCH(SR)
RCH(MR)
RCH(LR)

Parameter
Short Reach
Middle ReachLong Reach

Conditions-

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1.2.4. Data Lane
Transmission rate is able to be set up to 8Gbps depended on video pixel clock rate and color depth.

Recommended Data Lane
Table 5Resolution
Full HD(1920 x 1080p)

Cinema Full HD(2560 x 1080p)

4K2K(3840 x 2160p)

5K UHD TV(5120 x 2160p)

8K4K(7680 x 4320p)

10K QUHD TV(10240 x 4320p)

Example of Video Data Format vs. Number of Lane

Number of Data Lanes*1(pixel clock)

Color Depth[bit]

Packer Clock*2[MHz/lane]

FR(HSP)

FR(HS)

FR(HSP)

FR(HS)

120Hz (297MHz)
240Hz (594MHz)
120Hz (370MHz)
240Hz (740MHz)
60Hz (594MHz)
120Hz (1188MHz)
144Hz (1425.6MHz)
165Hz (1633.5MHz)
240Hz (2376MHz)
60Hz (740MHz)
120Hz (1480MHz)
60Hz (2376MHz)
120Hz (4752MHz)
60Hz (2160MHz)
120Hz (5620MHz)

24/30/36
24/30/36
24/30/36*3
24/30/36*3
24/30/36
24/30/36
24/30/36*3
24/30/36
24/30/36
24/30/36*3
24/30/36*3
24/30/36
24/30/36
24/30/36*3
24/30/36*3

2
4
2
4
4
8
8
16
16
4
8
16
32
16
32

4
8
4
8
8
16
16
32
32
8
16
32
64
32
64

148.5
148.5
185
185
148.5
148.5
178.2
102.1
148.5
185
185
148.5
148.5
185
185

74.25
74.25
92.5
92.5
74.25
74.25
89.1
51.05
74.25
92.5
92.5
74.25
74.25
92.5
92.5

Refresh Rate

*1 other lane numbers could be chosen; however, for the interoperability, the above numbers are STRONGLY recommended.
*2 refer to Chapter 1.2.4.2 about a definition of packer clock.
*3 ENC(EE) mode would be adequate for 36bit color depth.

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V-by-One®HS plus Standard Ver 1.02

Data Lane Consideration
This chapter is informative only. It shows the procedure to select the minimum and maximum number of lanes
necessary for the target application
06
SR
HS
08
SE
FR
_COL
_ENC
_RCH MR
HSP
10
EE
LR
12

As a 1st step, [Color Encoding] is decided in the following procedure. [Color Mode] is chosen from 06, 08, 10 or 12
depending upon color depth. [Encoding] is chosen from ENC(SE) or ENC(EE) depending upon display size andaspect ratio. ENC(EE) is suitable for cinema display size. When these parameters are chosen, [Color Encoding] isdecided according to Table 6.
Table 6 Color/Encoding Factor [Color Encoding]SymbolColor

COL(06)
COL(08)COL(10)
COL(12)

Encoding
ENC(SE)
30
30
40
50

Unit

ENC(EE)
T.B.D.
T.B.D.
T.B.D.
T.B.D.

bit
bit
bit
bit

As a 2nd step, [encoded total bit rate] is calculated in the following procedure. Total bit rate which is physicallytransmitted on V-by-One® HS plus line can be estimated. Multiplying [pixel clock] of the target application byencoded data amount per pixel results into [encoded total bit rate] of V-by-One® HS plus transmission.
[encoded total bit rate](bps) = [Color Encoding](bit) × [pixel clock](Hz)As a result, [encoded bit rate per lane] and [packer clock] are calculated in the following procedure. [encoded bit
rate per lane] can be calculated as [total bit rate] over [number of data lanes]. [number of data lanes] should bechosen properly so that [encoded bit rate per lane] is above 0.6Gbps and below 8Gbps.

[encoded bit rate per lane](bps/lane) ==[packer clock] is defined as follows,

Therefore,[encoded total bit rate](bps)[number of data lanes][Color Encoding ](bit) × [pixel clock](Hz)[number of data lanes][pixel clock](Hz)= [packer clock](Hz/lane)[number of data lanes][encoded bit rate per lane](bps/lane) = [Color Encoding](bit) × [packer clock](Hz/lane)[packer clock] should be selected appropriately for signal handling in applications.

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In FR(HSP) mode, [encoded bit rate per lane] should be above 0.6Gbps and below 8.0Gbps.
0.6Gbps ≤ [encoded bit rate per lane](bps/lane) ≤ 8.0Gbps
In FR(HS) mode, [encoded bit rate per lane] should be above 0.6Gbps and below 4.0Gbps.
0.6Gbps ≤ [encoded bit rate per lane](bps/lane) ≤ 4.0Gbps

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1.2.5. Hot Plug Detect Signal (HTPDN)HTPDN indicates the connecting condition between the transmitter and receiver. HTPDN of the transmitter side ishigh when the receiver is not active or not connected. Then the transmitter can enter into the power down mode.
HTPDN is set to low by the receiver when the receiver is active and connected with the transmitter, and then thetransmitter must start up and transmit CDR training pattern for link training. HTPDN is the open drain output at
the receiver side. Pull-up resistor is needed at the transmitter side (refer to Figure 1).
In RCH(SR) mode, HTPDN connection between the transmitter and receiver may be omitted as an application
option. In this case shown on Figure 2, HTPDN at the transmitter side is fixed low.
V-by-One® HS plus
Transmitter

Pixel Data

Control Data

V-by-One ® HS plus
Receiver

TX0n

RX0n

TX0p

RX0p

TX1n

RX1n

TX1p

RX1p

TXNn

RXNn

TXNp

RXNp

HTPDN
LOCKN

HTPDN
LOCKN

Pixel Data

Control Data▲
Indicates microstrip lines or cables with their differential characteristic impedance being Zdiff

Figure 2 V-by-One® HS plus Link System without HTPDN Connection Schematic Diagram

1.2.6. LOCKN Signal
LOCKN indicates whether the CDR is in the lock state or not. LOCKN at the transmitter input is set to high by a pullup resistor when the receiver is not active or at the CDR training state. LOCKN is set to low by the receiver when
CDR lock is done. Then the CDR training mode finishes, and the transmitter shifts to the normal mode. LOCKN is
the open drain output at the receiver side. Pull-up resistor is needed at the transmitter side.
When HTPDN is included in an application, the LOCKN signal should only be considered after the HTPDN is pulled
into low by the receiver.

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Connector and Cable
This chapter shows guideline of connector and cable to connect the V-by-One® HS plus transmitter (e.g. Video
processing unit) and receiver (e.g. Panel module).

5.1.

Pin Assignments

5.1.1. SSGSS Pin Assignment
In terms of pin assignment, SSGSS means “Signal-Signal-Ground-Signal-Signal” assignment.
Some systems might require a lot of user option, power supply pins and V-by-One® HS plus lanes at the same time.
Reduced ground format is applied to such a case. Compared with SSGGSS format signal integrity gets worse ingeneral; therefore, user must pay attention to achieve transmission quality between transmitter and receiver,incorporated in PCB design, and connector/harness selection.
The power supply should be constructed by another dedicated cable separated from V-by-One® HS plus high speed
lanes when system needs to transmit large current capacity between transmitter side and receiver side.
Note:
Some cable like Flexible Printed Circuits (FPC) may not have the symmetric conductor layout. This means that if
users connect the cable at reverse direction, i.e. Rx plug is connected to transmitter’s receptacle and Tx plug toreceiver’s receptacle, the correct connection cannot be achieved. Users must pay attention to the cable direction.

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FR(HSP) mode for 4K120Hz
Table 36 shows the 31 pin assignment in FR(HSP) mode for 4K120Hz. In this mode, it can be assigned 4 optional
pins in the cable. On the other hand, the power supply should be connected by using another cable to support
large current capacity.
Table 36SSGSS(31pin) Pin Assignment in FR(HSP) mode for 4K120Hz
Pin No (TX)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

31pins(Option)(Option)(Option)(Option)
HTPDN
LOCKN
GND
Rx0n
Rx0p
GND
Rx1n
Rx1p
GND
Rx2n
Rx2p
GND
Rx3n
Rx3p
GND
Rx4n
Rx4p
GND
Rx5n
Rx5p
GND
Rx6n
Rx6p
GND
Rx7n
Rx7p
GND

79

Pin No (RX)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31

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Table 37 shows the 41 pin assignment in FR(HSP) mode for 4K120Hz. In this mode, it can be assigned 14 optional
pins in the cable. On the other hand, the power supply should be connected by using another cable to support
large current capacity.
Table 37

SSGSS(41pin) Pin Assignment in FR(HSP) mode for 4K120Hz
Pin No (TX)
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

41pins(Option)(Option)(Option)(Option)(Option)(Option)(Option)(Option)(Option)(Option)(Option)(Option)(Option)(Option)
HTPDN
LOCKN
GND
Rx0n
Rx0p
GND
Rx1n
Rx1p
GND
Rx2n
Rx2p
GND
Rx3n
Rx3p
GND
Rx4n
Rx4p
GND
Rx5n
Rx5p
GND
Rx6n
Rx6p
GND
Rx7n
Rx7p
GND

80

Pin No (RX)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41

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Table 38 shows the 51 pin assignment in FR(HSP) mode for 4K120Hz. In this mode, it can be assigned 24 optional
pins in the cable. On the other hand, the power supply should be connected by using another cable to support
large current capacity.
Table 38SSGSS(51pin) Pin Assignment in FR(HSP) mode for 4K120Hz
Pin No (TX)
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

51pins(Option)(Option)(Option)(Option)(Option)(Option)(Option)(Option)(Option)(Option)(Option)(Option)(Option)(Option)(Option)(Option)(Option)(Option)(Option)(Option)(Option)(Option)(Option)(Option)
HTPDN
LOCKN
GND
Rx0n
Rx0p
GND
Rx1n
Rx1p
GND
Rx2n
Rx2p
GND
Rx3n
Rx3p
GND
Rx4n
Rx4p
GND
Rx5n
Rx5p
GND
Rx6n
Rx6p
GND
Rx7n
Rx7p
GND

81

Pin No (RX)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51

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FR(HSP) mode for 8K60Hz
Table 39 shows the 51 pin assignment in FR(HSP) mode for 8K60Hz. In this mode, both the power supply andoption pin should be connected by using another cable to support large current capacity.
Table 39 SSGSS(51pin) Pin Assignment in FR(HSP) mode for 8K60Hz
Pin No (TX)
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

51pins
HTPDN
LOCKN
GND
Rx0n
Rx0p
GND
Rx1n
Rx1p
GND
Rx2n
Rx2p
GND
Rx3n
Rx3p
GND
Rx4n
Rx4p
GND
Rx5n
Rx5p
GND
Rx6n
Rx6p
GND
Rx7n
Rx7p
GND
Rx8n
Rx8p
GND
Rx9n
Rx9p
GND
Rx10n
Rx10p
GND
Rx11n
Rx11p
GND
Rx12n
Rx12p
GND
Rx13n
Rx13p
GND
Rx14n
Rx14p
GND
Rx15n
Rx15p
GND

82

Pin No (RX)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51

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5.2.

Interoperability Order of Priority

For interoperability, the following points are STRONGLY RECOMMENDED to be paid attention to. The pin
assignment of V-by-One® HS plus transmission is absolutely irreplaceable and it should be fixed.
✔ V-by-One® HS plus Hot plug detect✔ V-by-One® HS plus Lock detect✔ V-by-One® HS plus Ground✔ V-by-One® HS plus Lane
The following is an example of 8 lane case. V-by-One® HS plus related pin assignment should be kept.
Table 40

Irreplaceable V-by-One® HS plus Transmission Signal on 41 Pin Assignment in FR(HSP) mode
TX sidePin Nosymbol
41(Option)40(Option)39(Option)38(Option)37(Option)36(Option)35(Option)34(Option)33(Option)32(Option)31(Option)30(Option)29(Option)28(Option)
27
HTPDN
26
LOCKN
25
GND
24
Tx0n
23
Tx0p
22
GND
21
Tx1n
20
Tx1p
19
GND
18
Tx2n
17
Tx2p
16
GND
15
Tx3n
14
Tx3p
13
GND
12
Tx4n
11
Tx4p
10
GND
9
Tx5n
8
Tx5p
7
GND
6
Tx6n
5
Tx6p
4
GND
3
Tx7n
2
Tx7p
1
GND

Desicritption(user option signal)(user option signal)(user option signal)(user option signal)(user option signal)(user option signal)(user option signal)(user option signal)(user option signal)(user option signal)(user option signal)(user option signal)(user option signal)(user option signal)
V-by-One HS plus Hot plug detect signal
V-by-One HS plus Lock detect signal
GroundV-by-One HS plus Lane0
V-by-One HS plus Lane0
GroundV-by-One HS plus Lane1
V-by-One HS plus Lane1
GroundV-by-One HS plus Lane2
V-by-One HS plus Lane2
GroundV-by-One HS plus Lane3
V-by-One HS plus Lane3
GroundV-by-One HS plus Lane4
V-by-One HS plus Lane4
GroundV-by-One HS plus Lane5
V-by-One HS plus Lane5
GroundV-by-One HS plus Lane6
V-by-One HS plus Lane6
GroundV-by-One HS plus Lane7
V-by-One HS plus Lane7
Ground83

RX sidesymbolPin No(Option)1(Option)2(Option)3(Option)4(Option)5(Option)6(Option)7(Option)8(Option)9(Option)10(Option)11(Option)12(Option)13(Option)
14
HTPDN
15
LOCKN
16
GND
17
Rx0n
18
Rx0p
19
GND
20
Rx1n
21
Rx1p
22
GND
23
Rx2n
24
Rx2p
25
GND
26
Rx3n
27
Rx3p
28
GND
29
Rx4n
30
Rx4p
31
GND
32
Rx5n
33
Rx5p
34
GND
35
Rx6n
36
Rx6p
37
GND
38
Rx7n
39
Rx7p
40
GND
41

Copyright(C) 2024 THine Electronics, Inc.

Abridged Edition
V-by-One®HS plus Standard Ver 1.02

If power is supplied via a cable, the following guideline should be observed.
✔ Power pins should be placed from Rx pin No. 1.
✔ Minimum number of power pins are defined but other option pins can be assigned to power pins.
✔ User needs to pay attention to the effect of power supply noise on V-by-One® HS plus lane.
The following is an example of 8 lane case. Power supply pin assignment should be from Rx pin No. 1.
Table 41 Irreplaceable Power Supply Pins on 41 Pin Assignment in FR(HSP) mode
TX sidePin Nosymbol
41
Vcc
40
Vcc
39
Vcc
38
Vcc
37
(Option)36(Option)35(Option)34(Option)33(Option)32(Option)31(Option)30(Option)29(Option)28(Option)
27
HTPDN
26
LOCKN
25-1
-

Desicritption
Supply voltage for module
Supply voltage for module
Supply voltage for module
Supply voltage for module(user option signal)(user option signal)(user option signal)(user option signal)(user option signal)(user option signal)(user option signal)(user option signal)(user option signal)(user option signal)
V-by-One HS plus Hot plug detect signal
V-by-One HS plus Lock detect signal-

RX sidesymbolPin No
Vcc
1
Vcc
2
Vcc
3
Vcc
4
(Option)5(Option)6(Option)7(Option)8(Option)9(Option)10(Option)11(Option)12(Option)13(Option)
14
HTPDN
15
LOCKN
16
17-41

If a system needs more power supply, option pins can be assigned to Vcc pins as power supply.
Table 42 Expanded Power Supply Example on 41 Pin Assignment in FR(HSP) mode
TX sidePin Nosymbol
41
Vcc
40
Vcc
39
Vcc
38
Vcc
37
Vcc
36
Vcc
35
Vcc
34
Vcc
33
(Option)32(Option)31(Option)30(Option)29(Option)28(Option)
27
HTPDN
26
LOCKN
25-1
-

Desicritption
Supply voltage for module
Supply voltage for module
Supply voltage for module
Supply voltage for module
Supply voltage for module
Supply voltage for module
Supply voltage for module
Supply voltage for module(user option signal)(user option signal)(user option signal)(user option signal)(user option signal)(user option signal)
V-by-One HS plus Hot plug detect signal
V-by-One HS plus Lock detect signal-

84

RX sidesymbolPin No
Vcc
1
Vcc
2
Vcc
3
Vcc
4
Vcc
5
Vcc
6
Vcc
7
Vcc
8
(Option)9(Option)10(Option)11(Option)12(Option)13(Option)
14
HTPDN
15
LOCKN
16
17-41

Copyright(C) 2024 THine Electronics, Inc.

Abridged Edition
V-by-One®HS plus Standard Ver 1.02

Option pins can be used for any purpose below.
✔ For another power supply in order to enhance power limit.
✔ For ground to stabilize power supply.
✔ For another control signals like I2C, SPI, GPIO or other user defined signals.
✔ If there are remainder of option pins, those pins should be assigned to ground.
The following is an example of 8 lane case. There are 13 user option pins which can be used arbitrary.
Table 43 User Option Pins on 41 Pin Assignment in FR(HSP) mode
TX sidePin Nosymbol
41
Vcc
40
Vcc
39
Vcc
38
Vcc
37
(Option)36(Option)35(Option)34(Option)33(Option)32(Option)31(Option)30(Option)29(Option)28(Option)
27
HTPDN
26
LOCKN
25
GND
24
Tx0n
23
Tx0p
22
GND
21
Tx1n
20
Tx1p
19
GND
18
Tx2n
17
Tx2p
16
GND
15
Tx3n
14
Tx3p
13
GND
12
Tx4n
11
Tx4p
10
GND
9
Tx5n
8
Tx5p
7
GND
6
Tx6n
5
Tx6p
4
GND
3
Tx7n
2
Tx7p
1
GND

Desicritption
Supply voltage for module
Supply voltage for module
Supply voltage for module
Supply voltage for module(user option signal)(user option signal)(user option signal)(user option signal)(user option signal)(user option signal)(user option signal)(user option signal)(user option signal)(user option signal)
V-by-One HS plus Hot plug detect signal
V-by-One HS plus Lock detect signal
GroundV-by-One HS plus Lane0
V-by-One HS plus Lane0
GroundV-by-One HS plus Lane1
V-by-One HS plus Lane1
GroundV-by-One HS plus Lane2
V-by-One HS plus Lane2
GroundV-by-One HS plus Lane3
V-by-One HS plus Lane3
GroundV-by-One HS plus Lane4
V-by-One HS plus Lane4
GroundV-by-One HS plus Lane5
V-by-One HS plus Lane5
GroundV-by-One HS plus Lane6
V-by-One HS plus Lane6
GroundV-by-One HS plus Lane7
V-by-One HS plus Lane7
Ground85

RX sidesymbolPin No
Vcc
1
Vcc
2
Vcc
3
Vcc
4
(Option)5(Option)6(Option)7(Option)8(Option)9(Option)10(Option)11(Option)12(Option)13(Option)
14
HTPDN
15
LOCKN
16
GND
17
Rx0n
18
Rx0p
19
GND
20
Rx1n
21
Rx1p
22
GND
23
Rx2n
24
Rx2p
25
GND
26
Rx3n
27
Rx3p
28
GND
29
Rx4n
30
Rx4p
31
GND
32
Rx5n
33
Rx5p
34
GND
35
Rx6n
36
Rx6p
37
GND
38
Rx7n
39
Rx7p
40
GND
41

Copyright(C) 2024 THine Electronics, Inc.

Abridged Edition
V-by-One®HS plus Standard Ver 1.02

The following pin assignment is an example of connecting I2C signals. In some use cases, the I2C is used for serialinterface between Tx PCB and Rx PCB. So d SDA signal assignment
Table 44 Tx PCB Arrangement Example to Rx PCB #41 Pin Assignment in FR(HSP) mode
TX sidePin Nosymbol
41
Vcc
40
Vcc
39
Vcc
38
Vcc
37
(Option)36(Option)35(Option)34(Option)33(Option)32(Option)31(Option)30(Option)
29
SCL
28
SDA
27
HTPDN
26
LOCKN
25-1
-

RX sidesymbolPin No
Vcc
1
Vcc
2
Vcc
3
Vcc
4
(Option)5(Option)6(Option)7(Option)8(Option)9(Option)10(Option)11(Option)
12
SCL
13
SDA
14
HTPDN
15
LOCKN
16
17-41

Desicritption
Supply voltage for module
Supply voltage for module
Supply voltage for module
Supply voltage for module(user option signal)(user option signal)(user option signal)(user option signal)(user option signal)(user option signal)(user option signal)(user option signal)
Serial Clock Line
Serial Data Line
V-by-One HS plus Hot plug detect signal
V-by-One HS plus Lock detect signal-

One type of Tx PCB might be connected to more than one type of Rx PCB in user’s system.
✔ Irreplaceable V-by-One® HS plus lines are simply connected to Rx PCB from Tx PCB.
✔ Tx HTPDN line might be connected to Rx PCB via a cable or Tx PCB ground (refer to Figure 57).
✔ Irreplaceable power supply lines might be simply connected to Rx PCB from Tx PCB.
✔ Option pins might be connected to Rx PCB via passive component on Tx PCB (e.g. 0Ω resistor).
0Ω resistor
Mounting or Unmounting#26

Tx PCB HTPDN

Tx PCB groundFigure 57 Tx HTPDN Circuit on Tx PCB

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Abridged Edition
V-by-One®HS plus Standard Ver 1.02

Glossary
Table 45 Glossary of Terms
Term

Description

Data Lane

One differential signal pair
FSACTIVE, FSBS, FSBP, FSBE, and FSBE_SR are the framing symbols.
One framing symbol is transmitted at the one pixel clock.
The data amount of framing symbols sending is depended on the byte mode setting.
8 bit data before 8b/10b encoder and after 8b/10b decoder.
10 bit data after 8b/10b encoder and before 8b/10b decoder.
In addition to the pixel data, special character is assigned. Refer to Table 12.

framing symbol

Character87

Copyright(C) 2024 THine Electronics, Inc.

Abridged Edition
V-by-One®HS plus Standard Ver 1.02

Acronyms
Table 46 Acronyms
Term

Description

3D
3DEN
3DLR
ALN
CDR
CMY
CTLE
DFE
DTV
EMI
FFC
GPIO
HDR
HF
I2C
LF
LFSR
LSB
MSB
PCB
RGB
RGBW
RGBY
SPI
TDR
XOR
YUV

three Dimensional
3D mode ENable
3D Left/Right Indicator
ALigNment
Clock Data Recovery
Cyan Magenta Yellow (color representation)
Continuous Time Linear Equalizer
Decision Feedback Equalizer
Digital TeleVision
ElectroMagnetic Interference
Flexible Flat Cable
General-Purpose Input/Output
High Dynamic Range
High Frequency
Inter-Integrated Circuit
Low Frequency
Linear Feedback Shift Register
Least Significant Bit
Most Significant Bit
Printed Circuit Board
Red Green Blue (color representation)
Red Green Blue White(color representation)
Red Green Blue Yellow (color representation)
Serial Peripheral Interface
Time Domain Reflectometry
eXclusive OR
Y for luminance U and V for chrominance (color representation)

88

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Abridged Edition
V-by-One®HS plus Standard Ver 1.02

Revision History
Date
June 1, 2023

Version
1.00

July 14, 2023

1.01

March 31, 2024

1.02

-

-

Change of Content
1st Version
Revised Figure24 and 25
Defined the input signal to measure the eye diagram in Chapter 3.3.2.
Fixed typo in Chapter 3.7
Revised Table36~44
Swapped HTPDN and LOCKN-

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Abridged Edition
V-by-One®HS plus Standard Ver 1.02

Notice and Requests
1. THIS DOCUMENT AND RELATED MATERIALS AND INFORMATION ARE PROVIDED "AS IS" WITH NO WARRANTIES,EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESSFOR A PARTICULAR PURPOSE, NON-INFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS, OR ANY WARRANTYOTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION, OR SAMPLE. THINE ASSUMES NO RESPONSIBILITY
FOR ANY ERRORS CONTAINED IN THIS DOCUMENT AND HAS NO LIABILITIES OR OBLIGATIONS FOR ANY DAMAGESARISING FROM OR IN CONNECTION WITH THE USE OF THIS DOCUMENT.
2. THine may have patents or pending patent applications, trademarks, copyrights, or other intellectual property
rights that relate to the presented subject matter. The furnishing of documents and other materials andinformation does not provide any license, express or implied, by estoppels or otherwise, to any such patents,
trademarks, copyrights, or other intellectual property rights.
3. This material contains copyright, know-how or other proprietary of THine. Copying without THine’s priorpermission is prohibited.
4. The specifications described in this material are subject to change without prior notice.
5. THine shall have no obligation to provide any support, installation or other assistance with regard to theinformation or products made in accordance with the information.
6. “THine”, “V-by-One”, “THine” logo, and “V-by-One” logo are trademarks or registered trademarks of THine or its
subsidiaries in Japan and other countries. The use of these trademarks without THine’s prior permission isprohibited.

90

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