KEK BPM (18K12)
Status Report
2013/June/27
Ryo Ichimiya (KEK)
rev. 2.20+Eng.
1

Candidates to get worth position
resolution
1. BPF, ADC input circuit may operate in non-linear
region.
2. Tails of BPF output spectrum exceeds Nyquist
window (250-375MHz) and it makes folding noise.
3. Triple harmonic (900MHz) also may cause foldingnoise.
4. Analogue noise from DC-DC converter etc.
introduces GND wobble, EMI and so forth.

2౉ജ䋱䌾䋴䌣䌨䈱䈇䈝䉏䈎䈮䌒䌆䋳䋰䋰㪤㪟䌺ᄌ⺞಴ജ䊶䌅䌅䌐䌒䌏䌍

Block diagram䉻䉟䊅䊚䉾䉪䉭䉟䊮䊐䉜䉪䉺䊷଻ሽ䇭䋻䊥䉶䉾䊃ᓟ䊨䊷䊄䊶䌆䌌䌁䌓䌈䌒䌏䌍䊶૶↪㔚Ḯ䋨䌖䌍䌅䋩䂓ో૕䊑䊨䉾䉪࿑Overview

䌆䌐䌇䌁䊒䊨䉫䊤䊛↪㩷䇭䌊䋭䌔䌁䌇䇮䌖䌍䌅䌢䌵䌳⚻↱䈪䉝䉾䊒䊂䊷䊃น⢻㩷䋫䋵䌖㩷䋫䋱䋲䌖㩷䋭䋱䋲䌖䋶䌁એౝᧂ૶↪
䋰䋮䋵䌁એౝ㪚㪟㪈 䇭ାภᬌ಴ㇱ㩿ਃశ␠⵾䋩㪛㫀㪽㪽㪘㪤㪧㪉㪌㪇㪤㪟㫑䍙䍻䍪䍽䍷䇭㪈㪍㪹㫀㫋㪘㪛㪚䇭䇭㪙㪧㪝㪂㪪㪮㪂㪘㪫㪫㪂㪘㪤㪧㪰㪂㪯㪄㩷㩷㪝㪠㪆㪝㪦㪚㪟㪉 䇭䇭䇭䇭䇭䇭䇭㩿ห਄䋩䇭㪈㪍㪹㫀㫋㪘㪛㪚㪚㪟㪊 䇭䇭䇭䇭䇭䇭䇭㩿ห਄䋩䇭㪈㪍㪹㫀㫋㪘㪛㪚㪚㪟㪋 䇭䇭䇭䇭䇭䇭䇭㩿ห਄䋩䇭㪈㪍㪹㫀㫋㪘㪛㪚㪛㪊㪉㪹㫌㫊㩷㩷㪛㪜㪣㪘㪰㩷㩷㪝㪠㪆㪝㪦㩷㩷㪛㪜㪣㪘㪰㩷㪦㪪㪚㩷㪉㪌㪇㪤㪟㫑㩷㩷㩷㩷㩷㩷㩷㩷㪘㪛㪚㪣㪢㪉㪇㪇䌾㪉㪌㪇㪤㪟㫑㪘㪊㪉㪹㫌㫊㩷㩷㪝㪠㪆㪝㪦䇭㩷㪤㪘㪠㪥㩷㪝㪧㪞㪘㩷㩷㩷㩷㪪㫇㪸㫉㫋㪸㫅㪄㪍㪠㪩㪨㪁㪛㪫㪘㪚㪢㩷㪜㪜㪧㪩㪦㪤㩷㩷㪝㪠㪆㪝㪦㩷㩷㪛㪜㪣㪘㪰㩷㩷ᩞᱜାภ಴ജㇱcal.
pulsar(300MHz)㩷㩿ਃశ␠⵾䋩䇭㪊㪇㪇㪤㪟㫑㪭㪤㪜㪹㫌㫊㩷㩷㪛㪜㪣㪘㪰㪯㪂㪰㪄㪪㪬㪙㩷㪝㪧㪞㪘㩿㪪㫇㪸㫉㫋㪸㫅㪄㪍㪀㩷㫏㪋㪺㪿㪡㪄㪫㪘㪞㩷㪝㫃㪸㫊㪿㩷㪩㪦㪤㩷㔚Ḯㇱ㩷㩷㪛㪚㪆㪛㪚㩷㩷㪩㪜㪞㪅㪫㪩㪠㪞㩿㪥㪠㪤㪀 㩷㩷㪠㪥 䃁㩷㩷㩷㪌㪇㪟㫑㩷㪦㪬㪫 䃁

Analogue
Frontendᩣ ࠺ࠫ࠹࠶ࠢࠬ⎇ⓥᚲ

㩷㪂㪌㪭㪂㪈㪉㪭㪄㪈㪉㪭㩷㩷㪇㪭[specifications]䋱䋸䌋䋱䋲ဳ㩷䋲䊌䊦䉴ኻᔕ䌂䌐䌍ାภಣℂ࿁〝
Gain: 32.5dB(confirmed)
Max Output: +12dBm(2.5Vpp)1ns

Att.(pre)0-31.5dBAtt.(post)
0-31.5dB*These tests presented in this slide have been performed with Pre:8dB, Post:0dB
setting. Total BPF gain is +24.5dB(x16.8).

3㩷䇭㪈㪏㪢㪈㪉ဳ㩷㪣㫀㫅㪸㪺㪙㪧㪤䇭㪘㪛㪚౉ജㇱ㩷ቯᢙᄌᦝ䊶೨㪆 ᓟ䈱․ᕈADC input circuit㪎㪏㪇㫄㪭㫇㪄㫇㩷㸢㪋㪇㪇㫄㪭㫇㪄㫇䇭䊶㪩㪙㪄㪙㪧㪝౉ജ䋺㪊㪇㪇㪤㪟㫑䊶㪇㪻㪙㫄㩷㪚㪮䇭䊶㪩㪝㪄㪙㪧㪝࿁〝䋺㪧㫉㪼㪘㪫㪫䋺㪈㪉㪻㪙䇭䇭㩷㩷䇭䇭䇭䇭䇭䇭䇭㩷㩷㪧㫆㫊㫋㪘㪫㪫䋺㪈㪉㪻㪙㪌㪇㪇㫄㪭㫇㪄㫇
㩷㸢㪊㪋㪇㫄㪭㫇㪄㫇㪋㪋㪇㫄㪭㫇㪄㫇

㪊㪇㪇㪤㪟㫑㪚㪮
㩷㪈㪊㪇㪇㫄㪭㫇㪄㫇䋲䋰䋱䋳䋯䋴䋯䋲䇭䇭䊂䉳䊁䉾䉪䉴⎇ⓥᚲ䇭ጊ↰㪏㪉㪇㫄㪭㫇㪄㫇㩷㸢㪋㪊㪇㫄㪭㫇㪄㫇㪏㪉㪇㫄㪭㫇㪄㫇㩷㸢㪋㪊㪇㫄㪭㫇㪄㫇㪎㪋㪇㫄㪭㫇㪄㫇㩷㪏㪍㪇㫄㪭㫇㪄㫇㩷㪘㪛㪚㪂౉ജ๟ᵄᢙ․ᕈ㽲䇭࿁〝ቯᢙᄌᦝ೨

250MHz 300MHz(fs)㩷㪘㪛㪚㪂౉ജ๟ᵄᢙ․ᕈ
䇭࿁〝ቯᢙᄌᦝᓟ

250MHz 300MHz(fs)4Hz, it is recommended to set the buffer current
ng on the input network design and frequency
the optimum buffer current settings may bethan the input network recommendations shownFigure 54.

inputs. This allows the common-mode output pin of the ato set this voltage between the interface of the two devices
wise, use an ac coupling capacitor in series on each of theinput as shown in Figure 54 for IF applications that do no
dc coupling. See the Memory Map section for more de

22pF -> Snubber circuit
3.3V

SMA

10nH 0.1µF

ADT1-1WT

ADT1-1WT

0.1µF

1.8V

09029-040

AIN+
AD9467• Thanks to Adrew’s suggestion
andmodification,
we have


16
INPUT
4.7pF
3.5pF
0.1µF
achieved
at ADC0.1µF
input
with
thissnubbercircuit
than=  +10dB
ADC
0.1µF
INTERNAL
INPUT Z
22pF, which
also
prevents
ADC
malfunction.
AIN–

0.1µF
0.1µF
NOTES
1. ALL CONNECTIONS AND POWER SUPPLY DECOUPLING NOT SHOWN.

Figure 51. Differential Transformer-Coupled Configuration for Baseband Applications up to 150 MHz

Snubber circuit

10nH 0.1µF

ADT1-1WT

0.1µF

ADT1-1WT
1.8pF

INPUT= 

0.1µF

0.1µF

0.1µF

0.1µF

AIN+

AD9467



0.1µF

1.8V

AIN–

3.5pF
ADC
INTERNAL
INPUT Z

NOTES
1. ALL CONNECTIONS AND POWER SUPPLY DECOUPLING NOT SHOWN.

1609029-041

SMA

3.3V

Figure 52. Differential Transformer-Coupled Configuration for IF Applications from 150 MHz to 300 MHz
C1R5R7FromDatasheetȝ) ADC9467
ȍȍANALOGIN

18R1ȍR3ȍ

C68.2pF

3.3V
AIN+

1.8V

522pF (before modification)• HSPICE simulation– Gain: 1/3 (-10dB) at 300MHz.
– Lower capacitance behaves unstable, so cannot reduce its capacitance.
MHF

6

Snubber circuit (after modification)• HSPICE simulation– Almost no gain drop at 300MHz.
– Implement on ch1, ch2 on #2 board.
MH

SnubberCircuit

7

ADC output• Consistent with calculation. x3 gain (+10dB).
• Proved it also suppress the ADC malfunction.

8

Block diagram of 1kV pulsar test
1:2
VPulsar

40dBAtt.

variableAtt.x2
−B−B

1:2
1:2BPM
Readout(Pre:8dB
Post:0dB)

Pulse
Gen.

9

Linearity check (1)••Attenuator output shows good linearity from 40dB to 0dB.
BPF output shows good linearity up to 2.85V(10dB) [Spec.2.5Vpp], but
after that it shows non-linear behavior. Also lower part of waveform has
distortion.

2.85V(10dB)

48mV(40dB)
0.01nC

4.8V(Att.:0dB)
corresponds
to the BPM
output at 1nC.

497mV(20dB)
0.1nC
10ADC input circuitry㩷䇭㪈㪏㪢㪈㪉ဳ㩷㪣㫀㫅㪸㪺㪙㪧㪤䇭㪘㪛㪚౉ജㇱ㩷ቯᢙᄌᦝ䊶೨㪆 ᓟ䈱․ᕈ䋲䋰䋱䋳䋯䋴䋯䋲䇭䇭䊂䉳䊁䉾䉪䉴⎇ⓥᚲ䇭ጊ↰㪎㪏㪇㫄㪭㫇㪄㫇㩷㸢㪋㪇㪇㫄㪭㫇㪄㫇䇭䊶㪩㪙㪄㪙㪧㪝౉ജ䋺㪊㪇㪇㪤㪟㫑䊶㪇㪻㪙㫄㩷㪚㪮䇭䊶㪩㪝㪄㪙㪧㪝࿁〝䋺㪧㫉㪼㪘㪫㪫䋺㪈㪉㪻㪙䇭䇭㩷㩷䇭䇭䇭䇭䇭䇭䇭㩷㩷㪧㫆㫊㫋㪘㪫㪫䋺㪈㪉㪻㪙-4dB IL: -0.4dB

㪋㪋㪇㫄㪭㫇㪄㫇㪊㪇㪇㪤㪟㫑㪚㪮㩷㪈㪊㪇㪇㫄㪭㫇㪄㫇+6dB㪌㪇㪇㫄㪭㫇㪄㫇㩷㸢㪊㪋㪇㫄㪭㫇㪄㫇㪏㪉㪇㫄㪭㫇㪄㫇㩷㸢㪋㪊㪇㫄㪭㫇㪄㫇㪏㪉㪇㫄㪭㫇㪄㫇㩷㸢㪋㪊㪇㫄㪭㫇㪄㫇㪎㪋㪇㫄㪭㫇㪄㫇㩷㪏㪍㪇㫄㪭㫇㪄㫇㩷㪘㪛㪚㪂౉ജ๟ᵄᢙ․ᕈ㽲䇭࿁〝ቯᢙᄌᦝ೨

ADL5562
Po1dB=4.9Vpp(1dB compression point)-> corresponding input level is 2.46Vpp (11.8dBm).
㩷㪘㪛㪚㪂౉ജ๟ᵄᢙ․ᕈ
䇭࿁〝ቯᢙᄌᦝᓟ

Acceptable input power:
11.8dBm+4dB+0.4dB=16.2dBm (4.08Vpp)

11

Linearity check (2)••Semi-Log plot of ADC output peak-peak difference v.s. Attenuator setting.
ch1, ch2 has x3 (+10dB) gain with snubber circuit.
– Observed ADC over level at 10dB setting for ch1, ch2 at lower limit (ADC reading is 0).
– At 0-5dB, ch3 and ch4 have been saturated.
– In this setting, >10dB attenuator setting is required to keep linearity.

12Linearity check (2)••To check it more precisely, integration of ADC reading (same manner tocalculate position resolution) v.s. attenuator setting is shown.
Also at lower than 10dB, it seems saturation.

13

Folding noise at ADC•Tails over the Nyquist window (250MHz - 375MHz) become folding noise.

50MHzPower (folded(dBm) signal)

300MHz(signal)

BPF
Spectrum
Folding noise
125(Nyquist)

250 300 375(fs)

500

625

Frequency(MHz) 14

Frequency response of the Band Pass Filter(S21)

250MHz375MHz

15

Frequency response of the Band Pass Filter(S21)
300MHz900MHz

16

Double Pulse test

• To test in more realistic conditions, two bunch signal isemulated by combining 100ns (20m) delayed and 2ns delayed
signal. 50 events has been taken with this setting.
– Att. Pre:8dB, Post:0dB, 40dB+ Additional: 20dB
– Data: ~ryo/vxworks/work/data/2013June19_exPulsar1kV_no2_doubled/
100ns(20m)VPulsar

40dB
Att.

1:2
Variable
Att.x2

1:22ns1:2

−B−BBPM
Readout(Pre:8dB
Post:0dB)

Pulse
Gen.
1st

2nd

ch1, 2(X)

12.2um

13.6umch3, 4(Y)

9.5um

17

Harmonics (600, 900MHz) reduction
with external LPF• When 300MHz CW input, double harmonic (600MHz), triple
harmonic (900MHz) were observed at about -15dB down tothe fundamental.
• When LPF (Mini Circuit VLFX-300) is inserted at BPF output,
harmonics have been suppressed to almost the BG level(>53dB suppression). In this setting 100 events data weretaken.
– Att. Pre:8dB, Post:0dB, 40dB+ Additional: 20dB

– Data: ~ryo/vxworks/work/data/2013June20_exPulsar1kV_no1/
1st

2nd

ch1, 2(X)

11.9um

14.4umch3, 4(Y)

9.8um• No significant difference were observed.

18

Beam Test
• As we can get about 10um position resolution constantlywith pulsar, we confirmed it with beam signal.
• Beam signal were divided to two input signal to emulate
ideal (no beam position jitter) beam signal.
20m
1:2

sp34-4-1 (X+)
sp34-4-3 (X-)

EVR(3sub)

1:2

BPM
Readout(Pre:8dB
Post:0dB)

TTL/NIM

19Beam Test (cont’d)•300events data were taken.
– @3-2, PFE 5Hz, 0.3nC– Att. Pre:8dB, Post:0dB <= Set this value to keep input <3Vpp.
– Data: ~ryo/vxworks/work/data/2013June19_beam_ch12fanout_doubled_ch34_fanout/

1st

2nd

ch1, 2(X)

11.9um

14.4umch3, 4(Y)

9.8um• At previous test (May 29th):– @3-2, PFE 1Hz, 0.5nC– Att. Pre:0dB, Post:0dB single pulse– Data: ~ryo/vxworks/work/data/2013May29_beam_ch12fanout_ch34fanout/•ch1, 2(X)

53.8umch3, 4(Y)

30.7umConfirmed that the worse position resolution were caused by input
saturation.

20

Beam test (cont’d)
2013June19 @3-2 run1 X

2013June19 @3-2 run1 Y
nameh1

4540
35

nameh2

Entries

300

Mean

192.5

RMS

9.146

Underflow

0Overflow

0306050

Entries300

Mean-7.778

RMS

13.22

Underflow

0Overflow

040

2530

201520101050501001502002503003500-150-100-5005010015021Beam Test (cont’d)• 100 events were taken with 0.45nC.
– Att. Pre:8dB, Post:0dB, 40dB+ Additional: 20dB

– Data:~ryo/vxworks/work/data/2013June19_beam_ch12fanout_doubled_ch34_fanout-no2/– Event#59 were rejected from analysis because it contains ADC
malfunction.

•1st

2nd

ch1, 2(X)

5.7um

8.2um

ch3, 4(Y)

5.1um

Better position resolution than 0.3nC. Position resolution may be limited bysignal source S/N. (i.e. 1kV pulsar might have not a good S/N than highcharge beam.)22

#59 event data•

Suddenly waveform sign were inverted after time > 288• Have to check ADC clock delay IC.

23