PCI-DAS64/M2/16

Specifications

Document Revision 1.0, February, 2010
© Copyright 2010, Measurement Computing Corporation

Specifications
Typical for 25 °C unless otherwise specified.
Specifications in italic text are guaranteed by design.

Analog input
Table 1. Analog input specifications
A/D converter type
Resolution
Number of channels
Input ranges(software programmable)
Polarity
A/D pacing(software programmable)

Burst mode
A/D gate sources
A/D gating modes

A/D trigger sources
A/D triggering modes

Data transfer
Configuration memory
Channel/gain queue
A/D conversion time
Calibration

Sub-ranging sampling ADC
16 bits
32 differential or 64 single-ended, software selectable±5 V, ±2.5 V, ±1.25 V, ±0.625 V, 0 to 5 V, 0 to 2.5 V, 0 to 1.25 V
Unipolar/bipolar, software selectable Internal counter – ASIC External source (A/D external pacer). The total number of sample clocks must be at least
5 greater than the total number of samples desired. This is required to accommodate thepipelined architecture of the ADC.
 Software polled
Software selectable option. Valid for a fixed input range only.
Burst rate = 667 nS.
 External digital (A/D pacer gate)
 External analog (analog trigger in)External digital: Programmable, active high or active low, level or edge
External analog: Software-configurable for:
 Above or below reference Positive or negative hysteresis
 In or out of window.
Trigger levels set by DAC0 and/or DAC1.
 External digital (A/D start trigger in and A/D stop trigger in) External analog (Analog Trigger In)
 External digital: Software-configurable for rising or falling edge.
 External analog: Software-configurable for positive or negative slope. Trigger levels set
by DAC0 and/or DAC1.
 Pre-/post-trigger: Unlimited number of pre-trigger samples, 16 Meg post-trigger
samples. Compatible with both digital and analog trigger options.
 From 8 k RAM buffer via DMA (demand or non-demand mode) using scatter gather.
 Programmed I/O
8 K words
Up to 8 K elements. Programmable channel, gain, and offset.
500 nS
Auto-calibration, calibration factors for each range stored on board in non-volatile RAM.

1

PCI-DAS64/M2/16

Specifications

System throughput
Table 2. System throughput specifications
Condition

Calibration coefficients

Max ADCrate

1. Single channel, single input range.
2. Multiple-channel, single-input range: ±5 V,±2.5 V, ±1.25 V, 0 to 5 V, 0 to 2.5 V
3. Multiple channel, single input range: ±0.625 V, 0
to 1.25 V
4. Single channel, multiple input ranges.

Per specified range
Per specified range

2.0 MS/s
1.5 MS/s

Per specified range

750 kS/s

Default to value for cbAInScan() range

500 kS/s

5. Multiple channels, multiple ranges. All samples in
unipolar or bipolar bode.
6. Multiple channels, multiple ranges. All samples in
unipolar and/or bipolar bode.
7. Multiple-channel, switching unipolar/bipolarmode, single-input range.

Default to value for cbAInScan() range

500 kS/s

Default to value for cbAInScan() range

500 kS/s

Default to value for cbAInScan() range

750 kS/s

Note 1:For conditions 1-3, specified accuracy is maintained at rated throughput. Conditions 4-7 apply
calibration coefficients which correspond to the range value selected in cbAInScan(). These
coefficients remain unchanged throughout the scan. Errors of up to 25 counts may be incurred
when switching gains while in bipolar or unipolar mode only (conditions 4 and 5). Errors of up to
500 counts may be incurred when mixing unipolar/bipolar modes (conditions 6 and 7).

Accuracy
A 100 kS/s sampling rate, single-channel operation and a 60-minute warm-up. Accuracies are listed for
operational temperatures within ±2ºC of internal calibration temperature. Calibrator test source high side tied tochannel 0 and low side tied to low-level ground at the user connector
Table 3. Analog input — absolute accuracy specifications
Range

Absolute accuracy±5.000 V±2.500 V±1.250 V±0.625 V
0 V to +5.000 V
0 V to +2.500 V
0 V to +1.250 V±6.0 LSB±8.0 LSB±8.0 LSB±10.0 LSB
±8.0 LSB±11.0 LSB
±13.0 LSB
Table 4. Analog input — typical accuracy specifications

Range

Typical accuracy±5.000 V±2.500 V±1.250 V±0.625 V
0 V to +5.000 V
0 V to +2.500 V
0 V to +1.250 V±5.5 LSB±7.5 LSB±7.5 LSB±9.5 LSB±7.5 LSB±10.5 LSB
±12.5 LSB

Each PCI-DAS64/M2/16 is tested at the factory to assure the board’s overall error does not exceed accuracy
limits shown in Table 3.

2

PCI-DAS64/M2/16

Specifications

Typical accuracy is derived directly from the various component typical errors. The information in Table 4
assumes that each of the errors contributes in the same direction.
Table 5. Analog input — accuracy components specifications
Range

Gain error

Offset error

DLE

ILE

±5.000 V±2.500 V±1.250 V±0.625 V
0 to + 5.000 V
0 to + 2.500 V
0 to + 1.250 V±3.0 max, ±2.0 typ±3.0 max, ±2.0 typ±3.0 max, ±2.0 typ±5.0 max, ±4.0 typ±4.0 max, ±3.0 typ±6.0 max, ±5.0 typ±6.0 max, ±5.0 typ±3.0 max, ±2.0 typ±5.0 max, ±4.0 typ±5.0 max, ±4.0 typ±5.0 max, ±4.0 typ±4.0 max, ±3.0 typ±5.0 max, ±4.0 typ±5.0 max, ±4.0 typ±1.0 max, ±0.5 typ±1.0 max, ±0.5 typ±1.0 max, ±0.5 typ±1.0 max, ±0.5 typ±1.0 max, ±0.5 typ±1.0 max, ±0.5 typ±1.0 max, ±0.5 typ±2 max, ±1.0 typ±2 max, ±1.0 typ±2 max, ±1.0 typ±2 max, ±1.0 typ±2 max, ±1.0 typ±2 max, ±1.0 typ±2 max, ±1.0 typ

As shown in Table 5, total board error is a combination of gain, offset, differential linearity error (DLE), andintegral linearity error (ILE). The theoretical worst-case error of the board can be calculated by summing thesecomponent errors. Worst-case errors are realized only in the unlikely event that each of the component errors
are at their maximum level, and causing error in the same direction.

Crosstalk
Crosstalk is defined here as the influence of one channel upon another when scanning two channels at the
maximum rate. A full-scale 100 Hz triangle wave is input on channel 1, and channel 0 is tied to analog groundat the 100-pin user connector. Table 6 summarizes the influence of channel 1 on channel 0 with the effects ofnoise removed. The residue on channel 0 is described in LSBs.
Table 6. Crosstalk specifications
Range

Crosstalk (LSB pk-pk)

Per channel rate (kS/s)

ADC rate (kS/s)±5.000 V±2.500 V±1.250 V±0.625 V
0 V to + 5.000 V
0 V to + 2.500 V
0 V to + 1.250 V

15
15
20
8
15
20
8

750
750
750
375
750
750
375

1500
1500
1500
750
1500
1500
750

Table 7. Analog input drift specifications
Analog input full-scale gain drift
Analog input zero drift
Overall analog input drift
Common mode range
CMRR @ 60Hz
Input leakage current
Input impedance
Absolute maximum input voltage
Warm-up time

+0.3 LSB/°C typical+2.1 LSB/°C typical±2.4 LSB/°C typical±5 V-90 dB
2.3 nA
10 x 1011 Ω±15 V
60 minutes

3

PCI-DAS64/M2/16

Specifications

Noise performance
Table 8 summarizes the worst case noise performance for the PCI-DAS64/M2/16. Noise distribution isdetermined by gathering 50 K samples with inputs tied to ground at the user connector. Samples are gathered at
the maximum specified single-channel sampling rate. Specification applies to both single-ended and differential
modes of operation.
Table 8. Noise performance specifications
Range±2 counts±1 count

MaxCounts

LSBrms (Note 2)± 5.000 V± 2.500 V± 1.250 V± 0.625 V
0 to +5.000 V
0 to +2.500 V
0 to +1.250 V

60%
60%
60%
45%
60%
60%
45%

40%
40%
40%
30%
40%
40%
30%

22
24
26
32
24
26
32

3.3
3.6
3.9
4.8
3.6
3.9
4.8

Note 2:RMS noise is defined as the peak-to-peak bin spread divided by 6.6.

Analog output
Table 9. Analog output specifications
Resolution
Number of channels
Voltage range
Monotonicity
Analog output zero drift
Overall analog output drift
Slew rate
Settling time
Current drive
Output short-circuit duration
Output coupling
Output impedancePower up and reset

16-bits2±5 V
Guaranteed monotonic over temperature±1.6 LSB/°C±4.0 LSB/°C
2.5 V/µs
FS step to .0008%: 6µs max, all ranges±15 mA
Indefinite @25 mA
DC
0.1 Ω
DACs cleared to 0 V±75 mV max

Accuracy
Table 10. Analog output — absolute accuracy specifications
Range

Absolute accuracy±5V±16.0 LSB
Table 11 Analog output — accuracy components specifications

Range

Gain error (LSB)

Offset error (LSB)

DLE (LSB)

ILE (LSB)±5.0 V±10.0 max

±5.0 max±1.0 max±1.0 max

Each PCI-DAS64/M2/16 is tested at the factory to assure the board’s overall error does not exceed the absoluteaccuracy limits listed in Table 10.

4

PCI-DAS64/M2/16

Specifications

Analog output pacing and triggering
Table 12. Analog output pacing and triggering specifications
D/A pacing (software-programmable)

D/A gate sources(software-programmable)
D/A gating modes

D/A trigger sources
D/A triggering modes
Data transfer

Internal counter – ASIC
External source (D/A external pacer)
Software paced
External digital (external D/A trigger/pacer gate)
External analog (analog trigger in)External digital: Programmable, active high or active low, level or edge
External analog: Software-configurable for above or below reference. Gatinglevels are set by DAC0 or DAC1.
External digital (external D/A trigger/pacer gate)
Software triggered
External digital: Software-configurable for rising or falling edge.
From 16 k RAM buffer via DMA (demand or non-demand mode) using scattergather.
Programmed I/O
100 kS/s max per channel

Digital input/output
Table 13. Digital I/O specifications
Digital type (main connector)
Configuration
Output high voltage (IOH = -0.4 mA)
Output low voltage (IOL = 8 mA)
Input high voltage
Input low voltage
Digital type (digital I/O connector)
Number of I/O
Configuration

Input high voltage
Input low voltage
Output high voltage (IOH = -2.5 mA)
Output low voltage (IOL = 2.5 mA)
Power-up / reset state
SSH output

SSH polarity

Output: 74LS175
Input: 74LS244
Four inputs, four outputs (DIN0 through DIN3; DOUT0 to DOUT3)
2.7 V min
0.5 V max
2.0 V min, 7 volts absolute max
0.8 V max, –0.5 volts absolute min
82C55
24 (FIRSTPORTA Bit 0 through FIRSTPORTC Bit 7)
2 banks of 8 and 2 banks of 4, or
3 banks of 8 or
2 banks of 8 with handshake
2.0 V min, 5.5 V absolute max
0.8 V max, –0.5 V absolute min
3.0 V min
0.4 V max
Input mode (high impedance)
TTL compatible output, HOLD is asserted from start of the conversion for
Channel 0 through conversion of the last channel in the scan. Available at user
connector (SSH OUT / D/A PACER OUT). This pin is software selectable as
SSH OUT (default) or D/A PACER OUT.
HOLD high (default) or HOLD low, software selectable5

PCI-DAS64/M2/16

Specifications

Interrupts
Table 14. Interrupt specifications
Interrupts
Interrupt enable
ADC interrupt

DAC interrupt sources(software-programmable)

External interrupt

PCI INTA# - Mapped to IRQn via PCI BIOS at boot-time
Programmable through PLX9080
DAQ_ACTIVE:
Interrupt is generated when a DAQ sequence is active.
DAQ_STOP:Interrupt is generated when A/D Stop Trigger In is detected.
DAQ_DONE:Interrupt is generated when a DAQ sequence completes.
DAQ_FIFO_1/4_FULL:
Interrupt is generated when ADC FIFO is ¼ full.
DAQ_SINGLE:
Interrupt is generated after each conversion completes.
DAQ_EOSCAN:
Interrupt is generated after the last channel is converted in
multi-channel scans.
DAQ_EOSEQ:
Interrupt is generated after each interval delay during multichannel scans.
DAC_ACTIVE:
Interrupt is generated when DAC waveform circuitry is active.
DAC_DONE:Interrupt is generated when a DAC sequence completes.
DAC_FIFO_1/4_EMPTY: Interrupt is generated DAC FIFO is ¼ empty.
DAC_HIGH_CHANNEL: Interrupt is generated when the DAC high channel output is
updated.
DAC_RETRANSMIT:
Interrupt is generated when the end of a waveform sequence
has occurred in retransmit mode.
Interrupt is generated via edge-sensitive transition on the External Interrupt pin.
Rising/falling edge polarity software selectable.

Counters
Table 15. Counter specifications
User counter type
Configuration
Counter 1 source
Counter 1 gate
Counter 1 output
Clock input frequency
High pulse width(clock input)
Low pulse width(clock input)
Gate width highGate width low
Input low voltage
Input high voltage
Output low voltage
Output high voltage

82C54
One down counter, 16-bits. Counters 2 and 3 not used.
External, from connector (CTR1 CLK)
Available at connector (CTR1 GATE).
Available at connector (CTR1 OUT).
10 MHz max
30 nS min
50 nS min
50 nS min
50 nS min
0.8 V max
2.0 V min
0.4 V max
3.0 V min6

PCI-DAS64/M2/16

Specifications

Pacer
Table 16. Pacer specifications
ADC pacer type
Configuration
ADC pacer source
ADC pacer gate
ADC pacer out
DAC pacer type
Configuration
DAC pacer source
DAC pacer gate
DAC pacer out

ASIC
One down counter, 24 bits (1 scan interval, 1 sample interval)
40 MHz internal source
Internally controlled by software/hardware trigger.
ADC pacer clock, available at user connector (A/D PACER OUT)ASIC
One down counter, 24 bits (1 scan interval, 1 sample interval)
40 MHz or 100 kHz internal source. Software-selectable.
Internally controlled by software/hardware trigger.
DAC pacer clock. Available at user connector (SSH OUT / D/A PACER OUT). Thispin is software selectable as SSH OUT (default) or D/A PACER OUT.
40 MHz
50 ppmInternal pacer crystal oscillator
Frequency accuracy

Power consumption
Table 17. Power specifications
+5 V
+12 V

2.9 A typical, 3.3 A max
10 mA max.

Environmental
Table 18. Environmental specifications
Operating temperature range
Storage temperature range
Humidity

0 to 50 °C-40 to 100 °C
0 to 95% non-condensing

Mechanical
Table 19. Mechanical specifications
Card dimensions

315 mm (L) x 100.6 mm (W) x 16 mm (H)Main connector and pin out
Table 20. Main connector and pinout specifications
Parameter

Specification

Connector typeCompatible cables

Shielded SCSI 100-pin D-type
C100HD50-x, unshielded ribbon cable. x = 3 or 6 feet.
C100MMS-x, shielded round cable. x = 1, 2, or 3 meters.
CIO-MINI50 (two required)
SCB-50
CIO-TERM100
SCB-100

Compatible accessory products
using the C100HD50-x cableCompatible accessory products
using the C100MMS-x cable7

PCI-DAS64/M2/16

Specifications

Differential mode pin out
Table 21. 32-channel differential mode pin out
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50

Signal Name
GND
CTR1 OUT
CTR1 CLK
CTR1 GATE
DOUT3
DOUT2
DOUT1
DOUT0
DIN3
DIN2
DIN1
DIN0
GND
-12 V
GND
+12 V
CH31 IN LO
CH30 IN LO
CH29 IN LO
CH28 IN LO
CH27 IN LO
CH26 IN LO
CH25 IN LO
CH24 IN LO
CH23 IN LO
CH22 IN LO
CH21 IN LO
CH20 IN LO
CH19 IN LO
CH18 IN LO
CH17 IN LO
CH16 IN LO
LLGND
CH15 IN LO
CH14 IN LO
CH13 IN LO
CH12 IN LO
CH11 IN LO
CH10 IN LO
CH9 IN LO
CH8 IN LO
CH7 IN LO
CH6 IN LO
CH5 IN LO
CH4 IN LO
CH3 IN LO
CH2 IN LO
CH1 IN LO
CH0 IN LO
GND

Pin
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100

Signal Name
GND
EXTERNAL INTERRUPT
A/D EXTERNAL PACER
A/D STOP TRIGGER IN
A/D START TRIGGER IN
ANALOG TRIGGER IN
A/D PACER GATE
A/D PACER OUTSSH OUT / D/A PACER OUT
EXTERNAL D/A TRIGGER/PACER GATE
D/A EXTERNAL PACER
PC +5 VD/A OUT 1
D/A GND 1
D/A OUT 0
D/A GND 0
CH31 IN HI
CH30 IN HI
CH29 IN HI
CH28 IN HI
CH27 IN HI
CH26 IN HI
CH25 IN HI
CH24 IN HI
CH23 IN HI
CH22 IN HI
CH21 IN HI
CH20 IN HI
CH19 IN HI
CH18 IN HI
CH17 IN HI
CH16 IN HI
LLGND
CH15 IN HI
CH14 IN HI
CH13 IN HI
CH12 IN HI
CH11 IN HI
CH10 IN HI
CH9 IN HI
CH8 IN HI
CH7 IN HI
CH6 IN HI
CH5 IN HI
CH4 IN HI
CH3 IN HI
CH2 IN HI
CH1 IN HI
CH0 IN HI
LLGND

8PCI-DAS64/M2/16

Specifications

Single-ended mode pin out
Table 22. 64-channel single-ended mode pin out
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50

Signal name
GND
CTR1 OUT
CTR1 CLK
CTR1 GATE
DOUT3
DOUT2
DOUT1
DOUT0
DIN3
DIN2
DIN1
DIN0
GND
-12 V
GND
+12 V
CH63 IN
CH62 IN
CH61 IN
CH60 IN
CH59 IN
CH58 IN
CH57 IN
CH56 IN
CH55 IN
CH54 IN
CH53 IN
CH52 IN
CH51 IN
CH50 IN
CH49 IN
CH48 IN
LLGND
CH47 IN
CH46 IN
CH45 IN
CH44 IN
CH43 IN
CH42 IN
CH41 IN
CH40 IN
CH39 IN
CH38 IN
CH37 IN
CH36 IN
CH35 IN
CH34 IN
CH33 IN
CH32 IN
GND

Pin
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100

Signal name
GND
EXTERNAL INTERRUPT
A/D EXTERNAL PACER
A/D STOP TRIGGER IN
A/D START TRIGGER IN
ANALOG TRIGGER IN
A/D PACER GATE
A/D PACER OUTSSH OUT / D/A PACER OUT
EXTERNAL D/A TRIGGER/PACER GATE
D/A EXTERNAL PACER
PC +5 VD/A OUT 1
D/A GND 1
D/A OUT 0
D/A GND 0
CH31 IN
CH30 IN
CH29 IN
CH28 IN
CH27 IN
CH26 IN
CH25 IN
CH24 IN
CH23 IN
CH22 IN
CH21 IN
CH20 IN
CH19 IN
CH18 IN
CH17 IN
CH16 IN
LLGND
CH15 IN
CH14 IN
CH13 IN
CH12 IN
CH11 IN
CH10 IN
CH9 IN
CH8 IN
CH7 IN
CH6 IN
CH5 IN
CH4 IN
CH3 INCH2 IN
CH1 IN
CH0 IN
LLGND

9PCI-DAS64/M2/16

Specifications

Digital input/output connector and pin out
Table 23. Digital I/O connector specifications
Connector type
Connector compatibility
Compatible cableCompatible accessory products

40-pin header
Translates to standard CIO-DIO24 type using BP40-37
C40FF-2
CIO-MINI40
Table 24. Digital I/O connector pin out

Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

Signal nameNC
NC
FIRSTPORTB Bit 7
FIRSTPORTB Bit 6
FIRSTPORTB Bit 5
FIRSTPORTB Bit 4
FIRSTPORTB Bit 3
FIRSTPORTB Bit 2
FIRSTPORTB Bit 1
FIRSTPORTB Bit 0
DIG GNDNC
DIG GNDNC
DIG GNDNC
DIG GND
PC +5 VDIG GND
NC

Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

10

Signal name
PC +5 VDIG GND
FIRSTPORTC Bit 7
FIRSTPORTC Bit 6
FIRSTPORTC Bit 5
FIRSTPORTC Bit 4
FIRSTPORTC Bit 3
FIRSTPORTC Bit 2
FIRSTPORTC Bit 1
FIRSTPORTC Bit 0
FIRSTPORTA Bit 7
FIRSTPORTA Bit 6
FIRSTPORTA Bit 5
FIRSTPORTA Bit 4
FIRSTPORTA Bit 3
FIRSTPORTA Bit 2
FIRSTPORTA Bit 1
FIRSTPORTA Bit 0NC
NCMeasurement Computing Corporation
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Suite 1008
Norton, Massachusetts 02766(508) 946-5100
Fax: (508) 946-9500
E-mail: info@mccdaq.com
www.mccdaq.com
PCI-DAS64-M2-16-spec.doc