PCI-DAS6052
Analog and Digital I/O

User's Guide

Document Revision 7A
December 2012
© Copyright 2012

Trademark and Copyright Information
Measurement Computing Corporation, InstaCal, Universal Library, and the Measurement Computing logo areeither trademarks or registered trademarks of Measurement Computing Corporation. Refer to the Copyrights &Trademarks section on mccdaq.com/legal for more information about Measurement Computing trademarks.
Other product and company names mentioned herein are trademarks or trade names of their respective
companies.
© 2012 Measurement Computing Corporation. All rights reserved. No part of this publication may be
reproduced, stored in a retrieval system, or transmitted, in any form by any means, electronic, mechanical, by
photocopying, recording, or otherwise without the prior written permission of Measurement Computing
Corporation.
NoticeMeasurement Computing Corporation does not authorize any Measurement Computing Corporation product for
use in life support systems and/or devices without prior written consent from Measurement Computing
Corporation. Life support devices/systems are devices or systems that, a) are intended for surgical implantation
into the body, or b) support or sustain life and whose failure to perform can be reasonably expected to result ininjury. Measurement Computing Corporation products are not designed with the components required, and are
not subject to the testing required to ensure a level of reliability suitable for the treatment and diagnosis ofpeople.

HM PCI-DAS6052.docx

Table of Contents
Preface

About this User's Guide ....................................................................................................................... 5
What you will learn from this user's guide ......................................................................................................... 5
Conventions in this user's guide ......................................................................................................................... 5
Where to find more information ......................................................................................................................... 5
Chapter 1

Introducing the PCI-DAS6052 .............................................................................................................. 6
Overview: PCI-DAS6052 features ..................................................................................................................... 6
Chapter 2

Installing the PCI-DAS6052 .................................................................................................................. 7
What comes with your PCI-DAS6052 shipment? .............................................................................................. 7
Hardware .......................................................................................................................................................................... 7
Documentation .................................................................................................................................................................. 7
Optional components ........................................................................................................................................................ 7

Unpacking the PCI-DAS6052 ............................................................................................................................ 8
Installing the software ........................................................................................................................................ 8
Installing the hardware ....................................................................................................................................... 8
Configuring the hardware ................................................................................................................................... 8

Differential input mode ..................................................................................................................................................... 9Single-ended input mode .................................................................................................................................................. 9
Non-referenced single-ended input mode ......................................................................................................................... 9
DAQ-Sync configuration .................................................................................................................................................. 9Signal connections ............................................................................................................................................ 10

SCSI connector ................................................................................................................................................................10
DAQ-Sync connector .......................................................................................................................................................13
Field wiring, signal termination and conditioning ...........................................................................................................14

Chapter 3

Functional Details ...............................................................................................................................15
Basic architecture ............................................................................................................................................. 15
Auxiliary input & output interface ...................................................................................................................................15
DAQ-Sync signals ...........................................................................................................................................................16

DAQ signal timing............................................................................................................................................ 18

SCANCLK signal ............................................................................................................................................................18
A/D START TRIGGER signal ........................................................................................................................................18
A/D STOP TRIGGER signal ...........................................................................................................................................19
STARTSCAN signal ........................................................................................................................................................20
SSH signal .......................................................................................................................................................................20
A/D CONVERT signal ....................................................................................................................................................21
A/D PACER GATE signal ...............................................................................................................................................21
A/D EXTERNAL TIME BASE signal ............................................................................................................................21
A/D STOP signal .............................................................................................................................................................22
ATRIG signal ...................................................................................................................................................................22

Waveform generation timing signals ................................................................................................................ 27
D/A START TRIGGER signal ........................................................................................................................................27
D/A CONVERT signal ....................................................................................................................................................27
D/A EXTERNAL TIME BASE signal ............................................................................................................................28

General-purpose counter signal timing ............................................................................................................. 28
CTR1 CLK signal ............................................................................................................................................................28
CTR1 GATE signal .........................................................................................................................................................29
CTR1 OUT signal ............................................................................................................................................................29
CTR2 CLK signal ............................................................................................................................................................29
CTR2 GATE signal .........................................................................................................................................................30
CTR2 OUT signal ............................................................................................................................................................30

3

PCI-DAS6052 User's Guide

Chapter 4

Calibrating the Board ..........................................................................................................................31
Introduction ...................................................................................................................................................... 31
Calibration theory ............................................................................................................................................. 31
Chapter 5

Specifications ......................................................................................................................................33
Analog input ..................................................................................................................................................... 33
Accuracy ..........................................................................................................................................................................34
Settling time .....................................................................................................................................................................35
Parametrics ......................................................................................................................................................................36
Noise performance ...........................................................................................................................................................36

Analog output ................................................................................................................................................... 37
Analog output pacing and triggering ................................................................................................................................38
Analog output external reference input (D/A EXTREF)..................................................................................................38

Analog trigger ................................................................................................................................................... 39
Analog I/O calibration ...................................................................................................................................... 39
Digital I/O ......................................................................................................................................................... 39
Interrupts........................................................................................................................................................... 40
Counters ............................................................................................................................................................ 40
Configurable AUXIN<5:0>, AUXOUT<2:0> external trigger/clocks ............................................................. 41
DAQ-Sync inter-board triggers/clocks ............................................................................................................. 42
Power consumption .......................................................................................................................................... 42
Environmental .................................................................................................................................................. 42
Mechanical ....................................................................................................................................................... 42
DAQ-Sync connector ....................................................................................................................................... 42
SCSI connector ................................................................................................................................................. 43
Declaration of Conformity ..................................................................................................................464

Preface

About this User's Guide
What you will learn from this user's guideThis user's guide describes the Measurement Computing PCI-DAS6052 data acquisition device and lists device
specifications.

Conventions in this user's guide
For more information
Text presented in a box signifies additional information related to the subject matter.
Caution! Shaded caution statements present information to help you avoid injuring yourself and others,
damaging your hardware, or losing your data.
bold text

Bold text is used for the names of objects on a screen, such as buttons, text boxes, and check boxes.

italic text

Italic text is used for the names of manuals and help topic titles, and to emphasize a word or phrase.

Where to find more information
Additional information about PCI-DAS6052 hardware is available on our website at www.mccdaq.com. You
can also contact Measurement Computing Corporation by phone, fax, or email with specific questions.
Phone: 508-946-5100 and follow the instructions for reaching Tech Support
Fax: 508-946-9500 to the attention of Tech Support
Email: techsupport@mccdaq.com
Knowledgebase: kb.mccdaq.com

If you need to program at the register level in your application, refer to the STC Register Map for the PCIDAS6000 Series. This document is available at www.mccdaq.com/registermaps/RegMapSTC6000.pdf.

5Chapter 1

Introducing the PCI-DAS6052
Overview: PCI-DAS6052 features
This manual explains how to install and use the PCI-DAS6052 board.
The PCI-DAS6052 board has eight lines of digital I/O, and two digital-to-analog outputs. It provides either
eight differential or 16 single-ended analog inputs with 16-bit resolution. Input ranges are either bipolar or
unipolar. Bipolar input ranges are ±10V, ±5V, ±2.5V, ±1V, ±0.5V, ±0.25V, ±0.1V and ±0.05V. Unipolar input
ranges are 0 to 10V, 0 to 5V, 0 to 2V, 0 to 1V, 0 to 0.5V, 0 to 0.2V and 0 to 0.1V. The input ranges aresoftware-selectable.
The board has nine user-configurable trigger/clock/gate pins that are available at a 100-pin I/O connector. Six
pins are configurable as inputs and three are configurable as outputs. Refer to Chapter 3 ("Functional Details")
and Chapter 5 ("Specifications") for more information.
The PCI-DAS6052 provides triggering and synchronization capability. There are five trigger/strobes and asynchronizing clock provided on a 14-pin header. Refer to Chapter 2 ("Installing the Board") and Chapter 5("Specifications") for more information on these signals.
Interrupts can be generated by up to seven ADC sources and four DAC sources. Interrupt sources are listed in
Chapter 5 ("Specifications").
The PCI-DAS6052 board contains an 82C54 counter chip, which consists of three 16-bit counters. Clock, gate,
and output signals from two of the three counters are available on the 100-pin I/O connector. The third counteris used internally.

6

Chapter 2

Installing the PCI-DAS6052
What comes with your PCI-DAS6052 shipment?
The following items are shipped with the PCI-DAS6052.

Hardware

PCI-DAS6052

Documentation
In addition to this hardware user's guide, you should also receive the Quick Start Guide. This booklet provides
an overview of the MCC DAQ software you received with the device, and includes information about installingthe software. Please read this booklet completely before installing any software or hardware.

Optional components
If you ordered any of the following products with your board, they should be included with your shipment.


CablesC100HD50-x

C100MMS-x

CDS-14-xSignal termination and conditioning accessories
MCC provides signal termination products for use with the PCI-DAS6052. Refer to the "Field wiring,
signal termination and conditioning" section on page 14 for a list of compatible accessory products.

7

PCI-DAS6052 User's Guide

Installing the PCI-DAS6052

Unpacking the PCI-DAS6052
As with any electronic device, you should take care while handling to avoid damage from static
electricity. Before removing the PCI-DAS6052 from its packaging, ground yourself using a wrist strap or bysimply touching the computer chassis or other grounded object to eliminate any stored static charge.
If any components are missing or damaged, notify Measurement Computing Corporation immediately byphone, fax, or e-mail:

Phone: 508-946-5100 and follow the instructions for reaching Tech Support.
Fax: 508-946-9500 to the attention of Tech Support
Email: techsupport@mccdaq.com

For international customers, contact your local distributor. Refer to the International Distributors section on our
web site at www.mccdaq.com/International.

Installing the software
Refer to the Quick Start Guide for instructions on installing the software on the MCC DAQ CD. This booklet isavailable in PDF at www.mccdaq.com/PDFmanuals/DAQ-Software-Quick-Start.pdf..

Installing the hardware
The PCI-DAS6052 board is completely plug-and-play. There are no switches or jumpers to set. Configuration iscontrolled by your system's BIOS. To install your board, follow the steps below.
Install the MCC DAQ software before you install your board
The driver needed to run your board is installed with the MCC DAQ software. Therefore, you need to install the
MCC DAQ software before you install your board. Refer to the Quick Start Guide for instructions on installingthe software.
1.

Turn your computer off, open it up, and insert your board into any available PCI slot.

2.

Close your computer and turn it on.

A dialog box pops up as the system loads indicating that new hardware has been detected. If theinformation file for this board is not already loaded onto your PC, you will be prompted for the disk
containing this file. The MCC DAQ software contains this file. If required, insert the Measurement
Computing Data Acquisition Software CD and click OK.
3.

To test your installation and configure your board, run the InstaCal utility installed in the previous section.
Refer to the Quick Start Guide that came with your board for information on how to initially set up andload InstaCal.

Allow your computer to warm up for at least 15 minutes before acquiring data with this board. The high speed
components used on the board generates heat, and it takes this amount of time for a board to reach steady state
if it has been powered off for a significant amount of time.

Configuring the hardware
All hardware configuration options on the PCI-DAS6052 are software controlled. You can select some of theconfiguration options using InstaCal, such as the analog input configuration (16 single-ended or eight
differential channels), the edge used for triggering when using an external pacer, and the source for the two
independent counters. Once selected, any program that uses the Universal Library will initialize the hardware
according to these selections.
Following is an overview of the available hardware configuration options for this board. There is additional
general information regarding analog signal connection and configuration in the Guide to Signal Connections(available on our web site at www.mccdaq.com/signals/signals.pdf).

8

PCI-DAS6052 User's Guide

Installing the PCI-DAS6052

Differential input mode
When all channels are configured for differential input mode, eight analog input channels are available. In thismode, the input signal is measured with respect to the low input. The input signal is delivered through threewires:
The wire carrying the signal to be measured connects to CH# IN HI.
The wire carrying the reference signal connects to CH# IN LO.
The third wire is connected to LLGND.

Differential input mode is the preferred configuration for applications in noisy environments, or when the signal
source is referenced to a potential other than PC ground.

Single-ended input mode
When all channels are configured for single-ended input mode, 16 analog input channels are available. In thismode, the input signal is referenced to the board’s signal ground (LLGND). The input signal is delivered
through two wires:

The wire carrying the signal to be measured connects to CH# IN HI.
The second wire is connected to LLGND.

Non-referenced single-ended input modeThis mode is a compromise between differential and single-ended modes. It offers some of the advantages ofeach mode. Using non-referenced single-ended mode, you can still get noise rejection, but not the limitation in
the number of channels resulting from a fully differential configuration. The possible downside is that theexternal reference input must be the same for every channel. It is equivalent to configuring the inputs fordifferential mode and then tying all of the low inputs together and using that mode as the reference input.
When configured for non-referenced single-ended input mode, 16 analog input channels are available. In thismode, each input signal is not referenced to the board’s ground, but to a common reference signal (AISENSE).
The input signal is delivered through three wires:

The wire carrying the signal to measure connects to CH# IN HI.
The wire carrying the reference signal connects to AISENSE.
The third wire is connected to LLGND.

This mode is useful when the application calls for differential input mode but the limitation on channel countprevents it.

DAQ-Sync configuration
You can interconnect multiple boards in the PCI-DAS6000 series to synchronize data acquisition or data output.
To do this, order and install a CDS-14-x cable at the DAQ-Sync connectors (P2) between the boards to besynchronized.
The "x" in the CDS-14-x part number specifies the number of connectors available on the cable, and therefore,
the number of boards you can interconnect. Using a CDS-14-2, you can connect two PCI-DAS6000 seriesboards together for I/O synchronization. Using a CDS-14-3, you can synchronize three boards, and so on. You
can connect up to five PCI-DAS6000 series boards. A CDS-14-3 cable is shown in Figure 3 on page 14.
By default, all DAQ-Sync connectors are configured as inputs (slave mode). In order to be useful, one board
must be set through software to serve as the master, and the signal sources of the slave boards must be defined.

9

PCI-DAS6052 User's Guide

Installing the PCI-DAS6052

Signal connections
SCSI connector
Board connectors, cables, accessory equipment
Connector typeCompatible cables
Compatible accessory products(with the C100HD50-x cable)

Compatible accessory products(with the C100MMS-x cable)

Shielded SCSI 100 D-type
C100HD50-x, unshielded ribbon cable. x = 3 or 6 feet
C100MMS-x, shielded round cable. x = 1, 2, or 3 meters
ISO-RACK16/P
ISO-DA02/P
BNC-16SE
BNC-16DI
CIO-MINI50
CIO-TERM100
SCB-50
SCB-100

10

PCI-DAS6052 User's Guide

Installing the PCI-DAS6052

8-channel differential mode pinout
Signal Name
Pin
GND
100
CTR2 OUT99
CTR2 GATE98
CTR2 CLK97
GND
96
CTR1 OUT
95
CTR1 GATE
94
CTR1 CLK
93
DIO7
92
DIO6
91
DIO5
90
DIO4
89
DIO3
88
DIO2
87
DIO1
86
DIO0
85
n/c
84
n/c
83
n/c
82
n/c
81
n/c
80
n/c
79
n/c
78
n/c
77
n/c
76
n/c
75
n/c
74
n/c
73
n/c
72
n/c
71
n/c
70
n/c
69
n/c
68
n/c
67
n/c
66
n/c
65
n/c
64
n/c
63
n/c
62
n/c
61
n/c
60
n/c
59
n/c
58
n/c
57
n/c
56
n/c
55
n/c
54
n/c
53
n/c
52
n/c
51
PCI slot ↓

Pin
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

11

Signal NameGND
AUXIN5 / A/D PACER GATEAUXIN4 / D/A START TRIGGER
AUXIN3 / D/A UPDATEAUXIN2 / A/D STOP TRIGGER
AUXIN1 / A/D START TRIGGER
D/A EXTREF
AUXIN0 / A/D CONVERT / ATRIGAUXOUT2 / SCANCLKAUXOUT1 / A/D PACER OUT
AUXOUT0 / D/A PACER OUT
PC +5 VD/A OUT1
D/A GND
D/A OUT 0
AISENSE
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
LLGND
CH7 IN LO
CH7 IN HI
CH6 IN LO
CH6 IN HI
CH5 IN LO
CH5 IN HI
CH4 IN LO
CH4 IN HI
CH3 IN LO
CH3 IN HI
CH2 IN LO
CH2 IN HI
CH1 IN LO
CH1 IN HI
CH0 IN LO
CH0 IN HI
LLGND

PCI-DAS6052 User's Guide

Installing the PCI-DAS6052

16-channel single-ended pinout
Signal Name
Pin
GND
100
CTR2 OUT99
CTR2 GATE98
CTR2 CLK97
GND
96
CTR1 OUT
95
CTR1 GATE
94
CTR1 CLK
93
DIO7
92
DIO6
91
DIO5
90
DIO4
89
DIO3
88
DIO2
87
DIO1
86
DIO0
85
n/c
84
n/c
83
n/c
82
n/c
81
n/c
80
n/c
79
n/c
78
n/c
77
n/c
76
n/c
75
n/c
74
n/c
73
n/c
72
n/c
71
n/c
70
n/c
69
n/c
68
n/c
67
n/c
66
n/c
65
n/c
64
n/c
63
n/c
62
n/c
61
n/c
60
n/c
59
n/c
58
n/c
57
n/c
56
n/c
55
n/c
54
n/c
53
n/c
52
n/c
51
PCI slot ↓

Pin
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

12

Signal NameGND
AUXIN5 / A/D PACER GATEAUXIN4 / D/A START TRIGGER
AUXIN3 / D/A UPDATEAUXIN2 / A/D STOP TRIGGER
AUXIN1 / A/D START TRIGGER
D/A EXTREF
AUXIN0 / A/D CONVERT / ATRIGAUXOUT2 / SCANCLKAUXOUT1 / A/D PACER OUT
AUXOUT0 / D/A PACER OUT
PC +5 VD/A OUT1
D/A GND
D/A OUT 0
AISENSE
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
LLGND
CH15 IN
CH7 IN
CH14 IN
CH6 IN
CH13 IN
CH5 IN
CH12 IN
CH4 IN
CH11 IN
CH3 IN
CH10 IN
CH2 IN
CH9 IN
CH1 IN
CH8 IN
CH0 INLLGND

PCI-DAS6052 User's Guide

Installing the PCI-DAS6052

Cabling – main I/O connector

Figure 1. C100HD50-x cable

Figure 2-2. C100MMS-x cable

Details on these cables are available on our web site at www.mccdaq.com/products/accessories.aspx.

DAQ-Sync connector
DAQ-Sync connector and cable types
Connector typeCompatible cable

14-pin right-angle 100 mil box header
MCC p/n: CDS-14-x, 14 pin ribbon cable for board-to board DAQ-Sync connection;x = number of boards (Figure 3 shows a CDS-14-3 cable)

13

PCI-DAS6052 User's Guide

Installing the PCI-DAS6052

DAQ-Sync connector pinout (view from top)
Signal Name

Pin

DS A/D START TRIGGER
DS A/D STOP TRIGGER
DS A/D CONVERTDS D/A UPDATEDS D/A START TRIGGER
RESERVEDSYNC CLK

1
3
5
7
9
11
13

■
■
■
■
■
■
■

■
■
■
■
■
■
■

Pin

Signal Name

2
4
6
8
10
12
14

GND
GND
GND
GND
GND
GND
GND

2
1

The red stripe
identifies pin # 1

2
14
1
13

2
14
1
13
14
13

14-pin Ribbon Cable

Figure 3. CDS-14-3 cable

Details on the this cable are available on our web site at www.mccdaq.com/products/accessories.aspx.

Field wiring, signal termination and conditioning
Screw terminal boards and BNC adapters

Use with the C100HD50-x cable:


CIO-MINI50: 50-pin universal screw terminal accessory.
CIO-TERM100: 16×4 screw terminal.
SCB-50 – 50 conductor, shielded signal connection/screw terminal box provides two independent 50-pin
connections.

Use with the C100MMS-x cable:


SCB-100: 100 conductor, shielded signal connection/screw terminal box provides two independent 50-pin
connections.

BNC connector boxes:BNC-16SE: 16-channel single-ended BNC connector box.
BNC-16DI: Eight-channel differential BNC connector box.

Details on these products are available on our web site at www.mccdaq.com/products/screw_terminal_bnc.aspx.
ISO-5B module racks

Use with the C100HD50-x cable:

ISO-RACK16/P: 16-channel isolation module mounting rack.
ISO-DA02/P: Two-channel, 5B module rack.

Details on these products are available on our web site at www.mccdaq.com/products/signal_conditioning.aspx.

14

Chapter 3

Functional Details
Basic architecture
Figure 4 on page 17 is a simplified block diagram of the PCI-DAS6052. This board provides all of thefunctional elements shown in the figure.
The System Timing and Control (STC) is the logical center for all DAQ, DIO, and DAC (if applicable)
operations. It communicates over two major busses: a local bus and a memory bus.
The local bus carries digital I/O data and software commands from the PCI Bus Master. There are two Direct
Memory Access (DMA) channels provided for data transfers to the PC.
Primarily, the memory bus carries A/D and D/A related data and commands. There are three buffer memories
provided on the memory bus:The queue buffer (8K configuration memory) stores programmed channel numbers, gains, and offsets.
The ADC buffer (8K FIFO [First In, First Out]) temporarily stores scanned and converted analog inputs.
The DAC 16K buffer stores data to be output as analog waveforms.

Auxiliary input & output interface
The board's 100-pin I/O connector provides six software-selectable inputs, and three software-selectable
outputs. The signals are user-configurable clocks, triggers and gates. Refer to the "DAQ signal timing" on page
18 for information about these signals and their timing requirements.
The following table lists all of the possible signals and the default signals you use on the nine pins.

15

PCI-DAS6052 User's Guide

Functional Details

Auxiliary I/O signals
I/O Type

Signal Name

Function

AUXIN<5:0> sources(SW selectable)

A/D CONVERT
A/D TIMEBASE IN
A/D START TRIGGER
A/D STOP TRIGGER
A/D PACER GATE
D/A START TRIGGER
D/A UPDATE
D/A TIMEBASE IN
STARTSCAN
SSH

External ADC Convert Strobe (default)
External ADC Pacer Time BaseADC Start Trigger (default)
ADC Stop Trigger (default)
External ADC Gate (default)
DAC Trigger/Gate (default)
DAC Update Strobe (default)
External DAC Pacer Time Base
A pulse indicating the start of conversion.
An active signal that terminates at the start of the lastconversion in a scan.
Indicates the end of a scan
ADC convert pulse (default)
Delayed version of ADC convert (default)
CTR1 clock source
D/A update pulse (default)
CTR2 clock source
ADC Start Trigger Out
ADC Stop Trigger Out
External ADC gate
DAC Start Trigger Out
A/D CONVERT
A/D START TRIGGER
A/D STOP TRIGGER
D/A UPDATE
D/A START TRIGGER
A/D PACER GATE
D/A UPDATE
A/D CONVERTSCANCLKAUXOUT<2:0> sources(SW selectable)

Default selections
summary

A/D STOP
A/D CONVERTSCANCLKCTR1 CLK
D/A UPDATECTR2 CLK
A/D START TRIGGER
A/D STOP TRIGGER
A/D PACER GATE
D/A START TRIGGER
AUXIN0
AUXIN1
AUXIN2
AUXIN3
AUXIN4
AUXIN5
AUXOUT0
AUXOUT1
AUXOUT2

DAQ-Sync signals
The DAQ-Sync hardware provides the capability of triggering or clocking up to four slave boards from a masterboard to synchronize data input and/or output.
The PCI-DAS6052 board provides the capability of inter-board synchronization between boards in the PCIDAS6000 family. There are five trigger/strobes and a synchronizing clock provided on a 14-pin header. The
following signals are available:







DS A/D START TRIGGER
DS A/D STOP TRIGGER
DS A/D CONVERTDS D/A UPDATEDS D/A START TRIGGERSYNC CLK

Except for the SYNC CLK signal, the DAQ-Sync timing and control signals are a subset of the AUXIO signals
available at the 100-pin I/O connector. These versions of the signals are used for board-to-board
synchronization and have the same timing specifications as their I/O connector counterparts. Refer to "DAQ
signal timing" on page 18 for explanations of signals and timing.

16

PCI-DAS6052 User's Guide

Functional Details

Use the SYNC CLCK signal to determine the master/slave configuration of a DAQ-Sync-enabled system. Eachsystem can have one master and up to three slaves. SYNC CLK is the 40 MHz time-base used to derive allboard timing and control. The master provides this clock to the slave boards so that all boards in the DAQ-syncenabled system are timed from the same clock.

Figure 4. Block diagram – PCI-DAS6052

17

PCI-DAS6052 User's Guide

Functional Details

DAQ signal timing
The DAQ timing signals are:











SCANCLK
A/D START TRIGGER
A/D STOP TRIGGER
STARTSCAN
SSH
A/D CONVERT
A/D PACER GATE
A/D EXTERNAL TIME BASE
A/D STOPATRIGSCANCLK signal
SCANCLK is an output signal that may be used for switching external multiplexers. It is a 400 ns wide pulsethat follows the CONVERT signal after a 50 ns delay. This is adequate time for the analog input signal to beacquired so that the next signal may be switched in. The polarity of the SCANCLK signal is programmable. The
default output pin for the SCANCLK signal is AUXOUT2, but any of the AUXOUT pins may be programmed
as a SCANCLK output.
CONVERT

SCANCLKtd

tw

td = 50 ns

tw = 400 ns

Figure 5. SCANCLK signal timing

A/D START TRIGGER signal
Use the A/D START TRIGGER signal for conventional triggering (when you only need to acquire data after a
trigger event). Figure 6 shows the A/D START TRIGGER signal timing for a conventionally triggeredacquisition.

A/D Start Trigger
Start Scan
ConvertScan Counter

4

3

2

1

0

Figure 6. Data Acquisition example for conventional triggering

The A/D START TRIGGER source is programmable and may be set to any of the AUXIN inputs or to the
DAQ-Sync DS A/D START TRIGGER input. The polarity of this signal is also programmable to trigger
acquisitions on either the positive or negative edge.

18

PCI-DAS6052 User's Guide

Functional Details

The A/D START TRIGGER signal is also available as an output and can be programmed to appear at any of the
AUXOUT outputs. See Figure 7 and Figure 8 for A/D START TRIGGER input and output timing
requirements.
twRising Edge Polarity
Falling Edge Polarity

tw = 37.5 ns minimum
Figure 7. A/D START TRIGGER input signal timingtw

tw = 50 ns
Figure 8. A/D START TRIGGER output signal timing

The A/D START TRIGGER signal is also used to initiate pre-triggered DAQ operations (when you need toacquire data just before a trigger event). In most pre-triggered applications, the A/D START TRIGGER signal
is generated by a software trigger. The use of A/D START TRIGGER and A/D STOP TRIGGER in pretriggered DAQ applications is explained next.

A/D STOP TRIGGER signal
Pre-triggered data acquisition continually acquires data into a circular buffer until a specified number ofsamples have been collected after the trigger event. Figure 9 illustrates a typical pre-triggered DAQ sequence.
A/D Start Trigger
A/D Stop Trigger

Don't care

Start Scan
ConvertScan Counter 3

2

1

0

3

2

1

0

3

2

1

Figure 9. Pre-triggered data acquisition example

The A/D STOP TRIGGER signal signifies when the circular buffer should stop and when the specified numberof post trigger samples should be acquired. It is available as an output and an input. By default, it is available at
AUXIN2 as an input but may be programmed for access at any of the AUXIN pins or the DAQ-Sync “DS A/D
STOP TRIGGER” input. It may be programmed for access at any of the AUXOUT pins as an output.
When using the A/D STOP TRIGGER signal as an input, the polarity may be configured for either rising or
falling edge. The selected edge of the A/D STOP TRIGGER signal initiates the post-triggered phase of a pretriggered acquisition sequence.
As an output, the A/D STOP TRIGGER signal indicates the event separating the pre-trigger data from the posttrigger data. The output is an active high pulse with a pulse width of 50 ns. Figure 10 and Figure 11 show the
input and output timing requirements for the A/D STOP TRIGGER signal.

19

PCI-DAS6052 User's Guide

Functional Details

twRising Edge Polarity
Falling Edge Polarity

tw = 37.5 ns minimum
Figure 10. A/D STOP TRIGGER input signal timingtw

tw = 50 ns
Figure 11. A/D STOP TRIGGER output signal timing

STARTSCAN signal
The STARTSCAN output signal indicates when a scan of channels has been initiated. You can program thissignal to be available at any of the AUXOUT pins. The STARTSCAN output signal is a 50 ns wide pulse theleading edge of which indicates the start of a channel scan.
twtw = 50 ns
Figure 12. STARTSCAN start of scan timing

SSH signal
The SSH signal can be used as a control signal for external sample/hold circuits. The SSH signal is a
programmable polarity pulse that is asserted throughout a channel scan. The state of this signal changes after thestart of the last conversion in the scan. The SSH signal may be routed via software selection to any of the
AUXOUT pins. Figure 13 shows the timing for the SSH signal.
Start Pulse
CONVERT

SSH
toff = 10 ns minimum
Figure 13. SSH Signal Timing

20

toff

PCI-DAS6052 User's Guide

Functional Details

A/D CONVERT signal
The A/D CONVERT signal indicates the start of an A/D conversion. It is available through software selection
as an input to any of the AUXIN pins (defaulting to AUXIN0) or the DAQ-Sync DS A/D CONVERT input andas an output to any of the AUXOUT pins.
When used as an input, the polarity is software selectable. The A/D CONVERT signal starts an acquisition on
the selected edge. The selected edge (either rising of falling) of the convert pulses must be separated by aminimum of 3 µs to remain within the 333 kS/s conversion rate specification.
Refer to Figure 6 on page 18 and Figure 9 on page 19 for the relationship of A/D CONVERT to the DAQ
sequence. Figure 14 and Figure 15 show the input and output pulse width requirements for the A/D CONVERT
signal.
tw
Rising Edge Polarity
Falling Edge Polarity

tw = 37.5 ns minimum

Figure 14. A/D CONVERT signal input timing requirementtwtw = 50 ns
Figure 15. A/D CONVERT signal output timing requirement

The A/D CONVERT signal is generated by the on-board pacer circuit unless the external clock option is in use.
This signal may be gated by hardware (A/D PACER GATE) or software.

A/D PACER GATE signal
The A/D PACER GATE signal is used to disable scans temporarily. This signal may be programmed for input
at any of the AUXIN pins.
If the A/D PACER GATE signal is active, no scans can occur. If the A/D PACER GATE signal becomes active
during a scan in progress, the current scan is completed and scans are then held off until the gate is de-asserted.

A/D EXTERNAL TIME BASE signal
The A/D EXTERNAL TIME BASE signal can serve as the source for the on-board pacer circuit rather thanusing the 40 MHz internal time base. Any AUXIN pin can be set programmatically as the source for this signal.
The polarity is programmable.
The maximum frequency for the A/D EXTERNAL TIME BASE signal is 20 MHz. The minimum pulse widthis 23 ns high or low. There is no minimum frequency specification.

21

PCI-DAS6052 User's Guide

Functional Details

Figure 16 shows the timing specifications for the A/D EXTERNAL TIME BASE signal.
tp =50 ns minimum
tp

tw

tw

tw =23 ns minimum
Figure 16. A/D EXTERNAL TIME BASE signal timing

A/D STOP signal
The A/D STOP signal indicates a completed acquisition sequence. You can program this signal to be available
at any of the AUXOUT pins. The A/D STOP output signal is a 50 ns wide pulse whose leading edge indicates a
DAQ done condition.
twtw = 50 ns
Figure 17. A/D STOP Signal Timing

ATRIG signal
In addition to standard digital trigger features, the PCI-DAS6052 also provides analog triggering capability.
When using the analog trigger, acquisitions may be started and controlled via an analog signal. There are four
trigger/gate modes available using the analog trigger feature:

Trigger – positive or negative slope
Gate – above reference or below reference
Hysteresis – positive or negative hysteresis
Window – inside or outside window

The trigger mode is used to start an acquisition sequence. The remaining modes provide gating functions during
an acquisition sequence which start and stop the acquisition based on the gate condition.


There are two possible inputs for the analog trigger source. The first is the AUXIN0/ATRIG pin on the
100-pin I/O connector. This is a software selectable dual-purpose pin that supports either digital or analog
trigger inputs. The source selection defaults to analog trigger on power-up and may be modified at any timeusing InstaCal. The input range on the ATRIG pin is always ±10V. 12-bit DACs are used to set the HI and
LO levels for the threshold(s). The threshold resolution in this mode is 4.88mV per step.

Caution! Remove all analog inputs before configuring this pin as a digital input. Any voltage levels above±15V in this configuration may cause damage to the product!
The post-gain version of any one of the 16 analog inputs may also be used as the analog trigger source. In thismode, the voltage present on the first channel in the scan may be used initiate the acquisition sequence.
Since the input to the analog trigger circuit has been scaled by the selected range, the effective resolution of thethresholds is equal to the A/D's full-scale-range (±2.5V) divided by 4096. For example, the ±2.5V range allows
for 5V/4096, or 1.2 mV of threshold resolution.
The following is a detailed description of each mode of operation. In each case a ±2V triangle waveform isused as the ATRIG input source. The THRESH_HI is set to 1.0V and the THRESH_LO signal is set to -1.0V.
22

PCI-DAS6052 User's Guide

Functional Details

In the following analog trigger signal diagrams, the bold portion of the waveform indicates the data acquired forthe given ATRIG mode.
Trigger Above
The acquisition will begin when the ATRIG signal first goes above the THRESH_HI. This mode is nonretriggerable.
+2
Thresh_HI

+1
0
-1
-2
Trigger

Acquired Data
+2
+1
0
-1
-2

Figure 18. Trigger Positive Slope

Trigger Below
The acquisition will begin when ATRIG signal fist goes below the THRESH_LO level. This mode is nonretriggerable.
+2+1
0
Thresh_LO-1-2
Trigger

Acquired Data
+2
+1
0
-1
-2

Figure 19. Trigger Negative Slope23

PCI-DAS6052 User's Guide

Functional Details

Gate Above
Data acquisition is enabled whenever ATRIG goes above the THRESH_HI level. Acquistion is suspended
whenever the ATRIG signal goes below the THRESH_HI level. This is a level-sensitive gating mode.
+2+1

Thresh_HI0-1-2
Trigger

Result+2+1
0-1

Figure 20. Gate Above

Gate Below
Data acquisition is enabled whenever ATRIG goes below the THRESH_LO level. Acquisition is suspended
whenever the ATRIG signal goes above the THRESH_LO level. This is a level-sensitive gating mode.
+2+1
0
Thresh_LO-1-2
Trigger

Acquired Data
+1
0
-1
-2

Figure 21. Gate Below

24

PCI-DAS6052 User's Guide

Functional Details

Gate Negative Hysteresis
Data acquisition is enabled whenever ATRIG goes above the THRESH_HI level. Acquisition is suspended
whenever the ATRIG signal goes below the THRESH_LO level. The hysteresis level is set by THRESH_LO.
This is a level-sensitive gating mode.
+2
Thresh_HI+10

Thresh_LO-1-2
Trigger

Acquired Data
+2
+1
0
-1

Figure 22. Gate Negative Hysteresis

Gate Positive Hysteresis
Data acquisition is enabled whenever ATRIG goes below the THRESH_LO level. Acquisition is suspended
whenever the ATRIG signal goes above the THRESH_HI level. The hysteresis level is set by THRESH_HI.
This is a level-sensitive gating mode.
+2
Thresh_HI+10

Thresh_LO-1-2
Trigger

Acquired Data
+2
+1
0
-1
-2

Figure 23. Gate Positive Hysteresis

25

PCI-DAS6052 User's Guide

Functional Details

Gate Inside Window
Data acquisition is enabled whenever ATRIG is below the THRESH_HI level and above the THRESH_LO
level. Acquisition is suspended whenever the ATRIG signal is outside of this region. This is a level-sensitive
gating mode+2
Thresh_HI+10

Thresh_LO-1-2
Trigger

Acquired Data
+2
+1
0
-1
-2

Figure 24. Gate Inside Window

Gate Outside Window
Data acquisition is enabled whenever ATRIG is above the THRESH_HI level or below the THRESH_LO level.
Acquisition is suspended whenever the ATRIG signal is between the THRESH_HI and THRESH_LO levels.
This is a level-sensitive gating mode+2
Thresh_HI+10

Thresh_LO-1-2
Trigger

Acquired Data
+2
+1
0
-1
-2

Figure 25. Gate Outside Window

26

PCI-DAS6052 User's Guide

Functional Details

Waveform generation timing signals
The signals that control the timing for the analog output functions on the PCI-DAS6052 are:


D/A START TRIGGER
D/A UPDATE
D/A EXTERNAL TIME BASE

D/A START TRIGGER signal
The D/A START TRIGGER signal is used to hold off output scans until after a trigger event. The DAQ-Sync“DS D/A START TRIGGER” input or any AUXIN pin can be programmed to serve as the D/A START
TRIGGER signal. It is also available as an output on any AUXOUT pin.
When used as an input, the D/A START TRIGGER signal may be software selected as either a positive or
negative edge trigger. The selected edge of the D/A START TRIGGER signal causes the DACs to start
generating the output waveform.
The D/A START TRIGGER signal can be used as an output to monitor the trigger that initiates waveformgeneration. The output is an active-high pulse having a width of 50 ns.
Figure 26 and Figure 27 show the input and output timing requirements for the D/A START TRIGGER signal.
tw

Rising Edge Polarity
Falling Edge Polarity

tw = 37.5 ns minimum
Figure 26. D/A START TRIGGER input signal timingtw

tw = 50 ns
Figure 27. D/A START TRIGGER output signal timing

D/A CONVERT signal
The D/A CONVERT signal causes a single output update on the D/A converters. You can program the DAQSync DS D/A UPDATE input or any AUXIN pin to accept the D/A CONVERT signal. It is also available as an
output on any AUXOUT pin. The D/A CONVERT input signal polarity is software selectable. DAC outputs
update within 100 ns of the selected edge. The D/A CONVERT pulses should be no less than 100 µs apart.
When used as an output, the D/A CONVERT signal may be used to monitor the pacing of the output updates.
The output has a pulse width of 225 ns with selectable polarity.

27

PCI-DAS6052 User's Guide

Functional Details

Figure 28 and Figure 29 show the input and output timing requirements for the D/A CONVERT signal.
tw

Rising Edge Polarity
Falling Edge Polarity

tw = 37.5 ns minimum

Figure 28. D/A CONVERT input signal timingtw
tw = 225 ns
Figure 29. D/A CONVERT output signal timing

D/A EXTERNAL TIME BASE signal
The D/A EXTERNAL TIME BASE signal can serve as the source for the on-board DAC pacer circuit rather
than using the internal time base. Any AUXIN pin can be set programmatically as the source for this signal. The
polarity is programmable.
The maximum frequency for the D/A EXTERNAL TIME BASE signal is 20 MHz. The minimum pulse widthis 23 ns high or low. There is no minimum frequency specification.
Figure 30 shows the timing requirements for the D/A EXTERNAL TIME BASE signal.
tp =50 ns minimum
tp

tw

tw

tw =23 ns minimum

Figure 30. D/A EXTERNAL TIME BASE signal timing

General-purpose counter signal timing
The general-purpose counter signals are:







CTR1 CLK
CTR1 GATE
CTR1 OUT
CTR2 CLK
CTR2 GATECTR2 OUT

CTR1 CLK signal
The CTR1 CLK signal can serve as the clock source for independent user counter 1. It can be selected throughsoftware at the CTR1 CLK pin rather than using the on-board 10 MHz or 100 kHz sources. It is also polarity
programmable. The maximum input frequency is 10 MHz. There is no minimum frequency specified.

28

PCI-DAS6052 User's Guide

Functional Details

Figure 31 shows the timing requirements for the CTR1 CLK signal.
tp =100 ns minimum

tw-H

tw-L

tw-H =15 ns minimum
tw-L =25 ns minimum
Figure 31. CTR1 CLK signal timing

CTR1 GATE signal
You can use the CTR1 GATE signal for starting and stopping the counter, saving counter contents, etc. It ispolarity programmable and is available at the CTR1 GATE pin.
Figure 32 shows the minimum timing requirements for the CTR1 GATE signal.
tw

Rising Edge Polarity
Falling Edge Polarity

tw = 25 ns minimum
Figure 32. CTR1 GATE signal timing

CTR1 OUT signal
This signal is present on the CTR1 OUT pin. The CTR1 OUT signal is the output of one of the two user’s
counters in an industry-standard 82C54 chip.
For detailed information on counter operations, please refer to the data sheet on our WEB page at
http://www.measurementcomputing.com/PDFmanuals/82C54.pdf.
Figure 33 shows the timing requirements for the CTR1 OUT signal for counter mode 0 and mode 2.
TC
CTR1 CLK
CTR1 OUT (Mode 2)
CTR1 OUT (Mode 0)

Figure 33. CTR1 OUT signal timing

CTR2 CLK signal
The CTR2 CLK signal can serve as the clock source for independent user counter 2. It can be selected throughsoftware at the CTR2 CLK pin rather than using the on-board 10 MHz or 100 kHz sources. It is also polarity
programmable. The maximum input frequency is 10 MHz. There is no minimum frequency specified.

29

PCI-DAS6052 User's Guide

Functional Details

Figure 34 shows the timing requirements for the CTR2 CLK signal.
tp =100 ns minimum

tw-H

tw-L

tw-H =15 ns minimum
tw-L =25 ns minimum
Figure 34. CTR2 CLK signal timing

CTR2 GATE signal
You can use the CTR2 GATE signal for starting and stopping the counter, saving counter contents, etc. It ispolarity programmable and is available at the CTR2 GATE pin.
Figure 35 shows the timing requirements for the CTR2 GATE signal.
tw

Rising Edge Polarity
Falling Edge Polarity

tw = 25 ns minimum

Figure 35. CTR2 GATE signal timing

CTR2 OUT signal
This signal is present on the CTR2 OUT pin. The CTR2 OUT signal is the output of one of the two user’s
counters in an industry-standard 82C54 chip.
For detailed information on counter operations, please refer to the data sheet on our web site at
http://www.measurementcomputing.com/PDFmanuals/82C54.pdf.
Figure 36 shows the timing of the CTR1 OUT signal for mode 0 and for mode 2.
TC
CTR2 CLK
CTR2 OUT (Mode 2)
CTR2 OUT (Mode 0)
Figure 36. CTR2 OUT signal timing

30

Chapter 4

Calibrating the Board
Introduction
You should calibrate the board (using the InstaCal utility) after the board has fully warmed up. The
recommended warm-up time is 15 minutes. For best results, calibrate the board immediately before making
critical measurements. The high resolution analog components on the board are somewhat sensitive totemperature. Pre-measurement calibration ensures that your board is operating at optimum calibration values.

Calibration theory
Analog inputs are calibrated for offset and gain. Offset calibration for the analog inputs is performed directly on
the input amplifier (PGIA) with coarse and fine trim DACs acting on the amplifier.
For input gain calibration, a precision calibration reference is used with coarse and fine trim DACs acting on the
ADC (see Figure 37).

Figure 37. Analog input calibration - basic elements

31

PCI-DAS6052 User's Guide

Calibrating the Board

A similar method is used to calibrate the analog output components. A trim DAC is used to adjust the gain of
the DAC. A separate DAC is used to adjust offset on the final output amplifier. The calibration circuits are
duplicated for both analog outputs (see Figure 38).

Figure 38. Analog output calibration – basic elements

32

Chapter 5

Specifications
All specifications are subject to change without notice.
Typical for 25 °C unless otherwise specified.
Specifications in italic text are guaranteed by design.

Analog input
Table 1. Analog input specifications
Parameter

Specification

A/D converter
Resolution
Maximum sample rate
Number of channels
Input ranges

Successive approximation type, 333 kS/s conversion rate.
16 bits, 1 in 65536
333 kS/s
16 single ended / 8 differential, software selectable
Bipolar:±10V, ±5V, ±2.5V, ±1V, ±0.5V, ±0.25V, ±0.1V, ±0.05V,
Unipolar:0 to 10V, 0 to 5V, 0 to 2V, 0 to 1V, 0 to 0.5V, 0 to 0.2V, 0 to 0.1V
Software selectable
Internal counter – ASIC. Software selectable time base: Internal 40 MHz, 50 ppm stability
 External source via AUXIN<5:0>, software selectable.
External convert strobe: A/D CONVERT
Software paced
Software selectable option, burst rate = 3 µS
External digital: A/D GATE
External analog: ATRIG input
CH0 IN through CH15 IN
External digital: Programmable, active high or active low, level or edge
External analog: Refer to the Analog trigger section on page 39
External digital: A/D START TRIGGER
A/D STOP TRIGGER
External analog: ATRIG input
CH0 IN through CH15 IN
External digital: Software-configurable for rising or falling edge.
External analog: Refer to the Analog trigger section on page 39
Pre-/post-trigger: Unlimited number of pre-trigger samples, 16 Meg post-trigger samples.
Available at user connector: A/D PACER OUT
8 K samples
DMA
Programmed I/ODemand or non-demand using scatter-gather
Up to 8 K elements. Programmable channel, gain, and offset
333 kS/s, system dependent

A/D pacing

Burst mode
A/D gate sources

A/D gating modes
A/D trigger sources

A/D triggering modes

ADC pacer out
RAM buffer size
Data transfer
DMA modes
Configuration memory
Streaming-to-disk rate33

PCI-DAS6052 User's Guide

Specifications

Accuracy
333 kS/s sampling rate, single channel operation and a 15-minute warm-up. Accuracies listed are formeasurements made following an internal calibration. They are valid for operational temperatures within ±1 °C
of internal calibration temperature and ±10 °C of factory calibration temperature. Calibrator test source highside tied to Channel 0 high and low side tied to Channel 0 how. Low-level ground is tied to Channel 0 low at
the user connector.
Table 2. Absolute accuracy specifications
Range

Absolute Accuracy

±10 V
±5 V
±2.5 V±1 V±500 mV±250 mV±100 mV±50 mV
0 to 10 V
0 to 5 V
0 to 2 V
0 to 1 V
0 to 500 mV
0 to 200 mV
0 to 100 mV±15.6 LSB
±5.7 LSB±15.6 LSB
±15.7 LSB
±15.9 LSB
±18.0 LSB
±21.0 LSB
±23.0 LSB
±8.1 LSB±27.8 LSB
±28.0 LSB
±28.0 LSB
±31.7 LSB
±36.4 LSB
±38.7 LSB
Table 3. Absolute accuracy components – all values are (±)

Range

±10V
±5V
±2.5V
±1V
±500mV±250mV±100mV±50mV
0 to 10V
0 to 5V
0 to 2V
0 to 1V
0 to 500mV
0 to 200mV
0 to 100mV% of
Reading

Offset(µV)

Noise +Quantization (µV)
Single Pt

Averaged(Note 1)0.03710.00710.03710.03710.0371
0.04210.04710.04710.00710.03710.03710.0371
0.04210.04710.0471

947
476
241
99.2
52.1
28.6
14.4
9.7
476
241
99.2
52.1
28.6
14.4
9.7

981
491
245
98.1
56.2
32.8
22.4
19.9
491
245
98.1
56.2
39.8
22.4
19.9

87.0
43.5
21.7
8.7
5.0
3.0
2.1
1.9
43.5
21.7
8.7
5.0
3.0
2.1
1.9

Temp Drift(%/DegC)

Absolute
Accuracy at
FS (mV)

0.00060.00010.00060.00060.00060.00060.00060.00060.00010.00060.00060.00060.00060.00060.0006

4.747
0.876
1.190
0.479
0.243
0.137
0.064
0.035
1.232
2.119
0.850
0.428
0.242
0.111
0.059

Note 1: Averaged measurements assume averaging of 100 single-channel readings

Each PCI-DAS6052 is tested at the factory to assure the board’s overall error does not exceed accuracy limits
described in Table 2.

34

PCI-DAS6052 User's Guide

Specifications

Table 4. Relative accuracy specifications – all values are (±)
Range
±10 V
±5 V
±2.5 V±1 V±500 mV±250 mV±100 mV±50 mV
0 to 10 V
0 to 5 V
0 to 2 V
0 to 1 V
0 to 500 mV
0 to 200 mV
0 to 100 mV

Relative Accuracy (µV)
Single Point

Averaged (Note 2)

1145
573
286
115
66.3
39.2
27.7
25.3
573
286
115
66.3
48.2
27.7
25.3

115
57.3
28.6
11.5
6.6
3.9
2.8
2.5
57.3
28.6
11.5
6.6
3.9
2.8
2.5

Note 2: Averaged measurements assume averaging of 100 single-channel readings

Relative accuracy is defined as the measured deviation from a straight line drawn between measured endpointsof the transfer function. ADC resolution, noise and front-end non-linearity are included in this measurement.
Table 5. Differential non-linearity specifications
All Ranges±0.5 LSB typ±1.0 LSB max

Settling time
Settling time is defined as the time required for a channel to settle to within a specified accuracy in response toa full-scale (FS) step. Two channels are scanned at the specified rate. A –FS DC signal is presented to Channel
1; a +FS DC signal is presented to Channel 0.
Table 6. Settling time specifications
Condition

Same range
to same
range

Range

±10 V
±5 V
±2.5 V±1 V±500 mV±250 mV±100 mV±50 mV
0 to 10 V
0 to 5 V
0 to 2 V
0 to 1 V
0 to 500 mV
0 to 200 mV
0 to 100 mV

Accuracy±0.00076%(±0.5 LSB)

±0.0015%(±1 LSB)±0.0031%(±2 LSB)±0.0061%(±4 LSB)±0.024%(±16 LSB)

20 µS typ20 µS typ20 µS typ20 µS typ20 µS typ20 µS typ20 µS typ20 µS typ20 µS typ20 µS typ20 µS typ20 µS typ20 µS typ20 µS typ20 µS typ

10 µS max
10 µS max
10 µS max
10 µS max
10 µS max
10 µS max
10 µS max
10 µS max
10 µS max
10 µS max
10 µS max
15 µS max
15 µS max
15 µS max
15 µS max

5 µS max
5 µS max
5 µS max
5 µS max
5 µS max
5 µS max
5 µS max
5 µS max
5 µS max
5 µS max
5 µS max
5 µS max
8 µS max
8 µS max
10 µS max

4 µS max
4 µS max
4 µS max
4 µS max
4 µS max
4 µS max
4 µS max
4 µS max
4 µS max
4 µS max
4 µS max
4 µS max
4 µS max
4 µS max
4 µS max

3 µS typ
3 µS typ
3 µS typ
3 µS typ
3 µS typ
3 µS typ
3 µS typ
3 µS typ
3 µS typ
3 µS typ
3 µS typ
3 µS typ
3 µS typ
3 µS typ
3 µS typ35

PCI-DAS6052 User's Guide

Specifications

Parametrics
Table 7. Parametric specifications
Max working voltage(signal + common-mode)
CMRR @ 60 Hz±11 V±10 V range:
92 dB
0 to 10 V and ±5 V range:
97 dB
0 to 5 V and ±2.5 V range: 101 dB
0 to 2 V and ±1 V range:
104 dB
0 to 1 V and ±0.5 V range: 105 dB
0 to 0.5 V and ±0.25 V range: 105 dB
0 to 0.5 V and ±0.1 V range: 105 dB
0 to 0.1 V and ±0.05 V range: 105 dB
480 kHzDC
100 GΩ in parallel with 100 pF in normal operation.
±200 pA±100 pA
Power ON: ±25 V, Power OFF: ±15 V (±20 mA; Note 3)
Protected inputs: CH<15:0> IN
 AISENSE
CH0 IN, single-ended mode, 0 V to 0.1 V input range (Note 4)
Adjacent channels: –75 dB
All other channels: –90 dB

Small signal bandwidth, all ranges
Input coupling
Input impedance
Input bias current
Input offset current
Absolute maximum input voltage

Power on and reset state
Crosstalk

Note 3: The analog input sink/source current must be limited to an maximum of ±20 mA in the power OFF

state to prevent damage to the board. A 1000 Ω (¼ W) current limiting resistor should be placed inseries with each analog input channel being used in applications where the power OFF statesink/source current into the board can exceed ±20 mA. Resistance values >1000 Ω may adversely
affect the noise and settling time performance of the board.
Note 4: Care should be taken to avoid the application of an input voltage to CH0 IN that could overdrive theanalog input circuit. Any unused analog input channel should be connected to LLGND.

Noise performance
Table 8 summarizes the noise performance for the PCI-DAS6052. Noise distribution is determined by gathering
50 K samples with inputs tied to ground at the user connector. Samples are gathered at the maximum specified
single channel sampling rate. Specification applies to differential mode operation.
Table 8. Analog input noise performance specifications
Range

LSBrmsTypical Counts

±10 V
±5 V
±2.5 V±1 V±500 mV±250 mV±100 mV±50 mV
0 to 10 V
0 to 5 V
0 to 2 V
0 to 1 V

0.95
0.95
0.95
0.95
1.1
1.3
2.3
4.2
0.95
0.95
0.95
1.1

11
11
11
11
11
13
23
42
11
11
11
11

36

PCI-DAS6052 User's Guide

Specifications

Range

LSBrmsTypical Counts

0 to 500 mV
0 to 200 mV
0 to 100 mV

1.3
2.3
4.2

13
23
42

Analog output
Table 9. Analog output specifications
Parameter

Specification

D/A converter type
Resolution
Number of channels
Voltage range
Monotonicity
Slew rate
Settling time (full scale step)
Noise
Glitch energy
Current drive
Output short-circuit duration
Output coupling
Output impedancePower up and reset

Double-buffered, multiplying
16-bits, 1 in 65536
2, voltage output type
±10 V, 0 to 10 V, ±EXT REF., 0 to EXT REF., software selectable16-bits, guaranteed
15 V/µs typ.
3.5 µs max to ±1 LSB
60 µVrms, DC to 1 MHz BW±10 mV with 1 µS duration (measured at mid-scale transition)±5 mA
Indefinite @ 25 mADC
0.1 Ω max
DACs cleared to 0 volts ±20 mV max.
Table 10. Absolute accuracy specifications

Range

Absolute Accuracy±10 V
0 to 10 V±4.6 LSB±7.7 LSB
Table 11. Absolute accuracy components specifications - all values are (±)

Range% of Reading

Offset(µV)

Temp Drift(%/DegC)

Absolute Accuracy at FS (mV)

±10 V
0 to 10 V

0.00610.0061798
569

0.00010.0001

1.405
1.176

Each PCI-DAS6052 is tested at the factory to ensure that the overall error does not exceed the values specified
in Table 10.
Table 12. Relative accuracy specifications
Range

Relative Accuracy

All ranges±0.35 LSB, typ±1.0 LSB, max

Relative accuracy is defined as the measured deviation from a straight line drawn between measured endpointsof the transfer function.

37

PCI-DAS6052 User's Guide

Specifications

Analog output pacing and triggering
Table 13. AO pacing and triggering specifications
Parameter

Specification

DAC pacing(SW programmable)

Internal counter – ASIC. Selectable time base: Internal 40 MHz, 50 ppm stability.
 External Source via AUXIN<5:0>, SW selectable.
External convert strobe: D/A UPDATE
Software paced
External digital: D/A START TRIGGER
External analog: ATRIG input
CH0 IN through CH15 IN
Software gatedExternal digital: Programmable, active high or active low, level or edge
External analog: Refer to the Analog trigger section on page 39
External digital: D/A START TRIGGER
External analog: ATRIG input
CH0 IN through CH15 IN
Software triggered
External digital: Software-configurable for rising or falling edge
External analog: Refer to the Analog trigger section on page 39
Available at user connector D/A PACER OUT
16 K samples
DMA
Programmed I/OUpdate DACs individually or simultaneously, software selectable
Demand or Non-demand using scatter gather
333 kS/s max per channel, 2 channels simultaneous

DAC gate sources(Software programmable)

DAC gating modes
DAC trigger sources

DAC triggering modes
DAC pacer out
RAM buffer size
Data transfer

DMA modes
Waveform generation throughput

Analog output external reference input (D/A EXTREF)
Table 14. External reference input (D/A EXTREF) specifications
Parameter

Specification

Range
Overvoltage protection
Input Impedance
Bandwidth (-3 dB)
Slew rate±11 V±25 V powered on, ±15 V powered off
10 kΩ min
3 kHz
0.3 V/µS

38

PCI-DAS6052 User's Guide

Specifications

Analog trigger
Table 15. Analog trigger specifications
Parameter

Specification

Analog trigger sources
Software selectable
Analog trigger levels

External: ATRIG input
CH0 IN through CH15 IN, first channel in scan
ATRIG input: ±10V
CH0 IN through CH15 IN: ± Full-scale, range dependent
External analog: software-configurable for:
 Positive or negative slope
External analog: Software-configurable for:
 Above or below reference Positive or negative hysteresis
 In or out of window
12-bits, 1-in-4096±1% full-scale range max
ATRIG input
700 kHzCH0 IN through CH15 IN
700 kHz

Analog trigger modes
Analog gate modes

Resolution
Accuracy
Bandwidth (-3dB)

Analog I/O calibration
Table 16. Analog I/O calibration specifications
Parameter

Specification

Recommended warm-up time
Calibration

15 minutes
Auto-calibration, calibration factors for each range stored on board in non-volatileRAM.
DC Level: 5.000 V± 1 mV. Actual measured values stored in EEPROM.
Tempco: 0.6 ppm/°C max
Long-term stability: ±6 ppm/sqrt (1000 hrs)
1 yearOnboard calibration reference

Calibration interval

Digital I/O
Table 17. DIO specifications
Parameter

Specification

Digital type
Number of I/O
Configuration

Discrete, 5V/TTL compatible
8
8 bits, independently programmable for input or output. All pins pulled up to +5 V
via 47 K resistors (default). Positions available for pull-down to ground. Hardware
selectable via solder gap.
2.0 V min, 7.0 V absolute max
0.8 V max, –0.5 V absolute min
3.80 V min, 4.20 V typ
0.55 V max, 0.22 V typ
Programmed I/O
Input mode (high impedance)

Input high voltage
Input low voltage
Output high voltage (IOH = -32 mA)
Output low voltage (IOL = 32 mA)
Data transfer
Power-up / reset state39

PCI-DAS6052 User's Guide

Specifications

Interrupts
Table 18. Interrupt specifications
Parameter

Specification

Interrupts
Interrupt enable
ADC Interrupt sources(software programmable)

PCI INTA# - mapped to IRQn via PCI BIOS at boot-time
Programmable through PLX9080
DAQ_ACTIVE: Interrupt is generated when a DAQ sequence is active.
DAQ_STOP:Interrupt is generated when A/D Stop Trigger In is detected.
DAQ_DONE: Interrupt is generated when a DAQ sequence completes.
DAQ_FIFO_1/4_FULL:
Interrupt is generated when ADC FIFO is ¼ full.
DAQ_SINGLE: Interrupt is generated after each conversion completes.
DAQ_EOSCAN: Interrupt is generated after the last channel is converted in
multi-channel scans.
DAQ_EOSEQ: Interrupt is generated after each interval delay during multichannel scans.
DAC_ACTIVE: Interrupt is generated when DAC waveform circuitry is active.
DAC_DONE:Interrupt is generated when a DAC sequence completes.
DAC_FIFO_1/4_EMPTY:Interrupt is generated DAC FIFO is ¼ empty.
DAC_HIGH_CHANNEL:
Interrupt is generated when the DAC high channel output is
updated.

DAC Interrupt sources(software programmable)

Counters
Table 19. Counter specifications
Parameter

Specification

User counter type
Number of channels
Resolution
Compatibility
CTRn base clock source(software selectable)
Internal 10 MHz clock source stability
Counter n gate
Counter n output
Clock input frequency
High pulse width (clock input)
Low pulse width (clock input)
Gate width highGate width low
Input low voltage
Input high voltage
Output low voltage
Output high voltage

82C54
216-bits
5V/TTLInternal 10 MHz, Internal 100 kHz or external connector (CTRn CLK)50 ppmAvailable at connector (CTRn GATE).
Available at connector (CTRn OUT).
10 MHz max
15 ns min
25 ns min
25 ns min
25 ns min
0.8 V max
2.0 V min
0.4 V max
3.0 V min40

PCI-DAS6052 User's Guide

Specifications

Configurable AUXIN<5:0>, AUXOUT<2:0> external trigger/clocks
The PCI-DAS6052 provides nine user-configurable trigger/clock pins available at the 100-pin I/O connector. Of
these, six are configurable as inputs while three are configurable as outputs.
Table 20. Configurable triggers/clocks specifications
Parameter

Specification

AUXIN<5:0> sources(SW selectable)

A/D CONVERT:
A/D TIMEBASE IN:
A/D START TRIGGER:
A/D STOP TRIGGER:
A/D PACER GATE:
D/A START TRIGGER:
D/A UPDATE:
D/A TIMEBASE IN:
STARTSCAN:SSH:

AUXOUT<2:0> sources(SW selectable)

Default selections:Compatibility
Edge-sensitive polarity
Level-sensitive polarity
Minimum pulse width

External ADC convert strobe
External ADC pacer time base
ADC Start Trigger
ADC Stop Trigger
External ADC gate
DAC trigger/gate
DAC update strobe
External DAC pacer time base
A pulse indicating start of conversion
Active signal that terminates at the start of the lastconversion in a scan
Indicates end of scan
ADC convert pulse
Delayed version of ADC convert
CTR1 clock source
D/A update pulse
CTR2 clock source
ADC Start Trigger Out
ADC Stop Trigger Out
External ADC gate
DAC Start Trigger Out
A/D CONVERT
A/D START TRIGGER
A/D STOP TRIGGER
D/A UPDATE
D/A START TRIGGER
A/D PACER GATE
D/A UPDATE
A/D CONVERTSCANCLK

A/D STOP:
A/D CONVERT:SCANCLK:CTR1 CLK:
D/A UPDATE:CTR2 CLK:
A/D START TRIGGER:
A/D STOP TRIGGER:
A/D PACER GATE:
D/A START TRIGGER:
AUXIN0:
AUXIN1:
AUXIN2:
AUXIN3:
AUXIN4:
AUXIN5:
AUXOUT0:
AUXOUT1:
AUXOUT2:
5V/TTL
Rising/falling, software selectable
Active high/active low, software selectable
3.75 nS

41

PCI-DAS6052 User's Guide

Specifications

DAQ-Sync inter-board triggers/clocks
The DAQ-Sync bus provides inter-board triggering and synchronization capability. Five trigger/strobe I/O pins
and one clock I/O pin are provided on a 14-pin header. The DAQ-Sync signals use dedicated pins. Only the
direction may be set.
Table 21. DAQ-Sync signal specifications
Connector

Signal names

DAQ-Sync

DS A/D START TRIGGER
DS A/D STOP TRIGGER
DS A/D CONVERTDS D/A UPDATEDS D/A START TRIGGERSYNC CLKPower consumption
Table 22. Power consumption specifications
Parameter

Specification+5 V

1.25 A typ, 1.5 A max. Does not include power consumed through the
I/O connector.
1A max, protected with a resettable fuse

+5 V available at I/O connector

Environmental
Parameter

Specification

Operating temperature range
Storage temperature range
Humidity

0 °C to 55 °C–20 °C to 70 °C
0% to 90% non-condensing

Mechanical
Table 23. Environmental specifications
Parameter

Specification

Card dimensions (L × W × H)

PCI half card: 174.4 (6.87) × 106.9 (4.21) × 11.65 mm (0.46 in.)

DAQ-Sync connector
Table 24. DAQ-Sync connector specifications
Parameter

Specification

Connector typeCompatible cables

14-pin right-angle 100 mil box header
MCC p/n: CDS-14-x, 14-pin ribbon cable.
x = number of boards (2 to 5)

42

PCI-DAS6052 User's Guide

Specifications

Table 25. DAQ-Sync connector pinout
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14

Signal NameDS A/D START TRIGGER
GND
DS A/D STOP TRIGGER
GND
DS A/D CONVERTGND
DS D/A UPDATEGND
DS D/A START TRIGGER
GND
RESERVEDGND
SYNC CLKGNDSCSI connector
Table 26. SCSI connector specifications
Parameter

Specification

Connector typeCompatible cables

Shielded SCSI 100 D-type
C100HD50-x, unshielded ribbon cable.
x = 3 or 6 feet
C100MMS-x, shielded round cable.
x = 1, 2, or 3 meters
ISO-RACK16/P
ISO-DA02/P
BNC-16SE
BNC-16DI
CIO-MINI50
CIO-TERM100
SCB-50
SCB-100

Compatible accessory products(with the C100HD50-x cable)

Compatible accessory products(with the C100MMS-x cable)

43

PCI-DAS6052 User's Guide

Specifications

Table 27. 8-channel differential mode pinout
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50

Signal Name
LLGND
CH0 IN HI
CH0 IN LO
CH1 IN HI
CH1 IN LO
CH2 IN HI
CH2 IN LO
CH3 IN HI
CH3 IN LO
CH4 IN HI
CH4 IN LO
CH5 IN HI
CH5 IN LO
CH6 IN HI
CH6 IN LO
CH7 IN HI
CH7 IN LO
LLGND
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
AISENSED/A OUT 0
D/A GND
D/A OUT1
PC +5 V
AUXOUT0 / D/A PACER OUT
AUXOUT1 / A/D PACER OUT
AUXOUT2 / SCANCLKAUXIN0 / A/D CONVERT / ATRIG
D/A EXTREF
AUXIN1 / A/D START TRIGGER
AUXIN2 / A/D STOP TRIGGER
AUXIN3 / D/A UPDATEAUXIN4 / D/A START TRIGGER
AUXIN5 / A/D PACER GATE
GND

Pin
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100

44

Signal Name
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
DIO0
DIO1
DIO2
DIO3
DIO4
DIO5
DIO6
DIO7
CTR1 CLK
CTR1 GATE
CTR1 OUTGND
CTR2 CLK
CTR2 GATECTR2 OUT
GND

PCI-DAS6052 User's Guide

Specifications

Table 28. 16-channel single-ended mode
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50

Signal Name
LLGND
CH0 IN
CH8 IN
CH1 IN
CH9 INCH2 IN
CH10 IN
CH3 IN
CH11 IN
CH4 IN
CH12 IN
CH5 IN
CH13 IN
CH6 IN
CH14 IN
CH7 IN
CH15 IN
LLGND
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
AISENSED/A OUT 0
D/A GND
D/A OUT1
PC +5 V
AUXOUT0 / D/A PACER OUT
AUXOUT1 / A/D PACER OUT
AUXOUT2 / SCANCLKAUXIN0 / A/D CONVERT / ATRIG
D/A EXTREF
AUXIN1 / A/D START TRIGGER
AUXIN2 / A/D STOP TRIGGER
AUXIN3 / D/A UPDATEAUXIN4 / D/A START TRIGGER
AUXIN5 / A/D PACER GATE
GND

Pin
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100

45

Signal Name
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
DIO0
DIO1
DIO2
DIO3
DIO4
DIO5
DIO6
DIO7
CTR1 CLK
CTR1 GATE
CTR1 OUTGND
CTR2 CLK
CTR2 GATECTR2 OUT
GND

Declaration of Conformity
Manufacturer:
Address:

Category:

Measurement Computing Corporation
10 Commerce Way
Suite 1008
Norton, MA 02766
USAElectrical equipment for measurement, control and laboratory use.

Measurement Computing Corporation declares under sole responsibility that the product

PCI-DAS6052
to which this declaration relates is in conformity with the relevant provisions of the following standards or otherdocuments:
EC EMC Directive 2004/108/EC: General Requirements, EN 61326-1:2006 (IEC 61326-1:2005).
Emissions:EN 55011 (2007) / CISPR 11(2003): Radiated emissions: Group 1, Class A
EN 55011 (2007) / CISPR 11(2003): Conducted emissions: Group 1, Class A

Immunity: EN 61326-1:2006, Table 3.







IEC 61000-4-2 (2001): Electrostatic Discharge immunity.
IEC 61000-4-3 (2002): Radiated Electromagnetic Field immunity.
IEC 61000-4-4 (2004): Electric Fast Transient Burst Immunity.
IEC 61000-4-5 (2001): Surge Immunity.
IEC 61000-4-6 (2003): Radio Frequency Common Mode Immunity.
IEC 61000-4-11 (2004): Voltage Interrupts.

To maintain compliance to the standards of this declaration, the following conditions must be met.






The host computer, peripheral equipment, power sources, and expansion hardware must be CE
compliant.
All I/O cables must be shielded, with the shields connected to ground.
I/O cables must be less than 3 meters (9.75 feet) in length.
The host computer must be properly grounded.
Equipment must be operated in a controlled electromagnetic environment as defined by Standards EN
61326-1:2006, or IEC 61326-1:2005.

Declaration of Conformity based on tests conducted by Chomerics Test Services, Woburn, MA 01801, USA in
July, 2004. Test records are outlined in Chomerics Test Report #EMI3931.04. Further testing was conducted by
Chomerics Test Services, Woburn, MA. 01801, USA in December, 2008. Test records are outlined in
Chomerics Test report #EMI5216.08.
We hereby declare that the equipment specified conforms to the above Directives and Standards.

Carl Haapaoja, Director of Quality Assurance

Measurement Computing Corporation
10 Commerce Way
Suite 1008
Norton, Massachusetts 02766(508) 946-5100
Fax: (508) 946-9500
E-mail: info@mccdaq.com
www.mccdaq.com