CIO-DAS16/M1
1MHz 8 Channel 12 Bit Analog Input, Programmable Gain Queue
24 Digital I/O & Three 16 Bit Counter/Timers

1 MHz DAS16/M1

HUGE SAMPLE BUFFER

The CIO-DAS16/M1 multifunction analog and digital I/O board is
the highest speed variation of the traditional DAS-16 architecture.
The extra features of this newest DAS16 are:

The CIO-DAS16/M1 combined with a MEGA-FIFO can acquire
sample sets of up to 128 Million Samples at full speed!

* Blazing fast analog input of 1MHz continuous to MEGA-FIFO
with sample size limited only by the size of memory on the MEGAFIFO board.
* Pre-trigger and Post-trigger buffers of unlimited size managed by
the hardware and software provide a seamless event driven sample
set.

The CIO-DAS16/M1 employs the DT-Connect and MEGA-FIFO
sample buffer board to acquire huge sample sets completely independent of PC bus rates or other simultaneous processes.
High speeds and large sample sets are also possible direct to PC bus
and PC memory because the CIO-DAS16/M1 uses a FIFO buffer andthe REP-INSW command to transfer blocks at high speed into PCmemoryCONNECTOR COMPATIBLE* Programmable 256 step channel/gain queue.
* DT-CONNECT interface for high speed direct transfer of analog
data to MEGA-FIFO, array processors and other accessories.
* 24 digital I/O lines and three 16 bit counters, exactly like a CIODIO24/CTR3. An 82C55 digital I/O chip and an 82C54 counter/timer provide an array of interfacing options.

LOW COST - EXTRA FEATURESThe CIO-DAS16/M1 is one of the lowest cost megahertz A/Dboards available. Compared with other high speed A/D boards theCIO-DAS16/M1 is less than half the price. By employing advanced
features like DT-Connect, the CIO-MEGAFIFO and CIO-DAS16/
M1 will out sample any other board we know of.

The CIO-DAS16/M1 is connector compatible with the older,original DAS-16. The control registers are very similar to the CIODAS16/330i so adapting low-level drivers to the CIO-DAS16/M1 isa snap. Use the Universal Library language driver software andprograms written for the CIO-DAS16/M1 will run other DAS-16
family boards as well.

STREAMING SOFTWARE
Streaming high speed samples to memory, RAM disk or hard disk iseasy with the CIO-DAS16/M1's advanced architecture. The Universal Library includes modes for streaming data to files under programcontrol.

ANALOG INPUTSGAIN & RANGE PROGRAMMING

The analog input section of the CIO-DAS16/M1 has been designed for highspeed, flexibility and accuracy in a number of configurations and ranges. Theanalog signals are brought on board by a standard 37 pin D connector directly
to balanced multiplexors. The multiplexors are configured as 8 channels ofdifferential input. Differential inputs can reject noise and ground loops(common mode voltages).

No need to set switches to select an analog input range. The analog input range
is fully programmable. A programmable gain queue controls both the unipolar/
bipolar setting and the amplification of the analog input signal.

Signals are amplified by a programmable gain amplifier prior to conversion by
the A/D converter. The possible gains and ranges and associated codes areshown in the table to the right.
An integral sample & hold captures the signal which is then converted by theA/D converter. The 12 bit A/D converter provides a resolution of 1 in 4096
parts of full scale.
The speed of data gathering may vary from less than 1Hz to 1MHz. Acquisition
speed is dependent on the method of triggering and data transfer (and the PC
speed if the MEGA-FIFO is not used).
METHOD
DT-Connect to MEGA-FIFO
REP INSW to PC Memory
Polled by software
Interrupt Service Routine (no REP INSW)DMA IS DEAD!

MAX A/D Speed
1MHz
330KHz - 1MHz
4KHz-20KHz
4KHz - 20KHz

The REP INSW story.

REP INSW (Repeat Input String) is an x86 class CPU instruction which allows
the PC to transfer large amounts of data using one instruction. The data istransferred at the maximum rate allowed by the bus. On a typical 286 AT, thisrate is 2Mbyte/sec or 1 sample every microsecond.
In order to employ REP INSW the A/D board must have a FIFO buffer toaccumulate sample data. The CIO-DAS16/M1 has a 1024 sample buffer.
When it is half full (512 samples), an interrupt generated by the DAS16/M1
starts an interrupt service routine which executes the instruction REP INSW,transfers the data to PC memory and empties the FIFO buffer.
The data is transferred completely in the background and no unreasonable
demands are placed on the PC's resources. For example, screen updates neednot be suspended!

A/D SPECIFICATIONS

12 BITChannels
A/D TypeConversion Time
A/D Convert & Transfer Speed
Out DT-Connect
REP-INSW to PC Memory
Paced Interrupt Service Routine

8 Differential
Subranging Flash AD1671
0.8uS

Accuracy
Integral Linearity
Maximum Overvoltage
Input Leakage Current
Gain Drift
Zero Drift

0.01% +/- 1 LSB+/- 1 LSB+/- 35V Continuous
250 nA Max @ 25oC+/- 35 ppm/Deg C Max+/- 25 ppm/Deg C Max

1MHz800KHz (typical 486/66)
20KHz (typical 486/66)

The gain/range control byte is located at BASE + 11:
D7
D6Range U/B

D5G1

D4G0

D3X

D2Ch2

D1
Ch1

D0Ch0

CHANNEL: The channel is set by bits Ch2-Ch0. Valid values are 0-7 for 8channel, differential mode. For example, Ch2 = 1, Ch1 = 0, Ch0 = 0, then channel
4 is selected.
RANGE = The A/D chip input range, either 10V full scale or 20V
full scale. 0 = 10V, 1 = 20V.
U/B = Unipolar or Bipolar ranges. 0 = Bipolar, 1 = Unipolar.
G1 G0 = the gain of the input amplifier. 0,0 = X1. 0,1 = X2.
1,0 = X4. 1,1 = X8.
Input Ranges+/- 10V+/- 5V
0 to 10V
0 to 5 V+/- 2.5V
0 to 2.5V+/- 1.25V +/- 0.625V
0 to 1.25V

GAIN QUEUE PROGRAMMINGThe channel/gain queue may be loaded with a sequence of between 1 and 256
channel+gain (CGQ) codes. When an analog input run is started, data will beacquired from the channels in the order specified by the CGQ. The programmable gain amplifier will be switched to the appropriate gain for the channel
selected.
After the CGQ is loaded with a sequence of up to 256 different channel/gain
combinations, all A/D channel & gain control are derived from the CGQ. The
CGQ is automatically restarted when the last CGQ entry written is reached. For
example, if you load 6 CGQ steps into the CGQ, the 1st, 7th, 12th... A/D sample
in a run is controlled by the 1st entry in the CGQ. In this manner, large sample
runs may be precisely controlled.

HIGH-SPEED CONTROL REGISTERThe DAS16/M1 has a special control register. This register controls word/byte transfers, enables the DT-Connect interface, pre/post trigger enable
and FIFO status.
D7D6DTC PTE

D5F/Q

D4X

D3X

D2X

D1X

D0X

DTC = DT Connect enable. 0 = disable. 1 = enable a DT Connect "MasterOut". Data is available as each A/D conversion is completed. The slave
must reply before the next conversion is complete.
PTE = Post Trigger Enable. 0 = disable. 1 = Enable the post-trigger counterto demarcate the boundary between pre- and post- trigger data.
F/Q = FIFO buffer status /CGQ Active. Read: 1 = Overrun. A logical ORof the fault conditions FIFO Full, DTC overrun and DMA overrun. 0= nofault.

24 DIGITAL & 3 COUNTER FEATURES

I/O & CONTROL REGISTER MAP
The CIO-DAS16/M1 uses 16 I/O addresses for registers which control
triggering, A/D sample rate, channel/gain queue and transfer mode. An
additional 8 registers control digital and counter I/O.

24 Lines of TTL Digital I/O (8255)
3 Sixteen Bit Counters (8254)
10 MHz Oscillator on board
Internal Jumpers for Counter Chaining

I/O ADDR.

FUNCTION R/WI/O ADDR.

FUNCTION R -/W

BASE + 0
BASE + 1
BASE + 2
BASE + 3
BASE + 4
BASE + 5
BASE + 6
BASE + 7

A/D Low Byte / Start A/DA/D High Byte / NACounter Source Control
Digital 4 In / Digital 4 Out
A/D Status / IR Clr
Control Settings / Control
CGQ Address
Gain & Range Queue

BASE + 8
BASE + 9
BASE + A
BASE + B
BASE + C
BASE + D
BASE + E
BASE + F

Q Counter 0 / Load
Q Counter 1 / Load
Q Counter 2 / LoadNA / 8254 Control
Counter 0 / Counter 0 LoadCounter 1 / Counter 1 LoadCounter 2 / Counter 2 Load
NA / 8254 Counter Control

For applications which require multiple digital inputs and outputs,or counters, a second connector at the rear of the board provides
access to one 82C55 DIO chip and one 82C54 counter. The
configuration of the connector is identical to the CIO-DIO24/
CTR3. Digital I/O points may be used to sense contact closures orcontrol relays.

I/O ADDR.

24 DIGITAL I/O & 3 COUNTERS

BASE + 400
BASE + 401
BASE + 402
BASE + 403

PORT A , 82C55
PORT B, 82C55PORT C, 82C55
82C55 CONTROL

CTR 0, 82C54
CTR 1, 82C54
CTR 2, 82C54
82C54 CONTROL

Three, sixteen bit counters allow you to measure frequency or count
events like the number of times a door opens, or items passing on aconveyor belt. The 8254 counter is easy to program and use fromany language.

BASE + 404
BASE + 405
BASE + 406
BASE + 407

STANDARD DAS16 ANALOG CONNECTOR
The 37 pin D connector on the CIO-DAS16/M1 is identical to thatof the CIO-DAS16.

LLGND

19CH0 LOW

18

CH1 LOW

17

CH2 LOW

16

CH3 LOW

15CH4 LOW

14CH5 LOW

13CH6 LOW

12CH7 LOW

11NC10NC9NC8GND7DGI. IN 16DIG. IN 35D IG . OU T 14D IG . 3 OU T

3CTR 0 OU T

2+ 5 V PC B U S

137

CH0 HIGH

36

CH1 HIGH

35

CH2 HIGH

34

CH3 HIGH

33

CH4 HIGH32

CH 5 HIGH

31

CH 6 HIGH30

CH 7 HIGH

29

LLGND

28

LLGND

27

NC

26

SS&H OUT25

DIG . IN 0 / TRIG GER

24

DIG. IN 223

D IG . OU T 022

D IG . OU T 221C TR 0 CL O CK I N20CTR 2 OUTV I E W F R O M R E A R OF P CBASE ADDRESSThe base address switch controls theblock of I/O addresses occupied by theCIO-DAS16/M1. The CIO-DAS16/
M1 occupies 16 addresses. The 24
digital I/O and 3 counters use 8 addresses in the PC unused address space
above 3FF Hex.

Of course, the pins whichcarry analog output signals on the CIO-DAS16
are no-connect (NC) onthe DAS16/M1 board.
These pins are left floating rather than tied toground or some other signal. That way your existing cables and connections will be compatible.
Because of Computer
Boards' strict adherence
to standards, cables andall of your existing hookups are 100% compatible
with the DAS16 connector in the 8 channel differential mode.

Address 300H shown9 8 7 6 5 4 3SWA9A8A7A6A5A4A3HEX
200
10080
40
20
108Please look at the connector diagram which shows the counter's
input, gate and output pin assignments. If you would like to learn
more about the 8254 counter, Intel publishes a data sheet that you
can obtain from their web site.

DIGITAL & COUNTER SPECIFICATIONS# TTL Digital I/O
Logic low level
Logic high level
Output low sink current
Output high source current
8254 COUNTER
Type - Fully programmable
Control - TTL Level
Max Input Frequency

24 as 3, 8 bit ports-0.5 to 0.8V
2.0 to 5.5V
0.4V @ 2.5mA
3.0V @ -2.5mA
16 Bit Down Counter
Gated Input
10MHz - On board Osc

DIGITAL
I/O CONNECTOR
The connector carries 24 digital I/O lines and +5V from the
PC power, or for the CTR3board, plus the counter inputs
and outputs.
The 8255 has 24 I/O lines. The
chip is configured as 3 ports.
Two ports, A & B, are 8 bits
wide. Port C may be an 8 bit
port or two 4 bit ports.
Individual ports may be configured as Input or Output and are
written to and read from as aunit.
Counter inputs, gates and outputs may be controlled orchained at the connector, or
inboard on a counter chaining
jumper.

UNIVERSAL LIBRARY
DOS & Windows- Language Libraries
Programmers will appreciate the easy to use programming library, The
Universal Library. It is universal in two ways. Universal functional syntax forall boards means that the program does not change no matter which A/D board
you use as long as boards share common features. Universal language syntax
means that the code is easily understood in all the languages supported
because the syntax is constant across all languages.
The full range of capability for the CIO-DAS16/M1 is supported and newlanguages are being added. Please see the data sheet for the UniversalLibrary

VI Components
Windows Language Libraries Plus VBx, OCX or ActiveX
controls
VI Components are a collection of routines you use like tools to save time solving
programming problems, like adding graphics or analysis to your programs.
Solve Regression & Simultaneous equations. Do FFTs, matrix math or curvefitting. Display the results with charting graphics or 3 D plotting routines.
Please see the data sheet for VI Components.

DT ConnectTM High Speed Board-to-Board Interface
High speed transfers of data from the data acquisition board to special function boards, such asarray processors or large sample buffers are best handled by dedicated interboard interfaces.
Several such interfaces have been proposed by data acquisition vendors and one, DT-Connect
has emerged as a standard.
Shown here is a high speed array processor connected to the CIO-DAS16/M1. A number ofvendors subscribe to the DT-Connect standard for interboard communication because large
blocks of data may be transferred at rates up to 10,000,000 Bytes/Sec independent of the PCbus.

MEGA-FIFO HUGE SAMPLE BUFFER
Some 1MHz plus A/D boards come with a 1Mega Sample (MS)buffer on board, others can hold as much as 4MS. Only the CIODAS16/M1 can store up to 128 million samples completely independent of PC memory. Imagine 2MS, 8MS, 32MS or 128MS - fullspeed - fully independent!
Because the MEGA-FIFO gets data from the A/D board over the DTConnect interface and not through the PC bus, transfer speeds areunaffected by PC overhead. Likewise, the A/D system does not slow
down the PC which may be number crunching, painting graphics ormoving data across networks.

Populate the MEGA-FIFO with Standard SIMMs
The MEGA-FIFO is sold without memory because you may haveolder 256K or 1M SIMMs stored in a drawer somewhere; the same
as you would use in a PC. If you do not, you can buy standard 80nS
SIMMs from a number of sources and the price is always falling. TheMEGA-FIFO holds 16 SIMMs. Populate as follows with 256K
SIMMs for 2MS, 1MBs for 8MS, 4MBs for 32MS or 16MBs for
128 Million Samples of A/D buffer!

CIO-DAS16/330

ORDERING GUIDE
1MHz Max Analog Input for AT/386 bus

CIO-DAS16/M1

128 MEGA Sample Buffer Board
Sold without memory - Takes 256K, 1M, 4M, 16M SIMMs

MEGA-FIFO

Universal Library Programming Language Library

UNIV-LIBRARY

Screw Terminal Boards
16" X 4" all signals from one 37 D plus proto area.
4" X 4" all signals from one 37 D connector.
16" X 4" all signals from one 37D, Spade Lug Terminals.

CIO-TERMINAL
CIO-MINI37
CIO-SPADE50

Cables40 Pin connector to D37 backplate
2 foot ribbon cable, 37 conductor, female connectors.
'N' foot ribbon cable, 37 conductor, female connectors.
5 foot shielded cable, molded female connectors, 37 cond.
10 foot shielded cable, molded female connectors, 37 cond.

BP40-37
C37FF-2
C37FF-N
C37FFS-5
C37FFS-10

Measurement Computing Corporation
10 Commerce Way
Suite 1008
Norton, Massachusetts 02766(508) 946-5100
Fax: (508) 946-9500
E-mail: info@mccdaq.com
www.mccdaq.com