QSFP+ Series
QO850-QSF-MP.M SeriesMulti-Mode 40GBASE-SR4
QSFP+ Transceiver
RoHS CompliantFeatures◆

Compliant to the IEEE 802.3ba (40GBASE-SR4)◆Support Interoperability with IEEE 802.3ae
10GBASE-SR Modules of Various Form Factors
such as SFP+, XFP, X2◆

Compliant to the QSFP+ MSA SFF-8436
Specification◆Up to 100m on OM3 and 150m on OM4 MMF◆VCSEL Array Transmitter and PIN Array Receiver◆Single 3.3V Power Supply and Power Dissipation

Applications◆40GBE and 10GBE Interconnects◆

Datacom/Telecom Switch & Router< 1.5W◆

Operates at 10.3125Gbps per Channel◆

Operating Case Temperature: 0℃~+70℃◆I2C interface with Integrated Digital DiagnosticConnections◆Applications

Monitoring◆

Data Aggregation and Backplane◆

Utilizes a Standard 12/8 Lane Optical Fiber withProprietary Protocol and Density
Application

MPO Connector◆

Safety Certification: TUV/UL/FDA*Note1◆

RoHS Compliant

Ordering Information
Part No.
QO850-QSF-MP.M

Data Rate

Fiber

Distance*(note2)

InterfaceTemp.

DDMI40Gbps

MMF

100m/150m

MPO

0℃~+70℃

Yes

Note1: For the latest certification information, please check with Data Controls.
Note2: 100m with OM3 MMF and 150m with OM4 MMF.
*The product image is only for reference purpose.

Data Controls Proprietary and Confidential Share Under NDA
Page 1 of 6
sales@dci.jp www.dci.jp

V1.m

QSFP+ Series
Absolute Maximum Ratings*Parameter

Symbol

Min.

Max.

Unit

Storage Temperature

Ts-40+85°C

Supply Voltage

Vcc

-0.5

3.6

V

Operating Relative Humidity

RH585%*Exceeding any one of these values may destroy the device immediately.

Recommended Operating Conditions
Parameter

SymbolMin.

Typ.

Operating Case Temperature

TC0Power Supply VoltageVcc

3.135

Power Supply Current

Icc

Aggregate Bit Rate

BRAVE

41.25

Gbps

Lane Bit Rate

BRLANE

10.3125

Gbps

3.3

Max.

Unit

+70°C

3.465

V450mA

Optical and Electrical Characteristics
Parameter

Symbol

Min.

Typ.

Max.

Unit

OM3 MMF

L

0.5-

100m

Aggregate Bit Rate

BRAVE

-40-Gbps

Per Lane Bit Rate

BRLANE-

10.3125-Gbps

Center Wavelength

λC

840

850

860nm

RMS Spectral Width

RMS--0.65

nm

Average Launch Power, each Lane*(note3)

Pout-7.6-

2.4dBmTransmit OMA, per Lane

TX_OMA-5.6-3dBm

Difference in Launch Power between Any Two Lanes(OMA)--4dB

Peak Power, each Lane--4dBmTransmitter

Transmitter and Dispersion Penalty, each Lane

TDP-

-

3.5

dB

Extinction Ratio*(note4)

ER3-

-dB

Optical Return Loss Tolerance

--

12dB

Average Launch Power of OFF, each Lane

--

-30

dBm

Output Optical Eye*(note4)

IEEE 802.3ba-2010 Compliant

ReceiverCenter Wavelength

λC

Damage Threshold

840

850

860

nm

3.4

--dB-9.5

dBm

Receiver Sensitivity in OMA, each Lane

SenOMA

Stressed Receiver Sensitivity in OMA, each Lane

Pmins---5.4dBm

Maximum Receive Power, each Lane

Pmax--

2.4

dBm

Average power, each Lane

RX-9.5-+2.4

dBm

LOS De-Assert, OMA

LOSD---7.5dBm

Receiver ReflectanceRr---12dB

LOS Assert

LOSA

-30

--dBm

Data Controls Proprietary and Confidential Share Under NDA
Page 2 of 6
sales@dci.jp www.dci.jp

V1.m

QSFP+ Series
LOS Hysteresis

0.5

--dB

Note3: Output is coupled into a 50/125μm multi-mode fiber.
Note4: Filtered, measured with a PRBS 231-1 test pattern @10.3125Gbps

QSFP+ Transceiver Electrical Pad Layout

Pin Arrangement and Definition
PinLogic

1Symbol

Description

Plug
Sequence

Notes
1GND

Ground12CML-I

Tx2n

Transmitter Inverted Data Input

33CML-I

Tx2p

Transmitter Non-Inverted Data Input

3GND

Ground145CML-I

Tx4n

Transmitter Inverted Data Input

36CML-I

Tx4p

Transmitter Non-Inverted Data Input

3GND

Ground178

LVTTL-I

ModSelL

Module Select39

LVTTL-I

ResetL

Module Reset

3VccRx+3.3V Power Supply Receiver

21011

LVCMOS- I/OSCL

2-wire serial interface clock

312

LVCMOS- I/OSDA

2-wire serial interface data

3GND

Ground11314CML-O

Rx3p

Receiver Non-Inverted Data Output

315CML-O

Rx3n

Receiver Inverted Data Output

3GND

Ground116

Data Controls Proprietary and Confidential Share Under NDA
Page 3 of 6
sales@dci.jp www.dci.jp

112

11
V1.m

QSFP+ Series
17

CML-O

Rx1p

Receiver Non-Inverted Data Output

318

CML-O

Rx1n

Receiver Inverted Data Output

319

GND

Ground1120

GND

Ground

1121

CML-O

Rx2nReceiver Inverted Data Output

322CML-O

Rx2p

Receiver Non-Inverted Data Output

3GND

Ground12324CML-O

Rx4n

Receiver Inverted Data Output

325CML-O

Rx4p

Receiver Non-Inverted Data Output

3GND

Ground126

1127

LVTTL-O

ModPrsL

Module Present

328

LVTTL-OIntLInterrupt

329

VccTx+3.3V Power supply transmitter

2230

Vcc1+3.3V Power supply

22

LPModeLow Power Mode

3

GND

Ground131

LVTTL-I

3233

CML-I

Tx3p

Transmitter Non-Inverted Data Input

334CML-I

Tx3n

Transmitter Inverted Data Input

3GNDGround

13536

CML-I

Tx1p

Transmitter Non-Inverted Data Input

337CML-I

Tx1nTransmitter Inverted Data Input

3GNDGround138111

1: GND is the symbol for signal and supply (power) common for the QSFP+ module. All are common within the QSFP+ module andall module voltages are referenced to this potential unless otherwise noted. Connect these directly to the host board signal-common
ground plane.
2: Vcc Rx, Vcc1 and Vcc Tx are the receiver and transmitter power supplies and shall be applied concurrently. Vcc Rx Vcc1 and Vcc
Tx may be internally connected within the QSFP+ Module in any combination. The connector pins are each rated for a maximum
current of 500mA.

Data Controls Proprietary and Confidential Share Under NDA
Page 4 of 6
sales@dci.jp www.dci.jp

V1.m

QSFP+ Series
Mechanical Specifications*This 2D drawing is only for reference, please check with Data Controls before ordering.

Obtaining Document
You can visit our website: https://www.dci.jp
Or contact Data Controls Inc., listed at the end of the documentation to get the latest documents.

Revision History
Revision History

RevisionRelease Date

V1.aPreliminary.

Jul 2, 2012

V1.b

Correct digital interface.

Aug 7, 2012

V1.c

Add photo.

Oct 30, 2012

V1.d

Update min. RX/lane and RegulatoryComplianceMar 20, 2014

V1.e

Update max. RX/lane

Apr 18, 2014

V1.f

Update Regulatory Compliance and
Tr/Tf, Add J2, J9 JitterDec 15, 2014

V1.g
V1.h
V1.i

Update 2D drawing & picture.
Remove some describe about
LOS ,2D drawing and regulatory compliance
Update V1.h revision record: Modify thepower dissipation and voltage tolerance.

Data Controls Proprietary and Confidential Share Under NDA
Page 5 of 6
sales@dci.jp www.dci.jp

Feb 6, 2017
Mar.9, 2017
Apr 12, 2017

V1.m

QSFP+ Series
Remove input voltage tolerance, AC common tolerance, input impedance.
Remove some describe about LOS, TX_DIS and FAULT. Remove output
voltage tolerance, AC common tolerance, Termination, output impedance,
remove rise/ fall Time. Modified 2D drawing and regulatory compliance
V1.j
V1.kUpdate the 2D drawing
Update the product image, regulatory compliance, 2D drawing and contact

Apr 28, 2017
Aug 15, 2018

V1.l

Updated the regulatory complianceinformation.

Dec 14, 2018

V1.m

Add OMA SEN and delete
preliminary.

Jul 30, 2020

Notice:Data Controls reserves the right to make changes or discontinue any optical link product or service identified inthis publication, without notice, in order to improve design and/or performance. Applications that are describedherein for any of the optical link products are for illustrative purposes only. Data Controls makes norepresentation or warranty that such applications will be suitable for the specified use without further testing ormodification.

Contact:
E-mail: sales@dci.jp
https://www.dci.jp

Data Controls Proprietary and Confidential Share Under NDA
Page 6 of 6
sales@dci.jp www.dci.jp

V1.m