PCI-DAS6402/16

Specifications

Document Revision 1.2, February, 2010
© Copyright 2010, Measurement Computing Corporation

Specifications
Typical for 25 °C unless otherwise specified.
Specifications in italic text are guaranteed by design.

Analog input
Table 1. Analog input specifications
A/D converter type
Resolution
Number of channels
Input ranges (SWprogrammable)
Polarity
A/D pacing (SWprogrammable)
Burst mode
A/D gate sources
A/D gating modes

A/D trigger sources
A/D triggering modes

Data transfer
Configuration memory
Channel/gain queue
A/D conversion time
Calibration

AD976A, successive approximation ADC
16 bits
64 single ended; 32 differential
Bipolar: ±10 V, ±5 V, ±2.5 V, ±1.25 V
Unipolar: 0 to 10 V, 0 to 5 V, 0 to 2.5 V, 0 to 1.25 V
Unipolar/Bipolar, software selectable
Internal counter – ASIC
External source (A/D external pacer)
Software polled
Software selectable option, burst rate = 5 µS. Valid for a fixed input range only.
External digital (A/D Pacer Gate)
External analog (Analog Trigger In)
External digital: Programmable, active high or active low, level, or edge
External analog: Software-configurable for:
 Above or below reference Positive or negative hysteresis
 In or out of window
Trigger levels set by D/A OUT 0 and/or D/A OUT 1.
External digital (A/D start trigger in and A/D stop trigger in)External analog (analog trigger in)External digital: Software-configurable for rising or falling edge.
External analog: Software-configurable for positive or negative slope.
Trigger levels set by D/A OUT 0 and/or D/A OUT 1.
Pre-/post-trigger: Unlimited number of pre-trigger samples, 16 Meg post-trigger samples.
Compatible with both digital and analog trigger options.
From 8k RAM buffer via DMA (demand or non-demand mode) using scatter gather.
Programmed I/O
8K words
Up to 8K elements. Programmable channel, gain, and offset.
5 µS
Auto-calibration, calibration factors for each range stored on board in non-volatile RAM.

1

PCI-DAS6402/16

Specifications

Accuracy
200 kHz sampling rate, single channel operation and a 60 minute warm-up. Accuracies are listed for operationaltemperatures within ±2 ºC of internal calibration temperature. Calibrator test source high side tied to Channel 0
High and low side tied to Channel 0 Low. Low-level ground is tied to Channel 0 Low at the user connector.
Table 2. Absolute accuracy
Range±10.000 V±5.000 V±2.500 V±1.250 V
0 V to +10.000 V
0 V to +5.000 V
0 V to +2.500 V
0 V to +1.250 V

Absolute accuracy±3.0 LSB±3.0 LSB±4.5 LSB±4.5 LSB±3.0 LSB±3.0 LSB±4.5 LSB±4.5 LSB
Table 3. Accuracy components

Range

Gain error

Offset error

DLE

ILE

±10.00 V±5.000 V±2.500 V±1.250 V
0 to +10.00 V
0 to +5.000 V
0 to +2.500 V
0 to +1.250 V±1.5 max±1.5 max±2.0 max±2.0 max±1.5 max±1.5 max±1.5 max±1.5 max±1.5 max±1.5 max±2.5 max±2.5 max±1.5 max±1.5 max±3.0 max±3.0 max±1.75 max
±1.75 max
±1.75 max
±1.75 max
±1.75 max
±1.75 max
±1.75 max
±1.75 max

±2 max±2 max±2 max±2 max±2 max±2 max±2 max±2 maxEach PCI-DAS6402/16 is tested at the factory to assure the board’s overall error does not exceed accuracy
limits described in Table 2 above.
As shown in Table 3, total analog input error is a combination of gain, offset, differential linearity and integral
linearity error. The theoretical worst-case error of the board may be calculated by summing these component
errors. Worst case errors are realized only in the unlikely event that each of the component errors are at theirmaximum level, and causing error in the same direction.

System throughput
Table 4. System throughput specifications
Condition

Calibration coefficients

ADC rate (max)

1. Single channel, single input range.
2. Multiple channel, single input range
3. Single channel, multiple input ranges. All
samples in unipolar OR bipolar mode.
4. Multiple channels, multiple input ranges.
All samples in unipolar OR bipolar mode.
5. Multiple channels, multiple input ranges,
switching Unipolar/bipolar mode
6. Multiple channel, single input range,
switching Unipolar/bipolar mode.

Per specified range
Per specified range
Default to value for cbAInScan() range

200 kHz200 kHz200 kHzDefault to value for cbAInScan() range

200 kHzDefault to value for cbAInScan() range

200 kHzDefault to value for cbAInScan() range

200 kHz2

PCI-DAS6402/16

Specifications

Note 1:For conditions 1-2 above, specified accuracy is maintained at rated throughput. Conditions 3-6
apply calibration coefficients which correspond to the range value selected in cbAInScan().
These coefficients remain unchanged throughout the scan. Errors of up to 25 counts may be
incurred when switching gains while in bipolar or unipolar mode only (conditions 3 and 4).
Errors of up to 100 counts may be incurred when mixing unipolar/bipolar modes (conditions 5
and 6).

Crosstalk
Crosstalk is defined here as the influence of one channel upon another when scanning two channels at the
maximum rate. A full scale 100 Hz triangle wave is input on Channel 1; Channel 0 is tied to Analog Ground at
the 100 pin user connector. The table below summarizes the influence of Channel 1 on Channel 0 with theeffects of noise removed. The residue on Channel zero is described in LSBs.
Table 5. Crosstalk specifications
Condition

Crosstalk

Per channel rate

ADC rate

Same range to same range
Any range to any range

3 LSB pk-pk
6 LSB pk-pk

100 kHz100 kHz200 kHz200 kHz

Analog input drift
Table 6. Analog input drift specifications
Analog input full-scale gain drift
Analog input zero drift
Overall analog input drift
Common mode range
CMRR @ 60 Hz
Input impedance
Absolute maximum input voltage

0.25 LSB/°C max
0.21 LSB/°C max
0.46 LSB/°C max±10 V-80 dB min
10 MegOhm min Channel 0: ±15 V, power on or off
 Channels 1-63: –40 V to +55 V, power on or off
60 minutes

Warm-up time

Noise performance
Table 7 below summarizes the noise performance for the PCI-DAS6402/16. Noise distribution is determined bygathering 50K samples with inputs tied to ground at the user connector.
Table 7. Board noise performance
Range

Standard
Deviation% within ±2
counts% within ±1
count

MaxCounts

LSBrms*±10.00 V±5.000 V±2.500 V±1.250 V
0 to +10.00 V
0 to +5.000 V
0 to +2.500 V
0 to +1.250 V

0.8
0.8
0.8
0.9
0.9
0.9
0.9
1.0

98%
98%
98%
97%
97%
97%
97%
95%

78%
78%
78%
73%
73%
73%
73%
68%

9
9
9
10
10
10
10
11

1.4
1.4
1.4
1.5
1.5
1.5
1.5
1.7

* RMS noise is defined as the peak-to-peak bin spread divided by 6.6.

3

PCI-DAS6402/16

Specifications

Analog output
Table 8. Analog output specifications
A/D converter type
Resolution
Number of Channels
Voltage ranges
Monotonicity
Analog output full-scale gain drift
Analog output zero drift
Overall analog output drift
Slew rate
Settling time
Current drive
Output short-circuit duration
Output coupling
Output impedancePower up and reset

AD669BR
16-bits
2±10 V, ±5 V, 0 to 10 V, 0 to 5 V. Each channel independently programmable.
Guaranteed monotonic over temperature±0.55 LSB/°C
10 V ranges: ±0.25 LSB/°C; 5 V ranges: ±0.45 LSB/°C
10 V ranges: ±0.8 LSB/°C; 5 V ranges: ±1.0 LSB/°C
10 V Ranges: 5 V/µs; 5 V ranges: 2.5 V/µs;
20 V step to .0008%:13 µs max; 10 V step to .0008%:6 µs typ±15 mA
Indefinite @ 25 mA
DC
0.1 ohms
DACs cleared to 0 volts ±75 mV max

Accuracy
Table 9. Absolute accuracy specifications
Range

Absolute accuracy±10.000 V±5.000 V
0 to +10.000 V
0 to +5.000 V±4.0 LSB±4.0 LSB±4.0 LSB±4.0 LSB
Table 10. Typical accuracy specifications

Range

Typical accuracy±10.000 V±5.000 V
0 to +10.00 V
0 to +5.000 V±3.5 LSB±3.5 LSB±3.5 LSB±3.5 LSB

Accuracy components
Table 11. Accuracy component specifications
Range

Gain error (LSB)

Offset error (LSB)

DLE (LSB)

ILE (LSB)±10.000 V±5.000 V
0 to +10.00 V
0 to +5.000 V±2.0 max, ±1.5 typ±2.0 max, ±1.5 typ±2.0 max, ±1.5 typ±2.0 max, ±1.5 typ±2.0 max, ±1.0 typ±2.0 max, ±1.0 typ±2.0 max, ±1.0 typ±2.0 max, ±1.0 typ±1.0 max, ±0.5 typ±1.0 max, ±0.5 typ±1.0 max, ±0.5 typ±1.0 max, ±0.5 typ±1.0 max, ±0.5 typ±1.0 max, ±0.5 typ±1.0 max, ±0.5 typ±1.0 max, ±0.5 typ

Each PCI-DAS6402/16 is tested at the factory to assure the board’s overall error does not exceed ±4.0 LSB.
Total analog output error is a combination of gain, offset, integral linearity, and differential linearity error. The
theoretical worst-case error of the board may be calculated by summing these component errors. Worst caseerror is realized only in the unlikely event that each of the component errors are at their maximum level, andcausing error in the same direction. Although an examination of the chart and a summation of the maximum
theoretical errors shows that the board could theoretically exhibit a ±6.0 LSB error, our testing assures this error
is never realized in a board that we ship.
4

PCI-DAS6402/16

Specifications

Typical accuracy is derived directly from the various component typical errors. This typical, maximum error
calculation for the PCI-DAS6402/16 yields ±3.5 LSB. However, this again assumes that each of the errors
contributes in the same direction and the ±3.5 LSB specification is quite conservative.

Analog output pacing and triggering
Table 12. Analog output pacing and triggering specifications
D/A pacing(SW programmable)
D/A gate sources(SW programmable)
D/A gating modes

D/A trigger sources
D/A triggering modes
Data transfer

Throughput

Internal counter – ASIC
External source (D/A external pacer)
Software paced
 External digital (external D/A trigger/pacer gate)
 External analog (analog trigger in) External digital: Programmable, active high or active low, level or edge
 External analog: Software-configurable for above or below reference. Gating levels set by
DAC0 or DAC1External digital (external D/A trigger/pacer gate)
Software triggered
External digital: Software-configurable for rising or falling edge.
 From 16k RAM buffer via DMA (demand or non-demand mode) using scatter gather.
 Programmed I/O
 Update DACs individually or simultaneously (SW selectable)
100 kHz max per channel, 2 channels simultaneous

Digital input/output
Table 13. Digital input/output specifications (main connector)
Digital type (main connector)
Configuration
Output high voltage (IOH = -0.4 mA)
Output low voltage (IOL = 8 mA)
Input high voltage
Input low voltage

Output: 74LS175
Input:
74LS244
4 inputs, 4 outputs (DIN0 through DIN3; DOUT0 to DOUT3)
2.7 V min
0.5 V max
2.0 V min, 7 volts absolute max
0.8 V max, –0.5 volts absolute min

Table 14. Digital input/output specifications (DIO connector)
Digital type (digital I/O connector)
Number of I/O
Configuration

Input high voltage
Input low voltage
Output high voltage (IOH = -2.5 mA)
Output low voltage (IOL = 2.5 mA)
Power-up / reset state

82C55
24 (FIRSTPORTA Bit 0 through FIRSTPORTC Bit 7)
 2 banks of 8 and 2 banks of 4 or
 3 banks of 8 or
 2 banks of 8 with handshake
2.0 V min, 5.5 V absolute max
0.8 V max, –0.5 V absolute min
3.0 V min
0.4 V max
Input mode (high impedance)

Table 15. Simultaneous sample and hold specifications
SSH output

SSH polarity

TTL-compatible output, HOLD is asserted from start of the conversion for
Channel 0 through conversion of the last channel in the scan. Available at user
connector (SSH OUT / D/A PACER OUT). This pin is software selectable as
SSH OUT or D/A PACER OUT.
HOLD high (default) or HOLD low, software selectable5

PCI-DAS6402/16

Specifications

Interrupts
Table 16. Interrupt specifications
Interrupts
Interrupt enable
ADC interrupt sources(sw programmable)

DAC interrupt sources(sw programmable)

External interrupt

PCI INTA# - mapped to IRQn via PCI BIOS at boot-time
Programmable through PLX9080
DAQ_ACTIVE:
Interrupt is generated when a DAQ sequence is active.
DAQ_STOP:Interrupt is generated when A/D Stop Trigger In is detected.
DAQ_DONE:Interrupt is generated when a DAQ sequence completes.
DAQ_FIFO_1/4_FULL:
Interrupt is generated when ADC FIFO is ¼ full.
DAQ_SINGLE:
Interrupt is generated after each conversion completes.
DAQ_EOSCAN:
Interrupt is generated after the last channel is converted in multichannel scans.
DAQ_EOSEQ:
Interrupt is generated after each interval delay during multichannel scans.
DAC_ACTIVE:
Interrupt is generated when DAC waveform circuitry is active.
DAC_DONE:Interrupt is generated when a DAC sequence completes.
DAC_FIFO_1/4_EMPTY: Interrupt is generated DAC FIFO is ¼ empty.
DAC_HIGH_CHANNEL: Interrupt is generated when the DAC high channel output is
updated.
DAC_RETRANSMIT:
Interrupt is generated when the end of a waveform sequence has
occurred in retransmit mode.
Interrupt is generated via edge-sensitive transition on the External Interrupt pin. Rising/fallingedge polarity software selectable.

Counters
Table 17. Counter specifications
User counter type
Configuration
Counter 1 source
Counter 1 gate
Counter 1 output
Clock input frequency
High pulse width (clock input)
Low pulse width (clock input)
Gate width highGate width low
Input low voltage
Input high voltage
Output low voltage
Output high voltage

82C54
One down counter, 16 bits. Counters 2 and 3 not used.
External from connector (CTR1 CLK)
Available at connector (CTR1 GATE).
Available at connector (CTR1 OUT).
10 MHz max
30 nS min
50 nS min
50 nS min
50 nS min
0.8 V max
2.0 V min
0.4 V max
3.0 V min6

PCI-DAS6402/16

Specifications

Pacer
Table 18. Pacer specifications
ADC pacer type
Configuration
ADC pacer Source
ADC pacer Gate
ADC pacer Out
DAC Pacer type
Configuration
DAC pacer source
DAC pacer gate
DAC pacer out
Internal pacer crystal oscillator
Frequency accuracy

ASIC
1 down counter, 24 bits (1 scan interval, 1 sample interval)
40 MHzInternally controlled by software/hardware trigger.
ADC pacer clock, available at user connector (A/D pacer out)
ASIC
1 down counter, 24 bits (1 scan interval, 1 sample interval)
40 MHz or 100 kHz internal source. Software selectable
Internally controlled by software/hardware trigger.
DAC pacer clock. Available at connector. (SSH OUT / D/A PACER OUT). This pin issoftware selectable as SSH OUT or D/A PACER OUT.
40 MHz
50 ppmPower consumption
Table 19. Power consumption specifications+5 V

2.9A typical, 3.3 max

Environmental
Table 20. Environmental specifications
Operating temperature range
Storage temperature range
Humidity

0 to 70 °C-40 to 100 °C
0 to 95% non-condensing

Mechanical
Table 21. Mechanical specifications
Card dimensions

312 mm (L) x 100.6 mm (W) x 16 mm (H)Main connector and pin out
Table 22. Main connector specifications
Connector typeCompatible cables
Compatible accessory products

100-pin high-density unshielded Robinson Nugent
C100FF-x cable (x = length in feet)
BNC-16SE
BNC-16DI
CIO-MINI50
CIO-TERM100
SCB-507

PCI-DAS6402/16

Specifications

Table 23. 32-channel differential mode pin out
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50

Signal name
LLGND
CH0 HI
CH0 LOCH1 HI
CH1 LOCH2 HI
CH2 LO
CH3HI
CH3 LOCH4 HI
CH4 LOCH5 HI
CH5 LOCH6 HI
CH6 LOCH7 HI
CH7 LO
LLGND
CH8 HI
CH8 LOCH9 HI
CH9 LO
CH10 HI
CH10 LO
CH11 HI
CH11 LO
CH12 HI
CH12 LO
CH13 HI
CH13 LO
CH14 HI
CH14 LO
CH15 HI
CH15 LO
D/A GND 0
D/A OUT 0
D/A GND 1
D/A OUT 1
CTR1 CLK
CTR1 GATE
CTR1 OUT
A/D EXTERNAL PACER
ANALOG TRIGGER IN
DIN0
A/D START TRIGGER IN
DIN1
A/D STOP TRIGGER IN
PC +5VSSH OUT / D/A PACER OUT
GND

Pin
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100

Signal name
LLGND
CH16 HI
CH16 LO
CH17 HI
CH17 LO
CH18 HI
CH18 LO
CH19 HI
CH19 LO
CH20 HI
CH20 LO
CH21 HI
CH21 LO
CH22 HI
CH22 LO
CH23 HI
CH23 LO
LLGND
CH24 HI
CH24 LO
CH25 HI
CH25 LO
CH26 HI
CH26 LO
CH27 HI
CH27 LO
CH28 HI
CH28 LO
CH29 HI
CH29 LO
CH30 HI
CH30 LO
CH31 HI
CH31 LO
DOUT0
DOUT1
DOUT2
DOUT3
GND
+12V
GND
-12V
DIN2
DIN3
A/D INTERNALPACER OUTPUT
D/A EXTERNAL PACER INPUT
EXTERNAL D/A TRIGGER/PACER GATE
A/D PACER GATEEXTERNAL INTERRUPT
GND

8

PCI-DAS6402/16

Specifications

Table 24. 64-channel single-ended mode pin out
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50

Signal name
LLGND
CH0 IN
CH32 IN
CH1 IN
CH33 IN
CH2 IN
CH34 IN
CH3 IN
CH35 IN
CH4 IN
CH36 IN
CH5 IN
CH37 IN
CH6 IN
CH38 IN
CH7 IN
CH39 IN
LLGND
CH8 IN
CH40 IN
CH9 INCH41 IN
CH10 IN
CH42 IN
CH11 IN
CH43 IN
CH12 IN
CH44 IN
CH13 IN
CH45 IN
CH14 IN
CH46 IN
CH15 IN
CH47 IN
D/A GND 0
D/A OUT 0
D/A GND 1
D/A OUT 1
CTR1 CLK
CTR1 GATE
CTR1 OUT
A/D EXTERNAL PACER
ANALOG TRIGGER IN
DIN0
A/D START TRIGGER IN
DIN1
A/D STOP TRIGGER IN
PC +5VSSH OUT / D/A PACER OUT
GND

Pin
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100

Signal name
LLGND
CH16 IN
CH48 IN
CH17 IN
CH49 IN
CH18 IN
CH50 IN
CH19 IN
CH51 IN
CH20 IN
CH52 IN
CH21 IN
CH53 IN
CH22 IN
CH54 IN
CH23 IN
CH55 IN
LLGND
CH24 IN
CH56 IN
CH25 IN
CH57 IN
CH26 IN
CH58 IN
CH27 IN
CH59 IN
CH28 IN
CH60 IN
CH29 IN
CH61 IN
CH30 IN
CH62 IN
CH31 IN
CH63 IN
DOUT0
DOUT1
DOUT2
DOUT3
GND
+12V
GND
-12V
DIN2
DIN3
A/D INTERNALPACER OUTPUT
D/A EXTERNAL PACER INPUT
EXTERNAL D/A TRIGGER/PACER GATE
A/D PACER GATEEXTERNAL INTERRUPT
GND

9PCI-DAS6402/16

Specifications

Auxiliary DIO connector and pin out
Table 25. DIO connector specifications
Connector typeCompatible cables

Compatible accessory productswith the C40FF-x cableCompatible accessory productswith the C40-37F-x cableorwith the BP40-37 and the
C37FF-x or C37FFS-x cable

40-pin header connector
 C40FF-x (x = length in feet) C40-37F-x (x = length in feet) BP40-37 (translates to a standard CIO-DIO24 type)
CIO-MINI40
CIO-MINI37
SCB-37
CIO-ERB24
CIO-ERB08
SSR-RACK24
SSR-RACK08
Table 26. Digital I/O connector pin out

Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

Signal nameNC
NC
FIRSTPORTB Bit 7
FIRSTPORTB Bit 6
FIRSTPORTB Bit 5
FIRSTPORTB Bit 4
FIRSTPORTB Bit 3
FIRSTPORTB Bit 2
FIRSTPORTB Bit 1
FIRSTPORTB Bit 0
DGND
NC
DGND
NC
DGND
NC
DGND
PC +5V
DGND
NC

Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

10

Signal name
PC +5VDGND
FIRSTPORTC Bit 7
FIRSTPORTC Bit 6
FIRSTPORTC Bit 5
FIRSTPORTC Bit 4
FIRSTPORTC Bit 3
FIRSTPORTC Bit 2
FIRSTPORTC Bit 1
FIRSTPORTC Bit 0
FIRSTPORTA Bit 7
FIRSTPORTA Bit 6
FIRSTPORTA Bit 5
FIRSTPORTA Bit 4
FIRSTPORTA Bit 3
FIRSTPORTA Bit 2
FIRSTPORTA Bit 1
FIRSTPORTA Bit 0NC
NCMeasurement Computing Corporation
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Suite 1008
Norton, Massachusetts 02766(508) 946-5100
Fax: (508) 946-9500
E-mail: info@mccdaq.com
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PCI-DAS6402_16-spec.doc