SPECIFICATIONS
PC104-DAS16JR/12
PC104-DAS16JR/16
Analog Input, Digital I/O,Counters

Revision 4, August, 2001

© Copyright 2001, MEASUREMENT COMPUTING CORPORATIONPower Consumption+5VDC quiescent
PC104-DAS16Jr/12
140 mA typical, 230 mA max
PC104-DAS16Jr/16
145 mA typical, 205 mA max+ 5VDC Operating (A/D converting to FIFO)
PC104-DAS16Jr/12
250 mA typical, 375 mA max
PC104-DAS16Jr/16
235 mA typical, 350 mA max

Analog Input Section
A/D converter type
PC104-DAS16Jr/16
PC104-DAS16Jr/12
Resolution
PC104-DAS16Jr/12
PC104-DAS16Jr/16
Number of channels
Input ranges
PC104-DAS16Jr/12
PC104-DAS16Jr/16
Polarity
A/D Pacing
A/D Trigger sources
A/D Triggering Modes
Digital:Data transfer
DMA
DMA enable
A/D conversion time
PC104-DAS16Jr/12
PC104-DAS16Jr/16
Throughput
PC104-DAS16Jr/12
PC104-DAS16Jr/16
Accuracy
PC104-DAS16Jr/12
PC104-DAS16Jr/16
Integral Linearity error
PC104-DAS16Jr/12
PC104-DAS16Jr/16
Differential Linearity
No missing codes guaranteed
PC104-DAS16Jr/12
PC104-DAS16Jr/16
Gain drift (A/D specs)
PC104-DAS16Jr/12
PC104-DAS16Jr/16
Zero drift (A/D specs)
PC104-DAS16Jr/12
PC104-DAS16Jr/16

AD7805
AD780012 bits
16 bits
8 differential or 16 single-ended, switch-selectable±10V, ±5V, ±2.5V, ±1.25V, ±0.625V, 0 to 10V, 0 to 5V, 0 to 2.5V,0 to 1.25V, fully programmable±10V, ±5V, ±2.5V, ±1.25V programmable in Bipolar mode OR 0 to10V, 0 to 5V, 0 to 2.5V, 0 to 1.25V programmable in Unipolar mode
Unipolar/Bipolar, switch-selectable
Programmable: internal counter, external source (Din 0 / Trigger) orsoftware polled
External polled gate trigger (DIn 0)
Gated pacer, software polled. (Gate must be disabled by software aftertrigger event.)
From 512 sample FIFO via interrupt, DMA or software polledChannel 1 or 3, switch-selectable
Programmable

3.3 µs
10 µs
150 kHz100 kHz
0.01% of reading, ±1LSB
0.003% of reading, ±1LSB±1 LSB±1.5 LSB (±3LSB on 1.25V ranges)±1 LSB
12 bits
16 bits±6 ppm/°C±7 ppm/°C±1 ppm/°C±2 ppm/°C

Common Mode Range
CMRR @ 60 Hz
Input leakage current (@ 25 deg C)
Input impedance
Absolute maximum input voltage±10V70 dB±20 nA
10 Mohms min±35V

Digital I/O Section
Digital type
Configuration
Input low voltage
Input high voltage
Output low voltage (IOL = 4 mA)
Output high voltage (IOH = −4 mA)
Absolute maximum input voltage
Interrupts
Interrupt enable
Interrupt sources

FPGA
Two ports, 4 bits each, 4 input and 4 output
0.8V max
2.0V min
0.32V max
3.86V min
−0.5V , +5.5V
Programmable: levels 2 to 7
ProgrammableEnd-of-conversion, DMA terminal countCounter Section
Counter type
Configuration

82C54
3 down-counters, 16 bits each
Counter 0 - Independent user counter
Source: Programmable (external or100 kHz internal source)
Gate: Available at connector (DIn 2)
Output: Available at connector (Ctr 0 Out)Counter 1 - ADC Pacer Lower Divider
Source: Jumper-selectable 1/10 MHz
Gate: Tied to Counter 2 gate, can be program-enabled at user
connector (DIn 0 / Trigger).
Output: Chained to Counter 2 Clock.
Counter 2 - ADC Pacer Upper Divider
Source: Counter 1 Output.
Gate: Tied to Counter 1 gate, programmable source.
Output: Programmable as ADC Pacer clock, hardwired to user
connector (Ctr 2 Out)Clock input frequency
High pulse width (clock input)
Low pulse width (clock input)
Gate width highGate width low
Input low voltage
Input high voltage
Output low voltage
Output high voltage

10 MHz max
30 ns min
50 ns min
50 ns min
50 ns min
0.8V max
2.0V min
0.4V max
3.0V minCrystal oscillator
Frequency
Frequency accuracy

10 MHz
100 ppm

Environmental
Operating temperature range
Storage temperature range
Humidity

0 to 50°C−40 to 100°C
0 to 90% non-condensing

Measurement Computing Corporation
10 Commerce Way
Suite 1008
Norton, Massachusetts 02766(508) 946-5100
Fax: (508) 946-9500
E-mail: info@mccdaq.com
www.mccdaq.com