R3-11

SASIMI 2021 Proceedings

Compact FPGA Implementation of Popcounter for BNN
Using Linear Feedback Shift RegisterNagisa ISHIURA

Ryota SAIMYOJI

School of Science and Technology, Kwansei Gakuin University
2-1 Gakuen, Sanda, Hyogo, 669–1337, Japan

Abstract— This paper presents an idea for reducing the size ofneurons for inference of binarized neural networks with a viewto pack as many neurons as possible in FPGAs to increase parallelism. We focus on input-serial neurons and use LFSRs (linear feedback shift registers) in place of binary counters. We alsopresents an idea to use LFSRs in parallel-serial hybrid neurons.
Implemented on Xilinx Artix-7, the number of LUTs is reduced
by 68.8% and 12.1% for a serial neuron and a hybrid neuron ofparallelism 16 , respectively, for threshold 3840.

y=Tx

en

w

t

counter RST enx
w

LUT

Fig. 1. Input-serial Neuron.

rst

LUT

LUT

c[0]
Q D
R enx
w

LUT

c[1]
Q D
R en

LUT

c[2]
Q D
R en

LUT

c[3]
Q D
R en

LUT

c[4]
Q D
R en

LUT

Q D
R en

LUT

c[5]

Let N be the number of inputs to a neuron in a BNN. Letxi and wi in {−1, +1} be the activation value and the weight for
the i-th input, respectively, b ∈ Z be the bias of the neuron.
TheN activation value y of the neuron is expressed as y = f (b +i=1 wi · xi ), where f (x) = 1 if 0 ≤ x and f (x) = −1 otherwise.
In the inference phase, we can represent −1 and +1 by 0 and 1,respectively, then multiplication for xi and wi is reduced to an
exclusive-NOR operation. Hereafter, for notational simplicity,
we denote the binary representation of xi and wi by simply xi

RST

rst(b) Economized implementation (t = log2 T )

yII. Binarized Neural Network (BNN)

counterrst(a) Fully serial implementation (n = log2 N)Introductionxw(a) Binary counter implementation
yc[5]

c[4]

c[3]

c[2]

c[1]

c[0]

Q D
R en

Q D
R en

Q D
R en

Q D
R en

Q D
R en

Q D
S en

LUT

Following the recent success of neural network technologies, deep learning is now widening the scope of its applications. One of the trends in this area is the shift from cloud toedge. Especially, neural inference on edge devices is expected
to further expand application domain of machine learning.
With this in view, active researches are being conducted on
developing eﬃcient hardware schemes for neural network inference. A binarized neural network (BNN), a neural networkwith binary weights and activations [1], is one of the promising
schemes to reduce hardware size and many eﬃcient hardware
architectures for BNNs have been proposed so far [2, 3, 4].
Since practical neural networks consist of a huge number ofneurons which in principle run in parallel, there is abundantparallelism to exploit in hardware design. Then, how to implement neuron hardware eﬃcient both in speed and in area isa key issue. In the case of FPGA implementation, to increase“operations per second per LUT” is one of the design goals.
In this paper, we present an idea for reducing the size of neurons in BNNs. We focus on input-serial neurons and replace anordinary binary popcounters with LFSRs. We also presents anidea of using LFSRs in the parallel-serial hybrid neurons. Implementation on a Xilinx Artix-7 FPGA shows that the numberof LUTs is reduced by 68.8% and 12.1% for a serial neuron and16-parallel hybrid neuron, respectively, for threshold 3840.

nT<LUTI.

yrst(b) LFSR implementation
Fig. 2. LUT-based Implementation of serial Neuron.

and wi . The computation of f is translated into counting of thenumber of 1’s in {xi ⊕ wi | 1 ≤ i ≤ N} and examining if it isgreater than or equal to threshold T , where T = (N + b)/2.
In an input-serial neuron, xi ⊕ wi is computed one by onefor each i and the number of 1’s are counted in N steps, while
in a parallel-serial hybrid neuron, P inputs are processed inparallel to complete the computation in N/P steps. The serial
neurons are the slowest, but their small implementation allows
exploiting other dimensions of parallelism, such as the neuron
parallelism or the feature map parallelism.
Fig. 1 (a) shows an example design of a serial neuron. We
assume that xi and wi are supplied serially from registers ormemories. The counter is n-bit wide where n = log2 N andits value is compared against T . We also assume that T isembedded [4], that is, each neuron works for a ﬁxed threshold.
Fig. 1 (b) shows a slightly economized design. It stops theincrement as soon as the count reaches T , which reduces thenecessary bits of the counter to t, where t = log2 T . When T
is greater than N/2, we may count 0’s instead of 1’s, so we canreduce the counter size at least by 1 bit.
III. LFSR Implementation of Popcounters

A. Serial Neuron
Fig. 2 (a) shows LUT-based implementation of a serial neuron using a t-bit binary counter (t = 6 in this case). Since the- 179 -T<register+p’+...

ymux

0t’x1
w1x2
w2xP
wP

TABLE I
Synthesis results.

(a) Typical implementation=T1p’s

LFSR

en+

msb

pp

binary+...

=T 1+1

y0
mux

p’x1
w1x2
w2xP
w

P

<T0

#cycle
257
513
1025
2049
4097
8193

NT
256 120512 2401024 480
2048 960
4096 1920
8192 3840(b) Parallel-serial hybrid neuron (P = 16)binaryLFSR#cycle #FF #LUT delay [ns] #FF #LUT delay [ns]
17
731
3.973
8273.995
33829
3.965
927
3.973
65929
3.961
1028
4.106
129
1031
3.998
1028
4.106
257
1132
4.110
1128
4.347
513
1233
4.376
1229
4.383

Fig. 3. Parallel-serial hybrid popcounter.

B. Parallel-Serial Hybrid Neuron
Fig. 3 (a) illustrates a structure of a hybrid neuron where P
inputs are processed at a time. P exclusive-NORs are computed and resulting 1’s are counted by an adder. The adder isp -bit wide where p = log2 (P + 1). The counts are accumulated into a t -bit wide register, where t = log2 (T +P−1), andaccumulation is disabled when the count reaches the threshold.
Since LFSRs does not ﬁt directly in the parallel-serial implementation, we propose an LFSR-binary hybrid implementation. The proposed design is illustrated in Fig. 3 (b). Theregister is divided into the lower p bits and the upper s bits,
where p = log2 P and s = t − p. While the lower part is abinary counter, the upper part is an LFSR. T 0 and T 1 are thelower p bits and the upper s bits of T . The design in (b) isalmost equivalent to that in (a) when the LFSR is replaced byan ordinary counter. Thus reduction of the LUT count on theupper part is expected by the use of the LFSR.
IV.

LFSR
#FF #LUT delay [ns]
74
4.358
8
4
4.376
95
4.509
105
4.360
115
4.353
125
4.353

NT
256 120512 2401024 480
2048 960
4096 1920
8192 3840(b) LFSR-binary hybrid implementationnext value of c[i] (the i-th bit of the counter) depends on c[0]through c[i], at least t LUTs are necessary. More LUTs will benecessary for larger t, for c[i]’s function has i + 1 inputs which
may exceed the maximum input number of an LUT.
We propose to replace the binary counter by a Fibonacci
LFSR. This results in a design in Fig. 2 (b) where the primitive
polynomial is x6 + x + 1. c[1] through c[5] need no LUT andc[0] only one LUT for exclusive-ORing c[5] and c[0]. Since nth order primitive polynomials with 3 or 5 terms exist for largen, a single LUT is enough to compute the feedback to c[0].

(a) Serial neuron
binary#FF #LUT delay [ns]77
4.391
894.387
994.524
10104.414
11124.519
1216
4.502

Target: Xilinx Artix-7, Synthesizer: Xilinx Vivado (2016.4)

tation consumed 12.1% fewer LUTs for T = 3840.
Considering that the delay of the serial and hybrid neurons isalmost the same, the hybrid neurons are more eﬃcient in termsof operations per second per LUT.
V. Conclusion
An idea of implementing BNN neurons using LFSRs has
been presented. This helps accommodating more neurons toexploit parallelism in neural inference.
We are working on designing a whole layer or a whole BNN
to evaluate the impact of our scheme. Moreover, the latest
FPGA chips have various features and auxiliary circuits, which
we will exploit to implement smaller neuron modules.

Acknowledgments
Authors would like to express their appreciation to Dr. Hiroyuki Kanbara of ASTEM/RI, Prof. Hiroyuki Tomiyama of
Ritsumeikan University, and Mr. Takayuki Nakatani (formerlywith Ritsumeikan University) for their discussion and valuablecomments. We would also like to thank to the members ofIshiura Lab. of Kwansei Gakuin University.
References

Preliminary Result

We implemented neuron modules in Verilog HDL based on
the proposed scheme, which are synthesized targeting Xilinx
Artix-7 using Xilinx Vivado (2016.4).
Table I (a) summarizes the result for the serial neurons. Notethat the circuit size depends only on T but not on N. #cycle
shows the number of execution cycles. In the case of serial
neurons, it takes N + 1 cycles (one cycle for initialization).
The number of the ﬂip-ﬂops is log2 T  for the all schemes.
Our design consumed fewer LUTs, as was suggested in Fig. 2.
A neuron for T = 3840 can be implemented with only 5 LUTs,
which is 68.8% fewer than the binary counter implementation.
The delay is almost the same between the two schemes.
Table I (b) lists the result for hybrid neurons for P = 16.
Though the impact of LFSRs on the LUT count became
smaller than that of the serial neurons, the LFSR implemen-[1] M. Courbariaux, et al.: “Binarized neural networks: Training deep neural networks with weights and activations
constrained to +1 or −1, pComputer Research Repository(Mar. 2016).
[2] H. Nakahara, H. Yonekawa, T. Sasao, H. Iwamoto, and M.
Motomura: “A memory-based realization of a binarized
deep convolutional neural network,” in Proc. FPT 2016,
pp. 273–276 (Dec. 2016).
[3] K. Ando, et al.: “BRein memory: A single-chip binary/ternary reconﬁgurable in-memory deep neural network accelerator achieving 1.4 TOPS at 0.6 W,” IEEE J.
Solid-State Circuits, 53-5, pp. 983–994 (Apr. 2018).
[4] R. Sugimoto and N. Ishiura: “Parameter embedding foreﬃcient FPGA implementation of binarized neural networks,” in Proc. SASIMI 2019, pp. 41-45 (Oct. 2019).

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