PCI-DAS6023 andPCI-DAS6025

Specifications

Document Revision 2.2, February, 2010
© Copyright 2010, Measurement Computing Corporation

Specifications
Typical for 25 °C unless otherwise specified.
Specifications in italic text are guaranteed by design.

Analog inputs
Table 1. Analog input specifications
A/D converter type
Resolution
Number of channels
Input ranges
A/D pacing(SW programmable)

Burst mode
A/D gate sources
A/D gating modes
A/D trigger sources
A/D triggering modes
ADC pacer out
RAM buffer size
Data transfer
DMA modes
Configuration memory
Streaming-to-disk rate

Successive approximation type, min 200 kS/s conversion rate.
12 bits, 1-in-4096
16 single ended / 8 differential. Software selectable±10 V, ±5 V, ±500 mV, ±50 mV. Software selectable
Internal counter – ASIC. Software selectable time base: Internal 40 MHz, 50 ppm stability
External source via AUXIN<5:0>. Software selectable.
External convert strobe: A/D CONVERT
Software paced
Software selectable option, burst rate = 5 µS.
External digital: A/D GATE
External digital: Programmable, active high or active low, level or edge
External digital: A/D START TRIGGER
A/D STOP TRIGGER
External digital: Software-configurable for rising or falling edge.
Pre-/Post-trigger: Unlimited number of pre-trigger samples, 16 Meg post-trigger samples.
Available at user connector: A/D PACER OUT
8 k samples
DMA
Programmed I/ODemand or non-demand using scatter gather.
Up to 8 k elements. Programmable channel, gain, and offset
200 kS/s, system dependent

Accuracy
200 kS/s sampling rate, single channel operation and a 15-minute warm-up. Accuracies listed are formeasurements made following an internal calibration. They are valid for operational temperatures within ±1 °Cof internal calibration temperature, and ±10 °C of factory calibration temperature. Calculations for Absolute
Accuracy are based on the average of 100 measurements performed at the max input voltage for a given range,measured after one year. Calibrator test source high side tied to channel 0 high, and low side tied to channel 0low. Low-level ground is tied to channel 0 low at the user connector.
Table 2. Absolute accuracy specifications
Range

Absolute Accuracy

±10 V
±5 V
±500 mV±50 mV±2.0 LSB±2.0 LSB±3.0 LSB±4.0 LSB1

PCI-DAS6023 and PCI-DAS6025

Specifications

Table 3. Absolute accuracy components - all values are (±)
Range% ofReading

Offset(mV)

Averaged Noise +Quantization (mV)1

Temp Drift(%/ C)

Absolute Accuracy
at FS (mV)

±10 V
±5 V
±500 mV±50 mV

0.05580.05630.10460.1340

2.930
1.460
0.150
0.024

1.262
0.605
0.057
0.007

0.00100.00100.00100.0010

9.77
4.88
0.73
0.098

1

Averaged measurements assume dithering and averaging of 100 single-channel readings.
Table 4. Differential non-linearity specifications

All ranges±0.5 LSB typ±1.0 LSB max

System throughput
Table 5. System throughput specifications
Condition

Calibration Coefficients

ADC Rate (max)

1. 1. Single channel, single input range.
2. 2. Multiple channel, single input range
3. 3. Single channel, multiple input
ranges.

Per specified range
Per specified range
Default to value for cbAInScan() range

200 kS/s
200 kS/s
200 kS/s

Note 1:For conditions 1-2 above, specified accuracy is maintained at rated throughput. Condition 3
applies a calibration coefficient which corresponds to the range value selected in cbAInScan().
This coefficient remains unchanged throughout the scan. Increased settling times may occur
during gain-switching operations.

Settling time
Settling time is defined here as the time required for a channel to settle to within a specified accuracy inresponse to a full-scale (FS) step. Two channels are scanned at a specified rate. A –FS DC signal is presented tochannel 1; a +FS DC signal is presented to channel 0.
Table 6. Settling time specifications
Condition

Same range to same rangeAny range to any range

Range±10 V±5 V±500 mV±50 mV-Accuracy±0.012%(±0.5 LSB)

±0.024%(±1.0 LSB)

±0.098%(±4.0 LSB)

5 µS typ5 µS typ5 µS typ5 µS typ25 µS typ5 µS max
5 µS max
5 µS max
5 µS max
20 µS typ5 µS max
5 µS max
5 µS max
5 µS max
15 µS typ2

PCI-DAS6023 and PCI-DAS6025

Specifications

Parametrics
Table 7. Parametrics specifications
Maximum working voltage(signal + common-mode)
CMRR @ 60 Hz

Small signal bandwidth, all ranges
Large signal bandwidth, all ranges
Input coupling
Input impedance
Input bias current
Input offset current
Absolute maximum input voltage

Crosstalk

Input must remain within ±11 V of ground±10 V:
85 dB
±5 V:
85 dB
±500 mV:
90 dB±50 mV:
90 dB
500 kHz225 kHzDC
100 GOhm in normal operation.
Min 10 MOhm in powered off or overload condition.
±200 pA±100 pA–40 V to +55 V, power on or off. Protected inputs: CH<15:0> IN AISENSE
Adjacent channels: -60 dB
All other channels: -80 dBNoise performance
Table 8 summarizes the noise performance for the PCI-DAS6025, PCI-DAS6023. Noise distribution isdetermined by gathering 50 K samples with inputs tied to ground at the user connector. Samples are gathered at
the maximum specified single-channel sampling rate. Specification applies to both single-ended and differential
modes of operation.
Table 8. Analog input noise performance (not including quantization)
Range

Typical Counts
Dithered

LSBrmsDithered

Typical Counts
Undithered

LSBrms
Undithered±10 V±5 V±500 mV±50 mV44470.6
0.60.60.82234

0.1
0.1
0.1
0.7

3

PCI-DAS6023 and PCI-DAS6025

Specifications

Analog outputs (PCI-DAS6025 only)
Table 9. Analog output specifications (PCI-DAS6025)
D/A converter type
Resolution
Number of channels
Voltage range
Monotonicity
DNL
Slew rate
Settling time
Noise
Glitch energy
Current drive
Output short-circuit duration
Output coupling
Output impedancePower up and reset

Double-buffered, multiplying
12-bits, 1-in-4096
2 voltage output±10 V
12-bits, guaranteed monotonic±1.0 LSB max
10 V/µs min
20 V step to 0.012% (0.5 LSB): 10 µs max
200 µVrms, DC to 1 MHz BW±24 mV @ 2 µs duration measured at mid-scale transition.
±5 mA
Indefinite @25 mA
DC0.1 ohms max
DACs cleared to 0 volts ±200 mV max
Table 10. Absolute accuracy specifications

Range

Absolute Accuracy±10 V±1.7 LSB
Table 11. Absolute accuracy components

Range% of Reading

Offset(mV)

Temp Drift(%/DegC)

Absolute Accuracy at FS (mV)

±10 V

±0.0219±5.93±0.0005±8.127

Each PCI-DAS6025 is tested at the factory to assure the board’s overall error does not exceed ±1.7 LSB.
Table 12. Relative accuracy specifications
Range

Relative Accuracy±10 V±0.3 LSB, typical±0.5 LSB, max

Relative accuracy is defined as the measured deviation from a straight line drawn between measured endpointsof the transfer function.

4

PCI-DAS6023 and PCI-DAS6025

Specifications

Analog output pacing and triggering
Table 13. Analog output pacing and triggering specifications
Internal counter – ASIC. Selectable time base: Internal 40 MHz, 50 ppm stability.
 External source via AUXIN<5:0>, SW selectable.
External convert strobe: D/A UPDATE
Software paced
External digital: D/A START TRIGGER
Software gatedExternal digital: Programmable, active high or active low, level or edge
External digital: D/A START TRIGGER
Software triggered
External digital: Software-configurable for rising or falling edge.
Available at user connector: D/A PACER OUT
16 K samples
DMA
Programmed I/OUpdate DACs individually or simultaneously, software selectable.
Demand or non-demand using scatter gather.
10 kS/s max per channel, 2 channels simultaneous

DAC pacing(software programmable)

DAC gate source(software programmable)
DAC gating modes
DAC trigger sources
DAC triggering modes
DAC pacer out
RAM buffer size
Data transfer

DMA modes
Waveform generation throughput

Analog input/output calibration
Table 14. Analog I/O calibration specifications
Recommended warm-up timeCalibration
Onboard calibration reference

Calibration interval

15 minutes
Auto-calibration, calibration factors for each range stored on board in non-volatileRAM.
DC Level: 10.000 V ± 5 mV. Actual measured values stored in EEPROM.
Tempco: 5 ppm/°C max, 2 ppm/°C typicalLong-term stability: 15 ppm, T = 1000 hrs, non-cumulative
1 yearDigital input/output
Discrete
Table 15. Discrete DIO specifications
Digital type
Number of I/OConfiguration

Input high voltage
Input low voltage
Output high voltage(IOH = -32 mA)
Output low voltage (IOL = 32 mA)
Data transfer
Power-up / reset state

Discrete, 5V/TTL compatible
88 bits, independently programmable for input or output. All pins pulled up to +5 V
via 47 K resistors (default). Positions available for pull-down to ground (factoryconfigured option).
2.0 V min, 7.0 V absolute max
0.8 V max, –0.5 V absolute min
3.80 V min, 4.20 V typ
0.55 V max, 0.22 V typ
Programmed I/O
Input mode (high impedance)

5

PCI-DAS6023 and PCI-DAS6025

Specifications

82C55 (PCI-DAS6025 only)
Table 16. 82C55 specifications (PCI-DAS6025)
Digital type
Number of I/O
Configuration

Pull up/pull-down configuration
Input high voltage
Input low voltage
Output high voltage (IOH = -2.5 mA)
Output low voltage (IOL = 2.5 mA)
Power-up / reset state

82C55
24 (FIRSTPORTA 0 through FIRSTPORTC 7)
2 banks of 8 and 2 banks of 4 or
3 banks of 8 or
2 banks of 8 with handshake
All pins pulled up to +5 V via 47 K resistors (default). Positions available forpull-down to ground (factory configured option).
2.0 V min, 5.5 V absolute max
0.8 V max, –0.5 V absolute min
3.0 V min
0.4 V max
Input mode (high impedance)

Interrupts
Table 17. Interrupt specifications
Interrupts
Interrupt enable
ADC Interrupt sources(software programmable)

DAC Interrupt sources(software programmable)

PCI INTA# - mapped to IRQn via PCI BIOS at boot-time
Programmable through PLX9080
DAQ_ACTIVE:
Interrupt is generated when a DAQ sequence is active.
DAQ_STOP:Interrupt is generated when A/D Stop Trigger In isdetected.
DAQ_DONE:Interrupt is generated when a DAQ sequence completes.
DAQ_FIFO_1/4_FULL:
Interrupt is generated when ADC FIFO is ¼ full.
DAQ_SINGLE:
Interrupt is generated after each conversion completes.
DAQ_EOSCAN:
Interrupt is generated after the last channel is converted in
multi-channel scans.
DAQ_EOSEQ:
Interrupt is generated after each interval delay duringmulti-channel scans.
DAC_ACTIVE:
Interrupt is generated when DAC waveform circuitry isactive.
DAC_DONE:Interrupt is generated when a DAC sequence completes.
DAC_FIFO_1/4_EMPTY: Interrupt is generated DAC FIFO is ¼ empty.
DAC_HIGH_CHANNEL: Interrupt is generated when the DAC high channel output
is updated.

6

PCI-DAS6023 and PCI-DAS6025

Specifications

Counters
Table 18. Counter specifications
User counter type
Number of channels
Resolution
Compatibility
CTRn base clock source (software selectable)
Internal 10 MHz clock source stability
Counter n gate
Counter n output
Clock input frequency
High pulse width (clock input)
Low pulse width (clock input)
Gate width highGate width low
Input low voltage
Input high voltage
Output low voltage
Output high voltage

82C54
216-bits
5 V/TTL
Internal 10 MHz, Internal 100 KHz or external connector (CTRn CLK)50 ppmAvailable at connector (CTRn GATE).
Available at connector (CTRn OUT).
10 MHz max
15 ns min
25 ns min
25 ns min
25 ns min
0.8 V max
2.0 V min
0.4 V max
3.0 V min7PCI-DAS6023 and PCI-DAS6025

Specifications

Configurable AUXIN<5:0>, AUXOUT<2:0> external trigger/clocks
The PCI-DAS6023 and PCI-DAS6025 provide nine user-configurable trigger/clock pins available at the
100-pin I/O connector. Of these, six are configurable as inputs while three are configurable as outputs.
Table 19. Configurable AUXIN, AUXOUT, and external trigger/clocks
AUXIN<5:0> sources(software selectable)

AUXOUT<2:0> sources(software selectable)

Default selections:Compatibility
Edge-sensitive polarity
Level-sensitive polarity
Minimum input pulse width

A/D CONVERT:
A/D TIMEBASE IN:
A/D START TRIGGER:
A/D STOP TRIGGER:
A/D PACER GATE:
D/A START TRIGGER
D/A UPDATE:
D/A TIMEBASE IN:
STARTSCAN:
SSH:

External ADC convert strobe
External ADC pacer time base
ADC Start Trigger
ADC Stop Trigger
External ADC gate
DAC trigger/gate
DAC update strobe
External DAC pacer time base
A pulse indicating start of conversion
Active signal that terminates at the start of thelast conversion in a scan.
Indicates end of scan
ADC convert pulse
Delayed version of ADC convert
CTR1 clock source
D/A update pulse
CTR2 clock source
ADC Start Trigger Out
ADC Stop Trigger Out
DAC Start Trigger Out
A/D CONVERT
A/D START TRIGGER
A/D STOP TRIGGER
D/A UPDATE
D/A START TRIGGER
A/D PACER GATE
D/A UPDATE
A/D CONVERTSCANCLK

A/D STOP:
A/D CONVERT:SCANCLK:CTR1 CLK:
D/A UPDATE:CTR2 CLK:
A/D START TRIGGER:
A/D STOP TRIGGER:
D/A START TRIGGER:
AUXIN0:
AUXIN1:
AUXIN2:
AUXIN3:
AUXIN4:
AUXIN5:
AUXOUT0:
AUXOUT1:
AUXOUT2:
5V/TTL
Rising/falling, software selectable
Active high/active low, software selectable
37.5 ns8

PCI-DAS6023 and PCI-DAS6025

Specifications

DAQ-Sync inter-board triggers/clocks
The DAQ-Sync bus provides inter-board triggering and synchronization capability. Five trigger/strobe I/O pins
and one clock I/O pin are provided on a 14-pin header. The DAQ-Sync signals use dedicated pins. Only thedirection may be set.
Table 20. DAQ-Sync inter-board triggers/clock specifications
DAQ-Sync signals:

DS A/D START TRIGGER
DS A/D STOP TRIGGER
DS A/D CONVERTDS D/A UPDATEDS D/A START TRIGGERSYNC CLKPower consumption
Table 21. Power consumption specifications+5 V+5 V available at I/O connector

PCI-DAS6025, PCI-DAS6023: 0.9 A typical, 1.1 A max. Does not include
power consumed through the I/O connector.
1 A max, protected with a resettable fuse

Environmental
Table 22. Environmental specifications
Operating temperature range
Storage temperature range
Humidity

0 to 55 °C-20 to 70 °C
0 to 90% non-condensing

Mechanical
Table 23. Mechanical specifications
Card dimensions

PCI half card: 174.6 mm (L) x 106.9 mm (W) x 11.65 mm (H)9PCI-DAS6023 and PCI-DAS6025

Specifications

DAQ-Sync connector and pin out
Table 24. DAQ-Sync connector specifications
Connector typeCompatible cables

14-pin right-angle 100 mil box header
MCC p/n: CDS-14-x, 14-pin ribbon cable.
x = number of boards
Table 25. DAQ-Sync connector pin out

Pin1234567891011121314Signal NameDS A/D START TRIGGER
GND
DS A/D STOP TRIGGER
GND
DS A/D CONVERTGND
DS D/A UPDATEGND
DS D/A START TRIGGER
GND
RESERVEDGNDSYNC CLKGND

Main connector and pin out
Table 26. Main connector specifications
Connector typeCompatible cables
Compatible accessory products(with C100HD50-x cable)

Compatible accessory products(with C100MMS-x cable)

Shielded SCSI 100 D-Type
C100HD50-x, unshielded ribbon cable. x = 3 or 6 feet
C100MMS-x, shielded round cable. x = 1, 2 or 3 meters
ISO-RACK16/P
ISO-DA02/P (PCI-DAS6025 only)
BNC-16SE
BNC-16DI
CIO-MINI50
CIO-TERM100
SCB-50SSR-RACK24 (PCI-DAS6025 only, with DADP-5037)
CIO-ERB24 (PCI-DAS6025 only, with DADP-5037)
CIO-ERB08 (PCI-DAS6025 only, with DADP-5037)
SCB-100

10PCI-DAS6023 and PCI-DAS6025

Specifications

Table 27. 8-channel differential mode pin outPin
1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950Signal Name
LLGND
CH0 IN HI
CH0 IN LO
CH1 IN HI
CH1 IN LO
CH2 IN HI
CH2 IN LO
CH3 IN HI
CH3 IN LO
CH4 IN HI
CH4 IN LO
CH5 IN HI
CH5 IN LO
CH6 IN HI
CH6 IN LO
CH7 IN HI
CH7 IN LO
LLGND
n/cn/cn/cn/cn/cn/cn/cn/cn/cn/cn/cn/cn/cn/cn/cn/cAISENSED/A OUT 0*
D/A GND*
D/A OUT1*PC +5 V
AUXOUT0 / D/A PACER OUT
AUXOUT1 / A/D PACER OUT
AUXOUT2 / SCANCLKAUXIN0 / A/D CONVERTn/c
AUXIN1 / A/D START TRIGGER
AUXIN2 / A/D STOP TRIGGER
AUXIN3 / D/A UPDATEAUXIN4 / D/A START TRIGGER
AUXIN5 / A/D PACER GATE
GND

Pin51525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100* = N/C on PCI-DAS6023

11Signal Name
FIRSTPORTA Bit 0 *FIRSTPORTA Bit 1 *FIRSTPORTA Bit 2 *FIRSTPORTA Bit 3 *FIRSTPORTA Bit 4 *FIRSTPORTA Bit 5 *FIRSTPORTA Bit 6 *FIRSTPORTA Bit 7 *FIRSTPORTB Bit 0 *FIRSTPORTB Bit 1 *FIRSTPORTB Bit 2 *FIRSTPORTB Bit 3 *FIRSTPORTB Bit 4 *FIRSTPORTB Bit 5 *FIRSTPORTB Bit 6 *FIRSTPORTB Bit 7 *FIRSTPORTC Bit 0 *FIRSTPORTC Bit 1 *FIRSTPORTC Bit 2 *FIRSTPORTC Bit 3 *FIRSTPORTC Bit 4 *FIRSTPORTC Bit 5 *FIRSTPORTC Bit 6 *FIRSTPORTC Bit 7 *n/cn/cn/cn/cn/cn/cn/cn/cn/cn/c
DIO0DIO1DIO2DIO3DIO4DIO5DIO6DIO7CTR1 CLK
CTR1 GATE
CTR1 OUTGND
CTR2 CLK
CTR2 GATECTR2 OUT
GND

PCI-DAS6023 and PCI-DAS6025

Specifications

Table 28. 16-channel single-ended mode pin outPin1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950Signal Name
LLGND
CH0 IN
CH8 IN
CH1 IN
CH9 INCH2 IN
CH10 IN
CH3 IN
CH11 IN
CH4 IN
CH12 IN
CH5 IN
CH13 IN
CH6 IN
CH14 IN
CH7 IN
CH15 IN
LLGND
n/cn/cn/cn/cn/cn/cn/cn/cn/cn/cn/cn/cn/cn/cn/cn/cAISENSED/A OUT 0*
D/A GND*
D/A OUT1*
PC +5 V
AUXOUT0 / D/A PACER OUT
AUXOUT1 / A/D PACER OUT
AUXOUT2 / SCANCLKAUXIN0 / A/D CONVERTn/c
AUXIN1 / A/D START TRIGGER
AUXIN2 / A/D STOP TRIGGER
AUXIN3 / D/A UPDATEAUXIN4 / D/A START TRIGGER
AUXIN5 / A/D PACER GATE
GND

Pin
51
52535455565758596061626364656667686970717273747576777879808182838485
86878889909192939495
96
979899100* = N/C on PCI-DAS6023

12Signal Name
FIRSTPORTA Bit 0 *FIRSTPORTA Bit 1 *FIRSTPORTA Bit 2 *FIRSTPORTA Bit 3 *FIRSTPORTA Bit 4 *FIRSTPORTA Bit 5 *FIRSTPORTA Bit 6 *FIRSTPORTA Bit 7 *FIRSTPORTB Bit 0 *FIRSTPORTB Bit 1 *FIRSTPORTB Bit 2 *FIRSTPORTB Bit 3 *FIRSTPORTB Bit 4 *FIRSTPORTB Bit 5 *FIRSTPORTB Bit 6 *FIRSTPORTB Bit 7 *FIRSTPORTC Bit 0 *FIRSTPORTC Bit 1 *FIRSTPORTC Bit 2 *FIRSTPORTC Bit 3 *FIRSTPORTC Bit 4 *FIRSTPORTC Bit 5 *FIRSTPORTC Bit 6 *FIRSTPORTC Bit 7 *n/cn/cn/cn/cn/cn/cn/cn/cn/cn/c
DIO0
DIO1
DIO2
DIO3
DIO4
DIO5
DIO6
DIO7
CTR1 CLK
CTR1 GATE
CTR1 OUTGND
CTR2 CLK
CTR2 GATECTR2 OUT
GND

Measurement Computing Corporation
10 Commerce Way
Suite 1008
Norton, Massachusetts 02766(508) 946-5100
Fax: (508) 946-9500
E-mail: info@mccdaq.com
www.mccdaq.com
PCI-DAS6023-25-spec.doc