LSI Package Board needs…
Mutual Communication
Design Consistency
Shorten Development Time
Enabled byLPB
LPBformat

LPB
LPB

New Standard

Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 2013-2014

2014/3/4

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Agenda and Speakers
EDA - example of design tool–Kazunari Koga

Zuken

EDA – example of modeling/simulations–Toru Watanabe

ANSYS

Summary : Benefits

LPB
LPB

Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 2013-2014

2014/3/4

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LPB Standard Format
Design environment to beconstructed by 6 formats
Conceptual design
N-Format

N-Format

1. Project Manage (M-Format)

Component

2. Netlist (N-Format)

Optimization
Timing
LVS

C-Format
LSI

3. Component (C-Format)

Detailed
design4. Design Rule (R-Format)

ProjectManage

5. Geometry (G-Format)

N-Format

N-Format

PKG

Board

Design Rule
R-Format

Designfeedback

M-Format

G-FormatSI

6. Glossary

Geometry

PIEMI

Post design analysis

LPB
LPB

Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 2013-2014

2014/3/4

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LPB sample files for test bench
Analog Signal(SMA x6)

FKB48

DDR3-1600Mbps

SOC PKG
SSTL15GPIO

DDR

SOCDIESSTL15

DDR

PCIe x4

Xtal
Passive

TOP

Power IC

Gen.2

Component

DetailsSOC

New Design

DDRgeneric parts

FKB48

generic parts

Power IC

generic parts

Xtalgeneric parts

Passivegeneric parts

Edge Finger(Based on LPB Standard Format Ver.2.1)

Golden Sample are provided as a test bench for
implementation.

LPB
LPB

Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 2013-2014

2014/3/4

Page4

Reference flow using LPB standard format
LSI Vendor(Package Design)LSIElectric Products
Maker

Requirement(2) LSI
Outline SPEC.

PKG C2PKG N2(4) PKG PinAssignment

PKG C3(6) PKG
Pre Layout

PKG C5PKGC4PKG C6
PKG G6PKG R6Board Artwork(1) BlockDiagram

ICs CICs N(3) Floor Plan

TOP C3TOP N3(5) Board
Pre Layout

TOP RTOP
N3(7) Pre Layout
CheckTOP
C7Discrete C
Discrete N

TOP C5TOP G5ICs
DDR, PowerIC,etc.
PWB Substrate

Passive,Socket,
Connector

TOP N7(8) PKG
Final Layout(9) BoardFinal Layout

PKG C8PKG G8LPB
LPB

Substrate/Component
Vendors(10) Final
Layout Check

Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 2013-2014

TOP C9TOP G9To understand the functionof the LPB standard format
2014/3/4

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Reference Flow
Demonstration

LPB
LPB

Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 2013-2014

2014/3/4

Page6

Reference flow using LPB standard format
LSI Vendor(Package Design)LSIElectric Products
Maker

Requirement(2) LSI
Outline SPEC.

PKG C2PKG N2(4) PKG PinAssignment

PKG C3(6) PKG
Pre Layout

PKG C5PKGC4PKG C6PKG G6PKG R6

Board Artwork(1) Block
Diagram

ICs CICs N(3) Floor Plan

TOP C3TOP N3(5) Board
Pre Layout

TOP RTOPN3(7) Pre Layout
CheckTOP
C7Discrete C
Discrete N

TOP C5TOP G5ICs
DDR, PowerIC,etc.
PWB Substrate

Passive,Socket,Connector

TOP N7(8) PKG
Final Layout(9) BoardFinal Layout

PKG C8PKG G8LPB
LPB

Substrate/
Component
Vendors(10) Final
Layout Check

Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 2013-2014

TOP C9TOP G92014/3/4

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(5) Board

Pre Layout

LPB
formatFloorplan Result.
Tentative pin assignment isdone.

Optimize
Placement

LPB
formatCritical PathRouting

LPB
LPB

Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 2013-2014

Add the change of floorplan
and pin assignment.
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(5) BoardPre Layout

Change placement
info.

<placement y="-8223.2" x="30206.5" mount="TOP" angle="270" z="200" inst="DDR0"
ref_module="DDR"/> <placement y="15911.7" x="36947.6" mount="TOP" angle="270" z="200"TOPinst="DDR1" ref_module="DDR"/><placement y="-6500" x="400" mount="TOP" angle="0" z="200" inst="SOC"
C3
ref_module="SOC_PKG"/><placement y="22417.2" x="-8150.9" mount="TOP" z="20" inst="GRM1_C1" ref_module="GRM1"/><placement y="23603.4" x="-4479.3" mount="TOP" z="20" inst="GRM1_C2" ref_module="GRM1"/><placement y="-3223.2" x="37206.5" mount="TOP" angle=“90" z="200" inst="DDR0"TOP
ref_module="DDR"/> <placement y="10911.7 " x="30947.6" mount="TOP" angle=“90" z="200"
inst="DDR1" ref_module="DDR"/>
C5<placement y="-6500" x="400" mount="TOP" angle=“45" z="200" inst="SOC"
ref_module="SOC_PKG"/><placement y="22417.2" x="-8150.9" mount=“BOTTOM" z="20" inst="GRM1_C1"
ref_module="GRM1"/><placement y="23603.4"
x="-4479.3" mount=" BOTTOM " z="20" inst="GRM1_C2"
Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 2013-2014
2014/3/4
Page9
ref_module="GRM1"/>

LPBLPB(5) Board

Pre Layout

Swap pin<port id="R24" type="signal" y="-1500" x="10500" name="DDRDQ[0]" direction="inout"/><port id="R25" type="signal" y="-1500" x="11500" name="DDRDQ[1]" direction="inout"/><port id="R26" type="signal" y="-1500" x="12500" name="DDRDQ[2]" direction="inout"/><port id="P24" type="signal" y=“ -500" x="10500" name="DDRDQ[3]" direction="inout"/><port id="P25" type="signal" y=“ -500" x="11500" name="DDRDQ[4]" direction="inout"/><port id="P26" type="signal" y=“ -500" x="12500" name="DDRDQ[5]" direction="inout"/>

PKG C4<port id="R24" type="signal" y="-1500" x="10500" name="DDRDQ[7]" direction="inout"/><port id="R25" type="signal" y="-1500" x="11500" name="DDRDQ[0]" direction="inout"/> PKG<port id="R26" type="signal" y="-1500" x="12500" name="DDRDQ[2]" direction="inout"/><port id=“P24” type=“signal” y=“ -500" x="10500" name="DDRDQ[6]" direction="inout"/><port id=“P25” type=“signal” y=“ -500" x="11500" name="DDRDQ[3]" direction="inout"/><port id=“P26” type=“signal” y=“ -500" x="12500" name="DDRDQ[4]" direction="inout"/>

LPB
LPBCopyright© JEITA EDA-TC LPB-WG All Rights Reserved 2013-2014

2014/3/4

C5Page10

Simulation Setup
Input for Simulation ：Layout Tools :Zuken Design Force CadenceAPD etc…
 Board, Package Geometry
 Traces, Vias, Pads

G-Format Planes, Polygons
 etc…

Package
Designed by APD
BoardDesigned by Design Force

Extraction Tools :ANSYS
 etc…
LPB
LPB

ANSYS SIwave, ANSYS HFSS

Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 2013-2014

2014/3/4

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Simulation Setup
Input for Simulation ：Layout Tools :Zuken Design Force CadenceAPD etc…
Capacitor(C, ESL, ESR) Passive Components
 C, L, R

Inductor (L)C-Format Constraints
 Skew, Frequency, etc…

Resistor (R)Extraction Tools :ANSYS
 etc…
LPB
LPB

ANSYS SIwave, ANSYS HFSS

Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 2013-2014

2014/3/4Page12

(7) Pre Layout Check
LSI Vendor(Package Design)LSIElectric Products
Maker

Requirement(2) LSIOutline SPEC.

PKG C2PKG N2(4) PKG PinAssignment

PKG C3(6) PKG
Pre Layout

PKG C5PKGC4PKG C6PKG G6PKG R6

Board Artwork(1) Block
Diagram

ICs C
ICs N
(3) Floor Plan

TOP C3TOP N3(5) Board
Pre Layout

TOP RTOP
N3(7) Pre Layout
CheckTOP
C7Discrete CDiscrete NTOP C5TOP G5ICs
DDR, PowerIC,etc.
PWB Substrate

Passive,Socket,Connector

TOP N7(8) PKG
Final Layout(9) BoardFinal Layout

PKG C8PKG G8LPB
LPB

Substrate/Component
Vendors(10) Final
Layout Check

Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 2013-2014

TOP C9TOP G92014/3/4

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(7) Pre Layout Check
Works :(7) Pre Layout Check● 【Signal Integrity Simulation of Critical Nets】● Timing Verification of DDRIII 1.3GBps Write Cycle• Is Damping Resistors required?
• What is the best ODT setting?
• Estimate the worst skew of DQ

LPBLPBCopyright© JEITA EDA-TC LPB-WG All Rights Reserved 2013-2014

2014/3/4

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(7) Pre Layout Check
Geometry :【Board】【Package】

G-Format

G-Format• Designed by Cadence APD• All nets are completely routed• DQs are NOT isometric• Designed by Zuken Design Force• Only 1.5V Power, Ground, DQS and DQ• DQS and DQs are isometric

ANSYS SIwave
Merged and stacked in Extraction Tool

LPB
LPB

Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 2013-2014

2014/3/4

Page15

(7) Pre Layout CheckOverview of Simulation :【Controller IC 】
• IC : IBIS Model• Input 666MHz Cycle PRBS to DQ0-7【DDRIII】• IC：IBIS Model• ODT：Test for 30, 40, 60 and 120Ω
DQS, DQ signals in Package and Board Layout / ANSYS SIwave (Extraction Tool)

LPB
LPB

Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 2013-2014

2014/3/4

Page16

(7) Pre Layout Check
Simulation Result :Eye Diagram (ODT：30Ω (FAIL))
DQSTransient Waveform of DQS and DQ0～7

DQ0

Eye Diagram (ODT：60Ω (Best Case))
DQS
DQ0【Worst Skew (Case of ODT=60Ω) 】• 42.8ps (DQ5-DQ6)
Eye Diagram and Transient Waveform / ANSYS DesignerSI (Circuit Simulator)

LPB
LPB

Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 2013-2014

2014/3/4

Page17

(9) Board
Import the result of pre layout
check• Skew• Decap

Final Layout
LPBformat

Re design tosatisfy theconstraints.
• Change pin
assignment• Change decap
Route other signal
Designpower/ground

LPB
LPB

Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 2013-2014

2014/3/4

Page18

(10) Final Layout Check
LSI Vendor(Package Design)LSIElectric Products
Maker

Requirement(2) LSIOutline SPEC.

PKG C2PKG N2(4) PKG PinAssignment

PKG C3(6) PKG
Pre Layout

PKG C5PKGC4PKG C6PKG G6PKG R6Board Artwork(1) Block
Diagram

ICs C
ICs N
(3) Floor Plan

TOP C3TOP N3(5) Board
Pre Layout

TOP RTOP
N3(7) Pre Layout
CheckTOP
C7Discrete C
Discrete N

TOP C5TOP G5ICs
DDR, PowerIC,etc.
PWB Substrate

Passive,Socket,
Connector

TOP N7(8) PKG
Final Layout(9) Board
Final Layout

PKG C8PKG G8LPB
LPB

Substrate/Component
Vendors(10) Final
Layout CheckCopyright© JEITA EDA-TC LPB-WG All Rights Reserved 2013-2014

TOP C9TOP G9

2014/3/4Page19

(10) Final Layout Check
Works :(10) Final Layout Check● 【Power Integrity Simulation of PDN】
● Input Impedance Analysis of Controller IC and Bypass CapsOptimization• Chip-Package-System Total Impedance• Bypass Caps Optimization● 【EMI (Far/Near Field) Simulation】● Far/Near Field analysis induced by Power Noise• CISPR 22 Test (Far Field)

LPBLPB• Checks Near Field
Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 2013-2014

2014/3/4Page20

(10) Final Layout Check
Overview of Simulation :Transient Waveform of 1.5V Power (V vs. T)【Controller IC 】
• IC：CPM (Chip Power Model / Apache RedHawk)• Place Port between 1.5V Power and Ground【Regulator】• DC 1.5V Power Supply【Bypass Capacitors 】• 16 Caps for 1.5V Power
Package and Board Layout / ANSYS SIwave (Extraction Tool)

LPB
LPB

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2014/3/4

Page21

(10) Final Layout Check
Overview of Simulation :【Bypass Capacitors (Placement) 】• 16 Caps are placed between 1.5V Power and Groundnearby Controller and DDRIII

Bypass Caps Placement (Bottom Layer) / ANSYS SIwave (Extraction Tool)

LPB
LPB

Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 2013-2014

2014/3/4

Page22

(10) Final Layout Check
Simulation Result :Package and Board (G9, C9)Chip, Package and Board (G9, C9 + CPM)
Chip, Package and Board after Optimization (G9, C10 + CPM)

Input Impedance of 1.5V Power on Controller IC / ANSYS SIwave (Extraction Tool)

LPB
LPB

Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 2013-20142014/3/4

Page23

(10) Final Layout Check
Simulation Result :NOT Required!

C-Format
Re-written to optimized list

Board Artwork
Bypass Caps Placement (Bottom Layer) / ANSYS SIwave (Extraction Tool)

LPB
LPB

Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 2013-2014

2014/3/4

Page24

(10) Final Layout Check

Max. E at 3m

Simulation Result :H-field 1mm above (100MHz)

H-field 1mm above (420MHz)CISPR 22 - Class A
CISPR 22 - Class B

Far Field and Near Field / ANSYS SIwave (Extraction Tool)

LPB
LPB

Copyright© JEITA EDA-TC LPB-WG All Rights Reserved 2013-2014

2014/3/4

Page25

(10) Final Layout CheckWorks :(10) Final Layout Check● 【Power Integrity Simulation of PDN】
● Input Impedance Analysis of Controller IC and Bypass CapsOptimization• Chip-Package-System Total Impedance ⇒ OK
• Bypass Caps Optimization ⇒ Optimized● 【EMI (Far/Near Field) Simulation】● Far/Near Field analysis induced by Power Noise• CISPR 22 Test (Far Field) ⇒ OK

LPBLPB• Checks Near Field ⇒ OKCopyright© JEITA EDA-TC LPB-WG All Rights Reserved 2013-2014

2014/3/4

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Benefit of LPB format• Quick & Accurate design/simulation setup
 Enable EMC check from development early stage
 No more e-mail/phone call/meetings
 Avoid human error; eliminate hand edit, versioncontrol• Feedback can be done from any parties,and instantly.
 For optimization/cost down/quality up feed back

• Easy implementation• Human readable, open format XML/Verilog-HDL• XML parser available.
• Simple / light geometry format (G-format:XFL)LPB
LPBCopyright© JEITA EDA-TC LPB-WG All Rights Reserved 2013-2014

2014/3/4

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