REVISIONSLTR

DESCRIPTIONDATE (YR-MO-DA)APPROVEDA

Update boilerplate paragraphs to current VID description requirements.
- PHN

22-03-22

Muhammad A. Akbar

CURRENT DESIGN ACTIVITY CAGE CODE 16236
HAS CHANGED NAMES TO:
DLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
Prepared in accordance with ASME Y14.24

Vendor Item Drawing

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PMIC N/A
Original date of drawing
YY MM DD

DEFENSE SUPPLY CENTER, COLUMBUS

PREPARED BY
Phu H. Nguyen
Phu H. Nguyen
APPROVED BY

14-12-22

COLUMBUS, OHIO 43218-3990
TITLE

CHECKED BYMICROCIRCUIT, DIGITAL, MIXED SIGNALMICRCONTROLLER, MONOLITHIC SILICON

Thomas M. HessSIZE

ACAGE CODE

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16236

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PAGE

V62/14608
1 OF 38AMSC N/A
DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.

5962-V027-22

1. SCOPE

1.1 Scope. This drawing documents the general requirements of a high performance mixed signal microcontroller
microcircuit, with an operating temperature range of -40ºC to +105ºC for device type 01 and -55ºC to +125ºC for device
type 02.
1.2 Vendor Item Drawing Administrative Control Number. The manufacturer’s PIN is the item of identification. The
vendor item drawing establishes an administrative control number for identifying the item on the engineering
documentation:
V62/14608-

Drawing
number01

X

E

Device type(see 1.2.1)

Case outline(see 1.2.2)

Lead finish(see 1.2.3)

1.2.1 Device type(s).
Device type

Generic

01
02

MSP430F5438-EP
MSP430F5438-EP

Circuit function-40°C to 105°C-55°C to 125°C

Mixed signal microcontroller
Mixed signal microcontroller

1.2.2 Case outline(s). The case outlines are as specified herein.
Outline letter

Number of pins

JEDEC PUB 95

Package style

X
Y

113
100

JEDEC MO-225
JEDEC MS-026

Plastic Ball Grid Array
Plastic Quad Flatpack

1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer:
Finish designator

Material

A
B
C
D
E
F
Z

DLA LAND AND MARITIMECOLUMBUS, OHIO

Hot solder dip
Tin-lead plate
Gold plate
PalladiumGold flash palladium
Tin-lead alloy
Other

SIZE
A

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1.3 Absolute maximum ratings.

1/

Voltage applied at VCC to VSS .......................................................................................................... -0.3 V to 4.1 V
Voltage apply to any pin (excluding VCORE) ................................................................................. -0.3 V to VCC + 0.3 V 2/
Diode current at any device pin ....................................................................................................... ±2 mA
Storage temperature, Tstg ................................................................................................................ -55°C to 150°C
3/
Maximum junction temperature, TJ................................................................................................... 95°C
1.4 Thermal characteristics.

Thermal metric

4/

Junction to ambient thermal resistance, θJA 5/
Junction to case (top) thermal resistance, θJCtop 6/
Junction to board thermal resistance, θJB 7/
Junction to top characterization parameter, ΨJT 8/
Junction to board characterization parameter, ΨJB 9/
Junction to case (bottom) thermal resistance, θJCbot 10/

Case outline
X
43.6
16.6
17.8
0.3
15.1
N/A

Case outline
Y
49
9.3
25
0.2
24.7
N/A

Units
°C/W

1/

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stressratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended
operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device
reliability.
2/ All voltage referenced to VSS. VCORE is for internal device usage only. No external DC loading or voltage should be applied.
3/ Higher temperature may be applied during board soldering according to the current JEDEC J-STD 020 specification with peak
reflow temperatures not higher than classified on the device label on the shipping boxes or reels.
4/ For more information about traditional and new thermal metrics, see manufacturer data.
5/ The junction to ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-Kboard, as specified in JESD51-7, in an environment described in JESD51-2a.
6/ The junction to case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specified JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
7/ The junction to board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the
PCB temperature, as described in JESD51-8.
8/ The junction to top characterization parameter, ΨJT, estimates the junction temperature of a device in a real system and is
extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
9/ The junction to board characterization parameter, ΨJB, estimates the junction temperature of a device in a real system and is
extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
10/ The junction to case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No
specified JEDEC- standard test exists, but a close description can be found in the ANSI SEMI standard G30-88

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1.5 Recommended operating conditions.

11/

Supply voltage during program execution and flash programming(AVCC = DVCC1/2/3/4= DVCC): ....................................................................................................... 1.8 V to 3.6 V
12/ 13/
Supply voltage (AVSS = DVSS1/2/3/4 =DVSS) ....................................................................................... 0 V
Operating free air temperature (TA):Device type 01 ......................................................................................................................... -40°C to 125°C
Device type 02 ......................................................................................................................... -55°C to 125°C
Operating junction temperature (TJ):
Device type 01 ......................................................................................................................... -40°C to 125°C
Device type 02 ......................................................................................................................... -55°C to 125°C
Recommended capacitor at VCORE (CVCORE) ................................................................................ 470 Typical nF
Capacitor ratio of DVCC to VCORE (CDVCC/CVCORE) ....................................................................... 10
Processor frequency (maximum MCLK frequency) 14/ 15/ (See Figure 4)
PMMCOREVx = 0, 1.8 V ≤ VCC ≤ 3.6 V, (default condition) .................................................... 0 MHz to 8.0 MHz
PMMCOREVx = 1, 2.0 V ≤ VCC ≤ 3.6 V ................................................................................... 0 MHz to 12.0 MHz
PMMCOREVx = 1, 2.2 V ≤ VCC ≤ 3.6 V ................................................................................... 0 MHz to 20.0 MHz
PMMCOREVx = 1, 2.4 V ≤ VCC ≤ 3.6 V ................................................................................... 0 MHz to 25.0 MHz

2. APPLICABLE DOCUMENTSJEDEC – SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC)JEP95
JESD51JESD51-2a
JESD51-7
JESD51-8
J-STD-020

–
–
–
–
–
–

Registered and Standard Outlines for Semiconductor Devices
Methodology for the Thermal Measurement of Component Packages (Single Semiconductor Device).
Integrated Circuits Thermal Test Method Environment Conditions – Natural Convection (Still Air)High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
Integrated Circuits Thermal Test Method Environment Conditions – Junction-to-board
Joint IPC/JEDEC standard for moisture/reflow sensitivity classification for nonhermetic solid state
surface mount devices.

(Copies of these documents are available online at https://www.jedec.org ).
AMERICAN NATIONAL STANDARDS INSTITUTE (ANSI) STANDARD
ANSI SEMI STANDARD G30-88– Test Method for Junction-to-Case Thermal Resistance Measurements for Ceramic
Packages(Copies of these documents are available online at https:/www.ansi.org.

__
4/
5/
6/
7/
8/

Typical values are specified at VCC = 3.3 V and TA = 25°C (unless otherwise noted).
It is recommended to power AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can
be tolerated during power up and operation.
The minimum supply voltage is defined by the supervisor SVS levels when it is enabled. See the PMM, SVS High Side thresholdparameters for the exact values and further details.
The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse duration of thespecified maximum frequency.
Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.

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3. REQUIREMENTS
3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3
herein and as follows:
A. Manufacturer’s name, CAGE code, or logo
B. Pin 1 identifier
C. ESDS identification (optional)
3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (ifapplicable) above.
3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance
characteristics are as specified in 1.3, 1.4, and table I herein.
3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified
herein.
3.5 Diagrams.
3.5.1

Case outline. The case outline shall be as shown in 1.2.2 and figure 1.

3.5.2

Terminal connections. The terminal connections shall be as shown in figure 2.

3.5.3

Functional block diagram. The functional block diagram shall be as shown in figure 3.

3.5.4

Frequency vs Supply Voltage. The Frequency vs Supply Voltage shall be as shown in figure 4.

3.5.5

SPI master mode, CKPH = 0. The SPI master mode, CKPH = 0 shall be as shown in figure 5.

3.5.6

SPI master mode, CKPH = 1. The SPI master mode, CKPH = 1 shall be as shown in figure 6.

3.5.7

SPI slave mode, CKPH = 0. The SPI slave mode, CKPH = 0 shall be as shown in figure 7.

3.5.8

SPI slave mode, CKPH = 1. The SPI slave mode, CKPH = 1 shall be as shown in figure 8.

3.5.9

I2C mode timing. The I2C mode timing shall be as shown in figure 9.

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PAGE 5TABLE I. Electrical performance characteristics. 1/
Test

Symbol-55 °C

Condition
VCC

2/

PMMCOREV Typ

Low Power Mode Supply Current (into VCC) Excluding External Current-40 °CMax

25 °C

125 °CTyp Max

Typ

Max Typ

Max

3/ 4/

Low power mode 0

ILPM0,

2.2 V

0

69

93

69

93

69

93

85

150

6/ 7/

1MHz

3V

3

73

100

73

100

73

100

90

150

Low power mode 2

ILPM2

2.2 V

0

11

15.5

11

15.5

11

15.5 12.5

30

3V

3

11.7

17.5

11.7 17.5 11.7

17.5 12.5

34

0

1.4

1.4

1.7

8.5

1

1.5

1.5

1.8

9.9

7/

8/

2.2 V
Low power mode 3,
crystal mode
9/

ILPM3,

2

1.5

1.5

2.0

XT1LF

0

1.8

1.8

2.1

1

1.8

1.8

2.3

2

1.9

1.9

2.4

3

2.0

2.0

2.3

2.6

11.8

34

0

1.0

1.0

1.2

1.42

7.5

32

1

1.0

1.0

1.3

7/

3V

Low power mode 3,
VLO mode7/

ILPM3,
10/

Low power mode 4
7/

VLO

ILPM4

3V

11/

Low power mode 4.5 12/

Test

3V

Execution
MemoryILPM4.5

2/

VCC

PMMCOREV

IAM, RAM

Flash

RAM

3V

3V

0
1
2
3
0
1
2
3

21

10.5
10.6

8

1.1

1.1

1.4

1.2

1.2

1.4

1.62

8.5

32

0

1.1

1.1

1.2

1.35

7.5

30

8.5

1

1.2

1.2

1.2

8

2

1.3

1.3

1.3

8.5

3

1.3

1.3

1.3

1.52

0.10

0.10

0.10

0.16 0.75

Frequency(fDCO =

fMCLK =

1 MHz

8 MHz

12 MHz20 MHzTyp Max

Typ

Typ

Active Mode Supply Current into VCC Excluding External Current
IAM, Flash

7.1

2

Condition

Max

8.5
32

fSMCLK)

Unit

25 MHzMax Typ Max TypMax

3/ 4/ 5/0.29 0.45
0.32
0.33
0.35
0.17 0.30
0.18
0.19
0.20

2.08
2.08
2.24
2.36
0.90
1.00
1.13
1.20

2.30

mA
3.10
3.50
3.70

6.37
6.75

8.90

14

1.10

mA
1.47
1.68
1.78

2.82
3.00

4.50

8

See footnotes at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
A

µA

10.1
2.4

3

3V

Unit

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PAGE 6

TABLE I. Electrical performance characteristics - Continued. 1/
Test

SymbolConditions

Limits

VCC

2/
Schmitt-Trigger Inputs – General Purpose I/O
Positive going input threshold voltage

VIT+

Negative going input thresholdvoltage
Input voltage hysteresis (VIT+ - VIT-)

VIT+
Vhys

Pullup/Pulldown resistor

RPull

Input capacitance
Inputs – Ports P1 and P2

CI
15/

External interrupt timing

16/t(int)

Min

Unit

Typ

Max

35

1.45
2.15
1.05
1.7
0.9
1.05
51

13/
1.8 V
3V
1.8 V
3V
1.8 V
3V

0.75
1.45
0.40
0.70
0.25
0.35
21

For pullup: VIN = VSS
For pulldown: VIN = VCC
VIN = VSS or VCC
Port P1, P2: P1.x toP2.x, External trigger
pulse width to set
interrupt flag

2.2 V,
3V17/

1.8 V,
3V

V

kΩ

5

pF

20

ns

Leakage Current – General Purpose I/O
High-impedance leakage current

Ilkg(Px.x)

18/

±50

nA

VCC
VCC
VCC
VCC
VSS + 0.35
VSS + 0.70
VSS + 0.35
VSS + 0.70

V

Outputs – General Purpose I/O (Full Drive Strength)High level output voltage

Low level output voltage

VOH

VOL

I(OHmax) = –3 mA 19/
I(OHmax) = –10 mA 20/
I(OHmax) = –5 mA 19/
I(OHmax) = –15 mA 20/
I(OLmax) = 3 mA 19/
I(OLmax) = 10 mA 20/
I(OLmax) = 5 mA 19/
I(OLmax) = 15 mA 20/

1.8 V

VCC - 0.35
VCC - 0.70
VCC - 0.35
VCC - 0.70
VSS
VSS
VSS
VSS

3V
1.8 V
3V

See footnotes at end of table.
v6214608a

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TABLE I. Electrical performance characteristics - Continued. 1/
Test

SymbolConditions

Limits

VCC

2/
Outputs – General Purpose I/O (Reduced Drive Strength)High level output voltage

Low level output voltage

VOH

VOL

Min

Typ

Unit
Max

21/

I(OHmax) = –1 mA 19/
I(OHmax) = –3 mA 20/
I(OHmax) = –2 mA 19/
I(OHmax) = –6 mA 20/
I(OLmax) = 1 mA 19/
I(OLmax) = 3 mA 20/
I(OLmax) = 2 mA 19/
I(OLmax) = 6 mA 20/

1.8 V
3V
1.8 V
3V

VCC - 0.35
VCC - 0.70
VCC - 0.35
VCC - 0.70
VSS
VSS
VSS
VSS

VCC
VCC
VCC
VCC
VSS + 0.35
VSS + 0.70
VSS + 0.35
VSS + 0.70

V

16

MHz

Output Frequency – General Purpose I/O
Port output frequency(with load)

fPx.y

Clock output frequency

fPort_CLK

P1.6/SMCLK
22/ 23/
P1.0/TA0CLK/ACLK
P1.6/SMCLK
P2.0/TA1CLK/MCLK
CL = 20 pF 23/

VCC = 1.8 V,
PMMCOREVx = 0
VCC = 3 V,
PMMCOREVx = 3
VCC = 1.8 V,
PMMCOREVx = 0
VCC = 3 V,
PMMCOREVx = 3

25
16
25

See footnotes at end of table.

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PAGE 8TABLE I. Electrical performance characteristics - Continued. 1/
Test

SymbolConditions
2/

Crystal Oscillator, XT1, Low-Frequency Mode

Differential XT1 oscillator crystal
current consumption from lowest
drive setting, LF mode

XT1 oscillator crystal frequency,
LF modeXT1 oscillator logic-level squarewave input frequency, LF mode

Oscillation allowance for LF
crystals
27/

fXT1,LF0
fXT1,LF,SW

XTS = 0, XT1BYPASS = 1

OALF

Integrated effective load
capacitance, LF mode

CL,eff28/

Duty cycle, LF mode
Oscillator fault frequency, LF
mode
30/

Min

fFault,LF

tSTAR,LF
Startup time, LF mode

Typ

Unit
Max

24/
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 1,
TA = 25°C
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 2,
TA = 25°C
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 3,
TA = 25°C
XTS = 0, XT1BYPASS = 0

ΔIDVCC.LF

Limits

VCC

3V

0.075

µA

0.170

0.290

32768

25/ 26/

10

XTS = 0,XT1BYPASS = 0, XT1DRIVEx = 0,
fXT1,LF = 32768 Hz, CL,eff = 6 pF
XTS = 0,XT1BYPASS = 0, XT1DRIVEx = 1,
fXT1,LF = 32768 Hz, CL,eff = 12 pF
XTS = 0, XCAPx = 0 29/
XTS = 0, XCAPx = 1
XTS = 0, XCAPx = 2
XTS = 0, XCAPx = 3
XTS = 0, Measured at ACLK,
fXT1,LF = 32768 Hz
XTS = 0
31/

32768

Hz
50

210

kΩ

300

2
5.5
8.5
12.0

fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 0,
TA = 25°C, CL,eff = 6 pF
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 1,
TA = 25°C, CL,eff = 12 pF

3V

pF

30

70

%

10

10000

Hz

1000

500

See footnotes at end of table.

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TABLE I. Electrical performance characteristics - Continued. 1/

Test

SymbolConditions
2/

Crystal Oscillator, XT1, High Frequency Mode

XT1 oscillator crystal current, HF mode

XT1 oscillator crystal frequency,
HF mode 0
XT1 oscillator crystal frequency,
HF mode 1
XT1 oscillator crystal frequency,
HF mode 2
XT1 oscillator crystal frequency,
HF mode 3
XT1 oscillator logic-level square-wave
input frequency, HF mode, bypass mode

Oscillation allowance for HF crystals
33/

Min

Typ

Unit
Max

24/

IDVCC.HF

fXT1,HF0
fXT1,HF1
fXT1,HF2
fXT1,HF3
fXT1,HF,SW

OAHF

Limits

VCC

fOSC = 4 MHz, XTS = 1,
XOSCOFF = 0, XT1BYPASS = 0,
XT1DRIVEx = 0, TA = 25°C
fOSC = 12 MHz, XTS = 1,
XOSCOFF = 0, XT1BYPASS = 0,
XT1DRIVEx = 1, TA = 25°C
fOSC = 20 MHz, XTS = 1,
XOSCOFF = 0, XT1BYPASS = 0,
XT1DRIVEx = 2, TA = 25°C
fOSC = 32 MHz, XTS = 1,
XOSCOFF = 0, XT1BYPASS = 0,
XT1DRIVEx = 3, TA = 25°C
XTS = 1,XT1BYPASS = 0, XT1DRIVEx = 0 32/
XTS = 1,XT1BYPASS = 0, XT1DRIVEx = 1 32/
XTS = 1,XT1BYPASS = 0, XT1DRIVEx = 2 32/
XTS = 1,XT1BYPASS = 0, XT1DRIVEx = 3 32/
XTS = 1,XT1BYPASS = 1 32/
25/
XTS = 1,XT1BYPASS = 0, XT1DRIVEx = 0,
fXT1,HF = 6 MHz, CL,eff = 15 pF
XTS = 1,XT1BYPASS = 0, XT1DRIVEx = 1,
fXT1,HF = 12 MHz, CL,eff = 15 pF
XTS = 1,XT1BYPASS = 0, XT1DRIVEx = 2,
fXT1,HF = 20 MHz, CL,eff = 15 pF
XTS = 1,XT1BYPASS = 0, XT1DRIVEx = 3,
fXT1,HF = 32 MHz, CL,eff = 15 pF

3V

200

µA

260

325

450

4

8

8

16

16

24

24

32

0.7

32
450

320

200

200

See footnotes at end of table.

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MHz

MHz
Ω

TABLE I. Electrical performance characteristics - Continued. 1/
Test

SymbolConditions
2/

Crystal Oscillator, XT1, High Frequency Mode - Continued

Startup time, HF mode

Integrated effective load capacitance, HF
mode
28/ 34/tSTART,HF

CL,effDuty cycle, HF mode
Oscillator fault frequency, HF mode 30/

fFault,HF

Limits

VCC
Min

Typ

Unit
Max

24/

fOSC = 6 MHz, XTS = 1,
XT1BYPASS = 0, XT1DRIVEx = 0,
TA = 25°C, CL,eff = 15 pF

3V

0.5

fOSC = 20 MHz, XTS = 1,
XT1BYPASS = 0, XT1DRIVEx = 2,
TA = 25°C, CL,eff = 15 pF

0.3

XTS = 1

1

XTS = 1
Measured at ACLK, fXT1,HF2 = 20 MHz

40

XTS = 1

30

31/

50

ms

pF
60

%

300

kHz

See footnotes at end of table.

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PAGE 11TABLE I. Electrical performance characteristics - Continued. 1/
Test

SymbolConditions
2/

Crystal Oscillator, XT2

35/

Limits

VCC
Min

Typ

Unit
Max

36/

XT2 oscillator crystal current
consumption

XT2 oscillator crystal frequency, mode 0
XT2 oscillator crystal frequency, mode 1
XT2 oscillator crystal frequency, mode 2
XT2 oscillator crystal frequency, mode 3
XT2 oscillator logic-level square wave
input frequency, bypass mode

Oscillation allowance for HF crystals
33/

Startup time

Integrated effective load capacitance, HF
mode
35/ 38/Duty cycle, HF mode
Oscillator fault frequency 30/

IDVCC.XT2

fXT2,HF0
fXT2,HF0
fXT2,HF0
fXT2,HF0

fXT2,HF,SW

OAHF

tSTART,HF

fOSC = 4 MHz, XT2OFF = 0,
XT2BYPASS = 0, XT2DRIVEx = 0,
TA = 25°C
fOSC = 12 MHz, XT2OFF = 0,
XT2BYPASS = 0, XT2DRIVEx = 1,
TA = 25°C
fOSC = 20 MHz, XT2OFF = 0,
XT2BYPASS = 0, XT2DRIVEx = 2,
TA = 25°C
fOSC = 32 MHz, XT2OFF = 0,
XT2BYPASS = 0, XT2DRIVEx = 3,
TA = 25°C
XT2DRIVEx = 0, XT2BYPASS = 0 32/
XT2DRIVEx = 1, XT2BYPASS = 0 32/
XT2DRIVEx = 2, XT2BYPASS = 0 32/
XT2DRIVEx = 3, XT2BYPASS = 0 32/
XT2BYPASS = 1 32/
37/
XT2DRIVEx = 0, XT2BYPASS = 0,
fXT2,HF0 = 6 MHz, CL,eff = 15 p
XT2DRIVEx = 0, XT2BYPASS = 0,
fXT2,HF0 = 12 MHz, CL,eff = 15 p
XT2DRIVEx = 0, XT2BYPASS = 0,
fXT2,HF0 = 20 MHz, CL,eff = 15 p
XT2DRIVEx = 0, XT2BYPASS = 0,
fXT2,HF0 = 32 MHz, CL,eff = 15 p
fOSC = 6 MHz,XT2BYPASS = 0, XT2DRIVEx = 0,
TA = 25°C, CL,eff = 15 pF
fOSC = 20 MHz,XT2BYPASS = 0, XT2DRIVEx = 2,
TA = 25°C, CL,eff = 15 pF

3V

200

260

325

450

4
8
16
24
0.7

8
16
24
32
32
450

200
200
3V

0.5

ms

0.3

40
30

50

pF
60
300

See footnotes at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
16236
REV

A

MHz
Ω

1
Measured at ACLK, fXT2,HF2 = 20 MHz
XT2BYPASS = 1
39/

MHz

320

CL,eff

fFault,HFµA

DWG NO.
V62/14608
PAGE 12%kHzTABLE I. Electrical performance characteristics - Continued. 1/
Test

SymbolConditions

Limits

VCC

2/

Unit

Min

Typ

Max

5

9.4

14

Internal Very-Low-Power Low-Frequency Oscillator (VLO)
VLO frequency

fVLO

Measured at ACLKVLO frequency temperature drift

dfVLO/dT

Measured at ACLK

40/

1.8 V to 3.6 V

0.5

%/°C

VLO frequency supply voltage drift

dfVLO/dVCC

Measured at ACLK

41/

1.8 V to 3.6 V

4%/V

Duty cycle

1.8 V to 3.6 V

Measured at ACLK

1.8 V to 3.6 V

40

50

60

kHz

%

Internal Reference, Low-Frequency Oscillator (REFO)REFO oscillator current
consumption

IREFO

REFO frequency calibrated
REFO absolute tolerance calibrated

fREFO

TA = 25°C

1.8 V to 3.6 V

3µA

Measured at ACLK

1.8 V to 3.6 V

32768

Hz

Full temperature range

1.8 V to 3.6 V

±3.5

%

3V

±1.5

%

TA = 25°C
REFO frequency temperature drift

dfREFO/dT

Measured at ACLK

40/

1.8 V to 3.6 V

0.01

%/°C

REFO frequency supply voltage drift

dfREFO/dVCC

Measured at ACLK

41/

1.8 V to 3.6 V

1.0

%/V

Duty cycle
REFO startup time

tSTART

Measured at ACLK

1.8 V to 3.6 V

40%/60% duty cycle

1.8 V to 3.6 V

40

50

60

25

See footnotes at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
16236
REV

A

DWG NO.
V62/14608
PAGE 13%µs

TABLE I. Electrical performance characteristics - Continued. 1/
Test

SymbolLimitsConditions
2/

Min

Typ

Unit
Max

DCO frequency
DCO frequency (0, 0) 42/
DCO frequency (0, 31) 42/
DCO frequency (1, 0) 42/
DCO frequency (1, 31) 42/
DCO frequency (2, 0) 42/
DCO frequency (2, 31) 42/
DCO frequency (3, 0) 42/
DCO frequency (3, 31) 42/
DCO frequency (4, 0) 42/
DCO frequency (4, 31) 42/
DCO frequency (5, 0) 42/
DCO frequency (5, 31) 42/
DCO frequency (6, 0) 42/
DCO frequency (6, 31) 42/
DCO frequency (7, 0) 42/
DCO frequency (7, 31) 42/
Frequency step between range
DCORSEL and DCORSEL + 1
Frequency step between tap
DCO and DCO + 1
Duty cycle
DCO frequency temperature
drift
40/
DCO frequency voltage drift
41/

fDCO(0,0)fDCO(0,31)
fDCO(0,0)fDCO(0,31)
fDCO(0,0)fDCO(0,31)
fDCO(0,0)fDCO(0,31)
fDCO(0,0)fDCO(0,31)
fDCO(0,0)fDCO(0,31)
fDCO(0,0)fDCO(0,31)
fDCO(0,0)fDCO(0,31)
fCORSELSDCO

DCORSELx = 0, DCOx = 0, MODx = 0
DCORSELx = 0, DCOx = 31, MODx = 0
DCORSELx = 1, DCOx = 0, MODx = 0
DCORSELx = 1, DCOx = 31, MODx = 0
DCORSELx = 2, DCOx = 0, MODx = 0
DCORSELx = 2, DCOx = 31, MODx = 0
DCORSELx = 3, DCOx = 0, MODx = 0
DCORSELx = 3, DCOx = 31, MODx = 0
DCORSELx = 4, DCOx = 0, MODx = 0
DCORSELx = 4, DCOx = 31, MODx = 0
DCORSELx = 5, DCOx = 0, MODx = 0
DCORSELx = 5, DCOx = 31, MODx = 0
DCORSELx = 6, DCOx = 0, MODx = 0
DCORSELx = 6, DCOx = 31, MODx = 0
DCORSELx = 7, DCOx = 0, MODx = 0
DCORSELx = 7, DCOx = 31, MODx = 0
SRSEL = fDCO(DCORSEL+1,DCO)/fDCO(DCORSEL,DCO)
SDCO = fDCO(DCORSEL,DCO+1)/fDCO(DCORSEL,DCO)
Measured at SMCLK

0.065
0.65
0.10
1.42
0.27
3.12
0.59
6.02
1.25
12.25
2.45
23.65
4.55
38.95
8.45
59.95
1.2

0.25
1.75
0.41
3.5
0.8
7.43
1.56
14.05
3.25
28.25
6.05
54.15
10.75
88.05
19.65
135.05
2.3

1.02

1.12

dfDCO/dT

40

fDCO = 1 MHz50
0.1

dfDCO/dVCC

fDCO = 1 MHz

1.9

60

DLA LAND AND MARITIMECOLUMBUS, OHIOCAGE CODE
16236
REV

A

ratio

%
%/°C
%/V

See footnotes at end of table.

SIZE
A

MHz

DWG NO.
V62/14608
PAGE 14TABLE I. Electrical performance characteristics - Continued. 1/
Test

SymbolConditions
2/

Limits
Min

Typ

0.78

1.30

Unit
Max

PMM, Brown-Out Reset (BOR)
BORH on voltage, DVCC falling level

V(DVCC_BOR_IT–)| dDVCC/dt | < 3 V/s

BORH off voltage, DVCC rising level

V(DVCC_BOR_IT+)| dDVCC/dt | < 3 V/s

BORH hysteresis

V(DVCC_BOR_hys)

58

tRESET2�����/NMI pin to accept a
Pulse length required at RST
reset

1.47

V

1.52

V

275

mV
µs

PMM, Core Voltage

Core voltage, active mode, PMMCOREV = 3

VCORE3(AM)

2.4 V ≤ DVCC ≤ 3.6 V

1.90Core voltage, active mode, PMMCOREV = 2

VCORE2(AM)

2.2 V ≤ DVCC ≤ 3.6 V

1.80

V

Core voltage, active mode, PMMCOREV = 1

VCORE1(AM)

2.0 V ≤ DVCC ≤ 3.6 V

1.60

Core voltage, active mode, PMMCOREV = 0

VCORE0(AM)1.8 V ≤ DVCC ≤ 3.6 V

1.40

Core voltage, low current mode, PMMCOREV = 3

VCORE3(LPM)

2.4 V ≤ DVCC ≤ 3.6 V

1.94Core voltage, low current mode, PMMCOREV = 2

VCORE2(LPM)

2.2 V ≤ DVCC ≤ 3.6 V

1.84

Core voltage, low current mode, PMMCOREV = 1

VCORE1(LPM)

2.0 V ≤ DVCC ≤ 3.6 V

1.64Core voltage, low current mode, PMMCOREV = 0

VCORE0(LPM)

1.8 V ≤ DVCC ≤ 3.6 V

1.44

SVSHE = 0, DVCC = 3.6 V

0nA

SVSHE = 1, DVCC = 3.6 V,
SVSHFP = 0

200

nA

SVSHE = 1, DVCC = 3.6 V,
SVSHFP = 1

1.5

µA

PMM, SVS High SideSVS current consumption

SVSH on voltage level

SVSH off voltage level

I(SVSH)

43/

43/

SVSH propagation delay

SVSH on or off delay time

DVCC rise time

V(SVSH_IT–)

V(SVSH_IT+)

tpd(SVSH)t(SVSH)SVSHE = 1, SVSHRVL = 0

1.55

1.68

1.8

SVSHE = 1, SVSHRVL = 1

1.77

1.88

2

SVSHE = 1, SVSHRVL = 2

1.96

2.08

2.23

SVSHE = 1, SVSHRVL = 3

2.07

2.18

2.33

SVSHE = 1, SVSMHRRL = 0

1.60

1.74

1.87

SVSHE = 1, SVSMHRRL = 1

1.86

1.94

2.09

SVSHE = 1, SVSMHRRL = 2

2.05

2.14

2.3

SVSHE = 1, SVSMHRRL = 3

2.18

2.30

2.44

SVSHE = 1, SVSMHRRL = 4

2.30

2.40

2.57

SVSHE = 1, SVSMHRRL = 5

2.50

2.70

2.9

SVSHE = 1, SVSMHRRL = 6

2.85

3.10

3.25

SVSHE = 1, SVSMHRRL = 7

2.85

3.10

3.25

SVSHE = 1, SVSHFP = 1
dVDVCC/dt = 10 mV/μs,

2.5

SVSHE = 1, SVSHFP = 0
dVDVCC/dt = 1 mV/μs

20

SVSHE = 0 → 1, SVSHFP = 1
dVDVCC/dt = 10 mV/μs,

12.5

SVSHE = 0 → 1, SVSHFP = 0
dVDVCC/dt = 10 mV/μs,

100

dVDVCC/dt

0

µs

1000

See footnotes at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
16236
REV

A

V

DWG NO.
V62/14608
PAGE 15

V/s

TABLE I. Electrical performance characteristics - Continued. 1/
Test

SymbolLimitsConditions
2/

Min

Typ

Unit
Max

PMM, SVM High SideSVMH current consumption

I(SVMH)

SVMH on or off voltage level
44/

V(SVMH)

SVMH propagation delay

tpd(SVMH)

SVMH on or off delay timet(SVMH)SVMHE = 0, DVCC = 3.6 V
SVMHE = 1, DVCC = 3.6 V, SVMHFP = 0
SVMHE = 1, DVCC = 3.6 V, SVMHFP = 1
SVMHE = 1, SVSMHRRL = 0
SVMHE = 1, SVSMHRRL = 1
SVMHE = 1, SVSMHRRL = 2
SVMHE = 1, SVSMHRRL = 3
SVMHE = 1, SVSMHRRL = 4
SVMHE = 1, SVSMHRRL = 5
SVMHE = 1, SVSMHRRL = 6
SVMHE = 1, SVSMHRRL = 7
SVMHE = 1, SVMHOVPE = 1
SVMHE = 1, SVMHFP = 1
dVDVCC/dt = 10 mV/μs,
SVMHE = 1, SVMHFP = 0
dVDVCC/dt = 1 mV/μs
SVMHE = 0 → 1, SVMHFP = 1
dVDVCC/dt = 10 mV/μs,
SVMHE = 0 → 1, SVMHFP = 0
dVDVCC/dt = 10 mV/μs,

1.61
1.86
2.05
2.18
2.30
2.50
2.85
2.85

0
200
1.5
1.74
1.94
2.14
2.30
2.40
2.70
3.10
3.10
3.75
2.5

1.87
2.09
2.30
2.44
2.58
2.93
3.25
3.25

nA
nA
µA
V

µs

20
12.5

µs

100

PMM, SVS Low SideSVSL current consumption

I(SVSL)SVSL propagation delay

tpd(SVSL)SVSL on or off delay timet(SVSL)SVSLE = 0, PMMCOREV = 2
SVSLE = 1, PMMCOREV = 2, SVSLFP = 0
SVSLE = 1, PMMCOREV = 2, SVSLFP = 1
SVSLE = 1, dVCORE/dt = 10 mV/μs, SVSLFP = 1
SVSLE = 1, dVCORE/dt = 1 mV/μs, SVSLFP = 0
SVSLE = 0 → 1, dVCORE/dt = 10 mV/μs, SVSLFP = 1
SVSLE = 0 → 1, dVCORE/dt = 1 mV/μs, SVSLFP = 0

0
200
1.5
2.5
20
12.5
100

nA
nA
µA
µs

SVMLE = 0, PMMCOREV = 2
SVMLE = 1, PMMCOREV = 2, SVMLFP = 0
SVMLE = 1, PMMCOREV = 2, SVMLFP = 1
SVMLE = 1, dVCORE/dt = 10 mV/μs, SVMLFP = 1
SVMLE = 1, dVCORE/dt = 1 mV/μs, SVMLFP = 0
SVMLE = 0 → 1, dVCORE/dt = 10 mV/μs, SVMLFP = 1
SVMLE = 0 → 1, dVCORE/dt = 1 mV/μs, SVMLFP = 0

0
200
1.5
2.5
20
12.5
100

nA
nA
µA
µs

PMM, SVM Low Side
SVML current consumption

I(SVML)

SVML propagation delay

tpd(SVML)

SVML on or off delay timet(SVML)See footnotes at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
16236
REV

A

DWG NO.
V62/14608
PAGE 16

TABLE I. Electrical performance characteristics - Continued. 1/
Test

SymbolConditions
2/

Limits

VCC
Min

Unit

Typ

Max

3.5
4.5

7.5
9.5

µs

150

170

µs

2

3.5

ms

2

3.5

ms

25

MHz

Wake-Up From Low Power Modes and Reset
Wake up time from LPM2,
LPM3, or LPM4 to active
mode
45/

tWAKE-UPFAST

Wake up time from LPM2,
LPM3, or LPM4 to active
mode
46/

tWAKE-UP-

Wake up time from LPM4.5
to active mode
45/����� orWake up time from RSTBOR event to active mode
47/
Timer_AtWAKE-UP-

SLOW

PMMCOREV = SVSMLRRL = n(where n = 0, 1, 2, or 3),
SVSLFP = 1

fMCLK ≥ 4.0 MHz
1.0 MHz < fMCLK< 4.0 MHzPMMCOREV = SVSMLRRL = n
where n = 0, 1, 2, or 3),
SVSLFP = 0

LPM5tWAKE-UPRESETInternal: SMCLK, ACLK,
External: TACLK,
Duty cycle = 50% ± 10%
All capture inputs
Minimum pulse width required for capture

1.8 V,
3V

Internal: SMCLK, ACLK,
External: TBCLK,
Duty cycle = 50% ± 10%
Timer_B capture timing
tTB,cap
All capture inputs
Minimum pulse width required for capture
USCI (UART Mode) Recommended Operating Conditions

1.8 V,
3V

Timer_A input clock
frequency

fTA

Timer_A capture timingtTA,cap

1.8 V,
3V

20

ns

Timer_B
Timer_B input clock frequency

fTB

USCI input clock frequency

fUSCI

BITCLK clock frequency(equals baud rate in MBaud)USCI (UART Mode)fBITCLKUART receive deglitch timetT

1.8 V,
3V

25

20

Internal: SMCLK, ACLK,
External: UCLK,
Duty cycle = 50% ± 10%

MHz

ns

fSYSTEM MHz

1

2.2 V
3V

50

600

48

620

ns

USCI (SPI Master Mode) Recommended Operating Conditions
USCI input clock frequency

fUSCIInternal: SMCLK, ACLK,
Duty cycle = 50% ± 10%

fSYSTEM MHz

See footnotes at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
16236
REV

A

DWG NO.
V62/14608
PAGE 17

TABLE I. Electrical performance characteristics - Continued. 1/
Test
USCI (SPI Master Mode)

Symbol49/

Conditions
2/

Limits

VCC
Min

fUSCI

SMCLK, ACLK,
Duty cycle = 50% ± 10%

SOMI input data setup time

tSU,MIPMMCOREV = 0

1.8 V

55

3V

38

PMMCOREV = 3

2.4 V

30

3V

25

1.8 V

0

3V

0

2.4 V

0

3V

0

tHD,MIfSYSTEM

PMMCOREV = 0
PMMCOREV = 3

SIMO output data valid timetVALID,MO50/

SIMO output data hold timeMax

see FIGURE 5 and 6

USCI input clock frequency

SOMI input data hold time

Typ

Unit

tHD,MOns

UCLK edge to SIMO valid,

1.8 V

20

CL = 20 pF, PMMCOREV = 0

3V

18

UCLK edge to SIMO valid,

2.4 V

16

CL = 20 pF, PMMCOREV = 3

3V

CL = 20 pF, PMMCOREV = 0

1.8 V

-10

3V

-8

2.4 V

-10

3V

-8

51/
CL = 20 pF, PMMCOREV = 3

15

See footnotes at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
16236
REV

A

MHz

DWG NO.
V62/14608
PAGE 18

TABLE I. Electrical performance characteristics - Continued. 1/
Test
USCI (SPI Slave Mode)

Symbol52/

Conditions
2/

Min

STE lag time, Last clock to STE highSTE access time, STE low to SOMItSTE,LEAD

Unit
Max

tSTE,LAG

tSTE,ACC

PMMCOREV = 0

1.8 V

11

3V

8

PMMCOREV = 3

2.4 V

7

3V

6

PMMCOREV = 0

1.8 V

3

3V

3

PMMCOREV = 3

2.4 V

3

3V

3

PMMCOREV = 0

1.8 V

66

3V

50

PMMCOREV = 3

2.4 V

36

3V

30

PMMCOREV = 0

1.8 V

30

3V

23

2.4 V

16

3V

13

data out

STE disable time, STE high to SOMItSTE,DIS

high impedance
PMMCOREV = 3
SIMO input data setup time

tSU,SIPMMCOREV = 0
PMMCOREV = 3

SIMO input data hold time

tHD,SIPMMCOREV = 0
PMMCOREV = 3

SOMI output data hold timeTypsee FIGURE 7 and 8

STE lead time, STE low to clock

SOMI output data valid time

Limits

VCC

52/

53/

tVALID,SO

tHD,SO

1.8 V

5

3V

5

2.4 V

2

3V

2

1.8 V

5

3V

5

2.4 V

5

3V

5

ns

UCLK edge to SOMI valid,
CL = 20 pF

1.8 V

76

PMMCOREV = 0

3V

60

UCLK edge to SOMI valid,

2.4 V

44

CL = 20 pF
PMMCOREV = 33V

40

CL = 20 pF

1.8 V

18

PMMCOREV = 03V

12

CL = 20 pF

2.4 V

10

PMMCOREV = 3

3V

8

See footnotes at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
16236
REV

A

DWG NO.
V62/14608
PAGE 19

TABLE I. Electrical performance characteristics - Continued. 1/
Test

SymbolUSCI (I2C Mode) see FIGURE 9
USCI input clock frequency

fUSCI

SCL clock frequency
Hold time (repeated) STARTfSCLtHD,STA

Setup time for a repeated
START
Data hold time
Data setup time
Setup time for STOP

tSU,STAtHD,DATtSU,DATtSU,STO

Conditions
2/

AVCC

Analog input voltage range 56/
Operating supply current into
AVCC terminal
57/

V(Ax)
IADC12_A

Input capacitance

CI

Input MUX ON resistance
12-Bit ADC, Timing Parameters

RI

fADC12CLKADC conversion clock

Internal ADC12 oscillator

62/

Conversion time

Sampling time

fDC12OSCtCONVERTtSample

Min

Unit

Typ

Internal: SMCLK, ACLK,
External: UCLK,
Duty cycle = 50% ± 10%

Max
fSYSTEM MHz

2.2 V, 3 V
2.2 V, 3 V

fSCL ≤ 100 kHz
fSCL > 100 kHz
fSCL ≤ 100 kHz
fSCL > 100 kHz

2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V

fSCL ≤ 100 kHz
fSCL > 100 kHz

Pulse duration of spikes
tSP
suppressed by input filter
12-Bit ADC, Power Supply and Input Range Conditions
Analog supply voltage

Limits

VCC

2.2 V
3V

0
4.0
0.6
4.7
0.6
0
250
4.0
0.6
50
50

400

ns
ns
µs
600
600

2.2

3.6

V

0

AVCC
155
270

V
µA

2.2 V
3V

125
150
20

Only one terminal Ax can be selected at onetime
0 V ≤ VAx ≤ AVCC
For specified performance of ADC12 linearity
parameters using an external reference
voltage or AVCC as reference59/
For specified performance of ADC12 linearity
parameters using the internal reference 60/
For specified performance of ADC12 linearity
parameters using the internal reference 61/
ADC12DIV = 0, fADC12CLK = fADC12OSC
REFON = 0, Internal oscillator,
ADC12OSC used for ADC conversion clock
External fADC12CLK from ACLK, MCLK, or
SMCLK,ADC12SSEL ≠ 0
RS = 400 Ω, RI = 1000 Ω, CI = 20 pF,
Ƭ = [RS + RI] × CI
64/

pF

200
2.2 V,
3V

2.2 V,
3V
2.2 V,
3V

Ω

0.45

4.8

5.0

0.45

2.4

4.0

0.45

2.4

2.7

4.2

4.8

5.4

MHz

3.1

µs

2.4

CAGE CODE
16236
REV

A

MHz

63/

2.2 V,
3V

1000

ns

See footnotes at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

ns

55/

AVCC and DVCC are connected together,
AVSS and DVSS are connected together
V(AVSS) = V(DVSS) = 0 V
All ADC12 analog input pins Ax
fADC12CLK = 5.0 MHz
58/

SIZE
A

kHz
µs

DWG NO.
V62/14608
PAGE 20

TABLE I. Electrical performance characteristics - Continued. 1/
Test

SymbolConditions
2/

Limits

VCC
Min

Typ

Unit
M
a
x

12-Bit ADC, Linearity Parameters Using an External Reference Voltage or AVCC as Reference Voltage
Integral linearity error

EI

65/

1.4 V ≤ dVREF ≤ 1.6 V
1.6 V < dVREF

Differential linearity error
65/

ED

Offset error

67/

EO

Gain error

67/

EG

Total unadjusted error

ET

66/

2.2 V, 3 V

66/

±2.0

LSB

±1.7

66/

2.2 V, 3 V±1.0

dVREF ≤ 2.2 V

66/

2.2 V, 3 V±2.0

dVREF > 2.2 V

66/

2.2 V, 3 V±2.0

2.2 V, 3 V

±2.0

66/
dVREF ≤ 2.2 V

66/

2.2 V, 3 V±3.5

dVREF > 2.2 V

66/

2.2 V, 3 V±3.5

12-Bit ADC, Linearity Parameters Using the Internal Reference Voltage
Integral linearity error

EI

65/
Differential linearity error

ED

65/
Offset error
Gain error

67/
67/

Total unadjusted error

EO
EG

ET

ADC12SR = 0, REFOUT = 1

fADC12CLK ≤ 4.0 MHz

ADC12SR = 0, REFOUT = 0

fADC12CLK ≤ 2.7 MHz

ADC12SR = 0, REFOUT = 1

fADC12CLK ≤ 4.0 MHz

ADC12SR = 0, REFOUT = 1

fADC12CLK ≤ 2.7 MHz

ADC12SR = 0, REFOUT = 0

fADC12CLK ≤ 2.7 MHz

ADC12SR = 0, REFOUT = 1

fADC12CLK ≤ 4.0 MHz

ADC12SR = 0, REFOUT = 0

fADC12CLK ≤ 2.7 MHz

ADC12SR = 0, REFOUT = 1

fADC12CLK ≤ 4.0 MHz

ADC12SR = 0, REFOUT = 0

fADC12CLK ≤ 2.7 MHz

ADC12SR = 0, REFOUT = 1

fADC12CLK ≤ 4.0 MHz

ADC12SR = 0, REFOUT = 0

fADC12CLK ≤ 2.7 MHz

2.2 V, 3 V

±1.7
±2.5

2.2 V, 3 V

±2.0
±1.5
±2.5

2.2 V, 3 V

±4.0
±4.0

2.2 V, 3 V

2.2 V, 3 V

±2.5
±1.5%
69/

VREF

±5

LSB

±1.5%
69/

VREF

See footnotes at end of table.

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TABLE I. Electrical performance characteristics - Continued. 1/
Test

SymbolConditions
2/

12-Bit ADC, Temperature Sensor and Built-In VMID
71/

VSENSORTCSENSOR

Sample time requiredtSENSOR(sample)

if channel 10 is selected
72/
AVCC divider at channel 11,
VAVCC factor

VMID

AVCC divider at channel 11
Sample time required
if channel 11 is selected
73/
REF, External ReferencetVMID(sample)

Limits

VCC
Min

Typ

Unit
Max

70/

ADC12ON = 1, INCH = 0Ah,

2.2 V

680

TA = 0°C

3V

680

ADC12ON = 1, INCH = 0Ah

2.2 V

2.25

3V

2.25

mV
mV/°C

ADC12ON = 1, INCH = 0Ah,

2.2 V

100

Error of conversion result ≤ 1
LSB

3V

100

ADC12ON = 1, INCH = 0Bh

2.2 V

0.48

0.5

0.52

VAVCC

ADC12ON = 1, INCH = 0Bh

2.2 V

1.04

1.1

1.14

V

3V

1.44

1.5

1.56

2.2 V, 3 V

1000

ADC12ON = 1, INCH = 0Bh,
Error of conversion result ≤ 1
LSB

µs

ns

74/

Positive external reference
voltage input

VeREF+

VeREF+ > VREF–/VeREF–

75/

1.4

AVCC

Negative external reference
voltage input

VREF–/VeREF–

VeREF+ > VREF–/VeREF–

76/

0

1.2

Differential external reference
voltage input(VeREF+ –VREF–/VeREF–)

VeREF+ > VREF–/VeREF–

77/

1.4

AVCC

Static input current

IVeREF+,
IVREF–/VeREF–

Capacitance at VREF+/-terminal

CVREF+/-

1.4 V ≤ VeREF+ ≤ VAVCC,
VeREF– = 0 V, fADC12CLK = 5 MHz,ADC12SHTx = 1h,
Conversion rate 200 ksps

2.2 V, 3 V

1.4 V ≤ VeREF+ ≤ VAVCC,
VeREF– = 0 V, fADC12CLK = 5 MHz,ADC12SHTx = 8h,
Conversion rate 200 ksps

2.2 V, 3 V

See

78/

±26

-2.5

µA

2.5

10

See footnotes at end of table.

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TABLE I. Electrical performance characteristics - Continued. 1/
Test
REF, Built-In Reference
Positive built-in reference
voltage output

AVCC minimum voltage,
Positive built-in reference
activeOperating supply current
into AVCC terminal
80/ 81/

SymbolConditions
2/

Limits

VCC
Min

Unit

Typ

Max

3V

2.50

±2.5%

3V

1.98

±2.5%

2.2 V,
3V

1.49

±2.5%

79/
VREF+

AVCC(min)

IREF+

Load-current regulation,
VREF+ terminal 82/

IL(VREF+)

Capacitance at VREF+
terminals
Temperature coefficientof built-in reference
40/

CVREF+
TCREF+

Power supply rejection
ratio (DC)

PSRR_DCPower supply rejection
ratio (AC)

PSRR_AC

Settling time of reference
voltage 83/

tSETTLEREFVSEL = {2} for 2.5 V,
REFON = REFOUT = 1, IVREF+ = 0 A
REFVSEL = {1} for 2.0 V,
REFON = REFOUT = 1, IVREF+ = 0 A
REFVSEL = {0} for 1.5 V,
REFON = REFOUT = 1, IVREF+ = 0 A
REFVSEL = {0} for 1.5 V
REFVSEL = {1} for 2.0 V
REFVSEL = {2} for 2.5 V
ADC12SR = 1 , REFON = 1,
REFOUT = 0, REFBURST = 0

V

2.2
2.3
2.8

ADC12SR = 1, REFON = 1,
REFOUT = 1, REFBURST = 0
ADC12SR = 0, REFON = 1,
REFOUT = 0, REFBURST = 0
ADC12SR = 0, REFON = 1,
REFOUT = 1, REFBURST = 0
REFVSEL = (0, 1, 2},
IVREF+ = +10 μA/–1000 μA,
AVCC = AVCC(min) for each reference level,
REFVSEL = (0, 1, 2}, REFON = REFOUT = 1
REFON = REFOUT = 1

3V

70

µA

3V

0.45

mA

3V

210

350

µA

3V

0.95

2

mA

2500

20

IVREF+ = 0 A,
REFVSEL = (0, 1, 2}, REFON = 1,
REFOUT = 0 or 1
AVCC = AVCC(min) - AVCC(max),
TA = 25°C, REFVSEL = (0, 1, 2}, REFON = 1,
REFOUT = 0 or 1
AVCC = AVCC(min) - AVCC(max),
TA = 25°C, f = 1 kHz, ΔVpp = 100 mV,REFVSEL = (0, 1, 2}, REFON = 1,
REFOUT = 0 or 1
AVCC = AVCC(min) - AVCC(max),
REFVSEL = (0, 1, 2}, REFOUT = 0,
REFON = 0 → 1
AVCC = AVCC(min) - AVCC(max),
CVREF = CVREF(max),
REFVSEL = (0, 1, 2}, REFOUT = 1,
REFON = 0 → 1

µV/mA

100

pF

30

ppm/°C

120

µV/V

6.4

mV/V

75

µs

75

See footnotes at end of table.

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Test

SymbolConditions
2/

Limits
Min

Unit

Typ

Max

Flash Memory
Program or erase supply voltage
Average supply current from DVCC during program
Average supply current from DVCC during erase
Average supply current from DVCC during masserase or bank erase
Cumulative program time
Program and erase endurance
Data retention duration
Word or byte program time
Block program time for first byte or word
Block program time for each additional byte or word,
except for last byte or word
Block program time for last byte or word
Erase time for segment, mass erase, and bankerase (when available)
MCLK frequency in marginal read mode
(FCTL4.MGR0 = 1 or FCTL4. MGR1 = 1)

Test

DVCC(PGM/ERASE)IPGM
IERASEIMERASE,
IBANK
tCPT

1.8
3

84/

3.6
7
7
7

V
mA
mA
mA

16

ms
cyclesyearsµs

tBlock, 1–(N–1)

TJ = 25°C
85/
85/
85/

104
100
64
49
37

tBlock, N
tErase

85/
85/

55
23

73
32

ms

0

1

MHz

tRetention
tWord
tBlock, 0

fMCLK,MGR

SymbolConditions
2/

105
85
65
49

Limits

VCC
Min

Typ

Unit
Max

JTAG and Spy-Bi-Wire Interface
Spy-Bi-Wire input frequency
Spy-Bi-Wire low clock pulse length
Spy-Bi-Wire enable time (TEST high toacceptance of first clock edge)
86/
Spy-Bi-Wire return to normal operation time
TCK input frequency, 4-wire JTAG 87/

fSBW
tSBW,LowtSBW, En

Internal pulldown resistance on TEST

Rinternal

2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V

tSBW,Rst
fTCK

2.2 V
3V
2.2 V, 3 V

0
0.025

20
15
1

15
0
0
45

100
5
10
80

60

MHz
µs

MHz
MHz
kΩ

See footnotes at end of table.

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Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the
specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may
not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization
and/or design.
Over recommended ranges of supply voltage and operating free air temperature (unless otherwise noted).
All inputs tied to 0 V or to VCC. Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal andexternal load capacitance are chosen to closely match the required 12.5 pF.
Characterized with program executing typical data processing.
fACLK = 32786 Hz, fDCO = fMCLK = fSMCLK at specified frequency.
XTS = CPUOFF = SCG0 = SCG1 = OSCOFF = SMCLKOFF = 0.
Current for watchdog timer clocked by SMCLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0); fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 1 MHz.
Current for brownout, high side supervisor (SVSH) normal mode included. Low side supervisor and monitors disabled (SVSL,
SVML). High side monitor disabled (SVMH). RAM retention enabled.
Current for watchdog timer and RTC clocked by ACLK included. ACLK = low frequency crystal operation(XTS = 0,
XT1DRIVEx = 0). CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 (LPM2); fACLK = 32768 Hz, fMCLK = 0 MHz,fSMCLK = fDCO = 0 MHz; DCO setting = 1 MHz operation, DCO bias generator enabled.
Current for watchdog timer and RTC clocked by ACLK included. ACLK = low frequency crystal operation (XTS = 0,
XT1DRIVEx = 0). CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0. (LPM3); fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz.
Current for watchdog timer and RTC clocked by ACLK included. ACLK = VLO. CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF =0 (LPM3); fACLK = fVLO, fMCLK = fSMCLK = fDCO = 0 MHz..
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 (LPM4); fDCO = fACLK = fMCLK = fSMCLK = 0 MHz..
Internal regulator disabled. No data retention. CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1, PMMREGOFF = 1 (LPM4.5);
fDCO = fACLK = fMCLK = fSMCLK = 0 MHz.
Same parametric apply to clock input pin when crystal bypass mode is used on XT1 (XIN) or XT2 (XT2IN).
����� pin when pullup/pulldown resistor is enabled.
Also applies to RST
Some devices may contain additional ports with interrupts. See the block diagram and terminal function descriptions.
An external signal sets the interrupt flag every time the minimum interrupt pulse width t(int) is met. It may be set by trigger signals
shorter than t(int).
The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor isdisabled.
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage
drop specified.
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum
voltage drop specified.
Selecting reduced drive strength may reduce EMI.
A resistive divider with 2 × R1 between VCC and VSS is used as load. The output is connected to the center tap of the divider. For
full drive strength, R1 = 550 Ω. For reduced drive strength, R1 = 1.6 kΩ. CL = 20 pF is connected to the output to VSS.
The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
To improve EMI on the XT1 oscillator, the following guidelines should be observed.
(a) Keep the trace between the device and the crystal as short as possible.
(b) Design a good ground plane around the oscillator pins.
(c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
(d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
(f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
When XT1BYPASS is set, XT1 circuits are automatically powered down. Input signal is a digital square wave with parametrics
defined in the Schmitt-trigger Inputs section of this datasheet.
Maximum frequency of operation of the entire device cannot be exceeded.

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Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the
XT1DRIVEx settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following
guidelines, but should be evaluated based on the actual crystal selected for the application:(a) For XT1DRIVEx = 0, CL,eff ≤ 6 pF(b) For XT1DRIVEx = 1, 6 pF ≤ CL,eff ≤ 9 pF(c) For XT1DRIVEx = 2, 6 pF ≤ CL,eff ≤ 10 pF(d) For XT1DRIVEx = 3, CL,eff ≥ 6 pF
Includes parasitic bond and package capacitance (approximately 2 pF per pin). Since the PCB adds additional capacitance, it isrecommended to verify the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitanceshould always match the specification of the used crystal.
Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies in between might set the flag.
Measured with logic-level input frequency but also applies to operation with crystals.
This represents the maximum frequency that can be input to the device externally. Maximum frequency achievable on the device
operation is based on the frequencies present on ACLK, MCLK, and SMCLK cannot be exceed for a given range of operation.
Oscillation allowance is based on a safety factor of 5 for recommended crystals.
Requires external capacitors at both terminals. Values are specified by crystal manufacturers. In general, an effective load
capacitance of up to 18 pF can be supported.
Requires external capacitors at both terminals. Values are specified by crystal manufacturers. In general, an effective load
capacitance of up to 18 pF can be supported.
To improve EMI on the XT2 oscillator the following guidelines should be observed.
(a) Keep the traces between the device and the crystal as short as possible.
(b) Design a good ground plane around the oscillator pins.
(c) Prevent crosstalk from other clock or data lines into oscillator pins XT2IN and XT2OUT.
(d) Avoid running PCB traces underneath or adjacent to the XT2IN and XT2OUT pins.
(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XT2IN and XT2OUT pins.
(f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
When XT2BYPASS is set, the XT2 circuit is automatically powered down. Input signal is a digital square wave with parametrics
defined in the Schmitt-trigger Inputs section of this datasheet.
Includes parasitic bond and package capacitance (approximately 2 pF per pin). Since the PCB adds additional capacitance, it isrecommended to verify the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitanceshould always match the specification of the used crystal.
Measured with logic-level input frequency but also applies to operation with crystals.
Calculated using the box method: (MAX(-40 to 85°C) – MIN(-40 to 85°C)) / MIN(-40 to 85°C) / (85°C – (–40°C)).
Calculated using the box method: (MAX(1.8 to 3.6 V) – MIN(1.8 to 3.6 V)) / MIN(1.8 to 3.6 V) / (3.6 V – 1.8 V).
When selecting the proper DCO frequency range (DCORSELx), the target DCO frequency, fDCO, should be set to reside within
the range of fDCO(n, 0),MAX ≤ fDCO ≤ fDCO(n, 31),MIN, where fDCO(n, 0),MAX represents the maximum frequency specified for the DCO
frequency, range n, tap 0 (DCOx = 0) and fDCO(n,31),MIN represents the minimum frequency specified for the DCO frequency, rangen, tap 31 (DCOx = 31). This ensures that the target DCO frequency resides within the range selected. It should also be notedthat if the actual fDCO frequency for the selected range causes the FLL or the application to select tap 0 or 31, the DCO fault flagis set to report that theselected range is at its minimum or maximum tap setting.
The SVSH settings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply
Voltage Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208) on recommended settings
and usage from manufacturer data sheet.
The SVMH settings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply
Voltage Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208) on recommended settings
and usage from manufacturer data sheet.
This value represents the time from the wakeup event to the first active edge of MCLK. The wakeup time depends on theperformance mode of the low side supervisor (SVSL) and low side monitor (SVML). Fastest wakeup times are possible with
SVSLand SVML in full performance mode or disabled when operating in AM, LPM0, and LPM1. Various options are available for
SVSLand SVML while operating in LPM2, LPM3, and LPM4. See the Power Management Module and Supply Voltage
Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208).

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73/

This value represents the time from the wakeup event to the first active edge of MCLK. The wakeup time depends on theperformance mode of the low side supervisor (SVSL) and low side monitor (SVML). In this case, the SVSLand SVML are innormal mode (low current) mode when operating in AM, LPM0, and LPM1. Various options are available for SVSLand SVML
while operating in LPM2, LPM3, and LPM4. See the Power Management Module and Supply Voltage Supervisor chapter in the
MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208) from manufacturer data sheet.
This value represents the time from the wakeup event to the reset vector execution.
Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses
are correctly recognized their width should exceed the maximum specification of the deglitch time.
fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(USCI) + tSU,SI(Slave), tSU,MI(USCI) + tVALID,SO(Slave)). For the slave's parameters tSU,SI(Slave) andtVALID,SO(Slave) see the SPI parameters of the attached slave.
Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing
diagrams in Figure 5 and Figure 6.
Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate thatthe data on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing
diagrams in Figure 5 and Figure 6.
fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(USCI), tSU,MI(Master) + tVALID,SO(USCI)). For the master's parameters tSU,MI(Master)and tVALID,MO(Master) see the SPI parameters of the attached slave.
Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing
diagrams in Figure 5 and Figure 6.
Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in
Figure 5 and Figure 6.
The leakage current is specified by the digital I/O input leakage.
The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results. If thereference voltage is supplied by an external source or if the internal reference voltage is used and REFOUT = 1, then decoupling
capacitors are required (see REF, External Reference and REF, Built-In Reference from manufacturer data sheet).
The internal reference supply current is not included in current consumption parameter IADC12_A.
ADC12ON = 1, REFON = 0, SHT0 = 0, SHT1 = 0, ADC12DIV = 0.
REFOUT = 0, external reference voltage: SREF2 = 0, SREF1 = 1, SREF0 = 0. AVCC as reference voltage: SREF2 = 0, SREF1= 0, SREF0 = 0. The specified performance of the ADC12 linearity is ensured when using the ADC12OSC. For other clock
sources, the specified performance of the ADC12 linearity is ensured with fADC12CLK maximum of 5.0 MHz.
SREF2 = 0, SREF1 = 1, SREF0 = 0, ADC12SR = 0, REFOUT = 1.
SREF2 = 0, SREF1 = 1, SREF0 = 0, ADC12SR = 0, REFOUT = 0. The specified performance of the ADC12 linearity is ensured
when using the ADC12OSC divided by 2.
The ADC12OSC is sourced directly from MODOSC inside the UCS.
13 × ADC12DIV × 1/fADC12CLK.
Approximately ten Tau (Ƭ) are needed to get an error of less than ±0.5 LSB: tSample = ln(2n+1) x (RS + RI) × CI + 800 ns,
where n = ADC resolution = 12, RS = external source resistance.
Parameters are derived using the histogram method.
The external reference voltage is selected by: SREF2 = 0 or 1, SREF1 = 1, SREF0 = 0. dVREF = VR+ - VR-, VR+ < AVCC,
VR- > AVSS. Unless otherwise mentioned, dVREF > 1.5 V. Impedance of the external reference voltage R < 100 Ω and two
decoupling capacitors, 10 μF and 100 nF, should be connected to VREF+/VREF- to decouple the dynamic current. See also the
MSP430x5xx and MSP430x6xxFamily User's Guide (SLAU208) from manufacturer data sheet.
Parameters are derived using a best fit curve.
The internal reference voltage is selected by: SREF2 = 0 or 1, SREF1 = 1, SREF0 = 1. dVREF = VR+ - VR-.
The gain error and total unadjusted error are dominated by the accuracy of the integrated reference module absolute accuracy.
In this mode the reference voltage used by the ADC12_A is not available on a pin.
The temperature sensor is provided by the REF module. See the REF module parametric, IREF+, regarding the current
consumption of the temperature sensor.
The temperature sensor offset can be significant. A single-point calibration is recommended to minimize the offset error of thebuilt-in temperature sensor. The TLV structure contains calibration values for 30°C ± 3°C and 85°C ± 3°C for each of theavailable reference voltage levels. The sensor voltage can be computed as VSENSE = TCSENSOR * (Temperature,°C) + VSENSOR,
where TCSENSOR and VSENSOR can be computed from the calibration values for higher accuracy. See also the MSP430x5xx and
MSP430x6xx Family User's Guide (SLAU208) from manufacturer data sheet.
The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on).
The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.

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The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance, Ci,
is also the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should
follow the recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.
The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with
reduced accuracy requirements.
The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with
reduced accuracy requirements.
The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be appliedwith reduced accuracy requirements.
Two decoupling capacitors, 10 μF and 100 nF, should be connected to VREF to decouple the dynamic current required for an
external reference source if it is used for the ADC12_A. See also the MSP430x5xx and MSP430x6xx Family User's Guide(SLAU208) from manufacturer data sheet.
The reference is supplied to the ADC by the REF module and is buffered locally inside the ADC. The ADC uses two internalbuffers, one smaller and one larger for driving the VREF+ terminal. When REFOUT = 1, the reference is available at the VREF+
terminal, as well as, used as the reference for the conversion and utilizes the larger buffer. When REFOUT = 0, the reference isonly used as the reference for the conversion and utilizes the smaller buffer.
The internal reference current is supplied via terminal AVCC. Consumption is independent of the ADC12ON control bit, unless aconversion is active. REFOUT = 0 represents the current contribution of the smaller buffer. REFOUT = 1 represents the current
contribution of the larger buffer without external load.
The temperature sensor is provided by the REF module. Its current is supplied via terminal AVCC and is equivalent to IREF+ with
REFON =1 and REFOUT = 0.
Contribution only due to the reference and buffer including package. This does not include resistance due to PCB trace, etc.
The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB. The settling time depends on theexternal capacitive load when REFOUT = 1.
The cumulative program time must not be exceeded when writing to a 128-byte flash block. This parameter applies to all
programming methods: individual word/byte write and block write modes.
These values are hardwired into the flash controller's state machine.
Tools accessing the Spy-Bi-Wire interface need to wait for the tSBW,En time after pulling the TEST/SBWTCK pin high before
applying the first SBWTCK clock edge.
fTCK may be restricted to meet the timing requirements of the module selected.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
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PAGE 28

Case XSEATING
PLANE
0.08

D1/E1

A

e1

A1

D/E

e
M
L
K
J
H
G
F
E
D
C
B
A

A2

A1 CORNERb

SymbolMillim eters
Min
Max

SymbolMillim eters
Min
Max

A
A1
A2
b

1.00
0.15
0.25
0.71
0.77
0.25 0.35

D/E
D1/E1
e
e1

6.90
7.10
5.50 TYP
0.50 BSC
0.25 TYPNOTES:

1.
2.
3.

e1

1
0.05

Dimensions

e

2

3

4

5

6

7

8

9

10

11

12

BOTTOM VIEWM

All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Falls within JEDEC MO-225.
FIGURE 1. Case outline.

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PAGE 29Case Y
D/E
D1/E1
D2/E2
75

51
50

76

26

100
25

1

e

b
0.08

M

A A1

SEATING
PLANE
SEE
DETAIL A

0.08

C
0°-7°
GAGE
PLANE

A3

A2

L

DETAIL A

Symbol
A
A1
A2
A3
b
c

Dimensions

Millim eters
Min
Max

SymbolMillim eters
Min
Max

1.60
1.45
TYP

D/E
D1/E1

15.80
16.20
13.80
14.20
12.00 TYP
0.50 BSC
0.45
0.75

1.35
0.25
0.05
0.17
0.13

0.27
NOM

e
L

NOTES:
1. All linear dimensions are in millimeters.
2. This drawing is subject to change without notice.
3. Falls within JEDEC MS-026.
FIGURE 1. Case outline - Continued.

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PAGE 30

Case outline X
P6.4

P6.2

RST

PJ.1

P5.3

P5.2

P11.2

P11.0

P10.6

P10.4

P10.1

P9.7

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

P6.6

P6.3

P6.1

PJ.3

PJ.0

DVSS4

DVCC4

P10.7

P10.5

P10.3

P9.6

P9.5

B1

B2

B3

B4

B5

B6

B7

B8

B9

B10

B11

B12

P7.5

P6.3

P9.4

P9.2

C1

C2

C11

C12

P5.0

P7.6

P6.0

PJ.2

TEST

P11.1

P10.2

P10.0

P9.0

P8.7

D1

D2

D4

D5

D6

D7

D8

D9

D11

D12

P5.1

AVCC

P6.5

P9.3

P8.6

DVCC2

E1

E2

E4

E9

E11

E12

P7.0

AVSS

P7.4

P9.1

P8.5

DVSS2

F1

F2

F4

F9

F11

F12

P7.1

DVSS1

P7.7

P8.3

P8.4

VCORE

G1

G2

G4

G9

G11

G12

P1.0

DVCC1

P1.1

P8.0

P8.1

P8.2

H1

H2

H4

H5

H6

H7

H8

H9

H11

H12

P1.3

P1.4

P1.2

P2.7

P3.2

P3.5

P4.0

P5.5

P7.2

P7.3

J1

J2

J4

J5

J6

J7

J8

J9

J11

J12

P1.5

P1.6

P5.6

P5.7

K1

K2

K11

K12

P1.7

P2.1

P2.3

P2.5

P3.0

P3.3

P3.4

P3.7

P4.2

P4.3

P4.5

P5.4

L1

L2

L3

L4

L5

L6

L7

L8

L9

L10

L11

L12

P2.0

P2.2

P2.4

P2.6

P3.1

DVSS3

DVCC3

P3.6

P4.1

P4.4

P4.6

P4.7

M1

M2

M3

M4

M5

M6

M7

M8

M9

M10

M11

M12

C3

E5

E6

E7

E8

F5

F8

G5

G8

FIGURE 2. Terminal connections.

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PAGE 31

Case outline Y.
Terminal
number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

Terminal symbol
P6.4/A4
P6.5/A5
P6.6/A6
P6.7/A7
P7.4/A12
P7.5/A13
P7.6/A14
P7.7/A15
P5.0/A8/VREF+/VeREF+
P5.1/A9/VREF−/VeREF−
AVCC
AVSS
P7.0/XIN
P7.1/XOUT
DVSS1
DVCC1
P1.0/TA0CLK/ACLK
P1.1/TA0.0
P1.2/TA0.1
P1.3/TA0.2
P1.4/TA0.3
P1.5/TA0.4
P1.6/SMCLK
P1.7
P2.0/TA1CLK/MCLK

Terminal
number
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50

Terminal symbol
P2.1/TA1.0
P2.2/TA1.1
P2.3/TA1.2
P2.4/RTCCLK
P2.5
P2.6/ACLK
P2.7/ADC12CLK/DMAE0
P3.0/UCB0STE/UCA0CLK
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK/UCA0STE
DVSS3
DVCC3
P3.4/UCA0TXD/UCA0SIMO
P3.5/UCA0RXD/UCA0SOMI
P3.6/UCB1STE/UCA1CLK
P3.7/UCB1SIMO/UCB1SDA
P4.0/TB0.0
P4.1/TB0.1
P4.2/TB0.2
P4.3/TB0.3
P4.4/TB0.4
P4.5/TB0.5
P4.6/TB0.6
P4.7/TB0CLK/SMCLKFIGURE 2. Terminal connections - Continued.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
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PAGE 32

Case outline Y - Continued.
Terminal
number
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75

Terminal symbol
P5.4/UCB1SOMI/UCB1SCL
P5.5/UCB1CLK/UCA1STE
P5.6/UCA1TXD/UCA1SIMO
P5.7/UCA1RXD/UCA1SOMI
P7.2/TB0OUTH/SVMOUT
P7.3/TA1.2
P8.0/TA0.0
P8.1/TA0.1
P8.2/TA0.2
P8.3/TA0.3
P8.4/TA0.4
VCORE
DVSS2
DVCC2
P8.5/TA1.0
P8.6/TA1.1
P8.7
P9.0/UCB2STE/UCA2CLK
P9.1/UCB2SIMO/UCB2SDA
P9.2/UCB2SOMI/UCB2SCL
P9.3/UCB2CLK/UCA2STE
P9.4/UCA2TXD/UCA2SIMO
P9.5/UCA2RXDUCA2SOMI
P9.6
P9.7

Terminal
number
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100

Terminal symbol
P10.0/UCB3STE/UCA3CLK
P10.1/UCB3SIMO/UCB3SDA
P10.2/UCB3SOMI/UCB3SCL
P10.3/UCB3CLK/UCA3STE
P10.4/UCA3TXD/UCA3SIMO
P10.5/UCA3RXDUCA3SOMI
P10.6
P10.7
P11.0/ACLK
P11.1/MCLK
P11.2/SMCLK
DVCC4
DVSS4
P5.2/XT2IN
P5.3/XT2OUTTEST/SBWTCK
PJ.0/TDO
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK�����/NMI/SBWTDIO
RST
P6.0/A0
P6.1/A1
P6.2/A2
P6.3/A3

FIGURE 2. Terminal connections - Continued.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
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PAGE 33

X1N

XT2OUTUNIFIEDCLOCK
SYSTEM

DVCC

DVSS

AVCC

AVSS

SMCLK

256KB
192KB
128KB

FLASH

EEM
(L:8+2)

P1.x

SYS

16KB

WATCHDOGMCLKCPUXV2
AND
WORKINGREGISTERS

RST/NMIPOWER
MANAGEMENT

ACLK

RAM

LDO
SVM/SVSBROWNOUT

PB

P2.x

P3.x

P4.x

P6.x

PE

PD

PC
P5.x

P7.x

P8.x

P9.x

P10.x

PF
P11.x

I/O PORTS
P1/P2
2x8 I/Os
INTERRUPTCAPABILITY

I/O PORTS
P3/P4
2x8 I/OsI/O PORTS
P5/P6
2x8 I/OsI/O PORTS
P7/P8
2x8 I/OsI/O PORTS
P9/P102x8 I/OsI/O PORTS
P11
1x3 I/Os

PA
1x16 I/Os

PB
1x16 I/Os

PC
1x16 I/Os

PD
1x16 I/Os

PE
1x16 I/Os

PF
1x3 I/Os

MAB

DMA

MDB

3 CHANNEL

MPY32

TA0

TA1

TA0

TIMER_A
5 CC
REGISTERSTIMER_A
3 CC
REGISTERSTIMER_B
7 CC
REGISTERS

RTC_A

USC10,1,2,3

ADC12_A

USCI_Ax:UART
IrDA,SPI

12 BIT
200 KSPS

CRC16

JTAG/
SBW
INTERFACEUSCI_Bx
SPI,I2CREF

12 CHANNELS(14 EXT/
2 INT)AUTOSCANFIGURE 3. Functional block diagram.

25
3
20
SYSTEM FREQUENCY-MHz

XT2IN

PA
XOUT

2

2,3

1

1,2

1,2,3

0,1

0,1,2

0,1,2,3

12

8

0

0

1.8

2.0

2.2

2.4

3.6

SUPPLY VOLTAGE-V
THE NUMBERS WITHIN THE FIELDS DENOTE
THE SUPPORTED PMMCOREVx SETTINGSFIGURE 4. Frequency vs Supply voltage.

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PAGE 34

1/f
UCxCLKCKPL=0UCLKCKPL=1
t

t

LO/HI

t
SU,MI

LO/HI

t
HD,MI

SOMI
t
HD,MO

t

VALID,MOSIMO

FIGURE 5. SPI master mode, CKPH = 0.

1/f
UCxCLKCKPL=0UCLKCKPL=1
t

t

LO/HI

t

LO/HI

t

SU,MI

HD,MI

SOMI
t

HD,MO

t

VALID,MOSIMO

FIGURE 6. SPI master mode, CKPH = 1.

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PAGE 35

t
STE,LAGt
STE,LEAD
STE
1/f
UCxCLKCKPL=0UCLKCKPL=1
t

t

LO/HI

t
SU,SI

LO/HI

t
HD,SI

SIMO
t
STE,ACC

t

HD,SO

t

t
STE,DISVALID,SO

SOMI

FIGURE 7. SPI slave mode, CKPH = 0.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
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PAGE 36

t
STE,LEADt
STE,LAGSTE
1/f
UCxCLKCKPL=0UCLKCKPL=1
t
LO/HI

t
LO/HI

t
SU,SI

t
HD,SI

SIMO
t

t
STE,ACC

t

MO,SO

t

STE,DISVALID,SO

SOMI

FIGURE 8. SPI slave mode, CKPH = 1.

tt

HD,STAt

SU,STAt

HD,STA

BUF

SDA
t
LOW

t
HIGH

t

SP

SCL
t

HD,DATtt

SU,DAT

SU,STOFIGURE 9. I2C mode timing.

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PAGE 37

4. VERIFICATION
4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as
indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices,classification, packaging, and labeling of moisture sensitive devices, as applicable.
5. PREPARATION FOR DELIVERY
5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial
practices for electrostatic discharge sensitive devices.
6. NOTES
6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum.
6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book.
The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided.
6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee
of present or continued availability as a source of supply for the item. DLA Land and Maritime maintains an online database of all
current sources of supply at https://landandmaritimeapps.dla.mil/programs/smcr/.

Vendor item drawing
administrative control
number 1/

Devicemanufacturer

V62/14608-01XE

01295

Tape and reel

MSP430F5438AQGQWREP

MF5438AQEP

V62/14608-02XE

01295

Tube

MSP430F5438AMGQWTEP

MF5438AMEP

V62/14608-02YE

01295

Tape and reel

MSP430F5438AMPZREP

MF5438AMEPTransport media

Top Sidemarking

Vendor part number

CAGE code

1/ The vendor item drawing establishes an administrative control number for identifying the item on theengineering documentation.

CAGE code

Source of supply

01295

DLA LAND AND MARITIMECOLUMBUS, OHIO

Texas Instruments, Inc.
Semiconductor Group
8505 Forest Lane
P.O. Box 660199
Dallas, TX 75243

SIZE
A

CAGE CODE
16236
REV

A

DWG NO.
V62/14608
PAGE 38