REVISIONSLTR

DESCRIPTIONDATE (YR-MO-DA)APPROVEDA

Correct device 01 and 02 temp range. Phn

16-08-18

Thomas M. HessB

Update boilerplate to current MIL-PRF-38535 requirements. - PHN

17-06-19

Thomas M. HessC

Update boilerplate paragraphs to current VID description requirements.
- PHN

23-04-20

Muhammad A. Akbar

CURRENT DESIGN ACTIVITY CAGE CODE 16236
HAS CHANGED NAMES TO:
DLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
Prepared in accordance with ASME Y14.24

Vendor Item Drawing

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PMIC N/A
Original date of drawing

Phu H. Nguyen

TITLE

CHECKED BY
Phu H. Nguyen

YY MM DD

DLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
http://www.landandmaritime.dla.mil/

PREPARED BYAPPROVED BY

09-11-03

MICROCIRCUIT, DIGITAL, DIGITAL SIGNALCONTROLLER (DSC), MONOLITHIC SILICON

Thomas M. HessSIZE

CAGE CODE

A

REV C

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PAGE

V62/09624

1 OF 61

AMSC N/A
DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.

5962-V072-23

1. SCOPE
1.1 Scope. This drawing documents the general requirements of a high performance digital signal controller microcircuit, with anoperating temperature range of -40ºC to +125ºC (device type 02) and an extended operating temperature range of -55ºC to +125ºC(device type 01).
1.2 Vendor Item Drawing Administrative Control Number. The manufacturer’s PIN is the item of identification. The vendor item
drawing establishes an administrative control number for identifying the item on the engineering documentation:
V62/09624-

Drawing
number01

X

E

Device type(see 1.2.1)

Case outline(see 1.2.2)

Lead finish(see 1.2.3)

1.2.1 Device type(s). 1/
Device type

Generic

01
02

Operating temperature

SM320F28335-EP
SM320F28335-EP

Circuit function-55°C to +125°C-40°C to +85°C

Digital signal controller
Digital signal controller

1.2.2 Case outline(s). The case outlines are as specified herein.
Outline letter

Number of pins

JEDEC PUB 95

Package style

X
Y

179
176

JEDEC MS-026

Plastic Ball Grid Array
Plastic Quad Flatpack

1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer:
Finish designator

Material

A
B
C
D
E
F
Z

Hot solder dip
Tin-lead plate
Gold plate
PalladiumGold flash palladium
Tin-lead alloy
Other_____________
1/

Users are cautioned to review the manufacturers data manual for additional user information relating to this device.

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PAGE 2

1.3 Absolute maximum ratings. 2/ 3/
Supply voltage range, (VDDIO, VDD3VFL) with respect to VSS ....................................................... -0.3 V to +4.6 V
Supply voltage range, (VDDA2, VDDAIO) with respect to VSSA ...................................................... -0.3 V to +4.6 V
Supply voltage range, (VDD) with respect to VSS ....................................................................... -0.3 V to +2.5 V
Supply voltage range, (VDD1A18, VDD2A18) with respect to VSSA .................................................. -0.3 V to +2.5 V
Supply voltage range, (VSSA2, VSSAIO, VSS1AGND, VSS2AGND) with respect to VSS ......................... -0.3 V to +0.3V
Input voltage range, (VI) ........................................................................................................... -0.3 V to +4.6 V
Output voltage range, (VO) ....................................................................................................... -0.3 V to +4.6 V
Input clamp current, (IIK) (VIN < 0 or VIN > VDDIO) 4/ ................................................................ ±20 mA
Output clamp current, (IOK) (VO < 0 or VO >VDDIO) .................................................................... ±20 mA
Operating ambient temperature ranges, (TA):Device type 01 ............................................................................................................... -55°C to +125° 5/Device type 02 .............................................................................................................. -40°C to +85°C 5/
Junction temperature range, (TJ) .............................................................................................. -40°C to +150°C
Storage temperature range, (TSTG)............................................................................................ -65°C to +150°C
1.4 Recommended operating conditions. 6/

5/
5/

7/

Device supply voltage, (I/O, VDDIO) ........................................................................................... +3.135 V to +3.465 V
Device supply voltage CPU, VDD:
Device operation @ 150 MHz ....................................................................................... +1.805 V to +1.995 V
Device operation @ 100 MHz ....................................................................................... +1.71 V to +1.89 V
Supply ground, (VSS, VSSIO, VSSAIO, VSSA2, VSSA1AGND, VSS2AGND) ............................................... 0 V
ADC supply voltage (3.3 V), (VDDA2, VDDAIO) ............................................................................. +3.135 V to +3.465 V
ADC supply voltage, VDD1A18, VDD2A18):
Device operation @ 150 MHz ....................................................................................... +1.805 V to +1.995 V
Device operation @ 100 MHz ....................................................................................... +1.71 V to +1.89 V
Flash supply voltage, VDD3VFL ................................................................................................... +3.135 V to +3.465 V
Device clock frequency (system clock), (fSYSCLKOUT) ................................................................. 2 MHz to 150 MHz
High level input voltage, (VIH) ................................................................................................... +2 V to VDDIO
Maximum low level input voltage, (VIL) ..................................................................................... +0.8 V
Maximum high level output source current, VOH = 2.4 V, (IOH):
All I/Os except group 2 .................................................................................................. -4 mA
Group 2 7/ .................................................................................................................... -8 mA
Maximum low level output sink current, (VOL = VOL MAX, (IOL):All I/Os except group 2 .................................................................................................. 4 mA
Group 2 7/ .................................................................................................................... 8 mA
Ambient temperature, TA:
Device type 01 .............................................................................................................. -55°C to +125°
Device type 02 .............................................................................................................. -40°C to +85°C
Maximum junction temperature (TJ) ......................................................................................... +125°C______
2/
Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These arestress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under“recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods
may affect device reliability.
3/
All voltage values are with respect to VSS., unless otherwise noted.
4/
Continuous clamp current per pin is ±2 mA. This includes the analog inputs which have an internal clamping circuit thatclamps the voltage to a diode drop above VDDA2 or below VSSA2.
5/Long term high temperature storage and/or extended use at maximum recommended operating conditions may result in a
reduction of overall device life.
6/
Use of this product beyond the manufacturers design rules or stated parameters is done at the user’s risk. The manufacturer
and/or distributor maintain no responsibility or liability for product used beyond the stated limits.
7/
Group 2 pins are as follows: GPIO28, GPIO29, GPIO30, GPIO31, TDO, XCLKOUT, EMU0, EMU1, XINTF pins, GPIO35-87,
������.
XRD

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2. APPLICABLE DOCUMENTSJEDEC PUB 95
JEDEC STD 51-7––

Registered and Standard Outlines for Semiconductor Devices
High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages(Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington,
VA 22201-3834 or online at http://www.jedec.org)
3. REQUIREMENTS
3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as
follows:
A.
B.
C.

Manufacturer’s name, CAGE code, or logo
Pin 1 identifier
ESDS identification (optional)

3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable)
above.
3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics areas specified in 1.3, 1.4, and table I herein.
3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein.
3.5 Diagrams.
3.5.1

Case outline(s). The case outline(s) shall be as shown in 1.2.2 and figure 1.

3.5.2

Terminal connections. The terminal connections shall be as shown in figure 2.

3.5.3

Block diagram. The block diagram shall be as specified in figure 3.

3.5.4

Timing waveforms. The timing waveforms shall be as shown in figure 4-39.

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PAGE 4TABLE I. Electrical performance characteristics.
Test

High level output voltage

Test condition
Device type: All
2/

Symbol

VOH

1/

2.4

IOH = 50 µA

VDDIO
– 0.2

VOL

IOL = IOL MAX

Input current(low level)

IIL

VDDIO = 3.3 V,
All I/Os (including �����XRS)
VIN = 0 V
VDDIO = 3.3 V, VIN = 0 V
VDDIO = 3.3 V, VIN = VDDIOVDDIO = 3.3 V, VIN = VDDIO
VO = VDDIO or 0 V

Pin with pulldown enable
Input current
Pin with pullup enable(high level)
Pin with pulldown enable
Output current, pullup or pulldown disabled
Input capacitance

IIH
IOZ
CI

Min

IOH = IOH MAX

Low level output voltage
Pin with pullup enable

Lim its

Unit
Max
V

0.4

V

-80

-190

µA

28

±2
±2
80
±2
TYP

2

µA
µA
pF

Current consumption by power supply pins at 150 MHz SYSCLOCKOUT
Operational (Flash) 3/

IDLE

STANDBY

HALT

IDD
IDDIO 4/
IDD3VFL 5/
IDDA18 6/
IDDA13 7/

IDD
IDDIO 4/
IDD3VFL 5/
IDDA18 6/
IDDA13 7/
IDD
IDDIO 4/
IDD3VFL 5/
IDDA18 6/
IDDA13 7/
IDD
IDDIO 4/
IDD3VFL 5/
IDDA18 6/
IDDA13 7/

The following clocks are enabled:- ePWM1/2/3/4/5/6 - eCAP1/2/3/4/5/6- eQEP1/2- eCAN-A- SCI-A/B (FIFO mode) - ADC- SPI-A(FIFO mode)- I2C- CPU Timer 0/1/2
All PWM pins are toggled at 150 kHz.
All I/O pins are left unconnected
8/Flash is powered down. XCLOKOUT isturned off. The following peripheral
clocks are enabled:- eCAN-A- SCI-A- SPI-A- I2C

Flash is powered down. Peripheral
clocks are off.

Flash is powered down. Peripheral
clocks are off. Input clocks is disabled.
10/

315
50
40
35
2

120
120
10
60
20
15
120
10
60
20
150 TYP 11/
120
10
60
20

mA

mA
µA

mA
µA

µA

See footnotes at end of table.

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PAGE 5TABLE I. Electrical performance characteristics - Continued.
Test

Test condition
Device type: All
2/

Symbol1/
Lim its

Unit

Min

Max

28.6
20
6.67
4
6.67
2
6.67
0.5
6.67

50
35
250
150
500
150
2000
150

Clocking and Nomenclature (150 MHz devices)
On chip oscillator clock
XCLKIN 12/SYSCLKOUTXCLKOUTHSPCLK 13/
LSPCLK 13/
ADC clocktc(OSC), cycle time
Frequencytc(CI), cycle time
Frequencytc(SCO), cycle time
Frequencytc(XCO), cycle time
Frequencytc(HCO), cycle time
Frequencytc(LCO), cycle time
Frequencytc(ADCCLK), cycle time
Frequency

150
13.3
75
40
25

Clocking and Nomenclature (100 MHz devices)
On chip oscillator clocktc(OSC), cycle time
Frequency
XCLKIN 14/
tc(CI), cycle time
Frequency
SYSCLKOUT
tc(SCO), cycle time
Frequency
XCLKOUT
tc(XCO), cycle time
Frequency
HSPCLK 13/
tc(HCO), cycle time
Frequency
LSPCLK 13/
tc(LCO), cycle time
Frequency
ADC clocktc(ADCCLK), cycle time
Frequency
Input clock frequency
Resonator (X1/X2)
Input clock frequency
fx
Crystal (X1/X2)
External oscillator/clock 150 MHz device
source (XCLKIN or X1
pin)
100 MHz device
Limp mode SYSCLKOUT
flfrequency range (with /2
enabled)

28.6
20
10
4
10
2
10
0.5
10

50
35
250
100
500
100
2000
100
100

20
50
40
25
20
20
4
4
1–5

35
35
150
100
TYP

ns
MHz
ns
MHz
ns
MHz
ns
MHz
ns
MHz
ns
MHz
ns
MHz
ns
MHz
ns
MHz
ns
MHz
ns
MHz
ns
MHz
ns
MHz
ns
MHz
MHz

MHz

See footnotes at end of table.

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TABLE I. Electrical performance characteristics - Continued.
No

Test

SymbolTest condition
Device type: All
2/

1/
Limits

Unit

Min

Max

33.3

45

200
6
6
55

ns
ns
ns
%

45

55

%

6.67
10

45

250
250
6
2
6
2
55

ns
ns
ns
ns
ns
ns
%

45

55

%

XCLKIN timing requirements – PLL enabled
C8
C9
C10
C11
C12

Cycle time, XCLKIN
Fall time, XCLKIN 15/
Rise time, XCLKIN 15/
Pulse duration, XCLKIN low as apercentage of tc(OSCCLK) 15/
Pulse duration, XCLKIN high as apercentage of tc(OSCCLK) 15/

tc(CI)
tf(CI)
tr(CI)
tw(CIL)See figure 4.

tw(CIH)XCLKIN timing requirements – PLL disabled
C8

Cycle time, XCLKIN

tc(CI)

C9

Fall time, XCLKIN 15/

tf(CI)

C10

Rise time, XCLKIN 15/

tr(CI)

150 MHz device
100 MHz device
Up to 30 MHz
30 MHz to 150 MHz
Up to 30 MHz
30 MHz to 150 MHz

C11

Pulse duration, XCLKIN low as atw(CIL)
percentage of tc(OSCCLK) 15/
C12 Pulse duration, XCLKIN high as atw(CIH)
percentage of tc(OSCCLK) 15/
XCLKOUT switching characteristics (PLL Bypassed or Enabled) 16/ 17/
C1
Cycle time, XCLKOUT
tC(XCO)
150 MHz device
100 MHz device
C3
Fall time, XCLKOUT
tf(XCO)
C4
Rise time, XCLKOUT
tr(XCO)
C5
Pull duration, XCLKOUT low
tw(XCOL)
C6
Pull duration, XCLKOUT hightw(XCOH)
PLL lock time
tp

6.67
10

ns
2
2

H-2
H-2

TYP
TYP
H+2
H+2
131072tc(OSCCLK)

ns
ns
ns
ns
cyclesSee footnotes at end of table.

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TABLE I. Electrical performance characteristics - Continued.
Test������ timing requirements
Reset 𝐗𝐗𝐗𝐗𝐗𝐗
Pulse duration, stable input
clock to �����XRS high
Pulse duration, �����XRS low
Pulse duration, reset pulse
generated by watchdog
Delay time, address/data valid
after �����XRS high
Oscillator start up time
Hold time for boot mode pin

Symboltw(RSL1) 19/
tw(RSL2)
tw(WDRS)1/

Test condition
Device type: All2/

Min

See figure 5 and 6.

32tc(OSCCLK)

Warm reset

32tc(OSCCLK)
512tc(OSCCLK)

TYP

32tc(OSCCLK)

TYP

Limitstd(EX)tOSCST 20/th(boot-mode)

1
200tc(OSCCLK)GPIO – OUTPUT TIMING
General Purpose Output switching characteristics See figure 8.
Rise time, GPIO switching lowtr(GPO)All GPIOs
to high
Fall time, GPIO switching hightf(GPO)All GPIOs
to low
Toggling frequency, GPO pins
tf(GPO)

Unit
Max
cycles10ms
cycles

8

ns

8

ns

25

MHz

General Purpose Input timing requirements See figure 9 and 10.
Sampling periodtw(SP)

Input qualifier sampling
window
Pulse duration, GPIO low/hightw(IQSW)
tw(GPI)22/

QUALPRD = 0
QUALPRD ≠ 0

1tc(SCO)2tc(SCO) * QUALPRD
tw(SP) * (n – 1) 21/

Synchronous mode
With input qualifier2tc(SCO)tw(IQSW) + tw(SP) +1tc(SCO)IDLE mode timing requirements See figure 11.
Pulse duration, external waketw(WAKE-INT)
Without input qualifier
up signal
With input qualifier
IDLE mode switching characteristics
Delay time, external wakesignal to program execution
resume23/
Without input qualifier
Wake up from flash•
Flash module in active
state
Wake up from flash•
Flash module in sleep
state•
Wake up from SARAM

cycles2tc(SCO)5tc(SCO) + tw(QSW)

cycles20tc(SCO)

cyclestd(WAKE-IDLE)

STANDBY mode timing requirementstw(WAKE-INT)

With input qualifier

20tc(SCO) + tw(IQSW)Without input qualifier
With input qualifier

1050tc(SCO)
1050tc(SCO) +tw(IQSW)
20tc(SCO)
20tc(SCO) + tw(IQSW)Without input qualifier
With input qualifier
Without input qualifier
With input qualifier 24/

3tc(OSCCLK)(2 + QUALSTDBY) *3tc(OSCCLK)

cyclesSee footnotes at end of table.

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PAGE 8TABLE I. Electrical performance characteristics - Continued.
Test

SymbolTest condition
Device type: All2/

1/
Lim its

Min

Unit
Max

GPIO – OUTPUT TIMING – Continued
STANDBY mode switching characteristics See figure 12
Delay time, IDLE
td(IDLE-XCOL)
32tc(SCO)
instruction executed to
XCLKOUT low
Delay, external wake signal td(WAKE-STBY)
to program execution
resume 23/
Without input qualifier• Wake up from flash- Flash module inWith input qualifier
active state
Without input qualifier• Wake up from flash- Flash module inWith input qualifier
sleep state
Without input qualifier• Wake up from SARAM
With input qualifier
HALT mode timing require ments
Pulse duration, GPUIO
tw(WAKE-GPIO)tOSCST + 2tc(OSCCLK)
wakeup signaltw(WAKE-XRS)
tOSCST + 8tc(OSCCLK)
Pulse duration, �����XRS
wakeup signal
HALT mode switching cha racteristics
See figure 13
Delay time, IDLE
td(IDLE-XCOL)
32tc(SCO)
instruction executed to
XCLKOUT low
PLL look-up time
tp
Delay time, PLL lock toprogram execution resume• Wake up from Flashtd(WAKE-HALT)- Flash module insleep state• Wake up from SARAM

45tc(SCO)

100tc(SCO)
100tc(SCO) + tw(WAKE-INT)
1125tc(SCO)
1125tc(SCO) + tw(WAKE-INT)
100tc(SCO)
100tc(SCO) + tw(WAKE-INT)
cycles45tc(SCO)
131072tc(OSCCLK)
1125tc(SCO)

35tc(SCO)

See footnotes at end of table.

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PAGE 9cyclesTABLE I. Electrical performance characteristics - Continued.
Test

Test condition
Device type: All
2/

SymbolePWM timing requirements
Sync input pulse width
EPWM switching characteristics
ePWM pulse duration, PWMx output highSync output pulse width
Delay time, trip input active to PWM
forced high/low
Delay time, trip input active to PWM Hi-Z

1/
Lim its
Min

Unit
Max

ENHANCED CONTROL PERIPHERALStw(SYCIN)
See figure

Asynchronous
Synchronous
With input qualifier2tc(SCO)2tc(SCO)
1tc(SCO) + tw(IQSW)

cycles20
25

ns
cycles
ns

20

ns

14

tw(PWM)
tw(SYNCOUT)
td(PWM)tza

8tc(SCO)no pin loadtd(TZ-PWM)HZ

Trip zone input timing requirements
Pulse duration, �����
TZx input low

tw(TZ)

Asynchronous
Synchronous
With input qualifier

1tc(SCO)2tc(SCO)
1tc(SCO) + tw(IQSW)

cyclesHigh resolution PWM characteristics at SYSCLKOUT = (60-150 MHz)
Micro edge positioning (MEP) step size
25/

310

ps

Enhanced capture (eCAP) timing requi rement
Capture input pulse width

Asynchronous
Synchronous
With input qualifiertw(CAP)

2tc(SCO)2tc(SCO)
1tc(SCO) + tw(IQSW)

cycles20

ns

2tc(SCO)2(1tc(SCO) +tw(IQSW))
2tc(SCO)2tc(SCO) + tw(IQSW)
2tc(SCO)2tc(SCO) + tw(IQSW)
2tc(SCO)2tc(SCO) + tw(IQSW)
2tc(SCO)2tc(SCO) + tw(IQSW)

cycleseCAP switching characteristics
Pulse duration, APWMx output high/lowtw(APWM)

Enhanced quadrature encoder pulse (e QEP) timing

requirements

QEP input periodtw(QEP)

Asynchronous /Synchronous
With input qualifier

QEP index input high timetw(INDEXH)

QEP index input low timetw(INDEXL)QEP strobe high timetw(STROBH)

QEP strobe input low timetw(STROBL)

Asynchronous /Synchronous
With input qualifier
Asynchronous /Synchronous
With input qualifier
Asynchronous /Synchronous
With input qualifier
Asynchronous /Synchronous
With input qualifier

eQEP switching characteristics
Delay time, external clock to counterincrement
Delay time, QEP input edge to position
compare sync output

td(CNTR)xin

4tc(SCO)td(PCS-

6tc(SCO)cyclesOUT)QEP

See footnotes at end of table.

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TABLE I. Electrical performance characteristics - Continued.
Test

Test condition
Device type: All
2/

Symbol1/
Lim its
Min

ENHANCED CONTROL PERIPHERALS - Continued
External ADC start of conversion switching characteristics See figure 15
tw(ADCSOCAL)
6tc(SCO)
Pulse duration, ���������������
ADCSOCAO low
EXTERNAL INTERRUPT TIMING
External interrupt timing requirements See figure 16
Pulse duration, INT input low/hightw(INT)
Synchronous
1tc(SCO)
26/
With qualifier
1tc(SCO) + tw(IQSW)External interrupt switching characteristics
Delay time, INT low/high to interrupt
td(INT)
vector fetch
I2C ELECTRICAL SPECIFICATION AND TIMING
I2C timing
I2C clock module frequency is
SCL clock frequency
fSCL
between 7 MHz and 12 MHz
and I2C prescaler and clock
divider register are configured
appropriately
Low level input voltage
VILHigh level input voltage
VIH
0.3 VDDIO
Input hysteresis
Vhys
0.3 VDDIO
Low level output voltage
VOL
3 mA sink current
0
Low period of SCL clocktLOW
I2C clock module frequency is
1.23
between 7 MHz and 12 MHz
and I2C prescaler and clock
High period of SCL clocktHIGH
divider register are configured
0.6
appropriately
Input current with an input voltage
II-10
between 0.1 VDDIO and 0.9 VDDIO
MAX

Unit
Max

cyclescycles12tc(SCO) +tw(IQSW

cycles400

kHz

0.3 VDDIO

V
V
V
V
µs

0.4

µs
10

See footnotes at end of table.

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PAGE 11µA

No

TABLE I. Electrical performance characteristics - Continued.

1/

Test condition

Limits

Test

SymbolDevice type: All
2/

SPI when(SPIBRR +1) is evenor SPIBRR = 0 or 2
Min

Max

SERIAL PERIPHERAL INTERFACE (SPI) TIMINGSPI master mode external timing (Clock phase = 0) 27/ 28/ 29/ 30/ 31/
See figure 17
4tc(LCO)
128tc(LCO)
Cycle time, SPICLK
tc(SPC)M
1
2

3

4

5

8

9

Pulse duration, SPICLK high(clock parity = 0)tW(SPCH)M

Pulse duration, SPICLK low(clock parity = 1)tW(SPCL)M

Pulse duration, SPICLK low(clock parity = 0)tW(SPCL)M

Pulse duration, SPICLK high(clock parity = 1)tW(SPCH)M

Delay time, SPICLK high to
SPISIMO valid(clock polarity = 0)td(SPCH-SIMO)M

Delay time, SPICLK low to
SPISIMO valid(clock polarity = 1)

td(SPCL-SIMO)M

Valid time, SPISIMO data valid
after SPICLK low(clock polarity = 0)tv(SPCL-SIMO)M

Valid time, SPISIMO data valid
after SPICLK high(clock polarity = 1)

tv(SPCH-SIMO)M

Setup time, SPISOMI before
SPICLK low (clock polarity = 0)tsu(SOMI-SPCL)M

Setup time, SPISOMI before
SPICLK high (clock polarity =1)

tsu(SOMI-SPCH)M

Valid time, SPISOMI data valid
after SPICLK low(clock polarity = 0)tv(SPCL-SOMI)M

Valid time, SPISOMI data valid
after SPICLK high(clock polarity = 1)

tv(SPCH-SOMI)MUnit

SPI when(SPIBRR +1) is odd
and SPIBRR > 3
Min

Max

5tc(LCO)

127tc(LCO)

32/

33/

34/

35/

32/

33/

34/

35/

32/

33/

36/

37/

32/

33/

36/

37/

10

10

10

10

32/

36/

32/

36/

35

35

35

35

38/

34/

38/

34/

See footnotes at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
16236
REV

C

DWG NO.
V62/09624
PAGE 12ns

No

TABLE I. Electrical performance characteristics - Continued.

1/

Test condition

Limits

Test

SymbolDevice type: All
2/

SPI when(SPIBRR +1) is evenor SPIBRR = 0 or 2
Min

Max

SERIAL PERIPHERAL INTERFACE (SPI) TIMING - Continued
SPI master mode external timing (Clock phase = 1) 39/ 28/ 29/ 30/ 31/
1
See figure 18
4tc(LCO)
128tc(LCO)
Cycle time, SPICLK
tc(SPC)M
2

3

6

7

10

9

Pulse duration, SPICLK high(clock parity = 0)tW(SPCH)M

Pulse duration, SPICLK low(clock parity = 1)tW(SPCL)M

Pulse duration, SPICLK low(clock parity = 0)tW(SPCL)M

Pulse duration, SPICLK high(clock parity = 1)tW(SPCH)M

Setup time, SPISIMO data valid
before SPICLK high(clock polarity = 0)tsu(SIMO-SPCH)M

Setup time, SPISIMO data valid
before SPICLK low(clock polarity = 1)

tsu(SIMO-SPCL)M

Valid time, SPISIMO data valid
after SPICLK high(clock polarity = 0)tv(SPCL-SIMO)M

Valid time, SPISIMO data valid
after SPICLK low(clock polarity = 1)

tv(SPCH-SIMO)M

Setup time, SPISOMI before
SPICLK high (clock polarity = 0)tsu(SOMI-SPCH)M

Setup time, SPISOMI before
SPICLK low (clock polarity = 1)

tsu(SOMI-SPCL)M

Valid time, SPISOMI data valid
after SPICLK high(clock polarity = 0)tv(SPCH-SOMI)M

Valid time, SPISOMI data valid
after SPICLK low(clock polarity = 1)

tv(SPCL-SOMI)MUnit

SPI when(SPIBRR +1) is odd
and SPIBRR > 3
Min

Max

5tc(LCO)

127tc(LCO)

32/

33/

34/

35/

32/

33/

34/

35/

32/

33/

36/

37/

32/

33/

36/

37/

32/

32/

32/

32/

32/

32/

32/

32/

35

35

35

35

38/

32/

38/

32/

See footnotes at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
16236
REV

C

DWG NO.
V62/09624
PAGE 13ns

TABLE I. Electrical performance characteristics - Continued.
No

Test

1/

Test condition

SymbolDevice type: All2/

Lim its
Min

Unit
Max

SERIAL PERIPHERAL INTERFACE (SPI) TIMING - Continued
SPI slave mode external timing (clock phase = 0) 40/ 28/ 29/ 30/ 31/
12 Cycle time, SPICLK
tc(SPC)SSee figure 19
4tc(LCO)13
14

tW(SPCH)S

0.5tc(SPC)S - 10

0.5tc(SPC)S

Pulse duration, SPICLK low (clock parity = 1)tW(SPCL)S

0.5tc(SPC)S - 10

0.5tc(SPC)S

Pulse duration, SPICLK low (clock parity = 0)tW(SPCL)S

0.5tc(SPC)S - 10

0.5tc(SPC)StW(SPCH)S

0.5tc(SPC)S - 10

0.5tc(SPC)S

Pulse duration, SPICLK high (clock parity = 1)
15

16

19

20

ns

Pulse duration, SPICLK high (clock parity = 0)

Delay time, SPICLK high to SPISOMI valid(clock polarity = 0)td(SPCH-SOMI)S

35

Delay time, SPICLK low to SPISOMI valid(clock polarity = 1)

td(SPCL-SOMI)S

35

Valid time, SPISOMI data valid after SPICLK low(clock polarity = 0)tv(SPCL-SOMI)S

0.75tc(SPC)S

Valid time, SPISOMI data valid after SPICLK high(clock polarity = 1)

tv(SPCH-SOMI)S

0.75tc(SPC)S

Setup time, SPISIMO before SPICLK low(clock polarity = 0)tsu(SIMO-SPCL)S

35

Setup time, SPISIMO before SPICLK high(clock polarity = 1)

tsu(SIMO-SPCH)S35

Valid time, SPISIMO data valid after SPICLK low(clock polarity = 0)tv(SPCL-SIMO)S

0.5tc(SPC)S - 10

Valid time, SPISIMO data valid after SPICLK high(clock polarity = 1)

tv(SPCH-SIMO)S

0.5tc(SPC)S - 10

See footnotes at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
16236
REV

C

DWG NO.
V62/09624
PAGE 14TABLE I. Electrical performance characteristics - Continued.
No

Test

1/

Test condition
Device type: All
2/

Symbol

Lim its
Min

Unit
Max

SERIAL PERIPHERAL INTERFACE (SPI) TIMING - Continued
SPI slave mode external timing (clock phase = 1) 41/ 28/ 29/ 30/ 31/
12 Cycle time, SPICLK
tc(SPC)SSee figure 20
4tc(LCO)13
14

tW(SPCH)S

0.5tc(SPC)S - 10

0.5tc(SPC)S

Pulse duration, SPICLK low (clock parity = 1)tW(SPCL)S

0.5tc(SPC)S - 10

0.5tc(SPC)S

Pulse duration, SPICLK low (clock parity = 0)tW(SPCL)S

0.5tc(SPC)S - 10

0.5tc(SPC)S
0.5tc(SPC)StW(SPCH)S

0.5tc(SPC)S - 10

Setup time, SPISOMI before SPICLK high(clock polarity = 0)tsu(SOMI-SPCH)S

0.125tc(SPC)S

Setup time, SPISOMI before SPICLK low(clock polarity = 1)

tsu(SOMI-SPCL)S

0.125tc(SPC)S

Valid time, SPISOMI data valid after SPICLK low(clock polarity = 0)tv(SPCH-SOMI)S

0.75tc(SPC)S

Valid time, SPISOMI data valid after SPICLK
high (clock polarity = 1)

tv(SPCL-SOMI)S

0.75tc(SPC)S

Setup time, SPISIMO before SPICLK high(clock polarity = 0)tsu(SIMO-SPCH)S

35

Setup time, SPISIMO before SPICLK low(clock polarity = 1)

tsu(SIMO-SPCL)S35

Valid time, SPISIMO data valid after SPICLK
high(clock polarity = 0)tv(SPCH-SIMO)S

0.5tc(SPC)S - 10

Valid time, SPISIMO data valid after SPICLK low(clock polarity = 1)

tv(SPCL-SIMO)S

0.5tc(SPC)S - 10

Pulse duration, SPICLK high (clock parity = 1)
17

18

21

22

ns

Pulse duration, SPICLK high (clock parity = 0)

Test

SymbolTest condition
Device type: All2/

Dur ations
X2TIMING = 0

Unit
X2TIMING = 1

EXTERNAL INTERFACE (XINTF) TIMING
Relationship between parameters configured in XTIMING and duration of Pulse
Lead period, read accessLR
XRDLEAD x tc(XTIM)
Active period, read accessAR(XRDACTIVE + WS + 1) x
tc(XTIM)
Trail period, read accessTR
XRDTRAIL x tc(XTIM)
Lead period, write accessLW
XWRLEAD x tc(XTIM)
Active period, write
AW(XWRACTIVE + WS + 1) x
accesstc(XTIM)
Trail period, write accessTW
XWRTRAIL x tc(XTIM)(XRDLEAD x 2) x tc(XTIM)(XRDACTIVE x 2 + WS + 1) x
tc(XTIM)(XRDTRAIL x 2) x tc(XTIM)(XWRLEAD x 2) x tc(XTIM)(XWRACTIVE x 2 + WS + 1) x
tc(XTIM)(XWRTRAIL x 2) x tc(XTIM)

See footnotes at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
16236
REV

C

DWG NO.
V62/09624
PAGE 15

ns

TABLE I. Electrical performance characteristics - Continued.
Test

1/

Test condition
Device type: All
2/

Symbol

Lim its
Min

EXTERNAL INTERFACE (XINTF) TIMING - Continued
External interface Read timing requirements
See figure 23
Access time, read data from address validta(A)Access time, read data valid from ������XRD active low������ strobe inactive
Setup time, read data valid before XRD
high������ inactive highHold time, read data valid after XRD
External interface READ switching characteristicsta(XRD)tsu(XD)XRD

14th(XD)XRD

0

Delay time, XCLKOUT high to zone chip select active low
Delay time, XCLKOUT high/low to zone chip selectinactive high
Delay time, XCLKOUT high to address valid������ active low
Delay time, XCLKOUT high/low to XRD
Delay time, XCLKOUT high/low to ������XRD inactive highHold time, address valid after zone chip select inactive
high
Hold time, address valid after ������XRD inactive highExternal interface WRITE switching characteristics

td(XCOH-XZCSL)
td(XCOHL-XZCSH)

Delay time, XCLKOUT high to zone chip select active low
Delay time, XCLKOUT high/low to zone chip selectinactive high
Delay time, XCLKOUT high to address valid
Delay time, XCLKOUT high/low to ��������
XWE0, ��������
XWE1 active
low 46/
Delay time, XCLKOUT high/low to ��������
XWE0, ��������
XWE1 high 46/
� low
Delay time, XCLKOUT high to XR/W� highDelay time, XCLKOUT high/low to XR/W��������
Enable time, data bus driven from XWE0, ��������
XWE1 low
Delay time, data valid after ��������
XWE0, ��������
XWE1 active low
Hold time, address valid after zone chip select inactive
high
Hold time, address valid after ��������
XWE0, ��������
XWE1 inactive hightd(XCOH-XZCSL)
td(XCOHL-XZCSH)

Maximum time for DSP to release the data bus after� inactive high
XR/W

See figure 23-1

td(XCOH-XA)
td(XCOHL-XRDL)
td(XCOHL-XRDH)th(XA)XZCSH

-1.5
45/

th(XA)XRD

45/
See figure 24
-1

Unit
Max

(LR + AR) –16 44/
AR – 14 44/

ns

1
0.5

ns

1.5
0.5
0.5

1
0.5

td(XCOH-XA)
td(XCOHL-XWEL)

1.5
2

td(XCOHL-XWEH)
td(XCOHL-XRNWL)
td(XCOHL-XRNWH)
ten(XD)XWEL
td(XWEL-XD)
th(XA)XZCSH

2
1
0.5

-1
0

1
47/

th(XD)XWE

TW-2
48/

tdis(XD)XRNW

4

See footnotes at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
16236
REV

C

DWG NO.
V62/09624
PAGE 16ns

TABLE I. Electrical performance characteristics - Continued.
Test

Test condition

SymbolDevice type: All2/

1/
Lim its
Min

Unit
Max

EXTERNAL INTERFACE (XINTF) TIMING - Continued
External interface READ switching characteristics (Ready on read, 1 Wait state)
Delay time, XCLKOUT high to zone chip select active lowtd(XCOH-

1ns

XZCSL)

Delay time, XCLKOUT high/low to zone chip select inactive
highDelay time, XCLKOUT high to address valid������ active low
Delay time, XCLKOUT high/low to XRD������ inactive high
Delay time, XCLKOUT high/low to XRD

td(XCOHL--1

0.5

XZCSH)

td(XCOH-XA)
td(XCOHL-

1.5
0.5

XRDL)

td(XCOHL-

-1.5

0.5

XRDH)

Hold time, address valid after zone chip select inactive high������ inactive highHold time, address valid after XRD

th(XA)XZCSHth(XA)XRD

45/
45/

External Interface READ timing requirements (Ready on Re ad, 1 Wait state)
Access time, read data from address validta(A)(LR + AR) – 16
44/
AR – 14 44/������ active low
Access time, read data valid from XRD������ strobe inactive highSetup time, read data valid before XRD������
Hold time, read data valid after XRD inactive highta(XRD)tsu(XD)XRD
th(XD)XRD

Synchronous XREADY timing requirements (Ready on REA D, 1 Waitstate)

Setup time, XREADY (synchronous) low before XCLKOUT
high/low
Hold time, XREADY (synchronous) lowtsu(XRDYsyn

See figure 25

ns

14
0

12

ns

chL)XCOHLth(XRDYsync

6

hL)

Earliest time, XREADY (synchronous) can go high before thesampling XCLKOUT edge.
Setup time, XREADY (synchronous) high before XCLKOUT
high/low
Hold time, XREADY (synchronous) held high after zone chip
select highte(XRDYsync

3

hH)

tsu(XRDYsyn

12chH)XCOHLth(XRDYsync

0hH)XZCSH)

Asynchronous XREADY timing requirements (Ready on RE AD, 1 Waitstate)

Setup time, XREADY (asynchronous) low before XCLKOUT
high/low
Hold time, XREADY (asynchronous) low

See figure 26

tsu(XRDYsyn

11nschL)XCOHLth(XRDYsync

6

hL)

Earliest time, XREADY (asynchronous) can go high before thesampling XCLKOUT edge.
Setup time, XREADY (asynchronous) high before XCLKOUT
high/low
Hold time, XREADY (asynchronous) held high after zone chip
select highte(XRDYsync

3

hH)

tsu(XRDYsyn

11chH)XCOHLth(XRDYsync

0hH)XZCSH)

See footnotes at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
16236
REV

C

DWG NO.
V62/09624
PAGE 17

TABLE I. Electrical performance characteristics - Continued.
Test

Symbol1/

Test condition
Device type: All2/

Lim its

Unit

Min

Max

-1

1
0.5

EXTERNAL INTERFACE (XINTF) TIMING - Continued
External interface WRITE switching characteristics (Ready on read, 1 Wait state)
Delay time, XCLKOUT high to zone chip select active low
Delay time, XCLKOUT high or low to zone chip selectinactive high
Delay time, XCLKOUT high to address valid
Delay time, XCLKOUT high/low to ��������
XWE0, ��������
XWE1 active
low 46/
Delay time, XCLKOUT high/low to ��������
XWE0, ��������
XWE1 high 46/
� low
Delay time, XCLKOUT high to XR/W� highDelay time, XCLKOUT high/low to XR/W��������
Enable time, data bus driven from XWE0, ��������
XWE1 low
Delay time, data valid after ��������
XWE0, ��������
XWE1 active low
Hold time, address valid after zone chip select inactive
high
Hold time, address valid after ��������
XWE0, ��������
XWE1 inactive highMaximum time for DSP to release the data bus after� inactive high
XR/W

td(XCOH-XZCSL)
td(XCOHL-XZCSH)
td(XCOH-XA)

1.5
2

td(XCOHL-XWEL)
td(XCOHL-XWEH)
td(XCOHL-XRNWL)
td(XCOHL-XRNWH)
ten(XD)XWEL
td(XWEL-XD)
th(XA)XZCSH

1
50/
TW-2
48/

tdis(XD)XRNW

4Synchronous XREADY timing requirements (Ready on

WRITE, 1 Waitstate)

Setup time, XREADY (synchronous) low before
XCLKOUT high/low
Hold time, XREADY (synchronous) low
Earliest time, XREADY (synchronous) can go high before
the sampling XCLKOUT edge.
Setup time, XREADY (synchronous) high before
XCLKOUT high/low
Hold time, XREADY (synchronous) held high after zone
chip select hightsu(XRDYsynchL)XCOHL

See figure 27

Setup time, XREADY (asynchronous) low before
XCLKOUT high/low
Hold time, XREADY (asynchronous) low
Earliest time, XREADY (asynchronous) can go highbefore the sampling XCLKOUT edge.
Setup time, XREADY (asynchronous) high before
XCLKOUT high/low
Hold time, XREADY (asynchronous) held high after zone
chip select highSee footnotes at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
A

51/
12

th(XRDYsynchL)te(XRDYsynchH)

6

tsu(XRDYsynchH)XCOHL

12th(XRDYsynchH)XZCSH)

0

tsu(XRDYsynchL)XCOHL

ns

3

state)

52/

See figure 28

11th(XRDYsynchL)te(XRDYsynchH)

6

tsu(XRDYsynchH)XCOHL

11th(XRDYsynchH)XZCSH)

0

ns

3

CAGE CODE
16236
REV

2
1
0.5

-1
0

th(XD)XWE

Asynchronous XREADY timing requirements (Ready on WRITE, 1 Waitns

C

DWG NO.
V62/09624
PAGE 18

TABLE I. Electrical performance characteristics - Continued.
Test

SymbolTest condition
Device type: All2/

1/
Lim its
Min

Max

EXTERNAL INTERFACE (XINTF) TIMING - Continued����������
������������ timing requirements (XCLKOUT = XTIMCLK) 53/ 54/ 55/
𝐗𝐗𝐗𝐗𝐗𝐗𝐗𝐗𝐗𝐗/𝐗𝐗𝐗𝐗𝐗𝐗𝐗𝐗𝐗𝐗𝐗𝐗
���������� low to HI-Z on all address,
Delay time, XHOLD
data, and control���������� low to XHOLDA����������� low
Delay time, XHOLD����������
Delay time, XHOLD high to �����������XHOLDA high���������� high to bus valid
Delay time, XHOLD���������� low to XHOLDA����������� low
Delay time, XHOLD

td(HL-HiZ)

See figure 29

4tc(XTIM) + 30 ns

td(HL-HAL)
td(HH-HAH)
td(HH-BV)
td(HL-HAL)

Delay time, ����������XHOLD high to �����������XHOLDA high���������� high to bus valid
Delay time, XHOLDDC specifications

58/

ns

5tc(XTIM) + 30 ns
3tc(XTIM) + 30 ns
4tc(XTIM) + 30 ns
4tc(XTIM) + 2tc(XCO)+ 30 ns����������/𝐗𝐗𝐗𝐗𝐗𝐗𝐗𝐗𝐗𝐗𝐗𝐗
������������ timing requirements (XCLO UT = ½ XT IMCLK) 53/ 54/ 55/
𝐗𝐗𝐗𝐗𝐗𝐗𝐗𝐗𝐗𝐗
���������� low to HI-Z on all address,
Delay time, XHOLD
data, and control���������� low to XHOLDA����������� low
Delay time, XHOLD

Unittd(HL-HiZ)

See figure 30

4tc(XTIM) + tc(XCO) +

ns

30 ns

td(HL-HAL)

4tc(XTIM) + 2tc(XCO)

td(HH-HAH)
td(HH-BV)

4tc(XTIM) + 30 ns
6tc(XTIM) + 30 ns+ 30 ns

ON CHIP ANALOG TO DIGITAL CONVERTER
ADC electrical characteristics 56/ 57/

Resolution
ADC clock

12
0.001

25

Bits
MHz

±1.5

lsb

Accuracy1 – 12.5 MHz ADC clock(6.25 MSPS)
12.5 – 25 MHz ADC clock(12.5 MSPS)INL ( Integral nonlinearity)±2

DNL (Differential nonlinearity) 59/
Offset error 58/ 60/
Overall gain error with internal reference 58/
61/
Overall gain error with external reference 58/
Channel to channel offset variation
Channel to channel gain variation

±1
±15
±30

TYP
TYP

±30
±4
±4

TYP
TYP
TYP

Analog input
Analog input voltage (ADCINx to ADCLO) 62/
ADCLO
Input capacitance
input leakage current

0
-5

3
5
10

TYP
±5

See footnotes at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
16236
REV

C

DWG NO.
V62/09624
PAGE 19

V
mV
pF
µA

TABLE I. Electrical performance characteristics - Continued.
Test

Internal voltage reference 61/

SymbolTest condition
Device type: All2/

1/
Lim its
Min

Unit
Max

ON CHIP ANALOG TO DIGITAL CONVERTER - Continued
ADC electrical characteristics 56/ 57/

VADCREFP – ADCREFP output voltage at the pin
based on internal reference
VADCREFM – ADCREFM output voltage at the pin
based on internal reference
Voltage difference, ADEREFP – ADCREFM
Temperature coefficient

1.275 TYP

V

0.525 TYP
0.75 TYP
50 TYP

PPM/ºC

External voltage reference 61/
VADCREFIN – External reference voltage input on
ADCREFIN pin 0.2 % or better accurate
reference recommended

ADCREFSEL[15:14] = 11b
ADCREFSEL[15:14] = 10b
ADCREFSEL[15:14] = 01b

1.024 TYP
1.500 TYP
2.048 TYP

V

67.5 TYP

dB

68 TYP-79 TYP
10.9 TYP
83 TYP

Bits
dB

AC specifications
SINAD (100 kHz) signal to noise ration +distortion
SNR (100 kHz) signal to noise ratio
THD (100 kHz) total harmonic distortion
ENOB (100 kHz) effective number of bits
SFDR (100 kHz) spurious free dynamic range
ADC power up delays
Delay time for band gap reference to be stable.
Bits 7 and 6 of the ADCTRL3 register(ADCBGRFDN1/0) must be set to 1 before the
PWDNADC bit is enabled.
Delay time for power down control to be stable.
Bit delay time for band gap reference to bestable. Bits 7 and 6 of the ADCTRL3 registertd(BGR)See figure 31

5td(PWD)20(ADCBGRFDN1/0) must be set to 1 before
PWDNADC bit is enabled. Bit 5 of ADCTRL3
register (PWDNADC) must be set to 1 before
any ADC conversions are initiated.

ms

µs

1

ms

See footnotes at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
16236
REV

C

DWG NO.
V62/09624
PAGE 20

TABLE I. Electrical performance characteristics - Continued.
Test

Sequential sampling mode timing

SymbolTest condition
Device type: All
2/

Sample n1/

Sample n +1

At 25 MHz
ADC
clock,
tc(ADCCLK) =40 ns

Remarks

40 ns
with
Acqps =
0
160 nsAcqps
value = 0 – 15
ADCTRL1{8:11]

ON CHIP ANALOG TO DIGITAL CONVERTER - Continued

Delay time from event trigger
to sampling
Sample/Hold width/Acquisition
widthtd(SH)

See figure 32

2.5tc(ADCCLK)tSH(1 + Acqps) *tc(ADCCLK)

Delay time for first result toappear in Result register
Delay time for successive
results to appear in Result
registertd(schx_n)4tc(ADCCLK)

td(schx_n + 1)

(2 + Acqps) *tc(ADCCLK)

80 ns

Simultaneous sampling mode timing
Delay time from event trigger
to sampling
Sample/Hold width/Acquisition
width
Delay time for first result toappear in Result register
Delay time for first result toappear in Result register
Delay time for successive
results to appear in Result
register
Delay time for successive
results to appear in Result
registertd(SH)

See figure 33

2.5tc(ADCCLK)tSH(1 + Acqps) *tc(ADCCLK)

td(schA0_n)

4tc(ADCCLK)

40 ns
with
Acqps =
0
160 nstd(schB0_n)4tc(ADCCLK)

200 nstd(schA0_n + 1)

(3 + Acqps) *tc(ADCCLK)

120 nstd(schB0_n + 1)

(3 + Acqps) *tc(ADCCLK)

120 nsAcqps
value = 0 – 15
ADCTRL1{8:11]

See footnotes at end of table.

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TABLE I. Electrical performance characteristics - Continued.
No

Test

Symbol1/

Test condition
Device type: All2/

Lim its
Min

Unit
Max

MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMINGMcBSP timing requirements 64/ 65/
McBSP module clock (CLKG, CLKX,

See figure

34 and 35

1

CLKR) range

kHz
25

McBSP module cysle time(CLKG,

66/

40

CLKX, CLKR) range

ns
1

M11

Cycle time, CLKR/X

tc(CKRX)

CLKR/X ext

2P

M12

Pulse duration, CLKR/X high or
CLKR/X low

tw(CKRX)

CLKR/X ext

P-7

M13

Rise time, CLKR/X

tr(CKRX)

CLKR/X ext

7

M14

Fall time, CLKR/X

tf(CKRX)

CLKR/X ext

7

M15

Setup time, external FSR high before

tsu(FRH-CKRL)CLKR int18

CLKR ext

2

CLKR int0

CLKR ext

6

CLKR int18

CLKR ext

2

CLKR int0

CLKR ext

6

CLKR int18

CLKR ext

2

CLKR int0

CLKR ext

6

CLKR low
M16

Hold time, external FSR high afterth(CKRL-FRH)

CLKR low
M17

Setup time, DR valid before CLKR lowtsu(DRV-CKRL)

M18

Hold time, DR valid after CLKR low

th(CKRL-DRV)

M19

Setup time, external FSX high before

tsu(FXH-CKXL)CLKX low
M20

Hold time, external FSX high afterMHz

th(CKXL-FXH)

CLKX lowms
ns

See footnotes at end of table.

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TABLE I. Electrical performance characteristics - Continued.
No

Test

1/

Test condition
Device type: All
2/

Symbol

Lim its
Min

Unit
Max

MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING - Continued
McBSP switching characteristics 64/ 67/
M1
M2
M3
M4

Cycle time, CLKR/X
Pulse duration, CLKR/X highPulse duration, CLKR/X low
Delay time, CLKR high to internal FSR validtc(CKRX)tw(CKRXH)
tw(CKRXL)
td(CKRH-

See figure
34 and 35

CLKR/X int
CLKR/X int
CLKR/X int
CLKR int

2P
D-5 68/C-5 68/0ns
D+5 68/
D+5 68/4

CLKR ext
CLKX int

3
0

27
4

CLKX ext
CLKX int

3

27
8

FRV)

M5

Delay time, CLKX high to internal FSX validtd(CKXHFXV)

M6Disable time, CLKX high to DX hightd(CKXH-

M7

impedance following last data bit
Delay time, CLKX high to DX valid
This applies to all bits except the first bit transDXHZ)

CLKX ext
CLKX int
CLKX ext

14928

CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext

814
P+8
P + 14
0
6

DXENA = 1

CLKX int
CLKX ext

P
P+6

DXENA = 0

CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext

td(CKXHDXV)Delay time, CLKX high to DX valid

DXENA = 0

Only applies to first bit transmitted when in Data
Delay 1 or 2 (XDATDLY = 01b or 10b) modes
Enable time, CLKX high to DX driven

DXENA = 1

M8

DXENA = 0ten(CKXHDX)

M9Only applies to first bit transmitted whenin Data Delay 1 or 2 (XDATDLY = 01b or 10b)
modes
Delay time, FSX high to DX validtd(FXH-DXV)

M10

Only applies to first bit transmitted whenin Data Delay 0 (XDATDLY = 00b) modes
Enable time, FSX high to DX driven

DXENA = 1
ten(FXH-DX)

Only applies to first bit transmitted whenin Data Delay 0 (XDATDLY = 00b) modes

DXENA = 0
DXENA = 1

814
P+8P + 140
6
P
P+6

See footnotes at end of table.

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TABLE I. Electrical performance characteristics - Continued.
No

Test

Test condition
Device type: All
2/

Symbol1/
Lim its

Unit

Mas terMin

Sla ve
Max

Min

Max

MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING - Continued
McBSP as SPI Master or Slave timing requirements (CLKSTP = 10 b, CLKXP = 0)M30
30
8P - 10
Setup time, DR valid before
tsu(DRV-CKXL) See figure 36
CLKX low
M31

Hold time, DR valid after CLKX
low

1th(CKXL-DRV)

M32

Setup time, FSX low before
tsu(BFXL-CKXH)
CLKX high
M33
Cycle time, CLKX
tc(CKX)
2P 67/
McBSP as SPI Master or Slave switching characteristics (CLKSTP = 10 b, CLKXP = 0)

8P - 10
8P + 10
16P

M24

Hold time, FSX low after CLKX
lowth(CKXL-FXL)

M25

Delay time, FSX low to CLKX
high

td(FXL-CKXH)P

M28Disable time, DX high impedance
following last data bit from FSX
lowtdis(FXH-DXHZ)

6

6P + 6

M29

Delay time, FSX low to DX validtd(FXL-DXV)

6

4P + 6

2P 67/

See figure 36

ns

ns

McBSP as SPI Master or Slave switching characteristics (CLKSTP = 10 b, CLKXP = 0)
M39

Setup time, DR valid before
CLKX hightsu(DRV-CKXH)

M40

Hold time, DR valid after CLKX
highth(CKXH-DRV)

See figure 37

30

8P - 101

8P - 10

M41

Setup time, FSX low before
tsu(FXL-CKXH)
CLKX high
M42
Cycle time, CLKX
tc(CKX)
2P 67/
McBSP as SPI Master or Slave switching characteristics (CLKSTP = 11 b, CLKXP = 0)

16P + 10
16P

M34

Hold time, FSX low after CLKX
lowth(CKXL-FXL)

M35

Delay time, FSX low to CLKX
high

td(FXL-CKXH)

2P 67/

M37

Disable time, DX high impedance
following last data bit from FSX
lowtdis(CKXL-

P+6

7P + 6

Delay time, FSX low to DX validtd(FXL-DXV)

6

4P + 6M38

See figure 37

P

ns

DXHZ)

See footnotes at end of table.

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PAGE 24TABLE I. Electrical performance characteristics - Continued.
No

Test

Test condition
Device type: All
2/

Symbol1/
Lim its

Mas terMin

Max

MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING - Continued
McBSP as SPI Master or Slave timing requirements (CLKSTP = 10 b, CLKXP = 1)
M49
30
Setup time, DR valid before
tsu(DRV-CKXH) See figure 38
CLKX high
M50

Hold time, DR valid after CLKX
high

Unit

1

th(CKXH-DRV)

M51

Setup time, FSX low before
tsu(BFXL-CKXL)CLKX low
M52
Cycle time, CLKX
tc(CKX)
2P 67/
McBSP as SPI Master or Slave switching characteristics (CLKSTP = 10 b, CLKXP = 0)

Sla veMin

Max

8P - 10
8P - 10
8P + 1016P

2P 67/

See figure 38

ns

ns

M43

Hold time, FSX low after CLKX
highth(CKXH-FXL)

M44

Delay time, FSX low to CLKX lowtd(FXL-CKXL)P

M47Disable time, DX high impedance
following last data bit from FSX
hightdis(FXH-DXHZ)

6

6P + 6

M48

Delay time, FSX low to DX validtd(FXL-DXV)

6

4P + 630

8P - 101

8P - 10

McBSP as SPI Master or Slave timing requirements (CLKSTP = 11 b, CLKXP = 1)
M58

Setup time, DR valid before
CLKX lowtsu(DRV-CKXL)

M59

Hold time, DR valid after CLKX
lowth(CKXL-DRV)

M60

Setup time, FSX low before
CLKX low
Cycle time, CLKX

tsu(FXL-CKXL)

M61

See figure 39ns

16P + 10tc(CKX)

2P 67/

16P

McBSP as SPI Master or Slave switching characteristics (CLKSTP = 11 b, CLKXP = 0)
See figure 39

P

ns

M53

Hold time, FSX low after CLKX
highth(CKXH-FXL)

M54

Delay time, FSX low to CLKX lowtd(FXL-CKXL)

2P 67/

M56

Disable time, DX high impedance
following last data bit from FSX
hightdis(CKXH-

P+6

7P + 6

Delay time, FSX low to DX validtd(FXL-DXV)

6

4P + 6

M57

DXHZ)

See footnotes at end of table.

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PAGE 25TABLE I. Electrical performance characteristics - Continued.
Test

SymbolFlash endurance for A and S temperature materialFlash endurance for the array (write/erase cycles)

1/

Test condition
Device type: All
2/

Min

100

Nf

0°C to +85°C (ambient)

NOTP

0°C to +85°C (ambient)Nf-40°C to +125°C (ambient)

OTP endurance for the array (write cycles)Flash parameters at 150 MHz SYSCLKOUT

NOTP-40°C to +125°C (ambient)

Erase time

16 Bit Word
32K Sector
16K Sector
32K Sector
16K Sector

VDD3VFL current consumption during theErase/Program cycle
VDD current consumption during theErase/Program cycle
VDDIO current consumption during theErase/Program cycle
Flash/OTP access timing
Paged Flash access time
Random access time
OTP access time

Unit
Max

FLASH TIMINGOTP endurance for the array (write cycles)Flash endurance for Q temperature materialFlash endurance for the array (write/erase cycles)

Program time

LimitsIDD3VFLP
70/
IDDP 70/

Erase
Program

IDDIOP 70/

cycles
1

100

write
cycles1

write

50 TYP
1000 TYP
500 TYP
11 TYP
11 TYP

µs
ms
ms
s
s

75 TYP
35 TYP
180 TYP

mA

20 TYPta(fp)
ta(fr)

37
37
60

ta(OTP)ns

See footnotes at end of table.

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TABLE I. Electrical performance characteristics - Continued.
1/

2/
3/
4/
5/

6/
7/
8/

9/
10/
11/
12/
13/
14/
15/
16/
17/
18/
19/
20/
21/
22/
23/
24/
25/

26/
27/
28/
29/
30/
31/

Testing and other quality control techniques are used to the extent deemed necessary to assure product performance overthe specified temperature range. Product may not necessarily be tested across the full temperature range and allparameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured bycharacterization and/or design.
Over operating free-air temperature range (unless otherwise noted).
When the ident/ical code is run off SARAM, IDD would increase as the code operates with zero wait states.
IDDIO current is dependent on the electrical loading on the I/O pins.
The IDD3VFL current indicated in this table is the flash read current and does not include additional current for erase/write
operations. During flash programming, extra current is drawn from the VDD and VDD3VFL rails, as indicated in manufacturer
data. If the user application involves onboard flash programming, this extra current must be taken into account whilearchitecting the power supply stage.
IDDA18 includes current into VDD1A18 and VDD2A18 pins. In order to realize the IDDA18 currents shown for IDLE, STANDBY, and
HALT, clock to the ADC module must be turned off explicitly by writing to the PCLKCR0 register.
IDDA33 includes current into VDDA2 and VDDAIO pins.
The following done in a loop:• Data is continuously transmitted out of the SCI-A, SCI-B, SPI-A, McBSP-A, and eCAN-A ports.
• Multiplication/addition operations are performed.
• Watchdog is reset.
• ADC is performing continuous conversion. Data is transferred to SARAM through the DMA.
• 32 bit read/write of the XINTF is performed.
• GPIO10 is toggled.
HALT mode IDD currents will increase with temperature in a non-linear fashion.
If a quartz crystal or ceramic resonator is used as the clock source, the HALT mode shuts down the internal oscillator.
The TYP numbers are applicable over room temperature and nominal voltage. MAX numbers are at 125ºC, and MAX
voltage (VDD = 2.0 V; VDDIO, VDD3VFL, VDDA = 3.6 V).
This also applies to the X1 pin if a 1.9 V oscillator is used.
Lower LSPCLK and HSPCLK will reduce device power consumption.
This also applies to the X1 pin if a 1.8 V oscillator is used.
This applies to the X1 pin also.
A load of 40 pF is assumed for these parameters.
H = 0.5tc(XCO).
OSCCLK is either the output of the on chip oscillator or the output from an external oscillator.
In addition to the tw(RSL1) requirement, �����XRS has to be low at least for 1 ms after VDD reaches 1.5 V.
Dependent on crystal/resonator and board design.
“n” represents the number of qualification samples as defined by GPxQSELn register.
For tw(GPI), pulse width is measured from VIL to VIL for an active low and VIH to VIH for an active high signal.
This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR(triggered by the wake up) signal involves additional latency.
QUALSTDBY is a 6 bit field in the LPMCR0 register.
Maximum MEP step size is based on worst case process, maximum temperature and maximum voltage. MEP step size will
increase with low voltage and high temperature and decrease with voltage and cold temperature. Applications that use the
HRPWM feature should use MEP Scale Factor Optimizer (SFO) estimation software functions. See manufacturer software
libraries for more details. SFO function help to estimate the number of MEP steps per SYSCLKOUT period dynamically while
the HRPWM is in operation.
This timing is applicable to any GPIO pin configured for ADCSOC functionality.
The MASTER/SLAVE bit (SPITL.2) is set and the CLOCK PHASE bit (SPICTL.3) is cleared.
tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
tc(LCO) = LSPCLK cycle time
Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25 MHz MAX, master mode receive 12.5 MHz MAX
Slave mode transmit 12.5 MHz MAX, slave mode receive 12.5 MHz MAX.
The active edge of the SPICLK signal referenced is controlled by the clock polarity bit (SPICCR.6).

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TABLE I. Electrical performance characteristics - Continued.
32/
33/
34/
35/
36/
37/
38/
39/
40/
41/
42/
43/
44/
45/
46/
47/
48/
49/

50/
51/

52/

53/
54/
55/
56/
57/
58/

0.5tc(SPC)M - 10
0.5tc(SPC)M
0.5tc(SPC)M – 0.5tc(LCO) - 10
0.5tc(SPC)M – 0.5tc(LCO)
0.5tc(SPC)M + 0.5tc(LCO) -10
0.5tc(SPC)M + 0.5tc(LCO)
0.25tc(SPC)M – 10
The MASTER/SLAVE bit (SPITL.2) is set and the CLOCK PHASE bit (SPICTL.3) is set.
The MASTER/SLAVE bit (SPITL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
The MASTER/SLAVE bit (SPITL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is set.
tc(XTIM) – Cycle time, XTIMCLKWS refers to the number of wait states inserted by hardware when using XREADY. If the zone is configured to ignore
XREADY (USEREADY = 0), then WS = 0.
LR = Lead period, read access. AR = Active period, read access.
During inactive cycles, the XINTF address bus always holds the last address put out on the bus except XA0, which remains
high. This includes alignment cycles.
��������
XWE1 is used in 32 bit data bus mode only. In 16 bit mode, this signal is XA0.
During inactive cycles, the XINTF address bus will always hold the last address put out on the bus except XA0, which
remains high.
TW = Trail period, write access.
The first XREADY (synchronous) sample occurs with respect to E in figure 25:
E = (XREADY + XRDACTIVE) tc(XTIM)
When first sampled, if XREADY (synchronous) is found to be high. then the access will finish. If XREADY (synchronous) isfound to be low, it is sampled again each tc(XTIM) until it is found to be high.
For each sample (n) the setup time (F) with respect to the beginning of the access can be calculated as:
F = (XREADY + XRDACTIVE + n -1) tc(XTIM) – tsu(XRDYsynchL)XCOHL
where n is the sample number: n = 1, 2, 3 and so forth.
During inactive cycles, the XINTF address bus will always hold the last address put out on the bus except XA0, which
remains high. This include alignment cycles.
The first XREADY (synchronous) sample occurs with respect to E in figure 27:
E = (XWRLEAD + XWRACTIVE) tc(XTIM)
When first sampled, if XREADY (synchronous) is found to be high. then the access will finish. If XREADY (synchronous) isfound to be low, it is sampled again each tc(XTIM) until it is found to be high.
For each sample, setup time from the beginning of the access can be calculated as:
F = (XWRLEAD + XWRDACTIVE + n -1) tc(XTIM) – tsu(XRDYsynchL)XCOHL
where n is the sample number: n = 1, 2, 3 and so forth.
The first XREADY (synchronous) sample occurs with respect to E in figure 28:
E = (XWRLEAD + XWRACTIVE -2) tc(XTIM)
When first sampled, if XREADY (asynchronous) is high. then the access will complete. If XREADY (asynchronous) is low, it
is sampled again each tc(XTIM) until it is high.
For each sample, setup time from the beginning of the access can be calculated as:
F = (XWRLEAD + XWRDACTIVE + n -3) tc(XTIM) – tsu(XRDYsynchL)XCOHL
where n is the sample number: n = 1, 2, 3 and so forth.
When a low signal is detected on ����������XHOLD, all pending XINTF accesses will be completed before the bus is placed in a highimpedance state.
���������� is latched on the rising edge of XTIMCLK.
The state of XHOLD����������
After XHOLD is detected low or high, all bus transitions and �����������XHOLDA transitions occur with respect to the rising edge of
XCLKOUT. Thus, for this mode where XCLKOUT = ½ XTIMCLK, the transitions can occur up to 1 XTIMCLK cycle earlier
than the maximum value specified.
Tested at 25 MHz ADCCLK.
All voltages listed in this table are with respect to VSSA2.
ADC parameters for gain error and offset error are only specified if the ADC calibration routine is executed from the Boot
ROM. See manufacturer data for more information.

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TABLE I. Electrical performance characteristics - Continued.
59/
60/
61/

62/
63/
64/
65/
66/
67/
68/
69/
70/
71/

Manufacturer specifies that the ADC will have no missing codes.
1 LSB has the weight value of 3.0/4096 = 0.732 mV.
A single internal/external band gap reference sources both ADCREFM signals, and hence, these voltages track together.
The ADC converter uses the difference between these two as its reference. The total gain error listed for the internalreference is inclusive of the movement of the internal band gap over temperature. Gain error over temperature for theexternal reference option will depend on the temperature profile of the source used.
Voltages above VDDA + 0.3 V or below VSS – 0.3 V applied to an analog input pin may temporarily affect the conversion ofanother pin. To avoid this, the analog inputs should be kept within these limits.
Manufacturer recommends using high precision external reference.
Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any signals is inverted, then the timing references of thatsignal are also inverted.
CLKSRG
2P = 1/CLKG in ns. CLKG is the output of sample rate generator mux. CLKG =CLKSRG can be LSPCLK,(1 + CLKGDV)
CLKX, CLKR as source. CLKSRG ≤ (SYSCLKOUT/2). McBSP performance is limited by I/O buffer switching speed.
Internal clock prescalers must be adjusted such that the McBSP clock (CLKG, CLKX, CLKR) speeds are not greater than the
I/O buffer speed limit (25 MHz).
2P = 1/CLKG in ns.
C = CLKRX low pulse width = P
D = CLKRX high pulse width = P
Write/erase operation outside of the temperature ranges indicated are not specified and may affect the endurance numbers.
Typical parameters as seen at room temperature including function call overhead, with all peripherals off.
Page and random wait-state must be ≥ 1.

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PAGE 29Case outline X

SymbolA
A1
A2bMillimeter
Min
Max
1.40
0.85
0.95
0.35
0.45
0.45
0.55

Symbol
e
e1
D/E
D1/E1

Milli meter
Min
Max
0.40 TYP
0.80 BSC
1.90
12.10
10.40 TYP

Notes:
1. All linear dimensions are in millimeters.
2. This drawing is subject to change without notice.

FIGURE 1. Case outlines.

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PAGE 30

Case outline Y

SymbolA
A1
A2bc

Millimeter
Min
Max
1.60
1.35
1.45
0.25
0.17
0.27
0.13 NOM

SymbolMilli meter
Min
Max
0.500 BSC
25.80
26.20
23.80
24.20
10.40 BSC
0.45
0.75

e
D/E
D1/E1
D2/E2
L

Notes:
1. All linear dimensions are in millimeters.
2. This drawing is subject to change without notice.
3. Body dimensions do nit include mold flash or protrusion.
4. This package is designed to be soldered to a thermal pad on the board. Refer to the manufacturer for more information.
5. Fall within JEDEC MS-026
FIGURE 1. Case outlines - Continued.

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Case outline X

FIGURE 2. Terminal connections.

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Case outline X – Continued.

FIGURE 2. Terminal connections - Continued.

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Case outline X – Continued.

FIGURE 2. Terminal connections - Continued.

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Case outline X – Continued.

FIGURE 2. Terminal connections - Continued.

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Case outline Y
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44

Signal Name
GPIO30/CANRXA/XA18
GPIO29/SCITXDA/XA19
VSS
VDD
GPIO0/EPWM1A
GPIO/EPWM1B/ECAP6/MFSRBGPIO2/EPWM2A
VSS
VDDIO
GPIO3/EPWM2B/ECAP5/MCLKRB
GPIO/EPWM3A
GPIO/EPWM3B/MFSRA/ECAP1
GPIO6/WM4A/EPWMSYNCI/EPWMSYNCO
VSSVDD
GPIO7/EPWM4B/MCLKRA/ECAP2���������������
GPIO8/EPWM5A/CANTXB/ADCSOCAOGPIO9/EPWM5B/SCITXDB/ECAP3���������������
GPIO10/EPWM6A/CANRXB/ADCSOCBO
GPIO11/EPWM6B/SCIRXDB/ECAP4�����/CANTXB/MDXBGPIO12/TZ1VSS
VDD�����/CANRXB/MDRB
GPIO13/TZ2�����/XHOLD����������/SCITXDB/MCLKXBGPIO14/TZ3�����������/SCIRXDB/MFSXB�����/XHOLDA
GPIO15/TZ4
�����
GPIO16/SPISIMOA/CANTXB/TZ5
�����
GPIO17/SPISOMIA/CANRXB/TZ6
VDD
VSS
VDD1A18
VSS1AGND
VSSA2
VDDA2
ADCINA7ADCINA6ADCINA5ADCINA4ADCINA3ADCINA2
ADCINA1
ADCINA0ADCLOVSSAIO

Pin No.
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88

Signal NameVDDAIOADCINB0
ADCINB1
ADCINB2
ADCINB3
ADCINB4ADCINB5ADCINB6ADCINB7
ADCREFIN
ADCREFMADCREFPADCRESEXTVSSA2GNDVDD2A18VSS
VDD
GPIO18/SPICLKA/SCITXDB/CANRXA�����������/SCIRXDB/CANTXAGPIO19/SPISTEAGPIO20/EQEP1A/MDXA/CANTXBGPIO21/EQEP1B/MDRA/CANRXBGPIO22/EQEP1S/MCLKXA/SCITXDBGPIO23/EQEP1/MFSXA/SCIRSDBGPIO24/ECAP1/EQEP2A/MDXBGPIO25/ECAP2/EQEP2B/MDRB
VSS
VDDIO
GPIO26/ECAP3/EQEP2I/MCLKXBGPIO27/ECAP4/EQEP2S/MFSXB���������������
GPIO32/SDAA/EPWMSYNCI/ADCSOCAO���������������
GPIO33/SCLA/EPWMSYNCO/ADCSOCBO
TDI
TDO�������
TRST
TMS
XRS
TEST1
TEST2
VSS
VDD3VFL
EMU0
EMU1
TCK
GPIO48/ECAP5/XD31

FIGURE 2. Terminal connections - Continued.

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Pin No.
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132

Signal Name
GPIO49/ECAP6/XD30
GPIO50/EQEP1A/XD29
GPIO51/EQEP1B/XD28
VSS
VDDIO
GPIO52/EQEP1S/XD27
GPIO53/EQEP1I/XD26
GPIO54/SPISIMOA/XD25
GPIO55/SPISOMIA/XD24
GPIO56/SPICLKA/XD23�����������/XD22
GPIO57/SPISTEAGPIO58/MCLKRA/XD21
VDD
X2
VSS
X1
XCLKIN
VSS
VDDIO
VSS
VDD
GPIO59/MFSRA/XD20
GPIO60/MCLKRB/XD19
GPIO61/MFSRB/XD18
GPIO62/SCIRXDC/XD17
GPIO63/SCITXDC/XD16
GPIO64/XD15
GPIO65/XD14
VDD
VSSGPIO66/XD13
VSS
VDDIO
GPIO67/XD12
GPIO68/XD11
GPIO69/XD10
VSS
VDDGPIO70/XD9
GPIO71/XD8
GPIO72/XD7
GPIO73/XD6
GPIO74/XD5
GPIO75/XD4Pin No.
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176

Signal Name
GPIO76/XD3
GPIO77/XD2
GPIO78/XD1
GPIO79/XD0��������
GPIO38/XWE0
XCLKOUTVDD
VSS��������
GPIO28/SCIRXDA/XZCS6
GPIO34/ECAP1/XREADY
VDDIO
VSS
��������
GPIO36/SCIRXDA/XZCS0VDDVSSGPIO35/SCITXDA/XR/W������
XRD
��������
GPIO37/ECAP2/XZCS7
��������
GPIO40/XA0/XWE1
GPIO41/XA1
GPIO42/XA2
VDD
VSS
GPIO43/XA3
GPIO44/XA4
GPIO45/XA5
VDDIO
VSS
GPIO46/XA6
GPIO47/XA7
GPIO80/XA8
GPIO81/XA9
GPIO82/XA10
VSS
VDD
GPIO83/XA11
GPIO84/XA12
VDDIO
VSS
GPIO85/XA13
GPIO86/XA14
GPIO87/XA15
GPIO39/XA16
GPIO31/CANTXA/XA17

FIGURE 2. Terminal connections - Continued.

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FIGURE 3. Functional block diagram.

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NOTES:
1. The relationship of XCLKIN to XCLKOUT depends on the device factor chosen. The waveform relationship shown isintended to illustrate the timing parameters only and may differ based on actual configuration.
2. XCLKOUT configured to reflect SYSCLKOUT.

FIGURE 4. Timing waveforms.

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NOTES:
1. Upon power up, SYSCLKOUT is OSCCLK/4. Sine both the XTIMCLK and CLKMODE bits in the XINTCNF2 register comeup with a reset state of 1, SYSCLKOUT is further divided by 4 before it appear at XCLKOUT. This explains why
XCLKOUT = OSCCLK/16 during this phase. Subsequently, boot ROM changes SYSCLKOUT to OSCCLK/2. Because the
XTIMCLK register is unchanged by the boot ROM, XCLKOUT is OSCCLK/8 during this phase.
2. After reset, the boot ROM code samples Boot mode pins. Based on the status of the Boot mode pin, the boot code
branches to destination memory or boot code function. If boot ROM code executes after power on conditions (in debugger
environment), the boot code execution time is based on the current SYSCLKOUT speed. The SYSCLKOUT will be basedon user environment and could be with or without PLL enabled.
3. See manufacturer data for requirements to ensure a high impedance state for GPIO pins during power up.

FIGURE 5. Timing waveforms.

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PAGE 40NOTES:
1. After reset, the boot ROM code samples Boot mode pins. Based on the status of the Boot mode pin, the boot code
branches to destination memory or boot code function. If boot ROM code executes after power on conditions (in debugger
environment), the boot code execution time is based on the current SYSCLKOUT speed. The SYSCLKOUT will be basedon user environment and could be with or without PLL enabled.
FIGURE 6. Timing waveforms.

FIGURE 7. Timing waveforms.

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FIGURE 8. Timing waveforms.

NOTES:
1. This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It canvary from 00 to 0xFF. If QUALPRD = 00, then the sampling period is 1 SYSCLKOUT cycle. For any other value “n” thequalification sampling period in 2n SYSCLKOUT (i.e., at every 2 n SYSCLKOUT cycles, the GPIO will be sampled.
2. The qualification period selected via the GPxCTRL register applies to groups of 8 GPIO pins.
3. The qualification block can take either three or six samples. The GPxQSELn register selects which sample mode is used.
4. In the example shown, for the qualifier to detect the change, the input should be stable for 10 SYSCLKOUT cycles orgreater. In other words, the input should be stable for ( 5 x QUALPRD x 2)SYSCLKOUT cycles. This would ensure 5
sampling periods for detection to occur. Since external signals are driven asynchronously, an 13 SYSCLKOUT wide pulse
ensures reliable recognition.
FIGURE 9. Timing waveforms.

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NOTES:
1. WAKE INT can be any enabled interrupt, ����������WDINT, XNMI, �����XRS.
FIGURE 11. Timing waveforms.

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NOTES:
1
IDLE instruction is executed to put the device into STANDBY mode.
2
The PLL block responds to the STANDBY signal. SYSCLKOUT is held for the number of cycles indicated below before
being turned off:•
16 cycles, when DIVSEL = 00 or 01•
32 cycles, when DIVSEL = 10•
64 cycles, when DUVSELK = 11This delay enables the CPU pipeline and any other pending operations to flush properly. If an access to XINTF isin progress and its access time is longer than this number then it will fail. = it is recommended to enter STANDBY
mode from SARAM without an XINTF access in progress.
3
Clock to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in
STANDBY mode.
4
The external wake up signal is driven active.
5
After a latency period, the STANDBY mode is exited.
6
Normal execution resumes. The device will respond to the interrupt (if enabled).

FIGURE 12. Timing waveforms.

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1
2

3
4

5
6
7

IDLE instruction is executed to put the device into HALT mode.
The PLL block responds to the HALT signal. SYSCLKOUT is held for the number of cycles indicated below before osciiator
is turned off and the CLKIN to the score is stopped:•
16 cycles, when DIVSEL = 00 or 01•
32 cycles, when DIVSEL = 10•
64 cycles, when DUVSELK = 11This delay enables the CPU pipeline and any other pending operations to flush properly. If an access to XINTF isin progress and its access time is longer than this number then it will fail. = it is recommended to enter HALT
mode from SARAM without an XINTF access in progress.
Clock to the peripherals are turned off and the PLL is shut down. If a quartz crystal or ceramic resonator is used as theclock source, the internal oscillator is shut down as well. The device is now in HALT mode and consumes absolute
minimum power.
When the GPIOn pin (using to bring the device out of HALT) is driven low, the oscillator is turned on and the oscillator wakeup sequence is initiated. The GPIO pin should be driven high only after oscillator has stabilized. This enables the provisionof a clean clock signal during the PLL lock sequence. Since the falling edge of the GPIO pin asynchronously begins thewake up process, care should be taken to maintain a low noise environment prior to entering and during HALT mode..
Once the oscillator has stabilized, the PLL lock sequence is initiated, which takes 131,072 OSCCLK (X1/X2 or X1 or
XCLKIN) cycles. Note that these 131,072 clock cycles are applicable even when the PLL is disabled (i.e., code execution
will be delayed by this duration even when the PLL is disabled)..
Clocks to the score and peripherals are enabled. The HALT mode is now exited. The device will respond to the interrupt (ifenabled), after a latency.
Normal operation resumes.

FIGURE 13. Timing waveforms.

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NOTES:�����, TZ6�����, TZ2�����, TZ3�����, �����
�����
1. ����
TZ – TZ1
TZ4, TZ5���� is taken high depends on the PWM.
2. PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ
FIGURE 14. Timing waveforms.

FIGURE 15. Timing waveforms.

FIGURE 16. Timing waveforms.

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NOTES:
1. In the master mode, ���������SPISTE goes active 0.5tc(SPC) (minimum) before valid SPI clock edge. On the trailing end of the word,��������� stays active
the ���������SPISTE will go inactive 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit, except that SPISTE
between back to back transmit words in both FIFO and non FIFO modes.
FIGURE 17. Timing waveforms.

NOTES:
1. In the master mode, ���������SPISTE goes active 0.5tc(SPC) (minimum) before valid SPI clock edge. On the trailing end of the word,��������� stays active
the ���������SPISTE will go inactive 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit, except that SPISTE
between back to back transmit words in both FIFO and non FIFO modes.
FIGURE 18. Timing waveforms.

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NOTES:
1. In the slave mode, ���������SPISTE signal should be asserted low at least 0.5tc(SPC) (minimum) before the valid SPI clock edge andremain low for at least 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit.
FIGURE 19. Timing waveforms.

NOTES:
1. In the slave mode, ���������SPISTE signal should be asserted low at least 0.5tc(SPC) (minimum) before the valid SPI clock edge andremain low for at least 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit.
FIGURE 20. Timing waveforms.

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FIGURE 21. Timing waveforms.

FIGURE 22. Timing waveforms.

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NOTES:
1. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an alignment
cycle before an access to meet this requirement.
2. During alignment cycles, all signals transition to their inactive state.
3. XA[0:19] holds the last address put on the bus during inactive cycles, including alignment cycles except XA0, which remainshigh.
4. Timing are also relevant for XCLKOUT = ½ XTIMCLK and CLKOUT = ¼ XTIMCLK.
5. ��������
XWE1 is used in 32 bit data bus mode. In 16 bit mode, this signal is XA0.
6. For USEREADY = 0, the external XREADY input signal is ignored.

FIGURE 23. Timing waveforms.

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NOTES:
1. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an alignment
cycle before an access to meet this requirement.
2. During alignment cycles, all signals transition to their inactive state.
3. XA[0:19] holds the last address put on the bus during inactive cycles, including alignment cycles except XA0, which remainshigh.
4. Timing are also relevant for XCLKOUT = ½ XTIMCLK and CLKOUT = ¼ XTIMCLK.
5. ��������
XWE1 is used in 32 bit data bus mode. In 16 bit mode, this signal is XA0.
6. For USEREADY = 0, the external XREADY input signal is ignored.

FIGURE 24. Timing waveforms.

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NOTES:
1. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an alignment
cycle before an access to meet this requirement.
2. During alignment cycles, all signals transition to their inactive state.
3. During inactive cycles, the XTINTF address bus always holds the last address put out on the bus except XA0, which remainhigh. This includes alignment cycles.
4. Timing are also relevant for XCLKOUT = ½ XTIMCLK and CLKOUT = ¼ XTIMCLK.
5. ��������
XWE1 is valid only in 32 bit data bus mode. In 16 bit mode, this signal is XA0.
6. For each sample, set up time from the beginning of the access can be calculated as:
D = (XRDLEAD + XRDACTIVE + n -1) tc(XTIM) – tsu(XRDYsynchL)XCOHL where n is the sample number: n = 1, 2, 3, and soforth.
7. Reference for the first sample is with respect to this point: F = (XRDLEAD + XRDACTIVE) tc(XTIM).

FIGURE 25. Timing waveforms.

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NOTES:
1. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an alignment
cycle before an access to meet this requirement.
2. During alignment cycles, all signals transition to their inactive state.
3. During inactive cycles, the XTINTF address bus always holds the last address put out on the bus except XA0, which remainhigh. This includes alignment cycles.
4. Timing are also relevant for XCLKOUT = ½ XTIMCLK and CLKOUT = ¼ XTIMCLK.
5. ��������
XWE1 is valid only in 32 bit data bus mode. In 16 bit mode, this signal is XA0.
6. For each sample, set up time from the beginning of the access (E) can be calculated as:
E = (XRDLEAD + XRDACTIVE + n -3) tc(XTIM) – tsu(XRDYsynchL)XCOHL where n is the sample number: n = 1, 2, 3, and soforth.
7. Reference for the first sample is with respect to this point: F = (XRDLEAD + XRDACTIVE - 2) tc(XTIM).
FIGURE 26. Timing waveforms.

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NOTES:
1. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an alignment
cycle before an access to meet this requirement.
2. During alignment cycles, all signals transition to their inactive state.
3. During inactive cycles, the XTINTF address bus always holds the last address put out on the bus except XA0, which remainhigh. This includes alignment cycles.
4. ��������
XWE1 is used in 32 bit data bus mode only. In 16 bit mode, this signal is XA0.
5. For each sample, set up time from the beginning of the access (E) can be calculated as:
E = (XWRLEAD + XWRACTIVE + n -1) tc(XTIM) – tsu(XRDYsynchL)XCOHL where n is the sample number: n = 1, 2, 3, and soforth.
6. Reference for the first sample is with respect to this point: F = (XWRLEAD + XWRACTIVE) tc(XTIM).
FIGURE 27. Timing waveforms.

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PAGE 54NOTES:
1. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an alignment
cycle before an access to meet this requirement.
2. During alignment cycles, all signals transition to their inactive state.
3. During inactive cycles, the XTINTF address bus always holds the last address put out on the bus except XA0, which remainhigh. This includes alignment cycles.
4. ��������
XWE1 is used in 32 bit data bus mode only. In 16 bit mode, this signal is XA0.
5. For each sample, set up time from the beginning of the access (E) can be calculated as:
E = (XWRLEAD + XWRACTIVE + n -3) tc(XTIM) – tsu(XRDYsynchL)XCOHL where n is the sample number: n = 1, 2, 3, and soforth.
6. Reference for the first sample is with respect to this point: F = (XWRLEAD + XWRACTIVE - 2) tc(XTIM).

FIGURE 28. Timing waveforms.

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NOTES:
1. All pending XINTF accesses are completed.
2. Normal XINTF operation resumes.
FIGURE 29. Timing waveforms.

NOTES:
1. All pending XINTF accesses are completed.
2. Normal XINTF operation resumes.
FIGURE 30. Timing waveforms.

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FIGURE 31. Timing waveforms.

FIGURE 32. Timing waveforms.

FIGURE 33. Timing waveforms.

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FIGURE 34. Timing waveforms.

FIGURE 35. Timing waveforms.

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FIGURE 36. Timing waveforms.

FIGURE 37. Timing waveforms.

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FIGURE 38. Timing waveforms.

FIGURE 39. Timing waveforms.

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4. VERIFICATION
4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as
indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices,classification, packaging, and labeling of moisture sensitive devices, as applicable.
5. PREPARATION FOR DELIVERY
5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial
practices for electrostatic discharge sensitive devices.
6. NOTES
6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum.
6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book.
The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided.
6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee
of present or continued availability as a source of supply for the item. DLA Land and Maritime maintains an online database of all
current sources of supply at https://landandmaritimeapps.dla.mil/programs/smcr/.

1/
2/

Vendor item drawing administrative
control number 1/

Device manufacturer
CAGE code

Vendor part number

V62/09624-01YE

01295

SM320F28335PTPMEP

V62/09624-02XE

2/

SM320F28335GHHAEP

The vendor item drawing establishes an administrative control number for identifying the item on
the engineering documentation.
Not available from an approved source of supply.

CAGE code

Source of supply

01295

DLA LAND AND MARITIMECOLUMBUS, OHIO

Texas Instruments, Inc.
Semiconductor Group
8505 Forest Lane
P.O. Box 660199
Dallas, TX 75243

SIZE
A

CAGE CODE
16236
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