RV-8263-C8
Application Manual

Application
Manual
RV-8263-C8
Ultra-Small
Real-Time Clock Modulewith I2C-Bus Interface

June 2023

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Ultra-Small Real-Time Clock Module with I2C-Bus Interface

RV-8263-C8

TABLE OF CONTENTS
1.

OVERVIEW ..................................................................................................................................................... 4
1.1. GENERAL DESCRIPTION ......................................................................................................................... 4
1.2. APPLICATIONS ......................................................................................................................................... 5
1.3. ORDERING INFORMATION ...................................................................................................................... 52.

BLOCK DIAGRAM ......................................................................................................................................... 6
2.1. PINOUT ...................................................................................................................................................... 7
2.2. PIN DESCRIPTION .................................................................................................................................... 7
2.3. FUNCTIONAL DESCRIPTION ................................................................................................................... 8
2.4. DEVICE PROTECTION DIAGRAM ........................................................................................................... 93.

REGISTER ORGANIZATION ....................................................................................................................... 10
3.1. REGISTER OVERVIEW ........................................................................................................................... 10
3.2. CONTROL REGISTERS .......................................................................................................................... 11
3.3. TIME AND DATE REGISTERS ................................................................................................................ 14
3.4. ALARM REGISTERS ............................................................................................................................... 17
3.5. TIMER REGISTERS ................................................................................................................................. 20
3.6. REGISTER RESET VALUES SUMMARY ............................................................................................... 21

4.

DETAILED FUNCTIONAL DESCRIPTION .................................................................................................. 224.1. POWER ON RESET (POR)...................................................................................................................... 224.2. SOFTWARE RESET ................................................................................................................................ 224.3. OSCILLATOR STOP FLAG ..................................................................................................................... 23
4.4. SETTING AND READING THE TIME ...................................................................................................... 24
4.5. INTERRUPT OUTPUT ............................................................................................................................. 25
4.6. ALARM FUNCTION ................................................................................................................................. 26
4.6.1. ALARM INTERRUPT ........................................................................................................................ 26
4.7. COUNTDOWN TIMER FUNCTION .......................................................................................................... 27
4.7.1. TIMER FLAG TF ............................................................................................................................... 27
4.7.2. TIMER INTERRUPT MODE TI_TP ................................................................................................... 27
4.7.3. PULSE GENERATOR 2 .................................................................................................................... 27
4.7.4. USE OF THE COUNTDOWN TIMER ............................................................................................... 28
4.8. MINUTE AND HALF MINUTE INTERRUPT FUNCTION ........................................................................ 30
4.8.1. PULSE GENERATOR 1 .................................................................................................................... 30
4.9. FREQUENCY OFFSET COMPENSATION ............................................................................................. 31
4.9.1. OFFSET COMPENSATION CALCULATION WORKFLOW ............................................................. 32
4.10. COMPENSATION INTERRUPT FUNCTION ........................................................................................... 34
4.10.1. COMPENSATION PULSES WHEN MODE = 0 (NORMAL MODE) ................................................. 34
4.10.2. COMPENSATION PULSES WHEN MODE = 1 (FAST MODE) ....................................................... 35
4.11. CLKOUT FREQUENCY SELECTION ..................................................................................................... 36
4.12. STOP BIT FUNCTION .............................................................................................................................. 37

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I2C INTERFACE ............................................................................................................................................ 39

5.

5.1. BIT TRANSFER ....................................................................................................................................... 39
5.2. START AND STOP CONDITIONS .......................................................................................................... 39
5.3. DATA VALID ............................................................................................................................................ 40
5.4. SYSTEM CONFIGURATION.................................................................................................................... 40
5.5. ACKNOWLEDGE ..................................................................................................................................... 41
5.6. SLAVE ADDRESS ................................................................................................................................... 42
5.7. WRITE OPERATION ................................................................................................................................ 42
5.8. READ OPERATION AT SPECIFIC ADDRESS ....................................................................................... 43
5.9. READ OPERATION ................................................................................................................................. 43
6.

ELECTRICAL SPECIFICATIONS ................................................................................................................ 44
6.1. ABSOLUTE MAXIMUM RATINGS .......................................................................................................... 44
6.2. OPERATING PARAMETERS .................................................................................................................. 45
6.3. OSCILLATOR PARAMETERS ................................................................................................................ 48
6.3.1. XTAL FREQUENCY VS. TEMPERATURE CHARACTERISTICS ................................................... 48
6.4. I2C-BUS CHARACTERISTICS ................................................................................................................. 49

7.

APPLICATION INFORMATION ................................................................................................................... 50
7.1. OPERATING RV-8263-C8 ....................................................................................................................... 50
7.2. OPERATING RV-8263-C8 WITH BACKUP CAPACITOR ...................................................................... 51

8.

PACKAGE .................................................................................................................................................... 52
8.1. DIMENSIONS AND SOLDER PAD LAYOUT .......................................................................................... 52
8.1.1. RECOMMENDED THERMAL RELIEF ............................................................................................. 52
8.2. MARKING AND PIN #1 INDEX ................................................................................................................ 53

9.

MATERIAL COMPOSITION DECLARATION & ENVIRONMENTAL INFORMATION ............................... 54
9.1. HOMOGENOUS MATERIAL COMPOSITION DECLARATION ............................................................. 54
9.2. MATERIAL ANALYSIS & TEST RESULTS ............................................................................................ 55
9.3. RECYCLING MATERIAL INFORMATION .............................................................................................. 56
9.4. ENVIRONMENTAL PROPERTIES & ABSOLUTE MAXIMUM RATINGS ............................................. 57

10.

SOLDERING INFORMATION ...................................................................................................................... 58

11.

HANDLING PRECAUTIONS FOR MODULES WITH EMBEDDED CRYSTALS........................................ 59

12.

PACKING & SHIPPING INFORMATION ..................................................................................................... 60

13.

COMPLIANCE INFORMATION ................................................................................................................... 61

14.

DOCUMENT REVISION HISTORY .............................................................................................................. 61

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RV-8263-C8
Ultra Small Real-Time Clock Module with I2C-Bus Interface
1. OVERVIEW
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RTC module with built-in “Tuning Fork” crystal oscillating at 32.768 kHzCounters for seconds, minutes, hours, date, weekday, month and year
Programmable Offset register for frequency adjustment
Automatic leap year calculation (2000 to 2099)
Alarm Interrupts for second, minutes, hour, date and weekday settings
Countdown Timer Interrupt function
Minute and Half Minute Interrupt
Oscillator stop detection function
Internal Power-On Reset (POR)
Programmable Clock Output for peripheral devices (32.768 kHz, 16.384 kHz, 8.192 kHz, 4.096 kHz, 2.048
kHz, 1.024 kHz and 1 Hz) with enable/disable function (CLKOE)
I2C-bus interface (up to 400 kHz)
Wide operating voltage range: 0.9 V to 5.5 V
Wide interface operating voltage: 1.8 to 5.5 V
Very low current consumption: 190 nA (VDD = 3.0 V, TA = 25°C)
Operating temperature range: -40 to +85°C
Ultra-miniature ceramic SMD package with metal lid, RoHS-compliant and 100% lead-free:
2.0 x 1.2 x 0.70 mm
Ultra-low profile (maximum height 0.70 mm), lightweight (5.1 mg)
Automotive qualification according to AEC-Q200 available

1.1. GENERAL DESCRIPTION
The RV-8263-C8 is a CMOS real-time clock/calendar module optimized for low power consumption. An Offset
register makes it possible to compensate for the frequency deviation of the clock of 32.768 kHz. All addresses anddata are transferred over an I2C-bus interface for communication with a host controller. The register address isincremented automatically after each written or read data byte.
This ultra-small and lightweight RTC module has been specially designed for miniature and cost sensitive highvolume applications.

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1.2. APPLICATIONSThe RV-8263-C8 RTC module combines standard RTC functions in high reliable, ultra-small ceramic package: Smallest RTC module (embedded XTAL) in miniature 2.0 x 1.2 x 0.70 mm lead-free ceramic package
 Price competitive
The unique size and the competitive pricing make this product perfectly suitable for many applications where highcircuit density or a smaller PCB is required: Communication: IoT / Wearables / Wireless Sensors and Tags / Handsets
 Automotive:
M2M / Navigation & Tracking Systems / Dashboard / Tachometers / Engine Controller
Car Audio & Entertainment Systems
 Metering:
E-Meter / Heating Counter / Smart Meters / PV Converter Outdoor:
ATM & POS systems / Surveillance & Safety systems / Ticketing Systems
 Medical:
Glucose Meter / Health Monitoring Systems
 Safety:
Security & Camera Systems / Door Lock & Access Control
 Consumer:
Gambling Machines / TV & Set Top Boxes / White Goods
 Automation:
PLC / Data Logger / Home & Factory Automation / Industrial and Consumer Electronics

1.3. ORDERING INFORMATION
Example:Code
TA (Standard)
Code
QC (Standard)
QA

June 2023

RV-8263-C8

TA

QC

Operating temperature range-40 to +85°C
Qualification
Commercial Grade
Automotive Grade AEC-Q200

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2. BLOCK DIAGRAM

VDD
VSS

SCL

SDA

5

4

POWER
CONTROL

81

I2C-BUSINTERFACEFREQUENCY
OFFSETCOMPENSATION

XTAL
OSC
CLKOUT
CLKOE

SYSTEMCONTROLLOGIC

DIVIDER

7
2

3

INPUT
OUTPUT
CONTROL

Control1
Control2
OffsetRAM
Seconds
Minutes
Hours
Date
Weekday
Month
Year
Seconds Alarm
Minutes Alarm
Hours Alarm
Date Alarm
Weekday Alarm
Timer Value
Timer Mode

00

11

INT

RESET

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2.1. PINOUT
RV-8263-C8 Package: (top view)

#8

#5

8263
#1

#1

SDA

#2

CLKOE

#3

̅̅̅̅̅
INT

#4

VSS

#5

VDD

#6

NC

#7

CLKOUT

#8

SCL

#4

2.2. PIN DESCRIPTION
Symbol

Pin #

SDA

1

CLKOE

2

̅̅̅̅̅
INT

3

VSS
VDD
NC

4
5
6

CLKOUT

7SCL

8June 2023

Description
I2C Serial Data Input-Output; open-drain; requires pull-up resistor.
Input to enable the CLKOUT pin. If CLKOE is HIGH, the CLKOUT pin is in output mode. When
CLKOE is tied to Ground, the CLKOUT pin is LOW.
Interrupt Output; open-drain; active LOW; requires pull-up resistor; Used to output alarm, minute,half minute, countdown timer and compensation Interrupt signals.
Ground.
Power Supply Voltage.
Not connected. Is internally connected and should be left floating.
Clock Output; push-pull; controlled by CLKOE. If CLKOE is HIGH (VDD), the CLKOUT pin drives thesquare wave of 32.768 kHz, 16.384 kHz, 8.192 kHz, 4.096 kHz, 2.048 kHz, 1.024 kHz or 1 Hz
(Default value is 32.768 kHz). When CLKOE is tied to Ground, the CLKOUT pin is LOW.
I2C Serial Clock Input; requires pull-up resistor.

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2.3. FUNCTIONAL DESCRIPTION
The RV-8263-C8 is a low power CMOS real-time clock/calendar module with embedded 32.768 kHz Crystal. The
CMOS IC contains 18 8-bit registers with an auto-incrementing register address, a frequency divider which provides
the source clock for the Real Time Clock (RTC), a programmable clock output, and an I2C-Bus interface (2 wires).
The Offset register allows to digitally adjust the 32.768 kHz oscillator frequency in order to compensate and minimize
time deviation.
The built-in address register will increment automatically after each read or write of a data byte up to the register 11h.
After register 11h, the auto-incrementing will wrap around to address 00h (see following Figure).
Handling address registers:
Address
00h
wrap around

01h
02h
03h

autoincrement

:
0Fh
10h
11h

All registers (see REGISTER OVERVIEW) are designed as addressable 8-bit parallel registers although not all bits
are implemented.
 The first two registers (memory address 00h and 01h) are used as control and status register.
 The register at address 02h is an Offset register allowing the compensation of time deviation.
 The register at address 03h is a free User RAM byte.
 The addresses 04h through 0Ah are used as counters for the clock function (seconds up to year counters).
 Address locations 0Bh through 0Fh contain alarm registers which define the conditions for an alarm.
 The registers at 10h and 11h are for the timer function.
The Seconds, Minutes, Hours, Date, Month and Year as well as the corresponding alarm registers are all coded in
Binary Coded Decimal (BCD) format. When one of the RTC registers is written or read, the contents of all time
counters are frozen. Therefore, faulty writing or reading of the clock and calendar during a carry condition is prevented
for up to 1 second.

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2.4. DEVICE PROTECTION DIAGRAM

SDA
CLKOE
INT

VSS

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1

8

2

7

3

6

4

5

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SCL
CLKOUT
NC

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3. REGISTER ORGANIZATION
Registers are accessed by selecting a register address and then performing read or write operations. Multiple reads
or writes may be executed in a single access, with the address automatically incrementing after each byte.
18 registers (00h – 11h) are available. The time registers are encoded in the Binary Coded Decimal format (BCD) tosimplify application use. Other registers are either bit-wise or standard binary format. When one of the RTC registers
is written or read, the contents of all time counters are frozen for up to 1 second. Therefore, faulty writing or readingof the clock and calendar during a carry condition is prevented.

3.1. REGISTER OVERVIEW
After reset, all registers are set according to Table in section REGISTER RESET VALUES SUMMARY.
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h

Function

Bit 7

Bit 6

Bit 5

Control1
Control2
OffsetRAM
Seconds
Minutes
Hours (24 hour)
Hours (12 hour)Date
Weekday
Month
Year
Seconds Alarm
Minutes Alarm
Hours Alarm (24h)
Hours Alarm (12h)Date Alarm
Weekday Alarm
Timer Value
Timer Mode

TEST
AIE
MODE

SR
AF

STOP
MI

OS
X

40
40

X

X

X
X
X
80
AE_S
AE_M

X
X
X
40
40
40

AE_H

X

AE_D
AE_W
128
X

X
X
64
X

20
20
20
AMPM
20
X
X
20
20
20
20
AMPM
20
X
32
X

Bit 4

Bit 3
SR

TF
OFFSETRAM data
10
8
10
8
10
8
10
8
10
8
X
X
10
8
10
8
10
8
10
8
10
8
10
8
10
8
X
X
16
8
TD

Bit 2

Bit 1

Bit 0

CIE

12_24
FD

CAP

4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
TE

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
TIE

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
TI_TP

HMI

Bit positions labeled as X are not implemented and will return a 0 when read.

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3.2. CONTROL REGISTERS
To ensure that all control registers will be set to their default values, the V DD level must be at zero volts at initial
power-up. If this is not possible, a reset must be initiated with the software reset command when power is stable.
Refer to section SOFTWARE RESET for details.

00h - Control1
Control and status register 1.
Address

Function

Bit 7

Bit 6

Bit 5

00h

Control1
Reset

TEST
0

SR
0

STOP
0

Bit

Symbol

Value

7

TEST

0
1

6

SR

5

STOP

4:3

SR

2

CIE

1

12_24

0

CAP

June 2023

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0

CIE
0

12_24
0

CAP
0

SR
0

Description

Normal mode.
External clock test mode. Do not use.
Software Reset (see SOFTWARE RESET)0
No software reset.
Initiate software reset; this bit always returns a 0 when read. For a software
1
reset, 01011000 (58h) must be sent to register Control1.
STOP bit (see STOP BIT FUNCTION)0
RTC clock runs.
RTC clock is stopped; the upper part of the RTC divider chain flip-flops
1(prescaler F2 to F14) are asynchronously set logic 0. The CLKOUT
frequencies 32.768 kHz, 16.384 kHz and 8.192 kHz are still available.
Software Reset (see SOFTWARE RESET)
00
No software reset.
Initiate software reset; this bits always returns a 0 when read. For a11
software reset, 01011000 (58h) must be sent to register Control1.
Compensation Interrupt Enable (see FREQUENCY OFFSET COMPENSATION)0
No compensation interrupt will be generated.
̅̅̅̅̅ at every
Compensation interrupt pulses will be generated on pin INT
1compensation cycle.
12 or 24 hour mode (see TIME AND DATE REGISTERS and ALARM REGISTERS)
024 hour mode is selected (0 to 23).
1
12 hour mode is selected (1 to 12).
0Must always be written with logic 0.

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01h - Control2
Control and status register 2.
Address

Function

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

01h

Control2
Reset

AIE
0

AF
0

MI
0

HMI
0

TF
0

Bit

Symbol

Value

7

AIE

6

AF

5

MI

4

HMI

3

TF

2:0

FD

FD
000
001
010
011
100
101
110
111

Bit 2

Bit 1

Bit 0

0

FD
0

0

Description

Alarm Interrupt Enable (see ALARM FUNCTION and INTERRUPT OUTPUT)
0
Disabled
1
Enabled
Alarm Flag (see ALARM FUNCTION and INTERRUPT OUTPUT)
Read: Alarm Flag inactive0
Write: Alarm Flag is cleared
Read: Alarm Flag active
1
Write: Alarm Flag remains unchanged
Minute Interrupt Enable (see MINUTE AND HALF MINUTE INTERRUPT FUNCTION
and TIMER FLAG TF)
0
Disabled
1
EnabledHalf Minute Interrupt Enable (see MINUTE AND HALF MINUTE INTERRUPTFUNCTION and TIMER FLAG TF)
0
Disabled
1
EnabledTimer Flag (see COUNTDOWN TIMER FUNCTION, INTERRUPT OUTPUT and
TIMER FLAG TF)
0
No timer interrupt generated
1
Flag set when timer interrupt generated
000 to
CLKOUT Frequency (see CLKOUT FREQUENCY SELECTION)
111
CLKOUT Frequency

32.768 kHz – Default value
16.384 kHz
8.192 kHz4.096 kHz2.048 kHz1.024 kHz
1 Hz (1)
CLKOUT = LOW(1) 1 Hz clock pulses are affected by compensation pulses (see FREQUENCY OFFSET COMPENSATION).

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02h – Offset Register
This register holds the OFFSET value to digitally compensate the initial frequency deviation of the 32.768 kHz
oscillator or for aging adjustment (see FREQUENCY OFFSET COMPENSATION).
Address

Function

Bit 7

02h

Offset
Reset

MODE
0

Bit

Symbol

Value

7

MODE

6:0

OFFSET0
1-64 to
+63

Bit 6
0

Bit 5
0

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0

OFFSET00

0

0

Description
Offset Mode
Normal Mode: Offset is made once every two hours.
Fast Mode: Offset is made every 4 minutes.
Offset value.
For MODE = 0, each LSB introduces an offset of 4.34 ppm. For MODE = 1,
each LSB introduces an offset of 4.069 ppm. The values of 4.34 ppm and4.069 ppm are based on a nominal 32.768 kHz clock. The offset value iscoded in two’s complement giving a range of +63 LSB to -64 LSB (seeFREQUENCY OFFSET COMPENSATION).

OFFSET

OFFSET compensation value
in decimalCompensation pulses
in steps

01111110111110:0000001
0000000

63
62
:
1
0

+63
+62
:
+1
0

11111111111110:
1000001
1000000

127
126
:
65
64

-1
-2
:
-63
-64

CLKOUT frequency
offset in ppm(1)Normal Mode
Fast Mode
MODE = 0
MODE = 1+273.420+256.347+269.080+252.278::+4.340+4.06900-4.340-8.680:-273.420-277.760-4.069-8.138:-256.347-260.416(1) The frequency offset measured at CLKOUT pin can be compensated by computing the compensation value OFFSET and writing it into

the Offset register (see OFFSET COMPENSATION CALCULATION WORKFLOW).

03h - RAM
Free RAM byte, which can be used for any purpose, for example, status byte of the system.
Address

Function

03h

RAM
Reset

Bit

Symbol

7:0

RAM

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Bit 7
0
Value
00h to
FFh

Bit 6
0

Bit 5
0

Bit 4

Bit 3

RAM data
0
0

Bit 2

Bit 1

Bit 0

0

0

0

Description
User RAM

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3.3. TIME AND DATE REGISTERS
04h - Seconds
This register holds the count of seconds, in two binary coded decimal (BCD) digits. Values will be from 00 to 59.
Address

Function

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

04h

Seconds
Reset

OS
1

40
0

20
0

10
0

8
0

4
0

2
0

1
0

Bit

Symbol

Value

7

0

OS

1
6:0

Seconds

00 to 59

Description
Oscillator Stop (see OSCILLATOR STOP FLAG)
Clock integrity is guaranteed.
Clock integrity is not guaranteed; oscillator has stopped or has beeninterrupted. – Default value
Holds the count of seconds, coded in BCD format.

05h - Minutes
This register holds the count of minutes, in two binary coded decimal (BCD) digits. Values will be from 00 to 59.
Address

Function

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

05h

Minutes
Reset

X
0

40
0

20
0

10
0

8
0

4
0

2
0

1
0

Bit

Symbol

Value

7
6:0

X
Minutes000 to 59

Description
UnusedHolds the count of minutes, coded in BCD format.

06h – Hours
This register holds the count of hours, in two binary coded decimal (BCD) digits. If the 12_24 bit is cleared (default)(see CONTROL REGISTERS, 00h - Control1) the values will be from 0 to 23. If the 12_24 bit is set, the hour values
will range from 1 to 12 and the AMPM bit will be 0 for AM hours and 1 for PM hours.
Address06h

Function
Hours (24 hour mode)– default value
Hours (12 hour mode)
Reset

Bit 7

Bit 6

X

X

0

0

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

20

10

8

4

2

1

AMPM
0

10
0

8
0

4
0

2
0

1
0

Hours (24 hour mode), 12_24 = 0 – default value
Bit

Symbol

7:6

X
Hours (24 hour mode)– default value

5:0

Value
0
0 to 23

Description
UnusedHolds the count of hours, coded in BCD format.

Hours (12 hour mode), 12_24 = 1
Bit

Symbol

Value

7:6

X

5

AMPM

4:0

Hours (12 hour mode)00
1
1 to 12June 2023

Description
UnusedAM hours.
PM hours.
Holds the count of hours, coded in BCD format.

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07h – Date
This register holds the current date of the month, in two binary coded decimal (BCD) digits. Values will range from
01 to 31. Leap years are correctly handled from 2000 to 2099.
Address

Function

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

07h

Date
Reset

X
0

X
0

20
0

10
0

8
0

4
0

2
0

1
1

Value

Description0

UnusedHolds the current date of the month, coded in BCD format. – Default value
= 01

Bit

Symbol

7:6

X

5:0

Date

01 to 3108h - Weekday
This register holds the current day of the week. Each value represents one weekday that is assigned by the user.
Values will range from 0 to 6.
Address

Function

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

08h

Weekday
Reset

X
0

X
0

X
0

X
0

X
0

4
1

2
1

1
0

Bit

Symbol

Value

7:3
2:0

X
Weekday0
0 to 6

Bit 3

Bit 2

Bit 1

Bit 0

0

0
0
0
0
1
1
1

0
0
1
1
0
0
1

0
1
0
1
0
1
0

Weekday
Weekday 1
Weekday 2
Weekday 3
Weekday 4
Weekday 5
Weekday 6
Weekday 7 – Default value

June 2023

Bit 7

0

Description
UnusedHolds the weekday counter value.
Bit 6

0

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Bit 4

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Ultra-Small Real-Time Clock Module with I2C-Bus Interface

RV-8263-C8

09h - Month
This register holds the current month, in two binary coded decimal (BCD) digits. Values will range from 01 to 12.
Address

Function

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

09h

Month
Reset

X
0

X
0

X
0

10
0

8
0

4
0

2
0

1
1

Bit

Symbol

Value

7:5
4:0

X
Month

0
01 to 12

UnusedHolds the current month, coded in BCD format.

Bit 7

Bit 6

Month
January – Default value
February
March
April
May
June
July
AugustSeptember
OctoberNovember
December

0

Description

0

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0

0
0
0
0
0
0
0
0
0
1
1
1

0
0
0
0
0
0
0
1
1
0
0
0

0
0
0
1
1
1
1
0
0
0
0
0

0
1
1
0
0
1
1
0
0
0
0
1

1
0
1
0
1
0
1
0
1
0
1
0

0Ah - Year
This register holds the current year, in two binary coded decimal (BCD) digits. Values will range from 00 to 99. Leap
years are correctly handled from 2000 to 2099.
Address

Function

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0Ah

Year
Reset

80
0

40
0

20
0

10
0

8
0

4
0

2
0

1
0

Bit

SymbolValue

Description

7:0

Year

00 to 99

Holds the current year, coded in BCD format.

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Ultra-Small Real-Time Clock Module with I2C-Bus Interface

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3.4. ALARM REGISTERS
0Bh – Seconds Alarm
This register holds the Seconds Alarm Enable bit AE_S and the alarm value for seconds, in two binary coded
decimal (BCD) digits. Values will range from 00 to 59.
Address

Function

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0Bh

Seconds Alarm
Reset

AE_S
1

40
0

20
0

10
0

8
0

4
0

2
0

1
0

Bit

Symbol

Value

7

AE_S

6:0

Seconds Alarm0
1
00 to 59

Description
Seconds Alarm Enable bit (see ALARM FUNCTION)
EnabledDisabled – Default value
Holds the alarm value for seconds, coded in BCD format.

0Ch – Minutes Alarm
This register holds the Minutes Alarm Enable bit AE_M and the alarm value for minutes, in two binary coded decimal(BCD) digits. Values will range from 00 to 59.
Address

Function

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0Ch

Minutes Alarm
Reset

AE_M
1

40
0

20
0

10
0

8
0

4
0

2
0

1
0

Bit

Symbol

Value

7

AE_M

6:0

Minutes Alarm

June 2023

0
100 to 59

Description
Minutes Alarm Enable bit (see ALARM FUNCTION)
EnabledDisabled – Default value
Holds the alarm value for minutes, coded in BCD format.

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Ultra-Small Real-Time Clock Module with I2C-Bus Interface

RV-8263-C8

0Dh – Hours Alarm
This register holds the Hours Alarm Enable bit AE_H and the alarm value for hours, in two binary coded decimal(BCD) digits. If the 12_24 bit is cleared (default value) (see CONTROL REGISTERS, 00h - Control1) the values will
range from 00 to 23. If the 12_24 bit is set, the hour values will be from 01 to 12 and the AMPM bit will be 0 for AM
hours and 1 for PM hours.
Address0Dh

Function
Hours Alarm (24 hourmode) – default value
Hours Alarm (12 hour
mode)
Reset

Bit 7

Bit 6

AE_H

X

1

0

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

20

10

8

4

2

1

AMPM

10

8

4

2

1

0

0

0

0

0

0

Hours Alarm (24 hour mode), 12_24 = 0 – default value
Bit

Symbol

7

AE_H

6

X
Hours Alarm (24 hourmode) – default value

5:0

Value

Description01
0

Hours Alarm Enable bit (see ALARM FUNCTION)
EnabledDisabled – Default value
Unused00 to 23

Holds the alarm value for hours, coded in BCD format.

Hours Alarm (12 hour mode), 12_24 = 1
Bit

Symbol

7

AE_H

6

X

5

AMPM

4:0

Hours Alarm (12 hourmode)

June 2023

Value

Description

0
1
0
0
1

Hours Alarm Enable bit (see ALARM FUNCTION)
EnabledDisabled – Default value
UnusedAM hours.
PM hours.

01 to 12

Holds the alarm value for hours, coded in BCD format.

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Ultra-Small Real-Time Clock Module with I2C-Bus Interface

RV-8263-C8

0Eh - Date Alarm
This register holds the Date Alarm Enable bit AE_D and the alarm value for the date, in two binary coded decimal(BCD) digits. Values will range from 01 to 31.
Address

Function

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0Eh

Date Alarm
Reset

AE_D
1

X
0

20
0

10
0

8
0

4
0

2
0

1
0

Bit

Symbol

Value

7

AE_D

6
5:0

X
Date Alarm01
001 to 31

Description
Date Alarm Enable bit (see ALARM FUNCTION)
EnabledDisabled – Default value
UnusedHolds the alarm value for the date, coded in BCD format.

0Fh – Weekday Alarm
This register holds the Weekday Alarm Enable bit AE_W and the alarm value for the weekday, in two binary coded
decimal (BCD) digits. Values will range from 0 to 6.
Address

Function

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0Fh

Weekday Alarm
Reset

AE_W
1

X
0

X
0

X
0

X
0

4
0

2
0

1
0

Bit

Symbol

Value

7

AE_W

6:3
2:0

X
Weekday Alarm

June 2023

01
00 to 6

Description
Weekday Alarm Enable bit (see ALARM FUNCTION)
EnabledDisabled – Default value
UnusedHolds the weekday alarm value, coded in BCD format.

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Ultra-Small Real-Time Clock Module with I2C-Bus Interface

RV-8263-C8

3.5. TIMER REGISTERS
10h – Timer Value
This register holds the current value of the Countdown Timer. It may be loaded with the desired starting value when
the Countdown Timer is stopped.
Address

Function

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

10h

Timer Value
Reset

128
0

64
0

32
0

16
0

8
0

4
0

2
0

1
0

Bit

Symbol7:0Timer Value

Value
00h toFFh

Description
Countdown Timer Value (see COUNTDOWN TIMER FUNCTION)Countdown Period in seconds:
Countdown Period =Timer Value
Timer Clock Frequency

11h – Timer Mode
This register controls the Countdown Timer function.
Address

Function

Bit 7

Bit 6

Bit 5

11h

Timer Mode
Reset

X
0

X
0

X
0

Bit

Symbol

7:5

X

4:3

TD

2

TE

1

TIE

0

TI_TP

Bit 4
1

Value
0
00
01
10
11

Bit 3

Bit 2

Bit 1

Bit 0

1

TE
0

TIE
0

TI_TP
0

TD

Description
UnusedTimer Clock Frequency (see COUNTDOWN TIMER FUNCTION)(1)
4.096 kHz

64 Hz(2)
1 Hz(2)
1/60 Hz – Default value(2)Timer Enable0
Disabled – Default value
1
EnabledTimer Interrupt Enable0
No interrupt generated from timer. – Default value
1
Interrupt generated from timer.
Timer Interrupt Mode.
̅̅̅̅̅ pulse generation is
How the setting of TI_TP and the Timer Flag TF can affect the INT
explained in sections COUNTDOWN TIMER FUNCTION and MINUTE AND HALFMINUTE INTERRUPT FUNCTION.
0Interval Mode. Interrupt follows Timer Flag TF. – Default value
1
Pulse Mode. Interrupt generates a pulse.

(1) When not in use, the TD field is recommended to be set to 11 (1⁄60 Hz) for power saving.
(2) Time periods can be affected by compensation pulses (64 Hz only in MODE = 1), (see FREQUENCY OFFSET COMPENSATION).

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Ultra-Small Real-Time Clock Module with I2C-Bus Interface

RV-8263-C8

3.6. REGISTER RESET VALUES SUMMARY
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h

FunctionControl1
Control2
OffsetRAM
Seconds
Minutes
Hours (24h / 12h)
Date
Weekday
Month
Year
Seconds Alarm
Minutes Alarm
Hours Alarm (24h / 12h)
Date Alarm
Weekday Alarm
Timer Value
Timer Mode

RV-8263-C8 resets to:Time (hh:mm:ss)
Date (YY-MM-DD)
Weekday
Mode
Pins
OffsetAlarmsTimer
Interrupts

June 2023

=
=
=
=
=
=
=
=
=

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0
0
0
0
1
0
0
0
0
0
0
1
1
1
1
1
0
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1

0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0

00:00:00
00-01-01
Weekday 7
RTC clock runs, 24 h mode
CLKOUT Frequency = 32.768 kHz (when CLKOE is HIGH)
0disabled
disabled, Timer Clock Frequency = 1/60 Hz
disabled

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Ultra-Small Real-Time Clock Module with I2C-Bus Interface

RV-8263-C8

4. DETAILED FUNCTIONAL DESCRIPTION
4.1. POWER ON RESET (POR)
The power on reset (POR) is generated at start-up. All registers including the Counter Registers are initialized to theirreset values (see REGISTER RESET VALUES SUMMARY).
There is a small probability that the registers of the RV-8263-C8 are corrupted after an automatic power-on reset if
the device is powered up with a residual VDD level. For a correct POR it is required that the VDD starts at zero volts at
power up or upon power cycling to ensure that the registers are not corrupted.
If a valid POR cannot be performed, the reset must be initiated with the software reset command after power-up (i.e.
when power is stable). See following section SOFTWARE RESET.

4.2. SOFTWARE RESET
Beside the POR, a reset can also be initiated with the software reset command. Software reset command requires a
combination of the bits 6, 4, and 3 in register Control1 (00h) set to 1 and all other bits to 0 by sending the bit sequence
01011000 (58h), see following Figure.
Software reset command:
Slave address

R/W

Register address 00h

Software reset 58h
(1)

SDA S

1

0

1

0

0

0

1

0

A

0

0

0

0

0

0

0

0

A

0

1

0

1

1

0

0

0

A P/S

SCL

internal
reset signal(1)

After sending the software reset command, it is recommended to re-initialize the interface by an I2C STOP
condition followed by an I2C START condition.

In reset state all registers are set according to the Table in section REGISTER RESET VALUES SUMMARY and theaddress pointer points to no address.

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Ultra-Small Real-Time Clock Module with I2C-Bus Interface

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4.3. OSCILLATOR STOP FLAG
When the oscillator of the RV-8263-C8 is stopped, the Oscillator Stop flag OS is set. The oscillator is considered to
be stopped between power up and stable crystal oscillation (start-up time tSTART). This time can be in a range oftypical 200 ms to maximal 2 s depending on temperature and supply voltage.
The flag remains set until cleared by command (see following Figure). If the flag cannot be cleared, then the oscillator
is not running. This method can be used to monitor the oscillator and to determine if the supply voltage has reduced
to the point where oscillation fails.
OS flag:
backupsupplypower upmain
supplyVDD
VDDminoscillation

1

OS flag

2

3

tSTARTOS = 1 and flag cannot be cleared
1

Oscillation now stable.

2

OS flag cleared by software.

3

OS flag set when oscillator stops.

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Ultra-Small Real-Time Clock Module with I2C-Bus Interface

RV-8263-C8

4.4. SETTING AND READING THE TIME
The following Figure shows the data flow and data dependencies starting from the 1 Hz clock tick.
Data flow for the time function:
1 Hz tick
SECONDSMINUTES

12_24 hour mode

HOURS

LEAP YEARCALCULATIONDATEWEEKDAYMONTHSYEARSDuring read/write operations, the time counting registers (memory locations 04h through 0Ah) are frozen for 1
second.
The freezing prevents:
 Faulty reading of the clock and calendar during a carry condition
 Incrementing the time registers during the read cycle
When the read/write access has been terminated within 1 second (t < 1 s), the time circuit is de-frozen immediately
and any pending request to increment the time counters that occurred during the read/write access is correctly
applied. Maximal one 1 Hz tick can be handled.
When the read/write access last longer than 1 second, the time circuit is de-frozen automatically after 1 second inorder not to miss 1 Hz ticks and the lost 1 Hz ticks cannot be handled completely. Therefore, each interface
communication has to be correctly terminated within 1 second (see following Figure).
Access time for read/write operations:
t<1s
START

SLAVE ADDRESS

DATA

DATA

STOP

Because of this method, it is very important to make a read or write access in one go, that is, setting or reading
seconds through to year should be made in one single access. Failing to comply with this method could result in thetime becoming corrupted.

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Ultra-Small Real-Time Clock Module with I2C-Bus Interface

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4.5. INTERRUPT OUTPUT
The interrupt pin ̅̅̅̅̅
INT can be triggered by four different functions: ALARM FUNCTION
 COUNTDOWN TIMER FUNCTION MINUTE AND HALF MINUTE INTERRUPT FUNCTION
 COMPENSATION INTERRUPT FUNCTION
Interrupt scheme:
HMI
0
1

SECONDS COUNTER

HMI

HMI/MI

SET0
1

MINUTES COUNTER

MI

0
CLEAR

PULSE
GENERATOR 1
TRIGGER

MI

0
1

1

CLEAR

from interface:clear TF

TI_TP

TIMER FLAGSET TFto interface:read TF

CLEAR

PULSE
GENERATOR 2
TRIGGER

TE

TIE
0

SET

COUNTDOWN COUNTER

INT

0
1

1

CLEAR

set alarm flag AF

ALARM FLAGAF
SET

to interface:read AF

AIE
0
1

CLEAR

from interface:clear AF

CIE
PULSE
GENERATOR 3
TRIGGER

offset circuit:
add/subtract pulse

0
1

CLEAR
from interface:clear CIE

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4.6. ALARM FUNCTION
By clearing the alarm enable bit (AE_x) of one or more of the alarm registers, the corresponding alarm condition(s)̅̅̅̅̅). The
are active. When an alarm occurs, AF is set logic 1. The asserted AF can be used to generate an interrupt (INT
AF is cleared by command.
The registers at addresses 0Bh through 0Fh contain alarm information. When one or more of these registers is loadedwith second, minute, hour, date or weekday, and its corresponding AE_x is logic 0, then that information is comparedwith the current second, minute, hour, date, and weekday. When all enabled comparisons first match, the Alarm Flag
(AF in CONTROL REGISTERS, 01h – Control2) is set logic 1.
Alarm function block diagram:check now signal

AE_S

SECOND ALARM=
SECOND TIME

1
0

AE_M
to interface:read AFMINUTE ALARM=MINUTE TIME

1
0

AIE

AE_H
HOUR ALARM=
HOUR TIME

1
0

ALARM
CONTROLALARM FLAG
AF
(1)
SET

0
1

INT

CLEAR

AE_D
from interface:clear AFDATE ALARM=DATE TIME

1
0
AE_W

WEEKDAY ALARM=WEEKDAY TIME
(1)

1
0

Only when all enabled alarm settings are matching.
It is only on increment to a matched case that the Alarm Flag is set.

4.6.1.ALARM INTERRUPTThe generation of interrupts from the alarm function is controlled via bit AIE. If bit AIE is enabled, the ̅̅̅̅̅
INT pin follows
the condition of bit AF. AF remains set until cleared by command. Once AF has been cleared, it will only be set again
when the time increments to match the alarm condition once more. Alarm registers which have their AE_x bit at logic
1 are ignored.

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4.7. COUNTDOWN TIMER FUNCTION
4.7.1.TIMER FLAG TF
The Timer Flag (bit TF) is set logic 1 on the first trigger of the Countdown Timer or the MI and HMI Interrupt. The
purpose of the flag is to allow the controlling system to interrogate what caused the interrupt: Timer/MI/HMI or Alarm.
The flag can be read and cleared by command.
The status of the Timer Flag TF can affect the ̅̅̅̅̅
INT pulse generation depending on the setting of TI_TP (see TIMERREGISTERS, 11h – Timer Mode):

4.7.2.TIMER INTERRUPT MODE TI_TP
When Interrupt is in Interval Mode (TI_TP = 0): only one Interrupt after the first countdown when TF is not cleared
 the ̅̅̅̅̅
INT generation follows the TF flag
 TF stays set until it is cleared If TF is not cleared before the next coming interrupt, no ̅̅̅̅̅
INT is generated
When Interrupt is in Timer Pulse Mode (TI_TP = 1):
 the Countdown Timer runs in a repetitive loop and keeps generating periodic interrupts
 an ̅̅̅̅̅
INT pulse is generated independent of the status of the Timer Flag TF
 TF stays set until it is cleared.
 TF does not affect ̅̅̅̅̅
INT

4.7.3.PULSE GENERATOR 2When the Timer Pulse Mode is activated (TI_TP = 1) the Pulse Generator 2 for the Countdown Timer Interrupt uses
an internal clock and is dependent on the selected Timer Clock Frequency for the countdown timer and on the Timer
Value. As a consequence, the width of the interrupt pulse varies (see following Table). The pulse widths are notaffected by the Offset Mode (bit MODE). TF and ̅̅̅̅̅
INT become active simultaneously.
̅̅̅̅̅
INT pulse width when using Countdown Timer:
Timer Clock Frequency
4.096 kHz
64 Hz
1 Hz
1/60 Hz̅̅̅̅̅INT pulse width
Timer Value = 1(1)122 µs
7.812 ms
15.625 ms
15.625 ms

Timer Value > 1(1)244 µs
15.625 ms
15.625 ms
15.625 ms(1) Timer Value = loaded countdown value. Timer stops when Timer Value = 0.

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4.7.4.USE OF THE COUNTDOWN TIMER
The timer has four selectable source clocks allowing for countdown periods in the range from 244 µs to 4 hours 15
min. For periods longer than 4 hours, the alarm function can be used.
Timer Clock Frequency and timer periods:
PeriodTD

Timer Clock Frequency(1)

00
01
10
11

4.096 kHzMinimum Period,
Timer Value = 1
244 µs
15.625 ms
1s
60 s

64 Hz(2)
1 Hz(2)
1/60 Hz(2)Maximum Period,
Timer Value = 255
62.256 ms
3.984 s255 s
4 hours 15 min(1) When not in use, the TD field is recommended to be set to 11 (1⁄60 Hz) for power saving.
(2) Time periods can be affected by compensation pulses (64 Hz only in MODE = 1), (see FREQUENCY OFFSET COMPENSATION).

Note that all timings are generated from the 32.768 kHz oscillator and therefore, based on the frequency
characteristics specified for the device, have a temperature profile with a parabolic frequency deviation which can
result in a change of up to 150 ppm across the entire operating temperature range of -40°C to 85°C (max. ± 20 ppm
at 25°C).
The timer counts down from the software-loaded 8-bit binary Timer Value in register 10h. Timer Values from 1 to 255
are valid. Loading the counter with 0 stops the timer.
When the counter decrements from 1, the Timer Flag (bit TF in register Control2) is set and the counter automatically
re-loads and starts the next timer period.
General countdown timer behavior:
Timer Value

xx

03

xx

03

Timer Clock
Countdown counter

02

01

03

02

01

03

02

01

03

TE
TF
INT
periodperiodThe first period has an uncertainty.
See table "First period duration for Timer Value n"

In this example, it is assumed that the Timer Flag TF is cleared before the next countdown period expires and̅̅̅̅̅ is set to Pulse Mode (TI_TP bit = 1).
that the pin INT

If a new Timer Value is written before the end of the current timer period, then this value takes immediate effect. It is
not recommended changing the Timer Value without first disabling the counter by setting bit TE logic 0. The updateof the Timer Value is asynchronous to the Timer Clock.
Therefore changing it without setting bit TE logic 0 may result in a corrupted value loaded into the countdown counter.
This results in an undetermined countdown period for the first period. The Timer Value will, however, be correctlystored and correctly loaded on subsequent timer periods.

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̅̅̅̅̅ is generated if this mode is enabled. See Section INTERRUPTWhen the TF flag is set, an interrupt signal on INTOUTPUT for details on how the interrupt can be controlled.
When starting the timer for the first time, the first period has an uncertainty. The uncertainty is a result of the enable
instruction being generated from the interface clock which is asynchronous from the Timer Clock Frequency.
Subsequent timer periods do not have such deviation. The amount of deviation for the first timer period depends onthe chosen source clock, see following Table.
First period duration for Timer Value n(1):TD

Timer Clock Frequency

00
01
10
11

4.096 kHz
64 Hz
1 Hz
1/60 HzFirst period duration
Minimum Period
Maximum Period(n – 1) * 244 µs(n – 1) * 15.625 ms(n – 1) * 1 s + 265 ms(n – 1) * 60 s + 59.212 s

n * 244 µs
n * 15.625 ms(n – 1) * 1 s + 280 ms(n – 1) * 60 s + 59.216 s

Subsequent
periods durationn * 244 µs
n * 15.625 ms
n*1s
n * 60 s(1) Timer Values n from 1 to 255 are valid. Loading the counter with 0 stops the timer.

At the end of every countdown, the timer sets the countdown Timer Flag (bit TF in register Control2). Bit TF can only
be cleared by command. The asserted bit TF can be used to generate an interrupt at pin ̅̅̅̅̅
INT. The interrupt may begenerated as a pulsed signal every countdown period or as a permanently active signal which follows the conditionof bit TF. Bit TI_TP is used to control this mode selection and the interrupt output may be disabled with bit TIE (seeTIMER REGISTERS, 11h – Timer Mode; and Figure “General countdown timer behavior” above).
When reading the Timer Value, the current countdown value is returned and not the initial Timer Value. Since it is
not possible to freeze the countdown timer counter during read back, it is recommended to read the register twiceand check for consistent results.
The Timer Clock Frequencies 64 Hz (only in MODE = 1), 1 Hz and 1⁄60 Hz can be affected by the Offset register.
The duration of a programmed period varies according to when the offset is initiated (OFFSET not 00h). For example,
if a 100 s timer is set using the 1 Hz clock as source, then some 100 s periods will contain compensation pulses andtherefore be longer or shorter depending on the setting of the Offset register (see FREQUENCY OFFSETCOMPENSATION).

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4.8. MINUTE AND HALF MINUTE INTERRUPT FUNCTION
The Minute Interrupt (bit MI) and Half Minute Interrupt (bit HMI) are pre-defined timers for generating interrupt pulses
on pin ̅̅̅̅̅
INT (see following Figure). The timers are running in sync with the seconds counter (see TIME AND DATEREGISTERS, 04h - Seconds).
The minute and half minute interrupts must only be used when the frequency offset is set to normal mode (MODE =̅̅̅̅̅ are 15.625 ms0), see FREQUENCY OFFSET COMPENSATION. In normal mode, the interrupt pulses on pin INT
wide.
When starting MI, the first interrupt will be generated after 1 second to 59 seconds. When starting HMI, the firstinterrupt will be generated after 1 second to 29 seconds.
Subsequent periods do not have such a delay. The timers can be enabled independently from one another. However,a Minute Interrupt enabled on top of a Half Minute Interrupt is not distinguishable.
̅̅̅̅̅
INT example for MI:
seconds counter

58

59

minutes counter

59

00

11

12

00

01

INT when MI enabled
TF when MI enabled̅̅̅̅̅ is set to Pulse ModeIn this example, the TF flag is not cleared after an interrupt and the pin INT(TI_TP bit = 1).
̅̅̅̅̅ generation:
Effect of bits MI and HMI on INT
Minute Interrupt (bit MI)

Half Minute Interrupt (bit HMI)

0
1
0
1

0
0
1
1

ResultNo interrupt generated
Interrupt every minuteInterrupt every 30 seconds

The duration of the timer is affected by the register Offset (see CONTROL REGISTERS, 02h – Offset Register). Only
when OFFSET has the value 00h the periods are consistent.

4.8.1.PULSE GENERATOR 1
When the Timer Pulse Mode is activated (TI_TP = 1) the Pulse Generator 1 for the HMI and MI Interrupt Functionuses an internal clock.
The minute and half minute interrupts must only be used when the frequency offset is set to normal mode (MODE =̅̅̅̅̅ are 15.625 ms wide. TF and INT̅̅̅̅̅ become active simultaneously.
0). In normal mode, the interrupt pulses on pin INT

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4.9. FREQUENCY OFFSET COMPENSATIONThe RV-8263-C8 incorporates an Offset register (see CONTROL REGISTERS, 02h – Offset Register) which can beused by customer to compensate the frequency offset of the 32.768 kHz oscillator which allows implementing
functions, such as: Improve time accuracy
 Aging compensation
02h – Offset Register:
Address

Function

Bit 7

02h

Offset
Reset

MODE
0

Bit

Symbol

Value

7

MODE

0
1

6:0

OFFSET-64 to
+63

Bit 6
0

Bit 5
0

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0

OFFSET00

0

0

Description
Offset Mode
Normal Mode: Offset is made once every two hours.
Fast Mode: Offset is made every 4 minutes.
Offset value.
For MODE = 0, each LSB introduces an offset of 4.34 ppm. For MODE = 1,
each LSB introduces an offset of 4.069 ppm. The values of 4.34 ppm and4.069 ppm are based on a nominal 32.768 kHz clock. The offset value iscoded in two’s complement giving a range of +63 LSB to -64 LSB.

OFFSET

OFFSET compensation value
in decimalCompensation pulses
in steps

01111110111110:0000001
0000000

63
62
:
1
0

+63
+62
:
+1
0

11111111111110:
1000001
1000000

127
126
:
65
64

-1
-2
:
-63
-64

CLKOUT offset value
in ppm(1)Normal Mode
Fast Mode
MODE = 0
MODE = 1+273.420+256.347+269.080+252.278::+4.340+4.06900-4.340-8.680:-273.420-277.760-4.069-8.138:-256.347-260.416(1) The frequency offset measured at CLKOUT pin can be compensated by computing the compensation value OFFSET and writing it into

the Offset register (see OFFSET COMPENSATION CALCULATION WORKFLOW).

The compensation is made by adding or subtracting clock compensation pulses. The affects to the different
frequencies are listed below.
CLKOUT frequencies:
 1 Hz can be affected
 1.024 kHz to 32.768 kHz are not affected
Timer Clock frequencies: MODE = 0 (Normal Mode):
o 1/60 Hz and 1 Hz can be affected
o 64 Hz and 4.096 kHz are not affected MODE = 1 (Fast Mode):
o 1/60 Hz, 1 Hz and 64 Hz can be affected
o 4.096 kHz is not affected

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4.9.1.OFFSET COMPENSATION CALCULATION WORKFLOW
Offset compensation calculation workflow:
ExampleMeasure the frequency on pin CLKOUT:
fCLKOUT

32768.48 Hz

Compute the CLKOUT offset value in ppm:
Offset [ppm] = ((fCLKOUT – 32768) / 32768) * 1 000 000

14.648 ppm

Compute the CLKOUT offset value in compensation
pulses:
MODE = 0 (Normal Mode):
Pulses = Offset [ppm] / 4.34 ppm
MODE = 1 (Fast Mode):
Pulses = Offset [ppm] / 4.069 ppm

3.375 3 compensaton pulses
are neededor3.600  4 compensaton pulses
are needed

Compute the OFFSET compensation value:

If Pulses > +63 or < -64, fCLKOUT is out of range to becorrected.
Else if 0
Else if -64

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PulsesPulses63, set OFFSET = Pulses.

OFFSET = 3 (MODE = 0)
= 4 (MODE = 1)

-1, set OFFSET = Pulses + 128.

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Result of the offset compensation (Example):

(2)
(1)

-6

-4

-2

0

2

4

6

Reachable
accuracy zone

8

10

12

14

16

Offset [ppm]Measured/calculatedOffset [ppm] 14.648 ppm(32768.48 Hz)

With the offset compensation the accuracy of ±2.17 ppm (0.5 * offset per LSB) can be reached (see CONTROLREGISTERS, 02h – Offset Register).
±1 ppm corresponds to a time deviation of 0.0864 seconds per day.
(1) MODE = 0: Deviation after compensation = Offset [ppm] – compensation pulses * 4.34 ppm= 14.648 ppm – 3 * 4.34 ppm = +1.628 ppm(2) MODE = 1: Deviation after compensation = Offset [ppm] – compensation pulses * 4.069 ppm= 14.648 ppm – 4 * 4.069 ppm = -1.628 ppm

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4.10. COMPENSATION INTERRUPT FUNCTION
It is possible to monitor when compensation pulses are applied. To enable Compensation Interrupt generation, bit
CIE (register Control1) has to be set logic 1. At every compensation cycle a pulse is generated on pin ̅̅̅̅̅
INT by the
Pulse Generator 3. The pulse width depends on the Offset Mode (MODE bit). If multiple compensation pulses areapplied, an interrupt pulse is generated for each compensation pulse applied.

4.10.1. COMPENSATION PULSES WHEN MODE = 0 (NORMAL MODE)
The compensation is triggered once every two hours and then compensation pulses are applied once per minuteuntil the programmed offset value has been compensated.
Compensation pulses when MODE = 0:Compensation pulses
in steps

Update every nth hourCompensation pulses on̅̅̅̅̅
INT per minute(1)Minute+1 or -1
+2 or -2
+3 or -3:
+59 or -59+60 or -60

200
200 and 01
200, 01, and 02::
2
00 to 58
2
00 to 59
2
00 to 59
+61 or -61
2nd and next hour00
200 to 59
+62 or -62
2nd and next hour
00 and 01
2
00 to 59
+63 or -63
2nd and next hour00, 01, and 02
2
00 to 59
-64
2nd and next hour00, 01, 02, and 03(1) When MODE = 0, the compensation pulses on pin INT̅̅̅̅̅ are 15.625 ms wide.

1
1
1
:
1
1
1
1
1
1
1
1
1
1

In MODE = 0, CLKOUT and Timer Clock frequencies < 64 Hz are affected by the compensation pulses.
Effect of compensation pulses on frequencies when MODE = 0:
Frequency

Effect of compensation

32.768 kHz
16.384 kHz
8.192 kHz4.096 kHz2.048 kHz1.024 kHz
1 Hz

no effectno effectno effectno effectno effectno effect
Frequency affected

4.096 kHz
64 Hz
1 Hz
1/60 Hzno effectno effect
Periods affected
Periods affected

CLKOUT

Timer Clock

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4.10.2. COMPENSATION PULSES WHEN MODE = 1 (FAST MODE)
The compensation is triggered once every four minutes and then compensation pulses are applied once per second
up to a maximum of 60 pulses. When compensation values greater than 60 pulses are used, additional compensation
pulses are made in the 59th second.
Clock compensation is made more frequently in MODE = 1; resulting in slightly higher power consumption.
Compensation pulses when MODE = 1:
Compensation pulses
in steps

Update every nth minute

SecondCompensation pulses on̅̅̅̅̅
INT per second(1)+1 or -1
+2 or -2
+3 or -3:
+59 or -59+60 or -60

4
4
4
:
4
4
4
4
4
4
4
4
4
4

00
00 and 01
00, 01, and 02:
00 to 58
00 to 59
00 to 58
59
00 to 58
59
00 to 58
59
00 to 58
59

1
1
1
:
1
1
1
2
1
3
1
4
1
5

+61 or -61+62 or -62+63 or -63-64(1) When MODE = 1, the compensation pulses on pin INT̅̅̅̅̅ are 977 µs wide. For multiple pulses, they are repeated at an interval of 1.953 ms.

In MODE = 1, CLKOUT or Timer Clock frequencies < 1.024 kHz are affected by the compensation pulses.
Effect of compensation pulses on frequencies when MODE = 1:
Frequency

Effect of compensation

32.768 kHz
16.384 kHz
8.192 kHz4.096 kHz2.048 kHz1.024 kHz
1 Hz

no effectno effectno effectno effectno effectno effect
Frequency affected

4.096 kHz
64 Hz
1 Hz
1/60 Hzno effect
Periods affected
Periods affected
Periods affected

CLKOUT

Timer Clock

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4.11. CLKOUT FREQUENCY SELECTION
A programmable square wave is available at pin CLKOUT. Operation is controlled by the FD field in the register
Control2. Frequencies of 32.768 kHz (default) down to 1 Hz can be generated for use as a system clock,microcontroller clock, input to a charge pump, or for calibration of the crystal oscillator.
Pin CLKOUT is a push-pull output and enabled at power-on. CLKOUT can be disabled by setting the FD field to 111
or by setting CLKOE LOW. When disabled, the CLKOUT is LOW.
The duty cycle of the selected clock is not controlled. However, due to the nature of the clock generation, all are 50: 50 except the 32.768 kHz frequency.
The STOP bit function can also affect the CLKOUT signal, depending on the selected frequency. When the STOP
bit is set logic 1, the CLKOUT pin generates a continuous LOW for those frequencies that can be stopped (for moredetails, see STOP BIT FUNCTION).
FD

CLKOUT Frequency

Typical duty cycle

Effect of STOP bit

000
001
010
011
100
101
110
111

32.768 kHz – Default value
16.384 kHz
8.192 kHz4.096 kHz2.048 kHz1.024 kHz50 ±10 %
50 %
50 %
50 %
50 %
50 %
50 %
-

no effectno effectno effect
CLKOUT = LOW
CLKOUT = LOW
CLKOUT = LOW
CLKOUT = LOW

1 Hz (1)
CLKOUT = LOW-(1) 1 Hz clock pulses are affected by compensation pulses (see FREQUENCY OFFSET COMPENSATION).

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4.12. STOP BIT FUNCTION
The function of the STOP bit is to allow for accurate starting of the time circuits.
The STOP bit function causes the upper part of the prescaler (F2 to F14) to be held in reset and thus no 1 Hz ticks
are generated. The STOP bit function will not affect the CLKOUT of 32.768 kHz, 16.384 kHz and 8.192 kHz (seealso CLKOUT FREQUENCY SELECTION).
STOP bit functional diagram:

OSCILLATOR

F0

2 Hz

1
0

F1

setting the OS fla g

4.096 kHz8.192 kHz16.384 kHz

32.768 kHz

OSCILLATOR STOP
DETECTOR

F2

F13

F14

RESET

RESET

RESET

1 Hz tick

STOP

The time circuits can then be set and do not increment until the STOP bit is released (see following Table and Figure).
First increment of time circuits after STOP bit release:
STOP bit

Prescaler bits 1)
F0F1-F2 to F14

1 Hz tickTime
hh:mm:ss

Comment

Clock is running normally0
01-0 0001 1101 0100
12:45:12
Prescaler counting normally
STOP bit is activated by user. F0F1 are not reset and values cannot be predicted externally1
XX-0 0000 0000 0000
12:45:12
Prescaler is reset; time circuits are frozen
New time is set by user
1
XX-0 0000 0000 0000
08:00:00
Prescaler is reset; time circuits are frozen
STOP bit is released by user
08:00:00
0
XX-0 0000 0000 0000
Prescaler is now running
08:00:00
XX-1 0000 0000 0000
08:00:00
XX-0 1000 0000 0000
0.507 813
08:00:00
toXX-1 1000 0000 0000
0.507 935 s:::
11-1 1111 1111 1110
08:00:00
00-0 0000 0000 0001
08:00:01
0 to 1 transition of F14 increments the time circuits
10-0 0000 0000 0001
08:00:01:::
11-1 1111 1111 1111
08:00:01
1.000 000 s
00-0 0000 0000 0000
08:00:01
10-0 0000 0000 0000
08:00:01:::
11-1 1111 1111 1110
08:00:01
00-0 0000 0000 0001
08:00:02
0 to 1 transition of F14 increments the time circuits
10-0 0000 0000 0001
08:00:02
1)
F0 is clocked at 32.768 kHz.

The lower two stages of the prescaler (F0 and F1) are not reset. And because the I2C-Bus is asynchronous to the
crystal oscillator, the accuracy of restarting the time circuits is between zero and one 8.192 kHz cycle (see following
Figure).

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STOP bit release timing:
8192 Hzstop released
0 µs to 122 µs

The first increment of the time circuits is between 0.507813 s and 0.507935 s after STOP bit is released. The
uncertainty is caused by the prescaler bits F0 and F1 not being reset (see Table above) and the unknown state of the
32 kHz clock.

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5. I2C INTERFACEThe I2C interface is for bidirectional, two-line communication between different ICs or modules. The RV-8263-C8 isaccessed at addresses A2h/A3h, and supports Fast Mode (up to 400 kHz). The I 2C interface consists of two lines:
one bi-directional data line (SDA) and one clock line (SCL). Both lines are connected to a positive supply via pull-up
resistors. Data transfer is initiated only when the interface is not busy.

5.1. BIT TRANSFER
One data bit is transferred during each clock pulse. The data on the SDA line remains stable during the HIGH periodof the clock pulse, as changes in the data line at this time are interpreted as a control signals. Data changes should
be executed during the LOW period of the clock pulse (see Figure below).
Bit transfer:
SDA
SCL
data line
stable;data validchange ofdataallowed5.2. START AND STOP CONDITIONSBoth data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while
the clock is HIGH, is defined as the START condition (S). A LOW-to-HIGH transition of the data line, while the clock
is HIGH, is defined as the STOP condition (P) (see Figure below).
Definition of START and STOP conditions:

SDA

SDA

SCL

SCL
S

P

START condition

STOP condition

A START condition which occurs after a previous START but before a STOP is called a Repeated START condition,and functions exactly like a normal STOP followed by a normal START.
Caution:When communicating with the RV-8263-C8 module, the series of operations from transmitting the START condition
to transmitting the STOP condition should occur within 1 second.
If this series of operations requires 1 second or longer, the I2C bus interface will be automatically cleared and set
to standby mode by the bus timeout function of the RV-8263-C8 module. Note with caution that both write and read
operations are invalid for communications that occur during or after this auto clearing operation (when the read
operation is invalid, all data that is read has a value of FFh).
Restarting of communications begins with transfer of the START condition again.

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5.3. DATA VALID
After a START condition, SDA is stable for the duration of the high period of SCL. The data on SDA may be changed
during the low period of SCL. There is one clock pulse per bit of data. Each data transfer is initiated with a START
condition and terminated with a STOP condition. The number of data bytes transferred between the START and
STOP conditions is not limited (however, the transfer time must be no longer than 1 second). The information istransmitted byte-wise and each receiver acknowledges with a ninth bit.

5.4. SYSTEM CONFIGURATION
Since multiple devices can be connected with the I2C-bus, all I2C-bus devices have a fixed and unique device number
built-in to allow individual addressing of each device.
The device that controls the I2C-bus is the Master; the devices which are controlled by the Master are the Slaves. A
device generating a message is a Transmitter; a device receiving a message is the Receiver. The RV-8263-C8 acts
as a Slave-Receiver or Slave-Transmitter.
Before any data is transmitted on the I2C-bus, the device which should respond is addressed first. The addressing isalways carried out with the first byte transmitted after the START procedure. The clock signal SCL is only an input
signal, but the data signal SDA is a bidirectional line.
System configuration:SDA
SCLMASTER
TRANSMITTERRECEIVER

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SLAVE
RECEIVERSLAVE
TRANSMITTERRECEIVER

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5.5. ACKNOWLEDGE
The number of data bytes transferred between the START and STOP conditions from transmitter to receiver isunlimited (however, the transfer time must be no longer than 1 second). Each byte of eight bits is followed by anacknowledge cycle.
 A slave receiver, which is addressed, must generate an acknowledge cycle after the reception of eachbyte.
 Also a master receiver must generate an acknowledge cycle after the reception of each byte that has beenclocked out of the slave transmitter.
 The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that
the SDA line is stable LOW during the HIGH period of the acknowledge-related clock pulse (set-up andhold times must be taken into consideration).
 A master receiver must signal an end of data to the transmitter by not generating an acknowledge cycle on
the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line
HIGH to enable the master to generate a STOP condition.
Data transfer and acknowledge on the I2C-bus:
data output
by transmitter
not acknowledge
data output
by receiveracknowledge
SCL from
master1

2

START
condition

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8

9S
clock pulse for
acknowledgement

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5.6. SLAVE ADDRESS
On the I2C-bus the 7-bit slave address 1010001b is reserved for the RV-8263-C8. The entire I2C-bus slave address
byte is shown in the following table.
Slave address

R/W

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

1

0

1

0

0

0

1

Transfer data

Bit 0
1(R)

A3h (read)A2h (write)0(W)After a START condition, the I2C slave address has to be sent to the RV-8263-C8 device. The R/W bit defines the
direction of the following single or multiple byte data transfer. The 7-bit address is transmitted MSB first. If this address
is 1010001b, the RV-8263-C8 is selected, the eighth bit indicates a read ( R/W = 1) or a write ( R/W = 0) operation(results in A3h or A2h) and the RV-8263-C8 supplies the ACK. The RV-8263-C8 ignores all other address values
and does not respond with an ACK.
In the write operation, a data transfer is terminated by sending either the STOP condition or the START condition of
the next data transfer.

5.7. WRITE OPERATION
Master transmits to Slave-Receiver at specified address. The Register Address is an 8-bit value that defines which
register is to be accessed next. After writing one byte, the Register Address is automatically incremented by 1.
Master writes to slave RV-8263-C8 at specific address:
1) Master sends out the START condition.
2) Master sends out Slave Address, A2h for the RV-8263-C8; the R/W bit is a 0 indicating a write operation.
3) Acknowledgement from RV-8263-C8.
4) Master sends out the Register Address to RV-8263-C8.
5) Acknowledgement from RV-8263-C8.
6) Master sends out the Data to write to the specified address in step 4).
7) Acknowledgement from RV-8263-C8.
8) Steps 6) and 7) can be repeated if necessary.
The address is automatically incremented in the RV-8263-C8.
9) Master sends out the STOP Condition.

2S

SLAVE ADDRESS

3

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4

5

0 A REGISTER ADDRESS A
R/W

1

6

7

8

DATA

A

DATA

9
A P

Acknowledge from RV-8263-C8

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5.8. READ OPERATION AT SPECIFIC ADDRESS
Master reads data from slave RV-8263-C8 at specific address:
1)
2)
3)
4)
5)
6)
7)
8)

Master sends out the START condition.
Master sends out Slave Address, A2h for the RV-8263-C8; the R/W bit is a 0 indicating a write operation.
Acknowledgement from RV-8263-C8.
Master sends out the Register Address to RV-8263-C8.
Acknowledgement from RV-8263-C8.
Master sends out the Repeated START condition (or STOP condition followed by START condition).
Master sends out Slave Address, A3h for the RV-8263-C8; the R/W bit is a 1 indicating a read operation.
Acknowledgement from RV-8263-C8.
At this point, the Master becomes a Receiver and the Slave becomes the Transmitter.
9) The Slave sends out the Data from the Register Address specified in step 4).
10) Acknowledgement from Master.
11) Steps 9) and 10) can be repeated if necessary.
The address is automatically incremented in the RV-8263-C8.
12) The Master, addressed as Receiver, can stop data transmission by not generating an acknowledge on thelast byte that has been sent from the Slave-Transmitter. In this event, the Slave-Transmitter must leave thedata line HIGH to enable the Master to generate a STOP condition.
13) Master sends out the STOP condition.

S

SLAVE ADDRESS

3

4

7

8

9

10

11

12 13

SLAVE ADDRESS

1 A

DATA

A

DATA

A P

5 6

0 A REGISTER ADDRESS A S

R/W

2

R/W

1

Repeated
START
Acknowledge from RV-8263-C8

Acknowledge from MasterNot-acknowledge from Master5.9. READ OPERATION
Master reads data from slave RV-8263-C8 immediately after first byte:
1) Master sends out the START condition.
2) Master sends out Slave Address, A3h for the RV-8263-C8; the R/W bit is a 1 indicating a read operation.
3) Acknowledgement from RV-8263-C8.
At this point, the Master becomes a Receiver and the Slave becomes the Transmitter.
4) The RV-8263-C8 sends out the Data from the last accessed Register Address incremented by 1.
5) Acknowledgement from Master.
6) Steps 4) and 5) can be repeated if necessary.
The address is automatically incremented in the RV-8263-C8.
7) The Master, addressed as Receiver, can stop data transmission by not generating an acknowledge on thelast byte that has been sent from the Slave-Transmitter. In this event, the Slave-Transmitter must leave thedata line HIGH to enable the Master to generate a STOP condition.
8) Master sends out the STOP condition.

2

3

4

5

6

7 8

S

SLAVE ADDRESS

1 A

DATA

A

DATA

A P

R/W

1

Acknowledge from RV-8263-C8

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6. ELECTRICAL SPECIFICATIONS
6.1. ABSOLUTE MAXIMUM RATINGS
The following Table lists the absolute maximum ratings.
Absolute Maximum Ratings according to IEC 60134:
SYMBOLPARAMETER

VDD
IDD
VI
VO
II
IO
PTOT

Power supply voltage
Power supply current
Input voltage
Output voltage
Input current
Output current
Total power dissipation

VESD

Electrostatic discharge
Voltage

ILU
TOPR
TSTO
TPEAK

Latch-up current
Operating temperature
Storage temperature
Maximum reflow condition

CONDITIONSAt any input
At any output

MIN

MAX

UNIT

-0.5
-50
-0.5
-0.5
-10
-10

6.5
50
6.5
6.5
10
10
300
±5000
±2000
200
85
125
265

V
mA
V
V
mA
mA
mW
V
V
mA
°C
°C
°C

(1)

HBM
CDM

(2)
(3)

Stored as bare product
JEDEC J-STD-020C

-40
-55

(1) HBM: Human Body Model, according to JESD22-A114.
(2) CDM: Charged-Device Model, according to JESD22-C101.
(3) Latch-up testing, according to JESD78, at maximum ambient temperature (TJune 2023

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6.2. OPERATING PARAMETERS
For this Table, TA = -40 to +85°C unless otherwise indicated. VDD = 0.9 to 5.5 V, TYP values at 25°C and 3.0 V.
Operating Parameters:
SYMBOLPARAMETERCONDITIONS

MIN

TYP

MAX

UNIT

Supplies
VDD

Power supply voltage

IDD

VDD supply current timekeeping.
CLKOUT disabled;
Interface inactive, fSCL = 0 Hz (3)IDD

VDD supply current timekeeping.
CLKOUT disabled;
Interface active, fSCL = 400 kHz

Time-keeping mode; interface(1)
inactive; fSCL = 0 Hz
Interface active;(2)
fSCL = 400 kHz
VDD = 3.0 V, TA = 25°C
VDD = 3.0 V, TA = 50°C
VDD = 3.0 V, TA = 85°C

0.9

5.5

1.8

5.5

V

(4)

VDD = 3.0 V

InputsVI
VIL
VIH

Input voltage
LOW level input voltage
HIGH level input voltage

ILEAK

Input leakage current

CI

Input capacitance

Outputs
VOH
VOL

HIGH level output voltage
LOW level output voltage

On pin CLKOUT
On pins SDA, ̅̅̅̅̅
INT, CLKOUT

IOH

HIGH level output current

On pin CLKOUT
VOH = 2.6 V, VDD = 3.0 V

190
230
450

450
500
600

nA

18

50

µA

VDD +0.5
0.3 VDD
VDD
±0.5

V
V
V
µA
µA

7

pF

VDD
0.2 VDDVV

VSS -0.5
VSS
0.7 VDD
VI = VSS or VDD
VI = VSS or VDD, post ESD event
On pins SDA, SCL and
(5)
CLKOE

0

0.8 VDD
VSS
Output source current
1

3

mA

Output sink current
On pin SDA
3
8.5mA
VOL = 0.4 V, VDD = 3.0 V
̅̅̅̅̅
IOL
LOW level output current
On pin INT
26mA
VOL = 0.4 V, VDD = 3.0 V
On pin CLKOUT
1
3mA
VOL = 0.4 V, VDD = 3.0 V(1) For reliable oscillator start-up at power-on, V greater than 1.2 V has to be applied. If powered up at 0.9 V, t
DD
START might be a little higher,
especially at high temperature. Normally the power supply is not 0.9 V at start-up and only occurs at the end of a battery discharge.
VDD min of 0.9 V is specified so that the customer can calculate the dimension of a battery or capacitor for a specific application. VDD minof 1.2 V or greater is needed to ensure speedy oscillator start-up time.
(2) 400 kHz I2C operation is production tested at 1.8 V. Design methodology allows I2C operation at 1.8 V - 5 % (1.71 V) which has beenverified during product characterization on a limited number of devices.
(3) Timer source clock = 1⁄60 Hz; level of pins SCL and SDA is V or V .
DD
SS(4) Tested on sample basis.
(5) Implicit by design.

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I2C active. Typical IDD with respect to fSCL:
50
IDD
[µA]
40
(1)

30

20
(2)

10

0
0

100

200

300

500

400
fSCL [kHz]

(1)
(2)

TA = 25°C; CLKOUT disabled.
VDD = 5.5 V.
VDD = 3.0 V.

Timekeeping mode. Typical IDD as a function of temperature:
800
IDD
[nA]
600

400
(1)

(2)

200

0
-50

(1)
(2)

June 2023

-30

-10

10

30

50

70
Temperature [°C]90

CLKOUT disabled.
VDD = 5.5 V.
VDD = 3.0 V.

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Timekeeping mode. Typical IDD with respect to VDD:
300
IDD
[nA]
250
200
150

100
50
0

0

1

2

3

4

5

4

5

VDD [V]6

TA = 25°C; timer clock frequency = 1/60 Hz; CLKOUT disabled.

Oscillator frequency variation with respect to VDD:
10f/f[ppm] 8
6
4
2

0
-2
-4
-6
-8
-10
0

1

2

3

6
VDD [V]TA = 25°C, normalized to VDD = 3 V

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6.3. OSCILLATOR PARAMETERS
For this Table, TA = -40 to +85°C unless otherwise indicated. VDD = 0.9 to 5.5 V, TYP values at 25°C and 3.0 V.
Oscillator Parameters:
SYMBOLPARAMETER

Xtal GeneralftSTART

Crystal Frequency
Oscillator start-up time

δCLKOUT

CLKOUT duty cycle

CONDITIONSMINFCLKOUT = 32.768 kHz
TA = 25°C

TYP

MAX

UNIT

32.768
0.2

2

kHz
s

60

%

±20

ppm

40

Xtal Frequency Characteristics
Δf/f

F = 32.768 kHz
TA = 25°C, VDD = 3.0 V

Frequency accuracy

Frequency vs. voltage
characteristics
Frequency vs. temperature
TOPR = -40°C to +85°C
Δf/fTOPR
characteristics
VDD = 3.0 V
T0
Turnover temperatureΔf/fAging first year max.
TA = 25°C, VDD = 3.0 V
Frequency Offset Compensation
OFFSET value when MODE = 0:Δt/tMin. comp. step (LSB) andTA = -40°C to +85°C
Max. comp. range
OFFSET value when MODE = 1:
Δt/tMin. comp. step (LSB) andTA = -40°C to +85°C
Max. comp. range
Calibrated at an initialΔt/tAchievable time accuracy
temperature and voltage

±10

Δf/V

±1

ppm/V

-0.035ppm/°C2 (TOPR-T0)2 ±10%

ppm

20

30
±3

°C
ppm

±4.34

+273.4/-277.8ppm±4.069+256.3/-260.4

ppm

-2.17

+2.17

ppm

6.3.1.XTAL FREQUENCY VS. TEMPERATURE CHARACTERISTICS

20
T0 = 25°C (± 5°C)
0-20

f/f [ppm]

-40
-60
-80
f/f = -0.035 * (T-T0)2 ppm (±10%)

-100
-120
-140
-160
-180
-50

June 2023

-40

-30

-20

-10

0

10
20
30
40
Temperature T [°C]

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50

60

70

80

90

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Ultra-Small Real-Time Clock Module with I2C-Bus Interface

RV-8263-C8

6.4. I2C-BUS CHARACTERISTICS
The following Figure and Table describe the I2C AC electrical parameters.
I2C AC Parameter Definitions:

SDA

t BUF

t VD:DAT

t LOW

or t

t HD:DATt SU:DATVD:ACKSCLt HD:STAt HIGHt RISEPt FALLSt SU:STOt SU:STA

SDA

Sr

P

For the following Table, VDD = 1.8 to 5.5 V, TA = -40°C to +85°C.
I2C AC Electrical Parameters:
SYMBOL
fSCL
tLOW
tHIGH
tRISE
tFALL
tHD:STAtSU:STAtSU:DATtHD:DATtSU:STOtBUF
tVD:DATtVD:ACKtSP
CbPARAMETER
SCL input clock frequency
Low period of SCL clock
High period of SCL clock
Rise time of SDA and SCL
Fall time of SDA and SCL
START condition hold time
START condition setup time
SDA setup time
SDA hold time
STOP condition setup time
Bus free time before a new transmission
Data valid time
Data valid acknowledge time
Spike pulse width
Capacitive load for each bus line

MIN

MAX

UNIT

0
1.3
0.6
20
20 x (VDD / 5.5 V)
0.6
0.6
100
0
0.6
1.3
0
0
0

400

kHz
µs
µs
ns
ns
µs
µs
ns
µs
µs
µs
µs
µs
ns
pF

300
300

0.9
0.9
50
400

S = Start condition, Sr = Repeated Start condition, P = Stop condition

Caution:When communicating with the RV-8263-C8 module, the series of operations from transmitting the START (orrepeated START) condition to transmitting the STOP (or repeated START) condition should occur within 1 second.
If this series of operations requires 1 second or more, the I 2C-bus interface will be automatically cleared and set tostandby mode by the bus timeout function of the RV-8263-C8 module.

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7. APPLICATION INFORMATION
7.1. OPERATING RV-8263-C8

100 nF

1

2
VDD

RV-8263-C8

VDD
INT

INT

SCL

SCL

SDA

SDA

CLKOE

GPIO

VDD

MCU

VSS
VSS

1
2
3

CLKOUT

3

A 100 nF decoupling capacitor is recommended close to the device.
̅̅̅̅̅ output is an open drain and requires a pull-up resistor to VDD.
The INT
CLKOUT offers selectable frequencies from 32.768 kHz to 1 Hz for application use. If not used, it isrecommended to disable CLKOUT for optimized current consumption by setting FD to 111b or by pulling
CLKOE LOW. When disabled, the CLKOUT is LOW.
Further current minimization can be achieved by turn off the timer (TE = 0) and setting the timer clock
frequency to 1/60 Hz (TD = 11b).

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7.2. OPERATING RV-8263-C8 WITH BACKUP CAPACITOR
An external diode-circuitry can be wired to ensure standby or back-up supply. With the RTC in its minimum power
configuration (see OPERATING RV-8263-C8) the RTC with a supercapacitor may operate for weeks and with abattery for years.

6

5

4
BackupSupercap
or Battery

7

100 nF

CLKOE

VDD_RTC

RV-8263-C8

VDD
INT

INT

SCL

SCL

SDA

SDA

VDD

MCU

VSS

VSS

4
5

6

7

CLKOUT

Supercapacitor (e.g. 1 farad), primary battery or secondary battery LMR (respect manufacturer
specifications for constant charging voltage).
When using a supercapacitor, a resistor is used to limit the inrush current into the supercapacitor at
power-on. E.g. to comply with the maximum forward current of the schottky diode.
or
When using a battery, a resistor is used to limit the maximum current in case of a short circuit.
Schottky diode. This low VF diode (less than 0.3 V) is needed to not exceed the specified maximum voltage
at the inputs of the RV-8263-C8 when normal supply voltage VDD is present (VI_MAX = VDD_RTC +0.5 V).
Schottky diodes have considerable leakage currents. To optimize backup time it is recommended to selecta low leakage Schottky (e.g. BAS70-05).
̅̅̅̅̅) are required in backup mode (VDD_RTC)
If the clock signal (pin CLKOUT) and/or the interrupt signal (pin INT̅̅̅̅̅ pin have to be connected to VDD_RTC.
the CLKOE pin and/or the pull-up resistor for the INT

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8. PACKAGE
8.1. DIMENSIONS AND SOLDER PAD LAYOUT
RV-8263-C8 Package:
Package dimensions (bottom view):

Recommended solder pad layout:

2,0

0,54

0,54

0,54

0,54

8

7

6

5

0,7

4

0,3

3

0,42

2

1,2

1

0,7

0,27

0,27

0,70 max

1,89

Metal lid is connected to VSS (pin #4)
Dimensions:
Tolerances:
Drawing:

in mmunless otherwise specified ±0.1 mm
RV-8263-C8_Pack-drw_20230623

8.1.1.RECOMMENDED THERMAL RELIEF
When connecting a pad to a copper plane, thermal relief is recommended.
RV-C8 Package:
GOOD

BAD

P
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Ultra-Small Real-Time Clock Module with I2C-Bus Interface

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8.2. MARKING AND PIN #1 INDEX
Laser marking RV-8263-C8 Package: (top view)

Product Date Code
#8

#5

M318A18263#1

M318A1
M
Micro Crystal

3
Year

18
Week

A1
Batch

#4
Part Designation

Pin 1 Index

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9. MATERIAL COMPOSITION DECLARATION & ENVIRONMENTAL INFORMATION
9.1. HOMOGENOUS MATERIAL COMPOSITION DECLARATION
Homogenous material information according to IPC-1752 standard
Material Composition RV-8263-C8:
4

5

2

1

8
3
6
7

(Symbolic drawing)
No.

Item
Component
Name

Sub ItemMaterial
Name

Material
Weight
(mg)
(%)

1
2

Resonator
Electrodes

Quartz Crystal
Cr+Au

0.099

3
4

Housing
Metal Lid

Ceramic
Kovar Lid

2.92

0.0035

100%
3%
97%
100%
91%

Substance
Element
SiO2
Cr
Au
Al2O3
Fe53Ni29Co18

5

Seal

6

Terminations

7
8

Resonator
attachCMOS IC

June 2023

0.15Internal and externalterminals

0.48Gold bumps

Cr:
Au:

8.9%
0.1%
80%
20%
80%
15%
5%

Ni
Au

Mo
Ni
Au, 0.5 micron

Fe:
Ni:
Co:
Ni:
Au:
Au:
Sn:
Mo:
Ni:
Au:

1.10
Ni-plating
Au-plating
Solder Preform

CAS
NumberAu80 / Sn2014808-60-7
7440-47-3
7440-57-5
1344-28-1
7439-89-6
7440-02-0
7440-48-4
7440-02-0
7440-57-5
7440-57-5
7440-31-5
7439-98-7
7440-02-0
7440-57-5

0.011

100%

Au

Au:

7440-57-5

SiliconGold bumps

0.29

90%
10%

Si
Au

Si:
Au:

7440-21-3
7440-57-5

Unit weight

5.05

54/61

Comment

Metal Lid (Kovar)
Nickel platingGold plating
Premelted on
Metal Lid
Molybdenum
Nickel platingGold plating

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Ultra-Small Real-Time Clock Module with I2C-Bus Interface

RV-8263-C8

9.2. MATERIAL ANALYSIS & TEST RESULTS
Homogenous material information according to IPC-1752 standard
No.
Item
Sub Item
RoHS
Component
Material
Name
Name

Cd

Hg

Cr(VI)

PBB

PBDE

F

CI

Br

I

BBP

DBP

DEHP

DIBP

Phthalates

Pb

Halogens

1

Resonator

Quartz Crystal

nd

nd

nd

nd

nd

nd

nd

nd

nd

nd

nd

nd

nd

nd

2

Electrodes

Cr+Au

nd

nd

nd

nd

nd

nd

nd

nd

nd

nd

nd

nd

nd

nd

3

Housing

Ceramic

nd

nd

nd

nd

nd

nd

nd

nd

nd

nd

nd

nd

nd

nd

4

Metal Lid

Kovar Lid & Plating

nd

nd

nd

nd

nd

nd

nd

nd

nd

nd

nd

nd

nd

nd

5

Seal

Solder Preform

nd

nd

nd

nd

nd

nd

nd

nd

nd

nd

nd

nd

nd

nd

6

Terminations

Int. & ext. terminals

nd

nd

nd

nd

nd

nd

nd

nd

nd

nd

nd

nd

nd

nd

7

Resonator
attachGold bumps

nd

nd

nd

nd

nd

nd

nd

nd

nd

nd

nd

nd

nd

nd

8

CMOS IC

Silicon & Gold bumps

nd

nd

nd

nd

nd

nd

nd

nd

nd

nd

nd

nd

nd

nd

MDL [ppm]

Method Detection Limit

2

8

5

50

50

nd (not detected) = below “Method Detection Limit” (MDL)
Test methods:
RoHS Pb, Cd
 Hg
 Cr(VI) PBB / PBDE
Halogens
Phthalates

June 2023

Test method with reference to:
IEC 62321-5:2013
IEC 62321-4:2013 + AMD1:2017
IEC 62321-7-2:2017
IEC 62321-6:2015
Test method with reference to BS EN 14582:2016
Test method with reference to IEC 62321-8:2017

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MDL:
MDL:
MDL:
MDL:
MDL:
MDL:

2 ppm
2 ppm
8 ppm
5 ppm
50 ppm50 ppmRev. 1.0

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Ultra-Small Real-Time Clock Module with I2C-Bus Interface

RV-8263-C8

9.3. RECYCLING MATERIAL INFORMATION
Recycling material information according to IPC-1752 standard.
Element weight is accumulated and referenced to the unit weight of 5.05 mg.
Item
No.
Item
Material
Substance
Material
Component
WeightElement
Name
Name
(mg)
(%)
Quartz Crystal
Chromium
Ceramic

1
2
3

Resonator
Electrodes
Housing

Gold

2
4
5
6
7
8
5
4
6

Electrodes
Metal Lid
Seal
Terminations
Resonator attach
CMOS IC
Seal
Metal Lid
Terminations

6
4

Terminations
Metal Lid

Tin
Nickel
Molybdenum
Kovar

Silicon8

CMOS IC

Unit weight (total)

June 2023

CAS
Number

0.099
0.0001
2.92

1.96
0.002
57.78

SiO2
Cr
Al2O3

Cr:

14808-60-7
7440-47-3
1344-28-1

0.19

3.73

Au

Au:

7440-57-5

0.03

0.59

Sn

Sn:

7440-31-5

0.17

3.36

Ni

Ni:

7440-02-0

0.38

7.60

Mo

1.00

19.81

Fe53Ni29Co18

0.26

5.16

Si

Mo:
Fe:
Ni:
Co:
Si:

7439-98-7
7439-89-6
7440-02-0
7440-48-4
7440-21-3

5.05

100

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Ultra-Small Real-Time Clock Module with I2C-Bus Interface

RV-8263-C8

9.4. ENVIRONMENTAL PROPERTIES & ABSOLUTE MAXIMUM RATINGS
PackageSON-8 ceramic package
Parameter
Product weight (total)
Storage temperature
Moisture sensitivity level (MSL)FIT / MTBF

Description
Small Outline Non-leaded (SON), hermetically sealed ceramic package with metal lid
Directive

Conditions
Store as bare product

IPC/JEDEC J-STD-020D

Value
5.05 mg-55 to +125°C
MSL1
available on request

Terminal finish:

NickelGold

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0.5 µmMolybdenum

5 µm

Ceramic

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Ultra-Small Real-Time Clock Module with I2C-Bus Interface

RV-8263-C8

10. SOLDERING INFORMATION
Maximum Reflow Conditions in accordance with IPC/JEDEC J-STD-020C “Pb-free”

tP

TP

Critical Zone
TL to TP

TemperatureRamp-up

TL

tL

Tsmax

Tsmin
Ramp-downtsPreheat25

t 25°C to Peak

Temperature Profile
Average ramp-up rate
Ramp down Rate
Time 25°C to Peak Temperature
PreheatTemperature min
Temperature max
Time Tsmin to Tsmax
Soldering above liquidus
Temperature liquidus
Time above liquidus
Peak temperature
Peak Temperature
Time within 5°C of peak temperature

June 2023

Time
Symbol(Tsmax to TP)
Tcool
Tto-peakCondition
3°C / second max
6°C / second max
8 minutes max

Unit°C / s°C / s
min

Tsmin
Tsmax
ts

150
200
60 – 180

°C
°C
sec

TL
tL

217
60 – 150

°C
sec

Tp
tp

260
20 – 40

°C
sec

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11. HANDLING PRECAUTIONS FOR MODULES WITH EMBEDDED CRYSTALSThe built-in tuning-fork crystal consists of pure Silicon Dioxide in crystalline form. The cavity inside the package isevacuated and hermetically sealed in order for the crystal blank to function undisturbed from air molecules, humidity
and other influences.
Shock and vibration:
Keep the crystal / module from being exposed to excessive mechanical shock and vibration. Micro Crystal
guarantees that the crystal / module will bear a mechanical shock of 5000 g / 0.3 ms.
The following special situations may generate either shock or vibration:
Multiple PCB panels - Usually at the end of the pick & place process the single PCBs are cut out with a router.
These machines sometimes generate vibrations on the PCB that have a fundamental or harmonic frequency close
to 32.768 kHz. This might cause breakage of crystal blanks due to resonance. Router speed should be adjusted
to avoid resonant vibration.
Ultrasonic cleaning - Avoid cleaning processes using ultrasonic energy. These processes can damage thecrystals due to the mechanical resonance frequencies of the crystal blank.
Overheating, rework high temperature exposure:
Avoid overheating the package. The package is sealed with a seal ring consisting of 80% Gold and 20% Tin. The
eutectic melting temperature of this alloy is at 280°C. Heating the seal ring up to >280°C will cause melting of themetal seal which then, due to the vacuum, is sucked into the cavity forming an air duct. This happens when using
hot-air-gun set at temperatures >280°C.
Use the following methods for rework:

Use a hot-air-gun set at 270°C.
Use 2 temperature controlled soldering irons, set at 270°C, with special-tips to contact all solder-joints fromboth sides of the package at the same time, remove part with tweezers when pad solder is liquid.

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12. PACKING & SHIPPING INFORMATION
Reel: 7” = 178 mm
Ø 13min. 8.4

max. 133,5 ±0,05

2 ±0,05

0,314 ±0,05
0,254 ±0,02

+0,3

8263

8263

8 -0,1

2,23 ±0,05

4 ±0,1

1,75 ±0,1

Carrier Tape:
Material: Polycarbonate, conductive
Width: 8 mm
Tape Leader and Trailer: Minimum length 300 mm

1,43 ±0,05

4 ±0,1(0,06)

0,83 ±0,05

Cover Tape

Direction of feed

All dimensions are in mm
RV-8263-C8_Tape-drw_20230623

Cover Tape:
Tape: Polypropylene, 3M™ Universal Cover Tape (UCT)
Adhesive Type: Pressure sensitive, Synthetic Polymer
Thickness: 0.06 mm
Peel Method:Medial section removal, both lateral stripes remain on carrier

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13. COMPLIANCE INFORMATION
Micro Crystal confirms that the standard product Real-Time Clock Module RV-8263-C8 is compliant with “EU RoHS
Directive” and “EU REACh Directives”.
Please find the actual Certificate of Conformance for Environmental Regulations on our website:
CoC_Environment_RV-Series.pdf

14. DOCUMENT REVISION HISTORY
Date

Revision #Revision Details

June 2023

1.0First release

The information contained in this document is believed to be accurate and reliable. However, Micro Crystal
assumes no responsibility for any consequences resulting from the use of such information nor for any
infringement of patents or other rights of third parties, which may result from its use. In accordance with ourpolicy of continuous development and improvement, Micro Crystal reserves the right to modify
specifications mentioned in this publication without prior notice and as deemed necessary.
Any use of Products for the manufacture of arms is prohibited. Customer shall impose that same obligation
upon all third-party purchasers.
Without the express written approval of Micro Crystal, Products are not authorized for use as components
in safety and life supporting systems as well as in any implantable medical devices. The unauthorized useof Products in such systems / applications / equipment is solely at the risk of the customer and suchcustomer agrees to defend and hold Micro Crystal harmless from and against any and all claims, suits,
damages, cost, and expenses resulting from any unauthorized use of Products.
No licenses to patents or other intellectual property rights of Micro Crystal are granted in connection withthe sale of Micro Crystal products, neither expressly nor implicitly. In respect of the intended use of Micro
Crystal products by customer, customer is solely responsible for observing existing patents and otherintellectual property rights of third parties and for obtaining, as the case may be, the necessary licenses.

Micro Crystal AG
Muehlestrasse 14
CH-2540 Grenchen
Switzerland
June 2023

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Phone +41 32 655 82 82
sales@microcrystal.com
www.microcrystal.com

Rev. 1.0