Freescale Semiconductor
Application NoteAN3865
Rev. 1.0, 2/2010

Managing Failure Detections and Using Required Components
to Meet ISO7637 pulse 1 on MC33903/4/5 Common Mode
Choke Implementation

1Overview

Contents
1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

This document describes the implementation of arecommended electrical component at the device’s CAN
terminal as well as the recommended software managementof the CAN interface for the MC33903/4/5 family in case offailure detection.

2ScopeThis document is divided into 3 sections:
1.
2.

3.

Application schematic in order to increase device
performance related to ISO pulse applied on CAN bus.
Recommended software practice in order to detect,manage and ensure proper recovery in case of ECU local
failures occurring on TxD or RxD terminals, and in case ofCAN over temperature.
Recommended software practice to properly detect andreport flags in the CAN register, to ensure reliable failure
report to main software.

© Freescale Semiconductor, Inc., 2010. All rights reserved.

2 Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3 CAN Interface Management2 . . . . . . . . . . . . . 2
3.1 CAN Terminal Schematic . . . . . . . . . . . . 2
3.2 TxD, RxD and Over-Temp Failure. . . . . . 3
3.3 Other CAN Faults . . . . . . . . . . . . . . . . . . . 6

CAN Interface Management

3CAN Interface Management

3.1

CAN Terminal Schematic

In order to improve the device performance regarding ISO7637 pulse 1 applied to the ECU CAN connector(CANH-ecu and CANH-ecu in figure below) when the device is implemented with a common mode choke, a
dedicated protection element (D1) should be connected between the common mode choke and the device CANHand CANL terminal as shown on the schematic below (See Figure 1).
This component (D1) should be connected per the recommendation below, and only if a common mode choke (L1)
is used. In cases where this common mode choke is not connected, protection element (D1) is not necessary. The
proposed protection element is a dual zener diode, specifically developed for CAN applications, and offering low
parasitic capacitance.

CANH
1

CANH_ecu

ECU connector

D1

CANL_ecu

3

IC1
Partial view

L1component list:
IC1: MC33903, MC33904, MC33905S, MC33905D
D1: NUP2105L package SOT23 (or PESD1CAN)
L1: Common Mode Choke per customer requirement, i.e TDK ACT45B-510(1): ESD protection element, bus filter capacitor, termination resistor

2

Additional optionalelements (1)

CANL
GND

ECU limit

Figure 1. CAN Terminal Schematic

3.2

TxD, RxD and Over-Temp Failure

The device detects and manages several types of failures that occur either on the CAN bus or locally on the ECU.
Some failures are reported as information only (flag), and some will in addition to being reported as flag disable theCAN driver in order to protect the device or prevent a general system failure. This is the case for the following:••Failures at TxD or RxD terminals
CAN driver over temperature

TxDominant failure means TxD internal ECU line is in permanent dominant state. Once this failure is detected, theCAN driver is disabled in order to avoid the CAN bus to be in permanent dominant state, preventing any further
communication on the network.
RxD failure means that RxD internal ECU line is shorted to gnd or 5V. Once this failure is detected, the CAN driveris also disabled, since the MCU could interpret RxD failure as bus idle state.
CAN driver over temperature will also disable the driver in order to prevent device from possible destruction.

3.2.1 Information Related to Flag Reporting and Consequences
3.2.1.1 Flag reporting
When a failure occurs (i.e TxD), the corresponding flag is set in the CAN register. The flag is latched, until the CAN
register is read (i.e SPI 0xE100). After read operation, the flag becomes a “real time” flag, and is then reset as soon
as the failure recovers.

Managing Failure Detections and Using Required Components to Meet ISO7637 pulse 1 on MC33903/4/5 Common
Mode Choke Implementation1, Rev. 1.02
Freescale SemiconductorCAN Interface Management

3.2.1.2 Failure Consequence
When the CAN is TxRx state (Transmit: Receive state) if TxD, RxD or CAN over temperature failures are detected,the bus driver is automatically disabled and the CAN is set to Rx only (Receive only) state. The CAN driver can bere-enable only via the SPI command with 3 conditions:
1.
2.
3.

Error has recovered
Flag is cleared by SPI command
CAN interface is set to TxRx state by SPI command

The paragraph below describes the recommended practice for the software that controls the device to detect such
events, report them to the MAIN software and how to reconfigure the device once failure has recover.
Two cases can be distinguished, depending upon usage or not of interruption (INT).
3.2.1.3 Case 1: INT not used
The main steps consists of the following:
1.

2.

Initialization routine
It should contain at least the two configuration commands listed below to ensure CAN interrupt is disabled and CAN
interface is set to Transmit/Receive state.
- INT configuration (disable)- CAN interface configuration (Transmit/Receive state)
MAIN software routine
It is assumed that the main software runs a periodic task that consists of the following:- Check CAN interface state- Check if any CAN flag is set- If flag is set or CAN interface is not in expected state, reset flags and set CAN in appropriate state.
- Then return to MAIN S/W and report CAN state information.

Managing Failure Detections and Using Required Components to Meet ISO7637 pulse 1 on MC33903/4/5 Common
Mode Choke Implementation1, Rev. 1.0
Freescale Semiconductor
3

CAN Interface Management

Partial Initialization routines:
Write INT register, disable all INT including CAN INT, SPI: 0x 6400
Read back INT register, SPI: 0x2500, expected miso bits 7...0= “0x 00”
Write CAN register, set CAN interface in Transmit/Receive mode, SPI: 0x 60C0 (note1)
Read back CAN register, SPI: 0x 2100, expected miso bits 7...0= “0x C0”“Get CAN status”routine
Periodic task: get CAN status:
Read back CAN register, SPI: 0x 2100
Extract bits[7,6] from MISO response

MAIN
S/W

Return to MAIN: CAN isin expected state.
yes

bits[7,6]= bin “1,1”

noCheck CAN failure flags:
Read CAN register flags, SPI: 0xE100 (note 2)
Extract bits[5,4,3,2] from MISO response

CAN interface re enable:
Write CAN register, set CAN interface inTransmit/Receive state, SPI: 0x 60C0
Read back CAN register, SPI: 0x 2100
Extract bits[7,6] from MISO response

Return to MAIN: CAN isin expected state.
yes

bits[7,6]= bin “1,1”yesReport error(s)to MAIN S/W

bit 5 or
4 or 3 or 2
set to “1”noNo error, orerror recovered

noReturn to MAIN: CAN is not in expected state.

Figure 2. Flow Chart without use of INT
Notes:
1.
2.

Bit 0 to 5 are set low in example. They could be set to different value, depending upon user choice (bus slew rate,CAN wake up option etc.).
If flag is set, the SPI 0xE100 command will result in one of the following:• If failure has recovered: clears flag
• If failure has not recovered: switch the flag operation from” latch” to “real time reporting” (flag will be reset as soon
as failure will recover, without the need for SPI command).

3.2.1.4 Case 2: INT is used
The main steps consists of the following:
1.

2.

Initialization routine
It should contain at least the two configurations listed below to ensure CAN interrupt is enabled, and CAN interface isset in Transmit/Receive mode.
- INT configuration (enable)- CAN interface configuration
MAIN software routine
It is assumed that when INT pulse occurs, the main software runs a task that consists of:- Check INT source- Check CAN interface state- Check if CAN flag is set
If flag is set or CAN interface is not in expected state, reset flags and set CAN in appropriate state.
- Then return to MAIN S/W and report CAN state information.
- The MAIN S/W must periodically attempt to re enable the CAN in Transmit/Receive mode.

Managing Failure Detections and Using Required Components to Meet ISO7637 pulse 1 on MC33903/4/5 Common
Mode Choke Implementation1, Rev. 1.04Freescale SemiconductorCAN Interface Management

Partial Initialization routines:
Write INT register, enable CAN INT, SPI: 0x 6480
Read back INT register, SPI: 0x2500, expected miso bits 7...0= “0x 80”

INT task

Write CAN register, set CAN interface in Transmit/Receive state, SPI: 0x 60C0 (note1)
Read back CAN register, SPI: 0x 2100, expected miso bits 7...0= “0x C0”

INT task:
Read back INT source, SPI: 0x6480 (note 3)
Extract bits [15,12,6] from MISO response

MAIN
S/W

noReturn to MAIN:
source is not CAN

INT

bits[7,6]= bin “1,1”yesPeriodic access if CAN is not in
expected state (note 4)“Get CAN status”routine describe in case 1
paragraph (INT not used) (note 4)

Figure 3. Flow Chart using INT
Notes:
1.
2.

3.

4.

Bit 0 to 5 are set low in example. They could be set to different value, depending upon user choice (bus slew rate,
CAN wake up option etc.).
If flag is set, the SPI 0xE100 command will result in one of the following:•If failure has recovered: clears flag
•If failure has not recovered: switch the flag operation from” latch” to “real time reporting” (flag will be reset assoon as failure recovers, without the need for SPI command).
Write command to get 16 bits standard and extended device status. Bit 15, 12 and 6 are INT status, CAN-generalflag and CAN local flag.
•Usage of any write command (i.e W/D refresh 0x5A00) is also possible.
The “Get CAN status” routine should be either:•One time execution if failure has recovered before INT task.
•Periodic execution if CAN is not in expected state.

Managing Failure Detections and Using Required Components to Meet ISO7637 pulse 1 on MC33903/4/5 Common
Mode Choke Implementation1, Rev. 1.0
Freescale Semiconductor
5

CAN Interface Management

3.3

Other CAN Faults

The device detects and manages several types of failures occurring either on the CAN bus or locally on the ECU.
Some failures are only reported as information (flag), and some will disable the CAN driver in order to protect thedevice or prevent a general system failure.
This section describes recommended practice to manage the CAN error flag that does not disable or modify the CAN
driver state. These flags are only for information and for system diagnostic purpose.
The flags are listed in the table below (extract from device data sheet, CAN register). 0xE100 and 0xE180 SPI
commands are used, and device provides 16 bits status on MISO. Table below describes bits 7-0:

SPI command MOSI16 bits0xE100

MISO response, bits 7-0bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0CAN-CAN
Over-temp

RxD lowRxd highTxD dom

Bus Domclamp

CAN
Over-current

CANL

CANL toVDDCANL toGND

CANH toVBATCANH toVDD

CANH to
GND

wake-up
0xE180CAN_UFCAN_F

to VBATFigure 4. CAN Register Flags
Bit 7 indicates that the error is not yet fully identified by the logic circuitry yet or that it is unstable.
Bit 6 indicates that the error is identified by the logic circuitry. The same error has been detected over a series of 5consecutive TxD transitions.
Bits 5 to 0 report the error detected by the device. These flags do not change the CAN status. CAN will remain in
TxRx state independently of the flag being set or not, and the communication is not affected.
However, some of theses flags could be set during exposure to EMC in the frequency range below 10MHz. It isrecommended to perform multiple sampling of these flags over a period of time before reporting them to the MAINsoftware.
As an example, the flag sampling can be performed as follows:
••
••
•
•

Upon execution of the ‘Get CAN status routine” described in above paragraph above.
Upon entering in Low Power mode
After device wake up.
At W/D refresh of the device
At a predetermined time period independent of above
Any combination of the above combinations.

If a flag is then consistently set over a number of samplings, it can then be reported to the MAIN software as aconsistent failure.

Managing Failure Detections and Using Required Components to Meet ISO7637 pulse 1 on MC33903/4/5 Common
Mode Choke Implementation1, Rev. 1.0
6
Freescale Semiconductor

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AN3865
Rev. 1.0
2/2010