REVISIONSLTR

DESCRIPTIONDATEAPPROVEDti
I!]

Prepared in accordance with ASME Y14.24.

Vendor item drawing

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REV STATUS
OF PAGESREVPAGEPMIC N/A

PREPARED BY

DLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
http://www.dla.mil/landandmaritime

Phu H. Nguyen
Original date of drawing
YY MM DD

19-05-17

TITLE

CHECKED BY
Phu H. Nguyen

MICROCIRCUIT, LINEAR-DIGITAL,PROCESSOR, MONOLITHIC SILICONAPPROVED BY
Thomas M. Hess
SIZE

A
REV

CODE IDENT. NO.

DWG NO.

V62/15602

16236
PAGE

1

AMSC N/A
DISTRIBUTION STATEMENT A. Approved for public release. Distribution is unlimited.

OF

1365962-V033-19

1. SCOPE
1.1 Scope. This drawing documents the general requirements of a high performance Processor microcircuit, with an operating
temperature range of -40°C to +105°C.
1.2 Vendor Item Drawing Administrative Control Number. The manufacturer’s PIN is the item of identification. The vendor item
drawing establishes an administrative control number for identifying the item on the engineering documentation:
V62/15602

-

01

I

Drawing
numberDevice type
(See 1.2.1)

X

F

I

I

Case outline(See 1.2.2)

Lead finish(See 1.2.3)

1.2.1 Device type(s).
Device type

Generic

Circuit function

01

AM3358 –EP

Processor

1.2.2 Case outline(s). The case outlines are as specified herein.
Outline letter

Number of pins

X

324

Package style
Plastic Ball Grid Array 1/

1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer:
Finish designator
A
B
C
D
E
F
Z

Material
Hot solder dip
Tin-lead plate
Gold plate
PalladiumGold flash palladium
Tin-lead alloy (BGA/CGA)
Other______________
1/

Devices listed on this drawing are supplied to lead finish “F”. The solder ball material contains compositions of Sn = 63%,
Pb = 34.5, Ag = 2% and Sb = 0.5 %.

DLA LAND AND MARITIMECOLUMBUS, OHIO

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1.3 Absolute maximum ratings.

1/ 2/Over junction temperature range (unless otherwise noted)
VDD_MPU

Supply voltage for the MPU core domain

Min
-0.5

Max
1.5

Unit
V

VDD_CORE

Supply voltage for the core domain

-0.5

1.5

V

CAP_VDD_RTC 3/

Supply voltage for the RTC core domain

-0.5

1.5

V

VPP

Supply voltage for the RTC domain

-0.5

2.2

V

VDDS_RTC

Supply voltage for the RTC domain

-0.5

2.1

V

VDDS_OSC

Supply voltage for the System oscillator

-0.5

2.1

V

VDDS_SRAM_CORE_BG

Supply voltage for the Core SRAM LDOs

-0.5

2.1

V

VDDS_SRAM_MPU_BB

Supply voltage for the MPU SRAM LDOs

-0.5

2.1

V

VDDS_PLL_DDR

Supply voltage for the DPLL DDR

-0.5

2.1

V

VDDS_PLL_CORE_LCD

Supply voltage for the DPLL Core and LCD

-0.5

2.1

V

VDDS_PLL_MPU

Supply voltage for the DPLL MPU

-0.5

2.1

V

VDDS_DDR

Supply voltage for the DDR IO domain

-0.5

2.1

V

VDDS

Supply voltage for all dual-voltage IO domains

-0.5

2.1

V

VDDA1P8V_USB0

Supply voltage for USBPHY

-0.5

2.1

V

VDDA1P8V_USB1

Supply voltage for USBPHY

-0.5

2.1

V

VDDA_ADCVDDSHV1

Supply voltage for ADC
Supply voltage for the dual-voltage IO domain

-0.5
-0.5

2.1
3.8

V
V

VDDSHV2

Supply voltage for the dual-voltage IO domain

-0.5

3.8

V

VDDSHV3

Supply voltage for the dual-voltage IO domain

-0.5

3.8

V

VDDSHV4

Supply voltage for the dual-voltage IO domain

-0.5

3.8

V

VDDSHV5

Supply voltage for the dual-voltage IO domain

-0.5

3.8

V

VDDSHV6

Supply voltage for the dual-voltage IO domain

-0.5

3.8

V

VDDA3P3V_USB0

Supply voltage for USBPHY

-0.5

4

V

VDDA3P3V_USB1

Supply voltage for USBPHY

-0.5

4

V

USB0_VBUS 5/

Supply voltage for USB VBUS comparator input

-0.5

5.25

V

USB1_VBUS 5/
DDR_VREF

Supply voltage for USB VBUS comparator input
Supply voltage for the DDR SSTL and HSTL
reference voltage

-0.5
-0.5

5.25
1.1

V
V

4/

Steady state max voltage at all IO
pins 6/
USB0_ID 7/
USB1_ID 7/
Transient overshoot and undershootspecification at IO terminal
Latch-up performance 8/-0.5 V to IO supply voltage +0.3 V

Steady state maximum voltage for the USB ID input

-0.5

2.1

V

Steady state maximum voltage for the USB ID input

-0.5

2.1

V

25% of corresponding IO supply
voltage for up to 30% of signal period
45
mA

Class II (105°C)

Junction temperature, TJ

-40

125

°C

Storage temperature, Tstg 9/

-55

155

°C

DLA LAND AND MARITIMECOLUMBUS, OHIO

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1.4 ESD ratings.
Electrostatic discharge (ESD) performance (VESD):
Human Body Model (HBM), per ANSI/ESDA/JEDEC JS001 ......................................... ±2000 V 10/
Charged Device Model (CDM), per JESD22-C101 ...................................................... ±500 V 11/
1.5 Power-On Hours (POH).
Reliability Data 12/ 13/ 14/ 15/

Operating Condition
Turbo
OPP120
OPP100OPP50

EXTENDED
Junction Temp (TJ)
Lifetime (POH) 16/–40°C to 105°C
80K–40°C to 105°C
100K–40°C to 105°C
100K–40°C to 105°C
100K__________________
1/

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stressratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
2/ All voltage values are with respect to their associated VSS or VSSA_x.
3/ This supply is sourced from an internal LDO when RTC_KALDO_ENn is low. If RTC_KALDO_ENn is high, this supply must be
sourced from an external power supply.
4/ During functional operation, this pin is a no connect.
5/ This terminal is connected to a fail-safe IO and does not have a dependence on any IO supply voltage.
6/ This parameter applies to all IO terminals which are not fail-safe and the requirement applies to all values of IO supply voltage.
For example, if the voltage applied to a specific IO supply is 0 volts the valid input voltage range for any IO powered by that
supply will be –0.5 to +0.3 V. Apply special attention anytime peripheral devices are not powered from the same power sources
used to power the respective IO supply. It is important the attached peripheral never sources a voltage outside the valid input
voltage range, including power supply ramp-up and ramp-down sequences.
7/ This terminal is connected to analog circuits in the respective USB PHY. The circuit sources a known current while measuring thevoltage to determine if the terminal is connected to VSSA_USB with a resistance less than 10 Ω or greater than 100 kΩ. The
terminal should be connected to ground for USB host operation or open-circuit for USB peripheral operation, and should never beconnected to any external voltage source.
8/ Based on JEDEC JESD78D [IC Latch-Up Test].
9/ For tape and reel the storage temperature range is [–10°C; +50°C] with a maximum relative humidity of 70%. TI recommends
returning to ambient room temperature before usage.
10/ JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
11/ JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
12/ The power-on hours (POH) information in this table is provided solely for your convenience and does not extend or modify thewarranty provided under TI's standard terms and conditions for TI semiconductor products.
13/ To avoid significant degradation, the device power-on hours (POH) must be limited as described in this table.
14/ Logic functions and parameter values are not assured out of the range specified in the recommended operating conditions.
15/ The above notations cannot be deemed a warranty or deemed to extend or modify the warranty under TI's standard terms andconditions for TI semiconductor products
16/ POH = Power-on hours when the device is fully functional.

DLA LAND AND MARITIMECOLUMBUS, OHIO

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1.6 Operating Performance Points (OPPs).
VDD_CORE OPPs for Case X Package -17/
VDD_CORE OPP
Device Rev. “Blank”

Min

VDD_CORE
NOM

Max

OPP100OPP50

1.056 V
0.912 V

1.100 V
0.950 V

1.144 V
0.998 V

DDR3 18
DDR3L
400 MHzDDR2 18/mDDR 18/

L3 and L4

266 MHz
125 MHz

200 MHz90 MHz

200 and 100 MHz
100 and 50 MHz

Valid Combinations of VDD_CORE and VDD_MPU OPPs for case X Package 17/ 18/
VDD_COREVDD_MPU

OPP50

OPP100

OPP100

OPP100

OPP100

OPP120

OPP100Turbo

VDD_MPU OPPs for Case X Package 17/
VDD_MPU OPP

VDD_MPU

ARM (A8)

Min

NOM

Max

Turbo

1.210 V

1.260 V1.326 V

800 MHzOPP1201,152 V

1.200 V1.248 V

720 MHzOPP1001.056 V

1.100 V

1.144 V

600 MHzOPP1000.912 V

0.950 V

0.988 V

300 MHz

Valid Combinations of VDD_CORE and VDD_MPU OPPs for case X Package
VDD_COREVDD_MPU

OPP50

OPP50

OPP50

OPP100

OPP100

OPP50

OPP100

OPP100

OPP100

OPP120

OPP100Turbo______________
17/
18/

Frequencies in this table indicate maximum performance for a given OPP condition.
This parameter represents the maximum memory clock frequency. Since data is transferred on both edges of the clock, double
data rate (DDR), the maximum data rate is two times the maximum memory clock frequency defined in this table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
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1.7 Recommended operating conditions.
Over junction temperature range (unless otherwise noted)
SUPPLY NAME

Min

NOM

Max

Unit

Supply voltage range for core domain; OPP100

1.056

1.100

1.144

V

Supply voltage range for core domain; OPP50

0.912

0.950

0.988

Supply voltage range for MPU domain; Turbo

1.210

1.260

1.326

Supply voltage range for MPU domain; OPP120

1.152

1.200

1.248

Supply voltage range for MPU domain; OPP100

1.056

1.100

1.144

Supply voltage range for MPU domain; OPP50

0.912

0.950

0.988

CAP_VDD_RTC 20/

Supply voltage range for RTC domain input

0.900

1.100

1.250

V

VDDS_RTC

Supply voltage range for RTC domain

1.710

1.800

1.890

V

Supply voltage range for DDR IO domain (DDR2)

1.710

1.800

1.890

Supply voltage range for DDR IO domain (DDR3)

1.425

1.500

1.575

Supply voltage range for DDR IO domain (DDR3L)

1.283

1.350

1.418

VDDS 21/

Supply voltage range for all dual-voltage IO domains

1.710

1.800

1.890

V

VDDS_SRAM_CORE_BG

Supply voltage range for Core SRAM LDOs, analog

1.710

1.800

1.890

V

VDDS_SRAM_MPU_BB

Supply voltage range for MPU SRAM LDOs, analog

1.710

1.800

1.890

V

VDDS_PLL_DDR 22/

Supply voltage range for DPLL DDR, analog

1.710

1.800

1.890

V

VDDS_PLL_CORE_LCD
22/

Supply voltage range for DPLL CORE and LCD, analog

1.710

1.800

1.890

V

VDDS_PLL_MPU 22/

Supply voltage range for DPLL MPU, analog

1.710

1.800

1.890

V

VDDS_OSC

Supply voltage range for system oscillator IO's, analog

1.710

1.800

1.890

V

VDDA1P8V_USB0 22/

Supply voltage range for USBPHY and PER DPLL
analog, 1.8 V

1.710

1.800

1.890

V

VDDA1P8V_USB1

Supply voltage range for USB PHY, analog, 1.8 V

1.710

1.800

1.890

V

VDDA3P3V_USB0

Supply voltage range for USB PHY, analog, 3.3 V

3.135

3.300

3.465

V

VDDA3P3V_USB1

Supply voltage range for USB PHY, analog, 3.3 V

3.135

3.300

3.465

V

VDDA_ADC

Supply voltage range for ADC, analog

VDD_CORE 19/

VDD_MPU 19/

VDDS_DDRDESCRIPTIONVDDSHV1VDDSHV2VDDSHV3

Supply voltage range for dual-voltage IO domain(1.8-V operation)

V

V

1.710

1.800

1.890

V

1.710

1.800

1.890

V

1.710

1.800

1.890

V

1.710

1.800

1.890

V

1.710

1.800

1.890

V

VDDSHV5

1.710

1.800

1.890

V

VDDSHV6

1.710

1.800

1.890

V

3.135

3.300

3.465

V

3.135

3.300

3.465

V

VDDSHV4VDDSHV1VDDSHV2

Supply voltage range for dual-voltage IO domain(3.3-V operation)

See foot notes at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

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ACODE IDENT NO.
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1.7 Recommended operating conditions- Continued.
Over junction temperature range (unless otherwise noted)
SUPPLY NAMEDESCRIPTIONVDDSHV3VDDSHV4VDDSHV5
VDDSHV6
DDR_VREF

Min

3.135
3.135
3.135
3.135
0.49 ×
VDDS_DDR
0.000
0.000

Supply voltage range for dual-voltage IO
domain (3.3 -V operation)
Voltage range for DDR SSTL and HSTL
reference input (DDR2, DDR3, DDR3L)

USB0_VBUS
USB1_VBUS
USB0_ID
USB1_ID
Operating temperature range, TJ

Voltage range for USB VBUS comparator input
Voltage range for the USB ID input
Extended temperature

NOM
3.300
3.300
3.300
3.300
0.49 ×
VDDS_DDR
5.000
5.000
23/
23/

-40

Max
3.465
3.465
3.465
3.465
0.49 ×
VDDS_DDR
5.250
5.250

105

Unit
V
V
V
V
V
V
V
V
V
°C

1.8 Thermal characteristics.
Thermal metric3/

Junction to case, RθJC
Junction to board, RθJB
Junction to free air, RΘJA

Junction-to-package top, φJT

Junction-to-board, φJB____________________

Case outline X(°C/W) 24/ 25/
10.2
12.1
24.2
20.1
19.3
18.8
0.3
0.6
0.7
0.8
12.7
12.3
12.3
12.2

AIR FLOW(m/s) 26/
N/A
N/A
0
1.0
2.0
3.0
0.0
1.0
2.0
3.0
0.0
1.0
2.0
3.0

19/ The supply voltage defined by OPP100 should be applied to this power domain before the device is released from reset.
20/ This supply is sourced from an internal LDO when RTC_KALDO_ENn is low. If RTC_KALDO_ENn is high, this supply must be
sourced from an external power supply.
21/ VDDS should be supplied irrespective of 1.8- or 3.3-V mode of operation of the dual-voltage IOs.
22/ For more details on power supply requirements, see Section 6.1.4 from manufacturer data.
23/ This terminal is connected to analog circuits in the respective USB PHY. The circuit sources a known current while measuring thevoltage to determine if the terminal is connected to VSSA_USB with a resistance less than 10 Ω or greater than 100 kΩ. The
terminal should be connected to ground for USB host operation or open-circuit for USB peripheral operation, and should never beconnected to any external voltage source.
24/ These values are based on a JEDEC-defined 2S2P system (with the exception of the theta JC [RΘJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:JESD51-2, JESD51-3, JESD51-7, JESD51-9,
25/ °C/W = degrees Celsius per watt.
26/ m/s = meters per second.

DLA LAND AND MARITIMECOLUMBUS, OHIO

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1.9 Power Consumption Summary.
Maximum Current Ratings at Power Terminals 27/
SUPPLY NAMEVDD_COREVDD_MPU

DESCRIPTION

Max

Unit

400

Maximum current rating for the core domain; OPP100

250

Maximum current rating for the core domain; OPP50
Maximum current rating for the MPU domain; Turbo

at 800 MHz

800

Maximum current rating for the MPU domain; OPP120

at 720 MHz

720

Maximum current rating for the MPU domain; OPP100

at 600 MHz

600

Maximum current rating for the MPU domain; OPP50

at 400 MHz

300

CAP_VDD_RTC 28/

Maximum current rating for RTC domain input and LDO output

2

VDDS_RTC

Maximum current rating for the RTC domain

5

VDDS_DDR

Maximum current rating for DDR IO domain

250

VDDS

Maximum current rating for all dual-voltage IO domains

50

VDDS_SRAM_CORE_BG

Maximum current rating for core SRAM LDOs

10

VDDS_SRAM_MPU_BB

Maximum current rating for MPU SRAM LDOs

10

VDDS_PLL_DDR

Maximum current rating for the DPLL DDR

10

VDDS_PLL_CORE_LCD

Maximum current rating for the DPLL Core and LCD

20

VDDS_PLL_MPU

Maximum current rating for the DPLL MPU

10

VDDS_OSC

Maximum current rating for the system oscillator IOs

5

VDDA1P8V_USB0

Maximum current rating for USBPHY 1.8 V

25

VDDA1P8V_USB1

Maximum current rating for USBPHY 1.8 V

25

VDDA3P3V_USB0

Maximum current rating for USBPHY 3.3 V

40

VDDA3P3V_USB1

Maximum current rating for USBPHY 3.3 V

40

VDDA_ADC

Maximum current rating for ADC

10

VDDSHV1

Maximum current rating for dual-voltage IO domain

50

VDDSHV2

Maximum current rating for dual-voltage IO domain

50

VDDSHV3

Maximum current rating for dual-voltage IO domain

50

VDDSHV4

Maximum current rating for dual-voltage IO domain

50

VDDSHV5

Maximum current rating for dual-voltage IO domain

50

VDDSHV6

Maximum current rating for dual-voltage IO domain

100

mA

____________________
27/ Current ratings specified in this table are worst-case estimates. Actual application power supply estimates could be lower. For more information,
see the manufacturer AM335x Power Consumption Summary application report (SPRABN5) on manufacturer data.

28/ This supply is sourced from an internal LDO when RTC_KALDO_ENn is low. If RTC_KALDO_ENn is high, this supply must be sourced from anexternal power supply.

DLA LAND AND MARITIMECOLUMBUS, OHIO

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1.9 Power Consumption Summary- Continued.
Low-Power Modes Power Consumption Summary
POWER
MODES

StandbyDeepsleep1

Deepsleep0

APPLICATION STATE

DDR memory is in self-refreshand contents are preserved.
Wake up from any GPIO. CortexA8 context/register contents arelost and must be saved before
entering standby. On exit,
context must be restored from
DDR. For wake-up, boot ROM
executes and branches tosystem resume.

On-chip peripheral registers arepreserved. Cortex-A8
context/registers are lost, so theapplication needs to save themto the L3 OCMC RAM or DDR
before entering DeepSleep. DDR
is in self- refresh. For wake-up,boot ROM executes andbranches to syste

PD_PER peripheral and CortexA8/MPU register information will
be lost. On- chip peripheral
register (context) information of
PD-PER domain needs to be
saved by application to SDRAM
before entering this mode. DDR
is in self- refresh. For wake-up,boot ROM executes andbranches to peripheral context
restore followed by system
resume.

DLA LAND AND MARITIMECOLUMBUS, OHIOPOWER DOMAINS, CLOCKS, AND
VOLTAGE SUPPLY STATESPower supplies:• All power supplies are ON.
• VDD_MPU = 0.95 V (nom)• VDD_CORE = 0.95 V (nom)Clocks:• Main Oscillator (OSC0) = ON
• All DPLLs are in bypass.
Power domains:• PD_PER = ON
• PD_MPU = OFF• PD_GFX = OFF• PD_WKUP = ON
DDR is in self-refresh.
Power supplies:• All power supplies are ON.
• VDD_MPU = 0.95 V (nom)• VDD_CORE = 0.95 V (nom)Clocks:• Main Oscillator (OSC0) = OFF• All DPLLs are in bypass.
Power domains:• PD_PER = ON
• PD_MPU = OFF• PD_GFX = OFF• PD_WKUP = ON
DDR is in self-refresh.
Power supplies:• All power supplies are ON.
• VDD_MPU = 0.95 V (nom)• VDD_CORE = 0.95 V (nom)Clocks:• Main Oscillator (OSC0) = OFF• All DPLLs are in bypass.
Power domains:• PD_PER = OFF• PD_MPU = OFF• PD_GFX = OFF• PD_WKUP = ON
DDR is in self-refresh.

SIZE
A

NOM

Max

Unit
mW

16.5

22.0

6.0

10.0

3.0

4.3

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2. APPLICABLE DOCUMENTSJEDEC – SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC)
JEP95
JEP155
JEP157JESD 51-2
JESD 51-3
JESD51-7
JESD51-9
JESD79-2F
JESD79-3F
JESD209B

–
–
–
–
–
–
–
–
–
–

Registered and Standard Outlines for Semiconductor Devices
Recommended ESD Target Levels For HBM/MM Qualification
Recommended ESD-CDM Target Levels
Integrated Circuits Thermal Test Method Environment Conditions – Natural Convection (Still Air)
Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages.
High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
Test Boards for Area Array Surface Mount Package Thermal Measurements.
DDR2 SDRAM specification.
DDR2 SDRAM specification.
Low Power Double Data Rate (LPDDR).

Applications for copies should be addressed to the Electronic Industries Alliance, 3103 North 10th Street, Suite 240–S, Arlington, VA
22201-2107 or online at https://www.jedec.org.
3. REQUIREMENTS
3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as
follows:
A.
B.
C.

Manufacturer’s name, CAGE code, or logo
Pin 1 identifier
ESDS identification (optional)

3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable)
above.
3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as
specified in 1.3, 1.4, and table I herein.
3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein.
3.5 Diagrams.
3.5.1

Case outline. The case outline shall be as shown in 1.2.2 and figure 1.

3.5.2

Functional block diagram. The functional block diagram shall be as shown in figure 2.

3.5.3 Pin Map Location (Section Left). Pin Map Location (Section Left) shall be as shown in figure 3.
3.5.4 Pin Map Location (Section Middle). Pin Map Location (Section Middle) shall be as shown in figure 4.
3.5.5 Pin Map Location (Section Right). Pin Map Location (Section Right) shall be as shown in figure 5.
3.5.6 Power Supply and Slew Rate. The Power Supply and Slew Rate shall be as shown in figure 6.
3.5.7 Preferred Power Supply Sequencing with Dual Voltage IOs Configured as 3.3 V. The Preferred Power Supply Sequencing with
Dual Voltage IOs Configured as 3.3 V shall be as shown in figure 7.
3.5.8 Alternate Power Supply Sequencing with Dual Voltage IOs Configured as 3.3 V. The Alternate Power Supply Sequencing with
Dual Voltage IOs Configured as 3.3 V shall be as shown in figure 8.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

V62/15602

REV

PAGE

10

3.5.9Power Supply Sequencing with Dual Voltage IOs Configured as 1.8 V. The Power Supply Sequencing with Dual Voltage IOs
Configured as 1,8 V shall be as shown in figure 9.

3.5.10Power-Supply Sequencing With Internal RTC LDO Disabled. The Power-Supply Sequencing With Internal RTC LDO
Disabled shall be as shown in figure 10.

3.5.11

Power-Supply Sequencing with RTC Feature Disabled. The Power-Supply Sequencing with RTC Feature Disabled shall be
as shown in figure 11.

3.5.12

VDD_MPU_MON Connectivity. The VDD_MPU_MON Connectivity shall be as shown in figure 12.

3.5.13

DPLL Power Supply Connectivity. The DPLL Power Supply Connectivity shall be as shown in figure 13.

3.5.14

OSC0 Start-Up Time. The OSC0 Start-Up Time shall be as shown in figure 14.

3.5.15OSC1 Start-Up Time. The OSC1 Start-Up Time shall be as shown in figure 15.

3.5.16OSC1 LVCMOS Circuit Schematic. The OSC1 LVCMOS Circuit Schematic shall be as shown in figure 16.

3.5.17DCANx Timings. The DCANx Timings shall be as shown in figure 17.

3.5.18Timer Timing. The Timer Timing shall be as shown in figure 18.

3.5.19

MDIO_DATA Timing - Input Mode. The MDIO_DATA Timing - Input Mode shall be as shown in figure 19.

3.5.20

MDIO_CLK Timing. The MDIO_CLK Timing shall be as shown in figure 20.

3.5.21

MDIO_DATA Timing - Output Mode. The MDIO_DATA Timing - Output Mode shall be as shown in figure 21.

3.5.22

GMII[x]_RXCLK Timing - MII Mode. The GMII[x]_RXCLK Timing - MII Mode shall be as shown in figure 22.

3.5.23

GMII[x]_TXCLK Timing - MII Mode. The GMII[x]_TXCLK Timing - MII Mode shall be as shown in figure 23.

3.5.24

GMII[x]_RXD[3:0], GMII[x]_RXDV, GMII[x]_RXER Timing - MII Mode. The GMII[x]_RXD[3:0], GMII[x]_RXDV, GMII[x]_RXER
Timing - MII Mode shall be as shown in figure 24.

3.5.25

GMII[x]_TXD[3:0], GMII[x]_TXEN Timing - MII Mode. The GMII[x]_TXD[3:0], GMII[x]_TXEN Timing - MII Mode shall be as
shown in figure 25.

3.5.26

RMII[x]_REFCLK Timing - RMII Mode. The RMII[x]_REFCLK Timing - RMII Mode shall be as shown in figure 26.

3.5.27

RMII[x]_RXD[1:0], RMII[x]_CRS_DV, RMII[x]_RXER Timing - RMII Mode. The RMII[x]_RXD[1:0], RMII[x]_CRS_DV,
RMII[x]_RXER Timing - RMII Mode shall be as shown in figure 27.

3.5.28RMII[x]_TXD[1:0], RMII[x]_TXEN Timing - RMII Mode. The RMII[x]_TXD[1:0], RMII[x]_TXEN Timing - RMII Mode shall be as
shown in figure 28.

3.5.29RGMII[x]_RCLK Timing - RGMII Mode. The RGMII[x]_RCLK Timing - RGMII Mode shall be as shown in figure 29.

3.5.30RGMII[x]_RD[3:0], RGMII[x]_RCTL Timing - RGMII Mode. The RGMII[x]_RD[3:0], RGMII[x]_RCTL Timing - RGMII Modeshall be as shown in figure 30.

3.5.31

RGMII[x]_TCLK Timing - RGMII Mode. The RGMII[x]_TCLK Timing - RGMII Mode shall be as shown in figure 31.

3.5.32

RGMII[x]_TD[3:0], RGMII[x]_TCTL Timing - RGMII Mode. The RGMII[x]_TD[3:0], RGMII[x]_TCTL Timing - RGMII Modeshall be as shown in figure 32.

3.5.33

GPMC and NOR Flash—Synchronous Single Read—(GpmcFCLKDivider = 0). The GPMC and NOR Flash—SynchronousSingle Read—(GpmcFCLKDivider = 0) shall be as shown in figure 33.

DLA LAND AND MARITIMECOLUMBUS, OHIO

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ACODE IDENT NO.
16236

DWG NO.

V62/15602

REV

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11

3.5.34

GPMC and NOR Flash—Synchronous Burst Read—4x16-bit (GpmcFCLKDivider = 0). The GPMC and NOR Flash—
Synchronous Burst Read—4x16-bit (GpmcFCLKDivider = 0) shall be as shown in figure 34.

3.5.35

GPMC and NOR Flash—Synchronous Burst Write—(GpmcFCLKDivider > 0). The GPMC and NOR Flash—Synchronous
Burst Write—(GpmcFCLKDivider > 0) shall be as shown in figure 35.

3.5.36

GPMC and Multiplexed NOR Flash—Synchronous Burst Read. The GPMC and Multiplexed NOR Flash—Synchronous Burst
Read shall be as shown in figure 36.

3.5.37

GPMC and Multiplexed NOR Flash—Synchronous Burst Write. The GPMC and Multiplexed NOR Flash—Synchronous Burst
Write shall be as shown in figure 37.

3.5.38

GPMC and NOR Flash—Asynchronous Read—Single Word. The GPMC and NOR Flash—Asynchronous Read—Single
Word shall be as shown in figure 38.

3.5.39GPMC and NOR Flash—Asynchronous Read—32-bit. The GPMC and NOR Flash—Asynchronous Read—32-bit shall be
as shown in figure 39.

3.5.40

GPMC and NOR Flash—Asynchronous Read—Page Mode 4x16-bit. The GPMC and NOR Flash—Asynchronous Read—
Page Mode 4x16-bit shall be as shown in figure 40.

3.5.41

GPMC and NOR Flash—Asynchronous Write—Single Word. The GPMC and NOR Flash—Asynchronous Write—Single
Word shall be as shown in figure 41.

3.5.42

GPMC and Multiplexed NOR Flash—Asynchronous Read—Single Word. The GPMC and Multiplexed NOR Flash—
Asynchronous Read—Single Word shall be as shown in figure 42.

3.5.43

GPMC and Multiplexed NOR Flash—Asynchronous Write—Single Word. The GPMC and Multiplexed NOR Flash—
Asynchronous Write—Single Word shall be as shown in figure 43.

3.5.44

GPMC and NAND Flash—Command Latch Cycle. The GPMC and NAND Flash—Command Latch Cycle shall be as shownin figure 44.

3.5.45

GPMC and NAND Flash—Address Latch Cycle. The GPMC and NAND Flash—Address Latch Cycle shall be as shown infigure 45.

3.5.46

GPMC and NAND Flash—Data Read Cycle. The GPMC and NAND Flash—Data Read Cycle shall be as shown in figure 46.

3.5.47

GPMC and NAND Flash— Data Write Cycle. The GPMC and NAND Flash— Data Write Cycle shall be as shown in figure
47.

3.5.48LPDDR Memory Interface Clock Timing. The LPDDR Memory Interface Clock Timing shall be as shown in figure 48.

3.5.49AM3358-EP Device and LPDDR Device Placement. The AM3358-EP Device and LPDDR Device Placement shall be as
shown in figure 49.

3.5.50

CK and ADDR_CTRL Routing and Topology. The CK and ADDR_CTRL Routing and Topology shall be as shown in figure50.

3.5.51

DQS[x] and DQ[x] Routing and Topology. The DQS[x] and DQ[x] Routing and Topology shall be as shown in figure 51.

3.5.52

DDR2 Memory Interface Clock Timing. The DDR2 Memory Interface Clock Timing shall be as shown in figure 52.

DLA LAND AND MARITIMECOLUMBUS, OHIO

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ACODE IDENT NO.
16236

DWG NO.

V62/15602

REV

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3.5.53

AM3358-EP Device and DDR2 Device Placement. The AM3358-EP Device and DDR2 Device Placement shall be as shownin figure 53.

3.5.54

CK and ADDR_CTRL Routing and Topology. The CK and ADDR_CTRL Routing and Topology shall be as shown in figure
54.

3.5.55

DQS[x] and DQ[x] Routing and Topology. The DQS[x] and DQ[x] Routing and Topology shall be as shown in figure 55.

3.5.56

DDR3 Memory Interface Clock Timing. The DDR3 Memory Interface Clock Timing shall be as shown in figure 56.

3.5.57

Placement Specifications. The Placement Specifications shall be as shown in figure 57.

3.5.58

CLM for Two Address Loads on One Side of PCB. The CLM for Two Address Loads on One Side of PCB shall be as shownin figure 58.

3.5.59DQLM for Any Number of Allowed DDR3 Devices. The DQLM for Any Number of Allowed DDR3 Devices shall be as shownin figure 59.

3.5.60I2C Receive Timing. The I2C Receive Timing shall be as shown in figure 60.

3.5.61I2C Transmit Timing. The I2C Transmit Timing shall be as shown in figure 61.

3.5.62JTAG Timing. The JTAG Timing shall be as shown in figure 62.

3.5.63

Command Write in Hitachi Mode. The Command Write in Hitachi Mode shall be as shown in figure 63.

3.5.64

Data Write in Hitachi Mode. The Data Write in Hitachi Mode shall be as shown in figure 64.

3.5.65

Command Read in Hitachi Mode. The Command Read in Hitachi Mode shall be as shown in figure 65.

3.5.66

Data Read in Hitachi Mode. The Data Read in Hitachi Mode shall be as shown in figure 66.

3.5.67Micro-Interface Graphic Display Motorola Write. The Micro-Interface Graphic Display Motorola Write shall be as shown infigure 67.

3.5.68Micro-Interface Graphic Display Motorola Read. The Micro-Interface Graphic Display Motorola Read shall be as shown infigure 68.

3.5.69Micro-Interface Graphic Display Motorola Status. The Micro-Interface Graphic Display Motorola Status shall be as shown infigure 69.

3.5.70Micro-Interface Graphic Display Intel Write. The Micro-Interface Graphic Display Intel Write shall be as shown in figure 70.

3.5.71

Micro-Interface Graphic Display Intel Read. The Micro-Interface Graphic Display Intel Read shall be as shown in figure 71.

3.5.72

Micro-Interface Graphic Display Intel Status. The Micro-Interface Graphic Display Intel Status shall be as shown in figure 72.

3.5.73

LCD Raster-Mode Active. The LCD Raster-Mode Active shall be as shown in figure 73.

3.5.74

LCD Raster-Mode Passive. The LCD Raster-Mode Passive shall be as shown in figure 74.

3.5.75LCD Raster-Mode Control Signal Activation. The LCD Raster-Mode Control Signal Activation shall be as shown in figure 75.

3.5.76

LCD Raster-Mode Control Signal Deactivation. The LCD Raster-Mode Control Signal Deactivation shall be as shown infigure 76.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

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REV

PAGE

13

3.5.77

McASP Input Timing. The McASP Input Timing shall be as shown in figure 77.

3.5.78McASP Input Timing. The McASP Input Timing shall be as shown in figure 78.

3.5.79McASP Output Timing. The McASP Output Timing shall be as shown in figure 79.

3.5.80SPI Slave Mode Receive Timing. The SPI Slave Mode Receive Timing shall be as shown in figure 80.

3.5.81SPI Slave Mode Transmit Timing. The SPI Slave Mode Transmit Timing shall be as shown in figure 81.

3.5.82

SPI Master Mode Receive Timing. The SPI Master Mode Receive Timing shall be as shown in figure 82.

3.5.83

SPI Master Mode Transmit Timing. The SPI Master Mode Transmit Timing shall be as shown in figure 83.

3.5.84MMC[x]_CMD and MMC[x]_DAT[7:0] Input Timing. The MMC[x]_CMD and MMC[x]_DAT[7:0] Input Timing shall be as
shown in figure 84.

3.5.85

MMC[x]_CMD and MMC[x]_DAT[7:0] Output Timing—Standard Mode. The MMC[x]_CMD and MMC[x]_DAT[7:0] Output
Timing—Standard Mode shall be as shown in figure 85.

3.5.86

MMC[x]_CMD and MMC[x]_DAT[7:0] Output Timing—High Speed Mode. The MMC[x]_CMD and MMC[x]_DAT[7:0] Output
Timing—High Speed Mode shall be as shown in figure 86.

3.5.87

PRU-ICSS PRU Direct Input Timing. The PRU-ICSS PRU Direct Input Timing shall be as shown in figure 87.

3.5.88PRU-ICSS PRU Direct Output Timing. The PRU-ICSS PRU Direct Output Timing shall be as shown in figure 88.

3.5.89PRU-ICSS PRU Parallel Capture Timing - Rising Edge Mode. The PRU-ICSS PRU Parallel Capture Timing - Rising Edge
Mode shall be as shown in figure 89.

3.5.90PRU-ICSS PRU Parallel Capture Timing - Falling Edge Mode. The PRU-ICSS PRU Parallel Capture Timing - Falling Edge
Mode shall be as shown in figure 90.

3.5.91

PRU-ICSS PRU Shift In Timing. The PRU-ICSS PRU Shift In Timing shall be as shown in figure 91.

3.5.92PRU-ICSS PRU Shift Out Timing. The PRU-ICSS PRU Shift Out Timing shall be as shown in figure 92.

3.5.93

PRU-ICSS MDIO_DATA Timing - Input Mode. The PRU-ICSS MDIO_DATA Timing - Input Mode shall be as shown in figure93.

3.5.94PRU-ICSS MDIO_CLK Timing. The PRU-ICSS MDIO_CLK Timing shall be as shown in figure 94.

3.5.95PRU-ICSS MDIO_DATA Timing – Output Mode. The PRU-ICSS MDIO_DATA Timing – Output Mode shall be as shown infigure 95.

3.5.96

PRU-ICSS MII_RXCLK Timing. The PRU-ICSS MII_RXCLK Timing shall be as shown in figure 96.

3.5.97

PRU-ICSS MII_TXCLK Timing. The PRU-ICSS MII_TXCLK Timing shall be as shown in figure 97.

3.5.98PRU-ICSS MII_RXD[3:0], MII_RXDV, and MII_RXER Timing. The PRU-ICSS MII_RXD[3:0], MII_RXDV, and MII_RXER
Timing shall be as shown in figure 98.

3.5.99PRU-ICSS MII_TXD[3:0], MII_TXEN Timing. The PRU-ICSS MII_TXD[3:0], MII_TXEN Timing shall be as shown in figure99.

3.5.100

PRU-ICSS UART Timing. The PRU-ICSS UART Timing shall be as shown in figure 100.

3.5.101

UART Timing. The UART Timing shall be as shown in figure 101.

3.5.102

UART IrDA Pulse Parameters. The UART IrDA Pulse Parameters shall be as shown in figure 102.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

V62/15602

REV

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14

TABLE I. Electrical performance characteristics. 1/ 2/ 3/
Test

SymbolLimits
Min

Typ

Unit
Max

DC Electrical Characteristics 3/

DDR_RESETn,DDR_CSn0,DDR_CKE,DDR_CK,DDR_CKn,DDR_CASn,DDR_RASn,DDR_WEn,DDR_BA0,DDR_BA1,DDR_BA2,
DDR_A0,DDR_A1,DDR_A2,DDR_A3,DDR_A4,DDR_A5,DDR_A6,DDR_A7,DDR_A8,DDR_A9,DDR_A10,DDR_A11,DDR_A12,
DDR_A13,DDR_A14,DDR_A15,DDR_ODT,DDR_D0,DDR_D1,DDR_D2,DDR_D3,DDR_D4,DDR_D5,DDR_D6,DDR_D7,DDR_D8,
DDR_D9,DDR_D10, DDR_D11,DDR_D12,DDR_D13,DDR_D14,DDR_D15,DDR_DQM 0,DDR_DQM1,DDR_DQS0,
DDR_DQSn0,DDR_DQS1,DDR_DQSn1 Pins
High-level input voltage
VIH
0.65 × VDDS_DDR
Low-level input voltage
VIL
0.35 ×
VDDS_DDR
Hysteresis voltage at an input
VHYS
0.07
0.25
High level output voltage, driver enabled, pullup or
IOH = 8 mA
VOH
VDDS_DDR – 0.4
pulldown disabled
Low level output voltage, driver enabled, pullup
IOL = 8 mA
VOL
0.4
orpulldown disabled
Input leakage current, Receiver disabled, pullup or pulldown
10
inhibited
II
Input leakage current, Receiver disabled, pullup enabled-240-80
Input leakage current, Receiver disabled, pulldown enabled80
240
Total leakage current through the terminal connection of a driverreceiver combination that may include a pullup or pulldown. The
IOZ
10driver output is disabled and the pullup or pulldown is inhibited.
DDR_RESETn,DDR_CSn0,DDR_CKE,DDR_CK,DDR_CKn,DDR_CASn,DDR_RASn,DDR_WEn,DDR_BA0,DDR_BA1,DDR_BA2,
DDR_A0,DDR_A1,DDR_A2,DDR_A3,DDR_A4,DDR_A5,DDR_A6,DDR_A7,DDR_A8,DDR_A9,DDR_A10,DDR_A11,DDR_A12,
DDR_A13,DDR_A14,DDR_A15, DDR_ODT,DDR_D0,DDR_D1,DDR_D2,DDR_D3,DDR_D4,DDR_D5,DDR_D6,DDR_D7,DDR_D8,
DDR_D9,DDR_D10,DDR_D11,DDR_D12,DDR_D13,DDR_D14, DDR_D15,DDR_DQM0,DDR_DQM1,DDR_DQS0, DDR_DQSn0,
DDR_DQS1,DDR_DQSn1 Pins (DDR2 - SSTL Mode)
High-level input voltage

VIH

Low-level input voltage

VIL

Hysteresis voltage at an input
High level output voltage, driver enabled, pullup or
IOH = 8 mA
pulldown disabled
Low level output voltage, driver enabled, pullup
IOL = 8 mA
orpulldown disabled
Input leakage current, Receiver disabled, pullup or pulldown
inhibited
Input leakage current, Receiver disabled, pullup enabled
Input leakage current, Receiver disabled, pulldown enabled
Total leakage current through the terminal connection of a driverreceiver combination that may include a pullup or pulldown. The
driver output is disabled and the pullup or pulldown is inhibited.

VHYS
VOH

V
V
V
μA

μA

V

DDR_VREF +
0.125

V

DDR_VREF –
0.125

N/A

V
V

VDDS_DDR –

0.4

0.4

VOL
II

V
V

V

10
-240
80

IOZ

μA

-80
240
10

μA

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

V62/15602

REV

PAGE

15

TABLE I. Electrical performance characteristics - Continued. 1/ 2/ 3/
Test

SymbolLimits
Min

Typ

Unit
Max

DC Electrical Characteristics (Continued) 3/

DDR_RESETn,DDR_CSn0,DDR_CKE,DDR_CK,DDR_CKn,DDR_CASn,DDR_RASn,DDR_WEn,DDR_BA0,DDR_BA1,DDR_BA2,
DDR_A0,DDR_A1,DDR_A2,DDR_A3,DDR_A4,DDR_A5,DDR_A6,DDR_A7,DDR_A8,DDR_A9,DDR_A10,DDR_A11,DDR_A12,
DDR_A13,DDR_A14,DDR_A15,DDR_ODT,DDR_D0,DDR_D1,DDR_D2,DDR_D3,DDR_D4,DDR_D5,DDR_D6,DDR_D7,
DDR_D8,DDR_D9,DDR_D10,DDR_D11,DDR_D12,DDR_D13,DDR_D14,DDR_D15,DDR_DQM0,DDR_DQM1,DDR_DQS0,
DDR_DQSn0,DDR_DQS1,DDR_DQSn1 Pins (DDR3, DDR3L - HSTL Mode)
DDR_VREF +VDDS_DDR = 1.5 V
VIH
0.1
High-level input voltage
DDR_VREF +VDDS_DDR = 1.35 V
0.09
DDR_VREF –VDDS_DDR = 1.5 V
VIL
0.1
Low-level input voltage
DDR_VREF –VDDS_DDR = 1.35 V
0.09
Hysteresis voltage at an input
VHYS
N/AHigh level output voltage, driver enabled, pullup or
IOH = 8 mA
VOH
VDDS_DDR –pulldown disabled
0.4
Low level output voltage, driver enabled, pullup
IOL = 8 mA
0.4
VOL
orpulldown disabled
Input leakage current, Receiver disabled, pullup or pulldown inhibited
10
II
Input leakage current, Receiver disabled, pullup enabled-240-80
Input leakage current, Receiver disabled, pulldown enabled80
240
Total leakage current through the terminal connection of a driverreceiver combination that may include a pullup or pulldown. The driver
IOZ
10
output is disabled and the pullup or pulldown is inhibited.
ECAP0_IN_PWM0_OUT,UART0_CTSn,UART0_RTSn,UART0_RXD,UART0_TXD,UART1_CTSn,UART1_RTSn,UART1_RXD,
UART1_TXD,I2C0_SDA,I2C0_SCL,XDMA_EVENT_INTR0,XDMA_EVENT_INTR1,WARMRSTn,EXTINTn,TMS,TDO,
USB0_DRVVBUS,USB1_DRVVBUS (VDDSHV6 = 1.8 V)
0.65 ×
High-level input voltage
VIH
VDDSHV6
0.35 ×Low-level input voltage
VIL
VDDSHV6
Hysteresis voltage at an input
VHYS
0.18
0.305
High level output voltage, driver enabled, pullup or
IOH = 4 mA
VOH
VDDSHV6 –pulldown disabled
0.45
Low level output voltage, driver enabled, pullup
IOL = 4 mA
VOL
0.45
orpulldown disabled
Input leakage current, Receiver disabled, pullup or pulldown inhibited
8
II
Input leakage current, Receiver disabled, pullup enabled
-161
-100
-52
Input leakage current, Receiver disabled, pulldown enabled
52
100
170
Total leakage current through the terminal connection of a driverreceiver combination that may include a pullup or pulldown. The driver
IOZ
8output is disabled and the pullup or pulldown is inhibited.

V

V

V
V
V
μA

μA

V
V
V
V
V
μA

μA

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

V62/15602

REV

PAGE

16

TABLE I. Electrical performance characteristics - Continued. 1/ 2/ 3/
Test

SymbolLimits
Min

Typ

Unit
Max

DC Electrical Characteristics (Continued) 3/

ECAP0_IN_PWM0_OUT,UART0_CTSn,UART0_RTSn,UART0_RXD,UART0_TXD,UART1_CTSn,UART1_RTSn,UART1_RXD,
UART1_TXD,I2C0_SDA,I2C0_SCL,XDMA_EVENT_INTR0,XDMA_EVENT_INTR1,WARMRSTn,EXTINTn,TMS,TDO,
USB0_DRVVBUS,USB1_DRVVBUS (VDDSHV6 = 3.3 V)
2High-level input voltage
VIH
0.8
Low-level input voltage
VIL
Hysteresis voltage at an input
VHYS
0.265
0.44
High level output voltage, driver enabled, pullup or
IOH = 8 mA
VOH
VDDSHV6 –pulldown disabled
0.45
Low level output voltage, driver enabled, pullup
IOL = 8 mA
VOL
0.45
orpulldown disabled
Input leakage current, Receiver disabled, pullup or pulldown inhibited
18
II
Input leakage current, Receiver disabled, pullup enabled
-243
-100
-19
Input leakage current, Receiver disabled, pulldown enabled
51
110
210
Total leakage current through the terminal connection of a driverreceiver combination that may include a pullup or pulldown. The
IOZ
18driver output is disabled and the pullup or pulldown is inhibited.
TCK (VDDSHV6 = 1.8 V)
High-level input voltage
VIH
1.45
Low-level input voltage
VIL
0.46
Hysteresis voltage at an input
VHYS
0.4
Input leakage current, Receiver disabled, pullup or pulldown inhibited
8
II
Input leakage current, Receiver disabled, pullup enabled
-161
-100
-52
Input leakage current, Receiver disabled, pulldown enabled
52
100
170
TCK (VDDSHV6 = 3.3 V)
High-level input voltage
VIH
2.15
Low-level input voltage
VIL
0.46
Hysteresis voltage at an input
VHYS
0.4
Input leakage current, Receiver disabled, pullup or pulldown inhibited
18
I
I
Input leakage current, Receiver disabled, pullup enabled
-243
-100
-19
Input leakage current, Receiver disabled, pulldown enabled
51
110
210
PWRONRSTn (VDDSHV6 = 1.8 or 3.3 V) 4/
High-level input voltage
VIH
1.35
Low-level input voltage
VIL
0.5
Hysteresis voltage at an input
VHYS
0.07
VI = 1.8 V
Input leakage current
II
0.1
VI = 3.3 V
2

V
V
V
V
V
μA

μA

V
V
V
μA

V
V
V
μA

V
V
V
μA

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

V62/15602

REV

PAGE

17

TABLE I. Electrical performance characteristics- Continued. 1/ 2/ 3/
Test

SymbolLimits
Min

Unit

Typ

Max

DC Electrical Characteristics (Continued) 3/
RTC_PWRONRSTn
High-level input voltage

VIH

Low-level input voltage

VIL

Hysteresis voltage at an input

VHYS
II

0.065
-1

VOH

VDDS_RTC –0.45

Input leakage current
PMIC_POWER_EN
High level output voltage, driver enabled, pullup or
pulldown disabled

IOH = 6 mA

Low level output voltage, driver enabled, pullup
IOL = 6 mA
orpulldown disabled
Input leakage current, Receiver disabled, pullup or pulldown inhibited
Input leakage current, Receiver disabled, pullup enabled
Input leakage current, Receiver disabled, pulldown enabled
Total leakage current through the terminal connection of a driverreceiver combination that may include a pullup or pulldown. The driver
output is disabled and the pullup or pulldown is inhibited.

V

0.65 ×
VDDS_RTC
0.35 ×
VDDS_RTC

VOL

1

V
V
μA
V

0.45

V

II

-1
-200
40

1
-40
200

μA

IOZ

-1

1

μA

High-level input voltage

VIH

0.65 ×
VDDS_RTC

Low-level input voltage

VIL

Hysteresis voltage at an input
Input leakage current, Receiver disabled, pullup or pulldown inhibited
Input leakage current, Receiver disabled, pullup enabled
Input leakage current, Receiver disabled, pulldown enabled

VHYS

EXT_WAKEUP

V
0.35 ×
VDDS_RTC

0.15
-1
-200
40

II

V
V

1
-40
200

μA

XTALIN (OSC0)
High-level input voltage

VIH

Low-level input voltage

VIL

RTC_XTALIN (OSC1)

I

High-level input voltage

VIH

Low-level input voltage

VIL

I

0.65 ×
VDDS_OSC

I

V

I

I

0.35 ×
VDDS_OSC

V

0.65 ×
VDDS_RTC

I

V

I

I

0.35 ×
VDDS_RTCV

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

V62/15602

REV

PAGE

18

TABLE I. Electrical performance characteristics- Continued. 1/ 2/ 3/
Test

SymbolLimits
Min

Typ

Unit
Max

DC Electrical Characteristics (Continued) 3/

All other LVCMOS pins (VDDSHVx = 1.8 V; x = 1 to 6)
High-level input voltage

VIH

Low-level input voltage

VIL

Hysteresis voltage at an input
High level output voltage, driver enabled, pullup or
pulldown disabled

VHYS
VOH

IOH = 6 mA

Low level output voltage, driver enabled, pullup
IOL = 6 mA
orpulldown disabled
Input leakage current, Receiver disabled, pullup or pulldown inhibited
Input leakage current, Receiver disabled, pullup enabled
Input leakage current, Receiver disabled, pulldown enabled
Total leakage current through the terminal connection of a driverreceiver combination that may include a pullup or pulldown. The
driver output is disabled and the pullup or pulldown is inhibited.
All other LVCMOS pins (VDDSHVx = 3.3 V; x = 1 to 6)
High-level input voltage
Low-level input voltage
Hysteresis voltage at an input
High level output voltage, driver enabled, pullup or IOH = 6 mA
pulldown disabled
Low level output voltage, driver enabled, pullup
IOL = 6 mA
orpulldown disabled
Input leakage current, Receiver disabled, pullup or pulldown inhibited
Input leakage current, Receiver disabled, pullup enabled
Input leakage current, Receiver disabled, pulldown enabled
Total leakage current through the terminal connection of a driverreceiver combination that may include a pullup or pulldown. The
driver output is disabled and the pullup or pulldown is inhibited.

0.65 ×
VDDSHVxV

0.18
VDDSHVx –
0.45

VOL

II

-161
52

-100
100

0.45

V

8
-52
170

μA

2
0.8
0.44

0.265
VDDSHVx –
0.45

-243
51

V
V

μA
V
V
V
V

VOL

II

V

8

IOZ

VIH
VIL
VHYS
VOH

0.35 ×
VDDSHVx
0.305

-100
110

0.45

V

18
-19
210

μA

18

IOZ

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

V62/15602

REV

PAGE

19

TABLE I. Electrical performance characteristics - Continued. 1/ 2/ 3/
Test

SymbolTest conditions

LimitsMin

Core Voltage Decoupling Characteristics
CVDD_COR
CVDD_MPU

Unit

Typ

Max

5.9 External Capacitors

5/
6/Power-Supply Decoupling Capacitor Characteristics
CVDDA_ADC
CVDDA1P8V_USB0
CCVDDA3P3V_USB0
CVDDA3P3V_USB1
CVDDS 7/CVDDS_DDR
CVDDS_OSC
CVDDS_PLL_DDR
CVDDS_PLL_CORE_LCD
CVDDS_SRAM_CORE_BG 9/CVDDS_SRAM_MPU_BB 10/
CVDDS_PLL_MPU
CVDDS_RTC
CVDDSHV1 11/
CVDDSHV2 11/
CVDDSHV3 11/
CVDDSHV4 11/
CVDDSHV5 11/
CVDDSHV6 12/

Output Capacitor Characteristics
CCAP_VDD_SRAM_CORE 13/
CCAP_VDD_RTC 13/ 14/
CCAP_VDD_SRAM_MPU 13/
CCAP_VBB_MPU 13/

I

I

10.08
10.05

μF

10
10
10
10
10.04
8/
10
10
10
10.01
10.01
10
10
10.02
10.02
10.02
10.02
10.02
10.06

nF

1
1
1
1

μF
nF

μF

μF

I

I

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

V62/15602

REV

PAGE

20

TABLE I. Electrical performance characteristics - Continued. 1/ 2/ 3/
Test

Test conditions

Limits
Min

Unit

Typ

Max

Touch Screen Controller and Analog-to-Digital Subsystem Electrical Parameters

TSC_ADC Electrical Parameters
Analog Input

VREFP

15/

VREFN

15/

VREFP + VREFN 15/
Full-scale input range

Differential non-linearity(DNL)

Integral non-linearity (INL)

Gain error

Offset error
Input sampling capacitance

Signal-to-noise ratio (SNR)

Total harmonic distortion THD)

(0.5 × VDDA_ADC) +0.25
0Internal voltage reference
External voltage reference
Internal voltage reference:
VDDA_ADC = 1.8 V
External voltage reference:
VREFP – VREFN = 1.8 V
Source impedance = 50 Ω
Internal voltage reference:
VDDA_ADC = 1.8 V
External voltage reference:
VREFP – VREFN = 1.8 V
Source impedance = 1 kΩInternal voltage reference:
VDDA_ADC = 1.8 V
External voltage reference:
VREFP – VREFN = 1.8 V
Internal voltage reference:
VDDA_ADC = 1.8 V
External voltage reference:
VREFP – VREFN = 1.8 V
Internal voltage reference:
VDDA_ADC = 1.8 V
External voltage reference:
VREFP – VREFN = 1.8 V

VDDA_ADC

V(0.5 × VDDA_ADC)– 0.25V

VDDA_ADC0
VREFN

VDDA_ADC
VREFP

V
V
V

-1

0.5

1

LSB

-2

±1

2

LSB

Internal voltage reference:
VDDA_ADC = 1.8 V
External voltage reference:
VREFP – VREFN = 1.8 V
Input signal: 30-kHz sine
wave at –0.5-dB full scaleInternal voltage reference:
VDDA_ADC = 1.8 V
External voltage reference:
VREFP – VREFN = 1.8 V
Input signal: 30-kHz sine
wave at –0.5-dB full scale

±1

LSB

±2

LSB

±2

LSB

5.5

pF

70

dB

75

dB

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

V62/15602

REV

PAGE

21

TABLE I. Electrical performance characteristics - Continued. 1/ 2/ 3/
Test

Test conditions

Limits
Min

Unit

Typ

Max

Touch Screen Controller and Analog-to-Digital Subsystem Electrical Parameters - Continued

TSC_ADC Electrical Parameters - Continued

Internal voltage reference:
VDDA_ADC = 1.8 V
External voltage reference:
Spurious free dynamic range
VREFP – VREFN = 1.8 V
Input signal: 30-kHz sine wave
at –0.5-dB full scaleInternal voltage reference:
VDDA_ADC = 1.8 V
External voltage reference:
Signal-to-noise plus distortion
VREFP – VREFN = 1.8 V
Input signal: 30-kHz sine wave
at –0.5-dB full scale
VREFP and VREFN input impedance
Input impedance of AIN[7:0] 15/
Sampling Dynamics
Conversion time
Acquisition time
Sampling rate
ADC clock = 3 MHz
Channel-to-channel isolation
Touch Screen Switch Drivers
Pull-up and pull-down switch ON resistance (Ron)Pull-up and pull-down
Source impedance = 500 Ω
switch current leakage Ileak
I
Drive current
Touch screen resistancePen touch detect

80

dB

69

dB

20

kΩ

[1 / ((65.97 × 10–12) × ƒ)]Ω
ADC
Clock cycles

15
2
200
100

I

I

2

kSPS
dB

0.5

Ω
uA

25
6
2

mA
kΩ
kΩ

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

V62/15602

REV

PAGE

22

TABLE I. Electrical performance characteristics - Continued. 1/ 2/
SUPPLY NAME

LimitsDESCRIPTION

Min

Unit

Typ

Max

1.71

1.8

1.89

V

1.71

1.8

1.71

1.8

1.71

1.8

50
1.89
50
1.89
50
1.89
50

mV (p-p)VmV (p-p)VmV (p-p)VmV (p-p)Power and Clocking (See Figure 6 to Figure 12)

Digital Phase-Locked Loop Power Supply Requirements
DPLL Power Supply Requirements (See Figure 13)
VDDA1P8V_USB0

VDDS_PLL_MPU
VDDS_PLL_CORE_LCD
VDDS_PLL_DDR

Supply voltage range for USBPHY and PER DPLL, Analog,
1.8 V
Max peak-to-peak supply noise
Supply voltage range for DPLL MPU, analog
Max peak-to-peak supply noise
Supply voltage range for DPLL CORE and LCD, analog
Max peak-to-peak supply noise
Supply voltage range for DPLL DDR, analog
Max peak-to-peak supply noise

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

V62/15602

REV

PAGE

23

TABLE I. Electrical performance characteristics - Continued. 1/ 2/
Test

SymbolTest conditions

LimitsMin

OSC0 Crystal Circuit Requirements
Crystal parallel resonance frequency

ƒxtal

CC1
CC2

Shunt capacitance

CshuntFundamental mode oscillation only

19.2, 24,
25 or 26

ESR

Frequency, LVCMOS reference clockstability and tolerance 17/
Duty cycle, LVCMOS reference clock period

50

Cshunt ≤ 5 pF

12

24

18

24

Cshunt ≤ 5 pF

12

24

Cshunt > 5 pF

18

24
7

ƒxtal = 19.2 MHz, oscillator has nominal
negative resistance of 272 Ω andworstcase negative resistance of 163 Ωƒxtal = 24 MHz, oscillator has nominal
negative resistance of 240 Ω andworstcase negative resistance of 144 Ωƒxtal = 25 MHz, oscillator has nominal
negative resistance of 233 Ω andworstcase negative resistance of 140 Ωƒxtal = 26 MHz, oscillator has nominal
negative resistance of 227 Ω andworstcase negative resistance of 137 Ω

54.5

ppm

pF

pF
Ω

48.0
46.6
45.3

0.01

Cpkg

pF

18

tsX

OSC0 LVCMOS Reference Clock Requirements
Frequency, LVCMOS reference clock

MHz

Cshunt > 5 pF

OSC0 Crystal Circuit Characteristics (See Figure 14)
Shunt capacitance of package
The actual values of the ESR, ƒxtal, and CL
should be used to yield a typical crystal
power dissipation value. Using the maximum
values specified for ESR, ƒxtal, and CL
parameters yields a maximum
powerdissipation value.
Start-up time

Max

-50

C2 capacitance

Crystal effective series resistance

TypPower and Clocking – Continued.
Clock Specifications

Crystal frequency stability and tolerance
17/
C1 capacitance

Unitƒ(XTALIN)

1.5

ms

19.2, 24,
25 or 26

MHz

-50

50

ppm

tdc(XTALIN)

45%

55%

Jitter peak-to-peak, LVCMOS reference
clock period
Time, LVCMOS reference clock risetjpp(XTALIN)

-1%

1%

tR(XTALIN)

5

ns

Time, LVCMOS reference clock falltF(XTALIN)5ns

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

V62/15602

REV

PAGE

24

TABLE I. Electrical performance characteristics - Continued. 1/ 2/ 3/
DESCRIPTION

SymbolLimitsMin

OSC1 Crystal Circuit Requirements
Crystal parallel resonancefrequency
Crystal frequency stability andtolerance 17/
C1 capacitanceC2 capacitance
Shunt capacitance
Crystal effective series
resistance

Typ

Unit
Max

Power and Clocking – Continued.
Clock Specifications

Fundamental mode oscillation onlyƒxtalMaximum RTC error = 10.512
minutes per year
Maximum RTC error = 26.28 minutes
per year

CC1
CC2
CshuntESRƒxtal = 32.768 kHz, oscillator has
nominal negative resistance of 725
kΩ and worstcase negative
resistance of 250 kΩ

OSC1 Crystal Circuit Characteristics(See Figure 15)

Shunt capacitance of GCZ package
The actual values of the ESR, ƒxtal, and CL should be used to yield atypical crystal power dissipation value. Using the maximum values
specified for ESR, ƒxtal, and CL parameters yields a maximum power
dissipation value.
Start-up time

OSC1 LVCMOS Reference Clock Requirements (See Figure 16)
Frequency, LVCMOS reference clock
Frequency, LVCMOS reference
Maximum RTC error =10.512
minutes/year
clock 21/
Maximum RTC error =26.28
minutes/year
Duty cycle, LVCMOS reference clock period
Jitter peak-to-peak, LVCMOS reference clock period
Time, LVCMOS reference clock rise
Time, LVCMOS reference clock fall

32.768

kHz

-20.0

20.0

ppm

-50.0

50.0

ppm

12.0
12.0

24.0
24.0
1.5
80

pF
pF
pF
kΩ

Cpkg
Pxtal

0.01
20/

pF

tsX

2

s

ƒ(RTC_XTALIN)

32.768tdc(RTC_XTALIN)
tjpp(RTC_XTALIN)tR(RTC_XTALIN)
tF(RTC_XTALIN)

-20.0

20.0

kHz
ppm

-50.0

50.0

ppm

45%
-1%

55%
1%
5
5

ns
ns

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

V62/15602

REV

PAGE

25

TABLE I. Electrical performance characteristics - Continued. 1/ 2/ 3/
No

Test

SymbolLimits
Min

Unit

Typ

Max

Peripheral Information and Timings

Controller Area Network (CAN)
Timing Requirements for DCANx Receive (See Figure 17)
1

Maximum programmable baud rate
Pulse duration, receive data bitƒbaud(baud)tw(RX)

H – 2 22/1
H + 2 22/Mbps
ns

H – 2 22/1
H + 2 22/Mbps
ns

Switching Characteristics for DCANx Transmit (See Figure 17)
2

Maximum programmable baud rate
Pulse duration, transmit data bitƒbaud(baud)tw(TX)

DMTimer Electrical Data and Timing
Timing Requirements for DMTimer [1-7] (See Figure 18)
1

Cycle time, TCLKIN

tc(TCLKIN)

Switching Characteristics for DMTimer [4-7]23

Pulse duration, highPulse duration, low(See Figure 18)
tw(TIMERxH)
tw(TIMERxL)

4P + 1 23/

ns

4P - 3 23/
4P - 3 23/

ns
ns

Ethernet Media Access Controller (EMAC) and Switch
EMAC and Switch Timing Conditions
Input Conditions

Input signal rise time
Input signal fall time
Output Condition
Output load capacitanceTiming Requirements for MDIO_DATA
1
2

tR
tF
CLOAD

Setup time, MDIO valid before MDC highHold time, MDIO valid from MDC highCycle time, MDC
Pulse duration, MDC highPulse duration, MDC low
Transition time, MDC

Switching Characteristics for MDIO_DATA
1

Delay time, MDC high to MDIO valid

24/
24/

5
5

3

(See Figure 19)

Switching Characteristics for MDIO_CLK
1
2
3
4

1
1

tsu(MDIO-MDC)
th(MDIO-MDC)(See Figure 20)

tc(MDC)
tw(MDCH)
tw(MDCL)tt(MDC)(See Figure 21)

td(MDC-MDIO)

24/
24/

ns
ns

30

pF

90
0

ns
ns

400
160
160

5

ns
ns
ns
ns

390

ns

I

I

10

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

V62/15602

REV

PAGE

26

TABLE I. Electrical performance characteristics - Continued. 1/ 2/ 3/
No

Test

Symbol
10 Mbps
Typ

I

I

Limits100 Mbps
Max
Min

I Min
Peripheral Information and Timings - Continued

I

Unit

I Typ I Max I

Ethernet Media Access Controller (EMAC) and Switch – Continued.

Timing Requirements for GMII[x]_RXCLK - MII Mode

(See Figure 22)

Timing Requirements for GMII[x]_TXCLK - MII Mode

(See Figure 23)

1
2
3
4
1
2
3
4

Cycle time, RX_CLK
Pulse duration, RX_CLK highPulse duration, RX_CLK low
Transition time, RX_CLKCycle time, TX_CLK
Pulse duration, TX_CLK highPulse duration, TX_CLK low
Transition time, TX_CLKtc(RX_CLK)
tw(RX_CLKH)
tw(RX_CLKL)
tt(RX_CLK)tc(TX_CLK)
tw(TX_CLKH)
tw(TX_CLKL)
tt(TX_CLK)I
I

399.96140140399.96
140
140

I
I

I

400.04
260
260
5

I

400.04
260
260
5

I
I

39.99614
14

39.99614
14

Timing Requirements for GMII[x]_RXD[3:0], GMII[x]_RXDV, and GMII[x]_RXER - MII Mode12

Setup time, RXD[3:0] valid before RX_CLK
Setup time, RX_DV valid before RX_CLK
Setup time, RX_ER valid before RX_CLK
Hold time RXD[3:0] valid after RX_CLK
Hold time RX_DV valid after RX_CLK
Hold time RX_ER valid after RX_CLK1>--------+-------------I
td(TX_CLK-TXD)

td(TX_CLK-TX_EN)

I

ns
ns
ns
ns

I

ns
ns
ns
ns

8

8

ns

8

8

ns

Switching Characteristics for GMII[x]_TXD[3:0], and GMII[x]_TXEN - MII Mode
Delay time, TX_CLK high to TXD[3:0] valid
Delay time, TX_CLK to TX_EN valid

I I

40.00426
26
5(See Figure 24)

tsu(RXD-RX_CLK)

tsu(RX_DV-RX_CLK)
tsu(RX_ER-RX_CLK)th(RX_CLK-RXD)th(RX_CLK-RX_DV)th(RX_CLK-RX_ER)

I I

40.00426
26
5

5(See Figure 25)

I I I I I I
25

5

25

ns

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

V62/15602

REV

PAGE

27

TABLE I. Electrical performance characteristics - Continued. 1/ 2/ 3/
No

Test

SymbolLimits
Min

Typ

Unit
Max

Peripheral Information and Timings - Continued

Ethernet Media Access Controller (EMAC) and Switch – Continued.

Timing Requirements for RMII[x]_REFCLK - RMII Mode (See Figure 26)
12
3

Cycle time, REF_CLK
Pulse duration, REF_CLK highPulse duration, REF_CLK lowtc(REF_CLK)
tw(REF_CLKH)
tw(REF_CLKL)

19.999
7
7

Timing Requirements for RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RXER - RMII Mode12tsu(RXD-REF_CLK)

20.001
13
13

ns
ns
ns

(See Figure 27)

Setup time, RXD[1:0] valid before REF_CLK
Setup time, CRS_DV valid before REF_CLK
Setup time, RX_ER valid before REF_CLK
Hold time RXD[1:0] valid after REF_CLK

tsu(CRS_DV-REF_CLK)
tsu(RX_ER-REF_CLK)th(REF_CLK-RXD)

4

ns

Hold time, CRS_DV valid after REF_CLK
Hold time, RX_ER valid after REF_CLKth(REF_CLK-CRS_DV)
th(REF_CLK-RX_ER)

2

ns

Switching Characteristics for RMII[x]_TXD[1:0], and RMII[x]_TXEN - RMII Mode (See Figure 28)
Delay time, REF_CLK high to TXD[1:0] validtd(REF_CLK-TXD)

2

Delay time, REF_CLK to TXEN valid
Rise time, TXD outputs

td(REF_CLK-TXEN)
tr(TXD)

3

Rise time, TX_EN output
Fall time, TXD outputs

tr(TX_EN)tf(TXD)

Fall time, TX_EN output

tf(TX_EN)

1

2

13

1

5

1

5

ns
ns
ns

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

V62/15602

REV

PAGE

28

TABLE I. Electrical performance characteristics - Continued. 1/ 2/ 3/
No

Test

Symbol10 Mps
Min
Max
I

I

I

Limits100 Mps
Min
Max

I

Peripheral Information and Timings - Continued

Unit

I

1000 Mps
Min
Max

I

I

Ethernet Media Access Controller (EMAC) and Switch – Continued.

Timing Requirements for RGMII[x]_RCLK - RGMII Mode1234

Cycle time, RXC
Pulse duration, RXC highPulse duration, RXC low
Transition time, RXC(See Figure 29)tc(RXC)
tw(RXCH)
tw(RXCL)tt(RXC)

I

360
160
160

I

440
240
240
0.75

36
16
16

2
3

Setup time, RD[3:0] valid before RXC high or low
Setup time, RX_CTL valid before RXC high or low
Hold time, RD[3:0] valid after RXC high or low
Hold time, RX_CTL valid after RXC high or low
Transition time, RD
Transition time, RX_CTL

tsu(RD-RXC)
tsu(RX_CTL-RXC)th(RXC-RD)th(RXC-RX_CTL)
tt(RD)
tt(RX_CTL)

1
1
1
1

Cycle time, TXC
Pulse duration, TXC highPulse duration, TXC low
Transition time, TXC

tc(TXC)
tw(TXCH)
tw(TXCL)tt(TXC)

1
1
1
1

I

360
160
160

I

440
240
240
0.75

I

0.5
0.5
0.75
0.75

I

I

44
24
24
0.75

I

0.5
0.5
0.75
0.75

I

7.2
3.6
3.6

Switching Characteristics for RGMII[x]_TD[3:0], and RGMII[x]_TCTL - RGMII Mode (See Figure 32)
1
2

TD to TXC output skew
TX_CTL to TXC output skew
Transition time, TD
Transition time, TX_CTL

tsk(TD-TXC)
tsk(TX_CTL-TXC)
tt(TD)tt(TX_CTL)

-0.5
-0.5

I

-0.5
-0.5

I

I

0.75
0.75

I

8.8
4.4
4.4
0.75

I

ns
ns
ns
ns

I

0.5
0.5
0.75
0.75

I

ns
ns
ns
ns

-0.5
-0.5

I

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

0.75
0.75
36
16
16

8.8
4.4
4.4
0.75

1
1
1
1

0.75
0.75

Switching Characteristics for RGMII[x]_TCLK - RGMII Mode (See Figure 31)
1
2
3
4

7.2
3.6
3.6

I (See Figure
I I30) ITiming Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL - RGMII Mode
1

44
24
24
0.75

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

V62/15602

REV

PAGE

29

TABLE I. Electrical performance characteristics - Continued. 1/ 2/
Test

SymbolLimits
Min

Unit

Typ

Max

Peripheral Information and Timings – Continued

External Memory Interfaces - General-Purpose Memory Controller (GPMC)

GPMC and NOR Flash Timing Conditions—Synchronous Mode
Input Conditions(See Figure 33 through 37)

Input signal rise time

tR

1

5

ns

Input signal fall time

tF

1

5

ns

CLOAD

3

30

pF

Output Condition
Output load capacitance

No

Test

SymbolLimitsUnit

OPP100
Min

OP50
Max

Min

Max

Peripheral Information and Timings – Continued

External Memory Interfaces – General-Purpose Memory Controller (GPMC) - Continued

GPMC and NOR Flash Timing Requirements – Synchronous Modee 27/ (See Figure 33 through 37)

F0

Setup time, input data gpmc_ad[15:0] valid before
output clock gpmc_clk highHold time, input data gpmc_ad[15:0] valid after output
clock gpmc_clk highSetup time, input wait gpmc_wait[x] 25/
valid before output clock gpmc_clk highHold time, input wait gpmc_wait[x] 25/
valid after output clock gpmc_clk highFrequency 40/, output clock gpmc_clk

F1

Typical pulse duration, output clock gpmc_clk high

F1

F12
F13
F21
F22

tsu(dV-clkH)

3.2

11.1

ns

th(clkH-dV)

4.74

4.74

ns

tsu(waitV-clkH)

3.2

3.2

ns

th(clkH-waitV)

4.74

4.74

ns

1 / tc(clk)

50

MHz

tw(clkH)

0.5P 37/

0.5P 37/100
0.5P 37/

0.5P 37/

ns

Typical pulse duration, output clock gpmc_clk low

tw(clkL)

0.5P 37/

0.5P 37/

0.5P 37/

0.5P 37/ns

Duty cycle error, output clock gpmc_clk

tdc(clk)

-500

500

-500

500

ps

Jitter standard deviation 30/, output clock gpmc_clk

tJ(clk)

33.33

33.33

ps

Rise time, output clock gpmc_clk

tR(clk)2

2

ns

Fall time, output clock gpmc_clk

tF(clk)2

2

ns

Rise time, output data gpmc_ad[15:0]

tR(do)

2

2

ns

Fall time, output data gpmc_ad[15:0]

tF(do)

2

2

ns

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

V62/15602

REV

PAGE

30

TABLE I. Electrical performance characteristics - Continued. 1/ 2/
No

Test

SymbolLimits
OPP100Min I Max

Peripheral Information and Timings – Continued

Unit
OP50

I
I

Min

I

Max

External Memory Interfaces - General-Purpose Memory Controller (GPMC) - Continued

GPMC and NOR Flash Switching Characteristics – Synchronous Mode - Continued 27/ (See Figure 33 through 37)
F2

Delay time, output clock gpmc_clk rising edge to output chip
select gpmc_csn[x] 26/ transition

td(clkH-csnV)

F – 2.2
31/

F + 4.5
31/

F – 3.2
31/

F + 9.5
31/

ns

F3

Delay time, output clock gpmc_clk rising edge to output chip
select gpmc_csn[x] 26/ invalidtd(clkH-csnIV)E – 2.2
30/

E + 4.5
30/

E – 3.2
30/

E + 9.5
30/

ns

F4

Delay time, output address gpmc_a[27:1] valid to output clock
gpmc_clk first edgetd(aV-clk)

B – 4.5
27/

B + 2.3
27/

B – 5.5
27/

B + 12.3
27/

ns

F5

Delay time, output clock gpmc_clk rising edge to output address
gpmc_a[27:1] invalidtd(clkH-aIV)

-2.3

4.5

-3.3

14.5

ns

F6

Delay time, output lower byte enable and command latch enablegpmc_be0n_cle, output upper byte enable gpmc_be1n valid to
output clock gpmc_clk first edgetd(be[x]nV-clk)

B – 1.927/

B + 2.3
27/

B – 2.927/

B + 12.3
27/

ns

F7

Delay time, output clock gpmc_clk rising edge to output lower byte
enable and command latch enable gpmc_be0n_cle, output upperbyte enable gpmc_be1n invalidtd(clkH-D – 2.3
29/

D + 1.9
29/

D – 3.3
29/

D + 11.929/nsbe[x]nIV)

F8

Delay time, output clock gpmc_clk rising edge to output address
valid and address latch enable gpmc_advn_ale transition

td(clkH-advn)

G – 2.3
32/

G + 4.5
32/

G – 3.3
32/

G + 9.5
32/

ns

F9

Delay time, output clock gpmc_clk rising edge to output address
valid and address latch enable gpmc_advn_ale invalidtd(clkH-advnIV)

D – 2.3
29/

D + 3.5
29/

D – 3.3
29/

D + 9.5
29/

ns

F10

Delay time, output clock gpmc_clk rising edge to output enablegpmc_oen transition

td(clkH-oen)

H – 2.3
33/

H + 3.5
33/

H – 3.3
33/

H + 8.5
33/

ns

F11

Delay time, output clock gpmc_clk rising edge to output enablegpmc_oen invalidtd(clkH-oenIV)

E– 2.333/

E + 3.5
33/

E – 3.3
33/

E + 8.5
33/

ns

F14

Delay time, output clock gpmc_clk rising edge to output write
enable gpmc_wen transition

td(clkH-wen)

I – 2.3
34/

I + 4.5
34/

I – 3.3
34/

I + 9.5
34/

ns

F15

Delay time, output clock gpmc_clk rising edge to output data
gpmc_ad[15:0] transition

td(clkH-do)

J – 2.3
25/

J + 1.925/

J – 3.3
25/

J + 11.9
25/

ns

F17

Delay time, output clock gpmc_clk rising edge to output lower byte
enable and command latch enable gpmc_be0n_cle transition

td(clkH-be[x]n)J – 2.3
25/

J + 1.925/

J – 3.3
25/

J + 11.9
25/

ns

F18

Pulse duration, output chip selectgpmc_csn[x] 26/
lowtw(csnV)

A 26/

A 26/

ns

A 26/

A 26/

ns

C 28/

C 28/

ns

C 28/

C 28/

ns

K 38/

K 38/

ns

K 38/

K 38/

ns

F19
F20

Pulse duration, output lower byte enable andcommand latch enable gpmc_be0n_cle, output upperbyte enable gpmc_be1n low
Pulse duration, output address valid and address
latch enable gpmc_advn_ale low

Read
Write
Read

tw(be[x]nV)

Write
Read

tw(advnV)

Write

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

V62/15602

REV

PAGE

31

TABLE I. Electrical performance characteristics - Continued. 1/ 2/
Test

SymbolLimits
Min

Unit

Typ

Max

Peripheral Information and Timings – Continued

External Memory Interfaces - General-Purpose Memory Controller (GPMC)

GPMC and NOR Flash Timing Conditions—Asynchronous Mode

(See figure 38 through 43)

Input Conditions

Input signal rise time
Input signal fall time
Output Condition
Output load capacitance

No

tR
tF

1
1

5
5

ns
ns

CLOAD

3

30

pF

Test

Limits
OPP100
Min

I

Max

I
I

Unit
OPP50
Min

I

Max

GPMC and NOR Flash Internal Timing Parameters—Asynchronous Mode – Continued. 42/ 43/(See Figure 38 through 43)
FI1

Delay time, output data gpmc_ad[15:0] generation frominternal functional clock GPMC_FCLK 44/

6.5

6.5

ns

FI2

Delay time, input data gpmc_ad[15:0] capture from internalfunctional clock GPMC_FCLK 44/

4

4

ns

FI3

Delay time, output chip select gpmc_csn[x] generation frominternal functional clock GPMC_FCLK 44/

6.5

6.5

ns

FI4

Delay time, output address gpmc_a[27:1] generation frominternal functional clock GPMC_FCLK 44/

6.5

6.5

ns

FI5

Delay time, output address gpmc_a[27:1] valid from internalfunctional clock GPMC_FCLK 44/

6.5

6.5

ns

FI6

Delay time, output lower-byte enable and command latch
enable gpmc_be0n_cle, output upper-byte enablegpmc_be1n generation from internal functional clock
GPMC_FCLK 44/

6.5

6.5

ns

FI7

Delay time, output enable gpmc_oen generation frominternal functional clock GPMC_FCLK 44/

6.5

6.5

ns

FI8

Delay time, output write enable gpmc_wen generation frominternal functional clock GPMC_FCLK 44/

6.5

6.5

ns

FI9

Skew, internal functional clock GPMC_FCLK 44/

100

100

ns

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

V62/15602

REV

PAGE

32

TABLE I. Electrical performance characteristics - Continued. 1/ 2/
No

Test

SymbolLimitsUnit

OPP100
Min

I

I

OPP50
Max

I

Peripheral Information and Timings – Continued

Min

Max

I

External Memory Interfaces - General-Purpose Memory Controller (GPMC)

GPMC and NOR Flash Timing Requirements—Asynchronous Mode - Continued. (See Figure 38 through 43)
FA5 -45/

Data access time

FA20 46/

Page mode successive data access time

tacc1-pgmode(d)tacc(d)FA21 -47/

I Page mode first data access time

tacc2-pgmode(d)H -49/P 48/

I

H -49/I

I

H -49/

ns

P 48/

ns

H -49/

I ns

See footnote at end of table.
No

Test

LimitsSymbolI

I Min I Max

2

2

I

GPMC and NOR Flash Switching Characteristics—Asynchronous Mode – Continued(See Figure 38 through 43)
Rise time, output data gpmc_ad[15:0]tR(d)Fall time, output data gpmc_ad[15:0]
FA0
FA1
FA3

Pulse duration, output lower-byte enable andcommand latch enable gpmc_be0n_cle, output
upper-byte enable gpmc_be1n valid time

Read

Pulse duration, output chip selectgpmc_csn[x] 63/ low

Read

Delay time, output chip select gpmc_csn[x] 63/
valid to output address valid and address latch
enable gpmc_advn_ale invalid

Read

Unit

OPP100
Min
Max

OPP50

I
ns

tF(d)

2

2

ns

tw(be[x]nV)

N 62/

N 62/

ns

N 62/

N 62/

ns

A 51/

A 51/

ns

A 51/

A 51/

ns

Write

tw(csnV)Write

td(csnV-advnIV)B – 0.2-52/

B + 2.0
-52/

B–5
-52/

B+5
-52/

ns

B+5
52/

ns

B – 0.2
52/

Write

B + 2.0
52/

B–5
52/

FA4

Delay time, output chip select gpmc_csn[x] 63/ valid to
output enable gpmc_oen invalid (Single
read)td(csnV-oenIV)C – 0.2
53/

C + 2.0
53/

C–5
53/

C+5
53/

ns

FA9

Delay time, output address gpmc_a[27:1] valid to output
chip select gpmc_csn[x] 63/ validtd(aV-csnV)

J – 0.2
59/

J + 2.0
59/

J–5
59/

J+5
59/

ns

Delay time, output lower-byte enable and command latch
enable gpmc_be0n_cle, output upper-byte enablegpmc_be1n valid to output chip select gpmc_csn[x] 63/
validtd(be[x]nV-csnV)

J – 0.2
59/

J + 2.0
59/

J–5
59/

J+5
59/

ns

FA10

Delay time, output chip select gpmc_csn[x] 63/ valid to
output address valid and address latch enablegpmc_advn_ale validtd(csnV-advnV)

K – 0.2
60/

K + 2.0
60/

K–5
60/

K+5
60/

ns

FA12

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

V62/15602

REV

PAGE

33

No

Test

SymbolLimitsMin

OPP100Max

Peripheral Information and Timings – Continued

Unit
OPP50

I Min I Max

External Memory Interfaces - General-Purpose Memory Controller (GPMC)

GPMC and NOR Flash Switching Characteristics—Asynchronous Mode (See Figure 38 through 43)
FA13

Delay time, output chip select gpmc_csn[x] 63/ valid to
output enable gpmc_oen validtd(csnV-oenV)

FA16

Pulse durationm output address gpmc_a[26:1] invalid
between 2 successive read and write accesses
Delay time, output chip select gpmc_csn[x] 63/ valid to
output enable gpmc_oen invalid (Burst read)L – 0.2
61/

tw(aIV)G 57/

td(csnV-oenIV)I – 0.2
58/

tw(aV)

G 57/

td(csnV-wenV)E – 0.2
55/

E + 2.0
55/

E–5
55/

E+5
55/

ns

F – 0.2
58/

F + 2.0
58/

F– 5
58/

F+5
58/

ns

5

ns

J+5
59/

ns

5

ns

FA18
FA20
FA25

Pulse duration, output address gpmc_a[27:1] valid - 2nd,
3rd, and 4th accesses
Delay time, output chip select gpmc_csn[x] 63/ valid to
output write enable gpmc_wen valid

FA27

Delay time, output chip select gpmc_csn[x] 63/ valid to
output write enable gpmc_wen invalidtd(csnV-wenIV)

FA28

Delay time, output write enable gpmc_ wen valid to output
data gpmc_ad[15:0] valid
Delay time, output data gpmc_ad[15:0] valid to output
chip select gpmc_csn[x] 63/ valid

td(wenV-dV)Delay time, output enable gpmc_oen valid to output
address gpmc_ad[15:0] phase end

td(oenV-aIV)

FA29
FA37

td(dV-csnV)

L + 2.0
61/

L–5
61/

L+5
61/

G 57/
I + 2.0
58/

ns

L–5
58/

L+5
58/

G 57/

J + 2.0
59/

ns
ns

2.0
J – 0.2
59/

ns

J–5
59/

2.0

See footnote at end of table.

Test

SymbolLimits
Min

Unit

Typ

Max

Peripheral Information and Timings – Continued

External Memory Interfaces - General-Purpose Memory Controller (GPMC)

GPMC and NAND Flash—Asynchronous Mode
GPMC and NAND Flash Timing Conditions—Asynchronous Mode (See Figure 44 through 47)
Input Conditions

Input signal rise time
Input signal fall time
Output Condition
Output load capacitance

tR
tF

1
1

5
5

ns
ns

CLOAD

3

30

pF

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

V62/15602

REV

PAGE

34

TABLE I. Electrical performance characteristics - Continued. 1/ 2/
No

Test

Limits
OPP100
Min

I

Unit
OPP50

I
Max

Peripheral Information and Timings – Continued

I

Min

I

Max

External Memory Interfaces - General-Purpose Memory Controller (GPMC)

GPMC and NAND Flash—Asynchronous Mode
GPMC and NAND Flash Internal Timing Parameters—Asynchronous Mode 64/ 65/ (See Figure 44 through 47)
GNFI1
GNFI2
GNFI3
GNFI4
GNFI5
GNFI6
GNFI7
GNFI8

Delay time, output data gpmc_ad[15:0] generation from internalfunctional clock GPMC_FCLK) 50/
Delay time, input data gpmc_ad[15:0] capture from internalfunctional clock GPMC_FCLK 50/
Delay time, output chip select gpmc_csn[x] generation from interna
functional clock GPMC_FCL 50/
Delay time, output address valid and address latch enablegpmc_advn_ale generation from internal functional clock
GPMC_FCLK 50/
Delay time, output lower-byte enable and command latch enablegpmc_be0n_cle generation from internal functional clock
GPMC_FCLK 50/
Delay time, output enable gpmc_oen generation from internalfunctional clock GPMC_FCLK 50/
Delay time, output write enable gpmc_wen generation from internalfunctional clock GPMC_FCLK 50/
Skew, functional clock GPMC_FCLK 50/

6.5

6.5

ns

4.0

4.0

ns

6.5

6.5

ns

6.5

6.5

ns

6.5

6.5

ns

6.5

6.5

ns

6.5

6.5

ns

100

100

ps

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

V62/15602

REV

PAGE

35

TABLE I. Electrical performance characteristics - Continued. 1/ 2/
No

Test

SymbolLimits
OPP100Min

IMax

Peripheral Information and Timings – Continued

Unit
OPP50

I
I

Min

I

Max

External Memory Interfaces –General-Purpose Memory Controller (GPMC)

GPMC and NAND Flash—Asynchronous Mode
GPMC and NAND Flash Timing Requirements—Asynchronous Mode (See Figure 44 through 47)
GNF12
66/

Access time, input data gpmc_ad[15:0]

tacc(d)

I

J 67/

-

I

I

GPMC and NAND Flash Switching Characteristics— Asynchronous Mode (See Figure 44 through 47)

J 67/

-

I

ns

Rise time, output data gpmc_ad[15:0]

tR(d)

2

2

ns

Fall time, output data gpmc_ad[15:0]

tF(d)

2

2

ns

GNF0

Pulse duration, output write enable gpmc_wen valid

GNF1

Delay time, output chip select gpmc_csn[x] 80/
valid to output write enable gpmc_wen validtd(csnV-wenV)

tw(wenV)B – 0.2
69/

B + 2.0
69/

B–5
69/

B+5
69/

ns

GNF2

Delay time, output lower-byte enable and commandlatch enable gpmc_be0n_cle high to output write
enable gpmc_wen validtw(cleH-wenV)C – 0.2
70/

C + 2.0
70/

C–5
70/

C+5
70/

ns

GNF3

Delay time, output data gpmc_ad[15:0] valid to
output write enable gpmc_wen valid

tw(wenV-dV)

D – 0.2
71/

D + 2.0
71/

D–5
71/

D+5
71/

ns

GNF4

Delay time, output write enable gpmc_wen Delaytime, output write enable gpmc_wen

tw(wenIV-dIV)

E – 0.2
72/

E + 2.0
72/

E–5
72/

E+5
72/

ns

GNF5

Delay time, output write enable gpmc_wen invalid to
output lower-byte enable and command latch enablegpmc_be0n_cle invalid

tw(wenIV-cleIV)F – 0.2
73/

F + 2.0
73/

F–5
73/

F+5
73/

ns

GNF6

Delay time, output write enable gpmc_wen invalid to
output chip select gpmc_csn[x] 80/ invalid

tw(wenIV-csnIV)

G – 0.2
74/

G + 2.0
74/

G–5
74/

G+5
74/

ns

GNF7

Delay time, output address valid and address latch
enable gpmc_advn_ale high to output write enablegpmc_wen validtw(aleH-wenV)C – 0.2
70/

C + 2.0
70/

C–5
70/

C+5
70/

ns

GNF8

Delay time, output write enable gpmc_we invalid to
output address valid and address latchenablegpmc_advn_ale invalid

tw(wenIV-aleIV)F – 0.2
73/

F + 2.0
73/

F–5
73/

F+5
73/

ns

GNF9

Cycle time, write

GNF10

Delay time, output chip select gpmc_csn[x] 80/
valid to output enable gpmc_oen validtd(csnV-oenV)

GNF13

Pulse duration, output enable gpmc_oen validtw(oenV)

GNF14

Cycle time, read

GNF15

Delay time, output enable gpmc_oen invalid to
output chip select gpmc_csn[x] 80/ invalidA

68/

tc(wen)

A

68/

H 75/
I – 0.2
76/

I + 2.0
76/

H 75/
I–5
76/

K 77/

tc(oen)L 78/

tw(oenIV-csnIV)

M– 0.2
79/

ns

I+5
76/

ns

K 77/

ns

L 78/
M + 2.0
79/

M–5
79/

ns
M+5
79/

ns

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

V62/15602

REV

PAGE

36

TABLE I. Electrical performance characteristics - Continued. 1/ 2/
No

Test

Limits
Min

Unit

Typ

Max

Peripheral Information and Timings – Continued

External Memory Interfaces – mDDR(LPDDR), DDR2, DDR3, DDR3L Memory Interface

mDDR (LPDDR) Routing Guidelines
Switching Characteristics for LPDDR Memory Interface (See Figure 48)
1tc(DDR_CK)
tc(DDR_CKn)

Cycle time, DDR_CK and DDR_CKn

5

Compatible JEDEC LPDDR Devices (Per Interface) 81/
1
JEDEC LPDDR device speed grade
2
2 JEDEC LPDDR device bit width
3
JEDEC LPDDR device count
4
JEDEC LPDDR device terminal count
PCB Stackup Specifications 82/
1
PCB routing and plane layers

LPDDR400
X16

I

I

148/

ns

X16
1
60

Bits
Devices
Terminals

42

Signal routing layers

2

3

Full ground layers under LPDDR routing region

1

4

Number of ground plane cuts allowed within LPDDR routing region

5

Full VDDS_DDR power reference layers under LPDDR routing region

6

Number of layers between LPDDR routing layer and reference ground
plane

7

PCB routing feature size

4

mils

8

PCB trace width, w

4

mils

0
1
0

9

PCB BGA escape via pad size 83/

18

10

PCB BGA escape via hole size 83/1011Single-ended impedance, Zo 84/

50

75

Ω

12

Impedance control 85/ 86/

Zo

Zo + 5Ω

Zo - 5

20

mils
mils

Placement Specifications (See Figure 49) 87/
1

X 88/ 89/

1750

mils

2

Y 88/ 89/

1280

mils

650

mils

4

Clearance from non-LPDDR signal to LPDDR keepout region- -_88/ 89/ 90/
3 I Y Offset
91/ 92/

4

Bulk Bypass Capacitor 93/

I

I

I

w

1

AM3358-EP VDDS_DDR bulk bypass capacitor count

1

2

AM3358-EP VDDS_DDR bulk bypass total capacitance

10

μF

3

DDR#1 bulk bypass capacitor count1

Devices

4

LPDDR#1 bulk bypass total capacitance

10

μF

5

LPDDR#2 bulk bypass capacitor count 94/

1

Devices6

LPDDR#2 bulk bypass total capacitance 94/

10μF

Devices

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

V62/15602

REV

PAGE

37

TABLE I. Electrical performance characteristics - Continued. 1/ 2/
No

Test

Limits
Min

Typ

Unit
Max

Peripheral Information and Timings – Continued

External Memory Interfaces – mDDR(LPDDR), DDR2, DDR3, DDR3L Memory Interface
mDDR (LPDDR) Routing Guidelines

High-Speed Bypass Capacitors
1

HS bypass capacitor package size 95/

0402

2

Distance from HS bypass capacitor to device being bypassed

3

Number of connection vias for each HS bypass capacitor 96/

4

Trace length from bypass capacitor contact to connection via

5

Number of connection vias for each AM3358-EP VDDS_DDR and VSS terminal

6

Trace length from AM3358-EP VDDS_DDR and VSS terminal to connection via

7

Number of connection vias for each LPDDR device power and ground terminal

8

Trace length from LPDDR device power and ground terminal to connection via

9AM3358-EP VDDS_DDR HS bypass capacitor count 97/

10

10AM3358-EP VDDS_DDR HS bypass capacitor total capacitance

0.6

µF

11

LPDDR device HS bypass capacitor count8

Devices

12

LPDDR device HS bypass capacitor total capacitance

0.4

µF

250
2
30
35

1

CK net class 99/

2

ADDR_CTRL net class 99/

3

22

102/

0

22

DQS0, DQS1, DQ0, and DQ1 net classes

0

22

CK and ADDR_CTRL Routing Specification 103/ 104/

mils
Devices

0
101/

mils
Vias

35

LPDDR Signal Terminations

mils
Vias

1

98/

mils
Vias

1

97/ 98/10 mils(See Figure 50)

I -I
Zo 100/Ω

Zo 100/Ω

Zo 100/Ω

1Center-to-center CK spacing

2

CK differential pair skew length mismatch 104/ 105/

25

mils

3

CK B-to-CK C skew length mismatch

25

mils

CACLM+50
100

mils

100

mils

2w

4

Center-to-center CK to other LPDDR trace spacing 106/

5

CK and ADDR_CTRL nominal trace length 107/

6

ADDR_CTRL-to-CK skew length mismatch

7

ADDR_CTRL-to-ADDR_CTRL skew length mismatch

8

Center-to-center ADDR_CTRL to other LPDDR trace spacing 106/

4w

9Center-to-center ADDR_CTRL to other ADDR_CTRL trace spacing 106/

3w

4w
CACLM 50

CACLM

mils

10

ADDR_CTRL A-to-B and ADDR_CTRL A-to-C skew length mismatch 104/

100

mils

11

ADDR_CTRL B-to-C skew length mismatch

100

mils

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

V62/15602

REV

PAGE

38

TABLE I. Electrical performance characteristics - Continued. 1/ 2/
No

Test

Limits
Min

Typ

Unit
Max

Peripheral Information and Timings – Continued

External Memory Interfaces – mDDR(LPDDR), DDR2, DDR3, DDR3L Memory Interface

mDDR (LPDDR) Routing Guidelines
DQS[x] and DQ[x] Routing Specification 108/ (See Figure 51)1
2
3

Center-to-center DQS[x] spacing
Center-to-center DDR_DQS[x] to other LPDDR trace spacing
DQS[x] and DQ[x] nominal trace length 110/

4
5
6
7

DQ[x]-to-DQS[x] skew length mismatch 110/
DQ[x]-to-DQ[x] skew length mismatch 110/
Center-to-center DQ[x] to other LPDDR trace spacing 109/ 111/
Center-to-center DQ[x] to other DQ[x] trace spacing 109/ 112/

109/

2w

4w
DQLM –
50

DQLM 50

mils

100
100

mils
mils

4w
3w

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

V62/15602

REV

PAGE

39

TABLE I. Electrical performance characteristics - Continued. 1/ 2/
No

Test

Limits
Min

Unit

Typ

Max

Peripheral Information and Timings – Continued

External Memory Interfaces – mDDR(LPDDR), DDR2, DDR3, DDR3L Memory Interface

DDR2 Routing Guidelines
Switching Characteristics for DDR2 Memory Interface (See Figure 52)
1

Cycle time, DDR_CK and DDR_CKn tc(DDR_CK) tc(DDR_CKn)

Compatible JEDEC DDR2 Devices (Per Interface)
12
3
4

8 113/

ns

X16
2
84

bits
devicesterminals

114/

JEDEC DDR2 device speed grade 115/JEDEC DDR2 device bit width
JEDEC DDR2 device count
JEDEC DDR2 device terminal count 116/

DDR2-533x8
1

IPCB Stackup Specifications 117/

60

I

I

1

PCB routing and plane layers

4

2

Signal routing layers

2

3

Full ground layers under DDR2 routing region

1

4

Number of ground plane cuts allowed within DDR2 routing region

5

Full VDDS_DDR power reference layers under DDR2 routing region

6

Number of layers between DDR2 routing layer and reference ground plane

7

PCB routing feature size

8

PCB trace width, w

4

9

PCB BGA escape via pad size 118/18

10PCB BGA escape via hole size 118/

10

11Single-ended impedance, Zo

50

75

Ω

12

Impedance control

Zo

Zo + 5

Ω

1750

mils

1280

mils

650

mils

0
1
0
4

119/

120/ 121/

Zo - 5

mils
mils
20

mils
mils

Placement Specifications 122/ (See Figure 53)
1

X

2

Y

123/ 124/3

123/ 124/I Y Offset-123/ 124/ 125/

4

Clearance from non-DDR2 signal to DDR2 keepout region

Bulk Bypass Capacitors 128/__

126/ 127/

I

4

I

I

I

w

1

AM3358-EP VDDS_DDR bulk bypass capacitor count

1

2

AM3358-EP VDDS_DDR bulk bypass total capacitance

10

μF

3

DDR2 number 1 bulk bypass capacitor count1

Devices

4

DDR2 number 1 bulk bypass total capacitance5

DDR2 number 2 bulk bypass capacitor count

6

DDR2 number 2 bulk bypass total capacitance

129/
129/

Devices10μF

1Devices10μF

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

V62/15602

REV

PAGE

40

TABLE I. Electrical performance characteristics - Continued. 1/ 2/
No

Test

Limits
Min

Typ

Unit
Max

Peripheral Information and Timings – Continued

External Memory Interfaces – mDDR(LPDDR), DDR2, DDR3, DDR3L Memory Interface
DDR2 Routing Guideline

HS Bypass Capacitors
1

HS bypass capacitor package size 130/

0402

2

Distance from HS bypass capacitor to device being bypassed

3

Number of connection vias for each HS bypass capacitor 131/

4

Trace length from bypass capacitor contact to connection via

5

Number of connection vias for each AM3358-EP VDDS_DDR and VSS terminal

6

Trace length from AM3358-EP VDDS_DDR and VSS terminal to connection via

7

Number of connection vias for each DDR2 device power and ground terminal

8

Trace length from DDR2 device power and ground terminal to connection via

9AM3358-EP VDDS_DDR HS bypass capacitor count10

AM3358-EP VDDS_DDR HS bypass capacitor total capacitance

0.6

µF

11

DDR2 device HS bypass capacitor count8

Devices12

DDR2 device HS bypass capacitor total capacitance 133/

0.4

µF

250
2
30
35
35

1

CK net class 134/

2

ADDR_CTRL net class 134/ 135/ 136/

03

DQS0, DQS1, DQ0, and DQ1 net classes 138/

N/A

22

1

CK net class 134/

0

22

2

ADDR_CTRL net class 134/ 135/ 136/

0

22

3

DQS0, DQS1, DQ0, and DQ1 net classes

0

22

CK and ADDR_CTRL Routing Specification 139/ 140/

mils
Devices0

Lower-Frequency DDR2 Signal Terminations

mils
Vias

10

DDR2 Signal Terminations

mils
Vias

1

132/ 133/

mils
Vias

1

132/

10 mils(See Figure 54)

I -I
I -I
10

Ω

Zo 137/Ω

N/AΩ

Zo 137/Ω

Zo 137/Ω

Zo 137/Ω

1

Center-to-center CK spacing

2

CK differential pair skew length mismatch 140/ 141/

25

mils

3

CK B-to-CK C skew length mismatch

25

mils

CACLM+50
100

mils

100

mils

2w

4

Center-to-center CK to other DDR2 trace spacing 142/

5

CK and ADDR_CTRL nominal trace length 143/

6

ADDR_CTRL-to-CK skew length mismatch

7

ADDR_CTRL-to-ADDR_CTRL skew length mismatch

8

Center-to-center ADDR_CTRL to other DDR2 trace spacing 142/

4w

9

Center-to-center ADDR_CTRL to other ADDR_CTRL trace spacing 142/

3w

10

ADDR_CTRL A-to-B and ADDR_CTRL A-to-C skew length mismatch 140/

100

mils

11

ADDR_CTRL B-to-C skew length mismatch

100

mils

4w
CACLM
- 50

CACLM

mils

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

V62/15602

REV

PAGE

41

TABLE I. Electrical performance characteristics - Continued. 1/ 2/
No

Test

Limits
Min

Typ

Unit
Max

Peripheral Information and Timings – Continued

External Memory Interfaces – mDDR(LPDDR), DDR2, DDR3, DDR3L Memory Interface

DDR2 Routing Guidelines
DQS[x] and DQ[x] Routing Specification 144/ (See Figure 55)
1
2
3
4
5
6
7
8

Center-to-center DQS[x] spacing
DQS[x] differential pair skew length mismatch 141/
Center-to-center DDR_DQS[x] to other LPDDR trace spacing 142/
DQS[x] and DQ[x] nominal trace length 145/
DQ[x]-to-DQS[x] skew length mismatch 145/
DQ[x]-to-DQ[x] skew length mismatch 145/
Center-to-center DQ[x] to other LPDDR trace spacing 142/ 146/
Center-to-center DQ[x] to other DQ[x] trace spacing 142/ 147/

4w
DQLM – 50

2w
25

mils

DQLM - 50
100
100

mils
mils
mils

4w
3w

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

V62/15602

REV

PAGE

42

TABLE I. Electrical performance characteristics - Continued. 1/ 2/
No

Test

Limits
Min

Unit

Typ

Max

Peripheral Information and Timings – Continued

External Memory Interfaces – mDDR(LPDDR), DDR2, DDR3, DDR3L Memory Interface

DDR3 and DDR3L Routing Guidelines
Switching Characteristics for DDR3 Memory Interface (See fFgure 56)
1tc(DDR_CK)Cycle time, DDR_CK and DDR_CKn
tc(DDR_CKn)
Compatible JEDEC DDR3 Devices (Per Interface)
1

JEDEC DDR3 device speed grade

2
3

JEDEC DDR3 device bit width
JEDEC DDR3 device count 150/

PCB Stackup Specifications

Test conditionstC(DDR_CK) and tC(DDR_CKn) = 3.3 ns
tC(DDR_CK) and tC(DDR_CKn)= 2.5 ns

2.5

3.3 149/ns

DDR3-800
DDR3-1600
X8
1

X16
2

bits
devices151/

1

PCB routing and plane layers

4

2

Signal routing layers

2

3

Full ground layers under DDR3 routing region

4

Full VDDS_DDR power reference layers under DDR3 routing region 152/

5

Number of reference plane cuts allowed within DDR3 routing region 153/

0

6

Number of layers between DDR3 routing layer and reference plane 154/

0

7

PCB routing feature size

4

mils

8

PCB trace width, w

4

mils

152/

1
1

9

PCB BGA escape via pad size 155/

18

10PCB BGA escape via hole size /1011Single-ended impedance, Zo 156/12

Impedance control 157/ 158/

Placement Specifications 159/
1

X

2

Y

160/ 161/ 162/

Zo - 5

20

mils

50

75

Ω

Zo

Zo + 5

Ω

1000

mils

600

mils

1500

mils

(See Figure 57)

3160/ 161/I Y Offset-160/ 161/ 162/

4

Clearance from non-LPDDR signal to DDR3 keepout region_ _163/ 164/

I

4

mils

I

I

I

w

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

V62/15602

REV

PAGE

43

TABLE I. Electrical performance characteristics - Continued. 1/ 2/
No

Test

Limits
Min

Typ

Unit
Max

Peripheral Information and Timings – Continued

External Memory Interfaces – mDDR(LPDDR), DDR2, DDR3, DDR3L Memory Interface
Bulk Bypass Capacitors 165/

DDR3 and DDR3L Routing Guidelines

1

AM3358-EP VDDS_DDR bulk bypass capacitor count22

AM3358-EP VDDS_DDR bulk bypass total capacitance

20

μF

3

DDR3 number 1 bulk bypass capacitor count2

Devices4

DDR3 number 1 bulk bypass total capacitance

20

μF

5

DDR3 number 2 bulk bypass capacitor count 166/

2

Devices6

DDR3 number 2 bulk bypass total capacitance 166/

20μF

High-Speed Bypass Capacitor

Devices1

HS bypass capacitor package size 167/

2

Distance, HS bypass capacitor to AM3358-EP VDDS_DDR and VSS
terminal being bypassed 168/ 169/ 170/

3

AM3358-EP VDDS_DDR HS bypass capacitor count

20

4AM3358-EP VDDS_DDR HS bypass capacitor total capacitance1

5

Trace length from AM3358-EP VDDS_DDR and VSS terminal to connection
via 168/

6

Distance, HS bypass capacitor to DDR3 device being bypassed 171/

7

DDR3 device HS bypass capacitor count 172/

12

Devices8

DDR3 device HS bypass capacitor total capacitance 172/

0.85

μF

9

Number of connection vias for each HS bypass capacitor 173/ 174/

10

Trace length from bypass capacitor connect to connection via 168/ 174/
Number of connection vias for each DDR3 device power and groundterminal 175/
Trace length from DDR3 device power and ground terminal to connection via
168/ 173/1112

CK and ADDR_CTRL Routing Specification

0201

176/ 177/

0402

10 mils400

mils
Devices
μF

35

70

mils

150

mils

2

vias
35

100

1

mils
vias

35

60

mils

2500

mils

178/

1

A1 + A2 length2

A1 + A2 skew

25

mils

3

A3 length

660

mils

4

A3 skew 179/

25

mils

5

A3 skew 180/

125

mils

6

AS length

100

mils

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

V62/15602

REV

PAGE

44

TABLE I. Electrical performance characteristics - Continued. 1/ 2/
No

Test

Limits
Min

Typ

Unit
Max

Peripheral Information and Timings – Continued

External Memory Interfaces – mDDR(LPDDR), DDR2, DDR3, DDR3L Memory Interface

DDR3 and DDR3L Routing Guidelines
CK and ADDR_CTRL Routing Specification - Continued 176/ 177/ 178/
7

AS skew

25

mils

8

AS+ and AS– length

70

mils

9

AS+ and AS– skew

5

mils

10

AT length 181/

500

mils

11

AT skew

182/

100

mils

12

AT skew

183/

13

CK and ADDR_CTRL nominal trace length

14

Center-to-center CK to other DDR3 trace spacing

15

Center-to-center ADDR_CTRL to other DDR3 trace spacing

185/

186/

4w

16

Center-to-center ADDR_CTRL to other ADDR_CTRL trace spacing

185/

3w

17

CK center-to-center spacing

18

CK spacing to other net

19

Rcp

188/

20

Rtt

188/

184/

5

mils

CACLM

CACLM+50

mils

Zo - 1Zo

Zo + 1Ω

Zo - 5Zo

Zo + 5Ωmils

CACLM-50
185/

4w

187/

185/

4w

189/

DQS[x] and DQ[x] Routing Specification

190/

191/

DQ0 nominal length 192/

193/

DQLM0

2

DQ1 nominal length 192/

194/

DQLM1

mils

3

DQ[x] skew 195/

25

mils

4

DQS[x] skew

5

mils

5

DQS[x]-to-DQ[x] skew 195/

25

mils

6

Center-to-center DQ[x] to other DDR3 trace spacing

197/

198/

4w

7

Center-to-center DQ[x] to other DQ[x] trace spacing 197/

199/

3w

8

DQS[x] center-to-center spacing 200/

9DQS[x] center-to-center spacing to other net 197/

1

196/

4w

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

V62/15602

REV

PAGE

45

TABLE I. Electrical performance characteristics - Continued. 1/ 2/
No

Test

SymbolLimitsSTANDARD MODE
Min
Max
I

I

Unit
FAST MODE
Min
Max

Peripheral Information and Timings – Continued

I2C - I2C Electrical Data and Timing
I C Timing Conditions – Slave Mode (See Figure 60)2Output Condition

Capacitive load for each bus line

400

Timing Requirements for I C Input Timings (See Figure 61)

400

pF

2

1

Cycle time, SCLtc(SCL)

10

2.5

µs

2

Setup time, SCL high before SDA low (for a repeated
START condition)tsu(SCLH-SDAL)

4.7

0.6

µs

3

Hold time, SCL low after SDA low (for a START anda repeated START condition)th(SDAL-SCLL)

4

0.6

µs

4

Pulse duration, SCL lowtw(SCLL)

4.7

1.3

µs

5

Pulse duration, SCL hightw(SCLH)

4

0.6

µs

6

Setup time, SDA valid before SCL hightsu(SDAV-SCLH)

250

100 201/µs

7

Hold time, SDA valid after SCL lowth(SCLL-SDAV)

0 202/

8

Pulse duration, SDA high between STOP and START
conditions

tw(SDAH)

4.7

9

Rise time, SDA

tr(SDA)

1000

300

ns

10

Rise time, SCL

tr(SCL)

1000

300

ns

11

Fall time, SDA

tf(SDA)

300

300

ns

12

Fall time, SCL

13

Setup time, high before SDA high (for STOP
condition)tsu(SCLH-SDAH)

4

14

Pulse duration, spike (must be suppressed)tw(SP)

03.45 203/

0 202/

0.9 203/1.3

300

tf(SCL)

300
0.6

50

0

µs
µs

ns
µs

50

ns

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

V62/15602

REV

PAGE

46

TABLE I. Electrical performance characteristics - Continued. 1/ 2/
No

Test

SymbolLimitsSTANDARD MODE
Min
Max

Unit
FAST MODE
Min
Max

Peripheral Information and Timings – Continued

I2C - I2C Electrical Data and Timing
Switching Characteristics for I C Output Timings (See Figure 61)215

Cycle time, SCL

16

18

Setup time, SCL high before SDA low (for arepeated ART condition)
Hold time, SCL low after SDA low (for a
START and a repeated START condition)
Pulse duration, SCL low

19

Pulse duration, SCL hightw(SCLH)

20

Setup time, SDA valid before SCL hightsu(SDAV-SCLH)

21

Hold time, SDA valid after SCL lowth(SCLL-SDAV)

0

22

tw(SDAH)

4.7

23

Pulse duration, SDA high between STOP and
START conditions
Rise time, SDA

tr(SDA)

1000

300

ns

24

Rise time, SCL

tr(SCL)

1000

300

ns

25

Fall time, SDA

tf(SDA)

300

300

ns

26

Fall time, SCL

tf(SCL)

300

300

ns

27

Setup time, high before SDA high (for STOP
condition)

17

tc(SCL)

10

2.5

µs

tsu(SCLH-SDAL)

4.7

0.6

µs

th(SDAL-SCLL)

4

0.6

µs

tw(SCLL)

4.7

1.3

µs

4

0.6

µs

250

100

µs

tsu(SCLH-SDAH)

3.45

0

0.9

1.3

4

µs
µs

0.6

µs

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

V62/15602

REV

PAGE

47

TABLE I. Electrical performance characteristics - Continued. 1/ 2/
No

Test

SymbolLimitsUnit

OPP100
Min

I

OPP50
Max

Min

I

Max

Peripheral Information and Timings – Continued
JTAG Electrical Data and Timing

Timing Requirements for JTAG (See Figure 62)
1

Cycle time, TCK

tc(TCK)

81.5

104.5

ns

1a

Pulse duration, TCK high (40% of tc)

tw(TCKH)

32.6

41.8

ns

1b

Pulse duration, TCK low (40% of tc)

tw(TCKL)

32.6

41.8

ns

3

Input setup time, TDI valid to TCK hightsu(TDI-TCKH)

3

3

ns

Input setup time, TMS valid to TCK hightsu(TMS-TCKH)

3

3

ns

Input hold time, TDI valid from TCK highth(TCKH-TDI)

8.05

8.05

ns

Input hold time, TMS valid from TCK highth(TCKH-TMS)

8.05

8.05

ns

4

Switching Characteristics for JTAG (See Figure 62)
2

Delay time, TCK low to TDO validtd(TCKL-TDO)

No

3

27.6

Test

4

Symbol36.8

Limits

ns

Unit

Min

Max

5
3

60
30

Peripheral Information and Timings – Continued
LCD Controller (LCDC)
LCD Interface Display Driver (LIDD Mode)LCD Controller Timing Conditions
Output Condition

LIDD mode
Raster mode

Output load capacitance

No

CLOAD

Test

Symbol

OPP100
Min

pF
pF
Unit

Max

Peripheral Information and Timings – Continued
7.10 LCD Controller (LCDC)
7.10.1 LCD Interface Display Driver (LIDD Mode)

Timing Requirements for LCD LIDD Mode
16

17
18

Setup time, LCD_DATA[15:0] valid before
LCD_MEMORY_CLK highHold time, LCD_DATA[15:0] valid after
LCD_MEMORY_CLK highTransition time, LCD_DATA[15:0](See Figure 64 through 72)

tsu(LCD_DATA-LCD_MEMORY_CLK)18

nsth(LCD_MEMORY_CLK-LCD_DATA)0nstt(LCD_DATA)

1

I

3

I ns

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

V62/15602

REV

PAGE

48

TABLE I. Electrical performance characteristics - Continued. 1/ 2/
No

Test

Symbol

OPP100
Min

Unit
Max

Peripheral Information and Timings – Continued
LCD Controller (LCDC)
LCD Interface Display Driver (LIDD Mode)

Switching Characteristics for LCD LIDD Mode

(See Figure 64 through figure 72)

1

Cycle time, LCD_MEMORY_CLK

2

Pulse duration, LCD_MEMORY_CLK hightc(LCD_MEMORY_CLK)

23.7

tw(LCD_MEMORY_CLKH)

0.45 tc

0.55tcns

3

Pulse duration, LCD_MEMORY_CLK low

4

Delay time, LCD_MEMORY_CLK high to LCD_DATA[15:0]
valid (write)

td(LCD_MEMORY_CLK-LCD_DATAV)tw(LCD_MEMORY_CLKL)

0.45 tc

0.55tc

ns

7

ns

5

Delay time, LCD_MEMORY_CLK high to LCD_DATA[15:0]
invalid (write)

td(LCD_MEMORY_CLK-LCD_DATAI)

0

6Delay time, LCD_MEMORY_CLK high to
LCD_AC_BIAS_EN

td(LCD_MEMORY_CLK-

0

6.8

ns

7

Transition time, LCD_AC_BIAS_EN

tt(LCD_AC_BIAS_EN)

1

10

ns

8

Delay time, LCD_MEMORY_CLK high to LCD_VSYNC

td(LCD_MEMORY_CLK-LCD_VSYNC)

0

7

ns

9

Transition time, LCD_VSYNC

tt(LCD_VSYNC)

1

10

ns

10

Delay time, LCD_MEMORY_CLK high to LCD_HSYNC

td(LCD_MEMORY_CLK-LCD_HYSNC)

0

7

ns

11

Transition time, LCD_HYSNC

tt(LCD_HSYNC)

1

10

ns

12

Delay time, LCD_MEMORY_CLK high to LCD_PCLK

td(LCD_MEMORY_CLK-LCD_PCLK)

0

7

ns

ns

ns

LCD_AC_BIAS_EN)

13

Transition time, LCD_PCLK

tt(LCD_PCLK)

1

10

ns

14

Delay time, LCD_MEMORY_CLK high to LCD_DATA[15:0]
high-Z

td(LCD_MEMORY_CLK-LCD_DATAZ)

0

7

ns

15

Delay time, LCD_MEMORY_CLK high to LCD_DATA[15:0]
driventd(LCD_MEMORY_CLK-LCD_DATA)

0

7

ns

19

Transition time, LCD_MEMORY_CLK

tt(LCD_MEMORY_CLK)

1

2.5

ns

20

Transition time, LCD_DATA

tt(LCD_DATA)

1

10

ns

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

V62/15602

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PAGE

49

TABLE I. Electrical performance characteristics - Continued. 1/ 2/
No

Test

SymbolLimits
OPP50

I Max IMin

Unit
OPP100Min
Max

Peripheral Information and Timings – Continued
LCD Controller (LCDC)LCD Raster Mode

Switching Characteristics for LCD Raster Mode

(See Figure 73 through figure 76)

1

Cycle time, pixel clocktc(LCD_PCLK)

15.8

ns

2

Pulse duration, pixel clock hightw(LCD_PCLKH)

0.45 tc

0.55tc0.45 tc

0.55tcns

3

Pulse duration, pixel clock low

tw(LCD_PCLKL)

0.45 tc

0.55tc0.45 tc

0.55tcns

4

Delay time, LCD_PCLK to
LCD_DATA[23:0] valid (write)

td(LCD_PCLK-LCD_DATAV)

1.9

ns

5

Delay time, LCD_PCLK to
LCD_DATA[23:0] invalid (write)

td(LCD_PCLK-LCD_DATAI)

-3.0

6

Delay time, LCD_PCLK to
LCD_AC_BIAS_EN

td(LCD_PCLK-

-3.0

3.0

tt(LCD_AC_BIAS_EN)

0.5

td(LCD_PCLK-LCD_VSYNC)

-3.0

7.9

3.0

ns

-1.7
-1.7

1.9

ns

2.4

0.5

2.4

ns

3.0

-1.7

1.9

ns

LCD_AC_BIAS_EN)

7

Transition time, LCD_AC_BIAS_EN

8

Delay time, LCD_PCLK to LCD_VSYNC

9Transition time, LCD_VSYNC

10

Delay time, LCD_PCLK to LCD_HSYNC

tt(LCD_VSYNC)

0.5

2.4

0.5

2.4

ns

td(LCD_PCLK-LCD_HSYNC)

-3.0

3.0

-1.7

1.9

ns

11
12

Transition time, LCD_HSYNC

tt(LCD_HSYNC)

0.5

2.4

0.5

2.4

ns

Transition time, LCD_PCLK

tt(LCD_PCLK)

0.5

2.4

0.5

2.4

ns

13

Transition time, LCD_DATA

tt(LCD_DATA)

0.5

2.4

0.5

2.4

ns

No

Test

SymbolLimits
Min

Unit

Typ

Max

Peripheral Information and Timings – Continued
McASP Timing Conditions

Multichannel Audio Serial Port (McASP)
McASP Electrical Data and Timing

Input Conditions

Input signal rise timetR

Input signal fall time

tF

204/
I 1 _
I

CLOAD

15

Output Condition
Output load capacitance

1

204/

4

204/

ns

30

pF

204/ I ns
I4 _See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

V62/15602

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PAGE

50

TABLE I. Electrical performance characteristics - Continued. 1/ 2/
No

Test

SymbolLimits
OPP100Min

IMax

Peripheral Information and Timings – Continued

I

Unit
OPP50
Min
Max

Multichannel Audio Serial Port (McASP)
McASP Electrical Data and Timing

Timing Requirements for McASP 205/ (See figure 78)
1
2
3
4

5

6

7

8

Cycle time, McASP[x]_AHCLKR and
McASP[x]_AHCLKX
Pulse duration, McASP[x]_AHCLKR and
McASP[x]_AHCLKX high or low
Cycle time, McASP[x]_ACLKR and
McASP[x]_ACLKX
Pulse duration, McASP[x]_ACLKR and
McASP[x]_ACLKX high or low
Setup time, McASP[x]_AFSR and
McASP[x]_AFSX input valid before
McASP[x]_ACLKR and
McASP[x]_ACLKX
Hold time, McASP[x]_AFSR and
McASP[x]_AFSX input valid after
McASP[x]_ACLKR and
McASP[x]_ACLKX
Setup time, McASP[x]_AXR input
valid before McASP[x]_ACLKR and
McASP[x]_ACLKX

Hold time, McASP[x]_AXR input
valid after McASP[x]_ACLKR and
McASP[x]_ACLKXACLKR andACLKX int
ACLKR andACLKX ext in
ACLKR andACLKX ext out
ACLKR andACLKX int
ACLKR andACLKX ext in
ACLKR andACLKX ext out
ACLKR andACLKX int
ACLKR andACLKX ext in
ACLKR andACLKX ext out
ACLKR andACLKX int
ACLKR andACLKX ext in
ACLKR andACLKX ext out

tc(AHCLKRX)

20

40

ns

tw(AHCLKRX)

0.5P – 2.5
206/
20

0.5P – 2.5
206/
40

ns

tw(ACLKRX)

0.5R – 2.5
207/
11.5

0.5R – 2.5
207/
15.5

ns

tsu(AFSRX- ACLKRX)

4

6

ns

4

6

-1

-1

0.4

0.4

0.4

0.4

11.5

15.5

4

6

4

6

-1

-1

0.4

0.4

0.4

0.4

tc(ACLKRX)th(ACLKRX- AFSRX)

tsu(AXR-ACLKRX)th(ACLKRX-AXR)

ns

ns

ns

ns

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

V62/15602

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PAGE

51

TABLE I. Electrical performance characteristics - Continued. 1/ 2/
No

Test

SymbolLimits
OPP100Min

IMax

Peripheral Information and Timings – Continued

I

Unit
OPP50
Min
Max

Multichannel Audio Serial Port (McASP)
McASP Electrical Data and Timing

Switching Characteristics for McASP 205/ (See figure 78)
9

10
11
12

13

14

15

Cycle time, McASP[x]_AHCLKR and
McASP[x]_AHCLKX
Pulse duration, McASP[x]_AHCLKR and
McASP[x]_AHCLKX high or low

Delay time, McASP[x]_ACLKR and
McASP[x]_ACLKX transmit edge to
McASP[x]_AFSR and
McASP[x]_AFSX output valid with Pad
Loopback
Delay time, McASP[x]_ACLKXtransmit edge to McASP[x]_AXR
output valid
Delay time, McASP[x]_ACLKXtransmit edge to McASP[x]_AXR
output valid with Pad Loopback
Disable time, McASP[x]_ACLKXtransmit edge to McASP[x]_AXR
output high impedance
Disable time, McASP[x]_ACLKXtransmit edge to McASP[x]_AXR
output high impedance with padloopback

20

40

ns

tw(AHCLKRX)

0.5P – 2.5
206/
20

0.5P – 2.5
206/
40

ns

0.5P – 2.5
207/
0

6

0.5P – 2.5
207/
0

6

2

13.5

2

18

2

13.5

2

18

0
2

6
13.5

0
2

6
18

2

13.5

2

18

0
2

6
13.5

0
2

6
18

2

13.5

2

18

tc(ACLKRX)

Cycle time, McASP[x]_ACLKR and
McASP[x]_ACLKX
Pulse duration, McASP[x]_ACLKR and
McASP[x]_ACLKX high or low
Delay time, McASP[x]_ACLKR and
McASP[x]_ACLKX transmit edge to
McASP[x]_AFSR and
McASP[x]_AFSX output validtc(AHCLKRX)

tw(ACLKRX)ACLKR andACLKX int
ACLKR andACLKX ext
in
ACLKR andACLKX ext
out
ACLKX in
ACLKX extin
ACLKX ext
out
ACLKX in
ACLKX extin
ACLKX extout

td(ACLKRX-AFSRX)

td(ACLKX-AXR)

tdis(ACLKX-AXR)

ns
ns

ns

ns

ns

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

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52

TABLE I. Electrical performance characteristics - Continued. 1/ 2/
No

Test

SymbolLimits

Unit

Min

Max

Peripheral Information and Timings – Continued
Multichannel Serial Port Interface (McSPI)McSPI Electrical Data and Timing

McSPI Timing Conditions – Slave Mode
Input Conditions

Input signal rise time
Input signal fall time
Output Condition20
Output load capacitance

No

Test

tr
tf

5
5

ns
ns

Cload

20

pF

SymbolLimitsUnit

OPP100
Min

OPP50
Max

Min

Max

Peripheral Information and Timings – Continued
Multichannel Serial Port Interface (McSPI)McSPI Electrical Data and Timing

Timing Requirements for McSPI Input Timings—Slave Mode (See Figure 79)
Cycle time, SPI_CLK

2

Typical pulse duration, SPI_CLK lowtc(SPICLK)tw(SPICLKL)

3

Typical pulse duration, SPI_CLK hightw(SPICLKH)

4

Setup time, SPI_D[x] (SIMO) valid before
SPI_CLK active edge 209/ 210/
Hold time, SPI_D[x] (SIMO) valid after SPI_CLK
active edge 209/ 210/

tsu(SIMO-SPICLK)

0.5P – 3.12
208/
0.5P – 3.12
208/
12.92

th(SPICLK-SIMO)

12.92

12.92

ns

8

Setup time, SPI_CS valid before SPI_CLK firstedge 209/

tsu(CS-SPICLK)

12.92

12.92

ns

9

Hold time, SPI_CS valid after SPI_CLK last
edge
209/

th(SPICLK-CS)

12.92

12.92

ns

5

62.5

ns

1

Switching Characteristics for McSPI Output Timings—Slave Mode
6

Delay time, SPI_CLK active edge to SPI_D[x](SOMI) transition 209/ 210/td(SPICLK-SOMI)

7

Delay time, SPI_CS active edge to SPI_D[x](SOMI) transition 209/ 210/td(CS-SOMI)

-4.00

124.8

0.5P + 3.12
208/
0.5P + 3.12
208/

(See figure 80)
17.12

0.5P – 3.12
208/
0.5P – 3.12
208/
12.92

-4.00

17.12

0.5P + 3.12
208/
0.5P + 3.12
208/

ns
ns
ns

17.12

ns

17.12

ns

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

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PAGE

53

TABLE I. Electrical performance characteristics - Continued. 1/ 2/
No

Test

LOW LOAD

SymbolMin

HIGH LOAD

Max

Min

Unit
Max

Peripheral Information and Timings – Continued
Multichannel Serial Port Interface (McSPI)McSPI Electrical Data and Timing

McSPI Timing Conditions – Master Mode
Input Conditions

Input signal rise time
Input signal fall time
Output Condition20
Output load capacitance

DLA LAND AND MARITIMECOLUMBUS, OHIO

tr
tf

8
8

8
8

ns
ns

Cload

5

25

pF

SIZE
A

CODE IDENT NO.
16236

DWG NO.

V62/15602

REV

PAGE

54

TABLE I. Electrical performance characteristics - Continued. 1/ 2/
No

Test

SymbolLimits
OPP100LOW LOAD

LOW LOAD

I I
Peripheral Information and Timings – Continued
Min

Unit

OPP50
HIGH LOAD

I Max I Min

Max

Min

Max

HIGH LOAD

I

Min

Max

Multichannel Serial Port Interface (McSPI)McSPI Electrical Data and Timing

Timing Requirements for McSPI Input Timings— Master Mode (See Figure 81)
45

Setup time, SPI_D[x](SOMI) valid before
SPI_CLK active edge
Hold time, SPI_D[x](SOMI) valid after
SPI_CLK active edgetsu(SOMI-

2.29

3.02

2.29

3.02

ns

7.25

7.25

7.7

7.7

ns

41.6

ns

SPICLKH)

th(SPICLKHSOMI)

Switching Characteristics for McSPI Output Timings—Master Mode
1

Cycle time, SPI_CLKtc(SPICLK)

2

Typical pulse duration,
SPI_CLK lowtw(SPICLKL)

Typical pulse duration,
SPI_CLK hightw(SPICLKH)

Rising time, SPI_CLKtr(SPICLK)

0.5P –
0.5P – 0.5P – 2.08
1.04 208/ 1.04
208/
208/
0.5P –
0.5P – 0.5P – 2.08
1.04 208/ 1.04
208/
208/
3.82

Falling time, SPI_CLK

tf(SPICLK)

3.44

Delay time, SPI_CLK
active edge to SPI_D[x](SIMO) transition 211/

td(SPICLK-Delay time, SPI_CS
active edge to SPI_D[x](SIMO) ransition 211/

td(CS-SIMO)

3

6
7

8

Delay time,
SPI_CS
active to
SPI_CLK
first edge

9

Delay time,
SPI_CLK
last edge
to SPI_CS
nactive

Mode 1
and 3
212/

SIMO)

td(CS-

Mode 0
and 2
212/

-3.57

20.8

3.57

41.6

0.5P –
0.5P –
0.5P –
0.5P –
0.5P –
ns
2.08 208/ 1.04 208/ 1.04 208/ 2.08 208/ 2.08 208/
0.5P –
0.5P –
0.5P –
0.5P –
0.5P –
ns
2.08 208/ 1.04 208/ 1.04 208/ 2.08 208/ 2.08 208/

-4.62

3.82

3.82

3.82

ns

3.44

3.44

3.44

ns

4.62

ns

4.62

ns

4.62

3.57

-3.57

4.62

3.57

-4.62

3.57

A – 4.2
213/

A – 2.54
213/

A – 4.2
213/

A – 2.54
213/

ns

B – 4.2
214/
B – 4.2
214/

B – 2.54
214/
B – 2.54
214/

B – 4.2
214/
B – 4.2
214/

B – 2.54
214/
B – 2.54
214/

ns

A – 4.2
213/

A – 2.54
213/

A – 4.2
213/

A – 2.54
213/

SPICLK)

Mode 0and 2 212/
Mode 1
and 3
212/

20.8

(See Figure 82)

td(SPICLK-

ns

CS)

ns

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

V62/15602

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PAGE

55

TABLE I. Electrical performance characteristics - Continued. 1/ 2/
No

Test

SymbolLimits
Min

Typ

Unit
Max

Peripheral Information and Timings – Continued
Multimedia Card (MMC) Interface
MMC Electrical Data and Timing

MMC Timing Conditions
Input Conditions

Input signal rise time
Input signal fall time

tr
tf

1
1

5
5

ns
ns

Cload

3

30

pF

Output Condition

Output load capacitanceTiming Requirements for MMC[x]_CMD and MMC[x]_DAT[7:0] (See Figure 83)
12
34

Setup time, MMC_CMD valid before MMC_CLK rising clock edge
Hold time, MMC_CMD valid after MMC_CLK rising clock edge
Setup time, MMC_DATx valid before MMC_CLK rising clock edge
Hold time, MMC_DATx valid after MMC_CLK rising clock edge

No

Test

tsu(CMDV-CLKH)th(CLKH-CMDV)
tsu(DATV-CLKH)th(CLKH-DATV)

4.1
3.76
4.1
3.76

SymbolLimitsSTANDARD MODE

Min
Switching Characteristics for MMC[x]_CLK (See Figure 84)
Operating frequency, MMC_CLK
ƒop(CLK)
5
Operating period: MMC_CLK
tcop(CLK)
Identification mode frequency, MMC_CLK
fid(CLK)
Identification mode period: MMC_CLK
tcid(CLK)
6
Pulse duration, MMC_CLK lowtw(CLKL)
7

Pulse duration, MMC_CLK hightw(CLKH)

8
9Rise time, all signals (10% to 90%)
Fall time, all signals (10% to 90%)8 tr(CLK)
tf(CLK)

ns
ns
ns
ns

Max

Unit
HIGH-SPEED MODE

Min

24
41.7

Max
48

20.8
400

2500
(0.5 × P) –tf(CLK) 215/(0.5 × P) –tf(CLK) 215/

400
2500
(0.5 × P) –tf(CLK) 215/(0.5 × P) –tf(CLK) 215/

2.2
2.2

MHz
ns
kHz
ns
ns
ns

2.2
2.2

ns
ns

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

V62/15602

REV

PAGE

56

TABLE I. Electrical performance characteristics - Continued. 1/ 2/
No

Test

SymbolLimitsUnit

OPP100
Min

OPP50
Max

Min

Max

Peripheral Information and Timings – Continued
Multimedia Card (MMC) Interface
MMC Electrical Data and Timing

Switching Characteristics for MMC[x]_CMD and MMC[x]_DAT[7:0] – Standard Mode (See Figure 85)
1011Delay time, MMC_CLK falling clock edge to
MMC_CMD transition
Delay time, MMC_CLK falling clock edge to
MMC_DATx transitiontd(CLKL-CMD)

-4

14

-4

17.5

ns

td(CLKL-DAT)

-4

14

-4

17.5

ns

Switching Characteristics for MMC[x]_CMD and MMC[x]_DAT[7:0]—High-Speed Mode
12

13

Delay time, MMC_CLK rising clock edge to
MMC_CMD transition
Delay time, MMC_CLK rising clock edge to
MMC_DATx transition

No

Test

td(CLKL-CMD)

2.5

14

td(CLKL-DAT)

2.5

14

Symbol(See Figure 86)
2.5

17.5

ns

2.5

17.5

ns

Limits
Min

Typ

Unit
Max

Peripheral Information and Timings – Continued

Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)
Programmable Real-Time Unit (PRU-ICSS PRU)
PRU-ICSS PRU Timing Conditions
Output Condition

Capacitive load for each bus line

Cload

30

pF

3.9
3.0
1.0
3.0

ns
ns
ns
ns
ns

3.9
3.0
1.0
5.0

ns
ns
ns
ns
ns

PRU-ICSS PRU Timing Requirements - Direct Input Mode (See Figure 87)12
3

Pulse width, GPI
Rise time, GPI
Fall time, GPI
Internal skew between GPI[n:0] signals-217/

I PRU0I PRU1tw(GPI)
tr(GPI)
tf(GPI)
tsk(GPI)

2 × P 216/
1.0
1.0

PRU-ICSS PRU Switching Requirements – Direct Output Mode (See Figure 88)
1
Pulse width, GPI
tw(GPO)
2 × P 216/
2
Rise time, GPI
tr(GPO)
1.0
Fall time, GPI
tf(GPO)
1.0
3
Internal skew between GPI[n:0] signals
PRU0tsk(GPO)II PRU1-218/
See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

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ACODE IDENT NO.
16236

DWG NO.

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57

TABLE I. Electrical performance characteristics - Continued. 1/ 2/
No

Test

SymbolLimits
Min

Unit
Max

Peripheral Information and Timings – Continued

Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)PRU-ICSS PRU Parallel Capture Mode Electrical Data and Timing
PRU-ICSS PRU Timing Requirements - Parallel Capture Mode (See Figure 89 and Figure 90)
1
2
3
4
5
6
7
8

Cycle time, CLOCKIN
Pulse duration, CLOCKIN low
Pulse duration, CLOCKIN highRising time, CLOCKIN
Falling time, CLOCKIN
Setup time, DATAIN valid before CLOCKIN
Hold time, DATAIN valid after CLOCK
Rising time, DATAIN
Falling time, DATAIN

tc(CLOCKIN)
tw(CLOCKIN_L)
tw(CLOCKIN_H)
tr(CLOCKIN)
tf(CLOCKIN)

20.00
10.00
10.00
1.00
1.00
5.00
0.00
1.00
1.00

tsu(DATAIN-CLOCKIN)
th(CLOCKIN-DATAIN)
tr(DATAIN)
tf(DATAIN)

3.00
3.00

ns
ns
ns
ns
ns
ns
ns
ns
ns

10.00
0.45 × P 216/
1.00
1.00

0.55 × P 216/
3.00
3.00

ns
ns
ns
ns

10.00
0.45 × P 216/
1.00
1.00
0.00
1.00
1.00

0.55 × P 216/
3.00
3.00
3.00
3.00
3.00

ns
ns
ns
ns
ns
ns
ns

3.00
3.00

7.14.1.3 PRU-ICSS PRU Shift Mode Electrical Data and Timing
PRU-ICSS PRU Timing Requirements – Shift In Mode (See Figure 91)12
34Cycle time, DATAIN
Pulse width, DATAIN
Rising time, DATAIN
Falling time, DATAIN

tc(DATAIN)
tw(DATAIN)
tr(DATAIN)
tf(DATAIN)

PRU-ICSS PRU Switching Requirements - Shift Out Mode (See Figure 92)
1
2
3
4
5
6

Cycle time, CLOCKOUT
Pulse width, CLOCKOUT
Rising time, CLOCKOUT
Falling time, CLOCKOUT
Delay time, CLOCKOUT to DATAOUT valid
Rising time, DATAOUT
Falling time, DATAOUT

tc(CLOCKOUT)
tw(CLOCKOUT)
tr(CLOCKOUT)
tf(CLOCKOUT)

td(CLOCKOUT-DATAOUT)
tr(DATAOUT)
tf(DATAOUT)

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

V62/15602

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58

TABLE I. Electrical performance characteristics - Continued. 1/ 2/
No

Test

SymbolLimits
Min

Unit

Typ

Max

Peripheral Information and Timings – Continued

Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem(PRU-ICSS)PRU-ICSS MII_RT and Switch

PRU-ICSS MII_RT Switch Timing Conditions
Input Conditions
Input signal rise timetR

Input signal fall timetF

I 1 -218/ I

CLOAD

3

1 218/

3 218/

ns

20

pF

I 3 -218/ I ns

Output Condition
Output load capacitance

7.14.2.1 PRU-ICSS MDIO Electrical Data and Timing
PRU-ICSS MDIO Timing Requirements – MDIO_DATA (See Figure 93)
1

Setup time, MDIO valid before MDC high2

Hold time, MDIO valid from MDC highPRU-ICSS MDIO Switching Characteristics - MDIO_CLK
1
2
3
4

Cycle time, MDC
Pulse duration, MDC highPulse duration, MDC low
Transition time, MDC

PRU-ICSS MDIO Switching Characteristics – MDIO_DATA
1

No

Delay time, MDC high to MDIO validTesttsu(MDIO-MDC)

90

nsth(MDIO-MDC)

0

ns

400
160
160

ns
ns
ns
ns

(See Figure 94)
tc(MDC)
tw(MDCH)
tw(MDCL)tt(MDC)(See Figure 95)

td(MDC-MDIO)

I

10

I

5
390

ns

LimitsSymbol
10 Mbps
Min

Max

Unit
100 Mbps
Min
Max

Peripheral Information and Timings – Continued

Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem(PRU-ICSS)PRU-ICSS MII_RT and Switch

PRU-ICSS MII_RT Electrical Data and Timing
PRU-ICSS MII_RT Timing Requirements – MII_RXCLK (See Figure 96)12
34Cycle time, RX_CLK
Pulse duration, RX_CLK highPulse duration, RX_CLK low
Transition time, RX_CLKtc(RX_CLK)
tw(RX_CLKH)
tw(RX_CLKL)
tt(RX_CLK)

399.96140140400.04260
260
339.99614
14

I

40.004
26
26
3

I

ns
ns
ns
ns

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

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DWG NO.

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TABLE I. Electrical performance characteristics - Continued. 1/ 2/
No

Test

SymbolLimits
10 Mbps
Min
Max

Unit
100 Mbps
Min
Max

Peripheral Information and Timings – Continued

Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem(PRU-ICSS)PRU-ICSS MII_RT and Switch

PRU-ICSS MII_RT Electrical Data and Timing
PRU-ICSS MII_RT Timing Requirements – MII[x]_TXCLK (See Figure 97)12
34Cycle time, TX_CLK
Pulse duration, TX_CLK highPulse duration, TX_CLK low
Transition time, TX_CLKtc(TX_CLK)
tw(TX_CLKH)
tw(TX_CLKL)
tt(TX_CLK)I

399.96140140I400.04
260
260
3

I

39.99614
14

I

40.004
26
26
3

ns
ns
ns
ns

PRU-ICSS MII_RT Timing Requirements - MII_RXD[3:0], MII_RXDV, and MII_RXER (See Figure 98)
12

Setup time, RXD[3:0] valid before RX_CLK
Setup time, RX_DV valid before RX_CLK
Setup time, RX_ER valid before RX_CLK
Hold time RXD[3:0] valid after RX_CLK
Hold time RX_DV valid after RX_CLK
Hold time RX_ER valid after RX_CLK

tsu(RXD-RX_CLK)
tsu(RX_DV-RX_CLK)
tsu(RX_ER-RX_CLK)th(RX_CLK-RXD)th(RX_CLK-RX_DV)th(RX_CLK-RX_ER)

8

8

ns

8

8

ns

RU-ICSS MII_RT Switching Characteristics - MII_TXD[3:0] and MII_TXEN
1

Delay time, TX_CLK high to TXD[3:0] valid
Delay time, TX_CLK to TX_EN validNo

td(TX_CLK-TXD)

5(See Figure 99)
25

5

25

ns

td(TX_CLK-TX_EN)

Test

SymbolLimits
Min

Unit
Max

Peripheral Information and Timings – Continued

Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem(PRU-ICSS)PRU-ICSS Universal Asynchronous Receiver Transmitter (PRU-ICSS UART)

Timing Requirements for PRU-ICSS UART Receive
3

Pulse duration, receive start, stop, data bit

1

Maximum programmable baud rate

2

Pulse duration, transmit start, stop, data bit(See Figure 100)tw(RX)

0.96U 220/

1.05U 220/nsƒbaud(baud)

0

12

MHz

tw(TX)

U – 2 220/

Switching Characteristics Over Recommended Operating Conditions for PRU-ICSS UART Transmit
U+2

220/

ns

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

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DWG NO.

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TABLE I. Electrical performance characteristics - Continued. 1/ 2/
No

Test

SymbolLimits
Min

Unit
Max

Peripheral Information and Timings – Continued

Universal Asynchronous Receiver Transmitter (UART)
UART Electrical Data and Timing

Timing Requirements for UARTx
3(See Figure 101)

Pulse duration, receive start, stop, data bit

Switching Characteristics for UARTx Transmit
1
2

Maximum programmable baud rate
Pulse duration, transmit start, stop, data bittw(RX)

0.96U 220/

1.05U 220/nsƒbaud(baud)tw(TX)

U – 2 220/3.6884
U + 2 220/

MHz
ns

(See Figure 101)

UART IrDA Interface

UART IrDA—Signaling Rate and Pulse Duration—Receive Mode
SIGNALING RATE

SIR

MIR

FIR

(See Figure 102)

ELECTRICAL PULSE DURATION

2.4 Kbps
9.6 Kbps
19.2 Kbps
38.4 Kbps
57.6 Kbps
115.2 Kbps

1.41
1.41
1.41
1.41
1.41
1.41

88.55
22.13
11.07
5.96
4.34
2.23

μs
μs
μs
μs
μs
μs

0.576 Mbps
1.152 Mbps

297.2
149.6

518.8
258.4

ns
ns

4 Mbps (single pulse)
4 Mbps (double pulse)

67
190

164
289

ns
ns

2.4 Kbps
9.6 Kbps
19.2 Kbps
38.4 Kbps
57.6 Kbps
115.2 Kbps

78.1
19.5
9.75
4.87
3.25
1.62

78.1
19.5
9.75
4.87
3.25
1.62

μs
μs
μs
μs
μs
μs

0.576 Mbps
1.152 Mbps

414
206

419
211

ns
ns

4 Mbps (single pulse)
4 Mbps (double pulse)

123
248

128
253

ns
ns

UART IrDA—Signaling Rate and Pulse Duration—Transmit Mode
SIR

MIR

FIR

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

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TABLE I. Electrical performance characteristics - Continued. 1/
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Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the
specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may notnecessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or
design.
over recommended ranges of supply voltage and operating temperature (unless otherwise noted).
The interfaces or signals described in this table correspond to the interfaces or signals available in multiplexing mode 0. Allinterfaces or signals multiplexed on the terminals described in this table have the same dc electrical characteristics.
The input voltage thresholds for this input are not a function of VDDSHV6.
The typical value corresponds to 1 cap of 10 μF and 8 caps of 10 nF.
The typical value corresponds to 1 cap of 10 μF and 5 caps of 10 nF.
Typical values consist of 1 cap of 10 μF and 4 caps of 10 nF.
For more details on decoupling capacitor requirements for the mDDR(LPDDR), DDR2, DDR3, DDR3L memory interface, see
Section 7.7.2.1.2.6 and Section 7.7.2.1.2.7 from manufacturer data when using mDDR(LPDDR) memory devices, Section
7.7.2.2.2.6 and Section 7.7.2.2.2.7 from manufacturer data when using DDR2 memory devices, or Section 7.7.2.3.3.6 and Section
7.7.2.3.3.7 from manufacturer data when using DDR3 or DDR3L memory devices.
VDDS_SRAM_CORE_BG supply powers an internal LDO for SRAM supplies. Inrush currents could cause voltage drop on the
VDDS_SRAM_CORE_BG supplies when the SRAM LDO is enabled after powering up VDDS_SRAM_CORE_BG terminals. A 10
μF is recommended to be placed close to the terminal and routed with widest traces possible to minimize the voltage drop on
VDDS_SRAM_CORE_BG terminals.
VDDS_SRAM_MPU_BB supply powers an internal LDO for SRAM supplies. Inrush currents could cause voltage drop on the
VDDS_SRAM_MPU_BB supplies when the SRAM LDO is enabled after powering up VDDS_SRAM_MPU_BB terminals. A 10 μF
is recommended to be placed close to the terminal and routed with widest traces possible to minimize the voltage drop on
VDDS_SRAM_MPU_BB terminals.
Typical values consist of 1 cap of 10 μF and 2 caps of 10 nF.
Typical values consist of 1 cap of 10 μF and 6 caps of 10 nF.
LDO regulator outputs should not be used as a power source for any external components.
The CAP_VDD_RTC terminal operates as an input to the RTC core voltage domain when the RTC_KLDO_ENn terminal is high.
VREFP and VREFN must be tied to ground if the internal voltage reference is used.
This parameter is valid when the respective AIN terminal is configured to operate as a general-purpose ADC input.
Initial accuracy, temperature drift, and aging effects should be combined when evaluating a reference clock for this requirement.
Pxtal = 0.5 ESR (2 π ƒxtal CL VDDS_OSC)2
Initial accuracy, temperature drift, and aging effects should be combined when evaluating a reference clock for this requirement.
Pxtal = 0.5 ESR (2 π ƒxtal CL VDDS_RTC)2
Initial accuracy, temperature drift, and aging effects should be combined when evaluating a reference clock for this requirement.
H = Period of baud rate, 1 / programmed baud rate.
P = Period of PICLKOCP (interface clock).
Except when specified otherwise.
In gpmc_wait[x], x is equal to 0 or 1.
For single read: A = (CSRdOffTime – CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK 39/
For burst read: A=(CSRdOffTime – CSOnTime + (n – 1)×PageBurstAccessTime)×(TimeParaGranularity + 1) × GPMC_FCLK 39/
For burst write: A=(CSWrOffTime – CSOnTime + (n – 1)×PageBurstAccessTime)×(TimeParaGranularity + 1) × GPMC_FCLK 39/
With n being the page burst access number.
B = ClkActivationTime × GPMC_FCLK 39/
For single read: C = RdCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK 39/
For burst read: C = (RdCycleTime + (n – 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK 39/
For burst write: C = (WrCycleTime + (n – 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK 39/
With n being the page burst access number.
For single read: D = (RdCycleTime – AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK 39/
For burst read: D = (RdCycleTime – AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK 39/
For burst write: D = (WrCycleTime – AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK 39/

DLA LAND AND MARITIMECOLUMBUS, OHIO

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For single read: E = (CSRdOffTime – AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK 39/
For burst read: E = (CSRdOffTime – AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK 39/
For burst write: E = (CSWrOffTime – AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK 39/
For csn falling edge (CS activated):– Case GpmcFCLKDivider = 0:
– F = 0.5 × CSExtraDelay × GPMC_FCLK 39/– Case GpmcFCLKDivider = 1:
– F = 0.5 × CSExtraDelay × GPMC_FCLK 39/ if (ClkActivationTime and CSOnTime are odd) or (ClkActivationTime and
CSOnTime are even)– F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK 39/ otherwise– Case GpmcFCLKDivider = 2:
– F = 0.5 × CSExtraDelay × GPMC_FCLK 39/ if ((CSOnTime – ClkActivationTime) is a multiple of 3)– F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK 39/ if ((CSOnTime – ClkActivationTime – 1) is a multiple of 3)– F = (2 + 0.5 × CSExtraDelay) × GPMC_FCLK 39/if ((CSOnTime – ClkActivationTime – 2) is a multiple of 3)
For ADV falling edge (ADV activated):– Case GpmcFCLKDivider = 0:
– G = 0.5 × ADVExtraDelay × GPMC_FCLK 39/– Case GpmcFCLKDivider = 1:
– G = 0.5 × ADVExtraDelay × GPMC_FCLK 39/ if (ClkActivationTime and ADVOnTime are odd) or (ClkActivationTime and
ADVOnTime are even)– G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK 39/ otherwise– Case GpmcFCLKDivider = 2:
– G = 0.5 × ADVExtraDelay × GPMC_FCLK 39 if ((ADVOnTime – ClkActivationTime) is a multiple of 3)– G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK 39/ if ((ADVOnTime – ClkActivationTime – 1) is a multiple of 3)– G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK 39/ if ((ADVOnTime – ClkActivationTime – 2) is a multiple of 3)
For ADV rising edge (ADV deactivated) in Reading mode:– Case GpmcFCLKDivider = 0:
– G = 0.5 × ADVExtraDelay × GPMC_FCLK 39/– Case GpmcFCLKDivider = 1:
– G = 0.5 × ADVExtraDelay × GPMC_FCLK 39/ if (ClkActivationTime and ADVRdOffTime are odd) or (ClkActivationTime
and ADVRdOffTime are even)– G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK 39/ otherwise– Case GpmcFCLKDivider = 2:
– G = 0.5 × ADVExtraDelay × GPMC_FCLK 39/ if ((ADVRdOffTime – ClkActivationTime) is a multiple of 3)– G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK 39/ if ((ADVRdOffTime – ClkActivationTime – 1) is a multiple of 3)– G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK 39/ if ((ADVRdOffTime – ClkActivationTime – 2) is a multiple of 3)
For ADV rising edge (ADV deactivated) in Writing mode:– Case GpmcFCLKDivider = 0:
– G = 0.5 × ADVExtraDelay × GPMC_FCLK 39/– Case GpmcFCLKDivider = 1:
– G = 0.5 × ADVExtraDelay × GPMC_FCLK 39/ if (ClkActivationTime and ADVWrOffTime are odd) or (ClkActivationTime and
ADVWrOffTime are even)– G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK 39/ otherwise– Case GpmcFCLKDivider = 2:
– G = 0.5 × ADVExtraDelay × GPMC_FCLK 39/ if ((ADVWrOffTime – ClkActivationTime) is a multiple of 3)– G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK 39/ if ((ADVWrOffTime – ClkActivationTime – 1) is a multiple of 3)– G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK 39/ if ((ADVWrOffTime – ClkActivationTime – 2) is a multiple of 3)

DLA LAND AND MARITIMECOLUMBUS, OHIO

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DWG NO.

V62/15602

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TABLE I. Electrical performance characteristics - Continued.
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For OE falling edge (OE activated) and IO DIR rising edge (Data Bus input direction):– Case GpmcFCLKDivider = 0:
– H = 0.5 × OEExtraDelay × GPMC_FCLK 39/– Case GpmcFCLKDivider = 1:
– H = 0.5 × OEExtraDelay × GPMC_FCLK 39/ if (ClkActivationTime and OEOnTime are odd) or (ClkActivationTime and
OEOnTime are even)– H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK 39/ otherwise– Case GpmcFCLKDivider = 2:
– H = 0.5 × OEExtraDelay × GPMC_FCLK 39/ if ((OEOnTime – ClkActivationTime) is a multiple of 3)– H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK 39/ if ((OEOnTime – ClkActivationTime – 1) is a multiple of 3)– H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK 39/ if ((OEOnTime – ClkActivationTime – 2) is a multiple of 3)
For OE rising edge (OE deactivated):– Case GpmcFCLKDivider = 0:
– H = 0.5 × OEExtraDelay × GPMC_FCLK 39/– Case GpmcFCLKDivider = 1:
– H = 0.5 × OEExtraDelay × GPMC_FCLK 39/if (ClkActivationTime and OEOffTime are odd) or (ClkActivationTime andOEOffTime are even)– H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK 39/ otherwise– Case GpmcFCLKDivider = 2:
– H = 0.5 × OEExtraDelay × GPMC_FCLK 39/ if ((OEOffTime – ClkActivationTime) is a multiple of 3)– H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK 39/ if ((OEOffTime – ClkActivationTime – 1) is a multiple of 3)– H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK 39/ if ((OEOffTime – ClkActivationTime – 2) is a multiple of 3)
For WE falling edge (WE activated):– Case GpmcFCLKDivider = 0:
– I = 0.5 × WEExtraDelay × GPMC_FCLK 39/– Case GpmcFCLKDivider = 1:
– I = 0.5 × WEExtraDelay × GPMC_FCLK 39/ if (ClkActivationTime and WEOnTime are odd) or (ClkActivationTime and
WEOnTime are even)– I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK 39/ otherwise– Case GpmcFCLKDivider = 2:
– I = 0.5 × WEExtraDelay × GPMC_FCLK 39/ if ((WEOnTime – ClkActivationTime) is a multiple of 3)– I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK 39/ if ((WEOnTime – ClkActivationTime – 1) is a multiple of 3)– I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK 39/ if ((WEOnTime – ClkActivationTime – 2) is a multiple of 3)
For WE rising edge (WE deactivated):– Case GpmcFCLKDivider = 0:
– I = 0.5 × WEExtraDelay × GPMC_FCLK 39/– Case GpmcFCLKDivider = 1:
– I = 0.5 × WEExtraDelay × GPMC_FCLK 39/ if (ClkActivationTime and WEOffTime are odd) or (ClkActivationTime andWEOffTime are even)– I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK 39/ otherwise– Case GpmcFCLKDivider = 2:
– I = 0.5 × WEExtraDelay × GPMC_FCLK 39/ if ((WEOffTime – ClkActivationTime) is a multiple of 3)– I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK 39/ if ((WEOffTime – ClkActivationTime – 1) is a multiple of 3)– I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK 39/ if ((WEOffTime – ClkActivationTime – 2) is a multiple of 3)
J = GPMC_FCLK 39/
In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, or 5. In gpmc_wait[x], x is equal to 0 or 1.
P = gpmc_clk period in ns.
For read: K = (ADVRdOffTime – ADVOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK 39/
For write: K = (ADVWrOffTime – ADVOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK 39/
GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
Related to the gpmc_clk output clock maximum and minimum frequencies programmable in the GPMC module by setting the
GPMC_CONFIG1_CSx configuration register bit field GpmcFCLKDivider.
The jitter probability density can be approximated by a Gaussian function.

DLA LAND AND MARITIMECOLUMBUS, OHIO

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The internal parameters table must be used to calculate data access time stored in the corresponding CS register bit field.
Internal parameters are referred to the GPMC functional internal clock which is not provided externally.
GPMC_FCLK is general-purpose memory controller internal functional clock.
The FA5 parameter shows the amount of time required to internally sample input data. It is expressed in number of GPMC
functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data is internally sampled by activefunctional clock edge. FA5 value must be stored inside the AccessTime register bit field.
The FA20 parameter shows amount of time required to internally sample successive input page data. It is expressed in number of
GPMC functional clock cycles. After each access to input page data, next input page data is internally sampled by activefunctional clock edge after FA20 functional clock cycles. The FA20 value must be stored in the PageBurstAccessTime register bit
field.
The FA21 parameter shows amount of time required to internally sample first input page data. It is expressed in number of GPMC
functional clock cycles. From start of read cycle and after FA21 functional clock cycles, first input page data is internally sampled
by active functional clock edge. FA21 value must be stored inside the AccessTime register bit field.
P = PageBurstAccessTime × (TimeParaGranularity + 1) × GPMC_FCLK 50/
H = AccessTime × (TimeParaGranularity + 1) × GPMC_FCLK 50/
GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
For single read: A = (CSRdOffTime – CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK 50/
For single write: A = (CSWrOffTime – CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK 50/
For burst read: A = (CSRdOffTime – CSOnTime + (n – 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) ×
GPMC_FCLK 50/
For burst write: A = (CSWrOffTime – CSOnTime + (n – 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) ×
GPMC_FCLK 50/ with n being the page burst access number
For reading: B = ((ADVRdOffTime – CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay – CSExtraDelay)) ×
GPMC_FCLK 50/
For writing: B = ((ADVWrOffTime – CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay – CSExtraDelay)) ×
GPC_FCLK 50/
C = ((OEOffTime – CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay – CSExtraDelay)) × GPMC_FCLK 50/
D = PageBurstAccessTime × (TimeParaGranularity + 1) × GPMC_FCLK 50/
E = ((WEOnTime – CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay – CSExtraDelay)) × GPMC_FCLK 50/
F = ((WEOffTime – CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay – CSExtraDelay)) × GPMC_FCLK 50/
G = Cycle2CycleDelay × GPMC_FCLK 50/
I = ((OEOffTime + (n – 1) × PageBurstAccessTime – CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay –CSExtraDelay)) × GPMC_FCLK 50/
J = (CSOnTime × (TimeParaGranularity + 1) + 0.5 × CSExtraDelay) × GPMC_FCLK 50/
K = ((ADVOnTime – CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay – CSExtraDelay)) × GPMC_FCLK 50/
L = ((OEOnTime – CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay – CSExtraDelay)) × GPMC_FCLK 50/
For single read: N = RdCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK 50/
For single write: N = WrCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK 50/
For burst read: N = (RdCycleTime + (n – 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK 50/
For burst write: N = (WrCycleTime + (n – 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK 50/
In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, or 5.
Internal parameters table must be used to calculate data access time stored in the corresponding CS register bit field.
Internal parameters are referred to the GPMC functional internal clock which is not provided externally.
The GNF12 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC
functional clock cycles. From start of the read cycle and after GNF12 functional clock cycles, input data is internally sampled by
the active functional clock edge. The GNF12 value must be stored inside AccessTime register bit field.
J = AccessTime × (TimeParaGranularity + 1) × GPMC_FCLK 50/
A = (WEOffTime – WEOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK 50/
B = ((WEOnTime – CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay – CSExtraDelay)) × GPMC_FCLK 50/
C = ((WEOnTime – ADVOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay – ADVExtraDelay)) × GPMC_FCLK 50/
D = (WEOnTime × (TimeParaGranularity + 1) + 0.5 × WEExtraDelay) × GPMC_FCLK 50/
E = ((WrCycleTime – WEOffTime) × (TimeParaGranularity + 1) – 0.5 × WEExtraDelay) × GPMC_FCLK 50/

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TABLE I. Electrical performance characteristics - Continued.
73/
74/
75/
76/
77/
78/
79/
80/
81/
82/
83/
84/
85/
86/
87/
88/
89/
90/
91/
92/
93/
94/
95/
96/
97/
98/
99/
100/
101/
102/
103/
104/
105/
106/
107/
108/
109/
110/
111/
112/

F = ((ADVWrOffTime – WEOffTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay – WEExtraDelay)) × GPMC_FCLK 50/
G = ((CSWrOffTime – WEOffTime) × (TimeParaGranularity + 1) + 0.5 × (CSExtraDelay – WEExtraDelay)) × GPMC_FCLK 50/
H = WrCycleTime × (1 + TimeParaGranularity) × GPMC_FCLK 50/
I = ((OEOnTime – CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay – CSExtraDelay)) × GPMC_FCLK 50/
K = (OEOffTime – OEOnTime) × (1 + TimeParaGranularity) × GPMC_FCLK 50/
L = RdCycleTime × (1 + TimeParaGranularity) × GPMC_FCLK 50/
M = ((CSRdOffTime – OEOffTime) × (TimeParaGranularity + 1) + 0.5 × (CSExtraDelay – OEExtraDelay)) × GPMC_FCLK 50/
In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, or 5.
If the LPDDR interface is operated with a clock frequency less than 200 MHz, lower-speed grade LPDDR devices may be used if
the minimum clock period specified for the LPDDR device is less than or equal to the minimum clock period selected for the
AM3358-EP LPDDR interface.
For the LPDDR device BGA pad size, see the LPDDR device manufacturer documentation.
A 20-10 via may be used if enough power routing resources are available. An 18-10 via allows for more flexible power routing to
the AM3358-EP device.
Zo is the nominal singled-ended impedance selected for the PCB.
This parameter specifies the AC characteristic impedance tolerance for each segment of a PCB signal trace relative to the chosen
Zo defined by the single-ended impedance parameter.
Tighter impedance control is required to ensure flight time skew is minimal.
LPDDR keepout region to encompass entire LPDDR routing area.
For dimension definitions, see Figure 49.
Measurements from center of AM3358-EP device to center of LPDDR device.
For single-memory systems, TI recommends that Y offset be as small as possible.
w is defined as the signal trace width.
Non-LPDDR signals allowed within LPDDR keepout region provided they are separated from LPDDR routing layers by a groundplane.
These devices should be placed near the device they are bypassing, but preference should be given to the placement of the highspeed (HS) bypass capacitors
Only used when two LPDDR devices are used.
LxW, 10-mil units; for example, a 0402 is a 40x20-mil surface-mount capacitor.
An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board.
These devices should be placed as close as possible to the device being bypassed.
Per LPDDR device.
Only series termination is permitted.
Zo is the LPDDR PCB trace characteristic impedance.
Series termination values larger than typical only recommended to address EMI issues.
Series termination values should be uniform across net class.
CK represents the clock net class, and ADDR_CTRL represents the address and control signal net class.
Series terminator, if used, should be located closest to the AM3358-EP device.
Differential impedance should be Zo x 2, where Zo is the single-ended impedance defined in Table 1 “PCB Stackup
Specifications” sheet 33.
Center-to-center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape androuting congestion
CACLM is the longest Manhattan distance of the CK and ADDR_CTRL net classes.
DQS[x] represents the DQS0 and DQS1 clock net classes, and DQ[x] represents the DQ0 and DQ1 signal net classes.
Center-to-center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape androuting congestion.
There is no requirement for skew matching between data bytes; that is, from net classes DQS0 and DQ0 to net classes DQS1
and DQ1.
Signals from one DQ net class should be considered other LPDDR traces to another DQ net class.
DQLM is the longest Manhattan distance of each of the DQS[x] and DQ[x] net classes.

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TABLE I. Electrical performance characteristics - Continued.
113/
114/
115/
116/
117/
118/
119/
120/
121/
122/
123/
124/
125/
126/
127/
128/
129/
130/
131/
132/
133/
134/
135/
136/
137/
138/
139/
140/
141/
142/
143/
144/
145/
146/
147/
148/
149/

The JEDEC JESD79-2F specification defines the maximum clock period of 8 ns for all standard-speed bin DDR2 memory
devices. Therefore, all standard-speed bin DDR2 memory devices are required to operate at 125 MHz.
If the DDR2 interface is operated with a clock frequency less than 266 MHz, lower-speed grade DDR2 devices may be used if
the minimum clock period specified for the DDR2 device is less than or equal to the minimum clock period selected for the
AM3358-EP DDR2 interface.
Higher DDR2 speed grades are supported due to inherent JEDEC DDR2 backwards compatibility.
92-terminal devices are also supported for legacy reasons. New designs will migrate to 84-terminal DDR2 devices. Electrically,
the 92- and 84-terminal DDR2 devices are the same.
For the DDR2 device BGA pad size, see the DDR2 device manufacturer documentation.
A 20-10 via may be used if enough power routing resources are available. An 18-10 via allows for more flexible power routing to
the AM3358-EP device.
Zo is the nominal singled-ended impedance selected for the PCB.
This parameter specifies the AC characteristic impedance tolerance for each segment of a PCB signal trace relative to thechosen Zo defined by the single-ended impedance parameter.
Tighter impedance control is required to ensure flight time skew is minimal.
DDR2 keepout region to encompass entire DDR2 routing area.
For dimension definitions, see Figure 53.
Measurements from center of AM3358-EP device to center of DDR2 device.
For single-memory systems, it is recommended that Y offset be as small as possible.
w is defined as the signal trace width.
Non-DDR2 signals allowed within DDR2 keepout region provided they are separated from DDR2 routing layers by a groundplane.
These devices should be placed near the device they are bypassing, but preference should be given to the placement of thehigh-speed(HS) bypass capacitors.
Only used when two DDR2 devices are used.
LxW, 10-mil units; for example, a 0402 is a 40x20-mil surface-mount capacitor.
An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board.
These devices should be placed as close as possible to the device being bypassed.
Per DDR2 device.
Only series termination is permitted.
Series termination values larger than typical only recommended to address EMI issues.
Series termination values should be uniform across net class.
Zo is the DDR2 PCB trace characteristic impedance.
No external termination resistors are allowed and ODT must be used for these net classes.
CK represents the clock net class, and ADDR_CTRL represents the address and control signal net class.
Series terminator, if used, should be located closest to the AM3358-EP device.
Differential impedance should be Zo x 2, where Zo is the single-ended impedance defined in table” PCB Stackup
Specifications” sheet 36 herein .
Center-to-center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape androuting congestion.
CACLM is the longest Manhattan distance of the CK and ADDR_CTRL net classes.
DQS[x] represents the DQS0 and DQS1 clock net classes, and DQ[x] represents the DQ0 and DQ1 signal net classes.
There is no requirement for skew matching between data bytes; that is, from net classes DQS0 and DQ0 to net classes DQS1
and DQ1.
Signals from one DQ net class should be considered other DDR2 traces to another DQ net class.
DQLM is the longest Manhattan distance of each of the DQS[x] and DQ[x] net classes.
The JEDEC JESD209B specification only defines the maximum clock period for LPDDR333 and faster speed bin LPDDR
memory devices. To determine the maximum clock period, see the respective LPDDR memory data sheet.
The JEDEC JESD79-3F Standard defines the maximum clock period of 3.3 ns for all standard-speed bin DDR3 and DDR3L
memory devices. Therefore, all standard-speed bin DDR3 and DDR3L memory devices are required to operate at 303 MHz.

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TABLE I. Electrical performance characteristics - Continued.
150/ For valid DDR3 device configurations and device counts, see manufacturer data Section 7.7.2.3.3.1, Figure 7-47 andFigures 7-49.
151/ For the DDR3 device BGA pad size, see the DDR3 device manufacturer documentation.
152/ Ground reference layers are preferred over power reference layers. Be sure to include bypass caps to accommodate reference
layer return current as the trace routes switch routing layers.
153/ No traces should cross reference plane cuts within the DDR3 routing region. High-speed signal traces crossing reference planecuts create large return current paths which can lead to excessive crosstalk and EMI radiation.
154/ Reference planes are to be directly adjacent to the signal plane to minimize the size of the return current loop.
155/ An 18-mil pad assumes Via Channel is the most economical BGA escape. A 20-mil pad may be used if additional layers areavailable for power routing. An 18-mil pad is required for minimum layer count escape.
156/ Zo is the nominal singled-ended impedance selected for the PCB.
157/ This parameter specifies the AC characteristic impedance tolerance for each segment of a PCB signal trace relative to thechosen Zo defined by the single-ended impedance parameter.
158/ Tighter impedance control is required to ensure flight time skew is minimal.
159/ DDR3 keepout region to encompass entire DDR3 routing area.
160/ For dimension definitions, see manufacturer data Figure 7-50.
161/ Measurements from center of AM3358-EP device to center of DDR3 device.
162/ Minimizing X1 and Y improves timing margins.
163/ w is defined as the signal trace width.
164/ Non-DDR3 signals allowed within DDR3 keepout region provided they are separated from DDR3 routing layers by a groundplane.
165/ These devices should be placed near the devices they are bypassing, but preference should be given to the placement of thehigh speed (HS) bypass capacitors and DDR3 signal routing.
166/ Only used when two DDR3 devices are used.
167/ LxW, 10-mil units; for example, a 0402 is a 40x20-mil surface-mount capacitor.
168/ Closer and shorter is better.
169/ Measured from the nearest AM3358-EP VDDS_DDR and ground terminal to the center of the capacitor package.
170/ Three of these capacitors should be located underneath the AM3358-EP device, between the cluster of VDDS_DDR andground terminals, between the DDR3 interfaces on the package.
171/ Measured from the DDR3 device power and ground terminal to the center of the capacitor package.
172/ Per DDR3 device.
173/ An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board. No
sharing of vias is permitted on the same side of the board.
174/ An HS bypass capacitor may share a via with a DDR3 device mounted on the same side of the PCB. A wide trace should be
used for the connection and the length from the capacitor pad to the DDR3 device pad should be less than 150 mils.
175/ Up to a total of two pairs of DDR3 power and ground terminals may share a via.
176/ CK represents the clock net class, and ADDR_CTRL represents the address and control signal net class.
177/ The use of vias should be minimized.
178/ Additional bypass capacitors are required when using the VDDS_DDR plane as the reference plane to allow the return current to jump between
179/
180/
181/
182/
183/
184/
185/
186/
187/
188/
189/

the VDDS_DDR plane and the ground plane when the net class switches layers at a via.
Mirrored configuration (one DDR3 device on top of the board and one DDR3 device on the bottom).

Non-mirrored configuration (all DDR3 memories on same side of PCB).
While this length can be increased for convenience, its length should be minimized.
ADDR_CTRL net class only (not CK net class). Minimizing this skew is recommended, but not required.
CK net class only.
CACLM is the longest Manhattan distance of the CK and ADDR_CTRL net classes + 300 mils. For definition, see manufacturer
data Section 7.7.2.3.6.1 and Figure 58 herein.
Center-to-center spacing is allowed to fall to minimum (w) for up to 1250 mils of routed length.
Signals from one DQ net class should be considered other DDR3 traces to another DQ net class.
CK spacing set to ensure proper differential impedance. Differential impedance should be Zo x 2, where Zo is the single-ended
impedance defined in manufacturer data in Table 7-60.
Source termination (series resistor at driver) is specifically not allowed.
Termination values should be uniform across the net class.

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TABLE I. Electrical performance characteristics - Continued.
190/
191/
192/
193/
194/
195/
196/
197/
198/
199/
200/
201/

202/
203/
204/
205/

206/
207/
208/
209/
210/
211/
212/

213/
214/
215/
216/
217/
218/
219/
220/

DQS[x] represents the DQS0 and DQS1 clock net classes, and DQ[x] represents the DQ0 and DQ1 signal net classes.
External termination disallowed. Data termination should use built-in ODT functionality
DQLMn is the longest Manhattan distance of a byte. For definition, see manufacturer data on Section 7.7.2.3.6.2 and Figure 59
DQLM0 is the longest Manhattan length for the DQ0 net class.
DQLM1 is the longest Manhattan length for the DQ1 net class.
Length matching is only done within a byte. Length matching across bytes is not required.
Each DQS clock net class is length matched to its associated DQ signal net class.
Center-to-center spacing is allowed to fall to minimum for up to 1250 mils of routed length.
Other DDR3 trace spacing means signals that are not part of the same DQ[x] signal net class.
This applies to spacing within same DQ[x] signal net class.
DQS[x] pair spacing is set to ensure proper differential impedance. Differential impedance should be Zo x 2, where Zo is the
singleended impedance defined in manufacturer data in Table 7-60
A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH)≥ 250 ns mustthen be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device
stretches the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH) = 1000 + 250 =
1250 ns (according to the standard-mode I2C-Bus Specification) before the SCL line is released.
A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge
the undefined region of the falling edge of SCL.
The maximum th(SDA-SCLL) has only to be met if the device does not stretch the low period [tw(SCLL)] of the SCL signal
Except when specified otherwise.
ACLKR internal: ACLKRCTL.CLKRM = 1, PDIR.ACLKR = 1
ACLKR external input: ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
ACLKR external output: ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
ACLKX internal: ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
ACLKX external output: ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
P = McASP[x]_AHCLKR and McASP[x]_AHCLKX period in nanoseconds (ns).
R = McASP[x]_ACLKR and McASP[x]_ACLKX period in ns.
P = SPI_CLK period.
This timing applies to all configurations regardless of MCSPIX_CLK polarity and which clock edges are used to drive output
data and capture input data.
Pins SPIx_D0 and SPIx_D1 can function as SIMO or SOMI.
Pins SPIx_D0 and SPIx_D1 can function as SIMO or SOMI.
The polarity of SPIx_CLK and the active edge (rising or falling) on which mcspix_simo is driven and mcspix_somi is latched isall software configurable:– SPIx_CLK(1) phase programmable with the bit PHA of MCSPI_CH(i)CONF register: PHA = 1 (Modes 1 and 3).
– SPIx_CLK(1) phase programmable with the bit PHA of MCSPI_CH(i)CONF register: PHA = 0 (Modes 0 and 2).
Case P = 20.8 ns, A = (TCS + 1) × TSPICLKREF (TCS is a bit field of MCSPI_CH(i)CONF register).
Case P > 20.8 ns, A = (TCS + 0.5) × Fratio × TSPICLKREF (TCS is a bit field of MCSPI_CH(i)CONF register).
Note: P = SPI_CLK clock period.
B = (TCS + 0.5) × TSPICLKREF × Fratio (TCS is a bit field of MCSPI_CH(i)CONF register, Fratio: Even ≥ 2).
P = MMC_CLK period.
P = L3_CLK (PRU-ICSS ocp clock) period.
n = 16n = 15
Except when specified otherwise.
U = UART baud time = 1/programmed baud rate.

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2.
3.
4.

All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.
This drawing is subject to change without notice.
Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For information, seemanufacturer data number SPRAA99.
Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
FIGURE 1. Case outline.

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n~~--_-_----------=--==-~ ---;:::=__--==-~~---- _ -- -------=-~1_----=-------,-~ -ARM
Cortex-AB
Up to 1 GHz

Graphics
PowerVR
SGX
3DGFX

32K and 32K L1+SED

CryptoPRU-ICS S

256K L2+ECC

64K
sharedRAM

PROFINET,
EtherNet/lP,
and more

176K ROMI

64K RAM

Display
24-bit LCD controller
Touch screen controller

L3 and L4 interconnect
SerialSystemUARTx6eDMA
Timers x8

SPlx2
ICx3
McASP x2
(4 channel)

ParalleleCAP x3
ADC (8 channel)
12-bit SAR

MMC, SD and
SDIOx3

WDT

GPIO
JTAG

RTC
eHRPWMx3

CANx2(Ver. 2A and B)

eQEP x3

CrystalOscillator X2

PRCM

USB 2.0 HS
OTG+PHYx2Memory interface
mDDR(LPDDR), DDR2
DDR3, DDR3L(16-bit. 200,266,400,400 MHz)EMAC (2-port) 10M, 1QOM, 1G
IEE 1588v2, and switch(MIi, RMII, RGMII)

NAND and NOT (16-bit ECC)~------------------------J
FIGURE 2. Functional block diagram.

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A

B

C

D

18

vss

EXTINTe

EXAPO_IN_PWMC_OUTUARTI_CTSn

UARTO_CTSn

MMCO_DAT217SP IO_SCLKSPIO_DO

12CO_SDAUART1 _RTSn

UARTO_RTSn

MMCO_DAT316SPIO_CSDSPIO_D1

12CO_SCLUART1_RXD

UARTO_ TXD

USBO_DRVVBUS

15

ZDMA_EVENT _INTROPWRONRSTnSPIO_CS 1

UART1 _ TXD

UARTO_RXD

USB1 _DRVVBUS

14

MCASPO_AHCLKX

EMU1

EMUO

XDMA_EVENT_INTR1VDDS

VDDSHV6

13MCASPO_AC LKXMCASPO_FSXMCASPO_FSR

MCASPO_AXR1

VDDSHV6

VDD_MPU12TCK

MCASPO_ACLKRMCASPO_ACLKRMCASPO_AXROVDDSHV6

VDD_MPU

11

TOO

TOI

TMS

CAP_VDD_SRAM_MPU

VDDSHV6

VDD_MPU

1Q

WARMRSTn

TRSTn

CAP_VBB_MPU

VDDS_SRAM_MPU_BB

VDDSHV6

VDD_MPU

9

VREFN

VREFP

AIN7

8

AIN6

AINS

AIN4

VDDA_ADCVSSA_ADC

vss

7

AIN3

AIN2

AIN1

VDDS_RTCVDDS_PLL_DRR

VDD_CORE6

RTC_XTALINAINOPM IC POWER EN

CAP_ VDD_RTC

VDDS

VDD_CORE

5

VSS_RTC

RTC KALDO ENu

EXT_WAKEUPDDR_A6

DDR_A2

DDR_A 10

4

RTC_XTALOUT

RTC_KALDO_ENu

DDR_BAO

DDR_AS

DDR_A 12

DDR_AO

3

RESERVED

DDR_BA2

DDR_A3

DDR_A 15

DDR_A 12

DDR_AO

2VDO_MPU_MON

DDR_WEn

DDR_A4

DDR_CK

DDR_A7

DDR_A11vss

DDR_AS

DDR_A9DDR_CKn

DDR_BA 1

DDR_CASnF

CAP_VDD_SRAM_CORE VDDS_SRAM_CORE_BG

VDDS

FIGURE 3. Pin Map Location (Section Left)

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G

H

K

L

M

18

MMCO_CMD

RMll1 - REF _CLK

Mll 1_TXD3

Mii 1- TX - CLK

Mll 1- RX - CLK

MDC

17

MMCO_CLK

Mll1_CRS

Mii 1_CRS

Mll1_TXDO

Mll 1- RXD3

MDIO

16

MMCO_DATO

Mll1_CO L

Mll1 _TX_EN

Mll1 _TXD1

Mll 1- RXD2

Mll1 - RX DO

15

MMCO_DAT1VDDS_PLL_MPU

Mll1 - RX - ER

Mll1_TXD2

Mll1 - RXD1

USBO_CE

14

VDDSHV6VDDSHV4VDDSHV4VDDSHVSVDDSHV5VSSA_US13

VDD_MPU

VDD_MP U

VDD_MPU

VDDS

vss

VDD_CORE

12

vss

vss

VDD_COREVDD_CORE

vss

vss

11

vss

VDD_CO RE

vss

vss

vss

VDD_CORE

10VDD_CORE

vss

vss

vss

vss

vss

9

vss

vss

vss

vss

VDD_CORE

vss

8

vss

vss

vss

VDD_COREVDD_CORE

vss

7

VDD_CORE

vss

vss

vss

VDD_CORE

vss

6

VDD_CORE

vss

vss

VDD_COREVDD_CORE

vss

5

VDDS_DDRVDDS_DDRVDDS_DD R

VDDS_DDRVDD_CORE

VP P

4

DDR_RASn

DD R_A14

VDDS_VRE F

DDR_D12

DDR_D14

DDR_D1

3

DDR_CKE

DDR_A13

VDDS_ VTP

DDR_D11

DD R_D13

DDR_DO2

DDR_RES ETn

DDR_CSnO

DDR_DQM1

DDR_D10

DDR_DQS n1

DD R_DQSO

DDR_ODT

DDR_A 1

DD R_D8

DDR_ D9

DD R_D0S1

DDR_D15

FIGURE 4. Pin Map Location (Section Middle)

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N

p

R

T

u

V

18

USBO_DM

USB1_CE

USB1_DM

USB1_VBUS

GPMC_BEn 1

vss

17

USBO_DP

USBUD

USB 1_DPGPMC_WAITO

GPMC_W Pn

GPMC_A11

16

VDDA 1P8V _USBO

USBO_ID

VDDA1P8V_USB1

GPMC_A10

GPMC_A9

GPMC_A8

15

VDDA3P3V _USBO

USBO_VB US

VDDA3P3V_USB1

GPMC_A?

GPMC_A6

GPMC_AS14

VSSA_ USB

VDDS

GPMC_A4

GPMC_A3

GPMC_A2

GPMC_A1

13

VDD_COREVDDSHV3

GPMC_AO

GPMC_CSn3

GPMC_AD 15

GPMC_AD1412VDD_COREVDDSHV3

GPMC_AD13

GPMC_AD12

GPMC_AD11

GPMC_CLK

11

vss

VDDSHV2

VDDS_OSC

GPMC_AD10XTALOUTVSS_OSC

10

vss

VDDSHV2

VDDS_PLL_CORE_LCD

GPMC_AD9GPMC_AD8XTALI N9VDD_CORE

VDDS

GPMC_AD6

GPMC_AD?

GPMC_CSn 1

GPMC_CSn2

8

VDD_COREVDDSHV1

GPMC_AD2

GPMC_AD3

GPMC_AD4

GPMC_ADS

7

vss

VDDSHV1

GPMC_ADVn _ALE

GPMC_OEn_R En

GPMC_ADOGPMC_AD16VDDS

VDDSHV6

LCD_AC_B IAS_ EN

GPMC_BEnO_CLE

GPMC_WEn

GPMC_CSnO

5

VDDSHV6VDDSHV6

LCD_HSYNC

LCD_DATA15

LCD_ VSYNC

LCD_PCLK

4

DDR_DS

DDR_D?

LCD_DATA3LCD_DATA?

LCD_DATA11

LCD_DATA1 4

3

DDR_D4

DDR_D6

LCD_DATA2LCD_DATA6LCD_DATA10LCD_DATA13

2

DDR_D3

DDR_DQSnOLCD_DATA1LCD_DATASLCD_DATA9LCD_DATA12

DDR_D2

DDR_DQSOLCD_DATAOLCD_DATA4LCD_DATA8

vss

FIGURE 5. Pin Map Location (Section Right)

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

V62/15602

REV

PAGE

74

SUPPLY VALUE

sleW rate<1 Ef5\/Jssle¥.1'.51.f.ip~ vale)I( 1E+5Vfs)
s~tt value~O µs

FIGURE 6. Power Supply and Slew Rate.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

V62/15602

REV

PAGE

75

'\,f.l!IS_R'FC

RTC~~

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ALL .8-¥81gr;1r

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Notes:A.

RTC_PWRONRSTn should be asserted for at least 1 ms to provide enough time for the internal RTC LDO output to reach avalid level before RTC reset is released.
B. When using the GCZ package option, VDD_MPU and VDD_CORE power inputs may be powered from the same source if theapplication only uses operating performance points (OPPs) that define a common power supply voltage for VDD_MPU andVDD_CORE.
C. If a USB port is not used, the respective VDDA1P8V_USB terminal may be connected to any 1.8-V power supply and therespective VDDA3P3V_USB terminal may be connected to any 3.3-V power supply. If the system does not have a 3.3-V power
supply, the VDDA3P3V_USB terminal may be connected to ground.
D. If the system uses mDDR or DDR2 memory devices, VDDS_DDR can be ramped simultaneously with the other 1.8-V IIO
power supplies.
E. VDDS_RTC can be ramped independent of other power supplies if PMIC_POWER_EN functionality is not required. If
VDDS_RTC is ramped after VDD_CORE, there might be a small amount of additional leakage current on VDD_CORE. The
power sequence shown provides the lowest leakage option.
F. To configure VDDSHVx [1-6] as 1.8 V, power up the respective VDDSHVx [1-6] to 1.8 V following the recommended sequence.
To configure VDDSHVx [1-6] as 3.3 V, power up the respective VDDSHVx [1-6] to 3.3 V following the recommended sequence.
FIGURE 7. Preferred Power Supply Sequencing with Dual Voltage IOs Configured as 3.3 V.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

V62/15602

REV

PAGE

76

RrC_PVIROtRSTm

A.L. 1&V'S1'p;,ilil

ltl.3;31--V~\UIS__LUl:-

I I-tl""'"TII

I

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11

1

PYIROtRSTn

ru<Jl.0SC""""TI-

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11

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11

-

I I
I I

.1V

11

I

11

11
11

Notes:A.

RTC_PWRONRSTn should be asserted for at least 1 ms to provide enough time for the internal RTC LDO output to reach a valid
level before RTC reset is released.
B. The 3.3-V IO power supplies may be ramped simultaneously with the 1.8-V IO power supplies if the voltage sourced by any 3.3-V
power supplies does not exceed the voltage sourced by any 1.8-V power supply by more than 2 V. Serious reliability issues may
occur if the system power supply design allows any 3.3-V IO power supplies to exceed any 1.8-V IO power supplies by more than
2 V.
C. When using the GCZ package option, VDD_MPU and VDD_CORE power inputs may be powered from the same source if theapplication only uses operating performance points (OPPs) that define a common power supply voltage for VDD_MPU andVDD_CORE.
D. If a USB port is not used, the respective VDDA1P8V_USB terminal may be connected to any 1.8-V power supply and therespective VDDA3P3V_USB terminal may be connected to any 3.3-V power supply. If the system does not have a 3.3-V power
supply, the VDDA3P3V_USB terminal may be connected to ground.
E. If the system uses mDDR or DDR2 memory devices, VDDS_DDR can be ramped simultaneously with the other 1.8-V IO power
supplies.
F. VDDS_RTC can be ramped independent of other power supplies if PMIC_POWER_EN functionality is not required. If
VDDS_RTC is ramped after VDD_CORE, there might be a small amount of additional leakage current on VDD_CORE. The
power sequence shown provides the lowest leakage option.
G. To configure VDDSHVx [1-6] as 1.8 V, power up the respective VDDSHVx [1-6] to 1.8 V following the recommended sequence.
To configure VDDSHVx [1-6] as 3.3 V, power up the respective VDDSHVx [1-6] to 3.3 V following the recommended sequence.
FIGURE 8. Alternate Power-Supply Sequencing with Dual-Voltage IOs Configured as 3.3 V.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

V62/15602

REV

PAGE

77

1.8V
VDDS_RTC
1.8V
RTC PWRONRSTn
1.8V
PMIC_POWER_EN------t-'

1.8V

ALL 1.8- V Su pplies-------t-------i-

1.8V/1 .5V/1 .35V
VDDS _ DDR
3.3V

ALL 3.3 - V Su pplies ---+-----i------r1.1V
VDD_ CORE, VD D_M PU ----+-l------t--,~PWRONRSTn

CLK_M_OSC

Notes:
A.
B.
C.
D.
E.
F.

RTC_PWRONRSTn should be asserted for at least 1 ms to provide enough time for the internal RTC LDO output to reach avalid level before RTC reset is released.
When using the GCZ package option, VDD_MPU and VDD_CORE power inputs may be powered from the same source if theapplication only uses operating performance points (OPPs) that define a common power supply voltage for VDD_MPU andVDD_CORE.
If a USB port is not used, the respective VDDA1P8V_USB terminal may be connected to any 1.8-V power supply and therespective VDDA3P3V_USB terminal may be connected to any 3.3-V power supply. If the system does not have a 3.3-V power
supply, the VDDA3P3V_USB terminal may be connected to ground.
If the system uses mDDR or DDR2 memory devices, VDDS_DDR can be ramped simultaneously with the other 1.8-V IO power
supplies.
VDDS_RTC can be ramped independent of other power supplies if PMIC_POWER_EN functionality is not required. If
VDDS_RTC is ramped after VDD_CORE, there might be a small amount of additional leakage current on VDD_CORE. The
power sequence shown provides the lowest leakage option.
To configure VDDSHVx [1-6] as 1.8 V, power up the respective VDDSHVx [1-6] to 1.8 V following the recommended sequence.
To configure VDDSHVx [1-6] as 3.3 V, power up the respective VDDSHVx [1-6] to 3.3 V following the recommended sequence.
FIGURE 9. Power-Supply Sequencing With Dual-Voltage IOs Configured as 1.8 V.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

V62/15602

REV

PAGE

78

1.8V
1. 1V

VDDS_RTC
CAP _ VDD_ RTC

1.8V

RTc_PWRON RST n
1.8V
PMIC_POWER_EN
1.8V
VDDSHV1-6
ALL 1.8-V Sup plies-------i------i-

1.8V /1.5V /1.35V
VD DS_DDR
3.3V
ALL 3.3 - V Sup plies
1.1 V
VDD_CORE, VDD_MPU

PWRONRSTn

CLK_M_OSC

Notes:A.

RTC_PWRONRSTn should be asserted for at least 1 ms to provide enough time for the internal RTC LDO output to reach avalid level before RTC reset is released.
B. The CAP_VDD_RTC terminal operates as an input to the RTC core voltage domain when the internal RTC LDO is disabled byconnecting the RTC_KALDO_ENn terminal to VDDS_RTC. If the internal RTC LDO is disabled, CAP_VDD_RTC should besourced from an external 1.1-V power supply.
C. When using the GCZ package option, VDD_MPU and VDD_CORE power inputs may be powered from the same source if theapplication only uses operating performance points (OPPs) that define a common power supply voltage for VDD_MPU andVDD_CORE.
D. If a USB port is not used, the respective VDDA1P8V_USB terminal may be connected to any 1.8-V power supply and therespective VDDA3P3V_USB terminal may be connected to any 3.3-V power supply. If the system does not have a 3.3-V power
supply, the VDDA3P3V_USB terminal may be connected to ground.
E. If the system uses mDDR or DDR2 memory devices, VDDS_DDR can be ramped simultaneously with the other 1.8-V IO power
supplies.
F. VDDS_RTC should be ramped at the same time or before CAP_VDD_RTC, but these power inputs can be ramped
independent of other power supplies if PMIC_POWER_EN functionality is not required. If CAP_VDD_RTC is ramped after
VDD_CORE, there might be a small amount of additional leakage current on VDD_CORE. The power sequence shown
provides the lowest leakage option.
G. To configure VDDSHVx [1-6] as 1.8 V, power up the respective VDDSHVx [1-6] to 1.8 V following the recommended sequence.
To configure VDDSHVx [1-6] as 3.3 V, power up the respective VDDSHVx [1-6] to 3.3 V following the recommended sequence.
FIGURE 10. Power-Supply Sequencing With Internal RTC LDO Disabled.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

V62/15602

REV

PAGE

79

1. 8VVDDS HV1-6
ALL 1.8-V Sup plies
1.8V / 1.SV / 1.35V
VD DS_DDR
3.3V
ALL 3.3-V Supp lies

1.1V

VDD CORE , VDD _ MPU- CAP VDD_RTC

PWRONRSTn

CLK _ M_ OSC

Notes:
A.
B.
C.
D.
E.

F.

CAP_VDD_RTC terminal operates as an input to the RTC core voltage domain when the internal RTC LDO is disabled byconnecting the RTC_KALDO_ENn terminal to VDDS_RTC. If the internal RTC LDO is disabled, CAP_VDD_RTC should besourced from an external 1.1-V power supply. The PMIC_POWER_EN output cannot be used when the RTC is disabled.
When using the GCZ package option, VDD_MPU and VDD_CORE power inputs may be powered from the same source if theapplication only uses operating performance points (OPPs) that define a common power supply voltage for VDD_MPU andVDD_CORE.
If a USB port is not used, the respective VDDA1P8V_USB terminal may be connected to any 1.8-V power supply and therespective VDDA3P3V_USB terminal may be connected to any 3.3-V power supply. If the system does not have a 3.3-V power
supply, the VDDA3P3V_USB terminal may be connected to ground.
If the system uses mDDR or DDR2 memory devices, VDDS_DDR can be ramped simultaneously with the other 1.8-V IO power
supplies.
VDDS_RTC should be ramped at the same time or before CAP_VDD_RTC, but these power inputs can be ramped
independent of other power supplies if PMIC_POWER_EN functionality is not required. If CAP_VDD_RTC is ramped after
VDD_CORE, there might be a small amount of additional leakage current on VDD_CORE. The power sequence shown
provides the lowest leakage option.
To configure VDDSHVx [1-6] as 1.8 V, power up the respective VDDSHVx [1-6] to 1.8 V following the recommended sequence.
To configure VDDSHVx [1-6] as 3.3 V, power up the respective VDDSHVx [1-6] to 3.3 V following the recommended sequence.
FIGURE 11. Power-Supply Sequencing with RTC Feature Disabled.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

V62/15602

REV

PAGE

80

Powernagement
IC

335x Device
VDO_MPU_MON
VfeedbackConnectioin for VDD MPU MON if volrage monitoring 1s used

VDO_MPU

VOD_MPU_MON

335x Device

POWER
SOURCE

Preferred connectioin for VDD MPU MON if nolrage monitoring is NOT used

VOD_MPU
POWER
SOURCE

335x Device

Optional conncection or VDD MPU MON if voltage monitoring is NOT used

FIGURE 12. VDD_MPU_MON Connectivity.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

V62/15602

REV

PAGE

81

MPU
PLL

VDDS _ PLL_ MP U

PER
PLL

VDDA1P8V_ USBO

~
L

DO R
PLL

LCD
PLL

VDDS _ PLL_ COR E_ LC D

VD DS_PLL_DDR

FIGURE 13. DPLL Power Supply Connectivity.

VDD_CORE( min)vss

I

VDD_COR E

Q)

0)

0

~

VD DS_OSC( min)>

VDDS_OSC--XTA LO UT"-

I !\/\/\/◄
A

vss

...
~

....

tsx

~

FIGURE 14. OSC0 Start-Up Time.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

V62/15602

REV

PAGE

82

CAP_ VDD_ RTC (mi n)

CAP_ VDD_ RTC

I

VSS _ RTC
Q)
0)0-:; VDDS _ RTC (mi n)>

VDDS _ RTC

I

I

VDDS_◄ ·/\1/\/\/\/ \/RTC XTALOUT

,..
~

'

tsx

►

Time
FIGURE 15. OSC1 Start-up Time.

AM335x(ZC Z Pac kage)
RTC _ XTA LI N

VSS _ RTC

RTC_XTA LOUTVDDS _ RTC
LVCMOS
Di gital
Clock
SourceN/ C

FIGURE 16. OSC1 LVCMOS Circuit Schematic.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

V62/15602

REV

PAGE

83

DCANx_ RX

DCANx_TX

FIGURE 17. DCANx Timings.

1

TCLKIN2
TIMER(x)3-----------FIGURE 18. Timer Timing.

MDIO_DAT A( outp ut)

MDIO_DAT A(I nput)

FIGURE 19. MDIO_DATA Timing - Input Mode.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

V62/15602

REV

PAGE

84

1:

4

-

2

3

·1

1·

·1
-t-1-_4_

MD IO_CLK-rr

FIGURE 20. MDIO_CLK Timing.

MD IO_CLK( output)

MDIO_DAT A( output)

FIGURE 21. MDIO_DATA Timing - Output Mode.

-\_ _ _ _ _ _ _GMll(x)_ RXCLK

~

I -

3

-

i,---------cf=rij

FIGURE 22. GMII[x]_RXCLK Timing - MII Mode.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

V62/15602

REV

PAGE

85

4

[

•

2

~

3

lr
L4

~1

1·

I

GMll(x)_TXCLK_JFIGURE 23. GMII[x]_TXCLK Timing - MII Mode.

2

1,------------+-~

GM ll(x)_MRCLK (input)
GM ll [x]_RXD[3.0], GMll[x ]_ RXDV
GMll[x]_RXER (Inputs) - - - ~I

I

FIGURE 24. GMII[x]_RXD[3:0], GMII[x]_RXDV, GMII[x]_RXER Timing - MII Mode.

GMll(x)_TXCLK (input)
GMll[xLTXD[3.0],
GMll[xLTXER(outputs) - - - - ~FIGURE 25. GMII[x]_TXD[3:0], GMII[x]_TXEN Timing - MII Mode.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

V62/15602

REV

PAGE

86

RMll(x)_REFCLK (input)

FIGURE 26. RMII[x]_REFCLK Timing - RMII Mode.

2
RMll(x)_REFCLK (input)
RMll(x)_Rxd[1.0], RMll[x]_CRS_DV
RM II[ x]_RXER (Inputs)

L _ _____/'------------------____/' - - - - - - - - - - - - - -_ _ 1

FIGURE 27. RMII[x]_RXD[1:0], RMII[x]_CRS_DV, RMII[x]_RXER Timing - RMII Mode.

RMll(x)_REFCLK (input)

RMll(x)_TXD[1 .0],
RMll[x]_TXEN (Outputs)

FIGURE 28. RMII[x]_TXD[1:0], RMII[x]_TXEN Timing - RMII Mode.

3
RGMll[x]_RCLKFIGURE 29. RGMII[x]_RCLK Timing - RGMII Mode.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

V62/15602

REV

PAGE

87

RGMll[x]_RCLK(A) _ _ _ __ _ /~ 1 s t Hal f -byte~-~r~
RGMI I[ x]_RD[ 3.0 ]( 8)RGRXD[3.0]

RGRXD[7:4

RGMll[x]_RCTL(s)RXDVRX ERR[_2_

2nd Half-byt- 3
Notes:A.
B.

RGMII[x]_RCLK must be externally delayed relative to the RGMII[x]_RD[3:0] and RGMII[x]_RCTL signals to meet therespective timing requirements.
Data and control information is received using both edges of the clocks. RGMII[x]_RD[3:0] carries data bits 3-0 on the risingedge of RGMII[x]_RCLK and data bits 7-4 on the falling edge of RGMII[x]_RCLK. Similarly, RGMII[x]_RCTL carries RXDV on
rising edge of RGMII[x]_RCLK and RXERR on falling edge of RGMII[x]_RCLK.
FIGURE 30. RGMII[x]_RD[3:0], RGMII[x]_RCTL Timing - RGMII Mode.

RGMll[x]_TCLKFIGURE 31. RGMII[x]_TCLK Timing - RGMII Mode.

RGMll[x]_ TCLK(A)_I~
RGM 11 [ x]_ TD[ 3.O]( 8 )RGMll[ x]_TCTL(B)----+-t-- 2

1st Half - byte 2nd Ha lf - byte

--~x

TXEN

~I

X

TXERR

X~ - - - '----------X-~X

Notes:A

B.

The EMAC and switch implemented in the AM3358-EP device supports internal delay mode, but timing closure was not
performed for this mode of operation. Therefore, the AM3358-EP device does not support internal delay mode.
Data and control information is transmitted using both edges of the clocks. RGMII[x]_TD[3:0] carries data bits 3-0 on the risingedge of RGMII[x]_TCLK and data bits 7-4 on the falling edge of RGMII[x]_TCLK. Similarly, RGMII[x]_TCTL carries TXEN on
rising edge of RGMII[x]_TCLK and TXERR of falling edge of RGMII[x]_TCLK..
FIGURE 32. RGMII[x]_TD[3:0], RGMII[x]_TCTL Timing - RGMII Mode.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

V62/15602

REV

PAGE

88

gpmc_ elk I

\

h~-

- FO

j\

~ ~ _ ) \ _ _/\_

F2

}'\_
F3

F18

7

\

gpmc_csn [x]IF4gpmc_a[1 O: 1] f{;(, .·~Valid Address-

gpmc _ beO n_ cl e

~
\

F7

F6
F19

gpmc_be1 n

\_

L

F6

--l

I

-~ ~-1
F8

F20

F9

-

7

\

gpmc_ ale

7

'I

F19

I

I

\

+j F10F11-1

gp mc_ oen~HDOgpmc_a d[15:0] .,,·c: _:' ,'.:_::i:(ti':~\\ ~,:".'

F13

gpmc_wait[x]Notes:A.
B.

In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, or 5.
In gpmc_wait[x], x is equal to 0 or 1.

FIGURE 33. GPMC and NOR Flash—Synchronous Single Read—(GpmcFCLKDivider = 0).

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

V62/15602

REV

PAGE

89

gpmc _ clk
gpmc _ csn[x]gpmc_a[ 10:1]
gpmc_beOn_cle
gpmc_be1 n

gpmc_ad[ 15:0]
gpmc_wait[x]Notes:A.
B.

In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, or 5.
In gpmc_wait[x], x is equal to 0 or 1.

FIGURE 34. GPMC and NOR Flash—Synchronous Burst Read—4x16-bit (GpmcFCLKDivider = 0).

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

V62/15602

REV

PAGE

90

gpmc_csn[ x]-----+------+---1-------+---------+---+-----+------+--------

I

F4

1

F6

gpmc _ be1 n

F9 -----,

F6

gpmc_ ale - ~gpmc _ we n

Notes:A.
B.

In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, or 5.
In gpmc_wait[x], x is equal to 0 or 1.

FIGURE 35. GPMC and NOR Flash—Synchronous Burst Write—(GpmcFCLKDivider > 0).

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

V62/15602

REV

PAGE

91

,-rni7q FI
gpmc_c lk

1F2

F3 _

1

gpmc_csn[x]gp mc_beOn_cle

Validgpmc _ be1 n

Validgpmc _ a[27:17]

F77
F?-1

Address
IFS

gpmc _ ad[15:0]

D1

LSB

D2

D3
F9-

1

gpmc_ale
gpmc_ oen
gpmc_wait[x]Notes:A.
B.

In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, or 5.
In gpmc_wait[x], x is equal to 0 or 1.

FIGURE 36. GPMC and Multiplexed NOR Flash—Synchronous Burst Read.

I

I

DLA LAND AND MARITIMECOLUMBUS, OHIO

I

SIZE
A

I

-

CODE IDENT NO.
16236
REV

1

1

DWG NO.

V62/15602
PAGE

92

-

i \ i \ i \ j\_ j\_ ; \ ; \ I \gpmc_clk

I\

I\

L1 F2

; \ j\_ j\_~F3 ~►1

F18

I

I

gpmc_csn[x],►F4Address (MSBl

gpmc_a[27: 17] '2/I?CX,►

gpmc_be1 n-►IF17F6- l 17

X

\

X

I
,►

gpmc_beOn_cle

g pmc_advn_a le

F6

7

X

L.~

~

\

I

I

~

X

Address /LSBl

F14

F14

DO

X
-►

y

~F9 e-►j-►IF15

gpmc_ ad[15:0]

1-------►1F17

F20

gpmc _ wen·,z.1,!YX

I

F17

F17

\

------►1F17

r -F22

I

1·

X~i F15 L 1 F15

D1

D2 Y

D3

F21

gpmc_wait[x]Notes:A.
B.

In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, or 5.
In gpmc_wait[x], x is equal to 0 or 1.

FIGURE 37. GPMC and Multiplexed NOR Flash—Synchronous Burst Write.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

V62/15602

REV

PAGE

93

GPMC_FCLK

gpmc_clk\nJ\nnf'V\JlnnnnnJ\nJ'\f\nnnnf\_
I

I

FAS
FA1
I

I

gpmc_cs n[x]~gpmc_a[1D:1]

. FA9

~

Valid Ad dress
FAD~► FA1D
gpmc _ beDn _ cle

I

\

I

Valid

I

FAD

I

I

gpmc_be1 n\
1-----►1 FA 12

gpmc_advn_ale

I

Valid

L_► FA1D

FA3
I

J
I

FA4
gpmc_oen
gpmc_ad[15:D]

FA 13

I
I

I

~ " '•:;.;: , _ - - - - - - - - - - - - - - - - - - - - - - - - - ~( Data IND ), _ - - ~( Data IND

gpmc_wa it[x]Notes:A.
B.
C.

In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, or 5. In gpmc_wait[x], x is equal to 0 or 1.
FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional
clock cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally sampled by activefunctional clock edge. FA5 value must be stored inside AccessTime register bits field.
GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.

FIGURE 38. GPMC and NOR Flash—Asynchronous Read—Single Word.

DLA LAND AND MARITIMECOLUMBUS, OHIO

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ACODE IDENT NO.
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GPMC_FCLK

gpmc_clk
FAS

FAS
I

FA1

FA1

I

gpmc _ csn [ x],►gpmc_ a[1Q:1]

FAQ

\
I

\

gpmc_be1 n

H FA12

FA1
Address 1~► FA1Q

Valid

I

\

FAQ

I
I

I

Valid

I

\

I

FAQ

I

I

Valid
FAQ

I

I

Valid

L► FA1Q- - FA3

r-

FA9

I

L► FA1Q

gpmc_ adv n_ ale

6

XC"!.\ X

AddressQ~► FA1Q

gpmc_beQn_cle

rr:

FA9

~

I

I

-1

FA3--1-►1FA12

\ J

\

\

FA4

I

FA4

FA13--1

FA13--1

I

gpmc_oen
gpmc_ ad[ 1S:Q]

D

~
\_
_/

¢ ata Up pe}-------c=

gpmc_wait[x]Notes:A.
B.
C.

In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, or 5. In gpmc_wait[x], x is equal to 0 or 1.
FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional
clock cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally sampled by activefunctional clock edge. FA5 value must be stored inside AccessTime register bits field.
GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.

FIGURE 39. GPMC and NOR Flash—Asynchronous Read—32-bit.

DLA LAND AND MARITIMECOLUMBUS, OHIO

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ACODE IDENT NO.
16236

DWG NO.

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GPMC_ FCLK

gpmc_clk

FA20 ------ ~ FA2 □ ------L FA20-►

FA21

I

FA1

I

I

gpmc_csn[x]iFA9gpmc_a[10 :1] ~

Add0

Add 1

~► FA10FAD~► FA10

FAD

Add2

Add3

Ad d4

I

gpmc_be0n_cle
I~,

gpmc_be1 n

I

FA10

gpmc_advn_ale

I

\
FA18
FA13

I
I
~

gpmc_oen
gpmc_ad[ 15:0] ~

~ D3

(D3

I

gpmc _ wait[x]Notes:
A.
B.
C.

D.

In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, or 5. In gpmc_wait[x], x is equal to 0 or 1.
FA21 parameter illustrates amount of time required to internally sample first input page data. It is expressed in number of
GPMC functional clock cycles. From start of read cycle and after FA21 functional clock cycles, first input page data will beinternally sampled by active functional clock edge. FA21 calculation must be stored inside AccessTime register bits field.
FA20 parameter illustrates amount of time required to internally sample successive input page data. It is expressed in number
of GPMC functional clock cycles. After each access to input page data, next input page data will be internally sampled by activefunctional clock edge after FA20 functional clock cycles. FA20 is also the duration of address phases for successive input page
data (excluding first input page data). FA20 value must be stored in PageBurstAccessTime register bits field.
GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.

FIGURE 40. GPMC and NOR Flash—Asynchronous Read—Page Mode 4x16-bit.

DLA LAND AND MARITIMECOLUMBUS, OHIO

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ACODE IDENT NO.
16236

DWG NO.

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gpmc _ fclk

gpmc _ clk
FA1gpmc_csn[x]Val id Ad,::,d-re_s_s__

gpmc_a[10 :1]

FAQ

gpmc_beOn_cle
FAQ - - -gpmc_be1 n

1 FA12
gpmc_advn_a le

___

FA25

gpmc_wenFA29
gpmc_ad[ 15 :0]

Data OUT

gpmc_wait[x]Notes:
A.

In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, or 5. In gpmc_wait[x], x is equal to 0 or 1.

FIGURE 41. GPMC and NOR Flash—Asynchronous Write—Single Word.

SIZE
A

DLA LAND AND MARITIMECOLUMBUS, OHIODWG NO.

V62/15602

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PAGE

~

I

I

I

-■

CODE IDENT NO.
16236
I

97

-I

gpmc_fclk

gpmc_clk
FA1
I

-

FAS
I

I
I

gpmc_csn[x]~►FA9gpmc_a[27: 17] ~gpmc_beQn_cle

gpmc_be1 nAddress (MSB)
I~► FA1Q

FAQ

\

Valid

I
I

~~ FA1Q

FAQ

I

I

\
~►j

gpmc_advn_ale

I

FA12

FA31

\

I

Valid

I

\
FM

FA13

I
I

I

gpmc_oen~►

FA29l►I FA37

gpmc_wait[x]Notes:A.
B.
C.

In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, or 5. In gpmc_wait[x], x is equal to 0 or 1.
FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional
clock cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally sampled by activefunctional clock edge. FA5 value must be stored inside AccessTime register bits field.
GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.

FIGURE 42. GPMC and Multiplexed NOR Flash—Asynchronous Read—Single Word.

DLA LAND AND MARITIMECOLUMBUS, OHIO

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ACODE IDENT NO.
16236

DWG NO.

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gpmc_fclk

gpmc_clk
FA1
gpmc_csn[x]

\

~--

FA9

gpmc_a[27: 17] ~gpmc_beDn_cle

gpmc_be1 nAddress ( MS BJ
FAD

~--

FA1D

~--

FA1D

1
I

\

FAD

\

~►j FA12

gpmc_advn_ale

'

I

I

FA3 1

\

I
FA27
FA25

I

I

I

gpmc_wen, -• FA29

L-, FA28

gpmc_wait[x]------------------------------------------

Notes:
A.

In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, or 5. In gpmc_wait[x], x is equal to 0 or 1.

FIGURE 43. GPMC and Multiplexed NOR Flash—Asynchronous Write—Single Word.

DLA LAND AND MARITIMECOLUMBUS, OHIO

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ACODE IDENT NO.
16236

DWG NO.

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99

GPMC_FCLK
GNF1

GNF6

-

I

GNF2

GNFS

-

'7

gpmc_csn[ x]~gpmc_beOn_cle
gpmc_advn_ale

gpmc_oen
GNFO

gpmc_wen
gpmc_ad[ 15:0]

Notes:
A.

In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, or 5..
FIGURE 44. GPMC and NAND Flash—Command Latch Cycle.

GPMC_FCLK
GNF6

gpmc_csn[ x]gpmc_beOn_cle

I

GNF8

GNF7

gpmc_advn_ale

gpmc_oen
GN F9
GNFO - - -T - - - - - - - -----=_

gpmc_wen
GNF4

gpmc_a d[15 :0]

Notes:
A.

In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, or 5..
FIGURE 45. GPMC and NAND Flash—Address Latch Cycle.

DLA LAND AND MARITIMECOLUMBUS, OHIO

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ACODE IDENT NO.
16236

DWG NO.

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GPMC_FCLKI G N F12~

GNF14

~ ~ GNF10

gpmc_ csn[x]gpmc_beO n_c legpmc_advn_ale

gpmc_oen
gpmc_ad[15:0 ]gpmc_wait[x ]Notes:A.
B.
C.

GNF12 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC
functional clock cycles. From start of read cycle and after GNF12 functional clock cycles, input data will be internally sampled
by active functional clock edge. GNF12 value must be stored inside AccessTime register bits field.
GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, or 5. In gpmc_wait[x], x is equal to 0 or 1.
FIGURE 46. GPMC and NAND Flash—Data Read Cycle.

GPMC_FC LK

1

GNF6

gpmc_csn[x]gpmc _ beOn _ cle

gpmc_advn_ale

gpmc_oen- ---=

GNF9T-----GNFO--

gpmc_wen
GNF4

_

1

gpmc_ad[ 15:0]

Notes:
A.

In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, or 5..
FIGURE 47. GPMC and NAND Flash— Data Write Cycle.
-r

I

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
A

1

CODE IDENT NO.
16236

T

DWG NO.

V62/15602

~

REV
I,

PAGE
I

101

I

DDR_CKDOR CKn

FIGURE 48. LPDDR Memory Interface Clock Timing.

X

A1

t

y
OF FSE T

i

>--

'

w

u

0:::: <(LPDDR
DEV ICEu

LJLL._

~

o._

l

y
OF FSE T

I

A1

I

.

_J

w

I--

z:

-

AM335x•Recom mended LPDDR
Device Orien tation

FIGURE 49. AM3358-EP Device and LPDDR Device Placement.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

V62/15602

REV

PAGE

102

rn
Q)

u

O::'.'.

A

+

0

0
0

1::

_J

C

Q)

o_ -+-uAM335xFIGURE 50. CK and ADDR_CTRL Routing and Topology.

+

I

A1

I

I
I

Q)

DO[O]

I

DO[ 1]

I

u
De:'.

I

0

o
t
0
Q)

0.... -+_JC

I-+
AM335xFIGURE 51. DQS[x] and DQ[x] Routing and Topology.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

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PAGE

103

DDR _ CK

DDR_CKn

FIGURE 52. DDR2 Memory Interface Clock Timing.

....

X

~

r-.

~

A1

t

~~

y

y

i

OF FSET

DD R2
Device

l

+
t

G)

u
0

N tm

O'.:'.

0
0

-+-

C

y
OF FSET

AM335x

A1~~ Recomme nde d DDR2
Device Orientation
FIGURE 53. AM3358-EP Device and DDR2 Device Placement.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

V62/15602

REV

PAGE

104

+

A1

rn

Q)

u

0
Q)
N't::

A

O:'.'.

o

-+-

o

~

+

u

+

AM335 xA1

FIGURE 54. CK and ADDR_CTRL Routing and Topology.

+

A1

r DQ[O]I

r 00[1]
I

(I)

I

u

0

I

N
O:'.'.

t:
(I)

o-+-

I

0

I

C

-+
AM335 xFIGURE 55. DQS[x] and DQ[x] Routing and Topology.

DDR_C K

DDR_C Kn
FIGURE 56. DDR3 Memory Interface Clock Timing.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

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PAGE

105

X1

I

-

X2

+
DDR3
INTERFACE

0

>-'

0

0

'

+ +
~

'

FIGURE 57. Placement Specifications.

0

CACLMY

0

0

Rtt
Vtt

FIGURE 58. CLM for Two Address Loads on One Side of PCB.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

V62/15602

REV

PAGE

106

+

DQ [ 0. 7],DMO,DQSO►1

D0[8: 15],DM 1,DQS 1, -DQLMX1 - - - -----D01i

DQLM Y10

DQLMYO

0ID)

DQO - D01 repesent data bytes 0- 1
Notes:
There are two DQLMs, one for each byte (16-bit interface). Each DQLM is the longest Manhattan distance of the byte; therefore:
DQLM0 = DQLMX0 + DQLMY0
DQLM1 = DQLMX1 + DQLMY1
FIGURE 59. DQLM for Any Number of Allowed DDR3 Devices.

12C[xLSDA
8

14

~

13

~- 5

12C(xLSCL
- 12

~ 3

~- 7

~

~ - .,_ 3

STOP

-

2

REPEATED
START

START

STOP

FIGURE 60. I2C Receive Timing.

DLA LAND AND MARITIMECOLUMBUS, OHIO

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ACODE IDENT NO.
16236

DWG NO.

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107

12C[x]_SDA
21

12C[x]_SCL
~ 18

22

STOP

-

17

REPEATED
START

START

STOP

FIGURE 61. I2C Transmit Timing.

1a
TCK

TDO

FIGURE 62. JTAG Timing.

DLA LAND AND MARITIMECOLUMBUS, OHIO

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ACODE IDENT NO.
16236

DWG NO.

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PAGE

108

W SU 0 to 31) -CS_DELAY(0 to 3)
W_HOLD(1 to 15

W_STROBE(1 to 63)

LCD_MEMORY_CLK

LCD_MEMORY_CLK(E1) - - + - - - - _ _ _ _ L ;LCD_DATA[? :O]

Write Instruction

LCD VSYNC
(RS)

9
10
LCD_HSYNC(R/W)
LCD_AC_BIAS_EN(EO)~_ ___J____ _ _11____L;

Notes:
A.

Hitachi mode performs asynchronous operations that do not require an external LCD_MEMORY_CLK. The first
LCD_MEMORY_CLK waveform is only shown as a reference of the internal clock that sequences the other signals. The second
LCD_MEMORY_CLK waveform is shown as E1 since the LCD_MEMORY_CLK signal is used to implement the E1 function in
Hitachi mode.
FIGURE 63. Command Write in Hitachi Mode.

DLA LAND AND MARITIMECOLUMBUS, OHIO

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ACODE IDENT NO.
16236

DWG NO.

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109

1◄
I

w_su

(0to31)►1➔

W_STROBE(1 to 63)

1

1
I◄
►

I

LCD_MEMORY_CLK

CS_DELAY(Oto 3)
W_HOLD(1to15~_.I ~6I

LCD_MEMORY_CLK
(E 1)

l

\

h
11

\

r--- I------r--4- - -~·, V1-----f~ ----=--------+--~.. I ~ 5

LCD_DATA[7:0]

Write Data

c=--

___.,
LCD_VSYNC(RS)

LCD_HSYNC
(PJW)

r-

____
1

- ~I\ ~ 10

LCD_Ac_sIA\-;0~ _

---~

1

rt 10
I J1t1---+I-

I

--~
1
r
6
~~
~ l1

1lvx -6___1_1_ _ _ _11Notes:
A.

Hitachi mode performs asynchronous operations that do not require an external LCD_MEMORY_CLK. The first
LCD_MEMORY_CLK wavefor m is only shown as a reference of the internal clock that sequences the other signals.The second
LCD_MEMORY_CLK waveform is shown as E1 since the LCD_MEMORY_CLK signal is used to implement the E1 function in
Hitachi mode.
FIGURE 64. Data Write in Hitachi Mode.

DLA LAND AND MARITIMECOLUMBUS, OHIO

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ACODE IDENT NO.
16236

DWG NO.

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PAGE

110

-,

R HOLD(1 to 15)r-

R SU
(0-to 31)__.

R_STROBE(1 to 63)

►'

1◄

_J

._

CS DELAY(0 to 3)~-

LCD- MEMORY- CLK

~

I

6

I

LCD- MEMORY- CLK(E1)Il 1 _J

~17
I

16

I
_.I ~ 15

LCD_DATA[7 :0]
Command-I~- 8

18 - ~_JI

LCD VSYNC
(RS)

I
~

LCD HSYNC(R/W)~ft6 ~-{ 6LCD- AC- BIAS- EN
(E0)

I

-

~

◄- 8

~6

I

I

I

~7

Notes:
A.

Hitachi mode performs asynchronous operations that do not require an external LCD_MEMORY_CLK. The first
LCD_MEMORY_CLK waveform is only shown as a reference of the internal clock that sequences the other signals. The second
LCD_MEMORY_CLK waveform is shown as E1 since the LCD_MEMORY_CLK signal is used to implement the E1 function in
Hitachi mode.
FIGURE 65. Command Read in Hitachi Mode.

DLA LAND AND MARITIMECOLUMBUS, OHIO

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ACODE IDENT NO.
16236

DWG NO.

V62/15602

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111

R SU
- , (0-to 31)

R_HOLD(1to15)r-__.

CS_DELAY(0 to 3)

R_STROBE(1 to 63)I.

~

LCD_MEMORY_CLKI

LCD_MEMORY_CLK
(E1)

I

I

~ IH 6~ 16--C-~ r11
~F

li 6

~7

I
I

I

.{

- 14 I

~

r

15

I

I

LCD_DATA[7:0]
18 -IJIJ~~ead Data

I

I

I

I

LCD_VSYNC(RS)
LCD_HSYNC
(R/W)

I

I

LCD_AC_BIAS_EN
(E0)

I

I

_.
I
t
s
1;r
I

~

I

I

I

~7

Notes:
A.

Hitachi mode performs asynchronous operations that do not require an external LCD_MEMORY_CLK. The first
LCD_MEMORY_CLK waveform is only shown as a reference of the internal clock that sequences the other signals. The second
LCD_MEMORY_CLK waveform is shown as E1 since the LCD_MEMORY_CLK signal is used to implement the E1 function in
Hitachi mode.
FIGURE 66. Data Read in Hitachi Mode.

DLA LAND AND MARITIMECOLUMBUS, OHIO

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ACODE IDENT NO.
16236

DWG NO.

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PAGE

112

W_HOLD(1-15)

w_su(0-31)

I◄

►I

~~

I

-.I W_STROBE◄I(1-63)-----.: CS_DELAYI

CS_DELAY
(0-3)

◄-

~-

I

(0- 3)II

LCD_MEMORY_CLK(MCLK) Sync ModeIr'~;I {◄~----+--------+---------f'~

LCD_MEMORY_CLK(CS1) Async ModeLCD_DATA[15:0]

LCD_AC_BIAS_EN(CSO)

LCD_VSYNC(ALE)

LCD_HSYNC(DIR)

LCD_PCLK(EN)

Notes:A.

Motorola mode can be configured to perform asynchronous operations or synchronous operations. When configured inasynchronous mode, LCD_MEMORY_CLK is not required, so it performs the CS1 function. When configured in synchronousmode, LCD_MEMORY_CLK performs the MCLK function. LCD_MEMORY_CLK is also shown as a reference of the internal
clock that sequences the other signals..
FIGURE 67. Micro-Interface Graphic Display Motorola Write.

DLA LAND AND MARITIMECOLUMBUS, OHIO

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ACODE IDENT NO.
16236

DWG NO.

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PAGE

113

W_HOLD(1-15)

w_su(0-31)~ W_STROBE

2(1-63)II~

CS_DELAY
(0-3)

I

I

I )) III

R_STROBE(1-63)

6

19

6

- ~

(~

I

I

61

:x

Wri•Address:\ I- ~ 1.~- 6- ~ -➔,c□-~:;
LCO_HSYNC
(DIR)

~_ 6

1,

I ========

Data

I

6

6

I

7

~~a

7
J
~ r-

-~1.-a

l

1
➔l~

10

:I-\.

~
~ ~- 12

LCD_PCLK
(EN)

Read

_J ~

I
-~~~7~I~~----1------------'--~--1___j_l"l _(____III ()~~I~~----11------11-------+
_1~
6

(CSO)

1,

~

I18

._

LCD_AC_BIAS_EN

1.-

J----+-----+V

1\

20

CS_DELAY
(0-3)

)

7

_ft

~

.
I
_

I

1.1.l
)
I ~--+----+--~--+I"
I I ~+-I
j r-,_J-~ ' I J ◄ "-~LCD_DATJ>115,~

r ._

~-►I

~~
._
I
~

LCD_MEMORY_CLK(MCLK) Sync ModeLCD MEMORY CLK(C-S1) Async Mode

R_HOLD(1-15)

R_SU(0-31)t~- - - -~
- It

- , ~- 11

\

9

I

I

r )

I

I

I

I

I

I

I

10
I

11

)

I
1

1

13

I

I

--►1 rl _12 -~~ ~- 121-~-I_ _ _)(\--) ~-\~------

Notes:A.

Motorola mode can be configured to perform asynchronous operations or synchronous operations. When configured inasynchronous mode, LCD_MEMORY_CLK is not required, so it performs the CS1 function. When configured in synchronousmode, LCD_MEMORY_CLK performs the MCLK function. LCD_MEMORY_CLK is also shown as a reference of the internal
clock that sequences the other signals.
FIGURE 68. Micro-Interface Graphic Display Motorola Read.

DLA LAND AND MARITIMECOLUMBUS, OHIO

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DWG NO.

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PAGE

114

R_SU
(0-31)

1~ _ i,( _

~

I

2 -►

~I

~

1

1◄

R_HOLD(1-15)

►I

I

...
I
----ri CS_DELAY . _~ I R_STROBE ◄~- 3(1-63)
I

I

(0-3)

I

I

LCD_MEMORY_CLK(MCLK) Sync ModeI-►i ◄- 19-

LCD_MEMORY_CLK(CS1) Async Mode~1◄- 6 1IIi
I~-►i I◄- 7

I

I

I

I

h'

_;I LJ-1Jl ◄~-6 ___j__l-

I

fl

I

_J ._,.I 16 ~

.

- 1,

I

J

1._- 1s_--+-I-

LCD_DATA[15:0)
I 18

LCD_AC_BIAS_EN(CSO)

LCD_VSYNC
(ALE)

Read
StatusI

1_----+-_____µ-,It 'JTT◄- 7 1
6

_Jr-a

I

1-----1-J l◄_-a__I

j ._,:I/

LCD_HSYNC(DIR)

Notes:A.

Motorola mode can be configured to perform asynchronous operations or synchronous operations. When configured inasynchronous mode, LCD_MEMORY_CLK is not required, so it performs the CS1 function. When configured in synchronousmode, LCD_MEMORY_CLK performs the MCLK function. LCD_MEMORY_CLK is also shown as a reference of the internal
clock that sequences the other signals.
FIGURE 69. Micro-Interface Graphic Display Motorola Status.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

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PAGE

115

w_su

W_HOLD(1-15)(0-31)

►I

~I
I

2

LCD_MEMORY_CLK(MCLK) Sync ModeI-► ~LCD MEMORY CLK(CS 1) Async Mode~~

W_STROBE(1-63)

6

I._~ CS_DELAY ~
(0-3)
I
)
)
I
I 1.- 6

LCD_DATJ'q15r~

t4~

Write Address' k- 20

7

I---.11. -6
11

8

8

I

LCD_AC_BIAS_EN(CSO)_. r- 6
•~
I

_.
r7
I

LCD_VSYNC(ALE)~_. I._
f~ ._ 9~LCD_HSYNC
(WS)

if

5

r- 10 _. r,= 10
If
I

11

(0-31)

►I
~►1

r-~
I

I

CS_DELAY
(0-3)

I

1.I

- 1 1. - 6
6

11

Sr·

-J I._ 5

~ I

1:r

()

r◄-►i

W_STROBE(1 -63)

I

', -r

t

' ~7

-►I

i◄

~

I

W_HOLD(1-15)w_su

I~I

Write Data

- , 1. -6

I

I
I
ss
I
I
())
I
I

11
I
I
I
-► r- 10_.I1.-101
I;
I

t

LCD_PCLK(RS)

Notes:A.

Intel mode can be configured to perform asynchronous operations or synchronous operations. When configured inasynchronous mode, LCD_MEMORY_CLK is not required, so it performs the CS1 function. When configured in synchronousmode, LCD_MEMORY_CLK performs the MCLK function. LCD_MEMORY_CLK is also shown as a reference of the internal
clock that sequences the other signals.
FIGURE 70. Micro-Interface Graphic Display Intel Write.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

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PAGE

116

w_su
(0-31)

1

1 ◄ -----►i ◄ ---►1

2_.~/1~LCD_MEMORY_CLK(CS1) Async Mode

-

I

~~

~►I

LCD_DATA[15:0]-►-i i

R_STROBE(1-63)(1-15)►I-1 CS_DELAYi◄-

1 f1◄ 6----+-----+------+"I6-

r~ 4--+-----+---~----til--r ,-~_-

~r-

I

r-s

I

<) ~ll◄- 6r ◄- 19-, 1 ◄--6
I I ~+----1----~ITI

1/◄-~5---+1------\,. ~ -◄---+-t- 16 - -rl~r- 17 ~ 1 ◄-15

1 r,-

,.J

j -)

_ w_rit_e A_dd_
res_s - ~
I

I
I
I
I

I )

() ~r-

I_JTT◄- 7
I )
~
~
I( I
LCD_VSYNC(ALE) ~~
lf--------\1) I
9_J , - 10 _j i◄-10 I
1
1
I
I~
If I
I
LCD_HSYNC(WS)
I-~~~ 11 --------rl I
I
6

~

(0-3)
I

I

2_0 _

LCD_AC_BIAS_EN
(CSO)

I◄

(0-3)

~- 7

- .1

R_HOLD

I

l
I

R_SU
(0-31)_.I w_~::3~BE I◄--1 CS_DELAY ~3

I

LCD_MEMORY_CLK(MCLK) Sync Mode

W_HOLD(1-15)

6i'~-sw •~~--~~

I
I
I
I

6

i\

_. 1;-6----+---

1

1

1()\---+-----+-------+-------+--

LCD_PCLK(RS)

I~1 f - - - ~-~--~--~-~--'--------'s<\)--~~-'r, r,~-~~ ~ 13
Notes:A.

Intel mode can be configured to perform asynchronous operations or synchronous operations. When configured inasynchronous mode, LCD_MEMORY_CLK is not required, so it performs the CS1 function. When configured in synchronousmode, LCD_MEMORY_CLK performs the MCLK function. LCD_MEMORY_CLK is also shown as a reference of the internal
clock that sequences the other signals.
FIGURE 71. Micro-Interface Graphic Display Intel Read.

DLA LAND AND MARITIMECOLUMBUS, OHIO

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ACODE IDENT NO.
16236

DWG NO.

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PAGE

117

R_SU
(0-31)

1◄-IJ,>j

R_HOLD(1-15)►~~1-+ R STROBE~LCD_MEMORY_CLK(MCLK) Sync ModeLCD_MEMORY_CLK(CS1) Async Mode

- 3 1 -(1-63)
I

I

~1.-

I_..,

-

61

Jl,,

CS_DELAY
(0-3)

~

19
-

1
.-

I

I

I

I

,

I ◄- 6

1f

I
I
I

-►

LCD_DATA[15:0)►
Read
Status

I 1a

I

I

I

- , b= 6

4-~,.

I

If

~r-- a lI-~r,=a

I

If

I

I

I

LCD_VSYNC
(ALE)

►1

I. _

I

_J ◄-14 1 16

LCD_AC_BIAS_EN
(CSO)

I◄

~r-

6

10
_,~,,
I

I

LCD_HSYNC(WS)
I- ~ ~ - 12
LCD_PCLK(RS)~ ~ 12It~ \13

Notes:A.

Intel mode can be configured to perform asynchronous operations or synchronous operations. When configured inasynchronous mode, LCD_MEMORY_CLK is not required, so it performs the CS1 function. When configured in synchronousmode, LCD_MEMORY_CLK performs the MCLK function. LCD_MEMORY_CLK is also shown as a reference of the internal
clock that sequences the other signals.
FIGURE 72. Micro-Interface Graphic Display Intel Status.

DLA LAND AND MARITIMECOLUMBUS, OHIO

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ACODE IDENT NO.
16236

DWG NO.

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PAGE

118

Frame Time

VSW

VBP

LPP_B10+LPP(Oto255)(1 to64).. 1..
I(1 to2048)

VFP

.,1,.

VSW

(0 to 255)

I

(1 to64)

LCD_HSYNC

LCD_VSYNC

LCD_DATA[23:0]

P, L-1

P, L

7J

LCD_AC_BIAS_EN(ACTVID)~rl

LCD_HSYNC

LCD_PCLK~I

LCD_DATA[23:0]

I~
I

LCD_AC_BIAS_EN(ACTVID)

I
I"

I

7

PPLMSB+PPLLSB

HFP

HSW

HBP

PPLMSB+PPLLSB

16 X (1 to 2048)(1 to256)(1 to64)(1 to256)

16 X (1 to 2048)

Line 1I

Line 2

FIGURE 73. LCD Raster-Mode Active.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

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PAGE

119

FRAME TIMELPP_B10+LPP

VBP = 0 I
VFP=0 -◄
VSW=1
I

(1 to 2048)~
TIME

LCD_HSYNC

LCD_VSYNC.----------'
1, L

DATA

LCD_DATA[7:0]
1, L-1
P, L-1Ir.------'I

LCD_AC_BIAS_EN

-- --

_J_I

r

~

L.

--

(

I

L

-I

,

~

I

ACB
(0 to 255)

I

I

ACB

- 1-

(0 to255)

~

I

I..
I

I

7

H
r
it'
"
:f
I

LCD_HSYNC

;)

11

I

nnn

LCD_PCLK

I

I

□

I

nrin

Af1-

I

I

½
\~

LCD_DATA[7:0]

PPLMSB+PPLLSB◄

16 X (1 to 2048)
Line 1

,

I

I

I

I

. . ·. · .....

,
I

HFP

HSW

I

I

(1 to256)(1 to64)I(1 to256)

◄

P, 6

HBP

~
I

r

PPLMSB+PPLLSB
16 X (1 to 2048)
Line2

~

Notes:A.

The dashed portion of LCD_PCLK is only shown as a reference of the internal clock that sequences the other signals.
FIGURE 74. LCD Raster-Mode Passive.

DLA LAND AND MARITIMECOLUMBUS, OHIO

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ACODE IDENT NO.
16236

DWG NO.

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120

LCD_AC_BIAS_EN------------'(\--_ ______- -_;. r-6---~~\-----)-h~- 7lf

I-

LCD_VSYNC
I

9L► 1 - 10

LJ - 10

LCD_HSYNC

8_ _ _ __ _ _ ' , ( ) \ - - - - -I I~------"'I
I l~---------C;-------------------'\--------I------J1 11
I

r,

r,

LCD_PCLK(passive mode)

I

\

I

\

.-~1

I

1

I

2

l. _ 1 3),,l r'1 r'1 Jr,i r,
I

n n
yUIL_

I

I

~

LCD_DATA[7:0](passive mode)

I

I

I

I

I

I

I

I

I

I

LCD_PCLK(active mode)I

LCD_DATA[23:0](active mode)

PPLMSB+PPLLSB

HFP

HSW

16 X (1 to 2048)(1 to 256)

(1 to64)◄I

HBP(1 to 256)

►I
1

I◄

Line LPPLMSB+PPLLSB
16 X (1 to 2048)
LINE 1 (Passive Only)

Notes:A.

The dashed portion of LCD_PCLK is only shown as a reference of the internal clock that sequences the other signals.
FIGURE 75. LCD Raster-Mode Control Signal Activation.

DLA LAND AND MARITIMECOLUMBUS, OHIO

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ACODE IDENT NO.
16236

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121

LCD_AC_BIAS_EN

LCD_VSYNC

__.

- 10

- 10

LCD_HSYNC

2

J.-

I

1

I

3
/\

LCD_PCLK(passive mode)

I

/\

/\

I

I

I

/\

I

/\

I

I

/\

I

/\

I

LCD_DATA[7:0](passive mode)

LCD_PCLK(active mode)

LCD_DATA[23:0](active mode)
VBP=0
VFP=0
VWS= 1PPLMSB+PPLLSB

HFP

HSW

PPLMSB+PPLLSB

16 X (1 to 2048)(1 to 256)

(1 to 64)

16 X (1 to 2048)

Line 1

LINE 1 for active
Line 2 for passive

Notes:A.

The dashed portion of LCD_PCLK is only shown as a reference of the internal clock that sequences the other signals.
FIGURE 76. LCD Raster-Mode Control Signal Deactivation.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

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122

McASP[xLACLKR/X (Falling Edge Polarity)

McASP[xLAHCLKR/X (Rising Edge Polarity)

McASP[xLACLKR/X (CLKRP = CLKXP = 0) (Al

McASP[xLACLKR/X (CLKRP = CLKXP = 1) (Bl

_J
5

~

McASP[xLAFSR/X (Bit Width, 0 Bit Delay)------McASP[xLAFSR/X (Bit Width, 1 Bit Delay)I- 6-~<>_,,__<)_ _ _ _ _ _______,,_<))~--~~-I

McASP[xLAFSR/X (Bit Width, 2 Bit Delay)

McASP[xLAFSR/X (Slot Width, 0 Bit Delay)
McASP[xLAFSR/X (Slot Width, 1 Bit Delay)

McASP[xLAFSR/X (Slot Width, 2 Bit Delay)

7
McASP[xLAXR[x] (Data In/Receive)
AO

A1

A30 A31BO

B1

B30 B31

CO

C1

C2

C3

C31

Notes:A.
B.

For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP receiver isconfigured for falling edge (to shift data in).
For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP receiver isconfigured for rising edge (to shift data in).
FIGURE 77. McASP Input Timing.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

V62/15602

REV

PAGE

123

9
McASP[xLACLKR/X (Falling Edge Polarity)
McASP[xLAHCLKR/X (Rising Edge Polarity)

McASP[xLACLKR/X (CLKRP = CLKXP = 1) (Al

McASP[xLACLKR/X (CLKRP = CLKXP = 0) (bl

McASP[xLAFSR/X (Bit Width, 0 Bit Delay)
McASP[xLAFSR/X (Bit Width, 1 Bit Delay)
McASP[xLAFSR/X (Bit Width, 2 Bit Delay)

McASP[xLAFSR/X (Slot Width, 0 Bit Delay)
McASP[xLAFSR/X (Slot Width, 1 Bil Delay)
McASP[xLAFSR/X (Slot Width, 2 Bil Delay)

McASP[x]_AXR[x] (Data Out/Transmit)

15

AO

A1

A30 A31BO

B1

B30 B31

CO

C1

C2

C3

C31

Notes:A.
B.

For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP receiver isconfigured for rising edge (to shift data in).
For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP receiver isconfigured for falling edge (to shift data in).
FIGURE 78. McASP Output Timing

DLA LAND AND MARITIMECOLUMBUS, OHIO

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ACODE IDENT NO.
16236

DWG NO.

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REV

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124

PHA=0
EPOL=1n,

SPI_CS[x] (in)SPI_SCLK (in)

POL=0

l

~

~

k➔,

POL=1
SPI_SCLK (in)

- 5~

0

BITn-2

SPI_D[x] (SIMO, In)

BITn-30

BITn-4

0

BIT0

)

PHA=1
EPOL=1SPI_CS[x] (in)SPI_SCLK (in)

POL=0

l ~.
I

rr1 ,
I

I"

tit- 2

9

►

2
3

POL=1
SPI_SCLK (in)SPI_D(x] (SIMO, In)5~

BIT n-2

D

BITn-3

D

BIT1

D

BIT0

FIGURE 79. SPI Slave Mode Receive Timing.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

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125

PHA=0
EPOL=1SPI_CS[x] (in) - - - - - -i ◄ -- 9-8►

SPI_SCLK (in) _POL=O_ _ _ ___J___;

POL=1
SPI_SCLK (in) _ _ _ _ ___J___ _~ 7
SPI_D[x] (SOMI, out) - - - - - - ~ ( -----cB=IT-n--1-,---------~~

BIT n-2r-6'/J

BIT n-3

1v1vV

BIT n-4 '/J

BIT0),---------

PHA=1
EPOL=1SPI_CS[x] (in)

POL=0

I

n1 ,

8

SPI_SCLK (in)

9

1◄

j

- 1
2
POL=1
SPI_SCLK (in)~~ 6
SPI_D[x] (SOMI, In) - - - - - - - - -(---i

BIT n-1

r-6
O ~ B=IT-n--2-~6~ ----'--'-__..,__0
-I
~"--'

BIT1

0

BIT0

)i---------FIGURE 80. SPI Slave Mode Transmit Timing.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

V62/15602

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126

PHA=0
EPOL=1SPI_CS[x) (Out)IPl'~ i, 1'8

POL=0
SPI_SCLK (Out)POL=1
SPI_SCLK (Out)

BITn-3

SPI_D[x) (SOMI, in)

'/J

'◄

~ 9

I

BIT1

'/J

BIT0

)

PHA=1
EPOL=1SPI_CS[x] (Out)SPI_SCLK (Out)

POL=0

l

►I

r 'r,t8Il~►j- 2

3

~ 5 ----.I
I
B-IT-n--2 -'/J

BIT n-3~L

POL=1
SPI_SCLK (Out)-SPI_D[x) (SOMI, In)

'/J

BIT 1

'/J

BIT 0

)>-------FIGURE 81. SPI Master Mode Receive Timing.

DLA LAND AND MARITIMECOLUMBUS, OHIO

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ACODE IDENT NO.
16236

DWG NO.

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127

SPI_CS[x) (Out)

PHA=0
EPOL=1!

~ 3: 28
SPI_SCLK (Out)

~L

POL=0

POL=1
SPI_SCLK (Out)

r-s

.,_ 7
SPI_D[x] (SIMO, Out)------~(

BITn-1U

PHA=1
EPOL=1SPI_CS[x) (Out)SPI_SCLK (Out)

POL=0

r

BIT0

BITn-2

w, 1,

8

I

~-L

t=·:t,

POL=1)>---------SPI_SCLK (Out)SPI_D[x) (SIMO, Out)~6 -., r-6(

BITn-1

xx

BIT1

YJ

BIT0

)

FIGURE 82. SPI Master Mode Transmit Timing.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

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128

2

MMC[xLCLK (Output)

MMC[xLCMD (Input)

MMC[xLDAT[7:0] (INPUTS)

3-----r

4
FIGURE 83. MMC[x]_CMD and MMC[x]_DAT[7:0] Input Timing.

s- -

61
~-7-,,II◄_

1

RMll[xLREFCLK(Input)►'1

I

FIGURE 84. MMC[x]_CLK Timing.

10
MMC[xLCLK (Outputs)

MMC[x]_CMD (Outputs)

MMC[x]_DAT[7:0] (Outputs)

11 - - - -r

FIGURE 85. MMC[x]_CMD and MMC[x]_DAT[7:0] Output Timing—Standard Mode.)

DLA LAND AND MARITIMECOLUMBUS, OHIO

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ACODE IDENT NO.
16236

DWG NO.

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129

1◄

12

I◄

13

MMC[xLCLK (Outputs)

MMC[xLCMD (Outputs)

MMC[x]_DAT[7:0] (Outputs)

FIGURE 86. MMC[x]_CMD and MMC[x]_DAT[7:0] Output Timing—High Speed Mode.)I◄
GPl[m:O]--, r-

►I

I

i:r

r

X

-►1 3 ~ -2

FIGURE 87. PRU-ICSS PRU Direct Input Timing.

I◄-, r-2►I

Ir

GPO(n:0( 7 e

X

~ 3k-

FIGURE 88. PRU-ICSS PRU Direct Output Timing.

DLA LAND AND MARITIMECOLUMBUS, OHIO

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ACODE IDENT NO.
16236

DWG NO.

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130

FIGURE 89. PRU-ICSS PRU Parallel Capture Timing - Rising Edge Mode.

I◄

1

CLOCKIN►I

r-2 )~- 3==:,~~I~ ~ 4 ~ ~ 5

\

V

I

DATAIN
I I

~~~◄

7

- ~

~8

FIGURE 90. PRU-ICSS PRU Parallel Capture Timing - Falling Edge Mode.

DATAINFIGURE 91. PRU-ICSS PRU Shift In Timing.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

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131

I

CLOCKOUT

►I

1

C-- 2

►I

- ~ ~- 4j
1~

DATAOUT

~ ~3

~

~

I I

I I

~5~

~ ~- 6
FIGURE 92. PRU-ICSS PRU Shift Out Timing.

-

2-'

MDIO_CLK (Output)

MDIO_DATA (Input)

FIGURE 93. PRU-ICSS MDIO_DATA Timing - Input Mode.

:◄

1 -----►I

4~

~2~

I

~ 3~

l~~I

l~~I

I

~-

I

l,~~I, I

MDIO_CLK

I

I

~

~4

FIGURE 94. PRU-ICSS MDIO_CLK Timing.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

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►'

MDIO_CLK (Output)

MDIO_DATA (Output)

FIGURE 95. PRU-ICSS MDIO_DATA Timing – Output Mode.

I◄

~ 2~

1 ----►I

~

4~

~ 3~
I I
l~~I
lr--~11I

l~-~I
MII_RXCLK

I

I

-►I

~

4

FIGURE 96. PRU-ICSS MII_RXCLK Timing.

I◄

1 ----►I

4~

I+ -- 2 -►1

I

~ 3~

l~~I

l~~I

~-

I I

l,~-~1,1

MII_TXCLK

I

I

~

~4

FIGURE 97. PRU-ICSS MII_TXCLK Timing.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

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133

~ 2~
I

I

MII_MRCLK (Input)
MII_RXD[3:0]
MII_RXDV,MII_RXER (Input)

FIGURE 98. PRU-ICSS MII_RXD[3:0], MII_RXDV, and MII_RXER Timing.

MIi_TXCLK (Input)
MII_TXD[3:0]
MII_TXER (Output)

FIGURE 99. PRU-ICSS MII_TXD[3:0], MII_TXEN Timing. )

►1

I◄

I

3
!◄

I

2

Start
Bit

UART TXD

Data Bits
I◄

►II

I

5
~

►1

I

UART_RXD

Start
Bit

4

I

Data Bits
FIGURE 100. PRU-ICSS UART Timing.

DLA LAND AND MARITIMECOLUMBUS, OHIO

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ACODE IDENT NO.
16236

DWG NO.

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134

I◄

►II

2
I◄

I

Start
Bit

UARTx_TXD

►I

I

2

I

I◄

►II

j( 7

2

I

Stop Bits

Data Bits
►II

I◄

3

1◄

I

I

UARTx_RXD

Start
Bit

►1

I

I

Data Bits

3

I◄

~

►I

3

I

/

Stop Bits

FIGURE 101. UART Timing.

I◄

►I ◄

Pulse Duration

Pulse Duration

►I

I

I

I

I

I

I

I

I

I

I

I

I

50%

50%

50%

FIGURE 102. UART IrDA Pulse Parameters.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
ACODE IDENT NO.
16236

DWG NO.

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135

4. VERIFICATION
4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as
indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices,classification, packaging, and labeling of moisture sensitive devices, as applicable.
5. PREPARATION FOR DELIVERY
5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial
practices for electrostatic discharge sensitive devices.
6. NOTES
6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum.
6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book.
The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided.
6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee ofpresent or continued availability as a source of supply for the item. DLA Land and Maritime maintains an online database of all current
sources of supply at https://landandmaritimeapps.dla.mil/programs/smcr/default.aspx

Vendor item drawing
administrative control
number 1/

I V62/15602-01XF
- _
2/ I

Devicemanufacturer
CAGE code

Vendor part number

Device Marking

24355

AM3358BGCZA80EP

M3358BGCZA80EP

1/ The vendor item drawing establishes an administrative control number for identifying the item on theengineering documentation.
2/ Devices listed on this drawing are supplied to lead finish “F”. The solder ball material contains
compositions of Sn = 63%,, Pb = 34.5, Ag = 2% and Sb = 0.5 %.

CAGE code
01295

DLA LAND AND MARITIMECOLUMBUS, OHIO

Source of supply
Texas Instruments, Inc.
Semiconductor Group
8505 Forest Lane
P.O. Box 660199
Dallas, TX 75243

SIZE
A

CODE IDENT NO.
16236

DWG NO.

V62/15602

REV

PAGE

136