Multi-layer Silicon MEMS Processes and Devices
Detailed MEMS Examples for Smart Systems

Collin Twanow
Vice President of Engineering

April 23rd, 2014

Outline•Micralyne Introduction•MEMS in Optical Telecom Smart Systems•

Variable Optical Attenuator (VOA)•

VOA MEMS Fabrication Method•MEMS Sensors for Smart Automotive and Medical Imaging Systems•

Capacitive Micro-machined Ultrasonic Transducer (CMUT) Fabrication•Summary

Goal: To provide a the audience with a component level view of
two example of MEMS devices used in smart systems.

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Micralyne Introduction

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Smart Optical Communication Systems•••

Stable fiber optic communication requires management of multiple wavelengthsof light to fully utilize fiber capacity.
Attenuation during transmission and amplification to not occur uniformly over allwavelengths.
Other functions such a remote power control and wavelength switching are alsoneeded within the network.

Wavelength Division Multiplexing (WDM)

Erbium Doped Fiber Amplifier Gain

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Variable Optical Attenuator (VOA)• Network component that can be used forwavelength management (one VOA perchannel), on/off switching, or whole signal
attenuation.
• MEMS mirror can operate in the range from 0 to20 volts depending on the MEMS and systemdesign. Typically 0 to 20V and 0 to 5V versions.
Output Fiber

Output Fiber~45 dB

0.8 dB

Full attenuation

Insertion Loss

Input Fiber

Tilting MEMS Mirror

Low Attenuation
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Input FiberHigh Attenuation

VOA MEMS Example

VOA MEMS Mirror

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Voltage vs. Tilt Characteristics

Vertical Comb Drive Actuator•Uses electro-static force to tilt mirror on a silicon torsional hinge•

Vertical comb drives:» are more efficient than parallel plate actuators» provide better actuation characteristics than simple parallel plateactuators

Comb Drive Ends7

Key Process Technologies•

Deep Reactive Ion Etching for high aspect ratio bulk machining of silicon»»Multi-height structure defined in single layer of silicon
Top surface remains bondable•

Aligned wafer Si-Si fusion bonding•

Stepper lithography»•

Non-contact for low defect count. Alignment of out-of-plane layers to within 0.4 µm

Low stress metallization (TiW/Au)»Enables metalized membranes with low stress

Acoustic image of bonded wafer8Mirror with better than 1.5 m ROC

MicraGEM-Si™ MEMS Process Flow9•

VOAs can be made with the following process•

MicraGEM-Si™ is a silicon-on-insulator based MEMS process
for devices such as micro mirrors, optical switches,
resonators, inertial and bio sensors•

The technology includes:»Two thick SOI structure layers with bulk micromachining»

Deep etch features on the upper and lower devices layers arealigned with sufficient accuracy to enable vertical comb drivestructures»Upper and lower devices layers are connected electrically throughthe bond interface allowing 3D routing of electrical signals»

Low stress gold metallization on the top surface is suited for highlyreflective mirrors as well as contact pads for gold wire bondingProcess Overview - Generalized Cross-Section
Z – Top Wafer Frontside

Top Wafer Device Layer, 30 µm0.01-0.02 ohm-cm

Y – Top Wafer Backside

Base Wafer Device Layer, 50 µm

B – Base Wafer Device Layer

0.01-0.02 ohm-cm

Base Wafer Handle
500 um thickness

Light Blue – Oxide
Grey – Silicon
Yellow – Lowstress metal

1-100 ohm-cm resistivity
A – Base Wafer Backside
Major Process Steps
Step 1 – Define and etch silicon structure in the Base Wafer device layer (B)Step 2 – Define and etch Top Wafer backside (Y)Step 3 – Bond Base Wafer to Top Wafer
Step 4 – Remove Top SOI handle and buried oxide
Step 5 – Deposit low stress metal on Top Wafer fronside (Z), pattern metal
Step 6 – Pattern and etch Top Wafer device layer to release structures
Step 7 – Dicing

10Step 1 – Pattern and Etch Base Wafer
Bond surface•Define Trench 1, Trench 2 and Trench 3regions»Trench 1 – regions etched 50 µm,
all the way to the buried oxide»Trench 2 – regions etched 35 +/- 2µm, leaving a 15 µm silicon featureon the buried oxide»

11Trench 3 – regions etched 10 +/- 1µm , leaving a 40 µm silicon featureon the buried oxide

Trench 3
Trench 1Trench 2

Multi-layer Etched Base Wafer

Bond surface

12Confidential

Step 2 – Define and Etch Top SOI Wafer Backside

Bond surface•Define Top SOI Wafer Backside etch»

Etch depth is 20 +/- 1 µm»

Min feature is 1.5 µm line, 1.5 µmspace»

In the final structure, the regions
etched here will be left as a 10 µm
membraneY13

Step 3 – Bond Base Wafer to Top Wafer
Bond interface•

Bottom and Top Wafers are aligned andfusion bonded in a controlledenvironment (under vacuum)»

Post bond alignment accuracy is +/10 µm»

The bond is mechanical, but also
provides electrical connection
between the two layers of silicon

Bond accuracy is +/- 10 µm

14Step 4 – Remove Top SOI Handle and Buried Oxide

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The Top Wafer SOI handle is removed
with a grind and polish process•

The exposed buried oxide is strippedleaving a pristine optically flat siliconsurfaceStep 5 – Deposit and Define Metal

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The top device layer is blanket coatedwith a low stress TiW/Au metallization.
The residual metal stress is 40-140 MPa.

•The metal is then patterned to form
device elements such as electrodes,
bond pads and highly reflective surfaces.
This is also the recommended layer toput labels.

Step 6 – Release Patterning and Etching

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The final DRIE process etches completely
through the 30 µm thick Top device layer andreleases the MEMS structures•

During this process, features in the lower layers
will be exposed to over-etching when the etchbreaks through and before all features are
etched to completion. In general, very widefeatures will open first, while high aspect ratio
features will open last.

•

The accuracy of this pattern is with 0.4 µm ofthe base device layer pattern•

Step 7: Dicing

MEMS Sensors for Smart Automobile Systems•

A variety of technologies are available for sensing the surroundings of vehicles toallow autonomous driving (adaptive cruise control, park assist) and increased safety(lane change warnings, crash avoidance).

•Safety regulation has accelerated the progress of these systems.
»CMUT devices made using MEMS technology and will offer multi-frequency arrays as wellas superior acoustic coupling.

Source: US Government http://www.nhtsa.gov

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Sensors for Medical Imaging•

Presently 2D images are made by clinical operators moving ahand held wand containing one linear array of piezoelectric
ultrasonic transducers over the surface of the patient and one
frequency is used.

•Capacitive Micro-machined Ultrasonic Transducers (CMUT) offer the ability to use
multiple frequencies and a 2D array of elements to image higher resolution and in
three dimensions.
»19This gives the ability to move from crude images to real time topographical images.

Capacitive Micro-machined Ultrasound Transducers

CMUT technology offers many potential
advantages over traditional linear arraypiezoelectric transducer technology, including:•Advantages of wafer fabrication scale•
2D arrays offer higher resolution•
Greater sensitivity•
Superior acoustic impedance matching•
Potential to co-integrate with electronics•
Choice of frequencies of interest possible
with just a change in geometry

Bonded double SOI process cross section - three devices

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CMUT Systems••••

CMUT technology provides MHz sound wave generation anddetection
Predictive modeling algorithms to design for specific frequencies
CMUT devices allow for a simpler interface with drive electronics
compared to piezoelectric transducers
Electronic and acoustic testing have verified model results

Model outputs and test systems used with Micralyne’s academic development partner.
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Summary• Two important Smart Systems MEMS devices were presented.
• Both can be fabricated with different versions of a multi-layer siliconprocess flow.
• MEMS components are a key element in the design of smart
systems, because they sense and interact with the world around us.

22Thank you

Questions?
Collin Twanow
Vice President of Engineering
Acting VP Sales & Marketing
collin@micralyne.com
1-780-431-4409

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