REVISIONSLTR

DESCRIPTIONDATE (YR-MO-DA)APPROVED

A

Change terminal number on XD[14] to XD[0] in section 6.7. Update boilerplate
to current MIL-PRF-38535 requirements. - PHN

18-08-24

Thomas M. HessB

Update the boilerplate paragraphs to the current MIL-PRF-38535 requirements.
- TTM

24-05-07

Muhammad A. Akbar

REV

B

B

B

B

B

B

B

B

SHEET

75

76

77

78

79

80

81

82

REV

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

SHEET

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

REV

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

SHEET

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

REV

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

B

SHEET

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

REV

B

B

B

B

B

B

B

B

B

B

B

B

B

B

OF SHEETS

SHEET

1

2

3

4

5

6

7

8

9

10

11

12

13

14

PMIC N/A

PREPARED BY

REV STATUS

DLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
https://www.dla.mil/LandandMaritime

Charles F. Saffle

STANDARD
MICROCIRCUITDRAWINGCHECKED BYCharles F. Saffle
APPROVED BY
Thomas M. Hess

THIS DRAWING IS AVAILABLEFOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSEDRAWING APPROVAL DATEMICROCIRCUIT, DIGITAL, CMOS, DIGITALSIGNAL PROCESSOR, MONOLITHIC SILICON

06-09-25
REVISION LEVELAMSC N/A

SIZE

CAGE CODE

A

67268

B
DSCC FORM 2233
APR 97
DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.

SHEET

5962-06208

1 OF 825962-E255-24

1. SCOPE
1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q) andspace application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or
Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN.
1.2 PIN. The PIN is as shown in the following example:

5962

-

06208

Federalstock classdesignator\

RHA
designator(see 1.2.1)

01

Q

X

A

Devicetype(see 1.2.2)

Deviceclass
designator(see 1.2.3)

Case
outline(see 1.2.4)

Leadfinish(see 1.2.5)/\/
Drawing number

1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and aremarked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.
1.2.2 Device type(s). The device type(s) identify the circuit function as follows:
Device type

Generic number

Circuit function

01

SMJ320F2812

Digital signal processor

1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level asfollows:
Device class

Device requirements documentation

Q or V

Certification and qualification to MIL-PRF-38535

1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows:
Outline letter
X

Descriptive designator
CQCC2-F172

Terminals

Package style172

Quad leaded chip carrier with
non-conductive tie bar

1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V.

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97

SIZE

5962-06208

A
REVISION LEVEL

B

SHEET

2

1.3 Absolute maximum ratings.

1/

Supply voltage ranges, (VDDIO, VDDA1, VDDA2, VDDAIO, AVDDREFBG) .............................................. -0.3 V to +4.6 V
Supply voltage ranges, (V DD, VDD1) ........................................................................................... -0.5 V to +2.5 V
VDD3VFL range ............................................................................................................................ -0.3 V to +4.6 V
Input voltage range, (V IN) .......................................................................................................... -0.3 V to +4.6 V
Output voltage range, (V O) ....................................................................................................... -0.3 V to +4.6 V
Input clamp current, IIK (VIN < 0 or VIN > VDDIO) ......................................................................... 20 mA 2/
Output clamp current, IOK (VO < 0 or VO > VDDIO) ...................................................................... 20 mA
Operating ambient temperature range, (TA) .............................................................................. -55C to +125C
Storage temperature range, (TSTG) ............................................................................................ -65C to +150C

3/
3/

On-Chip Analog-to-Digital Converter.
Supply voltage ranges, (VSSA1/VSSA2 to VDDA1/VDDA2/AVDDREFBG) ............................................... -0.3 V to +4.6 V
Supply voltage ranges, (V SS1 to VDD1) ....................................................................................... -0.3 V to 2.5 V
Analog input (ADCIN) clamp current, total (max) ...................................................................... 20 mA 4/
1.4 Recommended operating conditions.
Device supply voltage, I/O, (V DDIO) ........................................................................................... +3.14 V to +3.47 V
Device supply voltage, CPU, (VDD, VDD1):
1.8 V (135 MHz) ................................................................................................................ +1.71 V to 1.89 V
1.9 V (150 MHz) ................................................................................................................ +1.81 to +2 V
Supply ground, (VSS) ................................................................................................................ 0 V
ADC supply voltage (VDDA!, VDDA2, AVDDREFBG, VDDAIO) .............................................................. +3.14 V to +3.47 V
Flash programming supply voltage, (V DD3VFL) ........................................................................... +3.14 V to +3.47 V
Device clock frequency (system clock), (f SYSCLKOUT):VDD = 1.9 V  5% ............................................................................................................... 2 MHz to 150 MHz
VDD = 1.8 V  5% ............................................................................................................... 2 MHz to 135 MHz
High level input voltage, (V IH):
All inputs except XCLKIN .................................................................................................. +2 V to VDDIOXCLKIN (@ 50 A max) .................................................................................................... +0.7VDD to VDD
Maximum low level input voltage, (VIL):
All inputs except XCLKIN .................................................................................................. +0.8 V
XCLKIN (@ 50 A max) .................................................................................................... +0.3VDD
Maximum high level output source current, V OH = 2.4 V (IOH):
All I/Os except group 2 ...................................................................................................... -4 mA
Group 2 5/ ...................................................................................................................... -8 mA
Maximum low level output sink current, V OL = VOL max (IOL):All I/Os except group 2 ...................................................................................................... 4 mA
Group 2 5/ ...................................................................................................................... 8 mA
Operating ambient temperature range, (TA) ............................................................................. -55C to +125C
Flash Timing.
Minimum flash endurance for the array (N f) (Write/erase cycles) (0C to 85C) ....................... 100 cycles
Maximum One-Time Programmable (OTP) endurance for the array (NOTP)(Write cycles) (0C to 85C) ............................................................................................. 1 write

6/_________
1/

2/
3/
4/
5/
6/

Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These arestress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under“recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended
periods may affect device reliability.
Continuous clamp current per pin is 2 mA.
Long term high temperature storage and/or extended use at maximum temperature conditions may result in a reduction of
overall device life.
The analog inputs have an internal clamping circuit that clamps the voltage to a diode drop above V DDA or below VSS. The
continuous clamp current per pin is 2 mA.
Group 2 pins are as follows: XINTF pins, ̅̅̅̅̅̅̅̅̅̅̅̅̅PDPINTA, TDO, XCLKOUT, XF, EMU0, and EMU1.
Flash Timing Endurance is the minimum number of write/erase or write cycles specified over a programming temperature
range of 0C to 85C. Flash may be read over the operating temperature range of the device (-55C to +125C).

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97

SIZE

5962-06208

A
REVISION LEVEL

B

SHEET

3

2. APPLICABLE DOCUMENTS
2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a partof this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in thesolicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATIONMIL-PRF-38535-

Integrated Circuits, Manufacturing, General Specification for.

DEPARTMENT OF DEFENSE STANDARDSMIL-STD-883
MIL-STD-1835-

Test Method Standard Microcircuits.
Interface Standard Electronic Component Case Outlines.

DEPARTMENT OF DEFENSE HANDBOOKSMIL-HDBK-103
MIL-HDBK-780-

List of Standard Microcircuit Drawings.
Standard Microcircuit Drawings.

(Copies of these documents are available online at https://quicksearch.dla.mil/.)
2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the textof this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a
specific exemption has been obtained.
3. REQUIREMENTS
3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with
MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The
modification in the QM plan shall not affect the form, fit, or function as described herein.
3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified
in MIL-PRF-38535 and herein for device classes Q and V.
3.2.1 Case outline. The case outline shall be in accordance with 1.2.4 herein.
3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1.
3.2.3 Functional block diagram. The functional block diagram shall be as specified on figure 2.
3.2.4 Timing waveforms and test circuits. The Timing waveforms and test circuits shall be as specified on figures 3 – 39.
3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, theelectrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the fullambient operating temperature range.
3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electricaltests for each subgroup are defined in table I.

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97

SIZE

5962-06208

A
REVISION LEVEL

B

SHEET

4

3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also bemarked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer
has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still bemarked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535.
3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in
MIL-PRF-38535.
3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535
listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). The certificate of compliancesubmitted to DLA Land and Maritime-VA prior to listing as an approved source of supply for this drawing shall affirm that the
manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein.
3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 shallbe provided with each lot of microcircuits delivered to this drawing.

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97

SIZE

5962-06208

A
REVISION LEVEL

B

SHEET

5

TABLE I. Electrical performance characteristics.
Test

SymbolConditions-55C  TC  +125C
unless otherwise specified

Group A
subgroups

Devicetype

Limits
Min

Unit
Max

Electrical Characteristics Over Recommended Operating Conditions
High-level output voltage

VOH

IOH = IOH maximum

1, 2, 3All

2.4

IOH = 50 A
Low-level output voltage

VOL

IOL = IOL maximum

Low-level input current

IIL

With pullup.
VDDIO = 3.3 V, VIN = 0 V,̅̅̅̅̅̅) except
All I/Os (including XRS
EVB 1/
With pullup.
VDDIO = 3.3 V, VIN = 0 V,
GPIOB/EVB

High-level input current

IIH

IOZ

Input capacitanceCi

Output capacitanceCo

Quiescent supply current

IDD

V

-80

-190

A

-13

-35

2

With pullup.
VDDIO = 3.3 V, VIN = VDD

2
28

A

80
2

VO = VDDIO or 0 V
4

A

7 TYP

pF

7 TYP
Operational mode
IDLE mode

HALT mode

3/

5/ 6/

6/ 7/

Operational mode
IDLE mode

pF
230
8/

mA

150
8/

mA

10
8/

mA

30
8/

mA

10
8/

mA

20
8/

A

20
8/

A

A

70 TYP
3/

4/

STANDBY mode
HALT mode

1, 2, 3

4/

STANDBY mode

IDDIO

0.4

With pulldown.
VDDIO = 3.3 V, VIN = 0 V

With pulldown. 2/
VDDIO = 3.3 V, VIN = VDD
High-impedance (offstate)state output current

V

VDDIO –
0.2

5/ 6/

6/ 7/

See footnotes at end of table.

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97

SIZE

5962-06208

A
REVISION LEVEL

B

SHEET

6

TABLE I. Electrical performance characteristics - Continued.
Test

Quiescent supply current

SymbolIDD3VFL

Conditions-55C  TC  +125C
unless otherwise specified
Operational mode
IDLE mode

IDDA
9/

XCLKINtc(OSC)tc(CI)SYSCLKOUT

tc(SCO)XCLKOUT

tc(XCO)HSPCLKtc(HCO)

All

5/ 6/

3/

4/
5/ 6/

6/ 7/
Device Clocks

On-chip oscillator clock

1, 2, 3

6/ 7/

STANDBY mode
HALT mode

LimitsMin

3/Operational mode
IDLE mode

Devicetype

4/

STANDBY mode
HALT mode

Group A
subgroups

Cycle time

A

4
8/

A

4
8/

A

50
8/

mA

20
8/

A

20
8/

A

20
8/

A

50

ns

35

MHz

Cycle time

6.67

250

ns

Frequency

4

150

MHz

Cycle time

6.67

500

ns

Frequency

2

150

MHz

Cycle time

6.67

2000

ns

Frequency

0.5

150

MHz

Cycle time

6.67
150

MHz

tc(ADCCLK)
11/

9, 10, 11All

Cycle time
Cycle timetc(SPC)

Cycle time

ns

13.3

Frequency

ns
75

MHz

40

Frequency

ns
25

MHz

20

MHz

50

Frequencytc(XTIM)48/20

ADC clock

XTIMCLK

mA

28.6

tc(LCO)tc(CKG)

45
8/Frequency

LSPCLK

McBSP

Max

10/

Frequency

SPI clock

Unit

Cycle timens

50

Frequency

ns
20

Cycle time

MHz

6.67

Frequency

ns
150

MHz

See footnotes at end of table.

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97

SIZE

5962-06208

A
REVISION LEVEL

B

SHEET

7

TABLE I. Electrical performance characteristics - Continued.
Test

SymbolConditions 10/-55C  TC  +125C
unless otherwise specified

Group A
subgroups

Devicetype

Limits

Unit

Min

Max

20

35

Clock Requirements and Characteristics
Input Clock Frequency Requirements
Input clock frequency

fx

Resonator

9, 10, 11All

CrystalXCLKIN
Limp mode clock
frequency

12/

20

35

4

150

fl

MHz

2 TYP

MHz

XCLKIN Timing Requirements – PLL Bypassed or Enabled
Cycle time, XCLKIN

tc(CI)

See figure 4, reference C8.

Fall time, XCLKIN

tf(CI)

Rise time, XCLKIN

tr(CI)

Pulse duration,
X1/XCLKIN low as apercentage of tc(CI)

tw(CIL)

Pulse duration,
X1/XCLKIN high as apercentage of tc(CI)

tw(CIH)9, 10, 11

All

250

ns

See figure 4, reference C9.
Up to 30 MHz.

6

ns

See figure 4, reference C9.
30 MHz to 150 MHz.

2

See figure 4, reference C10.
Up to 30 MHz.

6

See figure 4, reference C10.
30 MHz to 150 MHz.

2

See figure 4.

6.67

ns

40

60

%

40

60

%

6.67

250

ns
ns

XCLKIN Timing Requirements – PLL Disabled
Cycle time, XCLKIN

tc(CI)

See figure 4, reference C8.

Fall time, XCLKIN

tf(CI)

See figure 4, reference C9.
Up to 30 MHz.

6

See figure 4, reference C9.
30 MHz to 150 MHz.

2

See figure 4, reference C10.
Up to 30 MHz.

6

See figure 4, reference C10.
30 MHz to 150 MHz.

2

Rise time, XCLKIN

tr(CI)

Pulse duration,
X1/XCLKIN low as apercentage of tc(CI)

tw(CIL)

Pulse duration,
X1/XCLKIN low as apercentage of tc(CI)

tw(CIH)9, 10, 11All

See figure 4.
XCLKIN  120 MHz

40

60

See figure 4.
120 MHz  XCLKIN  150 MHz

45

55

See figure 4.
XCLKIN  120 MHz

40

60

See figure 4.
120 MHz  XCLKIN  150 MHz

45

55

ns

%

%

See footnotes at end of table.

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97

SIZE

5962-06208

A
REVISION LEVEL

B

SHEET

8

TABLE I. Electrical performance characteristics - Continued.
Test

SymbolConditions 10/-55C  TC  +125C
unless otherwise specified

Group A
subgroups

Devicetype

LimitsMin

XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
9, 10, 11

Unit
Max

13/ 14/

Cycle time, XCLKOUT

tc(XCO)See figure 4, reference C1.

Fall time, XCLKOUT

tf(XCO)See figure 4, reference C3.

Rise time, XCLKOUT

tr(XCO)See figure 4, reference C4.

Pulse duration, XCLKOUT
lowtw(XCOL)See figure 4, reference C5.

H-2

H+2

ns

Pulse duration, XCLKOUT
high

tw(XCOH)

See figure 4, reference C6.

H-2

H+2

ns

PLL lock timetp

See figure 4.

131072tc(CI)

ns

Reset Timing̅̅̅̅̅̅) Timing Requirements
Reset (XRS
Pulse duration, stable
XCLKIN to ̅̅̅̅̅̅XRS high

tw(RSL1)

See figures 5, 6, and 7.

̅̅̅̅̅̅ low
Pulse duration, XRS

tw(RSL2)

See figures 5, 6, and 7.
Warm reset

Pulse duration, reset
pulse generated bywatchdogtw(WDRS)

Delay time, address/data̅̅̅̅̅̅ highvalid after XRS

td(EX)

Oscillator start-up time

tOSCST
17/

Setup time for ̅̅̅̅̅̅̅̅̅̅̅̅̅XPLLDIS

All

6.67
15/

ns

2 TYP

ns

2 TYP

ns

16/

9, 10, 11All

8tc(CI)

cycles8tc(CI)

cyclesSee figures 5, 6, and 7.
WD-initiated reset

512tc(CI)NOM

See figures 5, 6, and 7.

512tc(CI)NOM

cycles32tc(CI)NOM

cycles1

mstsu(XPLLDIS)

16tc(CI)

cycles̅̅̅̅̅̅̅̅̅̅̅̅̅ pin
Hold time for XPLLDIS̅̅̅̅̅ pin
Hold time for XMP/MCth(XPLLDIS)

16tc(CI)

cyclesth(XMP/MC)

16tc(CI)

cyclesHold time for boot-modepinsth(boot-

2520tc(CI)18/cyclespin

mode)

See footnotes at end of table.

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97

SIZE

5962-06208

A
REVISION LEVEL

B

SHEET

9

TABLE I. Electrical performance characteristics - Continued.
Test

SymbolConditions 10/-55C  TC  +125C
unless otherwise specified

Group A
subgroups

Devicetype

Limits
Min

Unit
Max

Low-Power Mode Wake-up Timing
IDLE Mode Switching Characteristics
Pulse duration, external
wake-up signaltw(WAKEINT)

See figure 8.
Without input qualifier.

9, 10, 11All

2*tc(SCO)

cyclesSee figure 8.
With input qualifier.

1*tc(SCO)+ IQT 19/

- Wake-up from Flash.
- Flash module in active
state.

See figure 8.
Without input qualifier.

8*tc(SCO)

cyclesSee figure 8.
With input qualifier.

8*tc(SCO)+ IQT 19/

cycles- Wake-up from Flash.
- Flash module in sleep
state.

See figure 8.
Without input qualifier.

1050 *tc(SCO)

cyclesSee figure 8.
With input qualifier.

1050 *tc(SCO)+ IQT 19/

cycles- Wake-up from SARAM.

See figure 8.
Without input qualifier.

8*tc(SCO)

cyclesSee figure 8.
With input qualifier.

8*tc(SCO)+ IQT 19/

cyclesDelay time, external wakesignal to program
execution resumetd(WAKEIDLE)20/

See footnotes at end of table.

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97

SIZE

5962-06208

A
REVISION LEVEL

B

SHEET

10

TABLE I. Electrical performance characteristics - Continued.
Test

SymbolConditions 10/-55C  TC  +125C
unless otherwise specified

Group A
subgroups

Devicetype

Limits
Min

Unit
Max

STANDBY Mode Switching characteristics
Delay time, IDLE
instruction executed to
XCLKOUT hightd(IDLE-

Pulse duration, external
wake-up signaltw(WAKE-32*tc(SCO)

cyclesSee figure 9.
Without input qualifier.

12*tc(CI)cyclesSee figure 9.
With input qualifier.

21/- Wake-up from Flash.
- Flash module in active
state.

See figure 9.
Without input qualifier.

12*tc(CI)cyclesSee figure 9.
With input qualifier.

12*tc(CI)+ tw(WAKE-INT)

cycles- Wake-up from Flash.
- Flash module in sleep

See figure 9.
Without input qualifier.

1125 * tc(SCO)

cyclesstate.

See figure 9.
With input qualifier.

1125 * tc(SCO)+
tw(WAKE-INT)

cycles- Wake-up from SARAM.

See figure 9.
Without input qualifier.

12*tc(CI)cyclesSee figure 9.
With input qualifier.

12*tc(CI)+ tw(WAKE-INT)

cyclesDelay time, external wakesignal to program
execution resume 20/

See figure 9.

9, 10, 11

All

XCOH)

INT)

td(WAKESTBY)

See footnotes at end of table.

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97

SIZE

5962-06208

A
REVISION LEVEL

B

SHEET

11

TABLE I. Electrical performance characteristics - Continued.
Test

SymbolConditions 10/-55C  TC  +125C
unless otherwise specified

Group A
subgroups

Devicetype

Limits
Min

Unit
Max

HALT Mode Switching Characteristics
Delay time, IDLE
instruction executed to
XCLKOUT hightd(IDLE-

Pulse duration, XNMI
wake-up signal
Pulse duration, ̅̅̅̅̅̅XRS

tw(WAKE-See figure 10.

9, 10, 11All

32*tc(SCO)

cycles2*tc(CI)

cycles8*tc(CI)

cycles

XCOH)

XNMI)

tw(WAKE-wake-up signal

XRS)

PLL lock-up time

tp131072cycles* tc(CI)
Delay time, PLL lock toprogram execution
resumetd(WAKE)- Wake-up from Flash.
- Flash module in sleep
state.
- Wake-up from SARAM.

1125 *tc(SCO)

cycles35*tc(SCO)

cycles25

ns

Event Manager Interface – PWM Timing 22/
PWM Switching Characteristics 23/ 24/
Pulse duration, PWMx
output high/lowtw(PWM)25/

See figure 11.

Delay time, XCLKOUT
high to PWMx output
switchingtd(PWM)XCO See figure 11.
XCLKOUT = SYSCLKOUT/4

9, 10, 1110Timer and Capture Unit Timing Requirements
Pulse duration, TDIRx
low/high

Pulse duration, CAPx
input low/hightw(TDIR)

tw(CAP)

Pulse duration, TCLKINx
low as a percentage of
TCLKINx cycle timetw(TCLKINL)

Pulse duration, TCLKINx
high as a percentage of
TCLKINx cycle time
Cycle time, TCLKINxAll

See figure 12.
Without input qualifierns

26/ 27/

9, 10, 11All

2*tc(SCO)

cyclesSee figure 12.
With input qualifier

1*tc(SCO)+ IQT 19/

cyclesSee figure 12.
Without input qualifier

2*tc(SCO)

cyclesSee figure 12.
With input qualifier

1*tc(SCO)+ IQT 19/

cyclesSee figure 12.

40

60

%

tw(TCLKINH)

40

60

%

tc(TCLKIN)

4*tc(HCO)ns

See footnotes at end of table.

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97

SIZE

5962-06208

A
REVISION LEVEL

B

SHEET

12

TABLE I. Electrical performance characteristics - Continued.
Test

SymbolConditions 10/-55C  TC  +125C
unless otherwise specified

Group A
subgroups

Devicetype
Min

External ADC Start-of-Conversion – EVA – Switching Characteristics
Delay time, XCLKOUT
̅̅̅̅̅̅̅̅̅̅̅̅̅ low
high to EVASOC

td(XCOH-

Pulse duration, ̅̅̅̅̅̅̅̅̅̅̅̅̅EVASOC

tw(EVASOCL)

LimitsSee figure 13.

9, 10, 11

Unit
Max

28/

All

1*tc(SCO)

cyclesEVASOCL)

32*tc(HCO)nslow
External ADC Start-of-Conversion – EVB – Switching Characteristics
Delay time, XCLKOUT
̅̅̅̅̅̅̅̅̅̅̅̅̅ low
high to EVBSOC

td(XCOH-̅̅̅̅̅̅̅̅̅̅̅̅̅
Pulse duration, EVBSOC

tw(EVBSOCL)

See figure 14.

9, 10, 11

28/

All

1*tc(SCO)

cyclesEVBSOCL)

32*tc(HCO)nslowInterrupt Timing
Interrupt Switching Characteristics
Delay time, ̅̅̅̅̅̅̅̅̅̅̅̅̅PDPINTx lowtd(PDP-

to PWM high-impedancestate

PWM)HZ

Delay time,̅̅̅̅̅̅̅̅̅̅̅/TxCTRIP
̅̅̅̅̅̅̅̅̅̅̅̅̅CxTRIP

td(TRIPPWM)HZ

signals low to PWM
high impedance state
Delay time, INT low/highto interrupt-vector fetchtd(INT)See figure 15.
Without input qualifier

9, 10, 11

All

12

ns

See figure 15.
With input qualifier

1*tc(SCO) +IQT + 1219/

See figure 15.
Without input qualifier

3*tc(SCO)

See figure 15.
With input qualifier[2*tc(SCO)]
+ IQT
19/

See figure 15.

tqual +
12tc(XCO)ns

ns

See footnotes at end of table.

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97

SIZE

5962-06208

A
REVISION LEVEL

B

SHEET

13

TABLE I. Electrical performance characteristics - Continued.
Test

SymbolConditions 10/-55C  TC  +125C
unless otherwise specified

Group A
subgroups

Devicetype

Limits
Min

Unit
Max

Interrupt Timing Requirements
Pulse duration, INT input
low/high̅̅̅̅̅̅̅̅̅̅̅̅̅
Pulse duration, PDPINTxtw(INT)See figure 15.
With no qualifiertw(PDP)

input low̅̅̅̅̅̅̅̅̅̅̅
Pulse duration, CxTRIP

tw(CxTRIP)

input low̅̅̅̅̅̅̅̅̅̅̅̅̅
Pulse duration, TxCTRIP

tw(TxCTRIP)

input low

9, 10, 11All

2*tc(SCO)

See figure 15.
With qualifier

1*tc(SCO) +IQT 19/See figure 15.
With no qualifier

2*tc(SCO)

See figure 15.
With qualifier

1*tc(SCO) +IQT 19/See figure 15.
With no qualifier

2*tc(SCO)

See figure 15.
With qualifier

1*tc(SCO) +IQT 19/See figure 15.
With no qualifier

2*tc(SCO)

See figure 15.
With qualifier

1*tc(SCO) +IQT 19/cyclescyclescyclescyclesGeneral-Purpose Input/Output (GPIO) – Output Timing
General-Purpose Output Switching Characteristics
Delay time, XCLKOUT
high to GPIO low/hightd(XCOH-

1*tc(SCO)

cyclesRise time, GPIO switching
low to hightr(GPO)

10ns

Fall time, GPIO switchinghigh to lowtf(GPO)

10

ns

Toggling frequency, GPO
pins

fGPO

20

MHz

GPO)

See figure 16.
All GPIOs

9, 10, 11

See figure 16.
General-Purpose Input/Output (GPIO) – Input Timing
General-Purpose Input Timing Requirements

Pulse duration, GPIO
low/high

All

tw(GPI)

See figure 18.
With no qualifier.

9, 10, 1129/All

2*tc(SCO)

See figure 18.
With qualifier.

cycles1*tc(SCO) +IQT 19/See footnotes at end of table.

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97

SIZE

5962-06208

A
REVISION LEVEL

B

SHEET

14

TABLE I. Electrical performance characteristics - Continued.
Test

SymbolConditions 10/-55C  TC  +125C
unless otherwise specified

Group A Device
subgroups typetc(SPC)M

Unit

Min

Max

4tc(LCO)

128tc(LCO)

5tc(LCO)

127tc(LCO)

0.5tc(SPC)M- 10

0.5tc(SPC)M

0.5tc(SPC)M- 0.5tc(LCO)- 10

0.5tc(SPC)M- 0.5tc(LCO)

See figure 19, reference 2. 32/(SPI when (SPIBRR + 1) iseven or SPIBRR = 0 or 2.)

0.5tc(SPC)M- 10

0.5tc(SPC)M

See figure 19, reference 2. 32/(SPI when (SPIBRR + 1) is

0.5tc(SPC)M- 0.5tc(LCO)

odd and SPIBRR  3.)

0.5tc(SPC)M- 0.5tc(LCO)- 10

See figure 19, reference 3. 32/

0.5tc(SPC)M

0.5tc(SPC)M

SPI Master Mode Timing
SPI Master Mode External Timing (Clock Phase = 0)
Cycle time, SPICLK

LimitsSee figure 19, reference 1.
(SPI when (SPIBRR + 1) iseven or SPIBRR = 0 or 2.)

9, 10, 1130/ 31/All

See figure 19, reference 1.
(SPI when (SPIBRR + 1) isns

odd and SPIBRR  3.)
Pulse duration, SPICLK
high (clock polarity = 0)tw(SPCH)M

See figure 19, reference 2. 32/(SPI when (SPIBRR + 1) isnseven or SPIBRR = 0 or 2.)
See figure 19, reference 2. 32/(SPI when (SPIBRR + 1) is
odd and SPIBRR  3.)
Pulse duration, SPICLK
low (clock polarity = 1)

Pulse duration, SPICLK

tw(SPCL)M

tw(SPCL)M

low (clock polarity = 0)

(SPI when (SPIBRR + 1) iseven or SPIBRR = 0 or 2.)

0.5tc(SPC)M+ 0.5tc(LCO)- 10

0.5tc(SPC)M+ 0.5tc(LCO)

See figure 19, reference 3. 32/(SPI when (SPIBRR + 1) iseven or SPIBRR = 0 or 2.)

0.5tc(SPC)M- 10

0.5tc(SPC)M

See figure 19, reference 3. 32/(SPI when (SPIBRR + 1) is

0.5tc(SPC)M+ 0.5tc(LCO)- 10

0.5tc(SPC)M+ 0.5tc(LCO)

odd and SPIBRR  3.)
tw(SPCH)M

ns

- 10

See figure 19, reference 3. 32/(SPI when (SPIBRR + 1) isPulse duration, SPICLK
high (clock polarity = 1)ns

odd and SPIBRR  3.)ns

See footnotes at end of table.

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97

SIZE

5962-06208

A
REVISION LEVEL

B

SHEET

15

TABLE I. Electrical performance characteristics - Continued.
Test

Delay time, SPICLK highto SPISIMO valid(clock polarity = 0)

Symboltd(SPCHSIMO)M

Conditions 10/-55C  TC  +125C
unless otherwise specified

Group A Device
subgroups type

Limits

Unit

Min

Max

-10

10

-10

10

See figure 19, reference 4. 32/(SPI when (SPIBRR + 1) iseven or SPIBRR = 0 or 2.)

-10

10

See figure 19, reference 4. 32/(SPI when (SPIBRR + 1) is

-10

10

See figure 19, reference 4. 32/(SPI when (SPIBRR + 1) iseven or SPIBRR = 0 or 2.)

9, 10, 11All

See figure 19, reference 4. 32/(SPI when (SPIBRR + 1) isns

odd and SPIBRR  3.)
Delay time, SPICLK low
to SPISIMO valid(clock polarity = 1)

td(SPCLSIMO)Mns

odd and SPIBRR  3.)
Valid time, SPISIMO data
valid after SPICLK low(clock polarity = 0)tv(SPCLSIMO)M

See figure 19, reference 5. 32/(SPI when (SPIBRR + 1) iseven or SPIBRR = 0 or 2.)
See figure 19, reference 5. 32/

0.5tc(SPC)M(SPI when (SPIBRR + 1) is+ 0.5tc(LCO)- 10

odd and SPIBRR  3.)
Valid time, SPISIMO data
valid after SPICLK high(clock polarity = 1)

tv(SPCHSIMO)M

See figure 19, reference 5. 32/(SPI when (SPIBRR + 1) iseven or SPIBRR = 0 or 2.)

0.5tc(SPC)M- 10

See figure 19, reference 5. 32/(SPI when (SPIBRR + 1) is

0.5tc(SPC)M+ 0.5tc(LCO)- 10

odd and SPIBRR  3.)
Setup time, SPISOMI
before SPICLK low(clock polarity = 0)tsu(SOMISPCL)M

0.5tc(SPC)M- 10

See figure 19, reference 8. 32/(SPI when (SPIBRR + 1) iseven or SPIBRR = 0 or 2.)

0

See figure 19, reference 8. 32/(SPI when (SPIBRR + 1) is

0

ns

ns

ns

odd and SPIBRR  3.)
Setup time, SPISOMI
before SPICLK high(clock polarity = 1)

tsu(SOMISPCH)M

See figure 19, reference 8. 32/(SPI when (SPIBRR + 1) iseven or SPIBRR = 0 or 2.)

0

See figure 19, reference 8. 32/(SPI when (SPIBRR + 1) is0ns

odd and SPIBRR  3.)
See footnotes at end of table.

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97

SIZE

5962-06208

A
REVISION LEVEL

B

SHEET

16

TABLE I. Electrical performance characteristics - Continued.
Test

Valid time, SPISOMI data
valid after SPICLK low(clock polarity = 0)

Symboltv(SPCLSOMI)M

Conditions 10/-55C  TC  +125C
unless otherwise specified

Group A Device
subgroups type

LimitsMin

See figure 19, reference 9. 32/(SPI when (SPIBRR + 1) iseven or SPIBRR = 0 or 2.)

9, 10, 11AllSOMI)M- 10

See figure 19, reference 5. 32/(SPI when (SPIBRR + 1) iseven or SPIBRR = 0 or 2.)

0.25tc(SPC)M- 10

See figure 19, reference 5. 32/(SPI when (SPIBRR + 1) is

0.5tc(SPC)M- 0.5tc(LCO)- 10

odd and SPIBRR  3.)
SPI Master Mode External Timing (Clock Phase = 1)
Cycle time, SPICLK

tc(SPC)Mns

0.5tc(SPC)M- 0.5tc(LCO)

odd and SPIBRR  3.)
tv(SPCH-Max

0.25tc(SPC)M- 10

See figure 19, reference 9. 32/(SPI when (SPIBRR + 1) is
Valid time, SPISOMI data
valid after SPICLK high(clock polarity = 1)

Unit

See figure 20, reference 1.
(SPI when (SPIBRR + 1) iseven or SPIBRR = 0 or 2.)

9, 10, 11ns

31/ 33/All

See figure 20, reference 1.
(SPI when (SPIBRR + 1) is

4tc(LCO)

128tc(LCO)

5tc(LCO)

127tc(LCO)ns

odd and SPIBRR  3.)
Pulse duration, SPICLK
high (clock polarity = 0)tw(SPCH)M

See figure 20, reference 2. 32/(SPI when (SPIBRR + 1) iseven or SPIBRR = 0 or 2.)

0.5tc(SPC)M - 0.5tc(SPC)M
10

See figure 20, reference 2. 32/(SPI when (SPIBRR + 1) is

0.5tc(SPC)M - 0.5tc(SPC)M 0.5tc(LCO) - 0.5tc(LCO)
10

odd and SPIBRR  3.)
Pulse duration, SPICLK
low (clock polarity = 1)

tw(SPCL)M

See figure 20, reference 2. 32/(SPI when (SPIBRR + 1) iseven or SPIBRR = 0 or 2.)

0.5tc(SPC)M - 0.5tc(SPC)M
10

See figure 20, reference 2. 32/

0.5tc(SPC)M - 0.5tc(SPC)M 0.5tc(LCO) - 0.5tc(LCO)
10(SPI when (SPIBRR + 1) is
odd and SPIBRR  3.)
Pulse duration, SPICLK
low (clock polarity = 0)tw(SPCL)M

See figure 20, reference 3. 32/(SPI when (SPIBRR + 1) iseven or SPIBRR = 0 or 2.)

0.5tc(SPC)M - 0.5tc(SPC)M
10

See figure 20, reference 3. 32/(SPI when (SPIBRR + 1) is

0.5tc(SPC)M + 0.5tc(SPC)M +0.5tc(LCO) - 0.5tc(LCO)
10

odd and SPIBRR  3.)

ns

ns

ns

See footnotes at end of table.

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97

SIZE

5962-06208

A
REVISION LEVEL

B

SHEET

17

TABLE I. Electrical performance characteristics - Continued.
Test

Pulse duration, SPICLK
high (clock polarity = 1)

Symboltw(SPCH)M

Conditions 10/-55C  TC  +125C
unless otherwise specified

Group A Device
subgroups typeMin

See figure 20, reference 3. 32/(SPI when (SPIBRR + 1) iseven or SPIBRR = 0 or 2.)
See figure 20, reference 3. 32/(SPI when (SPIBRR + 1) is
odd and SPIBRR  3.)

Setup time, SPISIMO data
valid before SPICLK high(clock polarity = 0)tsu(SIMOSPCH)M

Limits9, 10, 11

All

Unit
Max

0.5tc(SPC)M - 0.5tc(SPC)M
10

ns

0.5tc(SPC)M + 0.5tc(SPC)M +0.5tc(LCO) - 0.5tc(LCO)
10

See figure 20, reference 6. 32/(SPI when (SPIBRR + 1) iseven or SPIBRR = 0 or 2.)

0.5tc(SPC)M 10

See figure 20, reference 6. 32/(SPI when (SPIBRR + 1) is

0.5tc(SPC)M 10

ns

odd and SPIBRR  3.)
Setup time, SPISIMO data
valid before SPICLK low(clock polarity = 1)

tsu(SIMOSPCL)M

See figure 20, reference 6. 32/(SPI when (SPIBRR + 1) iseven or SPIBRR = 0 or 2.)

0.5tc(SPC)M 10

See figure 20, reference 6. 32/

0.5tc(SPC)M 10(SPI when (SPIBRR + 1) isns

odd and SPIBRR  3.)
Valid time, SPISIMO data
valid after SPICLK high(clock polarity = 0)tv(SPCHSIMO)M

See figure 20, reference 7. 32/(SPI when (SPIBRR + 1) iseven or SPIBRR = 0 or 2.)

0.5tc(SPC)M 10

See figure 20, reference 7. 32/(SPI when (SPIBRR + 1) is

0.5tc(SPC)M 10

ns

odd and SPIBRR  3.)
Valid time, SPISIMO data
valid after SPICLK low(clock polarity = 1)

tv(SPCLSIMO)M

See figure 20, reference 7. 32/(SPI when (SPIBRR + 1) iseven or SPIBRR = 0 or 2.)

0.5tc(SPC)M 10

See figure 20, reference 7. 32/(SPI when (SPIBRR + 1) is

0.5tc(SPC)M 10

ns

odd and SPIBRR  3.)
Setup time, SPISOMI
before SPICLK high(clock polarity = 0)tsu(SOMISPCH)M

See figure 20, reference 10. 32/(SPI when (SPIBRR + 1) iseven or SPIBRR = 0 or 2.)

0

See figure 20, reference 10. 32/(SPI when (SPIBRR + 1) is0ns

odd and SPIBRR  3.)
See footnotes at end of table.

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97

SIZE

5962-06208

A
REVISION LEVEL

B

SHEET

18

TABLE I. Electrical performance characteristics - Continued.
Test

Setup time, SPISOMI
before SPICLK low(clock polarity = 1)

Symboltsu(SOMISPCL)M

Conditions 10/-55C  TC  +125C
unless otherwise specified

Group A Device
subgroups type

LimitsMin

See figure 20, reference 10. 32/(SPI when (SPIBRR + 1) iseven or SPIBRR = 0 or 2.)

9, 10, 11

All

Unit
Max

0

See figure 20, reference 10. 32/(SPI when (SPIBRR + 1) isns0

odd and SPIBRR  3.)
Valid time, SPISOMI data
valid after SPICLK high(clock polarity = 0)tv(SPCHSOMI)M

See figure 20, reference 11. 32/(SPI when (SPIBRR + 1) iseven or SPIBRR = 0 or 2.)

0.25tc(SPC)M- 10

See figure 20, reference 11. 32/(SPI when (SPIBRR + 1) is

0.5tc(SPC)M 10

ns

odd and SPIBRR  3.)
Valid time, SPISOMI data
valid after SPICLK low(clock polarity = 1)

tv(SPCLSOMI)M

See figure 20, reference 11. 32/(SPI when (SPIBRR + 1) iseven or SPIBRR = 0 or 2.)

0.25tc(SPC)M- 10

See figure 20, reference 11. 32/

0.5tc(SPC)M 10(SPI when (SPIBRR + 1) isns

odd and SPIBRR  3.)
SPI Slave Mode Timing
SPI Slave Mode External Timing (Clock Phase = 0)
Cycle time, SPICLK

tc(SPC)SSee figure 21, reference 12.

Pulse duration, SPICLK
high (clock polarity = 0)tw(SPCH)S

See figure 21, reference 13.
35/

0.5tc(SPC)S - 0.5tc(SPC)S10

ns

Pulse duration, SPICLK
low (clock polarity = 1)

tw(SPCL)S

See figure 21, reference 13.
35/

0.5tc(SPC)S - 0.5tc(SPC)S10

ns

Pulse duration, SPICLK
low (clock polarity = 0)tw(SPCL)S

See figure 21, reference 14.
35/

0.5tc(SPC)S - 0.5tc(SPC)S10

ns

Pulse duration, SPICLK
high (clock polarity = 1)

tw(SPCH)S

See figure 21, reference 14.
35/

0.5tc(SPC)S - 0.5tc(SPC)S10

ns

Delay time, SPICLK highto SPISOMI valid(clock polarity = 0)td(SPCH-See figure 21, reference 15.
35/0.375tc(SPC)S
- 10

ns

Delay time, SPICLK low
to SPISOMI valid(clock polarity = 1)

td(SPCL-See figure 21, reference 15.
35/0.375tc(SPC)S
- 10

ns

SOMI)S

SOMI)S9, 10, 11

31/ 34/All

4tc(LCO)ns

See footnotes at end of table.

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97

SIZE

5962-06208

A
REVISION LEVEL

B

SHEET

19

TABLE I. Electrical performance characteristics - Continued.
Test

SymbolValid time, SPISOMI data
valid after SPICLK low(clock polarity = 0)tv(SPCL-

Valid time, SPISOMI data
valid after SPICLK hightv(SPCH-

SOMI)S

SOMI)S

Conditions 10/-55C  TC  +125C
unless otherwise specified

Group A Device
subgroups type

LimitsMin

See figure 21, reference 16.
35/

9, 10, 11

All

Unit
Max

0.75tc(SPC)Sns

See figure 21, reference 16.
35/

0.75tc(SPC)Sns

See figure 21, reference 19.
35/

0

ns

See figure 21, reference 19.
35/

0

ns

See figure 21, reference 20.
35/

0.5tc(SPC)Sns

See figure 21, reference 20.
35/

0.5tc(SPC)Sns

8tc(LCO)ns(clock polarity = 1)
Setup time, SPISIMO
before SPICLK low(clock polarity = 0)tsu(SIMO-

Setup time, SPISIMO
before SPICLK high(clock polarity = 1)

tsu(SIMO-

Valid time, SPISIMO data
valid after SPICLK low

tv(SPCL-

SPCL)S

SPCH)S

SIMO)S(clock polarity = 0)
Valid time, SPISIMO data
valid after SPICLK high(clock polarity = 1)

tv(SPCH-

Cycle time, SPICLK

tc(SPC)SSee figure 22, reference 12.

Pulse duration, SPICLK
high (clock polarity = 0)tw(SPCH)S

See figure 22, reference 13.
35/

0.5tc(SPC)S - 0.5tc(SPC)S10

ns

Pulse duration, SPICLK
low (clock polarity = 1)

tw(SPCL)S

See figure 22, reference 13.
35/

0.5tc(SPC)S - 0.5tc(SPC)S10

ns

Pulse duration, SPICLK
low (clock polarity = 0)tw(SPCL)S

See figure 22, reference 14.
35/

0.5tc(SPC)S - 0.5tc(SPC)S10

ns

Pulse duration, SPICLK
high (clock polarity = 1)

tw(SPCH)S

See figure 22, reference 14.
35/

0.5tc(SPC)S - 0.5tc(SPC)S10

ns

Setup time, SPISOMI
before SPICLK high(clock polarity = 0)tsu(SOMI-

See figure 22, reference 17.
35/0.125tc(SPC)Sns

Setup time, SPISOMI
before SPICLK low(clock polarity = 1)

tsu(SOMI-

See figure 22, reference 17.
35/0.125tc(SPC)Sns

Valid time, SPISOMI data
valid after SPICLK high(clock polarity = 0)tv(SPCH-See figure 22, reference 18.
35/

0.75tc(SPC)Sns

Valid time, SPISOMI data
valid after SPICLK low(clock polarity = 1)

tv(SPCL-See figure 22, reference 18.
35/

0.75tc(SPC)Sns

SIMO)SSPI Slave Mode External Timing (Clock Phase = 1)

SPCH)S

SPCL)S

SOMI)S

SOMI)S9, 10, 11

31/ 36/All

See footnotes at end of table.

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97

SIZE

5962-06208

A
REVISION LEVEL

B

SHEET

20

TABLE I. Electrical performance characteristics - Continued.
Test

SymbolSetup time, SPISIMO
before SPICLK high(clock polarity = 0)tsu(SIMO-

Setup time, SPISIMO
before SPICLK low(clock polarity = 1)

tsu(SIMO-

Valid time, SPISIMO data
valid after SPICLK high(clock polarity = 0)tv(SPCH-

Valid time, SPISIMO data
valid after SPICLK low(clock polarity = 1)

tv(SPCL-

SPCH)S

SPCL)S

SIMO)S

SIMO)S

Conditions 10/-55C  TC  +125C
unless otherwise specified

Group A Device
subgroups type

LimitsMin

See figure 22, reference 21.
35/

9, 10, 11

All

Unit
Max

0

ns

See figure 22, reference 21.
35/

0

ns

See figure 22, reference 22.
35/

0.5tc(SPC)Sns

See figure 22, reference 22.
35/

0.5tc(SPC)S

ns

External Interface Read Timing
External Memory Interface Read Switching Characteristics
Delay time, XCLKOUT
high to zone chip-selectactive lowtd(XCOH-

See figure 23.

9, 10, 11

All

1

ns

3

ns

2

ns

1

ns

1

ns

XZCSL)

Delay time, XCLKOUT
high/low to zone
chip-select inactive hightd(XCOHL-

Delay time, XCLKOUT
high to address validtd(XCOH-

Delay time, XCLKOUT
̅̅̅̅̅̅̅ active
high/low to XRD

td(XCOHL--2

XZCSH)

XA)

XRDL)

low
Delay time, XCLKOUT
high/low to ̅̅̅̅̅̅̅XRD inactive

td(XCOHL-

-2

XRDH)

high
Hold time, address valid
after zone chip-selectinactive highth(XA)XZCSH

37/

ns

Hold time, address valid̅̅̅̅̅̅̅ inactive highafter XRD

th(XA)XRD

37/

ns

See footnotes at end of table.

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97

SIZE

5962-06208

A
REVISION LEVEL

B

SHEET

21

TABLE I. Electrical performance characteristics - Continued.
Test

SymbolConditions 10/-55C  TC  +125C
unless otherwise specified

Group A Device
subgroups type

Limits
Min

Unit
Max

External Memory Interface Read Timing Requirements
Access time, read datafrom address validta(A)See figure 23.

Access time, read data̅̅̅̅̅̅̅ active
valid from XRD

ta(XRD)9, 10, 11All(LR + AR)
- 14
38/

ns

AR - 12
38/

ns

low
Setup time, read data
valid before ̅̅̅̅̅̅̅XRD strobe

tsu(XD)XRD

12nsth(XD)XRD

0nsinactive highHold time, read data valid̅̅̅̅̅̅̅ inactive highafter XRD

External Interface Write Timing
External Memory Interface Write Switching Characteristics
Delay time, XCLKOUT
high to zone chip-selectactive lowtd(XCOH-

Delay time, XCLKOUT
high or low to zone
chip-select inactive hightd(XCOHL-

Delay time, XCLKOUT
high to address validtd(XCOH-

Delay time, XCLKOUT
̅̅̅̅̅̅̅ low
high/low to XWE

td(XCOHL-

Delay time, XCLKOUT
̅̅̅̅̅̅̅ highhigh/low to XWE

td(XCOHL-

Delay time, XCLKOUT̅ lowhigh to XR/W

td(XCOH-

Delay time, XCLKOUT
̅ highhigh/low to XR/W

td(XCOHL-

Enable time, data bus̅̅̅̅̅̅̅ low
driven from XWEten(XD)XWEL

Delay time, data valid̅̅̅̅̅̅̅ active low
after XWE

td(XWEL-

Hold time, address valid
after zone chip-selectth(XA)XZCSH

See figure 24.

9, 10, 11

All

1

ns

3

ns

2

ns

2

ns

2

ns

1

ns

1

ns

XZCSL)-2

XZCSH)

XA)

XWEL)

XWEH)

XRNWL)-2

XRNWH)

0

ns
4

ns

XD)

37/

ns

inactive highSee footnotes at end of table.

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97

SIZE

5962-06208

A
REVISION LEVEL

B

SHEET

22

TABLE I. Electrical performance characteristics - Continued.
Test

SymbolHold time, write data valid̅̅̅̅̅̅̅ inactive highafter XWEth(XD)XWE

Data bus disabled after̅ inactive highXR/Wtdis(XD)

Conditions 10/-55C  TC  +125C
unless otherwise specified

Group A Device
subgroups type

LimitsMin

See figure 24.

9, 10, 11

All

Unit
Max

TW – 2
39/

ns

4

ns

XRNW

External Interface Ready-on-Read Timing With One External Wait State
External Memory Interface Read Switching Characteristics (Ready-on-Read, 1 Wait State)
Delay time, XCLKOUT
high to zone chip-selectactive lowtd(XCOH-

Delay time, XCLKOUT
high/low to zone
chip-select inactive hightd(XCOHL-

Delay time, XCLKOUT

9, 10, 11

All

1

ns

3

ns

td(XCOH-XA)

2

ns

td(XCOHL-

1

ns

1

ns

XZCSL)-2

XZCSH)

high to address valid
Delay time, XCLKOUT
high/low to ̅̅̅̅̅̅̅XRD active

XRDL)

low
Delay time, XCLKOUT
high/low to ̅̅̅̅̅̅̅XRD inactive

td(XCOHL-

-2

XRDH)

high
Hold time, address valid
after zone chip-selectinactive highth(XA)XZCSH

37/

ns

Hold time, address valid
after ̅̅̅̅̅̅̅XRD inactive highth(XA)XRD

37/

sn

External Memory Interface Read Timing Requirements (Ready-on-Read, 1 Wait State)
Access time, read datafrom address validta(A)Access time, read data̅̅̅̅̅̅̅ active
valid from XRD

ta(XRD)9, 10, 11All(LR + AR)
- 14
38/

ns

AR – 12
38/

ns

low
Setup time, read data
valid before ̅̅̅̅̅̅̅XRD strobe

tsu(XD)XRD

12nstsu(XD)XRD

0ns

inactive highHold time, read data̅̅̅̅̅̅̅ inactive
valid after XRD
high
See footnotes at end of table.

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97

SIZE

5962-06208

A
REVISION LEVEL

B

SHEET

23

TABLE I. Electrical performance characteristics - Continued.
Test

SymbolConditions 10/-55C  TC  +125C
unless otherwise specified

Group A Device
subgroups type

LimitsMin

Synchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State)
Setup time, XREADY(Synch) low before
XCLKOUT high/low

tsu(XRDY

Hold time, XREADY(Synch) lowth(XRDY

Earliest time XREADY(Synch) can go highte(XRDY

See figure 25.

9, 10, 11

All

Unit
Max

40/
15

ns

12

ns

synchL)
XCOHL

synchL)3ns

synchH)

before the sampling
XCLKOUT edge
Setup time, XREADY(Synch) high before
XCLKOUT high/low

tsu(XRDY

Hold time, XREADY(Synch) held high afterzone chip-select highth(XRDY

15

ns

0

ns

synchH)XCOHL

synchH)
XZCSH

Asynchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State)
Setup time, XREADY(Asynch) low before
XCLKOUT high/low

tsu(XRDY

Hold time, XREADYth(XRDY

See figure 26.

9, 10, 11

All

41/

11

ns

8

ns

asynchL)
XCOHL

asynchL)(Asynch) low
Earliest time XREADY(Asynch) can go highbefore the sampling
XCLKOUT edgete(XRDY

Setup time, XREADY(Asynch) high before
XCLKOUT high/low

tsu(XRDY

Hold time, XREADYth(XRDY(Asynch) held high afterzone chip-select high3ns

asynchH)

11

ns

0

ns

asynchH)
XCOHL

asynchH)
XZCSH

See footnotes at end of table.

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97

SIZE

5962-06208

A
REVISION LEVEL

B

SHEET

24

TABLE I. Electrical performance characteristics - Continued.
Test

SymbolConditions 10/-55C  TC  +125C
unless otherwise specified

Group A Device
subgroups type

Limits
Min

Unit
Max

External Interface Ready-on-Write Timing With One External Wait State
External Memory Interface Write Switching Characteristics (Ready-on-Write, 1 Wait State)
Delay time, XCLKOUT
high to zone chip-selectactive lowtd(XCOH-

Delay time, XCLKOUT
high or low to zone
chip-select inactive hightd(XCOHL-

Delay time, XCLKOUT
high to address valid

9, 10, 11

All

1

ns

3

ns

td(XCOH-XA)

2

ns

Delay time, XCLKOUT
̅̅̅̅̅̅̅ low
high/low to XWE

td(XCOHL-

2

ns

Delay time, XCLKOUT
̅̅̅̅̅̅̅ highhigh/low to XWE

td(XCOHL-

2

ns

Delay time, XCLKOUT̅ lowhigh to XR/W

td(XCOH-

1

ns

Delay time, XCLKOUT
̅ highhigh/low to XR/W

td(XCOHL-

1ns

Enable time, data bus̅̅̅̅̅̅̅ low
driven from XWEten(XD)XWEL

Delay time, data valid̅̅̅̅̅̅̅ active low
after XWE

td(XWEL-XD)

Hold time, address valid
after zone chip-selectth(XA)XZCSH

37/

ns

Hold time, write data valid̅̅̅̅̅̅̅ inactive highafter XWEth(XD)XWE

TW – 239/

ns

Data bus disabled after̅ inactive highXR/Wtdis(XD)

4ns

XZCSL)-2

XZCSH)

XWEL)

XWEH)

XRNWL)-2

XRNWH)

0

ns
4

ns

inactive high

XRNW

See footnotes at end of table.

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97

SIZE

5962-06208

A
REVISION LEVEL

B

SHEET

25

TABLE I. Electrical performance characteristics - Continued.
Test

SymbolConditions 10/-55C  TC  +125C
unless otherwise specified

Group A Device
subgroups type

LimitsMin

Synchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State)
Setup time, XREADY(Synch) low before
XCLKOUT high/low

tsu(XRDY

Hold time, XREADY(Synch) lowth(XRDY

Earliest time XREADY(Synch) can go highte(XRDY

See figure 27.

9, 10, 11

All

Unit
Max

42/
15

ns

12

ns

synchL)
XCOHL

synchL)3ns

synchH)

before the sampling
XCLKOUT edge
Setup time, XREADY(Synch) high before
XCLKOUT high/low

tsu(XRDY

Hold time, XREADY(Synch) held high afterzone chip-select highth(XRDY

15

ns

0

ns

synchH)XCOHL

synchH)
XZCSH

Asynchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State)
Setup time, XREADY(Asynch) low before
XCLKOUT high/low

tsu(XRDY

Hold time, XREADYth(XRDY

See figure 28.

9, 10, 11

All

43/
11

ns

8

ns

asynchL)
XCOHL

asynchL)(Asynch) low
Earliest time XREADY(Asynch) can go highbefore the sampling
XCLKOUT edgete(XRDY

Setup time, XREADY(Asynch) high before
XCLKOUT high/low

tsu(XRDY

Hold time, XREADYth(XRDY(Asynch) held high afterzone chip-select high3ns

asynchH)

11

ns

0

ns

asynchH)
XCOHL

asynchH)
XZCSH

See footnotes at end of table.

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97

SIZE

5962-06208

A
REVISION LEVEL

B

SHEET

26

TABLE I. Electrical performance characteristics - Continued.
Test

SymbolConditions 10/-55C  TC  +125C
unless otherwise specified

Group A Device
subgroups type

Limits
Min

Unit
Max

̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅̅ Timing
XHOLD/XHOLDA̅̅̅̅̅̅̅̅̅̅̅/XHOLDA̅̅̅̅̅̅̅̅̅̅̅̅̅ Timing Requirements (XCLKOUT = XTIMCLK)XHOLDDelay time, ̅̅̅̅̅̅̅̅̅̅̅XHOLD lowtd(HL-HiZ)

to Hi-Z on all Address,
Data, and Control̅̅̅̅̅̅̅̅̅̅̅ low
Delay time, XHOLD
to ̅̅̅̅̅̅̅̅̅̅̅̅̅XHOLDA low
Delay time, ̅̅̅̅̅̅̅̅̅̅̅XHOLD highto ̅̅̅̅̅̅̅̅̅̅̅̅̅XHOLDA high
Delay time, ̅̅̅̅̅̅̅̅̅̅̅XHOLD highSee figure 29.

9, 10, 11

44/ 45/All

4tc(XTIM)

nstd(HL-HAL)

5tc(XTIM)

nstd(HH-HAH)

3tc(XTIM)

nstd(HH-BV)

4tc(XTIM)

ns

4tc(XTIM) +tc(XCO)ns

to bus valid̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅̅ Timing Requirements (XCLKOUT = 1/2 XTIMCLK)XHOLD/XHOLDA̅̅̅̅̅̅̅̅̅̅̅ low
Delay time, XHOLD

td(HL-HiZ)

See figure 30.

9, 10, 11

44/ 45/ 46/

All

to Hi-Z on all Address,
Data, and Control
Delay time, ̅̅̅̅̅̅̅̅̅̅̅XHOLD lowtd(HL-HAL)

4tc(XTIM) +2tc(XCO)ns̅̅̅̅̅̅̅̅̅̅̅̅̅ low
to XHOLDA
Delay time, ̅̅̅̅̅̅̅̅̅̅̅XHOLD hightd(HH-HAH)

4tc(XTIM)ns

to ̅̅̅̅̅̅̅̅̅̅̅̅̅XHOLDA high̅̅̅̅̅̅̅̅̅̅̅ high
Delay time, XHOLD

td(HH-BV)

6tc(XTIM)ns

to bus valid
See footnotes at end of table.

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97

SIZE

5962-06208

A
REVISION LEVEL

B

SHEET

27

TABLE I. Electrical performance characteristics - Continued.
Test

SymbolConditions 10/-55C  TC  +125C
unless otherwise specified

Group A Device
subgroups type

Limits

Unit

Min

Max

Analog-to-Digital Converter (ADC) Electrical Characteristics Over Recommended Operating Conditions
DC Specifications 47/
Resolution

1, 2, 3All

12

ADC clock
48/

Bits

1

kHz
25

MHz

1.5

LSB

1

LSB

ACCURACY
INL (Integral nonlinearity)49/

1 – 18.75 MHz ADC clock

DNL (Differential
nonlinearity) 49/

1 – 18.75 MHz ADC clock

Offset error

1, 2, 3All

50/

Overall gain error withinternal reference 51/
Overall gain error with

If ADCREFP – ADCREFM =external reference

1 V 0.1%

52/

-80

80

LSB

-200

200

LSB

-50

50

LSB

Channel-to-channel
offset variation

8 TYP

LSB

Channel-to-channel
gain variation

8 TYPLSB

ANALOG INPUT
Analog input voltage(ADCINx to ADCLO) 53/

1, 2, 3All

ADCLO
Input capacitance

3

V

-5

5

mV

4

Input leakage current
INTERNAL VOLTAGE REFERENCE

0

10 TYP

pF
5

A

1.9

2.1

V

0.95

1.05

V

1, 2, 351/

Accuracy, ADCVREFP

1, 2, 3

All

Accuracy, ADCVREFM
Voltage difference
ADCREFP – ADCREFM

1 TYP

V

Temperature coefficient

50 TYP

PPM/
C

Reference noise

100 TYP

V

EXTERNAL VOLTAGE REFERENCE

52/

Accuracy, ADCVREFP

1, 2, 3

All

1.9

2.1

V

Accuracy, ADCVREFM

0.95

1.05

V

Input voltage difference,
ADCREFP - ADCREFM

0.99

1.01

V

See footnotes at end of table.

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97

SIZE

5962-06208

A
REVISION LEVEL

B

SHEET

28

TABLE I. Electrical performance characteristics - Continued.
Test

SymbolConditions 10/-55C  TC  +125C
unless otherwise specified

Group A Device
subgroups type

Limits

Unit

Min

Max

AC Specifications
Signal-to-noise ratio+ distortion

SINAD

Signal-to-noise ratio
Total harmonic distortion
Effective number of bits

9, 10, 11All

62 TYPdB

SNR

62 TYPdB

THD(100 kHz)-68 TYP

dB

ENOB

10.1 TYP

Bits

69 TYPdB(SNR)
Spurious free dynamic
range

SDFR
Current Consumption for Different ADC Configurations (at 25-MHz ADCCLK)

Quiescent supply currents

IDDA
55/
IDDAIO

Mode A (Operational Mode):- BG and REF enabled- PWD disabled

9, 10, 11All

40 TYPIDDAIO
IDD1
IDDA
55/
IDDAIO
IDD1
IDDA
55/
IDDAIO
IDD1

mA

1 TYP

A

0.5 TYP

mA

Mode B:- ADC clock enabled- BG and REF enabled- PWD enabled

7 TYP

mA

0 TYP

A

5 TYP

A

Mode C:- ADC clock enabled- BG and REF disabled- PWD enabled

1 TYP

A

0 TYP

A

5 TYP

A

Mode D:- ADC clock disabled- BG and REF disabled- PWD enabled

1 TYP

A

0 TYP

A

0 TYP

A

IDD1
IDDA
55/

54/

See footnotes at end of table.

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97

SIZE

5962-06208

A
REVISION LEVEL

B

SHEET

29

TABLE I. Electrical performance characteristics - Continued.
Test

SymbolConditions 10/-55C  TC  +125C
unless otherwise specified

Group A Device
subgroups type

Limits

Unit

Min

Max

7

10

ADC Power-Up Control Bit Timing
ADC Power-Up Delays 56/
Delay time for band gap
reference to be stable

td(BGR)See figure 31.
Bits 6 and 5 of the ADCTRL3
register (PWDNBG and

9, 10, 11All

ms

PWDNREF) are to be set to 1
before the ADCPWDN bit isenabled.
Delay time for power-down
control to be stable

td(PWD)See figure 31.
Bit 7 of the ADCTRL3 register(ADCPWDN) is set to 1 before
any ADC conversions are
initiated.

s

20

1

ms

Sequential Sampling Mode (Single-Channel) (SMODE = 0)
Sequential Sampling Mode Timing
Delay time from event
trigger to samplingtd(SH)

See figure 32.
Sample n

Sample/Hold width/
Acquisition widthtSH

See figure 32.
Sample n

9, 10, 11All

2.5tc(ADCCLK)(1 + Acqps)*
tc(ADCCLK)

Acqps value = 0 – 15
ADCTRL1[8:11]
See figure 32.
At 25 MHz ADC clock,tc(ADCCLK) = 40 ns
Acqps value = 0 – 15
ADCTRL1[8:11]
Delay time for first result
to appear in the Result
registertd(schx n)

Delay time for successive
results to appear in the
Result registertd(schx n + 1) See figure 32.
Sample n + 1

40 ns with Acqps = 0

See figure 32.
Sample n4tc(ADCCLK)

See figure 32.
At 25 MHz ADC clock,tc(ADCCLK) = 40 ns

160 ns(2 + Acqps)*
tc(ADCCLK)

See figure 32.
At 25 MHz ADC clock,tc(ADCCLK) = 40 ns

80 ns

See footnotes at end of table.

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97

SIZE

5962-06208

A
REVISION LEVEL

B

SHEET

30

TABLE I. Electrical performance characteristics - Continued.
Test

SymbolConditions 10/-55C  TC  +125C
unless otherwise specified

Group A Device
subgroups type

Limits
Min

Unit
Max

Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1)
Simultaneous Sampling Mode Timing
Delay time from event
trigger to samplingtd(SH)

See figure 33.
Sample n

Sample/Hold width/
Acquisition widthtSH

See figure 33.
Sample n
Acqps value = 0 – 15
ADCTRL1[8:11](1 + Acqps)*
tc(ADCCLK)

See figure 33.
At 25 MHz ADC clock,tc(ADCCLK) = 40 ns
Acqps value = 0 – 15
ADCTRL1[8:11]

40 ns with Acqps = 0

Delay time for first result
to appear in the Result
registertd(schA0 n)

Delay time for first result
to appear in the Result
registertd(schB0 n)

Delay time for successive
results to appear in the
Result registertd(schA0 n+ 1)

9, 10, 11All

2.5tc(ADCCLK)

See figure 33.
Sample n4tc(ADCCLK)

See figure 33.
At 25 MHz ADC clock,tc(ADCCLK) = 40 ns

160 nsSee figure 33.
Sample n

5tc(ADCCLK)

See figure 33.
At 25 MHz ADC clock,tc(ADCCLK) = 40 ns

200 nsSee figure 33.
Sample n + 1(3 + Acqps)*
tc(ADCCLK)

See figure 33.
At 25 MHz ADC clock,

120 nstc(ADCCLK) = 40 ns
Delay time for successive
results to appear in the
Result registertd(schB0 n+ 1)

See figure 33.
Sample n + 1(3 + Acqps)*
tc(ADCCLK)

See figure 33.
At 25 MHz ADC clock,tc(ADCCLK) = 40 ns

120 nsSee footnotes at end table.

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97

SIZE

5962-06208

A
REVISION LEVEL

B

SHEET

31

TABLE I. Electrical performance characteristics - Continued.
Test

SymbolConditions 10/-55C  TC  +125C
unless otherwise specified

Group A Device
subgroups type

Limits
Min

Unit
Max

Multichannel Buffered Serial Port (McBSP) Transmit and Receive Timing
McBSP Timing Requirements 57/ 58/
McBSP module clock(CLKG, CLKX, CLKR)
range

9, 10, 11

All

1

kHz
20

McBSP module cycle time
(CLKG, CLKX, CLKR)
range

59/

MHz

50

ns
1

ms

Cycle time, CLKR/X

tc(CKRX)See figure 34, reference M11.
CLKR/X ext

2P

ns

Pulse duration, CLKR/X
high or CLKR/X low

tw(CKRX)See figure 34, reference M12.
CLKR/X ext

P-7

ns

Rise time, CLKR/X

tr(CKRX)See figure 34, reference M13.
CLKR/X ext

7ns

Fall time, CLKR/X

tf(CKRX)See figure 34, reference M14.
CLKR/X ext

7ns

Setup time, external FSR

tsu(FRH-

See figure 34, reference M15.

high before CLKR low

CKRL)

CLKR int

Hold time, external FSR
high after CLKR low

th(CKRLFRH)

See figure 34, reference M15.
CLKR ext

2

See figure 34, reference M16.
CLKR int

0

See figure 34, reference M16.
CLKR ext

6
18

Setup time, DR validtsu(DRV-See figure 34, reference M17.

before CLKR low

CKRL)

CLKR int

Hold time, DR valid after
CLKR lowth(CKRLDRV)See figure 34, reference M17.
CLKR ext

2

See figure 34, reference M18.
CLKR int

0

See figure 34, reference M18.
CLKR ext

6
18

Setup time, external FSX

tsu(FXH-

See figure 34, reference M19.

high before CLKX low

CKXL)

CLKX int

Hold time, external FSX
high after CLKX lowth(CKXLFXH)

18

See figure 34, reference M19.
CLKX ext

2

See figure 34, reference M20.
CLKX int

0

See figure 34, reference M20.
CLKX ext

6

ns

ns

ns

ns

ns

ns

See footnotes at end of table.

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97

SIZE

5962-06208

A
REVISION LEVEL

B

SHEET

32

TABLE I. Electrical performance characteristics - Continued.
Test

SymbolConditions 10/-55C  TC  +125C
unless otherwise specified

Group A Device
subgroups type

LimitsMin

McBSP Switching Requirements

Unit
Max

57/ 60/

Cycle time, CLKR/X

tc(CKRX)See figure 35, reference M1.
CLKR/X int

Pulse duration, CLKR/X
high

tw(CKRXH)

See figure 35, reference M2.
CLKR/X int

D–5
61/

D+5
61/

ns

Pulse duration, CLKR/X
low

tw(CKRXL)

See figure 35, reference M3.
CLKR/X int

C–5
61/

C+5
61/

ns

Delay time, CLKR high tointernal FSR validtd(CKRH-

See figure 35, reference M4.
CLKR int

04

ns

See figure 35, reference M4.
CLKR ext

3

27

See figure 35, reference M5.
CLKX int

0

4

See figure 35, reference M5.
CLKX ext

3

27

Delay time, CLKX high tointernal FSX valid

FRV)

td(CKXHFXV)Disable time, CLKX highto DX high impedance
following last data bittdis(CKXH-Delay time, CLKX high to
DX valid (This applies toall bits except the first bit
transmitted.)

td(CKXH-

9, 10, 11

All

2P

ns

See figure 35, reference M6.
CLKX int

8

See figure 35, reference M6.
CLKX ext

14

See figure 35, reference M7.
CLKX int

9

See figure 35, reference M7.
CLKX ext

28

Delay time, CLKX high to

See figure 35, reference M7.

8

DX valid

CLKX int, DXENA = 0

DXHZ)

DXV)

Delay time, CLKX high to
DX valid (Only applies tofirst bit transmitted whenin Data Delay 1 or 2
(XDATDLY = 01b or 10b)modes.)

See figure 35, reference M7.
CLKX ext, DXENA = 0

14

See figure 35, reference M7.
CLKX int, DXENA = 1

P+8

See figure 35, reference M7.
CLKX ext, DXENA = 1

P + 14

ns

ns

ns

ns

ns

See footnotes at end of table.

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97

SIZE

5962-06208

A
REVISION LEVEL

B

SHEET

33

TABLE I. Electrical performance characteristics - Continued.
Test

Enable time, CLKX high to
DX driven

Symbolten(CKXHDX)

Enable time, CLKX high to
DX driven (Only applies
to first bit transmitted
when in Data Delay 1 or 2
(XDATDLY = 01b or 10b)modes.)
Delay time, FSX high to
DX validtd(FXHDXV)Delay time, FSX high to
DX valid (Only applies
to first bit transmitted
when in Data Delay 0(XDATDLY = 00b)
mode.)
Enable time, FSX high to
DX driventen(FXHDX)

Conditions 10/-55C  TC  +125C
unless otherwise specified

Group A Device
subgroups type

LimitsMin

See figure 35, reference M8.
CLKX int, DXENA = 0

9, 10, 11

All

Unit
Max

0

See figure 35, reference M8.
CLKX ext, DXENA = 0

6

See figure 35, reference M8.
CLKX int, DXENA = 1

P

See figure 35, reference M8.
CLKX ext, DXENA = 1

P+6

ns

ns

See figure 35, reference M9.
FSX int, DXENA = 0

8

See figure 35, reference M9.
FSX ext, DXENA = 0

14

See figure 35, reference M9.
FSX int, DXENA = 1

P+8

See figure 35, reference M9.
FSX ext, DXENA = 1

P + 14See figure 35, reference M10.
FSX int, DXENA = 0

0

See figure 35, reference M10.

6

ns

ns

ns

FSX ext, DXENA = 0
Enable time, FSX high to
DX driven (Only applies
to first bit transmitted
when in Data Delay 0(XDATDLY = 00b)
mode.)

See figure 35, reference M10.
FSX int, DXENA = 1

P

See figure 35, reference M10.
FSX ext, DXENA = 1

P+6

ns

See footnotes at end of table.

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97

SIZE

5962-06208

A
REVISION LEVEL

B

SHEET

34

TABLE I. Electrical performance characteristics - Continued.
Test

SymbolConditions 10/-55C  TC  +125C
unless otherwise specified

Group A Device
subgroups type

Limits
Min

Unit
Max

McBSP as SPI Master or Slave Timing
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)
Setup time, DR valid
before CLKX low

Hold time, DR valid after
CLKX lowtsu(DRVCKXL)th(CKXLDRV)

Setup time, FSX low
before CLKX hightsu(BFXL-

Cycle time, CLKX

tc(CKX)

CKXH)

See figure 36, reference M30.
Master9, 10, 11

All

P - 10See figure 36, reference M30.
Slave

8P - 10

See figure 36, reference M31.
MasterP - 10See figure 36, reference M31.
Slave

8P - 10

See figure 36, reference M32.
Slave

8P + 10ns

See figure 36, reference M33.
Master2P

ns

See figure 36, reference M33.
Slave

16P

McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)
Hold time, FSX low after
CLKX lowth(CKXL-

Delay time, FSX low to
CLKX hightd(FXL-

Disable time, DX highimpedance following last
data bit from FSX hightdis(FXH-

Delay time, FSX low to
DX validns

ns

See figure 36, reference M25.
MasterP

ns

See figure 36, reference M28.
Master6

ns

See figure 36, reference M28.
Slave

6P + 6td(FXL-See figure 36, reference M29.

6

DXV)

Master

CKXH)

DXHZ)

9, 10, 11

All

62/

2P

FXL)

See figure 36, reference M24.
Masterns

See figure 36, reference M29.
Slave

ns

4P + 6

See footnotes at end of table.

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97

SIZE

5962-06208

A
REVISION LEVEL

B

SHEET

35

TABLE I. Electrical performance characteristics - Continued.
Test

SymbolConditions 10/-55C  TC  +125C
unless otherwise specified

Group A Device
subgroups type

LimitsMin

McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)
Setup time, DR valid
before CLKX highHold time, DR valid after
CLKX hightsu(DRVCKXH)th(CKXHDRV)

Setup time, FSX low
before CLKX hightsu(FXL-

Cycle time, CLKX

tc(CKX)

CKXH)

See figure 37, reference M39.
Master9, 10, 11All

th(CKXL-

Delay time, FSX low to
CLKX hightd(FXL-

Disable time, DX highimpedance following last
data bit from CLKX low
Delay time, FSX low to
DX validMax62/

P - 10ns

See figure 37, reference M39.
Slave

8P - 10

See figure 37, reference M40.
MasterP - 10See figure 37, reference M40.
Slave

8P - 10

See figure 37, reference M41.
Slave

16P + 10ns

See figure 37, reference M42.
Master2P

ns

See figure 37, reference M42.
Slave

16P

McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)
Hold time, FSX low after
CLKX lowUnit

ns

See figure 37, reference M35.
Master2P

nstdis(CKXL-See figure 37, reference M37.

P+6

ns

DXHZ)

MasterCKXH)

td(FXLDXV)

9, 10, 11

All

62/

P

FXL)

See figure 37, reference M34.
Masterns

See figure 37, reference M37.
Slave

7P + 6

See figure 37, reference M38.
Master6

See figure 37, reference M38.
Slave

4P + 6ns

See footnotes at end of table.

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97

SIZE

5962-06208

A
REVISION LEVEL

B

SHEET

36

TABLE I. Electrical performance characteristics - Continued.
Test

SymbolConditions 10/-55C  TC  +125C
unless otherwise specified

Group A Device
subgroups type

LimitsMin

McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)
Setup time, DR valid
before CLKX highHold time, DR valid after
CLKX hightsu(DRVCKXH)th(CKXHDRV)

Setup time, FSX low
before CLKX lowtsu(FXL-

Cycle time, CLKX

tc(CKX)CKXL)

See figure 38, reference M49.
Master9, 10, 11All

th(CKXH-

Delay time, FSX low to
CLKX lowtd(FXL-

Disable time, DX highimpedance following last
data bit from FSX high
Delay time, FSX low to
DX validMax62/

P - 10ns

See figure 38, reference M49.
Slave

8P - 10

See figure 38, reference M50.
MasterP - 10See figure 38, reference M50.
Slave

8P - 10

See figure 38, reference M51.
Slave

8P + 10ns

See figure 38, reference M52.
Master2P

ns

See figure 38, reference M52.
Slave

16P

McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)
Hold time, FSX low after
CLKX high

Unit

ns

See figure 38, reference M44.
MasterPnstdis(FXH-

See figure 38, reference M47.

6

ns

DXHZ)

MasterCKXL)

td(FXLDXV)

9, 10, 11

All

62/

2P

FXL)

See figure 38, reference M43.
Masterns

See figure 38, reference M47.
Slave

6P + 6

See figure 38, reference M48.
Master6

See figure 38, reference M48.
Slave

4P + 6ns

See footnotes at end of table.

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97

SIZE

5962-06208

A
REVISION LEVEL

B

SHEET

37

TABLE I. Electrical performance characteristics - Continued.
Test

SymbolConditions 10/-55C  TC  +125C
unless otherwise specified

Group A Device
subgroups type

LimitsMin

McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)
Setup time, DR valid
before CLKX low

Hold time, DR valid after
CLKX lowtsu(DRVCKXL)th(CKXLDRV)

Setup time, FSX low
before CLKX lowtsu(FXL-

Cycle time, CLKX

tc(CKX)CKXL)

See figure 39, reference M58.
Master9, 10, 11

All

Max
62/

P - 10th(CKXH-

Delay time, FSX low to
CLKX lowtd(FXL-

Disable time, DX highimpedance following last
data bit from CLKX high
Delay time, FSX low to
DX validns

See figure 39, reference M58.
Slave

8P - 10

See figure 39, reference M59.
MasterP - 10See figure 39, reference M59.
Slave

8P - 10

See figure 39, reference M60.
Slave

16P + 10ns

See figure 39, reference M61.
Master2P

ns

See figure 39, reference M61.
Slave

16P

McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)
Hold time, FSX low after
CLKX high

Unit

ns

See figure 39, reference M54.
Master 63/

2P

ns

tdis(CKXH-

See figure 39, reference M56.

P+6

ns

DXHZ)

MasterCKXL)

td(FXLDXV)

9, 10, 11

All

62/

P

FXL)

See figure 39, reference M53.
Master 63/

ns

63/

See figure 39, reference M56.
Slave

7P + 6

See figure 39, reference M57.
Master 63/

6

See figure 39, reference M57.
Slave

4P + 6ns

See footnotes at end of table.

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97

SIZE

5962-06208

A
REVISION LEVEL

B

SHEET

38

TABLE I. Electrical performance characteristics - Continued.
Test

SymbolConditions 10/-55C  TC  +125C
unless otherwise specified

Group A Device
subgroups type
Min

Flash Timing
Flash Parameters at 150-MHz SYSCLKOUT
Program time

Unit
Max

64/
35 TYPs

8K Sector

170 TYP

ms

16K Sector

320 TYP

ms

8K Sector

10S

16K Sector

11

S

Erase

75

mA

Program

35mA

16-Bit Word

Erase time

Limits9, 10, 11All

VDD3VFL current
consumption during theErase/Program cycle

IDD3VFLP

VDD current consumption
during Erase/Program
cycle

IDDP

140

mA

VDDIO current consumption
during Erase/Program
cycle

IDDIOP

20mA

Flash/OTP Access Timing
Paged Flash access timeta(fp)

Random Flash access time
OTP access time

65/
9, 10, 11

All

36

ns

ta(fr)

36

nsta(OTP)

60

ns

See footnotes on next sheet.

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97

SIZE

5962-06208

A
REVISION LEVEL

B

SHEET

39

TABLE I. Electrical performance characteristics - Continued.

1/

The following pins have no internal pullup/pulldown: GPIOE0, GPIOE1, GPIOF0, GPIOF1, GPIOF2, GPIOF3, GPIOF12,GPIOG4, and GPIOG5.

2/̅̅̅̅̅, TESTSEL, and ̅̅̅̅̅̅̅̅
The following pins have an internal pulldown: XMP/MC
TRST.

3/

Operational mode test conditions: All peripheral clocks are enabled. All PWM pins are toggled at 100 kHz. Data is
continuously transmitted out of the SCIA, SCIB, and CAN ports. The hardware multiplier is exercised. Code is running outof flash with 5 wait-states.

4/

IDLE mode test conditions: Flash is powered down. XCLKOUT is turned off. All peripheral clocks are on, except ADC.

5/STANDBY mode test conditions: Flash is powered down. Peripheral clocks are turned off. Pins without an internal
pullup/pulldown are tied high/low.

6/

HALT and STANDBY modes cannot be used when the PLL is disabled.

7/

HALT mode test conditions: Flash is powered down. Peripheral clocks are turned off. Pins without an internal
pullup/pulldown are tied high/low. Input clock is disabled.

8/

Max limit numbers are at +125C, and max voltage (VDD = 2.0 V; VDDIO, VDD3VFL, VDDA = 3.6 V).

9/IDDA includes current into V DDA1, VDDA2, VDD1, AVDDREFBG, and VDDAIO pins.

10/

See figure 3, herein. This test load circuit is used to measure all switching characteristics.

11/

The maximum value for ADCCLK frequency is25 MHz. For SYSCLKOUT values of 25 MHz or lower, ADCCLK has to be
SYSCLKOUT/2 or lower. ADCCLK = SYSCLKOUT is not a valid mode for any value of SYSCLKOUT.

12/

The clock provided at the XCLKIN pin generates the internal CPU clock cycle.

13/

A load of 40 pF is assumed for these parameters.

14/

H = 0.5tc(XCO)15/

The PLL must be used for maximum frequency operation.

16/

If external oscillator/clock sources are used, reset time has to be low at least for 1 ms after V DD reaches 1.5 V.

17/

Dependent on crystal/resonator and board design.

18/

The boot ROM reads the password locations. Therefore, this timing requirement includes the wakeup time for flash.

19/

Input Qualification Time (IQT) = [5 x QUALPRD x 2] * t c(SCO)

20/This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an
ISR (triggered by the wake-up) signal involves additional latency.

21/

Minimum limit = (2 + QUALSTDBY) * t c(CI), where QUALSTDBY is a 6-bit field in the LPMCR0 register.

22/

PWM refers to all PWM outputs on EVA and EVB.

23/

See the GPIO output timing for fall/rise times for PWM pins.

24/

PWM pin toggling frequency is limited by the GPIO output buffer switching frequency (20 MHz).

25/

PWM outputs may be 100%, 0%, or increments of tc(HCO) with respect to the PWM period.

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97

SIZE

5962-06208

A
REVISION LEVEL

B

SHEET

40

TABLE I. Electrical performance characteristics - Continued.

26/

The QUALPRD bit field can range from 0 (no qualification) through 0xFF (510 SYSCLKOUT cycles). The qualification
sampling period is 2n SYSCLKOUT cycles, where “n” is the value stored in the QUALPRD bit field. As an example, when
QUALPRD = 1, the qualification sampling period is 1 x 2 = 2 SYSCLKOUT cycles (i.e., the input is sampled every 2
SYSCLKOUT cycles). Six such samples will be taken over five sampling windows, each window being 2n SYSCLKOUT
cycles. For QUALPRD = 1, the minimum width that is needed is 5 x 2 = 10 SYSCLKOUT cycles. However, since theexternal signal is driven asynchronously, a 11-SYSCLKOUT-wide pulse ensures reliable recognition.

27/

Maximum input frequency to the QEP = min[HSPCLK/2, 20MHz].

28/

XCLKOUT = SYSCLKOUT29/

See figure 17 for an example diagram of the GPIO Input Qualifier for QUALPRD = 1.

30/

The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is cleared.

31/

tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1); t c(LCO) = LSPCLK cycle time32/

The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
NOTE: Internal clock prescalers must be adjusted such that the SPI clock speed is not greater than the I/O buffer speed
limit (20 MHz).

33/

The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is set.

34/

The MASTER/SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.

35/

The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).

36/

The MASTER/SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is set.

37/

During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes
alignment cycles.

38/

LR = Lead period, read access. AR = Active period, read access.

39/

TW = Trail period, write access.

40/

The first XREADY (Synch) sample occurs with respect to E in figure 25:
E = (XRDLEAD + XRDACTIVE) tc(XTIM)
When first sampled, if XREADY (Synch) is found to be high, then the access will complete. If XREADY (Synch) is found tobe low, it will be sampled again each tc(XTIM) until it is found to be high.
For each sample (n) the setup time (D) with respect to the beginning of the access can be calculated as:
D = (XRDLEAD + XRDACTIVE + n – 1) tc(XTIM) – tsu(XRDYsynchL)XCOHL ;where n is the sample number: n = 1, 2, 3, and so forth41/

The first XREADY (Asynch) sample occurs with respect to E in figure 26:
E = (XRDLEAD + XRDACTIVE - 2) tc(XTIM)
When first sampled, if XREADY (Asynch) is found to be high, then the access will complete. If XREADY (Asynch) is foundto be low, it will be sampled again each t c(XTIM) until it is found to be high.
For each sample, setup time from the beginning of the access can be calculated as:
D = (XRDLEAD + XRDACTIVE – 3 + n) tc(XTIM) – tsu(XRDYasynchL)XCOHL ;where n is the sample number: n = 1, 2, 3, and so forth

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97

SIZE

5962-06208

A
REVISION LEVEL

B

SHEET

41

TABLE I. Electrical performance characteristics - Continued.

42/

The first XREADY (Synch) sample occurs with respect to E in figure 27:
E = (XWRLEAD + XWRACTIVE) tc(XTIM)
When first sampled, if XREADY (Synch) is found to be high, then the access will complete. If XREADY (Synch) is found tobe low, it will be sampled again each tc(XTIM) until it is found to be high.
For each sample, the setup time from the beginning of the access can be calculated as:
D = (XWRLEAD + XWRACTIVE + n – 1) tc(XTIM) – tsu(XRDYsynchL)XCOHL ;where n is the sample number: n = 1, 2, 3, and so forth43/

The first XREADY (Asynch) sample occurs with respect to E in figure 28:
E = (XWRLEAD + XWRACTIVE - 2) tc(XTIM)
When first sampled, if XREADY (Asynch) is found to be high, then the access will complete. If XREADY (Asynch) is foundto be low, it will be sampled again each t c(XTIM) until it is found to be high.
For each sample, setup time from the beginning of the access can be calculated as:
D = (XWRLEAD + XWRACTIVE – 3 + n) tc(XTIM) – tsu(XRDYasynchL)XCOHL ;where n is the sample number: n = 1, 2, 3, and so forth

44/

When a low signal is detected on ̅̅̅̅̅̅̅̅̅̅̅XHOLD, all pending XINTF accesses will be completed before the bus is placed in ahigh-impedance state.

45/

The state of ̅̅̅̅̅̅̅̅̅̅̅XHOLD is latched on the rising edge of XTIMCLK.

46/

After the ̅̅̅̅̅̅̅̅̅̅̅XHOLD is detected low or high, all bus transitions and ̅̅̅̅̅̅̅̅̅̅̅̅̅XHOLDA transitions will occur with respect to the risingedge of XCLKOUT. Thus, for this mode where XCLKOUT = 1/2 XTIMCLK cycle earlier than the maximum value specified.

47/

Tested at 12.5 MHz ADCCLK.

48/

If SYSCLKOUT  25 MHz, ADC clock  SYSCLKOUT/2.

49/

The INL degrades for frequencies beyond 18.75 MHz – 25 MHz. Applications that require these sampling rates should
use a 20 k resistor as bias resistor on the ADCRESEXT pin. This improves overall linearity and typical current drawn by
the ADC will be a few mA more than 24.9 k bias.

50/

1 LSB has the weighted value of 3.0/4096 = 0.732 mV.

51/

A single internal band gap reference (5% accuracy) sources both ADCREFP and ADCREFM signals, and hence, thesevoltages track together. The ADC converter uses the difference between these two as its reference. The total gain error
will be the combination of the gain error shown here and the voltage reference accuracy (ADCREFP – ADCREFM). A
software-based calibration procedure is recommended for better accuracy.

52/

In this mode, the accuracy of external reference is critical for overall gain. The voltage difference (ADCREFP –ADCREFM) will determine the overall accuracy.

53/

Voltages above V DDA + 0.3 V or below VSS – 0.3 V applied to an analog input pin may temporarily affect the conversion ofanother pin. To avoid this, the analog inputs should be kept within these limits.

54/

Test conditions:

55/

IDDA – includes current into V DDA1/VDDA2 and AVDDREFBG

56/

These delays are necessary and recommended to make the ADC analog reference circuit stable before conversions are
initiated. If conversions are started without these delays, the ADC results will show a higher gain. For power down, allthree bits can be cleared at the same time.

SYSCLKOUT = 150 MHz
ADC module clock = 25 MHz
ADC performing a continuous conversion of all 16 channels in Mode A

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TABLE I. Electrical performance characteristics - Continued.

57/

Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timingreferences of that signal are also inverted.

58/

2P = 1/CLKG in ns. CLKG is the output of sample rate generator mux. CLKG = CLKSRG/(1 + CLKGDV).
CLKSRG can be LSPCLK, CLKX, CLKR as source. CLKSRG  (SYSCLKOUT/2). McBSP performance is limited by I/Obuffer switching speed.

59/Internal clock prescalers must be adjusted such that the McBSP clock (CLKG, CLKX, CLKR) speeds are not greater thanthe I/O buffer speed limit (20 MHz).

60/

2P = 1/CLKG in ns.

61/

C = CLKRX low pulse width = P
D = CLKRX high pulse width = P

62/

2P = 1/CLKG
For all SPI slave modes, CLKX has to be minimum of 8 CLKG cycles. Also CLKG should be LSPCLK/2 by setting CLKSM= CLKGDV = 1. With maximum LSPCLK speed of 75 MHz, CLKX maximum frequency will be LSPCLK/16, that is 4.5 MHz
and P = 13.3 ns.

63/

C = CLKX low pulse width = P
D = CLKX high pulse width = P

64/

Typical parameters as seen at room temperature using flash API V1 including function call overhead.

65/

For 150 MHz, PAGE WS = 5 and RANDOM WS = 5
For 135 MHz, PAGE WS = 4 and RANDOM WS = 4

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Case outline:
Terminal
Terminal
numberSymbol1
VDDAIOX
Terminal
number44

Terminal
SymbolPWM7

Terminal
number87

Terminal
SymbolCANRXA

Terminal
number130

Terminal
Symbol̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
XZCS6AND723ADCINB0
ADCINB1

45
46

PWM8
PWM9

88
89

SCITXDBSCIRXDB

131
132

TESTSEL̅̅̅̅̅̅̅̅
TRST

4
5
6
7

ADCINB2
ADCINB3
ADCINB4ADCINB5

47
48
49
50

PWM10
PWM11
PWM12
̅
XR/W

90
91
92
93

PWM1
PWM2
PWM3
PWM4

133
134
135
136

8

ADCINB6

51

VSS

94

XD[12]

137

TCK
EMU0
XA[12]
XD[14]
̅̅̅̅̅̅̅̅̅̅̅̅̅
XF_XPLLDIS

9
10
11
12
13
14
15
16
17

ADCINB7
ADCREFMADCREFPAVSSREFBGAVDDREFBG
VDDA1
VSSA1
ADCRESEXT̅̅̅̅̅XMP/MC

52
53
54
55
56
57
58
59
60

T3PWM_T3CMP
XD[7]
T4PWM_T4CMP
VDD
CAP4_QEP3VSS
CAP5_QEP4CAP6_QEPI2
̅̅̅̅̅̅̅̅̅̅̅
C4TRIP

95
96
97
98
99
100
101
102
103

XD[13]
PWM5
VSS
VDD
PWM6
T1PWM_T1CMP
XA[4]T2PWM_T2CMP
VSS

138
139
140
141
142
143
144
145
146

XA[13]VSS
VDD
XA[14]VDDIO
EMU1
XD[15]
XA[15]
̅̅̅̅̅̅̅
XINT1_XBIO

18

XA[0]

61

104

CAP1_QEP1147

XNMI_XINT13

19

MDRA

62

̅̅̅̅̅̅̅̅̅̅̅
C5TRIP̅̅̅̅̅̅̅̅̅̅̅
C6TRIP105

CAP2_QEP2

148

XINT2_ADCSOC

20
21
22

XD[0]
MDXA
VDD

63
64
65

VDDIO
XD[8]
TEST2

106
107
108

XA[5]
CAP3_QEPI1
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
T1CTRIP_PDPINTA

149
150
151

XA[16]VDD
SCITXDA

23
24
25
26

XD[1]
MCLKRA
MFSXA
XD[2]

66
67
68
69

TEST1
XD[9]
VDD3VFL
TDIRB

109
110
111
112

152
153
154
155

XA[17]SCIRXDAXA[18]
̅̅̅̅̅̅̅̅̅̅̅
XHOLD

27

MCLKXA70

TCLKINB

113

XA[6]
VDD
VSS
VDDIO
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
T2CTRIP/EVASOC

156

28
29
30
31
32
33

MFSRA
XD[3]
VDDIO
VSS
XD[4]
SPICLKA

71
72
73
74
75
76

114
115
116
117
118
119

TDIRA
TCLKINAXA[7]XCLKOUT
XA[8]̅̅̅̅̅̅̅̅̅̅̅
C1TRIP

157
158
159
160
161
162

34

SPISTEA77

XD[10]
XD[11]VDD
X2
X1/CLKIN
VSS̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
T3CTRIP_PDPINTB̅̅̅̅̅̅XRS
XREADYVDD1VSS1ADCBGREFIN
VSSA2
VDDA2

120

163

ADCINA7

35

XD[5]

78

XA[2]

121

̅̅̅̅̅̅̅̅̅̅̅
C2TRIP̅̅̅̅̅̅̅̅̅̅̅
C3TRIP164

ADCINA6

36
37

VDD
VSS

79
80

VDDIO
̅̅̅̅̅̅̅̅̅̅̅̅̅XHOLDA

122
123

XA[9]
TMS

165
166

ADCINA5ADCINA4

38

XD[6]

81

124

TDO

167

ADCINA339

SPISIMOA

82

̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
T4CTRIP/EVBSOC̅̅̅̅̅̅̅
XWE

125

VDD

168

ADCINA2

40
41

SPISOMIA̅̅̅̅̅̅̅
XRD

83
84

XA[3]
VSS

126
127

VSS
XA[10]

169
170

ADCINA1
ADCINA0

42
43

XA[1]
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
XZCS0AND1

85
86

CANTXA̅̅̅̅̅̅̅̅̅̅
XZCS2

128
129

TDI
XA[11]

171
172

ADCLO
VSSAIOFIGURE 1. Terminal connections.

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NOTE: 45 of the possible 96 interrupts are used on the device.

FIGURE 2. Functional block diagram.

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3.3-V Test Load Circuit

NOTE: Timing is provided at the device pin. For output timing analysis, the tester pin electronics and its transmission line
effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce thedesired transmission line effect. The transmission line is intended as a load only. It is not necessary to add or subtract
the transmission line delay (2 ns or longer) from the device timing.
Input requirements are tested with an input skew rate of  4 Volts per nanosecond (4 V/ns) at the device pin.

FIGURE 3. Timing waveforms and test circuits.

NOTES:
1. The relationship of XCLKIN to XCLKOUT depends on the divide factor chosen. The waveform relationship shown isintended to illustrate the timing parameters only and may differ based on configuration.
2. XCLKOUT configured to reflect SYSCLKOUT.

FIGURE 4. Timing waveforms and test circuits.

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NOTES:
1. The state of the GPIO pins is undefined (i.e., they could be input or output) until the 1.8-V (or 1.9-V) supply reaches atleast 1 V and the 3.3-V supply reaches 2.5 V.
2. VDDAn – VDDA1/VDDA2 and AVDDREFBG.
3. Upon power-up, SYSCLKOUT is XCLKIN/2 if the PLL is enabled. Since both the XTIMCLK and CLKMODE bits in the
XINTCNF2 register come up with a reset state of 1, SYSCLKOUT is further divided by 4 before it appears at
XCLKOUT. This explains why XCLKOUT = XCLKIN/8 during this phase.
4. After reset, the Boot ROM code executes instructions for 1260 SYSCLKOUT cycles (SYSCLKOUT = XCLKIN/2) andthen samples Boot Mode pins. Based on the status of the Boot Mode pin, the boot code branches to destination
memory or boot code function in ROM. The Boot Mode pins should be held high/low for at least 2520 XCLKIN cycles
from boot ROM execution time for proper selection of Boot modes.
If Boot ROM code executes after power-on conditions (in debugger environment), the Boot code execution time isbased on the current SYSCLKOUT speed. The SYSCLKOUT will be based on user environment and could be with orwithout PLL enabled.
FIGURE 5. Timing waveforms and test circuits.

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NOTES:
1. Upon power-up, SYSCLKOUT is XCLKIN/2 if the PLL is enabled. Since both the XTIMCLK and CLKMODE bits in the
XINTCNF2 register come up with a reset state of 1, SYSCLKOUT is further divided by 4 before it appears at
XCLKOUT. This explains why XCLKOUT = XCLKIN/8 during this phase.
2. The state of the GPIO pin is undefined (i.e., they could be input or output) until the 1.8-V (or 1.9-V) supply reaches atleast 1 V and the 3.3-V supply reaches 2.5 V.

FIGURE 6. Timing waveforms and test circuits.

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NOTE: After reset, the Boot ROM code executes instructions for 1260 SYSCLKOUT cycles (SYSCLKOUT = XCLKIN/2) andthen samples Boot Mode pins. Based on the status of the Boot Mode pin, the boot code branches to destination
memory or boot code function in ROM. The Boot Mode pins should be held high/low for at least 2520 XCLKIN cycles
from boot ROM execution time for proper selection of Boot modes.
If Boot ROM code executes after power-on conditions (in debugger environment), the Boot code execution time isbased on the current SYSCLKOUT speed. The SYSCLKOUT will be based on user environment and could be with orwithout PLL enabled.

FIGURE 7. Timing waveforms and test circuits.

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NOTES:
1. XCLKOUT = SYSCLKOUT
2. WAKE INT can be any enabled interrupt, WDINT, XNMI, or XRS.

FIGURE 8. Timing waveforms and test circuits.

NOTES:
A. IDLE instruction is executed to put the device into STANDBY mode.
B. The PLL block responds to the STANDBY signal. SYSCLKOUT is held for approximately 32 cycles before being
turned off. This 32-cycle delay enables the CPU pipe and any other pending operations to flush properly.
C. The device is now in STANDBY mode.
D. The external wake-up signal is driven active (negative edge triggered shown in example).
E. After a latency period, the STANDBY mode is exited.
F. Normal operation resumes. The device will respond to the interrupt (if enabled).
FIGURE 9. Timing waveforms and test circuits.

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XCLKOUT = SYSCLKOUTNOTES:
A. IDLE instruction is executed to put the device into HALT mode.
B. The PLL block responds to the HALT signal. SYSCLKOUT is held for another 32 cycles before the oscillator is turned
off and the CLKIN to the core is stopped. This 32-cycle delay enables the CPU pipe and any other pending operations
to flush properly.
C. Clocks to the device are turned off and the internal oscillator and PLL are shut down. The device is now in HALT modeand consumes absolute minimum power.
D. When XNMI is driven active (negative edge triggered shown, as an example), the oscillator is turned on; but the PLL is
not activated.
E. When XNMI is deactivated, it initiates the PLL lock sequence, which takes 131,072 X1/XCLKIN cycles.
F. When CLKIN to the core is enabled, the device will respond to the interrupt (if enabled), after a latency. The HALT
mode is now exited.
G. Normal operation resumes.

FIGURE 10. Timing waveforms and test circuits.

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NOTE: XCLKOUT = SYSCLKOUT
FIGURE 11. Timing waveforms and test circuits.

NOTE: XCLKOUT = SYSCLKOUT
FIGURE 12. Timing waveforms and test circuits.

FIGURE 13. Timing waveforms and test circuits.

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FIGURE 14. Timing waveforms and test circuits.

NOTES:
1. XCLKOUT = SYSCLKOUT
2. TxCTRIP – T1CTRIP, T2CTRIP, T3CTRIP, or T4CTRIPCxTRIP C1TRIP, C2TRIP, C3TRIP, C4TRIP, C5TRIP, or C6TRIP
PDPINTx PDPINTA or PDPINTB
3. PWM refers to all the PWM pins in the device (i.e., PWMn and TnPWM pins or PWM pin pair relevant to each CxTRIP
pin). The state of the PWM pins after PDPINTx is taken high depends on the state of the FCOMPOE bit.

FIGURE 15. Timing waveforms and test circuits.

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FIGURE 16. Timing waveforms and test circuits.

NOTES:
1. This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It
can vary from 00 to 0xFF. Input qualification is not applicable when QUALPRD = 00. For any other value “n”, thequalification sampling period in 2n SYSCLKOUT cycles (i.e., at every 2n SYSCLKOUT cycle, the GPIO pin will besampled). Six consecutive samples must be of the same value for a given input to be recognized.
2. For the qualifier to detect the change, the input should be stable for 10 SYSCLKOUT cycles or greater. In other words,
the inputs should be stable for (5 x QUALPRD X 2) SYSCLKOUT cycles. This would ensure six sampling windows for
detection to occur. Since external signals are driven asynchronously, an 11-SYSCLKOUT-wide pulse ensures reliable
recognition.

FIGURE 17. Timing waveforms and test circuits.

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NOTE: The pulse width requirement for general-purpose input is applicable for the XBIO and ADCSOC pins as well.

FIGURE 18. Timing waveforms and test circuits.

NOTE: In the master mode, SPISTE goes active 0.5tc(SPC) before valid SPI clock edge. On the trailing end of the word, the
SPISTE will go inactive 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit.

FIGURE 19. Timing waveforms and test circuits.

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NOTE: In the master mode, SPISTE goes active 0.5tc(SPC) before valid SPI clock edge. On the trailing end of the word, the
SPISTE will go active 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit.

FIGURE 20. Timing waveforms and test circuits.

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NOTE: In the slave mode, the SPISTE signal should be asserted low at least 0.5tc(SPC) before the valid SPI clock edge andremain low for at least 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit.

FIGURE 21. Timing waveforms and test circuits.

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NOTE: In the slave mode, the SPISTE signal should be asserted low at least 0.5tc(SPC) before the valid SPI clock edge andremain low for at least 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit.

FIGURE 22. Timing waveforms and test circuits.

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NOTES:
1. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert analignment cycle before an access to meet this requirement.
2. During alignment cycles, all signals will transition to their inactive state.
3. For USEREADY = 0, the external XREADY input signal is ignored.
4. XA[0:18] will hold the last address put on the bus during inactive cycles, including alignment cycles.

FIGURE 23. Timing waveforms and test circuits.

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NOTES:
1. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert analignment cycle before an access to meet this requirement.
2. During alignment cycles, all signals will transition to their inactive state.
3. For USEREADY = 0, the external XREADY input signal is ignored.
4. XA[0:18] will hold the last address put on the bus during inactive cycles, including alignment cycles.

FIGURE 24. Timing waveforms and test circuits.

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NOTES:
1. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert analignment cycle before an access to meet this requirement.
2. During alignment cycles, all signals will transition to their inactive state.
3. During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes
alignment cycles.
4. For each sample, setup time from the beginning of the access (D) can be calculated as:
D = (XRDLEAD + XRDACTIVE + n – 1) tc(XTIM) – tsu(XRDYsynchL)XCOHL
where n is the sample number: n = 1, 2, 3, and so forth.
5. Reference for the first sample is with respect to this point:
E = (XRDLEAD + XRDACTIVE) tc(XTIM)FIGURE 25. Timing waveforms and test circuits.

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NOTES:
1. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert analignment cycle before an access to meet this requirement.
2. During alignment cycles, all signals will transition to their inactive state.
3. During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes
alignment cycles.
4. For each sample, setup time from the beginning of the access (D) can be calculated as:
D = (XRDLEAD + XRDACTIVE - 3+ n) tc(XTIM) – tsu(XRDYasynchL)XCOHL
where n is the sample number: n = 1, 2, 3, and so forth.
5. Reference for the first sample is with respect to this point:
E = (XRDLEAD + XRDACTIVE - 2) tc(XTIM)FIGURE 26. Timing waveforms and test circuits.

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NOTES:
1. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert analignment cycle before an access to meet this requirement.
2. During alignment cycles, all signals will transition to their inactive state.
3. During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes
alignment cycles.
4. For each sample, setup time from the beginning of the access (D) can be calculated as:
D = (XWRLEAD + XWRACTIVE + n – 1) tc(XTIM) – tsu(XRDYsynchL)XCOHL
where n is the sample number: n = 1, 2, 3, and so forth.
5. Reference for the first sample is with respect to this point:
E = (XWRLEAD + XWRACTIVE) tc(XTIM)FIGURE 27. Timing waveforms and test circuits.

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NOTES:
1. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert analignment cycle before an access to meet this requirement.
2. During alignment cycles, all signals will transition to their inactive state.
3. During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes
alignment cycles.
4. For each sample, setup time from the beginning of the access (D) can be calculated as:
D = (XWRLEAD + XWRACTIVE – 3 + n) tc(XTIM) – tsu(XRDYasynchL)XCOHL
where n is the sample number: n = 1, 2, 3, and so forth.
5. Reference for the first sample is with respect to this point:
E = (XWRLEAD + XWRACTIVE - 2) tc(XTIM)FIGURE 28. Timing waveforms and test circuits.

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NOTES:
1. All pending XINTF accesses are completed.
2. Normal XINTF operation resumes.

FIGURE 29. Timing waveforms and test circuits.

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NOTES:
1. All pending XINTF accesses are completed.
2. Normal XINTF operation resumes.

FIGURE 30. Timing waveforms and test circuits.

FIGURE 31. Timing waveforms and test circuits.

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FIGURE 32. Timing waveforms and test circuits.

FIGURE 33. Timing waveforms and test circuits.

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FIGURE 34. Timing waveforms and test circuits.

FIGURE 35. Timing waveforms and test circuits.

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FIGURE 36. Timing waveforms and test circuits.

FIGURE 37. Timing waveforms and test circuits.

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FIGURE 38. Timing waveforms and test circuits.

FIGURE 39. Timing waveforms and test circuits.

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4. VERIFICATION
4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with
MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan
shall not affect the form, fit, or function as described herein.
4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted
on all devices prior to qualification and technology conformance inspection.
4.2.1 Additional criteria for device classes Q and V.
a.

The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in thedevice manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained underdocument revision level control of the device manufacturer's Technology Review Board (TRB) in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shallspecify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified inmethod 1015 of MIL-STD-883.

b.

Interim and final electrical test parameters shall be as specified in table II herein.

c.

Additional screening for device class V beyond the requirements of device class Q shall be as specified in
MIL-PRF-38535, appendix B.

4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be inaccordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for groups
A, B, C, D, and E inspections (see 4.4.1 through 4.4.4).
4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with
MIL-PRF-38535 including groups A, B, C, D, and E inspections and as specified herein.
4.4.1 Group A inspection.
a.

Tests shall be as specified in table II herein.

b.

For device classes Q and V, subgroups 7 and 8 shall include verifying the functionality of the device.

c.

Subgroup 4 (CI and CO measurements) shall be measured only for initial test and after process or design changes
which may affect input or output capacitance.

4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table II herein.
4.4.2.1 Additional criteria for device classes Q and V. The steady-state life test duration, test condition and test temperature,
or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The
test circuit shall be maintained under document revision level control by the device manufacturer's TRB in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the
inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of
MIL-STD-883.

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TABLE II. Electrical test requirements.
Test requirements

Interim electricalparameters (see 4.2)
Final electricalparameters (see 4.2)
Group A test
requirements (see 4.4)
Group C end-point electricalparameters (see 4.4)
Group D end-point electricalparameters (see 4.4)
Group E end-point electricalparameters (see 4.4)

Subgroups(in accordance with
MIL-PRF-38535, table III)
DeviceDeviceclass Q
class V1, 7, 91, 7, 91, 2, 3, 7, 8a, 8b
9, 10, 11 1/
1, 2, 3, 4, 7, 8a, 8b
9, 10, 11
1, 7, 91, 2, 3, 7, 8a, 8b
9, 10, 11 2/
1, 2, 3, 4, 7, 8a, 8b
9, 10, 11
1, 7, 91, 7, 91, 7, 9------1/ PDA applies to subgroup 1.
2/ PDA applies to subgroups 1 and 7.

4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table II herein.
4.4.4 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness assured(see 3.5 herein).
a.

End-point electrical parameters shall be as specified in table II herein.

b.

For device classes Q and V, the devices or test vehicle shall be subjected to radiation hardness assured tests as
specified in MIL-PRF-38535 for the RHA level being tested. All device classes must meet the postirradiation end-point
electrical parameter limits as defined in table I at TA = +25C 5C, after exposure, to the subgroups specified in table II
herein.

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5. PACKAGING
5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device classes
Q and V.
6. NOTES
6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications(original equipment), design applications, and logistics purposes.
6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor
prepared specification or drawing.
6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record forthe individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal , or emailcommunication.
6.3 Record of users. Military and industrial users should inform DLA Land and Maritime when a system application requires
configuration control and which SMD's are applicable to that system. DLA Land and Maritime will maintain a record of users andthis list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectro nic
devices (FSC 5962) should contact DLA Land and Maritime -VA, telephone (614) 692-8108.
6.4 Comments. Comments on this drawing should be directed to DLA Land and Maritime -VA, Columbus, Ohio 43218-3990,
or telephone (614) 692-0591.
6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in
MIL-PRF-38535 and MIL-HDBK-1331.
6.6 Sources of supply.
6.6.1 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in MIL-HDBK103 and QML-38535. The vendors listed in MIL-HDBK-103 and QML-38535 have submitted a certificate of compliance (see 3.6
herein) to DLA Land and Maritime -VA and have agreed to this drawing.

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6.7 Signal descriptions.
Signal Descriptions.
Terminal
Name

Terminal
Number

I/O/Z
2/

PU/PD
3/

1/

Description
XINTF Signals.

XA[18]

154

O/Z

-

XA[17]

152

O/Z

-

XA[16]

149

O/Z

-

XA[15]

145

O/Z

-

XA[14]

141

O/Z

-

XA[13]

138

O/Z

-

XA[12]

135

O/Z

-

XA[11]

129

O/Z

-

XA[10]

127

O/Z

-

XA[9]

122

O/Z

-

XA[8]

118

O/Z

-

XA[7]

116

O/Z

-

XA[6]

109

O/Z

-

XA[5]

106

O/Z

-

XA[4]

101

O/Z

-

XA[3]

83

O/Z

-

XA[2]

78

O/Z

-

XA[1]

42

O/Z

-

XA[0]

18

O/Z

-

XD[15]

144

I/O/Z

PU

XD[14]

136

I/O/Z

PU

XD[13]

95

I/O/Z

PU

XD[12]

94

I/O/Z

PU

XD[11]

72

I/O/Z

PU

XD[10]

71

I/O/Z

PU

XD[9]

67

I/O/Z

PU

XD[8]

64

I/O/Z

PU

XD[7]

53

I/O/Z

PU

XD[6]

38

I/O/Z

PU

XD[5]

35

I/O/Z

PU

XD[4]

32

I/O/Z

PU

XD[3]

29

I/O/Z

PU

XD[2]

26

I/O/Z

PU

XD[1]

23

I/O/Z

PU

XD[0]

20

I/O/Z

PU

19-bit XINTF Address Bus

16-bit XINTF Data Bus

See footnotes at end of table.

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Signal Descriptions – Continued.
Terminal
Name

Terminal
Number

I/O/Z
2/

PU/PD
3/

1/

Description
XINTF Signals - Continued.

̅̅̅̅̅
XMP/MC

17

I

PD̅̅̅̅̅̅̅̅̅̅̅
XHOLD

155

I

PU

̅̅̅̅̅̅̅̅̅̅̅̅̅XHOLDA80

O/Z-̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
XZCS0AND1

43

O/Z

-

̅̅̅̅̅̅̅̅̅̅
XZCS2

86

O/Z

-

̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
XZCS6AND7

130

O/Z

-

̅̅̅̅̅̅̅
XWE

82

O/Z

-

Write Enable. Active-low write strobe. The write strobe waveform is
specified, per zone basis, by the Lead, Active, and Trail periods in the
XTIMINGx registers.

̅̅̅̅̅̅̅
XRD

41

O/Z

-

Read Enable. Active-low read strobe. The read strobe waveform is
specified, per zone basis, by the Lead, Active, and Trail periods in the̅̅̅̅̅̅̅ and XWE̅̅̅̅̅̅̅ signals are mutually
XTIMINGx registers. NOTE: The XRD
exclusive.

̅
XR/W

50

O/Z

-

Read Not Write Strobe. Normally held high. When low, XR/W indicateswrite cycle is active; when high, XR/W indicates read cycle is active.

XREADY

157

I

PU

Ready Signal. Indicates peripheral is ready to complete the access whenasserted to 1. XREADY can be configured to be a synchronous or an
asynchronous input. See the timing diagrams for more details.

Microprocessor/Microcomputer Mode Select. Switches between
microprocessor and microcomputer mode. When high, Zone 7 is enabled on
the external interface. When low, Zone 7 is disabled from the externalinterface, and on-chip boot ROM may be accessed instead. This signal islatched into the XINTCNF2 register on a reset and the user can modify this̅̅̅̅̅ pin is ignored after reset.
bit in software. The state of the XMP/MC̅̅̅̅̅̅̅̅̅̅̅
External Hold Request. XHOLD, when active (low), requests the XINTF torelease the external bus and place all buses and strobes into a highimpedance state. The XINTF will release the bus when any current accessis complete and there are no pending accesses on the XINTF.
̅̅̅̅̅̅̅̅̅̅̅̅̅ is driven active (low) when the XINTF
External Hold Acknowledge. XHOLDA̅̅̅̅̅̅̅̅̅̅̅ request. All XINTF buses and strobe signals will be inhas granted a XHOLD̅̅̅̅̅̅̅̅̅̅̅̅̅ is released when the XHOLD̅̅̅̅̅̅̅̅̅̅̅ signal isa high-impedance state. XHOLDA
released. External devices should only drive the external bus when̅̅̅̅̅̅̅̅̅̅̅̅̅XHOLDA is active (low).
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ is active (low) when
XINTF Zone 0 and Zone 1 Chip Select. XZCS0AND1
an access to the XINTF Zone 0 or Zone 1 is performed.
XINTF Zone 2 Chip Select. ̅̅̅̅̅̅̅̅̅̅
XZCS2 is active (low) when an access to the
XINTF Zone 2 is performed.
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ is active (low) when
XINTF Zone 6 and Zone 7 Chip Select. XZCS6AND7
an access to the XINTF Zone 6 or Zone 7 is performed.

JTAG and Miscellaneous Signals.
X1/XCLKIN

75

I

Oscillator Input − input to the internal oscillator. This pin is also used to feed
an external clock. The 28x can be operated with an external clock source,
provided that the proper voltage levels be driven on the X1/XCLKIN pin. Itshould be noted that the X1/XCLKIN pin is referenced to the 1.8-V (or 1.9-V)
core digital power supply (VDD), rather than the 3.3-V I/O supply (VDDIO). A
clamping diode may be used to clamp a buffered clock signal to ensure thatthe logic-high level does not exceed VDD (1.8 V or 1.9 V) or a 1.8-V oscillator
may be used.

X2

74

O

Oscillator Output.

See footnotes at end of table.

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Signal Descriptions – Continued.
Terminal
Name

Terminal
Number

I/O/Z
2/

PU/PD
3/

1/

Description

JTAG and Miscellaneous Signals - Continued.
XCLKOUT

117

O-

Output clock derived from SYSCLKOUT to be used for external wait-state
generation and as a general-purpose clock source. XCLKOUT is either thesame frequency, 1/2 the frequency, or 1/4 the frequency of SYSCLKOUT. At
reset, XCLKOUT = SYSCLKOUT/4. The XCLKOUT signal can be turned off
by setting bit 3 (CLKOFF) of the XINTCNF2 register to 1.

TESTSEL̅̅̅̅̅̅
XRS

131

I

PD

Test Pin. Reserved for TI. Must be connected to ground.

156

I/O PUPU

Device Reset (in) and Watchdog Reset (out).
Device reset. ̅̅̅̅̅̅XRS causes the device to terminate execution. The PC will
point to the address contained at the location 0x3FFFC0. When ̅̅̅̅̅̅XRS isbrought to a high level, execution begins at the location pointed to by the PC.
This pin is driven low by the DSP when a watchdog reset occurs. During
watchdog reset, the ̅̅̅̅̅̅XRS pin will be driven low for the watchdog reset
duration of 512 XCLKIN cycles.
The output buffer of this pin is an open-drain with an internal pullup (100 A,typical). It is recommended that this pin be driven by an open-drain device.

TEST1

66

I/O

-

Test Pin. Reserved for TI. On F281x devices, TEST1 must be left
unconnected.

TEST2

65

I/O

-

̅̅̅̅̅̅̅̅
TRST

132

I

PD

Test Pin. Reserved for TI. On F281x devices, TEST2 must be left
unconnected.
JTAG test reset with internal pulldown. ̅̅̅̅̅̅̅̅TRST, when driven high, gives thescan system control of the operations of the device. If this signal is notconnected or driven low, the device operates in its functional mode, and thetest reset signals are ignored.
NOTE: Do not use pullup resistors on ̅̅̅̅̅̅̅̅
TRST; it has an internal pulldown
device. In a low-noise environment, ̅̅̅̅̅̅̅̅
TRST can be left floating. In a highnoise environment, an additional pulldown resistor may be needed. The
value of this resistor should be based on drive strength of the debugger pods
applicable to the design. A 2.2-k resistor generally offers adequate
protection. Since this is application-specific, it is recommended that eachtarget board is validated for proper operation of the debugger and theapplication.

TCK

133

I

PU

JTAG test clock with internal pullup.

TMS

123

I

PU

JTAG test-mode select (TMS) with internal pullup. This serial control input isclocked into the TAP controller on the rising edge of TCK.

TDI

128

I

PU

JTAG test data input (TDI) with internal pullup. TDI is clocked into theselected register (instruction or data) on a rising edge of TCK.

TDO

124

O/Z

-

EMU0

134

I/O/Z

PU

EMU1

143

I/O/Z

PU

JTAG scan out, test data output (TDO). The contents of the selected
register (instruction or data) is shifted out of TDO on the falling edge of TCK.
Emulator pin 0. When ̅̅̅̅̅̅̅̅
TRST is driven high, this pin is used as an interrupt toor from the emulator system and is defined as input/output through the JTAG
scan.
Emulator pin 1. When ̅̅̅̅̅̅̅̅
TRST is driven high, this pin is used as an interrupt toor from the emulator system and is defined as input/output through the JTAGscan.

See footnotes at end of table.

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Signal Descriptions – Continued.
Terminal
Name

Terminal
Number

I/O/Z
2/

PU/PD
3/

1/

Description
ADC Analog Input Signals.

ADCINA7163I

ADCINA6164I

ADCINA5165

I

ADCINA4

166

I

ADCINA3167

I

ADCINA2

168

I

ADCINA1

169

I

ADCINA0170

I

ADCINB79I

ADCINB68I

ADCINB57I

ADCINB46I

ADCINB35I

ADCINB24I

ADCINB1

3I

8-Channel analog inputs for Sample-and-Hold A. The ADC pins should not
be driven before VDDA1, VDDA2, and VDDAIO pins have been fully
powered up.

8-Channel analog inputs for Sample-and-Hold B. The ADC pins should not
be driven before VDDA1, VDDA2, and VDDAIO pins have been fully
powered up.

ADCINB02

I

ADCREFP11O

ADC Voltage Reference Output (2 V). Requires a low ESR (50 m − 1.5 )
ceramic bypass capacitor of 10 F to analog ground. (Can accept externalreference input (2 V) if the software bit is enabled for this mode. 1−10 F
low ESR capacitor can be used in the external reference mode.)

ADCREFM10OADC Voltage Reference Output (1 V). Requires a low ESR (50 m − 1.5 )
ceramic bypass capacitor of 10 F to analog ground. (Can accept externalreference input (1 V) if the software bit is enabled for this mode. 1−10 F
low ESR capacitor can be used in the external reference mode.)

ADCRESEXT

16OADC External Current Bias Resistor (24.9 k 5).

ADCBGREFIN

160

I

Test Pin. Reserved for TI. Must be left unconnected.

AVSSREFBG

12IADC Analog GND.

AVDDREFBG

13I

ADC Analog Power (3.3-V).

ADCLO

171

I

Common Low Side Analog Input. Connect to analog ground.

VSSA1

15

I

ADC Analog GND.

VSSA2

161

I

ADC Analog GND.

VDDA1

14

I

ADC Analog 3.3-V Supply.

VDDA2

162

I

ADC Analog 3.3-V Supply.

VSS1

159

I

ADC Digital GND.

I

ADC Digital 1.8-V (or 1.9 V) Supply.

VDD1

158

VDDAIO

1

3.3-V Analog I/O Power Pin.

VSSAIO

172

Analog I/O Ground Pin.

See footnotes at end of table.

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Signal Descriptions – Continued.
Terminal
Name

Terminal
Number

I/O/Z
2/

PU/PD
3/

1/

Description
Power Signals.

VDD

22

VDD

36

VDD

55

VDD

73

VDD

98

VDD

110

VDD

125

VDD

140

VDD

150

VSS

31

VSS

37

VSS

51

VSS

57

VSS

76

VSS

84

VSS

97

VSS

103

VSS

111

VSS

126

VSS

139

VDDIO

30

VDDIO

63

VDDIO

79

VDDIO

112

VDDIO

142

VDD3VFL

68

1.8-V or 1.9-V Core Digital Power Pins.

Core and Digital I/O Ground Pins.

3.3-V I/O Digital Power Pins.

3.3-V Flash Core Power Pin. This pin should be connected to 3.3 V at all
times after power-up sequence requirements have been met. This pin isused as VDDIO in ROM parts and must be connected to 3.3 V in ROM parts
as well.

See footnotes at end of table.

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Signal Descriptions – Continued.

GPIO

Peripheral Signal

Terminal
Number

I/O/Z
2/

PU/PD
3/

4/

Description

GPIO or Peripheral Signals.
GPIOA or EVA Signals.
GPIOA0

PWM1 (O)

90

I/O/Z

PU

GPIO or PWM Output Pin #1.

GPIOA1

PWM2 (O)

91

I/O/Z

PU

GPIO or PWM Output Pin #2.

GPIOA2

PWM3 (O)

92

I/O/Z

PU

GPIO or PWM Output Pin #3.

GPIOA3

PWM4 (O)

93

I/O/Z

PU

GPIO or PWM Output Pin #4.

GPIOA4

PWM5 (O)

96

I/O/Z

PU

GPIO or PWM Output Pin #5.

GPIOA5

PWM6 (O)

99

I/O/Z

PU

GPIO or PWM Output Pin #6.

GPIOA6T1PWM_T1CMP (I)

100

I/O/Z

PU

GPIO or Timer 1 Output.

GPIOA7

T2PWM_T2CMP (I)

102

I/O/Z

PU

GPIO or Timer 2 Output.

GPIOA8

CAP1_QEP1 (I)

104

I/O/Z

PU

GPIO or Capture Input #1.

GPIOA9CAP2_QEP2 (I)

105

I/O/Z

PU

GPIO or Capture Input #2.

GPIOA10

CAP3_QEPI1 (I)

107

I/O/Z

PU

GPIO or Capture Input #3.

GPIOA11TDIRA (I)

114

I/O/Z

PU

GPIO or Timer Direction.

GPIOA12TCLKINA (I)̅̅̅̅̅̅̅̅̅̅̅
C1TRIP (I)

115

I/O/Z

PU

GPIO or Timer Clock Input.

119

I/O/Z

PU

GPIO or Compare 1 Output Trip.

120

I/O/Z

PU

GPIO or Compare 2 Output Trip.

GPIOA15̅̅̅̅̅̅̅̅̅̅̅ (I)C2TRIP̅̅̅̅̅̅̅̅̅̅̅ (I)
C3TRIP

121

I/O/Z

PU

GPIO or Compare 3 Output Trip.

GPIOB0

PWM7 (O)

44

I/O/Z

PU

GPIO or PWM Output Pin #7.

GPIOB1

PWM8 (O)

45

I/O/Z

PU

GPIO or PWM Output Pin #8.

GPIOB2

PWM9 (O)

46

I/O/Z

PU

GPIO or PWM Output Pin #9.

GPIOB3

PWM10 (O)

47

I/O/Z

PU

GPIO or PWM Output Pin #10.

GPIOB4

PWM11 (O)

48

I/O/Z

PU

GPIO or PWM Output Pin #11.

GPIOB5

PWM12 (O)

49

I/O/Z

PU

GPIO or PWM Output Pin #12.

GPIOB6

T3PWM_T3CMP (I)

52

I/O/Z

PU

GPIO or Timer 3 Output.

GPIOB7

T4PWM_T4CMP (I)

54

I/O/Z

PU

GPIO or Timer 4 Output.

GPIOB8

CAP4_QEP3 (I)

56

I/O/Z

PU

GPIO or Capture Input #4.

GPIOA13GPIOA14GPIOB or EVB Signals.

GPIOB9

CAP5_QEP4 (I)

58

I/O/Z

PU

GPIO or Capture Input #5.

GPIOB10

CAP6_QEPI2 (I)

59

I/O/Z

PU

GPIO or Capture Input #6.

GPIOB11TDIRB (I)

69

I/O/Z

PU

GPIO or Timer Direction.

GPIOB12TCLKINB (I)̅̅̅̅̅̅̅̅̅̅̅ (I)
C4TRIP

70

I/O/Z

PU

GPIO or Timer Clock Input.

60

I/O/Z

PU

GPIO or Compare 4 Output Trip.

̅̅̅̅̅̅̅̅̅̅
C5TRIP (I)̅̅̅̅̅̅̅̅̅̅̅
C6TRIP (I)

61

I/O/Z

PU

GPIO or Compare 5 Output Trip.

62

I/O/Z

PU

GPIO or Compare 6 Output Trip.

GPIOB13GPIOB14GPIOB15

See footnotes at end of table.

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97

SIZE

5962-06208

A
REVISION LEVEL

B

SHEET

79

Signal Descriptions – Continued.

GPIO

Peripheral Signal

Terminal
Number

I/O/Z
2/

4/

PU/PD
3/

Description

GPIOD or EVA Signals.
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ (I)T1CTRIP_PDPINTA
̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅̅ (I)
T2CTRIP/EVASOC

108

I/O/Z

PU

Timer 1 Compare Output Trip.

113

I/O/Z

PU

Timer 2 Compare Output Trip or External ADC
Start-of-Conversion EV-A.

77

I/O/Z

PU

Timer 3 Compare Output Trip.

GPIOD6

̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
T3CTRIP_PDPINTB (I)̅̅̅̅̅̅̅̅̅̅̅̅̅/EVBSOC̅̅̅̅̅̅̅̅̅̅̅̅̅ (I)
T4CTRIP

81

I/O/Z

PU

Timer 4 Compare Output Trip or External ADC
Start-of-Conversion EV-B.

GPIOE0̅̅̅̅̅̅̅ (I)XINT1_XBIO

146

I/O/Z

GPIOE1

XINT2_ADCSOC (I)148

GPIOE2

XNMI_XINT13 (I)

147

GPIOF0SPISIMOA (O)

39

I/O/Z

-

GPIO or SPI slave in, master out.

GPIOF1SPISOMIA (I)

40

I/O/Z

-

GPIO or SPI slave out, master in.

GPIOF2SPICLKA (I/O)

33

I/O/Z

-

GPIO or SPI clock.

GPIOF3SPISTEA (I/O)

34

I/O/Z

-

GPIO or SPI slave transmit enable.

GPIOD0GPIOD1

GPIOD or EVB Signals.
GPIOD5GPIOE or Interrupt Signals.
-

GPIO or XINT1 or ̅̅̅̅̅̅̅XBIO input.

I/O/Z

-

GPIO or XINT2 or ADC start of conversion.

I/O/Z

PU

GPIO or XNMI or XINT13.

GPIOF or SPI Signals.

GPIOF or SCI-A Signals.
GPIOF4SCITIXDA (O)

151

I/O/Z

PU

GPIO or SCI asynchronous serial port TX
data.

GPIOF5SCIRXDA (I)

153

I/O/Z

PU

GPIO or SCI asynchronous serial port RX
data.

GPIOF or CAN Signals.
GPIOF6CANTXA (O)

85

I/O/Z

PU

GPIO or eCAN transmit data.

GPIOF7CANRXA (I)

87

I/O/Z

PU

GPIO or eCAN receive data.

GPIOF8MCLKXA (I/O)

27

I/O/Z

PU

GPIO or transmit clock.

GPIOF or McBSP Signals.
GPIOF9MCLKRA (I/O)

24

I/O/Z

PU

GPIO or receive clock.

GPIOF10MFSXA (I/O)

25

I/O/Z

PU

GPIO or transmit frame synch.

GPIOF11MFSRA (I/O)

28

I/O/Z

PU

GPIO or receive frame synch.

GPIOF12MDXA (O)

21

I/O/Z

-

GPIO or transmitted serial data.

GPIOF13MDRA (I)

19

I/O/Z

PU

GPIO or received serial data.

See footnotes at end of table.

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97

SIZE

5962-06208

A
REVISION LEVEL

B

SHEET

80

Signal Descriptions – Continued.

GPIO

Peripheral Signal

Terminal
Number

I/O/Z
2/

PU/PD
3/

4/

Description

GPIOF or XF CPU Output Signal.
GPIOF14̅̅̅̅̅̅̅̅̅̅̅̅̅ (O)
XF_XPLLDIS

137

I/O/Z

PU

This pin has three functions:
1. XF - General-purpose output pin.
2. XPLLDIS - This pin will be sampled duringreset to check if the PLL needs to be disabled.
The PLL will be disabled if this pin is sensed
low. HALT and STANDBY modes cannot be
used when the PLL is disabled.
3. GPIO - GPIO function.

GPIOG or SCI-B Signals.
GPIOG4SCITXDB (O)

88

I/O/Z

-

GPIO or SCI asynchronous serial port transmit
data.

GPIOG5SCIRXDB (I)

89

I/O/Z

-

GPIO or SCI asynchronous serial port receive data.

1/

Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1
pins, which are 8 mA.

2/

I = Input, O = Output, Z = High impedance.

3/

PU = Pin has internal pullup; PD = Pin has internal pulldown.

4/

Typical drive strength of the output buffer for all pins [except TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins] is 4 mA
typical.

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97

SIZE

5962-06208

A
REVISION LEVEL

B

SHEET

81

Possible PLL Configuration Modes.

PLL Mode

Remarks

SYSCLKOUT

PLL Disabled̅̅̅̅̅̅̅̅̅̅̅̅̅ pin low upon reset. PLL block is completely
Invoked by tying XPLLDIS
disabled. Clock input to the CPU (CLKIN) is directly derived from the clock
signal present at the X1/XCLKIN pin.

XCLKINPLL Bypassed

Default PLL configuration upon power-up, if PLL is not disabled. The PLL
itself is bypassed. However, the /2 module in the PLL block divides theclock input at the X1/XCLKIN pin by two before feeding it to the CPU.

XCLKIN/2

PLL Enabled

Achieved by writing a non-zero value “n” into PLLCR register. The /2
module in the PLL block now divides the output of the PLL by two before
feeding it to the CPU.

(XCLKIN * n)/2

Minimum Required Wait-States at Different Frequencies.

1/

SYSCLKOUT (MHz)SYSCLKOUT (ns)Page Wait-State

1/

Random Wait-State

150

6.67

5

5

120

8.33

4

4

100

10

3

3

75

13.33

2

2

50

20

1

1

30

33.33

1

1

25

40

0

1

15

66.67

0

1

4

250

0

1

1/ 2/

Page Wait State = [ (ta(fp)/tc(SCO)) – 1 ] (round up to the next highest integer), or 0, whichever is larger.
Random Wait State = [ (ta(fr)/tc(SCO)) – 1 ] (round up to the next highest integer), or 1, whichever is larger.

2/

Random wait state must be greater than or equal to 1.

STANDARD
MICROCIRCUIT DRAWINGDLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97

SIZE

5962-06208

A
REVISION LEVEL

B

SHEET

82

STANDARD MICROCIRCUIT DRAWING BULLETIN
DATE: 24-05-07
Approved sources of supply for SMD 5962-06208 are listed below for immediate acquisition information only andshall be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will berevised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and acertificate of compliance has been submitted to and accepted by DLA Land and Maritime-VA. This information
bulletin is superseded by the next dated revision of MIL-HDBK-103 and QML-38535. DLA Land and Maritime
maintains an online database of all current sources of supply at https://landandmaritimeapps.dla.mil/programs/smcr/.

Standard
microcircuit drawing
PIN 1/

VendorCAGE
numberVendorsimilar
PIN 2/

5962-0620801QXC

01295

SMJ320F2812HFGM150

1/ The lead finish shown for each PIN representing a hermetic package isthe most readily available from the manufacturer listed for that part. If thedesired lead finish is not listed contact the vendor to determine its
availability.
2/ Caution. Do not use this number for item acquisition. Items acquired tothis number may not satisfy the performance requirements of thisdrawing.

Vendor CAGE
number01295

Vendor nameand address
Texas Instruments, Inc.
Semiconductor Group
8505 Forest Lane
P.O. Box 660199
Dallas, TX 75243

The information contained herein is disseminated for convenience only and theGovernment assumes no liability whatsoever for any inaccuracies in theinformation bulletin.