REVISIONSLTR

DESCRIPTIONDATE (YR-MO-DA)APPROVEDA

Update boilerplate paragraphs to current VID description requirements.
- PHN

23-08-24

Muhammad A. Akbar

CURRENT DESIGN ACTIVITY CAGE CODE 16236
HAS CHANGED NAMES TO:
DLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
Prepared in accordance with ASME Y14.24

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PMIC N/A
Original date of drawing
YY MM DD

PREPARED BY
Phu H. Nguyen

https://www.dla.mil/LandandMaritime

TITLE

CHECKED BY
Phu H. Nguyen
APPROVED BY

18-03-01

DEFENSE SUPPLY CENTER, COLUMBUS
COLUMBUS, OHIO 43218-3990

MICROCIRCUIT, LINEAR-DIGITAL, DUAL-CORE
MICROCONTROLLER, MONOLITHIC SILICON

Thomas M. HessSIZE

CAGE CODE

A

REV A

16236

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PAGE

V62/18601

1 OF 80

AMSC N/A
DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.

5962-V143-23

1. SCOPE
1.1 Scope. This drawing documents the general requirements of a high performance Dual-Core Microcontrollers microcircuit, with
an operating temperature range of -55ºC to +125ºC.
1.2 Vendor Item Drawing Administrative Control Number. The manufacturer’s PIN is the item of identification. The vendor item
drawing establishes an administrative control number for identifying the item on the engineering documentation:
V62/18601-

Drawing
number01

X

F

Device type(see 1.2.1)

Case outline(see 1.2.2)

Lead finish(see 1.2.3)

1.2.1 Device type(s).
Device type

Generic

01

Circuit function

TMS320F28377D –EP

Dual-Core Microcontrollers

1.2.2 Case outline(s). The case outlines are as specified herein.
Outline letter

Number of pins

JEDEC PUB 95

X
Y

337
176

JEDEC MO-026

Package style
Ball Grid Array Package (BGA)
Quad Flatpack Package

1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer:
Finish designator

Material

A
B
C
D
E
F
Z

Hot solder dip
Tin-lead plate
Gold plate
PalladiumGold flash palladium
Tin-lead alloy
Other______________
1/

Devices listed on this drawing are supplied to lead finish “F”. The solder ball material contains compositions of Sn = 63%,
Pb = 34.5%, Ag = 2 %, and Sb = 0.5%.

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1.3 Absolute maximum ratings.

1/ 2/

Supply voltage:
VDDIO with respect to VSS ................................................................................. -0.3 V to 4.6 V
VDD3VFL with respect to VSS .............................................................................. -0.3 V to 4.6 V
VDDOSC with respect to VSS .............................................................................. -0.3 V to 4.6 V
VDD with respect to VSS ................................................................................... -0.3 V to 1.5 V
Analog voltage
VDDA with respect to VSSA ............................................................................... -0.3 V to 4.6 V
Input voltage VIN(3.3 V) .......................................................................................... -0.3 V to 4.6 V
Output Voltage
VO .................................................................................................................... -0.3 V to 4.6 V
Input claim voltage:
Digital input (per pin), IIK (VIN < VSS or VIN > VDDIO) .......................................... -20 mA to 20 mA
Analog input (per pin), IIKANALOG (VIN < VSSA or VIN > VDDA) .............................. -20 mA to 20 mA
Total for all inputs, IIKTOTAL (VIN < VSS/VSSA or VIN > VDDIO/VDDA) ...................... -20 mA to 20 mA
Output current: - Digital output (per pin), IOUT ........................................................ -20 mA to 20 mA
Operating temperature range, TJ ............................................................................ -55°C to +150°C
Storage temperature range, Tstg ............................................................................. -65°C to 150°C 3/
1.4 Recommended operating conditions.
Device supply voltage, I/O, VDDIO ............................................................................ 3.14 to 3.47 V 4/
Device supply voltage, VDD .................................................................................... 1.14 V to 1.26 V
Supply ground, VSS ................................................................................................ 0 V
Analog supply voltage, VDDA ................................................................................... 3.14 V to 3.47 V
Analog ground, VSSA ............................................................................................... 0 V
Junction temperature, TJ ........................................................................................ -55°C to +125°C 5/
1.5 ESD Ratings
Electrostatic discharge (ESD):
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 6/
Case outline X ........................................................................................ ±2000 V
Case outline Y ........................................................................................ ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22 7/Case outline X ........................................................................................ ±500 V
Case outline Y ........................................................................................ ±500 V_____________
1/

2/
3/
4/
5/
6/
7/

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stressratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended
operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device
reliability.
All voltage values are with respect to VSS, unless otherwise noted.
Long-term high-temperature storage or extended use at maximum temperature conditions may result in a reduction of overall
device life. For additional information, see manufacturer data: Semiconductor and IC Package Thermal Metrics.
VDDIO, VDD3VFL, and VDDOSC should be maintained within 0.3 V of each other.
Operation above TJ = 105°C for extended duration will reduce the lifetime of the device. See manufacturer Calculating Useful
Lifetimes of Embedded Processors for more information.
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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1.4 Thermal resistance Characteristics.

Case outline X

Junction to case thermal resistance, RθJC
Junction to board thermal resistance, RθJB
Junction to free air thermal resistance, Rθja (High k PCB)
Junction to moving air thermal resistance, RθJMA

Junction-to-package top PsiJT
Junction to board, PsiJB

°C/W
8/
8.8
11.6
23.2
19.0
17.8
16.5
0.2
0.3
0.4
0.5
11.4
11.3
11.2
11.0

AIR FLOW(lfm) 9/
N/A
N/A
0
150
250
500
0
150
250
500
0
150
250
500

Case outline Y
°C/W
8/
10.2
7.9
19.4
12.8
11.4
10.1
0.11
0.24
0.33
0.42
6.1
5.5
5.4
5.3

AIR FLOW(lfm) 9/
N/A
N/A
0
150
250
500
0
150
250
500
0
150
250
500

2. APPLICABLE DOCUMENTSJEDEC – SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC)JEP95
JESD 51-2
JESD 51-3
JESD51-7
JESD51-9

–
–
–
–
–

JEDEC JS-001 –JESD22–
JEP155
JEP157––

Registered and Standard Outlines for Semiconductor Devices
Integrated Circuits Thermal Test Method Environment Conditions – Natural Convection (Still Air)
Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages.
High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
Test Boards for Area Array Surface Mount Package Thermal Measurements.
Joint JEDEC/ESDA standard for electrostatic discharge sensitivity test – Human Body Model (HBM)
Qualification Testing for Plastic Encapsulated Solid State Devices – Electro Static Discharge (ESD)
protection
Recommended ESD Target Levels For HBM/MM Qualification
Recommended ESD-CDM Target Levels(Copies of these documents are available online at https://www.jedec.org.)______________
8/
9/

These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see JESD51-2,
JESD51-3, JESD51-7, JESD51-9:
lfm = linear feet per minute

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3. REQUIREMENTS
3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as
follows:
A.
B.
C.

Manufacturer’s name, CAGE code, or logo
Pin 1 identifier
ESDS identification (optional)

3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable)
above.
3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics areas specified in 1.3, 1.4, and table I herein.
3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein.
3.5 Diagrams.
3.5.1

Case outline. The case outline shall be as shown in 1.2.2 and figure 1.

3.5.2

Terminal connections. The terminal connections shall be as shown in figure 2.

3.5.3

Functional block diagram. The functional block diagram shall be as shown in figure 3.

3.5.4

Power-on Reset. The Power-on Reset shall be as shown in figure 4.

3.5.5

Warm Reset. The Warm Reset shall be as shown in figure 5.

3.5.6

JTAG timing. The JTAG timing shall be as shown in figure 6.

3.5.7

General Purpose Output timing. The General Purpose Output timing shall be as shown in figure 7.

3.5.8

Sampling Mode. The Sampling Mode shall be as shown in figure 8.

3.5.9

General-Purpose Input Timing. The General-Purpose Input Timing shall be as shown in figure 9.

3.5.10External interrupt Timing. The External interrupt Timing shall be as shown in figure 10.

3.5.11

External interrupt Timing. The External interrupt Timing shall be as shown in figure 11.

3.5.12

STANDBY Entry and Exit timing diagram. The STANDBY Entry and Exit timing diagram shall be as shown in figure 12.

3.5.13

HALT Entry and Exit timing diagram. The HALT Entry and Exit timing diagram shall be as shown in figure 13.

3.5.14

HIBERNATE Entry and Exit timing diagram. The HIBERNATE Entry and Exit timing diagram shall be as shown in figure
14.

3.5.15

Asynchronous Memory Read Timing. The Asynchronous Memory Read Timing shall be as shown in figure 15.

3.5.16EMxWAIT Read Timing Requirements. The EMxWAIT Read Timing Requirements shall be as shown in figure 16.

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3.5.17

Asynchronous Memory Write Timing. The Asynchronous Memory Write Timing shall be as shown in figure 17.

3.5.18EMxWAIT Write Timing Requirements The EMxWAIT Write Timing Requirements shall be as shown in figure 18.

3.5.19Basic SDRAM Read Operation. The Basic SDRAM Read Operation shall be as shown in figure 19.

3.5.20

Basic SDRAM Write Operation. The Basic SDRAM Write Operation shall be as shown in figure 20.

3.5.21

Single-Ended Input Model. The Single-Ended Input Model shall be as shown in figure 21.

3.5.22Differential Input Model. The Differential Input Model shall be as shown in figure 22.

3.5.23

ADC Timings for 12-Bit Mode. The ADC Timings for 12-Bit Mode shall be as shown in figure 23.

3.5.24

ADC Timings for 16-Bit Mode. The ADC Timings for 16-Bit Mode shall be as shown in figure 24.

3.5.25CMPSS Comparator Input Referred Offset. The CMPSS Comparator Input Referred Offset shall be as shown in figure 25.

3.5.26CMPSS Comparator Hysteresis. The CMPSS Comparator Hysteresis shall be as shown in figure 26.

3.5.27CMPSS DAC Static Offset. The CMPSS DAC Static Offset shall be as shown in figure 27.

3.5.28CMPSS DAC Static Gain. The CMPSS DAC Static Gain shall be as shown in figure 28.

3.5.29CMPSS DAC Static Linearity. The CMPSS DAC Static Linearity shall be as shown in figure 29.

3.5.30Buffered DAC Offset. The Buffered DAC Offset shall be as shown in figure 30.

3.5.31

Buffered DAC Gain. The Buffered DAC Gain shall be as shown in figure 31.

3.5.32

Buffered DAC Linearity. The Buffered DAC Linearity shall be as shown in figure 32.

3.5.33

PWM Hi-Z Characteristics. The PWM Hi-Z Characteristics shall be as shown in figure 33.

3.5.343.5.35���������������
ADCSOCAO or ���������������
ADCSOCBO Timing. The ���������������
ADCSOCAO or ���������������
ADCSOCBO Timing shall be as shown in figure 34.

3.5.36

SDFM Timing Diagram – Mode 1. The SDFM Timing Diagram – Mode 1 shall be as shown in figure 36.

3.5.37

SDFM Timing Diagram – Mode 2. The SDFM Timing Diagram – Mode 2 shall be as shown in figure 37.

3.5.38

SDFM Timing Diagram – Mode 3. The SDFM Timing Diagram – Mode 3 shall be as shown in figure 38.

3.5.39McBSP Receive Timing. The McBSP Receive Timing shall be as shown in figure 39.

3.5.40McBSP Transmit Timing. The McBSP Transmit Timing shall be as shown in figure 40.

3.5.41

McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0. The McBSP Timing as SPI Master or Slave: CLKSTP= 10b, CLKXP = 0 shall be as shown in figure 41.

3.5.42

McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0. The McBSP Timing as SPI Master or Slave: CLKSTP= 11b, CLKXP = 0 shall be as shown in figure 42.

SDFM Timing Diagram – Mode 0. The SDFM Timing Diagram – Mode 0 shall be as shown in figure 35.

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3.5.43

McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1. The McBSP Timing as SPI Master or Slave: CLKSTP= 10b, CLKXP = 1 shall be as shown in figure 43.

3.5.44

McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1. The McBSP Timing as SPI Master or Slave: CLKSTP= 11b, CLKXP = 1 shall be as shown in figure 44.

3.5.45SPI Master Mode External Timing (Clock Phase = 0). The SPI Master Mode External Timing (Clock Phase = 0) shall be as
shown in figure 45.

3.5.46

SPI Master Mode External Timing (Clock Phase = 1). The SPI Master Mode External Timing (Clock Phase = 1) shall be as
shown in figure 46.

3.5.47SPI Slave Mode External Timing (Clock Phase = 0). The SPI Slave Mode External Timing (Clock Phase = 0) shall be as
shown in figure 47.

3.5.48SPI Slave Mode External Timing (Clock Phase = 1). The SPI Slave Mode External Timing (Clock Phase = 1) shall be as
shown in figure 48.

3.5.49High-Speed SPI Master Mode External Timing (Clock Phase = 0). The High-Speed SPI Master Mode External Timing(Clock Phase = 0) shall be as shown in figure 49.

3.5.50High-Speed SPI Master Mode External Timing (Clock Phase = 1). The High-Speed SPI Master Mode External Timing(Clock Phase = 1) shall be as shown in figure 50.

3.5.51High-Speed SPI Slave Mode External Timing (Clock Phase = 0). The High-Speed SPI Slave Mode External Timing (ClockPhase = 0) shall be as shown in figure 51.

3.5.52High-Speed SPI Slave Mode External Timing (Clock Phase = 1). The High-Speed SPI Slave Mode External Timing (ClockPhase = 1) shall be as shown in figure 52.

3.5.53µPP Single Data Rate (SDR) Receive Timing. The µPP Single Data Rate (SDR) Receive Timing shall be as shown in figure
53.

3.5.54µPP Double Data Rate (DDR) Receive Timing. The µPP Double Data Rate (DDR) Receive Timing shall be as shown in figure
54.

3.5.55µPP Single Data Rate (SDR) Transmit Timing. The µPP Single Data Rate (SDR) Transmit Timing shall be as shown in figure
55.

3.5.56µPP Double Data Rate (DDR) Transmit Timing. The µPP Double Data Rate (DDR) Transmit Timing shall be as shown infigure 56.

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TABLE I. Electrical performance characteristics
Test

SymbolTest conditions

Limits2/
High-level output voltage

VOH

Low-level output voltage

VOL

High-level output source current for all
output pins
Low-level output sink current for all
output pins

IOH

High-level input
voltage (3.3 V)

Low-level input
voltage (3.3 V)
Input current

Pin leakage

VIH

All other pins

VIL

Analog (except
ADCINB0 or
DACOUTx)
ADCINB0
DACOUTx

Input capacitanceMin

IOH = IOH MINIOH = –100 μA
IOL = IOL MAX
IOL = 100 μA

TypIpulldown
Ipullup

ILEAK

Unit
Max

VDDIO * 0.8
VDDIO – 0.2
0.4
0.2
-4

IOL

GPIO0–GPIO7,
GPIO42–
GPIO43,
GPIO46–GPIO47

Digital inputs with
Pulldown 3/
Digital inputs withpullup enabled
3/
Digital1/

4mA

VDDIO * 0.7

VDDIO + 0.3

V2.0
VSS – 0.3

VDDIO + 0.3
0.8

V
V

VDDIO = 3.3 V
VIN = VDDIOVDDIO = 3.3 V
VIN = 0 V

120

µA

150

µA

Pullups disabled
0 V ≤ VIN ≤ VDDIO

2
2

µA
µA

0 V ≤ VIN ≤ VDDA
2
66
2

CI

11 4/

µA
µA
pF

105

V/s

SystemPower Sequencing - Supply Ramp Rate
Supply ramp rate

VDDIO, VDD, VDDA, VDD3VFL,
330
VDDOSC with respect to VSS������) Timing Requirements See FIGURE 4 and FIGURE 5
Reset Timing - Reset (𝐗𝐗𝐗𝐗𝐗𝐗

Hold time for boot-mode pinsth(boot-mode)
1.5
Pulse duration, XRS low on warm reset
tw(RSL2)
3.2
������) Switching Characteristics See FIGURE 4 and FIGURE 5
Reset Timing - Reset (𝐗𝐗𝐗𝐗𝐗𝐗
Pulse duration, XRS driven low by device
tw(RSL1)
after supplies are stable
Pulse duration, reset pulse generated bytw(WDRS)
watchdog

ms
µs
100

µs

512tc(OSCCLK)

cyclesSee footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

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PAGE 8TABLE I. Electrical performance characteristics - Continued. 1/
Test

Input Clock Frequency

SymbolTest conditions

2/
System - Clock Specifications

Limits
Min

Unit

Typ

Max

Frequency, X1/X2, from external crystal orf(XTAL)10
resonator
Frequency, X1, from external oscillator (PLL
2f(X1)
enabled)Frequency, X1, from external oscillator (PLL2disabled)
Frequency, AUXCLKIN, from externalf(AUXI)2
oscillator
X1 Input Level Characteristics When Using an External Clock Source (Not a Crystal)
Valid low-level input voltage

X1 VIL–0.3

Valid high-level input voltage

X1 VIH

0.7 * VDDIO

20

MHz

25

MHz

100

MHz

60

MHz

0.3 *
VDDIO
VDDIO +
0.3

V

ns
ns
ns

V

X1 Timing Requirements
Fall time, X1
Rise time, X1
Pulse duration, X1 low as a percentage oftc(X1)
Pulse duration, X1 high as a percentage oftc(X1)AUXCLKIN Timing Requirements
Fall time, AUXCLKIN
Rise time, AUXCLKIN
Pulse duration, AUXCLKIN low as apercentage of tc(XCI)
Pulse duration, AUXCLKIN high as apercentage of tc(XCI)
PLL Lock Timestf(X1)
tr(X1)
tw(X1L)

45%

6
6
55%

tw(X1H)

45%

55%

ns

tf(AUXI)
tr(AUXI)
tw(AUXL)

45%

6
6
55%

ns
ns
ns

tw(AUXH)

45%

55%

ns

Lock time, Main PLL (X1, from external
oscillator)t(PLL)

Lock time, USB PLL (AUXCLKIN, fromexternal oscillator)t(USB)

50 μs +
2500 *
tc(OSCCLK)
5/50 μs +
2500 *
tc(OSCCLK)
5/

µs

µs

See footnote at end of table.

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PAGE 9TABLE I. Electrical performance characteristics - Continued. 1/
Test

Internal Clock Frequencies

SymbolTest conditions

Limits2/
System - Clock Specifications- Continued

Min

Typ

Unit
Max

Frequency, device (system) clockf(SYSCLK)2

200 6/MHz

Period, device (system) clocktc(SYSCLK)

5 6/

500

ns

Frequency, system PLL output (before
SYSCLK divider)f(PLLRAWCLK)

120

400

MHz

Frequency, auxiliary PLL output (before
AUXCLK divider)f(AUXPLLRAWCLK)

120

400

MHz

Frequency, AUXPLLCLKf(AUXPLL)

2

60

MHz

Frequency, PLLSYSCLKf(PLL)

2

200 6/MHz

Frequency, LSPCLK

60

f(LSP)

2

200 6/MHz

Period, LSPCLK

tc(LSPCLK)

5 6/

500

ns

Frequency, OSCCLK (INTOSC1 or
INTOSC2 or XTAL or X1)f(OSCCLK)

clock

MHz

100

MHz

100

MHz

50

MHz

tf(XCO)

5

ns

tr(XCO)

5ns

Frequency, EPWMCLK

f(EPWM)

Frequency, HRPWMCLK

f(HRPWM)

See

respective60

Output Clock Frequency
Frequency, XCLKOUT

f(XCO)XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
Fall time, XCLKOUT
Rise time, XCLKOUT

9/ 10/

Pulse duration, XCLKOUT low

tw(XCOL)

H-2

H+2

ns

Pulse duration, XCLKOUT hightw(XCOH)

H-2

H+2

ns

CL1, CL2

12

24

pF

7

pF

Crystal Oscillator Parameters
Load capacitance
Crystal shunt capacitance

C0

Crystal Oscillator Electrical Characteristics
Start-up timef = 20 MHz
ESR MAX = 50 Ω
CL1 = CL2 = 24 pF
C0 = 7 pF

11/Crystal drive level (DL)Internal Oscillator Electrical Characteristics
Frequency, INTOSC1 and INTOSC2Frequency stability at room temperature
Frequency stability over VDD
Frequency stability
Start-up and settling time2f(INTOSC)
f(INTOSC-

9.7
30ºC, Nominal VDD
30ºC
-3.0%

STABILITY)

f(INTOSC-ST)

10.0
±0.1%
±0.2%

ns

1

mW

10.3

MHz

3.0%
20

µs

See footnote at end of table.

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TABLE I. Electrical performance characteristics - Continued. 1/
Test

SymbolLimits2/
System - - Flash Parameters

Flash Parameters
Program Time

Test conditions

12/

Erase Time at < 25 cycles

13/

Erase Time at 50k cycles 13/
Write/erase cycles

Typ

Max

128 data bits + 16
ECC bits

40

300

µs

8KW sector

90

180

ms

32KW sector

360

720

ms

8KW sector

25

50

ms

32KW sector

30

55

ms

8KW sector

105

4000

ms

32KW sector

110

Nwec

Data retention duration at TJ = 85°C
JTAG Timing Requirements

Min

Unit

4000

ms

20000

cyclestretention

20

years

See FIGURE 6

1

Cycle time, TCK

tc(TCK)

66.66

ns

1a

Pulse duration, TCK high (40% of tc)

tw(TCKH)

26.66

ns

1b

Pulse duration, TCK low (40% of tc)

tw(TCKL)

26.66

ns

3

Input setup time, TDI valid to TCK hightsu(TDI-TCKH)

13

ns

Input setup time, TMS valid to TCK hightsu(TMS-

13

ns

Input hold time, TDI valid from TCK highth(TCKH-TDI)

7

ns

Input hold time, TMS valid from TCK highth(TCKH-TMS)

7

ns

TCKH)

4

JTAG Switching Characteristics
2

System - Emulation/JTAG
See FIGURE 6

Delay time, TCK low to TDO validtd(TCKL-TDO)

6

25

ns

System - GPIO Electrical Data and Timing
General-Purpose Output Switching Characteristics
See FIGURE 7
Rise time, GPIO switching low to hightr(GPO)All GPIOs

8

14/

ns

Fall time, GPIO switching high to lowtf(GPO)All GPIOs

8

14/

ns

Toggling frequency, GPO pins

tfGPO

General-Purpose Input Timing Requirements

See FIGURE 8 and FIGURE 925

Sampling periodtw(SP)

Input qualifier sampling window

Pulse duration, GPIO low/highMHz

QUALPRD = 0

1tc(SYSCLK)

cyclesQUALPRD ≠ 0

2tc(SYSCLK)*QUALPRD

cyclestw(IQSW)

tw(SP) * (n–1)
15/cyclestw(GPI)

2tc(SYSCLK)

cycles16/

tw(IQSW) +tw(SP) +1tc(SYSCLK)

cyclesSee footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
16236
REV

A

DWG NO.
V62/18601
PAGE 11TABLE I. Electrical performance characteristics - Continued. 1/
Test

SymbolTest conditions
2/

External Interrupt Timing Requirements

System - Interrupts
See FIGURE 10 17

Pulse duration, INT input low/hightw(INT)

External Interrupt Switching Characteristics
Delay time, INT low/high to interruptvector fetch 18/
IDLE Mode Timing Requirements

Lim its
Min

Units
Max

Synchronous

2tc(SYSCLK)

cyclesWith qualifiertw(IQSW) + tw(SP) +1tc(SYSCLK)

cyclesSee FIGURE 10

17/
tw(IQSW) +14tc(SYSCLK)

td(INT)

tw(IQSW) + tw(SP)+ 14tc(SYSCLK)

cyclesSystem - Low-Power Modes
See FIGURE 11 17/

Pulse duration, external wake-up

tw(WAKE)signalWithout input qualifier2tc(SYSCLK)

cyclesWith input qualifier2tc(SYSCLK) +tw(IQSW)

cyclesIDLE Mode Switching Characteristics

See FIGURE 11 17/

Delay time, external wake signal toprogram execution resume 19/

td(WAKE-

Wakeup from Flash– Flash module in active state
Wakeup from Flash

Without input qualifier

40tc(SYSCLK)

cyclesWith input qualifier

40tc(SYSCLK) +tw(WAKE)cyclesWithout input qualifier– Flash module in sleep state6700tc(SYSCLK)

cycles

6700tc(SYSCLK) +tw(WAKE) 20/

cyclesWithout input qualifier

25tc(SYSCLK)

cyclesWith input qualifier

25tc(SYSCLK) +tw(WAKE)cyclesWith input qualifier

Wakeup from RAM

STANDBY Mode Timing Requirements
Pulse duration, external wake-up
signalcyclesIDLE)

See FIGURE 12
tw(WAKE-INT)QUALSTDBY = 0 |2tc(OSCCLK)QUALSTDBY > 0 | cycles(2 + QUALSTDBY)tc(OSCCLK)
21/

3tc(OSCCLK)

cycles(2 +QUALSTDBY)* tc(OSCCLK)

cyclesSTANDBY Mode Switching Characteristics
Delay time, IDLE instruction
executed to XCLKOUT stop

XCOS)

Delay time, external wake signal
to program execution resume 22/

td(WAKE-

Wakeup from flash– Flash module in active statetd(IDLE-

16tc(INTOSC1)

cyclescycles

175tc(SYSCLK) +tw(WAKE-INT)

cyclesWakeup from flash– Flash module in sleep state6700tc(SYSCLK)+ tw(WAKE-INT) 20/

cyclesWakeup from RAM

3tc(OSC) +15tc(SYSCLK) +tw(WAKE-INT)

cyclesSTBY)

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
16236
REV

A

DWG NO.
V62/18601
PAGE 12TABLE I. Electrical performance characteristics - Continued. 1/
Test

SymbolTest conditions

Lim its

2/
HALT Mode Timing Requirements

Min

Units
Max

System - Low-Power Mode – Continued.
See FIGURE 13

Pulse duration, GPIO wake-up signal
23/
Pulse duration, �����XRS wake-up signal 23/

tw(WAKE-GPIO)

toscst + 2tc(OSCCLK)

cyclestw(WAKE-XRS)

toscst + 8tc(OSCCLK)

cyclesHALT Mode Switching Characteristics

See FIGURE 13

Delay time, IDLE instruction executed to
XCLKOUT stoptd(IDLE-XCOS)Delay time, external wake signal end to
CPU1 program execution resumetd(WAKE-HALT)

16tc(INTOSC1)

cyclescycles• Wakeup from flash– Flash module in active state75tc(OSCCLK)
20/

cycles• Wakeup from flash– Flash module in sleep state

17500tc(OSCCLK)

cycles75tc(OSCCLK)

cycles• Wakeup from RAM
HIBERNATE Mode Timing Requirements
Pulse duration, �������������HIBWAKE signal
Pulse duration, �����XRS wake-up signal

See FIGURE 14
tw(HIBWAKE)

40µs

tw(WAKEXRS)

40µs

HIBERNATE Mode Switching Characteristics

See FIGURE 14

Delay time, IDLE instruction executed to
XCLKOUT stoptd(IDLE-XCOS)

30tc(SYSCLK)

cyclesDelay time, external wake signal to lO
Restore function starttd(WAKE-HIB)

1.5

ms

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
16236
REV

A

DWG NO.
V62/18601
PAGE 13TABLE I. Electrical performance characteristics - Continued. 1/
Test

SymbolTest conditions

Lim its

2/

Min

Units
Max

System - External Memory Interface (EMIF)
EMIF Electrical Data and Timing - Asynchronous RAM See FIGURE 15 through FIGURE 18
EMIF Asynchronous Memory Timing Requirements 24/
EMIF clock periodE

tc(SYSCLK)

ns

tw(EM_WAIT)

2E

nstsu(EMDV-EMOEH)

15

nsth(EMOEH-EMDIV)

0ns

Setup Time, EMxWAIT asserted before
end of Strobe Phase 25/

tsu(EMOEL-

4E + 20

ns

Setup Time, EMxWAIT asserted before
end of Strobe Phase( 25/tsu(EMWEL-

4E + 20

ns

Pulse duration, EMxWAIT assertionand deassertion

2

Reads
12
13
14

Setup time, EMxD[y:0] valid before����������
EMxOE highHold time, EMxD[y:0] valid after ����������
EMxOE
high

EMWAIT)

Writes28

EMWAIT)

EMIF Asynchronous Memory Switching Characteristics 24/ 26/ 27/
Reads and Writes
1

Turn around timetd(TURNAROUND)(TA)*E–3(TA)*E+2

ns(RS+RST+RH+2)*
E–3(RS+RST+RH+2)*
E+2

ns(RS+RST+RH+2+(EWC*16))*E–3(RS+RST+RH+2+(EWC*16))*E+2

ns(RS)*E–3(RS)*E+2

ns

-3

2

ns

(RH)*E–3(RH)*E

ns

–3

0

ns

tsu(EMBAV-EMOEL)(RS)*E–3(RS)*E+2nsth(EMOEH-EMBAIV)(RH)*E–3(RH)*Enstsu(EMAV-EMOEL)(RS)*E–3(RS)*E+2nsth(EMOEH-EMAIV)(RH)*E–3(RH)*E

ns

Reads
3

EMIF read cycle time (EW = 0)tc(EMRCYCLE)

EMIF read cycle time (EW = 1)
4

5

6
7

����������������
Output setup time, EMxCS[y:2] low to����������
EMxOE low (SS = 0)����������������
Output setup time, EMxCS[y:2] low to����������
EMxOE low (SS = 1)����������������
Output hold time, EMxCS[y:2] low to����������
EMxOE low (SS = 0)����������������
Output hold time, EMxCS[y:2] low to����������
EMxOE low (SS = 1)
Output setup time, EMxBA[y:0]valid to ����������
EMxOE low
Output hold time, ����������
EMxOE high totsu(EMCEL-EMOEL)

th(EMOEH-EMCEH)

EMxBA[y:0] invalid

89Output setup time, EMxA[y:0] valid
to ����������
EMxOE low
Output hold time, ����������
EMxOE high to
EMxA[y:0] invalid

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
16236
REV

A

DWG NO.
V62/18601
PAGE 14TABLE I. Electrical performance characteristics - Continued. 1/
No

Test

SymbolTest
conditions

Lim its

2/

Min

System - External Memory Interface (EMIF)
EMIF Electrical Data and Timing - Asynchronous RAM See FIGURE 15 through FIGURE 18
EMIF Asynchronous Memory Switching Characteristics - Continued 24/ 26/ 27/
10 ����������
tw(EMOEL)(RST)*E–1
EMxOE active low width (EW = 0)����������
(RST+(EWC*16))*E–1
EMxOE active low width (EW = 1)
11
29
30
15

16

17

18
19
20
21
22
23
24

25
26
27

Delay time from EMxWAIT
deasserted to ����������
EMxOE highOutput setup time, EMxDQM[y:0]valid to ����������
EMxOE low
Output hold time, ����������
EMxOE high to
EMxDQM[y:0] invalid

Max

ns
ns

4E+10

(RST)*E+1(RST+(EWC*16))*E+
15E+15(RS)*E–3(RS)*E+2

ns(RH)*E–3(RH)*Ens(WS+WST+WH+2)*E–3(WS+WST+WH+2)*E+1(WS+WST+WH+2+(EWC*16))*E+1(WS)*E+1

ns

-3

1

ns

(WH)*E–3(WH)*E

ns

-3

0

ns

(WS)*E–3(WS)*E+1

ns(WH)*E–3(WH)*Enstsu(EMBAV-EMWEL)(WS)*E–3(WS)*E+1nsth(EMWEH-EMBAIV)(WH)*E–3(WH)*Enstsu(EMAV-EMWEL)(WS)*E–3(WS)*E+1nsth(EMWEH-EMAIV)(WH)*E–3(WH)*E

ns

tw(EMWEL)(WST)*E–1(WST+(EWC*16))*E–1

nsnstd(EMWAITH-

4E+10(WST)*E+1(WST+(EWC*16))*E+
15E+15

tsu(EMDV-EMWEL)(WS)*E–3(WS)*E+1nsth(EMWEH-EMDIV)(WH)*E–3(WH)*Ens

SIZE
A

CAGE CODE
16236

td(EMWAITH-

tsu(EMDQMVEMOEL)

th(EMOEHEMDQMIV)EMIF write cycle time (EW = 1)

tc(EMWCYCLE)

Output setup time, EMxCS[y:2]
low to ����������
EMxWE low (SS = 0)
Output setup time, EMxCS[y:2]
low to ����������
EMxWE low (SS = 1)
Output hold time, ����������
EMxWEhigh to����������������
EMxCS[y: 2] high (SS = 0)
Output hold time, ����������
EMxWE high to����������������
EMxCS[y: 2] high (SS = 1)
Output setup time, EMxDQM[y:0]valid to ����������
EMxWE low
Output hold time, ����������
EMxWE high to
EMxDQM[y:0] invalid
Output setup time, EMxBA[y:0]valid to ����������
EMxWE low
Output hold time, ����������
EMxWE high to
EMxBA[y:0] invalid
Output setup time, EMxA[y:0]valid to ����������
EMxWE low
Output hold time, ����������
EMxWE high to
EMxA[y:0] invalid����������
EMxWE active low width (EW = 0)����������
EMxWE active low width (EW = 1)

tsu(EMCEL-EMWEL)

Writes(WS+WST+WH+2+(EWC*16))*E–3(WS)*E–3th(EMWEH-EMCEH)

tsu(EMDQMV-

ns
ns

EMWEL)th(EMWEHEMDQMIV)ns

EMWEH)

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIOns

EMOEH)

EMIF write cycle time (EW = 0)

Delay time from EMxWAIT
deasserted to ����������
EMxWE highOutput setup time, EMxD[y:0]valid to ����������
EMxWE low
Output hold time, ����������
EMxWE high to
EMxD[y:0] invalid

Units

REV

A

DWG NO.
V62/18601
PAGE 15TABLE I. Electrical performance characteristics - Continued. 1/
No

Test

SymbolTest conditions

Lim its

2/

Min

Units

Max

System - External Memory Interface (EMIF)
EMIF Electrical Data and Timing Synchronous RAM See FIGURE 19 and FIGURE 20
EMIF Synchronous Memory Timing Requirements
19

Input setup time, read data valid on EMxD[y:0] before EMxCLK
risingtsu(EMIFDV-EM_CLKH)

2

ns

20

Input hold time, read data valid on EMxD[y:0] after EMxCLK
risingth(CLKH-DIV)

1.5

ns

tc(CLK)10nstw(CLK)

3

EMIF Synchronous Memory Switching Characteristics
1

Cycle time, EMIF clock EMxCLK

2

Pulse width, EMIF clock EMxCLK high or low����������������
Delay time, EMxCLK rising to EMxCS[y:2] valid

3456td(CLKH-CSV)

Output hold time, EMxCLK rising to ����������������
EMxCS[y: 2] invalidtoh(CLKH-CSIV)

Delay time, EMxCLK rising to EMxDQM[y:0] validtd(CLKH-DQMV)

Output hold time, EMxCLK rising to EMxDQM[y:0] invalidtoh(CLKH-DQMIV)

7

Delay time, EMxCLK rising to EMxA[y:0] and EMxBA[y:0] validtd(CLKH-AV)

8

Output hold time, EMxCLK rising to EMxA[y:0] and EMxBA[y:0]invalidtoh(CLKH-AIV)

9

Delay time, EMxCLK rising to EMxD[y:0] validtd(CLKH-DV)

10

Output hold time, EMxCLK rising to EMxD[y:0] invalidtoh(CLKH-DIV)

11

Delay time, EMxCLK rising to EMxRAS validtd(CLKH-RASV)

12

Output hold time, EMxCLK rising to EMxRAS invalidtoh(CLKH-RASIV)

13

Delay time, EMxCLK rising to EMxCAS validtd(CLKH-CASV)

14

Output hold time, EMxCLK rising to EMxCAS invalid
Delay time, EMxCLK rising to ����������
EMxWE validtoh(CLKH-CASIV)

Delay time, EMxCLK rising to EMxD[y:0] tri-statedtd(CLKH-DHZ)

Output hold time, EMxCLK rising to EMxD[y:0] driving

toh(CLKH-DLZ)

15
16
17
18

1
8

1
8

DLA LAND AND MARITIMECOLUMBUS, OHIOCAGE CODE
16236
REV

A

ns
ns

1

ns
ns

8
1

ns
ns

8
1

ns
ns

8
1

ns
ns

8
1

See footnote at end of table.

SIZE
A

ns
ns

8

toh(CLKH-WEIV)

ns
ns

1

td(CLKH-WEV)

Output hold time, EMxCLK rising to ����������
EMxWE invalidns
8

DWG NO.
V62/18601
PAGE 16

ns
ns

TABLE I. Electrical performance characteristics - Continued. 1/
Test

Test conditions 2/

LimitsMin
Analog Peripherals - Analog-to-Digital Converter (ADC)ADC Operating Conditions (16-Bit Differential Mode) 31/

Typ

ADCCLK (derived from PERx.SYSCLK)

5

Sample window duration (set by ACQPS
and PERx.SYSCLK) 28/

320

VREFHI

2.4

2.5 or 3.0

VREFLOVSSA

0

VREFHI – VREFLO

2.4

ADC input conversion range

VREFLOADC input signal common mode voltage
29/ 30/VREFCM– 50

ADC Characteristics (16-Bit Differential Mode)

Unit
Max

50

MHz
ns

VREFCM

VDDA

V

VSSA

V

VDDA

V

VREFHIV

VREFCM +
50

mV

31

ADCCLKs

500

µs

31/

ADC conversion cycles 32/

29.6

Power-up time (after setting
ADCPWDNZ to first conversion)
Gain error

-64

±9

LSBs

Offset error 33/

-16

±9

LSBs

±6

LSBs

Channel-to-channel gain error
Channel-to-channel offset error

±3

LSBs

ADC-to-ADC gain error

Identical VREFHI and VREFLO for all ADCs

±6

LSBs

ADC-to-ADC offset error

Identical VREFHI and VREFLO for all ADCs

±3

LSBs

DNL 34/

> -1

±0.5

1

LSBs

INL

-3

±1.5

3

LSBs

SNR 35/36/

VREFHI = 2.5 V, fin = 10 kHz

87.6

dB

THD 35/36/

VREFHI = 2.5 V, fin = 10 kHz

-93.5

dB

SFDR 35/

36/

VREFHI = 2.5 V, fin = 10 kHz

95.4

dB

SINAD 35/

36/

VREFHI = 2.5 V, fin = 10 kHz

86.6

dB
bits

36/

VREFHI = 2.5 V, fin = 10 kHz,
single ADC
37/

14.1

ENOB 35/

VREFHI = 2.5 V, fin = 10 kHz, bits
synchronous ADCs 37/

14.1

bits

VREFHI = 2.5 V, fin = 10 kHz,asynchronous ADCs 39/

Not
supported

bits

PSRR

VDDA = 3.3-V DC + 200 mV
DC up to Sine at 1 kHz

77

dB

PSRR

VDDA = 3.3-V DC + 200 mV
Sine at 800 kHz

74

dB

CMRR

DC to 1 MHz

VREFHI input current
ADC-to-ADC isolation( 36/40/ 41/

VREFHI = 2.5 V, synchronous ADCs

60

dB

190

µA

-2

VREFHI = 2.5 V, asynchronous ADCs

2
Not
supported

LSBs
LSB

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
16236
REV

A

DWG NO.
V62/18601
PAGE 17

TABLE I. Electrical performance characteristics - Continued. 1/
Test

Test conditions 2/

Limits

Unit

Min
Typ
Analog Peripherals - Analog-to-Digital Converter (ADC) – Continued.
ADC Operating Conditions (12-Bit Single-Ended Mode)Analog Pe
ADCCLK (derived from PERx.SYSCLK)
5
Sample window duration (set by ACQPS
75
and PERx.SYSCLK) 28/
VREFHI
2.4
2.5 or 3.0
VREFLOVSSA
0
VREFHI – VREFLO
2.4
ADC input conversion range
VREFLOADC Characteristics (12-Bit Single-Ended Mode)
ADC conversion cycles 32/
10.1
Power-up time
Gain error
Offset error
Channel-to-channel gain error
Channel-to-channel offset error
ADC-to-ADC gain error
ADC-to-ADC offset error
DNL 34/INL
SNR 35/ 36/
THD 35/ 36/
SFDR 35/ 36/
SINAD 35/ 36/

ENOB

35/

36/

PSRR
PSRR

-5
-4

Identical VREFHI and VREFLO for all ADCs
Identical VREFHI and VREFLO for all ADCs
> -1
-2
VREFHI = 2.5 V, fin = 100 kHz
VREFHI = 2.5 V, fin = 100 kHz
VREFHI = 2.5 V, fin = 100 kHz
VREFHI = 2.5 V, fin = 100 kHz
VREFHI = 2.5 V, fin = 100 kHz,
single ADC 37/, all packages
VREFHI = 2.5 V, fin = 100 kHz,synchronous ADCs 38/, all packages
VREFHI = 2.5 V, fin = 100 kHz,asynchronous ADCs 39/,
100-pin PZP package
VREFHI = 2.5 V, fin = 100 kHz,asynchronous ADCs 39/,
176-pin PTP package
VREFHI = 2.5 V, fin = 100 kHz,asynchronous ADCs 39/,337-ball ZWT package
VDDA = 3.3-V DC + 200 mV
DC up to Sine at 1 kHz
VDDA = 3.3-V DC + 200 mV
Sine at 800 kHz

±3
±2
±4
±2
±4
±2
±0.5
±1.0
68.8
-78.4
79.2
68.4
11.1

Max

50

MHz
ns

VDDA
VSSA
VDDA
VREFHI

V
V
V
V

11
500
5
4

ADCCLKs
µs
LSBs
LSBs
LSB
LSBs
LSBs
LSBs
LSBs
LSB
dB
dB
dB
dB
bits

1
2

11.1

bits

Not
supported

bits

9.7

bits

10.9

bits

60

dB

57

dB

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
16236
REV

A

DWG NO.
V62/18601
PAGE 18

TABLE I. Electrical performance characteristics - Continued. 1/
Test

Test conditions 2/

Limits

Unit

Min
Typ
Analog Peripherals - Analog-to-Digital Converter (ADC) – Continued.
ADC Characteristics (12-Bit Single-Ended Mode) - Continued.
VREFHI = 2.5 V, synchronous ADCs
all packages
ADC-to-ADC isolation
36/ 40/ 41/

38/,

-1

VREFHI = 2.5 V, asynchronous ADCs 39/,
100-pin PZP package

1
Not
supported

LSBs
LSBs

VREFHI = 2.5 V, asynchronous ADCs 39/,
176-pin PTP package

-9

9

LSBs

VREFHI = 2.5 V, asynchronous ADCs 39/,337-ball ZWT package

-2

2

LSBs

VREFHI input current

Test

Max

SymbolTest conditions
2/

Min

130

µA

Limits

Unit

Typ

Max

Analog Peripherals - Analog-to-Digital Converter (ADC) – Continued.
ADCEXTSOC Timing Requirements 42/
Pulse duration, INT input low/hightw(INT)

Single-Ended Input Model Parameters

Synchronous

2tc(SYSCLK)

cyclesWith qualifiertw(IQSW) + tw(SP)+ 1tc(SYSCLK)

cyclesSee FIGURE 21
VALUE (12-BIT MODE)

Parasitic input capacitance

Cp

Sampling switch resistance

Ron

425

Ω

Sampling capacitor

Ch

14.5

pF

Nominal source impedance

Rs

50

Ω

Differential Input Model Parameters

43/

See FIGURE 22
VALUE (16-BIT MODE)

Parasitic input capacitance

Cp

43/

Sampling switch resistance

Ron

700

Ω

Sampling capacitor

Ch

16.5

pF

Nominal source impedance

Rs

50

Ω

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
16236
REV

A

DWG NO.
V62/18601
PAGE 19

TABLE I. Electrical performance characteristics - Continued. 1/
ADCCLK PRESCALESYSCLK CYCLES

ADCCTL2[PRESCALE]

RATIO
tEOC
tLAT
tINT(EARLY)tINT(LATE)ADCCLK:SYSCLK
Analog Peripherals - Analog-to-Digital Converter (ADC) – Continued.
ADC Timing Diagrams - ADC Timings in 12-Bit Mode (SYSCLK Cycles) See FIGURE 23
0

1

11

13

1

1.5

2

2

21

23

3

2.5

26

4

3

31

5

3.5

6

4

7
8

1

ADCCLKCYCLES
tEOC

11

11.0

1

21

10.5

28

1

26

10.4

34

1

31

10.3

36

39

1

36

10.3

41

44

1

41

10.3

4.5

46

49

1

46

10.2

5

51

55

1

51

10.2

invalid

9

5.5

56

60

1

56

10.2

10

6

61

65

1

61

10.2

11

6.5

66

70

1

66

10.2

12

7

71

76

1

71

10.1

13

7.5

76

81

1

76

10.1

14

8

81

86

1

81

10.1

15

8.5

86

91

1

86

10.1

31

31.0

ADC Timing Diagrams - ADC Timings in 16-Bit Mode (SYSCLK Cycles)
0

1

1

1.5

2

See FIGURE 24

31

32

1

2

60

61

1

60

30.0

3

2.5

75

75

1

75

30.0

4

3

90

91

1

90

30.0

5

3.5

104

106

1

104

29.7

6

4

119

120

1

119

29.8

7

4.5

134

134

1

134

29.8

8

5

149

150

1

149

29.8

9

5.5

163

165

1

163

29.6

10

6

178

179

1

178

29.7

11

6.5

193

193

1

193

29.7

12

7

208

208

1

208

29.7

13

7.5

222

222

1

222

29.6

14

8

237

237

1

237

29.6

15

8.5

252

252

1

252

29.6

invalid

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
16236
REV

A

DWG NO.
V62/18601
PAGE 20

TABLE I. Electrical performance characteristics - Continued. 1/
Test

Test conditions

Limits2/
Min
TypAnalog Peripherals - Analog-to-Digital Converter (ADC) – Continued.
Temperature Sensor Electrical Characteristics

Unit
Max

Temperature accuracy

±15

°C

Start-up time (TSNSCTL[ENABLE] tosampling temperature sensor)

500

µs

ADC acquisition time

700

ns

Analog Peripherals - Comparator Subsystem (CMPSS)CMPSS Electrical Data and Timing - Comparator Electrical Characteristics See FIGURE 25 and FIGURE 26
Power-up time (fromCOMPCTL[COMPDACE] to comparator
ready)

10µs

Comparator input (CMPINxx) range

0

VDDA

V

Input referred offset error

-20

20

mV

1x

12

2x

34

CMPSS

3x

36

DAC LSB

4x48

Response time (delay from CMPINx input

Step response21change to output on ePWM X-BAR or

Ramp response (1.65 V/μs)

26ns

Output X-BAR)

Ramp response (8.25 mV/μs)

30

ns

Hysteresis

44/

60

ns

CMPSS DAC Static Electrical Characteristics See FIGURE 27, FIGURE 28 and FIGURE 29
CMPSS DAC output range
Static offset error
Static gain error

Internal reference

0

VDDA

External reference

0

VDAC

-25

25

mV

45/
45/

V

-2

2

% of FSR

Static DNL

Endpoint corrected

> -1

4

LSB

Static INL

Endpoint corrected

-16

16

LSB

Settling time

Settling to 1 LSB after full-scale
output change1µsResolution

12

CMPSS DAC output disturbance45/

CMPSS DAC disturbance time

45/

Error induced by comparator tripor CMPSS DAC code change
within the same CMPSS module

100
200

VDAC reference voltage
VDAC load

-100

bits

2.4

47/

2.5 or 3.0
6

LSB
ns

VDDA

V
Ω

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
16236
REV

A

DWG NO.
V62/18601
PAGE 21

TABLE I. Electrical performance characteristics - Continued. 1/
Test

Test conditions

Limits

Unit

48/
Min
Typ
Max
Analog Peripherals - Buffered Digital-to-Analog Converter (DAC)
Buffered DAC Electrical Data and Timing - Buffered DAC Electrical Characteristics See FIGURE 30, 31 and 32
Power-up time (DACOUTEN to
DAC output valid)
Trimmed offset error

10
Midpoint

Gain error

µs

-10

10

mV

-2.5

2.5

% of FSR

DNL

Endpoint corrected

> -1

1

LSB

INL

Endpoint corrected

-5

5

LSB

DACOUTx settling time

Settling to 2 LSBs after 0.3V-to-3V
transition

2

Resolutionµs

12

Voltage output range(

0.3

bits
VDDA – 0.3
100V

Capacitive load

Output drive capability

Resistive load

Output drive capability

5

Reference voltage

VDAC or VREFHI

2.4

Reference load(

VDAC or VREFHI

170

Output noise

Integrated noise from 100 Hz to 100 kHz

500

µVms

Noise density at 10 kHz

711

nVrms/√Hz

RPD

50
2.5 or 3.0

Glitch energy
PSRR

pF
kΩ
kΩ

VDDA

V
kΩ

1.5

V-ns

DC up to 1 kHz

70

dB

100 kHz

30

dB

SNR

1020 Hz

67

dB

THD

1020 Hz

-63

dB

SFDR

1020 Hz, including harmonics and spurs

66

dBc

1020 Hz, including only spurs

104

dBc

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
16236
REV

A

DWG NO.
V62/18601
PAGE 22

TABLE I. Electrical performance characteristics. - Continued. 1/
Test

SymbolTest conditions

Limits2/

Min

Control Peripherals - Enhanced Capture (eCAP)
eCAP Electrical Data and Timing - eCAP Timing Requirement 42/
Capture input pulse widthtw(CAP)
Asynchronous
Synchronous
With input qualifier2tc(SYSCLK)
2tc(SYSCLK)
1tc(SYSCLK) +tw(IQSW)

Unit
Max

cyclescyclescycleseCAP Electrical Data and Timing - eCAP Switching Characteristics
Pulse duration, APWMx output high/lowtw(APWM)
20
Control Peripherals - Enhanced Pulse Width Modulator (ePWM)
ePWM Electrical Data and Timing - ePWM Timing Requirements
42/
Asynchronous
2tc(EPWMCLK)
Sync input pulse widthtw(SYNCIN)
Synchronous
2tc(EPWMCLK)With input qualifier
1tc(EPWMCLK) +tw(IQSW)
ePWM Electrical Data and Timing - ePWM Switching Characteristics
Pulse duration, PWMx output high/lowtw(PWM)
20
Sync output pulse widthtw(SYNCOUT)
8tc(SYSCLK)
Delay time, trip input active to PWM forced high25
Delay time, trip input active to PWM forced lowtd(TZ-PWM)
Delay time, trip input active to PWM Hi-Z
Trip-Zone Input Timing Requirements
42/ See FIGURE 33
Asynchronous
1tc(EPWMCLK)����� input low
tw(TZ)
Synchronous
2tc(EPWMCLK)
Pulse duration, TZx
With input qualifier
1tc(EPWMCLK) +tw(IQSW)
External ADC Start-of-Conversion Electrical Data and Timing - Switching Characteristics See FIGURE 34
tw(ADCSOCL)
32tc(SYSCLK)
Pulse duration, ��������������
ADCSOCxO lownscyclescyclescyclesns
cyclesns

cyclescyclescyclescyclesSee footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
16236
REV

A

DWG NO.
V62/18601
PAGE 23

TABLE I. Electrical performance characteristics. - Continued. 1/
Test

SymbolTest conditions

Limits

2/

Min

Unit
Max

Control Peripherals - Enhanced Quadrature Encoder Pulse (eQEP)
eQEP Electrical Data and Timing - Timing Requirements 42/
Asynchronous 55/ /Synchronous

2tc(SYSCLK)

cycles2[1tc(SYSCLK) +tw(IQSW)]

cyclesAsynchronous 55/ /Synchronous

2tc(SYSCLK)

cyclesWith input qualifier2tc(SYSCLK) +tw(IQSW)

cyclesAsynchronous 55/ /Synchronous

2tc(SYSCLK)

cyclesWith input qualifier2tc(SYSCLK) +tw(IQSW)

cyclesAsynchronous 55/ /Synchronous

2tc(SYSCLK)

cyclesWith input qualifier2tc(SYSCLK) +tw(IQSW)

cyclesAsynchronous 55/ /Synchronous

2tc(SYSCLK)

cyclesWith input qualifier2tc(SYSCLK) +tw(IQSW)

cyclesQEP input periodtw(QEPP)With input qualifier

QEP Index Input High timetw(INDEXH)QEP Index Input Low time

QEP Strobe High time

QEP Strobe Input Low timetw(INDEXL)

tw(STROBH)

tw(STROBL)

eQEP Electrical Data and Timing - Switching Characteristics
Delay time, external clock to counterincrement
Delay time, QEP input edge to position
compare sync output

td(CNTR)xin

4tc(SYSCLK)

cyclestd(PCS-

6tc(SYSCLK)

cyclesOUT)QEP

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
16236
REV

A

DWG NO.
V62/18601
PAGE 24TABLE I. Electrical performance characteristics. - Continued. 1/
Test

SymbolTest conditions

Limits

2/

Unit

Min

Max

Control Peripherals - High-Resolution Pulse Width Modulator (HRPWM)
HRPWM Electrical Data and Timing - Characteristics
Micro Edge Positioning (MEP) step size

150

56/

TYP

ps
310

ps

Control Peripherals - Sigma-Delta Filter Module (SDFM)
SDFM Electrical Data and Timing - SDFM Timing Requirements See FIGURE 35 through FIGURE 38
Mode

1

Cycle time, SDx_Cy

tc(SDC)M040

256 * SYSCLK
periodns

Pulse duration, SDx_Cy hightw(SDCH)M0

10

tc(SDC)M0 – 10

ns

Setup time, SDx_Dy valid before SDx_Cy goeshightsu(SDDV-

5

ns

Hold time, SDx_Dy wait after SDx_Cy goes highth(SDCH-5ns

SDCH)M0SDD)M0Mode

2Cycle time, SDx_Cy

tc(SDC)M1

80

256 * SYSCLK
periodns

Pulse duration, SDx_Cy hightw(SDCH)M1

10tc(SDC)M1 – 10

ns

Setup time, SDx_Dy valid before SDx_Cy goeslowtsu(SDDV-

5

ns

Setup time, SDx_Dy valid before SDx_Cy goeshightsu(SDDV-

5

ns

Hold time, SDx_Dy wait after SDx_Cy goes lowth(SDCL-SDD)M1

5

ns

Hold time, SDx_Dy wait after SDx_Cy goes highth(SDCH-5ns

SDCL)M1

SDCH)M1

SDD)M1Mode

3tc(SDD)M2

8*tc(SYSCLK)

tw(SDDH)M2

10

Cycle time, SDx_Cy

tc(SDC)M3

40

256 * SYSCLK
periodns

Pulse duration, SDx_Cy hightw(SDCH)M3

10

tc(SDC)M3 – 5

ns

Setup time, SDx_Dy valid before SDx_Cy goeshightsu(SDDV-

5

ns

Hold time, SDx_Dy wait after SDx_Cy goes highth(SDCH-

5

ns

Cycle time, SDx_Dy
Pulse duration, SDx_Dy highMode

20 * tc(SYSCLK)ns4SDCH)M3

SDD)M3

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

ns

SIZE
A

CAGE CODE
16236
REV

A

DWG NO.
V62/18601
PAGE 25TABLE I. Electrical performance characteristics. - Continued. 1/
Test

SymbolTest conditions

Limits

2/

Min

Unit
Max

Communications Peripherals - Inter-Integrated Circuit (I2C)
I2C Electrical Data and Timing - I2C Timing Requirements nt
Hold time, START condition, SCL falldela after SDA fallth(SDASCL)START

0.6

μs

Setup time, Repeated START, SCL rise
before SDA fall delaytsu(SCLSDA)START

0.6

μs

Hold time, data after SCL fallth(SCL-DAT)0μs

Setup time, data before SCL risetsu(DAT-SCL)

100

ns

Rise time, SDA

tr(SDA)

Input tolerance

20

300

ns

Rise time, SCL

tr(SCL)

Input tolerance

20

300

ns

Fall time, SDA

tf(SDA)

Input tolerance

11.4

300

ns

Fall time, SCL

tf(SCL)

Input tolerance

11.4

300

ns

Setup time, STOP condition, SCL rise
before SDA rise delaytsu(SCLSDA)STOP

0.6

μs

I2C Electrical Data and Timing - I2C Switching Characteristics
SCL clock frequency

fSCL

0

400

Pulse duration, SCL clock lowtw(SCLL)

1.3

μs

Pulse duration, SCL clock hightw(SCLH)

0.6

μs

Pulse duration of spikes that will be
suppressed by the input filtertw(SP)

0

Bus free time between STOP and
START conditions

tBUF

1.3

50

kHz

ns
μs

Valid time, data after SCL falltv(SCL-DAT)

0.9

μs

Valid time, Acknowledge after SCL falltv(SCL-ACK)

0.9

μs

Valid low-level input voltage

VIL

-0.3

0.3 *
VDDIO

V

Valid high-level input voltage

VIH

0.7 * VDDIOVDDIO +
0.3

V

Low-level output voltage

VOL

Sinking 3 mA

0

0.4

V

0.1 Vbus < Vi < 0.9 Vbus

-10

10

μA

Input current on pinsII

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
16236
REV

A

DWG NO.
V62/18601
PAGE 26

TABLE I. Electrical performance characteristics. - Continued. 1/
Test

SymbolTest conditions
2/

Limits
Min

Unit
Max

Communications Peripherals - Multichannel Buffered Serial Port (McBSP)
McBSP Electrical Data and Timing - McBSP Timing Requirements See FIGURE 39 and FIGURE 40 57/ 58/
McBSP module clock (CLKG, CLKX,

1

CLKR) range
McBSP module cycle time (CLKG, CLKX,

MHz
25

MHz

1

ms

40

CLKR) range

ns

M11

Cycle time, CLKR/X

tc(CKRX)

CLKR/X ext

2P

ns

M12

Pulse duration, CLKR/X high or CLKR/X
low

tw(CKRX)

CLKR/X ext

P-7

ns

M13

Rise time, CLKR/X

tr(CKRX)

CLKR/X ext

M14

Fall time, CLKR/X

tf(CKRX)

CLKR/X ext

M15

Setup time, external FSR high before

tsu(FRH-CKRL)CLKR int

18

ns

CLKR ext

2

ns

CLKR int0ns

CLKR ext

6ns

CLKR int

18

ns

CLKR ext

5ns

CLKR int0ns

CLKR ext

3

ns

CLKR int

18

ns

CLKR ext

2

ns

CLKR int0ns

CLKR ext

6ns

CLKR low
M16

Hold time, external FSR high after CLKR

th(CKRL-FRH)

low
M17
M18
M19

Setup time, DR valid before CLKR low
Hold time, DR valid after CLKR low
Setup time, external FSX high before

tsu(DRV-CKRL)th(CKRL-DRV)
tsu(FXH-CKXL)CLKX low
M20

Hold time, external FSX high after CLKXth(CKXL-FXH)

low

7

ns

7

ns

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
16236
REV

A

DWG NO.
V62/18601
PAGE 27

TABLE I. Electrical performance characteristics. - Continued. 1/
Test

SymbolTest conditions

Limits

2/

Unit

Min

Max

Communications Peripherals - Multichannel Buffered Serial Port (McBSP)
McBSP Electrical Data and Timing - McBSP Switching Characteristics See FIGURE 39 and FIGURE 40

57/ 59/M1

Cycle time, CLKR/X

tc(CKRX)

CLKR/X int

2P

M2

Pulse duration, CLKR/X hightw(CKRXH)

CLKR/X int

D – 5 60/

D+5
60/

ns

M3

Pulse duration, CLKR/X low

tw(CKRXL)

CLKR/X int

C – 5 60/

C+5
60/

ns

M4

Delay time, CLKR high to internaltd(CKRH-FRV)

CLKR int

04

ns

CLKR ext

3

27

ns

CLKR int

04

ns

CLKR ext

3

FSR valid
M5

Delay time, CLKX high to internaltd(CKXH-FXV)FSX valid
M6

27

ns

Disable time, CLKX high to DX hightdis(CKXH-

CLKR int

8

ns

impedance following last data bit

DXHZ)

CLKR ext

14ns

CLKR int

9ns

CLKR ext

28

ns

CLKR int

8

CLKR ext

14ns

CLKR int

P+8

ns

CLKR ext

P + 14ns

Delay time, CLKX high to DX valid.
M7This applies to all bits except thefirst bit transmitted.

td(CKXH-DXV)

Delay time, CLKX high to DX valid

DXENA = 0

Only applies to first bit transmitted
when in Data Delay 1 or 2
(XDATDLY=01b

DXENA = 1

or 10b) modes
Enable time, CLKX high to DX driven
Only applies to first bit transmitted
M8

DXENA = 0ten(CKXH-DX)

when in Data Delay 1 or 2

DXENA = 1

(XDATDLY=01b or 10b) modes
Delay time, FSX high to DX valid
Only applies to first bit transmitted
M9

DXENA = 0td(FXH-DXV)

when in Data Delay 0

DXENA = 1

(XDATDLY=00b) mode.
Only applies to first bit transmitted

CLKR int0ns

CLKR ext

6ns

CLKR int

P

ns

CLKR ext

P+6

FSX int

DXENA = 0ten(FXH-DX)

when in Data Delay 0

DXENA = 1

(XDATDLY=00b) mode

ns
8

ns

FSX ext

14ns

FSX int

P+8ns

P + 14ns

FSX ext

Enable time, FSX high to DX driven
M10ns

FSX int

0ns

FSX ext

6ns

FSX int

Pns

FSX ext

P+6

ns

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
16236
REV

A

DWG NO.
V62/18601
PAGE 28

TABLE I. Electrical performance characteristics. - Continued. 1/
No

Test

SymbolMASTER

SLAVE

2/
Min
Max
Min
Communications Peripherals - Multichannel Buffered Serial Port (McBSP)
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)
See FIGURE 41

Unit
Max
61/

M30

Setup time, DR valid before CLKX lowtsu(DRV-CKXL)

30

8P – 10ns

M31

Hold time, DR valid after CLKX lowth(CKXL-DRV)

1

8P – 10ns

M32

Setup time, FSX low before CLKX hightsu(BFXL-CKXH)

8P + 10ns

M33

Cycle time, CLKX

16P

ns

tc(CKX)

2P

59/

McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)
M24

Hold time, FSX low after CLKX lowth(CKXL-FXL)

2P

M25

Delay time, FSX low to CLKX hightd(FXL-CKXH)P

M28Disable time, DX high impedance
following last data bit from FSX hightdis(FXH-DXHZ)

6

M29

Delay time, FSX low to DX validtd(FXL-DXV)6

See FIGURE 41

59/

ns
ns
6P + 6ns

4P + 6

McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)ns

See FIGURE 42

61/

M39

Setup time, DR valid before CLKX hightsu(DRV-CKXH)

30

8P – 10

ns

M40

Hold time, DR valid after CLKX HIGHth(CKXH-DRV)

1

8P – 10ns

M41

Setup time, FSX low before CLKX hightsu(BFXL-CKXH)

16P + 10ns

M42

Cycle time, CLKX

16P

ns

tc(CKX)

2P

59/

McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)th(CKXL-FXL)

See FIGURE 42

M34

Hold time, FSX low after CLKX low

P

ns

M35

Delay time, FSX low to CLKX hightd(FXL-CKXH)

2P

M37

Disable time, DX high impedance
following last data bit from FSX lowtdis(CKXL-DXHZ)

P+6

7P + 6

ns

M38

Delay time, FSX low to DX validtd(FXL-DXV)

6

4P + 6

ns

59/

ns

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
16236
REV

A

DWG NO.
V62/18601
PAGE 29TABLE I. Electrical performance characteristics. - Continued. 1/
No

Test

SymbolMASTER

SLAVE

Unit

2/
Min
Max
Min
Communications Peripherals - Multichannel Buffered Serial Port (McBSP)
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)
See FIGURE 43

Max
61/

M49

Setup time, DR valid before CLKX hightsu(DRV-CKXH)

30

8P – 10

ns

M50

Hold time, DR valid after CLKX highth(CKXH-DRV)

1

8P – 10ns

M51

Setup time, FSX low before CLKX lowtsu(BFXL-CKXL)

8P + 10ns

M52

Cycle time, CLKX

16P

ns

tc(CKX)

2P

59/

McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)
M34

Hold time, FSX low after CLKX highth(CKXL-FXL)

2P

M44

Delay time, FSX low to CLKX lowtd(FXL-CKXL)P

M47Disable time, DX high impedance
following last data bit from FSX hightdis(FXH-DXHZ)

6

M48

Delay time, FSX low to DX validtd(FXL-DXV)6

See FIGURE 43

59/

ns
ns
6P + 6ns

4P + 6

McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)

ns

See FIGURE 44

61

M58

Setup time, DR valid before CLKX lowtsu(DRV-CKXL)

30

8P – 10

ns

M59

Hold time, DR valid after CLKX lowth(CKXL-DRV)

1

8P – 10ns

M60

Setup time, FSX low before CLKX lowtsu(BFXL-CKXL)

16P + 10ns

M61

Cycle time, CLKX

16P

ns

tc(CKX)

2P

59/

McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)th(CKXL-FXL)

See FIGURE 44

M53

Hold time, FSX low after CLKX highP

M54

Delay time, FSX low to CLKX lowtd(FXL-CKXH)

M55

Delay time, CLKX high to DX validtd(CLKXH-DXV)

-2

M56

Disable time, DX high impedance
following last data bit from CLKX hightdis(CKXL-DXHZ)

P+6

7P + 6

ns

M57

Delay time, FSX low to DX validtd(FXL-DXV)

6

4P + 6ns

SIZE
A

CAGE CODE
16236

2P

ns
59/

ns
0

3P + 6

5P + 20

See footnote at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIOREVADWG NO.
V62/18601
PAGE 30

ns

TABLE I. Electrical performance characteristics. - Continued. 1/
Test 2/

Symbol(BRR + 1)
Lim its
CONDITION
62/
Min
Max
Communications Peripherals - Serial Peripheral Interface (SPI) - Non-High-Speed Master Mode Timings
SPI Master Mode Switching Characteristics (Clock Phase = 0)
See FIGURE 45

Unit

1

Cycle time, SPICLK

tc(SPC)M

128tc(LSPCLK)

ns

2

Pulse duration, SPICLK,tw(SPC1)M

first pulse
3

Pulse duration, SPICLK,

Even

4tc(LSPCLK)

Odd

5tc(LSPCLK)

127tc(LSPCLK)

ns

Even

0.5tc(SPC)M – 3

0.5tc(SPC)M + 3

ns

Odd

0.5tc(SPC)M + 0.5tc(LSPCLK) – 3

0.5tc(SPC)M + 0.5tc(LSPCLK) + 3

nstw(SPC2)M

Even

0.5tc(SPC)M – 3

0.5tc(SPC)M + 3

ns

Odd

0.5tc(SPC)M –0.5tc(LSPCLK) – 3

0.5tc(SPC)M –0.5tc(LSPCLK) + 3

ns

3

ns

second pulse
4

Delay time, SPICLK to
SPISIMO validtd(SIMO)M

Even, Odd

5

Valid time, SPISIMO validtv(SIMO)M

Even

0.5tc(SPC)M – 3

ns

after SPICLK
Delay time, ���������SPISTE active

Odd

0.5tc(SPC)M –0.5tc(LSPCLK) – 3

ns23

td(SPC)M

Even

tc(SPC)M – 3

ns

Odd

0.5tc(SPC)M –0.5tc(LSPCLK) – 3

ns

Even

0.5tc(SPC)M – 3

ns

Odd

0.5tc(SPC)M –0.5tc(LSPCLK) – 3

ns

to SPICLK24

Delay time, SPICLK to���������SPISTE inactivetd(STE)M

SPI Master Mode Switching Characteristics (Clock Phase = 1)

See FIGURE 46

1

Even

4tc(LSPCLK)

128tc(LSPCLK)

ns

Odd

5tc(LSPCLK)

127tc(LSPCLK)

ns

Cycle time, SPICLK

2

Pulse duration, SPICLK,tc(SPC)Mtw(SPC1)M

first pulse
3

Pulse duration, SPICLK,tw(SPC2)M

second pulsetd(SIMO)M

Even

0.5tc(SPC)M – 3

0.5tc(SPC)M + 3

ns

Odd

0.5tc(SPC)M - 0.5tc(LSPCLK) – 3

0.5tc(SPC)M - 0.5tc(LSPCLK) + 3

ns

Even

0.5tc(SPC)M – 3

0.5tc(SPC)M + 3

ns

Odd

0.5tc(SPC)M +0.5tc(LSPCLK) – 3

0.5tc(SPC)M +0.5tc(LSPCLK) + 3

ns

Even

0.5tc(SPC)M – 3

ns4

Delay time, SPISIMO valid

Odd

0.5tc(SPC)M +0.5tc(LSPCLK) – 3

ns5

Valid time, SPISIMO validtv(SIMO)M

Even

0.5tc(SPC)M – 3

ns

after SPICLK
Delay time, ���������SPISTE active
to SPICLK

Odd

0.5tc(SPC)M –0.5tc(LSPCLK) – 3

ns23

td(SPC)M

Even, Oddtc(SPC)M – 3

nstd(STE)M

Even

0.5tc(SPC)M – 3

ns

Odd

0.5tc(SPC)M –0.5tc(LSPCLK) – 3

ns

to SPICLK24

Delay time, SPICLK to���������SPISTE inactive

SPI Master Mode Timing Requirements
8

Setup time, SPISOMI valid
before SPICLK

tsu(SOMI)M

Even, Odd

20

ns

9

Hold time, SPISOMI valid
after SPICLKth(SOMI)M

Even, Odd0ns

See footnote at end of table.

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PAGE 31TABLE I. Electrical performance characteristics. - Continued. 1/
Test 2/

SymbolLimits

Unit

Min
Max
Communications Peripherals - Serial Peripheral Interface (SPI) - Non-High-Speed Slave Mode Timings
SPI Slave Mode Switching Characteristics
See FIGURE 47 and FIGURE 48
15
Delay time, SPICLK to SPISOMI validtd(SOMI)S
20

ns

16

0

ns

Valid time, SPISOMI valid after SPICLKSPI Slave Mode Timing Requirementstv(SOMI)SSee FIGURE 47 and FIGURE 48

12

Cycle time, SPICLK

tc(SPC)S

4tc(SYSCLK)

ns

13

Pulse duration, SPICLK, first pulsetw(SPC1)S2tc(SYSCLK) – 1

ns14

Pulse duration, SPICLK, second pulsetw(SPC2)S2tc(SYSCLK) – 1

ns19

Setup time, SPISIMO valid before SPICLK

tsu(SIMO)S

1.5tc(SYSCLK)

ns

20

Hold time, SPISIMO valid after SPICLK
Setup time, ���������SPISTE active before SPICLKth(SIMO)S

1.5tc(SYSCLK)

nstsu(STE)S

1.5tc(SYSCLK)

nsth(STE)S

1.5tc(SYSCLK)

ns

25
26

Hold time, ���������SPISTE inactive after SPICLK

See footnote at end of table.

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PAGE 32TABLE I. Electrical performance characteristics. - Continued. 1/
Test 2/(BRR + 1)
Lim its
CONDITION
62/
Min
Max
Communications Peripherals - Serial Peripheral Interface (SPI) - High-Speed Master Mode Timings
SPI High-Speed Master Mode Switching Characteristics (Clock Phase = 0)
See FIGURE 49
1
Cycle time, SPICLK
tc(SPC)M
Even
4tc(LSPCLK)
128tc(LSPCLK)
2

Pulse duration, SPICLK,

Symboltw(SPC1)M

first pulse
3

Pulse duration, SPICLK,tw(SPC2)M

second pulse

5tc(LSPCLK)

127tc(LSPCLK)

ns

Even

0.5tc(SPC)M – 1

0.5tc(SPC)M + 1

ns

Odd

0.5tc(SPC)M + 0.5tc(LSPCLK) – 1

0.5tc(SPC)M + 0.5tc(LSPCLK) + 1

ns

Even

0.5tc(SPC)M – 1

0.5tc(SPC)M + 1

ns

Odd

0.5tc(SPC)M –0.5tc(LSPCLK) – 1

0.5tc(SPC)M –0.5tc(LSPCLK) + 1

ns

1

ns

Delay time, SPICLK to
SPISIMO validtd(SIMO)M

Even, Odd

5

Valid time, SPISIMO

tv(SIMO)M

Even

23

valid after SPICLK
Delay time, ���������SPISTE

Delay time, SPICLK to���������SPISTE inactive

0.5tc(SPC)M – 1

Odd

active to SPICLK
24

Even

2

tc(SPC)M

Pulse duration, SPICLK,tw(SPC1)M

first pulse
3

Pulse duration, SPICLK,tw(SPC2)M

second pulse
4

Delay time, SPISIMO

td(SIMO)M

valid to SPICLK

ns

0.5tc(SPC)M –0.5tc(LSPCLK) – 1

Even

ns

0.5tc(SPC)M – 1

Odd

Cycle time, SPICLK

ns

tc(SPC)M – 1

ns

0.5tc(SPC)M –0.5tc(LSPCLK) – 1

SPI High-Speed Master Mode Switching Characteristics (Clock Phase = 1)
1

ns

0.5tc(SPC)M –0.5tc(LSPCLK) – 1

Odd
td(STE)M

ns

Odd

4

td(SPC)M

Unit

Even

ns

See FIGURE 50

4tc(LSPCLK)

128tc(LSPCLK)

ns

Odd

5tc(LSPCLK)

127tc(LSPCLK)

ns

Even

0.5tc(SPC)M – 1

0.5tc(SPC)M + 1

ns

Odd

0.5tc(SPC)M - 0.5tc(LSPCLK) – 1

0.5tc(SPC)M - 0.5tc(LSPCLK) + 1

ns

Even

0.5tc(SPC)M – 1

0.5tc(SPC)M + 1

ns

Odd

0.5tc(SPC)M +0.5tc(LSPCLK) – 1

0.5tc(SPC)M +0.5tc(LSPCLK) + 1

ns

Even

0.5tc(SPC)M – 1

ns

Odd

0.5tc(SPC)M +0.5tc(LSPCLK) – 1

ns5

Valid time, SPISIMO

tv(SIMO)M

Even

0.5tc(SPC)M – 1

ns

23

valid after SPICLK
Delay time, ���������SPISTE
active to SPICLK

td(SPC)M

Even, Oddtc(SPC)M – 1

nstd(STE)M

Even

0.5tc(SPC)M – 1

ns24

Delay time, SPICLK to���������SPISTE inactive

Odd

0.5tc(SPC)M –0.5tc(LSPCLK) – 1

Odd

ns

0.5tc(SPC)M –0.5tc(LSPCLK) – 1

ns

SPI High-Speed Master Mode Timing Requirements
8
9

Setup time, SPISOMI
valid before SPICLK

tsu(SOMI)M

Even, Odd

1

ns

Hold time, SPISOMI valid
after SPICLKth(SOMI)M

Even, Odd

5ns

See footnote at end of table.

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PAGE 33

TABLE I. Electrical performance characteristics. - Continued. 1/
Test 2/

SymbolLimits

Unit

Min
Max
Communications Peripherals - Serial Peripheral Interface (SPI) - High-Speed Slave Mode Timings
SPI High-Speed Slave Mode Switching Characteristics
See FIGURE 51 and FIGURE 52
15

Delay time, SPICLK to SPISOMI validtd(SOMI)S

16

Valid time, SPISOMI valid after SPICLK

tv(SOMI)S9

SPI High-Speed Slave Mode Timing Requirements

See FIGURE 51 and FIGURE 52

ns

0

ns

12

Cycle time, SPICLK

tc(SPC)S

4tc(SYSCLK)

ns

13

Pulse duration, SPICLK, first pulsetw(SPC1)S2tc(SYSCLK) – 1

ns14

Pulse duration, SPICLK, second pulsetw(SPC2)S2tc(SYSCLK) – 1

ns19

Setup time, SPISIMO valid before SPICLK

tsu(SIMO)S

1.5tc(SYSCLK)

ns

20

Hold time, SPISIMO valid after SPICLK
Setup time, ���������SPISTE active before SPICLKth(SIMO)S

1.5tc(SYSCLK)

nstsu(STE)S

1.5tc(SYSCLK)

nsth(STE)S

1.5tc(SYSCLK)

ns

25
26

Hold time, ���������SPISTE inactive after SPICLK

See footnote at end of table.

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PAGE 34TABLE I. Electrical performance characteristics. - Continued. 1/
Test

SymbolTest conditions

Limits

2/

Min

Unit
Max

Communications Peripherals - Universal Serial Bus (USB) Controller - USB Electrical Data and Timing
USB Input Ports DP and DM Timing Requirements
Differential input common mode range

V(CM)

0.8

Input impedance

Z(IN)

300

Crossover voltage

VCRS

1.3

VIL

0.8

Static SE input logic-low level

2.5

V
kΩ

2.0

V
V

Static SE input logic-high level

VIH

2.0

V

Differential input voltage

VDI

0.2

V

2.8

3.6

V

USB Output Ports DP and DM Switching Characteristics
D+, D– single-ended

VOH

USB 2.0 load conditions

D+, D– single-endedVOL

USB 2.0 load conditions

D+, D– impedanceZ(DRV)

0

0.3

V

28

44

Ω

Rise timetr

Full speed, differential, CL = 50 pF,
10%/90%, Rpu on D+

4

20

ns

Fall time

tf

Full speed, differential, CL = 50 pF,
10%/90%, Rpu on D+

4

20

ns

See footnote at end of table.

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PAGE 35TABLE I. Electrical performance characteristics. - Continued. 1/
Test

SymbolTest conditions
2/

Limits
Min

Unit
Max

Communications Peripherals - Universal Parallel Port (uPP) Interface uPP Electrical Data and Timing - uPP Timing Requirements See FIGURE 53 through FIGURE 56
1
2
3

Cycle time, CLKtc(CLK)

Pulse width, CLK hightw(CLKH)

Pulse width, CLK lowtw(CLKL)SDR mode20

ns

DDR mode40ns

SDR mode8ns

DDR mode18

ns

SDR mode8ns

DDR mode

18

ns

4

Setup time, START valid before CLK hightsu(STV-CLKH)

4

ns

5

Hold time, START valid after CLK highth(CLKH-STV)

0.8

ns

6

Setup time, ENABLE valid before CLK hightsu(ENV-CLKH)

4

ns

7

Hold time, ENABLE valid after CLK highth(CLKH-ENV)

0.8

ns

8

Setup time, DATA valid before CLK hightsu(DV-CLKH)

4

ns

9

Hold time, DATA valid after CLK highth(CLKH-DV)

0.8

ns

10

Setup time, DATA valid before CLK lowtsu(DV-CLKL)

4

ns

11

Hold time, DATA valid after CLK lowth(CLKL-DV)

0.8

ns

19

Setup time, WAIT valid before CLK high

20

ns

20
21
22

tsu(WTV-CLKH)

SDR mode

Hold time, WAIT valid after CLK highth(CLKH-WTV)

SDR mode0ns

Setup time, WAIT valid before CLK lowtsu(WTV-CLKL)

DDR mode20

ns

Hold time, WAIT valid after CLK lowth(CLKL-WTV)

DDR mode0ns

SDR mode20

ns

DDR mode40ns

SDR mode8ns

DDR mode18

ns

SDR mode8ns

DDR mode

18

ns

uPP Switching Characteristics
12
13
14

See FIGURE 53 through FIGURE 56

Cycle time, CLKtc(CLK)

Pulse width, CLK hightw(CLKH)

Pulse width, CLK lowtw(CLKL)

15

Delay time, START valid after CLK hightd(CLKH-STV)

3

12

ns

16

Delay time, ENABLE valid after CLK hightd(CLKH-ENV)

3

12

ns

17

Delay time, DATA valid after CLK hightd(CLKH-DV)

3

12

ns

18

Delay time, DATA valid after CLK low

td(CLKL-DV)

3

12

ns

See footnote at end of table.

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PAGE 36TABLE I. Electrical performance characteristics - Continued. 1/
1/

Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the
specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may
not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization
and/or design.
2/Over recommended operating conditions (unless otherwise noted).
3/
See Table 3-2 in manufacturer data for a list of pins with a pullup or pulldown.
4/
The MAX input leakage shown on ADCINB0 is at high temperature.
5/
The PLL lock time here includes the two required PLL lock sequences. Cycle count includes code execution of the PLL
initialization routine, which could vary depending on compiler optimizations and flash wait states.
6/
Using an external clock source. If INTOSC1 or INTOSC2 is used as the clock source, then the maximum frequency is 194 MHz
and the minimum period is 5.15 ns.
7/Lower LSPCLK will reduce device power consumption. The default at reset is SYSCLK/4.
8/
For SYSCLK above 100 MHz, the EPWMCLK must be half of SYSCLK.
9/
A load of 40 pF is assumed for these parameters10/
H = 0.5tc(XCO)
11/
Start-up time is dependent on the crystal and tank circuit components. TI recommends that the crystal vendor characterize theapplication with the chosen crystal.
12/
Program time is at the maximum device frequency. Program time includes overhead of the flash state machine but does notinclude the time to transfer the following into RAM:
• Code that uses flash API to program the flash• Flash API itself• Flash data to be programmed
In other words, the time indicated in this table is applicable after all the required code/data is available in the device RAM, readyfor programming. The transfer time will significantly vary depending on the speed of the emulator used.
Program time calculation is based on programming 144 bits at a time at the specified operating frequency. Program time
includesProgram verify by the CPU. The program time does not degrade with write/erase (W/E) cycling, but the erase time does.
Erase time includes Erase verify by the CPU and does not involve any data transfer.
13/ Erase time includes Erase verify by the CPU.
14/ Rise time and fall time vary with load. These values assume a 40-pF load.
15/ "n" represents the number of qualification samples as defined by GPxQSELn register.
16/ For tw(GPI), pulse width is measured from VIL to VIL for an active low signal and VIH to VIH for an active high signal.
17/
For an explanation of the input qualifier parameters, see Table I, General-Purpose Input Timing Requirements, herein.
18/ This assumes that the ISR is in a single-cycle memory.
19/ This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR(triggered by the wake-up signal) involves additional latency.
20/ This value is based on the flash power-up time, which is a function of the SYSCLK frequency, flash wait states (RWAIT), andFPAC1[PSLEEP]. For more information, see the manufacturer data on Flash and OTP Power-Down Modes and Wakeup
section of the TMS320F2837xD Dual-Core Delfino Microcontrollers Technical Reference Manual. This value can be realized
when SYSCLK is 200 MHz, RWAIT is 3, and FPAC1[PSLEEP] is 0x860.
21/ QUALSTDBY is a 6-bit field in the LPMCR register.
22/ This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR(triggered by the wake-up signal) involves additional latency.
23/ For applications using X1/X2 for OSCCLK, the user must characterize their specific oscillator start-up time as it is dependent on
circuit/layout external to the device. See Table 4-17 from manufacturer data for more information. For applications using
INTOSC1 or INTOSC2 for OSCCLK, see Section 4.7.3.5 from manufacturer data f or toscst. Oscillator start-up time does not
apply to applications using a single-ended crystal on the X1 pin, as it is powered externally to the device.
24/
E = EMxCLK period in ns.
25/
Setup before end of STROBE phase (if no extended wait states are inserted) by which EMxWAIT must be asserted to add
extended wait states. FIGURE 16 and FIGURE 18 describe EMIF transactions that include extended wait states inserted during
the STROBE phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement isto the start of where the HOLD phase would begin if there were no extended wait cycles.

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PAGE 37TABLE I. Electrical performance characteristics - Continued. 1/

26/

27/

28/
29/
30/
31/
32/
33/
34/
35/

36/
37/
38/
39/
40/
41/
42/
43/
44/
45/
46/
47/
48/
49/
50/
51/
52/
53/
54/
55/
56/

TA = Turn around, RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write
hold, MEWC = Maximum external wait cycles. These parameters are programmed through the Asynchronous Bank andAsynchronous Wait Cycle Configuration Registers. These support the following ranges of values: TA[4–1], RS[16–1], RST[64–4],
RH[8–1], WS[16–1], WST[64–1], WH[8–1], and MEWC[1–256]. See the manufacturer data TMS320F2837xD Dual-Core Delfino
Microcontrollers Technical Reference Manual for more information.
EWC = external wait cycles determined by EMxWAIT input signal. EWC supports the following range of values. EWC[256–1].
The maximum wait time before time-out is specified by bit field MEWC in the Asynchronous Wait Cycle Configuration Register.
See the manufacturer data TMS320F2837xD Dual-Core Delfino Microcontrollers Technical Reference Manual for more
information.
The sample window must also be at least as long as 1 ADCCLK cycle for correct ADC operation.
VREFCM = (VREFHI + VREFLO)/2
The VREFCM requirements will not be met if the negative ADC input pin is connected to VSSA or VREFLO.
Typical values are measured with VREFHI = 2.5 V and VREFLO = 0 V. Minimum and Maximum values are tested or characterizedwith VREFHI = 2.5 V and VREFLO = 0 V.
See manufacturer data Section 4.8.1.1.2
Difference from conversion result 32768 when ADCINp = ADCINn = VREFCM.
No missing codes
AC parameters will be impacted by clock source accuracy and jitter, this should be taken into account when selecting the clock
source for the system. The clock source used for these parameters was a high-accuracy external clock fed through the PLL. The
on-chip Internal Oscillator has higher jitter than an external crystal and these parameters will degrade if it is used as a clock
source.
I/O activity is minimized on pins adjacent to ADC input and VREFHI pins as part of best practices to reduce capacitive coupling
and crosstalk.
One ADC operating while all other ADCs are idle.
All ADCs operating with identical ADCCLK, S+H durations, triggers, and resolution.
Any ADCs operating with heterogeneous ADCCLK, S+H durations, triggers, or resolution.
Maximum DC code deviation due to operation of multiple ADCs simultaneously.
Value based on characterization.
For an explanation of the input qualifier parameters, see Table I: in General-Purpose Input Timing Requirements. herein.
See table 4-48 from manufacturer data
The CMPSS DAC is used as the reference to determine how much hysteresis to apply. Therefore, hysteresis will scale with the
CMPSS DAC reference voltage. Hysteresis is available for all comparator input source configurations.
Includes comparator input referred errors
Disturbance error may be present on the CMPSS DAC output for a certain amount of time after a comparator trip.
Per active CMPSS module.
Typical values are measured with VREFHI = 3.3 V and VREFLO = 0 V unless otherwise noted. Minimum and Maximum values aretested or characterized with VREFHI = 2.5 V and VREFLO = 0 V.
Gain error is calculated for linear output range
The DAC output is monotonic.
This is the linear output range of the DAC. The DAC can generate voltages outside this range, but the output voltage will not belinear due to the buffer.
For best PSRR performance, VDAC or VREFHI should be less than VDDA.
Per active Buffered DAC module.
VREFHI = 3.2 V, VDDA = 3.3 V DC + 100 mV Sine.
See manufacturer data TMS320F2837xD Dual-Core Delfino™ MCUs Silicon Errata for limitations in the asynchronous mode.
The MEP step size will be largest at high temperature and minimum voltage on VDD. MEP step size will increase with higher
temperature and lower voltage and decrease with lower temperature and higher voltage. Applications that use the HRPWM
feature should use MEP Scale Factor Optimizer (SFO) estimation software functions. See the manufacturer software libraries fordetails of using SFO functions in end applications. SFO functions help to estimate the number of MEP steps per SYSCLK period
dynamically while the HRPWM is in operation.

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PAGE 38TABLE I. Electrical performance characteristics - Continued. 1/

57/
58/
59/
60/
61/
62/

Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references ofthat signal are also inverted.
2P = 1/CLKG in ns. CLKG is the output of sample rate generator mux. CLKG = CLKSRG / (1 + CLKGDV). CLKSRG can be
LSPCLK, CLKX, CLKR as source. CLKSRG ≤ (SYSCLK/2).
2P = 1/CLKG in ns.
C = CLKRX low pulse width = P.
D = CLKRX high pulse width = P.
For all SPI slave modes, CLKX has to be a minimum of 8 CLKG cycles. Furthermore, CLKG should be LSPCLK/2 by setting
CLKSM = CLKGDV = 1.
The (BRR + 1) condition is Even when (SPIBRR + 1) is even or SPIBRR is 0 or 2. It is Odd when (SPIBRR + 1) is odd and
SPIBRR is greater than 3.

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PAGE 39Case XNOTES:
1. All linear dimensions are in millimeters.
2. This drawing is subject to change without notice.

FIGURE 1. Case outline.

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PAGE 40

Case YNOTES:
1. All linear dimensions are in millimeters.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion.
4. This package is designed to be soldered to a thermal pad on the board. Refer to manufacturer technical Brief, PowePad
Thermally Enhanced Package, Literature No. SLMA002 for information regarding recommended board layout.
5. Falls within JEDEC MO-026.
FIGURE 1. Case outline.

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PAGE 41Case X

Notes
1.
2,

Only the GPIO function is shown on GPIO terminals. See Table 3-1 from manufacturer data for the complete, muxed signal
name.
337-Ball ZWT New Fine Pitch Ball Grid Array (Bottom View) – [Quadrant A].

FIGURE 2. Terminal connections.

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PAGE 42Case X - Continued

Notes
1.
2,

Only the GPIO function is shown on GPIO terminals. See Table 3-1 from manufacturer data for the complete, muxed signal
name.
337-Ball ZWT New Fine Pitch Ball Grid Array (Bottom View) – [Quadrant B].
FIGURE 2. Terminal connections - Continued.

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PAGE 43

Case X - Continued

Notes
1.
2,

Only the GPIO function is shown on GPIO terminals. See Table 3-1 from manufacturer data for the complete, muxed signal
name.
337-Ball ZWT New Fine Pitch Ball Grid Array (Bottom View) – [Quadrant C].
FIGURE 2. Terminal connections - Continued.

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PAGE 44

Case X - Continued

Notes
1.
2,

Only the GPIO function is shown on GPIO terminals. See Table 3-1 from manufacturer data for the complete, muxed signal
name.
337-Ball ZWT New Fine Pitch Ball Grid Array (Bottom View) – [Quadrant D].
FIGURE 2. Terminal connections - Continued.

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PAGE 45

Case Y

Notes
1.
2,

Only the GPIO function is shown on GPIO terminals. See Table 3-1 from manufacturer data for the complete, muxed signal
name.
176-Pin PTP PowerPad Thermally Enhanced Low-Profile Quad Flatpack (Top View).
FIGURE 2. Terminal connections - Continued.

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PAGE 46

FIGURE 3. Functional block diagram.

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PAGE 47

Notes:A.
B.

The �����XRS pin can be driven externally by a supervisor or an external pullup resistor, see Table 3-1 from manufacturer data.
On-chip POR logicwill hold this pin low until the supplies are in a valid range.
After reset from any source (see Section 4.7.2.1 from manufacturer data), the boot ROM code samples Boot Mode pins.
Based on the status of the Boot Mode pin, the boot code branches to destination memory or boot code function. If boot ROM
code executes after power-on conditions (in debugger environment), the boot code execution time is based on the current
SYSCLK speed. The SYSCLK will be based on user environment and could be with or without PLL enabled.

FIGURE 4. Power-on Reset.

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Notes:A.

After reset from any source (see Section 4.7.2.1 from manufacturer data), the boot ROM code samples Boot Mode pins.
Based on the status of the Boot Mode pin, the boot code branches to destination memory or boot code function. If boot ROM
code executes after power-on conditions (in debugger environment), the boot code execution time is based on the current
SYSCLK speed. The SYSCLK will be based on user environment and could be with or without PLL enabled.

FIGURE 5. Warm Reset.

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FIGURE 6. JTAG timing.

FIGURE 7. General Purpose Output timing.

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Notes:
A.
B.
C.
D.

This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It can varyfrom 00 to 0xFF. If QUALPRD = 00, then the sampling period is 1 SYSCLK cycle. For any other value "n", the qualification
sampling period in 2n SYSCLK cycles (that is, at every 2n SYSCLK cycles, the GPIO pin will be sampled).
The qualification period selected through the GPxCTRL register applies to groups of 8 GPIO pins.
The qualification block can take either three or six samples. The GPxQSELn Register selects which sample mode is used.
In the example shown, for the qualifier to detect the change, the input should be stable for 10 SYSCLK cycles or greater. In
other words, the inputs should be stable for (5 x QUALPRD x 2) SYSCLK cycles. This would ensure 5 sampling periods for
detection to occur. Because external signals are driven asynchronously, an 13-SYSCLK-wide pulse ensures reliable
recognition.

FIGURE 8. Sampling Mode.

FIGURE 9. General-Purpose Input Timing.

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FIGURE 10. External interrupt Timing.

Notes:A.

WAKE can be any enabled interrupt, ����������WDINT or �����XRS. After the IDLE instruction is executed, a delay of five OSCCLK cycles(minimum) is needed before the wake-up signal could be asserted.
FIGURE 11. External interrupt Timing.

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Notes:A. IDLE instruction is executed to put the device into STANDBY mode.
B. The LPM block responds to the STANDBY signal, SYSCLK is held for a maximum 16 INTOSC1 clock cycles before being
turned off. This delay enables the CPU pipeline and any other pending operations to flush properly.
C. Clock to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in STANDBY
mode. After the IDLE instruction is executed, a delay of five OSCCLK cycles (minimum) is needed before the wake-up signal
could be asserted.
D. The external wake-up signal is driven active.
E. The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement. Furthermore,this signal must be free of glitches. If a noisy signal is fed to a GPIO pin, the wakeup behavior of the device will not be
deterministic and the device may not exit low-power mode for subsequent wakeup pulses.
F. After a latency period, the STANDBY mode is exited.
G. Normal execution resumes. The device will respond to the interrupt (if enabled).

FIGURE 12. STANDBY Entry and Exit timing diagram.

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Notes:A. IDLE instruction is executed to put the device into HALT mode.
B. The LPM block responds to the HALT signal, SYSCLK is held for a maximum 16 INTOSC1 clock cycles before being turned
off. This delay enables the CPU pipeline and any other pending operations to flush properly.
C. Clocks to the peripherals are turned off and the PLL is shut down. If a quartz crystal or ceramic resonator is used as the clock
source, the internal oscillator is shut down as well. The device is now in HALT mode and consumes very little power. It is
possible to keep the zero-pin internal oscillators (INTOSC1 and INTOSC2) and the watchdog alive in HALT MODE. This isdone by writing a 1 to CLKSRCCTL1.WDHALTI. After the IDLE instruction is executed, a delay of five OSCCLK cycles(minimum) is needed before the wake-up signal could be asserted.
D. When the GPIOn pin (used to bring the device out of HALT) is driven low, the oscillator is turned on and the oscillator wakeup
sequence is initiated. The GPIO pin should be driven high only after the oscillator has stabilized. This enables the provision ofa clean clock signal during the PLL lock sequence. Because the falling edge of the GPIO pin asynchronously begins the
wakeup procedure, care should be taken to maintain a low noise environment prior to entering and during HALT mode.
E. The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement. Furthermore,this signal must be free of glitches. If a noisy signal is fed to a GPIO pin, the wakeup behavior of the device will not be
deterministic and the device may not exit low-power mode for subsequent wakeup pulses.
F. When CLKIN to the core is enabled, the device will respond to the interrupt (if enabled), after some latency. The HALT mode is
now exited.
G. Normal operation resumes.
H. The user must relock the PLL upon HALT wakeup to ensure a stable PLL lock.

FIGURE 13. HALT Entry and Exit timing diagram.

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Notes:A.

CPU1 does necessary application-specific context save to M0/M1 memories if required. This includes GPIO state if using I/O
Isolation. Configures the LPMCR register of CPU1 for HIBERNATE mode. Powers down Flash Pump/Bank, USB-PHY,
CMPSS, DAC, and ADC using their register configurations. The application should also power down the PLL and peripheral
clocks before entering HIBERNATE. In dual-core applications, CPU1 should confirm that CPU2 has entered IDLE/STANDBY
using the LPMSTAT register.
B. IDLE instruction is executed to put the device into HIBERNATE mode.
C. The device is now in HIBERNATE mode. If configured, I/O isolation is turned on, M0 and M1 memories are retained. CPU1
and CPU2 are powered down. Digital peripherals are powered down. The oscillators, PLLs, analog peripherals, and Flash arein their software-controlled Low-Power modes. Dx, LSx, and GSx memories are also powered down, and their memory
contents lost.
D. A falling edge on the GPIOHIBWAKEn pin will drive the wakeup of the devices clock sources INTOSC1, INTOSC2, and X1/X2
OSC. The wakeup source must keep the GPIOHIBWAKEn pin low long enough to ensure full power-up of these clock
sources.
E. After the clock sources are powered up, the GPIOHIBWAKEn must be driven high to trigger the wakeup sequence of theremainder of the device.
F. The BootROM will then begin to execute. The BootROM can distinguish a HIBERNATE wakeup by reading theCPU1.REC.HIBRESETn bit. After the TI OTP trims are loaded, the BootROM code will branch to the user-defined IoRestore
function if it has been configured.
G. At this point, the device is out of HIBERNATE mode, and the application may continue.
H. The IoRestore function is a user-defined function where the application may reconfigure GPIO states, disable I/O isolation,
reconfigure the PLL, restore peripheral configurations, or branch to application code. This is up to the application
requirements.
I. If the application has not branched to application code, the BootROM will continue after completing IoRestore. It will disable
I/O isolation automatically if it was not taken care of inside of IoRestore. CPU2 will be brought out of reset at this point as well.
J. BootROM will then boot as determined by the HIBBOOTMODE register. Refer to the manufacturer data for ROM Code andPeripheral Booting chapter of the TMS320F2837xD Dual-Core Delfino Microcontrollers Technical Reference Manual for more
information.
FIGURE 14 HIBERNATE Entry and Exit timing diagram.

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FIGURE 15 Asynchronous Memory Read Timing.

FIGURE 16 EMxWAIT Read Timing Requirements.

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FIGURE 17 Asynchronous Memory Write Timing.

FIGURE 18 EMxWAIT Write Timing Requirements.

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FIGURE 19 Basic SDRAM Read Operation.

FIGURE 20 Basic SDRAM Write Operation.

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FIGURE 21 Single-Ended Input Model.

FIGURE 22 Differential Input Model.

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FIGURE 23 ADC Timings for 12-Bit Mode.

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FIGURE 24 ADC Timings for 16-Bit Mode.

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PAGE 61FIGURE 25 CMPSS Comparator Input Referred Offset.

FIGURE 26 CMPSS Comparator Hysteresis.

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FIGURE 27 CMPSS DAC Static Offset.

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FIGURE 28 CMPSS DAC Static Gain.

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FIGURE 29 CMPSS DAC Static Linearity.

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FIGURE 30 Buffered DAC Offset.

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FIGURE 31 Buffered DAC Gain.

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FIGURE 32 Buffered DAC Linearity.

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Notes:A.
B.

�����, TZ2�����, TZ3�����, TRIP1 – TRIP12.
����: TZ1
TZ���� is taken high dependens on the
PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ
PWM recovery software.
FIGURE 33 PWM Hi-Z Characteristics.

FIGURE 34 ���������������
ADCSOCAO or ���������������
ADCSOCBO Timing.

FIGURE 35 SDFM Timing Diagram – Mode 0.

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PAGE 69FIGURE 36 SDFM Timing Diagram – Mode 1.

FIGURE 37 SDFM Timing Diagram – Mode 2.

FIGURE 38 SDFM Timing Diagram – Mode 3.

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FIGURE 39 McBSP Receive Timing.

FIGURE 40 McBSP Transmit Timing.

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FIGURE 41 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0.

FIGURE 42 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0.

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FIGURE 43 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1.

FIGURE 44 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1.

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Notes:1.

On the trailing end of the word, ���������SPISTE will go inactive except between back-to-back transmit words in both FIFO and nonFIFO modes.
FIGURE 45 SPI Master Mode External Timing (Clock Phase = 0).

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Notes:2.

On the trailing end of the word, ���������SPISTE will go inactive except between back-to-back transmit words in both FIFO and nonFIFO modes.
FIGURE 46 SPI Master Mode External Timing (Clock Phase = 1).

FIGURE 47 SPI Slave Mode External Timing (Clock Phase = 0).

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FIGURE 48 SPI Slave Mode External Timing (Clock Phase = 1).

Notes:
1.

On the trailing end of the word, ���������SPISTE will go inactive except between back-to-back transmit words in both FIFO and nonFIFO modes.
FIGURE 49 High-Speed SPI Master Mode External Timing (Clock Phase = 0).

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Notes:1.

On the trailing end of the word, ���������SPISTE will go inactive except between back-to-back transmit words in both FIFO and nonFIFO modes.
FIGURE 50 High-Speed SPI Master Mode External Timing (Clock Phase = 1).

FIGURE 51 High-Speed SPI Slave Mode External Timing (Clock Phase = 0).

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FIGURE 52 High-Speed SPI Slave Mode External Timing (Clock Phase = 1).

FIGURE 53 µPP Single Data Rate (SDR) Receive Timing.

FIGURE 54 µPP Double Data Rate (DDR) Receive Timing.

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FIGURE 55 µPP Single Data Rate (SDR) Transmit Timing.

FIGURE 56 µPP Double Data Rate (DDR) Transmit Timing.

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4. VERIFICATION
4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as
indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices,classification, packaging, and labeling of moisture sensitive devices, as applicable.
5. PREPARATION FOR DELIVERY
5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial
practices for electrostatic discharge sensitive devices.
6. NOTES
6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum.
6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book.
The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided.
6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee
of present or continued availability as a source of supply for the item. DLA Land and Maritime maintains an online database of all
current sources of supply at https://landandmaritimeapps.dla.mil/programs/smcr/.

1/
2/

Vendor item drawing
administrative control
number 1/

Devicemanufacturer
CAGE code

Vendor part number

V62/18601-01XF 2/

01295

TMS320F28377DGWTEP

V62/18601-01YE

01295

TMS320F28377DPTPEP

The vendor item drawing establishes an administrative control number for
identifying the item on the engineering documentation.
Devices listed on this drawing are supplied to lead finish “F”. The solder ballmaterial contains compositions of Sn = 63%, Pb = 34.5%, Ag = 2 %, andSb = 0.5%.

CAGE code

Source of supply

01295

DLA LAND AND MARITIMECOLUMBUS, OHIO

Texas Instruments, Inc.
Semiconductor Group
8505 Forest Lane
P.O. Box 660199
Dallas, TX 75243

SIZE
A

CAGE CODE
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