REVISIONSLTR

DESCRIPTIONDATE (YR-MO-DA)APPROVEDA

Update boilerplate paragraphs to current VID description requirements. - DRH

22-09-26

Muhammad A. Akbar

CURRENT DESIGN ACTIVITY CAGE CODE 16236
HAS CHANGED NAMES TO:
DLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990

Prepared in accordance with ASME Y14.24

Vendor Item Drawing

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PMIC N/A
Original date ofdrawing
09-04-07

PREPARED BY
Phu H. Nguyen
CHECKED BY
Phu H. Nguyen
APPROVED BY
Thomas M. HessSIZE
CAGE CODEA
REVAMSC N/A

DLA LAND AND MARITIMECOLUMBUS, OHIO 43218-3990
https://www.dla.mil/landandmaritime

16236
A

TITLE

MICROCIRCUIT, DIGITAL, MIXED SIGNALMICROCONTROLLER, MONOLITHIC SILICONDWG NO.

PAGE

DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.

V62/09601
1 OF 405962-V100-22

1. SCOPE
1.1 Scope. This drawing documents the general requirements of a high performance mixed signal microcontroller microcircuit, with anoperating temperature range of -55°C to +125°C.
1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing
establishes an administrative control number for identifying the item on the engineering documentation:
V62/09601-

Drawing
number

01

X

A

Device type
(See 1.2.1)

Case outline(See 1.2.2)

Lead finish(See 1.2.3)

1.2.1 Device type(s).
Device type

Generic

01

Circuit function

MSP430F249-EP

Mixed signal microcontroller

1.2.2 Case outline(s). The case outlines are as specified herein.
Outline letter

Number of pins

JEDEC PUB 95

Package style

X

64

JEDEC MO-220

Plastic quad flatpack

1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer:
Finish designator

Material

A
B
C
D
E
Z

Hot solder dip
Tin-lead plate
Gold plate
PalladiumGold flash palladium
Other

1.3 Absolute maximum ratings. 1/
Voltage applied at VCC to VSS ........................................................................................ -0.3 V to 4.1 V
Voltage applied to any pin ............................................................................................. -0.3 V to VCC + 0.3 V
Diode current at any device terminal ............................................................................. ±2 mA
Storage temperature range, TSTG (unprogrammed device) ............................................ -55°C to 150°C 3/
Storage temperature range, TSTG (programmed device) ................................................ -55°C to 125°C 3/2/__________
1/

2/
3/

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stressratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended
operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device
reliability.
All voltages referenced to VSS. The JTAG fuse blow voltage, VFB, is allowed to exceed the absolute maximum rating. The
voltage is applied to the TDI/TCLK pin when blowing the JTAG fuse.
Higher temperature may be applied during board soldering process according to the current JEDEC J-STD-020 specification withpeak reflow temperatures not higher than classified on the device label on the shipping boxes or reels.

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PAGE 2

1.4 Recommended operating conditions. 4/
Supply voltage during program execution (VCC) (AVCC = DVCC = VCC) .......................... 1.8 V to 3.6 V 5/
Supply voltage during flash memory programming (VCC) (AVCC = DVCC = VCC) ............ 2.2 V to 3.6 V 5/
Supply voltage (VSS) (AVSS = DVSS = VSS)...................................................................... 0 V
Processor frequency fSYSTEM (Maximum MCLK frequency): 6/ 7/ 8/
VCC = 1.8 V, Duty Cycle 50% ±10% ....................................................................... 4.15 MHz
VCC = 2.7 V, Duty Cycle 50% ±10% ....................................................................... 12 MHz
VCC ≥ 3.3 V, Duty Cycle 50% ±10% ....................................................................... 16 MHz
Flash temperature range:
Read ...................................................................................................................... -55°C to 125°C
Write ....................................................................................................................... -55°C to 125°C
Operating free air temperature range, TA ...................................................................... -55°C to 125°C
2. APPLICABLE DOCUMENTS
SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC)JEDEC JEP95
JEDEC J-STD-020––

Registered and Standard Outlines for Semiconductor Devices.
Joint IPC/JEDEC standard for moisture/reflow sensitivity classification for nonhermetic solid state
surface mount devices.

(Copies of these documents are available online at https://www.jedec.org.)
3. REQUIREMENTS
3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as
follows:
A.
B.
C.

Manufacturer’s name, CAGE code, or logo
Pin 1 identifier
ESDS identification (optional)

3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable)
above.
3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as
specified in 1.3, 1.4, and table I herein.
3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein.

__________
4/
5/
6/
7/
8/

Use of this product beyond the manufacturers design rules or stated parameters is done at the user’s risk. The manufacturer
and/or distributor maintain no responsibility or liability for product used beyond the stated limits.
It is recommended to power AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC
can be tolerated during power up.
The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of thespecified maximum frequency.
Modules might have a different maximum input clock specification. Refer to the data sheet from manufacturer.
See figure 4.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
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PAGE 3

3.5 Diagrams.
3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1.
3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2.
3.5.3 Functional block diagram. The functional block diagram shall be as shown in figure 3.
3.5.4 Operating area. The operating area shall be as shown in figure 4.
3.5.5 Active mode supply current. The active mode supply current shall be as shown in figure 5.
3.5.6 POR/Brownout reset. The POR/Brownout reset shall be as shown in figure 6-8.
3.5.7 Test circuit and timing waveforms. The test circuit and timing waveforms shall be as shown in figure 9-15.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
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PAGE 4TABLE I. Electrical performance characteristics. 1/
Test

SymbolConditions 2/
unless otherwise specified

TA

VCC

Active mode supply current (into DVCC + AVCC) Excluding External current 3/ 4/
Active mode (AM) current
IAM, 1MHz fDCO = fMCLK = fSMCLK = 1 MHz,
-55°C to 105°C 2.2 V(1 MHz)fACLK = 32,768 Hz,
Program executes from flash,
125°C
BCSCTL1 = CALBC1_1MHz,
DCOCTL = CALDCO_1 MHz-55°C to 105°C 3 V
CPUOFF = 0, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
125°C
Active mode (AM) current(1 MHz)Active mode (AM) current(4 kHz)Active mode (AM) current(100 kHz)IAM, 1MHz fDCO = fMCLK = fSMCLK = 1 MHz,fACLK = 32,768 Hz,
Program executes in RAM,BCSCTL1 = CALBC1_1MHz,
DCOCTL = CALDCO_1 MHz
CPUOFF = 0, SCG0 = 0, SCG1 = 0,
OSCOFF = 0-55°C to 105°C 2.2 V

IAM, 4kHz fMCLK = fSMCLK= fACLK = 32,768 Hz/8 =4096 Hz, fDCO = 0 Hz,
Program executes in flash,
SELMx = 11, SELS = 1,
DIVMx = DIVSx = DIVAx = 11,
CPUOFF = 0, SCGO = 0, SCG1 = 0,
OSCOFF = 0-55°C to 105°C 2.2 V

IAM,
100kHzfMCLK = fSMCLK= fDCO(0,0) ≈ 100 kHz,fACLK = 0 Hz,
Program executes in flash,
RSELx = 0, DCOx = 0, CPUOFF = 0,
SCGO = 0, SCG1 = 0, OSCOFF = 1

3V

3V

Low power mode 0,(LPM0) current 5/

ILPM0,
1 MHz-55°C to 105°C 2.2 V

ILPM0,
100 kHz

3V-55°C to 105°C 2.2 V

386 TYP
449
230 TYPfMCLK = 0 MHz, fSMCLK= fDCO(0,0) ≈ 100
kHz, fACLK = 0 Hz,
RSELx = 0, DCOx = 0, CPUOFF = 1,
SCGO = 0, SCG1 = 0, OSCOFF = 1-55°C to 105°C 2.2 V

321 TYP

1.5 TYPDLA LAND AND MARITIMECOLUMBUS, OHIO

µA

2 TYP

55 TYPµA

67 TYP

60 TYP

3VµA

75 TYP
98

125°C

33 TYP
45

125°C
3V

36 TYP50

See footnotes at end of table.

SIZE
A

µA

88

125°C

125°C

318

100

fMCLK = 0 MHz, fSMCLK= fDCO = 1 MHz,fACLK = 32,768 Hz,
BCSCTL1 = CALBC1_1 MHz,DCOCTL = CALDCO_1 MHz,CPUOFF = 1, SCG0 = 0, SCG1 = 0,
OSCOFF = 0-55°C to 105°C

µA

81

125°C

-55°C to 105°C

275 TYP

12.2

125°C

125°C
Low power mode 0,(LPM0) current 5/

Max

10.5

125°C

-55°C to 105°C

Min

Unit

370

125°C

-55°C to 105°C

01

Limits267

125°C-55°C to 105°C

Devicetype

CAGE CODE
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PAGE 5µA

TABLE I. Electrical performance characteristics – Continued. 1/
Test

SymbolConditions 2/
unless otherwise specified

TA

VCC

Active mode supply current (into DVCC + AVCC) Excluding External current - Continued 3/ 4/
Low power mode 2
ILPM2 fMCLK = fSMCLK= 0 MHz, fDCO = 1 MHz, -55°C to 105°C 2.2 V(LPM2) current 6/
fACLK = 32,768 Hz,
BCSCTL1 = CALBC1_1MHz,
125°C
DCOCTL = CALDCO_1 MHz,CPUOFF = 1, SCG0 = 0, SCG1 = 1,
-55°C to 105°C 3 V
OSCOFF = 0
125°C
Low power mode 3(LPM3) current 6/

ILPM3,LFXT1

fDCO = fMCLK = fSMCLK = 0 MHz,fACLK = 32,768 Hz,
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 0-55°C

ILPM3,VLO

fDCO = fMCLK = fSMCLK = 0 MHz,fACLK = from internal LF oscillator (VLO),CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 0

fDCO = fMCLK = fSMCLK = 0 MHz,fACLK = 0 Hz,
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 1

Min

Unit

Max

20 TYP

23 TYP48
0.8 TYP

105°C

15

125°C

22
3V

1.4

105°C

17

125°C

27
2.2 V

0.3 TYP

25°C

0.9

105°C

4.5

125°C

15
3V

1

105°C

5.5

125°C

16

25°C

2.2 V/
3V

0.1 TYP
0.5

105°C

13

125°C

22

See footnotes at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
A

µA

0.4 TYP

25°C

-55°C

µA

0.9 TYP

25°C

-55°C

µA

42

1.3

-55°C

Low power mode 4
current (LPM4) 7/

01

Limits

25°C

-55°C

Low power mode 3
current (LPM3) 6/

2.2 V

Devicetype

CAGE CODE
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PAGE 6µA

TABLE I. Electrical performance characteristics – Continued. 1/
Test

SymbolConditions-55°C ≤ TA ≤ 125°C 2/
unless otherwise specified

VCC

Schmitt-trigger inputs – ports P1, P2, P3, P4, P5, P6, RST/RST, JTAG, XIN, and XT2IN) 8/
Positive going input threshold voltage
VIT+

Negative going input threshold voltage

Device
type

01

Vhys

Pullup/Pulldown resistor

RPull

Input capacitance

CI

Inputs – ports P1 and P2
External interrupt timingt(int)

Timer_A, Timer_B capture timing

tcap

Timer_A, Timer_B clock frequency

fTAextexternally applied to pin

fTBextTimer_A, Timer_B clock frequency

fTAintHigh level input voltage

VIH

0.45 VCC 0.75 VCC
1

1.65

3V

1.35

2.25
1.2

3V

0.75

1.65

2.2 V

0.2

1

3V

0.3

1

20

50

kΩ

5 TYP

pF

01

20
62

3V

50

TACLK, TBCLK, INCLK: t(H) = t(L)

2.2 V

8

3V

10

2.2 V

8

3V

10

2.2 V/
3V01

2.2 V/
3V

01

MHz

±50

nA

VSS

VSS + 0.6

V

0.8VCCVCC

See footnotes at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIOVns

TB0, TB1, TB2, TB3, TB4, TB5, TB6

SIZE
A

V

0.55

Port P1, P2: P1.x to P2.x, external trigger 2.2 V/
pulse width to set interrupt flag 9/
3V
TA0, TA1, TA2
2.2 V

SNCLK or ACLK signal selected

V

2.2 V

Pullup: VIN = VSS;
Pulldown: VIN = VCC
VIN = VSS or VCC

Leakage current – ports P1, P2, P3, P4, P5, and P6High impedance leakage current
Ilkg(Px.x)
10/ 11/

VIL

Max

0.25 VCC 0.55VCC

fTBintStandard inputs - RST/NMI
Low level input voltage

Min

Unit

2.2 V
VIT-

Input voltage hysteresis (VIT+ - VIT-)

LimitsCAGE CODE
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TABLE I. Electrical performance characteristics – Continued. 1/
Test

SymbolConditions-55°C ≤ TA ≤ 125°C 2/
unless otherwise specified

Outputs – ports P1, P2, P3, P4, P5, and P6High level output voltage
VOH IOH(max) = -1.5 mA
IOH(max) = -6 mA
IOH(max) = -1.5 mA
Low level output voltage

VOL

12/
12/
13/

IOL(max) = 1.5 mA

12/IOL(max) = 1.5 mA
IOL(max) = 6 mA

2.2 V

Device
type

01

13/

IOH(max) = -6 mA
IOL(max) = 6 mA

VCC

3V
2.2 V

13/
12/

3V

13/

Limits

Unit

Min

Max

VCC–0.25

VCC

VCC–0.6

VCC

VCC–0.25

VCC

VCC–0.6

VCC

VSS

VSS+0.25

VSS

VSS+0.6

VSS

VSS+0.25

VSS

VSS+0.6DC

10

Output frequency – ports P1, P2, P3, P4, P5, and P6
Port output frequency
fPx.y P1.4/SMCLK, CL = 20 pF, RL = 1 kΩ(with load)
14/ 15/

2.2 V
3V

DC

12

Clock output frequency

2.2 V

DC

12

3V

DC

16

Duty cycle of output frequency

fPort_CLK P2.0/ACLK/CA2, P1.4/SCMCLK,
CL = 20 pF, RL = 1 kΩ
15/t(Xdc)

01

P1.0/TACLK/CAOUT, CL = 20 pF, LF mode

30

P1.0/TACLK/CAOUT, CL = 20 pF, XT1 mode

40

P1.0/TA0, CL = 20 pF, XT1 mode

40

P1.0/TA0, CL = 20 pF, DCO
P1.4/SMCLK, CL = 20 pF, XT2 MODE
P1.4/SMCLK, CL = 20 pF, DCO
POR/brownout reset (BOR) 16/
Operating voltage

17/
VCC(start) dVCC/dt ≤ 3 V/s See figure 6

01

Negative going VCC reset threshold V(B_IT-) dVCC/dt ≤ 3 V/s See figure 6-8
voltage
VCC reset threshold hysteresis
Vhys(B_IT-) dVCC/dt ≤ 3 V/s See figure 6
BOR reset release delay timetd(BOR) See figure 6

Pulse length needed at RST/NMI
pin to accepted reset internallySee footnotes at end of table.

t(reset)DLA LAND AND MARITIMECOLUMBUS, OHIO

2.2 V/
3V

SIZE
A

V

MHz

MHz

%

50% - 15
ns
40

50% +
15 ns
60

50% - 15
ns

50% +
15 ns

0.7xV(B_IT-) TYP

70

V

%

V

1.71

V

210

mV

2000

µs

2

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PAGE 8µs

TABLE I. Electrical performance characteristics – Continued. 1/
Test

SymbolSVS (supply voltage supervisor/monitor)t(SVSR)

Conditions-55°C ≤ TA ≤ 125°C 2/
unless otherwise specified
dVCC/dt > 30 V/ms

See figure 9

Devicetype

01

Limits
Min

Max

5

150

dVCC/dt ≤ 30 V/ms
SVSON, switch from VLD = 0 to VLD ≠ 0, VCC = 3 V

tsettle

VLD ≠ 0See footnotes at end of table.

See figure 9

See figure 9

VLD = 1

DLA LAND AND MARITIMECOLUMBUS, OHIOdVCC/dt ≤ 3 V/s, External voltage
applied on A7,
See figure 9
dVCC/dt ≤ 3 V/s See figure 9-10

dVCC/dt ≤ 3 V/s, External voltage
applied on A7, See figure 9-10
VLD ≠ 0, VCC = 2.2 V/3 V

SIZE
A

150
12

VLD = 2 to 14

ICC(SVS)
20/

20

19/

V(SVSstart) VLD ≠ 0, VCC/dt ≤ 3 V/s

V(SVS_IT-)

µs

2000

td(SVSon)

Vhys(SVS_IT-) dVCC/dt ≤ 3 V/s

Unit

VLD = 15

70

1.7

V

210

mV

0.001 x 0.016 x
V(SVS_IT-) V(SVS_IT-)
4.4
20

VLD = 1

1.8

2.05

VLD = 2

1.94

2.25

VLD = 3

2.05

2.37

VLD = 4

2.14

2.48

VLD = 5

2.24

2.60

VLD = 6

2.33

2.71

VLD = 7

2.46

2.86

VLD = 8

2.58

3.00

VLD = 9

2.69

3.13

VLD = 10

2.83

3.29

VLD = 11

2.94

3.42

VLD = 12

3.11

3.61 18/

VLD = 13

3.24

3.76 18/

VLD = 14

3.43

3.99 18/

VLD = 15

1.1

1.3
15

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PAGE 9mVVµA

TABLE I. Electrical performance characteristics – Continued. 1/
Test

DCO frequency
Supply voltage range

SymbolVCC

Conditions-55°C ≤ TA ≤ 125°C 2/
unless otherwise specified

VCC

Devicetype

Limits

Unit

Min

Max

1.8

3.6

RSELx = 14

2.2

3.6

RSELx = 15

3.0

3.6

0.06

0.14

0.07

0.17

RSELx < 1401

DCO frequency (0, 0)

fDCO(0,0) RSELx = 0, DCOx = 0, MODx = 0

DCO frequency (0, 3)

fDCO(0, 3) RSELx = 0, DCOx = 3, MODx = 0

DCO frequency (1,3)

fDCO(1, 3) RSELx = 1, DCOx = 3, MODx = 0

0.10

0.20

DCO frequency (2, 3)

fDCO(2, 3) RSELx = 2, DCOx = 3, MODx = 0

0.14

0.28

DCO frequency (3, 3)

fDCO(3, 3) RSELx = 3, DCOx = 3, MODx = 0

0.20

0.40

DCO frequency (4, 3)

fDCO(4, 3) RSELx = 4, DCOx = 3, MODx = 0

0.28

0.54

DCO frequency (5, 3)

fDCO(5, 3) RSELx = 5, DCOx = 3, MODx = 0

0.39

0.77

DCO frequency (6, 3)

fDCO(6, 3) RSELx = 6, DCOx = 3, MODx = 0

0.54

1.06

DCO frequency (7, 3)

fDCO(7, 3) RSELx = 7, DCOx = 3, MODx = 0

0.80

1.50

DCO frequency (8, 3)

fDCO(8, 3) RSELx = 8, DCOx = 3, MODx = 0

1.10

2.10

DCO frequency (9, 3)

fDCO(9, 3) RSELx = 9, DCOx = 3, MODx = 0

1.60

3.00

DCO frequency (10, 3)

fDCO(10, 3) RSELx = 10, DCOx = 3, MODx = 0

2.50

4.30

DCO frequency (11, 3)

fDCO(11, 3) RSELx = 11, DCOx = 3, MODx = 0

3.00

5.50

DCO frequency (12, 3)

fDCO(12, 3) RSELx = 12, DCOx = 3, MODx = 0

4.30

7.30

DCO frequency (13, 3)

fDCO(13, 3) RSELx = 13, DCOx = 3, MODx = 0

6.00

9.60

DCO frequency (14, 3)

fDCO(14, 3) RSELx = 14, DCOx = 3, MODx = 0

8.60

13.9

DCO frequency (15, 3)

fDCO(15, 3) RSELx = 15, DCOx = 3, MODx = 0

3V

12.0

18.5

DCO frequency (15, 7)

fDCO(15, 7) RSELx = 15, DCOx = 7, MODx = 0

3V

16.0

26.0

Frequency step between range
RSEL and RSEL+1
Frequency step between tap DCO
and DCO+1
Duty cycle

SRSEL SRSEL = fDCO(RSEL+1, DCO) /fDCO(RSEL,DCO)

2.2 V/
3V

1.35

2.00

ratio

1.07

1.16

ratio

40

60

%

SDCO

SDCO = fDCO(RSEL,DCO+1)/fDCO(RSEL,DCO)

2.2 V/
3V

V

Measured at P1.4/SMCLK

See footnotes at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
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PAGE 10MHzTABLE I. Electrical performance characteristics – Continued. 1/
Test

SymbolConditions-55°C ≤ TA ≤ 125°C 2/
unless otherwise specified

VCC

Devicetype

Limits

Unit

Min

Max

-1

1

%

0.990

1.010

MHz

7.920

8.080

11.88

12.12

15.84

16.16

-2.5

2.5

8 MHz tolerance over temperature

-2.5

2.5

12 MHz tolerance over temperature

-2.5

2.5

16 MHz tolerance over temperature

-3.0

3.0

0.970
0.975
0.970
7.760
7.800
7.600
11.64
11.64
11.64
15.52
15.00

1.030
1.025
1.030
8.400
8.200
8.240
12.36
12.36
12.36
16.48
16.48

Calibrated DCO frequencies (Tolerance at Calibration)
Frequency tolerance at calibration
TA = 25°C
1 MHz calibration value

3V

fCAL(1 MHz) BCSCTL1 = CALBC1_1MHz,

DCOCTL = CALDCO_1MHz,
Gating time: 5 ms, TA = 25°C
8 MHz calibration valuefCAL(8 MHz) BCSCTL1 = CALBC1_8MHz,
DCOCTL = CALDCO_8MHz,
Gating time: 5 ms, TA = 25°C
12 MHz calibration valuefCAL(12 MHz) BCSCTL1 = CALBC1_12MHz,
DCOCTL = CALDCO_12MHz,
Gating time: 5 ms, TA = 25°C
16 MHz calibration valuefCAL(16 MHz) BCSCTL1 = CALBC1_16MHz,
DCOCTL = CALDCO_16MHz,
Gating time: 2 ms, TA = 25°C
Calibrated DCO frequencies (Tolerance over temperature)
1 MHz tolerance over temperature

1 MHz calibration value
8 MHz calibration value
12 MHz calibration value
16 MHz calibration value
See footnotes at end of table.

01

3V

fCAL(1 MHz) BCSCTL1 = CALBC1_1MHz,
DCOCTL = CALDCO_1MHz,
Gating time: 5 ms
fCAL(8 MHz) BCSCTL1 = CALBC1_8MHz,
DCOCTL = CALDCO_8MHz,
Gating time: 5 ms
fCAL(12 MHz) BCSCTL1 = CALBC1_12MHz,
DCOCTL = CALDCO_12MHz,
Gating time: 5 ms
fCAL(16 MHz) BCSCTL1 = CALBC1_16MHz,
DCOCTL = CALDCO_16MHz,
Gating time: 2 ms

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
A

2.2 V
3V
3.6 V
2.2 V
3V
3.6 V
2.2 V
3V
3.6 V
3V
3.6 V

01

CAGE CODE
16236

DWG NO.
V62/09601

REV A

PAGE 11%MHz

TABLE I. Electrical performance characteristics – Continued. 1/
Test

SymbolConditions-55°C ≤ TA ≤ 125°C 2/
unless otherwise specified

VCC

Devicetype

Limits

Unit

Min

Max

-3

3

Calibrated DCO frequencies (Tolerance over supply voltage VCC)
1 MHz tolerance over VCC
TA = 25°C

1.8 V to 3.6 V

8 MHz tolerance over VCC

1.8 V to 3.6 V-33

12 MHz tolerance over VCC

2.2 V to 3.6 V-33

16 MHz tolerance over VCC

3 V to 3.6 V-33

1.8 V to 3.6 V

0.970

1.030

1.8 V to 3.6 V

7.760

8.240

2.2 V to 3.6 V

11.64

12.36

3 V to 3.6 V

15.00

16.48

-5

+5

1 MHz calibration valuefCAL(1 MHz) BCSCTL1 = CALBC1_1MHz,

DCOCTL = CALDCO_1MHz,
Gating time: 5 ms, TA = 25°C
8 MHz calibration valuefCAL(8 MHz) BCSCTL1 = CALBC1_8MHz,
DCOCTL = CALDCO_8MHz,
Gating time: 5 ms, TA = 25°C
12 MHz calibration valuefCAL(12 MHz) BCSCTL1 = CALBC1_12MHz,
DCOCTL = CALDCO_12MHz,
Gating time: 5 ms, TA = 25°C
16 MHz calibration valuefCAL(16 MHz) BCSCTL1 = CALBC1_16MHz,
DCOCTL = CALDCO_16MHz,
Gating time: 2 ms, TA = 25°C
Calibrated DCO frequencies (Overall tolerance)
1 MHz tolerance over temperature

1.8 V to 3.6 V

01

01

8 MHz tolerance over temperature

1.8 V to 3.6 V-5+5

12 MHz tolerance over temperature

2.2 V to 3.6 V-5+5

16 MHz tolerance over temperature

3 V to 3.6 V-6+6

1.8 V to 3.6 V

0.950

1.050

1.8 V to 3.6 V

7.6

8.4

2.2 V to 3.6 V

11.4

12.6

3 V to 3.6 V

15.00

17.00

1 MHz calibration value

8 MHz calibration value

12 MHz calibration value

16 MHz calibration value

See footnotes at end of table.

fCAL(1 MHz) BCSCTL1 = CALBC1_1MHz,
DCOCTL = CALDCO_1MHz,
Gating time: 5 ms, TA = 25°C
fCAL(8 MHz) BCSCTL1 = CALBC1_8MHz,
DCOCTL = CALDCO_8MHz,
Gating time: 5 ms
fCAL(12 MHz) BCSCTL1 = CALBC1_12MHz,
DCOCTL = CALDCO_12MHz,
Gating time: 5 ms
fCAL(16 MHz) BCSCTL1 = CALBC1_16MHz,
DCOCTL = CALDCO_16MHz,
Gating time: 2 ms

DLA LAND AND MARITIMECOLUMBUS, OHIOSIZEACAGE CODE
16236

DWG NO.
V62/09601

REV A

PAGE 12

%

MHz

%

MHz

TABLE I. Electrical performance characteristics – Continued. 1/
Test

SymbolConditions-55°C ≤ TA ≤ 125°C 2/
unless otherwise specified

VCC

Wake up from lower power Modes (LPM3/4)
DCO clock wake up time from
tDCO,LPM3/4 BCSCTL1 = CALBC1_1MHz,
LPM3/4 21/
DCOCTL = CALDCO_1MHz,BCSCTL1 = CALBC1_8MHz,
DCOCTL = CALDCO_8MHz,BCSCTL1 = CALBC1_12MHz,
DCOCTL = CALDCO_12MHz,BCSCTL1 = CALBC1_16MHz,
DCOCTL = CALDCO_16MHz,
CPU wake up time from LPM3/4
tCPU,LPM3/4
22/
DCO with external resistor ROSC
24/
DCO output frequency with ROSC
fDCO,ROSC DCOR = 1, RSELx = 4, DCOx = 3,
MODx = 0, TA = 25°C
Temperature drift

2.2 V/3 V

Devicetype

Limits
Min

01

µs

1.5
1
3V

1
1/fMCLK + tClock,LPM3/4
TYP

2.2 V

01

3V

DCOR = 1, RSELx = 4, DCOx = 3,
MODx = 0
Drift with VCC
DV
DCOR = 1, RSELx = 4, DCOx = 3,
MODx = 0
Crystal Oscillator (LFXT1) Low frequency Modes 21/
LFXT1 oscillator crystal frequency,
fLFXT1,LF XTS = 0, LFXT1Sx = 0 or 1
1.8V to 3.6V
LF mode 0, 1
LFXT1 oscillator logic level square fLFXT1,LF,logic XTS = 0, LFXT1Sx = 3
wave input frequency, LF mode
Oscillation allowance for LF crystal
OALF
XTS = 0, LFXT1Sx = 0;
fLFXT1,LF = 32,768 Hz, CL,eff = 6 pF
XTS = 0, LFXT1Sx = 0;
fLFXT1,LF = 32,768 Hz, CL,eff = 12 pF
Integrated effective load
CL,eff
XTS = 0
XCAPx = 0
capacitance, LF mode 25/
XCAPx = 1
XCAPx = 2
XCAPx = 3
LF modeDuty cycle XTS = 0, Measured at P1.4/ACLK,
2.2 V/3 V
fLFXT1,LF = 32,768 Hz
Oscillator fault frequency
fFault,LF
XTS = 0, LFXT1Sx = 3
27/
2.2 V/3 V
threshold, LF mode 26/
See footnotes at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

Max
2

1.8 TYP

MHz

1.95 TYP

Dt

SIZE
A

Unit

01

±0.1 TYP%/°C

10 TYP%/V

32,768 TYP

Hz

10

kHz

50
500 TYPkΩ

200 TYP
1 TYP
5.5 TYP
8.5 TYP
11 TYP
30
70

pF

10

Hz

10000

CAGE CODE
16236

DWG NO.
V62/09601

REV A

PAGE 13%TABLE I. Electrical performance characteristics – Continued. 1/
Test

SymbolConditions-55°C ≤ TA ≤ 125°C 2/
unless otherwise specified

VCC

Internal very low power, Low frequency oscillator (VLO)
VLO frequency
fVLO
TA = -55°C to 85°C

2.2 V/3 V

Devicetype

01

Limits
Min

Max

4

20

dfVLO/dT

28/

VLO frequency supply voltage drift dfVLO/dVCC TA = 25°C

Integrated effective load
capacitance, HF mode 25/
HF modeOscillator fault frequency, HF
mode 26/
See footnotes at end of table.

CL,eff

%/V

0.4

1

MHz

1.8 V to 3.6 V

14

1.8 V to 3.6 V

210

2.2 V to 3.6 V

212

3 V to 3.6 V

216

1.8 V to 3.6 V

0.4

10

2.2 V to 3.6 V

0.4

12

3 V to 3.6 V

0.4

16

SIZE
A

01

2700 TYP

XTS = 0, LFXT1Sx = 0;
fLFXT1,HF = 1 MHz, CL,eff = 15 pF
XTS = 0, LFXT1Sx = 1;
fLFXT1,HF = 1 MHz, CL,eff = 15 pF
XTS = 0, LFXT1Sx = 2;
fLFXT1,HF = 1 MHz, CL,eff = 15 pF
XTS = 1, XCAPx = 0 30/Ω

800 TYP
300 TYP
1 TYP

Duty cycle XTS = 1, XCAPx = 0, Measured
at P1.4/ACLK, fLFXT1,HF = 10 MHz
XTS = 1, XCAPx = 0, Measured
at P1.4/ACLK, fLFXT1,HF = 16 MHz
fFault,HF XTS = 1, LFXT1Sx = 3,
XCAPx = 0 27/

DLA LAND AND MARITIMECOLUMBUS, OHIO

%/°C

4 TYP

1.8 V to 3.6 V

LFXT1 oscillator logic level square fLFXT1,HF,logic XTS = 1, LFXT1Sx = 3
wave input frequency, HF mode

OAHF

0.5 TYP
1.8 V to 3.6 V

29/

Crystal Oscillator (LFXT1) high frequency modes 24/
LFXT1 oscillator crystal frequency, fLFXT1,HF0 XTS = 1, LFXT1Sx = 0
HF mode 0
LFXT1 oscillator crystal frequency, fLFXT1,HF1 XTS = 1, LFXT1Sx = 1
HF mode 1
LFXT1 oscillator crystal frequency, fLFXT1,HF2 XTS = 1, LFXT1Sx = 2
HF mode 2

Oscillation allowance for HF
crystals See figure 11

kHz

22

TA = 125°C
VLO frequency temperature drift

Unit

2.2 V/3 V

2.2 V/3 V

40

60

40

60

30

300

CAGE CODE
16236

DWG NO.
V62/09601

REV A

PAGE 14

pF%

kHz

TABLE I. Electrical performance characteristics – Continued. 1/
Test

Crystal Oscillator, XT2 24/
XT2 oscillator crystal frequency,mode 0XT2 oscillator crystal frequency,mode 1XT2 oscillator crystal frequency,mode 2XT2 oscillator logic level squarewave input frequency

Oscillation allowance
See figure 12

Integrated effective load
capacitance, HF mode 25/

Oscillator fault frequency, HF
mode 26/
Timer_A
Timer_A clock frequency

SymbolConditions-55°C ≤ TA ≤ 125°C 2/
unless otherwise specified

VCC

Unit

Min

Max

0.4

1

XT2S = 0

1.8 V to 3.6 V

fXT2

XT2S = 1

1.8 V to 3.6 V

1

4

fXT2

XT2S = 2

1.8 V to 3.6 V

210

2.2 V to 3.6 V

2

12

fXT2

OA

CL,eff

XT2S = 3

2

16

0.4

10

2.2 V to 3.6 V

0.4

12

3 V to 3.6 V

0.4

16

fTA,cap

TA0, TA1, TA2

fTB

Internal: SMCLK, ACLK,
External: TBCLK,
Duty cycle = 50% ±10%800 TYP
300 TYP
1 TYP
2.2 V/3 V

2.2 V/3 V
2.2 V

60

40

60

30

300

kHz

7.5

MHz

01

20
01

TB0, TB1, TB2

USCI (UART mode)
USCI input clock frequency

fUSCIInternal: SMCLK, ACLK, External:
TBCLK, Duty cycle = 50% ±10%

ns
7.5

3V

fTB,cap

DLA LAND AND MARITIMECOLUMBUS, OHIO

MHz

16

2.2 V/3 V

20
01

ns
fSYSTEM

2.2 V/3 V

MHz

1

2.2 V

50

600

3V

50

600

See footnotes at end of table.

SIZE
A

%

16

2.2 V/3 V
2.2 V

pF

40

3V

Timer_B, capture timing

tζ

MHz

2700 TYPInternal: SMCLK, ACLK,
External: TACLK, INCLK,
Duty cycle = 50% ±10%Timer_A, capture timing

fBITCLK

3 V to 3.6 V
1.8 V to 3.6 V

XT2S = 0, fXT2 = 1 MHz,CL,,eff = 15 pF
XT2S = 1, fXT2 = 4 MHz,CL,,eff = 15 pF
XT2S = 2, fXT1, HF = 16 MHz,CL,,eff = 15 pF
30/

Duty cycle Measured at P1.4/SMCLK,fXT2 = 10 MHz
Measured at P1.4/SMCLK,fXT2 = 16 MHz
fFaultXT2S = 3
27/
fTA

01

LimitsfXT2

Timer_B
Timer_B clock frequency

BITCLK clock frequency(equals baud rate in MBaud)UART receive deglitch time 28/

Devicetype

CAGE CODE
16236

DWG NO.
V62/09601

REV A

PAGE 15

ns

TABLE I. Electrical performance characteristics – Continued. 1/
Test

SymbolUSCI (SPI Master mode) See figure 13
USCI input clock frequency
SOMI input data setup time
SOMI input data hold time
SIMO output data valid

32/

tSU,MI

Conditions-55°C ≤ TA ≤ 125°C 2/
unless otherwise specified
SMCLK, ACLK,
Duty cycle = 50% ±10%

tHD,MItVALID,MOUCLK edge to SIMO valid,
CL = 20 pF

USCI (SPI Slave mode) See figure 14 32/
STE lead time, STE low to clocktSTE,LEAD
STE lag time, last clock to STE
high
STE access time, STE low to
SOMI data out
STE disable time, STE high to
SOMI high impedance
SIMO input data setup time
SIMO input data hold time
SOMI output data valid

VCC

Limits
Min

01

Unit
Max

fSYSTEM

2.2 V

110

3V

75

2.2 V

0

3V

0

2.2 V

30

3V

20

2.2 V/3 V

01

50 TYP

2.2 V/3 V

tSTE,ACC

2.2 V/3 V

50 TYPtSTE,DIS

2.2 V/3 V

50 TYPtSU,SI

2.2 V

20

3V

15

2.2 V

10

3V

10

tHD,SItVALID,SO

fUSCI

SCL clock frequency

fSCL

Hold time (repeated) START

tHD,STAUCLK edge to SOMI valid,
CL = 20 pF

Internal: SMCLK, ACLK,
External: UCLK,
Duty cycle = 50% ±10%
fSCL ≤ 100 kHz
fSCL ≤ 100 kHz

110

3V

75
01

fSYSTEM TYP

MHz

2.2 V/3 V

0µs

2.2 V/3 V

4.0

400

0.6
2.2 V/3 V

fSCL > 100 kHz

4.7
0.6

Data hold time

tHD,DAT

2.2 V/3 V

0

Data setup time

tSU,DAT

2.2 V/3 V

250

Setup time for STOP

tSU,STO

2.2 V/3 V

4.0

tSP

2.2 V

50

600

3V

50

600

Pulse width of spikes suppressedby input filternsµs

See footnotes at end of table.

DLA LAND AND MARITIMECOLUMBUS, OHIO

SIZE
A

ns

10

2.2 V

fSCL > 100 kHz
tSU,STAMHz
ns

tSTE,LAGUSCI (I2C mode) See figure 15
USCI clock frequency

Setup time for a repeated START

Devicetype

CAGE CODE
16236

DWG NO.
V62/09601

REV A

PAGE 16ns

TABLE I. Electrical performance characteristics – Continued. 1/
Test

Comparator_A+ 33/

SymbolI(DD)Conditions-55°C ≤ TA ≤ 125°C 2/
unless otherwise specified

VCC

CAON = 1, CARSEL = 0, CAREF = 0

2.2 V

I(Refladder/Refdiode) CAON = 1, CARSEL = 0, CAREF = 1/2/3,
no load at p2.3/CA0/TA1 and P2.4/CA1/TA2
Common mode input voltage

V(IC)Voltage @ 0.25VCC node
VCC

V(Ref025)

Voltage @ 0.5VCC node
VCC

V(Ref050)

See figure 17

V(RefVT)

Offset voltage

V(offset)

Input hysteresis

Vhys

Low to high and high to low
35/t(response)

IREF+

Input capacitance

CI 36/

Input MUX ON resistance

RI 36/

Limits
Min

01

Unit

Max
40

3V

60

2.2 V

50

3V

71

CAON = 1

2.2 V/3 V

VCC - 1

PCA0 = 1, CARSEL = 1, CAREF = 1,
no load at P2.3/CA0/TA1 andP2.4/CA1/TA2
PCA0 = 1, CARSEL = 1, CAREF = 2,
no load at P2.3/CA0/TA1 andP2.4/CA1/TA2
PCA0 = 1, CARSEL = 1, CAREF = 3,
no load at P2.3/CA0/TA1 andP2.4/CA1/TA2, TA = 85°C

2.2 V/3 V

0.23

0.25

2.2 V/3 V

0.47

0.50

2.2 V

390

540

3V

400

550

2.2 V/3 V-30

30

2.2 V/3 V

0

1.4

TA = 85°C, Overdriver 10 mV,
Without filter: CAF = 0

2.2 V

80

300

3V

70

270

TA = 85°C, Overdriver 10 mV,With filter: CAF = 1

2.2 V

1.4

2.8

3V

0.9

2.2

2.2

3.6

0

VAVCC

34/
CAON = 1

12 bit ADC, power supply and input range conditions
Analog supply voltage
AVCC
AVCC and DVCC are connected together
AVSS and DVSS are connected together
V(AVSS) = V(DVSS) = 0 V
Analog input voltage range
V(P6.x/Ax)
All P6.0/A0 to P6.7/A7 terminals. Analog
42/
inputs selected in ADC12MCTLx register,P6Sel.x =1, 0 ≤ x ≤ 7,
V(AVSS) ≤ VP6.x/Ax ≤ V(AVCC)
Operating supply current into
IADC12
fADC12CLK = 5 MHz, ADC12ON = 1,
AVCC terminal 43/
REFON = 0, SHT0 = 0, SHT1 = 0,
ADC12DIV - 0
Operating supply current into
AVCC terminal 43/

Devicetype

fADC12CLK = 5 MHz, ADC12ON = 0,
REFON = 1, REF2_5V = 1
fADC12CLK = 5 MHz, ADC12ON = 0,
REFON = 1, REF2_5V = 0
Only one terminal can be selected at one
time, P6.x/Ax
0 V ≤ VAx ≤ VAVCC

01

2.2 V

0.8

DLA LAND AND MARITIMECOLUMBUS, OHIO

µA

V

mV

ns

V

mA

3V

1

3V

0.7

2.2 V

0.7

3V

0.7

2.2 V

40

pF

3V

2000

Ω

See footnotes at end of table.

SIZE
A

µA

CAGE CODE
16236

DWG NO.
V62/09601

REV A

PAGE 17

TABLE I. Electrical performance characteristics – Continued. 1/
Test

Symbol12 bit ADC, built in reference
Positive built in reference
VREF+
voltage output

AVCC minimum voltage,
Positive built in reference
activeLoad current out of VREF+
terminal
Load current regulation
VREF+ terminal

Load current regulation
VREF+ terminal
Capacitance at pin VREF+
46/
Temperature coefficient ofbuilt in reference
Settle time of internalreference voltage
See figure 19 47/
See footnotes at end of table.

Conditions 2/
unless otherwise specified

TA

VCC

Unit

Min

Max

2.4

2.6

-55°C to 105°C

3V

125°C

3V

2.37

2.64

REF2_5V = 0 (1.5 V),
IVREF +max ≤ IVREF+ ≤ IVREF+min-55°C to 105°C 2.2 V/3 V

1.44

1.56

2.2 V/3 V

1.42

1.57

125°C

01

Limits

REF2_5V = 1 (2.5 V),
IVREF +max ≤ IVREF+ ≤ IVREF+min

AVCC(min) REF2_5V = 0,
IVREF +max ≤ IVREF+ ≤ IVREF+min

IVREF+

Device
type

2.2
2.8

REF2_5V = 1,
-0.5 mA ≤ IVREF+ ≤ IVREF+min
REF2_5V = 1 (2.5 V),-1 mA ≤ IVREF+ ≤ IVREF+min

2.9
2.2 V

0.01

3V

0.01

-0.5

IL(VREF)+ IVREF+ = 500 µA ±100 µA
45/
Analog input voltage -0.75 V;
REF2_5V = 0

±2

3V

±2

IVREF+ = 500 µA ±100 µA
Analog input voltage ~1.25 V;
REF2_5V = 1
IDL(VREF)+ IVREF+ = 500 µA → 900 µA
36/
CVREF+ = 5 µF; ax ~0.5 x VREF+
Error of conversion result ≤ 1 LSB
CVREF+ REFON = 1,
0 mA ≤ IVREF+ ≤ IVREF+mAX
TREF+ IVREF+ is a constant in the range of
45/
0 mA ≤ IVREF+ ≤ 1 mA
tREFON IVREF+ = 0.5 mA, CVREF+ = 10 µF,
45/
VREF+ = 1.5 V, VACC = 2.2 V

3V

±2

3V

20

DLA LAND AND MARITIMECOLUMBUS, OHIO

2.2 V/3 V
2.2 V/3 V

mA

-1

2.2 V

SIZE
A

V

5

LSB

ns

µF
±100 ppm/°C
17CAGE CODE
16236

DWG NO.
V62/09601

REV A

PAGE 18

ms

TABLE I. Electrical performance characteristics – Continued. 1/
Test

SymbolConditions-55°C ≤ TA ≤ 125°C 2/
unless otherwise specified

VCC

12 bit ADC, timing parameters
fADC12CLK For specified performance of ADC12 linearity
parameters
Internal ADC12 oscillator
fADC12osc ADC12DIV = 0, fADC12CLK = fADC12osc
Conversion time

Turn on setting time of the
ADC
Sampling timetCONVERT CVREF+ ≥ 5 µF, Internal oscillator,
fADC12osc = 3.7 MHz to 6.3 MHz
External fADC12CLK from ACLK, MCLK,or SMCLK: ADC12SSEL ≠ 0
tADC12ON 49/
48/
tSample RS = 400 Ω, RI = 1000 Ω, CI = 30 pF
ζ = (RS + RI) x CI 50/

12-bit ADC, linearity parameters
Integral linearity error
EI

1.4 V ≤ (VeREF+ - VREF-/VeREF-) min ≤ 1.6 V

Devicetype

Limits
Min

Max

0.45

6.3

MHz

2.2 V/3 V

3.7

6.3

MHz

2.2 V/3 V

2.06

3.51

µs

13 x ADC12DIV x
1/fADC12CLK
100

ns

3V

1220

ns

2.2 V

1400

2.2 V/3 V

2.2 V/3 V

01

01

±1.7

1.6 V < (VeREF+ - VREF-/VeREF-) min ≤ [VAVCC]
Differential linearity error

53/

±1
±4

±2
±5

2.2 V

01

120

3V
2.2 V

986 TYP

3V

986 TYP

TCSENSOR ADC12ON = 1, INCH = 0Ah

2.2 V
3V
2.2 V

30

3V

30

Current into divider atchannel 11 55/

IVMID

2.2 V

NA

3V

NA

AVCC divider at channel 11

VMID

ADC12ON = 1, INCH = 0Bh,
VMID is ~0.5 x VAVCC

2.2 V

1.1 ±0.04

Sample time required ifchannel 11 is selected 56/

tVMID

ADC12ON = 1, INCH = 0Bh,
Error of conversion result ≤ 1 LSB

2.2 V

1400

3V

1220

3V

µs

DLA LAND AND MARITIMECOLUMBUS, OHIO

µA

V

1.1 ±0.04

See footnotes at end of table.

SIZE
A

mV

3.55 ±3% mV/
3.55 ±3% °C

Sample time required if
tSENSOR ADC12ON = 1, INCH = 0Ah,
channel 10 is selected 54/ (sample) Error of conversion result ≤ 1 LSB(sample)µA

160

VSENSOR ADC12ON = 1, INCH = 0Ah,
51/
TA = 0°C

ADC12ON = 1, INCH = 0Bh

LSB

±1.7

ED

(VeREF+ - VREF-/VeREF-)min ≤ (VeREF+ - VREF-/VeREF-),
CVREF+ = 10 µF (tantalum) and 100 nF (ceramic)
Offset error
EO(VeREF+ - VREF-/VeREF-)min ≤ (VeREF+ - VREF-/VeREF-),
Internal impedance of source RS < 100 Ω,
CVREF+ = 10 µF (tantalum) and 100 nF (ceramic)
Gain error
EG(VeREF+ - VREF-/VeREF-)min ≤ (VeREF+ - VREF-/VeREF-),
CVREF+ = 10 µF (tantalum) and 100 nF (ceramic)
Total unadjusted error
ET(VeREF+ - VREF-/VeREF-)min ≤ (VeREF+ - VREF-/VeREF-),
CVREF+ = 10 µF (tantalum) and 100 nF (ceramic)
12 bit ADC, temperature sensor and built-in VMID
Operating supply current
ISENSOR REFON = 0, INCH = 0Ah,
into AVCC terminal 52/
ADC12ON = 1, TA = 25°C

Unit

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TABLE I. Electrical performance characteristics – Continued. 1/
Test

flash memory
Program and erase supply
voltage
Flash timing generator frequency

SymbolConditions 2/
unless otherwise specified

VCC

VCC(PGM/ERASE)

Device
type

01

fFTG

Limits

Unit

Min

Max

2.2

3.6

V

257

476

kHz

Supply current from DVCC during
program
Supply current from DVCC during
erase
Cumulative program time

IPGM

2.7 V/3.6 V

5mA

IERASE

2.7 V/3.6 V

7

mA

tCPT

57/

2.7 V/3.6 V

4ms

Cumulative mass erase timetCMErase58/

2.7 V/3.6 V

Program/Erase endurance

20

ms

104

cycles100

years

Data retention durationtRetention

TJ = 25°C

Word or byte program time

tWord

59/

Block program time for 1st byte ortBlock, 0

30 TYPtBlock, 1-63

21 TYP

35 TYP

word
Block program time for each
additional byte or word
Block program end-sequence wait
time
Mass erase time 60/

tBlock, End

6 TYP

tMass Erase10593 TYP

Segment erase time

tSeg Erase4819 TYP

RAM
61/

VRAMh

JTAG interface
TCK input frequency
Internal pullup resistance on
TMS, TCK, TDI/TCLKJTAG fuse 64/
Supply voltage during fuse-blow
condition
Voltage level on TDI/TCLK forfuse blow
Supply current into TDI/TCLK
during fuse blow
Time to blow fuse
1/

2/
3/
4/
5/
6/

CPU halted

01

1.6

01

0

5

V

fTCK

62/

2.2 V
3V

0

10

RInternal

63/

2.2 V/3 V

25

90

VCC(FB)TA = 25°C

01

VFB

2.5
6

tFTG

MHz
Ω
V

7

V

IFB

100

mA

tFB

1

ms

Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the
specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may notnecessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or
design.
Over recommended ranges of supply voltage and operating free air temperature (unless otherwise noted).
All inputs are tied to 0 V or VCC. Outputs do not source or sink any current.
The current are characterized with a micro crystal. See manufacture data for more information.
Current for brownout and WDT+ is included. The WDT+ is clocked by SMCLK.
Current for brownout and WDT+ is included. The WDT+ is clocked by ACLK.

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TABLE I. Electrical performance characteristics – Continued. 1/
7/
8/
9/

Current for brownout included.
XIN and XT2IN only bypass mode.
The external signal sets the interrupt flag every time the minimum t(int) parameters are met. It may be set even with trigger signals
shorter than t(int).
10/ The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
11/ The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor isdisabled.
12/ The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±12 mA to satisfy the maximum voltage
drop specified.
13/ The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±48 mA to satisfy the maximum voltage
drop specified.
14/ A resistive divider with 2 times 0.5 kΩ between VCC and VSS is used as load. The output is connected to the center tap of thedivider.
15/ The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
16/ The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level
V(B_IT-) + Vhys(B_IT-) is ≤ 1.8 V.
17/ During power up, the CPU begins code execution following a period of td(BOR) after VCC = V(B_IT-) + Vhys(B_IT-), The default DCO
settings must not be changed until VCC ≥ VCC(min), where VCC(min) is the minimum supply voltage for the desired operating frequency.
18/ The recommended operating voltage range is limited to 3.6 V.
19/ tsettle is the setting time that the comparator output must have a stable level after VLD is switched VLD ≠ 0 to a different VLD value
somewhere between 2 and 15. The overdrive is assumed to be > 50 mV.
20/ The current consumption of the SVS module is not included in the ICC current consumption data.
21/ The DCO clock wake up time is measured from the edge of an external wake up signal (e.g., port interrupt) to the first clock edge
observable externally on a clock pin (MCLK or SMCLK).
22/ Parameter applicable only if DCOCLK is used for MCLK.
23/ ROSC = 100kΩ. Metal film resistor, type 0257. 0.6 watt with 1% tolerance and TK = ±50ppm/°C.
24/ To improve EMI on the LFXT1 oscillator the following guidelines should be observed:
a. Keep the trace between the device and the crystal as short as possible.
b. Design a good ground plane around the oscillator pin.
c. Prevent crosstalk from other clock or data lines into oscillator pin XIN and XOUT.
d. Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
e. Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
f. If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between oscillator pins.
g. Do not rout the XOUT line to the JTAG header to support the serial programming adapter as shown in other data. This signal
is no longer required for the serial programming adapter.
25/ Includes parasitic bond and package capacitance (approximately 2 pF per pin). Since the PCB adds additional capacitance it isrecommended to verify the correct load by measuring the ACLK frequency. For a correct setup the effective load capacitanceshould always match the specification on the used crystal.
26/ Frequencies below the MIN specification set the fault flag, frequencies above the MAX specification do not set the fault flag.
Frequencies in between might set the flag.
27/ Measured with logic level input frequency, but also applies to operation with crystals.
28/ Calculated using the box method:
I Version: [MAX(-55 to 85°C) – MIN(-40 to 85°C)]/ MIN(-40 to 85°C)]/[85°C – (-40°C)]
T version: [MAX(-40 to 105°C) – MIN(-40 to 105°C)]/ MIN(-40 to 105°C)]/[105°C – (-40°C)]
29/ Calculated using the box method:[Max(1.8…3.6V) – MIN(1.8…3.6 V)]/MIN(1.8…3.6 V)/(3.6 V – 1.8 V)
30/ Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
31/ Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that thepulses correctly recognized, their width should exceed the maximum specification of the deglitch time.
32/ fUCxCLK =1with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(Master) + tVALID,SO(USCI)).
2tLO/HIFor the master’s parameter tSU,MI(Master) and tVALID,MO(Master) refer to manufacturer data sheet.

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33/ The leakage current for the Comparator_A terminals is identical to Ilkg(Px.x) specification.
34/ The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A inputs on successive measurements.
The two successive measurements are then summed together.
35/ The response time is measured at P2.2/CAOUT/TA0/CA4 with an input voltage step, with Comparator_A+ already enabled(CAON = 1). If CAON is set at the same time, a setting time of up to 300 ns is added to the response time.
36/ Not production tested, limits verified by design.
37/ The leakage current is defined in the leakage current table with Px.x/Ax parameter.
38/ The analog input voltage range must be within the selected reference voltage range VR+ to VR- for valid conversion result.
39/ The internal reference supply current is not included in current consumption parameter IADC12.
40/ The internal reference current is supplied via terminal AVCC. Consumption is independent of the ADC12ON control bit, unless aconversion is active. The REFON bit enables the built in reference to settle before starting an A/D conversion.
41/ The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, CI, is also
the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow therecommendations on analog source impedance to allow the change to settle for 12 bit accuracy.
42/ The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
43/ The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with
reduced accuracy requirements.
44/ The accuracy limits the minimum external differential reference voltage. Lower differential reference voltage levels may be appliedwith reduced accuracy requirements.
45/ Not production tested, limits characterized.
46/ The internal buffer operational amplifier and the accuracy specifications require an external capacitor. All INL and DNL tests uses
two capacitors between pins VREF+ and AVSS and VREF-/VeREF- and AVSS:10 µF tantalum and 100 nF ceramic.
47/ The condition is that the error in a conversion started after tREFON is less than ±0.5 LSDB. The setting time depends on the external
capacitive load.
48/ Limits verified by design.
49/ The condition is that the error in a conversion started after tADC12ON is less than ±0.5 LSB. The reference and input signal are
already settled.
50/ Approximately ten Tau (𝜏𝜏) are needed to get an error of less than ±0.5 LSB:
tSample = In(2n+1) x (Rs + Ri) x Ci + 800 ns where n = ADC resolution = 12, RS = external source resistance.
51/ Limits characterized.
52/ The sensor current ISENSOR is consumed if (ADC12ON = 1 and REFON = 1) or (ADC12ON =1 and INCH = 0Ah and sample signal
is high). When REFON = 1, ISENSOR is included in IREF+.
53/ The temperature sensor offset can be as much as ±20°C. A single point calibration is recommended in order to minimize the offset
error of the built-in temperature sensor.
54/ The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor on time tSENSOR(on).
55/ No additional current is needed. The VMID is used during sample.
56/ The on time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.
57/ The cumulative program time must not be exceeded when writing to a 64 byte flash block. This parameter applies to all
programming methods: individual word/byte write and block write modes.
58/ The mass erase duration generated by the flash timing generator is at least 11.1 ms (= 5297 x 1/fFTG, max = 5297 x 1/476kHz). To
achieve the required cumulative mass erase time the Flash Controller’s mass erase can be repeated until this time is met. (A worst
case minimum of 19 cycles are required).
59/ These values are hardwired into the Flash Controller’s state machine (tFTG = 1/fFTG).
60/ To erase the complete code area the mass erase has to be performed once with a dummy address in the range of the lower 64kB.
Flash addresses and once with the dummy address in the upper 64kB Flash addresses.
61/ This parameter defines the minimum supply voltage when the data in program memory RAM remains unchanged. No program
execution should take place during this supply voltage condition.
62/ fTCK may be restricted to meet the timing requirements of the module selected.
63/ TMS, TDI/TCLK, and TCK pullup resistor are implemented in all versions.
64/ Once the fuse is blown, no further access to the JTAG/Test, Spy-Bi-Wire, and emulation feature is possible, and JTAG is switched
to bypass mode.

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Case X

Symbol
A
A1
A2
A3
b
C

Dimension
Min
Max
Symbol
1.60
D/E
1.35
1.45
D1/E1
0.25 TYP
D2/E2
0.05
e
0.17
0.27
L
0.13 NOM

Min
Max
11.80
12.20
9.80
10.20
7.50 TYP
0.50 BSC
0.45
0.75

NOTES:
1. All linear dimensions are in millimeters.
2. This drawing is subject to change without notice.
3. Falls within JEDEC MS-026.
4. May also be thermally enhanced plastic with leads connected to the die pads.
FIGURE 1. Case outline.

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PAGE 23Case outline X

Terminal
number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

Terminal symbol
DVCC
P6.3/A3
P6.4/A4
P6.5/A5
P6.6/A6
P6.7/A7/SVSINVREFXIN
XOUT
VeREF+
VREF-/VeREFP1.0/TACLK/CAOUT
P1.1/TA0
P1.2/TA1
P1.3/TA2
P1.4/SMCLK
P1.5/TA0
P1.6/TA1
P1.7/TA2
P2.0/ACLK/CA2
P2.1/TAINCLK/CA3
P2.2/CAOUT/TA0/CA4
P2.3/CA0/TA1
P2.4/CA1/TA2
P2.5/ROSC/CA5
P2.6/ADC12CLK/CA6
P2.7/TA0/CA7
P3.0/UCB0STE/UCA0CLK
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK/UCA0STE
P3.4/UCA0TXD/UCA0SIMO

Terminal
number
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64

Terminal symbol
P3.5/UCA0RXD/UCA0SOMI
P3.6/UCA1TXD/UCA1SIMO
P3.7/UCA1RXD/UCA1SOMI
P4.0/TB0
P4.1/TB1
P4.2/TB2
P4.3/TB3
P4.4/TB4
P4.5/TB5
P4.6/TB6
P4.7/TBCLK
P5.0/UCB1STE/UCA1CLK
P5.1/UCB1SIMO/UCB1SDA
P5.2/UCB1SOMI/UCB1SCL
P5.3/UCB1CLK/UCA1STE
P5.4/MCLK
P5.5/SMCLK
P5.6/ACLK
P5.7/TBOUTH/SVSOUT
XT2OUT
XT2IN
TDO/TDI
TDI/TCLKTMS
TCK
RST/NMI
P6.0/A0
P6.1/A1
P6.2/A2
AVSS
DVSS
AVCC

FIGURE 2. Terminal connections.

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FIGURE 3. Functional block diagram.

NOTE:
1. Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC of 2.2 V.
FIGURE 4. Operating area.

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FIGURE 5. Active mode supply current.

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FIGURE 6. POR/Brownout reset.

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FIGURE 7. POR/Brownout reset.

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FIGURE 8. POR/Brownout reset.

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FIGURE 9. Test circuit and timing waveforms.

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FIGURE 10. Test circuit and timing waveforms.

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PAGE 31FIGURE 11. Test circuit and timing waveforms.

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FIGURE 12. Test circuit and timing waveforms.

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FIGURE 13. Test circuit and timing waveforms.

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FIGURE 14. Test circuit and timing waveforms.

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FIGURE 15. Test circuit and timing waveforms.

FIGURE 16. Test circuit and timing waveforms.

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PAGE 36FIGURE 17. Test circuit and timing waveforms.

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FIGURE 18. Test circuit and timing waveforms.

FIGURE 19. Test circuit and timing waveforms.

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PAGE 38FIGURE 20. Test circuit and timing waveforms.

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4. VERIFICATION
4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicatedin their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification,
packaging, and labeling of moisture sensitive devices, as applicable.
5. PREPARATION FOR DELIVERY
5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial
practices for electrostatic discharge sensitive devices.
6. NOTES
6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum.
6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book.
The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided.
6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee ofpresent or continued availability as a source of supply for the item. DLA Land and Maritime maintains an online database of all current
sources of supply at https://landandmaritimeapps.dla.mil/programs/smcr/.

1/

Vendor item drawing
administrative control
number 1/

Devicemanufacturer
CAGE code

Vendor part number

V62/09601-01XE

01295

MSP430F249MPMEP

The vendor item drawing establishes an administrative control number for
identifying the item on the engineering documentation.

CAGE code

Source of supply

01295

Texas Instruments, Inc.
Semiconductor Group
8505 Forest lane
P.O. Box 660199
Dallas, TX 75243

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