APPLICATION NOTE
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NCP4318 Tips and Tricks
AND90154/D
Drain Voltage of SR MOSFETs

LLC converter is a popular isolated dc−dc power
conversion topology for high power applications.
The primary−side winding of the transformer in LLC
converter sees an ac current of the resonant tank. In lower
output voltage scenarios, center−tapped windings are used
for the secondary side of the transformer. Two diodes areused to rectify the output current of the secondary windings.
To improve conversion efficiency of the LLC converter,
people use a synchronous rectification (SR) technique on
the output rectifying diodes. Synchronous rectificationmeans using power transistors to replace the diodes. Within
the diode conduction time duration, turn on the powertransistor to replace the diode’s conduction role. It takes theadvantage of the on−resistance voltage drop of the powertransistor being lower than forward voltage dropof the diodes, thanks to the low on−resistance RDS(ON)of modern power transistors, such as power MOSFETs.
NCP4318 is a synchronous rectification controller
dedicated for LLC converters. Figure 1 shows a typicalapplication circuit of NCP4318. It senses the voltage acrossdrain and source pins of the SR MOSFETs through two setsof VD and VS pins. An ROFFSET is placed in series of each
VD and drain pin connection. NCP4318 has two VG pins todrive the respective SR MOSFET when its body diode canbe forward biased. VDD of NCP4318 can be supplied byvoltage not higher than 37 V, so the output voltageof the LLC converter can be directly used as NCP4318’s
power supply. Thus, NCP4318 can control the SR
MOSFETs with very low external part counts.
NCP4318 datasheet [1] had introduced basic operation
principle of this controller. This application note provides
further explanation for its practical operation in different
scenarios.

Figure 2 shows an example of the secondary−side currents
and voltage waveform of SR MOSFETs. When the current
in the Lr and Lm of the primary side of the LLC converter
diverts from each other, the difference between them
becomes the current transferred to the secondary side.
Whatever MOSFET or the body diode conducts
the secondary−side current, Figure 2 notes the current as
ISD, as the current is flowing from source to drain terminalof the SR MOSFET. When the current flows through M1,
VDS of M1 pulls low. If M2 conducts the secondary−sidecurrent, VDS of M1 shows VOUT plus reflected voltage fromthe transformer winding, which makes the voltage
amplitude roughly two times of VOUT.
In a below−resonant operation of the LLC converter, there
is a duration that no current is transferred from the primary
to the secondary side. The capacitor across the drain
and source terminals of the two SR MOSFETs resonateswith the equivalent Lr reflected to the secondary side,making a sub−resonance as in Figure 2.
Zooming in the VDS and ISD waveform when the ISD
current conducts, we get a waveform as shown in Figure 3.
The body diode of the SR MOSFET conducts first and then
NCP4318 generates gate signal, VG, making the SR
MOSFET turned on. The amplitude of VDS change fromthe forward voltage of the body diode to the voltage drop
across the MOSFET’s on−resistance. Thus, the conduction
loss of the secondary−side current on the rectifying device,
which means diodes, can be reduced. The gate signal will beturned off before the ISD current drop to zero. The timeinterval between gate turning off and current dropping
to zero is the dead time of the SR gate signal.

Figure 1. Typical Application Circuit of NCP4318© Semiconductor Components Industries, LLC, 2022

November, 2023 − Rev. 3

1

Publication Order Number:AND90154/D

AND90154/D
VDS.M 1stray inductance can still be found in the short PCB trace andthe MOSFET package. The stray inductance generates a
voltage difference VLS when amplitude of theflowing−through current changes. The sensed VDS becomesa summation of VLS and –ISD ⋅ RDS(ON). When ISD drops,
VLS becomes positive, which raises VDS voltage and makes
the SR controller turn off the SR MOSFET prematurely, as
shown in Figure 4 (b).
To overcome the premature turn−off phenomenon,
NCP4318 has a range of adjustable VTH−OFF levels and it
can adjust the VTH−OFF by optimizing its turning−off instantand adjusts the VTH−OFF to regulate the dead time. For
avoiding overreaction of the VTH−OFF adjustment, theoptimized dead time is defined as a hysteresis band.
NCP4318 adjusts VTH−OFF higher for the dead time being
longer than tDEAD−HBAND and lower for the dead time being
shorter than tDEAD−LBAND . More, the VTH−OFF is adjustedwith high resolution by the combination of VTH−OFF andIOFFSET. These are depicted in Figures 6 and 7.
The IOFFSET and ROFFSET changes the VDS detected in the
VD and VS pins, making the turn−off criterion become

Sub−resonance~2*VOUTISD.M1

ISD.M2

Ilr, ILm
ILm

Ilr

Figure 2. Typical SR Current and Voltage Waveformsof a Below−resonant LLC Converter
VDS.M1
Voltage drop of on−resistance

V DS ) I OFFSET @ R OFFSET * V TH*OFF + 0.

Body diode’s forward voltage(eq. 1)

So, we can define a virtual VTH−OFF as a combination of
VTH−OFF and IOFFSET’s effects as

VG1
ISD.M1

Virtual V TH*OFF + V TH*OFF * R OFFSET @ I OFFSET.
(eq. 2)tWith both VTH−OFF and IOFFSET as variables, VTH−OFF isdefined as larger step and IOFFSET is defines as smaller stepof the adjustment of the virtual VTH−OFF. Both of them arecontrolled by 5−bit digital numbers, so there are totally 1024
variations of the combination. Stepping down of the virtual
VTH−OFF can happen in every switching cycle for a fast
response. However, stepping up of the virtual VTH−OFF
needs 128 consecutive switching cycles having tDEAD >tDEAD−HBAND. This is for avoiding too fast dead time
reduction that may interfere the feedback loop of LLC
control.
IOFFSET varies between 0 and 310 mA, and NCP4318 has
two different step size for VTH−OFF. To make the
IOFFSET⋅ROFFSET fill the step size of VTH−OFF, the
value
is
30 W
for
recommended
ROFFSET
VTH−OFF−STEP = 8 mV and 15 W for VTH−OFF−STEP = 4 mV.
More, except the VTH−OFF−STEP options, NCP4318 also has
two different options for VTH−OFF−MIN . VTH−OFF−MIN and
VTH−OFF−STEP defines the variable range of VTH−OFF.
Larger VTH−OFF−STEP leads to higher VTH−OFF−MAX .

Figure 3. Zoomed−in Waveform of SR Current andVoltage
Dead Time Regulation and VTH−OFF Range

Figure 4 (a) shows an ideal operating scenario of the SR
MOSFET in LLC converters. When the body diode of the
SR MOSFET conducts, voltage across its drain and source
terminals, VDS, goes negative. Its amplitude is the forward
voltage of the body diode. NCP4318 senses the VDS to turnon the SR MOSFET when the measured VDS is lower thana turn−on threshold voltage noted as VTH−ON in the figure.
Since turned on the SR MOSFET, VDS shows the voltage
drop on the RDS−ON. As the source−to−drain current ISD
drops, VDS rise to a value close to 0 mV, and NCP4318 turns
off the SR MOSFET based on a turn−off threshold voltage
VTH−OFF. Then, ISD conducts via body diode for theremaining duration of non−zero ISD.
In practical scenarios, there are parasitic inductanceeverywhere in the current conducting path. Even if two
separate pins are used to sense the differential voltage VDS,

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ROFFSET VDVDSVSIOFFSET

Turn−off

VTH−OFF
COM2

Figure 7. IOFFSET and the Virtual VTH−OFFa) Without Stray InductanceV TH*OFF*MAX + V TH*OFF*MIN ) 31 @ V TH*OFF*STEP(eq. 3)

Wider range of VTH−OFF may be required when the strayinductance of the SR MOSFET is higher, such as with
TO−220 package, or the LLC is operating in below−resonant
region mostly. When the LLC converter operates in
below−resonant region, as in Figure 8 (a) and (b), variationin current slope tends to be larger. Thus, the effect of strayinductance on VDS becomes stronger. If the variable rangeof VTH−OFF is not large enough, the dead time will be larger
in heavy load condition. It is due to saturation of theadjustable VTH−OFF range; the required VTH−OFF for thewanted dead time is higher than VTH−OFF−MAX. So, when
the dead time is well regulated in light−load conditions andbecomes too large in heavy−load conditions, look for
VTH−OFF−STEP = 8 mV IC option, which provides higher
VTH−OFF−MAX.

a) With Stray Inductance

Figure 4. Effect of Stray Inductance on VDS

Inspecting VD Waveform on Oscilloscope

The operation of NCP4318 is based on detecting thevoltage across drain and source terminals of SR MOSFETs
to decide whether the VG signal should be high or low. For
an LLC converter with 19.5 V of output voltage, typical VD
waveform is like Figure 9 (a) and has an amplitude of around
40 V, but the portion of interest for VD waveform during the
SR operation is in the range of −1~1 V.

Figure 5. Stray Inductance of the MOSFET Package

Figure 6. Hysteresis Band of Dead Time Regulation
by Adjusting the Virtual VTH−OFF

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a) Below Resonant,Heavy Load

Overall, the waveform captured by differential probes
shows a much correct wave shape, but the oscilloscope may
introduce some voltage offset at different voltage scaleaccording to the oscilloscope’s characteristics. Inspecting
the behavior of SR controller by capturing VD signal has noproblem but capturing threshold voltage like VTH−OFF may
not be easy in an operating LLC converter.

b) Below Resonant,Light Load

Minimum On−Time and Multi−Step VTH−OFFc) Above Resonant,Heavy Load

When SR gate is turning on, VDS may show ringing due
to parasitic components. NCP4318 has a minimum on−time(tON−MIN ) to avoid premature gate turning off by theparasitic ringing.
In a load−transient condition under above−resonant
operation, the SR conduction time may reduce a lot inconsecutive cycles. NCP4318 has a multi−step VTH−OFF todeal with sudden reduction on the SR conduction time. The
multi−step VTH−OFF means to have lowered VTH−OFF in atime duration defined as K2ND−TOFF.

d) Above Resonant,Light Load

Figure 8. SR Current Waveform in Different
Operating Region of LLC Converter(Ch1: VG1 2 V/div, Ch2: VG2 2 V/div, Ch3: VD1
200 mV/div, Ch4: ISD1 2 A/div)a) Typical VD Waveformb) VD in 2 V/div

Figure 10. tON−MIN Prevents Premature
Turning−Off by Ringing Noisec) VD in 1 V/divd) VD in 0.5 V/div

Figure 9. VD Waveforms Captured by an
Oscilloscope (Ch1: VG1 10 V/div, Ch2: VD1 by
Standard Probe, Ch3: VD1 by Differential Probe)

When you try to check VD waveform in the range ofinterest for NCP4318 by oscilloscope, some non−ideal
waveform may be captured due to oscilloscope’s
characteristics. In the Figure 9, channel #2 and #3 are
capturing the same VD signal with different probes.
Channel #2 is with standard 10x probe and channel #3 uses
a differential probe set at 1/20 of signal ratio. Comparing
Figure 9 (b) and (c) for the y−axis zoom−in of the VD signal
around 0 V, the shape of VD is slightly different between two
kinds of probes. Also, when the voltage scale changes, DC
offset of the signal may also change. In Figure 9 (d), thewaveform captured by the standard 10x probe is evendistorted in its wave shape.

Figure 11. Multistep VTH−OFF Turns Off SR GATE
Earlier when SR Conducting Duration Reduces

Both tON−MIN and K2ND−TOFF response to operating
information of its previous switching cycle, making them
adaptive to operating conditions. The tON−MIN refers to a
SRCOND signal, and K2ND−TOFF refers to gate on−time.
More, tON−MIN and K2ND−TOFF change according tooperating−mode flags DLY_EN and LLD respectively.
Definition and variation of SRCOND, tON−MIN, andK2ND−TOFF under different operating modes of NCP4318
are depicted in Figure 12.

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Figure 13. Leading−edge Inversion Current

When the leading−edge inversion current happens, thecurrent inversion detection function SRCINV will be
triggered once. Then, turning−on criterion of VG1 and VG2
become requiring VD1 and VD2 to be lower than VTH−ON
continuously for a tON−DLY2 duration. To avoid conducting
inversion current, the tON−DLY2 needs to be longer than the
discharging time of the capacitive current and period of thefollowing sub−resonance.
NCP4318 offers various tON−DLY2 options from 240 ns to1580 ns. For an LLC converter operating in above−resonant
region, tON−DLY2 doesn’t need to be too long. It may stillwork in below−resonant region during its input bulk voltage
hold−up time during power−off, which is usually aheavy−load condition. However, when an LLC converter
can operate in below−resonant region with light loadcondition, longer tON−DLY2 may be required for avoiding theleading−edge inversion current.

a) DLY_EN = 0, LLD = 0b) DLY_EN = 1, LLD = 0c) DLY_EN = 0, LLD = 1 or 2

Figure 14. tON−DLY Changing InstantFigure 12. tON−MIN and K2ND−TOFF in Different Modes
Leading−Edge Inversion Current and tON−DLY2

For an LLC converter operating in below−resonant region
and light−load condition, current may conduct two times in
one switching cycle for a rectifier branch. This phenomenon
had been explained in [2] as capacitive current. The main
reason is that the amplitude of the Cr voltage is not enough,so the Lr current doesn’t built up at the beginning of the
primary−sideontime.
However,theCOSScharging/discharging during the switching transition makethe SR MOSFET’s body diode conducts for a short period.
If SR MOSFET turns on in the short period, it results inleading−edge inversion current in the SR MOSFET
conducting duration, which makes additional conduction
loss.

Figure 15. tON−DLY2 Avoids Inversion Current

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5AND90154/D
SRCINV makes turning−on delay time as the longer
tON−DLY2 , instead of a short tON−DLY. To recover back to theshort tON−DLY, NCP4318 inspects VD waveform before SR
gate turning on. If VD crosses below VTH−ON for only one
time, a hINV−EXT counter adds by one. This counter resets
when the VD < VTH−ON event happens more than one timein one switching cycle. When the hINV−EXT counter has
reached 16000, the criterion of turning on the SR gain
recovers back to tON−DLY, which is simply a propagation
delay. It can also be witnessed in Figure 16 that therecovering from tON−DLY2 of one channel is independent
from the other channel.

VDD = VOUTVDD−GATE−ONt

VD1, 2t
256 cycles

VG1, 27Vta) VDD Connects to VOUTVDD−GATE−ON

VDD

VOUT
t
VD1, 2t

256 cycles
VG1, 2

10 V

7V

t

Figure 16. Recovering from the Long tON−DLY2b) VDD Connects to an Auxiliary Power Source

Figure 17. Soft Start

Soft Start and VDD Connection

Although the steady−state operation of an LLC converter
is pulse−frequency modulation (PFM) with designed
frequency range, different LLC controllers may havedifferent process of initiating its switching operating after
power on. After VDD exceeds VDD−GATE−ON, NCP4318
counts switching cycle of the LLC converter and skips the
SR gate output for the first 256 cycles to avoid any
unpredicted behavior from the LLC controller. VDD of
NCP4318 can be connected to VOUT or an auxiliary powersource. With different connection, the SR gate starts at
different moment when the LLC converter start its switching
operation.

IOFFSET

[31]
[0]

VTH−
OFF

LLD
VG1, 2

[3]

[2]

[4]

[2]

[6]

[5]

[1]
6V

[7]

[8]

[9]

[0]
10 V

24576 cycles

Figure 18. IOFFSET, VTH−OFF, LLD, and VGATE when the
Virtual VTH−OFF Keeps Increasingwww.onsemi.com
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AND90154/D
When NCP4318 starts to deliver SR gate signals duringsoft start, amplitude of VG1 and VG2 starts with 7 V. If theadaptive gate voltage control is not enabled, VG1 and VG2changes its amplitude to 10 V after another 256 switchingcycles. However, when the adaptive gate voltage control isenabled, amplitude of VG1 and VG2 will be decided by the
LLD status. Take NCP4318ALC as an example. Its
VTH−OFF−MIN , VTH−OFF−STEP, and VTH−OFF−RST are −6, 4,
and 2 mV, which means, at powering on, its VTH−OFF resetto the 2nd step (( 2 mV − ( −6 mV )) / 4 mV = 2nd step ), in
which the 32 steps of VTH−OFF are noted as 0~31st steps.
VGATE amplitude changes to 10 V when the VTH−OFF ishigher than the 7th step. Each VTH−OFF step includes 32 stepsof IOFFSET change, and it takes 128 switching cycles for thevirtual VTH−OFF to increase by one step of IOFFSET change.
Assuming the virtual VTH−OFF keeps increasing during theprocess, it will take roughly (7 − 2 + 1) ⋅ 32 ⋅ 128 = 24576
switching cycles to make VTH−OFF rise to the level thatmakes VGATE change to 10 V. Overall, when the adaptivegate voltage control is enabled, the number of 7 V gate
pulses during soft start is much larger than 256.
Similar to the soft start, with different VDD connection,
SR gate signal stops at different moment when VOUT drops
during power off. In case VDD is supplied from VOUT, VG1and VG2 stops when VOUT drops below VDD−GATE−OFF,even if the primary side LLC controller still delivers gate
pulses to the LLC converter.

Primary−side
Gate signals

ML MU

ML

ILr
Resonant−
tank current

Rectifiercurrents

ML MU

ML

t

dormantt

ILm
ISD1 ISD2ta) Example #1

Primary−side
Gate signals
Resonant−
tank current

Rectifiercurrents

ML MU MLILr

ML MU ML

dormant

t

ILm
ISD2

t

ISD2

b) Example #2

t

Figure 19. Examples of Light−load Mode Current
Waveforms

Working with LLC Controllers with a Light−load Mode

Instead of operating the LLC converter withpulse−frequency modulation (PFM) with 50% of duty cycle,
some LLC controller provides special primary−side gate
drive pattern to improve light−load efficiency. Let’s call it alight−load mode here. The idea is to make the LLC converterdelivers similar amplitude of current to the secondary sidewith similar primary−side pulse on−time, while modulatinga dormant duration to adjust average delivered power.
In this mode of operation, the rectifier currents don’t growin every primary−side gate pulse. Whether the rectifier
currents grow or not depends on the design of the
primary−side pulse packet. For example, in Figure 19, you
see ML−MU−ML primary−side pulse packets. Figure 19 (b)shows shorter on−time in the last ML of the packet. It results
in no energy delivering during the MU pulse duration due tothe resulting Cr voltage in that duration.
Whatever the light−load−mode packet is, while therectifier currents grow, we want the respective SR gate toturn on, like what we can see in Figure 20. To better copewith the light−load mode operation, you can selectNCP4318 with its parameters adjusted as described below.

a) Primary−side Pulse vs. VD of SRb) Respective SR Gate Pulse

Figure 20. Waveform of NCP4318 Working with
Light−Load Modewww.onsemi.com
7AND90154/D
Shorter tON−DLY2
NCP4318 utilizes tON−DLY2 to deal with the leading−edgeinversion current happening in light−load conditions. Whenthe LLC converter operates in the light−load mode, theleading−edge inversion current may not happen. In addition,
the modulated dormant period, which had been indicated in
Figure 19, can be longer than tGRN2−ENT, making tON−DLY2
be activated. Thus, to work with LLC controllers with suchkind of light−load mode, the tON−DLY2 parameter should beshorter, such as 240 ns in NCP4318AHD.
However, sometimes the leading−edge inversion current
may still happen in light−load mode. The primary shutdown
may be triggered in this condition, as shown in Figure 21. In
this situation, slightly longer tON−DLY2 to cover thecapacitive current spike can help the SR operate muchstably.

VDtAfter GREEN2, SRCINV,
or reset to initial conditon.
VGt

Maximumon−time+550 ns

1.2 ms+550 nsa) tGATE−LIM Function
VDt
Deficient of SR gateon−time due to thetGATE−LIM function

VG

Maximumon−time+550 ns at mosttDead−time
regulationb) tGATE−LIM under a Short−long−short
Conduction PatternFigure 22. tGATE−LIM Function

Reduce tOFF−MIN
NCP4318 has a tOFF−MIN function which avoids SR gate
to be turned on by the noise generated around its turn−offtransition. SR gate is prohibited to be turned on again after
turning off within a tOFF−MIN time window. In the light−loadmode operation, if the dormant duration, as in Figure 19, isvery short, the SR gate may need to be turned on again after
it has just been turned off before the short dormant duration.
In this condition, we want the tOFF−MIN parameter of
NCP4318 to be shorter.

Figure 21. A Light−load Mode with Leading−edge
Inversion Current Makes Primary ShutdownProtection Triggered

Disable tGATE−LIM
The SR conduction duration of the light−load mode mayvary a lot in consecutive switching cycles. NCP4318 has an
optional tGATE−LIM function that makes the SR gate on−timeincrease gradually, as shown in Figure 22 (a). When the SR
operation is reset by power−on, SRCINV, or otherprotections, the on−time of SR gate pulses starts from 1.2 ms.
The increment rate of the SR gate pulses from their previous
cycles is limited to 550 ns. Apparently, that function will
make the SR gate on−time always small when the SR
conduction duration shows a repetitive short−long−shortpattern, as shown in Figure 22 (b). In a light−load mode, theprimary−side gate pulses of the LLC converter tend to be notconsistent, so as the SR conduction duration. Thus, thetGATE−LIM function should be disabled to make the SR gateon−time follows the actual conduction duration detectedfrom VDS signal.

VD
t

VG

tOFF−
MIN

t

Figure 23. tOFF−MIN Function

NCP4318 has shorter tOFF−MIN option for both its
H−version and L−version. In addition, since tON−DLY2 itself
can be seen as a minimum off−time, NCP4318 also offers an
option to disable tOFF−MIN when tON−DLY2 has been
activated.

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Estimating Gate−drive Power Consumption

The operation of SR is to turn on the MOSFET when the
body diode is in conduction and turn off the MOSFET to let
the body diode takes over at the end of the conducting
duration. Load of the gate driver is CISS and CRSS of the
MOSFET at VDS ≈ 0V. The VDD pin’s sinking current, IDD,
can be estimated as below.
C TOTAL 5 S all_MOSFETsǒC ISSǒ V DS + 0 Ǔ ) C RSSǒ V DS + 0 ǓǓ
(eq. 4)I DD

VG_loaded+ I DD

VG_open) C TOTAL @ V GATE @ f SW
(eq. 5)Figure 24. Capacitance vs. VDS Drawing for
FDMS004N08C

For example, the MOSFET FDMS004N08C shows
CISS ≈ 3200 pF and CRSS ≈ 270 pF. When we put two
MOSFET in parallel for each VG channel and make the LLC
converter operate at 103 kHz at full load, the total average
current consumption of the gate drivers is(3200 pF + 270 pF) × 2 × 2 × 10.5 V × 103 kHz = 15 mA.
When VG pins are open, the measured IDD is as 3 mA. So,
the total IDD is 18 mA.

The total power consumption of NCP4318 is VDD*IDD,
but not all power needs to be eventually dissipated as heat on
NCP4318. The gate−drive portion of the power
consumption have some variation based on external
circuitry. For example, when there is a series resistor RG in
the turning−on current path, it slows down the turn−on slew
rate and makes the power dissipated on RDRV−SOURCE
becomes

E DRV*SOURCE + ǒV DD @ C TOTAL @ V GATE*MAX * 0.5 @ C TOTAL @ V GATE*MAX Ǔ @2(eq. 6)

VDD

which implied that part of power dissipation will be directedfrom RDRV−SOURCE to the external RG. Also, the totalenergy that needs to be dissipated during gate turning off is
0.5 × CTOTAL × VGATE−MAX2. The turn−off energy can bedirected to an external PNP bipolar transistor when it is usedin the turn−off circuit. However, with the simplest
connection in Figure 1, which connects VG pins to
MOSFET’s gate terminal without any additional elements,
the gate drive power dissipation will be all on the NCP4318
chip.
P DRV + V DD @ C TOTAL @ V GATE*MAX @ f SW

R DRV*SOURCER DRV*SOURCE ) R G

RDRV−SOURCEVG

VGATE−MAX

RG
ISOURCEa) Gate Current Sourcing(eq. 7)

VDD

VG
Isink

b) Gate Current Sinking

Figure 25. Gate Current Sourcing and Sinking
Situation with Additional Elements

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PCB Layout Recommendation

between VS pin and source pin of MOSFET. If there isadditional connection between the GND pin and the output
ground, the impedance is denoted as Z3. Assume Z1<<Z2
and Z1<<Z3, for Z1 being in the main current trace. The
voltage difference VS0 between IC’s VS pin and MOSFET’ssource pin can be derived as I sec @ Z 1ń2 for Figure 27 (a) andI sec @ Z 1 @ (Z 2 ) Z 3)ń(Z 2 ) 2Z 3) for Figure 27 (b). The
voltage difference VS0 in Figure 27 (a) is smaller between
the two.

To explain the recommended PCB layout, let us look at theexample of an SR daughter card with NCP4318A as its SR
controller in Figure 26.
VD1 and VD2 pins for drain sensing are connected todrain pads at terminals that the flowing current, indicated asarrows, begins. It is not at any middle way of any possible
current path. This connection avoids the noise generated by
the changing current and the stray inductance on the PCB
trace.
VS1 and VS2 pins are connected to SR MOSFET’s source
terminals and GND pin separately, forming a Y connection.
GND pin also connect to a VDD capacitor.
Gate drive current goes from VG1 and VG2 to therespective source terminal of the MOSFET and returns to
GND through the VS1 and VS2 connections. Keeping theloop area of VG and VS connections small avoids the gate
drive current loop to interfere other parts of the circuit.
For a higher wattage application, gate charge for
MOSFETs in each switching cycle can be higher. Using
external PNP transistors Q1 and Q2 to help the turning−off
process can be considered. The PNP transistors reduces
turning−off current−loop area and alleviate the power
consumption on the SR controller during the turning−off
process.

Isec

Z1

Z2

Z2
VS0

Z1

a) IC round doesn’t connect to output ground

Isec

Z1

Z2
VS0

Z2
Z3

Z1

b) IC ground connects to output groundFigure 27. Ground Connection and Current Flow
Enhancing Heat−Dissipation Capability of SOIC−8 EP
Packagea) Printed Circuit Board

When NCP4318 needs to drive more paralleled SR
MOSFETs in higher−output−current designs, power
consumption on the gate driver of NCP4318 gets higher.
Higher power consumption leads to higher junction
temperature on the chip. NCP4318 has an SOIC−8 EP
package variant in its lineup. This type of package provides
exposed pad for direct thermal attachment, which makes
lower the thermal impedance to the chip. To make good useof the package’s characteristic, here we provide additional
reminder on the PCB layout design.
The exposed pad can be connected to NCP4318’s GND
pin. When a PCB design still has some room to extend thecopper area for GND, one way to enhance the thermal
dissipation is to connect the GND copper area to the exposed
pad of the package. This way, the copper area is utilized asheat−sinking copper. Make sure that the exposed padconnects exactly to the copper area. More, note that the GND
copper area is signal ground for NCP4318, not power
ground for the output of the LLC converter.

b) Schematic

Figure 26. NCP4318A SR Daughter Card

The GND pin of NCP4318 is connected to LLC
converter’s output ground terminal through the VS
connections. It doesn’t need to connect to output groundwith other additional connection. Figure 27 shows theconnection methods of VS pins, GND pin, and the output
ground of the LLC converter. It is assumed that the layout isperfectly symmetrical. Z1 is the impedance between source
pin of MOSFET and the output ground. Z2 is the impedance

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mis−trigger abnormal−VD protection, or at least interfere
the dead−time judgement. In such a situation, adding VD pin
capacitors may help to filter the spike. Or there are alsoorderable part numbers of NCP4318 that has a higher
VTH−HGH of 1.5 V, which can be an alternative solution tothis situation.

If the PCB design is of multi−layer, you may consider
drawing the ground copper area in the other layer of the same
position as the IC and connecting the exposed pad to theground copper area through thermal vias. The thermal vias
can be spaced by 1 mm and have diameter of 0.3 mm.
Figure 28 provides a design example.

VD

Isec
VD
VDS

VTH−HIGH

IG
VS0

VGATE

Figure 29. Effect of Gate Turn−off Current on VDSa) Top side

Misfiring on the SR Gate while the LLC Controller Shuts
Down
Another example that adding a capacitor between VD and
GND may help happens at shutting down of the LLC
controller. When the primary side LLC controller shuts
down its operation, the resonant tank stops delivering energy
to the secondary side. The remaining energy in Lm and COSSof the primary−side power switches makes a resonance. The
voltage across Lm reflects to the secondary side, making aslower ringing on VDS of the SR MOSFETs. At the sametime, the remaining energy in COSS of SR MOSFETs andleakage inductance on the secondary side makes anadditional resonance at a much higher frequency. Waveformof the two resonances is shown in Figure 30.

b) Bottom side

Figure 28. A PCB Layout with Thermal Vias for
Package with Exposed Pad
Situations That May Require Filtering Capacitorson the VD Pins

The application schematic of Figure 1 mentioned that acapacitor may be added between VD and GND pins. The
added capacitor on VD pin forms a low−pass filter withROFFSET on the VD signal. Since the low−pass filter willlead to delay on the VD signal, time constant of the low−passfilter had better not to be larger than a number around 30 ns
for a proper SR operation. So, use capacitor not greater than
2.2 nF for 15 W of ROFFSET, and not greater than 1 nF for
30 W of ROFFSET. Too large of a time constant delays VD
signal too much, making the judged dead time being
effectively subtracted by the time constant, which in turnmay make the gate be turned off too late. The capacitor is not
required in general cases for NCP4318 to operate normally.
However, there are some cases that adding capacitors on VD
pins may help.

Figure 30. Added−up Resonances on VDS at LLC
Controller Shutting Down

When the two resonances are added up, VDS on the SR
MOSFET may satisfy VTH−ON and NCP4318 generates gateturn−on signal, which results in an inversion current
conducted in the SR MOSFET. The SR inversion current
detection function or the primary shutdown protection canturn off the SR gate immediately; however, it is even better
if the VG signal isn’t turned on by the VDS ringing. In sucha case, adding a R−C snubber to the SR MOSFET or adding
a capacitor for the VD signal can absorb or filter out the VDS
ringing, avoiding the mis−triggered SR gate pulse. Note that

Gate Turn−off Noise
When the gate capacitance of the MOSFET is huge,
amplitude of the MOSFET turn−off current tends to behigher. The turn−off current of the gate driver can induce a
voltage spike on the parasitic inductor in the current path, as
described in Figure 29. If the spike is not higher than
VTH−HGH, it doesn’t cause problem. However, if the spikemakes VD exceeds VTH−HGH (0.85 V in typical), it may

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AND90154/D
the ROFFSET and VD pin capacitor equivalently form an
R−C snubber to the SR MOSFET.

SR Gate turns off by not−capturable noise
It had been observed that SR gate may sometimes beturned off while no clue can be found on its respective VD
signal. Possible reasons may include radiated noise on theboard or noise that is beyond resolution of oscilloscope.
In Figure 32 (a), when the VG2 turned off, VD2 didn’t show
a waveform that satisfied VTH−OFF or SRCINV. Although
the oscilloscope didn’t capture the problem, it was foundthat the problem can be solved by adding a capacitor on the
VD2 pin. If that happens in your design too, adding capacitor
on VD pins can be worth trying.

Mis−triggering of SR Gate During LLC Hold−up TimeYet another example that adding VD pin capacitors mayhelp happens during hold−up time. The LLC converter tends
to operate in below−resonant region during the hold−up
time, so sub−resonance can be seen in each switching cycle.
In addition, since the load during hold−up time is usually
heavy, turning−on delay of NCP4318 tends to be the shortertON−DLY, which means the SR gate turns on immediately
when VD < VTH−ON. Furthermore, the VCr amplitude tends
to be high during the hold−up time.
In some design examples, the amplitude of VCr may be
increased larger than VIN. Thus, when the current in M1 cuts
off and VD shows sub−resonance, the amplitude of the
sub−resonance becomes larger than 2 x VO, as depicted in
Figure 31. It makes VD2 dips to a negative value, which may
satisfy the VTH−ON criterion and mis−triggers turning−on of
M2. Same phenomenon happens on M1 on the other halfcycle.
In this case, a snubber on SR MOSFETs damps the
sub−resonance and makes the amplitude of the
sub−resonance reduce faster. Thus, adding snubber, or using
VD pin capacitor to form an equivalent snubber withROFFSET, helps avoiding the mis−triggering of SR gate
signals.

VD1
1V/div
VD2
1V/div

VG1
10V/div
VG2
10V/div

VG2 turns
off, but noclue can befound in VD2.

a) Without VD pin capacitor

time 5μ s/div

VD1
1V/div
VD2
1V/div

VG1
10V/div
VG2 operates normally.
VG2
10V/divb) With VD pin capacitor

Figure 32. SR Gate is Turned off
by Not−capturable Noisea) An LLC Converter
Slope =
(VIN − VCr)/(Lm + Lr)
ILr
VIN

VCr

VIN/2

nVo

(VIN − VCr)Lm/(Lm + Lr)

VTx
2Vo
VD2

Vo

time 5μ s/div

Vo + VTx/nb) Sub−resonance that Causes Mis−trigger of SR Gate

Figure 31. Increased Sub−resonance Amplitude
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AND90154/D
When VTX shows fast transitions, a displacement current
will be induced on the Cinter. The induced current flows
through the secondary−side circuit and returns on theEMI−suppressing capacitor CY. The current flowing
through the secondary−side circuit excites parasitic
components to resonate, resulting in the noise shown in
Figure 33.
So, when a design has a non−integrated Lr, the Lr had
better be placed in the position 1, which induces less noiseon the secondary−side circuit.
If the noise is found to be not manageable in some rarecases, the NCP4318 functional option of disablingdead−time regulation may be considered. However, solving
the noise through circuit modification is encouraged.

Common−mode Noise Affects Dead Time Regulation in
Above−resonant Operation
In some LLC converter designs, due to parasitic
components, such as inter−winding capacitor in thetransformer or stray inductance on the secondary side, ahigh−frequency noise is induced while the primary−sideswitches do switching transition. When the LLC converter
operates in above−resonant region, the switching transition
happens before SR current commutating. If the magnitudeof the noise is considerable, such as in Figure 33, the induced
noise will hinder the dead−time regulation of NCP4318 tooperate properly. The dead time will not be able to stay in therange of tDEAD−LBAND ~ tDEAD−HBAND for the noise
triggering turning−off of the SR gate signal.
If the noise frequency is as high as tens of MHz, adding
filtering capacitor on VD pins to form a low−pass filter forthe noise can be helpful to get rid of the noise. Even if thenoise doesn’t get filtered out completely, lowering
magnitude on the noise may make the dead−time regulation
get back to proper operation.
When the dead time is found to be always longer thantDEAD−HBAND in all load conditions, please give this VDS
noise a check.

M2

Q1

Lr position 1−

Lr position 2
VTXG2

VD1 VS2

n:1

VS1 VD2LmCr

GND VDD

VO

G1

HB
Q2

NCP4318A

VIN

Cinter

CO

RO

+

LLC
Controller

CY

M1

Shunt
Regulator(a) An LLC Converter

Switching transitionin the primary side

V GS of Q1
t
VIN

V HB
t
Noise

VTH-OFF to havethe regulated
dead time=V Cr

VTX while L r isin position 1

VIN /2
VIN − nVo

VTX while L r isin position 2

tDEAD-HBAND

Figure 33. Induced Common−mode Noise on VDS at
Switching Transition of the Primary−side Switches

t
nVo

t
−nVo

ISD1 of M1t(b) VTX at Switching Transition

When Lr is not integrated into the transformer, the positionof Lr matters in the generation of the common−mode noise.
Consider two positions for Lr placement as in Figure 34 (a).
For proper operation of the LLC converter, those two
positions give no difference. However, when theinter−winding capacitor is considered, which is lumped as a
Cinter in the figure, the two positions give different results forthe common−mode noise.
The voltage on one side of the Cinter is notated as VTX. As
drawn in Figure 34 (b), the Lr position 1 makes VTX equal
to VCr, which changes gradually during the switching
operation. Comparatively, when Lr is in position 2, the VTX
waveform shows sudden changes in switching transition of
the primary side and current commutating of the secondaryside.

Cinter
VTX

Zsec
CY

I(s) ≈ VTX (s) · (s· Cinter )(c) VTX Induces Displacement Current on
the Inter-winding Capacitor
Figure 34. Inter−winding Capacitance andPlacement of Lr

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AND90154/D
Conclusion

meant to share the insights for selecting the appropriate OPN
by explaining the functionalities in much detail. Somecircuit design tips are provided to ease the difficulties that
one might sometimes confront when designing LLC
converters with NPC4318 for the SR control.

NCP4318 is an SR controller for LLC converters withcenter−tapped secondary−side configuration. With highly
integrated functionalities, NCP4318 controls the SR powerswitches with very few additional circuit elements.
NCP4318 delivers the driving pulses for SR power switches
that maximize the efficiency of LLC converters. Withsophisticated protections, NCP4318 responds to suddenchanges in the operation of LLC converters with appropriate
actions in the gate drive signals.
NCP4318 has several orderable part numbers (OPNs) thatprovides different function sets and parameter values. For
different LLC converter designs, the required function sets
and parameter values may vary. This application note isReferences[1] NCP4318 Data Sheet
https://www.onsemi.com/pdf/datasheet/ncp4318−d.pdf[2] LLC Resonant Converter Synchronous
Rectification Design using FAN6248
https://www.onsemi.com/pub/collateral/and9618−
d.pdf

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