Copyright NTT and Mitsubishi Electric Corporation 2000-2002

Camellia: A 128-Bit Block Cipher
Suitable for Multiple Platforms
Kazumaro Aoki† Tetsuya Ichikawa‡ Masayuki Kanda†
Mitsuru Matsui‡ Shiho Moriai† Junko Nakajima‡ Toshio Tokita‡† Nippon Telegraph and Telephone Corporation
1-1 Hikarinooka, Yokosuka, Kanagawa, 239-0847 Japan{maro,kanda,shiho}@isl.ntt.co.jp‡ Mitsubishi Electric Corporation
5-1-1 Ofuna, Kamakura, Kanagawa, 247-8501 Japan{ichikawa,matsui,june15,tokita}@iss.isl.melco.co.jp
Ver 1.0:
Ver 2.0:
Ver 2.1:

July 13, 2000
September 26, 2001
February 18, 2002

Abstract. We present a 128-bit block cipher called Camellia. Camellia supports
128-bit block size and 128-, 192-, and 256-bit keys, i.e. the same interface specifications as the Advanced Encryption Standard (AES). Efficiency on both softwareand hardware platforms is a remarkable characteristic of Camellia in addition to its
high level of security. It is confirmed that Camellia provides strong security against
differential and linear cryptanalysis. Compared to the AES finalists, i.e. MARS,
RC6, Rijndael, Serpent, and Twofish, Camellia offers at least comparable encryption/decryption speed in software and hardware. An optimized implementation of
Camellia in assembly language can encrypt on a Pentium III (1.13GHz) at the rateof 471 Mbits per second. In addition, a distinguishing feature is its small hardware
design. A hardware implementation, which includes encryption, decryption, and the
key schedule for 128-bit keys, occupies only 7.875K gates using a 0.11µm CMOS
ASIC library. This is in the smallest class among all existing 128-bit block ciphers.

Copyright NTT and Mitsubishi Electric Corporation 2000-2002

Contents
1 Introduction

1

2 Design Rationale
2.1 F -function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 P -function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 s-boxes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4 F L- and F L−1 -functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5 Key Schedule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3
3
3
3
3
4

3 Performance Figures
3.1 Software Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Hardware Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

55
5

4 Software Implementation Techniques
4.1 Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2 Data Randomization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3 General Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11
11
12
18

5 Hardware Evaluations
5.1 Type 1: Fast Implementation-1 (Fully loop unrolled architecture) . . . . . . . . .
5.2 Type 2: Small Implementation-1 (Loop architecture) . . . . . . . . . . . . . . . .
5.3 Type 3: Small Implementation-2 (Special Case for FPGA, Loop architecture) . .
5.4 Type 4: Fast Implementation-2 (Pipeline architecture) . . . . . . . . . . . . . . .

20
20
21
22
24

6 Security
6.1 Differential and Linear Cryptanalysis . . . . . . . . . . . . . . . . . . . . . . . . .
6.2 Truncated Differential Cryptanalysis . . . . . . . . . . . . . . . . . . . . . . . . .
6.3 Truncated Linear Cryptanalysis . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4 Cryptanalysis with Impossible Differential . . . . . . . . . . . . . . . . . . . . . .
6.5 Boomerang Attack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6 Higher Order Differential Attack . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.7 Square Attack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.8 Interpolation Attack and Linear Sum Attack . . . . . . . . . . . . . . . . . . . .
6.9 No Equivalent Keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.10 Slide Attack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.11 Related-key Attack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.12 Statistical Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.13 Implementation Attacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.14 Brute Force Attacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

26
26
27
29
29
29
30
30
31
31
31
32
32
32
33

7 Conclusion

35

A History

41iCopyright NTT and Mitsubishi Electric Corporation 2000-2002

1

Introduction

This paper presents a 128-bit block cipher called Camellia, which was jointly developed by NTT
and Mitsubishi Electric Corporation. Camellia supports 128-bit block size and 128-, 192-, and256-bit key lengths, and so offers the same interface specifications as the Advanced Encryption
Standard (AES). The design goals of Camellia are as follows.
High level of security. The recent advances in cryptanalytic techniques are remarkable. A
quantitative evaluation of security against powerful cryptanalytic techniques such as differential
cryptanalysis [BS93] and linear cryptanalysis [M94] is considered to be essential in designing any
new block cipher. We evaluated the security of Camellia by utilizing state-of-art cryptanalytic
techniques. We have confirmed that Camellia has no differential and linear characteristics that
hold with probability more than 2−128 . Moreover, Camellia was designed to offer security against
other advanced cryptanalytic attacks including higher order differential attacks [K95, JK97],
interpolation attacks [JK97, A00], related-key attacks [B94, KSW96], truncated differential attacks [K95, MT99], boomerang attacks [W99], and slide attacks [BW99, BW00].
Efficiency on multiple platforms. As cryptographic systems are needed in various applications, encryption algorithms that can be implemented efficiently on a wide range of platforms
are desirable, however, few 128-bit block ciphers are suitable for both software and hardware
implementation. Camellia was designed to offer excellent efficiency in hardware and software
implementations, including gate count for hardware design, memory requirements in smart card
implementations, as well as performance on multiple platforms.
Camellia consists of only 8-by-8-bit substitution tables (s-boxes) and logical operations thatcan be efficiently implemented on a wide variety of platforms. Therefore, it can be implemented
efficiently in software, including the 8-bit processors used in low-end smart cards, 32-bit processors widely used in PCs, and 64-bit processors. Camellia doesn’t use 32-bit integer additions andmultiplications, which are extensively used in some software-oriented 128-bit block ciphers. Such
operations perform well on platforms providing a high degree of support, e.g., Pentium II/III or
Athlon, but not as well on others. These operations can cause a longer critical path and larger
hardware implementation requirements.
The s-boxes of Camellia are designed to minimize hardware size. The four s-boxes areaffine equivalent to the inversion function in the finite field GF(28 ). Moreover, we reduced theinversion function in GF(28 ) to a few GF(24 ) arithmetic operations. It enabled us to implement
the s-boxes by fewer gate counts.
The key schedule is very simple and shares part of its procedure with encryption. It supports
on-the-key subkey generation and subkeys are computable in any order. The memory requirement for generating subkeys is quite small; an efficient implementation requires about 32-byte
RAM for 128-bit keys and about 64-byte RAM for 192- and 256-bit keys.
Standardization activities. In March 2000 NTT and Mitsubishi Electric Corporation proposed Camellia in response to the call for contributions from ISO/IEC JTC 1/SC 27, aiming at
its being adopted as an international standard. In September 2000, we submitted Camellia to1

Copyright NTT and Mitsubishi Electric Corporation 2000-2002

NESSIE (New European Schemes for Signature, Integrity, and Encryption) project as a strong
cryptographic primitive. In September 2001, Camellia was selected as a candidates for the 2nd
Phase of the NESSIE project. We also submitted Camellia to several standards efforts such as
CRYPTREC, IETF, TV-Anytime Forum, and so on.
Outline of the paper. This paper is organized as follows: Section 2 describes the rationale
behind Camellia’s design. Section 3 discusses the performance of Camellia. Section 4 contains
the techniques for software implementation. In Section 5 we discuss our hardware evaluations.
In Section 6 we evaluated Camellia’s strength against known attacks. We conclude in Section 7.
For the specification of Camellia, please see the separate document titled “Specification of
Camellia – a 128-bit Block Cipher.” We will follow the definitions and notation given in thisseparate paper.

2

Copyright NTT and Mitsubishi Electric Corporation 2000-2002

2

Design Rationale

2.1

F -function

The design strategy of the F -function of Camellia follows that of the F -function of E2 [KMA+ 98].
The main difference between E2 and Camellia is the adoption of the 1-round (conservative) SPN(Substitution-Permutation Network), not the 2-round SPN, i.e. S-P-S. When the 1-round SPN
is used as the round function in a Feistel cipher, the theoretical evaluation of the upper boundof differential and linear characteristic probability becomes more complicated, but the speed
under the same level of “real” security is expected to be improved. See Section 6 for detailed
discussions on security.

2.2

P -function

The design rationale of the P -function is similar to that of the P -function of E2. That is, for computational efficiency, it should be represented using only bytewise exclusive-ORs and for security
against differential and linear cryptanalysis, its branch number should be optimal [KTM+ 99].
From among the linear transformations that satisfy these conditions, we chose one considering
highly efficient implementation on 32-processors [AU00] and high-end smart cards, as well as
8-bit processors.

2.3

s-boxes

As the s-boxes we adopted functions affine equivalent to the inversion function in GF(28 ) for
enhanced security and small hardware design.
It is well known that the smallest of the maximum differential probability of functions in
GF(28 ) was proven to be 2−6 , and the smallest of the maximum linear probability of functions in
GF(28 ) is conjectured to be 2−6 . There is a function affine equivalent to the inversion function
in GF(28 ) that achieves the best known of the maximum differential and linear probabilities,
2−6 . We choose this kind of functions as s-boxes. Moreover, the high degree of the Boolean
polynomial of every output bit of the s-boxes makes it difficult to attack Camellia by higher orderdifferential attacks. The two affine functions that are performed at the input and output of theinversion function in GF(28 ) complicates the expressions of the s-boxes in GF(28 ), which makes
interpolation attacks ineffective. Making the four s-boxes different slightly improves security
against truncated differential cryptanalysis [MT99].
For small hardware design, the elements in GF(28 ) can be represented as polynomials withcoefficients in the subfield GF(24 ). In other words, we can implement the s-boxes by using a few
operations in the subfield GF(24 ) [MIYY88]. Two affine functions at the input and output of
the inversion function in GF(28 ) also play a role in complicating the expressions of the s-boxes
in GF(24 ).

2.4

F L- and F L−1 -functions

F L- and F L−1 -functions are “inserted” between every 6 rounds of a Feistel network to provide
non-regularity across rounds. One of the goals for such a design is to thwart future unknown
attacks. It is one of merits of regular Feistel networks that encryption and decryption procedures
3

Copyright NTT and Mitsubishi Electric Corporation 2000-2002
are the same except for the order of the subkeys. In Camellia, F L/F L−1 -function layers areinserted every 6 rounds, but this property is still preserved.
The design criteria of F L- and F L−1 -functions are similar to those of the F L-function of
MISTY [M97]. The difference between MISTY and Camellia is the addition of 1-bit rotation.
This is expected to make bytewise cryptanalysis harder, but it has no negative impact on
hardware size or speed. The design criteria are that these functions must be linear for any fixed
key and that their forms depend on key values. Since these functions are linear as long as the key
is fixed, they do not make the average differential and linear probabilities of the cipher higher.
Moreover, these functions are fast in both software and hardware since they are constructed bylogical operations such as AND, OR, XOR, and rotations.

2.5

Key Schedule

The design criteria of the key schedule are as follows.
1. It should be simple and share part of its procedure with encryption/decryption.
2. Subkey generation for 128-, 192- and 256-bit keys can be performed by using the same keyschedule (circuit). Moreover, the key schedule for 128-bit keys can be performed by using
a part of this circuit.
3. Key setup time should be shorter than encryption time.
In cases where large amounts of data are processed with a single secret key, the setup time
for key scheduling may be unimportant. On the other hand, in applications in which the
key is changed frequently, key agility is a factor. One basic component of key agility is key
setup time.
4. It should support on-the-fly subkey generation.
5. On-the-fly subkey generation should be computable in the same way in both encryption
and decryption.
Some ciphers have separate key schedules for encryption and decryption. In otherciphers, e.g., Rijndael [DR98] or Serpent [ABK98], subkeys are computable in the forward
direction only and require unwinding for decryption.
6. There should be no equivalent keys.
7. There should be no related-key attacks or slide attacks.
Criteria 1 and 2 mainly address small hardware requirements, Criteria 3, 4, and 5 are advantageous in terms of practical applications, and Criteria 6 and 7 are for security.
The memory requirement for generating subkeys is quite small. An efficient implementationof Camellia for 128-bit keys requires 16 bytes (=128 bits) for the original secret key, KL , and 16
bytes (=128 bits) for the intermediate key, KA . Thus the required memory is 32 bytes. Similarly,
an efficient implementation of Camellia for 192- and 256-bit keys needs only 64 bytes.

4Copyright NTT and Mitsubishi Electric Corporation 2000-2002

3

Performance Figures

3.1

Software Performance

Table 1 summarizes the current software performance of Camellia on the commonly-used 32-bit
and 64-bit processors. Table 2 shows the software performance on the microprocessors used forsmart cards and embedded systems, which are equipped with the restricted memory. Generally
speaking, the first priority of the former is “Speed,” while that of the latter is “RAM Usage and
ROM Usage.” Some of the data are published in [AIK+ 00a, C01, ISKM01, AIK+ 00b, Y01a,
Y01b], but the others have not been published yet.
The tables show that Camellia can be efficiently implemented on low-end smart cards, 32-bit
and 64-bit processors. We use the abbreviations M (mega) for 106 and m (milli) for 10−3 in thetables.
Optimization level. When we coded programs using assembly language, we tried to use
many techniques described in Section 4 to achieve the best performance. However, there is aroom for further improvement.
On the other hand, depending on the C compiler used, different assembly codes are produced
from the same C code. This means that the assembly codes are not guaranteed to be optimal,
even if the C code is optimized. Thus, we did not spend a long time on optimizing C code.
How to measure speed. It is difficult to measure speed on modern processors since there
are many elements, for example, status of cache, that are beyond the users control and that
influence speed. We decided to measure speed under the following conditions and assumptions:• All codes and data are correctly aligned.
• Input and output texts and codes are preloaded to the first level cache.
• Branch predictions are correct.
• Setup function (except for on-the-fly implementations) generates subkey-dependent constants from the secret key, and the constants are used by encryption or decryption function.
• Encryption (decryption) function except for on-the-fly implementations can encrypt (decrypt) an integral number of blocks.
• We measured the speed many times, and chose the best result to eliminate cache hit misses
and other uncontrollable factors.
• We averaged the speed numbers for large block encryption, but the values include all
overheads including loop and function calls.

3.2

Hardware Performance

Table 3 represents the recent results on hardware performance of Camellia on ASIC (Application
Specific Integrated Circuit) and FPGA (Field Programmable Gate Array). Table 4 shows theenvironment of our hardware design and evaluation.
5

Copyright NTT and Mitsubishi Electric Corporation 2000-2002

Table 4: Hardware evaluation environment (ASIC, FPGA)
Language(ASIC, FPGA) Verilog-HDL
Design library (ASIC) Mitsubishi Electric 0.35µm CMOS ASIC library
Mitsubishi Electric 0.18µm CMOS ASIC library
0.25 µm CMOS ASIC library (reported by CRYPTREC
Report 2000)(FPGA) Xilinx XC4000XL series
Xilinx VirtexE series
Simulator(ASIC, FPGA) Verilog-XL (except for 0.25µm)(ASIC) VCS5.1 (used for 0.25µm)
Logic synthesis (ASIC) Design Compiler version 1998.08 (used for 0.35µm)
Design Compiler version 2000.11-SP1 (used for 0.18µm)
Design Compiler version 2000.05-1 (used for 0.25µm)(FPGA) Synplify version 5.3.1 and ALLIANCE version 2.1i
(used for XC4000XL series)
Synplify version 6.1.3 and ALLIANCE version 3.3.07i(used for VirtexE series)

Table 5: Hardware design policies (outline)
TypeTop priority
Outline of logic
Type 1 Fast implementation from the viewpoint of Enc(Dec) speed
Figure 1
Type 2 Small implementation from the viewpoint of total logic size
Figure 2
Type 3
Small implementation (special case for FPGA)
Figure 3
Type 4
Pipeline implementation
Figure 46

Copyright NTT and Mitsubishi Electric Corporation 2000-2002

We evaluated Type 1 through Type 4 logic. Table 5 shows the top priorities of the logic types.
The details of each type are described in Section 5.

7

Table 1: Performance of Camellia (updated on Aug.31, 2001)
Software Performance
RAM Usage(*1)

Speed
Processor

Language

Pentium III (*3)

Assembly

Pentium III (*4)

Assembly

Pentium II (*5)

ANSI CPentium III (*6)

Java

Alpha 21264 (*7)

Assembly

Alpha 21264 (*8)

Assembly

UltraSPARCIIi (*9)

AssemblyKey
Size

Encryption
Key
Decryption
scheduling[bits] [cycles] [cycles][Mbps]

128
128
192
256
128
128
128
128
128
128
128
192
256
128
128
128
128
128

1,570
308
160
371
222
494
226
494
‑
326
(Enc) 467 (*2)(Dec) 474 (*2)
263
577
9,091
793
158
326
118
339
176
445
176
445
‑
282
(Enc) 448 (*2)(Dec) 435 (*2)‑
355
403(*2)

290.9
241.5
181.4
181.4
255.2
0.72µsec
0.73µsec
66.6
161.4
261.9
251.8
191.9
191.9
210.2
0.97µsec
0.94µsec
144.2
1.01µsec

ROM Usage

Key
Enc./Dec.
scheduling[bytes][bytes]

288
28
28
28
‑
‑
‑
44
‑
48
48
48
48
‑
‑
‑
‑
‑

20
36
36
36
‑
‑
‑
64
‑
48
48
48
48
‑
‑
‑
‑
‑

Total
Size
[bytes]Key
Enc./Dec.
scheduling[bytes][bytes]15,012
11,42013,032
13,04829,285
20,11020,236
9,461‑
21,04020,73622,19622,20431,552
25,792
25,792
15,24023,992

6,788
1,046
1,469
1,485
‑
‑
‑
1,600
‑
1,600
1,132
1,668
1,676
‑
‑
‑
‑
‑

0
2,150
3,323
3,323
‑
‑
‑
3,733
‑
2,928
3,076
4,000
4,000
‑
‑
‑
‑
‑

(*1) The figure includes stack area, and excludes text area and key area.
(*2) The figure includes key generation and one block encryption. This is achieved by using the on‑the‑fly key generation.
(*3) IBM PC/AT compatible PC, Intel Pentium III (700MHz), 256KB on‑die L2 cache, FreeBSD 4.0R, 128MB main memory.
(*4) IBM PC/AT compatible PC, Intel Pentium III (650MHz), 256KB on‑die L2 cache, Windows98 SE, 64MB main memory.
(*5) IBM PC/AT compatible PC, Intel Pentium II (300MHz), 512KB L2 cache, Windows95, 160MB main memory.
(*6) IBM PC/AT compatible PC, Intel Pentium III (1GHz), 256KB on‑die L2 cache, Windows2000, 512MB main memory(*7) Alpha 21264 (667MHz), Tru64 UNIX 4.0F, 2GB main memory.
(*8) Alpha 21264 (463MHz), Tru64 UNIX V5.1, 512MB main memory.
(*9) Ultra SPARC IIi (400MHz), Solaris 7, 256MB main memory.

Table

Reference/Notes[bytes]8,224 1st NESSIE Workshop (Nov.2000)
8,224 1st NESSIE Workshop (Nov.2000)
8,240 1st NESSIE Workshop (Nov.2000)
8,240 1st NESSIE Workshop (Nov.2000)
CRYPTREC Report 2000‑
CRYPTREC Report 2000‑
CRYPTREC Report 2000‑
4,128 1st NESSIE Workshop (Nov.2000)
Not published‑
16,512 1st NESSIE Workshop (Nov.2000)
16,528 1st NESSIE Workshop (Nov.2000)
16,528 1st NESSIE Workshop (Nov.2000)
16,528 1st NESSIE Workshop (Nov.2000)
CRYPTREC Report 2000‑
CRYPTREC Report 2000‑
CRYPTREC Report 2000‑
CRYPTREC Report 2000‑
CRYPTREC Report 2000‑

Table 2: Performance of Camellia (updated on Aug.31, 2001)
Software Performance for Smart Card and Embedded Systems
Speed
Processor

Language

RAM Usage

ROM Usage

Key
Key
Encryption
Key
Enc./Dec
Size scheduling Decryption scheduling[bits][cycles][cycles][bytes]

Total
Size[bytes][bytes]Key
Enc./Dec.
scheduling[bytes][bytes]

Sharing
Size(*5)[bytes]Table[bytes]Reference/Notes(*1)

8051 (*6)

Assembly128
128

Z80 (*7)

Assembly128

H8/3113 (*8)

Assembly

128

MC68HC705B16 (*9)

Assembly

128

MC68HC908AB32 (*10)

Assembly

128

M32Rx/D (*11)

Assembly

128

10,217
10.22msec
5,146
28,382
1.03msec 5.68msec(Enc) 35,951 (*1)
7.19msec(Dec) 37,553 (*1)
7.51msec
2,380
4,100
0.95msec 1.64msec
7,500
9,900
3.57msec 4.71msec
5,679
8,430
0.71msec 1.05msec
642
1,236
6.42µsec 12.36µsec

032(*2)

990

0

702

288

44(*3)

62(*3)

1,698

358

1,183

288

0

60(*3)

‑

1,023

‑

0

(*3)

‑

1,042

‑

1,268
60

0 1st NESSIE Workshop (Nov.2000)‑131

Not published‑797

Not published

208(*4)

0

‑

‑

‑

‑

‑ Reported by Chung‑Huang Yang

208(*4)

0

‑

‑

‑

‑

‑

208(*4)

0

‑

‑

‑

‑

‑

44(*2)

44(*2)

8,684

1,392

3,164

4,128

(*1) The figure includes key generation and one block encryption. This is achieved by using the on‑the‑fly key generation.
(*2) The figure includes stack area, and excludes text area and key area.
(*3) The figure includes stack area, text area and key area.
(*4) The figure shows the size of round keys.
(*5) Some ROM size may be reduced, since some functions can be shared among key generation, encryption and decryption.
(*6) Intel 8051 (12MHz; 1cycle=12oscillator periods) simulator on Unix.
(*7) Z80 (5MHz) simulator on Windows.
(*8) Hitachi H8/3113 (5MHz; 1cycle=2oscillator periods) on Hitachi's E6000 Emulator.
(*9) Motorola 6805 series MC68HC705B16 (2.1MHz) on Motorola's In‑Circuit Simulator Kits.
(*10) Motorola 6805 series MC68HC908AB32 (8MHz) on Motorola's In‑Circuit Simulator Kits.
(*11) Mitsubishi 32‑bit microcomputer M32Rx/D (100MHz) on MSA2310 evaluation board.

[National Kaohsiung First
Univ. of Sci. and Tech.]Updated Version of SCIS2001

Reported by Chung‑Huang Yang
New Result

0 1st NESSIE Workshop (Nov.2000)

Table 3: Performance of Camellia (updated on Feb.18, 2002)
Hardware Performance
Speed
Type

Archi‑
tectureDesign Library

Mitsubishi 0.35 µm
Unrolled Mitsubishi 0.18 µm
Mitsubishi 0.18µm
Mitsubishi 0.35µm
Mitsubishi 0.35 µm
Mitsubishi 0.18 µm
Mitsubishi 0.18µm
Mitsubishi 0.18µm

ASIC

Mitsubishi 0.18µm
Loop

Mitsubishi 0.18µm
Mitsubishi 0.18µm
0.25µm
0.25µm
IBM 0.11µm
IBM 0.11µm
IBM 0.11µm
Xilinx XC4000XL

Loop
FPGA

Xilinx VirtexE
Xilinx VirtexE
Xilinx VirtexE

Unrolled

Xilinx VirtexE

Pipeline

Xilinx VirtexE

Area Size

Key Key Setup
Max. delay Latency
time
Size

Throughput[bits][nsec][nsec][cycles][Mbps]

128
128
128
128
128
128
128
128
128
128
128
256
256
128
128
128
128
128
128
128
128
128

24.36
40.00
45.96
110.20117.04144.88
25.92
28.20
23.20
137.2412.96

109.35
40.00
45.96
27.67
28.73
36.22
6.48
7.05
5.80
34.31
3.24
5.46
11.51
8.72
8.82
4.21
78.82
30.56
28.80
26.80
318.50
18.96

1
1
1
21
21
21
21
21
21
21
21

1170.55
3200.00
2785.00
220.28212.16168.28940.62864.571050.90
177.65
1881.25837.00397.00333.65806.26
1689.1077.34
199.46211.90227.42401.896749.99‑‑‑‑‑362.83135.03126.00127.04
97.70
83.25

‑
‑
44
18
18
21
21
21
21
1
20

Unit

Total (*1)[unit]

Kgate

Kgate

CLB

Slice

272.82355.10244.90
11.35
9.66
8.51
27.46
21.45
11.87
8.12
44.30
39.35
23.12
7.88
13.71
23.38
1,296
1,816
1,816
1,780
9,426
9,692

Efficiency

Key
Enc./Dec.
Throughput/Area(*3)
sched. (*2)[unit][unit][Kbps/unit]

55.91

216.91
‑
‑

4.98
5.75

‑
‑
6.37
3.91

‑
‑
‑
‑
‑
‑
22.76
13.30

‑
‑
‑
‑
‑
‑
16.33
9.67

‑
‑
‑
‑
‑
‑
‑

‑
‑
‑
‑
‑
‑
‑

‑
‑

‑
‑

Reference/Notes

4.29 1st NESSIE Workshop (Nov.2000)
Not published9.01
Not published
11.37
ISEC2000‑73 (Sep.2000)
19.41
21.96 1st NESSIE Workshop (Nov.2000)
Not published
19.77
Not published
34.25
Not published
40.31
Not published
88.52
Not published21.87
Not published
42.47
CRYPTREC Report 2000
21.27
CRYPTREC Report 2000
17.17
42.37
Reported by A.Satoh, et al.
[IBM Research]
58.80
SCIS2002 (Jan.2002)
72.24
59.68 1st NESSIE Workshop (Nov.2000)
ISEC2001‑53 (Sep.2001)
109.83
ISEC2001‑53 (Sep.2001)
116.69ISEC2001‑53 (Sep.2001)
127.76
ISEC2001‑53 (Sep.2001)
42.64
ISEC2001‑53 (Sep.2001)
696.45(*1) The figure includes key scheduling circuit, encryption/decryption circuit, controller, output register, subkey register and buffers for fan‑out adjustment.
(*2) The figure includes subkey register.
(*3) The figure includes output register.

Copyright NTT and Mitsubishi Electric Corporation 2000-2002

4

Software Implementation TechniquesThis section describes how to implement Camellia efficiently in software. In most cases, animplementation can be divided into two parts: setup including key schedule and data randomization, that is, encryption or decryption. We first describe how to optimize the setup code, andthen describe how to optimize the data randomization code.
This section describes specific techniques for 8-, 32-, or 64-bit processors. However, a technique for 8-bit processors may be applicable to 32- or 64-bit processors and a technique for 32-bit
processors may be applicable to 64-bit processors. Other word sizes may need to be considered.
We assume that you first implement Camellia using the specification as it is. This section
will optimize the resulting code.
Note that in this section “word” means the natural size of the target processor. For example,
the words of IA-32 without MMX technology, IA-32 with MMX technology and Alpha are 32-,64-, and 64-bits long respectively.

4.1
4.1.1

Setup
Store All Subkeys

Store all subkeys into memory once you generate them if you have sufficient memory, and use
the stored subkeys for data randomization.
4.1.2

Subkey Generation Order

You do not have to compute subkeys in order. For example, when you compute subkeys for a
128-bit key, first compute the subkeys that only depend on KL , and then compute subkeys that
only depend on KA . This reduces the number of registers or memory for storing KA .
4.1.3

XOR Cancellation Property in Key Schedule

The key schedule of Camellia is based on the Feistel structure. Between the 2nd round and the
3rd round, KL is XORed to an intermediate value. This structure causes cancellations of KL .
More precisely, the input of the 3rd round can be computed by the following equations.
((right half)(left half)((right half)(left half)

=
=
=
=

F (KLL , Σ1 )
F (KLR ⊕ (right half), Σ2 )KRR ⊕ F (KLL ⊕ KRL , Σ1 )KRL ⊕ F (KLR ⊕ (right half), Σ2 )for 128-bit keysfor 192- and 256-bit keys

Using the above equations, we can eliminate 3 and 2 XORs in L for 128- and 192/256-bit keys,
respectively, compared to the straightforward implementation of the specification.
4.1.4

Rotation Bits for KL , KR , KA , and KB

You do not need to keep KL , KR , KA , and KB , but you should keep their rotated values whengenerating subkeys. You can generate subkeys by rotating the kept values by a sum of integral
multiples of 16 ± 1 bits.
11

Copyright NTT and Mitsubishi Electric Corporation 2000-2002
kl5 and kl6 Generation from k11 and k12

4.1.5

For 192- and 256- bit keys, you can use word-oriented rotation to generate (kl5 , kl6 ) from(k11 , k12 ), since (kl5 , kl6 ) equals (k11 , k12 )<<<32 . This saves a few instructions compared to general rotation.
4.1.6

On-the-fly Subkey Generation

You can generate subkeys on-the-fly. All subkeys are one of the rotated values of KL , KR ,KA , and KB . Thus, you first generate KL , KR , KA , and KB , and then rotate them to get thesubkeys. Refer to Section 4.1.4 for the rotated numbers of bits for KL , KR , KA , and KB .
4.1.7

128-bit key and 192/256-bit key

If your code does not need to use key sizes larger than 128 bits, you do not need to generate
KB . That is, you can omit the computations for the last two F -functions.
4.1.8

How to Rotate an Element in Q

8-bit processor. As stated in Section 4.1.4, the amount of rotation in bits is a sum of integral
multiples of 16 ± 1. Thus, you can rotate an element in Q by 16 ± 1 bits by rotating 1-bit leftor right followed by a 2-byte move.
32-bit processor. Consider the use of a double precision shift instruction: shrd or shld if
you are programming on IA-32.
F -function

4.1.9

Key schedule includes F -functions, but the main usage of the F -function is for data randomization. Refer to Section 4.2.
4.1.10

Keyed Functions

Camellia has three keyed functions: bitwise XOR, bitwise OR, and bitwise AND. Consider theuse of a self-modifying code, if possible.

4.2

Data Randomization

4.2.1

Endian Conversion

Camellia prefers big endian. Thus, the code for little endian processors needs additional codefor endian conversions.
The most straightforward implementation converts the endian when loading a register frommemory and storing a register to memory. Only F L- and F L−1 -functions are endian dependent.
More precisely, only the 1-bit rotation in F L- or F L−1 -function is endian dependent. This meansthat you can convert endians just before or just after the 1-bit rotation with the appropriate

12Copyright NTT and Mitsubishi Electric Corporation 2000-2002

subkey generation scheme. A combination of computing endian conversion and 1-bit rotation
may increase the performance of Camellia. Details are described in Section 4.2.2.
Some processors have a special instruction for endian conversion. For example, IA-32 (after
80486) has bswap instruction. Use these instructions. However, do not use the byte swap
technique described in [C98, Appendix A]. The technique reduces the code size, but it is not
fast, since the memory load and store instruction incurs long latency.
As described above, the endian problem only effects the 1-bit rotation of a 32-bit word.
Thus, we do not need full 64-bit word endian conversion.
The following are general methods to realize endian conversion for 32-bit register x. In
the following techniques, you can use either ∪ or ⊕ instead of + in the equations, and you canswitch the computational order between shifts including rotations and ANDs with an appropriate
conversion of masked constants.
Straightforward.
x ← (x 24 ) + ((x ∩ 0xff00) 8 ) + ((x 8 ) ∩ 0xff00) + (x 24 )The technique has high parallelism.
Minimum operations without rotation.
x ← (x 16 ) + (x 16 )x ← ((x ∩ 0xff00ff) 8 ) + ((x 8 ) ∩ 0xff00ff)
Using rotations.
x ← ((x ∩ 0xff00ff)>>>8 ) + ((x<<<8 ) ∩ 0xff00ff)
Using SSE. New Intel Pentium family processors including Pentium III have a very effective
instruction for reordering data, which is called pshufw [I99]. 5 instructions including pshufw
are sufficient to convert endian for 64-bit data.
4.2.2

1-bit Rotation in Little Endian Interpretation

As described in Section 4.2.1, we do not need endian conversion when loading and storing texts
if we can efficiently implement 1-bit rotation in F L- and F L−1 -functions.
Assuming x to be a 32-bit register that contains little endian data to be rotated by 1-bit, we
can compute 1-bit rotation by the following equation.
x ← ((2x) ∩ 0xfefefefe) + ((x>>>15 ) ∩ 0xfefefefe)(1)

Of course, this technique requires an appropriate changes to subkey setup and other functions.
Note that + in Equation (1) can be replaced with ∪ or ⊕, and computing 2x can be done by1 , <<<1 or addition with x itself, and you can switch the computational order between shifts
including rotations and ANDs with an appropriate conversion of masked constants.
Confirm whether your processor has ANDNOT instruction, such as pandn in IA-32 and bic
in Alpha. In this case, you do not need to prepare the constant, 0xfefefefe.
13

Copyright NTT and Mitsubishi Electric Corporation 2000-2002

4.2.3

Whitening

The key additions kw2 and kw4 can be combined into other keyed operations using the following
equations.
(x ⊕ k) ⊕ y = (x ⊕ y) ⊕ k,(x ⊕ k) ⊕ l = x ⊕ (k ⊕ l),(x ⊕ k) ∩ l = (x ∩ l) ⊕ (k ∩ l),(2)(x ⊕ k)<<<1 = (x<<<1 ) ⊕ (k<<<1 ),(x ⊕ k) ∪ l = (x ∪ l) ⊕ (k ∩ l),where x, y, k, l are bit strings. Adjust subkeys at setup to eliminate 2 XORs in L.
4.2.4

Key XOR

Using Equations (2), you can move key XORs to any place if the movement does not go throughthe S-function. For example, changing F -function computation P (S(X ⊕ k)) to P (S(X)) ⊕ k0
may improve instruction scheduling.
4.2.5

S-function

s1 is defined by the arithmetics in GF(28 ). However, do not compute GF(28 ) arithmetics; instead
precompute and hard-code a table in your program, see Table 4 in the specification.
We strongly suggest that you also precompute and hard-code s2 , s3 , and s4 tables in addition
to s1 , if you have sufficient memory and 8-bit rotation is expensive. If you do not have sufficient
memory, the data of s2 , s3 , and s4 can be generated from the table for s1 using one rotation(See Section 4.5 in the specification).
If you have sufficient memory, and cost of table lookup is heavy, as is true for the current Javavirtual machines, consider the use of a two s-box combined table, for example (s1 (y1 ), s2 (y2 )).
4.2.6

P -function

32-bit processor. Let (ZL , ZR ) = ((z1 , z2 , z3 , z4 ), (z5 , z6 , z7 , z8 )) be the input of P -function0 ) = ((z 0 , z 0 , z 0 , z 0 ), (z 0 , z 0 , z 0 , z 0 )) be the output of P -function.
and (ZL0 , ZR
1 2 3 45 6 7 8From Figure 5 in the specification, you can see that P -function can be computed as follows.
ZL ← ZL ⊕ (ZR <<<8 )ZR ← ZR ⊕ (ZL <<<16 )ZL ← ZL ⊕ (ZR >>>8 )ZR ← ZR ⊕ (ZL >>>8 )ZL0 ← ZR

0
ZR
← ZL

14

Copyright NTT and Mitsubishi Electric Corporation 2000-2002

The critical path of this computation is long. We can modify the computation as follows.
ZL
ZL
ZL
ZL
ZL0

←
←
←
←
←

ZL ⊕ ZR
ZL >>>8
ZL ⊕ ZRZL <<<8
ZR

ZR
ZR
ZR
ZR
ZR
0
ZR

←
←
←
←
←
←

ZR <<<8
ZR <<<8
ZR ⊕ ZLZR <<<16
ZR ⊕ ZLZL

The critical path of the above computation is decreased. It seems that the technique requires one
additional rotation, however, you can probably combine the first step of the above computationand S-function without any additional cost.
8-bit processor (orthogonal mnemonics). If the instruction in your processor can XOR
any combination of registers and has sufficient registers, you can compute P -function by using
just 16 XORs using Figure 5 in the specification.
8-bit processor (accumulator based). If your processor is accumulator based, minimizing
the number of XORs is not always a good idea, since the computation may require register loadfrom memory and store into memory many times. The following computation is optimized foran accumulator based processor.
z80 ← z1 ⊕ z4 ⊕ z5 ⊕ z6 ⊕ z7
z40 ← z80 ⊕ z1 ⊕ z2 ⊕ z3
z70 ← z40 ⊕ z2 ⊕ z7 ⊕ z8
z30 ← z70 ⊕ z1 ⊕ z2 ⊕ z4
z60 ← z30 ⊕ z1 ⊕ z6 ⊕ z7
z20 ← z60 ⊕ z1 ⊕ z3 ⊕ z4
z50 ← z20 ⊕ z4 ⊕ z5 ⊕ z6
z10 ← z50 ⊕ z2 ⊕ z3 ⊕ z4
When indexing zi0 costs many operations, the following is useful.
σ ← z1 ⊕ z2 ⊕ z3 ⊕ z4 ⊕ z5 ⊕ z6 ⊕ z7 ⊕ z8

z10 ← σ ⊕ z2 ⊕ z5
z20 ← σ ⊕ z3 ⊕ z6
z30 ← σ ⊕ z4 ⊕ z7
z40 ← σ ⊕ z1 ⊕ z8

z50 ← σ ⊕ z3 ⊕ z4 ⊕ z5
z60 ← σ ⊕ z1 ⊕ z4 ⊕ z6
z70 ← σ ⊕ z1 ⊕ z2 ⊕ z7
z80 ← σ ⊕ z2 ⊕ z3 ⊕ z8
15

Copyright NTT and Mitsubishi Electric Corporation 2000-2002

4.2.7

Substitution and Permutation

This section describes how to efficiently compute P ◦ S compared to independently computing
S and P .
64-bit processor. If your processor has a sufficiently large first level cache, use the techniquedescribed in [RDP+ 96]. The technique prepares the following tables defined by Equations (3).
SP1 (y1 )SP2 (y2 )SP3 (y3 )SP4 (y4 )
SP5 (y5 )
SP6 (y6 )SP7 (y7 )
SP8 (y8 )

=
=
=
=
=
=
=
=

(s1 (y1 ), s1 (y1 ), s1 (y1 ),0, s1 (y1 ),0,0, s1 (y1 ))(0, s2 (y2 ), s2 (y2 ), s2 (y2 ), s2 (y2 ), s2 (y2 ),0,0)(s3 (y3 ),0, s3 (y3 ), s3 (y3 ),0, s3 (y3 ), s3 (y3 ),0)(s4 (y4 ), s4 (y4 ),0, s4 (y4 ),0,0, s4 (y4 ), s4 (y4 ))(0, s2 (y5 ), s2 (y5 ), s2 (y5 ),0, s2 (y5 ), s2 (y5 ), s2 (y5 ))(s3 (y6 ),0, s3 (y6 ), s3 (y6 ), s3 (y6 ),0, s3 (y6 ), s3 (y6 ))(s4 (y7 ), s4 (y7 ),0, s4 (y7 ), s4 (y7 ), s4 (y7 ),0, s4 (y7 ))(s1 (y8 ), s1 (y8 ), s1 (y8 ),0, s1 (y8 ), s1 (y8 ), s1 (y8 ),0)(3)

Next, compute the following equation:(z10 , z20 , z30 , z40 , z50 , z60 , z70 , z80 ) ←8M

SPi (yi )i=1This technique requires the following operations.
# of table lookups# of XORs
Size of table (KB)8
7
16

If the first cache of the target processor is moderately large, replace a few of the tables
defined by Equations (3) with the tables below.
SPα (y)SPβ (y)SPγ (y)SPδ (y)====(s1 (y), s1 (y), s1 (y), s1 (y), s1 (y), s1 (y), s1 (y), s1 (y))(s2 (y), s2 (y), s2 (y), s2 (y), s2 (y), s2 (y), s2 (y), s2 (y))(s3 (y), s3 (y), s3 (y), s3 (y), s3 (y), s3 (y), s3 (y), s3 (y))(s4 (y), s4 (y), s4 (y), s4 (y), s4 (y), s4 (y), s4 (y), s4 (y))(4)

Then, mask the necessary byte positions. This technique requires the following operations if
you use just tables of Equations (4).
# of table lookups# of XORs# of ANDs
Size of table (KB)

8
7
8
8

When implementing this technique on Alpha architecture [C98], and if the number of registers
is insufficient for storing constants for masking operation, use zap or zapnot instructions.

16

Copyright NTT and Mitsubishi Electric Corporation 2000-2002

If your processor can efficiently copy half bits of a register to the other half, for example, punpckldq/punpckhdq or pshufw instructions in IA-32 [I99] which are realized after Pentium with MMX technology and Pentium III, respectively, prepare SP1 , SP2 , SP3 , and SP4
defined in Equations (3). Then, compute the following equation:(z10 , z20 , z30 , z40 , z50 , z60 , z70 , z80 )← SP1 (y1 ) ⊕ SP2 (y2 ) ⊕ SP3 (y3 ) ⊕ SP4 (y4 ) ⊕ ν(SP1 (y8 ) ⊕ SP2 (y5 ) ⊕ SP3 (y6 ) ⊕ SP4 (y7 )),where ν denotes the operation that copies the first 4 bytes to the last 4 bytes. This techniquerequires the following operations.
# of table lookups# of XORs# of νs
Size of table (KB)

8
7
1
8

32-bit processor. [AU00] shows efficient implementations of Camellia-type substitution andpermutation networks. One of the techniques prepares the following tables defined by Equations (5):SP1110 (y) = (s1 (y), s1 (y), s1 (y),0)
SP0222 (y) = (0, s2 (y), s2 (y), s2 (y))(5)
SP3033 (y) = (s3 (y),0, s3 (y), s3 (y))
SP4404 (y) = (s4 (y), s4 (y),0, s4 (y))
Then, compute as follows:
D ← SP1110 (y8 ) ⊕ SP0222 (y5 ) ⊕ SP3033 (y6 ) ⊕ SP4404 (y7 )U(z10 , z20 , z30 , z40 )(z50 , z60 , z70 , z80 )← SP1110 (y1 ) ⊕ SP0222 (y2 ) ⊕ SP3033 (y3 ) ⊕ SP4404 (y4 )← D⊕U← (z10 , z20 , z30 , z40 ) ⊕ (U >>>8 )This technique requires the following operations.
# of table lookups# of XORs# of rotations
Size of table (KB)

8
8
1
4

[AU00] also shows an implementation that is suitable for a processor in which rotation is very
costly. The technique prepares the following tables in addition to tables defined by Equations (5):SP1001 (y)SP2200 (y)SP0330 (y)SP0044 (y)

=
=
=
=

(s1 (y),0,0, s1 (y))(s2 (y), s2 (y),0,0)(
0, s3 (y), s3 (y),0)(
0,0, s4 (y), s4 (y))

17Copyright NTT and Mitsubishi Electric Corporation 2000-2002

Then, compute as follows:
D ← SP1110 (y8 ) ⊕ SP0222 (y5 ) ⊕ SP3033 (y6 ) ⊕ SP4404 (y7 )(z10 , z20 , z30 , z40 )(z50 , z60 , z70 , z80 )← D ⊕ SP1110 (y1 ) ⊕ SP0222 (y2 ) ⊕ SP3033 (y3 ) ⊕ SP4404 (y4 )← D ⊕ SP1001 (y1 ) ⊕ SP2200 (y2 ) ⊕ SP0330 (y3 ) ⊕ SP0044 (y4 )This technique requires the following operations.
# of table lookups# of XORs
Size of table (KB)
4.2.8

12
11
8

Making Indices for s-box

You can make an index for s-box by simply using shifts and ANDs. However, several processors
have special instructions for making an index, for example, movzx in IA-32 [I99] and extbl in
Alpha [C98].
movzx is a fast operation in P6, but it can be used only for the two least significant bytes.
A straightforward implementation uses eax, ebx, ecx, and edx registers for storing (Lr , Rr ),and 2 rotations are used for making indices; 2 rotations are used for recovering byte order inthe registers every round. However, you can remove 2 rotations for recovering byte order every
round if you prepare rotated tables. Note that the byte order in registers returns to a naturalorder every 4 rounds.

4.3

General Guidelines

This section describes general guidelines. The guidelines are useful to optimize Camellia as wellas other block ciphers. Please refer to the optimization manuals for each processor.
Avoid misaligned data accesses. Almost all processors penalize misaligned data access.
Align data to the word boundary.
Avoid partial data accesses. Most processors have a function to access a smaller part thanword size. However, this function may cause a penalty. Do not access partial data, even
if you do not need full size of word and you have sufficient memory.
Be careful of the size of the cache. If the program or its data exceeds the size of the cache,the speed of the program will significantly decrease. Loop unrolling and table expansion
are good techniques to speed up the program, but do not exceed the size of the cache.
Use intrinsic functions. Several compilers support intrinsic functions. For example, when
you use Microsoft Visual C++ version 6 compiler on IA-32, and declare “#pragma
intrinsic( lrotl)” and use “ lrotl”, the compiler generates rotation instructions inassembly language. Refer to the manual of the compiler that you use for details.
Measuring precise speeds is difficult. The running time of your code depends on manyfactors: cache hit misses, OS interrupts, and so on. Furthermore, the cryptographic
18

Copyright NTT and Mitsubishi Electric Corporation 2000-2002

properties, for example, the number of blocks to be encrypted, also effect the runningtime.
A few processors have an instruction to get the time stamp. For example, IA-32 (after
Pentium) has rdtsc [I99] and Alpha has rpcc [C98]. It is a good idea to use the timestamp counter for measuring speeds, but you should not directly apply these instructions
to out-of-order architectures such as P6 and EV6.
If you want to measure speed precisely, consult good guidebooks. For example, if you
use Pentium family processors, refer to [F00].

19

Copyright NTT and Mitsubishi Electric Corporation 2000-2002

5

Hardware Evaluations

In Section 3, we showed evaluation results of hardware implementations (ASIC, FPGA) of
Camellia. In this Section, we describe the design policies of the four types of logic evaluated in
Section 3. The details of each type are described below.

5.1

Type 1: Fast Implementation-1 (Fully loop unrolled architecture)

Plaintext / Ciphertext
Encryption
andDecryption
Logic

Subkey Registers

Critical Path of Data Encryption(or Decryption)

In Type 1, we evaluate the hardware implementation (ASIC and FPGA) where the goal is toachieve the fastest encryption and decryption speed with no consideration of logic size. Figure 1
outlines the Type 1 logic. Table 6 shows the basic Type 1 components.

Key Expansion
Logic

Key

Critical Path of Key Expansion

OutputRegisters

Ciphertext / Plaintext

Figure 1: Outline of Type 1 (ASIC, FPGA)

Table 6: The basic Type 1 components
Encryption anddecryption logic
Output register
Key expansion logic
Subkey register

Data randomizing logic for encryption and decryption,
which consists of combinational logic.
Register for the encryption (decryption) data.
Logic in which subkeys are generated from key,which consists of combinational logic.
Register for the output data of key expansion logic.

The design policies of these basic components are listed below.
1. “Encryption and decryption logic” and “Key expansion logic”(a) Loop architecture is not introduced.
20

Copyright NTT and Mitsubishi Electric Corporation 2000-2002(b) Pipeline architecture is not introduced.
(c) Substitution tables (s-boxes) are designed by logic synthesis tool.
2. “Output register” and “Subkey register”(a) The size of Output register is one block (=128 bits).
(b) The size of Subkey register is the total length of all subkeys in the algorithm.
Under the above design policies, we evaluated Camellia on ASIC and FPGA devices. The
results are summarized in Table 3 in Section 3. “Throughput” is defined as follows:
Throughput[b/s] =5.2

Block size(128 [bits]).
Critical path of data encryption(decryption)[sec]Type 2: Small Implementation-1 (Loop architecture)

Key

Critical Path of Data Encryption(or Decryption)

Plaintext / Ciphertext
Key Schedule Logic
anda part of
Key Expansion Logic

Data Selector

One Round of
Encryption and Decryption
Logicwith sharing a part of(or all of) Key Expansion Logic

Subkey Registers

Critical Path of Key Expansion

In Type 2, we evaluate the hardware implementations on ASICs and FPGAs with the goal ofachieving the smallest logic in encryption (and decryption). Figure 2 outlines the Type 2 logic.
Table 7 shows the basic Type 2 components.

Output Registers

Ciphertext / Plaintext

Figure 2: Outline of Type 2 (ASIC, FPGA)

The design policies of these basic components are as follows.
1. “Encryption and decryption logic” and “Key scheduling logic”(a) Loop architecture is introduced (which consists of one round operation).
(b) Pipeline architecture is not introduced.
21

Copyright NTT and Mitsubishi Electric Corporation 2000-2002

Table 7: The basic Type 2 components
Encryption anddecryption logic
Output register
Data selector
Key scheduling logic

Subkey register

Data randomizing logic for one round operation of encryption anddecryption, which includes (a part of) key expansion logic, andconsists of combinational logics.
Register for the output (and intermediate) data.
Selector which selects either encryption/decryption data or output data.
Logic in which subkeys are generated using (a part of)
key expansion logic in encryption and decryption logic andconsists of combinational logics.
Register for the output data of key scheduling logic.

(c) Substitution tables (s-boxes) are optimized by hand.
(d) Key scheduling logic consists (a part of) key expansion logic and control logic.
2. “Output register”, “Subkey register” and “Data selector”(a) The size of Output register is one block (=128 bits).
(b) The size of Subkey register is that of the subkeys used in Encryption and decryption
logic.
(c) Data selector is 2-1 selector, whose size is one block (=128 bits).
Under the above design policies, we evaluated Camellia on ASICs and FPGAs. The results
are summarized in Table 3 in Section 3. “Throughput” is defined as follows:
Throughput[b/s] =5.3

Block size(128 [bits]).
Critical path of data encryption(decryption)[sec] × latency

Type 3: Small Implementation-2 (Special Case for FPGA, Loop architecture)

In Type 3, we evaluated the hardware implementation (FPGA) as a special case of Type 2.
In Type 3, we assume that all subkeys are given and are loaded into FPGA internal memory.
Figure 3 outlines the Type 3 logic. Table 8 shows the basic Type 3 components.
The design policies of these basic components are as follows.
1. “Encryption and decryption logic”(a) Loop architecture is introduced (which consists of one round operation).
(b) Pipeline architecture is not introduced.
(c) Substitution tables (s-boxes) are optimized by hand.
2. “Output register”, “Subkey memory” and “Data selector”
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Copyright NTT and Mitsubishi Electric Corporation 2000-2002

Data Selector

One Round of
Encryption
andDecryption
Logic

Subkey Memory

Critical Path of Data Encryption(or Decryption)

Plaintext / Ciphertext

Subkeys

Output Registers

Ciphertext / Plaintext

Figure 3: Outline of Type 3 (FPGA)

Table 8: The basic Type 3 components
Encryption anddecryption logic
Output register
Data selector
Subkey memory

Data randomizing logic for one round operation of encryption anddecryption, which includes (a part of) key expansion logic, andconsists of combinational logic.
Register for the output (and intermediate) data.
Selector which selects either encryption (decryption) data or output data.
Memory for the subkeys loaded from outside.

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Copyright NTT and Mitsubishi Electric Corporation 2000-2002(a) The size of Output register is one block (=128 bits).
(b) The size of Subkey memory is the length of all subkeys in the algorithm.
(c) Data selector is 2-1 selector whose size is one block (=128 bits).
Under the above design policies, we evaluated Camellia on an FPGA. The results are summarized in Table 3. “Throughput” is defined as follows:
Throughput[b/s] =5.4

Block size(128 [bits]).
Critical path of data encryption(decryption)[sec] × latency

Type 4: Fast Implementation-2 (Pipeline architecture)

In Type 4, we evaluate the hardware implementation (FPGA) where the goal is to achieve
the fastest encryption and decryption speed with no consideration of logic size. (The pipelinearchitecture cannot realize any feedback modes, such as CBC, CFB, and OFB). Figure 4 outlines
the Type 4 logic. Table 9 shows the basic Type 4 components.
Plaintext / Ciphertext

Encryption and
Decryption Logic
1 round

Subkey Registers

Stage 1

Critical Path of
Pipeline Stage

Register 1

Stage n-1

1 round
Register n-1

Stage nKey Expansion
Logic

1 round
Register nCritical Path of Key Expansion

Ciphertext / Plaintext

Figure 4: Outline of Type 4 (FPGA)

The design policies of these basic components are as follows.
1. “Encryption and decryption logic” and “Key expansion logic”(a) Loop architecture is not introduced.
(b) Pipeline architecture is introduced.
(c) Substitution tables (s-boxes) are designed by logic synthesis tool.
(d) The size of Registers (1 ∼ n) is one block (= 128 bits).
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Table 9: The basic Type 4 components
Encryption anddecryption logic
Key Expansion logic
Subkey register

Data randomizing logic for encryption and decryption,
which consists of combinational logic, andRegisters (1 ∼ n) for the output and intermediate data.
Combinational logic in which subkeys are generated from the key.
Register for the output data from key expansion logic.

2. “Subkey register”(a) The size of Subkey register is the total length of all subkeys in the algorithm.
Under the above design policies, we evaluated Camellia on an FPGA devices. The results
are summarized in Table 3. “Throughput” is defined as follows:
Throughput[b/s] =Block size (128 [bits]).
Critical path of Pipeline Stage [sec]25Copyright NTT and Mitsubishi Electric Corporation 2000-2002

6

Security

6.1

Differential and Linear Cryptanalysis

The most well-known and powerful approaches to attacking many block ciphers are differential
cryptanalysis, proposed by Biham and Shamir [BS93], and linear cryptanalysis, introduced by
Matsui [M94]. There are several methods of evaluating security against these attacks, where
there is a kind of “duality” relation between them [M95, CV95]: in other words, the security
against both attacks can be evaluated in similar ways.
It is known that the upper bounds of differential/linear characteristic probabilities can, forseveral block ciphers, be estimated using the minimum numbers of differential/linear active
s-boxes in some consecutive rounds. Kanda [K00] shows the minimum numbers of differential/linear active s-boxes for Feistel ciphers with conservative SPN (S-P) round function. Hereafter, we assume that linear transformation P is bijective.
Definition 1 The branch number B of linear transformation P is defined by
B = min(wH (x) + wH (P (x))),x6=0

where wH (x) denotes the bytewise Hamming weight of x.
Definition 2 A differential active s-box is defined as an s-box given a non-zero input difference.
A linear active s-box is defined as an s-box given a non-zero output mask value.
Theorem 1 The minimum number of differential/linear active s-boxes in any eight consecutive
rounds is equal or larger than 2B + 1.
Definition 3 For any given ∆x, ∆y, Γx, Γy ∈ GF(2m ), the differential/linear probabilities ofsi -box: GF(2m ) → GF(2m ) are defined as:#{x ∈ GF(2m )|si (x) ⊕ si (x ⊕ ∆x) = ∆y}2mm#{x ∈ GF(2 )|x · Γx = si (x) · Γy}Pr[x · Γx = si (x) · Γy] =x2m

Pr[si (x) ⊕ si (x ⊕ ∆x) = ∆y] =xDefinition 4 Let ps and qs be the maximum differential/linear probabilities of all s-boxes{s1 , s2 , . . .}.
ps = max max Pr[si (x) ⊕ si (x ⊕ ∆x) = ∆y]i∆x6=0,∆y x

qs = max max (2 Pr[x · Γx = si (x) · Γy] − 1)2iΓy6=0,Γxx

Theorem 2 Let D and L be the minimum numbers of total differential/linear active s-boxes.
L
Then, the maximum differential/linear characteristic probabilities are bounded by pD
s and qs ,respectively.

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With the above-mentioned techniques, we prove that Camellia offers immunity to these
attacks by showing the upper bounds of maximum differential/linear characteristic probabilities,
since Camellia is a Feistel cipher whose round function uses the S-P round function.
In the case of Camellia, the maximum differential/linear probabilities of the s-boxes are
ps = qs = 2−6 .
The branch number of the linear transformation (P -function) is 5, i.e.
B = 5.
Letting p, q be the maximum differential/linear characteristic probabilities of Camellia reduced
to 16-round without F L- and F L−1 -functions, respectively, we havep ≤ ps2(2B+1) = (2−6 )22 = 2−132

and q ≤ qs2(2B+1) = (2−6 )22 = 2−132

from Theorems 1 and 2. Both probabilities are below the security threshold of 128-bit blockciphers: 2−128 . It follows that there is no effective differential characteristic or linear characteristic for Camellia reduced to more than 15 rounds without F L- and F L−1 -functions. Since
F L- and F L−1 -functions are linear for any fixed key, they do not make the average differential/linear probabilities of the cipher higher. Hence, it is proven that Camellia offers enoughsecurity against differential and linear attacks.
Note that the result above are based on Theorems 1 and 2. Both theorems deal with generalcases of Feistel ciphers with SPN round function, so we expect that Camellia is actually moresecure than shown by the result above. As supporting evidence, we counted the number of active
s-boxes of Camellia with reduced rounds. The counting algorithm is similar to that describedin [M99] except following three items.
• Prepare the table for the number of active s-boxes instead of transition probability table.
• Count the number of active s-boxes instead of computing transition probability.
• F L- and F L−1 -functions set all elements to the minimum number of active s-boxes in thetable. This means that the algorithm gives consideration to existence of weak subkeys inserted to F L- and F L−1 -functions, since there may be some possibility of connecting every
later differential/linear characteristic with the previous one with the highest probability,
which is equivalent to the minimum number of active s-boxes.
As a result, we confirmed that 12-round Camellia with F L- and F L-functions has no differential/linear characteristic with probability higher than 2−128 (see Tables 10 and 11).

6.2

Truncated Differential Cryptanalysis

The attacks using truncated differentials were introduced by Knudsen [K95]. He defined themas differentials where only a part of the difference can be predicted. The notion of truncateddifferentials introduced by him is wide, but with a byte-oriented cipher it is natural to study
bytewise differentials as truncated differentials [MT99].

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Copyright NTT and Mitsubishi Electric Corporation 2000-2002# of rounds
Estimation basedon Th. 1 and 2
Camellia

1

2

3

4

2−12

2−30

5

6

7

12
2−96
(2) (5)
(7)
(11)
(16)
−6
−12
−42
−54
−66
−72
−72
−78
−108
−120
1 2
2
2
2
2
2
2
2
2
2
2−132
(0) (1) (2) (7) (9) (11) (12) (12) (13) (18) (20) (22)−1
without F L/F L - 1 2−6 2−12 2−42 2−54 2−66 2−78 2−90 2−108 2−126 2−132
functions(0) (1) (2) (7) (9) (11) (13) (15) (18) (21) (22)Note: The numbers in brackets are the number of active s-boxes.
2−42

8

9

10

11

2−66

Table 10: Upper bounds of differential characteristic probability of Camellia# of rounds
Estimation basedon Th. 1 and 2
Camellia

1

2

3

4

2−12

2−30

5

6

12
2−96
(2) (5)
(7)
(11)
(16)
1 2−6 2−12 2−36 2−54 2−66 2−72 2−72 2−78 2−102 2−120 2−132(0) (1) (2) (6) (9) (11) (12) (12) (13) (17) (20) (22)without F L/F L−1 - 1 2−6 2−12 2−36 2−54 2−66 2−78 2−84 2−108 2−120 2−132
functions(0) (1) (2) (6) (9) (11) (13) (14) (18) (20) (22)Note: The numbers in brackets are the number of active s-boxes.
2−42

7

8

9

10

11

2−66

Table 11: Upper bounds of linear characteristic probability of Camellia

The maximum differential probability is considered to provide the strict evaluation of security against differential cryptanalysis, but computing its value is impossible in general, since a
differential is a set of all differential characteristics with the same input difference and the same
output difference for a Markov cipher [LMM91]. On the other hand, a truncated differential
can be regarded as a subset of the differential characteristics which are exploitable in cryptanalysis. For some ciphers, e.g., byte-oriented ciphers, the probability of truncated differential
can be computed easily and correctly, and it gives a more strict evaluation than the maximum
differential characteristic probability.
A truncated differential cryptanalysis of reduced-round variants of E2 was presented by Matsui and Tokita at FSE’99 [MT99]. Their analysis was based on the “byte characteristic,” wherethe values to the difference in a byte are distinguished between non-zero and zero. They found a
7-round byte characteristic, which leads to a possible attack on an 8-round variant of E2 without
IT -Function (the initial transformation) and F T -Function (the final transformation). The best
attack of E2 shown in [MSAK00] breaks an 8-round variant of E2 with either IT -Function or
F T -Function using 294 chosen plaintexts. In [MSAK00] we also show the attack which distinguishes a 7-round variant of E2 with IT - and F T -Functions from a random permutation using
291 chosen plaintexts.
Camellia is a byte-oriented cipher similar to E2, and it is important to evaluate its security
against truncated differential cryptanalysis. We searched for truncated differentials using an
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algorithm similar to the one described in [MT99, MSAK00]. The main difference of the round
function between E2 and Camellia is the adoption of the 1-round SPN not the 2-round SPN,
i.e. S-P-S. In the search for truncated differentials of E2, we used about 2−8 as the probabilityof difference cancellation in byte at the XOR of Feistel network. However, the round functionof Camellia doesn’t have the second s-boxes-layer, and the cancellation sometimes occurs withprobability 1. As a result, more than 10-round Camellia is indistinguishable from a random
permutation both with/without F L-/F L−1 -function layers.
Recently, Sugita et al.’s paper on truncated and impossible differential cryptanalysis ofCamellia (without F L-/F L−1 -functions) was accepted for ASIACRYPT 2001 [SKI01]. They
claim that they found two non-trivial 9-round truncated differentials (with the same input/output
differential patterns), which lead to a possible attack of Camellia reduced to 11 rounds without
input/output whitenings and F L-/F L−1 -functions. However we think it is still open how manyrounds of Camellia can be attacked using the truncated differentials.

6.3

Truncated Linear Cryptanalysis

We introduce a new cryptanalysis called truncated linear cryptanalysis.
Due to the duality between differential and linear cryptanalysis, we can evaluate security
against truncated linear cryptanalysis by using a similar algorithm to that above. To put it
concretely, we can perform the search by replacing the matrix of P -function with the transposed matrix. As a result, more than 10-round Camellia is indistinguishable from a random
permutation without F L-/F L−1 -function layers.

6.4

Cryptanalysis with Impossible Differential

The impossible differential means the differential which holds with probability 0, or the differential which never exists. Using such an impossible differential, it is possible to narrow down thecandidates of the subkey. It is known that there is at least one 5-round impossible differential
in any Feistel network with a bijective round function. Since Camellia has the Feistel network(with F L- and F L−1 -functions inserted between every 6 rounds) and the round function is bijective, Camellia has 5-round impossible differentials. Additionally as a recent result, Sugita et al.
found a 7-round impossible differential for Camellia (without F L-/F L−1 -functions) [SKI01]. We
expect F L- and F L−1 -functions make attacking Camellia using impossible differentials difficult,since the functions change differential paths depending on key values. In consequent, Camellia
with full rounds will not be broken by cryptanalysis using impossible differentials.

6.5

Boomerang Attack

Boomerang attack [W99] requires 2 differentials. Let the probability of the differentials be p∆
and p∇ . An boomerang attack that is superior than exhaustive key search requiresp∆ p∇ ≥ 2−64 .

(6)

Using Table 10, there is no combination that satisfies Inequality (6) for Camellia without F Land F L−1 -functions. The best boomerang probability for Camellia without F L- and F L−1 functions reduced to 8-round is bounded by 2−66 that is obtained by p∆ = 2−12 (3 rounds) and29

Copyright NTT and Mitsubishi Electric Corporation 2000-2002p∇ = 2−54 (5 rounds). Since attackable rounds for Camellia without F L- and F L−1 -functions isbounded by much shorter than the specification of Camellia, 18, Camellia seems secure against
a boomerang attack.

6.6

Higher Order Differential Attack

Higher order differential attack is generally applicable to ciphers that can be represented as
Boolean polynomials of low degree. In the higher order differential attack described in [JK97,
Theorem 1], the property that if the intermediate bits are represented by Boolean polynomialsof degree at lea st d, the (d + 1)-th order differential of the Boolean polynomial becomes 0 is
utilized.
Degrees of Boolean polynomials of the s-boxes The functions affine (over GF(2)) equivalent to the inversion function in GF(28 ) are adopted as the s-boxes. It is known that the degreeof the Boolean polynomial of every output bit of the inversion function in GF(28 ) is 7, but thedegree for the s-boxes of Camellia is not trivial, since the affine functions are added at the input
and output. We confirmed that the degree of the Boolean polynomial of every output bit of thes-boxes is 7 by finding Boolean polynomial for every output bit of the s-boxes.
Degrees of Boolean polynomials of the entire cipher It is expected that the degreeof an intermediate bit in the encryption process increases as the data pass through many sboxes, whose degree is 7.
Therefore, we expect that higher order differential attacks failagainst Camellia with full rounds. However, there is still room for further study on higher orderdifferential attacks of Camellia, because there are other approaches for higher order differential
attacks. In [KK01] Kawabata et al. shows that Camellia with 10 rounds (without F L- andF L−1 -functions) can be attacked faster than exhaustive search when the key size is 256-bit.
The attack is applicable to 9 rounds for 192-bit keys and 8 rounds for 128-bit keys. Although
the above attack is titled a “higher order differential attack”, the used approach is similar tothat used for the Square attack.

6.7

Square Attack

The Square attack was proposed as a dedicated attack on Square [DKR97] that exploits its
byte-oriented structure. It works well for other byte-oriented ciphers such as Rijndael, Hierocrypt
and Camellia. For our cryptanalysis of Camellia using the Square attack, see Sect. 6.8.
The approach of Square attack resembles that of higher order differential attacks: onechooses a certain complete set of plaintexts, and after some rounds of the cipher, predicts a
key-independent property with probability one. The higher order differential attack of Camellia
by Kawabata et al. [KK01] also takes this approach.
Another Square attack by He and Qing [HQ01] on 6 rounds of Camellia was accepted
for ICICS 2001. The claimed attack on 6 rounds of Camellia requires much more complexity than Kawabata and Kaneko’s attack (the attack [HQ01] requires 2112 encryptions and theattack [KK01] 222 /6 encryptions), but fewer plaintexts (the attack [HQ01] requires 13 × 28
plaintexts and the attack [KK01] 217 plaintexts).

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6.8

Interpolation Attack and Linear Sum Attack

The interpolation attack proposed in [JK97] is typically applicable to attacking ciphers that use
simple algebraic functions.
The principle of interpolation attack is that, roughly speaking, if the ciphertext is represented
as a polynomial or rational expression of the plaintext whose number of unknown coefficientsis N , the polynomial or rational expression can be constructed using N pairs of plaintexts andciphertexts. Once the attacker constructs the polynomial or rational expression, he can encrypt
any plaintext into the corresponding ciphertext or decrypt any ciphertext into the corresponding
plaintext for the key without knowing the key. Since N determines the complexity and thenumber of pairs required for the attack, it is important to make N as large as possible. If N is
so large that it is impractical for the attackers to gather N plaintext-ciphertext pairs, the cipher
is secure against interpolation attack.
Linear sum attack [A00] is a generalization of the interpolation attack [JK97]. A practicalalgorithm that evaluates the security against linear sum attack was proposed in [A00]. We
searched for linear relations between any plaintext byte and any ciphertext byte over GF(28 )using the algorithm. Table 12 summarizes the results.
Table 12: Smallest number of unknown coefficients for 128-, 192-, and 256-bit keys
whitening×1 + round×r (r < 4)whitening×1 + round×4
More rounds

1
255
256

Table 12 shows that Camellia is secure against linear sum attack including interpolation
attack. It also implies that Camellia is secure against Square attack [DKR97] followed by [A00,
Theorem 3].

6.9

No Equivalent Keys

Since the set of subkeys generated by the key schedule contain the original secret key, there
is no equivalent set of subkeys generated from distinct secret keys. Therefore, we expect that
there are no distinct secret keys both of which encrypt each of many plaintexts into the same
ciphertext.

6.10

Slide Attack

In [BW99, BW00] the slide attacks were introduced, based on earlier work in [B94, K93]. In
particular it was shown that iterated ciphers with identical round functions, that is, equal
structures and equal subkeys in the round functions, are susceptible to slide attacks.
In Camellia, F L- and F L−1 -functions are “inserted” between every 6 rounds of a Feistel
network to provide non-regularity across rounds. Moreover, from the viewpoint of the keyschedule, slide attacks seems to be very unlikely to succeed (See Section 6.11).

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6.11

Related-key Attack

We are convinced that the key schedule of Camellia makes related-key attacks [B94, KSW96] very
difficult. In these attacks, an attacker must be able to get encryptions using several related keys.
If the relation between, say, two keys, is known then if the corresponding relations between thesubkeys can be predetermined, it might become possible to predict how the keys would encrypta pair of different plaintexts. However, since the subkeys depend on KA and KB , which are theresults of encryption of a secret key, and if an attacker wants to change the secret key, he can’t
get KA and KB desired, and vice versa, these subkey relations will be very hard to control andpredict.

6.12

Statistical Tests

Most of statistical characteristics depends on the differential attack and other cryptanalytic
attacks. For example, it is frequently discussed how many ciphertext bits are complemented
when one plaintext bit is complemented. According to the definition and the property of thedifferential distribution table, the resistance to differential attacks implies that the number ofcomplemented bits is about a half. Of course, we may find a statistical weakness, if we haveenough computational resource. However, none in the world has an efficient resource to compute
such a statistical measure for a 128-bit block cipher.
Note that the following. It is frequently tested for a round function, because of the limited
computational resource. However, we think that it is not significant, because we can constructa cipher that does not show good statistical properties for the round function but shows good
statistical properties for a cipher and we can also construct a cipher that shows good statisticalproperties for the round function but does not show good statistical properties for a cipher.
In the CRYPTREC Report 2000 [C01], it is reported that the avalanche-effect evaluation on
Camellia was held and that they found some points which deviate from the expected value inthe round function, but no particular characteristics in the data-randomizing part after the 4thround.

6.13

Implementation Attacks

It is well known that a poor implementation can leak information by timing attacks [K96] orpower analysis attacks [KJJ99]. Using the classification proposed in [DR99], Camellia is in thegroup of “favorable” algorithms, since it uses only logical operations and table-lookups and fixedrotations.
On the other hand, Chari et al. [CJRR99] claims that all AES candidates are susceptible topower analysis attacks. As these two papers contradict with each other, how to resist against
power analysis attacks is not known, since study on power analysis attacks has just begun. We
think that Camellia should be protected by the hardware techniques and should not be evaluatedby the security directly derived from the specification, considering the current art. We hope thatthe study on implementation attacks will be progressed in the near future.

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6.14

Brute Force Attacks

Most brute force attacks are applicable to any deterministic block cipher, and the corresponding
complexity depends on only the block size or key size∗ , regardless of its design. Camellia has
a block size of 128-bit and allows for the three key sizes of 128-, 192-, and 256-bit. In thediscussions below, k denotes the key size in bits.
Exhaustive key search. In exhaustive key search, if an attacker gets one pair of plaintext
and ciphertext encrypted in ECB mode, he can find the correct key by encrypting the plaintext
with all 2k possible keys.
A weakness in the key scheduling of the cipher can help improve the efficiency of exhaustive
key search attack [K94], but we have not found such a weakness in Camellia. The complexityof the exhaustive key search is estimated to be about 2k−1 encryptions on average. Thus, therequired complexity for exhaustive key search is 2127 , 2191 , and 2255 encryptions for Camellia
with 128-, 192-, and 256-bit keys, respectively. Therefore, Camellia’s security against exhaustive
key search is adequate.
Time-memory trade-off attack. There are some words that are often used in plaintexts.
If an attacker encrypts such a plaintext block using 2k keys and store them in space for 2k
ciphertexts, then after he gets the corresponding ciphertext, he only has to look it up to findthe corresponding key. This attack is called table attack. In this attack, after 2k encryption isdone, the attack complexity is much smaller than is true for exhaustive key search.
Time-memory trade-off attack [H80, KM96] can drastically reduce both time complexity on
intercepted ciphertexts of exhaustive key search and space complexity of table attack. However,both attacks require precomputation equivalent to the time complexity of exhaustive key search.
The key sizes supported by Camellia are long enough for security against exhaustive key searchby today’s technology.
Dictionary attack. In dictionary attack, an attacker collects plaintext-ciphertext pairs under
the same key and put them in a “dictionary”. When the attacker can see only a ciphertext
encrypted by the key, he can check if it is in the dictionary. If it is, he has already the plaintext.
Since the block size of Camellia is 128 bits, dictionary attack would require the space for 2128
different plaintext blocks to allow the attackers to encrypt or decrypt arbitrary messages underan unknown key. The success probability depends on the space for the dictionary, and as
the block size is larger, the required space to achieve the same success probability increases
exponentially. The 128-bit block cipher Camellia has enough security against this attack.
Matching ciphertext attack. In matching ciphertext attack [K98, Theorem 2], when about
the square root of all ciphertexts are available identical ciphertext blocks can be expected withprobability more than 12 by the “birthday paradox” for some modes of operations such as ECB,
CBC, and CFB modes. Then, valuable information about the plaintexts can be derived. Note∗

Strictly speaking, the computation time required for the attack depends on the performance of the blockcipher. However, the performance only affects the encryption time and only changes the time complexity by
negligible factor.

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that this attack is independent of the key size. Since the block size of Camellia is 128 bits, thethreat to this attack is small, if encryption of as many as 264 blocks under the same key is not
performed.

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7

Conclusion

We have presented Camellia, the rationale behind its design, its suitability for both softwareand hardware implementation, and the results of our cryptanalyses.
The performances shown in this paper leave room for further optimizations. The latest
performance results will be posted on the Camellia home page: http://info.isl.ntt.co.jp/
camellia/.
We have analyzed Camellia and found no important weakness. The cipher has a conservative
design and any practical attacks against Camellia would require a major breakthrough in thearea of cryptanalysis. We think that Camellia is a very strong cipher, which matches the securityof the existing best block ciphers.

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K. Aoki. Practical Evaluation of Security against Generalized Interpolation Attack.
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[ABK98]R. Anderson, E. Biham, and L. Knudsen. Serpent: A Flexible Block Cipher With
Maximum Assurance. In The First AES Candidate Conference, 1998.

[AIK+ 00a] K. Aoki, T. Ichikawa, M. Kanda, M. Matsui, S. Moriai, J. Nakajima, and T. Tokita.
Implementations of the 128-bit block cipher – Camellia –. Technical Report
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[AU00]

K. Aoki and H. Ueda. Optimized Software Implementations of E2. IEICE
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[B94]

E. Biham. New Types of Cryptanalytic Attacks Using Related Keys. Journal of
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[BS93]

E. Biham and A. Shamir. Differential Cryptanalysis of the Data Encryption Standard. Springer-Verlag, Berlin, Heidelberg, New York, 1993.

[BW99]

A. Biryukov and D. Wagner. Slide Attacks. In L. Knudsen, editor, Fast Software
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[BW00]

A. Biryukov and D. Wagner. Advanced Slide Attacks. In S. Vaudenay, editor,
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[C98]

Compaq Computer Corporation.
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Copyright NTT and Mitsubishi Electric Corporation 2000-2002[CJRR99] S. Chari, C. Jutla, J. R. Rao, and P. Rohatgi. A Cautionary Note Regarding Evaluation of AES Candidates on Smart-Cards. In Second Advanced Encryption Standard
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[CV95]

F. Chabaud and S. Vaudenay. Links Between Differential and Linear Cryptanalysis. In A. D. Santis, editor, Advances in Cryptology — EUROCRYPT’94, Volume
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[DKR97]

J. Daemen, L. R. Knudsen, and V. Rijmen. The Block Cipher Square. In E. Biham,
editor, Fast Software Encryption — 4th International Workshop, FSE’97, Volume1267 of Lecture Notes in Computer Science, pp. 54–68, Berlin, Heidelberg, New
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[DR98]

J. Daemen and V. Rijmen. AES Proposal: Rijndael, 1998. (http://www.esat.
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Copyright NTT and Mitsubishi Electric Corporation 2000-2002

A

History

Ver 2.1 (February 18, 2002)• Font problems in pages 8–10 were fixed. (It was not able to be printed from non-Japanese
printers.)• Hardware performance in Table 3 in Section 3 was updated.
• Abstract was renewed with the latest performance figures.
• In Section 1, “Standardization activities” was updated.
Ver 2.0 (September 26, 2001)• Abstract was renewed with the latest performance figures.
• Section 1, the paragraph of “Future developments” was renewed based on the current
status. The title was also changed into “Standardization activities”.
• Section 3 was renewed with the latest performance figures.
• In Section 4.2.7, the equation to calculate Eq.(3) using only four tables, SP1 , SP2 , SP3 , SP4 ,was corrected.
• Section 5 was renewed by adding the latest information on hardware evaluations.
• In Section 6.1 (Differential and Linear Cryptanalysis), an erratum in Table10 “Upper
bounds of differential characteristic probability of Camellia” (in the row of “without
F L/F L−1 -functions”) was fixed.
• Section 6.2 (Truncated Differential Cryptanalysis) was renewed by adding the recent result.
• Section 6.4 (Cryptanalysis with Impossible Differential) was renewed by adding the recent
result. An erratum was also fixed: “more than 6 rounds” → “more than 5 rounds”• Section 6.6 (Higher Order Differential Attack) was renewed based on the recent result.
• Section 6.7 (Square Attack) was added.
• Section 6.12 (Statistical Tests) was renewed by adding more information.

41