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2006 Kyoto Univ.

核整列固体3Heの世界一クールなMRI像(500µK)       

2016 Kyoto Univ.

超流動3Heのカイラルドメイン構造のMRI像
Kasai et al. Phys. Rev. Lett. (2018) 

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2016 Kyoto Univ.

Pair Annihilation during Annealing
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Compact MRI magnet and 100µm gap Parallel Plate Cell
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FIG. 1. CAD image of a typical H1 device. No substrate is shown in thisfigure. The springs also serve as electrical connections from the center plateto the external bonding pads on the chip.

using a specialized CAD software called L-Edit. The designs
were then sent to the company for fabrication. In this process, the following layers are deposited on the substrate: threepolysilicon layers (Poly0, Poly1, Poly2) used as the structural
material, one silicon nitride layer (Nitride) used for electricalisolation from the substrate, two phosphosilicate glass (PSG)
layers (first and second oxide) as sacrificial layers, and a metallayer (METAL) used for improved electrical connectivity. The
label, material, and thickness of each layer patterned on thewafer is listed in Table I. The process is carried out on 100 mmwafers (1–2 ! cm) and it starts by heavily doping the surface with phosphorus (9–10 !/sq). The layers are depositedusing low pressure chemical vapor deposition (LPCVD) andpatterned by a combination of photolithography and reactive

9=xmzSur8 wm%Q *ZMEMSRev. Sci. Instrum. 84, 025003 (2013)

FIG. 1. CAD image of a typical H1 device. No substrate is shown in thisfigure. The springs also serve as electrical connections from the center plateto the external bonding pads on the chip.

using a specialized CAD software called L-Edit. The designs
were then sent to the company for fabrication. In this process, the following layers are deposited on the substrate: threepolysilicon layers (Poly0, Poly1, Poly2) used as the structural
material, one silicon nitride layer (Nitride) used for electricalisolation from the substrate, two phosphosilicate glass (PSG)
layers (first and second oxide) as sacrificial layers, and a metallayer (METAL) used for improved electrical connectivity. Thelabel, material, and thickness of each layer patterned on thewafer is listed in Table I. The process is carried out on 100 mmwafers (1–2 ! cm) and it starts by heavily doping the surFIG. 2. SEM pictures of a typical device. An overall view of an H2 device
facewithin phosphorus(9–10
are ofdeposited
is shown
the top left figure.
The !/sq).
top rightThefigurelayers
shows half
the sameusingpressuredevice.low
The bottom
left chemical
figure showsvapor
a moredeposition
detailed view(LPCVD)of the springandofan H1 device
anchor point withthe substrate. A close andup lookat thepatterned
byataitscombinationof photolithography
reactivecomb-electrode fingers is displayed in the bottom right figure.
ion
etching (RIE). PSG is used in the process to dope the different Poly layers with phosphorus by annealing the wafer at◦
C inargontoduring
different
stepstheofpolysilicon
the process.
The1050
prevents
damagethe device
becausestructypicalresistivityof a Poly1Afterlayerdicing,is 2.61the× devices
10−3 ! werecm. Aftertures arenot yet movable.
“redepositing
andapatterning
allprocedure.
the necessary
to create
theleased” using
wet etching
Thislayers
removesthe sacstructures,
thelayers
resultingto the customer.
Morerificial PSG
and chips
frees arethe sentmechanicallyactive parts.
details
can befound suggested
in the design
handbook
company’s
A standard
processby thefoundryatisthefollowedfor
13
website.
releasing.13 The etching is done by immersing the chips inThe
die
received
fromthefoundrywasdiced
intosmaller
49% hydrofluoric acid for 7 min. After the release process, ifsquarechips∼2.5 tommusing
a diamondsaw.
the chips
are ofalloweddrysideby length
exposure
to theenvironment,
Duringthisplates
procedure,
the devices
were still
coatedby a phothe small
comprising
the devices
might
be pulled
totoresist
layer,otherand bythecapillary
sacrificial
layerandwasstickstilltogether.
present. ThisThis
wards eachactionphenomenon is called stiction. To avoid this problem the chips
were dried using a CO critical point dryer. After drying,
the chips were packaged in a custom designed 20-pin socket.

2TABLE I. Thickness of the different
layers used in PolyMUMPs.

FIG. 2. S
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device. Th
an H1 dev
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preventstures areleased”
rificial P
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