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Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. Other names and brands may be claimed as the property of others.

AND90011/D
NCP1618 Tips and Tricks

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Introduction

The NCP1618 is designed to feature most functions
required when designing a PFC stage. However, designers
often have unique specifications and needs to address, that
may require the addition of specific circuitries around thecontroller. Also, some functions can be utilized in different
manners depending on the application. This document
addresses questions that can be raised when developing a
NCP1618−driven PFC stage. More specifically, thefollowing topics are covered:
1. Soft−SKIP control
2. Optimizing zero current detection and redundantOVP

APPLICATION NOTE
• Idle phase: At the end of the active part of the burst, thecircuit enters a deep idle phase for which no DRV
pulses are generated. In addition, all non−necessary
circuitries are turned off so that the circuit consumption
is reduced to a minimum (250 mA typically). During
this phase, the output voltage decays and the circuit
resumes operation when the output voltage has dropped
below 98% of the regulation level (98% × Vout,nom).

Figure 1 shows typical waveforms obtained in soft−SKIP
mode using the NCP1618 500 W evaluation board [1].
Negative pulses were applied to the pfcOK pin to set thesoft−SKIP mode. The frequency of the pulses was 25 Hz.
The duration of the idle phase depends on the bulk
discharge speed and hence, on the load. In very light load, it
is far the longest phase. However, the burst period remains
relatively constant over the line range.

Soft−SKIP Control

The NCP1618 is designed to enter the soft−SKIP mode atvery light load. Soft−SKIP minimizes losses by forcing avery low frequency burst−mode of operation consisting of
two sequences:• Charge phase: during the active part of the burst, theoutput voltage (VBULK) charges up to 103% of thenominal value (103% × Vout,nom), where Vout,nom is
output voltage nominal voltage.

VBULK

20 s

V BULK

20 s

ILINE

ILINE

V pfcOK

VpfcOK

VM

VMa) 115 V, 60 Hzb) 230 V, 50 Hz

Figure 1. Soft−SKIP Operation in Low− (Left) and High−line (Right) Conditions

Figure 2 details the active part of the burst. At high line,
the bulk voltage recharges faster. However as attested by theVM pin voltage, the circuit does not recover the deep idle

© Semiconductor Components Industries, LLC, 2020

February, 2020 − Rev. 0

mode until a pfcOK negative pulse confirms the soft−skip
mode.

1

Publication Order Number:AND90011/D

AND90011/D

VBULK

VBULK
40 ms

40 ms

ILINE

ILINE

VpfcOK

VpfcOK
VM

VMa) 115 V, 60 Hzb) 230 V, 50 Hz

Figure 2. Active Part of Soft−SKIP Operation in Low− (Left) and High−line (Right) Conditions

ms maximum). A signal from the downstream converter istypically used to generate it. As an example, the PFC stage
can be loaded by a LLC converter driven by
ON Semiconductor NCP13992 [2]. This controller featuresa Pmode pin which remains permanently high in normal
operation. In light load, the NCP1392 enters skip mode tominimize the losses. In this case, the Pmode pin voltage ishigh when the LLC converter operates and low when it skips
cycles. The interface circuit of Figure 3a), consisting of a R,
C, a signal diode and of a Zener diode, can be used to force
the PFC into soft−SKIP using the Pmode signal. Note that
an R, C filter may have to be added. This is because the
pfcOK pin is generally applied to the brown−out input of the
LLC controller. If the brown−out protection features no or
too small a blanking time, the negative pulse may cause theprotection to trip. R2 and C3 of Figure 3a) must prevent this.

For limiting the risk of audible noise, each charge phasefinishes by a soft−stop sequence (gradual diminution of theline current). If the charge phase happens to cause an
overshoot that triggers the over−voltage protection, still thesoft−OVP 4−step stop of operation provides a softinterruption of the power delivery.
Soft−SKIP and CCM mode
The circuit cannot enter soft−SKIP as long as it operates
in CCM.
In addition, the circuit is prevented from entering theCCM mode during a soft−SKIP burst. However, if an abrupt
load change causes the feedback voltage to drop below the
dynamic response enhancer level (95.5% of the 2.5 V
regulation voltage reference), the NCP1618 can enter the
CCM mode, provided that the VM pin is above its soft−SKIP
threshold (VSKIP(th) which is 1.5 V typically).
How to Set the Soft−SKIP mode?
A negative pulse must be applied to the pfcOK pin to force
the pin below VSKIP2 (0.4 V min) for longer than TSKIP2 (33Neg. pulses filtering (optional)
R2
10k

NCP13992
BO PinInterface circuitry

C3
10nF

NCP1618
pfcOK Pin

D2
1N4148

R1
56k

C2
10nF

C1
10nF

NCP1618
VM Pin

R3
470

a)

C3
2.2nF

R1
6.8k

C2
10nF

C1
10nF

R3
470

NCP13992
Pmode Pin

D3
4.7V

D3
4.7V

Interface circuitry

NCP1618

NCP13992
Pmode Pin

D2
1N4148R2
1k

NCP1618

NCP13992

NCP13992b)

Using the NCP1618 pfcOK pin

Using the NCP1618 VM pin

Figure 3. Controlling the Soft−SKIP Mode

As shown by Figure 3b), another option consists ofapplying the negative pulses to the VM pin instead of the
pfcOK. In this case, the pulses must be sized so that the VM
pin drops below VSKIP(th) (1.2 V min) for longer than 100 ms.

NOTE: The values provided in Figure 3 for thecomponents of the ”interface” and ”neg. pulses
filtering” circuitries are indicative only. They
may have to be tweaked in accordance with thespecific conditions of any particular application.

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2

AND90011/D• A second comparator trips if the pin voltage exceeds

Optimizing Zero Current Detection and Redundant
OVP

VOVP2 of 4 V typically. In this case, an OVP2 isdetected leading to a 800 ms interruption of the PFC
operation. If in addition, the FB voltage is detected
below VDRE−L , that is, below the DRE lower threshold(1) when the OVP2 protection trips, a failure of the
feedback network is detected causing the circuit to latch
off.

This pin is designed to monitor a signal from an auxiliary
winding and to detect the core reset when this voltage drops
to zero. This function ensures valley turn on indiscontinuous and critical conduction modes (DCM and
CrM). The pin can also be used to detect an over−voltage
condition of the bulk voltage, hence offering a redundant
OVP protection.
Figure 4 shows how the two functions are performed:• A comparator compares the pin voltage to the VZCD(th)Hand VZCD(th)L thresholds (which typical value is 1.0 V
and 0.5 V respectively) for zero current detection+−

Ics < Iinrush

S

VZCD(th)H/ VZCD(th)LQ

fsw,min

DT

S
Q
Q

Q

ramp

R
R

reset
ZCD / OVP2

DRV

OVP2
800 ms interruption

+
−

VOVP2
Latch−off

VFB <VDRE−L

Figure 4. ZCD and OVP2 Block

Dissipative ZCD/OVP2 External Networks
Figure 5 illustrates a relatively straightforward utilizationof the ZCD/OVP2 pin.
When the auxiliary winding voltage is high like it happens
during the demagnetization phase, diode D1 is blocked andthe pin receives the following portion of the bulk voltage:
V ZCDńOVP2 +

R4R1 ) R2 ) R3 ) R4

V BULKV ZCDńOVP2(V aux + 0 V) +R4R3 ) R4

V F, D1(eq. 2)

Figure 5a) circuitry thus provides the signal necessary for
ZCD. In addition, the OVP2 protection trips when the pin
voltage exceeds 4 V typically. In our case, this will happen
when the bulk voltage goes above (VBULK)OVP2 defined by
the following equation:(eq. 1)(V BULK)

When Vaux is negative (during the on−time) or ringing
around zero (dead−time), diode D1 turns on, thus clamping
the D1 anode voltage to a low value. Resistor R3 is placed sothat the ZCD/OVP2 voltage is below VZCD(th)L (0.5 V
typically) when the auxiliary winding is zero:

OVP2

+

510

10 3 ) 510

10 3 ) 27
10 3

1010 3 ) 10

10 3

4 ^ 423V(eq. 3)Figure 5b) differs from Figure 3a) in the addition of a filter(R5 , C2 ) which can be necessary to get rid of the noise
brought by the parasitic capacitor of diode D1 .

1. The NCP1618 embeds a “dynamic response enhancer” circuitry (DRE) which firmly contains under− shoots by 10x increasing the loop
gain when the feed−back voltage drops below 95.5% of its nominal value and until the output voltage has recovered up to 98.0% of its
nominal value.

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3

AND90011/Da) Basic Circuitryb) With an R, C filter (R5, C2)

Figure 5. ZCD/OVP2 Circuit where the Bulk Voltage is Sensed for Redundant OVP

Important notes:• When the MOSFET is on, the auxiliary winding
voltage is negative and equal to (–N×Vin ). Thus thevoltage Vdemag of Figure 5a) is also (–N×Vin ) if weneglect D1 voltage drop. It is hence necessary to selectR3 high enough not exceed the −2 mA, +5 mA max
ratings of the ZCD pin (see data sheet). Practically, R3
should be selected higher than (N×Vin,max / 2 mA). For
instance, if N is 0.1 and Vin,max is 400 V, resistance R3
must be greater than (0.1×400/(2×10−3)) that is 20 kΩ.
• Signal Vdemag of Figure 5a) is clamped to Vaux by D1 .
During the off−time, the ZCD/OVP2 voltage is thenclamped to (N(VBULK −Vin )+VD1 ). Hence, when the
difference between the bulk and input voltages issmaller than the OVP2 threshold, OVP2 cannot trip.
Practically, if N is 0.1, the OVP2 will not be able to trip
when (VBULK −Vin ) is less than 40 V

noise and D1 parasitic capacitor since the pin cannot beheavily filtered (not to delay the zero current or valley
detection).
Figure 6a) provides a non−dissipative alternative solution
where the bulk voltage is not sensed directly but instead
reconstructed. Practically, charge pump R1, C2, D2, D3 andC2 builds N×VBULK where N is the turns ratio (auxiliary
winding number of turns / primary number of turns).
Capacitor C3 is referenced to Vo which can simply be groundor preferably VCC so that a voltage exists at startup for proper
ZCD.
The OVP2 protection trips when the pin voltage exceeds
VOVP2 (4 V typically), that is, when:
R4R2 ) R3 ) R4N

V BULK + V OVP2

(eq. 4)R2 ) R3 ) R4
R4(eq. 5)Thus, the OVP2 threshold is:(V BULK) OVP2 +Non Dissipative ZCD/OVP2 External Networks
Circuitries of Figure 5 may dissipate too much a power inapplications where stringent standby requirements are to be
met. As an example, Figure 5 circuitry consumes (VBULK 2 /(R1+R2+R3+R4)), i.e., about 150 mW if the output voltage
nominal voltage is 400 V. The impedance of the resistors’
divider can be increased to some extent, by two for instancebut careful attention must be paid to layout, surrounding

V OVP2N

If (N=1/10), it comes:(V BULK) OVP2 +

4
0.1

68

10 3 ) 27
10

10 3 ) 10
10 3

10 3

^ 420 V(eq. 6)

Again Figure 6b) differs from Figure 6a) in the additionof a filter (R5, C2) which can be necessary to get rid of thenoise brought by diode D1 parasitic capacitor.

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4

AND90011/Da) Basic Circuitryb) With an R, C filter (R5, C4 )Figure 6. ZCD/OVP2 Circuit where the Bulk Voltage is Reconstructed from the Auxiliary Winding

Note that if OVP2 is not useful, the simple circuit of
Figure 7 can be used. A 3.3 V Zener diode is added to prevent
the ZCD/OVP2 pin from reaching the OVP2 threshold andtriggering the OVP2 protection. Capacitor C1 is optional. It
can be implemented to delay the ZCD signal if necessary todetect the very valley of the MOSFET drain−source voltage.

Figure 7. ZCD Circuit without OVP2

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5AND90011/D
Improving High−line Zero Current Detection
As sketched by Figure 8, the auxiliary winding gives ascaled version of the inductor voltage which is easily usableby the controller. The PFC stage being a boost converter, this
auxiliary winding voltage provides:
⎛N

⎛N
⎝

⎞

P

⎠

P

This voltage used to detect the zero current detection
can be small when the input voltage is nearly the output
voltage• A voltage oscillating around zero during dead−times• − ⎢ NAUX ⋅ vin (t )⎟ during the MOSFET conduction time⎝⎞• ⎢ NAUX (VBULK − vin (t ))⎟ during the demagnetization time.

⎠

DRV
time

VIN

VDS

time
⎛ N AUX⎞(VBULK − vin (t ))⎟
⎢
N
⎝ P
⎠

VAUX

time

⎛N
⎞
− ⎢ AUX ⋅ vin (t )⎟⎝ NP⎠

Figure 8. Auxiliary Winding Signal

The voltage

ZCD more inaccurate at very high line. This effect can be
mitigated by replacing the upper resistor of the resistors
divider by a diode.
Figure 9 shows this modification for Figure 6. Note thatthe upper resistor R2 has to be adapted and that taking into
account for diode D4 , the OVP2 threshold is now:N AUX
(VBULK − vin (t )) is compared to the ZCD
NP

internal thresholds. At very high line, this voltage can be too
small to be detected, causing the circuit to operate at theminimum frequency since the minimum frequency ramp
provides the timeout signal. Even, due to the input voltage
ripple, the ZCD comparator may trigger and turn low too
early making the ZCD function inaccurate.
In circuits of Figure 5 to Figure 7, the ZCD voltage isclamped to the auxiliary winding voltage by diode D1. Morespecifically, the D1 anode voltage is scaled down by aresistors divider before being applied to ZCD pin making the(V BULK) OVP2 +ǒV OVP2R2 ) R4

N

R4

Ǔ

)

V F*D

4

N

(eq. 7)This is in our case:(V BULK) OVP2 +www.onsemi.com
6

ǒ0.14

Ǔ

100 ) 100.65)
^ 446 V100.1

(eq. 8)

AND90011/D

Figure 9. Improved Circuitry for Very High Voltage Operation

Important Remarks
Whenever the circuit must resume operation (cold startup
or recovery after an interruption) and whenever no ZCD is
detected within a cycle, the circuit monitors the ZCD/OVP2
pin impedance and prevents operation if too low. Practically,
the NCP1618 sources a current of 250 mA (typical value) andno DRV pulses are generated until the pin voltage exceeds
the upper ZCD threshold VZCD(th)H . Thus, the NCP1618 isinhibited if the ZCD/OVP2 pin is accidently grounded
which helps pass safety tests. Not to inappropriately trigger

the protection, the ZCD/OVP2 external network must be
selected so that the ZCD/OVP2 pin impedance exceeds
7.5 kW.
Components values given in above figures are indicative
only and only proposed to ease explanations. They may haveto be tweaked to meet practical specifications (OVP2threshold for instance) or specific conditions (different
auxiliary winding turns ratio). Note also that there is someflexibility in the selection of some components like thecharge pump or filter ones.

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7AND90011/D
References[1]. EVBUM2716/D, NCP1618 Evaluation Board
User’s Manual,
http://www.onsemi.com/pub_link/Collateral/
EVBUM2716−D.PDF[2]. “High Performance Current Mode Resonant
Controller with Integrated High−Voltage Drivers”,

NCP13992 data sheet,https://www.onsemi.com/pub/Collateral/NCP1399
2−D.PDFON Semiconductor andare trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are notdesigned, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, andexpenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if suchclaim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.

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