Selected Papers

A Wideband RF Chipset for Multi-band
Direct Conversion Transceivers
Munenari Kawashima†, Tadao Nakagawa,
Hitoshi Hayashi, and Kenjiro Nishikawa
Abstract
In a software-defined radio, the RF (Radio-Frequency) front-end must cope with multi-band radio signals. Therefore, we developed a wideband RF chipset for multi-band direct conversion transceivers. The
chipset consists of a wideband quadrature mixer, a wideband low-noise variable-gain amplifier(LNVGA), and a multi-band local oscillator. The mixer achieves its wideband performance through theincorporation of newly developed power dividers. The LNVGA attains its wideband performance without the use of reactance elements. It also has high linearity due to a feedback circuit using two anti-series
field-effect transistors. The local oscillator is able to cover the frequency bands of three systems, including a frequency-division duplexing system, while using only two voltage-controlled oscillators.

1. Introduction
There are currently various mobile communication
standards in use worldwide. Software-defined radio(SDR) enables the creation of multi-standard terminals, which can be flexibly used in various mobile
communication systems by simply rewriting theirsoftware [1]. However, to be compatible with different systems, the transceiver must be able to deal withvarious frequency bands. It is difficult to make transceivers with a superheterodyne architecture compatible with various systems, however, because suchtransceivers have IF (Intermediate-Frequency) channel filters and image-rejection filters that cannot be
programmed to change the frequency band. In contrast, transceivers with a direct conversion architecture do not require IF-channel filters or image-rejection filters because they convert RF (Radio-Frequency) signals directly to baseband signals [2]. Thus, thedirect conversion architecture is much more promising for designing a transceiver for SDR.
Transceiver components such as power dividers,phase shifters, local oscillators (LOs), and amplifiers† NTT Network Innovation Laboratories
Yokosuka-shi, 239-0847 Japan
E-mail: kawashima.munenari@lab.ntt.co.jp

Vol. 1 No. 4 July 2003

must also be capable of wideband performance tocover the frequency bands of various systems.
Although quadrature mixers using a 45º phase shifterfor direct conversion transceivers have been reported[3], [4], there have been no reports of a 45º phaseshifter that is compatible with wideband transceivers.
In this paper, we report on a wideband RF chipset
for multi-band direct conversion transceivers that iscompatible with three systems; the personal digitalcellular (PDC), the PHS (Personal Handy-phone System) and the 2.4-GHz wireless LAN (WLAN). Thischipset is based on a design that incorporates a quadrature mixer, a low-noise variable gain-amplifier(LNVGA), and a local oscillator [5]-[7]. We showthat these components are suitable for frequencywidening applications in mobile transceivers and discuss the measurement results we obtained from
MMICs (Monolithic Microwave Integrated Circuits)that we fabricated.
2. Transceiver configuration
Figure 1 shows a block diagram of the multi-banddirect conversion transceiver. The same type of quadrature mixer was used for both the demodulator andthe modulator. Therefore, they were able to share alocal oscillator. The target systems were PDC, PHS,
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Antenna

Fabricated chip-set
BasebandI output
Quadrature
mixer(demodulator)
BasebandQ output

LNVGA

Local
oscillator
Antenna
BasebandI input
Quadrature
mixer(modulator)
PA

BasebandQ input

Fig. 1. Block diagram of the multi-band direct conversion transceiver.

and a 2.4-GHz WLAN. The first is an FDD (Frequency-Division Duplexing) system and the second
and third are TDD (Time Division Duplexing) systems. Therefore, the target frequency range was from
0.9 to 2.5 GHz.
3. Quadrature mixer
The quadrature mixer consisted of two anti-parallel
diode mixers, a 45º power divider, an in-phase power

divider, and two differential amplifiers, as shown in
Fig. 2. Use of the direct conversion architecture had
two disadvantages: second-order distortion and DC
offset. However, it was possible to eliminate them byusing the anti-parallel diode mixers [8]. Such mixers,which connect diodes that have the same characteristics in parallel in reverse, do not output even-ordersignals. Consequently, the second-order distortionand DC offset equivalent to zero-order distortion
were suppressed. Moreover, the anti-parallel diode

BasebandI channel

Differential
amplifierRFIn-phase
power
divider45°
power
divider

Anti-parallel
diode mixer

LO

Differential
amplifierBasebandQ channel

Fig. 2. Circuit configuration of the quadrature mixer.

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mixers are even-harmonic mixers, which use LO signals whose frequency is half that of the RF signals.
The mixers have a balanced configuration thatenables them to obtain RF-to-LO isolation in a wide
frequency range [9]. To generate in-phase and quadrature signals, we used a 45º phase shifter in the LO
power divider. Our design targets for amplitude balance and quadrature phase error were less than 2 dB
and 4º, respectively.

Equation 1 shows that the phase characteristics ofthe band-pass filter had one inflection point as a function of the frequency. Equation 2 shows that the phasecharacteristics of the high-pass filter decreased
monotonically as a function of the frequency. Therefore, because the phase difference between ports 2
and 3 in Fig. 3(a) had at most two extreme values, this
divider was capable of wideband performance.
Figure 3(b) shows the S-parameter simulation
results. The lumped passive elements were set so thatthe amplitude difference was 0 dB and the phase difference was 45º at 1.0 GHz. The phase difference had
two extreme values. Hence, this divider exhibited
wideband performance.

3.1 The 45º power divider
Figure 3(a) shows the circuit configuration of the
proposed 45º power divider, which included a compensation capacitor (C1) and a compensation resistor(R2). The 45º power divider consisted of a band-passfilter and a high-pass filter using resistance-capacitance networks. Phase θb(ω) of the band-pass filter,
which consisted of C1, C3, and R1, is given by(1)

Phase θh2(ω) of the high-pass filter, which consisted of C2, R2, and R3, is given byeθ h 2 (ω ) = tan −1,
d ×ω
d = 1 + (Zs + R2) × (1/Zl + 1/R3),
e = (1/Zl + 1/R3) / C2.

(2)

90
60

R1

C3

Port 1

Port 3R2

C2

R3

Phase (S21, S31) [deg]Port 2C1

60
Phase (S21)
Phase (S31)
Phase difference

55

30

50

0

45

–30

40

–60

35

–90

30
0

(a)

Phase difference [deg]θ b (ω ) = tan −1 − b × ω + c ,aa ×ωa = 1 + (Zs + R1) / Zl + C3 / C1,
b = (Zs + R1) × C3,
c = (Zl × C1).

3.2 In-phase power divider
Figure 4(a) shows the circuit configuration of thein-phase power divider, which included a compensation capacitor (Cc). Under even-mode excitation, this
divider is a fifth-order high-pass filter. Thus, reflection characteristic S11 had at most two minimum values. Reflection characteristic S22 and isolation characteristic S32 also had at most two minimum values.
This is because the resonant point increased as aresult of adding the compensation capacitor. This
divider thus satisfied the matching conditions at two
frequencies, which enabled it to also achieve wideband performance.
Figure 4(b) shows S-parameter simulation results
for the in-phase power divider. The lumped passive
elements were set so that the matching conditions
were satisfied at 0.8 and 1.2 GHz. The divider’s S11,
S22, and S32 each had two minimum values and thus

12Frequency [GHz]

3

4

(b)

Fig. 3. 45º power divider: (a) circuit configuration and (b) simulated S-parameters.

Vol. 1 No. 4 July 2003

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0–10
S-parameter [dB]

Port 2

Port 1
Cc

–20

–30

S21
S11

Port 3
–40

S22
S32

–50
0.0

0.5

(a)

1.0
Frequency [GHz]

1.5

2.0

(b)

Fig. 4. In-phase power divider: (a) circuit configuration and (b) simulated S-parameters.

5

Amplitude balance [dB]

3.3 Fabrication and measurement results
The wideband quadrature mixer was designed andfabricated using a 0.3-µm GaAs MESFET (MEtal–
Semiconductor Field Effect Transistor) process with
ft = 20 GHz and fmax = 70 GHz. A photograph of thechip is shown in Fig. 5. The size was 1.8 × 2.3 mm2.
The measured amplitude balance and the quadrature phase error of the output signals for demodulation are shown in Fig. 6. The frequency of the baseband signal was set at 144 kHz (not zero), the RF
power level at –20 dBm, and the LO power level at +5
dBm. When the RF signal frequency was between 0.9
and 2.5 GHz, the amplitude balance and the quadrature phase error were less than 1.6 dB and 3º, respec-tively.
We tested the modulation performance using thesingle-side-band method, in which the image ratio
corresponds to the amplitude balance and the quadrature phase error [10]. Figure 7 shows the RF output
power as a function of the frequency. A 144-kHz
baseband signal with a phase difference of 90º was
input. The frequency was converted into an RF signalof frequency fRF based on the LO signal of frequency
fp = ( fRF – 144 kHz)/2. The input voltage of the baseband signal was 500 mVp-p. The input level of the LO
signal was +5 dBm from 0.7 to 2.3 GHz and +10 dBm
at 2.4 GHz or higher. When the RF signal frequency
was between 0.9 and 2.5 GHz, the image ratio wasless than –30 dBc and the leakage signal level at frequency 2fp was less than –40 dBm. This image ratio

0

10

–5

0

–10
0.5

Fig. 5. Photograph of the quadrature mixer.

34

20
Amplitude balance
Quadrature phase error

1.0

1.5
2.0
RF frequency [GHz]2.5

Quadrature phase error [degrees]

satisfied the matching conditions at two frequencies,
which, again, enabled it to achieve wideband performance.

–10
3.0

Fig. 6. Measured amplitude balance and quadraturephase error of the quadrature mixer for the
demodulator.

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0

Vc

Output power [dBm]–20
ASF variablefeedback circuit

–40
s

s

FET 2

–60
USB
LSB
2LO_leak

–80

1.0

Out
FET 1

LO power: +5 dBm
–100
0.5

FET 3

In

1.5

2.0

+10 dBm
2.5

Vd

Vg
3.0

RF signal frequency [GHz]
USB: upper sideband; LSB: lower sideband

Fig. 8. Circuit configuration of the low-noise variable-gain
amplifier.

Fig. 7. Measured output signals and leakage signals of
the quadrature mixer for the modulator.

indicates that the quadrature phase error was less than
3.6º if we assume an amplitude balance of 0 dB.
4. Low-noise variable-gain amplifierVol. 1 No. 4 July 2003

Fig. 9. Photograph of the low-noise variable-gain amplifier.
40–0.55 V
30

Gain [dB]

The variable-gain amplifier controls the gain in the
IF stage of transceivers with a superheterodyne architecture. However, there is no IF stage in transceivers
with a direct conversion architecture. Consequently, again-control mechanism was needed in the RF stage.
We therefore developed an LNVGA for that stage.
The design targets for the gain, noise figure, and variable-gain control range were above 20 dB, below 4
dB, and above 30 dB, respectively.
Figure 8 shows its circuit configuration. To achieve
wideband characteristics, no matching circuits withreactance elements were used. The amplifier used avariable-feedback circuit that consisted of two ASFs
(Anti-Series FETs) and two capacitors. The ASF circuit remained unsaturated with input power greaterthan the power which would cause a single FET tosaturate. As a result, the ASF circuit had lower distortion than a single FET [7]. Therefore, when theamplifier’s gain was controlled, the amplifier wascapable of low distortion.
The LNVGA was fabricated using 0.15-µm GaAs
pHEMT (pseudomorphic High Electron Mobility
Transistor) technology and had two-stage amplifiers.
A photograph of the chip is shown in Fig. 9. The size
was 1.3 × 2.0 mm2. The measured gain response,noise figure, and IP3 (3rd Intercept Point) are shownin Figs. 10, 11, and 12, respectively. From 0.9 to 2.5
GHz, the maximum gain was more than 26 dB, the–0.50 V20

–0.40 V10
–0.30 V
0–10

–0.20 V

0

2

4

6

8

10

Frequency [GHz]Fig. 10. Measured gain response of the low-noise
variable-gain amplifier.

35Selected Papers

noise figure at the maximum gain was less than 3.1
dB, and the variable-gain control range was morethan 30 dB. Moreover, when the LNVGA gain waschanged, the OIP3 (Output IP3) remained almost
constant near the value before the change.

8

Noise figure [dB]6–0.40 V

5. Local oscillator

4–0.50 V2
–0.55 V00246Frequency [GHz]

8

10

20

20

10

10

0

0

–10

–10

–20

–30
–10

IIP3 [dBm]

OIP3 [dBm]

Fig. 11. Measured noise figure of the low-noise variablegain amplifier.

–20

OIP3
IIP3
0

10

20

30

–30
40

Gain [dB]
OIP3: output IP3; IIP3: input IP3

Fig. 12. Measured third intercept points of the low-noise
variable-gain amplifier.

Our goal was to build a local oscillator that would
be able to cover the frequency bands of the target systems shown in Table 1. This LO would require only a
few commercially available VCOs (Voltage-Controlled Oscillators), and would have a tuning bandwidth within 10% of the center frequency. The actual
LO, whose architecture is shown in Fig. 13, has only
two VCOs. Variable frequency dividers with four
SPDT (Single Pole Double Throw) switches werealso used. Phase noise was reduced by using frequency division. Thus, the phase noise requirements were
not severe. This architecture was able to cover all
three systems from 0.9 to 2.5 GHz, including the
FDD system. In the FDD settings, the target suppression level for the leakage signal was more than 50 dB.
A block diagram of the variable frequency divider
is shown in Fig. 14. Dual-modulus prescalers andselectors were used because programmable counters
cannot operate at high frequencies. The frequency
division ratios were 2, 3, 4, 5, and 6. The variable frequency divider included an additional half frequency
divider that was used for PLL (Phase-Locked Loop)
input because many commercially available ICs for
PLLs operate at less than 2.5 GHz. The variable frequency divider was fabricated using a silicon bipolar
process with ft = 35 GHz. A photograph of the chip isshown in Fig. 15. The size was 2.0 × 2.0 mm2. The
fabricated variable frequency divider operated in thefrequency range of 100 MHz to 3.4 GHz when the

Table 1. Parameters for local oscillator settings.
Required tuning frequency range of VCO 1: 2402-2655 MHz.
Required tuning frequency range of VCO 2: 2694-2877 MHz.
SystemDuplexing

PDC

FDD

Frequency band
specification(MHz)

Settings selected
for the frequency
divider output

Division ratio of thevariable frequency
divider

Double the frequency of thefrequency divider output(MHz)

RX 810-885

Divider 1(to RX)6

801-885

TX 898-956

Divider 2(to TX)6

898-959

PHS

TDD

1895.15-1917.95

Divider 2(to TX,RX)3

1796-1918

2.4-GHzwireless LAN

TDD

2402-2484

Divider 1(to TX,RX)

2

2402-2655

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RF

Quadraturedownconverter
in RX

I
Q

Local oscillator
÷2

PLL
VCO 1

RX portVariablefrequency
divider 1

VCO 2

Variablefrequency
divider 2
PLL

TX port÷2

RF

Quadraturedownconverter
in TX

I
Q

RX: receiver
TX: transmitter
PLL: phase-locked loop

Fig. 13. Block diagram of the local oscillator architecture.

Outputfor PLL ICs

÷2

Input

÷2/÷3
÷2

Selector
Selector

÷4/÷5

Output÷2, ÷3, ÷4,
÷5, ÷6

Fig. 14. Block diagram of the variable frequency divider.

input power was –10 dBm. This showed that it waspossible to achieve all the frequencies in Table 1. The
VCOs and the switches were commercially available
products. The tuning ranges of the two VCOs werefrom 2.38 to 2.69 GHz and from 2.65 to 3.02 GHzwith a 3-V supply. The SPDT switches had 0.6 dB ofinsertion loss and 40 dB of isolation from DC to 2.5
GHz.
Figure 16 shows the output spectrum of the local
oscillator at the RX port shown in Fig. 13 for the FDD
system settings. The leakage signal level of 478 MHz
was suppressed by more than 60 dB compared with
Vol. 1 No. 4 July 2003

the desired signal level of 413 MHz.
6. Conclusion
We have developed an RF chipset for multi-banddirect conversion transceivers that covers the frequency bands of three systems (PDC, PHS, and 2.4GHz WLAN). The chipset consists of a quadrature
mixer, an LNVGA, and a local oscillator. The mixer
achieves wideband performance through the use of
newly developed wideband power dividers. When the
RF frequency was between 900 MHz and 2.5 GHz,
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Desired signal

Leakage signal

Center: 450 MHz; H: 10 MHz/div; V: 10 dB/div.

Fig. 16. Output spectrum of the local oscillator.
Fig. 15. Photograph of the variable frequency divider.
[2]

the demodulator mixer experimentally showed an
amplitude error of less than 1.6 dB and a quadraturephase error of less than 3º. For the same RF frequency range, the modulator mixer showed an image ratioof less than –30 dBc. The LNVGA achieves wideband performance without the use of reactance elements and displays highly linear performancethrough the use of an anti-series FET feedback circuit. From 900 MHz to 2.5 GHz, the maximum gain
is more than 28 ± 1.6 dB, the noise figure at the maximum gain less than 3.1 dB, and the variable-gain
control range more than 30 dB. The local oscillator
achieves multi-band performance that is able to cover
the target frequencies for PDC, PHS, and 2.4-GHz
WLAN systems.
This approach should significantly contribute to thedevelopment of compact multi-mode mobile transceivers such as software-defined radios.
References[1]38

H. Tsurumi and Y. Suzuki, “Broadband RF stage architecture for software-defined radio in handheld terminal applications,” IEEE Commun. Mag., pp. 90-95, 1999.

A. Abidi, “Direct-conversion radio transceivers for digital communications,” IEEE J. Solid-State Circuits, Vol. SC-30, No. 12, pp. 13941410, 1999.
T. Yamaji, H. Tanimoto, and H. Kokatsu, “An I/Q active balanced
harmonic mixer with IM2 cancelers and a 45º phase shifter,” IEEE J.
Solid-State Circuits, Vol. SC-33, No. 12, pp. 2240-2246, 1998.
[4] B. Matinpour, A. Sutono, and J. Laskar, “A low-power direct conversion receiver module for C-band wireless applications,” 2001 IEEE
MTT-S International Microwave Sym. Dig., Vol. 1, pp. 567-570,
2001.
[5] T. Nakagawa, M. Kawashima, H. Hayashi, and K. Araki, “A 0.9–2.5GHz wideband direct conversion receiver for multi-band applications,” 2001 IEEE GaAs IC Symp. Dig., pp. 37-40, 2001.
[6] M. Kawashima, T. Nakagawa, H. Hayashi, K. Nishikawa, and K.
Araki, “A 0.9-2.6-GHz broadband RF front-end for direct conversion
transceivers,” 2002 IEEE MTT-S International Microwave Sym.
Dig., Vol. 2, pp. 927-930, 2002.
[7] M. Kawashima, T. Nakagawa, H. Hayashi, K. Nishikawa, and K.
Araki, “A 0.9–2.6-GHz broadband RF front-end chip-set with a directconversion architecture,” IEICE Trans. Commun., Vol. E85-B, No.
12, pp. 2732-2740, 2002.
[8] K. Itoh, M. Shimozawa, N. Suematsu, and O. Ishida, “Even harmonic type direct conversion receiver ICs for mobile handsets,” 1999
IEEE RFIC Symp. Dig., pp. 53-56, 1999.
[9] D. Neuf, “Fundamental, harmonic and sampling MESFET mixer circuits,” Microwave Journal, pp. 76-58, 1995.
[10] J. W. Archer, J. Granlund, and R. E. Mauzy, “A Broad-band UHF
mixer exhibiting high image rejection over a multidecade baseband
frequency range,” IEEE J. Solid-State Circuits, Vol. SC-16, No. 4, pp.
385-392, 1981.
[3]

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Munenari Kawashima
Wireless Systems Innovation Laboratory, NTT
Network Innovation Laboratories.
He received the B.S. and M.S. degrees in physical chemistry from Osaka University, Toyonaka, Osaka, in 1995 and 1997, respectively. In
1997, he joined the NTT Wireless Systems Laboratories (now NTT Network Innovation Laboratories), Yokosuka, Japan, where he has been
engaged in research and development on monolithic microwave integrated circuits and theirapplications. His research interests include wideband RF circuit design for wireless transceivers.
He is a member of IEEE and the Institute of Electronics, Information and Communication Engineers (IEICE).

Tadao Nakagawa
Senior Research Engineer, Wireless Systems
Innovation Laboratory, NTT Network Innovation Laboratories.
He received the B.E. and M.E. degrees in material physics and the Dr.Eng. degree in communication engineering from Osaka University,
Osaka, Osaka, in 1986, 1988, and 1997, respectively. In 1988, he joined the NTT Radio Communication Systems Laboratories, Yokosuka,
Japan, where he was engaged in research anddevelopment on MMICs and microwave synthesizers. From 1997 to 1999, he was an AssociateManager at STE Telecommunication Engineering Co., Ltd., where he served as a technical consultant on wireless communications to Seiko
Epson Corporation, Nagano, Japan. Since 1999,
he has been a Senior Research Engineer at the NTT Network Innovation Laboratories, Yokosuka, Japan. He is currently involved in the design of multi-band transceivers and millimeter-wave transceivers. Since 2001, he has also been a part-time
instructor at Kanto Gakuin University, Yokohama, Japan. Since 2002, he has beenan Associate Editor for the regular issue and two special issues of the IEICE Transactions on Electronics. Dr. Nakagawa is a Senior Member of IEEE and a member of
IEICE. He was the recipient of the 1995 Young Engineer Award presented by IEICE.

Vol. 1 No. 4 July 2003

Hitoshi Hayashi
Senior Research Engineer, Wireless Systems
Innovation Laboratory, NTT Network Innovation Laboratories.
He received the B.E., M.E., and Ph.D. degrees
in electronics engineering from the University ofTokyo, Tokyo, in 1990, 1992, and 2000, respectively. In 1992, he joined the NTT Radio Communication Systems Laboratories, Yokosuka,
Japan. He is currently with the NTT Network
Innovation Laboratories, Yokosuka, Japan,
where he is engaged in the development of wireless communication systems. From 2000 to
2001, he was also involved in wireless systems
research at the Massachusetts Institute of Technology (MIT), U.S.A., as a Visiting Scientist. Dr.
Hayashi is a member of IEEE and IEICE. He was
the recipient of the 1998 Young Engineer Award
given by IEICE.

Kenjiro Nishikawa
Senior Research Engineer, Wireless Systems
Innovation Laboratory, NTT Network Innovation Laboratories.
He received the B.E. and M.E. degrees in welding engineering from Osaka University, Suita,
Osaka, in 1989 and 1991, respectively. In 1991,
he joined the NTT Radio Communication Systems Laboratories (now NTT Network Innovation Laboratories), Yokosuka, Japan. He has
been engaged in research and development on
three-dimensional and uniplanar MMICs on Si
and GaAs, and their applications. His current
interests are millimeter-wave MMIC design/
packaging technologies and microwave/millimeter-wave communication systems. He is a member of IEEE and IEICE. He received the 1996
Young Engineer Award from IEICE .

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