Signal Wireless Carrier Synchronization Using
Power Line for Interleaving in Power Converters
Keita Ohata
Dept. of Science of Technology
Innovation
Nagaoka University of Technology
Nagaoka, Japankeita_ohata@stn.nagaokaut.ac.jp

Hiroki Watanabe
Dept. of Electrical, Electronics, andInformation Engineering
Nagaoka University of Technology
Nagaoka, Japanhwatanabe@vos.nagaokaut.ac.jp

Abstract— This paper proposes a carrier synchronization
method that does not require synchronous signal lines and atime synchronization module, such as a GNSS module. Forinterleaved and multilevel operations, all carriers must be
synchronized in order to align the switching timing. In a
distributed control system with multiple controllers, signal lines
or additional time modules are required for synchronization,
reducing maintainability and cost. In this paper, the proposed
carrier synchronization is performed by superimposing a
synchronization signal on the power line. The proposed control
method is demonstrated by simulation, showing that thesynchronization accuracy is within 0.2 s. Especially thismethod is effective in realizing electrified systems in severe
conditions, such as in the sectors of construction machinery,aircraft, and aerospace.
Keywords— carrier synchronization, interleaving, multilevel,
modular multilevel converter, distributed control, electrification,
construction machinery

I. INTRODUCTION
Power converters are required to be compact and highpower density. Increasing equivalent switching frequency byinterleaving or multilevel operation is a popular technique toexpand the operation range of the power converter [1]-[4].
Interleaving and multilevel operations require synchronizedcarriers. Thus, one of the following system configurations
must be adopted; 1) a single controller manages all cells, and2) signal wires among controllers are added to share thesynchronization signal with a few microseconds of accuracy.
Some of the carrier synchronization methods with signal lines
are based on controller area network (CAN), EtherCAT, anda customized protocol based on Ethernet [5]-[7]. The
disadvantage of these methods is that the signal wires andadditional components for synchronization are needed. These
components bring increasing costs and limited reliability.
In contrast, power line communication (PLC) has attracted
in some industrial fields such as the Internet of Things (IoT)
devices and factory automation to reduce signal wires [8]-[9].
The PLC technique superimposes high-frequency signals on
power lines at the transmitter and uses the power lines astransmission lines. After arriving at the receiver, the data isrecovered by separating the high-frequency components of thepower line. The future of PLC is promising with the
publication of IEEE Std. 1901-2020 as a standard
specification for physical (PHY) and medium access control

Jun-ichi Itoh
Dept. of Science of Technology
Innovation
Nagaoka University of Technology
Nagaoka, Japan
itoh@vos.nagaokaut.ac.jp(MAC) layers [10]. The advantage of PLC is communicablewithout signal lines. Meanwhile, PLC needs additional
circuits and signal wires for the superimposing and extraction.
[11]-[13] proposed superimposing data signals to thepower line by changing the switching frequency without
additional circuits for PLC. These proposals will greatly
expand the PLC application because data transmission andpower conversion are integrated. However, these studies
focused on data communications, and carrier synchronization
using PLCs is not assumed. The carrier synchronization using
the power line requires high-precision synchronization withlow jitter compared to data transmission. Thus, carrier
synchronization using a power line is a challenging approach.
Meanwhile, as another approach, a carrier synchronization
technique has been proposed using the high-precisionsynchronization signal utilizing global navigation satellite
system (GNSS) signals [14]. In [14], a synchronized trigger isobtained by pulse per signal (PPS), which has highsynchronization accuracy and enables wireless carrier
synchronization among independent controllers within ±80 ns
synchronization error. The method reduces signal wires
among independent controllers for synchronization. However,
GNSS brings two disadvantages; 1) GNSS cannot be used inradio-shielded spaces, 2) Increasing costs by GNSS modules.
This paper proposes a carrier synchronization method that
does not require synchronous signal lines and a timesynchronization module, such as a GNSS module. The
proposed method has three steps; 1) the carrier synchronous
reference signal is generated in the low-frequency region
where it is easy to detect, 2) the carrier synchronous reference
signal is extracted by each controller, 3) Frequency
multiplying reference signal to carrier frequency. This allows
the controllers to generate high-precision carrier synchronous
signals without additional components. Thus enabling thecontroller to be signal wireless while preventing highcontroller costs.
The new contributions of the proposed method are that 1)
synchronization at the carrier level is achieved without signal
wires and additional time synchronization components, suchas GNSS module, 2) the synchronization is continuously
achieved in radio-shielded placements such as in basements,
reinforced-concrete buildings, and metal frames. The

converter is driven by an independent controller, and thecontroller clocks are not synchronized among controllers.

Cell #1 f = 10 kHz
sw
iin Lb
3 mH

S1

B. Controller

S2
Host controller
Cell #2
Cdc

Vin
100 V

100 F

Local controller #1

Rload

53.3 W

No signal wires
among controllers

Cell #3

Local controller #2
Fig. 1. Main circuit. A boost converter is used. The proposed carrier
synchronization method is also acceptable to various circuit topologies,
such as a dual active bridge (DAB) converter or a phase shift full bridge(PSFB) converter. There are no signal lines among controllers. The
carrier synchronization is performed based on the signal, which aresuperimposed on the output voltage detected by each controller.

DSP
Iin*

PI

S1
S2

CRPK
0

iin

Carrier

A/D
Host controller

Iin

FPGA
PI

S3
S4
A/D

Multiplication
rate Nfcarrier

Phase
shifter

mul

qcomp

Band-pass freq.: fsync

PLL

BPF
Fig.6

Fig.7

Fig. 3 shows the outline of the proposed wireless carrier
synchronization method. The proposed method consists of thefollowing three steps.
A. Superimposing carrier synchronous signal

fsync , Sine wave

iinIII. PRINCIPLE OF PROPOSED CARRIERSYNCHRONOUS METHOD

fca rri er

Synchronous signal
generator
Asy ncDSP
Iin*

Fig. 2 shows the controller configuration. One controller
is attached to each converter, for a total of three controllers.
One of the controllers is the host controller, and the others are
local controllers. The local controllers are controlled tosynchronize with the host controller’s carrier based on thesynchronization signal from the host controller. The hostcontroller consists of a digital signal processor (DSP) with acurrent proportional-integral (PI) controller and a carrier
synchronous signal generator. The local controller consists ofa DSP and a field programmable gate array (FPGA). The
function of DSP are a bandpass filter (BPF) that extracts thecarrier synchronous signal, a phase-locked loop that multiplies
from the reference signal to the carrier frequency. The
functions of FPGA are as a phase shifter to achieve theinterleaving and a comparator to implement carrier-based
modulation.

Iin

S5
S6
A/D IinSampling freq.
fsamp

A/D Vout

A/D Vout
Local controller #1
Local controller #2
Fig. 2. Proposed control system.

proposed method is simulated by three boost converter witheach independent controller. From the simulation results, thesynchronization accuracy within 0.5 s is achieved.
Furthermore, the characteristics of the proposed method arepartially verified by fundamental experiments.
II. SYSTEM CONFIGURATION
A. Main Circuit
Fig. 1 shows the targeted circuit in this study. Three boost
converters are connected in parallel. A DC power supply isconnected to the input, and a resistive load is connected. EachThe carrier synchronous signal usync(t) is expressed as
usync (t ) = Async sin(2 f sync t )(1),where Async is the amplitude of the synchronous signal, andfsync is the frequency of the synchronous signal. The
synchronous signal fsync (t) is superimposed on the output of
the input current PI controller. The zero degree of the carrier
synchronous signal is aligned on the bottom of the carrier.
B. Extracting component of carrier synchronous signal
using BPF
The synchronous signal frequency component is detectedby the local controller using a BPF. The bandpass frequency
is matched to the synchronous signal frequency fsync to extract
the synchronous signal component in the output voltage. In
designing the BPF, the phase characteristics should be linear
and gradual near the synchronous signal frequency. The
reason is to easily compensate the phase lead or lag due to the
BPF.
C. Reference signal restoration and frequency multiplying
The phase of the reference carrier is obtained by a PLL
with a frequency multiplier at the local controller based on
the BPF output. Then, the feed-forward compensation ofphase delay is needed. The estimated delay of recovered
synchronous signal rcvy is given by

Controller Plant

iin

Time
Step 1)Superimposing carrier sync. sig.
usync to duty command(usy nc synchroni zes to the bottomof carrier)z-1(Backward euler)

iconv
vL 1 iin
Kconv
sLb
Converter

ZOH

1

vout

ic sCoutgain

Carrier sync. sig.
usync(t)Time
10Local controller

Gain [dB]PI-i = 1000 rad/s

0

Step 2)Component of dummy s ignal is
extracted by BPF

2000 rad/s

03000 rad/s

Time

-20

4000 rad/s

fsync = 625 Hz-402

Phase [deg.]

04000 rad/s

Time

Del ay
comp.

0

High

156 deg. @ 2000rad/sPI-i = 1000 rad/s

-200

Low

Multiplicate
d carrier ref.
sig.

1
Rload

Fig. 4 block diagram of input current controller and load.

0

BPF output

Discrete PI

iin*

Low

AdummyCompensatedcarrier ref. sig. PLL output

iload

High

Carrier sync.
sig. usync

Carrier in hostcontroller

Host controller

-40
-400

Time

Carrier sync.
is achieved

Step 3)
PLL estimates the angle of imposed signal.
Frequency multiplication from carrierreference frequency to carrier frequency.

10

High

Time
Fig. 3 Outline of proposed carrier synchronization using power line.

Name
Input voltage
Number of cells
Rated output power
Boost inductor
Load resistance
Output capacitance

TABLE II.

CIRCUIT PARAMETERS.
Symbol
Vin
N
P
Lb
Rload

Value
100 V
3
1 kW
3 m
53.3 W
100 FCout(H = 2.67 ms)
H: Unit capacitance constant

CONTROLLER PARAMETERS.

Parameter
Sampling frequency

Symbolfsamp

Carrier frequency

fcarrier

Controller bandwidth
for input current
Amplitude of carrier sync.
sig.
Frequency of carrier sync.
sig.

PIi
Async

Multiplication rate

Nmul

fi

fsync

10000

Fig. 5 Frequency characteristic of output voltage from carrier
synchronous signal vout /usync.

Low

TABLE I.

100
1000
Frequency [Hz]Value
100 kHz
10 kHz
20 kHz (in Chap. V)
2000 rad/s
318.3 Hz
12 V(±10 % duty variation)

625 Hz1250 Hz (in Chap. V)
16
8 (in Chap. V)

determined by the controller bandwidth, the output
capacitance, and the load resistance. Tdet is the delay at thedetection circuit, TADC is the delay at the AD converter, TBPF
is the phase delay at the BPF, TPLL is the delay at the PLL.
In this paper, delays due to Tdet, TADC, TBPF, and TPLL areassumed to be zero and are not included in the simulation
model. The assumption is based on two reasons; 1) constantdelay (i.e., easy compensation), 2) These delay are notdominant for Tv-i.
Hence, this paper focuses on the dominant phase delay inrecovered synchronous signal Trcvy which is composed only
Tv-i. From these assumptions, (2) is approximated by
Trcvy  Tv − i(3).
IV. CONTROLLER DESIGN
Table I lists the circuit parameters. The input is connected
to 100V DC. A resistive load and a output capacitor isconnected at output terminals of boost converters. Table IIlists the controller parameters.
A. Input current controller

Trcvy = Tv −i + Tdet + TADC + TBPF + TPLL

(2),

where Tv-i is the phase delay of output voltage from thecarrier synchronous signal. The phase delay Tv-i is

The host controller superimposes the carrier synchronous
signal usync on the output of the current PI controller. Hence,the carrier synchronous signal is as a disturbance to theTABLE III.

DESIGN PARAMETERS FOR BAND-PASS FILTER

Parameter
Sampling frequency
Center frequency
Band-pass width

Coefficientsx (n)Symbolfsamp
fcenter
BW
a0
a1
a2
b0
b1
b2

b0

a0

b1

-a1

Value
100 kHz625 Hz0.05 octave
1.0007-1.99850.99930.00070.0000-0.0007

B. Band-pass filter
Table III lists the coefficients of the infinite impulse
response(IIR) filter. The second-order IIR filter is employed
as the BPF. Fig. 6 shows the frequency characteristics of the
BPF. The transfer function of the IIR filter is expressed as
GIIR ( z ) =

y (n)
z-1

z-1

-a2

b2

Gain [dB](a) block diagram.

0
-10
-20
-30
-40
-50
-60

(4),

where center is 2fcenter and Q is quality factor. Here, the filter
coefficients ak and bk are obtained by transforming (5) into
the z-domain using the bi-linear transformation.
fcenter=625 Hz

10

100

1000

10000

(b) Gain characteristic.
90

Phase [deg.]b0 + b1 z −1 + b2 z −2
a0 + a1 z −1 + a2 z −2

where ak and bk are filter coefficients. The transfer functionof typical BPF is given bycenter s
Q
GBPF ( s) =(5),
s 2 + center s +  2 center
Q

z-1

z-1

the bandwidth of the input current controller at local
controllers should be set to the same value. When designed
for 2000 rad/s, the output voltage phase is -156deg comparedwith the synchronous signal.

fcenter=625 Hz

45
0
-45
-90
10

100
1000
Frequency [Hz]10000(c) Phase characteristic.
Fig. 6. Implementation of bandpass filter.

vout_BPF

Phase
dete ctorPIsync Inte grator withwrapped stateq´syncFrequency/phaseangle converter

Nmul

ModuloCalc.

Angle of recovery
carrier qcarr

Delaycompensation

qcomp

C. PLL and frequency multiplierFig. 7 shows the implemented PLL and frequency
multiplier. This study employs an enhanced PLL. The phasedetector involves an adaptive notch filter to improve thetracking performance of PLL. The PLL output synchronizes
with the synchronous signal usync by the host controller. The
multiplication rate is determined byf(6).
N mul = carrier
f syncFor simplicity of implementation, the multiplication rateshould be set to a power of 2. In this paper, carrier frequency
fcarrier and carrier synchronous signal frequency fsync are set to
10 kHz and 625 Hz, respectively. Thus, the multiplication
rate Nmul is set to 16, respectively. The delay compensation
qcomp is set toT(7).
q comp = 2 rcvy
Tsync

Fig. 7 Implementation of PLL and frequency multiplier.

V. SIMULATION RESULTS

current PI controller. The control bandwidth of input current
PI controller must be limited in order to prevent a eliminationof the synchronous signal.
Fig. 5 shows the frequency characteristic of output
voltage from carrier synchronous signal vout/usync. In the
proposed method, the synchronous signal frequency is set toaround a few hundred Hz to a few kHz. The component of
the synchronous signal is eliminated due to increasing thecontrol bandwidth. The control bandwidth is set to 2000 rad/s
to prevent the elimination of the imposing signal. Moreover,Fig. 8 shows the simulation result with the proposed
carrier synchronization method. By superimposing a 1.25 kHz
carrier synchronous signal usync on the duty command, thefrequency component of the signal frequency is involved theoutput voltage with the phase delay v-i. By correcting thedelay and the delay of the BPF filter, the synchronous signal
is recovered. By multiplying the PLL output with themultiplication rate Nmul, the carrier of the local controllers aresynchronized with the carrier of the host controller. From thesimulation results, the synchronization accuracy within -0.21
s (-0.72 deg) is achieved. Hence, the proposed method has

2000

Carrier counter

Output voltage [V]

250
200

1000

150

0
5

Imposed signal (%Duty)

100
Input current [A]
15 0
1

0

3

4

2
Time [ms](a) DC coupling.

3

4

10

-5

Extractive imposed signal [V] (BPF output)
4
2
0
-2
-4
Recovered PLL output qref [rad]864800 s2(1.25kHz)0
Multiplificated Imposing signal angle qref [rad]
8
6
4
2
0
6 Input current [A]50

5 kHz LPF

0

v-i=0.68 ms (v-i = 155 deg)

-5-50.21s

5 0

0

1.6
1
1.5
Time [ms]Fig. 8 Simulation result (fsync = 1.25 kHz, fsw = 20 kHz).
0.5

Output voltage (AC coupling)
1
2

3

4

3

4

0

5 kHz LPF

-5

0

2

1

Input current (AC coupling)

5

4
0

2

Current command: 10 A

1

2Time [ms](b) AC coupling.

Fig. 9. Experimental waveforms of input current and output voltage at
rated output (1 kW) when the host controller only operates. The
synchronous signals were generated by varying duty cycle by ±10%.

the potential to achieve interleaving without wired
communication.

simulation results, the synchronization accuracy within -0.21
s (-0.72 deg) is achieved.

VI. FUNDAMENTAL EXPERIMENT

In future work, the experimental verification will bescheduled. In addtion, the relationship between transientcarrier synchronization accuracy during load fluctuations will
be studied.

Fig. 9 shows the input voltage and the input current at the
rated output when cell #1 only operates. The input voltage
and the input current are measured with AC coupling modein Fig. 9 (b). The phase difference between input current andoutput voltage v-i is -155 deg. This is the phase difference
determined by the control bandwidth of the input current
controller, the output capacitor, and the load. Meanwhile, theanalysis in Figure 5 shows a delay of -156 deg. Therefore, thetheoretical model (Fig. 4) agrees with experimental results.
VII. CONCLUSION
This paper proposed a carrier synchronization method
without signal lines that realize interleaving using a power line.
In the proposed method, a low-frequency carrier synchronous
signal is superimposed on the power line, and each controller
detects the signal individually. The signal multiplys to theswitching frequency.
The proposed method generates the carriers with highaccuracy while reducing the sampling frequency required forthe controller. Thus, the proposed method has two features; 1)
no restrictions on the location of use, 2) no additonalcomponents for the carrier synchrnonization. From the

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