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AND9175/D
Enable Pin Operation andFunctions of eFuses
Introduction

ON Semiconductor electronic fuses (eFuses) are analog
integrated circuits that are used to protect circuits operatingfrom 3.3, 5, or 12 V DC supplies. They have numerous
protection functionalities such as overvoltage clamping,current limiting, thermal shutdown, and a controlled output
voltage slew rate. They are available in thermal latching or
thermal auto-retry configurations.
A key feature of the eFuse family is the enable pin. Thisapplication note describes the features of the enable pin andprovides guidance to ensure its proper use. The enable pinof any eFuse may be left floating if the application does not
require that it be controlled and does not require thermal
fault notification. For a basic explanation of the operation of
an eFuse, please refer to the datasheets for the NIS5112,
NIS5135, NIS5132, and NIS5232.
The operation and functionality of the enable pin depends
on the particular eFuse being considered. Table 1 provides
information regarding the key differences between thedevices in the ON Semiconductor eFuse family.

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APPLICATION NOTE

2.5 V

Table 1. THE KEY DIFFERENCES BETWEENTHE FUNCTIONALITY OF THE ENABLE PIN FOR
ON SEMICONDUCTOR eFUSES
Startup
Blanking

Timer
Capability

Logic
LevelsNIS5112NoYes

Low or HighNIS5135,NIS5132, NIS5232

Yes*NoLow, Mid, orHigh

DeviceEnabledThe NIS5112 enable pin may also be used as a timer pinby adding a capacitor between it and ground as shown in
Figure 1. Such a capacitor provides a delay after power isapplied to the eFuse or after a transistor on the enable pintransitions from on to off. The timer circuit uses the internal
80 mA current source shown in Figure 1 to charge thecapacitor. The eFuse does not turn on until the current source
charges the capacitor to the high state of the enable pin.
The added delay is given by:

NIS5112 Enable/Timer Pin

The enable pin of the NIS5112 may be in either a high or
a low state. Figure 1 provides a simplified schematic of theenable circuit. The voltage at the enable pin is comparedwith a nominal 2.5 V internal reference voltage. If thevoltage at the enable pin is greater than this reference
voltage, the eFuse output is enabled. To force the enable pin
voltage low, it is recommended that a transistor is connected
as shown in Figure 1. An internal current source of about
80 mA serves as the pull-up device.
The NIS5112 has a typical thermal shutdown temperatureof 135°C. After a thermal shutdown, a thermal auto-retry
NIS5112 returns power to the load after its internal
temperature drops below 95°C (typical). By contrast,
a thermal latching NIS5112 remains in a disabled state with
its enable pin high after thermal shutdown. Resetting may bedone by cycling the power to the eFuse or by forcing theenable pin into the low state and then releasing the pin.

January, 2017 − Rev. 1+−Figure 1. Simplified Schematic of the Enable
Circuitry for the NIS5112. It Shows a Transistorand a Timing Capacitor Connected*The NIS5132MN3 does not have a startup blanking circuit.

© Semiconductor Components Industries, LLC, 2014

80 mA

Enable/Timer

Delay +(V High) (C)I Source(eq. 1)

Where VHigh is the voltage to enter the high state on theenable pin, C is the value of the capacitor between the enablepin and ground in farads, and ISource is the eFuse’s internalcurrent source on the enable pin. Values for the enable
voltage and charging current for different conditions areprovided in the NIS5112 datasheet. For example, at 25°C,
VHigh has a minimum value of 2.5 V and ISource has a typicalvalue of 83 mA. Therefore, to achieve a 25 ms delay,
the following calculation may be made:25

10 *3 +(2.5) (C)83 10 *6

C + 0.83 mF

1(eq. 2)Publication Order Number:
AND9175/D

AND9175/DNIS5135, NIS5132 and NIS5232 Enable/Fault PinThe enable pin of the NIS5135, NIS5132, and NIS5232
has three different logic levels. Table 2 provides a summaryof these logic levels. In contrast to traditional input/outputbuffers, there is no circuitry which isolates the input andoutput circuits from each other and the enable pin’s input andoutput functions operate simultaneously.

Table 2. TRI-STATE LEVELS OF THE ENABLE PIN OF THE NIS5135, NIS5132 AND NIS5232
LevelLowMidHighHow Enable Pin is Placed in Logic State

State of eFuse

Held low by startup blanking circuit for fixed time after power has been
applied to VCC*

Output disabled, thermal latch circuitry reset

Held low by external circuit

Output disabled, thermal latch circuitry reset

Forced to level by internal circuitry due to a thermal fault condition

Output disabled, thermal shutdown

Held in state by the enable pin of another eFuse

Output disabled

Pulled high by internal circuitry

Output enabled*The NIS5132MN3 does not have startup blanking circuitry.

A simplified schematic of the enable circuit is shown inFigure 2. The output of the enable circuit is the enableshutdown (SD) signal. A high enable SD forces the eFuse toshut down, removing power from the load. A low enable SD
allows normal operation. The enable SD comparator

generates the enable SD signal based on an internallygenerated nominal 2.64 V internal reference and the enable
voltage as shown in Figure 2. Under normal conditions andwith no external input, the enable pin is held high by a 12 mA
internal current source and the enable SD signal is low.

4.3 V
Startup
Blanking*

12 mA

2.64 VEN/Fault+−Enable SD

1.4 V−+SD

0.58 VThermalShutdown

Thermal Reset

Thermal SD(*MN1 and MN2 Versions)Figure 2. Simplified Schematic of the Enable Circuitry for the NIS5135, NIS5132 and NIS5232

startup blanking transistor in Figure 2. After the startup
time, the startup blanking transistor is turned off and theenable pin voltage is pulled to a high state.
The enable pin may be forced to the low or mid state withan external circuit to disable the eFuse. A low state may beforced by connecting a transistor as shown in Figure 3.
The enable pin should not be forced high. For example, itshould not be connected to VCC or directly to standard logic
circuits with active circuitry. Furthermore, it is notrecommended to connect a capacitor from the enable pin toground for timing purposes.

An enable SD high is generated by the enable SD
comparator any time the enable voltage goes below thenominal 2.64 V threshold for a high state. As shown inTable 2, there are four basic ways the enable pin can beforced or held below the high state. These are the startup
blanking circuit, an external transistor connected to theenable pin, the internal thermal shutdown circuit, and theenable pin of another eFuse.
When power is first applied to the eFuse, a startup
blanking circuit holds the enable pin to ground for a fixed
time (typically much less than 100 ms) by turning on thewww.onsemi.com
2

AND9175/D
8

results in the enable pin being pulled to the intermediate ormid state. Since the mid state is below the trip point for theenable SD comparator, a high enable SD is generated and theeFuse output is disabled.
An alternate method of controlling the state of the enable
pin is to tie the enable pins of multiple eFuses together.
The maximum fanout (the total number of eFuses that canbe connected to the pin for simultaneous shutdown) is three.
A common application is a system with 5 and 12 V rails
using the NIS5135 and the NIS5232 with the enable pins
connected to each other as shown in Figure 4. With multiple
enable pins tied together a thermal fault on one eFuse forces
a mid level on all of the eFuses. This ensures full shutdown
of a system under a thermal fault condition on any of theeFuses.

ENABLEGNDENABLE

10GNDFigure 3. Circuit for Forcing a Low Stateon the Enable Pin

Activation of the thermal shutdown circuit provides a highsignal to the internal thermal shutdown transistor to pull theenable pin out of the high state. A 1.4 V diode drop element
in series with the internal thermal shutdown transistor

VCC

VCC

SOURCE

SOURCERS

NIS5135ILIMIT

LOAD

dv/dt

NIS5232

ENABLE/FAULT

ENABLE/
FAULT

GND

GND

ILIMIT

dv/dt

LOAD

ENABLE

Figure 4. Example of Two eFuses with their Enable Pins Connected together for a Common Thermal Shutdown.
The Transistor Connected to the Enable Pin may be used to Hold the Enable Pin Low
or to Reset the eFuses after Thermal Latching

power to the VCC pin or alternatively by forcing the enable
pin into the low state and then releasing the pin. The functionof the reset circuit may be seen in Figure 2. If the logic levelon the enable pin is changed from the mid level to the lowlevel, the output of the thermal reset comparator goes from
low to high, signaling the thermal shutdown circuit to reset.

The functional distinction between the mid and low levels
is only significant for thermal latching eFuses. Aftera thermal shutdown, an auto-retry NIS5135 or NIS5132
returns power to the load after the internal temperature of theeFuse drops below 130°C (typical). The enable pin of thethermal latching versions is brought to the mid state afterthermal shutdown. The eFuse may be reset by cycling thewww.onsemi.com
3

AND9175/D
Summary

The enable pin of the NIS5135, NIS5132, and NIS5232 hasa middle logic state and their enable pins may be connected
to allow a common thermal shutdown. A capacitor may beconnected on the NIS5112 to serve as a startup timer, while
the NIS5135, NIS5132MN1, NIS5132MN2, and NIS5232
have an internal startup blanking circuit and should not havea capacitor connected from the enable pin to ground.

The enable pin of ON Semiconductor eFuses provides
a number of features. With all eFuses, a transistor may be
used to force the pin low to disable the output. In addition,
it may be left floating if no control of the enable pin isrequired. With thermal latching eFuses, it may be brought
low and then allowed to go high to reset the device.

ON Semiconductor andare trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage
may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer
is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless ofany support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can anddo vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s
technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized
for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices
intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify andhold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor wasnegligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyrightlaws and is not for resale in any manner.

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AND9175/D