STM32WL5 – SYSCFGSystem Configuration Controller
Revision 1.0

Hello, and welcome to this presentation of the System
Configuration Controller.

1Overview• All STM32WL5 devices feature a “System Configuration Controller”• Remap memory areas• Manage GPIO EXTI multiplexing• Manage “robustness” features• SRAM2 protection features• I2C Fast-mode Plus configuration• Independent CPU interrupt pre-masking

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STM32WL5 devices feature a set of configuration registers.
The System Configuration Controller gives access to thefollowing features: Remapping memory areas to Cortex-M4
address 0, multiplexing GPIOs to the internal interconnect
EXTI signals, certain robustness features, SRAM2 writeprotection and erase, the configuration of the 20 mA highdrive I/Os used for I²C Fast-mode Plus, and peripheral
interrupt pre-masking for the two CPUs.

2Memory mapping•Flash memory: up to 256 Kbyte, single bank••Reserved

32 Kbyte @ 0x2000 0000

User Options
0x1FFF 7800

OTP
0x1FFF 7400

32 Kbytes @ 0x2000 8000
32 Kbytes @ 0x1000 0000 (Only accessible by Cortex-M4)

Cortex-M4 bus relation•0x2000 0000

Reserved

SRAM2 (backup):•••

0xE000 0000

0x2000 8000

RAM1

SRAM1:••Cortex CPUs
Internalperipherals@0x0800 0000

SRAM: 64 Kbytes split in 2 parts:••

SRAM20xFFFF FFFF

Memories below address 0x2000 0000 areaccessed by D-code and I-code bus

Peripherals

System Memory
0x1FFF 0000

Reserved
0x4000 0000

Reserved
RAM0x2000 0000

Memories from address 0x2000 0000 andabove are accessed by S-bus

SRAM20x1000 0000

Reserved
User Flash
0x0800 0000

CodeMemory
depending on
Boot configuration

0x0000 0000

Pictured here is the 4-gigabyte linear address mapping of
the STM32WL5 microcontroller.
The Flash memory is up to 256 Kbytes, in a single-bankconfiguration.
The SRAM total size is 64 Kbytes. It is split into 2 parts:
SRAM1 is 32 Kbytes starting from address 0xx2000 0000
and SRAM2 backup RAM is 32 Kbytes starting from address
0x2000 8000 and also aliased at Cortex-M4 address 0x10000000. Both SRAM1 and SRAM2 are located in the usual
ARM memory space for RAM on the S-bus. SRAM2 can also
be accessed directly through Cortex-M4 Data code andInstruction code buses allowing zero wait states, used forcode execution.

0x0000 0000

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Memory remap
Performance booster!

• CPU1 Cortex-M4 address 0x0000 0000 remapping options (MEM_MODE)• Main Flash memory• System Flash memory (Bootloader)• SRAM1• Boosts performance thanks to I-Code/D-Code accesses instead of System Bus

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The memory remap at CPU1 Cortex-M4 address 0 allows
the boost of the performance thanks to Instruction and Databus access instead of using the System bus.
The memory remapping at address 0 is selected using theMEM_MODE bits in the System Configuration Remapregister. They allow the selection of either the main Flashmemory, or the system Flash memory, or the SRAM1.

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Bus matrix
CortexM0+DMA1

DMA2

When remappedDefault* = Adaptive Real Time Accelerator

ART*S-bus

D-bus

I-bus

Cortex-M4

Flash256 KB

SRAM1 32 KB
SRAM2 32 KB
AHB1Peripherals

APB1 Peripherals.
APB2 Peripherals.

AHB2
Peripherals
AHB3
Peripherals

APB3 Peripherals.

5Here we have the STM32WL5 bus matrix. The bus masters
are shown on top, the Cortex-M4 core, the Cortex-M0+ core
and the two DMA controllers communicate with the busslaves, shown on the right via the circled intersections.
The Flash memory is read through the accelerator. CortexM4 instructions are fetched through the Instruction bus andLiteral Pools are read through the Data bus. The SRAM1 isaccessed by default by the System bus and can beaccessed though I-bus and D-bus when it is remapped ataddress 0, shown by the dark blue circles in order toincrease performance. SRAM2 is accessible through the Ibus and D-bus allowing zero-wait-state code execution andthrough the S-bus. The AHB1, AHB2 and AHB3 peripherals
are also accessible through the S-bus.
The Cortex-M0+ also reads the Flash memory through theAdaptive Real Time accelerator (ART) and has access to theSRAM1 and SRAM2 memories and the AHB1, AHB2 andAHB Shared peripherals.
The two DMAs can access all memories and peripherals.
Different bus masters are able to access different memories
and peripherals simultaneously via the bus matrix, enablinghigh performance computing operations. Simultaneous
master accesses to the same bus is handled via round-robinarbitration.

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Cortex-m4 boot modes• BOOT0 pin or nBOOT0 option bit is selected through option bit nSWBOOT0
Boot mode selectionnBOOT1(option bit)

BOOT0 (pin)(or nBOOT0option bit)

BOOT_LOCK(option bit)

100

User Flash memory

110System memory (bootloader)

010

SRAM1000Hold, Cortex-M4 will NOT boot. Boot Cortex-M0+ instead.

xx

1

User Flash memory

CPU1 Cortex-M4 Boot mode

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There are three Cortext-M4 boot modes User Flash, Systemmemory Boot loader, and SRAM1. Which are selected by thenBOOT0 option bit or the BOOT0 pin, the option bit namednBOOT1 and the option bit named BOOT_LOCK. When theBOOT0, nBOOT1, and BOOT_LOCK option bits are set to 0,
the STM32WL5 holds the Cortex-M4 and boots on theCortex-M0+. The standard method to get the STM32WL5
Cortex-M4 core booting from User Flash is to set nBOOT1 =1 and BOOT0 and BOOT_LOCK option bits to 0.

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Cortex-m0+ boot modes
Boot mode selection• C2OPT option allows to select Cortex-M0+ boot between User Flash or SRAMnBOOT1
BOOT0 (pin)C2BOOT_LOCKCPU2
Cortex-M0+
Boot mode• BOOT0
pin or nBOOT0option
bit is selected throughoption
bit nSWBOOT0(option bit)(or nBOOT0
option bit)

(option bit)

1xx

1x

option Secure Boot Reset Vector (SBRV) and C2OPT000System memory (Secure Firmware Install)xx

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option Secure Boot Reset Vector (SBRV) and C2OPT

option Secure Boot Reset Vector (SBRV) and C2OPT

7There are two Cortext-M0+ boot modes. One is defined by
the Secure Boot Reset Vector and the CPU2 boot Option.
The other boot mode starts from System Memory SecureFirmware Install. The 2 modes are selected by the nBOOT0
option bit or the BOOT0 pin, the option bit named nBOOT1
and the option bit named C2BOOT_LOCK. When theBOOT0, nBOOT1, and BOOT_LOCK option bits are set to 0,
the STM32WL5 holds the Cortex-M4 and boots on theCortex-M0+ Secure Firmware Install located in the SystemMemory. The standard method to get the STM32WL5
booting on the Cortex-M4 core in User Flash and then theCortex-M0+ booting id to set the C2BOOT bit in the power
Controller.
The memory address the Cortex-M0+ boots from is definedby the secure boot reset vector and the CPU2 boot option.
This allows the Cortex-M0+ to boot from any word-alignedaddress in User Flash or SRAM memory.

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The BOOT0 pin or nBOOT0 option bit is selected by anotheroption bit nSWBOOT0.

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BootloaderProtocol

I/Os and Comments

USART

USART1 on pins PA9/PA10
USART2 on pins PA2/PA3

SPI

SPI1 on pins PA4/PA5/PA6/PA7
SPI2 on pins PB12/PB13/PB14/PB15

Comments

8The on-chip bootloader allows the user to program the Flashmemory through a serial communications peripheral. The
supported protocols are USART and SPI.

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Secure firmware install• Securely install Cortex-M4 and/or Cortex-M0+ software in User Flash.

9The on-chip Secure Firmware Install allows the user tosecurely install Cortex-M4 and Cortex-M0+ software in theFlash memory.

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SRAM2 features (1/2)
Performance, integrity and safety (Class B, SIL), retention in Standby• 32 Kbytes of SRAM2• with access through Cortex-M4 D-code and I-code:• Code execution maximum performance without remap• with access through S-bus:• Continuous RAM address space with SRAM1• HW parity check: 4 bits per word
• NMI generated on parity error• Optional Break to Timers• Optional retention in Standby
10The 32 Kbytes of SRAM2 is particularly suitable forperformance, integrity and safety, and low power operations.
From the Cortex-M4 core, the SRAM2 is accessed throughthe Data and Instruction busses without any remapping,which enables code execution at zero-wait-states. TheSRAM2 memory is accessible by Both CPUs through the Sbus allowing RAM address continuity between SRAM1 andSRAM2 memories.
The SRAM2 supports parity check. The Data bus width is 36
bits with 4 bits available for parity check (1 bit per byte) inorder to increase memory robustness, as required, forinstance, by Class B or SIL standards. Class B and SIL aresafety standards: Class B is for Home Appliances and SIL
for the Safety Integrity Level.
The parity bits are computed and stored when writing into
the SRAM memory. Then, they are automatically checked
when reading. If one bit fails, a Non-Maskable Interrupt(NMI) is generated. The same error can also be linked to the10

Break input of the timers.
The 32-Kbyte SRAM2 content can optionally be retained inStandby mode.

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SRAM2 features (2/2)
Secured SRAM

• Write protection with 1-Kbyte granularity• SYSCFG_SWPRn write protection register• Read/Write protection with RDP• Erased when RDP changed from Level 1 to Level 0• Software reset and optional Hardware reset when system reset• Erased when setting SRAM2ER bit• Erased with system reset with SRAM2_RST in user option bytes• Cortex-M0+ security• Cortex-M0+ exclusive access to SRAM2 areas.
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The SRAM2 memory is also suitable for secure applications.
It can be write-protected with a 1-Kbyte granularity.
The SRAM2 can also be readout-protected via the RDPoption byte. When protected, the SRAM2 cannot be read or
written by the JTAG or the serial wire debug (SWD) port,
when the boot in System flash or boot from SRAM memoryis selected. The SRAM2 is erased when the readout
protection is changed from Level 1 to Level 0. Please referto the System Memory Protections training for further details.
The SRAM2 can be erased by software by setting theSRAM2ER bit in the SRAM2 System Configuration Control
and Status register. The SRAM2 can also be erased with thesystem reset depending on the option bit SRAM2_RST inthe user option bytes.
Part of the SRAM2 can be made secure via user option
bytes, only giving the Cortex-M0+ core exclusive access to11

those areas.

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SYSCFG other features
Safety and robustness• Safety & Robustness features in Configuration register 2• SRAM2 Parity error flag
• ECC lock to connect Flash ECC error connection to TIM1/15/16/17 Break input• PVD lock to connect PVD interrupt to TIM1/16/17 Break input• SPL lock to connect SRAM2 parity error to TIM1/16/17 Break input• CLL lock to connect Cortex-M4 Hard Fault interrupt to TIM1/16/17 Break input• => Put timers in application safe state in case of application crash

12The System Configuration Register 2 contains the control
and status bits linked to safety and robustness such as theSRAM2 parity error flag, and the control bits to steer someerror detection events to the timers’ break inputs. This allows
timer outputs to be placed in a known state during anapplication crash. Once programmed, the connection islocked until the next system reset. These internal events
include a Flash error-code-correction event, a power voltage
detector event, a SRAM2 parity error event, and the Cortex
M4 hard fault.

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SYSCFG other features• Manage interconnect signal selection from GPIOx (x=A,…H)• 16 Multiplexers to select EXTI[n] signal between PA[n] PB[n] …. PH[n] (n=0,…15)• select a GPIO[n] pin to be used as• Internal interconnect trigger signals. (see Interconnect matrix for more information)• CPU interrupt and wakeup from Stop mode. (see EXTI for more information)• Other configurations• I2C GPIO Fast-mode-Plus 20 mA drive enable• I2C1 and I2C3 pins, high drive can be enabled even when not used for I2C.

• I/O analog switches voltage booster

13The System Configuration Controller manages the selectionof the GPIO as interconnect EXTI signal.
This can be used as asynchronous external interrupt or
event with capability to wake any MCU up from Stop state,
and also as an internal interconnect trigger signal toperipherals. See interconnect matrix training for moreinformation.
Other configurations are the I²C Fast-mode-Plus 20 mA drive
enable on the I2C1 and I2C3 I/Os. The high drive mode caneven be used when the pins are not used as I2C alternate
functions. For instance, they can be used to drive LEDs.
The I/O analog switch voltage booster can also be enabled.

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CPU interrupt pre-masking• To prevent peripheral interrupt to interrupt both CPUs a pre-masking is provided.
• Individual masks for interrupts sharing the same CPU NVIC vector.
• EXTIs• PVD and PVM• ADC, DAC

Other peripherals interrupts

PA0
PA
PA15

• AES

PB0

MASK

SYSCFG

INT_EXTI0

M4
MASK

CM4
NVIC

PH0

PA15
PB15

PH0PH

EXTI15MASK

INT_EXTIn

CM0+
M0+
MASK

....

.....

• RTC.....

PB
PB15

• RCC
• DMA, DMAMUX

EXTI0.....

• PKA

PA0
PB0

AIEC....

• Comparator• FlashSYSCFG

NVIC

PD15

PH3
14Peripheral interrupts sharing the same NVIC vector have apre-mask to prevent them from interrupting both CPUs.

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Related peripherals• Refer to these training modules linked to this peripheral:• Reset and clock control (RCC)• Power controller (PWR)• Interrupts (NVIC and EXTI)• Flash memory (Flash)• System memory protections• Inter-Integrated Circuit (I²C)

15In addition to this training, you can refer to the Reset andClock Control, Power Controller, Interrupts, Flash and
System Memory Protections, I²C trainings.

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References• For more details, please refer to following resources:• AN2606: STM32 microcontroller system memory boot mode
• AN4435: Guidelines for obtaining UL/CSA/IEC 60335 Class B certification in any STM32application

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For more details, please refer to application notes AN2606
STM32 microcontroller system memory boot mode andAN4435 Guidelines for obtaining UL/CSA/IEC 60335 ClassB certification in any STM32 application.

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