Achievement of 6.78-MHz and 3-kW Single
Inverter in Continuous Operation
M. Yamaguchi, Y. Uchida, H. Watanabe, K. Kusaka and J. Itoh
Nagaoka University of Technology, Japan

Abstract-- This paper proposes a design flow andimplementation method of a high-frequency and high-power
inverter for wireless power transfer(WPT) systems. This
design flow is revealed to achieve zero-voltage-switching(ZVS) operation and lower the thermal resistance for 3-kW
continuous operation in 6.78 MHz. The printed circuitboard(PCB) and a dead time design are theoreticallydescribed to achieve ZVS operation. In addition, theperformance of a heat dissipation structure for a surfacemounted device(SMD) is evaluated by comparison of three
types of heat dissipation structures to reduce the thermal
resistance effectively. As a result, the continuous operation of
the inverter is demonstrated with a 3.3 kW prototype at 6.78MHz in experimental.

S1

VDC

Recently, battery chargers have been installed widelyfor Electric Vehicles (EVs). Notably, WPT systems forbattery chargers have been actively studied for safety andconvenience [1–2]. So far, the WPT system for the EV
charger is normalized to 85 kHz. Although, the weight of
the transfer coil becomes heavy at 85 kHz. Thus, the WPTsystem with megahertz, which is 6.78-13.56 MHz as anindustrial scientific and medical(ISM) band, has been
actively studied [3–6] to reduce the weight and volume ofthe system. In order to achieve the megahertz switching, a
GaN device is usually employed in the circuit for the WPTsystem [7–8].
However, the design and implementation of the circuit,which employs a GaN device with megahertz operation,require much knowledge and know-how about the designof high-frequency circuits. Thus, the design andimplementation are complex and unclear to achieve thekilo-watts output with megahertz operation.
This paper proposes the design flow andimplementation method of the inverter circuit, which has akilo-watt output in the megahertz range. This design flow
conducts the optimization drive condition of the GaN
device with the zero-voltage switching (ZVS) and thesafety junction temperature in the megahertz operation.
Finally, the validity of design flow and circuit
implementation is demonstrated by experiment using a
3.3-kW prototype.
II. CURRENT PATH AND WIDTH DESIGN
A. Current path on PCB
Figure 1 shows the current path of the full bridge

Lr

CDC

Cr
RL

S2

S4

(a) Output current is positive (S1 & S4: ON).
S1

Index Terms—high-frequency inverter, wireless powertransfer, zero voltage switching, thermal design

I. INTRODUCTION

S3

VDC

S3
Lr

CDC

Cr
RL

S2

S4

(b) Dead time with positive current.

S1

VDC

S3
Lr

CDC

Cr
RL

S2

S4

(c) Output current is negative (S2 & S3: ON).

S1

VDC

S3
Lr

CDC

Cr
RL

S2

S4

(b) Dead time with negative current.
Fig. 1. Current flow of full-bridge inverter.




 f

1
 Spattern  4 2   d pattern
2

(2),

where w is the minimum wiring width on the current path,
Spattern is the minimum cross-sectional area required to flow
the maximum current of the wiring on the PCB, and dpatternis the thickness of the PCB pattern. Then, the minimum
wiring width w is 11.2 mm under the following conditions:the minimum cross-sectional area Spattern is 0.53-mm2, andthe thickness dpattern is 70 m.
III. ZVS OPERATION OF DEVICES
The importance of ZVS operation is very high inachieving a continuous operation with over a few kilowatts
output in the megahertz band. Then, the output current of
the inverter is expressed asi(t )  I peak sin(t   )Gate signal
Drain-Source
voltage V

vds1, vds4

S 1, S 4Time s
VDC

vds2, vds3

Time s
VDC

voutTime s
-VDC
-

Ipeak

iout

Time s(1),where  is the electric resistivity,  is the magnetic
permeability, and f is the frequency. Then, the skin depth is approximately 24 m under the following conditions:the frequency f is 6.78 MHz， the electric resistivity of
the copper  is 16-n∙m, the magnetic permeability of thecopper is 4×10H/m, which is the same as the magnetic
permeability in a vacuum.
The minimum wiring width considered the skin depth
is determined asw

Time std /2 td /2

Output voltage V

B. Pattern width of Current path
A skin-effect should be considered when designing thepattern width on PCB because the parasitic resistance of
wiring increases, especially in the megahertz band. The
skin depth  is expressed astd

S2, S3

Outputcurrent A

inverter for a WPT system. The output side of the inverter
is connected to the RLC resonant circuit as the WPTsystem. Figure 2 shows the ideal switching pattern ofdevices, drain-source voltage, and output current. The
phase delay of the output current is required to achieve theZVS operation of each device.
The charging and discharging current of the output
capacitance of devices flows between both legs during thedead time. Thus, the DC-link should be implemented todecrease the loop area, which consists of both legs and theDC-link wiring on the PCB, because the loop inductanceaffects output voltage and current.

(3),

where Ipeak is the amplitude of the output current and  isthe phase of the output current. Then, the charge amountat the output capacitance of each device during the deadtime is expressed as

Fig. 2. Current flow and ZVS operation.
Table 1. Simulation parameters.
Main circuit
DC link voltage

V DC

300 V

Switching frequency

fs

6.78 MHz

Parasitic capasitanceat drain-source of GaN-FET

C ds

130 pF

Resonant inductanceLr.0 H

Resonant capacitanceCr

100 pF

Load

td

Q

1 2
V
i  t  dt  2 DC sin( )sin(td )2 td fZ L(4),2

where VDC is the DC-link voltage, ZL is the impedance of
the RLC resonant load, and td is the dead time. Then, theminimum value of dead time to achieve ZVS operation isexpressed astd   2 fZ LQoss 
sin 1  V sin   

 DC

1

(5).

The validity of (5) is checked by simulation. Table 1
shows the simulation parameters. An additional capacitor
Cds is connected in parallel to the ideal switch as theparasitic capacitance.
Figure 3 shows the simulation result of the ZVS
operation based on the (5). The ZVS operation is achieved
when the dead time value satisfies the minimum value
calculated by (5). Thus, the equation of minimum deadtime value (5) is valid for achieving the ZVS operation.

Drain-Source
voltage vds V

300

vds1

Rth(j-a)

vds2

Tj

200

Ploss

100

Fig. 4. Equivalent thermal resistance.

(a) RL: 15 , dead time: 6.0 ns (Designed: 6.5 ns).

Surface Mounted Device

vds1

t

vds2

200

Thermal via array

100

TIM

Heatsink

50 ns/div0(a) Thermal via only.

(b) RL: 15 , dead time: 7.0 ns (Designed: 6.5 ns).
Drain-Source
voltage vds V

Solder

PCB

300

Time

300

vds1

Surface Mounted Device

vds2tHeat spreader

200
100

50 ns/div(c) RL: 30 , dead-time: 13.5 ns (Designed: 14.0 ns).
vds1

SolderHeatsink

0300

Solder

PCB

Time

Drain-Source
voltage vds V

Ta
40

Rth(PCB) Rth(TIM) Rth(Heatsink)

50 ns/div

0
Time

Drain-Source
voltage vds V

Rth(j-c)

vds2(b) Thermal via with heat spreader.
Surface Mounted Device
PCB

200

TIM

SolderCoppert

Heat spreader

100

Solder

50 ns/div0

Heatsink

Time(d) RL: 30 , dead-time: 14.5 ns (Designed: 14.0 ns).
Fig. 3. Simulation result of ZVS operation.

TIM(c) Copper block with heat spreader.
Fig 5. Thermal structure on PCB.
Table 2. Parameters of thermal components.

IV. THERMAL DESIGN OF DEVICES

Thermal conductivity of copper

k Cu

393 W/(m·K)

An optimum thermal design of devices is also essential
to continuously achieve a high-frequency and kilo-watt
operation because the thermal pad of the GaN device istiny. Figure 4 shows the thermal resistance circuit ofdevices. Then, the Rth(PCB) is the thermal resistance at the
PCB, and the Rth(TIM) is the thermal resistance of thethermal interface material. Then, the total thermal
resistance is expressed as

Thermal conductivity of solder

k Solder57.3 W/(m·K)

Thermal conductivity of air

k Air

0.026 W/(m·K)

Diameter of thermal via



0.3 mmThickness of the via

d PTH

5 m

Thickness of the PCB

d

1.6 mmNumber of via

N via

45

Thickness of cupper blockd Cu

1.5 mmWidth of cupper blockw Cu

3.0 mmR

th(PCB) Rth(TIM)  Rth  Heatsink  

kt Tjmax  Ta
PLoss

 Rth  j-c

(6),where Ta is the ambient temperature, Tjmax is the absolute
maximum value of the junction temperature, kt is thetemperature margin coefficient, and PLoss is the loss valueof each device.
The effective implementation of the thermal resistanceis investigated by comparing three cases of the thermal
configuration. Figure 5 shows the side view of eachthermal configuration. Then, the thermal resistance of
PCB and TIM are expressed as
Rth_a,b(PCB&TIM)  via d TIM(a)kTIM  wTIM(a)  lTIM(a) 

Length of cupper block

l Cu

10 mm

Thermal conductivity of TIM

k TIM

3.5 W/(m·K)

Thickness of TIM (a)d TIM(a)0.7 mmThickness of TIM (b & c)d TIM(b,c)

0.6 mmWidth of TIM (a)w TIM(a)5.0 mmWidth of TIM (b & c)

w TIM(b,c)

25 mmLength of TIM (a)l TIM(a)10 mmLength of TIM (b & c)l TIM(b,c)

25 mm

Thickness of heat-spreader

d spreader

2.0 mmWidth of heat-spreader

w spreader

25 mm

Length of heat-spreader

l spreader

25 mm

dspreader

kCu  wspreader  lspreader 



8 mm



d Cu
kCu  wCu  lCu dTIM(b,c)kTIM  wTIM(b,c)  lTIM(b,c) where d is the thickness, w is the width, l is the length, k is
the thermal conductivity of each material, and via is thethermal resistance of the thermal via. Table 2 shows eachparameter of thermal components. The thermal resistancevia is calculated by [9].
Figure 6 (a) shows the PCB board, which is used inthermal measurement, and (b) shows the measurement
configuration of the thermal resistance. The PCB board has
a footprint of a GaN-device PGA26E07BA(600V, 26A,
150℃: Panasonic) and each thermal structure. A heater isapplied on the top side of the PCB to get a thermal flow.
Then, the thermal resistance is calculated by the thermal
flow and the temperature difference.
Figure 7 shows the design and measurement value ofthe thermal resistance. Then, the filled material in thethermal via directly affects thermal resistance. In the caseof the thermal via filled-in solder, the thermal resistancediffers by about 24% compared to the case of the air.
In the thermal design, case (c) achieves a 95% decrease inthermal resistance compared to case (a). In themeasurement, case (c) also achieves a 92% decrease inthermal resistance.

V. EXPERIMENTAL VERIFICATION
Figure 8 shows the prototype circuit for 6.78 MHz
operation. The design of the current path and the thermal
implementation are applied to the prototype inverter. The
PGA26E07BA is employed as the GaN device.
Table 3 shows the experimental condition. The DC-link
voltage in the experiment is 350 V. Then, the output chargeof the GaN FET Qoss is 42 nC from the datasheet. The
minimum deadtime td based on the (5) is 6.6 ns.
Thermal condition is the same as the thermal
measurement. The copper block and the heat spreader areused in each device as the thermal structure Fig.5 (c). The
force air cooling is applied to the heatsink.
Figure 9 shows the experimental waveform of the
prototype circuit. The input power of the DC-side is 3.4kW, and the calculated output power based on themeasurement waveform is 3.3 kW. Thus, the circuit
efficiency achieves 96%.
The ZVS is achieved of devices. However, theminimum dead time value to achieve the ZVS operation islarger than the calculation about three times in theexperiment. One of the main causes is the parasitic
capacitor between each device and the heat spreader. The
required current to achieve ZVS operation increases when
the parasitic capacitor becomes large because a part of theload current charges and discharges to the parasitic

Copper block

Thermal via array

8 mm(a) Thermal via(c)(b) Via + Spreader

Copper block+
Spreader(a) Measurement board.
Styrofoam

Heater

Thermocouple

PCB
Heatsink

Thermocouple

TIM(b) Measurement structure.
Fig. 6. Thermal resistance measurement.
14.0

Thermal resistance Rth(case-heatsink) K/W

Rth_c(PCB&TIM) 

SFR : Solder Filled Ratio

12.0

TIM

10.0

Thermal via(w/o solder)

8.0

62 %

6.0

0%

4.0

100%

Thermal via(filled solder)

2.0
0.0

92 %

SFR

(a)

(b)
Designed

(c)

(a)

(b)
Measured(c)Fig. 7. Measurement result of thermal resistance.
Output terminal

Input terminal
200 mm

215 mmFig. 8. Prototype circuit operated in 6.78 MHz.
Table 3. Experimental condition.
M ain circuit
DC link voltage

V DC

325 V

Switching frequency

fs

6.78 M Hz

Q oss

42 nC

Output charge of GaN-FET
LoadResonant inductanceLr

5.8 μH

Resonant capacitanceCr

100 pF

Load resistanceRL

16.7 Ω

capacitor.
Figure 10 shows the temperature on the package of the
GaN device for one hour with continuous operation at 6.78
MHz. The package temperature saturates approximately
87℃. The temperature result indicates that the continuous
operation of the prototype is stable and safe at 6.78 MHz
without a water cooling system.

vgs1

10 V/divvds1

200 V/divvinv_out

200 V/div

0
0

0

0

iout

VI. CONCLUSIONREFERENCES[1] J. Li and D. Costinett, “Comprehensive Design for 6.78
MHz Wireless Power Transfer Systems”, 2018 IEEE
Energy Conversion Congress and Exposition (ECCE),
Portland, OR, 2018, pp. 906-913.
[2] N. K. Trung, T. Ogata, S. Tanaka, and K. Akatsu,“Attenuate Influence of Parasitic Elements in 13.56-MHz
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[3] S. Suzuki, T. Shimizu, “A Study on Efficiency
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[4] M. Fu, Z. Tang, and C. Ma, “Analysis and Optimized
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20 A/div

Fig 9. Experimental waveform.
100

Device package
temperature Tpac

This paper mentioned a design flow andimplementation to achieve a continuous operation with a3-kW class output in a 6.78 MHz band for a WPT system.
The current path and the skin effect should beconsidered in PCB design to reduce the influence of theparasitic components and the conduction loss. The skindepth determines the minimum width of the current path.
The skin depth is approximately 24 m in the case of the
6.78 MHz. Then, the minimum width was 11.2 mm for thisconsideration.
Moreover, the dead time design of the devices isnecessary to achieve the ZVS operation. The minimum
dead time to achieve the ZVS is derived from the device’s
output charges and load condition. The validity of the deadtime equation was checked by the simulation. The required
dead time is 6.6 ns in the experimental condition.
Furthermore, an optimization of the thermal design for
the PCB is also needed to reduce the thermal resistancebecause the thermal pad on the GaN device is very tiny.
The thermal resistance of the TIM decreased with a heatspreader. The thermal resistance of the PCB decreased bya copper block instead of the thermal via array. The heatspreader and copper block decreased the thermal
resistance between the device package and the heatsink byover 90%.
Finally, the prototype circuit based on the design flow
and implementation achieved 3.3 kW continuous
operation at 6.78 MHz without water cooling.

20 ns/div

80

87

60
40
20

27
0

10

20
30
40
Operation time min.

50

60

Fig. 10. Temperature of device package.

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