DATA SHEET
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110 V 2.5 A Single Channel
Floating Gate Drivers with
Desaturation Protection
and Charge Pump
FAD3151MXA, FAD3171MXA
The FAD3151MXA and FAD3171MXA are single channel floating
automotive gate drivers suitable for driving high−speed power
MOSFETs up to 110 V. Designed in a SOI technology, the drivers are
ideal for applications that require noise immunity against severe
negative transients and ground offset up to −80 V.
The FAD3151MXA/71 drivers have an integrated desaturation
detection to protect the power switches during short−circuit andover−current conditions. The drivers are also equipped with a soft
shutdown feature, which initiates a soft shutdown of driver outputs
upon desat detection, thus preventing possible overvoltage acrosspower MOSFETs during a heavy−load condition.
The FAD3151MXA/71 drivers are equipped with bidirectional fault
reporting pin that can generate a fault output during desat andunder−voltage lockout (UVLO) condition. The bidirectional nature of
the fault−reporting pin allows the driver to respond to external fault
commands, thereby facilitating fault communication across thesystem. In addition, the FAD3171MXA has an integrated charge pumpto support 100% duty cycle operation of high side MOSFETs.
In summary, the FAD3151MXA/71 are versatile drivers withfeatures like desat detection, soft shutdown, fault reporting capability,
UVLO protection, and charge pump.
Features• Single Channel Gate Driver with 110 V floating Vs capability• Negative Transient Capability up to −80 V• 2.5 A Output Source and Sink Current• MOSFET Drain−Source Desaturation Detection with Soft Shutdown• Integrated Charge Pump to support 100% Duty Cycle Operation

Typical Applications• Gate Driver for 80V and 100V MOSFETs• 48 V Belt Starter Generator• 48 V Auxiliary Motor Control (A/C compressor, e−turbo, …)• 48 V Battery Switches• 48 V DC−DC converter• PTC Heater, Active Discharge Circuit etc.

SOIC−8CASE 751EB

ORDERING INFORMATION
DevicePackage

Shipping†

FAD3151MXA

SOIC−8(Pb−Free)Tape & Reel

FAD3171MXA

SOIC−8(Pb−Free)Tape & Reel

†For information on tape and reel specifications,
including part orientation and tape sizes, pleaserefer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.

SAFETY SUPPORTSupport integration into customer’s safety
application with a set of safety documents
including FMEDA and a hardware−softwareinterface document.

(FAD3171MXA only)• Under−voltage Lock Out for both Input Logic and Output Stage• Bi−directional Fault Reporting Pin• High Speed Driver with Short Propagation Delay• dVs/dt Immune to min ±50 V/ns
• 3.3 V and 5 V Input Logic Compatible• Up to VDD Swing on Input Pins
• SOIC−8 package• Automotive Qualified to AEC Q100
• These Devices are Pb−Free and are RoHS Compliant© Semiconductor Components Industries, LLC, 2023

December, 2023 − Rev. 2

1

Publication Order Number:
FAD3151MXA/DFAD3151MXA, FAD3171MXA
48V

15V
RBOOT DBOOT
R1
R3

R4

1. V DD

8. V B

IN−High

2. IN

7. HO

FLT−High

3. FLT 6. Desat

CBOOT

D1

RG
R2

CBL

P1
5. V S

4. CO M

FAD3171MXA (with charge pump)
Optional
R1
1. V DD

8. V B

IN−Low

2. IN

7. HO

FLT−Low

3. FLT 6. Desat

CBOOT

Load

D1

RG
R2

CBL

P1
5. V S

4. CO M

FAD3151MXA
Figure 1. Application Schematic with FAD3171MXA as High Side and FAD3151MXA as Low Side drivers

UVLO(VDD)

Regulator(VDD)

UVLO(VBS)

Charge Pump
(F AD3171only)

Regulator(VBS)

VBS

DriverVDD

HOIN
Level Shifter
UP
FLT

Fault

COM

S

Q

R

Soft
Shutdown

VBS
IDESAT

Level Shifter
DOWN

Desat
VDESAT,TH

Figure 2. FAD3151MXA and FAD3171MXA (with charge pump) Block Diagram

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2

VS

FAD3151MXA, FAD3171MXAPIN FUNCTION DESCRIPTION

1. VDD

8. VB

2. IN

7. HO

3. FLT6. Desat

4. COM

5. VS

Figure 3. Pin Connection(Top View)

PIN FUNCTION DESCRIPTION
Pin #Pin Name

Description

1

VDD

Power supply for logic stage2

IN

Input command3

FLT

Bi−directional fault pin

4COM

Ground for logic stage

5

VS

Floating source connection

6

Desat

Drain to source desaturation detection pin

7HO

Output8

VB

Floating power supply for power stage

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FAD3151MXA, FAD3171MXA
MAXIMUM RATINGSTA = −40°C ~ 125°C unless otherwise noted. Voltage potentials are referenced to COM unless otherwise noted.
RatingSymbol

Value

Unit

Logic Power Supply

VDD−0.3 to 20

V

Logic Input Voltage (IN, FLT)

VIN

−0.3 to (VDD + 0.3)

V

Floating Source Voltage

VS−115 to 115

V

Floating Bootstrap Supply Voltage

VB(VS – 0.3) to (VS + 20)

V

Output Voltage

VHO(Vs – 0.3) to (VB + 0.3)

V

Desaturation Voltage

VDESAT(Vs – 0.3) to (VB + 0.3)

V

Allowable Offset Voltage Slew RatedVs/dt

+/−50

V/ns

TJ

150

°C

RthJA

200

°C/W

Maximum Junction Temperature
Thermal Resistance, Junction−to−Ambient (Note 1)
Power Dissipation at TA= 25°C

PD

0.625

W

Storage Temperature Range

TSTG−55 to 150°C

ESD Capability, Human Body Model (Note 2)

ESDHBM

2kV

ESD Capability, Charged Device Model (Note 2)

ESDCDM

500 for all pins

V

750 for corner pins
Moisture Sensitivity Level

MSL

1

−

Lead Temperature Soldering
Reflow (SMD Styles Only), Pb−Free Versions (Note 3)

TSLD

260

°C

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to the following standards:
JESD51−2: Integral circuits thermal test method environmental conditions – natural convection
JESD51−3: Low effective thermal conductivity test board for leaded surface mount packages
2. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per ANSI/ESDA/JEDEC JS−001−2012
ESD Charged Device Model tested per JESD22−C101
3. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D

RECOMMENDED OPERATING RANGESTA = −40°C ~ 125°C unless otherwise noted. Voltage potentials are referenced to COM unless otherwise noted.
Symbol

Min

Max

Unit

Power Supply

VDD

VDDUV+

18

V

Logic Input Voltage (IN, FLT)

VIN

0

18

V

High−Side Vs Floating Supply Offset Voltage

VS

−80

110

V

High−side VBS Bootstrap Voltage

VBS

VBSUV+

18

V

Rating

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.

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FAD3151MXA, FAD3171MXA
ELECTRICAL CHARACTERISTICS
VBIAS (VDD, VBS) = 15 V, VS = 0 V unless otherwise noted, TA = −40°C to 125°C. Voltage potentials are referenced to COM unlessotherwise noted.
Parameter

Test Conditions

Symbol

Min

Typ

Max

Unit

VBS Under−Voltage Positive−going Threshold

VBSUV+

6

8

10.5

V

VBS Under−Voltage Negative−going Threshold

VBSUV−

5.5

7.5

9.7

VBS Slew Rate During Startup (Note 4)

VBS(SR)

2.5

VDD Under−Voltage Positive−going Threshold

VDDUV+

POWER SUPPLY SECTIONVDD Under−Voltage Negative−going Threshold

VDDUV−

2.2

V/ms
6

V

5

mA
mA

3.9

Offset Supply Leakage Current

VB = VS = 80 V

ILK1

Quiescent VDD Supply Current

VIN = 0 V or 5 V

IQDD

270

500

Quiescent VBS Supply Current

VIN = 0 V or 5 V

IQBS

525

1000

Operating VDD Supply Current

VIN = 0 V or 5 V;
fSW = 20 kHz; CL = 1 nF

IPDD

250

600

Operating VBS Supply Current

VIN = 0 V or 5 V;
fSW = 20 kHz; CL = 1 nF

IPBS

1000

2000

Logic “1” Input threshold for IN, FLT

VIH

2.1

2.5

V

Logic “0” Input threshold for IN, FLT

VIL

70

mA

4. This limitation applies only to temperatures exceeding 105°C.
LOGIC INPUT SECTION

Logic Input High Bias Current

VIN = 5 V

IIN+

Logic Input Low Bias Current

VIN = 0 V

IIN−

Input Pull−down Resistance

1.3

1.7
48

2

RIN

80

mA
kW

FAULT SECTION
Fault Output Internally pulled down voltage level

10 kW pull up resistor to
VDD, VDESAT > VDESAT+VFLT+

Fault Output Not Internally pulled down voltage level

10 kW pull up resistor to
VDD, VDESAT < VDESAT+VFLT−

Fault Pin Pull−down Resistance

200
13.8

RFLT

Desaturation High detection threshold (Note 5)
Desaturation Bias Current

mV
V

110

kW

VDESAT,TH

2.3

3.0

4

V

IDESAT

180

320

430

mA

5. The actual desaturation threshold at the Power MOSFET can be adjusted to a value lower than VDESAT,TH with an external resistor (seeApplication Note)
GATE DRIVER OUTPUT SECTION
High−Level Output Voltage (VB − VHO)VIN = 5 V, No Load

VHOH

50

mV

Low−Level Output Voltage (VHO−VS)

VIN = 0 V, No Load

VHOL

50

mV

Source Peak Pulsed Current (Note 6)

VIN = 5 V, VHO = 0 V,
Pulse Width ≤10 ms

IO+

2.5

Sink Peak Pulsed Current (Note 6)

VHO = VBS= 15 V,
Pulse Width ≤10 ms

IO−

2.5

Allowable Negative VS pin voltage, with signal Propagation Capability from IN to HO

VS

−80

A

V

Driver Output Pull−up Resistance

IOUT = 90 mA (DC)

ROH

3

W

Driver Output Pull−down Resistance

IOUT = 90 mA (DC)

ROL

1.2

W

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5

FAD3151MXA, FAD3171MXA
ELECTRICAL CHARACTERISTICS
VBIAS (VDD, VBS) = 15 V, VS = 0 V unless otherwise noted, TA = −40°C to 125°C. Voltage potentials are referenced to COM unlessotherwise noted.
Parameter

Test Conditions

Symbol

Min

Typ

Max

Unit

VDD > VDDUV+, RL = 100 kW,
VS = 48 V

CPON

7.9

10.8

15.2

V

Turn off threshold level, referenced to VBS

CPOFF

8.3

11.2

15

V

Charge Pump VBS hysteresis

CPHYS

CHARGE PUMP SECTION [FAD3171MXA only]
Turn on threshold level, referenced to VBS

Delta (CPON − VBSUV−) (Note 7)

VDD > VDDUV+, RL=100 kW,
VS = 48 V

Charge Pump Supply Voltage
Charge Pump Output Current capability (Note 8)

VBS = CPON, VS > VS,CP

Charge Pump Oscillation Frequency (Note 6)

0.4

V

DCP,VBSUV−

1

V

VS,CP

24

V

ICP,OUT

150

mA

CPfs

5.5

MHz

7. Difference between the charge−pump turn on threshold and VBS under−voltage negative−going threshold.
8. Net output current, excluding the internal current consumption of the gate driver in steady state.
DYNAMIC SECTION
TIN_FILT40

VS = 0 V, CL = 1000 pF

tON

50

100

ns

Turn−Off Propagation Delay

VS = 0 V, CL = 1000 pF

tOFF

50

100

ns

Turn−On Rise TimeVs = 0 V, CL = 1000 pF

tR

15

25

ns

tF

10

20

ns

10

Input pulse filtering time (Note 9)Turn−On Propagation DelayTurn−Off Fall Timens

VDD and VBS Under−Voltage filtering time (Note 6)

VDD < VDDUV− or VBS<VBSUV− to VHO falls by 10%tVDDUVtVBSUV

External FLT Pulse Width (Note 10)

VFLT < VIL to VHO falls by
10%tFLT_Pulse

Desat detection to HO propagation delay

VDESAT > VDESAT+ to VHO
falls by 10% with RL= 0 W
and CL = 1 nF

TDESAT_HO

75

110

ns

Desat detection to FLT propagation delay

VDESAT > VDESAT,TH to VFLT< VFLT−

TDESAT_FLT

80

110

ns

Desaturation or UVLO
detectedtFLT_LO

FLT Locking Duration
Soft shutdown resistance

RSOFT

9. Shorter input pulses are filtered out and do not cause the output to change state.
10. The pulse width of the external fault signal at which the driver output turns off.

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6

ms

3

150

ms

550

ms

170

W

FAD3151MXA, FAD3171MXA
TYPICAL CHARACTERISTICS
20.0

100
90

18.0
RISE / FALL TIME (ns)tON / tOFF (ns)

80
70
60
50
40
30

−40

OPERATING SUPPY CURRENT (mA)

1200

−20

0

20

40

60

80

100

14.0
12.0
tF

10.0

6.0
−40

120

−

TEMPERATURE (°C)

20
40
60
80
TEMPERATURE (°C)

Figure 4. Propagation Delay vs. Temperature

Figure 5. Rise Time vs. Temperature

UVLO THRESHOLD (V)

IPDD

200

−20

0

20

40

60

80

100

7.4
7.2

−20

0

20

40

60

80

100

TEMPERATURE (°C)

Figure 7. VBS UVLO vs. Temperature

120

2.5

VDDUV+VDDUV−

3.6
3.4
3.2
3
−40

VBSUV−TEMPERATURE (°C)

LOGIC INPUT THRESHOLD (V)

3.8

7.6

Figure 6. Operating Supply Current vs.
Temperature

4.4

4

120

7.8

7
−40

120

4.6

4.2

100

VBSUV+

600

0
−40

0

8

800

400

−20

8.2

IPBS

1000

UVLO THRESHOLD (V)

tR

8.0

20
10

16.0

−20

0

20

40

60

80

100

VIH

2

VIL
1.5
1
0.5
0
−40

120

−20

0

20

40

60

80

100

120

TEMPERATURE (°C)

TEMPERATURE (°C)

Figure 8. VDD UVLO vs. Temperature

Figure 9. Logic Input Voltage vs. Temperature

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FAD3151MXA, FAD3171MXA
TYPICAL CHARACTERISTICS
3.5
SINK

3
2.5

PEAK PULSED CURRENT (A)PEAK PULSED CURRENT (A)

3.5

SOURCE

2
1.5
1
0.5
0

−40

−20

0

20
40
60
80
TEMPERATURE (°C)

100

3
2.5

SOURCE

2
1.5
1
0.5
0

120

SINK

TA = 25°C
12

Figure 10. Peak Pulsed Current vs.
Temperature

14
15
16
VBS, SUPPLY VOLTAGE (V)1718

Figure 11. Peak Pulsed Current vs. VBS
Voltage

3.7

330
325

3.5

320
315

3.3
IDESAT (mA)

VDESAT,TH (V)

13

3.1
2.9

310
305
300
295
290

2.7

285
2.5

−40

−20

0

20

40

60

80

100

280

120

0

20

40

60

80

100

120

Figure 12. Desat Threshold vs. Temperature

Figure 13. Desat Current vs. Temperature

350

14

300

13

250

CPOFF

12
11

RSOFT (W)

CHARGE PUMP THRESHOLD (V)−20

TEMPERATURE (°C)

15

CPON

10
9
8

200
150
100

7

50

6
5

−40

TEMPERATURE (°C)

−40

−20

0

20

40

60

80

100

0
−40

120

−20

0

20

40

60

80

100

TEMPERATURE (°C)

TEMPERATURE (°C)

Figure 14. Charge Pump Turn On/Turn Off
Threshold vs. Temperature

Figure 15. Soft Shutdown Resistance vs.
Temperature

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8120

FAD3151MXA, FAD3171MXA
GATE DRIVER DESCRIPTION
Figure 2 shows the block diagram of the FAD3151MXA
and FAD3171MXA (with charge pump). The section below
describes the functional characteristics of 3151/71 gate
drivers.

♦ The gate driver does not take any action and theoutput follows the input as expected.

• After 10 ms of under−voltage condition, the UVLO

circuit triggers a fault for a period equal to FLT locking
duration:♦ If the under−voltage condition lasts for a duration
shorter than the FLT locking duration, the fault pin isreleased after the FLT locking duration is over, uponwhich the driver output will begin to follow the
input logic as expected (see Figure 17).
♦ If the under−voltage condition lasts for a duration
longer than the FLT locking duration, the fault pin isreleased only after the under−voltage condition has
disappeared. The driver output will begin to follow
the input logic once the fault pin is released (seeFigure 18).
The figures below show examples of driver functionality
during various under−voltage conditions of the VBS supply;
note that the same description applies for an under−voltage
condition of the VDD supply.

Input and Fault Signal Buffer

The driver includes input and fault signal buffers to avoid
parasitic triggering due to noises at input and fault pins. The
input pin has a 40 ns filter, which means the driver output
will not change its state for an input pulse shorter than 40 ns.
Similarly, the fault pin has a 3 ms filter, which means thedriver output will not change its state for an external fault
pulse shorter than 3 ms.
VDD and VBS Under Voltage Lock Out

The gate driver has UVLO monitoring circuits with a
10 ms filter for both VDD and VBS power supplies. If the VDD
or VBS voltages were to drop below their respective UVLO
threshold:• Within the first 10 ms of an under−voltage condition(see Figure 16):

<10us

VBS

VBSUV−VBSUV+

IN

HO

FLT

Figure 16. Under−Voltage Condition Shorter than 10 ms

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FAD3151MXA, FAD3171MXA
10us

VBS

VBSUV+VBSUV−
Under voltage duration ≤ tFLT_LOIN

HO enabledHO

FLT Locking Duration(typ. 550us)

FLT

Figure 17. Under−Voltage Condition Shorter than FLT Locking Duration

10us

VBS

VBSUV+VBSUV−
Under voltage duration > tFLT_LO

IN

HO

FLT

FLT Locking Duration(typ. 550us)
HO disabled
FLT latched

Figure 18. Under−Voltage Condition Longer than FLT Locking Duration• An internal comparator that compares the voltage at theDesaturation Protection with Soft Shutdown

The gate driver has a desaturation detection circuit thatmonitors the drain to source VDS voltage of the power
MOSFET through the desaturation detection pin. As shownin the simplified block diagram in Figure 2, the desaturation
circuit comprises of:• An internal current source that provides a continuous
current toward the power stage to monitor the VDS
voltage. The desat current source (IDESAT) is supplied
from the VB pin and is continuously active as soon as
the VDD is higher than the UVLOVDD+, independent of
the status of the input logic.

desat pin (VDESAT) with the defined desat threshold(VDESAT,TH) of 3 V (typ.). When VDESAT exceeds
VDESAT,TH, the comparator simultaneously turns off theoutput ‘slowly’ and triggers a fault condition by pulling
down the fault pin internally.
As shown in application schematic in Figure 1, the desat
diode D1, resistor R1, blanking capacitor CBL, andP−channel JFET P1 are the minimum external components
required to operate the desaturation protection scheme. The
driver needs an external pull down transistor P1 to discharge
IDESAT and CBL as soon as the driver output turns off.

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FAD3151MXA, FAD3171MXA
When the voltage at the desaturation pin exceeds thedefined desat threshold, following protection sequence isperformed:• The gate driver initiates a soft shutdown. The driverwill provide a high resistive path through RSOFT for
gate capacitance to discharge slowly [see Figure 19].
The fall rate of HO is determined by the time constantof the RC discharge path.
• The driver also triggers an internal fault and pulls down
the fault pin for the period equivalent to Fault Locking
duration (typ. 550 ms).

Otherwise, the blanking capacitor will continue to charge up
and eventually trigger desat. The presence of a normally on
P1 also enhances noise immunity of desat blanking
capacitor against false triggering during the turn on event ofcomplementary power switch. The external desat
components can be modified to adjust the blanking time andthe desat detection threshold for a given application. It is
recommended to refer to the Application Note for moredetails.
If the power switch is turned−off rapidly during aheavy−load condition, the high currents may generate avoltage overshoot across the power switch that could
potentially damage it. In order to protect the devices, thedriver has a soft shutdown feature, which activates upondesat detection. The output is then driven low through a largeturn−off resistance (RSOFT) which provides a significantly
higher resistive path for the gate capacitance to dischargethan during the regular turn−off process. As a result, thepossibility of an abrupt overvoltage spike on the powerswitches is reduced.

NOTE: If the desat condition persists even after the fault
locking duration, and if the input signal is still
provided, the driver output will reappear for aperiod equivalent to the blanking time, after
which the desat protection will retrigger the soft
shutdown and turn off the output again.

VDESAT,TH

Desat

IN

Soft shutdown

HO
FLT

FLT Locking Duration(typ. 550us)

Figure 19. Desaturation Protection and Soft Shutdown

External Fault Triggerring

to logic 1). In this case, the FLT pin performs similar to an
enable pin. The external fault triggering capability allows
the interconnection of fault pins of multiple gate drivers on
both high side and low side driver stages. For example, in a
multi−phase inverter system, the fault pins of all high−side
drivers (or low−side drivers) could be tied together andcontrolled with an external controller to achieve Active
short−circuit (ASC) protection. It is recommended to referto the Application Note for more details.

The FLT pin is bi−directional in nature and is in apulled−up state for normal operation. The gate driver pulls
down the FLT pin internally during desat and under−voltage
lockout condition. As shown in Figure 20, if the FLT pin isexternally pulled down to a logic low for a period longer thanthe external FLT pulse width (min. 3 ms), the driver turns off.
It is important to note that the FLT locking duration is not
valid for external fault trigger condition. As a result, theoutput is reactivated as soon as the FLT pin is released (setwww.onsemi.com
11

FAD3151MXA, FAD3171MXA
External FLT Pulse Width(min. 3us)

FLT
(external)

IN

HO

Figure 20. External fault Triggering Condition
Charge Pump for 100% Duty Cycle Operation

It should be ensured that the total leakage current in thegate path does not exceed the maximum output current
capability of the charge pump ICP,OUT. For example, in
Figure 21, when the gate is continuously high, thepull−down resistance R2 will continuously sink a current
and for this reason, its value should be high enough tominimize the total leakage current drawn from the charge
pump. Considering a maximum output current of 150 mA at
VBS = CPON = 15 V, the value of R2 should be higher than
100 kW to maintain a steady charge pump output.

The FAD3171MXA driver contains an internal charge
pump that enables 100% duty−cycle operation of high−sidepower switches. When the high−side switch is kept on for along duration, the bootstrap capacitor could slowly
discharge and may eventually trigger the under−voltage
lockout protection and turn off the driver output. Therefore,
the purpose of the charge pump is to supply the VBS
quiescent current necessary for the high−side gate driver tooperate under 100% duty cycle and to compensate for
additional leakage current on the gate path.

48V

VDD
RBOOT DBOOT
R1
1. V DD

8. V B

2. IN

7. HO

3. FLT6. Desat

CBOOT

P1
4. COM

D1

RG

CBL

R2

5. V S

Figure 21. Leakage Current in the Gate Pathother times. The necessary conditions for the charge pumpin FAD3171MXA to activate are:
• The VDD voltage is higher than the VDD under voltage
positive−going threshold (VDDUV+)• The VS voltage is higher than VS,CP (24 V min.); below
this voltage, the efficiency of the charge pump isreduced.
• The VBS voltage decreases below the charge pump turnon threshold (CPON).

It is important to note that the charge pump is not intended
to provide gate charge during switching of power MOSFET;
rather its purpose is to only keep the MOSFET turned on. For
this, it should be ensured at the system level that thehigh−side MOSFET is not operated at very high duty cycle
or, if a high duty cycle operation is required, the off timeshould be long enough to allow the bootstrap capacitor onhigh−side gate driver to completely recharge.
In order to minimize continuous power dissipation, thecharge pump turns on only when needed, and remains off at

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FAD3151MXA, FAD3171MXA
The charge pump deactivates as soon as:• The VBS voltage rises back to a value higher the charge
pump turn off threshold (CPOFF).
• The VDD is lower than the VDD under voltage
negative−going threshold (VDDUV−).
In order to ensure that the charge pump and the UVLO
function do not interfere with each other, the charge pumpturn−on threshold (CPON) is designed to be higher than the
VBSUV− threshold. As a result, the driver output is higher
than the VBSUV− threshold during charge pump mode. If theload on the charge pump exceeds ICP,OUT, the voltage acrossthe VB−VS pins will slowly decrease and eventually trigger
the under−voltage lockout protection and turn off the driver
output.

Switching Time Definitions

7. HO

3. FLT 6. Desat
4. COM

5. V S

Figure 22. Switching Time Test Circuit

IN

HO
Figure 23. Input / Output Timing Diagram

IN

50%
tON

50%
tr

tOFF

tf

90%

90%

HO
10%

10%

Figure 24. Switching Time Waveform Definitions

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VBS=15V

2. IN

1uF

8. V B
100nF

1. V DD

1nF

100nF

1uF

10k

VDD=15V

FAD3151MXA, FAD3171MXA
PACKAGE DIMENSIONSSOIC8CASE 751EB
ISSUE Awww.onsemi.com
14

DATE 24 AUG 2017

FAD3151MXA, FAD3171MXA

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