Hello and welcome to this presentation of the STM32F7
Analog-to-Digital Converter block. It will cover the mainfeatures of this block, which is used to convert theexternal analog voltage-like sensor outputs to digitalvalues for further processing in the digital domain.

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The analog-to-digital converters inside STM32 products
allow the microcontroller to accept an analog signal, likea sensor output, and convert the signal into the digitaldomain. There are 16 to 24 analog inputs available
across the three ADCs. The ADC module itself is a 12-bit
successive approximation converter. The sampling
speed is two mega samples per second. Each ADC
module integrates an analog watchdog. The data can bemade available either through DMA movement orinterrupts. There are a number of triggering mechanisms
and the data management can be configured to minimize
the CPU workload.

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3 analog-to-digital converters are integrated inside
STM32F7 products. The input channel is connected toup to 24 GPIO channels capable of converting signals ineither Single-end or Differential mode. The ADCs canconvert signals in excess of 5 mega samples per
second. There are several functional modes which will
be explained later. There are also several different
triggering methods. In order to offload the CPU, the ADC
has an analog watchdog for monitoring thresholds.

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This slide shows the general block diagram for the 3
analog-to-digital converters embedded in the STM32F7.

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The ADC supports up to 2.4 mega samples per second ofconversion. By using triple interleaved mode, it can beextended to 7.2 mega samples per second. The sequencer
allows the user to convert up to 16 channels in any desiredorder. Also each channel can have different sampling period.
The ADC offers an auto calibration mechanism. It is
recommended to run the calibration on the application if thereference voltage changes more than 10% so this would
include emerging from RESET or from a low power state
where the analog voltage supply has been removed andreestablished.

5The ADC needs a minimum of 3 clock cycles for thesampling and 12 clock cycles for the conversion. With an36 MHz ADC clock, it can achieve 2.4 mega samples persecond. For higher speed sampling, it is possible toreduce the resolution down to 6 bits then the sampling
speed can go up to 4 mega samples per second.

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The sampling time can be programmed individually foreach input channel of the analog-to-digital converters.
The sampling times listed in this slide in ADC clock
cycles are available. Longer sample times ensure thatsignals having a higher impedance are correctlyconverted.

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The ADC has two clock domains, one for the interface
and another for the analog core. The analog clock input
has a prescaler to select the clock speed.

8The ADC supports several conversion modes:–Single mode, which converts only one channel, in
single-shot or continuous mode.
–Scan mode, which converts a complete set of predefined programmed input channels, in single-shot orcontinuous mode.
–Discontinuous mode, converts only a single channel at
each trigger signal from the list of pre-definedprogrammed input channels.

9Each ADC has an integrated analog watchdog with highand low threshold settings. The ADC conversion value iscompared to this threshold window. If the result exceeds
the threshold, an interrupt or external signal can begenerated or a timer can be immediately stopped without
CPU intervention.

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In normal scan conversion mode, the conversion isrepeated for all channels one by one.
If an injected conversion is started, the ADC stops
converting the normal conversion channels and proceed toconvert the injected configured channel. At the end of all
injected channels conversion, the ADC resumes theconversion from the channel where the normal conversion
was stopped.
When the trigger occurs, the regular conversion needs to befinished before the ADC proceeds to the injectedconversion.

The ADC conversion result is stored in a 16-bit dataregister. The system can use CPU polling, interrupts orDMA to make use of the converted data. An overrun flagcan be generated if data is not read before the next
converted data is ready. For injected channel
conversions, 4 dedicated data registers are available.

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An injected conversion is used to interrupt the regularconversion, then insert up to 4 channel conversions.
Once an injected conversion is finished, the regularconversion sequence can be resumed. The injected
conversion result is stored in dedicated data registers.
Flags and interrupts are available for the end ofconversion or end of sequence. The choices for an
injected channel can be reprogrammed on the fly. Even if
a regular or injected conversion is in progress, you canadd a different channel to the queue so that next injectedchannel can be different from the previous one.

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Each ADC can generate 4 different interrupts: end ofconversion, end of injected conversion, analog watch
dog, and data overrun.
DMA requests can be generated at each end ofconversion when the ADC output data is ready.

The ADCs are active in Run and Sleep modes. In Stopmode, the ADCs are not available but the contents oftheir registers are kept. In Standby mode, the ADCs arepowered-down and must be reinitialized when returning
to a higher power state. There is a Deep power-down
mode in each ADC itself which reduces leakage byturning off an on-chip power switch. This is therecommended mode whenever an ADC is not used.

The following table shows performance parameters forthe ADC.

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The STM32F7 embeds three ADCs. ADC 1, ADC 2 andADC 3 can be configured to work together in Dual orTriple mode, so that each analog-to-digital conversion
can be synchronized between the two or three modules.

These peripherals may need to be specifically configured
for correct use with the ADCs. Please refer to thecorresponding peripheral training modules for more
information.

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Several application notes dedicated to analog-to-digitalconverters are available. To learn more about ADCs, you
can visit a wide range of web pages discussing
successive approximation analog-to-digital converters.

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