Modeling of EBG Power Bus using Segmentation Method for GHz Noise Isolation
Myunghoi Kim, Kyoungchoul Koo, and Joungho Kim
Terahertz Interconnection and Package Lab., Dept. of EE, KAIST
373-1 Guseong-dong, Yuseong-gu, Daejeon 305-701, South Korea

mhkim80@kaist.ac.kr

Abstract
In this paper, we present a new modeling approach based on a segmentation
method for noise isolations of a power bus in which partial electromagnetic bandgap(EBG) structures are embedded. When the EBG structure is inserted partially in the
power bus, the stopband characteristics such as the cut-off frequencies and the noise
isolation level are different from those predicted by the models assuming infinite EBG
cells. The proposed modeling approach enables to predict the noise coupling coefficientof the partial EBG power bus accurately in the stopband as well as the passband. In
the proposed modeling, the partial EBG power bus is divided into three segments ofthe partial EBG structures and the different size rectangular power/ground planes.
The partial EBG structure is further divided vertically and modeled as thetransmission line networks with via structure and a rectangular plane cavity model.
The proposed modeling approach based on the segmentation method has beenvalidated by good agreement between the modeling result and the electromagnetic
simulation result.

1. INTRODUCTION
In the design of the highly integrated
mixed-signal systems with fast edge rates andhigh switching frequencies, electromagnetic
bandgap (EBG) structures have been studied as anefficient way to suppress the power/ground noise
coupling and achieve the high noise isolationlevel in multi-layer printed circuit boards (PCBs).
The partial EBG structures, especially, haverecently been attracting attentions due to the smallarea,
maintaining
the
power
integrity
characteristics and minimizing the effect of thereference plane on the signal lines [1]-[4].
In the partial EBG power bus, an EBG cell or a
few EBG cells are placed locally on the port
locations or the array of the EBG cells is inserted
between the noise source and the victim. The
small and finite numbers of the EBG cells in thepartial EBG power bus guarantee the power
integrity and the solid reference plane. However,
due to the insufficient number of EBG cells there
is no clear stopband in the partial EBG power bus.
Therefore, the noise isolation level needs to bepredicted cautiously for the partial EBG powerbus. Most previous studies on the modeling of the
EBG structure are focused on predicting the
cut-off frequencies of the stopband [5]. It isdifficult to apply the previous modeling approachto the partial EBG power bus to predict the noise
isolation.
In this paper, we present a new modelingapproach using segmentation method and a cavity
model for the prediction of the noise isolation of
the partial EBG power bus in multi-layer PCBs.
The modeling approach provides a simple
modeling
and an accurate result. In the
proposed modeling, the partial EBG power bus isdivided into partial EBG structures andrectangular power/ground planes. The partial
EBG structure is modeled as transmission line
networks combined with a cavity model. The
rectangular power/ground planes are modeledusing cavity models. Finally, the noise coupling
coefficient for the noise isolation prediction is
obtained using the segmentation method withimpedance matrices of each model.
2.

SEGMENTATION METHOD FOR PARTIAL
EBG POWER BUS
A partial EBG power bus with Z-shape EBG
structures in multi-layer PCBs is introduced in [4].
It shows the wideband suppressions of noise
coupling and high noise isolation level. We
adopted the partial EBG power bus introduced in[4] for noise isolation modeling. The partial EBG

power bus consists of the irregular shaped
power/ground planes and the four rectangular
EBG patches as shown in Fig. 1. The Z-shapebranches are formed in the center of the power
plane. The EBG patches are embedded between
the power plane and the ground plane. The EBG
patches are connected with Z-shape branchthrough vias.
A. Segmentations of Partial EBG Power Bus
In the segmentation method an irregularstructure can be considered as a combination ofseveral simple parts based on the theory of
Shelkunoff’s equivalence principles [6]. We
assume that the electric current sources are placedon both sides on the boundary of the segments
and the tangential fields remain the same as theoriginal partial EBG power bus. The couplings
between the segments are ignored in the proposedmodeling. Then, the partial EBG power bus canbe divided into three parts which are rectangularpower/ground planes and the partial EBG
structure as shown in Fig. 1. The rectangularpower /ground planes are the segment 1 andsegment 3 which can be modeled as therectangular cavities. Two partial EBG structures
are in the segment 2. A partial EBG structure
consists of a Z-shape branch, two EBG patches,
and the corresponding ground plane. The Z-shapebranch connects the power plane of segment 1
with the power plane of segment 3.

(c)
Fig 1. (a) Top view, (b) cross-sectional view of the partial
EBG power bus and (c) the segmented partial EBG power bus
for prediction of the noise isolation using segmentation
method.

For the segments, we define the group of ports
denoted as p, q, and r. The ports are definedvertically between the power plane and theground plane. The segments are connected with
the internal ports p2, p3, q1, q2, q3, q4, r1, and r2.
The port pairs of (p2, q1) and (p3, q3) connect therectangular cavity of the segment 1 with thepartial EBG structure of the segment 2. The portpairs of (q2, r1) and (q4, r2) connect the partial
EBG structure of the segment 2 with therectangular cavity of the segment 3. The
corresponding internal ports are connected to eachother with holding the continuity of the current.
The port p1 and r3 are the external ports. The
corresponding ports of p1 and r3 are the port 1 andport 2, respectively in the original partial EBG
power bus.
B. Impedance Matrices of Segmented Partial
EBG Power Bus
All port voltages and currents of the segment 1
and the segment 3 are related by the impedance
matrix, which can be obtained from the analytical
impedance expressions using the cavity model [7].
The Zp and Zr which is the impedance matrix ofthe segment 1 and the segment 2 are given by,
2
2
" "
Cm Cn
Z p ,ij # j&' ( h1 % h2 ) !!
2
2
2
m #0 n #0 Wx _ seg 1W y _ seg 1 ( k p , xm % k p , yn $ k )(a)( cos( k p , xm x p ,i ) cos( k p , yn y p , i ) cos( k p , xm x p , j ) cos( k p , yn y p , j )
(1)
and
"

(b)

"

2

2

C m Cn2
2
2
m #0 n #0 Wx _ seg 3W y _ seg 3 ( k r , xm % k r , yn $ k )Z r ,ij # j&' ( h1 % h2 ) !!

( cos( k r , xm x r ,i ) cos( k r , yn y r ,i ) cos( k r , xm xr , j ) cos( k r , yn y r , j )(2)where the index i and j represents the port number
1,2, and 3. The m and n represents the mode
number associated with the cavity size. The xp, yp,
xr, and yr are the locations of the ports. The otherterms such as the constant Cm, Cn, and the wave
number k are explained in [7].
The segment 2 consists of two identical partial
EBG structures. The impedance matrix Zq of thesegment 2 is partitioned into submatrices. Then,. Z e,11,Z
e , 21
Zq # ,, 0,- 0

Z e,120Z e, 2200Z e,110Z e , 21

(a)

0 +
0 )
)
Z e,12 ))Z e ,22 *(3)
where Ze,ij (i,j=1,2) is the matrix entry of the
impedance matrix Ze for a partial EBG structure
which will be derived in the next section. The
total impedance matrix Zt of the segmented partial
EBG power bus is expressed in terms of eachmatrix of the segments as shown in Fig. 2.

(b)Fig. 3. (a) Top view of the partial EBG structure and (b)cross-sectional view and vertical segmentation of the EBG cellFig. 2. Impedance matrices of the segmented partial EBG
power bus.

The impedance matrix Zt can be found using
the impedance matrix equations in [8]. The
impedance matrix equation introduced in [8]enables to eliminate the internal ports and find theimpedance matrix with only external ports. When
we obtain the impedance matrix Zt, then the noise
coupling coefficient S21 can be calculated from Zt
using the simple equation in [9].
3. MODELING OF PARTIAL EBG STRUCTURE
As mentioned in the introduction, it isimportant to predict the noise isolation level in thepartial EBG power bus. The modeling of thepartial EBG structure is crucial to the noise
isolation level. The partial EBG structure consistsof the bended transmission lines and the EBG
cells as shown in Fig. 3 (a). The EBG cell consistof the narrow branch on the power plane, theEBG patch, and the corresponding ground plane
as shown in Fig. 3 (b).

In multi-layer PCBs, the skin depth is usuallysmaller than the metal thickness of the EBG patch
over MHz frequencies and the noise cannot
propagate inside the EBG patch vertically. So, we
can ignore the vertical coupling through the EBG
patch. Then, the EBG patch can be divided into
two patches which connect at edge. Due to theseparated EBG patches, the EBG cell can bedivided vertically into the transmission line
networks with a via and the rectangular cavity.
The narrow branch connecting the upper plane of
the segmented EBG patch through a via forms thetransmission line networks with a via. The lower
plane of the segmented EBG patch and thecorresponding ground plane form the rectangularcavity. A noise current should detour the surfaceof the EBG patch at edges because it can only
flow on the surface of the EBG patch. The upper
EBG patch and the lower EBG patch areconnected at the edge. We define the port A1, A2,
B1, B2, C1, and C2 as shown in Fig. 3 (b). The
impedance matrix Zc can be obtained in terms ofZa and Zb, then. Z a ,11 % Z b,11
Zc # ,- Z a , 21 % Z b, 21

Z a ,12 % Z b,12 +Z a , 22 % Z b, 22 )*(4)
To find the impedance matrix Za of thetransmission line networks with a via, the ABCD
matrix is used. The transmission line networks
with a via can be modeled into a combination oftransmission lines and inductance as shown in Fig.
4.

Fig. 4. The ABCD matrix model of the transmission line
networks with a via.

The ports are located at the center of the edges.
Then, the impedance matrix Zb is given by,
2
2
" "
Cm Cn
Z b,ij # j&'h1 !!
2
2
2
2m # 0 n # 0 (W patch ) ( k b , xm % k b , yn $ k )( cos( k b , yn

W patchW) cos( k b , xmW patch ) cos( k p , yn patch )2
2(6)
The total impedance matrix of the partial EBG
structure is obtained and this impedance matrix isequal to the impedance matrix Ze. Finally, we canfind the impedance matrix Zt for the noise
isolation of the partial EBG power bus.
4. MODEL VALIDATION
To validate the proposed modeling, the noise
coupling coefficient calculated from the proposedmodel is compared with the electromagnetic (EM)simulation result using Ansoft SIWAVE. The
noise coupling coefficient S21 is compared in thefrequency range from 0.1GHz to 10GHz. The
simulation structure consists of three layers which
are the power plane layer, the EBG patch layer,
and the ground plane layer. The lossy FR-4 (losstangent: 0.02) is used as a dielectric material. The
copper is used as the metal, the conductivity ofwhich is 5.8x107S/m. The simulation structureand dimensions for the validation of the model are
shown in Fig. 5 and Table 1, respectively.

The total ABCD matrix can be calculated fromthe result of the equations below.

WW +.
Z o sinh(0 / cell ))cosh(0 / cell ).A B+ ,
2
2)
,C D ) # , 1
WW* , sinh(0 / cell ) cosh(0 / cell ) )
2
2
- Z0
*

Fig. 5. The simulation structure for the model validation

TABLE 1

. 1
(, 1
, j&L
via
-

W
W +
.
Z o sinh(0 / cell )) DIMENSIONS AND DESIGN PARAMETERS FOR THE VALIDATION
0+ , cosh(0 / cell )221)) , 1
Wcell
Wcell )OF THE MODEL* , Z sinh(0 / 2 ) cosh(0 / 2 ) )
- 0
*

(5)
where ZO is the characteristic impedance. The !
represents the propagation constant. The ABCD
matrix can be converted into the impedance
matrix Za using the equations in [9]The impedance matrix Zb is obtained using theresonant cavity model. The rectangular cavity isformed by the EBG metal patch and thecorresponding ground plane. The width of therectangular cavity is Wpatch and the height is h1.

Design parameters and Dimensions(Unit: mm)

Wx_seg120

Wy_seg122

Wx_seg3
Wpx_seg128
5

Wy_seg3
Wpy_seg1

364

Wpx_seg39Wpy_seg3

12

Wcell

4.2

Wpatch

4

WL

0.6

t

0.018

h1

0.1

h2

0.8

Fig. 6 depicts the calculated result using the
proposed modeling approach and the EM
simulation result. As shown in Fig. 6, theproposed modeling approach successfully predicts
the resonance peaks and the noise isolation level,compared to the EM simulation result.

Fig. 6. The noise coupling coefficients which illustrate that
good agreement validates the proposed modeling approach.

The proposed modeling approach forpredicting the noise isolation level of the partial
EBG power bus in multi-layer PCBs is validated
by good agreements between the calculated result
from the proposed model and the EM simulation
result.
5. CONCLUSION
We have presented a new modeling approachbased on a segmentation method using impedance
matrices to predict the noise isolation of thepartial EBG power bus. The proposed modelingapproach provides the analytical model, theaccurate result, and a simple modeling without theefforts to extract the equivalent circuit parametersof the partial EBG structure. The analytical modelfrom the proposed modeling approach provides
the accurate result and reduced the computationaltime, compared to the EM simulation result.
Further to enhance the modeling, the coupling
between the EBG patch and the segment 1, 3 canbe included in the modeling, which causes thediscrepancy of high-frequency peaks in the S21
result.
ACKNOWLEDGMENT
This work was supported by the National
Research Foundation of Korea (NRF) grant
funded by the Korea government (MEST) (No.
2010-0029179)
REFERENCES[1] Jong Hwa Kwon, Dong Uk Sim, Sang Il Kwak, andJong Gwan Yook, “Novel Electromagnetic Bandgap
Array Structure on Power Distribution Network for
Suppressing,” ," IEEE Trans. Electromag. Compat., vol.
52, no.2, pp. 365-372, May 2010.
[2] Lin, D.B., Hung, K.C., Wu, C.T., and Chang, C.S.,“Partial uniplanar compact electromagnetic bandgap
combined with high-impedance surface to suppress,”
Electronics Letters, vol. 45, no. 16, July 2009.
[3] J. Lee, Y. Kim, E. Song, and J. Kim, "Partial EBG
power distribution network using remants of signal
layers in multi-layer PCB," in Proc. 2006 IEEE Int.
Symp. Electromag. Compat., Portland, OR, Aug. 14-18,
pp. 43-46.
[4] Myunghoi Kim, Changwook Yoon, Woojin Lee, Hajin
Sung and Joungho Kim, “Power/Ground Noise
Mitigation Using Z-shape Partial Electromagnetic
Bandgap (ZP-EBG) Structure for Ultra-Wideband(UWB) System,” 2010 Asia-Pacific Radio Science
Conference (AP-RASC'10) , Sep. 2010.
[5] S.D. Rogers, “Electromagnetic-bandgap layers forbroad-band suppression of TEM modes in power
planes,ā IEEE Trans. Microw. Theory Tech., vol. 53,
no. 8, pp. 2495-2505, Aug. 2005.
[6] R. E. Collin, Field Theory of Guided Waves. New York:
Wiley-IEEE Press, 1990, pp. 37–39.
[7] G. T. Lei, R.W. Techentin, and B. K. Gilbert,“High-frequency
characterizationofpower/ground-plane structures,” IEEE Trans. Microw.
Theory Tech., vol. 47, no. 5, pp. 562–569, May 1999.
[8] T. Okoshi, Planar Circuits for Microwaves andLightwaves, Munich, Germany, Springer-Verlag, 1985,
Chapter 2.
[9] D. M. Pozar, Microwave Engineering, 2nd ed. New
York: Wiley, 1998,

Efficient Electromagnetic Simulation of Angled and Thin Structures
by Using CFDTD and HIE-FDTD Methods
Hideaki Muraoka*, Hideki Asai**
Department of Systems Eng., Graduate School of Eng., Shizuoka University*
e-mail: muraoka@tzasai7.sys.eng.shizuoka.ac.jp**
e-mail:㻌hideasai@sys.eng.shizuoka.ac.jp

Abstract
In this paper, we propose an effective electromagnetic simulation technique which isconstructed by combining the conformal FDTD (CFDTD) method and the hybrid
implicit-explicit (HIE)- FDTD method. The proposed technique can circumvent the above
problems by exploiting advantages of the HIE-FDTD method and the CFDTD method.
zDielectric layerThefinite-differencetime-domain(FDTD) method is one of the powerfulelectromagnetic simulation techniques forsolving Maxwell’s equations. Since the
FDTD method is based on the explicit timemarching method, it has a limitation on thetime step size related to the numericalstability condition. Concretely, the maximum
time step size used in the simulation, Δt isselected so that the following CourantFriedrichs-Lewy(CFL) condition is satisfied:
1

Dt £
v

(Dxmin )- 2 + (Dymin )- 2 + (Dzmin )- 2x69.6 mm
Load resistanceD

2.0 mmB
C
A

60.2 mm
5.0 mm60.2 mm

Voltage source

Load resistance
Ground plane

Fig. 1. CAD model of PCB, where twointerconnection patterns are angled 30 degrees
toward x axis.
ǼxSubcell(1)where Δxmin㸪Δymin, and Δzmin are minimum
lengths of the Yee's cell in x, y, and z
directions, respectively, and v is a maximum
wave velocity in medium.
Fig. 1 shows the computer-aided design(CAD) model of an angled interconnection
pattern on a printed circuit board (PCB). The
object to be analyzed is discretized finely inx and y directions to approximate the angledinterconnection pattern accurately. Hence, Δzbecomes extremely small compared withthose of other directions. As a result, thesefacts increase the total number of the cells,
and require an extremely small time step size
to satisfy (1).
In this paper, we propose an efficientelectromagnetic simulation technique for theangled interconnection pattern on the PCB
by exploiting the advantages of the CFDTD
and HIE-FDTD methods. The advantages
provide smaller number of cells and larger
time step sizes.

Interconnection pattern
69.6 mmy

1. Introduction

: Ex

b

c

: Ey
: Hz Ǽy
PEC

y
a
z

x

(i,j,k)Sz
Vacuumdlylx

Fig. 2. Electromagnetic fields arrangement in
the vicinity of PEC.

2. Conventional methods
The CFDTD method employs a subcell
scheme instead of the standard Yee’s cellmethod for the discretization of the angled
pattern which are shown in Fig. 2. [1] showsthat the subcell is easily exploited byincluding parameters of the subcell into thecoefficients of updating formulas in theconventional FDTD method. Because of
these characteristics, the CFDTD method iseffective for the simulation of theDt HIE £1v-2(Dxmin ) + (Dymin )-2(2)

3. Proposed method
In this section, we formulate the efficientelectromagnetic simulation technique by
exploiting the advantages of the CFDTD and
HIE-FDTD methods. In the proposed
method, not only the subcell is used for x
and y directions but also the hybrid
implicit-explicit finite difference scheme isapplied to the differential operator withrespect to time in z direction. Therefore,
Δxmin and Δymin can be enlarged, and the time
step size is determined by (2) similarly to the
HIE-FDTD method.
In order to generate updating formulas,
we focus on the feature of the CFDTD
method as mentioned in [1]. The updating
formula is led in a vector-matrix form:(3)
K1 × u n +1 = K2 × u n
where n denotes a time index, and u is theunknown vector composed of electric andmagnetic field vectors as shown in [3]. K1
includes the parameters of the subcell
defined in the CFDTD method. Additionally,
these values are stamped to the same
positions in a coefficient matrix of the
HIE-FDTD method. As a result, thecomputational complexity of the proposed
method is the same as that of the HIE-FDTD
method.

4. Numerical result
we applied the proposed method to theangled interconnection pattern illustrated inFig. 1 to estimate the accuracy and theefficiency of our approach. The details of

FDTD method
CFDTD method

0.01

HIE-FDTD method
Proposed method

Voltage[V]complicated structure compared with theconventional FDTD method.
The HIE-FDTD method employs the
hybrid implicit-explicit finite difference
scheme[2], which is different from the oneused in the conventional FDTD method, toapproximate a differential operator withrespect to time. Concretely, if the object tobe analyzed is discretized finely in z
direction, the differential operator withrespect to time in z direction is discretized
implicitly. As a result, in the HIE finite
difference scheme, the minimum cell size isfree from (1) as shown below:

0

−0.01
0

Fig. 3.

Time[ns]1

Waveform results at D in Fig. 1.

example circuit are shown in [3].
The waveform results at the observation
point D is illustrated in Fig. 3. Because ofusing the subcell scheme, the results of the
CFDTD method and the proposed method
agree with those of the FDTD method. Thismeans that the proposed method can obtain
the accurate result even if the coarse grid isemployed. Additionally the proposed method
is about 42.8 times faster than the FDTD
method. As a result, the proposed method ismore effective than the conventional
methods for the simulation of the angledinterconnection pattern on the PCB.

5. ConclusionIn
thispaper,
theefficientelectromagnetic simulation technique has
been developed for the analysis of the angledinterconnection pattern on the PCB based on
the CFDTD method and the HIE-FDTD
method.

References[1] S. Benkler and N. Chavannes, “A new
3-D conformal PEC FDTD scheme withuser-defined geometric precision andderived stability criterion,” IEEE Trans.
Antennas Propag., vol. 54, no. 6,
pp.1843–1849,Jun. 2006.
[2] J. Chen and J. Wang, “A threedimensional semi-implicit FDTD scheme
for calculation of shielding effectivenessof enclosure with thin slots, ”IEEE Trans.
Electromagn. Compat., vol. 54, no. 6,
pp.354–360, May2006.
[3] H. Muraoka, M Unno, S Aono and H
Asai , “ Efficient Electromagnetic
Simulation of Angled Interconnection
Pattern by Conformal- and HIE-FDTD
Methods,” In Proc. IEEE EDAPS2011,
Dec. 2011.

Three Types of Interconnect Analysis Schemes
Based on Latency Insertion Method
Hiroki Kurobe† and Hideki Asai†, †††Dept. of Systems Engineering, Graduate School of Eng., Shizuoka University††
Dept. of Systems Eng., Shizuoka University
3-5-1, Johoku, Naka-ku, Hamamatsu-shi, 432-8561, Japan
TEL: +81-53-478-1237 FAX: +81-53-478-1269†
E-mail: kurobe@tzasai7.sys.eng.shizuoka.ac.jp††
E-mail: hideasai@sys.rng.shizuoka.ac.jp

Abstract
This paper describes three types of interconnect analysis schemes based on the latency
insertion method (LIM). First, some features and the limitation of the time step size for the
LIM are described. Next, to overcome the inherent problems and expand the applicable scopeof the LIM, three types of improved schemes are developed. Finally, numerical results showthat our methods are useful and efficient for the simulations of large interconnect
networks.
i j2

1. Introduction

i jn ji j1

B

Significant
advancesofthesemiconductor packaging technology
have provided complicated designs ofhigh-speed and high-density electronic
circuits. Various effects related to thehigh-frequency characteristics of signals
induce unexpected behaviors, such as
signal delay, reflection, and crosstalk,which directly degrade the signal
integrity of interconnect networks on a
printed circuit board (PCB). In order todeal with detailed behaviors of thoseeffects, equivalent circuits of theinterconnects tend to be composed of alarge number of linear elements. These
facts force a large amount of simulation
cost for a conventional SPICE-likesimulator, and therefore, some kind offast and accurate simulation method isstrongly needed.
The latency insertion method (LIM) is
one of the finite difference time domain(FDTD)-based transient analysis methods forthe fast simulation of the large interconnects[1]. However, since the LIM is based on the
explicit method, it has a limitation on thetime step size to satisfy the numericalstability condition shown in [1].
In this paper, in order to overcome thelimitation of the LIM, three types ofimproved LIM are described.

R jk

L jk

E jk
-

Gj

Cj H j
(a)

vj

i jk

+

vk

(b)

Fig. 1. Network topologies required for the
LIM. The arrow corresponds to the direction of
branch current. (a) Node topology; a parallel
combination of the grounded capacitance Cj, theconductance Gj, and the independent current
source Hj. (b) Branch topology; a serial
combination of the inductance Ljk, the resistanceRjk, and the independent voltage source Ejk.

The remainder part of the paper isorganized as follows. In Section II, theconventional LIM is reviewed. Section III,IV, and V describe the concepts and thefeatures of the ADE-LIM, the PC-LIM, andthe LILIM. Finally, conclusions aredescribed in Section V.

2. Basic LIM
The LIM is one of the fast and powerful
circuit simulation techniques based on the
explicit leapfrog scheme [1]. The LIM
assumes that a network to be analyzed iscomposed of the node and the branch
topologies shown in Fig 1.

First, the Kirchhoff’s current law (KCL)
and the Kirchhoff’s voltage law (KVL) areapplied to the node topologies and thebranch topologies in the network, and thefollowing equation
Cj

L jk

dv j
dt
di jk

dt

+ G jv j = -n Bjåi + H ,

(1)

j

jk

n+

1

+ R jk v jk = v j - vk + E jk ,Cjn-

C j + DtG j

(2)

1

vj 2

æ nB nöDt
ç- i + H n ÷ ,jjk÷C j + DtG j çè k =1
øj+i njk+1 =aFig. 2.

å

L jk - DtR jk
L jk

i njk

n+
n+ ö
Dt æ n + 2
ç v j - v k 2 + E jk 2 ÷ ,÷ç
L jk è
ø
1

+

(3)

1

1

(4)

where n and ∆t indicate the time index andthe time step size. Note that each of thevoltage and current variables is arranged
alternately in every half time step due to theleapfrog scheme. Thus, the LIM can performthe fast and accurate analysis compared withthe matrix-based SPICE-like simulators.
Since the LIM is based on the explicit
method, it has the limitation on the time step
size to satisfy the numerical stability
condition similar to the CFL one. Concretely,
the maximum time step size of the LIM,
∆tmax, has the following upper bound [1,2]:
nBj
nN æ Cöj(L jm ) ÷÷ ,Dt max < 2 minç
min
j m=1
j =1 ç
øè nB(5)

where nBj is the number of the branches
connected to the node j, Ljm is the value ofthe inductor in the m-th branch connected to
the node j, and Cj is the value of thegrounded capacitor connected to the node j.
Clearly, ∆tmax is limited by the minimum
value of the reactive elements in the circuit.
Therefore, if the small and fictitious
elements are inserted into the circuit, ∆tmax
becomes extremely small, and the simulation
cost increases significantly.

cb

Example circuit.

3. ADE-LIM

k =1

are derived. Then, by applying the finite
difference method based on the leapfrog
scheme to (1) and (2), the updating formulasof the node voltage and the branch current
are lead as
vj 2 =

Negative
Positive

In order to overcome the limitation of thetime step size, we consider to introduce theADE scheme [3] and propose the ADE-LIM[4, 5], which contains two updating steps,
namely, Positive and Negative. Fig. 2 showsthe example circuit to explain the updating
steps. In Fig. 2, the ADE method is applied
to the KCL equation obtained from the nodeb, then, the following differential equation isled asvPn +,b1 =CbDt
iPn ,+ab1 + ibcn ,vbn +Cb + DtGb
Cb + DtGb

(

)

(6)

where P denotes the Positive. Then, theimplicit difference equation of (2) based on
the backward Euler method is substituted
into in+1 in (6). This treatment leads thefollowing updating formula,(1 + b a )v
b

ab

n +1
P ,b

- n +1- b b-a ab
v P ,a =b b+ vbn + b b-a ab+ iabn - b b- ibcn ,(7)where α and β are the coefficients. Equation(7) provides the explicit expression for the
unknown voltage if updating is performed
from left to right in Fig. 2. On the other hand,the updating formula in Negative is easily
derived based on that of the Positive.
In the ADE-LIM, updating the voltages
and the currents is performed twice in pertime step. Thus, the computational
complexity increases compared with that of
the basic LIM. However, the ADE-LIM
employs the larger time step size than thebasic LIM. As a result, the ADE-LIM canperform the fast circuit simulation.

4. PC-LIM
The LIM requires the reactance elements
to derive the updating formulas. Thus, if the
network is composed of the node without
capacitance or the branch without inductance,
the small value of capacitance / inductancemust be inserted into the ill-constructed
topologies. However, this treatment leads theextremely small time step size because the

f
Lab

Rab

time step size is deeply dependent on thereactance elements shown in (5). To
overcome this inherent problem, we
proposed the predictor-corrector (PC)-LIM[6]. The PC-LIM employs a large value ofthe fictitious element instead to the smallvalue. This treatment relaxes the limitationof (5).
In order to generate the updating formulafor the ill-constructed branch, first, the large
value of the fictitious inductance Lfab isinserted into the branch as shown in Fig. 3(b). In Fig. 3 (b), the following predictor
updating formula is derived,
n +1
sb

iˆ

1
1
n+ ö
L f - DtR n
Dt æ n += ab f ab iab+ f çç vb 2 - vb 2 ÷÷ .
Lab
Lab è
ø

(8)

n+1

The current iab updated by (8) is not thecorrect solution. In order to improve theaccuracy of the inaccurate value, extra
updating is performed by exploiting acompensation voltage source. Then, thefollowing corrector updating formula is led
asi sbn +1 =f
- DtRab n
Lab
i ab
f
Lab

Ê ab
-

va

vb

n +1
ab

iˆ

va

+

vb

n +1
ab

i

(a)

(b)

Fig. 3. Circuit representation. (a) Predictor
updating. (b) Corrector updating.
b=4

b=5
da5
da6

la5

la4

b=6 la6
da1

la1

b=5

da4

Aa la3 b=3
a
da3
la2

La6
b=6

La1

da2

b=1

b=2

(a)

b=4
La5
a

La4
b=3
La3

La2

b=1

Ca

b=2

(b)

Fig. 4. Voronoi diagram and triangular meshfor conductor media. (a) Double circle, dashedlines, and solid lines indicate the Voronoi point,
the Voronoi region, and triangular meshes. (b)Equivalent circuit, where the grounded
resistance G and the serial resistance R are notdepicted.

5. LIM with Triangular Meshn+n+ ö
Dt æç n + 2- vb 2 + Eˆ ab 2 ÷÷ ,
v
f ç b
Lab è
ø
1

+

f
Lab

Rab

1

1

(9)

where
ˆ n+1 nn+f dif iab - iab
Eˆ ab 2 = Lab
» Lab
Dt
dt
1

.

(10)

In the proposed PC-LIM, the unknown
current in the ill-constructed branch is
updated by (8). After that, the compensation
voltage source is generated by (10). Finally,
to improve the accuracy of the inaccurate
value, (9) is calculated.
The most important property of theabove predictor-corrector updating algorithm
is that it retains the leapfrog time-marching
scheme of the basic LIM. In addition, since
the large fictitious latency is exploited in thepredictor and the corrector, the maximum
time step size is not strictly limited by (5)compared with the basic LIM. Moreover,because the predictor and the corrector are
performed only for the ill-constructed
topologies, difference of the computational
complexity between the proposed method
and the basic LIM is slight.

For modeling of the arbitrary shaped
PDN, square meshes must be tiny because
the PDN contains the fine structures. This
fact leads that the number of unknown
variables increases drastically. Additionally,
the square mesh suffers from the staircase
approximation on the edge of the geometricstructure. To cope with the above inherent
problems, the efficient modeling methods
based on triangular mesh have been
proposed [7]. These methods successfully
reduce the total number of unknowns
without degrading the accuracy because thetriangular mesh scheme is flexible to capture
the complex structures by resizing the meshsizes locally. These triangular meshes arelead by Delaunay Triangularization andVoronoi Tessellation as shown in Fig. 4(a).
In Fig. 4(a), the gray hexagonal part, dab, andlab indicate the area of Voronoi region Aa
surrounding Voronoi point a, the length of
the Voronoi edge, and the length of the edgein the triangular mesh, respectively. The
equivalent circuit is extracted from theobject meshed triangularly, as shown in Fig.
4(b), where the Voronoi point and theVoronoi edge correspond to the node and thebranch topologies assumed by the LIM. The

Branch blocks

D

C㨙

L㨙

128 lines

equivalent circuit is composed of thegrounded capacitances and the serial
inductances, thus the LIM is directly applied
to the equivalent circuit extracted fromtriangular meshes.

B
LR

6. Numerical Results
C

In order to estimate the efficiency of the
proposed methods, the example circuit has
been simulated by the basic LIM and the
ADE-LIM. The example circuit is illustrated
in Fig. 5, which is composed of 128
transmission lines, and each transmission
line consists of 10 unit segments. Each of theunit segments is the π model constructed by
R (= 0.2 Ω), L (= 0.1 nH), C (= 0.1 pF), andG (= 0.001 S). Additionally, the values of themutual inductances and the mutual
capacitances are Lm = 1.0 pH, and Cm = 1.0
fF, respectively. In this case, the maximum
time step size used in the LIM, Δtmax, is equal
to 3.162 ps, which is less than the upperbound obtained by (5). The input current
sources Hin1 and Hin2 are connected at the
input points A and B in Fig 5, respectively.
These are the same trapezoidal pulse, of
which the pulse value is 0.033 A, rise andfall times are 0.1 ns, the pulse width is 5 ns,
and the period is 10.2 ns, except for thedelay times of 1.0 ns and 1.4 ns, respectively.
The simulation interval is [0 ns, 30 ns].
The waveform results at the observation
points C and D are illustrated in Fig. 6. The
waveform from the ADE-LIM with Δtmax
agrees well with the exact result by the LIM
and HSPICE. Furthermore, it is confirmedthat the numerical stability of the ADE-LIM
is much superior to the LIM though theaccuracy of the ADE-LIM with 7Δtmax isslightly degraded compared with the LIM.
Table I shows the CPU times andspeed-up ratios, and indicates that the
ADE-LIM with 7Δtmax is about 3.6 and 36
times faster than the LIM and the HSPICE,
respectively. As a result, it is confirmed thatthe proposed method is more effective thanthe conventional methods for the tightly
coupled transmission lines analysis.

7. Conclusions
In this paper, three types of interconnect
analysis schemes have been described. The

ACNode blocks

Fig. 5. Tightly coupled transmission lines,
each of which is composed of 11 node blocks
and 10 branch blocks. This network includes
174656 circuit elements.

(a)

(b)
Fig. 6. Waveform results at (a) C, and (b) D
in Fig. 6.
TABLE ICOMPARISON OF CPU T IMES.

first and the second approaches can do thefast transient simulations by overcoming theinherent problems of the basic LIM. the third
one is the modeling method which enables toapply the LIM to general structures.

Reference[1] J. E. Schutt-Ainé, “Latency insertion
method (LIM) for the fast transient
simulation of large networks,” IEEE
Trans. Circuits Syst. I, vol. 48, pp. 81–89,
Jan. 2001.
[2] S. N. Lalgudi and M. Swaminathan,“Analytical stability condition of thelatency insertion method for nonuniform
GLC circuits,” IEEE Trans. Circuits Syst.
II, vol. 55, no. 9, pp. 937–941, Sep.
2008.
[3] S. Leung and S. Osher, “An alternating
direction explicit (ADE) scheme fortime-dependent evolution equations,” inPreprint UCLA, 2005.

[4] H. Kurobe, T. Sekine, and H. Asai,“High-speed transient simulation of
power distribution network based on
ADE-LIM,” in ITC-CSCC 2010, Jul.
2010.
[5] ——, “Application of ADE-LIM to
multiconductor transmission lines withnonlinear drivers and terminations,” inProc. IEEE EDAPS 2010, Dec. 2010.
[6] ——, “Predictor–corrector latency
insertion method for fast transient
analysis of ill–constructed circuit,” inProc. IEEE ASP-DAC 2012, Jan. 2012,
pp. 365–370.
[7] K. –B. Wu, G.-H. Shiune, W. –D. Guo, C.
–M.
Lin,
and
R.
–B.
Wu,
“Delaunay–voronoi
modelingofpower–ground planes wirh souce port
correction,” IEEE Trans. Adv. Pachag.,vol. 31, no. 2, pp. 303–310, May 2008

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±$XJStudies of Electrostatic Discharge Simulation*1

Tsuyoshi Takada, and *2Hideki Asai**

Dept. of Systems Eng., Shizuoka University
3-5-1 Johoku, Naka-ku, Hamamatsu-shi, 432-8561, Japan*
TEL: +81-53-478-1237*1
e-mail: takada@tzasai7.sys.eng.shizuoka.ac.jp*2e-mail: hideasai@sys.eng.shizuoka.ac.jp

Abstract
This report describes the recent studies for the simulation techniques of the electrostatic
discharge (ESD), which is categorized into two modes, namely contact and air discharge
modes. Each of them is based on either circuit or electromagnetic simulation technique. We
review some early works and introduce some results.

1. Introduction
Recently, because of the speed-up of
operating frequency and lower operating
voltage, electronic systems are susceptible toexternal noises. Especially, the electrostatic
discharge
(ESD)
from
an
electrically-charged object causes severe
problems in the electronic systems.
Therefore, the immunity of an electronicequipment to the ESD is becoming more
important.
IEC 61000-4-2 is one of the standards forthe immunity test of the electronicequipment. In this standard, an ESD
generator is usually used to imitate ahuman-to-metal ESD. We inject thedischarge current to an equipment under test(EUT) and evaluate whether the EUT isbroken or not.
The waveform of the ESD current isdefined as shown in Fig. 1. The standard
defines the value of the peak amplitude, risetime, and falling edge of the current.
However,thesemeasurement-based
immunity tests are considered to be
impractical because we can not test
frequently in realistic circuit design.
Therefore, numerical simulations arenecessary to evaluate the immunity to the
ESD.
There are two modes of the ESD in the
IEC standard, namely contact and air
discharge modes. In the test of the contact
discharge mode, the electrode of the ESD
generator is held in contact with the EUT,

and the discharge switch within thegenerator is actuated to inject the current. As
for the air discharge mode, the charged
electrode of the generator is brought close to
the EUT, and the discharge current flows as
a spark to the EUT. It is difficult toreproduce the air discharge in the test even if
we use the same approaching speed andcharged voltage.
In addition, there are two ways how tosimulate the ESD events, namely a circuitand full-wave analyses. The circuit analysis
is performed based on the circuit theory andrelated circuit equations. On the other hand,the full-wave analysis directly deals with theelectromagnetic
fieldsgovernedbyMaxwell’s equations. This report introducessome of these simulation techniques
published in the early works.

2. Contact Discharge Mode
A variety of researches about thesimulations of the ESD events in the contact
discharge mode have been done. In some ofthem, the ESD has been interpreted as acurrent source without any load effect of the
ESD generator. However, interactions among
the components of the ESD generator suchas a metallic tip, a plastic body, and a groundstrap affect the current waveform. Therefore,
it is necessary to take into account the load
effect in the simulation.
In [1], the simulations were performed
using both the circuit and the full-wave

Fig. 1. The ESD current waveforms, one ofwhich is defined in the IEC standard.
Fig. 5. The ESD current waveforms in [2].

Fig. 2. The circuit model in [1].
Fig. 6. The magnetic field strength in [2].

Fig. 3. The full-wave model in [1].
Fig. 7. The electric field strength in [2].

Fig. 4. The waveform results of the ESD
current in [1].

models with the load effect. The models usedin the simulation are illustrated in Figs. 2 and3. The circuit model consists of the elements
associated with the switches, body, tip, andground strap connected to the ESD generator.
As for the full-wave model, the structures ofa metallic wall and ESD generator are
directly modeled in the three-dimensional
space by a commercially-based simulator.
The waveform results of the ESD
currents related to these models are shown in
Fig. 4. We can see the good agreements

between the results from the measurement,
circuit model and full-wave model. Although
the circuit model enables to do the fast
simulation, it can not calculate theelectromagnetic fields distributed over the
space. In contrast, the simulation withfull-wave model is time-consuming, but it
can simulate the radiated electromagnetic
fields.
One of the difficulties in the contact
discharge mode is modeling the relay, which
represents the discharge switch inside thegenerator. This is because it is necessary tomodel the switching process of the relay as
the time dependent material. However, ingeneral, most of the electromagnetic
simulation techniques can not incorporatesuch a material. In [2], this problem isovercome by developing a full-wave
simulator based on the finite-difference3. Air Discharge Mode
The recent research for the air discharge
has been described in [3]. In the air
discharge mode, the current waveform
depends on an arc length. However, the arc
length can not be controlled accurately due
to a statistical time lag. In [3], the arc model
proposed by Rompe and Weizel has beenused to represent the spark. The waveform
results are shown in Fig. 8. An agreement
can be observed. In the measurement, the arc
length is controlled by the approach speed of
the ESD generator.

4. Conclusions and Future Works
In this report, we have reviewed theresearches for the simulations of the ESD
events. I have written the program of thethree dimensional FDTD for my graduation
thesis. I am now planning to develop a highspeed simulator in which the circuit and fullwave analyses are combined with each other.

References[1] S. Caniggia and F. Maradei, “Circuit andnumerical modeling of electrostatic
discharge generators,” IEEE trans. Ind.
Appl., vol. 42, no. 6, pp. 1350-1357, Nov.
2006.

Fig. 8. The current waveforms related to thearc lengths in [3]. The length used in (b) is theaverage length between those used in (a) and(c).

time-domain(FDTD)
methodandincorporating the time dependent material.
The calculated and measured current
waveforms at the discharge point are shownin Fig. 5. The magnetic field strength at the
distance of 10 cm from the discharge point isshown in Fig. 6. In addition, the electric fieldstrength at the distance of 40 cm from thedischarge point is illustrated in Fig. 7. The
simulation results in these figures agree wellwith the measurement results.

[2] K. Wang, D. Pommerenke, R. Chundru, T.
Van Doren, J. Drewniak, and A.
Shashindranath, “Numerical modeling ofelectrostatic discharge generators,” IEEE
Trans. Electromagn. Compat., vol. 45, no.
2, pp. 258-271, May 2003.
[3] D. Liu, A. Nandy, F. Zhou, W. Huang, J.
Xiao, B. Seol, J. Lee, J. Fan, and D.
Pommerenke, ”Full-wave simulation ofan electrostatic discharge generator
discharging in air-discharge mode into a
product,” IEEE Trans. Electromagn.
Compat., vol. 53, no. 1, pp. 28-37, Feb.
2011.

Block-Latency Insertion Method for Fast Simulation of Nonlinear Circuit
Yusuke Hizawa†1, Hiroki Kurobe†2, Tadatoshi Sekine††3, and Hideki Asai†,††,†††4†Dept. of Systems Eng., Graduate School of Eng.,††Dept. of Information Science and Technology, Graduate School of Science and Technology,†††Dept. of Systems Eng., Shizuoka University 3-5-1, Johoku, Naka-ku, Hamamatsu-shi,
Shizuoka-ken, 432-8561 Japan
TEL: +81-478-1004{1hizawa, 2kurobe, 3sekine}@tzasai7.sys.eng.shizuoka.ac.jp
4hideasai@sys.eng.shizuoka.ac.jp

Abstract
For the analysis of large network including nonlinear active devices and coupled elements,
conventional SPICE-like simulators suffer from a large amount of computational cost due totime-consuming direct matrix operations. In order to overcome the problem, the block-latency
insertion method (block-LIM) has been proposed as a fast circuit simulation technique. The
advantage of the block-LIM is employing locally matrix solutions. However, there are few
applications of the block-LIM to the nonlinear circuit simulation. In this paper, we describe an
efficient nonlinear circuit simulation technique by using the nonlinear version of block-LIM,
and estimate its characteristics by applying to some example nonlinear circuits.

1. Introduction
Currently, the advancement of thesemiconductor packaging technologies has
provided the high-speed and high-density
electronic circuits. Especially, a low voltage
and high-speed signals result in asimultaneous switching noise which induces
significant signal/power integrity problems[1]. In order to estimate these effects
accurately, the equivalent circuit, including
the large scale linear passive network and thenonlinear active one illustrated in Fig. 1, has
to be analysed [2]. Thus, conventional
SPICE-like simulators take an enormous
amount of time for the simulation of such a
circuit. Therefore, some kind or another fastcircuit simulation method is strongly needed.
Recently, several kinds of fast circuit
simulation techniques for nonlinear networks
have been proposed [2], [3]. The LIM is
one of them, and based on a leapfrog
algorithm. In the LIM, it is assumed that thecircuit to be analysed is composed of branch
topologies and node topologies. In addition,
each topology in the circuit must contain areactance element: if there exists a branchwithout inductance or a node without shunt

1

Power line

m-1

vin

vout
Cload

Ccp

Ground line
R L

C SS

Fig. 1. Equivalent circuit of distribution network withnonlinear element

capacitance, a small inductance or shunt
capacitance is inserted into those topologies.
By this treatment, an arbitrary circuit can becompletely represented by using branch andnode topologies. In order to generate
updating formulas of the LIM, theKirchhoff’s voltage low (KVL) and theKirchhoff’s current low (KCL) are applied tothe branch topology and the node topology,
respectively. Then, the leapfrog algorithm isused for the solutions of the KVL and KCL
equations, where the unknown variables canbe updated by using explicit substitutions
without using the direct method.

On the other hand, since the LIM is basedon the explicit finite difference method, it has
a limitation of a time step size to satisfy thenumerical stability condition. Concretely, themaximum time step size of the LIM, Δtmax,
has the following upper bound:æ C j Nbj
ö
min L ÷Dtmax < 2 min ç
j m =1 ( jm ) ,j =1 ç
÷Nbè
øNn

2. Block-Latency Insertion Method
The block-LIM regards the topologies
connected by mutual inductance and mutual
capacitance as block topologies as shown in
Fig. 2. Additionally, the block-LIM assumes
that the circuit is composed of the basic
branch and node topologies, and the branch
block and node block topologies, and thevariables in these topologies are updated byapplying the leapfrog algorithm.
In order to generate the updating formulasof the block-LIM, the KVL and the KCL areapplied to the basic/block node and branch
topologies in the circuit, respectively. TheseKVL and KCL equations can be written
simultaneously in a vector-matrix form:M ù é v ù d é C 0 ù é v ù éh ù××+=R úû êë i úû dt êë 0 L úû êë i úû êë e úû

v a1

R1

L1

i1 L1, 2

E1

,

(2)

where v, i, h, and e are a node voltage vector,a branch current vector, an independent
current source vector, an independent
voltage source vector, respectively. In
addition, R, L, C, and G are a resistancematrix, an inductance matrix, a capacitancematrix, and a conductance matrix,
respectively. And M is an incidence matrix
which represents of the connection of the
topologies. The dimensions of the vectors
and sub-matrices in (2) are defined as

C1,3

C1, 2
C1 G1 H 1

L1,3
R2

va 2 L2

v1

vb1

E2

~
i2

vb 2

v2

i2 L2,3C2,3
C2 G 2 H 2(1)

where Nn is the total number of nodes in thecircuit, Nbj is the number of the branches
connected to the node j, Ljm is a value of theinductor in the branch connected to the node j,
and Cj is a value of the grounded capacitor
connected to the node j.
By extending the basic LIM algorithm, theblock-LIM [4] has been proposed for a fastmulticonductor transmission lines analysis. In
this paper, we propose an efficient nonlinear
circuit simulation technique based on theblock-LIM algorithm.

é G
ê-MT
ë

~
i1

~
i3

L(nb -1),nb
Rnb E
nb

vanb Lnbv3
C(nn -1),nn

vbnb

C3 G3 H 3

in

i nb

v nn

Cnn Gnn H nn(b)(a)
Fig. 2. Required block circuit topologies for block-LIM.
(a) Branch block topology. (b) Node block topology.

v, h ÎÂ Nn , i, e ÎÂ Nb ,R, L ÎÂ Nb ´ Nb , C , G ÎÂ Nn ´ Nn , M ÎÂ Nn ´ Nb .

Then, applying the difference method basedon the leapfrog algorithm to (2) leads toé D1t C + G
ê
T
ëê -M

0 ù é v n+ 2 ù é D1t C + G -M ù é v n- 2 ù é h ù
ú=êú + ê 1 ú ,(3)
ú×ê
ú×ê
1
L ûú ëê i n+1 ûú ëê 0
L úû ëê i n ûú ëêe n+ 2 ûú
Dt
1

1

n

1
Dt

where n and Δt are a time index and thetimestep size, respectively. Note that thecoefficient matrix of the left-hand side of (2)is a lower block triangular matrix, current
and voltage variables can be solved
independently.


3. Nonlinear Block-LIM
The LIM [3] can treat only two-terminal
nonlinear elements. This is because the KCL
equations at the nodes which are connected tomore than two-terminal nonlinear elements
are represented as simultaneous equations.
Therefore, the node voltages are not solved
individually.
We generate the updating formula of the
proposed method below, using MOSFET as
an example of the nonlinear element. In Fig.
3, CMOS inverter which is composed of
PMOS and NMOS is shown as an example inwhich some nodes are connected to thepower and the ground lines by parasitic
capacitances. Furthermore, a nonlinear block
consists of a set of nodes, out, DD, and SS.
Applying the KCL to each node in the
nonlinear block topology leads to thefollowing simultaneous
vector-matrix froméCload
d ê
0
dt ê
ê 0
ë

equationsinaù é vout ù éiDp + iDn ù é iout ùú-Ccp ú × êêvDD úú + êê -iDp úú + êêiDD úú = 0 ,Ccp + CSS úû êë vSS úû êë -iDn úû êë iSS úû (7)

0

0

Ccp
-Ccp

where iDp and iDn are the drain currents
flowing through PMOS and NMOS,
respectively, and iDD and iSSS are the sumof currents flowing out the nodes DD and SS
respectively. Then, applying the difference
method based on the leapfrog algorithm to(7) leads toéCload
1 ê
0
Dt ê
ê 0
ë

0
Ccp
-Ccp

1
n- ù
é n + 12
é n + 12 n + 12 ù2êv - v ú êi + iDn únù ê out 1 out 1 ú ê Dp1
ú é iout ùnn+êú ê n+ 2n ú2ú2
ú + iDD-Ccp ú × vDD - vDD + ê -iDp
=0
ê 1
ú ê
ú ê n ú11
êú
úCcp + CSSS û ê n + 2
i
,
n- ú
n+
SS
ê
ú
ë
û
2
2
êvSS - vSS ú ê -iDn
ú
(8)
ë
û ë
û

0

Note that the second term of the left handside in (8) is a nonlinear function vector.
Thus, the proposed method exploits the
Newton-Raphson (NR) method to solve (8)defining the left hand side of (8) as anonlinear function vector f = [f1 f2 f3]T ,and applying the NR method to f leads thefollowing updating formula of the nonlinear
block topology:
æ n+ 1 ,( k -1) ö n + 12 ,( k )æ n + 1 ,( k -1) ö n + 12 ,( k -1) ( k -1)
jç v 2= jç v 2
-f
÷× v
÷× v
è
ø
è
ø

, (9)

where
é ¶f1( k -1)
ê n +1/2, ( k -1)
ê ¶vout
æ n + 12 ,( k -1) ö ê ¶f 2( k -1)
jç v
÷ = ê n +1/2, ( k -1)èø ê ¶vout
ê
ê
0
ê
ë

v

1
n + ,( k )2é n+ 1 ,( k )= êvout 2
ëf ( k -1) = éë f1( k- 1)

1
n+ ,( k )vDD2

¶f1( k -1)
n +1/2, ( k -1)¶vDD¶f 2( k -1)
n +1/2, ( k -1)¶vDD( k -1)¶f3

n +1/2, ( k -1)
¶vDD

ù
ú
ú
ú
¶f 2( k -1) ún +1/2, ( k -1)
ú¶vSS
ú¶f3( k -1) ún +1/2, ( k -1) ú
¶vSS
û
0

,

T
1
n+ ,( k )vSS 2

f (2 -k )1 f ( 3 -k) ùû1

ù
ú,
û

T

and k is an iteration count of the NR method.
The unknown variables in the nonlinear
block topology are updated by solving (9)iteratively until the iterative solutions
converge. Moreover, this algorithm can beeasily applied to the nonlinear device withmore than two-terminals by changing the sizeof the matrices and vectors in (9).
Fig. 4 shows a graphical representation of
the unknown variables of (3) in the case thatthe proposed method is applied to the circuit
shown in Fig. 1. Note that the coefficientmatrices of the nonlinear block topology,

Power line
Ccp

vDD

~
iDD

DD

d
(vDD - vSS )
dt

iD p
out

vin

iDn

v SS
CSS

d
vSS
dt

SS

iout
vout ,
Cload

d
vout
dt

~
iSS
Ground line

Fig. 3. Enlarged part of nonlinear circuit withCMOS inverter in Fig. 1.

which is composed of the nodes connected to
the CMOS inverters, is a 3×3 local dense
matrix. Additionally, the coefficient matrix ofthe linear block topology, which is composed.
of the nodes connected to each mutual
capacitance, is a 2×2 local dense matrix. In
the proposed method, the nonlinear nodeblock topology is updated by using (9) while
the linear node block and branch topologies
are updated based on the basic block-LIM
algorithm. Thus, the nonlinear block-LIM
does not require the matrix operation for thewhole system similarly to the block-LIM. In
addition to the above advantage, the proposed
method can reduce the number of fill-ins
caused by the LU factorization. Fig. 5 shows
the coefficient matrix with fill-ins after the
LU factorization. Note that the matrix in
Fig.5 contains a number of non-zero entries
even though the original coefficient matrix issparse. On the other hand, the proposed
method inhibits the fill-ins because thismethod performs the direct matrix operations
and the calculations of the Jacobian matrix
only within the block topology. Hence, theproposedmethodcanreducethecomputational costs significantly comparedwith SPICE-like simulators.

4. Numerical Results
In order to estimate the validity andefficiently of the proposed method, weanalyze an example network by using the
proposed method and the HSPICE. The
network is composed of power and groundlines with m CMOS inverters between theselines as shown in Fig. 1. The element values
are R = 0.1Ω, L = 0.1 μH, Cload = 0.1 pF, Ccp= 1.0 fF, and CSS = 0.1pF, and the parametersLinear node blocks (2 ´ 2)
Nonlinear nodeblocks (3´ 3)

TABLE ΣParameter
Kp,n
Wp,n
Lp,n
VTp,Tn
λp,n

PMOS
8.362
2.0
1.0
-0.1340

NMOS
20.072
2.0
1.0
0.134
0

Unit
μA/V2
μm
μm
V
V-1

0

0

20

20

40

40

TABLE ΤElement
139
284
574
1444
2894

n
5
10
20
50
100

HSPICE
[s]
4.70
9.33
20.40
54.54
110.02

Proposedmethod [s]
0.69
0.88
1.41
2.77
5.32

Speed-up
ratio
6.8
10.6
14.5
19.7
20.7

used in all of MOSFETs are shown in
TABLE I. In this case, the time step size
derived from (1) is equal to 7.72 ps. The
input voltage is trapezoidal pulse of which an
initial value is 0 V, a pulse value is 3.3 V, adelay time is 0 ns, a rise and fall time are 10
ns, a pulse width is 40 ns, and a period is 100
ns, is connected to the first CMOS inverter.
The simulation interval is from 0 ns to 500 ns.
The voltage waveforms observed at the 100th
CMOS inverter is shown in Fig. 6. It is
confirmed that the waveform from the
proposed method agrees with that of the
HSPICE. TABLE II shows the CPU times
and speedup ratio on the basis of the CPU
time of the HSPICE in case of changing mfrom 5 to 100. In TABLE II, it can be seenthat speed-up ratio is increasing as m is doing.
As a result, we have confirmed that the
proposed method is more appropriate for thelarge nonlinear network analyses than theconventional SPICE-like simulators.

5. Conclusions
In this paper, the fast circuit simulation
technique based on the block-LIM algorithm
for the large linear network with nonlinear
devices has been described. The proposed
method regards the nodes, which areconnected each other by nonlinear device, as
one nonlinear block topology. The proposed
method can perform the fast circuit analysis
because the method has two superior featurescompared with SPICE-like simulators: that is
to say, the local matrix operations, and the
reduction of fill-ins in the LU factorization.

60

60
0

20

40

60

0

20

40

60

Fig. 4. Graphical representation Fig. 5. Graphical represent of the coefficient matrix intation of the coefficientmatrix inSPICE-like simul
proposed method.
-ators after LU factorization.

Fig. 6. Waveform results

Some numerical results have shown that the
proposed method is about 20 times fasterthan the HSPICE with appropriate
accurancy.

Reference[1] H.
asai,“PI/SI/EMI
simulation
technology for chip/package/board
co-design”, workshop w-th1, APEMC
2011, May. 2011.
[2] Z.Li,
C.-J.
R.Shi,“SILCA:SPICE-accurate iterative linear-centric
analysis for efficient time-domain
Simulation of VLSI circuits with strong
parasitic couplings”, IEEE Trans.
Comput.-Aided Design Integr. Circuits
Syst. 25, 6, pp. 1087-1103 Jun. 2006.
[3] J. E. Schutt-Ainé, “Latency insertion
method (LIM) for the fast transient
simulation of large networks”, IEEE
Trans. Circuits Syst. I, 48, pp.81–89 Jan.
2001.
[4] T. Sekine. and H. Asai. “Block latency
insertion method (block-LIM) for the
fast transient simulation of tightly
coupled transmission lines”, IEEE Trans.
Electromagn.Compat., 53, pp. 193–201,
Feb. 2011.

Eye-diagram of a High-speed Through Silicon Via Channel
Heegon Kim, Jonghyun Cho, Joohee Kim, Kiyeong
Kim, Jun So Pak and Joungho Kim

Kwang-Seong Choi and Hyun-Cheol Bae
Convergence Components and Materials Research Lab
ETRI
Daejeon, South Korea

TERA Lab
Korea Advanced Institute of Science and Technology
Daejeon, South Korea

Abstract
An eye-diagram estimation method for a through-silicon via (TSV) based three-dimensional integrated circuit(3D IC) was developed. To validate the proposed method, circuit-level simulations and time-domain measurements ofa fabricated 3D IC test vehicle were performed at different data rates. The eye-diagrams estimated by the proposed
method had good correlations with those of the circuit-level simulations and time-domain measurements.
I.

INTRODUCTION

Spurred by industrial demand for integrated-circuit
systems with improved channel bandwidths and compact
sizes, three-dimensional integrated circuit (3D IC)
technology is a potential solution [1]. 3D IC realizes
vertical interconnections between heterogeneous chips
and provides impressively short channel paths. Throughsilicon via (TSV) and silicon interposer are used toachieve shorter channel lengths and are the mostimportant technologies in 3D IC. However, as shown in
Fig. 1, although the channel length can be reduced by
TSV and interposer, signal integrity still cannot beensured in 3D IC as the data rate increases.

Figure 1. Eye-diagram degradation in 3D IC channel

The eye-diagram, which is a convenient graphicalmethod used to analyze the received digital signal, iswidely used to analyze signal integrity. However, toobtain the eye-diagram of 3D IC channel is difficult
because of the complexity of the channel. Simulation andmeasurement of the eye-diagram in TSV-based 3D IC
have several limitations: for example, they are time
consuming and require the fabrications of test vehicles.
Though there have been the previous studies that
efficiently estimate the eye-diagrams, these methods havethe limited accuracy in 3D IC because their target
channels are too simple [2-3]. Therefore, the method toefficiently estimate the precise eye-diagram of TSVbased 3D IC channels is needed.
In this paper, we propose an efficient eye-diagram
estimation method for TSV-based 3D IC. Because theproposed method employs the worst-case data patterns as
the input instead of a Pseudo Random Bit Sequence(PRBS), the eye-diagram of the TSV-based 3D IC
channel can be estimated quickly. Moreover, to estimate
the precise eye-diagram in TSV-based 3D IC channel, theproposed method employs the mathematical models of
the multi-stacked TSV and the silicon interposerinterconnect. By using the developed models, the precise
eye-diagram of TSV-based 3D IC channel can be
estimated.
To verify the proposed eye-diagram estimation
method for TSV based 3D IC, test vehicle consisting of
TSV and silicon interposer was fabricated. As a result of
the time-domain measurement of the test vehicle withvarious data rates, the eye-diagrams estimated by the
proposed method correlates well with the measurement
results; the maximum error rates of eye-opening voltage
and timing jitter were 7.0% of peak-to-peak voltage (Vp-p)
and 9.0% of 1 unit interval (UI), respectively. Moreover,the proposed method was also compared to circuit-level
simulation, and eye-diagrams estimated by the proposed
method and simulation were almost same.

EYE DIAGRAM ESTIMATION METHOD FOR A
TSV-BASED 3D IC CHANNELII.

A. ABCD matrix of 3D IC channel

Many poles and zeros exist in real channels; thus,
predicting the voltage-transfer function of the channel byconsidering all poles and zeros is almost impossible.
Therefore, we used an equivalent-circuit model of thechannel consisting of the dominant poles and zeros
instead. For the TSV-based 3D IC channel, we employ
equivalent-circuit models of TSV and silicon interposerinterconnect; previous studies for equivalent-circuit
models of them can be found elsewhere [4-5].

GSi

Conductance of silicon substrate between TSVs

RInt

Resistance of interposer interconnect

LInt

Inductance of interposer interconnect

CoxideCapacitance of oxide layer under metal line

Cpass

Fringing capacitance of passivation layer

Csilicon

Fringing capacitance in silicon substrate

Gsilicon

Conductance of silicon substrate

B. Eye diagram estimation method

A summary of the flow of the proposed eye-diagram
estimation method is shown in Fig. 2.

Using the equivalent-circuit models, the ABCD
matrices of the multi-stacked TSV channel and thesilicon interposer interconnect can be obtained as shownin (1) and (2), respectively; the channel is assumed to
one-layer ground-signal-ground (GSG) type. The symbol
descriptions are shown in Table 1. For the siliconinterposer, the ABCD matrix includes the exponent, M,
which accounts for the long interconnect length; theequivalent-circuit model of a long interconnect should be
the distributed model. If we have the ABCD matrices ofTx and Rx drivers, the ABCD matrix of a TSV-based 3D
IC channel can be derived by combining them with (1)and (2). The voltage-transfer function of a TSV-based 3D
IC channel can be obtained from the matrix [6].
( ATSV&C' TSVBTSV %DTSV #$

Figure 2. Flow chart for the eye-diagram estimation method(1)(%. 2.4 0 sC ox (GSi / sC si ) +2) N !RTSV / sLTSV "#&1 / N !RTSV / sLTSV " 0 ,,Gsi / s (1.2C ox / C si ) )*
&
#
1
&
#
. 2.4 0 sC ox (GSi / sC si ) +
))
N ,,
1
&
#
/
/
G
s
C
C
(
1
.
2
)
ox
si
- si
*
'&
$#

where N = the number of stacked TSV
BInt %
DInt #$( AInt
&C
' Int

(
%
.
+
2
,
&
#
sC oxide !Gsilicon / sC silicon " ))3&1 / !R / sL " 0 , sC
#
/
/
R
sL
Int
Int
Pass
Int
Int
,
&
#
.2
+)
/
/
G
s
C
C
,
)
,
)
&
#
siliconoxide
silicon )
,
3
*
*
1&
#
2
&
#
sC oxide !Gsilicon / sC silicon "&#3
sC Pass /
1
&
#
2
+
.
&
#
Gsilicon / s, C oxide /C silicon )
&'
#$
-3
*

TABLE I.

M

DESCRIPTION OF SYMBOLS IN (1) AND (2)SymbolDescription

RTSV/

Resistance of TSV and bump

LTSV

Inductance of TSV and bump

Cox

Capacitance of oxide layer in TSVCSi

Capacitance of silicon substrate between TSVs

(2)

In the first step, we define the worst case input signals
in the s domain. If we neglect the effect of reflection, we
can assume a unit pulse signal with non-zero rising andfalling times as the worst-case input signal that
corresponds to the worst output response. In subsequent
steps, the proposed method estimate the eye-diagram bycombining the defined worst input signals and thederived voltage transfer function. By multiplying the
input by the voltage transfer function, the output responsein the s domain can be obtained, and the inverse Laplacetransform of this response becomes the worst output
response in time-domain. Because the inner contour ofthe eye-diagram, which is the performance metric ofsignal integrity, is determined by the worst output
responses, we can estimate the eye-diagram of TSVbased 3D IC channel.
VERIFICATION OF EYE-DIAGRAM ESTIMATIONMETHOD BY SIMULATION AND MEASUREMENTIII.

To verify the proposed eye-diagram estimation
method, the test vehicle of the TSV-based 3D IC that arecomposed of TSV and silicon interposer was fabricated.
Fig. 3(a), (b) and (c) respectively show the cross-section,
top and bottom views of the test vehicle, which consists

of two TSVs and a short interposer interconnect; Fig. 3(a)was obtained from the scanning electron microscope(SEM) image. Two chips were stacked vertically, and theTSV channel and interposer interconnect were fabricatedon the top and bottom chips, respectively. Because of theshort length of the interposer interconnect (=500 !m) andlarge amount of Cox which came from large TSV
diameter (=46 !m) and thin thickness of the oxide-layer
in TSV (=0.5 !m), the TSVs had the considerable
channel loss.
For the time-domain measurement, a digital sampling
oscilloscope, TDS8000B from Tektronix with abandwidth of 20 GHz was used. The input signal was
generated by a pulse pattern generator (PPG), MP-1763C
from Anritz, with rise and fall times of 30 ps, and a
PRBS of 211-1 was used for the input data patterns. The
high-frequency cables with a maximum frequency of 40
GHz were used to minimize the effect of cable loss to themeasured eye-diagram.

proposed method successfully estimated the almost sameeye-diagram with that of time-domain measurement. The
error rates of the eye-opening voltage (VEOV) and timing
jitter (tTJ) were 7.0% of Vp-p and 9.0% of 1 UI,
respectively.
There are several factors that contribute to errors: theloss of cables, ringing of the input signal in PPG and
random jitters (RJ). Though the eye-diagrams estimatedby the proposed method only considered the channel lossof the test vehicle, the measured eye-diagrams
additionally contained the loss of the high-frequency
cables; it made the measured eye-diagrams degraded
more. Moreover, because there was ringing in the input
signal of the PPG when we measured the eye-diagram,the shape of the measured eye-diagram is distorted.
Though the effect of the ringing was negligible at the low
data rate as shown in Fig. 4(b), it became considerable atthe high data rate because of the reduced duty-cycle asshown in Fig. 5(b). In addition, though there must be RJ
in the measured eye-diagram, the proposed method takes
into account data-dependent jitter (DDJ) only. It also
made the measured eye-diagram worse than the eyediagram estimated by the proposed method.

(a)

(b)

(a)

(c)
Figure 3. Fabricated test vehicle for measuring the eye-diagramof TSV-based 3D IC channel (a) cross-section view and (b) top
view and (c) side viewFig. 4(a) and (b) respectively, show the estimated andmeasured eye-diagrams at a data rate of 10 Gbps. The(b)

Figure 4. Eye-diagrams of TSV-based 3D IC channel in test
vehicle at a data rate of 1 Gbps (a) using the proposed methodand (b) measurement

Fig. 5(a) and (b) respectively depict VEOV and tTJ in
accordance with the data rates. They were obtained by
the proposed method, circuit-level simulation and timedomain measurement. Agilent ADS 2008 was used for thesimulator to estimate the eye-diagram by using theequivalent-circuit model of TSV-based 3D IC channel.
VEOV and tTJ of simulation results that neglected the cable
loss were almost same with those of the proposed
method; the maximum error rates of VEOV and tTJ were4.0% of Vp-p and 1.9% of 1 UI, respectively. However,
the measured eye-diagrams were worse than the eyediagrams estimated by the proposed method and circuitlevel simulation because of the aforementioned error
factors; compared to the proposed method, the maximum
error rates of VEOV and tTJ were 7.0% of Vp-p and 9.0% of
1 UI, respectively. For the circuit-level simulation
including the cable loss, the amount of VEOV and tTJ
became close to those of the measurement. Therefore, if
we have the ABCD matrix of the cable, the proposed
method would be able to estimate the more accurate eyediagram by considering the cable loss.

(b)
Figure 5. (a) Eye-opening voltages and (b) timing jitters ofTSV-based 3D IC channel in test vehicle in accordance withdata rateIV.

CONCLUSIONSIn this study, a method to estimate the precise eyediagram of high-speed channel in a TSV-based 3D IC
was proposed. Equations for the ABCD matrices of themulti-stacked TSV and the silicon interposer interconnect
were developed to model the eye-diagram of the TSVbased 3D IC channel. To verify the proposed method, atest vehicle of TSV-based 3D IC was fabricated and theeye-diagrams were estimated, simulated and measured
with various data rates. Compared to the circuit-level
simulation, the proposed method estimated the eyediagram within error rates of 4.0% of Vp-p and 1.9% of 1
UI in VEOV and tTJ, respectively. Moreover, it was
successfully demonstrated that the proposed method canpredict the measured eye-diagram of TSV-based 3D IC
channel within error rates of 7.0% of Vp-p and 9.0% of 1
UI in VEOV and tTJ, respectively.

REFERENCES
[1]

(a)
[2]
[3]

[4]

[5]
[6]

J.S. Pak, C.H. Ryu and J.H. Kim, “Electricalcharacterization of through silicon via (TSV) depending
on structural and material parameters based on 3D fullwave simulation”, IEEE Electromagnetic Electronic
Materials and Packaging, 2008
J. Buckwalter, B. Analui and A. Hajimiri, “Predicting
data-dependent jitter,” CAS-II, 2004
W. Guo, J. Lin, C. Lin, T Huang and R, Wu, "Fastmethodology for determining eye diagram characteristics
of lossy transmission lines," IEEE Trans. Adv. Package.,
vol.32, no.1, pp.175-183, Feb. 2009
J.H. Kim, et.al., “High-frequency scalable electricalmodel and analysis of a through silicon via (TSV),” IEEE
Trans. Adv. Package., vol.1, no.2, pp.181-195, Mar. 2011
H.G. Kim, et.al., “Channel design for wide system
bandwidth in a TSV based 3D IC,” SPI2011, Mar. 2011
D.Pozar, “Microwave engineering, 3rd Ed.,” John Wiley &Sons, Inc., 2005

Through-Silicon Via (TSV) Depletion Effect
Jonghyun Cho, Myunghoi Kim, Joohee Kim, Jun So Pak, and Joungho Kim
Department of Electrical Engineering, KAIST,
s-112, NanoFab center, KAIST, Guseong-dong, Yuseong-gu, Daejeon, South Korea
TEL&FAX: +82-42-879-9868
e-mail: jonghyun.cho@kaist.ac.kr

Abstract
The effects of through-silicon via (TSV) depletion are analyzed based on the frequencyand time-domain measurements in this paper. As TSV dc bias voltage increases, a TSV
depletion region is generated; this region decreases TSV noise coupling at frequencies below 1
GHz. It also creates duty-cycle distortion of the coupled signal, which results from thenonlinearity of the TSV.

1. Introduction
TSV is constructed from conductive via,
silicon, and an insulation layer between thevia and the silicon; it constructs
metal-insulator-silicon (MIS) junction asshown in Fig. 1. Accumulation, depletion,and inversion modes occur in such MIS
structures based on the bias voltage
between metal and silicon [1]-[2].
In this paper, TSV depletion effects on
TSV noise coupling are analyzed using
frequency- and time-domain measurements.
The test vehicles are manufactured byHynix semiconductor Inc. using via-last
TSV. Even though TSV depletion may occur
at all frequencies, the effects of TSV
coupling are limited to frequencies below 1
GHz, where TSV capacitance plays a majorrole in the coupling. As the TSV dc bias
voltage increases, the TSV coupling
capacitance decreases, which also decreases
TSV noise coupling. Unlike small signal

Fig. 1. The conceptual structures and simplified
equivalent circuit model of TSV in the depletion
mode.

analysis in the frequency domain, large
signal analysis in time domain is not
simple. For large signals, the bias voltage
cannot be considered a fixed value; itchanges over time. The bias voltage
generates nonlinear voltage-dependent
TSV depletion capacitance and creates
duty-cycle distortion in the coupling voltage
measurements.

2. ANALYSIS OF TSV DEPLETIONEFFECT FOR SMALL SIGNALS
To analyze the TSV depletion effect, thenoise transfer function between the TSV andsubstrate contact is measured with varying
TSV dc bias voltage. The test vehicle ismanufactured by Hynix semiconductor Inc.
by using via-last TSV. It contains one TSV,
one substrate contact, a common ground forthe reference, and probing pads. The
diameter of the TSV is 33 um, the size of thesubstrate contact is 30 um × 30 um, and the
distance between the TSV and substratecontact is 100 um. More detailed dimensionsof the test vehicle are described in a previous
paper and are omitted in this paper [3].
The measured noise transfer function
with TSV dc bias voltage variation is shownin Fig. 2. As the dc bias voltage decreases
from +3 V to -3 V, the noise transfer function
increases from -46.7 dB to -41.7 dB at 10
MHz, while the high-frequency behavior
remains same. At low frequencies, TSV
coupling is mainly determined by TSV
capacitance, CTSV, while mid and highfrequency coupling is determined by silicon
resistance and capacitance [3].
Noise Transfer Function [dB]

-15
-20
-25
-30
-35

Coupling increase
as dc bias voltage decreases

power under noise floor while the coupled
signal has much larger power than the input
signal. It means that the harmoniccomponents are generated during the TSV
coupling. At dc -3V, there’s small
capacitance variation for the large dc voltage
variation while it has large variation at dc 0V.
This is the reason of much smaller
nonlinearity of dc -3V case.

-40
-45
-50
10M

DC 1.0V

DC 0.5V

DC 0.0V

DC -1.0V

100M
1G
Frequency [Hz]DC 0.2V

10G

Fig. 2. Noise transfer function (S21)
differences depending on TSV dc bias voltage

3. ANALYSIS OF TSV DEPLETIONEFFECT FOR LARGE SIGNALS
In this chapter, large signal analysis isperformed based on the measurements using
signal generator, oscilloscope, and spectrum
analyzer. The original injected signal and thecoupled signal with 0V TSV dc bias iscompared in Fig. 3. We can easily recognizethat the duty-cycle distortion occurs at the
coupled signal even though there’s noduty-cycle distortion at the original signal.

Fig. 3. Duty-cycle distortion of the coupled
signal when TSV dc bias voltage is 0V.
100MHz, 750mV amplitude sinusoidal wave is
injected to TSV

Fig. 4 illustrates the measured frequency
spectrum of the original and the coupled
signal when dc bias voltage is 0 V and -3 V.
for the harmonic frequencies, there exists
some strange phenomena. For DC 0V case at
200MHz, the difference between the original
and the coupled signal is very small, whichcannot be explained by the noise transfer
function. For 400MHz, 500MHz, and600MHz, the injected input signal has theFig. 4. Measured frequency spectrum of theinjected original signal and the coupled signal.
The sinusoidal signal with 100MHz frequency
and 750mV amplitude is mixed with TSV dc
voltage and injected into TSV.

4. Conclusion
The analysis, measurements using a TSV
coupling test vehicle are performed. The
TSV capacitance decreases as the dc bias
voltage increases for the small signal in thedepletion mode. For the large signal thatvaries between VFB and VTh, the results
indicated nonlinearity in the time-domain
measurements because the TSV capacitancechanges with time. This results can beapplied to not only TSV coupling but also
the TSV channel and other TSV applications.

Reference[1] D. A. Neamen, Semiconductor Physics
andDevices
Basic
Principles.
McGraw-Hill, 2003
[2] Katti, G., et.al., "Electrical Modeling andCharacterization of Through Silicon via
for Three-Dimensional ICs," Electron
Devices, IEEE Transactions on , vol.57,
no.1, pp.256-262, Jan. 2010[3] Jonghyun Cho, et.al., "Modeling andAnalysis of Through-Silicon Via (TSV)
Noise Coupling and Suppression Using a
Guard Ring," CPMT, IEEE Transactions

on , vol.1, no.2, pp.220-233, Feb. 2011

I/O Power Estimation and Analysis of High-speed
Channels in Through-Silicon Via (TSV)-based 3D IC
Joohee Kim, Jonghyun Cho, Jun So Pak, Taigon Song, *Hyungdong Lee, *Junho Lee and*Kunwoo Park and Joungho Kim
Department of Electrical Engineering, KAIST, Daejeon, South Korea
e-mail: joohee@eeinfo.kaist.ac.kr, Hiroshima University,*Advanced Design Team, Hynix Semiconductor Inc., Icheon-si, Gyeonggi-do, South Korea*
e-mail: hyungdong.lee@hynix.com

Abstract
In this paper, power estimations for various through-silicon via (TSV)-based
three-dimensional integrated circuit (3D IC) designs were conducted in efforts to realize
low-power-consumption 3D IC. In addition, the dominant power-consuming factor was foundamong the TSV-based interconnect components by a power comparison analysis based on the
proposed model.

1. Introduction
Recently,
through-silicon
via(TSV)-based
three-dimensional
integrated circuits (3D IC) are theleading technology for smaller form
factor and higher system performance.
With the reduced interconnection lengthby using a TSV as a verticalinterconnection method between stacked
dies, the TSV-based 3D IC has become
the key solution to reducing power
consumption. In this study, we estimatedthe power dissipation of the TSV-based
I/O channel in a 3D IC. As shown in
Figure 1, there are two main factors to beconsidered in power management of a
TSV-based I/O channel in a 3D IC: theTSV-based interconnect and the I/Ocircuitry. Because the I/O driver must be
optimized by considering the channel
characteristics and signal integrity
issues such as reflection, termination,etc., the dynamic and leakage power
consumptions due to the I/O driver were
not considered in this work. Instead, we
focusedonthedynamic
power
consumption of the TSV-based I/Ochannel. To estimate the dynamic power
consumption of the TSV-based I/Ochannel, analytic models were proposedfor calculating loading capacitances.

Fig. 1. Power consumption in a 3D IC; ձdynamic power consumption of TSV-based
interconnect,
ղ dynamic/static
power
consumption of I/O circuitry.

Based on the proposed capacitancemodels, we estimated the dynamic power
consumption of the TSV-based I/Ochannel and compared it for various 3D
IC designs such as TSV arrays withdifferent ground TSV counts, TSV and
RDL/interposer metal dimension andvarious 3D architectures.

2. Proposed Model for Power
Estimation of the TSV-based I/OChannelresults in a slow-mode effect. In addition, G2
can be expressed with C2 and material
properties such as an electrical permittivityof the silicon substrate, !, and a conductivityof the silicon substrate, ". Thus, theequivalent capacitance of the TSV, CTSV(1S1G),
can be derived as a function of C1, C2, C3
and material properties of the silicon
substrate, which has a one-signal andone-ground TSV configuration (1S1G).

As shown in Figure 2, the equivalentcapacitance of a TSV, CTSV, is proposed
based on the equivalent-circuit model of
TSV [1]. In this equivalent-circuit model, thebump effect is included as it is a necessarycomponent for TSV connection between
stacked dies. Due to the conductance of thesilicon substrate between signal and ground
TSVs, G2, the equivalent capacitance of theTSV changes depending on frequency, which*'%/ n # -. %&)$ , n # C3
CTSV ( 1sng) !. " +*0 '%%, n # C1 $ !, n $ 1" # C2 (( / n $/ n # -. &), n # C1C2 (( / n $0Fig. 2A cross-sectional structure with the simplified equivalent-circuit model of a TSV, including asignal TSV, a ground TSV and bumps and the equivalent capacitance equation of a TSV.

0 '*2Cv 2Ch 2 ( 2 $%2 # -. &)C RDL ,bottom !. " +$ Cv1 $ 2!Cd $ Ch1 "0 '*2Cv 2 $ 3Ch 2 ( 2 $%2 # -. &)Fig. 3 A cross-sectional structure of the RDL or interposer metal and its parasitic capacitances when
signal propagates through the bottom metal layer, which is the closest layer to the silicon substrate, andthe equivalent capacitance of a RDL.

3. Results and Discussion
With the 1s8g configuration, the changes
in dynamic power consumptions with TSV
dimension variation were calculated; here,
TSV diameter (dTSV), TSV pitch (pTSV) andinsulation layer thickness (tox) were the main
design parameters for dimension variation of
the TSV. As shown in Figure 4 Pd,TSV
increased as dTSV was increased and as pTSV
and tox was decreased. Because C1 and C2 in
Figure 2 both increased as dTSV wasincreased. In addition, C2 and C3 increased
as pTSV was decreased and C1 increased as tox
was decreased, causing Pd,TSV to increase.
Thus, to decrease dTSV and to increase
pTSV and tox are the ways to reduce thedynamic power dissipation from the TSV,
since they can reduce the equivalentcapacitance of TSV, CTSV.
To redistribute the I/O signals horizontally,
RDL and interposer metal routing must be
done within design parameters such as metal
width (W), space (S), thickness (T),inter-layer dielectric (ILD) height (H), andlength (L). Here, we estimated and compared
the dynamic power consumption withvariations in these parameters. As shown in
Figure 5 the dynamic power consumption
was more significantly influenced by widthvariation rather than space variation between
RDLs. This is because the parasitic
capacitance of an RDL is dominantly formedby the vertically confronting faces between
RDLs or between the RDL and the silicon
substrate. In the case of the interposer metal,
power consumption was also more strongly
affected by width than by space in the samemanner as in the RDL case. This conclusion
is only valid when the aspect ratio (W/T) is
larger than 1. If not, S becomes more
dominant in the dynamic power consumption
rather than W. Thus, to decrease W and toincrease S are the ways to reduce thedynamic power consumption from the
RDL/interposer metal.

4. Conclusion
Fig. 4 Dynamic power consumption of TSVwith dTSV variation (pTSV=135 #m, tox=0.5 #m),pTSV variation(dTSV=10 #m, tox=0.5 #m), toxvariation (dTSV=10 #m, pTSV=35 #m) with theactivity factor, supply voltage and operating
frequency assumed to be 0.15, 1.2 V and 800
MHz, respectively.

In this work, we proposed a capacitancemodel for a TSV-based I/O channel
including TSVs, bumps, the RDL andinterposer metal to estimate dynamic power
consumption of a TSV-based I/O channel ina 3D IC. With the proposed model, we
estimated and compared dynamic power
consumption depending on TSV / RDL /interposer metal dimensional variations.
Among the TSV-based I/O channel
components,thedynamic
power
consumption was dominated by the RDL,
and design guides of each component to savepower were proposed.

Reference
Fig. 5 Comparison of the dynamic power
consumption of RDL, Pd,RDL, depending on
width(W) and space(S) variation with theactivity factor, supply voltage and operating
frequency assumed to be 0.15, 1.2 V and 800
MHz.

[1] J. Kim, et al, “Through Silicon Via(TSV)
Equalizer,”
Proc.
18th
conferenceonElectrical
Performance of Electronic Packaging
and Systems, Portland (Tigard),
Oregon, 2009, pp. 13-16.

Vertical Noise Coupling on Wideband Low Noise
Amplifier from On-chip Switching-Mode DC-DC
Converter in 3D-IC
Kyoungchoul Koo1, Sangrok Lee and Joungho Kim
Terahertz Interconnection and Package Laboratory
Department of Electrical Engineering, KAIST
Daejoen, KOREA
1
kckoo@eeinfo.kaist.ac.kr ; teralab@ee.kaist.ac.kr

Abstract— 3D-IC mixed-signal systems introduce vertical noise
coupling which is a new noise coupling path by near-field
coupling between logic ICs and RF/analog ICs. To guarantee theperformance of the system, we should be aware of the amount of
the vertical noise coupling during the system design stage. This
paper reports the frequency-domain and time-domain
measurement results of the vertical noise coupling on wideband
low noise amplifier (LNA) from 200MHz on-chip switching-mode
DC-DC converter in 3D-IC configuration. In the measurementsfrom test vehicles with variations in stacking position and stackup of the silicon substrate of the LNA, the vertically couplednoise is serious enough to obstruct the RF receiver operation; up
to 80mVpp and 500mVpp of noise are vertically coupled acrosseach inductor and at signal output of the LNA, respectively. The
vertical noise coupling measurement results of this paper awake
the seriousness of the vertical noise coupling issue in 3D-IC
mixed-signal systems and can be a reference for the estimation ofamount of vertical noise coupling in 3D-IC mixed-signal systemdesign.

as shown in Fig. 1. The noise coupling can be more severe in
3D-IC than 2D SoC since several hundreds of µm distance
between digital and sensitive RF/analog circuits in 2D SoC, Fig.
1 (a), is reduced to only a few tens of µm, Fig. 1 (b), between
stacked digital and sensitive RF/analog chips.

(a)Keywords-component; Vertical noise coupling; 3D-IC; On-chip
switching DC-DC converter; Low noise amplifier (LNA)I.

INTRODUCTION

3D-IC is a new promising technology for designing amixed-signal system. 2D System-on-Chip (SoC) integration of
mixed-signal signal system has been using deep-submicron
CMOS technologies due to its large scale integration and low
cost. However, the deeply scaled CMOS technologies have
many limitations for designing RF/analog circuits such asleakage, low gain and more process variations due to reduced
supply voltage [1]. The 3D-IC technology resolves the
problems by enabling technology mix same as System-inPackage (SiP) technology. We can use proper technologies foreach of digital and RF/analog circuits. In the same time 3D-IC
technology provides much smaller form factors than using SiP
technology in the mixed-signal system design. These are great
advantages in an optimization of the performance, size and costof the mixed-signal system. However, in 3D-IC mixed-signal
system, a new unanticipated noise coupling path by near field
coupling between logic ICs and RF/analog ICs is introduced.
Previous researches [2,3] report that serious noise canvertically couple between stacked-chips by near-field coupling(b)
Figure 1. (a) Substrate noise coupling in mixed-signal system in 2D SOC (b)Vertical noise coupling between stacked digital and sensitive RF/analog chipsof mixed-signal system in 3D-IC by near-field coupling

In this paper, the frequency domain and time-domain
measurement result of the vertical noise coupling on wideband
low noise amplifier (LNA) from 200MHz on-chip switchingmode DC-DC converter in 3D-IC configuration are reported.
Chapter II describes various test vehicle designs for themeasurement; variations in stacking position of top-chip in 3DIC configuration and stack-up of the silicon substrate of the
LNA. Chapter III presents, first, measured vertical transfer
impedances between the noise source in the on-chip DC-DC
converter and inductors of the LNA up to 10GHz at those test
vehicles using on-chip probes. Then, measured verticallycoupled noises across the inductors of the LNA and at the LNA
output are presented. The measurement results of this paper
reveal the seriousness of the vertical noise coupling issue in

3D-IC mixed-signal systems and can be a reference for theestimation of amount of vertical noise coupling in 3D-IC
mixed-signal system design.
II.

TEST VEHICLE DESIGN

A. 200MHz On-chip DC-DC Converter Design
Fig. 2 depicts the schematic and chip-photo of the powerstage of 200MHz on-chip DC-DC converter. It is asynchronous buck switching DC-DC converter. Table I
summarizes the measured performance of the DC-DC
converter. Including 37nH on-chip spiral inductor and 2.5nF
on-chip filter capacitor, all components of the power stage areintegrated in the chip.

(b)

(c)
Figure 3. (a) Schematic and (b) chip-photo of wideband LNA (c) chip-photoof inductors of wideband LNA for vertical noise coupling measurement
TABLE II.

Figure 2. Schematic and chip-photo of 200MHz on-chip DC-DC converter
TABLE I.

MEASURED PERFORMANCE OF ON-CHIP DC-DC CONVERTERTechnology

CMOS 6M1P 0.18µm

Switching Frequency

200MHz

VDDin/VDDout

3.3V / 0.6~2.5V

Max. Iout / Min. Iout

200mA / 60mA

Max. Vripple
Max. Power Conversion
Efficiency<70mVpp~63%

B. Wideband LNA Design(a)

MEASURED PERFORMANCE OF WIDEBAND LNA

Technology

CMOS 6M1P 0.18µm

Operation Frequency Band

600M~3GHz

In/Output Matching<-10dB

Noise Figure~2.7dBGain

10~14dB

IP3 (input)

5.1dBm

P1dB-5.02dBm

The schematic and chip-photo of wideband LNA are shownin Fig. 3 (a) and (b). The LNA is cross-coupled differential
common-gate LNA [4]. It is applicable for 900MHz, 2.4GHz
ISM band applications. Table II summarizes the measured
performance of the wideband LNA. In the LNA chip shown in
Fig. 3 (c), inductors of wideband LNA, L+ and L- in Fig. 3 (a),are disconnected from the actives and have probing pads forvertical noise coupling measurement on-chip.
C. Final Test Vehicle
The final test vehicle is PCB mounted 2-chip stacked 3DIC as shown in Fig. 4 (a) and (b). The LNA chip is stacked on
the on-chip DC-DC converter with 20!m epoxy adhesive.
There are 3 types of variations in the final test vehicles. First, it
is in the type of LNA chips. TVcoupling set in Fig. 4 (a) uses thechip in Fig. 3 (c), which only contains inductors for LNA, as
the top-chip. TVLNAout set in Fig. 4 (b) uses the chip in Fig. 3(b), which contains full LNA circuit. TVcoupling set is for a direct
measurement of the vertical noise coupling from Vp of the onchip DC-DC converter to L+,L- of the LNA using on-chipprobing. In TVLNAout set, we measure vertically coupled noise at
off-chip LNA output from the on-chip DC-DC converter
switching in time-domain. Second, the variation is in the
thickness of silicon substrate of the LNA. The silicon substrateof the LNA is thinned to be 50!m in TV50u and 100!m in
TV100u as shown in Fig. 4(b). This variation is to measure theimpact of silicon substrate thickness of victim chip on theamount of vertical noise coupling.

For the last, the variation is in the stacking position of the
top chip (LNA) as shown in Fig. 4 (c). The description of the
final test vehicles and their names are summarized in Table III.
All the input/output signal of the LNA and the DC-DC
converter is wire-bonded out to the off-chip PCB. The PCB is a
simple pair of power/ground plane. There is no electricalconnection through the adhesive between the on-chip DC-DC
converter and the LNA.
III.

MEASUREMENT OF VERTICAL NOISE COUPLING

A. Source of Vertical Noise Coupling

(a)

(b)

Figure 5. (a) Measured switching voltage at Vp and DC output at VDDout of
the on-chip DC-DC converter with high-Z on-chip probe (b) Existence of highfrequency component up to 3.2GHz in the power spectrum of the switchingvoltage at Vp(c)Figure 4. Chip-photo and cross-section of final test vehicles: 2-chip stacked
3D-IC (a) TVcoupling : Test vehicle for vertical noise coupling measurementfrom Vp to L+/L- (b) TVLNAout : Test vehicle for measurement of verticallycoupled noise at LNA output (RFOut+/-) (c) TVCenter, TVUpper : Test vehicles withvariation in the position of the top chip (LNA)
TABLE III.

FINAL TEST VEHICLE SETS

Description of test vehicle set

Notation of test vehicle set

Variation in LNA chip
Variation in silicon substrate
thickness of the LNA chip
Variation in stacking positionof the LNA chip

TVCoupling/LNAout

Example of the name of final
test vehicle

TV50u/100u
TVCenter/Upper
TVCoupling/50u/Center

It is well known that the switching of the on-chip switching
DC-DC converter is the #1 source of EMI [2]. Accordingly, thesource of vertical noise coupling in the 200MHz on-chip DCDC converter is switching at Vp. Fig. 5 (a) shows the measured
voltage of switching at Vp and DC output voltage at VDDout
with high-Z on-chip probe. At Vp, there is 3.3V 200MHz
switching with duty of PWM input of the on-chip DC-DC
converter. In the measurement setup, the PWM input has half
duty and the load at the output is 18ohm. Accordingly, the DC
output voltage at VDDout becomes ~1.5V with 60mVpp voltage
ripple. Due to parasitic series inductance of input decoupling
capacitors and on-chip interconnections to off-chip VDDin,some ringing are found in the switching waveform of Vp.
Noticeable frequency spectrum components exist up to 3.2GHz
as shown in Fig. 5 (b).

B. Direct Measurement of Vertical Noise Coupling from Vp ofthe On-chip DC-DC Converter to Inductors of LNA
1) In Frequency Domain: The switching at Vp is verticallycoupled mainly to the inductors, L+ and L-, of the LNA [2]. It
is an inductive coupling since a capacitive coupling is
negligibly small due to the grounded substrate of the LNA [3].
The inductive coupling from Vp to bond-wires of LNA is also
ignored since it is negligibly small due to following reasons; 1)
they are vertically farther away than the L+ and L- from theVp and L 2) the direction of bond-wires is perpendicular to thedirection of inductor current at the right side of L.The verticalnoise coupling from Vp, noise source, of the on-chip DC-DC
converter to L+ and L- , noise victims, in the TVCoupling set aremeasured in terms of transfer impedance from 1MHz to
10GHz using 2-port Vector Network Analyzer and 50¡ onchip probes. Fig. 6 plots the transfer impedance from Vp to
L+,L- in TVCoupling/50u/Center. We choose transfer impedance
instead of s-parameter to evaluate the amount of veritcal
coupling since s-parameter assumes 50¡ termination at every
ports, which is not a realistic situation in an on-chip circuit.
The transfer impedance measurement cannot be done undertime-variant condition such as switching events at the on-chip
DC-DC converter. In that reason, we measure the transfer
impedance at 2 equivalent switching conditions of on-chip
DC-DC converter: HDRV on, LDRV off and HDRV off,
LDRV on. HDRV on, LDRV off condition is when theswitching at Vp goes to 3.3V from 0V. The high-side driver,
HDRV in Fugire 2, turns on and the low-side driver, LDRV,
turns off in that case. In the same manner, HDRV off, LDRV
on equals to the falling of the switching at Vp.

Figure 6. Measured vertical transfer impedance from Vp to L+/- in
TVCoupling/50u/Center from 2-port VNA measurement

In Fig. 6, we found that the HDRV on, LDRV off
condition shows larger and inductive transfer impedance than
HDRV off, LDRV on conditon in the 200MHz to 1GHz
frequency band. From the result, we can expect that there will
be more vertical noise coupling at the rising of the 200MHz
switching, up to 5th harmonics of the fundamental switchingfrequency component of the on-chip DC-DC converter. The
peak around 2GHz is from the resonance due to inductance of
L+/L- and capacitance reference to the silicon substrate. The
transfer impedance from Vp to L+, solid lines, and from Vp to
L-, dashed lines, do not different in the magnitude since theL+ and L- are symmetrically located to the center of theinductor, L, of the on-chip DC-DC converter.

Figure 7. Comparison of the measured vertical transfer impedance from Vp
to L+/- in (a),(b) TVCoupling/50u/Center and TVCoupling/50u/Upper (c),(d) TVCoupling/50u/Center
and TVCoupling/100u/Center

In Fig. 7 (a) and (b), we change the stacking position of the
top chip, LNA. TVCoupling/50u/Center shows larger transfer
impedance in 200MHz to 1GHz frequency band than
TVCoupling/50u/Upper in both cases: from Vp to L+ and from Vp to
L-. The difference between 2 TVs are greater in case of from
Vp to L-. This is natural since L+ and L- are moved away fromthe center of the L in TVCoupling/50u/Upper and L- is the one which
is moved farther away as depicted in Fig. 4 (c). The mutual
inductances extracted from the measurements are 1.1nH from
Vp to L+ and from Vp to L- of TVCoupling/50u/Center. It is
0.35nH/0.08nH from Vp to L+ and from Vp to L- of
TVCoupling/50u/Upper, respectively.
In Fig. 7 (c) and (d), TVCoupling/100u/Center shows less inductive
transfer impedance in 200MHz to 1GHz frequency band than
TVCoupling/50u/Upper in both cases: from Vp to L+ and from Vp to
L-. 50!m thicker silicon substrate of TVCoupling/100u/Center securesmore distance from Vp to L+/L-. The mutual inductances
extracted from the measurements are 0.5nH from Vp to L+ andfrom Vp to L- of TVCoupling/100u/Center. However, the transfer
impedance over 1GHz frequency has relatively less changes
than that of 200MHz to 1GHz frequency band. The transfer
impedance over 1GHz frequency is capacitive rather than
inductive. The capacitive coupling is less sensitive to thechanges in thickness of silicon substrate of the LNA due tobulk conductivity of the silicon substrate [5].
2) In Time Domain: Fig. 8 (a), (b) and (c) plot measured
vertically coupled noise across inductors of the LNA, L+/-,from the on-chip DC-DC converter switching in
TVCoupling/50u/Center, TVCoupling/50u/Upper and TVCoupling/100u/Center,
respectively. In TVCoupling/50u/Center, the vertically coupled noise
across L+ and L- are having almost same amplitude, about
80mVpp, but out-of-phased. This is because L+ and L- aremirror symmetric to the center of the inductor, L, of the onchip DC-DC converter. The polartiy of mutual inductance toL+ and L- are opposite. The polarity is also opssite in
TVCoupling/100u/Center in Fig. 8 (c). Only the amplitude of thevertically coupled noise across inductors has been reduced to36/31.5mVpp for L+ and L-, respectively. This change is easily
understandable from the direct measurement of vertical noise
coupling in Fig. 7 (c),(d). In case of TVCoupling/50u/Upper in Fig. 8(b), the vertically coupled noise across L+ and L- are inphased. This is because the L+ and L- are having samepolartiy of mutual inductance to the inductor L since both ofthem are placed at the outter side of the inductor L of the onchip DC-DC converter. It shows that there can be some
optimal placement of inductors to make the vertically couplednoise across the inductors a common-mode. Since the LNA isfully balanced, the common-mode vertically coupled noise
will be canceled out at the differential LNA output. This is oneof the soulution to minimize the impact of vertical noise
coupling on the LNA.

Figure 8. Measured vertically coupled noise across L+/- from the on-chip
DC-DC converter switching in (a) TVCoupling/50u/Center (b) TVCoupling/50u/Upper (c)TVCoupling/100u/Center

C. Vertical Noise Coupling at LNA Output (RFOut+/-)Fig. 9 plots measured vertically coupled noise at LNA
output, RFOut+/-, from the on-chip DC-DC converter switchingin TVCoupling/50u/Center, TVCoupling/50u/Upper and TVCoupling/100u/Center.
LNA inputs are all 50˖ terminated without RF signal input tomeasure a pure vertically coupled noise at the LNA output.
Due to the cross-coupled capacitor, CC in Fig. 3 (a), thevertically coupled noise at RFout+ and RFout- are out-of-phased
and have balanced amplitude even in TVCoupling/50u/Upper, whichshows in-phased and imbalanced vertically coupled noise
across L+ and L-. The vertically coupled noise at LNA output
is ranged from 100mVpp to 500mVpp. This amount is muchlarger than the vertically coupled noise across L+ and L- in Fig.

8. That is because LNA circuit amplifies the vertically couplednoise across L+ and L-. Table IV summarizes the measured
peak to peak vertically coupled noise.

Across inductor sof
LNA(mVpp)L+
L-

At LNA output(mVpp)
RFOutRFOut+

TVCoupling/50u/Center

80.5

78.5

TVCoupling/50u/Upper

35

16.5

449.9
97.6

506.89100.6

TVCoupling/100u/Center

36

31.6

365.83390.8

IV.

CONCLUSION

In this paper, the frequency domain and time-domain
measurement results of the vertical noise coupling on wideband
LNA from 200MHz on-chip switching-mode DC-DC converter
in 3D-IC configuration are reported. The test vehicles havevariations in stacking position and stack-up of the silicon
substrate of the LNA. The frequency domain measurement
results tell that the vertical noise coupling is inductive
dominant below 1GHz. From 3.3V 200MHz switching of the
on-chip DC-DC converter, measured vertically coupled noise is
up to 80mVpp and 500mVpp across each inductor and at LNA
output, respectively. Considering a typical RF signal of several
tens of mVpp in LNA output stage, it is clear that the verticalnoise coupling can cause serious problem in the RF receiver
operation. The vertical noise coupling measurement results ofthis paper awake the seriousness of the vertical noise couplingissue in 3D-IC mixed-signal systems and can be a reference forthe estimation of amount of vertical noise coupling in 3D-IC
mixed-signal system design.
ACKNOWLEDGMENT
This work was supported by the IT R&D program of
MKE/KEIT. [KI001472, Wafer Level 3D IC Design andIntegration]
REFERENCES
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[2]

[3]
[4]

Figure 9. Measured vertically coupled noise at LNA output (RFOut+/-) fromthe on-chip DC-DC converter switching in (a) TVCoupling/50u/Center (b)TVCoupling/50u/Upper (c) TVCoupling/100u/Center
TABLE IV.
SUMMARY OF THE MEASURED PEAK-TO-PEAK VERTICALLYCOUPLED NOISE AT WIDEBAND LNA FROM ON-CHIP DC-DC CONVERTER[5]

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