1PP ASIC
Overview and Prototype Test Results
Shuichi Ito and the TGC Electronics GroupFinal Design Review
6 Dec. 2018

Contents●Introduction●Target design●Prototype design and test results- LVDS receiver- PLL and variable delay- BCID- Power consumption●Gamma irradiation test for prototype chips●Summary2

Phase II TGC Trigger and Readout System
Thin Gap Chamber (TGC)ΦR

Two-dimensional measurements
by the wires and the strips

Replace all boards except for ASDs for an extension of thefrst-level trigger rate (1 MHz) and latency (10 μs).
All hit signals will be transferred to the of-detector boards.

3Phase II TGC PS Board Overview
Phase II TGC PS board contains PP ASICs, FPGAs, etc.

4PP ASIC･ Receive LVDS signals from ASDs,
and align the timing.
Send the aligned signals to FPGA.
･ Send test pulse to ASDs.

FPGA･ Collect signals from PP ASICs
and transfer to of-detector(8 Gbps × 2 = 16 Gbps)･ Control threshold voltage of thediscriminators of ASDs.

Phase II TGC PP ASIC Timeline

5Preliminary Design Review (PDR) was held on 6 Mar. 2018.
The tapeout of the prototype fnished in Jun. 2018.
Twenty packaged chips were delivered on 3 Oct. 2018.
Prototype layout

Test board with the PP ASIC prototype

Target Specifcation
Design process

Silterra 0.18 μm CMOS 6M1P

Supply voltage

3.3 V (LVDS Rx, TPG Driver)
1.8 V (PLL, Delay line, CMOS input and output)
Voltage tolerance : ± 10 %# of channels

Group A (16 ch), Group B (16 ch)

Timing control resolution< 1 nsTiming control range> 40 ns

Timing jitter< 0.1 ns (RMS)

Temperature range

10 ~ 70 ℃

Power consumption

130 mW (previous design) or less6

LVDS Receiver7

Schematic of LVDS Receiver●LVDS Rx consists of two diferential amplifers and two stages ofinverter.

●Level shifter is implemented in LVDS Rx. (3.3 V → 1.8 V)●DC power consumption is 0.23 mW from 3.3 V.(70 μA × 3.3 V)●

8LVDS Rx is not fully compatible with the LVDS Rx standard
specifcaition (IEEE 1596.3).

From ASD
board

To
delay line

Delay Dependence on Ofset and Amplitude
Delay of the LVDS reciever was measured depending on amplitude and ofset.
Ofset voltage is defned to be the central voltage of the input diferential signals.
Jitter : ~ 40 ps
Target range

1.8VCMOS output

Target range

The measured delay is the sum of the propagation delay of the receiver, themultiplexer, and the output bufer.
The dalay is 4.6 ± 0.1 ns for target ranges of amplitude and ofset.

satisfes the requirement of timing control resolution < 1 ns.

9Delay Dependence on VDD and Ofset
Delay of the LVDS receiver was measured depending on VDD and ofset.

Target range

Target range

The delay is 4.6 ± 0.1 ns for target ranges of VDD and ofset
satisfes the requirement of timing control resolution < 1 ns.

10PLL and Variable Delay

11

PLL and Variable Delay Line●●●A common delay cell design is used in both PLL and variable delaylines. They are controlled by a common bias voltage which is generated
from charge pump circuit in PLL.
PLL keeps the signal propagation delay of the ring at 25 ns.
The number of delay cells in PLL can be changed from 20 to 32 via
SPI control signal.
The propagation delay of the variable delay will be kept constantagainst the changes of oparation conditions.

12Relation between Delay and Control Voltage (V CON)

13

Delay of a delay cell of 10 chips was measured depending on V CON.

VCON was supplied by DC power supply.
Oscilloscope
DELIN

Pulse generator
DELIN
DC power supply
VCON

PPASICDELOUT
1.25

PLL STEP
20

0.75

32

The delay can be changed from 0.5 ns to 3 ns.
The requirement of timing control resolution < 1 ns is satisfed with margin.

Comparison with the Simulation

The measured delay for prototype v.0 is similar to the Layout Parasitic
Extraction (LPE) simulation with typical condition.
The prototype v.0 may not have enough margin in case of PLL STEP = 32.
For next version (v.1), the delay is reduced by changing the gate length oftransistor in the delay units.

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15

Delay Dependence on Temperature

PLL STEP
1.25

200.7532

The delay < 1 ns is covered for 0-80 degrees.

Linearity of the Variable Delay
Jitter : ~ 40 ps
PLL STEP

Delay per step

Control range

20

1.15 ns

54.1 ns240.96 ns

45.0 ns280.82 ns

38.1 ns

320.73 ns

34.2 ns

The linearity has been confrmed for all STEP confgurations.
The delay of single step is < 1 ns (target specifcation) for STEP ≧ 24.
The dynamic range is greater than the target specifcation.

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17

Performance of the Variable Delay Depending on VDD
The linearity of variable delay was confrmed for VDD = 1.62-1.98 V.

Performance of the Variable Delay
Depending on Temperature

The linearity of variable delay was confrmed for 0-80 degrees.

18

BCID

19

BCID

The BCID circuit synchronises the signals with 40 MHz clock.
Each rising edge of the 40 MHz clock corresponds to a bunch crossing.
BCID_Delay is used to adjust for the phase diference between the 40 MHz
clock and the earliest arrival times of signals from ASDs.
BCID_Gate is used to adjust the efective gate width. Each signal is assigned toeither one or two bunch crossings depending on the timing.

20

BCID Test Results●BCID GATE = 1●

BCID GATE = 26

27 ns

The functions of BCID circuit have been confrmed.

46 ns

21

Test Pulse Generator (TPG)

22Test Pulse Generator (TPG)
1CoarseDelay

TPG TRIGREF CLK(40MHz)

TPG TRIG

D0D

REF CLKQRQ1QR

DQR

QRN
CounterN = 400 ?
True 1,False 06

Q

REF CLKDQR

Q

TPG
Fine Delay
Output7

SPI

TPG generates the pulse with coarse delay (0-7 CLK).
The pulse is set via SPI in a range from 25 ns to 102.4 μs.
TPG output delay time is controlled by another fne delay (0-40 ns, < 1 nsresolution).

23

TPG
OutputTPG Driver
Drivability of TPG driver can be controlled by▪ Changing the number of current sources (EN[0-14])▪ Changing the bias current using variable resistor.
Load condition in measurements: 100 Ω/20 pF

24

TPG Driver Test Results
The amplitude was measured depending on temperature and VDD.
●Dependence on temperature●Dependence on VDD

The amplitude used for daily calibration in Run 1 and Run 2 is ~300 mV.
A similar value is assumed for Run 4 and the beyond.
The dependence on VDD is safely small for the daily calibration.

25

Power Consumption
10 pF load capacitance at LVCMOS outputs●Power consumption of TPG driver is not included.
●0.2 MHzThe power consumption is ~ 20 mW (0.63 mW/ch) under an expected hit rate of~0.2 MHz per channel at a luminosity of 7.5 × 10 34 cm-2s-1.
Note that the chip of the current system consumes ~130 mW.

26

YieldThe yield has been studied by measuring the performance of prototype v.0 chips.
In total 20 chips were produced, and 19 of them were measured.
One chip was damaged before the measurement by a wrong setup of power
supply outside the chip.
For all channels of 19 chips, two sets of pulse input were provided: 10 kHz and10 MHz.
For all channels, output signals were observed.
The power consumption for 10 kHz (10 MHz) input ranges
from 17 mW to 21 mW (from 44 mW to 51 mW) depending on the chips.
Although the measurements performed for all chips were limited,
the results indicate that the 19 chips have no signifcant failures.

27

Radiation Tolerance for Total Ionising Dose

Total ionising dose for L = 4000 fb-1 is estimated to be 6.0 Gy.
Requirement for PP ASIC is 27 Gy.
(SFsim × SFldr × SFlot = 1.5 × 1.5 × 2 = 4.5)28

Gamma Irradiation Test Setup
Facility: Cobalt 60 facility in Nagoya University
Dose rate: 8.2 Gy/min
Total dose: 1 kGy for three chips, 10 kGy for one chip
Irradiation room

PowerSupply
PP ASIC

SourceSource29Gamma Irradiation Test Result●

PLL and Variable Delay
Relation between the control voltage V CON and the measured delay of a delay
cell unit for total ionizing doses of 0 Gy, 1 kGy, and 10 kGy.

No signifcant change was observed.

30

Gamma Irradiation Test Result●

PLL and Variable Delay
The control voltage V CON for the PLL circuit locked with an external reference
clock of 40 MHz depending on the ionizing dose.
No signifcant change was observed.

Requirement: 0.027 kGy

31

Gamma Irradiation Test Result●

PLL and Variable DelayRelation between the setup of the number of delay cell units (“delay step”) andthe measured delay of the variable delay for total ionizing doses of 0 Gy, 1 kGy,
and 10 kGy. No signifcant change was observed.

32

Gamma Irradiation Test Result●Test Pulse Generator
The amplitude of the test pulse generator output depending on the number ofcurrent sources for total ionizing doses of 0 Gy, 1 kGy, and 10 kGy.
No signifcant change was observed.

33

Gamma Irradiation Test Result●Power consumption
The power consumption depending on the ionizing dose.
No signifcant change was observed.

Requirement: 0.027 kGy

34

Prototype ASIC v.0 Specifcation
Design process

Silterra 0.18 μs CMOS 6M1P

Supply voltage

3.3 V (LVDS Rx, TPG Driver)
1.8 V (PLL, Delay line, CMOS input and output)
Voltage tolerance : ± 10 %# of channels

Group A (16 ch), Group B (16 ch)

Timing control resolution< 1 nsTiming control range> 40 ns

Timing jitter~40 ps (LVDS Rx), ~40 ps (Variable Delay)

Temperature range

0 ~ 80 ℃

Power consumption~20 mW (Previous design: 130 mW)

All requirements are satisfed.

35Modifcation for Next Version●●

Change the gate length of transistor in the delay units for reducing thedelay time for an improved margin. See page 14.
Prototype v.0 has a wrong edge setup of SPI MISO signal.
Although it is fne for the use if the device controlling the PP ASIC

uses the corresponding edge, as done for prototype v.0 measurement,
we modifed the circuit for next version.
Before modifcation

After modifcation

The modifcations are very simple and already completed.

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