IoT-oriented RISC-V-based SOTB-65nm
System-on-Chip Implementations
Khai-Duy Nguyen, Koichiro Ishibashi, Cong-Kha Pham, andTrong-Thuc Hoang
Department of Computer and Network Engineering,
The University of Electro-Communications, Tokyo, Japan

June 20th, 2023

Outline● Introduction● System On Chip
○ System Architecture○ Core Architecture● Measurement and Results● Conclusions

2

Introduction
IoT Application

3

Introduction
IoT Application
CoreBus

MemoryPeripherals

I/O
4Introduction
IoT Application
CoreBus

MemoryPeripherals

I/O
5Introduction

Open8[1] 8-bit Processor in SOTB 65nm
[1] M. Sarmiento et al., IEEE TCAS-II, 2021.
[2] R. Serrano et al., ISOCC, 2021.

[2] 32-bit RISC-V SERV in 0.18μm.
6SERV SoC

Open8 SoC

RAM 16KB

Introduction[3] 8-bit and 32-bit in 0.18μm CMOS.
[3]M. Sarmiento et al., IEEE TCAS-II, 2022.

Power consumption of the SoCs at 32-kHz
and different VDD.
7

Outline● Introduction● System On Chip
○ System Architecture○ Core Architecture● Measurement and Results● Conclusions

8

System Architecture
SERV

I$

D$

Arbiter

SPI port

JTAG port

SPI Prog.

Debug
SystemWishbone
RAMROMUART

GPIO

SPIMem.

SPICtrl.

UART
PortGPIO
Port

Ext. SPI
MemorySPI PortTimer

9Outline● Introduction● System On Chip
○ System Architecture○ Core Architecture● Measurement and Results● Conclusions

10

Core Architecture
Address

csr_imm

4

CSRs

imm
buf

SRs

Inst.
Mem.

en cntInstruction
csr
Reg mtvec
File rs2
rs1

PC

ALU+cSRsenInstr.
Decoder Control
Signals+mepc
csr_rdreg_adr
alu_rdbuf_rdmem_rdReg
FileAddress

SRs

Wr_Dataen ackData
Mem.
Rd_Data11

Core Architecture
Address

csr_imm

4

CSRs

imm
bufSRsInst.
Mem.

en cntInstruction
csrReg mtvec
File rs2
rs1

PC

ALU+cSRs

enInstr.
Decoder Control
Signals+

mepc
csr_rdreg_adr
alu_rdbuf_rdmem_rdReg
FileAddress

SRs

Wr_Dataen ackData
Mem.
Rd_Data12

Core Architecture
Address

csr_imm

4

CSRs

imm
bufSRsInst.
Mem.

en cntInstruction
csr
Reg mtvec
File rs2
rs1

PC

ALU+cSRsenInstr.
Decoder Control
Signals+

mepc
csr_rdreg_adr
alu_rdbuf_rdmem_rdReg
FileAddress

SRs

Wr_Dataen ackData
Mem.
Rd_Data
13Outline● Introduction● System On Chip
○ System Architecture○ Core Architecture● Measurement and Results● Conclusions

14

Measurement and Results

15Measurement and Results

Area distribution of SoCs.
•16 registers = 28% core footprint•

SERV-32E is approximately 17%smaller than SERV-32I

16

Measurement and Results

SERV SoCs power breakdown:
SERV-32I is 1.5 times moreenergy than SERV-32E

17

Measurement and Results
Table I. ASIC Implementation in comparison.

19

Outline● Introduction● System On Chip
○ System Architecture○ Core Architecture● Measurement and Results● Conclusions

20

Conclusions

This paper presents two SERV serial architecture SoCs based on the RISCV specification, SERV-32I, and SERV-32E. We have shown how
architectural heterogeneity affects area overhead and power consumption.
In terms of area, cutting 16 registers in the RF reduces the footprint by28% of the processor. In terms of power consumption, the power
consumption of the SERV-32I is about 1.5 times higher than that of theSERV-32E in the reverse-body bias region.

21

Thank You For Your Listening

Acknowledgement
This work was supported by JST-CREST Grant Number JPMJCR16Q1. It is alsosupported by VDEC, the University of Tokyo, in collaboration with Synopsys,Inc., Cadence Design Systems Inc., Mentor Inc., Renesas Electronics Corp., andNippon Systemware Co., Ltd23

Acknowledgement
1.M. Sarmiento et al., “A Sub-µW Reversed Body-Bias 8-bit Processor on 65-nm Silicon-on-Thin-Box(SOTB) for IoT Applications,” IEEE TCAS-II, vol. 68, no. 9, pp. 3182–3186, Jun. 2021.
2.R. Serrano et al., “A Low-Power Low-Area SoC based in RISC-V Processor for IoT Applications,” inISOCC, Oct. 2021, pp. 375–376.
3.M. Sarmiento et al., “Systems on a Chip With 8 and 32 Bits Processors in 0.18-μm Technology for IoTApplications,” IEEE TCAS-II, vol. 69, no. 9, pp. 2438 - 2442, May 2022.
4.K. Ishibashi et al., “A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14µA sleep current using Reverse
Body Bias Assisted 65nm SOTB CMOS technology,” in IEEE COOL Chips, Apr. 2014, pp. 1–3.
5.Always-On 674µ W@4GOP/s Error Resilient Binary Neural Networks With Aggressive SRAM Voltage
Scaling on a 22-nm IoT End-Node,” IEEE TCAS-I, vol. 67, no. 11, pp. 3905–3918, Nov. 2020.
6.D. Walter et al., “A 0.55V ¨ 6.3µW/MHz Arm Cortex-M4 MCU with Adaptive Reverse Body Bias and Single
Rail SRAM,” in IEEE COOL Chips, Apr. 2020, pp. 1–3.
7.D. Bol et al., “SleepRunner: A 28-nm FDSOI ULP Cortex-M0 MCU With ULL SRAM and UFBR PVT
Compensation for 2.6–3.6-µW/DMIPS 40–80-MHz Active Mode and 131-nW/kB Fully Retentive Deep-Sleep
Mode,” IEEE JSSC., vol. 56, no. 7, pp. 2256–2269, Jul. 2021.
8.D. S. Truesdell et al., “A 6-140-nW 11Hz-8.2kHz DVFS RISC-V Mircoprocessor Using Scalable Dynamic
Leakage-Suppesstion Logic,” IEEE Solid-State Circ.Letters, vol. 2, no.8, pp.57-60, Aug. 2019.
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