An Effective Way to Perform Correlation Power Analysis
Attack on Cryptographic RISC-V SoC
Thai-Ha Tran, Cong-Kha Pham, and Trong-Thuc Hoang
University of Electro-Communications (UEC), Tokyo, Japan
Corresponding author: thaiha@vlsilab.ee.uec.ac.jp

I. INTRODUCTION

Since UC Berkeley first announced the RISC-V project in 2010, we have seen RICS-V System on Chips (SoCs) develop rapidly in the field ofinformation security, particularly in the development of cryptographic embedded systems. From an attacking perspective, however, SoC
designs still have weaknesses and are vulnerable to side-channel attacks, such as power consumption, electromagnetic radiation, thermal,etc. This poster is a part of our recent work, which has been accepted and is under publication in IEEE Transactions on Computers [1]. We
present an efficient strategy for attacking the cryptographic RISC-V SoC using the well-known Correlation Power Analysis (CPA) technique.
In CPA attacks, the attackers use a power model to predict the power consumption of the device under test. In each model, the effectivenessof an attack depends on the transition factor φ, which is a ratio related to different characteristics of the device’s power consumption. Thisproposal introduces a solution to estimate the quantity of leakage information by determining the relationship between the SNR and φ. The
experimental results show that applying the Switching Distance model brings the highest performance. In the best-case scenario, the numberof traces required to reveal the secret key can be reduced by 13.35% using our suggested range of transition factors.
II. ESTIMATE THE QUANTITY OF LEAKAGE INFORMATION

III. TARGETED RISC-V COMPUTER ARCHITECTURE
Table 2: Post-implementation utilization of different config.
Name ofconfigurations

Core #1

Core #2

Rocket1_32

Rocket_32

RocketR1_64
RocketBoomR_32

AES Accelerator
LUTs (%)

FFs (%)

-6.89

9.59

RocketR_64-

5.22

8.28

Rocket_32

BoomR_32

3.56

4.82

RocketR2_64

RocketR_64 RocketR_64

3.38

5.51

BoomR1_64

BoomR_64

3.09

4.87

-

COREPLEX
RISC-V core #1
I$RISC-V core #2

D$

I$

D$

TileLinkSystem bus

TileLinkPeripheral bus

Memory bus

Table 1: Powerconsumption models [2].
Transition
HW HD
factors

SHA3

Ed25519

AES
128/256

PRNGSDφ00000φ01111φ1001φφ11100

SNR TileLink toAXI4DDRcontroller

SPI

UARTGPIOFig. 2: The targeted RISC-V SoC architecture.
IV. EXPERIMENTAL RESULTS

Var  Pactive   Var  Pidle Var  Pidle (0)(0)
 SNR0   01   10 


(1)
(1)
 SNR1   01    10 Fig. 1: Histogram of power consumption.
REFERENCES[1] T. -H. Tran et al., "Transition Factors of Power Consumption Models for CPA Attacks on
Cryptographic RISC-V SoC," in IEEE Transactions on Computers.
doi: 10.1109/TC.2023.3262926.
[2] E. Peeters et al., “Power and electromagnetic analysis: Improved model, consequences
and comparisons,” Integration, vol. 40, no. 1, pp. 52–60, 2007.
[3] A. Waterman et al., “The RISC-V Instruction Set Manual, Volume I: User-Level ISA,
Version 2.0,” Tech. Rep. UCB/EECS-2014- 54, May 2014.
[4] A. Dorflinger et al., “A Comparative Survey of Open-Source Application-Class RISC-V
Processor Implementations”. USA: Association for Computing Machinery, 2021.

Fig. 3: Optimal range of transition factors.
 Recommended range: 0.85 ÷ 0.87

 Highest effectiveness: Gφ = 13.35 % at φ = 0.85