12Outline

The 5th COE Technical Presentation• Research Background– Testing of Interconnects– Design for 2-Pattern Testability– Related Works

A Design for 2-Pattern Testability of
System-on-Chip Interconnects• Serial 2-Pattern DFT• Parallel 2-Pattern DFT• Case Study• Conclusion

Yusuke Saga
Computer Design and Test Lab. (Fujiwara Lab.)

3

SoCs in Ubiquitous Systems

Testing of SoC

Many system-on-chips (SoCs) are used in ubiquitoussystem

SoC: Cores and interconnects
Testing by test access mechanism (TAM)

Hardware
SoC
SoC

Ubiquitous system

SoC
SoC

SoC
SoC

SoC
SoCTesting of Interconnects
High integration of interconnects
Bit lines of interconnects affect each other“Crosstalk”

TimeCcIllegal signal

01

TAMCoreTAMCore

6Maximal Aggressor (MA) Fault model(Cuviello et al., 1999)

Victim line is affected by transition at all aggressor lines

fault

Affection among
each lines

Test sequence

1-bit victim line, and (N-1)-bit aggressor lines
in N-bit interconnect

0 1 Crosstalk

01

Interconnect
Interconnectunder
undertest
testCoreCore
TAM
TAM

Test response

500

Test response sink (TRS)

Test pattern source (TPS)

SoCs need high reliability

C4Aggressor lines

Victim lines Glitch(pos/neg)
0 1 10 1 10 0 10 1 10 1 1

TimeN-bit
Illegal signal00100Delay (r/f) Speed-up
1 0 00 1 1 0 (r/f)
0 1 1 0 1 0 0
1 0 0 1 1 0 00 1 1 0 1 0 00 1 1 0 1 0 01111
14N+2 2-pattern test1

78

Design for 2-Pattern Testability (1/2)

Design for 2-Pattern Testability (2/2)

2-pattern testability

Design for testability (DFT)- Design a circuit to be tested easily (testability)
by adding extra hardware– 2-pattern controllability: capability to apply arbitrary
two patterns consecutively– 1-pattern observability: capability to observe arbitrary
one response
2-pattern controllability
Register
Register

n-bit

n-bit

n-bit
interconnect2-pattern
2-patterntestabletestableSoC
SoC

CoreCore

Register
Register

Register
RegisterTAM

1-pattern observability

Original
OriginalSoC
SoC

SoC
SoC

CoreCore

DFT
TAM

CoreCore

Core
Core

n-bit

910Related Works (1) - IEEE P1500 Wrappers

Testing of Interconnects by EXTESTArchitecture for SoC testing by IEEE

1. Scan test pattern into wrapper output cells
2. Apply test pattern to interconnects
3. Scan test response out from wrapper input cells- INTEST: Test mode for cores- EXTEST: Test mode for interconnects- BYPASS: Transparent mode for test of other cores
FFCoreCoreCoreCore11

Core
Core22

Wrapper cell

Wrapper
Wrapper11

Wrapper
Wrapper

Wrapper
Wrapper22

11

12

Testing of Interconnects by EXTEST

Testing of Interconnects by EXTEST

1. Scan test pattern into wrapper output cells
2. Apply test pattern to interconnects
3. Scan test response out from wrapper input cells

1. Scan test pattern into wrapper output cells
2. Apply test pattern to interconnects
3. Scan test response out from wrapper input cells

CoreCore11Wrapper
Wrapper11

CoreCore22Wrapper
Wrapper22CoreCore11CoreCore22Wrapper
11 and22
MA
areWrapper
Wrapper
MAtestingtestingand2-pattern
2-patterntesting
testingWrapper
areimpossible
impossible
bybyEXTESTEXTESTmodemode2

13

Related Works (2) - Design for Consecutive
Testability (Yoneda et al., 2002)

14

Objective of Our Work

Consecutive testability

We proposed two DFT methods for 2-pattern
testability of interconnects• Serial 2-pattern DFT - DFT with serial TAM– Consecutive controllability: capability to apply anarbitrary input sequence consecutively– Consecutive observability: capability to observe anarbitrary response sequence consecutively

SoC
SoC
SerialSerialn-bit
TAM
TAM
Interconnect
n-bit n-bit
n-bit

Testing of interconnects requires only two patterns
Area overhead can be reduced• Parallel 2-pattern DFT - DFT with parallel TAM

Consecutive test sequence Interconnect Consecutive test response
TPSTPS

SoC
SoC

under test

CoreCoreTRSTRSCoreCore

TPSTPSCoreCoreCoreCoreParallelParallel
n-bitInterconnect
TAM
TAM
n-bit n-bit
n-bit

TRSTRS

1516

Serial 2-Pattern DFT (1/2)

Serial 2-Pattern DFT (2/2)• Add wrappers to each core
• Add serial TAM through all wrappers• Add wrappers to each core
• Add serial TAM through all wrappers
To provide two patterns consecutively

cc2
2
cc1
1
Serial input

Wrapper
Wrapper

Serial TAM

Wrapper
Wrapper

cc3
3

cc4
4

Wrapper
input cells

Wrapper
Wrapper Serial output

Wrapper
Wrapper

Serial TAM

Wrapper
output cells
CoreCore
Wrapper
Wrapper

Serial TAM

1718

Serial 2-Pattern DFT ProblemSerial 2-Pattern DFT Algorithm

Input:
Output:1. Design of wrapper for each core
2. Optimal design of a serial TAM that makes
all interconnects 2-pattern testable

An SoCA serial TAM and wrappers that makeall interconnects 2-pattern testable
Objective: Minimizing hardware overhead(No. of registers and MUXs, and area of additional lines)
cc2
2
cc1
1
Serial input

Wrapper
Wrapper

Serial TAM

Wrapper
Wrapper

cc3
3

cc4
4
Wrapper
Wrapper Serial output

Wrapper
Wrapper319Parallel 2-Pattern DFT (1/3)

Parallel 2-Pattern DFT (2/3)

Design parallel TAM from TPS to TRS withregisters, MUXs and signal lines
n-bit

n-bit

Design parallel TAM from TPS to TRS withregisters, MUXs and signal lines
Parallel TAM internal:
Parallel TAM consists of extra hardware and existing interconnects

n-bit

2-pattern controllability

CoreCore

1-pattern observability

Primary input (TPS)

n-bit interconnect

This parallel TAM is not 2-pattern testable

Primary output(TRS)

Primary input(TPS)

CoreCore

20n/2-bit n-bit

n/2-bitParallel
ParallelTAMTAMn-bit
n-bit

n-bit
interconnect

CoreCoren/2-bit

21

Parallel 2-Pattern DFT (3/3)

22Parallel 2-Pattern DFT Problem
Input:
Output:An SoCA parallel TAM that makes all interconnects
2-pattern testable
Objective: Minimizing hardware overhead

Design parallel TAM from TPS to TRS withregisters, MUXs and signal lines
Parallel TAM internal:
Parallel TAM consists of extra hardware and existing interconnects(No. of registers and MUXs, and area of additional lines)

This parallel TAM is 2-pattern testable

CoreCore

n-bit
interconnect

n/2-bit n/2-bit

n-bit

n-bit

CoreCoreCoreCore

n-bit interconnect2-pattern controllability

1-pattern observability

Primary output(TRS)n/2-bitn-bit
Primary input(TPS)

Primary input (TPS)

n-bit

Parallel
ParallelTAM
TAM
n-bit
n-bit

2324

Parallel 2-Pattern DFT Algorithm

Case Study

1. Optimal design of a parallel TAM that makes allinterconnects 2-pattern controllable
2. Optimal augmentation of the parallel TAM thatmakes all interconnects 1-pattern observable

We apply three DFTs to this sample SoC:
• Serial 2-pattern DFT
e :16• Parallel 2-pattern DFTc4
v :(0,6)
ee :16e :16• Consecutive DFT(11,7) :16
c29PI

1

e2:16
v 2:(0,5)
PI1061e3:16

c1(3,5)

(7,6)

e7:16

c3(7,3)

e8:16

e4:16

e :16
Evaluation:• Number of MUXs
• Number of registers• Area of additional signal lines
5c5(11,4)

e11:32

POv 1:(18,6)
c6(15,6) e14 :32
vPO 2:(18,5)

e13:32
e12:32– Core external lines: bit width * Manhattan distance– Core internal lines: bit width because distance is 0

• Test application time of MA test4

25

26

Case Study Results

Conclusion

Serial 2-pattern DFT: Long test application time, large hardware area
Parallel 2-pattern DFT: Short test application time, small hardware area

We proposed designs for 2-pattern testability of interconnects

Serial 2-pattern DFT• Large hardware and long test application time

600

1400
1200
1000
8006004002000500
400300200
1000Registers (bit)350
300
250200150
100500Core internal lines(bit)

350
300
250
200

Parallel 2-pattern DFT• Small hardware and short test application time than both
serial 2-pattern DFT and consecutive DFT

150100500MUX (bit)
80000
70000
60000
50000
40000
30000
20000
10000
0Test application time (clock)Core external lines(bit*distance)

Parallel 2-pattern DFT is effective method

Serial 2-pattern DFT
Parallel 2-pattern DFTConsecutive DFT5