Distributed System
Exploration

Mirabilis Design Inc.

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Design Analysis 2:
Distributed Systemz System details• Multi-independent processing computers• Software tasks distributed across these computers• Connectivity across multiple shared networksz Analysis• Optimal Routing Table configuration• Capacity planning• Software tasks and thread distribution• Resource allocation
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Example 2: Distributed System
Logical Task Flow
M1

T2
M4

T1

M2
T4

M3

Initial Assignment

T3

List of Tasks: T1, T2, T3, T4
T1, T2 -> ECU_1T3 -> ECU_2
T4 -> ECU_3
Messages: M1, M2, M3, M4

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Mirabilis Design© Inc. ConfidentialSlide 3

Example 2: Distributed System
uP-Computer/Bus Physical Mapping
ECU_1

CAN_2

ECU_2

Bridge_2
CAN_3

Bridge_1

CAN_1

CAN_4

ECU_3

Bridge_4

Message Assignment•Messages: M1, M2, M3, M4• Internal to ECU, if Source ECU == Destination ECU•CAN_N bus segments selection based on Source:Destination of Task,•Routing is selected for shortest hops
•Dynamic allocation based on topology selection•An ECU is the equivalent of a core, processor or computer.
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Slide 4End-to-End Latency
RdWrRdWr

Signals SSSS

T1

T2

M1
RdWrSS• T1 writes latest S1(time) when task executes.
• M1 reads T1(time) via Middleware Buffer when it periodically executes, sends
packet through Bus structure.
• T2 reads M1(time) from buffer when it fires via Middleware Buffer, and if the lastnode, outputs end-to-end latency.
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Signal Table

Note: Destinations can be Tasks, or Messages
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Task/Message Table

Note: Read_Buffer, Write_Buffer columns can designate Tasks or Messages
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Routing Table

Note: Simple Source, Destination, Hop format
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Discovery Process
Discover Logical Path: M1 Source: T1 Destination: T2
Discover Physical Path: M1 Source: ECU_1 Destination: ECU_1First Hop Array:{"NONE"}

Final Hop Array:{{"CAN_1", "CAN_2", "CAN_3"}, {"CAN_1", "CAN_4", "CAN_3"}}

No Further Processing Required...

Discover Logical Path: M3 Source: T1 Destination: T3
Discover Physical Path: M3 Source: ECU_1 Destination: ECU_2

Discover Logical Path: M2 Source: T2 Destination: T4
Discover Physical Path: M2 Source: ECU_1 Destination: ECU_3

First Hop Array:{"CAN_1"}

First Hop Array:{"CAN_1"}

No Further Processing Required...

Second Hop Array:{"CAN_2", "CAN_4"}

Final Hop Array:{{"CAN_1"}}

Third Hop Array:{"CAN_3"}

Discover Logical Path: M4 Source: T2 Destination: T3
Discover Physical Path: M4 Source: ECU_1 Destination: ECU_2

Fourth Hop Array:{"NONE"}First Hop Array:{"CAN_1"}
No Further Processing Required...
Final Hop Array:{{"CAN_1"}}

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Slide 10End-to-End Delayz

End-to-End Delay is composed of the followingelements:• Task – Signal or Message (Signal) Middleware Buffer,
Periodic Task time, ECU Execution time
• Message – Task Middleware Buffer, Periodic Message time,Bus(n) Transfer timez

ECU Execution time:• Time due to arbitration/queueing, due to processingz

Bus Transfer time:• Time due to arbitration/queueing, due to transfer for each
Bus segment in a path.
Note: Receive Interrupt, or Polling can be added
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Slide 11End-to-End Delay Equation
Latency = Task (i ) Sample + Task (i ) Exec + Msg (i + 1) Sample + Msg (i + 1) Xmit
whereTask (i ) Sample = Sampling _ Delay _ of _ Application _ Software
Task (i ) Exec = Task _ Exec _ Time + Blocking _ due _ to _ Higher _ Pr iority
Msg (i + 1) Sample = Sampling _ Delay _ of _ Message
Msg (i + 1) Xmit = ΣMessage _ Xmit _ Time + Blocking _ due _ to _ Higher _ Pr iority

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Slide 12End-to-End Delay Histogram

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Task, Message Execution

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Slide 14Model Assumptionszzz

Each Task will execute periodically for a specified time on anECU, read from Middleware Buffers, or write a Signals from aprior Task from Middleware Buffers, desinated in a Table.
• Columns: Read_Buffer Write_Buffer
Each Message will execute periodically for a specified time,read from Middleware Buffers and send via Buses to a distant
Middleware Buffer.
• Same Columns: Read_Buffer Write_Buffer
If a Task accepts two Middleware Buffers, each will be retainedin an array to maintain proper end-to-end latency, or follow-on
processing.

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Slide 15Model Assumptions (cont)z

Deployment of Tasks to ECUs and Messages to Buses• Discovery process is flexible enough to allow the specification of the•zz

mapping of tasks (t1, t2, t3, t4) to ECUs and the automatic
determination of the mapping of messages (m1, m2, m3, m4) tobuses.
User can map Tasks to ECUs in a table format.

After Task completes, it will pass the transmit message, or
receive message, through bus segments to continue theprocess, unless destination is “NONE”.
Model will select M1, M2, M3… paths during initialization ofmodel and insert the shortest path into database memory foreach Task.

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Mirabilis Design© Inc. ConfidentialSlide 16

Model Advantageszzzzz

A Table-Driven model should scale simply by modifying the tableentries.
A Table-Driven model should allow entry of physical mapping, orrouting, from existing sources, some pre-processing to get into source,destination, hop format.
User can allocate Signals, Messages, Tasks, to perform What-If
scenarios.
• A single Script-based block can support 32 independent periodic
signals, tasks, or messages currently, and Mirabilis can provide 64
or 128 per block.
• One Table might be created and allocated to different tables in amodel.
Additional Task logic could be added, either in script form, block style,or C code.
Data structure fields can capture the internal flow with variable length
arrays containing physical names in one array and timestamps in a
double array.
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