An FPGA-based Implementation of Quantum Computer Simulator Qulacs
Kaijie WEI1
1Hideharu AMANO1

Takefumi MIYOSHI2

Graduate School of Science and Technology, Keio University

2

Yoshiki YAMAGUCHI3

WasaLabo, LLC.

3

Ryohei NIWASE3

Graduate School of Science and Technology, University of Tsukuba

Introduction

Qulacs Optimization using HLS

Quantum computing has achieved
significant developments, nevertheless, most quantum hardware
is only accessible to the publicthrough the cloud environment or
supercomputers. Among all challenges in the current emulator development, memory bomb comesto be the most severe problem fora practical quantum emulator. In
Figure1:
PhototypeofTrefoil
this research, we propose to use
Trefoil FPGA with an extensive
storage system to overcome resource limitations as shown in Figure 1. We summarize
our work as follows.

Taking H gate as an example:■ n-qubit quantum circuit with 2n states saved in vector state[ ]■ Target gate: t■ index0 = bn−1bn−2 . . . 0tbt−1bt−2 . . . b0
■ index1 = bn−1bn−2 . . . 1tbt−1bt−2 . . . b0
■ x0 = state[index0]; x1 = state[index0 + 1]
■ y0 = state[index1]; y1 = state[index1 + 1]
■ state[index0] = √12 (x0 + x1); state[index1] = √12 (y0 + y1)■ state[index0 + 1] = √12 (x0 − x1); state[index1 + 1] = √12 (y0 − y1)■ Working on all the state vectors bn−1 . . . b0
Streaming processing depending on target gate (t)’s location
Data stream optimization using buffering:■ A high-speed quantum simulator, Qulacs [1], on the M-KUBOS FPGA cluster■ HLS-based quantum gate implementations H gate, S gate, CNOT gate, and adense matrix computation■ Performance improvement to a similar level of the Ryzen sever■ Stable performance of increasing qubits with board extension

Quantum Gates
Figure 3: Hadamard gate optimization using buffering

A quantum state expression:  
10♣ψ⟩ = a0♣0⟩ + a1♣1⟩ (♣0⟩ =, ♣1⟩ =)01(1)n-qubit system:

Evaluation
Execution time of naive implementation:♣ψ⟩ = a0...00♣. . . 00⟩ + a0...01♣0 . . . 01⟩ + · · · + a1...11♣1 . . . 11⟩
   100
0
10
 + a0...01   + · · · + a1...11  ♣ψ⟩ = a0...00  ..  ..  .. 001Versatile Quantum Gate Implementation
Quantum Gate
Meaning
H (Hadamard)

Convert the qubit from clustering
state to uniform superposed state

SRotates qubits 90° around the Z
axis, counterclockwise

CNOT (ControlledNOT)

Entangle & disentangle Bell states

MatrixArbitrary 2 quantum gates
multiplication

Matrix
1 1√12 1 −1100 exp − iπ2
1000
0 1 0 0
0 0 0 1
0011(2)

Figure 4: Naive implementation concerning target qubit and execution time
Time evaluation of H gate after optimization

Target Platform
Figure 5: Hadamard gate evaluation after optimization

References
Y. Suzuki, Y. Kawase, Y. Masumura, Y. Hiraga, M. Nakadai, J. Chen, K. M.
Nakanishi, K. Mitarai, R. Imai, S. Tamiya, T. Yamamoto, T. Yan, T. Kawakubo,
Y. O. Nakagawa, Y. Ibe, Y. Zhang, H. Yamashita, H. Yoshimura, A. Hayashi, andK. Fujii, “Qulacs: a fast and versatile quantum circuit simulator for researchpurpose,” Quantum, vol. 5, p. 559, oct 2021. [Online]. Available:
https://doi.org/10.22331%2Fq-2021-10-06-559

Figure 2: M-KUBOS [2] architecture

K. Iizuka, H. Takagi, A. Kamei, K. Hironaka, and H. Amano, “Power analysis of
directly-connected FPGA clusters,” in 2022 IEEE Symposium in Low-Power andHigh-Speed Chips (COOL CHIPS), 2022, pp. 1–6.