Accelerating Custom Integrated Circuit Design:
Challenges, Innovations, and Open-Source Initiatives
Mehdi Saligane
University of Michigan
mehdi@umich.edu
June, 2023

●Evolution of Software Dev

Software Dev in the 90s○ Vendor provided compiler○ Toolchain incompatibilities○ OS dependent2

●Context and Background

Software Dev in the 90s○ Vendor provided compiler○ Toolchain incompatibilities
tnerr○ OS dependentuecliks
koov!
Lederahardw

3

●Lowering Costs & Barriers to Chip Design

Software Dev in the 90s○ Vendor provided compiler○ Toolchain incompatibilities
tnerr○ OS dependentueclikskoov!
Lederahardw

Describe your experience with(tapeout) toolchain in one word

No Response
22.5%
Neutral30.0%

Negative
47.5%

Survey of ~ 50 Students

4

●Lowering Costs & Barriers to Chip Design

Software Dev in the 90s○ Vendor provided compiler○ Toolchain incompatibilities
tnerr○ OS dependentuec

likskoov!
Lederahardw

Describe your experience with(tapeout) toolchain in one word

No Response
22.5%
Neutral30.0%

Negative
47.5%

Survey of ~ 50 Students

5

●Lowering Costs & Barriers to Chip Design

Software Dev in the 90s○ Vendor provided compiler○ Toolchain incompatibilities
tnerr○ OS dependentuecliks
koov!
Lederahardw

70 000 HW vs 830 000 SW
Eng.

Describe your experience with(tapeout) toolchain in one word

No Response
22.5%
Neutral30.0%

Negative
47.5%

Survey of ~ 50 Students

6

●Lowering Costs & Barriers to Chip Design

Software Dev in the 90s○ Vendor provided compiler○ Toolchain incompatibilities
tnerr○ OS dependentueclikskoov!
Lederahardw

Describe your experience with(tapeout) toolchain in one word

No Response
22.5%
Neutral30.0%

Negative
47.5%

Survey of ~ 50 Students

7

●Lowering Costs & Barriers to Chip Design

Software Dev in the 90s○ Vendor provided compiler○ Toolchain incompatibilities
tnerr○ OS dependentuec

likskoov!
Lederahardw

Describe your experience with(tapeout) toolchain in one word

No Response
22.5%
Neutral30.0%

Negative
47.5%

Survey of ~ 50 Students

70 000 HW vs 830 000 SW
Eng.

8

●

Lowering Costs & Barriers to Chip Design

Software Dev in the 90s○ Vendor provided compiler○ Toolchain incompatibilities
tnerr○ OS dependentueclikskoov!
Lederahardw

Is Hardware
Development Broken?

Describe your experience with(tapeout) toolchain in one word

No Response
22.5%
Neutral30.0%

Negative
47.5%

Survey of ~ 50 Students

9●Lowering Costs & Barriers to Chip DesignIs Hardware Development Broken?

Research $Saved
Source: ISSCC’23 - Plenary- T. Ansell and M. Saligane, "The Missing Pieces of Open Design Enablement: A
Recent History of Google Efforts : lnvited Paper," 2020 IEEE/ACM International
Conference On Computer Aided Design (ICCAD), San Diego, CA, USA, 2020.

Source: NIST

10

Traditional vs AutomatedAnalog DesignAnalog design flow
Manual/Custom●

Analog design ﬂow

Signiﬁcant number of manualand custom steps.

12Analog vs. Digital design flow

Automated

Manual/Custom●Analog design ﬂow●

Digital design (grid-based)
ﬂow

Signiﬁcant number of manualand custom steps.

Almost entirely automated.

13

Generated Analog into Digital design flow
SAR ADC Block Diagram

FASoC
Generator

ISSCC-2015

Temperature Sensor

D-LDO

Automated
Manual/Custom

ISSCC-2017

PLL

CICC-2010

DC-DC Converter

14Generated Analog into Digital design flow
SAR ADC Block Diagram

FASoC
Generator

ISSCC-2015

Temperature Sensor

D-LDO

Automated
Manual/Custom

ISSCC-2017

PLL

CICC-2010

DC-DC Converter

15Generated Analog into Digital design flow
SAR ADC Block Diagram

FASoC
Generator

ISSCC-2015

Temperature Sensor

D-LDO

Automated
Manual/Custom

ISSCC-2017PLL

CICC-2010

DC-DC Converter

ALIGN Automated Layout Generator

16

Initially only proprietary design flow
SAR ADC Block Diagram
Temperature Sensor
PLL

D-LDO
DC-DC Converter

Automated
Manual/Custom

17

Now proprietary or open source design flow
SAR ADC Block Diagram
Temperature Sensor
PLL

Automated
Manual/Custom

D-LDO
DC-DC Converter

OpenFASoC!
Automatedportableanalog18

Overview of FASOC
Fully Autonomous SoC Synthesis● DARPA IDEA Program (OpenROAD and FASoC)● Multi-University and Industry effort● Multiple tape-outs in TSMC 65, GF12LP, SkyWater 130nm

2.6mmTSMC65LP SoC (2019-08)

2mm

LDOs

https://fasoc.engin.umich.edu/2.6mm

First automated SoC
Fab’d in TSMC65nm

TempSenses
DCDC ARM
SRAM64KB
M0ADC core SRAMs
BT Tx
PLL

2mm
GF12LP SoC (2020-10)

19Overview of OpenFASOC Today
Fully Autonomous SoC Synthesis●●DARPA IDEA Program, now funded by Google, NIST and others
Multiple tape-outs in TSMC 65, GF12LP, SKY130, GF180MCU, Intel 16

CHIPS Alliance Workshop
2021-11

OpenPOWER AI Workshop
IBM - 2022-11

GF 12-nm GF 180

Intel 16-nm

CHIPS Alliance Technology Update2022-12MPW0

openfasoc.readthedocs.io

MPW1 MPW2 MPW4 MPW5 MPW6 MPW7

MPW8+ more!

SKY130<3 years, <10 people!

RISCV Alliance Japan2022-12

Trade-offs & Design Constraints Examples

D-LDO Power Routing Example
Performance loss caused by PnR○○

Large Series Resistance caused by wiringcongestion for increased array size
Unpredictable wiring due to random
placement of power cells

Narrow

Rseries

Wide●●

Unpredictable
Placement
Leads to More
Variation

DCO cells
DCO placements with Decap

Pre-PEX

Post-PEX22

D-LDO Power Routing Example
Constraints to improve
performance○○○○

Constraint less Post-PEX
R2 = 0.8865
Narrow

Scalable Constraint Post-PEX
R2 = 0.9993

Technology agnostic fencing toconstraint placements
Use power stripes to improve
series R problem
Automatic analysis of technology
database file for determining thestripe metal layers
Taped out in BiCMOS and bulk
130nm, TSMC 65LP and GF12LP
Improved
Predictability & Rseries
23

●Performance / Complexity Tradeoff

FASoC augments digital flow with APR tool placement/routing constraints andminimizes the (performance loss * complexity)24

On-Going Projects & Contributions

Open-Source IC & tapeouts➔ 1st Open Silicon Results

NIST Nanofabrication Accelerator➔ 1st Open Nanotechnology Platform➔ Cryogenic CMOS

Low-Power IC Design➔ Rapid Prototyping for Wearables

Hardware Security➔ 1st Open Root of Trust SoC

On-Going Projects & Contributions

Open-Source IC & tapeouts➔ 1st Open Silicon Results

NIST Nanofabrication Accelerator➔ 1st Open Nanotechnology Platform➔ Cryogenic CMOS

Low-Power IC Design➔ Rapid Prototyping for Wearables

Hardware Security➔ 1st Open Root of Trust SoC

27

28

OpenFASOC Demonstrator●MPW-I: 64 sensors + D-LDO

LDO in SKY130
3v3 to 1v8
ILOAD: 25mA

Actively contributing to the open source community●

1st open FASoC flow built on top of OpenROAD tools●

FASoC testchip in SKY130:○○○○

Focused on the Temp. Sensor Generator
Includes Caravel SoC
64 Temp. Sensor Mesh
LDO ported (~ a week)■■

Updatedcomparator
strongArm latch
5v native NMOS switch

64 sensor mesh
(3 Vt flavors)

toCaravel SoC +wishbone bus
Test-chip in MPW-I

29

Temperature Sensor Topology●Temperature Sensor Template DesignRelated Publication:--Q. Zhang et al., "An Open-Source and Autonomous Temperature Sensor Generator Verified With 64
Instances in SkyWater 130 nm for Comprehensive Design Space Exploration," in IEEE Solid-StateCircuits Letters, 2022.
M. Saligane, et al., "All-digital SoC thermal sensor using on-chip high order temperature curvaturecorrection," 2015 IEEE Custom Integrated Circuits Conference (CICC), San Jose, CA, USA, 2015.

30

Temperature Sensor Topology●Temperature Sensor Template Design31

Measurement Results●64 sensors array used for low-cost design space exploration

32

Measurement Results●Below 1 oC inaccuracy and SOTA results

33Summary Results●●

Only working Chip from MPW-I using Open Tools
Published at the Solid-State Circuits Letters!

34

OpenFASOC on MPW-II:●●

1st Open Source AMS SoC

Included initial support for voltage domains inOpenROAD

Array of 10
D-LDOsVoltage Refs. +analog buffers

Implementation of the OpenTitan SoC using an ECO flow
to fix hold timing with degrading the FMAX●

Temperature Sensor generator is using an end-to-end
Open Source flow

●Updates to the D-LDO generator:●●

https://efabless.com/projects/239
https://github.com/msaligane/caravan_openfasoc.git○○○OpenTitan SoC includes
16KB, 4 T-sensors andpowered by D-LDO

Embedded voltage references
Decap cells using MIM cap.
Multiple implementations and ILOAD
Test-chip in MPW-II

35

OpenFASOC on MPW-II: D-LDO generator●●

Aux cells are swapped to experimentwith different switch structures
Multi-gain feedback loop is
implemented

36

OpenFASOC on MPW-II:
OpenTitan Root of Trust●

1st SoC using AMS components●The Opentitan SoC contains○ UART, SPI interfaces○ 16KB of SRAM (OpenRAM)○ D-LDO is used to power-up all the blocks○ All Peripherals are connected through Tilelink●Timing has been carefully checked and an ECO flow has beenused to avoid altering the FMAX while fixing hold violations

Power connections
between LDO andOpenTitan are done
ManuallyOpenTitan RoT SoC - Die Photo37

On-Going Projects & Contributions

Open-Source IC & tapeouts➔ 1st Open Silicon Results

NIST Nanofabrication Accelerator➔ 1st Open Nanotechnology Platform➔ Cryogenic Enablement & Design

Low-Power IC Design➔ Rapid Prototyping for Wearables

Hardware Security➔ 1st Open Root of Trust SoC

Automated & Open Nanotechnology Platform●

Partnership with NIST:○○○

Re-characterization of SKY130 with wide range
temperatures including cryogenic (4K)
Automated test structures Generators
Nanofabrication Accelerator Platform

39

Automated & Open Nanotechnology Platform
CMOS Integration Critical for Measurements●New devices and materials are continually
proposed by the academic community

Resistive switching Phase Change Memory(PCM)
memory (ReRAM)

2D Materials

Spin Torque Transfer(STT - RAM)

Conductive Bridge(CB-RAM)

Nanotubes

Source: Brian Hoskins, NIST

Reliable monolithic integration isa requirement for experimental
prototyping

Automated & Open Nanotechnology Platform
The Concept

Monolithic Integration drastically reduces parasitics and leads to improved measurement quality and test ranges.

41

Automated & Open Nanotechnology Platform
Realization of Enhanced Parametric Test

100~1000x Less Parasitics→ Improved Signal Fidelity

Traditional Method

This Project

The aim of this project is to put part of the test apparatus on a silicon chip, which will be used as the carrier wafer for newnano device fabrication. Drastically reduced parasitics can lead to improved measurement quality and test ranges.
42Overview of Cryogenic Test Structures

43

OpenFASOC is Evolving
New tools and Python-based APIs
OpenFASOC v0.0

https://github.com/idea-fasoc/OpenFASOC

44

OpenFASOC is Evolving
New tools and Python-based APIs
OpenFASOC v0.0

https://github.com/idea-fasoc/OpenFASOC

45

Interleaved Placement in OpenROAD
OpenFASOC v0.0

Fully Automated Interleaved Ring-Oscillator VCO, with custom placement scripts

Platform: Sky130hd
Inverter array: 12 x 12●

https://github.com/idea-fasoc/OpenFASOC

Uses DEF manipulation using Python but could
be integrated within OpenROAD

46

OpenFASOC is Evolving
New tools and Python-based APIs
OpenFASOC v0.0

OpenFASOC v1.0

Fast Generation of all other ROstructures
HD HS HVL
(By Skywater)
HS(12T) LS(12T) MS(12T),HS(15T) LS(15T) MS(15T),
HS(18T) LS(18T) MS(18T)...
(Other Libs)

https://github.com/idea-fasoc/OpenFASOC

47

Automated custom structures
GDSfactory48

MIM Cap Generation using Gdsfactory
GDSFACTORY Array creation routine
GDSFACTORY Mesh creation routine

Inputs:Multiplicity a,bOffsets x,ym

Inputs:Mesh dimension n,mMesh pitch x,yMesh layers

ynxgf.path()
gf.add_ref()gf.move()gf.move()gf.add_ref()49

Example - Array of Flying MiM caps + Custom Padring
GDSFACTORY Pad-ring place & route routine
Inputs:
Pad ring array spec
Connection definitions (semi-custom)

gf.move() gf.add_ref()* Through Array creation routine

50

MIM Cap Generation using Gdsfactory● Computes the grid and places capacitor on grid
● Generates connecting metals (with minimum metal spacing)● Replicates and connects the structures to pads

51

OpenFASOC is Evolving
New tools and Python-based APIs

OpenFASOC - latest

https://github.com/idea-fasoc/OpenFASOC

52

OpenFASOC is Evolving
New tools and Python-based APIs
OpenFASOC v0.0

OpenFASOC v1.0

https://github.com/idea-fasoc/OpenFASOC

OpenFASOC - latest

53

Resultant Test Die
MPW-5

https://github.com/msaligane/openfasoc_cryo_caravel54

4 Tapeouts Already! Final Tapeout Loading…

MPW-5

MPW-6

MPW-7

MPW-855

●Lowering Barrier to Chip Design

Enabling Open Collaboration and other Research communities

Source: Brian Hoskins, NIST

56

Performance / Complexity Tradeoff●FASoC augments digital flow with APR tool placement/routing constraints andminimizes the (performance loss * complexity)

Automation andFull control overP&R tools
reduce complexity

Generator with a Higher Control/Precision● Addresses porting Aux-cells
to new PDK● Programmatic layout provide
fine control with automation

Auto-Generated Comparator Cell

Generator with a Higher Control/Precision●●●●Object oriented code provides flexibility
PDK -> py class
Generators -> py function
User codes hardware by importing py packages

Parameter Variation

Integration with GDSfactory & OpenROAD
OpenFASOC withGDSFactory Generator APIPython PDKGenerator

Technology Layers# function interface@gf.cell
def top(args, PDK):…
return top

PDK.get_layer()

DRC Rule Deck

Imports

User Created PY Script
import [PDK]
import openfasoc.[Generator]
cell = [Generator].top(args,PDK)
cell.write_gds()

e.g Voltage Header Cell

Component Lib

PDK.get_component()

Integrating Cells
1.
2.

Defined cell placement
Auto routeOn-Going Projects & Contributions

Open-Source IC & tapeouts➔ 1st Open Silicon Results

NIST Nanofabrication Accelerator➔ 1st Open Nanotechnology Platform➔ Cryogenic Enablement & DesignLow-Power IC Design➔ Rapid Prototyping for Wearables

Hardware Security➔ 1st Open Root of Trust SoC

Control Electronics for Quantum Computers

62

Requirement of Low Operating Power

Source: Brian Hoskins, NIST63

Open Cryogenic CMOS

Automated PMU for Low-K Operation
Measurement Results

Maximum Eff. Point

Robust against Temperature Variation

Cryogenic Test Setup

Experiments have shown
constant behavior across awide temperature range, down
to cryogenic temperatures.
Power Efficiency & Output Voltage
Versus Load Current, Clock Freq., and Temperature

Emulated Closed-Loop Response
At Maximum-Power Tracking