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Hybrid Bonding Plays StarringRole in 3D Chips
Tech makes millions ofconnections in a square
millimeter of silicon
SAMUEL K. MOORE
04 JUN 2024
7 MIN READ
Samuel K. Moore is IEEE Spectrum’s semiconductor editor.

Imec managed to make 3D connections between chips placed once every 2 micrometers.
IMEC

3D CHIPS HYBRID BONDING SYSTEM TECHNOLOGY COOPTIMIZATION MOORESLAW ADVANCED PACKAGING

Researchers at the IEEE Electronic Components and Technology Conference(ECTC) last week pushed the state of the art in a technology that isbecoming critical to cutting-edge processors and memory. Called
hybrid bonding, the technology stacks two or more chips atop
each other in the same package, allowing chipmakers to increase
the number of transistors in their processors and memories despite
a general slowdown in the pace of the traditional transistor shrinking
that once defined Moore’s Law. Research groups from majorchipmakers and universities demonstrated a variety of hard-foughtimprovements, with a few—including from Applied Materials, Imec, Intel,and Sony—showing results that could lead to a record density ofconnections between 3D stacked chips of around 7 million links in asquare millimeter of silicon.
All those connections are needed because of the new nature of
progress in semiconductors, Intel’s Yi Shi told engineers at ECTC.
As Intel general manager of technology development Ann
Kelleher explained to IEEE Spectrum in 2022, Moore’s Law is now
governed by a concept called system technology co-optimization,
or STCO. In STCO, a chip’s functions, such as cache memory,
input/output, and logic are separated out and made using the best
manufacturing technology for each. Hybrid bonding and otheradvanced packaging tech can then reassemble them so that theywork like a single piece of silicon. But that can only happen with ahigh density of connections that can shuttle bits between pieces ofsilicon with little delay or energy consumption.
Hybrid bonding is not the only advanced packaging technology inuse, but it provides the highest density of vertical connections.
And it dominated ECTC, making up about one-fifth of theresearch presented, according to Chris Scanlan, senior vice president oftechnology at Besi, whose tools were behind several of thebreakthroughs.

“It’s difficult to say what will be the limit.
Things are moving very fast.”—JEAN-CHARLES SOURIAU, CEA LETI

In hybrid bonding, copper pads are constructed at the top face ofeach chip. The copper is surrounded by insulation, usually siliconoxide, and the pads themselves are slightly recessed from thesurface of the insulation. After the oxide is chemically modified,
the two chips are then pressed together face-to-face, so therecessed pads align with each. This sandwich is then slowly
heated, causing the copper to expand across the gap, connecting
the two chips.
Hybrid bonding can either attach individual chips of one size to awafer full of chips of a larger size or used to bond two full wafersof chips of the same size together. Thanks in part to its use incamera chips, the latter is a more mature process than the former.
Imec, for example, reported some of the most dense wafer-on-wafer (WoW)
bonds ever with a bond-to-bond distance (or pitch) of just 400

nanometers. The same research center managed a 2-micrometer
pitch for the chip-on-wafer (CoW) scenario. (Commercial chips
today have connections about 9 μm apart.)Hybrid bonding starts by forming recessed copper pads at the top of the chip [top]. The
surrounding oxide dielectric bonds when the two chips are pressed together [middle]. Annealing
expands the copper to form a conductive connection [bottom].

“With the equipment available, it’s easier to align wafer to wafer
than chip to wafer. Most processes for microelectronics are madefor [full] wafers,” says Jean-Charles Souriau, scientific leader in
integration and packaging at the French research organization,
CEA Leti. However, it’s chip-on-wafer (or die-to-wafer) that’s
making a splash in high-end processors such as AMD’s Epyc line,
where the technique is used to assemble compute cores and cachememory in its advanced CPUs and AI accelerators.
In pushing for tighter and tighter pitches for both scenarios,
researchers focused on making surfaces fractionally flatter, gettingbound wafers to stick together better, and cutting the time andcomplexity of the whole process. Getting it right could ultimately
mean enabling a revolution in how chips are designed.

WoW, those are some tight pitches
The wafer-on-wafer (WoW) research that reported the tightest

pitches—500 nm to 360 nm—all spent a lot of effort on one thing:flatness. To bind two wafers together with 100-nm-level accuracy,
the whole wafer has to be nearly perfectly flat. If it’s bowed orwarped, whole sections of the materials won’t connect.

Flattening wafers is the job of a process called chemicalmechanical planarization, or CMP. It’s key to chipmaking
generally, especially for the parts of the process that produce thelayers of interconnects above the transistors.
“CMP is a key parameter we have to control for hybrid bonding,”says Souriau. Results presented this week at ECTC took CMP toanother level, not just flattening across the wafer but reducing
mere nanometers of roundness on the insulation between thecopper pads to ensure better connections.
Other research focused on ensuring those flattened parts stuck
together strongly enough by experimenting with different surface
materials such as silicon carbonitride instead of silicon oxide or byusing different schemes to chemically activate the surface.
Initially, when wafers or dies are pressed together, they are held inplace with relatively weak hydrogen bonds, and the concern isensuring that everything stays in place between the bonding andfurther steps. Bound wafers and chips are then heated slowly (aprocess called annealing) to form stronger chemical bonds. Justhow strong these bonds are—and how to even figure that out—
was the subject of a lot of research at ECTC.
Part of that final bond strength would come from the copper
connections as well. The annealing step expands the copper acrossthe gap to form a conductive bridge. Controlling the size of that
gap is key, explained Samsung’s Seung Ho Hahn. Too much of a gap
and the copper won’t connect. Too little and it will push thewafers apart. It’s a matter of nanometers, and Hahn reported
research on a new chemical process that hopes to get it just rightby etching away the copper a single atomic layer at a time.
The quality of the connection counts, too. Even after the copper
expands, most schemes showed that the metal’s grain boundaries
don’t cross from one side to another. Such a crossing reduces aconnection’s electrical resistance and should boost its reliability.
Researchers at Tohoku University in Japan reported a newmetallurgical scheme that could finally generate large, single
grains of copper that cross the boundary. “This is a drasticchange,” said Takafumi Fukushima, an associate professor atTohoku University. “We are now analyzing what underlies it.”“I think it’s possible to make more than 20layer stack using this technology.”—HYEONMIN LEE,SAMSUNG

Other experiments focused on streamlining the hybrid bonding
process. Several sought to reduce the annealing temperatureneeded to form bonds—typically around 300 °C—motivated by
the potential to reduce any risk of damage to the chips from theprolonged heating. And researchers from Applied Materials presented
progress on a method to radically reduce the time needed forannealing—from hours to just 5 minutes.

CoWs that are outstanding in thefield

Chip-on-wafer (CoW) hybrid bonding is more useful to industry at
the moment: It allows chipmakers to stack chiplets of different
sizes together, and to test each chip before it’s bound to another,ensuring that they aren’t fatally dooming an expensive CPU with asingle flawed part.

But CoW comes with all of the difficulties of WoW and fewer ofthe options to alleviate them. For example, CMP is designed toflatten wafers, not individual dies. Once dies have been cut fromtheir source wafer and tested, there’s less that can be done toimprove their readiness for bonding.
Nevertheless, Intel reported CoW hybrid bonds with a 3-μm pitch,and Imec managed 2 μm, largely by making the transferred diesvery flat while they were still attached to the wafer and keeping
them extra clean going forward. Efforts by both groups used
plasma etching to dice up the dies instead of the usual method,which uses a specialized blade. Plasma won’t lead to chipping at
the edges, which creates debris that interferes with connections. It
also allowed the Imec group to shape the die, making chamferedcorners that relieved mechanical stress that could break connections.

CoW hybrid bonding is going to be critical to the future of highbandwidth memory (HBM), several researchers told IEEESpectrum. HBM is a stack of DRAM dies atop a control logic chip—currently 8 to 12 dies high. Often placed within the same package
as high-end GPUs, HBM is crucial to providing the tsunami of data

needed to run large language models like ChatGPT. Today, HBM dies arestacked using so-called microbump technology, in which tiny ballsof solder between each layer are surrounded by an organic filler.
But with AI pushing memory demand even higher, DRAM
makers want to do 20 layers or more in HBM chips. However, thevolume microbumps take up mean that these stacks will soon be
too tall to fit in the package with GPUs. Hybrid bonding would
not just shrink the height of HBMs, it should also make it easier toremove excess heat from the package, because there is lessthermal resistance between its layers.

A 200-nanometer WoW pitch is not justpossible, but desirable.
At ECTC, Samsung engineers showed that a hybrid bonding
scheme could make a 16-layer HBM stack. “I think it’s possible to
make more than 20-layer stack using this technology,” said Hyeonmin
Lee, a senior engineer at Samsung.

Other new CoW technology could help bring hybrid bonding tohigh-bandwidth memory. Though they didn’t present research on

this at ECTC, researchers at CEA Leti are working on so-called selfalignment technology, says Souriau. That would help ensure CoW
connections using chemical processes. Some parts of each surface
would be made hydrophobic and some hydrophilic, resulting insurfaces that would slide into place automatically.
At ECTC, researchers at Tohoku University andYamaha Robotics reported work on a similar scheme, using thesurface tension of water to align 5-μm pads on experimental
DRAM chips with better than 50-nm accuracy.

How far can hybrid bonding go?

Researchers will almost certainly keep pushing the pitch of hybrid
bonding connections. A 200-nm WoW pitch is not just possible
but desirable, Han-Jong Chia, a program manager pathfinding systems
at Taiwan Semiconductor Manufacturing Co., told engineers atECTC. Within two years, TSMC plans to introduce a technology
called backside power delivery. (Intel plans it for the end of this year.) That’s
a technology that puts the chip’s chunky power-delivery
interconnects beneath the silicon instead of above it. With thoseout of the way, the uppermost interconnect levels can connect
better to smaller hybrid bonding bond pads, TSMC researchers
calculate. Back side power delivery with 200-nm bond pads would
cut down the capacitance of 3D connections so much that theproduct of energy efficiency and signal delay would be as much asnine times as high as what can be achieved with 400-nm bondpads.
At some point in the future, if bond pitches are narrowed evenfurther, Chia suggested, it might become practical to “fold” blocks
of circuitry so they are built across two wafers. That way some of
the longer connections within the block might be made shorter by
the vertical pathway, potentially speeding computations andlowering power consumption.
And hybrid bonding may not be limited to silicon. “Today there isa lot of development in silicon-to-silicon wafers, but we are also
looking to do hybrid bonding between gallium nitride and siliconwafers and glass wafers…everything on everything,” says CEA
Leti’s Souriau. His organization even presented research on hybrid

bonding for quantum-computing chips, which involves aligningand binding superconducting niobium instead of copper.
“It’s difficult to say what will be the limit,” Souriau says. “Thingsare moving very fast.”•A Peek at Intel’s Future Foundry Tech ›•3 Ways 3D Chip Tech Is Upending Computing ›•Hybrid Bonding ›Samuel K. Moore
is the senior editor at IEEE Spectrum in charge of semiconductors
coverage. See full bio →PUBLISH
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Gilles S C Lamant

6J U N ,2 0 2 4

You seem to imply that annealing creates matter (copper).....