2019 Silicon Nanoelectronics Workshop
June 9 – 10, 2019
Rihga Royal Hotel Kyoto, Kyoto, Japan
Table of contents
Sunday, June 9, 2019
8:30
Opening Remarks
Takahiro Shinada, Tohoku University
Session 1: Plenary
Session Chair: Takahiro Shinada, Tohoku University
8:40 1-1 [Plenary] Atomic qubits in siliconMichelle Y. Simmons
University of New South Wales
9:10 1-2 [Plenary] Ultra-Low Power Brain-Inspired Processors and Neuromorphic
Processors with CMOS/MTJ Hybrid technology
Tetsuo EndohTohoku University
Session 2: Ge Devices and Integration Technologies
Session Chair: Byung-Gook Park, Seoul National University
9:402-1
The GAAFETs with Five Stacked Ge Nano-sheets Made by 2D Ge/Si Multilayer
Epitaxy, Excellent Selective Etching, and Conformal Monolayer Doping
Chun-Lin Chu1, Guang-Li Luo1, Kehuey Wu1, Shih-Hong Chen1, Chien-Chung Hsu2, BoYuan Chen1, Kun-Lin Lin1, Wen-Fa Wu1, Wen-Kuan Yeh1
1Taiwan Semiconductor Research Institute, 2National Tsing Hua University
10:00 2-2
Study of Twin Ge FinFET Structure Non-volatile Memory
Chien Chang Li1, Mu Shih Yeh2, Yao Jen Lee2, Yung Chun Wu1
1National Tsing Hua University, 2Taiwan Semiconductor Research Institute10:20 2-3
Germanium Layer Transfer with Low Temperature Direct Bonding and Epitaxial
Lift-off Technique for Ge-based monolithic 3D integration
Tatsuro Maeda, Hiroyuki Ishii, Wen Hsin Chang, Toshifumi Irisawa, Yuichi Kurashima,
Hideki Takagi, Noriyuki Uchida
National Institute of Advanced Science and Technology

10:40

BreakSession 3: Neural Systems, New Computing and Modeling
Session Chair: Takahide Oya, Yokohama National University
11:00 3-1
[Invited] Temporal feature analysis in brain-inspired neural systems
Tomoki Fukai1,2 and Toshitake Asabuki31Okinawa Institute of Science and Technology, 2RIKEN, 3The University of Tokyo11:30 3-2
An Improved Hardware Acceleration Architecture of Binary Neural Network with
1T1R Array Based Forward/Backward Propagation Module
Yizhou Zhang, Zheng Zhou, Peng Huang, Mengqi Fan, Runze Han, Wensheng Shen,Lifeng Liu, Xiaoyan Liu, Jinfeng Kang
Peking University
11:50 3-3
A Parallel Bitstream Generator for Stochastic Computing
Yawen Zhang, Runsheng Wang, Xinyue Zhang, Zherui Zhang, Jiahao Song, ZuodongZhang, Yuan Wang, Ru Huang
Peking University
12:10 3-4
New-Generation Design-Technology Co-Optimization (DTCO): Machine-Learning
Assisted Modeling FrameworkZhe Zhang1, Runsheng Wang1, Cheng Chen1, Qianqian Huang1, Yangyuan Wang1,Cheng Hu2, Dehuang Wu2, Joddy Wang2, Yangyuan Wang1
1Peking University, 2Synopsys
12:30

Lunch

Session 4: Energy Efficient Electronics and Memory
Session Chair: Steve Chung, National Chiao Tung University
14:00 4-1
[Invited] Energy Efficient Nanoelectronics
An Chen
IBM Research
14:30 4-2
Characterization of Chalcogenide Selectors for Crossbar Switch Used in Nonvolatile
FPGA
Hideaki Numata1, Naoki Banno1, Koichiro Okamoto1, Noriyuki Iguchi1, Hiromitsu
Hada1, Masanori Hashimoto2, Tadahiko Sugibayashi1, Toshitsugu Sakamoto1,Munehiro Tada1
1NEC Corp, 2Osaka University
14:50 4-3
Switching Current of Ta2O5 Based Resistive Analog Memories
Yuanlin Li1, Atsushi Tsurumaki-Fukuchi1, Masashi Arita1, Yasuo Takahashi1, Takashi
Morie2

1Hokkaido University, 2Kyushu Institute of Technology

15:10

15:30

4-4

Application of Extreme Value Theory to Statistical Analyses of Worst Case SRAM
Data Retention Voltage
Tomoko Mizutani, Kiyoshi Takeuchi, Takuya Saraya, Masaharu Kobayashi, Toshiro
Hiramoto
The University of Tokyo
BreakSession 5: 3D NAND
Session Chair: Jiezhi Chen, Shangdong University
15:45 5-1
Effect of Device Scaling on Lateral Migration Mechanism of Electrons in V-NAND
Changbeom Woo, Shinkeun Kim, Jaeyeol Park, Hyungcheol ShinSeoul National University
16:05 5-2Error Correction for Read-hot Data in 3D-TLC NAND Flash by Read-disturb Modeled
Artificial Neural Network Coupled LDPC ECC
Daiki Kojima, Toshiki Nakamura, Ken Takeuchi
University of Chuo
16:25 5-3
Less Reliable Page Error Reduction for 3D-TLC NAND Flash Memories with Data
Overhead Reduction by 40% and Data-retention Time Increase by 5.0x
Kyosuke Maeda, Kyoji Mizoguchi, Ken Takeuchi
University of Chuo
Session 6: Posters
16:45-18:30
Session Co-Chairs: Katsuhiro Tomioka, Hokkaido University, Toshifumi Irisawa, AIST
16:45
Short oral presentation (1 min each)
6-1
Impacts of Remote Coulomb Scattering on Hole Mobility in Si p-MOSFFETs at
Cryogenic Temperatures
Xianle le Zhang, Pengying Chang, Gang Du, Xiaoyan Liu
Institute of Microelectronics, Peking University
6-2
Structural Design of T-gate, Air-spacer Poly-Si TFTs for RF applications
Yu-An Huang, Yu-Hsiang Yeh, Horng-Chih Lin, Pei-Wen Li
National Chiao Tung University
6-3Short-channel Effects and Sub-Surface Behavior in Bulk MOSFETs and Nanoscale
DG-SOI- MOSFETs: A TCAD Investigation
Aditya Sankar Medury, Harshit Kansal
Indian Institute of Science Education and Research Bhopal

6-4

6-5

6-6

6-7

6-8

6-9

6-10

6-11

6-12

Investigation of Ferroelectric Granularity for Double-Gate Negative-Capacitance
FETs Considering Position and Number Fluctuations
Che-Lun Fan, Kuei-Yang Tseng, You-Sheng Liu, Pin Su
National Chiao Tung University
Characterization and Analysis of 5 nm-thick Hf0.5Zr0.5O2 for Negative Capacitance
FinFETPin-Jui Chen1, Meng-Ju Tsai1, Fu-Ju Hou2, Yung-Chun Wu1
1National Tsing Hua University, 2Taiwan Semiconductor Research Institute
Reduced RTN Amplitude and Single Trap induced Variation for Ferroelectric FinFETby Substrate Doping Optimization
Zih-Tang Lin, Vita Pi-Ho Hu
University of National Central
Negative Capacitance in Short-Channel Tunnel Field-Effect Transistors Hung-Jin
Teng1,2, Yu-Hsuan Chen1,2, Nguyen Dang Chien3, Chun-Hsing Shih1
1National Chi Nan University, 2National Tsing Hua University, 3Dalat University
Elastic Response of 10-nm Insulator Films Measured by Dynamic Indentation forNano-scale Electron Device Fabrication
Leonid Bolotov, Noriyuki Uchida, Wen Hsin Chang, Tatsuro Maeda, Shinji Migita
National Institute of Advanced Industrial Science and Technology
ON Current Enhancement by Gate Controlled Strain in The InAs n-Type
Piezoelectric Tunnel FETs
Yuxiong Long1, Jun Z Huang2, Zhongming Wei1, Jun-Wei Luo1, Xiangwei Jiang1
1Institute of Semiconductors, CAS, 2MaxLinear Inc.
Ge Condensation Process for High ON/OFF Ratio of SiGe Gate-All-Around
Nanowire Tunnel Field-Effect Transistor
Ryoongbin Lee1, Junil Lee1, Sangwan Kim2, Kitae Lee1, Sihyun Kim1, Soyoun Kim1,Yunho Choi1, Byung-Gook Park1
1Seoul National University, 2Ajou University
Effect of Fluorine Incorporation with HfO2/Ti-GeOx gate stack on p-Germanium
Substrate through CF4 plasma treatment
Yi He Tsai1, Chen Han Chou1, Wen Kuan Yeh2, Yu Hsien Lin3, Fu Hsiang Ko1, Chao Hsin
Chien1
1University of National Chiao Tung, 2Institute of Taiwan Semiconductor Research,
3University of National United
Feasibility of Ge double quantum dots with high symmetry and tunability in size
and inter-dot spacing
Kang-Ping Peng, Tsung-Lin Huang, Thomas George, Horng-Chih Lin, Pei-WEN Li LiNational Chiao Tung University6-13

6-14

6-15

6-16

6-17

6-18

6-19

6-20

6-21

The Preliminary Investigation of Octrafluorocyclobutane Plasma Jet Etching ofCrystalline Silicon
Chun Huang, Wei-Ting Liu, Wei-Lun Li, Li-Ko Huang, Yi-An Chen
Yuan Ze University
Metallic Source/Drain Ge-Based Charge-Trapping Memory Cells
Yu-Hsuan Chen1,2, Chun-Hsing Shih1, Hung-Jin Teng1,2, Chenhsin Lien2
1National Chi Nan University, 2National Tsing Hua University
Modeling of Lateral Migration Mechanism of Holes in 3D NAND Flash MemoryCharge Trap Layer during Retention OperationJaeyeol park, Hyungcheol ShinSeoul National University
Prediction of Characteristics of Future Scaled 3D NAND Flash Memory by Using
TCAD and SPICE
Minsoo Kim, Hyungcheol ShinSeoul National University
Improved Gradual Reset Phenomenon in SiNx-based RRAM by Diode-Connected
Structure
Min-Hwi Kim1, Suhyun Bang1, Tae-Hyeon Kim1, Dong Keun Lee1, Sungjun Kim2,Seongjae Cho3, Byung-Gook Park1
1Seoul National University, 2Chungbuk National University, 3Gachon University
Effect of TiO Film Thickness on Resistive Switching Behavior of TiN/TiOx/HfO2/Pt
RRAM Device
Xiangxiang Ding, Lifeng Liu, Yulin Feng, Peng Huang
Peking University
Comparison of switching characteristics of HfOx RRAM device with different
switching layer thicknesses
Dong Keun Lee1, Min-Hwi Kim1, Suhyun Bang1, Tae-Hyeon Kim1, Yeon-Joon Choi1,Sungjun Kim2, Seongjae Cho3, Byung-Gook Park1
1Seoul National University, 2Chungbuk National University, 3Gachon University
Charge Effects on Semiconductor-Metal Phase Transition in Mono-layer MoTe2
Jixuan Wu1,2, Xiaolei Ma1,2, Jiezhi Chen1, Xiangwei Jiang2
1Shandong University, 2Chinese Academy of Science
Design of learning circuit for single-electron neural networks
Masaki Ueno, Takahide Oya
Yokohama National University

6-22

6-23

6-24

6-25

6-26

6-27

6-28

Thermal-noise-harnessing single-electron memory pair circuit and its application
to full adder circuit with simple structure
Risa Kaide, Takahide Oya
Yokohama National University
Design of multi-layer single-electron information-processing circuit mimicking
behavior of bubble film for solving nonlinear problem
Nobuhiko Kurata, Takahide Oya
Yokohama National University
Single-electron Information-processing Circuit Mimicking Behavior of Fish Shoals
Hideto Yamashita, Takahide Oya
Yokohama National UniversityA Systematic Model Parameter Extraction using Differential Evolution SearchingJeesoo Chang, Min-Hye Oh1, Byung-Gook Park
Seoul National University
Resonant Photocurrent at 1550 nm in an Erbium Low-Doped Silicon Transistor at
Room Temperature
Enrico Prati1, Michele Celebrano2, Lavinia Ghirardini2, Marco Finazzi2, Giorgio
Ferrari2, Takahiro Shinada3, Keinan Gi4, Yuki Chiba4, Ayman Abdelghafar4, Maasa
Yano4, Takashi Tanii4
1Consiglio Nazionale delle Ricerche, 2Politecnico di Milano, 3Tohoku University,4Waseda University
Evaluation of Photosensitive Performance of Different Structured UTBB MOSFET
Liqiao Liu, Xiaoyan Liu, Gang Du
Peking University
Potential of Nano-scale Optical Rotor Based on a pn-Junction Wire Yasuhisa Omura
Kansai University

Monday, June 10, 2019
Session 7: 2D materials
Session Chair: Iuliana Radu, IMEC
8:30
7-1
[Invited] 3D Heterogeneous Integration with 2D Materials
Eric Pop, Connor McClellan, Connor Bailey, Isha Datye, Alexander Gabourie, RyanGrady, Kirstin Schauble, and Sam Vaziri
Stanford University
9:00
7-2
Comparative study of high-k dielectric on MoS2 deposited by plasma enhanced
ALDWenhsin Chang1, Naoya Okada1, Hidehiro Asai1, Koichi Fukuda1, Mitsuhiro Okada1,Takahiko Endo2, Yasumitsu Miyata2, Toshifumi Irisawa1
1National Institute of Advanced Science and Technology, 2Tokyo Metropolitan
University
9:20
7-3
Atomistic Study of Transport Characteristics in Sub-1nm Ultra-narrow
Molybdenum Disulfide (MoS2) Nanoribbon Field Effect Transistors
Fei Wang1,2, Xiaolei Ma1,2, Jixuan Wu1,2, Jiezhi Chen1, Xiangwei Jiang2
1Shandong University, 2Chinese Academy of Science
9:40
7-4
Subthreshold Degradation of 2D material Junctionless FETs -Impact of Fringe Field
from Source/Drain Electrodes through InsulatorHidehiro Asai, Wen Hsin Chang, Naoya Okada, Koichi Fukuda, Toshifumi Irisawa
National Institute of Advanced Industrial Science and Technology
10:00

BreakSession 8: Ferroelectric FETs
Session Chair: Masaharu Kobayashi, The University of Tokyo
10:20 8-1
Experimental Demonstration of Performance Enhancement of MFMIS and MFIS
for 5-nm × 12.5-nm Poly-Si Nanowire Gate-All-Around Negative Capacitance FETs
Featuring Seed-Layer and PMA-Free ProcessShen-Yang Lee, Han-Wei Chen, Chiuan-Huei Shen, Po-Yi Kuo, Chun-Chih Chung, YuEn Huang, Hsin-Yu Chen, Tien-Sheng Chao
National Chiao Tung University
10:40 8-2
Study of Germanium Nanosheet Channel with Negative Capacitance Field-EffectTransistor
Yu Ning Chen1, Fu Ju Hou2, Chun Jung Su2, Yung Chun Wu1
1National Tsing Hua Univerty, 2Taiwan Semiconductor Research Institute11:00 8-3
Atomic-level Analysis by Synchrotron Radiation and Characterization of 2 nm, 3nm, and 5 nm-thick Hf0.5Zr0.5O2 Negative Capacitance FinFET11:20

8-4

11:40

8-5

12:00

Meng-Ju Tsai1, Pin-Jui Chen1, Po-Yang Peng2, Fu-Ju Hou3, Yung-Chun Wu1
1National Tsing Hua University, 2National Synchrotron Radiation Research Center,3Taiwan Semiconductor Research Institute
The Understanding of Gate Capacitance Matching on Achieving a High
Performance NC MOSFET with Sufficient Mobility
C. K. Chiang1, P. Hsuan1, Y. C. Luo1, F. L. Li2, E. R. Hsieh1, C. H. Liu2, Steve Chung1
1National Chiao Tung University, 2National Taiwan Normal University
Evaluation of Analog Circuit Performance for Ferroelectric SOI MOSFETs
considering Interface Trap Charges and Gate Length Variations
Yi-Chun Lu, Vita Pi-Ho Hu
University of National CentralLunch

Session 9: Quantum Computing and Quantum Dots
Session Chair: Louis Hutin, Leti
13:30 9-1
[Invited] Moving Spins from Lab to Fab: A Silicon-Based Platform for Quantum
Computing Device Technologies
Bogdan Govoreanu
IMEC
14:00 9-2
Simultaneous operation of singlet-triplet qubitsFederico Fedele, Anasua Chatterjee, Ferdinand Kuemmeth
University of Copenhagen
14:20 9-3
Characterization of top-gated Si/SiGe devices for spin qubit applications
Fabio Ansaloni, Christian Volk, Anasua Chatterjee, Ferdinand Kuemmeth
University of Copenhagen
14:40 9-4
Dopant-Induced Terahertz Resonance of a Dopant-Rich Silicon Quantum Dot
Takuya Okamoto1,2, Naoki Fujimura1,2, Tetsuo Kodera2, Yukio Kawano1,2
1FIRST, Tokyo Institute of Technology, 2Dept. of E.E., Tokyo Institute of Technology
15:00 9-5
Si Surface Orientation Dependence of SiC Nano-Dot Formation in Hot-C Ion
Implanted Bulk-Si Substrate
Tomohisa Mizuno1, Masaki Yamamoto1, Takashi Aoki1, Toshiyuki Sameshima2
1Kanagawa University, 2Tokyo University of Agriculture and Technology
15:20

BreakSession 10: SOI-Based Novel Devices and RTN
Session Chair: Daniel Moraru, Shizuoka University
15:35 10-1 Si Electron Nano-Aspirator towards Emerging Hydro-Electronics
Manjakavahoaka Razanoelina1, Himma Firdaus2, Yasuo Takahashi3,Akira Fujiwara4, Yukinori Ono1,2
1Res. Inst. of Electronics, Shizuoka University, 2Graduate School of Sci.
and Tech., Shizuoka University, 3Hokkaido University, 4NTT Basic
Research Laboratory
15:55 10-2 Comparative Study on 1-THz Antenna-Coupled Bolometer with
Various SOI-CMOS based Temperature Sensors: MOSFET, Diode,
Resistor and Thermocouple
Durgadevi Elamaran1, Takeo Ueta2, Hiroaki Satoh2,3, Norihisa
Hiromoto1,2, Hiroshi Inokawa1,31Graduate School of Science and Technology, Shizuoka University,
2Graduated School of Integrated Science and Technology, Shizuoka
University, 3Research Institute of Electronics, Shizuoka University
16:15 10-3 Directivity of SOI Photodiode with Gold Surface Plasmon Antenna
Anitharaj Nagarajan1, Shusuke Hara1, Hiroaki Satoh1, Aruna Priya
Panchanathan2, Hiroshi Inokawa1
1Shizuoka University, 2SRMIST
16:35 10-4 Characterization of Four-Level Random Telegraph Noise in a Gate-AllAround Poly-Si Nanowire Transistor
You-Tai Chang, Pei-Wen Li, Horng-Chih LinNational Chiao Tung University
16:55 10-5 From Gate Oxide Characterization to TCAD Predictions: Exploring
Impact of Defects Across Technologies
Gerhard Rzepa, Franz Schanovsky, Markus Karner
Global TCAD Solutions GmbH
17:15

Closing Remarks