General Chair
Y. Takahashi
Hokkaido University
Tel: +81-11-706-6794
y-taka@nano.ist.hokudai.ac.jp
Program Chair
K. EndoAIST
Tel: +81-29-861-3857
endo.k@aist.go.jp
Program Committee
S. Chung (NCTU)
K. De Meyer (IMEC)
S. Goodnick (Arizona State Univ.)
T. Hiramoto (Univ. Tokyo)
R. Huang (Peking Univ.)
A. Ionescu (EPFL)
T. Irisawa (Toshiba)
R. Jammy (Intermolecular)
K. Kakushima (Tokyo Tech)
D. Kim (Samsung)
T. Krishnamohan (Intel)
M. C. Lemme (Univ. Siegen)
P.-W. Li (Nat. Central Univ.)
B. Mizuno (Panasonic)H. Mizuta (JAIST)
Y. Ono (Toyama Univ.)
B.-G. Park (Seoul Nat. Univ.)
W. Porod (Univ. Notre Dame)
T. Shinada (Tohoku Univ.)
M. Tabe (Shizuoka Univ.)
M. Takenaka (Univ. Tokyo)
K. Uchida (Keio Univ.)
Y. Uraoka (NAIST)
M. Vinet (Leti)
Y.-C Yeo (Nat. Univ. Singapore)
G. Xing (Univ. Notre Dame)
Secretary
T. Takahashi (Keio Univ.)

2015 Silicon Nanoelectronics Workshop
June 14-15, 2015, Rihga Royal Hotel Kyoto, Kyoto, Japan

20th Anniversary
2nd Call for Papers
Deadline for Abstracts: March 31, 2015
General Information
The 2015 Silicon Nanoelectronics Workshop will be held at Rihga Royal Hotel Kyoto,
Japan on June 14-15, 2015, just prior to VLSI Symposium on Technology as asatellite workshop of the VLSI Symposia. The workshop will focus on silicon-related
nanoelectronics to bridge a gap between the Si nano-technology and the "real" VLSI
world. The first Silicon Nanoelectronics Workshop was held in June, 1996 at
Honolulu, Hawaii, USA. The 2015 Silicon Nanoelectronics Workshop will be the 20thin a series of annual workshops.
ScopeThe workshop will cover various aspects of VLSI-related silicon nanoelectronics.
Areas of interest include, but are not limited to:- Sub-10 nm transistors employing conventional and novel architecture including
non-classical structures, novel channel and source/drain materials, non-thermal
injection mechanisms- Device physics of nanodevices including quantum effects, nonequilibrium andballistic transport- Modeling and simulation of nanoscale devices- Extreme processing of nanostructures, including nanopatterning- Junction and insulator materials and process technology for nanodevices- Nanoscale surface, interface, and heterojunction effects in nanodevices- Device scaling issues including doping fluctuations and atomic granularity- Novel architectures for nanodevices including quantum computing- Optoelectronics using silicon nanostructures- Devices for heterogeneous integration on silicon, including 2D materials, Ge andIII-V, CNT, spin-based devices, MEMS and NEMS, etc.
- Environmental devices which contributes to low-carbon society (wireless sensors,energy harvesters, steep slope devices, etc.)

Plenary SpeakerHyeong Soo Kim, SK Hynix. Topic: Future Memory Technology.
Invited Speaker
David K. Ferry, Arizona State University Topic: Fluctuations and Energy Relaxationin Graphene.
Enrico Prati, Consiglio Nazionale delle Ricerche. Topic: Atomic Scale Devices.
Kensuke Ota, Toshiba. Topic: Reliability in Nanodevices.
Andrew Dzurak, The University of New South Wales. Topic: Quantum Computing.
Submission of Abstract
Prospective authors are requested to submit a PDF file of the abstract ON-LINE at
http://annex.jsap.or.jp/snw/
The abstract must consist of one page of text and one page of figures. The abstract
must include the title, the author's names, affiliation, full address, phone and FAX
numbers, and e-mail address. Faxed copies of the abstract will not be accepted.
Accepted abstracts will be reproduced in the workbook exactly as received. The
deadline for abstracts is March 31, 2015.
Questions may be addressed to endo.k@aist.go.jp (K. Endo)
Special Events for celebrating 20th Anniversary
To be announced.
Further Information
Registration forms and hotel reservation forms will be provided in the Web site of the2015 VLSI Technology Symposium (http://www.vlsisymposium.org/). Some of theaccepted papers will be presented in "Poster Sessions". Further information can beobtained at http://annex.jsap.or.jp/snw/