VisualSim® Interface with FPGA –User Guide

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Revision HistoryThe following table shows the revision history for this document
DateFeb 20, 2015
Apr 7, 2015

Version
2.0
2.1

Revision12

Table of Contents
Revision History ............................................................................................................................................ 3
Introduction .................................................................................................................................................. 5
VisualSim FPGA Interface applications ......................................................................................................... 5
Hardware and Software Requirements ........................................................................................................ 6
VisualSim FPGA Interface Kit......................................................................................................................... 6How Interface Works .................................................................................................................................... 6
VisualSim Interface with Xilinx Zynq 7000 ................................................................................................ 6
Procedure to Run Example ....................................................................................................................... 6
Configuring FPGA and about Source Files................................................................................................. 8
Possible Errors......................................................................................................................................... 11

IntroductionVisualSim® is a system level modeling and simulation tool from Mirabilis Design for conducting
Architecture Exploration, power and Performance analysis of proposed or existing systems early in thedesign flow. This document explains how to use FPGA in loop with VisualSim®. Here we have considered
Xilinx Zynq 7000 platform board as the example device that communicates with VisualSim®, however
the source code and the setup is completely generic. This interface has been demonstrated on Xilinx
Zynq 7000 platform board (Zybo board), using the Vivado tool suite from Xilinx and the accompanyingXilinx SDK. The version of Xilinx tool used is Vivado 10.2.
Using this interface one can communicate with FPGA boards from the host computer and perform
processing using the data transferred from VisualSim on the target FPGA and also VisualSim can receive
processed data back from FPGA for further analysis.

Host Computer

FPGA Board

VisualSim FPGA Interface applications
VisualSim FPGA Interface can be used for System level analysis of Embedded Systems including
performance, protocol checking, power and for generating test scenarios for the target FPGA. VisualSim
can generate verities of test scenarios very quickly and enables the user to validate application on FPGA
covering all corner cases.
VisualSim FPGA interface allows user to adopt below mentioned applications but it is not restricted.
Generating and running system level scenarios
o VisualSim can be used to generate system level scenarios from the system definition.
o Transferring the data to the FPGA to run actual data through the systemo Transfer the data back to VisualSim to perform analysis and display the information inuser readable format
Run performance simulations on the actual hardware systemo VisualSim to generate complex use case scenarios that define performance bottle necks
o Run these scenarios on the actual hardware systemo Collect process and display the results, so system level optimizations can be performed
Run power scenarios on the actual hardware
o Generate complex power scenarios for the systemo Run these scenarios on the actual hardware

oCollect process and display the results, so system issues can be identified and fixed

Hardware and Software Requirements
VisualSim can communicate with FPGA’s having Micro-Controller/Processor, Ethernet port and FPGA
design software’s along with SDK. Example Hardware and Software’s are as follows; Xilinx Zynq 7000,SmartFusion2, Xilinx Vivado.

VisualSim FPGA Interface Kit
VisualSim FPGA Interface Kit provides all the interface files and demo examples. As VisualSim FPGAInterface Kit is provided as completely configurable user can compile the interface based on therequirements.

How Interface Works
VisualSim Interface with Xilinx Zynq 7000
The Zynq platform has an ARM processor and an FPGA as part of its architecture. This interface uses theARM processor to enable the interface, so the users can use all of the FPGA for their logic, except for asmall layer to communicate with the interface.
The software running on the ARM processor is a lwIP Echo Server. The lwIP Echo server application
starts an echo server at port 7. Any data sent to this port is consumed by the FPGA processed and sent
back through this interface.
By default, the program assigns the following settings to the board:
IP Address: 192.168.1.10
Netmask : 255.255.255.0
Gateway : 192.168.1.1
MAC address: 00:0a:35:00:01:02
These settings can be changed in the file main.c.
platform.c implements certain processor and platform dependent functions.
The file platform_config.h is generated based on the hardware design. It makes two assumptions: The
timer has its interrupt line connected to the interrupt controller, and all the ethernet peripherals(xps_ethernetlite or xps_ll_temac) accessible from the processor can be used with lwIP.

Procedure to Run ExampleImport the Vivado project into the Vivado tool suite
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Make the required changes to the project to suit the hardware being used for the demo.
Compile the project in Vivado
Launch the SDK from Vivado, so all the required board support packages are exported to theSDKImport the SDK project into the SDK
Make the required changes in the SDK to match the paths of the new packages that weregenerated for the board being used
Compile the software
Program the FPGA with the generated bit stream
Then launch the software to run on the FPGA and monitor using a telnet from the host PC

To communicate with FPGA, VisualSim uses UDP socket ports and the user can send packet data from
VisualSim to FPGA using VisualSim’s “Datagram Writer” library block and receives packet from FPGA
using “Datagram Reader” library block. Sample VisualSim model and configuration of Datagram Writerand Datagram Reader is shown in below figure.

Figure 1: VisualSim Model
VisualSim Datagram Writer and Datagram Reader play a very important role in VisualSim FPGA interface.
Datagram Writer and Datagram Reader should be configured with right Socket number andRemote/Local address.

Figure 2: Configuring Datagram Writer block

Figure 3: configuring Datagram Reader
The blocks connected after Datagram Reader corresponds to the subsystems that are connected toFPGA platform and does processing based on the data from FPGA. In this example we have connected aSmart Timed Resource that models a simple buffer and it service that data based on the incoming data
size and buffer speed MHz.

Configuring FPGA and about Source Files
We have created a sample Vivado project that works with VisualSim. Please import the Vivado project
into Xilinx Vivado tool suite. To Import the project, please click on File  Open Project and selectmirab_eth.xpr and click Ok. Now the project has been loaded into Vivado design suite.
Now we need to generate bit stream for programming FPGA. Click on Run Implementation from themenu bar Flow  Run Implementation or click on the green arrow button on the tool bar.

After successful Implementation Run generate bit stream by selecting Generate Bitstream Option asshown below

Figure 4: Generate Bitstream
After successful Bitstream generation, we need to export hardware description file for SDK. To perform
this, please click on File  Export Hardware. As the original project was compiled using Vivado 10.2,
users with latest version of Vivado needs to upgrade IP and generate a new block diagram. Please referappendix 1 for more details on updating IP and block diagram generation.
When you click on Export Hardware, Vivado Suite will as if you want to generate output products or toSkip generation of output products

Figure 5: Generate Output Products
Click on Generate output Products
After generating output products for hardware, select the export location as local to projectFigure 6: Export Hardware
Click on OK.
Now we need to launch Xilinx SDK, Please make sure that you have installed Xilinx SDK package during
installation procedure.
As we need all the board support packages in SDK, launch Xilinx SDK from Vivado Design suite. Click on
File  Launch SDK. This will open Xilinx SDK, Make the required changes in the SDK to match the pathsof the new packages that were generated for the board being used. By default you can select theexported location as Local to project as shown below

Figure 7: Launch SDK
Click on Ok.

The source files are listed under TestApp1, please select TestApp1 in Project Explorer as shown below.

To compile source file click on Run menu from the Menu bar or Run button on the Tool Bar.
Now program the FPGA with the generated bitstream by clicking on Tools  Program Device
Launch the software to run on the FPGA and monitor using a telnet from the host PC.

Possible Errors
1. Failed to create a new socket on port {Port Number}
Solution: This error appears if the Datagram Writer local socket number and Datagram Reader
local socket number are same. Please make sure that both are different
2. Blank Report display
Solution: This is due to incorrect remote address/IP address or Remote socket number definedin Datagram Writer.

Appendix
1. For the users with Vivado design suite above 10.2, please follow the steps mentioned below toupgrade IP and to generate new block diagram.
If you are running Vivado design suite above 10.2 you may receive a message as mentionedbelow while performing Export Hardware.

At this point click on Open Block Design from the flow navigator as shown below

Click on Show IP Status

Click on Update Selected

This will update the existing IP’s