Ⅱ-9. Instrumentation

RIKEN Accel. Prog. Rep. 49 (2016)

New functions in Generic Trigger Operator
H. Baba,∗1 T. Ichihara,∗1 T. Isobe,∗1 T. Ohnishi,∗1 K. Yoshida,∗1 Y. Watanabe,∗1 S. Ota,∗2 S. Shimoura,∗2
S. Takeuchi,∗3 and Y. Togano∗3The Generic Trigger Operator (GTO) module1) isa ﬁeld-programmable gate array (FPGA)-based NIM
logic module. Common trigger ﬁrmware2) manages
trigger generation to ensure event synchronization between multiple CAMAC and VME front-end systems.
GTO modules implementing this ﬁrmware are permanently installed at experiments of BigRIPS, SHARAQ,
EURICA, SUNFLOWER, SAMURAI, and R3. Recently, advanced functions of scaler, gate-and-delaygenerator (GG) and selector have been developed forGTO. Here, we report these new functions.
Scaler
The scaler function has been introduced in the GTO
module. Scaler values can be readout via the Ethernet.
The functionality of the scaler ﬁrmware is as follows.
• 20-channel scaler inputs : Each scaler has a 32-bit
counter depth.
• Gate input : When the gate input function is enabled, scaler circuits count up only when the gate
signal is issued.
• Veto input : Inhibit counting.
• Read latch input : The readout value is held by
the read latch signal. Scaler circuits are still operational even if the read latch is issued.
• Clear input : Clear the scaler values to zero.
As additional functions, 1-Hz/1-kHz/10-kHz clock signals and level/pulse signals can be output.
Gate-and-Delay Generator
The ﬁrmware of the 4-channel GG has been developed. Two diﬀerent GG functions are introduced:
clock-asynchronous and clock-synchronous GG. The
clock-asynchronous GG is based on the D-Flip Flopdelay chain (details are described in Ref. 1). The gate
and delay circuits are driven according to the leadingedge of the input signal. The clock-synchronous GG isimplemented by simply counting up the clock signal.
In this case, input signals are synchronized by the internal clock. The speciﬁcation of each GG function isdescribed bellow.

– Gate-width range : Twid = 51 ns to 2.6 ms.
– Delay range : Tdl = 51 ns to 2.6 ms.
– Minimum step of Twid and Tdl : 1.2 ns.
– Timing jitter : σ � Tdl × 10−4 .
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3XOVHFig. 1. Functional diagram of the selector firmware• clock-synchronous GG– Clock interval : Tint = 20 ns to 10 μs.
– Gate-width range : Twid = 20 ns to 171 s.
– Delay range : Tdl = 20 ns √to 171 s.
– Timing jitter : σ = Tint /2 3 .
In the case of the clock-synchronous GG, the clock signal is variable. The minimum clock interval (Tint ) is 20ns, which originates from a 50-MHz crystal resonator.
This clock can be divided into 1/1 to 1/256 frequency
in FPGA. Thus, the clock interval is varied between
20 ns and 10 μs. The timing jitter of the output signal in clock-synchronous GG depends on Tint because
deterministic jitter is generated when the input signal
is synchronized by the clock. On the other hand, thetiming jitter in clock-asynchronous GG is a random
jitter.
Selector
A selector ﬁrmware has been developed to remotely
switch signal sources. The functional diagram is shownin Fig. 1. There are 8 output channels. Each output channel can be chosen from signal sources by themultiplexer (MUX) circuit. The signal sources of the20 inputs, down scaler (DS), 1k/10k-Hz clock, pulse,
and level signals are available. Input signals and 50MHz clock signals can be decimated using the DS circuit: this function is the so-called rate divider or downscaler.
These new functions implemented as ﬁrmware areutilized in RIBF experiments. In addition, the development of the time-to-digital converter (TDC) in theGTO is examined. The details of the TDC ﬁrmwareare described in Ref 3.

• clock-asynchronous GG∗1,QSXWLQSXWVReferences
1) H. Baba et al.: RIKEN Acc. Prog. Rep. 46, 213 (2013).
2) H. Baba et al.: RIKEN Acc. Prog. Rep. 47, 235 (2014).
3) T. Yoshida et al.: In this report.

RIKEN Nishina Center
Center for Nuclear Study, University of Tokyo
Department of Physics, Tokyo Institute of Technology- 201 -