QSFP-DD Hardware Rev 5.0

QSFP-DD MSA
QSFP-DD Hardware Specificationfor
QSFP DOUBLE DENSITY 8X PLUGGABLE TRANSCEIVER
Rev 5.0

July 9, 2019

Abstract: This specification defines: the electrical and optical connectors, electricalsignals and power supplies, mechanical and thermal requirements of the pluggable QSFP
Double Density (QSFP-DD) module, connector and cage system. This document provides acommon specification for systems manufacturers, system integrators, and suppliers ofmodules.

POINTS OF CONTACT:Tom Palkert
Technical Editor
Molex
2222 Wellington Court
Lisle, IL 60532-1682
Ph: 952-200-8542
tom.palkert at molex.com

Mark Nowell
Co-Chair
Cisco
170 West Tasman Dr
San Jose, CA 95134
Ph: 613-254-3391
mnowell at cisco.com

Scott Sommers
Co-ChairMolex
2222 Wellington Court
Lisle, IL 60532-1682
Ph: 630-527-4317
scott.sommers at molex.com

www.qsfp-dd.com
Limitation on use of Information:
This specification is provided "AS IS" with NO WARRANTIES whatsoever and therefore theprovision of this specification does not include any warranty of merchantability,
noninfringement, fitness for a particular purpose, or any other warranty otherwise
arising out of any proposal, specification or sample. The authors further disclaim all
liability, including liability for infringement of any proprietary rights, relating touse of information in this specification. No license, express or implied, by estoppel orotherwise, to any intellectual property rights is granted herein.
Permissions:
You are authorized to download, reproduce and distribute this document. All other rights
are reserved. The provision of this document should not be construed as the granting of
any right to practice, make, use or otherwise develop products that are based on the
document. Any and all IP rights related to this document and the designs disclosed
within, except for the rights expressly mentioned above, are reserved by the respective
owners of those IP rights.
Dedication:
The members of the QSFP-DD MSA would like to acknowledge the contributions of Edmund Poh.
He was an excellent engineer; his technical skills and collaborative attitude will bemissed.

1

QSFP-DD Hardware Rev 5.0

The following are Promoter member companies of the QSFP-DD MSA.

Broadcom LTD
Cisco
CorningFinisar
Foxconn Interconnect Technology
Huawei LTD
Intel
Juniper Networks
Lumentum
LuxteraMellanox
Molex LLC
Oclaro, Inc.
TE Connectivity

The following are contributing member companies of the QSFP-DD MSA.
AcaciaACON
Alibaba Group
AmphenolApplied Optoelectronics
Apresia
Celestica
Ciena
ColorChip
Credo
DellEMC
Delta Products
Dust Photonics
Eoptolink
FourteFujitsu
Genesis Connected Solutions
H3C
Hisense Broadband
Hitachi Metals
Hewlett Packard Enterprise
InnoLight
Innovium
Inphi
Ixia
JPC
Kaiam
Leoni
Lorom Cable Connection
LuxshareICT
Macom
Marvell
MaxLinear
MultiLane
NeoPhotonics
Nokia
PanduitPHY-SI2QSFP-DD Hardware Rev 5.0
RanovusSamtecSemtechSenko
SicoyaThe Siemon Company
Skorpios
Source Photonics
Spectra7 Microsystems
Spirent
Sumitomo Electric
US Conec
Xilinx
YamaichiChange History:
Revision
1.0
2.0
3.0
4.0

Date
Sept 19 2016
March 13 2017
Sept 19 2017
Sept 18 2018

5.0

July 9 2019

Changes
First public release
Second public release
Third public release
Fourth public release,
Additions to thermal
section 6, synchronous
clocking section 4.4,
Mechanical updates
Added Module type 2A,
module label drawings,
changes to latch
drawings, added ePPS
pin, updated power
supply testing, added
BiDi optical port
assignments, updated
cage drawings

Foreword
The development work on this specification was done by the QSFP-DD MSA, an industry
group. The membership of the committee since its formation in Feb 2016 has included a mixof companies which are leaders across the industry.
CONTENTS
1

Scope ............................................................................... 7
1.1

2

3

References .......................................................................... 7
2.1

Industry Documents......................................................................................................................................................... 7

2.2

Sources ................................................................................................................................................................................... 8

Introduction ........................................................................ 8
3.1

3

Description of Sections ............................................................................................................................................. 7

Objectives............................................................................................................................................................................ 8QSFP-DD Hardware Rev 5.0
3.2
4

Applications ....................................................................................................................................................................... 9Electrical Specification ............................................................ 9
4.1 Electrical Connector .................................................................................................................................................... 9
4.1.1 Low Speed Electrical Hardware Signals ................................................................................................. 17
4.1.2 Low Speed Electrical Specification ........................................................................................................ 18
4.1.3 Timing for soft control and status functions ................................................................................. 19
4.1.4 High Speed Electrical Specification ...................................................................................................... 21
4.2 Power Requirements....................................................................................................................................................... 22
4.2.1 Power Classes and Maximum Power Consumption ................................................................................... 22
4.2.2 Module Power Supply Specification ........................................................................................................... 23
4.2.3 Host Board Power Supply Noise Output .................................................................................................... 24
4.2.4 Module Power Supply Noise Output ............................................................................................................. 25
4.2.5 Module Power Supply Noise Tolerance ...................................................................................................... 25
4.3

ESD .......................................................................................................................................................................................... 27

4.4 Clocking Considerations ........................................................................................................................................... 27
4.4.1 Data Path Description ....................................................................................................................................... 27
4.4.2 Tx Clocking Considerations............................................................................................................................ 27
4.4.3 Rx Clocking Considerations............................................................................................................................ 27
5

Mechanical and Board Definition .................................................... 28
5.1

Introduction ..................................................................................................................................................................... 28

5.2

Datums, Dimensions and Component Alignment ............................................................................................. 30

5.3

Module Mechanical Dimensions ............................................................................................................................... 32

5.4

Module Flatness and Roughness ............................................................................................................................ 41

5.5

Module paddle card dimensions ............................................................................................................................ 42

5.6

Module Extraction and Retention Forces ....................................................................................................... 45

5.7 2x1 Electrical Connector Mechanical .............................................................................................................. 46
5.7.1 2x1 Connector and Cage host PCB layout ............................................................................................... 50
5.8 Surface Mount Electrical Connector Mechanical ...................................................................................... 53
5.8.1 Surface mount connector and cage host PCB layout ....................................................................... 60
5.9

Module Color Coding and Labeling ..................................................................................................................... 62

5.10 Optical Interface ......................................................................................................................................................... 63
5.10.1 MPO Optical Cable connections .................................................................................................................... 65
5.10.2 Dual LC Optical Cable connection ............................................................................................................. 67
5.10.3 Dual CS Optical Cable connection ............................................................................................................. 67
5.10.4 SN Optical Cable connections ....................................................................................................................... 68
5.10.5 MDC Optical Cable connection ....................................................................................................................... 68
5.10.6 Electrical data input/output to optical port mapping .............................................................. 69
6

4

Environmental and Thermal .......................................................... 70
6.1

Thermal Requirements .................................................................................................................................................. 70

6.2

Thermal Requirements – tighter controlled environments ................................................................. 70

6.3

External Case and Handle Touch Temperature ............................................................................................. 70

QSFP-DD Hardware Rev 5.0
7Management Interface ............................................................... 71
7.1 SCL, SDA and ModSEL Timing Specification .................................................................................................. 71
7.1.1 Introduction ............................................................................................................................................................. 71
7.1.2 Management Interface Timing Specification ........................................................................................ 71
7.1.3 Serial Interface Protocol .............................................................................................................................. 72

Appendix A

Informative overall module length with elastomeric handle ................ 75

Appendix B

Module Type 2A Heat Sink Examples ........................................ 76

Table 1- Pad Function Definition....................................................... 12
Table 2- Low Speed Control and Sense Signals........................................... 18
Table 3- Timing for QSFP-DD soft control and status functions.......................... 19
Table 4- I/O Timing for Squelch & Disable.............................................. 20
Table 5- Power Classes................................................................. 22
Table 6- Truncated Filter Response Coefficients for Host Power Supply Noise Output..... 24
Table 7- Power Supply specifications, Instantaneous, sustained and steady state current
limits................................................................................. 26
Table 8- Datums....................................................................... 30
Table 9- Module flatness specifications................................................ 41
Table 10- Insertion, Extraction and Retention Forces................................... 45
Table 11- Electrical Signal to Optical Port Mapping.................................... 69
Table 12- Temperature Range Class of operation......................................... 70
Table 13- Temperature Range Classes for Tighter Controlled Applications................ 70
Table 14- Management Interface timing parameters....................................... 74

5

QSFP-DD Hardware Rev 5.0
Figure 1: Application Reference Model................................................... 9
Figure 2: Module pad layout............................................................ 11
Figure 3: Example QSFP-DD Host Board Schematic For Optical Modules..................... 14
Figure 4: Example QSFP-DD Host Board Schematic for active copper cables................ 15
Figure 5: Example QSFP-DD Host Board Schematic for passive copper cables............... 16
Figure 6: Recommended Host Board Power Supply Filtering................................ 23
Figure 7: Instantaneous and sustained peak currents for Icc Host (see Fig. 6).......... 24
Figure 8: Truncated Transfer Response for Host Board Power Supply Noise Output
measurement............................................................................ 25
Figure 9: 2x1 stacked cage and module.................................................. 28
Figure 10: Press fit cage for surface mount (SMT) connector............................ 29
Figure 11: Type 1 Pluggable module..................................................... 29
Figure 12: Type 2 Pluggable module..................................................... 29
Figure 13: 2X1 stacked connector/cage datum descriptions............................... 31
Figure 14: Surface mount connector/cage datum descriptions............................. 32
Figure 15: Type 1 Module............................................................... 33
Figure 16: Type 2 Module............................................................... 33
Figure 17: Type 2A Module.............................................................. 34
Figure 18: Drawing of module........................................................... 37
Figure 19: Type 2A Module with Heat Sink............................................... 38
Figure 20: Detailed dimensions of module............................................... 40
Figure 21: Module paddle card dimensions............................................... 43
Figure 22: Module pad dimensions....................................................... 44
Figure 23: Integrated connector in 2x1 stacked cage.................................... 46
Figure 24: 2x1 stacked cage............................................................ 47
Figure 25: 2x1 stacked cage dimensions................................................. 48
Figure 26: Connector pins in 2x1 stacked cage as viewed from the front................. 49
Figure 27: 2x1 Bezel Opening........................................................... 49
Figure 28: 2X1 host board connector contacts........................................... 50
Figure 29: 2X1 Host PCB Mechanical Layout.............................................. 52
Figure 30: SMT connector in 1xn cage................................................... 53
Figure 31: SMT 1x1 Cage Design......................................................... 57
Figure 32: SMT 1x1 Connector Design.................................................... 58
Figure 33: SMT 1x1 bezel opening....................................................... 59
Figure 34: SMT Host PCB Mechanical Layout.............................................. 60
Figure 35: SMT Connector and Host PCB Pin Numbers...................................... 61
Figure 36: Optical Media Dependent Interface port assignments.......................... 64
Figure 37: MPO-12 Single Row optical patch cord and module receptacle.................. 65
Figure 38: MPO-16 Single Row optical patchcord and module receptacle................... 66
Figure 39: MPO-12 Two Row optical patchcord and module receptacle...................... 66
Figure 40: Dual LC optical patchcord and module receptacle............................. 67
Figure 41: Dual CS connector module receptacle (in support of breakout applications)... 67
Figure 42: SN optical connector plug and four-port module receptacle................... 68
Figure 43: MDC optical connector plug and four-port module receptacle.................. 68
Figure 44: QSFP-DD Timing Diagram...................................................... 72
Figure 45: SDA/SCL options for pull-up resistor, bus capacitance and rise/fall times... 73
Figure 46: Informative overall module length with handle for Type 1 module............. 75
Figure 47: Informative overall module length with handle for Type 2 and Type 2A modules 75

6

QSFP-DD Hardware Rev 5.0

QSFP-DD 8X Pluggable Transceiver
1

Scope

The scope of this specification is the definition of a high density 8-channel (8x)module, cage and connector system. QSFP-DD supports up to 400 Gb/s in aggregate over an
8 x 50 Gb/s electrical interface. The cage and connector design provides backwards
compatibility to QSFP28 modules which can be inserted into a QSFP-DD port and connected
to 4 of the 8 electrical channels.

1.1

Description of Sections

Section 1 Scope and Purpose
Section 2 Referenced and Related Standards and SFF Specifications
Section 3 Introduction
Section 4 Electrical specifications
Section 5 Mechanical specifications and printed circuit board recommendations
Section 6 Environmental and thermal considerations
Section 7 Management Interface

2

References

2.1

Industry Documents

The following documents are relevant to this Specification:- GR-253-CORE- IEEE Std 802.3TM-2018- IEEE Std 802.3cd- InfiniBand Architecture Specifications- FC-PI-6p- FC-PI-7- ANSI/TIA-568.3- TIA-604-5 (FOCIS 5)- TIA-604-10 (FOCIS 10)- TIA-604-18 (FOCIS 18)- IEC 61754-7-1- ANSI/ESDA/JDEC JS001- EN6100-4-2- Common Management Interface Specification (CMIS)- GR63 Section 4.1.7 (Touch Temperature Reference)- UL 60950-1 Section 4.5.4 (Touch Temperature Reference)- IEC 31300-3-35- EIA-964 Specification for QSFP+ 10 Gb/s Pluggable Transceiver- Keysight Application Brief 5991-2778EN: Methods for characterizing and tuning DC
inrush current
SFF Specifications- SFF-8636- SFF-8472- SFF-8661- SFF-8679
7Management Interface for Cabled Environments
Diagnostic Monitoring Interface for Optical Transceivers
QSFP+ 4X Pluggable Module
QSFP28 4X Base Electrical SpecificationQSFP-DD Hardware Rev 5.0

CS optical connector specification- CS-01242017 Revision 1.0

2.2(Can be found at www.QSFP-DD.com)

SourcesThis document can be obtained via the www.QSFP-DD.com web site.

3

Introduction

This Specification covers the following items:a) Electrical interfaces including pad assignments for data, control, status and power
supplies and host PCB layout requirements.
b) Optical interfaces (including optical receptacles and mating fiber plugs for
multimode and single-mode duplex and parallel fiber applications). Breakout cableapplications are also specified. Optical signaling specifications are not included inthis document but are defined in the applicable industry standards.
c) Mechanical specifications including dimensions and tolerances for the connector, cageand module system. Includes details of the requirements for correct mating of the moduleand host sides of the connector.
d) Thermal requirementse) Electrostatic discharge (ESD) requirements by reference to industry standard limits
and test methods.
This Specification does not cover the following items:a) Electromagnetic interference (EMI) protection. EMI protection is the responsibility of
the implementers of the cages and modules.
b) Memory map definition, which can be found in the 'Common Management Interface
Specification for 8x/16x pluggable transceivers' (see www.QSFP-DD.com).

3.1

Objectives

Electrical signal contact and channel assignments, electrical and power requirements
defined in Section 4 and optical lane assignments defined in Section 5 ensure that thepluggable modules and cable assemblies are functionally interchangeable. Dimensions,
mounting and insertion requirements defined in Section 5 for the bezel, optical module,
cable plug, cage and connector system on a circuit board ensure that these products aremechanically interchangeable.

8

QSFP-DD Hardware Rev 5.0

3.2

Applications

This specification defines a common solution for combined eight-channel ports that
support Ethernet and/or InfiniBand and/or Fibre Channel requirements. The QSFP-DD
interface can support pluggable modules or direct attach cables based on multimode fiber,
single mode fiber or copper wires.
An application reference Model, shown in Figure 1, shows the high-speed data interface
between an ASIC and the QSFP-DD module.

Figure 1: Application Reference Model

Note: For high speed electrical signals the compliance board methodology of IEEE and OIF
should be used. Measurements taken with QSFP-DD compliance boards should be corrected forany difference between the loss of these compliance boards and the loss of the complianceboards specified in the standard.

4

Electrical Specification

This section contains signal definitions and requirements that are specific to the QSFPDD module. High-speed signal requirements including compliance points for electricalmeasurements are defined in the applicable industry standard.

4.1

Electrical Connector

The QSFP-DD module edge connector consists of a single paddle card with 38 pads on the
top and 38 pads on the bottom of the paddle card for a total of 76 pads. The pads aredefined in such a manner so as to accommodate insertion of a QSFP module into a QSFP-DD
receptacle. The legacy signal locations are deeper on the paddlecard, so that legacy
QSFP module pads only connect to the longer row of connector pins, leaving the short row
of connector pins unconnected in a QSFP application.
9

QSFP-DD Hardware Rev 5.0
The pads are designed for a sequenced mating:First mate – ground pads
Second mate – power pads
Third mate – signal pads
Because the QSFP-DD module has 2 rows of pads, the additional QSFP-DD pads will have anintermittent connection with the legacy QSFP pins in the connector during the module
insertion and removal. The 'legacy' QSFP pads have a 'B' label shown in Table 1 todesignate them as the second row of module pads to contact the QSFP-DD connector. The
additional QSFP-DD pads have an 'A' label in Table 1 to designate them as the first row
of module pads to contact the QSFP-DD connector. The additional QSFP-DD pads have first,
second and third mate to the connector pins for both insertion and removal. Each of thefirst, second and third mate connections of the legacy QSFP pads and the respective
additional QSFP-DD pads are simultaneous.
Figure 2 shows the signal symbols and pad numbering for the QSFP-DD module edge
connector. The diagram shows the module PCB edge as a top and bottom view. There are 76
pads intended for high speed signals, low speed signals, power and ground connections.
Table 1 provides more information about each of the 76 pads. Figure 21 and Figure 22 show
pad dimensions. The connector can be integrated into a 2x1 stacked configuration with 2
ports as illustrated in Figure 9 or a surface mount configuration as shown in Figure 10.
For EMI protection the signals from the host connector should be shut off when the QSFPDD module is not present. Standard board layout practices such as connections to Vcc and
GND with vias, use of short and equal-length differential signal lines are recommended.
The chassis ground (case common) of the QSFP-DD module should be isolated from themodule’s circuit ground, GND, to provide the equipment designer flexibility regarding
connections between external electromagnetic interference shields and circuit ground,
GND, of the module.

10

QSFP-DD Hardware Rev 5.0

Top side viewed from top
Module Card Edge (Host Side)(Module Side)38 GND
37 TX1n
36 TX1p
35 GND
34 TX3n33 TX3p
32 GND
31 LPMode
30 Vcc1
29 VccTx
28 IntL
27 ModPrsL
26 GND
25 RX4p
24 RX4n23 GND
22 RX2p
21 RX2n20 GND76 GND
75 TX5n
74 TX5p
73 GND
72 TX7n
71 TX7p
70 GND
69 ePPS
68 Vcc2
67 VccTx1
66 Reserved
65 NC
64 GND63 RX8p
62 RX8n61 GND
60 RX6p
59 RX6n58 GND

LegacyQSFP28 Pads

Additional
QSFP-DD Pads

Figure 2: Module pad layout
11

QSFP-DD Hardware Rev 5.0

Pad
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38

12

Logic

CML-I
CML-I
CML-I
CML-I
LVTTL-ILVTTL-I
LVCMOSI/O
LVCMOSI/O
CML-O
CML-O
CML-O
CML-O

CML-O
CML-O
CML-O
CML-O
LVTTL-O
LVTTL-O

LVTTL-I
CML-I
CML-I
CML-I
CML-I

SymbolTable 1- Pad Function Definition
Description

GND
Tx2n
Tx2p
GND
Tx4n
Tx4p
GND
ModSelL
ResetL
VccRx
SCL

GroundTransmitter Inverted Data Input
Transmitter Non-Inverted Data Input
GroundTransmitter Inverted Data Input
Transmitter Non-Inverted Data Input
GroundModule Select
Module Reset+3.3V Power Supply Receiver
2-wire serial interface clock

Plug
Sequence4
1B
3B
3B
1B
3B
3B
1B
3B
3B
2B
3B

SDA

2-wire serial interface data

3B

GND
Rx3p
Rx3n
GND
Rx1p
Rx1n
GND
GND
Rx2n
Rx2p
GND
Rx4n
Rx4p
GND
ModPrsL
IntL
VccTx
Vcc1
LPMode
GND
Tx3p
Tx3n
GND
Tx1p
Tx1n
GND

GroundReceiver Non-Inverted Data Output
Receiver Inverted Data Output
GroundReceiver Non-Inverted Data Output
Receiver Inverted Data Output
GroundGroundReceiver Inverted Data Output
Receiver Non-Inverted Data Output
GroundReceiver Inverted Data Output
Receiver Non-Inverted Data Output
GroundModule Present
Interrupt+3.3V Power supply transmitter+3.3V Power supply
Low Power mode;
GroundTransmitter Non-Inverted Data Input
Transmitter Inverted Data Input
GroundTransmitter Non-Inverted Data Input
Transmitter Inverted Data Input
Ground

1B
3B
3B
1B
3B
3B
1B
1B
3B
3B
1B
3B
3B
1B
3B
3B
2B
2B
3B
1B
3B
3B
1B
3B
3B
1B

Notes
1

1

1

2

1

1

1
1

1

1

2
2
1

1

1

QSFP-DD Hardware Rev 5.0
Pad
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69

Logic

SymbolPlug
Sequence4
1A
3A
3A
1A
3A
3A
1A
3A
3A
2A
3A
3A
1A
3A
3A
1A
3A
3A
1A
1A
3A
3A
1A
3A
3A
1A
3A
3A
2A
2A
3A

Notes

Ground1
Transmitter Inverted Data Input
Transmitter Non-Inverted Data Input
Ground1
CML-I
Transmitter Inverted Data Input
CML-I
Transmitter Non-Inverted Data Input
Ground1
For future use
3
Module Vendor Specific 1
3
3.3V Power Supply
2
Module Vendor Specific 2
3
Module Vendor Specific 3
3Ground1
CML-O
Receiver Non-Inverted Data Output
CML-O
Receiver Inverted Data Output
Ground1
CML-O
Receiver Non-Inverted Data Output
CML-O
Receiver Inverted Data Output
Ground1
Ground1
CML-O
Receiver Inverted Data Output
CML-O
Receiver Non-Inverted Data Output
Ground1
CML-O
Receiver Inverted Data Output
CML-O
Receiver Non-Inverted Data Output
Ground1
No Connect
3
For future use
3
3.3V Power Supply
2
3.3V Power Supply
2
LVTTL-I
Precision Time Protocol (PTP) reference3
clock input
70
GND
Ground
1A
1
71
CML-I
Tx7p
Transmitter Non-Inverted Data Input
3A
72
CML-I
Tx7n
Transmitter Inverted Data Input
3A
73
GND
Ground
1A
1
74
CML-I
Tx5p
Transmitter Non-Inverted Data Input
3A
75
CML-I
Tx5n
Transmitter Inverted Data Input
3A
76
GND
Ground1A
1Note 1: QSFP-DD uses common ground (GND)for all signals and supply (power). All arecommon within the QSFP-DD module and all module voltages are referenced to thispotential unless otherwise noted. Connect these directly to the host board signalcommon ground plane.
Note 2: VccRx, VccRx1, Vcc1, Vcc2, VccTx and VccTx1 shall be applied concurrently.
Requirements defined for the host side of the Host Card Edge Connector are listed
in Table 7. VccRx, VccRx1, Vcc1, Vcc2, VccTx and VccTx1 may be internallyconnected within the module in any combination. The connector Vcc pins are each
rated for a maximum current of 1000 mA.
Note 3: All Vendor Specific, Reserved, No Connect and ePPS (if not used) pins may
be terminated with 50 Ohms to ground on the host. Pad 65 (No Connect) shall beleft unconnected within the module. Vendor specific and Reserved pads shall havean impedance to GND that is greater than 10 kOhms and less than 100 pF.
Note 4: Plug Sequence specifies the mating sequence of the host connector andmodule. The sequence is 1A, 2A, 3A, 1B, 2B, 3B. (see Figure 2 for pad locations)Contact sequence A will make, then break contact with additional QSFP-DD pads.
Sequence 1A,1B will then occur simultaneously, followed by 2A,2B,followed by 3A,3B.
13

CML-I
CML-I

GND
Tx6n
Tx6p
GND
Tx8n
Tx8p
GND
Reserved
VS1
VccRx1
VS2
VS3
GND
Rx7p
Rx7n
GND
Rx5p
Rx5n
GND
GND
Rx6n
Rx6p
GND
Rx8n
Rx8p
GND
NC
Reserved
VccTx1
Vcc2
ePPS

DescriptionQSFP-DD Hardware Rev 5.0

Figure 3, Figure 4 and Figure 5 show examples of QSFP-DD host PCB schematics withconnections to CDR and control ICs. An 8 wide electrical/optical interface is shown. Notealternate electrical/optical interfaces are supported using optical multiplexing (WDM) orelectrical multiplexing.
Vcc Host

To other QSFP-DD modules

4.7k to 10k ohms

1.0k to 3.3k ohms
SDA

Micro
Controller

SCL
ModPrsL
ModSelL
ResetLIntL
LPModeRXRate<1:8>

TXFault
<1:8>
RXLOS
<1:8>

TXDisable<1:8>

PLD/PAL

Rx1p/nTIA
Rx8p/nProtocolIC

Tx8p/nTx1p/nVcc Host
0.1uF

CDR
22 uF

1 uH
VccRx, VccRx1

Note: Filter capacitor
values are informative andvary depending on applications.
0.1 uF capacitors should be placed inclose proximity to power pins andmay be duplicated for individual pinsto provide additional high frequency
filtering.
Note: Vcc1 and/or Vcc2 may
be connected to VccTx, VccTx1 or
VccRx, VccRx1 provided theapplicable derating of the maximum
current limit is used

1 uH

22 uF

0.1uF

GND

Laser
Drivers

VccTx, VccTx1
22 uF

0.1uF

GND

1 uH

Vcc1, Vcc2
22 uF

0.1uF

GND

QSFP-DD Optical Module
Figure 3: Example QSFP-DD Host Board Schematic For Optical Modules

14

QSFP-DD Hardware Rev 5.0
Vcc Host
4.7k to 10k ohms

To other QSFP-DD modules
1k to 3.3k ohms
SDA
SCL
ModPrsL

MicroController

4.7k to 10k ohms

PLD/PALModSelL
ResetLIntL

RXRate<1:8>

TXFault
<1:8>
RXLOS
<1:8>

TXDisable<1:8>

LPModeProtocolIC

Rx1p/nRx1p/nRx8p/nRx8p/nTx8p/nTx8p/nTx1p/nTx1p/nVcc Host
0.1uF

CDR
22 uF

1 uH
VccRx, VccRx1

Note: Filter capacitor
values are informative andvary depending on applications.
0.1 uF capacitors should be placed inclose proximity to power pins andmay be duplicated for individual pinsto provide additional high frequency
filtering.

1 uH

22 uF

0.1uF

VccTx, VccTx1
22 uF

0.1uF

GND

1 uH
Note: Vcc1 and/or Vcc2 may
be connected to VccTx, VccTx1
or VccRx, VccRx1 provided theapplicable derating of the
maximum current limit is used

GND

Vcc1, Vcc2
22 uF

0.1uF

GND

QSFP-DD Active Copper Module
Figure 4: Example QSFP-DD Host Board Schematic for active copper cables

15

QSFP-DD Hardware Rev 5.0

Vcc Host

To other QSFP-DD modules

4.7k to 10k ohms
1k to 3.3k ohms
SDA
SCL
ModPrsL
4.7k to 10k ohms

PLD/PAL

Micro
Controller

ModSelL
ResetLIntL

RXRate<1:8>

TXFault
<1:8>
RXLOS
<1:8>

TXDisable<1:8>

LPModeProtocolIC

Rx1p/nRx1p/nRx8p/nRx8p/nTx8p/nTx8p/nTx1p/nTx1p/nVcc Host
0.1uF

22 uF

1 uH
Vcc1, Vcc2 VccTx, VccTx1, VccRx, VccRx1

Note: Filter capacitor values are informative andvary depending on applications.
0.1 uF capacitors should be placed in close proximity topower pins and may be duplicated for individual pins toprovide additional high frequency filtering.
Note: Recommended filtering is only valid for
dedicated passive copper cable ports. For ports
supporting both passive and active modules use
recommended filtering from Fig. 3 and 4.

22 uF

0.1uF

GND

QSFP-DD Passive Copper Module

Figure 5: Example QSFP-DD Host Board Schematic for passive copper cables

16

QSFP-DD Hardware Rev 5.0

4.1.1 Low Speed Electrical Hardware Signals
In addition to the 2-wire serial interface the module has the following low speed signals
for control and status:
ModSelL
ResetL
LPModeModPrsL
IntL
ePPS
4.1.1.1 ModSelL
The ModSelL is an input signal that shall be pulled to Vcc in the QSFP-DD module (seeTable 2). When held low by the host, the module responds to 2-wire serial communicationcommands. The ModSelL allows the use of multiple QSFP-DD modules on a single 2-wireinterface bus. When ModSelL is “High”, the module shall not respond to or acknowledge any
2-wire interface communication from the host.
In order to avoid conflicts, the host system shall not attempt 2-wire interface
communications within the ModSelL de-assert time after any QSFP-DD modules aredeselected. Similarly, the host must wait at least for the period of the ModSelL assert
time before communicating with the newly selected module. The assertion and de-asserting
periods of different modules may overlap as long as the above timing requirements aremet.
4.1.1.2 ResetL
The ResetL signal shall be pulled to Vcc in the module (see Table 2). A low level on the
ResetL signal for longer than the minimum pulse length (t_Reset_init) (See Table 3)
initiates a complete module reset, returning all user module settings to their default
state.
4.1.1.3 LPMode
LPMode is an input signal. The LPMode signal shall be pulled up to Vcc in the QSFP-DD
module (see Table 2). LPMode is used in the control of the module power mode.
See CMIS Section 6.3.1.3.

4.1.1.4 ModPrsL
ModPrsL shall be pulled up to Vcc Host on the host board and pulled low in the module(see Table 2). The ModPrsL is asserted “Low” when the module is inserted. The ModPrsL isdeasserted “High” when the module is physically absent from the host connector due to thepull-up resistor on the host board.

4.1.1.5 IntL
IntL is an output signal. The IntL signal is an open collector output and shall be pulled
to Vcc Host on the host board (see Table 2). When the IntL signal is asserted Low it
indicates a change in module state, a possible module operational fault or a status
critical to the host system. The host identifies the source of the interrupt using the 2wire serial interface. The IntL signal is deasserted “High” after all set interrupt flags
are read.

4.1.1.6 ePPS PTP Reference Clock (Optional)
For high-performance Precision Time Protocol(PTP) applications, a PTP reference clockwith Pulse Per Second modulation, (Enhanced Pulse Per Second (ePPS)) may be provided fromthe host to the module. This can be used for either offline delay characterization or
17

QSFP-DD Hardware Rev 5.0
real-time delay compensation within the module. The clock is used to synchronize tightly
the Host Time-of-Day counter to the module internal Time-of-Day Counter.
Editor’s Note – Full definition of ePPS is currently under development

4.1.2 Low Speed Electrical Specification
Low speed signaling other than the SCL and SDA interface is based on Low Voltage TTL(LVTTL) operating at Vcc. Vcc refers to the generic supply voltages of VccTx, VccRx, Vcc
host or Vcc1. Hosts shall use a pull-up resistor connected to Vcc host on each of the 2wire interface SCL (clock), SDA (data), and all low speed status outputs (see Table 2).
The SCL and SDA is a hot plug interface that may support a bus topology. During module
insertion or removal, the module may implement a pre-charge circuit which prevents
corrupting data transfers from other modules that are already using the bus.
Note: Timing diagrams for SCL and SDA are shown in Section 7.
The QSFP-DD low speed electrical specifications are given in Table 2. This specification
ensures compatibility between host bus masters and the 2-wire interface.

Parameter
SCL and SDA

SCL and SDA
Capacitance for SCL
and SDA I/O signal
Total bus
capacitive load for
SCL and SDA

18

Table 2- Low Speed Control and Sense Signals
SymbolMin
Max
Unit Condition
VOL
0
0.4
V
IOL(max)=3 mA for fastmode, 20 mA for Fast-mode
plus
VIL
-0.3
Vcc*0.3 V
VIH
VCC*0.7 Vcc+0.5 V
Ci
14
pF
Cb

LPMode, ResetL,
ModSelL and ePPS
LPMode, ResetL and
ModSelL
ePPS
IntL

VIL
VIH
|Iin|

ModPrsL

VOL
VOH

|Iin|
VOL
VOH

100

pF

200

pF

0.8
VCC+0.3
360

V
V
uA

0
VCC-0.5

TBD
0.4
VCC+0.3

uA
V
V

0

0.4

V

-0.3
2

For 400 kHz clock rateuse 3.0 k Ohms Pullup
resistor, max. For
1000kHz clock rate refer
to Figure 45
For 400kHz clock rate use
1.6 k Ohms pullup
resistor, max. For
1000kHz clock rate refer
to Figure 45.

0V<Vin<Vcc
0V<Vin<Vcc
IOL=2.0 mA
10k Ohms pull-up to Host
Vcc
IOL=2.0 mA
ModPrsL can be
implemented as a shortcircuit to GND on themoduleQSFP-DD Hardware Rev 5.0
4.1.3 Timing for soft control and status functions
Timing for QSFP-DD soft control and status functions are described in Table 3.
Table 3- Timing for QSFP-DD soft control and status functions
Parameter
SymbolMin
Max
Unit Conditions
Max MgmtInit
2000
ms
Time from power on1 , hot plug or
MgmtInitDuration
Durationrising edge of reset until
completion of the MgmtInit State
ResetL Assert Time t_reset_init
10µsMinimum pulse time on the ResetL
signal to initiate a module reset.
IntL Assert Time
ton_IntL
200
ms
Time from occurrence of condition
triggering IntL until
Vout:IntL=Vol
IntL Deassert Time toff_IntL
500µsTime from clear on read2 operationof associated flag until
Vout:IntL=Voh. This includes
deassert times for Rx LOS, Tx
Fault and other flag bits.
Rx LOS Assert Time ton_los
100ms
Time from Rx LOS condition present
to Rx LOS bit set (value = 1b) and
IntL asserted.
Rx LOS Assert Time ton_losf
1
msTime from Rx LOS state to Rx LOS(optional fast
bit set (value = 1b) and IntL
mode)
asserted.
Tx Fault Assert
ton_Txfault
200
ms
Time from Tx Fault state to Tx
Time
Fault bit set (value=1b) and IntL
asserted.
Flag Assert Time
ton_flag200
msTime from occurrence of condition
triggering flag to associated flag
bit set (value=1b) and IntL
asserted.
Mask Assert Time
ton_mask
100
ms
Time from mask bit set (value=1b)3
until associated IntL assertion is
inhibited
Mask Deassert Time toff_mask
100ms
Time from mask bit cleared(value=0b)3 until associated IntL
operation resumes
Module Select Wait ModSelL Wait
See Common Management Interface
Time
Time
Specification Table 8-28
DataPathDeinit Max
Duration
DataPathDeinit
DataPathInit Max_MaxDuration
Duration
ModulePwrDn Max
DataPathInit_
Duaration
MaxDuration
ModulePwrDn_
MaxDuration
Note 1. Power on is defined as the instant when supply voltages reach and remain at or
above the minimum level specified in Table 7.
Note 2. Measured from low to high SDA edge of the Stop condition of the read transaction
Note 3. Measured from low to high SDA edge of the Stop condition of the write transaction
Note 4. Rx LOS condition is defined at the optical input by the relevant standard

19

QSFP-DD Hardware Rev 5.0

Squelch and disable timings are defined in Table 4.

Parameter
Rx Squelch
Assert TimeRx Squelch
Deassert TimeTx Squelch
Assert TimeTx Squelch
Deassert Time
Tx Disable
Assert Time

Table 4- I/O Timing for Squelch & Disable
SymbolMax
Unit Conditions
ton_Rxsq
15
msTime from loss of Rx input signal until
the squelched output condition isreached. See Subsection 4.1.4.1.
toff_Rxsq
15
ms
Time from resumption of Rx input signals
until normal Rx output condition isreached. See subsection 4.1.4.1.
ton_Txsq
400
msTime from loss of Tx input signal until
the squelched output condition isreached. See subsection 4.1.4.2.
toff_Txsq
400ms
Time from resumption of Tx input signals
until normal Tx output condition isreached. See subsection 4.1.4.2.
ton_txdis
100
ms
Time from the stop condition of the Tx
Disable write sequence 1 until optical
output falls below 10% of nominal

Tx Disable
Assert Time
(optional fastmode)
Tx Disable
Deassert Time

ton_txdisf

3ms

Time from Tx Disable bit set (value =1b)1 until optical output falls below
10% of nominal

toff_txdis

400

ms

Tx Disable
Deassert Time
(optional fastmode)
Rx Output
Disable Assert
Time
Rx Output
Disable Deassert
Time

toff_txdisf

10ms

Time from Tx Disable bit cleared (value= 0b)1 until optical output rises above
90% of nominal
Time from Tx Disable bit cleared (value= 0b)1 until optical output rises above
90% of nominal

ton_rxdis

100ms

toff_rxdis

100

ms

ton_sqdis

100ms

toff_sqdis

100

ms

Squelch Disable
Assert Time
Squelch Disable
Deassert TimeTime from Rx Output Disable bit set(value = 1b)1 until Rx output falls
below 10% of nominal
Time from Rx Output Disable bit cleared(value = 0b)1 until Rx output rises
above 90% of nominal
This applies to Rx and Tx Squelch and is
the time from bit set (value = 0b)1
until squelch functionality is disabled.

This applies to Rx and Tx Squelch and is
the time from bit cleared (value = 0b)1
until squelch functionality is enabled
Note 1: Measured from LOW to HIGH SDA signal transition of the STOP condition of
the write transaction

20

QSFP-DD Hardware Rev 5.0
4.1.4 High Speed Electrical Specification
For detailed electrical specifications see the appropriate specification, e.g. IEEE Std
802.3-2018 Annex 86A, Annex 120E or Annex 120C, FC-PI-6, FC-PI-7, OIF-CEI-28G-VSR, OIFCEI-56G-VSR or the InfiniBand specification. Partial or complete squelch specifications
may be provided in the appropriate specification. Where squelch is not fully defined by
the appropriate specification, the recommendations of the following subsections 4.1.4.1
and 4.1.4.2 may be used.

4.1.4.1 Rx(n)(p/n)Rx(n)(p/n) are QSFP-DD module receiver data outputs. Rx(n)(p/n) are AC-coupled 100 Ohm
differential lines that should be terminated with 100 Ohm differentially at the Host
ASIC(SerDes). The AC coupling is inside the QSFP-DD module and not required on the Hostboard. When properly terminated, the differential voltage swing shall be less than orequal to 900 mVpp or the relevant standard, whichever is less.
Output squelch for loss of optical input signal, hereafter Rx Squelch, is required andshall function as follows. In the event of the Rx input signal on any optical port
becoming equal to or less than the level required to assert LOS, then the receiver
output(s) associated with that Rx port shall be squelched. A single Rx optical port canbe associated with more than one Rx output as shown in Section 5.10.6. In the squelchedstate output impedance levels are maintained while the differential voltage amplitude
shall be less than 50 mVpp.
In normal operation the default case has Rx Squelch active. Rx Squelch can bedeactivated using Rx Squelch Disable through the 2-wire serial interface. Rx Squelch
Disable is an optional function.
4.1.4.2 Tx(n)(p/n)Tx(n)(p/n) are QSFP-DD module transmitter data inputs. They are AC-coupled 100 Ohm
differential lines with 100 Ohm differential terminations inside the QSFP-DD opticalmodule. The AC coupling is implemented inside the QSFP-DD optical module and not
required on the Host board.
Output squelch for loss of electrical signal, hereafter Tx Squelch, is an optional
function. Where implemented it shall function as follows. In the event of thedifferential, peak-to-peak electrical signal amplitude on any electrical input channel
becoming less than 70 mVpp, then the transmitter optical output associated with thatelectrical input channel shall be squelched and the associated TxLOS flag set. If
multiple electrical input channels are associated with the same optical output channel,
the loss of any of the incoming electrical input channels causes the optical output
channel to be squelched.
For applications, e.g. Ethernet, where the transmitter off condition is defined in termsof average power, squelching by disabling the transmitter is recommended and for
applications, e.g. InfiniBand, where the transmitter off condition is defined in terms of
OMA, squelching the transmitter by setting the OMA to a low level is recommended.
In module operation, where Tx Squelch is implemented, the default case has Tx Squelch
active. Tx Squelch can be deactivated using Tx Squelch Disable through the 2-wire serialinterface. Tx Squelch and Tx Squelch Disable are optional functions.

21

QSFP-DD Hardware Rev 5.0

4.2

Power Requirements

The power supply has six designated pins, VccTx, VccTx1, Vcc1, Vcc2, VccRx, VccRx1 in theconnector. Vcc1 and Vcc2 are used to supplement VccTx, VccTx1, VccRx or VccRx1 at thediscretion of the module vendor. Power is applied concurrently to these pins.
A host board together with the QSFP-DD module(s) forms an integrated power system. The
host supplies stable power to the module. The module limits electrical noise coupled backinto the host system and limits inrush charge/current during hot plug insertion.
All power supply requirements in Table 7 shall be met at the maximum power supply
current. No power sequencing of the power supply is required of the host system since themodule sequences the contacts in the order of ground, supply and signals during
insertion.

4.2.1 Power Classes and Maximum Power Consumption
There are two power modes; Low Power Mode and High Power Mode, and eight power classes,
Class 1 - Class 8. Module power modes are defined in Table 7 and power classes aredefined in Table 5.
Since a wide range of module power classes exist, to avoid exceeding the system power
supply limits and cooling capacity when a module is inserted into a system designed toaccommodate only low power consumption modules, it is recommended that the host implement
the state machine defined in the QSFP-DD Management Interface Specification and identify
the power class of the module before allowing the module to go into high power mode.
Table 5- Power Classes
Power ClassMax Power (W)
1
1.5
2
3.5
3
7.0
4
8.0
5
10
6
12
7
14
8
>14
In general, the higher power classification levels are associated with higher data rates
and longer reaches. The system designer is responsible for ensuring that the maximum casetemperature does not exceed the case temperature requirements.
Host Board Power Supply Filtering. The specification of the host power supply filtering
network is beyond the scope of this specification, particularly because of the wide rangeof module Power Classes. During power transient events, the host should ensure that thatany neighboring modules sharing the same supply stay within their specified supply
voltage limits. An example of host board power supply filtering is shown in Figure 6.

22

QSFP-DD Hardware Rev 5.0

Figure 6: Recommended Host Board Power Supply Filtering

Any voltage drop across a filter network on the host is counted against the host DC set
point accuracy specification. Inductors with DC Resistance of less than 0.1 Ohm should be
used in order to maintain the required voltage at the Host Card Edge Connector. It is
recommended that the 22 uF capacitors each have an equivalent series resistance of 0.22
Ohm.
The specifications for the power supply are shown in Table 7. The limits in Table 7 apply
to the combined current that flows through all inductors in the power supply filter(represents ICC host in Figure 6). The test method for measuring inrush current can befound in SFF-8679. Keysight Technologies application brief 5991-2778EN provides usefulguidance.
4.2.2 Module Power Supply Specification
In order to avoid exceeding the host system power capacity, upon hot-plug, power cycle orreset, all QSFP-DD modules shall power up in Low Power Mode if LPMode is asserted. If
LPMode is not asserted the module will proceed to High Power Mode without hostintervention. Figure 7 shows waveforms for maximum instantaneous, sustained and steadystate currents for Low Power and High Power modes. Specification values for maximum
instantaneous, sustained and steady state currents at each power class are given in Table
7.

23

QSFP-DD Hardware Rev 5.0
Icc Host (ma)
LOW POWER MODE
Transmitters OFF

HIGH POWER MODE
Transmitters OFF

HIGH POWER MODE
Transmitters ON

500 ms, max
50 υs, max
Instantaneous peak, max
Sustained peak, max

50 υs, max

Steady state, max
500 ms, max
50 υs, max
Icc ip lp

500 ms, max

Icc sp lp

TxOff state inrush current
graph is informative. It
cannot exceed the Highpower mode TransmitterOn currents. No currents
or power consumption
are specified

Icc lpt
Hot Plug
Instant

Host Enables
Transmitters

Host Enables HighPower Mode

Figure 7: Instantaneous and sustained peak currents for Icc Host (see Fig. 6)

4.2.3 Host Board Power Supply Noise Output
The host shall generate an effective weighted integrated spectrum RMS noise less than theeN_Host value in Table 7 when tested by the methods of SFF-8431, section D.17.1 with thefollowing exception: The truncated function equation with coefficients from Table 6. The
frequency response of the truncated function is illustrated in Figure 8.

Table 6- Truncated Filter Response Coefficients for Host Power Supply Noise Output
Frequency
10 Hz < f < 240.2 Hz

a
0

b
0

c
0

d
0

e
-0.1

240.2 Hz < f < 24.03 kHz
24.03 kHz < f < 360.4 kHz
360.4 kHz < f < 12.6 MHz
12.6 MHz < f < 24 MHz

0.3784-22.67038
3.692166
0-3.6045430.392-91.467
012.694-3053.779
838.800-19.5569574.26-3400.38
0

11.002-11175.98
5139.285-60

24

QSFP-DD Hardware Rev 5.0

Figure 8: Truncated Transfer Response for Host Board Power Supply Noise Output measurement
4.2.4 Module Power Supply Noise Output
The QSFP-DD module shall generate less than the value in Table 7 when tested by themethods of SFF-8431, section D.17.2. Note: The series resistor specified in D.17 Figure
56 is reduced for high power modules by the following equation: R9series =0.1*1.5/(Module Advertised Power Consumption (max)).

4.2.5 Module Power Supply Noise Tolerance
The QSFP-DD module shall meet all requirements and remain fully operational in thepresence of a sinusoidal tolerance signal of amplitude given by Table 7, swept from 10
Hz to 10 MHz according to the methods of SFF-8431, section D.17.3 with the exception that
4.7uH in SFF-8431 Figure 58 is replaced with 1 uH and the ESR of the 22uF capacitor (0.5Ohm) is replaced with 0.22 Ohm. This emulates the worst case noise output of the host.

25

QSFP-DD Hardware Rev 5.0

Table 7- Power Supply specifications, Instantaneous, sustained and steady state current limits
Parameter
SymbolMin
NomMax
Power supply voltages VccTx, VccTx1,
3.135
3.3
3.465
VccRx, VccRx1, Vcc1 & Vcc2 including
ripple, droop and noise below 100kHz1
Host RMS noise output 40 Hz-10 MHz
25
Module RMS noise output 10 Hz - 10 MHz
30
Module power supply noise tolerance 10 Hz
PSNRmod66- 10 MHz (peak-to-peak)
Module inrush - instantaneous peak
T_ip50
duration2
Module inrush - initialization time2
T_init500
Low Power Mode
Power Consumption
P_lp
1.5
Instantaneous peak current at hot plug
Icc_ip_lp
600
Sustained peak current at hot plug
Icc_sp_lp
495
Steady state current
Icc_lpSee Note 3
High Power Mode Power Class 1 module
Power Consumption
P_1
1.5
Instantaneous peak current
Icc_ip_1
600
Sustained peak current
Icc_sp_1
495
Steady state current
Icc_1
See Note 3
High Power Mode Power Class 2 module
Power Consumption
P_2
3.5
Instantaneous peak current
Icc_ip_2
1400
Sustained peak current
Icc_sp_2
1155
Steady state current
Icc_2
See Note 3
High Power Mode Power Class 3 module
Power Consumption
P_3
7
Instantaneous peak current
Icc_ip_3
2800
Sustained peak current
Icc_sp_3
2310
Steady state current
Icc_3
See Note 3
High Power Mode Power Class 4 module
Power Consumption
P_4
8Instantaneous peak current
Icc_ip_4
3200
Sustained peak current
Icc_sp_4
2640
Steady state current
Icc_4
See Note 3
High Power Mode Power Class 5 module
Power Consumption
P_5
10
Instantaneous peak current
Icc_ip_5
4000
Sustained peak current
Icc_sp_5
3300
Steady state current
Icc_5
See Note 3
High Power Mode Power Class 6 module
Power Consumption
P_6
12Instantaneous peak current
Icc_ip_6
4800
Sustained peak current
Icc_sp_6
3960
Steady state current
Icc_6
See Note 3
High Power Mode Power Class 7 module
Power Consumption
P_7
14
Instantaneous peak current
Icc_ip_7
5600
Sustained peak current
Icc_sp_7
4620
Steady state current
Icc_7
See Note 3
High Power Mode Power Class 8 module
Power Consumption
P_84>14
Instantaneous peak current
Icc_ip_8
P_8/2.5
Sustained peak current
Icc_sp_8
P_8/3.03
Steady state current
Icc_8
6Note 1: Measured at VccTx, VccTx1, VccRx, VccRx1, Vcc1 and Vcc2
Note 2: T_ip and T_init are test conditions for measuring inrush current and notcharacteristics of the module
Note 3: The module must stay within its declared power class.
Note 4: User must read management register for maximum power consumption

26

Unit
V

mV
mV
mV
µs
ms
W
mA
mA
mA
W
mA
mA
mA
W
mA
mA
mA
W
mA
mA
mA
W
mA
mA
mA
W
mA
mA
mA
W
mA
mA
mA
W
mA
mA
mA
W
A
A
A

QSFP-DD Hardware Rev 5.0

4.3

ESD

Where ESD performance is not otherwise specified, e.g. in the InfiniBand specification,
the QSFP-DD module shall meet ESD requirements given in EN61000-4-2, criterion B test
specification when installed in a properly grounded cage and chassis. The units are
subjected to 15kV air discharges during operation and 8kV direct contact discharges tothe case. All the QSFP-DD module and host pins including high speed signal pins shallwithstand 1000 V electrostatic discharge based on Human Body Model per ANSI/ESDA/JEDEC
JS-001.

4.4 Clocking Considerations

4.4.1 Data Path Description
Within a module, host electrical and module media lanes are grouped together into a
logical concept called a data path. A data path is intended to represent a group of lanes
over which a block of data is distributed that will be powered up or down and initialized
together. Some examples include a 100GAUI-4 to 100GBASE-SR4 module implementation, where
the data path would include four host electrical lanes and four module media lanes, or a
400GAUI-8 to 400GBASE-DR4 module implementation, where the data path would include eight
host electrical lanes and four module media lanes.

4.4.2 Tx Clocking Considerations
Within a given Tx data path the host is responsible for ensuring that all electricallanes delivered to the module are frequency synchronous (sourced from the same clock
domain). If a module supports multiple Tx data paths running concurrently, the different
Tx data paths can either all be in a single clock domain or separate clock domains. The
module advertises which of these two modes it supports via the management registers.
If the module supports multiple Tx data paths running concurrently in a single clock
domain, the module shall ensure that active Tx data paths continue to operate undisturbed
even as other Tx data paths (and their associated Tx input lanes) are enabled/disabled by
the host.

4.4.3 Rx Clocking Considerations
Within a given Rx data path all lanes received on the module media interface are required
to be frequency synchronous (sourced from the same clock domain). If a module supports
multiple Rx data paths running concurrently, the module shall allow the different Rx data
paths to be asynchronous from each other (sourced from separate clock domains).

27

QSFP-DD Hardware Rev 5.0

5Mechanical and Board Definition

5.1

Introduction

The cages and modules defined in this section are illustrated in Figure 9 (2x1 stacked
cage and module), Figure 10 (press fit cage for surface mount connector}, Figure 11 (Type
1 pluggable module) and Figure 12 (Type 2 pluggable module). All pluggable modules anddirect attach cable plugs (both Type 1 and Type 2) must mate to the connectors and cages
defined in this specification. The Type 2 module allows an additional extension of themodule outside of the cage to allow for flexibility in module design. A Type 2A module
includes a heat sink on the extension of the module outside the cage to provide enhanced
thermal performance. Heat sink/clip thermal designs are application specific and not
specifically defined by this specification. See Appendix A for informative
recommendations on overall module length including handle. See Appendix B for recommended
heat sink design for Type 2A modules.

Figure 9: 2x1 stacked cage and module

28

QSFP-DD Hardware Rev 5.0

Figure 10: Press fit cage for surface mount (SMT) connector

Figure 11: Type 1 Pluggable module

Figure 12: Type 2 Pluggable module

29

QSFP-DD Hardware Rev 5.0

5.2

Datums, Dimensions and Component Alignment

A listing of the datums for the various components is contained in Table 8. The
alignments of some of the datums are noted. In order to reduce the complexity of thedrawings, all dimensions are considered centered unless otherwise specified. Dimensions
and tolerancing conform to ASME Y14.5-2009. All dimensions are in millimeters.
Table 8- Datums
Datum
Description
A
Host Board Top Surface
B
Inside surface of bezel
C**Distance between Connector terminal thru holes on host board
D*Hard stop on module
E**Width of module
F
Height of module housing
G**Width of module pc board
H
Leading edge of signal contact pads on module pc boardJ
Top surface of module pc board
K*Host board thru hole #1 to accept connector guide post
L
*Host board thru hole #2 to accept connector guide post
M**Width of bezel cut out
P
Vertical Center line of internal surface of cage
S
Seating plane of cage on host board
T*Hard stop on cage
AA**Connector slot widthBB
Seating plane of connector on host board
DD
Top surface of module housing
EE
Centerline of module opening to locate paddle card Datum H
FF
Centerline of upper port cage height
GG
Centerline of lower port cage height
EE
Primary Datum hole for 2x1 Host PCB*Datums D and T are aligned when assembled (see Figure 13 and Figure 14)**Centerlines of datums AA, C, E, G, M are aligned on the same vertical
plane

30

QSFP-DD Hardware Rev 5.0

Figure 13: 2X1 stacked connector/cage datum descriptions

31

QSFP-DD Hardware Rev 5.0

Figure 14: Surface mount connector/cage datum descriptions

5.3

Module Mechanical Dimensions

The mechanical outline for the Type 1 module is shown in Figure 15, the Type 2 module isshown in Figure 16 and the Type 2A module in Figure 17. The module shall provide a means
to self-lock with either the 2x1 stacked cage or SMT cage upon insertion. The module
package dimensions are defined in Figure 18 and Figure 20. The dimensions that control
the size of the module that extends outside of the cage are listed as maximum dimensions
per Note 4 in Figure 18. Note: All dimensions are in mm.

32

QSFP-DD Hardware Rev 5.0

Figure 15: Type 1 Module

Figure 16: Type 2 Module33

QSFP-DD Hardware Rev 5.0

Figure 17: Type 2A Module34

QSFP-DD Hardware Rev 5.0

35

QSFP-DD Hardware Rev 5.0

36

QSFP-DD Hardware Rev 5.0

Figure 18: Drawing of module
37

QSFP-DD Hardware Rev 5.0

Figure 19: Type 2A Module with Heat Sink
38

QSFP-DD Hardware Rev 5.0

39

QSFP-DD Hardware Rev 5.0

Figure 20: Detailed dimensions of module

40

QSFP-DD Hardware Rev 5.0

5.4

Module Flatness and Roughness

Module flatness and roughness are specified to improve module thermal characteristics
when used with a riding heat sink. Relaxed specifications are used for lower power
modules to reduce cost. The module flatness and roughness specifications apply to thespecified heat sink contact area as specified in Figure 18. Specifications for Module
flatness and surface roughness are shown in Table 9 (see Figure 18 note 11).

Power Class
1
2
3
4
5
6
7
8

41

Table 9- Module flatness specifications
Module Flatness (mm)Surface Roughness (Ra,µm)
0.075
1.6
0.075
1.6
0.075
1.6
0.075
1.6
0.050
0.8
0.050
0.8
0.050
0.8
0.050
0.8

QSFP-DD Hardware Rev 5.0

5.5 Module paddle card dimensions

Notes for Module Paddle Card Drawings (Figures
21):(Figures20
21 and 22)
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.

Pre-wipe pads (shaded area) on module card host side are optional
A single split in the pre-wipe signal pad is optional, and if implemented, theresulting 2 pads shall be separated with a gap of 0.13 +/- 0.05
Dimensioning and tolerancing conform to ASME Y14.5-2009
All dimensions are in millimeters
No solder mask within 0.05 mm of all defined contact pad edges.
No solder mask between end contacts and the sides of the paddle card
Datum H is established with Datum Target points at the leading edge of the outermost signal contact pads to be re-established on each side
Dimension applies from the first set of signal pads to the second set of signal pads
Dimension applies from the first set of signal pads to the second set of signal pads
Dimension and tolerance applies to all power pads on both top and bottom side ofpaddle card
Dimension and tolerance applies to all power pads on both top and bottom side ofpaddle card
Dimension and tolerance applies to all power pads on both top and bottom side ofpaddle card
A zero gap is allowed for a continuous pad option
Applies to all signal pad to pad spacing
Pre-wipe pads (shaded area) are required except in continuous power or groundpad
designs
Paddle card thickness is measured over pads vias must not be proud of the padsurface
Minimum dimension required for mating sequence between signal and ground pads
Component keep out area measured from Datum H
Contact pad plating
0.38 micrometers minimum gold over
1.27 micrometers minimum nickel

Alternate contact pad plating
0.05 micrometers minimum gold over
0.30 micrometers minimum palladium over
1.27 micrometers minimum nickel

42

QSFP-DD Hardware Rev 5.0

Figure 21: Module paddle card dimensions

43

QSFP-DD Hardware Rev 5.0

Figure 22: Module pad dimensions

44

QSFP-DD Hardware Rev 5.0

5.6

Module Extraction and Retention Forces

The requirements for insertion forces, extraction forces and retention forces are
specified in Table 10. The QSFP-DD cage and module are designed to ensure that excessive
force applied to a cable does not damage the QSFP-DD cage or host connector. If any partis damaged by excessive force, it should be the cable or media module and not the cage orhost connector which is part of the host system. The contact pad plating shall meet therequirements of Section 5.5.
Table 10- Insertion, Extraction and Retention Forces
Measurement
Min
Max
Units
Comments
QSFP module insertion 0
40
N
QSFP-DD module
090N
insertion
QSFP module
030
N
extraction
QSFP-DD module
050N
extraction
QSFP module retention 90
N/AN
No damage to module below
90N with latch engaged
QSFP-DD module
90
N/A
N
No damage to module below
retention
90N with latch engaged
Cage retention (Latch 125
N/AN
No damage to latch below
strength)
125N
Cage retention in
114
N/A
N
Force to be applied in a
Host Board
vertical direction, no
damage to cage
Insertion/removal
100
N/A
Cycles Number of cycles for thecycles, connector/
connector and cage withcage
multiple modules.
Insertion/removal
50
N/A
Cycles Number of cycles for an
cycles, QSFP-DD
individual module.
moduleNote: Insertion, extraction and retention forces apply with or without thepresence of a riding heat sink.

45

QSFP-DD Hardware Rev 5.0

5.7

2x1 Electrical Connector Mechanical

The QSFP-DD Connector is a 76-contact, right angle connector. The integrated connector ina 2x1 stacked cage is shown in Figure 23 with detailed drawings in Figure 24, Figure 25
and Figure 26. Recommendations for the 2x1 stacked cage bezel opening are shown in Figure
27.

Figure 23: Integrated connector in 2x1 stacked cage46

QSFP-DD Hardware Rev 5.0

Figure 24: 2x1 stacked cage47

QSFP-DD Hardware Rev 5.0

Figure 25: 2x1 stacked cage dimensions

48

QSFP-DD Hardware Rev 5.0

Figure 26: Connector pins in 2x1 stacked cage as viewed from the front

Figure 27: 2x1 Bezel Opening
49

QSFP-DD Hardware Rev 5.0

Figure 28: 2X1 host board connector contacts

5.7.1 2x1 Connector and Cage host PCB layout
A typical host board mechanical layout for attaching the QSFP-DD 2x1 Connector and Cagesystem is shown in
Figure 28 and Figure 29. Location of the pattern on the host board is application
specific. To achieve 25-50 Gbps performance pad dimensions and associated tolerances must
be adhered to and attention paid to the host board layout.

50

QSFP-DD Hardware Rev 5.0(Figure 29):

51

QSFP-DD Hardware Rev 5.0----

Figure 29: 2X1 Host PCB Mechanical Layout
52

QSFP-DD Hardware Rev 5.0+

5.8

Surface Mount Electrical Connector Mechanical

The QSFP-DD Connector is a 76-contact, right angle connector. The SMT connector in a 1xn
cage is shown in Figure 30 with detailed drawings in Figure 31 andFigure 32. Recommendations for the SMT cage bezel opening are shown in Figure 33.

Figure 30: SMT connector in 1xn cage53

QSFP-DD Hardware Rev 5.0

54

QSFP-DD Hardware Rev 5.0

55

QSFP-DD Hardware Rev 5.0

56

QSFP-DD Hardware Rev 5.0

Figure 31: SMT 1x1 Cage Design

57

QSFP-DD Hardware Rev 5.0

Figure 32: SMT 1x1 Connector Design
Note: Contact Pin Dimension Measured from Datum T

58

QSFP-DD Hardware Rev 5.0

Figure 33: SMT 1x1 bezel opening

59

QSFP-DD Hardware Rev 5.0

5.8.1 Surface mount connector and cage host PCB layout
A typical host board mechanical layout for attaching the QSFP-DD surface mount Connector
and Cage System is shown in Figure 34 andFigure 35. Location of the pattern on the host board is application specific.
To achieve 25-50 Gbps performance pad dimensions and associated tolerances must be
adhered to and attention paid to the host board layout.

Figure 34: SMT Host PCB Mechanical Layout
60

QSFP-DD Hardware Rev 5.0

Figure 35: SMT Connector and Host PCB Pin Numbers

61

QSFP-DD Hardware Rev 5.0

5.9 Module Color Coding and LabelingAn exposed feature of the QSFP-DD module (a feature or surface extending outside of thebezel) shall be color coded as follows:
Beige for 850nm
Blue for 1310nm
White for 1550nm
Each QSFP-DD module shall be clearly labeled. The complete labeling need not be visible
when the QSFP-DD module is installed and the bottom of the device is the recommended
location for the label. Labeling shall include:
Appropriate manufacturing and part number identification
Appropriate regulatory compliance labeling
A manufacturing traceability code
The label should also include clear specification of the external port characteristics
such as:Optical wavelength
Required fiber characteristics (i.e. MMF/SMF)
Operating data rate
Interface standards supported
Link length supported
Connector TypeIf required to comply with Section 6.3, a label must be applied to the top externalsurface of the module case, warning of high touch temperature.
The labeling shall not interfere with the mechanical, thermal or EMI features.

62

QSFP-DD Hardware Rev 5.0

5.10

Optical Interface

Eight examples of the QSFP-DD optical interface port are a male MPO receptacle (seeFigure 37, Figure 38 and Figure 39), a dual LC (see Figure 40), a CS connector (seeFigure 41), a SN receptacle (see Figure 39), or a MDC receptacle (see Figure 40). The
recommended location and numbering of the optical ports for each of the Media Dependent
Interfaces is shown in Figure 36. The transmit and receive optical lanes shall occupy the
positions depicted in Figure 36 when looking into the MDI receptacle with the connector
keyway feature on top.
Note: For some CS, SN, and MDC use cases, less connector ports may be needed. In thesecases, Port # 1 is always the left-most port. Successive ports then follow sequentiallyfrom left-to-right as shown.

63

QSFP-DD Hardware Rev 5.0

SN BiDi
Tx1
Rx2

Optical Signal Names
SN Ferrule Names

Tx3
Rx4

Tx5
Rx6

TR1

TR2

TR3

TR4

RT1

RT2

RT3

RT4

Tx7
Rx8

λ1
λ2

Rx1
Tx2

Rx3
Tx4

Rx5
Tx6

Rx7
Tx8

λ1
λ2

Tx1
Rx2

Tx3
Rx4

Tx5
Rx6

Tx7
Rx8

λ1
λ2

Rx7
Tx8

λ1
λ2

Optical Signal Names

MDC BiDi
Optical Signal Names
MDC Ferrule Names
Optical Signal Names

TR1

TR2

TR3

TR4

RT1

RT2

RT3

RT4

Rx1
Tx2

Rx3
Tx4

Rx5
Tx6

Note: For some CS, SN, and MDC use cases, less connector ports may be needed. In thesecases, Port #1 is always the left-most port. Successive ports then follow sequentiallyfrom left-to-right as shown.
Figure 36: Optical Media Dependent Interface port assignments

64

QSFP-DD Hardware Rev 5.0
5.10.1MPO Optical Cable connections
The optical plug and receptacle for the MPO-12 connector is specified in TIA-604-5 andshown in Figure 37 (MPO-12 Single Row)and Figure 39 (MPO-12 Two Row). The optical plugand receptacle for the MPO-16 connector is specified in TIA-604-18 and shown in Figure 38(MPO-16 Single Row). Note: This specification uses the terms MPO-12 in place of the TIA
term MPO and MPO-12 Two Row in place of the TIA term MPO Two Row.
Aligned keys are used to ensure alignment between the modules and the patchcords. The
optical connector is orientated such that the keying feature of the MPO receptacle is on
the top. Note: Two alignment pins are present in each receptacle.

Figure 37: MPO-12 Single Row optical patch cord and module receptacle

65

QSFP-DD Hardware Rev 5.0

Figure 38: MPO-16 Single Row optical patchcord and module receptacle

Figure 39: MPO-12 Two Row optical patchcord and module receptacle66

QSFP-DD Hardware Rev 5.0

5.10.2
Dual LC Optical Cable connection
The Dual LC optical patchcord and module receptacle is specified in TIA-604-10 and shownin Figure 40.

Figure 40: Dual LC optical patchcord and module receptacle

5.10.3
Dual CS Optical Cable connection
The Dual CS optical receptacle for a QSFP-DD module is specified in CS-01242017 (seeIndustry Documents) and shown in Figure 41.

Figure 41: Dual CS connector module receptacle (in support of breakout applications)67

QSFP-DD Hardware Rev 5.0

5.10.4
SN Optical Cable connections
The SN optical connector and receptacle for QSFP-DD module is specified in SN-60092019
and shown in Figure 42. The top key and offset bottom key are used to ensure alignment
between the modules and the patch cords.

Figure 42: SN optical connector plug and four-port module receptacle

5.10.5MDC Optical Cable connection
The MDC optical plug and receptacle for a QSFP-DD module is specified in USC-11383001 andshown in Figure 43. The optical connector is orientated such that the keying feature of
the MDC receptacle is on the top.

Figure 43: MDC optical connector plug and four-port module receptacle68

QSFP-DD Hardware Rev 5.0
5.10.6
Electrical data input/output to optical port mapping
Table 11 defines the mapping of electrical TX data inputs and Rx data outputs to optical
ports. Note that there is no defined mapping of electrical input/output to optical
wavelengths for WDM applications.
Table 11- Electrical Signal to Optical Port Mapping
Optical Port Type (see Figure 36)
LC, CS,
MPO-12, CS,
MPO-12, SN,
MPO-12 (two row)
MPO-12, SN, MDC
SN, MDCSN, MDCMDC
MPO-16BiDi
1 TX fiber
2 TX fibers
4 TX fibers
8 TX fibers
8 Tx (Rx) fibers2
1 RX fiber1 2 RX fibers1
4 RX fibers1
8 RX fibers1
Tx1
TX-1
TX-1
TR1
Tx2
TX-2
RT1
TX-1
Tx3
TX-2
TX-3
TR2
TX-1
Tx4
TX-4
RT2
Tx5
TX-3
TX-5
TR3
Tx6
TX-6
RT3
TX-2
Tx7
TX-4
TX-7
TR4
Tx8
TX-8
RT4
Rx1
RX-1
RX-1
RT1
Rx2
RX-2
TR1
RX-1
Rx3
RX-2
RX-3
RT2
RX-1
Rx4
RX-4
TR2
Rx5
RX-3
RX-5
RT3
Rx6
RX-6
TR3
RX-2
Rx7
RX-4
RX-7
RT4
Rx8
RX-8
TR4
Note 1: TX-n or RX-n where n is the optical port number as defined in Figure 36.
Note 2: TRn or RTn where n is the optical port number as defined in Figure 36.
Note: For some CS, SN, and MDC use cases, less connector ports may be needed. In thesecases, Port #1 is always the left-most port. Successive ports then follow sequentially fromleft-to-right as shown in Figure 36
Electrical
Signal69

QSFP-DD Hardware Rev 5.0

6 Environmental and Thermal
QSFP-DD is designed to allow for up to 36 modules; stacked, ganged and/or belly-to-belly
in a 1U 19" rack, with the appropriate thermal design for cooling/airflow.
The equipment supplier is responsible for controlling the module case temperature to thespecified range. The module supplier is responsible for defining a point on the modulecase where the temperature is measured. This should be a point connected to an internal
component with the least thermal margin, e.g. a laser diode. It is recommended that thedefined point on the module case be behind the equipment faceplate in order to enable insystem monitoring.

6.1 Thermal Requirements
The module case temperature may be within one or more of the case temperatures ranges
defined in Table 12. The temperature ranges are applicable between 60 m below sea leveland 1800m above sea level, utilizing the host systems designed airflow. For further
information see Telcordia GR-63-CORE, Issue 5, December 2017, NEBSTM Requirements:
Physical Protection.
Table 12- Temperature Range Class of operation
Class
Module Case TemperatureStandard
0°C through 70°C
Extended-5°C through 85°C
Industrial-40°C through 85°C

6.2 Thermal Requirements – tighter controlled environments
The classes in Table 13 are intended for tighter controlled environments, e.g. data
center environments as described in “Thermal guidelines for data processing
environments”, fourth Ed., ASHRAE, 2015. The four classes correspond to different rangesof equipment intake air temperature.

Table 13- Temperature Range Classes for Tighter Controlled Applications

Class
A1
A2
A3
A4

Module Functional Case
Temperature1
15°C to 62°C
10°C to 65°C
5°C to 70°C
5°C to 75°C

Module Performance
Case Temperature1
25°C to 62°C
20°C to 65°C
15°C to 70°C
15°C to 75°C

Note 1: Functional includes all features available in Low Power Mode.
Performance means all specifications are met in high power mode.

6.3 External Case and Handle Touch Temperature
For all power classes, all module case and handle surfaces outside of the cage mustcomply with applicable touch temperature requirements. If the module case temperature
will exceed applicable short-term touch temperature limits, a means must be provided toprevent contact with the case during unlatching and removal. Figure 11, Figure 12 andAppendix A show typical handles used to unlatch and remove the module, thereby limiting
contact with the module case. Handles are typically low thermal conductivity elastomer
and allow for a higher touch temperature. For more information see “IEC/UL 60950-1
Requirements for Information Technology Equipment” and “Telcordia GR-63-CORE, Issue 5,
December 2017, NEBSTM Requirements: Physical Protection”.
70

QSFP-DD Hardware Rev 5.0

7Management Interface

A management interface, as already commonly used in other form factors like QSFP, SFP,
and CDFP, is specified in order to enable flexible use of the module by the user. The
memory map for QSFP-DD is found in the 'Common Management Interface Specification for
8x/16x pluggable transceivers' (see www.QSFP-DD.com). Some timing requirements are
critical, especially for a multi-channel device, so the interface speed may optionally be
increased. Byte 00h on the Lower Page or Address 128 Page 00h is used to indicate theuse of the QSFP-DD memory map rather than the QSFP memory map. When a legacy QSFP28
module is inserted into a QSFP-DD port the legacy QSFP memory map (i.e. SFF-8636) must be
used. This case is outside the scope of this document.
In some applications, muxing or demuxing may occur in the module. In this specification,
all references to channel numbers are based on the electrical connector interface
channels, unless otherwise indicated. In cases where a status or control aspect isapplicable only to channels after muxing or demuxing has occurred, the status or control
is intended to apply to all channels in the mux group, unless otherwise indicated.

7.1

SCL, SDA and ModSEL Timing Specification

7.1.1 Introduction
Low speed signaling is based on Low Voltage CMOS (LVCMOS) operating at Vcc. Hosts shalluse a pull-up resistor connected to Vcc_host on the 2-wire interface SCL (clock) and SDA(Data) signals. Detailed electrical specifications are given in section 4.1.2.
Nomenclature for all registers more than 1 bit long is MSB-LSB.

7.1.2 Management Interface Timing Specification
The timing requirements are shown in Figure 44 and specified in Table 14.
QSFP-DD is positioned to leverage 2-wire timing (Fast Mode devices) to align the use of
related cores on host ASICs. The default clock rate is a maximum of 400 kHz with an
option to support up to a maximum of 1 MHz. This subsection closely follows the QSFP SFF8636 specification.

71

QSFP-DD Hardware Rev 5.0

Figure 44: QSFP-DD Timing Diagram

The 2-wire serial interface address of the QSFP-DD module is 1010000X (A0h). In order toallow access to multiple QSFP-DD modules on the same 2-wire serial bus, the QSFP-DD
includes a module select pad, ModSelL. This input (which is pulled high, deselected in
the module) must be held low by the host to select the module of interest and allow
communication over the 2-wire serial interface. The module must not respond to or accept
2-wire serial bus instructions unless it is selected.
Before initiating a 2-wire serial bus communication, the host shall provide setup time on
the ModSelL line of all modules on the 2-wire bus. The host shall not change the ModSelL
line of any module until the 2-wire serial bus communication is complete and the holdtime requirement is satisfied.

7.1.3

Serial Interface Protocol

7.1.3.1 Management Timing Parameters
The timing parameters for the 2-Wire interface to the QSFP-DD module and the QSFP-DD
memory transaction timings are shown in Table 14. Tradeoffs between pull-up resistor
values, bus capacitance and rise time are shown in Figure 45.

72

QSFP-DD Hardware Rev 5.0

Figure 45: SDA/SCL options for pull-up resistor, bus capacitance and rise/fall times73

QSFP-DD Hardware Rev 5.0

Parameter
Clock Frequency
Clock Pulse Width
Low
Clock Pulse Width
High
Time bus free
before newtransmission canstart
START Hold Time

Table 14- Management Interface timing parameters
Fast Mode Fast Mode
(400 kHz) Plus (1 MHz)
SymbolMin Max
Min
Max
Unit Conditions
fSCL
0
400
0
1000
kHz
tLOW
1.3
0.50
µs
tHIGH

0.6

0.26

µs

tBUF

20

1

µs

Between STOP and START and
between ACK and ReStart

tHD.STA

0.6

0.26

µs

START Setup Time

tSU.STA

0.6

0.26

µs

The delay required between SDA
becoming low and SCL starting
to go low in a STARTThe delay required between SCL
becoming high and SDA starting
to go low in a START

Data In Hold Time
Data In Setup Time
Input Rise Time

tHD.DATtSU.DAT
tR

0
0.1

0
0.1

Input Fall TimetF

STOP Setup Time
STOP Hold Time
Aborted sequence –bus releasetSU.STOtHD.STO
Deselect_Abort0.6
0.6

ModSelL Setup Time1tSU.
ModSelL22

ms

ModSelL Hold Time1tHD.
ModSelL22

ms

Serial Interface
Clock Holdoff“Clock Stretching”

T_clock_
hold

300

120

µs
µs
ns

300

120

ns

2

µs
µs
ms

0.26
0.26
2

500

500

us

From (VIL,MAX=0.3*Vcc) to(VIH, MIN=0.7*Vcc)
From (VIH,MIN=0.7*Vcc) to(VIL,MAX=0.3*Vcc)

Delay from a host de-asserting
ModSelL (at any point in a bus
sequence) to the QSFP-DD
module releasing SCL and SDA
ModSelL Setup Time is the
setup time on the select line
before the start of a host
initiated serial bus sequence.
ModSelL Hold Time is the delay
from completion of a serial bus
sequence to changes of module
select status.
Maximum time the QSFP-DD
module may hold the SCL line
low before continuing with aread or write operation
Complete Write of up to 8
Bytes

Complete Single
tWR
80
80
ms
or Sequential
Write to nonvolatile registers
Accept a single or tNACK80
80
ms
Time required for the module
sequential write
to accept a single or
to volatile
sequential write to volatilememory.
memory.
Endurance (Write
50K
50k
cycl Module Case Temperature = 700 C
Cycles)es
Note 1: When the host has determined that module is QSFP-DD, the management registers can beread to determine alternate supported ModSelL set up and hold times.

74

QSFP-DD Hardware Rev 5.0

Appendix A

Informative overall module length with elastomeric handle

Figure 46 and Figure 47 show flexible elastomeric handles attached to the module latches.
Handle ends for Types 1 and Type 2 modules should be aligned independent of module caseextension. Type 1 modules should meet the overall length of 118mm maximum per Figure 46
with a handle length of approximately 50mm. Type 2 modules should comply with Figure 47
and have reduced handle length equal to the module case length extension

Figure 46: Informative overall module length with handle for Type 1 module

Figure 47: Informative overall module length with handle for Type 2 and Type 2A modules

75

QSFP-DD Hardware Rev 5.0

Appendix B

Module Type 2A Heat Sink Examples

This appendix contains examples of designs for higher power Type 2A modules with heatsinks.
Thermal design is system dependent; however, systems seeking to maximize the benefit of
the external heat sink of Type 2A modules should consider minimizing bypass of airflow
through the external heat sink. One potential method is to use a minimal gap between theouter surface of the front panel and the trailing edge of the external heat sink fins asshown in Appendix B, Figure B-1 below.

Figure B-1: Type 2A example module insertion76

QSFP-DD Hardware Rev 5.0

Figure B-2: Type 2A example 1X1 bezel design77

QSFP-DD Hardware Rev 5.0

Figure B-3: Type 2A example 2X1 bezel design

78

QSFP-DD Hardware Rev 5.0

Figure B-4: Type 2A Extruded Heat Sink Example

79

QSFP-DD Hardware Rev 5.0

Figure B-5: Type 2A Die Cast Heat Sink with Metal Cover Example
80

QSFP-DD Hardware Rev 5.0

Figure B-6: Type 2A Zipper Fin Heat Sink Example

81

QSFP-DD Hardware Rev 5.0

End ofDocument82