Application Note

AN2027

Using the PSoC Microcontroller External Crystal Oscillator
By: Jeff Dahlin
Associated Project: No
Associated Part Family: CY8C25xxx, CY8C26xxx

Summary
The External Crystal Oscillator in the PSoC™ device has specific requirements for correct operation indifferent configurations. This Application Note details these requirements.

Introduction

External Crystal Oscillator Basics

The PSoC device’s External Crystal Oscillator(ECO) can be used directly as the reference fortime keeping or other low speed (<32 kHz)
operations. It can also act as the reference forthe phase-lock looped mode of the Internal Main
Oscillator (IMO) for operations that require anaccurate higher speed clock, such as DTMF
generation and serial communications. Optimal
performance from the ECO for each of thesefunctions requires different external components
and different control register settings.

The source for the PSoC 32K clock can be thelow accuracy Internal Low-speed Oscillator (ILO)or the higher accuracy External Crystal Oscillator(ECO). The 32K Select bit of the Oscillator
Control 0 Register (OSC_CR0) determines whichsource is used. The simplest way to set this bit isto set the “32K_Select” parameter in the Global
Resources grid of PSoC Designer to “External”(highlighted in Figure 1).
The ECO drive circuitry must be connected to a32,768 Hz watch crystal through the XTALIn andXTALOut pins of the PSoC MCU.
The XTALIn and XTALOut pins must have theirdrive modes set to High Z (highlighted in Figure2) for the ECO to work properly. If the pins’ drive
modes are not set to High Z, the drive circuitry
will free-run at an incorrect frequency.

Figure 1: 32K_Select Setting for ECO Operation
Figure 2: XTALIn and XTALOut Pin Drive Settings
for ECO Operation

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ECO Operation
The ECO operates as a low power oscillator. To
accomplish this it is designed as a low-amplitude,high-impedance analog circuit. It should betreated as such when placing the components
and designing the circuit. Layout is important toperformance. Also note that the presence ofcontaminants on the PCB can impact theperformance of the oscillator.
The crystal and the feedback capacitors shouldbe placed as close as is practical to the pins ofthe microcontroller and should be placed over acommon-ground plane. High-speed digital signals(signals with fast fall and rise times) should not
be routed close to the ECO circuit. Also, digital
signals should not be routed through the ECO
external components. When possible, the pins
immediately adjacent to the ECO pins should beleft unconnected, or they should have lower
speed signals connected to them.

The board capacitance will depend on PCB
geometry, but for example, a layout with 0.20”
long, 0.010” wide traces over a ground plane on
a 4-layer 0.062” thick PCB, has a board parasitic
capacitance of 0.3 pF on each pin.
Table 1 shows standard capacitor values that canbe used for C1 and C2 with the various PSoC
microcontroller packages, assuming the 0.3 pF
board capacitance in the previous example.
Table 1: ECO Capacitor Values for Balanced
Feedback

Package
8 PDIP
20 PDIP
20 SOIC
20 SSOP
28 PDIP
28 SOIC
28 SSOP
44 TQFP48 PDIP
48 SSOP

P1[1]
Vcc

C1Vcc

P1[0]

Vss

32.678 kHz

C1
22 pF
22 pF
22 pF
22 pF
22 pF22 pF
22 pF
22 pF
20 pF
22 pF

C2
22 pF
22 pF
22 pF
22 pF
22 pF
22 pF
22 pF
22 pF
20 pF
22 pF

ECO and PLL Lock Mode

C2Figure 3: ECO Crystal Connections

Notice that in Figure 3, the feedback capacitors
are shown connected to Vcc. This is the optimal
configuration because the ECO driver isreferenced to Vcc. If the capacitors are incorrectly
connected to Vss, the ECO will operate at thecorrect frequency, but will be slightly more
susceptible to power supply noise.
For standard ECO operation (when not being
used as a reference for the Internal Main
Oscillator PLL), the configurations described inthe CY8C25xxx/26xxx Family Data Sheet should
be used.
32.768 kHz, 12.5 pF, 1µW watch crystal
NPO ceramic capacitors
C1 = C2 = 25 pF – CP – CB
Where C1 and C2 are the ECO feedback crystals
shown in Figure 3, CP is the package capacitanceand CB is the board capacitance.
The package capacitances for the various PSoC
device packages can be found in the Clocking
section of the CY8C25xxx/26xxx Data Sheet.

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Typical CP0.9 pF
2.0 pF
1.0 pF0.5 pF
2.0 pF
1.0 pF0.5 pF0.5 pF
5.0 pF0.6 pFThe Internal Main Oscillator (IMO) can beconfigured to Phase Lock Loop (PLL) to theECO. This will result in an IMO with moreaccurate frequency and less voltage andtemperature drift than can be accomplished withthe Internal Main Oscillator alone.
When using the PLL configuration of the IMO, anunbalanced feedback capacitor configuration anda local bypass capacitor, as described in thefollowing sections, must be used for proper
operation.
The PLL Mode bit of the OSC_CR0 register
enables the PLL lock mode of the IMO. The
simplest way to set this bit is to set the“PLL_Mode” parameter to “Ext Lock” in theGlobal Resources window of PSoC Designer(highlighted in Figure 4).
In general, a PLL requires a low-jitter reference inorder to remain stable, and because the PSoC
microcontroller’s ECO uses a low-amplitude
signal, the presence of noise will cause theposition of the clock edges to jitter from cycle tocycle. The base frequency of the ECO will remain
accurate but the jitter can cause the IMO to beunstable.

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When using the PLL mode of the Internal Main
Oscillator (IMO), PCB layout is the most criticalfactor in minimizing jitter on the ECO. By carefully
designing the PCB, the amount of noise present
in the ECO circuit can be minimized. But there
are other required changes that increase thestability of the ECO. These include using
unbalanced feedback capacitors, providing alocal Vcc bypass, and increasing the ECO drive
current.

C P1.0 = C 2 + C B + C P
Equation 2: XTALOut (Port 1, Pin 0) CapacitanceFor this configuration, the total capacitance onthe XTALOut (Port 1, Pin 0) should be near 100
pF. Equation 3 shows the total capacitance at theXTALOut pin (CP1.0) if a 100 pF capacitor is used.

C P1.0 = 100 pF + C P + C B 0Equation 3: XTALOut (Port 1, Pin 0) Capacitance(Where CP is the package capacitance and CB0 is theboard parasitic capacitance on XTALOut.)The feedback capacitor at the XTALIn pin should
be calculated so that the series capacitance atthe crystal pins totals 12.5 pF. Equation 4 shows
the calculation for the ideal value of C1 (thecapacitor on P1[1] XTALIn).

C1 =(C 2 + C P + C B 0 ) ⋅ 12.5 pF− C P − C B1
(C 2 + C P + C B 0 ) − 12.5 pF

Equation 4: XTALIn (Port 1, Pin 1) Capacitance(Where CP is the package capacitance and CB1 is theboard parasitic capacitance on XTALIn.)

Table 2 lists typical package capacitances, andstandard capacitor values for C1 and C2 closest
to the calculated ideal values for various
packages. Board parasitic capacitance values of0.3 pF were used in these calculations.

Figure 4: PLL_Mode Setting for IMO Operation

Use of Unbalanced FeedbackCapacitors
By using an unbalanced pair of feedback
capacitors, the amplitude of the input signal canbe increased. This will reduce the ECO’s noise
susceptibility. In this case, the series capacitanceof the feedback capacitors still needs to be 12.5
pF. An unbalanced pair of capacitors will cause
an increase in the operating current and will not
improve the performance of the ECO, so thischange is not recommended for standard ECO
operation.

Table 2: ECO Capacitor Values for Unbalanced
Feedback

Package
8 PDIP
20 PDIP
20 SOIC
20 SSOP
28 PDIP
28 SOIC
28 SSOP
44 TQFP48 PDIP
48 SSOP

The capacitance on each pin is comprised of thepackage capacitance, in parallel with the board
parasitic capacitance, in parallel with the external
capacitor (see Equations 1 and 2).

C P1.1 = C1 + C B + C P

Typical CP
0.9 pF
2.0 pF
1.0 pF0.5 pF
2.0 pF
1.0 pF0.5 pF0.5 pF
5.0 pF0.6 pF

C112 pF
12 pF
12 pF
12 pF
12 pF
12 pF
12 pF
12 pF
9 pF
12 pF

C2
100 pF100 pF100 pF100 pF100 pF100 pF100 pF100 pF100 pF100 pFAn error of 1 pF in C1 or C2 will result in about
3 ppm of additional error in the output frequency.

Equation 1: XTALIn (Port 1, Pin 1) Capacitance

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Provide a Local Bypass
When using the PLL configuration of the IMO
additional filtering of the Vcc power is required.
For this purpose a local Vcc bypass capacitor isadd at the XTALIn pin (Port 1, Pin 1). To do this,configure the pin’s drive mode to be Strong andwrite a 1 to the Data Register (PRT1DR).
Connect the pin to Vcc and connect a 0.1 µF
capacitor between the pin and Vss. This willconnect the internal power bus to Vcc through thepin pull-up FET; providing a local low impedanceconnection to Vcc.

CBypassVcc
VssC1

P1[0]

32.678 kHz

1.
2.
3.

C2

Figure 5: PLL_Mode Connections

Increase the ECO Drive Current
To increase the drive current of the ECO circuit,write a 0x0F to the ECO Trim register (ECO_TR,Bank 1, 0x0F). This is done automatically byboot.asm when the “PLL_Mode” parameter is set
to “Ext Lock.”

Starting the IMO PLL Mode

The current version of boot.asm (PSoC Designer
version 3.20) holds off entry to main( ) until theclocks are stable. This means that calling main
will be delayed about one second when using theECO. The following delays are present inboot.asm:
1.

Start-up Requirements
Both the ECO and the IMO experience periods ofinstability when they are first started. Because ofthis, the output of the ECO should not be used asa source for the internal 32K clock or as areference for the PLL mode of the IMO until it has
had time to stabilize. Additionally, the CPU clock
speed must be lowered when the IMO is initiallyswitched to PLL mode to prevent the CPU clockfrom exceeding its operational limit.
These circumstances require the ECO and theIMO PLL mode to follow a specific start-up
sequence. boot.asm meets this requirement if theappropriate settings are selected in the Global
Resources grid in Device Editor of PSoC
Designer.

Starting the ECO
When the ECO is first enabled, its output is notconnected to the 32K clock tree within the PSoC
microcontroller. Instead, the 32K clock continues
to be driven by the Internal Low-speed Oscillator(ILO) until the Sleep Timer reaches terminal
count. With this mechanism, the Sleep Timer isused to delay connecting to the ECO until its
output has stabilized.

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The Sleep Timer should be set to 1
second and cleared. (The Sleep Timer
Interrupt does not have to be enabled.)
The ECO should be enabled (set the32K Select bit of OSC_CR0 to 1).
After the Sleep Timer reaches terminal
count, the ECO can be used as clock
source for event timing.

The IMO cannot be phase locked to the ECO
until the ECO is stable – approximately one
second. Also, there is a maximum CPU clockfrequency restriction (3 MHz) that cannot beexceeded when starting PLL mode. Both of theserestrictions are in place to prevent the CPU clock
frequency from temporarily exceeding 12 MHz for
3 V operation (or 24 MHz for 5 V operation).

Vcc

P1[1]

The steps listed below are followed by boot.asm
when starting the ECO:

2.

Whenever the ECO is enabled, a onesecond delay is added in order to wait for
the ECO to become stable.
Whenever the PLL lock mode of the IMO
is enabled, a 16 msec delay is added inorder to wait for the IMO frequency tostabilize prior to setting the CPU clock
frequency to the designer’s setting.

To accurately provide these delays, boot.asm
uses the Sleep Timer, but does not enable theinterrupt. Therefore, boot.asm no longer contains
a Sleep Timer Interrupt Service Routine (ISR). Ifa designer needs to add a Sleep Timer ISR, it isrecommended that one be created in a separate
source code file.
Previous versions of PSoC Designer provided avariable, ClockNotStable, which indicatedwhen the clocks were stable. Because main( ) is
now not called until the clocks are stable, thisvariable is no longer provided.
If some tasks must be accomplished before the1-second period is expired, initialization code
could be added to boot.asm, or a designer could
chose to write their own clock-initialization code
as long as the rules in this section are held to.

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Notes
1.

Setting
the“32K_Select”
GlobalResource to “Internal” and “PLL_Mode”
Global Resource to “External Lock” is aninvalid configuration. There is noconnection from the Internal Low-speed
Oscillator to the Internal Main Oscillator(see the Clock Tree diagram in the
CY8C25xxx/26xxx Family Data Sheet).

2.

The XTALIn and XTALOut pins are also
usedfortheIn-System
SerialProgramming. The pins can beconfigured to function for both
operations in the same design. See
Application Note AN2014, Design for InSystem Serial Programming (ISSP ),for more information on In-System
Programming.

Cypress MicroSystems, Inc.
22027 17th Avenue S.E. Suite 201
Bothell, WA 98021
Phone: 877.751.6100
Fax: 425.939.0999
http://www.cypressmicro.com/ / http://www.cypress.com/aboutus/sales_locations.cfm / support@cypressmicro.com
Copyright  2002-2003 Cypress MicroSystems, Inc. All rights reserved.
PSoC™ (Programmable System on Chip) is a trademark of Cypress MicroSystems, Inc.
All other trademarks or registered trademarks referenced herein are property of the respective corporations.
The information contained herein is subject to change without notice.

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Revision D-5-