IEEE Std 1355-1995

IEEE Standard for HeterogeneousInterConnect (HIC) (Low-Cost,
Low-Latency Scalable Serial Interconnect
for Parallel System Construction)

SponsorBus Architecture Standards Committeeof theIEEE Computer Society
Approved 21 September 1995

IEEE Standards Board

Abstract: Enabling the construction of high-performance, scalable, modular, parallel systems with low
system integration cost is discussed. Complementary use of physical connectors and cables, electricalproperties, and logical protocols for point-to-point serial scalable interconnect, operating at speeds of 10–
200 Mb/s and at 1 Gb/s in copper and optic technologies, is described.
Keywords: flow control, encoding schemes, OMI/HIC, packet routing, parallelism, point-to-point serial
scalable interconnect, protocols, routing fabric, serial links, serialization, silicon integration, switch chip,transaction layer, wormhole routing
The Institute of Electrical and Electronics Engineers, Inc.
345 East 47th Street, New York, NY 10017-2394, USA
Copyright © 1996 by the Institute of Electrical and Electronics Engineer, Inc.
All rights reserved. Published 1996. Printed in the United States of America.
ISBN 1-55937-595-7
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iiIntroduction[This introduction is not part of IEEE Std 1355-1995, IEEE Standard for Heterogeneous InterConnect (HIC) (Low-Cost, LowLatency Scalable Serial Interconnect for Parallel System Construction).]The construction of high-performance systems with parallel communications, parallel processing, and/or parallel I/Odemands a fast, low-cost, low-latency interconnect. It must be fast and low-latency, otherwise it will be the limiting
factor in system performance; and it must be low-cost, or it will dominate the system cost. It must also scale well inboth performance and cost relative to the system size, otherwise highly parallel systems will be limited in performanceor too expensive. Existing standards do not meet these criteria, because they are designed for communication over long
distances (which incurs high costs), or because they aim at the extreme of currently achievable performance (which
again increases costs), or because they are based on a restricted model such as a bus, which limits overall performanceand scalability. A detailed rationale for this standard is given in annex D.
This standard has been developed to complement recent technical developments of highly integrated, low powerinterconnect technology implemented in high volume commodity VLSI processes, and to exploit the simplifications in
encodings and protocols resulting from the use of relatively reliable media over relatively short distances. Aspects ofthe baseline for this standard have their origins in work on parallel systems, which has taken place in a number of
ESPRIT projects. In particular, the routing strategy was established in the PUMA project, and the DS-Links weredeveloped partially in the GP MIMD project. Work at interconnect for high performance mainframe computers at Bull
led to the development of the gigabit link technology implemented in Bi-CMOS and CMOS processes. More recently,
these developments, together with corresponding optical technology, have been brought together in the OMI/HIC
Project (Open Microprocessor Systems Initiative—High Performance Heterogeneous Interconnect—ESPRIT 7252).
Note: Attention is called to the possibility that implementation of this standard may require use of subject mattercovered by patent rights. By publication of this standard, no position is taken with respect to the existence or validityof any patent rights in connection therewith. The IEEE shall not be responsible for identifying all patents for which alicense may be required by an IEEE standard or for conducting inquiries into the legal validity or scope of those patents
that are brought to its attention.
The patent holder has, however, filed a statement of assurance that it will grant a license under these rights withoutcompensation or under reasonable rates and nondiscriminatory, reasonable terms and conditions to all applicants
desiring to obtain such a license. The IEEE makes no representation as to the reasonableness of rates and/or terms andconditions of the license agreement offered by the patent holder. Contact information may be obtained from the IEEE
Standards Department.
This standard has been developed with the efforts of many volunteers. The following is a list of those who attended
Working Group meetings while the draft and final standard documents were compiled:
Colin Whitby-Strevens, Chair
Roland Marbot, (Co-Chair)
Andrew Coffer, Editor
Harry Andreas
Noriaki Arikawa
Dan AterTon Balhaar
Edmund H. Baulsir
Harrison BeasleyRalf Bokämper
Thierry Brizard
Joe Brown
Richard Carlson
Stephen J. Cecil

Jean Jacques Chaput
Michael Christ
Chip Coffin
Stefan De Troch
Jean-Merri De Vanssay
Gerry Desmody
Ian Dobson
Jean Jacques Dumont
Mike Foster
David Franklin
Bob Gannon

Stein Gjessing
Oystein Gran Larsen
Howard Gurney
Claes-Göran Gustavsson
Stefan Haas
Brian Henderson
Geoffrey Hilton
Roger Hinsdale
Geir Horn
Shinichi Iwano
Ed Jacquesiii

Bjørn Johnsbråten
Anatol KaganovichThomas Kessler
Jangkyung Kim
Terry Kingham
Bill Kirk
Matthew Kirwan
Ernst Kristiansen
Alain Lagarde
Falk Langhammer
Craig Lund
Calogero Mantellina
Brian Martin

Kristian Martinson
Paolo Melloni
Michel Monchant
Jonathan Morris
Ken Naumann
Joe Norris
Mats Olstedt
Joar Martin Østby
Sylvain Paineau
Elwood Parsons
David Robak
Eivind Rongved
Pino Rosario

Jouko Saarinen
Yasuo Sasaki
Michael Scottp
Tor Skeie
Nobuaki SugiuraPeter Thompson
Joe Trainor
Toine van Laarhoven
Rob Volgersp
Richard Wagner
Paul Walker
Alan Welzel
David L. Wright

Bruno Houssay
Reza Nezamzadeh

James Wolffe
Bin WuContributions have also been received from:
Yogindra Abhyankar
Dave Cormie

The following persons were on the balloting committee:
Ghassan Abbas
Malcom Airst
Harry Andreas
Keith Anthony
James Barnette
Edmund Baulsir
Harrison Beasley
Christos Bezirtzoglou
Harold Blatter
Timothy Boggess
Ralf Bokämper
John Brightwell
Charles Brill
Chris Brown
Joe Brown
Trevor Carden
Richard Carlson
Yoon Chang
Andy Cheese
C. ChenMichael Christ
Andrew Coffer
Patrick Courtney
Robert Crowder
Robert Dahlgren
Martin Davis
Dante Del Corso
Ian Dobson
Jean-Jacques Dumont
Sourav Dutta
Wayne Fischer
Gordon Force
Bob Gannon

iv

Stein Gjessing
Chuck Grant
Peter Gutgarts
Stefan Haas
Bruno Houssay
Phillip Hughes
Shinichi Iwano
David James
Daniel Jochym
Sherry Johnson
Sun-Moo Kang
Yoshihisa Kawamura
Stephen Kempainen
Jangkyunk Kim
Jan Kindervater
Hans Peter Kraus
Ernst Kristiansen
Thomas Kulesza
Falk Langhammer
Conrad Laurvick
Michael Lazar
Udo Lechner
Rollins Linser
Gary Manchester
Roland Marbot
Joseph Marshall
Brian Martin
Wolfgang Meier
Michel Maillet
Michael Miskin
Yoshiki Mitani
Klaus-Dieter Mueller
Michael Munroe

J. Nicoud
Joe Norris
Daniel O'Connor
Katsuyuki Okada
Fred Orlando
Granville Ott
Elwood Parsons
Mohan Patnaik Lalit
Mira Pauker
Patrick Plancke
Mike Polehn
Brian Ramelson
Douglas Rawson-HarrisDavid RobakFred Rosenberger
Yasuo Sasaki
Frederick Sauer
Rudolf Schubert
Shreyas Shah
Tahir Sheikh
Tor SkeiePaul Slootweg
Nobuaki Sugiura
Michael Teener
Michael Thompson
Peter Thompson
Michael Timperman
Dirk Van de Lagemaat
Richard Wagner
Paul Walker
Thomas Wegmann
Alan Wetzel
Colin Whitby-StrevensJeffrey Wills
James Wolffe
Anthony Wood

J. Robert Wood
Bill Woodruff
David Wright

Bin WuOren Yuen
Janusz Zalewski

When the IEEE Standards Board approved this standard on September 21, 1995, it had the following membership:
E.G. “Al” Kiener, Chair
Donald C. Loughry, Vice Chair
Andrew G. Salem, Secretary
Gilles A. Baril
Clyde R. Camp
Joseph A. Cannatelli
Stephen L. Diamond
Harold E. Epstein
Donald C. Fleckenstein
Jay Forster*
Donald N. Heirman
Richard J. Holleman

Jim Isaak
Ben C. Johnson
Sonny Kasturi
Lorraine C. Kevra
Ivor N. Knight
Joseph L. Koepfinger*
D. N. “Jim” Logothetis
L. Bruce McClung
Marco W. Migliaro

Mary Lou Padgett
John W. Pope
Arthur K. Reilly
Gary S. Robinson
Ingo Rüsch
Chee Kiow Tan
Leonard L. Tripp
Howard L. Wolfman*Member Emeritus
Also included are the following nonvoting IEEE Standards Board liaisons:Satish K. Aggarwal
Richard B. Engelman

Robert E. Hebner
Chester C. Taylor
Lisa S. YoungIEEE Standards Project Editorv

CLAUSE
1.

PAGE

Overview .............................................................................................................................................................1
1.1 Scope .......................................................................................................................................................... 1
1.2 Purpose....................................................................................................................................................... 1

2.

References...........................................................................................................................................................1

3.

Definitions...........................................................................................................................................................3
3.1 General ....................................................................................................................................................... 3
3.2 Glossary ..................................................................................................................................................... 3

4.

Physical media and logical layers .......................................................................................................................6
4.1
4.2
4.3
4.4

5.

DS-SE and DS-DE ............................................................................................................................................14
5.1
5.2
5.3
5.4
5.5
5.6
5.7

6.

Physical medium ...................................................................................................................................... 32
Signal level............................................................................................................................................... 34
TS-FO character level .............................................................................................................................. 36
TS-FO exchange level.............................................................................................................................. 38

HS-SE-10 ..........................................................................................................................................................41
7.1
7.2
7.3
7.4

8.

General ..................................................................................................................................................... 14
DS-SE: physical medium ......................................................................................................................... 14
DS-SE signal level ................................................................................................................................... 15
DS-DE: physical medium ....................................................................................................................... 20
DS-DE signal level................................................................................................................................... 25
DS-SE and DS-DE character level........................................................................................................... 27
DS-SE and DS-DE exchange level .......................................................................................................... 29

TS-FO-02 fiber optic link .................................................................................................................................32
6.1
6.2
6.3
6.4

7.

Physical media ........................................................................................................................................... 6
Logical layers ............................................................................................................................................. 7
Interaction of layers ................................................................................................................................. 10
Implementations defined in the standard ................................................................................................. 12

HS-SE physical medium .......................................................................................................................... 41
HS-SE signal level ................................................................................................................................... 45
HS character level (8B/12B code) ........................................................................................................... 48
HS exchange level.................................................................................................................................... 65

HS-FO-10 fiber optic link .................................................................................................................................73
8.1 Physical medium ...................................................................................................................................... 73
8.2 Signal level............................................................................................................................................... 75
8.3 Character level end exchange level.......................................................................................................... 77

9.

Common packet level........................................................................................................................................77
9.1 General discussion ................................................................................................................................... 77
9.2 Packet format ........................................................................................................................................... 78vi

CLAUSEPAGE

9.3 Networks and routing ............................................................................................................................... 79
9.4 Error detection, recovery, and reporting .................................................................................................. 79
10.

Conformance criteria.........................................................................................................................................79
10.1 Conformance statements .......................................................................................................................... 79
10.2 Definition of subsets ................................................................................................................................ 79
10.3 Conformance statements and cable markings .......................................................................................... 80

Annex A (Normative) DS-DE connector specification ................................................................................................81
Annex B (Normative) HS-SE connector specification .................................................................................................88
Annex C (Normative) TS-FO and HS-FO connector specifications ............................................................................93
Annex D (Informative) Rationale ...............................................................................................................................107
Annex E (Informative) Switch chips, switches, and fabrics .......................................................................................111
Annex F (Informative) Use of the transaction layer—Asynchronous transfer mode (ATM) example ......................112
Annex G (Informative) Error handling .......................................................................................................................121
Annex H (Informative) Flow control calculations......................................................................................................122
Annex I (Informative) Synchronized channel communications .................................................................................124
Annex J (Informative) Example DS-SE driver circuit................................................................................................127
Annex K (Informative) DS-DE optional power supply recommendation ..................................................................129
Annex L (Informative) DS-DE fixed connector PCB recommendation.....................................................................130
Annex M (Informative) DS-DE cable (10 core) recommendation .............................................................................131
Annex N (Informative) DS-DE multiway connector housing recommendation ........................................................132
Annex O (Informative) HS-SE fixed connector PCB recommendation .....................................................................133
Annex P (Informative) HS-SE cable recommendation...............................................................................................134
Annex Q (Informative) HS-SE connector multiway housing recommendation .........................................................135
Annex R (Informative) TS/HS-FO connector PCB and front panel cut-out recommendation...................................136
Annex S (Informative) TS/HS-FO fiber cable recommendation ................................................................................137

vii

IEEE Standard for HeterogeneousInterConnect (HIC) (Low-Cost,
Low-Latency Scalable Serial Interconnect
for Parallel System Construction)

1. Overview

1.1 Scope
The scope of this standard is the physical connectors and cables, electrical properties, and logical protocols for pointto-point serial scalable interconnect, operating speeds of 10–200 Mb/s and at 1 Gb/s in copper and optic technologies[as developed in Open Microprocessor Systems Initiative/Heterogeneous InterConnect Project (OMI/HIC)].

1.2 Purpose
The purpose of this standard is to enable high performance, scalable, modular, parallel systems to be constructed withlow system integration cost; to support communications systems fabric; to provide a transparent implementation of arange of high level protocols [communications (e.g., ATM), message passing, shared memory transactions, etc.], andto support links between heterogeneous systems.

2. References
This standard shall be used in conjunction with the following publications:CISPR 22: 1993, Limits and methods of measurement of radio disturbance characteristics of information technology
equipment. 1
DIN-VDE 0472-517, Testing of cables, wires cords; crosstalk attenuation.2
1

CISPR documents are available from the International Electrotechnical Commission, 3 rue de Varembé, Case Postale 131, CH 1211, Genève 20,
Switzerland/Suisse. CISPR documents are also available in the United States from the Sales Department, American National Standards lnstitute, 11West 42nd Street, 13th Floor, New York, NY 10036, USA.
2DIN documents are available from the Deutsches Institut Füer Normung DIN, Burggrafenstrasse 6, Posffach 1007, 12623 Berlin 30, Germany.

1IEEE Std 1355-1995

IEEE STANDARD FOR HETEROGENEOUS INTERCONNECT (HIC) (LOW-COST, LOW-LATENCY

IEC 48B (Germany) 141, Time domain reflectrometry.
IEC 352-5: 1995, Solderless connections—Part 5.: Solderless press-in connections—General requirements, test
methods and practical guidance.3
IEC 512-2:1985, Electromechanical components for electronic equipment; basic testing procedures and measuringmethods—Part 2.: General examination, electrical continuity and contact resistance tests, insulation tests and voltage
stress tests.
IEC 512-3:1976, Electromechanical components for electronic equipment; basic testing procedures and measuringmethods—Part 3.: Current carrying capacity tests.
IEC 512-4 :1976, Electromechanical components for electronic equipment; basic testing procedures and measuringmethods—Part 4.: Dynamic stress tests.
IEC 512-5 : 1992, Electromechanical components for electronic equipment; basic testing procedures and measuringmethods—Part 5.: Impact tests (free components), static load tests (fixed components), endurance tests and overload
tests.
IEC 512-6 : 1984, Electromechanical components for electronic equipment; basic testing procedures and measuringmethods—Part 6.: Climatic tests and soldering tests.
IEC 512-7 : 1993, Electromechanical components for electronic equipment; basic testing procedures and measuringmethods—Part 7.: Mechanical operating tests and sealing tests.
IEC 512-8 : 1993, Electromechanical components for electronic equipment; basic testing procedures and measuringmethods—Part 8.: Connector tests (mechanical) and mechanical tests on contacts and terminations.
IEC 512-9 : 1992, Electromechanical components for electronic equipment; basic testing procedures and measuringmethods—Part 9.: Miscellaneous tests.
IEC 793-1 :1992, Optical fibres—Part 1.: Generic specifications.
IEC 793-2 :1992, Optical fibres—Part 2.: Product specifications.
IEC 801-4 : 1988, Electromagnetic compatibility for industrial-process measurement and control equipment—Part 4.:
Electrical fast transient/burst requirements (to be replaced by future IEC 1000-4-4 ).
IEC 825-1 : 1993, Safety of laser products—Part 1.: Equipment classification, requirements and user's guide.
IEC 825-2 : 1993, Safety of laser products—Part 2.: Safety of optical fiber communication systems.
IEC 917 : 1988, Modular order for the development of mechanical structures for electronic equipment practices.
IEC 1076-4-101 : 1995, Connectors with assessed quality for use in dc and low frequency analogue applications andin digital applications with high speed data rates. Part 4.: Printed board connectors—Section 101: Sectional
specification.
IEC 1076-4-107 : 1995, Two part connectors for basic grid of 2.0 mm, with free connectors for nonaccessible
insulation displacement termination.
3IEC publications are available from the IEC Sales Department, Case Postale 131, 3, rue de Varembé, CH-1211, Genve 20, Switzerland/Suisse. IEC

publications are also available in the United States from the Sales Department, American National Standards Institute, II West 42nd Street, 13th
Floor, New York, NY 10036, USA.

2

Copyright © 1995 IEEE All Rights Reserved

SCALABLE SERIAL INTERCONNECT FOR PARALLEL SYSTEM CONSTRUCTION)IEEE Std 1355-1995

IEC 1300 —, Fibre optic interconnecting devices and passive components—Basic test and measurement procedures.
IEC 1196-1 :1995, Radio-frequency cables—Specifications—Part 1.: Generic Specification, General Definitions,
Requirements and Test Methods.
IEC 1196-2, Radio-frequency cables—Specifications—Semi-rigid radio-frequency and coaxial cables with
polytetrafluoroethylene (PTFE) insulation—Sectional specification.
IEC 1754-6 :1995 [CDV document 86 B (Secretariat) 473], Fibre optic connector interfaces—Part 6.: Type MU
connector family.
IEEE Std 100-1992 , The New IEEE Standard Dictionary of Electrical and Electronics Terms (ANSI).4
IEEE Std 1301.3-1992, IEEE Standard for Metric Practice for Microcomputers—Convection Cooled with 2.5 mm
Connector (ANSI).
QC 210000: 1987, Connectors for optical fibres and cables. Part 1.: Generic specification.5

3. Definitions

3.1 General
Common terms are as defined in IEEE Std 100-1992. 6 The terms defined in this clause are specific to this standard.
The word shall is used to indicate mandatory requirements strictly to be followed in order to conform with the standard
and from which no deviation is permitted.
The word should is used to indicate that among several possibilities one is recommended as particularly suitable,
without mentioning or excluding others; or that a certain course of action is preferred but not necessarily required; orthat (in the negative form) a certain course of action is deprecated but not prohibited.
The word may is used to indicate a course of action:permissible within the limits of the standard.

3.2 Glossary
3.2.1 BER: See: bit error rate.
3.2.2 bit error rate: The ratio of errors to the total number of bits being sent in a data transmission from one location
to another.
3.2.3 box: A mechanical unit that contains links; the links may either remain inside the box, connecting internal
devices, or may leave the box in order to connect internal devices to external ones. A box is assumed to be an EMC
compliant enclosure and to operate under a single electrical environment.

4IEEE publicatons are available from the Institute of Electrical and Electronics Engineers, 445 Hoes Lane, P.O. Box 1331, Piscataway, NJ 088551331, USA.
5This publication also bears the number IEC 874-1. QC 210000 is available from International Electrotechnical Commission, IEC publications areavailable from IEC Sales Department, Case Postale 131, 3, rue de Varembé, CH-1211, Genève 20, Switzerland/Suisse. IEC publications are alsoavailable in the United States from the Sales Department, American National Standards Institute, 11 West 42nd Street, 13th Floor, New York, NY
10036, USA.
6
Information on references can be found in clause 2.

Copyright © 1995 IEEE All Rights Reserved

3IEEE Std 1355-1995

IEEE STANDARD FOR HETEROGENEOUS INTERCONNECT (HIC) (LOW-COST, LOW-LATENCY

3.2.4 character: A group of consecutive bits used to represent control or data information. Characters are of two
types: normal characters (N_chars) or link characters (L_chars). See also: control character, data character, linkcharacter, normal character.
3.2.5 character layer: The layer of the protocol stack that specifies the representation of characters in terms of groupsof consecutive bits. The character layer provides the service to the higher layers of the transmission of a continuous
sequence of characters on a link.
3.2.6 coding: The translation from the original set of bits (character) to a new set of bits (coded character) suitable forserial transmission. See also: decoding
3.2.7 control character: A character used for signaling purposes by the exchange, packet or transaction layers of thestack. Both N_chars and L_chars are used as control characters. See also: link character; normal character.
3.2.8 data character: A character used for packet payload or packet header. A data character represents one of thevalues of a byte, i.e., 0—255 (decimal). Only N_chars are used as data characters. See also: link character; normal
character.
3.2.9 decoding: The translation from the coded set of bits (coded character) to the original set of bits (character). See
also: coding.
3.2.10 deserialization: The assembly of a coded character from the sequence of serial bits. See also: serialization.
3.2.11 destination: One or more destination_identifiers, identifying the destination node(s) to which the packet is tobe transmitted. See also: destination_identifier.
3.2.12 destination_identifier (dest_id): An implementation dependent identity of a destination node for a packet.
3.2.13 destination node: The terminal node(s) that is/are to receive a particular packet. See also: node.
3.2.14 digital sum variation: The difference between the number of logical ls and the logical Os transmitted by a link
output since commencing operation. See also: running disparity.
3.2.15 disparity: The difference between the number of logical 1s and logical 0s in a character. A positive or negative
disparity indicates an excess of 1s or 0s, respectively.
3.2.16 end_of_packet marker: A control character that indicates the end of a packet. See also: packet.
3.2.17 exchange layer: The exchange layer describes the procedure of the node-to-node exchange of characters toensure the proper functioning of the link. The exchange layer provides the service to the higher layers of thetransmission of an indefinite sequence of N_chars.
3.2.18 fabric: A device or a collection of devices that provides a general routing capability, constructed from one ormore switches using links. See also: link; switch.
3.2.19 flow control character (FCC): A control character transmitted on a link in the opposite direction to data flowfor each direction of data flow, i.e., to the transmitter of data from the receiver, indicating that the receiver has spacereserved to receive a further F N_chars. The value of F is specified separately for each technology in this standard.
3.2.20 functional: A link interface becomes functional when the start-up procedure has successfully completed andthe link interface is ready to transmit data.
3.2.21 link: A means of communicating digital information bidirectionally in serial format between two devices orsubsystems. A link comprises two link interfaces connected by an appropriate medium (or media, for connections
between boards or cabinets), such that the link output of each interface is connected to the link input of the other.
3.2.22 link cable: The physical medium connecting two link interfaces, comprising of two or more electrical or opticalcables.
3.2.23 link character (or L_char): Control characters that are used on a link in order to ensure flow control and theproper functioning of the link. See also: normal character.
3.2.24 link input: A connection point for receiving signals. See also: link interface.

4

Copyright © 1995 IEEE All Rights Reserved

SCALABLE SERIAL INTERCONNECT FOR PARALLEL SYSTEM CONSTRUCTION)IEEE Std 1355-1995

3.2.25 link interface (or port): A connection point comprising a link input and a link output and implementing oneof the relevant conformance subsets defined in 10.2. See also: link.
3.2.26 link output: A connection point for transmitting signals. See also: link interface.
3.2.27 network: Any set of devices or subsystems connected by links joining (directly or indirectly) a set of terminal
nodes.
3.2.28 node: A device or subsystem having one or more link interfaces. A node may be a terminal node (q.v.). A node
may perform a muting function, muting packets between its node interfaces according to the information in thedestination field of the packet.
3.2.29 node interface: A link interface on a switch. See also: link interface; switch.
3.2.30 normal character (or N_char): N_chars represent, at the minimum, the 256 values of a byte (i.e., all the datacharacters) plus a control character representing an end_of_packet marker.
3.2.31 packet: A sequence of N_chars with a specific order and format. A packet consists of a destination followed bya payload. A packet is delimited by an end_of_packet marker. See also: destination; payload.
3.2.32 packet layer: The layer of the protocol concerned with end-to-end transmission of information, possibly
through a number of intermediate routers. It is at the packet layer that the muting decisions are taken.
3.2.33 payload: The data (a message, a memory access request, an acknowledgment, etc.) that is to be transferredfrom the source node to the destination node. It has a specific format, defined in the transaction layer. Note that apayload may be null. See also: packet.
3.2.34 physical medium: See: transmission medium.
3.2.35 port: See: link interface.
3.2.36 routing function: Inside a switch, this is function that determines to which numbered node interface a packet
is to be sent, based on the information contain in the packet destination. See also: switch.
3.2.37 run length: The maximum number of succesive bits of the same value that can occur in the coded 3.2.37 runlength: The maximum number of successive bits of the same bit stream.
3.2.38 running disparity: The cumulative sum of the disparities of characters transmitted from the start of operationof the link up to the present time. A link has two running disparities, one for each direction.
3.2.39 serialization: The process of transmitting coded characters one bit at a time. See also: deserialization.
3.2.40 signal: A measurable quantity (e.g., a voltage) that varies in time in order to transmit information. A signal
propagates along a wire or an optic fiber. It is interpreted as a sequence of bits that is grouped into a sequence ofcharacters by the character layer of the protocol stack. Signals are generated by a link output and are absorbed by a link
input.
3.2.41 signal layer: The layer of the protocol stack at which signals are specified.
3.2.42 sink: A consumer of normal characters at a link interface. See also: normal character.
3.2.43 source: A generator of normal characters at a link interface. See also: normal character.
3.2.44 source node: A terminal node that originates data. See also: destination node
3.2.45 switch: A routing device (for example, a box or board) providing a set of numbered node interfaces, constructedfrom one or more switch chips (or by other methods). See also: fabric, node interface, switch chip.
3.2.46 switch chip: A VLSI integrated circuit with two or more link interfaces, between which it provides packet
routing. See also: link; switch.
3.2.47 terminal node: A node with one or more link interfaces that are used to originate or consume data across aninterconnect complying with this standard. See also: source; sink.

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IEEE STANDARD FOR HETEROGENEOUS INTERCONNECT (HIC) (LOW-COST, LOW-LATENCY

3.2.48 transaction: A sequence of packets sent between two or more terminal nodes to perform some function. See
also: transaction layer.
3.2.49 transaction layer: The layer above the packet layer for use by applications. It is unspecified in this standard.
See also: transaction.
3.2.50 transmission medium: A means of transporting electrical or optical signals. See also: signal.

4. Physical media and logical layers
This standard defines a set of rules for information exchange (the logical layers) together with the ways in that it shallbe implemented on a variety of physical media. The logical layers are defined as a protocol stack. Each layer of the
protocol stack defines representations (information formats) in terms of the immediately lower layer, together withrules (protocols) for the exchange of these representations.
The use of the physical media and logical layers is illustrated in figure 4-1. The physical medium and the signal,
character and exchange layers are concerned with point-to-point communication between adjacent nodes, while thepacket layer provides end-to-end communication between terminal nodes.

Figure 4-1 —Protocol stack between nodes

4.1 Physical media
For electrical links, the physical characteristics include the specification of
a)
b)
c)
d)
e)
f)
g)
h)

Circuit board physical characteristics
Connectors and contacts
CablesShielding requirements
Line impedance
CrosstalkElectromagnetic emission
ESD susceptibility

For optical links, the physical characteristics include the specification of6

Optical transceiver properties
Optical connectors
Optical fiber
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SCALABLE SERIAL INTERCONNECT FOR PARALLEL SYSTEM CONSTRUCTION)IEEE Std 1355-1995

4.2 Logical layers
4.2.1 Layer 0: signal layer
4.2.1.1 General description
For electrical links, the signal layer includes the specification of
a)
b)
c)

Line signal levels and rates
Power budget, from which transmission distance may be calculated, taking into account the loss from thecables and connectors
Noise margins

For optical links, the signal layer includes the specification ofSpectral center wavelength, aperture
Optical power budget

It is important to note that there is a difference between signals and bits. Signals are the values of a measurable quantity(e.g., voltage levels) that are on the transmission line; bits are the logical ls and Os that the signals represent. The
measurable quantities vary both in nature and in value depending on the implementation (CMOS, ECL, CML, lightpulses on a fiber optic cable, etc.).
The signals may have various properties, such as limited running disparity, limited run length,and/or dc balance, overa period of time.
4.2.2 Layer 1: character layer
4.2.2.1 Definition of character
Bits are transmitted in groups called characters. The character layer provides the service to the higher layers of thetransmission of a continuous sequence of characters on a link.
4.2.2.2 General description
Characters are used by the higher layers of the protocol to communicate both data information and control
information. The number and representations of the various control characters and the representations of the 256
possible data values varies according to the different types of links specified in this standard.
4.2.3 Layer 2: exchange layer
4.2.3.1 Definition of the exchange layer
A link is the means of communicating digital information bidirectionally in serial format between two very large scale
integration (VLSI) devices. A link comprises two link interfaces connected by an appropriate medium (or media, forconnections between boards or cabinets), such that the link output of each link interface is connected to the link inputof the other.
The exchange layer describes the procedure of the node-to-node exchange of characters to ensure the proper
functioning of the link.
4.2.3.2 General description
Two types of character are defined: link character (L_char) and normal character (N_char).
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a)b)IEEE STANDARD FOR HETEROGENEOUS INTERCONNECT (HIC) (LOW-COST, LOW-LATENCY

L_chars: L_chars are used on a node-to-node link in order to ensure flow control and the proper functioningof the link.
N_chars: N_chars represent, at the minimum, the 256 values of a byte plus an end_of_packet marker. The
exchange layer provides the service to the higher layers of the transmission of an indefinite sequence ofN_chars. It is specified in such a way as to ensure that N_chars are not lost due to limitations of resources(e.g., lack of available buffer space).

L_chars may be arbitrarily interleaved with N_ehars on the link as required by the exchange layer.
Note that in the text of this standard the data values of a byte (0 to 255) are referred to as data characters, and all theother used characters (i.e., all L_chars and the remainder of the N_chars) as control characters.
Consider two connected nodes, NODE_A and NODE_B (see figure 4-2). Each node uses a link interface or port
(LINK_INTERFACE_A and LINK_INTERFACE_B respectively) in order to communicate with the other node. Notethat a node may have more than one link interface. Each link interface is divided into two parts: a transmitter and a
receiver, referred to as transmitter_A and receiver_A for NODE_A and transmitter_B and receiver_B for NODE_B.
Each link interface has a N_char source (SOURCE_A and SOURCE_B) that supply Nchars to transmitter_A andtransmitter_B respectively and a N_char sink (SINK_A and SINK_B) that accept data from receiver_A and receiver_B
respectively.
Exchange layer information generated and sent, for example, by transmitter_A are received and filtered by thereceiver_B and passed directly to transmitter_B (and vice-versa). L_chars shall not be generated by the source nor
written into the sink.
4.2.3.3 Flow control
The N_char sink associated with a link interface has a maximum capacity, defined by the physical implementation.
N_chars are written into the sink by the receiver as it receives them at the link interface, and are read from the sink by
the application using the link. In order to prevent sink overrun a flow control mechanism shall be implemented.
The source (at the other end of the link) maintains a “credit” associated with the receiving link interface that indicates
how many N_chars the source can transmit over the link without overrunning the sink at the receiving end. For every
N_char that the source sends, it shall decrement the credit by one. When the credit reaches zero, the source shall not
send any further N_chars, but it may continue to send L_chars. The credit maintained by the source shall be increased
by a block value (sometimes referred to as a “flit”) of F characters when the source receives a Flow Control Character(FCC) from the opposite receiver. If this happens when the credit was zero (which will have inhibited the transmissionof N_chars), then the source may recommence transmitting N_chars. An implementation may restrict the amount ofcredit that a source can record. If a FCC is received when this credit has its maximum value, the FCC may be discarded(ignored) without affecting the operation of the link. A source shall be able to record at least F N_chars of credit.
The initial value of the credit shall be O. The block size (value of F) is defined as a function of the technology used.
The sink should send a FCC to the source when it has the space to receive F N_chars. Each time the sink authorizes thesending of a FCC it shall reserve the space corresponding to F N_chars. While the sink has unreserved space available
it should send FCCs until all its space associated with the link interface is reserved. One of the first actions of each sinkafter the link has been started from a reset condition should therefore be to send the number of FCCs corresponding to
its unreserved space.
Using the flow control mechanism described above, there exists a theoretical maximum line length over which“continuous transmission” can be obtained in the case where every N_char written into the sink is immediately readout of the sink by the receiving application. This maximum length is determined by the size of the sink (which
determines the number of PCCs that the receiver sends to the transmitter after the link has been started from a reset

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SCALABLE SERIAL INTERCONNECT FOR PARALLEL SYSTEM CONSTRUCTION)IEEE Std 1355-1995

condition and thus the initial transmitter credit) and a number of implementation-dependent parameters. This isdetailed in annex H.

Figure 4-2 —Exchange layer
Exchange layer flow control greatly simplifies the higher layers of the protocol, since it prevents data from being lost
due to buffer overflow and so removes the need for re-transmission unless errors occur. To the user of the system, thenet result is that a link functions as a pair of fully handshaken first-in, first-outs, one in each direction.
Note that the link interface regulates the flow of data items without regard to the higher layer objects that they may
constitute. At any instant the N_chars buffered by a link interface may form part or all of one or more consecutive
higher layer objects. L_chars, including FCC, do not belong to such objects and are not buffered.
4.2.4 Layer 3: packet layer
4.2.4.1 Definition of a packet
A packet is a sequence of characters (N_chars only) with a specific order and format. Constituent characters ofdifferent packets shall not be interleaved on a link. A packet consists of a destination followed by a payload. A packet
is delimited by an end_of_packet marker.
4.2.4.2 General description
Terminal nodes generate (source node) and consume (destination node) packets. A network is any set of devices
connected by links joining (directly or indirectly) a set of terminal nodes.
The protocol assumes the use of packet-switched networks in which the routing information necessary to correctlytransmit the packet across the network is contained in the first K N_chars of the packet (where K is fixed throughout
a subnetwork). It is at the packet layer that the routing decisions are taken. The protocol does not define a specific (ormaximum) size for a packet. Successive packets transmitted on a link may have different lengths and/or destinations.

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IEEE STANDARD FOR HETEROGENEOUS INTERCONNECT (HIC) (LOW-COST, LOW-LATENCY

Each packet is transmitted in its entirety, i.e., the transmission of a packet on a link shall be completed before thetransmission of the successive packet may commence. Packets sent from a given source node to a given destination
node over a network may be delivered in an order different from the sending order. The details of mechanisms toensure in-order delivery are outside the scope of this standard.
4.2.4.3 Destination
The destination contains one or more destination identifiers (dest_id) that are used as the input to the routing function,
enabling the routing network to transit the packet from its source node to its destination node. The destination could benull for specific case of a point-to-point link (i.e., the network is just one link). More than one dest_id may denote thesame destination node. The method of allocating dest_ids to destinations is outside the scope of this standard. See also
clause 9. and annex E.
4.2.4.4 Payload
The payload is the data (a message, a memory access request, an acknowledgment, etc.) that has to be transferred fromthe source node to the destination node. It has a specific format, defined in the transaction layer. Note that a payload
may be null.
4.2.4.5 End of packet marker
A packet is delimited by an end of packet marker.
4.2.5 Layer 4: transaction layer
A transaction is a sequence of packets sent between two or more terminal nodes to perform some function. At thislayer there are two concepts:a)b)Definition of the specific payload formats necessary to perform the function
Definition of the sequence of exchanges of packets necessary to perform required function

The definition of any form of transaction is outside the scope of this standard. Annexes F and I illustrate the use of thetransaction layer.

4.3 Interaction of layers
The interaction of the layers is illustrated in figure 4-3.

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SCALABLE SERIAL INTERCONNECT FOR PARALLEL SYSTEM CONSTRUCTION)IEEE Std 1355-1995

Figure 4-3 —Protocol stack diagram showing interaction of layers
4.3.1 “Downward going”
4.3.1.1 Transaction layer to packet layer
The transaction layer provides packets to the packet layer. The packet sequence, payload contents and destination
address(es) are all determined by the transaction layer. The packet layer forms the packet destination from thedestination address(es) and appends the packet with the appropriate end_of_packet marker.
4.3.1.2 Packet layer to exchange layer
The packet layer provides the sequence of N_chars that forms each packet to the exchange layer.
4.3.1.3 Exchange layer to character layer
The exchange layer passes the N_chars that have been provided to it by the packet layer onto the character layer. In
order to perform the exchange layer functions, it intefieaves L_chars arbitrarily into the sequence of N_chars. The
sequence of N_chars is unchanged.

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IEEE STANDARD FOR HETEROGENEOUS INTERCONNECT (HIC) (LOW-COST, LOW-LATENCY

4.3.1.4 Character layer to signal layer
The character layer translates the characters (N_chars and L_chars) it receives from the exchange layer into a bit
stream that it passes to the signal layer. The translation is formed of two parts: coding and serialization. Coding is thetranslation from the original set of bits (character) to a new set of bits (coded character) suitable for serial transmission.
Serialization is the process of transmitting coded characters one bit at a time.
4.3.1.5 Signal layer
The signal layer takes the bit stream and outputs signals onto the physical medium.
4.3.2 “Upward Going”
4.3.2.1 Signal layer to character layer
At the receiver end, the signal layer receives signals from the line and generates the corresponding bit stream.
4.3.2.2 Character layer to exchange layer
The character layer deserializes and decodes the bit stream to produce a sequence of characters. Deserialization is theassembly of a coded character from the sequence of serial bits. Decoding is the translation from the coded set of bits
(coded character) to the original set of bits (character). The characters are passed to the exchange layer.
4.3.2.3 Exchange layer to packet layer
The exchange layer filters out L_chars for exchange layer functions and passes the N_chars to the packet layer.
4.3.2.4 Packet layer to transaction layer
The packet layer reconstitutes the packets from the received N_chars. This is a logical reconstitution and need not
imply that a whole packet is physically assembled. Routing functions are carried out at the packet layer, based on theinformation in the packet destination. When necessary (e.g., when a packet has arrived at its destination node), thepackets are delivered to the transaction layer.
4.3.2.5 Link status information
Link status information is passed up between the layers from the signal layer to the packet layer. The link status
information necessary is dependent on the implementation of the link and includes, for example, information on thecalibration of the receiver, parity errors, etc. It is for each layer to filter the information that is relevant to its
functioning and to pass up the remaining information.

4.4 Implementations defined in the standard
The physical and logical layers defined in this standard are illustrated in figure 4-4.
The physical layer may be implemented in a number of different technologies, identified according to signaling
convention, transmission medium, and maximum operating speed.
The format for this identification is given by three parameters:
SC-TM-dd
The possible values of these parameters are given in table 4-1.
Table 4-2 provides the major properties of each of the defined implementations.

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SCALABLE SERIAL INTERCONNECT FOR PARALLEL SYSTEM CONSTRUCTION)IEEE Std 1355-1995

Figure 4-4 —Defined implementations of physical and logical layers
Table 4-1 —Identification format for technologies
Parameter

SC

TM

dd

ValuesDescription

DS

Data/strobe encodingTS

Three-of-six encoding

HS

High speed encoding

SE

Single-ended electricaltransmission

DE

Differential electricaltransmission

FO

Fiber optic transmission

Two digits, representing the maximum operating speed
in units of 100 MBd

DS-SE links are intended for use for chip-to-chip and board-to-board interconnect. This standard does not therefore
specify any cable/connector system for these links. DS-DE links are intended for interconnecting sub-racks andadjacent racks using a protocol compatible with DS-SE link from the character layer upwards. TS-FO links areintended to provide longer distance transmission using, necessarily, optical technology, but at speeds compatible with
DS-SE links. The use of optical technology necessitates some differences at the exchange layer. HS-SE links areintended for high speed rack-to-rack interconnect. They can, of course, also be used between chips and between boards(across a backplane), given suitable attention to maintaining appropriate signal integrity. HS-FO links are intended toprovide longer distance transmission using a protocol compatible with HS-SE links from the character layer upwards.
This standard specifies an appropriate cable/connector system for each of the technologies specified within thisstandard, with the exception of DS-SE links. The connector system is intended as a front-panel adapter and matching
cable mounted connector.

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13IEEE Std 1355-1995

IEEE STANDARD FOR HETEROGENEOUS INTERCONNECT (HIC) (LOW-COST, LOW-LATENCY

Table 4-2 —Defined implementations

Technology

Baud Rate

Maximumbidirectional
data rate

Units

Baud

MByte/sType of transmission(full duplex)

Maximum
distance

Connector
specification—

Meters—

DS-SE-02

1.333-200 M

38

4 wires

1

None

TS-FO-02

250 M

39.4

2 multimode fibers

300

IEC 1754-6

DS-DE-02

1.333-200 M

38

8 wires10

IEC 1076-4-107

HS-SE-10

700-1 000 M

160

2 coax cables

8

IEC 1076-4-107

2 62.5 µm multimodefibers100

IEC 1754-6

2 50 µm multimodefibers

1 000

2 single-mode fibers

3 000

HS-FO-10

700-1 000 M

160

IEC 1754-6
IEC 1754-6

This standard does not specify any backplane or mezzanine connector standards. This is considered more
appropriately specified as an adjunct to specific existing backplane standards.

5. DS-SE and DS-DE

5.1 General
The DS-SE and DS-DE links are designed for point-to-point communication that may be on a single PCB, board toboard (DS-SE links), or box to box (DS-DE links). Since this implies that transmission line problems might be present,
the electrical level is specified as a transmission line system. In order to reduce the power required for each link(permitting single chips to have a large number of link ports) source-only termination is used for DS-SE links.
A DS-SE/DS-DE input is self-clocking, which means that in any particular system the actual operating speed may bechosen to suit the system, rather than the more normal case of having to engineer a system to suit a pre-determinedtransmission speed. The maximum speed at which it may run is a function of the maximum speed of the circuitry ateach end, plus the properties of the medium connecting the two ends. A link may be operated at lower speeds, forexample to provide power saving, down to a level at which the disconnection detection mechanism is triggered.
A link shall operate at a speed of 10 MBd unless and until the system in which it operates determines that it may
operate at a different speed. The electrical specification of the link has been designed to allow operating speeds of up
to 200 MBd, but the actual operating speed is left open to allow the design of any particular system to trade off
engineering costs against operating speed. The means of setting the speed of a link is not defined within this standard.

5.2 DS-SE: physical medium
5.2.1 Transmission line requirements
For distances greater than a few centimeters, signal integrity considerations dictate that the link line has to beconsidered as a transmission line. Discontinuities or variations in characteristic impedance should be kept to aminimum. The transmission line may be made on PCBs but care shall be taken to provide a good ground or power
plane beneath the link track and crosstalk with other tracks should be minimized (including between data and strobe
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SCALABLE SERIAL INTERCONNECT FOR PARALLEL SYSTEM CONSTRUCTION)IEEE Std 1355-1995

lines of the same link). The longest length of line achievable will depend on the materials used for interconnect and thegrounding arrangements.
DS-SE supports two standard nominal characteristic impedances for the physical medium, 50 Ω and 100 Ω. Drivers
conforming to the DS-SE electrical standard shall support one of these impedances and may support both. Eachdirection (i.e., the data and the strobe line) of a single point-to-point link shall use either one or other impedance
throughout the length of the link and use a matched driver. The opposing directions of a single point-to-point link may
however use different impedances.

5.3 DS-SE signal level
5.3.1 General
Each connection of a DS-SE link shall be implemented as a unidirectional point-to-point transmission line. The
transmission line shall have a characteristic impedance of either 50 Ω or 100 Ω and shall be terminated by highimpedance at the receiver. The transmission line may be provided by PCB, coax or other suitable controlled impedanceinterconnect. The receiver shall be designed to accept standard TTL input switching levels with a high input
impedance. The driver output impedance should be close to the characteristic impedance of the transmission line bothwhen the driver is driving low or high and also while switching. This is to ensure that reflections generated by thereceiver are sufficiently damped by the driver that they do not cause spurious transitions. The range 0.8 V to-2.0 V at
the receiver is defined as the transition region. It is very important that the signal at the receiver is monotonic in thetransition region, and that the reflections do not cause spurious transitions. This should be ensured by careful design ofthe interconnect and the driver output.
The propagation of signals is as follows. Assuming that the line is in a steady-state low condition, a high goingtransition is output by the driver. Because of the relatively high output impedance of the driver compared to the line,
this is attenuated, typically to a level of about 1.4 V at the driver output. At the receiver, the high input impedance ofthe receiver (effectively an open circuit) causes this to appear as a 2.8 V step (taking the input cleanly through thetransition region), and the reflection travels back down the line to the driver. Depending on how closely the driver
output impedance is matched to the line, this may cause further reflections: it is crucial that the driver is matchedsufficiently well that these reflections do not cause spurious transitions at the receiver, or interfere with subsequent
output transitions. Propagation for a low-going transition is similar. Figure 5-1 shows example, waveforms for thedriver and the receiver end of the transmission line for a 100 Ω system operating from a 5 V supply.
Note that the signal levels at the receiver and the specification of the driver allows DS-SE links to be interconnected
between devices operating from 5 V and 3.3 V supply rails as long as the inputs of the 3.3 V devices are tolerant of 5 V
signals.
5.3.2 DS-SE link driver
Each driver should have a nominal output impedance of either 50 Ω or 100 Ω depending on the transmission medium
to terminate the reflections from the receiver. The output impedance shall be controlled when the output is fully on
driving a high or low level, and also while switching. In order to be adequately matched, the characteristics of thedriver and the transmission line shall be related as shown in the table 5-1.

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15IEEE Std 1355-1995

IEEE STANDARD FOR HETEROGENEOUS INTERCONNECT (HIC) (LOW-COST, LOW-LATENCY

Table 5-1 —Driver to line impedance matching table
Vdd = 3.0 V to 3.6 V
Zn

Vdd = 4.5 V to 5.5 V

Zp

Zn

Zp

Units

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Zo=45–55

ohms

29

56

37

67

32

52

55

123

Zo=90–110

ohms

58

112

73

135

64

104

l10

247

Figure 5-1 —DS-SE link signal propagation
Zo is the characteristic impedance of the transmission line. Zn is the impedance of the driver when the output is driving
low, and Zp the impedance when it is driving high. The figures depend on the supply voltage used by the driver because
the input threshold is fixed.
It is recommended that nominal 50 Ω characteristic impedance transmission lines be used in nominal 3.3 V systems
and on backplanes.
On power on and reset, a DS-SE !ink output shall hold both the data and strobe signals low.
Annex J gives an example DS-SE link driver circuit for a 100 Ω transmission line with 5 V supplies.
5.3.3 DS-SE link receiver
A DS-SE link input shall present a high impedance termination to the transmission line. An impedance of >10 kΩ isrecommended. This high input impedance is essential to ensure that the correct signal levels are produced at thereceiver input.
The input threshold of the receiver is nominally 1.4 V and shall be within the transition region, which is defined as
0.8–2.0 V.
The input capacitance is modelled as described in 5.3.4 (see figure 5-2) and specified in table 5-2.
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SCALABLE SERIAL INTERCONNECT FOR PARALLEL SYSTEM CONSTRUCTION)IEEE Std 1355-1995

Table 5-2 —DS-SE input capacitance
SymbolCi

Parameter

Units

Input capacitancepF

100 MBd

100 MBd

200 MBd

Notes

Min.

Max.

Min.

Max.

Min.

Max.

—

300

—

30

—

4

—

5.3.4 DS-SE link timing
A link shall operate at a speed of I0 MBd, until the system in which it operates shall determine it may operate at adifferent speed. A link may be operated at a speed lower than its nominal speed to suit the transmission medium. If alink is operated at a lower speed, the same timing constraints shall apply at the receiver inputs.
DS-SE parameters are relative to a reference model, as shown in figure 5-2.

Figure 5-2 —DS-SE timing reference modelThis model shows the possibility of buffers in the signal path, in which case the output impedance of the second buffer
is assumed to be not more than 100 Ω and Co is assumed to be not more than Ci. If buffers are not used then Ci andCo are combined into a single capacitive load that may be twice the figure given in table 4. If the output drivers arematched to 100 Ω and it is required to use 50 Ω transmission lines, then buffers will be required.
Three sets of timing parameters are defined (see table 5.3 figure 5-3), to allow for operation at the default speed of 10
MBd (DS-SE-00 links), 100 MBd (DS-SE-01 links), and 200 MBd (DS-SE-02 links). A higher speed link type will
always be able to operate at a lower speed.
Table 5-3 —DS-SE timing and swings
SymbolParameter

Units

10 MBd100 MBd

200MBd

Min.

Max.

Min.

Max.

Min.

Max.

Notes

tDSI

D/S edge min. separation

ns

—

20

—

2.5

—

1

1.2

tDSDSI

Sustainable input bit period

ns

80

750

9

750

4.5

750

3

tLIDSfInput fall time (2.0–0.8 V)

ns

—

100

—

100

—

100

4

tLIDSrInput rise time (0.8–2.0 V)

ns

—

100

—

100

—

100

4

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17IEEE Std 1355-1995

IEEE STANDARD FOR HETEROGENEOUS INTERCONNECT (HIC) (LOW-COST, LOW-LATENCY

Figure 5-3 —DS-SE link timings
The output skew is determined by parameters given in table 5-4.

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SCALABLE SERIAL INTERCONNECT FOR PARALLEL SYSTEM CONSTRUCTION)IEEE Std 1355-1995

Table 5-4 —S-SE output skew parameters
SymbolParameter

Unit

10 MBd100 MBd

200 MBd

Min.

Max.

Min.

Max.

Min.

Max.

Notes

tDSO

Output DIS skew

ns

—

±5

—

±1

—

±0.5

1

tLODSfOutput fall time (2.0–0.8 V)

ns

—

40

—

4

—

2

—

tLODSrOutput rise time (0.8–2.0 V)

ns

—

40

—

4

—

2

—

NOTE — This is a skew measured at the 1.5 V threshold relative to the nominal time at which it is specified to cross it, definedin terms of consecutive edges. For example, if two consecutive edges are nominally 5 ns apart, the length of time
between the time at which each will cross the threshold can be 5 ns apart, the length of time between the time at which
each will cross the threshold can be 5 ns ±tDSO.

Allowable system skew is determined by the constraint that the sum of tDSI, the range of tDSO and the system skew
shall not exceed nominal bit time. Thus, for DS-SE-01 links the system skew shall not exceed 5.5 ns.
5.3.5 DS-SE link signals
Information on a DS-SE link shall be transmitted using two connections, referred to as data and strobe respectively, ineach direction. Each connection shall satisfy the electrical constraints specified in the previous subclause. The data line
carries binary data values, and the accompanying strobe line changes state each time the next bit has the same value as
the previous one (this does not correspond with the usual meaning of “strobe,” which would be a signal that indicatesevery time that another signal is valid). By this means each DS pair carries an encoded clock, in a way that allows up
to a full bit-time of skew-tolerance between the two connections. Figure 5-4 shows the form of signals on the data andstrobe connections.

Figure 5-4 —DS-SE link signal encoding
Since the data-strobe system carries a clock, the links are asynchronous; the receiving device synchronizes to theincoming data, This means that DS-SE (and DS-DE) links autobaud; the only restriction on the transmission rate isthat it does not exceed the maximum speed of the receiver. This also simplifies clock distribution within a system,
since the exact phase or frequency of the clock on a pair of communicating devices is not critical. It is not essential thatboth link outputs of one link connection should operate at the same speed, nor that a link output operate at a constant
speed. A link output might choose to vary its speed of operation to reduce power consumption when there is no data
to be transmitted, for example. The only constraint on the transmission rate is that the bit time limits given in table 53 are not violated, and that it is high enough to prevent a disconnect timeout being triggered (see 5.7.4.2).
A DS-SE link output transmits information on a pair of lines, and a DS-SE link input receives information on a pair oflines. A DS-SE link interface shall comprise a DS-SE link output and a DS-SE link input.
A device providing one or more DS-SE link interfaces shall identify the pins used for each link interface by aconvention (using subscription where multiple links are supported) based on function and direction of transmission asshown in table 5-5.

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19IEEE Std 1355-1995

IEEE STANDARD FOR HETEROGENEOUS INTERCONNECT (HIC) (LOW-COST, LOW-LATENCY

Table 5-5 —Identification of multiple link interfaces
DS_SE_data_in
For input of data to the device through the link interface
DS_SE_strobe_in
DS_SE_data_out
For output of data from the device through the link interface
DS_SE_strobe_out

A DS-SE link is constructed by connecting the DS_SE_data_out and DS_SE_strobe_out of one link interface to the
DS_SE_data_in and DS_SE_strobe_in respectively of the other link interface, and vice versa.
The DS_SE_data_out and DS_SE_strobe_out of a link interface may be connected to the DS_SE_data_in and
DS_SE_strobe_in respectively of the same link interface to create a loopback, e.g., for link testing.

5.4 DS-DE: physical medium
5.4.1 Link cable
A DS-DE link cable shall provide ten connections. Eight connections (in four pairs) shall support the eight signals in
the DS-DE link; the ninth and tenth connections shall support an optional remote power facility.
A recommendation for the DS-DE cable is given in annex M.
Each connection in the cable shall be color coded as given in table 5-6 and have the characteristics as given in table 5-7.
Note that attenuation and skew budgets are given in 5.5.3 and 5.5.4. (See also 10.3.)
Table 5-6 —DS-DE cable color code
Component

Conductor 1

Conductor 2

Pair 1Red

Green

Pair 2

Brown

Blue

Pair 3

OrangeYellow

Pair 4VioletGray

Pair 5

Black

White

The link cable shall be clearly marked “IEEE 1355 DS-DE Link Cable.”
5.4.2 Connector
The connector system consists of a through-panel (fixed) connector and a cable-mounted (free) connector.
It provides the following features:
a)
b)
c)
d)
e)
f)

20

A full duplex link connection per connector
Option for multiple connections on the cable connector
Complete screening
RobustLatching
Small size

Copyright © 1995 IEEE All Rights Reserved

SCALABLE SERIAL INTERCONNECT FOR PARALLEL SYSTEM CONSTRUCTION)IEEE Std 1355-1995

The DS-DE connectors shall be as specified in IEC 1076-4-107.
Table 5-7 —Electrical and mechanical characteristics and safety certification of DS-DE cable
Electrical characteristics
Differential impedance

95 Ω ± 10 Ω

EMC

Cable shall allow system to meet CISPR 22 regulations

Near end crosstalk(backward)

2% maximum at 100 MHz measured on 10 m sample indifferential mode

Far end crosstalk(forward)

4% maximum at 100 MHz measured on 10 m sample indifferential mode
Mechanical performance

Flexibility

A 60 mm maximum radius shall result when 610 mm ofcable is loaded with a suspended weight of 100 g

Flex life

1000 cycles through 180 degrees at 60 mm bend radiusand 100 g load. Following this test, the insulation andjacket should be free of cracks and the conductors free ofopens and shorts.

Minimum bending radius(static operation)

40 mm
Safety certification

For cables up to 10 ft (3 m)in the US

UL listing: AWM style 20276, 80C, 30 V, VW1

For cables 10 ft (3 m) to
100 m

UL listed class 2 power limited circuit cable (CL2)

The (free) connector at either end of the cable shall be connected to the conductors in the cable according to table 5-8.
Table 5-8 —DS-DE link cable conductors/connectors wiring
Pin

Conductor

Pin

1aPair 2 brown2e2aPair 2 blue

1e

1bPair 1 red

2d

2bPair 1 green

1d

1cPair 5 white1c2cPair 5 black

2c

1d

Pair 3 orange

2b2dPair 3 yellow

1b

1ePair 4 violet

2a2ePair 4 grey

1aCopyright © 1995 IEEE All Rights Reserved

21IEEE Std 1355-1995

IEEE STANDARD FOR HETEROGENEOUS INTERCONNECT (HIC) (LOW-COST, LOW-LATENCY

Note that the effect of the cable/plugs assembly is to provide a single twist in each of Pairs 1, 2, 3, and 4, and to provide
a single twist between Pairs 1 and 3 and between Pairs 2 and 4. This is shown in figure 5-5 using Pairs 2 and 4 as an
example.

Figure 5-5 —DS-DE cable assembly twist example
Any extension adapters allowing multiple segments of cables to be used shall also provide such a twist, so that theeffect of any such cable/adapter/cable combination is to provide a single twist, as illustrated in figure 5-6.

Figure 5-6 —DE-DE extension adapter
The allocation of DS-DE signals to the connector pins shall be as given in table 5-9 [which is oriented to correspondto the external view of the through-panel (fixed) connector when mounted on the upper surface of a horizontal PCB.
See figure 5-7.]. The direction of the signals is as on the fixed connector.

Figure 5-7 —DS-DE fixed connector external view
Pins 1c and 2c of the DS-DE fixed connector are either both left unconnected on the PCB, or are used to implement an
optional power supply, as specified in 5.4.4. It is recommended that fixed DS-DE link connectors with neither source
nor sink power connections should include 10 MΩ bleeders to ground on pins 1c and 2c to prevent static build-up on
otherwise unconnected power conductors.
In addition to the interface specification of IEC 1076-4-107, the connectors shall have the properties described in table
5-10.

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SCALABLE SERIAL INTERCONNECT FOR PARALLEL SYSTEM CONSTRUCTION)IEEE Std 1355-1995

Annex L provides a recommendation for the PCB layout of the fixed connector.
Table 5-9 —Pin allocation of DS-DE connector
21eDS_DE_data_in_plus

DS_DE_data_in_minusd

DS_DE_strobe_in_plus

DS_DE_strobe_in_minusc

No connect or optional power return

No connect or optional powerb

DS_DE_strobe_out_minus

DS_DE_strobe_out_plusaDS_DE_data_out_minus

DS_DE_data_out_plus(Chamfercorners at thisside of theconnector)

Table 5-10 —DS-DE connector modularity specifications
Characteristic

Specification

Modularity

Fixed connector modules shall be placed on a 6 mm pitch, or theircenterlines separated by more than 12 mm

Connector width

5.9 mm maximum

5.4.3 Environmental constraints
The environmental requirements for the DS-DE link cables and connectors are application dependent. However, as aminimum, the cables and connectors shall meet the constraints in table 5-11. Note that specific applications may haverequirements for extended temperature range, or other environmental parameters.
Table 5-11 —DS-DE environmental constraints
Parameter

Value

Operating temperature–10 °C to +60 °C

Non-operating temperature–40 °C to +85 °C

5.4.4 Optional power supply to DS-DE cable
5.4.4.1 Optional power supply
An explanation of the remote power, and recommendations of components that should meet the following
specification, are given in annex K.
Pin 1c either provides an output power supply based on the equipment's 5 V VCC, with a self-healing fuse forovercurrent protection and a (Schottky) diode for reverse-current protection, or provides power to local circuitry froma remote source. Components should be chosen to meet the specification given in table 5-12. Pin 2c provides for power
return.
The load drawn from this power supply at the end of 500 mm cable with conductors as specified for the DS-DE link
cable, shall meet the specification given in table 5-13. The product of power used and cable length shall not exceed
1 W·m.

Copyright © 1995 IEEE All Rights Reserved

23IEEE Std 1355-1995

IEEE STANDARD FOR HETEROGENEOUS INTERCONNECT (HIC) (LOW-COST, LOW-LATENCY

Table 5-12 —Optional power supply
SymbolParameter

Value

IpHoldHold current, the operating current thatthe overcurrent protection device willpass without going high impedance

750 mA minimum

VpOHmin.

Output voltage with respect to pin 2c at
maximum steady state output current

3.75 V minimum at 750 mA

VpOHmax.

Output voltage with respect to pin 2c at
any output current greater than aleakage current of 1 mA

5.0 V maximum

IpReverse

Reverse-current

1 mA maximum at reverse
voltage of 12 V with respect topin 2cTable 5-13 —Optional power supply load
SymbolParameter

Value

Pp

Power consumption

2.5 W maximum

VpRemoteLow

Lowest input voltage with respect topin 2c at remote power supply at
which the remote power supply isable to supply the required power

3.5 V maximum

VpRemoteHigh

Highest input voltage with respect topin 2c at remote power supply thatthe remote power supply can tolerate

5.0 V minimum

5.4.4.2 Power supply protection
The above specification for the remote power supply defines the minimal requirements for operation in the absence ofa fault. It is recommended that the overcurrent protection device meets the specification given in table 5-14 in the eventof an overcurrent fault.
Table 5-14 —Optional power supply protective device
Symbol24

Parameter

Value

IpTrip

Trip current, the minimum current
that will cause the overcurrent
protection device to switch to a highimpedance state

2.5 A

TpTrip

Trip time, the maximum time for theovercurrent protection device toswitch to its high impedance statewith a fault current of 10 A

0.5 s

TpResetReset time, the time from when afault is removed to when theovercurrent protection device returns
to its specified characteristics

1 h maximum (but note typicalrecovery to within 20% of
specification, normally within
less than 1 min)

Copyright © 1995 IEEE All Rights Reserved

SCALABLE SERIAL INTERCONNECT FOR PARALLEL SYSTEM CONSTRUCTION)IEEE Std 1355-1995

5.4.4.3 Layout convention
It is recommended that in any block of adjacent DS-DE link connectors, the end connector with space adjacent to its
pins 1 (the end with the D chamfers of the connector pointing outwards from the block), be supplied with power on pin
1c, and that if more than one connector in any block be supplied with power, all such connectors should be adjacent(see figure 5-8). Equipment need not have special markings to identify connectors supplying power, but it isrecommended that such connectors are clearly documented.

Figure 5-8 —Multiple power connectors

5.5 DS-DE signal level
5.5.1 General
Differential signaling may be used, e.g., for connections between equipment. Differential signaling provides thefollowing advantages over single-ended signaling:a)b)

Increased noise immunity
Avoidance of ground loops between equipment

A DS-DE link interface may be constructed by connecting two differential drivers and two differential receivers to a
DS-SE link interface as follows:Each connection point of the DS-SE link output is connected to the input of a differential driver, generating apair of balanced signals from the on-board DS-SE electrical specification. The two pairs of signals form theDS-DE link output.
Each connection point of the DS-SE link input is connected to the output of a differential receiver, convertingtwo pairs of balanced signals into two signals conforming to the on-board DS-SE electrical specification. The
two pairs of signals form the DS-DE link input.

A DS-DE link interface shall have the logical properties that it would inherit if connected to a DS-SE link interface inthis way. This is the recommended implementation of a DS-DE link interface.
A DS-DE link is constructed by connecting two DS-DE link interfaces by a suitable eight-wire transmission line, in themanner defined in 5.4.
A system built using DS-DE links shall meet CISPR 22 regulations concerning electromagnetic emissions.

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25IEEE Std 1355-1995

IEEE STANDARD FOR HETEROGENEOUS INTERCONNECT (HIC) (LOW-COST, LOW-LATENCY

5.5.2 DS-DE signals
Each connection in a DS-DE link shall be made with a nominal 95 Ω transmission line. The transmission line shall beterminated at the receiver inputs: the combination of receiver input impedance and line termination shall be 100 Ω.
The signaling uses a pair of balanced pseudo-ECL signals. Pseudo-ECL signals have ECL-levels shifted by 5 V. See
table 5-15.
Table 5-15 —DS-DE signal levels
Parameter

Units

Min.

Typ

Max

Driver differential output voltage

V

0.8

1.0

1.4

Driver common mode output voltage

V

2.5

—

4

Driver output rise time (20–80%)

ns

0.5

—

2

Receiver input impedance (including
termination resistance)

Ohms

90

100

110

Receiver input common mode
voltage

V

–1.2

—

7.2

Receiver sensitivity

mV

200

—

—

The relevant buffer shall not be placed more than 3 cm from the corresponding fixed connector unless the tracks
between the buffer and the connector are matched to 100 Ω.
The DS-SE connection consists of four signals. Each pair of DS-DE signals is specified by reference to acorresponding DS-SE signal, as defined in table 5-16. Note that DS-DE signals need not be implemented by being
derived from the corresponding DS-SE signals.
Table 5-16 —DS-DE correspondenceSingle-ended side

Differential side

DS_SE_data_out

DS_DE_data_out_plus

DS_DE_data_out_minus

DS_SE_strobe_out

DS_DE_strobe_out_plus

DS_DE_strobe_out_minus

DS_SE_data_in

DS_DE_data_in_plus

DS_DE_data_in_minus

DS_SE_strobe_in

DS_DE_strobe_in_plus

DS_DE_strobe_in_minus

In each differential pair, the plus version of the signal is positive going when the corresponding single ended signal is
positive going, and vice versa.
A link shall connect two sets of differential pairs by connecting the DS_DE_data_out_plus of one set to
DS_DE_data_in_plus of the other set, DS_DE_strobe_out_plus of one set to DS_DE_strobe_in_plus of the other set,and similarly for the _minus signals.
5.5.3 DS-DE_attenuation budget
The total attenuation for each of the DS-DE signals (from output of the driver to input of the receiver) shall be less thanor equal to 6 dB at 100 MHz. This attenuation shall be divided following the guidelines given in table 5-17.

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SCALABLE SERIAL INTERCONNECT FOR PARALLEL SYSTEM CONSTRUCTION)IEEE Std 1355-1995

Table 5-17 —Attribution of attenuation budget
Parameter

Maximum
attenuation/dB

Output of driver to output of connector

0.5

Across cable

5

Input to connector and input of receiver

0.5

5.5.4 DS-DE skew budget
The skew shall be divided following the guidelines given in table 5-18.
Table 5-18 —Attribution of skew budget
Parameter

Maximum skew between D and S/ns
10 MBd100 MBd

200 MBd

Output of differential driver to output of connector

5

0.5

0.35

Across cable

15

1.5

1.3

Input to connector and input of differential receiver

5

0.5

0.35

If the DS-DE links are implemented by using transceivers to convert between the differential signals and thecorresponding single ended DS-SE signals, then the differential skew between D and S shall be controlled so that theresulting single ended signal respects the guidelines given in 5.3.1.
5.5.5 DS-DE link timing
DS-DE link timing is as for DS-SE timing (see 5.3.4, with references to DS-SE replaced by DS-DE).
5.5.6 EM Susceptibility
A system using DS-DE links shall meet or exceed IEC 801-4 specifications on EM susceptibility as a function of theintended operating environment. To reduce susceptibility to EMC it is recommended that it is ensured that the fixed
connector is connected to housings by using appropriate EMC brackets and/or gaskets (similar to B.3), or that small
common-mode chokes are used in series on the signal lines, and the power lines if connected. A suitable specification
for such chokes is 200 Ω min at 20–300 MHz, 800 Ω typ at 100 MHz.

5.6 DS-SE and DS-DE character level
In order to provide efficient support for higher level protocols, it is useful to be able to encode characters that may
contain a data byte or control information (in other standards these might be referred to as symbols). Each charactershall start with a parity bit followed by a control bit that is used to distinguish between data and control characters. In
addition to the parity and control bits, data characters contain 8 b of data, and control characters have 2 b to indicate
the character type. This is illustrated in figure 5-9.

Copyright © 1995 IEEE All Rights Reserved27IEEE Std 1355-1995

IEEE STANDARD FOR HETEROGENEOUS INTERCONNECT (HIC) (LOW-COST, LOW-LATENCY

Figure 5-9 —-DS-SE/DS character encoding
Data bits shall be transmitted using the “little endian” convention, i.e., the least significant bit of data shall betransmitted first (immediately after the zero control bit). The first bit transmitted after a reset state shall be a zero(which implies that the first transition is on the strobe wire).
The parity bit in any character covers the parity of the data/control flag in the same character, and the data or control
bits in the previous character, as in figure 5-10. This allows an error in any single bit of a character, including thecharacter type flag, to be detected even though the characters are not all the same length. The parity bit is set such thatthe total number of 1s in all the bits covered (including the parity bit) is odd.

Figure 5-10 —DS-SE/DS-DE parity coverage
DS-SE/DS-DE links code the N_chars EOP_1 and EOP_2 as shown in table 5-19, in which P indicates the position of
the parity bit in the character.
DS-SE/DS-DE links define and code L_chars as shown in table 5-20, and their application is discussed in 5.7.
The null character is composed of two characters. The scope of the parity bit in a character that follows a null character
includes only the second 4 b control character of the null character; i.e., it will be a one if the following character is adata character, and will be a zero if following character is a control character.

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SCALABLE SERIAL INTERCONNECT FOR PARALLEL SYSTEM CONSTRUCTION)IEEE Std 1355-1995

Table 5-19 —Terminator character codings
Name

Description

Code

EOP_1

Normal end_of_packet marker

P101

EOP_2

Exceptional end_of_packet marker

P110

Table 5-20 —Link control character codings
Name

Description

Code

FCC

Flow control character

P100

ESC

Escape character

P111

NULL

Null character

ESC P100

5.7 DS-SE and DS-DE exchange level
5.7.1 GeneralOnce a link output has been started it shall send characters continuously at such a rate that the bit time constraints given
in table 5-2 are never exceeded, unless and until instructed to cease operation or an error is detected. In the absence ofother characters, a DS-SE/DS-DE link transmits NULL characters. This ensures the following:a)b)

Physical disconnection of a link detected; because a DS-SE/DS-DE link transmits characters continuously
even in message, a physical disconnect can be assumed if the inputting link detects that there are nocharacters being received, given that some have been received previously.
The final parity bit of a packet is transmitted immediately; because the parity of each character is validated by
the parity bit of the following character, the validation of the final character of a packet would otherwise bedelayed for an arbitrary amount of time.

5.7.2 DS-SE and DS-DE initialization
After reset, a DS-SE link output shall maintain both signals at their reset level until started, i.e., instructed to begin
operation (note that receipt of a character by the corresponding link input may be taken as such an instruction).
Thereafter it shall send only NULL characters unless and until at least one character has been received by thecorresponding link input since reset. After the link output has been started and at least one character has been received
by the corresponding link input since reset, the link shall begin normal operation. In normal operation, N_chars
provided for transmission are sent when there is flow control credit available, and flow control credit is issued bytransmitting FCCs corresponding to available space in the link input buffer. A timeline diagram illustrating DS-DE and
DS-DE initalization and reset is given in figure 5-12.
If a link interface is reset during normal operation, then it shall cease to transmit. This will be detected as a
disconnection error by the receiving interface, which then will also cease to transmit. After the exchange of silence
protocol, described in 5.7.4.2 and illustrated in figures 5-11 and 5-12, both ends of the link will enter the ready stateand normal operation may begin. The exchange of silence protocol allows the reset procedure to have the desired effectif the two links are operating in separate reset domains

Copyright © 1995 IEEE All Rights Reserved29IEEE Std 1355-1995

IEEE STANDARD FOR HETEROGENEOUS INTERCONNECT (HIC) (LOW-COST, LOW-LATENCY

Figure 5-11 —DS link states
5.7.3 Flow control
The credit value (F) of each Flow Control Character (FCC) is set at 8 N_chars.
5.7.4 DS-SE and DS-DE error detection
5.7.4.1 General
DS-SE/DS-DE links can detect various types of errors. The handling of link errors is a subject of annex G.
The DS-SE/DS-DE link exchange protocol allows two common types of error to be detected. First, because each
output link, once started, continues to transmit an uninterrupted stream of characters, the physical disconnection of a30

Copyright © 1995 IEEE All Rights Reserved

SCALABLE SERIAL INTERCONNECT FOR PARALLEL SYSTEM CONSTRUCTION)IEEE Std 1355-1995

link can be detected. Second, the parity system will detect all single bit errors at the DS-SE/DS-DE link exchange
level.

Figure 5-12 —DS link start-up and reset
5.7.4.2 Disconnection errors
If the links are disconnected for any reason while they are running, then flow control and character synchronization
may be lost. In order to restart the link it is therefore necessary to reset both ends to a known flow control and charactersynchronization point.
Disconnection is detected if, after a bit has been received, no bits are seen by a link input in any 850 ns window. Oncea disconnection error has been detected the link shall halt its output. This will subsequently be detected as a disconnect
error at the other end, and will cause that link to halt its output also. Once the output has halted, the link shall reset bothits transmitter and its receiver for 6.4 µs, during which time its receiver is insensitive to transitions on the data and

Copyright © 1995 IEEE All Rights Reserved31IEEE Std 1355-1995

IEEE STANDARD FOR HETEROGENEOUS INTERCONNECT (HIC) (LOW-COST, LOW-LATENCY

strobe inputs. After this, the link shall wait at least 12.8 µs before allowing communication to restart. This time issufficient to ensure that both ends of the link have observed disconnection and cycled through reset back into thewaiting state. The connection may now be restarted as described above. If a link interface detects a disconnect error
before it has started, it shall start, transmit at least one character, and then halt, to ensure that a disconnection error isalso detected by the other end, in the case that it was caused by an externally applied reset rather than physicaldisconnection. Figure 5-11 illustrates a suitable state machine for DS-SE and DS-DE error handling.
5.7.4.3 Parity errors
Following a parity error, both character-level synchronization and flow control status are no longer valid, therefore
both ends of the link must be reset. This is done autonomously by the DS-SE/DS-DE link using an exchange-of-silence
protocol.
When a link interface detects a parity error on its input it shall halt its output. This will subsequently be detected as a
disconnect error at the other end, and will cause that link interface to halt its output also, causing a disconnect to be
detected at the first end. The normal disconnect behavior described above will then ensure that both ends are reset(irrespective of line delay) before either is allowed to restart. If a link interface detects a parity error before it has been
started, it shall start, transmit at least one character, and then stop to ensure that a disconnection error is detected by theother end.

6. TS-FO-02 fiber optic link

6.1 Physical medium
6.1.1 General optical characteristics
The TS-FO-02 optical link cable is a fiber cable containing two fibers, one for transmission in each direction. A 62.5 µm
multimode fiber shall be used, and shall meet, at minimum, the specifications given in IEC 793-1 -A1-b. A summary of
the main optical characteristics (as specified in IEC 793-1 -Al-b) of the fiber is given in table 6-1.
The link cable shall be clearly marked “IEEE 1355 TS-FO Link Cable.” A recommendation for fiber construction is
given in annex S. (See also 10.3.)
Table 6-1 —Summary of main optical characteristics of TS-FO fibers
Parameter

Units

Value

—

MultimodeCore diameter

micrometers

62.5

Cladding diameter

micrometers

125

—

0.275

dB/km

4 maximum at 850 nm

Fiber type

NA
Attenuation

6.1.2 Optical connector
The TS-FO link optical connector is a MU connector-duplex. The MU connector-duplex consists of a through-panel(fixed) adapter and a cable mounted (free) plug. It provides the following features:a)

32

A dual multimode fiber connection per connector

Copyright © 1995 IEEE All Rights Reserved

SCALABLE SERIAL INTERCONNECT FOR PARALLEL SYSTEM CONSTRUCTION)b)c)IEEE Std 1355-1995

Push-pull coupling
Small size

The connectors shall be as specified in IEC 1754-6. Prior to approval of IEC 1754-6, annex C provides an interim
specification.
In addition to the interface specification of IEC 1754-6, the connectors shall have the properties described in table 6-2.
Table 6-2 —TS-FO connector modularity specifications
Characteristic

Specification

Modularity

Connector modules shall be placed on a 14 mm pitch, ortheir centerlines separated by more than 28 mm

Connector width

13.9 mm maximum

Overall connector length (to end of boot)55 mm maximum

The plug at either end of the cable shall be connected to the fibers in the cable in such a way as to connect ferrule 1 in
one plug with ferrule 2 in the other plug, and vice versa, as shown in figure 6-1.

Figure 6-1 —TS-FO cable fibers/plugs wiring
Note that the effect of the cable/plugs assembly is to provide a single twist. Any extension adapters allowing multiple
segments of cables to be used shall also provide such a twist, so that the effect of any such cable/adapter/cablecombination is to provide a single twist, as illustrated in figure 6-2.

Figure 6-2 —TS-FO extension adapter
The allocation of TS-FO signals to the plug ferrules and adapter shall he as given in table 6-3 (which is oriented tocorrespond to the external view of the through-panel (fixed) adapter when mounted on the upper surface of ahorizontal PCB; see figure 6-3). The direction of the signals is relative to the fixed adapter.

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33IEEE Std 1355-1995

IEEE STANDARD FOR HETEROGENEOUS INTERCONNECT (HIC) (LOW-COST, LOW-LATENCY

Figure 6-3 —TS-FO fixed adaptor, external view and ferrule allocation
Table 6-3 —TS-FO signal allocation
Ferrule2

1

SignalTS_FO_in

TS_FO_out

6.1.3 Environmental constraints
The environmental requirements for the TS-FO link cables and connectors are application dependent. However, as aminimum, the cables and connectors shall meet the constraints in table 6-4. Note that specific applications may haverequirements for extended temperature range or other environmental parameters.
Table 6-4 —TS-FO environmental constraints
Parameter

Value

Operating temperature–10 °C to +6 °C

Non-operating temperature–40 °C to +85 °C

Further environmental specifications are given in table C.2 (annex C).

6.2 Signal level
6.2.1 Transmitter and receiver characteristics
Launch power and sensitivity are strongly dependent on the kind of optical components used and on the configurationof the LED/laser modulation and of the photodiode amplifier. Table 6-5 gives the recommended transceivercharacteristics for an LED-based system.

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SCALABLE SERIAL INTERCONNECT FOR PARALLEL SYSTEM CONSTRUCTION)IEEE Std 1355-1995

Table 6-5 —TS-FO recommended transceiver characteristics
Value
Parameter

Units

Minimum

Typ

Maximum

Operating speed

MBd

—

—

250

TS-FO transmitter

—

—

—

—

(LED into 62.5 µm fiber)

—

—

—

—

Launch power

dBm

–13

—

–10

Wavelength

nm

760

—

900

Spectral width (FWHM)

nm

—

60

—

TS-FO receiver

—

—

—

—

Sensitivity atBER 10-12

dBm

–22

—

—

Dynamic range

dB

12

—

—

6.2.2 TS-FO link timing
The TS-FO link shall operate at 250 MBd ± 100 ppm.
6.2.3 TS-FO reference link
A link comprises of two link interfaces connected by appropriate media, and transmits information bidirectionally. For
specification and test purposes, a TS-FO Reference Link is defined as a transceiver (the link interface), connected bya pair of fibers to an adapter, connected by a plug-cable-plug assembly to another adapter, connected to anothertransceiver by a pair of fibers, as shown in figure 6-4. This figure also shows reference test points TP1–TP4 (where
TPx are at the extremities of the optical cable).

Figure 6-4 —TS-FO reference list
6.2.4 Link performance
The performance of the various components of the link system shall be as in table 6-6. The standard specifies a powerbudget for a link, i.e., the maximum loss. A “loopback” plug is defined as a single plug with a minimum length of fiberthat connects ferrule 1 to ferrule 2. This is used to provide the specification of the loss of a connector system and areference specification for the power budget for the cable assembly. The performance of a minimum length reference
cable is assumed to be equivalent to the performance of the loopback system. Note that this provides a high degree ofconfidence of interoperability within a practical test environment, but does not provide a guarantee of interoperability.
Copyright © 1995 IEEE All Rights Reserved

35IEEE Std 1355-1995

IEEE STANDARD FOR HETEROGENEOUS INTERCONNECT (HIC) (LOW-COST, LOW-LATENCY

Table 6-6 —TS-FO link performance specification
Characteristic

Specification

Test specification

Link length

300 m maximum

Power budget(total loss in a link)

6.5 dB maximum

TP1 to TP4 and TP3 to TP2

Loopback test loss

1.5 dB maximum

Loss between TP1 and TP2 using aloopback plug

5 dB maximum

Difference in loss between the loss
measured from TP1 to TP4 (and TP3
to TP2) with cable under test and theloopback test loss as defined above

Cable assembly additional
attenuation

6.2.5 Eye safety
IEC 825 is the most stringent standard for laser radiation eye safety. It is for the implementor to take appropriate
measures to ensure eye safety.

6.3 TS-FO character level
6.3.1 General
The coding is chosen to ensure that single-bit errors do not generate multiple-bit errors on decoding, and to avoid theoverheads of CRC checking (which would double the length of small packets).
6.3.2 Symbols
Each character is coded as two six-bit symbols, where each symbol has three ones and three zeros-hence the code is
described as a “three-of-six” code. There are twenty valid symbols that have three ones and three zeros, of which
sixteen values are used for data and two values are used for control. The remaining two values are unused. Table 6-7
shows the symbols allocated to the sixteen data nibbles [the symbols are drawn as on a oscilloscope trace, with theleast significant bit (i.e., the first transmitted) on the left].
Table 6-7 —Symbols allocated for character coding of data values

36

Hex

LSB-MSB

00110101101001

2011001

3110001400110151011006011100711010080010119100011

A

010011

B

110010C

001110D

100110E

010110F

100101

Copyright © 1995 IEEE All Rights Reserved

SCALABLE SERIAL INTERCONNECT FOR PARALLEL SYSTEM CONSTRUCTION)IEEE Std 1355-1995

This selection of data symbols for the particular four bit values has several advantages. Apart from the values 0 and F
the coding is systematic in respect of bits 0, 1, 3, and 4. The redundant bits, 2 and 5, are placed in such a manner as toguarantee transitions within each symbol in at least two locations, each location occurring in one of two places. Thus,
there will always be a transition either between the first and second bits or the second and third bits, and either between
the fourth and fifth bits or the fifth and sixth bits.
The symbols 000111 and 111000 are not utilized because they increase the run length and digital sum variation (DSV)of the code. Furthermore, the symbols 010101 and 101010 are not used for data symbols so as to limit the number ofadjacent alternating bits in a data stream, but are reserved as symbols used for control characters.
Control characters are formed by composing two symbols, called CONTROL and CONTROL*. Each of these two
symbols is always one of 101010 and 010101, depending upon the final bit of the preceding symbol, as shown intable 6-8.
Control characters are readily identifiable as having a greater number of transitions than any data symbol. Thisdefinition enablesa)b)

The boundaries between data characters and control characters to be easily identified.
Character synchronization to be checked.
Table 6-8 —Symbols for control characters
Previous symbol

CONTROL

CONTROL*xxxxx0010101101010xxxxx1101010010101

6.3.3 Data characters
Data characters are comprised of two data symbols. Bits 0 to 3 of each data character are transmitted by the firstsymbol and bits 4 to 7 are transmitted in the second symbol.
6.3.4 Control characters
The control characters NULL and FCC are comprised of CONTROL and CONTROL* symbols. The control
characters EOP_1 and EOP_2 are comprised of a control symbol and a data symbol, where the data symbol is thelongitudinal error check code described in 6.4.4.2. See table 6-9.
Table 6-9 —Coding of control characters
Control character
NULL

FCC

EOP_1

EOP_2

Symbols

Previous symbol

Symbols (binary)

CONTROL CONTROL*

xxxxx1101010 101010

xxxxx0010101 010101

xxxxx1101010 010101

xxxxx0010101 101010

xxxxx1101010 checksum

xxxxx0010101 checksum

checksum=xxxxx1

checksum 101010

checksum=xxxxx0

checksum 010101

CONTROL CONTROLCONTROL checksum

checksum CONTROL

Copyright © 1995 IEEE All Rights Reserved37IEEE Std 1355-1995

IEEE STANDARD FOR HETEROGENEOUS INTERCONNECT (HIC) (LOW-COST, LOW-LATENCY

A final control character, comprised of four symbols, is used for initialization. This is a sequence of as manytransitions as possible, as shown in table 6-10.
Table 6-10 —Coding of INIT
Control character
INIT

Symbols

Previous symbol

Symbols (binary)

CONTROL CONTROL*CONTROL* CONTROL*

xxxxx1101010101010101010101010xxxxx0010101010101010101010101

6.4 TS-FO exchange level
6.4.1 General
In normal operation and in the absence of other characters, a TS-FO link shall transmit NULL characters.
6.4.2 Initialization
When a link interface starts it shall transmit INIT characters. The very first INIT character is selected by assuming a“previous” symbol of xxxxx0. When a link interface has been both transmitting and receiving INIT characters for 125 µs± 5 µs, it shall then send NULL characters. When a link interface has been transmitting and receiving NULL charactersfor at least 125 µs ± 5 µs, it shall then transmit a single INIT character, followed by NULL characters. When a linkinterface has both sent and received a single INIT character, it may send FCC characters. When a link interface hasreceived at least one FCC, it is free to start normal operation. An appropriate state machine is illustrated in figure 6-5 anda timeline in figure 6-6.
If a link interface has been sending NULL characters for more than 400 µs, but has not received the INIT character, or
if the link interface has received any character other than NULL since the first NULL character it received and before
the INIT and FCC characters, the link interface shall restart the initialization sequence by reverting to transmitting
continuous INIT characters.

Figure 6-5 —TS link states
38

Copyright © 1995 IEEE All Rights Reserved

SCALABLE SERIAL INTERCONNECT FOR PARALLEL SYSTEM CONSTRUCTION)IEEE Std 1355-1995

6.4.3 Flow control
Exchange level flow control (i.e., control of the flow of characters between link interfaces) shall be performed on eachlink. The additional characters used are not visible to the higher-level packet protocol.
The credit value (F); of each Flow Control Character (FCC) is set at 16 N_chars.
6.4.3.1 Maximum transmission line length and latency
The appropriate formulas are given in annex H. Note that in a given implementation, the appropriate N_char sink size
will have to be chosen in order to prevent the flow control mechanism periodically stalling the data flow over long
lengths of fiber.
6.4.4 Error detection
Although DS-SE/DE, and fiber interfaced TS-FO lines are designed to be reliable, the attenuation, dynamic range, anddistance of fiber connected links mean they are prone to errors and these errors shall be detected.
Checks are applied to the connection itself, to packets, to characters, to symbols, and to bit-sequences.

Figure 6-6 —TS link start-up and reset

Copyright © 1995 IEEE All Rights Reserved

39IEEE Std 1355-1995

IEEE STANDARD FOR HETEROGENEOUS INTERCONNECT (HIC) (LOW-COST, LOW-LATENCY

6.4.4.1 Disconnection
During normal operation, if a link interface is reset, it shall start transmitting INIT characters and shall revert to theinitialization sequence. During normal operation, the reception of at least two consecutive INIT characters implies
disconnection. This allows links operating in separate reset domains to resynchronize correctly.
6.4.4.2 Packets checked with longitudinal error check code
The code for each symbol allows an unusually rigorous check, checking for all single-bit errors and only missing
errors when one bit is turned from a one to a zero, and another is turned from a zero to a one. Such errors shall be
detected by a longitudinal check covering all the data symbols in the packet. The check used shall be a longitudinaleven parity check of the nibbles of each data character. The data characters and the parity are subsequently encoded as
six bit data symbols.
The four check bits shall be converted into the corresponding data symbol for transmission, decoded on receipt, andcompared with the check computed from the received data symbols. The conversion of a packet into its encoded form,
incorporating the encoded parity in either the EOP_1 or the EOP_2 character, as desired, is shown in figure 6-7.

Figure 6-7 —TS-FO packet encoding

40

Copyright © 1995 IEEE All Rights Reserved

SCALABLE SERIAL INTERCONNECT FOR PARALLEL SYSTEM CONSTRUCTION)IEEE Std 1355-1995

6.4.4.3 Character level checks
All characters shall be checked. Any illegal character that is not otherwise reported as being a symbol orsynchronization error shall result in immediate link reset.
6.4.4.4 Bit-level checks and synchronization
Once the receiver has established character boundaries, it should stay in synchronization with these characterboundaries thereafter. If a control character is received that is not in synchronism, an error has occurred.
The INIT, NULL and FCC characters all have at least nine alternating bits, whereas the longest length of alternating
bits possible with data characters is eight. If a count is detected, therefore, of nine alternating bits, there should be
exactly three more bits to make the character; if there are more or fewer bits to the character boundary, synchronization
has been lost.
6.4.4.5 Recovery of character synchronization
On loss of character synchronization, the receiver shall disconnect and reinitialize, or shall attempt to resynchronize
with the new timing. In either case, the (part) packet immediately preceding the loss of synchronization shall bediscarded. If the receiver attempts to resynchronize without reinitializing, the (part) packets received until after
synchronization has been reestablished shall also be discarded. The receiver shall not set itself into synchronization
until it has received at least two control characters with the same character boundary.

7. HS-SE-10

7.1 HS-SE physical medium
7.1.1 General electrical characteristics
7.1.1.1 Characteristic impedance
The characteristic impedance of the complete transmission line from the serial output buffer to the serial input buffer
shall be 50 Ω ± 10%.
7.1.1.2 Other characteristics
Other characteristics are given in table 7-1.
Table 7-1 —HS-SE-10 links general characteristic
Characteristics

Value
Min.

Max.

—

5%

ESD susceptibility

12 kV

—

Sector noise

1 kV

—

E field

3 V/m—

CrosstalkA system built using HS-SE links shall meet CISPR 22 regulations concerning electromagnetic emissions.

Copyright © 1995 IEEE All Rights Reserved

41IEEE Std 1355-1995

IEEE STANDARD FOR HETEROGENEOUS INTERCONNECT (HIC) (LOW-COST, LOW-LATENCY

7.1.2 Printed circuit board (PCB)
A PCB track carrying HS-SE signals shall have the characteristics given in table 7-2.
Table 7-2 —PCB track characteristics
Characteristic

Value

Characteristic impedance at 1 GHz

50 Ω ± 10%

Crosstalk between adjacent tracks

2%

The maximum recommended bend angle is 120 °.
7.1.3 Single minicoaxial cableThis subclause describes the basic characteristics of a single minicoaxial cable.
7.1.3.1 PhysicalThe physical characteristics of a single minicoaxial cable shall be as in table 7-3.
Table 7-3 —Physical characteristics of a single coaxial cable
Characteristic

Value

Central conductor size

AWG 22External diameter

2.85 mm maximum

These characteristics are needed in order to be compatible with the coaxial contact.
7.1.3.2 Electrical
The electrical characteristics of a single minicoaxial cable shall be as in table 7-4.
Table 7-4 —Electrical characteristics of a single coaxial cable
Characteristic

Value

Characteristic impedance

50 Ω ±10%7.1.4 Link cable
7.1.4.1 General
The basic bidirectional HS Link cable contains two coaxial cables (one for each direction), and is referred to as“single-link” cable. All the individual coaxial cables in a link cable shall conform to the characteristics describedabove.
7.1.4.2 Shielding
A link cable may be shielded or unshielded (double braid or single braid respectively; see figure 7-10). Double
braiding may be used in order to comply with the EMC specifications and to protect the transmission line from42

Copyright © 1995 IEEE All Rights Reserved

SCALABLE SERIAL INTERCONNECT FOR PARALLEL SYSTEM CONSTRUCTION)IEEE Std 1355-1995

external noise sources. Link cables supplied for use outside a box shall be shielded. Link cables for use inside a box
may be shielded.
A recommendation for the shielded cable is given in annex P.
The link cable shall be clearly marked “IEEE 1355 HS-SE Link Cable (shielded)” or “IEEE 1355 HS-SE Link Cable(unshielded)” as appropriate. (See also 10.3.)

Figure 7-1 —Single braid and double braid link cables
7.1.4.3 Mechanical performance
Link cables shall have mechanical performance and safety certification as given in table 7-5.
Table 7-5 —Mechanical performance and safety certification of link cables
Mechanical performance
Characteristic
Minimum bending radius (static operation)

Value (shielded)
30 mm

Value (unshielded)
30 mm

Safety certification
For cables up to 3 m (10 ft) in the US

UL listing: AWM style 20276, 80C, 30 V, VW1

For cables 3 m (10 ft) to 100 m

UL listed class 2 power limited circuit cable (CL2)

7.1.5 Link connectors
7.1.5.1 General
The connector system consists of a cable-mounted free connector; and a PCB-mounted through-panel fixed connector.
It provides the following features:
a)
b)
c)
d)

A single link connection per connector
Option for multiple connections on the cable connector
Complete screening
RobustCopyright © 1995 IEEE All Rights Reserved

43IEEE Std 1355-1995

e)f)IEEE STANDARD FOR HETEROGENEOUS INTERCONNECT (HIC) (LOW-COST, LOW-LATENCY

Latch fixing (screw fixing may be used as an option)
Small size

The connectors and coaxial contacts shall be as specified in IEC 1076-4-107. See annex B.
The connector at either end of the single link cable shall be connected to the central conductors of the two coaxial
cables in the cable in such a way as to connect pin a in one connector with pin b in the other connector, and vice versa,
i.e., as shown in figure 7-2.

Figure 7-2 —HS-SE cable pins/connectors wiring
Note that the effect of the cable/connector assembly is to provide a single twist. Any extension adapters allowing
multiple segments of cables to be used shall also provide such a twist, so that the effect of any such cable/adapter/cablecombination is to provide a single twist, as illustrated in figure 7-3.

Figure 7-3 —HS-SE extension adapter
The allocation of signals to the connector pins shall be as given in table 7-6 (which is oriented to correspond to theexternal view of the through-panel (fixed) connector when mounted on the upper surface of a horizontal PCB; seefigure 7-4). The direction of the signals is relative to the through-panel (fixed) adapter.

Figure 7-4 —HS-SE fixed connector external view
Table 7-6 —Pin allocation of HS-SE connectorb

HS_SE_ina

HS_SE_out

In addition to the interface specification of IEC 1076-4-107 , the connectors shall have the properties described intable 7-7.

44

Copyright © 1995 IEEE All Rights Reserved

SCALABLE SERIAL INTERCONNECT FOR PARALLEL SYSTEM CONSTRUCTION)IEEE Std 1355-1995

Table 7-7 —HS-SE environmental constraints
Characteristic

Specification

Modularity

Fixed connector modules shall be placed on a 6 mm
pitch, or their centerlines separated by more than 12 mm

Connector width

5.9 mm maximum

Annex O provides a recommendation for the PCB layout for the fixed connector.
7.1.6 Environmental constraints
The environmental requirements for the HS-SE link cables and connectors are application dependent. However, as aminimum, the cables and connectors shall meet the constraints in table 7-8. Note that specific applications may haverequirements for extended temperature range, or other environmental parameters.
Table 7-8 —HS-SE environmental constraints
Parameter

Value

Operating temperature–10 °C to +60 °C

Non-operating temperature–4 °C to +85 °C

7.2 HS-SE signal level
7.2.1 General
HS-SE-10 signal levels are single ended. A HS-SE link shall operate in the ranges given in table 7-9.
Table 7-9 —Operating rates for HS-SE-10 links
Characteristic
Operating signalling speed
Bit period

Value
700 MBd to 1 GBd
1.428 ns to 1 ns

Maximum rise and fall time at the transmitter (10–90%)

300 psMinimum rise and fall time at the transmitter (10–90%)

100 ps

The electrical model of the link input and output buffers is shown in figure 7-5.

Copyright © 1995 IEEE All Rights Reserved

45

IEEE Std 1355-1995

IEEE STANDARD FOR HETEROGENEOUS INTERCONNECT (HIC) (LOW-COST, LOW-LATENCY

Figure 7-5 —Input and output buffer electrical model
The receiver amplifier should be polarized around its switching threshold, nominally at V DD/2 for a CMOS inverter.
This results in a maximum receiver sensitivity. The receiver input impedance (defined by R3 // R4) shall be 50 Ω 10%.
The driver is modeled by two current sources, pulling the line to logic level 1 or logic level 0 as a function of the bit to
be sent.
The nominal signal levels corresponding to these logic levels are as follows:VDD
Vs = threshold voltage of the receiver amplitude ≈ ----------

2

and(VS−VL) = (VH − VS) ≈ 400 mV
where
VL is voltage level corresponding to logic level 0 on the line
VH is voltage level corresponding to logic level 1 on the line
andR3//R4 = Zc
where
Zc is characteristic impedance of the transmission line (50 W)

46

Copyright © 1995 IEEE All Rights Reserved

SCALABLE SERIAL INTERCONNECT FOR PARALLEL SYSTEM CONSTRUCTION)IEEE Std 1355-1995

7.2.2 Attenuation budget
The total attenuation for each of the HS-SE signals (from output of the driver to input of the receiver) shall be less thanor equal to 7.6 dB at 500 MHz. This attenuation shall be divided following the guidelines given in table 7-10.
Table 7-10 —Attribution of attenuation budget
Maximum
attenuation (dB)Parameter
Output of driver to output ofconnector

0.8

Across cable

6

Input to connector and input ofreceiver0.8

7.2.3 Line signal levels—driver side
Owing to the nature of the line signal levels, the latter should be observed via a high impedance probe on a fully
connected line. For observation purposes at the driver side of the line, the line loss of the transmission medium shallbe less than 0.5 dB. The levels shall meet the requirements shown in table 7–11 for VDD = 3.3 V(nominal) and table
7-12 for V DD = 5.0 V(nominal).
Table 7-11 —Driver side line logic levels for VDD = 3.3 V (nominal)
SymbolParameter

Units

Min.

Typ

Max.

VOLS

Serial output low level

V

1.15

1.25

1.35

VOHS

Serial output high level

V

1.95

2.05

2.15

Table 7-12 —Driver side line logic levels for VDD = 5.0 V (nominal)
SymbolParameter

Units

Min.

Typ

Max.

VOLS

Serial output low level

V

2.0

2.1

2.2

VOHS

Serial output high level

V

2.8

2.9

3.0

Alternatively, the output of the driver may be ac coupled (see below) directly into the 50 Ω termination of an
oscilloscope. This allows measurement of the line swing only (as dc levels are masked by the ac coupling). The swings
shall meet the requirements shown in table 7-13.
Table 7-13 —Driver side line swing when ac coupled into 50 Ω termination
SymbolVSW

Parameter
Serial line swing

Units

Min.

Typ

Max.

V

0.6

0.8

1.0

7.2.4 AC coupling of the link
The HS Link 8B/12B coding scheme is dc balanced, with a maximum disparity of 8 b. This dc balance allows the code
to be transmitted across ac coupled links, which is advantageous for both fiber and coaxial cable systems. Therefore
the HS-SE-10 links using such media should be ac coupled.

Copyright © 1995 IEEE All Rights Reserved

47

IEEE Std 1355-1995

IEEE STANDARD FOR HETEROGENEOUS INTERCONNECT (HIC) (LOW-COST, LOW-LATENCY

If the ac coupling poles are too high in frequency, long strings of 1s or 0s will distort and degrade the opening of thedata eye. This distortion is called baseline wander. In order for the baseline wander to degrade the eye opening by lessthan 4% of the total, the ac coupling needs to follow the following guidelines:a)b)

If the node (transmit or receive) has a single dominant ac coupling pole in series, the pole frequency shall be
800 kHz or lower.
If the node (transmit or receive) has two equal ac coupling pole in series, the pole frequency shall be 400 kHz
or lower.

Transformer coupling or capacitive coupling may be used.
Because of static electricity considerations, it is undesirable to leave the cable conductors completely isolated fromground. A bleeder resistor (10 MΩ) should be included.
For HS Links that operate between two components on the same PCB (i.e., using only PCB tracks), ac coupling may
be used, but is less essential.
7.2.5 Receiver electrical
The receiver shall meet the electrical characteristics given table 7-14.
Table 7-14 —Receiver electrical characteristics
Characteristic

Value

Minimum sensitivity

250 mV

Maximum input voltage

1200 mV peak-to-peak

Minimum discrete connector return loss

20 dB

7.2.6 EM susceptibility
A system using HS-SE links shall meet or exceed IEC 801-4 specifications on EM susceptibility as a function of theintended operating environment.

7.3 HS character level (8B/12B code)
7.3.1 General
The HS-SE-10 uses an 8B/12B dc balanced code. This code provides the following features:
a)
b)
c)
d)

A positive going synchronization transition at the beginning of every character, to simplify clock recovery
An odd parity bit per character, enabling the detection of single bit errors
DC balance, with a maximum disparity of 8 b
Out-of-bound control characters

7.3.2 Transmission characters
Define d[7:0] to be the byte to be transmitted, where d[7] is the most significant bit. To each byte, an odd parity, AP,and an inversion bit, I, are added to form the encoded character (on 10 b). The transmission character (on 12 b) is theencoded character plus the Start (1) and Stop (0) bits that provide the positive going synchronization transition.
The transmission character therefore has the form:

48

Copyright © 1995 IEEE All Rights Reserved

SCALABLE SERIAL INTERCONNECT FOR PARALLEL SYSTEM CONSTRUCTION)

Start (‘1’)

APe[0] e[1] e[2] e[3] e[4] e[5] e[6] e[7]Invert, I

IEEE Std 1355-1995

Stop (‘0’)

wheree[7:0] is d[7:0] or d[7:0], as defined in 7.3.3.
On the serial line the bits shall be sent in the order Start to Stop ([0] = LSB).
The AP bit is defined as follows:
AP is 1 if there is an even number of 1s in e[7:0] and I
AP is 0 if there is an odd number of 1s in e[7:0] and I
7.3.3 DC balance
A code that is dc balanced is one that has a constant dc component regardless of the data pattern. This provides many
advantages for high data rate transmission on fibre optic and long distance copper media.
Assigning +1 and –1 to bit levels 1 and 0 respectively provides a measure of the dc component in each transmitted
character. The disparity, D, of a data word is the difference between the number of 1s and the number of 0s in theword—positive and negative disparities refer to an excess of 1s and 0s respectively. The running disparity, RD, is therunning (cumulative) sum of the disparities of all previous characters. In a code that is “ideally” dc balanced eachtransmitted character has a D = 0 and thus RD is always equal to 0. However, perfect dc balance is not required inpractice.
To maintain dc balance, a non-zero RD has always to tend towards zero. For each character to be sent, the following
algorithm is used: calculate the disparity D of the encoded character (since the Start and Stop bits are 1 and 0
respectively, they do not affect the disparity) with I = 0. If the result will reduce the absolute value of RD, then transmit
the character as it is (i.e., e[7:0] = d[7:0], I = 0). If the result will increase the absolute value of RD, then invert theencoded character and set I = 1 (i.e., e[7:0] = d[7:0], I = 1), so that the inverted character reduces or leaves unchanged
the absolute value of RD. The receiver uses the bit I to determine whether the character has been inverted or not. By
its definition, the AP is also inverted if d[7:0] and I are inverted. In summary:

If RD ≤ 0 and D > 0 then I = 0, e[7:0] = d[7:0](character non-inverted)

If RD < 0 and D ≤ 0 then I = 1, e[7:0] = d[7:0](character inverted)

If RD ≥ 0 and D < 0 then I = 0, e[7:0] = d[7:0](character non-inverted)

If RD > 0 and D ≥ 0 then I = 1, e[7:0] = d[7:0](character inverted)

If RD = 0 and D = 0 then I = 1, e[7:0] = d[7:0](character inverted)

7.3.4 Control characters
When the disparity of the encoded character is zero it does not effect the RD, and can therefore be transmitted either
non-inverted or inverted. This property enables the transmission of control characters. As defined above, if D = 0, thecharacter is transmitted inverted. Control characters are therefore defined as characters that have D = 0 but aretransmitted non-inverted. This gives 126 possible control characters.

Copyright © 1995 IEEE All Rights Reserved49

IEEE Std 1355-1995

IEEE STANDARD FOR HETEROGENEOUS INTERCONNECT (HIC) (LOW-COST, LOW-LATENCY

7.3.5 The code
Table 7-5 details the 256 data characters, giving the decimal value, the binary value, the transmission character and thedisparity. For data characters which have a D ≠ 0, the non-inverted (first row) and inverted forms (second row) of thecharacter is shown. Note that D can take the values 0, ± 4 and ± 8 only.
Table 7-16 details the 126 control characters, giving the control character ID (0 to 125), the decimal value, the binary
value, and the transmission character (the disparity being zero and the character being non-inverted).

Table 7-15— Data characters
Dec

Bin, d[0:7]

S—AP—e[0:7]–I—S

000000000

1 1 000000000 0–8

1 0 111111111 08

1 0 100000000 0–8

1 1 011111111 08

1 0 010000000 0–8

1 1 101111111 08

1 1 110000000 0–4

1 0 001111111 04

1 0 001000000 0–8

1 1 110111111 08

1 1 101000000 0–4

1 0 010111111 0

4

1 1 011000000 0–4

1 0 100111111 04

1 0 111000000 0–4

1 1 000111111 04

1 0 000100000 0–8

1 1 111011111 08

1 1 100100000 0–4

1 0 011011111 0

4

1 1 010100000 0–4

1 0 101011111 04

1 0 110100000 0–4

1 1 001011111 0

4

1 1 001100000 0–4

1 0 110011111 04

1 0 101100000 0

–4

1

2

3

4

5

6

7

8

9

10

11

12

13

50

10000000

01000000

11000000

00100000

10100000

01100000

11100000

00010000

10010000

01010000

11010000

00110000

10110000D

Copyright © 1995 IEEE All Rights Reserved

SCALABLE SERIAL INTERCONNECT FOR PARALLEL SYSTEM CONSTRUCTION)IEEE Std 1355-1995

Table 7-15— Data characters (Continued)
Dec

14Bin, d[0:7]01110000

S—AP—e[0:7]–I—S

D

1 1 010011111 04

1 0 011100000 0–4

1 1 100011111 0

41511110000

1 0 000011111 001600001000

1 0 000010000 0–8

1 1 111101111 08

1 1 100010000 0–4

1 0 011101111 0

4

1 1 010010000 0–4

1 0 101101111 04

1 0 110010000 0–4

1 1 001101111 0

4

1 1 001010000 0–4

1 0 110101111 04

1 0 101010000 0–4

1 1 010101111 04

1 0 011010000 0–4

1 1 100101111 0

4

17

18

19

20

21

22

10001000

01001000

11001000

00101000

10101000

01101000

2311101000

1 0 000101111 002400011000

1 1 000110000 0–4

1 0 111001111 04

1 0 100110000 0–4

1 1 011001111 04

1 0 010110000 0–4

1 1 101001111 0

4

25

26

10011000

01011000

27

11011000

1 0 001001111 002800111000

1 0 001110000 0–4

1 1 110001111 0

4

2910111000

1 0 010001111 0030011110001 0 100001111 003111111000

1 1 000001111 003200000100

1 0 000001000 0–8

1 1 111110111 0

8

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IEEE Std 1355-1995

IEEE STANDARD FOR HETEROGENEOUS INTERCONNECT (HIC) (LOW-COST, LOW-LATENCY

Table 7-15— Data characters (Continued)
Dec

Bin, d[0:7]

S—AP—e[0:7]–I—S

33

10000100

1 1 100001000 0–4

1 0 011110111 0

4

1 1 010001000 0–4

1 0 101110111 04

1 0 110001000 0–4

1 1 001110111 0

4

1 1 001001000 0–4

1 0 110110111 04

1 0 101001000 0–4

1 1 010110111 04

1 0 011001000 0–4

1 1 100110111 0

4

34

35

36

37

38

1100010000100100

10100100

01100100

39

11100100

1 0 000110111 004000010100

1 1 000101000 0–4

1 0 111010111 04

1 0 100101000 0–4

1 1 011010111 04

1 0 010101000 0–4

1 1 101010111 0

4

41

42

1001010001010100

43

11010100

1 0 001010111 004400110100

1 0 001101000 0–4

1 1 110010111 0

44510110100

1 0 010010111 004601110100

1 0 100010111 004711110100

1 1 000010111 004800001100

1 1 000011000 0–4

1 0 111100111 04

1 0 100011000 0–4

1 1 011100111 04

1 0 010011000 0–4

1 1 101100111 0

4

49

50

52

01000100D

10001100

01001100

51

11001100

1 0 001100111 005200101100

1 0 001011000 0–4

Copyright © 1995 IEEE All Rights Reserved

SCALABLE SERIAL INTERCONNECT FOR PARALLEL SYSTEM CONSTRUCTION)IEEE Std 1355-1995

Table 7-15— Data characters (Continued)
Dec

Bin, d[0:7]

S—AP—e[0:7]–I—S

D

1 1 110100111 045310101100

1 0 010100111 005401101100

1 0 100100111 005511101100

1 1 000100111 005600011100

1 0 000111000 0–4

1 1 111000111 0

45710011100

1 0 011000111 005801011100

1 0 101000111 005911011100

1 1 001000111 006000111100

1 0 110000111 006110111100

1 1 010000111 006201111100

1 1 100000111 006311111100

1 1 111111000 04

1 0 000000111 0–4

1 0 000000100 0–8

1 1 111111011 0

8

1 1 100000100 0–4

1 0 011111011 0

4

1 1 010000100 0–4

1 0 101111011 04

1 0 110000100 0–4

1 1 001111011 0

4

1 1 001000100 0–4

1 0 110111011 04

1 0 101000100 0–4

1 1 010111011 0

4

1 0 011000100 0–4

1 1 100111011 0

4

64

65

66

67

68

69

70

00000010

10000010

01000010

11000010

00100010

10100010

01100010

71

11100010

1 0 000111011 007200010010

1 1 000100100 0–4

1 0 111011011 04

1 0 100100100 0–4

1 1 011011011 0

473

Copyright © 1995 IEEE All Rights Reserved

10010010

53

IEEE Std 1355-1995

IEEE STANDARD FOR HETEROGENEOUS INTERCONNECT (HIC) (LOW-COST, LOW-LATENCY

Table 7-15— Data characters (Continued)
Dec

Bin, d[0:7]

S—AP—e[0:7]–I—S

74

01010010

1 0 010100100 0–4

1 1 101011011 047511010010

1 0 001011011 007600110010

1 0 001100100 0–4

1 1 110011011 0

47710110010

1 0 010011011 007801110010

1 0 100011011 007911110010

1 1 000011011 008000001010

1 1 000010100 0–4

1 0 111101011 04

1 0 100010100 0–4

1 1 011101011 0

4

1 0 010010100 0–4

1 1 101101011 0

4

81

82

10001010

01001010

83

11001010

1 0 001101011 008400101010

1 0 001010100 0–4

1 1 110101011 0

48510101010

1 0 010101011 008601101010

1 0 100101011 008711101010

1 1 000101011 008800011010

1 0 000110100 0–4

1 1 111001011 048910011010

1 0 011001011 009001011010

1 0 101001011 009111011010

1 1 001001011 009200111010

1 0 110001011 009310111010

1 1 010001011 009401111010

1 1 100001011 009511111010

1 1 111110100 04

1 0 000001011 0–4

1 1 000001100 0–4

1 0 111110011 04

1 0 100001100 0

–4

96

97

54

D

00000110

10000110

Copyright © 1995 IEEE All Rights Reserved

SCALABLE SERIAL INTERCONNECT FOR PARALLEL SYSTEM CONSTRUCTION)IEEE Std 1355-1995

Table 7-15— Data characters (Continued)
Dec

98

Bin, d[0:7]01000110

S—AP—e[0:7]–I—S

D

1 1 011110011 0

4

1 0 010001100 0–4

1 1 101110011 0

49911000110

1 0 001110011 0010000100110

1 0 001001100 0–4

1 1 110110011 0

410110100110

1 0 010110011 0010201100110

1 0 100110011 0010311100110

1 1 000110011 0010400010110

1 0 000101100 0–4

1 1 111010011 0

410510010110

1 0 011010011 0010601010110

1 0 101010011 0010711010110

1 1 001010011 0010800110110

1 0 110010011 0010910110110

1 1 010010011 0011001110110

1 1 100010011 0011111110110

1 1 111101100 04

1 0 000010011 0–4

1 0 000011100 0–4

1 1 111100011 0411200001110

113

10001110

1 0 011100011 00114

01001110

1 0 101100011 0011511001110

1 1 001100011 0011600101110

1 0 110100011 0011710101110

1 1 010100011 0011801101110

1 1 100100011 0011911101110

1 1 111011100 04

1 0 000100011 0

–4

120

00011110

1 0 111000011 0012110011110

1 1 011000011 00122

01011110

1 1 101000011 0012311011110

1 1 110111100 0

4

Copyright © 1995 IEEE All Rights Reserved

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IEEE Std 1355-1995

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Table 7-15— Data characters (Continued)
Dec

S—AP—e[0:7]–I—S

D

1 0 001000011 0

–4

124

00111110

1 1 110000011 0012510111110

1 1 101111100 04

1 0 010000011 0–4

1 1 011111100 04

1 0 100000011 0–4

1 0 111111100 04

1 1 000000011 0–4

1 0 000000010 0–8

1 1 111111101 08

1 1 100000010 0–4

1 0 011111101 0

4

1 1 010000010 0–4

1 0 101111101 04

1 0 110000010 0–4

1 1 001111101 0

4

1 1 001000010 0–4

1 0 110111101 04

1 0 101000010 0–4

1 1 010111101 04

1 0 011000010 0–4

1 1 100111101 0

4

126

127

128

129

130

131

132

133

134

011111101111111000000001

10000001

01000001

11000001

00100001

10100001

01100001

135

11100001

1 0 000111101 0013600010001

1 1 000100010 0–4

1 0 111011101 04

1 0 100100010 0–4

1 1 011011101 04

1 0 010100010 0–4

1 1 101011101 0

4

137

138

10010001

01010001

139

11010001

1 0 001011101 0014000110001

1 0 001100010 0–4

1 1 110011101 04

1 0 010011101 0

0

141

56

Bin, d[0:7]10110001

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SCALABLE SERIAL INTERCONNECT FOR PARALLEL SYSTEM CONSTRUCTION)IEEE Std 1355-1995

Table 7-15— Data characters (Continued)
Dec

Bin, d[0:7]

S—AP—e[0:7]–I—S

142

01110001

1 0 100011101 0014311110001

1 1 000011101 0014400001001

1 1 000010010 0–4

1 0 111101101 04

1 0 100010010 0–4

1 1 011101101 04

1 0 010010010 0–4

1 1 101101101 0

4

145

146

10001001

01001001

D

147

11001001

1 0 001101101 0014800101001

1 0 001010010 0–4

1 1 110101101 0

414910101001

1 0 010101101 0015001101001

1 0 100101101 0015111101001

1 1 000101101 00152000110011

1 0 000110010 0–4

1 1 111001101 0

415310011001

1 0 011001101 0015401011001

1 0 101001101 0015511011001

1 1 001001101 0015600111001

1 0 110001101 00157

10111001

1 1 010001101 0015801111001

1 1 100001101 0015911111001

1 1 111110010 0

4

1 0 000001101 0–4

1 1 000001010 0–4

1 0 111110101 04

1 0 100001010 0–4

1 1 011110101 04

1 0 010001010 0–4

1 1 101110101 0

4

160

161

162

00000101

10000101

01000101

163

11000101

1 0 001110101 0016400100101

1 0 001001010 0–4

1 1 110110101 0

4

Copyright © 1995 IEEE All Rights Reserved

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IEEE Std 1355-1995

IEEE STANDARD FOR HETEROGENEOUS INTERCONNECT (HIC) (LOW-COST, LOW-LATENCY

Table 7-15— Data characters (Continued)
Dec

Bin, d[0:7]

S—AP—e[0:7]–I—S

165

10100101

1 0 010110101 0016601100101

1 0 100110101 0016711100101

1 1 000110101 0016800010101

1 0 000101010 0–4

1 1 111010101 0416910010101

1 0 011010101 0017001010101

1 0 101010101 0017111010101

1 1 001010101 0017200110101

1 0 110010101 0017310110101

1 1 010010101 0017401110101

1 1 100010101 0017511110101

1 1 111101010 0

4

1 0 000010101 0–4

1 0 000011010 0–4

1 1 111100101 0417600001101

177

10001101

1 0 011100101 0017801001101

1 0 101100101 0017911001101

1 1 001100101 0018000101101

1 0 110100101 0018110101101

1 1 010100101 0018201101101

1 1 100100101 0018311101101

1 1 111011010 0

4

1 0 000100101 0

–4

184

00011101

1 0 111000101 0018510011101

1 1 011000101 0018601011101

1 1 101000101 0018711011101

1 1 110111010 0

4

1 0 001000101 0

–4

188

00111101

1 1 110000101 0018910111101

1 1 101111010 0

4

1 0 010000101 0–4

1 1 011111010 04

1 0 100000101 0

–4

190

58

D

01111101

Copyright © 1995 IEEE All Rights Reserved

SCALABLE SERIAL INTERCONNECT FOR PARALLEL SYSTEM CONSTRUCTION)IEEE Std 1355-1995

Table 7-15— Data characters (Continued)
Dec

Bin, d[0:7]

S—AP—e[0:7]–I—S

191

11111101

1 0 111111010 0

4

1 1 000000101 0–4

1 1 000000110 0–4

1 0 111111001 04

1 0 100000110 0–4

1 1 011111001 04

1 0 010000110 0–4

1 1 101111001 0

4

192

193

194

00000011

10000011

01000011

D

195

11000011

1 0 001111001 0019600100011

1 0 001000110 0–4

1 1 110111001 0419710100011

1 0 010111001 0019801100011

1 0 100111001 0019911100011

1 1 000111001 0020000010011

1 0 000100110 0–4

1 1 111011001 0420110010011

1 0 011011001 0020201010011

1 0 101011001 0020311010011

1 1 001011001 0020400110011

1 0 110011001 0020510110011

1 1 010011001 0020601110011

1 1 100011001 0020711110011

1 1 111100110 04

1 0 000011001 0–4

1 0 000010110 0–4

1 1 111101001 0420800001011

209

10001011

1 0 011101001 0021001001011

1 0 101101001 0021111001011

1 1 001101001 0021200101011

1 0 110101001 0021310101011

1 1 010101001 0021401101011

1 1 100101001 0021511101011

1 1 111010110 0

4

Copyright © 1995 IEEE All Rights Reserved

59IEEE Std 1355-1995

IEEE STANDARD FOR HETEROGENEOUS INTERCONNECT (HIC) (LOW-COST, LOW-LATENCY

Table 7-15— Data characters (Continued)
Dec

S—AP—e[0:7]–I—S

D

1 0 000101001 0

–4

216

00011011

1 0 111001001 0021710011011

1 1 011001001 0021801011011

1 1 101001001 0021911011011

1 1 110110110 04

1 0 001001001 0

–4

220

00111011

1 1 110001001 0022110111011

1 1 101110110 04

1 0 010001001 0–4

1 1 011110110 04

1 0 100001001 0–4

1 0 111110110 04

1 1 000001001 0–4

1 0 000001110 0–4

1 1 111110001 0

4

222

223

224

01111011

11111011

00000111

225

10000111

1 0 011110001 0022601000111

1 0 101110001 0022711000111

1 1 001110001 0022800100111

1 0 110110001 0022910100111

1 1 010110001 0023001100111

1 1 100110001 0023111100111

1 1 111001110 04

1 0 000110001 0

–4

232

00010111

1 0 111010001 0023310010111

1 1 011010001 0023401010111

1 1 101010001 0023511010111

1 1 110101110 04

1 0 001010001 0

–4

236

00110111

1 1 110010001 0023710110111

1 1 101101110 04

1 0 010010001 0–4

1 1 011101110 04

1 0 100010001 0

–4

238

60

Bin, d[0:7]01110111

Copyright © 1995 IEEE All Rights Reserved

SCALABLE SERIAL INTERCONNECT FOR PARALLEL SYSTEM CONSTRUCTION)IEEE Std 1355-1995

Table 7-15— Data characters (Continued)
Dec

Bin, d[0:7]

S—AP—e[0:7]–I—S

D

239

11110111

1 0 111101110 0

411000010001 0

–4

240

00001111

1 0 111100001 0024110001111

1 1 011100001 00242

01001111

1 1 101100001 0024311001111

1 1 110011110 04

1 0 001100001 0244

00101111

1 1 110100001 00245

10101111

1 1 101011110 04

1 0 010100001 0–4

1 1 011011110 04

1 0 100100001 0–4

1 0 111011110 04

1 1 000100001 0–4

1 1 111000 1 0

0

1 1 111000001 0024601101111247

11101111

248

00011111

Table 7-16—Control characters
ID

DecBin, d[0:7]

S—AP—e[0:7]I—S

0

15

11110000

1 1 11110000 0 012311101000

1 1 11101000 0 022711011000

1 1 11011000 0 032910111000

1 1 10111000 0 0430

01111000

1 1 01111000 0 0531111110001 0 11111000 0 063911100100

1 1 11100100 0 074311010100

1 1 11010100 0 084510110100

1 1 10110100 0 094601110100

1 1 01110100 0 0104711110100

1 0 11110100 0 0115111001100

1 1 11001100 0 0125310101100

1 1 10101100 0 0

Copyright © 1995 IEEE All Rights Reserved

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IEEE Std 1355-1995

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Table 7-16—Control characters (Continued)

62

ID

Dec

Bin, d[0:7]

S—AP—e[0:7]I—S

13

54

01101100

1 1 01101100 0 0145511101100

1 0 11101100 0 0155710011100

1 1 10011100 0 0165801011100

1 1 01011100 0 0175911011100

1 0 11011100 0 0186000111100

1 1 00111100 0 0196110111100

1 0 10111100 0 0206201111100

1 0 01111100 0 0217111100010

1 1 11100010 0 0227511010010

1 1 11010010 0 0237710110010

1 1 10110010 0 0247801110010

1 1 01110010 0 0257911110010

1 0 11110010 0 0268311001010

1 1 11001010 0 0278510101010

1 1 10101010 0 028

8601101010

1 1 01101010 0 0298711101010

1 0 11101010 0 0308910011010

1 1 10011010 0 0319001011010

1 1 01011010 0 032

9111011010

1 0 11011010 0 0339200111010

1 1 00111010 0 0349310111010

1 0 10111010 0 035

9401111010

1 0 01111010 0 036

9911000110

1 1 11000110 0 0

37

101

10100110

1 1 10100110 0 0

38

102

01100110

1 1 01100110 0 0

39

103

11100110

1 0 11100110 0 0

40

105

10010110

1 1 10010110 0 0

41

106

01010110

1 1 01010110 0 0

42

107

11010110

1 0 11010110 0 0

43

108

00110110

1 1 00110110 0 0

44

109

10110110

1 0 10110110 0 0

45

110

01110110

1 0 01110110 0 0

Copyright © 1995 IEEE All Rights Reserved

SCALABLE SERIAL INTERCONNECT FOR PARALLEL SYSTEM CONSTRUCTION)IEEE Std 1355-1995

Table 7-16—Control characters (Continued)
ID

Dec

Bin, d[0:7]

S—AP—e[0:7]I—S

46

113

10001110

1 1 10001110 0 0

47

114

01001110

1 1 01001110 0 0

48

115

11001110

1 0 11001110 0 0

49

116

00101110

1 1 00101110 0 0

50

117

10101110

1 0 10101110 0 0

51

118

01101110

1 0 01101110 0 0

52

120

00011110

1 1 00011110 0 0

53

121

10011110

1 0 10011110 0 0

54

122

01011110

1 0 01011110 0 0

55

124

00111110

1 0 00111110 0 0

56

135

11100001

1 1 11100001 0 0

57

139

11010001

1 1 11010001 0 0

58

141

10110001

1 1 10110001 0 0

59

142

01110001

1 1 01110001 0 0

60

143

11110001

1 0 11110001 0 0

61

147

11001001

1 1 11001001 0 0

62

149

10101001

1 1 10101001 0 0

63

150

01101001

1 1 01101001 0 0

64

151

11101001

1 0 11101001 0 0

65

153

10011001

1 1 10011001 0 0

66

154

01011001

1 1 01011001 0 0

67

155

11011001

1 0 11011001 0 0

68

156

00111001

1 1 00111001 0 0

69

157

10111001

1 0 10111001 0 0

70

158

01111001

1 0 01111001 0 0

71

163

11000101

1 1 11000101 0 0

72

165

10100101

1 1 10100101 0 0

73

166

01100101

1 1 01100101 0 0

74

167

11100101

1 0 11100101 0 0

75

169

10010101

1 1 10010101 0 0

76

170

01010101

1 1 01010101 0 0

77

171

11010101

1 0 11010101 0 0

78

172

00110101

1 1 00110101 0 0

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63IEEE Std 1355-1995

IEEE STANDARD FOR HETEROGENEOUS INTERCONNECT (HIC) (LOW-COST, LOW-LATENCY

Table 7-16—Control characters (Continued)

64

ID

Dec

Bin, d[0:7]

S—AP—e[0:7]I—S

79

173

10110101

1 0 10110101 0 0

80

174

01110101

1 0 01110101 0 0

81

177

10001101

1 1 10001101 0 0

82

178

01001101

1 1 01001101 0 0

83

179

11001101

1 0 11001101 0 0

84

180

00101101

1 1 00101101 0 0

85

181

10101101

1 0 10101101 0 0

86

182

01101101

1 0 01101101 0 0

87

184

00011101

1 1 00011101 0 0

88

185

10011101

1 0 10011101 0 0

89

186

01011101

1 0 01011101 0 0

90

188

00111101

1 0 00111101 0 0

91

195

11000011

1 1 11000011 0 0

92

197

10100011

1 1 10100011 0 0

93

198

01100011

1 1 01100011 0 0

94

199

11100011

1 0 11100011 0 0

95

201

10010011

1 1 10010011 0 0

96

202

01010011

1 1 01010011 0 0

97

203

11010011

1 0 11010011 0 0

98

204

00110011

1 1 00110011 0 0

99

205

10110011

1 0 10110011 0 0

100

206

01110011

1 0 01110011 0 0

101

209

10001011

1 1 10001011 0 0

102

210

01001011

1 1 01001011 0 0

103

211

11001011

1 0 11001011 0 0

104

212

00101011

1 1 00101011 0 0

105

213

10101011

1 0 10101011 0 0

106

214

01101011

1 0 01101011 0 0

107

216

00011011

1 1 00011011 0 0

108

217

10011011

1 0 10011011 0 0

109

218

01011011

1 0 01011011 0 0

110

220

00111011

1 0 00111011 0 0

111

225

10000111

1 1 10000111 0 0

Copyright © 1995 IEEE All Rights Reserved

SCALABLE SERIAL INTERCONNECT FOR PARALLEL SYSTEM CONSTRUCTION)IEEE Std 1355-1995

Table 7-16—Control characters (Continued)
ID

Dec

Bin, d[0:7]

S—AP—e[0:7]I—S

112

226

01000111

1 1 01000111 0 0

113

227

11000111

1 0 11000111 0 0

114

228

00100111

1 1 00100111 0 0

115

229

10100111

1 0 10100111 0 0

116

230

01100111

1 0 01100111 0 0

117

232

00010111

1 1 00010111 0 0

118

233

10010111

1 0 10010111 0 0

119

234

01010111

1 0 01010111 0 0

120

236

00110111

1 0 00110111 0 0

121

240

00001111

1 1 00001111 0 0

122

241

10001111

1 0 10001111 0 0

123

242

01001111

1 0 01001111 0 0

124

244

00101111

1 0 00101111 0 0

125

248

00011111

1 0 00011111 0 0

NOTE — Shaded control characters indicate that they are defined by
the exchange level or by the packet level.

7.4 HS exchange level
7.4.1 General
The exchange level shall perform the following functions that correspond to normal operation of a bidirectional link:
a)
b)
c)

Start-up
Shutdown
Flow control

The exchange level shall perform the following additional functions:Parity error detection and recovery
Receiver calibration loss detection and recovery
Disconnection detection and recovery
Reset

All exchange level functions remain invisible to the packet level during normal operation.
The exchange level uses the reserved L_chars detailed in table 7-17.

Copyright © 1995 IEEE All Rights Reserved

65IEEE Std 1355-1995

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Table 7-17 —Reserved L_chars for exchange level functions
SymbolControl character ID

Name

IDLE

0

Idle

START_REQ

5

Start request

START_ACK

1

Start acknowledge

STOP_REQ

2

Stop request

STOP_ACK

3

Stop acknowledge

STOP_NACK

4Stop negative acknowledge

FCC

125

Flow control

RESET

6

Reset

Consider two connected nodes, NODE_A and NODE_B (see figure 7-6). Each port is divided into two parts: atransmitter and a receiver, referred to as transmitter_A and receiver_A for NODE_A and transmitter_B and receiver_B
for NODE_B.
Each port has a N_char source (SOURCE_A and SOURCE_B) which supply N_chars to transmitter_A andtransmitter_B respectively and a N_char sink (SINK_A and SINK_B) which accept data from receiver_A andreceiver_B respectively.
Exchange level information (i.e., the L_chars detailed in table 7-17) generated and sent by, for example, transmitter_A,
are received and filtered by the receiver_B and passed directly to transmitter_B (and vice versa). L_chars shall not be
generated by the source nor written into the sink.
Each receiver shall have a flag, CAL, which indicates its state. When CAL is low, this indicates that the receiver is notcalibrated to the incoming serial data stream. When in this state, all characters shall be filtered by the receiver. When
CAL is high, this indicates that the receiver is calibrated to the incoming serial data stream. When in this state, all
N_chars shall be passed to the N_char sink and all L_chars shall be passed to the port's transmitter.
Each transmitter and receiver is controlled by a state machine. (See figure 7-7, figure 7-8, figure 7-9 and figure 7-10.)

66

Copyright © 1995 IEEE All Rights Reserved

SCALABLE SERIAL INTERCONNECT FOR PARALLEL SYSTEM CONSTRUCTION)IEEE Std 1355-1995

Figure 7-6 —Exchange level interconnection between two nodes

Figure 7-7 —Transmitter state machine controller—start-up
Copyright © 1995 IEEE All Rights Reserved

67IEEE Std 1355-1995

IEEE STANDARD FOR HETEROGENEOUS INTERCONNECT (HIC) (LOW-COST, LOW-LATENCY

Figure 7-8 —Transmitter state machine controller—functional

Figure 7-9 —Transmitter state machine controller—shutdown

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SCALABLE SERIAL INTERCONNECT FOR PARALLEL SYSTEM CONSTRUCTION)IEEE Std 1355-1995

Figure 7-10 —Receiver state machine controller
7.4.2 Start-up
A request to transmit in one direction automatically activates the complete bidirectional link, this being necessary toallow the exchange level functions. There are two different types of start-up possible:a)b)

Unidirectional
Bidirectional

The start-up procedure uses the L_char IDLE (control character ID = 0) in order to calibrate the receiver. IDLE has thecharacteristic that the only positive going edges in the character are the synchronization edges. This enables the clock
recovery circuit to correctly lock onto this edges.
7.4.2.1 Unidirectional start-up
In figure 7-6, NODE_A requests to transmit to NODE_B. At first the transmitter_A is started and IDLEs are sent tocalibrate receiver_B. When receiver_B is calibrated (flag CAL_B goes high), this automatically starts thetransmitter_B and IDLEs are sent to calibrate receiver_A. When receiver_A is calibrated, PORT_A sends a
start_request (START_REQ) to PORT_B. PORT_B responds by sending a start_acknowledge (START_ACK) to
PORT_A.
On receipt of START_ACK, PORT_A replies by sending a START_ACK to PORT_B. PORT_A becomes functional(see below). N_chars in the from A to B (if SOURCE_A is empty, IDLEs shall be sent) and flow when necessary.
On receipt of START_ACK, PORT_B SOURCE_B are transmitted from B to A (if SOURCE_B is empty, IDLEs shallbe sent) and flow control information is transmitted from B to A when necessary. Note that PORT_B is functional,
even if NODE_B has not been explicitly requested to transmit to NODE_A.
This exchange is shown in figure 7-11.
7.4.2.2 Bi-directional start-up
This is the case in which NODE_A and NODE_B request to transmit quasi-simultaneously (for example, they request
to transmit on power-up). IDLEs are sent in both directions and, when the appropriate CAL goes high, bothtransmitter_A and transmitter_B send START_REQ and both reply with START_ACK. Both then reply to the
START_ACK with another START_ACK (since each side does not “know” that it is a bi-directional start-up); theselast 2 START_ACKs have no effect.
This exchange is shown in figure 7-12.

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IEEE Std 1355-1995

IEEE STANDARD FOR HETEROGENEOUS INTERCONNECT (HIC) (LOW-COST, LOW-LATENCY

Figure 7-11 —Exchange for start-up, functional and shutdown

Figure 7-12 —Exchange for bidirectional start-up

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SCALABLE SERIAL INTERCONNECT FOR PARALLEL SYSTEM CONSTRUCTION)IEEE Std 1355-1995

7.4.3 Errors on start-up
7.4.3.1 Loss of START_REQ
In the case of a bidirectional start-up, it is possible that the START_REQ is sent before the opposite receiver iscalibrated (this is not possible during an unidirectional start-up). If this is the case, the START_REQ sent will befiltered and lost by the opposite port. Therefore, after a time-out period, tTO1, the START_REQ is resent. The value oftTO1 is given in table 7-18.
7.4.3.2 Destination node not connected or not under power
If a node requests to transmit and the opposite node is not connected or not under power, the transmitter state machine
will block in state Tx_Cal_1. If, after a time-out period tTO2, the transmitter state machine has not been able to indicate
to the port controller that it is functional, then it shall be returned to the Not_Working state. (Note: The same timeout
will cover any other failure to start up.) It is then for the port controller to signal the failure of start-up and to request
to transmit as and when appropriate (these details are outside the scope of this standard).
This functionality is desirable for two reasons:a)b)

The system is notified that there has been a failure of start-up on the link.
Fiber-optic safety. If the link is on a fiber-optic medium, and the fiber is disconnected, the laser must notcontinue to indefinitely emit into an open fiber for eye safety reasons.
Table 7-18 —Time-out values
Symbol

Unit

Value

tTO1

ms

5

tTO2

ms

50

7.4.3.3 Other errors
It is possible that other transmission errors (e.g., loss of receiver calibration, parity error, unexpected or no response
from opposite node) could interrupt the start-up mechanism. If any of these errors occur during start-up, the transmittershould return to the Not_Working state for the reasons stated above in 7.4.3.2.
7.4.4 Functional
7.4.4.1 General
When functional, the following information shall be sent across the link in order of decreasing priority:
a)
b)
c)

Link characters other than IDLE (primarily FCC, i.e., flow control information for the opposite going link)
N_chars in the SOURCE, in a flow-controlled manner (see 7.4.4.2)
IDLEs when there are no SOURCE N_chars to send (the SOURCE is empty), or when flow control prevents
the transmission of SOURCE N_chars

All L_chars shall be filtered by the receiver controller: IDLEs are discarded; other L_chars are passed to thetransmitter controller which acts appropriately on them. N_chars shall be written into the SINK.
7.4.4.2 Flow control
The credit value (F) of each Flow Control Character (FCC) is set at 32 N_chars.

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IEEE STANDARD FOR HETEROGENEOUS INTERCONNECT (HIC) (LOW-COST, LOW-LATENCY

A link interface shall send at least four other characters between each FCC. Note in particular that this may require atleast four IDLE characters to be transmitted after the first FCC on link startup. Note that in normal operation a linkinterface will issue an FCC for every 32 N_chars received, and therefore would normally transmit at least 32 characters
between each FCC.
7.4.4.3 Maximum transmission line length and latency
The appropriate formulae are given in annex H.
7.4.5 Link reset mechanism
A port may require to reset the bidirectional link (Request_Reset). The port sends the RESET L_char and its
transmitter passes to the Tx_Working_1 state. On receipt of RESET, the opposite port's transmitter passes into the
Tx_Working_2 state. The unidirectional start procedure then proceeds as described above (7.4.4.1). A Request_Resetalso implies a reset of the flow control: the transmitter resets its credit to zero and the receiver clears its sink andresends the appropriate number of FCCs.
7.4.6 Errors when functional
Note that a further discussion on the handling of errors is provided in annex G.
7.4.6.1 Loss of receiver calibration
Loss of receiver calibration on the incoming serial data stream is indicated by the flag CAL passing low. The port
whose receiver has lost calibration has two options in order to recalibrate the link:a)b)

Initiate the reset mechanism described in 7.4.5.
Hold its serial output low, which will force a receiver calibration error in the opposite port. The bidirectional
start-up procedure then proceeds as described in 7.4.2.2.

Calibration errors should be reported to the port controller for error logging purposes.
The handling of packets that have been interrupted by a loss of calibration is outside the scope of this standard.
7.4.6.2 Parity error detected
The precise handling of parity errors is outside the scope of this standard. Parity errors should be reported to the port
controller for error logging purposes.
If a parity error and a receiver calibration error occur simultaneously, the port should follow the calibration error
procedure described in 7.4.6.1.
7.4.7 Shutdown
The bidirectional link shall not be shutdown unless both NODE_A and NODE_B have requested a shutdown. This isdone by a request to stop demand from the port. The transmitter sends a stop_request (STOP_REQ). The response toa STOP_REQ is either a stop_acknowledge (STOP_ACK) if the opposite user is ready to stop, or astop_not_acknowledge (STOP_NACK) if the opposite user is not ready to stop. Once a request to stop has been
demanded, any new N_chars placed in the source shall not be transmitted: the transmitter shall only send L_chars(primarily IDLEs and FCCs). If the port receives a STOP_NACK in reply to its request_to_stop, it may restarttransmission by a request to transmit.
When shutdown, the transmitter is in the Not_Working state and the serial output shall be static.

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SCALABLE SERIAL INTERCONNECT FOR PARALLEL SYSTEM CONSTRUCTION)IEEE Std 1355-1995

8. HS-FO-10 fiber optic link

8.1 Physical medium
8.1.1 General optical characteristics
The HS-FO optical link cable is a fiber cable containing two fibers, one for transmission in each direction. 62.5 or 50 µm
multimode shall be used (50 µm allows longer reach), and shall meet at minimum, the specifications given in IEC 7931 -Al-a. Where even longer reach is required, a single-mode fiber, as specified in IEC 793-1 -B1, may be used. A
summary of the main optical characteristics (as specified in IEC 793-1 -Al-a and IEC 793-1 -B1) of these fibers is given
table 8-1.
The link cable shall be clearly marked “IEEE 1355 HS-FO Link Cable (multimode)” or “IEEE 1355 HS-FO Link
Cable (single-mode)” as appropriate. A recommendation for fiber construction is given in annex S. (See also 10.3.)
Table 8-1 —Summary of main optical characteristics of HS-FO fibers
Parameter
Fiber type

Units

Value

—

multimode

multimode

single-mode

Core diameter

micrometers

62.5

50

9

Cladding
diametermicrometers

125

125

125

—

0.275

0.2

—

dB/km

4 maximum at 850 nm

4 maximum at 850 nm

0.5 maximum at 1300 nm

NAAttenuation

8.1.2 Optical connector
The HS-FO link optical connector is a MU connector-duplex The MU connector-duplex consists of a through-panel(fixed) adapter and a cable mounted (free) plug. It provides the following features:
a)
b)
c)

A dual multimode or single-mode fiber connection per connector
Push-pull coupling
Small size

The connectors shall be as specified in IEC 1754-6. Prior to approval of IEC 1754-6 , annex C provides an interim
specification.
In addition to the interface specification of IEC 1754-6, the connectors shall have the properties described in table 8-2.
Table 8-2 —THS-FO connector modularity specifications
Characteristic

Specification

Modularity

Fixed connector modules shall be placed on a 14 mm
pitch, or their centerlines separated by more than 28 mm

Connector width

13.9 mm maximum

Overall connector length(to end of boot)55 mm maximum

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IEEE STANDARD FOR HETEROGENEOUS INTERCONNECT (HIC) (LOW-COST, LOW-LATENCY

The plug at either end of the cable shall be connected to the fibers in the cable in such a way as to connect ferrule 1 in
one plug with ferrule 2 in the other plug, and vice versa, as shown in figure 8-1.

Figure 8-1 —HS-FO cable fibers/plugs wiring
Note that the effect of the cable/connector assembly is to provide a single twist. Any extension adapters allowing
multiple segments of cables to be used shall also provide such a twist, so that the effect of any such cable/adapter/cablecombination is to provide a single twist, as illustrated in figure 8-2.

Figure 8-2 —HS-FO extension adapter
The allocation of HS-FO signals to the plug ferrules and adapter shall be as given in table 8-3 (which is oriented tocorrespond to the external view of the through-panel (fixed) adapter when mounted on the upper surface of ahorizontal PCB—see figure 8-3). The direction of the signals is relative to the fixed adapter.

Figure 8-3 —HS-FO fixed adapter, external view and ferrule allocation
Table 8-3 —HS-FO signal allocation
FerruleSignal2

1

HS_FO_in

HS_FO_out

8.1.3 Environmental constraints
The environmental requirements for the HS-FO link cables and connectors are application dependent. However, as aminimum, the cables and connectors shall meet the constraints in table 8-4. Note that specific applications may haverequirements for extended temperature range or other environmental parameters.

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Table 8-4 —HS-FO environmental constraints
Parameter

Value

Operating temperature–10°C to +60°C

Non-operating temperature–40°C to +85°C

Further environmental specifications are given in annex C.

8.2 Signal level
8.2.1 General
The HS-SE-10 electrical signal levels operate with a nominal swing of 800 mV, equivalent to ECL or PECL swings.
Because the link may be ac coupled, the electrical driver and receiver can be directly interfaced with standard fiber
optic transceiver components (which operate on ECL or PECL levels).
The ac coupling requirements are as for the HS-SE-10 electrical link (see 7.2.4).
8.2.2 Transmitter and receiver characteristics
Launch power and sensitivity are strongly dependent on the kind of optical components used and on the configurationof the LED/laser modulation and of the photodiode amplifier. Table 8-5 gives the recommended transceivercharacteristics for a laser based system for multimode fiber, and table 8-6 gives the recommended transceivercharacteristics for monomode fiber.
Table 8-5 —HS-FO recommended transceiver characteristics for multimode fiber
Parameter

Units

Value
Min.

Typ

Max.

MBd

—

—

1000

Launch power

dBm

–13

–11

Wavelength

nm

760

900

Spectral width FWHM

nm

—

60

—

Sensitivity at BER = 10-12

dBm

–21

—

—

Dynamic range

dB

10

—

—

Operating speed
HS-FO transmitter(Laser into 50 or 62.5 µm fiber)

HS-FO receiver

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Table 8-6 —HS-FO recommended transceiver characteristics for single mode fiber
Parameter

Units

Value
Min.

Typ

Max.

MBd

—

—

1000

Launch power

dBm

–12

—

–8

Wavelength

nm

1250

—

1340

Spectral width FWHM

nm

—

2

—

Sensitivity at BER = 10-12

dBm

–20

—

—

Dynamic range

dB

12

—

—

Operating speed
HS-FO transmitter

HS-FO receiver

8.2.3 HS-FO reference link
A link comprises of two link interfaces connected by appropriate media, and transmits information bidirectionally. For
specification and test purposes, a HS-FO Reference Link is defined as a transceiver (the link interface), connected bya pair of fibers to an adapter, connected by a plug-cable-plug assembly to another adapter, connected to anothertransceiver by a pair of fibers, as shown in figure 8-4. This figure also shows reference test points TPI-TP4 (where TPx
are at the extremities of the optical cable).

Figure 8-4 —HS-FO reference link
8.2.4 Link performance
The performance of the various components of the link system shall be as in table 8-7. The standard specifies a powerbudget for a link, i.e., the maximum loss. A “loopback” plug is defined as a single plug with a minimum length of fiber
which connects ferrule a to ferrule b. This is used to provide the specification of the loss of a connector system and areference specification for the power budget for the cable assembly. The performance of a minimum length reference
cable is assumed to be equivalent to the performance of the loopback system. Note that this provides a high degree ofconfidence of interoperability within a practical test environment, but does not provide a guarantee of interoperability.

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Table 8-7 —HS-FO link performance specification
Characteristic

Specification

Test specification

Link length (62.5 µm multimode fiber)

100 m maximum—

Link length (50 µm multimode fiber)

1000 m maximum—

Link length (single-mode fiber)

3000 m maximum—

Power budget (total loss in a link)

5.5 dB maximum

TPI to TP4 and TP3 to TP2

Loopback test loss

1.5 dB maximum

Loss between TP1 and TP2 using aloopback plug

Cable assembly additional attenuation

4 dB maximum

Difference in loss between the loss
measured from TP1 to TP4 (and TP3
to TP2) with cable under test and theloopback test loss as defined above

8.2.5 Eye safety
IEC 825 is the most stringent standard for laser radiation eye safety. It is for the implementor to take appropriate
measures to ensure eye safety.

8.3 Character level end exchange level
The character level and exchange level are identical to the HS-SE-10 implementation. See 7.3 and 7.4.
Note that in a given implementation, an appropriately large N_char sink size will have to be chosen in order to preventthe flow control mechanism periodically stalling the data flow over long lengths of fiber. See annex H.

9. Common packet level

9.1 General discussion
A packet is a sequence of characters (N_chars only) with a specific order and format. Constituent characters ofdifferent packets shall not be interleaved on a link. A packet consists of a destination followed by a payload. A packet
is delimited by an end_of_packet marker.
This standard does not define a specific size (or maximum size) for packets. This enables different packet formats to
be carried by a HIC network. However, packets should be limited in size so that no one very long packet can occupy
the network for an extended period of time. A limited known packet size also enables an upper bound to be placed on
the latency of any packet transmission.
Terminal nodes generate (source node) and consume (destination node) packets. A network is any set of devices
connected by links joining (directly or indirectly) a set of terminal nodes.
The protocol assumes the use of packet-switch network in which the routing information necessary to correctlytransmit the packet across the network is contained in the first K N_chars of the packet (where K is fixed throughout
a subnetwork). It is at the packet level that the routing decisions are taken. The protocol does not define a specific (ormaximum) size for a packet. Successive packets transmitted on a link may have different destinations. Each packet istransmitted in its entirety, i:e., the transmission of a packet on a link shall be completed before the transmission of thesuccessive packet may begin.
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9.2 Packet format
A packet consists of a destination followed by a payload, and is delimited by an end_of_packet marker:〈DEST〉 〈PAYLOAD〉 〈End_Of_Packet〉
9.2.1 Destination
The destination normally contains a list of one or more destination identifiers (dest_id) which are used to enable a
network to transmit the packet from its source node to its destination node. A dest_id is a fixed size field (K bytes long,where K ≥ 1), its size being known to the (sub)network.
The list is not delimited and only the first dest_id is used by a switch for routing purposes. The switch shall treat theother dest_id(s) in the list (if they exist) as part of the payload. A switch may provide a facility for deleting the first
dest_id as it outputs the packet, so that the next switch uses the next destid in the original list. This mechanism may be
used to connect (sub)networks which use different size dest_ids (different values for K). The method of allocating
dest_ids to destinations is outside the scope of this standard.
The destination may be null, for example for the specific case of a point-to-point link (i.e., the network is just one link).
9.2.2 Payload
The payload is the data (a message, a memory access request, an acknowledgment, etc.) that is to be transferred fromthe source node to the destination node. It has a specific format, defined in the transaction level. A payload may he null.
The definition of any packet format is outside the scope of this standard.
9.2.3 End_of_packet marker
The end_of_packet marker (EOP in its generic form) is a N_char, and shall always be the last character of a packet; it
acts as the packet delimiter. Packets do not have a start_of_packet marker: the first N_char received after an EOP shallbe taken as the first character of the next packet.
Different EOP markers are defined in table 9-1.
Table 9-1 —End_of_packet markers
Name

Description

EOP_1

Normal end_of_packet marker

EOP_2

Exceptional end_of_packet marker

The exceptional_end_of_packet marker may be used to signal an end of message or an error. Implementations may
provide more than one type of exceptional_end_of_packet marker. The N_char codes used for the EOP markers in DS
and HS Links are as given in table 9-2.
Table 9-2 —Codes for EOP markers
Name

Description

Code for DS-SE and DS-DE

Code for HS-SE and HS-FO

EOP_1

Normal end_of_packet marker

P101

Control char ID= 7

EOP_2

Exceptional end_of_packet marker

P110

Control char ID= 8

Note that the N_char codes for TS-FO links have a more complex format, and a longitudinal checksum.
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9.3 Networks and routing
The (sub)network7 routes the packet using the information contained in the destination field of the packet. The routing
algorithm takes the fixed size8 dest_id as its input in order to determine how to route the packet within the(sub)network. The routing algorithm is outside the scope of this standard.
Packets sent from a given source node to a given destination node over a network may be delivered in an order different
from the sending order. The details of mechanisms to ensure in-order delivery are outside the scope of this standard.

9.4 Error detection, recovery, and reporting
The function of the protocol is to deliver an error free9 packet from its source-terminal-node to its destination node. At
the packet level or above, a system of high level error checking may be required. It is the responsibility of thetransaction level to define the high level check that is to be used and therefore any definition of a high level check is
outside the scope of this standard. In general, a high-level check is required at the packet level if the low level issuspected of being error prone and there is no higher level check (e.g., a message level CRC in a message passing
system).
A further discussion is given in annex G.

10. Conformance criteria

10.1 Conformance statements
Many implementations will implement only a subset of the protocol stack. For example, an interface on a box may
comply with a vertical “slice” through the stack to incorporate the necessary elements for a particular speed/medium
combination, whereas for a cable assembly only the physical parameters are relevant. Accordingly, a number ofsubsets are defined, to which implementations may claim conformance. Any such conformance statement shall takethe following form (The interfaces on) this implementation/product conform(s) to the [identification] specification ofIEEE Std 13557 (See also 10.3.) The text to be substituted for [identification], and the clauses of this standard to which
the corresponding implementation shall conform, are given in 10.2 (see tables 10-1, 10-2, 10-3, and 10-4).

10.2 Definition of subsets
An implementation of a connector shall conform to all of the mandatory specifications given in all of the clauses forone of the identifications given in table 10-1.
Table 10-1 —Conformance identifications for connectors
Identification

Relevant clauses

DS-DE connector

5.4.2, A.2

HS-SE connector

7.1.5, B:2, B.3, B.4

TS-FO/HS-FO connector (MM)6.1.2, C.2, C.4, C.5

HS-FO connector (SM)8.1.2, C.3, C.4, C.5

7Subnetworks refer to the building blocks of a hierarchical network; see 9.2.1.
8

Fixed size means that the size is constant for a given (sub)network and is known to the (sub)network. The size determines the number ofdestinations that can he reached by the des_id, e.g., a one byte des_id can address 256 nodes; two bytes, 65 536 nodes, etc.
9For some applications such as video data, the error free criterion is not so important, and so any error recovery action that interrupts the flow of data
may need to he disabled.

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79IEEE Std 1355-1995

IEEE STANDARD FOR HETEROGENEOUS INTERCONNECT (HIC) (LOW-COST, LOW-LATENCYAn implementation of a link cable shall conform to all of the mandatory specifications given in all of the clauses forone of the identifications given in table 10-2.
Table 10-2 —Conformance Identifications for link cables
Identification

Relevant clauses

DS-DE link cable

5.4.1

HS-SE link cable

7.1.3, 7.1.4

TS-FO link cable

6.1.1

HS-FO link cable

8.1.1

An implementation of a link cable assembly shall conform to all of the mandatory specifications given in all of theclauses for one of the identifications given in table 10-3.
An implementation of a link interface shall conform to all of the appropriate mandatory specifications given in all of
the clauses for one of the identifications given in table 10-4.
Table 10-3 —Conformance identifications for link cable assemblies
Identification

Relevant clauses

DS-DE link cable assembly

5.4, A.2

HS-SE link cable assembly

7.1, B.2, B.3, B.4

TS-FO/HS-FO link cable assembly (MM)

6.1, C.2, C.4, C.5

HS-FO link cable assembly (SM)

8.1, C.3, C.4, C.5

Table 10-4 —Common identifications for link interfaces
Identification

Relevant clauses

DS-SE-00 link interface

5.1, 5.2, 5.3, 5.6, 5.7, 9

DS-DE-00 link interface

5.1, 5.5, 5.6, 5.7, 9

DS-SE-01 link interface

5.1, 5.2, 5.3, 5.6, 5.7, 9

DS-DE-01 link interface

5.1, 5.5, 5.6, 5.7, 9

DS-SE-02 link interface

5.1, 5.2, 5.3, 5.6, 5.7, 9

DS-DE-02 link interface

5.1, 5.5, 5.6, 5.7, 9

HS-SE-10 link interface

7.2, 7.3, 7.4, 9

TS-FO-02 link interface

6.2, 6.3, 6.4, 9

HS-FO-10 link interface

8.2, 8.3, 9

10.3 Conformance statements and cable markings
At the time of publication of this document, this standard was under consideration for approval as ISO/IEC 14575.
Upon approval by ISO/IEC, references to “IEEE 1355” in conformance statements and cable markings may bereplaced by references to “ISO/IEC 14575 (IEEE 1355).”

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Annex A DS-DE connector specification(Normative)

A.1 General
The DS-DE connectors shall be as specified in IEC 10764-107. The connector system comprises a throughpanel(fixed) connector, which connects to a cable mounted (free) connector. A connector is required to support one DS-DE
link. An option (described in annex N) allows a connector to support multiple DS-DE links, by arraying multiple DSDE connectors.
Any properties not specified in IEC 10764-107 shall be as in the following specification.

A.2 Specification
The connectors shall be implemented according to the table A.1 and be of dimensions specified in figures A.1 to A.7.
Nothing in the connector design shall impede the assembly of systems which meet CISPR 22 regulations.

Figure A.2 —DS-DE fixed connector side view

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81IEEE Std 1355-1995

IEEE STANDARD FOR HETEROGENEOUS INTERCONNECT (HIC) (LOW-COST, LOW-LATENCY

Figure A.1 —DS-DE fixed connector front view

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SCALABLE SERIAL INTERCONNECT FOR PARALLEL SYSTEM CONSTRUCTION)IEEE Std 1355-1995

Figure A.3 —DS-DE fixed connector top view

Figure A.4 —DS-DE connector latch

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83IEEE Std 1355-1995

IEEE STANDARD FOR HETEROGENEOUS INTERCONNECT (HIC) (LOW-COST, LOW-LATENCY

Figure A.5 —DS-DE free connector front view

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SCALABLE SERIAL INTERCONNECT FOR PARALLEL SYSTEM CONSTRUCTION)IEEE Std 1355-1995

Figure A.6 —DS-DE free connctor side view

Figure A.7 —DS-DE free connector contact

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IEEE STANDARD FOR HETEROGENEOUS INTERCONNECT (HIC) (LOW-COST, LOW-LATENCY

Table A.1— DS-DE connector requirements
Characteristic

86

Spec.

Test spec.

Conditions

IEC 1076-4-107

IEC 512-2,
Test 1a—

IEC 917;1076.4-107

IEC 512-2,
Test 1b—

5.9 mm maximum

IEC 1076-4-107

IEC 512-2,
Test 1b—

Connector pitch

6.0 mmIEC 1076-4-107

IEC 512-2,
Test 1b—

Modularity

Adjacent connectors shall beplaced on a 6 mm pitch. Nonadjacent connectors shall havetheir centerlines separated by atleast 12 mm

IEC 1076-4-107——

ShieldingCompletely shielded

IEC 1076-4-107

IEC 512-2,
Test 1a—Polarization

Chamfer design prevents 180
degree incorrect mating

IEC 1076-4-107

IEC 512-7,
Test 13e—Male-female contact
overlap

0.9 mm minimum when matedIEC 1076-4-107——

Misalignment intransverse andlongitudinal axes

± 0.45 mm

IEC 1076-4-107——

Inclination oftransverse andlongitudinal axes

± 7° maximum

IEC 1076-4-107——

Voltage proof Vrms

750 V contact/contact 750 V
contact/shielding

IEC 1076-4-107

IEC 512-2,
Test 4a—Current-carrying
capacity

1.5 A at 70 ° C

IEC1076-4-107

IEC 512-3,
Test 5b

All contacts
fully loaded

Contact resistance

35 mΩ maximum

IEC 1076-4-107

IEC 512-2,
Test 2a—Insulation resistance

104 MΩ minimum contact/
contact 104 MΩ minimum
contact/shielding

IEC 1076-4-107

IEC 512-2,
Test 3a—Crosstalk

Data/strobe: 3.6% Data/data:
1.2%

IEC 1076-4-107—

Tr=1 ns;
differential
wiringImpedance

110 ± 20Ω

IEC 1076-4-107

IEC 48 (B) 141

Differential
wiringContacts

10 per connector; arranged as
two rows of 5 contacts

Contact grid

2 mm * 2 mmConnector width

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SCALABLE SERIAL INTERCONNECT FOR PARALLEL SYSTEM CONSTRUCTION)IEEE Std 1355-1995

Table A.1— DS-DE connector requirements (Continued)
Characteristic

Spec.

Test spec.

Conditions
Between row aand row e

Skew

80 ps maximum

IEC 1076-4-107—

Temperature range–10°C to +60°C

IEC 1076-4-107

IEC 512-6,
Test 11—

Creepage andclearance distance:
contact/contact/
shielding

0.65 mm minimum

IEC 1076-4-107

IEC 512-2,
Test lb—

Mechanical operations

250 operations

IEC 1076-4-107

IEC 512-5,
Test 9a—Total insertion force

10 N maximum per connector
moduleIEC 1076-4-107

IEC 512-7,
Test 13bMax. speed ofoperation: 10
mm/s

Withdrawal force bypulling on latch

2 N minimum per connector
moduleIEC 1076-4-107

IEC 512-7,
Test 13bMax. speed ofoperation: 10
mm/s

Withdrawal force withclosed latch

100 N minimum per connector
moduleIEC 10764-107

IEC 512-8,
Test 15f—

Tensile strength ofcable-connector clamp

110 N minimum. per connector
moduleIEC 1076-4-107

IEC 512-9 ,Test 17c—

Vibration

20 g/10–500 Hz/8 cycles/2h per
axis contact disturbance 1 µs
maximum

IEC 1076-4-107

IEC 512-4,
Test 6d—Shock

49g/5 ms/5 shocks per plane
contact disturbance 1 µs
maximum

IEC 1076-4-107

IEC 512-4,
Test 6c—

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Annex B HS-SE connector specification(Normative)

B.1 General
The HS-SE connectors shall be as specified in IEC 1076-4-107, Any properties not specified in IEC 1076-4-107 shallbe as in the following specification. The connector system comprises a through-panel (fixed) connector, whichconnects to a cable mounted (free) connector. A connector is required to support one HS-SE link. An option (describedin annex Q) allows a connector to support multiple HS-SE links, by arraying multiple HS-SE connectors.

B.2 Specification
The connectors shall be implemented according to table B.1, with dimensions specified in figures B.1 to B.5.

Table B.1—HS-SE connector requirements
Characteristic

Test spec.

Conditions

Coaxial contacts

2 per connector

IEC 1076-4-107

IEC 512-2, Test 1a—

Connector width

5.9 mm maximum

IEC 1076-4-107

IEC 512-2, Test 1b—

Connector pitch

6.0 mmIEC 1076-4-107

IEC 512-2, Test 1b—

Modularity

Adjacent connectors shall beplaced on a 6 mm pitch. Nonadjacent connectors shall havetheir centerlines separated by 12mm or more

IEC 1076-4-107——

ShieldingCompletely shielded

IEC 1076-4-107

IEC 512-2, Test 1a—

Polarization

Chamfer design prevents 180
degree incorrect mating

IEC 1076-4-107

IEC 512-7, Test 13e—

Male-female contact
overlap

2.0 mm minimum when matedIEC 1076-4-107——

Misalignment intransverse axes

± 0.6 mm

IEC 1076-4-107——

Misalignment inlongitudinal axes

± 0.9 mm

IEC 1076-4-107——

Inclination oftransverse axes

± 2 degrees maximum

IEC 1076-4-107——

Voltage proof Vrms:
center contact/groundcontact

1000 VIEC 1076-4-107

IEC 512-2, Test 4a—

IEC 1076-4-107

IEC 512-2, Test 2a—

Contact resistance:
center contact groundcontact shielding
contact

88Spec.

12 mΩ max.
6 mΩ max.
30 mΩ max.

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SCALABLE SERIAL INTERCONNECT FOR PARALLEL SYSTEM CONSTRUCTION)IEEE Std 1355-1995

Table B.1—HS-SE connector requirements (Continued)
Characteristic

Spec.

Test spec.

Conditions

Insulation resistance5000 MΩ min.

IEC 1076-4-1072

IEC 512-2, Test 3a—

Insertion loss

max. 0.3 dB √F (F in GHz)

IEC 1076-4-107

DIN 0472, P 517—

HF leakage

Min. 40 dB at 3 GHz

IEC 1076-4-107

IEC 46A (Co) 159-II,
SEC.7.1—

Crosstalk attenuation

Min. 35 dB at 3 GHz

IEC 1076-4407

DIN 0472, PART 517—
Mated
couple male
+ femalecontact

VSWR< 1.3 at 3 GHz

IEC 1076-4-107

IEC 46A (Co)159-I,
Section 6.12

Impedance

50 Ω±10%IEC 1076-4-107

IEC 46A (Co) 159-I—

Temperature range–10°C to +60°C

IEC 1076-4-107

IEC 512-6, Test 11—

Mechanical operations

500 operations

IEC 1076-4-107

IEC 512-5, Test 9A—

Insertion force

3.0 N max. per coax line

IEC 1076-4-107

IEC 512-7, Test 13b—

Withdrawal force

0.5 N min. per coax line

IEC 1076-4-107

IEC 512-7, Test 13b—

Withdrawal force withclosed latch

100 N min. per connector
moduleIEC 1076-4-107

IEC 512-8, Test 15f—

Tensile strength ofcable connector clamp

50 N single braid cable; 100 N
double braid cableIEC 1076-4-107

IEC 512-9, Test 17c—

Vibration

15 g/10–60 Hz/30 min per axis
contact disturbance 1 µs max.

IEC 1076-4-107

—

—

Shock

50 g/5 ms/3 shocks per plane
Contact disturbance 1 µs max.

IEC 10764-107

IEC 512-4, Test 6c—

Nothing in the connector design shall impede the assembly of systems which meet CISPR 22 regulations.

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Figure B.1 —HS-SE free connector front view

Figure B.2 —HS-SE free connector side view

B.3 Shielding
A link connector shall be shielded if the link cable is shielded. There shall be a 360° mechanical connection between
the outer braid of the link cable and the connector housing. In case of high electromagnetic compatibility (EMC)
requirements, additional parts (e.g., EMC brackets and gaskets) may be used to ensure mechanical connection between
the panel and connector housings.

90

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SCALABLE SERIAL INTERCONNECT FOR PARALLEL SYSTEM CONSTRUCTION)IEEE Std 1355-1995

Figure B.3 —HS-SE fixed connector front view

Figure B.4 —HS-SE fixed connector side view

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Figure B.5 —HS-SE connector link

B.1 Coaxial contacts
An HS-SE connector contains two coaxial contacts. The contacts shall be of dimensions shown in figure B.6.

Figure B.6 —HS-SE contact interface dimensions
92

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SCALABLE SERIAL INTERCONNECT FOR PARALLEL SYSTEM CONSTRUCTION)IEEE Std 1355-1995

Annex C TS-FO and HS-FO connector specifications(Normative)

C.1 General
The TS-FO and HS-FO conne tots shall be as specified in IEC 1754-6. Any properties not specified in IEC 1754-6
shall be as in the following specification.

C.2 TS-FO and HS-FO multimode connector
The TS-FO and HS-FO (multimode) connectors shall be implemented according to the table C.1 (interface
specifications) and table C.2 (performance and environmental specifications), and be of dimensions specified infigures C.1 to C.2.

Table C.1—TS-FO and HS-FO (multimode) connector requirements
Characteristic

Specification

Test specification reference
IEC QC210000 (IEC 1300 )Plug interface
dimension

IEC 1754-6-2 Duplex plug connector interfacepush/pull

Adapter interface dimension

IEC 1754-6-4 Duplex adapter connector interfacepush/pull

Ferrule spacing

4.5 mm—Connector width

14 mm

—

Contact

2 per connector—

Shielding—

Modularity
Polarization

Keyed

Coupling

Push/pull(Mechanicaloperation)
operationmechanicalendurance

Requirements:

IEC 1300-2-2—Attenuation: deviationfrom the initial value lessthan 0.2 dB—Cycles; 500—Return loss: more than
20 dB

—Preconditioning procedure; none

—Specimen optically functioning—Recovery procedure; clean plug and adapter after
every 25 matings—Deviations; none
—Reference adapter shall be in accordance with IEC
1754-6-4 : Duplex adapter interface—push/pull

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Table C.1—TS-FO and HS-FO (multimode) connector requirements (Continued)
Characteristic

Specification

Cable pulling

Initial measurement andperformancerequirements:

IEC 1300-2-4—Attenuation; less than
0.75 dB—Rate of application of the tensile load; 50 N/min.
<Load rate < 250 N/min—Return loss; more than
20 dB

—Point of application of the tensile load; 22–28 cm fromthe connector

Final measurement andperformancerequirements:—Specimen optically non-functioning—Attenuation; less than
0.75 dB—Return loss; more than
20 dB
—The specimen has no
mechanical damage
Cable torsion

Test specification reference

Magnitude; 70 N

— Preconditioning procedure; clean plug and adapter
before testing—Recovery procedure; none
—Deviation; none
—Reference adapter shall be in accordance with IEC
1754-6-4 : Duplex adapter interface—push/pull

Initial measurement andperformancerequirements:

IEC 1300-2-5—Attenuation; less than
0.75

—Application of load; twist cable 2.5 turns in one
direction with specified load applied, then twist it 5 turns
in other direction and back 5 turns for 5 cycles—Return loss; more than
20 dB
Final measurement andperformancerequirements:

Tensile load: 5 N—Point of application of the tensile load; 22-28 cm fromthe connector—Specimen optically non-functioning—Preconditioning procedure; none

—Attenuation; less than
0.75 dB—Return loss; more than
20 dB
—The specimen has no
mechanical damage

94—Recovery procedure; none
—Deviations; none
—Reference adapter shall be in accordance with IEC
1754-6-4 : Duplex adapter interface—push/pull

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SCALABLE SERIAL INTERCONNECT FOR PARALLEL SYSTEM CONSTRUCTION)IEEE Std 1355-1995

Table C.1—TS-FO and HS-FO (multimode) connector requirements (Continued)
Characteristic
Strength ofcouplingmechanism

Specification

Test specification reference

Initial measurement andperformancerequirements:

IEC 1300-2-6—Attenuation; less than
0.75 dB—Rate of application of the tensile load; 50 N/min <Load rate < 250 N/min—Return loss; more than
20 dB

—Point of application of the tensile load; 22–28 cm fromconnector

Final measurement andperformancerequirements:—Specimen optically non-functioning—Attenuation; less than
0.75 dB—Recovery procedure; none

—Magnitude; 70 N

—Preconditioning procedure; none

—Deviations; none
—Return loss; more than
20 dB

—Reference adapter shall be in accordance with IEC
1754-6-4 : Duplex adapter interface—push/pull—The specimen has no
mechanical damage
Vibration

Initial measurement andperformancerequirements:—Attenuation; less than
0.75 dB

IEC 1300-2-1—Frequency range; 10–55 Hz—Vibration amplitude; 0.75 mm constant displacement—Sweep time; 1 octave/min—Endurance duration per axis; 30 min—Return loss; more than
20 dB
Final measurement andperformancerequirements:—Method of mounting; an adapter shall be mounted
rigidly to the mounting fixture—Specimen optically non-functioning—Preconditioning procedure; none

—Attenuation; less than
0.75 dB—Recovery procedure; clean plug and adapter before
final measurement—Return loss; more than
20 dB

—Divination; none

—The specimen has no
mechanical damage—Reference adapter shall be in accordance with IEC
1754-6-6 : Duplex adapter interface—push/pull

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Table C.1—TS-FO and HS-FO (multimode) connector requirements (Continued)
Characteristic
Drop

Specification
Initial measurement andperformance requirments:

Test specification reference
IEC 1300-2-1—Method; A—Attenuation; less than
0.75 dB—Return loss; more than
20 dB

—Number of drops; 5—Drop height; 1000 mm—Specimen optically non-functioning

Final measurement andperformancerequirements:—Attenuation; less than
0.75 dB—Preconditioning procedure; with dust cap—Recovery procedure; clean plug and adapter before
final measurement—Deviation; none

—Return loss; more than
20 dB

—Reference adapter shall be in accordance with IEC
1754-6-4 : Duplex adapter interface—push/pull—The specimen has no
mechanical damage
Engagement andseparation force

Engagement force:max. 30 N
Separation force:max 30.N

IEC 1300-3-11—Preconditioning procedure; none
—Deviation; as necessary—Reference adapter shall be in accordance with IEC
1754-6-4 : Duplex adapter interface—push/pull

C.3 HS-FO single-mode connector
The HS-FO (single-mode) connector shall be implemented according to the table C.3 (interface specifications) andtable C.4 (performance and environmental specifications) and be of dimensions specified in figures C.1 to C.2.

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Table C.2—Performance and environmental specification for
TS-FO and HS-FO (multimode) connector
Characteristic
Attenuation

Specification

Test specification referenceLess than 0.5 dB against referenceplug

IEC 1300-3-4

In random connection—Method 7

Less than 0.75 dB—Equilibrium mode condition(50 or 62.5/125 µm multimode fiber)—Definition of reference plug are as follows:•Ferrule outer diameter is 1.249 mm ±0.0003 mm•Eccentricity of the fiber core with the outer
diameter of the ferrule is less than 0.3 µm•Angular misalignment of ferrule is less than 0.2
degrees•Eccentricity of spherical polished ferrule endface isless than 30 µm—Reference adapter shall be in accordance withIEC 1754-64 : Duplex adapter connector interface—push/pull—Number of measurements to be averaged: 5—Source; LD—Peak wavelength; 1.3 µm—Precoditioning procedure; the plug and adapter shallbe cleaned

Return loss

More than 20 dB (50 or 62.5/125 µm
multimode fiber)

IEC 1300-3-6—Method 3—Source; LD—Peak wavelength; 1.3 µ;m—Reference adapter shall be in accordance withIEC 1754-64 Duplex adapter interface—push/pull

Cold

Requirements:

IEC 1300-2-17—Attenuation; deviation from theinitial value less than 0.2 dB—Temperature; –10 °C—Return loss; more than 20 dB—Duration; 96 h
—Specimen optically functioning—Conditioning procedure; specimen lowered to test
temperature and returned to room temperature at a rate
not to exceed 1°/min—Deviations; none
—Reference adapter shall be in accordance withIEC 1754-6-4 : Duplex adapter interface—push/pull—Monitoring method of attenuation and return loss shallbe in accordance with IEC 1300-3-2

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Table C.2—Performance and environmental specification for
TS-FO and HS-FO (multimode) connector (Continued)
Characteristic
Dry heat

Specification

Test specification reference

Requirements:

IEC 1300-2-18—Attenuation; deviation from theinitial value less than 0.2 dB—Temperature; 60° C—Return loss: more than 20 dB—Duration; 96 h
—Specimen optically functioning—Conditioning procedure; specimen raised to test
temperature and returned to room temperature at a rate
not to exceed 1 °/min—Deviations; none
—Reference adapter shall be in accordance with IEC
1754-6-4 : Duplex adapter interface—push/pull—Monitoring method of attenuation and return loss shallbe in accordance with IEC 1300-3-20

Damp heat(Steady state)

Requirements:

IEC 1300-2-19—Attenuation; deviation from theinitial value less than 0.2 dB—Temperature; 40°C

—Return loss: more than 20 dB—Relative humidity; 90–95%—Duration; 4 days
—Precautions regarding surface moisture removal: none
—Specimen optically functioning—Conditioning procedure; Specimen raised to test
temperature and returned to room temperature at a rate
not to exceed 1 degree/min—Deviations, none
—Reference adapter shall be in accordance with IEC
1754-6-4 : Duplex adapter interface—push/pull—Monitoring method of attenuation and return loss shallbe in accordance with IEC 1300-3-2

Operation
temperature98–10 °C to +60 ° C

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SCALABLE SERIAL INTERCONNECT FOR PARALLEL SYSTEM CONSTRUCTION)IEEE Std 1355-1995

Table C.2—Performance and environmental specification for
TS-FO and HS-FO (multimode) connector (Continued)
Characteristic
Change oftemperature(Test NA)

Specification

Test specification reference

Initial measurement andperformance requirements

IEC 1300-2-22—Attenuation; less than 0.75 dB—Test method; NA—Return loss; more than 20 dB—High temperature; 70° C

Final measurement and performancerequirements—Low temperature; –25°C—Attenuation; less than 0.75 dB—Duration of extreme temperature; 30 min—Return loss; more than 20 dB—Change over time; 0.5 min—Number of cycles; 5—Specimen optically non-functioning—Preconditioning procedure; with dust cap—Recovery procedure; after test, specimens shall bemaintained in room temperature condition for 2 h. Clean
endface before final measurement—Deviation; none
—Reference adapter shall be in accordance withIEC 1754-6-4 : Duplex adapter interface—push/pull

Table C.3—HS-FO (single-mode) connector requirements
Characteristic

Specification

Test specification reference—

IEC QC210000 (IEC 1300 )Plug interface
dimension—

IEC 1754-6-2 Duplex plug connector interface—push/
pull

Adapterinterfacedimension—

IEC 1754-6-4 Duplex adapter connector interface—push/pull

Ferrule spacing

4.5 mm—Connector width

14 mm

—

Contact

2 per connector—

Shielding——

Modularity——

Polarization

Keyed

—

Coupling

Push/pull—

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Table C.3—HS-FO (single-mode) connector requirements (Continued)
Characteristic
Mechanicalendurance(mechanicaloperation)

Specification

Test specification reference

Requirements:

IEC 1300-2-2—Attenuation; deviation from theinitial value less than 0.2dB—Cycles; 500—Return loss: more than 26 dB—Specimen optically functioning—Preconditioning procedure; none
—Recovery procedure; clean plug and adapter after
every 25 matings—Deviations; none
—Reference adapter shall be in accordance with IEC
1754-6-4 : Duplex adapter interface—push/pull

Cable pulling

Initial measurement andperformance requirements:

IEC 1300-2-4—Attenuation; less than 0.75 dB

Magnitude; 70 N

—Return loss; more than 20 dB—Rate of application of the tensile load; 50 N/min<Load rate < 250 N/min

Final measurement and performancerequirements—Point of application of the tensile load; 22–28 cm fromthe connector—Attenuation; less than 0.75 dB—Specimen optically non-functioning—Return loss; more than 26 dB—Preconditioning procedure; clean plug and adapter
before testing—The specimen has no mechanicaldamage—Recovery procedure; none
—Deviation; none
—Reference adapter shall be in accordance with IEC
1754-6-4 : Duplex adapter interface—push/pull

Cable torsion

Initial measurement andperformance requirements:

IEC 1300-2-5—Attenuation; less than 0.75 dB

Tensile load; 5 N—Return loss; more than 26 dB—Application of load; twist cable 2.5 turns in one
direction with specified load applied, then twist 5 turns inother direction and back 5 turns for 5 cycles

Final measurement and performancerequirements:—Point of application of the tensile load; 22–28 cm fromthe connector—Attenuation; less than 0.75 dB—Specimen optically non-functioning—Return loss; more than 26 dB—Preconditioning procedure; none

—The specimen has no mechanicaldamage—Recovery procedure; none
—Deviations; none
—Reference adapter shall be in accordance with IEC
1754-6-4 : Duplex adapter interface—push/pull

100

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Table C.3—HS-FO (single-mode) connector requirements (Continued)
Characteristic
Strength ofcouplingmechanism

Specification

Test specification reference

Initial measurement andperformance requirements:

IEC 1300-2-6—Attenuation; less than 0.75 dB—Magnitude; 70 N

—Return loss; more than 26 dB—Rate of application of the tensile load; 50 N/min <Load rate < 250 N/min

Final measurement and performancerequirements:—Point of application of the tensile load; 22–28 cm fromthe connector—Attenuation; less than 0.75 dB—Specimen optically non-functioning—Return loss; more than 26 dB—Preconditioning procedure; none
—Recovery procedure; none
—Deviations; none
—Reference adapter shall be in accordance with IEC
1754-6-4 : Duplex adapter interface—push/pull

Vibration

Initial measurement andperformance requirements:

IEC 1300-2-1—Attenuation; less than 0.75 dB—Frequency range; 10–55 Hz—Return loss; more than 26 dB—Vibration amplitude; 0.75 mm constant displacement

Final measurement and performancerequirements:—Sweep time; 1 octave/min—Attenuation; less than 0.75 dB—Endurance duration per axis; 30 min—Return loss; more than 26 dB—Method of mounting; an adapter shall be mounted
rigidly to the mounting fixture—The specimen has no mechanicaldamage—Specimen optically non-functioning—Preconditioning procedure; none
—Recovery procedure; clean plug and adapter before
final measurement—Divination; none
—Reference adapter shall be in accordance with IEC
1754-6-4 : Duplex adapter interface—push/pull

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Table C.3—HS-FO (single-mode) connector requirements (Continued)
Characteristic
Drop

Specification

Test specification reference

Initial measurement andperformance requirements

IEC 1300-2-1—Attenuation; less than 0.75 dB—Method: A—Return loss; more than 26 dB—Number of drops: 5

Final measurement and performancerequirements:—Drop height: 1000 mm—Attenuation; less than 0.75 dB—Specimen optically non-functioning—Return loss; more than 26 dB—Preconditioning procedure; with dust cap—The specimen has no mechanicaldamage—Recovery procedure; clean plug and adapter before
final measurement—Divination; none
—Reference adapter shall be in accordance with IEC
1754-6-4 : Duplex adapter interface—push/pullEngagement andseparation force

Engagement force; max. 30 N
Separation force; max. 30 N

IEC 1300-3-11—Preconditioning procedure; none
—Deviation; as necessary—Reference adapter shall be in accordance with IEC
1754-6-4 : Duplex adapter interface—push/pull

C.4 TS-FO/HS-FO multimode and HS-FO single-mode connector dimensions
Annex R shows the recommended PCB footprint for the fixed connector and annex S the recommended fiber.

C.1 Color coding of connector
The connectors for TS-FO, HS-FO multimode and HS-FO single-mode are externally physically identical. In order todistinguish between the different types of connector, the keying mark on the fixed and free connectors shall be color
coded as shown in table C.5.

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Figure C.1 —TS-FO/HS-FO link free connector

Figure C.2 —TS-FO/HS-FO link fixed connector

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Table C.4—Performance and environmental specification for
HS-FO (single-mode) connector
Characteristic
Attenuation

Specification

Test specification referenceLess than 0.5 dB against reference plug

IEC 1300-3-4

In random connection—Method 7

UnTuned—Definition of reference plug are as follows:

Less than 0.35 dB (average)•Ferrule outer diameter is 1.249 ± 0.0003 mm

Less than 0.75 dB•Eccentricity of the fiber core with the outer
diameter of the ferrule is less than 0.3 µm(95% probability)•Angular misalignment of ferrule is less than 0.2
degrees

Tuned•Eccentricity of spherical polished ferrule endface isless than 30 µm

Less than 0.5 dB (average)

Reference adapter shall be in accordance withIEC 1754-6-4 : Duplex adapter connector inter-face—push/pullLess than 0.5 dB—Number of measurements to be averaged; 5—Source; LD—Peak wavelength; 1.3 µm
Preconditioning procedure; the plug and adapter shall becleanedReturn loss

More than 26 dB

IEC 1300-3-6—Method 3—Source; LD—Peak wavelength; 1.3 µm—Reference adapter shall be in accordance with IEC
1754-6-4 Duplex adapter interface—push/pull

Cold

Requirements

IEC 1300-2-17—Attenuation; deviation from theinitial value less than 0.2 dB—Temperature; -10 °C—Return loss: more than 26 dB—Duration; 96 h
—Specimen optically functioning—Conditioning procedure; specimen lowered to test
temperature and returned to room temperature at a rate
not to exceed 1 °/min—Deviations; none
—Reference adapter shall be in accordance with IEC
1754-6-4 : Duplex adapter interface—push/pull—Monitoring method of attenuation and return loss shallbe in accordance with IEC 1300-3-20

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Table C.4—Performance and environmental specification for
HS-FO (single-mode) connector (Continued)
Characteristic
Dry heat

Specification

Test specification reference

Requirements

IEC 1300-2-18—Attenuation; deviation from theinitial values less than 0.2 dB—Temperature; 60 °C—Return loss: more than 26 dB—Duration; 96 h
—Specimen optically functioning—Conditioning procedure; specimen raised to test
temperature and returned to room temperature at a rate
not to exceed 1 degree/min—Deviations; none
—Reference adapter shall be in accordance with IEC
1754-6-4 : Duplex adapter interface—push/pull—Monitoring method of attenuation and return loss shallbe in accordance with IEC 1300-3-20

Damp heat(steady state)

Requirements

IEC 1300-2-19—Attenuation; deviation from theinitial value less than 0.2 dB—Temperature; 40 °C—Return loss: more than 26 dB—Relative humidity; 90-95%—Duration; 4 days
—Precautions regarding surface moisture removal: none
—Specimen optically functioning—Conditioning procedure; specimen raised to test
temperature and returned to room temperature at a rate
not to exceed 1 °/min—Deviations; none
—Reference adapter shall be in accordance with IEC
1754-6-4 : Duplex adapter interface—push/pull—Monitoring method of attenuation and return loss shallbe in accordance with IEC 1300 3-2

Operation
temperature–10 °C to +60 °C

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Table C.4—Performance and environmental specification for
HS-FO (single-mode) connector (Continued)
Characteristic
Change oftemperature(test NA)

Specification

Test specification reference

Initial measurement and performancerequirements

IEC 1300-2-22—Attenuation; less than 0.75 dB—Test method; NA

Return loss; more than 26 dB—High temperature; 70 °C

Final measurement and performancerequirements—Low temperature; –25 °C—Attenuation; less than 0.75 dB—Duration of extreme temperature; 30 min—Return loss; more than 26 dB—Change over time; 0.5 min—The specimen has no mechanicaldamage—Number of cycles; 5—Specimen optically non-functioning—Preconditioning procedure; with dust cap—Recovery procedure; after test, specimens shall bemaintained in room temperature condition for 2 h; clean
endface before final measurement—Deviation; none
—Reference adapter shall be in accordance withIEC 1754-6-4 : Duplex adapter interface—push/pull

Table C.5 —Color coding of TS/HS-FO connectors
Type of interconnect

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Color

TS-FO

Blue

HS-FO multimodeWhite

HS-FO single-mode

Yellow

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SCALABLE SERIAL INTERCONNECT FOR PARALLEL SYSTEM CONSTRUCTION)IEEE Std 1355-1995

Annex D Rationale(Informative)

D.1 Need for a new standard
It is widely recognized that the most economic way to build high-performance systems is by using parallelism. Parallelsystems can provide very high computational power (in machines such as the CM-5 and the Parsytec GC-machine),
fast response (for transaction processing or distributed control), very large I/O throughput (in RAID systems) andextremely high reliability (in redundant fault-tolerant systems). They also have the potential to be more maintainable
and more expandable than conventional, monolithic systems.
The construction of high-performance systems with parallel processing and/or parallel I/O demands a fast, low-cost,
low-latency interconnect. It must be fast and low-latency, otherwise it will be the limiting factor in system
performance; and it must be low-cost, or it will dominate the system cost. It must also scale well in both performanceand cost relative to the system size, otherwise highly parallel systems will be limited in performance or too expensive.
Existing standards do not meet these criteria, either because they are designed for communication over long distances(which incurs high costs), or because they aim at the extreme of currently achievable performance (which again
increases costs), or because they are based on a restricted model such as a bus, which limits overall performance andscalability.
The purpose of this new interconnect standard is to enable high-performance, sealable, modular, parallel systems to beconstructed with low-cost, where “cost” must include not only the price of components, but also the engineering effort
required to use them successfully. This international standard specifies the physical connectors and cables to be used,the electrical/optical properties of the interconnect, and a cleanly-separated set of logical protocols to perform theinterconnection in the simplest possible way.

D.2 Aspects of a parallel systems interconnect
D.2.1 Parallel interconnect
The requirements of performance, scalability and low-cost can be met in a way that is similar to the requirements of thewhole parallel system: by allowing many instances of a cheap component to operate concurrently. Thus theinterconnect should consist of many separate connections operating simultaneously to give a high aggregate
performance. Provided each connection can be utilized at a reasonable level, its raw performance need not be very
high, which allows both component and engineering costs to be kept down. For maximum simplicity, modularity, andfault-tolerance, each connection should be point-to-point.
The requirement of low-cost implies that, at the very least, a connection to the interconnect can be implemented witha relatively small amount of circuitry in a non-exotic technology. Ideally, such a connection could be integrated onto achip with a processor or other device to minimize costs. The requirement of a small amount of circuitry implies that
protocols must be simple and require minimal buffering. At the system level, cost limits the number of signal
connections which can be used. Too large a number would make integration with a processor impractical; for example,
would limit the maximum number of connections available on a device, and lead to skew-control problems at thesystem level.
D.2.2 Routing
To connect many devices together, it is not possible to provide a direct, physical connection between every pair. Nor
is it acceptable to connect only certain pairs unless the connection pattern happens to match that required by theapplication. To enable every pair of devices to communicate without necessarily having a direct connection, data must
be routed in some way through intermediate nodes.
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In order for every pair of devices to be able to communicate, data must be routed in different ways at different times.
This can be achieved either by configuring intermediate nodes to make each connection before the data is sent, or bymaking the data self-routing so that it contains within it information which determines which way it should be routed.
Configuring the nodes in advance of the data requires that the destination of the data must be supplied to a central
controller, which increases latency, and creates the danger that the controller will become a system bottleneck. Selfrouted systems enable the control function to be distributed, and to scale in performance with the size of the system.
A piece of data together with its associated routing information is called a packet. If a packet is sent directly fromsender to receiver, it is not necessary for the length of the packet to be represented within it; it is only necessary toensure that the sender and receiver agree on the length. However, where packets pass through intermediate nodes, it
must be possible for these nodes to determine the length of the packet passing through, to determine when the task ofrouting a particular packet is complete. The requirement of low-latency implies that packets must be limited in length,
since otherwise connections could be occupied indefinitely by long packets. Since for many purposes short messages
are required, the overhead on each packet must be small, and the packet size must be variable. This requires that the
protocol provides an indication of the packet length, such as a termination marker or an initial length count.
D.2.3 Wormhole routing
In most serial packet-switching networks each intermediate node inputs a packet, decodes the header, and thenforwards the packet to the next node. This is undesirable for a parallel systems interconnect for two reasons:a)b)

It requires storage in each node for transmitted packets, which either limits the capacity of the node or
requires a separate memory (which increases costs).
It causes potentially long delays between the output of a packet and its reception, because each node waits forthe whole packet to be received before starting re-transmission, thereby increasing latency.

A more suitable approach is wormhole routing, in which only the header of the packet is initially read in by the node.
The routing decision is taken, the header is output, and the rest of the packet is sent directly from the input to the output
without being stored in the node. This means that a packet can be passing through several nodes at the same time, andthe head of the packet may be received by the destination before the whole packet has been transmitted by the source.
Thus this method can be thought of as a form of dynamic circuit switching, in which the header of the packet, in
passing through the network, creates a temporary circuit (the “wormhole”) through which the data flows. As the tail ofthe packet is pulled through, the circuit vanishes (the analogy of an earthworm pushing its way through sand is veryapt). The transmission of a single packet may thus be pipelined through a series of devices.
Note that, as far as the senders and receivers of packets are concerned, the wormhole routing is invisible. Its only effectis to minimize the latency in the message transmission. If one or more intermediate nodes were to store-and-forward
the packet it would still be delivered correctly. Note also, however, that wormhole routing has the further advantagethat it is independent of the packet length. In a store-and-forward system, the maximum packet size must be
determined in advance so that buffering can be provided; if few packets are of this size, then the extra buffering islargely unused. In addition, independence from the packet length is desirable because it achieves a clean separation oflayers of the protocol.
D.2.4 Flow control
Guaranteeing that physical connections will be available for each stage of a packet's journey requires global
information about the state of the system. Accumulating global information is time-consuming and inherently nonscalable. Thus in a low-latency, scalable system, the possibility exists that the header of a packet will be input by anode but be unable to proceed because the required output is already in use. The body of the packet will still be passing
through previous nodes. There are then three possibilities:
a)
b)
c)
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The incoming packet body is buffered in the node where the packet is stalled
The incoming data is discarded
A flow-control mechanism stops the flow of data
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The first of these, a), is a return to store-and-forward routing,10 with the disadvantage of requiring buffer resources ineach muting node. This increases cost and destroys the packet length independence of the routing. The second option,b), is undesirable because it forces the end-equipment to engage in complex protocols to deal with the possibility ofdata loss. In addition, once part of a packet has been lost the packet is probably useless and may as well be entirely
destroyed. A system using this scheme could then easily degenerate into a state where most of the connections werecarrying packets to the point of their destruction. Clearly it would be preferable to propagate information about a stallback along the path of the packet, and to implement a system of flow-control, as in c).
Rather than provide buffering for an entire packet, the flow-control system must be capable of stalling the flow of data
part-way through a packet. This implies that it operates on a level below that of packets. It is the flow of the sub-unitsof which packets are composed which must controlled. With this scheme, when a packet is unable to proceed, data may
continue to move unit all buffering along the path of the packet is filled. The flow-control mechanism must then ensurethat data movement ceases so that no buffers are overwritten. This means that all links which are still occupied thepacket will be idle; however, this is an improvement on the previous scenario in which the links would be busy moving
data to the point at which it is discarded.

D.3 Comparison with other types
In this subclause we consider how the requirements for parallel system interconnect compare with those of other typesof communications system.
D.3.1 Telecommunications systems
The principal feature of digital over long distances. This means the actual, physical most of the attributes of such
systems are a consequence of this. Because or satellite, etc.) is expensive, it is worthwhile using expensive endequipment to extract the most from it. It is justifiable to push the basic operating frequency to a level at which the biterror rate (BER) is non-negligible and to compensate for errors with very sophisticated protocols if this results in a net
improvement in data rate. Protocols may be further complicated by the need to perform a number of functions via thesame medium, since in general there will not be an alternative connection (and if there were, it would not be economic
to dedicate it only to functions which are used infrequently, however important).
The extended nature of the medium makes it vulnerable to noise and transient interruption. Information may be lost;for example, if fine-grained flow-control were employed it would frequently fall due to loss of x control information(it would also be inappropriate because of the large latencies involved). This implies that flow-control must be coarsegrained, and so large buffers must be provided. Since packets may be lost, they must be buffered for re-transmission
until positive confirmation of reception is received. This may cause further packets to be lost if the buffers of aforwarding node are full. Telecommunications systems are intrinsically prone to loss and higher-level protocols mustcompensate for this.
D.3.2 Local area networks
LANs share some of the attributes of telecommunications systems, but the balance of cost between the physicalmedium and the end-equipment is quite different. Because the cost of the medium is still significant, LANs work on
the principle that a number of pieces of end-equipment effectively share the same medium (and hence share its
bandwidth). BERs are lower, but the protocols used can still be quite complicated in order to organize the sharing of
the medium.
To economize on wiring, the most popular physical configuration of LANs is a ring. Rings may be linked together via
bridges; this improves the bandwidth because the bandwidth of each ring is shared between the active users connected
to it, while separate rings joined by bridges may operate concurrently. It also improves the fault-tolerance, since thefailure of one ring can be isolated from the others. However, the overall level of concurrency in the interconnect is low.
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D.3.3 Parallel systems interconnect
For communications in a parallel system, the constraints are rather different. When connecting devices on a board orin a card-cage, the actual cost of the wires involved is negligible. However, the pins and board area consumed by wide,
parallel connections and the difficulty of correctly routing them is considerable, and this leads to a preference for serial
communications.
Since the cost of the copper tracks is not significant, it is not necessary to maximize the data rate on each one. Nor isit essential to use a complex protocol to perform a variety of different functions on a single connection, since the costof providing separate connections, for example, for configuration, control, or monitoring purposes need not be
prohibitive.
Within a system with limited physical dimensions and reasonably clean electrical properties it is entirely feasible to
make connections with extremely low BERs (10–15 or less). Thus connections can be assumed reliable, andcomplicated systems of acknowledgments, anti-acknowledgments and retries can be avoided. Moreover, since thesystem can be designed and controlled as a whole, each part can be relied upon to obey strict rules, and need not
behave defensively with respect to other parts of the system, allowing further simplifications. Although in such
systems it is possible to make communications synchronous with a common clock, this can create serious problems ofhigh-speed clock distribution and should be avoided to keep costs down.
In such systems, the cost of the end-equipment for each connection is significant. This is because at least one such end
must be provided for each device, and so contributes to the cost of the node. For reasons of both cost and performance
it is advantageous to be able to integrate the end-equipment with the device chip(s). Thus it is preferable not to requiresensitive analogue circuitry, exotic technology (GaAs, etc.), or large amounts of logic. Replicating a simple piece of
end-equipment is more cost-effective than providing a complex one with maximum performance.
High bandwidth and low latency are essential for the communications to be matched with the speed of the devices. In
particular it is important to provide a high total bandwidth when many devices need to communicate simultaneously,
and for the latency of each communication to be moderate even under high load. Fault-tolerance is highly desirable,
and these requirements together imply that the communication should be performed via a number of independent,
concurrently operating connections, rather than one higher-speed connection.

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Annex E Switch chips, switches, and fabrics(Informative)
A switch provides a number of node interfaces, and determines how these interfaces are identified (numbered). The
standard specifies the protocols on each of these interfaces, which includes routing information defining theinterface(s) to which an individual packet is to be routed. A switch may be implemented from one or more switch chips(or by other methods). A switch chip may provide pins which directly implement switch interfaces, in which case it
can claim appropriate conformance to the standard. This standard leaves open how switch chips can be combined to
implement a switch. The standard is not prescribing how routing works, but saying some things about it essential to theuse of a switch. This allows competitive proprietary technologies for implementing the internals of switches, withoutcompromising the open nature and value of a standard for using the switches.
A fabric is a general routing capability, constructed from one or more switches. This standard defines the format for
packets which are routed through a number of such switches (the technique of “header deletion” as a packet leaves aswitch is proposed).
The standard thus can guarantee that a user can use switches from different vendors (bought possibly at different
times) in combination (subject to their using the same subset).
A network, each of whose link outputs has the same address (the value of the packet header which causes the packet
to be directed to that output), regardless of which link input is used, is called flat. The number of possible link outputsof a flat network is limited by the size of the packet header.
Two or more flat networks can be joined together without changing the addressing scheme of either, provided thatheader deletion is used on the links which join them. This means that each packet which is directed to a link output ofa flat network, which is connected to another flat network, has its header deleted. Provided the packet when introduced
into the first network has a second header applicable to the second network as the first part of its body, it can becorrectly directed to a link output of the second network. Note that it is not necessary with this scheme for the header
size to be the same in the two networks. Packets can be directed across an unlimited series of connected flat networks
provided they are introduced with enough concatenated headers.
Flat networks joined in this way are not flat because the header which is required to address a particular link output of
the combined network depends on the link input used. If the link input is one of the same flat network to which the link
output belongs, the header is shorter.
If two or more flat networks are joined together by means of a unique other flat network, rather than directly, thecombination is called hierarchical. This term is also used if one or more of the original networks is hierarchical.
Hierarchical networks have the property that there is a unique series of networks to be traversed between any particularlink input/output pair.
Other functionalities such as multicast and broadcast may be supported by a network:a)b)Multicast is the distribution of a packet to a set of destination nodes. How multicast is supported is outside thescope of this standard.
Broadcast is the distribution of a packet to all destination nodes in a network. How broadcast is supported isoutside the scope of this standard.

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Annex F Use of the transaction layer—Asynchronous transfer mode (ATM) example(Informative)
This annex discusses the mapping of the ATM onto the Transaction Layer defined in this standard.

F.1 Mapping for ATM
F.1.1 Introduction
Asynchronous Transfer Mode (ITU-T I.321 and related) is the new recommended standard for broad
telecommunications, and is being adopted in both the public and private communications marketplaces by thecomputer industries. Its main feature is that it provides a common format for the transport of dig information
supporting a wide variety of services (voice, video, data, etc.), and enables the arbitrary dynamic multiplexing of suchservices on the transmission lines and through the switches telecommunications network.
ATM supports LANs, WANs and combinations of these, and has been designed with very high s transmission links inmind (up to Gb/s rates). It is connection oriented, and defines minimal error check assuming that the “users” of theservices will perform appropriate checking.
Implementations of the Heterogeneous InterConnect international standard are likely to be cost-effective and efficientwhen applied to the implementation of ATM switches, the interfaces of applications to networks, and for intra-office
ATM lines. This annex identifies the issues which need to be addressed outlines appropriate solutions.
F.1.2 ATM networks
An ATM network is constructed by interconnecting Network Nodes (i.e., switches) with transmission p Some Network
Nodes will provide User-Network Interfaces (UNIs), for connecting the user's end tern equipment (TE). This is
illustrated in figure F.1.

Figure F.1 —ATM network
A similar interface, the Network-Network Interface (NNI) allows networks to be connected together.
It is also possible to construct a switch which will interface a number of UNI interfaces (for end user terminal
equipment) to a UNI interface on an ATM network. In practice this will frequently be used, for example, to constructlocal premise networks, interfacing them to a public network.

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ATM specifies a connection-oriented protocol. The protocol is based on the concept of the Virtual Channel
Connection. A virtual channel connection is dynamically created when required (e.g., at the start of a telephone call).
A route is established between the caller and the recipient(s) through the network, and then the desired information istransmitted as a sequence of cells (similar to packets in a data communications network) along this route; the virtualchannel connection.
Both the NNI and the UNI are capable of handling multiple virtual channels, and cells from different virtual channels
may be multiplexed in an arbitrary manner on any transmission path. A concept, similar to that of the virtual channel
and called the Virtual Path, provides a trunking mechanism for muting a group of virtual channels through several
network nodes.
F.1.3 ATM services
ATM provides a general shared network functionality by allowing the arbitrary interleaving of cells from different
virtual channels on any transmission path. ATM also addresses issues of performance and quality of service. Thus,
when a virtual channel is created, the network as a whole guarantees to provide a certain level of performance for
information transmission on the virtual channel (and, quid pro quo, the caller has to limit his demand). This has an
impact at the time the call is set up (several possible routes may be tried before an acceptable one is found), and during
information transmission, where each individual switch has to play its part in delivering the quality of service, and inensuring that an errant user does not affect the guarantees of the level of performance provided to other users.
This implies, in turn, that the design of ATM switch and/or an ATM network incorporating HIC links has to beconcerned with issues of bandwith, latency and jitter through HIC packet routers and along HIC links. Fortunately,issues concerning cell loss and, to a large extent, cell error ratios, are not of concern (although they are of major
concern in the general ATM case when other transmission technologies are used), as HIC provides flow control below
the packet (in ATM terms, the cell) level, and is only employed in circumstances where the transmission medium isrelatively reliable.
The ITU-T recommendations classify the various classes of service according to the tinting relationship between
source and destination (including whether or not some form of clock recovery is possible), the bit rate (constant orvariable), and the (connection-oriented or connectionless).
F.1.4 The ATM protocol stack
ATM uses a three layer model (see figure F.2) to define its functionality (in addition, each layer is divided into sublayers). The layers are the ATM Adaptation Layer, the ATM Layer and the Physical Layer.

Figure F.2 —ATM layers

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The key to ATM is that there is only one format (with minor variants) for the ATM layer: the ATM cell. This comprises
48 bytes of payload and a five byte header. The header provides all the information required to route individual cells
through a switch, and provides a limited amount of support for header error checking and flow control.
The function of the various ATM Adaptation Layer (AAL) definitions is to specify how user information is to be
subdivided into 48-byte payloads and re-assembled. AAL comprises a set of end-to-end protocols, and the ATM
network is not concerned with the nature of the payload information in each cell. The AAL specifications are given in
ITU-T recommendation I.363. The AALs also correspond to the various qualities of service.
AAL1

provides a constant bit rate service (i.e., it compensates for jitter), and also transmits timing information
between source and destination.
AAL2 supports variable bit-rate services, and transmits timing information between source and destination.
AAL3/4 is used for connection oriented services with no timing relationships (i.e., data transmission).
AAL5 supports an available bit-rate service, with no guarantees as to latency or bandwidth.
Note that control, status, and management information is also transmitted using the standard ATM protocols on
reserved virtual channels.
The ATM layer is processed by each switch in the network. As each cell arrives at an interface, the header information
is examined to determine on which output the cell has to be transmitted. The switch will generate a new header for thecell before outputting the cell for the next switch (or end user equipment, if the output interface is a UNI) to process.
In general, the switch will also perform buffering and scheduling of ATM cells on a particular interface, in order toensure that it satisfies its quality of service commitments (cells on one virtual channel may take priority over cells on
another virtual channel). In cases of heavy load, it may even destroy cells.
The physical layer is responsible for transmitting ATM cells between network nodes and between the network and theend user equipment. It does not have to interpret the information in the cells in any way. It converts the bytes of the cell
into an appropriate bit encoding, and transmits these serially in either a framed (e.g., SONET/SDH) or unframed
format. There are a large number of different standards available for the physical media giving a wide range of speed/
distance/performance trade-offs. Many of these standards are based on existing ITU-T telecommunications standards[e.g., ITU-T G707-709 for SDH (Synchronous Digital Hierarchy)]. More industry agreements defining further
physical specifications are being developed, particularly for local area networks, by the ATM Forum.
F.1.5 Virtual channels and virtual paths
ATM cells are transmitted from source to destination along virtual channel connections. When a call is set up, the TE
negotiates with the UNI for a virtual channel identifier (VCI), which it places in the cell header. Virtual channels aregrouped into virtual paths, and the negotiation will also concern a virtual path identifier (VPI). (The negotiation may
be to add a new virtual channel to an existing virtual path, using the existing VPI, or may create a new virtual path, witha new VPI). This relationship is illustrated in figure F.3.
Each unidirectional transmission path between two network nodes implements one or more virtual path links. A virtual
path connection (VPC) is formed by concatenating a number of virtual path links, using transmission lines between
appropriate nodes of the network (or between a network node and a terminal equipment). Each node along the virtual
path connection will switch the cells arriving on the input transmission path to the corresponding output transmission
path.

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Figure F.3 —Virtual channels and virtual paths
In general, a number of virtual path links will share the same transmission path. A separate VPI is used for each virtual
path link, and is negotiated between the two network nodes concerned. When switching between one virtual path link
and another (i.e., on the same virtual path connection), the network node examines the cell, uses the VPI (which was
negotiated between it and the previous node when the path was established) to determine the output transmission path,and replaces the VPI with the appropriate value, as negotiated between it and the next cell.
The virtual channel system works in exactly the same way, except that the transmission paths between one node andthe next are replaced by virtual path connections, and the nodes switch information for individual virtual channels.
Each virtual path connection can support a number of virtual channel links, and each virtual channel link has its
associated virtual channel identifier VCI. A virtual channel connection (VCC) comprises a number of concatenatedvirtual channel links. A more sophisticated form of network node supports the “end-points” of virtual paths, and willswitch between virtual channels. This will use both the VCI and the VPI to identify the virtual channel, and will
replace both in the header. An important point is that the negotiation for VCI numbers takes place between the two
nodes at either end of a virtual path connection carrying the new virtual channel, not between physically adjacentnodes. The principles of virtual path and virtual channel switching are illustrated in figure F.4.

Figure F.4 —Example of virtual path and virtual channel switching

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Certain virtual channels are reserved for special purposes. Some are used for maintenance and resource management,
and some are used for signaling purposes (e.g., for call set-up). Unassigned cells (representing unused bandwidth) are
given the VPI/VCI value 0/0. Each interface has a meta-signaling channel (VCI value 1). Requests are made on thisvirtual channel to establish further signaling channels (e.g., a call setup is not negotiated on the meta-channel, but ona virtual channel designated for the purpose, whose identity is communicated to the caller on the meta-channel).
It may be possible to create a virtual path through a network, in which case the negotiation on VCI allocation can takeplace between the TE at either end.
Part of the setup negotiation procedure between two nodes is to agree on the number of virtual paths that can besupported between them, and the number of virtual channels that each virtual path can support. This allows buffer
sizes, etc., to be allocated from a finite memory in each node.
The format at the UNI of ATM header is illustrated in figure F.5.

Figure F.5 —ATM cell header
The format at the NNI is identical with the exception of the replacement of GFC by four more bits for VPI.
The GFC (generic flow control) is present only at the UNI, and is used to throttle the rate at which the TE supplies
information to the UNI. The PT (payload type) and CLP (cell loss priority) bits are not of concern to the mapping tolinks confirming to this international standard (beyond the fact that such links may have to transmit this information;see ), and their use is outside the scope of this subclause. The HEC (Header Error Control) is checked by the
implementation of the physical layer on cell arrival, and generated immediately before cell departure. Whether the
HEC has to be carded is discussed in F.1.6.10.
F.1.6 Mappings for ATM applications interfaces and switch implementations
This international standard has been developed particularly to support parallel system construction. Within a TE, thisstandard will be particularly valuable when there is a significant degree of logical parallelism, for example where there
are multiple virtual channels to an application, and/or multiple applications, and/or multiple transmission lines (tomultiple UNIs), and when the bandwidth required mitigates against the use of buses and similar structures.
F.1.6.1 Terminal equipment systems
For case of description, the reference model illustrated in figure F.6 is used.
In general, each transmission path (ending in the line termination unit) will be carrying a number of virtual paths, eachin turn carrying a number of virtual channels.

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Figure F.6 —Mapping reference model
The line termination module implements the appropriate PHY (physical layer) interface, and passes a string of bytes
to the ATM layer processing function. This function processes the cell header and prepares it for routing through a
network conforming to this standard. The function of the routing network is to route each virtual channel to theappropriate applicafion or to an ATM output. In the reverse direction, the application will generate ATM cells, but witha header as specified in clause 9., which will be routed to the ATM layer processing function associated with thetransmisson interface supporting the appropriate virtual channel. The ATM layer processing function will generate theappropriate ATM header and pass the cell onto the PHY interface for onward transmission.
The application will perform the appropriate AAL functions and higher level protocol handling.
F.1.6.2 Physical level
Any appropriate link conforming to may be used. Note that the intended implementation is within a rack for which DSSE or HS-SE links would be most appropriate.
F.1.6.3 Character level
Each octet of the ATM cell is encoded as a 10 b DS-SE character, a 12 b TS-FO character or a 12 b HS-SE character
as appropriate.
Note that although ATM is “big-endian” (for bit ordering) and the links specified by this standard “little endian,” theuse of translation into one of character encodings specified in this standard provides a clean separation between thesetwo. There is no direct translation between the ATM bit stream and a bit stream confirming to this standard.
F.1.6.4 Exchange level
The flow control corresponding to DS-SE or HS-SE links is used.
F.1.6.5 Packet level
ATM user cells are mapped by the ATM layer processing unit as follows:

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Traffic from external ATM sources
The VPI, possibly with the VCI, is used to determine a routing header as specified in clause 9., and is then translated(if necessary; i.e., if the cell is going to an ATM output). The ATM layer forms a packet which complies with clause
9. starting with the routing header, following by the ATM header (with the translated VPI/VCI, followed by the 48
bytes of payload, followed by an end of packet character.
Routing may be performed on the basis of just the VPI or both the VPI and VCI. The prime role of the control unit is
to allocate the headers. All units exchange messages with the control unit to request identifiers, and to relinquish
identifiers when no longer required. This is analogous with and happens as part of the creation and deletion of virtualchannels.
ATM signaling cells are processed by the ATM layer processing unit directly, which then sends appropriate messages
to the control unit (usually to create or to free up the internal route for the VPI/VCI). The control unit will send
appropriate messages to the application to open/close the internal route. These messages are analogous to the signaling
messages at the UNI.
ATM layer OAM (operations and maintenance) cells are processed by the ATM layer processing unit directly. Lower
level OAM cells will be taken out of the cell stream by the PHY layer, and higher levels will be dealt with by the AAL
processing in the front end of the application.
VPI/VCI origination
The ATM layer identifies the ATM header required from the internal routing header (many routing headers will lead tothe same ATM layer processing unit). The ATM layer adds the VPI/VCI fields, the PT and the CLP. A GFC field may
be added if needed but is not otherwise relevant to the contents of the cell. Note that the HEC will be computed andadded by the PHY layer (line termination).
F.1.6.6 Control messages
Control messages are routed to the control unit. This will cause the routing tables in the line units and application units
to be updated to reflect the resulting changes in the VCIs/VPIs. The way in which this happens is implementation
dependent. Note that this function can be carded out by the routing network itself if care is taken to allocate routing
headers for this internal management function that are distinct from the routing headers for this internal management
function that are distinct from the routing headers used to implement the internal ATM cell routing.
F.1.6.7 Performance aspects
The overall performance of the TE system need not, in general, be limited by the performance of the interconnect itself(in contrast to bus or ring based systems). The overall bandwidth will be limited either by the bandwidth to the ATM
network(s), by the amount of bandwidth that the ATM network can accept (a quality of service issue), or by the
bandwidth of the applications.
The latency through the interconnect will, in general, add very little to the time taken to transmit a single cell throughthe interconnect (note that this is from start of transmission of the cell to start of reception; in ATM evaluation, thelatency is conventionally taken from the start of transmission to the completion of reception).
However, it is possible for congestion to occur as a result of several cells competing for the same destination (either anapplication or, in the other direction, an ATM layer processing unit). The network's flow control, as specified in thisstandard, will result in cells being delayed, rather than being discarded, which greatly cases the management function.
The effects of delay can be minimized by ensuring sufficient buffering at the point of competition for the maximum
number of cells which can compete in this way. If the traffic has a predictable or random distribution, then nearly
optimal performance can be achieved by using much less buffering. The effects of delay can also be greatly reduced byusing multiple physical links to appropriate units, or even the use of multiple networks (the latter can also provide a118

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very high measure of fault tolerance). In general it will be possible to engineer such TE systems, providing a
sophisticated functionality, without the ATM layer processing having to discard cells.
F.1.6.8 Physical aspects
The interconnect compliant with this international standard may be implemented as a fixed, hard-wired system, or
using an active backplane (or center plane), or as an active board-based interconnect with mezzanine cards. The latter
two options provide the possibility for, on the one hand, line handling and ATM layer cards to be plugged into the TE,
and, on the other hand, applications to be plugged into the system.
In such systems, each slot would carry one or more physical links compliant with this standard. The interconnect
would define a muting topology, and allocate a range of logical channels to each physical link (i.e., header numbers).
This topology and allocation would be engineered into the system and established no later than at power-on/reset time.
One logical channel would be reserved for meta-signaling purposes. The identities of the logical channels for eachphysical link would be known to the control card. A simple form of initialization would be for the control card totransmit a wakeup message on each meta-signaling channel. Each unit (ATM layer processing or application) would
be able to respond, using as destination a logical channel identified in the wakeup message. This system would be able
to handle live insertion (provided that the physical engineering is appropriate).
F.1.6.9 ATM switchingThis operates very similarly to a combination of the two cases described in . However, the processing at the ATM layer
is somewhat different.
It is necessary to perform a full VPI/VCI translation. The options for this are as follows:a)b)

To perform it at the time that the incoming VPI/VCI is translated. The packet transmitted through the network
therefore has the new ATM header (apart from the GFC and HEC, which are added as in ).
To perform it on output. This has the advantage that the bandwidth through the switch is slightly less, but has
the disadvantage of requiring two translations (the translation on input is essential in any case). The ATM
layer processing on output also has to add in the appropriate PT and CLP fields (these can be obtained at thesame time as the outgoing VPI/VCI information).

On balance, a) is preferred. (If this option is taken, then for application interfaces it would be preferable for the header
to be passed to the application, and for the application to generate the outgoing header.)F.1.6.10 Mappings for ATM lines
This international standard can be used to provide a PHY implementation. DS-DE, TS-FO and HS-FO links arerecommended for this purpose. This standard provides, in ATM terminology, a cell based option (as against a framed
implementation, e.g., Synchronous Data Hierarchy (SDH) or Plesiosochronous Data Hierarchy (PDH)).
The PHY layer of ATM is divided into two sub-layers; transmission convergence (which translates the cell into a stringof bits) and physical medium.
Transmission convergence is split into the functions of






Cell rate decoupling
HEC header sequence generation/verification
Cell delineation
Transmission frame adaptation
Transmission frame generation/recovery

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For links compliant with this standard, only the first of these is necessary, though the second should be used to give
added confidence, and to assist translation into some other medium. Note that scrambling is not necessary for
implementations compliant with this standard and is not recommended. Cell delineation is required. The other two
functions are only appropriate to framed transmission. However, they are replaced by the character layer of thisstandard corresponding to the physical medium being used.
There are two approaches:a)b)

HEC and cell delineation is performed as described in the ATM specification. Note that this approach is likely
to be unnecessarily expensive, as it is designed to compensate for difficulties unlikely to be encountered with
implementations compliant with this standard.
HEC is not performed, and an end_of_packet marker is placed between each cell for cell delineation.

Note that the use of the character encoding specified in this standard allows the use of the exchange level functionality
for flow control.
The physical medium functions are the corresponding layers of this international standard.

F.2 Bibliography(informative)[B1] ITU-T Recommendation I.113: 1994, (Rev.2) Vocabulary of Terms for Broadband Aspects of ISDN.
[B2] ITU-T Recommendation I.121: 1991, (Rev. 1) Broadband Aspects of ISDN.
[B3] ITU-T Recommendation I.150: 1991, B-ISDN ATM Functional Characteristics.
[B4] ITU-T Recommendation I.211: 1993, B-ISDN Service Aspects.
[B5] ITU-T Recommendation I.311: 1993, (Rev. 1) B-ISDN General Network Aspects.
[B6] ITU-T Recommendation I.321:1991, (Rev. 1) B-ISDN Protocol Reference Model and its Application.
[B7] ITU-T Recommendation I.327: 1993, (Rev. 1) B-ISDN Functional Architecture.
[B8] ITU-T Recommendation I.361: 1993, (Rev. 1) B-ISDN ATM Layer Specification.
[B9] ITU-T Recommendation I.362: 1993, (Rev. 1) B-ISDN ATM Adaptation Layer (AAL) Functional Description.
[B10] ITU-T Recommendation I.363: 1993, (Rev. 1) B-ISDN ATM Adaptation Layer (AAL) Specification.
[B11] ITU-T Recommendation I.364: 1993, (Rev. 1) Support of Broadband Connectionless Data Service on B-ISDN.
[B12] ITU-T Recommendation I.371:1993, Traffic and Congestion Control in B-ISDN.
[B13] ITU-T Recommendation I.413:1993, (Rev. 1) B-ISDN User-Network Interface.
[B14] ITU-T Recommendation I.414:1993, Overview of Recommendations on Layer 1 for ISDN and B-ISDN
Customer Accesses.
[B15] ITU-T I.432:1994, (Rev. 1) B-ISDN User-Network Interface—Physical Layer Specification.
[B16] ITU-T I.610: 1994, (Rev. 1) B-ISDN OAM Principles and Functions.

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Annex G Error handling(Informative)
The links specified in this standard are designed to be highly reliable and therefore able to use lightweight protocols(giving all the advantages discussed in annex D). However, implementers may decide in their particular use of a link
more protection is required against errors than is provided by the mandatory protocols. This could be the case, forexample, when using a fiber optic link (where the manufacturers often specify a BER of 10–12) or an electrical link ina noisy environment, or when accidental disconnection of a link is to be expected. In general, in applications where allconnections are on a single board or within a single box, the communications system can reasonably be regarded as
being reliable. In this environment errors are considered to be rate, but may be treated as being catastrophic should one
occur. If an error occurs it should be detected and reported. Normal practice should then be to reset the subsystem inwhich the error has occurred and to restart the application. This minimizes the overhead on each communication, but
if an error does occur there will be an interruption in the operation of the system.
For other applications, such as when a disconnect or parity error may be expected during normal operation, a higher
level of fault-tolerance may be required. Possible approaches in this case are the following:
a)

b)

c)

Localize errors to the link on which they occur. If an error occurs, packets in transit at the time of the error
will be discarded or truncated, and the link will be reset automatically. This minimizes the interruption of theoperation of a system, but imposes an overhead on all communications to deal with the possibility data may
be lost.
A localized retry mechanism could use & local positive acknowledge system to confirm correct transmissionof data between two nodes, storing the data at the transmitter until it has been acknowledged as correctly
received. One approach would be to increase the role of the Flow Control Character to make it an
acknowledge of correct transmission of a block of data, and to store blocks at the transmitter until
acknowledged. The advantage is that the effect of errors is localized and dealt with on a link by link basis andso do not become a system-wide problem (i.e., errors are detected and corrected at the Exchange Level). The
error detection mechanism may be the character by character parity check, or may insert extra codes into thedata (e.g., longitudinal parity check or a cyclic redundancy code,). Such a increased buffering at each linkinterface, more complex protocols, and increases the latency of transmission.
A packet level check is used to check the validity of each packet's payload at its destination node. This isnormally achieved by appending an error checking code (e.g., a CRC) to the payload. Since this code isnormally calculated as the data is transmitted, it is added to the end of the payload. This implies that thedestination node cannot check the validity of the payload until it has received the whole packet. The
transaction levels decide when to use the incoming packet. A hardware retry at the packet level would be
difficult to implement, since it implies the packet level needs to know the source address of the erroneous
packet and a packet ID number, so that it can request retransmission (even if it could extract these from thepacket, it cannot be sure that these were not the bytes in error). It would be easier to leave the task to thetransaction level and higher: any erroneous packet is discarded at arrival by the packet level, and a signal ispassed up the levels to indicate the problem. Since the transaction level knows with which other terminal node
it is communicating, retransmission can be requested. In some implementations, the error checking code
could be checked in each routing node. In others, such as combining networks, the payload may be changedin the routing node, and the error checking code has to be recalculated. The error checking code may notcover the destination field of the packet, because the latter's contents may be modified by header deletion andmulticast functionalities. Adding an error checking or correcting code to each destination identifier ispossible and relatively simple. By doing this, each destination is checked before the routing decision is taken.

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Annex H Flow control calculations(Informative)
Using the flow control mechanism described in 4.2.3.3, there exists a theoretical maximum line length over which
continuous transmission can be obtained in the case where every N_char written into the sink is immediately read outof the sink by the receive application. This maximum length is determined by the size of the sink (which determines
the number of FCCs that the receiver sends to the transmitter after start-up and thus the initial transmitter credit).
Considering the general situation in which
a)
b)
c)
d)
e)

The sink size is B N_chars (which are available to the receiver)
The flow control block size is F N_chars
The transmitter sends a N_char every cycle of T ns
The length of the transmission line is D meters (at 5 ns/meter propagation time)
The bidirectional link has a latency parameter of L cycles

The source thus acquires an initial credit of B N_chars and therefore starts to transmit its N_chars. As the receiverreceives the data, it writes it into the sink, from which the receive user immediately reads it. When the user has read F
N_chars, the sink authorizes the sending of a FCC. The condition for continuous transmission is that the FCC arrives
at the transmitter before the latter's credit is consumed. The timings are shown in figure H.1.
The last N_char of the first data block (where a data block is F N_chars) is read by the receive user (L1.T + 5
D) ns after it is sent (assuming 5 ns/m cable propagation time).
There is a delay of L2.T ns before the FCC is sent.
The FCC arrives at the opposite receiver after (L3.T + 5 D) ns
The transmitter's credit is incremented after L4.T ns

The total time is therefore (LT + 10 D) ns.
where
L = L1 + L2 + L3 + L4
For continuous transmission, this time has to be inferior to (B-F).T.
Therefore,
Dmax = (T÷10).(B−F−(L1 + L2 + L3 + L4)
The relationship in a typical implementation between sink size and maximum distance for continuous transmission for
DS (operating at 200 MBd), TS and HS (operating at 1 Gbd) links is shown in figures H.2 and H.3.

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Figure H.1—Theoretical maximum transmission length calculation

Figure H.2—Distance vs. buffer size for DS and TS links

Figure H.3—Distance vs. buffer size for HS-SE links

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Annex I Synchronized channel communications(Informative)

I.1 Introduction
A widely used model for the design and programming of concurrent systems is that of Communicating Sequential
Processes (CSP). It is sufficiently abstract that the “processes” can be software processes executed by a CPU, or
hardware state machines, or even a mixture of the two. Implementing the full generality of this model on a distributed
system is very difficult, but the restricted (yet still very powerful) version in which concurrent processes interact purely
pairwise by exchanging messages on pre-defined channels can be implemented very efficiently over the links specified
in this standard.

I.2 Synchronized communication
The CSP model is one of asynchronous concurrent processes, which can perform internal actions or interact with one
another. Interactions are always synchronized, i.e., they do not occur until all processes involved are ready toparticipate. If any process is not ready, all other processes wait until it is. Once all the processes are ready, theinteraction takes place and they all continue asynchronously once more.
I.2.1 Channel communication
A restricted form of interaction is channel communication. In this model, each process is permitted to interact with
only one other process at a time. This interaction takes place via a named intermediate object called a channel, and also
involves a transfer of a message between the two processes. To communicate, one process outputs a message to thechannel and another inputs from it. Whichever process performs its action first waits for the other. Once both processes
are ready, the message is transferred and the processes continue. This model is straightforward to work with because
neither process proceeds beyond the communication until the inputting process has a complete copy of the message.
This means that the outputting process is immediately free to modify its data, while the inputting process is guaranteeda stable copy. Note that processes and channels are distinct; different processes may use the same channel at different
times, and the same processes may use different channels at different times.

I.3 Virtual channels
Annex I describes a transaction layer protocol which can allow an arbitrary number of synchronized channel
communications over one or more links conforming to this standard. Since this time-shares a limited physical resource
between a number of uses, the channels on which the communication takes place are called virtual channels by
analogy with virtual memory in computers. Like virtual memory, virtual channels make programming easier at somecost in hardware; generally, a good trade-off for overall effectiveness.
I.3.1 Division of messages into packets
The messages communicated between processes can be any size. To multiplex arbitrary length messages on a numberof virtual channels down a single physical channel, each message must be broken down into a sequence of packets, all(or nearly all) of the same size, so that the packets of different messages can be interleaved. Since short messages (andthe last parts of long messages) will not occupy a whole fixed-size packet there must be information as to where thepacket ends. Moreover, since an arbitrary set of virtual channels may be multiplexed at any moment (in contrast to
time-division multiplexing), each packet must contain header information identifying which channel it is on. Thus acomplete packet consists of a header, the data, and an indication of length. The link protocol includes control codes toindicate the point at which a packet ends.

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I.3.1.1 Acknowledge packets
The system just described is asynchronous at the packet level. To maintain the synchronized communication of CSP(where each communicating process waits until the data transfer is complete before continuing) and to ensure no data
is lost or overwritten, each packet is acknowledged by the recipient before another is sent, and all the packets of amessage must be acknowledged before the sending process continues. The simplest way to do this is to send an
acknowledge packet back to the sender when the data packet is received by a process. If the inputting process is readythere need be no break in transmission, since the acknowledge packet can be sent as soon as the start of the data packet
is seen.
I.3.2 Packet formats
Two formats of packet are used. All packets start with one or more bytes of header, including the dest_id, and end with
an EOP character. The minimal size of header is the dest_id length. The additional number of header bytes required isa function of the node addressed by the dest_id. If a node implements only one virtual link, no additional bytes are
required. If it implements many, the additional header must be long enough to index them all. If there are no further
bytes of payload after the header bytes and the packet is terminated with an EOP_1 packet, the packet is an
acknowledge packet, otherwise it is a data packet. The additional bytes of payload in a data packet are limited by a
network-wide maximum packet size. A suitable value is 32 B.
I.3.3 Virtual links
Since each data packet must be acknowledged before the next is sent, for each choice of header for transmission of data
packets from node A to there must be a corresponding choice of header for transmission of acknowledge packets fromto node. A One choice is to distinguish data and acknowledge packets; this choice can be utilized for data packets fromnode B to node A. Conversely, where there is already such a choice for sending data the same choice can be used toacknowledge packets as well. Thus there is a natural pairing of headers between. A choice of header to use in eachdirection and a connection between these two headers at each end is called a virtual link, which provides a pair of
virtual CSP channels, one in each direction.

I.4 Protocol
I.4.1 Message transmission
Communication on a nodes (node A and node B) proceeds as follows: when a process on node A the corresponding
virtual link is added to a queue of virtual links the corresponding interface(s). (A queue is necessary in order toperform multiplexing between many virtual channels, and can be omitted if a node only implements one virtual link.)
When the virtual link reaches the head of the queue, node A sends a data packet, including the header associated withthis end of the virtual link (which is sufficient to direct the packet to node B), via the interface. If the amount of data
to be sent is less than or equal to the maximum amount of data that can be contained in a packet, the whole of themessage is sent in one packet, which is terminated with an EOP_2 character; otherwise the first part of the message issent in a packet containing the maximum amount of data, terminated with an EOP_1 character. No further data is senton this virtual link, and neither is the outputting process allowed to continue, until an acknowledge packet is received.
When an acknowledge packet is received whose header is associated with this virtual link, if the last packet of themessage has been transmitted, the outputting process is allowed to continue, otherwise the virtual link is returned tothe queue and the above process is repeated.
I.4.2 Message reception
When a packet arrives on an interface of some node (node B), the node extracts the identifier of the virtual link fromthe header and determines the format of the packet. If it is an acknowledge packet, it proceeds as above. If it is a data
packet, the node checks to see whether there is a process waiting to receive a message on this virtual link. Associatedwith each end of a virtual link is a buffer sufficient to contain a whole packet of data of the maximum allowed size. If

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the first packet of a message arrives before there is a process ready to receive it, it is stored in this buffer until a process
is ready. If and when there is a process waiting to receive a message, the data in the packet is supplied to the process,and the corresponding virtual link is added to a queue of virtual links waiting to send an acknowledge packet on thecorresponding interface(s). (A queue is necessary in order to perform multiplexing between many virtual channels,
and can be omitted if a node only implements one virtual link.) When the virtual link reaches the head of the queue,
node B sends an acknowledge packet via the interface, including the header associated with this end of the virtual link,
which is sufficient to direct the packet to node A. If the received data packet ends with an EOP_1 character, it is not thelast packet of the message, and so the inputting process must continue to wait. If the packet ends with an EOP_2
character, it is the last packet of the message, and so the inputting process can proceed.

I.5 Notes
This transaction protocol operates with an extremely simple packet format. Note that the pre-assigned connection
between incoming and outgoing headers between nodes connected by a virtual link avoids the necessity for packets tocontain any source information. Also, the strict exchange of an acknowledge packet for each data packet ensures data
sequence integrity on each virtual channel and avoids the need for sequence numbering. Using the packet length and
EOP type to distinguish different packet formats avoids the need for packet format type fields. Thus each packet
consists only of the header identifying the destination node and virtual link, and the data (if any). Using the EOP_2
character to signify the end of a message allows nodes to exchange messages whose length is previously unknown.
Without this technique, a separate communication or more complex packet format would be required to communicate
the length information.

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Annex J Example DS-SE driver circuit(Informative)
The following equivalent circuit may be used to simulate the output from DS-SE pad drivers. It has been done in sucha manner that any circuit simulator (provided it can model inductors) will be capable of modeling the link pad driver,with no reliance on any specific device models.
The circuit should be constructed from idealized components with the parameters listed below. For simulation time
reasons it may be preferable to add a small capacitance (e.g., 100 fF) between the MOS device drains and theirrespective supply. In addition it is more realistic to add a supply-to-supply capacitance for the IC which will depend on
which chip the DS-SE link is on. This may be 1 uF to only a few 100 pF.
Table J. 1 lists the parameters covering the full range of processing, temperature and supply voltage encountered by a
DS-SE link. Vdd may have the range 4.5 V to 5.5 V.
Table J.1—Parameter spread for DS-SE link driver
Parameter

Units

Minimum

MaximumRonp, Vds=-1 V

Ohms

106

481

Ronn, Vds=1V

Ohms

25

82

Rp

Ohms

332

508

Rn

Ohms

227

333

tpd, rising and falling transitions

ns

0.66

2.0

tf, 10/90% of Vdd, Va,Vb,Vc,Vd

ns

1.2

2.3

tr, 10/90% of Vdd, Va,Vb,Vc,Vd

ns

1.5

2.8

Cpad

pF

0.5

0.5

Cpcb, any interconnect before transmission line

pF

2.0

As board layout dictates

In SPICE simulations the following model may be used for the transistors:.model n

nmos

Level=1

vt0=0.7

kp=50utox=40nmodel ppmos

Level=1

vt:0=0.7

kp=20utox=40nThis leads to the following transistor sizes (at 27C only):
Ronn (max.)

w=55u

l=1u

Ronn (min.)w=175ul=1uRonp (max.)

w=23u

l=1u

Ronp (min.)

w=102ul=1u

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The circuit diagram is given in figure J. 1.
Waveforms for Va, Vb, Vc and Vd are given in figure J.2.

Figure J.1—S-SE pad equivalent circuit

Figure J.2—Simulation input waveforms

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Annex K DS-DE optional power supply recommendation(Informative)
K.1 General
The optional output power supplied from the DS-DE link connector is designed to supply 2 W at 5 V to circuitry
attached to a short cable. With an 80% efficient dc-dc converter supplying the 2W load, the power input required by thedc-dc converter is 2.5 W.
To meet the specification, various components should be used to protect from different fault conditions:
a)
b)
c)

A polymer fuse is used to protect both equipment and load from a short circuit load.
A diode is used in case a cable is connected between two connectors; both have power available.
A relatively low value bleeder path to ground (10 kω) is used to assure that the diode is forward biased to a
low impedance even if the far end of the cable is disconnected.

The polymer fuse, like any fuse, takes a finite time to trip. In order to limit the current to an acceptable level until thefuse trips, a resistor may be required in series with the fuse and diode. if it is acceptable that under fault conditions of
the attached cable or remote unit that the equipment falls, or if there is sufficient resistance in the other components,
or if there is sufficient capacitance and power-supply capability to withstand the short period of high current, thenresistor can be eliminated and the 2.5 W be supplied by a lower current and higher voltage.
An example circuit with these components is shown in figure K. 1.

Figure K.1—Optional power supply circuit

K.2 Example components
Suitable fuses are Bourns MF-SM-100-2 or Raychem SMD 100-2. These are polymer fuses which self-heal after thefault is removed. They reset to a low resistance very quickly (20 s) although they can take up to an hour to recover tothe specified maximum resistance value.
A suitable diode is BYV10-30, available from Philips and SGS-THOMSON; diodes are available with lower forward
voltage drops, but many more are available with 0.55 V drop, including diodes with higher breakdown voltage if thisis deemed necessary.
Possible power supply components, depending on the required load, are the National Semiconductor “Simple
Switcher,” the Maxim MAX731, or the Linear Technology LT1302.

K.3 EMCIt may be desirable to fit common-mode chokes to ensure (for controlling EMC emissions) that the current out frompin 1c is equaled by the current into pin 2c. The resistance of such a choke may eliminate the need for any resistors
such as the 0.3 Ω shown in figure K.1.
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Annex L DS-DE fixed connector PCB recommendation(Informative)
The recommended DS-DE fixed connector PCB layout is given in table L.1 and figure L. 1.
Table L.1—PCB details for DS-DE connector attachment
Parameter

Value

Electrical termination, PCB connector

solderPC hole diameter contact
PC hole diameter location peg
Printed board thickness, daughter card

Reference

0.6 mm min.

Draft IEC 1076-4-101

2.0 mm ± 0.05 mm

Draft IEC 1076-4-101

2.7 mm max.

Figure L.1—DS-DE fixed connector PCB layout

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Annex M DS-DE cable (10 core) recommendation(Informative)
The cable required for a differential DS-DE link cable consists of five shielded, twisted pairs, which are then shielded
overall. Each differential pair shall have a characteristic impedance of 100 ω A suitable cable would be a 10 conductor
30 AWG composite cable, as shown in the figure M.1 and specified in table M.1.

Figure M.1—Recommended DS-DE link cable cross section
Table M.1—Recommended DS-DE link cable specification
Pair
Conductor

30 AWG 7/38 tin plated copper, 0.30 mm diameter

Insulation

0.22 mm polypropylene, 0.74 mm diameter, dielectric constant is 2.24

Pair

Two insulated conductors twisted together

Pair shield

0.025 mm/0.025 mm polyester tape, aluminum side facing out, 25% overlap
Cable

Core

Polypropylene filler

Layer 1Five pairs twisted around the core

Inner shield

Aluminium/Polyester/Aluminium tape, 25% overlap

Outer shield

36 AWG tin plated copper braid, 65% nominal coverage

JacketSuper flexible PVC, loosely applied to enhance flexibility, color; black

Diameter

5.46 mm ± 0.25 mm

With the 5 dB power budget allocated for the cable, a typical cable length of 10 m may be used.

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Annex N DS-DE multiway connector housing recommendation(Informative)
Figures N.1 and N.2 show the recommended way of constructing multiway DS-DE connector housings.

Figure N.1—DS-DE connector multiway housing

Figure N.2—DS-DE (multiway) front panel cut-out

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SCALABLE SERIAL INTERCONNECT FOR PARALLEL SYSTEM CONSTRUCTION)IEEE Std 1355-1995

Annex O HS-SE fixed connector PCB recommendation(Informative)
Figure O.1 shows the recommendation for the HS-SE fixed connector PCB layout.

Figure O.1—Recommended HS-SE fixed connector PCB layout

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133IEEE Std 1355-1995

IEEE STANDARD FOR HETEROGENEOUS INTERCONNECT (HIC) (LOW-COST, LOW-LATENCY

Annex P HS-SE cable recommendation(Informative)

Figure P.1—Recommended HS-SE link shielded cable cross section
Table P.1—Recommended HS-SE cable specifications
Single minicoaxial cable
Conductor

22 AWG 7/30 tinned copper

Dielectric

Cellular polyolefin

Shield38 TC braid, 95 % min. coverage

Jacket0.152 mm wall thermoplastic
Cable

Core

2 coaxial components laid parallel

Shield38 TC braid, 85% min. coverage

Jacket0.763 mm wall thermoplastic

With the 6 dB power budget allocated for the cable, a typical cable length of 8 m may be used.

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SCALABLE SERIAL INTERCONNECT FOR PARALLEL SYSTEM CONSTRUCTION)IEEE Std 1355-1995

Annex Q HS-SE connector multiway housing recommendation(Informative)
Figure Q. 1 and Q.2 show the recommended way of constructing multiway HS-SE connector housings.

Figure Q.1—HS-SE multiway housing

Figure Q.2—HS-SE (multiway) front panel cut out

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IEEE STANDARD FOR HETEROGENEOUS INTERCONNECT (HIC) (LOW-COST, LOW-LATENCY

Annex R TS/HS-FO connector PCB and front panel cut-out recommendation(Informative)

Figure R.1—TS/HS-FO fixed connector PCB footprint

Figure R.2—TS/HS-FO fixed connector front panel cut-out

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SCALABLE SERIAL INTERCONNECT FOR PARALLEL SYSTEM CONSTRUCTION)IEEE Std 1355-1995

Annex S TS/HS-FO fiber cable recommendation(Informative)

Figure S.1—Example of TS/HS-FO fiber cable structure

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