x86 Intrinsics Cheat Sheet
Jan Finis
finis@in.tum.de

Bit Operations

Conversions

Boolean Logic

Bit Shifting & Rotation
Arithmetic
Shift Right

Bool XOR

Bool AND

Bool NOT AND

Bool ORSSE
SSE2
si128,ps[SSE],pd
mi xor_si128(mi a,mi b)

SSE
SSE2
si128,ps[SSE],pd
mi and_si128(mi a,mi b)

SSE
SSE2
si128,ps[SSE],pd
mi andnot_si128(mi a,mi b)!a & bSSE
SSE2
si128,ps[SSE],pd
mi or_si128(mi a,mi b)

xor

and

Selective Bit Moving
Bit Scatter(Deposit) ≤64
_pdep

BMI2

_pext

u32-64
NOTE: Extract bits from a at
the corresponding bit
locations specified by mask
m to contiguous low bits indst; the remaining upper
bits in dst are set to zero.

u64 _pdep_u64(u64 a,u64 m)

u64 _pext_u64(u64 a, u64 m)

SSE2

Extract Bits

≤64

Reset Lowest
1-Bit ≤64
BMI1

u32-64
NOTE: Zeros all bits in ahigher than and including
the bit at index i.

_blsr

VariableArithmetic Shift

Variable Logic
Shift

AVX2

Find Lowest
1-Bit ≤64

_blsmskBMI1

u32-64
NOTE: Returns a but withthe lowest 1-bit set to 0.
u64 _blsr_u64(u64 a)(a-1) & au64 _bzhi_u64(u64 a, u32 i)
dst := a
IF (i[7:0] < 64)
dst[63:n] := 0

mi slli_epi32(mi a,ii i)
mi sll_epi32(mi a,mi b)

mi slav_epi32(mi a,mi b)

mi sllv_epi32(mi a,mi b)

u32-64

Bit Counting

u32-64
NOTE: Returns an int thathas only the lowest 1-bit in aor no bit set if a is 0.
u64 _blsi_u64(u64 a)(-a) & a

NOTE: Returns an int thathas all bits set up to andincluding the lowest 1-bit ina or no bit set if a is 0.
u64 _blsmsk_u64(u64 a)(a-1) ^ a

POPCNT≤64_[l]rot[w]l/r

x86

Sign Extend
cvtX_Y

SSE4.1

pack[u]sSSE2

epi16,epi32
NOTE: Packs ints from two
input registers into one
register halving the bitwidth.
Overflows are handled using
saturation. The u version
saturates to the unsigned
integer type.

Zero Extend
SSE4.1

cvtX_Y

epi8-32

epu8-32 → epi8-32

NOTE: Sign extends eachelement from X to Y. Y must
be longer than X.

NOTE: Zero extends eachelement from X to Y. Y must
be longer than X.

mi cvtepi8_epi32(mi a)

mi cvtepu8_epi32(mi a)

mi pack_epi32(mi a,mi b)

Single Element Conversion
Bit ScanForward/Reverse

128
SSE2

NOTE: Returns the index of
the lowest/highest bit set inthe 32bit int a. Undefined if
a is 0.

Count Trailing
Zeros ≤64

LZCNT

BMI1

_lzcntu32-64
NOTE: Counts the number ofleading zeros in a.
u64 _lzcnt_u64(u64 a)

cvtX_Y

SSE

Single SSE Float
to Normal Float
Conversion 128

Single 128-bit
Int Conversion

128

si32-64,ss/d → ss/d
NOTE: Converts a single
element in b from X to Y.
The remaining bits of theresult are copied from a.
md cvtsi64_sd(md a,i64 b)
double(b[63:0]) |(a[127:64] << 64)

S/D/I32
Conversion
SSE2

128

128

cvt[t]X_Y

cvt[t]X_Y

cvtX_YSSE2

ss/d → si32-64
NOTE: Converts a single
element from X (int) to Y
(float). Result is normal int,
not an SSE register!
The t version performs a
truncation instead ofrounding.

SSE2

si32-128
NOTE: Converts a single
integer from X to Y. Either of
the types must be si128. If
the new type is longer, theinteger is zero extended.

cvtX_Yss→f32,sd→f64
NOTE: Converts a single SSE
float from X (SSE Float type)to Y (normal float type).
f cvtss_f32(m a)mi cvtsi32_si128(i a)i cvtss_si32(m a)_tzcntRound up(ceiling)

castX_Y

SSE2

si128,ps/d
NOTE: Reinterpret casts
from X to Y. No operation is
generated.
md castsi128_pd(mi a)

epi32,ps/d
NOTE: Converts packed
elements from X to Y. If pd isused as source or target
type, then 2 elements areconverted, otherwise 4.
The t version is only
available when casting to int
and performs a truncation
instead of rounding.
md cvtepi32_pd(mi a)

ps/d,ss/d
md ceil_pd(md a)

Round down
(floor)castX_Y

AVX

floor

SSE4.1

pd128↔pd256,
ps128↔ps256,
si128↔si256
NOTE: Reinterpret casts
from X to Y. If cast is from
128 to 256 bit, then theupper bits are undefined! No
operation is generated.

ps/d,ss/d
md floor_pd(md a)

Round

m128d castpd256_pd128(m256d a)

round

SSE4.1

cvt[t]_X2Ypi↔ps,si↔ss
NOTE: Converts X to Y.
Converts between int andfloat. p_ versions convert 2packs from b and fill resultwith upper bits of operanda. s_ versions do the samefor one element in b.
The t version truncatesinstead of rounding and isavailable only whenconverting from float to int.
m cvt_si2ss(m a,i b)

ceil

SSE4.1

128/256bit
Cast 256

Old Float/Int
Conversion 128
SSE

See also: Conversion to int
performs rounding implicitly

128bit Cast

Convert a single element in the lower bytes of an SSE register

Single Float to
Int Conversion

Single Conversion
to Float with Fill≤64
_bit_scan_forward/reverse
(i32)

x86

Count Leading
Zeros ≤64

popcntcvtX_Y

Reinterpet Casts Rounding

Convert all elements in a packed SSE register

Pack With
Saturationph ↔ ps
NOTE: Converts between 4x
16 bit floats and 4x 32 bit
floats (or 8 for 256 bitmode). For the 32 to 16-bit
conversion, a rounding moder must be specified.
m cvtph_ps(mi a)
mi cvtps_ph(m a, i r)

u64 _lrotl(u64 a)i32 _bit_scan_forward(i32 a)

u32-64
NOTE: Counts the number of
1-bits in a.
u32 popcnt_u64(u64 a)

CVT16(u16-64)
NOTE: Rotates bits in a left/right by a number of bits
specified in i. The l version
is for 64-bit ints and the w
version for 16-bit ints.

Count specific ranges of 0 or 1 bits

Count 1-Bits(Popcount) ≤64

Convert Float
16bit ↔ 32bit

sl/rlv

AVX2

epi32-64
NOTE: Shifts elements left/right while shifting in zeros.
Each element in a is shiftedby an amount specified by
the corresponding element
in b.

_blsi

BMI1

sl/rav

epi32-64
NOTE: Shifts elements left/right while shifting in signbits. Each element in a isshifted by an amountspecified by thecorresponding element in b.

u64 _bextr_u64(u64 a,u32 s,u32 l)(a >> s) & ((1 << l)-1)

Mask Up To
Lowest 1-Bit≤64

sl/rl[i]SSE2

mi srai_epi32(mi a,ii32 i)mi sra_epi32(mi a,mi b)

u32-64
NOTE: Extracts l bits from astarting at bit s.

epi8,pd,ps[SSE]
NOTE: Creates a bitmask
from the most significant bitof each element.
i movemask_epi8(mi a)sra[i]

Rotate Left/Right

epi16-64
NOTE: Shifts elements left/right while shifting in zeros.
The i version takes animmediate as count. The
version without i takes thelower 64bit of an SSE
register.

≤64

movemask

Logic Shift
Left/Right

epi16-64
NOTE: Shifts elements rightwhile shifting in sign bits.
The i version takes animmediate as count. The
version without i takes thelower 64bit of an SSE
register.

_bextr

BMI1

Set or reset a range of bits

Zero High Bits_bzhi

Movemask
SSE2

u32-64
NOTE: Deposit contiguous
low bits from a to dst at
the corresponding bit
locations specified by maskm; all other bits in dst are
set to zero.

BMI2

or

Change the position of selected bits, zeroing out
remaining ones

Bit Gather(Extract) ≤64
BMI2

Bit Masking

andnotPacked Conversions

ps/d,ss/d
NOTE: Rounds according to arounding paramater r.
md round_pd(md a,i r)

256bit Cast
256

castX_Y

AVX

ps,pd,si256
NOTE: Reinterpret casts
from X to Y. No operation is
generated.
m256 castpd_ps(m256d a)

u32-64
NOTE: Counts the number oftrailing zeros in a.
u64 _tzcnt_u64(u64 a)

Arithmetics
Basic Arithmetics
Register I/O Loading data into an SSE register or storing data from an SSE register
Load

Overview
FencesLoading data into an SSE register

Set Register

Inserting data into an register without loading from memory

Set Reversed

Set

SEQ!
SSE2
AVX
epi8-64x,ps[SSE]/d,m128/m128d/i[AVX]NOTE: Sets and returns an SSE
register with input values. The
order in the register isreversed, i.e. the first input
gets stored in the lowest bits.
For epi64, use the epi64x
suffix.

SEQ!
SSE2
AVX

setr

Insertset

SSE4.1

epi8-64x,ps[SSE]/d,ss/d,
m128/m128d/i[AVX]NOTE: Sets and returns an
SSE register with input
values. E.g., epi8 version
takes 16 input parameters.
The first input gets stored in
the highest bits. For epi64,
use the epi64x suffix.

mi setr_epi32(i a,i b,i c,i d)

SSE

Replicate128

insertepi16[SSE2],
epi8-64,ps
NOTE: Inserts an element i
at a position p into a.
mi insert_epi16(mi a,i i,ii p)
dst[127:0] := a[127:0]
sel := p[2:0]*16
dst[sel+15:sel]:=i[15:0]

SEQ!
SSE2

set1

epi8-64x,ps[SSE]/d
NOTE: Broadcasts one input
element into all slots of an
SSE register.
mi set1_epi32(i a)PrefetchsfenceSSE

NOTE: Fetch the line of datafrom memory that contains
address ptr to a location in
the cache heirarchy specified
by the locality hint i.
v prefetch(c* ptr,i i)

Load Fence

Cache Line
Flush
SSE2

lfenceStream Load
SSE2

Load Aligned

stream_load

pd,ps,si128
NOTE: Loads 128 bit frommemory into register.
Memory address must bealigned!
md load_pd(d* ptr)

mi lddqu_si128(mi* ptr)

Load
Unaligned
loadu

SSE2

loadr

pd,ps
NOTE: Loads 128 bit frommemory into register. The
elements are loaded inreversed order. Memory
must be aligned!

Load
Broadcast
High/Low 128 SEQ! Load 128
loadh/l

SSE2

pd,pi
NOTE: Loads a value frommemory into the high/low
half of a register and fills theother half from a.
md loadl_pd(md a,d* ptr)
dst[63:0] :=*(ptr)[63:0]
dst[127:64] := a[127:64]

SSE2

load1

Memory Fence(Load & Store)
SSE2

AVX

undefined

ps/d,si128-256
NOTE: Returns an SSE
register with undefinedcontents.
mi undefined_si128()

mfenceNOTE: Guarantees thatevery memory access thatprecedes, in program order,
the memory fence
instruction is globally visible
before any memory
instruction which follows thefence in program order.
v mfence()mi maskload_epi64(i64* ptr,mi mask)
dst[MAX:128] := 0
FOR j := 0 to 1
i := j*64
IF mask[i+63]
dst[i+63:i]:= *(ptr+i)
ELSE
dst[i+63:i]:= 0pd,psNOTE: Loads a float frommemory into all slots of the
128-bit register.
For pd, there is also theoperation loaddup in SSE3
which may perform fasterthan load1.
md load1_pd(d* ptr)

Gather

Mask Gather

broadcast

AVX2 i32/i64gather

AVX2 mask_i32/i64gather

ss/d,ps/d
NOTE: Broadcasts one input(ss/d) element or 128bits(ps/d) from memory into allslots of an SSE register. All
suffixes but ss are only
available in 256 bit mode!

epi32-64,ps/d
NOTE: Gather elements frommemory using 32-bit/64-bit
indices. The elements areloaded from addresses
starting at ptr and offset byeach 32-bit/64-bit element ina (each index is scaled by thefactor in s). Gatheredelements are merged into dst.
s should be 1, 2, 4 or 8. The
number of gathered elements
is limited by the minimum of
the type to load and the typeused for the offset.

epi32-64,ps/d
NOTE: Same as gather but
256
takes an additional mask andsrc register. Each element isonly gathered if the highest
corresponding bit in the mask
is set. Otherwise it is copiedfrom src.

m broadcast_ss(f* a)128bit Pseudo
Broadcast
SEQ! Gather
256
Load 128 AVX loadu2

Load Single
128

load

SSE2

Broadcast
Load
AVX

loaddup

NOTE: Loads 128 bit or less(for si16-64 versions) frommemory into the low-bits ofa register.

NOTE: Loads a 64-bit float
from memory into all slots of
the 128-bit register.

md loadu_pd(d* ptr)

md load_sd(d* ptr)

md loaddup_pd(d* ptr)

Store

v lfence()

AVX
AVX2
ps/d,epi32-64[AVX2]
NOTE: Loads from memory
if the highest bit for eachelement is set in the mask.
Otherwise 0 is used. ptr
must be aligned!

maskload

ss,sd,epi64
NOTE: Loads a single
element from memory andzeros remaining bytes. For
epi64, the command isloadl_epi64!

pd,ps,si16-si128

Mask Load

Get Undefined
Register

Loading data from a memory address which does
not have to be aligned to a specific boundary

Fast Load
Unaligned
si128
NOTE: Loads 128bit integer
data into SSE register. Is
faster than loadu if value
crosses cache line boundary.
Should be preferred overloadu.

128

m loadr_ps(f* ptr)
dst[31:0]:=*(ptr)[127:96]
dst[63:32]:=*(ptr)[95:64]
dst[95:64]:=*(ptr)[63:32]
dst[127:96]:=*(ptr)[31:0]

Unaligned Load
lddqu

Load Reversed
SEQ!
SSE2

load

SSE2

si128,si256[AVX]NOTE: Loads 128 bit frommemory into register.
Memory address must bealigned! Memory is fetchedat once from an USWC
device without going
through the cache hierachy.
mi stream_load_si128(mi* ptr)

SSE3

NOTE: Guarantees that every
load instruction thatprecedes, in program order,
is globally visible before anyload instruction which follows
the fence in program order.

Loading data from a memory address which must be
16-byte aligned (or 32-byte for 256bit instructions)clflushNOTE: Flushes cache linethat contains p from allcache levelsv clflush(v* ptr)-

Aligned Loadprefetch

NOTE: Guarantees that every
store instruction thatprecedes, in program order, is
globally visible before any
store instruction which follows
the fence in program order.
v sfence()

SSE2

mi set_epi32(i a,i b,i c,i d)

Introduction

Misc I/O

Store Fence

SSE3

pd

m128,m128d,m128i
NOTE: Loads two 128bit
elements from two memory
locations.
m loadu2_m128(f* p1,f* p2)
dst[127:0] = *p2;
dst[255:128] = *p1;

mi i64gather_epi32(i* ptr,mi a,i s)
FOR j := 0 to 1;
i := j*32
m := j*64
dst[i+31:i] :=*(ptr + a[m+63:m]*s])dst[MAX:64] := 0

mi mask_i64gather_epi32(mi src,i* ptr,mi a,
mi mask,i32 s)
FOR j := 0 to 1;
i := j*32
m := j*64
IF mask[i+31]
dst[i+31:i]:=*(ptr+a[i+63:i]*s)mask[i+31] := 0
ELSE
dst[i+31:i] :=src[i+31:i]mask[MAX:64] := 0
dst[MAX:64] := 0

AlignedStream Store
streamSSE
SSE2

NOTE: Stores the elementsfrom the register to memory
in reverse order. Memory
must be aligned!

Sequence Indicator: If thisindicator is present, it meansthat the intrinsic will
generate a sequence ofassembly instructions insteadof only one. Thus, it may not
be as efficient as anticipated.

256 : Only available for 256bit SSE registers (always use _mm256_ prefix)
128 : Only available for 128bit SSE registers (always use _mm_ prefix)≤64 : Operation does not operate on SSE registers but usual 64bit registers (always use _mm_ prefix)

Instruction Set: Specifies the
instruction set which isnecessary for this operation.
If more than one instruction
set is given here, thendifferent flavors of thisoperation require different
instruction sets.

SEQ!
SSE2

128

cmp[n]Z

ps/d,ss/d,
si128[SSE4.1]
NOTE: Z can be one of:ge/le/lt/gt/eq
Returns a single int that iseither 1 or 0. The n version isa not version, e.g., neq
computes not equal.
md cmpeq_pd(md a,md b)

Signature and Pseudocode: Shows one possible signature of the intrinsic in order to depict the parameter types and the return type. Note that only
one flavor and data type suffix is shown; the signature has to be adjusted for other suffixes and falvors. The data types are displayed in shortened
form. Consult the data types table for more information.
In addition to the signature, the pseudocode for some intrinsics is shown here. Note that the special variable dst depicts the destination register ofthe method which will be returned by the intrinsic.

Data Type Suffixes

Data Types

Each intrinsic is only available on machines which support thecorresponding instruction set. This list depicts the instruction sets
and the first Intel and AMD CPUs that supported them.

Most intrinsics are available for various suffixes which depict different
data types. The table depicts the suffixes used and the corresponding
SSE register types (see Data Types for descriptions).

The following data types are used in the signatures of the intrinsics.
Note that most types depend on the used type suffix and only one
example suffix is shown in the signature.

I.Set

Suffix
ph
ps/d
epiX
epuX

Intel (Year)

AMD (Year)

x86
all
all
SSE Pentium III 99 K7 Palomino 01
SSE2 Pentium 4 01
K8 03
SSE3
Prescott 04
K9 05
SSSE3 Woodcrest 06 Bulldozer 11
SSE4.1 Penryn 07
Bulldozer 11
SSE4.2 Nehalem 08
Bulldozer 11
AVX Sandy Bridge 11 Bulldozer 11
AVX2
Haswell 13
FMA
Haswell 13
Bulldozer 11
AES
Westmere 10 Bulldozer 11
CLMUL Westmere 10 Bulldozer 11
CVT16 Ivy Bridge 12
Bulldozer 11
TSX
Haswell 13
POPCNT Nehalem 08
K10 07LZCNT
Haswell 13
K10 07
BMI1 Sandy Bridge 11 Bulldozer 11
BMI2 Haswell?? 14-

Description
x86 Base Instructions

Streaming SIMD
Extensions

SSE2

storehpd
NOTE: Stores the high 64bits
into memory.
v storeh_pd(v* ptr,m a)v storeu_pd(v* ptr,m a)

Type
mi
m/md
mi
mi

Description
Packed half float (16 bit float)
Packed single float / packed double float
Packed X bit signed integer
Packed X bit unsigned integer
Single X bit signed integer. If there is a si128
version, the same function for 256 bits is usuallymisuffixed with si256.
Single X bit unsigned integer in SSE registermiSingle X bit unsigned integer (not in SSE register)Single single float/double float, remaining bits
copied. Operations involving these types often
have different signatures: An extra input registerm/md is used and all bits which are not used by thesingle element are copied from this register. The
signatures are not depicted here; see manual for
exact signatures.

siX

Advanced Vector
Extensions
Fused Multiply and Add
Advanced Encryption Standard
Carryless Multiplication
16-bit Floats
Transactional Sync. Extensions

suX
uX

ss/d

Bit Manipulation
Instructions

Broadcast
Store 128
SEQ!

Aligned Store
SSE
SSE2
si128,pd,ps[SSE],
si256[AVX]

SSE
SSE2

store

store1

pd,ps[SSE]
NOTE: Stores a float to 128bits of memory replicating it
two (pd) or four (ps) times.
Memory location must bealigned!

NOTE: Stores 128-bits intomemory. Memory locationmust be aligned!
v store_pd(d* ptr,md a)v store1_pd(d* ptr,md a)

Mix Registers

Extract

Move Elementwith Fill 128

Masked StoreAVX
AVX2 maskstore
ps/d,epi32-64[AVX2]
NOTE: Stores bytes from a
into memory at p if thecorresponding byte in themask m has its highest bit
set. Memory must bealigned!

128
SSE4.1extract

epi16[SSE2],
epi8-64,ps
NOTE: Extracts one element
and returns it as a normal int(no SSE register!)i extract_epi16(mi a,ii i)(a>>(i[2:0]*16))[15:0]v maskstore_ps(f* p,mi m,m a)

SSE
SSE2

move

ss[SSE],sd
NOTE: Moves the lowest
element from first input andfills remaining elementsfrom second input
m move_ss(m a,m b)a[31:0] | b[127:32]

MoveHigh↔Low 128
SSE

movelh/hl

ps
NOTE: The lh version
moves lower half of b into
upper half of result. Rest is
filled from a. The hl version
moves upper half to lower
half.

aesimcSingle Element
Store 128

Masked Store

SSE
SSE2
ss[SSE],sd,epi64

SSE2

NOTE: Stores the low element
into memory. The l version
must be used for epi64 andcan be used for pd.

NOTE: Stores bytes intomemory if the corresponding
byte in mask has its highest
bit set.
v maskmoveu_si128(mi a,mi mask,c* ptr)

store[l]128bit Pseudo
SEQ! Scatter
256
storeu2maskmoveu

AVX

si128

m128,m128d,m128i
NOTE: Stores two 128bit
elements into two memory
locations.
v storeu2_m128(f* p,f* q,m a)*p = dst[127:0];*q = dst[255:128];

AES Encrypt

AES Decrypt

128
AES

aesenc[last]

128
AES

Cyclic Redundancy
Check (CRC32) ≤64

aesdec[last] SSE4.2

si128
NOTE: Perform one round of
an AES encryption flow on thestate in a using the roundkey. The last version
performs the last round.

si128
NOTE: Perform one round of
an AES decryption flow on thestate in a using the roundkey. The last version
performs the last round.

mi aesenc_si128(mi a,mi key)

mi aesdec_si128(mi a,mi key)crc32

u8-u64
NOTE: Starting with the initialvalue in crc, accumulates a
CRC32 value for unsigned Xbit integer v, and stores theresult in dst.
u crc32_u32(u crc,u v)

Miscellaneous
MonitorMemory

Pause
SSE2

pause

NOTE: Provide a hint to theprocessor that the code
sequence is a spin-wait loop.
This can help improve theperformance and power
consumption of spin-waitloops.
v pause()SSE3

monitorNOTE: Arm address
monitoring hardware using
the address specified in p. A
store to an address within thespecified address range
triggers the monitoring
hardware. Specify optional
extensions in e, and optional
hints in h.
v monitor(v* ptr,u e,u h)v
X*256bit Insert
AVX
AVX2

extractf128

si256,ps/d
NOTE: Extracts 128bit andreturns it as a 128bit SSE
register. For AVX2, there is
only si256 and theoperation is named
extracti128.
m128 extractf128_ps(m256 a,ii i)(a >> (i * 128))[128:0]

Interleave(Unpack)
SSE2

unpackhi/lo

epi8-64,ps[SSE],pd
NOTE: Interleaves elementsfrom the high/low half of
two input registers into atarget register.
mi unpackhi_epi32(mi a,mi b)
dst[31:0] := a[95:64]
dst[63:32] := b[95:64]
dst[95:64] := a[127:96]
dst[127:96]:= b[127:96]

insertf128

Dual Register
Float Shuffle

Blend
SSE4.1
AVX2

256

SSSE3

SSE
SSE2

blend[v]epi8-16,
epi32[AVX2],ps/d
NOTE: blendv uses 128bit
mask, blend uses
immediatemi blend_epi16(mi a,mi b,ii imm)
FOR j := 0 to 7
i := j*16
IF imm[j]dst[i+15:i] := b[i+15:i]
ELSE
dst[i+15:i] := a[i+15:i]

shuffleps[SSE],pd
NOTE: Shuffles floats fromtwo registers. The lower partof the result receives values
from the first register. The
upper part receives values
from the second register.
Shuffle mask is animmediate!
md shuffle_pd(md a,md b,ii i)
dst[63:0]:= (i[0] == 0) ?
a[63:0] : a[127:64]
dst[127:64]:= (i[1] == 0) ?
b[63:0] : b[127:64]

alignrepi8
mi alignr_epi8(mi a,mi b,i c)((a << 128) | b) >> c*8

128-bit Dual
Register Shuffle
AVX
AVX2

256

permute2f128

ps/d,si256
NOTE: Takes 2 registers andshuffles 128 bit chunks to atarget register. Each chunk
can also be cleared by a bitin the mask. For AVX2, there
is only the si256 version
which is renamed topermute2x128.
md permute2f128_pd(md a,md b,ii i)
S(s1, s2, control){CASE(control[1:0])
0: tmp[127:0]:=s1[127:0]
1: tmp[127:0]:=s1[255:128]
2: tmp[127:0]:=s2[127:0]
3: tmp[127:0]:=s2[255:128]
IF control[3]tmp[127:0] := 0
RETURN tmp[127:0]}
dst[127:0] :=S(a,b,i[3:0])
dst[255:128]:=S(a,b,i[7:4])
dst[MAX:256]:=0

Monitor Wait
SSE3

mwait

NOTE: Hint to the processor
that it can enter animplementation-dependentoptimized state while waiting
for an event or store
operation to the address
range specified by MONITOR.
v mwait(u ext,u hints)

Get MXCSR
RegisterSSE

getcsr

NOTE: Get the content of the
MXCSR register.
u getcsr()

Set MXCSR
RegisterSSE

setcsr

NOTE: Set the MXCSR registerwith a 32bit int.
v setcsr(u a)AbortTransaction
TSX_xabort

NOTE: Force an RTM abort. The
EAX register is updated toreflect an XABORT instruction
caused the abort, and the imm
parameter will be provided inbits [31:24] of EAX. Following
an RTM abort, the logicalprocessor resumes execution
at the fallback addresscomputed through theoutermost XBEGIN instruction.
v _xabort(ii imm)

Transactional
MemoryCommitTransaction
TSX

_xend

NOTE: Specify the end of an
RTM code region. If thiscorresponds to the outermost
scope, the logical processor
will attempt to commit thelogical processor stateatomically. If the commit fails,
the logical processor will
perform an RTM abort.
v _xend()Begin
Transaction
TSX_xbegin

NOTE: Specify the start of an
RTM code region. If the logicalprocessor was not already intransactional execution, then it
transitions into transactional
execution. On an RTM abort,the logical processor discards
all architectural register andmemory updates performed
during the RTM execution,
restores architectural state,and starts execution beginningat the fallback addresscomputed from the outermost
XBEGIN instruction.
u _xbegin()setzerops[SSE]/d,si128
NOTE: Returns a registerwith all bits zeroed.
mi setzero_si128()

Zero High
128
SSE2

move
epi64

NOTE: Moves lower half of
input into result and zeroremaining bytes.
mi move_epi64(mi a)a[63:0]

SSE2

AVX

zeroall

NOTE: Zeros all SSE/AVX
registers.
v zeroall()Zero High All
Registers 256
AVX

zeroupper

NOTE: Zeros all bits in[MAX:256] of all SSE/AVX
registers.
v zeroupper()High / Low
16bit Shuffle

shuffle

SSE2

epi32
mi shuffle_epi32(mi a,ii i)S(s, mask){
CASE(mask[1:0])
0: r := s[31:0]
1: r := s[63:32]
2: r := s[95:64]
3: r := s[127:96]
RETURN r[31:0]}
dst[31:0]:=S(a,i[1:0])
dst[63:32]:=S(a,i[3:2])
dst[95:64]:=S(a,i[5:4])
dst[127:96]:=S(a,i[7:6])

shufflehi/lo

epi16
NOTE: Shuffles the high/low
half of the register using an
immediate control mask.
Rest of the register is copiedfrom input.
mi shufflehi_epi16(mi a,ii i)
dst[63:0] := a[63:0]
dst[79:64] :=(a >> (i[1:0]*16))[79:64]
dst[95:80] :=(a >> (i[3:2]*16))[79:64]
dst[111:96] :=(a >> (i[5:4]*16))[79:64]
dst[127:112] :=(a >> i[7:6]*16))[79:64]

Byte Shuffle
SSSE3

shuffleepi8
NOTE: Shuffle packed 8-bit
integers in a according toshuffle control mask in thecorresponding 8-bit elementof b, and store the results indst.
mi shuffle_epi8(mi a,mi b)
FOR j := 0 to 15
i := j*8
IF b[i+7] == 1
dst[i+7:i] := 0
ELSEk := b[i+3:i]*8
dst[i+7:i]:= a[k+7:k]

AVX

4x64bitShufflepermute[var]8x32bitShuffleps/d
NOTE: 128-bit version is thesame as int shuffle for floats.
256-bit version performs thesame operation on two 128bit lanes. The normal version
uses an immediate and thevar version a register b (thelowest bits in each element
in b are used for the mask ofthat element in a).

epi64,pd
NOTE: Same as float shuffle
but no [var] version isavailable. In addition, theshuffle is performed over thefull 256 bit instead of twolanes of 128 bit.

epi32,ps
NOTE: Same as 4x64 bit
shuffle but with 8x32bit andonly a [var] version taking a
register instead of animmediate is available.

m permutevar_ps(m a,mi b)

md permute4x64_pd(md a,ii i)m permutevar8x32_ps(m a,mi b)

moveduppd
NOTE: Duplicates the lower
half of a.
md movedup_pd(md a)a[0:63]|(a[63:0]<<64)32-bit Broadcast
High/Low
SSE3

permute4x64

Replicating one element in a register
to fill the entire register64-bitBroadcast
SSE3

AVX2

movel/hduppsNOTE: Duplicates 32bits into
the lower 64bits of theresult. l version duplicatesbits [31:0], h version
duplicates bits [63,32].
m moveldup_ps(m a)

256
AVX2

epi16
NOTE: Treat the 16-bitwords in registers A and B as
signed 15-bit fixed-point
numbers between −1 and 1(e.g. 0x4000 is treated as 0.5
and 0xa000 as −0.75), andmultiply them together.
mi mulhrs_epi16(mi a,mi b)

Add

Add with
Saturation

Alternating Add
and Subtract

SSSE3

hadds

hadd

SSSE3

SSE
SSE2
epi8-64,ps[SSE]/d,
ss[SSE]/dmi add_epi16(mi a,mi b)

SSE
SSE2
epi8-16,epu8-16
mi adds_epi16(mi a,mi b)

Subtract

Subtract with
Saturation

add

epi16
NOTE: Adds adjacent pairs ofelements with saturation
mi hadds_epi16(mi a,mi b)

epi16-32,ps/d
NOTE: Adds adjacent pairs ofelements
mi hadd_epi16(mi a,mi b)

Horizontal Subtract
with Saturation

Horizontal
Subtract

SSSE3

hsubs

hsub

SSSE3

epi16
NOTE: Subtracts adjacent pairsof elements with saturation
mi hsubs_epi16(mi a,mi b)

adds

SSE
SSE2
epi8-64,ps[SSE]/d,
ss[SSE]/dmi sub_epi16(mi a,mi b)

sub

epi16-32,ps/d
NOTE: Subtracts adjacentpairs of elements
mi hsub_epi16(mi a,mi b)

Approx.
Reciprocal

Div
SSE2

div

ps/d
m addsub_ps(m a,m b)
FOR j := 0 to 3
i := j*32
IF (j is even)dst[i+31:i] :=a[i+31:i] - b[i+31:i]
ELSE
dst[i+31:i] :=a[i+31:i] + b[i+31:i]

subs

SSE2

epi8-16,epu8-16
mi subs_epi16(mi a,mi b)

Approx.
Reciprocal Sqrt

rcp

SSE

ps/d,ss/d
m div_ps(m a,m b)

Sign
Modification

Square Root
SSE
SSE2

rsqrt

SSE

ps,ss
m rcp_ps(m a)ps,ssAbsolute

sqrt

ps/d,ss/dm sqrt_ps(m a)NOTE: Approximates 1.0/sqrt(x)SSSE3

broadcastXepi8-64,ps/d,si256
NOTE: Broadcasts thelowest element into all slotsof the result register. The
si256 version broadcasts one
128bit element! The letter X
must be the following:
epi8: b, epi16: w, epi32: d,
epi64:q, ps: s, pd: d,
si256: si128
mi broadcastb_epi8(mi a)abs

epi8-32
mi abs_epi16(mi a)m rsqrt_ps(m a)Conditional
Negate or Zero

Min/Max/Avg
Horizontal
Min
128
SSE4.1

addsub

SSE3

Min

minposMax

SSE2
SSE4.1
SSE:ps SSE2:epu8,
epi16,pd
SSE4.1:
epi8-32,epu8-32

SSE2
SSE4.1
SSE:ps SSE2:epu8,
epi16,pd
SSE4.1:
epi8-32,epu8-32

mi min_epu16(mi a,mi b)

mi max_epu16(mi a,mi b)

min

epu16
NOTE: Computes horizontal
min of one input vector of
16bit uints. The min is stored in
the lower 16 bits and its index
is stored in the following 3 bits
mi minpos_epu16(mi a)

Average

max

SSSE3

avg

SSE2

sign

epi8-32
NOTE: For each element in aand b, set result element toa if b is positive, set result
element to -a if b isnegative or set result
element to 0 if b is 0.

epu8-16
mi avg_epu16(mi a,mi b)

mi sign_epi16(mi a,mi b)

Perform more than one operation at once

Compwosite Int Arithmetics
Multiply andHorizontal Add

dp

SSSE3

ps/d
NOTE: Computes the dot
product of two vectors. A
mask is used to state which
components are to be
multiplied and stored.

Multiply and Sum of Absolute Sum of Absolute
Horizontal Add
Differences
Differences 2

maddubsm dp_ps(m a,m b,ii imm)
FOR j := 0 to 3
IF imm[4+j]tmp[i+31:i] :=a[i+31:i] * b[i+31:i]
ELSE
tmp[i+31:i] := 0

madd

SSE3

epi16
NOTE: Adds vertical 8 bit ints
producing a 16 bit int andadds horizontal pairs withsaturation producing 8x16 bit
ints. The first input is treatedas unsigned and the second as
signed. Results andintermediaries are signed.
*

SSE4.1

epu8
NOTE: Compute the absolutedifferences of packed
unsigned 8-bit integers in aand b, then horizontally sumeach consecutive 8
differences to produce two
unsigned 16-bit integers, andpack these unsigned 16-bit
integers in the low 16 bits of
64-bit elements in dst.

NOTE: Multiply 16-bit ints
producing a 32-bit int andadd horizontal pairs withsaturation producing
4x32-bit ints
+S
*

sad

SSE2

epi16

+S

+S
+S
+S

*

sum[31:0] :=tmp[127:96] + tmp[95:64]+ tmp[63:32]+ tmp[31:0]*

ABS(a-b)+S0+

mi maddubs_epi16(mi a,mi b)

FOR j := 0 to 3
IF imm[j]dst[i+31:i] :=sum[31:0]
ELSE
dst[i+31:i] := 00

mi madd_epi16(mi a,mi b)+

mi sad_epu8(mi a,mi b)

sadbw

epu8
NOTE: Compute the sum ofabsolute differences (SADs) ofquadruplets of unsigned 8-bit
integers in a compared to thosein b, and store the 16-bit results.
Eight SADs are performed using
one quadruplet from b and eight
quadruplets from a. One
quadruplet is selected from b
starting at on the offset specified
in imm. Eight quadruplets areformed from sequential 8-bit
integers selected from a startingat the offset specified in imm.
mi sadbw_epu8(mi a,mi b,ii imm)
a_offset := imm[2]*32
b_offset := imm[1:0]*32
FOR j := 0 to 7
i := j*8
k := a_offset+il := b_offset
dst[i+15:i] :=ABS(a[k+7:k]-b[l+7:l])+ABS(a[k+15:k+8]-b[l+15:l+8])+ABS(a[k+23:k+16]-b[l+23:l+16])+
ABS(a[k+31:k+24]-b[l+31:l+24])

Fused Multiply and Add

256

permutevar8x32

FM-AddFMA

FM-Subf[n]madd

FMA

FM-AddSub

f[n]madd

ps/d,ss/d
NOTE: Computes (a*b)+c
for each element. The n
version computes -(a*b)+c.

ps/d,ss/d
NOTE: Computes (a*b)-c
for each element. The n
version computes -(a*b)-c.

m fmadd_ps(m a,m b,m c)

m fmsub_ps(m a,m b,m c)

FMA

FM-SubAdd

fmaddsubFMA

ps/d,ss/d
NOTE: Computes (a*b)+c
for elements with even indexand (a*b)-c for elementswith odd index.

fmsubadd

ps/d,ss/d
NOTE: Computes (a*b)-c
for elements with even indexand (a*b)+c for elementswith odd index.
m fmsubadd_ps(m a,m b,m c)

Byte Movement
Byteshift
left/right

Broadcast
AVX2mulhrsSSSE3

Float Shuffle

BroadcastZero All
Registers 256

Change the byte order using a control mask

32-bit Int
ShuffleConcatenate andByteshift (Align)si256,ps/d
NOTE: Inserts 128bit at a
position specified by i. For
AVX2, there is only si256
and the operation is named
inserti128.
m insertf128_ps(m a,m b,ii i)
dst[255:0] := a[255:0]
sel := i*128
dst[sel+15:sel]:=b[127:0]

m movehl_ps(m a,m b)

AVX
AVX2

Special Algorithms

si128
NOTE: Performs the inversemix columns transformationon the input.
mi aesimc_si128(mi a)md

Byte ShufflingMix the contents of two registers

SSE
SSE2

AES

m

mulhi

SSE2

epi16,epu16
NOTE: Multiplies verticallyand writes the high 16bits
into the result.
mi mulhi_epi16(mi a,mi b)

Horizontal
Add

Horizontal Add
with Saturation

SSE4.1

Extraction

Specialssi128
NOTE: Assist in expanding the
AES cipher key by computing
steps towards generating around key for encryption cipher
using data from a and an 8-bit
round constant specified in i.
mi aeskeygenassist_si128(mi a,ii i)

mi

mullo

Addition / Subtraction

Conditional
Dot ProductZero Registeraeskeygenassist

f
d

m128,
m,
AVX sometimes uses this suffix for 128bit float/m128d,
double/int operations.
m128i md,miByte Zeroing

AES

ii

Description
Signed 32 bit integer (int)
Signed X bit integer (intX_t)
Unsigned X bit integer (uintX_t)
Immediate signed 32 bit integer: The value used forparameters of this type must be a compile time constant32-bit float (float)64-bit float (double)
Integer SSE register, i.e., __m128i or __m256i,
depending on the bitwidth used.
32-bit Float SSE register, i.e., __m128 or __m256,
depending on the bitwidth used.
64-bit Float (double) SSE register, i.e., __m128d or__m256d, depending on the bitwidth used.
void
Pointer to X (X*)

Change the order of bytes in a register, duplicating or zeroingv store_sd(d* ptr,md a)

AES KeyGen
AES Inverse Mix
Assist 128
Columns 128

SuffixiiXuX

Mul High withRound & Scale

Mul High

Div/Sqrt/Reciprocal

Instruction Sets

Byte Manipulation bytes selectively or mixing the bytes of two registers

Storing data to a memory address which does
not have to be aligned to a specific boundary

128

List of available data type suffixes: Consult the suffix table for further information about the various possible suffixes. The suffix chosen
determines the data type on which the intrinsic operates. It must be added as a suffix to the intrinsic name separated by an underscore, so a
possible name for the data type pd in this example would be _mm_cmpeq_pd. A suffix is followed by an instruction set in brackets, then this
instruction set is required for the suffix. All suffixes without an explicit instruction set are available in the instruction set specified at the left.
If no type suffixes are shown, then the method is type independent and must be used without a suffix. If the suffixes are in parenthesis, the suffixes
must not be appended and are encoded into the name of the intrinsic in another way (see notes for further information).

Notes: Explains the semanticsof the intrinsic, the various
flavors, and other important
information.

256bit Extract

Store High

Name(s) of the intrinsic: The names of the various flavors of the intrinsic. To assemble the final name to be used for an intrinsic, one must add aprefix and a suffix. The suffix determines the data type (see next field). Concerning the prefix, all intrinsics, except the ones which are prefixed witha green underscore _, need to be prefixed with _mm_ for 128bit versions or _mm256_ for 256bit versions. Blue letters in brackets like [n]indicate that adding this letter leads to another flavor of the function. Blue letters separated with a slash like l/r indicate that either letter can beused and leads to a different flavor. The different flavors are explained in the notes section. A red letter like Z indicates that various different
strings can be inserted here which are stated in the notes section.

SSE2
SSE4.1
epi16,epi32[SSE4.1]
NOTE: Multiplies verticallyand writes the low 16/32
bits into the result.
mi mullo_epi16(mi a,mi b)...

storeuAvailable Bitwidth: If no bitwidth is specified, the operation is available for 128bit and 256bit SSE registers. Use the _mm_ prefix for the 128bit andthe _mm256_ prefix for the 256bit flavors. Otherwise, the following restrictions apply:

SSE
SSE2
epi32[SSE4.1],epu32,
ps/d,ss/d
NOTE: epi32 and epu32
version multiplies only 2 ints
instead of 4!
mi mul_epi32(mi a,mi b)

mul

si128
NOTE: Perform a carry-lessmultiplication of two 64-bit
integers, selected from aand b according to imm, andstore the results in dst(result is a 127 bit int).
mi clmulepi64_si128(mi a,mi b,ii imm)

...

SSE
SSE2
si16-128,pd,ps[SSE],
si256[AVX]NOTE: Stores 128 bits (orless for the si16-64 versions)
into memory.

Name: Human readable
name of the operation

Mul Low...

v storer_pd(d* ptr,md a)

Unaligned Store
UnalignedStore

storerpd,ps[SSE]

Each family of intrinsics is depicted by a box as described below. It was tried to group the intrinsics meaningfully. Most information is taken from the Intel Intrinsics Guide (http://software.intel.com/en-us/articles/intel-intrinsics-guide). Let me know(finis@in.tum.de) if you find any wrong or unclear content.
When not stated otherwise, it can be assumed that each vector intrinsic performs its operation vertically on all elements which are packed into the input SSE registers. E.g., the add instruction has no description. Thus, it can be assumed that it performs
a vertical add of the elements of the two input registers, i.e., the first element from register a is added to the first element in register b, the second is added to the second, and so on. In contrast, a horizontal add would add the first element of a to thesecond element of a, the third to the fourth, and so on.
To use the intrinsics, included the <x86intrin.h> header and make sure that you set the target architecture to one that supports the intrinsics you want to use (using the -march=X compiler flag).

clmulepi64

Mul

...

SSE
SSE2
si32-128,pd,ps[SSE],
si256[AVX]NOTE: Stores 128-bits (or 3264) for si32-64 integer ainto memory using a nontemporal hint to minimize
cache pollution. Memory
location must be aligned!
v stream_si32(i* p,i a)v stream_si128(mi* p,mi a)

128
CLMUL

Dot Product

Storing data to a memory address which must be 16byte aligned (or 32-byte for 256bit instructions)

Aligned Reverse
Store 128
SEQ!

Carryless Mul

This cheat sheet displays most x86 intrinsics supported by Intel processors. The following intrinsics were omitted:·
obsolete or discontinued instruction sets like MMX and 3DNow!
·
AVX-512, as it will not be available for some time and would blow up the space needed due to the vast amount of new instructions·
Intrinsics not supported by Intel but only AMD like parts of the XOP instruction set (maybe they will be added in the future).
·
Intrinsics that are only useful for operating systems like the _xsave intrinsic to save the CPU state·
The RdRand intrinsics, as it is unclear whether they provide real random numbers without enabling kleptographic loopholes

Float Compare

Multiplication

Composite Arithmetics

Storing data from an SSE register into memory or registers

Aligned Store

Version 2.1f

SSE2[b]sl/rli

si128,epi128[256]NOTE: Shift input register
left/right by i bytes while
shifting in zeros. There is nodifference between the band the non-b version.
mi bsrli_si128(mi a,ii i)

Byte Swap≤64

x86_bswap[64](i32,i64)
NOTE: Swaps the bytes inthe 32-bit int or 64-bit int.
i64 _bswap64(i64 a)Comparisons
Float Compare
Float
Compare 128
SSE2

cmp[n]Z

ps/d,ss/d
NOTE: Z can be one of:ge/le/lt/gt/eq
The n version is a notversion, e.g., neq computes
not equal. Elements thatcompare true receive 1s inall bits, otherwise 0s.
md cmpeq_pd(md a,md b)

Bit Compare

Int CompareCompare Not
NaN 128
SSE2

cmp[un]ord

ps/d,ss/d
NOTE: For each element paircmpord sets the result bits
to 1 if both elements are not
NaN, otherwise 0.
cmpunord sets bits if at
least one is NaN.
md cmpord_pd(md a,md b)

Test Mix Ones
Zeros

SSE4.1AVX
si128[SSE4.1],
si256,ps/d
NOTE: Compute the bitwise
AND of 128 bits in a and b, andset ZF to 1 if the result is zero,otherwise set ZF to 0.
Compute the bitwise AND NOTof a and b, and set CF to 1 if
the result is zero, otherwise
set CF to 0. The c version
returns CF and the z version
ZF. For 128 bit, there is also
test_all_zeros which does
the same as testz_si128.

SSE4.1
test_ncz
AVX
si128[SSE4.1],
si256,ps/d
NOTE: Compute the bitwise
AND of 128 bits in a and b,
and set ZF to 1 if the result iszero, otherwise set ZF to 0.
Compute the bitwise AND
NOT of a and b, and set CF to
1 if the result is zero,otherwise set CF to 0. Return!CF && !ZF. For 128 bit,there is also the operation
test_mix_ones_zeros which
does the same.
i test_mix_ones_zeros(mi a,mi b)
ZF := ((a & b) == 0)
CF := ((a & !b) == 0)
RETURN !CF && !ZF;

i testc_si128(mi a,mi b)
ZF := ((a & b) == 0)
CF := ((a & !b) == 0)
RETURN CF;

cmp

AVX

ps/d,ss/d
NOTE: Compares packed or
single elements based on
imm. Possible values are 0-31
(check documentation).
Elements that compare truereceive 1s in all bits,
otherwise 0s.
md cmp_pd(md a,md b,ii imm)

Perform a bitwise operation and check whether all bits
are 0s afterwards

Test And Not/And
testc/zCompareString Compare String Compare
Mask
Index

Test All Ones
SEQ!
128
SSE4.1 test_all_ones
NOTE: Returns true iff all bits
in a are set. Needs two
instructions and may beslower than native
implementations.
i test_all_ones(mi a)(~a) == 0CompareSingle Float
SSE2

Int Compare[u]comiZ

SSE2

ss/d
NOTE: Z can be one of:
eq/ge/gt/le/lt/neq
Returns a single int that iseither 1 or 0. The u version
does not signal an exception
for QNaNs and is notavailable for 256 bits!
i comieq_sd(mi a,mi b)

cmpZ

epi8-32,epi64[SSE4.1]
NOTE: Z can be one of:lt/gt/eq.Elements that
equal receive 1s in all bits,
otherwise 0s.
mi cmpeq_epi8(mi a,mi b)

String Compare
String Compare Description
cmpistrX(mi a, mi b, ii i)
cmpestrX(mi a, i la, mi b, i lb, ii i)
Each operation has an i and an e version. The i version compares
all elements, the e version compares up to specific lengths la andlb. The immediate value i for all these comparisons consists ofbit flags. Exactly one flag per group must be present:
Data type specifier_SIDD_UBYTE_OPS
unsigned 8-bit chars_SIDD_UWORD_OPS
unsigned 16-bit chars_SIDD_SBYTE_OPS
signed 8-bit chars_SIDD_SWORD_OPS
signed 16-bit chars
Compare mode specifier
For each character c in a, determine_SIDD_CMP_EQUAL_ANY
iff any character in b is equal to c.
For each character c in a, determine_SIDD_CMP_RANGES
whether b0 <= c <= b1 or b2 <= c <= b3…
_SIDD_CMP_EQUAL_ORDERED Check for string equality of a and b
Search substring b in a. Each byte where_SIDD_CMP_EQUAL_EACH
b begins in a is treated as match.
Polarity specifier_SIDD_POSITIVE_POLARITY Match is indicated by a 1-bit.
_SIDD_NEGATIVE_POLARITY Negation of resulting bitmask.
Negation of resulting bitmask_SIDD_MASKED_NEGAT
except for bits that have an index
IVE_POLARITY
larger than the size of a or b.

StringCompareString Comparewith Nullcheck

StringNullcheck
SSE4.2 cmpi/estrs/z

SSE4.2 cmpi/estrm

SSE4.2 cmpi/estri

SSE4.2 cmpi/estrc

SSE4.2 cmpi/estra

ps/d,ss/d
NOTE: Compares strings a andb and returns the comparsion
mask. If _SIDD_BIT_MASK isused, the resulting mask is a
bit mask. If _SIDD_UNIT_MASK isused, the result is a byte mask
which has ones in all bits ofthe bytes that do not match.
mi cmpistrm(mi a,mi b,ii i)
mi cmpestrm(mi a,i la,mi b,i lb,ii i)

ps/d,ss/d
NOTE: Compares strings in aand b and returns the index
of the first byte thatmatches. Otherwise Maxsize
is returned (either 8 or 16
depending on data type).
i cmpistri(mi a,mi b,ii i)
i cmpestri(mi a,i la,mi b,i lb,ii i)

ps/d,ss/d

ps/d,ss/d

ps/d,ss/d

NOTE: Compares strings in aand b and returns true iff theresulting mask is not zero,i.e., if there was a match.

NOTE: Compares strings in aand b and returns true iff theresulting mask is zero andthere is no null character in b.

NOTE: Compares two stringsa and b and returns if a (sversion) or b (z version)contains a null character.

i cmpistrc(mi a,mi b,ii i)
i cmpestrc(mi a,i la,mi b,i lb,ii i)

i cmpistra(mi a,mi b,ii i)
i cmpestra(mi a,i la,mi b,i lb,ii i)

i cmpistrs(mi a,mi b,ii i)
i cmpestrs(mi a,i la,mi b,i lb,ii i)