Muon trigger electronics development
toward high luminosity LHC

Makoto TomotoNagoya University

2Introduction• LHC is the energy-frontier experiment to explore new physics by :- precise measurements of Higgs couplings and the other SM processes, and- direct searches for new particles and phenomena• A series of LHC accelerator and ATLAS detector upgrades are scheduled.

Run1

Run2
L=2-3

1034 cm-2s-1

L=5-7.5

1034 cm-2s-1

40 fb-1

We are here.

Phase-1
Productions are started.

Phase-2
Detector and electronics
designs are ﬁnalizing.

Phase-2 upgrades3• The detector for HL-LHC should be designed for peak luminosity of 7 1034 cm-2 s-1
and integrated luminosity of 3000 fb-1 (300 fb-1/year).
- The rates for low-q2 QCD background events are increased.
- The average number of collisions per bunch crossing (pileup) is the level of 200.
- The detector and electronics are exposed to more intense radiation.

A top quark pair production eventwith 200 collisions (pileup)• The detector upgrade for HL-LHC is focused on- Development of the advanced trigger and data acquisition system➡Muon trigger upgrade- Replacement of the inner and forward detectors➡Inner tracker upgradeTrigger and readout scheme

4• To take full advantage of HL-LHC, a new trigger and readout scheme with longer
latency and higher rate is essential.
Latency

Rate

Current

2.5 μs

100 kHz

HL-LHC

10 μs

1 MHz

• Most of the electronics for muon system should be replaced by new ones.
• The advanced muon trigger algorithm is developed to reduce the background ratewith keeping the eﬃciency of the interesting events high.

- Coincidence trigger → Tracking trigger
Muon detectors :Monitored drift tube (MDT): barrel & end-cap
Resistive plate chamber (RPC): barrel
Thin gap chamber (TGC): end-cap

End-cap muon trigger upgrade5• In HL-LHC, the end-cap muon trigger makes trigger decision using the deﬂection
angle (β) between track segments provided by the inner and outer stations- New small wheel (introduced after the Phase1 upgrade) will provide the track
segments with ~1 mrad resolution.

- Upgraded TGC trigger will provide the track segments with ~3 mrad resolution.
- MDT trigger will be newly introduced from Phase2 upgrade and provide the track
segments with ~1 mrad resolution.
MonitoredDriftᐃჾTube (MDT)䃛⢏Ꮚ㣕㊧⢭ᐦ㻾㼑㼟㼕㼟㼠㼕㼢㼑㻌㼜㼘㼍㼠㼑㻌㼏㼔㼍㼙㼎㼑㼞㼟㻔㻾㻼㻯㻕

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New Small Wheel(Micro Megas and TGC)
16

1412108642m

0Performance of new muon trigger

6• Trigger rate study for single muon trigger with 20 GeV threshold is emulated using
Run1 data, s=8 TeV, 25 ns bunch spacing- Rate reduction by the TGC tracking trigger is about 30% in end-cap region(1.3 < |η| < 2.4)
- Rate reduction by the combination of the TGC tracking trigger and the MDT
tracking trigger is about 50% in |η| < 2.4- Eﬃciency of muons reconstructed as pT>20 GeV by oﬄine is better than 95%
ηdistribution of the muons passed the muon trigger condition of pT > 20 GeV

phase-1

New TGC

TGC+MDToﬄine selected muon
pT>20 GeVEnd-cap muon track trigger electronics

We are developing trigger algorithm.
End-cap trigger processor

ASD=ampliﬁer-shaper-discriminator ASICThreshold

TGC front-end board
Variable delay

TGC

Bunch crossing ID

Transmitter
NSW etc.

ASD

We have produced prototype front-end electronics.
MDTTDC

FIFO

Read outTrigger
Processor

CentralTrigger

MDT trigger

Chamber service moduleMarge

MDT mezzanine card

7

EncodeASD
On-detector front-end electronics

TGC front-end board( 20 Gbps hit data transmitter, discriminator threshold )K. Shukutani
T. Kawaguchi

Hit extractor

Read outOﬀ-detector electronics in the counting room

MDT mezzanine card
(TDC readout of drift tube signal)

K. Mizukoshi
Y. Horii

Prototype of TGC front-end board
256 channels
450 mm

270 mmFPGAXilinx Kintex-7(XC7K325TFFG900)
TGC data Transmitter
ASIC/DAC/ADC control
DAC
DAC7578SPW
ADC
LTC1289CCSW

8Bunch crossing ID ASIC
8 ASICs
4 on mother board
4 on daughter board

SFP+ connectors
4 Tx and 4 Rx
(up to 40 Gbps)
RJ45 connector
for debugging
External clock etc.

• This board has all functions for HL-LHC upgrade.
- Bunch crossing ID ASICs need to be replaced by new ones.
- Operating devices (FPGA etc.) in the intense radiation needs to be tested.

9Demonstration of TGC front-end board with test beam
Vthmeasured (mV)Linearity ofThreshold
DAC forthe(Wire,discriminator
thresholdvoltageOpeamp)

μ beam0

Range of the value
in operation

− 50
− 100
− 150
− 200− 250− 300

TGC front-end board− 300

TGC (4 layers)

− 250

− 200

− 150

− 100

VthCERN H8C beam line
Wire: 32 channels0(mV)Eﬃciency of TGC hits
Efficiency

μ beam−50

expected

10.9

μ beam spot
0.8

Layer 4 0.7
Layer 3

Strip:32 channels

1/160.6

BeamLayer 2
Layer 1Layer 1

Layer 2

Layer 3Layer 4The eﬃciencies for L1 and 3 are lower due to the support structure.

The basic functionalities of TGC front-end board has been demonstrated.
14

Prototype of MDT mezzanine card

320 Mbps10• 24 channels• 112.9 mm 92.71 mm• Chips- 3 ASD (amp-shaper-discriminator ) ASIC
- 1 Kintex-7 FPGA (Xilinx) for TDC• I/O- 3 Input connectors for input (other side)- 1 LVDS copper connector for output- SFP+ connector (6.4 Gbps) for debug
26.4 Gbps - 2 SMA connectors• This board has all functions for HL-LHC upgrade.
- ASD ASIC needs to be replaced by new one (developed by MPI group).
- Radiation-tolerant TDC device needs to be considered.
- We are testing to operate FPGA in the intense radiation.
- Alternative candidate is the MDT mezzanine card with ASIC TDC (proposed byUS group)TDC on FPGA11• A multisampling scheme using quad phase clocks with frequency of 320 MHz isemployed to make the bin size of 0.78 nsec.

• The quad phase clocks are synchronized with 40 MHz reference clock (from LHC).
• Time resolution is measured using the test pulse to be 0.23 nsec
= quantization error (0.78 / 12)• The linearity from 0.5 μsec to 100μs is conﬁrmed.
• Raising reference clock up to 110 MHz, the bin size of 0.28 nsec can be achieved.

40 MHz reference clock

The digital part of the mezzanine card has been tested!
→ Extracting drift-time information from MDT hits is on going.

12

Radiation tolerant FPGA

• Choosing radiation tolerant FPGA is crucial for the TGC/MDT electronics upgrades- SRAM type (e.g. Xilinx-Kintex) is expected to have high radiation tolerance
against the total ionization dose (TID), but low radiation tolerance against thesingle event eﬀect (SEE).

- Flash memory type (e.g. Microsemi-IGLOO2) is expected to have high radiation
tolerance against SEE• We produced a test board checking radiation tolerance of IGLOO2 FPGA.
Y. Sanoγ
irradiation
test
has
beenperformedandfound:•- Downloading ﬁrmware got impossible within 100 Gy.
SMA for- Logics already downloaded seem to survive with aHigh speed
higher dose of 100-200 Gy.

serial interface➡ Depending on the location of the front-end
electronics in ATLAS, IGLOO2 FPGA can/cannot
be used for HL-LHC.

• Further studies of radiation tolerant FPGA is needed.
- Rad-tolerance of IGLOO2 FPGA against SEE- Rad-tolerance of Kintex FPGA against TID and SEE

SFP+

IGLOO2 FPGA
M2GL010-FGG484
SMA

JSPS grant“Formation of the international network to challenge the discovery of the newparticles from the advanced muon trigger development”

13Conclusion

14• To take full advantage of HL-LHC physics program, replacement of the trigger andreadout electronics with longer latency and higher rate is essential.

• We devote our large eﬀorts to developing the front-end boards and trigger
algorithm for TGC and MDT tracking trigger.

• The functionalities of the front-end boards has been demonstrated using test
beam and test pulse.

• The radiation tolerance of FPGA is under consideration.

Young staﬀs and students from Nagoya are very active in HL-LHC upgrade project !!

15

Backup16

Muon trigger upgrade
1. Trigger/DAQ scheme upgrade → Replacement of all electronics
L0 Trigger : latency=6μs, Rate=1MHz
L1 Trigger : latency=20μs, Rate=400kHz
2. Development of the advanced trigger algorithm
TGC/RPC track trigger, MDT trigger Monitored䃛⢏Ꮚ㣕㊧⢭ᐦᐃჾDrift Tube(MDT)
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10(2)
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ToroidalMagnetNew small wheelෆ㒊䃛⢏Ꮚ᳨ฟჾ

Current

HL-LHC(1)TGC/RPC Trigger(1)Advanced TGC/RPC trigger(2) MDT trigger(3) Tile-μ trigger
16141210(4) NSW μ trigger(5) ITK trigger

(3)

(3)

2(5)
8Calorimeter

(1)

64

Inner Trackers
Solenoid2m(5)

0Interactionpoint17

FPGA radiation-tolerance study

TID~ 10 kGy(65 nm CMOS Vertex-5)~ 100 Gy
(65 nm IGOOL2)

18

19

We are developing trigger algorithm.

We have produced prototype modules.

TGC

TGC front-end board
Variable delay
Bunch crossing ID

MDT mezzanine card
MDTTDC

EncodeTransmitter
NSW etc.

FIFO

Read outTrigger
Processor

CentralTrigger

MDT trigger
Chamber service moduleMarge

ThresholdEnd-cap trigger processor

On-detector Front-end electronics

Hit extractor

Read out