参考資料
BUF634JAJSH51C – AUGUST 2000 – REVISED MARCH 2024

BUF634 250mA 高速バッファ
1 特長

3 概要

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BUF634 は高速なユニティ ゲインの開ループ バッファで、幅広い用途に適しています。BUF634 をオペアンプの帰還ループ内で使用することにより、出力電流を増幅し、熱帰還を解消し、容量性負荷駆動能力を向上できます。

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このデバイスには、より新しいバージョンが存在します。
BUF634A
大出力電流：250mA
スルーレート：2000V/µs
ピンで選択可能な帯域幅：30MHz～180MHz
低い静止電流：1.5mA (30MHz BW)
幅広い電源電圧範囲：±2.25V～±18V
内部電流制限サーマル シャットダウン保護機能
パッケージ：– 5 ピン SOIC
– 5 ピン TO-220– 5 ピン TO-263 表面実装

2 アプリケーション
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低消費電力のアプリケーションでは、BUF634 は出力250mA、スルーレート 2000V/µs、帯域幅 30MHz で1.5mA の静止電流を実現します。V- ピンと BW ピンとの間に抵抗を接続して、帯域幅を 30MHz～180MHz の範囲で調節できます。
出力回路は内部電流制限とサーマル シャットダウンによって完全に保護されているため、このデバイスは堅牢で、簡単に使用できます。
BUF634 は、機械的要件や消費電力要件に適合するように各種のパッケージで供給されます。SOIC-8 表面実装、
5 リードの TO‑220、5 リードの TO‑263 (DDPAK) 表面実
装プラスチック パワー パッケージがあります。

バルブ ドライバ
ソレノイド ドライバ
オペアンプの電流ブースタ
ライン ドライバ
ヘッドフォン ドライバ
ビデオ ドライバ
モーター ドライバ
試験用機器
ATE ピン ドライバ

パッケージ情報
部品番号

BUF634(1)(2)

パッケージ (1)

パッケージ サイズ(2)D (SOIC、8)4.9mm × 6mm

KC (TO-220、5)

10.16mm × 4.45mm

KTT (TO-263、5)10.16mm × 15.24mm

詳細については、セクション 11 を参照してください。
パッケージ サイズ (長さ × 幅) は公称値であり、該当する場合はピンも含まれます。

1 2

OPA2810

任意のオペアンプの出力電流を増幅

このリソースの元の言語は英語です。 翻訳は概要を便宜的に提供するもので、自動化ツール (機械翻訳) を使用していることがあり、TI では翻訳の正確性および妥当性につきましては一切保証いたしません。 実際の設計などの前には、ti.com で必ず最新の英語版をご参照くださいますようお願いいたします。

English Data Sheet: SBOS030

BUF634

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JAJSH51C – AUGUST 2000 – REVISED MARCH 2024

Table of Contents
1 特長................................................................................... 1
2 アプリケーション...................................................................1
3 概要................................................................................... 1
4 Device Comparison Table...............................................2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics: TO-220 and TO-263
Packages.......................................................................5
6.6 Electrical Characteristics: Wide-Bandwidth Modefor SOIC Package ........................................................ 7
6.7 Electrical Characteristics: Low-QuiescentCurrent Mode for SOIC Package ................................. 8
6.8 Typical Characteristics: TO-220 and TO-263
Packages.......................................................................96.9 Typical Characteristics: SOIC Package ................... 12
7 Detailed Description......................................................18

7.1 Overview................................................................... 18
7.2 Functional Block Diagram......................................... 18
7.3 Feature Description...................................................19
7.4 Device Functional Modes..........................................19
8 Application and Implementation.................................. 20
8.1 Application Information............................................. 20
8.2 Typical Application.................................................... 22
8.3 Power Supply Recommendations.............................23
8.4 Layout....................................................................... 23
9 Device and Documentation Support............................26
9.1 Device Support......................................................... 26
9.2 Documentation Support............................................ 26
9.3 ドキュメントの更新通知を受け取る方法........................ 26
9.4 サポート・リソース........................................................ 26
9.5 Trademarks............................................................... 27
9.6 静電気放電に関する注意事項.................................... 27
9.7 用語集....................................................................... 27
10 Revision History.......................................................... 27
11 Mechanical, Packaging, and Orderable
Information.................................................................... 27

4 Device Comparison Table
VS±(V)

IQ/CHANNEL
(mA)

BW
(MHz)

SLEW RATE(V/µs)VOLTAGE NOISE(nV/√HZ)BUF634A±18

1.5 to 8.5

35 to 210

3750

3.4

Unity-gain, open-loop buffer

BUF634±18

1.5 to 15

30 to 180

2000

4

Unity-gain, open-loop buffer

LMH6321

±18

11

110

1800

2.8

Unity-gain, open-loop buffer withadjustable current limit

DEVICE

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AMPLIFIER DESCRIPTION

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Product Folder Links: BUF634
English Data Sheet: SBOS030

BUF634

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JAJSH51C – AUGUST 2000 – REVISED MARCH 2024

5 Pin Configuration and Functions
BW

1

8

NC

NC

2

7

V+

VIN

3

6

VO

V–

4

5

NC

G=1

G=1

図 5-1. D Package, 8-Pin SOIC (Top View)

1 2 3 4 5

BW V–
V+
VIN VO

図 5-2. KC Package, 5-Pin TO-220 (Top View)

G=1

1 2 3 4 5

BW V–
V+
VIN VO

図 5-3. KTT Package, 5-Pin TO-263 (Top View)
表 5-1. Pin Functions
PIN
NO.
NAME

TYPE

D (SOIC)KC (TO-220)
KTT (TO-263)

BW

1

1

NC

2, 5, 8

V+

7

VIN

3

VO

6

V–

4

DESCRIPTION

Input

Bandwidth adjust pin——

No internal connection

5

Input

Positive power supply

2

Input

Input

4

OutputOutput3

Input

Negative power supply

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Product Folder Links: BUF634
English Data Sheet: SBOS030

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JAJSH51C – AUGUST 2000 – REVISED MARCH 2024

6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)MIN
Supply voltage
Input voltage

V

Continuous

Operating temperature

(1)

UNIT

±18
±VS

Output short-circuit (to ground)

Tstg

MAX

125

°C

Junction temperature

–40

150

°C

Lead temperature (soldering, 10 s)

300

°C

125

°C

Storage temperature–55

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated underRecommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.

6.2 ESD Ratings
VALUE

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)

±2500

V

Charged-device model (CDM), per JEDEC specification JESD22-C101(2)

±1000

V

±2500

V

BUF634U in D (SOIC) Package
V(ESD)

Electrostatic discharge

BUF634U in D (SOIC) Package
V(ESD)

Electrostatic discharge,

BUF634F in KC (TO-220) and KTT (TO-263) Packages
V(ESD)(1)(2)

Electrostatic discharge

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)

JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VS = (V+) – (V–)

Supply voltage

TA

Operating temperature

MIN

NOM

MAX

UNIT

±2.25 (4.5)±15 (30)±18 (36)

V

-40

25

85

°C

6.4 Thermal Information
BUF634
THERMAL METRIC(1)D (SOIC)KC (TO-220)

KTT (TO-263)

8 PINS

5 PINS

5 PINS

UNIT

RθJA

Junction-to-ambient thermal resistance

123

32.1

41.8

°C/W

RθJC(top)

Junction-to-case (top) thermal resistance

55

25.6

45

°C/W

RθJB

Junction-to-board thermal resistance

68

18.3

24.8

°C/W

ψJT

Junction-to-top characterization parameter

12

8.5

13.1

°C/W

ψJB

Junction-to-board characterization parameter

67

17.7

23.8

°C/W

RθJC(bot)

Junction-to-case (bottom) thermal resistance

N/A

0.7

2.4

°C/W

(1)

For information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

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English Data Sheet: SBOS030

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6.5 Electrical Characteristics: TO-220 and TO-263 Packages
at TA = +25°C(1), VS = ±15 V, specifications are for both low quiescent-current mode and wide-bandwidth mode (unlessotherwise noted)
PARAMETERTEST CONDITIONS

MIN

TYP

MAX

±30

±100

UNIT

INPUT
Offset voltage
Offset voltage vs temperatureSpecified temperature range

Offset voltage vs power supply

VS = ±2.25 V(2) to ±18 V

Input bias current

VIN = 0 V

Input impedance

RL = 100 ΩNoise voltage

±100

mV
µV/°C

0.1

1

Low quiescentcurrent mode

±0.5

±2

Wide bandwidth
mode

±5

±20

mV/V

µA

Low quiescentcurrent mode

80 || 8Wide bandwidthmode

8 || 8

MΩ || pF

f = 10 kHz

4nV/√HzGAIN

Gain

RL = 1 kΩ, VO = ±10 V

0.95

0.99

RL = 100 Ω, VO = ±10 V

0.85

0.93

RL = 67 Ω, VO = ±10 V

0.8

0.9

V/V

OUTPUT
Current output, continuous

Voltage output±250

Positive

IO = 10 mA(V+) – 2.1(V+) – 1.7

Negative

IO = –10 mA(V–) + 2.1(V–) + 1.8

Positive

IO = 100 mA(V+) – 3(V+) – 2.4

Negative

IO = –100 mA(V–) + 4(V–) + 3.5

Positive

IO = 150 mA(V+) – 4(V+) – 2.8

Negative

IO = –150 mA(V–) + 5(V–) +4

Short-circuit current

mA

V

Low quiescent current mode

±350

±550

Wide bandwidth mode

±400

±550

mA

DYNAMIC RESPONSE

RL = 1 kΩ
Bandwidth, –3dB
RL = 100 Ω

Slew rate
Settling time

Low quiescentcurrent mode

30

Wide bandwidth
mode

180

Low quiescentcurrent mode20

Low quiescentcurrent mode

160

20 Vp-p, RL = 100 Ω
0.1%
1%

Differential gain

Differential phase

Copyright © 2024 Texas Instruments Incorporated

2000
200

20-V step, RL = 100 Ω

3.58 MHz, VO = 0.7 V,
RL = 150 Ω

3.58 MHz, VO = 0.7 V,
RL = 150 ΩMHz

50
Low quiescentcurrent mode

4%

Wide bandwidth
mode

0.4%

Low quiescentcurrent mode

2.5

Wide bandwidth
mode

0.1

V/µs
ns

°

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Product Folder Links: BUF634
English Data Sheet: SBOS030

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JAJSH51C – AUGUST 2000 – REVISED MARCH 2024

6.5 Electrical Characteristics: TO-220 and TO-263 Packages (続き)at TA = +25°C(1), VS = ±15 V, specifications are for both low quiescent-current mode and wide-bandwidth mode (unlessotherwise noted)
PARAMETERTEST CONDITIONS

MIN

TYP

MAX

UNIT

POWER SUPPLYSpecified operating voltage±15±2.25(2)Operating voltage

IQ

Quiescent current

IO = 0 mA

V±18

Low quiescentcurrent mode

±1.5

±2

Wide bandwidth
mode

±15

±20

V

mA

TEMPERATURE
TJ(1)

Thermal shutdown temperature

175

°C

(2)

Tests are performed on high-speed automatic test equipment, at approximately 25°C junction temperature. The power dissipation ofthis product causes some parameters to shift when warmed up. See セクション 6.8 for overtemperature performance.
Limited output swing available at low supply voltage. See output voltage specifications.

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JAJSH51C – AUGUST 2000 – REVISED MARCH 2024

6.6 Electrical Characteristics: Wide-Bandwidth Mode for SOIC Package
at TA = 25°C, VS = ±15 V, BW pin connected to V–, and RL = 100 Ω connected to mid-supply (unless otherwise noted)
PARAMETERTEST CONDITIONS

MIN

TYP

MAX

UNIT

AC PERFORMANCEBW

Bandwidth, –3 dB

SR

RL = 1 kΩ

210

RL = 100 Ω

200

MHz

Bandwidth for 0.1-dB flatness

VO = 10 mVPP, RL = 100 Ω, RS = 50 Ω

50

MHz

Slew rate

VO = 20-V step, VIN-SR = 4000 V/µs

3750

V/µs

Rise and fall timeVO = 200-mV step

1.3

ns

Settling time to 0.1%

VO = 20-V step, VIN-SR = 2500 V/µs

90ns

Settling time to 1%

VO = 20-V step, VIN-SR = 2500 V/µs

20

ns

en

Voltage noisef = 1 kHz

3.4

nV/√HzinCurrent noisef = 100 kHz

0.85

pA/√HzVO = 2 VPP, f = 20 kHz–77

VO = 10 VPP, f = 20 kHz–69

VO = 2 VPP, f = 20 kHz–77

VO = 10 VPP, f = 20 kHz

–56

HD2

2nd-harmonic distortionHD3

3rd-harmonic distortion

dBc
dBc

DC PERFORMANCE
VOS
IB
G

Input offset voltage

TA = 25℃

36

Input offset voltage drift(1)TA = –40℃ to 125℃

175

Input bias current

VIN = 0 V

0.25

65
2

VO = ±10 V, RL = 1 kΩ

0.95

0.99

VO = ±10 V, RL = 100 Ω

0.93

0.95

VO = ±10 V, RL = 67 Ω

0.91

0.93

Linear input voltage range

RL = 1 kΩ, IB < 10 µA–13Input impedance

RL = 100 Ω

180 || 5

IO = ±10 mA

1.6

1.8

IO = ±100 mA

2.0

2.2

IO = ±150 mA

2.2

2.5

Gain

mV
µV/℃
µA
V/V

INPUT
ZIN

13

V
MΩ || pF

OUTPUT
Output headroom to supplies
IO

Current output, continuous

±250

ISC

Short-circuit current

±375

ZO

Output impedance

DC, IO = 10 mA

V
mA

±550

mA

5

Ω

POWER SUPPLYVSOperating voltage range

IQ

Quiescent current

IO = 0 mA

±2.25

PSRR

Power-supply rejection ratio

VS = ±2.25 V to ±18 V

8.5
64

±18

V

12

mA

75

dB

180

℃

THERMAL SHUTDOWN
Thermal shutdown
temperature(1)

Based on electrical characterization over temperature of 35 devices.

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English Data Sheet: SBOS030

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JAJSH51C – AUGUST 2000 – REVISED MARCH 2024

6.7 Electrical Characteristics: Low-Quiescent-Current Mode for SOIC Package
at TA = 25°C, VS = ±15 V, BW pin left open, and RL = 100 Ω connected to mid-supply (unless otherwise noted)
PARAMETERTEST CONDITIONS

MIN

TYP

MAX

UNIT

AC PERFORMANCEBW

Bandwidth, –3 dB

SR

RL = 1 kΩ

35

RL = 100 Ω

31

MHz

Bandwidth for 0.1-dB flatness

VO = 10 mVPP, RL = 100 Ω, RS = 50 Ω

2.3

MHz

Slew rate

VO = 20-V step, VIN-SR = 4000 V/µs

3750

V/µs

Rise and fall timeVO = 200-mV step4

ns

Settling time to 0.1%

VO = 20-V step, VIN-SR = 2500 V/µs

400

ns

Settling time to 1%

VO = 20-V step, VIN-SR = 2500 V/µs

90

ns

en

Voltage noisef = 1 kHz

8.1

nV/√HzinCurrent noisef = 10 kHz

0.3

pA/√HzVO = 2 VPP, f = 20 kHz–54

VO = 10 VPP, f = 20 kHz–65

VO = 2 VPP, f = 20 kHz–40

VO = 10 VPP, f = 20 kHz

–44

HD2

2nd-harmonic distortionHD3

3rd-harmonic distortion

dBc
dBc

DC PERFORMANCE
VOS
IB
G

Input offset voltage

TA = 25℃

36

Input offset voltage drift(1)TA = –40℃ to 125℃

175

Input bias current

VIN = 0 V

0.03

65
0.25

VO = ±10 V, RL = 1 kΩ

0.95

0.99

VO = ±10 V, RL = 100 Ω

0.93

0.95

VO = ±10 V, RL = 67 Ω

0.91

0.93

Linear input voltage range

RL = 1 kΩ, IB < 10 µA–13Input impedance

RL = 100 Ω

1400 || 5

IO = ±10 mA

1.6

1.8

IO = ±100 mA

2.0

2.2

IO = ±150 mA

2.2

2.5

Gain

mV
µV/℃
µA
V/V

INPUT
ZIN

13

V
MΩ || pF

OUTPUT
Output headroom to supplies
IO

Current output, continuous

±250

ISC

Short-circuit current

±350

ZO

Output impedance

DC, IO = 10 mA

V
mA

±550

7

mA
Ω

POWER SUPPLYVSOperating voltage range

IQ

Quiescent current

IO = 0 mA

±2.25

PSRR

Power-supply rejection ratio

VS = ±2.25 V to ±18 V

1.5
64

±18

V

2.3

mA

80

dB

180

℃

THERMAL SHUTDOWN
Thermal shutdown
temperature(1)

Based on electrical characterization over temperature of 35 devices.

8

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English Data Sheet: SBOS030

BUF634

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JAJSH51C – AUGUST 2000 – REVISED MARCH 2024

6.8 Typical Characteristics: TO-220 and TO-263 Packages
at TA = 25°C, VS = ±15 V (unless otherwise noted)

–10
0

–40

Phase (°)

–30

–5

Wide BW–15–20

TJ = –40°C
TJ = 25°C
TJ = 125°C

Low IQ

–30
–40

–50

–50
10M
100M
Frequency (Hz)1G

1M

図 6-1. Gain and Phase vs Frequency vs Quiescent Current

10M
100M
Frequency (Hz)

図 6-2. Gain and Phase vs Frequency vs Temperature

100Wide BW–5

Low IQ

RS = 50ΩVO = 10mV

Gain (dB)

RL = 100Ω
VO = 10mV 5

1G–5Low IQ

–20
–30

–15

–10

Wide BW

Phase (°)

RS = 0Ω
RS = 50Ω
RS = 100Ω

Low IQ–40

Wide BW–20

RL = 1kΩ
RL = 100Ω
RL = 50Ω

Low IQ

–30
–40

–50

–50
1M

10M
100M
Frequency (Hz)1G

1M

図 6-3. Gain and Phase vs Frequency vs Source Resistance
10
5
0
–5

1G

図 6-4. Gain and Phase vs Frequency vs Load Resistance
RL = 100Ω
RS = 50ΩVO = 10mV

Gain (dB)

RL = 100Ω
RS = 50ΩVO = 10mV

Low IQ Mode

10M
100M
Frequency (Hz)–40

Phase (°)

–30

–15

–10

CL = 0pF
CL = 50pF
CL = 200pF
CL = 1nF–20

CL = 0CL = 50pF
CL = 200pF
CL = 1nF

–20
–30
–40

–50

0

–10
0

–15

–10

5

–5

Wide BW Mode

–10
0

10

Gain (dB)

Phase (°)

–10
0

–15

–10

5
0

Wide BW–10
0

10

Gain (dB)

1M

Phase (°)

0–10

IQ = 15mA
IQ = 9mA
IQ = 4mA
IQ = 2.5mA
IQ = 1.5mA–20

Wide BW

5

–10
0

–15

–10

Phase (°)

Low IQ

10

Gain (dB)–5

RL = 100Ω
RS = 50ΩVO = 10mV

Gain (dB)10
RL = 100Ω
5RS = 50ΩVO = 10mV 0

–50
1M

10M
100M
Frequency (Hz)1G

図 6-5. Gain and Phase vs Frequency vs Load Capacitance

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1M

10M
100M
Frequency (Hz)1G

図 6-6. Gain and Phase vs Frequency vs Load Capacitance

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JAJSH51C – AUGUST 2000 – REVISED MARCH 2024

6.8 Typical Characteristics: TO-220 and TO-263 Packages (continued)
at TA = 25°C, VS = ±15 V (unless otherwise noted)
100

5

90

0
–5

Low IQ–10
0–15

Phase (°)

–10

Wide BW–20

Low IQ–30–40

VS = ±18V
VS = ±12V
VS = ±5V
VS = ±2.25V

Power Supply Rejection (dB)

Wide BW

10

Gain (dB)

RL = 100Ω
RS = 50ΩVO = 10mV

80
Wide BW

70
60
50
40
Low IQ

30
20
10
0

–50
1M

10M
100M
Frequency (Hz)

1k

1G

10k

100k

1M

10M

Frequency (Hz)

図 6-7. Gain and Phase vs Frequency vs Power Supply Voltage20

図 6-8. Power Supply Rejection vs Frequency
500

+15V

18
450

15mA at R = 0

14

BW

12

R

Limit Current (mA)

Quiescent Current (mA)

16

10
8

–15V

6
4

400

Wide Bandwidth Mode350
Low IQ Mode
300
250

2

1.5mA at R = ∞

200

0
10

100

1k

–50

10k

–25

0

Resistance (Ω)

図 6-9. Quiescent Current vs Bandwidth Control Resistance
7

25

50

75

100

125

150

Junction Temperature (°C)

図 6-10. Short-Circuit Current vs Temperature
20

Cooling
Low IQ Mode

Quiescent Current (mA)

Quiescent Current (mA)

6
5
4
»10°C
3
2

Thermal Shutdown

15

10
»10°C

Wide BW Mode
51Cooling
Thermal Shutdown

00–50 –25

0

25

50

75

100 125 150 175 200–50

図 6-11. Quiescent Current vs Temperature

10

–25

0

25

50

75

100

125

150

175

200

Junction Temperature (°C)

Junction Temperature (°C)

図 6-12. Quiescent Current vs Temperature

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6.8 Typical Characteristics: TO-220 and TO-263 Packages (continued)
at TA = 25°C, VS = ±15 V (unless otherwise noted)
13

13

VIN = 13V

Output Voltage Swing (V)Output Voltage Swing (V)1211
VS = ±15V
Low IQ Mode

10
–10
–11

TJ = –40°C
TJ = 25°C
TJ = 125°C–12
VIN = –13V

VIN = 13V

12
11
VS = ±15V
Wide BW Mode

10
–10
–11

TJ = –40°C
TJ = 25°C
TJ = 125°C–12
VIN = –13V

–13

–13
0

50

100

150

200

250

300

0

50

100

|Output Current| (mA)

150

200

300

図 6-13. Output Voltage Swing vs Output Current

図 6-14. Output Voltage Swing vs Output Current

312TO-220 and DDPAKInfinite Heat Sink
ΘJC = 6°C/W

2

Power Dissipation (W)10Power Dissipation (W)250|Output Current| (mA)

TO-220 and DDPAKFree AirΘJA = 65°C/W

8-Pin DIP
ΘJA = 100°C/W
1SO-8
ΘJA = 150°C/W

8
6

TO-220 and DDPAKFree AirΘJA = 65°C/W

4
2
0

0
–50

–25

0

25

50

75

100

125

–50

150

図 6-15. Maximum Power Dissipation vs Temperature

Input

100mV/div

0

25

50

75

100

125

150

図 6-16. Maximum Power Dissipation vs Temperature

Input

Wide BW
Mode

Wide BWMode

Low IQMode

Low IQMode

20ns/div
RS = 50 Ω, RL = 100 Ω

100mV/div

20ns/div

RS = 50 Ω, RL = 100 Ω

図 6-17. Small-Signal Response

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Ambient Temperature (°C)

Ambient Temperature (°C)

図 6-18. Large-Signal Response

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6.9 Typical Characteristics: SOIC Package

10

5

5

0

0

-10
0

-15

-10
-20

8.6 mA
6.6 mA
4.9 mA
2.7 mA
1.5 mA

-30
-40
-50
100k

1M

10M
Frequency (Hz)

100M

-5
Phase (o)Phase (o)-5Normalized Gain (dB)

10

-10
-15

0
-10
-20
-30

-40oC
25oC
125oC

-40
-50
100k

1G

Normalized Gain (dB)at TA = 25°C, VS = ±15 V, RS = 50 Ω, and RL = 100 Ω (unless otherwise noted).

1M

D001

10M
Frequency (Hz)

100M

1G
D002

Solid lines indicate wide-BW mode,
dashed lines indicate low-IQ mode

5

0

0

-15

-10
-20

-50
100k

1M

10M
Frequency (Hz)

100M

-30
-40
-50
100k

1G

0

CL = 0 pF
CL = 47 pF
CL = 220 pF
CL = 1 nF-5Phase (o)Normalized Gain (dB)

Phase (o)図 6-22. Gain and Phase vs Frequency and Load Resistance

0

-20

-10
0

-20
-30
-40

1G

-15

-10

-50
100k

D005

Low-IQ mode

CL = 0 pF
CL = 47 pF
CL = 220 pF
CL = 1 nF
1M

10M
Frequency (Hz)

100M

1G
D006

Wide-BW mode

図 6-23. Gain and Phase vs Frequency and Load Capacitance

12

D004

5

-10

100M

1G

10

-15

0

10M
Frequency (Hz)

100M

5

-10

1M

10M
Frequency (Hz)

10

-5

-50
100k

1M

Solid lines indicate wide-BW mode,
dashed lines indicate low-IQ mode

図 6-21. Gain and Phase vs Frequency and Source Resistance-40

RL = 1 k:
RL = 100 :RL = 50 :D003

Solid lines indicate wide-BW mode,
dashed lines indicate low-IQ mode

-30

-15

-10
-20

RS = 0 :RS = 50 :
RS = 100 :

-40

-10
0

Normalized Gain (dB)-30

-5Phase (o)Phase (o)-10Normalized Gain (dB)

10

5

-5

0

図 6-20. Gain and Phase vs Frequency and Temperature

10

Normalized Gain (dB)

図 6-19. Gain and Phase vs Frequency and Quiescent Current

図 6-24. Gain and Phase vs Frequency and Load Capacitance

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6.9 Typical Characteristics: SOIC Package (continued)
at TA = 25°C, VS = ±15 V, RS = 50 Ω, and RL = 100 Ω (unless otherwise noted).
100

5

90

Phase (o)

-5
-10
0

-15

-10
-20
VS = ±2.25 V
VS = ±5 V
VS = ±12 V
VS = ±18 V

-30
-40
-50
100k

1M

10M
Frequency (Hz)

100M

Normalized Gain (dB)0Power Supply Rejection Ratio (dB)

10

80
70
60
50
40
30
20
PSRR+
PSRR

10
0
10

1G

100

D008

Low-IQ
Wide-BW

10

Current Noise (pA/—Hz)

Voltage Noise (nV/—Hz)

10M

100

Low-IQ
Wide-BW

1k
Frequency (Hz)1M

図 6-26. PSRR vs Frequency

図 6-25. Gain and Phase vs Frequency and Power-Supply
Voltage

100

10k
100k
Frequency (Hz)Solid lines indicate wide-BW mode,
dashed lines indicate low-IQ mode

Solid lines indicate wide-BW mode,
dashed lines indicate low-IQ mode

1
10

1k

D007

10k

10

1

0.1
0.1

100k

1

10

D011

図 6-27. Voltage Noise Density vs Frequency

100
1k
10k
Frequency (Hz)

100k

1M

10M
D017

図 6-28. Current Noise Density vs Frequency

-40

-40

Harmonic Distortion (dBc)

Harmonic Distortion (dBc)

-50
-60
-70
-80
-90
-100
-110
-120
100

-50

-60

-70

HD2
HD3
1k

10k
100k
Frequency (Hz)

1M

HD2
HD3

10M

-80
100

D012

1k

10k
100k
Frequency (Hz)1M

Wide-BW mode, VIN = 10 VPP, RL = 1 kΩWide-BW mode, VIN = 10 VPP, RL = 100 Ω

図 6-29. Harmonic Distortion vs Frequency

図 6-30. Harmonic Distortion vs Frequency

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10M
D013

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6.9 Typical Characteristics: SOIC Package (continued)
at TA = 25°C, VS = ±15 V, RS = 50 Ω, and RL = 100 Ω (unless otherwise noted).
-30

-30

Harmonic Distortion (dBc)

-50
-60
-70
-80
-90

-40

-50

-60

HD2
HD3

-100
100

1k

10k
100k
Frequency (Hz)

1M

HD2
HD3
-70
100

10M

Low-IQ mode, VIN = 10 VPP, RL = 1 kΩ
図 6-31. Harmonic Distortion vs Frequency
RL = 1 k:
RL = 100 :D015

Low-IQ
Wide-BW

400

180

Limit Current (mA)

-3 dB Bandwidth (MHz)10M

図 6-32. Harmonic Distortion vs Frequency

150
120
90

375
350
325
300

60
30
10

100

1k
10k
Resistance (:)

100k

275
-50

1M

-12

13.5

-12.4

13.2

-12.8

12.9

-13.2

12.6

-13.6

12.3
50

100
150
|Output Current| (mA)

200

-14
250

Output Voltage Swing - Sourcing (V)13.8

図 6-35. Output Voltage Swing vs Output Current

25
50
75
100
Junction Temperature (oC)

125

150
D016

14.1

-11.6

13.8

-12

13.5

-12.4

13.2

-12.8

12.9

-13.2

12.6

-13.6
TA = -40oC
TA = 25oC
TA = 125oC

12.3

-14

12
0

50

D035

Wide-BW mode (solid lines indicate sourcing current,
dashed lines indicate sinking current)0

図 6-34. Short-Circuit Current vs Temperature-11.6

TA = 25oC
TA = -40oC
TA = 125oC

Output Voltage Swing - Sinking (V)

14.1

-25

D001

図 6-33. Small-Signal Bandwidth vs Bandwidth Adjustment
Resistance

Output Voltage Swing - Sourcing (V)

1M

425

210

14

10k
100k
Frequency (Hz)Low-IQ mode, VIN = 10 VPP, RL = 100 Ω

240

0

1k

D014

100
150
|Output Current| (mA)200

Output Voltage Swing - Sinking (V)Harmonic Distortion (dBc)

-40

-14.4
250
D034

Low-IQ mode (solid lines indicate sourcing current,
dashed lines indicate sinking current)
図 6-36. Output Voltage Swing vs Output Current

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6.9 Typical Characteristics: SOIC Package (continued)
at TA = 25°C, VS = ±15 V, RS = 50 Ω, and RL = 100 Ω (unless otherwise noted).
12

0.2

Input and Output Voltage (V)8

Input and Output Voltage (V)

VIN
VO-Low-IQ
VO-Wide-BW

10
6
4
2
0
-2
-4
-6
-8

VIN
VO-Low-IQ
VO-Wide-BW

0.15
0.1
0.05
0
-0.05
-0.1

-10
-12

-0.15
Time (50 ns/div)

Time (20 ns/div)
D010

D009

図 6-37. Large-Signal Transient Response

図 6-38. Small-Signal Transient Response

100

10
Low-IQ
Wide-BW

Low-IQ: Sinking
Low-IQ: Sourcing
Wide-BW: Sinking
Wide-BW: Sourcing

Output Impedance (:)

Output Impedance (:)

8

10

6

4

2

0
10

1
0

50

100
150
Output Current (mA)

200

250

100

1k

10k
100k
1M
Frequency (Hz)D030

f = 100 kHz

100M
D036

IO = 100 mA

図 6-39. Output Impedance vs Output Current

図 6-40. Output Impedance vs Frequency

60

6000

50

5000
No. of Units in Each Bin

40
30
20
TA = 40oC
TA = 25oC
TA = 85oC
TA = 125oC

10

4000
3000
2000
1000

0

48

46

44

42

40

36

38

32

36

28

34

16
20
24
Supply Voltage (V)

32

12

30

8

28

0
4

26

Offset Voltage (mV)

10M

Offset Voltage (mV)

D020

D032

14000 devices, µ = 35.7 mV, σ = 2.15 mV
図 6-41. Offset Voltage vs Supply Voltage

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図 6-42. Offset Voltage Distribution Histogram

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6.9 Typical Characteristics: SOIC Package (continued)

55

14

50

12

No. of Units in Each Bin

Offset Voltage (mV)at TA = 25°C, VS = ±15 V, RS = 50 Ω, and RL = 100 Ω (unless otherwise noted).

45
40
35
30

10
8
6
4
2

25

155

150

145

140

135

150

130

125

125

25
50
75
100
Ambient Temperature (oC)

120

0

115

-25

110

0

20
-50

D031

Input Offset Drift (PV/oC)

D021

35 devices

TA = –40°C to +125°C, 35 devices,µ = 134 μV/°C, σ = 7.4 μV/°C

図 6-43. Offset Voltage vs Temperature

図 6-44. Offset Voltage Drift Distribution Histogram

0.2

1

0.15

0.8

Input Bias Current (PA)Input Bias Current (PA)

0.6
0.1
0.05
0
-0.05
-0.1

0.4
0.2
0
-0.2
-0.4
-0.6

-0.15

-0.8

-0.2

-1
4

6

8 10 12 14 16 18 20 22 24 26 28 30 32 34 36
Supply Voltage (V)
D022

4

6

8 10 12 14 16 18 20 22 24 26 28 30 32 34 36
Supply Voltage (V)D023

Low-IQ mode, 35 devices

Wide-BW mode, 35 devices

図 6-45. Input Bias Current vs Supply Voltage

図 6-46. Input Bias Current vs Supply Voltage
9

Quiescent Current (mA)

Quiescent Current (mA)

1.6

1.5

1.4

1.3

1.2

8.5

8

7.5

7
4

8

12

16
20
24
Supply Voltage (V)

28

32

36

4

D024

Low-IQ mode, 35 devices

12

16
20
24
Supply Voltage (V)

28

32

36
D025

Wide-BW mode, 35 devices

図 6-47. Quiescent Current vs Supply Voltage

168

図 6-48. Quiescent Current vs Supply Voltage

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6.9 Typical Characteristics: SOIC Package (continued)
at TA = 25°C, VS = ±15 V, RS = 50 Ω, and RL = 100 Ω (unless otherwise noted).
9.5

Quiescent Current (mA)

Quiescent Current (mA)

1.8

1.7

1.6

1.5

9.1

8.7

8.3

7.9

1.4
-50

-25

0
25
50
75
Ambient Temperature (oC)

100

7.5
-50

125

-25

D028

Low-IQ mode, 35 devices

0.955

0.965

0.95

0.96

0.945

D029

0.955

0.94

0.95

0.935

0.945

0
25
50
75
Ambient Temperature (oC)125

図 6-50. Quiescent Current vs Temperature
0.97

Gain (V/V)

Gain (V/V)

図 6-49. Quiescent Current vs Temperature

-25

100

Wide-BW mode, 35 devices

0.96

0.93
-50

0
25
50
75
Ambient Temperature (oC)

100

125

0.94
-50

-25

D026

Low-IQ mode, 35 devices

0
25
50
75
Ambient Temperature (oC)

100

125
D027

Wide-BW mode, 35 devices

図 6-51. Buffer Gain vs Temperature

図 6-52. Buffer Gain vs TemperaturePower Dissipation (W)

2

1.5

1

0.5

0
-50

-25

0

25
50
75
100
Ambient Temperature (oC)

125

150
D033

図 6-53. Maximum Power Dissipation vs Temperature

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7 Detailed Description
7.1 Overview
The BUF634 device is a high-speed, unity-gain open-loop buffer recommended for a wide range of applications.
The BUF634 can be used inside the feedback loop of op amps to increase output current, eliminate thermal
feedback, and improve capacitive load drive.
For low-power applications, the BUF634 operates on 1.5-mA quiescent current with 250-mA output, 2000‑V/µsslew rate, and 30-MHz bandwidth. Bandwidth can be adjusted from 30 MHz to 180 MHz by connecting a resistor
between V– and the BW pin; see 図 6-9 and 図 6-1. Output circuitry is fully protected by internal current limit andthermal shutdown, making this device rugged and easy to use.
For a simplified circuit diagram of the BUF634 showing the open-loop complementary follower design, see セクシ
ョン 7.2.

7.2 Functional Block Diagram
V+

V+

ThermalShutdown

ThermalShutdown

I1(1)
VIN 200Ω

50

VO

VO

VIN

1.2 k

I1(1)

8k
BW

150Ω

V±

図 7-2. Internal Block Diagram: SOIC

4kΩ

BW

V–

Signal path indicated in bold.
Note: (1) Stage currents are set by I1.

図 7-1. Internal Block Diagram: TO-220 and TO-263

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7.3 Feature Description
7.3.1 Output Current
The BUF634 delivers up to ±250-mA continuous output current. Internal circuitry limits output current toapproximately ±350 mA; see 図 6-10. For many applications, however, the continuous output current is limited bythermal effects.
The output voltage swing capability varies with junction temperature and output current; see 図 6-14. Although
all four package types are tested for the same output performance using a high speed test, the higher junction
temperatures with the DIP and SO-8 package types often provide less output voltage swing. Junction
temperature is reduced in the TO-263 surface-mount power package because this package is soldered directly
to the circuit board. The TO-220 package used with a good heat sink further reduces junction temperature,
allowing maximum possible output swing.

7.4 Device Functional Modes
The BUF634 is operational when the power-supply voltage is greater than 4.5 V (±2.25 V). The maximum power
supply voltage for the BUF634 is 36 V (±18 V). At low power supply conditions, such as ±2.25 V, the output
swing can be limited. For additional information, see セクション 6.5.

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8 Application and Implementation
注以下のアプリケーション情報は、TI の製品仕様に含まれるものではなく、TI ではその正確性または完全性を保証いたしません。個々の目的に対する製品の適合性については、お客様の責任で判断していただくことになります。お客様は自身の設計実装を検証しテストすることで、システムの機能を確認する必要があります。

8.1 Application Information
図 8-1 shows the BUF634 device connected as an open-loop buffer. The source impedance and optional input
resistor, RS, influence frequency response: see セクション 6.8. Bypass power supplies with capacitors connectedclose to the device pins. Capacitor values as low as 0.1 µF provide stable operation in most applications, buthigh output current and fast output slewing can demand large current transients from the power supplies. Solidtantalum 10-µF capacitors are recommended. High-frequency, open-loop applications can benefit from special
bypassing and layout considerations. For more information, see セクション 8.1.1.
V+
10µF
DIP/SO-8
Pinout shown
7
VIN

RS

3

BUF634
4

1

6

VO
RL

10µF
Optional connection for
wide bandwidth — see text.
V–

図 8-1. Buffer Connections
8.1.1 High Frequency Applications
The excellent bandwidth and fast slew rate of the BUF634 device are useful in a variety of high frequency openloop applications. When operated open-loop, printed-circuit-board layout and bypassing technique can affectdynamic performance.
For best results, use a ground plane-type circuit board layout and bypass the power supplies with 0.1-µF
ceramic chip capacitors at the device pins in parallel with solid tantalum 10-µF capacitors. Source resistanceaffects high-frequency peaking, step-response overshoot and ringing. Best response is usually achieved with aseries input resistor of 25 Ω to 200 Ω, depending on the signal source. Response with some loads (especiallycapacitive) can be improved with a resistor of 10 Ω to 150 Ω in series with the output.

図 8-2. High Performance Headphone Driver

20

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+24V

C(1)
10kΩ
+

10µF

BUF634
C(1)
10kΩ

+
12V
–
pseudoground+12V–

NOTE: (1) System bypass capacitors.

図 8-3. Pseudo-Ground Driver
IO = ±200mA

VIN±2V
OPA177

BUF634Valve10Ω

図 8-4. Current-Output Valve Driver
10kΩ

1kΩ

VIN
±1V

10kΩ

9kΩ

1/2
OPA2234

BUF634

Motor

BUF634

1/2
OPA2234±20V
at 250mA

図 8-5. Bridge-Connected Motor Driver

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8.2 Typical Application
8.2.1 Boosting Op Amp Output Current
The BUF634 device can be connected inside the feedback loop of most op amps to increase output current (see
図 8-6). When connected inside the feedback loop, the offset voltage of the BUF634 device and other errors arecorrected by the feedback of the op amp.
V+

C1(1)
VO
VIN

OPA

NOTE: (1) C1 not required
for most common op amps.
Use with unity-gain stablehigh speed op amps.

BUF634
BW

Wide BW mode
(if required)V–

OP AMPRECOMMENDATIONSOPA177, OPA1013
OPA111, OPA2111
OPA121, OPA234 (1),
OPA130 (1)Use Low I Q mode. G = 1 stable.

OPA27, OPA2107
OPA602, OPA131 (1)Low I Q mode is stable. Increasing CL may cause
excessive ringing or instability. Use Wide BW mode.

OPA627, OPA132 (1)Use Wide BW mode, C1 = 200pF. G = 1 stable.

OPA637, OPA37

Use Wide BW mode. These op amps are not G = 1
stable. Use in G > 4.

NOTE: (1) Single, dual, and quad versions.

図 8-6. Boosting Op Amp Output Current
8.2.1.1 Design Requirements
•
•
•
•
•
•

Boost the output current of an OPA627
Operate from ±15V power supplies
Operate from -40°C to +85°C
Gain = 23.5 V/V
Output current = ±250 mA
Bandwidth greater than 100 kHz

8.2.1.2 Detailed Design Procedure
To make sure that the composite amplifier remains stable, the phase shift of the BUF634 must remain small
throughout the loop gain of the circuit. For a G = +1 op-amp circuit, the BUF634 must contribute little additional
phase shift (approximately 20° or less) at the unity-gain frequency of the op amp. Phase shift is affected byvarious operating conditions that can affect stability of the op amp; see セクション 6.8.
Most general-purpose or precision op amps remain unity-gain stable with the BUF634 connected inside thefeedback loop as shown. Large capacitive loads can require the BUF634 to be connected for wide bandwidthand stable operation. High-speed or fast-settling op amps generally require the wide bandwidth mode to remain
stable and to maintain good dynamic performance. To check for stability with an op amp, look for oscillations orexcessive ringing on signal pulses with the intended load, and worst-case conditions that affect phase responseof the buffer. Connect the circuit as shown in 図 8-6. Choose resistors to provide a voltage gain of 23.5 V/V.
Select the feedback resistor to be 2.7 kΩ. Choose the input resistor to be 120 Ω.

22

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8.2.1.3 Application Curve

Gain (db)

40

20

0
100

1k

10k
Frequency (Hz)

100k

1M

図 8-7. Frequency Response of Composite Amplifier

8.3 Power Supply Recommendations
The BUF634 is specified for operation from 4.5V to 36 V (±2.25 V to ±18 V). Many specifications apply from –40°C to +85°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature
are presented in セクション 6.8.

8.4 Layout
8.4.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:• Noise can propagate into analog circuitry through the power pins of the circuit. Bypass capacitors are used toreduce the coupled noise by providing low-impedance power sources local to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds paying attention to the flow of the ground current. For more detailed information refer toCircuit Board Layout Techniques, SLOA089.
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If
these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as opposed
to in parallel with the noisy trace.
• Place the external components as close to the device as possible. As illustrated in 図 8-9• Keep the length of input traces as short as possible. Always remember that the input traces are the mostsensitive part of the circuit.
• Clean the PCB following board assembly for best performance.
• Any precision integrated circuit can experience performance shifts due to moisture ingress into the plastic
package. Following any aqueous PCB cleaning process, bake the PCB assembly to remove moisture
introduced into the device packaging during the cleaning process. A low temperature, post cleaning bake at
85°C for 30 minutes is sufficient for most circumstances.
Power dissipated in the BUF634 causes the junction temperature to rise. A thermal protection circuit in the
BUF634 disables the output when the junction temperature reaches approximately 175°C. When the thermal
protection is activated, the output stage is disabled, allowing the device to cool. Quiescent current isapproximately 6 mA during thermal shutdown. When the junction temperature cools to approximately 165°C, theoutput circuitry is again enabled. The die overheating can cause the protection circuit to cycle on and off with a
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period ranging from a fraction of a second to several minutes or more, depending on package type, signal, load
and thermal environment.
The thermal protection circuit is designed to prevent damage during abnormal conditions. Any tendency toactivate the thermal protection circuit during normal operation is a sign of an inadequate heat sink or excessive
power dissipation for the package type.
The TO-220 package provides the best thermal performance. When the TO-220 is used with a properly sizedheat sink, output is not limited by thermal performance. The TO-263 also has excellent thermal characteristics;
for good heat dissipation, solder the mounting tab to a circuit board copper area. 図 8-8 shows typical thermal
resistance from junction to ambient as a function of the copper area. The mounting tab of the TO-220 and
TO-263 packages is electrically-connected to the V– power supply.
The DIP and SO-8 surface-mount packages are excellent for applications requiring high output current with low
average power dissipation. To achieve the best possible thermal performance with the DIP or SO-8 packages,
solder the device directly to a circuit board. Because much of the heat is dissipated by conduction through the
package pins, sockets degrade thermal performance. Use wide circuit board traces on all the device pins,
including pins that are not connected. With the DIP package, use traces on both sides of the printed circuit board
if possible.
THERMAL RESISTANCE vs
CIRCUIT BOARD COPPER AREA

Thermal Resistance, ΘJA (°C/W)

60

Circuit Board Copper Area
BUF634F
Surface Mount Package
1oz copper

50

40

30

20

BUF634F
Surface Mount Package

10
0

1

2

3

4

5

Copper Area (inches2)

図 8-8. Thermal Resistance vs Circuit Board Copper Area
8.4.1.1 Power Dissipation
Power dissipation depends on power supply voltage, signal, and load conditions. With dc signals, power
dissipation is equal to the product of output current times the voltage across the conducting output transistor, VS– VO. Power dissipation can be minimized by using the lowest possible power supply voltage necessary toprovide the required output voltage swing.
For resistive loads, the maximum power dissipation occurs at a dc output voltage of one-half the power supply
voltage. Dissipation with ac signals is lower. The Power Amplifier Stress And Power Handling Limitations
application bulletin explains how to calculate or measure power dissipation with unusual signals and loads.
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate
heat sink. For reliable operation, limit the junction temperature to 150°C, maximum. To estimate the margin ofsafety in a complete design, increase the ambient temperature until the thermal protection is triggered. The
thermal protection triggers more than 45°C greater than the maximum expected ambient condition of yourapplication.

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JAJSH51C – AUGUST 2000 – REVISED MARCH 2024

8.4.2 Layout Example

Optional: Use forwide bandwidth
applications
Place all passive
components close to
the device to reduceparasitic errors

VS+

Run the input trace
as far away fromthe supply lines
as possible

BW

BUF634 SOIC
Package

NC

NC

V+

VIN

VO

V±

NC

10 µF
GND

RS
VIN

OutputUse low-ESR, ceramic
bypass capacitor

10 µF

Use low-ESR,
ceramic bypass
capacitor

GND

VS±

Ground (GND) plane on another layer

図 8-9. BUF634 Layout Example

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JAJSH51C – AUGUST 2000 – REVISED MARCH 2024

9 Device and Documentation Support
9.1 Device Support
9.1.1 Development Support

9.1.1.1 TINA-TI™シミュレーション・ソフトウェア (無償ダウンロード)
TINA-TI™ シミュレーション・ソフトウェアは、SPICE エンジンをベースにした単純かつ強力な、使いやすい回路シミュレー
ション・プログラムです。TINA-TI シミュレーション・ソフトウェアは、TINA™ ソフトウェアのすべての機能を持つ無償バージ
ョンで、パッシブ・モデルとアクティブ・モデルに加えて、マクロモデルのライブラリがプリロードされています。TINA-TI シミ
ュレーション・ソフトウェアには、SPICE の標準的な DC 解析、過渡解析、周波数ドメイン解析などの全機能に加え、追加の設計機能が搭載されています。
TINA-TI シミュレーション・ソフトウェアは設計ツールとシミュレーション Web ページから無料でダウンロードでき、ユーザ
ーが結果をさまざまな方法でフォーマットできる、広範な後処理機能を備えています。仮想計測器により、入力波形を選択し、回路ノード、電圧、および波形をプローブして、動的なクイック・スタート・ツールを作成できます。
注
これらのファイルを使用するには、TINA ソフトウェアまたは TINA-TI ソフトウェアがインストールされている必要があります。TINA-TI™ ソフトウェア・フォルダから、無償の TINA-TI シミュレーション・ソフトウェアをダウンロー
ドしてください。
9.1.1.2 TI のリファレンス・デザイン
TI のリファレンス・デザインは、TI の高精度アナログ・アプリケーション専門家により作成されたアナログ・ソリューションです。TI のリファレンス・デザインは、動作原理、部品の選択、シミュレーション、完全な PCB 回路図およびレイアウト、部品表、測定済みの性能を提供します。TI のリファレンス・デザインは、http://www.ti.com/ww/en/analog/precision-designs/
からオンラインで入手できます。

9.2 Documentation Support
9.2.1 Related Documentation
For related documentation see the following:• Texas Instruments, Combining an Amplifier With the BUF634 application bulletin• Texas Instruments, Add Current Limit to the BUF634 application bulletin• Texas Instruments, Power Amplifier Stress and Power Handling Limitations application bulletin• Texas Instruments, Shelf-Life Evaluation of Lead-Free Component Finishes application report

9.3 ドキュメントの更新通知を受け取る方法
ドキュメントの更新についての通知を受け取るには、www.tij.co.jp のデバイス製品フォルダを開いてください。[通知] をクリックして登録すると、変更されたすべての製品情報に関するダイジェストを毎週受け取ることができます。 変更の詳細については、改訂されたドキュメントに含まれている改訂履歴をご覧ください。

9.4 サポート・リソース
テキサス・インスツルメンツ E2E™ サポート・フォーラムは、エンジニアが検証済みの回答と設計に関するヒントをエキスパートから迅速かつ直接得ることができる場所です。既存の回答を検索したり、独自の質問をしたりすることで、設計で必要な支援を迅速に得ることができます。
リンクされているコンテンツは、各寄稿者により「現状のまま」提供されるものです。これらはテキサス・インスツルメンツの仕様を構成するものではなく、必ずしもテキサス・インスツルメンツの見解を反映したものではありません。テキサス・インスツ
ルメンツの使用条件を参照してください。

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JAJSH51C – AUGUST 2000 – REVISED MARCH 2024

9.5 Trademarks
TINA-TI™ and テキサス・インスツルメンツ E2E™ are trademarks of Texas Instruments.
TINA™ is a trademark of DesignSoft, Inc.
すべての商標は、それぞれの所有者に帰属します。

9.6 静電気放電に関する注意事項

この IC は、ESD によって破損する可能性があります。テキサス・インスツルメンツは、IC を取り扱う際には常に適切な注意を払うことを推奨します。正しい取り扱いおよび設置手順に従わない場合、デバイスを破損するおそれがあります。
ESD による破損は、わずかな性能低下からデバイスの完全な故障まで多岐にわたります。精密な IC の場合、パラメータがわずかに変化するだけで公表されている仕様から外れる可能性があるため、破損が発生しやすくなっています。

9.7 用語集
テキサス・インスツルメンツ用語集

この用語集には、用語や略語の一覧および定義が記載されています。

10 Revision History
資料番号末尾の英字は改訂を表しています。その改訂履歴は英語版に準じています。
Changes from Revision B (March 2019) to Revision C (March 2024)
•
•
•
•
•
•
•
•

Changes from Revision A (November 2015) to Revision B (March 2019)
•
•
•

Page

「特長」および「概要」セクションに BUF634A アップグレード デバイスの説明を追加................................................ 1「任意のオペアンプの出力電流を増幅」図で、アンプを OPA2810 に変更し、表を削除........................................... 1
Added Device Comparison Table ...................................................................................................................... 2

Changes from Revision * (September 2000) to Revision A (April 2015)•

Page

データシートから PDIP パッケージを削除............................................................................................................. 1
データシートからほとんどの DDPAK の名称を削除し、TO-263 に置き換え............................................................ 1
BUF634 と BUF634A の比較の段落を削除..........................................................................................................1
Changed BUF634F to BUF634U for SOIC and PDIP packages in ESD Ratings ..............................................4
Changed values for D (SOIC) package in Thermal Information table................................................................ 4
Added Electrical Characteristics table specifically for TO‑220 and TO‑263 packages.......................................5
Added Typical Characteristics section specifically for TO-220 and TO-263 packages.......................................9
Added new block diagram for SOIC packages.................................................................................................18

Page「ESD 定格」表、「機能説明」セクション、「デバイスの機能モード」セクション、「アプリケーションと実装」セクション、「電源に関する推奨事項」セクション、「レイアウト」セクション、「デバイスおよびドキュメントのサポート」セクション、「メカニカ
ル、パッケージ、および注文情報」セクションを追加。..............................................................................................1

11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and revision ofthis document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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Product Folder Links: BUF634
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重要なお知らせと免責事項
テキサス・インスツルメンツは、技術データと信頼性データ (データシートを含みます)、設計リソース (リファレンス デザインを含みます)、アプリケーショ
ンや設計に関する各種アドバイス、Web ツール、安全性情報、その他のリソースを、欠陥が存在する可能性のある「現状のまま」提供しており、商品性および特定目的に対する適合性の黙示保証、第三者の知的財産権の非侵害保証を含むいかなる保証も、明示的または黙示的にかかわらず拒否します。
これらのリソースは、 テキサス・インスツルメンツ製品を使用する設計の経験を積んだ開発者への提供を意図したものです。(1) お客様のアプリケーションに適した テキサス・インスツルメンツ製品の選定、(2) お客様のアプリケーションの設計、検証、試験、(3) お客様のアプリケーションに該当する各種
規格や、その他のあらゆる安全性、セキュリティ、規制、または他の要件への確実な適合に関する責任を、お客様のみが単独で負うものとします。
上記の各種リソースは、予告なく変更される可能性があります。これらのリソースは、リソースで説明されている テキサス・インスツルメンツ製品を使用するアプリケーションの開発の目的でのみ、 テキサス・インスツルメンツはその使用をお客様に許諾します。これらのリソースに関して、他の目的で複製することや掲載することは禁止されています。 テキサス・インスツルメンツや第三者の知的財産権のライセンスが付与されている訳ではありません。お客様
は、これらのリソースを自身で使用した結果発生するあらゆる申し立て、損害、費用、損失、責任について、 テキサス・インスツルメンツおよびその代理人を完全に補償するものとし、 テキサス・インスツルメンツは一切の責任を拒否します。
テキサス・インスツルメンツの製品は、 テキサス・インスツルメンツの販売条件、または ti.com やかかる テキサス・インスツルメンツ製品の関連資料などのいずれかを通じて提供する適用可能な条項の下で提供されています。 テキサス・インスツルメンツがこれらのリソースを提供することは、適用される
テキサス・インスツルメンツの保証または他の保証の放棄の拡大や変更を意味するものではありません。
お客様がいかなる追加条項または代替条項を提案した場合でも、 テキサス・インスツルメンツはそれらに異議を唱え、拒否します。IMPORTANT
NOTICE
郵送先住所：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2024, Texas Instruments Incorporated

PACKAGE OPTION ADDENDUM
www.ti.com

8-Aug-2023

PACKAGING INFORMATION
Orderable Device

Status(1)

Package Type Package Pins Package
Drawing
Qty

Eco Plan(2)

Lead finish/
Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

(3)

(4/5)

(6)

BUF634F/500

NRND

DDPAK/
TO-263

KTT

5

500

RoHS & GreenSN

Level-2-260C-1 YEAR

-40 to 125

BUF634F

BUF634F/500E3

NRND

DDPAK/
TO-263

KTT

5

500

RoHS & GreenSN

Level-2-260C-1 YEAR

-40 to 125

BUF634F

BUF634FKTTTNRND

DDPAK/
TO-263

KTT

5

250

RoHS & GreenSN

Level-2-260C-1 YEAR

-40 to 125

BUF634F

BUF634FKTTTE3NRNDDDPAK/
TO-263

KTT

5

250

RoHS & GreenSN

Level-2-260C-1 YEAR

-40 to 125

BUF634F

BUF634T

NRND

TO-220KC

549

RoHS & Green

Call TI | SN

N / A for Pkg Type

-40 to 125

BUF634T

BUF634TG3

NRND

TO-220KC

549

RoHS & GreenSN

N / A for Pkg Type

-40 to 125

BUF634T

BUF634U

NRND

SOIC

D

8

75

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 125

BUF
634U

BUF634U/2K5

NRND

SOIC

D

8

2500

RoHS & Green

NIPDAU

Level-3-260C-168 HR-40 to 125

BUF
634U

(1)

The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)

RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)

MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

Addendum-Page 1

SamplesPACKAGE OPTION ADDENDUM
www.ti.com

8-Aug-2023(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.
(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to twolines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION
www.ti.com

8-Aug-2023

TAPE AND REEL INFORMATIONREEL DIMENSIONSTAPE DIMENSIONS
K0

P1

B0 W
Reel
DiameterCavity
A0
B0
K0
W
P1

A0

Dimension designed to accommodate the component width
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers

Reel Width (W1)QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes

Q1

Q2

Q1

Q2

Q3

Q4

Q3

Q4

User Direction of Feed

Pocket Quadrants*All dimensions are nominal

DeviceBUF634U/2K5

Package Package Pins
Type Drawing
SOIC

D

8

SPQ

Reel
Reel
A0
Diameter Width (mm)(mm) W1 (mm)

2500

330.0

12.4

Pack Materials-Page 1

6.4

B0
(mm)

K0
(mm)

P1
(mm)

W
Pin1
(mm) Quadrant

5.2

2.1

8.0

12.0

Q1

PACKAGE MATERIALS INFORMATION
www.ti.com

8-Aug-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)

W

L

H

*All dimensions are nominal

DevicePackage Type

Package Drawing

Pins

SPQ

Length (mm)Width (mm)Height (mm)

BUF634U/2K5

SOIC

D

8

2500

367.0

367.0

35.0

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION
www.ti.com

8-Aug-2023

TUBE
T - TubeheightL - Tube length

W - Tubewidth

B - Alignment groove width*All dimensions are nominal

DevicePackage Name

Package Type

Pins

SPQ

L (mm)W (mm)

T (µm)B (mm)

BUF634TKC

TO-220

5

49

546

31

11930

3.17

BUF634TG3KC

TO-220

5

49

546

31

11930

3.17

BUF634U

D

SOIC

8

75

506.6

8

3940

4.32

Pack Materials-Page 3

PACKAGE OUTLINE

D0008ASOIC - 1.75 mm max height
SCALE 2.800

SMALL OUTLINE INTEGRATED CIRCUITCSEATING PLANE.228-.244 TYP[5.80-6.19]
A.004 [0.1] C

PIN 1 ID AREA
6X .050[1.27]
8

1

2X
.150
[3.81].189-.197[4.81-5.00]
NOTE 3

4X (0 -15 )4
5
B

8X .012-.020[0.31-0.51].010 [0.25]
C A B.150-.157[3.81-3.98]
NOTE 4.069 MAX[1.75].005-.010 TYP[0.13-0.25]

4X (0 -15 )SEE DETAIL A.010[0.25].004-.010[0.11-0.25]

0 -8.016-.050[0.41-1.27]

DETAIL A(.041)[1.04]TYPICAL

4214825/C 02/2019

NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.

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EXAMPLE BOARD LAYOUT

D0008ASOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )[1.55]SYMM

SEE
DETAILS

1
8
8X (.024)[0.6]

6X (.050 )[1.27]

SYMM

5

4(R.002 ) TYP[0.05](.213)[5.4]

LAND PATTERN EXAMPLEEXPOSED METAL SHOWNSCALE:8X

METAL

SOLDER MASKOPENINGEXPOSED
METAL.0028 MAX
[0.07]ALL AROUNDSOLDER MASKOPENINGMETAL UNDERSOLDER MASKEXPOSED
METAL.0028 MIN
[0.07]ALL AROUNDSOLDER MASKDEFINEDNON SOLDER MASKDEFINEDSOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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EXAMPLE STENCIL DESIGN

D0008ASOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )[1.55]SYMM
1
88X (.024)[0.6]

6X (.050 )[1.27]

SYMM

5

4(R.002 ) TYP[0.05](.213)[5.4]

SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCILSCALE:8X

4214825/C 02/2019

NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

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PACKAGE OUTLINE

KC0005A

TO-220 - 16.51 mm max height
SCALE 0.850

TO-220

4.83
4.06
10.67
9.65

3.05
2.54

B
1.40
1.14

A

6.86
5.69
3.71-3.96

8.89
6.86

(6.275)
12.88
10.08

OPTIONAL
CHAMFER
16.51
MAX

2X (R1)OPTIONAL

9.25
7.67
C

(4.25)

PIN 1 ID
(OPTIONAL)NOTE 3

14.73
12.29

1
5X
0.25

5
0.61
0.30

1.02
0.64
C A B

3.05
2.03

4X 1.76.8

154215009/A 01/2017
NOTES:
1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are forreference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Shape may vary per different assembly sites.

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EXAMPLE BOARD LAYOUT

KC0005A

TO-220 - 16.51 mm max height
TO-220

4X (1.45)

PKG
0.07 MAXALL AROUND

0.07 MAXALL AROUND

METAL
TYP

(1.45)PKG(2)

4X (2)

1(R0.05) TYP
5X ( 1.2)

SOLDER MASKOPENING, TYP(1.7) TYP

5

FULL R
TYP(6.8)

LAND PATTERNNON-SOLDER MASK DEFINEDSCALE:12X

4215009/A 01/2017

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