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DesignOPA1652, OPA1654
SBOS477B – DECEMBER 2011 – REVISED DECEMBER 2016

OPA165x SoundPlus™ Low Noise and Distortion, General-Purpose, FET-Input
Audio Operational Amplifiers
1 Features

3 Description•

The OPA1652 (dual) and OPA1654 (quad) FET-input
operational amplifiers achieve a low 4.5-nV/√Hz noise
density with an ultra-low distortion of 0.00005% at 1
kHz. The OPA1652 and OPA1654 op amps offer railto-rail output swing to within 800 mV with a 2-kΩload, which increases headroom and maximizes
dynamic range. These devices also have a highoutput drive capability of ±30 mA.

1

•
•
•
•
•
•
•
•
•
•

Low Noise:
4.5 nV/√Hz at 1 kHz
3.8 nV/√Hz at 10 kHz
Low Distortion: 0.00005% at 1 kHz
Low Quiescent Current:
2 mA per Channel
Low Input Bias Current: 10 pA
Slew Rate: 10 V/μs
Wide Gain Bandwidth: 18 MHz (G = 1)
Unity-Gain Stable
Rail-to-Rail Output
Wide Supply Range:±2.25 V to ±18 V, or 4.5 V to 36 V
Dual and Quad Versions Available
Small Package Sizes:
Dual: SO-8 and MSOP-8
Quad: SO-14 and TSSOP-14

These devices operate over a very-wide-supply rangeof ±2.25 V to ±18 V, or 4.5 V to 36 V, on only 2 mA ofsupply current per channel. The OPA1652 andOPA1654 op amps are unity-gain stable and provide
excellent dynamic behavior over a wide range of loadconditions.
These devices also feature completely independentcircuitry for lowest crosstalk and freedom frominteractions between channels, even when overdriven
or overloaded.
The OPA1652 and OPA1654 temperature ranges are
specified from –40°C to +85°C.

2 Applications
•
•
•
•
•
•

SoundPlus™

Analog and Digital Mixers
Audio Effects Processors
Musical Instruments
A/V Receivers
DVD and Blu-Ray™ Players
Car Audio Systems

Device Information(1)PART NUMBER
OPA1652

OPA1654

PACKAGEBODY SIZE (NOM)

SOIC (8)4.90 mm × 3.91 mm

VSSOP (8)3.00 mm × 3.00 mm

WSON (8)3.00 mm × 3.00 mm

SOIC (14)8.65 mm × 3.91 mm

TSSOP (14)5.00 mm × 4.40 mm(1) For all available packages, see the orderable addendum atthe end of the data sheet.

Input Voltage Noise Spectral Density
9ROWDJH 1RLVH 6SHFWUDO 'HQVLW\ Q9 ¥+]

1000

100

10

1
1

10

100

1k

10k

Frequency (Hz)

100k

1M

10M
C006

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

OPA1652, OPA1654
SBOS477B – DECEMBER 2011 – REVISED DECEMBER 2016

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Table of Contents
1
2
3
4
5
6

Features .................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions ......................... 3
Specifications......................................................... 5
6.1
6.2
6.3
6.4
6.5
6.6
6.7

7

Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information: OPA1652 ................................ 6
Thermal Information: OPA1654 ................................ 6
Electrical Characteristics: VS = ±15 V....................... 7
Typical Characteristics .............................................. 8

Detailed Description ............................................ 14
7.1
7.2
7.3
7.4

Overview ................................................................. 14
Functional Block Diagram ....................................... 14
Feature Description................................................. 14
Device Functional Modes........................................ 17

8

Application and Implementation ........................ 18
8.1 Application Information............................................ 18
8.2 Typical Application .................................................. 21

9 Power Supply Recommendations...................... 24
10 Layout................................................................... 24
10.1 Layout Guidelines ................................................. 24
10.2 Layout Example .................................................... 25
10.3 Power Dissipation ................................................. 25

11 Device and Documentation Support ................. 26
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8

Device Support...................................................... 26
Documentation Support ........................................ 27
Related Links ........................................................ 27
Receiving Notification of Documentation Updates 27
Community Resource............................................ 27
Trademarks ........................................................... 27
Electrostatic Discharge Caution ............................ 27
Glossary ................................................................ 28

12 Mechanical, Packaging, and Orderable
Information ........................................................... 28

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (August 2016) to Revision B

Page

•

Added new SON (8) package and body size information to Device Information table .......................................................... 1•

Added new pinout drawing for OPA1652 DRG (WSON) package ........................................................................................ 3•

Added thermal information for the DRG (WSON) package in the Thermal Information table................................................ 6

2

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SBOS477B – DECEMBER 2011 – REVISED DECEMBER 2016

5 Pin Configuration and Functions
OPA1652 D and DGK Packages
8-Pin SOIC and VSSOPTop View

OPA1652 DRG Package
8-Pin WSON With Exposed Thermal Pad
Top View

OUT A

1

8

V+

±IN A

2

7

OUT B

+IN A

3

6

±IN B

V±

4

5

+IN B

OUT A

1

±IN A

2

+IN A

3

V±

4

Thermal
Pad

8

V+

7

OUT B

6

±IN B

5

+IN B

Not to scale
Not to scale

Pin Functions: OPA1652
PIN

I/O

DESCRIPTION

NAME

NO.

–IN A

2

I

Inverting input, channel A

+IN A

3

I

Noninverting input, channel A

–IN B

6

I

Inverting input, channel B

+IN B

5

I

Noninverting input, channel B

OUT A

1

O

Output, channel A

OUT B

7

O

Output, channel B

V–

4

—

Negative (lowest) power supply

V+

8

—

Positive (highest) power supply

Thermal pad——

Exposed thermal die pad on underside of DRG package; connect thermal die pad to V–.
Soldering the thermal pad improves heat dissipation and provides specified performance

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OPA1654 D and PW Packages
14-Pin SOIC and TSSOPTop View

OUT A

1

14

OUT D

±IN A

2

13

±IN D

+IN A

3

12

+IN D

V+

4

11

V±

+IN B

5

10

+IN C

±IN B

6

9

±IN C

OUT B

7

8

OUT C

Not to scale

Pin Functions: OPA1654
PIN

I/O

DESCRIPTION

NAME

NO.

–IN A

2

I

Inverting input, channel A

+IN A

3

I

Noninverting input, channel A

–IN B

6

I

Inverting input, channel B

+IN B

5

I

Noninverting input, channel B

–IN C

9

I

Inverting input, channel C

+IN D

10

I

Noninverting input, channel C

–IN D

13

I

Inverting input, channel D

+IN D

12

I

Noninverting input, channel D

OUT A

1

O

Output, channel A

OUT B

7

O

Output, channel B

OUT C

8

O

Output, channel C

OUT D

14

O

Output, channel D

V–

11

—

Negative (lowest) power supply

V+

4

—

Positive (highest) power supply

4

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SBOS477B – DECEMBER 2011 – REVISED DECEMBER 2016

6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
Voltage

InputV(V+) + 0.5

V

–10

10

mA

125

°C

200

°C

150

°C

Output short-circuit (2)Continuous

Operating, TA
Temperature–55

Junction, TJ
Storage, Tstg

(2)

UNIT

40
(V–) – 0.5

Input (all pins except power-supply pins)

Current(1)

MAX

Supply voltage, VS = (V+) – (V–)–65

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Short-circuit to VS / 2 (ground in symmetrical dual supply setups), one amplifier per package.

6.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)(1)(2)

Electrostatic discharge

(1)

UNIT

±2000

Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)±1000

Machine model (MM)

±200

V

JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
Supply voltage
TA

NOM

MAX

UNIT

4.5 (±2.25)

36 (±18)

V

–40

85

°C

Operating temperature

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6.4 Thermal Information: OPA1652
OPA1652
THERMAL METRIC(1)

D (SOIC)DGK(VSSOP)

DRG (WSON)

8 PINS

8 PINS

8 PINS

UNIT

RθJA

Junction-to-ambient thermal resistance

143.6

218.9

66.9

°C/W

RθJC(top)

Junction-to-case (top) thermal resistance

76.9

78.6

54.5

°C/W

RθJB

Junction-to-board thermal resistance

61.8

103.7

40.4

°C/W

ψJT

Junction-to-top characterization parameter

27.8

14.6

1.9

°C/W

ψJB

Junction-to-board characterization parameter

61.3

101.8

40.4

°C/W

RθJC(bot)

Junction-to-case (bottom) thermal resistance

N/A

N/A

10.8

°C/W

(1)

For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

6.5 Thermal Information: OPA1654
OPA1654
THERMAL METRIC (1)

D (SOIC)PW (TSSOP)

14 PINS

14 PINS

UNIT

RθJA

Junction-to-ambient thermal resistance

90.1

126.9

°C/W

RθJC(top)

Junction-to-case (top) thermal resistance

54.8

46.6

°C/W

RθJB

Junction-to-board thermal resistance

44.4

58.6

°C/W

ψJT

Junction-to-top characterization parameter

19.9

5.5

°C/W

ψJB

Junction-to-board characterization parameter

44.2

57.8

°C/W

RθJC(bot)

Junction-to-case (bottom) thermal resistance

N/A

N/A

°C/W

(1)

6

For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

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SBOS477B – DECEMBER 2011 – REVISED DECEMBER 2016

6.6 Electrical Characteristics: VS = ±15 V
at TA = 25°C, RL = 2 kΩ, and VCM = VOUT = midsupply, unless otherwise noted
PARAMETERTEST CONDITIONS

MIN

TYP

MAX

UNIT

AUDIO PERFORMANCE
THD + N

IMD

Total harmonic distortion + noiseIntermodulation distortion

0.00005%
G = 1, f = 1 kHz, VO = 3 VRMS

G = 1,VO = 3 VRMS–126

SMPTE and DIN Two-Tone, 4:1(60 Hz and 7 kHz)

0.00005%

DIM 30 (3-kHz square wave
and 15-kHz sine wave)

0.00005%

CCIF Twin-Tone(19 kHz and 20 kHz)

0.00005%

dB

–126

dB

–126

dB

–126

dB

MHz

FREQUENCY RESPONSE
GBW

Gain-bandwidth product

G=1

18

SR

Slew rate

G = –110

V/µs

Full power bandwidth (1)VO = 1 VP

1.6

MHz

Overload recovery timeG = –101µsChannel separation (dual and quad)f = 1 kHz

–120

dB

Input voltage noisef = 20 Hz to 20 kHz

4.0

µVPP

f = 1 kHz

4.5

nV/√Hzf = 10 kHz

3.8

nV/√Hzf = 1 kHz

3

fA/√HzNOISE
en

Input voltage noise density
In

Input current noise density

OFFSET VOLTAGE
VOS

Input offset voltage

PSRR

Power-supply rejection ratio

VS = ±2.25 V to ±18 V

±0.5

±1.5

mV

VS = ±2.25 V to ±18 V, TA = –40°C to 85°C (2)

2

8

µV/°C

VS = ±2..25 V to ±18 V

3

8

µV/V

INPUT BIAS CURRENT
IB

Input bias current

VCM = 0 V

±10

±100

pA

IOS

Input offset current

VCM = 0 V

±10

±100

pA

INPUT VOLTAGE RANGE
VCMCommon-mode voltage range(V–) + 0.5

CMRR

Common-mode rejection ratio

100(V+) – 2

V

110

dB

INPUT IMPEDANCE
Differential

100 || 6

MΩ || pF

Common-mode

6000 || 2

GΩ || pF

OPEN-LOOP GAIN
Open-loop voltage gain(V–) + 0.8 V ≤ VO ≤ (V+) – 0.8 V, RL = 2 kΩVOUTVoltage output

RL = 2 kΩ

IOUT

Output current

ZO

Open-loop output impedance

ISC

Short-circuit current (3)

±50

mA

CLOAD

Capacitive load drive

100

pF

AOL

106

114

dB

OUTPUT(V–) + 0.8(V+) – 0.8

See Typical Characteristics
f = 1 MHzV
mA

See Typical Characteristics

Ω

POWER SUPPLYVS
IQ

Specified voltage
Quiescent current(per channel)±2.25
IOUT = 0 A

2

IOUT = 0 A, TA = –40°C to 85°C (2)

±18

V

2.5

mA

2.8

mA

TEMPERATURE

(1)
(2)
(3)

Specified range

–40

85

°C

Operating range

–55

125

°C

Full-power bandwidth = SR / (2π × VP), where SR = slew rate.
Specified by design and characterization.
One channel at a time.

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6.7 Typical Characteristics
at TA = 25°C, VS = ±15 V, and RL = 2 kΩ, unless otherwise noted.

Voltage Noise (500 nV/div)

9ROWDJH 1RLVH 6SHFWUDO 'HQVLW\ Q9 ¥+]

1000

100

10

1
1

10

100

1k

10k

100k

1M

10M

Frequency (Hz)Time (1 s/div)

C006

Figure 2. 0.1-Hz to 10-Hz Noise

Figure 1. Input Voltage Noise Density vs Frequency
20

10k
E2o = e2n + (inRS)2 + 4KTRS

18

RS

Output Voltage (V)Voltage Noise (nV/ Hz)

EO

1k

G002

OPA166x100
OPA165x10VS = ± 15 V

15
12
10
8
5

VS = ± 2.25 V

2Resistor Noise
1
100

1k

10k

100k

0
10k

1M

Source Resistance (W)

Gain
Phase

120

Gain = −1 V/V
Gain = +1 V/V
Gain = +10 V/V

90

60
40

0

45

20

20
Gain (dB)80

Phase (°)

135

100

G004

40

180

140

10M

Figure 4. Maximum Output Voltage vs Frequency

Figure 3. Voltage Noise vs Source ResistanceGain (dB)

100k
1M
Frequency (Hz)G003

0
CL = 10 pF
−20

10

100

1k

10k
100k
Frequency (Hz)

1M

10M

0
100M
G005

CL = 10 pF
−20
100k

1M

10M
Frequency (Hz)Figure 5. Gain and Phase vs Frequency

8

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100M
G006

Figure 6. Closed-Loop Gain vs Frequency

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Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, and RL = 2 kΩ, unless otherwise noted.
0.01

G = 10 V/V, RL = 600 Ω
G = 10 V/V, RL = 2 kΩ
G = +1 V/V, RL = 600 Ω
G = +1 V/V, RL = 2 kΩ
G = −1 V/V, RL = 600 Ω
G = −1 V/V, RL = 2 kΩ

0.001

VOUT = 3 VRMS
BW = 80 kHz

+15V

-15V

0.00010.00001

0.001

20

100

1k
Frequency (Hz)10k

0.0000120k

20

G = 10 V/V, RL = 600 Ω
G = 10 V/V, RL = 2 kΩ
G = +1 V/V, RL = 600 Ω
G = +1 V/V, RL = 2 kΩ
G = −1 V/V, RL = 600 Ω
G = −1 V/V, RL = 2 kΩ

0.001

100

10k

20k
G008

Figure 8. THD+N Ratio vs Frequency
0.01

VOUT = 3 VRMS
BW = 500 kHz

VOUT = 3 VRMS
BW = 500 kHz+15V

RS = 0 W
RS = 30 W
RS = 60 W
RS = 1 kW

RSOURCE OPA1652-15V

THD+N (%)

THD+N (%)

1k
Frequency (Hz)

RL

G007

Figure 7. THD+N Ratio vs Frequency

0.00010.001

RL

0.000120100

1kFrequency (Hz)10k

0.00001

100k

20

100

G009

Figure 9. THD+N Ratio vs Frequency

1kFrequency (Hz)

10k

100k
G010

Figure 10. THD+N Ratio vs Frequency

0.01

0.01
DIM 30: 3 kHz − Square Wave, 15 kHz Sine Wave
CCIF Twin Tone: 19 kHz and 20 kHz
SMPTE / DIN: Two −Tone 4:1, 60 Hz and 7 KHz

f = 1 kHzBW = 80 kHz
RS = 0 Ω
0.001

THD+N (%)

THD+N (%)

RS = 0 W
RS = 30 W
RS = 60 W
RS = 1 kW

0.00010.01

0.00001

VOUT = 3 VRMS
BW = 80 kHz

RSOURCE OPA1652

THD+N (%)

THD+N (%)

0.01

G = 10 V/V, RL = 600 Ω
G = 10 V/V, RL = 2 kΩ
G = +1 V/V, RL = 600 Ω
G = +1 V/V, RL = 2 kΩ
G = −1 V/V, RL = 600 Ω
G = −1 V/V, RL = 2 kΩ

0.00010.00001
1m

10m

0.001

0.0001100m
1Output Amplitude (Vrms)

10 20

Figure 11. THD+N Ratio vs Output Amplitude

G = +1 V/V
0.00001
100m

G011

1
Output Amplitude (Vrms)

10

20
G012

Figure 12. Intermodulation Distortion vs Output Amplitude

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Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, and RL = 2 kΩ, unless otherwise noted.
140−80
VOUT = 3 VRMS
Gain = +1 V/V

120
CMRR, PSRR (dB)

Crosstalk (dB)

−100

−120

−140

−160
100

1k

10k

100
80
60
40

100k

Frequency (Hz)

0
100

1k

10k

100k
1M
Frequency (Hz)

10M

100M
G014

Figure 14. CMRR and PSRR vs Frequency(Referred to Input)
VIN
VOUT

Voltage (25 mV/div)

Voltage (25 mV/div)

VIN
VOUT

G = −1 V/V
CL = 100 pF

G = +1 V/V
CL = 100 pF
Time (0.2 ms/div)

Time (0.2 ms/div)

G015

Figure 15. Small-Signal Step Response (100 mV)

VIN
VOUT

G = −1 V/V
CL = 100 pF

Voltage (2.5 V/div)

G = + 1V/V
RF = 2 kW
CL = 100 pF

Time (1 ms/div)

Time (1 ms/div)

G017

Figure 17. Large-Signal Step Response

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G016

Figure 16. Small-Signal Step Response (100 mV)

VIN
VOUT

Voltage (2.5 V/div)

+PSRR
−PSRR
CMRR

G013

Figure 13. Channel Separation vs Frequency

10

20

G018

Figure 18. Large-Signal Step Response

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Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, and RL = 2 kΩ, unless otherwise noted.
50

40

+15 V

35

RS
OPA1652

30
VOUT = 100 mVPP
G = +1 V/V

25
20

RL

-15 V

CL

-15 V

25

5
300

350

VOUT = 100 mVPP
G = −1 V/V

20

10

150
200
250
Capacitance (pF)

CL

30

5
100

RS
OPA1652

15

50

+15 V

35

10

0

RS = 0 W
RS = 25 W
RS = 50 W

RF = 2 kW

40

15

0

RI = 2 kW

45

Overshoot (%)

Overshoot (%)

50

RS = 0 W
RS = 25 W
RS = 50 W

45

0

400

0

50

100

150
200
250
Capacitance (pF)

G019

Figure 19. Small-Signal Overshoot vs Capacitive Load

300

350

400
G020

Figure 20. Small-Signal Overshoot vs Capacitive Load
425
VOUT = 100 mVPP
G = −1 V/V
RS = 0 W

20

CF
RI = 2 kW

RF = 2 kW

3RS

OPA1652

15

AOL (µV)

Overshoot (%)

+15 V

CL
-15 V

10

2

1

5

0

0

−1
−40

RL = 2 kΩ

0

1

2
3
Capacitance (pF)

4

5
G021

1200

85

110

135
G022

Ibp
Ibn
Ios

6

0
−400
−800
−1200
−1600
−2000
−40

35
60
Temperature (°C)

8
Ibn
Ibp
Ios

Ib and Ios Current (pA)

Ib and Ios Current (pA)

400

10

Figure 22. Open-Loop Gain vs Temperature

Figure 21. Small-Signal Overshoot vs Feedback Capacitor(100-mV Output Step)

800

−15

4
2
0
−2
−4
−6

−15

10

35
60
Temperature (°C)

85

110

135
G023

Figure 23. IB and IOS vs Temperature−8−18 −15 −12 −9 −6 −3 0369Common − Mode Voltage (V)

12

15

18
G024

Figure 24. IB and IOS vs Common-Mode Voltage

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Typical Characteristics (continued)
3

3

2.5

2.5
Supply Current (mA)

Supply Current (mA)at TA = 25°C, VS = ±15 V, and RL = 2 kΩ, unless otherwise noted.

2
1.5
1

2
1.5
1

0.5

0.5

0
−40

−15

10

35
60
Temperature (°C)

85

110

0

135

30

80

8

12
16
20
24
Supply Voltage (V)

0
−40 C
−25 C
0C
25 C
85 C
125 C

−10
−20
−30

36
G026

+Isc
−Isc

0

5

10

15

20 25 30 35 40
Output Current (mA)

45

50

55

20
0
−20
−40
−60
−80

60

−100
−40

−15

10

G029

Figure 27. Output Voltage vs Output Current

3560
Temperature (°C)

85

110

135
G028

Figure 28. Short-Circuit Current vs Temperature

9050
G = +1 V/V80

G = +1 V/V
VIN = 100 mVPP
40

70
Overshoot (%)

60
50
40
30
20

30

20

10

VS = ± 2.25 V
VS = ± 18 V

10
0

50

100

150
200
250
Capacitance (pF)

300

350

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400

0

0

50

G031

Figure 29. Phase Margin vs Capacitive Load

12

32

40

10

0

28

60

20

Phase Margin (°)

4

Figure 26. Supply Current vs Supply Voltage
100

Isc (mA)

Output Volage Swing (V)Figure 25. Supply Current vs Temperature
40

−40

0

G025

100

150
200
250
Capacitance (pF)

300

350

400
G032

Figure 30. Percent Overshoot vs Capacitive Load

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Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, and RL = 2 kΩ, unless otherwise noted.
20 kW

VIN
VOUT

2 kW

20 kW
+18 V

2 kW

+18 V
VOUT

OPA1652

Output Voltage (5 V/div)

Output Voltage (5 V/div)

G = −10 V/V

VIN
-18 V

G = -10
VIN
VOUT

VOUT

OPA1652
VIN-18 V

G = −10 V/V

G = -10
Time (0.4 ms/div)

Time (0.4 ms/div)

G033

Figure 31. Negative Overload Recovery

Figure 32. Positive Overload Recovery

1k

20
+18 V

15

Voltage (V)10
Impedance (Ω)

G027

100

5

G = +1 V/V

OPA1652

-18 V
37VPP
Sine Wave(±18.5 V)

0
−5
−10
VIN
VOUT

−15
10

10

100

1k

10k
100k
Frequency (Hz)

1M

10M

100M

−20

G030

Figure 33. Open-Loop Output Impedance vs Frequency

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Time (125 ms/div)

G034

Figure 34. No Phase Reversal

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7 Detailed Description
7.1 Overview
The OPA1652 and OPA1654 are unity-gain stable, precision dual and quad op amps with very low noise. The
Functional Block Diagram shows a simplified schematic of the OPA165x (with one channel shown). The device
consists of a very low noise input stage with a folded cascode and a rail-to-rail output stage. This topology
exhibits superior noise and distortion performance across a wide range of supply voltages not previously
delivered by audio operational amplifiers.

7.2 Functional Block Diagram
V+
Tail
Current
VBIAS1
VIN+
Class AB
Control
CircuitryVO

VINVBIAS2

VCopyright © 2016, Texas Instruments Incorporated

7.3 Feature Description
7.3.1 Phase Reversal Protection
The OPA165x family has internal phase-reversal protection. Many op amps exhibit phase reversal when the
input is driven beyond the linear common-mode range. This condition is most often encountered in noninverting
circuits when the input is driven beyond the specified common-mode voltage range, causing the output toreverse into the opposite rail. The input of the OPA165x prevents phase reversal with excessive common-mode
voltage. Instead, the appropriate rail limits the output voltage. This performance is shown in Figure 35.
20
+18 V

15

Voltage (V)105

G = +1 V/V

OPA1652

-18 V
37VPP
Sine Wave(±18.5 V)

0
−5
−10
VIN
VOUT

−15
−20
Time (125 ms/div)

G034

Figure 35. Output Waveform Devoid of Phase Reversal During an Input Overdrive Condition

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Feature Description (continued)
7.3.2 Input Protection
The input terminals of the OPA1652 and OPA1654 are protected from excessive differential voltage with back-toback diodes, as Figure 36 illustrates. In most circuit applications, the input protection circuitry has noconsequence. However, in low-gain or G = 1 circuits, fast ramping input signals can forward bias these diodes
because the output of the amplifier cannot respond rapidly enough to the input ramp. If the input signal is fastenough to create this forward bias condition, the input signal current must be limited to 10 mA or less. If the input
signal current is not inherently limited, an input series resistor (RI) or a feedback resistor (RF) can limit the signal
input current. This resistor degrades the low-noise performance of the OPA165x, and is examined in the Noise
Performance section. Figure 36 shows an example configuration when both current-limiting input and feedback
resistors are used.
RF-

OPA165x
RI
Input

Output+Copyright © 2016, Texas Instruments Incorporated

Figure 36. Pulsed Operation
7.3.3 Electrical Overstress
Designers typically ask questions about the capability of an operational amplifier to withstand electricaloverstress. These questions tend to focus on the device inputs, but can involve the supply voltage pins or the
output pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from
accidental ESD events both before and during product assembly.
A good understanding of this basic ESD circuitry and the relevance to an electrical overstress event is helpful.
Figure 37 illustrates the ESD circuits contained in the OPA165x (indicated by the dashed line area). The ESD
protection circuitry involves several current-steering diodes connected from the input and output pins and routed
back to the internal power-supply lines, where the diodes meet at an absorption device internal to the operational
amplifier. This protection circuitry is intended to remain inactive during normal circuit operation.

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Feature Description (continued)
TVS

+
±

RF

+VS

R1

IN±

250 Ÿ

RS

IN+

250 Ÿ

+
Power-Supply
ESD Cell

ID

VIN

RL

+
±

+
±
±VS

TVS
Copyright © 2016, Texas Instruments Incorporated

Figure 37. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application
An ESD event produces a short-duration, high-voltage pulse that is transformed into a short-duration, highcurrent pulse when discharging through a semiconductor device. The ESD protection circuits are designed toprovide a current path around the operational amplifier core to prevent damage. The energy absorbed by theprotection circuitry is then dissipated as heat.
When an ESD voltage develops across two or more amplifier device pins, current flows through one or more
steering diodes. The absorption device activates depending on the path that the current takes. The absorption
device has a trigger, or threshold voltage, that is above the normal operating voltage of the OPA165x, but below
the device breakdown voltage level. When this threshold is exceeded, the absorption device quickly activatesand clamps the voltage across the supply rails to a safe level.
When the operational amplifier connects into a circuit (refer to Figure 37), the ESD protection components areintended to remain inactive and do not become involved in the application circuit operation. However,circumstances may arise where an applied voltage exceeds the operating voltage range of a given pin. If thiscondition occurs, there is a risk that some internal ESD protection circuits can turn on and conduct current. Anysuch current flow occurs through steering-diode paths and rarely involves the absorption device.
Figure 37 shows a specific example where the input voltage (VIN) exceeds the positive supply voltage (V+) by
500 mV or more. Much of what happens in the circuit depends on the supply characteristics. If V+ can sink thecurrent, one of the upper input steering diodes conducts and directs current to V+. Excessively high current
levels can flow with increasingly higher VIN. As a result, the data sheet specifications recommend thatapplications limit the input current to 10 mA.
If the supply is not capable of sinking the current, VIN begins sourcing current to the operational amplifier, andthen becomes the source of positive supply voltage. The danger in this case is that the voltage can rise to levels
that exceed the absolute maximum ratings of the operational amplifier.

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Feature Description (continued)
Another common question explains what happens to the amplifier if an input signal is applied to the input when
the power supplies (V+ or V–) are at 0 V. This depends on the supply characteristic when at 0 V, or at a level
below the input signal amplitude. If the supplies appear as high impedance, then the input source supplies theoperational amplifier current through the current-steering diodes. This state is not a normal bias condition; most
likely, the amplifier does not operate normally. If the supplies are at low impedance, then the current through thesteering diodes can become quite high. The current level depends on the ability of the input source to delivercurrent, and any resistance in the input path.
If there is any uncertainty about the ability of the supply to absorb this current, add external Zener diodes to the
supply pins; see Figure 37. Select the Zener voltage so the diode does not turn on during normal operation.
However, the Zener voltage must be low enough so that the Zener diode conducts if the supply pin rises above
the safe-operating, supply-voltage level.

7.4 Device Functional Modes
7.4.1 Operating Voltage
The OPA165x series op amps operate from ±2.25 V to ±18 V supplies while maintaining excellent performance.
The OPA165x series can operate with as little as 4.5 V between the supplies and with up to 36 V between the
supplies. However, some applications do not require equal positive and negative output voltage swing. With the
OPA165x series, power-supply voltages do not need to be equal. For example, the positive supply can be set to
25 V with the negative supply at –5 V.
In all cases, the common-mode voltage must be maintained within the specified range. In addition, key
parameters are assured over the specified temperature range of TA = –40°C to +85°C. Parameters that varysignificantly with operating voltage or temperature are shown in the Typical Characteristics section.

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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

8.1 Application Information
8.1.1 Noise Performance
Figure 38 shows the total circuit noise for varying source impedances with the op amp in a unity-gain
configuration (no feedback resistor network, and therefore no additional noise contributions).
The OPA165x ( Gain bandwidth = 18 MHz, G = 1) is shown with total circuit noise calculated. The op amp
contributes a voltage noise component and a current noise component. The voltage noise is commonly modeled
as a time-varying component of the offset voltage. The current noise is modeled as the time-varying componentof the input bias current, and reacts with the source resistance to create a voltage component of noise.
Therefore, the lowest noise op amp for a given application depends on the source impedance. For low source
impedance, current noise is negligible, and voltage noise typically dominates the total noise of the circuit. The
voltage noise of the OPA165x series op amps makes the series a suitable choice for source impedances greaterthan or equal to 1-kΩ.
The equation in Figure 38 shows the calculation of the total circuit noise, with these parameters:• en = Voltage noise• in = Current noise• RS = Source impedance• k = Boltzmann’s constant = 1.38 × 10–23 J/K• T = Temperature in Kelvins (K)10k

Voltage Noise (nV/ Hz )E2o = e2n + (inRS)2 + 4KTRS
1k
OPA166X
100
OPA165X
10

Resistor Noise
1
100

1k

10k

100k

1M

Source Resistance (Ω)

G003

Figure 38. Noise Performance of the OPA165x in Unity-Gain Buffer Configuration
Design of low-noise op amp circuits requires careful consideration of a variety of possible noise contributors:
noise from the signal source, noise generated in the op amp, and noise from the feedback network resistors. The
total noise of the circuit is the root-sum-square combination of all noise components.
The resistive portion of the source impedance produces thermal noise proportional to the square root of theresistance. Figure 38 plots this equation. The source impedance is typically fixed; consequently, select the op
amp and the feedback resistors to minimize the respective contributions to the total noise.

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Application Information (continued)
Figure 39 illustrates both inverting (Figure 39 B) and noninverting (Figure 39 A) op amp circuit configurations withgain. In circuit configurations with gain, the feedback network resistors contribute noise. The current noise of theop amp reacts with the feedback resistors, creating additional noise components. The feedback resistor values
can generally be selected to make these noise sources negligible. The equations for total noise are shown forboth configurations.
Noise at the output:A) Noise in Noninverting Gain Configuration
R2

2
2
O

E

R1

R2

= 1+

R1

2
2

en +

R2

2
2

R1

2

e1 + e2 + 1 +

R2
R1

es2

EO

RS

Where eS =4kTRS = thermal noise of RSe1 =4kTR1 = thermal noise of R1e2 =4kTR2 = thermal noise of R2

VS

Noise at the output:B) Noise in Inverting Gain Configuration
R2

2

R2

2

EO = 1 +R1RS

R 1 + RS

en2 +

2

R2
R1 + RSe12 + e22 +2R2
R1 + RS

es2

EO

VS

Where eS =4kTRS = thermal noise of RSe1 =4kTR1 = thermal noise of R1e2 =4kTR2 = thermal noise of R2
Copyright © 2016, Texas Instruments Incorporated

Note:

For the OPA165x series of op amps at 1 kHz, en = 4.5 nV/√Hz.

Figure 39. Noise Calculation in Gain Configurations
8.1.2 Total Harmonic Distortion Measurements
The OPA165x series op amps have excellent distortion characteristics. THD + noise is below 0.0002% (G = 1,
VO = 3 VRMS, bandwidth = 80 kHz) throughout the audio frequency range, 20 Hz to 20 kHz, with a 2-kΩ load (seeFigure 7 for characteristic performance).
The distortion produced by the OPA165x series op amps is below the measurement limit of many commerciallyavailable distortion analyzers. However, a special test circuit (such as Figure 40 shows) can extend themeasurement capabilities.
Op amp distortion can be considered an internal error source that refers to the input. Figure 40 shows a circuitthat causes the op amp distortion to be gained up (refer to the table in Figure 40 for the distortion gain factor forvarious signal gains). The addition of R3 to the otherwise standard noninverting amplifier, configuration alters the
feedback factor or noise gain of the circuit. The closed-loop gain is unchanged, but the distortion gain factor
reduces the feedback available for error connection, that extends the resolution by the same amount. Note thatthe input signal and load applied to the op amp are the same as with conventional feedback without R3. The
value of R3 must be kept small to minimize the effect on the distortion measurements.
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Application Information (continued)
The validity of this technique can be verified by duplicating measurements at high gain or high frequency where
the distortion is within the measurement capability of the test equipment. The Audio Precision System Two
distortion and noise analyzer calculated the measurements for this data sheet, which significantly simplifies
repetitive measurements. Manual distortion measurement instruments performs this measurement technique.
R1

R2

SIGNAL DISTORTION
GAIN
GAIN
R3

OPA165xVO = 3 VRMS

R
Signal Gain = 1+ 2
R1
Distortion Gain = 1+

R2
R1 II R3

Generator
Output

R1

R2

R3

¥

1 kW

10 W

+1

101

-1

101

4.99 kW 4.99 kW 49.9 W

+10

110

549 W 4.99 kW 49.9 W

Analyzer
Input

Audio Precision
System Two(1)with PC Controller

Load

Copyright © 2016, Texas Instruments Incorporated(1) For measurement bandwidth, see Figure 7 through Figure 12.

Figure 40. Distortion Test Circuit
8.1.3 Capacitive Loads
The dynamic characteristics of the OPA1652 and OPA1654 are optimized for commonly encountered gains,loads, and operating conditions. The combination of low closed-loop gain and high capacitive loads decreases
the phase margin of the amplifier and can lead to gain peaking or oscillations. As a result, heavier capacitive
loads must be isolated from the output. The simplest way to achieve this isolation is to add a small resistor (RSequal to 50 Ω, for example) in series with the output.
This small series resistor also prevents excess power dissipation if the output of the device becomes shorted.
Figure 19 illustrates a graph of Small-Signal Overshoot vs Capacitive Load for several values of RS. For moredetails about analysis techniques and application circuits, see Feedback Plots Define Op Amp AC Performance(SBOA015), available for download from the TI website (www.ti.com).

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8.2 Typical Application
The low noise and distortion of the OPA165x family of audio operational amplifiers make them an excellent
choice for a number of analog audio circuits. Figure 41 illustrates a power amplifier circuit suitable for high-fidelity
headphone applications.
+12 V

100 F
0.1 F
CBULK
0.1 F

CBYP

CBYP
+

Input
RIN

±

100 k

OPA1652

BUF634

Output

0.1 F
RBW

0.1 F

CBYP
100 F

CBYP

CBULK

-12V
R1

R2

200

200

Copyright © 2016, Texas Instruments Incorporated

Figure 41. Composite Power Amplifier for Headphones
8.2.1 Design Requirements••••

Gain: 6 dB
Output Voltage: > 2 VRMS, 32-Ω Load
Output Impedance: < 1 Ω
THD+N: < –110dB (1 kHz, 2 VRMS, 32-Ω Load)

8.2.2 Detailed Design Procedure
The power amplifier circuit (single channel shown) features a BUF634 high-speed buffer amplifier inside thefeedback loop of an OPA1652 to increase the amount of available output current. The bandwidth and power
consumption of the BUF634 can be set with an external resistor (RBW). For this circuit, RBW uses a 0-Ω resistor
that configures the BUF634 for the widest bandwidth and highest performance. Feedback resistors R1 and R2 (asshown in Equation 1) calculate the gain of the circuit:
R2
AV 1
R1
(1)
To achieve the design goal of a 6-dB voltage gain (2 V/V), R1 and R2 must have equal values. These resistors
also contribute noise thermal noise to the circuit. The voltage noise spectral density of the feedback resistors,
referred to the amplifier input, is given in Equation 2:

eNR

4kT R2 || R1(2)

Ideally, the thermal noise contributions of the resistors do not significantly degrade the noise performance of thecircuit. Selecting resistor values so the resistor noise is less than one-third the input voltage noise of the op amp(Equation 3) ensures that any increase in the circuit noise as a result of the feedback resistor contributions is
minimal.

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Typical Application (continued)
eNR d

eOA
3

(3)

To calculate the required resistor values, Equation 3 is inserted into Equation 2, and the resulting equation isrearranged to solve for the parallel combination of R1 and R2 , as shown in Equation 4. Using a value of 3.8
nV/√Hz as the broadband voltage noise of the OPA1652 results in a value of 96.8 Ω for the parallel combinationof R1 and R2. R1 and R2 use standard value 200-Ω resistors, resulting in a parallel value of 100 Ω, which issuitably close to the required value.
2

3.8 nV/ Hz
e 2
R1||R2 d OA dd 96.836kT 36×1.381×10-23 ×300

(4)

Because of the extremely wide bandwidth and high slew rate of the BUF634, no additional components are
required to maintain stability in the circuit or prevent latch-up conditions. This circuit is stable with capacitive
loads over 1-nF, which is suitable for headphone applications.
8.2.3 Application Curves

Total Harmonic Distortion + Noise (dB)

6.2
6.15

Gain (dB)

6.1
6.05
6
5.95
5.9
No Load

5.85

32-

5.8
10

100

1k

Load

10k

Frequency (Hz)

0.1

±60
±70

0.01

±80
±90

0.001

±100
±110
±120
±130
±140
0.001

16-

Load

32-

Load

128-

Load

250-

Load

0.01

0.00010.000010.1

110Output Voltage (VRMS)

C005

Total Harmonic Distortion + Noise (%)

The measured performance of the circuit is shown in Figure 42 through Figure 46. The frequency response isextremely flat over the full audio bandwidth, deviating only 0.004 dB over the audible range. The decrease ingain shown at low frequency is a result of the test equipment, and not the amplifier circuit. The amplifier output
impedance, calculated from the change in gain in the loaded and unloaded conditions, is 0.036 Ω. The maximum
output power (before clipping) is displayed in Figure 43. For a 32-Ω load, the power amplifier delivered 781 mW
before clipping. The best THD+N performance achieved with a 32-Ω load was –117.2 dB at 678 mW (1 kHz, 22kHz measurement bandwidth). THD+N vs frequency is shown in Figure 44 for a 2-VRMS output level measured ina 90-kHz bandwidth. The worst-case measurement was for a 16-Ω load (250 mW), 20-kHz input frequency,–91.8 dB (0.0026%). The amplifier output spectrum for a 2-VRMS, 1 kHz, fundamental into two different loads isshown in Figure 45 and Figure 46. All distortion harmonics are below –120 dB relative to the fundamental forboth loading conditions.

C007

22-kHz measurement bandwidth, 1-kHz output
Figure 42. Amplifier Transfer Function

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Figure 43. THD+N vs Frequency for Various Loads

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±70
±80

16-

Load

32-

Load

128-

Load

250-

Load

0

0.1

0.01

±90
0.001

±100
±110

±20
±40
Amplitude (dBc)±60

Total Harmonic Distortion + Noise (%)

Total Harmonic Distortion + Noise (dB)

Typical Application (continued)

10

100

1k
Frequency (Hz)

±80
±100
±120
±140
±160

0.0001

±120

±60

±180

10k

0

5k

10k

15k

Frequency (Hz)C002

90-kHz measurement bandwidth, 2-VRMS output

20k
C003

1 kHz, 32-Ω load, 2-VRMS output

Figure 44. THD+N vs Frequency for Various Loads

Figure 45. Output Spectrum

0±20

Amplitude (dBc)

±40
±60
±80
±100
±120
±140
±160
±180
0

5k

10k

15k

Frequency (Hz)

20k
C004

1 kHz, 250-Ω load, 2 VRMS
Figure 46. Output Spectrum

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9 Power Supply Recommendations
The OPA165x series is specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V); many specifications apply
from –40°C to +85°C. Parameters that can exhibit significant variance with regard to operating voltage ortemperature are presented in the Typical Characteristics section. Applications with noisy or high-impedance
power supplies require decoupling capacitors close to the device pins. In most cases, 0.1-µF capacitors areadequate.

10 Layout10.1 Layout Guidelines
For best operational performance of the device, use good printed-circuit board (PCB) layout practices, including:• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and of op amp
itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources
local to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are typically devoted to groundplanes. A ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise pickup.
Physically separate digital and analog grounds, observing the flow of the ground current.
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If
these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as opposed toin parallel with the noisy trace.
• Place the external components as close to the device as possible. As illustrated in Figure 47, keeping RF and
RG close to the inverting input minimizes parasitic capacitance.
• Keep the length of input traces as short as possible. Always remember that the input traces are the mostsensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduceleakage currents from nearby traces that are at different potentials.
• Cleaning the PCB following board assembly is recommended for best performance.
• Any precision integrated circuit can experience performance shifts resulting from moisture ingress into theplastic package. Following any aqueous PCB cleaning process, TI recommends baking the PCB assembly toremove moisture introduced into the device packaging during the cleaning process. A low temperature, postcleaning bake at 85°C for 30 minutes is sufficient for most circumstances.

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SBOS477B – DECEMBER 2011 – REVISED DECEMBER 201610.2 Layout Example
+

VIN A

+

VIN B
VOUT ARG

VOUT B

RG

RF

RF(Schematic Representation)
Place components
close to device and toeach other to reduceparasitic errors

Output A
VS+

Output A

Use low-ESR,
ceramic bypass
capacitor. Place as
close to the device
as possible

GND

V+

RF

Output B

GND

-In A

Output B

+In A

-In B

RF

RG
VIN A

GND
RG

V±

Use low-ESR,
ceramic bypass
capacitor. Place as
close to the device
as possible

GND

+In B

VS±

Ground (GND) plane on another layer

VIN B

Keep input traces shortand run the input traces
as far away fromthe supply lines
as possible

Copyright © 2016, Texas Instruments Incorporated

Figure 47. Operational Amplifier Board Layout for Noninverting Configuration

10.3 Power Dissipation
The OPA1652 and OPA1654 series op amps are capable of driving 2-kΩ loads with a power-supply voltage up to±18 V and full operating temperature range. Internal power dissipation increases when operating at high supply
voltages. Copper leadframe construction used in the OPA165x series op amps improves heat dissipationcompared to conventional materials. Circuit board layout minimizes junction temperature rise. Wide copper
traces help dissipate the heat by acting as an additional heat sink. Temperature rise is further minimized bysoldering the devices to the circuit board rather than using a socket.

Copyright © 2011–2016, Texas Instruments Incorporated

Product Folder Links: OPA1652 OPA1654

Submit Documentation Feedback

25

OPA1652, OPA1654
SBOS477B – DECEMBER 2011 – REVISED DECEMBER 2016

www.ti.com

11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 TINA-TI™ (Free Software Download)
TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI™ isa free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to arange of both passive and active models. TINA-TI provides all the conventional DC, transient, and frequency
domain analysis of SPICE, as well as additional design capabilities.
Available as a free download from the WEBENCH® Design Center, TINA-TI offers extensive post-processing
capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to selectinput waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.
NOTE
These files require that either the TINA software (from DesignSoft™) or TINA-TI software
be installed. Download the free TINA-TI software from the TINA-TI folder.
11.1.1.2 DIP Adapter EVM
The DIP Adapter EVM tool provides an easy, low-cost way to prototype small surface mount devices. The
evaluation tool these TI packages: D or U (SOIC-8), PW (TSSOP-8), DGK (VSSOP-8), DBV (SOT23-6, SOT23-5
and SOT23-3), DCK (SC70-6 and SC70-5), and DRL (SOT563-6). The DIP Adapter EVM may also be used withterminal strips or may be wired directly to existing circuits.
11.1.1.3 Universal Operational Amplifier EVM
The Universal Op Amp EVM is a series of general-purpose, blank circuit boards that simplify prototyping circuits
for a variety of IC package types. The evaluation module board design allows many different circuits to beconstructed easily and quickly. Five models are offered, with each model intended for a specific package type.
PDIP, SOIC, VSSOP, TSSOP and SOT-23 packages are all supported.
NOTE
These boards are unpopulated, so users must provide their own devices. TI recommends
requesting several op amp device samples when ordering the Universal Op Amp EVM.
11.1.1.4 Smart Amplifier Speaker Characterization Board Evaluation Module
The Smart Amplifier Speaker Characterization Board, when used in conjunction with a supported TI Smart
Amplifier and PurePath Console software, provides users the ability to measure speaker excursion, temperatureand other parameters for use with a TI Smart Amplifier products.
11.1.1.5 TI Precision Designs
TI Precision Designs are analog solutions created by TI’s precision analog applications experts and offer thetheory of operation, component selection, simulation, complete PCB schematic and layout, bill of materials, andmeasured performance of many useful circuits. TI Precision Designs are available online at
http://www.ti.com/ww/en/analog/precision-designs/.
11.1.1.6 WEBENCH® Filter Designer
WEBENCH® Filter Designer is a simple, powerful, and easy-to-use active filter design program. The WEBENCH
Filter Designer allows the user to create optimized filter designs using a selection of TI operational amplifiers andpassive components from TI's vendor partners.
Available as a web-based tool from the WEBENCH® Design Center, WEBENCH® Filter Designer allows theuser to design, optimize, and simulate complete multistage active filter solutions within minutes.
26

Submit Documentation Feedback

Copyright © 2011–2016, Texas Instruments Incorporated

Product Folder Links: OPA1652 OPA1654

OPA1652, OPA1654
www.ti.com

SBOS477B – DECEMBER 2011 – REVISED DECEMBER 201611.2 Documentation Support
11.2.1 Related Documentation
The following documents are relevant to using the OPA165x, and recommended for reference. All are available
for download at www.ti.com unless otherwise noted.
• OPA1652, OPA1654 EMIR Immunity Performance (SBOT007)• Source resistance and noise considerations in amplifiers (SLYT470)• Single-Supply Operation of Operational Amplifiers (SBOA059)• Op Amp Performance Analysis (SBOA054)• Compensate Transimpedance Amplifiers Intuitively (SBOA055)• Tuning in Amplifiers (SBOA067)• Feedback Plots Define Op Amp AC Performance (SBOA015)• Active Volume Control for Professional Audio (TIDU034)

11.3 Related Links
Table 1 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to sample or buy.
Table 1. Related LinksPARTS

PRODUCT FOLDERSAMPLE & BUY

TECHNICALDOCUMENTS

TOOLS &SOFTWARE

SUPPORT &COMMUNITY

OPA1652

Click here

Click here

Click here

Click here

Click here

OPA1654

Click here

Click here

Click here

Click here

Click here

11.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that haschanged. For change details, review the revision history included in any revised document.

11.5 Community Resource
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms ofUse.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools andcontact information for technical support.

11.6 Trademarks
TINA-TI, E2E are trademarks of Texas Instruments.
SoundPlus is a trademark of Texas Instruments Incorporated.
WEBENCH is a registered trademark of Texas Instruments.
Blu-Ray is a trademark of Blu-Ray Disc Association.
TINA, DesignSoft are trademarks of DesignSoft, Inc.
All other trademarks are the property of their respective owners.

11.7 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

Copyright © 2011–2016, Texas Instruments Incorporated

Product Folder Links: OPA1652 OPA1654

Submit Documentation Feedback

27

OPA1652, OPA1654
SBOS477B – DECEMBER 2011 – REVISED DECEMBER 2016

www.ti.com

11.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and revision ofthis document. For browser-based versions of this data sheet, refer to the left-hand navigation.

28

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Copyright © 2011–2016, Texas Instruments Incorporated

Product Folder Links: OPA1652 OPA1654

PACKAGE OPTION ADDENDUM
www.ti.com

20-Aug-2024

PACKAGING INFORMATION
Orderable Device

Status(1)

Package Type Package Pins Package
Drawing
Qty

Eco Plan(2)

Lead finish/
Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking(3)

Samples

(4/5)

(6)

OPA1652AIDACTIVE

SOIC

D

8

75

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 85

OP1652

Samples

OPA1652AIDGKACTIVE

VSSOP

DGK

8

80

RoHS & Green

NIPDAUAG

Level-1-260C-UNLIM-40 to 85

OUPI

Samples

OPA1652AIDGKR

ACTIVE

VSSOP

DGK

8

2500

RoHS & Green

NIPDAU | SN
| NIPDAUAG

Level-1-260C-UNLIM-40 to 85

OUPI

Samples

OPA1652AIDRACTIVE

SOIC

D

8

2500

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 85

OP1652

Samples

OPA1652AIDRGR

ACTIVE

SON

DRG

8

3000

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 85

OP1652

Samples

OPA1652AIDRGT

ACTIVE

SON

DRG

8

250

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 85

OP1652

Samples

OPA1654AIDACTIVE

SOIC

D

14

50

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 85

OPA1654

Samples

OPA1654AIDRACTIVE

SOIC

D

14

2500

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 85

OPA1654

Samples

OPA1654AIPW

ACTIVE

TSSOP

PW

14

90

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 85

OPA1654

Samples

OPA1654AIPWRACTIVE

TSSOP

PW

14

2000

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 85

OPA1654

Samples(1)

The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)

RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)

MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1

PACKAGE OPTION ADDENDUM
www.ti.com

20-Aug-2024(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.
(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to twolines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION
www.ti.com

25-Sep-2024

TAPE AND REEL INFORMATIONREEL DIMENSIONSTAPE DIMENSIONS
K0

P1

B0 W
Reel
DiameterCavity
A0
B0
K0
W
P1

A0

Dimension designed to accommodate the component width
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers

Reel Width (W1)QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes

Q1

Q2

Q1

Q2

Q3

Q4

Q3

Q4

User Direction of Feed

Pocket Quadrants*All dimensions are nominal

DevicePackage Package Pins
Type Drawing

SPQ

Reel
Reel
A0
Diameter Width (mm)(mm) W1 (mm)

B0
(mm)

K0
(mm)

P1
(mm)

W
Pin1
(mm) Quadrant

OPA1652AIDGKR

VSSOP

DGK

8

2500

330.0

12.4

5.3

3.4

1.4

8.0

12.0

Q1

OPA1652AIDR

SOIC

D

8

2500

330.0

OPA1652AIDR

SOIC

D

8

2500

330.0

12.4

6.4

5.2

2.1

8.0

12.0

Q1

12.4

6.4

5.2

2.1

8.0

12.0

Q1

OPA1652AIDRGR

SON

DRG

8

3000

OPA1652AIDRGT

SON

DRG

8

250

330.0

12.4

3.3

3.3

1.1

8.0

12.0

Q2

180.0

12.4

3.3

3.3

1.1

8.0

12.0

OPA1654AIDR

SOIC

D

14

Q2

2500

330.0

16.4

6.5

9.0

2.1

8.0

16.0

Q1

OPA1654AIPWR

TSSOP

PW

14

2000

330.0

12.4

6.9

5.6

1.6

8.0

12.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION
www.ti.com

25-Sep-2024

TAPE AND REEL BOX DIMENSIONS

Width (mm)

W

L

H

*All dimensions are nominal

DevicePackage Type

Package Drawing

Pins

SPQ

Length (mm)Width (mm)Height (mm)

OPA1652AIDGKR

VSSOP

DGK

8

2500

353.0

353.0

32.0

OPA1652AIDR

SOIC

D

8

2500

353.0

353.0

32.0

OPA1652AIDR

SOIC

D

8

2500

356.0

356.0

35.0

OPA1652AIDRGR

SON

DRG

8

3000

346.0

346.0

33.0

OPA1652AIDRGT

SON

DRG

8

250

210.0

185.0

35.0

OPA1654AIDR

SOIC

D

14

2500

356.0

356.0

35.0

OPA1654AIPWR

TSSOP

PW

14

2000

356.0

356.0

35.0

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION
www.ti.com

25-Sep-2024

TUBE
T - TubeheightL - Tube length

W - Tubewidth

B - Alignment groove width*All dimensions are nominal

DevicePackage Name

Package Type

Pins

SPQ

L (mm)W (mm)

T (µm)B (mm)OPA1652AID

D

SOIC

8

75

506.6

8

3940

4.32

OPA1652AIDGK

DGK

VSSOP

8

80

330

6.55

500

2.88

OPA1654AID

D

SOIC

14

50

506.6

8

3940

4.32

OPA1654AIPW

PW

TSSOP

14

90

530

10.2

3600

3.5

Pack Materials-Page 3

PACKAGE OUTLINE

DGK0008AVSSOP - 1.1 mm max height
SCALE 4.000

SMALL OUTLINE PACKAGE

C

5.05
TYP
4.75

A

0.1 C

PIN 1 INDEX AREASEATING
PLANE
6X 0.65

8
1

2X
3.1
2.9
NOTE 3

1.95

4
5
8X
B

3.1
2.9
NOTE 4

0.38
0.25
0.13

C A B

0.23
0.13

SEE DETAIL A

0.25
GAGE PLANE
1.1 MAX

0 -8

0.15
0.05

0.7
0.4

DETAIL A
A 20

TYPICAL
4214862/A 04/2023
PowerPAD is a trademark of Texas Instruments.

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187.

www.ti.com

EXAMPLE BOARD LAYOUTTM

DGK0008AVSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

SYMM
8X (1.4)

8X (0.45)(R0.05) TYP

1

8

SYMM

6X (0.65)
54SEE DETAILS(4.4)

LAND PATTERN EXAMPLEEXPOSED METAL SHOWNSCALE: 15X

SOLDER MASKOPENINGMETAL UNDERSOLDER MASKMETALSOLDER MASKOPENINGEXPOSED METALEXPOSED METAL
0.05 MAXALL AROUNDNON-SOLDER MASKDEFINED(PREFERRED)

0.05 MIN
ALL AROUNDSOLDER MASKDEFINEDSOLDER MASK DETAILS
15.0004214862/A 04/2023

NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shownon this view. It is recommended that vias under paste be filled, plugged or tented.
9. Size of metal pad may vary due to creepage requirement.

www.ti.com

EXAMPLE STENCIL DESIGNTM

DGK0008AVSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

SYMM(R0.05) TYP

8X (1.4)

8X (0.45)

1

8

SYMM

6X (0.65)
5

4

(4.4)

SOLDER PASTE EXAMPLESCALE: 15X

4214862/A 04/2023

NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.

www.ti.com

PACKAGE OUTLINE

D0014ASOIC - 1.75 mm max height
SCALE 1.800

SMALL OUTLINE INTEGRATED CIRCUIT

C
6.2
TYP
5.8

SEATING PLANE
PIN 1 ID
AREA

A

0.1 C
12X 1.27
14

1

2X
7.62

8.75
8.55
NOTE 3

7
8
B

4.0
3.8
NOTE 4

SEE DETAIL A

14X

0.51
0.31
0.25

C A B

1.75 MAX

0.25
TYP
0.13
0.25
GAGE PLANE

0 -8

0.25
0.10

1.27
0.40

DETAIL A
TYPICAL

4220718/A 09/2016

NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm, per side.
5. Reference JEDEC registration MS-012, variation AB.

www.ti.com

EXAMPLE BOARD LAYOUT

D0014ASOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

14X (1.55)

SYMM
1
14

14X (0.6)

12X (1.27)

SYMM

8

7
(R0.05)TYP(5.4)

LAND PATTERN EXAMPLESCALE:8X

SOLDER MASKOPENINGMETALSOLDER MASKOPENINGMETAL UNDERSOLDER MASK

0.07 MAXALL AROUND

0.07 MIN
ALL AROUNDSOLDER MASKDEFINEDNON SOLDER MASKDEFINEDSOLDER MASK DETAILS

4220718/A 09/2016

NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

D0014ASOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

14X (1.55)

SYMM
1
14

14X (0.6)

12X (1.27)

SYMM

7

8
(5.4)

SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCILSCALE:8X

4220718/A 09/2016

NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com

PACKAGE OUTLINE

D0008ASOIC - 1.75 mm max height
SCALE 2.800

SMALL OUTLINE INTEGRATED CIRCUITCSEATING PLANE.228-.244 TYP[5.80-6.19]
A.004 [0.1] C

PIN 1 ID AREA
6X .050[1.27]
8

1

2X
.150
[3.81].189-.197[4.81-5.00]
NOTE 3

4X (0 -15 )4
5
B

8X .012-.020[0.31-0.51].010 [0.25]
C A B.150-.157[3.81-3.98]
NOTE 4.069 MAX[1.75].005-.010 TYP[0.13-0.25]

4X (0 -15 )SEE DETAIL A.010[0.25].004-.010[0.11-0.25]

0 -8.016-.050[0.41-1.27]

DETAIL A(.041)[1.04]TYPICAL

4214825/C 02/2019

NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.

www.ti.com

EXAMPLE BOARD LAYOUT

D0008ASOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )[1.55]SYMM

SEE
DETAILS

1
8
8X (.024)[0.6]

6X (.050 )[1.27]

SYMM

5

4(R.002 ) TYP[0.05](.213)[5.4]

LAND PATTERN EXAMPLEEXPOSED METAL SHOWNSCALE:8X

METAL

SOLDER MASKOPENINGEXPOSED
METAL.0028 MAX
[0.07]ALL AROUNDSOLDER MASKOPENINGMETAL UNDERSOLDER MASKEXPOSED
METAL.0028 MIN
[0.07]ALL AROUNDSOLDER MASKDEFINEDNON SOLDER MASKDEFINEDSOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

D0008ASOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )[1.55]SYMM
1
88X (.024)[0.6]

6X (.050 )[1.27]

SYMM

5

4(R.002 ) TYP[0.05](.213)[5.4]

SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCILSCALE:8X

4214825/C 02/2019

NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com

PACKAGE OUTLINE

DRG0008A

WSON - 0.8 mm max height
SCALE 5.000

PLASTIC SMALL OUTLINE - NO LEAD

3.1
2.9

A

B

3.1
2.9

PIN 1 INDEX AREA

0.8
0.7
C
SEATING PLANE
0.05
0.00

0.08 CEXPOSEDTHERMAL PAD(0.2) TYP

1.2 0.1

4

5

2X
1.5

2 0.1

8

1
6X 0.58X
PIN 1 ID

8X

0.6
0.4

0.3
0.2
0.1
0.08

C A B
C

4218885/A 03/2020

NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

DRG0008A

WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

(1.2)
SYMM

8X (0.7)

8

1
8X (0.25)
SYMM(2)(0.75)

6X (0.5)
4(R0.05) TYP

5( 0.2) VIA
TYP(0.35)(2.7)

LAND PATTERN EXAMPLEEXPOSED METAL SHOWNSCALE:20X

0.07 MIN
ALL AROUND

0.07 MAXALL AROUNDEXPOSEDMETALEXPOSEDMETALSOLDER MASKOPENINGMETALMETAL UNDERSOLDER MASKNON SOLDER MASKDEFINED(PREFERRED)SOLDER MASKOPENINGSOLDER MASKDEFINEDSOLDER MASK DETAILS

4218885/A 03/2020
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shownon this view. It is recommended that vias under paste be filled, plugged or tented.

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EXAMPLE STENCIL DESIGN

DRG0008A

WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

SYMM

8X (0.7)

8X (0.25)

METAL
TYP

8

1

SYMM

(1.79)

6X (0.5)
4

5(R0.05) TYP(1.13)(2.7)

SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCILEXPOSED PAD
84% PRINTED SOLDER COVERAGE BY AREASCALE:25X

4218885/A 03/2020

NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

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PACKAGE OUTLINE

PW0014ATSSOP - 1.2 mm max height
SCALE 2.500

SMALL OUTLINE PACKAGESEATING
PLANE
C

6.6
TYP
6.2

A

0.1 C

PIN 1 INDEX AREA
12X 0.65
14

1

2X
5.1
4.9
NOTE 33.9

4X (0 -12 )
7
8
14X
B

4.5
4.3
NOTE 4

0.30
0.17

0.1

C A B

1.2 MAX(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05

0 -8

0.75
0.50

DETAIL A
A 20

TYPICAL
4220202/B 12/2023

NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.

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EXAMPLE BOARD LAYOUT

PW0014ATSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

SYMM

14X (1.5)(R0.05) TYP

1
14

14X (0.45)

SYMM

12X (0.65)

8

7

(5.8)

LAND PATTERN EXAMPLEEXPOSED METAL SHOWNSCALE: 10X

SOLDER MASKOPENINGMETAL UNDERSOLDER MASKMETALSOLDER MASKOPENINGEXPOSED METALEXPOSED METAL
0.05 MAXALL AROUNDNON-SOLDER MASKDEFINED(PREFERRED)

0.05 MIN
ALL AROUNDSOLDER MASKDEFINEDSOLDER MASK DETAILS
15.0004220202/B 12/2023

NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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EXAMPLE STENCIL DESIGN

PW0014ATSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

14X (1.5)

SYMM(R0.05) TYP

1
14X (0.45)

14

SYMM

12X (0.65)

8

7

(5.8)

SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCILSCALE: 10X

4220202/B 12/2023

NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

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