2015 Silicon Nanoelectronics Workshop
June 14-15, 2015
Rihga Royal Hotel Kyoto, Kyoto, Japan
Table of Contents
Sunday, June 14, 2015
8:30

Opening Remarks
Yasuo Takahashi, Hokkaido University

Session 1: Plenary and Nonvolatile Memories
Session Co-Chairs: Kazuhiko Endo, AIST and Takahiro Shinada, Tohoku University
8:40

1-1(Plenary)process technologies
1S1Rfor HighDensity
Cross Point
Advanced Advanced
process technologies
of 1S1R forofHigh
Density
Cross
Point ReRAM
ReRAM, B. Y. Kim and H. S. Kim (SK Hynix Inc.)

9:10

1-2

Trade-off of Performance, Reliability and Cost of SCM/NAND Flash Hybrid SSD, H.
H. Takishita, S. Ning, and K. Takeuchi (Chuo University)

9:30

1-3

Additional Charge Trapping Layer SONOS Nonvolatile Memory Based on Ultra-Thin
Body Poly-Si Junctionless FinFET, Wei-Cheng Wang, Chien-Chih Chung, MingHsien Chung, Cheng-Ping Wang, Yung-Chun Wu (National Tsing Hua University)

9:50

1-4

Understanding the Underlying Physics of Superior Endurance in Bi-layered TaOXRRAM, Y. D. Zhao, P. Huang, Z. Chen, C. Liu, H. T. Li, W. J. Ma, B. Gao, X. Y. Liu,J. F. Kang (Peking University)10:10

BreakSession 2: Novel Process Technology for Nanoelectronics
Session Co-Chairs: Kensuke Ota, Toshiba and Toshifumi Irisawa (AIST)
10:30

2-1

Variability Suppression of FinFETs by Smoothing Sidewall Roughness Using Ion
Beam Etching Technology, T. Matsukawa1, K. Endo1, H. Akasaka2, Y. Kamiya2, M.
Ikeda2, K. Tsunekawa2, T. Nakagawa2, Y.X. Liu1, and M. Masahara1 (1AIST, 2Canon
ANELVA)

10:50

2-2

sSOI Relaxation by BOX Creep Technique for Dual Strain CMOS Integration, A.
Bonnevialle1,2, C. Le Royer2, Y. Morand1, S. Reboh2, D. Rouchon2, N. Bernier2, B.
Mathieu2, C. Plantier2, M. Vinet2 (1STMicroelectronics, 2CEA LETI)

11:102-3Significance of Kinetic-linkage of Oxygen Vacancy with SiO2/Si Interface for SiO2IL Scavenging in HfO2 Gate Stacks, X. Li, T. Yajima, T. Nishimura, and A. Toriumi(The University of Tokyo)

11:30

2-4

Gate-stack engineering for self-aligned Ge-gate/SiO2/SiGe-channel Insta-MOS
devices, Wei-Ting Lai1,2, Kuo-Ching Yang2, Po-Hsiang Liao2, Thomas George2, andPei-Wen Li1,2 (1National Chiao Tung University, 2National Central University)

11:50

2-5

Impact of H2, O2, and N2 anneals on atomic-scale surface flattening for 3-D Ge
channel architecture, Y. Morita, H. Ota, M. Masahara, and T. Maeda (AIST)

12:10

Lunch

Session 3: Nanowire FETs
Session Co-Chairs: Kristin De Mayer, IMEC and Hiroshi Mizuta, JAIST, University of Southampton
13:30

3-1(Invited) Experimental Study of Reliabilities in Tri-gate Nanowire Transistor ~Whatis Main Reliability Issue in 3D Transistor?~, K. Ota, C. Tanaka, D. Matsushita, T.
Numata, and M. Saitoh (Toshiba Corporation)

14:00

3-2Threshold Voltage and Current Variability of Extremely Narrow Silicon Nanowire
MOSFETs with Width down to 2nm, T. Mizutani, Y. Tanahashi, R. Suzuki, T.
Saraya, M. Kobayashi, and T. Hiramoto (University of Tokyo)

14:20

3-3

Performance of GAA Poly-Si Channel of Junctionless Field Effect Transistors with
Ultra-Thin Body, Yan-Bo Liu, Yi-Ruei Jhan, Cheng-Ping Wang, and Yung-Chun Wu(National Tsing Hua University)

14:40

3-4

Investigation of Reconfigurable Silicon Nanowire Schottky Barrier TransistorsBased Logic Gate Circuits and SRAM Cell, J. Wang, G. Du, and X. Y. Liu (PekingUniversity)

15:00

3-5

Impacts of Surface Roughness Scattering on Hole Mobility in Germanium
Nanowires, H. Tanaka, J. Suda, and T. Kimoto (Kyoto University)

15:20

BreakSession 4: Finite Dopants in Nanodevices
Session Chair: Steve S. Chung, National Chiao Tung University
15:35

4-1

(Invited) Single ion implantation of Ge donor impurity in silicon transistors, E. Prati
1, Y. Chiba2, M. Yano2, K. Kumagai2, M. Hori3, G. Ferrari4, T. Shinada5, and T. Tanii2,1

Consiglio Nazionale delle Ricerche, 2Waseda University, 3University of Toyama,

4Politecnico di Milano, 5Tohoku University)

16:054-2

Impact of Diffused Donor-Clusters near Lead/Channel Boundary on HighTemperature Single-Electron Tunneling in Narrow SOI-FETs, D. Moraru, A.
Samanta1, Y. Takasu1, K. Tyszka1,2, T. Mizuno1, R. Jablonski2 and M. Tabe1(1Shizuoka University, 2Warsaw University of Technology)

16:25

4-3

The impact of single donor and donor-acceptor pair on electronic and transport
properties of silicon nanostructures, L. T. Anh1, D. Moraru2, M. Manoharan1,M.Tabe2, and H. Mizuta1,3 (1JAIST, 2Shizuoka University, 3Southampton University)

Session 5 Posters
16:45-18:30

Starting with Short Oral Presentation

Session Chairs: Mitsuru Takenaka, University of Tokyo and Kazuhiko Endo, AIST
5-1

Investigation of the Impact of Grain Boundary on Threshold Voltage of 3-D MLC
NAND Flash Memory, Z. Lun, L. Shen, Y. Cong, G. Du, X. Liu, Y, Wang (PekingUniversity)

5-2

Resistive Switching Characteristics in HfOx Memory Devices with Local Electrical
Field Design, Tsung-Kuei Kang, Wei-Len Chen, Yu-Han Chen, Pei-Hsun Tsai(Feng-Chia University)

5-3

Position and Number Control of Donor-QD Potential by Pattern-doping in SOI-FETChannels, K. Tyszka1,2, D. Moraru1, T. Mizuno1, R. Jablonski2, M. Tabe1 (ShizuokaUniversity, Warsaw University)

5-4

Nanodamascene metal-insulator-metal single electron transistor prepared byatomic layer deposition of tunnel barrier and subsequent reduction of metal surface
oxide, G. Karbasian, A. O. Orlov, and G. L. Snider (University of Notre Dame)

5-5

Impacts of Channel Constriction Dimensions of Graphene Single Carrier Transistors
on the Coulomb Diamond Characteristics, T. Iwasaki1, M. Muruganathan1, and H.
Mizuta1,2, (1JAIST, 2University of Southampton)

5-6

Series-triple quantum dots fabricated under each control gate by the use of thermaloxidation, T. Uchida1, H. Sato1, A. Tsurumaki-Fukuchi1, M. Arita1, A. Fujiwara2, and
Y. Takahashi1 (1Hokkaido University, 2NTT Corporation)

5-7

Fabrication and characterization of physically-defined double quantum dots without
unintentional localized states on highly-doped silicon substrate, Y. Yamaoka, T.
Kodera, S. Oda (Tokyo Institute of Technology)

5-8Characterization of carrier dynamics in Ge quantum dots through Ge quantum-dot
MOSFETs using pulsed voltage technique, Ming-Hao Kuo1, Ho-Chane Chen1, WeiTing Lai1,2, and Pei-Wen Li1,2 (1National Central University, 2National Chiao TungUniversity)

5-9

Simultaneous two gate reflectometric spectroscopy of Si coupled donor-dot system,
X. Jehl1, A. O. Orlov2, R. Maurand1, P. Fay2, G. L. Snider2, S. Barraud3, and M.
Sanquer1 (1DSM-INAC, 2University of Notre Dame, 3DRT-Leti)

5-10

Fabrication of a highly controllable Si-MOS quantum dot device, T. Honda1, J.
Yoneda2,3, K, Takeda2,3, T. Kodera1,2, S. Tarucha2,3, and S. Oda1 (1Tokyo Instituteof Technology, 2The University of Tokyo, 3RIKEN

5-11

Tunneling Field-Effect Transistor with a Grown Si Epitaxial Layer for Boosting ON
Current, J. Lee, J. H. Kim, D. W. Kwon, E. Park, T. Hyung Park, and B.-G. Park
(Seoul National University)

5-12

Short-Drain Effect of 5 nm Tunnel Field-Effect Transistors, Yu-Hsuan Chen1,Nguyen Dang Chien2, Jr-Jie Tsai1, Yan-Xiang Luo3, and Chun-Hsing Shih1(1National Chi Nan University, 2University of Da Lat, 3National Tsing Hua University)

5-13

Fabrication and Characterization of Silicon Nanowire Ultra-thin Channel Poly-Si
Junctionless Field Effect Transistors with a Trench Structure Ko-Wei Lin, Mu-Shih
Yeh, Min-Hsin Wu, Yung-Chun Wu (National Tsing Hua University)

5-14

Hybrid Channel Poly-Si Junctionless Field-Effect Transistors with Trench Structure
Formed by Dry Etching Process, C.-P. Wang, Y.-R. Jhan, J.-J. Su, Y.-C. Wu(National Tsing Hua University)

5-15

Built-in Effective Body-Bias Effect in UTBB Hetero-Channel MOSFETs and Its
Suppression, C.-H. Yu, P. Su (National Chiao Tung University)

5-16

Boolean logic circuit implementation using multi-input floating-body MOSFET, MinWoo Kwon, Hyungjin Kim, Jungjin Park, Byung-Gook Park (Seoul NationalUniversity)

5-17

Comparison of Electrical Characteristics of N-type Silicon Junctionless Transistors
with and without Film Profile Engineering by TCAD Simulation, Jung-Ruey Tsai1,Horng-Chih Lin2, Hsiu-Fu Chang1, Bo-Shiuan Shie2, Ting-Ting Wen2, and Tiao-Yuan
Huang2 (Asia University, National Chiao Tung University)

5-18

Thermodynamicstabilityof1

highphosphorus
1

concentration
1,2insilicon1

nanostructures, M. Perego , G. Seguini , E. Arduca , J. Frascaroli , D. De
Salvador1,2, M. Mastromatteo1,2, A. Carnera1,2, G. Nicotra1, M. Scuderi1, C. Spinella1,G. Impellizzeri1, C. Lenardi2, and E. Napolitani1,2 (1IMM-CNR, 2Università degli Studidi Padova)
5-19

3D-TCAD Simulation Study of the Novel T-FinFET Structure for Sub-14nm MetalOxide-Semiconductor Field-Effect Transistor, Chen-Han Chou, Chung-Chun Hsu,
Steve S. Chung, Chao-Hsin Chien (National Chiao Tung University)

5-20Characteristics of Inversion, Accumulation and Junctionless mode Silicon N-Typeand P-Type Bulk FinFETs with optimized 3-nm nano-fin structure, V.
Thirunavukkarasu, Y.-R. Jhan, Y.-B. Liu, and Y.-C. Wu (National Tsing HuaUniversity)

5-21

Bringing Physics to Device Design - a Fast and Predictive Device Simulation
Framework, M. Karner, Z. Stanojevic, F. Mitterbauer, C. Kernstock, H. Demel(Global TCAD Solutions GmbH)

5-22

A Capacitance-Voltage model for DG-TFET, A. Biswas, A. M. Ionescu (EcolePolytechnique Fédérale de Lausanne)

5-23

Physics-based Model for the Conductive Filament at the Low Resistance State ofThin SiO2 Films, R. Yamaguchi, S. Sato, and Y. Omura (Kansai University)

5-24

Performance Evaluation of Si Ultra-Thin Body (1 nm) Junctionless FET with LG = 1nm and LG = 3 nm, Yi-Ruei Jhan, Yan-Bo Liu, Yung-Chun Wu (National Tsing HuaUniversity)

5-25

Design and analysis of electric-field-assisted nonlocal silicon-channel spin devices,
D.Kitagata, T.Akushichi, Y.Takamura, Y.Shuto, S.Sugahara (Tokyo Institute ofTechnology)

5-26

Silicon-Compatible Resonant Plasma-Wave Transistor with 2D Silicene Channel for
High-Performance Terahertz Electromagnetic Wave Emitters, Jong Yul Park, SungHo Kim, and Kyung Rok Kim (Ulsan National Institute of Science and Technology)

5-27

Novel Trigate Field-Plated Poly-Si TFT with Improved Leakage Current and HighOn/Off Current Ratio, Yong-Hong Syu, Hsin-Hui Hu*, Jhen-Yu Tsai, Kai-Ming Wang,Jia-Jin Tsa (National Taipei University of Technology)

5-28

Frequency-Dependent Response of Nanoscale Thermocouples Using Temperature
Oscillations Produced by Nanoscale Heaters, Gergo P. Szakmany, Alexei O. Orlov,Gary H. Bernstein, Wolfgang Porod (University of Notre Dame)Monday, June 15, 2015
Session 6: New Low-Power Devices
Session Co-Chairs: Byung-Gook Park, Seoul National University
and Enrico Prati,Consiglio Nazionale delle Ricerche
8:30

6-1

New features in Planar SiGe Channel Tunnel FETs Performance and Operation, C.
Le Royer1, L. Hutin1, S. Martinie1, P. Nguyen1, S. Barraud1, F. Glowacki1, S.
Cristoloveanu2, M. Vinet1 (1CEA LETI, 2IMEP-LAHC)

8:50

6-2

Design of Complementary Tilt-gate TFETs with SiGe/Si and III-V IntegrationsFeasible for Ultra-low-power Applications E. R. Hsieh1, Y. S. Lin2, Y. B. Zhao1, C.
H. Liu2, C. H. Chien1, and Steve S. Chung1 (1National Chiao Tung University,
2

National Taiwan Normal University)

9:10

6-3

Dopant-Assisted Tunnel-Current Enhancement in Two-Dimensional Esaki Diodes,
H.N. Tan1, D. Moraru1, K. Tyszka1,2, A. Sapteka3, S. Purwiyanti3, L.T. Anh4, M.
Manoharan4, T. Mizuno1, R. Jablonski2, D. Hartanto3, H. Mizuta4,5, M. Tabe1(1Sizuoka University, 2Warsaw University of Technology, 3University of Indonesia,
4JAIST, 5University of Southampton)

9:30

6-4

Fabrication of high-quality Co2FeSi0.5Al0.5/CoFe/MgO/Si spin injectors for Si-channel
spin devices, T. Kondo, Y. Kawame, Y. Takamura, Y. Shuto, S. Sugahara. (TokyoInstitute of Technology)

9:50

BreakSession 7: Quantum Computing and Electronics
Session Co-Chairs: Michiharu Tabe, Sizuoka University and Pei-Wen Li, National Central University
10:10

7-1

(Invited) Spin-based Quantum Computing in Silicon, A. Dzurak (UNSW)

10:40

7-2

Variation of Coulomb diamonds and excited states caused by electric field in Si
single-electron transistor, H. Satoh1, T. Uchida1, A. Tsurumaki-Fukuchi1, M. Arita1,A. Fujiwara2, and Y. Takahashi1 (1Hokkaido University, 2NTT Corporation)

11:00

7-3

Study of charged island formation in nanoscale Si single-electron transistors using
dual port reflectometric spectroscopy, A. O. Orlov1, P. Fay1, G. L. Snider1, X. Jehl2,
R. Lavieville3, S. Barraud3, and M. Sanquer2 (1University of Notre Dame, 2DSMINAC, 3DRT-Leti)

11:20

7-4

Low Temperature Charge Pumping in SOI Gated PIN Diode, T. Watanabe1, M.
Hori1, T. Saruwatari1, A. Fujiwara2, and Y. Ono1 (1University of Toyama, 2NTT)

11:40

7-5

Charge sensing of p-channel double quantum dots fabricated on (110) silicon
substrate, K. Iwasaki, T. Kodera, and S. Oda (Tokyo Institute of Technology)

12:00

Lunch

Session 8:

Post Silicon Materials and Devices

Session Co-Chairs: Yukinori Ono, University of Toyama and Kazuhiko Endo, AIST
13:30

8-1

(Invited) Fluctuations and Relaxation in Graphene, D. K. Ferry, B. Liu, and R. Akis
(Arizona State University)

14:00

8-2

Low pull-in voltage graphene nanoelectromechanical switches, M. Manoharan1, T.
Chikuba1, N. Kanetake1, J. Sun1, and H. Mizuta1,2 (1JAIST,2

University ofSouthampton)
14:20

8-3

Challenges of 3D VLSI-CoolCubeTM process with p-Ge-OI and n-InGaAs-OI for
Ultimate CMOS Nodes, F. Nemouchi1, L. Hutin1, H. Boutry1, P. Rodriguez1, E.
Ghegin1,2, J. Borrel1,2, Y. Morand2, S. Kerdiles1, P. Batude1, and M. Vinet1 (CEA Leti,
STMicroelectronics)

14:40

8-4

CMOS Roadmap Analysis from the Perspective of III-V technology using MASTAR,G.

Hiblot1,2,Q.

Rafhay2,G.

Mugny1,G.

Ghibaudo2,andF.

Boeuf1(1STMicroelectronics, 2IMEP-LAHC)
15:00

8-5

Effect of Free Carrier Accumulation or Depletion on Zone-center Vibrational Modein Ge, S. Kabuyanagi, T. Nishimura, T. Yajima, and A. Toriumi (The University ofTokyo)

15:20

8-6

N+/P Shallow Junction with High Dopant Activation and Low Contact Resistivity
Fabricated by Solid Phase Epitaxy Method for Ge Technology, P. Liu, M. Li, X. An,
M. Lin, Y. Zhao, B. Zhang, X. Xia, R. Huang (Peking University)
Break

15:40

Session 9: 20th Anniversary Panel Session
16:00-17:30
Moderator: T. Irisawa, AIST
Topics:Past and future of Si-nano related electronics

Panelists:

D. Ferry (Arizona State University)
H. Iwai (Tokyo Institute of Technology)
S. Oda (Tokyo Institute of Technology)
T. Hiramoto (The University of Tokyo)
K. De Meyer (imec)

17:30

Closing Remarks