BIPOLAR OPERATION USING THE DACx578

reRail-to-rail operation at the amplifier output isachievable using an OPA703 as the output amplifier.

thhretopaDevelopment of a prototype front-end board of the Thin
GapfamilyChamber
The DACx578
of products is designed forp
single-supply operation, but a bipolar output range iscfor ATLAS at the High-Luminosity LHC
also Tomomi
possible using
the circuit in either
Figure 118.
Kawaguchi(NagoyaUniv.) c

Performance Test
The output voltage for any input code can be

Measurement of Higgs coupling and new physics searches with higher statistics.

calculated
Equation2.
1. Demonstrationof thewith
DataTransfer!

0×1

×3

Run-4, 5, …
13~14 TeV
5~7×1034cm-2s-1

2028

2026

2022

The collision rate
will be increased.

YearIn order to cope with the higher event rate for HL-LHC,
all trigger and readout electronics need to be replaced by new ones.

Data transfer of 16 Gbps

This result has an output voltage range of ±5V withhas been successfully demonstrated!
000h corresponding to a -5V output and FFFhGbps
corresponding to]aQ(UBDSa#/<)d8.0
a +5V output for the12bit
8.91 x 10.17
2. Demonstrationof the ASDTOQF[a]aQ
Threshold <Control
DAC7578.

Thin Gap Chamber (TGC) for ATLAS
ATLAS detector

TGC

Off-detectorΦ (strip)

PS board

On-detector

Signal for the ASD threshold Set value
2
 Channel ID of DAC

VAV

EXTREFTGC Trigger Processor
andReadout board䃛⢏Ꮚ㣕㊧⢭ᐦᐃჾ
Monitored
Drift Tube(MDT)㻾㼑㼟㼕㼟㼠㼕㼢㼑㻌㼜㼘㼍㼠㼑㻌㼏㼔㼍㼙㼎㼑㼞㼟㻔㻾㻼㻯㻕Resistive
Plate Chambers (RPC)

1. Trigger Algorithm

12 m㼀㼔㼕㼚㻌㼓㼍㼜㻌TGC
㼏㼔㼍㼙㼎㼑㼞㼟
3㻔㼀㻳㻯㻕mradβ84䝖䝻䜲䝗☢ሙෆ㒊䃛⢏Ꮚ᳨ฟჾ

2NSW
1 mrad161412108642m

0Momentum resolution at the trigger improved by TGC tracking. Rate for single
muon trigger with pT threshold of 15 GeV reduced by 30% in the endcaps.

TGC trigger/readout system for Phase-II
2. Concept of Trigger and Readout Electronics
864

480

PS board

ASD

192

hit data
Trigger, control
hit data
Trigger, control

2 fibers/board for up-stream
1 fiber/board for down-stream

PS board:
TGC front-end board

NSW

to Software
to MDT trigger

0.1#F

Tx・transfer all hit data to off-detector,
・control the ASD threshold.

IC• Voltage range : -2~2 V
Demonstrationof the ASD

Result of the measurement of the A

For the timing alignment(old) Patch-Panel ASIC
4 on mother board
4 on daughter board
32 × 8 = 256 channels

This prototype board has
all functions for HL-LHC!

For hit data transfer andcontrol of Patch-Panel ASIC and DAC

FPGAXilinx Kintex-7
XC7K325TFFG900-2
256 channel data Tx
PP ASIC control via JTAGDAC control via I2C
For ASD threshold supply and monitoring

DAC
DAC7578SPW
8 channels × 2ADC
LTC1289CCSW

ThresholdThresholdvoltagefor(Wire,wireof a Ch.0channelvoltageOpeamp)
0− 50
Copyright © 2010, Texas Instruments
Incorporated

Range of the value in Run-2 operation
Wire : -250 mV~60 mV
Strip : 70 mV~160 mV− 100

Product Folder Link(s): DAC557− 150− 200− 250

あ− 300
Perfect linearity between the set
and the measured values are obtained!
− 300

− 250

− 200

− 150

− 100

−50

expected

Vth0(mV)

Range of the value in Run-2 operation:-250 mV ~ -60 mV

Perfect linearity between the set and theDemonstration with Muon •Beam
off-detector

DataControl

measured value is obtained.
• Offset of the linear fit ranges from 0 mV todepending on channels,
whichis due to the variation of the resistor
ThresholdTx (Data)
and R2 ( ± 0.5%).
Data
Rx (Control)
256 channels
16 Gbps→ Schematic haveto be,consideredfor theprototype.
TGC

on-detector

2016/11/25

PS board

Oct. - Nov. 2016, @H8C beam line (CERN)

Efficiency for a channel has been estimated from the events which have
one hit for each layer other than theLayer
layerof interest.
1
Wire support

Prototype of TGC PS Board

V+"6VGND

Figure 118. Bipolar Output Range Using External• Step size : 0.98 mV (12bit)
Reference at 5V

Inner muon
detectors

Main function of PS board:!5V

ASD threshold

Serial Interface
2FPGARx

data readout
TGC trigger processor
andreadout board

PS board

ASD

off-detector

AVDD
VOUT
VREFIN/DACx578
VREFOUT
DAC7578SPW

8 channels×2 8 channels×2

TGC trigger processor
andreadout board

on-detector

M2 M3

10#F

6

Toroidal Magnet

Before the start of HL-LHC,
NSW 1mrad measurement available.

M1

OP amp
OPA703

Measure the ASD threshold withdigital voltmeter.

PC

TGC trigger for HL-LHC:
track-based trigger(Trigger decision: β)ToroidalMagnetToroidalMagnet䝖䝻䜲䝗☢ሙ

+6V
V-

R1
10k$

DAC

10Current TGC trigger:
coincidence-based trigger

FR2
10k$

3.3 V…

with the latency and rate for HL-LHC.
Gas chamber with 2.8 mmgap
small wheel will provide track segments with 1 mrad resolution at the endcap inner• New→ Provide first level muon
trigger
endcapregionafteratthe
phase-1 upgrade.
→ Identify 40MHz bunch-crossing• We plan to provide TGC track segments with 3 mrad resolution at the big wheel.
Number of layers : 7 • Deflection angle between a NSW segment and a TGC segment can be used for the trigger
decision.

DD2V

TGC track trigger reminder
R (wire)Thecurrent
TGCtrigger
and readout electronics need to be replaced by new ones to cope•

TGC Track Trigger

R2 "!R + R "Result of Loop back (Eye Diagram)(2)
Eye Diagram from IBERT
Voltage offset
Bit error rate
Where: 100 1×10−1
DIN = 50
decimalequivalentofthebinarycode
that−31×10
is loaded to the DAC register. It can range from 0−50to 4095 (12 bit), 0 to 1023 (10 bit), and 0 to1×10255(8 bit)−50 1×10−7
n = −100resolutionin bits
1×10−900.25
0.5
Gain = 1 −0.5 −0.25
Unit interval" 10 ! DIN #Data transfer
VOUT =rate
5V%& $raten errorBit< 8.91×10-15
8.0 Gbps × 2'(2(3)

HL-LHC

Vthmeasured (mV)

sity

2024

u2020

2018

2016

2012

2014

dL
ate×4egrinosity
Int
ed LumIntegratomin

D! IN "!
"
2Measure the bit error
ratebackhigh-speed
VO UT= %withV loop
# Gain# by#% 1VREF#%& $for% a&transceiver&&% REF' 2n ( ' R1
' R1 ( (&('data transfer by Xilinx’s IBERT.

s i tyRun-3
13~14 TeV
2×1034cm-2s-1

LuminoRun-2
13~14 TeV
1×1034cm-2s-1

IntegratedRun-1
7~8 TeV~7×1033cm-2s-1

2010

Integrated Luminosity

High-Luminosity LHC (2026~)• Most of the channels in the beam
area has almost 100% efficiency.
• The efficiency is relatively small forsome channels.
→Due to support structure of thewires inside the chamber.

10.9
0.8
0.70.6
0.5

Button support

0.4

Optical Rx/Tx
2 Tx and 2 Rx
(up to 20 Gbps)

Basic functionalities of the TGC PS board have been demonstrated!

Ethernetfor debugging

Conclusion

TTC• A prototype of PS board has been developed with the concept for HL-LHC,- all hit data transfer with 16 Gbps per board,- ASD threshold control and monitoring based on FPGA.
• The prototype of PS board has been successfully demonstrated.