Firmware development for the first level trigger of ATLAS LAr Calorimeter
KMI 2017

K.Uno on behalf of ATLAS LAr Calorimeter group
The University of TokyoIntroduction

The ATLAS Liquid Argon (LAr) calorimeter is one of critical component for ATLAS physics achievement, i.e. thediscovery of 𝐻 → 𝛾𝛾. In order to cope with high luminosity LHC run in the future, enforcement of the calorimeter
trigger performance is essential for new physics search. Here the readout electronics system developed toward thePhase-I upgrade (2018 ‒ 2020) is presented.

The new trigger readout scheme

Upgrade of the readout electronics

The new scheme so-called Super Cell, will be introduced
in order to measure EM (electromagnetic) shower shape attrigger level..

Tokyo group is working for the Backend electronics.

Trigger Tower scheme

Super Cell scheme
0,3layer:Δ𝜂×Δ𝜙=
0.1×0.1
Δ𝜂×Δ𝜙 = 0.1×0.1
1, 2 layer : Δ𝜂×Δ𝜙 = 0.025×0.1
1 Trigger Tower = 1 + 4+4+1 = 10 Super Cell

The new trigger readout (Black point) can decrease theenergy threshold than the current one (Blue point), because
it provides better energy resolution and the shower
information which enhances the separation capability
between electron, photon and hadronic jet.
3 layer

Trigger Tower readoutΔη × Δϕ = 0.1× 0.1
φ2 layerdepth1 layerη104

requirement from L1 trigger
ATLAS

s = 14 TeV, µ = 80
Electron efficiency = 95%

21010

Super Cell readout
0 , 3 layer : Δη × Δϕ = 0.1× 0.1
1 , 2 layer : Δη × Δϕ = 0.025 × 0.1
photon1 Trigger Tower = 1+4+4+1 = 10 Super Cell

HadCore ≤ 1 GeV
HadCore cut + wη,2 < 0.0146

1Requirement
・The latency of signal processing is less than 125 ns.
・Transferred to L1Calo at ~ 50 Tbps.

31 LDPBs installed in three ATCA crates.
4 AMCs so-called LATOME in one LDPB.
à The total of 124 LATOME is used.
Transceiver speed
Challenging!
~11.2 Gbps/fiber à ~ 450 Gbps/LATOME

Simulation

103

20 kHz0 layerphoton

L1 Rates [kHz]!" $%&'(%)*+ ,- ./ $&011'& &2$' 3)& (041*' !5 )6'7'8$

LDPB (LAr Digital Processing Blade)
Main role・ Convert ADC data of each Super Cell (~34k) into ET.
・ Identify the bunch crossing of the significant energy.

HadCore cut + R η > 0.93
HadCore + w η,2 + Rη cuts
HadCore + w η,2 + Rη cuts + f 3 < 0.02

10-1 10 15 20 25 30 35 40 45 50 55

LATOME Board- 4 pairs of 𝜇Pod
- 96 optical fibers- Arria10 FPGA
2- 156 × 73.5 mm

L1 EM ET [GeV]

Firmware development

Signal Processing
Digital filtering

Each FPGA takes care of 320 Super Cells.
à Serialize 6 Super Cell with 62 parallel processing with240 MHz.
Core processing block: 6 channel serialized FIR Filter.
- Use circular buffer RAM to correspond to 6 channel.
- All calculation is done in DSP Block in FPGA.
àImprove Fmax and latency.

FIR Filter
𝐸9 = > 𝑎@ (𝑆@ − 𝑃) , 𝐸9 𝜏 = > 𝑏@ (𝑆@ − 𝑃)
EE@FG@FG

Selection criteria
8 𝑛𝑠 ∶ −1 𝐺𝑒𝑉 ≤ 𝐸9 < 10 𝐺𝑒𝑉
𝜏 <2 𝑛𝑠 ∶ 10 𝐺𝑒𝑉 ≤ 𝐸9

coefficientpedestal
circular buffer

𝑆@ : 𝐴𝐷𝐶 𝑑𝑎𝑡𝑎, 𝑃: 𝑝𝑒𝑑𝑒𝑠𝑡𝑎𝑙, 𝑎@ , 𝑏@ : 𝑐𝑜𝑒𝑓𝑓𝑖𝑐𝑖𝑒𝑛𝑡,𝜏 ∶ 𝑇𝑖𝑚𝑖𝑛𝑔 𝑜𝑓 𝑝𝑢𝑙𝑠𝑒

coefficientpedestal
circular buffer

coefficientpedestal
circular buffer

coefficientpedestal
circular buffer

ADC

FIR Filter firmware result・Total latency : 87.5 ns・Fmax : 257.6 MHz・DSP Block usage ratio : 16 %5 clock delay

5 clock delay

Use 240 MHz clock

5 clock delay

register

6 channel filter#01# %&!" = ( )# (+, − .),2#

Latency = 87.5 ns

DSP Block

DSP BlockAll results are satisfied with the requirement.

Summary and Prospect
Tokyo group has been working on Phase-I upgrade for
ATLAS LAr calorimeter in order to enhance performance ofthe calorimeter trigger. The FPGA firmware on LATOME
AMC is developed, which calculates the transverse energy
with a fixed latency. We have established the first version offirmware fulfilling all requirements, and confirmed stablerunning in the hardware test. The prototype hardware will
be assembled soon and tested carefully before entering masproduction. All hardware will be verified before installation
into ATLAS by the end of 2018, then installed by 2020.

Test result on hardware (LATOME/Dev-Kit)
Tested the firmware forseveral hours.
- Checker flag = 1- Error counter = 0Generator
testbench

firmware

FIR Filtermodule

Checker
testbench

1. Input data (ADC data, coefficient and pedestal) and the calculation result by PC is stored in RAM.
2. Generator testbench provides input data for FIR Filter module.
3. Checker testbench compares the calculation result and firmware result.
à output ”checker flag” and “error counter”.

checker flag

The firmware stably works.

Confirmed the firmware works

error counter

Reference
ATLAS Collaboration, ATLAS LAr Calorimeter Phase-I upgrade TDR, CERN-LHCC-2013-017