General Chair
K. Endo (AIST)
Tel: +81-29-861-3857
endo.k@aist.go.jp
Program Chair
T. Shinada (Tohoku Univ.)
Tel: +81-22-796-3410
shinada@cies.tohoku.ac.jp
Vice Program Chair
T. Irisawa (AIST)
toshifumi1.irisawa@aist.go.jp
Program Committee

2017 Silicon Nanoelectronics Workshop
June 4-5, 2017, Rihga Royal Hotel Kyoto, Kyoto, Japan

Call for Papers
Deadline for Abstracts: March 31, 2017
General Information
The 2017 Silicon Nanoelectronics Workshop will be held at Rihga Royal HotelKyoto, Japan on June 4-5, 2016, just prior to VLSI Symposium on Technology asa satellite workshop of the VLSI Symposia. The workshop will focus on siliconrelated nanoelectronics to bridge a gap between the Si nano-technology and the"real" VLSI world. The first Silicon Nanoelectronics Workshop was held in June,
1996 at Honolulu, Hawaii, USA. The 2017 Silicon Nanoelectronics Workshop willbe the 22th in a series of annual workshops.

An Chen (IBM)Steve Chung (NCTU)
Jean Pierre Colinge (TSMC)
Shamik Das (MITRE)
Stephen Goodnick (Arizona State Univ.) Scope
The workshop will cover various aspects of VLSI-related silicon nanoelectronics.
Ru Huang (Peking Univ.)
Areas of interest include, but are not limited to:
Adrian M. Ionescu (EPFL)- Sub-10 nm transistors employing conventional and novel architecture including
Raj Jammy (Carl Zeiss)
non-classical structures, novel channel and source/drain materials, non-thermal
Kuniyuki Kakushima (Tokyo Tech)
injection mechanisms
Dong-Won Kim (Samsung Elec.)- Device physics of nanodevices including quantum effects, nonequilibrium andMasaharu Kobayashi (Univ. Tokyo)
ballistic transport- Modeling and simulation of nanoscale devices
Tejas Krishnamohan (Intel)- Extreme processing of nanostructures, including nanopatterning
Max C. Lemme (Univ. Siegen)- Junction and insulator materials and process technology for nanodevices
Pei-Wen Li (NCTU)- Nanoscale surface, interface, and heterojunction effects in nanodevices
Bunji Mizuno (Panasonic)- Device scaling issues including doping fluctuations and atomic granularity
Hiroshi Mizuta (JAIST)- Novel architectures for nanodevices including quantum computing- Optoelectronics using silicon nanostructures
Daniel Moraru (Shizuoka Univ.)- Devices for heterogeneous integration on silicon, including 2D materials, Ge andYukinori Ono (Shizuoka Univ.)
III-V, CNT, spin-based devices, MEMS and NEMS, etc.
Byung-Gook Park (Seoul Nat. Univ.)- Environmental devices which contributes to low-carbon society (wireless sensors,Wolfgang Porod (Univ. Notre Dame)energy harvesters, steep slope devices, etc.)
Enrico Prati (CNR)
Submission of Abstract
Iuliana Radu (IMEC)
Prospective authors are requested to submit a PDF file of the abstract ON-LINE
Yasuo Takahashi (Hokaido Univ.)
at http://annex.jsap.or.jp/snw/
Mitsuru Takenaka (Univ. Tokyo)
Katsuhiro Tomioka (Hokkaido Univ.)
The abstract must consist of one page of text and one page of figures. The abstract
Ken Uchida (Keio Univ.)
must include the title, the author's names, affiliation, full address, phone and FAX
Yukiharu Uraoka (NAIST)
numbers, and e-mail address. Faxed copies of the abstract will not be accepted.
Maud Vinet (Leti)

Accepted abstracts will be reproduced in the workbook exactly as received. The
deadline for abstracts is March 31, 2017.
Questions may be addressed to shinada@cies.tohoku.ac.jp (T. Shinada)

Further Information
Registration forms and hotel reservation forms will be provided in the Web site of
the 2017 VLSI Technology Symposium (http://www.vlsisymposium.org/).
Some of the accepted papers will be presented in "Poster Sessions". Further
information can be obtained at http://annex.jsap.or.jp/snw/