Document No.: FT_000053
FT232R USB UART IC Datasheet Version 2.04
Clearance No.: FTDI# 38

Future Technology Devices
International Ltd.
FT232R USB UART IC
The FT232R is a USB to serial UART
interface with the following advanced
features:•

FIFO receive and transmit buffers for high data
throughput.

•

Synchronous and asynchronous bit banginterface options with RD# and WR# strobes.

•

Single chip USB to asynchronous serial datatransfer interface.

•

Device supplied pre-programmed with unique
USB serial number.

•

Entire USB protocol handled on the chip. No
USB specific firmware programming required.

•Supports bus powered, self powered and highpower bus powered USB configurations.

•

Fully integrated 1024 bit EEPROM storing
device descriptors and CBUS I/O configuration.

•

Integrated +3.3V level converter for USB I/O.

•

Fully integrated USB termination resistors.

••

Fully integrated clock generation with noexternal crystal required plus optional clock
output selection enabling a glue-less interface
to external MCU or FPGA.

Integrated level converter on UART and CBUSfor interfacing to between +1.8V and +5V
logic.

•

True 5V/3.3V/2.8V/1.8V CMOS drive output
and TTL input.

•

Configurable I/O pin output drive strength.

•

Integrated power-on-reset circuit.

•

Fully integrated AVCC supply filtering - noexternal filtering required.

•

UART signal inversion option.

•

Data transfer rates from 300 baud to 3 Mbaud(RS422, RS485, RS232 ) at TTL levels.

•

128 byte receive buffer and 256 byte transmit
buffer utilising buffer smoothing technology toallow for high data throughput.

•

FTDI’s royalty-free Virtual Com Port (VCP) andDirect(D2XX)
drivers
eliminatetherequirement for USB driver development inmost cases.

•+3.3V (using external oscillator) to +5.25V(internal oscillator) Single Supply Operation.

•

Low operating and USB suspend current.

•

Unique USB FTDIChip-ID™ feature.

•

Low USB bandwidth consumption.

•

Configurable CBUS I/O pins.

•

UHCI/OHCI/EHCI host controller compatible.

•

Transmit and receive LED drive signals.

•

USB 2.0 Full Speed compatible.

•

UART interface support for 7 or 8 data bits, 1
or 2 stop bits and odd / even / mark / space /no parity•-40°C to 85°C extended operating temperature
range.

•

Available in compact Pb-free 28 Pin SSOP and
QFN-32 packages (both RoHS compliant).

Neither the whole nor any part of the information contained in, or the product described in this manual, may be adapted or reproduced
in any material or electronic form without the prior written consent of the copyright holder. This product and its documentation aresupplied on an as-is basis and no warranty as to their suitability for any particular purpose is either made or implied. Future Technology
Devices International Ltd will not accept any claim for damages howsoever arising as a result of use or failure of this product. Yourstatutory rights are not affected. This product or any variant of it is not intended for use in any medical appliance, device or system inwhich the failure of the product might reasonably be expected to result in personal injury. This document provides preliminary
information that may be subject to change without notice. No freedom to use patents or other intellectual property rights is implied by
the publication of this document. Future Technology Devices International Ltd, Unit 1, 2 Seaward Place, Centurion Business Park, Glasgow
G41 1HH United Kingdom. Scotland Registered Company Number: SC136640

Copyright © 2009 Future Technology Devices International Limited1

Document No.: FT_000053
FT232R USB UART IC Datasheet Version 2.04
Clearance No.: FTDI# 38

1

Typical Applications•

USB to RS232/RS422/RS485 Converters•

USB Industrial Control•

Upgrading Legacy Peripherals to USB•

USB MP3 Player Interface•

Cellular and Cordless Phone USB data transfer
cables and interfaces•

USB FLASH Card Reader and Writers•

Set Top Box PC - USB interface•

Interfacing MCU/PLD/FPGA based designs toUSB•

USB Digital Camera Interface•

USB Audio and Low Bandwidth Video datatransfer•

USB Hardware Modems•

USB Wireless Modems•

PDA to USB data transfer•

USB Bar Code Readers•

USB Smart Card Readers••

USB Instrumentation

USB Software and Hardware Encryption
Dongles

1.1 Driver Support
Royalty free VIRTUAL COM PORT
(VCP) DRIVERS for...

Royalty free D2XX Direct Drivers(USB Drivers + DLL S/W Interface)•

Windows 98, 98SE, ME, 2000, Server 2003, XP
and Server 2008•

Windows 98, 98SE, ME, 2000, Server 2003, XP
and Server 2008•

Windows XP and XP 64-bit•

Windows XP and XP 64-bit•

Windows Vista and Vista 64-bit•

Windows Vista and Vista 64-bit•

Windows XP Embedded•

Windows XP Embedded•

Windows CE 4.2, 5.0 and 6.0•

Windows CE 4.2, 5.0 and 6.0•

Mac OS 8/9, OS-X•

Linux 2.4 and greater•

Linux 2.4 and greater

The drivers listed above are all available to download for free from FTDI website (www.ftdichip.com).
Various 3rd party drivers are also available for other operating systems - see FTDI website(www.ftdichip.com) for details.
For driver installation, please refer to the application note AN232B-10.

1.2 Part Numbers
Part Number

Package

FT232RQ-xxxx

32 Pin QFNFT232RL-xxxx

28 Pin SSOP

Note: Packing codes for xxxx is:- Reel: Taped and Reel, (SSOP is 2,000pcs per reel, QFN is 6,000pcs per reel).
- Tube: Tube packing, 47pcs per tube (SSOP only)- Tray: Tray packing, 490pcs per tray (QFN only)
For example: FT232RQ-Reel is 6,000pcs taped and reel packing

1.3 USB Compliant
The FT232R is fully compliant with the USB 2.0 specification and has been given the USB-IF Test-ID (TID)
40000133.
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Clearance No.: FTDI# 38

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FT232R Block Diagram

VCC

SLEEP#

Baud Rate
Generator

48MHz

3V3OUT

USBDP

USBDM

3.3 Volt
LDO
Regulator

USB
Transceiver
with
Integrated
SeriesResistors
and 1.5K
Pullup

FIFO RX
BufferSerial Interface
Engine( SIE )

USB
Protocol Engine

UART Controller
withProgrammable
Signal Inversion

UART
FIFO Controller

DBUS0
DBUS1
DBUS2
DBUS3
DBUS4
DBUS5
DBUS6
DBUS7

CBUS0
CBUS1
CBUS2
CBUS3

Internal
EEPROMUSB DPLL

3V3OUT

FIFO TX Buffer
OSCO(optional)
OCSI(optional)Internal
12MHz
Oscillator

x4 Clock
Multiplier

RESET#

48MHz

Reset
Generator

To USB Transeiver Cell

TEST
GND

Figure 2.1 FT232R Block Diagram

For a description of each function please refer to Section 4.

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Clearance No.: FTDI# 38

Table of Contents
1

Typical Applications ........................................................................ 2
1.1

Driver Support .................................................................................... 2

1.2

Part Numbers...................................................................................... 2

Note: Packing codes for xxxx is: .................................................................. 2
1.3

USB Compliant .................................................................................... 22

FT232R Block Diagram .................................................................... 3

3

Device Pin Out and Signal Description ............................................ 6

4

5

6

7

3.1

28-LD SSOP Package .......................................................................... 6

3.2

SSOP Package Pin Out Description...................................................... 6

3.3

QFN-32 Package ................................................................................. 9

3.4

QFN-32 Package Signal Description .................................................... 9

3.5

CBUS Signal Options ......................................................................... 12

Function Description ..................................................................... 13
4.1

Key Features ..................................................................................... 13

4.2

Functional Block Descriptions ........................................................... 14

Devices Characteristics and Ratings.............................................. 16
5.1

Absolute Maximum Ratings............................................................... 16

5.2

DC Characteristics............................................................................. 17

5.3

EEPROM Reliability Characteristics ................................................... 20

5.4Internal Clock Characteristics ........................................................... 20

USB Power Configurations ............................................................ 22
6.1

USB Bus Powered Configuration ...................................................... 22

6.2

Self Powered Configuration .............................................................. 23

6.3

USB Bus Powered with Power Switching Configuration .................... 24

6.4

USB Bus Powered with Selectable External Logic Supply .................. 25

Application Examples .................................................................... 26
7.1

USB to RS232 Converter ................................................................... 26

7.2

USB to RS485 Coverter ..................................................................... 27

7.3

USB to RS422 Converter ................................................................... 28

7.4

USB to MCU UART Interface .............................................................. 29

7.5

LED Interface .................................................................................... 30

7.6

Using the External Oscillator ............................................................ 31

8Internal EEPROM Configuration .................................................... 32

9Package Parameters ..................................................................... 34
9.1

SSOP-28 Package Dimensions .......................................................... 34
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9.2

QFN-32 Package Dimensions ............................................................ 35

9.3

QFN-32 Package Typical Pad Layout ................................................. 36

9.4

QFN-32 Package Typical Solder Paste Diagram ................................. 36

9.5

Solder Reflow Profile ........................................................................ 37

10

Contact Information ................................................................... 38

Appendix A - List of Figures and Tables ..................................................... 39
Appendix B - Revision History.................................................................... 41

Copyright © 2009 Future Technology Devices International Limited

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Device Pin Out and Signal Description

3.1 28-LD SSOP Package

TXD

28

1

DTR#

4

OSCO

20

VCCIO

TXD

VCC
RXD

OSCI
16

RTS#

TEST

RTS#
15

VCCIO

AGND

RXD

USBDM
USBDP
CTS#

FT232RL

NC
8

RI#

CBUS0
19

GND

CBUS1

NC

GND

24
27
28

DSR#

VCC

DCD#

RESET#

CTS#

GND

NC

DTR#
DSR#

RESET#
NC

DCD#

OSCI
RI#

OSCO

CBUS0
CBUS1

CBUS4

3V3OUT

CBUS2

USBDM

CBUS3

15

14

USBDP

17

3V3OUT
A
G
N
D
25

G
N
D
7

G
N
D
18

T
E
S
T

G
N
D
21

CBUS2
CBUS3
CBUS4

1
5
3
11
2
9
10
6
23
22
13
14
12

26

Figure 3.1 SSOP Package Pin Out and Schematic Symbol

3.2 SSOP Package Pin Out Description
Note: The convention used throughout this document for active low signals is the signal name followed bya#
Pin No.

Name

Type

Description

15

USBDP

I/O

USB Data Signal Plus, incorporating internal series resistor and 1.5kΩ pull up
resistor to 3.3V.

16

USBDM

I/O

USB Data Signal Minus, incorporating internal series resistor.

Table 3.1 USB Interface GroupPin No.

Name

Type

Description

4

VCCIO

PWR

+1.8V to +5.25V supply to the UART Interface and CBUS group pins (1...3, 5, 6,
9...14, 22, 23). In USB bus powered designs connect this pin to 3V3OUT pin todrive out at +3.3V levels, or connect to VCC to drive out at 5V CMOS level. Thispin can also be supplied with an external +1.8V to +2.8V supply in order to drive
outputs at lower levels. It should be noted that in this case this supply should
originate from the same source as the supply to VCC. This means that in bus
powered designs a regulator which is supplied by the +5V on the USB bus should
be used.

7, 18,
21

GND

PWR

Device ground supply pins

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Pin No.

Name

Type

Description

17

3V3OUT

Output+3.3V output from integrated LDO regulator. This pin should be decoupled to
ground using a 100nF capacitor. The main use of this pin is to provide the internal+3.3V supply to the USB transceiver cell and the internal 1.5kΩ pull up resistor on
USBDP. Up to 50mA can be drawn from this pin to power external logic if
required. This pin can also be used to supply the VCCIO pin.

20

VCC

PWR

+3.3V to +5.25V supply to the device core. (see Note 1)

25

AGND

PWR

Device analogue ground supply for internal clock multiplier

Table 3.2 Power and Ground GroupPin No.

Name

Type

Description

8, 24

NC

NC

No internal connection

19

RESET#

Input

Active low reset pin. This can be used by an external device to reset the
FT232R. If not required can be left unconnected, or pulled up to VCC.

26

TEST

Input

Puts the device into IC test mode. Must be tied to GND for normal
operation, otherwise the device will appear to fail.

27

OSCI

Input

Input 12MHz Oscillator Cell. Optional – Can be left unconnected fornormal operation. (see Note 2)

28

OSCO

OutputOutput from 12MHZ Oscillator Cell. Optional – Can be left unconnected
for normal operation if internal Oscillator is used. (see Note 2)

Table 3.3 Miscellaneous Signal GroupPin No.

Name

Type

Description

1

TXD

OutputTransmit Asynchronous Data Output.

2

DTR#

OutputData Terminal Ready Control Output / Handshake Signal.

3

RTS#

OutputRequest to Send Control Output / Handshake Signal.

5

RXD

Input

Receiving Asynchronous Data Input.

6

RI#

Input

Ring Indicator Control Input. When remote wake up is enabled in theinternal EEPROM taking RI# low (20ms active low pulse) can be used toresume the PC USB host controller from suspend.

9

DSR#

Input

Data Set Ready Control Input / Handshake Signal.

10

DCD#

Input

Data Carrier Detect Control Input.

11

CTS#

Input

Clear To Send Control Input / Handshake Signal.

12

CBUS4

I/O

Configurable CBUS output only Pin. Function of this pin is configured in
the device internal EEPROM. Factory default configuration is SLEEP#. See
CBUS Signal Options, Table 3.9.

13

CBUS2

I/O

Configurable CBUS I/O Pin. Function of this pin is configured in thedevice internal EEPROM. Factory default configuration is TXDEN. See
CBUS Signal Options, Table 3.9.

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Pin No.

Name

Type

Description

14

CBUS3

I/O

Configurable CBUS I/O Pin. Function of this pin is configured in thedevice internal EEPROM. Factory default configuration is PWREN#. See
CBUS Signal Options, Table 3.9. PWREN# should be used with a 10kΩ
resistor pull up.

22

CBUS1

I/O

Configurable CBUS I/O Pin. Function of this pin is configured in thedevice internal EEPROM. Factory default configuration is RXLED#. See
CBUS Signal Options, Table 3.9.

23

CBUS0

I/O

Configurable CBUS I/O Pin. Function of this pin is configured in thedevice internal EEPROM. Factory default configuration is TXLED#. See
CBUS Signal Options, Table 3.9.

Table 3.4 UART Interface and CUSB Group (see note 3)

Notes:

1. The minimum operating voltage VCC must be +4.0V (could use VBUS=+5V) whenusing the internal clock generator. Operation at +3.3V is possible using an external
crystal oscillator.
2. Contact FTDI Technical Support for details on how to use an external crystal, ceramic
resonator, or oscillator with the FT232R.
3. When used in Input Mode, the input pins are pulled to VCCIO via internal 200kΩ
resistors. These pins can be programmed to gently pull low during USB suspend(PWREN# = “1”) by setting an option in the internal EEPROM.

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3.3 QFN-32 Package
32

25

1

1

24

FTDI

19

FT232RQ
9

15

5
12

17

13

16

26

27

28

29

30

31

VCC
USBDM
RTS#

14

25
29

25

18

32

23
27

AGND 24

1

VCCIO

NC 23

2

RXD

28

CBUS0 22

3

RI#

16

CBUS1 21

4 GND

GND 20

5 NC

VCC 196DSR#

RESET# 18

7 DCD#

GND 17

8 CTS#

USBDP
CTS#

NC

FT232RQ

NC
NC

15

14

13

12

11

10

DTR#
DSR#

NC
NC

DCD#
RI#

RESET#
NC

CBUS0

OSCI
OSCO

CBUS1

3V3OUT
A
G
N
D
24

16

TXD
RXD

YYXX-AXXXXXXX
8

VCCIO

G
N
D
4

G
N
D
17

T
E
S
T

G
N
D
20

CBUS2
CBUS3
CBUS4

30
2
32
8
31
6
7
3
22
21
10
11
9

26

9

Figure 3.2 QFN-32 Package Pin Out and schematic symbol

3.4 QFN-32 Package Signal Description
Pin No.

Name

Type

Description

14

USBDP

I/O

USB Data Signal Plus, incorporating internal series resistor and 1.5kΩ pull up resistor
to +3.3V.

15

USBDM

I/O

USB Data Signal Minus, incorporating internal series resistor.

Table 3.5 USB Interface GroupPin No.

Name

Type

Description

1

VCCIO

PWR

+1.8V to +5.25V supply for the UART Interface and CBUS group pins (2, 3,
6,7,8,9,10 11, 21, 22, 30,31,32). In USB bus powered designs connect this pin to
3V3OUT to drive out at +3.3V levels, or connect to VCC to drive out at +5V CMOS
level. This pin can also be supplied with an external +1.8V to +2.8V supply in orderto drive out at lower levels. It should be noted that in this case this supply should
originate from the same source as the supply to VCC. This means that in bus
powered designs a regulator which is supplied by the +5V on the USB bus should be
used.

4, 17,GND

PWR

Device ground supply pins.

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FT232R USB UART IC Datasheet Version 2.04
Clearance No.: FTDI# 38
Pin No.

Name

Type

Description

20

16

3V3OUT

Output+3.3V output from integrated LDO regulator. This pin should be decoupled to
ground using a 100nF capacitor. The purpose of this output is to provide theinternal +3.3V supply to the USB transceiver cell and the internal 1.5kΩ pull up
resistor on USBDP. Up to 50mA can be drawn from this pin to power external logic if
required. This pin can also be used to supply the VCCIO pin.

19

VCC

PWR

+3.3V to +5.25V supply to the device core. (See Note 1).

24

AGND

PWR

Device analogue ground supply for internal clock multiplier.

Table 3.6 Power and Ground GroupPin No.

Name

Type

Description

5, 12,
13, 23,25, 29NC

NC

No internal connection. Do not connect.

18

RESET#

Input

Active low reset. Can be used by an external device to reset the FT232R. If
not required can be left unconnected, or pulled up to VCC.

26

TEST

Input

Puts the device into IC test mode. Must be tied to GND for normal
operation, otherwise the device will appear to fail.

27

OSCI

Input

Input 12MHz Oscillator Cell. Optional – Can be left unconnected for normal
operation. (See Note 2).

28

OSCO

OutputOutput from 12MHZ Oscillator Cell. Optional – Can be left unconnected fornormal operation if internal Oscillator is used. (See Note 2).

Table 3.7 Miscellaneous Signal Group

Pin
No.

Name

Type

30

TXD

OutputTransmit Asynchronous Data Output.

31

DTR#

OutputData Terminal Ready Control Output / Handshake Signal.

32

RTS#

OutputRequest to Send Control Output / Handshake Signal.

2

RXD

Input

Receiving Asynchronous Data Input.

3

RI#

Input

Ring Indicator Control Input. When remote wake up is enabled in the internal
EEPROM taking RI# low (20ms active low pulse) can be used to resume the
PC USB host controller from suspend.

6

DSR#

Input

Data Set Ready Control Input / Handshake Signal.

7

DCD#

Input

Data Carrier Detect Control Input.

8

CTS#

Input

Clear To Send Control Input / Handshake Signal.

9

CBUS4

I/O

Configurable CBUS output only Pin. Function of this pin is configured in thedevice internal EEPROM. Factory default configuration is SLEEP#. See CBUS

Description

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Pin
No.

Name

Type

Description
Signal Options, Table 3.9.

10

CBUS2

I/O

Configurable CBUS I/O Pin. Function of this pin is configured in the device
internal EEPROM. Factory default configuration is TXDEN. See CBUS Signal
Options, Table 3.9.

11

CBUS3

I/O

Configurable CBUS I/O Pin. Function of this pin is configured in the device
internal EEPROM. Factory default configuration is PWREN#. See CBUS Signal
Options, Table 3.9. PWREN# should be used with a 10kΩ resistor pull up.

21

CBUS1

I/O

Configurable CBUS I/O Pin. Function of this pin is configured in the device
internal EEPROM. Factory default configuration is RXLED#. See CBUS Signal
Options, Table 3.9.

22

CBUS0

I/O

Configurable CBUS I/O Pin. Function of this pin is configured in the device
internal EEPROM. Factory default configuration is TXLED#. See CBUS Signal
Options, Table 3.9.

Table 3.8 UART Interface and CBUS Group (see note 3)

Notes:

1. The minimum operating voltage VCC must be +4.0V (could use VBUS=+5V) whenusing the internal clock generator. Operation at +3.3V is possible using an external
crystal oscillator.
2. Contact FTDI Technical Support for details on how to use an external crystal, ceramic
resonator, or oscillator with the FT232R.
3. When used in Input Mode, the input pins are pulled to VCCIO via internal 200kΩ
resistors. These pins can be programmed to gently pull low during USB suspend (PWREN# = “1”) by setting an option in the internal EEPROM.

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3.5 CBUS Signal Options
The following options can be configured on the CBUS I/O pins. CBUS signal options are common to both
package versions of the FT232R. These options can be configured in the internal EEPROM using thesoftware utility MPROG, which can be downloaded from the FTDI Utilities (www.ftdichip.com) . The
default configuration is described in Section 8.
CBUS
SignalOptionAvailable On CBUS Pin

TXDEN

CBUS0, CBUS1, CBUS2, CBUS3, CBUS4

Enable transmit data for RS485

PWREN#

CBUS0, CBUS1, CBUS2, CBUS3, CBUS4

Output is low after the device has been configured
by USB, then high during USB suspend mode. This
output can be used to control power to external
logic P-Channel logic level MOSFET switch. Enable
the interface pull-down option when using the
PWREN# in this way.*

TXLED#

CBUS0, CBUS1, CBUS2, CBUS3, CBUS4

Transmit data LED drive – pulses low whentransmitting data via USB. See Section 7.5 for moredetails.

RXLED#

CBUS0, CBUS1, CBUS2, CBUS3, CBUS4

Receive data LED drive – pulses low when receiving
data via USB. See Section 7.5 for more details.

TX&RXLED#

CBUS0, CBUS1, CBUS2, CBUS3, CBUS4

LED drive – pulses low when transmitting or
receiving data via USB. See Section 7.5 for moredetails.

SLEEP#

CBUS0, CBUS1, CBUS2, CBUS3, CBUS4

Goes low during USB suspend mode. Typically used
to power down an external TTL to RS232 level
converter IC in USB to RS232 converter designs.

CLK48

CBUS0, CBUS1, CBUS2, CBUS3, CBUS4

48MHz Clock output.**

CLK24

CBUS0, CBUS1, CBUS2, CBUS3, CBUS4

24 MHz Clock output.**

CLK12

CBUS0, CBUS1, CBUS2, CBUS3, CBUS4

12 MHz Clock output.**

CLK6

CBUS0, CBUS1, CBUS2, CBUS3, CBUS4

6 MHz Clock output.**

Description

CBitBangI/O

CBUS0, CBUS1, CBUS2, CBUS3

CBUS bit bang mode option. Allows up to 4 of the
CBUS pins to be used as general purpose I/O.
Configured individually for CBUS0, CBUS1, CBUS2and CBUS3 in the internal EEPROM. A separate
application note, AN232R-01, available from FTDI
website (www.ftdichip.com) describes in more detail
how to use CBUS bit bang mode.

BitBangWRn

CBUS0, CBUS1, CBUS2, CBUS3

Synchronous and asynchronous bit bang mode WR#
strobe output.

BitBangRDn

CBUS0, CBUS1, CBUS2, CBUS3

Synchronous and asynchronous bit bang mode RD#
strobe output.

Table 3.9 CBUS Configuration Control* PWREN# should be used with a 10kΩ resistor pull up.
**When in USB suspend mode the outputs clocks are also suspended.

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4

Function Description

The FT232R is a USB to serial UART interface device which simplifies USB to serial designs and reduces
external component count by fully integrating an external EEPROM, USB termination resistors and an
integrated clock circuit which requires no external crystal, into the device. It has been designed tooperate efficiently with a USB host controller by using as little as possible of the total USB bandwidthavailable.

4.1 Key Features
Functional Integration. Fully integrated EEPROM, USB termination resistors, clock generation, AVCC
filtering, POR and LDO regulator.
Configurable CBUS I/O Pin Options. The fully integrated EEPROM allows configuration of the Control
Bus (CBUS) functionality, signal inversion and drive strength selection. There are 5 configurable CBUS
I/O pins. These configurable options are

1.
2.
3.
4.
5.
6.
7.

TXDEN - transmit enable for RS485 designs.
PWREN# - Power control for high power, bus powered designs.
TXLED# - for pulsing an LED upon transmission of data.
RXLED# - for pulsing an LED upon receiving data.
TX&RXLED# - which will pulse an LED upon transmission OR reception of data.
SLEEP# - indicates that the device going into USB suspend mode.
CLK48 / CLK24 / CLK12 / CLK6 - 48MHz, 24MHz, 12MHz, and 6MHz clock output
signal options.

The CBUS pins can also be individually configured as GPIO pins, similar to asynchronous bit bang mode.
It is possible to use this mode while the UART interface is being used, thus providing up to 4 general
purpose I/O pins which are available during normal operation. An application note, AN232R-01, available
from FTDI website (www.ftdichip.com) describes this feature.
The CBUS lines can be configured with any one of these output options by setting bits in the internal
EEPROM. The device is supplied with the most commonly used pin definitions pre-programmed - see
Section 8 for details.
Asynchronous Bit Bang Mode with RD# and WR# Strobes. The FT232R supports FTDI’s previous
chip generation bit-bang mode. In bit-bang mode, the eight UART lines can be switched from the regularinterface mode to an 8-bit general purpose I/O port. Data packets can be sent to the device and they will
be sequentially sent to the interface at a rate controlled by an internal timer (equivalent to the baud rate
pre-scaler). With the FT232R device this mode has been enhanced by outputting the internal RD# andWR# strobes signals which can be used to allow external logic to be clocked by accesses to the bit-bang
I/O bus. This option will be described more fully in a separate application note available from FTDI
website (www.ftdichip.com).
Synchronous Bit Bang Mode. The FT232R supports synchronous bit bang mode. This mode differs fromasynchronous bit bang mode in that the interface pins are only read when the device is written to. This
makes it easier for the controlling program to measure the response to an output stimulus as the data
returned is synchronous to the output data. An application note, AN232R-01, available from FTDI website(www.ftdichip.com) describes this feature.
FTDIChip-ID™. The FT232R also includes the new FTDIChip-ID™ security dongle feature. ThisFTDIChip-ID™ feature allows a unique number to be burnt into each device during manufacture. This
number cannot be reprogrammed. This number is only readable over USB and forms a basis of a security
dongle which can be used to protect any customer application software being copied. This allows thepossibility of using the FT232R in a dongle for software licensing. Further to this, a renewable license
scheme can be implemented based on the FTDIChip-ID™ number when encrypted with other information.
This encrypted number can be stored in the user area of the FT232R internal EEPROM, and can bedecrypted, then compared with the protected FTDIChip-ID™ to verify that a license is valid. Web based
applications can be used to maintain product licensing this way. An application note, AN232R-02,
available from FTDI website (www.ftdichip.com) describes this feature.
The FT232R is capable of operating at a voltage supply between +3.3V and +5V with a nominal
operational mode current of 15mA and a nominal USB suspend mode current of 70µA. This allows greater
margin for peripheral designs to meet the USB suspend mode current limit of 2.5mA. An integrated level
converter within the UART interface allows the FT232R to interface to UART logic running at +1.8V, 2.5V,+3.3V or +5V.
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4.2 Functional Block Descriptions
The following paragraphs detail each function within the FT232R. Please refer to the block diagram shownin Figure 2.1.
Internal EEPROM. The internal EEPROM in the FT232R is used to store USB Vendor ID (VID), Product ID(PID), device serial number, product description string and various other USB configuration descriptors.
The internal EEPROM is also used to configure the CBUS pin functions. The FT232R is supplied with theinternal EEPROM pre-programmed as described in Section 8. A user area of the internal EEPROM isavailable to system designers to allow storing additional data. The internal EEPROM descriptors can be
programmed in circuit, over USB without any additional voltage requirement. It can be programmedusing the FTDI utility software called MPROG, which can be downloaded from FTDI Utilities on the FTDI
website (www.ftdichip.com).
+3.3V LDO Regulator. The +3.3V LDO regulator generates the +3.3V reference voltage for driving theUSB transceiver cell output buffers. It requires an external decoupling capacitor to be attached to the
3V3OUT regulator output pin. It also provides +3.3V power to the 1.5kΩ internal pull up resistor on
USBDP. The main function of the LDO is to power the USB Transceiver and the Reset Generator Cells
rather than to power external logic. However, it can be used to supply external circuitry requiring a+3.3V nominal supply with a maximum current of 50mA.
USB Transceiver. The USB Transceiver Cell provides the USB 1.1 / USB 2.0 full-speed physical interface
to the USB cable. The output drivers provide +3.3V level slew rate control signalling, whilst a differential
input receiver and two single ended input receivers provide USB data in, Single-Ended-0 (SE0) and USB
reset detection conditions respectfully. This function also incorporates the internal USB series termination
resistors on the USB data lines and a 1.5kΩ pull up resistor on USBDP.
USB DPLL. The USB DPLL cell locks on to the incoming NRZI USB data and generates recovered clock
and data signals for the Serial Interface Engine (SIE) block.
Internal 12MHz Oscillator - The Internal 12MHz Oscillator cell generates a 12MHz reference clock. This
provides an input to the x4 Clock Multiplier function. The 12MHz Oscillator is also used as the reference
clock for the SIE, USB Protocol Engine and UART FIFO controller blocks.
Clock Multiplier / Divider. The Clock Multiplier / Divider takes the 12MHz input from the Internal
Oscillator function and generates the 48MHz, 24MHz, 12MHz and 6MHz reference clock signals. The 48Mz
clock reference is used by the USB DPLL and the Baud Rate Generator blocks.
Serial Interface Engine (SIE). The Serial Interface Engine (SIE) block performs the parallel to serialand serial to parallel conversion of the USB data. In accordance with the USB 2.0 specification, it
performs bit stuffing/un-stuffing and CRC5/CRC16 generation. It also checks the CRC on the USB data
stream.
USB Protocol Engine. The USB Protocol Engine manages the data stream from the device USB control
endpoint. It handles the low level USB protocol requests generated by the USB host controller and thecommands for controlling the functional parameters of the UART in accordance with the USB 2.0
specification chapter 9.
FIFO RX Buffer (128 bytes). Data sent from the USB host controller to the UART via the USB data OUT
endpoint is stored in the FIFO RX (receive) buffer. Data is removed from the buffer to the UART transmit
register under control of the UART FIFO controller. (Rx relative to the USB interface).
FIFO TX Buffer (256 bytes). Data from the UART receive register is stored in the TX buffer. The USB
host controller removes data from the FIFO TX Buffer by sending a USB request for data from the device
data IN endpoint. (Tx relative to the USB interface).
UART FIFO Controller. The UART FIFO controller handles the transfer of data between the FIFO RX and
TX buffers and the UART transmit and receive registers.
UART Controller with Programmable Signal Inversion and High Drive. Together with the UARTFIFO Controller the UART Controller handles the transfer of data between the FIFO RX and FIFO TX
buffers and the UART transmit and receive registers. It performs asynchronous 7 or 8 bit parallel to serialand serial to parallel conversion of the data on the RS232 (or RS422 or RS485) interface.
Control signals supported by UART mode include RTS, CTS, DSR, DTR, DCD and RI. The UART Controller
also provides a transmitter enable control signal pin option (TXDEN) to assist with interfacing to RS485
transceivers. RTS/CTS, DSR/DTR and XON / XOFF handshaking options are also supported. Handshaking
is handled in hardware to ensure fast response times. The UART interface also supports the RS232
BREAK setting and detection conditions.

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Additionally, the UART signals can each be individually inverted and have a configurable high drive
strength capability. Both these features are configurable in the EEPROM.
Baud Rate Generator - The Baud Rate Generator provides a 16x clock input to the UART Controller
from the 48MHz reference clock. It consists of a 14 bit pre-scaler and 3 register bits which provide finetuning of the baud rate (used to divide by a number plus a fraction or “sub-integer”). This determines thebaud rate of the UART, which is programmable from 183 baud to 3 Mbaud.
The FT232R supports all standard baud rates and non-standard baud rates from 183 Baud up to 3
Mbaud. Achievable non-standard baud rates are calculated as follows Baud Rate = 3000000 / (n + x)
where ‘n’ can be any integer between 2 and 16,384 ( = 2 ) and ‘x’ can be a sub-integer of the value 0,0.125, 0.25, 0.375, 0.5, 0.625, 0.75, or 0.875. When n = 1, x = 0, i.e. baud rate divisors with values
between 1 and 2 are not possible.
14This gives achievable baud rates in the range 183.1 baud to 3,000,000 baud. When a non-standard baudrate is required simply pass the required baud rate value to the driver as normal, and the FTDI driver willcalculate the required divisor, and set the baud rate. See FTDI application note AN232B-05 on the FTDI
website (www.ftdichip.com) for more details.
RESET Generator - The integrated Reset Generator Cell provides a reliable power-on reset to the device
internal circuitry at power up. The RESET# input pin allows an external device to reset the FT232R.
RESET# can be tied to VCC or left unconnected if not being used.

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5

Devices Characteristics and Ratings

5.1 Absolute Maximum Ratings
The absolute maximum ratings for the FT232R devices are as follows. These are in accordance with the
Absolute Maximum Rating System (IEC 60134). Exceeding these may cause permanent damage to thedevice.
Parameter

Value

Unit

Storage Temperature-65°C to 150°C

Degrees C

Floor Life (Out of Bag) At Factory Ambient

168 Hours(30°C / 60% Relative Humidity)(IPC/JEDEC J-STD-033A MSL Level 3
Compliant)*

Hours

Ambient Temperature (Power Applied)-40°C to 85°C

Degrees C

MTTF FT232RL

11162037

hours

MTTF FT232RQ

4464815hours

VCC Supply Voltage-0.5 to +6.00

V

DC Input Voltage – USBDP and USBDM-0.5 to +3.8

V

DC Input Voltage – High Impedance
Bidirectionals-0.5 to + (VCC +0.5)

V

DC Input Voltage – All Other Inputs-0.5 to + (VCC +0.5)

V

DC Output Current – Outputs

24

mA

DC Output Current – Low Impedance
Bidirectionals

24

mA

Power Dissipation (VCC = 5.25V)

500

mW

Table 5.1 Absolute Maximum Ratings* If devices are stored out of the packaging beyond this time limit the devices should be baked before
use. The devices should be ramped up to a temperature of +125°C and baked for up to 17 hours.

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5.2 DC Characteristics
DC Characteristics (Ambient Temperature = -40°C to +85°C)
Parameter

Description

Minimum

TypicalMaximum

Units

Conditions

VCC1

VCC Operating Supply
Voltage

4.0

---

5.25

V

Using Internal
Oscillator

VCC1

VCC Operating Supply
Voltage

3.3

---

5.25

V

Using External
CrystalVCC2

VCCIO Operating
Supply Voltage

1.8

---

5.25

V

Icc1

Operating Supply
Current

---

15

---

mA

Normal Operation

Icc2

Operating Supply
Current

50

70

100

µA

USB Suspend

3V3

3.3v regulator output

3.0

3.3

3.6

V

Table 5.2 Operating Voltage and Current

Parameter

Description

Minimum

TypicalMaximum

Units

Conditions

Voh

Output Voltage High

3.2

4.1

4.9

V

I source = 2mA

Vol

Output Voltage Low

0.3

0.4

0.6

V

I sink = 2mA

Vin

Input SwitchingThreshold

1.0

1.2

1.5

V

**

VHys

Input Switching
Hysteresis

20

25

30

mV

**

Table 5.3 UART and CBUS I/O Pin Characteristics (VCCIO = +5.0V, Standard Drive Level)

Parameter

Description

Minimum

TypicalMaximum

Units

Conditions

Voh

Output Voltage High

2.2

2.7

3.2

V

I source = 1mA

Vol

Output Voltage Low

0.3

0.4

0.5

V

I sink = 2mA

Vin

Input SwitchingThreshold

1.0

1.2

1.5

V

**

VHys

Input Switching
Hysteresis

20

25

30

mV

**

Table 5.4 UART and CBUS I/O Pin Characteristics (VCCIO = +3.3V, Standard Drive Level)

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Parameter

Description

Minimum

TypicalMaximum

Units

Conditions

Voh

Output Voltage High

2.1

2.6

2.8

V

I source = 1mA

Vol

Output Voltage Low

0.3

0.4

0.5

V

I sink = 2mA

Vin

Input SwitchingThreshold

1.0

1.2

1.5

V

**

VHys

Input Switching
Hysteresis

20

25

30

mV

**

Table 5.5 UART and CBUS I/O Pin Characteristics (VCCIO = +2.8V, Standard Drive Level)

Parameter

Description

Minimum

TypicalMaximum

Units

Conditions

Voh

Output Voltage High

1.32

1.62

1.8

V

I source = 0.2mA

Vol

Output Voltage Low

0.06

0.1

0.18

V

I sink = 0.5mA

Vin

Input SwitchingThreshold

1.0

1.2

1.5

V

**

VHys

Input Switching
Hysteresis

20

25

30

mV

**

Table 5.6 UART and CBUS I/O Pin Characteristics (VCCIO = +1.8V, Standard Drive Level)

Parameter

Description

Minimum

TypicalMaximum

Units

Conditions

Voh

Output Voltage High

3.2

4.1

4.9

V

I source = 6mA

Vol

Output Voltage Low

0.3

0.4

0.6

V

I sink = 6mA

Vin

Input SwitchingThreshold

1.0

1.2

1.5

V

**

VHys

Input Switching
Hysteresis

20

25

30

mV

**

Table 5.7 UART and CBUS I/O Pin Characteristics (VCCIO = +5.0V, High Drive Level)

Parameter

Description

Minimum

TypicalMaximum

Units

Conditions

Voh

Output Voltage High

2.2

2.8

3.2

V

I source = 3mA

Vol

Output Voltage Low

0.3

0.4

0.6

V

I sink = 8mA

Vin

Input SwitchingThreshold

1.0

1.2

1.5

V

**

VHys

Input Switching
Hysteresis

20

25

30

mV

**

Table 5.8 UART and CBUS I/O Pin Characteristics (VCCIO = +3.3V, High Drive Level)

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Parameter

Description

Minimum

TypicalMaximum

Units

Conditions

Voh

Output Voltage High

2.1

2.6

2.8

V

I source = 3mA

Vol

Output Voltage Low

0.3

0.4

0.6

V

I sink = 8mA

Vin

Input SwitchingThreshold

1.0

1.2

1.5

V

**

VHys

Input Switching
Hysteresis

20

25

30

mV

**

Table 5.9 UART and CBUS I/O Pin Characteristics (VCCIO = +2.8V, High Drive Level)

Parameter

Description

Minimum

TypicalMaximum

Units

Conditions

Voh

Output Voltage High

1.35

1.67

1.8

V

I source = 0.4mA

Vol

Output Voltage Low

0.12

0.18

0.35

V

I sink = 3mA

Vin

Input SwitchingThreshold

1.0

1.2

1.5

V

**

VHys

Input Switching
Hysteresis

20

25

30

mV

**

Table 5.10 UART and CBUS I/O Pin Characteristics (VCCIO = +1.8V, High Drive Level)** Only input pins have an internal 200KΩ pull-up resistor to VCCIO

Parameter

Description

Minimum

TypicalMaximum

Units

Vin

Input SwitchingThreshold

1.3

1.6

1.9

V

VHys

Input Switching
Hysteresis

50

55

60

mV

Conditions

Table 5.11 RESET# and TEST Pin Characteristics

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Parameter

Description

MinimumUVoh

I/O Pins Static Output(High)

UVol

TypicalMaximum

Units

Conditions

2.8

3.6

V

RI = 1.5kΩ to
3V3OUT (D+) RI =15KΩ to GND (D-)

I/O Pins Static Output
(Low)

0

0.3

V

RI = 1.5kΩ to
3V3OUT (D+) RI =15kΩ to GND (D-)

UVseSingle Ended Rx
Threshold

0.8

2.0

V

UCom

Differential Common
Mode

0.8

2.5

V

UVDif

Differential Input
Sensitivity

0.2

UDrvZ

Driver Output
Impedance

26

V

29

44

Ohms

See Note 1

Table 5.12 USB I/O Pin (USBDP, USBDM) Characteristics

5.3 EEPROM Reliability Characteristics
The internal 1024 Bit EEPROM has the following reliability characteristics:
Parameter

Value

Unit

Data Retention

15

Years

Read / Write Cycle

100,000

CyclesTable 5.13 EEPROM Characteristics

5.4 Internal Clock Characteristics
The internal Clock Oscillator has the following characteristics:
Value
Parameter

Unit
Minimum

TypicalMaximum

Frequency of Operation(see Note 1)

11.98

12.00

12.02

MHz

Clock Period

83.19

83.33

83.47

ns

Duty Cycle

45

50

55

%

Table 5.14 Internal Clock Characteristics

Note 1: Equivalent to +/-1667ppm

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Parameter

Description

Minimum

TypicalMaximum

Units

Conditions

Voh

Output Voltage High

2.1

2.8

3.2

V

I source =
3mA

Vol

Output Voltage Low

0.3

0.4

0.6

V

I sink = 8mA

Vin

Input Switching Threshold

1.0

1.2

1.5

V

Table 5.15 OSCI, OSCO Pin Characteristics – see Note 1

Note1: When supplied, the FT232R is configured to use its internal clock oscillator. These characteristics
only apply when an external oscillator or crystal is used.

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6

USB Power Configurations

The following sections illustrate possible USB power configurations for the FT232R. The illustrations haveomitted pin numbers for ease of understanding since the pins differ between the FT232RL and FT232RQ
package options.
All USB power configurations illustrated apply to both package options for the FT232R device. Please refer
to Section 3 for the package option pin-out and signal descriptions.

6.1 USB Bus Powered Configuration
Vcc

Ferrite
Bead

1

TXD
VCC
RXD

2

USBDM

3

USBDP

RTS#
CTS#
4
10nF +VCCIO

FT232R

DTR#

NC

5

DSR#

RESET#SHIELD

NC

DCD#

OSCI
RI#

OSCO

GND

CBUS0
Vcc
CBUS1
100nF

4.7uF +

100nF

GND

3V3OUT
A
G
N
D

G
N
D

G
N
D

G
N
D

T
E
S
T

CBUS2
CBUS3
CBUS4

GND

GND

Figure 6.1 Bus Powered Configuration

Figure 6.1 Illustrates the FT232R in a typical USB bus powered design configuration. A USB bus powered
device gets its power from the USB bus. Basic rules for USB bus power devices are as follows –

i)
ii)
iii)

iv)
v)

On plug-in to USB, the device should draw no more current than 100mA.
In USB Suspend mode the device should draw no more than 2.5mA.
A bus powered high power USB device (one that draws more than 100mA) should
use one of the CBUS pins configured as PWREN# and use it to keep the current
below 100mA on plug-in and 2.5mA on USB suspend.
A device that consumes more than 100mA cannot be plugged into a USB bus
powered hub.
No device can draw more than 500mA from the USB bus.

The power descriptors in the internal EEPROM of the FT232R should be programmed to match the current
drawn by the device.
A ferrite bead is connected in series with the USB power supply to reduce EMI noise from the FT232R andassociated circuitry being radiated down the USB cable to the USB host. The value of the Ferrite Beaddepends on the total current drawn by the application. A suitable range of Ferrite Beads is available from
Steward (www.steward.com), for example Steward Part # MI0805K400R-10.
Note: If using PWREN# (available using the CBUS) the pin should be pulled to VCCIO using a 10kΩ
resistor.

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6.2 Self Powered Configuration
TXD
VCC = 3.3V - 5V

1

VCC
RXD

2

USBDM

3

USBDP

RTS#
CTS#
4
VCCIO

4k7

FT232R

DTR#

NC

5

DSR#

RESET#SHIELD

NC
GND

10k

DCD#

OSCI
RI#

OSCO
GND

CBUS0

VCC
CBUS1
100nF

100nF

4.7uF +

100nF

GND

3V3OUT
A
G
N
D

G
N
D

G
N
D

G
N
D

T
E
S
T

CBUS2
CBUS3
CBUS4

GND

GND

Figure 6.2 Self Powered Configuration

Figure 6.2 illustrates the FT232R in a typical USB self powered configuration. A USB self powered device
gets its power from its own power supply, VCC, and does not draw current from the USB bus. The basic
rules for USB self powered devices are as follows –

i)
ii)
iii)

A self powered device should not force current down the USB bus when the USB
host or hub controller is powered down.
A self powered device can use as much current as it needs during normal operationand USB suspend as it has its own power supply.
A self powered device can be used with any USB host, a bus powered USB hub or aself powered USB hub.

The power descriptor in the internal EEPROM of the FT232R should be programmed to a value of zero(self powered).
In order to comply with the first requirement above, the USB bus power (pin 1) is used to control the
RESET# pin of the FT232R device. When the USB host or hub is powered up an internal 1.5kΩ resistor on
USBDP is pulled up to +3.3V (generated using the 4K7 and 10k resistor network), thus identifying thedevice as a full speed device to the USB host or hub. When the USB host or hub is powered off, RESET#
will be low and the FT232R is held in reset. Since RESET# is low, the internal 1.5kΩ resistor is not pulled
up to any power supply (hub or host is powered down), so no current flows down USBDP via the 1.5kΩ
pull-up resistor. Failure to do this may cause some USB host or hub controllers to power up erratically.
Figure 6.2 illustrates a self powered design which has a +3.3V to +5V supply. Any design whichinterfaces to +3.3 V or +1.8V logic would differ from Figure 6.2 by having a +3.3V or +1.8V supply to
VCCIO. In this case the VCC operates over the range +3.3V to +5V supply to VCC
Note:

1. When the FT232R is in reset, the UART interface I/O pins are tri-stated. Input pins haveinternal 200kΩ pull-up resistors to VCCIO, so they will gently pull high unless driven bysome external logic.
2. When using internal FT232R oscillator the VCC supply voltage range must be aminimum of +4.0V.

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6.3 USB Bus Powered with Power Switching Configuration

Figure 6.3 Bus Powered with Power Switching Configuration

A requirement of USB bus powered applications, is when in USB suspend mode, the application draws atotal current of less than 2.5mA. This requirement includes external logic. Some external logic has theability to power itself down into a low current state by monitoring the PWREN# signal. For external logic
that cannot power itself down in this way, the FT232R provides a simple but effective method of turning
off power during the USB suspend mode.
Figure 6.3 shows an example of using a discrete P-Channel MOSFET to control the power to external
logic. A suitable device to do this is an International Rectifier (www.irf.com) IRLML6402, or equivalent. It
is recommended that a “soft start” circuit consisting of a 1kΩ series resistor and a 0.1µF capacitor is used
to limit the current surge when the MOSFET turns on. Without the soft start circuit it is possible that thetransient power surge, caused when the MOSFET switches on, will reset the FT232R or the USB host/hub
controller. The soft start circuit example shown in Figure 6.3 powers up with a slew rate of
approximaely12.5V/ms. Thus supply voltage to external logic transitions from GND to +5V inapproximately 400 microseconds.
As an alternative to the MOSFET, a dedicated power switch IC with inbuilt “soft-start” can be used. A
suitable power switch IC for such an application is the Micrel (www.micrel.com) MIC2025-2BM or
equivalent.
With power switching controlled designs the following should be noted:i)

The external logic to which the power is being switched should have its own reset circuitry toautomatically reset the logic when power is re-applied when moving out of suspend mode.

ii) Set the Pull-down on Suspend option in the internal FT232R EEPROM.
iii) One of the CBUS Pins should be configured as PWREN# in the internal FT232R EEPROM, and used
to switch the power supply to the external circuitry. This should be pulled high through a 10 kΩ
resistor.
iv) For USB high-power bus powered applications (one that consumes greater than 100mA, and up
to 500mA of current from the USB bus), the power consumption of the application must be set in
the Max Power field in the internal FT232R EEPROM. A high-power bus powered application uses
the descriptor in the internal FT232R EEPROM to inform the system of its power requirements.
v) PWREN# gets its VCC from VCCIO. For designs using 3V3 logic, ensure VCCIO is not powered
down using the external logic. In this case use the +3V3OUT.
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6.4 USB Bus Powered with Selectable External Logic Supply
3.3V or 5V
Supply toExternal Logic

VCCIO

Vcc

100nF

Ferrite
Bead

1

TXD
VCC
RXD

2

USBDM

3

USBDP

RTS#
CTS#
1

4

10nF +
5

2

VCCIO

3

NC

NC

DCD#

OSCI

GND

RI#

OSCO
Vcc

100nF

DTR#
DSR#

RESET#

JumperSHIELDFT232R

VCCIO

CBUS0

4.7uF +CBUS1
3V3OUT
A
G
N
D

100nF

G
N
D

G
N
D

G
N
D

T
E
S
T

10K

CBUS2
CBUS3
CBUS4

PWREN#SLEEP#

GND
GND

GND

Figure 6.4 USB Bus Powered with +3.3V or +5V External Logic Power Supply

Figure 6.4 illustrates a USB bus power application with selectable external logic supply. The external logic
can be selected between +3.3V and +5V using the jumper switch. This jumper is used to allow the
FT232R to be interfaced with a +3.3V or +5V logic devices. The VCCIO pin is either supplied with +5Vfrom the USB bus (jumper pins1 and 2 connected), or from the +3.3V output from the FT232R 3V3OUT
pin (jumper pins 2 and 3 connected). The supply to VCCIO is also used to supply external logic.
With bus powered applications, the following should be noted:

i)

ii)

To comply with the 2.5mA current supply limit during USB suspend mode, PWREN#
or SLEEP# signals should be used to power down external logic in this mode. If thisis not possible, use the configuration shown in Section 6.3.
The maximum current sourced from the USB bus during normal operation should
not exceed 100mA, otherwise a bus powered design with power switching (Section
6.3) should be used.

Another possible configuration could use a discrete low dropout (LDO) regulator which is supplied by the
5V on the USB bus to supply between +1.8V and +2.8V to the VCCIO pin and to the external logic. In
this case VCC would be supplied with the +5V from the USB bus and the VCCIO would be supplied fromthe output of the LDO regulator. This results in the FT232R I/O pins driving out at between +1.8V and+2.8V logic levels.
For a USB bus powered application, it is important to consider the following when selecting the regulator:i)ii)

The regulator must be capable of sustaining its output voltage with an input voltageof +4.35V. An Low Drop Out (LDO) regulator should be selected.
The quiescent current of the regulator must be low enough to meet the total current
requirement of <= 2.5mA during USB suspend mode.

A suitable series of LDO regulators that meets these requirements is the MicroChip/Telcom(www.microchip.com) TC55 series of devices. These devices can supply up to 250mA current and have aquiescent current of under 1µA.

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7

Application Examples

The following sections illustrate possible applications of the FT232R. The illustrations have omitted pinnumbers for ease of understanding since the pins differ between the FT232RL and FT232RQ package
options.

7.1 USB to RS232 Converter

Figure 7.1 Application Example showing USB to RS232 Converter

An example of using the FT232R as a USB to RS232 converter is illustrated in Figure 7.1. In thisapplication, a TTL to RS232 Level Converter IC is used on the serial UART interface of the FT232R toconvert the TTL levels of the FT232R to RS232 levels. This level shift can be done using the popular “213”series of TTL to RS232 level converters. These “213” devices typically have 4 transmitters and 5 receivers
in a 28-LD SSOP package and feature an in-built voltage converter to convert the +5V (nominal) VCC tothe +/- 9 volts required by RS232. A useful feature of these devices is the SHDN# pin which can be used
to power down the device to a low quiescent current during USB suspend mode.
A suitable level shifting device is the Sipex SP213EHCA which is capable of RS232 communication at up
to 500k baud. If a lower baud rate is acceptable, then several pin compatible alternatives are available
such as the Sipex SP213ECA, the Maxim MAX213CAI and the Analogue Devices ADM213E, which are all
suitable for communication at up to 115.2k baud. If a higher baud rate is required, the Maxim
MAX3245CAI device is capable of RS232 communication rates up to 1Mbaud. Note that the MAX3245 is
not pin compatible with the 213 series devices and that the SHDN pin on the MAX device is active highand should be connect to PWREN# pin instead of SLEEP# pin.
In example shown, the CBUS0 and CBUS1 have been configured as TXLED# and RXLED# and are being
used to drive two LEDs.

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7.2 USB to RS485 Coverter

Figure 7.2 Application Example Showing USB to RS485 Converter

An example of using the FT232R as a USB to RS485 converter is shown in Figure 7.2. In this application,a TTL to RS485 level converter IC is used on the serial UART interface of the FT232R to convert the TTL
levels of the FT232R to RS485 levels.
This example uses the Sipex SP481 device. Equivalent devices are available from Maxim and Analogue
Devices. The SP481 is a RS485 device in a compact 8 pin SOP package. It has separate enables on boththe transmitter and receiver. With RS485, the transmitter is only enabled when a character is beingtransmitted from the UART. The TXDEN signal CBUS pin option on the FT232R is provided for exactly thispurpose and so the transmitter enable is wired to CBUS2 which has been configured as TXDEN. Similarly,
CBUS3 has been configured as PWREN#. This signal is used to control the SP481’s receiver enable. The
receiver enable is active low, so it is wired to the PWREN# pin to disable the receiver when in USB
suspend mode. CBUS2 = TXDEN and CBUS3 = PWREN# are the default device configurations of theFT232R pins.
RS485 is a multi-drop network; so many devices can communicate with each other over a two wire cableinterface. The RS485 cable requires to be terminated at each end of the cable. A link (which provides the120Ω termination) allows the cable to be terminated if the SP481 is physically positioned at either end of
the cable.
In this example the data transmitted by the FT232R is also present on the receive path of the SP481.This
is a common feature of RS485 and requires the application software to remove the transmitted data fromthe received data stream. With the FT232R it is possible to do this entirely in hardware by modifying theexample shown in Figure 7.2 by logically OR’ing the FT232R TXDEN and the SP481 receiver output andconnecting the output of the OR gate to the RXD of the FT232R.
Note that the TXDEN is activated 1 bit period before the start bit. TXDEN is deactivated at the same timeas the stop bit. This is not configurable.

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7.3 USB to RS422 Converter

Figure 7.3 USB to RS422 Converter Configuration

An example of using the FT232R as a USB to RS422 converter is shown in Figure 7.3. In this application,
two TTL to RS422 Level Converter ICs are used on the serial UART interface of the FT232R to convert the
TTL levels of the FT232R to RS422 levels. There are many suitable level converter devices available. This
example uses Sipex SP491 devices which have enables on both the transmitter and receiver. Since theSP491 transmitter enable is active high, it is connected to a CBUS pin in SLEEP# configuration. The
SP491 receiver enable is active low and is therefore connected to a CBUS pin PWREN# configuration. This
ensures that when both the SP491 transmitters and receivers are enabled then the device is active, andwhen the device is in USB suspend mode, the SP491 transmitters and receivers are disabled. If a similar
application is used, but the design is USB BUS powered, it may be necessary to use a P-Channel logic
level MOSFET (controlled by PWREN#) in the VCC line of the SP491 devices to ensure that the USB
standby current of 2.5mA is met.
The SP491 is specified to transmit and receive data at a rate of up to 5 Mbaud. In this example themaximum data rate is limited to 3 Mbaud by the FT232R.

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7.4 USB to MCU UART Interface

Figure 7.4 USB to MCU UART Interface

An example of using the FT232R as a USB to Microcontroller (MCU) UART interface is shown in Figure
7.4. In this application the FT232R uses TXD and RXD for transmission and reception of data, and RTS# /CTS# signals for hardware handshaking. Also in this example CBUS0 has been configured as a 12MHz
output to clock the MCU.
Optionally, RI# could be connected to another I/O pin on the MCU and used to wake up the USB hostcontroller from suspend mode. If the MCU is handling power management functions, then a CBUS pin canbe configured as PWREN# and would also be connected to an I/O pin of the MCU.

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7.5 LED Interface
Any of the CBUS I/O pins can be configured to drive an LED. The FT232R has 3 configuration options fordriving LEDs from the CBUS. These are TXLED#, RXLED#, and TX&RXLED#. Refer to Section 3.5 forconfiguration options.

Figure 7.5 Dual LED Configuration

An example of using the FT232R to drive LEDs is shown in Figure 7.5. In this application one of the CBUSpins is used to indicate transmission of data (TXLED#) and another is used to indicate receiving data
(RXLED#). When data is being transmitted or received the respective pins will drive from tri-state to low
in order to provide indication on the LEDs of data transfer. A digital one-shot is used so that even a small
percentage of data transfer is visible to the end user.

Figure 7.6 Single LED Configuration

Another example of using the FT232R to drive LEDs is shown in Figure 7.6. In this example one of the
CBUS pins is used to indicate when data is being transmitted or received by the device (TX&RXLED). In
this configuration the FT232R will drive only a single LED.

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7.6 Using the External Oscillator
The FT232R defaults to operating using its own internal oscillator. This requires that the device ispowered with VCC(min)=+4.0V. This supply voltage can be taken from the USB VBUS. Applications which
require using an external oscillator, VCC= +3.3V, must do so in the following order:
1. When device powered for the very first time, it must have VCC > +4.0V. This supply is available
from the USB VBUS supply = +5.0V.
2. The EEPROM must then be programmed to enable external oscillator. This EEPROM modification
cannot be done using the FTDI programming utility, MPROG. The EEPROM can only be re-configured
from a custom application. Please refer to the following applications note on how to do this:

http://www.ftdichip.com/Documents/AppNotes/AN_100_Using_The_FT232_245R_With_External_
Osc(FT_000067).pdf
3. The FT232R can then be powered from VCC=+3.3V and an external oscillator. This can be doneusing a link to switch the VCC supply.
The FT232R will fail to operate when the internal oscillator has been disabled, but no external oscillator
has been connected.

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8Internal EEPROM Configuration

Following a power-on reset or a USB reset the FT232R will scan its internal EEPROM and read the USB
configuration descriptors stored there. The default factory programmed values of the internal EEPROM
are shown in Table 8.1.

Parameter

Value

Notes

USB Vendor ID (VID)

0403h

FTDI default VID (hex)

USB Product UD (PID)

6001h

FTDI default PID (hex)Serial Number Enabled?

Yes

Serial Number

See Note

A unique serial number is generated andprogrammed into the EEPROM during device final
test.

Pull down I/O Pins in USB
SuspendDisabled

Enabling this option will make the device pull downon the UART interface lines when in USB suspendmode (PWREN# is high).

Manufacturer Name

FTDI

Product Description

FT232R USB UARTMax Bus Power Current

90mA

Power Source

Bus Powered

Device TypeFT232R
Returns USB 2.0 device description to the host.
Note: The device is a USB 2.0 Full Speed device(12Mb/s) as opposed to a USB 2.0 High Speed
device (480Mb/s).

USB Version

0200

Remote Wake Up

EnabledTaking RI# low will wake up the USB host controller
from suspend in approximately 20 ms.

High Current I/Os

Disabled

Enables the high drive level on the UART and CBUS
I/O pins.

Load VCP Driver

EnabledMakes the device load the VCP driver interface forthe device.

CBUS0

TXLED#

Default configuration of CBUS0 – Transmit LED
drive.

CBUS1

RXLED#

Default configuration of CBUS1 – Receive LED drive.

CBUS2

TXDEN

Default configuration of CBUS2 – Transmit data
enable for RS485

CBUS3

PWREN#

Default configuration of CBUS3 – Power enable. Low
after USB enumeration, high during USB suspendmode.

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Parameter

Value

Notes

CBUS4

SLEEP#

Default configuration of CBUS4 – Low during USB
suspend mode.

Invert TXDDisabled

Signal on this pin becomes TXD# if enable.

Invert RXD

Disabled

Signal on this pin becomes RXD# if enable.

Invert RTS#

Disabled

Signal on this pin becomes RTS if enable.

Invert CTS#Disabled

Signal on this pin becomes CTS if enable.

Invert DTR#

Disabled

Signal on this pin becomes DTR if enable.

Invert DSR#

Disabled

Signal on this pin becomes DSR if enable.

Invert DCD#

Disabled

Signal on this pin becomes DCD if enable.

Invert RI#

Disabled

Signal on this pin becomes RI if enable.

Table 8.1 Default Internal EEPROM Configuration

The internal EEPROM in the FT232R can be programmed over USB using the FTDI utility program MPROG.
MPROG can be downloaded from FTDI Utilities on the FTDI website (www.ftdichip.com). Version 2.8a orlater is required for the FT232R chip. Users who do not have their own USB Vendor ID but who would liketo use a unique Product ID in their design can apply to FTDI for a free block of unique PIDs. Contact FTDI
support for this service.

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9Package Parameters

The FT232R is available in two different packages. The FT232RL is the SSOP-28 option and the FT232RQ
is the QFN-32 package option. The solder reflow profile for both packages is described in Section 9.5.

9.1 SSOP-28 Package Dimensions
7.80 +/-0.40
5.30 +/-0.30

28

1
1.02 Typ.

0.05 Min

0.30 +/-0.012

12° Typ1.25 +/-0.12

0.09

0.25
0° - 8°0.75 +/-0.20

0.65 +/-0.026

15

14

Figure 9.1 SSOP-28 Package Dimensions

The FT232RL is supplied in a RoHS compliant 28 pin SSOP package. The package is lead (Pb) free anduses a ‘green’ compound. The package is fully compliant with European Union directive 2002/95/EC.
This package is nominally 5.30mm x 10.20mm body (7.80mm x 10.20mm including pins). The pins areon a 0.65 mm pitch. The above mechanical drawing shows the SSOP-28 package.
All dimensions are in millimetres.
The date code format is YYXX where XX = 2 digit week number, YY = 2 digit year number. This isfollowed by the revision number.
The code XXXXXXXXXXXX is the manufacturing LOT code. This only applies to devices manufactured
after April 2009.

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9.2 QFN-32 Package Dimensions
32

1

Indicates Pin #1(Laser Marked)

25

FTDI

24

YYXX-AXXXXXXX
8

FT232RQ
917165.000 +/-0.075
CentralHeat Sink
Area

9

0.500

0.250 +/-0.050

10

11

12

13

14

15

16

0.150 Max

8

17

7

18

6

19

5

20

4

21

3

22

2

23

1

24

Pin #1 ID

32

31

30

29

28

27

3.200 +/-0.100

26

0.200 Min250.500 +/-0.050

0.900 +/
-0.100

0.200

0.050

Note: The pin #1 ID is connected internally to the device’s central
heat sink area . It is recommended to ground the central heat sinkarea of the device.
Dimensions in mm.
Figure 9.2 QFN-32 Package Dimensions

The FT232RQ is supplied in a RoHS compliant leadless QFN-32 package. The package is lead ( Pb ) free,
and uses a ‘green’ compound. The package is fully compliant with European Union directive 2002/95/EC.
This package is nominally 5.00mm x 5.00mm. The solder pads are on a 0.50mm pitch. The above
mechanical drawing shows the QFN-32 package. All dimensions are in millimetres.
The centre pad on the base of the FT232RQ is not internally connected, and can be left unconnected, orconnected to ground (recommended).
The date code format is YYXX where XX = 2 digit week number, YY = 2 digit year number.
The code XXXXXXX is the manufacturing LOT code. This only applies to devices manufactured after April
2009.
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9.3 QFN-32 Package Typical Pad Layout
2.50

25

0.150 Max1

0.500
3.200 +/-0.100

0.30

Optional GND
Connection

3.200 +/-0.100

Optional GND
Connection

0.20
2.50
17

0.200 Min
0.100

9

0.500
+/-0.050
Figure 9.3 Typical Pad Layout for QFN-32 Package

9.4 QFN-32 Package Typical Solder Paste Diagram

Figure 9.4 Typical Solder Paste Diagram for QFN-32 Package

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9.5 Solder Reflow Profile
The FT232R is supplied in Pb free 28 LD SSOP and QFN-32 packages. The recommended solder reflow
profile for both package options is shown in Figure 9.5.

Temperature, T (Degrees C)

tp
Tp

Critical Zone: when
T is in the range
TL to Tp

Ramp UpTLtL
TS Max

Ramp
Down
TS MintSPreheat25

T = 25º C to TP

Time, t (seconds)
Figure 9.5 FT232R Solder Reflow Profile

The recommended values for the solder reflow profile are detailed in Table 9.1. Values are shown for botha completely Pb free solder process (i.e. the FT232R is used with Pb free solder), and for a non-Pb freesolder process (i.e. the FT232R is used with non-Pb free solder).
Profile Feature

Pb Free Solder Process

Non-Pb Free Solder Process

Average Ramp Up Rate (Ts to Tp)

3°C / second Max.

3°C / Second Max.

Preheat- Temperature Min (Ts Min.)

150°C

100°C

- Temperature Max (Ts Max.)

200°C

150°C

- Time (ts Min to ts Max)

60 to 120 seconds

60 to 120 seconds

217°C

183°C

60 to 150 seconds

60 to 150 seconds

260°C

240°C

20 to 40 seconds

20 to 40 seconds

Ramp Down Rate

6°C / second Max.

6°C / second Max.

Time for T= 25°C to Peak Temperature, Tp

8 minutes Max.

6 minutes Max.

Time Maintained Above Critical Temperature
TL:- Temperature (TL)
- Time (tL)Peak Temperature (Tp)
Time within 5°C of actual Peak Temperature(tp)

Table 9.1 Reflow Profile Parameter Values

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10 Contact Information
Head Office – Glasgow, UK
Future Technology Devices International Limited
Unit 1, 2 Seaward PlaceCenturion Business Park
Glasgow, G41 1HH
United Kingdom
Tel: +44 (0) 141 429 2777
Fax: +44 (0) 141 429 2758
E-mail (Sales)
sales1@ftdichip.com
E-mail (Support) support1@ftdichip.com
E-mail (General Enquiries) admin1@ftdichip.com
http://www.ftdichip.com
Web Site URL
Web Shop URL
http://www.ftdichip.com

Branch Office – Taipei, Taiwan
Future Technology Devices International Limited (Taiwan)
2F, No 516, Sec. 1 NeiHu Road
Taipei 114
Taiwan, R.O.C.
Tel: +886 (0) 2 8791 3570
Fax: +886 (0) 2 8791 3576
E-mail (Sales)
tw.sales1@ftdichip.com
E-mail (Support) tw.support1@ftdichip.com
E-mail (General Enquiries) tw.admin1@ftdichip.com
Web Site URL
http://www.ftdichip.com

Branch Office – Hillsboro, Oregon, USA
Future Technology Devices International Limited (USA)7235 NW Evergreen Parkway, Suite 600
Hillsboro, OR 97123-5803
USA
Tel: +1 (503) 547 0988
Fax: +1 (503) 547 0987
E-Mail (Sales)
E-Mail (Support)
Web Site URL

us.sales@ftdichip.com
us.admin@ftdichip.com
http://www.ftdichip.com

Branch Office – Shanghai, China

Future Technology Devices International Limited (China)
Room 408, 317 Xianxia Road,
ChangNing District,
ShangHai, China
Tel: +86 (21) 62351596
Fax: +86(21) 62351595
E-Mail (Sales): cn.sales@ftdichip.com
E-Mail (Support): cn.support@ftdichip.com
E-Mail (General Enquiries): cn.admin1@ftdichip.com
Web Site URL: http://www.ftdichip.com

Distributor and Sales Representatives
Please visit the Sales Network page of the FTDI Web site for the contact details of our distributor(s) andsales representative(s) in your country.

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Appendix A - List of Figures and Tables
List of Figures
Figure 2.1 FT232R Block Diagram ................................................................................................... 3
Figure 3.1 SSOP Package Pin Out and Schematic Symbol .......................................................... 6
Figure 3.2 QFN-32 Package Pin Out and schematic symbol ................................................................ 9
Figure 6.1 Bus Powered Configuration ........................................................................................... 22
Figure 6.2 Self Powered Configuration ........................................................................................... 23
Figure 6.3 Bus Powered with Power Switching Configuration ............................................................ 24
Figure 6.4 USB Bus Powered with +3.3V or +5V External Logic Power Supply .................................... 25
Figure 7.1 Application Example showing USB to RS232 Converter ..................................................... 26
Figure 7.2 Application Example Showing USB to RS485 Converter .................................................... 27
Figure 7.3 USB to RS422 Converter Configuration........................................................................... 28
Figure 7.4 USB to MCU UART Interface .......................................................................................... 29
Figure 7.5 Dual LED Configuration ................................................................................................ 30
Figure 7.6 Single LED Configuration .............................................................................................. 30
Figure 9.1 SSOP-28 Package Dimensions ....................................................................................... 34
Figure 9.2 QFN-32 Package Dimensions......................................................................................... 35
Figure 9.3 Typical Pad Layout for QFN-32 Package .......................................................................... 36
Figure 9.4 Typical Solder Paste Diagram for QFN-32 Package ........................................................... 36
Figure 9.5 FT232R Solder Reflow Profile ........................................................................................ 37

List of Tables
Table 3.1 USB Interface Group ....................................................................................................... 6
Table 3.2 Power and Ground Group ................................................................................................. 7
Table 3.3 Miscellaneous Signal Group .............................................................................................. 7
Table 3.4 UART Interface and CUSB Group (see note 3) .................................................................... 8
Table 3.5 USB Interface Group ....................................................................................................... 9
Table 3.6 Power and Ground Group ............................................................................................... 10
Table 3.7 Miscellaneous Signal Group ............................................................................................ 10
Table 3.8 UART Interface and CBUS Group (see note 3) .................................................................. 11
Table 3.9 CBUS Configuration Control ........................................................................................... 12
Table 5.1 Absolute Maximum Ratings ............................................................................................ 16
Table 5.2 Operating Voltage and Current ....................................................................................... 17
Table 5.3 UART and CBUS I/O Pin Characteristics (VCCIO = +5.0V, Standard Drive Level) .................. 17
Table 5.4 UART and CBUS I/O Pin Characteristics (VCCIO = +3.3V, Standard Drive Level) .................. 17
Table 5.5 UART and CBUS I/O Pin Characteristics (VCCIO = +2.8V, Standard Drive Level) .................. 18
Table 5.6 UART and CBUS I/O Pin Characteristics (VCCIO = +1.8V, Standard Drive Level) .................. 18
Table 5.7 UART and CBUS I/O Pin Characteristics (VCCIO = +5.0V, High Drive Level) ......................... 18
Table 5.8 UART and CBUS I/O Pin Characteristics (VCCIO = +3.3V, High Drive Level) ......................... 18
Table 5.9 UART and CBUS I/O Pin Characteristics (VCCIO = +2.8V, High Drive Level) ......................... 19
Table 5.10 UART and CBUS I/O Pin Characteristics (VCCIO = +1.8V, High Drive Level) ....................... 19
Table 5.11 RESET# and TEST Pin Characteristics ............................................................................ 19
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Table 5.12 USB I/O Pin (USBDP, USBDM) Characteristics ................................................................. 20
Table 5.13 EEPROM Characteristics ............................................................................................... 20
Table 5.14 Internal Clock Characteristics ....................................................................................... 20
Table 5.15 OSCI, OSCO Pin Characteristics – see Note 1 ................................................................. 21
Table 8.1 Default Internal EEPROM Configuration............................................................................ 33
Table 9.1 Reflow Profile Parameter Values ..................................................................................... 37

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Appendix B - Revision History
Version 0.90

Initial Datasheet CreatedAugust 2005

Version 0.96

Revised Pre-release datasheet

October 2005

Version 1.00

Full datasheet released

December 2005

Version 1.02

Minor revisions to datasheet

December 2005

Version 1.03

Manufacturer ID added to default EEPROM configuration; Buffer sizes added

January 2006

Version 1.04

QFN-32 Pad layout and solder paste diagrams added

January 2006

Version 2.00

Reformatted, updated package info, added notes for 3.3V operation;

June 2008

Part numbers, TID; added UART and CBUS characteristics for +1.8V;
Corrected RESET#; Added MTTF data;
Corrected the input switching threshold and input hysteresis values for VCCIO=5V
Version 2.01

Corrected pin-out number in table3.2 for GND pin18.
Improved graphics on some Figures.
Add packing details. Changed USB suspend current spec from 500uA to 2.5mA
Corrected Figure 9.2 QFN dimensions.

Version 2.02

August 2008

Corrected Tape and Reel quantities.
Added comment “PWREN# should be used with a 10kΩ resistor pull up”.
Replaced TXDEN# with TXDEN since it is active high in various places.
Added lot number to the device markings.
Added 3V3 regulator output tolerance.
Clarified VCC operation and added section headed “Using an external Oscillator”
Updated company contact information.

April 2009

Version 2.03

Corrected the RX/TX buffer definitions to be relative to the USB interface

June 2009

Version 2.04

Additional dimensions added to QFN solder profile

June 2009

Copyright © 2009 Future Technology Devices International Limited

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