MDI-2(Data sheet V2.5_01)
FW 02.02

Fast VME sequencer
and digitizer.

mesytec MDI-2 is a VME sequencer and ADC for readout of MTM16 frontend modules.
It provides 2 Buses, which allow to connect up to 16 MTM-16 frontend modules, andprocess their amplitude data. So up to 512 channels can be served by a single module.

Features:• High quality 12 bit (4 k) conversion
with sliding scale ADC (DNL < 1 %)• 10 M samples /s per bus.
• Up to 512 channels can be converted• Multi event buffer• Connected frontend modules can be remotecontroled (gain, threshold, polarity)• 1 k words multi event buffer• Zero supression with individual thresholds• Supports different types of time stamping• mesytec control bus to control external
mesytec modules• Address modes: A24 / A32• Data transfer modes: D16 (registers),
D32, BLT32, MBLT64, CBLT, CMBLT64• Multicast for event reset and timestamping start• Easy compatibility to MADC-32 (only special registers
0x6040 to 0x6070 are different)mesytec GmbH & Co. KG
Wernher-von-Braun-Str. 1, D-85640 Putzbrunn, Germany
phone: +49 - 89 / 456007-30 fax: +49 - 89 / 456007-39
info@mesytec.com - www.mesytec.com

MDI2 Schematic:

Yellow MTA signal (monitor output). Blue CHS signal

mesytec GmbH & Co. KG
Wernher-von-Braun-Str. 1, D-85640 Putzbrunn, Germany
phone: +49 - 89 / 456007-30 fax: +49 - 89 / 456007-39
info@mesytec.com - www.mesytec.com

Operation principle
For starting the readout of MTM-16 modules a trigger
source is needed. It may come from an independent
detector with strict timing correlation to the MTM-16 input
event, or may come from some or all MTM-16 in one orseveral readout chains. MTM-16 trigger output can beinhibited for individual modules.
The individual trigger (multiplicity) outputs at MDI-2 are
negative current outputs and can be connected, producing acurrent sum. For triggering external devices the common
trigger output can be programmed to output trigger 0,1 or
an ored trigger. If more complex trigger decisions are
created by an external logic, the "veto" input can be used
to accept or reject a trigger signal. The veto signal shouldbe active before the rising edge of the internally created"gate" signal.
The "gate" delay and width, which is created inside MDI-2
for MTM-16 modules, can be adjusted via VME registers.
The trigger signal from MTM-16 is well suited as a highresolution timing signal.
The MDI-2 provides two TDC channels, one for each bus,which are started by the coresponding bus trigger andstopped by the stop inputs.
About 500 ns after the "gate" signal, the sequencer MDI-2sequencer is started and produces the clock sequence forreading out the MTM-16 modules in two connected chains.
The incoming analog amplitude data are digitized by a
12 bit sliding scale ADC (DNL <1 %) and compared withan individual threshold (one for each channel, configured
via VME-bus). If the value is above threshold, it is stored
together with the channel address in a memory (fifo).
After conversion ready the data can be accessed via VME
bus.

Front panel view of MDI-2

MDI-2 also includes a control bus for each of the bus
outputs which allow to communicate with the MTM-16
modules. It allows to set discriminator thresholds,
amplification and polarity. An additional control bus isprovided to control mesytec modules like Shapers and HVbias modules.
The MDI-2 is able to read out up to 2x16 MDI-16
modules, resulting in 512 channels.

mesytec GmbH & Co. KG
Wernher-von-Braun-Str. 1, D-85640 Putzbrunn, Germany
phone: +49 - 89 / 456007-30 fax: +49 - 89 / 456007-39
info@mesytec.com - www.mesytec.com

Chaining several MTM-16 Units

mesytec GmbH & Co. KG
Wernher-von-Braun-Str. 1, D-85640 Putzbrunn, Germany
phone: +49 - 89 / 456007-30 fax: +49 - 89 / 456007-39
info@mesytec.com - www.mesytec.com

Technical Data
Digital Inputs /outputs (see IO register block 0x6060)
Input /output direction termination

Defaultfunctionality
Common Trigger In/Out

TRIG

In/Out

50 R

VETO

Input

50 R

VETO

BUSY/
CBUS

In/Out50 R

Busy out

Alternate functionalities
Gate(when active, triggers are accepted, see reg. 0x604C)
1) Cbus I/O (0x6080)
2) External time stamp oscillator input (0x6096),
max 20 MHz

Power consumption (Total: 4.5 W)
+ 5V
+12 V
–12 V

+230 mA+160 mA–100 mA

The power consumtion of connected MTM-16 mudules adds at +5 V and –12 V.

mesytec GmbH & Co. KG
Wernher-von-Braun-Str. 1, D-85640 Putzbrunn, Germany
phone: +49 - 89 / 456007-30 fax: +49 - 89 / 456007-39
info@mesytec.com - www.mesytec.com

MDI-2 register set
Data FIFO, read data at address 0x0000 (access R/W D32, 64)
for 64 bit access, last 32 bits will be filled with 0 for odd number of 32 bit data words
memory size: 1024 + 2 = 1026 words with 32 bit length
Header (4 byte)2
header signature

6
subheader

8
module id4reservedb01

b000000

module id

b0000

Data (4 byte)2
data-sigb00

12
number of following data words,
including EOE
number of 32 bit data words

DATA event
4

10
Sample number
Sample number

00 01

1
Bus number
0/1

1
out of range
Oor

2

12

b00

ADC amplitude

channel numbers may come in arbitrary order
Data (4 byte)

Extended timestamp2
data-sig
b00

4

10

16

00 11

00 1000 0000

16 high bits of timestamp

Data (4 byte), fill dummy (to fill MBLT-64 word at odd data number)2
data-sig
b00

4

10

1

0

0

0

1
0

2

12

0

0

End of Event mark (4 byte)
2
b11

30
trigger counter / time stamp

Threshold memory at address x4000 to x4FFF (16 bit words, access: R/W D16)
Address
0x4000Name
treshold_bus0[0]

Bits
12

dir
RW

Default
0.
.
.
0x4008treshold_bus1[0]treshold_bus0[1]treshold_bus1[1]treshold_bus0[2]

12

RW

0

Comment
Threshold value of channel 0
value 0 = threshold not used

Threshold value of bus0, channel 2

mesytec GmbH & Co. KG
Wernher-von-Braun-Str. 1, D-85640 Putzbrunn, Germany
phone: +49 - 89 / 456007-30 fax: +49 - 89 / 456007-39
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Registers, Starting at address x6000 (access D16)
Address

Bits

dir default

0x60000x60020x6004Name
Address registers
address_source
address_reg
module_id

1
16
8

RW
RW
RW

0x6008soft_reset

1W

0x600E

firmware_revision

16R

0x60100x60120x60140x60160x6018

IRQ (ROACK)
irq_level
irq_vector
irq_test
irq_reset
irq_threshold

3
8
0
0
10

0x601A

Max_transfer_data

0x601C

Withdraw IRQ

Comment

000xFF

0 = from board coder, 1 from address_reg
address to override decoder on board
is part of data header
If value = FF, the 8 high bits of baseaddress are used (board coder).
breaks all activities, sets criticalparameters to default
0x01.10

RW
RW
W
W
RW

0
0

11

RW

1

1

RW

1

IRQ priority 1..7, 0 = IRQ off
IRQ return value
initiates an IRQ (for test)
resets IRQ (for test)
Every time the number of 32 bit words in the
FIFO exceeds this threshold, an IRQ is emitted.
Maximum allowed threshold is 956.
Maximum data words to transfer before ending the transfer at next end of event word.
Only works for multievent mode 3.
At Max_transfer_data = 1, 1 event pertransfer is emitted. Maximum number of
events is 2047.
Usually the same or higer value than in
0x6018 is used. Setting the value to 0 allows
unlimited transfer.
Withdraw IRQ when data empty

1

For multievent mode 2 and 3 the IRQ is:- set when the fifo fill level gets more than the threshold and is- withdrawn when IRQ is acknowledged or when the fill level goes below the threshold.

MCST CBLT
0x6020 cblt_mcst_control
0x6022 cblt_address
0x6024 mcst_address

8
8
8

RW
0
see table
RW 0xAA A31..A25 CBLT- address
R 0xBB A31..A25 MCST- addressmesytec GmbH & Co. KG
Wernher-von-Braun-Str. 1, D-85640 Putzbrunn, Germany
phone: +49 - 89 / 456007-30 fax: +49 - 89 / 456007-39
info@mesytec.com - www.mesytec.com

0x6020: CBLT_MCST_Control
Bit

Name

Write

Read

7

MCSTENB

10

Enable MCSTNo effect

06

MCSTDIS10

Disable MCSTNo effect

1
0

5

FIRSTENB

1
Enable first module in a CBLT
chain
0
No effect

04

FIRSTDIS

1
Disable first module in a CBLT
chain
0
No effect

1
0

3

LASTENB

1
Enable last module in an CBLT
chain
0
No effect

02

LASTDIS1

1
0

0

Disable last module in an
CBLT chain
No effect

1

CBLTENB

10

Enable CBLTNo effect

00

CBLTDIS10

Disable CBLTNo effect

10MCST enabled
MCST disabledFirst module in a CBLT chain
Not first module in a CBLT chain

Last module in a CBLT chain
Not last module in a CBLT chain

CBLT enabled
CBLT disabled

CBLT Address Field
A31..............A24

A23.................................................................A00

CBLT ADRS

8 high bits, not significant + 16 bit module address space

MCST Address Field
A31..............A24

A23.................................................................A00

MCST ADRS

8 high bits, not significant + 16 bit module address space

At BLT32:
When an empty module is accessed at address 0, BERR is emitted.
At CBLT:
When no module contains data, no data are transmitted. The last module emits BERR.
Usually when zero suppression is used and all modules were triggered, each Module emits the header andfooter with time stamp (2 Words with 32 bits each: MDI-2 Header, MDI-2 footer).

0x6030

FIFO handlingbuffer_data_length

14

R

amount of data in FIFO (only fully converted events).

mesytec GmbH & Co. KG
Wernher-von-Braun-Str. 1, D-85640 Putzbrunn, Germany
phone: +49 - 89 / 456007-30 fax: +49 - 89 / 456007-39
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0x6032

data_len_format

0x6034

readout_reset

0x6036

multievent

2

RW

2

W

4

RW

0

Units → data_len_format.
Can be used for single- and multi event transfer
0 = 8 bit, 1 = 16 bit, 2 = 32 bit, 3 = 64 bit
At 3 a fill word may be added to the buffer to get evennumber of 32 bit words.
At single event mode (multievent = 0):
allow new trigger, allow IRQ
At multievent = 1: checks threshold, sets IRQ whenenough data. Allows safe
operation when buffer fill level does not go below thedata threshold at readout.
At mutievent = 3 : clears Berr, allows next readout
allow multi event buffering (bit 0,1)
0 = no (0x6034 clears event, allows new conversion)
1 = yes, unlimited transfer, no readout reset required(0x6034 can be written after block readout) .
Don’t use for CBLT
3 = yes but MDI transfers limited amount of data.
With reg 0x601A the number of data words can be
specified. After word limit is reached, the next end of
event mark terminates transfer by emitting Berr.
So 0x601A = 1 means event by event transfer(Berr after each event). The next data block can betransferred after writing 0x6034 (resets Berr).
Berr handling: when bit 2 is set:
Send EOB = bit[31:30] = bx10 instead of Berr

0x6038marking_type

2

RW

0

0x603A

start_acq

1

RW

1

0x603C
0x603E

fifo_reset
data_ready

1

W
R

x6040
x6042

trigger
seq_enable
trig_source0

2
3

RW
RW

3
7

Bit 3: Compare number of transmitted events (insteadof number of data words) with max_transfer_data(0x601A) for Berr condition.
00 → event counter
01 → time stamp
11 → extended time stamp
1 → start accepting gates
If there is no external trigger logic, which stopps thetriggers when daq is notrunningis, this register should be set to 0
before applying the fifo_reset to get a well defined
status.
When setting it to 1 again for dataacquisition start, the buffer is in a well defined status.
initialise fifo
1 → data available

enable sequecer 1,0 or both
select trigger to start bus0 sequencer
source: common, trigger1, trigger0

mesytec GmbH & Co. KG
Wernher-von-Braun-Str. 1, D-85640 Putzbrunn, Germany
phone: +49 - 89 / 456007-30 fax: +49 - 89 / 456007-39
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x6044

trig_source1

3

RW

7

x6046

com_trig_source

2

RW

3

x6048

gen_trigger

1

W

x604A

gen_event

1

W

x604C

veto_gate

1

RW

x6050

hold / gate
generation
hold_delay0

12

RW

x6052
x6054

hold_delay1
hold_width0

12
7

RW
RW

x6056

hold_width1

7

RW

SQT
0x60600x6060

Sequencer
timingbus_whatchdg

1RW

0x6062frontend_reset

0W

0x6064

seq_clk_freq0

3

RW

3

0x60660x6068seq_clk_freq1
seq_busy

3
2

RW
R

3

0x606A

sample_delay_reg0

4

RW

3

0x606C
0x606E

sample_delay_reg1
enable_busy

4
1

RW
RW

3
1

0

select trigger to start bus0 sequencer
source: common, trigger1, trigger 0
select source for common trigger I/Osource: trigger1, trigger 0
generate software trigger 0 / 1(for test)
generate trigger and event data for test.
amplitude rising from 100 to 4 k(for test)
0 = use "veto" input as veto
veto is possible from trigger to 25 ns
before end of hold-delay.
1 = use "veto" input as gate(when active triggers are accepted)
veto and gate have to be active at least 25 ns before
hold_delay0/1 runs out.
If different delays for bus1/0 are used,
the shorter one is relevant.
(Typically 475 ns after trigger for MTM-16 timing)

1000 multiple of 0.5 ns(default: gate on bus0 starts 0.5 us after trigger)
1000 same for bus 1
44 multiple of 25 ns(gate length on bus 0 default = 1.1 us)
44 samefor bus 1

1

bus whatchdog. 1 = on
if no event trigger for 1 s, sends frontend reset.
Protects against deadlocks.
frontend_reset (sends "reset sequencer" to MTM-16,
settings left unchanged)
clock frequency, Bus 0:
0 = 1.25 MHz,1 = 2.5 MHz,2 = 5 MHz ,3 = 10 MHz
clock frequency, Bus 1
read sequencer 1 / 0 busy
when seq ready (= 0) , data are available
at buffer
one additional tic delay for multiple of 2.5 m cables.
For standard cable of 3 m
set to 4"
enable busy signal at Lemo output
Do not allow when used as control bus
or for timestamping

mesytec GmbH & Co. KG
Wernher-von-Braun-Str. 1, D-85640 Putzbrunn, Germany
phone: +49 - 89 / 456007-30 fax: +49 - 89 / 456007-39
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SQL
0x60700x60700x60720x60740x60760x6078

Sequencer len
seq0_mctseq1_mct
seq0_cct
seq1_cct
allow_sync_word

4
4
10
10
1

RW
RW
RW
RW
RW

0
0
17
17
0

Not usedNot used
17 counts per MTM-16 needed"
allow_sync_words in fifo buffer. Useful when zero
suppression in frontend MTM-16 (future feature)0, 1 are the two readout buses
2 is the external bus, comes out at busy output
0...15 (module Address set with hexcoder at MTM-16
modules)Comman codes sent to MTM-16:
3 = RC_on,
4 = RC_off,
6 = read_id,
16 = write_data,
18 = read_data
MTM-16 internal address, see box below
data (send or receive), write starts sending
bit0 = active
bit1 = address collision
bit2 = any collision (no termination?)
bit3 = no response from bus (no valid address)

Mesytec control bus
MRC
0x60800x6080Module RC
rc_busno

2RW

00x6082rc_modnum

4

RW

0

0x6084

rc_opcode7RW

0x60860x60880x608Arc_adrrc_datsend return status

8
16
4

RW
RW
R

Send time is 400µs. After this time response at 0x6088 is valid, and sending new data is possible.
At 0x608A bit0 = 1 while sending is active.
The Cbus-LED shows data traffic on the bus , the Cbus-Err-LED shows bus errors (i.e. non terminated lines)

Example for controlling MTM frontend modules connected to the buses
The MTM-16 has two registers (Address 0 and Address 1):
Data at Address 0
4
set rc-status
1 = set3
rc_status(1 = on)2
Not used1
polarity
0 = neg. input
1 = pos input

mesytec GmbH & Co. KG
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phone: +49 - 89 / 456007-30 fax: +49 - 89 / 456007-39
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0gain
0 = high gain
1 = low gain

When set = 0, the bit values are not changed, but only read back.
Data at Address 1: threshold
12 Valid bits
Max value 0xfff = 50 % of single channel range

The data are immediately read back from the module and can be checked at register 0x6086 and 0x6088.
Eplicit reading with opcode 18 is not supported for MTM-16.

Example:set MTM with Address 5 at bus 1 to threshold to 0x0ff(gets only active when RC is switched on)
write 0x6080 1
write 0x6082 5
write 0x6084 16
write 0x6086 1
write 0x6088 0x00ff// bus 1// address module 5// decimal 16 = write to MTM-16// write to MTM-16 - address 1// set threshold to 0x00ff (about 3 % max range)

set MTM16 to positive, high gain and activate the remote control values(deactivate G/P coder and threshold potentiometer)
write 0x6080 1
write 0x6080 5
write 0x6084 16
write 0x6086 0
write 0x6088 0b11010// bus 1// address module 5// decimal 16 = write to MTM-16// write to MTM-16 - address 0// "set" "rc-status on" "nc" "positive pol." "high gain"

Example for controlling external modules with mesytec RC-bus
Initialise and read out a MSCF-16 Shaper module. MSCF-16 ID-coder set to 7.
Bus line must be terminated at the far end.
Activate MDI-2 control bus at busy line
Write (16)addr 0x606E data 3
Get Module ID-Code (= Type of module = 20 for MSCF16)
Write (16)addr 0x6080 data 2// bus 2 (busy output)
Write (16)addr 0x6082 data 7// address module 7
Write (16)addr 0x6084 data 6// send code “read IDC”

mesytec GmbH & Co. KG
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phone: +49 - 89 / 456007-30 fax: +49 - 89 / 456007-39
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Write (16)addr 0x6088 data 0// initialise send request. Data has no effectWait loop: Read (16) 0x608A and compare bit 0 to get 0. Then evaluate other bits for error status
Read (16)addr 0x6088 data 40

Set gain for channel 1 to 10
Write (16)addr 0x6080 data 2
Write (16)addr 0x6082 data 7
Write (16)addr 0x6084 data 16
Write (16)addr 0x6086 data 1
Write (16)addr 0x6088 data 10// at ID readout the bit 0 shows the module RC status// (1 is on). Bit 1..7 show the IDC// → interpretation: Module off, IDC = 20// bus 2 (busy output)// address module 7// code “write_data”// address module memory location 1// start send. Data to send

Wait loop: Read (16) 0x608A and compare bit 0 to get 0. Then evaluate other bits for error status
Optional the read back data is available.
Read (16)addr 0x6088 data 10 // read back written data for control
Read gain of channel 1
Write (16)addr 0x6080 data 2
Write (16)addr 0x6082 data 7
Write (16)addr 0x6084 data 18
Write (16)addr 0x6086 data 1
Write (16)addr 0x6088 data 0// bus 2 (busy output)// address module 7// code “read_data”// address module memory location 1// send read request. Data has no effectWait loop: Read (16) 0x608A and compare bit 0 to get 0. Then evaluate other bits for error status
Read (16)addr 0x6088 data 10 // read out data, “10” returned
Activate RC in module. All set data will get active. This can also be done before setting the values.
Write (16)addr 0x6080 data 2// bus 2 (busy output)
Write (16)addr 0x6082 data 7// address module 7
Write (16)addr 0x6084 data 3// send code “RC_on”
Write (16)addr 0x6088 data 0// initialise send request. Data has no effectDeactivate MDI-2 control bus at busy line
Write (16)addr 0x606E data 0// busy output used as busy

mesytec GmbH & Co. KG
Wernher-von-Braun-Str. 1, D-85640 Putzbrunn, Germany
phone: +49 - 89 / 456007-30 fax: +49 - 89 / 456007-39
info@mesytec.com - www.mesytec.com

CTRA

Timestamp counters, event counters
All counters have to be read in the order: low word then high word !!! They are latched at low word
read. The event counter counts events which are written to the buffer. Fast cleared events are not counted.
CTRA
0x60900x6090countersA
Reset_ctr_ab2

RW

0x60920x60940x6096

evctr_lo
evctr_hits_sources

16
16
2

R
R
RW

0
0
b00

0x6098ts_divisor

16

RW

1

0x609C
0x609E

ts_counter_lo
ts_counter_hi

16
16

R
R

b0001 resets all counters in CTRA,
b0010 resets all counters in CTRB,
b1100 allows single shot reset for CTRA
with first edge of external reset signal.
the bit bx1xx is reset with this first edge
event counter low value
event counter high value
bit0: frequency source(VME = 0, external = 1)
bit1: external reset enable = 1
timestamp = time / ( ts_divisor)
0 means division by 65536
Time low value
Time high value

CTRB

Counters are latched when VME is reading the low word
For counters "ADC_busy" and "Gate1_busy" the count basis is 25 ns.
Output value is divided by 40 to give a 1 us time basis
CTRB
0x60A00x60A0countersB
adc_busy_time_lo

16R

0x60A20x60A80x60AA
0x60AC
0x60AE

adc_busy_time_hi
time_0
time_1
time_2
stop_ctr

16
16
16
16
2

R
R
R
R
RW

ADC busy time, from gate to end of
conversion. Step [1 us]
Time [1 us] (48 bit)00 = run , 1= stop counter
bit 0 all counter B
bit 1 time stamp counter (A)mesytec GmbH & Co. KG
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Data handling
The event buffer is organised as a FIFO with a depth of 1 k x 32 bit.
Data is organized in an event structure, maximum size of one event is 516 32-bit words.
Event structure
Word # (32 bit) Content
0

Event header (indicates # of n following 32-bit words)

1

Data word #1

2

Data word #2

…

…

n-1

Data word #n-1

nEnd of event marker

Event Header (4 byte, 32 bit)
Short #1

Short #0

Byte #3

Byte #2

Byte #1

Byte #0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

hsig

subheader

module id0 1 0 0 0 0 0 0

i

i

i

i

i

i

9

f
i

i

f

8

7

6

5

4

3

2

1

0

# of following words
o 0 0 n n n n n n n n n n n n

hsig:

header signature = b01

subheader:currently = b000000→ Byte #3 = 0x40

module id:

depending on board coder settings→ Byte #2 = MDI-2 Module ID

output format f:currently = 0# of follow. words:

indicates amount n of following 32-bit words:
n-1 events + 1 end of event marker)

mesytec GmbH & Co. KG
Wernher-von-Braun-Str. 1, D-85640 Putzbrunn, Germany
phone: +49 - 89 / 456007-30 fax: +49 - 89 / 456007-39
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Data words (4 byte, 32 bit)

DATA-event

Short #1

Short #0

Byte #3

Byte #2

Byte #1

Byte #0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

dsig

fix

1

0

c b v 0 0 d d d d d d d d d d ddchannel #
c

c

c

c

c

V
c

c

9

8

7

6

5

4

3

2

ADC data (12 valid bits)

0 0 0 0 0 1 c

c

dsig:

data signature = b00

fix:

bitfield currently without meaning = b0001

channel #:number of channel on bus (MTM-ID*16 + MTM channel address)
ADC channels may occur in arbitrary orderV:b:

V = 1 indicates ADC overflow
bus number: 0 for bus0, 1 for bus1

ADC data:

ADC conversion data, 12 valid bits

End of Event mark (4 byte, 32 bit)
Short #1

Short #0

Byte #3

Byte #2

Byte #1

Byte #0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

esig
1 1

esig:

9

8

7

6

5

4

3

2

1

0

t

t

t

t

t

t

t

t

t

trigger counter / time stamp (30 bit)
t

t

t

t

t

t

t

t

t

t

t

t

t

t

t

t

t

t

t

t

t

end of event signature = b11

trigger counter/ 30 bit trigger counter or time stamp information, depending on registertime stamp
0x6038 “marking type”: 0 = event counter, 1 = time stamp
When in single event mode (register 0x6036 = 0), reading beyond EOE, MDI-2 emits a VME Berr(bus error).
When in multi event mode 3 (register 0x6036 = 3), reading beyond EOE after the limit specified in register
0x601A, MDI-2 emits a VME Berr (bus error)
This can be used to terminate a block transfer or multi block transfer.

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Event structure when two buses are operated
The two independent sequencers can be started simultaneously with the same trigger or can be operated
independently. When operated simultaneous, the data of both buses are merged into the same event structure(Header, data, end of event). When independently triggered, the two bus data are added into the same event
when the time between the two triggers is less than 200 ns. When the difference is larger, the later trigger
falls into conversion dead time and is skipped.

Data addresses

The Amplitude data are addressed in the order they are transmitted by the buses.
As the MTM-16 does not transmit the amplitude in the straight channel order, the addresses have to be
assigned to channel numbers by the user.

Channel Order by
MTM-16

Sample number in
MDI-2 event structure

0

0

8

1

1

2

9

3

2

4

10

5

3

6

11

7

4

8

12

9

5

10

13

11

6

12

14

13

7

14

15

15

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The MDI-2 read out in two modes
Single event readout

In this mode the event data from buses are then stored in a memory and the module waits for the VME
readout. After readout of the data at 0x0000 the register 0x6034 is written and allows a new gtrigger to start
the conversion. Triggers coming within the time from accepted trigger to writing the 0x6034 register are
ignored. For dead time the conversion time and VME readout time add up.
1. Assumed: 32 bit read (D32 or BLT32)
Wait for IRQ to start readout of an event
Read register #6030 for event lengt
Read from buffer event_length + 1
Write reset register 0x6034
2. After IRQ start block transfer until BERR on VME-bus
Then write reset register 0x6034
ExampleHardware configuration:• 1x MTM-16 25 MeV connected with 1.5 m twisted pair cable to Bus0 of MDI-2• MTM frontend: Address set to 0
• MTM frontend: R/P switch set to E
• Tail-pulser applied to pulser input, externally terminated pulser line,
amplitude –200 mV, 50 ns rise time, 100 us decay time
MDI sequencer setup (default setting)
Reg 0x6050 → 1000 (gate0 delay 500 ns)
Reg 0x6054 → 44 (gate0 length 1.1 us)
Reg 0x6074 → 17 (16 data + 1x Sync)
Reg 0x606A → 3 (delay adapted to 1.5 m of cable)
Stop acquisition: 0x603A = 0; Stop
Set multievent register 0x6036 = 0 (default).
At power up reset or after soft reset, the IRQ register is set to 0 (no interrupt)
Initialise IRQ (for example to IRQ1, Vector = 0):
set IRQ:
set reg 0x6012 to 0 (IRQ Vector)
set reg 0x6010 to 1 (IRQ-1 will be set when event is converted)
Reset fifo: write register 0x6034 (any value)
start_acq: 0x603A = 1; Start
Now module is ready for IRQ triggered readout loop:→ IRQ
Read register 0x6030 for event lengt (D16)
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Read from buffer event_length + 1 (BLT32)
Write reset register 0x6034 (D16)
Or:
→ IRQ
Start block transfer (BLT32) until BERR on VME-bus
Then write reset register 0x6034 (D16)
The above procedure works completely unchanged with multi event mode 0x6036 = 3 and 0x601A = 0.
In this mode the buffer is used but the data are read out event by event. After each event a Berr is emitted,
which is removed by writing the 0x6034 readout reset.
Multi event readout

In multievent readout mode (0x6036, mutievent = 1 or 3) the input is decoupled from output by a 1024
words buffer. So the input is ready for a new gate after the conversion time of the ADC.
When several converter modules are used in one setup, there has to be a way to identify coincident data fromdifferent modules which belong to the same event.
Event synchronisation

One methode is event counting.
Each module has an event counter and counts the incomming gates. In complex setups, the gates are best
initiated by the individual detector timing signals and significant amount of logic and timing modules have tobe established and adjusted to coordinate the detector triggers. Also fast clears may be necessary for somedetectors. A single timing error in all the experiment run time, which will allow an additional gate to come tosome module or a suppression of a gate, will corrupt the complete data set, as data get asynchronous.
The better one is time stamping.
A central oscillator clock (for MDI-2 this can be the VME built in clock of 16 MHz or an external clock up
to 20 MHz) is counted to create a time basis. At experiment start the time counters of all modules are reset
via a VME multicast write to a reset register, or by an external reset signal.
All incomming events are then labeled with a 30 bit long time tag. At data analysis the data streams fromdifferent modules are analyse and correlated events are grouped for further processing.
The synchronisation methodes allow the different modules to be completely independent from each other.
It gets now possible to use large data buffers in the frontend modules, and do the readout when the VME databus is not occupied. The MDI-2 alows to set a buffer fill threshold which emits an interrupt when the data filllevel in the buffer exceed the threshold.

Data transfer

In principle any amount of data can be read at any time from the buffer, but then events may be
splitted to two consecutive readout cycles, which normally is no problem.
When only full events should be read in one readout cycle, there are three possibilities.
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1. multievent mode = 1: read “buffer_data_length” (0x6030) and transfer
the amount of data read there.
2. multievent mode = 1: The buffer must be read to the end which means to the Berr mark. Note that this inprinciple requires to read an infinite number of words, because at fastest conversion the incoming data
rate on both buses may be as high as 20 Mwords/s, the VME readout rate is realistic about 5 Mwords /s in
BLT32, 10 Mwords/s at MBLT64. So under worst conditions it is not possible to empty the buffer via
VME and get an empty fifo signal “Berr” !
So if high rates can appear, the data acquisition should at least be tolerant to splitted events.
3. multievent mode = 3 : MDI transfers a limited amount of data. With reg 0x601A the number of datawords can be specified. After word limit is reached, the next end of event mark terminates transfer by
emitting Berr. So 0x601A = 1 means event by event transfer (Berr after each event). The next data block
can be transferred after writing 0x6034 (resets Berr).
IRQ

For many setups it is useful to control the readout via interrup requests (IRQ) defined by VME.
For MDI-2 an IRQ is initiated when the buffer fill level gets above the “irq_threshold” (0x6018).
The IRQ is acknowledged by the VME controler, then the controler starts a readout sequence.
When not using the readout reset (0x6034) at the end of a readout cycle, the MDI does not know when thecycle ends. The IRQ is then set again when the data fill level exceeds the irq-threshold. When not enoughdata are read from fifo to drive the fifo fill level below the threshold, no new IRQ will be emitted.
So for a readout which is stable against any external influences (readout delays, high input rates),
we recommend to write the readout_reset after each readout sequence. For several MDI modules in VME bin
this can also be done with a single multicast write.

Example 1, multievent readout
1. Stop acquisition

start_acq 0x603A = 0; Stop

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2. Time stamping

The module will use here an external reference oscillator and will be reset (synchronised)
via VME command.
set oscillator input

ECL_gate1_osc

0x6064 = 1;

Set oscillator source, reset source

ts_sources

0x6096 = 2; (ext osc, int reset only)

Show timestamp in EOE markmarking type0x6038 = 1;

Synchronisation:

reset_ctr_ab

0x6090 = 3; reset all counters

3. Set Multievent

Multievent 0x6036 = 3

Multievent with limited data transfer

Irq_threshold 0x6018 = 200

Irq is set when more than 200 (32 bit-)words are in buffer

Max_transfer_dat 0x601A = 218

Transmit maximum 223 words +reset of event before sending Berr.
(In this case data fits into one VME 255 word blt32 transfer)

4. IRQ

Initialise IRQ (for example to IRQ1, Vector = 0):
set IRQ:
set reg 0x6012 to 0
(IRQ Vector)
set reg 0x6010 to 1
(IRQ-1 will be set when event is converted)
set reg 0x6018 to 100(IRQ emitted when more than 100 words in fifo)

5. Buffer initialisation, start

Fifo_reset 0x603C = 0;
Readout reset 0x6034 = 0;start_acq 0x603A = 1; Start
6. Readout loop

→ IRQ
Start multi block transfer (BLT32 or MBLT64) until BERR on VME-bus.
Then write reset register 0x6034 (D16)

Example 2, chained block transfer
Describes multi event readout but with 2 MDCs and 1 MDI-2 via chained block transfer
To operate several modules in one VME bin, each module has to be given a different address.
The 4 coders on the main board code for the highest 16 bits of the 32 bit address. Best way is, to use only thehighest 8 bits for coding (2 rotary coder marked with high). It makes sense to use the slot number as highaddress. So:
MADC 1 in slot 1 gets 0x0100
MDI 2 in slot 2 gets 0x0200
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MADC 3 in slot 3 gets 0x0300
If you don’t change the module ID default, the modules will now also have the ID 1…3 which will betransmitted in the data header.
Now initialise the individual modules

ADC1: set 0x0100 6020 to 0xA2

(CBLT first module, Multicast enable)

MDI2: set 0x0200 6020 to 0x82

(CBLT mid module, Multicast enable) also any further module inthe middle of the readout chain is initialised this way.

ADC3: set 0x0300 6020 to 0x8A

(CBLT last module, Multicast enable)

When you don’t change the default addresses for CBLT and MCST, the modules will have the CBLT start
address of 0xAA00 0000 and the MCST start address of 0xBB00 0000.
You can now do the initialisation 1) to 5) of Example 1 via multicast at the offset address 0xBB00.
The readout loop has to be modified slightly→ IRQ
Start multi block transfer (BLT32, MBLT64) at address 0xAA00 0000 until BERR on VME-bus
Then write reset register 0xBB00 6034 (D16) at the multicast address.
Note: use multievent mode 0 or 3 for CBLT (mode 1 will not work !)Special Operation
MBLT64

MBLT64 is defined by the address modifier. At buffer unpacking in analysis software it helps to keep thealignment within the transmitted 64-bit word. When setting register 0x6032 to 3 a fill word is added to theconverted channels when converted channel number is odd.
CMBLT64

Is intrinsic when chained block transfer is used with MBLT64.
Note: Register 0x6032 has to be set to 3 to align the words !

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MDI2 overview

programming
connector

Address coders

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Scope traces showing timing structure on the bus

MDI-2 with two MTM-16 connected at bus0, 10 MHz sequencer frequency

Yellow: CHS-signal: in order of occurrence: Gate, clocking sequence, reset pulse
Blue: Shaper output of one channel inside MTM-16
Magenta: MDI-2 monitor signal, available at front panel. In order of occurrence:
Trigger pulse, 32 Amplitude values with 2 negative synchronisation pulses

Monitor signal. Flicker mark maks the ADC sampling time. The flicker position can be adjusted byregister 0x6054 / 0x6056 (in steps of 25 ns) and by the bus cable length.
Adding 1 m cable to the bus, shifts the sampling time 10 ns to the left.
The sampling time should be about 10 ns before the falling edge of the amplitude signal.

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Power supply of MTM-16 modules

The MTM-16 modules are supplied with power via their bus line.
The length of the bus line is limited by the voltage drop. Typical 12 mV/m/module can be expected.
So for 4 MTM-16 modules with a bus length of 3 m a voltage drop of 4 x 4 x 12 mV = 192 mV can be
expected. The maximum allowed drop is 400 mV. If the voltage drop exceeds this value, the modules needan external supply.

Several MTM-16 modules in a chain

When several modules are connected to a bus, the Address coders must be set from 0 to module number -1.
For example: 5 modules at bus 0: the coders are set to 0, 1, 2, 3, 4 or 1, 0, 4, 3, 2.
Not allowed is for example 1, 2, 3, 4, 5 or 0, 2, 3, 4, 5.
The bus line must be terminated with a special terminator plug.
It terminates the CHS and MTA lines with 50 Ω to ground.

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phone: +49 - 89 / 456007-30 fax: +49 - 89 / 456007-39
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