Uniform Sector
Standard and Dual Serial Flash

GD25WD40C/20C
DATASHEET

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Rev.2.1

GD25WD40C/20CUniform Sector
Standard and Dual Serial Flash

GD25WD40C/20C

CONTENTS1.

FEATURES ................................................................................................................................................................ 42.

GENERAL DESCRIPTION ..................................................................................................................................... 5

3.

MEMORY ORGANIZATION .................................................................................................................................. 8

4.

DEVICE OPERATION ........................................................................................................................................... 10

5.

DATA PROTECTION ............................................................................................................................................. 116.

STATUS REGISTER ............................................................................................................................................... 127.

COMMANDS DESCRIPTION............................................................................................................................... 13
7.1.

WRITE ENABLE (WREN) (06H) ......................................................................................................................... 15

7.2.

WRITE DISABLE (WRDI) (04H) ......................................................................................................................... 15

7.3.

READ STATUS REGISTER (RDSR) (05H)............................................................................................................. 16

7.4.

WRITE STATUS REGISTER (WRSR) (01H) .......................................................................................................... 16

7.5.

READ DATA BYTES (READ) (03H)..................................................................................................................... 17

7.6.

READ DATA BYTES AT HIGHER SPEED (FAST READ) (0BH)................................................................................ 17

7.7.

DUAL OUTPUT FAST READ (3BH) ...................................................................................................................... 18

7.8.

PAGE PROGRAM (PP) (02H)................................................................................................................................ 18

7.9.

SECTOR ERASE (SE) (20H)................................................................................................................................. 19

7.10.

32KB BLOCK ERASE (BE) (52H) ....................................................................................................................... 20

7.11.

64KB BLOCK ERASE (BE) (D8H) ...................................................................................................................... 20

7.12.

CHIP ERASE (CE) (60/C7H)................................................................................................................................ 21

7.13.

DEEP POWER-DOWN (DP) (B9H) ....................................................................................................................... 22

7.14.

RELEASE FROM DEEP POWER-DOWN / READ DEVICE ID (ABH)........................................................................ 22

7.15.

READ MANUFACTURE ID/ DEVICE ID (REMS) (90H)........................................................................................ 23

7.16.

READ IDENTIFICATION (RDID) (9FH) ................................................................................................................ 24

7.17.

READ UNIQUE ID (4BH) .................................................................................................................................... 25

8.

ELECTRICAL CHARACTERISTICS.................................................................................................................. 26
8.1.

POWER-ON TIMING ....................................................................................................................................... 26

8.2.

INITIAL DELIVERY STATE ............................................................................................................................ 26

8.3.

ABSOLUTE MAXIMUM RATINGS ............................................................................................................... 26

8.4.

CAPACITANCE MEASUREMENT CONDITIONS........................................................................................ 27

8.5.

DC CHARACTERISTICS................................................................................................................................. 28

8.6.

AC CHARACTERISTICS................................................................................................................................. 31

9.

ORDERING INFORMATION ............................................................................................................................... 37
9.1.

10.

VALID PART NUMBERS........................................................................................................................................ 38
PACKAGE INFORMATION ............................................................................................................................. 40

10.1.

PACKAGE SOP8 150MIL.................................................................................................................................... 40

10.2.

PACKAGE SOP8 208MIL.................................................................................................................................... 41

10.3.

PACKAGE TSSOP8 173MIL ............................................................................................................................... 42

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10.4.

PACKAGE DIP8 300MIL..................................................................................................................................... 43

10.5.

PACKAGE USON8 (1.5*1.5MM) ......................................................................................................................... 44

10.6.

PACKAGE USON8 (3*2MM, THICKNESS 0.45MM)............................................................................................... 45

10.7.

PACKAGE WLCSP .............................................................................................................................................. 46

11.

REVISION HISTORY ........................................................................................................................................ 47

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1. FEATURES�

4M/2M-bit Serial Flash� Fast Program/Erase Speed-512K/256K-byte-Page Program time: 1.6ms typical-256 bytes per programmable page

-Sector Erase time: 150ms typical-Block Erase time: 0.5/0.8s typical�Standard, Dual Output-Chip Erase time: 6/3s typical-Standard SPI: SCLK, CS#, SI, SO, WP#-Dual Output: SCLK, CS#, IO0, O1, WP#

� Flexible Architecture-Uniform Sector of 4K-byte�Clock Frequency-Uniform Block of 32/64K-byte-100MHz for fast read on 3.0~3.6V power supply��� Low Power Consumption

Dual Output Data Transfer up to 160Mbits/s-70MHz for fast read on 2.1~3.0V power supply��

-0.1uA typical standby current-0.1uA typical power down current

Dual Output Data Transfer up to 120Mbits/s-50MHz for fast read on 1.65~2.1V power supply��� Advanced Security Features

Dual Output Data Transfer up to 80Mbits/s-128-bit Unique ID for each device
� Software/Hardware Write Protection-Write protect all/portion of memory via software

Single Power Supply Voltage

�-Enable/Disable protection with WP# Pin-Full voltage range: 1.65~3.6V

� Minimum 100,000 Program/Erase Cycles

Package option

�-SOP8 150mil
� Data Retention-SOP8 208mil-20-year data retention typical-TSSOP8 173mil-DIP8 300mil-USON8 1.5*1.5mm-USON8 3*2mm-WLCSP

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GD25WD40C/20C

2. GENERAL DESCRIPTIONThe GD25WD40C/20C (4M/2M-bit) Serial flash supports the standard Serial Peripheral Interface (SPI), andsupports the Dual Output: Serial Clock, Chip Select, Serial Data I/O0 (SI), O1 (SO). The Dual Output data is transferredwith maximum speed of 160Mbits/s.

CONNECTION DIAGRAM

CS#

1

8

VCC

CS#

1

SO
(O1)

2

7

NC

SO
(O1)

2

WP#

3

6

SCLK

WP#

VSS

4

5

SI
(IO0)

VSS

Top View

8

VCC

7

NC

3

6

SCLK

4

5

SI
(IO0)

8�LEAD
SOP/TSSOP/DIPTop View

8�LEAD USONTOP VIEW

BOTTOM VIEW

A1

A2

A2

A1

VCC

CS#

CS#

VCC

B1

B2

B2

B1

SCLK

SO
(IO1)

SO
(IO1)

SCLK

C1

C2

C2

C1

SI
(IO0)

VSS

VSS

SI
(IO0)

WLCSP

PIN DESCRIPTION
Table 1. Pin Description for SOP/TSSOP/DIP/USON package
Pin Name

I/O

Description

CS#

I

Chip Select Input

SO (O1)O

Data Output (Data Output 1)

WP#

I

Write Protect Input
GroundVSS
SI (IO0)

I/O

Data Input (Data Input Output 0)

SCLK

I

Serial Clock Input

NC

No Connection

VCC

Power Supply

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Table 2. Pin Description for WLCSP package
Pin Name

Ball Name

I/O

Description

CS#

A2

I

Chip Select Input

SO (IO1)

B2

I/O

Data Output (Data Input Output 1)

VSS

C2

SI (IO0)C1

I/O

Data Input (Data Input Output 0)

SCLK

B1

I

Serial Clock Input

VCC

A1

GroundPower Supply

Note: CS# must be driven high if chip is not selected. Please don’t leave CS# floating any time after power is on.

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BLOCK DIAGRAM

Write Control
Logic

StatusRegister

SCLK
CS#

SPI
Command &Control Logic

High Voltage
Generators
Page Address
Latch/Counter

Flash
MemoryColumn Decode And
256-Byte Page Buffer

SI(IO0)SO(O1)

Byte Address
Latch/Counter

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Write Protect Logic
and Row Decode

WP#

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3. MEMORY ORGANIZATION
GD25WD40C
Each device has

Each block has

Each sector has

Each page has

512K

64/32K

4K

256

bytes

2K

256/128

16

-

pages

128

16/8

-

-

sectors

8/16

-

-

-

blocksEach device has

Each block has

Each sector has

Each page has

256K

64/32K

4K

256

bytes

1K

256/128

16

-

pages

64

16/8

-

-

sectors

4/8

-

-

-

blocksGD25WD20C

UNIFORM BLOCK SECTOR ARCHITECTURE
GD25WD40C 64K Bytes Block Sector Architecture
Block

7

6

……

……

2

1

0

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SectorAddress range

127

07F000H

07FFFFH

……

……

……

112

070000H

070FFFH

111

06F000H

06FFFFH

……

……

……

96

060000H

060FFFH

……

……

……

……

……

……

……

……

……

……

……

……

……

……

……

……

……

……

47

02F000H

02FFFFH

……

……

……

32

020000H

020FFFH

31

01F000H

01FFFFH

……

……

……

16

010000H

010FFFH

1500F000H

00FFFFH

……

……

……

0

000000H

000FFFH

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GD25WD20C 64K Bytes Block Sector Architecture
Block

3

2

1

0

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SectorAddress range

6303F000H

03FFFFH

……

……

……

48

030000H

030FFFH47

02F000H

02FFFFH

……

……

……

32

020000H

020FFFH

31

01F000H

01FFFFH

……

……

……

16

010000H

010FFFH

1500F000H

00FFFFH

……

……

……

0

000000H

000FFFH

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4. DEVICE OPERATIONSPI ModeStandard SPI
The GD25WD40C/20C features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select (CS#),
Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported. Input data is latched on therising edge of SCLK and data shifts out on the falling edge of SCLK.
Dual SPIThe GD25WD40C/20C supports Dual Output operation when using the “Dual Output Fast Read” (3BH) commands.
These commands allow data to be transferred to or from the device at twice the rate of the standard SPI. When using theDual Output command the SI and SO pins become bidirectional I/O pins: IO0 and O1.

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5. DATA PROTECTION
The GD25WD40C/20C provides the following data protection methods:
Write Enable (WREN) command: The WREN command is set the Write Enable Latch bit (WEL). The WEL bit will��

reset to 0 in the following situations:-Power-Up-Write Disable (WRDI)-Write Status Register (WRSR)-Page Program (PP)-Sector Erase (SE) / Block Erase (BE) / Chip Erase (CE)Software Protection Mode: The Block Protect (BP2, BP1, BP0) bits define the section of the protected memory area��

which is read-only and unalterable.
�Hardware Protection Mode: WP# goes low to protect the BP0~BP2 bits and SRP bits.

��

Deep Power-Down Mode: In Deep Power-Down Mode, all commands are ignored except the Release from DeepPower-Down Mode command.
Write Inhibit Voltage (VWI): Device would reset automatically when VCC is below a certain threshold VWI.

��

Table3(a) GD25WD40C Protected area size
Status Register Content

Memory Content

BP2

BP1

BP0

BlocksAddresses

Density

Portion

0

0

0

NONE

NONE

NONE

NONE

0

0

1

Sector 0 to 125

000000H-07DFFFH

504KB

Lower126/128

0

1

0

Sector 0 to 123

000000H-07BFFFH

496KB

Lower 124/128

0

1

1

Sector 0 to 119

000000H-077FFFH

480KB

Lower 120/128

1

0

0

Sector 0 to 111

000000H-06FFFFH

448KB

Lower 112/128

1

0

1

Sector 0 to 95

000000H-05FFFFH

384KB

Lower 96/128

1

1

0

Sector 0 to 63

000000H-03FFFFH

256KB

Lower 64/128

1

1

1

All

000000H-07FFFFH

512KB

ALL

Table3(b) GD25WD20C Protected area size
Status Register Content

Memory Content

BP2

BP1

BP0

BlocksAddresses

Density

Portion

0

0

0

NONE

NONE

NONE

NONE

0

0

1

Sector 0 to 61

000000H-03DFFFH

248KB

Lower 62/64

0

1

0

Sector 0 to 59

000000H-03BFFFH

240KB

Lower 60/64

0

1

1

Sector 0 to 55

000000H-037FFFH

224KB

Lower 56/64

1

0

0

Sector 0 to 47

000000H-02FFFFH

192KB

Lower 48/64

1

0

1

Sector 0 to 31

000000H-01FFFFH

128KB

Lower 32/64

1

1

X

All

000000H-03FFFFH

256KB

ALL

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6. STATUS REGISTER
S7

S6

S5

S4

S3

S2

S1

S0

SRP

Reserved

Reserved

BP2

BP1

BP0

WEL

WIP

The status and control bits of the Status Register are as follows:
WIP bit.
The Write In Progress (WIP) bit indicates whether the memory is busy in program/erase/write status register progress.
When WIP bit is set to 1, it means the device is busy in program/erase/write status register progress. when WIP bit is cleared
to 0, it means the device is not in program/erase/write status register progress. The default value of WIP is 0.
WEL bit.
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal
Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status Register, Program orErase command is accepted. The default value of WEL is 0.
BP2, BP1, BP0 bits.
The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be software protectedagainst Program and Erase commands. These bits are written with the Write Status Register (WRSR) command. When the
Block Protect (BP2, BP1, BP0) bits are set to 1, the relevant memory area (as defined in Table3).becomes protected against
Page Program (PP), Sector Erase (SE) and Block Erase (BE) commands. The Block Protect (BP2, BP1, BP0) bits can be
written provided that the Hardware Protected mode has not been set. The Chip Erase (CE) command is executed, if theBlock Protect (BP2, BP1, BP0) bits are all 0. The default value of BP2:0 are 0s.

SRP bit
The Status Register Protect (SRP) bit operates in conjunction with the Write Protect (WP#) signal. The Status Register
Write Protect (SRP) bit and Write Protect (WP#) signal set the device to the Hardware Protected mode. When the Status
Register Protect (SRP) bit is set to 1, and Write Protect (WP#) is driven Low. In this mode, the non-volatile bits of the Status
Register(SRP, BP2, BP1, BP0) become read-only bits and the Write Status Register (WRSR) instruction is not execution.
The default value of SRP is 0.

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7. COMMANDS DESCRIPTION
All commands, addresses and data are shifted in and out of the device by the host system, with the most significant
bit first. On the first rising edge of SCLK after CS# is driven low, the one-byte command code must be shifted into the device,with the most significant bit first on SI, and each bit being latched on the rising edges of SCLK.
See Table4, every command sequence starts with a one-byte command code. Depending on the command, this might
be followed by address bytes, or data bytes, or dummy bytes. CS# must be driven high after the last bit of the commandsequence has been completed.
For the command of Read, Fast Read, Read Status Register or Release from Deep Power-Down, and Read Device
ID, the shifted-in command sequence is followed by a data-out sequence. All read instruction can be completed after any
bit of the data-out sequence is being shifted out, and then CS# must be driven high to return to deselected status.
For the command of Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Write Enable,
Write Disable or Deep Power-Down command, CS# must be driven high exactly at a byte boundary, which means the clock
pulse number should be an exact multiple of eight. Otherwise the command is rejected to executed. Especially for Page
Program command, if at any time the input end is not a completed byte, nothing will be written into the memory array, neither
would WEL bit be reset.
Table4. Commands
Command Name

Byte 1

Byte 2

Write Enable
Write Disable
Read Status Register
Write Status Register
Read Data
Fast Read
Dual Output
Fast Read
Page Program
Sector Erase
Block Erase(32K)
Block Erase(64K)
Chip Erase
Deep Power-Down
Release From DeepPower-Down, And
Read Device ID
Release From DeepPower-Down
Manufacturer/
Device ID
Read Identification

06H
04H
05H
01H
03H
0BH
3BH

(S7-S0)S7-S0
A23-A16
A23-A16
A23-A16

A15-A8
A15-A8
A15-A8

A7-A0
A7-A0
A7-A0

(D7-D0)
dummy
dummy

(Next byte)(D7-D0)(D7-D0)(1)

A23-A16
A23-A16
A23-A16
A23-A16

A15-A8
A15-A8
A15-A8
A15-A8

A7-A0
A7-A0
A7-A0
A7-A0

D7-D0

Next byte

dummy

dummy

dummy

(DID7DID0)

90H

00H

00H

00H

(MID7MID0)

9FH(MID7MID0)(JDID15JDID8)(JDID7JDID0)

Read Unique ID

4BH

00H

00H

00H

02H
20H
52H
D8H
C7/60 H
B9H
ABH

Byte 3

Byte 4

Byte 5

Byte 6n-Bytes(continuous)(continuous)(continuous)(continuous)(continuous)

ABH(DID7DID0)(continuous)
dummy(UID7UID0)NOTE:
1. Dual Output data
IO0 = (D6, D4, D2, D0)
O1 = (D7, D5, D3, D1)

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GD25WD40C/20C

TABLE OF ID DEFINATION:
GD25WD40C

Operation Code

M7-M0

ID15-ID8

ID7-ID0

9FH

C8

64

13

90H

C8

12

ABH

12

GD25WD20C
Operation Code

M7-M0

ID15-ID8

ID7-ID0

9FH

C8

64

12

90H

C8

11

ABH

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7.1. Write Enable (WREN) (06H)
The Write Enable (WREN) command is for setting the Write Enable Latch (WEL) bit to 1. The Write Enable Latch(WEL) bit must be set prior to every Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE) and Write
Status Register (WRSR) command.
The Write Enable (WREN) command sequence: CS# goes low � sending the Write Enable command � CS# goeshigh.
Figure1. Write Enable Sequence Diagram
CS#
SCLK

0

1

2

3

4

5

6

7

CommandSI

06H
High-ZSO

7.2. Write Disable (WRDI) (04H)
The Write Disable command is for resetting the Write Enable Latch (WEL) bit to 0. The WEL bit is reset by following
condition: Power-up and upon completion of the Write Status Register, Page Program, Sector Erase, Block Erase and Chip
Erase commands.
The Write Disable command sequence: CS# goes low�Sending the Write Disable command �CS# goes high.
Figure2. Write Disable Sequence Diagram
CS#
SCLK
SI
SO

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0

1

2

3

4

5

Command04H
High-Z

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7.3. Read Status Register (RDSR) (05H)
The Read Status Register (RDSR) command is for reading the Status Register. The Status Register may be read at
any time, even while a Program, Erase or Write Status Register cycle is in progress.
When one of these cycles is in progress, it is recommended to check the Write In Progress (WIP) bit before sending
a new command to the device. It is also possible to read the Status Register continuously. For command code “05H”, theSO will output Status Register bits S7~S0.

Figure3. Read Status Register Sequence Diagram
CS#
SCLK

0

1

SI
SO

2

3

4

5

6

7

8

9 10 11 12 13 14 15

7

6Command05H
High-Z

S7~S0 out
5 4 3 2

MSB

1

0

7

6

5

S7~S0 out
4 3 2 1

0

7MSB

7.4. Write Status Register (WRSR) (01H)
The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. A Write Enable(WREN) instruction must be executed previously to set the Write Enable Latch (WEL) bit, before it can be accepted.
The Write Status Register (WRSR) instruction is entered by driving Chip Select (CS#) Low, followed by
the instruction code and the data byte on Serial Data Input (DI).
The Write Status Register (WRSR) instruction has no effect on S6, S5, S1 and S0 of the Status Register. S6 and S5
are always read as 0. Chip Select (CS#) must be driven High after the eighth bit of the data byte has been latched in.
Otherwise, the Write Status Register (WRSR) instruction is not executed. As soon as Chip Select (CS#) is driven High, theself-timed Write Status Register cycle (the duration is tW) is initiated. While the Write Status Register cycle is in progress,
reading Status Register to check the Write In Progress (WIP) bit is achievable.
The Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and turn to 0 on the completionof the Write Status Register. When the cycle is completed, the Write Enable Latch (WEL) is reset to 0.
The Write Status Register (WRSR) instruction allows the user to change the values of the Block Protect (BP2, BP1,
BP0) bits, which are utilized to define the size of the read-only area.
The Write Status Register (WRSR) instruction also allows the user to set or reset the Status Register Protect (SRP)
bit in accordance with the Write Protect (WP#) signal, by setting which the device can enter into Hardware Protected Mode.
The Write Status Register (WRSR) instruction is not executed once enter into the Hardware Protected Mode.

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Figure4. Write Status Register Sequence Diagram
CS#
1

0

SCLK

2

3

4

5

6

7

8

CommandSI

9 10 11 12 13 14 15

Status Register in

7

01H

6

5

MSB

SO

4

3

2

1

0

High-Z

7.5. Read Data Bytes (READ) (03H)
The Read Data Bytes (READ) command is followed by a 3-byte address (A23-A0), and each bit being latched-in on
the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, and each bit being shifted out, at
a Max frequency fR, on the falling edge of SCLK. The first byte addressed can be at any location. The address is
automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore,
be read with a single Read Data Bytes (READ) command. Any Read Data Bytes (READ) command, while an Erase,
Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress.
Figure5. Read Data Bytes Sequence Diagram
CS#
SCLK

0

1

SI
SO

2

3

4

5

6

7

8

Command03H
High-Z

9 10

28 29 30 31 32 33 34 35 36 37 38 39

24-bit address

3

23 22 21

2

1

0

MSB
MSB

7

6

Data Out1
5 4 3 2 1

Data Out2

07.6. Read Data Bytes At Higher Speed (Fast Read) (0BH)
The Read Data Bytes at Higher Speed (Fast Read) command is for quickly reading data out. It is followed by a 3-byte
address (A23-A0) and a dummy byte, and each bit being latched-in on the rising edge of SCLK. Then the memory content,
at that address, is shifted out on SO, and each bit being shifted out, at a Max frequency f C, on the falling edge of SCLK. The
first byte addressed can be at any location. The address is automatically incremented to the next higher address after eachbyte of data is shifted out.

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Figure6. Read Data Bytes at Higher Speed Sequence Diagram

CS#

0

SCLK

1

2

3

4

5

6

8

7

9 10

24-bit address

CommandSI

28 29 30 31

23 22 21

0BH

1

2

3

0

High-ZSOCS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

SCLK
SI

Dummy Byte
7

6

5

4

3

0

1

2

SO

Data Out1
5 4 3 2

7 6
MSB

0

1

Data Out2
7 6 5
MSB

7.7. Dual Output Fast Read (3BH)
The Dual Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, and each bit being
latched in on the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO.
The command sequence is shown in followed Figure7. The first byte addressed can be at any location. The address is
automatically incremented to the next higher address after each byte of data is shifted out.
Figure7. Dual Output Fast Read Sequence Diagram
CS#
SCLK
SI
SO

0

1

2

3

4

5

6

7

8

9 10

Command28 29 30 31

24-bit address

3BH

3

23 22 212

1

0

High-ZCS#

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
SI

Dummy Clocks

SO

4

2

0

6

4

2

0

6

Data Out1
Data Out2
7 5 3 1 7 5 3 1
MSB
MSB

7

6

7.8. Page Program (PP) (02H)
The Page Program (PP) command is for programming the memory. A Write Enable (WREN) command must
previously have been executed to set the Write Enable Latch (WEL) bit before sending the Page Program command.

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GD25WD40C/20C

The Page Program (PP) command is entered by driving CS# Low, followed by the command code, three address
bytes and at least one data byte on SI.
If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes beyond the end of thecurrent page are programmed from the start address of the same page (from the address whose 8 least significant bits (A7A0) are all zero). CS# must be driven low for the entire duration of the sequence.
The Page Program command sequence: CS# goes low � sending Page Program command � 3-byte address on SI
� at least 1 byte data on SI � CS# goes high. The command sequence is shown in Figure8.
If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes areguaranteed to be programmed correctly within the same page. If less than 256 data bytes are sent to device, they arecorrectly programmed at the requested addresses without having any effects on the other bytes of the same page. CS#
must be driven high after the eighth bit of the last data byte has been latched in; otherwise the Page Program (PP) commandis not executed.
As soon as CS# is driven high, the self-timed Page Program cycle (whose duration is tPP) is initiated. While the Page
Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The
Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At some unspecified
time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
A Page Program (PP) command is not executed when it is applied to a page protected by the Block Protect (BP2,
BP1, BP0).
Figure8. Page Program Sequence Diagram
CS#
5

6

7

8

9 10

Command24-bit address

3

23 22 21

2

1

0 7

6

5

4

3

2

1

2079

02H

Data Byte 1

2078

SI

28 29 30 31 32 33 34 35 36 37 38 39

2077

4

2075

3

2076

2

2074

1

1

0

0

MSB

CS#

40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

2072

MSB

2073

0

SCLK

SCLK
SI

Data Byte 2
7

6

5

4

MSB

3

2

Data Byte 3

1

0 7

6

5

4

3

2

MSB

Data Byte 256

1

0

7

6

5

4

3

2

MSB

7.9. Sector Erase (SE) (20H)
The Sector Erase (SE) command is for erasing the all data of the specific sector. A Write Enable (WREN) commandmust previously have been executed to set the Write Enable Latch (WEL) bit. The Sector Erase (SE) command is enteredby driving CS# low, followed by the command code, and 3-address byte on SI. Any address inside the sector is a valid
address for the Sector Erase (SE) command. CS# must be driven low for the entire duration of the sequence.
The Sector Erase command sequence: CS# goes low � sending Sector Erase command � 3-byte address on SI �
CS# goes high. The command sequence is shown in Figure9. CS# must be driven high after the eighth bit of the last address
byte has been latched in; otherwise the Sector Erase (SE) command is not executed. As soon as CS# is driven high, theself-timed Sector Erase cycle (whose duration is tSE) is initiated. While the Sector Erase cycle is in progress, the Status

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Register is accessed to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during theself-timed Sector Erase cycle, and becomes 0 when it is completed. At some unspecified time before the cycle is completed,
the Write Enable Latch (WEL) bit is reset. A Sector Erase (SE) command applied to a sector which is protected by the Block
Protect (BP2, BP1, BP0) bit (see Table3) is not executed.
Figure9. Sector Erase Sequence Diagram
CS#
SCLK

0

1

2

3

4

5

6

7

8

CommandSI

929 30 31

24 Bits Address

20H

23 22
MSB

2

1

0

7.10. 32KB Block Erase (BE) (52H)
The 32KB Block Erase (BE) command is for erasing the all data of the chosen block. A Write Enable (WREN)
command must previously have been executed to set the Write Enable Latch (WEL) bit. The 32KB Block Erase (BE)command is entered by driving CS# low, followed by the command code, and three address bytes on SI. Any address inside
the block is a valid address for the 32KB Block Erase (BE) command. CS# must be driven low for the entire duration of thesequence.
The 32KB Block Erase command sequence: CS# goes low � sending 32KB Block Erase command � 3-byte address
on SI � CS# goes high. The command sequence is shown in Figure10. CS# must be driven high after the eighth bit of thelast address byte has been latched in; otherwise the 32KB Block Erase (BE) command is not executed. As soon as CS# isdriven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated. While the Block Erase cycle is in progress,
the Status Register is accessed to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1during the self-timed Block Erase cycle, and becomes 0 when it is completed. At some unspecified time before the cycle iscompleted, the Write Enable Latch (WEL) bit is reset. A 32KB Block Erase (BE) command applied to a block which isprotected by the Block Protect (BP2, BP1, BP0) bits (see Table3) is not executed.
Figure10. 32KB Block Erase Sequence Diagram
CS#
SCLK
SI

0

1

2

3

4

5

6

7

8

Command52H

929 30 31

24 Bits Address
23 22
MSB

2

1

0

7.11. 64KB Block Erase (BE) (D8H)
The 64KB Block Erase (BE) command is for erasing the all data of the chosen block. A Write Enable (WREN)
command must previously have been executed to set the Write Enable Latch (WEL) bit. The 64KB Block Erase (BE)command is entered by driving CS# low, followed by the command code, and three address bytes on SI. Any address inside
the block is a valid address for the 64KB Block Erase (BE) command. CS# must be driven low for the entire duration of the

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Uniform Sector
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GD25WD40C/20C

sequence.
The 64KB Block Erase command sequence: CS# goes low � sending 64KB Block Erase command � 3-byte address
on SI � CS# goes high. The command sequence is shown in Figure11. CS# must be driven high after the eighth bit of thelast address byte has been latched in; otherwise the 64KB Block Erase (BE) command is not executed. As soon as CS# isdriven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated. While the Block Erase cycle is in progress,
the Status Register is accessed to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1during the self-timed Block Erase cycle, and becomes 0 when it is completed. At some unspecified time before the cycle iscompleted, the Write Enable Latch (WEL) bit is reset. A 64KB Block Erase (BE) command applied to a block which isprotected by the Block Protect (BP2, BP1, BP0) bits (see Table3) is not executed.
Figure11. 64KB Block Erase Sequence Diagram
CS#
SCLK

0

1

2

3

4

5

6

7

8

9

CommandSI

29 30 31

24 Bits Address

D8H

2

23 22
MSB

1

0

7.12. Chip Erase (CE) (60/C7H)
The Chip Erase (CE) command is for erasing the all data of the chip. A Write Enable (WREN) command must
previously have been executed to set the Write Enable Latch (WEL) bit .The Chip Erase (CE) command is entered by driving
CS# Low, followed by the command code on Serial Data Input (SI). CS# must be driven Low for the entire duration of thesequence.
The Chip Erase command sequence: CS# goes low � sending Chip Erase command � CS# goes high. The
command sequence is shown in Figure12. CS# must be driven high after the eighth bit of the command code has beenlatched in, otherwise the Chip Erase command is not executed. As soon as CS# is driven high, the self-timed Chip Erase
cycle (whose duration is tCE) is initiated. While the Chip Erase cycle is in progress, the Status Register may be read to checkthe value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Chip Erase cycle, andis 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
The Chip Erase (CE) command is executed if the Block Protect (BP2, BP1, BP0) bits are all 0. The Chip Erase (CE)command is not executed if any sector is under protection.
Figure12. Chip Erase Sequence Diagram
CS#
SCLK
SI

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0

1

2

3

4

5

Command

60H or C7H

21

Rev.2.1

6

7

Uniform Sector
Standard and Dual Serial Flash

GD25WD40C/20C

7.13. Deep Power-Down (DP) (B9H)
Executing the Deep Power-Down (DP) command is the only way to enter the lowest consumption mode (the DeepPower-Down Mode). Unlike deselecting the device by driving CS# high, or entering into the Standby Mode (if there is nointernal cycle currently in progress), the Deep Power-Down Mode provides an extra software protection mechanism while
the device is not in active use. The only access to this mode is by executing the Deep Power-Down (DP) command. Since
in the Deep Power-Down mode, the device ignores all Write, Program and Erase commands. Once the device is in the
Deep Power-Down Mode, all commands are ignored except the Release from Deep Power-Down and Read Device ID (RDI)command. This releases the device from this mode. The Release from Deep Power-Down and Read Device ID (RDI)command also allows the Device ID of the device to be output on SO.
The Deep Power-Down Mode automatically stops at Power-Down, and the device always Power-Up in the Standby
Mode. The Deep Power-Down (DP) command is entered by driving CS# low, followed by the command code on SI. CS#
must be driven low for the entire duration of the sequence.
The Deep Power-Down command sequence: CS# goes low � sending Deep Power-Down command � CS# goeshigh. The command sequence is shown in Figure13. CS# must be driven high after the eighth bit of the command code has
been latched in; otherwise the Deep Power-Down (DP) command is not executed. As soon as CS# is driven high, it requires
a delay of tDP before the supply current is reduced to ICC2 and the Deep Power-Down Mode is entered. Any Deep PowerDown (DP) command, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on thecycle that is in progress.
Figure13. Deep Power-Down Sequence Diagram

CS#
SCLK
SI

tDP

0 1 2 3 4 5 6 7
CommandStand-by mode Deep Power-down mode

B9H

7.14. Release from Deep Power-Down / Read Device ID (ABH)
The Release from Power-Down and Read Device ID command is a multi-purpose command, which can be used torelease the device from the Power-Down state or obtain the devices electronic identification (ID) number.
When used to release the device from the Power-Down state, the command is issued by driving the CS# pin low,shifting the instruction code “ABH” and driving CS# high as shown in Figure14. Release from Power-Down will take thetime duration of tRES1 (See AC Characteristics) before the device will resume normal operation and other command are
accepted. The CS# pin must keep high during the tRES1 time duration.
When used only to obtain the Device ID while not in the Power-Down state, the command is initiated by driving theCS# pin low and shifting the instruction code “ABH” followed by 3-dummy byte. The Device ID bits are then shifted out on
the falling edge of SCLK with most significant bit (MSB) first as shown in Figure15. The Device ID value for the
GD25WD40C/20C is listed in Manufacturer and Device Identification table. The Device ID can be read continuously. The
command is completed by driving CS# high.
When used to release the device from the Power-Down state and obtain the Device ID, the command is the sameas previously described, and shown in Figure15, except that after CS# is driven high it must remain high for a time
duration of tRES2 (See AC Characteristics). After this time duration the device will resume normal operation and other

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Uniform Sector
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GD25WD40C/20C

command will be accepted. If the Release from Power-Down and Read Device ID command is issued while an Erase,
Program or Write cycle is in process (when WIP equal 1) the command is ignored and will not have any effects on thecurrent cycle.
Figure14. Release Power-Down Sequence Diagram

CS#

0

SCLK

1

2

3

4

5

6

t RES1

7

CommandSI

ABH
Deep Power-down modeStand-by mode

Figure15. Release Power-Down and Read Device ID Sequence Diagram
CS#

0

1

2

3

4

5

6

7

8

9

29 30 31 32 33 34 35 36 37 38

SCLKCommand
SI

SO

ABH

High-Zt RES23 Dummy Bytes

23 22

2

1

0

MSB

MSB

7

6

Device ID
5 4 3 2

10

Deep Power-down Mode Stand-by Mode

7.15. Read Manufacture ID/ Device ID (REMS) (90H)
The Read Manufacturer/Device ID command is an alternative to the Release from Power-Down / Device ID commandthat provides both the JEDEC assigned Manufacturer ID and the specific Device ID.
The command is initiated by driving the CS# pin low and shifting the command code “90H” followed by a 24-bit address(A23-A0) of 000000H. After that, the Manufacturer ID and the Device ID are shifted out on the falling edge of SCLK withmost significant bit (MSB) first as shown in Figure16. If the 24-bit address is initially set to 000001H, the Device ID will beread first.

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Uniform Sector
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GD25WD40C/20C

Figure16. Read Manufacture ID/ Device ID Sequence Diagram
CS#

0

SCLK

1

2

3

4

5

6

7

8

9 10

CommandSI

28 29 30 31

24-bit address

90H

3

23 22 212

1

0

High-ZSOCS#

33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

32

SCLK
SI

7

SO

6

Device ID

Manufacturer ID
5 4 3 2 1

0

MSB

7

6

5

4

3

2

1

0

MSB

7.16. Read Identification (RDID) (9FH)
The Read Identification (RDID) command allows the 8-bit manufacturer identification to be read, followed by two bytes
of device identification. The device identification indicates the memory type in the first byte, and the memory capacity of thedevice in the second byte. Any Read Identification (RDID) command while an Erase or Program cycle is in progress is notdecoded, and has no effect on the cycle that is in progress. The Read Identification (RDID) command should not be issued
while the device is in Deep Power-Down Mode.
The device is first selected by driving CS# low. Then, the 8-bit command code for the command is shifted in. This isfollowed by the 24-bit device identification, stored in the memory. Each bit is shifted out on the falling edge of Serial Clock.
The command sequence is shown in Figure17. The Read Identification (RDID) command is terminated by driving CS# highat any time during data output. When CS# is driven high, the device is in the Standby Mode. Once in the Standby Mode,the device waits to be selected, so that it can receive, decode and execute commands.
Figure17. Read Identification ID Sequence Diagram

CS#

0

SCLK
SI

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15

7

6

9FH
Command

SO

MSB

CS#

Manufacturer ID
5 4 3 2 1

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

SCLK
SI

7

SO

MSB

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6

5 4 3 2 1
Memory TypeJDID15-JDID8

0

7

MSB
24

Rev.2.1

6

5 4 3 2
Capacity
JDID7-JDID0

1

0

0

Uniform Sector
Standard and Dual Serial Flash

GD25WD40C/20C

7.17. Read Unique ID (4BH)
The Read Unique ID command accesses a factory-set read-only 128bit number that is unique to each device. The
Unique ID can be used in conjunction with user software methods to help prevent copying or cloning of a system.
The Read Unique ID command sequence: CS# goes low � sending Read Unique ID command � 3-Byte Address(000000H) �Dummy Byte�128bit Unique ID Out �CS# goes high.
Figure18. Read Unique ID Sequence Diagram
CS#

0

SCLK

1

2

3

4

5

6

7

8

CommandSI

9 10

28 29 30 31

24-bit address

4BH

3

23 22 212

1

0

High-ZSOCS#

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
SI
SO

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Dummy Byte

7

6

5

4

3

2

1

0

7 6
MSB

25

Rev.2.1

Data Out1
5 4 3 2

10Data Out2
7 6 5
MSB

Uniform Sector
Standard and Dual Serial Flash

GD25WD40C/20C

8. ELECTRICAL CHARACTERISTICS
8.1. POWER-ON TIMING
Figure19. Power-On Timing Sequence Diagram
VCC
VCC(max.)
Chip Selection is not allowed

VCC(min.)tVSL

VPWD(max.)

Full Device
AccessAllowedtPWD
Time

Table 5. Power-Up Timing and Write Inhibit Threshold
SymbolParameter

Min.

tVSL

VCC (min.) to device operation

0.3

VWI

Write Inhibit Voltage

1

VPWD

VCC voltage needed to below VPWD for ensuring initialization will occur

tPWD

The minimum duration for ensuring initialization will occur

300

Max.

Unit
ms

1.55

V

0.5

V
us

8.2. INITIAL DELIVERY STATE
The device is delivered with the memory array erased: all bits are set to 1(each byte contains FFH).The Status Registercontains 00H (all Status Register bits are 0).

8.3. ABSOLUTE MAXIMUM RATINGS
Parameter
Ambient Operating Temperature

Value

Unit

-40 to 85

�-40 to 105-40 to 125
Storage Temperature-65 to 150

�Applied Input/Output Voltage-0.6 to VCC+0.4

V

Transient Input/Output Voltage (note: overshoot)-2.0 to VCC+2.0

V-0.6 to 4.2

V

VCC

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Uniform Sector
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GD25WD40C/20C

Figure20. Maximum Negative/positive Overshoot Diagram
Maximum Negative Overshoot Waveform
20ns

Maximum Positive Overshoot Waveform

20ns

20ns

Vss
Vcc + 2.0V

Vss-2.0V
Vcc

20ns

20ns

20ns

8.4. CAPACITANCE MEASUREMENT CONDITIONS
SymbolParameter

Min

Typ.

Max

Unit

Conditions

CIN

Input Capacitance6

pF

VIN=0V

COUT

Output Capacitance8pF

VOUT=0V

CL

Load Capacitance

30

pF

Input Rise And Fall time

5ns

Input Pulse Voltage

0.1VCC to 0.8VCC

V

Input Timing Reference Voltage

0.2VCC to 0.7VCC

V

Output Timing Reference Voltage

0.5VCCV

Figure 21. Input Test Waveform and Measurement Level

0.8VCC

Input timing reference level

0.1VCC

0.7VCC
0.2VCC

Output timing reference level
AC Measurement Level

Note: Input pulse rise and fall time are <5ns

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0.5VCCUniform Sector
Standard and Dual Serial Flash

GD25WD40C/20C

8.5. DC CHARACTERISTICS(T= -40�~85�, VCC=1.65~3.6V)
SymbolParameter

Test Condition

Min.

Typ.

Max.

Unit.

ILI

Input Leakage Current

±2

��

ILO

Output Leakage Current

±2

��

ICC1

Standby Current

0.1

2

��

0.1

2

��

3

6

mA

2.5

4.5

mA

1.3

3.5

mA

1.6

4

mA

1.2

2.5

mA

CS#=VCC,
VIN=VCC or VSS

ICC2Deep Power-Down Current

CS#=VCC,
VIN=VCC or VSS
CLK=0.1VCC / 0.9VCC
at 100MHz,
Q=Open(*1 I/O)
CLK=0.1VCC / 0.9VCC
at 80MHz,
Q=Open(*1 I/O,*2
Output)
CLK=0.1VCC / 0.9VCC

ICC3

Operating Current (Read)at 50MHz,
Q=Open(*1 I/O)
CLK=0.1VCC / 0.9VCC
at 40MHz,
Q=Open(*1 I/O,*2
Output)
CLK=0.1VCC / 0.9VCC
at 16MHz,
Q=Open(*1 I/O,*2
Output)

ICC4

Operating Current (PP)

CS#=VCC

7

20

mA

ICC5

Operating Current (WRSR)

CS#=VCC

7

20

mA

ICC6

Operating Current (SE)

CS#=VCC

7

20

mA

ICC7

Operating Current (BE)

CS#=VCC

7

20

mA

ICC8

Operating Current (CE)

CS#=VCC

7

20

mA

VIL

Input Low Voltage-0.5

0.2VCCV

VIH

Input High Voltage

0.7VCC

VCC+0.4

V

VOL

Output Low Voltage

IOL ������

0.4

V

VOH

Output High Voltage

IOH =-�����

VCC-0.2

Note:
1. Typical value tested at T = 25�. Icc3 (>80MHz) tested at VCC = 3.3V. Icc3 (<80MHz) tested at VCC = 1.8V.
2. Value guaranteed by design and/or characterization, not 100% tested in production.

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VUniform Sector
Standard and Dual Serial Flash

GD25WD40C/20C(T= -40�~105�, VCC=1.65~3.6V)
SymbolParameter

Test Condition

Min.

Typ.

Max.

Unit.

ILI

Input Leakage Current

±2

��

ILO

Output Leakage Current

±2

��

ICC1

Standby Current

0.1

10

��

0.1

10

��

3

22

mA

2.5

20

mA

1.6

7

mA

1.2

5.5

mA

CS#=VCC,
VIN=VCC or VSS

ICC2Deep Power-Down Current

CS#=VCC,
VIN=VCC or VSS
CLK=0.1VCC / 0.9VCC
at 100MHz,
Q=Open(*1 I/O)
CLK=0.1VCC / 0.9VCC
at 80MHz,
Q=Open(*1 I/O,*2
Output)

ICC3

Operating Current (Read)

CLK=0.1VCC / 0.9VCC
at 40MHz,
Q=Open(*1 I/O,*2
Output)
CLK=0.1VCC / 0.9VCC
at 16MHz,
Q=Open(*1 I/O,*2
Output)

ICC4

Operating Current (PP)

CS#=VCC

7

30

mA

ICC5

Operating Current (WRSR)

CS#=VCC

7

30

mA

ICC6

Operating Current (SE)

CS#=VCC

7

30

mA

ICC7

Operating Current (BE)

CS#=VCC

7

30

mA

ICC8

Operating Current (CE)

CS#=VCC

7

30

mA

VIL

Input Low Voltage-0.5

0.2VCCV

VIH

Input High Voltage

0.7VCC

VCC+0.4

V

VOL

Output Low Voltage

IOL ������

0.4

V

VOH

Output High Voltage

IOH =-�����

VCC-0.2

Note:
1. Typical value tested at T = 25�. Icc3 (>80MHz) tested at VCC = 3.3V. Icc3 (<80MHz) tested at VCC = 1.8V.
2. Value guaranteed by design and/or characterization, not 100% tested in production.

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VUniform Sector
Standard and Dual Serial Flash

GD25WD40C/20C(T= -40�~125�, VCC=1.65~3.6V)
SymbolParameter

Test Condition

Min.

Typ.

Max.

Unit.

ILI

Input Leakage Current

±2

��

ILO

Output Leakage Current

±2

��

ICC1

Standby Current

0.1

15

��

0.1

15

��

3

22

mA

2.5

20

mA

1.6

7

mA

1.2

5.5

mA

CS#=VCC,
VIN=VCC or VSS

ICC2Deep Power-Down Current

CS#=VCC,
VIN=VCC or VSS
CLK=0.1VCC / 0.9VCC
at 100MHz,
Q=Open(*1 I/O)
CLK=0.1VCC / 0.9VCC
at 80MHz,
Q=Open(*1 I/O,*2
Output)

ICC3

Operating Current (Read)

CLK=0.1VCC / 0.9VCC
at 40MHz,
Q=Open(*1 I/O,*2
Output)
CLK=0.1VCC / 0.9VCC
at 16MHz,
Q=Open(*1 I/O,*2
Output)

ICC4

Operating Current (PP)

CS#=VCC

7

30

mA

ICC5

Operating Current (WRSR)

CS#=VCC

7

30

mA

ICC6

Operating Current (SE)

CS#=VCC

7

30

mA

ICC7

Operating Current (BE)

CS#=VCC

7

30

mA

ICC8

Operating Current (CE)

CS#=VCC

7

30

mA

VIL

Input Low Voltage-0.5

0.2VCCV

VIH

Input High Voltage

0.7VCC

VCC+0.4

V

VOL

Output Low Voltage

IOL ������

0.4

V

VOH

Output High Voltage

IOH =-�����

VCC-0.2

Note:
1. Typical value tested at T = 25�. Icc3 (>80MHz) tested at VCC = 3.3V. Icc3 (<80MHz) tested at VCC = 1.8V.
2. Value guaranteed by design and/or characterization, not 100% tested in production.

http://www.elm-tech.com

30

Rev.2.1

VUniform Sector
Standard and Dual Serial Flash

GD25WD40C/20C

8.6. AC CHARACTERISTICS(T= -40�~85�, VCC=1.65~3.6V, CL=30pf)
Symbol
fC1
fC2
fC3
fR1
fR2
fR3

Parameter

Min.

Typ.

Serial Clock Frequency For: Fast read (0BH), on 3.0 – 3.6V
power supply
Serial Clock Frequency For: Fast read (0BH), on 2.1 – 3.0V
power supply
Serial Clock Frequency For: Fast read (0BH), on 1.65 – 2.1V
power supply
Serial Clock Frequency For: Read (03H), Dual Output (3BH), on
3.0 – 3.6V power supply
Serial Clock Frequency For: Read (03H), Dual Output (3BH), on
2.1 – 3.0V power supply
Serial Clock Frequency For: Read (03H), Dual Output (3BH), on
1.65 – 2.1V power supply

Max.

Unit.

100

MHz

70

MHz

50

MHz

80

MHz

60

MHz

40

MHz

tCLH1

Serial Clock High Time for 2.1 – 3.6V Power Supply

4

ns

tCLH2

Serial Clock High Time for 1.65 – 2.1V Power Supply

8

ns

tCLL1

Serial Clock Low Time for 2.1 – 3.6V Power Supply

4

ns

tCLL2

Serial Clock Low Time for 1.65 – 2.1V Power Supply

8

ns

tCLCH

Serial Clock Rise Time (Slew Rate)

0.1

V/ns

tCHCL

Serial Clock Fall Time (Slew Rate)

0.1

V/ns

tSLCH

CS# Active Setup Time

10

ns

tCHSH

CS# Active Hold Time

10

ns

tSHCH

CS# Not Active Setup Time

10

ns

tCHSL

CS# Not Active Hold Time

10

ns

tSHSL

CS# High Time (Read/Write)

40

ns

tSHQZ

Output Disable Time

tCLQX

Output Hold Time

0

ns

tDVCH

Data In Setup Time

4

ns

tCHDX

Data In Hold Time

4

ns

tCLQV

Clock Low To Output ValidtWHSL

Write Protect Setup Time Before CS# Low

20

ns

tSHWL

Write Protect Hold Time After CS# High

100

ns

tDP

CS# High To Deep Power-Down Mode

tRES1

12

12

ns

ns

0.1

��

0.1

��

0.1

��

5

40

ms

CS# High To Standby Mode Without Electronic Signature
Read

tRES2

CS# High To Standby Mode With Electronic Signature ReadtW

Write Status Register Cycle TimetBP1

Byte Program Time (First Byte)

�

40

97

��

tBP2

Addition Byte Program Time (After First Byte)

�

5

10

��

tPP

Page Programming Time

1.6

6

ms

tSE

Sector Erase Time

150

500

ms

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31

Rev.2.1

Uniform Sector
Standard and Dual Serial Flash

GD25WD40C/20C

tBE1

Block Erase Time (32K Bytes)

0.5

2

s

tBE2

Block Erase Time (64K Bytes)

0.8

3

s

tCE

Chip Erase Time (GD25WD40C/20C)

6/3

15/7.5sNote:
1. Typical values given for TA=25°C VCC = 1.8V.
2. Value guaranteed by design and/or characterization, not 100% tested in production.

http://www.elm-tech.com

32

Rev.2.1

Uniform Sector
Standard and Dual Serial Flash

GD25WD40C/20C(T= -40�~105�, VCC=1.65~3.6V, CL=30pf)
Symbol
fC1
fC2
fC3
fR1
fR2
fR3

Parameter

Min.

Typ.

Serial Clock Frequency For: Fast read (0BH), on 3.0 – 3.6V
power supply
Serial Clock Frequency For: Fast read (0BH), on 2.1 – 3.0V
power supply
Serial Clock Frequency For: Fast read (0BH), on 1.65 – 2.1V
power supply
Serial Clock Frequency For: Read (03H), Dual Output (3BH), on
3.0 – 3.6V power supply
Serial Clock Frequency For: Read (03H), Dual Output (3BH), on
2.1 – 3.0V power supply
Serial Clock Frequency For: Read (03H), Dual Output (3BH), on
1.65 – 2.1V power supply

Max.

Unit.

100

MHz

70

MHz

50

MHz

80

MHz

60

MHz

40

MHz

tCLH1

Serial Clock High Time for 2.1 – 3.6V Power Supply

4

ns

tCLH2

Serial Clock High Time for 1.65 – 2.1V Power Supply

8

ns

tCLL1

Serial Clock Low Time for 2.1 – 3.6V Power Supply

4

ns

tCLL2

Serial Clock Low Time for 1.65 – 2.1V Power Supply

8

ns

tCLCH

Serial Clock Rise Time (Slew Rate)

0.1

V/ns

tCHCL

Serial Clock Fall Time (Slew Rate)

0.1

V/ns

tSLCH

CS# Active Setup Time

10

ns

tCHSH

CS# Active Hold Time

10

ns

tSHCH

CS# Not Active Setup Time

10

ns

tCHSL

CS# Not Active Hold Time

10

ns

tSHSL

CS# High Time (Read/Write)

40

ns

tSHQZ

Output Disable Time

tCLQX

Output Hold Time

0

ns

tDVCH

Data In Setup Time

4

ns

tCHDX

Data In Hold Time

4

ns

tCLQV

Clock Low To Output ValidtWHSL

Write Protect Setup Time Before CS# Low

20

ns

tSHWL

Write Protect Hold Time After CS# High

100

ns

tDP

CS# High To Deep Power-Down Mode

tRES1

12

12

ns

ns

0.1

��

0.1

��

0.1

��

5

40

ms

CS# High To Standby Mode Without Electronic Signature
Read

tRES2

CS# High To Standby Mode With Electronic Signature ReadtW

Write Status Register Cycle TimetBP1

Byte Program Time (First Byte)

�

40

110

��

tBP2

Addition Byte Program Time (After First Byte)

�

5

12

��

tPP

Page Programming Time

1.6

6

ms

tSE

Sector Erase Time

150

550

ms

tBE1

Block Erase Time (32K Bytes)

0.5

2.2

s

tBE2

Block Erase Time (64K Bytes)

0.8

3.5

s

http://www.elm-tech.com

33

Rev.2.1

Uniform Sector
Standard and Dual Serial FlashtCE

Chip Erase Time (GD25WD40C/20C)

6/3

Note:
1. Typical values given for TA=25°C VCC = 1.8V.
2. Value guaranteed by design and/or characterization, not 100% tested in production.

http://www.elm-tech.com

GD25WD40C/20C

34

Rev.2.1

18/9sUniform Sector
Standard and Dual Serial Flash

GD25WD40C/20C(T= -40�~125�, VCC=1.65~3.6V, CL=30pf)
Symbol
fC1
fC2
fC3
fR1
fR2
fR3

Parameter

Min.

Typ.

Serial Clock Frequency For: Fast read (0BH), on 3.0 – 3.6V
power supply
Serial Clock Frequency For: Fast read (0BH), on 2.1 – 3.0V
power supply
Serial Clock Frequency For: Fast read (0BH), on 1.65 – 2.1V
power supply
Serial Clock Frequency For: Read (03H), Dual Output (3BH), on
3.0 – 3.6V power supply
Serial Clock Frequency For: Read (03H), Dual Output (3BH), on
2.1 – 3.0V power supply
Serial Clock Frequency For: Read (03H), Dual Output (3BH), on
1.65 – 2.1V power supply

Max.

Unit.

100

MHz

70

MHz

50

MHz

80

MHz

60

MHz

40

MHz

tCLH1

Serial Clock High Time for 2.1 – 3.6V Power Supply

4

ns

tCLH2

Serial Clock High Time for 1.65 – 2.1V Power Supply

8

ns

tCLL1

Serial Clock Low Time for 2.1 – 3.6V Power Supply

4

ns

tCLL2

Serial Clock Low Time for 1.65 – 2.1V Power Supply

8

ns

tCLCH

Serial Clock Rise Time (Slew Rate)

0.1

V/ns

tCHCL

Serial Clock Fall Time (Slew Rate)

0.1

V/ns

tSLCH

CS# Active Setup Time

10

ns

tCHSH

CS# Active Hold Time

10

ns

tSHCH

CS# Not Active Setup Time

10

ns

tCHSL

CS# Not Active Hold Time

10

ns

tSHSL

CS# High Time (Read/Write)

40

ns

tSHQZ

Output Disable Time

tCLQX

Output Hold Time

0

ns

tDVCH

Data In Setup Time

4

ns

tCHDX

Data In Hold Time

4

ns

tCLQV

Clock Low To Output ValidtWHSL

Write Protect Setup Time Before CS# Low

20

ns

tSHWL

Write Protect Hold Time After CS# High

100

ns

tDP

CS# High To Deep Power-Down Mode

tRES1

12

12

ns

ns

0.1

��

0.1

��

0.1

��

5

40

ms

CS# High To Standby Mode Without Electronic Signature
Read

tRES2

CS# High To Standby Mode With Electronic Signature ReadtW

Write Status Register Cycle TimetBP1

Byte Program Time (First Byte)

�

40

120

��

tBP2

Addition Byte Program Time (After First Byte)

�

5

14

��

tPP

Page Programming Time

1.6

6

ms

tSE

Sector Erase Time

150

600

ms

tBE1

Block Erase Time (32K Bytes)

0.5

2.5

s

tBE2

Block Erase Time (64K Bytes)

0.8

4

s

http://www.elm-tech.com

35

Rev.2.1

Uniform Sector
Standard and Dual Serial FlashtCE

GD25WD40C/20C

Chip Erase Time (GD25WD40C/20C)

6/3

Note:
1. Typical values given for TA=25°C VCC = 1.8V.
2. Value guaranteed by design and/or characterization, not 100% tested in production.
Figure22. Serial Input Timing

tSHSL

CS#
tCHSL

SCLK

tSLCH

tDVCH

tCHSH

MSB

SO

High-Z

tCHCL

tCLCH

tCHDX

SI

tSHCH

LSB

Figure23. Output Timing

CS#

tCLH

SCLK
tCLQV
tCLQX

tCLQV

tCLL

tCLQX

SO

LSB

SI
Least significant address bit (LIB) in

http://www.elm-tech.com

36

Rev.2.1

tSHQZ

20/10

s

Uniform Sector
Standard and Dual Serial Flash

GD25WD40C/20C

9. ORDERING INFORMATIONGD XX XX XX X X X X X
Packing
T or no mark: Tube
Y: Tray
R: Tape and Reel
Green Code
G: Pb Free + Halogen Free Green Package
Temperature Range
I: Industrial (-40� to +85�)
J: Industrial (-40� to +105�)
E: Industrial (-40� to +125�)
F: Industrial+ (-40� to +85�)**Package Type
T: SOP8 150mil
S: SOP8 208mil
O: TSSOP8 173mil
P: DIP8 300mil
K: USON8 (1.5x1.5mm )E: USON8 (3x2mm, 0.45mm thickness )L: WLCSP
Generation
C: C Version
Density
40: 4M bit
20: 2M bit
Series
WD: 1.65~3.6V, 4KB Uniform Sector
Product Family
25: SPI NOR Flash**F grade has implemented additional test flows to ensure higher product quality than I grade.

http://www.elm-tech.com

37

Rev.2.1

9.1.

Uniform Sector
Standard and Dual Serial Flash

Valid Part Numbers

GD25WD40C/20C

Please contact GigaDevice regional sales for the latest product selection and available form factors.
Temperature Range I: Industrial (-40� to +85�)Product Number

Density

GD25WD40CTIG
GD25WD20CTIG
GD25WD40CSIG
GD25WD20CSIG
GD25WD40COIG
GD25WD20COIG
GD25WD40CPIG
GD25WD20CPIG
GD25WD40CKIG
GD25WD20CKIG
GD25WD40CEIG
GD25WD20CEIG
GD25WD40CLIGR

4Mbit
2Mbit
4Mbit
2Mbit
4Mbit
2Mbit
4Mbit
2Mbit
4Mbit
2Mbit
4Mbit
2Mbit
4Mbit

Package TypeSOP8 150mil
SOP8 208mil
TSSOP8 173mil
DIP8 300mil
USON8 (1.5x1.5mm)
USON8 (3x2mm, 0.45mm thickness)
WLCSP

Temperature Range J: Industrial (-40� to +105�)

Product Number

Density

GD25WD40CTJG
GD25WD20CTJG
GD25WD40CSJG
GD25WD20CSJG
GD25WD40COJG
GD25WD20COJG
GD25WD40CPJG
GD25WD20CPJG
GD25WD40CKJG
GD25WD20CKJG
GD25WD40CEJG
GD25WD20CEJG
GD25WD40CLJGR

4Mbit
2Mbit
4Mbit
2Mbit
4Mbit
2Mbit
4Mbit
2Mbit
4Mbit
2Mbit
4Mbit
2Mbit
4Mbit

http://www.elm-tech.com

Package TypeSOP8 150mil
SOP8 208mil
TSSOP8 173mil
DIP8 300mil
USON8 (1.5x1.5mm)
USON8 (3x2mm, 0.45mm thickness)
WLCSP

38

Rev.2.1

Uniform Sector
Standard and Dual Serial Flash

GD25WD40C/20C

Temperature Range E: Industrial (-40� to +125�)

Product Number

Density

GD25WD40CTEG
GD25WD20CTEG
GD25WD40CSEG
GD25WD20CSEG
GD25WD40COEG
GD25WD20COEG
GD25WD40CPEG
GD25WD20CPEG
GD25WD40CKEG
GD25WD20CKEG
GD25WD40CEEG
GD25WD20CEEG
GD25WD40CLEGR

4Mbit
2Mbit
4Mbit
2Mbit
4Mbit
2Mbit
4Mbit
2Mbit
4Mbit
2Mbit
4Mbit
2Mbit
4Mbit

Package TypeSOP8 150mil
SOP8 208mil
TSSOP8 173mil
DIP8 300mil
USON8 (1.5x1.5mm)
USON8 (3x2mm, 0.45mm thickness)
WLCSP

Temperature Range F: Industrial+ (-40� to +85�)Product Number

Density

GD25WD40CTFG
GD25WD20CTFG
GD25WD40CSFG
GD25WD20CSFG
GD25WD40COFG
GD25WD20COFG
GD25WD40CPFG
GD25WD20CPFG
GD25WD40CKFG
GD25WD20CKFG
GD25WD40CEFG
GD25WD20CEFG
GD25WD40CLFGR

4Mbit
2Mbit
4Mbit
2Mbit
4Mbit
2Mbit
4Mbit
2Mbit
4Mbit
2Mbit
4Mbit
2Mbit
4Mbit

http://www.elm-tech.com

Package TypeSOP8 150mil
SOP8 208mil
TSSOP8 173mil
DIP8 300mil
USON8 (1.5x1.5mm)
USON8 (3x2mm, 0.45mm thickness)
WLCSP

39

Rev.2.1

Uniform Sector
Standard and Dual Serial Flash

GD25WD40C/20C

10. PACKAGE INFORMATION
10.1. Package SOP8 150MIL
D
8

5

E

E1

h

L1

L
1

4

“A”

�

b

A2

A
b

Base Metalc
Detail “A”

A1e

Dimensions
Symbol

A

A1

A2

b

c

D

E

E1

Min

-

0.10

1.25

0.31

0.10

4.80

5.80

3.80

Nom

-

0.15

1.45

0.41

0.20

4.90

6.00

3.90

Max

1.75

0.25

1.55

0.51

0.25

5.00

6.20

4.00

Unit
mm

Note:
1. Both the package length and width do not include the mold flash.
2. Seating plane: Max. 0.1mm.

http://www.elm-tech.com

40

Rev.2.1

e

L

L1

0.40
1.27

0.90

1.04

h

�

0.25

0°

-

-

0.50

8°

Uniform Sector
Standard and Dual Serial Flash

GD25WD40C/20C

10.2. Package SOP8 208MIL

D
8

5

E

E1

L
1

4

“A”

L1

�

b
A

A2

b

Base Metalc

Detail “A”

A1e

Dimensions
Symbol

A

A1

A2

b

c

D

E

E1

Min

-

0.05

1.70

0.31

0.15

5.13

7.70

5.18

Nom

-

0.15

1.80

0.41

0.20

5.23

7.90

5.28

Max

2.16

0.25

1.90

0.51

0.25

5.33

8.10

5.38

Unit
mm

Note:
1. Both the package length and width do not include the mold flash.
2. Seating plane: Max. 0.1mm.

http://www.elm-tech.com

41

Rev.2.1

e

L

L1

0.50
1.27

0.85

�
0°

1.31

8°

Uniform Sector
Standard and Dual Serial Flash

GD25WD40C/20C

10.3. Package TSSOP8 173MIL
D
8

5

E1

E

L1

L
1

“A”

4

�
b

A2

A
b

Base Metalc
Detail “A”

A1e

Dimensions
Symbol

A

A1

A2

b

c

D

E

E1

Min

-

0.05

0.80

0.19

0.09

2.90

6.20

4.30

Nom

-

0.10

1.00

0.25

0.15

3.00

6.40

4.40

Max

1.20

0.15

1.05

0.30

0.20

3.10

6.60

4.50

Unit
mm

Notes:
1. Both package length and width do not include mold flash.
2. Seating plane: Max. 0.1mm.

http://www.elm-tech.com

42

Rev.2.1

e

L

L1

0.45
0.65

0.75

�
0°

1.00

8°

Uniform Sector
Standard and Dual Serial Flash

GD25WD40C/20C

10.4. Package DIP8 300MIL

1

4

E

E1

c

�

8

5

eA

D

A

A2

A1
L

e

b1
b

Dimensions
Symbol

A

A1

A2

b

b1

C

D

E

E1

Min

-

0.38

3.00

1.14

0.36

0.20

9.02

7.62

6.10

Nom

-

-

3.30

1.52

0.46

0.25

9.27

7.87

6.35

Max

3.88

-

3.50

1.78

0.56

0.35

9.59

8.26

6.60

Unit
mm

Note: Both the package length and width do not include the mold flash.

http://www.elm-tech.com

43

Rev.2.1

e

2.54

L

eA

�

2.92

8.45

0°

3.30

8.90

-

3.81

9.35

11°

Uniform Sector
Standard and Dual Serial Flash

GD25WD40C/20C

10.5. Package USON8 (1.5*1.5mm)
A3

D

A2

PIN 1#E

A1
A

Top View
L

L1

Side View

D2

K1
K2

5

4

e

E2

b

8

1

E1

K

D1
Bottom View
Dimensions
Symbol
Unit
Min

A

A1

0.40 0.00

mm Nom 0.45 0.02
Max

0.50 0.05

A2

A3

0.33 0.127
REF REF

b

D

E

D1

0.13 1.40 1.40
0.18 1.50 1.50
0.25 1.60 1.60

E10.20 0.05
REF REF

D2

E2

0.60 1.20
0.70 1.30
0.80 1.40

e
0.40
REF

L
0.15
0.20
0.25

L1

K

K1

K2

0.06

0.20

0.10

0.15

REF

REF

REF

REF

Note:
1. Both the package length and width do not include the mold flash.
2. The exposed metal pad area on the bottom of the package is floating.
3. Coplanarity ���������������������������������������
4. The lead shape may be of little difference according to different package factories. These lead shapes
are compatible with each other.

http://www.elm-tech.com

44

Rev.2.1

Uniform Sector
Standard and Dual Serial Flash

GD25WD40C/20C

10.6. Package USON8 (3*2mm, thickness 0.45mm)c

D

PIN 1#E

A1
A

Top View

Side View

D1

L1

4

5

E1

e

b

1

8

L
Bottom View

Dimensions
Symbol

A

A1

c

b

D

D1

E

E1

Min

0.40

0.00

0.10

0.20

2.90

0.15

1.90

1.55

Nom

0.45

0.02

0.15

0.25

3.00

0.20

2.00

1.60

Max

0.50

0.05

0.20

0.30

3.10

0.25

2.10

1.65

Unit
mm

e

L

L1

0.30
0.50

0.35

0.10

0.40

Note:
1. Both the package length and width do not include the mold flash.
2. The exposed metal pad area on the bottom of the package is floating.
3. Coplanarity ���������������������������������������
4. The lead shape may be of little difference according to different package factories. These lead shapes
are compatible with each other.

http://www.elm-tech.com

45

Rev.2.1

Uniform Sector
Standard and Dual Serial Flash

GD25WD40C/20C

10.7. Package WLCSP

PIN 1

E

1

X2

X1
2

2

A

1

A

b

B

D

PIN 1

Y1

B

e
C

C

Y2

Bottom View
(Ball Side)Top View(Mark Side)

A3
A A2
A1
Side View

Dimensions
Symbol

A

A1

A2

Min

0.280

0.072

0.175

Nom

0.305

0.080

0.200

Max

0.330

0.088

0.225

Unit
mm

Note:
Please contact GigaDevice for full dimension information.

http://www.elm-tech.com

46

Rev.2.1

A3

e

0.025

0.275

BSC

BSC

b
0.144
0.160
0.176

Uniform Sector
Standard and Dual Serial Flash

GD25WD40C/20C

11. REVISION HISTORY
Version No

Description

Page

Date

1.0

Initial ReleaseALL

2017-6-20

1.1

Modify AC CHARACTERISTICS: fc,FrP27

2017-6-29

Modify VWI in Table 5 from 1.4 to 1.5

P24

Add Icc3 at 50MHz. Typ.= 6mA; Max. = 8mA

P24

Modify ID15-ID8 from 40 to 64

P13

Add Transient Input/Output Voltage of “-2.0V to VCC+2.0V”

P24

Modify tpp max. value from 4ms to 6ms

P27

Modify Icc3 @50MHz from 6-8mA to 5-7mA

P26

Modify Icc3 @40MHz from 6-8mA to 3.5-5mA

P26

Add Icc3 @16MHz of 2.2-4mA

P26

Modify the description of 60/C7H command: delete “or all 1” at the end

P20

1.2

1.3

1.4

2017-7-10

2017-7-13

2017-8-23of the last but one sentence.
Modify the description of ABH command: modify “figure 14” to “figure

P2115” at the end of 2nd sentence in 3rd paragraph.

1.5

Modify VCC from “-0.5 to 4.2” to “-0.6 to 4.2”.

P24

Modify tw from 4-30ms to 5-40ms

P27

Add Icc8 in DC CHARACTERISTICS, of which the max. value is 15mA.

P26

Add Tbp1 of 15-30us and Tbp2 of 2.5-5us in AC CHARACTERISTICS.

P27

Modify Tce of GD25WD40C from 5-10s to 6-15s.

P27

Modify Tce of GD25WD20C from 2.5-6s to 3-7.5s.

P27

Modify Tbe(64K Bytes) max. value from 2.5s to 3s.

P27Classify Fc and Fr by power supply. Fc max. values are 100MHz,

P27

2017-8-28

70HMz and 50MHz for 3.0-3.6V, 2.1-3.0V, 1.65-2.1V. Fr max values are
80MHz, 60MHz and 40MHz for 3.0-3.6V, 2.1-3.0V, 1.65-2.1V.

1.6

1.7

1.8

1.9

Add Icc3 @100MHz of 13-18mA and @80MHz of 12-15mA.

P26

Modify tCLH and tCLL from 8ns to 4ns

P27

Delete Icc3 @50MHz

P26

Modify Icc4-Icc7 max value from 10mA to 15mA

P26

Modify tCLH and tCLL for 1.65 – 2.1V power supply from 4ns to 8ns

P27

Update the description all packages

P31-35Modify Icc1 max. value from 1uA to 2uA

P26

Modify Icc2 max. value from 1uA to 2uA

P26

Modify Tbp1 from 15~30us to 40~97us

P27

Modify Tbp2 from 2.5~5us to 5~10us

P27

Modify Tvsl min value from 5ms to 0.5ms

P24

Add “J” and “E” to 7th code of Ordering Information

P29

Add DC/AC characteristics @-40�~105�

P27/31

Add DC/AC characteristics @-40�~125�

P28/32Modify Ordering Information

P35

Modify VWI max value from 1.5V to 1.55V

P24

Modify Tvsl max value from 0.5ms to 0.3ms

P24

http://www.elm-tech.com

47

Rev.2.1

2017-12-25

2018-4-19

2018-7-11

2018-10-24

Uniform Sector
Standard and Dual Serial Flash

2.0

2.1

GD25WD40C/20C

Add Package USON8 1.5*1.5mm

P43

Add Package WLCSPP45

Modify Icc3 typ. value @100MHz from 13mA to 3mA

P28, 29, 30

Modify Icc3 typ. value @80MHz from 12mA to 2.5mA

P28, 29, 30

Modify Icc3 typ. value @40MHz from 3.5mA to 1.6mA

P28, 29, 30

Modify Icc3 typ. value @16MHz from 2.2mA to 1.2mA

P28, 29, 30

Modify Icc3 max. value @100MHz @-40� to 85� from 18mA to 6mA

P28

Modify Icc3 max. value @80MHz @-40� to 85� from 15mA to 4.5mA

P28

Add Icc3 @50MHz @-40�-85� of 1.3~3.5mA

P28

Modify “L” (min) of USON8 1.5x1.5 package from 0.125mm to 0.15mm

P44

Add 4BH commandP25

Add Icc4-8 typical value

http://www.elm-tech.com

P28, 29, 30

48

Rev.2.1

2019-4-30

2019-9-12

Uniform Sector
Standard and Dual Serial Flash

GD25WD40C/20C

Important NoticeThis document is the property of GigaDevice Semiconductor (Beijing) Inc. and its subsidiaries (the "Company"). This
document, including any product of the Company described in this document (the “Product”), is owned by the Company
under the intellectual property laws and treaties of the People’s Republic of China and other jurisdictions worldwide. The
Company reserves all rights under such laws and treaties and does not grant any license under its patents, copyrights,
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including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. The Company
does not assume any liability arising out of the application or use of any Product described in this document. Any information
provided in this document is provided only for reference purposes. It is the responsibility of the user of this document toproperly design, program, and test the functionality and safety of any application made of this information and any resulting
product. Except for customized products which has been expressly identified in the applicable agreement, the Products aredesigned, developed, and/or manufactured for ordinary business, industrial, personal, and/or household applications only.
The Products are not designed, intended, or authorized for use as components in systems designed or intended for theoperation of weapons, weapons systems, nuclear installations, atomic energy control instruments, combustion control
instruments, airplane or spaceship instruments, traffic signal instruments, life-support devices or systems, other medical
devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substancesmanagement, or other uses where the failure of the device or Product could cause personal injury, death, property or
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Products in accordance with the applicable laws and regulations. The Company is not liable, in whole or in part, andcustomers shall and hereby do release the Company as well as it’s suppliers and/or distributors from any claim, damage,or other liability arising from or related to all Unintended Uses of the Products. Customers shall indemnify and hold theCompany as well as it’s suppliers and/or distributors harmless from and against all claims, costs, damages, and otherliabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of the Products.
Customers shall discard the device according to the local environmental law.
Information in this document is provided solely in connection with the Products. The Company reserves theright to make changes, corrections, modifications or improvements to this document and the Products andservices described herein at any time, without notice.

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49

Rev.2.1