Table of Contents

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Application Report

ITU-T G.8262 Compliance Test Results for the
LMK5C33216

ABSTRACTThe LMK5C33216 is an ultra-low jitter clock synchronizer with integrated EEPROM targeted for communicationand industrial applications. This document details the compliance of the LMK5C33216 to the ITU-T G.8262(timing characteristics of a synchronous Ethernet equipment slave clock) standard.

Table of Contents
1 Introduction.............................................................................................................................................................................2
2 Wander Generation.................................................................................................................................................................4
2.1 Wander Generation MTIE Option 1, G.8262 EEC Option 1............................................................................................... 5
2.2 Wander Generation TDEV G.8262 EEC Option 1..............................................................................................................6
2.3 Wander Generation MTIE Stratum ITU-T G.8262 EEC Option 2.......................................................................................7
2.4 Wander Generation TDEV G.8262 EEC Option 2..............................................................................................................8
3 Wander Transfer......................................................................................................................................................................9
3.1 Transfer Function of the PLL for Option 1 and Option 2.................................................................................................... 9
3.2 Wander Transfer TDEV G.8262 Option 2.........................................................................................................................11
4 Wander Tolerance................................................................................................................................................................. 11
4.1 Wander Tolerance G.8262 Option 1................................................................................................................................. 11
4.2 Wander Tolerance G.8262 Option 2.................................................................................................................................12
5 Jitter Tolerance..................................................................................................................................................................... 12
5.1 Jitter Tolerance G.8262 Option 1 and Option 2................................................................................................................12
6 Phase Transient Generation................................................................................................................................................ 15
6.1 Short-Term Phase Transient Response G.8262 Option 1................................................................................................15
6.2 Short-Term Phase Transient Response G.8262 Option 2................................................................................................17
6.3 Phase Transient Generation With Signal Interruptions G.8262 EEC Option 1................................................................ 18
6.4 Phase Discontinuity G.8262 Option 1.............................................................................................................................. 20
6.5 Phase Discontinuity G.8262 Option 2.............................................................................................................................. 21
7 Holdover................................................................................................................................................................................ 21
7.1 Holdover G.8262 Option 1............................................................................................................................................... 21
7.2 Holdover G.8262 Option 2............................................................................................................................................... 22
8 Free-Run Accuracy...............................................................................................................................................................23
8.1 Free-Run Accuracy G.8262 Option 1 and Option 2......................................................................................................... 23
9 Pull-In and Hold-In................................................................................................................................................................ 23
9.1 Pull-In Range G.8262 Option 1 and Option 2.................................................................................................................. 23
10 Conclusion.......................................................................................................................................................................... 24
11 References...........................................................................................................................................................................24

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Introduction

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1 Introduction
The LMK5C33216 device is a high-performance network clock generator, synchronizer, and jitter attenuator withadvanced reference clock selection and hitless switching capabilities designed to meet the stringent
requirements of communications infrastructure applications.
This document contains the summary of the test setups and measured results highlighting compliance to ITU-T
G.8262 (Timing characteristics of a synchronous Ethernet equipment slave clock) standard. The device-undertest (LMK5C33216) was configured using Texas Instruments' TICS Pro Silicon EVM Programming Tool. Unlessspecified otherwise, the LMK5C33216 Digital PLL loop bandwidth for EEC-Option 1 was set to 10 Hz and for
EEC-Option 2 to 0.1 Hz.
All measurement results included in this document are for DPLL1. The measurement results for DPLL1 are an
accurate representation of compliance characteristics for all three DPLLs. All three DPLLs passed standard
compliance test requirements.
Throughout this document, the acronym MTIE stands for maximum time interval error and the acronym TDEV
stands for time deviation.
Testing was performed using the Calnex Rb/GPS frequency reference and Calnex Paragon-T hardware. Other
test hardware was used as required for the measurements.
Notable features of this high-performance device includes:• Hitless Switching with minimal phase transients (< 100 ps)• Ultra High-Performance VCO allows use of a low-cost holdover reference without sacrificing performance• High-Performance DPLL Channel with Programmable loop bandwidth for jitter and wander filtering suitable
for EEC Option 1 and EEC Option 2• Reference Priority Selection, Gapped Clock and Runt Pulse Detectors, Automatic/Manual Switchover,Holdover, and Tuning Word History
Table 1-1. DPLL1 ITU-T G.8262 Compliance Summary
EEC OPT 1(SECTION IN G.8262)

EEC OPT 2(SECTION IN G.8262)

SECTIONDESCRIPTIONCOMPLIANT

Section 2.1

MTIE EEC Option 1; Must not exceed MTIE mask

8.1.1

Section 2.2

TDEV EEC Option 1; Must not exceed TDEV mask

8.1.1

Section 2.3

MTIE EEC Option 2; Must not exceed MTIE mask

8.1.2

Yes

Section 2.3

TDEV EEC Option 2; Must not exceed TDEV mask

8.1.2

Yes

10.2

Yes

10.2

Yes

WANDER GENERATIONYes
Yes

WANDER TRANSFER
Section 3.1

Transfer function of the PLL for EEC Option 1 and EEC
Option 2; Must meet bandwidth requirements

Section 3.2

Wander Transfer TDEV G.8262 for EEC Option 2; Must
not exceed TDEV mask

10.1

WANDER TOLERANCE
Section 4.1

Wander Tolerance EEC Option 1; Must tolerate at least
input wander defined by MTIE/TDEV mask

Section 4.2

Wander Tolerance EEC Option 2; Must tolerate at least
input wander defined by TDEV mask

Section 5.1

Jitter Tolerance for EEC Option 1 and EEC Option 2;
Must tolerate jitter defined by UI mask

Section 6.1

Short Term Phase Transient EEC Option 1; Must notexceed limits set by standard

Section 6.2

Short Term Phase Transient EEC Option 2; Must notexceed MTIE mask set by standard

Section 6.3

Phase Transient Generation with Signal Interruptions
EEC Option 1; Must not exceed phase variation limit

9.1.1

Yes
9.1.2

Yes

9.2.1

Yes

JITTER TOLERANCE
9.2.1

PHASE TRANSIENT GENERATION

2

11.1.1Yes
11.1.211.4.211.3.1

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Yes
Yes

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Table 1-1. DPLL1 ITU-T G.8262 Compliance Summary (continued)
SECTIONDESCRIPTIONEEC OPT 1(SECTION IN G.8262)

Section 6.4

Phase Discontinuity EEC Option 1; Must not exceed
phase variation limits

11.4.1

Section 6.5

Phase Discontinuity EEC Option 2; Must not exceed
MTIE mask set by standard

Section 7.1

Holdover EEC Option 1; Must not exceed TIE mask set
by standard

Section 7.2

Holdover EEC Option 2; Must meet TIE mask set bystandard

EEC OPT 2(SECTION IN G.8262)

COMPLIANT
Yes

11.4.2Yes

HOLDOVER PERFORMANCE
11.2.1Yes
11.2.2

Yes

6.1

6.2

Yes

7.1.1

7.1.2
7.2.2

Yes

FREE-RUN ACCURACY
Section 8.1

Free-run Accuracy EEC Option 1 and Option 2; Must notexceed ±4.6 ppm

Section 9

Pull-in and Hold-in EEC Option 1 and Option 2; Minimum
pull-in range and hold-in range must be ±4.6 ppm

PULL-IN AND HOLD-IN

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2 Wander Generation
The following MTIE and TDEV ECC option 1 and 2 tests measure the amount of wander generated by the
LMK5C33216. Figure 2-1 shows the setup used for these tests.
CALNEX 10 MHz to 25 MHz
Frequency Converter

10 MHzPORT 1CALNEX RB/GPS FREQ REFERENCECALNEX PARAGON-T
PORT 2SyncedCommunica on
LMK 24.576 MHz to 10 MHz
Frequency Converter

10 MHz24.576 MHz
Communica on
LMK5C33216

10 MHzHoldover OCXO
Reference
25 MHzFigure 2-1. Test Setup for Wander Generation

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2.1 Wander Generation MTIE Option 1, G.8262 EEC Option 1
While the DPLL is locked to an input clock that is wander-free, it will not generate wander that exceeds the green
MTIE masks shown in Figure 2-2 and Figure 2-3. These masks can be seen in Figure 1 in the G.8262
specification. There is no noise modulation applied to the input for this test. The LMK5C33216 passed the
Wander Generation MTIE Option 1, G.8262 EEC Option 1 requirement as shown in Figure 2-2 and Figure 2-3.

Figure 2-2. Wander Generation MTIE Option 1, G.8262 EEC Option 1 Results, Tested at Constant Room
Temperature With DPLL Bandwidth of 10 Hz

Figure 2-3. Wander Generation MTIE Option 1, G.8262 EEC Option 1 Results, Tested at Temperature of
85°C With DPLL Bandwidth of 10 Hz

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2.2 Wander Generation TDEV G.8262 EEC Option 1
While the DPLL is locked to an input clock signal that is wander-free, it will not generate wander that exceeds thegreen TDEV mask shown in Figure 2-4 (Figure 2 in the G.8262 specification). The LMK5C33216 passed the
Wander Generation TDEV G.8262 EEC Option 1 requirement as shown in Figure 2-4.

Figure 2-4. Wander Generation TDEV G.8262 EEC Option 1 Results, Tested at Constant Room
Temperature With DPLL Bandwidth of 10 Hz

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Wander Generation

2.3 Wander Generation MTIE Stratum ITU-T G.8262 EEC Option 2
While the DPLL is locked to an input clock signal that is wander-free, it will not generate wander that exceeds thegreen MTIE mask shown in Figure 2-5 (Figure 3 in the G.8262 specification). The LMK5C33216 passed the
Wander Generation MTIE Stratum ITU-T G.8262 EEC Option 2 requirement as shown in Figure 2-5.

Figure 2-5. Wander Generation MTIE ITU-T G.8262 EEC Option 2 Results, Tested at Constant Room
Temperature With DPLL Bandwidth of 0.1 Hz

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2.4 Wander Generation TDEV G.8262 EEC Option 2
While the DPLL is locked to an input clock signal that is wander-free, it will not generate wander that exceeds thegreen TDEV mask shown in Figure 2-6 (Figure 4 in the G.8262 specification). The LMK5C33216 passed the
Wander Generation TDEV G.8262 EEC Option 2 requirement as shown in Figure 2-6.

Figure 2-6. Wander Generation TDEV G.8262 EEC Option 2 Results, Tested at Constant Room
Temperature With DPLL Bandwidth of 0.1 Hz

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Wander Transfer

3 Wander Transfer
The following ECC option 1 and 2 tests measure the wander transfer of the LMK5C33216. Figure 3-1 shows the
setup used for these tests.
CALNEX 10 MHz to 25 MHz
Frequency Converter

10 MHzPORT 1CALNEX RB/GPS FREQ REFERENCECALNEX PARAGON-T
PORT 2SyncedCommunica on
LMK 24.576 MHz to 10 MHz
Frequency Converter

10 MHz24.576 MHz
Communica on
LMK5C33216

10 MHzHoldover OCXO
Reference
25 MHzFigure 3-1. Test Setup for Wander Transfer

3.1 Transfer Function of the PLL for Option 1 and Option 2
Wander transfer is determined by the DPLL loop BW and peaking. For Option 1, the DPLL loop bandwidth was
set to 10 Hz and for Option 2, the DPLL loop bandwidth was set to 0.1 Hz. Both Option 1 and Option 2 require <0.2 dB of peaking. The LMK5C33216 meets the requirements for the transfer function of the PLL for EEC Option
1 and Option 2 as shown in Figure 3-2 and Figure 3-3. The results show a close match between expectedbandwidth and measured bandwidth on LMK5C33216. For Option 1, the expected bandwidth is 10 Hz and themeasured bandwidth is around 10 Hz. For Option 2, the expected bandwidth is 0.1 Hz and the measured
bandwidth is around 0.1 Hz.

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Wander Transfer

Figure 3-2. Wander Transfer EEC Option 1 With Max DPLL Bandwidth of 10 Hz

Figure 3-3. Wander Transfer EEC Option 2 With Max DPLL Bandwidth of 0.1 Hz

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3.2 Wander Transfer TDEV G.8262 Option 2
The process for this specification is to measure the output wander (TDEV) when the device is locked to a clockthat has wander as defined by the TDEV mask shown in figure 8 in the G.8262 specification and Table 3-1(Table 10 in the G.8262 specification) and to ensure that the TDEV output is below the mask shown in figure 11
in the G.8262 specification. Results from Section 3.1 offer sufficient information regarding the bandwidth of the
DPLL to state that the LMK5C33216 meets the requirements for wander transfer TDEV G.8262 Option 2.
Table 3-1. Input Wander Tolerance (TDEV) for EEC-Option 2
TDEV LIMIT (ns)

OBSERVATION INTERVAL τ (s)17

0.1 < τ ≤ 3

5.77 × τ

3 < τ ≤ 30

31.6325 × τ0.5

30 < τ ≤ 1000

4 Wander Tolerance
The following ECC option 1 and 2 tests measure the wander tolerance of the LMK5C33216. Figure 4-1 shows
the same general setup used for these tests.
CALNEX 10 MHz to 25 MHz
Frequency Converter

10 MHzPORT 1
SyncedCALNEX RB/GPS FREQ REFERENCECALNEX PARAGON-T
PORT 2SyncedCommunica onz

LMK 24.576 MHz to 10 MHz
Frequency Converter

10 MHz24.576 MHz
Communica on
LMK5C33216
SMB10010 MHzHoldover
Reference

25 MHzFigure 4-1. Test Setup for Wander Tolerance

4.1 Wander Tolerance G.8262 Option 1
A PLL that is locked to an input clock must be able to tolerate the wander defined in figure 5 in the G.8262
specification. The definition of tolerance is such that the device will not trigger any alarms while locked to suchan input clock and it will be able to pull-in to such as an input clock. Test signals with a sinusoidal phase variation

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Wander Tolerance

can be used, according to the levels in Table 4-1 (Table 9 in the G.8262 specification), to check conformance tothe mask in figure 5 in the G.8262 specification.
Test signals with sinusoidal phase variation according to levels shown in Table 4-1 were introduced using theCalnex Paragon-T box. There were no amplitude, frequency, or missing clock cycle alarms flagged by the
LMK5C33216 DUT (10-Hz loop bandwidth). The device stayed locked and was able to pull-in to the input clock
throughout the duration of this test. The LMK5C33216 showed a passing result for the wander tolerance G.8262
Option 1 specification.
Table 4-1. Lower Limit of Maximum Tolerable Sinusoidal Input Wander for EEC-Option 1 (1)PEAK-TO-PEAK WANDER AMPLITUDE(1)

WANDER FREQUENCY

A1 (µs)A2 (µs)A3 (µs)f4 (mHz)f3 (mHz)f2 (mHz)f1 (Hz)f0 (Hz)

0.25

2

5

0.32

0.8

16

0.13

10

Table 4-1 shows the resultant requirements

4.2 Wander Tolerance G.8262 Option 2
A PLL that is locked to an input clock must be able to tolerate the wander defined in figure 8 in the G.8262
specification. The definition of tolerance is such that the device will not trigger any alarms while locked to suchan input clock and it will be able to pull-in to such as an input clock. Test signals with sinusoidal phase variationaccording to levels shown in Table 4-1 (Table 9 in the G.8262 specification) were introduced using the Calnex
Paragon-T box for this test, too. There were no amplitude, frequency, or missing clock cycle alarms flagged by
the LMK5C33216 DUT (0.1-Hz loop bandwidth), and the device stayed locked and was able to pull-in to the
input clock throughout the duration of this test. The LMK5C33216 showed a passing result for the wander
tolerance G.8262 Option 2 specification.

5 Jitter Tolerance
The following ECC option 1 and 2 tests measure the jitter tolerance of the LMK5C33216. Figure 5-1 shows the
setup used for these tests.

LMK5C33216
E4437B Signal Generator
Modulated
Reference
25 MHz
SMB10010 MHzHoldover
Reference

Agilent 5052B

Communica on

Figure 5-1. Test Setup for Jitter Tolerance

5.1 Jitter Tolerance G.8262 Option 1 and Option 2
A PLL that is locked to an input clock must be able to tolerate the jitter defined in figure 9 in the G.8262
specification and figure 10 in the G.8262 specification. The definition of tolerance is that the device will not
trigger any alarms while locked to such an input clock and that it will be able to pull-in to such an input clock. For
Option 1, LMK5C33216 DPLL loop bandwidth was set to 10 Hz. For Option 2, the DPLL loop bandwidth was set
to 0.1 Hz. For this test, the modulation frequency and frequency deviation was applied on the E4437B.
In compliance with the jitter tolerance specification requirement, the reference clock to LMK5C33216 (generatedusing E4437B) was modulated. The LMK5C33216 met the jitter tolerance requirements per the standard. The
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Jitter Tolerance

LMK5C33216 did not trigger any alarms, stayed locked to the reference and there was no observed degradation
to the integrated RMS (12 kHz to 20 MHz) phase jitter of the output clock (156.25 MHz). The integrated RMS
phase jitter was < 250 fs (max) for the duration for this test.
Table 5-1. 1G Synchronous Ethernet Wideband Jitter Tolerance for EEC-Option
1 & EEC-Option 2 (1)(1)

PEAK-TO-PEAK JITTER AMPLITUDE (UI)FREQUENCY f (Hz)312.5

10 < f ≤ 12.1

3750 f-1

12.1 < f ≤ 2.5k

1.5

2.5k < f ≤ 50k

1G includes 1000BASE-KX, -SX, -LX; multi-lane interfaces are for further study.

Table 5-2. 10G Synchronous Ethernet Wideband Jitter Tolerance for EECOption 1 andEEC-Option 2 (1)PEAK-TO-PEAK JITTER AMPLITUDE (UI)(1)

FREQUENCY f (Hz)2488

10 < f ≤ 12.1

3000 f-1

12.1 < f ≤ 20k

1.5

20k < f ≤ 40k

10G includes 10GBASE-SR/LR/ER, 10GBASE-LRM, 10GBASE-SW/LW/EW and multi-lane
interfaces consisting of 10G lanes including 40GBASE-KR4/CR4/SR4/LR4 and 100GBASE-CR10/
SR10.

Table 5-3. 25G Synchronous Ethernet Wideband Jitter Tolerance for EECOption 1 andEEC-Option 2 (1)(1)

PEAK-TO-PEAK JITTER AMPLITUDE (UI)FREQUENCY f (Hz)6445

10 < f ≤ 11.17

72000 f-1

11.17 < f ≤ 20k

3.6

20k < f ≤ 100k

25G includes multi-lane interfaces consisting of 25G lanes including 100GBASE-LR4/ER4.

Table 5-4. 1G Test Conditions
MOD FREQUENCY (Hz)PEAK-TO-PEAK PHASEAMPLITUDE (UI)

FREQ DEVIATION (kHz)

10

312.5

0.245

12.1

312.5

0.297

100

40

0.314

1000

4

0.314

2500

1.5

0.295

10000

1.5

1.178

50000

1.5

5.890

Table 5-5. 10G Test Conditions
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PEAK-TO-PEAK PHASEAMPLITUDE (UI)

FREQ DEVIATION (kHz)

10

2488

0.195

12.1

2488

0.236

100

300

0.236

1000

30

0.236

2500

12

0.236

20000

1.5

0.236

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Jitter Tolerance

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Table 5-5. 10G Test Conditions (continued)
MOD FREQUENCY (Hz)PEAK-TO-PEAK PHASEAMPLITUDE (UI)

40000

FREQ DEVIATION (kHz)

1.5

0.471

Table 5-6. 25G Test Conditions
MOD FREQUENCY (Hz)14

PEAK-TO-PEAK PHASEAMPLITUDE (UI)

FREQ DEVIATION (kHz)

10

6455

0.203

11.17

6455

0.227

100

720

0.226

1000

72

0.226

2500

28.8

0.226

20000

3.6

0.226

100000

3.6

1.131

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6 Phase Transient Generation
The following EEC option 1 and 2 tests measure the short-term phase transient of the LMK5C33216. Figure 6-1
shows the setup used for these tests.
CALNEX RB/GPS FREQ REFERENCE

Synced10 MHzPORT 1 CALNEX PARAGON-T
PORT 2SyncedCommunica on

10 MHzLMK 24.576 MHz to 10 MHz
Frequency Converter

LMK04806
24.576 MHz

25 M
CALNEX 10 MHz – MHz
Frequency ConverterHz
LMK5C33216
SMB100Hz
25 M

10 MHzHoldover
Reference

25 MHzCommunica on

Figure 6-1. Test Setup for Phase Transient Generation

6.1 Short-Term Phase Transient Response G.8262 Option 1
For this test, the device is forced into holdover for 15 seconds by performing a manual switch from a valid active
clock input (IN0) to another input with no valid signal (IN1), then the holdover state is exited by manuallyswitching back to the valid active clock input. The test is completed after an entry into holdover and exit fromholdover has taken place within 15 seconds. The output phase variation, relative to the input reference before it
was lost, is bounded by the following requirements.
The phase error must not exceed ∆t + 5 × 10-8 × S seconds over any period S up to 15 seconds. ∆t represents
two phase jumps that may occur during the transition into and out of holdover state which both must not exceed
120 ns with a temporary frequency offset of no more than 7.5 ppm. The resultant overall requirements issummarized in green in Figure 6-2 (Figure 12 in the G.8262 specification). This figure is intended to depict theworst-case phase movement attributable to an EEC reference clock switch.
The LMK5C33216 passed the requirements for short-term phase transient response. No significant phase hits
were observed during holdover entry and exit using LMK5C33216.

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Figure 6-2. Short-Term Phase Transient Result

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Phase Transient Generation

6.2 Short-Term Phase Transient Response G.8262 Option 2
For this test, the device is forced into holdover for 15 seconds by performing a manual switch from a valid active
clock input (IN0) to another input with no valid signal (IN1), then the holdover state is exited by manuallyswitching back to the valid active clock input. The test is completed after an entry into holdover and exit fromholdover has taken place within 15 seconds. The output will not exceed the green MTIE requirement shown in
Figure 6-3 (Figure 14 in the G.8262 specification).
The below MTIE data captures the phase transient at the output of LMK5C33216 during multiple reference clock
switchover events, displaying a passing result. The resolution of Calnex equipment is limited to 1 ns for MTIE.
The unique phase cancellation scheme implemented in LMK5C33216 allows for a phase transient < 100 ps
which cannot be measured accurately using this setup.

Figure 6-3. Short-Term Phase Transient Option 2

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6.3 Phase Transient Generation With Signal Interruptions G.8262 EEC Option 1
The passing condition for this specification is that an input interruption that does not force a switchover does notcause an output phase transient greater than 120 ns with a maximum frequency offset of 7.5 ppm in a period of
16 ms. For this setup, a pulse generator was inserted into the general setup as in Figure 6-4. An 8110A pulse
generator is used to generate a gapped clock and was set to generate 25 MHz with 1 pulse missing every 2048
clock cycles. This gapped clock was used as reference to LMK5C33216 and the LMK5C33216 output wasmonitored for phase transients.
The LMK5C33216 passed the requirements for the phase transient generation with signal interruptions G.8262
EEC Option 1. There were no significant phase hits (meets compliance requirements) during operation of thedevice while receiving a gapped clock as reference.
CALNEX RB/GPS FREQ REFERENCE

SyncedCALNEX PARAGON-T
PORT 2

Communica on
Synced10 MHzLMK 24.576 MHz to 10 MHz
Frequency Converter

24.576 MHz

LMK5C33216

8110A Pulse Generator

25 MHzGappedReference
Clock
Communica on

Figure 6-4. Test Setup for Phase Transient Generation With Signal Interruption

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Phase Transient Generation

Figure 6-5. Phase Transient With Signal Interruptions Results

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Phase Transient Generation

6.4 Phase Discontinuity G.8262 Option 1
Passing this test requires that switching between two input clocks of the same frequency but with different
phases does not cause an output phase transient greater than what is outlined in Section 11.4.1 of the G.8262
specification. The setup for this test (shown in Figure 6-6) is as follows:• There are two inputs that are 180 degrees out of phase going into the DUT• The output is measured to ensure that the objective is met
The TIE data for phase discontinuity during reference switchover G.8262 EEC Option 1 (shown in Figure 6-7)
indicates compliance to the standard.
CALNEX RB/GPS FREQ REFERENCE

SyncedPORT 1 CALNEX PARAGON-T
PORT 2

10 MHzCommunica on

10 MHzLMK 24.576 MHz to 10 MHz
Frequency Converter

LMK04806

24.576 MHzz
MH
25 s 180°k
Cloc f phaseoout Hz
25 M

CALNEX 10 MHz – MHz
Frequency Converter

LMK5C33216
SMB10010 MHzHoldover
Reference

25 MHzCommunica on

Figure 6-6. Test Setup for Phase Discontinuity

Figure 6-7. Phase Discontinuity Results

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Phase Transient Generation

6.5 Phase Discontinuity G.8262 Option 2
For this test, the requirement is that switching between two input clocks of the same frequency but with different
phase will not exceed the green MTIE mask shown in Figure 6-8 (Figure 14 and Table 15 in the G.8262 spec).
The LMK5C33216 met this requirement, as shown in Figure 6-8.

Figure 6-8. Phase Discontinuity Option 2 Results

7 Holdover
7.1 Holdover G.8262 Option 1
To meet this specification, a PLL in holdover must meet the requirements shown in figure 13 in the G.8262
specification. The procedure for this test is that the LMK5C33216 DUT will lock to IN0, which contains a valid
input clock. Then the input is switched to IN1, which contains no valid input, thereby causing the device to enter
holdover and remain in holdover for the remainder of the test. The LMK5C33216 device was set up in with a 10Hz loop bandwidth and forced into holdover. The LMK5C33216 met this specification. The TIE plot shown in
Figure 7-1 demonstrates compliance to the standard in green.

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Figure 7-1. Holdover Option 1 Result

7.2 Holdover G.8262 Option 2
To meet this specification, a PLL in holdover must meet the requirements in Table 7-1 (Table 15 in the G.8262
specification). The procedure for this test is that the DUT obtains lock from IN0, which contains a valid input
clock. Then the input is switched to IN1, which contains no valid input, thus entering holdover and remains inholdover for the remainder of the test. The LMK5C33216 met this specification. The TIE plot shown in Figure 7-2
demonstrates compliance to the standard in green.
Table 7-1. Transient Response Specifications During Holdover
EEC Option 2
S > TBD (6)Applies For(ns/s)(1)50

a 2 (ns/s)(2)300

b (ns/s2)(3)

4.63 × 10-4c (ns)(4)1000

d (ns/s2)(5)4.63 × 10-4

a1

(1)
(2)

(6)

a 1 represents an initial frequency offset under constant temperature conditions (±1 K)a 2 accounts for temperature variations after the clock went into holdover. If there are no temperature variations, the term a 2 S should
not contribute to the phase error.
b represents the average frequency drift caused by aging. This value is derived from typical aging characteristics after 60 days ofcontinuous operation. It is not intended to measure this value on a per day basis, as the temperature effect will dominate.
The phase offset c takes care of any additional phase shift that may arise during the transition at the entry of the holdover state.
d represents the maximum temporary frequency drift rate at constant temperature allowed during holdover. However, it is not requiredthat d and b be equal.
TBD: To be defined.

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ITU-T G.8262 Compliance Test Results for the LMK5C33216

(3)
(4)
(5)

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Free-Run Accuracy

Figure 7-2. Holdover Option 2 Result

8 Free-Run Accuracy
8.1 Free-Run Accuracy G.8262 Option 1 and Option 2
To meet this requirement, the free-run frequency will never exceed ±4.6 ppm with reference to a traceable
Stratum-1 reference. This includes initial power-up or wherever there is not sufficient holdover history
accumulated.
With the LMK5C33216 reference removed, the device was locked to the holdover reference upon power on
reset until holdover history was available. The holdover reference selected was within ±4.6 ppm. The output
clock from LMK5C33216 followed the holdover reference.

9 Pull-In and Hold-In
9.1 Pull-In Range G.8262 Option 1 and Option 2
To meet this requirement, a PLL which is in free-run or holdover within its ±4.6 ppm frequency range (based on
its TCXO/OCXO) must be able to pull-in to a reference that is within ±4.6 ppm frequency (traceable toStratum-1). In other words, the PLL should be able to pull-in a minimum of ±9.2 ppm and no alarms should beasserted during this process. Hold-in range is defined as the largest offset between the reference frequency of aslave clock and a specified nominal frequency, within which the slave clock maintains lock as the frequency
varies over the frequency range. The hold-in range for EEC-Option 2 should be ±4.6 ppm, whatever the internal
oscillator frequency offset may be. The minimum pull-in range for Option 1 and Option 2 should be ±4.6 ppm,
whatever the internal oscillator frequency offset may be.
The LMK5C33216 meets the specification for pull-in and hold-in range as shown in Table 9-1 and Table 9-2.
Table 9-1. Pull-In Results
REFERENCE TO DPLLTCXOOUTPUT

NOTES

25 MHz - 4.6 ppm

10 MHz + 4.6 ppm

10 MHz - 4.6 ppm

25 MHz - 4.6 ppm

10 MHz - 4.6 ppm

10 MHz - 4.6 ppm

Lock from POR with FASTLOCK
Enabled

25 MHz + 4.6 ppm

10 MHz + 4.6 ppm

10 MHz + 4.6 ppm

25 MHz + 4.6 ppm

10 MHz - 4.6 ppm

10 MHz + 4.6 ppm

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Table 9-2. Hold-In Results
REFERENCE TO DPLLTCXOOUTPUT

NOTES

25 MHz - 4.6 ppm

10 MHz ± 4.6 ppm

10 MHz - 4.6 ppm

25 MHz + 4.6 ppm

10 MHz ± 4.6 ppm

10 MHz + 4.6 ppm

25 MHz ± 4.6 ppm

10 MHz - 4.6 ppm

10 MHz ± 4.6 ppm'±' here refers to reference
frequency (TCXO or Reference toDPLL) being swept from '-' to '+'and vice-versa

25 MHz ± 4.6 ppm

10 MHz + 4.6 ppm

10 MHz ± 4.6 ppm

10 Conclusion
The LMK5C33216 Network Synchronizer device, along with a compliant TCXO or OCXO, meets or exceeds therequirement set in ITU-T G.8262/Y.1362 (07/2010) and Amendment 2 (10/2012).
Notable features of this high performance device includes:• Hitless Switching with minimal phase transients (< 100 ps)• Ultra High-Performance VCO allows use of a low-cost holdover reference without sacrificing performance• High-Performance DPLL Channel with Programmable loop bandwidth for jitter and wander filtering suitable
for EEC Option 1 and EEC Option 2• Reference Priority Selection, Gapped Clock and Runt Pulse Detectors, Automatic/Manual Switchover,Holdover, and Tuning Word History

11 References
For reference, see the following:• ITU-T G.8262 Standard

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