MNC Abstract Sample, Copyright since 2005
by the Japan Science of Applied Physics

Effect of fabrication process on hysteresisy of carbon nanotube FETs
H. Shimauchi1, Y. Ohno1,2, S. Kishimoto1, and T. Mizutani1
Dept. of Quantum Eng., Nagoya Univ., Furo-cho, Chikusa-ku, Nagoya 464-8603, Japan
2
PRESTO/JST, 4-1-8 Honcho Kawaguchi, Saitama 332-0012, Japan
Phone: +81-52-789-5387, Fax: +81-52-789-5232, E-mail: yohno@nuee.nagoya-u.ac.jp

1

1.

INTRODUTION
Carbon nanotube field-effect transistors (CNTFETs) have great advantages over the conventional Si
MOS FETs because of their high transconductance and large current driving capability. However,
CNTFETs exhibit a large hysteresis in the ID-VGS characteristics. W. Kim et al. have reported that the watermolecules on the device surface are the origin of the large hysteresis, which can be suppressed by surface
passivation using PMMA [1]. In our experiments, however, the reproducibility was quite poor. In this study,
we have statistically studied the hysteresis and the passivation process. The reproducibility of thepassivation has been improved by introducing cleaning process before the PMMA passivation.

2.

EXPERIMENTS
Figure 1 shows a schematic device structure of the fabricated nanotube FETs [2]. The SWNTs weregrown directly on the Si wafer by alcohol catalytic chemical vapor deposition [3]. The present passivation
process consists of two steps; a surface coating with PMMA (~2 Pm) followed by baking at 180qC for 24 h,
and a subsequent SiO2 (100 nm) cover layer deposition on the PMMA. This cover layer was introduced tosecure long-term stability of the passivation. Figure 2 shows the ID as a function of the VGS of theSiO2/PMMA-passivated device. Here, the VDS was -0.1 V. This device exhibited negligible hysteresis in theambient atmosphere. The hysteresis has been suppressed at least for a month. However, the effect of thepassivation on the hysteresis depends on devices. In the present case, the passivation was effective only for
one device, and did not work for most devices as shown in the histogram of Fig. 3(a).
We have found that the poor reproducibility is related to the device fabrication process, as it will bediscussed below. Figure 4(a) shows the variation of hysteresis by baking in vacuum (200qC, 1u10-3 Pa) for
two batches, with and without the process to form the source and drain electrodes. In the latter case, thecatalysts were used as the source and drain electrodes. The hysteresis decreased with baking time for bothbatches. This is because of the desorption of water molecules near the nanotube. Figure 4(b) is acomparison of the hysreresis between two batches after baking for 96 h. It should be noted that thehysteresis voltage width and the dispersion of the batch without the contact formation process is muchsmaller than those of the batch with the process. This shows that the hysteresis is related to the contact
formation process. The most plausible factor impeding the decrease in the hysteresis is the scum of thephotoresist.
In order to remove the scum of the photoresist, we introduced the cleaning process using H2SO4:H2O2(4:1) before the SiO2/PMMA passivation process. Figure 3(b) shows histogram of the hysteresis voltage
width of the devices with the cleaning process. In this case, the hysteresis was reduced for most devices bythe passivation. The long-term stability was also confirmed.

3.

SUMMARY
We have shown that the hysteresis of nanotube FETs is related to the fabrication process usingphotoresist. By introducing cleaning process before the passivation, the reproducibility of the passivation
was drastically improved. Long-term stability of the passivation was secured by a SiO2 cover layer on thePMMA passivation film.

REFERENCES[1] W. Kim, A. Javey, O.Vermesh, Q.Wang, Y. Li. and H. Dai, Nano Lett. 3, 193 (2003).
[2] Y. Ohno, S. Iwatsuki, T. Hiraoka, T. Okazaki, S. Kishimoto, K, Maezawa, S. Shinohara, and T.
Mizutani, Jpn. Appl. Phys. 42, 4116 (2003).
[3]Y. Murakami, Y. Miyauchi, S. Chiashi, and S. Maruyama, Chem. Phys. Lett. 374, 53 (2003).

MNC Abstract Sample, Copyright since 2005
by the Japan Science of Applied Physics
0.06

PMMADrain-ID (PA)

SourceVDS = -0.1 V

0.05

SiO2Cat.

SiO2p+-Si Sub.

0.04
0.03
0.02
0.01

Back Gate

0-10

Fig.1 Schematic structure of carbon nanotube FETs.

-50VGS5Fig. 2 ID-VGS characteristics
SiO2/PMMA-passivated device.
(a)

of(b)

10
Before passivation

w/o cleaning

After passivation
Number of devices

8
Number of devices

10(V)

642

14

Before passivation

12

After passivation

with cleaning

10864
2

000 1 2 3 4 5 6 7 8 9 10 11 12Hysteresis voltage width (V)01

2 3 4 5 6 7 8 9 10Hysteresis voltage width (V)Fig. 3 Histogram of the hysteresis voltage width of the devices with
SiO2/PMMA passivation; (a) without cleaning process, and (b) withcleaning process.

(b)8with contact process
w/o contact process

76

Number of devices

Hysteresis voltage width (V)(a)

5432with contact process
w/o contact process

201510510-20250204060

Baking time (h)801000012345Hysteresis voltage width (V)Fig. 4 Effect of process to form contact electrodes. (a) Variation of hysteresisby baking in vacuum for batches with and without process. (b) Comparisionof hysteresis voltage width between two batches with and without process
after baking for 96 h.