ISSUE 2, 2023

How the ADC noise figure
impacts RF receiver designs
Comparing dual-supply
discrete and integrated
instrumentation amplifiers
Optimize your application witha Power Path battery charger
Powering precision
ADCs: Average versus
transient current

Table of contents

02
06

Comparing dual-supply discrete andintegrated instrumentation amplifiersThis article compares three dual-supply
instrumentation amplifier (IA) circuits: a discrete IA
using a quad operational amplifier (op amp), a
general-purpose IA with an integrated gain-setting
resistor (RG) and a precision IA with an external RG.

your application with
12 Optimizea Power Path battery charger

How the ADC noise figure impacts
RF receiver designs
In an effort to build smaller digital receivers, the aerospace anddefense industry is embracing modern direct radio-frequency(RF) sampling analog-to-digital converters (ADCs). These ADCs
eliminate RF mixing stages and are closer to the antenna,
simplifying digital receiver designs while also saving costand printed circuit board (PCB) area. One critical (and often
misunderstood) parameter is the ADC noise figure, which sets
the amount of RF gain to detect very small signals. This article
explains how to calculate the noise figure of an RF-sampling
ADC, and illustrate how the ADC noise figure affects RF signal
chain designs.

precision ADCs:
17 Powering
Average versus transient current
In this article, we delve into the topic of ADC
transient current demand by first introducing how
the device data sheet specifies current, and thensharing the results of several tests that quantify
transient current demand under different operating
conditions. Multiple power-supply configurations
that can source both average and transient currents
are discussed, and finally we consider the effects ofvarious power-down methods.

Designing an application with a battery charging
integrated circuit (IC) with Power Path helps
prevent issues by disconnecting the system fromthe battery to conserve power. It also optimizes therelationship between the power for the system andthe power to charge the battery in order to improvethe effective capacity of the battery. Using a battery
charging product with Power Path helps provide
lower quiescent current modes to enable thelongest battery runtime and minimize battery
fatigue. The following article delves deeper into thetechnical details behind these benefits and explains
how these benefits can help optimize yourapplication.
ISSUE 2, 2023

Analog Design Journal

How the ADC noise figure impacts RF
receiver designs
Thomas Neu
System Engineer

Introduction

Why the noise figure matters in digital receiver
designs

In an effort to build smaller digital receivers, theaerospace and defense industry is embracing modern

The digital receiver operates in one of two distinct

direct radio-frequency (RF) sampling analog-to-digital

scenarios as illustrated in Figure 1. In the blocking

converters (ADCs). These ADCs eliminate RF mixing

condition, an interferer or jammer is present and thestages and are closer to the antenna, simplifying digital

receiver has to operate with reduced RF gain in order

receiver designs while also saving cost and printed

not to saturate the ADC. In this setup, the ADC iscircuit board (PCB) area.

driven close to full scale by the interferer; thus, thelarge-signal signal-to-noise ratio (SNR) of the ADC

One critical (and often misunderstood) parameter is thedetermines how weak a signal can be detected. There

ADC noise figure, which sets the amount of RF gain

are additional degrading mechanisms such as phase

to detect very small signals. This article explains how

noise and spurious free dynamic range.

to calculate the noise figure of an RF-sampling ADC,
and illustrate how the ADC noise figure affects RF signal-

In the second scenario, there is no interferer present.

chain designs.

Detecting the weakest signal possible is solely
dependent on the inherent noise floor of the receiver, acondition typically measured as receiver sensitivity. The
noise figure measures the SNR degradation caused bycomponents in the receiver signal chain.
Blocking Scenario

Receiver Sensitivity
FullscaleHead Room

JammerFullscale

Weak desired signal

Receiver SFDR
Receiver Noise Floor
ADC Noise Floor

Receiver Noise Floor
ADC Noise Floor

Figure 1. Comparison between blocking or jamming and receiver sensitivity scenarios.

How the ADC noise figure impacts RF receiver designs

2

ISSUE 2, 2023

Analog Design Journal
The noise figure of the ADC is typically the weakest

LNA1

LNA2

ADC

link of the receiver (approximately 25 to 30 dB), while
low-noise amplifiers (LNAs) have noise figures as low

F1
G1

F2
G2

F3
G3

as <1 dB. It is possible, however, to improve the ADC
noise figure by adding gain to the analog RF front

Figure 2. Typical receive signal chain.

end (close to the antenna) using LNAs. The difference
between a 1-dB receiver system noise figure and a 2-dB

There are two important things to highlight: the system

receiver system noise figure translates to approximately

noise figure is primarily dominated by the noise figure F1

20%. This difference means that a receiver with a 1-dBof the first element, as long as gain G1 and G2 are large

noise figure can detect signals with approximately 20%

enough to where the ADC noise figure F3 is negligible.

weaker amplitude. In a software-defined radio (SDR), that

Comparing two different ADCs with 20-dB vs. 25-dB

translates to radios with reduced output power – saving

noise figures in a system with two cascaded LNAs showsbattery life – while in radar, that makes it possible toa drastic difference in system noise figures (see Table 1).

cover a longer distance.

LNA1

LNA2

ADC1

ADC2

1 dB

3 dB

20 dB

25 dB

12 dB

15 dB

0 dB

0 dB

1.8 dB

2.9 dB

Modern receiver designs in SDRs or digital radars use

Noise figure

direct RF-sampling ADCs in order to reduce size, weightGainand power. This architecture simplifies receiver designs

Resulting system noise figure

by eliminating the RF downconversion mixing stage. The

Table 1. System noise figure with two LNA stages.

better the ADC noise figure, the less gain required, which
results in additional savings. Furthermore, using lessGetting the system listed in the ADC2 column (with aadditional RF gain means that when a jammer is present,

5-dB worse noise figure) to a system noise figure below

there is less gain to reduce, with a higher dynamic range

2 dB would require an additional 10 dB of gain using amaintained in the receiver.

third LNA (noise figure = 3 dB), as shown in Table 2.
Table 2 highlights the impact of the ADC noise

Calculating a system’s noise figure

figure on the overall system noise figure. Adding

You can use the Friis equation to calculate a receivera third LNA increases cost, board area (matchingsystem’s noise figure. Assuming a simplified, ideal

components, routing and power supply) and system

receiver with two amplifiers and one ADC, as shown in

power consumption, and further reduces the full-scale

Figure 2, Equation 1 calculates the cascaded system

headroom.

noise factor as:
F −1
F −1
F −1
FSystem = F1 + 2G
+ G3 ∙ G + … + G ∙ G n… ∙ G
1

1

2

1

2

n−1

(1)

LNA1

LNA2

LNA3

ADC2

Noise figure

1 dB

3 dB

3 dB

25 dB

Gain

12 dB

15 dB

10 dB

Resulting system noise figure

where Fx are the noise factors and Gx are the power

0 dB
1.4 dB

Table 2. System noise figure using ADC2 with three LNA stages.

gains.

Assuming a target receiver sensitivity of –172 dBm, or

The system noise figure in decibels is:very weak signals just 2 dB above the absolute noise
NFSystem = 10 log FSystem(2)floor (–174 dBm + 2 dB = –172 dBm), this receiver
requires an noise figure better than 2 dB. Let’s use theabove example with ADC1 (with a 20-dB noise figure, as

How the ADC noise figure impacts RF receiver designs

3

ISSUE 2, 2023

Analog Design Journal
listed in Table 1) and a cascaded system noise figure of

Finally, the noise contribution of ADC1 (noise figure =1.8 dB.

20 dB) reduces to just 0.6 dB, as it gets reduced by
the 27-dB gain of both LNAs. Therefore, you end up

As shown in Figure 3 and Table 3, LNA1 with a gain of 12with a system noise figure of 1.8 dB, which leaves

dB raises both the input signal and noise by 12 dB while

approximately 0.2 dB of headroom to detect weak input

degrading the noise figure by 1 dB (noise figureLNA1 = 1

signals.

dB). LNA2 raises both signal and noise by 15 dB. Even
though LNA2 has a higher inherent noise Figure 3 dB, its
impact is reduced to just 0.2 dB because of the 12-dB

Absolute Noise (dBm)gain of LNA1.
LNA1

LNA2

ADC

F1 = 1 dB
G1 = 12 dB

F2 = 3 dB
G2 = 15 dB

F2 = 20 dB
G2 = 0 dB

1.2 dB

1.8 dBADC Noise Floor
ADC Noise Floor
15 dB
Weak Input
Signal

1 dB

20 dB
12 dB
2 dB

Figure 3. Graphical illustration of the individual noise figure contributions in a receive signal chain.
LNA1

LNA2

ADC

High-speed data converters rarely list noise figure in the

Noise figure (dB)

1

3

20

device-specific data sheet. The noise figure for an ADC

Gain (dB)

12

15

0

Noise power(linear)10^(noise
figure/10)

1.26
101/102
103/10100
10100/10

can be calculated using Equation 3 using the common

Power gain(linear)
10^(gain/10)

15.85
1012/1031.62
1015/101
100/10Noise figure of
LNA1 only (dB)

1

–

–

Noise figure of
LNA1 + LNA2
only (dB)
Noise figure of
LNA1 + LNA2 +ADC (dB)
Additional
impact on
system noise
figure (dB)data-sheet parameters (see Table 4) for the ADC32RF54
RF-sampling ADC.

1.2
10log[1.26+(2-1)/15.85]

1

0.2

0.6

Description

V

Input full-scale voltage
peak to peak (Vpp)

RIN

Input termination
impedance (Ω)

100 Ω

FS

ADC sampling rate

2.6 GSPSSNR

ADC SNR for smallinput signals (dBFS),
typically –20 dBFS

1.1

1.35

64.4

67.1

Table 4. Data sheet parameters of the ADC32RF54.

Table 3. Calculations for individual noise figure contributions.

How the ADC noise figure impacts RF receiver designs

Parameter–

1.810log[1.26 + (2-1)/15.85 + (100-1)/15.85/31.62]

ADC32RF54ADC32RF54(2 times(1 times AVG)
AVG)

ADC Noise figure (dB) = PSIG,dBm + 174 dBm – SNR(dBFS) – bandwidth (Hz)4

ISSUE 2, 2023

Analog Design Journal

NFADC dB = 10log− 10log FS
2

2
V
2× 2
× 1000RIN+ 174 − SNR (3)For the ADC32RF54, the noise figure calculates to:
Noise figure (1x AVG) = 20.3 dB
10log[(1.1/2/sqrt(2))2/100 x 1000] +174 – 64.4 –10log[2.6e9/2]
Noise figure (2x AVG) = 19.3 dB
10log[(1.35/2/sqrt(2))2/100 x 1000] +174 – 67.1 –10log[2.6e9/2]

Conclusion
The receiver noise figure is an important system design
parameter because it determines the weakest detectablesignal. In addition to a very low inherent noise figure,
the ADC32RF54 also provides a high SNR, which allows
the system to maintain its noise figure even with a largerinput power signal. An ADC with same noise figure but
a lower SNR would require a reduction in the input gainto prevent saturation, in which case the ADC noise figure
starts adding more to the overall noise.

Important Notice: The products and services of Texas Instruments Incorporated and its subsidiaries described herein are sold subject to TI’s standard
terms and conditions of sale. Customers are advised to obtain the most current and complete information about TI products and services before
placing orders. TI assumes no liability for applications assistance, customer’s applications or product designs, software performance, or infringementof patents. The publication of information regarding any other company’s products or services does not constitute TI’s approval, warranty or
endorsement thereof.
All trademarks are the property of their respective owners.
© 2023 Texas Instruments Incorporated

SLYT839

Analog Design Journal

Comparing dual-supply discrete andintegrated instrumentation amplifiersPeter Semig
Applications Manager
Jacob Nogaj
Applications Engineer
Jerry Madalvanos
Applications Engineer
14

1
R

R
–
A

The advantages and disadvantages of designingRG

a discrete instrumentation amplifier (IA) versus an

3

13
12

D

+

VIN–

+

2

–

IntroductionR

TLV9064

V+

4

VIN+

5

+

6

–

11

V–
VREF

R
B

integrated IA are numerous and often debated. Some

R

10

–

9

C
R

R
7

of the variables to consider include printed circuit board

+

8
VOUT

(PCB) area, gain range, performance (over temperature)
Figure 1. A discrete dual-supply IA using a quad op amp.

and cost. The purpose of this article is to compare
three dual-supply IA circuits: a discrete IA using a quad

Equation 1 gives the transfer function for this circuit:

operational amplifier (op amp), a general-purpose IA withan integrated gain-setting resistor (RG) and a precision IA

VOUT = VIN + − VIN − × 1 + 20R kΩ

(1)Gwith an external RG.

Designers will typically select a discrete IA when PCB

Dual-supply circuits

area and performance are secondary to cost and gain

Figure 1 is a simplified schematic of a discrete, dual-

range. TI’s TLV9064IRUCR op amp was selected for this

supply IA using the Texas Instruments (TI) TLV9064 quadcomparison because it is a rail-to-rail input/output device

op-amp circuit. In this circuit, three of the four amplifier(RRIO) with a wide bandwidth (10 MHz) and a low typicalchannels (A, B and C) are connected as a traditional

initial input offset voltage (VOS(typ) = 300 µV), and comes

three-op-amp IA. The reference voltage (VREF) connects

in a small package (RUC = X2QFN = 4 mm2). While there

to ground. With no use for the fourth channel, D, it isare less expensive RRIO quad op amps in RUC/X2QFN

therefore connected as a buffer to mid-supply (ground)packages, they come at the expense of bandwidth andthrough a resistor for transient robustness. All resistors

typical offset voltage.

labeled “R” have a value of 10 kΩ; RG sets the differential

To be consistent with the design priorities of discrete IAs,

gain. The differential input voltage is VIN+ − VIN– and theinexpensive ±1% tolerance, ±100-ppm/°C drift resistors

output voltage is VOUT. Some components, such as thewere installed. Not only do these resistors differ in initialload resistor (10 kΩ) and decoupling capacitors, are notvalue, they will likely drift significantly over temperature.

shown. Drawing all circuits from a package perspective

Since RG is external, the gain for this configuration is

illustrates the number of external discrete components.

primarily limited by the input offset voltage of the op
amps.

Comparing dual-supply discrete and integrated instrumentation amplifiers

6

ISSUE 2, 2023

Analog Design Journal
Figure 2 is a simplified schematic of the TI INA350ABS,

Figure 3 is a simplified schematic of the TI INA333

a general-purpose dual-supply IA with an integrated

precision dual-supply IA with an external RG. VREF

RG. VREF connects to ground. This circuit integrates

connects to ground. In this circuit, the IA integrates

all resistors in the IA. The differential input voltage

all resistors except RG. The differential input voltage

is VIN+ − VIN– and the output voltage is VOUT. Someis VIN+ − VIN– and the output voltage is VOUT. Some

components, such as the load resistor (10 kΩ) andcomponents, such as the load resistor (10 kΩ) anddecoupling capacitors, are not shown. The gain of the IA

decoupling capacitors, are not shown.

is set based on the switch connected to pin 1 (open = 20

RG

V/V, closed = 10 V/V). In an actual application, the switch
would not be present. To enable the device, connect pin

50 k

8 (SHDN) to V+ or leave it floating.

–
SHDN

INA333–VIN+

RG

150 k

150 k

VREF
5

–
6

VOUT

+

–

V–
+

4

4

90 k

VIN+
3

V–

VOUT
6

+

3

V+

90 k

50 k

+

60 k
7

V+
7

–

60 k

–

2

8

INA350ABS+

150 k

+1

150 k

VIN–
2

VIN–

8

1

60 k

60 k

Figure 3. Precision dual-supply IA with an external RG.

VREF
5Equation 3 gives the transfer function for this circuit:
Figure 2. General-purpose dual-supply IA with an integrated RG.
kΩ
VOUT = VIN + − VIN − × 1 + 100
R

Equation 2 gives the transfer function for this circuit:V
VOUT = VIN + − VIN − × 10 V
V or 20 V(3)GDesigners typically use a precision IA when performance(2)is the highest priority. The INA333AIDRGR precision

Designers will typically select this IA when their

IA was selected for this comparison because it is low

requirements necessitate a balance of cost, performance

voltage (5 V), has excellent precision (G = 1 V/V, VOS(typ)and PCB area. The INA350ABSIDSGR IA was chosen for= 35 µV) and comes in a small package (DRG = WSON

this comparison because of its affordability, performance,= 9 mm2). The performance over temperature depends

small package (lead DSG = WSON = 4 mm2), selectableon the selection of the external RG. Therefore, to begain (10 V/V or 20 V/V) and low typical input offset

consistent with the primary design priority – performance

voltage (VOS(typ) = 200 µV). This implementation needs– we used a precision RG for a gain of 10 V/V

no external components. For designs that require higher(±0.05%, ±10 ppm/°C). Because the precision op amps

gains, the INA350CDS has gains of 30 V/V or 50 V/V.

are integrated, this implementation has excellent gain
range (1 V/V to 1,000 V/V). The overall cost is usually
greater than the other two solutions, however, given the
integrated precision op amps and required precision RG.

Comparing dual-supply discrete and integrated instrumentation amplifiers

7

ISSUE 2, 2023

Analog Design Journal

PCB layout
A PCB specifically designed for this comparison, containing the three circuits outlined above in a circular region, uponwhich the nozzle of a temperature forcing unit would fit. Care was taken to present the same input signal to each circuit,alleviating any concern for “leakage.” Each output was routed separately to ensure isolation.
Figure 4 shows a simplified layout of each IA circuit to compare the relative sizes of each solution, including decoupling
capacitors. For comparison purposes, the smallest device packages were used, along with resistors and capacitors in
the 0402 package.

Figure 4. Simplified PCB layout comparison for dual-supply IA circuits.

As you can see, the discrete IA implementation is significantly larger than the two integrated solutions. And with the
integrated RG and overall smaller die size, the general-purpose IA layout is almost half the size of the precision IA layout.

Measurement results
Gain and offset errors were used as a measure of the relative performance of each circuit across temperature. As abaseline measurement, the precision dual-supply IA was put in a gain of 1 V/V (RG = open). For each sweep, the input
signals were scaled such that the output voltage ranged from –2 V to +2 V.
Table 1 depicts the baseline gain and offset errors for the precision IA, G = 1 V/V across temperature. The table includes
the data sheet’s typical gain and offset error values at 25°C, to validate the measurement system.
Temperature

–40°C

0°C

25°C

100°C

125°C

Error TypeGain

OffsetGain

OffsetGain

OffsetGain

OffsetGain

OffsetMeasured(data sheet
typical)0.00270%

10.1 µV

0.00019%

9.1 µV–0.00281%(±0.01%)

7.5 µV(±35 µV)–0.00523%

23.5 µV–0.00572%

31.2 µV

Table 1. Precision IA gain and offset error vs. temperature (G = 1 V/V).

Comparing dual-supply discrete and integrated instrumentation amplifiers

8

ISSUE 2, 2023

Analog Design Journal
Table 2 depicts the gain and offset error (referred-to-output [RTO]) for all IAs in a gain of 10 V/V and across temperature.
The green shading indicates the highest-performing implementation at each temperature.
Temperatur
e

–40°C

0°C

25°C

100°C

125°C

Error TypeGain

OffsetGain

OffsetGain

OffsetGain

OffsetGain

OffsetDiscrete IA–0.60853%–4.09 mV

–0.70079%–3.67 mV

–0.73929%–4.07 mV

–0.90846%–4.07 mV

–0.95486%–3.69 mV

Generalpurpose IA–0.02532%

2.07 mV–0.03182%

2.05 mV–0.00250%

2.04 mV

0.00876%

2.12 mV–0.00970%

2.21 mV

Precision IA

0.17320%–58.8 µV

0.08103%–43.2 µV

0.02941%–35.2 µV

–0.06125%–2.2 µV–0.07883%

33.8 µV

Table 2. Gain and offset error (RTO) vs. temperature (Gain = 10 V/V).

From a performance perspective, Table 1 and Table 2 show that without an external RG, the precision dual-supply
IA is superior to all other solutions. From a gain error perspective, the general-purpose and precision IA solutions arecomparable. This is primarily because of the external RG required for the G = 10 V/V precision IA implementation,
whereas the general-purpose solution integrates RG. When looking at the offset error, the precision IA solution is clearly
the most accurate, while the general-purpose offset error is about half that of the discrete solution. Overall, the discrete
IA has significantly worse performance when compared to both integrated solutions.

Conclusion
While many designers typically implement a discrete solution in low-cost applications, new general-purpose IAs (TI’s
INA350, for example) will likely yield lower overall cost and better performance. Depending on the gain, precision IAs
such as the INA333 can offer superior performance and gain range, although the external RG is an important factor in
performance, especially over temperature.
Table 3 summarizes the comparison.
PCB Area

Gain Range

Performance

Cost

Discrete IA

48.78 mm2

1 V/V to @100 V/V

Good

$$

General-purpose IA

16.79 mm2

10, 20, 30, 50 V/V

Better$Precision IA

29.7 mm2

1 V/V to 1,000 V/V

Best

$$$$

Table 3. Comparison of dual-supply IA circuit solutions.

The next time you are designing a dual-supply IA, weigh the trade-offs outlined in this article. For applications
that require the greatest accuracy, precision IAs are the obvious choice. For applications that require cost-effective
performance, the choice is no longer as easy as building a discrete IA. New general-purpose IAs can provide significantly
better performance than discrete solutions, while taking up less PCB area and lowering system costs at the same time.

Important Notice: The products and services of Texas Instruments Incorporated and its subsidiaries described herein are sold subject to TI’s standard
terms and conditions of sale. Customers are advised to obtain the most current and complete information about TI products and services before
placing orders. TI assumes no liability for applications assistance, customer’s applications or product designs, software performance, or infringementof patents. The publication of information regarding any other company’s products or services does not constitute TI’s approval, warranty or
endorsement thereof.
All trademarks are the property of their respective owners.
© 2023 Texas Instruments Incorporated

SLYT840

Analog Design Journal

Power

Optimize your application with a power
path battery charger
Charles Harthan
Product Marketing Engineer
to provide small current into the battery, ensuring that the

Introduction

system is still getting the required power to turn on.

With so many options for batteries and differing

When there is high demand for system current while

system requirements, it can be challenging to design

charging the battery, the Q2 MOSFET can also turn on to

the best battery charging integrated circuit (IC) to

combine power from the input and the battery to support

maximize battery lifetime and enable optimum system

the system load. This feature is known as supplement

performance. The decision to choose a power path ormode, where the device will pull current from the battery

non-power path battery charger can have a big impact

to supplement the current from the input in case theon the functionality of your charging IC.

system is pulling more current than what the input canFigure 1 shows non-power path devices have one path

provide. A typical application that would benefit fromfor charging, in which the system and battery connect topower path charger features would be a smartphone.

the same node. This makes non-power path charging an

The following sections show how power path topology

effective option when you do not need to use the system

improves system performance and battery life.

and charge the battery at the same time, since you
cannot control how much current is devoted to powering

Maximizing shelf life

the system vs. charging the battery. Applications such

A product can be in transit and on the shelf for months

as shavers or electric bikes are a good fit for non-power

before its purchase by a consumer, who typically prefers

path chargers.

to use the product right out of the box. With somecountries adopting new shipping restrictions that restrict

System and Battery power

System and Battery power

5-V USB

System

5-V USB

Charging

Systembatteries to only a certain amount of charge before

Charging
Supplemental modethey’re shipped, it is crucial to conserve every bit of

Systembattery capacity.

Battery

Figure 1. Non-power path and power path block diagrams.

In a non-power path topology, the system has toPower path charging is a better option for products

go into a low-power mode, as the system connects

when both charging and use can occur simultaneously,

directly to the battery. Low-power mode often imposessince the integrated Q2 metal-oxide semiconductor field-

requirements for a load switch or some other way toeffect transistor (MOSFET) in the battery allows you toisolate the battery from the system.

customize the amount of current devoted to powering

In the power path topology, the battery FET can

the system vs. charging the battery. This customization is

disconnect the battery from the system in ship mode

also useful when a battery is deeply discharged. Because– that is the state in which the product is consuming

deeply discharged batteries are often charged withthe lowest battery current. Ship mode also prevents thesmall currents, a power path device can independently

battery from powering the system by shutting off theregulate the system and battery current from the adapter

Optimize your application with a power path battery charger

battery FET. Designing your charging IC with power path

12

ISSUE 2, 2023

Analog Design JournalPowerand ship mode can enable instant turnon right out of themonitoring at low values by measuring the current

box when the consumer plugs in the adapter or presses

passing through the Q2 battery FET.

the power button.

Performing a watchdog reset
In some scenarios, when the system processor or hostis nonresponsive, a forced hardware reset or a power
cycle might be necessary; you can accomplish this witha watchdog reset. For instance, on TI’s BQ25180 charger
device, a hardware reset is possible when meeting
conditions such as:• No I2C communication for 15 s or more after plugging
Figure 2. Extra capacity from a lower ITERM.

in the adapter.
• The user pressed the reset button for an extended

Figure 2 also highlights how inaccurate ITERM monitoring

period of time.

can lead to termination at 4 mA instead of 1 mA, which• A duration >40 s from the last I2C communication.

means that the user would lose 5% of the available 41-

During a hardware reset sequence, the charger IC

mAhr battery capacity. Because a power path charger
regulates charging and system currents separately, any

disconnects the system from the battery and adapter

variations in system current will have no effect on the(if present), waits for a configurable duration, and thencharging current. Charge termination can thus occur

turns the system back on, enabling system startup

at a consistent pre-determined value, maximizing theand initialization. Because the battery is physicallyconnected to the system, an external load switch might

battery’s state of charge.

be necessary in a non-power path charger device toUsing power path to enable accurate, low ITERM is

perform a hardware reset.

analogous to filling up a cup of water from a faucet. In
the analogy, the cup is the battery, the water in the cup is

Employing the full battery capacity

the charge in the battery, and the water coming from theGetting the most battery capacity is a primary goal

faucet is the charge current. The goal is to fill up the cup

when designing a charger IC, since it translates to moreas much as possible without the water overflowing. It istime between charging for users. Inaccurate terminationmuch easier to do so by slowly decreasing the flow ofcurrent (ITERM) monitoring can lead to charge terminationwater coming from the faucet as the water gets closer to

at values higher than the desired ITERM value and preventthe top, so that you can easily control the water level.

use of the full battery capacity, as shown in Figure 2.

Allowing the fastest flow from the faucet at all times
will likely cause the water to overflow, or you will pull

Power path enables the most battery capacity with athe cup away from the faucet before you’ve used all ofhigher-accuracy ITERM. In a lithium-ion (Li-ion) charging

the cup’s capacity. Translating back into battery charger

profile, the charge current tapers down during theterminology, reducing the charge current (water fromconstant voltage phase until it reaches ITERM and thenthe faucet) to a controlled, measurable ITERM allows the

shuts off. In order to maximize the battery capacity,

charger to fill the battery (the cup) with as much charge

it is important to have a low ITERM and the ability(water in the cup) as possible, without overcharging or

to accurately measure low ITERM values to precisely

undercharging the battery.

terminate charging. Power path enables accurate current

Optimize your application with a power path battery charger

13

ISSUE 2, 2023

Analog Design Journal

Power

Minimizing battery fatigue

TI power path battery chargers

When a rechargeable battery is exposed to multiple

Linear chargers such as the BQ25180 are useful incharge and discharge cycles, its ability to power

charge current applications <1 A. The BQ25180 comes

the system degrades, which can negatively affect its

equipped with ship mode to provide a low-power mode

performance and run time. In order to maximize theto conserve the battery. In ship mode, the battery

lifetime of both the battery and the system, it is importantquiescent current is only 15 nA, which is significantly

to design the IC to limit the overall cycle count of thelower than the 3-µA battery quiescent current in thebattery.

BQ25180’s normal operation. It is possible to program

Figure 3 shows that the cell capacity of a Li-ion battery

the BQ25180 to have an extremely low ITERM of 0.5
mA, which helps charge the battery to its full capacity.

decreases as the number of recharge cycles increases.

Adjusting the ITERM is simple, as it is a fixed 10% of the

Designing a power path battery-charging IC enables

programmed fast charge current, and easily changeable

you to maximize its lifetime by shutting off the battery

through I2C communication. This charger also prioritizes

FET – powering the system directly from the adapter

system power with supplement mode.

and preventing the system from using the battery for
power eliminates the need to discharge and recharge the

The BQ25620 is a switching buck charger that comesbattery. With power path, you can choose to power theequipped with power path. Switching chargers are

system with only the adapter if the adapter is present,

useful in applications that need a charge current >1

which reduces the number of recharge cycles on theA, since switching chargers are better for higher-power

battery and maximizes its lifetime.

applications. The BQ25620 can support up to 3.5 A
of charge current. It also has ship mode for battery
conservation, with 150 nA of battery quiescent current,
while supplement mode optimizes system performance.
In order to maximize battery capacity, the BQ25620 has
an ITERM as low as 10 mA and can be easily customized
with I2C communication.

Conclusion
There are trade-offs between a power path or a nonpower path battery-charger IC. Battery-charger ICs with

Figure 3. Li-ion cell capacity vs. number of recharge cycles.

power path provide additional functionality with the
integrated battery FET: additional power modes such

Note
Factors that affect cycle-life and possible

as ship mode to conserve the battery, full systemdegradation mechanisms of a Li-Ion cell based

reset capability to recover unresponsive hosts, and theon LiCoO2,” Journal of Power Sources 111

ability to maximize both the battery capacity for longer(2002) 130-136 .

run times and minimize battery fatigue. These typesof charger ICs will help increase battery and system
performance in applications that need simultaneous
charging and system use.

Optimize your application with a power path battery charger

14

ISSUE 2, 2023

Analog Design Journal

Power

Related Websites• For an overview of the differences between linear andswitching chargers, watch the video Introduction toBattery Charger Topologies and Their Applications.
• The video Fast-Charging Trends and Challenges forSingle-Cell Batteries has more details on charger
battery safety features.
• To learn more about ship mode, read the technicalarticle, Pull the Tab: How to Implement Ship Mode inYour Lithium-Ion Battery Design.

Important Notice: The products and services of Texas Instruments Incorporated and its subsidiaries described herein are sold subject to TI’s standard
terms and conditions of sale. Customers are advised to obtain the most current and complete information about TI products and services before
placing orders. TI assumes no liability for applications assistance, customer’s applications or product designs, software performance, or infringementof patents. The publication of information regarding any other company’s products or services does not constitute TI’s approval, warranty or
endorsement thereof.
All trademarks are the property of their respective owners.
© 2023 Texas Instruments Incorporated

SLYT842Analog Design Journal

Powering precision ADCs: Average
versus transient current
Luke Allen
Applications Engineer
Bryan Lizon
Applications Manager
current that scales relative to the data rate or increased

Introduction

current demand when enabling internal features such

Understanding the analog-to-digital converter (ADC)

as programmable gain amplifiers (PGAs) or voltage

data-sheet power-supply parameters can help you

references (VREFs). As an example, Table 1 shows

design more reliable precision data acquisition (DAQ)

the data-sheet power-supply specifications at different

systems. Specifically, it is important to understandoperating conditions for TI’s ADS1261, a 24-bit, 40-

that current consumption in an ADC data sheet is

kSPS, 11-channel delta-sigma ADC with an integrated

an average value specified at steady-state operating

PGA and VREF.

conditions. These measured current values therefore do

Power Supply

not characterize transient current demand, even though
Parameter

ADC transient currents can be orders of magnitude

IAVVD,
IAVSS

larger than the specified ADC current. Transient currents
can occur when transitioning between different ADC

TYP

MAX

Unit

PGA Bypass

2.7

4.5

mA

PGA mode,
gain = 1 to 32

3.8

6

PGA mode,
gain = 64 or
128

4.3

6.5

Power-down
mode

2

8

Analogsupplycurrent (byfunction)

Voltagereference

0.2

40-kSPS mode

0.5

Current
sourcesAs
programmed

Digitalsupplycurrent

20 SPS

0.4

0.65

40 kSPS

0.6

0.85

Power-down
mode

30

50

µA

Power
dissipation

PGA mode

20

32

mW

Power-down
mode

0.1

0.2

Analogsupplycurrent

modes of operation and are most significant when
initially powering the device. Moreover, the circuitry andcomponents surrounding the ADC can cause additionaltransient current demand.

IAVVD,
IAVSS

This article delves into the topic of ADC transient current
demand by first introducing how a typical ADC data
sheet specifies current, and then sharing the resultsof several tests that quantify transient current demand

IDVDD

under different operating conditions. Multiple powersupply configurations that can source both average andtransient currents are discussed, and finally the effects ofPDvarious power-down methods are compared.

Power-supply specifications

Test
Conditions

MIN

µA
mA

mA

Table 1. The data-sheet power-supply specifications for the
ADS1261.

Current consumption in an ADC data sheet is an averagevalue specified at steady-state operating conditions.
An ADC with many different operating conditions
requires the specification of several current values.
These conditions can include an average ADC supply

Powering precision ADCs: Average versus transient current

17

ISSUE 2, 2023

Analog Design Journal
The highlighted PGA Bypass section in Table 1
shows that the average analog current drawn by
the ADS1261 during normal operation with the PGA
bypassed is 2.7 mA (typical) or 4.5 mA (maximum). The
highlighted “by function” section indicates how much thecurrent increases when enabling each function. All ofthese supply-current specifications are characterized bymeasuring the average current drawn by the device after
the current settles.
Data-sheet power-supply specifications therefore
average out any transient current demand that the

Figure 1. Transient current test circuit using the ADS1261 EVM.

device or supporting circuitry requires during normal
operation. This is important because transient currents

The first transient current test was a power-up test

during startup and switching can be significantly larger

with the recommended 10-µF (C23) and 0.1-µF (C24)than the values specified in the data sheet. A reliable

decoupling capacitors from AVDD to ground installed.

system design must be able to account for both average

Figure 2 shows the ADS1261 transient current under

and transient current demand.

these conditions.

Transient currents
One challenge with transient currents is that theirmagnitude and duration can vary significantly as aresult of the ADC operating conditions and surrounding
circuitry. ADC data sheets therefore rarely specify
transient currents. However, it is possible to measuretransient currents for a given system configurationby probing with an oscilloscope across a small-value

Figure 2. Measured transient current at power up withresistor placed in series with the power-supply trace.

decoupling capacitors installed.

You can then use Ohm’s law to determine the resulting

Recall from the ADS1261 power-supply specifications incurrent.

Table 1 that the average current with the PGA disabled

The ADS1261 has an evaluation module (EVM) thatis 2.7 mA (typical) or 4.5 mA (maximum). However, theincorporates such a resistor between the power-supply

blue arrow in Figure 2 points to a 250-mA transient spike

output and the ADC AVDD pin. Figure 1 shows thethat occurs when the ADS1261 is initially powered. This

relevant portion of the EVM schematic that includes atransient is >90 times the typical current and >55 times

10-Ω measurement resistor (R33). Measuring the average

the maximum current specified in the data sheet. Similar

or transient voltage drop across this resistor and thencurrent spikes can occur when the ADC undergoes any

dividing by 10 Ω calculates the average or transientchange in state.

current drawn by the ADS1261, respectively. I performed
multiple tests under a variety of conditions to better
understand the transient current behavior of this ADC.

Powering precision ADCs: Average versus transient current

18

ISSUE 2, 2023

Analog Design Journal
The green arrow in Figure 2 identifies a second transient

I performed a third set of tests to verify that different

current required to charge up the decoupling capacitors.

functions can also cause transient current spikes.

Under normal operating conditions, the decoupling

Enabling the ADS1261 VREF was one such function thatcapacitors store supplemental charge to provide extra

produced a spike. Figure 4 shows the observed behavior

current when transients occur. This extra charge helpsof this transient current.

maintain a steady supply voltage such that ADC
operation remains unaffected. The capacitors must be
charged up to the supply voltage from an uncharged
state when the system is powered, however. Unpowered
capacitors behave like a short at the instant the system
powers up, resulting in a large inrush current. The
magnitude of the inrush current increases as the valueof the decoupling capacitor increases.
Figure 4. Measured transient current with the ADS1261 VREF

To measure only the transient current that the ADC

enabled.

requires, the second transient current test removed therecommended 10- and 0.1-µF decoupling capacitors

Recall from Table 1 that the typical ADS1261 VREF

from AVDD to ground in Figure 1. Figure 3 shows thecurrent is 0.2 mA. Operating the ADC with the PGA

ADS1261 transient current under these conditions.

disabled (2.7 mA) and the internal VREF enabled should
yield 2.9 mA of total current. However, the 60-mA
measured transient current in Figure 4 is >20 times the
expected value. This transient largely results from theinrush current required to charge a filtering capacitor
placed between the VREF output pin and ground.
One interesting characteristic of Figure 4 is thatthe current demand remains constant at 60 mA for
essentially the entire transient pulse. This behavior

Figure 3. Measured transient current at power up withresults from an inherent current limit designed into thedecoupling capacitors removed.

ADS1261 internal VREF, which helps protect the ADC in

The 45-mA transient spike in Figure 1 represents only

case the REFOUT pin shorts to ground.

the power-up current required by the ADC attributable

I performed some additional function tests that did not

to switching. As expected, the ADC-only transient isshow any measurable transient current, although I did

smaller compared to the 250-mA spike that occurred

not test all operating conditions. Also, I should note thatwhen the decoupling capacitors were installed. However,this behavior is not limited to the ADS1261; it is possible

this reduced transient magnitude comes at the cost of

to observe the transient currents documented in thisa significantly longer time for the ADC to reach thearticle with all precision ADCs.

steady-state current because the capacitors no longer
provide any supplemental charge. Additionally, this 45mA transient is still 10 times the maximum ADC current
specification of 4.5 mA listed in Table 1.

Powering precision ADCs: Average versus transient current

19

ISSUE 2, 2023

Analog Design Journalrequires a cathode current of ≥1 mA. These two

Power-supply circuit options

restrictions limit the output-current capabilities of theTransient currents can cause issues such as voltage

standard setup shown in Figure 5 and Figure 6.

droop that may lead to unstable ADC operation.
Therefore, it is important to design power supplies
to accommodate both average and transient current
demand. Review the benefits and challenges of threedifferent power-supply options:• Low dropout regulators (LDOs). TI recommends using
LDOs to power precision ADCs. LDOs offer many
benefits, such as excellent noise performance; low
voltage ripple; and a small, simple implementation.
The most important benefit of an LDO is its ability toreliably maintain the output voltage during transients

Figure 5. Current-limited shunt regulator circuit with positive

output.

while also providing low quiescent current. For more
information on how to select the best LDO for any
application, see Related Website section below.
• Linear regulators. Linear regulators with standard
dropout voltages can also be a good option if
selecting an LDO is cost-prohibitive. Linear regulators
can reliably maintain the output voltage duringtransients while also providing low quiescent current
similar to LDOs. The challenge with linear regulators
is that the dropout voltage is significantly larger, which
can require specific voltage rails just to power thesedevices. Linear regulators also tend to come in larger

Figure 6. Current-limited shunt regulator circuit with negative

output.

packages because they are less efficient and must
dissipate more heat. Additional heat can raise the

Figure 5 and Figure 6 show that both the cathodetemperature of a closed system, which can contributecurrent and the current supplied to the ADC must flow

to drift errors in precision systems.

through resistor R1. This configuration limits the supply• Shunt regulators. One of the most cost-effective

current to (VSUP – VREF) / R1, resulting in two design

power-supply options is a shunt regulator. The costchallenges. First, current flowing continuously through R1

savings come at the expense of the additional

consumes power even with no applied load. Attempting

complexity required to design a reliable power-supply

to reduce R1 to increase the available supply current

circuit. As an example, a precision ADC requiringalso proportionally increases the static power dissipation.

bipolar supply operation might use the TLV431 – aSecond, the maximum current set by R1 generally

low-voltage, adjustable shunt regulator – to generatecannot support the hundreds of milliamperes of transient±2.5-V rails. You can use the TLV431 for this purpose

current that the ADC requires. An inability to provide thebecause it has a low VREF. However, one challengenecessary current causes the supply voltage to droop,with this regulator is that it can supply only a limited

and can lead to unstable ADC operation.

amount of current. The TLV431 data sheet also

Powering precision ADCs: Average versus transient current

20

ISSUE 2, 2023

Analog Design Journal
Mitigate these issues by adding two components to the

Low-power systems: Power down or power
off?

circuit in Figure 5 and Figure 6. Figure 7 and Figure 8
show a modified shunt regulator circuit that includes a

Low-power DAQ systems often conserve energy bytransistor and a bias resistor, Rb.

using different power-down methods. Some ADCs offer
a power-down mode that helps reduce system power
consumption by putting the device in a low-power state
when it is not in use. The ADC data sheet then specifies
the current consumption in this mode. Another popular
power-saving technique is to simply turn off the power
supply when the ADC is not in use and turn the power
supply back on when needed. This method should resultin no power consumption while the system is off.
The latter method is subject to the transient currents

Figure 7. Improved shunt regulator circuit with positive output.

discussed in this article, however, because any
capacitors must recharge every time the supply cycles.
You can estimate how much current the system
consumes when the supply is turned off by using thestandard equations for charge (Q) and current (I), andthen compare this value to the ADC data-sheet value inpower-down mode.
For example, the ADS1261 data sheet recommends 10and 0.1-µF decoupling capacitors in parallel from AVDD
to AVSS. The data sheet also specifies that AVDD mustbe 5 V. Equation 2 and Equation 3 calculate that the

Figure 8. Improved shunt regulator circuit with negative output.

average current is 50.5 µA if the power supply cycles

The power-supply circuit in Figure 7 and Figure 8 canonce per second:

provide more current compared to the system in Figure
Q = C × V = 10.1 μF × 5 V = 50.5 μC

5 and Figure 6 because the transistor eliminates any
resistance between the supply input (VSUP) and output

Q

I= t =(VOUT). This new circuit can also maintain a cathodecurrent of ≥1 mA by installing Rb instead of relying on

2(3)

Recall from the green highlighted section in Table

set the output voltage as per Equation 1.
R

50.5 μC
1 s = 50.5 μA

where, C = 10.1 µF (10 µF + 0.1 µF), V = 5 V and t = 1 s.

R1. Resistors R1 and R2 therefore are only required to

Vout = 1 + R1 × Vref

(2)

1 that the ADS1261 power-down current in powerdown mode is only 8 μA (maximum). Comparing both(1)

options reveals that using the ADC power-down modeconserves >6 times more power relative to turning off

For more information on how to use a voltage reference

the supplies. Therefore, it is important to consider theas a shunt regulator, see Related Website section below.

effect that transient currents can have on overall power
consumption. Choosing to put the ADC in a power-down
state can often be the more energy-efficient solution.

Powering precision ADCs: Average versus transient current

21

ISSUE 2, 2023

Analog Design Journal

Related Website• Download these e-books:– Texas Instruments: LDO Basics– Texas Instruments: Tips and Tricks for Designing with
Voltage References• Check out these TI E2E™ design support forums
technical articles:– How to Choose an LDO or Switching Regulator– How to Use a Voltage Reference as a Voltage
Regulator• Texas Instruments: Understanding Stability Boundary
Conditions Charts in TL431, TL432 Data Sheets• Find an LDO for your next precision ADC design using
the LDO parametric search

Important Notice: The products and services of Texas Instruments Incorporated and its subsidiaries described herein are sold subject to TI’s standard
terms and conditions of sale. Customers are advised to obtain the most current and complete information about TI products and services before
placing orders. TI assumes no liability for applications assistance, customer’s applications or product designs, software performance, or infringementof patents. The publication of information regarding any other company’s products or services does not constitute TI’s approval, warranty or
endorsement thereof.
All trademarks are the property of their respective owners.
© 2023 Texas Instruments Incorporated

SLYT841

SLYT845

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